MT6359 Design Notice (for MT6779) [1.0 ed.]

Citation preview

CONFIDENTIAL B

MT6359 Design Notice (for MT6779)

V1.0 2019/07/31

History Revision V0.1

Date 2018/07/29

Author Ice Initial

V0.2

2018/10/08

Ice

V0.3

2018/11/16

Ice

CONFIDENTIAL B

Description

1. Add VS1/VS2 remote sensing constraint 2. Add BATON differential description 3. Update VSIM1/VSIM2/VIO28/VEMC, VXO22/VRFCK/VBBCK LDO layout constraint 4. Update VA09/VA12/VUSB LDO cap range 5. Update VCN33 default off 3.3V 6. Update power on/off sequence: VPU/XO_SOC/32K 7. Update PCB layout guideline 1. Update power plan with VGPU up to 1.05V, VMCH=3V, MT6360 LDO1/2/3/7 current. 2. Update “Power ON/OFF Sequence” with MT6360 power domain and VBBCK /VRFCK. 3. Add “VAUX18 Behavior in Power-off Mode” 4. Update more description about “Power Domain for I/O” 5. Update in “Layout Constraint of LDO”, “Note: For near-end Cap C1 can be removed if meet above spec.” 6. Update fig in “Controller power trace layout constraint”. 7. Update description about “Chip Placement Recommendation” 1

History Revision

Date

Author

V0.4

2019/01/10

Ice

V0.5

2019/05/15

Ice

V0.6

2019/05/31

Ice

1. Update RTC part, add the description about “How to set 32K driving”

V1.0

2019/07/31

Ice

1. Modify VIBR output voltage range from “1.2V~3.3” to “2.7V to 3.3V”.

CONFIDENTIAL B

Description 1. Add “RTC EOSC Cali Mode VXO22 Power on/off Behavior” 2. Update typo “VAXU18” to “VAUX18” 1. Add “Update Figure for Chip Placement Recommendation” 2. Update VPA Imax=1000mA (align MT6359 datasheet) 3. Update “MT6359 PMIC Part Number Notice”

2

Content ▪ ▪ ▪ ▪ ▪

MT6359 Introduction Function Description Reference Design Function Block Notice PCB Layout Guideline

CONFIDENTIAL B

3

MT6359 – General Description ▪

The MT6359 highly integrated function fulfill all power requirement in smart phone system •

Buck Converters MT6359 x 10 (VPROC1, VPROC2, VGPU11/12, VCORE, VMODEM, VPU, VPA, VS1, VS2)

•

LDOs ▪ Analog LDO ▪ Digital LDO ▪ RTC

•

*6 * 25 *1

Audio ▪ Audio Codec ▪ Audio Line Out

• • •

RTC Macro Fuel Gauge XO Control and Output

CONFIDENTIAL B

4

MT6359 + MT6360 Power Plan

AC Adaptor or USB VBUS

MT6359

MT6360

MT6360 VSYS

Charger

Current Sinks

VPA

R/G/B LEDs

Buck

ON

4.8A 0.4V ~ 1.19V

BATFET

USB Type-C

VBA T

VPROC1 4.8A 0.4V ~ 1.19V

TypeC/PD

Battery Pack

Camera Flash Current Driver

3G/LTE PA

DVDD18_DIG

CPU Little

2.8V, 2mA

VPU 2.4A 0.4V ~ 1.19V

VMODEM 4.8A 0.4V ~ 1.10V

VCORE

ON

1.8V, 10mA

VRTC VPROC2

LDO

OFF

1A 0.5V ~ 3.6V

ON

ON

Peripherals

CPU Big

VPU

Audio DL

0.55V ~ 0.85V VAUD18

ON

1.8V, 300mA

ON

MODEM 0.55V ~ 0.9V

ON

SoC 0.55V ~ 0.85V

VCAMIO

OFF

1.8V, 300mA

VCN18 VRF18

GPU 0.55V ~ 1.05V

VEFUSE

ON

VM18

2A 2.0V

ON

VCN13

ON

IO, RFE MIPI

OFF ON

VSRAM_PROC2

ON

ON ON ON

0.5V~1.29V 600m A

VSRAM_MD

ON

0.5V~1.29V 600m A

ON

MDLA 0.55V ~ 0.85V

VA09

VDRAM 1 3A

ON

0.9V, 300mA

VBBCK 1.2V, 40mA

CONFIDENTIAL B

MSDC1 (SD Card)

OFF

SD CARD

ON

OFF

OFF

RFFE

ON

USB 2.0 Audio

VAUX18

ON

AUXADC

1.84V, 50mA

VXO22

ON

DCXO

2.24V, 50mA

eM MC Vibrator

ON

RF Clock Buffer

1.6V, 25mA

VCAMAF_EXT

OFF

Camera AF

SIM1

SIM2

OFF

Finger Print

OFF

To uch Panel

1.8V, 150mA

VTP

VUSB

VRFCK OFF

1.86V, 200mA

VFP

OFF

3.07V, 200mA

VCAMA EXT1/2/3

LCD BL Driver

DDR

MT6186 RF

0.5V~1.29V 600m A

VSRAM_OTHERS

0.3V ~ 1.3V

OFF

1.86V, 200mA

VSIM2

VFE28

OFF

Camera AVDD

OFF

UFS/MMC

OFF

0.5V~1.29V 600m A

3A

IO & Sensor

1.8V, 200mA

MT6635 (WCN)

1.2V, 300mA

VSRAM_PROC1

VSIM1

Battery temp. sensor

eFuse

OFF

1.2V, 800mA

VA12

VIBR

OFF

2.8V, 50mA

LCM ON

1.3V, 350mA

VRF12

Camera IO

MT6186 RF

1.8V, 300m A

1.35V

VMDLA

OFF

2.8V, 200mA

OFF

1.8V, 300mA

VUFS

Audio UL

MT6635 (WCN)

1.8V, 600mA

VEMC

VBIF28 MT6635 (WCN)

2.8V, 200mA

3V, 800mA

OFF

1.8V, 1200mA

VIO18

ON

4.8A

2A

OFF

3V, 800mA

ON

0.40V ~ 1.19V

VS2 External Power

OFF

3V, 200mA

VMCH

0.40V ~ 1.19V

VS1 Camera Power Display Power

VCN33_2

VMC

1.86V, 1200mA

System Power

3.5V, 800mA

0.6V ~ 1.12V

VGPU12

WCN Power

RTC

VIO28

1.8V, 450mA

RF Power

VCN33_1

2.8V, 200mA

VGPU11 4.8A

3.5V, 800mA

0.6V ~ 1.12V

4.8A 0.4V ~ 1.19V

Memory/ storage

PMIC DIG

ON

LCD +/- Bias

OFF

ABB

VCAMD EXT1/2/3

OFF

VMDDR

ON

Camera DVDD

CPU-B SRAM

CPU-L SRAM

SoC SRAM

MD SRAM

SSUSB, UFS BB Clock Buffer

0.75V, 300mA

VDRAM 2 0.6V, 600mA

DDRPHY

ON LPDDR4x

5

MT6359 Buck Power Plan Circuit Type

Name VPROC1 VPROC2 VGPU11/12 VCORE VMODEM

Buck

VPU VS1 VS2 VPA

CONFIDENTIAL B

Output Voltage Range (V) 0.40 ~ 1.19 (6.25mV/step) 0.40 ~ 1.19 (6.25mV/step) 0.40 ~ 1.19 (6.25mV/step) 0.40 ~ 1.19 (6.25mV/step) 0.40 ~ 1.10 (6.25mV/step) 0.40 ~ 1.19 (6.25mV/step) 1.86 ~ 2.20 (12.5mV/step) 1.20 ~ 1.60 (12.5mV/step) 0.50 ~ 3.60 (50mV/step)

Boot Default (V)

IOUT-MAX (mA)

ON (0.80)

4800

ON (0.80)

4800

ON (0.55)

4800 *2

ON (0.80)

4800

ON (0.85)

4800

ON (0.55)

2400

ON (2.0)

2000

ON (1.35)

2000

OFF

1000

6

MT6359 LDO Power Plan (1/4) Circuit Type

Name

Output Voltage (V)

Boot Default (V)

IOUT-MAX (mA)

Expected use

VFE28

2.80

OFF (2.8)

200

RFFE

VUSB

3.07

ON (3.07)

200

USB

VAUX18

1.84

ON (1.84)

50

AUXADC

VXO22

2.24

ON (2.24)

50

DCXO

VRFCK

1.60

ON (1.6)

25

DCXO

VBIF28

2.80

OFF (2.8)

50

Battery Interface

VRTC

VRTC

2.80

ON (2.8)

2

RTC

VDIG

DVDD18_DIG

1.80

ON (1.8)

10

PMIC Digital

ALDO

CONFIDENTIAL B

7

MT6359 LDO Power Plan (2/4) Circuit Type

Name VSIM1 VSIM2

DLDO

Output Voltage (V)

1.7/1.8/1.86/ 2.76/3.0/3.1 1.7/1.8/1.86/ 2.76/3.0/3.1

Boot Default (V)

IOUT-MAX (mA)

Expected use

OFF (1.86)

200

SIM

OFF (1.86)

200

SIM

VCN33_1

3.3/3.4/3.5/3.6

OFF (3.3)

800

Connectivity

VCN33_2

3.3/3.4/3.5/3.6

OFF (3.3)

800

Connectivity

VEMC

2.9/3.0/3.3

ON (3.0)

800

eMMC / UFS

VIO28

2.8/2.9/3.0/ 3.1/3.2/3.3

OFF (2.8)

200

IO & Sensor

VIBR

2.7/2.8/3/3.3

OFF (2.8)

200

Vibrator

CONFIDENTIAL B

8

MT6359 LDO Power Plan (3/4) Circuit Type

Name

Output Voltage (V)

Boot Default (V)

IOUT-MAX (mA)

Expected use

VEFUSE

1.80

OFF (1.8)

300

EFUSE

VAUD18

1.80

ON (1.8)

300

Audio

VCAMIO

1.80

OFF (1.8)

300

Camera IO

VM18

1.80

ON (1.8)

300

DRAM

VRF18

1.80

OFF (1.8)

450

RF

VIO18

1.80

ON (1.8)

600

IO & Sensor

VCN18

1.80

OFF (1.8)

1200

Connectivity

VUFS

1.86

ON (1.86)

1200

eMMC / UFS

SLDO1

CONFIDENTIAL B

9

MT6359 LDO Power Plan (4/4) Circuit Type

SLDO2

Name

Output Voltage (V)

Boot Default (V)

IOUT-MAX (mA)

Expected use

VBBCK

1.2

ON (1.2)

40

DCXO

VA09

0.9

ON (0.9)

300

AP Analog Module

VA12

1.2

ON (1.2)

300

AP Analog Module

VCN13

1.3

OFF (1.3)

350

Connectivity

ON (0.9)

600

SRAM

ON (0.9)

600

SRAM

ON (0.9)

600

SRAM

ON (0.9)

600

SRAM

OFF (1.2)

800

RF

VSRAM_PROC1 VSRAM_PROC2 VSRAM_OTHERS VSRAM_MD VRF12

CONFIDENTIAL B

0.50 ~ 1.29 (6.25mV/step) 0.50 ~ 1.29 (6.25mV/step) 0.50 ~ 1.29 (6.25mV/step) 0.50 ~ 1.29 (6.25mV/step) 1.2

10

Feature List Function

MT6356

MT6358

MT6359

Buck Converter

6

9

10

LDO

31

28

31

Driver

ERM Vibrator *1

ERM Vibrator *1

ERM Vibrator *1

Audio

Audio Codec

Audio Codec

Audio Codec

Others

RTC macro

RTC macro SD_DET

RTC macro

Charger

Fuel Gauge

Fuel Gauge

Fuel Gauge

CONFIDENTIAL B

11

Content ▪ ▪ ▪ ▪ ▪

MT6359 Introduction Function Description Reference Design Function Block Notice PCB Layout Guideline

CONFIDENTIAL B

12

Power ON/OFF Sequence

by Pressing PWRKEY or Charger Plug In/Out VSYS

VSYS

DDLO

DDLO

UVLO

UVLO

delay time = 33ms

delay time = 141ms

CHRDETB

CHRDETB delay time = 42ms

delay time = 35ms

PWRKEY PWRHOLD (SW RG)

PWRKEY PWRHOLD (SW RG)

HT shutdown level (default 60⁰C)

• Release flow ▪ DCAP disable is auto reset when charger plug out

※ DCAP enable flow need follow programming guide setting CONFIDENTIAL B

23

O_off to VBAT > UVLO_on

SPAR Flow Chart PMIC exception: 1.no power on source 2.UVLO 3.BUCK OC 4.Power not good 5.Thermal shutdown 6.WDTRSTB 7.Long Press shutdown

PMIC exception occurs PMIC RSTB=0

PMIC Off state

Power on condition

SW bring up => PWRHOLD =1 => Clear SPAR power on condition

PMIC exception occurs PMIC RSTB=0

No Check SPAR function

Yes PMIC exception occurs PMIC RSTB=0

NO CONFIDENTIAL B

PMIC exception is UVLO && VBAT drop time < 0.1s/0.6s/1.6s/always on

YES

SPAR power on source set to High, keep all SPAR related RG setting

24

SPAR ▪ Feature support condition • VRTC output need coin cell or keep-alive capacitor

▪ Enabled by software • Three time settings can be selected ▪ ▪ ▪ ▪

100ms, VRTC output need coin cell or >2.2uF capacitor 0.6s, VRTC output need coin cell or >4.7uF capacitor 1.6s , VRTC output need coin cell or >22uF capacitor Min SPAR trigger condition: “duration of (VSYS 1ms VBAT

0.1/0.6/1.6sec

VRTC UVLO PWRKEY PWRHOLD

SPAR de-bounce

PWRON

RESETB CONFIDENTIAL B

25

FSOURCE, PMU_TESTMODE ▪

FSOURCE, PMU_TESTMODE • These pins should be connected to ground for normal operation.

CONFIDENTIAL B

26

Power Domain for I/O MT6359 Pin Name PWRKEY HOMEKEY RESETB CHRDETB EXT_PMIC_EN1 EXT_PMIC_EN2 EXT_PMIC_PG WDTRSTB_IN SRCLKEN_IN0 SRCLKEN_IN1 SPI_CSN SPI_CLK SPI_MOSI SPI_MISO

CONFIDENTIAL B

Power Source Ball Name DVDD18_DIG DVDD18_IO VIO18 VSYS_SMPS VSYS_SMPS VSYS_SMPS VSYS_SMPS DVDD18_IORT (SoC) DVDD18_IORT (SoC) DVDD18_IORT (SoC) DVDD18_IORT (SoC) DVDD18_IORT (SoC) DVDD18_IORT (SoC) DVDD18_IORT (SoC)

Power Source Domain DVDD18_DIG VIO18 VIO18 VSYS VSYS VSYS VSYS VIO18 VIO18 VIO18 VIO18 VIO18 VIO18 VIO18

Power Source Voltage 1.8V 1.8V 1.8V 3.1V ~ 5.0V 3.1V ~ 5.0V 3.1V ~ 5.0V 3.1V ~ 5.0V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V

27

Content ▪ ▪ ▪ ▪ ▪

MT6359 Introduction Function Description Reference Design Function Block Notice PCB Layout Guideline

CONFIDENTIAL B

28

BAT_ON

CONFIDENTIAL B

29

Block Diagram for Smart Battery 3-PIN Smart Battery Smart battery

VBAT

VBATXXX

SPI

▪

BAT Presence Detection

BIF

BATON

MIPI BIF Module

RNTC

Secondary Slave

BIF

Secondary Slave

C3

BCL

CPU

R4

Secondary Slave

BIF

Battery cell

BIF

VBIF28

Primary Slave

AP

PMIC

SRCLKEN_IN

GND

KEY FEATURES • MIPI BIF Smart Battery • HW Battery Pack Presence / Removal Detection

CONFIDENTIAL B

30

HW Battery Presence Detection ▪ Battery presence is detected by sensing the existence of RNTC or RID resistor inside the battery pack. ▪ Dedicated comparator is used for Battery Pack Presence/ Removal Detection. • Battery pack is considered not present if BAT_ON is above 0.964*VBIF. • Interrupts are generated when detecting battery insertion or removal • Charging shall be stopped upon battery removal Parameter

Min

Typ

Max

Units

Presence Detection comparator threshold

(0.964*VBIF)-20mV

0.964*VBIF

(0.964*VBIF)+20mV

V

CONFIDENTIAL B

31

BATON: Schematics & Layout Notice Smart battery

VBAT

VBATXXX

SPI BAT Presence Detection

BIF

BATON

MIPI BIF Module

RNTC

Secondary Slave

BIF

Secondary Slave

C3

BCL

CPU

R4

Secondary Slave

BIF

Battery cell

BIF

VBIF28

Primary Slave

AP

PMIC

SRCLKEN_IN

GND

C3: VBIF bypass cap (1uF)

R4: pull high resistor

 VBIF need bypass cap 1uF  BATON trace total capacitance : • should be smaller than 50pF with Smart battery • should be smaller than 500pF with Low cost battery CONFIDENTIAL B

RNTC: Thermistor (IN pack side)

32

R4/RNTC Selection Guide R4 // RNTC < 40KΩ Voltage of BATON pin should follow BIF Spec.

CONFIDENTIAL B

Copyright © MediaTek Inc. All rights reserved.

2019/8/5

33

Note 1: Recommended Location of NTC in Battery Pack ▪ Recommended location of NTC in battery pack • Move NTC thermistor away from P+ and P• Mount NTC thermistor to the side of PCB toward the cell 10K 1% NTC

P-

CONFIDENTIAL B

P+

34

34

Note 2: Confirm to Meet the above Specifications ▪ Violation of the above specifications will result in measurement error of battery’s temperature.

Battery will be under dangerous environment.

CONFIDENTIAL B

35

35

Safety Protection @ High Temperature ▪ Disable charger in auto power on (DCAP) condition when high temperature • Enable flow ▪ Set DCAP enable by SW when charger in and BAT temp > HT shutdown level (default 60⁰C)

• Release flow ▪ DCAP disable is auto reset when charger plug out ※ DCAP enable flow need follow programming guide setting CONFIDENTIAL B

36

Content ▪ ▪ ▪ ▪ ▪

MT6359 Introduction Function Description Reference Design Function Block Notice PCB Layout Guideline

CONFIDENTIAL B

37

Fuel Gauge

CONFIDENTIAL B

38

Fuel Gauge: Schematics & Layout Notice ▪

1 : Sense resistor Rfg should be 10mΩ±1% ,0.5W↑(depend on system max power consumption 7A-> 0.5W, 10A -> 1W) package in series with battery negative terminal to ground • •

▪ ▪

System max power consumption < 10A, Rfg is 10mΩ System max power consumption > 10A, Rfg is 5mΩ

2：Rfg should be placed near battery connector in PCB layout. 3：FGP_IC/FGN_IC should be 4mil differential traces from chip CS_N/CS_P to Rfg

MT6359

CONFIDENTIAL B

39

FGN_IC, FGP_IC: Layout Example 4mil 4mil

FGP is connected to system GND. It needs adequate amount of VIAs to system GND in order to withstand system current consumption.

FGP

FGN

FGN is connected to BATTERY GND. It needs adequate trace width to BATTERY GND In order to withstand the system current consumption

Rfg Please note that sense traces should be connected to the middle of the pads and the layout should be symmetry between FGN and FGP(Kelvin Connection).

Rfg

FGP_IC CONFIDENTIAL B

FGN_IC 40

GM3.0 Board Offset Calibration Test Point (Option)

TP1 & TP2 for system power supply ——The test point should on the main trace ，as it is used for power input point

TP2 & TP3 for GM3.0 calibration ——The test point should on the main trace ，or the width of trace to test point should not less than 40 mil as the current would be 1000mA ——The test point DO NOT draw from the trace of CS_N &CS_P

TP3 Rfg TP2

TP1 TP2

TP3

TP2

Rfg For GM3.0 For Power Supply CONFIDENTIAL B

The TP3 is on the trace between CS_N Pad to Battery GND

41

Layout Example ▪ TP should be placed on main power trace, not on current sensing trace. Current Sensing Resistor

Main Power Trace (O)

Current Sensing Trace (X) CONFIDENTIAL B

42

DC-DC

CONFIDENTIAL B

43

Buck: Schematic/Layout Notice

InputDecoupling Placement and Schematic Guide ▪

Please place CIN as close to PMIC as possible and put in shield case.

▪

GND_VBUCKs x balls(as highlight in following fig.) must connect to related input cap first, and then connect to main GND plane.

CONFIDENTIAL B

44

Buck: Schematic/Layout Notice

Output Decoupling Placement and Schematic Guide ▪

Place power inductors as closer to PMIC balls as possible and put in shield case.

▪

VBUCK_FB & GND_VBUCK_FB layout should follow PCB layout constraint.

CONFIDENTIAL B

Schematic/Layout Notice

Buck Converter Output Decoupling #1 BUCK

Output Decoupling

VS1

1uH/2016

(22uF/0603 *2) ~ (22uF/0603 *2 + 10uF/0603 *1)

VS2

1uH/2016

(22uF/0603 *2) ~ (22uF/0603 *2 + 10uF/0603 *1)

VPA

1uH/2016

1uF + 14uF

VMODEM

0.47uH/2016

(22uF/0603 *2) ~ (22uF/0603 *2 + 10uF/0603 *1)

VPROC1

0.47uH/2520

(22uF/0603 *4) ~ (22uF/0603 *4 + 10uF/0603 *2)

VPROC2

0.47uH/2520

(22uF/0603 *4) ~ (22uF/0603 *4 + 10uF/0603 *2)

VCORE

0.47uH/2520

(22uF/0603 *2) ~ (22uF/0603 *2 + 10uF/0603 *1)

VGPU11

0.47uH/2016

(22uF/0603 *2) ~ (22uF/0603 *2 + 10uF/0603 *1)

VGPU12

0.47uH/2016

(22uF/0603 *2) ~ (22uF/0603 *2 + 10uF/0603 *1)

VPU

0.47uH/2016

(22uF/0603 *2) ~ (22uF/0603 *2 + 10uF/0603 *1)

Note1: for VPA out cap distribution, please refer “VPA Output Capacitance Notice” CONFIDENTIAL B

Schematic/Layout Notice

Buck Converter Output Decoupling #2 Buck

COUT (typical value)

PDN Cap (typical value)

Total COUT Value (after derating)

VS1

22uF/0603/6.3V/X5R *2

x

≥ 16.6uF

#2

VS2

22uF/0603/6.3V/X5R *2

x

≥ 19.6uF

#3

VMODEM

22uF/0603/6.3V/X5R *2

1uF/0201/6.3V/X5R *12

≥ 20.6uF

#1

VPROC1

22uF/0603/6.3V/X5R *4

1uF/0201/6.3V/X5R *10

≥ 41.2uF

#1

VPROC2

22uF/0603/6.3V/X5R *4

1uF/0201/6.3V/X5R *8

≥ 41.2uF

#1

VCORE

22uF/0603/6.3V/X5R *2

1uF/0201/6.3V/X5R *12

≥ 20.6uF

#1

VGPU11 + VGPU12

22uF/0603/6.3V/X5R *4

1uF/0201/6.3V/X5R *10

≥ 41.2uF

#1

VPU

22uF/0603/6.3V/X5R *2

1uF/0201/6.3V/X5R *8

≥ 20.6uF

#1

Note #1: Total COUT Value @ 1V derating for AC 0.01Vrms and overall operating temperature. Note #2: Total COUT Value @ 2V for AC 0.01Vrms and overall operating temperature. Note #3: Total COUT Value @ 1.35V derating for AC 0.01Vrms and overall operating temperature.

CONFIDENTIAL B

Schematic/Layout Notice Buck Converter Input Decoupling #1

BUCK VS2

Input Capacitor Typical Vale 4.7uF/0402/6.3V/X5R

Total CIN Value (after derating) ≥ 0.84uF #1

VPA

10uF/0402/6.3V/X5R

≥ 1.7uF #1

VMODEM

10uF/0402/6.3V/X5R

≥ 1.7uF #1

VPU

10uF/0402/6.3V/X5R

≥ 1.7uF #1

VPROC1

10uF/0402/6.3V/X5R

≥ 1.7uF #1

VPROC2

10uF/0402/6.3V/X5R

≥ 1.7uF #1

VGPU11

10uF/0402/6.3V/X5R

≥ 1.7uF #1

VGPU12

10uF/0402/6.3V/X5R

≥ 1.7uF #1

VCORE

10uF/0402/6.3V/X5R

≥ 1.7uF #1

VS1

4.7uF/0402/6.3V/X5R

≥ 0.84uF #1

Note #1: Total CIN Value @ 5V derating for AC 0.01Vrms and overall operating temperature. L_PWR1

VSYS

PMIC VSYS_BUCK

CIN 1

CONFIDENTIAL B

GND_BUCK L_GND1

ND1

Schematic/Layout Notice Buck Converter Input Decoupling #2 BUCK VS2

CIN2 (typical value) 10uF/0603/6.3V/X5R #1

CIN1 (typical value) 2.2uF/0201/6.3V/X5R #3

VPA

x

10uF/0402/6.3V/X5R

VMODEM VPU VPROC1 VPROC2 VGPU11 VGPU12 VCORE VS1

22uF/0603/6.3V/X5R

#2

22uF/0603/6.3V/X5R

#2

22uF/0603/6.3V/X5R

#2

22uF/0603/6.3V/X5R

#2

2.2uF/0201/6.3V/X5R #3 2.2uF/0201/6.3V/X5R #3 2.2uF/0201/6.3V/X5R #3 2.2uF/0201/6.3V/X5R #3 2.2uF/0201/6.3V/X5R #3 2.2uF/0201/6.3V/X5R #3 2.2uF/0201/6.3V/X5R #3 2.2uF/0201/6.3V/X5R #3

Note #1: Total CIN2 (10uF) Value ≥ 1.6uF @ 5V derating for AC 0.01Vrms and overall operating temperature. Note #2: Total CIN2 (22uF) Value ≥ 3.6uF @ 5V derating for AC 0.01Vrms and overall operating temperature. Note #3: Total CIN1 (2.2uF) Value ≥ 0.36uF @ 5V derating for AC 0.01Vrms and overall operating temperature. L_PWR2

VSYS

PMIC VSYS_BUCK

CIN 2

CONFIDENTIAL B

L_PWR1

CIN 1

GND_BUCK

Schematic/Layout Notice Buck Input Cap. Layout Spec. #1

▪ If CIN1=0402 size ▪ MMD spec  The spec. of trace parasitic inductance from buck input cap to PMIC Ball Input Trace MT6359 Spec. for Inductance BUCK (from C to IC ball) ▪ (L_PWR1 + L_GND1) < Spec VSYS_VS1 IN1

VS1

L_PWR1

VSYS

PMIC

GND_BUCK L_GND1

CONFIDENTIAL B

GND_VPU

(L_PWR1 + L_GND1) < 2nH

VS2

VSYS_VS2 GND_VS2

(L_PWR1 + L_GND1) < 2nH

VPA

VSYS_VPA GND_VPA

(L_PWR1 + L_GND1) < 1.5nH

VMODEM

VSYS_VMODEM GND_VMODEM

(L_PWR1 + L_GND1) < 1nH

VPROC1

VSYS_VPROC1 GND_VPROC1

(L_PWR1 + L_GND1) < 1nH

VPROC2

VSYS_VPROC2 GND_VPROC2

(L_PWR1 + L_GND1) < 1nH

VCORE

VSYS_VCORE GND_VCORE

(L_PWR1 + L_GND1) < 1nH

VGPU11

VSYS_VGPU11 GND_VGPU11

(L_PWR1 + L_GND1) < 1nH

VGPU12

VSYS_VGPU12 GND_VGPU12

(L_PWR1 + L_GND1) < 1nH

VSYS_BUCK CIN 1

GND_VS1

VPU

VSYS_VPU

(L_PWR1 + L_GND1) < 2nH

Schematic/Layout Notice Buck Input Cap. Layout Spec. #2

▪ If CIN1=2.2uF/0201 ▪ MMD spec => the spec of trace parasitic inductance from CIN2 to CIN1 ▪ (L_PWR2 + L_GND2) < Spec

Buck

Input Trace (from CIN2 to CIN1)

Spec. for Inductance

VSYS_BUCKx

VS2

CIN2 to CIN1

(L_PWR2 + L_GND2) < 1.7nH

CIN2 to CIN1

(L_PWR2 + L_GND2) < 1.7nH

GND_BUCKx

VMDEM VPU

VPROC1 VPROC2

CIN2 to CIN1

(L_PWR2 + L_GND2) < 1.4nH

VGPU11 VPGU12

CIN2 to CIN1

(L_PWR2 + L_GND2) < 1.4nH

VCORE VS1

CIN2 to CIN1

(L_PWR2 + L_GND2) < 1.7nH

PMIC VSYS

L_PWR2

L_PWR1

CIN 1

L_GND2

L_GND1

L_PWR2

L_PWR1

CIN 2

VSYS_BUCKy CIN 1

GND_BUCKy L_GND2

L_GND1

CONFIDENTIAL B

Schematic/Layout Notice Layout Guide (1/2)

▪

Inductance need to follow application notice that has components selection guide.

▪

Placement, layout and schematic need to follow checklist.

Buck input cap detail layout rule, please refer to next page. CONFIDENTIAL B

Schematic/Layout Notice Layout Guide (2/2)

▪

Inductance need to follow application notice that has components selection guide.

▪

Placement, layout and schematic need to follow checklist.

Example 1 PMIC Buck GND ball

Example 2

Input Cap GND pad

PMIC Buck GND ball

Layer-1

Input Cap GND pad

Layer-1 GND return path

Layer-2

Layer-2 Solution 2

Solution 1

GND return path

Layer-3

Layer-3

Layer-5

Layer-5

Main-GND Layer

Main-GND Layer

CONFIDENTIAL B

Solution 2

Solution 1

Schematic/Layout Notice

Controller power trace layout constraint Bat. connector

Buck Input

GND

BAT_BUS

22uF

4mil

Buck controller power trace(VSYS_SMPS) must be use single trace connect to battery VBAT_BUS directly, and can’t merge with others. VSYS add 1Ω Resistor to VSYS_SMPS CONFIDENTIAL B

54

Schematic/Layout Notice

Layout Guide 1/5: Remote Sense Application ▪

DC/DC remote sense feedback traces are recommended using GND shielding to avoid noise coupled.

CONFIDENTIAL B

Schematic/Layout Notice

Layout Guide 2/5: Remote Sense Application ▪

DC/DC remote sense feedback & feedback_GND traces are recommended using GND shielding and differential pair to avoid noise coupled.

CONFIDENTIAL B

Copyright © MediaTek Inc. All rights reserved.

2019/8/5

56

Schematic/Layout Notice

Layout Guide 3/5: Remote Sense Application Cout1

Rc1

L1

L4

Remote pt.1

Cout2

R_remote spec (Follow MMD SPEC)

Lout

Rc2

PMIC L3

SOC

L2 Cout3

Rc3 1. 2.

Find path with lowest inductance, the remote point can be located within Coutlowest L + 1n. For example, in case of Cout1 is path with lowest inductance. • Inductance between Cout1 and Remote pt. 1 is L4, L4 must be lower than 1n (L4 < 1n). • The remote point location can be between Cout1 and Remote pt. 1. 3. Same case apply to L2 & L3 if they are lowest inductance path. 4. Above case is for multi-path, in case of single path, consider the only path as the lowest inductance path directly. CONFIDENTIAL B

Schematic/Layout Notice

Layout Guide 4/5: Remote Sense Application VOUT_FB GND_FB LX

Domain B.

+

PDN Cap.

SOC

Plane

A.

Bulk Cap. SMT Layer

Main GND

A. For GND/VOUT of PDN/Bulk cap. pads, please tie together through Plane before connected to Main GND (L8/L9 if SMT in L10, L6/L7 if SMT in L8) B. GND_FB/VOUT_FB (Fully differentially connected) trace routes directly to PDN cap. pads through short-pad at the layer PDN cap. placed, which also satisfies “Remote Sense Application Notice : Layout Guide (3)” CONFIDENTIAL B

Bucks

Schematic/Layout Notice

Layout Guide 5/5: Remote Sense Application VS1 Remote Sensing to VS1_LDO2 ball internally VS2 Remote Sensing to VS2_LDO2 ball internally Power Inductor VSYS

VSYS_VSx

VSx

COUT

PMIC ESL

ESR VSx_LDOn

CONFIDENTIAL B

Buck

LDO input ball (Direct-Sense to)

Max. ESR (mΩ)

Max. ESL (nH)

VS1

VS1_LDO2

25

4

VS2

VS2_LDO2

25

4

Schematic/Layout Notice

Buck Converter Input/Output Layout Trace Width ▪

Place Input cap, output inductor & cap. as close AP as possible

Input net name

Trace Width (mils)

Output net name

Trace Width (mils)

VSYS_VS1

50

VS1

50

VSYS_VS2

35

VS2

50

VSYS_VMODEM

48

VMODEM

105

VSYS_VPA

60

VPA

60

VSYS_VPROC1

60

VPROC1

125

VSYS_VPROC2

60

VPROC2

125

VSYS_VCORE

60

VCORE

100

VSYS_VGPU1 VSYS_VGPU2

40 40

VGPU1 VGPU2

70 70

VSYS_VPU

25

VSYS_VPU

55

CONFIDENTIAL B

Critical Component Selection Guide Power Inductor #1

•

Inductors are recommended to follow below notice. 1. Rate current of the inductor should be follow bellow table: (Inductance change within ±30% from nominal value). 2. Although small size and high efficiency are major concerns, the inductor should have low core losses and low DCR (copper wire resistance). Efficiency data in MT6359 datasheet is based on 30mΩ DCR. BUCK

Inductance (uH)

ISAT,MAX (A)

ITEMP, MAX (A)

VS1

1.0

2.6

2.0

VS2

1.0

2.6

2.0

VPA

1.0

4.0

3.4

VMODEM

0.47

4.8

4.2

VPROC1

0.47

5.5

4.8

VPROC2

0.47

5.5

4.8

VCORE

0.47

5.5

4.8

VGPU11

0.47

4.0

3.4

VGPU12

0.47

4.0

3.4

VPU

0.47

2.8

2.2

CONFIDENTIAL B

Note:ISAT: Depends on inductance saturation. ( -30% reduction from Initial L value )

61

Critical Component Selection Guide Power Inductor #2

Example:

L ≥30%

Note: 1. The inductor saturation current with 30% decreasing “must be” higher than PMIC Imax for all operation condition.

CONFIDENTIAL B

Copyright © MediaTek Inc. All rights reserved.

2019/8/5

62

VPA Output Capacitance Notice #1 Why define the output capacitor range •

Capacitor Specification Requirement •

•

Item

Typical Cap (uF)

Effective Min Cap (uF) *1

Effective Max Cap (uF) *2

Rated V (V)

Placement Location

Feedback Cap+ (Middle +PA side Cap)

1 + ~14

4.2

7.0

≥6.3

Feedback Cap Close to PMIC ; Others Close to PAs.

*1 : -30oC~85oC / DC=0.5~3.6V / AC=0.01Vrms *2 : -30oC~85oC / DC=2.5~3.6V / AC=0.01Vrms , the capacitance increased when lower DC

Device side ( recommend ~14uF)

PMIC side(1uF)

PMIC VPA

PMU_VPA

L

Feedback Cap

CONFIDENTIAL B PA side Cap

0R 0R

PA_VCC1 PA_VCC2

PA2

PA1

Middle Cap GND

1.“0R” for VCC1/VCC2 PCB routing star connection of PA 2.Replace “0R” with “PCB short PAD part” to reduce DCR when mass production

C C

Capacitor Topology

C C

▪

The updated is for dimension of capacitor don’t care that accept small than 0603 and only need to follow the absolute effective capacitance shown below table. The electrical performance also be guarantee for the previous capacitance notice. Typical total output capacitance is 1uF (Feedback)+ ~14uF (Middle +PA)

C C

▪

The PA’s transient voltage and timing are more critical ▪ Stability ,ripple and transient voltage drop issue If output capacitor is too small ▪ Stability and dynamic voltage scaling timing issue If output capacitor is too bigger

C

▪

63

VPA Output Capacitance Notice #2 ▪ Part Reference ; •

Reference ; http://ds.murata.co.jp/software/simsurfing/en-us/# Part

Part Number

Rated Voltage(V)

Part Size

1uF

GRM033R60J105MEA2

6.3

0201

10uF

GRM155R60J106ME15

6.3

0402

▪ Example for Capacitors arrangement

10uF/0402; NC/0402

PAs side Cap

1. 1uF/0201 *4 2. ≤100pF/0201 *4

1. 1uF/0201 *4 2. ≤100pF/0201 *4 0R

NC

10uF

1.0uF

0R

Middle Cap

C

0402 Size

L PA(2)

PA_VCC2

Feedback Cap

C

From PMIC

PA_VCC1

H/M PA(1)

200mΩ

Application #3 C3(≦0.5xtypical cap) => Support Multi-application

▪ Notice • Typical cap please refer design notice • DC spec is no included PCB DC drop • Trace width > 6mil

▪ Detail layout constraint please refer per project. CONFIDENTIAL B

75

Layout Constraint of LDO #5

Rough Guidelines-use from CAD Extraction w (mil) 4

w (um) 101.6

h (um) 50

t @ 1/3 oz (um) 12

L (nH) = 4.85 nH ×

len (cm) 1.27

trace inductance (nH) 4.85

trace resistance (mΩ) 198

101.6 um len h × × w 1.27 cm 50um

101.6 um len R (mΩ) = 198 mΩ × × w 1.27 cm

where w = 4mil~40mil

Parameter Dielectrically constant Conductivity CONFIDENTIAL B

Value 4.0 5.8e7 s/m

w = trace width len = trace length t = trace thickness h = dielectric height 76

Layout Constraint of VRTC ▪

VRTC: Application circuit (2 options) ▪

0.1uF

▪

0.1uF + 1.5kΩ + super cap



0.1uF cap MUST and be close to PMIC CONFIDENTIAL B

77

Layout Constraint of VREF ▪

VREF bypass cap as close as possible to PMIC

▪

GND_VREF pin must first connect to capacitor GND pin and then connect to system GND by VIA

▪

VREF cap is 100nF.

CONFIDENTIAL B

78

Layout Constraint of VIO18 ▪ Keep star-connection from PMIC VIO18_PMU to import 1.8V power domain. AP Peripheral PMIC MT6359

AVDD18_xx

VIO18_PMU

DVDD18_xx

Peripheral device I/O

CONFIDENTIAL B

79

Layout Constraint of VUSB Priority1 -The de-coupled cap should be put closed to AVDD30_AUD/ AVSS30_AUD and AVDD18_CODEC / AVSS30_AUD - The trace width should be >10mil - Connecting AVSS30_AUD to the main GND through at least one via - Connecting AVDD30_AUD from pad VUSB directly , then do a star connect from AVDD30_AUD to VUSB_PMU.

CONFIDENTIAL B

2019/8/5

80

AP ANALOG POWER PCB LAYOUT CONSTRAIN

CONFIDENTIAL B

81

AP Analog Power List Voltage

1.8V

PMIC Pin Name

VIO18

AP analog pin name AVDD18_MD, AVDD18_AP, AVDD18_WBG, AVDD18_CPU, AVDD18_PLLGP

AVDD18_USB, AVDD18_SSUSB, AVDD18_UFS, AVDD18_DDR AVDD12_PLLGP, AVDD12_UFS, AVDD12_USB, AVDD12_WBG, AVDD12_DDR

1.2V

VA12

AVDD12_MD, AVDD12_DSI

0.9V

VA09

AVDD09_UFS, AVDD09_SSUSB

3.07V

VUSB

AVDD33_USB

CONFIDENTIAL B

Copyright © MediaTek Inc. All rights reserved.

AVDD12_CSI

8/5/2019

- 82 -

AP Analog Layout Constraint 

AVDD18_xxx layout constraint

Star-connection analog power group, AVDD18_SOC by short-pad on VIO18 cap.  Please be sure to follow “reference design” & “PMIC MMD” 

Follow PMIC MMD PMIC



IR spec.



Total path from PMIC LDO pin to AVDD power pin of AP-site



Target IR < 1%  For each AVDDXX_XXX path  Simulate all power pin currents at the same time CONFIDENTIAL B

Copyright © MediaTek Inc. All rights reserved.

8/5/2019

- 83 -

AP AVDD18_xxx Layout Guideline 1 Group#1: AVDD18_MD, AVDD18_AP, AVDD18_WBG, AVDD18_CPU, AVDD18_PLLGP Group#2: AVDD18_USB, AVDD18_SSUSB, AVDD18_UFS, AVDD18_DDR

Follow PMIC MMD

AVDD18_xxx1

Others …

Cnx

Group#1

AVDD18_xxx2 Cnx

VIO18_PMU

PMIC

AVDD18_xxx3

P1

Cnx

AP

AVDD18_SOC

VIO18 C1

SHORT PAD

AVDD18_xxx4 Cnx

E x ample

AVDD18_xxx5

Group#2

Notice 1. PCB drop voltage ≦ 18mV (PMIC VIO18 ball to AP AVDD18_xxx ball) 2. PCB Length/Width ≦ PCB Ratio

Cnx AVDD18_xxx6

P2

Cnx

A v erage

P CB

P CB

P CB Rat io

P CB

P CB

P CB drop

Widt h

Lengt h

Lengt h/ Widt h

Thic k nes s

Res is t er

v olt age

Trac e

Trac e S t art

Trac e E nd

c urrent

Trac e 1

P MIC V IO18 ball

C1

0. 430A

20mil

200mil

10

0. 3oz

17. 7m

7. 6mV

Trac e 2

C1

P 1/ P 2

0. 090A

20mil

1000mil

50

0. 3oz

88. 7m

8. 0mV

Trac e 3

P 1/ P 2

A P A V DD18_ X X X ball

0. 050A

12mil

320mil

27

0. 3oz

47. 3m

2. 4mV

CONFIDENTIAL B

Copyright © MediaTek Inc. All rights reserved.

8/5/2019

- 84 -

Pass ≦18mV

AP AVDD18_xxx Layout Guideline 2 Follow PMIC MMD AVDD18_xxx1

Others …

Cnx AVDD18_xxx2 Cnx

VIO18_PMU

PMIC

AVDD18_xxx3 Cnx

AP

VIO18 AVDD18_SOC

C1

SHORT PAD

AVDD18_xxx4

P1

Cnx AVDD18_xxx5

Notice 1. PCB drop voltage ≦ 18mV (PMIC VIO18 ball to AP AVDD18_xxx ball) 2. PCB Length/Width ≦ PCB Ratio E x ample

Cnx AVDD18_xxx6 Cnx

A v erage

P CB

P CB

P CB Rat io

P CB

P CB

P CB drop

Widt h

Lengt h

Lengt h/ Widt h

Thic k nes s

Res is t er

v olt age

Trac e

Trac e S t art

Trac e E nd

c urrent

Trac e 1

P MIC V IO18 ball

C1

0. 430A

20mil

200mil

10

0. 3oz

17. 7m

7. 6mV

Trac e 2

C1

P1

0. 180A

40mil

1000mil

25

0. 3oz

44. 3m

8. 0mV

Trac e 3

P1

A P A V DD18_ X X X ball

0. 050A

12mil

320mil

27

0. 3oz

47. 3m

2. 4mV

CONFIDENTIAL B

Copyright © MediaTek Inc. All rights reserved.

8/5/2019

- 85 -

Pass ≦18mV

AP AVDD12_xxx Layout Guideline 1 Group#1: AVDD12_MD, AVDD12_DSI, Group#2: AVDD12_PLLGP, AVDD12_UFS, AVDD12_USB, AVDD12_WBG, AVDD12_DDR

AVDD12_xxx1 Cnx

Group#1

PMIC

AVDD12_xxx2 Cnx P1

Cnx

AVDD12_xxx3

VA12

Group#2

C1

AP P2

AVDD12_xxx4 Cnx AVDD12_xxx5 Cnx

Notice 1. PCB drop voltage ≦ 12mV (PMIC VA12 ball to AP AVDD12_xxx ball) 2. PCB Length/Width ≦ PCB Ratio E x ample

AVDD12_xxx6 Cnx AVDD12_CSI Cnx A v erage

P CB

P CB

P CB Rat io

P CB

P CB

P CB drop

Trac e

Trac e S t art

Trac e E nd

c urrent

Widt h

Lengt h

Lengt h/ Widt h

Thic k nes s

Res is t er

v olt age

Trac e 1

P MIC V A 12 ball

C1

0. 280A

20mil

160mil

8

0. 3oz

14. 2m

4. 0mV

Trac e 2

C1

P 1/ P 2

0. 070A

20mil

900mil

45

0. 3oz

79. 8m

5. 6mV

Trac e 3

P 1/ P 2

A P A V DD12_ X X X ball

0. 055A

12mil

300mil

25

0. 3oz

44. 3m

2. 4mV

Trac e 4

C1

A P A V DD12_ CS I

0. 140A

32mil

1000mil

31

0. 3oz

55. 4m

7. 8mV

CONFIDENTIAL B

Copyright © MediaTek Inc. All rights reserved.

8/5/2019

- 86 -

Pass ≦12mV

AP AVDD12_xxx Layout Guideline 2 AVDD12_xxx1 Cnx AVDD12_xxx2 Cnx

PMIC

Cnx

AVDD12_xxx3

VA12

AP C1

AVDD12_xxx4

P1

Cnx AVDD12_xxx5 Cnx

Notice 1. PCB drop voltage ≦ 12mV (PMIC VA12 ball to AP AVDD12_xxx ball) 2. PCB Length/Width ≦ PCB Ratio E x ample

AVDD12_xxx6 Cnx AVDD12_CSI Cnx A v erage

P CB

P CB

P CB Rat io

P CB

P CB

P CB drop

Trac e

Trac e S t art

Trac e E nd

c urrent

Widt h

Lengt h

Lengt h/ Widt h

Thic k nes s

Res is t er

v olt age

Trac e 1

P MIC V A 12 ball

C1

0. 280A

20mil

160mil

8

0. 3oz

14. 2m

4. 0mV

Trac e 2

C1

P1

0. 140A

40mil

900mil

23

0. 3oz

39. 9m

5. 6mV

Trac e 3

P1

A P A V DD12_ X X X ball

0. 055A

12mil

300mil

25

0. 3oz

44. 3m

2. 4mV

Trac e 4

C1

A P A V DD12_ CS I

0. 140A

32mil

1000mil

31

0. 3oz

55. 4m

7. 8mV

CONFIDENTIAL B

Copyright © MediaTek Inc. All rights reserved.

8/5/2019

- 87 -

Pass ≦12mV

AP AVDD09_xxx Layout Guideline

AVDD09_UFS

Cnx

VA09

Cnx

C1

AP AVDD09_SSUSB

P1

Notice 1. PCB drop voltage ≦ 9mV (VA09 ball to AP AVDD09_xxx ball) 2. PCB Length/Width ≦ PCB Ratio E x ample

A v erage

P CB

P CB

P CB Rat io

P CB

P CB

P CB drop

Widt h

Lengt h

Lengt h/ Widt h

Thic k nes s

Res is t er

v olt age

Trac e

Trac e S t art

Trac e E nd

c urrent

Trac e 1

V A 09 ball

C1

0. 060A

18mil

200mil

11

0. 3oz

19. 7m

1. 2mV

Trac e 2

C1

P1

0. 060A

18mil

1000mil

56

0. 3oz

98. 5m

5. 9mV

Trac e 3

P1

A P A V DD09_ X X X ball

0. 040A

8mil

200mil

25

0. 3oz

44. 3m

1. 8mV

CONFIDENTIAL B

Copyright © MediaTek Inc. All rights reserved.

8/5/2019

- 88 -

Pass ≦9mV

AP AVDD33_USB Layout Guideline AP

PMIC VUSB

AVDD33_USB

Cnx C1

Notice 1. PCB drop voltage ≦ 30mV (PMIC VUSB ball to AP AVDD33_USB ball) 2. PCB Length/Width ≦ PCB Ratio E x ample

A v erage

P CB

P CB

P CB Rat io

P CB

P CB

P CB drop

Widt h

Lengt h

Lengt h/ Widt h

Thic k nes s

Res is t er

v olt age

Trac e

Trac e S t art

Trac e E nd

c urrent

Trac e 1

P MIC V US B ball

C1

0. 050A

8mil

200mil

25

0. 3oz

44. 3m

2. 2mV

Trac e 2

C1

A P A V DD33_ US B ball

0. 050A

8mil

2500mil

313

0. 3oz

554. 3m

27. 7mV

CONFIDENTIAL B

Copyright © MediaTek Inc. All rights reserved.

8/5/2019

Pass ≦30mV - 89 -

SPI

CONFIDENTIAL B

90

Layout Constraint of PMIC SPI ▪ All traces of PMIC SPI bus should be well-shielded by nearby ground traces in the same layer, and surrounded by ground traces in n-1 and n+1 layers, and closed to each others. ▪ All traces of SPI bus should be far away from noisy sources, such as VBUS (plug-in spike), Buck switching node..etc.

▪ The max. length of SPI bus between SOC and MT6359 should be shorter than 6 inches (consider 6 inches = 1ns).

CONFIDENTIAL B

91

RTC

CONFIDENTIAL B

92

Schematics Design Notice

• • •

•

•

•

0.1uF for VRTC is a must. [A] Recommend implementing 10~100uF for VRTC. MTK recommend implement 22uF, Smaller capacity sustains shorter time. Please do not use Gold Cap. because of the time when removed the Main battery precision: +-1.5 sec every 30 sec. [B] For battery un-replaced system design, R8201(1.5K) and C8202(22uF) can be removed for eBOM optimized. [B] RTC32K_CK such as a clock signal, needs well ground shielding and try to minimize via number in PCB design.. [C]

RTC32K_CK trace length must be controlled within 2000mil.

CONFIDENTIAL B

93

How to set 32K driving ▪ Preloader API ▪ Code • Change 2369764

▪ API • void set_32K1V8_0_driving(int select); • only support 4mA/8mA

preloader/platform/mt6785/src/drivers/inc/rtc.h CONFIDENTIAL B

Copyright © MediaTek Inc. All rights reserved.

2019/8/5

94

How to set 32K driving File path: preloader/platform/mt6785/src/drivers/platform.c

Set 32K1V8_0 driving after pmic_init_setting(). To make sure new setting can overwrite default value

CONFIDENTIAL B

Copyright © MediaTek Inc. All rights reserved.

2019/8/5

95

Content ▪ ▪ ▪ ▪ ▪

MT6359 Introduction Function Description Reference Design Function Block Notice PCB Layout Guideline

CONFIDENTIAL B

96

Package Outline of MT6359

CONFIDENTIAL B

97

Ballmap of MT6359 202

1

2

3

4

5

6

7

8

A

NC

VRF12

VS2

VSYS_VS2

VSYS_VPA

VPA

VSYS_VPU

VPU

GND_VMODE VSYS_VMOD VSYS_VPROC VMODEM M EM 2

VPROC2

GND_VPROC VSYS_VPROC VSYS_VPROC A 2 1 1

B

VRF12_S

VA12

VS2

GND_VS2

GND_VPA

VPA

GND_VPU

VPU

GND_VMODE VSYS_VMOD VSYS_VPROC VMODEM M EM 2

VPROC2

GND_VPROC 2

C

VCN13

VS2_LDO2

VA09

VSYS_SMPS

VS2_FB

GND_SMPS

VPA_FB

GND_VPU_F B

D

VSRAM_MD VS2_LDO1

E

AU_V18N

F

FLYN

G

FLYP

VSRAM_PRO VSRAM_othe EXT_PMIC_P EXT_PMIC_E EXT_PMIC_E C1 rs G N2 N1

VSRAM_PRO C2

AVSS18_AUD

RESETB

GND

GND

9

VPU_FB

PWRKEY

10

11

CHRDETB

PMU_TESTM ODE

SPI_CLK

GND

GND

GND

LDO

E

XXX

AUDIO

VSYS_VGPU1 VSYS_VGPU1 F 2 2

XXX

DCXO

SRCLKEN_IN VSYS_VGPU1 VSYS_VGPU1 VGPU11_FB G 1 1 1

XXX

STRUP/PCHR_VREF

H

XXX

AUXADC/ FGADC

RTC32K_1V8 GND_VGPU1 GND_VGPU1 GND_VGPU1 WDTRSTB_IN J _1 1_FB 1 1

XXX

Digital IO

SPI_CSN

GND

SPI_MOSI

AU_HPR

AU_REFN

AUD_NLE_M AUD_DAT_M OSI1 ISO1

GND

GND

GND

FSOURCE

AU_HPL

AUD_DAT_M AUD_CLK_M ISO0 OSI

AU_HSP

AUD_DAT_M AUD_DAT_M OSI0 ISO2

DVSS18_IO

K

AVDD18_CO DEC

HP_EINT

ACCDET

AUD_DAT_M AUD_DAT_M OSI1 OSI2

DVDD18_DIG DVDD18_IO

L

AU_VIN0_P AU_VIN0_N AU_VIN3_N AU_VIN3_P

M

AU_VIN1_P AU_VIN2_P

AU_MICBIAS AU_MICBIAS 1 2

BATADC_P

CS_P

AUXADC_VIN 1

XO_WCN

AVSS_XO_IS AU_VIN1_N AU_VIN2_N AVSS_RFCK AVSS_BBCK O

SPI_MISO

VGPU12

VPROC1_FB

RTC32K_1V8 SRCLKEN_IN _0 0

AVSS18_AUX ADC

VAUX18

VFE28

SCP_VREQ_V AO

VGPU11

VGPU12

VGPU11

GND_VCORE GND_VCORE GND_VCORE K _FB

CS_N

GND_VREF

VREF

VRTC28

VIBR

VSYSSNS

BATON

UVLO_VTH

VIO28

VCAMIO

VAUD18

VEFUSE

VM18

VS1_LDO1

VS1_LDO2

VCORE

VCORE

VS1

VS1

N

VS1_FB

GND_VS1

VSYS_VS1

P

R

XTAL1

AVSS_XO

VRFCK_1

XO_CEL

VBBCK

XO_EXT

VUSB

VSIM1

R

AVSS_XO

XTAL2

VXO22

VRFCK

XO_SOC

XO_NFC

VBIF28

VSIM2

VEMC

VCN33_1

VCN33_2

VUFS

VCN18

VRF18

VIO18

NC

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

CONFIDENTIAL B

L

VCORE_FB VSYS_VCORE VSYS_VCORE M

P

VSYS_LDO2 VSYS_LDO1

B

XXX

GND

AU_HSN

VPROC1

GND_VPROC GND_VGPU1 GND_VGPU1 D 1_FB 2 2

VPROC2_FB

HOMEKEY

GND

AVDD30_AU AVSS30_AUD D

VPROC1

16

BUCK

AUD_NLE_M AUD_SYNC_ OSI0 MOSI

J

15

XXX

AU_LOLN

AVDD18_AU D

14

GND_VPROC GND_VPROC C 1 1

AU_LOLP

AU_MICBIAS 0

13

GND_VMODE GND_VPROC VMODEM_FB M_FB 2_FB

H

N

12

98

Layout: MT6359 Power Input (1/2) VSYS Input 

Routing from 22uF VSYS capacitor uses start topology to connect to each device. 1. Input for BUCK. (Fig. 2) 2. Input for LDO. (Fig. 2)



All the decoupling capacitors should be placed near MT6359. The priority is buck capacitor then decoupling capacitor of LDO. (Fig.1)

Fig. 2

Fig. 1

CONFIDENTIAL B

99

Layout: MT6359 Power Input (2/2)  Layout method of MT6359 power Input for Buck GND

Fig.1

-

Buck GND balls are connected to buck capacitors close to pin with plane or trace (Trace Width > 8mil * N (ball number) + M (ball pitch)). (Fig.1~2)

-

Buck GND balls should be connected to buck capacitors first and isolated from the nearby GND trace and plane then connected to main GND at L3 (Fig.1~2).

Fig.2

MT6359

CONFIDENTIAL B

BUCK GND is isolated from nearby GND trace and plane.

100

Layout: MT6359 Buck Output (1/2) Fig.2 

The buck inductors should be placed near MT6359. (Fig.1)

Fig.1

MT6359

CONFIDENTIAL B

101

Layout: MT6359 Buck Output (2/2) 

Those signals are differential pairs and should be shielded by GND and far away from noise signals (Fig.1 ~ Fig.2). 1. VPROC1_FB/GND_VPROC1_FB 2. VPROC2_FB/GND_VPROC2_FB 3. VCORE_FB/GND_VCORE_FB 4. VPU_FB/GND_VPU_FB Fig. 1 5. VGPU11_FB/GND_VGPU11_FB 6. VMODEM_FB/GND_VMODEM_FB 7. VS1_FB, VS2_FB, VPA_FB

Fig. 2

CONFIDENTIAL B

102

Layout: MT6359 LDO Output (1/2) 

See table. for the suggested LDO output layout.

1. Trace width≧6mil 2. Value and placement of capacitor please refer design notice Ball name VFE28 VAUX18 VBIF28 VCN33_1 VCN33_2 VIO28 VEMC VSIM1 VSIM2 VIBR VUSB VEFUSE VAUD18 VCAMIO VM18 VUFS VCN18 VRF18 VIO18 VCN13 VRF12 VA12 VA09 VSRAM_PROC1 VSRAM_PROC2 VSRAM_OTHERS VSRAM_MD

Imax 200mA 50mA 50mA 800mA 800mA 200mA 800mA 200mA 200mA 200mA 200mA 300mA 300mA 300mA 300mA 1200mA 1200mA 450mA 600mA 350mA 800mA 300mA 300mA 600mA 600mA 600mA 600mA CONFIDENTIAL B

Trace Length 1500mil 1500mil 1500mil 1500mil 1500mil 1500mil 1500mil 1500mil 1500mil 1500mil 1500mil 1000mil 1500mil 1500mil 900mil 1200mil 1500mil 1500mil 1500mil 1500mil 1500mil 1200mil 1200mil 1200mil 1200mil 1200mil 1200mil

Trace Width 6mil 6mil 6mil 25mil 25mil 10mil 25mil 10mil 10mil 6mil 8mil 12mil 12mil 6mil 25mil 25mil 8mil 20mil 20mil 25mil 25mil 20mil 20mil 10mil 10mil 22mil 10mil

Rpcb H=50um, 1/3 oz 400mΩ 400mΩ 400mΩ 100mΩ 100mΩ 240mΩ 100mΩ 240mΩ 240mΩ 400mΩ 300mΩ 135mΩ 200mΩ 400mΩ 60mΩ 80mΩ 300mΩ 120mΩ 120mΩ 100mΩ 100mΩ 100mΩ 100mΩ 190mΩ 190mΩ 90mΩ 190mΩ



Core power/DRAM power/AVDDxx power: 



VRF18/VRF12/VRF12_S: •



Traces should be in inner layer or under shielding case.

VRF12_S: 



Follow MMD/MES

VRF12_S should connect to VRF12 application

Trace width/length can adjust by application Imax

If trace is series 0Ω resister, 0Ω resister is having 0~50mΩ variation. It would be drop voltage.

103

Layout: MT6359 LDO Output (2/2) 

VREF capacitor should be placed near L12/L11 pin.



DVDD18_DIG capacitor should be placed near K10 pin.

MT6359

CONFIDENTIAL B

104

Layout: Others for MT6359 Gauge

CS_P/CS_N (ball: L9/L10) should be routed as differential pairs and far away from noise signals.

MT6359 DCXO_32K

CS_P CS_N

CONFIDENTIAL B

105

MT6359 Audio PCB Layout Guide 

MT6359 Audio PCB Layout Guide Please refer “ MT6779 Design Notice “

CONFIDENTIAL B

106

MT6359 AuxADC/DCXO PCB Layout Guide 

MT6359 AUXADC /DCXO PCB Layout Guide Please refer “ MT6779 Design Notice “

CONFIDENTIAL B

107

Chip Placement Recommendation  Following PCB layout are recommended by MTK for WLCSP (MT6359 / MT6360) 1. Opposite shield frame could not overlap package outline 2. The opposite chip (especially large chip, ex. AP & eMCP) could not overlap package outline 3. If underfill was adopted, the properties were recommended : - CTE-1 < 30 ppm/˚C, Tg > 125 ˚C

CONFIDENTIAL B

Copyright © MediaTek Inc. All rights reserved.

2019/8/5

108

How to Connect for Un-usd Pin Unused Part Interface General Gauge DCXO

Pin Connection if not used EXT_PMIC_ENx Ext chip enable pin Floating HOMEKEY button with default long press function Short to GND HOMEKEY HOMEKEY button without default long press function Floating BATON Battery NTC pin for battery and its temperature sensing Pull-Low 10KΩ to GND BATADC Fuel gauge ADC input pin for monitoring battery voltage VBAT CS_N Fuel gauge ADC input pin GND CS_P Fuel gauge ADC input pin GND XO_NFC 26MHz output to NFC Floating XO_EXT 26MHz output to UFS or others Floating Pin Name

CONFIDENTIAL B

Description

109

APPENDIX

CONFIDENTIAL B

110

MT6359 PMIC Part Number Notice

Platform P/N

MT6799 MT6359P

MT6785 MT6359KP

PMIC P/N

CONFIDENTIAL B

111

Copyright © MediaTek Inc. All rights reserved.