MT6186M RF Design Notice [CS0050-GAL2AC-DGD-V1.02EN ed.]

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© MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.

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Platform_System_RF_MT6186M_RF_Design_Notice

RSD/RF1 2018/08/13 © MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.

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Revision History Revision

Date

Description

V0.1

2018.12.7

1st MT6186M customer design note release

V0.2

2019.01.15

1. Add RX IQ connect constraint 2. Modify MT6186M – Power VRF12/VRF18 PCB Layout Constraint

V0.3

2019.02.15

1. Modify IQ layout guide 2. Modify DCXO LDO layout constraint

V0.4

2019.03.13

1. Modify MT6186M schematic/PCB check list:MT6186M – Clock, put 0 ohm at XO_CEL output

V0.4

2019.03.27

1. Modify MT6186M RX feature

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Topic • Key Change & Improvement • MT6186M vs. MT6186 vs. MT6177 • MT6186M function block

• MT6186M reference circuit • MT6186M RF layout guide • Modem control interface notice

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Key Change & Improvement

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Key Change & Improvement • TOP: –

Support inter-band 2CA

–

Robust package design (FCCSP)

• RX: –

Support P/D 18dB/13dB eLNA

–

Post-SAW filter removal (eLNA case)

–

Support 2G P+D function

–

No external ac-coupled cap at all RX inputs (MT6177 needed)

• TX: –

Support 2G power detection function

–

CIM3 and CIM5 performance improve

–

Harmonics improved to support PA input LC-type MN removal

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External LNA Design Consideration • MT6777/79 platform support external LNA. (13.5dB and 18dB) – Need to use all 13.5dB or 18dB eLNA for one phone product (SW limitation)

• The most benefit to add external LNA is sensitivity boost

• TX leakage signal can be amplified by E-LNA module and lead to TX de-sense at RX port while RX is receiving. – No 2nd SAW requirement – High/Low TX ISO criterion for customer reference.

• Suggest to use High TX ISO at all band DRX path and TDD band PRX path • Suggest to use Low TX ISO at FDD band PRX path

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ELNA Type ELNA Gain = 18 dB

ELNA Gain = 13.5 dB

ELNA Off

ELNA Off

ELNA Always On LowTxISO

ELNA Always On LowTxISO

ELNA Always On HighTxISO

ELNA Always On HighTxISO

ELNA Bypass LowTxISO

ELNA Bypass LowTxISO

ELNA Bypass HighTxISO

ELNA Bypass HighTxISO

*All 18dB eLNA have bypass mode, 18dB eLNA don’t support always on operation

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ELNA setting

Not support 18dB eLNA

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18dB eLNA + HISO / LISO

Suggest to use High TX ISO at all band DRX path and TDD band PRX path Suggest to use Low TX ISO at FDD band PRX path Confidential B

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13.5dB eLNA + HISO / LISO

Suggest to use High TX ISO at all band DRX path and TDD band PRX path Suggest to use Low TX ISO at FDD band PRX path Confidential B

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MT6186M vs. MT6186 vs. MT6177

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MT6186M vs. MT6186 vs. MT6177 • MT6186M, MT6186 and MT6177 main features: MT6177

MT6186

MT6186M

Radio mode

6M(2G/WCDMA/TDSCDMA/FDD-LTE/TDDLTE/C2K)

6M(2G/WCDMA/TDSCDMA/FDD-LTE/TDDLTE/C2K)

6M(2G/WCDMA/TDSCDMA/FDD-LTE/TDDLTE/C2K)

LTE feature

CAT7 2DL CA, 2UL CCA (MT6763T) CAT6 2DL CA (MT6763)

CAT12 3DL CCA/ICA and 256QAM, 2UL CCA/ICA

CAT7 2DL CA and 256QAM, 2UL CCA and 64QAM

4x4 MIMO

Not Support

MHB/UHB/LAA (4x4) + MHB/LB (2x2) or MHB (4x4) + UHB/LAA (2x2)

Not Support

Sawless RX for TDD

2GHB/TDS/LTE B34,B39

Not Support

Not Support

TX port

10 (4LB/3MB/3HB)

TX0: 5 (2LB/2MB/1HB, support 2G) TX1: 4 (2MB/2HBUHB)

TX0: 5 (2LB/2MB/1HB, support 2G)

PRX port

14 (7 Groups)

15 (5LB/8MHB/2UHBLAA)

15 (5LB/8MHB/2UHB)

DRX port

14 (7 Groups)

15 (5LB/8MHB/2UHBLAA)

15 (5LB/8MHB/2UHB)

FDD+TDD CA

Yes

Yes

Yes

3.5GHz band (B42)

Yes

Yes

Yes

600MHz band (B71)

Yes

Yes

Yes

LAA (B46)

No

Yes (DL only)

No

E-LNA BYPASS mode

Yes (13dB)

Yes (18dB/13dB w/o post SAW)

Yes (18dB/13dB w/o post SAW)

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MT6186M Function Block

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Key features:

Transmitter:

•

▪

Full multi-mode RF solution (C2K/GGE/WCDMA/TDSCDMA/LTE/LTE-CA) – Carrier aggregation – Multi-band LTE/WCDMA/TD-SCDMA/GGE/C2K – 64QAM UL/256QAM DL (LTE) – C2K/2G/3G/4G co-banding – RxD support (15 RxD ports, include 2G)

▪

No external ac-coupled cap at all RX inputs (MT6177 needed)

Low supply current & operation directly from dual DC-DC converters Temperature measurement sub-system

LAA/UHB(x2)

RX single-ended input LB(x5)

▪

TX

MHB(x8)

HB/UHB

LB (x2)

MB (x2)

DET input TX0 (wi GSM supported)

From TTG

LB

Driver

TX0

SRX0

RXP0/RXD0

MB

U/HB Driver

TIA

TIA

SRX1

RXP1/RXD1

DET PATH LO

From SRX0

2

PGA

2

PGA

RX

Hybrid direct-conversion (4G/3G/C2K)/low-IF (GGE, DC-HSDPA) receiver • 15+15 RX ports (5LBs, 8MHBs, 2UHB) • 4 RXIF IQ outputs 2 SRX and 1 STX

I-I

• •

Receiver:

Driver

–

Direct conversion (LTE/3G/8-PSK) and DFM for GMSK • Dedicated power detection circuits for power control over specific power range • 5 TX ports (2LB/2MB/1UHB, support 2G+1LB/1MB/1HBUHB)

DRX PRX

put

MT6186M Transceiver RF Overview

Controller DCO

STX-dig 2

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RX single

2

4

STX0 2

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MT6186M Band Support

• Multi-band LTE/WCDMA/TD-SCDMA/GGE/C2K

(Blocks A-F)

Band Reference [3GPP/3GPP2]

Band Name

LTE

WCDMA

1 2 3 4 5 6 7 8 9 11 12 13 14 17 18 19 20 21 25 26 27 28 29 30 32 33 34 38 39 40 41 42 44 48 65 66 67 69 [71] BC0 BC1 BC4 BC6 BC10 BC14 BC15

IMT2100 PCS1900 (Blocks A-F) DCS1800 AWS (AWS-1) A-F CELL850 JCELL800 IMT-E 2600 EGSM950 J1700 Lower-PDC 700 lower A-C 700 upper C 700 upper D 700 lower B-C Japan Lower 800 Japan Upper 800 EU800 (Digital Dividend) Upper-PDC Extended-PCS (A-G) Extended-CELL SMR/E850 APT 700 lower D/E WCS (Blocks A/B) B32 (L-Band) B33 B34 B38 B39 B40 B41 B42 APT-TDD CBRS Extended IMT Extended AWS blocks A-J (AWS-1/AWS-3) EU 700 Supplemental DL B3 600MHz Extended-Cell PCS1900 (Blocks A-F) KPCS IMT2100 Sec. 800 Extended-PCS (Blocks A-G)

yes yes yes yes yes

yes yes yes yes yes yes

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yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes

TDSCMA

GGE

C2K

yes yes yes

yes

yes

yes

yes

yes yes

yes

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yes yes yes yes yes yes yes

16

MT6186M Ball Map • 4.8 x 5.3 FCCSP package with 0.35mm ball pitch to accommodate 8-layer HDI2 PCB stack up. 1

W V

RX_DLB5

RX_DMH B1

RX_DMH B3

D

B

GND RX_DMH B6

RX_DMH B7

A 1

GND GND

RX_DMH B8 2

3

GND GND

RX_PUHB 1 4

5

NC GND

RX_PUHB 2 6

RX_DBBQ 1

RX_DBBQ 2

GND

7

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9

Confidential A

U

MRX RF

MRX BB

VDDH_TX T 0_HF

RX RF

RX BB

TOP

TEST

NC GND

L

J RX_PBBI2 H

RX_PBBQ 2

G NC

NC

NC 11

12

VDDH_T D OP GND

GND NC

13

14

F E

GND

NC

M

RX_PBBI1 K

NC

GND

• RX P/D ports arrangement discussion in next page • VIO18 are not needed. Only VRF18/VRF12.

N

GND

GND

RX_DUHB 2 10

TX BB

RX_PBBQ 1 RX_DBBI 2

EN_BB

VDDL_ST X_HF

GND RX_DUHB 1 8

TX RF

MRX_BBI P

RX_DBBI 1

VDDL_RX _LF

GND

TX0_LB1 V

NC

GND VDDH_RX _HF

NC

GND

NC

FSRCI

CLK26M

GND

VDD

MRX_BB Q

MRX0_RF

BSI_EN

TEST1

GND

TX0_BBQ _M

BSI_CK

GND

RCAL

W

R

GND

BSI_DAT A1

GND

GND

RX_DMH B5

C

GND VDDL_RX SRX1_HF

GND

RX_DMH B4

E

GND

17

GND GND

TX0_BBQ _P GND

TEST2

VDDH_SR X VDDL_SR X_LF

GND RX_DMH B2

G F

VDDL_RX _HF

GND

GND

BSI_DAT A0

GND

16

TX0_LB2

GND

TEST0

GND

15

TX0_BBI_ M

GND

GND

14

TX0_MB1 TX0_HB1

VDDL_TX 0_LF

GND

13

TX0_BBI_ P VDDL_TX 0_HF

GND

GND

GND

12

TX0_MB2 GND

GND

GND

11

GND

GND

VDDL_RX SRX0_HF

GND

10

RX_PLB1

GND

GND

RX_PMH B7

J H

GND

9

RX_PLB2

VDDH_RX SRX

NC

GND

RX_PMH B8

8

RX_PLB3 RX_PLB4

GND

RX_PMH B6

7

GND

RX_PMH B5

L K

6

RX_PLB5 RX_DLB1

GND

RX_PMH B4

5

GND

RX_PMH B3

N M

4

RX_DLB2 RX_DLB3

RX_PMH B2

R P

3

RX_PMH B1

U T

2

RX_DLB4

C NC

NC 15

16

B A

17

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MT6186M RX P/D Ports Grouping Consideration • Comparison: –

MT6177 (P/D two separate grouping): P(LMB/HB/LAAUHB) / D(LMB/HB/LAAUHB).

–

MT6186M (P/D interleaved grouping): UHB D/P, MHB D/P, LB D/P

• MT6177 LMB_P LMB_P HB_P LAAUHB_P

• Pros and Cons:

LMB_D

–

MT6177: On-chip RF/LO routing will be more complicated. And hence with larger current and poorer isolation.

–

MT6186M : Easier on-chip routing and hence better isolation/spur and current. Side-effect: P/D PCB routing crossing might be needed.

HB_D LAAUHB_D HB_D • MT6186M UHB_P

• PCB crossing considerations with different FE module :

UHB_D

–

Phase 2: PCB crossing is necessary due to discrete components are on the same side with RFIC. D might need to go PCB inner layer to cross P. (ex: one routing cross between LB_D and MHB_P if LAA not used)

MHB_D

–

Phase 6L: Concerns in phase 2 can be relieved since P is already on backside (PAMid), D can be on the same side with RF IC.

MHB_P

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LB_D

LB_P 18

MT6186M Receiver Architecture

TX0

• Each band signal can be routed to at least 2 RX paths.

SRX0 RXP0/RXD0

• Minimize CA spurs approach: Spur mitigation flow

Solutions: Arrange floorplan properly / multiple divider option / RX different path selection / define isolation requirement

–

Chip verifications done and matched well.

• PRX/DRX LNAs have been integrated on-chip. Support external LNA to boost sensitivity performance. No post-SAW filter needed. –

iLNA mode RX NF spec: 2.3dB

–

eLNA (18dB) mode RX NF spec: 1.5dB (inc. eLNA)

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LB(x5)

–

DRX PRX

MHB(x8)

A MTK internal complete methodology to check all on/off-chip potential spur mechanism (Ex: VCO/DIV/MIxer coupling, PCB coupling) under all CA cases.

RXP1/RXD1

LAA/UHB(x2)

–

SRX1

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MT6186M RX Port Support Frequency Range RX port

Frequency Range

RX_PLB1~5, RX_DLB1~5

617-960MHz

RX_PMHB1~8, RX_DMHB1~8

1452-2690MHz

RX_PUHB1~2, RX_DUHB1~2

3400-3700MHz

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RX MHB Port Assignment Consideration • Adjacent port suggest not to support CA (to have better isolation). • B1 UL freq=B2 DL freq, B2 UL freq=B3 DL freq. B1/2/3 ports need to be separate. • Due to phase 2/3 HB PA 3P4T isolation problem, B7 to B40/41 need to be separate.

• CA cases have harmonic related coefficient need to be separate. • After considering 1~4, our RX port assignment are listed as below (China Sku). 1 RX_PMH K B8

• Ex: Suggested MHB P path ballmap PRX2 PRX1

PRX4 PRX3

PRX6 PRX5

PRX7

M

1

40

41

7

3

RX_PMH B6 RX_PMH B5

N P

39

RX_PMH B7

L

PRX8

2/M

RX_PMH B4 RX_PMH B3

R

34 T

2

RX_PMH B2

RX_PMH B1 Copyright © MediaTek Inc. All rights reserved U

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MT6186M RX Port Assignment for China global Sku Port RX_PLB1 RX_PLB2 RX_PLB3 RX_PLB4 RX_PLB5 RX_PMHB1 RX_PMHB2 RX_PMHB3 RX_PMHB4 RX_PMHB5 RX_PMHB6 RX_PMHB7 RX_PMHB8 RX_PUHB1 RX_PUHB2 RX_DLB1 RX_DLB2 RX_DLB3 RX_DLB4 RX_DLB5 RX_DMHB1 RX_DMHB2 RX_DMHB3 RX_DMHB4 RX_DMHB5 RX_DMHB6 RX_DMHB7 RX_DMHB8 RX_DUHB1 RX_DUHB2

EU+China+APAC+India B5 (BC0/B26/G850) B8 (G900) B20 B12 (B17) B28 B1 B39 B41 (B38) B40 B3 (G1800) B7 B34/B32 B2 (G1900) B42 B5 (BC0/B26/G850) B8 (G900) B20 B12 (B17) B28 B1 B39 B41 (B38) B40 B3 (G1800) B7 B34/B32 B2 (G1900) B42

 If no L+L CA requirement, LB ports could change. Confidential B

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TX Architecture

HB/UHB

LB (x2)

MB (x2)

DET input TX0 (wi GSM supported)

From TTG

I-I

Driver

LB

Driver

MB

TIA

TIA

Driver

U/HB

DET PATH LO

PGA

From SRX0

2

PGA

2

Controller DCO

STX-dig 2

Confidential B

2

4

STX0 2

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MT6186M TX Ports Assignment

Feature Total Number TX Ports

TX0 5

GSM/EDGE Support

Yes

UHB Support

Yes

Number LB Ports Supported

2 (inc 1 port for GGE)

Number MB Ports Supported

2 (inc 1 port for GGE)

Number HB/UHB Ports Supported

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1

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MT6186M TX Bands Allocation TX port

Band

TX0_LB1

B5,B6,B8,B12,B13,B14,B17,B18, B19,B20,B26,B27,B28,B71

TX0_LB2

GSM LB

TX0_MB1

B1,B2,B3,B4,B9,B10,B11,B21,B25,B34,B39

TX0_MB2

GSM HB

TX0_HB1

B7,B30,B38,B40,B41,B42,B48

 TX allocation must follow above table

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Approach to Minimize TX Spurious • Key TX spurious mechanisms includes: 1. CIM3/CIM5 2. TX Harmonics  1 & 2: had been improved in MT6186M 3. Image Response (SSB) 4. LO (@ TX Port)  3 & 4: can calibrate and compensate within DFE 5. ACLR

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TX Harmonic Improvement • For M/H bands, 3LO-BB is improved about 20dB. For UHB, 3LO-BB is improved about 15dB • PA input LC-type matching has about 15~20dB rejection  MT6186M doesn’t need this filter to provide harmonic rejections

3LO-BB MT6186M MT6177

Band Group

Unit

LB

MB

HB

UHB

-45 -40 Confidential B

-45 -20

-40 -20

-35 dBc -20 dBc Copyright © MediaTek Inc. All rights reserved

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MT6186M Reference Circuit

Confidential B

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RF Design Note: MT6186M schematic/PCB check list Function

Common part

Front end TRX

MT6186M RXRF (with DUP)

MT6186M TXRF (PDET/TMES)

MT6186M Clock MT6186M - IQ

MT6186M – Power

APC & Vbias MT6359 – Power De-sense

Class

Done

Check Items

A

□

Use MTK QVL 26MHz TSX, PAMID, LFEM, DiFEM, Duplexer, SAW, 2G PA , 3G/LTE PA (support R7/R8/R9) , ASM or TXM

A

□

RX SAW filter, duplexer to ASM or TXM needs to reserve T or Pi-matching network and series DC-block capacitor (If ASM or TXM includes DC-block capacitor, it can be removed.)

A A A

□ □ □

Refer to design note about detailed schematic description. ASM/switch/eLNA. Connect its power pin to VFE28 (2.8V) or VRF18 (1.8V), not BPI All BPI traces to ASM or TXM need to reserve shunt cap

A

□

Check the LNA port assignment to follow the reference design and CA combination.

A

□

GSM RX can co-band with WCDMA/LTE to lower BOM cost and layout size, but sensitivity will degrade 1~1.5dB.

A

□

eLNA should use the same gain type for all path. If you use 18dB gain eLNA, all eLNA should be 18dB gain eLNA.

A

□

RX trace to RX SAW or duplexer need to reserve single-ended T or Pi-matching network to do RX matching.

A

□

A

□

MT6186M TX trace to PA need to reserve T or pi-matching network. LTE and WCDMA with closed loop power control need to use coupler to MT6186M detector input. Refer to design note; use wide band coupler with attenuator and let the detector input power ranges at 0~-40dBm.

A

□

MT6186M TX port assignment must follow the reference design. LB2/MB2 supports 2G output. Put 3/4G LB TX on LB1 ,3/4G MB on MB1 and 3/4G HB/UHB on HB1. Put SP2T on TX0_HB1 for B42 and HB support usage.

A

□

LTE/3G PA power can select VCC_PA or VBAT, but it is suggested to use VCC_PA to save power consumption.

B

□

Connect MT6359 CLK buffer output (XO_CEL) to MT6186M CLK26M and reserve 0ohm at XO_CEL output. The 0 ohmt should keep 1 cm away from XTAL.

A

□

26MHz clock trace must have good GND shielding and impedence control between 50~30ohm. 26MHz trace cap loading must be PRXBBI1 RX_PBBQ1 -> PRXBBQ1 RX_PBBI2 -> PRXBBI2 RX_PBBQ2 -> PRXBBQ2

RX_DBBI1 -> DRXBBI1 RX_DBBQ1 -> DRXBBQ1 RX_DBBI2 -> DRXBBI2 RX_DBBQ2 -> DRXBBQ2 Confidential B

Confidential A

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Reference Circuit Schematic: Power of MT6186M VRF18_FE

R3121 2

VRF18_RFIC

1

R / 0 / ohm R3119 2 1

VRF18_PMU

2

 Bypass cap should be put close to MT6186M.  Refer to Layout Guide for the location to place the bypass cap and the method to route power.

1.8V 4.7uF cap close to MT6186M

C3152 C / 4.7 / uF / 6.3V

1

R / 0 / ohm

D_GND

1.2V sensing feedback point and 1.2V 10uF cap close to MT6186M

VRF12_TX R3199 1 R / 0 / ohm

VRF12_SRX

VRF12_PMU

2

2

1

C3151 C / 2.2 / uF / 6.3V

R / 0 / ohm

2

VRF12_RX R3150 2

SH3102 1 2 NC/MMD/L1/4MIL

VRF12_s [21]

1

2

1

R3149

C3153 C / 10 / uF / 6.3V

1 D_GND

D_GND

R / 0 / ohm

Share? Confidential B

Confidential A

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MRX connection • TX0 coupler feedback to MRX0. • MRX input peak power should be lower than 10dBm for 2G and 0dBm for 3/4G. Put 6dB attenuator and resistor close to MT6186M.

Confidential B

Use Daisy chain to let TX0 coupler feedback to MRX0

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Reference Schematic China Single Ant Area China

2G 3G 4G 4G Roaming UL intra-band CA DL intra-band CA 2/3/5/8 1/2/3/5/8 1/3/5(26)/7/8/34/ 4/8/17/20 CCA: 3+3, 38+38, 39+39, /34/39/BC 38/39/40/41 40+40, 41+41 0 New:1+1(CCA)

DL inter-band CA 1+3, 1+5(26), 3+5(26), 39+41,

1. TXM(SKY77927)+LMH PA(SKY77643) 2. Detector Attenuator to 6dB for both SKY and Qorvo Phase3 TXM 3. Reserved Shunt C to 27pF for MIPI CLK and DATA

Confidential B

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LTE B34/B39 to GPS De-sense Solution • B34/39 not TXM reuse case: –

Antenna isolation between GPS and B34/39 + Band-Pass Filter after B34/39 PA > 35dB - Use B39 SAW filter (ex: SAFEA1G90MA0F0A) for B39 only SKU - B34+B39 dual SAW filter (ex: SAWEN1G90PA0F0A) for both B34 and B39 SKU - Use BPF (ex: LFB181G95CT9E362) + antenna isolation 14dB TXM Main Ant

GSM LB GSM HB B34/B39

3G/4G MMPA

Antenna isolation

1. Originally use a LPF and need ANT isolation >35dB to avoid GPS desense 2. Replace to use B39 SAW filter for B39 only SKU

GPS Ant

3. Use B34+B39 dual SAW filter for both B34 and B39 SKU

GPS SAW LNA MT6625L

4. Use B34/39 BPF, and let BPF+ANT ISO >35dB Confidential B

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MT6186M Layout Guide

Confidential B

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38

Common RF Placement Guide 1.

Put Battery CONN close to 2G PA to reduce voltage drop in max. output power.

2.

The Thermistor sensor placement should be close to PA.

3.

(RF trace, Clock) away from high power (PA output), high current (VBAT, VCC_PA), and high speed circuit (Flash/DRAM) region.

4.

Keep PA far away from TRX LNA input trace.

5.

Keep RF matching circuit placement similar to the reference design with good impedance control to save the fine-tuning matching effort.

6.

HB/UHB RX matching components should be close to MT6186M RX port.

7.

The TX port to 3G/4G PA path requires pi-matching circuit for TX power matching.

8.

Make high band RX trace as short as possible.

9.

Make high band TRX trace as short as possible.

10. MT6186M and PA should be placed at different sides or different shielding spaces. 11. For the harmonic CA case, separate the PA shielding space for LB and MHB PA. Confidential B

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39

Common Layout Guide for RF 1.

RX uses 50ohm single-ended trace. Keep enough space between trace-to-trace and trace-to-ground plane.

2.

Keep out the space between the top layer of RX single-ended trace and the ground plane by 3~5 times of L1-L2 thickness.

3.

Keep out the second layer of RF trace, RF component’s PAD and RX single-ended matching area to minimize capacitance and loss.

4.

Susceptible traces (RF, 26MHz, VAPC and PDET) should be covered by GND plane and surrounded by a wall of GND via or GND trace act of a similar coaxial cable.

5.

TX/RX isolation is critical to 3G/4G RX performance. Good isolation depends on good layout.

6.

Keep good isolation between 2G TX output and coupling feedback path.

7.

Keep good isolation between BSI signals and MIPI, BPI control signals.

8.

Remove broken and small ground plane or add GND via to main GND.

9.

In a good board design, drop as many “vias” to ground as possible in the RF circuitry section.

10. MT6186M power balls should connect to bypass caps first. Confidential B

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40

MT6186M Layout Notice (1/5) RX LNA port isolate from RF power balls

Use GND shielding 26M CLK / BSI signals to protect RF power and IQ signals.

Confidential B

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41

MT6186M Layout Notice (2/5)

GND thru-via

XIN

1. CLK26M should go inner layer as soon as possible and close to CLK26M ballpad projection area 2. CLK26M trace must away from VDDL_RX# & VDDL_TX# traces 3. Ground thru-via must close to CLK26M trace and put as many as possible (at lease two) Confidential B

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42

MT6186M Layout Notice (4/5) • BSI VIA should be shielding GND and isolated from VRF12 power ball/VIA.

Confidential B

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43

MT6186M Layout Notice (5/5)

L1 GND trace should cover inner VRF12 Trace and Chip can’t see VRF12_TX power directly VRF12_TX power trace should be routed symmetrically

Confidential B

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44

MT6186M Layout Notice (4/4)

For CA_3A_40A, B3 RX should be route inner layer for B3/B40 isolation.

Confidential B

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45

Common Layout Guide for Power •

The width of VCC_PA trace should be at least 50mils from PMIC to 3G/LTE PA and 30 mil in RF room (The DCR should be less than 70mohm, refer to Figure. 1 in next page).

•

The width of VRF18 trace should be at least 30mils from PMIC to MT6186M and 12 mil in RF room (The DCR should be less than 130mohm, refer to Figure. 2 in next page).

•

The width of VRF12 trace should be at least 40mils from PMIC to MT6186M and 12 mil in RF room (The DCR should be less than 110mohm(A+B), refer to figure. 2 in next page).

•

VBAT should be at least 80mil from battery connector to 2G PA and 50mil in RF room.

•

Give as many vias as possible when switching layers for VCC_PA and VBAT.

•

Good power trace layout should be surrounded by ground plane and via.

•

Do not let power trace be a loop.

•

Do not use a power plane in RF PCB. Loop trace and power plane like an antenna.

•

Use a star topology to reduce coupling between various supply pins in a system.

•

Do not put power trace in top layer without any shielding.

•

Drop through hole GND via surrounding PCB.

•

Ground via reduces current return paths. Drop as many GND vias near battery connector and switching layers as possible.

•

PA VCC2 must keep away RF trace and signal via. Surround VCC2 with GND plane and use GND via to keep distance with RF trace and signal via.

•

Each RF/FE power domain totally output capacitor must meet the capacitor range that descript in PMIC design notice.

•

IQ and 26MHz clock trace must keep away PMIC buck inductor to avoid power noise and de-sense. IQ trace keep all buck inductors >1mm away. 26MHz clock trace keep VPA inductor > 2mm away and keep other buck inductors > 1mm away. Confidential B

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46

VRF PCB Layout Constraint • Power Domain Information and PCB Layout Constraint Power Domain

PMIC DC Accuracy(mV)

RF IC Min. Voltage(V)

Loading Current(A)

PCB Resistance A+B constraint(mΩ)

VRF12

+/- 12

1.18

0.55

A < 120; B < 10

VRF18

+/- 18

1.75

0.21

1mm away to avoid power noise and de-sense. – If the phone only support 2CC intra, A+A, A+C CA case, IQ can layout with 2(I)/4(spacing)/2(Q) constraint. The IQ layout with 2(I)/2(Spacing)/2(GND)/2(Spacing)/2(Q) constraint can obtain the better performance.

– Differential IQ traces (TX IQ) can have more resistance for common mode noise. Single end IQ trace should be more carefully. – For avoid buck inductors, IQ trace can be routed partial with no GND shielding 2(I)/4(spacing)/2(Q). But the trace length must be < 10mm.

1mm Inductor

Confidential B

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52

Layout Guide for co-TMS • Placement Concept –

Keep TMS far away noise source. (Buck, NCP, Class-D… or other toggling signals)

–

This document is for reducing thermal impact for crystal. Please reserve enough area for crystal routing and keep-out region. The clock stability is very important for RF performance.

• Placement –

Keep the crystal and PMIC DCXO area > 10 mm away from the heat sources (i.e., RF and WiFi PAs).

–

Keep the crystal > 10 mm away from 1A charger, and > 20mm from 2A charger.

–

Keep the crystal > 4.4 mm away from PMIC, and > 15 mm away from AP.

–

Keep-out at least the first two inner layers of metal including all crystal circuits.

–

Keep-out all crystal components > 0.25 mm away from the surrounding metal.

–

Do not place the crystal and PMIC DCXO area directly under the heat sources that on the opposite side (i.e., CPU, RF and WiFi PAs).

–

Place the crystal inside the shielding case, and keep > 1 mm away from the PCB edge, and > 20 mm away from USB, headphones, vibrators, etc.

–

Place VXO22, VRFCK, VRFCK_1 capacitor close to ball within 1mm.

Confidential B

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53

DCXO LDO Output Cap • DCXO LDO output cap ground connect to buffer ground. • DCXO LDO output cap is placed near the power ball. – VRFCK/VRFCK_1/VXO22 LDO output cap is placed near the VRFCK/VRFCK_1/VXO22 ball (trace