MT6359 Design Notice (for MT6883, MT6885, MT6889) [0.7 ed.]

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CONFIDENTIAL B

MT6359 Design Notice

V0.7

History Revision

Date 2019/04/01

Author Mark Initial

2019/05/06

Mark

2019/05/30

Mark

V0.1

CONFIDENTIAL B

Description

Page4 Update Power plan Page5 VMODEM buck for VRF09, VPU buck for VDIGRF Page8 VM18 change to default on 1.8V Page9 Change VA09/VSARM PROC1/VSRAM PROC2/VSARM Others/VSRAM MD LDO boot default voltage and application Page44 Change decoupling values Page45 Change Cout and PDN cap values Page58/59 Change trace width and inductor Itemp./Isat. Max. of Buck Page68 Change LDO application of SRAM_LDOs/VA09 Page80/86 Change VSRAM_xPU to SRAM CORE Page106 Add UFS2.5/UFS3.0 Power configuration Page3/4 Change IC’s Part number Page8/9 Update VPA Imax=1000mA(align MT6359 datasheet) and VPU buck Vboot Page 84/90 add VBBCK_PMU to AP AVDD12_CKBUF_UFS constraint Page 48/49 Revise Cout cap range and Capacitance Page72 Adjust VA09 LDO cap range Page112 Add “Update Figure for Chip Placement Recommendation” Page16 Add power on/off sequence 1

History Revision

Date

Author

V0.2

2019/08/01

Mark

V0.3

2019/10/22

CONFIDENTIAL B

the block diagram

Mark

Description Page113 Add IC package layout recommendation Page14 VSRAM_PROC2 boot up voltage change to 0.9V Page 11/14 VRFCK/VBBCK boot up voltage change to 1.24V Page64 VGPU for VCORE inductor Itemp. change to 4.7A Add Notice for inductor selection guide Page73/74/76/77 VCN13/VXO22/VBBCK cap range update Page9 Power plan typo update Page60/62 Update Couts ESL constraint Page 114 Update MT6359PP/B to MT6359VPP/B Page 17 Revise Power on/off sequence and add +/-20% tolerance Page63 Update VDIGRF Trace width

Page5 Update PMIC change comparison table for VXO22/VRFCK/VBBCK Page11/14 Update VXO22/VRFCK/VBBCK IMAX Page12 Update VIBR output voltage setting Page51 Update MT6359P Cin capacitor notice Page103 Add MT6359VPP MES layout constraint Page104 Update VRF18 trace length and Rpcb Page113 Update MT6359VPP for MT6883 platform

2

History Revision

Date

Author

V0.4

2020/01/15

Mark

V0.5

2020/05/08

Mark

Page11/63 Update Vs1 IMAX Page50 Update VPA cap range

V0.6

2020/05/10

Mark

Page50 Update cap range

V0.7

2020/05/20

Mark

Page38 Update R4/RNTC selection notice Page79/96 Update VRTC selection noted

CONFIDENTIAL B

Description Page17 Update some power rail power off sequence from 0.1ms to 0.2ms Page13 Update VEMC setting for 2.5V Page111 BATON Short to GND while RU=NC, Pull-Low 10KΩ to GND while RU exist

3

Content ▪ ▪ ▪ ▪ ▪ ▪

Feature comparison MT6359 Introduction Function Description Reference Design Function Block Notice PCB Layout Guideline

CONFIDENTIAL B

4

Power plan comparison MT6359PP/B Buck (PWRAP)

MT6360PP Buck (I2C) MT6315PP/B Buck (SPMI) MT6315QP/B Buck (SPMI)

MT6315RP/B Buck (SPMI)

PMIC MT6359 ball name Buck VPROC1 VPROC2 VCORE VPU VPA VS1 VS2 VMODEM

P90

Helio 5G

Power-plan

Power-plan

CPU-B CPU-L CORE VPU VPA VS1 VS2 MODEM

APU DLA VRF13 VDIGRF VPA VS1 VS2 VRF09

VGPU11+VGPU12

GPU

CORE

BUCK1 BUCK2 CH1 CH2 CH4 CH3 CH1 CH2 CH4 CH3 CH1 CH2 CH3 CH4

MDLA LP4x_VDD2

LP4x_VDD2 LP4x_VDDQ

MT6691SVP/A MT6691OTP/A

PMIC MT6359 ball name VM18 VCAMIO VAUD18 VA09 VA12 MT6359PP/B VCN13 LDO VSRAM_MD (PWRAP) VSRAM_PROC1 VSRAM_PROC2

CPU-B CPU-L GPU VSRAM_CORE

MT6360PP LDO (I2C)

MODEM NR SRAM_MD VMDDR USB3.0 1.2V MT6680P/A

CONFIDENTIAL B

P90

Helio 5G

Power-plan

Power-plan

LDO LP4x_VDD1 Camera IO Camera IO Audio, 1.8V Audio, 1.8V AP analog 0.9V VSRAM_DIGRF AP analog 1.2V AP analog 1.2V WCN, 1.3V WCN, 1.3V VSRAM_MD VSRAM_APU VSRAM_CPUB VSRAM_CPUB VSRAM_CPUL VSRAM_CPUL

VSRAM_Others

VSRAM_CORE

VSRAM_GPU

VRF12

RF12

AP analog 1.2V

Fingerprint

Fingerprint

Touch panel

Touch panel

AP MSDC

AP MSDC

SD card

SD card

LDO1 (VFP) (150mA) LDO2 (VTP) (200mA) LDO3 (VMC) (200mA) LDO5 (VMCH) (800mA) LDO6 (AP_VMDDR) (300mA) LDO7 (LP4x_VDDQ) (600mA)

VMDDR

VDDQ

VMDDR_EN LP4x_VDD1

PMIC change comparison table PMICs

Ext. Buck/LDO Interface Buck Phase UFS DRAM power MT6359 VCORE buck

P90

Helio 5G

MT6359 (MT6359P/A) MT6360 (MT6360P)

MT6359 (MT6359PP/B) MT6360 (MT6360PP) MT6315*3 (MT6315PP/B, MT6315QP/B, MT6315RP/B)

N/A

MT6691SVP/A (EMI VMDDR) MT6680P/A (VDD1) MT6691OTP/A (UFS3.0 1.2V) (Option)

PWRAP+I2C

PWRAP+I2C+SPMI

12

24

Only support UFS2.1 power

Support UFS2.1/UFS3.0 power

2×16-bit LPDDR4X at 1866 MHz

4x 16-bit LPDDR4X at 2133 MHz

Max voltage up to 1.19V

Max voltage up to 1.3V

MT6359 VA09 LDO

Support min. voltage 0.9V

Support min. voltage 0.85V

MT6359 VRF12 LDO

Default off for RFIC 1.2V power

Default on for AP 1.2V analog power

MT6359 VEMC LDO

No HW trapping

HW trapping 3.0V/2.55V

MT6359 VXO22

IMAX 50mA

IMAX 25mA

MT6359 VRFCK

Default voltage 1.6V, IMAX 40mA

Default voltage 1.24V, IMAX 10mA

IMAX 40mA

IMAX 10mA

MT6359 VBBCK CONFIDENTIAL B

6

PMIC change comparison table P90

Helio 5G

MT6360 HW trapping

RG:000, HW trapping short to VDDA

RG:001, HW trapping short 1.8M to gnd

MT6360 Buck1 IMAX

3A

4A

MT6360 Buck1 inductor (Fsw)

0.33uH (2.4Mhz) for VMDLA

0.24uH (2.72Mhz) for VDD2

MT6360 Buck2 inductor (Fsw)

0.33uH (2.4Mhz) for VDD2

0.47uH (2.4Mhz) for VDDQ

MT6360 LDO6

0.75V for VMDDRPHY

NC

MT6360 LDO7

0.6V for VDDQ

1.8V for VMDDRPHY Enable

N/A

MT6315 for CPU/GPU/MD power

MT6315

CONFIDENTIAL B

7

Content ▪ ▪ ▪ ▪ ▪ ▪

Feature comparison MT6359 Introduction Function Description Reference Design Function Block Notice PCB Layout Guideline

CONFIDENTIAL B

8

MT6359 – General Description ▪

The MT6359 highly integrated function fulfill all power requirement in smart phone system •

Buck Converters MT6359 x 10 (VCORE, APU, DLA, VS1, VS2, RF09, RF13, DIGRF )

•

LDOs ▪ Analog LDO ▪ Digital LDO ▪ RTC

•

*6 * 25 *1

Audio ▪ Audio Codec ▪ Audio Line Out

• • • •

RTC Macro Fuel Gauge XO Control and Output Ext. LDOs/Buck ▪ MT6680 (EMI_VDD1) ▪ MT6691 (EMI_VMDDR)

CONFIDENTIAL B

9

MT6359 + MT6360+MT6315 Power Plan AC Adaptor or USB VBUS

MT6359

MT6315

MT6360

VSYS

MT6360 Current Sinks

USB TypeC

TypeC/ PD

VPA

R/G/B LEDs

OFF

1.0A

Buck

DVDD18_DIG

3G/LTE PA

ON

1.8V, 10mA

0.5V~3.6V

PMIC DIG

VCN33_1 VCN33_2

VPROC1

BATFET

ON

4.8A 0.4V~1.193V

VBAT LDO

VPROC2

APU 0.55V~0.8V

VRTC

ON

0.75V/4.8A

VAUX18

VCORE DLA 0.55~0.725V 0.55V~0.8V

ON

0.7V/2.4A

ON

1.84V, 50mA

VXO22 VPU Battery Pack

ON

2.24V, 50mA

VRFCK

0.9V/4.8A

VRF09

0.4V~1.1V

ON

MT6680

OFF

VAUD18

VRF13

VGPU11

RF Power

4.8A 0.4V~1.19V

VCAMIO ON

WCN Power

OFF

1.8V, 300mA

VCN18

VCORE 0.55~0.725V

VGPU12

ON

1.8V, 300mA

0.4V ~ 1.193V

Memory/ storage

OFF

1.8V,1 200mA

VRF18

4.8A 0.4V~1.19V

ON

1.8V, 600mA

Camera Power Display Power

VEFUSE VS1 2.5A 2.0V

DCXO

OFF

1.8V, 300mA

ON VUFS

ON

1.86V, 1200mA

External Power

VM18

RF Clock Buffer

LDO3

LDO5 VEMC

DDR Audio UL

2.8V, 200mA

VIBR VSIM1 Camera IO

OFF

MT6635/31 (WCN)

VRF18

1.8V, 150mA

IO RFFE MIPI

1.8V, 200mA

eFuse UFS/ MMC

LDO2

MT6359 Buck : 8* 1-PH+1* 2-PH LDO : 30

VS2 2.5A

VRF12

MT6360

OFF

MT6635 (WCN)

ON ON

1.2V, 300mA

VA09

BUCK : 2 LDO : 6

OFF

VBBCK

2.8V, 200mA

VSRAM_PROC2

ON

BB Clock Buffer

ON

CPUB_ SRAM

ON

CPUL_ SRAM

ON

GPU_ SRAM

0.4V~1.193V 600mA

VSRAM_OTHERS

External

0.4V~1.193V 600mA

VSRAM_MD VDRAM2

VDRAM1

RFFE

OFF OFF

OFF

3.07V, 200mA

USB 2.0 Audio

Vibrator SIM1

SIM2

OFF

Finger Print

OFF

Touch Panel

6315-3(MODEM) 2-Phase IP

ON

ON

0.8V/10A

ON VSW

CPU-B

0.75V/15A

0.55V~1.0V

VSW3

ON

0.8V/5A

ON

0.8V/5A

CPU-L 0.55V~0.9V

VSW4 0.85V/5A

ON

MODEM

NR

SRAM_ MD

6315-2 (GPU & SRAM_CORE) 3-Phase IP

ON VSW

GPU

0.75V/15A

0.55V~0.85V

APU_SRAM

LPDDR4x

Buck2 (6360) 0.6V/3A

Buck1 (6360)

0.4V~1.193V 600mA

ON

Battery temp. sensor

eMMC

3-Phase IP

VSW3

0.4V~1.193V 600mA

BUCK: 12-PH

ON

VUSB ON

6315-1(CPU-B & CPU-L)

ABB1 VSRAM_DI GRF

1.2V, 300mA

VSRAM_PROC1

LCM

SD CARD

ABB2

ON

0.9V, 300mA

MT6315*3

BUCK: 2 + BL/LCM LDO: 9 CONFIDENTIAL B

Camera DVDD

1.20V, 800mA

VA12

OFF

VFE28

VSW1~2 OFF

1.3V, 450mA

ON

1.35V

LCM

ON

1/2/3

VCN13

OFF

2.8V, 50mA

MSDC1

1.8V, 200mA

VCAMD

OFF

LCD +/- Bias

Camera AVDD

Sensor

(SD Card)

1.86V, 200mA

LDO1

CAM AF

VBIF28 OFF

1.86V, 200mA

VSIM2

OFF

LCD BL Driver OFF

2.95V, 800mA

3V, 800mA

OFF

1.8V, 450mA

Peripherals

VIO18

System Power

VIO28

OFF

VCAMA Ext. 1/2/3

MT6635 (WCN)

3.3~3.6V, 800mA

2.8V, 200mA

ON

1.8V 1000mA

VCORE 1.3V/4.8A

OFF

3V, 200mA

1.24V, 25mA

OFF

AUXADC

VDIGRF

0.4V ~ 1.193V

VMODEM

RTC

VCAMAF

0.4V ~ 1.193V

Flash Current Driver

ON

2.8V, 2mA

OFF

3.3~3.6V, 800mA

MT6691 0.75V/2A

ON LPDDR4x

DDRPHY VSW3 0.85V/5A

1.125V/4A LDO7 (EN pin)

ON

ON

SRAM CORE 0.75V

10

MT6359 Buck Power Plan Circuit Type

Buck

Buck Name (Application name) VPROC1 (DVDD_APU) VPROC2 (DVDD_DLA) VGPU11/12 (DVDD_CORE) VCORE (VRF13_PMU) VMODEM (VRF09_PMU) VPU (VDIGRF_PMU) VS1 (VS1_PMU) VS2 (VS2_PMU) VPA (VPA_PMU)

CONFIDENTIAL B

Output Voltage Range (V) 0.40 ~ 1.19 (6.25mV/step) 0.40 ~ 1.19 (6.25mV/step) 0.40 ~ 1.19 (6.25mV/step) 0.50 ~ 1.3 (6.25mV/step) 0.40 ~ 1.10 (6.25mV/step) 0.40 ~ 1.19 (6.25mV/step) 1.86 ~ 2.20 (12.5mV/step) 1.20 ~ 1.60 (12.5mV/step) 0.50 ~ 3.60 (50mV/step)

Boot Default (V)

IOUT-MAX (mA)

ON (0.75)

4800

ON (0.75)

4800

ON (0.725)

4800 *2

OFF

4800

OFF

4800

ON (0.7)

2400

ON (2.0)

2200

ON (1.35)

2500

OFF

1000

11

MT6359 LDO Power Plan (1/4) Circuit Type

LDO Name

Output Voltage (V)

Boot Default (V)

IOUT-MAX (mA)

Expected use

VFE28

2.80

OFF (2.8)

200

RFFE

VUSB

3.07

ON (3.07)

200

USB

VAUX18

1.84

ON (1.84)

50

AUXADC

VXO22

2.24

ON (2.24)

25

DCXO

VRFCK

1.24

ON (1.24)

10

DCXO

VBIF28

2.80

OFF (2.8)

50

Battery Interface

VRTC

VRTC

2.80

ON (2.8)

2

RTC

VDIG

DVDD18_DIG

1.80

ON (1.8)

10

PMIC Digital

ALDO

CONFIDENTIAL B

12

MT6359 LDO Power Plan (2/4) Circuit Type

LDO Name VSIM1 VSIM2

DLDO

Output Voltage (V)

1.7/1.8/1.86/ 2.76/3.0/3.1 1.7/1.8/1.86/ 2.76/3.0/3.1

Boot Default (V)

IOUT-MAX (mA)

Expected use

OFF (1.86)

200

SIM

OFF (1.86)

200

SIM

VCN33_1

3.3/3.4/3.5/3.6

OFF (3.3)

800

Connectivity

VCN33_2

3.3/3.4/3.5/3.6

OFF (3.3)

800

Connectivity

VEMC

2.5/2.9/3.0/3.3

ON (3.0)

800

eMMC / UFS

VIO28

2.8/2.9/3.0/ 3.1/3.2/3.3

OFF (2.8)

200

IO & Sensor

VIBR

2.7/2.8/3/3.3

OFF (2.8)

200

Vibrator

CONFIDENTIAL B

13

MT6359 LDO Power Plan (3/4) Circuit Type

LDO Name

Output Voltage (V)

Boot Default (V)

IOUT-MAX (mA)

Expected use

VEFUSE

1.80

OFF (1.8)

300

EFUSE

VAUD18

1.80

ON (1.8)

300

Audio

VCAMIO

1.80

OFF (1.8)

300

Camera IO

VM18

1.80

ON (1.8)

300

NA

VRF18

1.80

OFF (1.8)

450

RF

VIO18

1.80

ON (1.8)

600

IO & Sensor

VCN18

1.80

OFF (1.8)

1200

Connectivity

VUFS

1.86

ON (1.86)

1200

eMMC / UFS

SLDO1

CONFIDENTIAL B

14

MT6359 LDO Power Plan (4/4) Circuit Type

SLDO2

LDO Name

Output Voltage (V)

Boot Default (V)

IOUT-MAX (mA)

Expected use

VBBCK

1.2

ON (1.2)

10

DCXO

VA09

0.85

ON (0.85)

300

DIGRF SRAM (VRF0P85_MEM_PMU)

VA12

1.2

ON (1.2)

300

AP Analog Module

VCN13

1.3

OFF (1.3)

350

Connectivity

ON (0.85)

600

CPUB SRAM

ON (0.9)

600

CPUL SRAM

ON (0.85)

600

GPU SARM

ON (0.85)

600

APU SRAM

ON (1.2)

800

AP Analog Module

VSRAM_PROC1 VSRAM_PROC2 VSRAM_OTHERS VSRAM_MD VRF12

CONFIDENTIAL B

0.50 ~ 1.29 (6.25mV/step) 0.50 ~ 1.29 (6.25mV/step) 0.50 ~ 1.29 (6.25mV/step) 0.50 ~ 1.29 (6.25mV/step) 1.2

15

Feature List Function

MT6356

MT6358

MT6359

Buck Converter

6

9

10

LDO

31

28

31

Driver

ERM Vibrator *1

ERM Vibrator *1

ERM Vibrator *1

Audio

Audio Codec

Audio Codec

Audio Codec

Others

RTC macro

RTC macro SD_DET

RTC macro

Fuel Gauge

Fuel Gauge

Fuel Gauge

Fuel Gauge

CONFIDENTIAL B

16

Content ▪ ▪ ▪ ▪ ▪

MT6359 Introduction Function Description Reference Design Function Block Notice PCB Layout Guideline

CONFIDENTIAL B

17

Power ON/OFF Sequence

by Pressing PWRKEY or Charger Plug In/Out VSYS

VSYS

DDLO

DDLO

UVLO

UVLO

delay time = 33ms

delay time = 141ms

CHRDETB

CHRDETB delay time = 42ms

delay time = 35ms

PWRKEY PWRHOLD (SW RG)

PWRKEY PWRHOLD (SW RG)

Clear SPAR power on condition

PMIC exception occurs PMIC RSTB=0

No Check SPAR function

Yes PMIC exception occurs PMIC RSTB=0

NO CONFIDENTIAL B

PMIC exception is UVLO && VBAT drop time < 0.1s/0.6s/1.6s/always on

YES

SPAR power on source set to High, keep all SPAR related RG setting

29

SPAR ▪ Feature support condition • VRTC output need coin cell or keep-alive capacitor

▪ Enabled by software • Three time settings can be selected ▪ ▪ ▪ ▪

100ms, VRTC output need coin cell or >2.2uF capacitor 0.6s, VRTC output need coin cell or >4.7uF capacitor 1.6s , VRTC output need coin cell or >22uF capacitor Min SPAR trigger condition: “duration of (VSYS 1ms VBAT

0.1/0.6/1.6sec

VRTC UVLO PWRKEY PWRHOLD

SPAR de-bounce

PWRON

RESETB CONFIDENTIAL B

30

FSOURCE, PMU_TESTMODE ▪

FSOURCE, PMU_TESTMODE • These pins should be connected to ground for normal operation.

PMIC PMU_TESTMODE FSOURCE

CONFIDENTIAL B

31

Power Domain for I/O MT6359 Pin Name PWRKEY HOMEKEY RESETB CHRDETB EXT_PMIC_EN1 EXT_PMIC_EN2 EXT_PMIC_PG WDTRSTB_IN SRCLKEN_IN0 SRCLKEN_IN1 SPI_CSN SPI_CLK SPI_MOSI SPI_MISO

CONFIDENTIAL B

Power Source Ball Name DVDD18_DIG DVDD18_IO VIO18 VSYS_SMPS VSYS_SMPS VSYS_SMPS VSYS_SMPS DVDD18_IORT (SoC) DVDD18_IORT (SoC) DVDD18_IORT (SoC) DVDD18_IORT (SoC) DVDD18_IORT (SoC) DVDD18_IORT (SoC) DVDD18_IORT (SoC)

Power Source Domain DVDD18_DIG VIO18 VIO18 VSYS VSYS VSYS VSYS VIO18 VIO18 VIO18 VIO18 VIO18 VIO18 VIO18

Power Source Voltage 1.8V 1.8V 1.8V 3.1V ~ 5.0V 3.1V ~ 5.0V 3.1V ~ 5.0V 3.1V ~ 5.0V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V

32

Content ▪ ▪ ▪ ▪ ▪ ▪

Feature comparison MT6359 Introduction Function Description Reference Design Function Block Notice PCB Layout Guideline

CONFIDENTIAL B

33

BAT_ON

CONFIDENTIAL B

34

Block Diagram for Smart Battery 3-PIN Smart Battery Smart battery

VBAT

VBATXXX

SPI

▪

BAT Presence Detection

BIF

BATON

MIPI BIF Module

RNTC

Secondary Slave

BIF

Secondary Slave

C3

BCL

CPU

R4

Secondary Slave

BIF

Battery cell

BIF

VBIF28

Primary Slave

AP

PMIC

SRCLKEN_IN

GND

KEY FEATURES • MIPI BIF Smart Battery • HW Battery Pack Presence / Removal Detection

CONFIDENTIAL B

35

HW Battery Presence Detection ▪ Battery presence is detected by sensing the existence of RNTC or RID resistor inside the battery pack. ▪ Dedicated comparator is used for Battery Pack Presence/ Removal Detection. • Battery pack is considered not present if BAT_ON is above 0.964*VBIF. • Interrupts are generated when detecting battery insertion or removal • Charging shall be stopped upon battery removal Parameter

Min

Typ

Max

Units

Presence Detection comparator threshold

(0.964*VBIF)-20mV

0.964*VBIF

(0.964*VBIF)+20mV

V

CONFIDENTIAL B

36

BATON: Schematics & Layout Notice Smart battery

VBAT

VBATXXX

SPI BAT Presence Detection

BIF

BATON

MIPI BIF Module

RNTC

Secondary Slave

BIF

Secondary Slave

C3

BCL

CPU

R4

Secondary Slave

BIF

Battery cell

BIF

VBIF28

Primary Slave

AP

PMIC

SRCLKEN_IN

GND

C3: VBIF bypass cap (1uF)

R4: pull high resistor

 VBIF need bypass cap 1uF  BATON trace total capacitance : • should be smaller than 50pF with Smart battery • should be smaller than 500pF with Low cost battery CONFIDENTIAL B

RNTC: Thermistor (IN pack side)

37

R4/RNTC Selection Guide • Should Limit selection of R4 // RNTC < 40KΩ for getting more stable voltage after ADC settled • BATON noted that VOH should over 1.1V once using BIF battery

Voltage of BATON pin should follow BIF Spec.

CONFIDENTIAL B

Copyright © MediaTek Inc. All rights reserved.

2020/5/25

38

Note 1: Recommended Location of NTC in Battery Pack ▪ Recommended location of NTC in battery pack • Move NTC thermistor away from P+ and P• Mount NTC thermistor to the side of PCB toward the cell 10K 1% NTC

P-

CONFIDENTIAL B

P+

39

39

Note 2: Confirm to Meet the above Specifications ▪ Violation of the above specifications will result in measurement error of battery’s temperature.

Battery will be under dangerous environment.

CONFIDENTIAL B

40

40

Content ▪ ▪ ▪ ▪ ▪ ▪

Feature comparison MT6359 Introduction Function Description Reference Design Function Block Notice PCB Layout Guideline

CONFIDENTIAL B

41

Fuel Gauge

CONFIDENTIAL B

42

Fuel Gauge: Schematics & Layout Notice ▪

1 : Sense resistor Rfg should be ±1% ,0.5W↑(depend on system max power consumption 7A-> 0.5W, 10A -> 1W) package in series with battery negative terminal to ground • •

▪ ▪

System max power consumption < 10A, Rfg is 10mΩ System max power consumption > 10A, Rfg is 5mΩ

2：Rfg should be placed near battery connector in PCB layout. 3：FGP_IC/FGN_IC should be 4mil differential traces from chip CS_N/CS_P to Rfg

MT6359

CONFIDENTIAL B

43

FGN_IC, FGP_IC: Layout Example 4mil 4mil

FGP is connected to system GND. It needs adequate amount of VIAs to system GND in order to withstand system current consumption.

FGP

FGN

FGN is connected to BATTERY GND. It needs adequate trace width to BATTERY GND In order to withstand the system current consumption

Rfg Please note that sense traces should be connected to the middle of the pads and the layout should be symmetry between FGN and FGP(Kelvin Connection).

Rfg

FGP_IC CONFIDENTIAL B

FGN_IC 44

GM3.0 Board Offset Calibration Test Point (Option)

TP1 & TP2 for system power supply ——The test point should on the main trace ，as it is used for power input point

TP2 & TP3 for GM3.0 calibration ——The test point should on the main trace ，or the width of trace to test point should not less than 40 mil as the current would be 1000mA ——The test point DO NOT draw from the trace of CS_N &CS_P

TP3 Rfg TP2

TP1 TP2

TP3

TP2

Rfg For GM3.0 For Power Supply CONFIDENTIAL B

The TP3 is on the trace between CS_N Pad to Battery GND

45

Layout Example ▪ TP should be placed on main power trace, not on current sensing trace. Current Sensing Resistor

Main Power Trace (O)

Current Sensing Trace (X) CONFIDENTIAL B

46

DC-DC

CONFIDENTIAL B

47

Buck: Schematic/Layout Notice

InputDecoupling Placement and Schematic Guide ▪

Please place CIN as close to PMIC as possible and put in shield case.

▪

GND_VBUCKs x balls(as highlight in following fig.) must connect to related input cap first, and then connect to main GND plane.

CONFIDENTIAL B

48

Buck: Schematic/Layout Notice

Output Decoupling Placement and Schematic Guide ▪

Place power inductors as closer to PMIC balls as possible and put in shield case.

▪

VBUCK_FB & GND_VBUCK_FB layout should follow PCB layout constraint.

CONFIDENTIAL B

Schematic/Layout Notice

Buck Converter Output Decoupling #1 BUCK

Application

Inductor

Total COUT Range

VS1

VS1

1uH/2016

(22uF*2) ~ (47uF + 10uF)

VS2

VS2

1uH/2016

(22uF*2) ~ (47uF + 10uF)

VPA

VPA

1uH/2016

Follow VPA notice

VMODEM

VRF09

1uH/2016

(22uF) ~ (22uF+10uF)

VPROC1

APU

0.24uH/1608

(22uF*3) ~ (47uF + 22uF + 10uF)

VPROC2

DLA

0.24uH/1608

(22uF*3) ~ (47uF + 22uF + 10uF)

VCORE

VRF13

1uH/2016

(22uF) ~ (22uF+10uF)

VGPU11 VGPU12 VPU

VCORE VDIGRF

0.24uH/2016 0.24uH/2016 1uH/2016

(22uF*5) ~ (47uF*2+22uF*1 + 10uF) (22uF) ~ (22uF+10uF)

Note1: for VPA out cap distribution, please refer “VPA Output Capacitance Notice”

CONFIDENTIAL B

Schematic/Layout Notice

Buck Converter Output Decoupling #2 Buck

Application

PMIC COUT (typical value)

PDN Cap (typical value)

Total COUT Value (after derating)

VS1

VS1

47uF/0603/6.3V/X5R *1

x

≥ 20.6uF

#2

VS2

VS2

47uF/0603/6.3V/X5R *1

x

≥ 20.6uF

#3

VMODEM

VRF09

22uF/0603/6.3V/X5R *1

0.1uF *10

≥ 10.3uF

#1

VPROC1

APU

4.3uF*2

≥ 30.9uF

#1

VPROC2

DLA

4.3uF*2

≥ 30.9uF

#1

VCORE

VRF13

22uF/0603/6.3V/X5R *1

0.1uF*6

≥ 10.3uF

#1

VGPU

VCORE

47uF/0603/6.3V/X5R *2 22uF/0603/6.3V/X5R *1

4.3uF*2+1uF*4

≥ 51.5uF

#1

VPU

VDIGRF

22uF/0603/6.3V/X5R *1

0.1uF*2

≥ 10.3uF

#1

47uF/0603/6.3V/X5R *1+ 22uF/0603/6.3V/X5R *1 47uF/0603/6.3V/X5R *1+ 22uF/0603/6.3V/X5R *1

Note #1: Total COUT Value @ 1V derating for AC 0.01Vrms and overall operating temperature. Note #2: Total COUT Value @ 2V for AC 0.01Vrms and overall operating temperature. Note #3: Total COUT Value @ 1.35V derating for AC 0.01Vrms and overall operating temperature.

CONFIDENTIAL B

Schematic/Layout Notice Buck Converter Input Decoupling

MT6359’s BUCK VPA VS2 VMODEM VPU VPROC1 VPROC2 VGPU11 VGPU12 VCORE VS1

CIN2 (typical value) -

10uF/0402/6.3V/X5R *2pcs #1 #4 #5

CIN1 (typical value) 10uF/0402/6.3V/X5R #1 2.2uF/6.3V/X5R #2 #3 #4 2.2uF/6.3V/X5R #2 #3 #4 2.2uF/6.3V/X5R #2 #3 #4 2.2uF/6.3V/X5R #2 #3 #4 2.2uF/6.3V/X5R #2 #3 #4 2.2uF/6.3V/X5R #2 #3 #4 2.2uF/6.3V/X5R #2 #3 #4 2.2uF/6.3V/X5R #2 #3 #4 2.2uF/6.3V/X5R #2 #3 #4

Note #1: Total CIN2 (10uF) Value ≥ 1.6uF @ 5V derating for AC 0.01Vrms and overall operating temperature. Note #2: CIN1 (2.2uF) can be 0402 size or 0201 size. Note #3: Total CIN1 (2.2uF) Value ≥ 0.36uF @ 5V derating for AC 0.01Vrms and overall operating temperature. Note #4: CIN2 can be NC while CIN1 be 2.2uF/0402 Note #5: CIN2 should be closed to MT6359 VSYS_XX pin within a 10mm distance

CONFIDENTIAL B

Schematic/Layout Notice Buck Input Cap. Layout Spec. #1

▪ If CIN1=0402 size ▪ MMD spec  The spec. of trace parasitic inductance from buck input cap to PMIC Ball Input Trace MT6359 Spec. for Inductance BUCK (from C to IC ball) ▪ (L_PWR1 + L_GND1) < Spec VSYS_VS1 IN1

VS1

L_PWR1

VSYS

PMIC

GND_BUCK L_GND1

CONFIDENTIAL B

GND_VPU

(L_PWR1 + L_GND1) < 2nH

VS2

VSYS_VS2 GND_VS2

(L_PWR1 + L_GND1) < 2nH

VPA

VSYS_VPA GND_VPA

(L_PWR1 + L_GND1) < 1.5nH

VMODEM

VSYS_VMODEM GND_VMODEM

(L_PWR1 + L_GND1) < 1nH

VPROC1

VSYS_VPROC1 GND_VPROC1

(L_PWR1 + L_GND1) < 1nH

VPROC2

VSYS_VPROC2 GND_VPROC2

(L_PWR1 + L_GND1) < 1nH

VCORE

VSYS_VCORE GND_VCORE

(L_PWR1 + L_GND1) < 1nH

VGPU11

VSYS_VGPU11 GND_VGPU11

(L_PWR1 + L_GND1) < 1nH

VGPU12

VSYS_VGPU12 GND_VGPU12

(L_PWR1 + L_GND1) < 1nH

VSYS_BUCK CIN 1

GND_VS1

VPU

VSYS_VPU

(L_PWR1 + L_GND1) < 2nH

Schematic/Layout Notice Layout Guide (1/2)

▪

Inductance need to follow application notice that has components selection guide.

▪

Placement, layout and schematic need to follow checklist.

Buck input cap detail layout rule, please refer to next page. CONFIDENTIAL B

Schematic/Layout Notice Layout Guide (2/2)

▪

Inductance need to follow application notice that has components selection guide.

▪

Placement, layout and schematic need to follow checklist.

Example 1 PMIC Buck GND ball

Example 2

Input Cap GND pad

PMIC Buck GND ball

Layer-1

Input Cap GND pad

Layer-1 GND return path

Layer-2

Layer-2 Solution 2

Solution 1

GND return path

Layer-3

Layer-3

Layer-5

Layer-5

Main-GND Layer

Main-GND Layer

CONFIDENTIAL B

Solution 2

Solution 1

Schematic/Layout Notice

Controller power trace layout constraint Bat. connector

Buck Input

GND

BAT_BUS

22uF

4mil

Buck controller power trace(VSYS_SMPS) must be use single trace connect to battery VBAT_BUS directly, and can’t merge with others. VSYS add 1Ω+/-5% Resistor to VSYS_SMPS CONFIDENTIAL B

56

Schematic/Layout Notice

Layout Guide 1/5: Remote Sense Application ▪

DC/DC remote sense feedback traces are recommended using GND shielding to avoid noise coupled.

CONFIDENTIAL B

Schematic/Layout Notice

Layout Guide 2/5: Remote Sense Application ▪

DC/DC remote sense feedback & feedback_GND traces are recommended using GND shielding and differential pair to avoid noise coupled.

CONFIDENTIAL B

Copyright © MediaTek Inc. All rights reserved.

2020/5/25

58

Schematic/Layout Notice

Layout Guide 3/5: Remote Sense Application Cout1

Rc1

L1

L4

Remote pt.1

Cout2

R_remote spec (Follow MMD SPEC)

Lout

Rc2

PMIC L3

SOC

L2 Cout3

Rc3 1. 2.

Find path with lowest inductance, the remote point can be located within Coutlowest L + 1n. For example, in case of Cout1 is path with lowest inductance. • Inductance between Cout1 and Remote pt. 1 is L4, L4 must be lower than 1n (L4 < 1n). • The remote point location can be between Cout1 and Remote pt. 1. 3. Same case apply to L2 & L3 if they are lowest inductance path. 4. Above case is for multi-path, in case of single path, consider the only path as the lowest inductance path directly. 5. Inductance between Cout1 and other Cout(Cout2/Cout3) must be lower than 1.5n(L1+L2 6mil

▪ Detail layout constraint please refer per project. CONFIDENTIAL B

77

Layout Constraint of LDO #5

Rough Guidelines-use from CAD Extraction w (mil) 4

w (um) 101.6

h (um) 50

t @ 1/3 oz (um) 12

L (nH) = 4.85 nH ×

len (cm) 1.27

trace inductance (nH) 4.85

trace resistance (mΩ) 198

101.6 um len h × × w 1.27 cm 50um

101.6 um len R (mΩ) = 198 mΩ × × w 1.27 cm

where w = 4mil~40mil

Parameter Dielectrically constant Conductivity CONFIDENTIAL B

Value 4.0 5.8e7 s/m

w = trace width len = trace length t = trace thickness h = dielectric height 78

Layout Constraint of VRTC ▪

VRTC: Application circuit (2 options) ▪

0.1uF

▪

0.1uF + 1.5kΩ + super cap



0.1uF cap MUST and be close to PMIC Noted: Follow Ref. Vcoin=22uF if customers don’t want FG re-define initial SOC at the scenario below

CONFIDENTIAL B

Scenario: Plug in charger then press power key over 15sec. Due to sub-PMIC would disable power MOS between VBAT to VSYS and stop charging, VRTC would drop at Vcoin=0.1uF after VSYS decreased. After that, FG will re-define initial SOC due to RTC disappeared

79

Layout Constraint of VREF ▪

VREF bypass cap as close as possible to PMIC

▪

GND_VREF pin must first connect to capacitor GND pin and then connect to system GND by VIA

▪

VREF cap is 100nF.

CONFIDENTIAL B

80

Layout Constraint of VIO18 ▪ Keep star-connection from PMIC VIO18_PMU to import 1.8V power domain. AP Peripheral PMIC MT6359

AVDD18_xx

VIO18_PMU

DVDD18_xx

Peripheral device I/O

CONFIDENTIAL B

81

Layout Constraint of VUSB Priority1 -The de-coupled cap should be put closed to AVDD30_AUD/ AVSS30_AUD and AVDD18_CODEC / AVSS30_AUD - The trace width should be >10mil - Connecting AVSS30_AUD to the main GND through at least one via - Connecting AVDD30_AUD from pad VUSB directly , then do a star connect from AVDD30_AUD to VUSB_PMU.

CONFIDENTIAL B

2020/5/25

82

AP ANALOG POWER PCB LAYOUT CONSTRAIN

CONFIDENTIAL B

83

AP Analog Power List Voltage

PMIC Pin Name

AP analog pin name

VIO18

AVDD18_USB AVDD18_APPLLGP AVDD18_MDPLLGP AVDD18_UFS AVDD18_CKSQ AVDD18_DRF AVDD18_WBG AVDD18_DPTX

1.8V

VIO18

VA12

AVDD12_CSI AVDD12_APPLLGP AVDD12_UFS AVDD12_WBG

1.2V

VA12_ABB1_PMU

1.2V

VRF12

AVDD12_SSUSB AVDD12_CKSQ AVDD12_DRF AVDD12_DRF (Columbus) AVDD12_DSI AVDD12_MDPLLGP AVDD12_USB AVDD12_DPTX AVDD12_DDR

1.2V

VA12_ABB2_PMU

1.2V

VBBCK

AVDD12_CKBUF_UFS

1.2V

VBBCK_PMU

0.75V

VSRAM_CORE

AVDD04_DSI

0.75V

VSRAM_CORE

1.8V

1.2V

3.07V

VUSB

CONFIDENTIAL B

AVDD33_USB 3.07V Copyright © MediaTek Inc. All rights reserved.

5/25/2020

VUSB

- 84 -

AP Analog Layout Constraint 

AVDD18_xxx layout constraint

Star-connection analog power group, AVDD18_SOC by short-pad on VIO18 cap.  Please be sure to follow “reference design” & “PMIC MMD” 

Follow PMIC MMD PMIC



IR spec.



Total path from PMIC LDO pin to AVDD power pin of AP-site



Target IR < 2%  For each AVDDXX_XXX path  Simulate all power pin currents at the same time CONFIDENTIAL B

Copyright © MediaTek Inc. All rights reserved.

5/25/2020

- 85 -

AP AVDD18_xxx Layout Guideline 1 Follow PMIC MMD AVDD18_xxx1

Others …

Cnx AVDD18_xxx2 Cnx

VIO18_PMU

PMIC

AVDD18_xxx3 Cnx

AP

VIO18 AVDD18_SOC

C1

SHORT PAD

AVDD18_xxx4

P1

Cnx AVDD18_xxx5

Notice 1. PCB drop voltage ≦ 36mV (PMIC VIO18 ball to AP AVDD18_xxx ball) 2. PCB Length/Width ≦ PCB Ratio Example

Cnx AVDD18_xxx6 Cnx

Trace End

Average current

Trace 1 PMIC VIO18 ball

C1

0.600A

20mil

180mil

9

0.3oz

16.0m

9.6mV

Trace 2

C1

P1

0.070A

12mil

1100mil

92

0.3oz

162.6m

11.4mV

Trace 3

P1

AP AVDD18_XXX ball

0.030A

8mil

300mil

38

0.3oz

66.5m

2.0mV

Trace

Trace Start

CONFIDENTIAL B

PCB Width

PCB Length

PCB Ratio Length/Width

Copyright © MediaTek Inc. All rights reserved.

PCB PCB PCB drop Thickness Resister voltage

5/25/2020

- 86 -

Pass ≦36mV

AP VA12  AVDD12_xxx Layout Guideline Follow PMIC MMD AVDD12_xxx1 Cnx AVDD12_xxx2 Cnx

PMIC

Cnx

AVDD12_xxx3

AP

VA12 C1

AVDD12_xxx4

P1

Cnx AVDD12_xxx5 Cnx

Notice 1. PCB drop voltage ≦ 24mV (PMIC VA12 ball to AP AVDD12_xxx ball) 2. PCB Length/Width ≦ PCB Ratio Example Trace

Trace Start

Trace End

AVDD12_xxx6 Cnx

Average PCB current Width

PCB Length

PCB Ratio Length/Width

PCB Thickness

PCB Resister

PCB drop voltage

Trace 1 PMIC VA12 ball

C1

0.250A

24mil

240mil

10

0.3oz

17.7m

4.4mV

Trace 2

C1

P1

0.250A

24mil

800mil

33

0.3oz

59.1m

14.8mV

Trace 3

P1

AP AVDD12_XXX ball

0.140A

12mil

200mil

17

0.3oz

29.6m

4.1mV

CONFIDENTIAL B

Copyright © MediaTek Inc. All rights reserved.

5/25/2020

- 87 -

Pass ≦24mV

AP VRF12  AVDD12_xxx Layout Guideline Follow PMIC MMD

AVDD12_xxx1 Cnx AVDD12_xxx2 Cnx

PMIC

Cnx

AVDD12_xxx3

AP

VRF12 C1

AVDD12_xxx4

P1

Cnx AVDD12_xxx5 Cnx AVDD12_xxx6 Cnx

Notice 1. PCB drop voltage ≦ 24mV (PMIC VRF12 ball to AP AVDD12_xxx ball) 2. PCB Length/Width ≦ PCB Ratio Ex ample

Cnx

AVDD12_DRF

RF

P2

Av erage

PCB

PCB

PCB Rat io

PCB

PCB

PCB drop v olt age

Trac e

Trac e St art

Trac e End

c urrent

Widt h

Lengt h

Lengt h/ Widt h

Thic k nes s

Res is t er

Trac e 1

PMIC VRF12 ball

C1

0. 250A

24mil

240mil

10

0. 3oz

17. 7m

4. 4mV

Trac e 2

C1

P1

0. 200A

24mil

800mil

33

0. 3oz

59. 1m

11. 8mV

Trac e 3

P1

AP AVDD12_ XXX ball

0. 050A

8mil

200mil

25

0. 3oz

44. 3m

2. 2mV

CONFIDENTIAL B

Copyright © MediaTek Inc. All rights reserved.

5/25/2020

- 88 -

Pass ≦24mV

AP VRF12  AVDD12_xxx Layout Guideline Follow PMIC MMD

AVDD12_xxx1 Cnx AVDD12_xxx2 Cnx

PMIC

Cnx

AVDD12_xxx3

AP

VRF12 C1

AVDD12_xxx4

P1

Cnx AVDD12_xxx5 Cnx AVDD12_xxx6 Cnx

Notice 1. PCB drop voltage ≦ 24mV (PMIC VRF12 ball to RF AVDD12_DRF ball) 2. PCB Length/Width ≦ PCB Ratio Ex ample

Cnx

AVDD12_DRF

RF

P2

Av erage

PCB

PCB

PCB Rat io

PCB

PCB

PCB drop

Widt h

Lengt h

Lengt h/ Widt h

Thic k nes s

Res is t er

v olt age

Trac e

Trac e St art

Trac e End

c urrent

Trac e 1

PMIC VRF12 ball

C1

0. 250A

24mil

240mil

10

0. 3oz

17. 7m

4. 4mV

Trac e 2

C1

P2

0. 050A

8mil

800mil

100

0. 3oz

177. 4m

8. 9mV

Trac e 3

P1

RF AVDD12_ DRF ball

0. 050A

8mil

200mil

25

0. 3oz

44. 3m

2. 2mV

CONFIDENTIAL B

Copyright © MediaTek Inc. All rights reserved.

5/25/2020

- 89 -

Pass ≦24mV

AP AVDD12_CKBUF_UFS Layout Guideline

Follow PMIC MMD

VBBCK

AVDD12_CKBU F_UFS

Cnx

AP

C1 P1

Notice 1. PCB drop voltage ≦ 24mV (VBBCK ball to AP AVDD12_CKBUF_UFS ball) 2. PCB Length/Width ≦ PCB Ratio Example

Average PCB current Width

PCB Length

PCB Ratio Length/Width

PCB Thickness

PCB Resister

PCB drop voltage

Trace

Trace Start

Trace End

Trace 1

PMIC VBBCK

C1

0.020A

8mil

240mil

30

0.3oz

53.2m

1.1mV

Trace 2

C1

P2

0.020A

8mil

800mil

100

0.3oz

177.4m

3.5mV

Trace 3

P1

AP AVDD12_XXX ball

0.020A

8mil

200mil

25

0.3oz

44.3m

0.9mV

CONFIDENTIAL B

Copyright © MediaTek Inc. All rights reserved.

5/25/2020

- 90 -

Pass ≦24mV

AP AVDD04_DSI Layout Guideline Follow PMIC MMD

Others …

SRAM_CORE

AVDD04_xxx

Cnx

AP AVDD04_xxx

Cnx

C1 P1

Notice 1. PCB drop voltage ≦ 15mV (SRAM_CORE ball to AVDD04_xxx ball) 2. PCB Length/Width ≦ PCB Ratio Ex ample

Av erage

PCB

PCB

PCB Rat io

PCB

PCB

PCB drop

Lengt h

Lengt h/ Widt h

Thic k nes s

Res is t er

v olt age

Trac e

Trac e St art

Trac e End

c urrent

Widt h

Trac e 1

SRAM CORE ball

C1

0. 500A

20mil

180mil

9

0. 3oz

16. 0m

8. 0mV

Trac e 2

C1

P1

0. 040A

12mil

1000mil

83

0. 3oz

147. 8m

5. 9mV

Trac e 3

P1

AP AVDD04_ XXX ball

0. 040A

8mil

120mil

15

0. 3oz

26. 6m

1. 1mV

CONFIDENTIAL B

Copyright © MediaTek Inc. All rights reserved.

5/25/2020

- 91 -

Pass ≦15mV

AP AVDD33_USB Layout Guideline Follow PMIC MMD

AP

PMIC VUSB

AVDD33_USB

Cnx C1

Notice 1. PCB drop voltage ≦ 30mV (PMIC VUSB ball to AP AVDD33_USB ball) 2. PCB Length/Width ≦ PCB Ratio Example Trace

Trace Start

Trace 1 PMIC VUSB ball Trace 2

C1

CONFIDENTIAL B

Trace End

Average PCB current Width

PCB Length

PCB Ratio Length/Width

PCB Thickness

PCB Resister

PCB drop voltage

C1

0.050A

8mil

200mil

25

0.3oz

44.3m

2.2mV

AP AVDD33_USB ball

0.050A

8mil

2500mil

313

0.3oz

554.3m

27.7mV

Copyright © MediaTek Inc. All rights reserved.

5/25/2020

- 92 Pass ≦30mV

SPI

CONFIDENTIAL B

93

Layout Constraint of PMIC SPI ▪ All traces of PMIC SPI bus should be well-shielded by nearby ground traces in the same layer, and surrounded by ground traces in n-1 and n+1 layers, and closed to each others. ▪ All traces of SPI bus should be far away from noisy sources, such as VBUS (plug-in spike), Buck switching node..etc.

▪ The max. length of SPI bus between SOC and MT6359 should be shorter than 6 inches (consider 6 inches = 1ns).

CONFIDENTIAL B

94

RTC

CONFIDENTIAL B

95

Schematics Design Notice •

RTC32K_CK trace length must be controlled within 2000mil.

[A] [B]

[C] • • •

• •

0.1uF for VRTC is a must. [A] Recommend implementing 10~100uF for VRTC. MTK recommend implement 22uF, Smaller capacity sustains shorter time. Please do not use Gold Cap. because of the time when removed the Main battery precision: +-1.5 sec every 30 sec. [B] For battery un-replaced system design, R8201(1.5K) and C8202(22uF) can be removed for eBOM optimized. [B] RTC32K_CK such as a clock signal, needs well ground shielding. [C] Noted: Follow Ref. Vcoin=22uF if customers don’t want FG re-define initial SOC at the scenario below

Scenario: Plug in charger then press power key over 15sec. Due to sub-PMIC would disable power MOS between VBAT to VSYS and stop charging, CONFIDENTIAL B 96 VRTC would drop at Vcoin=0.1uF after VSYS decreased. fine initial SOC due to RTC disappeared

Content ▪ ▪ ▪ ▪ ▪ ▪

Feature comparison MT6359 Introduction Function Description Reference Design Function Block Notice PCB Layout Guideline

CONFIDENTIAL B

97

Package Outline of MT6359PP

CONFIDENTIAL B

98

Ballmap of MT6359PP 202

1

2

3

4

5

6

7

8

A

NC

VRF12

VS2

VSYS_VS2

VSYS_VPA

VPA

VSYS_VPU

VPU

GND_VMODE VSYS_VMOD VSYS_VPROC VMODEM M EM 2

VPROC2

GND_VPROC VSYS_VPROC VSYS_VPROC A 2 1 1

B

VRF12_S

VA12

VS2

GND_VS2

GND_VPA

VPA

GND_VPU

VPU

GND_VMODE VSYS_VMOD VSYS_VPROC VMODEM M EM 2

VPROC2

GND_VPROC 2

C

VCN13

VS2_LDO2

VA09

VSYS_SMPS

VS2_FB

GND_SMPS

VPA_FB

GND_VPU_F B

D

VSRAM_MD VS2_LDO1

E

AU_V18N

F

FLYN

G

FLYP

VSRAM_PRO VSRAM_othe EXT_PMIC_P EXT_PMIC_E EXT_PMIC_E C1 rs G N2 N1

VSRAM_PRO C2

AVSS18_AUD

RESETB

GND

GND

9

VPU_FB

PWRKEY

10

11

CHRDETB

PMU_TESTM ODE

SPI_CLK

GND

GND

GND

LDO

E

XXX

AUDIO

VSYS_VGPU1 VSYS_VGPU1 F 2 2

XXX

DCXO

SRCLKEN_IN VSYS_VGPU1 VSYS_VGPU1 VGPU11_FB G 1 1 1

XXX

STRUP/PCHR_VREF

H

XXX

AUXADC/ FGADC

RTC32K_1V8 GND_VGPU1 GND_VGPU1 GND_VGPU1 WDTRSTB_IN J _1 1_FB 1 1

XXX

Digital IO

SPI_CSN

GND

SPI_MOSI

AU_HPR

AU_REFN

AUD_NLE_M AUD_DAT_M OSI1 ISO1

GND

GND

GND

FSOURCE

AU_HPL

AUD_DAT_M AUD_CLK_M ISO0 OSI

AU_HSP

AUD_DAT_M AUD_DAT_M OSI0 ISO2

DVSS18_IO

K

AVDD18_CO DEC

HP_EINT

ACCDET

AUD_DAT_M AUD_DAT_M OSI1 OSI2

DVDD18_DIG DVDD18_IO

L

AU_VIN0_P AU_VIN0_N AU_VIN3_N AU_VIN3_P

M

AU_VIN1_P AU_VIN2_P

AU_MICBIAS AU_MICBIAS 1 2

BATADC_P

CS_P

AUXADC_VIN 1

XO_WCN

AVSS_XO_IS AU_VIN1_N AU_VIN2_N AVSS_RFCK AVSS_BBCK O

SPI_MISO

VGPU12

VPROC1_FB

RTC32K_1V8 SRCLKEN_IN _0 0

AVSS18_AUX ADC

VAUX18

VFE28

SCP_VREQ_V AO

VGPU11

VGPU12

VGPU11

GND_VCORE GND_VCORE GND_VCORE K _FB

CS_N

GND_VREF

VREF

VRTC28

VIBR

VSYSSNS

BATON

UVLO_VTH

VIO28

VCAMIO

VAUD18

VEFUSE

VM18

VS1_LDO1

VS1_LDO2

VCORE

VCORE

VS1

VS1

N

VS1_FB

GND_VS1

VSYS_VS1

P

R

XTAL1

AVSS_XO

VRFCK_1

XO_CEL

VBBCK

XO_EXT

VUSB

VSIM1

R

AVSS_XO

XTAL2

VXO22

VRFCK

XO_SOC

XO_NFC

VBIF28

VSIM2

VEMC

VCN33_1

VCN33_2

VUFS

VCN18

VRF18

VIO18

NC

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

CONFIDENTIAL B

L

VCORE_FB VSYS_VCORE VSYS_VCORE M

P

VSYS_LDO2 VSYS_LDO1

B

XXX

GND

AU_HSN

VPROC1

GND_VPROC GND_VGPU1 GND_VGPU1 D 1_FB 2 2

VPROC2_FB

HOMEKEY

GND

AVDD30_AU AVSS30_AUD D

VPROC1

16

BUCK

AUD_NLE_M AUD_SYNC_ OSI0 MOSI

J

15

XXX

AU_LOLN

AVDD18_AU D

14

GND_VPROC GND_VPROC C 1 1

AU_LOLP

AU_MICBIAS 0

13

GND_VMODE GND_VPROC VMODEM_FB M_FB 2_FB

H

N

12

99

Layout: MT6359PP Power Input (1/2) VSYS Input 

Routing from 22uF VSYS capacitor uses start topology to connect to each device. 1. Input for BUCK. (Fig. 2) 2. Input for LDO. (Fig. 2)



All the decoupling capacitors should be placed near MT6359. The priority is buck capacitor then decoupling capacitor of LDO. (Fig.1)

Fig. 2

Fig. 1

CONFIDENTIAL B

100

Layout: MT6359PP Power Input (2/2)  Layout method of MT6359PP power Input for Buck GND

Fig.1

-

Buck GND balls are connected to buck capacitors close to pin with plane or trace (Trace Width > 8mil * N (ball number) + M (ball pitch)). (Fig.1~2)

-

Buck GND balls should be connected to buck capacitors first and isolated from the nearby GND trace and plane then connected to main GND at L3 (Fig.1~2).

Fig.2

MT6359

CONFIDENTIAL B

BUCK GND is isolated from nearby GND trace and plane.

101

Layout: MT6359PP Buck Output (1/2) Fig.2 

The buck inductors should be placed near MT6359PP. (Fig.1)

Fig.1

MT6359

CONFIDENTIAL B

102

Layout: MT6359PP Buck Output (2/2) 

Those signals are differential pairs and should be shielded by GND and far away from noise signals (Fig.1 ~ Fig.2). 1. VPROC1_FB/GND_VPROC1_FB 2. VPROC2_FB/GND_VPROC2_FB 3. VCORE_FB/GND_VCORE_FB 4. VPU_FB/GND_VPU_FB Fig. 1 5. VGPU11_FB/GND_VGPU11_FB 6. VMODEM_FB/GND_VMODEM_FB 7. VS1_FB, VS2_FB, VPA_FB

Fig. 2

CONFIDENTIAL B

103

Layout: MT6359 Buck Output ▪

Layout guideline for MES simulation.

MT6359

Application

Resistance (PMIC to SoC power ball)

VSRAM_PROC1

DVDD_SRAM_PROC_B

≤ 100 mΩ

VSRAM_PROC2

DVDD_SRAM_PROC_L

≤ 100 mΩ

VSRAM_OTHERS

DVDD_SRAM_GPU

≤ 90 mΩ

VSRAM_MD

DVDD_SRAM_APU

≤ 90 mΩ

VPROC1

DVDD_APU

≤ 23 mΩ

VPROC2

DVDD_DLA

≤ 27 mΩ

VGPU11/VGPU12

DVDD_CORE

≤ 7.5 mΩ

EXT_PWR for VDD1

VDD1_EMI

≤ 11 mΩ

CONFIDENTIAL B

104

Layout: MT6359PP LDO Output (1/2) 

See table. for the suggested LDO output layout.

1. Trace width≧6mil 2. Value and placement of capacitor please refer design notice Ball name VFE28 VAUX18 VBIF28 VCN33_1 VCN33_2 VIO28 VEMC VSIM1 VSIM2 VIBR VUSB VEFUSE VAUD18 VCAMIO VM18 VUFS VCN18 VRF18 VIO18 VCN13 VRF12 VA12 VA09

Imax 200mA 50mA 50mA 800mA 800mA 200mA 800mA 200mA 200mA 200mA 200mA 300mA 300mA 300mA 300mA 1200mA 1200mA 450mA 600mA 350mA 800mA 300mA 300mA

CONFIDENTIAL B

Trace Length 1500mil 1500mil 1500mil 1500mil 1500mil 1500mil 1500mil 1500mil 1500mil 1500mil 1500mil 1000mil 1500mil 1500mil 900mil 1200mil 1500mil 1200mil 1500mil 1500mil 1500mil 1200mil 1200mil

Trace Width 6mil 6mil 6mil 25mil 25mil 10mil 25mil 10mil 10mil 6mil 8mil 12mil 12mil 6mil 25mil 25mil 8mil 20mil 20mil 25mil 25mil 20mil 20mil

Rpcb H=50um, 1/3 oz 400mΩ 400mΩ 400mΩ 100mΩ 100mΩ 240mΩ 100mΩ 240mΩ 240mΩ 400mΩ 300mΩ 135mΩ 200mΩ 400mΩ 60mΩ 80mΩ 300mΩ 100mΩ 120mΩ 100mΩ 100mΩ 100mΩ 100mΩ



Core power/DRAM power/AVDDxx power: 



VRF18/VRF12/VRF12_S: •



Traces should be in inner layer or under shielding case.

VRF12_S: 



Follow MMD/MES

VRF12_S should connect to VRF12 application

Trace width/length can adjust by application Imax

If trace is series 0Ω resister, 0Ω resister is having 0~50mΩ variation. It would be drop voltage.

105

Layout: MT6359PP LDO Output (2/2) 

VREF capacitor should be placed near L12/L11 pin.



DVDD18_DIG capacitor should be placed near K10 pin.

MT6359PP

CONFIDENTIAL B

106

Layout: Others for MT6359 Gauge

CS_P/CS_N (ball: L9/L10) should be routed as differential pairs and far away from noise signals.

MT6359PP DCXO_32K

CS_P CS_N

CONFIDENTIAL B

107

MT6359 Audio PCB Layout Guide 

MT6359 Audio PCB Layout Guide Please refer “ MT6883 Design Notice “

CONFIDENTIAL B

108

MT6359 AuxADC/DCXO PCB Layout Guide 

MT6359 AUXADC /DCXO PCB Layout Guide Please refer “ MT6883 Design Notice “

CONFIDENTIAL B

109

Chip Placement Recommendation  Following PCB layout are recommended by MTK for WLCSP 1. Opposite shield frame could not overlap package outline. 2. The opposite chip (especially large chip, ex. AP & eMCP) could not overlap package outline. 3. Underfill is suggested to adopt - Recommended property: CTE-1 < 30 ppm/˚C, Tg > 125 ˚C.

CONFIDENTIAL B

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2020/5/25

110

How to Connect for Un-usd Pin Unused Part

Pin Name

Pin Connection if not used

Description

Interface

EXT_PMIC_ENx Ext chip enable pin HOMEKEY button with default long press function HOMEKEY HOMEKEY button without default long press function

Floating Short to GND Floating

General

BATON

Battery NTC pin for battery and its temperature sensing

1. Short to GND while RU=NC 2. Pull-Low 10KΩ to GND while RU exist

BATADC CS_N CS_P XO_NFC XO_EXT

Fuel gauge ADC input pin for monitoring battery voltage Fuel gauge ADC input pin Fuel gauge ADC input pin 26MHz output to NFC 26MHz output to UFS or others

VBAT GND GND Floating Floating

Gauge DCXO

CONFIDENTIAL B

111

UFS2.1 / UFS3.0 Power configuration  UFS long term power plan required 2.5V/3.0V 1. PMIC VEMC LDO add 2.5V/3.0V HW trapping for UFS2.0/UFS3.0 2. UFS3.0 needs 1.2V requirement should find ext. Buck/LDO and needs VIO18 enable for satisfied UFS sequence 3. UFS sequence: a. Power on sequence: 1.8V(VUFS18)  1.2V(Ext.)  3.0V(VEMC) b. Power off sequence: 3.0V(VEMC)  1.2V (Ext.)  1.8V(VUFS18)

CONFIDENTIAL B

112

Chip Placement Recommendation  Following PCB layout are recommended by MTK for WLCSP (MT6359 / MT6360/MT6315) 1. Opposite shield frame could not overlap package balls 2. The opposite chip (especially large chip, ex. AP & eMCP) could not overlap package balls 3. If underfill was adopted, the properties were recommended : - CTE-1 < 30 ppm/˚C, Tg > 125 ˚C

CONFIDENTIAL B

Copyright © MediaTek Inc. All rights reserved.

2020/5/25

113

MT6359 PMIC Part Number Notice

Platform P/N

MT6799 MT6359P

MT6785 MT6359KP

MT6883 MT6359VPP

PMIC P/N

CONFIDENTIAL B

114

Copyright © MediaTek Inc. All rights reserved.