MT6359 Design Notice (for MT6853) [0.2 ed.]

Citation preview

CONFIDENTIAL B

MT6359 Design Notice (for MT6853)

V0.2 2020/05/20

History Revision V0.1

V0.2

Date 2020/04/10 Initial

Description

1. Page 45 update “Buck Converter Output Decoupling #2” 2. Page 80 update “AP Analog Power List” 2020/05/20 3. Page 94, 95 delete “How to set 32K driving” 4. Page 92, 93 update “RTC”

CONFIDENTIAL B

Content ▪ ▪ ▪ ▪

MT6359 Introduction Function Description Function Block Notice PCB Layout Guideline

CONFIDENTIAL B

MT6359 – General Description ▪

The MT6359 highly integrated function fulfill all power requirement in smart phone system •

Buck Converters MT6359 x 10 (VCORE, VGPU, VRF09, VS1, VS2, VPROC_L, VPROC_B(x2), DIGRF, VPA)

•

LDOs ▪ Analog LDO ▪ Digital LDO ▪ RTC

•

*6 * 25 *1

Audio ▪ Audio Codec ▪ Audio Line Out

• • • •

RTC Macro Fuel Gauge XO Control and Output Ext. LDO ▪ RT9078 (RFIO18)

CONFIDENTIAL B

Copyright © MediaTek Inc. All rights reserved.

3

MT6359 + MT6360+MT6315 Power Plan MT6359VNP/NP

AC Adaptor or USB VBUS

MT6359

MT6360UP / A

MT6315NP/B

MT6360

MT6315

MT6360 VSYS

Charger

Current Sinks

VPA

R/G/B LEDs

1A 0.5V ~ 3.4V

VPROC1

LDO

ON

4.8A 0.4V ~ 1.19V

BATFET

USB Type-C

OFF

VBAT

TypeC/PD

VPROC2 4.8A 0.4V ~ 1.19V

VPU Battery Pack

Camera Flash Current Driver

2.4A 0.4V ~ 1.19V

VMODEM 4.8A 0.5V ~ 1.10V

VCORE

ON

CPU-L 1.8V, 300mA

ON

RF_DIG

VCAMIO

OFF

1.8V, 300mA

OFF

RF RF09

VCN18 VRF18

ON

CORE

OFF

1.8V, 1200mA

OFF

1.8V, 450mA

VIO18

ON

1.8V, 600mA

ON

CPU-B

VEFUSE

OFF

1.8V, 300mA

VUFS

VS1

ON

ON

VM18

ON

1.8V, 300mA

VRFCK

Peripherals

2A

RTC

VCN33_1

VCN33_2 :2.8

VCN13

ON

Audio UL

3V, 200mA

LDO3 LDO5

Camera IO

3V, 800mA

MT6631 (WCN)

3V, 800mA

RF

2.8V, 200mA

VEMC VIBR VSIM1 IO, AVDD

1.86V, 200mA

eFuse

1.86V, 200mA

UFS/MMC

1.8V, 150mA

LPDDR4x

1.8V, 200mA

VSIM2 LDO1

LDO2

RF RFIO_18

OFF

VBIF28 MT6631 (WCN)

2.8V, 800mA

2.8V, 200mA

RF Clock Buffer

OFF

3.3V, 800mA

Audio DL

ON

1.8V, 300mA

Camera Power Display Power VS2

PMIC DIG

ON

1.24V, 10mA

RT9078

System Power

ON

1.86V, 1200mA 2A 2.0V

WCN Power

ON

2.8V, 2mA

VAUD18

9.6A

RF Power

ON

1.8V, 10mA

VRTC

GPU

0.4V ~ 1.19V

Memory/ storage

DVDD18_DIG

VIO28

4.8A 0.4V ~ 1.3V

VGPU11 //VGPU12

3G/LTE PA

OFF

2.8V, 50mA

VFE28

OFF

2.8V, 200mA

OFF

IO & Sensor

OFF

MSDC1 (SD Car d)

OFF

SD CARD

ON OFF

OFF OFF OFF OFF

VUSB

ON

3.07V, 200mA

VAUX18

ON

1.84V, 50mA

VXO22

ON

2.24V, 50mA

Battery temp. sensor

RFFE USB 2.0 Audio AUXADC DCXO

eMMC Vibrator VCAMAF_EXT

OFF

Camera AF

SIM1 SIM2

VCAMA EXT1/2/3

Finger Print

LCD BL Driver

Touch Panel

OFF

Camera AVDD

OFF LCM

LCD +/- Bias

VCAMD EXT1/2/3

OFF

OFF

Camera DVDD

OFF

1.3V, 350mA

1.35V

External Power

VRF12

ON

1.2V, 800mA

RF ABB

VA12

MT6315NP/B VBUCK4

1.2V, 300mA

ON SRAM_MD

5A

VBUCK2 //VBUCK1

ON

10A

BUCK3

ON

MODEM (MD+NR)

VSRAM_PROC1 0.5V~1.29V 600mA

VSRAM_PROC2

ON

ON

0.5V~1.29V 600mA

VSRAM_OTHERS

5A

ON

ON

0.5V~1.29V 600mA

APU

VSRAM_MD

ON

0.5V~1.29V 600mA

VA09

ON

0.85V, 300mA

VBBCK

ON

1.2V, 10mA

LDO6

ON

0.75V, 300mA

CONFIDENTIAL B

VBUCK1 3A / 1.125V

ON

VBUCK2

OFF

LDO7 0.6V, 600mA

RF

ABB CPU-B SRAM

CPU-L SRAM

OTHER SRAM

GPU SRAM

RFDIG SRAM

BB Clock Buffer DDRPHY VMDDR

ON

LPDDR4x

4

MT6359 Buck Power Plan Circuit Type

Buck

Buck Name (Application name) VPROC1 (DVDD_GPU) VPROC2 (DVDD_PROC_L) VGPU11+12 (DVDD_PROC_B) VCORE (DVDD_CORE) VMODEM (VRF09_PMU) VPU (VDIGRF_PMU) VS1 (VS1_PMU) VS2 (VS2_PMU) VPA (VPA_PMU)

CONFIDENTIAL B

Output Voltage Range (V) 0.40 ~ 1.19 (6.25mV/step) 0.40 ~ 1.19 (6.25mV/step) 0.40 ~ 1.19 (6.25mV/step) 0.40 ~ 1.3 (6.25mV/step) 0.50 ~ 1.10 (6.25mV/step) 0.40 ~ 1.19 (12.5mV/step) 1.86 ~ 2.20 (12.5mV/step) 1.20 ~ 1.50 (12.5mV/step) 0.50 ~ 3.40 (50mV/step)

Boot Default (V)

IOUT-MAX (mA)

ON (0.75)

4800

ON (0.75)

4800

ON (0.75)

4800 *2

ON (0.75)

4800

OFF

4800

ON (0.7)

2400

ON (2.0)

2200

ON (1.35)

2500

OFF

1000

Copyright © MediaTek Inc. All rights reserved.

5

MT6359 LDO Power Plan (1/4) Circuit Type

LDO Name

Output Voltage (V)

Boot Default (V)

IOUT-MAX (mA)

Expected use

VFE28

2.80

OFF (2.8)

200

RFFE

VUSB

3.07

ON (3.07)

200

USB

VAUX18

1.84

ON (1.84)

50

AUXADC

VXO22

2.24

ON (2.24)

25

DCXO

VBIF28

2.80

OFF (2.8)

50

Battery Interface

VRTC

VRTC

2.80

ON (2.8)

2

RTC

VDIG

DVDD18_DIG

1.80

ON (1.8)

10

PMIC Digital

ALDO

CONFIDENTIAL B

MT6359 LDO Power Plan (2/4) Circuit Type

LDO Name VSIM1 VSIM2

DLDO

Output Voltage (V)

1.7/1.8/1.86/ 2.76/3.0/3.1 1.7/1.8/1.86/ 2.76/3.0/3.1

Boot Default (V)

IOUT-MAX (mA)

Expected use

OFF (1.86)

200

SIM

OFF (1.86)

200

SIM

VCN33_1

3.3/3.4/3.5/3.6

OFF (3.3)

800

Connectivity

VCN33_2

3.3/3.4/3.5/3.6

OFF (3.3)

800

Connectivity

VEMC

2.55/2.9/3.0/3.3

ON (3.0)

800

eMMC / UFS

VIO28

2.8/2.9/3.0/ 3.1/3.2/3.3

OFF (2.8)

200

IO & Sensor

VIBR

2.7/2.8/3/3.3

OFF (2.8)

200

Vibrator

CONFIDENTIAL B

MT6359 LDO Power Plan (3/4) Circuit Type

LDO Name

Output Voltage (V)

Boot Default (V)

IOUT-MAX (mA)

Expected use

VEFUSE

1.80

OFF (1.8)

300

EFUSE

VAUD18

1.80

ON (1.8)

300

Audio

VCAMIO

1.80

OFF (1.8)

300

Camera IO

VM18

1.80

ON (1.8)

300

DRAM

VRF18

1.80

OFF (1.8)

450

RF

VIO18

1.80

ON (1.8)

600

IO & Sensor

VCN18

1.80

OFF (1.8)

1200

Connectivity

VUFS

1.86

ON (1.86)

1200

eMMC / UFS

VRFCK

1.40 @ boot 1.60 @ work

ON (1.4)

10

DCXO

VBBCK

1.24

ON (1.24)

10

DCXO

SLDO1

DCXO LDO

CONFIDENTIAL B

MT6359 LDO Power Plan (4/4) Circuit Type

LDO Name

Output Voltage (V)

Boot Default (V)

IOUT-MAX (mA)

Expected use

VA09

0.85

ON (0.85)

300

DIGRF SRAM (VRF0P85_MEM_PMU)

VA12

1.2

ON (1.2)

300

AP Analog Module

VCN13

1.3

OFF (1.3)

350

Connectivity

ON (0.85)

600

CPUB SRAM

ON (0.85)

600

CPUL SRAM

ON (0.75)

600

OTHERS SRAM

ON (0.85)

600

GPU SRAM

ON (1.2)

800

AP Analog Module

VSRAM_PROC1 SLDO2 VSRAM_PROC2 VSRAM_OTHERS VSRAM_MD VRF12

CONFIDENTIAL B

0.60 ~ 1.2 (6.25mV/step) 0.60 ~ 1.2 (6.25mV/step) 0.60 ~ 1.2 (6.25mV/step) 0.60 ~ 1.2 (6.25mV/step) 1.2

Feature List Function

MT6356

MT6358

MT6359

Buck Converter

6

9

10

LDO

31

28

31

Driver

ERM Vibrator *1

ERM Vibrator *1

ERM Vibrator *1

Audio

Audio Codec

Audio Codec

Audio Codec

Others

RTC macro

RTC macro SD_DET

RTC macro

Charger

Fuel Gauge

Fuel Gauge

Fuel Gauge

CONFIDENTIAL B

Content ▪ ▪ ▪ ▪

MT6359 Introduction Function Description Function Block Notice PCB Layout Guideline

CONFIDENTIAL B

Power ON/OFF Sequence

by Pressing PWRKEY or Charger Plug In/Out VSYS

VSYS

DDLO

DDLO

UVLO

UVLO

delay time = 33ms

delay time = 141ms

CHRDETB

CHRDETB delay time = 42ms

delay time = 35ms

PWRKEY PWRHOLD (SW RG)

PWRKEY PWRHOLD (SW RG)

10mA •



VAUX18 continuous power on to accumulate system power consumption.

GM3.0 is disabled, VAUX18 follow normal power-off sequence. RESETB

VAUX18

Note: all the timing spec variation : ±20%

500ms

If IBAT>10mA

If IBAT 150 ℃ PMU HW shutdown

CONFIDENTIAL B

DCAP

Safety Protection when High Temperature ▪ Disable charger in auto power on (DCAP) condition when high temperature • Enable flow ▪ Set DCAP enable by SW when charger in and BAT temp > HT shutdown level (default 60⁰C)

• Release flow ▪ DCAP disable is auto reset when charger plug out

※ DCAP enable flow need follow programming guide setting CONFIDENTIAL B

SPAR Flow Chart PMIC exception: 1.no power on source 2.UVLO 3.BUCK OC 4.Power not good 5.Thermal shutdown 6.WDTRSTB 7.Long Press shutdown

PMIC exception occurs PMIC RSTB=0

PMIC Off state

Power on condition

SW bring up => PWRHOLD =1 => Clear SPAR power on condition

PMIC exception occurs PMIC RSTB=0

No Check SPAR function

Yes PMIC exception occurs PMIC RSTB=0

NO

CONFIDENTIAL B

PMIC exception is UVLO && VBAT drop time < 0.1s/0.6s/1.6s/always on VBAT drop time = VBAT < UVLO_off to VBAT > UVLO_on

YES

SPAR power on source set to High, keep all SPAR related RG setting

SPAR ▪ Feature support condition • VRTC output need coin cell or keep-alive capacitor

▪ Enabled by software • Three time settings can be selected ▪ ▪ ▪ ▪

100ms, VRTC output need coin cell or >2.2uF capacitor 0.6s, VRTC output need coin cell or >4.7uF capacitor 1.6s , VRTC output need coin cell or >22uF capacitor Min SPAR trigger condition: “duration of (VSYS 1ms VBAT

0.1/0.6/1.6sec

VRTC UVLO PWRKEY PWRHOLD

SPAR de-bounce

PWRON

RESETB CONFIDENTIAL B

FSOURCE, PMU_TESTMODE ▪

FSOURCE, PMU_TESTMODE • These pins should be connected to ground for normal operation.

PMIC PMU_TESTMODE

FSOURCE

CONFIDENTIAL B

Power Domain for I/O MT6359 Pin Name PWRKEY HOMEKEY RESETB CHRDETB EXT_PMIC_EN1 EXT_PMIC_EN2 EXT_PMIC_PG WDTRSTB_IN SRCLKEN_IN0 SRCLKEN_IN1 SPI_CSN SPI_CLK SPI_MOSI SPI_MISO

CONFIDENTIAL B

Power Source Ball Name DVDD18_DIG DVDD18_IO VIO18 VSYS_SMPS VSYS_SMPS VSYS_SMPS VSYS_SMPS DVDD18_IORT (SoC) DVDD18_IORT (SoC) DVDD18_IORT (SoC) DVDD18_IORT (SoC) DVDD18_IORT (SoC) DVDD18_IORT (SoC) DVDD18_IORT (SoC)

Power Source Domain DVDD18_DIG VIO18 VIO18 VSYS VSYS VSYS VSYS VIO18 VIO18 VIO18 VIO18 VIO18 VIO18 VIO18

Power Source Voltage 1.8V 1.8V 1.8V 3.1V ~ 5.0V 3.1V ~ 5.0V 3.1V ~ 5.0V 3.1V ~ 5.0V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V

Content ▪ ▪ ▪ ▪

MT6359 Introduction Function Description Function Block Notice PCB Layout Guideline

CONFIDENTIAL B

BAT_ON

CONFIDENTIAL B

Block Diagram for Smart Battery 3-PIN Smart Battery Smart battery

VBAT

VBATXXX

SPI

▪

BAT Presence Detection

BIF

BATON

MIPI BIF Module

RNTC

Secondary Slave

BIF

Secondary Slave

C3

BCL R4

Secondary Slave

BIF

Battery cell

BIF

VBIF28

Primary Slave

AP

PMIC

SRCLKEN_IN

GND

KEY FEATURES • MIPI BIF Smart Battery • HW Battery Pack Presence / Removal Detection

CONFIDENTIAL B

CPU

HW Battery Presence Detection ▪ Battery presence is detected by sensing the existence of RNTC or RID resistor inside the battery pack. ▪ Dedicated comparator is used for Battery Pack Presence/ Removal Detection. • Battery pack is considered not present if BAT_ON is above 0.964*VBIF. • Interrupts are generated when detecting battery insertion or removal • Charging shall be stopped upon battery removal Parameter

Min

Typ

Max

Units

Presence Detection comparator threshold

(0.964*VBIF)-20mV

0.964*VBIF

(0.964*VBIF)+20mV

V

CONFIDENTIAL B

BATON: Schematics & Layout Notice Smart battery

VBAT

VBATXXX

SPI BAT Presence Detection

BIF

BATON

MIPI BIF Module

RNTC

Secondary Slave

BIF

Secondary Slave

C3

BCL

CPU

R4

Secondary Slave

BIF

Battery cell

BIF

VBIF28

Primary Slave

AP

PMIC

SRCLKEN_IN

GND

C3: VBIF bypass cap (1uF)

R4: pull high resistor

 VBIF need bypass cap 1uF  BATON trace total capacitance : • should be smaller than 50pF with Smart battery • should be smaller than 500pF with Low cost battery CONFIDENTIAL B

RNTC: Thermistor (IN pack side)

R4/RNTC Selection Guide • Should Limit selection of R4 // RNTC < 40KΩ for getting more stable voltage after ADC settled • BATON noted that VOH should over 1.1V once using BIF battery

Voltage of BATON pin should follow BIF Spec.

CONFIDENTIAL B

Copyright © MediaTek Inc. All rights reserved.

2020/5/25

32

Note 1: Recommended Location of NTC in Battery Pack ▪ Recommended location of NTC in battery pack • Move NTC thermistor away from P+ and P• Mount NTC thermistor to the side of PCB toward the cell 10K 1% NTC

P-

CONFIDENTIAL B

P+

33

Note 2: Confirm to Meet the above Specifications ▪ Violation of the above specifications will result in measurement error of battery’s temperature.

Battery will be under dangerous environment.

CONFIDENTIAL B

34

Content ▪ ▪ ▪ ▪

MT6359 Introduction Function Description Function Block Notice PCB Layout Guideline

CONFIDENTIAL B

Fuel Gauge

CONFIDENTIAL B

Fuel Gauge: Schematics & Layout Notice ▪

1 : Sense resistor Rfg should be ±1% ,0.5W↑(depend on system max power consumption 7A-> 0.5W, 10A -> 1W) package in series with battery negative terminal to ground

▪ ▪

2：Rfg should be placed near battery connector in PCB layout. 3：FGP_IC/FGN_IC should be 4mil differential traces from chip CS_N/CS_P to Rfg

MT6359

CONFIDENTIAL B

FGN_IC, FGP_IC: Layout Example 4mil 4mil

FGP is connected to system GND. It needs adequate amount of VIAs to system GND in order to withstand system current consumption.

FGP

FGN

FGN is connected to BATTERY GND. It needs adequate trace width to BATTERY GND In order to withstand the system current consumption

Rfg Please note that sense traces should be connected to the middle of the pads and the layout should be symmetry between FGN and FGP(Kelvin Connection).

Rfg

FGP_IC CONFIDENTIAL B

FGN_IC

GM3.0 Board Offset Calibration Test Point (Option)

TP1 & TP2 for system power supply ——The test point should on the main trace ，as it is used for power input point

TP2 & TP3 for GM3.0 calibration ——The test point should on the main trace ，or the width of trace to test point should not less than 40 mil as the current would be 1000mA ——The test point DO NOT draw from the trace of CS_N &CS_P

TP3 Rfg TP2

TP1 TP2

TP3

TP2

Rfg For GM3.0 For Power Supply CONFIDENTIAL B

The TP3 is on the trace between CS_N Pad to Battery GND

Layout Example ▪ TP should be placed on main power trace, not on current sensing trace. Current Sensing Resistor

Current Sensing Trace (X) CONFIDENTIAL B

Main Power Trace (O)

DC-DC

CONFIDENTIAL B

Buck: Schematic/Layout Notice

Input Decoupling Placement and Schematic Guide ▪

Please place CIN as close to PMIC as possible and put in shield case.

▪

GND_VBUCKs x balls(as highlight in following fig.) must connect to related input cap first, and then connect to main GND plane.

CONFIDENTIAL B

Buck: Schematic/Layout Notice

Output Decoupling Placement and Schematic Guide ▪

Place power inductors as closer to PMIC balls as possible and put in shield case.

▪

VBUCK_FB & GND_VBUCK_FB layout should follow PCB layout constraint.

CONFIDENTIAL B

Schematic/Layout Notice

Buck Converter Output Decoupling #1 BUCK

Application

Inductor

Total COUT Range

VS1

VS1

1uH/2016

(22uF*2) ~ (47uF+10uF)

VS2

VS2

1uH/2016

(22uF*2) ~ (47uF+10uF)

VPA

VPA

1uH/2016

1uF + 14uF

VMODEM

VRF09

1uH/2016

(22uF) ~ (22uF+10uF)

VPROC1

VGPU

0.24uH/2016

(22uF*4) ~ (22uF*4 + 10uF*2)

VPROC2

VPROC_L

0.24uH/2016

(22uF*3) ~ (22uF*3 + 10uF*2)

VCORE

VCORE

0.24uH/2016

(22uF*4+10uF) ~ (22uF*4 + 10uF*2)

VGPU11

VGPU12 VPU

VPROC_B VDIGRF

0.24uH/2016

0.24uH/2016 1uH/2016

(22uF*4) ~ (22uF*4 + 10uF*3) (22uF) ~ (22uF+10uF)

Note1: for VPA out cap distribution, please refer “VPA Output Capacitance Notice”

CONFIDENTIAL B

Schematic/Layout Notice

Buck Converter Output Decoupling #2 Buck

Application

PMIC COUT (typical value)

PDN Cap (typical value)

Total COUT Value (after derating)

VS1

VS1

22uF/0603/6.3V/X5R *2

x

≥ 20.6uF

#2

VS2

VS2

22uF/0603/6.3V/X5R *2

x

≥ 20.6uF

#3

VMODEM

VRF09

22uF/0603/6.3V/X5R *1

Reference Design SCH.

≥ 10.3uF

#1

VPROC1

VGPU

22uF/0603/6.3V/X5R *4

Reference Design SCH.

≥ 41.2uF #1

VPROC2

VPROC_L

22uF/0603/6.3V/X5R *3

Reference Design SCH.

≥ 30.9uF #1

VCORE

VCORE

22uF/0603/6.3V/X5R *4

Reference Design SCH.

≥ 46.5uF

#1

VGPU

VPROC_B

22uF/0603/6.3V/X5R *3

Reference Design SCH.

≥ 41.2uF

#1

VPU

VDIGRF

22uF/0603/6.3V/X5R *1

Reference Design SCH.

≥ 10.3uF

#1

Note #1: Total COUT Value @ 1V derating for AC 0.01Vrms and overall operating temperature. Note #2: Total COUT Value @ 2V for AC 0.01Vrms and overall operating temperature. Note #3: Total COUT Value @ 1.35V derating for AC 0.01Vrms and overall operating temperature.

CONFIDENTIAL B

Schematic/Layout Notice Buck Converter Input Decoupling #1

MT6359’s BUCK VPA VS2 VMODEM VPU VPROC1 VPROC2 VGPU11 VGPU12 VCORE VS1

CIN2 (typical value) -

10uF/0402/6.3V/X5R *2pcs #1 #4

CIN1 (typical value) 10uF/0402/6.3V/X5R #1 2.2uF/6.3V/X5R #2 #3 2.2uF/6.3V/X5R #2 #3 2.2uF/6.3V/X5R #2 #3 2.2uF/6.3V/X5R #2 #3 2.2uF/6.3V/X5R #2 #3 2.2uF/6.3V/X5R #2 #3 2.2uF/6.3V/X5R #2 #3 2.2uF/6.3V/X5R #2 #3 2.2uF/6.3V/X5R #2 #3

Note #1: Total CIN2 (10uF/0402) Value ≥ 1.6uF @ 5V derating for AC 0.01Vrms and overall operating temperature. Note #2: CIN1 (2.2uF) can be 0402 size or 0201 size. Note #3: Total CIN1 (2.2uF) Value ≥ 0.36uF @ 5V derating for AC 0.01Vrms and overall operating temperature. Note #4: CIN2 should be closed to MT6359 VSYS_XX pin and follow layout spec. in page 51.

CONFIDENTIAL B

Schematic/Layout Notice Buck Converter Input Decoupling #2

BUCK VPA

Input Capacitor Typical Vale 10uF/0402/6.3V/X5R

Total CIN Value (after derating) ≥ 1.7uF #1

VS2

4.7uF/0402/6.3V/X5R

≥ 0.84uF #1

VMODEM

10uF/0402/6.3V/X5R

≥ 1.7uF #1

VPU

10uF/0402/6.3V/X5R

≥ 1.7uF #1

VPROC1

10uF/0402/6.3V/X5R

≥ 1.7uF #1

VPROC2

10uF/0402/6.3V/X5R

≥ 1.7uF #1

VGPU11

10uF/0402/6.3V/X5R

≥ 1.7uF #1

VGPU12

10uF/0402/6.3V/X5R

≥ 1.7uF #1

VCORE

10uF/0402/6.3V/X5R

≥ 1.7uF #1

VS1

4.7uF/0402/6.3V/X5R

≥ 0.84uF #1

Note #1: Total CIN Value @ 5V derating for AC 0.01Vrms and overall operating temperature. L_PWR1

VSYS

PMIC VSYS_BUCK

CIN 1

GND_BUCK L_GND1

CONFIDENTIAL B

Schematic/Layout Notice Buck Input Cap. Layout Spec. #1

▪ MMD spec  The spec. of trace parasitic inductance from buck input cap Input Trace to PMIC Ball MT6359 Spec. for Inductance BUCK (from C to IC ball) ▪ (L_PWR1 + L_GND1) < Spec VSYS_VS1 IN1

VS1

L_PWR1

VSYS

PMIC

GND_BUCK L_GND1

CONFIDENTIAL B

(L_PWR1 + L_GND1) ≤ 2nH

VS2

VSYS_VS2 GND_VS2

(L_PWR1 + L_GND1) ≤ 2nH

VPA

VSYS_VPA GND_VPA

(L_PWR1 + L_GND1) ≤ 1.5nH

VMODEM

VSYS_VMODEM GND_VMODEM

(L_PWR1 + L_GND1) ≤ 1nH

VPROC1

VSYS_VPROC1 GND_VPROC1

(L_PWR1 + L_GND1) ≤ 1nH

VPROC2

VSYS_VPROC2 GND_VPROC2

(L_PWR1 + L_GND1) ≤ 1nH

VCORE

VSYS_VCORE GND_VCORE

(L_PWR1 + L_GND1) ≤ 1nH

VGPU11

VSYS_VGPU11 GND_VGPU11

(L_PWR1 + L_GND1) ≤ 1nH

VGPU12

VSYS_VGPU12 GND_VGPU12

(L_PWR1 + L_GND1) ≤ 1nH

VPU

VSYS_VPU GND_VPU

(L_PWR1 + L_GND1) ≤ 2nH

VSYS_BUCK CIN 1

GND_VS1

Schematic/Layout Notice Buck Input Cap. Layout Spec. #2

▪ MMD spec  the spec of trace parasitic inductance from CIN2 to CIN1 ▪ (L_PWR2 + L_GND2) < Spec

VSYS

L_PWR2

L_PWR1

PMIC VSYS_BUCK1

CIN 1

GND_BUCK1 L_GND2

L_GND1

CIN 2

L_PWR2

L_PWR1

VSYS_BUCKn CIN 1

GND_BUCKn L_GND2

L_GND1

CONFIDENTIAL B

MT6359 Buck Name

Input Trace (from CIN2 to CIN1)

Spec. for Inductance

VS1 VS2 VPU VPROC2

CIN2 to CIN1

(L_PWR2 + L_GND2) ≤ 1.7nH

VGPU11 VGPU12 VMODEM VCORE VPROC1

CIN2 to CIN1

(L_PWR2 + L_GND2) ≤ 1.4nH

Schematic/Layout Notice Buck Input Cap. Layout Spec. #3

▪ MMD spec  the spec of trace parasitic inductance from CIN3 to CIN2 ▪ (L_PWR3 + L_GND3) < Spec VSYS

Sub-PMIC

L_PWR3

PMIC

L_PWR2

L_PWR1

VSYS

VSYS_BUCKx CIN 3

CIN 2

CIN 1

GND

GND_BUCKx L_GND3

CONFIDENTIAL B

L_GND2

L_GND1

Input Trace (from CIN3 to CIN2)

Spec. for Inductance

CIN3 to CIN2

(L_PWR3 + L_GND3) ≤ 2.5nH

Schematic/Layout Notice Layout Guide (1/2)

▪

Inductance need to follow application notice that has components selection guide.

▪

Placement, layout and schematic need to follow checklist.

Buck input cap detail layout rule, please refer to next page. CONFIDENTIAL B

Schematic/Layout Notice Layout Guide (2/2)

▪

Inductance need to follow application notice that has components selection guide.

▪

Placement, layout and schematic need to follow checklist.

Example 1 PMIC Buck GND ball

Example 2

Input Cap GND pad

PMIC Buck GND ball

Layer-1

Input Cap GND pad

Layer-1 GND return path

Layer-2

Layer-2 Solution 2

Solution 1

GND return path

Layer-3

Layer-3

Layer-5

Layer-5

Main-GND Layer

Main-GND Layer

CONFIDENTIAL B

Solution 2

Solution 1

Schematic/Layout Notice

Controller power trace layout constraint Bat. connector

Buck Input

GND

BAT_BUS

22uF

4mil

Buck controller power trace(VSYS_SMPS) must be use single trace connect to battery VBAT_BUS directly, and can’t merge with others. VSYS add 1Ω+/-5% Resistor to VSYS_SMPS CONFIDENTIAL B

Schematic/Layout Notice

Layout Guide 1/5: Remote Sense Application ▪

DC/DC remote sense feedback traces are recommended using GND shielding to avoid noise coupled.

CONFIDENTIAL B

Schematic/Layout Notice

Layout Guide 2/5: Remote Sense Application ▪

DC/DC remote sense feedback & feedback_GND traces are recommended using GND shielding and differential pair to avoid noise coupled.

CONFIDENTIAL B

Schematic/Layout Notice

Layout Guide 3/5: Remote Sense Application Cout1

Rc1

L1

L4

Remote pt.1

Cout2

R_remote spec (Follow MMD SPEC)

Lout

Rc2

PMIC L3

SOC

L2 Cout3

Rc3 1. 2.

Find path with lowest inductance, the remote point can be located within Coutlowest L + 1n. For example, in case of Cout1 is path with lowest inductance. • Inductance between Cout1 and Remote pt. 1 is L4, L4 must be lower than 1n (L4 < 1n). • The remote point location can be between Cout1 and Remote pt. 1. 3. Same case apply to L2 & L3 if they are lowest inductance path. 4. Above case is for multi-path, in case of single path, consider the only path as the lowest inductance path directly. 5. Inductance between Cout1 and other Cout(Cout2/Cout3) must be lower than 1.5n (L1+L2 6mil

▪ Detail layout constraint please refer per project. CONFIDENTIAL B

Layout Constraint of LDO #5

Rough Guidelines-use from CAD Extraction w (mil) 4

w (um) 101.6

h (um) 50

t @ 1/3 oz (um) 12

L (nH) = 4.85 nH ×

len (cm) 1.27

trace inductance (nH) 4.85

trace resistance (mΩ) 198

101.6 um len h × × w 1.27 cm 50um

101.6 um len R (mΩ) = 198 mΩ × × w 1.27 cm

where w = 4mil~40mil

Parameter Dielectrically constant Conductivity CONFIDENTIAL B

Value 4.0 5.8e7 s/m

w = trace width len = trace length t = trace thickness h = dielectric height

Layout Constraint of VREF ▪

VREF bypass cap as close as possible to PMIC

▪

GND_VREF pin must first connect to capacitor GND pin and then connect to system GND by VIA

▪

VREF cap is 100nF.

CONFIDENTIAL B

Layout Constraint of VIO18 ▪ Keep star-connection from PMIC VIO18_PMU to import 1.8V power domain. AP Peripheral PMIC MT6359

AVDD18_xx

VIO18_PMU

DVDD18_xx

Peripheral device I/O

CONFIDENTIAL B

Layout Constraint of VUSB Priority1 -The de-coupled cap should be put closed to AVDD30_AUD/ AVSS30_AUD and AVDD18_CODEC / AVSS30_AUD - The trace width should be >10mil - Connecting AVSS30_AUD to the main GND through at least one via - Connecting AVDD30_AUD from pad VUSB directly , then do a star connect from AVDD30_AUD to VUSB_PMU.

CONFIDENTIAL B

AP ANALOG POWER PCB LAYOUT CONSTRAINT

CONFIDENTIAL B

AP Analog Power List Voltage

PMIC Pin Name

AP analog pin name

VIO18

AVDD18_USB AVDD18_APPLLGP AVDD18_MDPLLGP AVDD18_UFS AVDD18_CKSQ AVDD18_DRF AVDD18_WBG

VIO18_PMU_AVDD

VA12

AVDD12_CSI AVDD12_APPLLGP AVDD12_UFS AVDD12_WBG

VA12_ABB1_PMU

1.2V

VRF12

AVDD12_SSUSB AVDD12_CKSQ AVDD12_DRF AVDD12_DRF ( RF IC ) AVDD12_DSI AVDD12_MDPLLGP AVDD12_GPPLLGP AVDD12_USB AVDD12_DDR

VA12_ABB2_PMU

1.2V

VBBCK

AVDD12_CKBUF_UFS

VBBCK_PMU

0.75V

VSRAM_OTHERS

AVDD04_DSI

DVDD_VSRAM_OTHERS

3.07V

VUSB

AVDD33_USB

VUSB_PMU

1.8V

1.2V

CONFIDENTIAL B

AP Analog Layout Constraint 

AVDD18_xxx layout constraint

Star-connection analog power group, AVDD18_SOC by short-pad on VIO18 cap.  Please be sure to follow “reference design” & “PMIC MMD” 

Follow PMIC MMD PMIC



IR spec.



Total path from PMIC LDO pin to AVDD power pin of AP-site



Target IR < 2%  For each AVDDXX_XXX path  Simulate all power pin currents at the same time CONFIDENTIAL B

AP AVDD18_xxx Layout Guideline 1 Follow MMD AVDD18_xxx1

Others …

Cnx AVDD18_xxx2 Cnx

VIO18_PMU

PMIC

AVDD18_xxx3 Cnx

AP

VIO18 AVDD18_SOC

C1

SHORT PAD

P1

AVDD18_xxx5

Notice 1. PCB drop voltage ≦ 36mV (PMIC VIO18 ball to AP AVDD18_xxx ball) 2. PCB Length/Width ≦ PCB Ratio Example Trace Trace 1 Trace 2 Trace 3

Trace Start PMIC VIO18 ball C1 P1

Trace End C1 P1 AP AVDD18_XXX ball

CONFIDENTIAL B

AVDD18_xxx4 Cnx Cnx AVDD18_xxx6 Cnx

Average current 0.600A 0.150A 0.040A

PCB Width 20mil 12mil 8mil

PCB Length 180mil 1100mil 300mil

PCB Ratio Length/Width 9 92 38

PCB PCB PCB drop Thickness Resister voltage 0.3oz 16.0mΩ 9.6mV 0.3oz 162.6mΩ 24.4mV 0.3oz 66.5mΩ 2.7mV

Pass ≦36mV

AP VA12  AVDD12_xxx Layout Guideline Follow MMD AVDD12_xxx1 Cnx AVDD12_xxx2 Cnx

PMIC

Cnx

AVDD12_xxx3

AP

VA12 C1 P1

AVDD12_xxx4 Cnx AVDD12_xxx5 Cnx

Notice 1. PCB drop voltage ≦ 24mV (PMIC VA12 ball to AP AVDD12_xxx ball) 2. PCB Length/Width ≦ PCB Ratio Example Trace Trace 1 Trace 2 Trace 3

Trace Start PMIC VA12 ball C1 P1

Trace End C1 P1 AP AVDD12_XXX ball

CONFIDENTIAL B

AVDD12_xxx6 Cnx

Average current 0.250A 0.250A 0.140A

PCB Width 24mil 24mil 12mil

PCB Length 240mil 800mil 200mil

PCB Ratio Length/Width 10 33 17

PCB Thickness 0.3oz 0.3oz 0.3oz

PCB Resister 17.7mΩ 59.1mΩ 29.6mΩ

PCB drop voltage 4.4mV 14.8mV 4.1mV

Pass ≦24mV

AP VRF12  AVDD12_xxx Layout Guideline Follow MMD

AVDD12_xxx1 Cnx AVDD12_xxx2 Cnx

PMIC

Cnx

AVDD12_xxx3

AP

VRF12 C1

AVDD12_xxx4

P1

Cnx AVDD12_xxx5 Cnx AVDD12_xxx6 Cnx

Notice 1. PCB drop voltage ≦ 24mV (PMIC VRF12 ball to AP AVDD12_xxx ball) 2. PCB Length/Width ≦ PCB Ratio Example Trace Trace Start Trace End Trace 1 PMIC VRF12 ball C1 Trace 2 C1 P1 Trace 3 P1 AP AVDD12_XXX ball CONFIDENTIAL B

Average PCB PCB current Width Length 0.250A 24mil 240mil 0.200A 24mil 800mil 0.050A 8mil 200mil

Cnx

AVDD12_DRF

RF

P2

PCB Ratio Length/Width 10 33 25

PCB Thickness 0.3oz 0.3oz 0.3oz

PCB Resister 17.7mΩ 59.1mΩ 44.3mΩ

PCB drop voltage 4.4mV 11.8mV 2.2mV

Pass ≦24mV

AP VRF12  AVDD12_xxx Layout Guideline Follow MMD

AVDD12_xxx1 Cnx AVDD12_xxx2 Cnx

PMIC

Cnx

AVDD12_xxx3

AP

VRF12 C1

AVDD12_xxx4

P1

Cnx AVDD12_xxx5 Cnx AVDD12_xxx6 Cnx

Cnx P2

Notice: refer to RF IC design notice

CONFIDENTIAL B

AVDD12_DRF

RF

AP AVDD12_CKBUF_UFS Layout Guideline Follow MMD

VBBCK

Cnx

AVDD12_CKBUF_UFS

AP C1

P1

Notice 1. PCB drop voltage ≦ 24mV (VBBCK ball to AP AVDD12_CKBUF_UFS ball) 2. PCB Length/Width ≦ PCB Ratio Example Trace Trace 1 Trace 2 Trace 3

Trace Start PMIC VBBCK C1 P1

Trace End C1 P2 AP AVDD12_XXX ball

CONFIDENTIAL B

Average PCB PCB current Width Length 0.020A 8mil 240mil 0.020A 8mil 800mil 0.020A 8mil 200mil

PCB Ratio Length/Width 30 100 25

PCB Thickness 0.3oz 0.3oz 0.3oz

PCB Resister 53.2mΩ 177.4mΩ 44.3mΩ

PCB drop voltage 1.1mV 3.5mV 0.9mV

Pass ≦24mV

AP AVDD04_DSI Layout Guideline Follow MMD Others

VSRAM_OTHERS Cnx Cnx

C1

AVDD04_xxx

AP AVDD04_xxx

P1

Notice 1. PCB drop voltage ≦ 15mV (VSRAM_OTHERS ball to AP AVDD04_xxx ball) 2. PCB Length/Width ≦ PCB Ratio Example Trace Trace 1 Trace 2

Trace Start C1 P1

CONFIDENTIAL B

Trace End P1 AP AVDD04_XXX ball

Average current 0.040A 0.040A

PCB PCB PCB Ratio PCB Width Length Length/Width Thickness 12mil 1000mil 83 0.3oz 8mil 120mil 15 0.3oz

PCB Resister 147.8mΩ 26.6mΩ

PCB drop voltage 5.9mV 1.1mV

Pass ≦15mV

AP AVDD33_USB Layout Guideline AP

PMIC VUSB

Cnx

AVDD33_USB

C1

Notice 1. PCB drop voltage ≦ 60mV (PMIC VUSB ball to AP AVDD33_USB ball) 2. PCB Length/Width ≦ PCB Ratio Example Trace Trace Start Trace 1 PMIC VUSB ball Trace 2 C1

Trace End C1 AP AVDD33_USB ball

CONFIDENTIAL B

Average PCB PCB current Width Length 0.060A 8mil 200mil 0.050A 8mil 2500mil

PCB Ratio Length/Width 25 313

PCB Thickness 0.3oz 0.3oz

PCB Resister 44.3mΩ 554.3mΩ

PCB drop voltage 2.7mV 27.7mV

Pass ≦60mV

SPI

CONFIDENTIAL B

Layout Constraint of PMIC SPI ▪ All traces of PMIC SPI bus should be well-shielded by nearby ground traces in the same layer, and surrounded by ground traces in n-1 and n+1 layers, and closed to each others. ▪ All traces of SPI bus should be far away from noisy sources, such as VBUS (plug-in spike), Buck switching node..etc.

▪ The max. length of SPI bus between SOC and MT6359 should be shorter than 6 inches (consider 6 inches = 1ns).

CONFIDENTIAL B

RTC

CONFIDENTIAL B

Layout Constraint of VRTC ▪

VRTC: Application circuit (2 options) ▪

0.1uF

▪

0.1uF + 1.5kΩ + super cap



0.1uF cap MUST and be close to PMIC Noted: Follow Ref. Vcoin=22uF if customers don’t want FG re-define initial SOC at the scenario below

CONFIDENTIAL B

Scenario: Plug in charger then press power key over 15sec. Due to sub-PMIC would disable power MOS between VBAT to VSYS and stop charging, VRTC would drop at Vcoin=0.1uF after VSYS decreased. After that, FG will re-define initial SOC due to RTC disappeared

92

Schematics Design Notice •

RTC32K_CK trace length must be controlled within 2000mil.

[A] [B]

[C] • • •

• •

0.1uF for VRTC is a must. [A] Recommend implementing 10~100uF for VRTC. MTK recommend implement 22uF, Smaller capacity sustains shorter time. Please do not use Gold Cap. because of the time when removed the Main battery precision: +-1.5 sec every 30 sec. [B] For battery un-replaced system design, R8201(1.5K) and C8202(22uF) can be removed for eBOM optimized. [B] RTC32K_CK such as a clock signal, needs well ground shielding. [C] Noted: Follow Ref. Vcoin=22uF if customers don’t want FG re-define initial SOC at the scenario below

Scenario: Plug in charger then press power key over 15sec. Due to sub-PMIC would disable power MOS between VBAT to VSYS and stop charging, CONFIDENTIAL B 93 VRTC would drop at Vcoin=0.1uF after VSYS decreased. fine initial SOC due to RTC disappeared

Content ▪ ▪ ▪ ▪

MT6359 Introduction Function Description Function Block Notice PCB Layout Guideline

CONFIDENTIAL B

Package Outline of MT6359

CONFIDENTIAL B

Ballmap of MT6359 202

1

2

3

4

5

6

7

8

A

NC

VRF12

VS2

VSYS_VS2

VSYS_VPA

VPA

VSYS_VPU

VPU

GND_VMODE VSYS_VMOD VSYS_VPROC VMODEM M EM 2

VPROC2

GND_VPROC VSYS_VPROC VSYS_VPROC A 2 1 1

B

VRF12_S

VA12

VS2

GND_VS2

GND_VPA

VPA

GND_VPU

VPU

GND_VMODE VSYS_VMOD VSYS_VPROC VMODEM M EM 2

VPROC2

GND_VPROC 2

C

VCN13

VS2_LDO2

VA09

VSYS_SMPS

VS2_FB

GND_SMPS

VPA_FB

GND_VPU_F B

D

VSRAM_MD VS2_LDO1

E

AU_V18N

F

FLYN

G

FLYP

VSRAM_PRO VSRAM_othe EXT_PMIC_P EXT_PMIC_E EXT_PMIC_E C1 rs G N2 N1

VSRAM_PRO C2

AVSS18_AUD

RESETB

GND

GND

9

VPU_FB

PWRKEY

10

11

CHRDETB

PMU_TESTM ODE

SPI_CLK

GND

GND

GND

LDO

E

XXX

AUDIO

VSYS_VGPU1 VSYS_VGPU1 F 2 2

XXX

DCXO

SRCLKEN_IN VSYS_VGPU1 VSYS_VGPU1 VGPU11_FB G 1 1 1

XXX

STRUP/PCHR_VREF

H

XXX

AUXADC/ FGADC

RTC32K_1V8 GND_VGPU1 GND_VGPU1 GND_VGPU1 WDTRSTB_IN J _1 1_FB 1 1

XXX

Digital IO

SPI_CSN

GND

SPI_MOSI

AU_HPR

AU_REFN

AUD_NLE_M AUD_DAT_M OSI1 ISO1

GND

GND

GND

FSOURCE

AU_HPL

AUD_DAT_M AUD_CLK_M ISO0 OSI

AU_HSP

AUD_DAT_M AUD_DAT_M OSI0 ISO2

DVSS18_IO

K

AVDD18_CO DEC

HP_EINT

ACCDET

AUD_DAT_M AUD_DAT_M OSI1 OSI2

DVDD18_DIG DVDD18_IO

L

AU_VIN0_P AU_VIN0_N AU_VIN3_N AU_VIN3_P

M

AU_VIN1_P AU_VIN2_P

AU_MICBIAS AU_MICBIAS 1 2

BATADC_P

CS_P

AUXADC_VIN 1

XO_WCN

AVSS_XO_IS AU_VIN1_N AU_VIN2_N AVSS_RFCK AVSS_BBCK O

SPI_MISO

VGPU12

VPROC1_FB

RTC32K_1V8 SRCLKEN_IN _0 0

AVSS18_AUX ADC

VAUX18

VFE28

SCP_VREQ_V AO

VGPU11

VGPU12

VGPU11

GND_VCORE GND_VCORE GND_VCORE K _FB

CS_N

GND_VREF

VREF

VRTC28

VIBR

VSYSSNS

BATON

UVLO_VTH

VIO28

VCAMIO

VAUD18

VEFUSE

VM18

VS1_LDO1

VS1_LDO2

VCORE

VCORE

VS1

VS1

N

VS1_FB

GND_VS1

VSYS_VS1

P

R

XTAL1

AVSS_XO

VRFCK_1

XO_CEL

VBBCK

XO_EXT

VUSB

VSIM1

R

AVSS_XO

XTAL2

VXO22

VRFCK

XO_SOC

XO_NFC

VBIF28

VSIM2

VEMC

VCN33_1

VCN33_2

VUFS

VCN18

VRF18

VIO18

NC

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

CONFIDENTIAL B

L

VCORE_FB VSYS_VCORE VSYS_VCORE M

P

VSYS_LDO2 VSYS_LDO1

B

XXX

GND

AU_HSN

VPROC1

GND_VPROC GND_VGPU1 GND_VGPU1 D 1_FB 2 2

VPROC2_FB

HOMEKEY

GND

AVDD30_AU AVSS30_AUD D

VPROC1

16

BUCK

AUD_NLE_M AUD_SYNC_ OSI0 MOSI

J

15

XXX

AU_LOLN

AVDD18_AU D

14

GND_VPROC GND_VPROC C 1 1

AU_LOLP

AU_MICBIAS 0

13

GND_VMODE GND_VPROC VMODEM_FB M_FB 2_FB

H

N

12

Layout: MT6359 Power Input (1/2) VSYS Input 

Routing from 22uF VSYS capacitor uses start topology to connect to each device. 1. Input for BUCK. (Fig. 2) 2. Input for LDO. (Fig. 2)



All the decoupling capacitors should be placed near MT6359. The priority is buck capacitor then decoupling capacitor of LDO. (Fig.1)

Fig. 1

MT6359

CONFIDENTIAL B

Fig. 2

Layout: MT6359 Power Input (2/2)  Layout method of MT6359 power Input for Buck GND

Fig.1

-

Buck GND balls are connected to buck capacitors close to pin with plane or trace (Trace Width > 8mil * N (ball number) + M (ball pitch)). (Fig.1~2)

-

Buck GND balls should be connected to buck capacitors first and isolated from the nearby GND trace and plane then connected to main GND at L3 (Fig.1~2).

Fig.2

MT6359

CONFIDENTIAL B

BUCK GND is isolated from nearby GND trace and plane.

Layout: MT6359 Buck Output (1/2) Fig.2 

The buck inductors should be placed near MT6359. (Fig.1)

Fig.1

MT6359

CONFIDENTIAL B

Layout: MT6359 Buck Output (2/2) 

Those signals are differential pairs and should be shielded by GND and far away from noise signals (Fig.1 ~ Fig.2). 1. VPROC1_FB/GND_VPROC1_FB 2. VPROC2_FB/GND_VPROC2_FB 3. VCORE_FB/GND_VCORE_FB 4. VPU_FB/GND_VPU_FB Fig. 1 5. VGPU11_FB/GND_VGPU11_FB 6. VMODEM_FB/GND_VMODEM_FB 7. VS1_FB, VS2_FB, VPA_FB

Fig. 2

CONFIDENTIAL B

Layout: MT6359 Buck/LDO Output ▪

Layout guideline for MES simulation.

MT6359

Application

Resistance (PMIC to SoC power ball)

VSRAM_PROC1

DVDD_SRAM_PROC_B

≤ 75 mΩ

VSRAM_PROC2

DVDD_SRAM_PROC_L

≤ 110 mΩ

VSRAM_OTHERS

DVDD_SRAM_OTHERS

≤ 85 mΩ

VSRAM_MD

DVDD_SRAM_GPU

≤ 110 mΩ

VPROC1

DVDD_GPU

≤ 18 mΩ

VPROC2

DVDD_PROC_L

≤ 24 mΩ

VCORE

DVDD_CORE

≤ 16 mΩ

VGPU11 // VGPU12

DVDD_PROC_B

≤ 14 mΩ

CONFIDENTIAL B

Layout: MT6359 LDO Output (1/2) 

See table. for the suggested LDO output layout.

1. Trace width≧6mil 2. Value and placement of capacitor please refer design notice Ball name VFE28 VAUX18 VBIF28 VCN33_1 VCN33_2 VIO28 VEMC VSIM1 VSIM2 VIBR VUSB VEFUSE VAUD18 VCAMIO VM18 VUFS VCN18 VRF18 VIO18 VCN13 VRF12 VA12 VA09

Imax 200mA 50mA 50mA 800mA 800mA 200mA 800mA 200mA 200mA 200mA 200mA 300mA 300mA 300mA 300mA 1200mA 1200mA 450mA 600mA 350mA 800mA 300mA 300mA

CONFIDENTIAL B

Trace Length 1500mil 1500mil 1500mil 1500mil 1500mil 1500mil 1500mil 1500mil 1500mil 1500mil 1500mil 1000mil 1500mil 1500mil 900mil 1200mil 1500mil 1500mil 1500mil 1500mil 1500mil 1200mil 1200mil

Trace Width 6mil 6mil 6mil 25mil 25mil 10mil 25mil 10mil 10mil 6mil 8mil 12mil 12mil 6mil 25mil 25mil 8mil 20mil 20mil 25mil 25mil 20mil 20mil

Rpcb H=50um, 1/3 oz 400mΩ 400mΩ 400mΩ 100mΩ 100mΩ 240mΩ 100mΩ 240mΩ 240mΩ 400mΩ 300mΩ 135mΩ 200mΩ 400mΩ 60mΩ 80mΩ 300mΩ 120mΩ 120mΩ 100mΩ 100mΩ 100mΩ 100mΩ



Core power/DRAM power/AVDDxx power: 



VRF18/VRF12/VRF12_S: •



Traces should be in inner layer or under shielding case.

VRF12_S: 



Follow MMD/MES

VRF12_S should connect to VRF12 application

Trace width/length can adjust by application Imax

If trace is series 0Ω resister, 0Ω resister is having 0~50mΩ variation. It would be drop voltage.

Layout: MT6359 LDO Output (2/2) 

VREF capacitor should be placed near L12/L11 pin.



DVDD18_DIG capacitor should be placed near K10 pin.

MT6359

CONFIDENTIAL B

Layout: Others for MT6359 Gauge

CS_P/CS_N (ball: L9/L10) should be routed as differential pairs and far away from noise signals.

MT6359 DCXO_32K

CS_P CS_N

CONFIDENTIAL B

MT6359 Audio PCB Layout Guide 

MT6359 Audio PCB Layout Guide Please refer “MT6853_Baseband_Design_Notice“

CONFIDENTIAL B

MT6359 AuxADC/DCXO PCB Layout Guide 

MT6359 AUXADC /DCXO PCB Layout Guide Please refer “MT6853_Baseband_Design_Notice“

CONFIDENTIAL B

Chip Placement Recommendation  Following PCB layout are recommended by MTK for WLCSP (MT6359 / MT6315 / MT6360) WLCSP 請注意週邊的 IC 1. Opposite shield frame could not overlap package balls

2. The opposite chip (especially large chip, ex. AP & eMCP) could not overlap package balls 3. If underfill was adopted, the properties were recommended : - CTE-1 < 30 ppm/˚C, Tg > 125 ˚C

CONFIDENTIAL B

How to Connect for Un-used Pin Unused Part Interface

General

Gauge DCXO

Pin Connection if not used EXT_PMIC_ENx Ext chip enable pin Floating HOMEKEY button with default long press function Short to GND HOMEKEY HOMEKEY button without default long press function Floating 1. Short to GND while RU=NC BATON Battery NTC pin for battery and its temperature sensing 2. Pull-Low 10KΩ to GND while RU exist BATADC Fuel gauge ADC input pin for monitoring battery voltage VBAT CS_N Fuel gauge ADC input pin GND CS_P Fuel gauge ADC input pin GND XO_NFC 26MHz output to NFC Floating XO_EXT 26MHz output to UFS or others Floating Pin Name

CONFIDENTIAL B

Description

UFS2.1 / UFS3.0 Power configuration  UFS long term power plan required 2.5V/3.0V 1. PMIC VEMC LDO add 2.5V/3.0V HW trapping for UFS2.0/UFS3.0 2. UFS3.0 needs 1.2V requirement should find ext. Buck/LDO and needs VIO18 enable for satisfied UFS sequence 3. UFS sequence: a. Power on sequence: 1.8V(VUFS18)  1.2V(Ext.)  3.0V(VEMC) b. Power off sequence: 3.0V(VEMC)  1.2V (Ext.)  1.8V(VUFS18)

CONFIDENTIAL B

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