MT6360 PMIC Datasheet [1.1 ed.]
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English Pages 210 Year 2019
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MT6360 PMIC Datasheet
Version: Release date:
1.1 2019-05-24
Specifications are subject to change without notice.
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited
MT6360 PMIC Datasheet Confidential A
Document Revision History Revision 0.1
Date 2018-03-13
Author JW Lin
0.2
2018-08-30
JW Lin
MediaTek Confidential
Description First edition Features Page 6, 7 -Modified Charger, Flash, LDO, RGB, Moonlight and Buck contents General Descriptions Page 9 -Modify Buck & LDO descriptions Pin Assignments Page 12 -Updated and typo PD_CC2, PD_VBUS, BUCK1_VOUT Table 1-1 Pin descriptions Page 12 to 14 -Updated and Modified Figure 1-2 Application circuit Page 15 -Add D7, D8 and Modify Buck net name Absolute Maximum Ratings Page 16 -Updated and Modified Recommended Operation Range Page 17 -Update and Modified Electrical Characteristics Page 18 to 31 -Update and Modified Application Information Page 32 to 77 -Corrected general descriptions for six LDOs -Modified VDDA OVP contents -Updated OTP descriptions -Updated MRSTB function -Modified Charger Mode Operation contents -Modify OTG mode Operation descriptions -Corrected Shipping Mode contents -Corrected Interrupt contents -Updated ADC Conversion Operation Flow -Add FLED Power Control -Add FLED Core Control -Add LDO Application Reference -Add SD_CARD_DET_N Pin -Modified Layout Considerations contents -Removed Top Layer PCB layout guide Functional Descriptions Page 78 to 83 -Modified CHRDETB pin name -Corrected Table 4-1 Control pin description -Corrected Table 4-2 Channel is unused table -Modified Table 4-3 BOM list -Modified Table 4-4 Protection list Register Table and Descriptions Page 84 to 207 -Modified PMU Part Register Detail Description Page 84 to 135 -Modified PMIC Part Register Detail Description Page 136 to 157 -Modified LDO Part Register Detail Description Page 158 to 173 -Modified PD Part Register Detail Description Page 174 to 207 Outline Dimensions Page 208 -Updated package dimensions © 2018 - 2019 MediaTek Inc.
This document contains information that is proprietary to MediaTek Inc.
Page 2 of 210
MT6360 PMIC Datasheet Confidential A Revision
Date
Author
0.3
2018-10-25
JW Lin
0.4
2018-11-01
JW Lin
0.5
2018-11-09
JW Lin
0.6
2018-12-14
JW Lin
MediaTek Confidential
Description Features Page 7, 8 -Modified and Typo General Descriptions Page 10 -Modified Electrical Characteristics Page 23, 27, 28, 29, 30, 31, 32 -Updated and Modified Application Information Page 68 -Corrected FLED Power Control Register Table and Descriptions -Modified PMU Part Register Detail Description Page 85, 87, 88, 96, 97, 102, 103, 105, 117, 119, 124, 125, 131, 132, 133 -Modified PMIC Part Register Detail Description Page 137, 139, 140, 141, 144, 145, 149, 151, 152, 155, 156 -Modified LDO Part Register Detail Description Page 161, 165, 168, 171 -Modified PD Part Register Detail Description Page 206 Recommended Operation Range Page 18 -Updated and Modify Electrical Characteristics Page 31 -Updated and Modify Register Table and Descriptions -Modified PMU Part Register Detail Description Page 104, 105 -Modified PMIC Part Register Detail Description Page 152, 155, 156 -Modified LDO Part Register Detail Description Page 161, 165, 167, 168, 171 Functional Descriptions Page 84 -Modified table 4-4 Protection list Features Page 7 -Modified and Typo LDO General Descriptions Page 10 -Modified Buck & LDO descriptions Pin Assignments Page 14 -Typo FAULTB Figure1-2 application circuit Page 16 -Added C30 and Modified C16, another PMIC, VDDIO Electrical Characteristics Page 29, 30, 31 -Updated and Modified Buck, LDO Functional Descriptions Page 81, 82, 84 -Modified table 4-4 Protection list -Modified table 4-3 BOM list Register Table and Descriptions Page 117 -Modified PMU Part Register Detail Description Features Page 9 -Typo RGB Pin Assignments Page 15 -Modified SRCLKEN_0 Figure 1-2 Typical Application Circuit Page 17 -Modified LDO7_VOUTS Electrical Characteristics Page 21, 23, 24, 27 -Updated and Modify EOC, QONB, USB_ID Application Information Page 46, 47, 48, 51, 52 -Add Power-Up from CHG_VIN -Corrected ADC
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Page 3 of 210
MT6360 PMIC Datasheet Confidential A Revision
Date
Author
0.7
2019-01-31
JW Lin
1.0
2019-02-27
JW Lin
1.1
2019-05-24
JW Lin
MediaTek Confidential
Description Functional Descriptions Page 85 --Modify table 4-4 Protection list Register Table and Descriptions -Modified PMU Part Register Detail Description Page 106, 127, 134 -Modified PMIC Part Register Detail Description Page 143, 145, 146, 147, 149, 150, 154 General Description Page 11 -Typo RGB 20mA change to 24mA Pin Assignments Page 15 -Modified CHG_VDDP Electrical Characteristics Page 20, 30, 31 - Added L1, L2 -Modified typo BUCK1, BUCK2 supply current Application Information Page 40, 41, 42, 43, 46, 55, 74 -Modified Functional Descriptions Page 83 -Modified functional block diagram Functional Descriptions Page 86 -Modified table 4-3 BOM list Register Table and Descriptions -Modified PMU Part Register Detail Description Page 112 -Modified PMIC Part Register Detail Description Page 141 Typical Operating Characteristics Page 34 - Added Typical Operating Characteristics Typical Operating Characteristics Page 34 - Typo and corrected to VBAT 4.35V Application Information Page 70 -Updated 2.3V to 2.7V Functional Descriptions Page 86 -Typo and modified table 5-3 BOM list
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Page 4 of 210
MT6360 PMIC Datasheet Confidential A
Table of Contents Document Revision History ......................................................................................... 2 Table of Contents .........................................................................................................5 1 Overview............................................................................................................. 8 1.1 Features .....................................................................................................................................8 1.2 Applications ............................................................................................................................. 10 1.3 General Descriptions................................................................................................................11 1.4 Ordering Information ............................................................................................................. 12 1.5 Top Marking Definition .......................................................................................................... 13 1.6 Pin Assignments and Descriptions ........................................................................................ 14 1.7 Typical Application Circuit ..................................................................................................... 17 2 Electrical Characteristics ................................................................................... 18 2.1 Absolute Maximum Ratings ................................................................................................... 18 2.2 Recommended Operating Range ........................................................................................... 19 2.3 Electrical Characteristics ....................................................................................................... 20 3 Typical Operating Characteristics .......................................................................34 3.1 Typical Operating Characteristics ..........................................................................................34 4 Application Information..................................................................................... 35 4.1 General Descriptions...............................................................................................................35 4.2 VDDA Over-Voltage Protection..............................................................................................36 4.3 Over-Temperature Protection ................................................................................................ 37 4.4 MRSTB Pin ............................................................................................................................. 38 4.5 Switching Charger .................................................................................................................. 40 4.6 Charger Mode Operation ........................................................................................................ 41 4.7 OTG Mode Operation..............................................................................................................45 4.8 Shipping Mode ........................................................................................................................46 4.9 Power Up from CHG_VIN ...................................................................................................... 47 4.10 MediaTek Pump Express+ (MTK, PE+) ............................................................................... 50 4.11 Interrupt .................................................................................................................................. 51 4.12 CHG_VBATOVPB Pin.............................................................................................................52 4.13 Analog IR Drop Compensation .............................................................................................. 53 4.14 CHG_ILIM Pin ........................................................................................................................54 4.15 ADC Conversion Operation Flow ........................................................................................... 55 4.16 USB_PD ................................................................................................................................... 57 4.17 Type-C Detection.....................................................................................................................58 4.18 Detection through Autonomous DRP Toggles ......................................................................59 4.19 PD Protocol Communication................................................................................................. 60 4.20 FLED Flow Chart.....................................................................................................................62 4.21 Strobe Mode Operation ..........................................................................................................64 4.22 Torch Mode Operation............................................................................................................65 4.23 FL_TXMASK Function ...........................................................................................................66 4.24 FLED Short Protection ...........................................................................................................67 4.25 Input Capacitor Selection ...................................................................................................... 68 4.26 FLED Strobe Mode Supply Limit ...........................................................................................69 MediaTek Confidential
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Page 5 of 210
MT6360 PMIC Datasheet Confidential A 4.27 Low Battery Voltage Protection (LBP) ...................................................................................70 4.28 FLED Power Control ............................................................................................................... 73 4.29 FLED Core Control.................................................................................................................. 74 4.30 RGB LED Driver ...................................................................................................................... 75 4.31 Flash Mode ..............................................................................................................................76 4.32 Breath Mode ............................................................................................................................ 77 4.33 Register Mode .........................................................................................................................78 4.34 Low Dropout Regulator (LDOs) and Application Reference ................................................ 79 4.35 SD_CARD_DET_N Pin ......................................................................................................... 80 4.36 I2C Interface............................................................................................................................. 81 4.37 Thermal Considerations ........................................................................................................ 82 4.38 Layout Considerations ........................................................................................................... 83 5 Functional Descriptions .................................................................................... 84 5.1 General Descriptions.............................................................................................................. 84 5.2 Register Table and Descriptions ........................................................................................... 90 6 MT6360 Packaging .......................................................................................... 209 6.1 Outline Dimensions ............................................................................................................. 209 Appendix ................................................................................................................. 210
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Page 6 of 210
MT6360 PMIC Datasheet Confidential A Lists of Figures and Tables Figure 1-1. MT6360 WL-CSP-103B 4.64x4.14 (BSC) (top view) .............................................................. 14 Figure 1-2. Application circuit .................................................................................................................... 17 Figure 3-1. Typical operating characteristics ............................................................................................ 34 Figure 4-1. MRSTB function ...................................................................................................................... 38 Figure 4-2. MRSTB diagram ...................................................................................................................... 39 Figure 4-3. Charge profile ........................................................................................................................... 41 Figure 4-4. VDDM power plan....................................................................................................................47 Figure 4-5. IRQB pin diagram .................................................................................................................... 51 Figure 4-6. ADC conversion operation flow...............................................................................................55 Figure 4-7. Type-C port controller (TCPC) interface ................................................................................ 60 Figure 4-8. FLED flow chart ...................................................................................................................... 63 Figure 4-9. FLCS1_EN and FLCS2_EN (FL_STROBE) .......................................................................... 64 Figure 4-10. FLCS1_EN and FLCS2_EN (FL_STROBE_reg) ................................................................. 64 Figure 4-11. FLCS1_EN and FLCS2_EN (FL_TORCH) ........................................................................... 65 Figure 4-12. FLCS1_EN and FLCS2_EN (FL_TORCH_reg) ................................................................... 65 Figure 4-13. FL_TXMASK function .......................................................................................................... 66 Figure 4-14. Torch case (CHG_VIN < 5.6V) ............................................................................................. 70 Figure 4-15. Strobe case (CHG_VIN < 5.6V) ............................................................................................ 70 Figure 4-16. Torch case (CHG_VIN ≥ 5 .6V) ............................................................................................. 71 Figure 4-17. Strobe case (CHG_VIN ≥ 5.6V) ............................................................................................. 71 Figure 4-18. Torch case with OTG .............................................................................................................. 71 Figure 4-19. Strobe case with OTG .............................................................................................................72 Figure 4-20. FLED power control block diagram ......................................................................................73 Figure 4-21. FLED core control block diagram..........................................................................................74 Figure 4-22. RGB LED driver application circuit ......................................................................................75 Figure 4-23. RGB flash mode operating principle .................................................................................... 76 Figure 4-24. RGB breath mode operating principle .................................................................................. 77 Figure 4-25. RGB register mode operating principle ............................................................................... 78 Figure 4-26. I2C timing diagrams ...............................................................................................................81 Figure 4-27. Derating curve of maximum power dissipation .................................................................. 82 Figure 5-1. MT6360 functional block diagram ......................................................................................... 84 Figure 6-1. Package dimension ................................................................................................................ 209
Table 1-1. MT6360 pin descriptions ........................................................................................................... 14 Table 2-1. Electrical specifications............................................................................................................. 20 Table 4-1. CHRDETB status....................................................................................................................... 48 Table 4-2. Adapter detection...................................................................................................................... 49 Table 4-3. USB PD abbreviations .............................................................................................................. 60 Table 4-4. LDO types and brief specifications .......................................................................................... 79 Table 5-1. Control pin description ............................................................................................................. 85 Table 5-2. If a channel is unused, follow the setting instructions as below. ........................................... 85 Table 5-3. BOM list ..................................................................................................................................... 86 Table 5-4. Protection list ............................................................................................................................ 87 Table 5-5. PMU Part Register Detailed Description ................................................................................. 90 Table 5-6. PMIC Part Register Detail Description.................................................................................. 140 Table 5-7. LDO Part Register Detail Description.................................................................................... 160 Table 5-8. PD Part Register Detail Description ....................................................................................... 175
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Page 7 of 210
MT6360 PMIC Datasheet Confidential A
1
Overview
1.1
‒ Current Capability Definition and Detection
Features
Battery Charger ‒ High-Accuracy Voltage/Current Regulation ‒ Average Input Current Regulation (AICR): 0.1A to 3.25A in 50mA steps ‒ Charge Current Regulation Accuracy: ±5% ‒ Charge Voltage Regulation Accuracy: ±0.5% (0 to 70°C) ‒ Battery Temperature Sensing ‒ Synchronous 1.5MHz/1MHz/0.75MHz Fixed-Frequency PWM Controller with Up to 95% Duty Cycle ‒ Thermal Regulation and Protection ‒ Over-Temperature Protection ‒ Input Over-Voltage Protection ‒ IRQ Output for Communication via I2C ‒ Automatic Charging ‒ BATFET Control to Support Ship Mode, Wake Up, and Full System Reset ‒ Resistance Compensation from Charger Output to Cell Terminal ‒ USB OTG Output Voltage Range: 4.85V to 5.825V ‒ D+/D- Detection for BC1.2 ‒ Micro-B ID Pin Rust ‒ Integrated ADCs for System Monitoring (Charger Current, Voltage, and
Temperature) ‒ Low Battery Protection from 2.3V to 3.8V for Boost Operation ‒ Initial VOREG Set for Relieve Battery Protection DO1 Output Current: 150mA USB_PD ‒ PD-Compatible Dual-Role ‒ Attach/Detach Detection as Host, Device or Dual-Role Port MediaTek Confidential
‒ Cable Recognition ‒ Alternate Mode Supported ‒ Supports VCONN with Programmable Over-Current Protection (OCP) ‒ Dead Battery Support ‒ Ultra-Low Power Mode for Attach Detection (< 10mA) ‒ BIST Mode Supported ‒ USB PD3.0 Flash LED Driver ‒ Synchronous Boost Dual Flash LED Driver with Dual IndependentlyProgrammable LED Current Sources ‒ Torch Mode Current: from 25mA to 400mA in 12.5mA Steps per Channel ‒ I2C-Programmable Flash Safety Timer, from 64ms to 2432ms with 32ms/Step ‒ Flash LED1/LED2 Short-Circuit Protection, and Output Short-Circuit Protection ‒ TXMask Protection with Dedicated FL_TXMASK Pin ‒ Shared Charger/OTG as Power Stage ‒ Independent Torch Bypass MOSFET from VSYS ‒ Strobe Mode Current: 50mA to 1.5A in 12.5mA Steps or 25mA to 750mA in 6.25mA Steps per Channel, and Up to 2.5A in Total LDO ‒ 6-Channel LDO ‒ ‒ ‒ ‒
LDO2/3 Output Current: 200mA LDO5 Output Current: 800mA LDO6 Output Current: 300mA LDO7 Output Current: 600mA
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Page 8 of 210
MT6360 PMIC Datasheet Confidential A RGB LED Driver ‒ 3-Channel LED Driver ‒ Sink Current for 3 RGB LEDs: 24mA/Channel ‒ Flash Mode Frequency Range: 0.125Hz to 256Hz ‒ RGB_ISINK1 for CHG_VIN Power Good Indicator ‒ Support Register Mode, Flash Mode, and Breath Mode Moonlight LED Driver ‒ 5 to 150mA Sink Type LED driver ‒ Linear Mode Control ‒ 5mA/Step Buck ‒ 2-Channel Buck ‒ 0.3V to 1.3V Programmable Slew Rate for Voltage Transitions ‒ Output Current Capability: 3A ‒ Support Sequenced off Delay Time Selection ‒ Input Under-Voltage Lockout (UVLO) ‒ Thermal Shutdown and Overload Protection
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Page 9 of 210
MT6360 PMIC Datasheet Confidential A
1.2
Applications
Cellular Telephones Personal Information Appliances Tablet PCs Portable Instruments
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Page 10 of 210
MT6360 PMIC Datasheet Confidential A
1.3
General Descriptions
The MT6360 is a highly-integrated smart power management IC, which includes a single cell Li-Ion/Li-Polymer switching battery charger, a USB Type-C & Power Delivery (PD) controller, dual Flash LED current sources, a RGB LED driver, two Buck converters, and six LDOs for portable devices. The switching charger integrates a synchronous PWM controller, power MOSFETs, input current sensing and input current regulation, high-accuracy voltage regulation, and charge termination circuitry. Besides, the charge current is regulated through the integrated sensing resistors. It also features USB On-The-Go (OTG) support. The USB Type-C & PD controller complies with the latest USB Type-C and PD standards. It integrates a complete Type-C transceiver including the Type-C termination resistors, Rp and Rd, and enables the USB Type-C detection including attach and orientation. It also integrates the physical layer of the USB BMC power delivery protocol, allowing power transfers and role swaps. The BMC PD function provides full support for alternate modes on the USB Type-C standard.
Dual BUCK converter can deliver a digitally programmable output 0.3V to 1.3V from an input voltage supply of 2.5V to 5.5V. The output voltage is programmed through an I2C interface capable of operating up to 3.4MHz. By using a proprietary architecture with synchronous rectification, the BUCK1/2 are capable of delivering 3A continuously as PVIN > 3.1V. The LDO1 can be used to supply power to finger print unit (VFP). The LDO2 can be used to supply power to touch panel unit (VTP). The LDO3 and LDO5 can be used to supply power to SD card and UFS card (VMC & VMCH). The LDO6 and LDO7 can be used to supply power to a DRAM (VMDDR and VDRAM2). These are in mobile phones and other hand-held devices. The output voltage is programmable via the I2C interface. The RGB LED driver is a 3-Channel smart LED string controller to drive 3 channels of LEDs with a sink current of up to 24mA and a CHG_VIN power good indicator with a sink current of up to 24mA. All channels can be set independently via the I2C interface, and are provided with three operation modes: Register Mode, Flash Mode and Breath Mode. The MT6360 is available in a WL-CSP-103B 4.64x4.14 (BSC) package.
Dual independent current sources supply for each flash LED. The power for the current sources in strobe mode are from the CHG_VMID pin, which is supplied from the charger in reverse boost mode, the same operation as OTG mode of the charger. The high-side current sources, allowing for grounded-cathode connection for LEDs, provide strobe mode current levels from 50mA to 1.5A in a 12.5 mA step or from 25mA to 750mA in a 6.25mA step and t current levels from 25mA to 400mA in a 12.5mA step. The two channels can support totally up to 2.5A.
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Page 11 of 210
MT6360 PMIC Datasheet Confidential A
1.4
Ordering Information
MT6360 Package Type P : WL-CSP-103B 4.64x4.14 (BSC)
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Page 12 of 210
MT6360 PMIC Datasheet Confidential A
1.5
Top Marking Definition
MT6360P
$: Random code YYWW: Date code
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Page 13 of 210
MT6360 PMIC Datasheet Confidential A
1.6
Pin Assignments and Descriptions A1
A2
A3
A4
A6
A7
A8
A9
A10
A11
CHG_ VIN
CHG_ VIN
CHG_ VIN
CHG_ILIM
FL_ LEDCS2
FL_ LEDCS1
PD_CC2
PD_VBUS
RGB_ ISINK3
RGB_ ISINK1
B7
B8
B1
B2
B3
B5
B6
CHG_ VMID
CHG_ VMID
CHG_ VMID
FL_ VMID
FL_ VMID
PD_ FL_ VINTORCH VCONN5V
B9
B10
B11
PD_IRQB
ML_ ISINK
RGB_ ISINK2
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
CHG_ VLX
CHG_ VLX
CHG_ VLX
CHG_ VDDP
CHG_ BOOT
FL_ TXMASK
CHRDETB
PD_CC1
RGB_ PGND
LDO1_ VOUT
LDO2_ VOUT
D1
D2
D3
D5
D6
D8
D9
D10
D11
CHG_ PGND
CHG_ PGND
CHG_ PGND
FL_ TORCH
FL_ STROBE
AGND
SRCLKEN_0
LDO3_ VOUT
LDO_ VIN1
E1
E3
E5
E6
E7
E8
E9
E10
E11
VSYS
CHG_ VBATOVPB
AGND
AGND
AGND
AGND
EN
LDO6_ VOUT
LDO_ VIN2
F1
F2
F3
F4
F5
F6
F7
F8
F9
F11
VSYS
VSYS
VSYS
CHG_ ENB
AGND
AGND
AGND
AGND
MRSTB
LDO5_ VOUT
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
VBAT
VBAT
VBAT
IRQB
AGND
AGND
AGND
AGND
FAULTB
LDO7_ VOUTS
LDO7_ VOUT
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
VBAT
CHG_ QONB
UVLO_ SEL
VREF_ TS
SDA
SDCARD_ DET_N
BUCK2_ RSGND
BUCK2_ VOUT
BUCK1_ VOUT
BUCK1_ RSGND
LDO_ VIN3
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
J11
VBATS
TS
HW_ TRAPPING
USB_ID
SCL
BUCK2_ PGND
BUCK2_ LX
BUCK2_ PVIN
BUCK1_ PVIN
BUCK1_ LX
BUCK1_ PGND
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
VBATS_ GND
D-
D+
VDDA
VDDM
BUCK2_ PGND
BUCK2_ LX
BUCK2_ PVIN
BUCK1_ PVIN
BUCK1_ LX
BUCK1_ PGND
Figure 1-1. MT6360 WL-CSP-103B 4.64x4.14 (BSC) (top view)
Table 1-1. MT6360 pin descriptions Pin No. A1, A2, A3
Pin Name CHG_VIN
A4
CHG_ILIM
A6 A7
FL_LEDCS2 FL_LEDCS1
A8
PD_CC2
A9
PD_VBUS
A10 A11
RGB_ISINK3 RGB_ISINK1
B1, B2, B3
CHG_VMID
B5, B6
FL_VMID
B7 B8
FL_VINTORCH PD_VCONN5V
B9
PD_IRQB
B10 B11 C1, C2, C3
ML_ISINK RGB_ISINK2 CHG_VLX
MediaTek Confidential
Pin Description Charger power input. Input current limit setting pin. A resistor is connected from CHG_ILIM pin to ground to set the maximum input current limit. The actual input current limit is the lower value set through the CHG_ILIM pin and IAICR register bits. High-side current source output 2 for flash LED2. High-side current source output 1 for flash LED1. Type-C connector Configuration Channel (CC) 2. It is used to detect a cable plug event and determine the cable orientation. CHRDETB detection and VBUS input for attach and detach detection when the device operates as an UFP port. RGB LED current sink output 3 RGB LED current sink output 1. Connection point between the reverse-blocking MOSFET and the highside switching MOSFET. Flash LED driver power input for strobe mode. Connect a 4.7µF ceramic capacitor between FL_VMID and ground. Flash LED driver power input for torch mode. Regulated input voltage to power PD_CC pins as VCONN. Active-low open-drain interrupt output. It requests the processor to check the registers. Moonlight LED current sink output. RGB LED current sink output 2 Charger switch node for output inductor connection.
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Page 14 of 210
MT6360 PMIC Datasheet Confidential A Pin No.
Pin Name
RGB_PGND LDO1_VOUT LDO2_VOUT CHG_PGND FL_TORCH FL_STROBE
Pin Description Regulated output voltage to supply for the PWM low-side gate driver and the bootstrap capacitor. Connect a 2.2µF ceramic capacitor between CHG_VDDP to ground. 1. If VBUS is plugged in, CHG_VDDP will be powered by CHG_VIN and regulated to 4.9V. 2. If VBUS is unplugged, the charger will operate in sleep mode and the CHG_VDDP voltage will be 0V. Charger bootstrap voltage to supply the high-side MOSFET gate driver. Connect a capacitor between CHG_BOOT and CHG_VLX. Configurable power amplifier synchronization input or configurable active-high torch mode enable. Connect a 300kΩ internal pull-down resistor between FL_TXMASK and ground. CHG_VIN ready indication, open-drain output that indicates PD_VBUS is in. Type-C connector Configuration Channel (CC) 1, It is used to detect a cable plug event and determine the cable orientation. RGB ground. Tie RGB_PGND and ground on the PCB. LDO1 output. LDO2 output. Charger ground. Tie CHG_PGND and ground on the PCB. Flash LED Torch mode enable input. Flash LED Strobe mode enable input.
AGND
Analog ground. Tie AGND and ground on the PCB.
SRCLKEN_0 LDO3_VOUT
Source clock enable ON and LP control pin 0. LDO3 output. LDO_VIN1 power input for LDO1, LDO2 and LDO3. Connect a 2.2µF ceramic capacitor between LDO_VIN1 and ground. System connection node. Internal BATFET is connected between VSYS and VBAT. Connect a 22µF ceramic capacitor between VSYS and ground. Battery over-voltage protection (BAT OVP) indication. It is an open– drain and active-low output. It is low if BAT OVP occurs; otherwise, it is high. Buck1, Buck2, LDO6 and LDO7 enable control input. When EN = low, all bucks and LDOs are turned off. LDO6 output. LDO_VIN2 power input for LDO5 and logic circuit of LDO6/7. Connect a 2.2µF ceramic capacitor between LDO_VIN2 and ground. Charger enable input, active-low. Manual reset input for hardware reset. LDO5 output. Charge current output node for battery connection. The internal BATFET is connected between VSYS and VBAT. Connect a 10µF ceramic capacitor between VBAT and ground. Active-low open-drain interrupt output. It requests the processor to read the registers. Indicates power not good of Bucks and LDOs. Active-low open-drain. LDO7 output voltage-sense input. LDO7 output. Internal BATFET enable control input. In shipping mode, CHG_QONB is pulled Low for the duration of tSHIPMODE_CHG (typical 0.9s) to exit shipping mode.
C4
CHG_VDDP
C5
CHG_BOOT
C6
FL_TXMASK
C7
CHRDETB
C8
PD_CC1
C9 C10 C11 D1, D2, D3 D5 D6 D8, E5, E6, E7, E8, F5, F6, F7, F8, G5, G6, G7, G8 D9 D10 D11 E1, F1, F2, F3
LDO_VIN1 VSYS
E3
CHG_VBATOVPB
E9
EN
E10
LDO6_VOUT
E11
LDO_VIN2
F4 F9 F11
CHG_ENB MRSTB LDO5_VOUT
G1, G2, G3, H1
VBAT
G4
IRQB
G9 G10 G11
FAULTB LDO7_VOUTS LDO7_VOUT
H2
CHG_QONB
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Page 15 of 210
MT6360 PMIC Datasheet Confidential A Pin No.
Pin Name
H3
UVLO_SEL
H4
VREF_TS
H5
SDA
H6 H7 H8 H9 H10
SDCARD_DET_N BUCK2_RSGND BUCK2_VOUT BUCK1_VOUT BUCK1_RSGND
H11
LDO_VIN3
J1
VBATS
J2
TS
J3
HW_TRAPPING
J4
USB_ID
J5
SCL
J6, K6
BUCK2_PGND
J7, K7
BUCK2_LX
J8, K8
BUCK2_PVIN
J9, K9
BUCK1_PVIN
J10, K10
BUCK1_LX
J11, K11
BUCK1_PGND
K1 K2 K3
VBATS_GND DD+
K4
VDDA
K5
VDDM
MediaTek Confidential
Pin Description SYSUVLO rising threshold voltage setting and UVLO_SEL pin defines default value. Power output of 1.8V reference power for temperature sensing. I2C interface serial data input/output. Open-drain. An external pull-up resistor is required. When SDCARD_DET_N is active, disable LDO5. BUCK2 remote sense ground. BUCK2 output voltage sense through this pin. BUCK1 output voltage sense through this pin. BUCK1 remote sense ground. LDO_VIN3 power input for LDO6 & LDO7. Connect a 2.2µF ceramic capacitor between LDO_VIN3 and ground. Battery voltage-sense. Temperature-sense input, connected to a resistor divider for temperature programming. Either use an external pull-down resistance or connect the pin to VDDA to define power configuration. USB ID Port Connected to USB Receptacle. I2C interface serial clock input. Open-drain. An external pull-up resistor is required. BUCK2 power ground. The low-side MOSFET is referenced to this pin. CIN and COUT should be returned with a minimal path to these pins. Buck2 switching node. Connect to the inductor. BUCK2 power input voltage. Connect to the input power source. Connect to CIN with minimal path. BUCK1 power input voltage. Connect to the input power source. Connect to CIN with minimal path. Buck1 switching node. Connect to the inductor. BUCK1 power ground. The low-side MOSFET is referenced to this pin. CIN and COUT should be returned with a minimal path to these pins. Battery voltage-sense ground. USB D- port. USB D+ port. Regulated power input for an internal analog base. Connect a 2.2μF ceramic capacitor between VDDA and ground. Regulated voltage output. Connect a 2.2μF ceramic capacitor between VDDM and PGND. It also provides power to all VDDA-powered circuits.
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Page 16 of 210
MT6360 PMIC Datasheet Confidential A
1.7
Typical Application Circuit TVS
VBUS
C1 2.2µF/35V
A1, A2, A3 C2 2.2µF/35V
D1
CHG_VIN
CHG_VMID
CHG_BOOT A9 TVS
CC1
C8 C3 330pF/25V
D7
C4 330pF/25V
D8 Type-C or micro USB Connector
C5 4.7µF/6.3V
R1 1M
PD_CC1
VSYS
K3 DP K2
DN TVS
J4 R2 698R
TVS
A4
D3
D2
C1, C2, C3
L3 C16 47nF~100nF/16V 1µH
VBATS
C17 22µF/6.3V TVS
C18 10µF/6.3V
PD_VCONN5V
D+
CHG_VDDP
Battery Pack
K1 C4 C19 2.2µF/6.3V
DCHG_PGND
D1, D2, D3
USB_ID FL_VINTORCH
CHG_ILIM
B7
To VSYS
FL_LEDCS1 J2 TS
R4 NTC/10k
FL_LEDCS2
C7 2.2µF/6.3V
FL_TORCH
VDDM
FL_STROBE K4
C8 2.2µF/6.3V
A7 A6
FL_TXMASK
VDDA
R6 2.2K
D6 C6 To VSYS LED1
R7 2.2K
R8 2.2K
R9 2.2K
R10 2.2K
RGB_ISINK1 J5 H5 G4 B9
Processor
E3
SCL
RGB_ISINK2
SDA
RGB_ISINK3
IRQB PD_IRQB
F9 D9
MT6360
ML_ISINK RGB_PGND
UVLO_SEL
HW_TRAPPING
LDO_VIN1 G9 E9 H2
LDO_VIN2
LDO_VIN3 E9
SD CARD
AGND LDO2_VOUT
J9, K9
To VSYS
C9 4.7µF/6.3V L1 0.33µH
VMDLA C10 22µF/6.3V
C11 22µF/6.3V To VMDLA_FB To VMDLA_GND
H9 H10 J11, K11
J8, K8
To VSYS C12 4.7µF/6.3V L2 0.33µH
VDRAM1 C13
J7, K7
To VDRAM1_FB To VDRAM1_GND
BUCK1_LX
J3
RUVLO_SEL
RHW_TRAPPING
D11 C21 2.2µF/6.3V E11 C22 2.2µF/6.3V H11 C23 2.2µF/6.3V C10 C24 1µF/6.3V C11 C25 1µF/6.3V
LDO5_VOUT
D10 C26 1µF/6.3V F11 C27 1µF/6.3V
BUCK1_VOUT BUCK1_RSGND BUCK1_PGND
LDO6_VOUT
LDO7_VOUT
BUCK2_PVIN LDO7_VOUTS
C14
H3
BUCK1_PVIN LDO3_VOUT
J10, K10
C9
SDCARD_DET_N LDO1_VOUT
D8, E5, E6, E7, E8, F5, F6, F7, F8, G5, G6, G7, G8
B10
CHG_QONB
C7 CHRDETB
LED4
A10
FAULTB EN
LED3
B11
MRSTB SRCLKEN_0
LED2
A11
CHG_VBATOVPB
F4 CHG_ENB
Another PMIC
D6
D5
To VDDIO R5 100K
To CHG_VMID
D5 K5
VDDM
C20 4.7µF/25V
FL_VMID
H4 VREF_TS R3 3.9k
D4
J1
B5, B6
C6 1nF~4.7nF/6.3V
To System
E1, F1, F2, F3
PD_CC2
VBATS_GND
ID
C5
VBAT
B8
To SYS
CHG_VLX
C15 4.7µF/25V
G1, G2, G3, H1 A8
TVS
CC2
PD_VBUS
B1, B2, B3
E10 C28 10µF/6.3V G11 C29 22µF/6.3V
To VSYS
To VSYS
From VDRAM1
To VFP
To VTP
To VMC
To VMCH
To VMDDR C30 22µF/6.3V To VDRAM2
G10
BUCK2_LX BUCK2_VOUT
H7 J6, K6
BUCK2_RSGND BUCK2_PGND
Figure 1-2. Application circuit
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Page 17 of 210
MT6360 PMIC Datasheet Confidential A
2
Electrical Characteristics
2.1
Absolute Maximum Ratings
(Note 1) Parameter PD_VBUS PD_CC1, PD_CC2
Conditions
Steady state Transient (< 10ms)
Battery Pin Input (Note 4)
Min -0.5 -0.5 -0.5 -0.5
Typ -----
Max 28 24 6 7
Unit V V
-0.5
--
22
V
-0.5 -0.5
---
24 16
V
--0.5
---
-2 6
--
--
4.69
W
--
21.3
--
°C/W
--65 --
----
260 150 2
°C °C kV
CHG_VIN, CHG_VMID, CHG_BOOT, FL_VMID USB ID, D+, DCHG_LX
LX (Peak < 100ns duration)
Other Pins @ TA = 25°C WL-CSP-103B 4.64x4.14 (BSC)
Power Dissipation, PD Package Thermal Resistance (Note 2) Lead Temperature Storage Temperature Range ESD Susceptibility (Note 3)
WL-CSP-103B 4.64x4.14 (BSC), θJA Soldering, 10 sec. HBM (Human Body Model)
V V
V V
Note 1: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2: θJA is measured under natural convection (still air) at TA = 25°C with the component mounted on a high effective-thermal-conductivity four-layer test board on a JEDEC 51-7 thermal measurement standard. Note 3: Devices are ESD sensitive. Handling precaution is recommended. Note 4: Battery input pin: VBAT / VBATS / VSYS / BUCKx_PVIN / BUCKx_LX / LDO_VINx / FL_VINTORCH
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Page 18 of 210
MT6360 PMIC Datasheet Confidential A
2.2
Recommended Operating Range
(Note 5) PD_VBUS, CHG_VIN Supply Input Voltage --------------------------- VBAT Supply Input Voltage ---------------------------------------------- BUCK1/2_PVIN Input Voltage------------------------------------------- LDO_VIN1/2 -------------------------------------------------------------- LDO_VIN3----------------------------------------------------------------- IBAT (Discharging current with internal MOSFET) ------------------- IBAT (Discharging current with internal MOSFET) ------------------- Junction Temperature Range -------------------------------------------- Ambient Temperature Range ---------------------------------------------
4V to 14V 2.8V to 5V 3.1V to 5V 3.15V to 5V 1.1V to 5V 6A (continues) 9A (peak, up to 1 sec duration) -40°C to 125°C -40°C to 85°C
Note 5: The device is not guaranteed to function outside its operating conditions.
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Page 19 of 210
MT6360 PMIC Datasheet Confidential A
2.3
Electrical Characteristics
VCHG_VIN = 5V, VBAT = 4.2V, L1 = L2 = 0.33µH, L3 = 1µH, C2 = 2.2µF, C18 = 10µF, TA = 25°C, unless otherwise specified Table 2-1. Electrical specifications Parameter Symbol PMIC Quiescent Current
Test Conditions
Min
Typ
Max
Unit
Shutdown Current
ISHDN
On VBAT pin, with all channels shut down, VBAT = 4V
--
63
85
µA
Shipping-Mode Current
IBAT_SHIP
VBAT only, in shipping mode
--
16
46
µA
ICHG_VIN
VCHG_VLX is non-switching, VCHG_VIN = 5V, VBAT = VCV_CHG, ICHG = 0, Flash LED, LDOs, Bucks and RGB devices disabled, PD cable attached (Full functions are not in the communication situation)
--
8.55
11.12
mA
--
810
1053
µA
--
150
--
°C
-15
--
15
°C
95
110
125
°C
IDS = 10mA
--
--
0.4
V
Logic high threshold
1.2
--
--
V
Logic low threshold
--
--
0.4
V
External R selection, R = 1MΩ (2.9V), 100mV/Step
2.8
--
3.3
V
VSYS rising, default 2.9V
-50
--
+50
mV
--
15
--
ms
I2C programmable, default 2.5V, 50mV/Step
2.4
--
2.8
V
VSYS falling, default 2.5V
-50
--
+50
mV
CHG_VIN Supply Current
CHG_VIN Supply Current with Charger ICHG_VIN_HZ in H-Z Mode Over-Temperature Protection Threshold TOTP Over-Temperature Protection Accuracy TOTP_ACC Over-Temperature TOTP_RECOVER Protection Recover Control I/O Pin & VDDA & VSYS Logic-Low Threshold Voltage for All Open- VOL Drain Outputs Logic-High Threshold Voltage VIH for All Inputs Logic-Low Threshold Voltage for All VIL Inputs SYS Under-Voltage VSYS_UVLO_RI Protection Rising SE Threshold Range SYS Under-Voltage VSYS_UVLO_AC Protection Rising Threshold Accuracy C_RISE
VCHG_VLX is in high-impedance mode, VCHG_VIN = 5V, VBAT =4V Flash LED, LDOs, Bucks, PD and RGB devices disabled Thermal shutdown threshold temperature Thermal shutdown temperature accuracy Thermal shutdown recover temperature
De-bouncing time by tDEBOUN_SYS_ SYS UVLO Rising UVLO_RISE SYS Under-Voltage Protection falling Threshold Range SYS Under-Voltage Protection Falling Threshold Accuracy
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VSYS_UVLO_FA LL
VSYS_UVLO_AC C_FALL
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Page 20 of 210
MT6360 PMIC Datasheet Confidential A Parameter Symbol VDDA Over-Voltage Protection Threshold VVDDA_OVP VDDA Over-Voltage VVDDA_OVP_H Protection YS Hysteresis Pull-Down Ability on IPD_MRSTB MRSTB
Test Conditions
Min
Typ
Max
Unit
VDDA rising
5.25
5.5
5.75
V
VDDA falling
--
0.2
--
V
--
1
2.3
µA
--
1
2.3
µA
RSRCLKEN_0
--
350
--
kΩ
REN
--
350
--
kΩ
Pull-Down Ability on IPD_SDCARD_D SDCARD_DET_N ET_N Pull-Down Resistance on SRCLKEN_0 Pull-Down Resistance on EN USB ID USB_ID Pull-Up Voltage
VUSB_ID_PULL
VUSB_ID = 1V, 0x6F[7] = 1
0.57
0.6
0.63
V
UP
VUSB_ID = 1.8V, 0x6F[7] = 0
1.71
1.8
1.89
V
500kΩ, 75kΩ, 5kΩ, 1kΩ
-20
--
20
%
500kΩ, 75kΩ, 5kΩ, 1kΩ
3.75
5
6.25
kΩ
0x6F[6] = 0, 0x6F[7] = 0 0x6F[6] = 1, 0x6F[7] = 1 0x6F[7] =1 0x6F[7] = 0
1.3 0.18 ---
1.45 0.2 0.05 0.1
1.6 0.22 ---
I2C programmable, range 5µs to 64ms (default 50µs)
-10
--
10
%
--
--
20
pF
VCHG_VIN falling, VCHG_VIN-VBAT
0
0.04
0.1
V
VCHG_VIN rising, VCHG_VIN-VBAT
0.04
0.1
0.2
V
Exit sleep-mode
--
120
--
ms
VCHG_VIN falling
--
3.8
--
V
VCHG_VIN rising
--
150
--
mV
--
50
--
mA
--
30
--
ms
320
355
390
AΩ
RUSB_ID_PULL USB_ID Pull-Up Resistance Tolerance UP USB_ID Pull-Down Resistance
RUSB_ID_PULL UP
Interrupt Threshold Voltage
VID_INT
Interrupt Threshold Voltage Hysteresis
VID_INT_HYS
Interrupt De-bounce Time Tolerance
tID_INT_DEB
Input Equivalent Capacitance Charger
CID_IN_CAP
Sleep-Mode Entry Threshold
VSLEEP_
Sleep-Mode Exit Threshold
VSLEEP_EXIT_
Sleep-Mode Exit Deglitch Time
tD_SLEEP_
CHG_VIN Bad Adapter Threshold CHG_VIN Bad Adapter Hysteresis CHG_VIN Bad Adapter Sink Current CHG_VIN Bad Adapter Detection Time Input Current Limit Factor
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ENTER_CHG
CHG
EXIT_CHG
VBAD_ADP_ CHG
VBAD_ADP_ HYS_CHG
IBAD_ADP_ SINK_CHG
tBAD_ADP_ DET_CHG
KILIM_CHG
Input current regulation 508mA by CHG_ILIM pin with resistance = 698Ω
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
V V
Page 21 of 210
MT6360 PMIC Datasheet Confidential A Parameter Symbol CHG_VIN Minimum Input Voltage VMIVR_CHG Regulation (MIVR) Threshold CHG_VIN Minimum V MIVR_ACC_ Input Voltage Regulation Accuracy CHG
Test Conditions
Min
Typ
Max
Unit
I2C programmable range in 0.1V steps
3.9
--
13.4
V
VMIVR = 4.4V or 9V
-2
--
2
%
86
93
100
mA
440
470
500
mA
880
940
1000
mA
CHG
IAICR = 1500mA, VCHG_VIN = 5V, VBAT = 3.8V
1300
1400
1500
mA
CHG_VIN UVLO
VUVLO_CHG
VCHG_VIN rising
3.05
3.3
3.55
V
CHG_VIN UVLO Hysteresis
VUVLO_HYS_
VCHG_VIN falling
--
150
--
mV
VCHG_VIN_OVP VCHG_VIN rising, I2C programmable 5.5V _CHG1
5.17
5.5
5.86
V
VCHG_VIN_OVP VCHG_VIN rising, I2C programmable 6.5V (default) _CHG2
6.11
6.5
6.92
V
VCHG_VIN_OVP VCHG_VIN rising, I2C programmable 11V _CHG3
10.34
11
11.71
V
VCHG_VIN_OVP VCHG_VIN rising, I2C programmable 14.5V _CHG4
13.63
14.5
15.44
V
--
100
--
ns
--
250
--
mV
106
108
110
%
--
2
--
%
--
120
--
°C
4.9
5.25
5.5
V
2.2
2.4
2.6
V
2.3
2.5
2.8
V
AICR 100mA Mode AICR 500mA Mode AICR 1000mA Mode AICR 1500mA Mode
CHG_VIN OverVoltage Protection Threshold CHG_VIN OverVoltage Protection Threshold CHG_VIN OverVoltage Protection Threshold CHG_VIN OverVoltage Protection Threshold CHG_VIN OverVoltage Protection Propagation Delay CHG_VIN OverVoltage Protection Hysteresis
IAICR_100mA_
IAICR = 100mA, VCHG_VIN = 5V,
CHG
VBAT = 3.8V
IAICR_500mA_
IAICR = 500mA, VCHG_VIN = 5V,
CHG
VBAT = 3.8V
IAICR_1000mA_ IAICR = 1000mA, VCHG_VIN = 5V, VBAT = 3.8V
CHG
IAICR_1500mA_
CHG
tCHG_VIN_OVP_ VCHG_VIN rising above VCHG_VIN overvoltage protection threshold turn off CH UUG MOS, OVP setting = 6.5V VCHG_VIN_OVP _HYS_CHG
VBAT Over-Voltage VBAT_OVP_ Protection Threshold CHG VBAT Over-Voltage Protection Hysteresis
VBAT_OVP_ HYS_CHG
VCHG_VIN falling VBAT rising, as percentage of VOREG_CHG, as VBAT/VOREG_CHG, 0x12[4] TE = 0 VBAT falling, as (VBAT VOREG_CHG)/VOREG_CHG, 0x12[4] TE =0 Charge current starts decreasing (default)
Thermal Regulation TTHREG_CHG Threshold VSYS Over-Voltage Protection Threshold VSYS_OVP_CHG VSYS rising VSYS Under-Voltage V falling Protection Threshold V VBAT Depletion Threshold Voltage
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VBAT_DPL_ RISE
VBAT_DPL rising
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Page 22 of 210
MT6360 PMIC Datasheet Confidential A Parameter VBAT Depletion Threshold Voltage CHG_VIN Force Sleep Mode Supply Current End of Charge Battery Regulation Voltage Range Battery Regulation Voltage Accuracy Re-Charge Mode Threshold Re-Charge Deglitch Time End-of-Charge Current Default End-ofCharge Current End-of-Charge Current Accuracy End-of-Charge Deglitch Time
Min
Typ
Max
Unit
VBAT_DPL falling
2
2.3
2.39
V
Reg: 0x11[3] = 1
--
--
2.5
mA
I2C programmable in 10mV steps
3.9
--
4.71
V
VOREG_CHG = 4.2V, 4.35V, 4.36V, 4.37V, 4.38V, 4.43V or VOREG_CHG = 4.45V (TC = -10°C to 70°C) (Note 7)
-0.5
--
0.5
%
VRECH_CHG
I2C programmable, VBAT falling, the difference below VOREG_CHG
50
100
150
mV
tD_RECH_CHG
VBAT falling
--
120
--
ms
IEOC_CHG
I2C programmable in 50mA steps
100
--
850
mA
--
250
--
mA
-20
--
20
%
--
2
--
ms
I2C programmable in 0.1A steps, 0x17 bit[7:2]
0.3
--
3
A
VBAT = 3.8V, 300mA ≤ ICHG < 500mA, (TC = -10°C to 70°C)
-20
--
20
%
VBAT = 3.8V, 500mA ≤ ICHG < 1000mA, (TC = -10°C to 70°C)
-10
--
10
%
VBAT = 3.8V, ICHG ≥ 1000mA, (TC = 10°C to 70°C)
-5
--
5
%
I2C programmable in 0.1V steps, VBAT rising
2.0
--
3.5
V
--
0.2
--
V
-5
--
5
%
--
150
--
mA
-20
--
20
%
--
2
--
V
--
mV
VBAT_DPL_ FALL
ICHG_VIN_ SLEEP
VOREG_CHG VOREG_ACC_ CHG
IEOC_ACC
ICHG Current Accuracy 1
ICHG_ACC1_
ICHG Current Accuracy 2
ICHG_ACC2_
ICHG Current Accuracy 3
ICHG_ACC3_
CHG
CHG
CHG
VPRECHG_CHG
Pre-Charge Mode Hysteresis
VPRECHG_HYS
Pre-Charge Threshold Accuracy
VPRECHG_ACC_
Pre-Charge Current Accuracy
_CHG
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Pre-charge hysteresis, VBAT falling
CHG
IPRECHG_ CHG
I2C programmable (default)
IPRECHG_ACC_ CHG
Trickle Charge VTRICHG Threshold Trickle Charge 200 V Threshold Hysteresis TRICHG_HYS Trickle Charge VTRICHG_ACC Threshold Accuracy Trickle Current
IEOC_CHG = 150mA, 200mA, 250mA
tD_EOC_CHG ICHG
Pre-Charge Current
Test Conditions
IEOC_DEF_CHG Default
Charge Current
Pre-Charge Mode Threshold
--
Symbol
VBAT falling VBAT rising
ITRICHG
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
-5
--
5
%
--
100
--
mA
Page 23 of 210
MT6360 PMIC Datasheet Confidential A Parameter Trickle Current Accuracy VSYS Regulation Voltage
Symbol
Test Conditions
Min
Typ
Max
Unit
ITRICHG_ACC
-20
--
20
%
VSYS_MIN_CHG I2C programmable in 0.1V steps
3.3
--
4
V
-3
--
3
%
VSYS Regulation Voltage Accuracy
VSYS_MIN_ACC
UUG On-Resistance
RON_UUG_CHG From CHG_VIN to CHG_VMID
--
10
30
mΩ
--
20
40
mΩ
_CHG
UG On-Resistance
RON_UG_CHG
From CHG_VMID to CHG_VLX
LG On-Resistance
RON_LG_CHG
From CHG_VLX to PGND
--
20
40
mΩ
PPMOS OnResistance
RON_PPMOS_
From VSYS to VBAT
--
12
30
mΩ
fOSC0_CHG
I2C programmable to 1.5MHz (default)
--
1.5
--
fOSC1_CHG
I2C programmable to 1MHz
--
1
--
fOSC2_CHG
I2C programmable to 0.75MHz
--
0.75
--
-10
--
10
%
--
97
--
%
0
--
--
%
4.5
4.9
5.3
V
ICHG_BUCK_
VCHG_VIN = 5.5V REG0x1D[2] = 1’b0
4
6
8
OCP_CHG
REG0x1D[2] = 1 ‘b1
5.6
8
10.4
16.15
19
21.85
kΩ
0.86
0.96
1.06
s
CHG_QONB low time to enable full system reset
12
15
18
s
BATFET off-time during full system reset
0.6
0.66
0.72
s
15
18
21.6
s
--
4.6
--
V
--
50
--
mV
I2C programmable default
--
5.05
--
V
ILOAD = 0mA
-3
--
3
%
OTG_OC = 0.5A, REG 0x1A[2:0] = 000
0.5
--
--
A
VCHG_VMID rising
5.72
6
6.28
V
--
200
--
mV
Switching Frequency
CHG
Switching Frequency fOSC_ACC_CHG Accuracy Maximum Duty DMAX_CHG Cycle Minimum Duty Cycle DMIN_CHG VDDP Regulation Charger_Buck OCP Current Internal QONB PullUp Resistance QONB Exit Shipping Mode Duration QONB System Reset Duration BATFET Reset Time
VVDDP_CHG
RQONB_CHG tSHIPMODE_ CHG
tQONB_RST_ CHG
tBATFET_RST_ CHG
CHG_QONB low for BATFET on-time to exit shipping mode
Shipping Mode Entry Deglitch Time
tD_SHIP_ENTER Enter shipping mode delay
AICC Threshold
VAICC_VTH
AICC Hysteresis OTG Output Regulation OTG Output Accuracy
VAICC_HYS_ VTH
VBSTCV_CHG VBSTCV_ACC_ CHG
OTG Over-Load Protection Threshold IBST_0.5A_CHG OTG CHG_VMID VMIDOVP_OTG Over-Voltage Protection Threshold _CHG OTG CHG_VMID Over-Voltage
MediaTek Confidential
VCHG_VIN rising, I2C programmable
VMIDOVP_OTG _HYS_CHG
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
MHz
A
Page 24 of 210
MT6360 PMIC Datasheet Confidential A Parameter Protection Hysteresis OTG VBAT UnderVoltage Protection Threshold OTG VBAT UnderVoltage Protection Hysteresis Boost Supply Current OTG Over-Current Protection Threshold Pull-Down Ability on CHG_ENB D+/D- Detection
Symbol
Min
Typ
Max
Unit
2.62
2.8
2.98
V
--
400
--
mV
IBOOST_SUPPLY OTG mode, ILOAD = 0mA
--
8
--
mA
IOTG_OCP_CHG Default = 6.5A
5.2
6.5
8.2
A
IPD_CHG_ENB
--
1
2.3
µA
VBAT_UVP_OTG _CHG
VBAT_UVP_OTG _HYS_CHG
Test Conditions
I2C default, VBAT falling VBAT rising
D+ Source Voltage
VDP_SRC
0.5
0.6
0.7
V
Data Detect Voltage
VDAT_REF
0.25
0.3
0.4
V
VLGC Voltage
VLGC_CHG
0.8
--
2
V
D- Sink Current
IDM_SINK
50
100
150
µA
7
--
13
µA
50
90
130
Ω
Data Contract Detect IDP_SRC Current Source Dedicated Charging Port Resistance RD+D- DCP Across D+/-
sEN_DCP = 1
D+ Source On Time
tDP_SRC_ON
40
64
--
ms
DCD Timeout
tDCD_TIMEOUT
300
--
1200
ms
D+ Source Off to High Current
tDPSRC_HICRN
28
32
36
ms
Charger Detect Debounce
tCHGR_DET_
27
30
33
ms
6
--
14.5
V
-3
--
3
%
--
150
--
mV
2.6
--
3.7
V
-4
--
4
%
--
150
--
mV
CHRDETB PD_VBUS OverVoltage Protection Threshold Range PD_VBUS OverVoltage Protection Accuracy PD_VBUS OverVoltage Protection Hysteresis
T
DBNC
VPD_VUS_OVP
VPD_VUS_OVP rising, I2C programmable (default 10.5V)
VPD_VUS_OVP_ ACC
VPD_VUS_HYS
PD_VBUS UVLO VPD_VUS_UVLO falling, I2C Protection Threshold VPD_VUS_UVLO programmable 0.1V/Step (default Range 3.7V) PD_VBUS UVLO Protection Accuracy PD_VBUS UVLO Protection Hysteresis ADC
MediaTek Confidential
VPD_VUS_UVLO _ACC
VPD_VUS_UVLO _HYS_
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Page 25 of 210
MT6360 PMIC Datasheet Confidential A Parameter
Symbol
ADC Conversion Time
tCONV_ADC
Number of Bits for ADC Resolution
RES_ADC
CHG_VIN_DIV5 Measurement Range
VVBUS_DIV5_A
CHG_VIN_DIV5 Resolution
VVBUS_DIV5AD
CHG_VIN_DIV5 Accuracy
VVBUS_DIV5AD
CHG_VIN_DIV2 Measurement Range
VVBUS_DIV2_A
CHG_VIN_DIV2 Resolution
VVBUS_DIV2AD
CHG_VIN_DIV2 Accuracy
VVBUS_DIV2AD
VBAT Measurement Range
VBAT_ADC_RA
VBAT Resolution
Test Conditions Only for one channel, 0x56[5:3] = 0ms of wait time and 0x58[7:0] = 0ms of idle time
DC_RANGE
C_RES
C_ACC
DC_RANGE
C_RES
C_ACC
NGE
Min
Typ
Max
Unit
20.8
26
31.2
ms
--
12
--
bits
1
--
22
V
--
25
--
mV
-3
--
3
LSB
1
--
VDDA x2
V
--
10
--
mV
-3
--
3
LSB
0
--
VDDA
V
VBAT_ADC_RES
--
5
--
mV
VBAT Accuracy
VBAT_ADC_ACC
-2
--
2
LSB
VSYS Measurement Range
VSYS_ADC_RAN
0
--
VDDA
V
VSYS Resolution
VSYS_ADC_RES
--
5
--
mV
VSYS Accuracy
VSYS_ADC_ACC
-2
--
2
LSB
IBUS Measurement Range
IIBUS_ADC_RA
0
--
5
A
IBUS Resolution
IIBUS_ADC_RES
--
50
--
mA
IBUS > 2A, IAICR [7:2] setting ≥ 400mA
-3
--
3
IBUS < 2A, IAICR [7:2] setting ≥ 400mA
-2
--
2
IBUS < 2A, IAICR [7:2] setting < 400mA
-2
--
2
0
--
5
A
IBUS Accuracy
GE
NGE
IIBUS_ADC_ACC
LSB
IBAT Measurement Range
IIBAT_ADC_RA
IBAT Resolution
IIBAT_ADC_RES
--
50
--
mA
IBAT Accuracy
IIBAT_ADC_ACC
-2
--
2
LSB
TEMP_JC Measurement Range
TTEMP_JC_ADC
-40
--
120
°C
--
2
--
°C
-3
--
3
LSB
1.782
1.8
1.818
V
TEMP_JC Resolution TEMP_JC Accuracy VREF_TS Pull-Up Voltage
MediaTek Confidential
NGE
_RANGE
TTEMP_JC_ADC _RES
TTEMP_JC_ADC _ACC
Temperature < 85°C
VREF_TS_ADC
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Page 26 of 210
ch
MT6360 PMIC Datasheet Confidential A Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
0
--
VDDA
V
TS Voltage Measurement Range
VTS_ADC_
TS Resolution
VTS_ADC_RES
--
5
--
mV
TS Accuracy
TTS_ADC_ACC
-2
--
2
LSB
USB_ID Measurement Range
VUSBID_ADC_R
0
--
VDDA - 1.4
V
--
5
--
mV
ms
USB_ID Resolution
RANGE
ANGE
VDDA > 3.4V
VUSB_ID_ADC_ RES
Pump Express PE+1 On Time (A)
tON_A_PE
VBAT = 3.8V. Use PE+ adapter
430
500
570
PE+1 On Time (B)
tON_B_PE
VBAT = 3.8V. Use PE+ adapter
240
300
360
ms
100
130
ms
PE+1 On Time (C)
tON_C_PE
VBAT = 3.8V. Use PE+ adapter
70
PE+1 Off Time (D)
tOFF_D_PE
VBAT = 3.8V. Use PE+ adapter
70
100
130
ms
PE+1 Off Time (I)
tOFF_I_PE
VBAT = 3.8V. Use PE+ adapter
80
--
225
ms
PE+2 Off Time (D)
tOFF_D_PE
VBAT = 3.8V. Use PE+ adapter
87
105
128
ms
PE+2 On Time (E)
tON_E_PE
VBAT = 3.8V. Use PE+ adapter
147
190
248
ms
PE+2 On Time (F)
tON_F_PE
VBAT = 3.8V. Use PE+ adapter
87
102.5
118
ms
PE+2 On Time (G)
tON_G_PE
VBAT = 3.8V. Use PE+ adapter
22
50
68
ms
VBAT = 3.8V. Use PE+ adapter
22
50
68
ms
VBAT = 3.8V. Use PE+ adapter
135
155
175
ms
Flash LED current is set 25mA to 400mA
-8
--
8
%
Flash LED current set 0.4A to 1.5A
-6
--
6
%
VLEDVIN = 5V, LEDCSX = 0, LEDCSX disabled
--
0.1
4
µA
LEDCSX = 0, LEDCSX enabled
--
320
1000
µA
--
1
1.3
V
1.8
2.5
3.3
ms
--
1248
--
ms
-10
--
10
%
PE+2 Off Time (H)
tOFF_H_PE
PE+2 Off Time (I)
tOFF_I_PE Flash LED Current Source LED Current ILED_ACC_FL Accuracy LED Current ILED_ACC_FL Accuracy FL_LEDCSx Leakage ILEAK_FL Current FL_LEDCSx Start ISTART_FL Up Current LEDCSX Short VSC_FL Threshold LEDCSX Short Event tD_SC_FL Timer Flash Time-Out Flash Timer Accuracy Current Source Regulation Voltage Current Source Regulation Voltage Strobe/TXMask Deglitch Time --
4.5 Ready Time Flash
tTIMEOUT_FL
FLEDx_STRB_TO = 0100101
tTMR_ACC_FL
Timer set by register
VREG_FL
ILED = 200mA, 0x7C[1:0] = 00
--
200
300
mV
VREG_FL
ILED = 1500mA, 0x7C[1:0] = 01
--
--
500
mV
--
10
--
µs
5
ms
tD_STRB_FL tFLSH_RDY_FL
800mA target value
Strobe FL-CHG_VIN VIN_OVP_FL OVP Strobe FL-CHG_VIN VIN_OVP_ OVP Hysteresis Hys_FL
MediaTek Confidential
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
5.45
5.6
5.75
V
0.23
0.3
0.37
V
Page 27 of 210
MT6360 PMIC Datasheet Confidential A Parameter High-Side Switch On-Resistance Low-Side Switch OnResistance Pull-Down Resistance On FL_STROBE Pull-Down Resistance On BL_EN Pull-Down Resistance On FL_TXMASK USB_PD
Min
Typ
Max
Unit
RON_H_FL
--
60
--
mΩ
RON_L_FL
--
36
--
mΩ
RL_FL_STROBE
--
350
--
kΩ
RL_FL_TORCH
--
350
--
kΩ
RL_FL_TXMASK
--
350
--
kΩ
fBitRate_PD
270
300
330
Kbps
pBitRate_PD
--
--
0.25
%
25
--
--
µs
-1
--
1
µs
--
--
23
µs
tFall_PD Time to cease driving tHoldLowBMC_P the line after the final high-to-low D transition
300
--
--
ns
1
--
--
µs
Rise Time
tRise_PD
300
--
--
ns
Voltage Swing
VSwing_PD
1.05
1.125
1.2
V
Transmitter Output Impedance
zDriver_PD
33
--
75
Ω
12
--
20
µs
1
--
--
MΩ
--
32
45
µA
--
0.7
1
Ω
200
--
600
mA
Bit Rate Maximum difference between the bit rate during the part of the packet following the Preamble and the reference bit-rate. Time from the end of last bit of a frame until the start of the first bit of the next Preamble. Time before the start of the first bit of the Preamble when the transmitter shall start driving the line Time to cease driving the line after the end of the last bit of the frame.
Symbol
Test Conditions
tInterFrameGap_ PD
tStartDrive_PD
tEndDriveBMC_ PD
Fall Time
Time window for detecting non-idle Receiver Input Impedance Low-Power Mode
tTransitionWindo w_PD
zBmcRx_PD ILOW-POWER_
VCONN Switch OnResistance
RON_VCONN_P
OCP Range
IOCP_PD
MediaTek Confidential
DRP toggle
D
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Page 28 of 210
MT6360 PMIC Datasheet Confidential A Parameter DFP 80µA CC Current
Symbol
Typ
Max
Unit
64
80
96
µA
166
180
194
µA
304
330
356
µA
4.59
5.1
5.61
kΩ
Under ICHG = ICC_DFP80_PD and ICC_DFP180_PD
0.2
--
1.6
V
Under ICHG = ICC_DFP330_PD
0.8
--
2.45
V
3.5
--
4.0
V
REG 0xAB bit=0 in low-power mode
1.8
2
2.2
V
ILED = 20mA
-5
--
5
%
ILED = 20mA
-5
--
5
%
ILED = 20mA
--
75
150
mV
1
--
24
mA
PD
ICC_DFP180_ PD
DFP 330µA CC Current
PD
ICC_DFP330_
UFP Pull-Down Resistance through Rd_PD CC Pin UFP Pull-Down Threshold Voltage in VTH_DBL_PD Dead Battery UFP Pull-Down Threshold Voltage in VTH_DBH_PD Dead Battery
CC Pin Lower PullUp Voltage
Min
ICC_DFP80_
DFP 180µA CC Current
Valid VBUS Detection Threshold
Test Conditions
VVALID_VBUS_ PD
VLPWR_PULLU P_CC
RGB / Moonlight LED Driver Current Accuracy Current Matching Dropout Voltage RGB_ISINK1/2/3 Output Current Range Moonlight Output Current Range Moonlight Current Accuracy Moonlight Dropout Voltage RGB Supply Current Moonlight Supply Current RGB Timing Accuracy BUCK1-VMDLA
ILED_ACC_RGB ILED_MATCH_ RGB
VDROP_RGB ILED_ISINK ILED_ML
5mA/Step
5
--
150
mA
ILED_ACC_ML
ILED = 60mA (default)
-5
--
5
%
ILED = 150mA
--
--
200
mV
VML_DROP_ RGB
ILED_ISINK_SU PPLY
ILED_ML_SUPP LY
--
203
--
µA
--
162
--
µA
1 channels set to 20mA
--
122
--
µA
Moonlight set to 100mA
--
176
--
µA
-5
--
5
%
--
--
10
%
4
5
6
Α
--
84
--
--
84.8
--
TACC_RGB
Turn-On Overshoot Over-Current Protection (OCP)
IOCP1
Efficiency
Eff_BUCK
MediaTek Confidential
All 3 channels set to 20mA 2 channels set to 20mA
VOUT = default, no load Peak inductor current, as REG_PMIC, 0x15[2:1] = 01 VBAT = 4V, VOUT = 0.8V, I_LOAD = 100mA, L_DCR_max = 26mΩ VBAT = 4V, VOUT = 0.8V, I_LOAD = 500mA, L_DCR_max = 26mΩ
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
%
Page 29 of 210
MT6360 PMIC Datasheet Confidential A Parameter
Symbol
Test Conditions VBAT = 4V, VOUT = 0.8V, I_LOAD = 1000mA, L_DCR_max = 26mΩ VBAT = 4V, VOUT = 0.8V, I_LOAD = 2000mA, L_DCR_max = 26mΩ
Min
Typ
Max
--
84.1
--
--
76.5
--
Unit
BUCK Soft-Start Time
tSS_BUCK
VOUT = 0.55V, I2C programmable
110
--
1000
µs
Switch Frequency
fOSC_BUCK
In FPWM
2.1
2.4
2.7
MHz
Output Voltage Ripple (PWM) Output Voltage Ripple (PFM)
VBAT = 3.1V, I_LOAD = 0.5 x Imax 20MHz measurement BW VBAT = 3.1V, I_LOAD = 0.5 x Imax 20MHz measurement BW VBAT = 3.1V, I_LOAD = 0.1 to 2.06A, tr/tf = 1µs VIN = 5 to 4.3V/3.5V to 2.8V, VOUT = 0.8V, I_LOAD = 2A
Load Transient Line Transient DC Accuracy (Included Line/Load Regulation @ PWM) DC Accuracy (Included Line/Load Regulation @ PFM) Output Discharge Switch OnResistance BUCK1 Supply Current BUCK2-VDRAM1 Turn-On Overshoot Over-Current Protection (OCP)
Efficiency
IBUCK1_PVIN
IOCP2
Eff_BUCK
-5.65% x Vo+11 -5.65% x Vo+11
---
+8% x Vo-11 +8% x Vo-11
mV mV
-53
--
53
mV
-40
--
40
mV
VBAT = 3.1 to 5.0V, I_LOAD = PWM load
-6
--
6
mV
VBAT = 3.1 to 5.0V, I_LOAD = PFM load
-10
--
22.5
mV
--
11
--
Ω
VBUCK1_PVIN = 4V, ILOAD = 0mA, BUCK1_VOUT = 0.55V
--
4
6
µA
VOUT = default, no load Peak inductor current, as REG_PMIC, 0x25[2:1] = 01 VBAT = 4V, VOUT = 1.125V, I_LOAD = 100mA, L_DCR_max = 26mΩ VBAT = 4V, VOUT = 1.125V, I_LOAD = 500mA, L_DCR_max = 26mΩ VBAT = 4V, VOUT = 1.125V, I_LOAD = 1000mA, L_DCR_max = 26mΩ VBAT = 4V, VOUT = 1.125V, I_LOAD = 2000mA, L_DCR_max = 26mΩ
--
--
10
%
4
5
6
A
--
85
--
--
83
--
--
78
--
--
69
--
%
BUCK Soft-Start Time
tSS_BUCK
VOUT = 1.125V, I2C programmable
--
--
1000
µs
Switch Frequency
fOSC_BUCK
In FPWM
2.1
2.4
2.7
MHz
--
1
--
%
--
40
--
mVpp
-40
--
40
mV
-40
--
40
mV
Output Voltage Ripple (PWM) Output Voltage Ripple (PFM) Load Transient Line Transient
MediaTek Confidential
VBAT = 3.1V, VOUT = 1.125V, I_LOAD = 0mA to Imax 20MHz measurement BW VBAT = 3.1V, VOUT = 1.125V, I_LOAD = 0mA to Imax 20MHz measurement BW VBAT = 3.1V, VOUT = 1.125V I_LOAD = 0.1 to 0.9A, tr/tf = 1µs VIN = 5 to 4.3V/3.5V to 2.8V, VOUT = 1.125V, I_LOAD = 2A
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Page 30 of 210
MT6360 PMIC Datasheet Confidential A Parameter DC Accuracy (Included Line/Load Regulation @ PWM) DC Accuracy (Included Line/Load Regulation @ PFM) Output Discharge Switch OnResistance BUCK2 Supply Current
Symbol
Test Conditions
Min
Typ
Max
Unit
VBAT = 3.1 to 5.0V, I_LOAD = PWM load
-0.9
--
0.9
%
VBAT = 3.1 to 5.0V, I_LOAD = PFM load
-0.9
--
3
%
--
11
--
Ω
VBUCK2 = 4V, ILOAD = 0mA, -4 6 BUCK2_VOUT = 1.125V LDO1 to 7 (LDO1: VFP / LDO2: VTP / LDO3: VMC / LDO5: VMCH / LDO6: VMDDR / LDO7: VDRAM2) max{Vo -5 +0.35 ; VLDO_VIN1 3.15} max{Vo +0.35 ; -5 Input Voltage Range VLDO_VIN2 3.15}
Output Voltage Accuracy
Output Current Limit
IBUCK2_PVIN
VLDO_VIN3
LDO7 = 1.8V/10mA
2
--
5
VLDO_VIN3
LDO6 = 0.75V/300mA; LDO7= 0.6V/ 600mA
1.08
--
2
ΔVOUT_LDO1
VOUT = 1.8V (default), IOUT = 150mA
-1
--
1
ΔVOUT_LDO2
VOUT = 1.8V (default), IOUT = 200mA
-1
--
1
ΔVOUT_LDO3
VOUT = 3V (default), IOUT = 200mA
-1
--
1
ΔVOUT_LDO5
VOUT = 2.95V (default), IOUT = 800mA
-1
--
1
ΔVOUT_LDO6
VOUT = 0.75V (default), IOUT = 300mA
-1
--
1
ΔVOUT_LDO7
VOUT = 0.6V (default), IOUT = 600mA
-1
--
1
Ioc_LDO1
225
--
420
Ioc_LDO2
300
--
560
Ioc_LDO3
300
--
500
Ioc_LDO5
1200
--
2000
Ioc_LDO6
450
--
840
Ioc_LDO7
900
--
1680
OCFB_EN = 1
30
--
150
OCFB_EN = 1
40
--
200
OCFB_EN = 1
40
--
200
OCFB_EN = 1
160
--
800
OCFB_EN = 1
60
--
300
OCFB_EN = 1
120
--
600
ISHORTLIM_LD O1
ISHORTLIM_LD O2
ISHORTLIM_LD Output Short Current Limit
O3
ISHORTLIM_LD O5
ISHORTLIM_LD O6
ISHORTLIM_LD O7
MediaTek Confidential
µA
V
%
mA
mA
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Page 31 of 210
MT6360 PMIC Datasheet Confidential A Parameter
Symbol
VDROP_LDO6/7
Test Conditions I_LOAD1 = 150mA, I_LOAD2 = 200mA, I_LOAD3 = 200mA, I_LOAD5 = 800mA I_LOAD6 = 300mA, I_LOAD7 = 600mA
I_LDO1
VDROP_LDO1/2 Dropout Voltage
Rated Load Current (I_rated)
/3/5
--
--
350
I_rated ≤ 150mA
--
--
150
I_LDO2
I_rated ≤ 200mA
--
--
200
I_LDO3
I_rated ≤ 200mA
--
--
200
I_LDO5
I_rated ≤ 800mA
--
--
800
I_LDO6
I_rated ≤ 300mA
--
--
300
I_LDO7
I_rated ≤ 600mA
--
--
600
--
45
--
PSRRLDO1/2/3
1. I load ≤ I_rated 2. Freq = 50Hz to 1kHz 1. I load ≤ I_rated 2. Freq = 1kHz to 10kHz
--
30
--
--
15
--
--
15
--
--
75
--
--
55
--
--
40
--
--
25
--
1. I load ≤ I_rated 2. Freq = 10kHz to 100kHz 1. I load ≤ I_rated 2. Freq = 100kHz to 1MHz 1. I load ≤ I_rated 2. Freq = 50Hz to 1kHz 1. I load ≤ I_rated 2. Freq = 1kHz to 10kHz 1. I load ≤ I_rated 2. Freq = 10kHz to 100kHz 1. I load ≤ I_rated 2. Freq = 100kHz to 1MHz VOUT_LDO = 90% of VOUT_LDO (Target)
--
--
1000
tSS_LDO3/5
VOUT_LDO = 90% of VOUT_LDO (Target)
--
--
1000
tSS_LDO6
VOUT_LDO = 90% of VOUT_LDO (Target)
--
--
2000
tSS_LDO7
VOUT_LDO = 90% of VOUT_LDO (Target)
--
--
3300
toff_LDO1/2/3/7
VOUT_LDO = 10% of VOUT_LDO (Target)
--
--
2000
toff_LDO5
VOUT_LDO = 10% of VOUT_LDO (Target)
--
--
1500
toff_LDO6
VOUT_LDO = 10% of VOUT_LDO (Target)
--
--
1000
IIQ_NM_LDO1/2 ILOAD = 0mA, LDO1/2/3 is from LDO_VIN1, LDO5 is from /3/5 LDO_VIN2, not include base Iq.
--
--
32
ILOAD = 0mA, LDO6 is from LDO_VIN2 and LDO_VIN3, not
--
--
169
ILOAD = 0mA, LDO7 is from LDO_VIN2 and LDO_VIN3, not include base Iq.
--
--
143
I
IIQ_NM_LDO7
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mA
dB
tSS_LDO1/2
Soft-Start Time
Unit
mV 100
PSRRLDO6/7
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Max
--
Power Supply Rejection Ratio (PSRR)
Normal Mode Quiescent
Typ
--
/5
Power Off Time
Min
µs
µs
µA
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MT6360 PMIC Datasheet Confidential A Parameter
Low Power Mode Quiescent Current
I2C Characteristics LOW-Level Input Voltage HIGH-Level Input Voltage LOW-Level Output Voltage Input Current Each IO Pin
Symbol
Test Conditions
Min
Typ
Max
IIQ_LP_LDO1/2/ ILOAD = 0mA, LDO1/2/3 is from LDO_VIN1, LDO5 is from 3/5 LDO_VIN2, not include base Iq.
--
--
16
IIQ_LP_LDO6
ILOAD = 0mA, LDO6 is from LDO_VIN2 and LDO_VIN3, not include base Iq.
--
--
20
IIQ_LP_LDO7
ILOAD = 0mA, LDO7 is from LDO_VIN2 and LDO_VIN3, not include base Iq.
--
--
17.6
VIL_I2C
--
--
0.4
V
VIH_I2C
1.2
--
--
V
--
--
0.4
V
-10
--
10
µA
CB ≤ 100pF
--
--
3.4
100pF ≤ CB ≤ 400pF
--
--
1.7
VOL_I2C
Open-drain
IIN_I2C
0.1 x VDD < VI < 0.9 x VDD(MAX)
SCL Clock Frequency fSCL_I2C_HSM
Unit
µA
MHz
Data Hold Time
tDH_I2C
30
--
--
ns
Data Set-Up Time
tDS_I2C
70
--
--
ns
Note 5: A 10kΩ NTC thermistor with β = 3435k is suggested, and a SEMITEC 103KT1608T is in use. Note 6: Quiescent, or ground current, is the difference between input and output currents. It is defined by IQ = IIN - IOUT under no load condition (IOUT = 0mA). The total current drawn from the supply is the sum of the load current plus the ground pin current. Note 7: Guaranteed by design.
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MT6360 PMIC Datasheet Confidential A
3
Typical Operating Characteristics
3.1
Typical Operating Characteristics Charger Efficiency vs. Charger Current 96
94
94
92
92
Charger Efficiency (%)
Charger Efficiency (%)
Charger Efficiency vs. Charger Current 96
90 88
VBUS = 5V
86
VBUS = 9V
84
VBUS = 12V
82 80 78 76
90 88
VBUS = 5V
86
VBUS = 9V
84
VBUS = 12V
82 80 78
VBAT = 3.9V, fSW = 1.5MHz
74
VBAT = 4.35V, fSW = 1.5MHz
76 0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
0.3
0.6
0.9
Charger Current (A)
Boost Efficiency vs. Load Current
1.5
1.8
2.1
2.4
2.7
3.0
CV Regulation vs. Temperature
100
4.50
95
4.45 4.44V
90 85
VBAT = 4.35V
80
VBAT = 4V
75
VBAT = 3.8V
70
VBAT = 3.5V
CV Regulation (V)
Boost Efficiency (%)
1.2
Charger Current (A)
65
4.40 4.35 4.35V 4.30 4.25 4.20
60 4.15
55
VBUS = 5.05V, fSW = 1.5MHz
50
4.10 0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
-50
-25
Load Current (A)
0
25
50
75
100
Temperature (°C)
Figure 3-1. Typical operating characteristics
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125
MT6360 PMIC Datasheet Confidential A
4 4.1
Application Information General Descriptions
The MT6360 is a highly-integrated smart power management IC, which includes a single-cell Liion/Li-polymer switching battery charger, a USB Type-C PD controller, dual Flash LED current sources, a RGB LED driver, two Buck converters, and six LDOs for portable devices.
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MT6360 PMIC Datasheet Confidential A
4.2
VDDA Over-Voltage Protection
The device provides VDDA over-voltage protection (VDDA OVP). If VDDA exceeds VVDDA_OVP, VDDA OVP will be triggered and the channels behavior is decided by register (0x0E[6]) of PMU. There are two options. The first one is that MT6360 only sends interrupt. The other one is not only sends interrupt, but also shuts down all channels except CHG/FLED/PD and reset CHx_EN_CTRLx.
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MT6360 PMIC Datasheet Confidential A
4.3
Over-Temperature Protection
The MT6360 also features over-temperature protection (OTP), and have three sensors of OTP0 (in CHG), OTP1 (in Bucks) and LDO5_OTP. They can be enabled in the registers (0x0E[5],[4] and [2]). The registers (0x0E[3] and [1]) are designed to save the power. When Bucks/LDOs is not in the normal mode, the OTP1 and LDO5_OTP is forced to turn-off. The OTP can be triggered to shut down the device if the junction temperature exceeds TOTP, 150°C typically. The channels which will be turned off can be selected by register (0x0E[7]) of PMU. If the junction temperature drops to TOTP_RECOVER, 110°C typically, the device can be reactivated.
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MT6360 PMIC Datasheet Confidential A
4.4
MRSTB Pin
The device provides a MRSTB pin to manually reset the hardware or registers. This function is enabled by register (0x01[4]) = 1 of PMU. The de-bounce time can be selected by 0x01 bit [3:1], and the reset method can be selected by register (0x01[0]) of PMU. The control diagram is shown below.
Phone turns on
High Level > 1.2V Low Level < 0.4V
AP’s GPIO to driver MRSTB pin
2
Enable MRSTB function and set MRSTB timeout
AP give the I C command to the MT6360
MRSTB_TMR The MT6360 internal reset trigger
Reset trigger. All register reset to default value and MRSTB default is off
Figure 4-1. MRSTB function
As the Figure 4-2. shown, MRSTB can reset the PMU and PD with the register (0x01[4]) of PMU, in addition, it can reset the Bucks and LDOs with register (0x06[7]) of PMU.
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MT6360 PMIC Datasheet Confidential A
MT6360 MRSTB Diagram Reset by VDDA = 0 or ALL_RST = 1
EFUSE BASE 3MOSC
CHG FLED RGB PD
MRSTB_RST
REG_PMU0x01[4]: MREN (default = 0, disable)
MRSTB Bucks LDOs
WDTRST REG_PMU0x06[7]: WDTRST_EN (default = 0, disable)
Figure 4-2. MRSTB diagram
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MT6360 PMIC Datasheet Confidential A
4.5
Switching Charger
The switching charger integrates a synchronous PWM controller with power MOSFETs to provide Minimum Input Voltage Regulation (MIVR), Average Input Current Regulation (AICR), high-accuracy current and voltage regulation, and charge termination. The charger also features OTG (On-The-Go) boost mode. The switching charger has three operation modes: charge mode, boost mode (OTG-Boost), and highimpedance mode. In charge mode, the charger supports a precision charging system for single-cell batteries. In boost mode, the charger works as a boost converter to boost the battery voltage back to the CHG_VIN pin for sourcing OTG devices. In high-impedance mode, the charger stops charging or boosting and operates at a low sinking current from the CHG_VIN pin or the battery to reduce power consumption when the device is in standby mode.
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MT6360 PMIC Datasheet Confidential A
4.6
Charger Mode Operation
4.6.1
Charge Profile
The switching charger provides a precision Li-ion or Li-polymer charging solution for single-cell applications. Input current limit, charge current, end-of-current current, charge voltage, and input voltage MIVR are all programmable via the I2C interface. In charge mode, the switching charger has five regulation loops to control charge current: input current, charge current, charge voltage, input voltage MIVR and device junction temperature. While charging a battery, all five loops (if MIVR is enabled) are enabled, but only one of them will dominate the charging behavior at a time. For normal charging operation, the switching charger starts from pre-charge mode. When the battery voltage rises above a pre-charge threshold voltage (VPRECHG_CHG), the charger enters fast-charge mode. Once the battery voltage approaches the regulation voltage (VOREG_CHG), the charger enters constant voltage mode. Charge Profile
IBAT (ICHG)
IBAT (IPRECHG_CHG)
VOREG_CHG
VBAT & IBAT
VBAT (VOREG_CHG - VRECH_CHG)
VBAT (VPRECHG_CHG) IBAT (IEOC_CHG)
Time Pre-charge stage
Charging State
Fast-charge stage (Constant current)
Fast-charge stage (Constant voltage)
Charge termination stage
R-eharge stage
Figure 4-3. Charge profile
4.6.2
Pre-Charge Mode
To prolong battery life, the battery under low battery condition cannot be charged with a large current. When the VBAT pin voltage is below pre-charge threshold voltage (VPRECHG_CHG), the
chargercurrent is in pre nt equal to a pre-charge (IPRECHG_CHG). There are two control loops in pre-charge mode. One is the ICHG and the other is the SYSREG. If the battery voltage is lower than the VSYS voltage, the BATFET will not be fully turned-on so that the
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MT6360 PMIC Datasheet Confidential A VSYS is not equal to VBAT. That is, the VSYS can be powered by the charger-buck converter rather than the low battery, which is being charged by the pre-charge current. As a result, the system power can be guaranteed in such low battery condition. The pre-charge current levels IPREC (0x18, bit[3:0]) are programmable from 100mA to 850mA in a step of 50mA via the I2C interface.
4.6.3
Fast-Charge Mode and Settings
Once the VBAT pin rises above VPRECHG_CHG, the charger enters fast-charge mode and starts fast charging. Notice that a MUIC integrates input power source detection function, from an AC adapter or USB input, and the switching charger can automatically set the charge current with options accordingly. Different from a linear charger (LDO-based), the switching charger (buck-based) is like a current amplifier because the current sinking to the switching charger is different from the current sourcing into the battery. Average Input Current Regulation (AICR) levels (0x13, bit[7:2]) and output charge current (ICHG) (0x17, bit[7:2]) are all user-programmable.
4.6.4
Cycle-by-Cycle Current Limit
The switching charger features an embedded cycle-by- cycle current limit for output inductor. Once the inductor current reaches the current limit, the charger stops charging immediately to prevent the device from being damaged by the over-current condition. Note the protection can be disabled in no case.
4.6.5
Charging Safety Timer
The device has built-in safety timer to prevent extended charging cycle due to abnormal battery conditions. According to the battery voltage, there are different safety time. The user can program precharge and fast charge safety timer through I2C (WT_PRC and WT_FC bits). When safety timer expires, the CHG_STAT bits are set to11 and the CHG_TMRI_EVT is asserted to the host. The safety timer feature can be disabled by writing 0 to TMR_EN bit. During AICR, MIVR or thermal regulation, the safety timer counts at half clock rate. This half clock rate feature can be disabled by writing 0 to TMR2X_EN bit. During the fault, the charging is stopped and the buck converter continues to operate to supply system load. Once the fault goes away, fault resumes. Timer gets reset by toggling CHG_EN or TMR_EN bits, replugging CHG_VIN.
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MT6360 PMIC Datasheet Confidential A 4.6.6
Charge Current (ICHG)
The charge current into the battery is determined by the sensed power path on-resistance and I2Cprogrammable ICHG setting. The voltage between the VSYS and VBAT pins is regulated to the voltage controlled by the ICHG setting, and the fast-charge currents (ICHG) are I2C programmable from 300mA to 3000mA with a resolution of 100mA.
4.6.7
Constant Voltage Mode (VOREG_CHG)
The switching charger enters constant voltage mode when the VBAT voltage approaches the output regulation voltage (VOREG_CHG). When entering this mode, the fast-charge current (ICHG) will begin to decrease. For default settings (charge current termination (IEOC) function is disabled), the charger will not be turned off and will always regulate the battery voltage at VOREG_CHG. However, if charge current termination (IEOC) function is enabled, the charger will be turned off or battery charging is terminated when the charge current is below an end-of-charge current (IEOC_CHG) in constant-voltage mode. The output regulation voltage is I2C programmable from 3.9V to 4.71V in 10mV steps.
4.6.8
End-of-Charge Current (IEOC_CHG)
If the charge current termination (IEOC) is enabled, the end-of-charge current is determined by the termination current sense voltage. IEOC_CHG can be set via the I2C interface from 100mA to 850mA in 50mA steps. The charge mode is shown as below, and the charge mode which the charger operates in will be determined according to the VBAT level: Battery Voltage Level VBAT
Battery Charge Current IBAT
Trickle Mode
VBAT < 2V
100mA
Pre-charge Mode
VBAT < VPREC (0x18, bit[7:4])
IPREC (0x18, bit[3:0])
Fast-charge Mode
VBAT < VOREG (0x14, bit[7:1])
Charge current is determined by several control loops
End-of-charge Mode
VBAT = VOREG (0x14, bit[7:1])
Charge current decreases naturally
There are 2 register bits related to the CHG_VLX switching of the MT6360: 1.
SEL_SWFREQ (0x11, bit[7]) and SEL_SWFREQ 2 (0x11, bit[5]): • If SEL_SWFREQ is set to 1 and SEL_SWFREQ2 is 0, the switching frequency is 0.75MHz. • If SEL_SWFREQ is set to 0 or 1 and SEL_SWFREQ2 is 1, the switching frequency is 1MHz. • If SEL_SWFREQ is set to 0 and SEL_SWFREQ2 is 0, the switching frequency is 1.5MHz (default). 2. FIXFREQ (0x11, bit[6]): • If FIXFREQ is disabled (set to 0), the charge switching frequency would be varied when VCHG_VIN is closed to VBAT.
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MT6360 PMIC Datasheet Confidential A •
If FIXFREQ is enabled (set to 1), the charger switching frequency is fixed.
There are 4 charger-related enable bits: 1. CFO_EN (0x12, bit[1]): The CFO_EN bit is used to enable or disable charge mode and boost mode of the charger. 2. CHG_EN (0x12, bit[0]): When the CHG_EN bit is disabled, the power path BATFET will be turned off so that the no charge current will go into the battery. That is, the input power source continuously delivers power to the system but does not charge the battery. However, if the system load is higher than the input source current limit, the power path BATFET will be immediately turned back on so that the battery power can help supply the system. The CHG_EN bit function is the same as that of the CHG_ENB pin. 3. HZ (0x11, bit[2]): When the HZ bit is enabled, most of the internal circuits of the charger will be turned off to reduce quiescent current. 4. Force_Sleep (0x11, bit[3]): When the Force_Sleep bit is enabled, charger-buck will not switching In end-of-charge mode, if EOC_EN (0x19, bit[3]) is enabled, once the charge current is lower than IEOC (0x19, bit[7:4]) level and within CHG_TDEG_EOC (0x19, bit[2:0]), the PMIC will send out IRQB and CHG_IEOCI_EVB = 1 (0xD4, bit[7]). Then, the PMIC will start to check statuses of the following three bits. 1.
TE (0x12, bit[4]): If this bit is enabled, the power path will be turned off, and the buck of the charger will keep providing power to the system. 2. EOC_TIMER (0x17, bit[1:0]): With CHG_IEOCI_EVB = 1, the power path will not be turned off. The PMIC can keep charging the battery for 30 to 60 minutes to extend battery charging capacity.
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MT6360 PMIC Datasheet Confidential A
4.7
OTG Mode Operation
The MT6360 also supports OTG mode and enters OTG mode via OPA_MODE (0x11, bit[0]). It not only provides several output current limit protection levels, but also has low battery protection for overall system considerations. The MT6360 can select switching frequency via SEL_SWFREQ (0x11, bit[7]), no matter whether the MT6360 already operates in OTG mode or not. The MT6360 also provides UUG_ON (0x1D, bit[1]) bit, which can be applied to different applications. If OTG mode and UUG_ON are enabled, the boost-mode output is on the CHG_VIN pin, which can be used for OTG (On-the-Go) mode in mobile phones. 2. If OTG mode is enabled and UUG_ON bit is disabled, the boost-mode output is on the CHG_VMID pin, which can be used in power banks; that is, adapter power can be delivered to PD-powered devices directly. 1.
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MT6360 PMIC Datasheet Confidential A
4.8
Shipping Mode
From a manufacturer to an end user, it may take long time for products to travel. In view of this, the MT6360 provides shipping mode to further minimize battery leakage. After enabling SHIP_MODE (0x12, bit[7]), the MT6360 will shut down internal circuits to reduce quiescent current. The delay time for BATFET to be turned off can be selected by BATDET_DIS_DLY (0x12, bit[6]). Several ways to exit shipping mode are listed below. 1. 2. 3. 4.
Input power source is plugged in. Disable SHIP_MODE bit. CHG_QONB pin is pulled from Logic High to Logic Low within 0.9 second. Enable ALL_RST (0x02, bit[7]) to reset all registers to default values.
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MT6360 PMIC Datasheet Confidential A
4.9
Power Up from CHG_VIN
When the VBUS is plugged in, the power up sequence is as listed: 1. Power Up CHG_VDDP 2. CHG_VMID 3. VDDM 4. CHRDETB 5. Poor Source Detection 6. Input Source Selection: IINLMTSEL, Input Source Type Detection is based on D+/D–, CHG_ILIM 7. Average Input Current Regulation (AICR) 8. Minimum Input Voltage Regulation (MIVR) 9. Buck Converter Power-up
4.9.1
Power Up CHG_VDDP Regulation
PWM low-side driver positive supply output. Internally, the CHG_VDDP is connected to the anode of the boost-strap diode. If the VBUS is plugged in, the CHG_VDDP will be powered by the CHG_VIN and regulated to 4.9V. If the VBUS is unplugged, the charger will operate in sleep mode and the CHG_VDDP voltage will be 0V.
4.9.2
CHG_VMID
The connection point between the reverse-blocking MOSFET and the high-side switching MOSFET. After the VBUS is plugged in for 120ms, it will be connected to the CHG_VMID MIN by turning on the UUG.
4.9.3
VDDM and VDDA
The VDDM power is from the VBAT directly or the CHG_VMID Regulator output. The VDDA is connected with the VDDM on PCB. VSYS Power Path Controller VBAT
VDDM
VDDM Power Selection CHG_VIN
CHG_VMID VDDA UUG
VDDM Regulator
Figure 4-4. VDDM power plan
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MT6360 PMIC Datasheet Confidential A 4.9.4
CHRDETB Function
Detect the VBUS and CC1/CC2 state for power-on conditions. UVLO < VBUS < OVP or CC attached CHRDETB = LOW VBUS < UVLO/VBUS > OVP and CC detached CHRDETB = HIGH Table 4-1. CHRDETB status CHRDETB status
VBUS < UVLO
UVLO < VBUS < OVP
VBUS > OVP
CC attached CC detached
L H
L L
L H
UVLO threshold = 2.6 to 3.7V, 100mV per step OVP threshold = 6, 6.5, 7, 7.5, 8.5, 9.5, 10.5, 11.5, 12.5, 14.5V
4.9.5
Poor Source Detection
After the CHG_VDDP is powered up, the device checks the current capability of the input source. The input source has to meet following requirements to turn on the buck. • The CHG_VIN voltage is below VCHG_VIN_OVP • The CHG_VIN voltage is above VBAD_ADP_CHG pulling IBAD_ADP_SINK_CHG (typical 50mA) Once the CHG_VIN source passes all of the above conditions, the status register bit PWR_RDY is asserted high and the INT pin signals the master. If the device does not pass the poor source detection, the poor source detection is repeated every 2 seconds.
4.9.6
Input Source Selection
The host can over-write the ILIM_EN or the IINLMTSEL register to change the input current limit if needed.
4.9.6.1
IINLMTSEL
This flexible setting is suitable for wide applications of adapters: 1) If IINLMTSEL = 00, the input current limit is decided by the lower one of IAICR = 3.25A and the current limit is set by the CHG_ILIM pin. 2) If IINLMTSEL = 01, the input current limit is decided by the lower one of CHG_TYP results and the current limit is set by the CHG_ILIM pin. 3) If IINLMTSEL = 10, the input current limit is decided by the lower one of IAICR register value and the current limit is set by the CHG_ILIM pin. 4) If IINLMTSEL = 11, the input current limit is decided by the lower one of IAICR = 3.25A, CHG_TYP, IAICR register value and the current limit is set by the CHG_ILIM pin.
4.9.6.2 After the CHG_VIN voltage is above CHG_VIN UVLO, the device runs input source detection through D+/D– when the USBCHGEN bit is set. The MT6360 follows the USB Battery Charging Specification 1.2 (BC1.2) to detect input source (NSDP/SDP/CDP/DCP). After input source type detection is completed, an INT pulse is asserted to the host.
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MT6360 PMIC Datasheet Confidential A Table 4-2. Adapter detection
4.9.6.3
CHG TYPE
AICR setting
SDP CDP DCP
500mA 1500mA 3250mA
CHG_ILIM
For hardware protection, the device has an additional hardware pin on ILIM to limit maximum input current on the ILIM pin. The input maximum current is set by a resistor from the ILIM pin to ground as: IINMAX = KILIM / RILIM For example, if the input current limit is to be set as 2A with a typical input current limit factor KILIM as 355AΩ, a resistor of 180Ω will then be chosen as the resistor from the CHG_ILIM pin to ground. The actual input current limit is the result of smaller value between IINLMTSEL and CHG_ILIM.
4.9.7
Average Input Current Regulation (AICR)
The AICR current setting is programmed via the I2C interface. For example, AICR 100mA Mode limits the input current to 100mA, and AICR 500mA Mode to 500mA. If not needed, this function can be disabled. The AICR current levels are in the range of 100mA to 3250mA with a resolution of 50mA.
4.9.8
Minimum Input Voltage Regulation (MIVR)
The switching charger features Minimum Input Voltage Regulation function to prevent input voltage from dropping due to insufficient current provided by the adapter or USB input. If MIVR function is enabled, the input voltage decreases when the over current of the input power source occurs. VCHG_VIN is regulated at a predetermined voltage level which can be set from 3.9V to 13.4V in 0.1V steps via I2C interface. At this time, the current drawn by the switching charger equals the maximum current value that the input power can provide at the predetermined voltage level, instead of the set value.
4.9.9
Converter Power-Up
After the AICR is set, the converter is enabled and starts switching. The BATFET stays on unless charger is disabled (CHG_EN = 0) or enters shipping mode (SHIP_MODE = 0). The device integrated a synchronous PWM controller with 1.5MHz switching frequency, high-accuracy current and voltage regulation. The device also supports PFM control to improve light-load efficiency.
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MT6360 PMIC Datasheet Confidential A
4.10
MediaTek Pump Express+ (MTK, PE+)
The MT6360 can provide an input current pulse to communicate with an MTK-PE+ high voltage adapter. When EN_PUMPX is enabled, the host can increase or decrease adapter output voltage by setting PUMPX_UP_DN to the desired value. After enabling either one of them, the MT6360 will generate a CHG_VIN current pattern for the MTK-PE+ adapter to automatically identify whether to increase or decrease output voltage (CHG_VIN pin). Once the current pattern generation is finished, IRQB will be triggered accordingly to request the processor to read the registers.
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MT6360 PMIC Datasheet Confidential A
4.11
Interrupt
The MT6360 reports status to host (CPU, MCU, EC, or etc.) by the IRQB (interrupt command to host) pin, which is an open-drain output. The IRQB pin goes low when any fault occurs. It will be automatically reset when all the fault events are cleared. The IRQB pin is used to indicate whether the MT6360 has any PMU, PMIC, LDO events. If an application processor (AP) detects a falling edge on the IRQB pin, the AP will start to read the IRQB registers 0xD0 through 0xDF sequentially.
INT_RETRIGGER
INT_RET
16/32/64/128µs
STAT# Write Clear EVT#
IRQB
Figure 4-5. IRQB pin diagram
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MT6360 PMIC Datasheet Confidential A
4.12
CHG_VBATOVPB Pin
Battery over-voltage protection (BAT OVP) indication is accomplished by the open-drain and activelow output, CHG_VBATOVPB: It is low if BAT OVP occurs; otherwise, it is high.
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MT6360 PMIC Datasheet Confidential A
4.13
Analog IR Drop Compensation
The resistance between the charger output and the battery cell terminal may cause the charger to enter constant voltage operation mode from constant current operation mode too early, and thus increase the battery charging time. To reduce the battery charging time to speed up charge cycle, the MT6360 provides IR compensation function so that the charger has more precise control over the timing that the charger operates in constant current mode, which has the maximum charge current. Host (AP) can set IR compensation function by programming the register bits BAT_COMP (0x2C, bit[5:3]) and VCLAMP (0x2C, bit[2:0]). The formula is as below: VACTUAL = V + min. (ICHG (Actual) x BAT_COM, VCLAMP)
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MT6360 PMIC Datasheet Confidential A
4.14
CHG_ILIM Pin
For hardware protection, the MT6360 supports input current limit setting on the CHG_ILIM pin by way of a resistor from CHG_ILIM pin to ground. IINMAX = KILIM / RILIM For example, if the input current limit is to be set as 2A with a typical input current limit factor KILIM as 355AΩ, a resistor of 180Ω will then be chosen as the resistor from the CHG_ILIM pin to ground. The actual input current limit is the result of smaller value between IINLMTSEL (0x12, bit[3:2]) and CHG_ILIM.
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MT6360 PMIC Datasheet Confidential A
4.15
ADC Conversion Operation Flow
The figure below shows the flow chart of ADC conversion operation. ADC conversion starts from selecting an ADC channel by setting ADC_RPT_SEL(0x5A,[7:4]), ADC_CHx_EN (0x56, bit[2:0] and 0x57, bit[7:0]). After about 26ms of ADC conversion time for one channel conversion to be completed, ADC_DONEI (0xD5, bit[4]) will be enabled. The host can be informed that ADC conversion is completed by reading the register bits.
ADC Conversion Starts
Set ADC channel ADC_RPT_SEL(0x5A[7:4]), ADC_CHx_EN (0x56, bit[2:0]) & (0x57, bit[7:0]) and Start ADC conversion
Check ADC conversion complete ADC_DONEI (0xD5, bit4) = 1
Read ADC code ADC_PRT_CH (0x5A[3:0]), ADC_RPT_H (0x5B[7:0]), ADC_RPT_L (0x5C[3:0]) and Calculate measurement
Finish ADC Conversion
Figure 4-6. ADC conversion operation flow The host can read ADC channel from ADC_RPT_CH(0x5A,[3:0], ADC high-byte codes from ADC_RPT_H (0x5B, bit[7:0]) and low-byte codes from ADC_RPT_L (0x5C, bit[7:0]) to calculate the measured voltage/current/temperature data with respect to each ADC channel. The table below shows measurement equations for various ADC channels. ADC Channel Measurement Equation Measurement Range CHG_VIN_DIV5 [(ADC_CODEH x 256) + ADC_CODEL] x 6.25mV 1V to 22V CHG_VIN_DIV2 [(ADC_CODEH x 256) + ADC_CODEL] x 2.5mV 1V to VDDA x 2 VBAT [(ADC_CODEH x 256) + ADC_CODEL] x 1.25mV 0V to VDDA VSYS [(ADC_CODEH x 256) + ADC_CODEL] x 1.25mV 0V to VDDA IBUS [(ADC_CODEH x 256) + ADC_CODEL] x 2.5mA x 0.76 0A to 0.4A IAICR[7:2] setting < 400mA
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MT6360 PMIC Datasheet Confidential A ADC Channel Measurement Equation Measurement Range IBUS [(ADC_CODEH x 256) + ADC_CODEL] x 2.5mA 0A to 5A IAICR[5:0] setting ≥ 400mA IBAT [(ADC_CODEH x 256) + ADC_CODEL] x 2.5mA 0A to 3A ICHG[5:0] setting ≥ 300mA TEMP_JC [(ADC_CODEH x 256) + ADC_CODEL] x 1.05°C - 80°C -40°C to 120°C VREF_TS [(ADC_CODEH x 256) + ADC_CODEL] x 1.25mV 0V to VDDA TS [(ADC_CODEH x 256) + ADC_CODEL] x 1.25mV 0V to VDDA USB_ID [(ADC_CODEH x 256) + ADC_CODEL] x 1.25mV 0V to VDDA - 1.2
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MT6360 PMIC Datasheet Confidential A
4.16
USB_PD
The PD function of the MT6360 complies with USB Type-C Port Controller Interface spec 3.0. Some “Not support” functions are listed in the register table.
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MT6360 PMIC Datasheet Confidential A
4.17
Type-C Detection
The USB_PD implements multiple comparators which can be used by software to determine the state of the PD_CC1, PD_CC2 pins. This status information provides the host processor all of the information required to determine attach and detach status of the cable. The USB_PD has three threshold comparators, which match the USB Type-C specification for the three charge current levels, which can be detected by a Type-C device. These comparators can automatically trigger interrupts to occur when there is a state change.
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MT6360 PMIC Datasheet Confidential A
4.18
Detection through Autonomous DRP Toggles
The USB_PD has the capability to do autonomous DRP toggles. In DRP toggles, the MT6360 implements DRP toggle between SRC (source) and SNK (sink). It can also present as a SRC or SNK only and monitor PD_CC1, PD_CC2 status.
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MT6360 PMIC Datasheet Confidential A
4.19
PD Protocol Communication
Type-C connectors allow USB Power Delivery (PD) to communicate over the connected PD_CCx pins between two ports. The communication method is the BMC Power Delivery protocol. Possible usages are outlined below: • • • •
Negotiating and controlling power levels Alternate mode interfaces, such as Display Port Role swap for dual-role ports, switchable between as the source or sink Communication with USB Type-C full featured cables
The USB_PD integrates a BMC PD block, which includes a BMC physical layer and packet buffer, which allow packets to be sent and received by host software through I2C. The USB_PD allows host software to implement all features of the USB BMC PD through writes and reads of the buffer and control of the USB_PD physical interface. Table 4-3. USB PD abbreviations Term BMC TCPC TCPCI TCPM
Description Biphase Mark Coding Type-C Port Controller Type-C Port Controller Interface Type-C Port Manager
Type-C Port Manager Policy Engine Protocol Layer INT_N In
I2C Master
TCPC Interface
INT_N Out
I2C Slave
Tx/Rx Buffer GoodCRC/Retry Physical Layer Type-C CC Logic
Figure 4-7. Type-C port controller (TCPC) interface
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MT6360 PMIC Datasheet Confidential A The Type-C Port Controller Interface, TCPCI, is the interface between a Type-C Port Manager and a Type-C Port Controller. •
The Controller Interface uses the I2C protocol:
•
The TCPM is the only master on this I2C bus.
•
The TCPC is a slave device on this I2C bus.
• • •
The TCPC supports Fast-Mode bus speed. The TCPC has an open-drain output, active-low PD_IRQB pin. This pin is used to indicate change of state, where the PD_IRQB pin is asserted when any Alert Bits are set. The TCPCI supports I/O nominal voltages of 1.8V and 3.3V.
•
The TCPC supports auto-increment of the I2C internal register address for the last byte transferred during a read, independent of an ACK/NACK from the master.
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MT6360 PMIC Datasheet Confidential A
4.20
FLED Flow Chart
The MT6360 provides torch mode and strobe mode operation for FLED application. Torch mode power supply by the battery directly and the strobe mode power supply by the battery operating in OTG mode. There are two power switches to select the power loop. In torch mode, the FL_VINTORCH turn on to connect to battery. In strobe mode, the CHG_VIN voltage is detected avoiding the high voltage stress to turn on the FLED. The charger will operate in OTG mode to provide the power in strobe mode.
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MT6360 PMIC Datasheet Confidential A
FLED OFF
No
TORCH Enable?
STROBE Enable?
No
( GPIO : FL_STROBE=0 →1 or FL_STROBE_reg=0 →1)
( GPIO : FL_TORCH=1 or FL_TORCH_reg=1)
Yes Yes
Yes CHG_VIN ≥ 5.6V ?
No
Turn ON FL_VINTORCH
Turn ON FL_VMID
Turn ON FLED_OTG
No CHG SSEND = 1
Yes Turn ON FLED Current Source Turn ON FLED Current Source No
STROBE Enable? Yes
No STROBE Timeout?
Yes TORCH Disable? No
Turn OFF FLED_OTG
Yes
Turn OFF FLED Current Source
Turn OFF FLED Current Source
Turn OFF
Turn OFF
FL_VMID
Figure 4-8. FLED flow chart
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MT6360 PMIC Datasheet Confidential A
4.21
Strobe Mode Operation
The MT6360 provides 117 different current levels from 25mA to 750mA in steps of 6.25mA or 50mA to 1500mA in steps of 12.5mA in strobe mode. FLED1 and FLED2 strobe currents can be programmed by register 0x74[6:0] and register 0x78[6:0] for flash brightness. The two channels can support totally up to2.5A. The following figure shows that when strobe target current is higher than timeout current level, it will be terminated by the strobe timeout period to elapse. FLED turns off completely after the strobe timeout which is set by register 0x73[6:0] for strobe LED1 and LED2. If the strobe target current is lower than timeout current level, it will keep lighting even the timeout is finished.
FL_STROBE FLCS1_EN (REG0x7E[1]) FLCS2_EN (REG0x7E[0]) FL_LEDCS1 (Current)
FLED_STRB_TO
FLED_STRB_TO
FL_LEDCS2 (Current)
FLED_STRB_TO FL_LEDCS2 off when FLCS2_EN low
Note: If FLCS1_EN/FLCS2_EN = “0”, FLED will not be turned on even FL_STROBE enable. Figure 4-9. FLCS1_EN and FLCS2_EN (FL_STROBE)
FL_STROBE_reg reset to “0” when FLED_STRB_TO finish FL_STROBE_reg FLCS1_EN (REG0x7E[1]) FLCS2_EN (REG0x7E[0]) FL_LEDCS1 (Current)
FLED_STRB_TO
FLED_STRB_TO
FL_LEDCS2 (Current)
FLED_STRB_TO FL_LEDCS2 off when FLCS2_EN low
Note: If FLCS1_EN/FLCS2_EN = “0”, FLED will not be turned on even FL_STROBE register is set “1”. Figure 4-10. FLCS1_EN and FLCS2_EN (FL_STROBE_reg)
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MT6360 PMIC Datasheet Confidential A
4.22
Torch Mode Operation
The MT6360 provides 31 different current levels from 25mA to 400mA in steps of 12.5mA. FLED1 and FLED2 torch currents can be programmed by reg0x75[4:0] and reg0x79[4:0] for torch brightness. Once torch mode is enabled, the current sources will ramp up to the programmed torch current.
FL_TORCH FLCS1_EN (REG0x7E[1]) FLCS2_EN (REG0x7E[0]) FL_LEDCS1 (Current) FL_LEDCS2 (Current)
Note: If FLCS1_EN/FLCS2_EN = “0”, FLED will not be turned on even when FL_TORCH is enabled. Figure 4-11. FLCS1_EN and FLCS2_EN (FL_TORCH)
FL_TORCH_reg FLCS1_EN (REG0x7E[1]) FLCS2_EN (REG0x7E[0]) FL_LEDCS1 (Current) FL_LEDCS2 (Current)
Note: If FLCS1_EN/FLCS2_EN = “0”, FLED will not be turned on even when FL_TORCH register is set to “1”. Figure 4-12. FLCS1_EN and FLCS2_EN (FL_TORCH_reg)
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4.23
FL_TXMASK Function
The strobe current setting can be changed to torch current level setting by reg0x75[4:0] and reg0x79[4:0] when the FL_TXMASK pin goes high during strobe operation. It can release the current from torch to strobe when FL_TXMASK pin goes low within the timeout period.
FL_STROBE FL_TXMASK Current Level (FLED_ISTRB) Current Level (FLED_ITOR)
FL_LEDCS# (Current)
Note: TXActiveLevel = 1, TXSEL ≠ Figure 4-13. FL_TXMASK function
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MT6360 PMIC Datasheet Confidential A
4.24
FLED Short Protection
The device features a built-in protection against flash LED failures result from short-circuit. When the FL_LEDCS1 or FL_LEDCS2 voltage is lower than 1V, the current source will be clamped to 320µA to prevent the over load issue.
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MT6360 PMIC Datasheet Confidential A
4.25
Input Capacitor Selection
Input ceramic capacitor of 4.7µF is recommended for FL_VMID pin. For better voltage filtering, ceramic capacitor with low ESR is recommended. The best performance of the Flash LED can be achieved by using the capacitor of large capacitance. X5R and X7R types are suitable because of their wider voltage and temperature ranges.
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MT6360 PMIC Datasheet Confidential A
4.26
FLED Strobe Mode Supply Limit
When the adapter supply power is higher than VOVP_STRB_FL (typ. 5.6V), the flash LED will not work to protect the internal circuit.
FL_STROBE or FL_STROBE_reg
TA Plug (CHG_VIN ≥ 5.6V) FL_LEDCS (Current)
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MT6360 PMIC Datasheet Confidential A
4.27
Low Battery Voltage Protection (LBP)
When the battery voltage is lower than a specified value, the FLED will be turned off. Until the battery voltage rises above the low battery voltage protection threshold plus hysteresis voltage value, the FLED resumes turn-on. The low battery voltage protection can be programmed with register 0x1A[7:4] for 16 different levels (2.7V to 3.8V, 0.1V step).
4.27.1
Charger adapter (CHG_VIN < VOVP_STRB_FL (typ. 5.6V)) plug in/out
If a charger power input VCHG_VIN < VOVP_STRB_FL (typ. 5.6V) is plugged in/out, the flash LED current sources will operate the same as described before, as shown in Figure 4-14. and Figure 4-15. for torch mode and strobe mode, respectively.
FL_TORCH or FL_TORCH_reg
TA Plug (CHG_VIN < 5.6V) FL_LEDCS (Current)
Figure 4-14. Torch case (CHG_VIN < 5.6V)
FL_STROBE or FL_STROBE_reg
TA Plug (CHG_VIN < 5.6V) FL_LEDCS (Current)
Timeout
Figure 4-15. Strobe case (CHG_VIN < 5.6V)
4.27.2
Charger adapter (CHG_VIN ≥ 5.6V) plug in/out
When charger adapter (CHG_VIN ≥ 5.6V) is plugged in, there is no influence on FLED operation with flash mode forand the FLED output current will be interrupted immediately with torch mode protection.
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MT6360 PMIC Datasheet Confidential A FL_ TORCH or FL_ TORCH_reg
TA Plug ( CHG_VIN ≥ 5.6V) FL_LEDCS (Current)
Figure 4-16. Torch case (CHG_VIN ≥ 5 .6V)
FL_STROBE or FL_STROBE_reg
TA Plug (CHG_VIN ≥ 5.6V) FL_LEDCS (Current)
Figure 4-17. Strobe case (CHG_VIN ≥ 5.6V)
4.27.3
FLED operation with Charger in OTG mode
The CHG_VMID voltage level will change from strobe mode setting to OTG setting when the OTG function is enabled. FL_ TORCH or FL_ TORCH_reg
CHG_ OTG
FL_LEDCS (Current)
CHG_ VMID
VOBST
Figure 4-18. Torch case with OTG
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MT6360 PMIC Datasheet Confidential A FL_ STROBE or FL_ STROBE_reg
CHG_ OTG
FL_LEDCS (Current)
Timeout
VOBST CHG_ VMID
V_FL
Figure 4-19. Strobe case with OTG
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MT6360 PMIC Datasheet Confidential A
4.28
FLED Power Control
Below is the block diagram of the FLED power control. In strobe mode the power goes through M3 and M4 from M1 to drive FLED. In torch mode the power goes through M3 from M2 to drive FLED. The driver features discharge function. When FLED is disable, the R_disch can be selected by pulled_low_R[0]. FL_TORCH (PIN), AMR = 6V M2
FL_VMID (PIN), AMR = 22V
Power Select M1
Strobe on Torch on Ultra_ISTRB1 [0] *2
Open/Short
Power MOS Select
M4 M3 Power MOS Driver 1:1
FL_LEDCSX (PIN)
FLEDX Driver 2.5kΩ
Pulled_LOW_R [0]
20k Ω
Pulled Low R CTRL
*2 : default short Torch on, open Strobe on, short Strobe on and Ultra_ISTRB1 = 1, open
Figure 4-20. FLED power control block diagram
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MT6360 PMIC Datasheet Confidential A
4.29
FLED Core Control
Below is the flow chart of the FLED core control. The FLED driver can be enabled by either FL_STROBE (PIN) or FL_STROBE_reg [0], and it is the same when the IC is in FL_TORCH mode. The current level is selected by FLEDX_ISTRB[6:0] and FLEDX_ITOR[4:0]. FLEDX_ISTRB[6:0] FLEDX_ITOR[4:0]
FLEDX_TCL[2:0]
FLED_STRB_LES [0]
Input PIN CTRL
FL_STROBE (PIN)
Current Level Comparator
FLEDX Driver Strobe on Time Out CTRL *1
FL_STROBE_reg [0] FLCSX_EN [0]
FLED Current CTRL
Torch on
FL_TORCH_reg [0] FLED_STRB_TO[6:0] FL_TORCH (PIN)
TXCTRL[1:0] TXSEL[1:0] FL_TXMASK (PIN)
TX CTRL
*1 : Time Out CTRL is only for strobe turned on. Torch turned on is without time out setting.
Figure 4-21. FLED core control block diagram
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4.30
RGB LED Driver
The MT6360 integrates a three-channel RGB LED driver, designed to provide a variety of lighting effects for mobile device applications. The RGB LED driver includes a smart LED string controller, and it can drive 3 channels of LEDs with a sink current of up to 24mA. The default setting of RGB_ISINK1 is auto mode for CHG_VIN power good indicator, and RGB_ISINK1 also supports software mode. It provides three operation modes for the RGB LEDs: flash mode, breath mode, and register mode. The device can increase or decrease the brightness of the RGB LEDs upon command via the I2C interface. To VSYS
RGB_ISINK1 RGB_ISINK2 RGB_ISINK3 RGB_PGND
RGB Driver
Figure 4-22. RGB LED driver application circuit
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MT6360 PMIC Datasheet Confidential A
4.31
Flash Mode
The MT6360 features a built-in flash mode control by setting ISINKx_DIM_MODE to register 0x81/82/83 [7:6] = 00. The RGB_ISINK1 to RGB_ISINK3 of the MT6360 can provide up to 24mA per string. There are 13 steps of LED current control by setting ISINKx_CUR_SEL each channel. The ON/OFF of the current source is synchronized to the PWM signal. The frequency of LED current is equal to the PWM input signal that is setting by ISINKx_DIM_FSEL. In order to guarantee the PWM resolution, the dimming frequency have to be operated at range of 0.125Hz to 256Hz that is selected by ISINKx_DIM_FSEL.
…
24 mA
4 mA
Current
2 mA 1 mA 0 mA
Time Frequency Duty 256 steps
Figure 4-23. RGB flash mode operating principle
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MT6360 PMIC Datasheet Confidential A
4.32
Breath Mode
In the breath mode, the 3 channels of the MT6360 can provide up to 24mA per string. There are 13 steps of LED current control by setting register ISINKx_CUR_SEL each channel. In order to provide a smooth breath mode, there are 6 period timing to control the rising time and falling time, and it is controlled by setting register ISINKx_VREATH_TON_SEL, BISINKx_BREATH_TOFF_SEL, BISINKx_BREATH_Trx_SEL and ISINKx_BREATH_Tfx_SEL. In breath mode, the sink current works like PWM output with 256Hz and controls the duty which is similar to the breath up and down. Please refer to Figure 4-24. below, when the duty cycle increases, the current increases, and vice versa. The human eyes filter the PWM current with the frequency that is higher than 100Hz.
…
24 mA
IRGB
4 mA 2 mA 1 mA 0 mA
Time tOFF
tr1
tr2
tON
tf1
tf2
…
24 mA
IRGB (After eye filter)
4 mA
Current
2 mA 1 mA 0 mA
Time tOFF
tr1
tr2
tON
tf1
tf2
Figure 4-24. RGB breath mode operating principle
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MT6360 PMIC Datasheet Confidential A
4.33
Register Mode
The MT6360 features a built-in register mode control by setting ISINKx_DIM_MODE to 1X. The register ISINKx_SFSTR_EN controls the soft-start time ON/OFF. If ISINKx_SFSTR_EN is enable, ISINKx_SFSTRx_TC can select soft-start time for the each step. The three channels of the MT6360 can provide up to 24mA per string. There are 13 steps of LED current control by setting register ISINKx_CUR_SEL each channel.
…
24 mA
4 mA
Current
2 mA 1 mA 0 mA
Time
Figure 4-25. RGB register mode operating principle
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MT6360 PMIC Datasheet Confidential A
4.34
Low Dropout Regulator (LDOs) and Application Reference Table 4-4. LDO types and brief specifications
Type
LDO Name
Input Power Domain
Controller Power Domain
DLDO DLDO DLDO DLDO DLDO SLDO
LDO1 LDO2 LDO3 LDO5 LDO6 LDO7
VSYS VSYS VSYS VSYS VDRAM1 VDRAM1
VSYS VSYS VSYS VSYS VSYS VSYS
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Output Voltage (V) 1.8V 1.8V 3.0V 2.95V 0.75V 0.6V
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Imax (mA)
Application
150mA 200mA 200mA 800mA 300mA 600mA
Finger Print Touch Panel MSDC SD card VMDDR DRAM
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MT6360 PMIC Datasheet Confidential A
4.35
SD_CARD_DET_N Pin
The device provides a SD_CARD_DET_N pin to detect an SD card removal with a micro-SD socket. This function is enabled by 0x0c bit [6] = 1 and active level can be selected by 0x0c bit [7]. When SD card is removed, this pin will control to disable the LDO5.
Active High LDO5
SDCARD_DET_N
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Active Low LDO5
SDCARD_DET_N
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MT6360 PMIC Datasheet Confidential A
4.36
I2C Interface
The following table shows the MT6360 unique address as a PMU, PMIC, LDO or PD slave to AP, respectively.
MSB 011010 MSB 001101 MSB 110010 MSB 100111
PMU Slave Address LSB R/W Bit 0 1/0 PMIC Slave Address LSB R/W Bit 0 1/0 LDO Slave Address LSB R/W Bit 0 1/0 PD Slave Address LSB R/W Bit 0 1/0
R/W 69/68 R/W 35/34 R/W C9/C8 R/W 9D/9C
The I2C interface also supports High-Speed (HS) mode for data transfer rate up to 3.4Mbits. The I2C timing diagrams are listed below.
Read N bytes from the MT6360 Slave Address
Register Address
S
0
MSB
Slave Address A Sr
A
1
Assume Address = m
R/W
MSB
A Data for Address = m
Data 2
LSB
MSB
Data N
LSB A
A
S
Register Address 0
R/W
A
MSB
Data 1
LSB
A Assume Address = m
P
Data for Address = m + N - 1
Data for Address = m + 1 Write N bytes to the MT6360 Slave Address
LSB
Data 1
A
MSB
Data 2
LSB
A Data for Address = m MSB
A Data for Address = m + 1
Data N
LSB A
P
Data for Address = m + N - 1 Driven by Master,
Driven by Slave, P Stop,
S Start,
Sr Repeat Start
Figure 4-26. I2C timing diagrams
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MT6360 PMIC Datasheet Confidential A
4.37
Thermal Considerations
The junction temperature should never exceed the absolute maximum junction temperature TJ(MAX), listed under Absolute Maximum Ratings, to avoid permanent damage to the device. The maximum allowable power dissipation depends on the thermal resistance of the IC package, the PCB layout, the rate of surrounding airflow, and the difference between the junction and ambient temperatures. The maximum power dissipation can be calculated using the following formula: PD(MAX) = (TJ(MAX) - TA) / θJA where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and θJA is the junction-to-ambient thermal resistance. For continuous operation, the maximum operating junction temperature indicated under Recommended Operating Conditions is 125°C. The junction-to-ambient thermal resistance, θJA, is highly package dependent. For a WL-CSP-103B 4.64x4.14 (BSC) package, the thermal resistance, θJA, is 21.3°C/W on a standard JEDEC 51-7 high effective-thermal-conductivity four-layer test board. The maximum power dissipation at TA = 25°C can be calculated as below: PD(MAX) = (125°C - 25°C) / (21.3°C /W) = 4.69W for a WL-CSP-103B 4.64x4.14 (BSC) package. The maximum power dissipation depends on the operating ambient temperature for the fixed TJ(MAX) and the thermal resistance, θJA. The derating curves in Figure 4-27. allows the designer to see the effect of rising ambient temperature on the maximum power dissipation.
Maximum Power Dissipation (W)1
5.0 Four-Layer PCB 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0
25
50
75
100
125
Ambient Temperature (°C)
power dissipation
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Page 82 of 210
MT6360 PMIC Datasheet Confidential A
4.38
Layout Considerations
The PCB layout is an important step to maintain the high performance of the MT6360. Both the high current and the fast switching nodes demand full attention to the PCB layout to save the robustness of the MT6360 through the PCB layout. Improper layout might show the symptoms of poor line or load regulation, ground and output voltage shifts, stability issues, unsatisfying EMI behavior or worsened efficiency. For the best performance of the MT6360, the following PCB layout guidelines must be strictly followed. • • • • • • •
Keep the main power traces as wide, short and two layers as possible. Directly connect the output capacitors to the remote sense network of each channel to avoid bouncing caused by parasitic resistance and inductance from the PCB trace. Place input capacitor as close as possible to PMID pin and GND pin connections and use shortest copper trace connection or GND plane. Put output capacitor near to the inductor and the IC. Ground connections need to be tied to the IC ground with a short copper trace connection or GND plane. Place inductor input terminal to LX pin as close as possible. Minimize the copper area of this trace to lower electrical and magnetic field radiation but make the trace wide enough to carry the charging current. The via size and number should be enough for a given current path. Decoupling capacitors should be placed next to the IC pins and make trace connection as short as possible.
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Page 83 of 210
MT6360 PMIC Datasheet Confidential A
5 5.1
Functional Descriptions General Descriptions CHG_VDDP
Charger / USB PD / FLED CHG_VMID
CHG_VIN VDDA PD_VDDA
PD_VBUS
PD_VCONN5V
CHG_BOOT
LDO UUG Controller
PD_VBUS
Programmable USB Type-C PD Controller
CHG Protection
Charger/OTG Controller
CHG_VLX
CHG H/L Driver
PD_CC1 PD_CC2 CHG_PGND
PD_IRQB DP BC 1.2
DN
FL_VMID
VBATS
FL_VINTORCH
VBATS_GND
CHG State Machine CHRDETB FLED Controller
FL_LEDCS1 CHG_ENB
FL_LEDCS2
CHG_ILIM CHG_QONB
FL_TORCH
CHG_VDDA
FL_STROBE VBAT
FL_TXMASK
CHG_VMID
VSYS VDDA ADC VDDM
VDDA Regulator
Power Path Controller
Silicon Temp Detection
VBAT BASE
AGND
TS Detector
VREF_TS TS
SCL
I2C
SDA
RGB Driver RGB Current Stage
TOP_CTRL
RGB_ISINK1 RGB_ISINK2 RGB_ISINK3 MT_ISINK
RGB Control EN FAULTB EN CTRL
RGB PWM RC
MRSTB
RGB_PGND
IRQB SDCARD_DET_N
LDO5
SRCLKEN_0 PREG HW_TRAPPING UVLO_SEL
USB_ID
RDET
LDOx (x=1~3)
LDO_VIN2
LDOx_VOUTS
LDO_VIN1 P-Type LDOx
VREF
USB_ID VREF
LDO5_VOUT
VFB
LDOx_VOUT BUCKx_VIN
BUCKx_LX
BUCKx LDO6 LDO7
H/L Driver
Buck Control
VREF
BUCKx_PGND
PWM Logic
N-Type LDO7 Core
LDO_VIN3
LDO6_VOUT LDO7_VOUT
BUCKx_VOUT
Figure 5-1. MT6360 functional block diagram
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Page 84 of 210
MT6360 PMIC Datasheet Confidential A Table 5-1. Control pin description
Part
Pin Name
Pin Description
Pin Type
MRSTB
Manual reset input for hardware reset.
Input/ActiveLow (Default: Disable)
Yes
Input/Output /Open-Drain
Yes
Input/Output /Open-Drain
Yes
Output/OpenDrain
No
Output/OpenDrain
No
Floating
Input/ActiveLow
Yes
Tie to ground to enable charger
No
Floating
No
Floating
SDA Top
Pin Connection Suggestion Controlled When Unused I2 C
SCL IRQB PD_IRQB CHG_ENB
I2C interface serial data input/output. Open-drain. An external pull-up resistor is required. I2C interface serial clock input. Opendrain. An external pull-up resistor is required. Interrupt output, active-low opendrain, to request the processor to read the registers. Interrupt output, active-low opendrain, to request the processor to read the registers. Charger enable input, active-low.
Battery over-voltage protection (BAT OVP) indication, open–drain and active-low output: Low if BAT OVP CHG_VBATO occurs, and High, otherwise. Output/OpenVPB Drain Battery over-voltage protection (BAT Charger OVP) indication. It is an open-drain and active-low output. It is low if BAT OVP occurs; otherwise, it is High. Internal BATFET enable control input. In shipping mode, CHG_QONB is Input/ActiveCHG_QONB pulled Low for the duration of Low tQONB_EXIT_SHIP_CHG (typical 0.9s) to exit shipping mode. Input/ActiveFL_TORCH Flash LED Torch mode enable Input. High Input/ActiveFL_STROBE Flash LED Strobe mode enable input. High Configurable power amplifier Flash synchronization input or configurable active-high torch mode enable. Input/ActiveFL_TXMASK Connect an internal pull-down resistor High (Default) of 400kΩ between FL_TXMASK and ground.
Yes Yes
No
Floating
Short to ground Short to ground Short to ground
Table 5-2. If a channel is unused, follow the setting instructions as below. Unused Part
Unused Function Input current limit setting
Charger PD
D+/D- Detection All functions
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Unused Pin Name CHG_ILIM D+ DCC1
Pin Connection (Short to ground/Floating/Others) Short to ground Floating Floating Floating
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Page 85 of 210
MT6360 PMIC Datasheet Confidential A Unused Part
Unused Function
CC2 PD_VCONN5V FL_VINTORCH FL_VMID FL_LEDCS1 FL_LEDCS2 FL_TORCH FL_STROBE FL_TXMASK FL_LEDCS1 FL_LEDCS2 LDO1_VOUT LDO2_VOUT LDO3_VOUT LDO5_VOUT RGB_ISINK1 RGB_ISINK2 RGB_ISINK3 ML_ISINK
All functions Flash
LDO
RGB
Unused Pin Name
Channel 1 only Channel 2 only LDO1 LDO2 LDO3 LDO5 Channel 1 only Channel 2 only Channel 3 only Moonlight
Pin Connection (Short to ground/Floating/Others) Floating Short to ground Short to VSYS Short to VMID Floating Floating Short to ground Short to ground Short to ground Floating Floating Floating Floating Floating Floating Floating Floating Floating Floating
Table 5-3. BOM list Reference Q'ty
Part Number ESD56241D12
D1
1
ESD5641D12 PTVSHC3N12VU
Package
Manufacturer
DFN 2x2
Willsemi
DFN 2x2
Willsemi
DFN 2x2
Prisemi
SOD962 DFN1006-2L DFN1006-2L SOD−323 SOD−323 DFN1006-2L
Nexperia Amazing Micro Willsemi Willsemi Willsemi Prisemi
Flash LED
2x1.6
Everlight
TVS Diode TVS Diode
DFN 1.6x1 DFN 1.6x1
Willsemi Amazing Micro MURATA MURATA MURATA MURATA
D3
1 1 1
D4
1
D5, D6
2
D7, D8
2
C1, C2 C3, C4 C5, C9, C12 C6 C7, C8, C19, C21, C22, C23 C10, C11, C13, C14,
2 2 2 1
GRM188R6YA225KA12 GRM0335C1E331GA01 GRM155R60J475ME47 GRM155R71H472KA01
2.2µF/0603/35V/X5R 330pF/0201/25V/C0G 4.7µF/0402/6.3V/X5R 4.7nF/0402/50V/X7R
0603 0201 0402 0402
1
GRM155R60J225ME15D
2.2µF/0402/6.3V/X5R
0402
MURATA
2
GRM188R60J226MEA0
22µF/0603/6.3V/X5R
0603
MURATA
D2
PESD4V0Z1BCSF AZ5315-02F ESD5681N15 ESD56151W04 ESD56201D04 PTVSHC3D4V5B ELCH08NB5565J6J8283910-F1S ESD56101D15 AZ4514-01F
Description TVS Diode (For surge 100V/200V/300V/450V) TVS Diode (For surge 100V/200V/300V/400V) TVS Diode (For surge 100V/200V/300V/350V) TVS Diode TVS Diode TVS Diode TVS Diode (For surge 250V) TVS Diode (For surge 200V) TVS Diode (For surge 200V)
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Page 86 of 210
MT6360 PMIC Datasheet Confidential A Reference Q'ty C17, C29, C30
Part Number
Description
Package
Manufacturer
MURATA MURATA Samsung
C15, C20 C16 C18, C28 C24, C25, C26, C27
2 1 1
GRM188R61E475KE11 GRM155R61C104KA88 CL10A106MQ8NNNC
4.7µF/0603/25V/X5R 47nF/0402/16V/JIS 10µF/0603/6.3V/X5R
0603 0402 0603
5
GRM033R60J105MEA2
1µF/0201/6.3V/X5R
0201
MURATA
L1, L2
1
TFM201610ALCR33MTAA HMMQ20161T-R33MDR
0.33µH/2016/DCR = 20mΩ
2016
TDK
L3
1
R R1 R2 R3
6 1 1 1
0.33µH/2016/DCR = 21mΩ
2016
CYNTEC
HTTK25201T-1R0MSR
1µH/2520/DCR = 25mΩ
2520
CYNTEC
CIGT252010EH1R0MNE RM02FTN2201 RM02FTN1004 RR0306S-6980-FNH RM02FTN3901
1µH/2520/DCR = 26mΩ 2.2k/0201/1% 1M/0201/1% 698/0201/1% 3.9k/0201/1%
2520 0201 0201 0201 0201
Samsung TA-I TA-I Cyntec TA-I
Table 5-4. Protection list Part
TOP
Protection Type
Threshold (Typical Value)
SYSUVLO
VSYS < VSYS_UVLO_FALL
VDDA OVP
VDDA > VVDDA_OVP
OTP
Sleep Mode
Temperature > 150°C VCHG_VIN falling, VCHG_VIN -VBAT < 40mV
Deglitch Time
Protection Method
VSYS > Setting by PMIC all BUCKs and 0x05,bit[7:6] LDOs UVLO shutdown VSYS_UVLO_RISE VDDA OVP shutdown VDDA < 5.3V selection by (0x0E, 32µs Latch-off bit[6]) OTP shutdown Temperature < 0 selection by (0x0E, 110°C bit[7]) VCHG_VIN rising , 0
Charger shutdown
Sink 50mA current per 2s and keep to check VCHG_VIN > whether the adapter is 3.95V good or not
32ms
CHG_VIN UVLO VCHG_VIN < 3.15V
5µs
Charger shutdown
0
Charger shutdown
CHG_VIN OVP
VBAT OVP EG_CHG
< 2%
Thermal Regulation Threshold
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VCHG_VIN > 5.5V,6.5V.11V.14.5V selection by (0x61, bit[6:5]) VBAT/VOREG_CHG> 108% Temperature > 100 to 120°C
VCHG_VIN - VBAT > 100mV
VIN Bad Adapter VCHG_VIN < 3.8V
Charger
Reset Method
VCHG_VIN > 3.3V VCHG_VIN < 5.25V,6.25V,10.7 5V,14.25V (VBAT -
0
Stop charging
VOREG_CHG)/VOR
0
Charging current is limited by thermal loop
N/A
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Page 87 of 210
MT6360 PMIC Datasheet Confidential A Part
Protection Type
Threshold (Typical Value) selection by (0x15, bit[1:0])
System OVP
VSYS > 5.25V
System UVP
OTG OLP OTG VMIDOVP
Protection Method
VSYS < 4.95V
2ms
Inductor peak current limit level of charger buck is half (option, 0x1D[3])
VSYS > 2.55V
0
Cycle by cycle current limit
ICHG_VLX < 6A ICHG_VLX < 8A
Start to hiccup
IOUT < 0.5 to 2.4A
Boost stop switching
VCHG_VMID < 5.8V
> 6A
ICHG_VLX > 8A selection by (0x1D, bit[2]) IOUT > 0.5 to 2.4A (selection by (0x1A, bit[2:0])) VCHG_VMID > 6V
4ms 0
VBAT < 2.3 to 3.8V OTG VBATUVP
OTG OCP
selection by (0x1A, bit[7:4]) ICHG_VLX > 3.5A, 4.5A, 5.5A or 6.5A selection by (0x1F, bit[2:1])
512µs
0
ICHG_VLX < 3.5A, 4.5A, 5.5A or 6.5A Clear INT (1.0x1F, bit[1] 2.0x11, bit[1]) Clear INT (1.0x1F, bit[7] 2.0x11, bit[1])
6µs
VCONN OCP shutdown selection by (0x8C, bit[7:5])
VCONN OVP
VCONN > 5.75V
6µs
VCONN shutdown
LEDCS Short
VFL_LEDCSx < 1V (typ.)
Strobe Mode FL-CHG_VIN OVP
VCHG_VIN ≥ 5.6V (typ.)
2.5ms
FLED shutdown
VFL_LEDCSx > 1V (typ.)
5µs
FLED shutdown
VCHG_VIN ≤ 5.3V (typ.)
RGB OpenCircuit Flag
RGB_ISINKx Voltage < 100mV
28µs
RGB ShortCircuit Flag
RGB_ISINKx voltage > VSYS - 0.5V
28µs
Current Limit
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Peak inductor current >5A
VBAT > 2.7V to 4.2V
Cycle by cycle current limit
VCONN > 300mA
RGB
Buck
Leave OTG mode
VCONN OCP PD
FL
Reset Method
Charger shutdown
0
VSYS < 2.4V
CHG_VLX
Charger-Buck OCP Current
Deglitch Time
0
Report only, Open_EN =1 ISINK Voltage< open LED protection threshold Report only, Short_EN =1 ISINK Voltage> short LED protection threshold Buck shutdown selection by (0x12, bit[1] and 0x22, bit[1])
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Open event Released Report flag RC Short event Released Report flag RC Re-start
Page 88 of 210
MT6360 PMIC Datasheet Confidential A Part
Protection Type
Threshold (Typical Value)
Deglitch Time
Protection Method PGB protect selection by (0x18, bit[1:0]) and (0x28, bit[1:0]), default hiccup
Vout PGB
Vout < 0.8 x Vtarget
400μs
Vout UVP
Vout < 0.6 x Vtarget
0
Report only
Vin UVP
BUCKx_PVIN < 2.4V
0
Buck stop switching
OTP
Temperature > 150°C
0
LDO1
Over-Current
1.5 x Imax to 2.8 x Imax
60μs
LDO2
Over-Current
1.5 x Imax to 2.8 x Imax
60μs
LDO3
Over-Current
1.5 x Imax to 2.5 x Imax
60μs
LDO5
Over-Current
1.5 x Imax to 2.5 x Imax
60μs
LDO6
Over-Current
1.5 x Imax to 2.8 x Imax
60μs
LDO7
Over-Current
1.5 x Imax to 2.8 x Imax
60μs
LDO5
OTP
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Temperature > 150°C
0
OTP shutdown selection by (0x0E, bit[7]) Latch-off protection. Automatically disable LDO1 Latch-off protection. Automatically disable LDO2 Latch-off protection. Automatically disable LDO3 Latch-off protection. Automatically disable LDO5 Hiccup protection. Only interrupt, and won't disable LDO6 Hiccup protection. Only interrupt, and won't disable LDO7 OTP shutdown selection by (0x0E, bit[7])
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Reset Method
PG, Latch-off Vout > 0.6 x Vtarget BUCKx_PVIN > 2.4 Temperature < 110°C Re-start Re-start Re-start Re-start Hiccup Hiccup Temperature 2.5V, power path is turned on with deglitch time select 00: 32msec 01: 64msec 10: 128msec
Page 102 of 210
MT6360 PMIC Datasheet Confidential A Address
0x1F
0x20
0x21
0x22
Reg Name
CHG CTRL 15
Bit
Bit Name
Default
Type
7:6
VDDP_VOSEL
11
RW
5:3
Reserved
000
R
2:1
Higher_OCP_BST
11
RW
0
Reserved
0
R
7:1
AICC_VTH
0000111
RW
0
CHG_VBATOVPB_INDI CATOR
0
RW
7:2
RG_AICC_RESULT
111111
RW
1:0
Reserved
00
R
7
USBCHGEN
0
RW
CHG CTRL 16
CHG_AICC_ RESULT
Device Type
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Description 11: 256msec VDDP Output Voltage Setting: 11: 4.9V 10: 4.65V 01: 4.41V 00: 4.165V Reserved Inductor peak current limit level of Boost Mode 00: OCP_BST = 3.5A 01: OCP_BST = 4.5A 10: OCP_BST = 5.5A 11: OCP_BST = 6.5A Reserved Input AICC_VTH threshold setting 0000000 : 3.9V 0000001 : 4V 0000010 : 4.1V 0000011 : 4.2V 0000100 : 4.3V 0000101 : 4.4V 0000110 : 4.5V 0000111 : 4.6V … 0011110 : 6.9V 0011111: 7V … 0110010 : 8.9V 0110011 : 9V … 1010000 : 11.9V 1010001 : 12V … 1011111 : 13.4V 1100000 to 1111111: 13.4V CHG_VBATOVPB pin control select. When VBAT OVP happens, CHG_VBATOVPB pulls low (open drain) 0: Control by 0x45[6:5] HW BAT OVP 1: Control by 0xD5[1], ADC BAT OVP If RG_EN_AICC (0x1E[7]) = 0, RG_AICC_RESULT[5:0] = IAICR[5:0]( 0x13[7:0]) If RG_EN_AICC (0x1E[7]) = 1, the value will be controlled by AICC function. Reserved USB charger detection flow enable/disable 0: Disable USB charger detection flow
Page 103 of 210
MT6360 PMIC Datasheet Confidential A Address
0x24
0x27
0x28
Reg Name
DCP Control
Bit
Bit Name
Default
Type
6
DCD Timeout EN
1
RW
5:4
DCD_TIMEOUT
01
RW
3:0 7:2
Reserved Reserved
0000 000000
R R
1
EN_DCP
0
RW
0 7
Reserved Reserved
0 0
R R
6:4
USB Status
000
R
3
CHGDET
0
R
2
DCDT
0
R
1:0 7:5
Reserved Reserved
00 000
R R
4
DPDM_CTRL_EN
0
RW
3:0
DPDM_CTRL
0000
RW
USB Status 1
DPDM_CTRL
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© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description 1: Enable USB charger detection flow 0: Disable DCD Timeout 1: Enable DCD Timeout Data contact detection timeout 00: 300ms 01: 600ms 10: 900ms 11: 1200ms Reserved Reserved Enable dedicate charging port 0: Disable 1: Enable Reserved Reserved 000: No VBUS 001: VBUS flow is going 010: SDP 011: Unknown adapter 100: DCP 101: CDP 110: VBUS IN but BC12 flow is disable 111: Reserved 0: Charger port is not detected 1: Charger port is detected 0: DCD Timeout event of BC detection not occurs 1: DCD Timeout event of BC detection occurs Reserved Reserved DPDM register ctrl enable 0: Disable 1: Enable RW DPDM control selection 0000: DP / DM = HZ / HZ 0001: DP / DM = Hz / 0V 0010: DP / DM = 0V / Hz 0011: DP / DM = 0V / 0V 0100: DP / DM = 0V / 0.6V 0101: DP / DM = 0.6V / 0V 0110: DP / DM = 0.6V / 0.6V 0111: DP / DM = 0.6V / 3.3V 1000: DP / DM = 3.3V / 0.6V 1001: DP / DM = 3.3V / 3.3V 1010: DP / DM = Hz / Hz 1011: DP / DM = Hz / Hz
Page 104 of 210
MT6360 PMIC Datasheet Confidential A Address
0x2A
0x2B
Reg Name
CHG_PUMP
CHG CTRL 17
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Bit
Bit Name
Default
Type
7
PP_OFF_rst dis
0
RW
6
sBCK_SWITCHING_EN
1
RW
5:3
Reversed
000
RW
2
WD_PMU_EN
0
RW
1
WD_HW_EN
0
RW
0
WD_SW_EN
0
RW
7
EN_PUMPX
0
RW
6
PUMPX_2.0_1.0
0
RW
5
PUMPX_UP_DN
0
RW
4:0
PUMPX_DEC
00000
RW
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description 1100: DP / DM = Hz / Hz 1101: DP / DM = Hz / Hz 1110: DP / DM = Hz / Hz 1111: DP / DM = Hz / Hz Disable/enable QON = 0 for 15s to sys reset 0: Don’ t disable reset function (QON = 0 for 15s will reset system) 1: Disable reset function (QON = 0 will not reset system) Only charger_buck enable/disable (allowing Boost operation) 0: Disable 1: Enable Reversed Water detection function enable 0: Disable 1: Enable (support WD_HW_EN and WD_SW_EN) Trigger DPDM water detection while PD_VBUS plug-in 0: Disable 1: Enable SW trigger DPDM water detection (start water detection while 0->1, should disable WD_HW_EN first) 0: Disable 1: Enable Enable MTK pump express pulse 0: Disable 1: Allow MTK pump express pulse MTK pump express 2.0/1.0 enable 0: PE1.0 Enable 1: PE2.0 Enable MTK pump express 1.0 voltage up/down enable 0: PE1.0 voltage down enable 1: PE1.0 voltage up enable MTK pump express 2.0 voltage request setting 00000: 5.5V 00001: 6V 00010: 6.5V … 00111: 9V … 01101: 12V … 11101: 20V
Page 105 of 210
MT6360 PMIC Datasheet Confidential A Address
0x2C
0x2D
0x2E
Reg Name
Bit
Bit Name
Default
Type
7
Reserved
0
R
6
EN_IRCOMP
1
RW
5:3
BAT_COMP
000
RW
2:0
VCLAMP
000
RW
7:4
CHRDETB_VBUS_UVL O
1011
RW
3:0
CHRDETB_VBUS_OVP
0110
RW
7
CHRDETB_EN
1
RW
6:0
Reserved
0000000
R
CHG CTRL 18
CHRDETB_C TRL1
CHRDETB_C TRL2
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Description 11110: Adapter healthy self-testing 11111: Disable cable drop compensation Reserved Battery IR compensation enable 0: Disable 1: Enable Battery IR compensation resistor setting 000: 0mΩ 001: 25mΩ 010: 50mΩ 011: 75mΩ 100: 100mΩ 101: 125mΩ 110: 150mΩ 111: 175mΩ Battery IR compensation maximum voltage clamp 000: 0mV 001: 32mV 010: 64mV 011: 96mV 100: 128mV 101: 160mV 110: 192mV 111: 224mV CHRDETB Block, PD_VBUS UVLO (Rising) 0000: 2.6V 0001: 2.7V 0010: 2.8V 0011: 2.9V 0100: 3.0V 0101: 3.1V 0110: 3.2V 0111: 3.3V 1000: 3.4V 1001: 3.5V 1010: 3.6V 1011: 3.7V 1100 to 1111: 3.7V CHRDETB Block, PD_VBUS OVP (Rising) 0000: 6V 0001: 6.5V 0010: 7V 0011: 7.5V 0100: 8.5V 0101: 9.5V 0110: 10.5V 0111: 11.5V 1000: 12.5V 1001 to 1111: 14.5V 0: Disable 1: Enable Reserved
Page 106 of 210
MT6360 PMIC Datasheet Confidential A Address
0x4A
0x51
0x52 0x53
0x56
Reg Name
CHG STAT
OTHERS_CT RL
ADC_DATA_ H ADC_DATA_ L
Bit
Bit Name
Default
Type
7:6
CHG_STAT
00
RO
5
VBAT_LVL
0
RO
4
VBAT_TRICKLE
0
RO
3
BOOST_STAT
0
RO
2
BST_VBUSOVP_STAT
0
RO
1:0 7:2
Reserved Reserved
00 000000
R R
1
BAT_OVP_ADC_EN
1
RW
0
Reserved
0
R
Description Charger status 00: Ready 01: Charge is in progress 10: Charge is done 11: Fault Battery voltage level selection for 2 operation modes 0: In pre-charge mode 1: In fast-charge mode Battery voltage level for operation mode 0: Charger does not operate in trickle level 1: Charger operates in trickle level Boost mode status 0: Not in boost mode 1: Boost mode Boost mode VBUS OVP status 0: Boost-mode VBUS OVP does not occur 1: Boost-mode VBUS OVP occurs Reserved Reserved When ZCV is active or SW write ADC_CH4_EN = 1'b1, enable BAT_OVP_ADC detection 0: Disable BAT_OVP_ADC function 1: Enable BAT_OVP_ADC function, when ZCV is active or SW write ADC_CH4_EN = 1'b1 Reserved
7:0
ADC_BAT_CODEH
00000000
R
ADC code high byte
7:0
ADC_BAT_CODEL
00000000
R
ADC code low byte
7
ADC_EN
1
RW
6
ZCV_EN
1
RW
5:3
ADC_WAIT_T
001
RW
ADC_CONFI G
MediaTek Confidential
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
0: Disable ADC 1: Enable ADC When TA plug-in, ADC automatically detect VBAT at background 0: Disable Zero Current Voltage function 1: Enable Zero Current Voltage function ADC wait time after every channel 000: 0ms 001:25ms 010:50ms 011:100ms 100:150ms 101:200ms 110:250ms
Page 107 of 210
MT6360 PMIC Datasheet Confidential A Address
0x57
0x58
0x5A
0x5B 0x5C
Reg Name
Bit
Bit Name
Default
Type
2
ADC_CH10_EN
0
RW
1
ADC_CH9_EN
0
RW
0
ADC_CH8_EN
0
RW
7
ADC_CH7_EN
0
RW
6
ADC_CH6_EN
0
RW
5
ADC_CH5_EN
0
RW
4
ADC_CH4_EN
0
RW
3
ADC_CH3_EN
0
RW
2
ADC_CH2_EN
0
RW
1
ADC_CH1_EN
0
RW
0
ADC_CH0_EN
0
RW
7:0
ADC_IDLE_T
00001010
RW
7:4
ADC_RPT_SEL
1111
RW
3:0
ADC_RPT_CH
0000
RO
7:0 7:0
ADC_RPT_H ADC_RPT_L
00000000 00000000
RO RO
ADC_EN2
ADC_IDLE_T
ADC_RPT_1
ADC_RPT_2 ADC_RPT_3
MediaTek Confidential
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description 111: 300ms ADC CH10: TS 0: Disable ADC channel 10 1: Enable ADC channel 10 ADC CH9: VREF_TS 0: Disable ADC channel 9 1: Enable ADC channel 9 ADC CH8: TEMP_JC 0: Disable ADC channel 8 1: Enable ADC channel 8 ADC CH7: CHG_VDDP 0: Disable ADC channel 7 1: Enable ADC channel 7 ADC CH6: IBAT 0: Disable ADC channel 6 1: Enable ADC channel 6 ADC CH5: IBUS 0: Disable ADC channel 5 1: Enable ADC channel 5 ADC CH4: VBAT 0: Disable ADC channel 4 1: Enable ADC channel 4 ADC CH3: VSYS 0: Disable ADC channel 3 1: Enable ADC channel 3 ADC CH2: CHG_VIN /2 0: Disable ADC channel 2 1: Enable ADC channel 2 ADC CH1 : CHG_VIN /5 0: Disable ADC channel 1 1: Enable ADC channel 1 ADC CH0: USB_ID 0: Disable ADC channel 0 1: Enable ADC channel 0 ADC idle time after every turn 00000000: 0ms 00000001: 200ms 00000010: 400ms … 00001010: 2000ms … 11111111: 51000ms 0000: Prefer report channel 0 0001: Prefer report channel 1 ... 1010: Prefer report channel 10 1011 to 1111: Report current channel ADC report channel I2C read this address will latch ADC data for ADC_RPT2 and ADC_RPT3 ADC report High byte ADC report Low byte
Page 108 of 210
MT6360 PMIC Datasheet Confidential A Address
Reg Name
Bit
Bit Name
Default
Type
0x5F
BAT_OVP_T H_SEL_COD EH
7:0
BAT_OVP_TH_SEL_C ODEH
00001101
RW
0x60
BAT_OVP_T H_SEL_COD EL
7:0
BAT_OVP_TH_SEL_C ODEL
11000000
RW
7
Reserved
0
R
6:5
CHG_VIN_OVP_VTHS EL
01
RW
4:0 7:2
Reserved Reserved
00000 000000
R R
1:0
VOVDDM_SEL
11
RW
7
USBID_EN
0
RW
6:5
ID_RUPSEL
00
RW
4:2
IS_TDET
011
RWSC
1:0
IS_PERIOD
01
RW
0x61
0x62
0x6D
CHG_CTRL 19
VDDA Supply
USBID_CTRL 1
MediaTek Confidential
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description BAT_OVP_TH_SEL_CO DEH Note: This byte is combinatorial with REG_PMU0x60, so must write two bytes (REG_PMU0x5F and REG_PMU0x60) in one sequence BAT_OVP_TH_SEL_CO DEL, 1LSB = 250µV, default = 4.4V BAT_OVP_TH = [(CODEH * 256) + CODEL] * 250µV Reserved CHGVIN_OVP threshold voltage selection 00: 5.5V 01: 6.5V 10: 11V 11: 14.5V Reserved Reserved VDDM output voltage setting : 11: 4.88V 10: 4.8V 01: 4.7V 00: 4.6V USB_ID function enable control 0: Disable 1: Enable USB_ID pull up resistance selection 00: 500k 01: 75k 10: 5k 11: 1k USB_ID current source on time for detection 000: 400µs 001: 1ms 010: 4ms 011: 10ms 100: 40ms 101: 100ms 110: 400ms 111: Always ON (manual mode) Note: When USBID_FON_EN = 1'b1, then USBID_EVT = 0->1, next automatically set IS_TDET = 3'b111 Repeat period 00 = 4x (4 times of IS_TDET) 01 = 100x
Page 109 of 210
MT6360 PMIC Datasheet Confidential A Address
0x6E
0x6F
Reg Name
Bit
Bit Name
Default
Type
7:5
ID_TD
001
RW
4:2
Reserved
000
R
1
USBID_FLOATING
0
RW
0
USBID_FON_EN
0
RW
7
ID_PREG_VOSEL
0
RW
6
ID_VTHSEL
0
RW
5:4
Reserved
00
R
3:1
ID_TDIS
000
RWSC
USBID_CTRL 2
USBID_CTRL 3
MediaTek Confidential
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description 10 = 200x 11 = 1600x USB_ID de-bounce time selection (fSW = 65kHz ) 000: 1T 001: 3T 010: 16T 011: 32T 100: 130T 101: 520T 110: 2078T 111: 4156T Reserved 0: Discharge when USB_ID is OFF 1: Floating when USB_ID is OFF Note: When USB_ID pin is floating, user can detect the voltage value on USB_ID pin by ADC. USBID_FON function: When USBID_EVT = 0 1, automatically set IS_TDET = 3'b111 or not 0: Disable USBID_FON function 1: Enable USBID_FON function. USB_ID pre-regulator output voltage selection 0: 1.8V 1: 0.6V USB_ID interrupt threshold voltage / hysteresis voltage When ID_PREG_VOSEL = 1'b0 0: 1.45V/100mV 1: 0.4V/100mV When ID_PREG_VOSEL = 1'b1 0: 0.6V/50mV 1: 0.2V/50mV Reserved USB_ID discharge time selection: (4T = 4RC for 98.2% discharging, fSW = 65kHz) 000: 0µs 001: 3T 010: 9T 011: 16T 100: 32T (20nF, 5kΩ + 25%) 101: 64T 110: 128T 111: 160T Note: While ID_FLOATING_EN =
Page 110 of 210
MT6360 PMIC Datasheet Confidential A Address
0x70
0x72
Reg Name
Bit
Bit Name
Default
Type
0
Reserved
0
R
7
TX Active Level
1
RW
6:5
TXSEL
00
RW
4:2
Reserved
000
R
1
FLED_STRB_LES
0
RW
0
PULLED_LOW_R
1
RW
7
Reserved
0
R
6:4
FLED1_TCL
000
RW
3:0 7
Reserved Reserved
0000 0
R R
6:0
FLED_STRB_TO
0100101
RW
7
FLED1 ULTRA LOW ISTRB\ (utral_istrb1)
0
RW
FLED_CFG
FLED1_CTRL
0x73
FLED_STRB_ CTRL (FLED Strobe Control)
0x74
FLED1_STRB_ CTRL (FLED1 Strobe Control)
MediaTek Confidential
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description 1'b1->0, the default value is 3'b000 While ID_FLOATING_EN = 1'b0->1, the default value is 3'b100 Reserved TX active level selection: 0: Low level 1: High level FLED TX function enable control bits 00: ALL FLEDs' TX function disable 01: FLED1's TX function enable and FLED2's disable 10: FLED1's TX function disable and FLED2's enable 11: ALL FLEDs' TX function enable Reserved FLED strobe mode: level sensitive enable or rising edge trigger one-shot operation. 0: Level sensitive 1: Rising edge trigger FL_LEDCS1/2 pulled low res setting 0: 2.5kΩ 1: 20kΩ Reserved FLED1 timeout current level. 000: 25mA 001: 50mA ... 110: 175mA 111: 200mA If utra_istrb1 = 1 000 = 12.5mA 111 = 100mA Reserved Reserved FLED1 strobe timeout 0000000: 64ms 0000001: 96ms … 0100101: 1248ms ... 1001001: 2400ms 1001010 to 1111111: 2432ms 0: Normal, 1: I(FLED1_ISTRB[6:0])/2 FLED1 strobe current 0x74[6:0] 000,0000: 25mA
Page 111 of 210
MT6360 PMIC Datasheet Confidential A Address
0x75
0x76
0x78
0x79
Reg Name
FLED1_TOR_ CTRL (FLED1 Torch Control)
FLED2_CTRL
Bit
Bit Name
Default
Type
6:0
FLED1_ISTRB
0111100
RW
7:5
Reserved
000
R
4:0
FLED1_ITOR
00001
RW
7
Reserved
0
R
6:4
FLED2_TCL
000
RW
3:0
Reserved
0000
R
7
FLED2 ULTRA LOW ISTRB\ (utral_istrb2)
0
RW
6:0
FLED2_ISTRB
0111100
RW
7:5
Reserved
000
R
4:0
FLED2_ITOR
00001
RW
FLED2_STRB _CTRL (FLED2 Strobe Control)
FLED2_TOR _CTRL (FLED2 Torch Control)
MediaTek Confidential
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description 000,0001: 31.25mA … 0111100: 400mA … 1110100 to 1111111: 750mA FLED1 strobe current 0000000: 50mA 0000001: 62.5mA … 0111100: 800mA ... 1110100 to 1111111: 1500mA Reserved FLED1 torch current 00000: 25mA 00001: 37.5mA … 01111: 212.5mA ... 11110 to 11111: 400mA Reserved FLED2 timeout current level. 000: 25mA 001: 50mA ... 110: 175mA 111: 200mA If utra_istrb2 = 1 000 = 12.5mA 111 = 100mA Reserved 0: Normal, 1: I(FLED2_ISTRB[6:0])/2 FLED2 Strobe current 0x74[6:0] 000,0000: 25mA 000,0001: 31.25mA ... 0111100: 400mA ... 1110100: 750mA ... 1111111: 750mA FLED2 strobe current 0000000: 50mA 0000001: 62.5mA ... 0111100: 800mA ... 1110100: 1500mA ... 1111111: 1500mA Reserved FLED2 torch current 00000: 25mA 00001: 37.5mA … 01111 : 212.5mA
Page 112 of 210
MT6360 PMIC Datasheet Confidential A Address
0x7A
0x7E
0x80
0x81
Reg Name
FLED_VMID TRK_CTRL1 (VMID Fix Mode Control)
FLED_EN (TORCH / STROBE)
RGB_EN
RGB1_ISINK
MediaTek Confidential
Bit
Bit Name
Default
Type
7:6
Reserved
00
R
5:0
FLED_VMID
110111
RW
7:4 3:2
Reserved Reserved
0000 00
R R
1
FLCS1_EN
0
RW
0
FLCS2_EN
0
RW
7
ISINK1_CHRIND_EN
0
RW
6
ISINK2_EN
0
RW
5
ISINK3_EN
0
RW
4
ISINK4_ML_EN
0
RW
3
ISINK1_CHRIND_EN_ SEL
0
RW
2
ISINK_Breath Mode_Freq
0
RW
1:0
Reserved
00
R
7:6
ISINK1_CHRIND_DIM _MODE
11
RW
5:4
Reserved
00
R
3:0
ISINK1_CHRIND_CUR _SEL
1010
RW
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description ... 11110 : 400mA Reserved MID Regulation Level (priority is higher than charger setting when EN_FLED = 1) 000000: 3.625V 000001: 3.65V 000010: 3.675V … 110111: 5V … 111110: 5.175V 111111: 5.2V Reserved Reserved FL_LEDCS1 enable control 0: Disable FL_LEDCS1 1: Enable FL_LEDCS1 FL_LEDCS2 enable control 0: Disable FL_LEDCS2 1: Enable FL_LEDCS2 ISINK1 charge indicator current sink enable 0: Disable 1: Enable ISINK2 current sink enable 0: Disable 1: Enable ISINK3 current sink enable 0: Disable 1: Enable ISINK4 Moon-light Current Sink Enable 0: Disable 1: Enable ISINK1 charge indicator control mode select 0= Auto mode (charger indicator) 1= Software mode All ISINK breath mode switching frequency select 0 = 256Hz 1 = 128Hz Reserved ISINK1 mode select 00 = Flash mode 01 = Breath mode 1X = Register mode Reserved ISINK1 maximum LED current level 0000 = 1mA 0001 = 2mA
Page 113 of 210
MT6360 PMIC Datasheet Confidential A Address
0x82
0x83
0x84
Reg Name
Bit
Bit Name
Default
Type
7:6
ISINK2_DIM_MODE
11
RW
5:4
Reserved
00
R
3:0
ISINK2_CUR_SEL
1010
RW
7:6
ISINK3_DIM_MODE
11
RW
5:4
Reserved
00
R
3:0
ISINK3_CUR_SEL
1010
RW
7
ISINK4_ML_RAMP_UP
1
RW
RGB2_ISINK
RGB3_ISINK
RGB_ML_ISI NK
MediaTek Confidential
6:5
Reserved
00
R
4:0
ISINK4_ML_CUR_SEL
01100
RW
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description 0010 = 4mA 0011 = 6mA … 1010 = 20mA ... 1100 = 24mA … 1111 = 24mA ISINK2 mode select 00 = Flash mode 01 = Breath mode 1X = Register mode Reserved ISINK2 maximum LED current level 0000 = 1mA 0001 = 2mA 0010 = 4mA 0011 = 6mA … 1010 = 20mA ... 1100 = 24mA … 1111 = 24mA ISINK3 mode select 00 = Flash mode 01 = Breath mode 1X = Register mode Reserved ISINK3 maximum LED current level 0000 = 1mA 0001 = 2mA 0010 = 4mA 0011 = 6mA … 1010 = 20mA ... 1100 = 24mA … 1111 = 24mA ISINK4 moon-light register mode ramp up function enable control 0: Disable ISINK4 register mode ramp up function 1: Enable ISINK4 register mode ramp up function Note: 16 Steps for Total Ramp Up Time is 230µs ±5% Reserved ISINK4 moon-light maximum LED current level 00000 = 5mA 00001 = 5mA 00010 = 10mA
Page 114 of 210
MT6360 PMIC Datasheet Confidential A Address
Reg Name
Bit
Bit Name
Default
Type
0x85
RGB1_DIM
7:0
ISINK1_CHRIND_DIM _DUTY
00011111
RW
0x86
RGB2_DIM
7:0
ISINK2_DIM_DUTY
00011111
RW
0x87
RGB3_ISINK
7:0
ISINK3_DIM_DUTY
00011111
RW
7:5
ISINK1_CHRIND_DIM _FSEL
010
RW
4:2
ISINK2_DIM_FSEL
010
RW
1:0
Reserved
00
R
7:5
ISINK3_DIM_FSEL
010
RW
4:0
Reserved
00000
R
0x89
0x8A
RGB1/2_Freq
RGB3/4_Freq
MediaTek Confidential
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description 00011 = 15mA 00100 = 20mA … 01100 = 60mA 01101 = 65mA ... 10100 = 100mA … 11110 = 150mA 11111 = 150mA ISINK1 charge indicator flash mode dimming duty = (N+1)/256 N = 0 to 255 Default = 32/256 ISINK1 charge indicator flash mode dimming duty = (N+1)/256 N = 0 to 255 Default = 32/256 ISINK1 charge indicator flash mode dimming duty = (N+1)/256 N = 0 to 255 Default = 32/256 ISINK1 charge indicator flash mode dimming frequency select 000 = 0.125Hz 001 = 0.25Hz 010 = 0.5Hz 011 = 1Hz 100 = 2Hz 101 = 4Hz 110 = 128Hz 111 = 256Hz ISINK2 flash mode dimming frequency select 000 = 0.125Hz 001 = 0.25Hz 010 = 0.5Hz 011 = 1Hz 100 = 2Hz 101 = 4Hz 110 = 128Hz 111 = 256Hz Reserved ISINK3 flash mode dimming frequency select 000 = 0.125Hz 001 = 0.25Hz 010 = 0.5Hz 011 = 1Hz 100 = 2Hz 101 = 4Hz 110 = 128Hz 111 = 256Hz Reserved
Page 115 of 210
MT6360 PMIC Datasheet Confidential A Address
0x8B
0x8C
0x8D
Reg Name
Bit
Bit Name
Default
Type
7:4
ISINK1_CHRIND_BRE ATH_Tr1_SEL
0001
RW
3:0
ISINK1_CHRIND_BRE ATH_Tr2_SEL
0001
RW
7:4
ISINK1_CHRIND_BRE ATH_Tf1_SEL
0001
RW
3:0
ISINK1_CHRIND_BRE ATH_Tf2_SEL
0001
RW
7:4
ISINK1_BREATH_TON _SEL
0001
RW
RGB1_Tr
RGB1_Tf
RGB1_TON_ TOFF
MediaTek Confidential
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description ISINK1 charge indicator breath mode first rising time select Duty : 0% to 25% 0000 = 0.125s 0001 = 0.375s 0010 = 0.625s ‧‧‧ 1000 = 2.125s ‧‧‧ 1111 = 3.875s 16 Steps, 0.25s/step ISINK1 charge indicator breath mode second rising time select Duty : 25% to 100% 0000 = 0.125s 0001 = 0.375s 0010 = 0.625s ‧‧‧ 1000 = 2.125s ‧‧‧ 1111 = 3.875s 16 steps, 0.25s/step ISINK1 charge indicator breath mode first falling time select Duty : 100% to 25% 0000 = 0.125s 0001 = 0.375s 0010 = 0.625s ‧‧‧ 1000 = 2.125s ‧‧‧ 1111 = 3.875s 16 steps, 0.25s/step ISINK1 charge indicator breath mode second falling time select Duty : 25% to 0% 0000 = 0.125s 0001 = 0.375s 0010 = 0.625s ‧‧‧ 1000 = 2.125s ‧‧‧ 1111 = 3.875s 16 steps, 0.25s/step ISINK1 breath mode on time select 0000 = 0.125s 0001 = 0.375s 0010 = 0.625s ‧‧‧ 1000 = 2.125s ‧‧‧
Page 116 of 210
MT6360 PMIC Datasheet Confidential A Address
0x8E
0x8F
Reg Name
Bit
Bit Name
Default
Type
3:0
ISINK1_BREATH_TOF F_SEL
0001
RW
7:4
ISINK2_BREATH_Tr1_ SEL
0001
RW
3:0
ISINK2_BREATH_Tr2_ SEL
0001
RW
7:4
ISINK2_BREATH_Tf1_ SEL
0001
RW
3:0
ISINK2_BREATH_Tf2_ SEL
0001
RW
RGB2_Tr
RGB2_Tf
MediaTek Confidential
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description 1111 = 3.875s 16 Steps, 0.25s/step ISINK1 Breath mode off time select 0000 = 0.25s 0001 = 0.75s 0010 = 1.25s ‧‧‧ 1000 = 4.25s ‧‧‧ 1111 = 7.75s 16 Steps, 0.5s/step ISINK2 Breath mode first rising time select Duty: 0% to 25% 0000 = 0.125s 0001 = 0.375s 0010 = 0.625s ‧‧‧ 1000 = 2.125s ‧‧‧ 1111 = 3.875s 16 Steps, 0.25s/step ISINK2 Breath mode second rising time select 0000 = 0.125s 0001 = 0.375s 0010 = 0.625s ‧‧‧ 1000 = 2.125s ‧‧‧ 1111 = 3.875s 16 Steps, 0.25s/step ISINK2 breath mode first falling time select Duty : 100% to 25% 0000 = 0.125s 0001 = 0.375s 0010 = 0.625s ‧‧‧ 1000 = 2.125s ‧‧‧ 1111 = 3.875s 16 steps, 0.25s/step ISINK2 breath mode second falling time select Duty : 25% to 0% 0000 = 0.125s 0001 = 0.375s 0010 = 0.625s ‧‧‧ 1000 = 2.125s ‧‧‧ 1111 = 3.875s 16 steps, 0.25s/step
Page 117 of 210
MT6360 PMIC Datasheet Confidential A Address
0x90
0x91
0x92
Reg Name
Bit
Bit Name
Default
Type
7:4
ISINK2_BREATH2_TO N_SEL
0001
RW
3:0
ISINK2_BREATH_TOF F_SEL
0101
RW
7:4
ISINK3_BREATH_Tr1_ SEL
0001
RW
3:0
ISINK3_BREATH_Tr2_ SEL
0001
RW
7:4
ISINK3_BREATH_Tf1_ SEL
0001
RW
3:0
ISINK3_BREATH_Tf2_ SEL
0001
RW
RGB2_TON_ TOFF
RGB3_Tr
RGB3_Tf
MediaTek Confidential
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description ISINK2 breath mode on time select 0000 = 0.125s 0001 = 0.375s 0010 = 0.625s ‧‧‧ 1000 = 2.125s ‧‧‧ 1111 = 3.875s 16 steps, 0.25s/step ISINK2 breath mode off time select 0000 = 0.25s 0001 = 0.75s 0010 = 1.25s ‧‧‧ 1000 = 4.25s ‧‧‧ 1111 = 7.75s 16 steps, 0.5s/step ISINK3 breath mode first rising time select Duty : 0% to 25% 0000 = 0.125s 0001 = 0.375s 0010 = 0.625s ‧‧‧ 1000 = 2.125s ‧‧‧ 1111 = 3.875s 16 Steps, 0.25s/step ISINK3 breath mode second rising time select Duty : 25% to 100% 0000 = 0.125s 0001 = 0.375s 0010 = 0.625s ‧‧‧ 1000 = 2.125s ‧‧‧ 1111 = 3.875s 16 steps, 0.25s/step ISINK3 breath mode first falling time select Duty : 100% to 25% 0000 = 0.125s 0001 = 0.375s 0010 = 0.625s ‧‧‧ 1000 = 2.125s ‧‧‧ 1111 = 3.875s 16 steps, 0.25s/step ISINK3 breath mode second falling time select
Page 118 of 210
MT6360 PMIC Datasheet Confidential A Address
0x93
0xD0
0xD1
Reg Name
Bit
Bit Name
Default
Type
7:4
ISINK3_BREATH_TON _SEL
0001
RW
3:0
ISINK3_BREATH_TOF F_SEL
0001
RW
7
PWR_RDY_EVT
0
WC
6
CHG_MIVR_EVT
0
WC
5
CHG_AICR_EVT
0
WC
4
CHG_TREG_EVT
0
WC
3:0
Reserved
0000
R
7
CHG_VINOVPCHG_EV T
0
WC
6
CHG_VBATOV_EVT
0
WC
RGB3_TON_ TOFF
CHG_IRQ1
CHG_IRQ2
MediaTek Confidential
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description Duty : 25% to 0% 0000 = 0.125s 0001 = 0.375s 0010 = 0.625s ‧‧‧ 1000 = 2.125s ‧‧‧ 1111 = 3.875s 16 steps, 0.25s/step ISINK3 breath mode on time select 0000 = 0.125s 0001 = 0.375s 0010 = 0.625s ‧‧‧ 1000 = 2.125s ‧‧‧ 1111 = 3.875s 16 steps, 0.25s/step ISINK3 breath mode off time select 0000 = 0.25s 0001 = 0.75s 0010 = 1.25s ‧‧‧ 1000 = 4.25s ‧‧‧ 1111 = 7.75s 16 steps, 0.5s/step Power ready detection result: Input power is good, UVLO < VIN < VOVP and VIN > BATS + VSLP 0: No operation 1: Event occurs Charger warning. Input voltage MIVR loop active. 0: No operation 1: Event occurs Charger warning. Input current AICR loop active. 0: No operation 1: Event occurs Charger warning. Thermal regulation loop active. 0: No operation 1: Event occurs Reserved CHG_VIN over-voltage protection fault. It will forbid charger operation. 0: No operation 1: Event occurs Charger fault. Battery OVP fault 0: No operation 1: Event occurs
Page 119 of 210
MT6360 PMIC Datasheet Confidential A Address
0xD3
0xD4
Reg Name
CHG_IRQ4
CHG_IRQ5
MediaTek Confidential
Bit
Bit Name
Default
Type
5
CHG_VSYSOV_EVT
0
WC
4
CHG_VSYSUV_EVT
0
WC
3
FLED_CHG_VINOVP_ EVT
0
WC
2
Reserved
0
R
1
CHG_BATSYSUV_EVT
0
WC
0
Reserved
0
R
7
OTPI_EVT
0
WC
6
CHG_RVPI_EVT
0
WC
5
CHG_ADPBADI_EVT
0
WC
4
Reserved
0
R
3
CHG_TMRI_EVT
0
WC
2
WD_PMU_DONE
0
WC
1
WD_PMU_DET
0
WC
0
Reserved
0
R
7
CHG_IEOCI_EVT
0
WC
6
CHG_TERMI_EVT
0
WC
5
Reserved
0
WC
4
SSFINISHI_EVT
0
WC
3
WDTMRI_EVT
0
WC
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description Charger fault. System OVP fault 0: No operation 1: Event occurs Charger fault. System UVP fault 0: No operation 1: Event occurs CHG_VIN over 5.6V voltage protection fault which only works when FLED is ON and will forbid strobe operation. 0: No operation 1: Event occurs Reserved The voltage: MAX (VBAT,VSYS) UVLO's event 0: No fault occurs 1: Fault ever occurred Reserved Thermal shutdown fault 0: No operation 1: Event occurs Charger reverse protection fault 0: No event occurs 1: Event occurs Charger bad adapter fault 0: No event occurs 1: Event occurs Reserved Charger timer time-out fault 0: No event occurs 1: Event occurs PMU WD done event 0: No event occurs 1: Event occurs PMU WD status event 0: No event occurs 1: Event occurs Reserved Charging current is lower than EOC current event occurs 0: No event occurs 1: Event occurs Charge termination event 0: No event occurs 1: Event occurs Reserved Charger or Boost softstart finishes event 0: No event occurs 1: Event occurs Watch dog timer timeout fault
Page 120 of 210
MT6360 PMIC Datasheet Confidential A Address
0xD5
0xD6
0xD7
Reg Name
CHG_IRQ6
DPDM IRQ
CHRDETB_I RQ
MediaTek Confidential
Bit
Bit Name
Default
Type
2 1
Reserved Reserved
0 0
R R
0
CHG_AICCMeasI_EVT
0
WC
7
BST_OLPI_EVT
0
WC
6
BST_MIDOVI_EVT
0
WC
5
BST_BATUVI_EVT
0
WC
4
ADC_DONEI
0
WC
3
ADC_WAKEUP_EVT
0
WC
2
Reserved
0
R
1
BAT_OVP_ADC_EVT
0
WC
0
PUMPX_DONEI_EVT
0
WC
7
DCDTI_EVT
0
WC
6:2
Reserved
00000
R
1
Detach_I
0
WC
0
Attach_I
0
WC
7:5
Reserved
000
R
4
CHRDETB_EXT_EVT
0
WC
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description 0: No event occurs 1: Event occurs Reserved Reserved AICC measurement function done event 0: No event occurs 1: Event occurs Boost overload protection event 0: No event occurs 1: Event occurs Boost CHG_VMID OVP fault event 0: No event occurs 1: Event occurs Boost low voltage input fault event 0: No event occurs 1: Event occurs ADC measurement done event 0: No event occurs 1: Event occurs ADC wake up event 0: No event occurs 1: Event occurs Reserved BAT_OVP_ADC fault event 0: No event occurs 1: Event occurs MTK pump express function done event 0: No event occurs 1: Event occurs Data contact detection event 0: Data contact detection timeout is not detected 1: Data contact detection timeout is detected when DCDT goes from 0 to 1 Reserved VBUS detach, when VBUSPG_D goes from 1 to 0 0: No event occurs 1: Event occurs Charger type detection done event 0: No event occurs 1: Event occurs Reserved VBUS voltage detect 0: No event 1: VBUS enters into or releases from normal region which is between UV_TH and OV_TH.
Page 121 of 210
MT6360 PMIC Datasheet Confidential A Address
0xD8
0xD9
Reg Name
BASE_IRQ
FLED_IRQ1
MediaTek Confidential
Bit
Bit Name
Default
Type
3
CHRDETB_OVP_EVT
0
WC
2
CHRDETB_UVPB_EVT
0
WC
1:0
Reserved
00
R
7
SYSUV_EVT
0
WC
6
VDDAOV_EVT
0
WC
5
OTP_EVT
0
WC
4
MRSTB_EVT
0
WC
3
QONB_RST_EVT
0
WC
2
EN_EVT
0
WC
1
APWDTRST_EVT
0
WC
0
USBID_EVT
0
WC
7
FLED1_SHORT_EVT
0
WC
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description VBUS OVP detection (deglitch 1ms) 0: No event occurs 1: Event occurs VBUS entry or release of OV_TH VBUS UVP detection (deglitch 1ms) 0: No event occurs 1: Event occurs VBUS entry or release of UV_TH Reserved Report whether the protection event of SYS UVLO occurs. 0: No protection event occurs. 1: Protection event ever occurs. Report whether the protection event of VDDA OVP occurs. 0: No protection event occurs. 1: Protection event ever occurs. Report whether the protection event of OTP ever occurs. 0: No protection event occurs. 1: Protection event ever occurs. Report whether the reset event of MRSTB ever occurs. 0: No reset event occurs. 1: Reset event ever occurs. Report whether the reset event of QONB Reset ever occurs. 0: No reset event occurs. 1: Reset event ever occurs. Report whether the EN pin ever switch. 0: No switch occurs 1: switch ever occurs Report whether the reset event of APWDTRST ever occurs. 0: No reset event occurs. 1: Reset event ever occurs. USB_ID interrupt (Rising/Falling trigger) 0: No event 1: The voltage of USB_ID > VTH_ID Report whether the event of FLED1 short-circuit occurs. 0: No event occurs. 1: Event ever occurs.
Page 122 of 210
MT6360 PMIC Datasheet Confidential A Address
0xDA
0xDC
Reg Name
Bit
Bit Name
Default
Type
6
FLED2_SHORT_EVT
0
WC
5:4
Reserved
00
R
3
FLED_LVF_EVT
0
WC
2
FLED_TX_EVT
0
WC
1
FLED_TORPIN_EVT
0
WC
0
FLED_STRBPIN_EVT
0
WC
7:6
Reserved
00
R
5
FLED1_TOR_EVT
0
WC
4
FLED2_TOR_EVT
0
WC
3
FLED1_STRB_TO_EVT
0
WC
2
FLED2_STRB_TO_EVT
0
WC
1
FLED1_STRB_EVT
0
WC
0
FLED2_STRB_EVT
0
WC
7
Reserved
0
R
6
BUCK1_UV_EVT
0
WC
5
BUCK1_OV_EVT
0
WC
FLED_IRQ2
BUCK1_IRQ
MediaTek Confidential
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description Report whether the event of FLED2 short-circuit occurs. 0: No event occurs. 1: Event ever occurs. Reserved Report whether the event of FLED low VF occurs. 0: No event occurs. 1: Event ever occurs. Report whether the event of FLED TXMask occurs. (If sENB_TX = 1'b1, this event will not interrupt) 0: No event occurs. 1: Event ever occurs. Report whether the event of FLED torch pin occurs. 0: No event occurs. 1: Event ever occurs. Report whether the event of FLED strobe pin occurs. 0: No event occurs. 1: Event ever occurs. Reserved Report whether the event of FLED1 torch occurs. 0: No event occurs. 1: Event ever occurs. Report whether the event of FLED2 torch occurs. 0: No event occurs. 1: Event ever occurs. Report whether the event of FLED1 strobe timeout occurs. 0: No event occurs. 1: Event ever occurs. Report whether the event of FLED2 strobe timeout occurs. 0: No event occurs. 1: Event ever occurs. Report whether the event of FLED1 strobe occurs. 0: No event occurs. 1: Event ever occurs. Report whether the event of FLED2 strobe occurs. 0: No event occurs. 1: Event ever occurs. Reserved Report whether BUCK1 UV occurs. 0: No event or be masked. 1: Protection ever occurs. Report whether BUCK1 OV occurs. 0: No event or be masked.
Page 123 of 210
MT6360 PMIC Datasheet Confidential A Address
0xDD
0xDE
Reg Name
Bit
Bit Name
Default
Type
4
BUCK1_OC_EVT
0
WC
3:1
Reserved
000
R
0
BUCK1_PGB_EVT
0
WC
7
Reserved
0
R
6
BUCK2_UV_EVT
0
WC
5
BUCK2_OV_EVT
0
WC
4
BUCK2_OC_EVT
0
WC
3:1
Reserved
000
R
0
BUCK2_PGB_EVT
0
WC
7
LDO7_OC_EVT
0
WC
6
LDO6_OC_EVT
0
WC
5
LDO5_OC_EVT
0
WC
4
Reserved
0
R
3
LDO3_OC_EVT
0
WC
2
LDO2_OC_EVT
0
WC
1
LDO1_OC_EVT
0
WC
0
Reserved
0
R
BUCK2_IRQ
LDO_EVT1
MediaTek Confidential
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description 1: Protection ever occurs. Report whether BUCK1 OC occurs. 0: No event or be masked. 1: Protection ever occurs. Reserved Report whether BUCK1 PG fault occurs. 0: No event or be masked. 1: PG fault ever occurs. Reserved Report whether BUCK2 UV occurs. 0: No event or be masked. 1: Protection ever occurs. Report whether BUCK2 OV occurs. 0: No event or be masked. 1: Protection ever occurs. Report whether BUCK2 OC occurs. 0: No event or be masked. 1: Protection ever occurs. Reserved Report whether BUCK2 PG fault occurs. 0: No event or be masked. 1: PG fault ever occurs. Report whether the event of LDO7 OC occurs. 0: No protection event occurs. 1: Event ever occurs. Report whether the event of LDO6 OC occurs. 0: No protection event occurs. 1: Event ever occurs. Report whether the event of LDO5 OC occurs. 0: No protection event occurs. 1: Event ever occurs. Reserved Report whether the event of LDO3 OC occurs. 0: No protection event occurs. 1: Event ever occurs. Report whether the event of LDO2 OC occurs. 0: No protection event occurs. 1: Event ever occurs. Report whether the event of LDO1 OC occurs. 0: No protection event occurs. 1: Event ever occurs. Reserved
Page 124 of 210
MT6360 PMIC Datasheet Confidential A Address
0xDF
0xE0
0xE1
Reg Name
LDO_EVT2
CHG_STAT1
CHG_STAT2
MediaTek Confidential
Bit
Bit Name
Default
Type
7
LDO7_PGB_EVT
0
WC
6
LDO6_PGB_EVT
0
WC
5
LDO5_PGB_EVT
0
WC
4
Reserved
0
R
3
LDO3_PGB_EVT
0
WC
2
LDO2_PGB_EVT
0
WC
1
LDO1_PGB_EVT
0
WC
0
Reserved
0
R
7
PWR_RDY_STAT
0
R
6
CHG_MIVR_STAT
0
R
5
CHG_AICR_STAT
0
R
4
CHG_TREG_STAT
0
R
3:0
Reserved
0000
R
0
R
7
STAT
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description Report whether LDO7 PG fault occurs. 0: No event. 1: PG fault ever occurs. Report whether LDO6 PG fault occurs. 0: No event. 1: PG fault ever occurs. Report whether LDO5 PG fault occurs. 0: No event. 1: PG fault ever occurs. Reserved Report whether LDO3 PG fault occurs. 0: No event. 1: PG fault ever occurs. Report whether LDO2 PG fault occurs. 0: No event. 1: PG fault ever occurs. Report whether LDO1 PG fault occurs. 0: No event. 1: PG fault ever occurs. Reserved Power ready status bit 0: Input power is bad, CHG_VIN > VOVP or CHG_VIN < VUVLO or CHG_VIN < BATS + VSLP 1: Input power is good, UVLO < CHG_VIN < VOVP & CHG_VIN > BATS + VSLP Charger warning. Input voltage MIVR loop active. 0: MIVR loop is not active 1: MIVR loop is active Charger warning. Input current AICR loop active. 0: AICR loop is not active 1: AICR loop is active Charger warning. Thermal regulation loop active. 0: Thermal regulation loop is not active 1: Thermal regulation loop is active Reserved VCHG_VIN over-voltage protection (when VCHG_VIN > VCHG_VIN_OVP) 0: VCHG_VIN is not overvoltage 1: VCHG_VIN is overvoltage
Page 125 of 210
MT6360 PMIC Datasheet Confidential A Address
0xE3
Reg Name
Bit
Bit Name
Default
Type
6
CHG_VBATOV_STAT
0
R
5
CHG_VSYSOV_STAT
0
R
4
CHG_VSYSUV_STAT
0
R
3
FLEDCHG_VINOVP_STAT
0
R
2
Reserved
0
R
1
CHG_BATSYSUV_STAT
0
R
0
Reserved
0
R
7
OTPI_STAT
0
R
6
CHG_RVPI_STAT
0
R
5
CHG_ADPBADI_STAT
0
R
4
Reserved
0
R
3
CHG_TMRI_STAT
0
R
2
WD_PMU_DONE_ STAT
0
R
1
WD_PMU_DET_STAT
0
R
0
Reserved
0
R
CHG_STAT4
MediaTek Confidential
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description Charger fault. Battery OVP. 0: Battery is not overvoltage 1: Battery is over-voltage Charger fault. System OVP. 0: System is not overvoltage 1: System is over-voltage Charger fault. System UVP. 0: System is not undervoltage 1: System is under-voltage CHG_VIN over voltage protection which only works when FLED is ON. CHG_VINVOP threshold voltage = 5.6 / 5.3V 0: CHG_VIN is not over voltage 1: CHG_VIN is over voltage Reserved The voltage: MAX (VBAT, VSYS) UVLO's state. 0: Max (VBAT, VSYS) is not UVLO 1: Max (VBAT, VSYS) is UVLO Reserved Thermal shutdown status 0: IC is not thermal shutdown 1: IC is thermal down Charger reverse protection status 0: Charger is not charger reverse protection 1: Charger is charger reverse protection Charger bad adapter status 0: Charger is not bad adapter 1: Charger is bad adapter Reserved Charger timer time-out status 0: Charger is not time-out 1: Charger is time-out Reserved for WD_PMU_DONE_STAT (short pulse, hard be read by I2C) PMU WD status 0: PMU is not in WD 1: PMU is in WD Reserved
Page 126 of 210
MT6360 PMIC Datasheet Confidential A Address
0xE4
0xE5
R
Reg Name
Bit
Bit Name
Default
Type
7
CHG_IEOCI_STAT
0
R
6
CHG_TERMI_STAT
0
R
5
Reserved
0
R
4
SSFINISHI_STAT
0
R
3
WDTMRI_STAT
0
R
2:1
Reserved
00
R
0
CHG_AICCMeasI_STAT
0
R
7
BST_OLPI_STAT
0
R
6
BST_MIDOVI_STAT
0
R
5
BST_BATUVI_STAT
0
R
4
ADC_DONEI_STAT
0
R
3
ADC_WAKEUP_STAT
0
R
CHG_STAT5
CHG_STAT6
Reserved 1
MediaTek Confidential
BAT_OVP_ADC_STAT
0
R
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description Charging current is lower than EOC current status 0: Charger is not EOC 1: Charger is EOC Charge terminated status 0: Charger is not terminated 1: Charger is terminated Reserved Charger or Boost softstart finishes status 0: Charger is not soft start finish 1: Charger is soft start finish Watch dog timer timeout fault status 0: Charger is not watch dog timer time-out 1: If CHG_WDT_EN (0x1D[7] = 1) and I2C is no read/write, Charger watch dog timer is timeout by CHG_WDT[1:0] (0x1D[5:4]). Then, WDWTMRI_STAT = 1 Reserved AICC measurement function done status 0: AICC is not done 1: AICC is done Boost overload protection status 0: Boost is not overload 1: Boost is overload Boost CHG_VMID OVP fault status 0: Boost is not OVP 1: Boost is OVP Boost low voltage input fault status 0: Boost is not low voltage input 1: Boost is low voltage input Reserved for ADC_DONEI (short pulse, hard be read by I2C) Reserved for ADC_WAKEUP (short pulse, hard be read by I2C) BAT_OVP_ADC fault status 0: BAT is not OVP 1: BAT is OVP
Page 127 of 210
MT6360 PMIC Datasheet Confidential A Address
0xE6
0xE7
0xE8
Reg Name
Bit
Bit Name
Default
Type
0
PUMPX_DONEI_STAT
0
R
7
DCDTI_STAT
0
R
6
CHGDETI_STAT
0
R
5:2
Reserved
0000
R
1
Detach_I_STAT
0
R
0
CHGDET_DONEI_ STAT
0
R
7:5
Reserved
000
R
4
CHRDETB_EXT_STAT
0
R
3
CHRDETB_OVP_STAT
0
R
2
CHRDETB_UVPB_STA T
0
R
1:0
Reserved
00
R
7
SYSUV_STAT
0
R
6
VDDAOV_STAT
0
R
DPDM_STAT
CHRDETB_S TAT
BASE_STAT
MediaTek Confidential
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description Reserved for PUMPX_DONEI_STAT (short pulse, hard be read by I2C) Data contact detection event 0: Data contact detection timeout is not detected 1: Data contact detection timeout is detected when DCDT goes from 0 to 1 Output of USB charger detection. The bit will be set to 1 if COMN > VDAT_REF & COMN < VLGC 0: COMN < VDAT_REF or COMN > VLGC (charger port is not detected) 1: COMN > VDAT_REF & COMN < VLGC (charger port is detected) when CHGDET goes from 0 to 1 Reserved VBUS detach, when VBUSPG_D goes from 1 to 0 0: VBUS is valid. 1: VBUS is invalid. Charger type detection done 0: No operation or charger type detection is detecting 1: Charger type detection is done Reserved VBUS voltage detect 0: VBUS ≤ VBUS_UV_TH or VBUS ≥ VBUS_OV_TH 1: VBUS_UV_TH < VBUS < VBUS_OV_TH VBUS OV detection (deglitch 1ms) 0: State low than OV_TH 1:State high than OV_TH VBUS UV detection (deglitch 1ms) 0: State low than UV_TH 1: State high than UV_TH Reserved SYS UVLO status 0: SYSUVLO is off or VSYS isn't under voltage 1: VSYS is under voltage VDDA OVP status 0: VDDAOVP is off or VDDA isn't over voltage 1: VDDA is over voltage
Page 128 of 210
MT6360 PMIC Datasheet Confidential A Address
0xE9
R
Reg Name
FLED_STAT1
Bit
Bit Name
Default
Type
5
OTP_STAT
0
R
4
MRSTB_STAT
0
R
3
QONB_RST_STAT
0
R
2
EN_STAT
0
R
1
APWDTRST_STAT
o
R
0
USBID_STAT
0
R
7
FLED1_SHORT_STAT
0
R
6
FLED2_SHORT_STAT
0
R
5:4
Reserved
00
R
3
FLED_LVF_STAT
0
R
2
FLED_TX_STAT
0
R
1
FLED_TORPIN_STAT
0
R
not occur
0xEA
FLED_STAT2
MediaTek Confidential
7:6
Reserved
00
R
5
FLED1_TOR_STAT
0
R
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description OTP status 0: OTPs are off or IC isn't over-temperature 1: IC is over-temperature Reserved for MRSTB_STAT (short pulse, hard be read by I2C) Reserved for QONB_RST_STAT (short pulse, hard be read by I2C) EN pin status (with 128µs de-bounding time) 0 : EN pin is logic Low 1 : EN pin is logic High Reserved for APWDTRST_STAT (short pulse, hard be read by I2C) Report USB_ID detector result 0: The voltage of USB_ID < VTH_ID or disable detector 1: The voltage of USB_ID > VTH_ID FLED1 short-circuit status 0: FLED1 short-circuit does not occur 1: FLED1 short-circuit occurred FLED2 short-circuit status 0: FLED2 short-circuit does not occur 1: FLED2 short-circuit occurred Reserved FLED low-VF status 0: FLED low-VF does not occur 1: FLED low-VF occurred FLED TXMask status 0: FLED TXMask does not occur 1: FLED TXMask occurred FLED torch pin status 0: FLED torch pin does not occur 1: FLED torch pin occurred FLED strobe pin status 0: FLED strobe pin does 1: FLED strobe pin occurred Reserved FLED1 torch mode status 0: FLED1 torch mode
Page 129 of 210
MT6360 PMIC Datasheet Confidential A Address
0xEC
0xED
Reg Name
Bit
Bit Name
Default
Type
4
FLED2_TOR_STAT
0
R
3
FLED1_STRB_TO_STA T
0
R
2
FLED2_STRB_TO_STA T
0
R
1
FLED1_STRB_STAT
0
R
0
FLED2_STRB_STAT
0
R
7
Reserved
0
R
6
BUCK1_UV_STAT
0
R
5
BUCK1_OV_STAT
0
R
4
BUCK1_OC_STAT
0
R
3:1
Reserved
000
R
0
BUCK1_PGB_STAT
0
R
7
Reserved
0
R
6
BUCK2_UV_STAT
0
R
BUCK1_STAT
BUCK2_STAT
MediaTek Confidential
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description does not occur 1: FLED1 torch mode occurred FLED2 torch mode status 0: FLED2 Torch mode does not occur 1: FLED2 Torch mode occurred FLED1 strobe timeout status 0: FLED1 strobe timeout does not occur 1: FLED1 strobe timeout occurred FLED2 strobe timeout status 0: FLED2 strobe timeout does not occur 1: FLED2 strobe timeout occurred FLED1 strobe mode Status 0: PFLED1 strobe does not occur 1: FLED1 strobe occurred FLED2 strobe mode status 0: FLED2 strobe does not occur 1: FLED2 strobe occurred Reserved Report BUCK1 UV state 0: BUCK1 is off or BUCK1_VOUT isn't under-voltage 1: BUCK1_VOUT is under-voltage Report BUCK1 OV state 0: BUCK1 is off or BUCK1_VOUT isn't overvoltage 1: BUCK1_VOUT is overvoltage Report BUCK1 OC state 0: BUCK1 is off or BUCK1 over-current doesn't occur 1: BUCK1 over-current occur Reserved Report BUCK1 PG fault state. 0: BUCK1 is off or BUCK1 PG fault doesn't occur 1: BUCK1 PG fault occurs Reserved Report BUCK2 UV state 0: BUCK2 is off or BUCK2_VOUT isn't under-voltage 1: BUCK2_VOUT is under-voltage
Page 130 of 210
MT6360 PMIC Datasheet Confidential A Address
0xEE
0xEF
Reg Name
LDO_STAT1
LDO_STAT2
MediaTek Confidential
Bit
Bit Name
Default
Type
5
BUCK2_OV_STAT
0
R
4
BUCK2_OC_STAT
0
R
3:1
Reserved
000
R
0
BUCK2_PGB_STAT
0
R
7
LDO7_OC_STAT
0
R
6
LDO6_OC_STAT
0
R
5
LDO5_OC_STAT
0
R
4
Reserved
0
R
3
LDO3_OC_STAT
0
R
2
LDO2_OC_STAT
0
R
1
LDO1_OC_STAT
0
R
0
Reserved
0
R
7
LDO7_PGB_STAT
0
R
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description Report BUCK2 OV state 0: BUCK2 is off or BUCK2_VOUT isn't overvoltage 1: BUCK2_VOUT is overvoltage Report BUCK2 OC state 0: BUCK1 is off or BUCK2 over-current doesn't occur 1: BUCK2 over-current occur Reserved Report BUCK2 PG fault state. 0: BUCK2 is off or BUCK2 PG fault doesn't occur 1: BUCK2 PG fault occurs Report whether the event of LDO7 OC occurs. 0: LDO7 is off or LDO7 over-current doesn't occur 1: LDO7 over-current occurs Report whether the event of LDO6 OC occurs. 0: LDO6 is off or LDO6 over-current doesn't occur 1: LDO6 over-current occurs Report whether the event of LDO5 OC occurs. 0: LDO5 is off or LDO5 over-current doesn't occur 1: LDO5 over-current occurs Reserved Report whether the event of LDO3 OC occurs. 0: LDO3 is off or LDO3 over-current doesn't occur 1: LDO3 over-current occurs Report whether the event of LDO2 OC occurs. 0: LDO2 is off or LDO2 over-current doesn't occur 1: LDO2 over-current occurs Report whether the event of LDO1 OC occurs. 0: LDO1 is off or LDO1 over-current doesn't occur 1: LDO1 over-current occurs Reserved Report LDO7 PG fault state. 0: LDO7 is off or LDO7 PG fault doesn't occur 1: LDO7 PG fault occurs
Page 131 of 210
MT6360 PMIC Datasheet Confidential A Address
0xF0
0xF1
Reg Name
Bit
Bit Name
Default
Type
6
LDO6_PGB_STAT
0
R
5
LDO5_PGB_STAT
0
R
4
Reserved
0
R
3
LDO3_PGB_STAT
0
R
2
LDO2_PGB_STAT
0
R
1
LDO1_PGB_STAT
0
R
0
Reserved
0
R
7
PWR_RDYM
1
RW
6
CHG_MIVRM
1
RW
5
CHG_AICRM
1
RW
4
CHG_TREGM
1
RW
3:0
Reserved
1111
R
7
CHG_VINOVPCHGM
1
RW
6
CHG_VBATOVM
1
RW
5
CHG_VSYSOVM
1
RW
4
CHG_VSYSUVM
1
RW
CHG_MASK1
CHG_MASK2
MediaTek Confidential
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description Report LDO6 PG fault state. 0: LDO6 is off or LDO6 PG fault doesn't occur 1: LDO6 PG fault occurs Report LDO5 PG fault state. 0: LDO5 is off or LDO5 PG fault doesn't occur 1: LDO5 PG fault occurs. Reserved Report LDO3 PG fault state. 0: LDO3 is off or LDO3 PG fault doesn't occur 1: LDO3 PG fault occurs Report LDO2 PG fault state. 0: LDO2 is off or LDO2 PG fault doesn't occur 1: LDO2 PG fault occurs Report LDO1 PG fault state. 0: LDO1 is off or LDO1 PG fault doesn't occur 1: LDO1 PG fault occurs Reserved Power ready interrupt mask 0: Interrupt is not masked 1: Interrupt is masked Input voltage MIVR loop active interrupt mask 0: Interrupt is not masked 1: Interrupt is masked Input current AICR loop active interrupt mask 0: Interrupt is not masked 1: Interrupt is masked Thermal regulation loop active interrupt mask 0: Interrupt is not masked 1: Interrupt is masked Reserved CHG_VIN over-voltage protection mask 0: Interrupt is not masked 1: Interrupt is masked Battery OVP interrupt mask 0: Interrupt is not masked 1: Interrupt is masked System OVP interrupt mask 0: Interrupt is not masked 1: Interrupt is masked System UVP interrupt mask 0: Interrupt is not masked 1: Interrupt is masked
Page 132 of 210
MT6360 PMIC Datasheet Confidential A Address
0xF3
0xF4
Reg Name
CHG_MASK4
CHG_MASK5
MediaTek Confidential
Bit
Bit Name
Default
Type
3
FLED-CHG_VINOVPM
1
RW
2
Reserved
1
R
1
CHG_BATSYSUVM
1
RW
0
Reserved
1
R
7
OTPM
1
RW
6
CHG_RVPM
1
RW
5
CHG_ADPBADM
1
RW
4
Reserved
1
R
3
CHG_TMRM
1
RW
2
WD_PMU_DONEM
1
RW
1
WD_PMU_DETM
1
RW
0
Reserved
1
R
7
CHG_IEOCM
1
RW
6
CHG_TERMM
1
RW
5
Reserved
1
R
4
SSFINISHM
1
RW
3
WDTMRM
1
RW
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description CHG_VIN over 5.6V voltage protection mask which only works when FLED is ON 0: Interrupt is not masked 1: Interrupt is masked Reserved The voltage : MAX (VBAT, VSYS) UVLO's mask 0: Interrupt is not masked 1: Interrupt is masked Reserved Thermal shutdown fault interrupt mask 0: Interrupt is not masked 1: Interrupt is masked Charger reverse protection fault interrupt mask 0: Interrupt is not masked 1: Interrupt is masked Charger bad adapter fault interrupt mask 0: Interrupt is not masked 1: Interrupt is masked Reserved Charger timer timeout fault interrupt mask 0: Interrupt is not masked 1: Interrupt is masked PMU WD done interrupt mask 0: Interrupt is not masked 1: Interrupt is masked PMU WD status interrupt mask 0: Interrupt is not masked 1: Interrupt is masked Reserved Charging current is lower than EOC current interrupt mask 0: Interrupt is not masked 1: Interrupt is masked Charge terminated event interrupt mask 0: Interrupt is not masked 1: Interrupt is masked Reserved Charger or Boost soft start finishes event interrupt mask 0: Interrupt is not masked 1: Interrupt is masked Watch dog timer timeout fault interrupt mask 0: Interrupt is not masked 1: Interrupt is masked
Page 133 of 210
MT6360 PMIC Datasheet Confidential A Address
0xF5
0xF6
RW
Reg Name
CHG_MASK6
DPDM_MAS K1
Bit
Bit Name
Default
Type
2
CHGDET_DONEM
1
RW
1
Reserved
1
R
0
CHG_AICCMeasM
1
RW
7
BST_OLPM
1
RW
6
BST_MIDOVM
1
RW
5
BST_BATUVM
1
RW
4
ADC_DONEM
1
RW
3
ADC_WAKEUP_MASK
1
RW
2
Reserved
0
R
1
BAT_OVP_ADC_MASK
1
RW
0
PUMPX_DONEM
1
RW
7
DCDTM
1
RW
6
CHGDETM
1
RW
5:2
Reserved
1111
R
1
Detach_M
1
RW
done interrupt mask
0xF7
CHRDETB_M ASK
MediaTek Confidential
Description Charger type detection done event interrupt mask 0: Interrupt is not masked 1: Interrupt is masked Reserved AICC measurement function done event interrupt mask 0: Interrupt is not masked 1: Interrupt is masked Boost overload protection event interrupt mask 0: Interrupt is not masked 1: Interrupt is masked Boost CHG_VMID OVP fault event interrupt mask 0: Interrupt is not masked 1: Interrupt is masked Boost low voltage input fault event interrupt mask 0: Interrupt is not masked 1: Interrupt is masked ADC measurement done event interrupt mask 0: Interrupt is not masked 1: Interrupt is masked ADC wake up event interrupt mask 0: Interrupt is not masked 1: Interrupt is masked Reserved BAT_OVP_ADC fault event interrupt mask 0: Interrupt is not masked 1: Interrupt is masked MTK pump express function done event interrupt mask 0: Interrupt is not masked 1: Interrupt is masked Data contact detection event interrupt mask 0: Interrupt is not masked 1: Interrupt is masked Output of USB charger detection interrupt mask 0: Interrupt is not masked 1: Interrupt is masked Reserved VBUS detach event interrupt mask 0: Interrupt is not masked 1: Interrupt is masked Charger type detection
7:5
Reserved
000
R
0: Interrupt is not masked 1: Interrupt is masked Reserved
4
CHRDETB_EXT_MASK
0
RW
VBUS EXT interrupt mask
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Page 134 of 210
MT6360 PMIC Datasheet Confidential A Address
0xF8
Reg Name
Bit
Bit Name
Default
Type
3
CHRDETB_OVP_MASK
1
RW
2
CHRDETB_UVPB_MAS K
1
RW
1:0
Reserved
00
R
7
SYSUV_MASK
1
RW
6
VDDAOV_MASK
1
RW
5
OTP_MASK
1
RW
4
MRSTB_MASK
1
RW
3
QONB_RST_MASK
1
RW
2
EN_MASK
1
RW
1
APWDTRST_MASK
1
RW
0
USB_ID_MASK
1
RW
7
FLED1_SHORT_MASK
1
RW
BASE_MASK
1: Interrupt is masked. 0xF9 MASK1 6
MediaTek Confidential
FLED2_SHORT_MASK
1
RW
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description 0: Interrupt is not masked. 1: Interrupt is masked. VBUS OVP interrupt mask 0: Interrupt is not masked. 1: Interrupt is masked. VBUS UVP interrupt mask 0: Interrupt is not masked. 1: Interrupt is masked. Reserved SYS UVLO interrupt mask. 0: Interrupt is not masked. 1: Interrupt is masked. VDDA OVP interrupt mask. 0: Interrupt is not masked. 1: Interrupt is masked. OTP interrupt mask. 0: Interrupt is not masked. 1: Interrupt is masked. MRSTB Reset interrupt mask. 0: Interrupt is not masked. 1: Interrupt is masked. QONB Reset interrupt mask. 0: Interrupt is not masked. 1: Interrupt is masked. EN interrupt mask. 0: Interrupt is not masked. 1: Interrupt is masked. APWDTRST interrupt mask. 0: Interrupt is not masked. 1: Interrupt is masked. USB_ID interrupt mask 0: Interrupt is not masked. 1: Interrupt is masked. FLED1 short-circuit mask. 0: Interrupt is not masked. FLED2 short-circuit mask. 0: Interrupt is not masked. 1: Interrupt is masked.
Page 135 of 210
MT6360 PMIC Datasheet Confidential A Address
0xFA
0xFB
Reg Name
Bit 5:4
Bit Name Reserved
Default 11
Type R
3
FLED_LVF_MASK
1
RW
2
FLED_TX_MASK
1
RW
1
FLED_TORPIN_MASK
1
RW
0
FLED_STRBPIN_MASK
1
RW
7:6
Reserved
11
R
5
FLED1_TOR_MASK
1
RW
4
FLED2_TOR_MASK
1
RW
3
FLED1_STRB_TO_MAS K
1
RW
2
FLED2_STRB_TO_MA SK
1
RW
1
FLED1_STRB_MASK
1
RW
0
FLED2_STRB_MASK
1
RW
7
BUCK1_FAULTB_MAS K
0
RW
6
BUCK2_FAULTB_MASK
0
RW
5
LDO7_FAULTB_MASK
0
RW
FLED_MASK 3
FAULTB_MA SK
MediaTek Confidential
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description Reserved FLED low-VF mask. 0: Interrupt is not masked. 1: Interrupt is masked. FLED TXMask mask. 0: Interrupt is not masked. 1: Interrupt is masked. FL_TORCH pin mask. 0: Interrupt is not masked. 1: Interrupt is masked. FL_STROBE pin mask. 0: Interrupt is not masked. 1: Interrupt is masked. Reserved FLED1 torch interrupt mask. 0: Interrupt is not masked. 1: Interrupt is masked. FLED2 torch interrupt mask. 0: Interrupt is not masked. 1: Interrupt is masked. FLED1 strobe timeout interrupt mask. 0: Interrupt is not masked. 1: Interrupt is masked. FLED2 strobe timeout interrupt mask. 0: Interrupt is not masked. 1: Interrupt is masked. FLED1 strobe interrupt mask. 0: Interrupt is not masked. 1: Interrupt is masked. FLED2 strobe interrupt mask. 0: Interrupt is not masked. 1: Interrupt is masked. BUCK1 PGB FAULTB MASK 0: FAULTB isn't masked 1: FAULTB is masked BUCK2 PGB FAULTB MASK 0: FAULTB isn't masked 1: FAULTB is masked LDO7 PGB FAULTB MASK 0: FAULTB isn't masked 1: FAULTB is masked
Page 136 of 210
MT6360 PMIC Datasheet Confidential A Address
0xFC
0xFD
Reg Name
BUCK_MASK
BUCK_MASK
MediaTek Confidential
Bit
Bit Name
Default
Type
4
LDO6_FAULTB_MASK
0
RW
3
LDO5_FAULTB_MASK
1
RW
2
LDO3_FAULTB_MASK
1
RW
1
LDO2_FAULTB_MASK
1
RW
0
LDO1_FAULTB_MASK
1
RW
7
Reserved
1
R
6
BUCK1_UV_MASK
1
RW
5
BUCK1_OV_MASK
1
RW
4
BUCK1_OC_MASK
1
RW
3:1
Reserved
111
R
0
BUCK1_PGB_MASK
1
RW
7
Reserved
1
R
6
BUCK2_UV_MASK
1
RW
5
BUCK2_OV_MASK
1
RW
4
BUCK2_OC_MASK
1
RW
3:1
Reserved
111
RW
1
BUCK2_PGB_MASK
1
RW
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description LDO6 PGB FAULTB MASK 0: FAULTB isn't masked 1: FAULTB is masked LDO5 PGB FAULTB MASK 0: FAULTB isn't masked 1: FAULTB is masked LDO3 PGB FAULTB MASK 0: FAULTB isn't masked 1: FAULTB is masked LDO2 PGB FAULTB MASK 0: FAULTB isn't masked 1: FAULTB is masked LDO1 PGB FAULTB MASK 0: FAULTB isn't masked 1: FAULTB is masked Reserved BUCK1 UV interrupt's mask 0: Interrupt is not masked. 1: Interrupt is masked. BUCK1 OV interrupt's mask 0: Interrupt is not masked. 1: Interrupt is masked. BUCK1 OC interrupt's mask 0: Interrupt is not masked. 1: Interrupt is masked. Reserved BUCK1 PG Fault interrupt's mask 0: Interrupt is not masked. 1: Interrupt is masked. Note: If BUCK1 is in sequence, this bit's default value is 1'b0 Reserved BUCK2 UV interrupt's mask 0: Interrupt is not masked. 1: Interrupt is masked. BUCK2 OV interrupt's mask 0: Interrupt is not masked. 1: Interrupt is masked. BUCK2 OC interrupt's mask 0: Interrupt is not masked. 1: Interrupt is masked. Reserved BUCK2 PG Fault interrupt's mask
Page 137 of 210
MT6360 PMIC Datasheet Confidential A Address
0xFE
0xFF
Reg Name
LDO_MASK1
LDO_MASK2
MediaTek Confidential
Bit
Bit Name
Default
Type
7
LDO7_OC_MASK
1
RW
6
LDO6_OC_MASK
1
RW
5
LDO5_OC_MASK
1
RW
4
Reserved
1
R
3
LDO3_OC_MASK
1
RW
2
LDO2_OC_MASK
1
RW
1
LDO1_OC_MASK
1
RW
0
Reserved
1
R
7
LDO7_PGB_MASK
1
RW
6
LDO6_PGB_MASK
1
RW
5
LDO5_PGB_MASK
1
RW
4
Reserved
1
R
3
LDO3_PGB_MASK
1
RW
2
LDO2_PGB_MASK
1
RW
1
LDO1_PGB_MASK
1
RW
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description 0: Interrupt is not masked. 1: Interrupt is masked. Note: If BUCK2 is in sequence, this bit's default value is 1'b0 LDO7 OC interrupt's mask 0: Interrupt is not masked. 1: Interrupt is masked. LDO6 OC interrupt's mask 0: Interrupt is not masked. 1: Interrupt is masked. LDO5 OC interrupt's mask 0: Interrupt is not masked. 1: Interrupt is masked. Reserved LDO3 OC interrupt's mask 0: Interrupt is not masked. 1: Interrupt is masked. LDO2 OC interrupt's mask 0: Interrupt is not masked. 1: Interrupt is masked. LDO1 OC interrupt's mask 0: Interrupt is not masked. 1: Interrupt is masked. Reserved LDO7 PG interrupt's mask 0: Interrupt is not masked. 1: Interrupt is masked. LDO6 PG interrupt's mask 0: Interrupt is not masked. 1: Interrupt is masked. LDO5 PG interrupt's mask 0: Interrupt is not masked. 1: Interrupt is masked. Reserved LDO3 PG interrupt's mask 0: Interrupt is not masked. 1: Interrupt is masked. LDO2 PG interrupt's mask 0: Interrupt is not masked. 1: Interrupt is masked. LDO1 PG interrupt's mask 0: Interrupt is not masked. 1: Interrupt is masked.
Page 138 of 210
MT6360 PMIC Datasheet Confidential A Address
Reg Name
MediaTek Confidential
Bit 0
Bit Name Reserved
Default 1
Type R
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description Reserved
Page 139 of 210
MT6360 PMIC Datasheet Confidential A Table 5-6. PMIC Part Register Detail Description Address
Reg Name
Bit
0x00
RST_PMIC_P AS_CODE1
7:0
RST_PMIC_PAS_CODE 00000000 1
RW
0x01
RST_PMIC_P AS_CODE1
7:0
RST_PMIC_PAS_CODE 00000000 1
RW
0x02
RST_PMIC
MediaTek Confidential
Bit Name
Default
Type
7
ALL_PMIC_RST
0
WC
6
Reserved
0
R
5
BUCK2_RST
0
WC
4
BUCK1_RST
0
WC
3
LDO7_RST
0
WC
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description RST_PMIC_PAS_CODE1 [7:0] / Passcode 1 for RST: Set REG_PMIC0x00 = 8'hA9 then set REG_PMIC0x01 = 8'h96 , can start up REG_PMIC0x02: ***_RST. To erase RST_PMIC_PAS_CODE, REG_PMU0x02 won't work. RST_PMIC_PAS_CODE1 [7:0] / Passcode 1 for RST: Set REG_PMIC0x00 = 8'hA9 then set REG_PMIC0x01 = 8'h96 , can start up REG_PMIC0x02: ***_RST. To erase RST_PMIC_PAS_CODE, REG_PMU0x02 won't work. All PMIC relative registers and logic reset bit. 0: Don't reset all registers and logic 1: Reset all registers and logic. (Notice: This bit will be reset to "0" after reset procedure finish) Reserved BUCK2 registers and logic reset bit. 0: Don't reset BUCK2 relative registers and logic. 1: Reset BUCK2 relative registers and logic. (Notice: This bit will be reset to "0" after reset procedure finish) BUCK1 registers and logic reset bit. 0: Don't reset BUCK1 relative registers and logic. 1: Reset BUCK1 relative registers and logic. (Notice: This bit will be reset to "0" after reset procedure finish) LDO7 registers and logic reset bit.
Page 140 of 210
MT6360 PMIC Datasheet Confidential A Address
0x04
0x05
0x06
Reg Name
Bit
Bit Name
Default
Type
2
LDO6_RST
0
WC
1
Reserved
0
R
0
REG_PMIC_RST
0
WC
7:5
HW_SYSUV_SEL
001
RW
4:1
SYSUV_SEL
0010
RW
0
Reserved
1
R
7:6
TD_SYSUV_F
00
RW
5:0
Reserved
000000
R
7
HWEN_RPL_ENB
0
RWSC
SYSUV_CTRL 1
SYSUV_CTRL 2
HW_TRAPPI NG
MediaTek Confidential
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description 0: Don't reset LDO7 relative registers and logic. 1: Reset LDO7 relative registers and logic. (Notice: This bit will be reset to "0" after reset procedure finish) LDO6 registers and logic reset bit. 0: Don't reset LDO6 relative registers and logic. 1: Reset LDO6 relative registers and logic. (Notice: This bit will be reset to "0" after reset procedure finish) Reserved REG_PMIC registers reset bits 0: Don't reset REG_PMU registers. 1: Reset Specified REG_PMIC register according to RST table. (Notice: This bit will be reset to "0" after reset procedure finish) SYSUVLO rising threshold voltage setting: 000: 2.8V 001: 2.9V 010: 3.0V 011: 3.1V 100: 3.2V 101 to 111: 3.3V Note: UVLO_SEL pin defines default value SYSUVLO falling threshold voltage selection (50mV/step) 0000: 2.4V 0001: 2.45V 0010: 2.5V … 0111: 2.75V 1000 to 1111: 2.8V Reserved SYSUVLO falling deglitch time selection: 00: 0µs (only clock sampling) 01: 16µs 10: 32µs 11: 64µs Reserved 0: EN pin has 350kΩ. pull down resistor 1: EN pin is floating gate
Page 141 of 210
MT6360 PMIC Datasheet Confidential A Address
Reg Name USBPD_REV _VER
Bit
Bit Name
Default
Type
6
SRCLKEN_2
0
RW
5:4
TB_REBOOT
00
RW
3
FAULTB_STAT
0
R
2:0
HW_TRAPPING
000
R
010: BUCK1_VOUT =
MediaTek Confidential
Description Note: HW Reset condition 1. When SYSUV happen 2. When APWDTRST trigger 3. CHG_QONB long press shutdown 4. While enter Shipping mode When (CHx_SCLKEN_2_OP_E N = 1'b1 & CHx_SRCLKEN_2_OP_C FG = 2'b00), this bit is for CHx ON/OFF control 0: Disable CHx immediately 1: Elect CHx ON When (CHx_SCLKEN_2_OP_E N = 1'b1 & CHx_SRCLKEN_2_OP_C FG = 2'b10), this bit is for Low power mode enable control 1: Normal mode 0: Low power mode Blocking time between PMIC OFF to ON 00: 0ms 01: 25ms 10: 50ms 11: 100ms Note: Remain EN 128µs de-bounce time It indicate the PG fault of all LDOs and BUCKs 0: No PG fault 1: Any of BUCKs and LDOs has PG fault Report HW_TRAPPING detected result for BUCKx and VDRAM's default setting: 000: BUCK1_VOUT = 0.45 to 1V (VPU/VMDLA/VPROC12) BUCK2_VOUT = 1.125V (VDRAM1 LP4x) VDRAM2 =0.6V 001: BUCK1_VOUT = 0.45 to 1V (VPU/VMDLA/VPROC12) BUCK2_VOUT = 1.125V (VDRAM1 LP4x) VDRAM2 = 1.8V 1.125V (VDRAM1 LP4x) BUCK2_VOUT = 0.45 to 1V (VPU/VMDLA/VPROC12) VDRAM2 = 0.6V
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Page 142 of 210
MT6360 PMIC Datasheet Confidential A Address
0x07
0x08
Reg Name
BUCK1_SEQ OFFDLY
BUCK2_SEQ OFFDLY
Bit
Bit Name
Default
Type
7:6
Reserved
00
R
5:0
BUCK1_SEQOFFTD
000000
RW
7:6
Reserved
00
R
5:0
BUCK2_SEQOFFTD
000000
RW
111111: 126ms
0x09
MediaTek Confidential
7:6
Reserved
00
R
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description 011: BUCK1_VOUT =1.125V (VDRAM1 LP4x) BUCK2_VOUT = 0.45 to 1V (VPU/VMDLA/VPROC12) VDRAM2 = 1.8V 100: BUCK1_VOUT = 0.45 to 1V (VPU/VMDLA/VPROC12) BUCK2_VOUT = 1.225V (VDRAM1 LP3) VDRAM2 off 101: BUCK1_VOUT = 1.225V (VDRAM1 LP3) BUCK2_VOUT = 0.45 to 1V (VPU/VMDLA/VPROC12) VDRAM2 off 110: BUCK1_VOUT = 0.45 to 1V (VPU/VMDLA/VPROC12) BUCK2_VOUT = 1.125V (VDRAM1 LP4) VDRAM2 off 111: BUCK1_VOUT = 0.45 to 1V (VPU/VMDLA/VPROC12) BUCK2_VOUT = 0.45 to 1V (VPU/VMDLA/VPROC12) VDRAM2 off Reserved BUCK1 sequenced off delay time selection (2ms/step): 000000: 0ms 000001: 2ms ... 000110: 12ms ... 111110: 124ms 111111: 126ms Note: If BUCK1 isn't in sequence, these bits are useless. Reserved BUCK2 sequenced off delay time selection (2ms/step): 000000: 0ms 000001: 2ms ... 000100: 8ms ... 111110: 124ms Note: If BUCK2 isn't in sequence, these bits are useless. Reserved
Page 143 of 210
MT6360 PMIC Datasheet Confidential A Address
Reg Name
Bit
Bit Name
Default
Type
LDO7_SEQO FFDLY
5:0
LDO7_SEQOFFTD
000000
RW
7:6
Reserved
00
R
5:0
LDO6_SEQOFFTD
000000
RW
0x0A
LDO6_SEQO FFDLY
0x10
BUCK1_ VOSEL
7:0
BUCK1_VOSEL
00000000
RW
0x11
BUCK1_LP_V OSEL
7:0
BUCK1_LP_VOSEL
00000000
RW
7
BUCK1_OC_EN
1
RW
6:5
BUCK1_OC_WND
01
RW
4:3
BUCK1_OC_THD
01
RW
0x12
BUCK1_OC
MediaTek Confidential
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description LDO7 (VDRAM2) sequenced off delay time selection (2ms/step): 000000: 0ms 000001: 2ms 000010: 4ms ... 111110: 124ms 111111: 126ms Note: If LDO7 isn't in sequence, these bits are useless. Reserved LDO6 ( VMDDR ) sequenced off delay time selection (2ms/step): 000000: 0ms 000001: 2ms 000010: 4ms ... 111110: 124ms 111111: 126ms Note: If LDO6 isn't in sequence, these bits are useless. BUCK1 VOUT selection in normal mode: (5mV/step) 00000000: 0.3V 01011010: 0.75V 10100101: 1.125V 10111001: 1.225V 11001000 to 11111111: 1.3V BUCK1_VO in Normal mode = 0.3V + (5mV x code) Note: default value decide by HW_TRAPPING BUCK1 VOUT selection in LP mode: (5mV/step) 00000000: 0.3V 01011010: 0.75V 10100101: 1.125V 10111001: 1.225V 11001000 to 11111111: 1.3V BUCK1_VO in LP mode = 0.3V + (5mV x code) Note: default value decide by REG_PMU0x99[2:0] BUCK1 OC enable 0: Disable 1: Enable BUCK1 OC window 00: 8µs 01: 16µs 10: 32µs 11: 64µs BUCK1 OC flag occur condition 00: 4times 01: 8times
Page 144 of 210
MT6360 PMIC Datasheet Confidential A Address
0x13
0x14
0x15
0x16
Reg Name
Bit
Bit Name
Default
Type
2
BUCK1_OC_STATUS
0
R
1
BUCK1_OC_SDN_EN
0
RW
0
BUCK1_FPWM_DN_E N
1
RW
7
BUCK1_SFCHG_REN
1
RW
6:0
BUCK1_SFCHG_RRAT E
0000010
RW
7
BUCK1_SFCHG_FEN
1
RW
6:0
BUCK1_SFCHG_FRATE
0000101
RW
7
Reserved
0
R
6:5
BUCK1_DVS_EN_CTRL
11
RW
4:3
BUCK1_DVS_EN_TD
01
RW
2:1
BUCK1_OC_limit
10
RW
0
Reserved
0
R
7
BUCK1_GO_LP_OP
0
RWSC
BUCK1_SFCH G_R
BUCK1_SFCH G_F
BUCK1_DVS
BUCK1_EN_ CTRL1
MediaTek Confidential
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description 10: 16times 11: 32times BUCK1 OC Status 0: No OC 1: OC occur BUCK1 OC shutdown enable: 0: OC occur don't turn off BUCK1, only interrupt 1: OC occur turn off BUCK1 and reset BUCK1_EN_CTRL1/2 except auto-writing BUCK1_SW_EN = 1'b0. BUCK1 TRA_DN sPWM Enable: 0: Disable sPWM 1: Enable sPWM BUCK1 soft change rising enable 0: Disable 1: Enable BUCK1 soft change rising rate Ref clock = 3MHz, 1 step (5mV) = (code+1) / 3M BUCK1 soft change falling enable 0: Disable 1: Enable BUCK1 soft change falling rate Ref clock = 3MHz, 1 step (5mV) = (code+1) / 3M Reserved BUCK1 DVS_EN transition pulse enable: 00: Disable 01: Falling Enable 10: Rising Enable 11: Rising/Falling Enable BUCK1 DVS_EN transition pulse window: 00: 30µs 01: 45µs 10: 60µs 11: 75µs BUCK1 out load limit: 00: NA 01: 3A 10: 4A 11: 5A Reserved 0: Prefer LP; enter LP if one of SRCLKEN_0/SRCLKEN_ 2/REG_EN is "LP" 1: Prefer no LP; leave LP if one of
Page 145 of 210
MT6360 PMIC Datasheet Confidential A Address
0x17
Reg Name
BUCK1_EN_ CTRL2
MediaTek Confidential
Bit
Bit Name
Default
Type
6
Reserved
0
R
5
BUCK1_SRCLKEN_0_O P_EN
0
RWSC
4:3
BUCK1_SRCLKEN_0_O P_CFG
00
RWSC
2
BUCK1_SRCLKEN_2_O P_EN
0
RWSC
1:0
BUCK1_SRCLKEN_2_ OP_CFG
00
RWSC
7
BUCK1_SW_OP_EN
1
RWSC
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description SRECLKEN_0/SRCLKEN _2/REG_EN is "NO LP" Reserved 0: Deprive the control power of SRCLKEN_0 pin for BUCK1 1: Allow SRCLKEN_0 pin to control BUCK1 Select the use of SRCLKEN_0 pin when BUCK1_SRCLKEN_0_OP _EN = 1'b1 00: SRCLKEN_0 pin can elect BUCK1 ON /OFF When SRCLKEN_0 pin is logic low, elect BUCK1 OFF When SRCLKEN_0 pin is logic high, elect BUCK1 ON 01: NA 10: SRCLKEN_0 pin can elect BUCK1 LP mode ON/OFF When SRCLKEN_0 pin is logic low, elect BUCK1 LP mode ON When SRCLKEN_0 pin is logic high, elect BUCK1 LP mode OFF 11: NA 0: Deprive the control power of SRCLKEN_2for BUCK1 1: Allow SRCLKEN_2 to control BUCK1 Select the use of SRCLKEN_2 when BUCK1_SRCLKEN_2_OP _EN = 1'b1 00: SRCLKEN_2 can elect BUCK1 ON / OFF When SRCLKEN_2 is logic low, elect BUCK1 OFF When SRCLKEN_2 is logic high, elect BUCK1 ON 01: NA 10: SRCLKEN_2 can elect BUCK1 LP Mode ON/OFF When SRCLKEN_2 is logic low, elect BUCK1 LP mode ON When SRCLKEN_2 is logic high, elect BUCK1 LP mode OFF 11: NA 0: Deprive the control power of BUCK1_SW_EN/LP
Page 146 of 210
MT6360 PMIC Datasheet Confidential A Address
0x18
Reg Name
Bit
Bit Name
Default
Type
6
BUCK1_SW_EN
0
RWSC
5
BUCK1_SW_LP
0
RWSC
4
Reserved
0
R
3
BUCK1_GO_ON_OP
0
RWSC
2
BUCK1_EN
0
R
1:0
BUCK1_MODE
00
R
7:6
Reserved
00
R
5:4
BUCK1_STCD_TD
00
RW
3
BUCK1_STCD
0
R
2
BUCK1_PG
0
R
BUCK1_CTRL 1
MediaTek Confidential
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description 1: Allow BUCK1_SW_EN/LP working This bit is useless when BUCK1_SW_OP_EN = 1'b0 0: Elect BUCK1 OFF 1: Elect BUCK1 ON Note1: If BUCK1 is in sequence, the default value = 1'b1 Note2: When BUCK1 power is not good or OC happens and only turns off itself, reset BUCK1_EN_CTRLx except auto-writing this bit = 1'b0. And EN pin = 0->1 will reload this bit to the default value This bit is useless when BUCK1_SW_OP_EN = 1'b0 0: Elect BUCK1 LP mode OFF 1: Elect BUCK1 LP mode ON Reserved 0: Prefer ON; turn ON if one of SRCLKEN_0/SRCLKEN_ 2/REG_EN is "ON" 1: Prefer OFF; turn OFF if one of SRECLKEN_0/SRCLKEN _2/REG_EN is "OFF" Indicate the result of enable election 0: BUCK1 is ON 1: BUCK1 is OFF Indicate the operation mode of BUCK1 00: Normal mode 01: NA 10: LP mode 11: NA Reserved BUCK1 FAULT extended block time after soft-start count down 00: 1ms 01: 2ms 10: 4ms 11: 8ms It indicates BUCK1 softstart count down or not 0: Off or soft-start not count down 1: Soft-start count down It indicates BUCK1 power good or not
Page 147 of 210
MT6360 PMIC Datasheet Confidential A Address
0x19
Reg Name
BUCK1_CTRL 2
Bit
Bit Name
Default
Type
1:0
BUCK1_PGB_PTSEL
10
RW
7:6
Reserved
01
R
5:4
BUCK1_SS_SR
11
RW
3:0
Reserved
0000
R
0x20
BUCK2_VOS EL
7:0
BUCK2_VOSEL
00000000
RW
0x21
BUCK2_LP_V OSEL
7:0
BUCK2_LP_VOSEL
00000000
RW
7
BUCK2_OC_EN
1
RW
6:5
BUCK2_OC_WND
01
RW
0x22
BUCK2_OC
MediaTek Confidential
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description 0: Power not good or off 1: Power good (BUCK1_STCD = 1 and sPG_BUCK1 = 1) The reaction when BUCK1 power not good happens 00: Only interrupt, and won't disable any channel 01: Only shutdown BUCK1 and reset BUCK1_EN_CTRL1/2 then set BUCK1_EN=1'b0 10: Shutdown all Bucks and LDOs, reset CHx_EN_CTRL1/2 and after the blocking time: TB_REBOOT, then confirm EN pin 11: Equal to 2'b10 Reserved The speed of SOFT START DVS 00 = 10mV step/µs 01 = 5mV step/µs 10 = 2.5mV step/µs 11 = 1.25mV step/µs Reserved BUCK2 VOUT selection in normal mode: (5mV/step) 00000000: 0.3V 01011010: 0.75V 10100101: 1.125V 10111001: 1.225V 11001000 to 11111111: 1.3V BUCK2_VO in normal mode = 0.3V + (5mV x code) Note: Default value decide by HW_TRAPPING BUCK2 VOUT selection in LP mode: (5mV/step) 00000000: 0.3V 01011010: 0.75V 10100101: 1.125V 10111001: 1.225V 11001000 to 11111111: 1.3V BUCK2_VO in LP mode = 0.3V + (5mV x code) Note: Default value decide by HW_TRAPPING BUCK2 OC enable 0: Disable 1: Enable BUCK2 OC window 00: 8µs 01: 16µs 10: 32µs 11: 64µs
Page 148 of 210
MT6360 PMIC Datasheet Confidential A Address
0x23
0x24
0x25
Reg Name
Bit
Bit Name
Default
Type
4:3
BUCK2_OC_THD
01
RW
2
BUCK2_OC_STATUS
0
R
1
BUCK2_OC_SDN_EN
0
RW
0
BUCK2_FPWM_DN_E N
1
RW
7
BUCK2_SFCHG_REN
1
RW
6:0
BUCK2_SFCHG_RRAT E
0000010
RW
7
BUCK2_SFCHG_FEN
1
RW
6:0
BUCK2_SFCHG_FRAT E
0000101
RW
7
Reserved
0
R
6:5
BUCK2_DVS_EN_CTR L
11
RW
4:3
BUCK2_DVS_EN_TD
01
RW
2:1
BUCK2_OC_limit
01
RW
0
Reserved
0
R
7
BUCK2_GO_LP_OP
0
RWSC
BUCK2_SFC HG_R
BUCK2_SFC HG_F
BUCK2_DVS
0x26
MediaTek Confidential
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description BUCK2 OC flag occur condition 00: 4times 01: 8times 10: 16times 11: 32times BUCK2 OC status 0: No OC 1: OC occur BUCK2 OC shutdown enable: 0: OC occur don't turn off BUCK2, only interrupt 1: OC occur turn off BUCK2 and reset BUCK2_EN_CTRL1/2 except auto-writing BUCK2_SW_EN = 1'b0. BUCK2 TRA_DN sPWM Enable: 0: Disable sPWM 1: Enable sPWM BUCK2 soft change rising enable 0: Disable 1: Enable BUCK2 soft change rising rate Ref clock = 3MHz, 1 step (5mV) = (code+1) / 3M BUCK2 soft change falling enable 0: Disable 1: Enable BUCK2 soft change falling rate Ref clock = 3MHz, 1 step (5mV) = (code+1) / 3M Reserved BUCK2 DVS_EN Transition pulse enable: 00: Disable 01: Falling Enable 10: Rising Enable 11: Rising/Falling Enable BUCK2 DVS_EN transition pulse window: 00: 30µs 01: 45µs 10: 60µs 11: 750µs BUCK2 out load limit: 00: NA 01: 3A 10: 4A 11: 5A Reserved 0: Prefer LP; enter LP if one of
Page 149 of 210
MT6360 PMIC Datasheet Confidential A Address
Reg Name
Bit
Bit Name
Default
Type
6
Reserved
0
R
5
BUCK2_SRCLKEN_0_ OP_EN
0
RWSC
4:3
BUCK2_SRCLKEN_0_ OP_CFG
00
RWSC
2
BUCK2_SRCLKEN_2_ OP_EN
0
RWSC
1:0
BUCK2_SRCLKEN_2_ OP_CFG
00
RWSC
BUCK2_EN_ CTRL1
MediaTek Confidential
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description SRCLKEN_0/SRCLKEN_ 2/REG_EN is "LP" 1: Prefer no LP; leave LP if one of SRECLKEN_0/SRCLKEN _2/REG_EN is "NO LP" Reserved 0: Deprive the control power of SRCLKEN_0 pin for BUCK2 1: Allow SRCLKEN_0 pin to control BUCK2 Select the use of SRCLKEN_0 pin when BUCK2_SRCLKEN_0_O P_EN = 1'b1 00: SRCLKEN_0 pin can elect BUCK2 ON /OFF When SRCLKEN_0 pin is logic low, elect BUCK2 OFF When SRCLKEN_0 pin is logic high, elect BUCK2 ON 01: NA 10: SRCLKEN_0 pin can elect BUCK2 LP mode ON/OFF When SRCLKEN_0 pin is logic low, elect BUCK2 LP mode ON When SRCLKEN_0 pin is logic high, elect BUCK2 LP mode OFF 11: NA 0: Deprive the control power of SRCLKEN_2for BUCK2 1: Allow SRCLKEN_2 to control BUCK2 Select the use of SRCLKEN_2 when BUCK2_SRCLKEN_2_O P_EN = 1'b1 00: SRCLKEN_2 can elect BUCK2 ON /OFF When SRCLKEN_2 is logic low, elect BUCK2 OFF When SRCLKEN_2 is logic high, elect BUCK2 ON 01: NA 10: SRCLKEN_2 can elect BUCK2 LP Mode ON/OFF When SRCLKEN_2 is logic low, elect BUCK2 LP mode ON When SRCLKEN_2 is logic high, elect BUCK2 LP Mode OFF
Page 150 of 210
MT6360 PMIC Datasheet Confidential A Address
0x27
0x28
Reg Name
Bit
Bit Name
Default
Type
7
BUCK2_SW_OP_EN
1
RWSC
6
BUCK2_SW_EN
0
RWSC
5
BUCK2_SW_LP
0
RWSC
4
Reserved
0
R
3
BUCK2_GO_ON_OP
0
RWSC
2
BUCK2_EN
0
R
1:0
BUCK2_MODE
00
R
7:6
Reserved
00
R
5:4
BUCK2_STCD_TD
00
RW
3
BUCK2_STCD
0
R
BUCK2_EN_ CTRL2
BUCK2_CTR L1
MediaTek Confidential
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description 11: NA 0: Deprive the control power of BUCK2_SW_EN/LP 1: Allow BUCK2_SW_EN/LP working This bit is useless when BUCK2_SW_OP_EN = 1'b0 0: Elect BUCK2 OFF 1: Elect BUCK2 ON Note1: If BUCK2 is in sequence, the default value = 1'b1 Note2: When BUCK2 power is not good or OC happens and only turns off itself, reset BUCK2_EN_CTRLx except auto-writing this bit = 1'b0. And EN pin = 0->1 will reload this bit to the default value This bit is useless when BUCK2_SW_OP_EN = 1'b0 0: Elect BUCK2 LP mode OFF 1: Elect BUCK2 LP mode ON Reserved 0: Prefer ON; turn ON if one of SRCLKEN_0/SRCLKEN_ 2/REG_EN is "ON" 1: Prefer OFF; turn OFF if one of SRECLKEN_0/SRCLKEN _2/REG_EN is "OFF" Indicate the result of enable election 0: BUCK2 is ON 1: BUCK2 is OFF Indicate the operation mode of BUCK2 00: Normal mode 01: NA 10: LP mode 11: NA Reserved BUCK2 FAULT extended block time after soft-start count down 00: 1ms 01: 2ms 10: 4ms 11: 8ms It indicates BUCK2 softstart count down or not
Page 151 of 210
MT6360 PMIC Datasheet Confidential A Address
0x29
0x30
RWSC
Reg Name
BUCK2_CTR L2
LDO7_EN_C TRL1 (VDRAM2)
_EN = 1'b1
MediaTek Confidential
Bit
Bit Name
Default
Type
2
BUCK2_PG
0
R
1:0
BUCK2_PGB_PTSEL
10
RW
7:6
Reserved
01
R
5:4
BUCK2_SS_SR
11
RW
3:0
Reserved
0000
R
7
LDO7_GO_LP_OP
0
RWSC
6
Reserved
0
R
5
LDO7_SRCLKEN_0_O P_EN
0
RWSC
P_CFG
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description 0: Off or soft-start not count down 1: Soft-start count down It indicates BUCK2 power good or not 0: Power not good or off 1: Power good (BUCK2_STCD = 1 and sPG_BUCK2 = 1) The reaction when BUCK2 OC or power not good happens 00: Only interrupt, and won't disable any channel 01: Only shutdown BUCK2 and reset BUCK2_EN_CTRL1/2 then set BUCK2_EN = 1'b0 10: Shutdown all Bucks and LDOs, reset CHx_EN_CTRL1/2 and after the blocking time: TB_REBOOT , then confirm EN pin 11: Equal to 2'b10 Note: If BUCK2 isn't in sequence, the default value is 2'b01 Reserved The speed of SOFT START DVS 00 = 10mV step/µs 01 = 5mV step/µs 10 = 2.5mV step/µs 11 = 1.25mV step/µs Reserved 0: Prefer LP; enter LP if one of SRCLKEN_0/SRCLKEN_ 2/REG_EN is "LP" 1: Prefer no LP; leave LP if one of SRECLKEN_0/SRCLKEN _2/REG_EN is "NO LP" Reserved 0: Deprive the control power of SRCLKEN_0 pin for LDO7 1: Allow SRCLKEN_0 pin to control LDO7 Select the use of SRCLKEN_0 pin when LDO7_SRCLKEN_0_OP 00: SRCLKEN_0 pin can elect LDO7 ON /OFF When SRCLKEN_0 pin is logic low, elect LDO7 OFF
Page 152 of 210
MT6360 PMIC Datasheet Confidential A Address
0x31
Reg Name
Bit
Bit Name
Default
Type
2
LDO7_SRCLKEN_2_OP _EN
0
RWSC
1:0
LDO7_SRCLKEN_2_OP _CFG
00
RWSC
7
LDO7_SW_OP_EN
1
RWSC
6
LDO7_SW_EN
0
RWSC
5
LDO7_SW_LP
0
RWSC
4
Reserved
0
R
3
LDO7_GO_ON_OP
0
RWSC
LDO7_EN_C TRL2 (VDRAM2)
MediaTek Confidential
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description When SRCLKEN_0 pin is logic high, elect LDO7 ON 01: NA 10: SRCLKEN_0 pin can elect LDO7 LP mode ON/OFF When SRCLKEN_0 pin is logic low, elect LDO7 LP mode ON When SRCLKEN_0 pin is logic high, elect LDO7 LP mode OFF 11: Reserved 0: Deprive the control power of SRCLKEN_2 for LDO7 1: Allow SRCLKEN_2 to control LDO7 Select the use of SRCLKEN_2 when LDO7_SRCLKEN_2_OP_ EN = 1'b1 00: SRCLKEN_2 can elect LDO7 ON /OFF When SRCLKEN_2 is logic low, elect LDO7 OFF When SRCLKEN_2 is logic high, elect LDO7 ON 01: NA 10: SRCLKEN_2 can elect LDO7 LP mode ON/OFF When SRCLKEN_2 is logic low, elect LDO7 LP mode ON When SRCLKEN_2 is logic high, elect LDO7 LP mode OFF 11: Reserved 0: Deprive the control power of LDO7_SW_EN/LP 1: Allow LDO7_SW_EN/LP working This bit is useless when LDO7_SW_OP_EN = 1'b0 0: Elect LDO7 OFF 1: Elect LDO7 ON This bit is useless when LDO7_SW_OP_EN = 1'b0 0: Elect LDO7 LP Mode OFF 1: Elect LDO7 LP Mode ON Reserved 0: Prefer ON; turn ON if one of SRCLKEN_0/SRCLKEN_ 2/REG_EN is "ON"
Page 153 of 210
MT6360 PMIC Datasheet Confidential A Address
0x32
0x33
Reg Name
LDO7_CTRL0 (VDRAM2)
LDO7_CTRL1 (VDRAM2)
MediaTek Confidential
Bit
Bit Name
Default
Type
2
LDO7_EN
0
R
1:0
LDO7_MODE
00
R
7:6
Reserved
00
R
5:4
LDO7_STCD_TD
00
RW
3
LDO7_STCD
0
R
2
LDO7_PG
0
R
1:0
LDO7_PGB_PTSEL
10
RW
7
LDO7_LP_CLAMP_EN
1
RW
6
LDO7_OC_EN
1
RW
5
LDO7_LPOC_EN
0
RW
4
Reserved
00
R
3
LDO7_OCFB_EN
1
RWSC
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description 1: Prefer OFF; turn OFF if one of SRECLKEN_0/SRCLKEN _2/REG_EN is "OFF" Indicate the result of enable election 0 : LDO7 is ON 1 : LDO7 is OFF Indicate the operation mode of LDO7 00: Normal mode 01: NA 10: LP mode 11: NA Reserved LDO7 FAULT extended block time after soft-start count down 00: 1ms 01: 2ms 10: 4ms 11: 8ms It indicates LDO7 softstart count down or not 0: Off or soft-start not count down 1: Soft-start count down It indicates LDO7 power good or not 0: Power not good or off 1: Power good The reaction when LDO7 power not good happens 00: Only interrupt, and won't disable any channel 01: Only shutdown LDO7 and reset LDO7_EN_CTRL1/2 then set LDO7_EN = 1'b0 10: Shutdown all BUCKs and LDOs, reset CHx_EN_CTRL1/2 and after the blocking time: TB_REBOOT, then confirm EN pin 11: Equal to 2'b10 0: Disable Clamp circuit at LP mode 1: Enable Clamp circuit at LP mode 0: Disable OC circuit 1: Enable OC circuit Low Power Mode OC enable control 0: Disable 1: Enable Reserved OCFB function enable control 0: Disable
Page 154 of 210
MT6360 PMIC Datasheet Confidential A Address
0x34
0x35
0x36
Reg Name
LDO7_CTRL2 (VDRAM2)
Bit
Bit Name
Default
Type
2:1
LDO7_OCFB_TD
10
RW
0
LDO7_OC_PTSEL
0
RWSC
7:6
LDO7_STBTD
00
RW
5:4
Reserved
00
R
3
LDO7_DUMMY_LOAD _GATED_DIS
0
RW
2
LDO7_NDIS_EN
1
RW
1:0
LDO7_DUMMY_LOAD
00
RW
7:4
LDO7_VOSEL
0001
RW
3:0
LDO7_VOCAL
0000
RW
7
LDO6_GO_LP_OP
0
RWSC
LDO7_CTRL3 (VDRAM2)
LDO6_EN_ CTRL1 (VMDDR)
MediaTek Confidential
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description 1: Enable OCFB deglitch time selection: 00: 10µs 01: 15µs 10: 60µs 11: 100µs The reaction when LDO7 OC happens 0: Only interrupt, and won't disable LDO7 1: Automatically disable LDO7 after 5ms debouncing time and reset LDO7_EN_CTRL1/2 then set LDO7_EN = 1'b0 Soft-start OC deglitch time selection : 00: 1100µs 01: 3300µs 10: 6600µs 11: 9900µs Reserved The permission to make LDO7_DUMMY_LOAD = 2'b00, when LDO7 in LP mode. 0: LDO7_DUMMY_LOAD will be gated by LP mode. 1: LDO7_DUMMY_LOAD will be regardless with LP. 0: Disable output discharge 1: Enable output discharge 00: 0A dummy load 01: 100µA dummy load 10: 1mA dummy load 11: 1.1mA dummy load LDO7 VO coarse tune 0001: 0.6V … Note: VO7 = 0.5 + (0.1 x LDO7_VOSEL) + (0.01 x LDO7_VOCAL) LDO7 VO fine tune (+10mV/step) : 0000: +00 mV 0001: +10mV … 1010 to 1111: +100mV LDO7_VOCAL = 10mV x code 0: Prefer LP; enter LP if one of SRCLKEN_0/SRCLKEN_ 2/REG_EN is "LP" 1: Prefer no LP; leave LP if one of
Page 155 of 210
MT6360 PMIC Datasheet Confidential A Address
power of 0x37
Reg Name
LDO6_EN_C TRL2 (VMDDR)
MediaTek Confidential
Bit
Bit Name
Default
Type
6
Reserved
0
R
5
LDO6_SRCLKEN_0_O P_EN
0
RWSC
4:3
LDO6_SRCLKEN_0_O P_CFG
00
RWSC
2
LDO6_SRCLKEN_2_O P_EN
0
RWSC
1:0
LDO6_SRCLKEN_2_O P_CFG
00
RWSC
7
LDO6_SW_OP_EN
1
RWSC
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description SRECLKEN_0/SRCLKEN _2/REG_EN is "NO LP" Reserved 0: Deprive the control power of SRCLKEN_0 pin for LDO6 1: Allow SRCLKEN_0 pin to control LDO6 Select the use of SRCLKEN_0 pin when LDO6_SRCLKEN_0_OP _EN = 1'b1 00: SRCLKEN_0 pin can elect LDO6 ON/OFF When SRCLKEN_0 pin is logic low, elect LDO6 OFF When SRCLKEN_0 pin is logic high, elect LDO6 ON 01: NA 10: SRCLKEN_0 pin can elect LDO6 LP mode ON/OFF When SRCLKEN_0 pin is logic low, elect LDO6 LP mode ON When SRCLKEN_0 pin is logic high, elect LDO6 LP mode OFF 11: Reserved 0: Deprive the control power of SRCLKEN_2for LDO6 1: Allow SRCLKEN_2 to control LDO6 Select the use of SRCLKEN_2 when LDO6_SRCLKEN_2_OP _EN = 1'b1 00: SRCLKEN_2 can elect LDO6 ON/OFF When SRCLKEN_2 is logic low, elect LDO6 OFF When SRCLKEN_2 is logic high, elect LDO6 ON 01: NA 10: SRCLKEN_2 can elect LDO6 LP Mode ON/OFF When SRCLKEN_2 is logic low, elect LDO6 LP mode ON When SRCLKEN_2 is logic high, elect LDO6 LP mode OFF 11: Reserved 0: Deprive the control LDO6_SW_EN/LP 1: Allow LDO6_SW_EN/LP working
Page 156 of 210
MT6360 PMIC Datasheet Confidential A Address
0x38
Reg Name
LDO6_CTRL0 (VMDDR)
MediaTek Confidential
Bit
Bit Name
Default
Type
6
LDO6_SW_EN
0
RWSC
5
LDO6_SW_LP
0
RWSC
4
Reserved
0
R
3
LDO6_GO_ON_OP
0
RWSC
2
LDO6_EN
0
R
1:0
LDO6_MODE
00
R
7:6
Reserved
00
R
5:4
LDO6_STCD_TD
00
RW
3
LDO6_STCD
0
R
2
LDO6_PG
0
R
1:0
LDO6_PGB_PTSEL
10
RW
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description This bit is useless when LDO6_SW_OP_EN = 1'b0 0: Elect LDO6 OFF 1: Elect LDO6 ON This bit is useless when LDO6_SW_OP_EN = 1'b0 0: Elect LDO6 LP mode OFF 1: Elect LDO6 LP mode ON Reserved 0: Prefer ON; turn ON if one of SRCLKEN_0/SRCLKEN_ 2/REG_EN is "ON" 1: Prefer OFF; turn OFF if one of SRECLKEN_0/SRCLKEN _2/REG_EN is "OFF" Indicate the result of enable election 0: LDO6 is ON 1: LDO6 is OFF Indicate the operation mode of LDO6 00: Normal mode 01: NA 10: LP mode 11: NA Reserved LDO6 FAULT extended block time after soft-start count down 00: 1ms 01: 2ms 10: 4ms 11: 8ms It indicates LDO6 softstart count down or not 0:Off or soft-start not count down 1: Soft-start count down It indicates LDO6 power good or not 0: Power not good or off 1: Power good The reaction when LDO6 power not good happens 00: Only interrupt, and won't disable any channel 01: Only shutdown LDO7 and reset LDO6_EN_CTRL1/2 then set LDO6_EN = 1'b0 10: Shutdown all BUCKs and LDOs, reset CHx_EN_CTRL1/2 and after the blocking time:
Page 157 of 210
MT6360 PMIC Datasheet Confidential A Address
0x39
0x3A
Reg Name
Bit Name
Default
Type
7
LDO6_LP_CLAMP_EN
1
RW
6
LDO6_OC_EN
1
RW
5
LDO6_LPOC_EN
0
RW
4
Reserved
00
R
3
LDO6_OCFB_EN
1
RWSC
2:1
LDO6_OCFB_TD
10
RW
0
LDO6_OC_PTSEL
0
RWSC
7:6
LDO6_STBTD
01
RW
5:4
Reserved
00
R
3
LDO6_DUMMY_LOAD _GATED_DIS
0
RW
2
LDO6_NDIS_EN
1
RW
1:0
LDO6_DUMMY_LOAD
00
RW
7:4
LDO6_VOSEL
0010
RW
LDO6_CTRL1 (VMDDR)
LDO6_CTRL2 ( VMDDR )
01: 100µA dummy load
0x3B
Bit
LDO6_CTRL3 ( VMDDR )
MediaTek Confidential
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description TB_REBOOT, then confirm EN pin 11: Equal to 2'b10 1: Enable Clamp circuit at LP mode 0: Disable Clamp circuit at LP mode 1: Enable OC circuit 0: Disable OC circuit Low Power Mode OC enable control 0: Disable 1: Enable Reserved OCFB function enable control 0: Disable 1: Enable OCFB deglitch time selection: 00: 10µs 01: 15µs 10: 60µs 11: 100µs The reaction when LDO6 OC happens 0: Only interrupt, and won't disable LDO6 1: Automatically disable LDO6 after 5ms debouncing time and reset LDO6_EN_CTRL1/2 then set LDO6_EN = 1'b0 Soft-start OC deglitch time selection: 00: 1000µs 01: 2000µs 10: 4000µs 11: 8000µs Reserved The permission to makeLDO6_DUMMY_LO AD =2'b00, when LDO6 is in LP mode. 0: LDO6_DUMMY_LOAD will be gated by LP mode. 1: LDO6_DUMMY_LOAD will be regardless with LP mode. 0: Disable output discharge 1: Enable output discharge 00: 0A dummy load 10: 1mA dummy load 11: 1.1mA dummy load LDO6 VO coarse tune 0010: 0.7V …
Page 158 of 210
MT6360 PMIC Datasheet Confidential A Address
Reg Name
MediaTek Confidential
Bit
Bit Name
Default
Type
3:0
LDO6_VOCAL
0101
RW
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description Note: VO6 = 0.5 + (0.1 x LDO6_VOSEL) + (0.01 x LDO6_VOCAL) LDO6 VO fine tune (+10mV/step) : 0000: +00mV 1010 to 1111: +100Mv LDO6_VOCAL = 10mV x code
Page 159 of 210
MT6360 PMIC Datasheet Confidential A Table 5-7. LDO Part Register Detail Description Address
Reg Name
Bit
0x00
RST_LDO_P AS_CODE1
7:0
RST_LDO_PAS_CODE1 00000000
RW
0x01
RST_LDO_P AS_CODE2
7:0
RST_LDO_PAS_CODE2 00000000
RW
0x02
Bit Name
Default
Type
7
ALL_LDO_RST
0
WC
6
Reserved
0
R
5
LDO5_RST
0
WC
4
Reserved
0
R
3
LDO3_RST
0
WC
2
LDO2_RST
0
WC
RST_LDO
LDO2 registers and logic
MediaTek Confidential
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description RST_LDO_PAS_CODE1[ 7:0]/Passcode 1 for RST: set REG_LDO0x00 = 8'hA9 then set REG_LDO0x01 = 8'h96 , can start up REG_LDO0x02: ***_RST. To erase RST_LDO_PAS_CODE, REG_PMU0x02 won't work. RST_LDO_PAS_CODE2[ 7:0] /Passcode 2 for RST: set REG_LDO0x00 = 8'hA9 then set REG_LDO0x01 = 8'h96 , can start up REG0x02 ***_RST. To erase RST_LDO_PAS_CODE, REG0x02 won't work. All LDO relative registers and logic reset bit. 0: Don't reset all registers and logic 1: Reset all registers and logic. (Notice: This bit will be reset to "0" after reset procedure finish) Reserved LDO5 registers and logic reset bit. 0: Don't reset LDO5 relative registers and logic. 1: Reset LDO5 relative registers and logic. (Notice: This bit will be reset to "0" after reset procedure finish) Reserved LDO3 registers and logic reset bit. 0: Don't reset LDO3 relative registers and logic. 1: Reset LDO3 relative registers and logic. (Notice: This bit will be reset to "0" after reset procedure finish) reset bit. 0: Don't reset LDO2 relative registers and logic.
Page 160 of 210
MT6360 PMIC Datasheet Confidential A Address
0x04
Reg Name
Bit
Bit Name
Default
Type
1
LDO1_RST
0
WC
0
REG_LDO_RST
0
WC
7
LDO3_GO_LP_OP
0
RWSC
6
Reserved
0
R
5
LDO3_SRCLKEN_0_O P_EN
0
RWSC
4:3
LDO3_SRCLKEN_0_O P_CFG
00
RWSC
LDO3_EN_ CTRL1 (VMC)
mode ON
MediaTek Confidential
Description 1: Reset LDO2 relative registers and logic. (Notice: This bit will be reset to "0" after reset procedure finish) LDO1 registers and logic reset bit. 0: Don't reset LDO1 relative registers and logic. 1: Reset LDO1 relative registers and logic. (Notice: This bit will be reset to "0" after reset procedure finish) REG_LDO registers reset bits 0: Don't reset REG_PMU registers. 1: Reset Specified REG_LDO registers according to RST table. (Notice: This bit will be reset to "0" after reset procedure finish) 0: Prefer LP; enter LP if one of SRCLKEN_0/SRCLKEN_ 2/REG_EN is "LP" 1: Prefer no LP; leave LP if one of SRECLKEN_0/SRCLKEN _2/REG_EN is "NO LP" Reserved 0: Deprive the control power of SRCLKEN_0 pin for LDO3 1: Allow SRCLKEN_0 pin to control LDO3 Select the use of SRCLKEN_0 pin when LDO3_SRCLKEN_0_OP _EN = 1'b1 00: SRCLKEN_0 pin can elect LDO3 ON/OFF When SRCLKEN_0 pin is logic low, elect LDO3 OFF When SRCLKEN_0 pin is logic high, elect LDO3 ON 01: NA 10: SRCLKEN_0 pin can elect LDO3 LP mode ON/OFF When SRCLKEN_0 pin is logic low, elect LDO3 LP When SRCLKEN_0 pin is logic high, elect LDO3 LP mode OFF 11: Reserved
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Page 161 of 210
MT6360 PMIC Datasheet Confidential A Address
0x05
Reg Name
LDO3_EN_ CTRL2 (VMC)
MediaTek Confidential
Bit
Bit Name
Default
Type
2
LDO3_SRCLKEN_2_OP _EN
0
RWSC
1:0
LDO3_SRCLKEN_2_OP _CFG
00
RWSC
7
LDO3_SW_OP_EN
1
RWSC
6
LDO3_SW_EN
0
RWSC
5
LDO3_SW_LP
0
RWSC
4
Reserved
0
R
3
LDO3_GO_ON_OP
0
RWSC
2
LDO3_EN
0
R
1:0
LDO3_MODE
00
R
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description 0: Deprive the control power of SRCLKEN_2 for LDO3 1: Allow SRCLKEN_2 to control LDO3 Select the use of SRCLKEN_2 when LDO3_SRCLKEN_2_OP_ EN = 1'b1 00: SRCLKEN_2 can elect LDO3 ON /OFF When SRCLKEN_2 is logic low, elect LDO3 OFF When SRCLKEN_2 is logic high, elect LDO3 ON 01: NA 10: SRCLKEN_2 can elect LDO3 LP Mode ON/OFF When SRCLKEN_2 is logic low, elect LDO3 LP mode ON When SRCLKEN_2 is logic high, elect LDO3 LP mode OFF 11: Reserved 0: Deprive the control power of LDO3_SW_EN/LP 1: Allow LDO3_SW_EN/LP working This bit is useless when LDO3_SW_OP_EN = 1'b0 0: Elect LDO3 OFF 1: Elect LDO3 ON This bit is useless when LDO3_SW_OP_EN = 1'b0 0: Elect LDO3 LP mode OFF 1: Elect LDO3 LP mode ON Reserved 0: Prefer ON; turn ON if one of SRCLKEN_0/SRCLKEN_ 2/REG_EN is "ON" 1: Prefer OFF; turn OFF if one of SRECLKEN_0/SRCLKEN _2/REG_EN is "OFF" Indicate the result of enable election 0: LDO3 is OFF 1: LDO3 is ON Indicate the operation mode of LDO3 00: Normal mode 01: NA 10: LP mode
Page 162 of 210
MT6360 PMIC Datasheet Confidential A Address
0x06
0x07
Reg Name
LDO3_CTRL0 (VMC)
Bit
Bit Name
Default
Type
7:6
Reserved
00
R
5:4
LDO3_STCD_TD
00
RW
3
LDO3_STCD
0
R
2
LDO3_PG
0
R
1:0
LDO3_PGB_PTSEL
01
RW
7
Reserved
0
R
6
LDO3_SS_ISEL
1
RW
5
LDO3_LPOC_EN
0
RW
4
Reserved
0
R
3
LDO3_OCFB_EN
1
RW
2:1
LDO3_OCFB_TD
10
RW
0
LDO3_OC_PTSEL
0
RW
LDO3_CTRL1 (VMC)
MediaTek Confidential
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description 11: NA Reserved LDO3 FAULT extended block time after soft-start count down 00: 1ms 01: 2ms 10: 4ms 11: 8ms It indicates LDO3 softstart count down or not 0: Off or soft-start not count down 1: Soft-start count down It indicates LDO3 power good or not 0: Power not good or off 1: Power good The reaction when LDO3 power not good happens 00: Only interrupt, and won't disable any channel 01: Only shutdown LDO3 and reset LDO3_EN_CTRL1/2 then set LDO3_EN = 1'b0 10: Shutdown all BUCKs and LDOs, reset CHx_EN_CTRL1/2 and after the blocking time: TB_REBOOT, then confirm EN pin 11: Equal to 2'b10 Reserved Soft-Start Current Selection 0: 25mA 1: 8mA 0: Disable 1: Enable Reserved OCFB function enable control 0: Disable 1: Enable OCFB deglitch time selection: 00: 10µs 01: 15µs 10: 60µs 11: 100µs The reaction when LDO3 OC happens 0: Only interrupt, and won't disable LDO3 and reset LDO3_EN_CTRL1/2 then set LDO3_EN = 1'b0
Page 163 of 210
MT6360 PMIC Datasheet Confidential A Address
0x08
0x09
0x0A
Reg Name
Bit
Bit Name
Default
Type
7:6
LDO3_STBTD
10
RW
5
LDO3_STB_SRSEL
0
RW
4
Reserved
0
R
3
LDO3_DUMMY_LOAD _GATED_DIS
0
RW
2
LDO3_NDIS_EN
1
RW
1:0
LDO3_DUMMY_LOAD
00
RW
7:4
LDO3_VOSEL
1011
RW
3:0
LDO3_VOCAL
0000
RW
7
LDO5_GO_LP_OP
0
RWSC
LDO3_CTRL2 (VMC)
LDO3_CTRL3 (VMC)
LDO5_EN_ CTRL1 (VMCH)
MediaTek Confidential
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description 1: Automatically disable LDO3 after 5ms debouncing time Soft-start OC deglitch time selection : 00: 40µs 01: 120µs 10: 1000µs 11: 3000µs Soft-start slew rate selection 0: Fast 1: Slow Reserved The permission to make LDO3_DUMMY_LOAD = 2'b00, when LDO3 in LP mode. 0: LDO3_DUMMY_LOAD will be gated by LP mode. 1: LDO3_DUMMY_LOAD will be regardless with LP mode. 0: Disable output discharge 1: Enable output discharge 00: 0A dummy load 01: 100µA dummy load 10: 1mA dummy load 11: 1.1mA dummy load LDO3 VO coarse tune: 0000: reserved … 0011: reserved 0100: 1.8V 0101: reserved … 1001: reserved 1010: 2.9V 1011: 3.0V 1100: reserved 1101: 3.3V 1110: reserved 1111: reserved LDO5 VO fine tune (+10mV/step) : 0000: +00mV 0101 :+50mV 1010 to 1111: +100mV LDO3_VOCAL = 10mV x code 0: Prefer LP; enter LP if one of SRCLKEN_0/SRCLKEN_ 2/REG_EN is "LP" 1: Prefer no LP; leave LP if one of SRECLKEN_0/SRCLKEN _2/REG_EN is "NO LP"
Page 164 of 210
MT6360 PMIC Datasheet Confidential A Address
1: Allow 0x0B
Reg Name
Bit 6
Bit Name Reserved
Default 0
Type R
5
LDO5_SRCLKEN_0_O P_EN
0
RWSC
4:3
LDO5_SRCLKEN_0_O P_CFG
00
RWSC
2
LDO5_SRCLKEN_2_OP _EN
0
RWSC
1:0
LDO5_SRCLKEN_2_OP _CFG
00
RWSC
7
LDO5_SW_OP_EN
1
RWSC
CTRL2 (VMCH) 6
MediaTek Confidential
LDO5_SW_EN
0
RWSC
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description Reserved 0: Deprive the control power of SRCLKEN_0 pin for LDO5 1: Allow SRCLKEN_0 pin to control LDO5 Select the use of SRCLKEN_0 pin when LDO5_SRCLKEN_0_OP _EN = 1'b1 00: SRCLKEN_0 pin can elect LDO5 ON /OFF When SRCLKEN_0 pin is logic low, elect LDO5 OFF When SRCLKEN_0 pin is logic high, elect LDO5 ON 01: NA 10: SRCLKEN_0 pin can elect LDO5 LP mode ON/OFF When SRCLKEN_0 pin is logic low, elect LDO5 LP mode ON When SRCLKEN_0 pin is logic high, elect LDO5 LP mode OFF 11: Reserved 0: Deprive the control power of SRCLKEN_2 for LDO5 1: Allow SRCLKEN_2 to control LDO5 Select the use of SRCLKEN_2 when LDO5_SRCLKEN_2_OP_ EN = 1'b1 00: SRCLKEN_2 can elect LDO5 ON /OFF When SRCLKEN_2 is logic low, elect LDO5 OFF When SRCLKEN_2 is logic high, elect LDO5 ON 01: NA 10: SRCLKEN_2 can elect LDO5 LP Mode ON/OFF When SRCLKEN_2 is logic low, elect LDO5 LP mode ON When SRCLKEN_2 is logic high, elect LDO5 LP mode OFF 11: Reserved 0: Deprive the control power of LDO5_SW_EN/LP LDO5_SW_EN/LP working This bit is useless when LDO5_SW_OP_EN = 1'b0
Page 165 of 210
MT6360 PMIC Datasheet Confidential A Address
0x0C
Reg Name
Bit
Bit Name
Default
Type
5
LDO5_SW_LP
0
RWSC
4
Reserved
0
R
3
LDO5_GO_ON_OP
0
RWSC
2
LDO5_EN
0
R
1:0
LDO5_MODE
00
R
7
SDCARD_HLACT
1
RW
6
SDCARD_DET_EN
0
RW
5:4
LDO5_STCD_TD
00
RW
3
LDO5_STCD
0
R
2
LDO5_PG
0
R
1:0
LDO5_PGB_PTSEL
01
RW
LDO5_CTRL0 (VMCH)
MediaTek Confidential
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description 0: Elect LDO5 OFF 1: Elect LDO5 ON This bit is useless when LDO5_SW_OP_EN = 1'b0 0: Elect LDO5 LP Mode OFF 1: Elect LDO5 LP Mode ON Reserved 0: Prefer ON; turn ON if one of SRCLKEN_0/SRCLKEN_ 2/REG_EN is "ON" 1: Prefer OFF; turn OFF if one of SRECLKEN_0/SRCLKEN _2/REG_EN is "OFF" Indicate the result of enable election 0: LDO5 is ON 1: LDO5 is OFF Indicate the operation mode of LDO5 00: Normal mode 01: NA 10: LP mode 11: NA The active level selection for SDCARD_DET_N pin 0: Low level 1: High level SDCARD_DET function enable control 0: Disable, SDCARD_DET_N pin is useless 1: Enable LDO5 FAULT extended block time after soft-start count down 00: 1ms 01: 2ms 10: 4ms 11: 8ms It indicates LDO5 softstart count down or not 0: Off or soft-start not count down 1: Soft-start count down It indicates LDO5 power good or not 0: Power not good or off 1: Power good The reaction when LDO5 power not good happens 00: Only interrupt, and won't disable any channel 01: Only shutdown LDO5 and reset
Page 166 of 210
MT6360 PMIC Datasheet Confidential A Address
0x0D
0x0E
RWSC
Reg Name
LDO5_CTRL1 (VMCH)
Bit
Bit Name
Default
Type
7:6
Reserved
00
R
5
LDO5_LPOC_EN
1
RW
4
Reserved
0
R
3
LDO5_OCFB_EN
1
RW
2:1
LDO5_OCFB_TD
10
RW
0
LDO5_OC_PTSEL
0
RW
7:6
LDO5_STBTD
10
RW
5
LDO5_STB_SRSEL
0
RW
4
Reserved
0
R
3
LDO5_DUMMY_LOAD _GATED_DIS
0
RW
LDO5_CTRL2 (VMCH)
discharge
1:0
MediaTek Confidential
LDO5_DUMMY_LOAD
00
RW
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description LDO5_EN_CTRL1/2 then set LDO5_EN = 1'b0 10: Shutdown all BUCKs and LDOs, reset CHx_EN_CTRL1/2 and after the blocking time: TB_REBOOT, then confirm EN pin 11: Equal to 2'b10 Reserved 0: Disable 1: Enable Reserved OCFB function enable control 0: Disable 1: Enable OCFB deglitch time selection: 00: 10µs 01: 15µs 10: 60µs 11: 100µs The reaction when LDO5 OC happens 0: Only interrupt, and won't disable LDO5 1: Automatically disable LDO5 after 5ms debouncing time and reset LDO5_EN_CTRL1/2 then set LDO5_EN = 1'b0 Soft-start OC deglitch time selection : 00: 40µs 01: 120µs 10: 1000µs 11: 3000µs Soft-start slew rate selection 0: Fast 1: Slow Reserved The permission to make LDO5_DUMMY_LOAD = 2'b00, when LDO5 in LP mode. 0: LDO5_DUMMY_LOAD will be gated by LP mode. 1: LDO5_DUMMY_LOAD will be regardless with LP mode. 0: Disable output 1: Enable output discharge 00: 0A dummy load 01: 100µA dummy load 10: 1mA dummy load 11: 1.1mA dummy load
Page 167 of 210
MT6360 PMIC Datasheet Confidential A Address
0x0F
0x10
Reg Name
Bit 7
Bit Name Reserved
Default 0
Type R
6:4
LDO5_VOSEL
010
RW
3:0
LDO5_VOCAL
0101
RW
7
LDO2_GO_LP_OP
0
RWSC
6
Reserved
0
R
5
LDO2_SRCLKEN_0_O P_EN
0
RWSC
4:3
LDO2_SRCLKEN_0_O P_CFG
00
RWSC
0
RWSC
LDO5_CTRL3 (VMCH)
LDO2_EN_ CTRL1 (VTP)
1: Allow SRCLKEN_2 to
2
1:0
MediaTek Confidential
LDO2_SRCLKEN_2_O
LDO2_SRCLKEN_2_O P_CFG
00
RWSC
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description Reserved LDO5 VO coarse tune: 000: reserved 001: reserved 010: 2.9V 011: 3.0V 100: reserved 101: 3.3V 110: reserved 111: reserved LDO5 VO fine tune (+10mV/step) : 0000: +00mV 0101: +50mV 1010 to 1111: +100mV LDO5_VOCAL = 10mV x code 0: Prefer LP; enter LP if one of SRCLKEN_0/SRCLKEN_ 2/REG_EN is "LP" 1: Prefer no LP; leave LP if one of SRECLKEN_0/SRCLKEN _2/REG_EN is "NO LP" Reserved 0: Deprive the control power of SRCLKEN_0 pin for LDO2 1: Allow SRCLKEN_0 pin to control LDO2 Select the use of SRCLKEN_0 pin when LDO2_SRCLKEN_0_OP _EN = 1'b1 00: SRCLKEN_0 pin can elect LDO2 ON /OFF When SRCLKEN_0 pin is logic low, elect LDO2 OFF When SRCLKEN_0 pin is logic high, elect LDO2 ON 01 : NA 10 : SRCLKEN_0 pin can elect LDO2 LP mode ON/OFF When SRCLKEN_0 pin is logic low, elect LDO2 LP mode ON When SRCLKEN_0 pin is logic high, elect LDO2 LP mode OFF 11: Reserved 0: Deprive the control power of SRCLKEN_2 for LDO2 control LDO2 Select the use of SRCLKEN_2 when LDO2_SRCLKEN_2_OP _EN = 1'b1
Page 168 of 210
MT6360 PMIC Datasheet Confidential A Address
0x11
count down 0x12
Reg Name
LDO2_EN_ CTRL2 (VTP)
(VTP)
MediaTek Confidential
Bit
Bit Name
Default
Type
7
LDO2_SW_OP_EN
1
RWSC
6
LDO2_SW_EN
0
RWSC
5
LDO2_SW_LP
0
RWSC
4
Reserved
0
R
3
LDO2_GO_ON_OP
0
RWSC
2
LDO2_EN
0
R
1:0
LDO2_MODE
0
R
7:6
Reserved
00
R
5:4
LDO2_STCD_TD
00
RW
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description 00: SRCLKEN_2 can elect LDO2 ON /OFF When SRCLKEN_2 is logic low, elect LDO2 OFF When SRCLKEN_2 is logic high, elect LDO2 ON 01: NA 10: SRCLKEN_2 can elect LDO2 LP Mode ON/OFF When SRCLKEN_2 is logic low, elect LDO2 LP mode ON When SRCLKEN_2 is logic high, elect LDO2 LP mode OFF 11: Reserved 0: Deprive the control power of LDO2_SW_EN/LP 1: Allow LDO2_SW_EN/LP working This bit is useless when LDO2_SW_OP_EN=1'b0 0: Elect LDO2 OFF 1: Elect LDO2 ON This bit is useless when LDO2_SW_OP_EN = 1'b0 0: Elect LDO2 LP mode OFF 1: Elect LDO2 LP mode ON Reserved 0: Prefer ON; turn ON if one of SRCLKEN_0/SRCLKEN_ 2/REG_EN is "ON" 1: Prefer OFF; turn OFF if one of SRECLKEN_0/SRCLKEN _2/REG_EN is "OFF" Indicate the result of enable election 0: LDO2 is ON 1: LDO2 is OFF Indicate the operation mode of LDO2 00: Normal mode 01: NA 10: LP mode 11: NA Reserved LDO2 FAULT extended block time after soft-start 00: 1ms 01: 2ms 10: 4ms 11: 8ms
Page 169 of 210
MT6360 PMIC Datasheet Confidential A Address
0x13
0x14
Reg Name
LDO2_CTRL1 (VTP)
Bit
Bit Name
Default
Type
3
LDO2_STCD
0
R
2
LDO2_PG
0
R
1:0
LDO2_PGB_PTSEL
01
RW
7:6
Reserved
00
R
5
LDO2_LPOC_EN
1
RW
4
Reserved
0
R
3
LDO2_OCFB_EN
1
RW
2:1
LDO2_OCFB_TD
10
RW
0
LDO2_OC_PTSEL
0
RW
7:6
LDO2_STBTD
01
RW
5
LDO2_STB_SRSEL
0
RW
4
Reserved LDO2_DUMMY_LOAD _GATED_DIS
0
R
0
RW
LDO2_CTRL2 (VTP)
3
MediaTek Confidential
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description It indicates LDO2 softstart count down or not 0: Off or soft-start not count down 1: Soft-start count down It indicates LDO2 power good or not 0: Power not good or off 1: Power good The reaction when LDO2 power not good happens 00: Only interrupt, and won't disable any channel 01: Only shutdown LDO2 and reset LDO2_EN_CTRL1/2 then set LDO2_EN = 1'b0 10: Shutdown all BUCKs and LDOs, reset CHx_EN_CTRL1/2 and after the blocking time: TB_REBOOT, then confirm EN pin 11: Equal to 2'b10 Reserved 0: Disable 1: Enable Reserved OCFB function enable control 0: Disable 1: Enable OCFB deglitch time selection: 00: 10µs 01: 15µs 10: 60µs 11: 100µs The reaction when LDO2 OC happens 0: Only interrupt, and won't disable LDO2 1: Automatically disable LDO2 after 5ms debouncing time and reset LDO2_EN_CTRL1/2 then set LDO2_EN = 1'b0 Soft-start OC deglitch time selection : 00: 500µs 01: 1000µs 10: 2500µs 11: 5000µs Soft-start slew rate selection 0: Fast 1: Slow Reserved The permission to make LDO2_DUMMY_LOAD =
Page 170 of 210
MT6360 PMIC Datasheet Confidential A Address
0x15
0x16
Reg Name
Bit
Bit Name
Default
Type
2
LDO2_NDIS_EN
1
RW
1:0
LDO2_DUMMY_LOAD
00
RW
7:4
LDO2_VOSEL
0100
RW
3:0
LDO2_VOCAL
0000
RW
7
LDO1_GO_LP_OP
0
RWSC
6
Reserved
0
R
5
LDO1_SRCLKEN_0_OP _EN
0
RWSC
4:3
LDO1_SRCLKEN_0_OP _CFG
00
RWSC
LDO2_CTRL3 (VTP)
LDO1_EN_ CTRL1 (VFP)
MediaTek Confidential
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description 2'b00, when LDO2 is in LP mode. 0: LDO2_DUMMY_LOAD will be gated by LP mode. 1: LDO2_DUMMY_LOAD will be regardless with LP mode. 0: Disable output discharge 1: Enable output discharge 00: 0A dummy load 01: 100µA dummy load 10: 1mA dummy load 11: 1.1mA dummy load LDO2 VO coarse tune: 0000: reserved … 0011: reserved 0100: 1.8V 0101: 2.0V 0110: 2.1V 0111: 2.5V 1000: 2.7V 1001: 2.8V 1010: 2.9V 1011: 3.0V 1100: 3.1V 1101: 3.3V 1110: reserved 1111: reserved LDO2 VO fine tune (+10mV/step) : 0000: +00mV 1010 to 1111: +100mV LDO2_VOCAL = 10mV x code 0: Prefer LP; enter LP if one of SRCLKEN_0/SRCLKEN_ 2/REG_EN is "LP" 1: Prefer no LP; leave LP if one of SRECLKEN_0/SRCLKEN _2/REG_EN is "NO LP" Reserved 0: Deprive the control power of SRCLKEN_0 pin for LDO1 1: Allow SRCLKEN_0 pin to control LDO1 Select the use of SRCLKEN_0 pin when LDO1_SRCLKEN_0_OP_ EN = 1'b1 00: SRCLKEN_0 pin can elect LDO1 ON /OFF When SRCLKEN_0 pin is logic low, elect LDO1 OFF When SRCLKEN_0 pin is logic high, elect LDO1 ON
Page 171 of 210
MT6360 PMIC Datasheet Confidential A Address
0x17
Reg Name
LDO1_EN_ CTRL2 (VFP)
MediaTek Confidential
Bit
Bit Name
Default
Type
2
LDO1_SRCLKEN_2_OP _EN
0
RWSC
1:0
LDO1_SRCLKEN_2_OP _CFG
00
RWSC
7
LDO1_SW_OP_EN
1
RWSC
6
LDO1_SW_EN
0
RWSC
5
LDO1_SW_LP
0
RWSC
4
Reserved
0
R
3
LDO1_GO_ON_OP
0
RWSC
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description 01: NA 10: SRCLKEN_0 pin can elect LDO1 LP mode ON/OFF When SRCLKEN_0 pin is logic low, elect LDO1 LP mode ON When SRCLKEN_0 pin is logic high, elect LDO1 LP mode OFF 11: Reserved 0: Deprive the control power of SRCLKEN_2 for LDO1 1: Allow SRCLKEN_2 to control LDO1 Select the use of SRCLKEN_2 when LDO1_SRCLKEN_2_OP_ EN = 1'b1 00: SRCLKEN_2 can elect LDO1 ON /OFF When SRCLKEN_2 is logic low, elect LDO1 OFF When SRCLKEN_2 is logic high, elect LDO1 ON 01 : NA 10 : SRCLKEN_2 can elect LDO1 LP Mode ON/OFF When SRCLKEN_2 is logic low, elect LDO1 LP mode ON When SRCLKEN_2 is logic high, elect LDO1 LP mode OFF 11: Reserved 0: Deprive the control power of LDO1_SW_EN/LP 1: Allow LDO1_SW_EN/LP working This bit is useless when LDO1_SW_OP_EN = 1'b0 0: Elect LDO1 OFF 1: Elect LDO1 ON This bit is useless when LDO1_SW_OP_EN = 1'b0 0: Elect LDO1 LP mode OFF 1: Elect LDO1 LP mode ON Reserved 0: Prefer ON; turn ON if one of SRCLKEN_0/SRCLKEN_ 2/REG_EN is "ON" 1: Prefer OFF; turn OFF if one of SRECLKEN_0/SRCLKEN _2/REG_EN is "OFF"
Page 172 of 210
MT6360 PMIC Datasheet Confidential A Address
0x18
0x19
Reg Name
Bit
Bit Name
Default
Type
2
LDO1_EN
0
R
1:0
LDO1_MODE
00
R
7:6
Reserved
00
R
5:4
LDO1_STCD_TD
00
RW
3
LDO1_STCD
0
R
2
LDO1_PG
0
R
1:0
LDO1_PGB_PTSEL
01
RW
7:6
Reserved
00
R
5
LDO1_LPOC_EN
1
RW
4
Reserved
0
R
3
LDO1_OCFB_EN
1
RW
2:1
LDO1_OCFB_TD
10
RW
LDO1_CTRL0 (VFP)
LDO1_CTRL1 (VFP)
MediaTek Confidential
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description Indicate the result of enable election 0: LDO1 is ON 1: LDO1 is OFF Indicate the operation mode of LDO1 00: Normal mode 01: NA 10: LP mode 11: NA Reserved LDO1 FAULT extended block time after soft-start count down 00 : 1ms 01 : 2ms 10 : 4ms 11 : 8ms It indicates LDO1 softstart count down or not 0: Off or soft-start not count down 1: Soft-start count down It indicates LDO1 power good or not 0: Power not good or off 1: Power good The reaction when LDO1 power not good happens 00: Only interrupt, and won't disable any channel 01: Only shutdown LDO1 and reset LDO1_EN_CTRL1/2 then set LDO1_EN = 1'b0 10: Shutdown all BUCKs and LDOs, reset CHx_EN_CTRL1/2 and after the blocking time: TB_REBOOT, then confirm EN pin 11: Equal to 2'b10 Reserved 0: Disable 1: Enable Reserved OCFB function enable control 0: Disable 1: Enable OCFB deglitch time selection : 00: 10µs 01: 15µs 10: 60µs 11: 100µs
Page 173 of 210
MT6360 PMIC Datasheet Confidential A Address
0x1A
0x1B
Reg Name
Bit
Bit Name
Default
Type
0
LDO1_OC_PTSEL
0
RW
7:6
LDO1_STBTD
01
RW
5
LDO1_STB_SRSEL
0
RW
4
Reserved
0
R
3
LDO1_DUMMY_LOAD _GATED_DIS
0
RW
2
LDO1_NDIS_EN
1
RW
1:0
LDO1_DUMMY_LOAD
00
RW
7:4
LDO1_VOSEL
0100
RW
3:0
LDO1_VOCAL
0000
RW
LDO1_CTRL2 ( VFP )
LDO1_CTRL3 ( VFP )
MediaTek Confidential
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description The reaction when LDO1 OC happens 0: Only interrupt, and won't disable LDO1 1: Automatically disable LDO1 after 5ms debouncing time and reset LDO1_EN_CTRL1/2 then set LDO1_EN = 1'b0 Soft-start OC deglitch time selection : 00: 500µs 01: 1000µs 10: 2500µs 11: 5000µs Soft-start slew rate selection 0: Fast 1: Slow Reserved The permission to make LDO1_DUMMY_LOAD = 2'b00, when LDO1 is in LP mode. 0: LDO1_DUMMY_LOAD will be gated by LP mode. 1: LDO1_DUMMY_LOAD will be regardless with LP mode. 0: Disable output discharge 1: Enable output discharge 00: 0A dummy load 01: 100µA dummy load 10: 1mA dummy load 11: 1.1mA dummy load LDO1 VO coarse tune: 0000: reserved … 0011: reserved 0100: 1.8V 0101: 2.0V 0110: 2.1V 0111: 2.5V 1000: 2.7V 1001: 2.8V 1010: 2.9V 1011: 3.0V 1100: 3.1V 1101: 3.3V 1110: reserved 1111: reserved LDO1 VO fine tune (+10mV/step) : 0000: +00mV 1010 to 1111: +100mV LDO1_VOCAL = 10mV x code
Page 174 of 210
MT6360 PMIC Datasheet Confidential A Table 5-8. PD Part Register Detail Description Address 0x00
Reg Name VENDOR_ID
0x01 0x02
PRODUCT_I D
0x03 0x04
DEVICE_ID
0x05 0x06
USBTYPEC_R EV
0x07 0x08 0x09 0x0A
USBPD_REV _VER
PD_INTERFA CE_REV
0x0B
0x10
ALERT
MediaTek Confidential
Bit
Bit Name
Default
Type
7:0
VID[7:0]
CF
R
7:0
VID[15:8]
29
R
7:0
PID[7:0]
72
R
7:0
PID[15:8]
63
R
7:0
DID[7:0]
91
R
7:0
DID[15:8]
34
R
7:0
USBTYPEC_REV
12
R
7:0
Reserved
00
R
7:0
USBPD_VER
11
R
7:0
USBPD_REV
30
R
7:0
PDIF_VER
12
R
7:0
PDIF_REV
10
R
7
ALARM_VBUS_VOLTA GE_H
0
R
6
TX_SUCCESS
0
RW
5
TX_DISCARD
0
RW
4
TX_FAIL
0
RW
3
RX_HARD_RESET
0
RW
2
RX_SOP_MSG_STATU S
0
RW
1
POWER_STATUS
0
RW
0
CC_STATUS
0
RW
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description A unique 16-bit unsigned integer. Assigned by the USB-IF to the Vendor. A unique 16-bit unsigned integer. Assigned uniquely by the Vendor to identify the TCPC. A unique 16-bit unsigned integer. Assigned by the Vendor to identify the version of the TCPC. Version number assigned by USB-IF (Currently at Revision 1.1: 0001 0001) 0001 0000: Version 1.0 0001 0001: Version 1.1 Etc. 0010 0000: Revision 2.0 0011 0000: Revision 3.0 0001 0000: Version 1.0 0001 0001: Version 1.1 0001 0010: Version 1.2 Etc. 0001 0000: Revision 1.0 0: Cleared 1: A high-voltage alarm has occurred 0: Cleared 1: Reset or SOP* message transmission successful. 0: Cleared 1: Reset or SOP* message transmission not sent due to incoming receive message. 0: Cleared 1: SOP* message transmission not successful, no GoodCRC response received on SOP* message transmission. 0: Cleared 1: Received Hard Reset message 0: Cleared 1: Receive status register changed 0: Cleared 1: Port status changed 0: Cleared 1: CC status changed
Page 175 of 210
MT6360 PMIC Datasheet Confidential A Address
Reg Name
Bit
Bit Name
Default
Type
7
VENDOR_DEFINED_ ALERT
0
RW
Reserved EXTENDED_STATUS_ CHANGE
0
R
0
RW
4
Reserved
0
R
3
VBUS_SINK_DISCNT
0
R
2
RXBUF_OVFLOW
0
RW
1
FAULT
1
RW
0
ALARM_VBUS_VOLTA GE_L
0
R
7
M_ALARM_VBUS_VOL TAGE_H
1
RW
6
M_TX_SUCCESS
1
RW
5
M_TX_DISCARD
1
RW
4
M_TX_FAIL
1
RW
3
M_RX_HARD_RESET
1
RW
2
M_RX_SOP_MSG_STA TUS
1
RW
1
M_POWER_STATUS
1
RW
0
M_CC_STATUS
1
RW
0
RW
1
R
1
R
1
R
1
RW
6 5 0x11
0x12
ALERT
ALERT_MAS K
7 6 5 0x13
ALERT_MAS K
MediaTek Confidential
4 3
M_VENDOR_DEFINED _ALERT Reserved M_EXTENDED_STATU S_CHANGE Reserved M_VBUS_SINK_DISCN T
2
M_RXBUF_OVFLOW
1
RW
1
M_FAULT
1
RW
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description 0: Cleared 1: A vendor defined alert has been detected. Defined in the VENDOR_DEFINED registers. Refer to the vendor datasheet for details. This bit can be cleared, regardless of the current status of the alert source. Reserved 0: Cleared 1: Extended status changed Reserved 0: Cleared 1: A VBUS sink disconnect threshold crossing has been detected 0: TCPC Rx buffer is functioning properly. 1: TCPC Rx buffer has overflowed. 0: No Fault. 1: A Fault has occurred. Read the FAULT_STATUS register. 0: Cleared 1: A low-voltage alarm has occurred 0: Interrupt masked, 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked, 1: Interrupt unmasked Reserved 0: Interrupt masked, 1: Interrupt unmasked Reserved 0: Interrupt masked, 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked
Page 176 of 210
MT6360 PMIC Datasheet Confidential A Address
Reg Name
Bit
Bit Name M_ALARM_VBUS_VOL TAGE_L M_DBG_ACC_CONNE CT
Default
Type
1
RW
1
RW
6
M_TCPC_INITIAL
1
RW
5
M_SRC_HV
1
RW
4
M_SRC_VBUS
1
RW
3
M_VBUS_PRESENT_D ETC
1
RW
2
M_VBUS_PRESENT
1
RW
1
M_VCONN_PRESENT
1
RW
0
M_SINK_VBUS
1
RW
7
M_ALL_REGISTERS_ RESET_TO_DEFAULT
1
RW
6
M_FORCE_OFF_VBUS
1
RW
5
M_AUTO_DISC_FAIL
1
RW
4
M_FORCE_DISC_FAIL
1
RW
3
M_VBUS_OC
1
RW
2
M_VBUS_OV
1
RW
1
M_VCON_OC
1
RW
0
M_I2C_ERROR
1
RW
7:1
Reserved
0000000
R
0
M_VSAFE0V
1
RW
7
H_IMPEDENCE
0
R
6
DEBUG_ACCESSORY_ CONNECT
1
RW
0 7
0x14
0x15
0x16
0x18
POWER_STA TUS_MASK
FAULT_STAT US_MASK
EXTENDED_ STATUS_MA SK
CONFIG_ STANDARD_ OUTPUT
MediaTek Confidential
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description 0: Interrupt masked, 1: Interrupt unmasked 0: Interrupt masked, 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked, 1: Interrupt unmasked 0: Interrupt masked, 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked, 1: Interrupt unmasked 0: Interrupt masked, 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked Reserved 0: Interrupt masked, 1: Interrupt unmasked 0: Standard output control 1: Force all outputs to high impedance May be used to save power in Sleep Controlled by the TCPM 0: Debug Accessory Connected# output is driven low. Debug Accessory connected 1: Debug Accessory Connected# output is driven high. No Debug Accessory connected (default) Controlled by either the TCPM or TCPC. The TCPC shall ignore writes to this bit if TCPC_CONTROL.Debug AccessoryControl = 0b.
Page 177 of 210
MT6360 PMIC Datasheet Confidential A Address
0x19
Reg Name
Bit
Bit Name
Default
Type
5
AUDIO_ACC_CONNEC T
1
R
4
ACTIVE_CABLE_CONN ECT
0
R
3:2
MUX_CTRL
00
R
1
CONNECT_PRESENT
0
RW
0
CONNECT_ORIENT
0
RW
7
Reserved
0
R
6
ENABLE_LOOKING4CO NNECTION_ALERT
0
RW
5
ENABLE_WATCHDOG_ TIMER
0
RW
4
DEBUG_ACCESSORY_ CONTROL
0
RW
3:2
Reserved
00
R
1
BIST_TEST_MODE
0
RW
TCPC_CONT ROL
MediaTek Confidential
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description 0: Audio accessory connected 1: No audio accessory connected controlled by the TCPM 0: No active cable connected 1: Active cable connected Controlled by the TCPM 00: No connection 01: USB3.1 Connected 10: DP Alternate Mode – 4 lanes 11: USB3.1 + Display Port Lanes 0 & 1 Controlled by the TCPM 0: No Connection 1: Connection Controlled by the TCPM. 0: Normal (CC1 = A5, CC2 = B5, TX1 = A2/A3, RX1 = B10/B11) 1: Flipped (CC2 = A5, CC1 = B5, TX1 = B2/B3, RX1 = A10/A11) Controlled by the TCPM The TCPC shall ignore writes to this bit if TCPC_CONTROL.Debug AccessoryControl = 0 Reserved 0: Disable ALERT.CcStatus assertion when CC_STATUS.Looking4Co nnection changes 1: Enable ALERT.CcStatus assertion when CC_STATUS.Looking4Co nnection changes 0: Watchdog monitoring is disabled 1: Watchdog monitoring is enabled 0: Controlled by TCPC 1: Controlled by TCPM. The TCPM writes 1 to this register to take over control of asserting the DebugAccessoryConnecte d#. Reserved 0: Normal operation. incoming messages enabled by RECEIVE_DETECT passed to TCPM via Alert. 1: BIST test mode. Incoming messages enabled by RECEIVE_DETECT result
Page 178 of 210
MT6360 PMIC Datasheet Confidential A Address
0x1A
Reg Name
ROLE_CONT ROL
Bit
Bit Name
Default
Type
0
PLUG_ORIENT
0
RW
7
Reserved
0
R
6
DRP
0
RW
5:4
RP_VALUE
00
RW
3:2
CC2
10
RW
1:0
CC1
10
RW
7:5
Reserved DIS_FORCE_OFF_VBU S
000
R
0
RW
4
0x1B
FAULT_CON TROL
3
DIS_VBUS_DISC_FAU LT_TIMER
0
RW
VBUS control 2
MediaTek Confidential
DIS_VBUS_OC
0
RW
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description in GoodCRC response but may not be passed to the TCPM via Alert. TCPC may temporarily store incoming messages in the receive message buffer, but this may or may not result in a Receive SOP* message status or a Rx buffer overflow alert. 0: When Vconn is enabled, apply it to the CC2 pin. Monitor the CC1 pin for BMC communications if PD messaging is enabled. 1: When Vconn is enabled, apply it to the CC1 pin. Monitor the CC2 pin for BMC communications if PD messaging is enabled. Required Reserved 0: No DRP. Bits B3..0 determine Rp/Rd/Ra settings 1: DRP 00: Rp default 01: Rp 1.5A 10: Rp 3.0A 11: Reserved 00: Ra 01: Rp (Use Rp definition in B5..4) 10: Rd 11: Open (Disconnect or don’t care) Set to 11 if enabling DRP in B7..6 00: Ra 01: Rp (Use Rp definition in B5..4) 10: Rd 11: Open (Disconnect or don’t care) Set to 11 if enabling DRP in B7..6 Reserved Not support 0: Allow STANDARD INPUT SIGNAL Force Off VBUS control 1: Block STANDARD INPUT SIGNAL Force Off 0: Internal and External OCP circuit enabled 1: Internal and External OCP circuit disabled
Page 179 of 210
MT6360 PMIC Datasheet Confidential A Address
0x1C
0x1D
Reg Name
POWER_CON TROL
CC_STATUS
MediaTek Confidential
Bit
Bit Name
Default
Type
1
DIS_VBUS_OV
0
RW
0
DIS_VCON_OC
0
RW
7
Reserved
0
R
6
VBUS_VOL_MONITOR
1
RW
5
DIS_VOL_ALARM
1
RW
4
AUTO_DISC_DISCNCT _EN
0
RW
3
BLEED_DISC_EN
1
RW
2
FORCE_DISC_EN
0
RW
1
VCONN_POWER_SPT
0
RW
0
EN_VCONN
0
RW
7:6
Reserved
00
R
5
DRP_STATUS
0
R
4
DRP_RESULT
0
R
3:2
CC2_STATUS
00
R
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description 0: Internal and External OVP circuit enabled 1: Internal and External OVP circuit disabled 0: Fault detection circuit enabled 1: Fault detection circuit disabled Reserved 0: VBUS_VOLTAGE monitoring is enabled 1: VBUS_VOLTAGE monitoring is disabled 0: Voltage Alarms Power status reporting is enabled 1: Voltage Alarms Power status reporting is disabled 0: The TCPC shall not automatically discharge VBUS based on VBUS voltage. 1: The TCPC shall automatically discharge 0: Disable bleed discharge 1: Enable bleed discharge of VBUS Discharge current: 0.6mA 0: Disable forced discharge 1: Enable forced discharge of VBUS Discharge current: 7mA 0: TCPC delivers at least 1W on VCONN 1: TCPC delivers at least the power indicated in DEVICE_CAPABILITIES. VCONNPowerSupported 0: Disable VCONN source 1: Enable VCONN sSource to CC Required Reserved 0: The TCPC has stopped toggling or (ROLE_CONTROL.DRP = 00) 1: The TCPC is toggling 0: The TCPC is presenting Rp 1: The TCPC is presenting Rd If (ROLE_CONTROL.CC2 = Rp) or (DrpResult = 0) 00: SRC.Open (Open, Rp) 01: SRC.Ra (below maximum vRa) 10: SRC.Rd (within the vRd range) 11: Reserved
Page 180 of 210
MT6360 PMIC Datasheet Confidential A Address
Reg Name
Bit
Bit Name
Default
Type
Description If (ROLE_CONTROL.CC2 = Rd) or (DrpResult = 1) 00: SNK.Open (Below maximum vRa) 01: SNK.Default (Above minimum vRd-Connect) 10: SNK.Power1.5 (Above minimum vRd-Connect) Detects Rp 1.5A 11: SNK.Power3.0 (Above minimum vRd-Connect) Detects Rp 3.0A If ROLE_CONTROL.CC2 = Ra, this field is set to 00 If ROLE_CONTROL.CC2 = Open, this field is set to 00 This field always returns 00 if (DrpStatus = 1) or (POWER_CONTROL.Ena bleVconn = 1 and POWER_CONTROL.Plug Orientation = 0). Otherwise, the returned value depends upon ROLE_CONTROL.CC2. If (ROLE_CONTROL.CC1 = Rp) or (DrpResult = 0) 00: SRC.Open (Open, Rp) 01: SRC.Ra (below maximum vRa) 10: SRC.Rd (within the vRd range) 11: Reserved
1:0
CC1_STATUS
00
R
If (ROLE_CONTROL.CC1 = Rd) or DrpResult = 1) 00: SNK.Open (Below maximum vRa) 01: SNK.Default (Above minimum vRd-Connect) 10: SNK.Power1.5 (Above minimum vRd-Connect) Detects Rp-1.5A 11: SNK.Power3.0 (Above minimum vRd-Connect) Detects Rp-3.0A If ROLE_CONTROL.CC1 = Ra, this field is set to 00 If ROLE_CONTROL.CC1 = Open, this field is set to 00 This field always returns 00 if (DrpStatus = 1) or (POWER_CONTROL.Ena bleVconn = 1 and POWER_CONTROL.Plug
MediaTek Confidential
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Page 181 of 210
MT6360 PMIC Datasheet Confidential A Address
0x1E
0x1F
Reg Name
POWER_STA TUS
Bit
Bit Name
Default
Type
7
DEBUG_ACCESSORY_C ONNECT
0
R
6
TCPC_INITIAL
0
R
5
SRC_HV
0
R
4
SRC_VBUS
0
R
3
VBUS_PRESENT_DET C
1
R
2
VBUS_PRESENT
0
R
1
VCONN_PRESENT
0
R
0
SINK_VBUS
0
R
7
ALL_REGISTERS_RESE T_TO_DEFAULT
1
RW
6
FORCE_OFF_VBUS
0
RW
5
AUTO_DISC_FAIL
0
RW
FAULT_STAT US
MediaTek Confidential
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description Orientation = 0). Otherwise, the returned value depends upon ROLE_CONTROL.CC1 0: No debug accessory connected 1: Debug accessory connected Reflects the state of the DebugAccessoryConnecte d# output if supported 0: The TCPC has completed initialization and all registers are valid 1: The TCPC is still performing internal initialization and the only registers that are guaranteed to return the correct values are 00h..0Fh 0: vSafe5V 1: High voltage 0: Sourcing Vbus is disabled 1: Sourcing Vbus is enabled 0: VBUS present Detection disabled 1: VBUS present detection enabled 0: VBUS disconnected 1: VBUS connected 0: VCONN is not present 1: This bit is asserted when VCONN present CC1 or CC2. Threshold is fixed at 2.4V 0: Sink is disconnected (Default and if not supported) 1: TCPC is sinking VBUS to the system load This bit is asserted when the TCPC resets all registers to their default value. This happens at initial power up or if an unexpected power reset occurs. 0: No fault detected, no action (default and not supported) 1: VBUS source/sink has been forced off due to external fault 0: No discharge failure 1: Discharge commanded by the TCPM failed
Page 182 of 210
MT6360 PMIC Datasheet Confidential A Address
0x20
Reg Name
EXTENDED_ STATUS
Bit
Bit Name
Default
Type
4
FORCE_DISC_FAIL
0
RW
3
VBUS_OC
0
RW
2
VBUS_OV
0
RW
1
VCONN_OC
0
RW
0
I2C_ERROR
0
RW
7:1
Reserved
0000000
R
0
VSAFE0V
0
R
etectionEnabled = 0.
MediaTek Confidential
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description 0: No discharge failure 1: Discharge commanded by the TCPM failed. 0: Not in an over-current protection state 1: Over-current fault latched 0: Not in an over-voltage protection state 1: Over-voltage fault latched. 0: No fault detected 1: Over-current VCONN fault latched 0: No Error 1: I2C error has occurred. Some of the conditions for asserting this bit: • TCPM writes to A the TRANSMIT register has been sent when the with an empty TRANSMIT_BUFFER is empty. • The watchdog timer has expired • TCPM writes an invalid COMMAND • TCPM writes a non-zero value to a reserved bit in a register • TCPM writes to the TRANSMIT_BUFFER when TCPC is transmitting the Fast Role Swap signal as triggered by the STANDARD INPUT signal Source Fast Role Swap • TCPM writes to CONFIG_EXTENDED1.F RSwapBidirectionalPin and STANDARD_INPUT_CA PABILITIES.SourceFastR oleSwap is not 10 Reserved 0: VBUS is not at vSafe0V 1: VBUS is at vSafe0V The TCPC shall report VBUS is at vSafe0V when TCPC detects VBUS is below 0.8V. This bit is not valid when POWER_STATUS.VbusD
Page 183 of 210
MT6360 PMIC Datasheet Confidential A Address
Reg Name
Bit
Bit Name
Default
Type
0x23
COMMAND
7:0
COMMAND
00000000
W
0x24
DEVICE_CAP ABILITIES_1 L
7:5
CPB_ROLES_SUPPORT
110
R
MediaTek Confidential
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description 0010 0010 DisableVbusDetect: Disable Vbus present and vSafe0V detection. The TCPC shall ignore this command and assert the FAULT_STATUS. I2CInterfaceError if it has sourcing or sinking power over Vbus enabled 0011 0011 EnableVbusDetect: Enable Vbus present and vSafe0V detection. 1001 1001 Look4Connection. Start DRP Toggling if ROLE_CONTROL.DRP = 1b. If ROLE_CONTROL.CC1/C C2 = 01b starts with Rp, if ROLE_CONTROL.CC1/C C2 =10b starts with Rd. If ROLE_CONTROL.CC1/C C2 are not both 01b or 10b, then do not start toggling. The TCPM shall issue COMMAND.Look4Conne ction to enable the TCPC to restart Connection Detection in cases where the ROLE_CONTROL contents will not change. An example of this is when a potential connection as a Source occurred but was further debounced by the TCPM to find the Sink disconnected. In this case a Source Only or DRP should go back to its Unattached.Src state. This would result in ROLE_CONTROL staying the same. 000: Type-C Port Manager can configure the Port as Source only or Sink only (not DRP) 001: Source only 010: Sink only 011: Sink with accessory support (optional) 100: DRP only 101: Adapter or Cable (Ra) only 110: Source, Sink, DRP, Adapter/Cable all
Page 184 of 210
MT6360 PMIC Datasheet Confidential A Address
0x25
Reg Name
DEVICE_CAP ABILITIES_1 H
MediaTek Confidential
Bit
Bit Name
Default
Type
4
CPB_ALL_SOP_SUPPO RT
1
R
3
CPB_SOURCE_VCONN
1
R
2
CPB_SINK_VBUS
1
R
1
CPB_SOURCE_HV_VBU S
0
R
0
CPB_SOURCE_VBUS
1
R
7
CPB_VBUS_HV_TARGE T
0
R
6
CPB_VBUS_OC
0
R
5
CPB_VBUS_OV
0
R
4
CPB_BLEED_DISC
1
R
3
CPB_FORCE_DISC
1
R
2
CPB_VBUS_MEASURE_ ALARM
0
R
1:0
CPB_SOURCE_RP_SUP PORT
10
R
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description supported 111: Not valid 0: All SOP* except SOP’_DBG/SOP”_DBG 1: All SOP* messages are supported 0: TCPC is not capable of switching VCONN 1: TCPC is capable of switching VCONN 0: TCPC is not capable controlling the sink path to the system load 1: TCPC is capable of controlling the sink path to the system load 0: TCPC is not capable of controlling the source high voltage path to VBUS 1: TCPC is capable of controlling the source high voltage path to VBUS 0: TCPC is not capable of controlling the source path to VBUS 1: TCPC is capable of controlling the source path to VBUS 0: VBUS_HV_TARGET register not implemented 1: VBUS_HV_TARGET register implemented 0: VBUS OCP is not reported by the TCPC 1: VBUS OCP is reported by the TCPC 0: VBUS OVP is not reported by the TCPC 1: VBUS OVP is reported by the TCPC 0: No Bleed Discharge implemented in TCPC 1: Bleed Discharge is implemented in the TCPC 0: No Force Discharge implemented in TCPC 1: Force Discharge is implemented in the TCPC 0: No VBUS voltage measurement nor VBUS Alarms 1: VBUS voltage measurement and VBUS Alarms 00: Rp default only 01: Rp 1.5A and default 10: Rp 3.0A, 1.5A, and default 11: Reserved Rp values which may be configured by the TCPM
Page 185 of 210
MT6360 PMIC Datasheet Confidential A Address
Reg Name
Bit
Bit Name
Default
Type
0x26
DEVICE_CAP ABILITIES_2 L
7
CPB_SINK_DISCONNEC T_DET
0
R
6
CPB_STOP_DISC_THD
0
R
Description via the ROLE_CONTROL register 0: VBUS_SINK_DISCONNE CT_THRESHOLD is not implemented (Use POWER_STATUS.VbusPr esent = 0 to indicate a Sink disconnect) 1: VBUS_SINK_DISCONNE CT_THRESHOLD implemented 0: VBUS_STOP_DISCHARG E_THRESHOLD is not implemented 1: VBUS_STOP_DISCHARG E_THRESHOLD is implemented 00: TCPC has 25mV LSB for its voltage alarm and uses all 10 bits in VBUS_VOLTAGE_ALAR M_HI_CFG and VBUS_VOLTAGE_ALAR M_LO_CFG. 01: TCPC has 50mV LSB for its voltage alarm and uses only 9 bits.
0x26
DEVICE_CAP ABILITIES_2 L
5:4
CPB_VBUS_VOL_ALAR M_LSB
00
R
VBUS_VOLTAGE_ALAR M_HI_CFG[0] and VBUS_VOLTAGE_ALAR M_LO_CFG[0] are ignored by TCPC. 10: TCPC has 100mV LSB for its voltage alarm and uses only 8 bits. VBUS_VOLTAGE_ALAR M_HI_CFG[1:0] and
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3:1
CPB_VCONN_POWER
000
R
0
CPB_VCONN_OCF
1
R
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
VBUS_VOLTAGE_ALAR M_LO_CFG[1:0] are ignored by TCPC. 11: Reserved 000: 1.0W 001: 1.5W 010: 2.0W 011: 3W 100: 4W 101: 5W 110: 6W 111: External 0: TCPC is not capable of detecting a Vconn fault
Page 186 of 210
MT6360 PMIC Datasheet Confidential A Address
0x27
Reg Name
Bit
Bit Name
Default
Type
7:6
Reserved
00
R
5
CPB_GENERIC_TIMER
0
R
4
CPB_LONG_MESSAGE
0
R
3
CPB_SMBUS_PEC
0
R
2
CPB_SRC_FRS
0
R
DEVICE_CAP ABILITIES_2 H
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© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description 1: TCPC is capable of detecting a Vconn fault Reserved 0: GENERIC_TIMER register is not supported 1: GENERIC_TIMER register is supported 0: TCPC only supports 30 bytes content of the SOP* message. The value in READABLE_BYTE_COU NT shall be less than or equal to 31. The value in I2C_WRITE_BYTE_COU NT shall be less than or equal to 30. 1: TCPC is capable of supporting 264 bytes content of the SOP* message. The TRANSMIT _BUFFER holds up to 264 bytes content of the SOP* message. The TCPM can write up to 132 bytes to the TX_BUF_BYTE_x in one burst. The value supported in I2C_WRITE_BYTE_COU NT shall be up to 132. RECEIVE_BUFFER holds up to 264 bytes 0: TCPC_CONTROL.Enable SMBusPEC is not implemented 1: TCPC_CONTROL.Enable SMBusPEC is implemented 0: Not capable of sending Fast Role Swap signal as Source when receiving COMMAND.SendFRSwap Signal or receiving STANDARD INPUT Source Fast Role Swap low. 1: Capable of sending Fast Role Swap signal as Source TCPC when receiving COMMAND.SendFRSwap Signal. If STANDARD_INPUT_CA PABITILIES.SourceFRSw ap = 1, capable of sending Fast Role Swap signal as Source when STANDARD INPUT Source Fast Role Swap is set low.
Page 187 of 210
MT6360 PMIC Datasheet Confidential A Address
0x28
Reg Name
Bit
Bit Name
Default
Type
1
CPB_SNK_FRS
0
R
0
CPB_WATCHDOG
1
R
7:5
Reserved
000
R
4:3
CPB_INPUT_SRC_FRS
00
R
2
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
7:5
CPB_INPUT_VBUS_ EXT_OV CPB_INPUT_VBUS_ EXT_OC CPB_INPUT_FORCE_ OFF_VBUS CPB_OUTPUT_VBUS_ SNK_DISCONNECT CPB_OUTPUT_DEBUG _ACCESSORY CPB_OUTPUT_VBUS_ PRESENT CPB_OUTPUT_AUDIO _ACCESSORY CPB_OUTPUT_ACTIVE _CABLE CPB_OUTPUT_MUX_C TRL CPB_OUTPUT_CONNE CT_PRESENT CPB_OUTPUT_CONNE CT_ORIENT Reserved
000
R
4
CABLE_PLUG
0
RW
STANDARD_ INPUT_CAPA BILITIES
1 0 7 6 5 0x29
STANDARD_ OUTPUT_CA PABILITIES
4 3 2 1 0
0x2E
MESSAGE_H EADER_INF O
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© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description 0: POWER_CONTROL.Fast RoleSwapEnable is not supported as Sink 1: POWER_CONTROL.Fast RoleSwapEnable supported as Sink 0: TCPC_CONTROL.Enable Watchdog Timer is not implemented 1: TCPC_CONTROL.Enable Watchdog Timer is implemented Reserved 00: Not present in TCPC 01: Present in TCPC as an input only pin 10: Present in TCPC as a bidirectional pin, sharing with the STANDARD OUTPUT signal Vbus Sink Disconnect Detect Indicator. The “Vbus Sink Disconnect Detect Indicator” bit in STANDARD_OUTPUT_C APABILITIES register shall also be set to 1. 11: Reserved 0: Not present in TCPC 1: Present in TCPC 0: Not present in TCPC 1: Present in TCPC 0: Not present in TCPC 1: Present in TCPC 0: Not present in TCPC 1: Present in TCPC 0: Not present in TCPC 1: Present in TCPC 0: Not present in TCPC 1: Present in TCPC 0: Not present in TCPC 1: Present in TCPC 0: Not present in TCPC 1: Present in TCPC 0: Not present in TCPC 1: Present in TCPC 0: Not present in TCPC 1: Present in TCPC 0: Not present in TCPC 1: Present in TCPC Reserved 0: Message originated from Source, Sink, or DRP 1: Message originated from a Cable Plug
Page 188 of 210
MT6360 PMIC Datasheet Confidential A Address
0x2F
0x30
0x31
0x32 0x33 0x34
Reg Name
RECEIVE_DE TECT
RX_BYTE_C OUNT
RX_BUF_FR AME_TYPE
RX_BUF_HE ADER_BYTE _0 RX_BUF_HE ADER_BYTE _1 RX_BUF_OB J1_BYTE_0
MediaTek Confidential
Bit
Bit Name
Default
Type
3
DATA_ROLE
0
RW
2:1
USBPD_SPECREV
01
RW
0
POWER_ROLE
0
RW
7
Reserved
0
R
6
EN_CABLE_RST
0
RW
5
EN_HARD_RST
0
RW
4
EN_SOP2DB
0
RW
3
EN_SOP1DB
0
RW
2
EN_SOP2
0
RW
1
EN_SOP1
0
RW
0
EN_SOP
0
RW
7:0
RX_BYTE_COUNT
00000000
RW
7:3
Reserved
00000
R
2:0
RX_FRAME_TYPE
000
R
7:0
RX_HEAD_0
00000000
R
Byte 0 (bits 7..0) of message header
7:0
RX_HEAD_1
00000000
R
Byte 1 (bits 15..8) of message header
7:0
RX_OBJ1_0
00000000
R
Byte 0 (bits 7..0) of 1st data object
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description 0: Sink 1: Source 00: Revision 1.0 01: Revision 2.0 10: Revision 3.0 11: Reserved 0: Sink 1: Source Reserved 0: TCPC does not detect Cable Reset signaling 1: TCPC detects Cable Reset signaling 0: TCPC does not detect Hard Reset signaling 1: TCPC detects Hard Reset signaling 0: TCPC does not detect SOP_DBG’’ message 1: TCPC detects SOP_DBG’’ message 0: TCPC does not detect SOP_DBG’ message 1: TCPC detects SOP_DBG’ message 0: TCPC does not detect SOP’’ message 1: TCPC detects SOP’’ message 0: TCPC does not detect SOP’ message 1: TCPC detects SOP’ message 0: TCPC does not detect SOP message 1: TCPC detects SOP message Indicates number of bytes in this register that are not stale. The TCPM should read the first RECEIVE_BYTE_COUNT bytes in this register. Reserved Type of received frame 000: Received SOP 001: Received SOP' 010: Received SOP'' 011: Received SOP_DBG’ 100: Received SOP_DBG’’ 110: Received Cable Reset All others are reserved.
Page 189 of 210
MT6360 PMIC Datasheet Confidential A Address 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F
0x50
Reg Name RX_BUF_OB J1_BYTE_1 RX_BUF_OB J1_BYTE_2 RX_BUF_OB J1_BYTE_3 RX_BUF_OB J2_BYTE_0 RX_BUF_OB J2_BYTE_1 RX_BUF_OB J2_BYTE_2 RX_BUF_OB J2_BYTE_3 RX_BUF_OB J3_BYTE_0 RX_BUF_OB J3_BYTE_1 RX_BUF_OB J3_BYTE_2 RX_BUF_OB J3_BYTE_3 RX_BUF_OB J4_BYTE_0 RX_BUF_OB J4_BYTE_1 RX_BUF_OB J4_BYTE_2 RX_BUF_OB J4_BYTE_3 RX_BUF_OB J5_BYTE_0 RX_BUF_OB J5_BYTE_1 RX_BUF_OB J5_BYTE_2 RX_BUF_OB J5_BYTE_3 RX_BUF_OB J6_BYTE_0 RX_BUF_OB J6_BYTE_1 RX_BUF_OB J6_BYTE_2 RX_BUF_OB J6_BYTE_3 RX_BUF_OB J7_BYTE_0 RX_BUF_OB J7_BYTE_1 RX_BUF_OB J7_BYTE_2 RX_BUF_OB J7_BYTE_3 TX_BUF_FR AME_TYPE
MediaTek Confidential
Bit
Bit Name
Default
Type
7:0
RX_OBJ1_1
00000000
R
7:0
RX_OBJ1_2
00000000
R
7:0
RX_OBJ1_3
00000000
R
7:0
RX_OBJ2_0
00000000
R
7:0
RX_OBJ2_1
00000000
R
7:0
RX_OBJ2_2
00000000
R
7:0
RX_OBJ2_3
00000000
R
7:0
RX_OBJ3_0
00000000
R
7:0
RX_OBJ3_1
00000000
R
7:0
RX_OBJ3_2
00000000
R
7:0
RX_OBJ3_3
00000000
R
7:0
RX_OBJ4_0
00000000
R
7:0
RX_OBJ4_1
00000000
R
7:0
RX_OBJ4_2
00000000
R
7:0
RX_OBJ4_3
00000000
R
7:0
RX_OBJ5_0
00000000
R
7:0
RX_OBJ5_1
00000000
R
7:0
RX_OBJ5_2
00000000
R
7:0
RX_OBJ5_3
00000000
R
7:0
RX_OBJ6_0
00000000
R
7:0
RX_OBJ6_1
00000000
R
7:0
RX_OBJ6_2
00000000
R
7:0
RX_OBJ6_3
00000000
R
7:0
RX_OBJ7_0
00000000
R
7:0
RX_OBJ7_1
00000000
R
7:0
RX_OBJ7_2
00000000
R
7:0
RX_OBJ7_3
00000000
R
7:6
Reserved
00
R
5:4
TX_RETRY_CNT
00
RW
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description Byte 1 (bits 15..8) of 1st data object Byte 2 (bits 23..16) of 1st data object Byte 3 (bits 31..24) of 1st data object Byte 0 (bits 7..0) of 2st data object Byte 1 (bits 15..8) of 2st data object Byte 2 (bits 23..16) of 2st data object Byte 3 (bits 31..24) of 2st data object Byte 0 (bits 7..0) of 3st data object Byte 1 (bits 15..8) of 3st data object Byte 2 (bits 23..16) of 3st data object Byte 3 (bits 31..24) of 3st data object Byte 0 (bits 7..0) of 4st data object Byte 1 (bits 15..8) of 4st data object Byte 2 (bits 23..16) of 4st data object Byte 3 (bits 31..24) of 4st data object Byte 0 (bits 7..0) of 5st data object Byte 1 (bits 15..8) of 5st data object Byte 2 (bits 23..16) of 5st data object Byte 3 (bits 31..24) of 5st data object Byte 0 (bits 7..0) of 6st data object Byte 1 (bits 15..8) of 6st data object Byte 2 (bits 23..16) of 6st data object Byte 3 (bits 31..24) of 6st data object Byte 0 (bits 7..0) of 7st data object Byte 1 (bits 15..8) of 7st data object Byte 2 (bits 23..16) of 7st data object Byte 3 (bits 31..24) of 7st data object Reserved 00: No message retry is required 01: Automatically retry message transmission once
Page 190 of 210
MT6360 PMIC Datasheet Confidential A Address
0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F 0x60 0x61 0x62 0x63
Reg Name
TX_BYTE_C OUNT TX_BUF_HE ADER_BYTE _0 TX_BUF_HE ADER_BYTE _1 TX_BUF_OB J1_BYTE_0 TX_BUF_OB J1_BYTE_1 TX_BUF_OB J1_BYTE_2 TX_BUF_OB J1_BYTE_3 TX_BUF_OB J2_BYTE_0 TX_BUF_OB J2_BYTE_1 TX_BUF_OB J2_BYTE_2 TX_BUF_OB J2_BYTE_3 TX_BUF_OB J3_BYTE_0 TX_BUF_OB J3_BYTE_1 TX_BUF_OB J3_BYTE_2 TX_BUF_OB J3_BYTE_3 TX_BUF_OB J4_BYTE_0 TX_BUF_OB J4_BYTE_1 TX_BUF_OB J4_BYTE_2 TX_BUF_OB J4_BYTE_3
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Bit
Bit Name
Default
Type
3
Reserved
0
R
2:0
TX_FRAME_TYPE
000
RW
7:0
TX_BYTE_COUNT
00000000
RW
7:0
TX_HEAD_0
00000000
RW
Byte 0 (bits 7..0) of message header
7:0
TX_HEAD_1
00000000
RW
Byte 1 (bits 15..8) of message header
7:0
TX_OBJ1_0
00000000
RW
7:0
TX_OBJ1_1
00000000
RW
7:0
TX_OBJ1_2
00000000
RW
7:0
TX_OBJ1_3
00000000
RW
7:0
TX_OBJ2_0
00000000
RW
7:0
TX_OBJ2_1
00000000
RW
7:0
TX_OBJ2_2
00000000
RW
7:0
TX_OBJ2_3
00000000
RW
7:0
TX_OBJ3_0
00000000
RW
7:0
TX_OBJ3_1
00000000
RW
7:0
TX_OBJ3_2
00000000
RW
7:0
TX_OBJ3_3
00000000
RW
7:0
TX_OBJ4_0
00000000
RW
7:0
TX_OBJ4_1
00000000
RW
7:0
TX_OBJ4_2
00000000
RW
7:0
TX_OBJ4_3
00000000
RW
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description 10: Automatically retry message transmission twice 11: Automatically retry message transmission three times Reserved 000: Transmit SOP 001: Transmit SOP' 010: Transmit SOP'' 011: Transmit SOP_DBG’ 100: Transmit SOP_DBG’’ 101: Transmit Hard Reset 110: Transmit Cable Reset 111: Transmit BIST Carrier Mode 2 (TCPC shall exit the BIST mode no later than tBISTContMode max) The number of bytes the TCPM will write
Byte 0 (bits 7..0) of 1st data object Byte 1 (bits 15..8) of 1st data object Byte 2 (bits 23..16) of 1st data object Byte 3 (bits 31..24) of 1st data object Byte 0 (bits 7..0) of 2st data object Byte 1 (bits 15..8) of 2st data object Byte 2 (bits 23..16) of 2st data object Byte 3 (bits 31..24) of 2st data object Byte 0 (bits 7..0) of 3st data object Byte 1 (bits 15..8) of 3st data object Byte 2 (bits 23..16) of 3st data object Byte 3 (bits 31..24) of 3st data object Byte 0 (bits 7..0) of 4st data object Byte 1 (bits 15..8) of 4st data object Byte 2 (bits 23..16) of 4st data object Byte 3 (bits 31..24) of 4st data object
Page 191 of 210
MT6360 PMIC Datasheet Confidential A Address 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F
0x8A
0x8C
Reg Name TX_BUF_OB J5_BYTE_0 TX_BUF_OB J5_BYTE_1 TX_BUF_OB J5_BYTE_2 TX_BUF_OB J5_BYTE_3 TX_BUF_OB J6_BYTE_0 TX_BUF_OB J6_BYTE_1 TX_BUF_OB J6_BYTE_2 TX_BUF_OB J6_BYTE_3 TX_BUF_OB J7_BYTE_0 TX_BUF_OB J7_BYTE_1 TX_BUF_OB J7_BYTE_2 TX_BUF_OB J7_BYTE_3
Bit
Bit Name
Default
Type
7:0
TX_OBJ5_0
00000000
RW
7:0
TX_OBJ5_1
00000000
RW
7:0
TX_OBJ5_2
00000000
RW
7:0
TX_OBJ5_3
00000000
RW
7:0
TX_OBJ6_0
00000000
RW
7:0
TX_OBJ6_1
00000000
RW
7:0
TX_OBJ6_2
00000000
RW
7:0
TX_OBJ6_3
00000000
RW
7:0
TX_OBJ7_0
00000000
RW
7:0
TX_OBJ7_1
00000000
RW
7:0
TX_OBJ7_2
00000000
RW
7:0
TX_OBJ7_3
00000000
RW
7:6
RP_VALUE_CC2
00
RW
5
RP_VALUE_CC2_EN
0
RW
4:0
Reserved
00000
R
7:5
VCONN_OCP_SEL
010
RW
4:1
Reserved
0000
R
CC_CTRL1
VCONNCTRL1
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© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description Byte 0 (bits 7..0) of 5st data object Byte 1 (bits 15..8) of 5st data object Byte 2 (bits 23..16) of 5st data object Byte 3 (bits 31..24) of 5st data object Byte 0 (bits 7..0) of 6st data object Byte 1 (bits 15..8) of 6st data object Byte 2 (bits 23..16) of 6st data object Byte 3 (bits 31..24) of 6st data object Byte 0 (bits 7..0) of 7st data object Byte 1 (bits 15..8) of 7st data object Byte 2 (bits 23..16) of 7st data object Byte 3 (bits 31..24) of 7st data object RP value of CC2 00: Rp default 01: Rp 1.5A 10: Rp 3.0A 11: Reserved Note: These bits work when RP_VALUE_CC2_EN is 1'b1. When this bit is 1'b1, RP value of CC1 and CC2 can select different values. 0: RP value of CC1 and CC2 are determined by RP_VALUE (reg 0x1A[5:4]) 1: RP value of CC1 is determined by RP_VALUE (reg 0x1A[5:4]). RP value of CC2 is determined by RP_VALUE_CC2 (reg 0x8A[7:6]) Reserved PD_VCONN OCP level selection 000: 100mA 001: 200mA 010: 300mA 011: 400mA 100: 500mA 101: 600mA 110: 700mA 111: 800mA Reserved
Page 192 of 210
MT6360 PMIC Datasheet Confidential A Address
0x8F
Reg Name
Bit
Bit Name
Default
Type
0
VCONN_CLIMIT_EN
0
RW
7
PD_DISMODE_EN
0
RW
6
ENEXTMSG
1
RW
5
SHIPPING_OFF
0
RW
4
WAKEUP_EN
1
RW
3
AUTOIDLE_EN
0
RW
2:0
AUTOIDLE_TIMEOUT
010
RW
MODECTRL2
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© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description PD_VCONN OCP current limit 0: OCP shutdown mode (disable PD_VCONN immediately when OC occurs) 1: OCP current limit mode (PD will clamp the current of PD_VCONN not to exceed OC level when OC occurs) PD Disable Mode Control 0:Enable PD connection 1:Disable PD connection 0: Disable PD3.0 Extended message 1: Enable PD3.0 Extended message affect GoodCRC receive detect between PD2.0 and PD3.0 In shutdown/shipping mode, both CC1 and CC2 keep with Rd, PD function is disabled. Exiting shutdown/shipping mode, PD function is available. 0: Shutdown/Shipping mode 1: NonShutdown/Shipping mode Wake up function for that can escape from lowpower mode when CC is attached under low-power mode 0: Disable 1: Enable When it enters idle mode, OSC of interrupt is closed for power saving.If there are status changes on CC or Vbus, the OSC will be restarted. The idle mode timeout time is based on AUTOIDLE_TIMEOUT(0 x8F[2:0]) setting 0: Auto enter idle mode disable 1: Auto enter idle mode enable These bits can be used to set the time before entering into auto idle, and the time setting is based on: (AUTOIDLE_TIMEOUT* 2+1)*6.4ms 000: 6.4ms 001: 19.2ms 010: 32ms
Page 193 of 210
MT6360 PMIC Datasheet Confidential A Address
0x90
0x91
Reg Name
Bit
Bit Name
Default
Type
7
PD_BG_EN
1
RW
6
BMCIO_IDLE_EN
0
RW
5
VCONN_DISCHARGE_E N
0
RW
4
LPWR_LDO_EN
0
RW
3
LPWR_EN
0
RW
2
PD_IREF_EN
1
RW
1
VBUS_DET_EN
1
RW
0
BMCIO_OSC_EN
1
RW
7:6
Reserved
00
R
5
M_VBUS_VALID
0
RW
MODECTRL3
RT_MASK1
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© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description …… 111: 96ms This bit will enable PD bandgap and OSC_320K. Furthermore, the whole PD function is gated by this bit. 0: PD Bandgap and OSC_320K disable 1: PD Bandgap and OSC_320K enable When no I2C command, interrupt and CC communication occurs, and the manual idle function can be on. 0: Disable 1: Enable PD_VCONN discharge path 0: Disable 1: Enable CC pin pull-up voltage selection in low-power mode 0: LDO disable (bypass VDDA) 1: LDO enable (2V) Set this bit to 1'b1, CC will enter low-power mode. In low-power mode, CC apply low-power Rp/Rd to reduce power consumption, and CC will exit low-power mode when Rp or Rd attached on CC1 or CC2 automatically. 0: Exit low-power mode 1: Enter low-power mode Set this bit to enable PD IREF. PD function can work after PD IREF is enabled. 0: Disable PD IREF 1: Enable PD IREF PD VBUS detection function 0: Disable 1: Enable 24M oscillator for BMC communication 0: Disable 24M oscillator 1: Enable 24M oscillator Note: 24M oscillator will be enabled automatically when INT occur. Reserved 0: Interrupt masked, 1: Interrupt unmasked
Page 194 of 210
MT6360 PMIC Datasheet Confidential A Address
0x92
0x93
0x95
0x96
Reg Name
RT_MASK2
RT_MASK3
RT_MASK5
Bit
Bit Name
Default
Type
4
M_VBUS_MEAS_80_F
0
RW
3
M_VCONN_SHT_GND
0
RW
2
M_OTD_FLAG
0
RW
1
M_VBUS_80
0
RW
0
M_WAKEUP
0
RW
7
M_WATER_DET_DONE
0
RW
6
M_WATER_EVENT
0
RW
5
Reserved
0
R
4
M_VCONN_VALID
0
RW
3
M_VCONOCP_CLIMIT
0
RW
2
M_VCONN_RV
0
RW
1
M_VCONN_OV_CC2
0
RW
0
M_VCONN_OV_CC1
0
RW
7
M_CMP_VBUS_TO_CC2
0
RW
6
M_CMP_VBUS_TO_CC1
0
RW
5
M_TX_DISCARD_TIME OUT
0
RW
4
M_CTD
0
RW
3:0
Reserved
0000
R
7
M_MIDDET_CC2
0
RW
6
M_MIDDET_CC1
0
RW
5
M_HIDET_CC2
0
RW
4
M_HIDET_CC1
0
RW
3
M_LODET_CC2
0
RW
2
M_LODET_CC1
0
RW
1
M_RA_CABLE_CC2
0
RW
0
M_RA_CABLE_CC1
0
RW
7:6
Reserved
00
R
5
INT_VBUS_VALID
0
RWC
4
INT_VBUS_MEAS_80_ F
0
RWC
RT_INT1
MediaTek Confidential
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description 0: Interrupt masked, 1: Interrupt unmasked 0: Interrupt masked, 1: Interrupt unmasked 0: Interrupt masked, 1: Interrupt unmasked 0: Interrupt masked, 1: Interrupt unmasked 0: Interrupt masked, 1: Interrupt unmasked 0: Interrupt masked, 1: Interrupt unmasked 0: Interrupt masked, 1: Interrupt unmasked Reserved 0: Interrupt masked, 1: Interrupt unmasked 0: Interrupt masked, 1: Interrupt unmasked 0: Interrupt masked, 1: Interrupt unmasked 0: Interrupt masked, 1: Interrupt unmasked 0: Interrupt masked, 1: Interrupt unmasked 0: Interrupt masked, 1: Interrupt unmasked 0: Interrupt masked, 1: Interrupt unmasked 0: Interrupt masked, 1: Interrupt unmasked 0: Interrupt masked, 1: Interrupt unmasked Reserved 0: Interrupt masked, 1: Interrupt unmasked 0: Interrupt masked, 1: Interrupt unmasked 0: Interrupt masked, 1: Interrupt unmasked 0: Interrupt masked, 1: Interrupt unmasked 0: Interrupt masked, 1: Interrupt unmasked 0: Interrupt masked, 1: Interrupt unmasked 0: Interrupt masked, 1: Interrupt unmasked 0: Interrupt masked, 1: Interrupt unmasked Reserved 0: Cleared 1: When VBUS_VALID status (0x9B[5]) changes 0: Cleared, 1: When VBUS_MEAS_80 (0x9B[4]) status changes from 1'b0 to 1'b1
Page 195 of 210
MT6360 PMIC Datasheet Confidential A Address
0x97
0x98
Reg Name
Bit
Bit Name
Default
Type
3
INT_VCONN_SHT_GND
0
RWC
2
INT_OTD_FLAG
0
RWC
1
INT_VBUS_80
0
RWC
0
INT_WAKEUP
0
RWC
7
INT_ONESHOT_EVENT
0
RWC
6
INT_RUST_EVENT
0
RWC
5
Reserved
0
R
4
INT_VCONN_INVALID
0
RWC
3
INT_VCONNOCP_CLIM IT_F
0
RWC
2
INT_VCONN_RV
0
RWC
1
INT_VCONN_OV_CC2
0
RWC
0
INT_VCONN_OV_CC1
0
RWC
7
INT_CMP_VBUS_TO_C C2
0
RWC
6
INT_CMP_VBUS_TO_C C1
0
RWC
RT_INT2
RT_INT3
MediaTek Confidential
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description 0: Cleared 1: When VCONN_SHT_GND status (0x9B[3]) changes to 1'b1 0: Cleared 1: When OTD_FLAG status (0x9B[2]) changes from 1'b0 to 1'b1 0: Cleared 1: When VBUS_SAFE0V (0x9B[1]) changes from 1'b0 to 1'b1 0: Cleared 1: Exit Low-power mode When RUST_DET_ONESHOT_ EN is set 1'b1 then the detection is operated 0: Detection is not operated 1: Detection is over Water detection interrupt 0: No event 1: When the number of counts set by 0xC1[3:2] with rust status (0xC0[3:0]) is achieved, this bit will become 1'b1 Reserved 0: Cleared 1: VCONN_INVALID status (0x9C[4]) changes from 1'b0 to 1'b1 0: Cleared 1: VCONN_OCP_FLAG (0x9C[3]) changes from 1'b1 to 1'b0 at current Limit Mode 0: Cleared 1: VCONN_RV status (0x9C[2]) changes from 1'b0 to 1'b1 0: Cleared 1: VCONN_OV_CC2 status (0x9C[1]) changes from 1'b0 to 1'b1(level trigger) 0: Cleared 1: VCONN_OV_CC1 status (0x9C[0]) changes from 1'b0 to 1'b1(level trigger) 0: Cleared 1: CMP_VBUS_TO_CC2 status (0x9D[7]) changes from 1'b0 to 1'b1 0: Cleared 1: CMP_VBUS_TO_CC1 status (0x9D[6]) changes from 1'b0 to 1'b1
Page 196 of 210
MT6360 PMIC Datasheet Confidential A Address
0x9A
0x9B
Reg Name
RT_INT5
Bit 5
Bit Name Reserved
Default 0
Type R
4
INT_CTD
0
RWC
3:0
Reserved
0000
R
7
INT_MIDDET_CC2
0
RWC
6
INT_MIDDET_CC1
0
RWC
5
INT_HIDET_CC2
0
RWC
4
INT_HIDET_CC1
0
RWC
3
INT_LODET_CC2
0
RWC
2
INT_LODET_CC1
0
RWC
1
INT_RA_CABLE_CC2
0
RWC
0
INT_RA_CABLE_CC1
0
RWC
7:6
Reserved
00
R
5
VBUS_VALID
0
R
4
VBUS_MEAS_80
0
R
3
VCONN_SHT_GND
0
R
2
OTD_FLAG
0
R
RT_ST1
MediaTek Confidential
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description Reserved 0: Cleared 1: When cable yype detection is done. Reserved 0: Cleared 1: MIDDET_CC2 status (0x9F[7]) changes 0: Cleared 1: MIDDET_CC1 status (0x9F[6]) changes 0: Cleared 1: HIDET_CC2 status (0x9F[5]) changes 0: Cleared 1: HIDET_CC1 status (0x9F[4]) changes 0: Cleared 1: LODET_CC2 status (0x9F[3]) changes 0: Cleared 1: LODET_CC1 status (0x9F[2]) changes 0: Cleared 1: RA_CABLE_CC2 status (0x9F[1]) changes from 1'b0 to 1'b1 0: Cleared 1: RA_CABLE_CC1 status (0x9F[0]) changes from 1'b0 to 1'b1 Reserved 0: When VBUS voltage is lower than VREF_VBUS_VALID (0xDA[7:5]) 1: When VBUS voltage is greater than VREF_VBUS_VALID (0xDA[7:5]) 0: When VBUS voltage is lower than VREF_VBUS_MEAS(0xD 9[5:0]) 1: When VBUS voltage is greater than VREF_VBUS_MEAS (0xD9[5:0]) PD_VCONN short to GND means PD_VCONN is not greater than 2.4V after VCONN_SHT_GND_TIM ER (0xE3[5:4]) when PD_VCONN is enabled. 0: No PD_VCONN short to GND 1: PD_VCONN short to GND This bit works when TYPEC_OTD_EN (0x8A[2]) is enabled.
Page 197 of 210
MT6360 PMIC Datasheet Confidential A Address
0x9C
Reg Name
Bit
Bit Name
Default
Type
1
VBUS_SAFE0V
0
R
0
Reserved
0
R
7:6
WD_STATUS
00
R
5
Reserved
0
R
4
VCONN_INVALID
0
R
3
VCONN_OCP_FLAG
0
R
2
VCONN_RV
0
R
1
VCONN_OV_CC2
0
R
0
VCONN_OV_CC1
0
R
RT_ST2
VCONN_OVP_EN_CC1
0x9D
RT_ST3
MediaTek Confidential
7
CMP_VBUS_TO_CC2
0
R
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description 0: OT event not occur. 1: OT event occur. Note: OT event is from PMIC. 0: When VBUS voltage is greater than 0.8V. 1: When VBUS voltage is lower than 0.8V. Reserved Water detection results (update after water detection check done). 00: No water 01: CC1 or CC2 has water 10: DP or DM has water 11: Either of CC1 or CC2 and either of DP or DM have water Reserved 0: PD_VCONN voltage is greater than 2.7V. 1: PD_VCONN voltage is lower than 2.7V. Note: This bit works when VCONN_CLIMIT_EN (0x8C[0]) is enabled. 0: PD_VCONN current is lower than VCONN_OCP_SEL (0x8C[7:5]) setting. 1: PD_VCONN current is greater than VCONN_OCP_SEL (0x8C[7:5]) setting. When CC (selected for VCONN) voltage is greater than PD_VCONN (internal VCONN voltage), PD_VCONN RV event will occur. 0: no PD_VCONN RV occur 1: PD_VCONN RV occur 0: CC2 voltage is lower than 5.75V. 1: CC2 voltage is greater than 5.75V. Note: This bit works when VCONN_OVP_EN_CC2 (0xE2[3]) is enabled. 0: CC1 voltage is lower than 5.75V. 1: CC1 voltage is greater than 5.75V. Note: This bit works when (0xE2[4]) is enabled. Result of VBUS short to CC2 detection. 0: CC2 voltage is less than 3.45V
Page 198 of 210
MT6360 PMIC Datasheet Confidential A Address
0x9F
Reg Name
Bit
Bit Name
Default
Type
6
CMP_VBUS_TO_CC1
0
R
5
Reserved
0
R
4
CABLE_TYPE
0
R
3:0
Reserved
0000
R
7
MIDDET_CC2
0
R
6
MIDDET_CC1
0
R
RT_ST5
MediaTek Confidential
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description 1: CC2 voltage is greater than 3.45V Note: this bit works when CMPEN_VBUS_TO_CC2 (0xDC[7]) is set to 1'b1. Result of VBUS short to CC1 detection. 0: CC1 voltage is less than 3.45V 1: CC1 voltage is greater than 3.45V Note: this bit works when CMPEN_VBUS_TO_CC1 (0xDC[6]) is set to 1'b1. Reserved Result of Cable Type Detection. This bit will keep 1'b0 when VBUS is not present. 0: Type-C 1: Type-A Reserved Result of CC2 voltage detection. 0: CC2 voltage is less than VREF_LODET_CC2 (0xD5[3:0]) or greater than VREF_HIDET_CC2 (0xD5[7:4]). 1: CC2 voltage is greater than VREF_LODET_CC2 (0xD5[3:0]) and greater than VREF_HIDET_CC2 (0xD5[7:4]). Note: This bit works when CMPEN_VDET_CC2 (0xDB[5]), CMPEN_LODET_CC2 (0xDB[4]), and CMPEN_HIDET_CC2 (0xDB[3]) are all set to 1'b1 Result of CC1 voltage detection. 0: CC1 voltage is less than VREF_LODET_CC1 (0xD6[3:0]) or greater than VREF_HIDET_CC1 (0xD6[7:4]). 1: CC1 voltage is greater than VREF_LODET_CC1 (0xD6[3:0]) and greater than VREF_HIDET_CC1(0xD6 [7:4]). Note: This bit works when CMPEN_VDET_CC1 (0xDB[2]), CMPEN_LODET_CC1 (0xDB[1]), and
Page 199 of 210
MT6360 PMIC Datasheet Confidential A Address
Reg Name
MediaTek Confidential
Bit
Bit Name
Default
Type
5
HIDET_CC2
0
R
4
HIDET_CC1
0
R
3
LODET_CC2
0
R
2
LODET_CC1
0
R
1
RA_CABLE_CC2
0
R
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description CMPEN_HIDET_CC1(0x DB[0]) are all set to 1'b1 Result of CC2 voltage detection. 0: CC2 voltage is greater than VREF_HIDET_CC2 (0xD5[7:4]). 1: CC2 voltage is less than VREF_HIDET_CC2 (0xD5[7:4]). Note: This bit works when CMPEN_VDET_CC2 (0xDB[5]) and CMPEN_HIDET_CC2 (0xDB[4]) are both set to 1'b1 Result of CC1 voltage detection. 0: CC1 voltage is greater than VREF_HIDET_CC1 (0xD6[7:4]). 1: CC1 voltage is less than VREF_HIDET_CC1 (0xD6[7:4]). Note: This bit works when CMPEN_VDET_CC1 (0xDB[2]) and CMPEN_HIDET_CC1 (0xDB[1]) are both set to 1'b1 Result of CC2 voltage detection. 0: CC2 voltage is less than VREF_LODET_CC2 (0xD5[3:0]). 1: CC2 voltage is greater than VREF_LODET_CC2 (0xD5[3:0]). Note: This bit works when CMPEN_VDET_CC2 (0xDB[5]) and CMPEN_LODET_CC2 (0xDB[3]) are both set to 1'b1 Result of CC1 voltage detection. 0: CC1 voltage is less than VREF_LODET_CC1 (0xD6[3:0]). 1: CC1 voltage is greater than VREF_LODET_CC1 (0xD6[3:0]). Note: This bit works when CMPEN_VDET_CC1 (0xDB[2]) and CMPEN_LODET_CC1 (0xDB[0]) are both set to 1'b1 E-Mark Cable (RA) detection on CC2 during low-power mode.
Page 200 of 210
MT6360 PMIC Datasheet Confidential A Address
0xA0
Reg Name
SOFTRESET
0xA2
DRP_CTRL1
0xA3
DRP_CTRL2
0xA4
DRP_CTRL3
MediaTek Confidential
Bit
Bit Name
Default
Type
0
RA_CABLE_CC1
0
R
7:1
Reserved
0000000
R
0
SOFT_RESET
0
W
7:4
Reserved
0000
R
3:0
TDRP
0011
RW
7:0
DCSRCDRP[7:0]
01000111
RW
7:2
Reserved
000000
R
1:0
DCSRCDRP[9:8]
01
RW
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description 0: No RA Cable on CC2. 1: RA Cable on CC2. Note: This bit works when low-power mode is enabled. (LPWR_EN(0x90[3]) = 1'b1) E-Mark Cable (RA) detection on CC1 during low-power mode. 0: No RA Cable on CC1. 1: RA Cable on CC1. Note: This bit works when low-power mode is enabled. (LPWR_EN(0x90[3]) = 1'b1) Reserved When writing 1'b1 to this bit, it will trigger softreset event, and all register setting will reset to default value. Reserved The period a DRP will complete a Source to Sink and back advertisement. (Period = TDRP * 6.4 + 51.2 ms) 0000: 51.2 ms 0001: 57.6 ms 0010: 64 ms 0011: 70.4 ms … 1110: 140.8 ms 1111: 147.2 ms The percent of time that a DRP will advertise Source during tDRP. (DUTY = (DCSRCDRP[9:0] + 1) / 1024) 0000000000: 1/1024 0000000001: 2/1024 … 0101000111: 328/1024 … 1111111110: 1023/1024 1111111111: 1024/1024 Note: Setting with 0xA4[9:8] default = 328/1024 Reserved The percent of time that a DRP will advertise Source during tDRP. (DUTY = (DCSRCDRP[9:0] + 1) / 1024) 0000000000: 1/1024 0000000001: 2/1024 …
Page 201 of 210
MT6360 PMIC Datasheet Confidential A Address
Reg Name
Bit
Bit Name
Default
Type
0xBD
CABLE_TYPE _CTRL
7:0
CTD_TIMER
00011001
RW
7:4
Reserved
0000
R
WATCHDOG_ CTRL
3:0
WATCHDOG_SEL
1011
RW
I2C_TO_RST_
7
I2C_TO_RST_EN
0
RW
0xBE
0xBF
CTRL
and all register will reset
6:4
MediaTek Confidential
Reserved
000
R
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description 0101000111: 328/1024 … 1111111110: 1023/1024 1111111111: 1024/1024 Note: Setting with 0xA3[7:0] default = 328/1024 Cable Type Detect timer starts when RP connect or CTD_ONESHOT (0xEC[0]) = 1'b1, and stops when Cable Type Detect timer timeout. (Cable Type Detect timer timeout = (CTD_TIMER) * 3.2ms) 00000000: 0ms 00000001: 3.2ms … 00011001: 80ms ... 11111110: 812.8ms 11111111: 816.0ms Reserved The watchdog timer shall start when any of the interrupts that are not masked in the Alert register are set or when the Interrupt pin is asserted. (watchdog timeout time = (WATCHDOG_SEL+1) * 0.4 sec) 0000: 0.4s 0001: 0.8s … 1011: 4.4s ... 1110: 6.0s 1111: 6.4s Set this bit to 1'b1 to enable I2C reset timer. When I2C reset timer is enabled, it will monitor SCL and SDA. When SCL and SDA both keep low, I2C reset timer will start to count, and I2C reset timer will be cleared to 0 when SCL or SDA becomes high. When I2C reset timer timeout, it will trigger soft reset event, to default value. 0: Disable I2C reset timer 1: Enable I2C reset timer Reserved
Page 202 of 210
MT6360 PMIC Datasheet Confidential A Address
0xC0
Reg Name
Bit
Bit Name
Default
Type
3:0
I2C_TO_RST_SEL
1000
RW
7
WD_DPDM_DET_EN
0
RW
6
WD_PROTECT_EN
0
RW
5
WD_ONESHOT_EN
0
RW
WD_DET_CT RL1
MediaTek Confidential
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description Timeout time for I2C reset timer (timeout time = (I2C_TO_RST_SEL+1) * 12.5ms) 0000: 12.5ms 0001: 25.0ms … 1000: 112.5ms ... 1111: 200ms When this bit set to 1'b1, it will enable water detection flow. When water detection flow is enabled, it will process water detection checked on DP or DM after CC1 or CC2 attached. 0: Disable Water Detection flow 1: Enable Water Detection flow Note: Water detection flow works when lowpower mode is enabled (LPWR_EN(0x90[3]) = 1'b1). When this bit set to 1'b1, it will enable water protection flow. In water protection flow, CC1/CC2 or DP/DM will process water detection checked periodically (determined by WD_PINS_SEL(0xC1[7:6 ])). When CC1/CC2/DP/DM are not in water detection check, they will keep in floating. The period is determined from WD_SLEEP_TIME (0xC4[7:0]). 0: Disable water protection flow 1: Enable water protection flow Note: Water protection flow is work when lowpower mode is enabled (LPWR_EN(0x90[3]) = 1'b1). Set this bit to 1'b1 to trigger one-shot mode in water detection. When one-shot mode is triggered, it will process water detection check on CC1/CC2 or DP/DM (determined by WD_PINS_SEL
Page 203 of 210
MT6360 PMIC Datasheet Confidential A Address
0xC1
Reg Name
Bit
Bit Name
Default
Type
4
WD_VBUS_MODE_STS
0
R
3
WD_CC2_RUST_STS
0
R
2
WD_CC1_RUST_STS
0
R
1
WD_DM_RUST_STS
0
R
0
WD_DP_RUST_STS
0
R
7:6
WD_PINS_SEL
00
RW
5:4
Reserved
00
R
3:2
WD_PINS_CNT
00
RW
1:0
WD_EXIT_COUNT
00
RW
WD_DET_CT RL2
MediaTek Confidential
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description (0xC1[7:6])). 0: Not trigger 1: Trigger (after detection done→ reset to 0 automatically) WD+ mode status (for micro-b VBUS trigger DPDM water detection) 0:WD+ mode disable 1:WD+ mode enable Note: When WD+ mode is enabled, every time VBUS detect event occurs, oneshot mode is triggered once. Water Detection Status of CC2 0: No water detected in CC2 1: Water is detected in CC2 Water Detection Status of CC1 0: No water detected in CC1 1: Water is detected in CC1 Water Detection Status of DM 0: No water detected in DM 1: Water is detected in DM Water Detection Status of DP 0: No water detected in DP 1: Water is detected in DP WD pins selection when WD_PROTECT_EN or WD_ONESHOT_EN is set to "1" 00: DP, DM, CC1 and CC2 01: DP and DM 10: CC1 and CC2 11: Reserve Reserved Water detection senses CC1/CC2/DP/DM four pins, "WD_PINS_CNT=00" means at least 1 pin is detected for water detection. 00: at least 1 pin 01: at least 2 pins 10: at least 3 pins 11: at least 4 pins (all of four pins are detected water) Exiting counts during rust protection flow (when WD_PROTECT_EN is
Page 204 of 210
MT6360 PMIC Datasheet Confidential A Address
Reg Name
Bit
Bit Name
Default
Type
0xC4
WD_DET_CT RL5
7:0
WD_SLEEP_TIME
00001001
RW
7:4
VREF_HIDET_CC2
0111
RW
3:0
VREF_LODET_CC2
0001
RW
7:4
VREF_HIDET_CC1
0111
RW
0xD5
0xD6
HILO_CTRL1
HILO_CTRL2
MediaTek Confidential
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description "1") 00: 1 01: 2 10: 4 11: 8 Check period in water protection flow(when WD_PROTECT_EN (0xC0[6]) is 1'b1) 00000000: 102.4ms 00000001: 204.8ms … 00001001: 1.024s ... 11111110: 26.112s 11111111: 26.214s CC Voltage High detection VREF setting for CC2. Adjust VREF for dedicated voltage detect and trigger HIDET interrupt. This setting is also applied to DRP when toggled as Source to detect dedicated attached CC level. (VREF = 0.2V * (Code+1)) 0000: 0.2V 0001: 0.4V ... 0111: 1.6V (default) ... 1110: 3.0V 1111: 3.2V CC Voltage Low detection VREF setting for CC2. Adjust VREF for dedicated voltage detect and trigger LODET interrupt. This setting is also applied to DRP when toggled as Source to detect dedicated attached CC level. (VREF = 0.2V * (Code+1)) 0000: 0.2V 0001: 0.4V ... 1110: 3.0V 1111: 3.2V CC Voltage High detection VREF setting for CC1. Adjust VREF for dedicated voltage detect and trigger HIDET interrupt. This setting also applies to DRP when toggled as Source to detect dedicated attached CC level. (VREF = 0.2V * (Code+1))
Page 205 of 210
MT6360 PMIC Datasheet Confidential A Address
0xD9
0xDA
0xDC
Reg Name
Bit
Bit Name
Default
Type
3:0
VREF_LODET_CC1
0001
RW
7
VBUS_HYS_EN
1
RW
6
VBUS_MEAS_EN
0
RW
5:0
VREF_VBUS_MEAS_80
000000
RW
7:5
VREF_VBUS_VALID
000
RW
4:0
Reserved
00000
R
7
CMPEN_VBUS_TO_CC2
0
RW
6
CMPEN_VBUS_TO_CC1
0
RW
VBUS_CTRL1
VBUS and CC_CTRL
RESV_SEL
MediaTek Confidential
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description 0000: 0.2V 0001: 0.4V ... 0111: 1.6V (default) ... 1110: 3.0V 1111: 3.2V CC Voltage Low detection VREF setting for CC1. Adjust VREF for dedicated voltage detect and trigger LODET interrupt. This setting also applies to DRP when toggled as Source to detect dedicated attached CC level. (VREF= 0.2V*(Code+1)) 0000: 0.2V 0001: 0.4V ... 1110: 3.0V 1111: 3.2V VBUS detection hysteresis voltage 0: Disable 1: Enable VBUS voltage Measure comparator enable 0: Disable 1: Enable Voltage for VBUS*80% voltage measure (threshold: 0.5V to 24V, LSB = 0.5V*80% 000000: 0.5V * 80% 000001: 1.0V * 80% … 101110: 23.5V*80% 101111: 24.0V*80% 110000: Reserved … 111111: Reserved VBUS_VALID (0x9B[5]) threshold: 2.6V to 4.0V, LSB = 0.2V 000: 2.6V 001: 2.8V … 110: 3.8V 111: 4.0V Reserved 0: Disable VBUS short to CC2 detection 1: Enable VBUS short to CC2 detection (Check if CC2 voltage is greater than 3.45V or not) 0: Disable VBUS short to CC1 detection 1: Enable VBUS short to
Page 206 of 210
MT6360 PMIC Datasheet Confidential A Address
0xEC
Reg Name
CTD_CTRL2
MediaTek Confidential
Bit
Bit Name
Default
Type
5:0
Reserved
000000
R
7
DIS_RPDET
0
RW
6
RPDET_ONESHOT
0
RW
5
OT_CCOPEN_EN
1
RW
4
VBUS_AUTODIS
0
R
3
VBUS_BLEEDDIS
0
R
2
VBUS_FORCEDIS
0
R
1
CTD_EN
1
RW
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description CC1 detection (Check if CC1 voltage is greater than 3.45V or not) Reserved Rp Connect auto detection will check if Rp connects on CC every time CC acts as Sink after DRP toggling is finished. 0: Enable Rp Connect auto detection 1: Disable Rp Connect auto detection Set this bit to 1'b1 to enable Rp Connect detection manually. It will check if Rp connects on CC when CC acts as Sink. This bit works when RP Connect auto detection is disabled. (DIS_RPDET(0xEC[7]) set to 1'b1). 0: Disable Rp Connect detection 1: Enable Rp Connect detection Enable CC open when Type-C Connector OT is detected. 0: No change on CC when Type-C Connector OT detected. 1: Set CC open when TypeC Connector OT detected. VBUS auto discharge status 0: Not perform auto discharge 1: Perform auto discharge VBUS bleed discharge status 0: Not perform bleed discharge 1: Perform bleed discharge VBUS force discharge status 0: Not perform force discharge 1: Perform force discharge Set this bit to 1'b1 to enable auto cable type detection. For auto cable type detection, it will check the cable is Type-C or Type-A every time after cable plug-in when CC acts as Sink. 0: Disable auto cable type detection
Page 207 of 210
MT6360 PMIC Datasheet Confidential A Address
Reg Name
MediaTek Confidential
Bit
Bit Name
Default
Type
0
CTD_ONESHOT
0
RW
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Description 1: Enable auto cable type detection Set this bit to 1'b1 will trigger one-shot cable type detection. It will process cable type detection once. This bit will clear to 1'b0 when cable type detection is finished. 0: No operation 1: Trigger one-shot cable type detection Note: This bit works when CTD_EN (0xEC[1]) is 1'b0.
Page 208 of 210
MT6360 PMIC Datasheet Confidential A
6 6.1
MT6360 Packaging Outline Dimensions
Figure 6-1. Package dimension
MediaTek Confidential
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Page 209 of 210
MT6360 PMIC Datasheet Confidential A
Appendix
MediaTek Confidential
© 2018 - 2019 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc.
Page 210 of 210