MT6360U PMIC Datasheet [1.1 ed.]

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MT6360U PMIC Datasheet

Version:

1.1

Release date:

2020-04-15

Use of this document and any information contained therein is subject to the terms and conditions set forth in Exhibit 1. This document is subject to change without notice.

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MT6360U PMIC Datasheet Confidential A

Document Revision History Revision 0.1

Date 2020-04-01

Author JW Lin

1.0

2020-04-10

JW Lin

1.1

2020-04-15

JW Lin

MediaTek Proprietary and Confidential.

Description First edition First official release. 1. Features on p7: Modified Charger contents 2. Electrical Characteristics on p21: Modified Charger Frequency 3. Register Table and Descriptions on p132, 133: Modified and added note of PMU Part Register Detail Description 1. Application Information on p42: Corrected OTG Mode Operation descriptions 2. Application Information on p76: Corrected Table44 & Table4-5 3. Register Table and Descriptions on p91: Reserved PMU Part Register

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MT6360U PMIC Datasheet Confidential A

Table of Contents Document Revision History .......................................................................................................................... 2 Table of Contents ......................................................................................................................................... 3 1

2

3

Overview ........................................................................................................................................... 7 1.1

Features............................................................................................................................................. 7

1.2

Applications ....................................................................................................................................... 8

1.3

General Description .......................................................................................................................... 8

1.4

Ordering Information ........................................................................................................................ 9

1.5

Top Marking Definition ..................................................................................................................... 9

1.6

Pin Assignments and Description .................................................................................................... 10

1.7

Typical Application Circuit ............................................................................................................... 14

Electrical Characteristics....................................................................................................................15 2.1

Absolute Maximum Ratings ............................................................................................................ 15

2.2

Recommended Operating Range .................................................................................................... 16

2.3

Electrical Characteristics ................................................................................................................. 17

Typical Operating Characteristics ......................................................................................................31 3.1

4

Typical Operating Characteristics .................................................................................................... 31

Application Information ....................................................................................................................32 4.1

General Description ........................................................................................................................ 32

4.2

VDDA Over-Voltage Protection ....................................................................................................... 33

4.3

Over-Temperature Protection......................................................................................................... 34

4.4

MRSTB Pin ....................................................................................................................................... 35

4.5

Switching Charger ........................................................................................................................... 37

4.6

Charger Mode Operation ................................................................................................................ 38

4.7

OTG Mode Operation ...................................................................................................................... 42

4.8

Shipping Mode ................................................................................................................................ 43

4.9

Power Up from CHG_VIN ................................................................................................................ 44

4.10 MediaTek Pump Express+ (MTK, PE+) ............................................................................................. 48 4.11 Interrupt .......................................................................................................................................... 49 4.12 CHG_VBATOVPB Pin ........................................................................................................................ 50 4.13 Analog IR Drop Compensation ........................................................................................................ 51 4.14 CHG_ILIM Pin .................................................................................................................................. 52 4.15 ADC Conversion Operation Flow ..................................................................................................... 53 4.16 USB_PD............................................................................................................................................ 55 4.17 Type-C Detection ............................................................................................................................. 56 4.18 Detection through Autonomous DRP Toggles................................................................................. 57

............................................................... 58 4.20 FLED Flow Chart .............................................................................................................................. 60 4.21 Strobe Mode Operation .................................................................................................................. 62 4.22 Torch Mode Operation .................................................................................................................... 63 4.23 FL_TXMASK Function....................................................................................................................... 64 MediaTek Proprietary and Confidential.

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MT6360U PMIC Datasheet Confidential A 4.24 FLED Short Protection ..................................................................................................................... 65 4.25 Input Capacitor Selection ................................................................................................................ 66 4.26 FLED Strobe Mode Supply Limit ...................................................................................................... 67 4.27 Low Battery Voltage Protection (LBP) ............................................................................................. 68 4.28 FLED Power Control......................................................................................................................... 70 4.29 FLED Core Control ........................................................................................................................... 71 4.30 RGB LED Driver ................................................................................................................................ 72 4.31 Flash Mode ...................................................................................................................................... 73 4.32 Breath Mode ................................................................................................................................... 74 4.33 Register Mode ................................................................................................................................. 75 4.34 Low Dropout Regulator (LDOs) and Application Reference ............................................................ 76 4.35 SD_CARD_DET_N Pin....................................................................................................................... 77 4.36 I2C Interface ..................................................................................................................................... 78 4.37 Thermal Considerations .................................................................................................................. 79 4.38 Layout Considerations ..................................................................................................................... 80 5

6

Functional Description ......................................................................................................................81 5.1

General Description ........................................................................................................................ 81

5.2

Register Table and Description ....................................................................................................... 87

MT6360U Packaging ........................................................................................................................ 199 6.1

Outline Dimensions ....................................................................................................................... 199

Appendix .................................................................................................................................................. 200 Exhibit 1 Terms and Conditions ................................................................................................................. 201

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MT6360U PMIC Datasheet Confidential A Lists of Figures Figure 1-1. MT6360U WL-CSP-103B 4.64×4.14 (BSC) (top view) .......................................................................... 10 Figure 1-2. Application circuit ............................................................................................................................... 14 Figure 3-1. Typical operating characteristics......................................................................................................... 31 Figure 4-1. MRSTB function .................................................................................................................................. 35 Figure 4-2. MRSTB diagram .................................................................................................................................. 36 Figure 4-3. Charge profile ..................................................................................................................................... 38 Figure 4-4. VDDM power plan .............................................................................................................................. 44 Figure 4-5. IRQB pin diagram ................................................................................................................................ 49 Figure 4-6. ADC conversion operation flow .......................................................................................................... 53 Figure 4-7. Type-C port controller (TCPC) interface .............................................................................................. 58 Figure 4-8. FLED flow chart ................................................................................................................................... 61 Figure 4-9. FLCS1_EN and FLCS2_EN (FL_STROBE) ............................................................................................... 62 Figure 4-10. FLCS1_EN and FLCS2_EN (FL_STROBE_reg) ...................................................................................... 62 Figure 4-11. FLCS1_EN and FLCS2_EN (FL_TORCH) .............................................................................................. 63 Figure 4-12. FLCS1_EN and FLCS2_EN (FL_TORCH_reg) ....................................................................................... 63 Figure 4-13. FL_TXMASK function ........................................................................................................................ 64 Figure 4-14. CHG_VIN ≥ 5.6V strobe case............................................................................................................. 67 Figure 4-15. Torch case (CHG_VIN < 5.6V) ............................................................................................................ 68 Figure 4-16. Strobe case (CHG_VIN < 5.6V) .......................................................................................................... 68 Figure 4-17. Torch case (CHG_VIN ≥ 5.6V) ............................................................................................................ 69 Figure 4-18. Strobe case (CHG_VIN ≥ 5.6V) .......................................................................................................... 69 Figure 4-19. Torch case with OTG ......................................................................................................................... 69 Figure 4-20. Strobe case with OTG........................................................................................................................ 69 Figure 4-21. FLED power control block diagram ................................................................................................... 70 Figure 4-22. FLED core control block diagram ...................................................................................................... 71 Figure 4-23. RGB LED driver application circuit .................................................................................................... 72 Figure 4-24. RGB flash mode operating principle ................................................................................................. 73 Figure 4-25. RGB breath mode operating principle .............................................................................................. 74 Figure 4-26. RGB register mode operating principle ............................................................................................ 75 Figure 4-27. SD_CARD_DET_N function ............................................................................................................... 77 Figure 4-28. I2C timing diagrams ........................................................................................................................... 78 Figure 4-29. Derating curve of maximum power dissipation ................................................................................ 79 Figure 5-1. MT6360U functional block diagram ................................................................................................... 81 Figure 6-1. Package dimension ........................................................................................................................... 199

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MT6360U PMIC Datasheet Confidential A Lists of Tables Table 1-1. MT6360U pin description..................................................................................................................... 10 Table 2-1. Electrical specifications ........................................................................................................................ 17 Table 4-1. CHRDETB status ................................................................................................................................... 45 Table 4-2. Adapter detection ................................................................................................................................ 46 Table 4-3. USB PD abbreviations ........................................................................................................................... 58 Table 4-4. LDO types and brief specifications ....................................................................................................... 76 Table 4-5. LDO output voltage table ..................................................................................................................... 76 Table 4-6. Slave address list .................................................................................................................................. 78 Table 5-1. Control pin description......................................................................................................................... 82 Table 5-2. Setting instructions for unused channels ............................................................................................. 83 Table 5-3. BOM list ................................................................................................................................................ 83 Table 5-4. Protection list ....................................................................................................................................... 84 Table 5-5. PMU part register detailed description ................................................................................................ 87 Table 5-6. PMIC part register detail description ................................................................................................. 136 Table 5-7. LDO part register detail description ................................................................................................... 154 Table 5-8. PD part register detail description ..................................................................................................... 168

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MT6360U PMIC Datasheet Confidential A

1

Overview

1.1

‒ Supports dead battery

Features

‒ Ultra-low power mode for attach detection (<  Battery charger

10 mA)

‒ High-accuracy voltage/current regulation

‒ Supports BIST mode

‒ Average input current regulation (AICR):

‒ USB PD3.0

0.1~3.25A in 50 mA steps ‒ Charge current regulation accuracy: ±5% ‒ Charge voltage regulation accuracy: ±0.5% (0~70°C)

 Flash LED driver ‒ Synchronous boost dual flash LED driver with dual independently-programmable LED

‒ Battery temperature sensing

current sources

‒ Synchronous 1.5MHz fixed-frequency PWM controller with up to 95% duty cycle

‒ Torch mode current: 25~400 mA in 12.5 mA steps per channel

‒ Thermal regulation and protection

‒ I2C-programmable flash safety timer, from 64

‒ Over-temperature protection

ms to 2,432 ms with 32 ms/step

‒ Input over-voltage protection

‒ Flash LED1/LED2 short-circuit protection;

‒ IRQ output for communication via I2C

output short-circuit protection

‒ Automatic charging

‒ TXMask protection with dedicated

‒ BATFET control to support ship mode, wakeup, and full system reset

FL_TXMASK pin ‒ Shared charger/OTG as power stage

‒ Resistance compensation from charger

‒ Independent torch bypass MOSFET from

output to cell terminal

VSYS

‒ USB OTG output voltage range: 4.85~5.825V

‒ Strobe mode current: 50 mA ~ 1.5A in 12.5

‒ D+/D- detection for BC1.2

mA steps or 25~750 mA in 6.25 mA steps per

‒ Micro-B ID pin rust

channel; up to 2.5A in total

‒ Integrated ADCs for system monitoring (charger current, voltage, and temperature) ‒ Low battery protection from 2.7V to 3.8V for boost operation

 LDO ‒ 6-channel LDO ‒ LDO1 output current: 150 mA

‒ Initial VOREG set for relieve battery

‒ LDO2/3 output current: 200 mA

protection

‒ LDO5 output current: 800 mA ‒ LDO6 output current: 300 mA

 USB_PD

‒ LDO7 output current: 600 mA

‒ PD-compatible dual-role ‒ Attach/Detach detection as host, device or dual-role port ‒ Current ‒ Cable recognition ‒ Supports alternate mode ‒ Supports VCONN with programmable overcurrent protection (OCP) MediaTek Proprietary and Confidential.

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MT6360U PMIC Datasheet Confidential A  RGB LED driver

accuracy voltage regulation, and charge

‒ 3-channel LED driver

termination circuitry. Besides, the charge current is

‒ Sink current for 3 RGB LEDs: 24 mA/channel

regulated through the integrated sensing resistors.

‒ Flash mode frequency range: 0.125~256 Hz

It also features USB on-the-go (OTG) support.

‒ RGB_ISINK1 for CHG_VIN power food The USB Type-C and PD controller complies with

indicator ‒ Supports register mode, flash mode, breath

the latest USB Type-C and PD standards. It integrates a complete Type-C transceiver including

mode

the Type-C termination resistors, Rp and Rd, and  Moonlight LED driver

enables the USB Type-C detection including attach

‒ 5~150 mA sink type LED driver

and orientation. It also integrates the physical layer

‒ Linear mode control

of the USB BMC power delivery protocol, allowing

‒ 5 mA/Step

power transfers and role swaps. The BMC PD function provides full support for alternate modes

 Buck

on the USB Type-C standard.

‒ 2-channel buck ‒ 0.3~1.3V programmable slew rate for voltage

Dual independent current sources supply for each flash LED. The power for the current sources in

transitions ‒ Output current capability: 3A

strobe mode are from the CHG_VMID pin, which is

‒ Supports sequenced off delay time selection

supplied from the charger in reverse boost mode,

‒ Input under-voltage lockout (UVLO)

the same operation as OTG mode of the charger.

‒ Thermal shutdown and overload protection

The high-side current sources, allowing for grounded-cathode connection for LEDs, provide strobe mode current levels from 50 mA to 1.5A in a

1.2

Applications

12.5 mA step or from 25 mA to 750 mA in a 6.25 mA step, and torch mode current levels from 25

 Cellular telephones

mA to 400 mA in a 12.5mA step. The two channels

 Personal information appliances

is able to support totally up to 2.5A.

 Tablet PCs  Portable instruments

The dual buck converter delivers a digitally programmable output 0.3V to 1.3V from an input

1.3

voltage supply of 2.5V to 5.5V. The output voltage

General Description

is programmed through an I2C interface capable of

MT6360U is a highly-integrated smart power

operating up to 3.4 MHz.

management IC which includes a single cell LiIon/Li-Polymer switching battery charger, a USB

By using a proprietary architecture with

Type-C and power delivery (PD) controller, dual

synchronous rectification, BUCK1/2 are capable of

flash LED current sources, a RGB LED driver, two

delivering 3A continuously as PVIN > 3.1V.

buck converters LDO1 supplies power to finger print unit (VFP); The switching charger integrates a synchronous

LDO2 supplies power to the touch panel unit (VTP);

PWM controller, power MOSFETs, input current

LDO3 and LDO5 supply power to SD card and UFS

sensing and input current regulation, high-

card (VMC and VMCH); LDO6 and LDO7 supply

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MT6360U PMIC Datasheet Confidential A power to DRAM (VMDDR and VDRAM2). These are in mobile phones and other hand-held devices. The output voltage is programmable via the I2C interface. The RGB LED driver is a 3-channel smart LED string controller to drive three channels of LEDs with a sink current of up to 24 mA and a CHG_VIN power good indicator with a sink current of up to 24 mA. All channels can be set independently via the I2C interface and are provided with three operation modes, register mode, flash mode and breath mode. MT6360U is available in a WL-CSP-103B 4.64×4.14 (BSC) package.

1.4

Ordering Information

MT6360U Package Type P : WL-CSP-103B 4.64x4.14 (BSC)

1.5

Top Marking Definition

MT6360UP

MT6360UP YYWW-$$$$H $$$$$$$$ $: Random code YYWW: Date code

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MT6360U PMIC Datasheet Confidential A

1.6

Pin Assignments and Description A1

A2

A3

CHG_ VIN

CHG_ VIN

CHG_ VIN

B1

B2

B3

CHG_ VMID

CHG_ VMID

CHG_ VMID

A4

A6

A7

CHG_ILIM

FL_ LEDCS2

FL_ LEDCS1

B5

B6

B7

FL_ VMID

FL_ VMID

C1

C2

C3

C4

C5

C6

CHG_ VLX

CHG_ VLX

CHG_ VLX

CHG_ VDDP

CHG_ BOOT

FL_ TXMASK

D1

D2

D3

D5

D6

CHG_ PGND

CHG_ PGND

FL_ TORCH

FL_ STROBE

E1

E3

E5

E6

VSYS

CHG_ VBATOVPB

CHG_ PGND

F1 VSYS

F2 VSYS

A9

A10

A11

PD_CC2

PD_VBUS

RGB_ ISINK3

RGB_ ISINK1

B8

B9

B10

B11

PD_IRQB

ML_ ISINK

RGB_ ISINK2

A8

FL_ PD_ VINTORCH VCONN5V C7 CHRDETB

E7

C8

C9

C10

C11

PD_CC1

RGB_ PGND

LDO1_ VOUT

LDO2_ VOUT

D8

D9

D10

D11

AGND

SRCLKEN_0

LDO3_ VOUT

LDO_ VIN1

E8

E9

E10

E11

LDO6_ VOUT

LDO_ VIN2

AGND

AGND

AGND

AGND

EN

F5

F6

F7

F8

F9

F11 LDO5_ VOUT

F3

F4

VSYS

CHG_ ENB

AGND

AGND

G4

G5

AGND

AGND

MRSTB

G6

G7

G8

G9

G10

G11

AGND

AGND

AGND

FAULTB

LDO7_ VOUTS

LDO7_ VOUT

H8

H9

H10

H11

BUCK2_ VOUT

BUCK1_ VOUT

BUCK1_ RSGND

LDO_ VIN3

G1

G2

G3

VBAT

VBAT

VBAT

H1

H2

H3

H4

H5

H6

H7

VBAT

CHG_ QONB

UVLO_ SEL

VREF_ TS

SDA

SDCARD_ DET_N

BUCK2_ RSGND

J1

J2

J3

J4

J5

J6

J7

J8

J9

J10

J11

VBATS

TS

HW_ TRAPPING

USB_ID

SCL

BUCK2_ PGND

BUCK2_ LX

BUCK2_ PVIN

BUCK1_ PVIN

BUCK1_ LX

BUCK1_ PGND

K1

K2

K3

K4

K5

K6

K7

K8

K9

K10

K11

VDDA

VDDM

BUCK2_ PGND

BUCK2_ LX

BUCK2_ PVIN

BUCK1_ PVIN

BUCK1_ LX

BUCK1_ PGND

VBATS_ GND

D-

D+

IRQB

AGND

Figure 1-1. MT6360U WL-CSP-103B 4.64×4.14 (BSC) (top view)

Table 1-1. MT6360U pin description Pin no. A1, A2, A3

Pin name CHG_VIN

A4

CHG_ILIM

A6 A7

FL_LEDCS2 FL_LEDCS1

A8

PD_CC2

and VBUS input for attach and detach A9 A10 A11

MediaTek Proprietary and Confidential.

PD_VBUS RGB_ISINK3 RGB_ISINK1

Pin description Charger power input Input current limit setting pin A resistor is connected from CHG_ILIM pin to ground to set up the maximum input current limit. The actual input current limit is the lower value set through the CHG_ILIM pin and IAICR register bits. High-side current source output 2 for flash LED2 High-side current source output 1 for flash LED1 Type-C connector configuration channel (CC) 2 This is used to detect a cable plug event and determine the cable orientation. detection when the device operates as an UFP port RGB LED current sink output 3 RGB LED current sink output 1

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Page 10 of 201

MT6360U PMIC Datasheet Confidential A Pin no.

Pin name

B1, B2, B3

CHG_VMID

B5, B6

FL_VMID

B7 B8

FL_VINTORCH PD_VCONN5V

B9

PD_IRQB

B10 B11 C1, C2, C3

ML_ISINK RGB_ISINK2 CHG_VLX

C4

CHG_VDDP

C5

CHG_BOOT

C6

FL_TXMASK

C7

CHRDETB

C8

PD_CC1

C9

RGB_PGND

C10 C11

LDO1_VOUT LDO2_VOUT

D1, D2, D3

CHG_PGND

D5 D6 D8, E5, E6, E7, E8, F5, F6, F7, F8, G5, G6, G7, G8 on and LP control pin D90 D10

FL_TORCH FL_STROBE

D11

LDO_VIN1

MediaTek Proprietary and Confidential.

AGND

LDO3_VOUT

Pin description Connection point between the reverse-blocking MOSFET and the high-side switching MOSFET Flash LED driver power input for strobe mode Connect a 4.7μF ceramic capacitor between FL_VMID and ground. Flash LED driver power input for torch mode Regulated input voltage to power PD_CC pins as VCONN Active-low open-drain interrupt output This requests the processor to check the registers. Moonlight LED current sink output RGB LED current sink output 2 Charger switch node for output inductor connection Regulated output voltage to supply for the PWM low-side gate driver and the bootstrap capacitor Connect a 2.2μF ceramic capacitor between CHG_VDDP and ground. 1. If VBUS is plugged in, CHG_VDDP will be powered by CHG_VIN and regulated to 4.9V. 2. If VBUS is unplugged, the charger will operate in sleep mode and the CHG_VDDP voltage will be 0V. Charger bootstrap voltage to supply the high-side MOSFET gate driver Connect a capacitor between CHG_BOOT and CHG_VLX. Configurable power amplifier synchronization input or configurable active-high torch mode enable Connect a 300kΩ internal pull-down resistor between FL_TXMASK and ground. CHG_VIN ready indication, open-drain output that indicates PD_VBUS is in Type-C connector configuration channel (CC) 1 This is used to detect a cable plug event and determine the cable orientation. RGB ground Tie RGB_PGND and ground on the PCB. LDO1 output LDO2 output Charger ground Tie CHG_PGND and ground on the PCB. Flash LED torch mode enable input Flash LED strobe mode enable input Analog ground Tie AGND and ground on the PCB. LDO3 output LDO_VIN1 power input for LDO1, LDO2 and LDO3 Connect a 2.2μF ceramic capacitor between LDO_VIN1 and ground.

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Page 11 of 201

e

MT6360U PMIC Datasheet Confidential A Pin no.

Pin name

E1, F1, F2, F3

VSYS

E3

CHG_VBATOVPB

E9

EN

E10

LDO6_VOUT

E11

LDO_VIN2

F4 F9 F11

CHG_ENB MRSTB LDO5_VOUT

G1, G2, G3, H1

VBAT

G4

IRQB

G9

FAULTB

G10 G11

LDO7_VOUTS LDO7_VOUT

H2

CHG_QONB

H3

UVLO_SEL

H4

VREF_TS

H5

SDA

H6 H7 H8 H9 H10

SDCARD_DET_N BUCK2_RSGND BUCK2_VOUT BUCK1_VOUT BUCK1_RSGND

H11

LDO_VIN3

Pin description System connection node Internal BATFET is connected between VSYS and VBAT. Connect a 22μF ceramic capacitor between VSYS and ground. Battery over-voltage protection (BAT OVP) indication This is an open-drain and active-low output. It will be low if BAT OVP occurs; otherwise, it is high. BUCK1, BUCK2, LDO6 and LDO7 enable control input When EN = low, all bucks and LDOs are turned off. LDO6 output LDO_VIN2 power input for LDO5 and logic circuit of LDO6/7 Connect a 2.2μF ceramic capacitor between LDO_VIN2 and ground. Charger enable input, active-low Manual reset input for hardware reset LDO5 output Charge current output node for battery connection The internal BATFET is connected between VSYS and VBAT. Connect a 10μF ceramic capacitor between VBAT and ground. Active-low open-drain interrupt output This requests the processor to read the registers. Indicates power not good of bucks and LDOs Active-low open-drain LDO7 output voltage-sense input LDO7 output Internal BATFET enable control input In shipping mode, CHG_QONB is pulled low for the duration of tSHIPMODE_CHG (typical 0.9s) to exit shipping mode. SYSUVLO rising threshold voltage setting and the UVLO_SEL pin defines default value Power output of 1.8V reference power for temperature sensing I2C interface serial data input/output Open-drain. An external pull-up resistor is required. When SDCARD_DET_N is active, disable LDO5. BUCK2 remote sense ground BUCK2 output voltage sense through this pin BUCK1 output voltage sense through this pin BUCK1 remote sense ground LDO_VIN3 power input for LDO6 and LDO7 Connect a 2.2μF ceramic capacitor between LDO_VIN3 and ground.

J1 J2

TS

J3

HW_TRAPPING

J4

USB_ID

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Temperature-sense input, connected to a resistor divider for temperature programming Either uses an external pull-down resistor or connects the pin to VDDA to define power configuration USB ID port connected to USB receptacle

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Page 12 of 201

MT6360U PMIC Datasheet Confidential A Pin no.

Pin name

Pin description I C interface serial clock input Open-drain. An external pull-up resistor is required. BUCK2 power ground The low-side MOSFET is referenced to this pin. CIN and COUT should be returned with a minimal path to these pins. BUCK2 switching node Connect to the inductor. BUCK2 power input voltage Connect to the input power source. Connect to CIN with minimal path. BUCK1 power input voltage Connect to the input power source. Connect to CIN with minimal path. BUCK1 switching node Connect to the inductor. BUCK1 power ground The low-side MOSFET is referenced to this pin. CIN and COUT should be returned with a minimal path to these pins. Battery voltage-sense ground USB D- port USB D+ port Regulated power input for an internal analog base Connect a 2.2μF ceramic capacitor between VDDA and ground. Regulated voltage output Connect a 2.2μF ceramic capacitor between VDDM and PGND. It also provides power to all VDDA-powered circuits. 2

J5

SCL

J6, K6

BUCK2_PGND

J7, K7

BUCK2_LX

J8, K8

BUCK2_PVIN

J9, K9

BUCK1_PVIN

J10, K10

BUCK1_LX

J11, K11

BUCK1_PGND

K1 K2 K3

VBATS_GND DD+

K4

VDDA

K5

VDDM

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Page 13 of 201

MT6360U PMIC Datasheet Confidential A

1.7

Typical Application Circuit TVS

VBUS

C1 2.2µF/35V

A1, A2, A3 C2 2.2µF/35V

D1

CHG_VIN

CHG_VMID

CHG_BOOT A9 TVS

CC1

C8 C3 330pF/25V

D7

A8 C4 330pF/25V

D8 Type-C or micro USB Connector

C5 4.7µF/6.3V

R1 1M

PD_CC1

VSYS

K3 DP K2

DN TVS

J4 R2 698R

TVS

A4

D3

D2

C1, C2, C3

L3 C16 47nF~100nF/16V 1µH

VBATS

C17 22µF/6.3V TVS

C18 10µF/6.3V

PD_VCONN5V

D+

CHG_VDDP

Battery Pack

K1 C4 C19 2.2µF/6.3V

DCHG_PGND

D1, D2, D3

USB_ID FL_VINTORCH

CHG_ILIM

B7

To VSYS

FL_LEDCS1 J2 TS

R4 NTC/10k

FL_LEDCS2

C7 2.2µF/6.3V

FL_TORCH

VDDM

FL_STROBE K4

C8 2.2µF/6.3V

A7 A6

FL_TXMASK

VDDA

R6 2.2K

D6 C6 To VSYS LED1

R7 2.2K

R8 2.2K

R9 2.2K

R10 2.2K

RGB_ISINK1 J5 H5 G4 B9

Processor

E3

SCL

RGB_ISINK2

SDA

RGB_ISINK3

IRQB

MT6360U

PD_IRQB

F9 D9

ML_ISINK RGB_PGND

UVLO_SEL

HW_TRAPPING

LDO_VIN1 G9 E9

EN

LDO_VIN2

CHG_QONB C7 CHRDETB LDO_VIN3 E9

SD CARD

AGND LDO2_VOUT

J9, K9

To VSYS

C9 4.7µF/6.3V L1 0.33µH

To VDRAM1 C10 22µF/6.3V

C11 22µF/6.3V To VDRAM1_FB To VDRAM1_GND

H9 H10 J11, K11

J8, K8

To VSYS C12 4.7µF/6.3V L2 0.47µH

To VRF13 C13

BUCK1_LX

J7, K7 H8

To SOC_SRAM+ADSP_FB H7 To SOC_SRAM+ADSP_GND J6, K6

H3

J3

LDO5_VOUT

BUCK1_RSGND BUCK1_PGND

LDO6_VOUT

LDO7_VOUT

BUCK2_PVIN

RUVLO_SEL

RHW_TRAPPING

D11 C21 2.2µF/6.3V E11 C22 2.2µF/6.3V H11 C23 2.2µF/6.3V C10 C24 1µF/6.3V C11 C25 1µF/6.3V D10 C26 1µF/6.3V F11 C27 1µF/6.3V

BUCK1_VOUT

LDO7_VOUTS

C14

C9

BUCK1_PVIN LDO3_VOUT

J10, K10

B10

SDCARD_DET_N LDO1_VOUT

D8, E5, E6, E7, E8, F5, F6, F7, F8, G5, G6, G7, G8

LED4

A10

FAULTB

H2

LED3

B11

MRSTB SRCLKEN_0

LED2

A11

CHG_VBATOVPB

F4 CHG_ENB

Another PMIC

D6

D5

To VDDIO R5 100K

To CHG_VMID

D5 K5

VDDM

C20 4.7µF/25V

FL_VMID

H4 VREF_TS R3 3.9k

D4

J1

B5, B6

C6 1nF~4.7nF/6.3V

To System

E1, F1, F2, F3

PD_CC2

VBATS_GND

ID

C5

VBAT

B8

To SYS

CHG_VLX

C15 4.7µF/25V

G1, G2, G3, H1

TVS

CC2

PD_VBUS

B1, B2, B3

E10 C28 10µF/6.3V G11 C29 22µF/6.3V

From VSYS

From VSYS

From VDRAM1

To VFP

To VTP

To VMC

To VMCH

To VMDDR C30 22µF/6.3V To VDRAM2

G10

BUCK2_LX BUCK2_VOUT BUCK2_RSGND BUCK2_PGND

Figure 1-2. Application circuit MediaTek Proprietary and Confidential.

© 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in part, is strictly prohibited.

Page 14 of 201

MT6360U PMIC Datasheet Confidential A

2

Electrical Characteristics

2.1

Absolute Maximum Ratings

(Note 1)

Parameter PD_VBUS PD_CC1, PD_CC2

Condition

Steady state Transient (< 10 ms)

Battery pin input (Note 4) CHG_VIN, CHG_VMID, CHG_BOOT, FL_VMID USB ID, D+, DCHG_LX

LX (peak < 100 ns duration)

Other pins Power dissipation, PD Package thermal resistance (Note 2) Lead temperature Storage temperature range ESD susceptibility (Note 3)

@TA = 25°C WL-CSP-103B 4.64x4.14 (BSC) WL-CSP-103B 4.64x4.14 (BSC), JA Soldering, 10 sec. HBM (human body model)

Min. -0.5 -0.5 -0.5 -0.5

Typ. -

Max. 28 24 6 7

Unit V V V V

-0.5

-

22

V

-0.5 -0.5 -0.5

-

24 16 -2 6

V

-

-

4.69

W

-65 -

21.3 -

260 150 2

°C/W °C °C kV

V V

Note 1: Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2: JA is measured under natural convection (still air) at TA = 25°C with the component mounted on a high effectivethermal-conductivity four-layer test board on a JEDEC 51-7 thermal measurement standard. Note 3: Devices are ESD sensitive. Handling precaution is recommended. Note 4: Battery input pin: VBAT/VBATS/VSYS/BUCKx_PVIN/BUCKx_LX/LDO_VINx/FL_VINTORCH

MediaTek Proprietary and Confidential.

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Page 15 of 201

MT6360U PMIC Datasheet Confidential A

2.2

Recommended Operating Range

(Note 5)

 PD_VBUS, CHG_VIN supply input voltage: 4~14V  VBAT supply input voltage: 2.8~5V  BUCK1/2_PVIN input voltage: 3.1~5V  LDO_VIN1/2: 3.15~5V  LDO_VIN3: 1.1~5V  IBAT (discharging current with internal MOSFET): 6A (continues)  IBAT (discharging current with internal MOSFET): 9A (peak, up to 1 sec duration)  Junction temperature range: -40~125°C  Ambient temperature range: -40~85°C Note 5: The device is not guaranteed to function outside its operating conditions.

MediaTek Proprietary and Confidential.

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Page 16 of 201

MT6360U PMIC Datasheet Confidential A

2.3

Electrical Characteristics

VCHG_VIN = 5V, VBAT = 4.2V, L1 = L2 = 0.33μH, L3 = 1μH, C2 = 2.2μF, C18 = 10μF, TA = 25°C, unless otherwise specified Table 2-1. Electrical specifications Parameter PMIC quiescent current

Symbol

Test condition

Min.

Typ.

Max.

Unit

Shutdown current

ISHDN

On VBAT pin, with all channels shut down, VBAT = 4V

-

63

85

μA

Shipping-mode current

IBAT_SHIP

VBAT only, in shipping mode

-

16

46

μA

-

8.55

11.12

mA

-

810

1,053

μA

-

150

-

°C

-15

-

15

°C

95

110

125

°C

-

-

0.4

V

Logic-high threshold

1.2

-

-

V

Logic-low threshold

-

-

0.4

V

External R selection R = 1 MΩ (2.9V), 100 mV/step

2.8

-

3.3

V

VSYS rising, default 2.9V

-50

-

+50

mV

-

15

-

ms

CHG_VIN supply current

ICHG_VIN

CHG_VIN supply current with charger ICHG_VIN_HZ in H-Z mode Over-temperature TOTP protection threshold Over-temperature TOTP_ACC protection accuracy Over-temperature TOTP_RECOVER protection recover Control I/O pin, VDDA and VSYS Logic-low threshold voltage for all open- VOL drain outputs Logic-high threshold VIH voltage for all inputs Logic-low threshold VIL voltage for all inputs SYS under-voltage protection rising VSYS_UVLO_RISE threshold range SYS under-voltage protection rising VSYS_UVLO_ACC_RISE threshold De-bouncing time by tDEBOUN_SYS_UVLO_RISE SYS UVLO rising

MediaTek Proprietary and Confidential.

VCHG_VLX is non-switching VCHG_VIN = 5V, VBAT = VCV_CHG ICHG = 0 Flash LED, LDOs, bucks and RGB devices disabled, PD cable attached (Full functions are not in the communication situation.) VCHG_VLX is in high-impedance mode VCHG_VIN = 5V, VBAT =4V Flash LED, LDOs, bucks, PD and RGB devices disabled Thermal shutdown threshold temperature Thermal shutdown temperature accuracy Thermal shutdown recover temperature

IDS = 10 mA

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Page 17 of 201

MT6360U PMIC Datasheet Confidential A Parameter SYS under-voltage protection falling threshold range SYS under-voltage protection falling threshold accuracy VDDA over-voltage protection threshold VDDA over-voltage protection hysteresis Pull-down ability on MRSTB Pull-down ability on SDCARD_DET_N Pull-down resistance on SRCLKEN_0 Pull-down resistance on EN USB ID USB_ID pull-up voltage USB_ID pull-up resistance tolerance USB_ID pull-down resistance Interrupt threshold voltage Interrupt threshold voltage hysteresis Interrupt debounce time tolerance Input equivalent capacitance Charger Sleep-mode entry threshold Sleep-mode exit threshold Sleep-mode exit deglitch time CHG_VIN bad adapter threshold CHG_VIN bad adapter CHG_VIN bad adapter sink current

MediaTek Proprietary and Confidential.

Symbol

Test condition

Min.

Typ.

Max.

Unit

VSYS_UVLO_FALL

I2C programmable, default 2.5V, 50 mV/step

2.4

-

2.8

V

VSYS_UVLO_ACC_FALL

VSYS falling, default 2.5V

-50

-

+50

mV

VVDDA_OVP

VDDA rising

5.25

5.5

5.75

V

VVDDA_OVP_HYS

VDDA falling

-

0.2

-

V

IPD_MRSTB

-

1

2.3

μA

IPD_SDCARD_DET_N

-

1

2.3

μA

RSRCLKEN_0

-

1

2.3

μA

REN

-

350

-

kΩ

VUSB_ID_PULLUP

VUSB_ID = 0.6V, 0x6F[7] = 1 VUSB_ID = 1.8V, 0x6F[7] = 0

0.57 1.71

0.6 1.8

0.63 1.89

V V

RUSB_ID_PULLUP

500 kΩ, 75 kΩ, 5 kΩ, 1 kΩ

-20

-

20

%

RUSB_ID_PULLUP

500 kΩ, 75 kΩ, 5 kΩ, 1 kΩ

3.75

5

6.25

kΩ

0x6F[6] = 0, 0x6F[7] = 0 0x6F[6] = 1, 0x6F[7] = 1 0x6F[7] = 1 0x6F[7] = 0 I2C programmable,5 μs ~ 64 ms (default 50 μs)

1.3 0.18 -

1.45 0.2 0.05 0.1

1.6 0.22 -

-10

-

10

%

-

-

20

pF

VID_INT VID_INT_HYS tID_INT_DEB CID_IN_CAP

V V

VSLEEP_ENTER_CHG

VCHG_VIN falling, VCHG_VIN - VBAT

0

0.04

0.1

V

VSLEEP_EXIT_CHG

VCHG_VIN rising, VCHG_VIN - VBAT

0.04

0.1

0.2

V

tD_SLEEP_EXIT_CHG

Exit sleep-mode

-

120

-

ms

VBAD_ADP_CHG

VCHG_VIN falling

-

3.8

-

V

V

V

-

150

-

mV

-

50

-

mA

rising

IBAD_ADP_SINK_CHG

© 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in part, is strictly prohibited.

Page 18 of 201

MT6360U PMIC Datasheet Confidential A Parameter CHG_VIN bad adapter detection time Input current limit factor CHG_VIN minimum input voltage regulation (MIVR) threshold CHG_VIN minimum input voltage regulation accuracy

Symbol

Test condition

tBAD_ADP_DET_CHG

Min.

Typ.

Max.

Unit

-

30

-

ms

KILIM_CHG

Input current regulation 508 mA by CHG_ILIM pin with resistance = 698Ω

320

355

390

AΩ

VMIVR_CHG

I2C programmable range in 0.1V steps

3.9

-

13.4

V

VMIVR_ACC_CHG

VMIVR = 4.4V or 9V

-2

-

2

%

86

93

100

mA

440

470

500

mA

880

940

1,000

mA

1,300

1,400

1,500

mA

3.05

3.3

3.55

V

-

150

-

mV

VUVLO_CHG

IAICR = 100 mA, VCHG_VIN = 5V, VBAT = 3.8V IAICR = 500 mA, VCHG_VIN = 5V, VBAT = 3.8V IAICR = 1,000 mA, VCHG_VIN = 5V, VBAT = 3.8V IAICR = 1,500 mA, VCHG_VIN = 5V, VBAT = 3.8V VCHG_VIN rising

VUVLO_HYS_CHG

VCHG_VIN falling

VCHG_VIN_OVP_CHG1

VCHG_VIN rising, I2C programmable 5.5V

5.17

5.5

5.86

V

VCHG_VIN_OVP_CHG2

VCHG_VIN rising, I2C programmable 6.5V (default)

6.11

6.5

6.92

V

VCHG_VIN_OVP_CHG3

VCHG_VIN rising, I2C programmable 11V

10.34

11

11.71

V

VCHG_VIN_OVP_CHG4

VCHG_VIN rising, I2C programmable 14.5V

13.63

14.5

15.44

V

CHG_VIN overvoltage protection propagation delay

tCHG_VIN_OVP_CH

VCHG_VIN rising above VCHG_VIN over-voltage protection threshold turn off UUG MOS, OVP setting = 6.5V

-

100

-

ns

CHG_VIN overvoltage protection hysteresis

VCHG_VIN_OVP_HYS_CHG VCHG_VIN falling

-

250

-

mV

106

108

110

%

-

2

-

%

AICR 100 mA mode

IAICR_100mA_CHG

AICR 500 mA mode

IAICR_500mA_CHG

AICR 1,000 mA mode AICR 1,500 mA mode CHG_VIN UVLO CHG_VIN UVLO hysteresis CHG_VIN overvoltage protection threshold CHG_VIN overvoltage protection threshold CHG_VIN overvoltage protection threshold CHG_VIN overvoltage protection threshold

IAICR_1000mA_CHG IAICR_1500mA_CHG

VBAT VBAT_OVP_CHG protection threshold VBAT over-voltage VBAT_OVP_HYS_CHG protection hysteresis MediaTek Proprietary and Confidential.

V rising, as percentage of VOREG_CHG, as VBAT/VOREG_CHG, 0x12[4] TE = 0 VBAT falling, as (VBAT VOREG_CHG)/VOREG_CHG 0x12[4] TE = 0 © 2020 MediaTek Inc. All rights reserved.

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Page 19 of 201

MT6360U PMIC Datasheet Confidential A Parameter Thermal regulation threshold VSYS over-voltage protection threshold VSYS under-voltage protection threshold VBAT depletion threshold voltage VBAT depletion threshold voltage CHG_VIN force sleep mode supply current End of charge Battery regulation voltage range Battery regulation voltage accuracy Re-charge mode threshold Re-charge deglitch time End-of-charge current Default end-ofcharge current End-of-charge current accuracy End-of-charge deglitch time Charge current ICHG current Accuracy 1 ICHG current Accuracy 2 ICHG current Accuracy 3 Pre-charge mode threshold Pre-charge mode hysteresis Pre-charge accuracy Pre-charge current Pre-charge current accuracy MediaTek Proprietary and Confidential.

Symbol TTHREG_CHG

Test condition Charge current starts decreasing (default)

Min.

Typ.

Max.

Unit

-

120

-

°C

VSYS_OVP_CHG

VSYS rising

4.9

5.25

5.5

V

VSYS_UVP_CHG

VSYS falling

2.2

2.4

2.6

V

VBAT_DPL_RISE

VBAT_DPL rising

2.3

2.5

2.8

V

VBAT_DPL_FALL

VBAT_DPL falling

2

2.3

2.39

V

ICHG_VIN_SLEEP

Reg: 0x11[3] = 1

-

-

2.5

mA

3.9

-

4.71

V

-0.5

-

0.5

%

50

100

150

mV

-

120

-

ms

100

-

850

mA

-

250

-

mA

-20

-

20

%

-

2

-

ms

0.3

-

3

A

-20

-

20

%

-10

-

10

%

-5

-

5

%

2.0

-

3.5

V

-

0.2

-

V

-5

-

5

%

-

150

-

mA

-20

-

20

%

VOREG_CHG

VOREG_ACC_CHG

VRECH_CHG

I2C programmable in 10 mV steps VOREG_CHG = 4.2V, 4.35V, 4.36V, 4.37V, 4.38V, 4.43V or VOREG_CHG = 4.45V (TC = -10~ 70°C) (Note 6) I2C programmable, VBAT falling, difference below VOREG_CHG

tD_RECH_CHG

VBAT falling

IEOC_CHG

I2C programmable in 50 mA steps

IEOC_DEF_CHG

Default

IEOC_ACC

IEOC_CHG = 150 mA, 200 mA, 250 mA

tD_EOC_CHG ICHG ICHG_ACC1_CHG ICHG_ACC2_CHG ICHG_ACC3_CHG VPRECHG_CHG VPRECHG_HYS_CHG

I2C programmable in 0.1A steps, 0x17 bit[7:2] VBAT = 3.8V, 300 mA ≤ ICHG < 500 mA, (TC = -10~70°C) VBAT = 3.8V, 500 mA ≤ ICHG < 1,000 mA, (TC = -10~70°C) VBAT = 3.8V, ICHG ≥ 1,000 mA (TC = -10~70°C) I2C programmable in 0.1V steps, VBAT rising Pre-charge hysteresis VBAT falling

VPRECHG_ACC_CHG IPRECHG_CHG

I2C programmable (default)

IPRECHG_ACC_CHG © 2020 MediaTek Inc. All rights reserved.

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Page 20 of 201

MT6360U PMIC Datasheet Confidential A Parameter Trickle charge threshold Trickle charge threshold hysteresis Trickle charge threshold accuracy Trickle current Trickle current accuracy VSYS regulation voltage VSYS regulation voltage accuracy UUG on-resistance UG on-resistance LG on-resistance PPMOS onresistance Switching frequency Switching frequency accuracy Maximum duty cycle Minimum duty cycle VDDP regulation Charger buck OCP current Internal QONB pullup resistance QONB exit shipping mode duration QONB system reset duration BATFET reset time

-3

Symbol

Test condition

Max.

Unit

VBAT falling

-

2

-

V

VTRICHG_HYS

VBAT rising

-

200

-

mV

VTRICHG_ACC

-5

-

5

%

ITRICHG

-

100

-

mA

-20

-

20

%

3.3

-

4

V

-3

-

3

%

ITRICHG_ACC I2C programmable in 0.1V steps

VSYS_MIN_CHG VSYS_MIN_ACC_CHG RON_UUG_CHG RON_UG_CHG RON_LG_CHG

From CHG_VIN to CHG_VMID From CHG_VMID to CHG_VLX From CHG_VLX to PGND

-

10 20 20

30 40 40

mΩ mΩ mΩ

RON_PPMOS_CHG

From VSYS to VBAT

-

12

30

mΩ

fOSC0_CHG

I2C programmable to 1.5 MHz (default)

-

1.5

-

MHz

fOSC_ACC_CHG

-10

-

10

%

DMAX_CHG DMIN_CHG VVDDP_CHG

0 4.5 4 5.6

97 4.9 6 8

5.3 8 10.4

% % V

16.15

19

21.85

kΩ

0.86

0.96

1.06

s

12

15

18

s

0.6

0.66

0.72

s

15

18

21.6

s

-

4.6

-

V

-

50

-

mV

-

5.05

-

V

0.5

-

-

A

ICHG_BUCK_OCP_CHG

VCHG_VIN = 5.5V REG0x1D[2] = 1’b0 REG0x1D[2] = 1‘b1

RQONB_CHG tSHIPMODE_CHG tQONB_RST_CHG tBATFET_RST_CHG

CHG_QONB low for BATFET ontime to exit shipping mode CHG_QONB low time to enable full system reset BATFET off-time during full system reset Enter shipping mode delay

AICC threshold

VAICC_VTH

VCHG_VIN rising I2C programmable

AICC hysteresis

VAICC_HYS_VTH

OTG output VBSTCV_CHG regulation OTG - o 3 % BSTCV_ACC_CHG OTG over-load IBST_0.5A_CHG protection threshold

Confidential.

Typ.

VTRICHG

Shipping mode entry tD_SHIP_ENTER deglitch time

MediaTek Proprietary and

Min.

I2C programmable default

A

LOAD

OTG_OC = 0.5A REG 0x1A[2:0] = 000

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Page 21 of 201

MT6360U PMIC Datasheet Confidential A Parameter OTG CHG_VMID over-voltage protection threshold OTG CHG_VMID over-voltage protection hysteresis OTG VBAT undervoltage protection threshold OTG VBAT undervoltage protection hysteresis

Symbol

Min.

Typ.

Max.

Unit

5.72

6

6.28

V

-

200

-

mV

2.62

2.8

2.98

V

-

400

-

mV

-

8

-

mA

5.2

6.5

8.2

A

-

1

2.3

μA

0.5 0.25 0.8 50

0.6 0.3 100

0.7 0.4 2 150

V V V μA

7

-

13

μA

50

90

130

Ω

tDP_SRC_ON tDCD_TIMEOUT

40 300

64 -

1,200

ms ms

tDPSRC_HICRNT

28

32

36

ms

tCHGR_DET_DBNC

27

30

33

ms

6

-

14.5

V

VPD_VUS_OVP_ACC

-3

-

3

%

VPD_VUS_HYS

-

150

-

mV

2.6

-

3.7

V

-4

-

4

%

VMIDOVP_OTG_CHG

MediaTek Proprietary and Confidential.

VCHG_VMID rising

VMIDOVP_OTG_HYS_CHG

VBAT_UVP_OTG_CHG

I2C default, VBAT falling

VBAT_UVP_OTG_HYS_CHG VBAT rising

Boost supply current IBOOST_SUPPLY OTG over-current protection threshold Pull-down ability on CHG_ENB D+/D- detection D+ source voltage Data detect voltage VLGC voltage D- sink current Data contract detect current source Dedicated charging port resistance across D+/D+ source on-time DCD timeout D+ source off to high current Charger detect debounce CHRDETB PD_VBUS overvoltage protection threshold range PD_VBUS overvoltage protection accuracy PD_VBUS overvoltage protection hysteresis PD_VBUS UVLO protection threshold range PD_VBUS UVLO protection accuracy

Test condition

IOTG_OCP_CHG

OTG mode, ILOAD = 0 mA Default = 6.5A

IPD_CHG_ENB VDP_SRC VDAT_REF VLGC_CHG IDM_SINK IDP_SRC RD+D- DCP

VPD_VUS_OVP

VPD_VUS_UVLO

sEN_DCP = 1

VPD_VUS_OVP rising, I2C programmable (default 10.5V)

VPD_VUS_UVLO falling, I C programmable 0.1V/Step (default 3.7V)

VPD_VUS_UVLO_ACC © 2020 MediaTek Inc. All rights reserved.

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Page 22 of 201

MT6360U PMIC Datasheet Confidential A Parameter Symbol PD_VBUS UVLO VPD_VUS_UVLO_HYS_ protection hysteresis ADC

Min.

Typ.

Max.

Unit

-

150

-

mV

20.8

26

31.2

ms

RES_ADC

-

12

-

bit

VVBUS_DIV5_ADC_RANGE

1

-

22

V

VVBUS_DIV5ADC_RES

-

25

-

mV

VVBUS_DIV5ADC_ACC

-3

-

3

LSB

VVBUS_DIV2_ADC_RANGE

1

-

VDDA*2

V

VVBUS_DIV2ADC_RES

-

10

-

mV

VVBUS_DIV2ADC_ACC

-3

-

3

LSB

VBAT_ADC_RANGE

0

-

VDDA

V

VBAT_ADC_RES VBAT_ADC_ACC

-3

5 -

3

mV LSB

VSYS_ADC_RANGE

0

-

VDDA

V

VSYS_ADC_RES VSYS_ADC_ACC

-3

5 -

3

mV LSB

IIBUS_ADC_RANGE

0

-

5

A

-

50

-

mA

-3

-

3

-2

-

2

-2

-

2

IIBAT_ADC_RANGE

0

-

5

A

IIBAT_ADC_RES IIBAT_ADC_ACC

-2

50 -

2

mA LSB

T

-40

-

120

°C

-3

2 -

3

°C LSB

1.782

1.8

1.818

V

Only for one channel, 0x56[5:3] = 0 ms of waiting time and 0x58[7:0] = 0 ms of idle time

ADC conversion time tCONV_ADC Number of bits for ADC resolution CHG_VIN_DIV5 measurement range CHG_VIN_DIV5 resolution CHG_VIN_DIV5 accuracy CHG_VIN_DIV2 measurement range CHG_VIN_DIV2 resolution CHG_VIN_DIV2 accuracy VBAT measurement range VBAT resolution VBAT accuracy VSYS measurement range VSYS resolution VSYS accuracy IBUS measurement range IBUS resolution

IBUS accuracy

IBAT measurement range IBAT resolution IBAT accuracy TEMP_JC measurement TEMP_JC resolution TEMP_JC accuracy VREF_TS pull-up voltage MediaTek Proprietary and Confidential.

Test condition

IIBUS_ADC_RES

IIBUS_ADC_ACC

TTEMP_JC_ADC_RES TTEMP_JC_ADC_ACC

IBUS > 2A, IAICR [7:2] setting ≥ 400 mA IBUS < 2A, IAICR [7:2] setting ≥ 400 mA IBUS < 2A, IAICR [7:2] setting < 400 mA

Temperature < 85°C

VREF_TS_ADC © 2020 MediaTek Inc. All rights reserved.

Unauthorized reproduction or disclosure of this document, in whole or in part, is strictly prohibited.

LSB

Page 23 of 201

MT6360U PMIC Datasheet Confidential A Parameter Symbol TS voltage VTS_ADC_RANGE measurement range TS resolution VTS_ADC_RES TS accuracy TTS_ADC_ACC USB_ID VUSBID_ADC_RANGE measurement range USB_ID resolution VUSB_ID_ADC_RES Pump express PE+1 on time (A) tON_A_PE PE+1 on time (B) tON_B_PE PE+1 on time (C) tON_C_PE PE+1 off time (D) tOFF_D_PE PE+1 off time (I) tOFF_I_PE PE+2 off time (D) tOFF_D_PE PE+2 on time (E) tON_E_PE PE+2 on time (F) tON_F_PE PE+2 on time (G) tON_G_PE PE+2 off time (H) tOFF_H_PE PE+2 off time (I) tOFF_I_PE Flash LED current source

Min.

Typ.

Max.

Unit

0

-

VDDA

V

-2

5 -

mV LSB

0

-

-

5

2 VDDA 1.4 -

430 240 70 70 80 87 147 87 22 22 135

500 300 100 100 105 190 102.5 50 50 155

570 360 130 130 225 128 248 118 68 68 175

ms ms ms ms ms ms ms ms ms ms ms

-8

-

8

%

-6

-

6

%

-

0.1

4

μA

-

320

1,000

μA

VSC_FL

-

1

1.3

V

tD_SC_FL

1.8

2.5

3.3

ms

LED current accuracy ILED_ACC_FL LED current accuracy ILED_ACC_FL FL_LEDCSx leakage current FL_LEDCSx start-up current LEDCSX short threshold LEDCSX short event timer Flash timeout Flash timer accuracy Current source regulation voltage Current source regulation voltage Strobe/TXMask deglitch time Flash ready time Strobe FL OVP Strobe FL-CHG_VIN OVP hysteresis High-side switch onresistance MediaTek Proprietary and Confidential.

ILEAK_FL ISTART_FL

Test condition

VDDA > 3.4V

VBAT = 3.8V. Use PE+ adapter VBAT = 3.8V. Use PE+ adapter VBAT = 3.8V. Use PE+ adapter VBAT = 3.8V. Use PE+ adapter VBAT = 3.8V. Use PE+ adapter VBAT = 3.8V. Use PE+ adapter VBAT = 3.8V. Use PE+ adapter VBAT = 3.8V. Use PE+ adapter VBAT = 3.8V. Use PE+ adapter VBAT = 3.8V. Use PE+ adapter VBAT = 3.8V. Use PE+ adapter Flash LED current can be set from 25 mA to 400 mA Flash LED current can be set from 0.4A to 1.5A VLEDVIN = 5V, LEDCSX = 0, LEDCSX is disabled LEDCSX = 0, LEDCSX is enabled

V mV

tTIMEOUT_FL tTMR_ACC_FL

FLEDx_STRB_TO = 0100101 Timer is set by register.

-10

1,248 -

10

ms %

VREG_FL

ILED = 200 mA, 0x7C[1:0] = 00

-

200

300

mV

VREG_FL

ILED = 1,500 mA, 0x7C[1:0] = 01

-

-

500

mV

-

10

-

μs

-

4.5

5

ms

VIN_OVP_FL

5.45

5.6

5.75

V

VIN_OVP_Hys_FL

0.23

0.3

0.37

V

-

60

-

mΩ

tD_STRB_FL tFLSH_RDY_FL

EN_LEDCS = 1 to current reach 800 mA target value

RON_H_FL © 2020 MediaTek Inc. All rights reserved.

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Page 24 of 201

MT6360U PMIC Datasheet Confidential A Parameter Low-side switch onresistance Pull-down resistance on FL_STROBE Pull-down resistance on BL_EN Pull-down resistance on FL_TXMASK USB_PD Bit rate Maximum difference between the bit rate during the part of the packet following the preamble and the reference bitrate Time from the end of last bit of a frame until the start of the first bit of the next preamble Time before the start of the first bit of the preamble when the transmitter should start driving the line Time to cease driving the line after the end of the last bit of the frame Falling time Time to cease driving the line after the final high-to-low transition Rising time Voltage swing Transmitter output impedance Time window for detecting non-idle Receiver input impedance Low-power mode VCONN switch onresistance OCP range MediaTek Proprietary and Confidential.

Symbol

Test condition

Min.

Typ.

Max.

Unit

RON_L_FL

-

36

-

mΩ

RL_FL_STROBE

-

350

-

kΩ

RL_FL_TORCH

-

350

-

kΩ

RL_FL_TXMASK

-

350

-

kΩ

fBitRate_PD

270

300

330

Kbps

pBitRate_PD

-

-

0.25

%

tInterFrameGap_PD

25

-

-

μs

tStartDrive_PD

-1

-

1

μs

tEndDriveBMC_PD

-

-

23

μs

300

-

-

ns

1

-

-

μs

tRise_PD VSwing_PD

300 1.05

1.125

1.2

ns V

zDriver_PD

33

-

75

Ω

tTransitionWindow_PD

12

-

20

μs

z

1

-

-

MΩ

-

32

45

μA

-

0.7

1

Ω

200

-

600

mA

tFall_PD tHoldLowBMC_PD

ILOW-POWER_PD

DRP toggle

RON_VCONN_PD IOCP_PD © 2020 MediaTek Inc. All rights reserved.

Unauthorized reproduction or disclosure of this document, in whole or in part, is strictly prohibited.

Page 25 of 201

MT6360U PMIC Datasheet Confidential A Parameter Symbol DFP 80μA CC current ICC_DFP80_PD DFP 180μA CC ICC_DFP180_PD current DFP 330μA CC ICC_DFP330_PD current UFP pull-down resistance through Rd_PD CC pin UFP pull-down threshold voltage in VTH_DBL_PD dead battery UFP pull-down threshold voltage in VTH_DBH_PD dead battery Valid VBUS detection VVALID_VBUS_PD threshold CC pin lower pull-up VLPWR_PULLUP_CC voltage RGB/Moonlight LED driver Current accuracy ILED_ACC_RGB Current matching ILED_MATCH_RGB Dropout voltage VDROP_RGB RGB_ISINK1/2/3 ILED_ISINK output current range Moonlight output ILED_ML current range Moonlight current ILED_ACC_ML accuracy Moonlight dropout VML_DROP_RGB voltage RGB supply current

ILED_ISINK_SUPPLY

Moonlight supply ILED_ML_SUPPLY current RGB timing accuracy TACC_RGB BUCK1 Turn-on overshoot Over-current IOCP1 protection (OCP)

Efficiency

MediaTek Proprietary and Confidential.

E

Test condition

Min. 64

Typ. 80

Max. 96

Unit μA

166

180

194

μA

304

330

356

μA

4.59

5.1

5.61

kΩ

Under ICHG = ICC_DFP80_PD and ICC_DFP180_PD

0.2

-

1.6

V

Under ICHG = ICC_DFP330_PD

0.8

-

2.45

V

3.5

-

4.0

V

REG 0xAB bit = 0 in low-power mode

1.8

2

2.2

V

ILED = 20 mA ILED = 20 mA ILED = 20 mA

-5 -5 -

75

5 5 150

% % mV

1

-

24

mA

5 mA/step

5

-

150

mA

ILED = 60 mA (default)

-5

-

5

%

ILED = 150 mA

-

-

200

mV

All 3 channels set to 20 mA 2 channels set to 20 mA 1 channels set to 20 mA

-

203 162 122

-

μA μA μA

Moonlight set to 100 mA

-

176

-

μA

-5

-

5

%

-

-

10

%

4

5

6

A

-

84

-

VOUT = default, no load Peak inductor current, as REG_PMIC, 0x15[2:1] = 01 VBAT = 4V, Vout = 0.8V, I_LOAD = 100 mA, L_DCR_max = 26 mΩ VBAT = 4V, Vout = 0.8V, I_LOAD = 500 mA, L_DCR_max = 26 mΩ

% -

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84.8

-

Page 26 of 201

MT6360U PMIC Datasheet Confidential A Parameter

Symbol

BUCK soft-start time tSS_BUCK Switch frequency

fOSC_BUCK

Output voltage ripple (PWM) Output voltage ripple (PFM) Load transient Line transient DC accuracy (includes line/load regulation@PWM) DC accuracy (includes line/load regulation@PFM) Output discharge switch on-resistance BUCK1 supply IBUCK1_PVIN current BUCK2 Turn-on overshoot Over-current IOCP2 protection (OCP)

Efficiency

Eff_BUCK

BUCK soft-start time tSS_BUCK Switch frequency Output voltage ripple (PWM) MediaTek Proprietary and Confidential.

fOSC_BUCK

Test condition VBAT = 4V, VOUT = 0.8V, I_LOAD = 1000mA, L_DCR_max = 26mΩ VBAT = 4V, VOUT = 0.8V, I_LOAD = 2000mA, L_DCR_max = 26mΩ VOUT = 0.55V, I2C programmable In FPWM VBAT = 3.1V, I_LOAD = 0.5 x Imax 20 MHz measurement BW VBAT = 3.1V, I_LOAD = 0.5 x Imax 20MHz measurement BW VBAT = 3.1V, I_LOAD = 0.1 to 2.06A, tr/tf = 1 μs VIN = 5 to 4.3V/3.5V to 2.8V, Vout = 0.8V, I_LOAD = 2A

Min.

Typ.

Max.

-

84.1

-

-

76.5

-

110

-

1,000

μs

2.1

2.4

2.7

MHz

-5.65% *Vo+11

-

+8%* Vo-11

mV

-5.65% *Vo+11

-

+8%* Vo-11

mV

-53

-

53

mV

-40

-

40

mV

VBAT = 3.1 to 5.0V I_LOAD = PWM load

-6

-

6

mV

VBAT = 3.1 to 5.0V I_LOAD = PFM load

-10

-

22.5

mV

-

11

-

Ω

-

4

6

μA

-

-

10

%

4

5

6

A

-

85

-

-

83

-

VBUCK1_PVIN = 4V, ILOAD = 0 mA, BUCK1_VOUT = 0.55V VOUT = default, no load Peak inductor current, as REG_PMIC, 0x25[2:1] = 01 VBAT = 4V, Vout = 1.125V, I_LOAD = 100 mA, L_DCR_max = 26 mΩ VBAT = 4V, Vout = 1.125V, I_LOAD = 500 mA, L_DCR_max = 26 mΩ VBAT = 4V, Vout = 1.125V, I_LOAD = 1,000 mA, L_DCR_max = 26 mΩ VBAT = 4V, Vout = 1.125V, I_LOAD = 2,000 mA, Vout = 1.125V I2C programmable In FPWM VBAT = 3.1V, Vout = 1.125V I_LOAD = 0 mA ~ Imax

% -

78

-

-

69

-

-

-

1,000

μs

2.1

2.4

2.7

MHz

-

1

-

%

© 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in part, is strictly prohibited.

Unit

Page 27 of 201

MT6360U PMIC Datasheet Confidential A Parameter

Symbol

Test condition 20 MHz measurement BW VBAT = 3.1V, Vout = 1.125V I_LOAD = 0 mA ~ Imax 20 MHz measurement BW VBAT = 3.1V, Vout = 1.125V I_LOAD = 0.1~0.9A, tr/tf = 1 μs VIN = 5 ~ 4.3V/3.5V ~ 2.8V, Vout = 1.125V, I_LOAD = 2A

Output voltage ripple (PFM) Load transient Line transient

Min.

Typ.

Max.

Unit

-

40

-

mVpp

-40

-

40

mV

-40

-

40

mV

DC accuracy VBAT = 3.1~5.0V -0.9 0.9 (includes line/load I_LOAD = PWM load regulation@PWM) DC accuracy VBAT = 3.1~5.0V -0.9 3 (includes line/load I_LOAD = PFM load regulation@PFM) Output discharge 11 switch on-resistance BUCK2 supply VBUCK2 = 4V, ILOAD = 0 mA, IBUCK2_PVIN 4 6 current BUCK2_VOUT = 1.125V LDO1 to 7 (LDO1: VFP/LDO2: VTP/LDO3: VMC/LDO5: VMCH/LDO6: VMDDR/LDO7: VDRAM2) max{Vo +0.35 ; 3.15} max{Vo +0.35 ; 3.15}

VLDO_VIN1

Input voltage range

VLDO_VIN2 VLDO_VIN3 VLDO_VIN3 ΔVOUT_LDO1 ΔVOUT_LDO2

Output voltage accuracy

ΔVOUT_LDO3 ΔVOUT_LDO5 ΔVOUT_LDO6 ΔVOUT_LDO7

Ioc_LDO1 Ioc_LDO2 Ioc_LDO3 Output mA Ioc_LDO5 Ioc_LDO6 Ioc_LDO7 Output short current ISHORTLIM_LDO1 limit ISHORTLIM_LDO2 MediaTek Proprietary and Confidential.

LDO7 = 1.8V/10 mA LDO6 = 0.75V/300 mA LDO7= 0.6V/600 mA VOUT = 1.8V (default) IOUT = 150 mA VOUT = 1.8V (default) IOUT = 200 mA VOUT = 3V (default) IOUT = 200 mA VOUT = 2.95V (default) IOUT = 800 mA VOUT = 0.75V (default) IOUT = 300 mA VOUT = 0.6V (default) IOUT = 600 mA

OCFB_EN = 1 OCFB_EN = 1

-

5

-

5

2

-

5

1.08

-

2

-1

-

1

-1

-

1

-1

-

1

% Ω μA

V

% -1

-

1

-1

-

1

-1

-

1

225 300 300 1,200 450 900 30 40

-

420 560 500 2,000 840 1,680 150 200

© 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in part, is strictly prohibited.

%

mA

Page 28 of 201

MT6360U PMIC Datasheet Confidential A Parameter

Symbol ISHORTLIM_LDO3 ISHORTLIM_LDO5 ISHORTLIM_LDO6 ISHORTLIM_LDO7 VDROP_LDO1/2/3/5

Dropout voltage VDROP_LDO6/7

Rated load current (I_rated)

I_LDO1 I_LDO2 I_LDO3 I_LDO5 I_LDO6 I_LDO7

PSRRLDO1/2/3/5

Power supply rejection ratio (PSRR)

PSRRLDO6/7

tSS_LDO1/2 tSS_LDO3/5 Soft-start time tSS_LDO6 tSS_LDO7 toff_LDO1/2/3/7 Power off-time

toff_LDO5 toff_LDO6

Normal mode quiescent current MediaTek Proprietary and Confidential.

IIQ_NM_LDO1/2/3/5

Test condition OCFB_EN = 1 OCFB_EN = 1 OCFB_EN = 1 OCFB_EN = 1 I_LOAD1 = 150 mA, I_LOAD2 = 200 mA, I_LOAD3 = 200 mA, I_LOAD5 = 800 mA I_LOAD6 = 300 mA, I_LOAD7 = 600 mA I_rated ≤ 150 mA I_rated ≤ 200 mA I_rated ≤ 200 mA I_rated ≤ 800 mA I_rated ≤ 300 mA I_rated ≤ 600 mA 1. I load ≤ I_rated 2. Freq = 50 Hz~1 kHz 1. I load ≤ I_rated 2. Freq = 1~10 kHz 1. I load ≤ I_rated 2. Freq = 10~100 kHz 1. I load ≤ I_rated 2. Freq = 100 kHz~1 MHz 1. I load ≤ I_rated 2. Freq = 50 Hz~1 kHz 1. I load ≤ I_rated 2. Freq = 1~10 kHz 1. I load ≤ I_rated 2. Freq = 10~100 kHz 1. I load ≤ I_rated 2. Freq = 100 kHz~1 MHz VOUT_LDO = 90% of VOUT_LDO (target) VOUT_LDO = 90% of VOUT_LDO (target) VOUT_LDO = 90% of VOUT_LDO (target) VOUT_LDO = 90% of VOUT_LDO (target) VOUT_LDO = 10% of VOUT_LDO (target) VOUT_LDO = 10% of VOUT_LDO VOUT_LDO = 10% of VOUT_LDO (target) ILOAD = 0 mA, LDO1/2/3 is from LDO_VIN1, LDO5 is from LDO_VIN2, not include base Iq.

Min. 40 160 60 120

Typ. -

Max. 200 800 300 600

-

-

350 mV

-

-

100

-

-

150 200 200 800 300 600

-

45

-

-

30

-

-

15

-

-

15

-

-

75

-

-

55

-

-

40

-

-

25

-

-

-

1,000

-

-

1,000

-

-

2,000

-

-

3,300

-

-

2,000

-

-

1,500

-

-

1,000

-

-

32

mA

dB

μs

© 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in part, is strictly prohibited.

Unit

μs

μA

Page 29 of 201

MT6360U PMIC Datasheet Confidential A Parameter

Symbol

Min.

Typ.

Max.

-

-

169

-

-

143

-

-

16

-

-

20

-

-

17.6

VIL_I2C

-

-

0.4

V

VIH_I2C

1.2

-

-

V

-

-

0.4

V μA

IIQ_NM_LDO6

IIQ_NM_LDO7

IIQ_LP_LDO1/2/3/5 Low power mode quiescent current

IIQ_LP_LDO6

IIQ_LP_LDO7 I2C characteristics LOW-level input voltage HIGH-level input voltage LOW-level output voltage Input current each I/O pin

Test condition ILOAD = 0 mA, LDO6 is from LDO_VIN2 and LDO_VIN3, not include base Iq. ILOAD = 0 mA, LDO7 is from LDO_VIN2 and LDO_VIN3, not include base Iq. ILOAD = 0 mA, LDO1/2/3 is from LDO_VIN1, LDO5 is from LDO_VIN2, not include base Iq. ILOAD = 0 mA, LDO6 is from LDO_VIN2 and LDO_VIN3, not include base Iq. ILOAD = 0 mA, LDO7 is from LDO_VIN2 and LDO_VIN3, not include base Iq.

VOL_I2C

Open-drain

IIN_I2C

0.1 × VDD < VI < 0.9 × VDD(MAX)

-10

-

10

SCL clock frequency

fSCL_I2C_HSM

CB ≤ 100 pF 100 pF ≤ CB ≤ 400 pF

Data hold time Data set-up time

tDH_I2C tDS_I2C

30 70

-

3.4 1.7 -

Unit

μA

MHz ns ns

Note 6: Guaranteed by design.

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Page 30 of 201

MT6360U PMIC Datasheet Confidential A

3

Typical Operating Characteristics

3.1

Typical Operating Characteristics Charger Efficiency vs. Charger Current 96

94

94

92

92

Charger Efficiency (%)

Charger Efficiency (%)

Charger Efficiency vs. Charger Current 96

90 88

VBUS = 5V

86

VBUS = 9V

84

VBUS = 12V

82 80 78 76

90 88

VBUS = 5V

86

VBUS = 9V

84

VBUS = 12V

82 80 78

VBAT = 3.9V, fSW = 1.5MHz

VBAT = 4.2V, fSW = 1.5MHz

76

74 0.3

0.6

0.9

1.2

1.5

1.8

2.1

2.4

2.7

0.3

3.0

0.6

0.9

Charger Current (A)

Boost Efficiency vs. Load Current

1.5

1.8

2.1

2.4

2.7

3.0

CV Regulation vs. Temperature

100

4.50

95

4.45

90

4.44V

85

VBAT = 4.35V

80

VBAT = 4V

75

VBAT = 3.8V

70

VBAT = 3.5V

CV Regulation (V)

Boost Efficiency (%)

1.2

Charger Current (A)

65

4.40 4.35 4.35V 4.30 4.25 4.20

60 4.15

55

VBUS = 5.05V, fSW = 1.5MHz 4.10

50 0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

-50

-25

0

25

50

75

100

125

Temperature (°C)

Load Current (A)

Figure 3-1. Typical operating characteristics

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Page 31 of 201

MT6360U PMIC Datasheet Confidential A

4

Application Information

4.1

General Description

The MT6360U is a highly-integrated smart power management IC, which includes a single-cell Li-ion/Li-polymer switching battery charger, a USB Type-C PD controller, dual Flash LED current sources, a RGB LED driver, two buck converters, and six LDOs for portable devices.

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Page 32 of 201

MT6360U PMIC Datasheet Confidential A

4.2

VDDA Over-Voltage Protection

The device provides VDDA over-voltage protection (VDDA OVP). If VDDA exceeds VVDDA_OVP, VDDA OVP will be triggered and the channels behavior is decided by register (0x0E[6]) of PMU. There are two options. One is that MT6360U only sends interrupt; the other is that is not only sends interrupts but also shuts down all channels except for CHG/FLED/PD and resets CHx_EN_CTRLx.

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Page 33 of 201

MT6360U PMIC Datasheet Confidential A

4.3

Over-Temperature Protection

MT6360U features over-temperature protection (OTP) and have three sensors of OTP0 (in CHG), OTP1 (in bucks) and LDO5_OTP. They can be enabled in the registers (0x0E[5],[4] and [2]). The registers (0x0E[3] and [1]) are designed to save power. When bucks/LDOs are not in normal mode, OTP1 and LDO5_OTP is forced to being turned off. The OTP can be triggered to shut down the device if the junction temperature exceeds TOTP, 150°C typically. The channels that will be turned off can be selected by register (0x0E[7]) of PMU. If the junction temperature drops below TOTP_RECOVER, 110°C typically, the device will be reactivated.

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Page 34 of 201

MT6360U PMIC Datasheet Confidential A

4.4

MRSTB Pin

The device provides a MRSTB pin to manually reset the hardware or registers. This function is enabled by register (0x01[4]) = 1 of PMU. The debounce time can be selected by 0x01 bit [3:1], and the reset method can be selected by register (0x01[0]) of PMU. The control diagram is shown below.

Phone turns on

High Level > 1.2V Low Level < 0.4V

AP’s GPIO to driver MRSTB pin

2

Enable MRSTB function and set MRSTB timeout

AP give the I C command to the MT6360U

MRSTB_TMR The MT6360U internal reset trigger

Reset trigger. All register reset to default value and MRSTB default is off

Figure 4-1. MRSTB function As Figure 4-2 shows, MRSTB can reset the PMU and PD with the register (0x01[4]) of PMU. In addition, it can reset the bucks and LDOs with register (0x06[7]) of PMU.

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Page 35 of 201

MT6360U PMIC Datasheet Confidential A

MT6360U MRSTB Diagram Reset by VDDA = 0 or ALL_RST = 1

EFUSE BASE 3MOSC

CHG FLED RGB PD

MRSTB_RST

REG_PMU0x01[4]: MREN (default = 0, disable)

MRSTB Bucks LDOs

WDTRST REG_PMU0x06[7]: WDTRST_EN (default = 0, disable)

Figure 4-2. MRSTB diagram

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Page 36 of 201

MT6360U PMIC Datasheet Confidential A

4.5

Switching Charger

The switching charger integrates a synchronous PWM controller with power MOSFETs to provide minimum input voltage regulation (MIVR), average input current regulation (AICR), high-accuracy current and voltage regulation, and charge termination. The charger also features OTG (on-the-go) boost mode. The switching charger has three operation modes, charge mode, boost mode (OTG-boost), and high-impedance mode. In charge mode, the charger supports a precision charging system for single-cell batteries. In boost mode, the charger works as a boost converter to boost the battery voltage back to the CHG_VIN pin for sourcing OTG devices. In high-impedance mode, the charger stops charging or boosting and operates at a low sinking current from the CHG_VIN pin or the battery to reduce power consumption when the device is in standby mode.

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MT6360U PMIC Datasheet Confidential A

4.6

Charger Mode Operation

4.6.1

Charge Profile

The switching charger provides a precision Li-ion or Li-polymer charging solution for single-cell applications. Input current limit, charge current, end-of-current current, charge voltage, and input voltage MIVR are all programmable via the I2C interface. In charge mode, the switching charger has five regulation loops to control charge current: input current, charge current, charge voltage, input voltage MIVR and device junction temperature. While charging a battery, all five loops (if MIVR is enabled) are enabled, but only one of them will dominate the charging behavior at a time. For normal charging operation, the switching charger starts from pre-charge mode. When the battery voltage rises above a pre-charge threshold voltage (VPRECHG_CHG), the charger enters fast-charge mode. Once the battery voltage approaches the regulation voltage (VOREG_CHG), the charger enters constant voltage mode. Charge Profile

IBAT

IBAT

(IPRECHG_CHG)

(ICHG)

VOREG_CHG

VBAT & IBAT

VBAT (VOREG_CHG - VRECH_CHG)

VBAT (VPRECHG_CHG) IBAT (IEOC_CHG)

Time Charging State

Pre-charge stage

Fast-charge stage (Constant current)

Fast-charge stage (Constant voltage)

Charge termination stage

R-eharge stage

Figure 4-3. Charge profile

4.6.2

Pre-charge Mode

To prolong battery life, the battery under low battery condition cannot be charged with a large current. When the VBAT pin voltage is below pre-charge threshold voltage (VPRECHG_CHG), the charger is in pre-charge mode and provides a weak charge current equal to a pre-charge current (IPRECHG_CHG).

There are twobattery control loops in pre d the other is the SYSREG. If the voltage is lower than the VSYS voltage, BATFET will not be fully turned on so that VSYS is not equal to VBAT. That is, VSYS can be powered by the charger-buck converter rather than the low battery, which is being charged by the pre-charge current. As a result, the system power can be guaranteed in such low battery condition. MediaTek Proprietary and Confidential.

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MT6360U PMIC Datasheet Confidential A The pre-charge current levels IPREC (0x18, bit[3:0]) are programmable from 100 mA to 850 mA in a step of 50 mA via the I2C interface.

4.6.3

Fast-Charge Mode and Settings

Once the VBAT pin rises above VPRECHG_CHG, the charger enters fast-charge mode and starts fast charging. Note that a MUIC integrates input power source detection function, from an AC adapter or USB input, and the switching charger can automatically set up the charge current with options accordingly. Different from a linear charger (LDO-based), the switching charger (buck-based) is like a current amplifier because the current sinking to the switching charger is different from the current sourcing into the battery. The average input current regulation (AICR) levels (0x13, bit[7:2]) and output charge current (ICHG) (0x17, bit[7:2]) are all user-programmable.

4.6.4

Cycle-by-Cycle Current Limit

The switching charger features an embedded cycle-by- cycle current limit for output inductor. Once the inductor current reaches the current limit, the charger stops charging immediately to prevent the device from being damaged by the over-current condition. Note the protection can be disabled in no case.

4.6.5

Charging Safety Timer

The device has built-in safety timer to prevent extended charging cycle due to abnormal battery conditions. According to the battery voltage, there are different safety time. The user can program pre-charge and fast charge safety timer through I2C (WT_PRC and WT_FC bits). When safety timer expires, the CHG_STAT bits are set to 11 and the CHG_TMRI_EVT is asserted to the host. The safety timer feature can be disabled by writing 0 to the TMR_EN bit. During AICR, MIVR or thermal regulation, the safety timer counts at half clock rate. This half clock rate feature can be disabled by writing 0 to the TMR2X_EN bit. During the fault, the charging is stopped and the buck converter continues to operate to supply system load. Once the fault goes away, fault resumes. The timer is reset by toggling CHG_EN or TMR_EN bits, replugging CHG_VIN.

4.6.6

Charge Current (ICHG)

er path on-resistance Theand ch I2Cprogrammable ICHG setting. The voltage between the VSYS and VBAT pins is regulated to the voltage controlled by the ICHG setting, and the fast-charge currents (ICHG) are I2C programmable from 300 mA to 3,000 mA with a resolution of 100 mA. MediaTek Proprietary and Confidential.

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MT6360U PMIC Datasheet Confidential A 4.6.7

Constant Voltage Mode (VOREG_CHG)

The switching charger enters constant voltage mode when the VBAT voltage approaches the output regulation voltage (VOREG_CHG). When entering this mode, the fast-charge current (ICHG) will begin to decrease. For default settings (charge current termination (IEOC) function is disabled), the charger will not be turned off and will always regulate the battery voltage at VOREG_CHG. However, if the charge current termination (IEOC) function is enabled, the charger will be turned off or battery charging is terminated when the charge current is below an end-of-charge current (IEOC_CHG) in constant-voltage mode. The output regulation voltage is I2C programmable from 3.9V to 4.71V in 10 mV steps.

4.6.8

End-of-Charge Current (IEOC_CHG)

If charge current termination (IEOC) is enabled, the end-of-charge current will be determined by the termination current sense voltage. IEOC_CHG can be set via the I2C interface from 100 mA to 850 mA in 50 mA steps. The charge mode is shown as below, and the charge mode which the charger operates in will be determined according to the VBAT level:

Trickle mode Pre-charge mode

Battery voltage level VBAT VBAT < 2V VBAT < VPREC (0x18, bit[7:4])

Fast-charge mode

VBAT < VOREG (0x14, bit[7:1])

End-of-charge mode

VBAT = VOREG (0x14, bit[7:1])

Battery charge current IBAT 100 mA IPREC (0x18, bit[3:0]) Charge current is determined by several control loops. Charge current decreases naturally.

There are four charger-related enable bits: 1. CFO_EN (0x12, bit[1]): The CFO_EN bit is used to enable or disable charge mode and boost mode of the charger. 2. CHG_EN (0x12, bit[0]): When the CHG_EN bit is disabled, the power path BATFET will be turned off so that the no charge current will go into the battery. That is, the input power source continuously delivers power to the system but does not charge the battery. However, if the system load is higher than the input source current limit, the power path BATFET will be immediately turned back on so that the battery power can help supply the system. The CHG_EN bit function is the same as that of the CHG_ENB pin. 3. HZ (0x11, bit[2]): When the HZ bit is enabled, most of the internal circuits of the charger will be turned off to reduce the quiescent current.

harger-buck will not 4. switch. Force_Sleep (0x11, bit[3]): When the Force_Sleep bit is enabled, In end-of-charge mode, if EOC_EN (0x19, bit[3]) is enabled, once the charge current is lower than IEOC (0x19, bit[7:4]) level and within CHG_TDEG_EOC (0x19, bit[2:0]), the PMIC will send out IRQB and CHG_IEOCI_EVB = 1 (0xD4, bit[7]). Then, the PMIC will start to check statuses of the following three bits. MediaTek Proprietary and Confidential.

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MT6360U PMIC Datasheet Confidential A 1. TE (0x12, bit[4]): If this bit is enabled, the power path will be turned off, and the buck of the charger will keep providing power to the system. 2. EOC_TIMER (0x17, bit[1:0]): With CHG_IEOCI_EVB = 1, the power path will not be turned off. The PMIC can keep charging the battery for 30 to 60 minutes to extend the battery charging capacity.

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MT6360U PMIC Datasheet Confidential A

4.7

OTG Mode Operation

MT6360U also supports OTG mode and enters OTG mode via OPA_MODE (0x11, bit[0]). It not only provides several output current limit protection levels but also has low battery protection for overall system considerations. MT6360U also provides UUG_ON (0x1D, bit[1]) bit, which can be applied to different applications. 1. If OTG mode and UUG_ON are enabled, the boost-mode output will be on the CHG_VIN pin, which can be used for OTG (on-the-go) mode in mobile phones. 2. If OTG mode is enabled and UUG_ON bit is disabled, the boost-mode output is on the CHG_VMID pin, which can be used in power banks. That is, adapter power can be delivered to PD-powered devices directly.

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MT6360U PMIC Datasheet Confidential A

4.8

Shipping Mode

From a manufacturer to an end user, it may take long time for products to travel. In view of this, MT6360U provides shipping mode to further minimize battery leakage. After enabling SHIP_MODE (0x12, bit[7]), MT6360U will shut down internal circuits to reduce the quiescent current. The delay time for BATFET to be turned off can be selected by BATDET_DIS_DLY (0x12, bit[6]). There are several ways to exit the shipping mode: 1. Input power source is plugged in. 2. Disable SHIP_MODE bit. 3. CHG_QONB pin is pulled from logic high to logic low within 0.9 second. 4. Enable ALL_RST (0x02, bit[7]) to reset all registers to default values.

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MT6360U PMIC Datasheet Confidential A

4.9

Power Up from CHG_VIN

When the VBUS is plugged in, the power up sequence is as below: 1. Power up CHG_VDDP. 2. CHG_VMID 3. VDDM 4. CHRDETB 5. Poor source detection 6. Input source selection: IINLMTSEL, input source type detection is based on D+/D–, CHG_ILIM. 7. Average input current regulation (AICR) 8. Minimum input voltage regulation (MIVR) 9. Buck converter power-up

4.9.1

Power up CHG_VDDP Regulation

PWM low-side driver positive supply output. Internally, CHG_VDDP is connected to the anode of the booststrap diode. If VBUS is plugged in, CHG_VDDP will be powered by CHG_VIN and regulated to 4.9V. If VBUS is unplugged, the charger will operate in sleep mode and the CHG_VDDP voltage will be 0V.

4.9.2

CHG_VMID

The connection point between the reverse-blocking MOSFET and the high-side switching MOSFET. After the VBUS is plugged in for 120 ms, it will be connected to CHG_VMID MIN by turning on UUG.

4.9.3

VDDM and VDDA

The VDDM power is from the VBAT directly or the CHG_VMID regulator output. VDDA is connected to VDDM on the PCB. VSYS Power Path Controller VBAT

VDDM

VDDM Power Selection CHG_VIN

CHG_VMID

VDDA

VDDM Regulator (4.88V)

UUG Controller

Figure 4-4. VDDM power plan MediaTek Proprietary and Confidential.

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MT6360U PMIC Datasheet Confidential A 4.9.4

CHRDETB Function

Detect the VBUS and CC1/CC2 state for power-on conditions. UVLO < VBUS < OVP or CC attached  CHRDETB = LOW VBUS < UVLO/VBUS > OVP and CC detached  CHRDETB = HIGH

Table 4-1. CHRDETB status CHRDETB status CC attached CC detached

VBUS < UVLO L H

UVLO < VBUS < OVP L L

VBUS > OVP L H

UVLO threshold = 2.6~3.7V, 100 mV per step OVP threshold = 6/6.5/7/7.5/8.5/9.5/10.5/11.5/12.5/14.5V

4.9.5

Poor Source Detection

After CHG_VDDP is powered up, the device checks the current capability of the input source. The input source has to meet the following requirements to turn on the buck.  The CHG_VIN voltage is below VCHG_VIN_OVP.  The CHG_VIN voltage is above VBAD_ADP_CHG pulling IBAD_ADP_SINK_CHG (typical 50 mA). Once the CHG_VIN source passes all of above conditions, the status register bit PWR_RDY is asserted high and the INT pin signals the master. If the device does not pass the poor source detection, the poor source detection is repeated every two seconds.

4.9.6

Input Source Selection

The host can over-write ILIM_EN or the IINLMTSEL register to change the input current limit if needed.

4.9.6.1

IINLMTSEL

This flexible setting is suitable for wide applications of adapters: 1) If IINLMTSEL = 00, the input current limit is decided by the lower one of IAICR = 3.25A and the current limit is set by the CHG_ILIM pin. 2) If IINLMTSEL = 01, the input current limit is decided by the lower one of CHG_TYP results and the current limit is set by the CHG_ILIM pin. 3) If IINLMTSEL = 10, the input current limit is decided by the lower one of IAICR register value and the current limit is set by the CHG_ILIM pin. 4) If IINLMTSEL = 11, the input current limit is decided by the lower one of IAICR = 3.25A, the CHG_TYP, IAICR register value and the current limit is set by the CHG_ILIM pin. MediaTek Proprietary and Confidential.

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MT6360U PMIC Datasheet Confidential A 4.9.6.2

Input Source Type Detection

After the CHG_VIN voltage is above CHG_VIN UVLO, the device will run input source detection through D+/D– when the USBCHGEN bit is set. MT6360U follows the USB Battery Charging Specification 1.2 (BC1.2) to detect the input source (NSDP/SDP/CDP/DCP). After input source type detection is completed, an INT pulse will be asserted to the host. Table 4-2. Adapter detection CHG TYPE SDP CDP DCP

4.9.6.3

AICR setting 500 mA 1,500 mA 3,250 mA

CHG_ILIM

For hardware protection, the device has an additional hardware pin on ILIM to limit the maximum input current on the ILIM pin. The input maximum current is set by a resistor from the ILIM pin to ground as: IINMAX = KILIM/RILIM For example, if the input current limit is to be set as 2A with a typical input current limit factor KILIM as 355 A, a resistor of 180 will then be chosen as the resistor from the CHG_ILIM pin to ground. The actual input current limit is the result of smaller value between IINLMTSEL and CHG_ILIM.

4.9.7

Average Input Current Regulation (AICR)

The AICR current setting is programmed via the I2C interface. For example, AICR 100 mA mode limits the input current to 100 mA and AICR 500 mA mode to 500 mA. If not needed, this function can be disabled. The AICR current levels are in the range of 100 mA to 3,250 mA with resolution of 50 mA.

4.9.8

Minimum Input Voltage Regulation (MIVR)

The switching charger features minimum input voltage regulation function to prevent input voltage from dropping due to insufficient current provided by the adapter or USB input. If MIVR function is enabled, the input voltage will decrease when the over-current of the input power source occurs. VCHG_VIN is regulated at a pre-determined voltage level which can be set from 3.9V to 13.4V in 0.1V steps via the I2C interface. At this time, the current drawn by the switching charger equals the maximum current value that the input power can provide at the predetermined voltage level, instead of the set value.

4.9.9 After the AICR is set, the converter is enabled and starts switching. BATFET stays on unless the charger is disabled (CHG_EN = 0) or enters shipping mode (SHIP_MODE = 0). MediaTek Proprietary and Confidential.

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MT6360U PMIC Datasheet Confidential A The device integrates a synchronous PWM controller with 1.5 MHz switching frequency, high-accuracy current and voltage regulation. The device also supports PFM control to improve light-load efficiency.

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MT6360U PMIC Datasheet Confidential A

4.10

MediaTek Pump Express+ (MTK, PE+)

MT6360U provides an input current pulse to communicate with an MTK-PE+ high voltage adapter. When EN_PUMPX is enabled, the host can increase or decrease adapter output voltage by setting PUMPX_UP_DN to the desired value. After enabling either one of them, MT6360U will generate a CHG_VIN current pattern for the MTK-PE+ adapter to automatically identify whether to increase or decrease the output voltage (CHG_VIN pin). Once the current pattern generation is finished, IRQB will be triggered accordingly to request the processor to read the registers.

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MT6360U PMIC Datasheet Confidential A

4.11

Interrupt

MT6360U reports status to host (CPU, MCU, EC, etc.) by the IRQB (interrupt command to host) pin, which is an open-drain output. The IRQB pin goes low when any fault occurs. It will be automatically reset when all the fault events are cleared. The IRQB pin is used to indicate whether MT6360U has any PMU, PMIC, LDO events. If an application processor (AP) detects a falling edge on the IRQB pin, the AP will start to read the IRQB registers 0xD0 through 0xDF sequentially.

INT_RETRIGGER

INT_RET

16/32/64/128µs

STAT# Write Clear EVT#

IRQB

Figure 4-5. IRQB pin diagram

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MT6360U PMIC Datasheet Confidential A

4.12

CHG_VBATOVPB Pin

Battery over-voltage protection (BAT OVP) indication is accomplished by the open-drain and active-low output, CHG_VBATOVPB: It will be low if BAT OVP occurs; otherwise, it will be high.

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MT6360U PMIC Datasheet Confidential A

4.13

Analog IR Drop Compensation

The resistance between the charger output and the battery cell terminal may cause the charger to enter constant voltage operation mode from constant current operation mode too early and thus increase the battery charging time. To reduce the battery charging time to speed up the charge cycle, MT6360U provides IR compensation function so that the charger has more precise control over the timing that the charger operates in constant current mode, which has the maximum charge current. The host (AP) can set up IR compensation function by programming the register bits BAT_COMP (0x2C, bit[5:3]) and VCLAMP (0x2C, bit[2:0]). The formula is as below: VACTUAL = V + min. (ICHG (Actual) × BAT_COM, VCLAMP)

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MT6360U PMIC Datasheet Confidential A

4.14

CHG_ILIM Pin

For hardware protection, MT6360U supports input current limit setting on the CHG_ILIM pin by way of a resistor from CHG_ILIM pin to ground. IINMAX = KILIM/RILIM For example, if the input current limit is to be set as 2A with a typical input current limit factor KILIM as 355 AΩ, a resistor of 180Ω will then be chosen as the resistor from the CHG_ILIM pin to ground. The actual input current limit is the result of smaller value between IINLMTSEL (0x12, bit[3:2]) and CHG_ILIM.

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× 2.5 mV × 1.25 mV

MT6360U PMIC Datasheet Confidential A

4.15

ADC Conversion Operation Flow

The figure below shows the flow chart of ADC conversion operation. The ADC conversion starts from selecting an ADC channel by setting up ADC_RPT_SEL (0x5A,[7:4]) and ADC_CHx_EN (0x56, bit[2:0] and 0x57, bit[7:0]). After about 26 ms of ADC conversion time for one channel conversion to be completed, ADC_DONEI (0xD5, bit[4]) will be enabled. The host can be informed that ADC conversion is completed by reading the register bits.

ADC Conversion Starts

Set ADC channel ADC_RPT_SEL(0x5A[7:4]), ADC_CHx_EN (0x56, bit[2:0]) & (0x57, bit[7:0]) and Start ADC conversion

Check ADC conversion complete ADC_DONEI (0xD5, bit4) = 1

Read ADC code ADC_PRT_CH (0x5A[3:0]), ADC_RPT_H (0x5B[7:0]), ADC_RPT_L (0x5C[3:0]) and Calculate measurement

Finish ADC Conversion

Figure 4-6. ADC conversion operation flow The host can read the ADC channel from ADC_RPT_CH (0x5A,[3:0], ADC high-byte codes from ADC_RPT_H (0x5B, bit[7:0]) and low-byte codes from ADC_RPT_L (0x5C, bit[7:0]) to calculate the measured voltage/current/temperature data with respect to each ADC channel. The table below shows measurement equations for various ADC channels. ADC channel CHG_VIN_DIV5 CHG_VIN 1V ~ VDDA × 2 VBAT0V ~ VDDA VSYS IBUS IAICR[7:2] setting < 400 mA MediaTek Proprietary and Confidential.

Measurement equation [(ADC_CODEH × 256) + ADC_CODEL] × 6.25 mV

Measurement range 1~22V

[(ADC_CODEH × 256) + ADC_CODEL] × 1.25 mV

0V ~ VDDA

[(ADC_CODEH × 256) + ADC_CODEL] × 2.5 mA × 0.76 © 2020 MediaTek Inc. All rights reserved.

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0~0.4A Page 53 of 201

MT6360U PMIC Datasheet Confidential A ADC channel

Measurement equation

IBUS IAICR[5:0] setting ≥ 400 mA IBAT ICHG[5:0] setting ≥ 300 mA TEMP_JC VREF_TS TS USB_ID

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Measurement range

[(ADC_CODEH × 256) + ADC_CODEL] × 2.5 mA

0~5A

[(ADC_CODEH × 256) + ADC_CODEL] × 2.5 mA

0~3A

[(ADC_CODEH × 256) + ADC_CODEL] × 1.05~80°C [(ADC_CODEH × 256) + ADC_CODEL] × 1.25 mV [(ADC_CODEH × 256) + ADC_CODEL] × 1.25 mV [(ADC_CODEH × 256) + ADC_CODEL] × 1.25 mV

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-40~120°C 0V ~ VDDA 0V ~ VDDA 0V ~ VDDA - 1.2

Page 54 of 201

MT6360U PMIC Datasheet Confidential A

4.16

USB_PD

The PD function of the MT6360U complies with USB Type-C spec revision 1.2, PD spec revision 3.0 version 1.1 and Type-C Port Controller Interface spec revision 1.0 version 1.2. Some “not supported” functions are listed in the register table.

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MT6360U PMIC Datasheet Confidential A

4.17

Type-C Detection

The USB_PD implements multiple comparators which can be used by software to determine the state of the PD_CC1, PD_CC2 pins. This status information provides the host processor all of the information required to determine attach and detach status of the cable. USB_PD has three threshold comparators which match the USB Type-C specification for the three charge current levels and can be detected by a Type-C device. These comparators can automatically trigger interrupts to occur when there is a state change.

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MT6360U PMIC Datasheet Confidential A

4.18

Detection through Autonomous DRP Toggles

USB_PD is capable of performing autonomous DRP toggles. In DRP toggles, MT6360U implements DRP toggle between SRC (source) and SNK (sink). It also presents as a SRC or SNK only and monitors PD_CC1, PD_CC2 status.

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MT6360U PMIC Datasheet Confidential A

4.19

PD Protocol Communication

The Type-C connectors allow USB power delivery (PD) to communicate over the connected PD_CCx pins between two ports. The communication method is the BMC power delivery protocol. Possible usages are as below:  Negotiating and controlling power levels  Alternate mode interfaces, such as display port  Role swap for dual-role ports, switchable between as the source or sink  Communication with USB Type-C full featured cables USB_PD integrates a BMC PD block which includes a BMC physical layer and packet buffer. This allows packets to be sent and received by host software through I2C. USB_PD allows host software to implement all features of the USB BMC PD through writes and reads of the buffer and control of the USB_PD physical interface.

Table 4-3. USB PD abbreviations Term BMC TCPC TCPCI TCPM

Description Biphase mark coding Type-C port controller Type-C port controller interface Type-C port manager

Type-C Port Manager Policy Engine Protocol Layer INT_N In

I2C Master

TCPC Interface

INT_N Out

I2C Slave

Tx/Rx Buffer GoodCRC/Retry Physical Layer

Type-C Port Controller

Figure 4-7. Type-C port controller (TCPC) interface MediaTek Proprietary and Confidential.

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MT6360U PMIC Datasheet Confidential A The Type-C port controller interface, TCPCI, is the interface between a Type-C port manager and a Type-C port controller.  The controller interface uses the I2C protocol.  TCPM is the only master on this I2C bus.  TCPC is a slave device on this I2C bus.  TCPC supports fast-mode bus speed.  TCPC has an open-drain output, active-low PD_IRQB pin. This pin is used to indicate change of state, where the PD_IRQB pin is asserted when any alert bits are set.  TCPCI supports I/O nominal voltages of 1.8V and 3.3V.  TCPC supports auto-increment of the I2C internal register address for the last byte transferred during a read, independent of an ACK/NACK from the master.

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MT6360U PMIC Datasheet Confidential A

4.20

FLED Flow Chart

MT6360U provides torch mode and strobe mode operation for FLED applications. The torch mode power is supplied by the battery directly, and the strobe mode power is supplied by the battery operating in OTG mode. There are two power switches to select the power loop. In torch mode, FL_VINTORCH is turned on to connect to the battery. In strobe mode, the CHG_VIN voltage is detected avoiding the high voltage stress to turn on the FLED. The charger operates in OTG mode to provide the power in strobe mode.

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MT6360U PMIC Datasheet Confidential A

FLED OFF

No

TORCH Enable?

STROBE Enable?

No

( GPIO : FL_STROBE=0 1 or FL_STROBE_reg=0 1)

( GPIO : FL_TORCH=1 or FL_TORCH_reg=1)

Yes Yes

Yes CHG_VIN  5.6V ?

No

Turn ON FL_VINTORCH

Turn ON FL_VMID

Turn ON FLED_OTG

No CHG SSEND = 1

Yes Turn ON FLED Current Source Turn ON FLED Current Source No

STROBE Enable? Yes

No STROBE Timeout?

Yes TORCH Disable? No

Turn OFF FLED_OTG

Yes

Turn OFF FLED Current Source

Turn OFF FLED Current Source

Turn OFF

Turn OFF

FL_VMID

Figure 4-8. FLED flow chart

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MT6360U PMIC Datasheet Confidential A

4.21

Strobe Mode Operation

MT6360U provides 117 different current levels from 25 mA to 750 mA in steps of 6.25 mA or 50 mA to 1,500 mA in steps of 12.5 mA in strobe mode. FLED1 and FLED2 strobe currents can be programmed by register 0x74[6:0] and register 0x78[6:0] for flash brightness. The two channels support up to2.5A. The following figure shows that when the strobe target current is higher than timeout current level, it will be terminated by the strobe timeout period to elapse. FLED will be turned off completely after the strobe timeout set by register 0x73[6:0] for strobe LED1 and LED2. If the strobe target current is lower than timeout current level, it will keep lighting even when the timeout is finished.

FL_STROBE FLCS1_EN (REG0x7E[1]) FLCS2_EN (REG0x7E[0]) FL_LEDCS1 (Current) FL_LEDCS2 (Current)

FLED_STRB_TO

FLED_STRB_TO

FLED_STRB_TO FL_LEDCS2 off when FLCS2_EN low

Note: If FLCS1_EN/FLCS2_EN = 0, FLED will not be turned on even when FL_STROBE is enabled.

Figure 4-9. FLCS1_EN and FLCS2_EN (FL_STROBE)

FL_STROBE_reg reset to “0” when FLED_STRB_TO finish FL_STROBE_reg FLCS1_EN (REG0x7E[1]) FLCS2_EN (REG0x7E[0]) FL_LEDCS1 (Current) FL_LEDCS2 (Current)

FLED_STRB_TO

FLED_STRB_TO

FLED_STRB_TO FL_LEDCS2 off when FLCS2_EN low

Note: If FLCS1_EN/FLCS2_EN = 0, FLED will not be turned on even when FL_STROBE register is set to 1.

Figure 4-10. FLCS1_EN and FLCS2_EN (FL_STROBE_reg)

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MT6360U PMIC Datasheet Confidential A

4.22

Torch Mode Operation

MT6360U provides 31 different current levels from 25 mA to 400 mA in steps of 12.5 mA. FLED1 and FLED2 torch currents can be programmed by reg0x75[4:0] and reg0x79[4:0] for torch brightness. Once the torch mode is enabled, the current sources will ramp up to the programmed torch current.

FL_TORCH FLCS1_EN (REG0x7E[1]) FLCS2_EN (REG0x7E[0]) FL_LEDCS1 (Current) FL_LEDCS2 (Current)

Note: If FLCS1_EN/FLCS2_EN = 0, FLED will not be turned on even when FL_TORCH is enabled.

Figure 4-11. FLCS1_EN and FLCS2_EN (FL_TORCH)

FL_TORCH_reg FLCS1_EN (REG0x7E[1]) FLCS2_EN (REG0x7E[0]) FL_LEDCS1 (Current) FL_LEDCS2 (Current)

Note: If FLCS1_EN/FLCS2_EN = 0, FLED will not be turned on even when FL_TORCH register is set to 1.

Figure 4-12. FLCS1_EN and FLCS2_EN (FL_TORCH_reg)

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MT6360U PMIC Datasheet Confidential A

4.23

FL_TXMASK Function

The strobe current setting can be changed to torch current level setting by reg0x75[4:0] and reg0x79[4:0] when the FL_TXMASK pin goes high during strobe operation. It can release the current from torch to strobe when FL_TXMASK pin goes low within the timeout period.

FL_STROBE FL_TXMASK Current Level (FLED_ISTRB) Current Level (FLED_ITOR)

FL_LEDCS# (Current)

Note: TXActiveLevel = 1, TXSEL ≠

Figure 4-13. FL_TXMASK function

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MT6360U PMIC Datasheet Confidential A

4.24

FLED Short Protection

The device features a built-in protection against flash LED failures result from short-circuit. When the FL_LEDCS1 or FL_LEDCS2 voltage is lower than 1V, the current source will be clamped to 320μA to prevent the overload issue.

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MT6360U PMIC Datasheet Confidential A

4.25

Input Capacitor Selection

Input ceramic capacitor of 4.7 μF is recommended for the FL_VMID pin. For better voltage filtering, ceramic capacitor with low ESR is recommended. The best performance of the flash LED can be achieved by using the capacitor of large capacitance. X5R and X7R types are suitable because of their wider voltage and temperature ranges.

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4.26

FLED Strobe Mode Supply Limit

When the adapter supply power is higher than VOVP_STRB_FL (typ. 5.6V), the flash LED will not work to protect the internal circuit.

FL_STROBE or FL_STROBE_reg

TA Plug (CHG_VIN  5.6V) FL_LEDCS (Current)

Figure 4-14. CHG_VIN ≥ 5.6V strobe case

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4.27

Low Battery Voltage Protection (LBP)

When the battery voltage is lower than a specified value, FLED will be turned off. Until the battery voltage rises above the low battery voltage protection threshold plus hysteresis voltage value, FLED resumes turn-on. The low battery voltage protection can be programmed with register 0x1A[7:4] for 16 different levels (2.7V to 3.8V, 0.1V step).

4.27.1

Charger Adapter (CHG_VIN < VOVP_STRB_FL (typ. 5.6V)) Plug In/Out

If a charger power input VCHG_VIN < VOVP_STRB_FL (typ. 5.6V) is plugged in/out, the flash LED current sources will operate the same as described. Figure 4-15. Torch case (CHG_VIN < 5.6V) and Figure 4-16. Strobe case (CHG_VIN < 5.6V) show the torch mode and strobe mode respectively.

FL_TORCH or FL_TORCH_reg

TA Plug (CHG_VIN < 5.6V) FL_LEDCS (Current)

Figure 4-15. Torch case (CHG_VIN < 5.6V)

FL_STROBE or FL_STROBE_reg

TA Plug (CHG_VIN < 5.6V) FL_LEDCS (Current)

Timeout

Figure 4-16. Strobe case (CHG_VIN < 5.6V)

4.27.2

Charger Adapter (CHG_VIN ≥ 5.6V) Plug In/Out

When the charger adapter (CHG_VIN ≥ 5.6V) is plugged in, it does not affect the FLED operation with torch mode, and the FLED output current will be interrupted immediately with flash mode for protection.

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MT6360U PMIC Datasheet Confidential A FL_ TORCH or FL_ TORCH_reg

TA Plug ( CHG_VIN  5.6V) FL_LEDCS (Current)

Figure 4-17. Torch case (CHG_VIN ≥ 5.6V)

FL_STROBE or FL_STROBE_reg

TA Plug (CHG_VIN  5.6V) FL_LEDCS (Current)

Figure 4-18. Strobe case (CHG_VIN ≥ 5.6V)

4.27.3

FLED Operation with Charger in OTG Mode

The CHG_VMID voltage level will change from strobe mode setting to OTG setting when the OTG function is enabled. FL_ TORCH or FL_ TORCH_reg

CHG_ OTG

FL_LEDCS (Current)

VOBST

CHG_ VMID

Figure 4-19. Torch case with OTG FL_ STROBE or FL_ STROBE_reg

CHG_ OTG

Timeout

(Current)

VOBST CHG_ VMID

V_FL

Figure 4-20. Strobe case with OTG MediaTek Proprietary and Confidential.

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MT6360U PMIC Datasheet Confidential A

4.28

FLED Power Control

See below for the block diagram of FLED power control. In strobe mode, the power goes through M3 and M4 from M1 to drive FLED. In torch mode, the power goes through M3 from M2 to drive FLED. The driver features discharge function. When FLED is disabled, R_disch can be selected by pulled_low_R[0]. FL_VINTORCH (PIN), AMR = 6V M2

FL_VMID (PIN), AMR = 22V

Power Select M1

Strobe on Torch on Ultra_ISTRB1 [0] *2

Power MOS Select

Open/Short M4 M3

Power MOS Driver 1:1

FL_LEDCSX (PIN)

FLEDX Driver 2.5k

20k 

Pulled Low R CTRL

Pulled_LOW_R [0]

*2 : default short Torch on, open Strobe on, short Strobe on and Ultra_ISTRB1 = 1, open

Figure 4-21. FLED power control block diagram

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MT6360U PMIC Datasheet Confidential A

4.29

FLED Core Control

See below for the flow chart of FLED core control. The FLED driver can be enabled by either FL_STROBE (PIN) or FL_STROBE_reg [0], and it is the same when the IC is in FL_TORCH mode. The current level is selected by FLEDX_ISTRB[6:0] and FLEDX_ITOR[4:0]. FLEDX_ISTRB[6:0] FLEDX_ITOR[4:0]

FLEDX_TCL[2:0]

FLED_STRB_LES [0]

Current Level Comparator

Input PIN CTRL

FL_STROBE (PIN)

FLEDX Driver Strobe on Time Out CTRL *1

FL_STROBE_reg [0] FLCSX_EN [0]

FLED Current CTRL

Torch on

FL_TORCH_reg [0] FLED_STRB_TO[6:0] FL_TORCH (PIN)

TXCTRL[1:0] TXSEL[1:0] FL_TXMASK (PIN)

TX CTRL

*1 : Time Out CTRL is only for strobe turned on. Torch turned on is without time out setting.

Figure 4-22. FLED core control block diagram

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MT6360U PMIC Datasheet Confidential A

4.30

RGB LED Driver

MT6360U integrates a three-channel RGB LED driver, designed to provide a variety of lighting effects for mobile device applications. The RGB LED driver includes a smart LED string controller, and it can drive three channels of LEDs with a sink current of up to 24 mA. The default setting of RGB_ISINK1 is auto mode for CHG_VIN power good indicator, and RGB_ISINK1 also supports software mode. It provides three operation modes for the RGB LEDs: flash mode, breath mode, and register mode. The device can increase or decrease the brightness of the RGB LEDs upon command via the I2C interface. To VSYS

RGB_ISINK1 RGB_ISINK2 RGB_ISINK3 RGB_PGND

RGB Driver

Figure 4-23. RGB LED driver application circuit

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MT6360U PMIC Datasheet Confidential A

4.31

Flash Mode

MT6360U features a built-in flash mode control by setting ISINKx_DIM_MODE to register 0x81/82/83 [7:6] = 00. RGB_ISINK1 to RGB_ISINK3 of MT6360U provide up to 24 mA per string. There are 13 steps of LED current control which are set by ISINKx_CUR_SEL for each channel. The on/off of the current source is synchronized to the PWM signal. The frequency of LED current is equal to the PWM input signal that is set by ISINKx_DIM_FSEL. In order to guarantee the PWM resolution, the dimming frequency has to be operated at range of 0.125 Hz to 256 Hz selected by ISINKx_DIM_FSEL.

…

24 mA

4 mA

Current

2 mA 1 mA 0 mA

Time Frequency Duty 256 steps

Figure 4-24. RGB flash mode operating principle

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4.32

Breath Mode

In the breath mode, the three channels of MT6360U provide up to 24 mA per string. There are 13 steps of LED current control which are set by register ISINKx_CUR_SEL for each channel. In order to provide a smooth breath mode, there are six period timings to control the rising time and falling time, and it is controlled by setting up register ISINKx_VREATH_TON_SEL, BISINKx_BREATH_TOFF_SEL, BISINKx_BREATH_Trx_SEL and ISINKx_BREATH_Tfx_SEL.

In breath mode, the sink current works like PWM output with 256 Hz and controls the duty which is similar to the breath up and down. See Figure 4-25. RGB breath mode operating principle, when the duty cycle increases, the current increases, and vice versa. The human eyes filter the PWM current with the frequency that is higher than 100 Hz.

…

24 mA

IRGB

4 mA 2 mA 1 mA 0 mA

Time tOFF

tr1

tr2

tON

tf1

tf2

…

24 mA

IRGB (After eye filter)

4 mA

Current

2 mA 1 mA 0 mA

Time tOFF

tr1

tr2

tON

tf1

tf2

Figure 4-25. RGB breath mode operating principle

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MT6360U PMIC Datasheet Confidential A

4.33

Register Mode

MT6360U features a built-in register mode control by setting ISINKx_DIM_MODE to 1X. The register ISINKx_SFSTR_EN controls the soft-start time on/off. If ISINKx_SFSTR_EN is enabled, ISINKx_SFSTRx_TC can select soft-start time for the each step. The three channels of MT6360U provide up to 24 mA per string. There are 13 steps of LED current control which are set by register ISINKx_CUR_SEL for each channel.

…

24 mA

4 mA

Current

2 mA 1 mA 0 mA

Time

Figure 4-26. RGB register mode operating principle

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MT6360U PMIC Datasheet Confidential A

4.34

Low Dropout Regulator (LDOs) and Application Reference Table 4-4. LDO types and brief specifications

Type

LDO name

DLDO DLDO DLDO DLDO SLDO SLDO

LDO1 LDO2 LDO3 LDO5 LDO6 LDO7

Input power domain VSYS VSYS VSYS VSYS VDRAM1 VDRAM1

Controller power domain VSYS VSYS VSYS VSYS VSYS VSYS

Output voltage (V) 1.8V 1.8V 3.0V 2.95V 0.75V 0.6V

Imax (mA) 150 mA 200 mA 200 mA 800 mA 300 mA 600 mA

Application Finger print Touch panel MSDC SD card VMDDR DRAM

Table 4-5. LDO output voltage table Circuit Type

Name LDO1 LDO2

LDO

LDO3 LDO5 LDO6 LDO7

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Output Voltage (V) 1.8/2.0/2.1/2.5/2.7/2.8/2.9/ 3.0/3.1/3.3 1.8/2.0/2.1/2.5/2.7/2.8/2.9/ 3.0/3.1/3.3 1.8/2.8/2.9/3.0/3.3 2.9/3.0/3.3 0.75/NA (by HW trapping) 1.8/0.6/NA (by HW trapping)

Boot Default (V)

IOUT-MAX (mA)

Expected Use

OFF (1.8)

150

Fingerprint

OFF (1.8)

200

Touch Panel

OFF (3.0) OFF (3.0)

200 800

SD Card SD Card

ON/OFF (0.75/NA)

300

EMI_VMDDR

ON/ON/OFF (1.8/0.6/NA)

600

EMI_VDDQ

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MT6360U PMIC Datasheet Confidential A

4.35

SD_CARD_DET_N Pin

The device provides a SD_CARD_DET_N pin to detect an SD card removal with a micro-SD socket. This function is enabled by 0x0c bit [6] = 1 and the active level can be selected by 0x0c bit[7]. When SD card is removed, this pin will disable LDO5.

Active High LDO5

SDCARD_DET_N

Active Low LDO5

SDCARD_DET_N

Figure 4-27. SD_CARD_DET_N function

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MT6360U PMIC Datasheet Confidential A

I2C Interface

4.36

The following table shows the MT6360U unique address as a PMU, PMIC, LDO or PD slave to AP, respectively.

Table 4-6. Slave address list PMU slave address LSB R/W bit 0 1/0 PMIC slave address LSB R/W bit 0 1/0 LDO slave address LSB R/W bit 0 1/0 PD slave address LSB R/W bit 0 1/0

MSB 011010 MSB 001101 MSB 110010 MSB 100111

R/W 69/68 R/W 35/34 R/W C9/C8 R/W 9D/9C

The I2C interface also supports high-speed (HS) mode for data transfer rate up to 3.4 Mbits. See below for the I2C timing diagrams: Read N bytes from the MT6360U Slave Address

Register Address

S

0

Slave Address

A

MSB

A Sr

1

MSB

A Data for Address = m

Data 2

LSB

MSB

Data N

LSB A

A

S

Register Address 0

R/W

A

MSB

Data 1

LSB

A Assume Address = m

P

Data for Address = m + N - 1

Data for Address = m + 1 Write N bytes to the MT6360U Slave Address

LSB

A

Assume Address = m

R/W

Data 1

MSB

Data 2

LSB

A Data for Address = m MSB

A Data for Address = m + 1

Data N

LSB A

P

Data for Address = m + N - 1 Driven by Master,

Driven by Slave, P Stop,

S Start,

Sr Repeat Start

Figure 4-28. I2C timing diagrams

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MT6360U PMIC Datasheet Confidential A

4.37

Thermal Considerations

The junction temperature should never exceed the absolute maximum junction temperature TJ(MAX), listed under absolute maximum ratings, to avoid permanent damage to the device. The maximum allowable power dissipation depends on the thermal resistance of the IC package, the PCB layout, the rate of surrounding airflow, and the difference between the junction and ambient temperatures. The maximum power dissipation can be calculated using the following formula: PD(MAX) = (TJ(MAX) - TA)/JA where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and JA is the junction-toambient thermal resistance. For continuous operation, the maximum operating junction temperature indicated under recommended operating conditions is 125°C. The junction-to-ambient thermal resistance, JA, is highly package dependent. For a WL-CSP-103B 4.64x4.14 (BSC) package, the thermal resistance, JA, is 21.3°C/W on a standard JEDEC 51-7 high effective-thermal-conductivity four-layer test board. The maximum power dissipation at TA = 25°C can be calculated as below: PD(MAX) = (125°C - 25°C)/(21.3°C/W) = 4.69W for a WL-CSP-103B 4.64×4.14 (BSC) package. The maximum power dissipation depends on the operating ambient temperature for the fixed TJ(MAX) and the thermal resistance,JA. The derating curves in Figure 4-29. Derating curve of maximum power dissipation allows the designer to see the effect of the rising ambient temperature on the maximum power dissipation.

Maximum Power Dissipation (W)1

5.0 Four-Layer PCB 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0

25

50

75

100

125

Ambient Temperature (°C)

Figure 4-29. Derating curve of maximum power dissipation

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4.38

Layout Considerations

The PCB layout is an important step to maintain the high performance of MT6360U. Both the high current and the fast switching nodes demand full attention to the PCB layout to save the robustness of MT6360U through the PCB layout. Improper layout might show the symptoms of poor line or load regulation, ground and output voltage shifts, stability issues, unsatisfying EMI behavior or worsened efficiency. For the best performance of MT6360U, the following PCB layout guidelines must be strictly followed.  Keep the main power traces as wide, short and two layers as possible.  Directly connect the output capacitors to the remote sense network of each channel to avoid bouncing caused by parasitic resistance and inductance from the PCB trace.  Place input capacitor as close as possible to PMID pin and GND pin connections and use shortest copper trace connection or GND plane.  Place the output capacitor close to the inductor and the IC. Ground connections need to be tied to the IC ground with a short copper trace connection or GND plane.  Place the inductor input terminal as close to the LX pin as possible. Minimize the copper area of this trace to lower electrical and magnetic field radiation but make the trace wide enough to carry the charging current.  The via size and number should be enough for a given current path.  Decoupling capacitors should be placed next to the IC pins and make trace connection as short as possible.

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MT6360U PMIC Datasheet Confidential A

5

Functional Description

5.1

General Description CHG_VDDP

Charger / USB PD / FLED CHG_VMID

CHG_VIN VDDA

CHG_BOOT

LDO PD_VDDA

PD_VBUS

PD_VCONN5V

UUG Controller

PD_VBUS

Programmable USB Type-C PD Controller

CHG Protection

Charger/OTG Controller

CHG_VLX

CHG H/L Driver

PD_CC1 PD_CC2 CHG_PGND

PD_IRQB DP BC 1.2

DN

FL_VMID

VBATS

FL_VINTORCH

VBATS_GND

CHRDETB

CHG State Machine

FLED Controller CHG_ENB CHG_ILIM

FL_LEDCS1

CHG_QONB

FL_LEDCS2 FL_TORCH

CHG_VDDA

FL_STROBE VBAT

FL_TXMASK

CHG_VMID

VSYS VDDA ADC VDDM

VDDA Regulator

Power Path Controller

Silicon Temp Detection

VBAT BASE

AGND

TS Detector

VREF_TS TS

SCL

I2C

SDA

RGB Driver RGB Current Stage

TOP_CTRL

RGB_ISINK1 RGB_ISINK2 RGB_ISINK3 MT_ISINK

RGB Control EN FAULTB EN CTRL

RGB PWM RC

MRSTB

RGB_PGND

IRQB SDCARD_DET_N

LDO5

SRCLKEN_0 PREG HW_TRAPPING UVLO_SEL

USB_ID

RDET

LDOx (x=1~3)

LDO_VIN2

LDOx_VOUTS

LDO_VIN1 VREF

USB_ID VREF

P-Type LDOx LDO5_VOUT

VFB

LDOx_VOUT

BUCKx

BUCKx_VIN

LDO6 LDO7

H/L Driver

BUCKx_LX

Buck Control

VREF

BUCKx_PGND

PWM Logic

N-Type LDO7 Core

LDO_VIN3

LDO6_VOUT LDO7_VOUT

BUCKx_VOUT VREF

BUCKx_RSGND

Figure 5-1. MT6360U functional block diagram

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MT6360U PMIC Datasheet Confidential A Table 5-1. Control pin description Part

Pin name

Pin description

Pin type

I2C controlled

Input/ActiveManual reset input for hardware low (default: reset. disable) I2C interface serial data input/output. Open-drain. An Input/Output/ SDA external pull-up resistor is Open-drain required. I2C interface serial clock input. Input/Output/ SCL Open-drain. An external pull-up Open-drain resistor is required. Interrupt output, active-low Output/OpenIRQB open-drain, to request the drain processor to read the register Interrupt output, active-low Output/OpenPD_IRQB open-drain, to request the drain processor to read the register Input/ActiveCHG_ENB Charger enable input, active-low low Battery over-voltage protection (BAT OVP) indication, open-drain and active-low output: will be low if BAT OVP occurs; otherwise, it is high. Output/OpenCHG_VBATOVPB Battery over-voltage protection drain (BAT OVP) indication. It is an open-drain and active-low output. Will be low if BAT OVP occurs; otherwise, it is high. Internal BATFET enable control input. In shipping mode, CHG_QONB is pulled low for the Input/ActiveCHG_QONB duration of tQONB_EXIT_SHIP_CHG low (typical 0.9s) to exit shipping mode. Flash LED torch mode enable Input/ActiveFL_TORCH Input high Flash LED strobe mode enable Input/ActiveFL_STROBE input high Configurable power amplifier synchronization input or configurable active-high torch Input/ActiveFL_TXMASK mode enable. Connect an internal pull-down resistor of 400 kΩ between FL_TXMASK and ground. MRSTB

Top

Charger

Flash

h (default)

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Yes

Pin connection suggestion when unused

Floating

Yes

Yes

No

No

Floating

Yes

Tie to ground to enable charger.

No

Floating

No

Floating

Yes

Short to ground

Yes

Short to ground

No

Short to ground

Page 82 of 201

MT6360U PMIC Datasheet Confidential A Table 5-2. Setting instructions for unused channels Unused part

Unused function

Unused pin name

Input current limit setting Charger

PD

D+/D- detection All functions

All functions Flash

LDO

RGB

Channel 1 only Channel 2 only LDO1 LDO2 LDO3 LDO5 Channel 1 only Channel 2 only Channel 3 only Moonlight

CHG_ILIM D+ DCC1 CC2 PD_VCONN5V FL_VINTORCH FL_VMID FL_LEDCS1 FL_LEDCS2 FL_TORCH FL_STROBE FL_TXMASK FL_LEDCS1 FL_LEDCS2 LDO1_VOUT LDO2_VOUT LDO3_VOUT LDO5_VOUT RGB_ISINK1 RGB_ISINK2 RGB_ISINK3 ML_ISINK

Pin connection (short to ground/floating/others) Short to ground Floating Floating Floating Floating Short to ground Short to VSYS Short to VMID Floating Floating Short to ground Short to ground Short to ground Floating Floating Floating Floating Floating Floating Floating Floating Floating Floating

Table 5-3. BOM list Reference

Q'ty

Part number

PESD4V0Z1BCSF AZ5315-02F ESD5681N15 ESD56151W04 ESD56201D04 PTVSHC3D4V5B

Description TVS diode (for surge 100V/200V/300V/450V) TVS diode (for surge 100V/200V/300V/400V) TVS diode (for surge 100V/200V/300V/350V) TVS diode TVS diode TVS diode TVS diode (for surge 250V) TVS diode (for surge 200V) TVS diode (for surge 200V)

NB5565J6J8283910-F1S ESD56101D15 AZ4514-01F GRM188R6YA225KA12

TVS diode TVS diode 2.2 μF/0603/35V/X5R

ESD56241D12 D1

1

ESD5641D12 PTVSHC3N12VU

D3

1 1 1

D4

1

D2

2x1.6 D5, D6 Everlight D7, D8

2

C1, C2

2

MediaTek Proprietary and Confidential.

Package

Manufacturer

DFN 2x2

Prisemi

DFN 2x2

Willsemi

DFN 2x2

Willsemi

SOD962 DFN1006-2L DFN1006-2L SOD−323 SOD−323 DFN1006-2L

Nexperia Willsemi Willsemi Prisemi Willsemi Willsemi

DFN 1.6x1 DFN 1.6x1 0603

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Willsemi Amazing Micro MURATA Page 83 of 201

MT6360U PMIC Datasheet Confidential A Reference Q'ty Part number C3, C4 2 GRM0335C1E331GA01 C5, C9, C12 2 GRM155R60J475ME47 C6 1 GRM155R71H472KA01 C7, C8, C19, 1 GRM155R60J225ME15D C21, C22, C23 C10, C11, C14, C17, 2 GRM188R60J226MEA0 C29, C30 C15, C20 2 GRM188R61E475KE11 C16 1 GRM155R61C104KA88 C13, C18, C28 1 CL10A106MQ8NNNC C24, C25, 5 GRM033R60J105MEA2 C26, C27 TFM201610ALC-R33MTAA L1, L2 1 HMMQ20161T-R33MDR HTTK25201T-1R0MSR L3 1 CIGT252010EH1R0MNE R 6 RM02FTN2201 R1 1 RM02FTN1004 R2 1 RR0306S-6980-FNH R3 1 RM02FTN3901

Description 330 pF/0201/25V/C0G 4.7 μF/0402/6.3V/X5R 4.7 nF/0402/50V/X7R

Package 0201 0402 0402

Manufacturer MURATA MURATA MURATA

2.2 μF/0402/6.3V/X5R

0402

MURATA

22 μF/0603/6.3V/X5R

0603

MURATA

4.7 μF/0603/25V/X5R 100 nF/0402/16V/JIS 10 μF/0603/6.3V/X5R

0603 0402 0603

MURATA MURATA Samsung

1 μF/0201/6.3V/X5R

0201

MURATA

0.33 μH/2016/DCR = 20 mΩ 0.33 μH/2016/DCR = 21 mΩ 1 μH/2520/DCR = 25 mΩ 1 μH/2520/DCR = 26 mΩ 2.2k/0201/1% 1M/0201/1% 698/0201/1% 3.9K/0201/1%

2016 2016 2520 2520 0201 0201 0201 0201

TDK CYNTEC CYNTEC Samsung TA-I TA-I Cyntec TA-I

Table 5-4. Protection list Part

Protection type

Threshold (typical value)

Deglitch Protection method time Set by PMIC all bucks and VSYS < VSYS_UVLO_FALL 0x05,bit[7:6] LDOs UVLO shutdown VDDA OVP shutdown VDDA > VVDDA_OVP 32 μs selection by (0x0E, bit[6]) OTP shutdown Temperature > 150°C 0 selection by (0x0E, bit[7])

SYSUVLO

TOP

VDDA OVP

OTP

VCHG_VIN falling, VCHG_VIN - VBAT < 40 mV

Sleep mode

VIN bad adapter VCHG_VIN < 3.8V

0

32 ms

Charger CHG_VIN UVLO V

< 5.25V, CHG_VIN OVP

MediaTek Proprietary and Confidential.

VCHG_VIN < 3.15V V > 5.5V, 6.5V.11V.14.5V selection by (0x61, bit[6:5])

5 μs

Charger shutdown

Reset method VSYS > VSYS_UVLO_RISE VDDA < 5.3V Latch-off Temperature < 110°C VCHG_VIN rising, VCHG_VIN - VBAT > 100 mV

Sink 50 mA current per 2s and keep to VCHG_VIN > 3.95V check whether the adapter is good or not Charger shutdown VCHG_VIN > 3.3V CHG_VIN

0

Charger shutdown

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6.25V, 10.75V, 14.25V

Page 84 of 201

MT6360U PMIC Datasheet Confidential A Part

Protection type VBAT OVP

Threshold (typical value)

Deglitch time

VBAT/VOREG_CHG > 108%

0

Stop charging

(VBAT VOREG_CHG)/VOREG_C HG < 2%

0

Charging current is limited by thermal loop.

N/A

System OVP

Temperature > 100~120°C selection by (0x15, bit[1:0]) VSYS > 5.25V

System UVP

VSYS < 2.4V

Thermal regulation threshold

0 2 ms

> 6A ICHG_VLX > 8A selection by (0x1D, bit[2]) IOUT > 0.5~2.4A (selection by (0x1A, bit[2:0])) VCHG_VMID > 6V VBAT < 2.3~3.8V selection by (0x1A, bit[7:4]) ICHG_VLX > 3.5A, 4.5A, 5.5A or 6.5A selection by (0x1F, bit[2:1])

Protection method

Reset method

Charger shutdown Inductor peak current limit level of charger buck is half (option, 0x1D[3])

VSYS < 4.95V

Cycle by cycle current limit

ICHG_VLX < 6A ICHG_VLX < 8A

Start to hiccup

IOUT < 0.5~2.4A

Boost stop switching

VCHG_VMID < 5.8V

Leave OTG mode

VBAT > 2.7~4.2V

Cycle-by-cycle current limit

ICHG_VLX < 3.5A, 4.5A, 5.5A or 6.5A

VSYS > 2.55V

CHG_VLX

Charger-buck OCP current

OTG OLP OTG VMIDOVP OTG VBATUVP

OTG OCP

0

4 ms 0 512 μs

0

VCONN OCP

VCONN > 300 mA

6 μs

VCONN OVP

VCONN > 5.75V

6 μs

LEDCS short

VFL_LEDCSx < 1V (typ.)

PD

FL

eport only, Short_EN

2.5 ms

Strobe mode VCHG_VIN ≥ 5.6V FL-CHG_VIN OVP (typ.)

5 μs

RGB open-circuit RGB_ISINKx voltage < flag 100 mV

28 μs

RGB short-circuit RGB_ISINKx voltage > flag VSYS - 0.5V

28 μs

RGB

MediaTek Proprietary and Confidential.

VCONN OCP shutdown Clear INT (1.0x1F, selection by (0x8C, bit[1] 2.0x11, bit[7:5]) bit[1]) Clear INT (1.0x1F, VCONN shutdown bit[7] 2.0x11, bit[1]) VFL_LEDCSx > 1V FLED shutdown (typ.) VCHG_VIN ≤ 5.3V FLED shutdown (typ.) Report only, Open_EN Open event =1 Released ISINK voltage < open LED protection Report flag RC threshold =1 ISINK voltage> short LED protection threshold

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Short event Released Report flag RC

Page 85 of 201

MT6360U PMIC Datasheet Confidential A Threshold (typical value)

Deglitch time

Current limit

Peak inductor current > 5A

0

Vout PGB

Vout < 0.8 × Vtarget

400 μs

Vout UVP

Vout < 0.6 × Vtarget

0

Vin UVP

BUCKx_PVIN < 2.4V

0

OTP

Temperature > 150°C

0

LDO1

Over-current

1.5 × Imax to 2.8 × Imax

60 μs

LDO2

Over-Current

1.5 × Imax to 2.8 × Imax

60 μs

LDO3

Over-Current

1.5 × Imax to 2.5 × Imax

60 μs

LDO5

Over-Current

1.5 × Imax to 2.5 × Imax

60 μs

LDO6

Over-Current

1.5 × Imax to 2.8 × Imax

60 μs

LDO7

Over-Current

1.5 × Imax to 2.8 × Imax

60 μs

LDO5

OTP

Temperature > 150°C

Part

Protection type

Buck

MediaTek Proprietary and Confidential.

0

Protection method

Buck shutdown selection by (0x12, Re-start bit[1] and 0x22, bit[1]) PGB protect selection by (0x18, bit[1:0]) and PG, latch-off (0x28, bit[1:0]), default hiccup Vout > 0.6 × Report only Vtarget BUCKx_PVIN > Buck stop switching 2.4 OTP shutdown Temperature < selection by (0x0E, 110°C bit[7]) Latch-off protection Automatically disable Re-start LDO1 Latch-off protection Automatically disable Re-start LDO2 Latch-off protection Automatically disable Re-start LDO3 Latch-off protection Automatically disable Re-start LDO5 Hiccup protection Only interrupt; will not Hiccup disable LDO6 Hiccup protection Only interrupt; will not Hiccup disable LDO7 OTP shutdown Temperature < selection by (0x0E, 110°C, latch-off bit[7])

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Reset method

Page 86 of 201

MT6360U PMIC Datasheet Confidential A

5.2

Register Table and Description Table 5-5. PMU part register detailed description

Address

Reg name

Bit

Bit name

Default

Type

Description Enables I C safe timer for SDA/SCL low active 0: Disable safe timer 1: Enable safe timer I2C safe timer deglitch time 00: 0.5 sec 01: 0.75 sec 10: 1 sec 11: 2 sec GPIO: MRSTB reset function enable control 0: Disable 1: Enable (MRSTB pull low will start MRSTB timer counting.) Selects MRSTB debounce time 000: 0.75 ms 001: 1 ms 010: 1.25 ms 011: 1.5 ms 100: 1.75 ms 101: 2 ms 110: 2.25 ms 111: 2.5 ms Selects I2CSTMR_RST and MRSTB reset 0: Particular hardware reset: reset PD/CHG/FLED/RGB relative logic and REG_PD/REG_PMU (except Note 1) 1: Register reset: reset REG_PMU except FAULTB/BUCK/LDO's EVT/STAT/MASK, CHG_BATSYSUV_FLAG Note 1: REG_TM, REG_PMIC, REG_LDO and QONB/SHIPPING relative functions and FAULTB/BUCK/LDO's EVT/STAT/MASK, CHG_BATSYSUV_FLAG All registers and logic reset bit 0: Not reset all registers and logic 1: Reset all registers and logic Note: This byte will be reset to 0 after the reset procedure is finished. CHG registers and logic reset bit 2

7

I2CSTMR_RST_E N

0

RW

6:5

I2CSTMR_RST_T MR

00

RW

MREN

0

RW

100

RW

4

0x01

Core Ctrl 1 3:1

0x02 RST1 0: Not reset CHG relative registers and

MediaTek Proprietary and Confidential.

MRSTB_TMR

0

MRSTB_RST_SEL

0

RW

7

ALL_RST

0

WC

6

CHG_RST

0

WC

5

FLED_RST

0

WC

logic 1: Reset CHG relative registers and logic FLED registers and logic reset bit 0: Not reset FLED relative registers and logic

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Page 87 of 201

MT6360U PMIC Datasheet Confidential A Address

0x03

Reg name

CRC_EN

Bit

Bit name

Default

4

USBID

0

3

RGB_RST

0

2

ADC_RST

0

1

Reserved

0

0

REG_RST

0

7

EN_PMIC_CRC

1

6

EN_LDO_CRC

0

5

Reserved

0

4

HWEN_F_TDB

0

3

Reserved

00

2

FAULTB_RETRIG GER

0

FAULTB_RET

00

1:0

Type

Description 1: Reset FLED relative registers and logic USB_ID registers and logic reset bit 0: Not reset USB_ID relative registers WC and logic 1: Reset USB_ID relative registers and logic RGB registers and logic reset bit 0: Not reset RGB relative registers and WC logic 1: Reset RGB relative registers and logic ADC registers and logic reset bit 0: Not reset ADC relative registers and WC logic 1: Reset ADC relative registers and logic R Reserved REG_PMU registers reset bits 0: Not reset REG_PMU registers 1: Reset specified REG_PMU register RW according to the RST table Note: This bit will be reset to 0 after the reset procedure is finished. PMIC I2C access CRC check enable bit 0: Disable RO 1: Enable Note: default value form efuse76[5] LDOS I2C access CRC check enable bit 0: Disable RO 1: Enable Note: Default value from efuse76[4] R Reserved Selects EN pin falling edge debouncing time RW 0: < 18 μs 1: 128 μs R Reserved Re-triggers interrupt 0: Disable RWSC 1: Trigger (after trigger, this bit will be cleared to 0.) Selects interrupt retrigger time 00: 16 μs RW 01: 32 μs

10: 64 μs

0x04

RST_PAS_COD E1

MediaTek Proprietary and Confidential.

7:0

RST_PAS_CODE 1

00000000

RW

11: 128 μs RST_PAS_CODE1[7:0]/Passcode 1 for RST (except for PD): Set REG0x04 = 8'hA9 then REG0x05 = 8'h96 to start up REG0x02: ***_RST.

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Page 88 of 201

MT6360U PMIC Datasheet Confidential A Address

Reg name

Bit

Bit name

Default

Type

0x05

RST_PAS_COD E2

7:0

RST_PAS_CODE 2

00000000

RW

7

APWDTRST_EN

0

RW

6

APWDTRST_SEL

0

RW

5:4

CC_OPEN_SEL

00

RW

3:2

I2C_CC_OPEN_T SEL

00

RW

1

PD_MDEN

0

RW

0

Reserved

0

R

7

CHG_EVT

0

RO

6

FLED_EVT

0

RO

0x06

0x0B 0: No IRQ event

Core Ctrl 2

IRQ_IND (IRQ Source Indicator)

Confidential.

Flash LED IRQ event indicator 0: No IRQ event 1: IRQ event occurs. LDO IRQ event indicator

4

MediaTek Proprietary and

Description To erase RST_PAS_CODE, REG0x02 will not work. RST_PAS_CODE2[7:0]/Passcode 2 for RST (except for PD): Set REG0x04 = 8'hA9 then REG0x05 = 8'h96 to start up REG0x02: ***_RST. To erase RST_PAS_CODE, REG0x02 will not work. AP watchdog timer enable control 0: Disable 1: Enable Selects AP watchdog timer reset 0: Reset REG_PMIC and REG_LDO except for their EVT/STAT/MASK in REG_PMU 1: BUCKs and LDO7/6 power off in sequence then reset REG_PMIC and REG_LDO except for EVT/STAT/MASK in REG_PMU. Next check EN pin's state after TB_REBOOT (COLD_RST). 00: Disable 01: SCL/SDA low time out will open CC for 40 ms. 10: Reserved 11: SCL/SDA low time out and SYSUV will open CC for 40 ms. 00: SCL/SDA both low 4 ms for timeout 01: SCL/SDA both low 8 ms for timeout 10: SCL/SDA both low 16 ms for timeout 11: SCL/SDA both low 32 ms for timeout Enables PD function 0: Not support PD function 1: Support PD function Reserved Charger IRQ event indicator 0: No IRQ event 1: IRQ event occurs.

RGB_EVT

0

RO

1: IRQ event occurs. RGB IRQ event indicator 0: No IRQ event 1: IRQ event occurs.

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Page 89 of 201

MT6360U PMIC Datasheet Confidential A Address

0x0C

Reg name

IRQ_MASK (IRQ Source Indicator Mask)

Bit

Default

3

BUCK2_EVT

0

2

BUCK1_EVT

0

1

BASE_EVT

0

0

FAULTB_EVT

0

7

CHG_MASK

0

6

FLED_MASK

0

5

LDOs_MASK

0

4

RGB_MASK

0

3

BUCK2_MASK

0

2

BUCK1_MASK

0

1

BASE_MASK

0

0 7:3 2 0x0D

Bit name

Reserved Reserved

1 00000

INT_RETRIGGER

0

INT_RET

00

IRQ_SET (IRQ Setting) 1:0

Type

Description BUCK2 IRQ event indicator RO 0: No IRQ event 1: IRQ event occurs. BUCK1 IRQ event indicator RO 0: No IRQ event 1: IRQ event occurs. BASE/USBID IRQ event indicator RO 0: No IRQ event 1: IRQ event occurs. FAULTB event indicator RO 0: No PG fault event occurs. 1: PG fault event ever occurs. Charger IRQ mask function RW 0: Bypass IRQB and event 1: Mask IRQB and event Flash IRQ mask function RW 0: Bypass IRQB and event 1: Mask IRQB and event LDO IRQ mask function RW 0: Bypass IRQB and event 1: Mask IRQB and event RGB IRQ mask function RW 0: Bypass IRQB and event 1: Mask IRQB and event BUCK2 IRQ mask function RW 0: Bypass IRQB and event 1: Mask IRQB and event BUCK1 IRQ mask function RW 0: Bypass IRQB and event 1: Mask IRQB and event BASE/USBID IRQ mask function RW 0: Bypass IRQB and event 1: Mask IRQB and event R Reserved R Reserved Re-triggers interrupt 0: Disable RWSC 1: Trigger (after trigger, this bit will be cleared to 0.) Selects interrupt retrigger time 00: 16 μs RW 01: 32 μs 10: 64 μs

11: 128 μs

0x0E

SHDN_CTRL

MediaTek Proprietary and Confidential.

7

OT_SHDN_SEL

1

RW

Reaction when OT happens, except that CHG/FLED is hiccup; others are latch-off 0: Only interrupt; will not disable any channel except for CHG

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Page 90 of 201

MT6360U PMIC Datasheet Confidential A Address

Reg name

Bit

Bit name

Default

Type

6

VDDAOV_SHDN _SEL

0

RW

5

OTP0_EN

1

RW

4

OTP1_EN

1

RW

3

OTP1_LPFOFF_E N

0

RW

2

LDO5_OTP_EN

1

RW

1

LDO5_OTP_LPF OFF_EN

0

RW

0 000010

R R

SHDN_CTRL

0 7:2

0x10

OSC_CTRL

0x11

CHG_CTRL1

MediaTek Proprietary and Confidential.

Reserved Reserved

1

FON_ENBASE

0

RW

7 6 5

Reserved Reserved Reserved

0 0 0

R R R

Description 1: Shut down all channels and reset CHx_EN_CTRLx Note: When the temperature is recovered after TB_REBOOT, if EN is logic high, enable channels in sequence. Reaction when VDDAOV happens, except that CHG/FLED/PD is not affected; others are latch-off 0: Only interrupt; will not disable any channel 1: Shut down all channels except for CHG/FLED/PD and reset CHx_EN_CTRLx Note: When VDDA is recovered after TB_REBOOT, if EN is logic high, enable channels in sequence. OTP0 (in CHG) enable control 0: Disable 1: Enable OTP1 (in BUCKs) enable control 0: Disable 1: Enable 0: OTP1 enable control by OTP1_EN 1: When any buck is on and in normal mode, OTP1 enable control by OTP1_EN. For other conditions, force OTP1 off. OTP (in LDO5) enable control 0: Disable 1: Enable 0: LDO5_OTP enable control by OTP5_OTP_EN 1: When LDO5 is on and in normal mode, LDO5_OTP enable control by OTP5_OTP_EN. For other conditions, force LDO5_OTP off. Reserved Reserved Forces BASE to turn on or not 0: BASE turns on according to system application. 1: Force BASE to turn on Forces OSC to turn on or not 0: OSC turns on according to system application. 1: Force OSC to turn on Reserved Reserved Reserved

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Page 91 of 201

MT6360U PMIC Datasheet Confidential A Address

0x12

Reg name

Bit 4

Bit name Reserved

Default 0

3

Force_Sleep

0

2

HZ

0

1

Reserved

0

0

OPA_MODE

0

7

SHIP_MODE

0

6

BATDET_DIS_DL Y

0

5

Reserved

0

4

TE

1

IINLMTSEL

00

1

CFO_EN

1

0

CHG_EN

1

CHG_CTRL2 3:2

Type Description R Reserved Forces sleep to reduce ICHG_VIN RW 0: Normal 1: Force sleep Selects Hz RWSC 0: No high impedance mode 1: High impedance mode R Reserved Enables boost mode RWSC 0: Charge mode 1: Boost mode for OTG Enables shipping mode; forces BATFET off 0: Allow BATFET to turn on 1: Force BATFET to turn off RWSC Note: The following conditions clear this bit 0: 1) TA plugged in; 2) CHG_QONB pin is pulled from logic high to logic low over 0.9s. BATFET turn-off delay 0: BATFET turns off immediately. RW 1: BATFET turns off with 18s delay after SHIP_MODE bit is set. R Reserved Enables termination RW 0: Disable charge current termination 1: Enable charge current termination Input current limit selection bit 00: AICR = 3.25A 01: CHG_TYP results is applied. RW 10: IAICR[5:0] results is applied. 11: Input limit is set by the lower level of these three. Enables charger and OTG 0: Disable CFO 1: Enable CFO RWSC Note: 1) Reset by CHG_VIN plug-in. 2) CHGWDT_RST trigger will set this bit to 1'b0. Enables charging 0: Disable CHG 1: Enable CHG RWSC Note:

1) Reset by CHG_VIN plug-in.

0x13

CHG_CTRL3

MediaTek Proprietary and Confidential.

7:2

IAICR

001000

RW

2) CHGWDT_RST trigger will set this bit to 1'b0. AICR setting 000000: 100 mA 000001: 150 mA

© 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in part, is strictly prohibited.

Page 92 of 201

MT6360U PMIC Datasheet Confidential A Address

0x14

Reg name

CHG_CTRL4

Bit

CHG_CTRL5

Default

Type

1

AICR_EN

1

RW

0

ILIM_EN

1

RW

7:1

VOREG

0011110

RW

0

R

011001

RW

0

0x15

Bit name

7:2

Reserved

VOBST

Description 000010: 200 mA 000011: 250 mA ... 001000: 500 mA 001001: 550 mA ... 100110: 2A ... 11101 : 3A ... 111111: 3.25A Enables AICR loop 0: Disable AICR loop 1: Enable AICR loop Enables ILIM function 0: Disable ILIM function 1: Enable ILIM function Battery regulation voltage The delta-V of the battery regulation voltage is 10 mV. 0000000: 3.9V 0000001: 3.91V 0000010: 3.92V 0000011: 3.93V … 0011101: 4.19V 0011110: 4.2V 0011111: 4.21V … 0101100: 4.34V 0101101: 4.35V 0101110: 4.36V ... 1010001: 4.71V 1010001~1111111: 4.71V Reserved OTG regulation voltage The delta-V of the OTG regulation voltage is 25 mV. 000000~010000: Reserved 010001: 4.85V 010010: 4.875V … 010111: 5V 011000: 5.025V

011001: 5.05V 011010: 5.075V 011011: 5.1V ... 111000: 5.825V 111000~111111: 5.825V MediaTek Proprietary and Confidential.

© 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in part, is strictly prohibited.

Page 93 of 201

MT6360U PMIC Datasheet Confidential A Address

0x16

Reg name

Bit

Default

Type

1:0

THREG

11

RW

7:1

VMIVR

0000101

RW

1

RW

010011

RW

CHG_CTRL6

0

7:2 0x17

Bit name

MIVR_EN

ICHG (0.3A)

CHG_CTRL7

Description Charger thermal regulation threshold 00: Reserved 01: Reserved 10: 100oC 11: 120oC Input MIVR threshold setting 0000000: 3.9V 0000001: 4V 0000010: 4.1V 0000011: 4.2V 0000100: 4.3V 0000101: 4.4V 0000110: 4.5V … 0011110: 6.9V 0011111: 7V … 0110010: 8.9V 0110011: 9V … 1010000: 11.9V 1010001: 12V … 1011111: 13.4V 1100000~1111111: 13.4V Enables MIVR loop 0: Disable MIVR loop 1: Enable MIVR loop Regulated charge current 000000: Reserved ... 000010: 0.3A ... 001000: 0.9A 001001: 1A 001010: 1.1A ... 010010: 1.9A 010011: 2A ... 011100: 2.9A 011101: 3A 011110~111111: Reserved Note: When ICHG is set above 2.5A, setting OCP to higher level is

recommended. (Addr 0x1D[2] = 1)

1:0

MediaTek Proprietary and Confidential.

EOC_TIMER

00

RW

EOC back-charging time 00: 0 min 01: 30 mins 10: 45 mins 11: 60 mins

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Page 94 of 201

MT6360U PMIC Datasheet Confidential A Address

0x18

0x19

Reg name

Bit

Bit name

Default

Type

7:4

VPREC

1010

RW

3:0

IPREC

0001

RW

7:4

IEOC

0011

RW

CHG_CTRL8

CHG_CTRL9

Description Pre-charge voltage threshold (rising) 0000: 2V 0001: 2.1V 0010: 2.2V 0011: 2.3V 0100: 2.4V 0101: 2.5V 0110: 2.6V 0111: 2.7V 1000: 2.8V 1001: 2.9V 1010: 3.0V 1011: 3.1V 1100: 3.2V 1101: 3.3V 1110: 3.4V 1111: 3.5V Pre-charge current level 0000 : 100 mA 0001: 150 mA 0010: 200 mA 0011: 250 mA 0100: 300 mA 0101: 350 mA 0110: 400 mA 0111: 450 mA 1000: 500 mA 1001: 550 mA 1010: 600 mA 1011: 650 mA 1100: 700 mA 1101: 750 mA 1110: 800 mA 1111: 850 mA End-of-charge current (IEOC) setting 0000: 100 mA 0001: 150 mA 0010: 200 mA 0011: 250 mA 0100: 300 mA 0101: 350 mA 0110: 400 mA 0111: 450 mA 1000: 500 mA 1001: 550 mA

1010: 600 mA 1011: 650 mA 1100: 700 mA 1101: 750 mA 1110: 800 mA 1111: 850 mA MediaTek Proprietary and Confidential.

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Page 95 of 201

MT6360U PMIC Datasheet Confidential A Address

Reg name

Bit 3

0x1A

Bit name EOC_EN

Default

Type

1

RW

2:0

CHG_TDEG_EOC

100

RW

7:4

LBP

0101

RW

1

RW

011

RW

CHG_CTRL10

3

2:0

LBP_EN

OTG_OC[2:0]

Description Enables/Disable IEOC (charge current termination) 0: Disable 1: Enable EOC deglitch time 000: Reserved 001: Reserved 010: Reserved 011: Reserved 100: 2 ms 101: 4 ms 110: 8 ms 111: 16 ms Selects low battery protection voltage (falling edge threshold, hysteresis voltage = 0.4V) 0000: Reserved 0001: Reserved 0010: Reserved 0011: Reserved 0100: 2.7V 0101: 2.8V 0110: 2.9V 0111:3.0V 1000: 3.1V 1001: 3.2V 1010: 3.3V 1011 3.4V 1100: 3.5V 1101: 3.6V 1110: 3.7V 1111: 3.8V Enables/Disables low battery protection 0: Disable 1: Enable OTG overload threshold of UUG current (minimum) 000: 0.5A 001: 0.7A 010: 1.1A 011: 1.3A 100: 1.8A 101: 2.1A 110: 2.4A

111: Reserved 0x1B

CHG_CTRL11

MediaTek Proprietary and Confidential.

7

ADP_DIS

0

RW

6

Reserved

0

R

Disables charger adapter detection 0: Enable adapter detection 1: Disable adapter detection Reserved

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Page 96 of 201

MT6360U PMIC Datasheet Confidential A Address

0x1C

Reg name

CHG_CTRL12

timer 0x1D

Bit

Bit name

Default

Type

5

SYSUV_HW_SEL

1

RW

4:2

SYSREG

011

RW

1:0

VRECH

00

RW

7:5

WT_FC

000

RW

4:3

WT_PRC

00

RW

2

TMR2X_EN

0

RW

1

TMR_EN

1

RW

0

TMR_PAUSE

0

RW

7

CHG_WDT_EN

0

RW

6

CHG_WDT_TRST

1

RW

CHG_CTRL13

MediaTek Proprietary and Confidential.

Description System UV protection selection bit 0: Switching is not turned off when system is in UVP. 1: Switching is turned off when system is in UVP. System minimum regulation voltage 000: 3.3V 001: 3.4V 010: 3.5V 011: 3.6V 100: 3.7V 101: 3.8V 110: 3.9V 111: 4.0V Charging re-charge voltage threshold with VOREG 00 : 100 mV 01: 150 mV 10: 200 mV 11: 250 mV Fast charge timer 000: 4 hrs 001: 6 hrs 010: 8 hrs 011: 10 hrs 100: 12 hrs 101: 14 hrs 110: 16 hrs 111: 20 hrs Pre-charge timer 00: 30 mins 01: 45 mins 10: 60 mins 11: 60 mins Double charger timer during MIVR, AICR, and thermal regulation 0: Disable 2x extended charger timer 1: Enable 2x extended charger timer Enables/Disables charger timer 0: Disable 1: Enable Timer control bit 0: Timer is active. 1: Timer is paused. Enables/Disables charger watchdog 0: Disable 1: Enable Waiting timer to set REG0x12[1]: CFO_EN = 0, REG0x12[0]: CHG_EN = 0, REG0x11[1:0] = 00: OTG disable and

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Page 97 of 201

MT6360U PMIC Datasheet Confidential A Address

Reg name

Bit

Bit name

Default

Type

Description REG0x01[7]: I CSTMR_RST_EN = 1 after watchdog is asserted 0: 256 ms 1: 512 ms Watchdog timer, from WDTEN is enabled to watchdog IRQ 00: 8s 01: 40s 10: 80s 11: 160s System UV protection inductor peak current limit level of Charger_Buck selection bit Refer to 0x1D[2]. 0: Inductor peak current limit level of Charger_Buck is normal when system UVP. 1: Inductor peak current limit level of Charger_Buck is half when system UVP. Inductor peak current limit level of Charger_Buck mode 0: OCP = 6A 1: OCP = 8A UUG enable/disable control 0: Force UUG to turn off 1: Allow UUG to turn on Reserved Enables AICC function 0: Disable 1: Enable Comparator output deglitch time 00: 2 ms 01: 4 ms 10: 8 ms 11: 16 ms Detection internal time 00: 50 ms 01: 100 ms 10: 200 ms 11: 400 ms AICC loop break 0: No constraint 1: Enter AICC once When Max (VSYS, VBAT) UVLO > 2.5V, 2

5:4

0x1E

CHG_WDT

01

RW

3

SYSUV_HW_OC P_SEL

0

RW

2

Higher_OCP

0

RW

1

UUG_ON

1

RW

0

Reserved

0

R

7

RG_EN_AICC

0

RW

6:5

TDEG_AICC_ME AS

00

RW

4:3

AICC_MEAS_INT VL

00

RW

2

RG_AICC_ONCE

1

RW

SET_DEG_PP

10

RW

CHG CTRL 14

power path is turned on with deglitch 1:0

MediaTek Proprietary and Confidential.

time select 00: 32 msec 01: 64 msec 10: 128 msec 11: 256 msec

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Page 98 of 201

MT6360U PMIC Datasheet Confidential A Address

0x1F

0x20

Reg name

Bit name

Default

Type

7:6

VDDP_VOSEL

11

RW

5:3

Reserved

000

R

2:1

Higher_OCP_BS T

11

RW

0

Reserved

0

R

7:1

AICC_VTH

0000111

RW

CHG CTRL 15

CHG CTRL 16

CHG_AICC_RE SULT will be controlled by AICC function. 0x21

0x22

Bit

Device Type

MediaTek Proprietary and Confidential.

0

CHG_VBATOVPB _INDICATOR

0

RW

7:2

RG_AICC_RESUL T

111111

RW

1:0

Reserved

00

R

USBCHGEN

0

RW

7

Description VDDP output voltage setting 00: 4.165V 01: 4.41V 10: 4.65V 11: 4.9V Reserved Inductor peak current limit level of boost mode 00: OCP_BST = 3.5A 01: OCP_BST = 4.5A 10: OCP_BST = 5.5A 11: OCP_BST = 6.5A Reserved Input AICC_VTH threshold setting 0000000: 3.9V 0000001: 4V 0000010: 4.1V 0000011: 4.2V 0000100: 4.3V 0000101: 4.4V 0000110: 4.5V 0000111: 4.6V … 0011110: 6.9V 0011111: 7V … 0110010: 8.9V 0110011: 9V … 1010000: 11.9V 1010001: 12V … 1011111: 13.4V 1100000~1111111: 13.4V Selects CHG_VBATOVPB pin control When VBAT OVP happens, CHG_VBATOVPB pulls low (open drain) 0: Control by 0x45[6:5], HW BAT OVP 1: Control by 0xD5[1], ADC BAT OVP If RG_EN_AICC (0x1E[7]) = 0, RG_AICC_RESULT[5:0]= IAICR[5:0]( 0x13[7:0]) If RG_EN_AICC (0x1E[7]) = 1, the value Reserved Enables/Disables USB charger detection flow 0: Disable USB charger detection flow 1: Enable USB charger detection flow

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Page 99 of 201

MT6360U PMIC Datasheet Confidential A Address

Reg name

Bit 6

0x24

DCP Control

Type

1

RW

01

RW

DCD_TIMEOUT

3:0 7:2

Reserved Reserved

0000 000000

R R

1

EN_DCP

0

RW

0 7

Reserved Reserved

0 0

R R

000

R

USB Status

USB Status 1 3

CHGDET

0

R

2

DCDT

0

R

00 000

R R

0

RW

0000

RW

1:0 7:5 4

0x28

Default

5:4

6:4

0x27

Bit name DCD Timeout EN

Reserved Reserved DPDM_CTRL_EN

DPDM_CTRL 3:0

DPDM_CTRL

Description 0: Disable DCD timeout 1: Enable DCD timeout Data contact detection timeout 00: 300 ms 01: 600 ms 10: 900 ms 11: 1,200 ms Reserved Reserved Enables dedicate charging port 0: Disable 1: Enable Reserved Reserved 000: No VBUS 001: VBUS flow is going. 010: SDP 011: Unknown adapter 100: DCP 101: CDP 110: VBUS IN but BC12 flow is disable 111: Reserved 0: Charger port is not detected 1: Charger port is detected 0: DCD timeout event of BC detection does not occur. 1: DCD timeout event of BC detection occurs. Reserved Reserved Enables DPDM register control 0: Disable 1: Enable Selects RW DPDM control 0000: DP/DM = HZ/HZ 0001: DP/DM = Hz/0V 0010: DP/DM = 0V/Hz 0011: DP/DM = 0V/0V 0100: DP/DM = 0V/0.6V 0101: DP/DM = 0.6V/0V 0110: DP/DM = 0.6V/0.6V 0111: DP/DM = 0.6V/3.3V 1000: DP/DM = 3.3V/0.6V

1001: DP/DM = 3.3V/3.3V 1010: DP/DM = Hz/Hz 1011: DP/DM = Hz/Hz 1100: DP/DM = Hz/Hz 1101: DP/DM = Hz/Hz 1110: DP/DM = Hz/Hz MediaTek Proprietary and Confidential.

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Page 100 of 201

MT6360U PMIC Datasheet Confidential A Address

Reg name

Bit

0x2B

Default

Type

7

PP_OFF_rst dis

0

RW

6

sBCK_SWITCHIN G_EN

1

RW

000

RW

5:3 0x2A

Bit name

Reversed

CHG_PUMP 2

WD_PMU_EN

0

RW

1

WD_HW_EN

0

RW

0

WD_SW_EN

0

RW

7

EN_PUMPX

0

RW

6

PUMPX_2.0_1.0

0

RW

5

PUMPX_UP_DN

0

RW

00000

RW

CHG CTRL 17

4:0

PUMPX_DEC

Description 1111: DP/DM = Hz/Hz Disables/Enables QON = 0 for 15s to sys reset 0: Not disable reset function (QON = 0 for 15s will reset system.) 1: Disable reset function (QON = 0 will not reset system.) Enables/Disables only charger_buck (allowing Boost operation) 0: Disable 1: Enable Reversed Enables water detection function 0: Disable 1: Enable (support WD_HW_EN and WD_SW_EN) Triggers DPDM water detection when PD_VBUS is plugged in 0: Disable 1: Enable SW trigger DPDM water detection Start water detection while 0 -> 1; WD_HW_EN should be disabled first. 0: Disable 1: Enable Enables MTK pump express pulse 0: Disable 1: Allow MTK pump express pulse Enables MTK pump express 2.0/1.0 0: Enable PE1.0 1: Enable PE2.0 Enables MTK pump express 1.0 voltage up/down 0: Enable PE1.0 voltage down 1: Enable PE1.0 voltage up MTK pump express 2.0 voltage request setting 00000: 5.5V 00001: 6V 00010: 6.5V … 00111: 9V … 01101: 12V

…

0x2C

CHG CTRL 18

MediaTek Proprietary and Confidential.

7

Reserved

0

R

11101: 20V 11110: Adapter healthy self-testing 11111: Disable cable drop compensation Reserved

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Page 101 of 201

MT6360U PMIC Datasheet Confidential A Address

0x2D

Reg name

Bit

Bit name

Default

Type

6

EN_IRCOMP

1

RW

5:3

BAT_COMP

000

RW

2:0

VCLAMP

000

RW

7:4

CHRDETB_VBUS _UVLO

1011

RW

3:0

CHRDETB_VBUS _OVP

0110

RW

CHRDETB_CTR L1

0101: 9.5V

Description Enables battery IR compensation 0: Disable 1: Enable Battery IR compensation resistor setting 000: 0 mΩ 001: 25 mΩ 010: 50 mΩ 011: 75 mΩ 100: 100 mΩ 101: 125 mΩ 110: 150 mΩ 111: 175 mΩ Battery IR compensation maximum voltage clamp 000: 0 mV 001: 32 mV 010: 64 mV 011: 96 mV 100: 128 mV 101: 160 mV 110: 192 mV 111: 224 mV CHRDETB block, PD_VBUS UVLO (rising) 0000: 2.6V 0001: 2.7V 0010: 2.8V 0011: 2.9V 0100: 3.0V 0101: 3.1V 0110: 3.2V 0111: 3.3V 1000: 3.4V 1001: 3.5V 1010: 3.6V 1011: 3.7V 1100~1111: 3.7V CHRDETB block, PD_VBUS OVP (rising) 0000: 6V 0001: 6.5V 0010: 7V 0011: 7.5V 0100: 8.5V 0110: 10.5V 0111: 11.5V 1000: 12.5V 1001~1111: 14.5V

0x2E MediaTek Proprietary and Confidential.

7

CHRDETB_EN

1

RW

0: Disable

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Page 102 of 201

MT6360U PMIC Datasheet Confidential A Address

Reg name CHRDETB_CTR L2

0x4A

CHG STAT

Bit

OTHERS_CTRL

Default

Type

6:0

Reserved

0000000

R

7:6

CHG_STAT

00

RO

5

VBAT_LVL

0

RO

4

VBAT_TRICKLE

0

RO

3

BOOST_STAT

0

RO

2

BST_VBUSOVP_ STAT

0

RO

00 000000

R R

1

RW

1

0 0x52

ADC_DATA_H

7:0

0x53

ADC_DATA_L

7:0

Reserved Reserved

BAT_OVP_ADC_ EN

Reserved 0 ADC_BAT_CODE 00000000 H ADC_BAT_CODE 00000000 L

R

Reserved Charger status 00: Ready 01: Charge is in progress. 10: Charge is done. 11: Fault Battery voltage level selection for two operation modes 0: In pre-charge mode 1: In fast-charge mode Battery voltage level for operation mode 0: Charger does not operate in trickle level. 1: Charger operates in trickle level. Boost mode status 0: Not in boost mode 1: Boost mode Boost mode VBUS OVP status 0: Boost-mode VBUS OVP does not occur. 1: Boost-mode VBUS OVP occurs. Reserved Reserved When ZCV is active or SW writes ADC_CH4_EN = 1'b1, enable BAT_OVP_ADC detection. 0: Disable BAT_OVP_ADC function 1: Enable BAT_OVP_ADC function, when ZCV is active or SW writes ADC_CH4_EN = 1'b1. Reserved

R

ADC code high byte

R

ADC code low byte

7

ADC_EN

1

RW

6

ZCV_EN

1

RW

0x56 ADC_CONFIG 1: Enable zero current voltage function

5:3

MediaTek Proprietary and Confidential.

Description 1: Enable

1:0 7:2

0x51

Bit name

ADC_WAIT_T

001

RW

0: Disable ADC 1: Enable ADC When TA is plugged in, ADC automatically detects VBAT at background. 0: Disable zero current voltage function ADC waiting time after every channel 000: 0 ms 001:25 ms 010:50 ms 011:100 ms

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Page 103 of 201

MT6360U PMIC Datasheet Confidential A Address

0x57

0x58

Reg name

Bit

Bit name

Default

Type

2

ADC_CH10_EN

0

RW

1

ADC_CH9_EN

0

RW

0

ADC_CH8_EN

0

RW

7

ADC_CH7_EN

0

RW

6

ADC_CH6_EN

0

RW

5

ADC_CH5_EN

0

RW

4

ADC_CH4_EN

0

RW

3

ADC_CH3_EN

0

RW

2

ADC_CH2_EN

0

RW

1

ADC_CH1_EN

0

RW

0

ADC_CH0_EN

0

RW

7:0

ADC_IDLE_T

00001010

RW

ADC_EN2

ADC_IDLE_T

Description 100:150 ms 101:200 ms 110:250 ms 111: 300 ms ADC CH10: TS 0: Disable ADC channel 10 1: Enable ADC channel 10 ADC CH9: VREF_TS 0: Disable ADC channel 9 1: Enable ADC channel 9 ADC CH8: TEMP_JC 0: Disable ADC channel 8 1: Enable ADC channel 8 ADC CH7: CHG_VDDP 0: Disable ADC channel 7 1: Enable ADC channel 7 ADC CH6: IBAT 0: Disable ADC channel 6 1: Enable ADC channel 6 ADC CH5: IBUS 0: Disable ADC channel 5 1: Enable ADC channel 5 ADC CH4: VBAT 0: Disable ADC channel 4 1: Enable ADC channel 4 ADC CH3: VSYS 0: Disable ADC channel 3 1: Enable ADC channel 3 ADC CH2: CHG_VIN/2 0: Disable ADC channel 2 1: Enable ADC channel 2 ADC CH1: CHG_VIN /5 0: Disable ADC channel 1 1: Enable ADC channel 1 ADC CH0: USB_ID 0: Disable ADC channel 0 1: Enable ADC channel 0 ADC idle time after every turn 00000000: 0 ms 00000001: 200 ms 00000010: 400 ms …

00001010: 2,000 ms

0x5A

ADC_RPT_1

MediaTek Proprietary and Confidential.

7:4

ADC_RPT_SEL

1111

RW

… 11111111: 51,000 ms 0000: Prefer report channel 0 0001: Prefer report channel 1 ...

© 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in part, is strictly prohibited.

Page 104 of 201

MT6360U PMIC Datasheet Confidential A Address

Reg name

Bit

Bit name

Default

3:0

ADC_RPT_CH

0000

0x5B 0x5C

ADC_RPT_2 ADC_RPT_3

7:0 7:0

ADC_RPT_H ADC_RPT_L

00000000 00000000

0x5F

BAT_OVP_TH_ SEL_CODEH

7:0

BAT_OVP_TH_S EL_CODEH

00001101

0x60

BAT_OVP_TH_ SEL_CODEL

7:0

BAT_OVP_TH_S EL_CODEL

11000000

7

0x61

0x62

0x6D

CHG_CTRL 19

VDDA Supply

Reserved

0

6:5

CHG_VIN_OVP_ VTHSEL

01

4:0 7:2

Reserved Reserved

1:0

VOVDDM_SEL

11

7

USBID_EN

0

6:5

ID_RUPSEL

00

4:2

IS_TDET

011

00000 000000

USBID_CTRL1

Type

Description 1010: Prefer report channel 10 1011~1111: Report current channel ADC report channel RO I2C reading this address will latch ADC data for ADC_RPT2 and ADC_RPT3. RO ADC report high byte RO ADC report low byte BAT_OVP_TH_SEL_CODEH Note: This byte is combinatorial with RW REG_PMU0x60; therefore, write two bytes (REG_PMU0x5F and REG_PMU0x60) in one sequence. 1LSB = 250 μV, default = 4.4V RW BAT_OVP_TH = [(CODEH*256) + CODEL]*250 μV R Reserved Selects CHGVIN_OVP threshold voltage 00: 5.5V RW 01: 6.5V 10: 11V 11: 14.5V R Reserved R Reserved VDDM output voltage setting 00: 4.6V RW 01: 4.7V 10: 4.8V 11: 4.88V USB_ID function enable control RW 0: Disable 1: Enable Selects USB_ID pull-up resistance 00: 500K RW 01: 75K 10: 5K 11: 1K USB_ID pull-up resister on-time for detection 000: 400 μs 001: 1 ms 010: 4 ms RWSC 011: 10 ms

100: 40 ms 101: 100 ms 110: 400 ms 111: Always on (manual mode)

MediaTek Proprietary and Confidential.

© 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in part, is strictly prohibited.

Page 105 of 201

MT6360U PMIC Datasheet Confidential A Address

0x6E

0x6F

Reg name

USBID_CTRL2

Bit

Bit name

Default

1:0

IS_PERIOD

01

7:5

ID_TD

001

4:2

Reserved

000

1

USBID_FLOATIN G

0

0

USBID_FON_EN

0

7

ID_PREG_VOSEL

0

6

ID_VTHSEL

0

5:4

Reserved

00

3:1

ID_TDIS

000

USBID_CTRL3

SW

MediaTek Proprietary and Confidential.

Type

Description Note: When USBID_FON_EN = 1'b1, then USBID_EVT = 0->1; IS_TDET will next be automatically set to 3'b111. Repeat period 00 = 4x (4 times of IS_TDET) RW 01 = 100x 10 = 200x 11 = 1600x Selects USB_ID debounce time (fSW = 65 kHz) 000: 1T 001: 3T 010: 16T RW 011: 32T 100: 130T 101: 520T 110: 2,078T 111: 4,156T R Reserved 0: Discharge when USB_ID is off 1: Floating when USB_ID is off RW Note: When USB_ID pin is floating, the voltage value on USB_ID pin can be detected by ADC. USBID_FON function When USBID_EVT = 0 -> 1, IS_TDET will RW be automatically set to 3'b111 or not 0: Disable USBID_FON function 1: Enable USBID_FON function. Selects USB_ID pre-regulator output voltage RW 0: 1.8V 1: 0.6V USB_ID interrupt threshold voltage/hysteresis voltage When ID_PREG_VOSEL = 1'b0, 0: 1.45V/100 mV RW 1: 0.4V/100 mV When ID_PREG_VOSEL = 1'b1, 0: 0.6V/50 mV 1: 0.2V/50 mV R Reserved Selects USB_ID discharge time (4T = 4RC for 98.2% discharging, f = 65 kHz) RWSC 000: 0 μs 001: 3T 010: 9T 011: 16T

© 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in part, is strictly prohibited.

Page 106 of 201

MT6360U PMIC Datasheet Confidential A Address

0x70

0x72

Reg name

FLED_CFG

FLED1_CTRL

Bit

Bit name

Default

Type

0

Reserved

0

R

7

TX Active Level

1

RW

6:5

TXSEL

00

RW

4:2

Reserved

000

R

1

FLED_STRB_LES

0

RW

0

PULLED_LOW_R

1

RW

7

Reserved

0

R

6:4

FLED1_TCL

000

RW

3:0 7

Reserved Reserved

0000 0

R R

6:0

FLED_STRB_TO

0100101

RW

FLED_STRB_C 0x73

(FLED Strobe Control)

MediaTek Proprietary and Confidential.

Description 100: 32T (20 nF, 5 kΩ+ 25%) 101: 64T 110: 128T 111: 160T Note: When ID_FLOATING_EN = 1'b1-> 0, the default value is 3'b000. When ID_FLOATING_EN = 1'b0 -> 1, the default value is 3'b100. Reserved Selects Tx active level 0: Low level 1: High level FLED TX function enable control bits 00: Disable all FLEDs' Tx function 01: Enable FLED1's Tx function and disable FLED2's 10: Disable FLED1's Tx function and enable FLED2's 11: Enable all FLEDs' Tx function Reserved FLED strobe mode: level sensitive enable or rising edge trigger one-shot operation 0: Level sensitive 1: Rising edge trigger FL_LEDCS1/2 pulled low resister setting 0: 2.5 kΩ 1: 20 kΩ Reserved FLED1 timeout current level 000: 25 mA 001: 50 mA ... 110: 175 mA 111: 200 mA If utra_istrb1 = 1, 000 = 12.5 mA 111 = 100 mA Reserved Reserved FLED1 strobe timeout 0000000: 64 ms 0000001: 96 ms … 0100101: 1,248 ms ... 1001001: 2,400 ms 1001010~1111111: 2,432 ms

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Page 107 of 201

MT6360U PMIC Datasheet Confidential A Address

0x74

0x75

Reg name

Bit

0x78

Default

Type

7

FLED1 ULTRA LOW ISTRB\ (utral_istrb1)

0

RW

6:0

FLED1_ISTRB

0111100

RW

7:5

Reserved

000

R

4:0

FLED1_ITOR

00001

RW

0

R

FLED1_STRB_ CTRL (FLED1 Strobe Control)

FLED1_TOR_C TRL (FLED1 Torch Control)

7

0x76

Bit name

FLED2_CTRL

FLED2_STRB_ CTRL (FLED2 Strobe

Reserved

6:4

FLED2_TCL

000

RW

3:0

Reserved

0000

R

0

RW

7

FLED2 ULTRA LOW ISTRB\ (utral_istrb2)

Description 0: Normal 1: I (FLED1_ISTRB[6:0])/2 FLED1 strobe current 0x74[6:0] 000,0000: 25 mA 000,0001: 31.25 mA … 0111100: 400 mA … 1110100~1111111: 750 mA FLED1 strobe current 0000000: 50 mA 0000001: 62.5 mA … 0111100: 800 mA ... 1110100~1111111: 1,500 mA Reserved FLED1 torch current 00000: 25 mA 00001: 37.5 mA … 01111: 212.5 mA ... 11110~11111: 400 mA Reserved FLED2 timeout current level 000: 25 mA 001: 50 mA ... 110: 175 mA 111: 200 mA If utra_istrb2 = 1, 000 = 12.5 mA 111 = 100 mA Reserved 0: Normal 1: I(FLED2_ISTRB[6:0])/2 FLED2 strobe current 0x74[6:0] 000,0000: 25 mA 000,0001: 31.25 mA ... 0111100: 400 mA ...

1110100: 750 mA

6:0

MediaTek Proprietary and Confidential.

FLED2_ISTRB

0111100

RW

... 1111111: 750 mA FLED2 strobe current 0000000: 50 mA 0000001: 62.5 mA

© 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in part, is strictly prohibited.

Page 108 of 201

MT6360U PMIC Datasheet Confidential A Address

0x79

0x7A

0x7E

0x80

Reg name

FLED2_TOR_C TRL (FLED2 Torch Control)

FLED_VMIDTR K_CTRL1 (VMID Fix Mode Control)

FLED_EN (TORCH / STROBE)

Bit

Bit name

7:5

Reserved

4:0

FLED2_ITOR

7:6

Reserved

5:0

FLED_VMID

7:4 3:2

Default

Type

000

R

00001

RW

00

R

110111

RW

Reserved Reserved

0000 00

R R

1

FLCS1_EN

0

RW

0

FLCS2_EN

0

RW

7

ISINK1_CHRIND _EN

0

RW

6

ISINK2_EN

0

RW

5

ISINK3_EN

0

RW

4

ISINK4_ML_EN

0

RW

3

ISINK1_CHRIND _EN_SEL

0

RW

RGB_EN

Description ... 0111100: 800 mA ... 1110100: 1,500 mA ... 1111111: 1,500 mA Reserved FLED2 torch current 00000: 25 mA 00001: 37.5 mA … 01111 : 212.5 mA ... 11110 : 400 mA Reserved MID regulation level (priority is higher than charger setting when EN_FLED = 1) 000000: 3.625V 000001: 3.65V 000010: 3.675V … 110111: 5V … 111110: 5.175V 111111: 5.2V Reserved Reserved FL_LEDCS1 enable control 0: Disable FL_LEDCS1 1: Enable FL_LEDCS1 FL_LEDCS2 enable control 0: Disable FL_LEDCS2 1: Enable FL_LEDCS2 Enables ISINK1 charge indicator current sink 0: Disable 1: Enable Enables ISINK2 current sink 0: Disable 1: Enable Enables ISINK3 current sink 0: Disable

1: Enable

MediaTek Proprietary and Confidential.

Enables ISINK4 moonlight current sink 0: Disable 1: Enable Selects ISINK1 charge indicator control mode

© 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in part, is strictly prohibited.

Page 109 of 201

MT6360U PMIC Datasheet Confidential A Address

Reg name

Bit

Default

Type

ISINK_Breath Mode_Freq

0

RW

1:0

Reserved

00

R

7:6

ISINK1_CHRIND _DIM_MODE

11

RW

5:4

Reserved

00

R

3:0

ISINK1_CHRIND _CUR_SEL

1010

RW

7:6

ISINK2_DIM_M ODE

11

RW

5:4

Reserved

00

R

3:0

ISINK2_CUR_SEL

1010

RW

7:6

ISINK3_DIM_M ODE

11

RW

2

0x81

0x82

Reserved

Bit name

RGB1_ISINK

RGB2_ISINK

0x83 3:0

MediaTek Proprietary and Confidential.

ISINK3_CUR_SEL

1010

RW

Description 0: Auto mode (charger indicator) 1: Software mode Selects all ISINK breath mode switching frequency 0: 256 Hz 1: 128 Hz Reserved Selects ISINK1 mode 00: Flash mode 01: Breath mode 1X: Register mode Reserved ISINK1 maximum LED current level 0000: 1 mA 0001: 2 mA 0010: 4 mA 0011: 6 mA … 1010: 20 mA ... 1100: 24 mA … 1111: 24 mA Selects ISINK2 mode 00: Flash mode 01: Breath mode 1X: Register mode Reserved ISINK2 maximum LED current level 0000: 1 mA 0001: 2 mA 0010: 4 mA 0011: 6 mA … 1010: 20 mA ... 1100: 24 mA … 1111: 24 mA Selects ISINK3 mode 00: Flash mode 01: Breath mode 1X: Register mode ISINK3 maximum LED current level 0000: 1 mA 0001: 2 mA 0010: 4 mA 0011: 6 mA

© 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in part, is strictly prohibited.

Page 110 of 201

MT6360U PMIC Datasheet Confidential A Address

Reg name

Bit

Default

Type

ISINK4_ML_RA MP_UP

1

RW

6:5

Reserved

00

R

4:0

ISINK4_ML_CUR _SEL

01100

RW

7

0x84

Bit name

RGB_ML_ISIN K

0x85

RGB1_DIM

7:0

ISINK1_CHRIND _DIM_DUTY

00011111

RW

0x86

RGB2_DIM

7:0

ISINK2_DIM_DU 00011111 TY

RW

0x87

RGB3_ISINK

7:0

ISINK3_DIM_DU 00011111 TY

RW

7:5

ISINK1_CHRIND _DIM_FSEL

Description … 1010: 20 mA ... 1100: 24 mA … 1111: 24 mA ISINK4 moonlight register mode ramp up function enable control 0: Disable ISINK4 register mode ramp up function 1: Enable ISINK4 register mode ramp up function Note: 16 Steps for total ramp up time is 230 μs ±5%. Reserved ISINK4 moonlight maximum LED current level 00000: 5 mA 00001: 5 mA 00010: 10 mA 00011: 15 mA 00100: 20 mA … 01100: 60 mA 01101: 65 mA ... 10100: 100 mA … 11110: 150 mA 11111: 150 mA ISINK1 charge indicator flash mode dimming duty = (N + 1)/256 N = 0~255 Default: 32/256 ISINK1 charge indicator flash mode dimming duty = (N + 1)/256 N = 0~255 Default: 32/256 ISINK1 charge indicator flash mode dimming duty = (N + 1)/256 N = 0~255 Default: 32/256 Selects ISINK1 charge indicator flash

mode dimming frequency 0x89

RGB1/2_Freq

MediaTek Proprietary and Confidential.

010

RW

000: 0.125 Hz 001: 0.25 Hz 010: 0.5 Hz 011: 1 Hz 100: 2 Hz

© 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in part, is strictly prohibited.

Page 111 of 201

MT6360U PMIC Datasheet Confidential A Address

0x8A

0x8B

Reg name

RGB3/4_Freq

Bit

Bit name

Default

Type

4:2

ISINK2_DIM_FS EL

010

RW

1:0

Reserved

00

R

7:5

ISINK3_DIM_FS EL

010

RW

4:0

Reserved

00000

R

7:4

ISINK1_CHRIND _BREATH_Tr1_S EL

0001

RW

3:0

ISINK1_CHRIND _BREATH_Tr2_S EL

0001

RW

RGB1_Tr

Description 101: 4 Hz 110: 128 Hz 111: 256 Hz Selects ISINK2 flash mode dimming frequency 000: 0.125 Hz 001: 0.25 Hz 010: 0.5 Hz 011: 1 Hz 100: 2 Hz 101: 4 Hz 110: 128 Hz 111: 256 Hz Reserved Selects ISINK3 flash mode dimming frequency 000: 0.125 Hz 001: 0.25 Hz 010: 0.5 Hz 011: 1 Hz 100: 2 Hz 101: 4 Hz 110: 128 Hz 111: 256 Hz Reserved Selects ISINK1 charge indicator breath mode first rising time Duty: 0~25% 0000: 0.125s 0001: 0.375s 0010: 0.625s ... 1000: 2.125s ... 1111: 3.875s 16 steps, 0.25s/step Selects ISINK1 charge indicator breath mode second rising time Duty: 25~100% 0000: 0.125s 0001: 0.375s 0010: 0.625s ...

1000: 2.125s ... 1111: 3.875s 16 steps, 0.25s/step

MediaTek Proprietary and Confidential.

© 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in part, is strictly prohibited.

Page 112 of 201

MT6360U PMIC Datasheet Confidential A Address

0x8C

0x8D

0x8E

Reg name

Bit

Bit name

Default

Type

7:4

ISINK1_CHRIND _BREATH_Tf1_S EL

0001

RW

3:0

ISINK1_CHRIND _BREATH_Tf2_S EL

0001

RW

7:4

ISINK1_BREATH _TON_SEL

0001

RW

3:0

ISINK1_BREATH _TOFF_SEL

0001

RW

0001

RW

RGB1_Tf

RGB1_TON_T OFF

RGB2_Tr

MediaTek Proprietary and Confidential.

7:4

_Tr1_SEL

Description Selects ISINK1 charge indicator breath mode first falling time Duty: 100~25% 0000: 0.125s 0001: 0.375s 0010: 0.625s ... 1000: 2.125s ... 1111: 3.875s 16 steps, 0.25s/step Selects ISINK1 charge indicator breath mode second falling time Duty: 25~0% 0000: 0.125s 0001: 0.375s 0010: 0.625s ... 1000: 2.125s ... 1111: 3.875s 16 steps, 0.25s/step Selects ISINK1 breath mode on-time 0000: 0.125s 0001: 0.375s 0010: 0.625s ... 1000: 2.125s ... 1111: 3.875s 16 steps, 0.25s/step Selects ISINK1 breath mode off-time 0000: 0.25s 0001: 0.75s 0010: 1.25s ... 1000: 4.25s ... 1111: 7.75s 16 steps, 0.5s/step Selects ISINK2 breath mode first rising time Duty: 0~25% 0000: 0.125s 0001: 0.375s 0010: 0.625s ... 1000: 2.125s ...

© 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in part, is strictly prohibited.

Page 113 of 201

MT6360U PMIC Datasheet Confidential A Address

0x8F

0x90

Reg name

Bit

Bit name

Default

Type

3:0

ISINK2_BREATH _Tr2_SEL

0001

RW

7:4

ISINK2_BREATH _Tf1_SEL

0001

RW

3:0

ISINK2_BREATH _Tf2_SEL

0001

RW

7:4

ISINK2_BREATH 2_TON_SEL

0001

RW

3:0

ISINK2_BREATH _TOFF_SEL

RGB2_Tf

RGB2_TON_T OFF

Description 1111: 3.875s 16 steps, 0.25s/step Selects ISINK2 breath mode second rising time 0000: 0.125s 0001: 0.375s 0010: 0.625s ... 1000: 2.125s ... 1111: 3.875s 16 steps, 0.25s/step Selects ISINK2 breath mode first falling time Duty: 100~25% 0000: 0.125s 0001: 0.375s 0010: 0.625s ... 1000: 2.125s ... 1111: 3.875s 16 steps, 0.25s/step Selects ISINK2 breath mode second falling time Duty: 25~0% 0000: 0.125s 0001: 0.375s 0010: 0.625s ... 1000: 2.125s ... 1111: 3.875s 16 steps, 0.25s/step Selects ISINK2 breath mode on-time 0000: 0.125s 0001: 0.375s 0010: 0.625s ... 1000: 2.125s ... 1111: 3.875s 16 steps, 0.25s/step

Selects ISINK2 breath mode off-time

MediaTek Proprietary and Confidential.

0101

RW

0000: 0.25s 0001: 0.75s 0010: 1.25s ... 1000: 4.25s

© 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in part, is strictly prohibited.

Page 114 of 201

MT6360U PMIC Datasheet Confidential A Address

0x91

0x92

Reg name

Bit

Bit name

Default

Type

7:4

ISINK3_BREATH _Tr1_SEL

0001

RW

3:0

ISINK3_BREATH _Tr2_SEL

0001

RW

7:4

ISINK3_BREATH _Tf1_SEL

0001

RW

3:0

ISINK3_BREATH _Tf2_SEL

0001

RW

RGB3_Tr

RGB3_Tf

Description ... 1111: 7.75s 16 steps, 0.5s/step Selects ISINK3 breath mode first rising time Duty: 0~25% 0000: 0.125s 0001: 0.375s 0010: 0.625s ... 1000: 2.125s ... 1111: 3.875s 16 steps, 0.25s/step Selects ISINK3 breath mode second rising time Duty: 25~100% 0000: 0.125s 0001: 0.375s 0010: 0.625s ... 1000: 2.125s ... 1111: 3.875s 16 steps, 0.25s/step Selects ISINK3 breath mode first falling time Duty: 100~25% 0000: 0.125s 0001: 0.375s 0010: 0.625s ... 1000: 2.125s ... 1111: 3.875s 16 steps, 0.25s/step Selects ISINK3 breath mode second falling time Duty: 25~0% 0000: 0.125s 0001: 0.375s 0010: 0.625s ...

1000: 2.125s

0x93

RGB3_TON_T OFF

MediaTek Proprietary and Confidential.

7:4

ISINK3_BREATH _TON_SEL

0001

RW

... 1111: 3.875s 16 steps, 0.25s/step Selects ISINK3 breath mode on-time 0000: 0.125s

© 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in part, is strictly prohibited.

Page 115 of 201

MT6360U PMIC Datasheet Confidential A Address

0xD0

Reg name

Bit

Default

Type

3:0

ISINK3_BREATH _TOFF_SEL

0001

RW

7

PWR_RDY_EVT

0

WC

6

CHG_MIVR_EVT

0

WC

5

CHG_AICR_EVT

0

WC

4

CHG_TREG_EVT

0

WC

0000

R

CHG_IRQ1

3:0

0xD1

Bit name

Reserved

7

CHG_VINOVPCH G_EVT

0

WC

6

CHG_VBATOV_E VT

0

WC

0

WC

CHG_IRQ2 CHG_VSYSOV_E VT

4 MediaTek Proprietary and Confidential.

CHG_VSYSUV_E VT

Description 0001: 0.375s 0010: 0.625s ... 1000: 2.125s ... 1111: 3.875s 16 steps, 0.25s/step Selects ISINK3 breath mode off-time 0000: 0.25s 0001: 0.75s 0010: 1.25s ... 1000: 4.25s ... 1111: 7.75s 16 steps, 0.5s/step Power ready detection result Input power is good, UVLO < VIN < VOVP and VIN > BATS + VSLP 0: No operation 1: Event occurs. Charger warning Input voltage MIVR loop active 0: No operation 1: Event occurs. Charger warning Input current AICR loop active 0: No operation 1: Event occurs. Charger warning Thermal regulation loop active 0: No operation 1: Event occurs. Reserved CHG_VIN over-voltage protection fault This will forbid charger operation. 0: No operation 1: Event occurs. Charger fault Battery OVP fault 0: No operation 1: Event occurs. Charger fault System OVP fault 0: No operation 1: Event occurs. Charger fault System UVP fault 0: No operation 1: Event occurs.

© 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in part, is strictly prohibited.

Page 116 of 201

MT6360U PMIC Datasheet Confidential A Address

0xD3

0xD4

Reg name

CHG_IRQ4

Bit

Bit name

Default

Type

3

FLED_CHG_VIN OVP_EVT

0

WC

2

Reserved

0

R

1

CHG_BATSYSUV _EVT

0

WC

0

Reserved

0

R

7

OTPI_EVT

0

WC

6

CHG_RVPI_EVT

0

WC

5

CHG_ADPBADI_ EVT

0

WC

4

Reserved

0

R

3

CHG_TMRI_EVT

0

WC

2

WD_PMU_DON E

0

WC

1

WD_PMU_DET

0

WC

0

Reserved

0

R

7

CHG_IEOCI_EVT

0

WC

6

CHG_TERMI_EV T

0

WC

5

Reserved

0

WC

4

SSFINISHI_EVT

0

WC

3

WDTMRI_EVT

0

WC

2 1

Reserved Reserved

0 0

R R

CHG_IRQ5

Description CHG_VIN over 5.6V voltage protection fault which only works when FLED is on and will forbid strobe operation 0: No operation 1: Event occurs. Reserved The voltage: MAX (VBAT,VSYS) UVLO's event 0: No fault occurs. 1: Fault ever occurs. Reserved Thermal shutdown fault 0: No operation 1: Event occurs. Charger reverse protection fault 0: No event occurs 1: Event occurs. Charger bad adapter fault 0: No event occurs 1: Event occurs. Reserved Charger timer timeout fault 0: No event occurs. 1: Event occurs. PMU WD done event 0: No event occurs. 1: Event occurs. PMU WD status event 0: No event occurs. 1: Event occurs. Reserved Charging current is lower than EOC current event occurs 0: No event occurs. 1: Event occurs. Charge termination event 0: No event occurs. 1: Event occurs. Reserved Charger or boost soft-start finishes event 0: No event occurs. 1: Event occurs.

Watchdog timer timeout fault

MediaTek Proprietary and Confidential.

0: No event occurs. 1: Event occurs. Reserved Reserved

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Page 117 of 201

MT6360U PMIC Datasheet Confidential A Address

0xD5

0xD6

Reg name

Bit

Bit name

Default

Type

0

CHG_AICCMeasI _EVT

0

WC

7

BST_OLPI_EVT

0

WC

6

BST_MIDOVI_E VT

0

WC

5

BST_BATUVI_EV T

0

WC

4

ADC_DONEI

0

WC

3

ADC_WAKEUP_ EVT

0

WC

2

Reserved

0

R

1

BAT_OVP_ADC_ EVT

0

WC

0

PUMPX_DONEI_ EVT

0

WC

7

DCDTI_EVT

0

WC

CHG_IRQ6

6:2

Reserved

00000

R

1

Detach_I

0

WC

0

Attach_I

0

WC

7:5

Reserved

000

R

0

WC

0

WC

DPDM IRQ

0xD7

4

3

MediaTek Proprietary and Confidential.

CHRDETB_EXT_

CHRDETB_OVP_ EVT

Description AICC measurement function done event 0: No event occurs. 1: Event occurs. Boost overload protection event 0: No event occurs. 1: Event occurs. Boost CHG_VMID OVP fault event 0: No event occurs. 1: Event occurs. Boost low voltage input fault event 0: No event occurs. 1: Event occurs. ADC measurement done event 0: No event occurs. 1: Event occurs. ADC wake-up event 0: No event occurs. 1: Event occurs. Reserved BAT_OVP_ADC fault event 0: No event occurs. 1: Event occurs. MTK pump express function done event 0: No event occurs. 1: Event occurs. Data contact detection event 0: Data contact detection timeout is not detected. 1: Data contact detection timeout is detected when DCDT goes from 0 to 1. Reserved VBUS detach, when VBUSPG_D goes from 1 to 0 0: No event occurs. 1: Event occurs. Charger type detection done event 0: No event occurs. 1: Event occurs. Reserved Detects VBUS voltage 0: No event 1: VBUS enters or releases from normal region which is between UV_TH and OV_TH. VBUS OVP detection (deglitch 1 ms) 0: No event occurs.

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Page 118 of 201

MT6360U PMIC Datasheet Confidential A Address

Reg name

Bit

Bit name

Default

Type

2

CHRDETB_UVPB _EVT

0

WC

Reserved

00

R

7

SYSUV_EVT

0

WC

6

VDDAOV_EVT

0

WC

5

OTP_EVT

0

WC

4

MRSTB_EVT

0

WC

3

QONB_RST_EVT

0

WC

2

EN_EVT

0

WC

1

APWDTRST_EVT

0

WC

0

USBID_EVT

0

WC

7

FLED1_SHORT_ EVT

0

WC

1:0

0xD8

BASE_IRQ

Description 1: Event occurs VBUS entry or release of OV_TH. VBUS UVP detection (deglitch 1 ms) 0: No event occurs. 1: Event occurs VBUS entry or release of UV_TH. Reserved Reports whether the protection event of SYS UVLO occurs 0: No protection event occurs. 1: Protection event ever occurs. Reports whether the protection event of VDDA OVP occurs 0: No protection event occurs. 1: Protection event ever occurs. Reports whether the protection event of OTP ever occurs 0: No protection event occurs. 1: Protection event ever occurs. Reports whether the reset event of MRSTB ever occurs 0: No reset event occurs. 1: Reset event ever occurs. Reports whether the reset event of QONB Reset ever occurs 0: No reset event occurs. 1: Reset event ever occurs. Reports whether the EN pin ever switches 0: No switch occurs. 1: Switch ever occurs. Reports whether the reset event of APWDTRST ever occurs 0: No reset event occurs. 1: Reset event ever occurs. USB_ID interrupt (rising/falling trigger) 0: No event 1: Voltage of USB_ID > VTH_ID Reports whether the event of FLED1 short-circuit occurs 0: No event occurs. 1: Event ever occurs. Reports whether the event of FLED2

short-circuit occurs0xD9 EVT 5:4 3 MediaTek Proprietary and Confidential.

Reserved

00

R

FLED_LVF_EVT

0

WC

0: No event occurs. 1: Event ever occurs. Reserved Reports whether the event of FLED low VF occurs

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Page 119 of 201

MT6360U PMIC Datasheet Confidential A Address

Reg name

Bit

Default

Type

2

FLED_TX_EVT

0

WC

1

FLED_TORPIN_E VT

0

WC

0

FLED_STRBPIN_ EVT

0

WC

Reserved

00

R

5

FLED1_TOR_EVT

0

WC

4

FLED2_TOR_EVT

0

WC

3

FLED1_STRB_TO _EVT

0

WC

2

FLED2_STRB_TO _EVT

0

WC

1

FLED1_STRB_EV T

0

WC

0

FLED2_STRB_EV T

0

WC

7

Reserved

0

R

6

BUCK1_UV_EVT

0

WC

5

BUCK1_OV_EVT

0

WC

7:6

0xDA

Bit name

FLED_IRQ2

Description 0: No event occurs. 1: Event ever occurs. Reports whether the event of FLED TXMask occurs (If sENB_TX = 1'b1, this event will not interrupt.) 0: No event occurs. 1: Event ever occurs. Reports whether the event of FLED torch pin occurs 0: No event occurs. 1: Event ever occurs. Reports whether the event of FLED strobe pin occurs 0: No event occurs. 1: Event ever occurs. Reserved Reports whether the event of FLED1 torch occurs 0: No event occurs. 1: Event ever occurs. Reports whether the event of FLED2 torch occurs 0: No event occurs. 1: Event ever occurs. Reports whether the event of FLED1 strobe timeout occurs 0: No event occurs. 1: Event ever occurs. Reports whether the event of FLED2 strobe timeout occurs 0: No event occurs. 1: Event ever occurs. Reports whether the event of FLED1 strobe occurs 0: No event occurs. 1: Event ever occurs. Reports whether the event of FLED2 strobe occurs 0: No event occurs. 1: Event ever occurs. Reserved Reports whether BUCK1 UV occurs 0: No event or be masked

0xDC 1: Protection ever occurs.

MediaTek Proprietary and Confidential.

Reports whether BUCK1 OV occurs 0: No event or be masked 1: Protection ever occurs.

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Page 120 of 201

MT6360U PMIC Datasheet Confidential A Address

Reg name

Bit

Bit name

Default

Type

4

BUCK1_OC_EVT

0

WC

000

R

3:1

0xDD

0

BUCK1_PGB_EV T

0

WC

7

Reserved

0

R

6

BUCK2_UV_EVT

0

WC

5

BUCK2_OV_EVT

0

WC

4

BUCK2_OC_EVT

0

WC

000

R

BUCK2_IRQ

3:1

0xDE

Reserved

LDO_EVT1

0: No protection event occurs.

0

BUCK2_PGB_EV T

0

WC

7

LDO7_OC_EVT

0

WC

6

LDO6_OC_EVT

0

WC

5

LDO5_OC_EVT

0

WC

4

Reserved

0

R

3

LDO3_OC_EVT

0

WC

2

LDO2_OC_EVT

0

WC

1

MediaTek Proprietary and Confidential.

Reserved

LDO1_OC_EVT

0

WC

Description Reports whether BUCK1 OC occurs 0: No event or be masked 1: Protection ever occurs. Reserved Reports whether BUCK1 PG fault occurs 0: No event or be masked 1: PG fault ever occurs. Reserved Reports whether BUCK2 UV occurs 0: No event or be masked 1: Protection ever occurs. Reports whether BUCK2 OV occurs 0: No event or be masked 1: Protection ever occurs. Reports whether BUCK2 OC occurs 0: No event or be masked 1: Protection ever occurs. Reserved Reports whether BUCK2 PG fault occurs 0: No event or be masked 1: PG fault ever occurs. Reports whether the event of LDO7 OC occurs 0: No protection event occurs. 1: Event ever occurs. Reports whether the event of LDO6 OC occurs 0: No protection event occurs. 1: Event ever occurs. Reports whether the event of LDO5 OC occurs 0: No protection event occurs. 1: Event ever occurs. Reserved Reports whether the event of LDO3 OC occurs 0: No protection event occurs. 1: Event ever occurs. Reports whether the event of LDO2 OC occurs 1: Event ever occurs. Reports whether the event of LDO1 OC occurs 0: No protection event occurs. 1: Event ever occurs.

© 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in part, is strictly prohibited.

Page 121 of 201

MT6360U PMIC Datasheet Confidential A Address

0xDF

0xE0

Reg name

LDO_EVT2

Bit 0

LDO7_PGB_EVT

0

6

LDO6_PGB_EVT

0

5

LDO5_PGB_EVT

0

4

Reserved

0

3

LDO3_PGB_EVT

0

2

LDO2_PGB_EVT

0

1

LDO1_PGB_EVT

0

0

Reserved

0

7

PWR_RDY_STAT

0

6

CHG_MIVR_STA T

0

5

CHG_AICR_STAT

0

4

CHG_TREG_STA T

0

3:0

0xE1

Default 0

7

CHG_STAT1

CHG_VIN

Bit name Reserved

Reserved

0000

7

CHG_VINOVPCH G_STAT

0

6

CHG_VBATOV_S TAT

0

CHG_STAT2

MediaTek Proprietary and Confidential.

Type Description R Reserved Reports whether LDO7 PG fault occurs WC 0: No event 1: PG fault ever occurs. Reports whether LDO6 PG fault occurs WC 0: No event 1: PG fault ever occurs. Reports whether LDO5 PG fault occurs WC 0: No event 1: PG fault ever occurs. R Reserved Reports whether LDO3 PG fault occurs WC 0: No event 1: PG fault ever occurs. Reports whether LDO2 PG fault occurs WC 0: No event 1: PG fault ever occurs. Reports whether LDO1 PG fault occurs WC 0: No event. 1: PG fault ever occurs. R Reserved Power ready status bit 0: Input power is bad, CHG_VIN > VOVP or CHG_VIN < VUVLO or CHG_VIN < R BATS + VSLP 1: Input power is good, UVLO < CHG_VIN < VOVP & CHG_VIN > BATS + VSLP Charger warning Input voltage MIVR loop active R 0: MIVR loop is not active. 1: MIVR loop is active. Charger warning Input current AICR loop active R 0: AICR loop is not active. 1: AICR loop is active. Charger warning Thermal regulation loop active R 0: Thermal regulation loop is not active. 1: Thermal regulation loop is active. R Reserved VCHG_VIN over-voltage protection (when VCHG_VIN > VCHG_VIN_OVP) R 0: V is not over-voltage. 1: VCHG_VIN is over-voltage. Charger fault Battery OVP R 0: Battery is not over-voltage. 1: Battery is over-voltage.

© 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in part, is strictly prohibited.

Page 122 of 201

MT6360U PMIC Datasheet Confidential A Address

0xE3

Reg name

Bit name

5

CHG_VSYSOV_S TAT

0

R

4

CHG_VSYSUV_S TAT

0

R

3

FLEDCHG_VINOVP_S TAT

0

R

2

Reserved

0

R

1

CHG_BATSYSUV _STAT

0

R

0

Reserved

0

R

7

OTPI_STAT

0

R

6

CHG_RVPI_STAT

0

R

5

CHG_ADPBADI_ STAT

0

R

4

Reserved

0

R

3

CHG_TMRI_STA T

0

R

2

WD_PMU_DON E_STAT

0

R

1

WD_PMU_DET_ STAT

0

R

0

Reserved

0

R

0

R

CHG_STAT4

7

0: Charger is not EOC. 0xE4

Bit

CHG_IEOCI_STA

Default

Type

CHG_STAT5

MediaTek Proprietary and Confidential.

6

CHG_TERMI_ST AT

0

R

5

Reserved

0

R

Description Charger fault System OVP 0: System is not over-voltage. 1: System is over-voltage. Charger fault System UVP 0: System is not under-voltage. 1: System is under-voltage. CHG_VIN over voltage protection which only works when FLED is on CHG_VINVOP threshold voltage = 5.6/5.3V 0: CHG_VIN is not over-voltage. 1: CHG_VIN is over-voltage. Reserved The voltage: MAX (VBAT, VSYS) UVLO’s state 0: Max (VBAT, VSYS) is not UVLO. 1: Max (VBAT, VSYS) is UVLO. Reserved Thermal shutdown status 0: IC is not thermal shutdown. 1: IC is thermal down. Charger reverse protection status 0: Charger is not charger reverse protection. 1: Charger is charger reverse protection. Charger bad adapter status 0: Charger is not bad adapter. 1: Charger is bad adapter. Reserved Charger timer timeout status 0: Charger does not time out. 1: Charger times out. Reserved for WD_PMU_DONE_STAT (short pulse, hard be read by I2C) PMU WD status 0: PMU is not in WD. 1: PMU is in WD. Reserved Charging current is lower than EOC current status. 1: Charger is EOC. Charge terminated status 0: Charger is not terminated. 1: Charger is terminated. Reserved

© 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in part, is strictly prohibited.

Page 123 of 201

MT6360U PMIC Datasheet Confidential A Address

Reg name

Bit

Bit name

Default

Type

4

SSFINISHI_STAT

0

R

3

WDTMRI_STAT

0

R

Reserved

00

R

0

CHG_AICCMeasI _STAT

0

R

7

BST_OLPI_STAT

0

R

6

BST_MIDOVI_ST AT

0

R

5

BST_BATUVI_ST AT

0

R

0

R

0

R

0

R

2:1

0xE5

CHG_STAT6

4 3 2

0xE6

ADC_DONEI_ST AT ADC_WAKEUP_ STAT Reserved

1

BAT_OVP_ADC_ STAT

0

R

0

PUMPX_DONEI_ STAT

0

R

7

DCDTI_STAT

0

R

6

CHGDETI_STAT

0

R

DPDM_STAT

(charger port is not detected)

5:2 1 MediaTek Proprietary and Confidential.

Reserved Detach_I_STAT

0000

R

0

R

Description Charger or boost soft-start finish status 0: Charger is not soft start finish. 1: Charger is soft start finish. Watchdog timer timeout fault status 0: Charger is not watchdog timer timeout. 1: If CHG_WDT_EN (0x1D[7] = 1) and I2C is no read/write, charger watchdog timer is timeout by CHG_WDT[1:0] (0x1D[5:4]). Then, WDWTMRI_STAT = 1. Reserved AICC measurement function done status 0: AICC is not done. 1: AICC is done. Boost overload protection status 0: Boost is not overload. 1: Boost is overload. Boost CHG_VMID OVP fault status 0: Boost is not OVP. 1: Boost is OVP. Boost low voltage input fault status 0: Boost is not low voltage input. 1: Boost is low voltage input. Reserved for ADC_DONEI (short pulse, hard be read by I2C) Reserved for ADC_WAKEUP (short pulse, hard be read by I2C) Reserved BAT_OVP_ADC fault status 0: BAT is not OVP. 1: BAT is OVP. Reserved for PUMPX_DONEI_STAT (short pulse, hard be read by I2C) Data contact detection event 0: Data contact detection timeout is not detected. 1: Data contact detection timeout is detected when DCDT goes from 0 to 1. Output of USB charger detection The bit will be set to 1 if COMN > VDAT_REF & COMN < VLGC 0: COMN < VDAT_REF or COMN > VLGC 1: COMN > VDAT_REF & COMN < VLGC (charger port is detected) when CHGDET goes from 0 to 1 Reserved VBUS detach, when VBUSPG_D goes from 1 to 0

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Page 124 of 201

MT6360U PMIC Datasheet Confidential A Address

Reg name

Bit

Bit name

Default

Type

0

CHGDET_DONEI _ STAT

0

R

000

R

7:5

0xE7

CHRDETB_STA T

4

CHRDETB_EXT_ STAT

0

R

3

CHRDETB_OVP_ STAT

0

R

2

CHRDETB_UVPB _STAT

0

R

Reserved

00

R

7

SYSUV_STAT

0

R

6

VDDAOV_STAT

0

R

5

OTP_STAT

0

R

4

MRSTB_STAT

0

R

3

QONB_RST_STA T

0

R

2

EN_STAT

0

R

1

APWDTRST_STA T

o

R

0

USBID_STAT

0

R

7

FLED1_SHORT_S TAT

1:0

0xE8

BASE_STAT

Reserved

Description 0: VBUS is valid. 1: VBUS is invalid. Charger type detection done 0: No operation or charger type detection is detecting. 1: Charger type detection is done. Reserved Detects VBUS voltage 0: VBUS ≤ VBUS_UV_TH or VBUS ≥ VBUS_OV_TH 1: VBUS_UV_TH < VBUS < VBUS_OV_TH VBUS OV detection (deglitch 1 ms) 0: State low than OV_TH 1: State high than OV_TH VBUS UV detection (deglitch 1 ms) 0: State low than UV_TH 1: State high than UV_TH Reserved SYS UVLO status 0: SYSUVLO is off or VSYS is not undervoltage. 1: VSYS is under-voltage. VDDA OVP status 0: VDDAOVP is off or VDDA is not overvoltage. 1: VDDA is over-voltage. OTP status 0: OTPs are off or IC is not overtemperature. 1: IC is over-temperature. Reserved for MRSTB_STAT (short pulse, hard be read by I2C) Reserved for QONB_RST_STAT (short pulse, hard be read by I2C) EN pin status (with 128μs de-bounding time) 0: EN pin is logic low. 1: EN pin is logic high. Reserved for APWDTRST_STAT (short pulse, hard be read by I2C) Report USB_ID detector result 0: The voltage of USB_ID < VTH_ID or disable detector

1: The voltage of USB_ID > VTH_ID 0xE9

FLED_STAT1

MediaTek Proprietary and Confidential.

0

R

FLED1 short-circuit status 0: FLED1 short-circuit does not occur. 1: FLED1 short-circuit occurs.

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Page 125 of 201

MT6360U PMIC Datasheet Confidential A Address

Reg name

Bit

Bit name

Default

Type

6

FLED2_SHORT_S TAT

0

R

Reserved

00

R

3

FLED_LVF_STAT

0

R

2

FLED_TX_STAT

0

R

1

FLED_TORPIN_S TAT

0

R

0

FLED_STRBPIN_ STAT

0

R

Reserved

00

R

5

FLED1_TOR_STA T

0

R

4

FLED2_TOR_STA T

0

R

3

FLED1_STRB_TO _STAT

0

R

2

FLED2_STRB_TO _STAT

0

R

1

FLED1_STRB_ST AT

0

R

0

FLED2_STRB_ST AT

0

R

7

Reserved

0

R

6

BUCK1_UV_STA T

0

R

5

BUCK1_OV_STA T

0

R

4

BUCK1_OC_STA T

5:4

7:6

0xEA

0xEC

FLED_STAT2

BUCK1_STAT

Description FLED2 short-circuit status 0: FLED2 short-circuit does not occur. 1: FLED2 short-circuit occurs. Reserved FLED low-VF status 0: FLED low-VF does not occur. 1: FLED low-VF occurs. FLED TXMask status 0: FLED TXMask does not occur. 1: FLED TXMask occurs. FLED torch pin status 0: FLED torch pin does not occur. 1: FLED torch pin occurs. FLED strobe pin status 0: FLED strobe pin does not occur. 1: FLED strobe pin occurs. Reserved FLED1 torch mode status 0: FLED1 torch mode does not occur. 1: FLED1 torch mode occurs. FLED2 torch mode status 0: FLED2 Torch mode does not occur. 1: FLED2 Torch mode occurs. FLED1 strobe timeout status 0: FLED1 strobe timeout does not occur. 1: FLED1 strobe timeout occurs. FLED2 strobe timeout status 0: FLED2 strobe timeout does not occur. 1: FLED2 strobe timeout occurs. FLED1 strobe mode status 0: PFLED1 strobe does not occur. 1: FLED1 strobe occurs. FLED2 strobe mode status 0: FLED2 strobe does not occur. 1: FLED2 strobe occurs. Reserved Reports BUCK1 UV state 0: BUCK1 is off or BUCK1_VOUT is not under-voltage. 1: BUCK1_VOUT is under-voltage. Reports BUCK1 OV state 0: BUCK1 is off or BUCK1_VOUT is not over-voltage.

1: BUCK1_VOUT is over-voltage.

3:1 MediaTek Proprietary and Confidential.

Reserved

0

R

000

R

Reports BUCK1 OC state 0: BUCK1 is off or BUCK1 over-current does not occur. 1: BUCK1 over-current occurs. Reserved

© 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in part, is strictly prohibited.

Page 126 of 201

MT6360U PMIC Datasheet Confidential A Address

0xED

Reg name

Bit

Bit name

Default

Type

0

BUCK1_PGB_ST AT

0

R

7

Reserved

0

R

6

BUCK2_UV_STA T

0

R

5

BUCK2_OV_STA T

0

R

4

BUCK2_OC_STA T

0

R

000

R

BUCK2_STAT

3:1

0xEE

LDO_STAT1

Reserved

0

BUCK2_PGB_ST AT

0

R

7

LDO7_OC_STAT

0

R

6

LDO6_OC_STAT

0

R

5

LDO5_OC_STAT

0

R

4

Reserved

0

R

3

LDO3_OC_STAT

0

R

2

LDO2_OC_STAT

0

R

Description Reports BUCK1 PG fault state 0: BUCK1 is off or BUCK1 PG fault does not occur. 1: BUCK1 PG fault occurs. Reserved Reports BUCK2 UV state 0: BUCK2 is off or BUCK2_VOUT is not under-voltage. 1: BUCK2_VOUT is under-voltage. Reports BUCK2 OV state 0: BUCK2 is off or BUCK2_VOUT is not over-voltage. 1: BUCK2_VOUT is over-voltage. Reports BUCK2 OC state 0: BUCK1 is off or BUCK2 over-current does not occur. 1: BUCK2 over-current occurs. Reserved Reports BUCK2 PG fault state 0: BUCK2 is off or BUCK2 PG fault does not occur. 1: BUCK2 PG fault occurs. Reports whether the event of LDO7 OC occurs 0: LDO7 is off or LDO7 over-current does not occur. 1: LDO7 over-current occurs. Reports whether the event of LDO6 OC occurs 0: LDO6 is off or LDO6 over-current does not occur. 1: LDO6 over-current occurs. Reports whether the event of LDO5 OC occurs 0: LDO5 is off or LDO5 over-current does not occur. 1: LDO5 over-current occurs. Reserved Reports whether the event of LDO3 OC occurs 0: LDO3 is off or LDO3 over-current does not occur. 1: LDO3 over-current occurs.

Reports whether the event of LDO2 OC

MediaTek Proprietary and Confidential.

occurs 0: LDO2 is off or LDO2 over-current does not occur. 1: LDO2 over-current occurs.

© 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in part, is strictly prohibited.

Page 127 of 201

MT6360U PMIC Datasheet Confidential A Address

0xEF

0xF0

Reg name

LDO_STAT2

Bit

Bit name

Default

Type

1

LDO1_OC_STAT

0

R

0

Reserved

0

R

7

LDO7_PGB_STA T

0

R

6

LDO6_PGB_STA T

0

R

5

LDO5_PGB_STA T

0

R

4

Reserved

0

R

3

LDO3_PGB_STA T

0

R

2

LDO2_PGB_STA T

0

R

1

LDO1_PGB_STA T

0

R

0

Reserved

0

R

7

PWR_RDYM

1

RW

6

CHG_MIVRM

1

RW

5

CHG_AICRM

1

RW

4

CHG_TREGM

1

RW

1111

R

CHG_MASK1

Description Reports whether the event of LDO1 OC occurs 0: LDO1 is off or LDO1 over-current does not occur. 1: LDO1 over-current occurs. Reserved Reports LDO7 PG fault state 0: LDO7 is off or LDO7 PG fault does not occur. 1: LDO7 PG fault occurs. Reports LDO6 PG fault state 0: LDO6 is off or LDO6 PG fault does not occur. 1: LDO6 PG fault occurs. Reports LDO5 PG fault state 0: LDO5 is off or LDO5 PG fault does not occur. 1: LDO5 PG fault occurs. Reserved Reports LDO3 PG fault state 0: LDO3 is off or LDO3 PG fault does not occur. 1: LDO3 PG fault occurs. Reports LDO2 PG fault state 0: LDO2 is off or LDO2 PG fault does not occur. 1: LDO2 PG fault occurs. Reports LDO1 PG fault state 0: LDO1 is off or LDO1 PG fault does not occur. 1: LDO1 PG fault occurs. Reserved Power ready interrupt mask 0: Interrupt is not masked. 1: Interrupt is masked. Input voltage MIVR loop active interrupt mask 0: Interrupt is not masked. 1: Interrupt is masked. Input current AICR loop active interrupt mask 0: Interrupt is not masked. 1: Interrupt is masked.

Thermal regulation loop active

3:0

MediaTek Proprietary and Confidential.

Reserved

interrupt mask 0: Interrupt is not masked. 1: Interrupt is masked. Reserved

© 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in part, is strictly prohibited.

Page 128 of 201

MT6360U PMIC Datasheet Confidential A Address

0xF1

0xF3

Reg name

Bit

Bit name

Default

Type

7

CHG_VINOVPCH GM

1

RW

6

CHG_VBATOVM

1

RW

5

CHG_VSYSOVM

1

RW

4

CHG_VSYSUVM

1

RW

3

FLEDCHG_VINOVPM

1

RW

2

Reserved

1

R

1

CHG_BATSYSUV M

1

RW

0

Reserved

1

R

7

OTPM

1

RW

6

CHG_RVPM

1

RW

5

CHG_ADPBADM

1

RW

4

Reserved

1

R

3

CHG_TMRM

1

RW

2

WD_PMU_DON EM

1

RW

1

RW

CHG_MASK2

CHG_MASK4

1

0xF4

CHG_MASK5

MediaTek Proprietary and Confidential.

M

0

Reserved

1

R

7

CHG_IEOCM

1

RW

Description CHG_VIN over-voltage protection mask 0: Interrupt is not masked. 1: Interrupt is masked. Battery OVP interrupt mask 0: Interrupt is not masked. 1: Interrupt is masked. System OVP interrupt mask 0: Interrupt is not masked. 1: Interrupt is masked. System UVP interrupt mask 0: Interrupt is not masked. 1: Interrupt is masked. CHG_VIN over 5.6V voltage protection mask which only works when FLED is on 0: Interrupt is not masked. 1: Interrupt is masked. Reserved The voltage: MAX (VBAT, VSYS) UVLO's mask 0: Interrupt is not masked. 1: Interrupt is masked. Reserved Thermal shutdown fault interrupt mask 0: Interrupt is not masked. 1: Interrupt is masked. Charger reverse protection fault interrupt mask 0: Interrupt is not masked. 1: Interrupt is masked. Charger bad adapter fault interrupt mask 0: Interrupt is not masked. 1: Interrupt is masked. Reserved Charger timer timeout fault interrupt mask 0: Interrupt is not masked. 1: Interrupt is masked. PMU WD done interrupt mask 0: Interrupt is not masked. 1: Interrupt is masked. PMU WD status interrupt mask 0: Interrupt is not masked. 1: Interrupt is masked. Reserved Charging current is lower than EOC current interrupt mask

© 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in part, is strictly prohibited.

Page 129 of 201

MT6360U PMIC Datasheet Confidential A Address

0xF5

Reg name

Bit

Bit name

Default

Type

6

CHG_TERMM

1

RW

5

Reserved

1

R

4

SSFINISHM

1

RW

3

WDTMRM

1

RW

2

CHGDET_DONE M

1

RW

1

Reserved

1

R

0

CHG_AICCMeas M

1

RW

7

BST_OLPM

1

RW

6

BST_MIDOVM

1

RW

5

BST_BATUVM

1

RW

4

ADC_DONEM

1

RW

3

ADC_WAKEUP_ MASK

1

RW

1

BAT_OVP_ADC_ MASK

1

RW

0

PUMPX_DONE M

1

RW

CHG_MASK6

Description 0: Interrupt is not masked. 1: Interrupt is masked. Charge terminated event interrupt mask 0: Interrupt is not masked. 1: Interrupt is masked. Reserved Charger or boost soft start finishes event interrupt mask 0: Interrupt is not masked. 1: Interrupt is masked. Watchdog timer timeout fault interrupt mask 0: Interrupt is not masked. 1: Interrupt is masked. Charger type detection done event interrupt mask 0: Interrupt is not masked. 1: Interrupt is masked. Reserved AICC measurement function done event interrupt mask 0: Interrupt is not masked. 1: Interrupt is masked. Boost overload protection event interrupt mask 0: Interrupt is not masked. 1: Interrupt is masked. Boost CHG_VMID OVP fault event interrupt mask 0: Interrupt is not masked. 1: Interrupt is masked. Boost low voltage input fault event interrupt mask 0: Interrupt is not masked. 1: Interrupt is masked. ADC measurement done event interrupt mask 0: Interrupt is not masked. 1: Interrupt is masked. ADC wake up event interrupt mask 0: Interrupt is not masked. 1: Interrupt is masked.

Reserved

MediaTek Proprietary and Confidential.

BAT_OVP_ADC fault event interrupt mask 0: Interrupt is not masked. 1: Interrupt is masked. MTK pump express function done event interrupt mask

© 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in part, is strictly prohibited.

Page 130 of 201

MT6360U PMIC Datasheet Confidential A Address

0xF6

Reg name

DPDM_MASK 1

Bit

CHRDETB_MA SK

BASE_MASK

1

RW

6

CHGDETM

1

RW

5:2

Reserved

1111

R

1

Detach_M

1

RW

0

CHGDET_DONEI _M

1

RW

000

R

Confidential.

Reserved

4

CHRDETB_EXT_ MASK

0

RW

3

CHRDETB_OVP_ MASK

1

RW

2

CHRDETB_UVPB _MASK

1

RW

Reserved

00

R

7

SYSUV_MASK

1

RW

6

VDDAOV_MASK

1

RW

5

OTP_MASK

1

RW

4

MRSTB_MASK

1

RW

3

QONB_RST_MA SK

1

RW

2

EN_MASK

1

RW

1

APWDTRST_MA SK

1

RW

1: Interrupt is masked.

MediaTek Proprietary and

Type

DCDTM

1:0

0xF8

Default

7

7:5

0xF7

Bit name

Description 0: Interrupt is not masked. 1: Interrupt is masked. Data contact detection event interrupt mask 0: Interrupt is not masked. 1: Interrupt is masked. Output of USB charger detection interrupt mask 0: Interrupt is not masked. 1: Interrupt is masked. Reserved VBUS detach event interrupt mask 0: Interrupt is not masked. 1: Interrupt is masked. Charger type detection done interrupt mask 0: Interrupt is not masked. 1: Interrupt is masked. Reserved VBUS EXT interrupt mask 0: Interrupt is not masked. 1: Interrupt is masked. VBUS OVP interrupt mask 0: Interrupt is not masked. 1: Interrupt is masked. VBUS UVP interrupt mask 0: Interrupt is not masked. 1: Interrupt is masked. Reserved SYS UVLO interrupt mask 0: Interrupt is not masked. 1: Interrupt is masked. VDDA OVP interrupt mask 0: Interrupt is not masked. 1: Interrupt is masked. OTP interrupt mask 0: Interrupt is not masked. 1: Interrupt is masked. MRSTB reset interrupt mask 0: Interrupt is not masked. 1: Interrupt is masked. QONB reset interrupt mask 0: Interrupt is not masked. EN interrupt mask 0: Interrupt is not masked. 1: Interrupt is masked. APWDTRST interrupt mask 0: Interrupt is not masked.

© 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in part, is strictly prohibited.

Page 131 of 201

MT6360U PMIC Datasheet Confidential A Address

Reg name

Bit

0xF9

Type

USB_ID_MASK

1

RW

7

FLED1_SHORT_ MASK

1

RW

6

FLED2_SHORT_ MASK

1

RW

Reserved

11

R

3

FLED_LVF_MAS K

1

RW

2

FLED_TX_MASK

1

RW

1

FLED_TORPIN_ MASK

1

RW

0

FLED_STRBPIN_ MASK

1

RW

Reserved

11

R

5

FLED1_TOR_MA SK

1

RW

4

FLED2_TOR_MA SK

1

RW

3

FLED1_STRB_TO _MASK

1

RW

2

FLED2_STRB_TO _MASK

1

RW

1

FLED1_STRB_M ASK

1

RW

0

FLED2_STRB_M ASK

1

RW

7

BUCK1_FAULTB _MASK

0

RW

7:6

0xFA

Default

0

5:4 FLED_ MASK1

Bit name

FLED_MASK3

Description 1: Interrupt is masked. USB_ID interrupt mask 0: Interrupt is not masked. 1: Interrupt is masked. FLED1 short-circuit mask 0: Interrupt is not masked. 1: Interrupt is masked. FLED2 short-circuit mask 0: Interrupt is not masked. 1: Interrupt is masked. Reserved FLED low-VF mask 0: Interrupt is not masked. 1: Interrupt is masked. FLED TXMask mask 0: Interrupt is not masked. 1: Interrupt is masked. FL_TORCH pin mask 0: Interrupt is not masked. 1: Interrupt is masked. FL_STROBE pin mask 0: Interrupt is not masked. 1: Interrupt is masked. Reserved FLED1 torch interrupt mask 0: Interrupt is not masked. 1: Interrupt is masked. FLED2 torch interrupt mask 0: Interrupt is not masked. 1: Interrupt is masked. FLED1 strobe timeout interrupt mask 0: Interrupt is not masked. 1: Interrupt is masked. FLED2 strobe timeout interrupt mask 0: Interrupt is not masked. 1: Interrupt is masked. FLED1 strobe interrupt mask 0: Interrupt is not masked. 1: Interrupt is masked. FLED2 strobe interrupt mask 0: Interrupt is not masked. 1: Interrupt is masked. BUCK1 PGB FAULTB MASK

0: FAULTB is not masked. 0xFB

FAULTB_MASK

MediaTek Proprietary and Confidential.

1: FAULTB is masked. Note: If BUCK1 is not in sequence, this bit’s default value is 1’b1. If BUCK1 is in sequence, this bit’s default is 1’b0.

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Page 132 of 201

MT6360U PMIC Datasheet Confidential A Address

0xFC

Reg name

BUCK_MASK

Bit

Bit name

Default

Type

6

BUCK2_FAULTB _MASK

1

RW

5

LDO7_FAULTB_ MASK

0

RW

4

LDO6_FAULTB_ MASK

0

RW

3

LDO5_FAULTB_ MASK

1

RW

2

LDO3_FAULTB_ MASK

1

RW

1

LDO2_FAULTB_ MASK

1

RW

0

LDO1_FAULTB_ MASK

1

RW

7

Reserved

1

R

6

BUCK1_UV_MA SK

1

RW

5

BUCK1_OV_MA SK

1

RW

4

BUCK1_OC_MA SK

1

RW

111

R

1

RW

1

R

1

RW

3:1

0

7 0xFD

BUCK_MASK

MediaTek Proprietary and Confidential.

6

Reserved BUCK1_PGB_M

Reserved BUCK2_UV_MA SK

Description BUCK2 PGB FAULTB MASK 0: FAULTB is not masked. 1: FAULTB is masked. Note: If BUCK2 is not in sequence, this bit’s default value is 1’b1. If BUCK2 is in sequence, this bit’s default is 1’b0. LDO7 PGB FAULTB MASK 0: FAULTB is not masked. 1: FAULTB is masked. Note: If LDO7 is not in sequence, this bit’s default value is 1’b1. If LDO7 is in sequence, this bit’s default is 1’b0. LDO6 PGB FAULTB MASK 0: FAULTB is not masked. 1: FAULTB is masked. Note: If LDO6 is not in sequence, this bit’s default value is 1’b1. If LDO6 is in sequence, this bit’s default is 1’b0. LDO5 PGB FAULTB MASK 0: FAULTB is not masked. 1: FAULTB is masked. LDO3 PGB FAULTB MASK 0: FAULTB is not masked. 1: FAULTB is masked. LDO2 PGB FAULTB MASK 0: FAULTB is not masked. 1: FAULTB is masked. LDO1 PGB FAULTB MASK 0: FAULTB is not masked. 1: FAULTB is masked. Reserved BUCK1 UV interrupt's mask 0: Interrupt is not masked. 1: Interrupt is masked. BUCK1 OV interrupt's mask 0: Interrupt is not masked. 1: Interrupt is masked. BUCK1 OC interrupt's mask 0: Interrupt is not masked. 1: Interrupt is masked. Reserved BUCK1 PG Fault interrupt's mask 0: Interrupt is not masked. 1: Interrupt is masked. Note: If BUCK1 is in sequence, this bit's default value will be 1'b0. Reserved BUCK2 UV interrupt's mask 0: Interrupt is not masked.

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Page 133 of 201

MT6360U PMIC Datasheet Confidential A Address

Reg name

Bit

Bit name

5

BUCK2_OV_MA SK

1

RW

4

BUCK2_OC_MA SK

1

RW

111

RW

3:1

0xFE

0xFF

LDO_MASK1

BUCK2_PGB_M ASK

1

RW

7

LDO7_OC_MAS K

1

RW

6

LDO6_OC_MAS K

1

RW

5

LDO5_OC_MAS K

1

RW

4

Reserved

1

R

3

LDO3_OC_MAS K

1

RW

2

LDO2_OC_MAS K

1

RW

1

LDO1_OC_MAS K

1

RW

0

Reserved

1

R

7

LDO7_PGB_MA SK

1

RW

6

LDO6_PGB_MA SK

1

RW

5

LDO5_PGB_MA SK

1

RW

4

Reserved

1

R

3

LDO3_PGB_MA SK

1

RW

1: Interrupt is masked.

Confidential.

Type

1

LDO_MASK2

MediaTek Proprietary and

Reserved

Default

Description 1: Interrupt is masked. BUCK2 OV interrupt's mask 0: Interrupt is not masked. 1: Interrupt is masked. BUCK2 OC interrupt's mask 0: Interrupt is not masked. 1: Interrupt is masked. Reserved BUCK2 PG fault interrupt's mask 0: Interrupt is not masked. 1: Interrupt is masked. Note: If BUCK2 is in sequence, this bit's default value will be 1'b0. LDO7 OC interrupt's mask 0: Interrupt is not masked. 1: Interrupt is masked. LDO6 OC interrupt's mask 0: Interrupt is not masked. 1: Interrupt is masked. LDO5 OC interrupt's mask 0: Interrupt is not masked. 1: Interrupt is masked. Reserved LDO3 OC interrupt's mask 0: Interrupt is not masked. 1: Interrupt is masked. LDO2 OC interrupt's mask 0: Interrupt is not masked. 1: Interrupt is masked. LDO1 OC interrupt's mask 0: Interrupt is not masked. 1: Interrupt is masked. Reserved LDO7 PG interrupt's mask 0: Interrupt is not masked. 1: Interrupt is masked. LDO6 PG interrupt's mask 0: Interrupt is not masked. 1: Interrupt is masked. LDO5 PG interrupt's mask 0: Interrupt is not masked. Reserved LDO3 PG interrupt's mask 0: Interrupt is not masked. 1: Interrupt is masked.

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Page 134 of 201

MT6360U PMIC Datasheet Confidential A Address

Reg name

MediaTek Proprietary and Confidential.

Bit

Bit name

Default

Type

2

LDO2_PGB_MA SK

1

RW

1

LDO1_PGB_MA SK

1

RW

0

Reserved

1

R

Description LDO2 PG interrupt's mask 0: Interrupt is not masked. 1: Interrupt is masked. LDO1 PG interrupt's mask 0: Interrupt is not masked. 1: Interrupt is masked. Reserved

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Page 135 of 201

MT6360U PMIC Datasheet Confidential A Table 5-6. PMIC part register detail description Address

Reg name

Bit

0x00

RST_PMIC_PA S_CODE1

7:0

RST_PMIC_PAS_ 00000000 CODE1

RW

0x01

RST_PMIC_PA S_CODE1

7:0

RST_PMIC_PAS_ 00000000 CODE1

RW

7

ALL_PMIC_RST

0

WC

6

Reserved

0

R

5

BUCK2_RST

0

WC

4

BUCK1_RST

0

WC

3

LDO7_RST

0

WC

2

LDO6_RST

0

WC

0x02

RST_PMIC

Bit name

Default

Type

Description RST_PMIC_PAS_CODE1[7:0]/Passcode 1 for RST Set REG_PMIC0x00 = 8'hA9 then REG_PMIC0x01 = 8'h96 to start up REG_PMIC0x02: ***_RST. To erase RST_PMIC_PAS_CODE, REG_PMU0x02 will not work. RST_PMIC_PAS_CODE1[7:0]/Passcode 1 for RST Set REG_PMIC0x00 = 8'hA9 then REG_PMIC0x01 = 8'h96 to start up REG_PMIC0x02: ***_RST. To erase RST_PMIC_PAS_CODE, REG_PMU0x02 will not work. All PMIC relative registers and logic reset bit 0: Not reset all registers and logic 1: Reset all registers and logic Note: This bit will be reset to 0 after reset procedure is finished. Reserved BUCK2 registers and logic reset bit 0: Not reset BUCK2 relative registers and logic 1: Reset BUCK2 relative registers and logic Note: This bit will be reset to 0 after reset procedure is finished. BUCK1 registers and logic reset bit 0: Not reset BUCK1 relative registers and logic 1: Reset BUCK1 relative registers and logic Note: This bit will be reset to 0 after reset procedure is finished. LDO7 registers and logic reset bit 0: Not reset LDO7 relative registers and logic 1: Reset LDO7 relative registers and logic Note: This bit will be reset to 0 after reset procedure is finished. LDO6 registers and logic reset bit

0: Not reset LDO6 relative registers and

MediaTek Proprietary and Confidential.

logic 1: Reset LDO6 relative registers and logic Note: This bit will be reset to 0 after reset procedure is finished.

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Page 136 of 201

MT6360U PMIC Datasheet Confidential A Address

0x04

Reg name

Bit 1

REG_PMIC_RST

0

7:5

HW_SYSUV_SEL

001

4:1

SYSUV_SEL

0010

SYSUV_CTRL1

SYSUV_CTRL2

Reserved

1

7:6

TD_SYSUV_F

00

5:0

Reserved

7

0x06

Default 0

0

0

0x05

Bit name Reserved

HW_TRAPPIN G USBPD_REV_ VER

MediaTek Proprietary and Confidential.

000000

HWEN_RPL_EN B

0

Type Description R Reserved REG_PMIC registers reset bits 0: Not reset REG_PMU registers 1: Reset specified REG_PMIC register WC according to RST table Note: This bit will be reset to 0 after reset procedure is finished. SYSUVLO rising threshold voltage setting 000: 2.8V 001: 2.9V 010: 3.0V RW 011: 3.1V 100: 3.2V 101~111: 3.3V Note: UVLO_SEL pin defines the default value. SYSUVLO falling threshold voltage selection (50 mV/step) 0000: 2.4V 0001: 2.45V RW 0010: 2.5V … 0111: 2.75V 1000~1111: 2.8V R Reserved Selects SYSUVLO falling deglitch time 00: 0 μs (only clock sampling) RW 01: 16 μs 10: 32 μs 11: 64 μs R Reserved 0: EN pin has 350kΩ. pull down resistor 1: EN pin is floating gate Note: HW reset condition RWSC 1. When SYSUV happens; 2. When APWDTRST is triggered; 3. CHG_QONB long press shutdown 4. When entering shipping mode When (CHx_SCLKEN_2_OP_EN = 1'b1 & CHx_SRCLKEN_2_OP_CFG = 2'b00), this bit is for CHx ON/OFF control. 0: Disable CHx immediately 1: Elect CHx on When (CHx_SCLKEN_2_OP_EN = 1'b1 & CHx_SRCLKEN_2_OP_CFG = 2'b10), this bit is for low power mode enable control. 0: Low power mode

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Page 137 of 201

MT6360U PMIC Datasheet Confidential A Address

Reg name

Bit

Bit name

Default

Type

5:4

TB_REBOOT

00

RW

3

FAULTB_STAT

0

R

2:0

HW_TRAPPING

000

R

7:6

Reserved

00

R

5:0

BUCK1_SEQOFF TD

Description 1: Normal mode Blocking time between PMIC off to on 00: 0 ms 01: 25 ms 10: 50 ms 11: 100 ms Note: Remain EN 128 μs debounce time. Indicates PG fault of all LDOs and bucks 0: No PG fault 1: Any of bucks and LDOs has PG fault. Report HW_TRAPPING detected result for BUCKx and VDRAM's default setting: 000: BUCK1_VOUT = 1.3V (VRF13) BUCK2_VOUT = 1.125V (VDRAM1 LP4x) VDRAM2 = 0.6V 001: BUCK1_VOUT = 1.3V (VRF13) BUCK2_VOUT = 1.125V (VDRAM1 LP4x) VDRAM2 = 1.8V 010: BUCK1_VOUT = 1.125V (VDRAM1 LP4x) BUCK2_VOUT = 1.3V (VRF13) VDRAM2 = 0.6V 011: BUCK1_VOUT = 1.125V (VDRAM1 LP4x) BUCK2_VOUT = 1.3V (VRF13) VDRAM2 = 1.8V 100: BUCK1_VOUT = 1.3V (VRF13)) BUCK2_VOUT = 1.225V (VDRAM1 LP3) VDRAM2 off 101: BUCK1_VOUT = 1.225V (VDRAM1 LP3) BUCK2_VOUT = 1.3V (VRF13)) VDRAM2 off 110: BUCK1_VOUT = 1.3V (VRF13) BUCK2_VOUT = 1.125V (VDRAM1 LP4) VDRAM2 off 111: BUCK1_VOUT = 1.3V (VRF13) BUCK2_VOUT = 1.3V (VRF13) VDRAM2 off Reserved

Selects BUCK1 sequenced off delay 0x07

BUCK1_SEQO FFDLY

MediaTek Proprietary and Confidential.

000000

RW

time (2 ms/step) 000000: 0 ms 000001: 2 ms ... 000110: 12 ms

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Page 138 of 201

MT6360U PMIC Datasheet Confidential A Address

0x08

0x09

0x0A

0x10

Reg name

BUCK2_SEQO FFDLY

LDO7_SEQOF FDLY

LDO6_SEQOF FDLY

BUCK1_

MediaTek Proprietary and Confidential.

Bit

Bit name

7:6

Reserved

5:0

BUCK2_SEQOFF TD

7:6

Reserved

5:0

LDO7_SEQOFFT D

7:6

Reserved

5:0

7:0

Default

Type

00

R

000000

RW

00

R

000000

RW

00

R

LDO6_SEQOFFT D

000000

RW

BUCK1_VOSEL

00000000

RW

Description ... 111110: 124 ms 111111: 126 ms Note: If BUCK1 is not in sequence, these bits are useless. Reserved Selects BUCK2 sequenced off delay time (2 ms/step) 000000: 0 ms 000001: 2 ms ... 000100: 8 ms ... 111110: 124 ms 111111: 126 ms Note: If BUCK2 is not in sequence, these bits are useless. Reserved Selects LDO7 (VDRAM2) sequenced off delay time (2 ms/step) 000000: 0 ms 000001: 2 ms 000010: 4 ms ... 111110: 124 ms 111111: 126 ms Note: If LDO7 is not in sequence, these bits are useless. Reserved Selects LDO6 (VMDDR) sequenced off delay time (2 ms/step) 000000: 0 ms 000001: 2 ms 000010: 4 ms ... 111110: 124 ms 111111: 126 ms Note: If LDO6 is not in sequence, these bits are useless. Selects BUCK1 Vout in normal mode:(5 mV/step) 00000000: 0.3V 01011010: 0.75V 10100101: 1.125V 10111001: 1.225V 11001000~11111111: 1.3V BUCK1_VO in normal mode = 0.3V + (5 mV × code)

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Page 139 of 201

MT6360U PMIC Datasheet Confidential A Address

Reg name

Bit

Bit name

Default

Type

0x11

BUCK1_LP_V OSEL

7:0

BUCK1_LP_VOS EL

00000000

RW

7

BUCK1_OC_EN

1

RW

6:5

BUCK1_OC_WN D

01

RW

4:3

BUCK1_OC_THD

01

RW

2

BUCK1_OC_STA TUS

0

R

1

BUCK1_OC_SDN _EN

0

RW

0

BUCK1_FPWM_ DN_EN

1

RW

7

BUCK1_SFCHG_ REN

1

RW

6:0

BUCK1_SFCHG_ RRATE

0000010

RW

7

BUCK1_SFCHG_ FEN

1

RW

Enables BUCK1 soft change falling 0: Disable 1: Enable

6:0

BUCK1_SFCHG_ FRATE

0000101

RW

BUCK1 soft change falling rate

0x12

0x13

BUCK1_OC

BUCK1_SFCH G_R

(code + 1)/3M

0x14

BUCK1_SFCH G_F

MediaTek Proprietary and Confidential.

Description Note: The default value is decided by HW_TRAPPING. Selects BUCK1 Vout in LP mode (5 mV/step) 00000000: 0.3V 01011010: 0.75V 10100101: 1.125V 10111001: 1.225V 11001000~11111111: 1.3V BUCK1_VO in LP mode = 0.3V + (5 mV × code) Note: The default value is decided by REG_PMU0x99[2:0]. Enables BUCK1 OC 0: Disable 1: Enable BUCK1 OC window 00: 8 μs 01: 16 μs 10: 32 μs 11: 64 μs BUCK1 OC flag occur condition 00: 4 times 01: 8 times 10: 16 times 11: 32 times BUCK1 OC status 0: No OC 1: OC occurs. Enables BUCK1 OC shutdown 0: Occurrence of OC does not turn off BUCK1, only interrupt. 1: Occurrence of OC turns off BUCK1 and resets BUCK1_EN_CTRL1/2 except auto-writing BUCK1_SW_EN = 1'b0. Enables BUCK1 TRA_DN sPWM 0: Disable sPWM 1: Enable sPWM Enables BUCK1 soft change rising 0: Disable 1: Enable BUCK1 soft change rising rate Ref clock = 3 MHz, 1 step (5 mV) =

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Page 140 of 201

MT6360U PMIC Datasheet Confidential A Address

Reg name

Bit

7

0x15

0x16

BUCK1_DVS

Bit name

Default

Reserved

0

6:5

BUCK1_DVS_EN _CTRL

11

4:3

BUCK1_DVS_EN _TD

01

2:1

BUCK1_OC_ limit

10

0

Reserved

0

7

BUCK1_GO_LP_ OP

0

6

Reserved

0

5

BUCK1_SRCLKE N_0_OP_EN

0

4:3

BUCK1_SRCLKE N_0_OP_CFG

00

BUCK1_EN_C TRL1

Type

Description Ref clock = 3 MHz, 1 step (5 mV) = (code + 1)/3M R Reserved Enables BUCK1 DVS_EN transition pulse 00: Disable RW 01: Enable falling 10: Enable rising 11: Enable rising/falling BUCK1 DVS_EN transition pulse window 00: 30 μs RW 01: 45 μs 10: 60 μs 11: 75 μs BUCK1 out load limit 00: NA RW 01: 3A 10: 4A 11: 5A R Reserved 0: Prefer LP; enter LP if one of SRCLKEN_0/SRCLKEN_2/REG_EN is "LP". RWSC 1: Prefer no LP; leave LP if one of SRECLKEN_0/SRCLKEN_2/REG_EN is "NO LP". R Reserved 0: Deprive the control power of SRCLKEN_0 pin for BUCK1 RWSC 1: Allow SRCLKEN_0 pin to control BUCK1 Selects the use of SRCLKEN_0 pin when BUCK1_SRCLKEN_0_OP_EN = 1'b1 00: SRCLKEN_0 pin can elect BUCK1 on/off. When SRCLKEN_0 pin is logic low, elect BUCK1 off. When SRCLKEN_0 pin is logic high, elect BUCK1 on. RWSC 01: NA 10: SRCLKEN_0 pin can elect BUCK1 LP mode on/off. When SRCLKEN_0 pin is logic low, elect BUCK1 LP mode on. When SRCLKEN_0 pin is logic high, elect

BUCK1 LP mode off.

2

MediaTek Proprietary and Confidential.

BUCK1_SRCLKE N_2_OP_EN

0

11: NA 0: Deprive the control power of RWSC SRCLKEN_2for BUCK1 1: Allow SRCLKEN_2 to control BUCK1

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Page 141 of 201

MT6360U PMIC Datasheet Confidential A Address

0x17

Reg name

BUCK1_EN_C TRL2

Bit

Bit name

Default

Type

1:0

BUCK1_SRCLKE N_2_OP_CFG

00

RWSC

7

BUCK1_SW_OP _EN

1

RWSC

6

BUCK1_SW_EN

0

RWSC

5

BUCK1_SW_LP

0

RWSC

4

Reserved

0

R

3

BUCK1_GO_ON _OP

0

RWSC

2

BUCK1_EN

0

R

1:0

BUCK1_MODE

00

R

7:6

Reserved

00

R

Description Selects the use of SRCLKEN_2 when BUCK1_SRCLKEN_2_OP_EN = 1'b1 00: SRCLKEN_2 can elect BUCK1 on/off. When SRCLKEN_2 is logic low, elect BUCK1 off. When SRCLKEN_2 is logic high, elect BUCK1 on. 01: NA 10: SRCLKEN_2 can elect BUCK1 LP mode on/off. When SRCLKEN_2 is logic low, elect BUCK1 LP mode on. When SRCLKEN_2 is logic high, elect BUCK1 LP mode off. 11: NA 0: Deprive the control power of BUCK1_SW_EN/LP 1: Allow BUCK1_SW_EN/LP working This bit is useless when BUCK1_SW_OP_EN = 1’b0. 0: Elect BUCK1 off 1: Elect BUCK1 on. Note: 1) If BUCK1 is in sequence, the default value = 1'b1. 2) When BUCK1 power is not good or OC happens and only turns off itself, reset BUCK1_EN_CTRLx except autowriting this bit = 1'b0. EN pin = 0->1 will reload this bit to the default value. This bit is useless when BUCK1_SW_OP_EN = 1'b0. 0: Elect BUCK1 LP mode off 1: Elect BUCK1 LP mode on Reserved 0: Prefer on; turn on if one of SRCLKEN_0/SRCLKEN_2/REG_EN is "ON". 1: Prefer off; turn OFF if one of SRECLKEN_0/SRCLKEN_2/REG_EN is "OFF". Indicates the result of enable election 0: BUCK1 is on. 1: BUCK1 is off/ Indicates the operation mode of

BUCK1

0x18

BUCK1_CTRL1

MediaTek Proprietary and Confidential.

00: Normal mode 01: NA 10: LP mode 11: NA Reserved

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Page 142 of 201

MT6360U PMIC Datasheet Confidential A Address

0x19

0x20

Reg name

BUCK1_CTRL2

BUCK2_VOSEL

Bit

Bit name

Default

Type

5:4

BUCK1_STCD_ TD

00

RW

3

BUCK1_STCD

0

R

2

BUCK1_PG

0

R

1:0

BUCK1_PGB_PT SEL

10

RW

7:6

Reserved

01

R

5:4

BUCK1_SS_SR

11

RW

3:0

Reserved

0000

R

7:0

BUCK2_VOSEL

00000000

RW

Description BUCK1 FAULT extended block time after soft-start count down 00: 1 ms 01: 2 ms 10: 4 ms 11: 8 ms Indicates BUCK1 soft-start counts down or not 0: Off or soft-start not count down 1: Soft-start counts down Indicates BUCK1 power is good or not 0: Power is not good or off. 1: Power is good (BUCK1_STCD = 1 and sPG_BUCK1 = 1). Reaction when BUCK1 power not good happens 00: Only interrupt; will not disable any channel 01: Only shut down BUCK1 and reset BUCK1_EN_CTRL1/2 then set BUCK1_EN = 1'b0 10: Shut down all bucks and LDOs; reset CHx_EN_CTRL1/2 and after the blocking time: TB_REBOOT, then confirm EN pin. 11: Equal to 2'b10 Reserved Speed of SOFT START DVS 00: 10 mV step/μs 01: 5 mV step/μs 10: 2.5 mV step/μs 11: 1.25 mV step/μs Reserved Selects BUCK2 Vout in normal mode (5 mV/step) 00000000: 0.3V 01011010: 0.75V 10100101: 1.125V 10111001: 1.225V 11001000~11111111: 1.3V BUCK2_VO in normal mode = 0.3V + (5 mV × code) Note: The default value is decided by

HW_TRAPPING.

0x21

BUCK2_LP_V OSEL

MediaTek Proprietary and Confidential.

7:0

BUCK2_LP_VOS EL

00000000

RW

Selects BUCK2 Vout in LP mode (5 mV/step) 00000000: 0.3V 01011010: 0.75V 10100101: 1.125V 10111001: 1.225V

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Page 143 of 201

MT6360U PMIC Datasheet Confidential A Address

0x22

0x23

0x24

Reg name

Bit

Bit name

Default

Type

7

BUCK2_OC_EN

1

RW

6:5

BUCK2_OC_WN D

01

RW

4:3

BUCK2_OC_THD

01

RW

2

BUCK2_OC_STA TUS

0

R

1

BUCK2_OC_SDN _EN

0

RW

0

BUCK2_FPWM_ DN_EN

1

RW

7

BUCK2_SFCHG_ REN

1

RW

6:0

BUCK2_SFCHG_ RRATE

0000010

RW

7

BUCK2_SFCHG_ FEN

1

RW

6:0

BUCK2_SFCHG_ FRATE

0000101

RW

0

R

BUCK2_OC

BUCK2_SFCH G_R

BUCK2_SFCH G_F

7

Reserved

Description 11001000~11111111: 1.3V BUCK2_VO in LP mode = 0.3V + (5mV x code) Note: The default value is decided by HW_TRAPPING. Enables BUCK2 OC 0: Disable 1: Enable BUCK2 OC window 00: 8 μs 01: 16 μs 10: 32 μs 11: 64 μs BUCK2 OC flag occur condition 00: 4 times 01: 8 times 10: 16 times 11: 32 times BUCK2 OC status 0: No OC 1: OC occurs. Enables BUCK2 OC shutdown 0: Occurrence of OC does not turn off BUCK2, only interrupt. 1: Occurrence of OC turns off BUCK2 and resets BUCK2_EN_CTRL1/2 except auto-writing BUCK2_SW_EN = 1'b0. Enables BUCK2 TRA_DN sPWM 0: Disable sPWM 1: Enable sPWM Enables BUCK2 soft change rising 0: Disable 1: Enable BUCK2 soft change rising rate Ref clock = 3 MHz, 1 step (5 mV) = (code + 1)/3M Enables BUCK2 soft change falling 0: Disable 1: Enable BUCK2 soft change falling rate Ref clock = 3 MHz, 1 step (5 mV) = (code + 1)/3M Reserved

Enables BUCK2 DVS_EN transition 0x25

BUCK2_DVS

MediaTek Proprietary and Confidential.

6:5

BUCK2_DVS_EN _CTRL

11

RW

pulse 00: Disable 01: Enable falling 10: Enable rising 11: Enable rising/falling

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Page 144 of 201

MT6360U PMIC Datasheet Confidential A Address

0x26

Reg name

BUCK2_EN_C TRL1

BUCK2 off. When SRCLKEN_2 is logic

MediaTek Proprietary and Confidential.

Bit

Bit name

Default

Type

4:3

BUCK2_DVS_EN _TD

01

RW

2:1

BUCK2_OC_limi t

01

RW

0

Reserved

0

R

7

BUCK2_GO_LP_ OP

0

RWSC

6

Reserved

0

R

5

BUCK2_SRCLKE N_0_OP_EN

0

RWSC

4:3

BUCK2_SRCLKE N_0_OP_CFG

00

RWSC

2

BUCK2_SRCLKE N_2_OP_EN

0

RWSC

00

RWSC

1:0

N_2_OP_CFG

Description BUCK2 DVS_EN transition pulse window 00: 30 μs 01: 45 μs 10: 60 μs 11: 750 μs BUCK2 out load limit 00: NA 01: 3A 10: 4A 11: 5A Reserved 0: Prefer LP; enter LP if one of SRCLKEN_0/SRCLKEN_2/REG_EN is "LP". 1: Prefer no LP; leave LP if one of SRECLKEN_0/SRCLKEN_2/REG_EN is "NO LP". Reserved 0: Deprive the control power of SRCLKEN_0 pin for BUCK2 1: Allow SRCLKEN_0 pin to control BUCK2 Selects the use of SRCLKEN_0 pin when BUCK2_SRCLKEN_0_OP_EN = 1'b1 00: SRCLKEN_0 pin can elect BUCK2 on/off. When SRCLKEN_0 pin is logic low, elect BUCK2 off. When SRCLKEN_0 pin is logic high, elect BUCK2 on. 01: NA 10: SRCLKEN_0 pin can elect BUCK2 LP mode on/off. When SRCLKEN_0 pin is logic low, elect BUCK2 LP mode on. When SRCLKEN_0 pin is logic high, elect BUCK2 LP mode off. 11: NA 0: Deprive the control power of SRCLKEN_2for BUCK2 1: Allow SRCLKEN_2 to control BUCK2 Selects the use of SRCLKEN_2 when BUCK2_SRCLKEN_2_OP_EN = 1'b1 00: SRCLKEN_2 can elect BUCK2 on/off. When SRCLKEN_2 is logic low, elect high, elect BUCK2 on. 01: NA 10: SRCLKEN_2 can elect BUCK2 LP mode on/off. When SRCLKEN_2 is logic low, elect BUCK2 LP mode on. When

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Page 145 of 201

MT6360U PMIC Datasheet Confidential A Address

0x27

10: 4 ms

Reg name

BUCK2_EN_C TRL2

Bit

Bit name

Default

Type

7

BUCK2_SW_OP _EN

1

RWSC

6

BUCK2_SW_EN

0

RWSC

5

BUCK2_SW_LP

0

RWSC

4

Reserved

0

R

3

BUCK2_GO_ON _OP

0

RWSC

2

BUCK2_EN

0

R

1:0

BUCK2_MODE

00

R

7:6

Reserved

00

R

5:4

BUCK2_STCD_T D

00

RW

Description SRCLKEN_2 is logic high, elect BUCK2 LP mode off. 11: NA 0: Deprive the control power of BUCK2_SW_EN/LP 1: Allow BUCK2_SW_EN/LP working This bit is useless when BUCK2_SW_OP_EN = 1'b0 0: Elect BUCK2 off 1: Elect BUCK2 on Note: 1) If BUCK2 is in sequence, the default value = 1'b1. 2) When BUCK2 power is not good or OC happens and only turns off itself, reset BUCK2_EN_CTRLx except autowriting this bit = 1'b0. EN pin = 0->1 will reload this bit to the default value. This bit is useless when BUCK2_SW_OP_EN = 1'b0 0: Elect BUCK2 LP mode off 1: Elect BUCK2 LP mode on Reserved 0: Prefer on; turn on if one of SRCLKEN_0/SRCLKEN_2/REG_EN is "ON". 1: Prefer off; turn off if one of SRECLKEN_0/SRCLKEN_2/REG_EN is "OFF". Indicates the result of enable election 0: BUCK2 is on. 1: BUCK2 is off. Indicates the operation mode of BUCK2 00: Normal mode 01: NA 10: LP mode 11: NA Reserved BUCK2 FAULT extended block time after soft-start count down 00: 1 ms 01: 2 ms

0x28

3 MediaTek Proprietary and Confidential.

BUCK2_STCD

0

R

11: 8 ms Indicates BUCK2 soft-start counts down or not 0: Off or soft-start does not count down.

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Page 146 of 201

MT6360U PMIC Datasheet Confidential A Address

Reg name

Bit

2

0x29

0x30

BUCK2_CTRL2

Bit name

Default

BUCK2_PG

0

1:0

BUCK2_PGB_PT SEL

10

7:6

Reserved

01

5:4

BUCK2_SS_SR

11

3:0

Reserved

0000

7

LDO7_GO_LP_O P

0

6

Reserved

0

5

LDO7_SRCLKEN _0_OP_EN

0

4:3

LDO7_SRCLKEN _0_OP_CFG

00

LDO7_EN_CT RL1 (VDRAM2)

10: SRCLKEN_0 pin can elect LDO7 LP

Type

Description 1: Soft-start counts down. Indicates BUCK2 power is good or not 0: Power is not good or off. R 1: Power is good (BUCK2_STCD = 1 and sPG_BUCK2 = 1). Reaction when BUCK2 OC or power not good happens 00: Only interrupt; will not disable any channel 01: Only shut down BUCK2 and reset BUCK2_EN_CTRL1/2 then set BUCK2_EN = 1'b0 RW 10: Shut down all bucks and LDOs, reset CHx_EN_CTRL1/2 and after the blocking time: TB_REBOOT, then confirm EN pin. 11: Equal to 2'b10 Note: If BUCK2 is not in sequence, the default value is 2'b01. R Reserved Speed of SOFT START DVS 00: 10 mV step/μs RW 01: 5 mV step/μs 10: 2.5 mV step/μs 11: 1.25 mV step/μs R Reserved 0: Prefer LP; enter LP if one of SRCLKEN_0/SRCLKEN_2/REG_EN is "LP". RWSC 1: Prefer no LP; leave LP if one of SRECLKEN_0/SRCLKEN_2/REG_EN is "NO LP". R Reserved 0: Deprive the control power of SRCLKEN_0 pin for LDO7 RWSC 1: Allow SRCLKEN_0 pin to control LDO7 Selects the use of SRCLKEN_0 pin when LDO7_SRCLKEN_0_OP_EN = 1'b1 00: SRCLKEN_0 pin can elect LDO7 on/off. When SRCLKEN_0 pin is logic low, elect LDO7 off. When SRCLKEN_0 pin is logic high, elect LDO7 on. RWSC 01: NA mode on/off. When SRCLKEN_0 pin is logic low, elect LDO7 LP mode on. When SRCLKEN_0 pin is logic high, elect LDO7 LP mode off. 11: Reserved

MediaTek Proprietary and Confidential.

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Page 147 of 201

MT6360U PMIC Datasheet Confidential A Address

0x31

Reg name

LDO7_EN_CT RL2 (VDRAM2)

Bit

Bit name

Default

Type

2

LDO7_SRCLKEN _2_OP_EN

0

RWSC

1:0

LDO7_SRCLKEN _2_OP_CFG

00

RWSC

7

LDO7_SW_OP_E N

1

RWSC

6

LDO7_SW_EN

0

RWSC

5

LDO7_SW_LP

0

RWSC

4

Reserved

0

R

3

LDO7_GO_ON_ OP

0

RWSC

2

LDO7_EN

0

R

1:0

LDO7_MODE

00

R

7:6

Reserved

00

R

Description 0: Deprive the control power of SRCLKEN_2 for LDO7 1: Allow SRCLKEN_2 to control LDO7 Selects the use of SRCLKEN_2 when LDO7_SRCLKEN_2_OP_EN = 1'b1 00: SRCLKEN_2 can elect LDO7 on/off. When SRCLKEN_2 is logic low, elect LDO7 off. When SRCLKEN_2 is logic high, elect LDO7 on. 01: NA 10: SRCLKEN_2 can elect LDO7 LP mode on/off. When SRCLKEN_2 is logic low, elect LDO7 LP mode on. When SRCLKEN_2 is logic high, elect LDO7 LP mode off. 11: Reserved 0: Deprive the control power of LDO7_SW_EN/LP 1: Allow LDO7_SW_EN/LP working This bit is useless when LDO7_SW_OP_EN = 1'b0 0: Elect LDO7 off 1: Elect LDO7 on This bit is useless when LDO7_SW_OP_EN = 1'b0. 0: Elect LDO7 LP mode off 1: Elect LDO7 LP mode on Reserved 0: Prefer on; turn ON if one of SRCLKEN_0/SRCLKEN_2/REG_EN is "ON". 1: Prefer off; turn OFF if one of SRECLKEN_0/SRCLKEN_2/REG_EN is "OFF". Indicates the result of enable election 0: LDO7 is on. 1: LDO7 is off. Indicates the operation mode of LDO7 00: Normal mode 01: NA 10: LP mode 11: NA Reserved

LDO7 FAULT extended block time after 0x32

LDO7_CTRL0 (VDRAM2)

MediaTek Proprietary and Confidential.

5:4

LDO7_STCD_TD

00

RW

soft-start count down 00: 1 ms 01: 2 ms 10: 4 ms 11: 8 ms

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Page 148 of 201

MT6360U PMIC Datasheet Confidential A Address

0x33

Reg name

Bit

Bit name

Default

Type

Description Indicates LDO7 soft-start counts down or not R 0: Off or soft-start does not count down. 1: Soft-start counts down. Indicates LDO7 power is good or not R 0: Power is not good or off. 1: Power is good. Reaction when LDO7 power not good happens 00: Only interrupt; will not disable any channel 01: Only shut down LDO7 and reset LDO7_EN_CTRL1/2 then set LDO7_EN = RW 1'b0 10: Shut down all bucks and LDOs, reset CHx_EN_CTRL1/2 and after the blocking time: TB_REBOOT, then confirm EN pin 11: Equal to 2'b10 0: Disable clamp circuit in LP mode RW 1: Enable clamp circuit in LP mode 0: Disable OC circuit RW 1: Enable OC circuit Low power mode OC enable control RW 0: Disable 1: Enable R Reserved OCFB function enable control RWSC 0: Disable 1: Enable Selects OCFB deglitch time 00: 10 μs RW 01: 15 μs 10: 60 μs 11: 100 μs Reaction when LDO7 OC happens 0: Only interrupt; will not disable LDO7 1: Automatically disable LDO7 after 5 RWSC ms de-bouncing time and reset LDO7_EN_CTRL1/2 then set LDO7_EN = 1'b0 Selects soft-start OC deglitch time

3

LDO7_STCD

0

2

LDO7_PG

0

1:0

LDO7_PGB_PTS EL

10

7

LDO7_LP_CLAM P_EN

1

6

LDO7_OC_EN

1

5

LDO7_LPOC_EN

0

4

Reserved

00

3

LDO7_OCFB_EN

1

2:1

LDO7_OCFB_TD

10

0

LDO7_OC_PTSE L

0

7:6

LDO7_STBTD

00

RW

5:4

Reserved

00

R

LDO7_CTRL1 (VDRAM2)

00: 1,100 μs 0x34

LDO7_CTRL2 (VDRAM2)

MediaTek Proprietary and Confidential.

01: 3,300 μs 10: 6,600 μs 11: 9,900 μs Reserved

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Page 149 of 201

MT6360U PMIC Datasheet Confidential A Address

0x35

0x36

Reg name

Bit

Bit name

Default

3

LDO7_DUMMY_ LOAD_GATED_D IS

0

2

LDO7_NDIS_EN

1

1:0

LDO7_DUMMY_ LOAD

00

7:4

LDO7_VOSEL

0001

3:0

LDO7_VOCAL

0000

LDO7_CTRL3 (VDRAM2)

7

LDO6_GO_LP_O P

0

6

Reserved

0

5

LDO6_SRCLKEN _0_OP_EN

0

4:3

LDO6_SRCLKEN _0_OP_CFG

00

LDO6_EN_ CTRL1 (VMDDR)

Type

Description Permission to make LDO7_DUMMY_LOAD = 2'b00, when LDO7 is in LP mode RW 0: LDO7_DUMMY_LOAD will be gated by LP mode. 1: LDO7_DUMMY_LOAD will be regardless with LP. 0: Disable output discharge RW 1: Enable output discharge 00: 0A dummy load 01: 100 μA dummy load RW 10: 1 mA dummy load 11: 1.1 mA dummy load LDO7 VO coarse-tuning 0001: 0.6V RW … Note: VO7 = 0.5 + (0.1 x LDO7_VOSEL) + (0.01 × LDO7_VOCAL) Fine-tunes LDO7 VO (+10 mV/step) 0000: +00 mV 0001: +10 mV RW … 1010~1111: +100 mV LDO7_VOCAL = 10 mV × code 0: Prefer LP; enter LP if one of SRCLKEN_0/SRCLKEN_2/REG_EN is "LP". RWSC 1: Prefer no LP; leave LP if one of SRECLKEN_0/SRCLKEN_2/REG_EN is "NO LP". R Reserved 0: Deprive the control power of SRCLKEN_0 pin for LDO6 RWSC 1: Allow SRCLKEN_0 pin to control LDO6 Selects the use of SRCLKEN_0 pin when LDO6_SRCLKEN_0_OP_EN = 1'b1 00: SRCLKEN_0 pin can elect LDO6 on/off. When SRCLKEN_0 pin is logic low, elect LDO6 off. When SRCLKEN_0 pin is logic high, elect LDO6 on. RWSC 01: NA 10: SRCLKEN_0 pin can elect LDO6 LP mode on/off. When SRCLKEN_0 pin is

logic low, elect LDO6 LP mode on.

2 MediaTek Proprietary and Confidential.

LDO6_SRCLKEN _2_OP_EN

0

When SRCLKEN_0 pin is logic high, elect LDO6 LP mode off. 11: Reserved 0: Deprive the control power of RWSC SRCLKEN_2for LDO6

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Page 150 of 201

MT6360U PMIC Datasheet Confidential A Address

0x37

01: 2 ms

0x38

Reg name

LDO6_EN_CT RL2 (VMDDR)

LDO6_CTRL0 (VMDDR)

Bit

Bit name

Default

Type

1:0

LDO6_SRCLKEN _2_OP_CFG

00

RWSC

7

LDO6_SW_OP_E N

1

RWSC

6

LDO6_SW_EN

0

RWSC

5

LDO6_SW_LP

0

RWSC

4

Reserved

0

R

3

LDO6_GO_ON_ OP

0

RWSC

2

LDO6_EN

0

R

1:0

LDO6_MODE

00

R

7:6

Reserved

00

R

5:4

LDO6_STCD_TD

00

RW

3 MediaTek Proprietary and Confidential.

LDO6_STCD

0

R

Description 1: Allow SRCLKEN_2 to control LDO6 Selects the use of SRCLKEN_2 when LDO6_SRCLKEN_2_OP_EN = 1'b1 00: SRCLKEN_2 can elect LDO6 on/off. When SRCLKEN_2 is logic low, elect LDO6 off. When SRCLKEN_2 is logic high, elect LDO6 on. 01: NA 10: SRCLKEN_2 can elect LDO6 LP mode on/off. When SRCLKEN_2 is logic low, elect LDO6 LP mode on. When SRCLKEN_2 is logic high, elect LDO6 LP mode off. 11: Reserved 0: Deprive the control power of LDO6_SW_EN/LP 1: Allow LDO6_SW_EN/LP working This bit is useless when LDO6_SW_OP_EN = 1'b0. 0: Elect LDO6 off. 1: Elect LDO6 on. This bit is useless when LDO6_SW_OP_EN = 1'b0. 0: Elect LDO6 LP mode off. 1: Elect LDO6 LP mode on. Reserved 0: Prefer on; turn on if one of SRCLKEN_0/SRCLKEN_2/REG_EN is "ON". 1: Prefer off; turn off if one of SRECLKEN_0/SRCLKEN_2/REG_EN is "OFF". Indicates the result of enable election 0: LDO6 is on. 1: LDO6 is off. Indicates the operation mode of LDO6 00: Normal mode 01: NA 10: LP mode 11: NA Reserved LDO6 FAULT extended block time after soft-start count down 00: 1 ms 10: 4 ms 11: 8 ms Indicates LDO6 soft-start counts down or not 0: Off or soft-start does not count

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Page 151 of 201

MT6360U PMIC Datasheet Confidential A Address

Reg name

Bit

2

0x39

LDO6_CTRL1 (VMDDR)

0x3A

Default

LDO6_PG

0

1:0

LDO6_PGB_PTS EL

10

7

LDO6_LP_CLAM P_EN

1

6

LDO6_OC_EN

1

5

LDO6_LPOC_EN

0

4

Reserved

00

3

LDO6_OCFB_EN

1

2:1

LDO6_OCFB_TD

10

0

LDO6_OC_PTSE L

0

LDO6_STBTD

01

7:6

Reserved

Bit name

Type

down. 1: Soft-start counts down. Indicates LDO6 power is good or not R 0: Power is not good or off. 1: Power is good. Reaction when LDO6 power not good happens 00: Only interrupt; will not disable any channel 01: Only shut down LDO7 and reset LDO6_EN_CTRL1/2 then set LDO6_EN = RW 1'b0 10: Shut down all bucks and LDOs, reset CHx_EN_CTRL1/2 and after the blocking time: TB_REBOOT, then confirm EN pin 11: Equal to 2'b10 0: Disable clamp circuit at LP mode RW 1 : Enable clamp circuit at LP mode 0: Disable OC circuit RW 1: Enable OC circuit Low power mode OC enable control RW 0: Disable 1: Enable R Reserved OCFB function enable control RWSC 0: Disable 1: Enable Selects OCFB deglitch time 00: 10 μs RW 01: 15 μs 10: 60 μs 11: 100 μs Reaction when LDO6 OC happens 0: Only interrupt; will not disable LDO6 1: Automatically disable LDO6 after 5 RWSC ms de-bouncing time and reset LDO6_EN_CTRL1/2 then set LDO6_EN = 1'b0 Selects soft-start OC deglitch time 00: 1,000 μs RW 01: 2,000 μs 10: 4,000 μs 11: 8,000 μs

(VMDDR) 3

MediaTek Proprietary and Confidential.

LDO6_DUMMY_ LOAD_GATED_D IS

0

Description

RW

Permission to make LDO6_DUMMY_LOAD =2'b00, when LDO6 is in LP mode 0: LDO6_DUMMY_LOAD will be gated by LP mode.

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Page 152 of 201

MT6360U PMIC Datasheet Confidential A Address

0x3B

Reg name

Bit

Bit name

Default

Type

2

LDO6_NDIS_EN

1

RW

1:0

LDO6_DUMMY_ LOAD

00

RW

7:4

LDO6_VOSEL

0010

RW

3:0

LDO6_VOCAL

0101

RW

LDO6_CTRL3 (VMDDR)

MediaTek Proprietary and Confidential.

Description 1: LDO6_DUMMY_LOAD will be regardless with LP mode. 0: Disable output discharge 1: Enable output discharge 00: 0A dummy load 01: 100 μA dummy load 10: 1 mA dummy load 11: 1.1 mA dummy load LDO6 VO coarse-tuning 0010: 0.7V … Note: VO6 = 0.5 + (0.1 × LDO6_VOSEL) + (0.01 × LDO6_VOCAL) Fine-tunes LDO6 VO (+10 mV/step) 0000: +00 mV 1010~1111: +100 mV LDO6_VOCAL = 10 mV × code

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Page 153 of 201

MT6360U PMIC Datasheet Confidential A Table 5-7. LDO part register detail description Address

Reg name

Bit

0x00

RST_LDO_PAS _CODE1

7:0

RST_LDO_PAS_C 00000000 ODE1

RW

0x01

RST_LDO_PAS _CODE2

7:0

RST_LDO_PAS_C 00000000 ODE2

RW

7

ALL_LDO_RST

0

WC

6

Reserved

0

R

5

LDO5_RST

0

WC

4

Reserved

0

R

3

LDO3_RST

0

WC

2

LDO2_RST

0

WC

0x02

Bit name

Default

Type

RST_LDO

Description RST_LDO_PAS_CODE1[7:0]/Passcode 1 for RST Set REG_LDO0x00 = 8'hA9 then set REG_LDO0x01 = 8'h96 to start up REG_LDO0x02: ***_RST. To erase RST_LDO_PAS_CODE, REG_PMU0x02 will not work. RST_LDO_PAS_CODE2[7:0]/Passcode 2 for RST Set REG_LDO0x00 = 8'hA9 then set REG_LDO0x01 = 8'h96 to start up REG0x02 ***_RST. To erase RST_LDO_PAS_CODE, REG0x02 will not work. All LDO relative registers and logic reset bit 0: Not reset all registers and logic 1: Reset all registers and logic. Note: This bit will be reset to 0 after reset procedure is finished. Reserved LDO5 registers and logic reset bit 0: Not reset LDO5 relative registers and logic. 1: Reset LDO5 relative registers and logic. Note: This bit will be reset to 0 after reset procedure is finished. Reserved LDO3 registers and logic reset bit 0: Not reset LDO3 relative registers and logic 1: Reset LDO3 relative registers and logic Note: This bit will be reset to 0 after reset procedure is finished. LDO2 registers and logic reset bit 0: Not reset LDO2 relative registers and logic 1: Reset LDO2 relative registers and logic Note: This bit will be reset to 0 after

reset procedure is finished.

1

MediaTek Proprietary and Confidential.

LDO1_RST

0

WC

LDO1 registers and logic reset bit 0: Not reset LDO1 relative registers and logic 1: Reset LDO1 relative registers and logic

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Page 154 of 201

MT6360U PMIC Datasheet Confidential A Address

0x04

Reg name

Bit

Bit name

Default

Type

0

REG_LDO_RST

0

WC

7

LDO3_GO_LP_O P

0

RWSC

6

Reserved

0

R

5

LDO3_SRCLKEN _0_OP_EN

0

RWSC

4:3

LDO3_SRCLKEN _0_OP_CFG

00

RWSC

2

LDO3_SRCLKEN _2_OP_EN

0

RWSC

1:0

LDO3_SRCLKEN _2_OP_CFG

00

RWSC

LDO3_EN_ CTRL1 (VMC)

Description Note: This bit will be reset to 0 after reset procedure is finished. REG_LDO registers reset bits 0: Not reset REG_PMU registers 1: Reset specified REG_LDO registers according to RST table Note: This bit will be reset to 0 after reset procedure is finished. 0: Prefer LP; enter LP if one of SRCLKEN_0/SRCLKEN_2/REG_EN is "LP". 1: Prefer no LP; leave LP if one of SRECLKEN_0/SRCLKEN_2/REG_EN is "NO LP". Reserved 0: Deprive the control power of SRCLKEN_0 pin for LDO3 1: Allow SRCLKEN_0 pin to control LDO3 Selects the use of SRCLKEN_0 pin when LDO3_SRCLKEN_0_OP_EN = 1'b1 00: SRCLKEN_0 pin can elect LDO3 on/off. When SRCLKEN_0 pin is logic low, elect LDO3 off. When SRCLKEN_0 pin is logic high, elect LDO3 on. 01: NA 10: SRCLKEN_0 pin can elect LDO3 LP mode on/off. When SRCLKEN_0 pin is logic low, elect LDO3 LP mode on. When SRCLKEN_0 pin is logic high, elect LDO3 LP mode off. 11: Reserved 0: Deprive the control power of SRCLKEN_2 for LDO3 1: Allow SRCLKEN_2 to control LDO3 Selects the use of SRCLKEN_2 when LDO3_SRCLKEN_2_OP_EN = 1'b1 00: SRCLKEN_2 can elect LDO3 on/off. When SRCLKEN_2 is logic low, elect LDO3 off. When SRCLKEN_2 is logic high, elect LDO3 on. 01: NA 10: SRCLKEN_2 can elect LDO3 LP mode on/off. When SRCLKEN_2 is logic low,

elect LDO3 LP mode on. When

0x05

LDO3_EN_

MediaTek Proprietary and Confidential.

7

LDO3_SW_OP_E N

1

SRCLKEN_2 is logic high, elect LDO3 LP mode off. 11: Reserved 0: Deprive the control power of RWSC LDO3_SW_EN/LP

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Page 155 of 201

MT6360U PMIC Datasheet Confidential A Address

0x06

Reg name CTRL2 (VMC)

Bit

Bit name

Default

6

LDO3_SW_EN

0

5

LDO3_SW_LP

0

4

Reserved

0

3

LDO3_GO_ON_ OP

0

2

LDO3_EN

0

1:0

LDO3_MODE

00

7:6

Reserved

00

5:4

LDO3_STCD_TD

00

3

LDO3_STCD

0

2

LDO3_PG

0

LDO3_CTRL0 (VMC)

1:0

MediaTek Proprietary and Confidential.

LDO3_PGB_PTS

01

Type

Description 1: Allow LDO3_SW_EN/LP working This bit is useless when LDO3_SW_OP_EN = 1'b0. RWSC 0: Elect LDO3 off 1: Elect LDO3 on This bit is useless when LDO3_SW_OP_EN = 1'b0. RWSC 0: Elect LDO3 LP mode off 1: Elect LDO3 LP mode on R Reserved 0: Prefer on; turn on if one of SRCLKEN_0/SRCLKEN_2/REG_EN is "ON". RWSC 1: Prefer off; turn off if one of SRECLKEN_0/SRCLKEN_2/REG_EN is "OFF". Indicates the result of enable election R 0: LDO3 is off. 1: LDO3 is on. Indicates the operation mode of LDO3 00: Normal mode R 01: NA 10: LP mode 11: NA R Reserved LDO3 FAULT extended block time after soft-start count down 00: 1 ms RW 01: 2 ms 10: 4 ms 11: 8 ms Indicates LDO3 soft-start counts down or not R 0: Off or soft-start does not count down. 1: Soft-start counts down. Indicates LDO3 power is good or not R 0: Power is not good or off. 1: Power is good. Reaction when LDO3 power not good happens 00: Only interrupt; will not disable any channel RW 01: Only shut down LDO3 and reset LDO3_EN_CTRL1/2 then set LDO3_EN = 1'b0 10: Shut down all bucks and LDOs, reset CHx_EN_CTRL1/2 and after the

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Page 156 of 201

MT6360U PMIC Datasheet Confidential A Address

0x07

Reg name

Bit

Type

Reserved

0

R

6

LDO3_SS_ISEL

1

RW

5

LDO3_LPOC_EN

0

RW

4

Reserved

0

R

3

LDO3_OCFB_EN

1

RW

2:1

LDO3_OCFB_TD

10

RW

0

LDO3_OC_PTSE L

0

RW

LDO3_STBTD

10

RW

5

LDO3_STB_SRSE L

0

RW

4

Reserved

0

R

3

LDO3_DUMMY_ LOAD_GATED_D IS

0

RW

2

LDO3_NDIS_EN

1

RW

00

RW

1011

RW

LDO3_CTRL1 (VMC)

LDO3_CTRL2 (VMC)

01: 100 μA dummy load

0x09

Default

7

7:6

0x08

Bit name

1:0

LDO3_CTRL3 (VMC)

MediaTek Proprietary and Confidential.

7:4

LOAD

LDO3_VOSEL

Description blocking time: TB_REBOOT, then confirm EN pin 11: Equal to 2'b10 Reserved Selects soft-start current 0: 25 mA 1: 8 mA 0: Disable 1: Enable Reserved OCFB function enable control 0: Disable 1: Enable Selects OCFB deglitch time 00: 10 μs 01: 15 μs 10: 60 μs 11: 100 μs Reaction when LDO3 OC happens 0: Only interrupt; will not disable LDO3 and reset LDO3_EN_CTRL1/2 then set LDO3_EN = 1'b0 1: Automatically disable LDO3 after 5 ms de-bouncing time Selects soft-start OC deglitch time 00: 40 μs 01: 120 μs 10: 1,000 μs 11: 3,000 μs Selects soft-start slew rate 0: Fast 1: Slow Reserved Permission to make LDO3_DUMMY_LOAD = 2'b00, when LDO3 in LP mode 0: LDO3_DUMMY_LOAD will be gated by LP mode. 1: LDO3_DUMMY_LOAD will be regardless with LP mode. 0: Disable output discharge 1: Enable output discharge 00: 0A dummy load 10: 1 mA dummy load 11: 1.1 mA dummy load LDO3 VO coarse-tuning 0000: Reserved …

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Page 157 of 201

MT6360U PMIC Datasheet Confidential A Address

0x0A

Reg name

LDO5_EN_ CTRL1 (VMCH)

Bit

Bit name

3:0

LDO3_VOCAL

Default

Type

0000

RW

7

LDO5_GO_LP_O P

0

RWSC

6

Reserved

0

R

5

LDO5_SRCLKEN _0_OP_EN

0

RWSC

4:3

LDO5_SRCLKEN _0_OP_CFG

00

RWSC

2

LDO5_SRCLKEN _2_OP_EN

0

RWSC

1:0

LDO5_SRCLKEN _2_OP_CFG

00

Description 0011: Reserved 0100: 1.8V 0101: Reserved … 1001: Reserved 1010: 2.9V 1011: 3.0V 1100: Reserved 1101: 3.3V 1110: Reserved 1111: Reserved Fine-tunes LDO5 VO (+10 mV/step) 0000: +00 mV 0101 :+50 mV 1010~1111: +100 mV LDO3_VOCAL = 10 mV × code 0: Prefer LP; enter LP if one of SRCLKEN_0/SRCLKEN_2/REG_EN is "LP". 1: Prefer no LP; leave LP if one of SRECLKEN_0/SRCLKEN_2/REG_EN is "NO LP". Reserved 0: Deprive the control power of SRCLKEN_0 pin for LDO5 1: Allow SRCLKEN_0 pin to control LDO5 Selects the use of SRCLKEN_0 pin when LDO5_SRCLKEN_0_OP_EN = 1'b1 00: SRCLKEN_0 pin can elect LDO5 on/off. When SRCLKEN_0 pin is logic low, elect LDO5 off. When SRCLKEN_0 pin is logic high, elect LDO5 on. 01: NA 10: SRCLKEN_0 pin can elect LDO5 LP mode on/off. When SRCLKEN_0 pin is logic low, elect LDO5 LP mode on. When SRCLKEN_0 pin is logic high, elect LDO5 LP mode off. 11: Reserved 0: Deprive the control power of SRCLKEN_2 for LDO5 1: Allow SRCLKEN_2 to control LDO5 Selects the use of SRCLKEN_2 when

LDO5_SRCLKEN_2_OP_EN = 1'b1

MediaTek Proprietary and Confidential.

00: SRCLKEN_2 can elect LDO5 on/off. RWSC When SRCLKEN_2 is logic low, elect LDO5 off. When SRCLKEN_2 is logic high, elect LDO5 on. 01: NA

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Page 158 of 201

MT6360U PMIC Datasheet Confidential A Address

0x0B

Reg name

LDO5_EN_ CTRL2 (VMCH)

Bit

Bit name

Default

Type

7

LDO5_SW_OP_E N

1

RWSC

6

LDO5_SW_EN

0

RWSC

5

LDO5_SW_LP

0

RWSC

4

Reserved

0

R

3

LDO5_GO_ON_ OP

0

RWSC

2

LDO5_EN

0

R

LDO5_MODE

00

R

7

SDCARD_HLACT

1

RW

6

SDCARD_DET_E N

0

RW

5:4

LDO5_STCD_TD

00

RW

1:0

0x0C

LDO5_CTRL0 (VMCH)

01: 2 ms

3

MediaTek Proprietary and Confidential.

LDO5_STCD

0

R

Description 10: SRCLKEN_2 can elect LDO5 LP mode on/off. When SRCLKEN_2 is logic low, elect LDO5 LP mode on. When SRCLKEN_2 is logic high, elect LDO5 LP mode off. 11: Reserved 0: Deprive the control power of LDO5_SW_EN/LP 1: Allow LDO5_SW_EN/LP working This bit is useless when LDO5_SW_OP_EN = 1'b0. 0: Elect LDO5 off. 1: Elect LDO5 on. This bit is useless when LDO5_SW_OP_EN = 1'b0. 0: Elect LDO5 LP mode off 1: Elect LDO5 LP mode on. Reserved 0: Prefer on; turn on if one of SRCLKEN_0/SRCLKEN_2/REG_EN is "ON". 1: Prefer off; turn off if one of SRECLKEN_0/SRCLKEN_2/REG_EN is "OFF". Indicates the result of enable election 0: LDO5 is on. 1: LDO5 is off. Indicates the operation mode of LDO5 00: Normal mode 01: NA 10: LP mode 11: NA Selects active level for SDCARD_DET_N pin 0: Low level 1: High level SDCARD_DET function enable control 0: Disable. SDCARD_DET_N pin is useless. 1: Enable LDO5 FAULT extended block time after soft-start count down 00: 1 ms 10: 4 ms 11: 8 ms Indicates LDO5 soft-start counts down or not

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Page 159 of 201

MT6360U PMIC Datasheet Confidential A Address

Reg name

Bit

Default

Type

LDO5_PG

0

R

1:0

LDO5_PGB_PTS EL

01

RW

7:6

Reserved

00

R

5

LDO5_LPOC_EN

1

RW

4

Reserved

0

R

3

LDO5_OCFB_EN

1

RW

2:1

LDO5_OCFB_TD

10

RW

0

LDO5_OC_PTSE L

0

RW

LDO5_STBTD

10

RW

LDO5_STB_SRSE L

0

RW

0

R

0

RW

2

0x0D

LDO5_CTRL1 (VMCH)

7:6

0x0E

LDO5_CTRL2 (VMCH)

5

1: Slow 4 3

MediaTek Proprietary and Confidential.

Bit name

Reserved LDO5_DUMMY_ LOAD_GATED_D IS

Description 0: Off or soft-start does not count down. 1: Soft-start counts down Indicates LDO5 power is good or not 0: Power is not good or off. 1: Power is good. Reaction when LDO5 power not good happens 00: Only interrupt; will not disable any channel 01: Only shut down LDO5 and reset LDO5_EN_CTRL1/2 then set LDO5_EN = 1'b0 10: Shut down all bucks and LDOs, reset CHx_EN_CTRL1/2 and after the blocking time: TB_REBOOT, then confirm EN pin 11: Equal to 2'b10 Reserved 0: Disable 1: Enable Reserved OCFB function enable control 0: Disable 1: Enable Selects OCFB deglitch time 00: 10 μs 01: 15 μs 10: 60 μs 11: 100 μs Reaction when LDO5 OC happens 0: Only interrupt; will not disable LDO5 1: Automatically disable LDO5 after 5 ms de-bouncing time and reset LDO5_EN_CTRL1/2 then set LDO5_EN = 1'b0 Selects soft-start OC deglitch time 00: 40 μs 01: 120 μs 10: 1,000 μs 11: 3,000 μs Selects soft-start slew rate 0: Fast Reserved Permission to make LDO5_DUMMY_LOAD = 2'b00, when LDO5 in LP mode

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Page 160 of 201

MT6360U PMIC Datasheet Confidential A Address

Reg name

Bit

Bit name

Default

Type

2

LDO5_NDIS_EN

1

RWSC

1:0

LDO5_DUMMY_ LOAD

00

RW

Reserved

0

R

7

0x0F

0x10

6:4

LDO5_VOSEL

010

RW

3:0

LDO5_VOCAL

0101

RW

LDO5_CTRL3 (VMCH)

7

LDO2_GO_LP_O P

0

RWSC

6

Reserved

0

R

5

LDO2_SRCLKEN _0_OP_EN

0

RWSC

4:3

LDO2_SRCLKEN _0_OP_CFG

00

RWSC

LDO2_EN_CT RL1 (VTP)

10: SRCLKEN_0 pin can elect LDO2 LP

Description 0: LDO5_DUMMY_LOAD will be gated by LP mode. 1: LDO5_DUMMY_LOAD will be regardless with LP mode. 0: Disable output discharge 1: Enable output discharge 00: 0A dummy load 01: 100 μA dummy load 10: 1 mA dummy load 11: 1.1 mA dummy load Reserved LDO5 VO coarse-tuning 000: Reserved 001: Reserved 010: 2.9V 011: 3.0V 100: Reserved 101: 3.3V 110: Reserved 111: Reserved Fine-tunes LDO5 VO (+10 mV/step) 0000: +00 mV 0101: +50 mV 1010!1111: +100 mV LDO5_VOCAL = 10 mV × code 0: Prefer LP; enter LP if one of SRCLKEN_0/SRCLKEN_2/REG_EN is "LP". 1: Prefer no LP; leave LP if one of SRECLKEN_0/SRCLKEN_2/REG_EN is "NO LP". Reserved 0: Deprive the control power of SRCLKEN_0 pin for LDO2 1: Allow SRCLKEN_0 pin to control LDO2 Selects the use of SRCLKEN_0 pin when LDO2_SRCLKEN_0_OP_EN = 1'b1 00: SRCLKEN_0 pin can elect LDO2 on/off. When SRCLKEN_0 pin is logic low, elect LDO2 off. When SRCLKEN_0 pin is logic high, elect LDO2 on. 01: NA mode on/off. When SRCLKEN_0 pin is logic low, elect LDO2 LP mode on. When SRCLKEN_0 pin is logic high, elect LDO2 LP mode off. 11: Reserved

MediaTek Proprietary and Confidential.

© 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in part, is strictly prohibited.

Page 161 of 201

MT6360U PMIC Datasheet Confidential A Address

0x11

0x12

Reg name

LDO2_EN_CT RL2 (VTP)

(VTP)

MediaTek Proprietary and Confidential.

Bit

Bit name

Default

Type

2

LDO2_SRCLKEN _2_OP_EN

0

RWSC

1:0

LDO2_SRCLKEN _2_OP_CFG

00

RWSC

7

LDO2_SW_OP_E N

1

RWSC

6

LDO2_SW_EN

0

RWSC

5

LDO2_SW_LP

0

RWSC

4

Reserved

0

R

3

LDO2_GO_ON_ OP

0

RWSC

2

LDO2_EN

0

R

1:0

LDO2_MODE

0

R

7:6

Reserved

00

R

5:4

LDO2_STCD_TD

00

RW

Description 0: Deprive the control power of SRCLKEN_2 for LDO2 1: Allow SRCLKEN_2 to control LDO2 Selects the use of SRCLKEN_2 when LDO2_SRCLKEN_2_OP_EN = 1'b1 00: SRCLKEN_2 can elect LDO2 on/off. When SRCLKEN_2 is logic low, elect LDO2 off. When SRCLKEN_2 is logic high, elect LDO2 on. 01: NA 10: SRCLKEN_2 can elect LDO2 LP mode on/off. When SRCLKEN_2 is logic low, elect LDO2 LP mode on. When SRCLKEN_2 is logic high, elect LDO2 LP mode off. 11: Reserved 0: Deprive the control power of LDO2_SW_EN/LP 1: Allow LDO2_SW_EN/LP working This bit is useless when LDO2_SW_OP_EN = 1'b0. 0: Elect LDO2 off 1: Elect LDO2 on This bit is useless when LDO2_SW_OP_EN = 1'b0. 0: Elect LDO2 LP mode off 1: Elect LDO2 LP mode on Reserved 0: Prefer on; turn on if one of SRCLKEN_0/SRCLKEN_2/REG_EN is "ON". 1: Prefer off; turn off if one of SRECLKEN_0/SRCLKEN_2/REG_EN is "OFF". Indicates the result of enable election 0: LDO2 is on. 1: LDO2 is off. Indicates the operation mode of LDO2 00: Normal mode 01: NA 10: LP mode 11: NA Reserved LDO2 FAULT extended block time after soft-start count down 00: 1 ms 01: 2 ms 10: 4 ms 11: 8 ms

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Page 162 of 201

MT6360U PMIC Datasheet Confidential A Address

0x13

Reg name

LDO2_CTRL1 (VTP)

Bit

0

R

2

LDO2_PG

0

R

1:0

LDO2_PGB_PTS EL

01

RW

7:6

Reserved

00

R

5

LDO2_LPOC_EN

1

RW

4

Reserved

0

R

3

LDO2_OCFB_EN

1

RW

2:1

LDO2_OCFB_TD

10

RW

0

LDO2_OC_PTSE L

0

RW

LDO2_STBTD

01

RW

LDO2_STB_SRSE L

0

RW

0

R

0

RW

5 4 3

Confidential.

Type

LDO2_STCD

LDO2_CTRL2

MediaTek Proprietary and

Default

3

7:6

0x14

Bit name

Reserved LDO2_DUMMY_ LOAD_GATED_D IS

Description Indicates LDO2 soft-start counts down or not 0: Off or soft-start does not count down. 1: Soft-start counts down. Indicates LDO2 power is good or not 0: Power is not good or off. 1: Power is good. Reaction when LDO2 power not good happens 00: Only interrupt; will not disable any channel 01: Only shut down LDO2 and reset LDO2_EN_CTRL1/2 then set LDO2_EN = 1'b0 10: Shut down all bucks and LDOs, reset CHx_EN_CTRL1/2 and after the blocking time: TB_REBOOT, then confirm EN pin 11: Equal to 2'b10 Reserved 0: Disable 1: Enable Reserved OCFB function enable control 0: Disable 1: Enable Selects OCFB deglitch time 00: 10 μs 01: 15 μs 10: 60 μs 11: 100 μs Reaction when LDO2 OC happens 0: Only interrupt; will not disable LDO2 1: Automatically disable LDO2 after 5 ms de-bouncing time and reset LDO2_EN_CTRL1/2 then set LDO2_EN = 1'b0 Selects soft-start OC deglitch time 00: 500 μs 01: 1,000 μs 10: 2,500 μs 11: 5,000 μs Selects soft-start slew rate 0: Fast 1: Slow Reserved Permission to make LDO2_DUMMY_LOAD = 2'b00, when LDO2 is in LP mode

© 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in part, is strictly prohibited.

Page 163 of 201

MT6360U PMIC Datasheet Confidential A Address

0x15

0x16

Reg name

Bit

Bit name

Default

2

LDO2_NDIS_EN

1

1:0

LDO2_DUMMY_ LOAD

00

7:4

LDO2_VOSEL

0100

3:0

LDO2_VOCAL

0000

LDO2_CTRL3 (VTP)

LDO1_EN_CT RL1 (VFP)

7

LDO1_GO_LP_O P

0

6

Reserved

0

5

LDO1_SRCLKEN _0_OP_EN

0

4:3

LDO1_SRCLKEN _0_OP_CFG

00

on/off. When SRCLKEN_0 pin is logic

MediaTek Proprietary and Confidential.

Type

Description 0: LDO2_DUMMY_LOAD will be gated by LP mode. 1: LDO2_DUMMY_LOAD will be regardless with LP mode. 0: Disable output discharge RW 1: Enable output discharge 00: 0A dummy load 01: 100 μA dummy load RW 10: 1 mA dummy load 11: 1.1 mA dummy load LDO2 VO coarse-tuning 0000: Reserved … 0011: Reserved 0100: 1.8V 0101: 2.0V 0110: 2.1V 0111: 2.5V RW 1000: 2.7V 1001: 2.8V 1010: 2.9V 1011: 3.0V 1100: 3.1V 1101: 3.3V 1110: Reserved 1111: Reserved Fine-tunes LDO2 VO (+10 mV/step) 0000: +00 mV RW 1010~1111: +100 mV LDO2_VOCAL = 10 mV × code 0: Prefer LP; enter LP if one of SRCLKEN_0/SRCLKEN_2/REG_EN is "LP". RWSC 1: Prefer no LP; leave LP if one of SRECLKEN_0/SRCLKEN_2/REG_EN is "NO LP". R Reserved 0: Deprive the control power of SRCLKEN_0 pin for LDO1 RWSC 1: Allow SRCLKEN_0 pin to control LDO1 Selects the use of SRCLKEN_0 pin when LDO1_SRCLKEN_0_OP_EN = 1'b1 00: SRCLKEN_0 pin can elect LDO1 RWSC low, elect LDO1 off. When SRCLKEN_0 pin is logic high, elect LDO1 on. 01: NA 10: SRCLKEN_0 pin can elect LDO1 LP mode on/off. When SRCLKEN_0 pin is

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Page 164 of 201

MT6360U PMIC Datasheet Confidential A Address

0x17

Reg name

LDO1_EN_CT RL2 (VFP)

Bit

Bit name

Default

Type

2

LDO1_SRCLKEN _2_OP_EN

0

RWSC

1:0

LDO1_SRCLKEN _2_OP_CFG

00

RWSC

7

LDO1_SW_OP_E N

1

RWSC

6

LDO1_SW_EN

0

RWSC

5

LDO1_SW_LP

0

RWSC

4

Reserved

0

R

3

LDO1_GO_ON_ OP

0

RWSC

2

LDO1_EN

0

R

LDO1_MODE

00

R

1:0

Description logic low, elect LDO1 LP mode on. When SRCLKEN_0 pin is logic high, elect LDO1 LP mode off. 11: Reserved 0: Deprive the control power of SRCLKEN_2 for LDO1 1: Allow SRCLKEN_2 to control LDO1 Selects the use of SRCLKEN_2 when LDO1_SRCLKEN_2_OP_EN = 1'b1 00: SRCLKEN_2 can elect LDO1 on/off. When SRCLKEN_2 is logic low, elect LDO1 off. When SRCLKEN_2 is logic high, elect LDO1 on. 01: NA 10: SRCLKEN_2 can elect LDO1 LP mode on/off. When SRCLKEN_2 is logic low, elect LDO1 LP mode on. When SRCLKEN_2 is logic high, elect LDO1 LP mode off. 11: Reserved 0: Deprive the control power of LDO1_SW_EN/LP 1: Allow LDO1_SW_EN/LP working This bit is useless when LDO1_SW_OP_EN = 1'b0. 0: Elect LDO1 off 1: Elect LDO1 on This bit is useless when LDO1_SW_OP_EN = 1'b0. 0: Elect LDO1 LP mode off 1: Elect LDO1 LP mode on Reserved 0: Prefer on turn on if one of SRCLKEN_0/SRCLKEN_2/REG_EN is "ON". 1: Prefer off; turn off if one of SRECLKEN_0/SRCLKEN_2/REG_EN is "OFF". Indicates the result of enable election 0: LDO1 is on. 1: LDO1 is off. Indicates the operation mode of LDO1 00: Normal mode 01: NA

10: LP mode

0x18

LDO1_CTRL0 (VFP)

MediaTek Proprietary and Confidential.

7:6

Reserved

00

R

5:4

LDO1_STCD_TD

00

RW

11: NA Reserved LDO1 FAULT extended block time after soft-start count down 00 : 1 ms

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Page 165 of 201

MT6360U PMIC Datasheet Confidential A Address

0x19

Reg name

LDO1_CTRL1 (VFP)

Bit

0x1A

Default

Type

3

LDO1_STCD

0

R

2

LDO1_PG

0

R

1:0

LDO1_PGB_PTSE L

01

RW

7:6

Reserved

00

R

5

LDO1_LPOC_EN

1

RW

4

Reserved

0

R

3

LDO1_OCFB_EN

1

RW

2:1

LDO1_OCFB_TD

10

RW

0

LDO1_OC_PTSE L

0

RW

LDO1_STBTD

01

RW

5

LDO1_STB_SRSE L

0

RW

4

Reserved

0

R

7:6 11: 5,000 μs

Bit name

LDO1_CTRL2 (VFP)

MediaTek Proprietary and Confidential.

Description 01 : 2 ms 10 : 4 ms 11 : 8 ms Indicates LDO1 soft-start counts down or not 0: Off or soft-start does not count down. 1: Soft-start counts down. Indicates LDO1 power is good or not 0: Power is not good or off. 1: Power is good. Reaction when LDO1 power not good happens 00: Only interrupt; will not disable any channel 01: Only shut down LDO1 and reset LDO1_EN_CTRL1/2 then set LDO1_EN = 1'b0 10: Shut down all bucks and LDOs, reset CHx_EN_CTRL1/2 and after the blocking time: TB_REBOOT, then confirm EN pin 11: Equal to 2'b10 Reserved 0: Disable 1: Enable Reserved OCFB function enable control 0: Disable 1: Enable Selects OCFB deglitch time 00: 10 μs 01: 15 μs 10: 60 μs 11: 100 μs Reaction when LDO1 OC happens 0: Only interrupt; will not disable LDO1 1: Automatically disable LDO1 after 5 ms de-bouncing time and reset LDO1_EN_CTRL1/2 then set LDO1_EN = 1'b0 Selects soft-start OC deglitch time 00: 500 μs 01: 1,000 μs 10: 2,500 μs Selects soft-start slew rate 0: Fast 1: Slow Reserved

© 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in part, is strictly prohibited.

Page 166 of 201

MT6360U PMIC Datasheet Confidential A Address

0x1B

Reg name

Bit

Bit name

Default

Type

3

LDO1_DUMMY_ LOAD_GATED_D IS

0

RW

2

LDO1_NDIS_EN

1

RW

1:0

LDO1_DUMMY_ LOAD

00

RW

7:4

LDO1_VOSEL

0100

RW

3:0

LDO1_VOCAL

0000

RW

LDO1_CTRL3 (VFP)

MediaTek Proprietary and Confidential.

Description Permission to make LDO1_DUMMY_LOAD = 2'b00, when LDO1 is in LP mode 0: LDO1_DUMMY_LOAD will be gated by LP mode. 1: LDO1_DUMMY_LOAD will be regardless with LP mode. 0: Disable output discharge 1: Enable output discharge 00: 0A dummy load 01: 100 μA dummy load 10: 1 mA dummy load 11: 1.1 mA dummy load LDO1 VO coarse-tuning 0000: Reserved … 0011: Reserved 0100: 1.8V 0101: 2.0V 0110: 2.1V 0111: 2.5V 1000: 2.7V 1001: 2.8V 1010: 2.9V 1011: 3.0V 1100: 3.1V 1101: 3.3V 1110: Reserved 1111: Reserved Fine-tunes LDO1 VO (+10 mV/step) 0000: +00 mV 1010~1111: +100 mV LDO1_VOCAL = 10 mV × code

© 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in part, is strictly prohibited.

Page 167 of 201

MT6360U PMIC Datasheet Confidential A Table 5-8. PD part register detail description Address 0x00

Reg name

Bit

Bit name

Default

Type

7:0

VID[7:0]

CF

R

0x01

7:0

VID[15:8]

29

R

0x02

7:0

PID[7:0]

72

R

0x03

7:0

PID[15:8]

63

R

0x04

7:0

DID[7:0]

91

R

7:0

DID[15:8]

34

R

7:0

USBTYPEC_REV

12

R

7:0

Reserved

00

R

7:0

USBPD_VER

11

R

7:0

USBPD_REV

30

R

7:0

PDIF_VER

12

R

7:0

PDIF_REV ALARM_VBUS_V OLTAGE_H

10

R

0

R

6

TX_SUCCESS

0

RW

5

TX_DISCARD

0

RW

4

TX_FAIL

0

RW

0

RW

0

RW

VENDOR_ID

PRODUCT_ID

DEVICE_ID

0x05 0x06 0x07 0x08

USBTYPEC_RE V

USBPD_REV_ VER

0x09

0x0A

PD_INTERFAC E_REV

0x0B

7

0x10

ALERT

3 2 0: Cleared

0x11

ALERT

MediaTek Proprietary and Confidential.

RX_HARD_RESE T RX_SOP_MSG_S TATUS

1

POWER_STATUS

0

RW

0

CC_STATUS

0

RW

7

VENDOR_DEFIN ED_

0

RW

Description Unique 16-bit unsigned integer Assigned by the USB-IF to the vendor. Unique 16-bit unsigned integer Assigned uniquely by the vendor to identify TCPC. Unique 16-bit unsigned integer Assigned by the vendor to identify the version of TCPC. Version number assigned by USB-IF (Currently at Revision 1.1: 0001 0001) 0001 0000: Version 1.0 0001 0001: Version 1.1 and so on. 0010 0000: Revision 2.0 0011 0000: Revision 3.0 0001 0000: Version 1.0 0001 0001: Version 1.1 0001 0010: Version 1.2 and so on. 0001 0000: Revision 1.0 0: Cleared 1: A high-voltage alarm has occurred. 0: Cleared 1: Reset or SOP* message transmission is successful. 0: Cleared 1: Reset or SOP* message transmission is not sent due to the incoming received message. 0: Cleared 1: SOP* message transmission not is successful; no GoodCRC response is received on SOP* message transmission. 0: Cleared 1: Received hard reset message 0: Cleared 1: Receive status register changed 1: Port status changed 0: Cleared 1: CC status changed 0: Cleared 1: A vendor defined alert has been

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Page 168 of 201

MT6360U PMIC Datasheet Confidential A Address

Reg name

Bit

6 5 4

0

RW

0

R

2

RXBUF_OVFLO W

0

RW

1

FAULT

1

RW

0

R

1

RW

ALARM_VBUS_V OLTAGE_L M_ALARM_VBU S_VOLTAGE_H

6

M_TX_SUCCESS

1

RW

5

M_TX_DISCARD

1

RW

4

M_TX_FAIL

1

RW

1

RW

1

RW

1

RW

1

RW

0

RW

1

R

1

R

1

R

1

RW

1

RW

2 1 0 7 6 5 4

2 1

Confidential.

R

R

3

MediaTek Proprietary and

0

0

ALERT_MASK

ALERT_MASK

Type

VBUS_SINK_DIS CNT

7

0x13

Reserved EXTENDED_STAT US_CHANGE Reserved

Default

3

0

0x12

Bit name ALERT

M_RX_HARD_RE SET M_RX_SOP_MS G_STATUS M_POWER_STAT US M_CC_STATUS M_VENDOR_DE FINED_ALERT Reserved M_EXTENDED_S TATUS_CHANGE Reserved M_VBUS_SINK_ DISCNT M_RXBUF_OVFL OW M_FAULT

Description detected. Defined in the VENDOR_DEFINED registers. Refer to the vendor datasheet for details. This bit can be cleared, regardless of the current status of the alert source. Reserved 0: Cleared 1: Extended status changed Reserved 0: Cleared 1: A VBUS sink disconnect threshold crossing has been detected 0: TCPC Rx buffer is functioning properly. 1: TCPC Rx buffer has overflowed. 0: No fault 1: A fault has occurred. Read the FAULT_STATUS register. 0: Cleared 1: A low-voltage alarm has occurred. 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked Reserved 0: Interrupt masked 1: Interrupt unmasked Reserved 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked

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Page 169 of 201

MT6360U PMIC Datasheet Confidential A Address

Reg name

Bit

Bit name M_ALARM_VBU S_VOLTAGE_L M_DBG_ACC_C ONNECT

Default

Type

1

RW

1

RW

6

M_TCPC_INITIAL

1

RW

5

M_SRC_HV

1

RW

4

M_SRC_VBUS

1

RW

1

RW

1

RW

1

RW

1

RW

1

RW

1

RW

1

RW

1

RW

0 7

0x14

POWER_STAT US_MASK

3 2 1 0 7 6 5

0x15

0x16

FAULT_STATU S_MASK

EXTENDED_ST ATUS_MASK

4

Confidential.

M_SINK_VBUS M_ALL_REGISTE RS_RESET_TO_D EFAULT M_FORCE_OFF_ VBUS M_AUTO_DISC_ FAIL M_FORCE_DISC _FAIL

3

M_VBUS_OC

1

RW

2

M_VBUS_OV

1

RW

1

M_VCON_OC

1

RW

0

M_I2C_ERROR

1

RW

0000000

R

7:1

Reserved

0

M_VSAFE0V

1

RW

7

H_IMPEDENCE

0

R

6

DEBUG_ACCESS ORY_CONNECT

CONFIG_STAN 0: Debug Accessory Connected# output 0x18 T

MediaTek Proprietary and

M_VBUS_PRESE NT_DETC M_VBUS_PRESE NT M_VCONN_PRE SENT

1

RW

Description 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked Reserved 0: Interrupt masked 1: Interrupt unmasked 0: Standard output control 1: Force all outputs to high impedance. May be used to save power in sleep controlled by TCPM. is driven low. Debug Accessory connected. 1: Debug Accessory Connected# output is driven high. No Debug Accessory connected (default).

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Page 170 of 201

MT6360U PMIC Datasheet Confidential A Address

Reg name

Bit

Bit name

Default

Type

5

AUDIO_ACC_CO NNECT

1

R

4

ACTIVE_CABLE_ CONNECT

0

R

MUX_CTRL

00

R

1

CONNECT_PRES ENT

0

RW

0

CONNECT_ORIE NT

0

RW

7

Reserved

0

R

6

ENABLE_LOOKIN G4CONNECTION _ALERT

0

RW

5

ENABLE_WATCH DOG_TIMER

0

RW

4

DEBUG_ACCESS ORY_ CONTROL

0

RW

Reserved

00

R

0

RW

3:2

0x19

TCPC_CONTR OL

3:2

result in GoodCRC response but may

1

BIST_TEST_MOD

Description Controlled by either TCPM or TCPC. TCPC should ignore writes to this bit if TCPC_CONTROL.DebugAccessoryContro l = 0b. 0: Audio accessory connected 1: No audio accessory connected controlled by TCPM 0: No active cable connected 1: Active cable connected controlled by TCPM 00: No connection 01: USB 3.1 connected 10: DP alternate mode - 4 lanes 11: USB 3.1 + display port lane 0 & 1 controlled by TCPM 0: No connection 1: Connection controlled by TCPM 0: Normal (CC1 = A5, CC2 = B5, TX1 = A2/A3, RX1 = B10/B11) 1: Flipped (CC2 = A5, CC1 = B5, TX1 = B2/B3, RX1 = A10/A11) Controlled by TCPM. TCPC should ignore writes to this bit if TCPC_CONTROL.DebugAccessoryContro l=0 Reserved 0: Disable ALERT.CcStatus assertion when CC_STATUS.Looking4Connection changes 1: Enable ALERT.CcStatus assertion when CC_STATUS.Looking4Connection changes 0: Watchdog monitoring is disabled. 1: Watchdog monitoring is enabled. 0: Controlled by TCPC 1: Controlled by TCPM. TCPM writes 1 to this register to take over control of asserting DebugAccessoryConnected#. Reserved 0: Normal operation. The incoming messages enabled by RECEIVE_DETECT are passed to TCPM via alert. 1: BIST test mode. The incoming messages enabled by RECEIVE_DETECT not be passed to TCPM via alert. TCPC may temporarily store the incoming messages in the received message buffer, but this may or may not result in

MediaTek Proprietary and Confidential.

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Page 171 of 201

MT6360U PMIC Datasheet Confidential A Address

0x1A

Reg name

Bit

Type

PLUG_ORIENT

0

RW

7

Reserved

0

R

6

DRP

0

RW

5:4

RP_VALUE

00

RW

3:2

CC2

10

RW

1:0

CC1

10

RW

7:5

Reserved DIS_FORCE_OFF _VBUS

000

R

0

RW

ROLE_CONTR OL

FAULT_CONTR OL

0: Fault detection circuit enabled

0x1C

Default

0

4

0x1B

Bit name

POWER_CON TROL

MediaTek Proprietary and Confidential.

3

DIS_VBUS_DISC _FAULT_TIMER

0

RW

2

DIS_VBUS_OC

0

RW

1

DIS_VBUS_OV

0

RW

0

DIS_VCON_OC

0

RW

7

Reserved VBUS_VOL_MO NITOR

0

R

1

RW

6

Description a Receive SOP* message status or an Rx buffer overflow alert. 0: When Vconn is enabled, apply it to the CC2 pin. Monitor the CC1 pin for BMC communications if PD messaging is enabled. 1: When Vconn is enabled, apply it to the CC1 pin. Monitor the CC2 pin for BMC communications if PD messaging is enabled. Required Reserved 0: No DRP. Bits B3..0 determine Rp/Rd/Ra settings 1: DRP 00: Rp default 01: Rp 1.5A 10: Rp 3.0A 11: Reserved 00: Ra 01: Rp (Use Rp definition in B5..4) 10: Rd 11: Open (Disconnect or don’t care) Set to 11 if enabling DRP in B7..6 00: Ra 01: Rp (Use Rp definition in B5..4) 10: Rd 11: Open (Disconnect or don’t care) Set to 11 if enabling DRP in B7..6 Reserved Not support 0: Allow STANDARD INPUT SIGNAL. Force Off VBUS control 1: Block STANDARD INPUT SIGNAL. Force Off VBUS control 0: Internal and external OCP circuit enabled 1: Internal and external OCP circuit disabled 0: Internal and external OVP circuit enabled 1: Internal and external OVP circuit disabled 1: Fault detection circuit disabled Reserved 0: VBUS_VOLTAGE monitoring is enabled.

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Page 172 of 201

MT6360U PMIC Datasheet Confidential A Address

Reg name

Bit

Default

Type

5

DIS_VOL_ALAR M

1

RW

4

AUTO_DISC_DIS CNCT_EN

0

RW

3

BLEED_DISC_EN

1

RW

2

FORCE_DISC_EN

0

RW

1

VCONN_POWER _SPT

0

RW

0

EN_VCONN

0

RW

Reserved

00

R

5

DRP_STATUS

0

R

4

DRP_RESULT

0

R

3:2

CC2_STATUS

00

R

7:6

0x1D

Bit name

CC_STATUS

Description 1: VBUS_VOLTAGE monitoring is disabled. 0: Voltage alarms power status reporting is enabled. 1: Voltage alarms power status reporting is disabled. 0: TCPC should not automatically discharge VBUS based on VBUS voltage. 1: TCPC should automatically discharge. 0: Disable bleed discharge 1: Enable bleed discharge of VBUS Discharge current: 0.6 mA 0: Disable forced discharge 1: Enable forced discharge of VBUS Discharge current: 7 mA 0: TCPC delivers at least 1W on VCONN. 1: TCPC delivers at least the power indicated in DEVICE_CAPABILITIES.VCONNPowerSup ported. 0: Disable VCONN source 1: Enable VCONN source to CC Required Reserved 0: TCPC has stopped toggling or (ROLE_CONTROL.DRP = 00). 1: TCPC is toggling. 0: TCPC is presenting Rp. 1: TCPC is presenting Rd. If (ROLE_CONTROL.CC2 = Rp) or (DrpResult = 0), 00: SRC.Open (Open, Rp) 01: SRC.Ra (below maximum vRa) 10: SRC.Rd (within the vRd range) 11: Reserved If (ROLE_CONTROL.CC2 = Rd) or (DrpResult = 1), 00: SNK.Open (below maximum vRa) 01: SNK.Default (above minimum vRdConnect) 10: SNK.Power1.5 (above minimum vRd-Connect) detects Rp 1.5A. 11: SNK.Power3.0 (above minimum vRd-Connect) detects Rp 3.0A.

If ROLE_CONTROL.CC2 = Ra, this field is set to 00. If ROLE_CONTROL.CC2 = Open, this field is set to 00. This field always returns 00 if (DrpStatus = 1) or (POWER_CONTROL.EnableVconn = 1 MediaTek Proprietary and Confidential.

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Page 173 of 201

MT6360U PMIC Datasheet Confidential A Address

0x1E

Reg name

POWER_STAT US

0: VBUS disconnected

MediaTek Proprietary and Confidential.

Bit

Bit name

Default

Type

1:0

CC1_STATUS

00

R

7

DEBUG_ACCESS ORY_CONNECT

0

R

6

TCPC_INITIAL

0

R

5

SRC_HV

0

R

4

SRC_VBUS

0

R

3

VBUS_PRESENT _DETC

1

R

2

VBUS_PRESENT

0

R

1

VCONN_PRESEN T

0

R

Description and POWER_CONTROL.PlugOrientation = 0). Otherwise, the returned value depends upon ROLE_CONTROL.CC2. If (ROLE_CONTROL.CC1 = Rp) or (DrpResult = 0), 00: SRC.Open (Open, Rp) 01: SRC.Ra (below maximum vRa) 10: SRC.Rd (within the vRd range) 11: Reserved If (ROLE_CONTROL.CC1 = Rd) or DrpResult = 1), 00: SNK.Open (below maximum vRa) 01: SNK.Default (above minimum vRdConnect) 10: SNK.Power1.5 (above minimum vRd-Connect) detects Rp-1.5A. 11: SNK.Power3.0 (above minimum vRd-Connect) detects Rp-3.0A. If ROLE_CONTROL.CC1 = Ra, this field is set to 00. If ROLE_CONTROL.CC1 = Open, this field is set to 00. This field always returns 00 if (DrpStatus = 1) or (POWER_CONTROL.EnableVconn = 1 and POWER_CONTROL.PlugOrientation = 0). Otherwise, the returned value depends upon ROLE_CONTROL.CC1. 0: No debug accessory connected 1: Debug accessory connected Reflects the state of the DebugAccessoryConnected# output if supported 0: TCPC has completed initialization and all registers are valid. 1: TCPC is still performing internal initialization. The only registers that are guaranteed to return the correct values are 00h..0Fh 0: vSafe5V 1: High voltage 0: Sourcing Vbus is disabled. 1: Sourcing Vbus is enabled. 0: VBUS present detection disabled 1: VBUS present detection enabled 1: VBUS connected 0: VCONN is not present. 1: This bit is asserted when VCONN present CC1 or CC2. Threshold is fixed at 2.4V.

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Page 174 of 201

MT6360U PMIC Datasheet Confidential A Address

0x1F

Reg name

FAULT_STATU S

Bit

Bit name

Default

Type

0

SINK_VBUS

0

R

7

ALL_REGISTERS_ RESET_TO_DEFA ULT

1

RW

6

FORCE_OFF_VB US

0

RW

5

AUTO_DISC_FAI L

0

RW

4

FORCE_DISC_FAI L

0

RW

3

VBUS_OC

0

RW

2

VBUS_OV

0

RW

1

VCONN_OC

0

RW

0

I2C_ERROR

0

RW

Description 0: Sink is disconnected (default and if not supported). 1: TCPC is sinking VBUS to the system load. This bit is asserted when TCPC resets all registers to their default value. This happens at initial power up or if an unexpected power reset occurs. 0: No fault detected, no action (default and not supported) 1: VBUS source/sink has been forced off due to external fault. 0: No discharge failure 1: Discharge commanded by the TCPM failed 0: No discharge failure 1: Discharge commanded by the TCPM failed. 0: Not in an over-current protection state 1: Over-current fault latched 0: Not in an over-voltage protection state 1: Over-voltage fault latched. 0: No fault detected 1: Over-current VCONN fault latched 0: No error 1: I2C error has occurred. Conditions for asserting this bit:  TCPM writes to A the TRANSMIT register has been sent when TRANSMIT_BUFFER is empty.  The watchdog timer has expired.  TCPM writes an invalid COMMAND.  TCPM writes a non-zero value to a reserved bit in a register.  TCPM writes to TRANSMIT_BUFFER when TCPC is transmitting the fast role swap signal as triggered by the STANDARD INPUT signal source fast role swap.  TCPM writes to CONFIG_EXTENDED1.FRSwapBidirecti onalPin and

STANDARD_INPUT_CAPABILITIES.Sou

0x20

EXTENDED_ST ATUS

MediaTek Proprietary and Confidential.

7:1

Reserved

0000000

R

0

VSAFE0V

0

R

rceFastRoleSwap is not 10. Reserved 0: VBUS is not at vSafe0V. 1: VBUS is at vSafe0V. TCPC should report VBUS is at vSafe0V

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Page 175 of 201

MT6360U PMIC Datasheet Confidential A Address

0x23

0x24

Reg name

Bit

Bit name

COMMAND

7:0

COMMAND

7:5

CPB_ROLES_SUP PORT

Default

Type

00000000

W

110

R

DEVICE_CAPA BILITIES_1L

CPB_ALL_SOP_S

SOP’_DBG/SOP”_DBG

3

MediaTek Proprietary and Confidential.

CPB_SOURCE_V CONN

1

R

Description when TCPC detects VBUS is below 0.8V. This bit is not valid when POWER_STATUS.VbusDetectionEnabled = 0. 0010 0010 DisableVbusDetect: Disable Vbus present and vSafe0V detection. TCPC should ignore this command and assert FAULT_STATUS. I2CInterfaceError if it has sourcing or sinking power over Vbus enabled 0011 0011 EnableVbusDetect: Enable Vbus present and vSafe0V detection. 1001 1001 Look4Connection. Start DRP toggling if ROLE_CONTROL.DRP = 1b. If ROLE_CONTROL.CC1/CC2 = 01b starts with Rp, if ROLE_CONTROL.CC1/CC2 =10b starts with Rd. If ROLE_CONTROL.CC1/CC2 are not both 01b or 10b, do not start toggling. TCPM should issue COMMAND.Look4Connection to enable TCPC to restart connection detection in cases where the ROLE_CONTROL contents will not change. An example of this is when a potential connection as a source occurred but was further debounced by TCPM to find the sink disconnected. In this case a source only or DRP should go back to its Unattached.Src state. This will result in ROLE_CONTROL staying the same. 000: Type-C port manager can configure the port as source only or sink only (not DRP) 001: Source only 010: Sink only 011: Sink with accessory support (optional) 100: DRP only 101: Adapter or cable (Ra) only 110: Source, sink, DRP, adapter/cable all supported 111: Not valid 0: All SOP* except 1: All SOP* messages are supported. 0: TCPC is not capable of switching VCONN. 1: TCPC is capable of switching VCONN.

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Page 176 of 201

MT6360U PMIC Datasheet Confidential A Address

0x25

0x26

Reg name

DEVICE_CAPA BILITIES_1H

DEVICE_CAPA BILITIES_2L

Bit

Bit name

Default

Type

2

CPB_SINK_VBUS

1

R

1

CPB_SOURCE_H V_VBUS

0

R

0

CPB_SOURCE_V BUS

1

R

7

CPB_VBUS_HV_T ARGET

0

R

6

CPB_VBUS_OC

0

R

5

CPB_VBUS_OV

0

R

4

CPB_BLEED_DIS C

1

R

3

CPB_FORCE_DIS C

1

R

2

CPB_VBUS_MEA SURE_ALARM

0

R

1:0

CPB_SOURCE_RP _SUPPORT

10

R

7

CPB_SINK_DISCO NNECT_DET

0

R

Description 0: TCPC is not capable of controlling the sink path to the system load. 1: TCPC is capable of controlling the sink path to the system load 0: TCPC is not capable of controlling the source high voltage path to VBUS. 1: TCPC is capable of controlling the source high voltage path to VBUS. 0: TCPC is not capable of controlling the source path to VBUS. 1: TCPC is capable of controlling the source path to VBUS. 0: VBUS_HV_TARGET register not implemented 1: VBUS_HV_TARGET register implemented 0: VBUS OCP is not reported by TCPC. 1: VBUS OCP is reported by TCPC. 0: VBUS OVP is not reported by TCPC. 1: VBUS OVP is reported by TCPC. 0: No bleed discharge is implemented in TCPC. 1: Bleed discharge is implemented in the TCPC. 0: No force discharge is implemented in TCPC. 1: Force discharge is implemented in TCPC. 0: No VBUS voltage measurement nor VBUS alarms 1: VBUS voltage measurement and VBUS alarms 00: Rp default only 01: Rp 1.5A and default 10: Rp 3.0A, 1.5A, and default 11: Reserved Rp values which may be configured by the TCPM via the ROLE_CONTROL register 0: VBUS_SINK_DISCONNECT_THRESHOLD is not implemented. (Use POWER_STATUS.VbusPresent = 0 to indicate a sink disconnect.)

1:

0x26

DEVICE_CAPA BILITIES_2L

MediaTek Proprietary and Confidential.

6

CPB_STOP_DISC _THD

0

R

VBUS_SINK_DISCONNECT_THRESHOLD is implemented. 0: VBUS_STOP_DISCHARGE_THRESHOLD is not implemented.

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Page 177 of 201

MT6360U PMIC Datasheet Confidential A Address

Reg name

Bit

Default

Type

5:4

CPB_VBUS_VOL_ ALARM_LSB

00

R

3:1

CPB_VCONN_PO WER

000

R

0

CPB_VCONN_OC F

1

R

Reserved

00

R

5

CPB_GENERIC_TI MER

0

R

4

CPB_LONG_MES SAGE

0

R

7:6

0x27

Bit name

DEVICE_CAPA BILITIES_2H

Description 1: VBUS_STOP_DISCHARGE_THRESHOLD is implemented. 00: TCPC has 25mV LSB for its voltage alarm and uses all 10 bits in VBUS_VOLTAGE_ALARM_HI_CFG and VBUS_VOLTAGE_ALARM_LO_CFG. 01: TCPC has 50mV LSB for its voltage alarm and uses only 9 bits. VBUS_VOLTAGE_ALARM_HI_CFG[0] and VBUS_VOLTAGE_ALARM_LO_CFG[0] are ignored by TCPC. 10: TCPC has 100mV LSB for its voltage alarm and uses only 8 bits. VBUS_VOLTAGE_ALARM_HI_CFG[1:0] and VBUS_VOLTAGE_ALARM_LO_CFG[1:0] are ignored by TCPC. 11: Reserved 000: 1.0W 001: 1.5W 010: 2.0W 011: 3W 100: 4W 101: 5W 110: 6W 111: External 0: TCPC is not capable of detecting a Vconn fault. 1: TCPC is capable of detecting a Vconn fault. Reserved 0: GENERIC_TIMER register is not supported. 1: GENERIC_TIMER register is supported. 0: TCPC only supports 30 bytes content of the SOP* message. The value in READABLE_BYTE_COUNT should be less than or equal to 31. The value in I2C_WRITE_BYTE_COUNT should be less than or equal to 30. 1: TCPC is capable of supporting 264 bytes content of the SOP* message.

TRANSMIT _BUFFER holds up to 264 bytes content of the SOP* message. TCPM can write up to 132 bytes to TX_BUF_BYTE_x in one burst. The value supported in I2C_WRITE_BYTE_COUNT MediaTek Proprietary and Confidential.

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Page 178 of 201

MT6360U PMIC Datasheet Confidential A Address

0x28

Reg name

Bit

Bit name

Default

Type

3

CPB_SMBUS_PE C

0

R

2

CPB_SRC_FRS

0

R

1

CPB_SNK_FRS

0

R

0

CPB_WATCHDOG

1

R

7:5

Reserved

000

R

4:3

CPB_INPUT_SRC _FRS

00

R

0

R

0

R

0

R

STANDARD_IN PUT_CAPABILI TIES 2 1

0x29

STANDARD_O UTPUT_CAPA BILITIES

MediaTek Proprietary and Confidential.

7

CPB_INPUT_VB US_EXT_OV CPB_INPUT_VB US_EXT_OC CPB_INPUT_FOR CE_OFF_VBUS CPB_OUTPUT_V BUS_SNK_DISCO NNECT

Description should be up to 132. RECEIVE_BUFFER holds up to 264 bytes 0: TCPC_CONTROL.EnableSMBusPEC is not implemented. 1: TCPC_CONTROL.EnableSMBusPEC is implemented 0: Not capable of sending Fast Role Swap signal as source when receiving COMMAND.SendFRSwapSignal or receiving STANDARD INPUT Source Fast Role Swap low. 1: Capable of sending Fast Role Swap signal as Source TCPC when receiving COMMAND.SendFRSwapSignal. If STANDARD_INPUT_CAPABITILIES.Sourc eFRSwap = 1, capable of sending Fast Role Swap signal as source when STANDARD INPUT Source Fast Role Swap is set low. 0: POWER_CONTROL.FastRoleSwapEnable is not supported as sink. 1: POWER_CONTROL.FastRoleSwapEnable is supported as sink. 0: TCPC_CONTROL.Enable watchdog timer is not implemented. 1: TCPC_CONTROL.Enable watchdog timer is implemented. Reserved 00: Not present in TCPC 01: Present in TCPC as an input only pin 10: Present in TCPC as a bidirectional pin, sharing with the STANDARD OUTPUT signal Vbus Sink Disconnect Detect Indicator. The “Vbus Sink Disconnect Detect Indicator” bit in STANDARD_OUTPUT_CAPABILITIES register should also be set to 1. 11: Reserved 0: Not present in TCPC 1: Present in TCPC 0: Not present in TCPC 1: Present in TCPC 0: Not present in TCPC 1: Present in TCPC 0: Not present in TCPC 1: Present in TCPC

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Page 179 of 201

MT6360U PMIC Datasheet Confidential A Address

Reg name

Bit 6 5 4 3 2 1

0 7:5

0x2E

0x2F

MESSAGE_HE ADER_INFO

RECEIVE_DET ECT

MediaTek Proprietary and Confidential.

Bit name CPB_OUTPUT_D EBUG_ACCESSO RY CPB_OUTPUT_V BUS_PRESENT CPB_OUTPUT_A UDIO_ACCESSO RY CPB_OUTPUT_A CTIVE_CABLE CPB_OUTPUT_ MUX_CTRL CPB_OUTPUT_C ONNECT_PRESE NT CPB_OUTPUT_C ONNECT_ORIEN T Reserved

Default

Type

0

R

0: Not present in TCPC 1: Present in TCPC

0

R

0: Not present in TCPC 1: Present in TCPC

0

R

0: Not present in TCPC 1: Present in TCPC

0

R

0

R

0

R

0: Not present in TCPC 1: Present in TCPC

0

R

0: Not present in TCPC 1: Present in TCPC

000

R

4

CABLE_PLUG

0

RW

3

DATA_ROLE

0

RW

2:1

USBPD_SPECRE V

01

RW

0

POWER_ROLE

0

RW

7

Reserved

0

R

6

EN_CABLE_RST

0

RW

5

EN_HARD_RST

0

RW

4

EN_SOP2DB

0

RW

3

EN_SOP1DB

0

RW

1

EN_SOP1

0

RW

0

EN_SOP

0

RW

Description

0: Not present in TCPC 1: Present in TCPC 0: Not present in TCPC 1: Present in TCPC

Reserved 0: Message originated from source, sink, or DRP 1: Message originated from a cable plug 0: Sink 1: Source 00: Revision 1.0 01: Revision 2.0 10: Revision 3.0 11: Reserved 0: Sink 1: Source Reserved 0: TCPC does not detect Cable Reset signaling. 1: TCPC detects Cable Reset signaling. 0: TCPC does not detect Hard Reset signaling. 1: TCPC detects Hard Reset signaling. 0: TCPC does not detect SOP_DBG’’ message. 1: TCPC detects SOP_DBG’’ message. 0: TCPC does not detect SOP_DBG’ message. 1: TCPC detects SOP_DBG’ message. 0: TCPC does not detect SOP’’ message. 1: TCPC detects SOP’’ message. 0: TCPC does not detect SOP’ message. 1: TCPC detects SOP’ message. 0: TCPC does not detect SOP message. 1: TCPC detects SOP message.

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Page 180 of 201

MT6360U PMIC Datasheet Confidential A Address 0x30

0x31

Reg name

Bit

Bit name

Default

Type

RX_BYTE_CO UNT

7:0

RX_BYTE_COUN T

00000000

RW

7:3

Reserved

00000

R

2:0

RX_FRAME_TYP E

000

R

7:0

RX_HEAD_0

00000000

R

Byte 0 (bit7-0) of message header

7:0

RX_HEAD_1

00000000

R

Byte 1 (bit15-8) of message header

7:0

RX_OBJ1_0

00000000

R

Byte 0 (bit7-0) of 1st data object

7:0

RX_OBJ1_1

00000000

R

Byte 1 (bit15-8) of 1st data object

7:0

RX_OBJ1_2

00000000

R

Byte 2 (bit23-16) of 1st data object

7:0

RX_OBJ1_3

00000000

R

Byte 3 (bit31-24) of 1st data object

7:0

RX_OBJ2_0

00000000

R

Byte 0 (bit7-0) of 2nd data object

7:0

RX_OBJ2_1

00000000

R

Byte 1 (bit15-8) of 2nd data object

7:0

RX_OBJ2_2

00000000

R

Byte 2 (bit23-16) of 2nd data object

7:0

RX_OBJ2_3

00000000

R

Byte 3 (bit31-24) of 2nd data object

7:0

RX_OBJ3_0

00000000

R

Byte 0 (bit7-0) of 3rd data object

7:0

RX_OBJ3_1

00000000

R

Byte 1 (bit15-8) of 3rd data object

7:0

RX_OBJ3_2

00000000

R

Byte 2 (bit23-16) of 3rd data object

7:0

RX_OBJ3_3

00000000

R

Byte 3 (bit31-24) of 3rd data object

7:0

RX_OBJ4_0

00000000

R

Byte 0 (bit7-0) of 4th data object

7:0

RX_OBJ4_2

00000000

R

Byte 2 (bit23-16) of 4th data object

7:0

RX_OBJ4_3

00000000

R

Byte 3 (bit31-24) of 4th data object

RX_BUF_FRA ME_TYPE

RX_BUF_HEA DER_BYTE_0 RX_BUF_HEA 0x33 DER_BYTE_1 RX_BUF_OBJ1 0x34 _BYTE_0 RX_BUF_OBJ1 0x35 _BYTE_1 RX_BUF_OBJ1 0x36 _BYTE_2 RX_BUF_OBJ1 0x37 _BYTE_3 RX_BUF_OBJ2 0x38 _BYTE_0 RX_BUF_OBJ2 0x39 _BYTE_1 RX_BUF_OBJ2 0x3A _BYTE_2 RX_BUF_OBJ2 0x3B _BYTE_3 RX_BUF_OBJ3 0x3C _BYTE_0 RX_BUF_OBJ3 0x3D _BYTE_1 RX_BUF_OBJ3 0x3E _BYTE_2 RX_BUF_OBJ3 0x3F _BYTE_3 RX_BUF_OBJ4 0x40 _BYTE_0 RX_BUF_OBJ4 Byte 1 (bit15-8) of 4th 0x41data object _BYTE_1 RX_BUF_OBJ4 0x42 _BYTE_2 RX_BUF_OBJ4 0x43 _BYTE_3 0x32

MediaTek Proprietary and Confidential.

Description Indicates number of bytes in this register that are not stale. TCPM should read the first RECEIVE_BYTE_COUNT bytes in this register. Reserved Type of received frame 000: Received SOP 001: Received SOP' 010: Received SOP'' 011: Received SOP_DBG’ 100: Received SOP_DBG’’ 110: Received Cable Reset All others are reserved.

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Page 181 of 201

MT6360U PMIC Datasheet Confidential A Address 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F

0x50

Reg name RX_BUF_OBJ5 _BYTE_0 RX_BUF_OBJ5 _BYTE_1 RX_BUF_OBJ5 _BYTE_2 RX_BUF_OBJ5 _BYTE_3 RX_BUF_OBJ6 _BYTE_0 RX_BUF_OBJ6 _BYTE_1 RX_BUF_OBJ6 _BYTE_2 RX_BUF_OBJ6 _BYTE_3 RX_BUF_OBJ7 _BYTE_0 RX_BUF_OBJ7 _BYTE_1 RX_BUF_OBJ7 _BYTE_2 RX_BUF_OBJ7 _BYTE_3

TX_BUF_FRA ME_TYPE

Bit

MediaTek Proprietary and Confidential.

Default

Type

Description

7:0

RX_OBJ5_0

00000000

R

Byte 0 (bit7-0) of 5th data object

7:0

RX_OBJ5_1

00000000

R

Byte 1 (bit15-8) of 5th data object

7:0

RX_OBJ5_2

00000000

R

Byte 2 (bit23-16) of 5th data object

7:0

RX_OBJ5_3

00000000

R

Byte 3 (bit31-24) of 5th data object

7:0

RX_OBJ6_0

00000000

R

Byte 0 (bit7-0) of 6th data object

7:0

RX_OBJ6_1

00000000

R

Byte 1 (bit15-8) of 6th data object

7:0

RX_OBJ6_2

00000000

R

Byte 2 (bit23-16) of 6th data object

7:0

RX_OBJ6_3

00000000

R

Byte 3 (bit31-24) of 6th data object

7:0

RX_OBJ7_0

00000000

R

Byte 0 (bit7-0) of 7th data object

7:0

RX_OBJ7_1

00000000

R

Byte 1 (bit15-8) of 7th data object

7:0

RX_OBJ7_2

00000000

R

Byte 2 (bit23-16) of 7th data object

7:0

RX_OBJ7_3

00000000

R

Byte 3 (bit31-24) of 7th data object

7:6

Reserved

00

R

5:4

TX_RETRY_CNT

00

RW

Reserved

0

R

000

RW

Reserved 00: No message retry is required. 01: Automatically retry message transmission once 10: Automatically retry message transmission twice 11: Automatically retry message transmission three times Reserved 000: Transmit SOP 001: Transmit SOP' 010: Transmit SOP'' 011: Transmit SOP_DBG’ 100: Transmit SOP_DBG’’ 101: Transmit Hard Reset 110: Transmit Cable Reset 111: Transmit BIST Carrier Mode 2 (TCPC should exit BIST mode no later than tBISTContMode max.)

3

2:0

TX_BYTE_COU Number of bytes TCPM 0x51 will write NT TX_BUF_HEA 0x52 DER_BYTE_0 TX_BUF_HEA 0x53 DER_BYTE_1

Bit name

TX_FRAME_TYP E

TX_BYTE_COUN T 7:0

TX_HEAD_0

00000000

RW

Byte 0 (bit7-0) of message header

7:0

TX_HEAD_1

00000000

RW

Byte 1 (bit15-8) of message header

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Page 182 of 201

MT6360U PMIC Datasheet Confidential A Address 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B

Reg name TX_BUF_OBJ1 _BYTE_0 TX_BUF_OBJ1 _BYTE_1 TX_BUF_OBJ1 _BYTE_2 TX_BUF_OBJ1 _BYTE_3 TX_BUF_OBJ2 _BYTE_0 TX_BUF_OBJ2 _BYTE_1 TX_BUF_OBJ2 _BYTE_2 TX_BUF_OBJ2 _BYTE_3 TX_BUF_OBJ3 _BYTE_0 TX_BUF_OBJ3 _BYTE_1 TX_BUF_OBJ3 _BYTE_2 TX_BUF_OBJ3 _BYTE_3 TX_BUF_OBJ4 _BYTE_0 TX_BUF_OBJ4 _BYTE_1 TX_BUF_OBJ4 _BYTE_2 TX_BUF_OBJ4 _BYTE_3 TX_BUF_OBJ5 _BYTE_0 TX_BUF_OBJ5 _BYTE_1 TX_BUF_OBJ5 _BYTE_2 TX_BUF_OBJ5 _BYTE_3 TX_BUF_OBJ6 _BYTE_0 TX_BUF_OBJ6 TX_BUF_OBJ6 _BYTE_2 TX_BUF_OBJ6 _BYTE_3

MediaTek Proprietary and Confidential.

Bit

Bit name

Default

Type

Description

7:0

TX_OBJ1_0

00000000

RW

Byte 0 (bit7-0) of 1st data object

7:0

TX_OBJ1_1

00000000

RW

Byte 1 (bit15-8) of 1st data object

7:0

TX_OBJ1_2

00000000

RW

Byte 2 (bit23-16) of 1st data object

7:0

TX_OBJ1_3

00000000

RW

Byte 3 (bit31-24) of 1st data object

7:0

TX_OBJ2_0

00000000

RW

Byte 0 (bit7-0) of 2nd data object

7:0

TX_OBJ2_1

00000000

RW

Byte 1 (bit15-8) of 2nd data object

7:0

TX_OBJ2_2

00000000

RW

Byte 2 (bit23-16) of 2nd data object

7:0

TX_OBJ2_3

00000000

RW

Byte 3 (bit31-24) of 2nd data object

7:0

TX_OBJ3_0

00000000

RW

Byte 0 (bit7-0) of 3rd data object

7:0

TX_OBJ3_1

00000000

RW

Byte 1 (bit15-8) of 3rd data object

7:0

TX_OBJ3_2

00000000

RW

Byte 2 (bit23-16) of 3rd data object

7:0

TX_OBJ3_3

00000000

RW

Byte 3 (bit31-24) of 3rd data object

7:0

TX_OBJ4_0

00000000

RW

Byte 0 (bit7-0) of 4th data object

7:0

TX_OBJ4_1

00000000

RW

Byte 1 (bit15-8) of 4th data object

7:0

TX_OBJ4_2

00000000

RW

Byte 2 (bit23-16) of 4th data object

7:0

TX_OBJ4_3

00000000

RW

Byte 3 (bit31-24) of 4th data object

7:0

TX_OBJ5_0

00000000

RW

Byte 0 (bit7-0) of 5th data object

7:0

TX_OBJ5_1

00000000

RW

Byte 1 (bit15-8) of 5th data object

7:0

TX_OBJ5_2

00000000

RW

Byte 2 (bit23-16) of 5th data object

7:0

TX_OBJ5_3

00000000

RW

Byte 3 (bit31-24) of 5th data object

7:0

TX_OBJ6_0

00000000

RW

Byte 0 (bit7-0) of 6th data object

7:0

TX_OBJ6_1

00000000

RW

Byte 1 (bit15-8) of 6th data object

7:0

TX_OBJ6_2

00000000

RW

Byte 2 (bit23-16) of 6th data object

7:0

TX_OBJ6_3

00000000

RW

Byte 3 (bit31-24) of 6th data object

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Page 183 of 201

MT6360U PMIC Datasheet Confidential A Address 0x6C 0x6D 0x6E 0x6F

0x8A

0x8C

Reg name TX_BUF_OBJ7 _BYTE_0 TX_BUF_OBJ7 _BYTE_1 TX_BUF_OBJ7 _BYTE_2 TX_BUF_OBJ7 _BYTE_3

Bit

Bit name

Default

Type

7:0

TX_OBJ7_0

00000000

RW

Byte 0 (bit7-0) of 7th data object

7:0

TX_OBJ7_1

00000000

RW

Byte 1 (bit15-8) of 7th data object

7:0

TX_OBJ7_2

00000000

RW

Byte 2 (bit23-16) of 7th data object

7:0

TX_OBJ7_3

00000000

RW

Byte 3 (bit31-24) of 7th data object

7:6

RP_VALUE_CC2

00

RW

5

RP_VALUE_CC2_ EN

0

RW

00000

R

CC_CTRL1

4:0

Reserved

7:5

VCONN_OCP_SE L

010

RW

4:1

Reserved

0000

R

VCONNCTRL1

0

VCONN_CLIMIT_ EN

0

RW

7

PD_DISMODE_E N

0

RW

6

ENEXTMSG

1

RW

0x8F

MediaTek Proprietary and Confidential.

Description

RP value of CC2 00: Rp default 01: Rp 1.5A 10: Rp 3.0A 11: Reserved Note: These bits work when RP_VALUE_CC2_EN is 1'b1. When this bit is 1'b1, RP value of CC1 and CC2 can select different values. 0: RP value of CC1 and CC2 are determined by RP_VALUE (reg 0x1A[5:4]). 1: RP value of CC1 is determined by RP_VALUE (reg 0x1A[5:4]). RP value of CC2 is determined by RP_VALUE_CC2 (reg 0x8A[7:6]). Reserved Selects PD_VCONN OCP level 000: 100 mA 001: 200 mA 010: 300 mA 011: 400 mA 100: 500 mA 101: 600 mA 110: 700 mA 111: 800 mA Reserved PD_VCONN OCP current limit 0: OCP shutdown mode (disable PD_VCONN immediately when OC occurs) 1: OCP current limit mode (PD will clamp the current of PD_VCONN not to exceed OC level when OC occurs) PD disable mode control 0: Enable PD connection 1: Disable PD connection 0: Disable PD3.0 extended message 1: Enable PD3.0 extended message affect GoodCRC receive detect between PD2.0 and PD3.0

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Page 184 of 201

MT6360U PMIC Datasheet Confidential A Address

Reg name

Bit

Default

Type

5

SHIPPING_OFF

0

RW

4

WAKEUP_EN

1

RW

3

AUTOIDLE_EN

0

RW

010

RW

2:0

0x90

Bit name

AUTOIDLE_TIME OUT

7

PD_BG_EN

1

RW

6

BMCIO_IDLE_EN

0

RW

5

VCONN_DISCHA RGE_EN

0

RW

3

LPWR_EN

0

RW

MODECTRL3

MediaTek Proprietary and Confidential.

Description In shutdown/shipping mode, both CC1 and CC2 keep with Rd, PD function is disabled. Exiting shutdown/shipping mode, PD function is available. 0: Shutdown/Shipping mode 1: Non-shutdown/shipping mode Wake up function for that can escape from low-power mode when CC is attached under low-power mode 0: Disable 1: Enable When it enters idle mode, OSC of interrupt is closed for power saving. If there are status changes on CC or Vbus, OSC will be restarted. The idle mode timeout time is based on AUTOIDLE_TIMEOUT(0x8F[2:0]) setting 0: Disable auto entering idle mode 1: Enable auto entering idle mode These bits can be used to set up the time before entering into auto idle, and the time setting is based on: (AUTOIDLE_TIMEOUT×2 + 1)*6.4 ms 000: 6.4 ms 001: 19.2 ms 010: 32 ms … 111: 96 ms This bit will enable PD bandgap and OSC_320K. Furthermore, the whole PD function is gated by this bit. 0: Disable PD bandgap and OSC_320K 1: Enable PD bandgap and OSC_320K When no I2C command, interrupt and CC communication occurs, and the manual idle function can be on. 0: Disable 1: Enable PD_VCONN discharge path 0: Disable 1: Enable Selects CC pin pull-up voltage in lowpower mode 0: Disable LDO (bypass VDDA) 1: Enable LDO (2V) Set this bit to 1'b1, CC will enter lowpower mode. In low-power mode, CC apply low-power Rp/Rd to reduce power consumption, and CC will exit

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Page 185 of 201

MT6360U PMIC Datasheet Confidential A Address

Reg name

Bit

1

RW

1

VBUS_DET_EN

1

RW

0

BMCIO_OSC_EN

1

RW

Reserved

00

R

M_VBUS_VALID

0

RW

0

RW

0

RW

4 3

M_OTD_FLAG

0

RW

1

M_VBUS_80

0

RW

0

M_WAKEUP

0

RW

0

RW

0

RW

0

R

0

RW

0

RW

0

RW

0

RW

0

RW

0

RW

6 5 4 RT_MASK2

3 2 1

1: Interrupt unmasked

0 0x93

RT_MASK3

MediaTek Proprietary and Confidential.

M_VBUS_MEAS _80_F M_VCONN_SHT _GND

2

7

0x92

Type

PD_IREF_EN

5

RT_MASK1

Default

2

7:6

0x91

Bit name

7

M_WATER_DET _DONE M_WATER_EVE NT Reserved M_VCONN_VALI D M_VCONOCP_ CLIMIT M_VCONN_RV M_VCONN_OV M_VCONN_OV _CC1 M_CMP_VBUS_ TO_CC2

Description low-power mode when Rp or Rd attached on CC1 or CC2 automatically. 0: Exit low-power mode 1: Enter low-power mode Set this bit to enable PD IREF. PD function can work after PD IREF is enabled. 0: Disable PD IREF 1: Enable PD IREF PD VBUS detection function 0: Disable 1: Enable 24M oscillator for BMC communication 0: Disable 24M oscillator 1: Enable 24M oscillator Note: 24M oscillator will be enabled automatically when INT occurs. Reserved 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked Reserved 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked

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Page 186 of 201

MT6360U PMIC Datasheet Confidential A Address

Reg name

Bit 6 5 4 3:0

0x95

M_CTD Reserved

Default

Type

0

RW

0

RW

0

RW

0000

R

7

M_MIDDET_CC2

0

RW

6

M_MIDDET_CC1

0

RW

5

M_HIDET_CC2

0

RW

4

M_HIDET_CC1

0

RW

3

M_LODET_CC2

0

RW

2

M_LODET_CC1

0

RW

0

RW

0

RW

00

R

RT_MASK5

1 0 7:6

0x96

Bit name M_CMP_VBUS_ TO_CC1 M_TX_DISCARD _TIMEOUT

RT_INT1

M_RA_CABLE_C C2 M_RA_CABLE_C C1 Reserved

5

INT_VBUS_VALI D

0

RWC

4

INT_VBUS_ME AS_80_F

0

RWC

3

INT_VCONN_S HT_GND

0

RWC

2

INT_OTD_FLAG

0

RWC

1

INT_VBUS_80

0

RWC

0

INT_WAKEUP

0

RWC

0

RWC

INT_ONESHOT_E VENT 0x97

RT_INT2 6

MediaTek Proprietary and Confidential.

INT_RUST_EVEN T

Description 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked Reserved 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked 0: Interrupt masked 1: Interrupt unmasked Reserved 0: Cleared 1: When VBUS_VALID status (0x9B[5]) changes 0: Cleared, 1: When VBUS_MEAS_80 (0x9B[4]) status changes from 1'b0 to 1'b1 0: Cleared 1: When VCONN_SHT_GND status (0x9B[3]) changes to 1'b1 0: Cleared 1: When OTD_FLAG status (0x9B[2]) changes from 1'b0 to 1'b1 0: Cleared 1: When VBUS_SAFE0V (0x9B[1]) changes from 1'b0 to 1'b1 0: Cleared 1: Exit low-power mode When RUST_DET_ONESHOT_EN is set to 1'b1, the detection is operated. 0: Detection is not operated. 1: Detection is over. Water detection interrupt 0: No event 1: When the number of counts set by

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Page 187 of 201

MT6360U PMIC Datasheet Confidential A Address

0x98

0x9A

Reg name

RT_INT3

RT_INT5

MediaTek Proprietary and Confidential.

Bit

Bit name

Default

Type

5

Reserved

0

R

4

INT_VCONN_IN VALID

0

RWC

3

INT_VCONNOCP _CLIMIT_F

0

RWC

2

INT_VCONN_RV

0

RWC

1

INT_VCONN_OV _CC2

0

RWC

0

INT_VCONN_OV _CC1

0

RWC

7

INT_CMP_VBU S_TO_CC2

0

RWC

6

INT_CMP_VBU S_TO_CC1

0

RWC

5

Reserved

0

R

4

INT_CTD

0

RWC

3:0

Reserved

0000

R

7

INT_MIDDET_CC 2

0

RWC

6

INT_MIDDET_CC 1

0

RWC

5

INT_HIDET_CC2

0

RWC

4

INT_HIDET_CC1

0

RWC

3

INT_LODET_CC2

0

RWC

1

INT_RA_CABLE_ CC2

0

RWC

Description 0xC1[3:2] with rust status (0xC0[3:0]) is achieved, this bit will become 1'b1. Reserved 0: Cleared 1: VCONN_INVALID status (0x9C[4]) changes from 1'b0 to 1'b1. 0: Cleared 1: VCONN_OCP_FLAG (0x9C[3]) changes from 1'b1 to 1'b0 at current limit mode. 0: Cleared 1: VCONN_RV status (0x9C[2]) changes from 1'b0 to 1'b1. 0: Cleared 1: VCONN_OV_CC2 status (0x9C[1]) changes from 1'b0 to 1'b1(level trigger). 0: Cleared 1: VCONN_OV_CC1 status (0x9C[0]) changes from 1'b0 to 1'b1(level trigger). 0: Cleared 1: CMP_VBUS_TO_CC2 status (0x9D[7]) changes from 1'b0 to 1'b1. 0: Cleared 1: CMP_VBUS_TO_CC1 status (0x9D[6]) changes from 1'b0 to 1'b1. Reserved 0: Cleared 1: When cable yype detection is done. Reserved 0: Cleared 1: MIDDET_CC2 status (0x9F[7]) changes 0: Cleared 1: MIDDET_CC1 status (0x9F[6]) changes 0: Cleared 1: HIDET_CC2 status (0x9F[5]) changes 0: Cleared 1: HIDET_CC1 status (0x9F[4]) changes 0: Cleared 1: LODET_CC2 status (0x9F[3]) changes 0: Cleared 1: LODET_CC1 status (0x9F[2]) changes 0: Cleared 1: RA_CABLE_CC2 status (0x9F[1]) changes from 1'b0 to 1'b1.

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Page 188 of 201

MT6360U PMIC Datasheet Confidential A Address

Reg name

Bit

Bit name

Default

0

INT_RA_CABLE_ CC1

0

Reserved

00

5

VBUS_VALID

0

4

VBUS_MEAS_80

0

3

VCONN_SHT_GN D

0

2

OTD_FLAG

0

1

VBUS_SAFE0V

0

0

Reserved

0

WD_STATUS

00

5

Reserved

0

4

VCONN_INVALID

0

3

VCONN_OCP_FL AG

0

R

2

VCONN_RV

0

R

7:6

0x9B

RT_ST1

7:6

0x9C

RT_ST2

Type

Description

0: Cleared RWC 1: RA_CABLE_CC1 status (0x9F[0]) changes from 1'b0 to 1'b1 R Reserved 0: When VBUS voltage is lower than VREF_VBUS_VALID (0xDA[7:5]) R 1: When VBUS voltage is greater than VREF_VBUS_VALID (0xDA[7:5]) 0: When VBUS voltage is lower than VREF_VBUS_MEAS(0xD9[5:0]) R 1: When VBUS voltage is greater than VREF_VBUS_MEAS (0xD9[5:0]) PD_VCONN short to GND means PD_VCONN is not greater than 2.4V after VCONN_SHT_GND_TIMER R (0xE3[5:4]) when PD_VCONN is enabled. 0: No PD_VCONN short to GND 1: PD_VCONN short to GND This bit works when TYPEC_OTD_EN (0x8A[2]) is enabled. R 0: OT event does not occur. 1: OT event occurs. Note: OT event is from PMIC. 0: When VBUS voltage is greater than 0.8V. R 1: When VBUS voltage is lower than 0.8V. R Reserved Water detection results (update after water detection check is done) 00: No water R 01: CC1 or CC2 has water. 10: DP or DM has water. 11: Either of CC1 or CC2 and either of DP or DM has water. R Reserved 0: PD_VCONN voltage is greater than 2.7V. 1: PD_VCONN voltage is lower than R 2.7V. Note: This bit works when VCONN_CLIMIT_EN (0x8C[0]) is enabled.

0: PD_VCONN current is lower than

MediaTek Proprietary and Confidential.

VCONN_OCP_SEL (0x8C[7:5]) setting. 1: PD_VCONN current is greater than VCONN_OCP_SEL (0x8C[7:5]) setting. When CC (selected for VCONN) voltage is greater than PD_VCONN (internal

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Page 189 of 201

MT6360U PMIC Datasheet Confidential A Address

0x9D

Reg name

RT_ST3

Bit

Bit name

Default

Type

1

VCONN_OV_CC2

0

R

0

VCONN_OV_CC1

0

R

7

CMP_VBUS_TO_ CC2

0

R

6

CMP_VBUS_TO_ CC1

0

R

5

Reserved

0

R

4

CABLE_TYPE

0

R

0000

R

0

R

3:0

7 0x9F

Reserved

MIDDET_CC2

RT_ST5

Description VCONN voltage), PD_VCONN RV event will occur. 0: No PD_VCONN RV occurs. 1: PD_VCONN RV occurs. 0: CC2 voltage is lower than 5.75V. 1: CC2 voltage is greater than 5.75V. Note: This bit works when VCONN_OVP_EN_CC2 (0xE2[3]) is enabled. 0: CC1 voltage is lower than 5.75V. 1: CC1 voltage is greater than 5.75V. Note: This bit works when VCONN_OVP_EN_CC1 (0xE2[4]) is enabled. Result of VBUS short to CC2 detection 0: CC2 voltage is less than 3.45V 1: CC2 voltage is greater than 3.45V Note: This bit works when CMPEN_VBUS_TO_CC2 (0xDC[7]) is set to 1'b1. Result of VBUS short to CC1 detection 0: CC1 voltage is less than 3.45V 1: CC1 voltage is greater than 3.45V Note: This bit works when CMPEN_VBUS_TO_CC1 (0xDC[6]) is set to 1'b1. Reserved Result of cable type detection This bit will keep 1'b0 when VBUS is not present. 0: Type-C 1: Type-A Reserved Result of CC2 voltage detection 0: CC2 voltage is less than VREF_LODET_CC2 (0xD5[3:0]) or greater than VREF_HIDET_CC2 (0xD5[7:4]). 1: CC2 voltage is greater than VREF_LODET_CC2 (0xD5[3:0]) and greater than VREF_HIDET_CC2 (0xD5[7:4]). Note: This bit works when CMPEN_VDET_CC2 (0xDB[5]),

CMPEN_LODET_CC2 (0xDB[4]), and

6 MediaTek Proprietary and Confidential.

MIDDET_CC1

0

R

CMPEN_HIDET_CC2 (0xDB[3]) are all set to 1'b1. Result of CC1 voltage detection 0: CC1 voltage is less than VREF_LODET_CC1 (0xD6[3:0]) or greater than VREF_HIDET_CC1

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MT6360U PMIC Datasheet Confidential A Address

Reg name

Bit

Bit name

Default

Type

5

HIDET_CC2

0

R

4

HIDET_CC1

0

R

3

LODET_CC2

0

R

2

LODET_CC1

0

R

Description (0xD6[7:4]). 1: CC1 voltage is greater than VREF_LODET_CC1 (0xD6[3:0]) and greater than VREF_HIDET_CC1(0xD6[7:4]). Note: This bit works when CMPEN_VDET_CC1 (0xDB[2]), CMPEN_LODET_CC1 (0xDB[1]), and CMPEN_HIDET_CC1(0xDB[0]) are all set to 1'b1. Result of CC2 voltage detection 0: CC2 voltage is greater than VREF_HIDET_CC2 (0xD5[7:4]). 1: CC2 voltage is less than VREF_HIDET_CC2 (0xD5[7:4]). Note: This bit works when CMPEN_VDET_CC2 (0xDB[5]) and CMPEN_HIDET_CC2 (0xDB[4]) are both set to 1'b1. Result of CC1 voltage detection 0: CC1 voltage is greater than VREF_HIDET_CC1 (0xD6[7:4]). 1: CC1 voltage is less than VREF_HIDET_CC1 (0xD6[7:4]). Note: This bit works when CMPEN_VDET_CC1 (0xDB[2]) and CMPEN_HIDET_CC1 (0xDB[1]) are both set to 1'b1. Result of CC2 voltage detection 0: CC2 voltage is less than VREF_LODET_CC2 (0xD5[3:0]). 1: CC2 voltage is greater than VREF_LODET_CC2 (0xD5[3:0]). Note: This bit works when CMPEN_VDET_CC2 (0xDB[5]) and CMPEN_LODET_CC2 (0xDB[3]) are both set to 1'b1. Result of CC1 voltage detection 0: CC1 voltage is less than VREF_LODET_CC1 (0xD6[3:0]). 1: CC1 voltage is greater than VREF_LODET_CC1 (0xD6[3:0]). Note: This bit works when CMPEN_VDET_CC1 (0xDB[2]) and CMPEN_LODET_CC1 (0xDB[0]) are both

set to 1'b1.

1

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RA_CABLE_CC2

0

R

E-Mark Cable (RA) detection on CC2 during low-power mode 0: No RA cable on CC2 1: RA cable on CC2 Note: This bit works when low-power

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Page 191 of 201

MT6360U PMIC Datasheet Confidential A Address

Reg name

Bit

Bit name

Default

Type

0

RA_CABLE_CC1

0

R

0000000

R

0

W

7:1 0xA0

SOFTRESET

0xA2

DRP_CTRL1

0xA3

DRP_CTRL2

0xA4

DRP_CTRL3

0

Reserved SOFT_RESET

7:4

Reserved

0000

R

3:0

TDRP

0011

RW

7:0

DCSRCDRP[7:0]

01000111

RW

7:2

Reserved

000000

R

1:0

DCSRCDRP[9:8]

01

RW

Description mode is enabled. (LPWR_EN(0x90[3]) = 1'b1) E-Mark Cable (RA) detection on CC1 during low-power mode 0: No RA cable on CC1. 1: RA cable on CC1. Note: This bit works when low-power mode is enabled. (LPWR_EN(0x90[3]) = 1'b1) Reserved When writing 1'b1 to this bit, it will trigger soft-reset event, and all register settings will be reset to default value. Reserved The period a DRP will complete a Source to Sink and back advertisement Period = TDRP×6.4 + 51.2 ms 0000: 51.2 ms 0001: 57.6 ms 0010: 64 ms 0011: 70.4 ms … 1110: 140.8 ms 1111: 147.2 ms Percent of time that a DRP will advertise source during tDRP DUTY = (DCSRCDRP[9:0] + 1)/1024 0000000000: 1/1024 0000000001: 2/1024 … 0101000111: 328/1024 … 1111111110: 1023/1024 1111111111: 1024/1024 Note: Setting with 0xA4[9:8] Default: 328/1024 Reserved Percent of time that a DRP will advertise source during tDRP DUTY = (DCSRCDRP[9:0] + 1)/1024 0000000000: 1/1024 0000000001: 2/1024 … 0101000111: 328/1024

… 1111111110: 1023/1024 1111111111: 1024/1024 Note: Setting with 0xA3[7:0] Default: 328/1024

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Page 192 of 201

MT6360U PMIC Datasheet Confidential A Address

Reg name

Bit

0xBD

CABLE_TYPE_ CTRL

7:0

CTD_TIMER

7:4

0xBE

WATCHDOG_C TRL 3:0

7

0xBF

Bit name

Default

Type

00011001

RW

Reserved

0000

R

WATCHDOG_SEL

1011

RW

I2C_TO_RST_EN

0

RW

I2C_TO_RST_C TRL 6:4

Reserved

000

R

3:0

I2C_TO_RST_SEL

1000

RW

Description Cable Type Detect timer starts when RP connect or CTD_ONESHOT (0xEC[0]) = 1'b1, and stops when Cable Type Detect timer timeout. Cable Type Detect timer timeout = (CTD_TIMER)×3.2 ms 00000000: 0 ms 00000001: 3.2 ms … 00011001: 80 ms ... 11111110: 812.8 ms 11111111: 816.0 ms Reserved The watchdog timer should start when any of the interrupts that are not masked in the Alert register are set or when the Interrupt pin is asserted. Watchdog timeout time = (WATCHDOG_SEL + 1)×0.4 sec 0000: 0.4s 0001: 0.8s … 1011: 4.4s ... 1110: 6.0s 1111: 6.4s Set this bit to 1'b1 to enable I2C reset timer. When I2C reset timer is enabled, it will monitor SCL and SDA. When SCL and SDA both keep low, I2C reset timer will start to count, and I2C reset timer will be cleared to 0 when SCL or SDA becomes high. When I2C reset timer timeout, it will trigger soft reset event, and all register will reset to default value. 0: Disable I2C reset timer 1: Enable I2C reset timer Reserved Timeout time for I2C reset timer Timeout time = (I2C_TO_RST_SEL + 1)×12.5 ms 0000: 12.5 ms 0001: 25.0 ms

…

0xC0

WD_DET_CTR L1

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7

WD_DPDM_DE T_EN

0

RW

1000: 112.5 ms ... 1111: 200 ms When this bit set to 1'b1, it will enable water detection flow. When water

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Page 193 of 201

MT6360U PMIC Datasheet Confidential A Address

Reg name

Bit

Bit name

Default

Type

6

WD_PROTECT_ EN

0

RW

5

WD_ONESHOT _EN

0

RW

4

WD_VBUS_MO DE_STS

0

R

3

WD_CC2_RUST _STS

0

R

2

WD_CC1_RUST _STS

0

R

1

WD_DM_RUST _STS

0

R

0

WD_DP_RUST_ STS

0

R

Water detection status of DM

MediaTek Proprietary and Confidential.

Description detection flow is enabled, it will process water detection checked on DP or DM after CC1 or CC2 attached. 0: Disable Water Detection flow 1: Enable Water Detection flow Note: Water detection flow works when low-power mode is enabled (LPWR_EN(0x90[3]) = 1'b1). When this bit set to 1'b1, it will enable water protection flow. In water protection flow, CC1/CC2 or DP/DM will process water detection checked periodically (determined by WD_PINS_SEL(0xC1[7:6])). When CC1/CC2/DP/DM are not in water detection check, they will keep in floating. The period is determined from WD_SLEEP_TIME (0xC4[7:0]). 0: Disable water protection flow 1: Enable water protection flow Note: Water protection flow is work when low-power mode is enabled (LPWR_EN(0x90[3]) = 1'b1). Set this bit to 1'b1 to trigger one-shot mode in water detection. When oneshot mode is triggered, it will process water detection check on CC1/CC2 or DP/DM (determined by WD_PINS_SEL (0xC1[7:6])). 0: Not trigger 1: Trigger (after detection done → reset to 0 automatically) WD+ mode status (for micro-b VBUS trigger DPDM water detection) 0: Disable WD+ mode 1: Enable WD+ mode Note: When WD+ mode is enabled, every time VBUS detect event occurs, one-shot mode is triggered once. Water detection status of CC2 0: No water detected in CC2 1: Water is detected in CC2. Water detection status of CC1 0: No water detected in CC1 1: Water is detected in CC1. 0: No water detected in DM 1: Water is detected in DM. Water detection status of DP 0: No water detected in DP 1: Water is detected in DP.

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Page 194 of 201

MT6360U PMIC Datasheet Confidential A Address

0xC1

0xC4

0xD5

Reg name

WD_DET_CTR L2

WD_DET_CTR L5

Bit

Bit name

Default

Type

7:6

WD_PINS_SEL

00

RW

5:4

Reserved

00

R

3:2

WD_PINS_CNT

00

RW

1:0

WD_EXIT_COUN T

00

RW

7:0

WD_SLEEP_TIM 00001001 E

RW

7:4

VREF_HIDET_CC 2

RW

HILO_CTRL1

0111

Description Selects WD pins when WD_PROTECT_EN or WD_ONESHOT_EN is set to 1 00: DP, DM, CC1 and CC2 01: DP and DM 10: CC1 and CC2 11: Reserved Reserved Water detection senses CC1/CC2/DP/DM four pins, "WD_PINS_CNT=00" means at least 1 pin is detected for water detection. 00: At least 1 pin 01: At least 2 pins 10: At least 3 pins 11: At least 4 pins (all of four pins are detected water) Exiting counts during rust protection flow (when WD_PROTECT_EN is 1) 00: 1 01: 2 10: 4 11: 8 Check period in water protection flow (when WD_PROTECT_EN (0xC0[6]) is 1'b1) 00000000: 102.4 ms 00000001: 204.8 ms … 00001001: 1.024s ... 11111110: 26.112s 11111111: 26.214s CC voltage high detection VREF setting for CC2 Adjust VREF for dedicated voltage detect and trigger HIDET interrupt. This setting is also applied to DRP when toggled as source to detect dedicated attached CC level. (VREF = 0.2V×(Code + 1)) 0000: 0.2V 0001: 0.4V ... 0111: 1.6V (default)

...

3:0

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VREF_LODET_CC 2

0001

RW

1110: 3.0V 1111: 3.2V CC voltage low detection VREF setting for CC2

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Page 195 of 201

MT6360U PMIC Datasheet Confidential A Address

0xD6

1: Enable

0xD9

Reg name

Bit

Bit name

Default

Type

7:4

VREF_HIDET_CC 1

0111

RW

3:0

VREF_LODET_CC 1

0001

RW

HILO_CTRL2

7

VBUS_HYS_EN

1

RW

6

VBUS_MEAS_EN

0

RW

VBUS_CTRL1

5:0

MediaTek Proprietary and Confidential.

VREF_VBUS_ME AS_80

000000

RW

Description Adjust VREF for dedicated voltage detect and trigger LODET interrupt. This setting is also applied to DRP when toggled as source to detect dedicated attached CC level. (VREF = 0.2V×(Code + 1)) 0000: 0.2V 0001: 0.4V ... 1110: 3.0V 1111: 3.2V CC voltage high detection VREF setting for CC1 Adjust VREF for dedicated voltage detect and trigger HIDET interrupt. This setting also applies to DRP when toggled as source to detect dedicated attached CC level. (VREF = 0.2V×(Code + 1)) 0000: 0.2V 0001: 0.4V ... 0111: 1.6V (default) ... 1110: 3.0V 1111: 3.2V CC voltage low detection VREF setting for CC1 Adjust VREF for dedicated voltage detect and trigger LODET interrupt. This setting also applies to DRP when toggled as source to detect dedicated attached CC level. (VREF = 0.2V×(Code + 1)) 0000: 0.2V 0001: 0.4V ... 1110: 3.0V 1111: 3.2V VBUS detection hysteresis voltage 0: Disable 1: Enable Enables VBUS voltage measure comparator 0: Disable Voltage for VBUS*80% voltage measure Threshold: 0.5~24V, LSB = 0.5V*80% 000000: 0.5V*80% 000001: 1.0V*80%

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Page 196 of 201

MT6360U PMIC Datasheet Confidential A Address

0xDA

0xDC

Reg name

VBUS and CC_CTRL

Bit

7:5

VREF_VBUS_VAL ID

4:0

Reserved

Default

Type

000

RW

00000

R

7

CMPEN_VBUS_T O_CC2

0

RW

6

CMPEN_VBUS_T O_CC1

0

RW

000000

R

RESV_SEL

5:0

0xEC

Bit name

Reserved

7

DIS_RPDET

0

RW

6

RPDET_ONESHO T

0

RW

5

OT_CCOPEN_EN

1

RW

4

VBUS_AUTODIS

0

R

3

VBUS_BLEEDDIS

0

R

CTD_CTRL2

Description … 101110: 23.5V*80% 101111: 24.0V*80% 110000: Reserved … 111111: Reserved VBUS_VALID (0x9B[5]) threshold: 2.6~ 4.0V, LSB = 0.2V 000: 2.6V 001: 2.8V … 110: 3.8V 111: 4.0V Reserved 0: Disable VBUS short to CC2 detection 1: Enable VBUS short to CC2 detection (Check if CC2 voltage is greater than 3.45V or not) 0: Disable VBUS short to CC1 detection 1: Enable VBUS short to CC1 detection (Check if CC1 voltage is greater than 3.45V or not) Reserved Rp Connect auto detection will check if Rp connects on CC every time CC acts as Sink after DRP toggling is finished. 0: Enable Rp Connect auto detection 1: Disable Rp Connect auto detection Set this bit to 1'b1 to enable Rp Connect detection manually. It will check if Rp connects on CC when CC acts as sink. This bit works when RP Connect auto detection is disabled. (DIS_RPDET(0xEC[7]) set to 1'b1). 0: Disable Rp Connect detection 1: Enable Rp Connect detection Enables CC open when Type-C Connector OT is detected 0: No change on CC when Type-C Connector OT is detected. 1: Set CC open when Type-C Connector OT is detected. VBUS auto discharge status 0: Not perform auto discharge

1: Perform auto discharge

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VBUS bleed discharge status 0: Not perform bleed discharge 1: Perform bleed discharge

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Page 197 of 201

MT6360U PMIC Datasheet Confidential A Address

Reg name

MediaTek Proprietary and Confidential.

Bit

Bit name

Default

Type

2

VBUS_FORCEDIS

0

R

1

CTD_EN

1

RW

0

CTD_ONESHOT

0

RW

Description VBUS force discharge status 0: Not perform force discharge 1: Perform force discharge Set this bit to 1'b1 to enable auto cable type detection. For auto cable type detection, it will check the cable is Type-C or Type-A every time after cable plug-in when CC acts as sink. 0: Disable auto cable type detection 1: Enable auto cable type detection Set this bit to 1'b1 will trigger one-shot cable type detection. It will process cable type detection once. This bit will clear to 1'b0 when cable type detection is finished. 0: No operation 1: Trigger one-shot cable type detection Note: This bit works when CTD_EN (0xEC[1]) is 1'b0.

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Page 198 of 201

MT6360U PMIC Datasheet Confidential A

6

MT6360U Packaging

6.1

Outline Dimensions

Figure 6-1. Package dimension MediaTek Proprietary and Confidential.

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Page 199 of 201

MT6360U PMIC Datasheet Confidential A

Appendix

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Page 200 of 201

MT6360U PMIC Datasheet Confidential A

Exhibit 1 Terms and Conditions Your access to and use of this document and the information contained herein (collectively this “Document”) is subject to your (including the corporation or other legal entity you represent, collectively “You”) acceptance of the terms and conditions set forth below (“T&C”). By using, accessing or downloading this Document, You are accepting the T&C and agree to be bound by the T&C. If You don’t agree to the T&C, You may not use this Document and shall immediately destroy any copy thereof. This Document contains information that is confidential and proprietary to MediaTek Inc. and/or its affiliates (collectively “MediaTek”) or its licensors and is provided solely for Your internal use with MediaTek’s chipset(s) described in this Document and shall not be used for any other purposes (including but not limited to identifying or providing evidence to support any potential patent infringement claim against MediaTek or any of MediaTek’s suppliers and/or direct or indirect customers). Unauthorized use or disclosure of the information contained herein is prohibited. You agree to indemnify MediaTek for any loss or damages suffered by MediaTek for Your unauthorized use or disclosure of this Document, in whole or in part. MediaTek and its licensors retain titles and all ownership rights in and to this Document and no license (express or implied, by estoppels or otherwise) to any intellectual propriety rights is granted hereunder. This Document is subject to change without further notification. MEDIATEK DOES NOT ASSUME ANY RESPONSIBILITY ARISING OUT OF OR IN CONNECTION WITH ANY USE OF, OR RELIANCE ON, THIS DOCUMENT, AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY, INCLUDING, WITHOUT LIMITATION, CONSEQUENTIAL OR INCIDENTAL DAMAGES. THIS DOCUMENT AND ANY OTHER MATERIALS OR TECHNICAL SUPPORT PROVIDED BY MEDIATEK IN CONNECTION WITH THIS DOCUMENT, IF ANY, ARE PROVIDED “AS IS” WITHOUT WARRANTY OF ANY KIND, WHETHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE. MEDIATEK SPECIFICALLY DISCLAIMS ALL WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, COMPLETENESS OR ACCURACY AND ALL WARRANTIES ARISING OUT OF TRADE USAGE OR OUT OF A COURSE OF DEALING OR COURSE OF PERFORMANCE. MEDIATEK SHALL NOT BE RESPONSIBLE FOR ANY MEDIATEK DELIVERABLES MADE TO MEET YOUR SPECIFICATIONS OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM. Without limiting the generality of the foregoing, MEDIATEK MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR DOES MEDIATEK ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT, CIRCUIT OR SOFTWARE. You agree that You are solely responsible for the designing, validating and testing Your product incorporating MediaTek’s product and ensure such product meets applicable standards and any safety, security or other requirements. The above T&C and all acts in connection with the T&C or this Document shall be governed, construed and interpreted in accordance with the laws of Taiwan, without giving effect to the principles of conflicts of law.

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