Logic And Computer Design Fundamentals

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1-1

OUTPUT

INPUT 5.0

HIGH

4.0

HIGH

3.0 2.0 LOW

1.0 0.0 Volts

LOW

Fig. 1-1 An Example of Voltage Ranges for Binary Signals

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

1-2

Memory

CPU

Control unit

Datapath

Input/Output Fig. 1-2 Block Diagram of a Digital Computer

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

1-3

TABLE 1-1 Powers of Two n

2n

n

2n

n

2n

0 1 2 3 4 5 6 7

1 2 4 8 16 32 64 128

8 9 10 11 12 13 14 15

256 512 1,024 2,048 4,096 8,192 16,384 32,768

16 17 18 19 20 21 22 23

65,536 131,072 262,144 524,288 1,048,576 2,097,152 4,194,304 8,388,608

Table 1-1 Powers of Two

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

1-4

TABLE 1-2 Numbers with Different Bases Decimal (base 10)

Binary (base 2)

Octal (base 8)

Hexadecimal (base 16)

00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

00 01 02 03 04 05 06 07 10 11 12 13 14 15 16 17

0 1 2 3 4 5 6 7 8 9 A B C D E F

Table 1-2 Numbers with Different Bases © 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

1-5

TABLE 1-3 Binary-Coded Decimal (BCD) Decimal Symbol

BCD Digit

0 1 2 3 4 5 6 7 8 9

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001

Table 1-3 Binary-Coded Decimal (BCD)

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

1-6

TABLE 1-4 American Standard Code for Information Interchange (ASCII) B 7 B6 B5 B4 B3 B 2 B1

000

001

010

011

100

101

110

111

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

NULL SOH STX ETX EOT ENQ ACK BEL BS HT LF VT FF CR SO SI

DLE DC1 DC2 DC3 DC4 NAK SYN ETB CAN EM SUB ESC FS GS RS US

SP ! " # $ % &

0 1 2 3 4 5 6 7 8 9 : ; < = > ?

@ A B C D E F G H I J K L M N O

P Q R S T U V W X Y Z [ \ ] ^ _

` a b c d e f g h i j k l m n o

p q r s t u v w x y z { | } ~ DEL

′

( ) * + , . /

Control Characters:

NULL SOH STX ETX EOT ENQ ACK BEL BS HT LF VT FF CR SO SI SP

NULL Start of heading Start of text End of text End of transmission Enquiry Acknowledge Bell Backspace Horizontal tab Line feed Vertical tab Form feed Carriage return Shift out Shift in Space

DLE DC1 DC2 DC3 DC4 NAK SYN ETB CAN EM SUB ESC FS GS RS US DEL

Data link escape Device control 1 Device control 2 Device control 3 Device control 4 Negative acknowledge Synchronous idle End of transmission block Cancel End of medium Substitute Escape File separator Group separator Record separator Unit separator Delete

Table 1-4 American Standard Code for Information Interchange (ASCII) © 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

2-1

TABLE 2-1 Truth Tables for the Three Basic Logic Operations AND X

Y

0 0 1 1

0 1 0 1

Z = X⋅Y

0 0 0 1

OR X

Y

0 0 1 1

0 1 0 1

Z = X +Y

0 1 1 1

NOT X

Z=X

0 1

1 0

Table 2-1 Truth Tables for the Three Basic Logical Operations

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

2-2

X

X

Z = X •Y

Y

Z = X +Y

Y

• NOT gate or inverter

OR gate

AND gate

X

(a) Graphic symbols

X

0

0

1

1

Y

0

1

0

1

(AND)

X •Y

0

0

0

1

(OR)

X +Y

0

1

1

1

(NOT)

X

1

1

0

0

(b) Timing diagram Fig. 2-1 Digital Logic Gates © 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

X

2-3

A B C

F = A BC

(a) Three-input AND gate

A B C D E F

F=A+B+C+D+E+F (b) Six-input OR gate

Fig. 2-2 Gates with More than Two Inputs

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

2-4

TABLE 2-2 Truth Table for the Function F ⫽ X ⫹ YZ X

Y

Z

F

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0 1 0 0 1 1 1 1

Table 2-2 Truth Table for the Function F ⫽ X ⫹ Y Z

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

2-5

X Y

•

Z Fig. 2-3 Logic Circuit Diagram for F = X + Y′Z

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

F

2-6

TABLE 2-3 Basic Identities of Boolean Algebra 1. 3. 5. 7. 9. 10. 12. 14. 16.

X +0 = X X +1 = 1 X +X = X X +X = 1 X=X X +Y = Y +X X + (Y + Z ) = (X + Y ) + Z X ( Y + Z) = XY + XZ X +Y = X⋅Y

2. 4. 6. 8.

X⋅1 = X X⋅0 = 0 X⋅X = X X⋅X = 0

11. 13. 15. 17.

XY = YX X( YZ) = ( XY )Z X + YZ = ( X + Y ) (X + Z ) X⋅Y = X +Y

Table 2-3 Basic Identities of Boolean Algebra

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

Commutative Associative Distributive DeMorgan’s

2-7

TABLE 2-4 Truth Tables to Verify DeMorgan’s Theorem A)

X

Y

X ⫹Y

X +Y

0 0 1 1

0 1 0 1

0 1 1 1

1 0 0 0

B)

X

Y

X

Y

X⋅Y

0 0 1 1

0 1 0 1

1 1 0 0

1 0 1 0

1 0 0 0

Table 2-4 Truth Tables to Verify DeMorgan’s Theorem

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

2-8

TABLE 2-5 Truth Table for Boolean Function X

Y

Z

F

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0 0 1 1 0 1 0 1

Table 2-5 Truth Table for Boolean Function

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

2-9

X

•

•

•

•

Y

•

Z

F

• (a) F = XYZ + XYZ + XZ

X

•

•

Y F Z (b) F = XY + XZ Fig. 2-4 Implementation of Boolean Function with Gates

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

2-10

TABLE 2-6 Minterms for Three Variables X

Y

Z

Product Term

Symbol

m0

m1

m2

m3

m4

m5

m6

m7

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

XYZ X YZ XYZ XYZ XY Z XYZ XYZ XYZ

m0 m1 m2 m3 m4 m5 m6 m7

1 0 0 0 0 0 0 0

0 1 0 0 0 0 0 0

0 0 1 0 0 0 0 0

0 0 0 1 0 0 0 0

0 0 0 0 1 0 0 0

0 0 0 0 0 1 0 0

0 0 0 0 0 0 1 0

0 0 0 0 0 0 0 1

Table 2-6 Minterms for Three Variables

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

2-11

TABLE 2-7 Maxterms for Three Variables X

Y

Z

Sum Term

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

X +Y +Z X +Y +Z X +Y +Z X +Y +Z X +Y +Z X +Y +Z X +Y +Z X +Y +Z

Symbol

M0

M1

M2

M3

M4

M5

M6

M7

M0 M1 M2 M3 M4 M5 M6 M7

0 1 1 1 1 1 1 1

1 0 1 1 1 1 1 1

1 1 0 1 1 1 1 1

1 1 1 0 1 1 1 1

1 1 1 1 0 1 1 1

1 1 1 1 1 0 1 1

1 1 1 1 1 1 0 1

1 1 1 1 1 1 1 0

Table 2-7 Maxterms for Three Variables

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

2-12

TABLE 2-8 Boolean Functions of Three Variables (a)

X

Y

Z

F

F

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

1 0 1 0 0 1 0 1

0 1 0 1 1 0 1 0

(b)

X

Y

Z

E

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

1 1 1 0 1 1 0 0

Table 2-8 Boolean Functions of Three Variables

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

2-13

Y X Y Z X Y Fig. 2-5 Sum-of-Products Implementation

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

F

2-14

A B

A B

C

C

D

D

C

E

E (a) AB + C ( D + E )

(b) AB + CD + CE

Fig. 2-6 Three-Level and Two-Level Implementation

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

2-15

X Y Z

F

X Y Z Fig. 2-7 Product-of-Sums Implementation

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

2-16

Y X

0

1

m0

m1

0 XY

XY

m2

m3

1 XY

XY

(a)

(b)

Fig. 2-8 Two-Variable Map

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

2-17

Y X

0

1

0

1 (a) XY

1

1 1

0

0 1

Y X

1

1

(b) X + Y

Fig. 2-9 Representation of Functions in the Map

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

2-18

YZ X

Y 00

01

11

10

m0

m1

m3

m2

0 XY Z XY Z XY Z XY Z

m4

m5

m7

m6

X 1 XY Z XY Z XY Z XY Z Z

(a)

(b) Fig. 2-10 Three-Variable Map

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

2-19

YZ 00 X

Y 01

0 X 1

XY

1

11

10

1

1

XY

1 Z

Fig. 2-11 Map for Example 2-3

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

2-20

YZ 00 X

Y 01

11

3 10 XZ

1

7 5

0

0

1

3

2

2

0

X 1

4

5

7

6

6

4

XZ Z (a)

(b)

Fig. 2-12 Three-Variable Map: Flat and on a Cylinder to Show Adjacent Squares

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

2-21

YZ 00 X

01

11

10

0

1

1

X 1

1

1

Z

X YZ 00 X

Y Z

0

1

Y 01

11

10

1

1

1

1

1

X 1

Z

Z

(a)

(b)

Fig. 2-13 Product Terms Using Four Minterms

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

Y

2-22

YZ 00 X

Y 01

11 1

0 X 1

10

1

1

1

YZ 00 X 0

1

X 1

1

Z

Y 01

11

10 1

1

1 Z

(a) F1 (X, Y, Z) = Σm (3, 4, 6, 7) = YZ + XZ

(b) F2 (X, Y, Z) = Σm(0, 2, 4, 5, 6) = Z + XY

Fig. 2-14 Maps for Example 2-4

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

2-23

YZ 00 X 0 X 1

1

Y 01

11

1

1

1

10

1 Z

Fig. 2-15 F( X, Y , Z ) = Σm(1, 3, 4, 5, 6)

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

2-24

YZ 00 X

Y 01

11

10

0

1

1

1

X 1

1

1 Z

Fig. 2-16 F( X, Y , Z ) = Σm (1 ,2 , 3, 5, 7)

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

2-25

YZ 00 WX m0

m1

m3

m2

00

m4

m5

m7

m6

01

Y 11

01

10

X 11

m 12 m 13 m 15 m 14 W m8

m9

m 11 m 10

10

Z (a)

(b) Fig. 2-17 Four-Variable Map

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

2-26

YZ 00 WX 00 01

0 4

Y 01

11

10

1

3

2

5

7

XZ 2

0

10

8

6 X

11

12

13

15

14

W 10

XZ

11

9 8

9

11

10

3

1

Z (a)

(b)

Fig. 2-18 Four-Variable Map: Flat and on a Torus to Show Adjacencies

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

2-27

YZ 00 WX

Y 11

01

10

00

1

1

1

01

1

1

1 X

11

1

1

10

1

1

1

W

Z Fig. 2-19 Map for Example 2-5: F = Y + WZ + XZ

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

2-28

C

CD AB 00

00

01

1

1

11

10 1

01

1 B

11 A 10

1

1

1 D

Fig. 2-20 Map for Example 2-6: F = BD + BC + ACD

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

2-29

C

CD 00

AB 00 01

1

01

11

1

1

1

1

10

1 B

11

1

1

A 10

D Fig. 2-21 Prime Implicants for Example 2-7: AD, BD, and AB

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

2-30

C

CD 00

AB 00

11

01

10

00

AB 00

1

01

C

CD

10

1

01

1

11

01

1

B 11

1

1

B 11

1

A

1

1

1

A 10

1

1

10

D (a) Plotting the minterms

1

1

D (b) Essential prime implicants

Fig. 2-22 Simplification with Prime Implicants in Example 2-8

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

2-31

C

CD 00

01

00

1

1

01

1

1

AB

11

10

3

1

B 11 A

1

1

10

1

1

D 1

2

Fig. 2-23 Map for Example 2-9

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

2-32

C

CD 00

01

11

10

00

1

1

0

1

01

0

1

0

0

AB

B 11

0

0

0

0

1

1

0

1

A 10

D Fig. 2-24 Map for Example 2-10: F = (A + B) (C + D) (B + D)

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

2-33

C

CD 00

01

11

10

00

X

1

1

X

01

0

X

1

0

AB

C

CD 00

01

11

10

00

X

1

1

X

01

0

X

1

0

AB

B 11

0

0

1

B

0

A

11

0

0

1

0

10

0

0

1

0

A 10

0

0

1

0

D (a) F = CD + AB

D (b) F = CD + AD

Fig. 2-25 Example with Don't-Care Conditions

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

2-34

Graphics Symbols Name

AND

OR

Distinctive shape

Rectangular shape

X

X

F = XY

Y 0 1 0 1

F 0 0 0 1

F = X +Y

X 0 0 1 1

Y 0 1 0 1

F 0 1 1 1

F Y

X

X

≥1

F

Y

F Y

1

NOT (inverter)

X

Buffer

X

•

F

X

F

X

•

F

F=X

X 0 1

F 1 0

F

F=X

X 0 1

F 0 1

1

NAND

NOR

Exclusive–OR (XOR)

Exclusive–NOR (XNOR)

X Y

X Y

X

•

•

X

•

F 1 1 1 0

F = X +Y

X 0 0 1 1

Y 0 1 0 1

F 1 0 0 0

F

F = XY + XY =X Y

X 0 0 1 1

Y 0 1 0 1

F 0 1 1 0

F

F = XY + XY =X Y

X 0 0 1 1

Y 0 1 0 1

F 1 0 0 1

F

≥1

F

•

F

Y

X

=1

F

Y

Y

Y 0 1 0 1

Y

X

X

F = X •Y

X 0 0 1 1

&

F

Y

X

•

=1

•

F Y

Truth table X 0 0 1 1

&

F

Y

Algebraic equation

Fig. 2-26 Digital Logic Gates © 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

2-35

NOT

AND

X

X

•

Y

X OR Y

XX

•

• •

•

X

•

XY = XY

•

XY = X + Y

Fig. 2-27 Logical Operations with NAND Gates

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

2-36

X Y Z

•

XYZ

X Y Z

•

X + Y + Z = XYZ

(b) NOT – OR

(a) AND - NOT X

• • •

X

X

•

X

(c) NOT Fig. 2-28 Alternative Graphics Symbols for NAND and NOT Gates

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

2-37

A

A

B

B

•

• •

F C

C

D

D

•

(a)

(b) A B C D

• •

F

• (c)

Fig. 2-29 Three Ways to Implement F = AB + CD

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

F

2-38

YZ 00 X 0

Y 01

11

10

1

1

1 F = XY + XY + Z

X 1

1

1

1 Z (a)

X

•

Y X

Y

• • •

•

Y Z

X

•

F

X Y

• •

•

Z (c)

(b) Fig. 2-30 Solution to Example 2-12 © 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

F

2-39

C D B A F

B C (a) AND – OR gates C D

•

B

• •

•

A B C

• (b) NAND gates Fig. 2-31 Implementing F = A (CD + B) + BC

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

• •

F

2-40

A B A

F

B

E

C D (a) AND – OR gates A

•

B A

•

B C D

• •

• •

E

• X

• •

(b) NAND gates Fig. 2-32 Implementing F = ( A B + AB )E (C + D) © 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

•

F

2-41

Inverter X

OR

XX

•

X

•

Y

X AND Y

• •

•

X

•

X +Y = X +Y

•

X + Y = XY

Fig. 2-33 Logic Operations with NOR Gates

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

2-42

X Y Z

•

X +Y + Z

X Y Z

• • •

(a) OR – NOT

XYZ = X +Y + Z (b) NOT – AND

Fig. 2-34 Two Graphic Symbols for NOR Gate

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

2-43

A B C D

• •

• • •

F

E Fig. 2-35 Implementing F = (A + B) (C + D) E with NOR Gates

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

2-44

B A B C D

• • • •

•

• •

Y

F

•

A

E

•

• •

Fig. 2-36 Implementing F = (AB + AB) E (C + D) with NOR Gates

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

2-45

X

•

• •

• •

• •

• Y

• Fig. 2-37 Exclusive-OR Constructed with NAND Gates

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

F=X

Y

2-46

YZ 00 X

Y 01 1

0 X 1

11

10

00

AB 00

1

1

C

CD

10 1

1

01

1

11

01

1

1

B 11

Z

1

1

A (a) X

Y

Z

10

1

1 D

(b) A

B

C

Fig. 2-38 Maps for Multiple-Variable Odd Functions

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

D

2-47

TABLE 2-9 Truth Table for an Even Parity Generator Three-Bit Message X

Y

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

Parity Bit

Z

0 1 0 1 0 1 0 1

P

0 1 1 0 1 0 0 1

Table 2-9 Truth Table for an Even Parity Generator

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

2-48

X

X

Y

Y

Z

Z P

P (a) P = X

Y

Z

C

(b) C = X Fig. 2-39 Multiple-Input Odd Functions

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

Y

Z

P

2-49

IN

IN

•

OUT

OUT

t PLH

tPHL

t pd = max (t PHL, t PLH ) Fig. 2-40 Propagation Delay for an Inverter

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

2-50

A

B A B: No Delay (ND)

a

b

c

d e

Transport Delay (TD)

Inertial Delay (ID)

0

2

4

6

8

10

12

14

16 Time (ns)

Fig. 2-41 Examples of Behavior of Transport and Inertial Delays © 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

2-51

Signal value

Logic value

Signal value

Logic value

H

1

H

0

L

0

L

1

(a) Positive logic

(b) Negative logic

Fig. 2-42 Signal Assignment and Logic Polarity

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

2-52 X L L H H

Y L H L H

Z L L L H

(a) Truth table with H and L X 0 0 1 1

Y 0 1 0 1

Z 0 0 0 1

(c) Truth table for positive logic X 1 1 0 0

Y 1 0 1 0

Z 1 1 1 0

(e) Truth table for negative logic

X Y

CMOS Gate

Z

(b) Gate block diagram

X Y

Z

(d) Positive-logic AND gate X Y

Z

(f) Negative-logic OR gate

Fig. 2-43 Demonstration of Positive and Negative Logic © 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

2-53

C

• X

TG

•

X • • Y C = 1 and C = 0 Y

•

(b)

TG

X

C

X • • Y C = 0 and C = 1

(a)

(c)

C

• (d)

Fig. 2-44 Transmission Gate (TG)

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

Y

2-54

• A

•

TG0

C

•

•

•

• •

•

F

A

C

TG1

TG0

F

0

0

No path

Path

0

0

1

Path

No path

1

1

0

No path

Path

1

1

1

Path

No path

0

TG1

(a) Fig. 2-45 Transmission Gate Exclusive-OR

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

(b)

3-1

n inputs

• • •

Combinational circuit

• • •

m outputs

Fig. 3-1 Block Diagram of Combinational Circuit

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

3-2 X0 X1 X 2 9-Input X3 0dd X4 X5 function X6 X7 X8

ZO

(a) Symbol for circuit

X0 X1 X2 X3 X4 X5 X6 X7 X8

A 0 3-Input A 1 odd B O A function 2

A 0 3-Input A 1 odd B O A function

A 0 3-Input A 1 odd B O A function

2

ZO

2

A 0 3-Input A 1 odd B O A function 2

(b) Circuit as interconnected 3-input odd function blocks A0 A1

BO

A2 (c) 3-input odd function circuit as interconnected exclusive-OR blocks

•

• •

•

(d) Exclusive-OR block as interconnected NANDs

Fig. 3-2 Example of Design Hierarchy and Reusable Blocks

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

3-3

9-input odd function

3-input odd function

XOR

3-input odd function

XOR

XOR

9-input odd function

3-input odd function

XOR

XOR

XOR

3-input odd function

XOR

XOR

3-input odd function

XOR

-NAND (a) Fig. 3-3 Diagrams Representing the Hierarchy for Figure 3-2

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

(b)

3-4

HDL Description of Circuit

Electronic, Speed, and Area Constraints

Technology Library

Translation

Intermediate Representation

Pre-optimization

Optimization/ Technology Mapping

Netlist Fig. 3-4 High-Level Flow for Synthesis Tool

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

3-5

•

A B

•

T3

•

T1

F1

C

• D

T2

•

T4

• T5 Fig. 3-5 Logic Diagram for Analysis Example

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

F2

3-6

X Y Z

• •

• •

•

T1 S

•

T2

•

T3

• • •

•

Fig. 3-6 Logic Diagram for Binary Adder

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

C

3-7

TABLE 3-1 Truth Table for Binary Adder X

Y

Z

C

C

T1

T2

T3

S

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0 0 0 1 0 1 1 1

1 1 1 0 1 0 0 0

0 0 0 0 0 0 0 1

0 1 1 1 1 1 1 1

0 1 1 0 1 0 0 0

0 1 1 0 1 0 0 1

Table 3-1 Truth Table for Binary Adder

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

3-8

X S Y

AND3

OR2

Z

OR3 AND2 AND2 INV C

AND2

OR3

AND2

Fig. 3-7 Xilinx Foundation Schematic for Binary Adder in Figure 3-6

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

3-9

0.0

iX iY iZ

20ns

40ns

60ns

80ns

100ns

120ns

140ns

Cs Cs Cs

oS oC Fig. 3-8 Waveforms for the Binary Adder Schematic in Figure 3-7

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

3-10

X 0 0 0 0 1 1 1 1

Y 0 0 1 1 0 0 1 1

Z 0 1 0 1 0 1 0 1

F 1 1 1 0 0 0 0 0

(a) Truth table

YZ 00 X 0

1

Y 01

11

1

10

X

1

Y

•

X 1 Z

• •

Z (b) Map F = XY + XZ Fig. 3-9 Solution to Example 3-1

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

(c) Logic diagram

• •

F

3-11

TABLE 3-2 Truth Table for Code Converter Example Decimal Digit

0 1 2 3 4 5 6 7 8 9

Input BCD

Output Excess-3

A

B

C

D

W

X

Y

Z

0 0 0 0 0 0 0 0 1 1

0 0 0 0 1 1 1 1 0 0

0 0 1 1 0 0 1 1 0 0

0 1 0 1 0 1 0 1 0 1

0 0 0 0 0 1 1 1 1 1

0 1 1 1 1 0 0 0 0 1

1 0 0 1 1 0 0 1 1 0

1 0 1 0 1 0 1 0 1 0

Table 3-2 Truth Table for Code Converter Example

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

3-12 C

CD 00

AB

11

01

C

CD 10

00

AB

00

00

01

1

1

1

01

1

11

X

01

11

10

1

1

1

X

X

X

1

X

X

B 11

X

X

X

B

X

A

A 10

1

1

X

10

X

D

D X = BC + BD + BCD

W = A + BC + BD

C

CD 00

AB

11

01

C

CD 10

00

AB

11

01

10

00

1

1

00

1

1

01

1

1

01

1

1

11

X

10

1

B 11

X

X

X

B

X

A

X

X

X

X

X

A 10

1

X

X

D Y = CD + CD

D Z=D

Fig. 3-10 Maps for BCD-to-Excess-3 Code Converter

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

3-13

A W

•

• B

•

•

X

• • C

•

•

• D

•

•

Y

•

Fig. 3-11 Logic Diagram of BCD-to-Excess-3 Code Converter © 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

Z

3-14

a f e

b g

c

d (a) Segment designation

(b) Numeric designation for display Fig. 3-12 Seven-Segment Display

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

3-15

TABLE 3-3 Truth Table for BCD–to–Seven-Segment Decoder BCD Input

Seven-Segment Decoder

A

B

C

D

a

b

c

d

e

f

g

0 0 0 0 0 0 0 0 1 1

0 0 0 0 1 1 1 1 0 0

0 0 1 1 0 0 1 1 0 0

0 1 0 1 0 1 0 1 0 1

1 0 1 1 0 1 1 1 1 1

1 1 1 1 1 0 0 1 1 1

1 1 0 1 1 1 1 1 1 1

1 0 1 1 0 1 1 0 1 1

1 0 1 0 0 0 1 0 1 0

1 0 0 0 1 1 1 0 1 1

0 0 1 1 1 1 1 0 1 1

0

0

0

0

0

0

0

All other inputs

Table 3-3 Truth Table for BCD–to–Seven-Segment Decoder

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

3-16 D0 = A2 A1 A0

• A0

•

•

• •

•

• A1

• •

•

• A2

•

• •

• •

•

•

•

• • •

•

D1 = A2 A1 A0

D2 = A2 A1 A0

D3 = A2 A1 A0

D4 = A2 A1 A0

D5 = A2 A1 A0

D6 = A2 A1 A0

D7 = A2 A1 A0 Fig. 3-13 3-to-8-Line Decoder © 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

3-17

• A0

•

•

• A1 E

•

•

•

•

•

D0

•

•

D1

•

•

D2

• •

•

D3

E

A1 A0

D 0 D1 D2 D3

0 0 0 0 1

0 0 1 1 X

0 1 1 1 1

0 1 0 1 X

1 0 1 1 1

1 1 0 1 1

(b) Truth table

D0 = E A1 A0 D1 = E A1 A0 D2 = E A1 A0 D3 = E A1 A0

(a) Logic diagram

(c) Logic Equations

Fig.3-14 A 2–to–4-Line Decoder

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

1 1 1 0 1

3-18

TABLE 3-4 Truth Table for 3–to–8-Line Decoder Inputs

Outputs

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0 0 0 0 0 0 0 1

0 0 0 0 0 0 1 0

0 0 0 0 0 1 0 0

0 0 0 0 1 0 0 0

0 0 0 1 0 0 0 0

0 0 1 0 0 0 0 0

0 1 0 0 0 0 0 0

1 0 0 0 0 0 0 0

Table 3-4 Truth Table for 3–to–8-Line Decoder

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

3-19

2–to–4 Decoder A0

•

A1 A2

• •

•

20 21

0 1

D0

2 3

D2

0 1

D4

2 3

D6

D1 D3

Enable

2–to–4 Decoder 20 21 Enable

D5 D7

Fig. 3-15 A 3-to-8 Decoder Constructed with Two 2-to-4 Decoders

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

3-20

3–to–8 Decoder

Z

20

Y

21

X

22

0 1 2 3 4 5 6 7

S

C

•

Fig. 3-16 Implementing a Binary Adder Using a Decoder

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

3-21

TABLE 3-5 Truth Table for Octal–to–Binary Encoder Inputs

Outputs

D7

D6

D5

D4

D3

D2

D1

D0

A2

A1

A0

0 0 0 0 0 0 0 1

0 0 0 0 0 0 1 0

0 0 0 0 0 1 0 0

0 0 0 0 1 0 0 0

0 0 0 1 0 0 0 0

0 0 1 0 0 0 0 0

0 1 0 0 0 0 0 0

1 0 0 0 0 0 0 0

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

Table 3-5 Truth Table for Octal–to–Binary Encoder

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

3-22

TABLE 3-6 Truth Table of Priority Encoder Inputs

Outputs

D3

D2

D1

D0

A1

A0

V

0 0 0 0 1

0 0 0 1 X

0 0 1 X X

0 1 X X X

X 0 0 1 1

X 0 1 0 1

0 1 1 1 1

Table 3-6 Truth Table of Priority Encoder

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

3-23

D1D0 D3D2 00 00

X

01

1

11 D3

10

D1 11

01

D3D2

10

00 1

1

1

1

1 D3

1

1

1

1

00

01

X

11

10

1

1

01

1 D2

1

D1

D2D0

D2

11

1

1

1

1

10

1

1

1

1

D0

D0

A1 = D2 + D3 Fig. 3-17 Maps for Priority Encoder

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

A 0 = D 3 + D 1D 2

3-24

D3

•

•

•

D2

A0 D1

• • •

A1

V D0 Fig. 3-18 Logic Diagram of a 4-Input Priority Encoder

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

3-25

Function table S0 S1

•

•

S1 S0 0 0 1 1

•

•

• D0

0 1 0 1

Y D0 D1 D2 D3

•

•

D1

Y

• D2

D3 Fig. 3-19 4-to-1-Line Multiplexer

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

3-26 S0

•

•

S1

•

• • TG (S 0 = 0)

D0

•

•

• D1

•

•

TG (S 1 = 0)

•

TG (S 0 = 1)

• •

D2

•

•

TG (S 0 = 0)

• •

•

TG (S 1 = 1)

•

D3

TG (S 0 = 1)

•

Fig. 3-20 4-to-1-Line Multiplexer with Transmission Gates © 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

•

Y

3-27 A0 Y0 A1

•

A2

•

A3

•

•

Y1

•

Y2

•

Y3

B0

• B1

•

B2

•

B3

•

• S (select)

•

Function table E 0 1 1

• •

•

E (enable)

Fig. 3-21 Quadruple 2-to-1-Line Multiplexer © 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

S X 0 1

Output Y All 0's Select A Select B

3-28

4 x 1 MUX

X 0 0 0 0 1 1 1 1

Y 0 0 1 1 0 0 1 1

Z 0 1 0 1 0 1 0 1

F 0 1 1 0 0 0 1 1

(a) Truth table

F=Z F=Z F=0

Y

S0

X

S1

Z

0

Z

1

0

2

1

3

F=1 (b) Multiplexer implementation

Fig. 3-22 Implementing a Boolean Function with a Multiplexer

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

F

3-29

8 x 1 MUX A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

F 0 1 0 1 1 0 0 0 0 0 0 1 1 1 1 1

C

S0

B

S1

F=D

A

S2

F=D

D

F=D

•

•

0 1

F=0 F=0

• 0

• •

2 3 4

F=D F=1

5 1

•

6 7

F=1

Fig. 3-23 Implementing a Four-Input Function with a Multiplexer

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

F

3-30

E

• S0

•

•

• •

• •

• S1

•

• •

D0

D1

D2

D3 Fig. 3-24 1-to-4-Line Demultiplexer

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

3-31

TABLE 3-7 Truth Table of Half Adder Inputs

Outputs

X

Y

C

S

0 0 1 1

0 1 0 1

0 0 0 1

0 1 1 0

Table 3-7 Truth Table of Half Adder

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

3-32

X Y

• •

S

C Fig. 3-25 Logic Diagram of Half Adder

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

3-33

TABLE 3-8 Truth Table of Full Adder Inputs

Outputs

X

Y

Z

C

S

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0 0 0 1 0 1 1 1

0 1 1 0 1 0 0 1

Table 3-8 Truth Table of Full Adder

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

3-34

YZ 00 X 0 X 1

Y 01

11

1

10 1

1

YZ 00 X

01

11

0 X 1

1

Y

Z

10

1 1

1

1

Z

S = X YZ + XYZ + XY Z + XY Z =X Y Z

C = XY + XZ + YZ = XY + Z ( XY + XY ) = XY + Z ( X Y )

Fig. 3-26 Maps for Full Adder

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

3-35

Half adder X Y

Half adder

•

•

•

S

• C Z Fig. 3-27 Logic Diagram of Full Adder

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

3-36

B3

A3

FA

C4

S3

B2

C3

A2

FA

S2

B1

C2

A1

FA

B0

C1

S1

Fig. 3-28 4-Bit Ripple Carry Adder

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

A0

FA

S0

C0

3-37

•

•

S A3

B3

PFA

S3

G3

G

C

A2

B1

PFA

P3

C3

C4

S2

G2

A •

P

B2

B

A1

B0

PFA

P2

C2

S1

G1

PFA

P1

C1

•

•

A0

S0

G0

P0

• •

C0

•

C0

Ripple Carry (a) G3

P3

C3

G2

P2

C2

G1

P1

C1

G0

•

•

P0

•

• • •

•

• • •

•

•

• •

•

•

• •

•

•

G 0-3

•

• Carry Lookahead

P 0-3 (b)

Fig. 3-29 Development of a Carry Lookahead Adder © 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

•

3-38 A

B

•• ••

•• •• Binary adder

Borrow

Complement

Subtract/Add

Binary subtractor

Selective 2's complementer

0 1 S Quadruple 2-to-1 multiplexer Result

Fig. 3-30 Block Diagram of Binary Adder-Subtractor © 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

3-39

B3

A3

B2

A2

B1

•

FA

C4

S3

C3

FA

S2

A1

B0

•

C2

FA

•

C1

S1

Fig. 3-31 Adder-Subtractor Circuit

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

A0

FA

S0

•

S

C0

3-40

TABLE 3-9 Signed Binary Numbers

Decimal

Signed 2’s Complement

Signed 1’s Complement

Signed Magnitude

⫹7 ⫹6 ⫹5 ⫹4 ⫹3 ⫹2 ⫹1 ⫹0 ⫺0 ⫺1 ⫺2 ⫺3 ⫺4 ⫺5 ⫺6 ⫺7 ⫺8

0111 0110 0101 0100 0011 0010 0001 0000 — 1111 1110 1101 1100 1011 1010 1001 1000

0111 0110 0101 0100 0011 0010 0001 0000 1111 1110 1101 1100 1011 1010 1001 1000 —

0111 0110 0101 0100 0011 0010 0001 0000 1000 1001 1010 1011 1100 1101 1110 1111 —

Table 3-9 Signed Binary Numbers © 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

3-41

V C

C n–1

•

Cn n-bit Adder/Subtractor

Fig. 3-32 Overflow Detection for Addition and Subtraction

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

3-42

C3

B1

B0

A1

A0

A0B1

A0B0

A 1B 1

A 1B 0

C2

C1

C0

A0

A1

•

•

B1

HA

C3 C2 Fig. 3-33 A 2-Bit by 2-Bit Binary Multiplier © 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

B1

B0

B0

HA

C1

C0

3-43 •

A0

A1

•

•

B3

•

B2

B1

B3

•

B2

•

B1

B0

B0

0

Addend

Augend 4-bit adder

Carry output

A2

•

•

•

B3

B2

B1

B0

Addend

Augend 4-bit adder

Carry output

C6

Sum

Sum

C5

C4

C3

C2

C1

Fig. 3-34 A 4-Bit by 3-Bit Binary Multiplier © 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

C0

3-44 Addend

K

Augend

4-bit binary adder Z3 Z2 Z1 Z0

• Output carry C

• •

•

• • 0

•

4-bit binary adder S3 S2 S1 S0

BCD sum

Fig. 3-35 Block Diagram of BCD Adder © 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

Input carry

3-45 -- 2-to-4 Line Decoder: Structural VHDL Description -- (See Figure 3-14 for logic diagram) library ieee, lcdf_vhdl; use ieee.std_logic_1164.all, lcdf_vhdl.func_prims.all; entity decoder_2_to_4 is port(E_n, A0, A1: in std_logic; D0_n, D1_n, D2_n, D3_n: out std_logic); end decoder_2_to_4; architecture structural_1 of decoder_2_to_4 is component NOT1 port(in1: in std_logic; out1: out std_logic); end component; component NAND3 port(in1, in2, in3: in std_logic; out1: out std_logic); end component; signal E, A0_n, A1_n: std_logic; begin g0: NOT1 port map (in1 => A0, out1 => A0_n); g1: NOT1 port map (in1 => A1, out1 => A1_n); g2: NOT1 port map (in1 => E_n, out1 => E); g3: NAND3 port map (in1 => A0_n, in2 => A1_n, in3 => E, out1 => D0_n); g4: NAND3 port map (in1 => A0, in2 => A1_n, in3 => E, out1 => D1_n); g5: NAND3 port map (in1 => A0_n, in2 => A1, in3 => E, out1 => D2_n); g6: NAND3 port map (in1 => A0, in2 => A1, in3 => E, out1 => D3_n); end structural_1;

-- 1 -- 2 -- 3 -- 4 -- 5 -- 6 -- 7 -- 8 -- 9 -- 10 -- 11 -- 12 -- 13 -- 14 -- 15 -- 16 -- 17 -- 18 -- 19 -- 20 -- 21 -- 22 -- 23 -- 24 -- 25 -- 26 -- 27 -- 28 -- 29 -- 30 -- 31 -- 32

Fig. 3-36 Structural VHDL Description of a 2-to-4 Line Decoder

© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

3-46 -- 4-to-1 Line Multiplexer: Structural VHDL Description -- (See Figure 3-19 for logic diagram) library ieee, lcdf_vhdl; use ieee.std_logic_1164.all, lcdf_vhdl.func_prims.all; entity multiplexer_4_to_1_st is port(S: in std_logic_vector(0 to 1); D: in std_logic_vector(0 to 3); Y: out std_logic); end multiplexer_4_to_1_st; architecture structural_2 of multiplexer_4_to_1_st is component NOT1 port(in1: in std_logic; out1: out std_logic); end component; component AND3 port(in1, in2, in3: in std_logic; out1: out std_logic); end component; component OR4 port(in1, in2, in3, in4: in std_logic; out1: out std_logic); end component; signal S_n: std_logic_vector(0 to 1); signal N: std_logic_vector(0 to 3); begin g0: NOT1 port map (S(0), S_n(0)); g1: NOT1 port map (S(1), S_n(1)); g2: AND3 port map (S_n(1), S_n(0), D0), N(0)); g3: AND3 port map (S_n(1), S(0), D(1), N(1)); g4: AND3 port map (S(1), S_n(0), D(2), N(2)); g5: AND3 port map (S(1), S(0), D(3), N(3)); g6: OR4 port map (N(0), N(1), N(2), N(3), Y); end structural_2;

-- 1 -- 2 -- 3 -- 4 -- 5 -- 6 -- 7 -- 8 -- 9 -- 10 -- 11 -- 12 -- 13 -- 14 -- 15 -- 16 -- 17 -- 18 -- 19 -- 20 -- 21 -- 22 -- 23 -- 24 -- 25 -- 26 -- 27 -- 28 -- 29 -- 30 -- 31 -- 32 -- 33 -- 34

Fig. 3-37 Structural VHDL Description of a 4-to-1 Line Multiplexer © 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

3-47

-- 2-to-4 Line Decoder: Dataflow VHDL Description -- (See Figure 3-14 for logic diagram) Use library, use, and entity entries from 2_to_4_decoder_st; architecture dataflow_1 of decoder_2_to_4 is signal A0_n, A1_n: std_logic; begin A0_n