Fundamentals of Logic Design [7 ed.] 1133628478, 9781133628477
Updated with modern coverage, a streamlined presentation, and excellent companion software, this seventh edition of FUND
1,043 132 27MB
English Pages 710 Year 2014
Table of contents :
Cover Page
Title Page
Copyright Page
Dedication
Preface
Acknowledgments
How to Use This Book for Self-Study
About the Authors
Unit 1. Introduction Number Systems and Conversion
Unit 2. Boolean Algebra
Unit 3. Boolean Algebra (Continued)
Unit 4. Applications of Boolean Algebra Minterm and Maxterm Expansions
Unit 5. Karnaugh Maps
Unit 6. Quine-McCluskey Method
Unit 7. Multi-Level Gate Circuits NAND and NOR Gates
Unit 8. Combinational Circuit Design and Simulation Using Gates
Unit 9. Multiplexers, Decoders, and Programmable Logic Devices
Unit 10. Introduction to VHDL
Unit 11. Latches and Flip-Flops
Unit 12. Registers and Counters
Unit 13. Analysis of Clocked Sequential Circuits
Unit 14. Derivation of State Graphs and Tables
Unit 15. Reduction of State Tables State Assignment
Unit 16. Sequential Circuit Design
Unit 17. VHDL for Sequential Logic
Unit 18. Circuits for Arithmetic Operations
Unit 19. State Machine Design with SM Charts
Unit 20. VHDL for Digital System Design
Appendix A. MOS and CMOS Logic
Appendix B. VHDL Language Summary
Appendix C. Tips for Writing Synthesizable VHDL Code
Appendix D. Proofs of Theorems
References
Cover Page
Title Page
Copyright Page
Dedication
Preface
Acknowledgments
How to Use This Book for Self-Study
About the Authors
Unit 1. Introduction Number Systems and Conversion
Unit 2. Boolean Algebra
Unit 3. Boolean Algebra (Continued)
Unit 4. Applications of Boolean Algebra Minterm and Maxterm Expansions
Unit 5. Karnaugh Maps
Unit 6. Quine-McCluskey Method
Unit 7. Multi-Level Gate Circuits NAND and NOR Gates
Unit 8. Combinational Circuit Design and Simulation Using Gates
Unit 9. Multiplexers, Decoders, and Programmable Logic Devices
Unit 10. Introduction to VHDL
Unit 11. Latches and Flip-Flops
Unit 12. Registers and Counters
Unit 13. Analysis of Clocked Sequential Circuits
Unit 14. Derivation of State Graphs and Tables
Unit 15. Reduction of State Tables State Assignment
Unit 16. Sequential Circuit Design
Unit 17. VHDL for Sequential Logic
Unit 18. Circuits for Arithmetic Operations
Unit 19. State Machine Design with SM Charts
Unit 20. VHDL for Digital System Design
Appendix A. MOS and CMOS Logic
Appendix B. VHDL Language Summary
Appendix C. Tips for Writing Synthesizable VHDL Code
Appendix D. Proofs of Theorems
References
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- Author / Uploaded
- Charles H. Roth
- Larry L. Kinney
- Commentary
- This book was extracted from the Cengage mobile app; as such, it is paginated differently than the print edition. The file has not been modified.
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