Руководство пользователя Version 5.6а

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ModelSim

®

SE

Ver s i o n 5 . 6 :23/

я/02

T h e l d ’ s m o s t p o p u l a r HDL s m u l a t or T h e l d ’ s m o s t p o p u l a r HDL s m u l a t or T h e l d ’ s m o s t p o p u l a u l a t or я я я HDL T h e l d ’ s m o s t p o p u l a r HDL s m u l a t or

ModelSim /VHDL, ModelSim /VLOG, ModelSim /LNL, Model Technology Incorporated.

ModelSim / PLUS , Model Technology.

,

, Model Technology. ,

.

, .

,

,

. ModelSim -

Model Technology Incorporated. PostScript Adobe Systems Incorporated. UNIX AT&T . FLEXlm Globetrotter Software, Inc. IBM, , PC , AIX RISC System/6000 International Business Machines. Windows, Microsoft, MS-DOS Microsoft. OSF/Motif Open Software Foundation, . SPARC SPARCstation SPARC International. Sun Microsystems , Sun  ,SunOS OpenWindows Sun Microsystems. . Copyright (c) 1990 -2000, Model Technology Incorporated. . . Model Technology . Model Technology Incorporated 10450 SW Nimbus Avenue / Bldg. R-B Portland OR 97223-4347 USA

phone: 503-641-1340 fax: 503-526-5410 e-mail: [email protected], [email protected] home page: http://www.model.com support page: http://www.model.com/support

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1 - Introduction( ) ............................................. 28 ModelSim graphic interface ............................................. 28 ( ModelSim’s)........................ 28 Standards supported......................................................................... 29 ( )...................................................... 29 Assumptions( )...................................................... 29 Sections in this document ( ) ............. 30 Command reference( ) ................................. 32 What is an "HDL item"( - " HDL ") ............ 32 Text conventions( ).................................. 33 Where to find our documentation ................................................... 33 ( ) ................................................. 33 Download a free PDF reader with Search ...................................... 34 ( PDF ) ............................................................................................................ 34 Technical support and updates( )................................................................................. 34

2 - Projects ( ) .................................................... 36 Introduction( ).................................................... 37 What are project? ( ?) ....................... 37 What are the benefits of projects?( ?)......................................................................... 37 How do projects differ from pre-5.5 versions?( 5.5?)37 Project conversion between versions( ) .............................................. 38 Getting started with projects( ) ............................................................................................. 38 Step 1 - Create a new project( 1)............................................................................ 39 Step 2 -Add items to the project ( 2) ......................................................... 39 Step 3 — Compile the files ( 3— ) .............................................................................. 40

Step 4 — Simulate a design ( 4— Other basic project operations (

The Project tab (

)........... 41 )41

) ................................................. 41

Sorting the list ( Project tab context menu (

)........................................................ 42 ) ........... 42

Changing compile order(

) ..... 43

Auto-generating compile order ( Grouping files (

-

)44 ).................................................... 44

Creating a Simulation Configuration ( ) ............................................................................... 44 Organizing projects with folders ( ) ........................................................................................... 45 Adding a folder(

) ............................................................ 45

Setting compiler options ( )46 Accessing projects from the command line ( ).......................................................................... 47

3 - Design Libraries ( )_.................................................. 48 Design library contents ( )............................................................................. 49 Design unit information( ) ........................................................................... 49 Design library types ( )....... 50 Working with design libraries ( )............................................................................. 50 Creating a library ( )................... 50 Managing library contents( ) ...................................................................... 51 Assigning a logical name to a design library ( )............................................................................. 52 Moving a library( )............. 54 Specifying the resource libraries( ) ...................................................... 54 Verilog resource libraries ( Verilog)............................................................................... 54

4

VHDL resource libraries ( VHDL )....................... 54 Predefined libraries( ) ............................ 55 Alternate IEEE libraries supplied ................................................................. 55 ( ) ...................................... 55 Rebuilding supplied libraries ( ) ....................................................................................................... 56 Regenerating your design libraries................................................................ 56 ( ) .................................... 56 Maintaining 32-bit and 64-bit versions in the same library ........................ 57 ( 3264) ..................................................................................................... 57

Importing FPGA libraries(

FPGA

)57

4 - VHDL Simulation( VHDL ) ........... 59 Compiling and simulating with the GUI ( GUI ) .............. 60 ModelSim variables( ModelSim)............... 60 Compiling VHDL designs( VHDL )........................................................................... 61 Creating a design library( )............................................................................. 61 Invoking the VHDL compiler( VHDL )..................................................................... 61 Dependency checking( ) ........... 61 Range and index checking ( ) ............................................................................. 61 Simulating VHDL designs ( VHDL )........................................................................... 62 Simulator resolution limit( )........................ 62 Simulating with an elaboration file ( )...................................... 63 Overview ( ).............................................. 63 Elaboration file flow ( ) ............................................................................... 63 Creating an elaboration file ( ).......................................... 64

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Loading an elaboration file ( )...... 64 Modifying stimulus ( ).............................................. 64 Using with the PLI or FLI( PLI FLI)...................... 65 Syntax( ) ......................................................................................... 65

Using the TextIO package(

TextIO ) ..... 65

Syntax for file declaration ( )............ 66 Using STD_INPUT and STD_OUTPUT within ModelSim ........................ 66 ( STD_INPUT STD_OUTPUT ModelSim)................ 66

TextIO implementation issues(

TextIO)67

Writing strings and aggregates( ) ................... 67 Reading and writing hexadecimal numbers ................................................. 68 ( ) ......................................... 68 Dangling pointers( ) ...................................................... 68 The ENDLINE function( ENDLINE) .......................................... 69 The ENDFILE function( ENDFILE) ........................................... 69 Using alternative input/output files( – )................................................................................ 69 Providing stimulus ( ) ........ 69

Obtaining the VITAL specification and source code..................... 70 ( VITAL ).......... 70 VITAL packages( VITAL)................................................ 70 ModelSim VITAL compliance( VITAL ModelSim)71 VITAL compliance checking( VITAL compliance warnings(

VITAL).............. 71 VITAL). 71

Compiling and Simulating with accelerated VITAL packages..... 73 ( VITAL) .............................................................................................. 73 Util package ( Util)................................................................. 74 get_resolution() ................................................................................................ 74 init_signal_driver() .......................................................................................... 74 init_signal_spy() ............................................................................................... 75 signal_force() .................................................................................................... 75 signal_release()................................................................................................. 75 to_real()............................................................................................................. 75 to_time()............................................................................................................ 76

Foreign language interface(

).......... 77

5 - Verilog Simulation( Verilog )......... 78 Compilation( ).............................................. 80 Incremental compilation( ) ..... 81 Library usage( ) ................ 84 Verilog-XL compatible compiler arguments 6

(Verilog-XL ) 85 Verilog-XL ‘uselib compiler directive ( VerilogXL ‘ uselib).................................................. 86 Simulation( ).......................................... 88 Invoking the simulator( ) ............................................................... 88 Simulation resolution limit( ) ....................................... 88 Event ordering in Verilog designs( Verilog).......................................... 90 Negative timing check limits .......... ( ) ................................... 93 Verilog-XL compatible simulator arguments (Verilog-XL ) 96 Compiling for faster performance( ) ..................................... 96 Compiling with "-fast"( " - fast ") ............................................................................ 97 Compiling with +opt ( +opt ).................. 98 Compiling mixed designs with –fast ( –fast) ...................................... 98 Compiling gate-level designs with –fast ( –fast)......................... 99 Referencing the optimized design ( )........................................ 99 Enabling design object visibility with the +acc option....... ( +acc ).................................................................. 103 Using pre-compiled libraries( ). 105 Event order and optimized designs ( ) ........................... 105

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Timing checks in optimized designs ( )................................................................... 105

Simulating with an elaboration file( ).................................................... 106 Overview( )............................................................. 106 Elaboration file flow ...................................................................................... 106 ( )................................................. 106 Creating an elaboration file ( ) .. 107 Loading an elaboration file( ).... 107 Modifying stimulus ( ) ............................................... 107 Using with the PLI or FLI( PLI FLI).................... 107 Syntax( ) ....................................................................................... 108

Cell Libraries( SDF timing annotation( Delay modes(

System Tasks(

) ........................................... 108 SDF )..................... 108 ) .............................................................. 108

) ............................................... 110

IEEE Std 1364 system tasks ( Std 1364 )........ 110 Verilog-XL compatible system tasks ........................................................... 112 (Verilog-XL ) ........................................ 112 $init_signal_driver system task( $init_signal_driver )114 $init_signal_spy system task( $init_signal_spy) ........ 114 $signal_force system task( $signal_force) .................. 114 $signal_release system task( $signal_release) ............ 115

Compiler Directives(

) ....................... 115

IEEE Std 1364 compiler directives( Std 1364 ) ................................................................................................. 116 Verilog-XL compatible compiler directives ................................................ 116 ( Verilog-XL ) ........................... 116

Verilog PLI/VPI .............................................................................. 118 Registering PLI applications( PLI)118 Registering VPI applications ( VPI) ............................................ 121 Compiling and linking PLI/VPI applications ......................................... 122 ( PLI/VPI) .. 122 Compiling and linking PLI/VPI C++ applications( PLI/VPI C++) .................................................. 125 Using 64-bit ModelSim with 32-bit PLI/VPI Applications( 64ModelSim 32PLI/VPI) .... 128 Specifying the PLI/VPI file to load .............................................................. 128 ( PLI/VPI ) .......................................... 128 PLI example( PLI)........................................................................... 129 VPI example ( VPI ) ........................................................................ 129 The PLI callback reason argument( PLI) 130 The sizetf callback function( sizetf)............................... 132 8

PLI object handles( PLI) ........................................... 132 Third party PLI applications( PLI)133 Support for VHDL objects( VHDL)............... 134 IEEE Std 1364 ACC routines ....................................................................... 135 ( Std 1364 ACC ) ................................................... 135 IEEE Std 1364 TF routines ( Std 1364 TF ) ....... 135 Verilog-XL compatible routines................................................................... 136 ( Verilog-XL).......................................... 136 64-bit support in the PLI ( 64PLI).................... 136 PLI/VPI tracing( PLI/VPI ) ................................................. 137 Debugging PLI/VPI application code( PLI/VPI) ........................................................................................................ 138

6 - Mixed VHDL and Verilog Designs........................... 139 ( VHDL Verilog).................... 139 Separate compilers, common design libraries( , ) .............................. 140 Access limitations in mixed-language designs( )...................................................................... 140 Simulator resolution limit( )............................................................................................ 140

Mapping data types(

) .................. 140

VHDL generics ( VHDL) ................................................................ 141 Verilog parameters( Verilog ) .................................................. 141 VHDL and Verilog port( VHDL Verilog ) ................................... 141 Verilog states( Verilog ) .............................................................. 142

VHDL instantiation of Verilog design units ................................. 144 (VHDL Verilog) ...................... 144 Verilog instantiation criteria( Verilog) .............. 144 Component declaration( ) ................................. 144 vgencomp component declaration................................................................ 146 ( vgencomp) ....................................................... 146

Verilog instantiation of VHDL design units ................................. 147 (Verilog VHDL) ...................... 147 VHDL instantiation criteria( SDF annotation( SDF

VHDL).................. 147 ) ............................................................. 148

7 – WLF files (datasets) and virtuals............................. 149 (WLF ( ) ).... 149 WLF files (datasets)( WLF ( ))149 Saving a simulation to a WLF file( WLF).................................... 150 Opening datasets( ) ........ 150 9

Viewing dataset structure ( )............................................................................ 150 Managing multiple datasets( ) ............................................................ 151 Saving at intervals with Dataset Snapshot( ) ................................................................................. 153

Virtual Objects (User-defined buses, and more).......................... 154 ( ( , . .)) .................................................................................. 154 Virtual signals( Virtual functions( Virtual regions( Virtual types(

) ............................................. 154 ) ........................................ 156 )............................................... 156 ) ...................................................... 157

Dataset, WLF file, and virtual commands .................................... 157 ( , WLF ) .. 157

8 - Graphic Interface( ) ...... 159 Window overview( Window) .............. 160 Common window features( )161 Quick access toolbars( ) ............................................................. 162 Drag and Drop( ) .......................... 162 Command history( ) ................ 163 Automatic window updating( ) .................................................. 163 Finding names, searching for values, and locating cursors ........................................................................................... 163 ( , , ).............................................. 163 Sorting HDL items( HDL ) .... 164 Multiple window copies( )164 Saving window layout( )164 Context menus( ) ........................... 164 Menu tear off( ) ................................... 164 Customizing menus and buttons( ) ............................................................................ 164

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Tree window hierarchical view( )............................................................................................. 165

Main window(

)....................................................... 166

Workspace( ) ..................................................................... 167 Transcript( ) .................................................................................. 167 The Main window menu bar( ) ................ 168 The Main window toolbar( )174 The Main window status bar( ) ....... 176 Mouse and keyboard shortcuts ( ).................................................................................................. 177

Dataflow window ( Dataflow)............................................................................. 179 Adding items to the window ( ).................. 179 Links to other windows( ) ................................. 180 Dataflow window menu bar ( Dataflow) ................... 180 The Dataflow window toolbar( Dataflow). 183 Exploring the connectivity of your design( ) ......................................................................................................... 185 Zooming and panning ( ) ........ 186 Tracing events (causality)( ( ))187 Tracing the source of an unknown (X)( (X)) .............................................................................................. 188 Finding items by name in the Dataflow window( Dataflow) ............................................................................... 188 Printing and saving the display( ) .. 189 Configuring page setup( )... 190 Symbol mapping( )................................................ 190 Configuring window options( ) . 192

List window(

)............................................................ 192

HDL items you can view( HDL)...... 193 Adding HDL items to the List window( HDL List ) ................................................................................................................ 193 The List window menu bar ( )..................... 194 Editing and formatting HDL items in the List window( HDL List) ..................................... 196 Combining items in the List window( List)197 Setting List window display properties( )................................................................................................. 198 Finding items by name in the List window( List) ........................................................................................ 200 Searching for item values in the List window............................................. 200 ( ) ............................................ 200 Setting time markers in the List window .................................................... 201 ( ) ..................................... 201 11

Saving List window data to a file ................................................................. 202 ( )........................................... 202 List window keyboard shortcuts .................................................................. 202 ( List)................................................................... 202

Process window(

) ................................................ 203

The Process window menu bar(

Signals window(

Process) ................ 204

) .................................................. 206

The Signals window menu bar( Signals) ................ 207 Selecting HDL item types to view( HDL, )..................................................................................................... 209 Forcing signal and net values( ) ........................................................................................................... 210 Adding HDL items to the Wave and List windows or a WLF file............ 211 ( HDL Wave List WLF)... 211 Finding HDL items in the Signals window ( HDL )...................................................................... 212 Setting signal breakpoints( )... 213 Defining clock signals( ). 213

Source window(

) .................................................. 214

The Source window menu bar ( Source) ................... 214 The Source window toolbar( Source) 217 Setting file-line breakpoints( ) ................................................................................................. 219 Checking HDL item values and descriptions.............................................. 219 ( HDL )................................. 219 Finding and replacing in the Source window( Source)............................................................................................... 220 Setting tab stops in the Source window and Main window Transcript ... 220 ( Source Main) ................................................................................................. 220

Structure window(

)......................................... 222

The Structure window menu bar( ).... 223 Structure window context menu( Structure) .. 224 Finding items in the Structure window( ).......................................................................................... 225

Variables window(

) ...................................... 225

The Variables window menu bar( ) . 226 Finding HDL items in the Variables window( HDL Variables ).......................................................................................... 228

Wave window( Pathname pane( Values pane( Waveform pane( Cursor panes(

) .................................................... 228 ) ....................................................... 228 ) .................................................................. 229 ).................................. 229 )................................................................... 229 12

HDL items you can view( HDL )....... 230 Adding HDL items in the Wave window( HDL Wave)..................................................................................................... 231 The Wave window menu bar( ) ............. 232 The Wave window toolbar( Wave).... 236 Using Dividers( ) ....................................... 238 Splitting Wave window panes( Wave) .......... 238 Combining items in the Wave window ........................................................ 239 ( Wave) ................................................... 239 Editing and formatting HDL items in the Wave window.......................... 240 ( HDL Wave). 240 Setting Wave window display properties .................................................... 241 ( Wave) ...................................... 241 Sorting a group of HDL items( HDL)242 Setting signal breakpoints( ).... 242 Finding items by name or value in the Wave window( Wave) ................................. 243 Searching for item values in the Wave window.......................................... 243 ( Wave) ................................................ 243 Using time cursors in the Wave window( Wave) ................................................................................ 244 Finding a cursor( )................................................. 245 Making cursor measurements( ) .............. 245 Zooming - changing the waveform display range( ) .............................................................................. 246 Saving zoom range and scroll position with bookmarks ........................... 247 ( )........................................................ 247 Wave window mouse and keyboard shortcuts ........................................... 248 ( Wave)......................... 248 Printing and saving waveforms( ) ...................................................................................................... 249

Compiling with the graphic interface ( ) ........................................................ 253 Locating source errors during compilation( ) .................................................................. 253 Setting default compile options( ) .................................................................................. 253

Simulating with the graphic interface( ) ........................................................ 257 Design tab( VHDL tab( Verilog tab (

) ...................................................................... 257 VHDL) ....................................................................... 258 Verilog)..................................................................... 260 13

Libraries tab( ) ......................................................... 261 SDF tab( SDF) ............................................................................... 261 Options tab( )...................................................................... 262 Setting default simulation options( ) ............................................... 263

Creating and managing breakpoints( ) .................................................................. 265 Signal breakpoints( File-line breakpoints( Breakpoints dialog(

-

).................................... 265 ) ...................... 266 ) ...................................... 266

Miscellaneous tools and add-ons( )...................................................... 268 The GUI Expression Builder ........................................................................ 269 ( GUI) ................................................................ 269 Language templates( )...................................................... 270 The Button Adder ( )................................................. 271 The Macro Helper ( ) ................................................... 272 The Tcl Debugger ( Tcl )............................................................. 273

Graphic interface commands( ) .................................................................................... 277

9 - Performance Analyzer ( ) ............................ 279 Introducing Performance Analysis................................ 280 ( )280 A Statistical Sampling Profiler (

) .................................................................... 281 Getting Started ( ) .............................................. 281 Interpreting the data( )........ 282 Viewing Performance Analyzer Results ( ) ..... 282 Interpreting the Name Field( )................................................................................. 283 Interpreting the Under(%) and In(%) Fields( Under(%) In(%)) ............... 284

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Differences in the Ranked and Hierarchical Views ................................... 284 ( )....... 284

Reporting results ( ) .............................. 285 Performance Analyzer preference variables ................................ 285 ( ).................................................................... 285 Performance Analyzer commands( )................................................................... 286

10 - Code Coverage( Enabling Code Coverage ( The coverage_summary window (

) ........................... 287 _

) ......... 288 ).... 288

Summary information( ) ........................................ 288 Misses tab( )................................................................. 289 Excluded tab( )........................................................ 289 The coverage_summary window menu bar( coverage_summary )...................................................................................... 290

Coverage data in the Source window( Source ) ............................................................................................ 290 Excluding lines and files(

)......................... 291

Merging coverage report files( )....................................................................................... 291 Exclusion filter files( ) ................ 292 Syntax( ) ....................................................................................... 292 Arguments( ) ............................................................................. 292 Example( ) ......................................................................................... 292 Default filter file( ) ................. 293

Code Coverage preference variables( ) ...................................................... 293 Code Coverage commands ( )............ 293

11 - Waveform Comparison( ) ..... 294 Introduction( )................................................. 295 Two modes of comparison( ) 296 Comparing hierarchical and flattened designs( ) ......................... 296 Graphic interface to Waveform Comparison( Waveform Comparison).......................... 297

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Opening dataset comparison( ). 297 Adding signals, regions and/or clocks( , )................................................................................ 298 Setting compare options( ) ............... 300 Wave window display ( Wave) ..................................... 301 Printing compare differences( )................. 303 Compare objects in the List window( List)303

Waveform Comparison preference variables ( Waveform Comparison).. 304 Waveform Comparison commands ( Waveform Comparison).............................................. 304

12 - Signal Spy( )..................... 305 Introduction( ).................................................. 306 Designed for testbenches( testbenches)...................................................................... 306 init_signal_driver ............................................................ 306 Call only once( )................................ 307 Syntax( )......................................................... 307 Returns( )............................................................ 307 Arguments( )............................................... 307 Related procedures( ).............. 308 Limitations( )........................................... 308 Example( )........................................................... 308 init_signal_spy ................................................................. 309 Call only once( )................................ 309 Syntax( )......................................................... 309 Returns( )............................................................ 309 Arguments( )................................................ 309 Related functions( )..................... 310 Limitations( )............................................ 310 Example( )........................................................... 310 signal_force ...................................................................... 310 Syntax( )......................................................... 310 Returns( )............................................................ 311 Arguments( )................................................ 311

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Related functions( )................................................... 311 Limitations( ) .......................................................................... 311 Example( ) ......................................................................................... 311

signal_release................................................................................... 312 Syntax( ) ....................................................................................... 312 Returns( ) .......................................................................................... 312 Arguments( ) .............................................................................. 312 Related functions( )................................................... 313 Limitations( ) .......................................................................... 313 Example( ) ......................................................................................... 313

$init_signal_driver .......................................................................... 313 Call only once( ) .............................................................. 313 Syntax( ) ....................................................................................... 314 Returns( ) .......................................................................................... 314 Arguments( ) .............................................................................. 314 Related procedures( )............................................ 314 Limitations( ) .......................................................................... 314 Example( ) ......................................................................................... 314

$init_signal_spy ............................................................................... 315 Call only once( ) .............................................................. 315 Syntax( ) ....................................................................................... 315 Returns( ) .......................................................................................... 315 Arguments( ) .............................................................................. 315 Related functions( )................................................... 316 Limitations( ) .......................................................................... 316 Example( ) ......................................................................................... 316

$signal_force.................................................................................... 316 Syntax( ) ....................................................................................... 317 Returns( ) .......................................................................................... 317 Arguments( ) .............................................................................. 317 Related functions( )................................................... 317 Limitations( ) .......................................................................... 317 Example( ) ......................................................................................... 317

$signal_release................................................................................. 318 Syntax( ) ....................................................................................... 318 Returns( ) .......................................................................................... 318 Arguments( ) .............................................................................. 318 Related functions( )................................................... 318 Limitations( ) .......................................................................... 318 Example( ) ......................................................................................... 319

13 - Standard Delay Format (SDF) Timing Annotation320 ( (SDF) ) ....................................... 320 17

Specifying SDF files for simulation( SDF ) ....................................................... 321 Instance specification ( )............................................................................ 321 SDF specification with the GUI( SDF GUI) ................. 321 Errors and warnings( )................................ 322

VHDL VITAL SDF......................................................................... 322 SDF to VHDL generic matching( SDF VHDL) ......................................................................................................................... 322 Resolving errors( ) .................................................... 323

Verilog SDF ..................................................................................... 323 The $sdf_annotate system task( $sdf_annotate) ........ 324 SDF to Verilog construct matching( SDF Verilog) ........................................................................................................... 325 Optional edge specifications( )327 Optional conditions( ) ....................................... 329 Rounded timing values( )............................................................................................ 329

SDF for Mixed VHDL and Verilog Designs( SDF VHDL Verilog) ........................................................... 330 Interconnect delays( ) ............................... 330 Troubleshooting( ) ...................... 330 Specifying the wrong instance( ) .... 330 Mistaking a component or module name for an instance label ( )....................... 331 Forgetting to specify the instance( ) 331

14 - Value Change Dump (VCD) Files ( (VCD)) ........................................ 333 ModelSim VCD commands and VCD tasks ( ModelSim VCD VCD )_............. 334 Creating a VCD file( VCD) .............. 336 Flow for four-state VCD file( ё VCD)................................................. 336 Flow for extended VCD file( VCD) ......................................... 336 Case sensitivity( )........ 336 Resimulating a design from a VCD file ( VCD )....... 337

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Example 1 — Verilog counter( Example 2 — VHDL adder( Example 3 — Mixed-HDL design(

1-

ё

23-

Verilog ) .................. 337 VHDL)...................... 337 HDL )338

A VCD file from source to output(VCD ) .................................................................................... 338 VHDL source code( VHDL)............................................ 338 VCD simulator commands( VCD )339 VCD output( VCD)............................................................................ 339

Capturing port driver data ............................................................ 340 ( ) ........................................ 340 Supported TSSI states ( TSSI)................. 340 Strength values( ) ........................................................ 341 Port identifier code ( ) ................................. 341 Example VCD output from vcd dumpports............................................... 341 ( VCD vcd dumpports) ................................................ 341

15 - Logic Modeling SmartModels ( )........................................................................... 341 VHDL SmartModel interface (VHDL

)..................... 342

Creating foreign architectures with sm_entity ........................................... 343 ( sm_entity)......................................... 343 Vector ports( ) ................................................................ 347 Command channel( ) ....................................................... 347 SmartModel Windows( Windows) ............... 348 Memory arrays ( ) ......................................................... 350

Verilog SmartModel interface(Verilog )....................................................... 350 Linking the LMTV interface to the simulator( LMTV ) ............................................................ 350

16 - Logic Modeling Hardware Models (

)351

VHDL Hardware Model interface ( VHDL) ................................ 352 Creating foreign architectures with hm_entity ( hm_entity) ........................................ 353 Vector ports( ) ...................................................................... 356 Hardware model commands( ) ............... 357

17- Tcl and macros (DO files) ( Tcl (DO files)) ................................ 357 19

Tcl features within ModelSim ( Tcl ModelSim)....... 358 Tcl References( Tcl)......................................................... 359 Tcl tutorial(

Tcl ) ................................................ 359

Tcl commands ( Tcl command syntax(

Tcl) ...................................................... 359 Tcl)......................... 360

if command syntax ( if) ............................................ 362 set command syntax( set )........................................ 363 Command substitution ( ) ............................................... 364 Command separator( ) ............................................. 364 Multiple-line commands( ).............................. 364 Evaluation order ( ) ........................................................ 365 Tcl relational expression evaluation( Tcl) ............................................................................................ 365 Variable substitution( )............................................... 365 System commands ( ) ................................................... 366

List processing ( ) .......................................... 366 ModelSim Tcl commands ( ModelSim Tcl) ................. 367 ModelSim Tcl time commands ( ModelSim Tcl) ................................................................................. 368 Conversions( Relations( Arithmetic (

Tcl examples( Example 1( Example 2(

Macros (DO files)(

) .................................................................. 368 ) ................................................................................. 369 )............................................................................ 369

Tcl)......................................................... 370 1) .................................................................................. 370 2) .................................................................................. 372

(DO

) )..................... 374

Creating DO files( DO ) .................................................... 374 Using Parameters with DO files( DO )........................................................................................................ 375 Making macro parameters optional( )........................................................................ 375 Useful commands for handling breakpoints and errors( )....................... 376 Error action in DO files( DO ) .............. 377 Using the Tcl source command with DO files( source Tcl DO ) ......................................................... 377

A - ModelSim Variables( ModelSim ) .... 378 Variable settings report( )...................................................................... 379

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Personal preferences( ) .................. 379 Returning to the original ModelSim defaults ............................... 380 ( ModelSim )....................................................................................... 380 Environment variables( ) .............................. 380 ModelSim Environment Variables( ModelSim) ...... 381 Creating environment variables in Windows( Windows)......................................................................................... 382 Referencing environment variables within ModelSim( ModelSim) ................................................................ 383 Removing temp files (VSOUT)( (VSOUT))384

Preference variables located in INI files ( , INI

) ............................ 384

[Library] library path variables( [ ] )................................................................................................... 384 [vcom] VHDL compiler control variables................................................... 385 ( [vcom] VHDL )....................... 385 [vlog] Verilog compiler control variables( Verilog ) ................................................................................... 386 [vsim] simulator control variables ( ) ........................................................................... 387 [lmc] Logic Modeling variables( [lmc] )........................................................................................... 391 Setting variables in INI files ( INI ). 391 Reading variable values from the INI file( INI )...................................................................................................... 392 Commonly used INI variables ( INI)392

Preference variables located in TCL files ..................................... 395 ( , TCL )............................................................................................ 395 User-defined variables ( More preferences( ё

) 396 ).......................................................... 396

Variable precedence( )...................... 396 Simulator state variables( ) ............................................................................. 397 Referencing simulator state variables( )........................................................ 397 Special considerations for $now( $now)397

B - ModelSim shortcuts (

ModelSim) ............. 398

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Wave window mouse and keyboard shortcuts( Wave) .................... 399 List window keyboard shortcuts( List).................................................................. 400 Command shortcuts( ).......................... 400 Command history shortcuts( )........................................................................................... 400 Mouse and keyboard shortcuts in the Main ................................. 401 and Source windows( Main Source) .......................................... 401 Right mouse button(

) ........................................... 403

C - ModelSim messages(

ModelSim) ........ 403

ModelSim message system(

ModelSim).... 404

Message format( Getting more information(

) ........................................................ 404 ).......... 405

Suppressing warning messages( ) .................................................. 405 Suppressing VCOM warning messages( VCOM)................................................... 405 Suppressing VLOG warning messages( VLOG).................................................... 406 Suppressing VSIM warning messages( VSIM) ..................................................... 406

Exit codes( Miscellaneous messages(

)...................................................... 406 )..................... 408

Lock message( Tcl Initialization error 2( Too few port connections(

).................................................... 408 Tcl) ...................... 408 ) ....................... 409

2

D - Using the FLEXlm License Manager ( FLEXlm)........................ 410 Starting the license server daemon( daemon ) ........................................................................ 411 Locating the license file( ) .............................................................................. 411 Controlling the license file search( ) ............................................................ 411

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Manual start( )........................................................................ 412 Automatic start at boot time( ) .................................................................................. 413 What to do if another application uses FLEXlm( FLEXlm) ............................................ 413

Format of the license file( Feature names(

) ...... 413 ) .................................................................. 414

Format of the daemon options file( daemon)............................................................................................ 414 License administration tools( ) .................................................. 415 lmstat............................................................................................................... 416 lmdown............................................................................................................ 416 lmremove ........................................................................................................ 417 lmreread.......................................................................................................... 417 Administration tools for Windows ( Windows) .......................................................... 418

E - System initialization(

)418

Files accessed during startup( ) ........................................................................................... 418 Environment variables accessed during startup( ) .......................................... 419 Initialization sequence( ) .................... 420

F - Tips and Techniques( )............. 422 How to use checkpoint/restore( / )...................... 423 The difference between checkpoint/restore and restarting ( / ) ............................................................. 425 Using macros with restart and checkpoint/restore ( checkpoint/restore.)......................................................... 425 Running command-line and batch-mode simulations( ) ............... 425 Command-line mode( ) .... 426 Batch mode( ) ................................... 427

23

Source code security and -nodebug( –nodebug) ..................................... 427 Saving and viewing waveforms in batch mode ( ) ......................................................... 428 Setting up libraries for group use ( ) ............................................................. 429 Using a DO file to test for assertions( DO )............................ 429 Sampling signals at a clock change( )................ 429 Converting signal values to strings( )................... 430 Converting an integer into a bit_vector ( bit_vector) ............ 430 Maintaining 32-bit and 64-bit modules in the same library ( 3264)...................... 431 Hiding library cell signals when saving a waveform file( ).............. 431 Examining constants in a package( )........................................................ 432 Bus contention checking( )432 Bus float checking( ).... 433 Design stability checking( ) .......................................................................... 433 Toggle checking( ) ............... 434 Detecting infinite zero-delay loops................................. 434 ( ) ...................................................................... 434

24

Referencing source files with location maps................................. 435 ( )435 Using location mapping( )435 Pathname syntax( ) .............................................. 436 How location mapping works( ) .............................................................................................. 436 Mapping with Tcl variables( Tcl).......... 436

Improve performance by locking memory on HP-UX 10.2 ........ 437 ( HPUX 10.2) ........................................................................................... 437 Configuring memory locking( )437 Limitations( ) .......................................................................... 437 System parameter setting( ) ............. 438

Improve performance of large simulations on Sun/Solaris( Sun/Solaris) ........................................................... 438 Enabling shared memory( )........................................................................................................... 438 How it works( )................................................................. 439

Performance affected by scheduled events being cancelled( ё ) .................................................................. 439 Modeling memory in VHDL( VHDL) .......................................................................................................... 440 Configuring a List trigger with Expression Builder ................... 444 ( ) .................................................................................... 444 Delta delays( ).................................................... 445

G - ModelSim Tk widgets( ModelSim Tk) .................................................................. 447 Widgets and the ModelSim GUI( GUI ModelSim) ............................................................ 448 MTI tree widget( MTI) ....... 449 Index arguments( ) ................. 449

25

Tree commands( Tree options( Additional Wave tree options(

).................................................. 450 ).......................................................... 455 Wave). 457

Wave tree commands( Wave) ............................. 458 Wave tree zoom commands( Wave) .................................................................................. 460 Wave tree cursor commands( Wave)461 Tree widget default bindings( ) .............................................................. 462 MTI vlist widget( MTI vlist )........................... 463 Vlist widget commands ( Vlist) ...... 463 Vlist widget options( Vlist) .................. 468 Miscellaneous commands( ) ..................... 470

H - What’s new in ModelSim( ModelSim)471 New features( ) ................................... 471 Command and variable changes( ) ................................................................... 472 Documentation changes ( )473 GUI changes in version 5.6( 5.6)................................ 474 Main window changes( ) .. 475 Menu bar( )............................................... 475 File menu( File)..................................................... 475 Design menu( ) ....................................... 476 View menu( ) .............................. 476 Project menu( )....................................... 477 Run menu ( ).................................. 477 Compare menu( )............................... 478 Macro menu( ) ........................................... 478 Options menu( )......................................... 478 Dataflow window changes ( Dataflow)479 List window changes( List) ............... 479 Edit menu( )............................. 479 Markers menu( )............................... 480

26

Prop menu(

) ......................................................................... 480

Signals window changes( Edit menu ( View menu ( Context menu (

).......................................................... 481 ) ........................................................... 481 ) ........................................................... 481

Source window changes( File menu( Edit menu( Object menu ( Options menu(

Signals) .................... 481

Source) ..................... 481

).............................................................................. 481 )........................................................... 481 )................................................................. 481 ) ....................................................................... 482

Structure window changes( Variables window changes( Edit menu ( View menu(

Wave window changes(

Structure)............ 482 Variables)............ 482 ).......................................................... 482 ) ............................................................ 482

Wave) ......................... 482

Menu bar and toolbar ( )... 482 File menu ( )............................................................................. 482 Edit menu ( ).......................................................... 483 Cursor menu ( ).................................................................... 483 Zoom menu ( )............................................... 484 Compare menu ( )........................................................... 484 Bookmark menu ( ) ........................................................... 484

License Agreement(

) ....... 533

27

1 - Introduction(

) ModelSim

- " HDL

"

ModelSim SE/EE WINDOWS98/Me/ NT 2000/XP. ModelSim -

,

5.6

UNIX, Microsoft

README .

.

ModelSim graphic interface ( ModelSim’s) , ModelSim .

,

,

: • SPARCstation OpenWindows, OSF/Motif,

CDE

• IBM RISC System/6000 OSF/Motif • Hewlett-Packard HP9000 Series 700 HPVUE, OSF/Motif, • Linux (Red Hat v. 6/7) KDE • Microsoft Windows NT

CDE

GNOME

WINDOWS 98/ME/ NT /2000/XP ModelSim

Tcl/TK,

,

. , 28

(

."Preference variables located in INI and MPF files" ( " INI MPF ") , "Graphic interface commands"( " ") ) , , . . " Tcl ModelSim " Tcl. ModelSim,

Graphic Interface(

.,

,

8-

).

Standards supported (

)

ModelSim VHDL , IEEE 1076-1987 1076-1993 VHDL, 1164-1993 Standard Multivalue Logic System for VHDL Interoperability, ( VHDL ), 1076.2-1996 Standard VHDL Mathematical Packages standards. ( VHDL). ModelSim VHDL IEEE 1076-1987

,

1076-1993.

ModelSim Verilog IEEE Std 1364-1995 Standard Hardware Description Language Based on the Verilog Hardware Description Language ( , Verilog ). Verilog Verilog LRM 2.0 . PLI (Programming Language Interface) VCD (Value Change Dump) ModelSim PE

2.2b,

SE.

, SDF 1.0 3.0, VITAL VITAL’ 95 – IEEE 1076.4-1995 , VITAL2000 – IEEE 1076.4-2000.

Assumptions( ,

) .

: OpenWindows, OSF/Motif, CDE, HP VUE, KDE, GNOME, Microsoft Windows 98/Me/NT/2000/XP.. , VHDL Verilog. ModelSim , HDL, , . HDLs, - www.model.com . , , ModelSim

29

ModelSim. ModelSim. web

ModelSim

ModelSim : www.model.com. ,

Start

Here for ModelSim, website: www.model.com.

ModelSim. Start Here

Sections in this document (

) ё

, : 2"

" ModelSim, .

3HDL, ,

,

ModelSim,

,

,

.

4 - VHDL -

VHDL

ModelSim.

5 - Verilog -

Verilog

6-

VHDL

ModelSim.

Verilog (SKS- single-kernel simulation) ModelSim/Plus

VHDL /

, Verilog.

, 7 - WLF

HDLs. (

) virtuals – ModelSim.

8, ModelSim .

ModelSim. ,

930

,

ModelSim ,

. 10 – . , . 11 , . 12 – , Verilog , ,

VHDL ,

,

VHDL

.

13 -

(SDF- Standard Delay Format)

ModelSim SDF ( . .

SDF,

14 -

VITAL SDF

) Verilog

(VCD - Value Change Dump) Verilog VCD ModelSim.

Model Technology’s VCD ,

VHDL. 15 -

SmartModels(

)

SmartModel Library SmartModel Windows ModelSim. 16 – ModelSim. 17 - Tcl

(DO files) Tcl (tool command language ModelSim.

),

A-

ModelSim ,

,

ModelSim.

31

B–

ModelSim .

ModelSim C-C

ModelSim ModelSim.

D-

FLEXlm FLEXlm Model Technology's ModelSim.

E,

ModelSim.

FModelSim . G–

ModelSim Tk Tk , ModelSim

H-

ModelSim

ModelSim 5.6 .

Command reference( ModelSim. "CR" (

) ModelSim Command Reference. Command Reference –

,"

" (CR-27)).

What is an "HDL item"(

- " HDL

VHDL

ModelSim Verilog, HDL ”

, Verilog

Verilog, “HDL” . :

,

VHDL

, ,

,

), ,

,

VHDL ,“

, (

")

,

, , ,

,

32

Text conventions(

)

,

:

italic text ,

ё

ё ,

bold text

, ,

,

ё

,

,

monospace type

(>)

, : File > Quit UNIX ,

-

Windows

UPPER CASE (

, DO, , WLF, INI, MPF, PDF,

ModelSim . .)

Where to find our documentation ( ) ModelSim www.model.com/support/documentation.asp

Start Here SE/EE (

ModelSim

ModelSim )

ModelSim SE Quick Guide ( )

ModelSim SE ModelSim SE

:

PDF

PDF

PDF, HTML PDF, HTML

Main window > Help > SE Documentation; Support page web site:: www.model.com ModelSim Main window > Help > SE Documentation; Support page web site:: www.model.com Main window > Help > SE Documentation, Support page web site:: www.model.com Main window > Help > SE Documentation 33

ModelSim SE

Std_DevelopersKit User’s Manual( _ -

PDF, HTML PDF, HTML PDF

Main window > Help > SE Documentation Main window > Help > SE Documentation www.model.com/support/pdf/sdk_um.pdf

Mentor Graphics QuickHDL. ) Command Help

ASCII

Error message help

ASCII

Tcl Man Pages ( Tcl)

HTML

Ч

[

] Main,

verror

HTML

Main window > Help > Tcl Man Pages, contents.htm \modeltech\docs\tcl_help_html www.model.com/resources/techdocs.asp

HTML

www.model.com/resources/faqs.asp

ASCII

Main window > Help > Technotes, \modeltech\docs\technotes

Download a free PDF reader with Search ( PDF Model Technology’s PDF Adobe http://www.adobe.com. Reader with Search ;

) Adobe Acrobat Reader. ModelSim. , Acrobat , .

Technical support and updates( ) Web

Model Technology

,

,

.

www.model.com/support/default.asp , www.model.com/contact_us.asp .

.

www.model.com/products/release.asp

34

. www.model.com/support/register_news_list.asp

35

2 - Projects (

-

)

? ? -5.5?

1— 2— 3— 4—

-

ModelSim. ModelSim.

Introduction(

)

What are project? (

?) HDL

. "

,

,

",

. mpf, .

, ,

. :

•

HDL

•

,

README

• •

What are the benefits of projects?(

?) .

•

ModelSim;

•

;

• ;

, HDL

• ;

,

•

;

•

"

";

,

, •

.ini, ModelSim

; ,

.ini

How do projects differ from pre-5.5 versions?( 5.5?) 5.5. : • •

. ; .

37

• .

; ,

, . •

(

,

,

)

.mpf. ,

:

,

5.5

. ,

,

5.5. 15

,

, .

Project conversion between versions( ) .

,

(

5.6,

,

5.5), ,

.

. , .

< ,

.mpf.bak .

Getting started with projects(

) .

1— .mp

.

2— HDL, ,

,

. . 3— ModelSim . 4— , .

38

Step 1 - Create a new project(

1-

File > New > Project ( Create Project.

)

Main),

.

: • . • ,

.

.mpf

• .

"

" . "work."

,

, Project Location. OK,

Project Add Items to the Project .

Step 2 -Add items to the project (

2-

)

Add Items to the Project ( :

)

• VHDL, Verilog, Tcl, .

,

Source.

• . •

.

ё

, .

" •

" ё

. "

.

"

.

39

VHDL, Verilog, Tcl,

Create New File Source. selecting File > Add to Project > New File ( (2Windows; 3UNIX) Project > New file.

, Main) Project

Add to

:

Create Project File • . • .

VHDL, Verilog, TCL,

.

• ,

. ,

. "

OK, Project

Source

ё

, Main.

Add Existing File (

) ,

File (

"

.

)

,

UNIX)

Project

File > Add to Project > Existing (2Windows; 3Add to Project > Existing File. :

Add file to Project • ,

.

. • ." (

" , .v –

, Verilog).

• ,

.

,

. "

"

.

•

/ . OK,

( )

ё ( )

Project

Main.

Step 3 — Compile the files (

3—

) 40

.

Project , , Compile > Compile All (

, Project

Main)

Compile > Compile All. , ,

Library

"+",

.

Step 4 — Simulate a design (

4—

)

, Simulate.

,

.

. ,

Wave .

ModelSim.

Other basic project operations (

)

ModelSim ,

. ,

File > Close > Project ( Library Structure ( .

File > Delete > Project (

The Project tab (

File > Open > Project (

Main). " sim "

Main).

Project, )

Main).

) 41

Project

. .

-

. ,

. VHDL

Verilog.

;X

, ;

. –

,

Windows

ё , Compile All. -

,

. , . Customize Project View. Project

Customize View.

Sorting the list (

) .

,

;

,

. , (

)

(

).

Project tab context menu ( ,

ё

, UNIX)

) Project

, Windows; 3-

( 2-

-

. :

• ModelSim. • ( ).

,

, -

Compile Selected,

.

• ,

.

• ,

.

• . "

"

. 42

• . • . • ( ) .

"

"

. • . • . • . "

"

.

• . "

"

.

• . . • Project

.

• View/change ( ).

Changing compile order(

) , ModelSim . : 1)

; 2)

. ,

1

Compile > Compile Order ( Project.

:

Main)

43

,

2 .

-

, .

Auto-generating compile order ( Auto Generate

-

)

Compile Order( , ;

)"

" . -

, . ,

( ) .

Grouping files (

) Compile Order, , , .

. Verilog Verilog. , 1

:

,

.

Group

2

,

,

Ungroup.

Creating a Simulation Configuration ( ) ( .

,

)

,

, ,

(generics),

SDF

. .

, ( ,

, top_config). Project, . 44

, 1

:

File > Add to Project > Simulation Conf ( Project .

2 3

Main)

Simulation Configuration Name. ,

( ).

( )

4 5

Add. , .

"

". Project.

OK, ,

.

Organizing projects with folders ( ) ,

,

.

"

"

. –

.

,

.

Adding a folder(

) ,

File > Add to Project > Folder.

, Project .

,

OK.

, ,

.

,

.

, Properties

(

, Properties

). 45

Setting compiler options ( VHDL

Verilog

(vcom

) vlog,

)

, . ,

Compile > Compile Options (

).

. , Project

( ) Properties.

,

. VHDL Verilog,

VHDL

VHDL

Verilog

, General,

, , General ,

Verilog General.

General

. .

, .

,

,

,

General

:

• Do Not Compile( ,

) .

• Compile to library ( ,

) ; .

• Place in Folder(

) ,

( ). "

.

• File Properties (

) (

,

"

,

,

, VHDL

, Project.

).

Verilog

"

". ,

:

•

, (

)

" " " OK, ModelSim

.

, "

. •

VHDL VHDL

Verilog,

Verilog, . 46

Accessing projects from the command line ( ) ,

ModelSim GUI ( ).

, ,

. , MODELSIM (< Project_Root_Dir > / < Project_Name > .mpf). project (CR-192) , .

.

47

3 - Design Libraries (

)_

Verylog VHDL

32... FPGA VHDL

64-

,

, ;

. Verilog .

,

, ModelSim ,

Design library contents ( -

)

,

. , ,

;

Verilog

VHDL , UDPs (user defined primitives -

). : • ,

,

,

,

UDPs. . • . .

, .

Design unit information( , •

) :

,

• •

ё

49

Design library types (

) :

-

.

,

. ,

.

; )

(

,

. ModelSim; (

work, ).

, ,

. work -

.

,

.

Working with design libraries (

) VHDL

ModelSim, , ё

,

Verilog.

; .

Creating a library ( (

) "

" ), ModelSim .

, ,

. ModelSim. ModelSim

UNIX / DOS,

vlib (CR-

285): vlib ModelSim, > New > Library (

File

Main).

Create a New Library • Create a new library and a logical mapping to it (

: ё)

50

Library Name. ,

.

, . • Create a map to an existing library (

) Library Name,

Browse ,

Library Maps to • Library Name (

. ) .

• Library Physical Name (

) . ModelSim

.

• library Maps to(

) . reate a map to an existing

Browse , library . OK, ModelSim ,

_info

"[Library] library path variables([ .

,

ModelSim. [Library-

modelsim.ini ]

,

:

.

_info

)"

-

; GUI ModelSim,

, vlib (CR-282). ,

UNIX

].

Windows.

Managing library contents(

) ,

,

,

, . Library (

,

, (

Library (

Windows — 2- , UNIX — 3-

,

,

) , ( M),

(E),

.

. )

,

Type.

, )

Library .

:

51

• Simulate .

- vsim (CR-296).

• Edit Source, "

Edit Library Mapping (

, ")

• Refresh ( ) - vcom (CR-250)

.

-refresh.

• Recompile .

-

vcom (CR-250). • Optimize Verilog. (CR-286)

- vlog "

+opt.

+opt "

. • Delete .

- vdel (CR-

256). ,

,

.

,

, .

ё

. ,

,

Delete.

, .

• View Customize ,

,

,

.

• View Update . • New

ё

.

• Properties ( .

,

,

Assigning a logical name to a design library ( VHDL

,

,

. .)

)

, ModelSim. 52

, ModelSim (

),

,

,

, . GUI,

,

,

. GUI , Edit

.. .

,

ё

,

: ё

• Library Mapping Name (

)

. • Library Pathname (

) .

Library mapping from the command line ( )

, ; ё

:

vmap UNIX/DOS ModelSim. vmap (CR-295) modelsim.ini , modelsim.ini, [Library]

modelsim.ini. ,

.

: =

,

modelsim.ini :

[Library] work = /usr/rick/design my_asic = /usr/rick/design work ,

my_asic .

53

Unix UNIX

,

: ln -s vmap (CR-295 )

, .

,

: vmap

: •

modelsim.ini.

•

,

modelsim.ini modelsim.ini,

, . ,

,

.

Moving a library(

) . ,

, .

Specifying the resource libraries( ) Verilog resource libraries ( ModelSim .

Verilog) Verilog

vlog (CR-286), . UDPs ( , ,

VHDL) .

"

".

VHDL resource libraries (

VHDL )

VHDL,

library VHDL, , .

library library .

, . 54

,

library

,

ё

vcom (CR-250)

;

. ,

work. ,

vcom- work .

Predefined libraries(

) VHDL.

std

standard

.

textio,

Э 1987

.

ANSI/IEEE Std 1076-1993. use VHDL , . .

VHDL, Std 1076TextIO ".

,"

, —

use

,

:

LIBRARY std, work; USE std.standard.all ,

,

, /

.all ,

USE std, .

. standard VHDL,

, USE. - work, .

library ,

, USE ,

, , ,

, . : Verilog

-L

-Lf

Verilog vlog (CR-286).

Alternate IEEE libraries supplied (

VHDL.

) :

• ieeepure , std_logic_1164

(

ModelSim).

• ieee Synopsys , Model Technology, math_complex, math_real, numeric_bit, numeric_std, std_logic_1164, std_logic_misc, std_logic_textio, std_logic_arith, std_logic_signed, std_logic_unsigned, vital_primitives, vital_timing. , , modelsim.ini. 55

modelsim.ini

ieee.

Rebuilding supplied libraries (

) ,

modeltech. vhdl_src; Windows (rebldlibs.do). DO ModelSim

, :

do rebldlibs.do (

,

-

,

modeltech

). UNIX (rebuild_libs.csh rebuild_libs.sh). rebuild_libs ,

, modeltech.

,

: 1993, vcom (CR-250)

,

-93.

Regenerating your design libraries (

)

ModelSim, . ,

README, ,

. Refresh

Library ( " 250)

" ),

-refresh

vcom (CR-

vlog (CR-286). ,

vcom VHDL Verilog.

,

-refresh, vlog

,

;

-refresh, -work ,

. ,

,

Verilog

,

mylib,

VHDL

:

vcom -work mylib -refresh vlog -work mylib -refresh -refresh -

, .

,

,

, ModelSim (4.6 .

).

,

, (

Verilog)

. 56

,

: 1993, vcom (CR-250)

,

-93

.

Maintaining 32-bit and 64-bit versions in the same library ( 3264) 32,

ModelSim, . (64-

32-

"

64-

),

"

.

32-

:

ModelSim:

vcom file1.vhd vcom file2.vhd ,

64-

ModelSim:

vcom -refresh , , ModelSim

. ,

"

Importing FPGA libraries(

".

FPGA

)

ModelSim FPGA. . : FPGA

,

,

.

FPGA ,

ModelSim.

FPGA

,

,

File > Import > Library (

Main).

.

57

58

4 - VHDL Simulation( VHDL

)

VHDL . VHDL

VHDL

PLI

FLI.

TextIO STD_INPUT

STD_OUTPUT ModelSim.

TextIO

ENDLINE ENDFILE . (

)

vsim VITAL

VITAL VITAL ModelSim VITAL VITAL VITAL

get_resolution() 59

init_signal_driver() init_signal_spy() signal_force() signal_release() to_real() to_time()

VHDL; VITAL (VHDL Initiative

TextIO ModelSim; ModelSim Towards ASIC Libraries VHDL ASIC) ModelSim’s.

ASIC;

TextIO 1987 Э Std 1076-1993;

VHDL, VHDL

Э Std 1076-

.

Compiling and simulating with the GUI ( GUI ) . ModelSim GUI,

.:

• • •

ModelSim variables(

ModelSim) ,

, ,

, .

-

, . ModelSim ModelSim.

GUI ModelSim. ,

60

Compiling VHDL designs(

VHDL

Creating a design library(

)

) ,

, vlib (CR-285),

.

.

: vlib work ,

work.. work. work -

:

work.

, _info. UNIX, MS WINDOWS, DOS vlib (CR-285).

."

,

" .

Invoking the VHDL compiler(

VHDL

)

VHDL

ModelSim vcom (CR-250) VHDL

.

, .

VHDL,

,

. , -1993

VHDL. VHDL , 1076 –1987

,

1076 -1987

vcom (CR-250)

, -93 vcom (CR-250), 1076 - 1993. modelsim.ini ( . " ).

. ; , , INI"

Dependency checking( ,

1076

,

,

) , . vcom (CR-250) . ,

,

,

, , ,

,

.

Range and index checking (

) ,

,

, 61

.

,

,

,

. ,

.

(

NoRangeCheck INI

) vcom (CR-250). NoIndexCheck . "

, ,

" work -

:

, _info.

, UNIX, MS Windows,

,

modelsim.ini,

work. , vlib (CR-

DOS -

285).

Simulating VHDL designs (

VHDL

) vsim (CR-

, 296). Windows/DOS

UNIX (

")

"

"

Simulate( )" .

VHDL

vsim (CR-296) , , . vsim (CR-296)

.

, ,

/

structure :

my_asic

vsim my_asic structure

Simulator resolution limit( ) 64, . modelsim.ini. report (CR-

Resolution , 200)

simulator state.

Overriding the resolution (

ModelSim, Resolution

)

,

-t Simulate. : 1x, 10x

100x

Simulator ,

,

,

,

,

. , vsim -t 10ps topmod ,

10

: .

–t , , 62

. 0

,

4

.

Choosing the resolution (

) , . , ,

.

Simulating with an elaboration file ( ) Overview (

)

ModelSim

, .

, . ,

: -

.

,

, 5.6,

ModelSim (

.

),

. ,

"

".

.

,

PLI

FLI.

? . "

,

,"

, ,

.

,

-

,

,

, ,

,

SDF.

., , . ModelSim, ,

ё

ModelSim ,

Elaboration file flow (

.

)

63

, . , -sdf instance=)

1 ( ,. Verilog, ,

$sdf_annotate. ё

$sdf_annotate . ,

2

vsim.

(

)

,

(

Modifying stimulus). ,

3 (

).

Creating an elaboration file (

) vsim (CR-296) ,

-elab .

ЕК

ModelSim.

Loading an elaboration file (

) vsim (CR-296) ,

- load_elab < filename > : .

, OS,

vsim (

,

, ).

Modifying stimulus (

) . .

•

, .

; ,

,

,

.

• , stdin/stdout. • . vcdread

-filemap_elab. , VCD vcdstim

, . ,

VCD

,

,

,

. • Verilog, mc_scan_plusargs (). +args +args

+args, ё

PLI

, ,

, .

64

Using with the PLI or FLI(

PLI

PLI

FLI)

, , tf.

sizetf, misctf -load_elab,

,

checktf,

PLI

. tf

,

load_elab – FLI

Verilog HDL

,

PLI

-

. , .

FLI,

,

(-elab)

. FLI ,

(-load_elab) , , ,

-load_elab. "

/ FLI

Syntax(

FLI " .

)

vsim (CR-296) compress_elab, -filemap_elab, -load_elab. : . vsim ( , GUI

-elab, , , OS,

Using the TextIO package(

, ).

TextIO ) TextIO,

VHDL: USE std.textio.all; ,

TextIO:

USE std.textio.all; ENTITY simple_textio IS END; ARCHITECTURE simple_behavior OF simple_textio IS BEGIN PROCESS VARIABLE i: INTEGER:= 42; VARIABLE LLL: LINE; BEGIN WRITE (LLL, i); WRITELINE (OUTPUT, LLL); WAIT; END PROCESS; END simple_behavior;

65

Syntax for file declaration (

)

VHDL ’ 87

:

file identifier : subtype_indication is [mode] file_logical_name ; "file_logical_name"

.

VHDL ’ 93

:

file identifier_list: subtype_indication [file_open_information] ; "file_open_kind_expression" : [open file_open_kind_expression]

file_logical_name file_logical_name;

(VHDL ’ 87): file filename : TEXT is in "usr/rick/myfile"; ,

,

,

,

ё.

,

, , RETURNs(

, , )

.

, ,

modelsim.ini. , ConcurrentFileLimit.

DelayFileOpen

.

.

B - ModelSim Variables .

Using STD_INPUT and STD_OUTPUT within ModelSim ( STD_INPUT STD_OUTPUT ModelSim) VHDL ’ 87

TextIO

:

file input: TEXT is in "STD_INPUT"; file output: TEXT is out "STD_OUTPUT"; VHDL ’ 93

TextIO

:

file input: TEXT open read_mode is "STD_INPUT"; file output: TEXT open write_mode is "STD_OUTPUT"; STD_INPUT

,

, ,

,

STD_OUTPUT

. 66

ModelSim, .

STD_INPUT ,

STD_OUTPUT

.

TextIO implementation issues(

TextIO)

Writing strings and aggregates(

)

VHDL

, STRING

, VHDL

WRITE ,

BIT_VECTOR.

:

WRITE (L, "hello"); : ERROR: Subprogram "WRITE" is ambiguous. TextIO, BIT_VECTOR .

WRITE

STRING :

procedure WRITE(L: inout LINE; VALUE: in BIT_VECTOR; JUSTIFIED: in SIDE:= RIGHT; FIELD: in WIDTH := 0); procedure WRITE(L: inout LINE; VALUE: in STRING; JUSTIFIED: in SIDE:= RIGHT; FIELD: in WIDTH := 0); , , ,

" hello " , . :

WRITE (L, "010101"); 67

, , .

, "010101" :

•

,

,

:

WRITE (L, string’("hello")); •

,

,

:

WRITE_STRING (L, " hello "); WRITE_STRING WRITE,

,

STRING WRITE,

. WRITE_STRING Io_utils, //modeltech/examples/io_utils.vhd. .

Reading and writing hexadecimal numbers (

) VHDL. VHDL

(ISAC-VASG) .

,

TextIO

, ModelSim Io_utils, /modeltech/examples/io_utils.vhd. ,

io_utils, VHDL:

use std.textio.all; use work.io_utils.all;

Dangling pointers(

) TextIO,

WRITELINE

(

),

. VHDL:

VHDL (

L1

L2

):

READLINE (infile, L1); -- Read and allocate buffer L2 := L1; -- Copy pointers WRITELINE (outfile, L1); -- Deallocate buffer

VHDL (

L1

L2

): 68

READLINE (infile, L1); L2 := new string’(L1.all); WRITELINE (outfile, L1);

-- Read and allocate buffer -- Copy contents -- Deallocate buffer

The ENDLINE function(

ENDLINE) Э

ENDLINE, Э Std 1076-1987 VHDL. ,

,

VHDL VHDL ,

.

ISAC-VASG ,

ENDLINE

TextIO. : (L = NULL) OR (L’LENGTH = 0)

The ENDFILE function(

ENDFILE)

VHDL

, :

ENDFILE

Э Std 1076-1987

Э Std 1076-1993,

-- function ENDFILE (L: in TEXT) return BOOLEAN; , ENDFILE ,

,

TextIO. , .

Using alternative input/output files( – ) TextIO,

.

,

TEXT. VHDL ’ 87

:

file myinput : TEXT is in "pathname.dat"; VHDL ’ 93

:

file myinput : TEXT open read_mode is "pathname.dat"; ("myinput" READLINE

)

WRITELINE.

Providing stimulus ( ,

) ,

, ,

, . 69

VHDL :

.

ModelSim

< install_dir>/modeltech/examples/stimulus.vhd

Obtaining the VITAL specification and source code ( VITAL

)

VITAL ASIC 1076.4

VITAL ASIC :

445 Hoes Lane Piscataway, NJ 08855-1331 Tel: (732) 981-0060 Fax: (732) 981-1721 : http://www.ieee.org VITAL VITAL /modeltech/ Vhdl_src/vital2.2b, /vital95

VITAL packages(

/ /vital2000.

VITAL) VITAL 2000

-

ieee

VITAL 1995

,

vital95. use

.

VHDL , LIBRARY vital95; USE vital95.all , ModelSim vsim (CR-296) VITAL v2.2b, /modeltech/vital2.2b.

VITAL 1995.

VITAL2000. -vital2.2b, ,

:

,

, vital

70

ModelSim VITAL compliance(

VITAL ModelSim)

VITAL, SDF , VITAL, VITAL Model Development Specification.( ). ModelSim IEEE 1076.4 VITAL ASIC Modeling Specification. , ModelSim VITAL_TIMING VITAL_Primitives VITAL_MEMORY. IEEE 1076.4 VITAL ASIC Modeling Specification (VITAL 1995 and 2000).

VITAL compliance checking(

VITAL) VITAL;

, VITAL. vcom (CR-250)

VITAL 2000

VITAL_LEVEL0 , VITAL_LEVEL0 VITAL_LEVEL1. VITAL 2.2b, , vcom (CR-250) VITAL 1995 , , .

, -novitalcheck. VITAL 2000 ,

VITAL compliance warnings(

VITAL)

LRM

( ,

1-

VITAL);

. • (

)

(1076.4

• PreviousDataIn VITALStateTable (1076.4 6.4.3.2.2) • (

q_w, )(1076.4

VITAL 6.4.3)

DataIn PreviousDataIn VITALStateTable 6.4.3.2.2) DataIn

, 71

LRM.

,

,

VITAL 3.0 LRM –

, . -

, . ,

CheckEnabled VITAL

,

. -

vcom (CR-250). , nowarn vcom -nowarn 6. 6 , , ,WARNING [6]. [vcom] VHDL compiler control variables( modelsim.ini VHDL ).

vcom -

[vcom] Show_VitalChecksWarnings = 0

72

Compiling and Simulating with accelerated VITAL packages ( VITAL) ё ,

vcom (CR-250) ieee .

VITAL

,

: • VITAL Level-0 optimization " 0,

".

–

-1,

-1.

• VITAL Level-1 optimization -1 VITAL 3.0, VITAL.

-

.

VITAL vcom (CR-250)

VITAL

: -O0 | -O4 -O0 ( ,

,

).

.

, , . -O4 (

).

-debugVA , , ModelSim

,

VITAL VITAL

, -1.

VITAL VITAL.

73

Util package ( util,

Util)

ModelSim VHDL. modeltech

5.5

, modelsim_lib, modelsim.ini.

, VHDL

:

library modelsim_lib; use modelsim_lib.util.all;

get_resolution() get_resolution () .

, 1e-15.

1 Syntax resval := get_resolution(); Returns(

)

resval ,

Arguments(

)

Related functions( to_real() to_time()

Example(

)

) 10ps, :

resval := get_resolution(); ,

resval

1e-11.

init_signal_driver() Init_signal_driver () VHDL

VHDL

Verilog

Verilog. VHDL (

,

testbench). init_signal_driver

12 – . 74

init_signal_spy() Init_signal_spy () VHDL , , , testbench). init_signal_ spy

(

VHDL

/

Verilog

Verilog. VHDL 12– .

signal_force() signal_force ()

,

Verilog ,

/

VHDL ,

. VHDL (

force (CR-154 ) . signal_ force 12–

, testbench). signal_force ,

.

signal_release() signal_release () , , VHDL Verilog , , VHDL ( , testbench). signal_release noforce (CR-171). signal_release 12– .

.

to_real() to_real () . .

,

1900 fs ps,

2.0 (

, 2 ps).

Syntax realval := to_real(timeval); Returns(

)

realval

Arguments (

-

)

timeval

75

Related functions (

)

get_resolution() to_time () Example (

) ps, :

realval := to_real(12.99 ns); ,

timeval

12990.0 (ns)

, , :

get_resolution () realval := 1e+9 * (to_real(12.99 ns)) * get_resolution(); ,

(fs),

: realval : = 1e+15 * (to_real(12.99 ns)) * get_resolution();

to_time() to _time () . . ,

5.9

,

ps ,

6 ps.

Syntax timeval := to_time(realval); Returns(

)

timeval -

Arguments (

)

realval

Related functions (

)

get_resolution() to_real () Example (

) ps, :

timeval := to_time(72.49); 76

,

timeval

72 ps.

Foreign language interface(

) (FLI)

C, Model Technology’s HDL, vsim. ,

HDL VHDL ,

) FLI ModelSim’s

, , (

. ModelSim FLI. ModelSim ModelSim.

77

5 - Verilog Simulation( Verilog

)

Verilog-XL Verilog-XL ‘

uselib.

. . Verilog Verilog-XL

-fast +opt -fast -fast +acc .

-

PLI

FLI.

SDF

Std 1364 Verilog-XL $init_signal_driver $init_signal_spy $signal_force $signal_release

Std 1364-1995

. 78

Verilog-XL Verilog PLI/VPI PLI VPI PLI/VPI ++ PLI/VPI 64-

ModelSim 32-

PLI/VPI PLI/VPI PLI VPI PLI . sizetf PLI PLI VHDL Std 1364 ACC Std 1364 TF Verilog-XL 64PLI/VPI

. . PLI

, Verilog. ModelSim Verilog

Verilog ModelSim IEEE Std 1364, .

Verilog,

, ModelSim Verilog

Std 1364-1995, :

•

(SDF -Standard Delay Format ) Verilog ASIC

•

FPGA

VCD ( Value Change Dump -

•

)

PLI/VPI

•

,

• •

VHDL

Verilog

(

SDF) • •

, ,

ModelSim VHDL Verilog-XL Std 1364

ModelSim Verilog:

79

• Verilog (VPI - Verilog Procedural Interface) ( . / < install_dir > /modeltech/docs/technotes/Verilog_VPI.note ) • Verilog 2001 (see //modeltech/docs/technotes/vlog_2000.note ) . GUI ModelSim

:

• • •

Compilation(

) Verilog, Verilog

,

.

Verilog . . 2 - Design Libraries (

).

ModelSim Verilog , vlog, ,

Verilog ,

,

.

, UDPs

.

,

. -work. , :

,

,

Contents top.v: module top; initial $display("Hello world"); endmodule : % vlib work : % vlog top.v - - Compiling module top Top level modules: top (

): 80

% vdir MODULE top : % vsim -c top # Loading work.top VSIM 1> run -all # Hello world VSIM 2> quit

,

, ,

-c. run –all

, , .

,

. "transcript"

,

(log) .

Incremental compilation(

)

, ModelSim Verilog

,

,

,

.

Verilog, , (

, ;

, . " Compiling for faster performance( )" . ,

, ,

UDP . , .

,

:

,

, ,

,

. , : Contents of top.v: module top; or2(n1, a, b); and2(n2, n1, c); endmodule

Contents of and2.v: module and2(y, a, b); output y; 81

input a, b; and(y, a, b); endmodule

Contents of or2.v: module or2(y, a, b); output y; input a, b; or(y, a, b); endmodule (

,

): % vlog top.v -- Compiling module top Top level modules: top % vlog and2.v -- Compiling module and2 Top level modules: and2 % vlog or2.v -- Compiling module or2 Top level modules: or2 ,

, ,

"

"

,

.

,

, . .

, . , % vlog top.v -- Compiling -- Compiling -- Compiling

and2.v module module module

or2.v top and2 or2

Top level modules: top , ,

.

, (

). 82

, .

,

-incr, ,

. ,

,

.

:

,

% vlog -incr -- Compiling -- Compiling -- Compiling

top.v and2.v or2.v module top module and2 module or2

Top level modules: top ,

,

"or2":

% vlog -incr top.v and2.v or2.v -- Skipping module top -- Skipping module and2 -- Compiling module or2 Top level modules: top ,

" top "

"and2",

"Or2". , .

, ;

, . ,

: , (

) ,

.

,

, ModelSim

.

83

Library usage(

)

UDPs

Verilog

.

, . , ,

, .

-

,

ASIC :

% vlib work % vlib asiclib % vlog -work asiclib and2.v or2.v -- Compiling module and2 -- Compiling module or2 Top level modules: and2 or2 % vlog top.v -- Compiling module top Top level modules: Top ,

–work asiclib, asiclib , work. , ,

. work, .

.

Verilog

•

:

ё

,

-Lf

. • •

, ,

ё

"

Verilog-XL -L ,

uselib " .

. • •

work. , . ,

—

,

work UDP, ,

work ,

, . , 84

-

.

, .

-L work

,

. ,

, "modA" "libA" "libB". , "modA" "modB" "cellA" "libA" "libB". , " -L libA - LlibB " "modB" "libA" "cellA".

" Top " "modB" , "cellA", , ,

"cellA"

" -L work -L libA -L libB ".

Verilog-XL compatible compiler arguments (Verilog-XL

)

,

Verilog-XL, vlog (CR-286 )

ModelSim. . +define+[=] +delay_mode_distributed +delay_mode_path +delay_mode_unit +delay_mode_zero -f +incdir+ +mindelays +maxdelays +nowarn +typdelays -u

, , Verilog-XL.

vlog (CR-286)

. ,

, ModelSim

,

. ModelSim

, . . , ,

.

UDPs, , .

85

, . . -v -y +libext+ +librescan +nolibcell -R []

Verilog-XL ‘uselib compiler directive ( Verilog- XL ‘ uselib) ‘ uselib – -v, -y, +libext. , , compile_uselibs (

)

, .

‘ uselib , vlog (CR-286).

-

‘ uselib: ‘ uselib ... : dir= | file= | libext= | lib= : dir=-y file=-v libext=+libext+ , ‘uselib dir=/h/vendorA libext=.v : -y /h/vendorA +libext +.v Verilog,

‘ uselib

. ‘ uselib

, ,

‘ uselib. ,

,

, :

‘uselib dir=/h/vendorA file=.v NAND2 u1(n1, n2, n3); 86

‘uselib dir=/h/vendorB file=.v NAND2 u2(n4, n5, n6); NAND2

vendorA

vendorB. -compile_uselibs ModelSim (CR-286) ,

5.5

,

-compile_uselibs ‘ uselib.

, , modelsim.ini this is still the default behavior when -compile_uselibs is not used. Э ( compile_uselibs И .

. -

),

-compile_uselibs, ModelSim , ,

ё : • , -compile_uselibs =./mydir • , " ") • mti_uselibs, ModelSim

:

, ,

-compile_uselibs. MTI_USELIB_DIR (

5.5,

, ModelSim Verilog.

uselib ,

, compile_uselibs – . www.model.com/products/documentation/pre55_uselib.pdf pre-5.5. ‘uselib is persisten (‘ uselib

. vlog -compile_uselibs dut.v srtr.v dut.v dut.v, , ,

dut.v,

,

‘ uselib ,

,

,

‘ -

)

, ,

vlog ,

.

,

uselib. ‘ uselib ‘ uselib . ‘ uselib dut.v,

:

srtr.v . -

, "

srtr ,

"

‘ uselib.

87

Simulation(

) Verilog

ModelSim

VHDL

, . , Verilog

.

Invoking the simulator(

)

Verilog

, . (

).

, "testbench"

" globals",

: vsim testbench globals ,

, UDPs

, .

UDPs

work. . –L

, "

-Lf

, UDPs vsim (

"

). ,

run , ,

.

,

Verilog. , run 100 ns).

$finish ( quit ,

, run –all ,

.

Simulation resolution limit( ) 64,

.

,

‘ timescale ‘ timescale:

. ‘ timescale 1 ns / 100 ps

, ,

ns

-

. 100 ps.

timescale 88

, timescale timescale

. .

,

,

:

vsim vsim mod2 mod1, 10 ps. timescale,

2 10 ps. 1

, ( 2,

/mod1/set 1.55 ns , 1 ns 20 ps . , , 15.5 ps

, 1.55

1

2 ModelSim :

, /mod2/set

Wave,

timescale).

, 20 ps.

** Warning: (vsim-3010) [TSCALE] - Module ’mod1’ has a ‘timescale directive in effect, but previous modules do not.( ’mod1‘ ‘timescale , .) vsim vsim mod1 mod2, , ModelSim : ** Warning: (vsim-3009) [TSCALE] - Module ’mod2’ does not have a ‘timescale directive in effect, but previous modules do. ( : (vsim-3009) [TSCALE] ’mod2‘ timescale , .) . ‘ timescale, ,

modelsim.ini. (

Resolution 1 ns

.) timescale

,

timescale.

timescale

, ,

vlog (CR-286). timescales. timescale .

timescale ( ModelSim)

89

, Simulate. sec.

-t ps, ns, us, ms,

: 1x, 10x

100x fs,

10 ps: vsim -t 10ps top ,

. timescale

-t , , .

,

4 ps

0 ps.

, . , ,

.

Event ordering in Verilog designs( Verilog) ( ).

ModelSim , " Delta Verilog

" ,

,

.

,

, Event queues( 5

,

.

) Std 1364-1995 LRM, ,

, .

, :

• • • • •

-

-

LRM

,

- 1) ;

2) 3)

; ;; 4) ;; 5) -

, . ,

, . 90

,

.

,

:

1 always@(q) p = q; 2 always @(q) p2 = not q; 3 always @(p or p2) clk = p and p2; 4 always @(posedge clk) : q = 0, p = 0, p2=1 . #,

, (old->new) new

#

,

1:

2:

1

2

,

. 2, clk clk.

’

.

.

,

1, clk

.

;

,

-

‘

/

-

,

, .

-

.

, ,

, :

• • • -

, .(

-

.)

-

. ,

,

. 91

, .(

,

.)

.

-

,

-

. gen1: always @(master) clk1 = master; gen2: always @(clk1) clk2 = clk1; f1 : always @(posedge clk1) begin q1 run -all VSIM 2> quit ,

,

,

. , .

Compiling with +opt (

+opt )

+opt

-fast, (

Makefile,

,

,

). ,

-fast, +opt. ,

,

+opt –

-fast. ,

+opt,

; +opt . ,

–L

-Lf,

. , .

vlog (CR-286)

- fast, +acc, .

,

+opt. PLI.

Compiling mixed designs with –fast ( –fast) Verilog . VHDL

, , VHDL

Verilog -fast, Verilog,

-fast .

98

Compiling gate-level designs with –fast ( –fast) netlist , - fast. : • forcecode

- fast

-forcecode.

, • •

-

. -fast.

testbench ,

. testbench

, . .

,

,

, testbench -fast , ModelSim vlog , . +nocheck

. . 5.5b,

vlog (CR-286). write cell_report (CR-320) , . write cell_report

vlog (CR-286),

-debugCellOpt , ,

. " (cell) "

-

.

,

Module: top Architecture: fast Module: bottom (cell) Architecture: fast

bottom

, top bottom . -debugCellOpt

-fast,

top .

-fast Transcript,

,

. : ModelSim

5.6

,

-

.

, " celldefine.

Referencing the optimized design ( ) , , . fast,

99

- "verilog". (

" fast ") ,

- fast = < option>. "Opt1"

,

,

: % vlog -fast=opt1 cpu_rtl.v ,

, , , ,

,

.

(testbenches).

,

, ,

,

,

. :

% vlog -fast=t1 testbench1.v design.v -- Compiling module testbench1 -- Compiling module design Top level modules: testbench1 Analyzing design... Optimizing 2 modules of which 0 are inlined: -- Optimizing module design(t1) -- Optimizing module testbench1(t1)

% vlog -fast=t2 testbed2.v design.v -- Compiling module testbench2 -- Compiling module design Top level modules: testbench2 Analyzing design... 100

Optimizing 2 modules of which 0 are inlined: -- Optimizing module design(t2) -- Optimizing module testbench2(t2) design.v, , t2. testbench1,

testbench1 testbench2

,

testbench1 testbench2

,

t1

t1. t2.

,

. ,

, , ,

.

,

, (

)

. ( ).

"verilog", ,

,

testbench

, , . ,

defparams, , .

, % vlog -fast=c1 testbench.v design.v config1.v -- Compiling module testbench -- Compiling module design -- Compiling module config1 Top level modules: testbench config1 Analyzing design... Optimizing 3 modules of which 0 are inlined: -- Optimizing module design(c1) -- Optimizing module testbench(c1) -- Optimizing module config1(c1)

101

% vlog -fast=c2 testbench.v design.v config2.v -- Compiling module testbench -- Compiling module design -- Compiling module config2 Top level modules: testbench config2 Analyzing design... Optimizing 3 modules of which 0 are inlined: -- Optimizing module design(c2) -- Optimizing module testbench(c2) -- Optimizing module config2(c2) "testbench"

,

,

.

,

% vsim ’ testbench (c1) ’ config1 ,

config1, .

, ,

.

,

,

Simulate ,

, .

– fast .

1

GUI, Library (Main window) , ,

.

vdir (CR-257)

.

, VSIM 1> vdir design # MODULE design # Optimized Module t1 # Optimized Module t2 102

,

: " __ < n> "

.

, (

,

).

Enabling design object visibility with the +acc option ( +acc ) ,

– fast PLI.

,

, . PLI.

,

PLI Access , ,

,

,

, .

,

– fast , .

, –fast ,

+acc .

,

, .

+acc

:

+acc[=][+[.]] :

b

. PLI, .

, ,

. zxtqrfv

c

rb.

Verilog

ё

,

PLI

. .

l ,, n p

,

.

. , PLI , ( .

, ) (

r

,

,

,

) 103



,

< module> . ,

ё

.

,

"." "+".

, . PLI, , $dumpvars -

, +acc.

, PLI,

, PLI acc_vcl_add, , . ,

VCD.

ё

, $dumpvars

,

$dumpvars,

testbench ( ):

initial $dumpvars; , : % vlog -fast +acc=rn testbench.v design.v ,

, (

,

1

,

):

initial $dumpvars(1, testbench.u1); ( testbench.u1

" design"):

% vlog -fast +acc=rn+design testbench.v design.v , (

, 0

testbench.u1 ):

,

initial $dumpvars(0, testbench.u1); : % vlog -fast +acc=rn+design. testbench.v design.v , .

104

Using pre-compiled libraries( ) –fast , , , -L

vlog (CR-286).

-Lf

, .

,

. ,

XL

‘ uselib (

.Verilog-

‘ uselib ). ‘ uselib ,

, .

-L or –Lf vsim (CR-296) ,

:

.

Event order and optimized designs ( ) ,

Verilog .

,

,

–fast ,

–fast. (

ordering in Verilog designs" -keep_delta ( ,

).

. " "Event

,

. vlog (CR-286))

–fast , .

,

.

Timing checks in optimized designs ( ) , ,

.

–fast. ,

, ,

. -

–fast

Std 1364-1995. ,

, –fast Std

1364-2001.

105

Simulating with an elaboration file( ) Overview( ) ModelSim

, .

, .

,

:

.

ModelSim (

,

,

.

5.6, ),

. ,

,

"

."

. PLI

, FLI. ? . ,"

,

"

, , .

, -

, , ,

SDF.

. , .

ModelSim ,

, ModelSim

,

.

Elaboration file flow (

) , .

1 , -sdf instance=) . Verilog, $sdf_annotate , 2 vsim, . ( , ( ). 3 )( ).

, ( $sdf_annotate. . )

,

106

Creating an elaboration file (

) ,

-elab ModelSim.

К

(CR-296).

Loading an elaboration file(

vsim

) ,

-load_elab

vsim (CR-296). : . vsim ( ,

, OS,

,

).

Modifying stimulus (

) . .

•

, .

; ,

, •

, .

-filemap_elab, . ,

• .

stdin/stdout. , . , .

VCD vcdread vcdstim

• Verilog, mc_scan_plusargs (). +args

ё

,

, ,

PLI

+args,

+args

VCD

,

ё

,

.

Using with the PLI or FLI( PLI , sizetf, misctf -load_elab,

FLI) tf

checktf, PLI tf ,

. ,

, .

Verilog HDL

PLI

-load_elab

, PLI

. FLI

,

107

.

FLI,

(-elab) (-load_elab)

, .

FLI , ,

, ,

,

-load_elab. "

/

FLI "

FLI

Syntax(

.

)

vsim (CR-296 ) -compress_elab, -filemap_elab, -load_elab.

-elab,

Cell Libraries( Model Technology ) ". .

) ё

ASIC Council’s Verilog Si2 "Library Tested and Approved( , Verilog ASIC.

, ModelSim Verilog.

ASIC

"

ё

FPGA

Verilog

" Verilog , .

. , 14.5 . ModelSim Verilog

Std 1364-1995

Std 1364

13

Verilog-XL

SDF timing annotation( ModelSim Verilog

.

SDF

)

,

(SDF - Standard Delay Format). 11 - Standard Delay Format (SDF) Timing Annotation (SDF) .

. (Ф

Delay modes(

)

)

Verilog

, , UDPs, ,

. -

. ,

,

ё

port -to- port ,

-

.

Verilog .

,

module and2(y, a, b); 108

input a, b; output y; and(y, a, b); specify (a => y) = 5; (b => y) = 5; endspecify endmodule " "

" " ,

,

,

.

,

,

. ,

,

, ..

,

,

, (

Std 1364-1995).

-

, .

Verilog-XL.

.

. +delay_mode_distributed ‘ delay_mode_distributed.

,

, .

+delay_mode_path

(

ё

‘ delay_mode_path.

, time_unit

‘ timescale), . +delay_mode_unit

‘ delay_mode_unit.

, . +delay_mode_zero ‘ delay_mode_zero.

109

System Tasks(

)

Std 1364 ModelSim Verilog

Verilog, , Verilog-XL. ,

,

, Language Interface) Interface).

(PLI – Programming Verilog (VPI - Verilog Procedural ,

,

PLI/VPI, .

IEEE Std 1364 system tasks (

Std 1364

) Std 1364.

$printtimescale $timeformat

$finish $stop

$dist_chi_square $dist_erlang $dist_exponential $dist_normal $dist_poisson $dist_t $dist_uniform $random

$bitstoreal $itor $realtobits $rtoi $signed $unsigned

$realtime $stime $time

$q_add $q_exam $q_full $q_initialize $q_remove

$test$plusargs $value$plusargs

$hold $nochange $period $recovery $setup $setuphold $skew $width $removal $recrem

110

PLA $display $displayb $displayh $displayo $monitor $monitorb $monitorh $monitoro $monitoroff $monitoron $strobe $strobeb $strobeh $strobeo $write $writeb $writeh $writeo яФ $fclose $fdisplay $fdisplayb $fdisplayh $fdisplayo $ferror $fflush $fgetc $fgets $fmonitor $fmonitorb $fmonitorh $fmonitoro

$async$and$array $async$nand$array $async$or$array $async$nor$array $async$and$plane $async$nand$plane $async$or$plane $async$nor$plane $sync$and$array $sync$nand$array $sync$or$array $sync$nor$array $sync$and$plane $sync$nand$plane $sync$or$plane $sync$nor$plane

В $fopen $fread $fscanf $fseek $fstrobe $fstrobeb $fstrobeh $fstrobeo $ftell $fwrite $fwriteb

(VCD) $dumpall $dumpfile $dumpflush $dumplimit $dumpoff $dumpon $dumpvars $dumpportson $dumpportsoff $dumpportsall $dumpportsflush $dumpports $dumpportslimit

- ы $fwriteh $fwriteo $readmemb $readmemh $rewind $sdf_annotate $sformat $sscanf $swrite $swriteb $swriteh $swriteo $ungetc

: $readmemb $readmemh Std 1364. , . , ModelSim ,

Verilog-XL, , [127:0] 0

[0:127], 127.

111

Verilog-XL compatible system tasks (Verilog-XL

) Verilog-XL.

, Std 1364. $countdrivers $getpattern $sreadmemb $sreadmemh Verilog-XL, Std 1364. $deposit(variable, value); Verilog ; value -

variable , .

.

, $deposit

. ModelSim

force –deposit.

$system("operating system shell command");

. ,

Unix:

$system ("ls"); ,

,

( Verilog-XL.

)

$recovery (reference_event, data_event, removal_limit, recovery_limit ,[notifier], [tstamp_cond], [tcheck_cond], {delayed-reference],[delayed_data]) $recovery notifier , $recrem recovery_limit

recovery_limit . $recovery .

,

, removal_limit

.

$setuphold(clk_event, data_event, setup_limit, hold_limit, [notifier], [tstamp_cond], [tcheck_cond], [delayed_clk], [delayed_data])

112

tstamp_cond clk_event.

data_event clk_event

data_event.

tcheck_cond clk_event.

data_event clk_event

delayed_clk clk_event.

data_event.

, ,

setup_limit,

. delayed_data, data_event. . delayed_clk

,

delayed_data

hold_limit

,

, .

delayed_clk

delayed_data

clk

data .

, . delayed_data

delayed_clk , "Negative timing check limits"

.

,

.

-

Verilog-XL,

ModelSim Verilog,

.

$input("filename") . do . $list [(hierarchical_name)] ,

.

. Source . $reset 0. - restart. $restart("filename") , ,

$save. restore .

$save("filename") 113

, . checkpoint . $scope (hierarchical_name) hierarchical_name. environment . $showscopes , . show. $showvars , .

show.

$init_signal_driver system task( $init_signal_driver () VHDL

Verilog

$init_signal_driver ) VHDL Verilog. Verilog

(

, testbench). $init_signal_driver

12- Signal Spy .

$init_signal_spy system task(

$init_signal_spy)

$init_signal_spy () /

VHDL, VHDL.

Verilog

Verilog , , Verilog ( , testbench). $init_signal_spy 12- Signal Spy .

$signal_force system task(

$signal_force)

$signal_force () VHDL

, Verilog. Verilog (

, ,

testbench). $signal_force

$signal_force

force (CR-154 ) . 12- Signal Spy .

,

114

$signal_release system task(

$signal_release)

$signal_release () VHDL noforce (CR-171.) $signal_release 12- Signal Spy .

, Verilog. $signal_release

Compiler Directives(

)

ModelSim Verilog 1364

,

Std

Verilog-XL (

.

‘timescale) , ‘

resetall. ,

, .

,

, ,

,

. ,

‘ resetall ( Std 1364): ‘ ‘ ‘ ‘ ‘ ‘ ‘ ‘ ‘

celldefine Define_nettype Delay_mode_distributed Delay_mode_path Delay_mode_unit Delay_mode_zero timescale Unconnected_drive uselib 115

ModelSim Verilog

:

‘define MODEL_TECH

IEEE Std 1364 compiler directives( )

Std 1364 Std 1364.

‘ celldefine ‘ default_nettype ‘define ‘else ‘endcelldefine ‘endif ‘ifdef ‘include ‘nounconnected_drive ‘resetall ‘timescale ‘unconnected_drive ‘undef

Verilog-XL compatible compiler directives ( Verilog-XL

) Verilog-XL.

‘default_decay_time , , ,

. "

"

,

.

‘delay_mode_distributed . modes(

)

. Delay

.

‘ delay_mode_path ё Delay modes(

.

)

.

.

‘ delay_mode_unit

. Delay modes(

)

. .

116

‘ delay_mode_zero . modes(

)

. Delay

.

‘ uselib +libext. . Verilog-XL ‘uselib compiler directive( Verilog-XL ) .

-v, -y, ‘uselib

Verilog-XL ё

ModelSim Verilog. ModelSim Verilog,

,

Verilog-XL.

‘accelerate ‘autoexpand_vectornets ‘disable_portfaults ‘enable_portfaults ‘endprotect ‘expand_vectornets ‘noaccelerate ‘noexpand_vectornets ‘noremove_gatenames ‘noremove_netnames ‘nosuppress_faults ‘protect ‘remove_gatenames ‘remove_netnames ‘suppress_faults Verilog-XL ModelSim Verilog. -

ModelSim Verilog, ModelSim Verilog

, Verilog-XL.

‘default_trireg_strength ‘signed ‘unsigned

117

Verilog PLI/VPI Verilog PLI (Programming Language Interface(Verilog Procedural Interface -

)

VPI

Verilog) C.

PLI ( (

, . Third party PLI applications PLI

Verilog )).

,

PLI/VPI.

ModelSim Verilog

PLI acc_handle_datapath(). ,

cc_handle_datapath(),

Std 1364, , .

5.6 , VPI

Std 1364-2001. :

< install_dir>/modeltech/docs/technotes/Verilog_VPI.note. Std 1364 -

,

PLI/VPI. PLI/VPI ModelSim Verilog.

Registering PLI applications(

PLI)

PLI , . PLI Verilog-XL, ModelSim Verilog PLI s_tfcell.

veriuser.h

, : 118

typedef int (*p_tffn)(); typedef struct t_tfcell { short type;/* USERTASK, USERFUNCTION, or USERREALFUNCTION */ short data;/* */ p_tffn checktf; /* , */ p_tffn sizetf; /* */ p_tffn calltf; /* */ p_tffn misctf; /* */ char *tfname;/* */ /*

ModelSim Verilog */

int forwref; char *tfveritool; char *tferrmessage; int hash; struct t_tfcell *left_p; struct t_tfcell *right_p; char *namecell_p; int warning_printed; } s_tfcell, *p_tfcell; (checktf, sizetf, calltf,

misctf)

Std 1364.

. ,

,

calltf, Verilog.

,

PLI, (USERTASK) (USERFUNCTION) (USERREALFUNCTION). tfname $).

,

( ). , ( ModelSim Verilog.

PLI, init_usertfs,

veriusertfs. ,

init_usertfs

, mti_RegisterUserTF ()

. veriuser.h

mti_RegisterUserTF ()

:

void mti_RegisterUserTF(p_tfcell usertf); ё (de-references) , 0.

usertf , usertf,

, . ,

veriusertfs (

Verilog-XL), 119

init_usertfs, ( 0).

,

s_tfcell veriusertfs[] = { {usertask, 0, 0, 0, abc_calltf, 0, "$abc"}, {usertask, 0, 0, 0, xyz_calltf, 0, "$xyz"}, {0} /* last entry must be 0 */ }; ,

init_usertfs, :

void init_usertfs() { p_tfcell usertf = veriusertfs; while (usertf->type) mti_RegisterUserTF(usertf++); } , init_usertfs.

PLI

veriusertfs

PLI ,

( ,

"Compiling and linking PLI/ VPI applications"(" PLI/VPI " ). PLI Windows .dll): •

Veriuser

(

.

,

modelsim.ini:

Veriuser = pliapp1.so pliapp2.so pliappn.so •

PLIOBJS:

% setenv PLIOBJS " pliapp1.so pliapp2.so pliappn.so " •

-pli

(

):

-pli pliapp1.so -pli pliapp2.so -pli pliappn.so

.

PLI ,

. .

120

Registering VPI applications (

VPI)

VPI .

,

. Vpi_register_systf () Vpi_register_cb () ,

. vlog_startup_routines

,

. 0

.

PLI_INT32 MyFuncCalltf (PLI_BYTE8 *user_data) {..} PLI_INT32 MyFuncCompiletf (PLI_BYTE8 *user_data) {..} PLI_INT32 MyFuncSizetf (PLI_BYTE8 *user_data) {..} PLI_INT32 MyEndOfCompCB (p_cb_data cb_data_p) {..} PLI_INT32 MyStartOfSimCB (p_cb_data cb_data_p) {..} void RegisterMySystfs( void ) { vpiHandle tmpH; s_cb_data callback; S_vpi_systf_data systf_data; Systf_data.type = vpiSysFunc; Systf_data.sysfunctype = vpiSizedFunc; Systf_data.tfname = "$myfunc"; Systf_data.calltf = MyFuncCalltf; Systf_data.compiletf = MyFuncCompiletf; Systf_data.sizetf = MyFuncSizetf; Systf_data.user_data = 0; tmpH =Vpi_register_systf (&systf_data);

vpi_free_object(tmpH); callback.reason = cbEndOfCompile; callback cb_rtn = MyEndOfCompCB; callback user_data =0; tmpH = vpi_register_cb (&callback);

vpi_free_object(tmpH); callback.reason = cbStartOfSimulation; callback cb_rtn = MyStartOfSimCB; callback user_data = 0; 121

tmpH = vpi_register_cb (&callback);

vpi_free_object(tmpH); ) void (*vlog_startup_routines [ ] ) () = { RegisterMySystfs, 0 /* 0 */ }; VPI

-

"Registering PLI applications(

PLI) ".

PLI

VPI ,

. : •

init_usertfs ()

, ,

mti_RegisterUserTF (). •

init_usertfs ()

,

veriusertfs

, veriusertfs.

, •

init_usertfs () Vlog_startup_routines , vlog_startup_routines.

,

veriusertfs

,

,

,

PLI

VPI

, .

VPI, vlog_startup_routines ,

init_usertfs ().

Compiling and linking PLI/VPI (

applications PLI/VPI)

PLI/VPI C , Microsoft Visual C / C ++ gcc cc . PLI/VPI ё ModelSim /modeltech/ include. _user.h ACC, TF, vpi_user.h VPI , . ,

, ModelSim. Windows DLLs, UNIX , veriuser.h . PLI

VPI

. -

, . 122

, (

("Specifying the PLI/VPI file to load " )).

PLI/VPI, Windows

cl -c -I\modeltech\include app.c link -dll -export: app.obj \ \modeltech\win32\mtipli.lib/out:app.dll Verilog PLI, "init_usertfs". , init_usertfs, , "veriusertfs". Verilog VPI, "vlog_startup_routines". , , ModelSim , DLL. PLI VPI DLLs, Microsoft Visual C / C ++ 4.1 . gcc PLI/VPI Windows. , gcc Microsoft. lib/.dll. Linux gcc compiler: gcc -c -I//modeltech/include app.c ld -shared -E -o app.so app.o cc compiler: cc -c -I//modeltech/include app.c ld -shared -E -o app.so app.o 32-

Solaris

gcc compiler: gcc -c -I//modeltech/include app.c ld -G -B symbolic -o app.so app.o cc compiler: cc -c -I//modeltech/include app.c ld -G -B symbolic -o app.so app.o :

-B

ld , .

.

. ,

app.so

Solaris, :

. •

app.so

.(

.) 123

• LD_LIBRARY_PATH =


64Solaris cc -v -xarch=v9 -O -I$//modeltech/include -c app.c ld -G -B symbolic app.o -o app.so :

ld ,

-B

. .

.

32-

HP700 ё

, (

+z

,

) , -b ).

-fpic

( gcc compiler:

gcc -c -fpic -I / /modeltech/include app.c ld -b -o app.sl app.o cc compiler: cc -c +z -I / /modeltech/include app.c ld -b -o app.sl app.o ,

gcc.

-fpic

64-

HP700

cc -v +DD64 -O -I/modeltech/include -c app.c ld -b -o app.so app.o

32ModelSim IBM RS/6000. ModelSim's ,

IBM RS/6000 PLI/VPI VPI

PLI . ModelSim rs6000/mti_exports ModelSim

. PLI/VPI

,

, C,

‘-lc’

PLI/VPI. ‘ld’.

, gcc

cc

AIX 4.x: gcc compiler:

124

gcc -c -I / /modeltech/include app.c ld -o app.sl app.o -bE:app.exp \ - bI://modeltech/rs6000/mti_exports -bM:SRE -bnoentry -lc cc compiler: cc -c -I / /modeltech/include app.c ld -o app.sl app.o -bE:app.exp \ - bI://modeltech/rs6000/mti_exports -bM:SRE -bnoentry –lc app.exp

PLI/VPI.

PLI,

"init_usertfs".

, "veriusertfs".

init_usertfs ,

VPI,

"vlog_startup_routines". ,

, ,

ModelSim 64-

.

IBM RS/6000 4.3 AIX

64-

. 64-

.

gcc

:

cc -c -q64 -I//modeltech/include app.c ld -o app.s1 app.o -b64 -bE:app.exports \ -bI://modeltech/rs64/mti_exports -bM:SRE -bnoentry -lc AIX 4.3 32-

:

,

-DUSE_INTTYPES

. ,

inttypes.h

mti.h.

Compiling and linking PLI/VPI C++ applications( PLI/VPI C++) ModelSim C;

,

C++

. PLI/VPI ModelSim C++

C, PLI/VPI

.

extern: extern "C" {

} veriuser.h, acc_user.h,

vpi_user.h

extern.

125

PLI/VPI (veriusertfs, init_usertfs,

vlog_startup_routines) extern. ModelSim C C++, iostreams cout, . io_mcdprintf (), io_printf (), vpi_mcd_printf (), vpi_printf (), vpi_vprintf (), vpi_mcd_vprintf () (transcript). , PLI/VPI C++ , ModelSim. Microsoft Visual C++ Windows DLLs, C++ C++ UNIX. , . , " PLI/VPI ". Windows

GNU

Microsoft Visual C++: cl -c [-GX] -I\modeltech\include app.cxx link -dll -export: app.obj \ \modeltech\win32\mtipli.lib /out:app.dll -GX . Verilog PLI, "init_usertfs". , init_usertfs, , "veriusertfs". Verilog VPI, "vlog_startup_routines". , , ModelSim , DLL.

: GNU PLI/VPI Microsoft. lib/.dll.

C++ Windows.

32GNU C++

,

GNU C++

Linux 2.95.3

c++ -c -fPIC -I/modeltech/include app.C c++ -shared -fPIC -o app.so app.o 32Sun WorkShop

Solaris 5.0

CC -c -Kpic -o app.o -I/modeltech/include app.C CC -G -o app.so app.o -lCstd -lCrun GNU C++

2.95.3

126

c++ -c -fPIC -I/modeltech/include app.C c++ -shared -fPIC -o app.so app.o 64-

Solaris

Sun WorkShop

5.0

CC -c -v -xcode=pic32 -xarch=v9 -o app.o \ -I/modeltech/include app.C CC -G -xarch=v9 -o app.so app.o -lCstd -lCrun 32-

HP-UX C++, .

: UX 11.0 HP C++

HP-

3.25

aCC -c +DAportable +z -o app.o -I/modeltech/include app.C aCC -v -b -o app.so app.o -lstd -lstream –lCsup GNU C++

2.95.3

c++ -c -fPIC -I/modeltech/include app.C c++ -shared -fPIC -o app.so app.o

ModelSim

GNU C++ -

, ModelSim .

64HP C++

-UX,

. ,

- UX 3.25

aCC -c +DA2.0W +z -o app.o -I/modeltech/include app.C aCC -v +DA2.0W -b -o app.so app.o -lstd -lstream -lCsup 32-

IBM RS/6000

IBM C++ version 3.6 xlC -c -o app.o -I/modeltech/include app.C makeC++SharedLib -o app.sl \ -bI:/modeltech/rs6000/mti_exports -p 10 app.o 64IBM C++

IBM RS/6000 3.6

127

xlC -q64 -c -o app.o -I/modeltech/include app.C makeC++SharedLib -o app.sl -X64 \ -bI:/modeltech/rs64/mti_exports -p 10 app.o

Using 64-bit ModelSim with 32-bit PLI/VPI Applications( ModelSim 32PLI/VPI) 32-

PLI/VPI

64-

ModelSim,

64ILP32

64-

,

LP64. ,

64-

:

Sun Solaris 7 64-bit Developer’s Guide http://docs.sun.com:80/ab2/coll.45.10/SOL64TRANS/ HP HP-UX 64-bit Porting and Transition Guide http://docs.hp.com:80/dynaweb/hpux11/hpuxen1a/0462/@Generic__BookView HP-UX 11.x Software Transition Kit http://software.hp.com/STK/

Specifying the PLI/VPI file to load ( PLI/VPI

)

PLI/VPI •

: Veriuser

modelsim.ini :

Veriuser = pliapp1.so pliapp2.so pliappn.so •

PLIOBJS:

% setenv PLIOBJS " pliapp1.so pliapp2.so pliappn.so " •

. -pli

(

):

-pli pliapp1.so -pli pliapp2.so -pli pliappn.so : .dll

Windows,

,

.so. PLI/VPI

.

,

. .

modelsim.ini.

ModelSim

128

PLI example(

PLI) ,

PLI.

hello.c: #include "veriuser.h" static hello() { io_printf("Hi there\n"); return 0; } s_tfcell veriusertfs[] = { {usertask, 0, 0, 0, hello, 0, "$hello"}, {0} /* last entry must be 0 */ }; hello.v: module hello; initial $hello; endmodule Compile the PLI code for the Solaris operating system: % cc -c -I/modeltech/include hello.c % ld -G -o hello.sl hello.o Compile the Verilog code: % vlib work % vlog hello.v Simulate the design: % vsim -c -pli hello.sl hello # Loading work.hello # Loading ./hello.sl VSIM 1> run -all # Hi there VSIM 2> quit

VPI example (

VPI ) ,

VPI.

hello.c: #include "vpi_user.h" static PLI_INT32 hello(PLI_BYTE8 * param) { vpi_printf( "Hello world!\n" ); } 129

void RegisterMyTfs( void ) { s_vpi_systf_data systf_data; vpiHandle systf_handle; systf_data.type = vpiSysTask; systf_data.sysfunctype = vpiSysTask; systf_data.tfname = "$hello"; systf_data.calltf = hello; systf_data.compiletf = 0; systf_data.sizetf = 0; systf_data.user_data = 0; systf_handle = vpi_register_systf( &systf_data ); vpi_free_object( systf_handle ); } void (*vlog_startup_routines[])() = { RegisterMyTfs, 0 }; hello.v: module hello; initial $hello; endmodule Compile the VPI code for the Solaris operating system: % gcc -c -I/include hello.c % ld -G -o hello.sl hello.o Compile the Verilog code: % vlib work % vlog hello.v Simulate the design: % vsim -c -pli hello.sl hello # Loading work.hello # Loading ./hello.sl VSIM 1> run -all # Hello world! VSIM 2> quit

The PLI callback reason argument(

PLI)

PLI 1364

. Std 1364. misctf

. veriuser.h. . Std ModelSim Verilog, , : 130

reason_endofcompile . reason _finish $finish

quit.

. reason _startofsave checkpoint , .

PLI tf_write_save,

,

reason_save. reason _save ё

, tf_write_save.

checkpoint.

PLI

reason _startofrestart restore , . ,

PLI ё

tf_read_restart, reason_startofrestart ,

reason_restart. , -restore.

reason _restart restore.

ё

-

PLI tf_read_restart.

reason _reset restart .

ё

PLI ,

.

PLI

, , PLI -keeploaded (CR-299) -keeploadedrestart (CR-299) .)

( vsim

.

reason _endofreset ,

restart, ,

,

.

reason _interactive $stop . reason _scope environment acc_set_interactive_scope,

. callback_flag

.

reason _paramvc .

131

reason _synch ,

tf_synchronize().

reason _rosynch ,

tf_rosynchronize().

reason _reactivate ,

tf_setdelay.

reason _paramdrc ModelSim Verilog. reason _force ModelSim Verilog. reason _release ModelSim Verilog. reason _disable ModelSim Verilog.

The sizetf callback function(

sizetf)

sizetf , . sizetf •

sizetf,

Std 1364: 32.

•

sizetf " real" Verilog.

0,

•

sizetf " integer" Verilog.

-32,

PLI object handles(

PLI) ,

PLI ACC

,

, ,

,

acc_close

.

,

, cc_close(). ModelSim Verilog

:

accOperator (acc_handle_condition) accWirePath (acc_handle_path) 132

accTerminal (acc_handle_terminal, acc_next_cell_load, acc_next_driver, cc_next_load) accPathTerminal (acc_next_input acc_next_output) accTchkTerminal (acc_handle_tchkarg1 acc_handle_tchkarg2) accPartSelect (acc_handle_conn, acc_handle_pathin, acc_handle_pathout) accRegBit (acc_handle_by_name, acc_handle_tfarg, acc_handle_itfarg) PLI

,

acc_close

, .

ё

PLI accTerminal, .

accRegBit

,

acc_close () ,

Third party PLI applications(

PLI) PLI

ModelSim Verilog. ModelSim Verilog , PLI. ModelSim Verilog.

,

,

Verilog-XL PLI,

, Verilog-XL PLI veriuser.c. veriuser.c "Registering PLI applications"( " ModelSim Verilog, veriuser.c , ( . "Compiling and linking PLI/VPI applications"(" PLI/VPI") ). , veriuser.c , , Solaris:

PLI ").

libapp.a,

% cc -c -I /modeltech/include veriuser.c % ld -G -o app.sl veriuser.o libapp.a PLI

ModelSim Verilog.

Veriuser PLIOBJS (

modesim.ini, "

HP700, , Verilog-XL

:

-pli PLI " ).

+z.

,

, ,

,

, ,

ModelSim Verilog.

, 133

, ,

.

Support for VHDL objects(

VHDL)

PLI ACC VHDL VHDL VHDL , : Type ( ) Fulltype( ) accArchitecture accArchitecture accArchitecture accEntityVitalLevel0 accArchitecture

ccArchVitalLevel0

accArchitecture

cArchVitalLevel1

accArchitecture

VHDL/Verilog.

Description(

)

, VITAL_Level0 , VITAL_Level0 , VITAL_Level1 , FOREIGN

accForeignArch

VHDL , generics accArchitecture

accForeignArchMixed

, FOREIGN VHDL , generics

accBlock accForLoop accForeign

accBlock accForLoop accShadow mti_CreateRegion ()

accGenerate

accGenerate

accPackage accSignal

accPackage accSignal

acc_vhdl.h. ACC , , , ModelSim VHDL (mti_* .

ё ,

VHDL )

(

, ).

. generics, .

, ,

PLI ,

. FLI Reference Manual

134

IEEE Std 1364 ACC routines ( Std 1364 ACC ) ModelSim Verilog Std 1364. : acc_fetch_paramval () , acc_fetch_paramval_str () Acc_fetch_paramval_str () , cc_fetch_paramval () , Acc_fetch_paramval_str ()

ACC

,

64.

-

,

PLI acc_user.h.

. ,

*. .

IEEE Std 1364 TF routines ( ModelSim Verilog Std 1364.

Std 1364 TF ) TF

,

135

Verilog-XL compatible routines (

Verilog-XL)

PLI

Std 1364,

ModelSim Verilog

Verilog-XL. char *acc_decompile_exp(handle condition)

acc_decompile_expr Verilog-XL. acc_handle_condition.

, acc_decompile_exp –

, .

char *tf_dumpfilename(void) VCD. void tf_dumpflush(void) VCD ( $dumpflush

Verilog).

int tf_getlongsimtime(int *aof_hightime) 64.

, aof_hightime.

64-bit support in the PLI ( acc_fetch_paramval PLI () , acc_fetch_paramval_str () Acc_fetch_paramval_str () , acc_fetch_paramval () *. Acc_fetch_paramval_str ()

64-

PLI) 64.

-

,

PLI acc_user.h.

. , .

136

PLI/VPI tracing(

PLI/VPI )

, PLI

VPI. : ,

-

,

;

,

C,

,

, .

logfile(

)

PLI

VPI.

,

MTI PLI/VPI,

, PLI/VPI. VHDL/Verilog,

, .

,

vsim (CR-235)

-trace_foreign:

vsim -trace_foreign [-tag ]

:

ё

1

"mti_trace_" ё

2

"mti_data_.c", "mti_init_.c", "mti_replay_.c" and "mti_top_.c" ё

3

-tag ,

.

.

137

vsim -trace_foreign 1 mydesign logfile. vsim -trace_foreign 3 mydesign , logfile

.

vsim -trace_foreign 1 -tag 2 mydesign logfile "2".

, (calltf, checktf, sizetf

PLI/VPI

misctf

),

Verilog VCL.

Debugging PLI/VPI application code(

PLI/VPI) PLI/VPI

, (

).

-g

Solaris, AIX, vsim ‘). , wdb ‘

ddd ‘ (

.

vsim

ё

,

, ,

vsim

.

Linux

gdb - UX

ddd (

,

wdb HP www.hp.com/go/wdb.

vsim ‘). 1.2

. vsim's PLI/VPI, PLI/VPI,

. ,

,

()

. vsim, .

acc_product_version , ,

(

vsim

, " run -c top").

HP-UX

,

vsim , F5 , HP-UX " __ dld_flags "

. . HP Windows NT, , , vsim GUI. go , vsim wdb. , . share , . ,

vsim Exceed,

NT " go"

PLI/VPI. .

. PLI/VPI.

,

share . PLI/VPI

.

PLI/VPI.

138

6 - Mixed VHDL and Verilog Designs ( VHDL Verilog) ,

VHDL Verilog VHDL Verilog Verilog VHDL

Verilog Verilog vgencomp

Verilog VHDL SDF

VHDL

,

(SKS - single-kernel simulation) ModelSim VHDL / Verilog. ,

HDLs. VHDL ,

VHDL

Verilog

.

,

VHDL . HDL

Verilog.

Verilog, .

, VHDL

Verilog.

139

Separate compilers, common design libraries( , ) vcom (CR-250)

VHDL

(

(

, Verilog UDPs)

)

,

.

, ,

vlog (CR-286) . VHDL

Verilog, VHDL

( ).

. "Design Libraries"( "

") ,

vcom (CR-250)

vlog(CR-286).

Access limitations in mixed-language designs( ) Verilog VHDL. , ,

,

. VHDL (

, . .)

, . ,

Verilog VHDL.

"

VHDL VHDL: 1) ; 2) 12 - Signal Spy

" )

(

Verilog Signal Spy( ).

Simulator resolution limit( ) VHDL.

" Simulator resolution limit "

.

Mapping data types( - HDL ModelSim

. HDL -

) ,

-

, ,

HDL . 140

VHDL

Verilog .

VHDL Verilog

, Verilog VHDL generics VHDL. ModelSim HDL .

Verilog

VHDL generics ( VHDL integer real time physical enumeration string

VHDL) Verilog integer or rea integer or real integer or real integer or rea integer or real string literal real, real

,

. : ‘ timescale.

Verilog

, T'VAL (P),

Verilog. , VAL -

T–

VHDL , ,

Verilog parameters( Verilog VHDL integer real string

P-

.

)

Verilog Integer Real String Verilog

VHDL and Verilog port( VHDL ё

VHDL Verilog:

ё

VHDL

.

Verilog

) Verilog

,

Bit bit_vector std_logic std_logic_vector vl_logic 141

vl_logic_vector vl_logic ,

,

Verilog,

ё vl_logic

.

bit

std_logic ,

Verilog. ,

vl_logic . vl_types

Vl_logic verilog. ( std

ieee). ModelSim. (

vl_types . \modeltech\vhdl_src\verilog\vltypes.vhd.)

Verilog states( Verilog

)

Verilog

std_logic

bit

:

Verilog

std_logic

bit

HiZ

’Z‘

’0‘

Sm0

’L‘

’0‘

Sm1

’H‘

’1‘

SmX

’W‘

’0‘

Me0

’L‘

’0‘

Me1

’H‘

’1‘

MeX

’W‘

’0‘

We0

’L‘

’0‘

We1

’H‘

’1‘

WeX

’W‘

’0‘

La0

’L‘

’0‘

La1

’H‘

’1‘

142

LaX

’W‘

’0‘

Pu0

’L‘

’0‘

Pu1

’H‘

’1‘

PuX

’W‘

’0‘

St0

’0‘

’0‘

St1

’1‘

’1‘

StX Su0

’X‘ ’0‘

’0‘ ’0‘

Su1

’1‘

’1‘

SuX

’X‘

’0‘

ё

Verilog •

(strength):

'0'

• std_logic strong strength(

'X',

• std_logic strong strength(

'W',

0

1

) 0 )

1

VHDL

Verilog bit '0' '1'

VHDL std_logic,

:

Verilog St0 St1

Verilog Std_logic

Verilog

'U' 'X' '0' '1' 'Z' 'W' 'L' 'H'

StX StX St0 St1 HiZ PuX Pu0 Pu1

:

143

'- '

StX

VHDL instantiation of Verilog design units (VHDL Verilog) Verilog, , Verilog

VHDL

. .

ё

,

,

ё

,

Verilog

.

Verilog instantiation criteria(

Verilog)

Verilog : •

VHDL,

-

(UDPs,

•

). (Verilog

).

•

( VHDL).

Component declaration( Verilog VHDL ,

)

,

, VHDL. , vgencomp (CR-259). vgencomp (CR-259)

, .

: • std_logic • std_logic_vector ,

:

144

• bit

bit_vector

• vl_logic VHDL

vl_logic_vector

Verilog VHDL

,

ё

ё VHDL 1076-1987, VHDL 1076-1993 ( -93). VHDL

Verilog

,

Verilog VHDL

ё

,

.

Verilog ,

: • Verilog (CR-259)

-93.

vgencomp VHDL 1076-1993 Verilog,

, . , Verilog , , vgencomp (CR-259) -93 . : Verilog , -93 .

•

Verilog topmod TOPMOD TopMod top_mod _topmod

VHDL topmod topmod topmod top_mod \_topmod\

\topmod \ \topmod\

topmod \topmod\

Verilog

ё .

,

,

-93:

Verilog

VHDL

Topmod

topmod

TOPMOD

\TOPMOD\

TopMod

\TopMod\

top_mod

top_mod

_topmod

\_topmod\

145

\topmod

Topmod

\ \topmod\

\topmod\

vgencomp component declaration ( vgencomp) vgencomp (CR-259)

:

Generic clause(

) ,

. , .

,

,

integer

integer

real

real

string literal

string

-

:

.

Verilog p1 = 1 - 3;

VHDL p1 : integer := -2;

p2 = 3.0;

p2 : real := 3.000000;

p3 = "Hello";

p3 : string := "Hello";

,

. Verilog

VHDL

. 146

VHDL VHDL

,

bit, std_logic, vl_logic. - bit_vector, std_logic_vector, ,

Verilog vl_logic_vector. ,

.

Verilog

VHDL

input p1;

p1 : in std_logic;

output [7:0] p2;

p2 : out std_logic_vector(7 downto 0);

output [4:7] p3;

p3 : out std_logic_vector(4 to 7);

inout [width-1:0] p4;

p4 : inout std_logic_vector;

Verilog .

,

Verilog,

Verilog

.

Verilog instantiation of VHDL design units (Verilog VHDL) VHDL

Verilog (

).

VHDL instantiation criteria(

VHDL)

VHDL : •

Verilog,

-

/

• Vl_ulogic_vector, . • -

.

bit, bit_vector, std_ulogic, std_ulogic_vector, vl_ulogic, .

,

, .

,

,

,

.

. ,

. 147

-

VHDL

(1076-1993).

VHDL -

, VHDL

. . ,

ё

defparam

generics

. .

Verilog

. ,

. Verilog,

, .

" Library usage ( .

)" ,

, :

\mylib.entity(arch) u1 (a, b, c); \mylib.entity u1 (a, b, c); \entity(arch) u1 (a, b, c);

, : • library = mylib • design unit = entity • architecture = arch

SDF annotation( SDF VHDL/Verilog for Mixed VHDL and Verilog Designs( SDF .

) SDF. "SDF VHDL /Verilog ")

148

7 – WLF files (datasets) and virtuals (WLF ( ) WLF

(

)

) WLF

ModelSim (

,

,

. .)

WLF WLF(wave log format -wlf vsim (CR. ,

ModelSim 296))

)( "

",

WLF

. ModelSim

5.3

,

WLF

.

, ,

,

.

WLF files (datasets)( WLF

(

))

(WLF)

.

WLF . WLF

"

"

,

, .

WLF

,

" sim ",

. WLF.

,

Wave — 149

" sim "; " gold" .

(

: " Simulator resolution limit " ) ,

.

Saving a simulation to a WLF file( WLF) Dataflow, List, log ,

Wave WLF ,

vsim.wlf ,

. . vsim (CR-296), , WLF . File > Save Dataset Wave Main dataset save (CR-129 dataset snapshot (CR-130), .

,

vsim.wlf

–wlf < filename >

, WLF :

dataset save dataset snapshot, quit quit –sim , WLF. , WLF .

ModelSim )"

" bad magic number ( .

Opening datasets(

) , File > Open > Dataset( dataset open (CR-127.

Open Dataset • Dataset Pathname( WLF • Logical Name for Dataset( , .

Viewing dataset structure (

Main)

. ) ,

. ) .

WLF

)

150

5.5

,

,

,

Structure

. " Structure:

Structure ".

("sim")

("test"

"gold").

, ,

, ,

, UNIX — 2-

(Windows – 1-

). , (Windows — 2-

, , UNIX — 3-

. " Structure window context menu( .

)

-

Structure )"

Managing multiple datasets(

) Ь ,

Dataset Browser. ,

View > Dataset (

Dataset Browser

Main).

.

• Open Open Dataset (

"

)" .

• Close . . • Make Active "

".

,

.

,

, , :

.

env

VSIM.

Main. .

• Rename .

,

,

vsim -view .

151

WLF

. vsim –

,

view

:

-view = : vsim -view foo=vsim.wlf ModelSim ,

,

"

" . Main. ,

. environment (CR-147),

rowser

,

Dataset . WLF

,

.

:

Sim:/top/alu/out View:/top/alu/out Golden:top.alu.out ,

, .

, ModelSim Wave . Tools > Window Preferences (

, Wave

List).

"

ModelSim

List

"

..

environment (CR-147)

.

:

env foo: foo foo. . (

"

")

,

.

Signals

. ,

, . (

, ,

,

pref.tcl, PrefMain (DisplayDatasetPrefix). ё 0 . 1

,

: /top/foo), . File > Environment (

1

Signals).

,

.

152

, Tools > Edit Preferences (

pref.tcl, ).

,

, . - dataset ( , pref.tcl.

environment -nodataset, , environment (CR-147) 1).

environment

Saving at intervals with Dataset Snapshot( ) WLF . "

"

WLF

,

. , Snapshot (

Tools > Dataset

Wave).

Dataset Snapshot Dataset Snapshot

:

• Enabled/Disabled . Disabled К • Simulation Time ,

, 1000000

.

.

• WLF File Size ,

, .

WLF - 100 .

К • Snapshot contains only data since previous snapshot ( , ModelSim, , . • Snapshot contains all previous data ( , .

) . WLF

) ,

153

WLF

,

. К

К

• Directory ,

Ф ModelSim

.

• . ModelSim

.

.wlf

/ • Always replace snapshot file( ,

) . .

• Use incrementing suffix on snapshot files( ) , ё . ( , vsim_snapshot_0.wlf, vsim_snapshot_1.wlf,

. .)..

Virtual Objects (User-defined buses, and more) ( ( , . .)) GUI,

-

ModelSim.

,

5.3, ModelSim : • • • • ,

Bus1

:

Virtual signals(

) 154

-

,

WLF , , , force. (Edit > Combine),

. examine , virtual signal (CR-280). ,

.

, . -install , .

virtual signal

,

,

RTL ,

. ,

RTL-

,

. virtual hide (CR-271) ,

, . ,

WLF

,

virtuals:/Signals. -

, ,

. virtuals save(CR-278). .

, , ModelSim )

, virtuals (

Wave Wave )

" implicit(

virtuals.do

List ,

List,

,

virtuals.do ( Wave

.

virtual

List

: ) virtuals "

Wave

List.

virtuals ModelSim ,

, .

ё

Wave,

,

. -

,

ё

, .

155

"explicit(

) virtuals ".

Virtual functions(

) GUI

,

.

, .

,

,

examine (CR-148),

force

( CR-154). : •

,

•

,

•

,

"

• 1.34 ns "

"

,

"

CLK,

,

ё

.

GUI :

,

, , std_logic, std_logic_vector, 9.

,

. Verilog VHDL std_logic

Verilog ,

the virtual function

(CR-268). ModelSim , Verilog "vreg" Verilog.

Verilog GUI, .

Virtual regions(

.

Verilog ,

)

,

RTL .

,

156

,

RTL . ,

virtual region

(CR-277) .

Virtual types(

) , -

. ,

. , . ,

virtual type

(CR-283).

Dataset, WLF file, and virtual commands ( , WLF

)

, WLF

,

. ,

,

ModelSim.

dataset alias (CR-122) dataset list (CR-126) dataset open (CR-127) dataset save (CR-129) dataset snapshot (CR-130) log (CR-164)

WLF

nolog (CR-172)

WLF

searchlog (CR-212) WLF virtual function (CR-268)

virtual region (CR-277) virtual signal (CR-280) virtual type (CR-283) 157

vsim (CR-296) -wlf

WLF

,

158

)

8 - Graphic Interface( Window

ё

.

ModelSim Windows ;

,

ModelSim

,

. ,

ModelSim , ModelSim .

. Tcl/Tk,

,

,

.

159

Window overview(

Window) .

ModelSim

( File > New

). Window. : • ,

. .

ModelSim ) .

(

• "

"

(

).

• VHDL,

Verilog

. • ,

.

• VHDL, ,

Verilog .

• , ("

HDL .( . see "Source code security and -nodebug" -nodebug ") .)

• , ,

,

,

VHDL

, .

5.5

Verilog,

,

, .

• VHDL

,

Verilog

(

),

, .

• ( VHDL,

), Verilog

. .

160

Common window features(

)

ModelSim’s

, ; .

Quick access toolbars(

Main, Source,

Wave

) Drag and Drop (

Dataflow, List, Process, Signals, Source, Structure, Variables,

)

Command history( ) Automatic window updating ( ) Finding names, searching for values, and locating cursors ( , , ) Sorting HDL items ( HDL ) Multiple window copies ( Menu tear off(

Dataflow, Process, Signals,

Wave

Structure

Process, Signals, Source, Structure, Variables Wave

) )

Customizing menus and buttons ( ) Combining items in the List window List) ( Combining items in the Wave window ( Wave) Tree window hierarchical view (

List Wave

Structure, Signals, Variables,

Wave

)

• Cut/Copy/Paste/Delete

, .

•

cut/copy/paste - ^X / ^ C / ^ V .

161

• (

, ). ,

.

•

( )

• -

: ,

,

-

X- Windows

(

),

-

. : X- Windows. ё X- Windows (xterm, emacs,

•

. .). Transcript

Edit > Paste

.

•

.

Quick access toolbars(

)

Dataflow, Main, Source,

Wave .

Drag and Drop(

) HDL

.

,

,

, •

,

.

: Dataflow, List, Process, Signals, Source, Structure, Variables,

•

Wave

: Dataflow, List,

Wave ,

: List

Wave. 162

Command history(

) ;

,

.

Automatic window updating(

) :

ModelSim

Dataflow window

Process window Signals window Source window Structure window Variables window Dataflow window Signals window Structure window Variables window Dataflow window Process window Signals window Source window

Process window

Signals window Structure window

Finding names, searching for values, and locating cursors ( , , •

HDL Edit > Find : Dataflow, List, Process, Signals, Source, Structure, Variables, , .

Wave

(\)

Find , \Arch Signal 1 \,

• List

)

HDL Wave

. \\ Arch.... ,

,

Edit > Find

:

. :

•

List,

•

Wave ,

View > Goto. View > Cursor.

163

,

< < Find>>,

. (

Find

Sun). event add Tcl/Tk.

< < Find>>, ,

event add

Sorting HDL items(

HDL

Process, Signals, Structure, Variables ,

View > Sort HDL net_1, net_10,

)

net_2

Signals

Multiple window copies(

Wave, . Wave.

)

File > New Window , .

.

Saving window layout(

) ModelSim

. :

,

1 2

, . Tools > Save Preferences ( Main) modelsim.tcl . 3 " " shortcut ModelSim, ( Windows), MODELSIM_TCL, ( " Windows " ).

Context menus(

) ,

" " Windows, UNIX — 3-

(2-

,

Menu tear off(

) «

.

,

). , . , . : Dataflow, List, Main, Signals, Source,. Wave.

»( torn off), ,

,

.

Customizing menus and buttons( ,

)

,

. .

164

• "Customizing menus and buttons" ( "

") ,

• "The Button Adder" ("

")

.

Tree window hierarchical view( ) ,

ModelSim

"

" Structure, Signals, Variables,

Structure Wave. HDL

, , VHDL HDL

Verilog :

VHDL (

) ,

,

, ,

, Verilog (

) ,

,

,

,

, ,

, )

(

) ,

,

, ." ,

( . .) " .

165

,

,

,

, .

, , .

[+]

ё

+,

[-]

ё

-,

ё

Find , < control- f > (Windows).

< control-s> (Unix)

,

Edit > Find

Find .

.

,

• "Finding items by name in the List window" (" ") • "Finding HDL items in the Signals window" ( " ")

HDL

• "Finding items by name or value in the Wave window" ( " " ).

Main window(

) ,

ModelSim.

,

, ; ,

ModelSim .

Main

:

,

,

/

. 166

The toolbar provides buttons for quick access to the many common commands.

ModelSim. . ,

ModelSim. ,

.

Workspace(

) 5.5

.

, ,

/

. View > Hide/Show Workspace.

. •

Project

•

, 2- Project Library

. .

"

"

•

.

Structure .

,

" Structure window " . .

•

"

.

" Compare ,

,

. .

11 -

Transcript(

) Main

, ,

,

ModelSim. VSIM, .

ё

,

.

,

, (

"

"

).

Main 167

, Main. modelsim.ini .

TranscriptFile

modelsim.tcl

PrefMain (file) ,

TranscriptFile

modelsim.ini –

.

, . ,

File > Transcript > Save Transcript As, File , Tcl - PrefMain Save Transcript.

Transcript > Save Transcript . Save Transcript As, (saveFile). ,

,

Save.

.

,

(DO

) (DO file).

do (CR-137 )

.

The Main window menu bar(

)

ModelSim . .

New

: FolderSource-

VHDL, Verilog,

ProjectLibrary-

ё ;

Window-

"

ё

"

Open

: File ProjectDataset-

hdl .mpf WLF

Close

: ProjectDataset-

Import

: Library-

FPGA; 168

Save Delete

"Importing FPGA libraries" : Dataset: Project-

Change Directory Transcript

.mpf :

Save Transcript-

transcript Main window transcript file" (" ") Save Transcript as...-

Main "Save Transcript as"( , ), . "Saving the

Main

Clear TranscriptMain Add to Project

: File – ; see "Step 2 — Add items to the project" Simulation Configuration – , ( ) ; "Creating a Simulation Configuration" Folder – "Organizing projects ; with folders"

Recent Directories Recent Projects Quit

, ModelSim

Copy Paste Select All Unselect All Find

All Windows Dataflow

ModelSim /

Dataflow

169

List Process Signals Source

/ / / /

Structure

/

Structure

Variables

/

Variables

Wave

/

Wave

Datasets , Hide/Show Workspace Encoding.

List Process Signals Source

Dataset Browser ,

select from alphebetical list of encoding names that enable proper display of character representations used by various operating systems or file systems, such as Unicode, ASCII, or Shift-JIS , , , ASCII,

Unicode,

Shift-JIS

Properties

Compile Compile Options

HDL VHDL "Setting default compile options" : "Step 3 — Compile the files" Verilog:

Compile All Compile Order

:

"Changing compile order"

Compile Report ( ) Compile Summary

170

Simulate

Simulating

; with the graphic interface

Simulation Options Run

; "Setting default simulation options" : Run ; Simulate > Simulation Options, Run Length Run –All ; . Continuerun (CR-208) -continue Run –Next -

, run (CR-208) ; .

Step -

;

.

step (CR-220 ) Step –Over Restart -

, ;

,

,

; — ,

, , )

( restart (CR-202 )

;

.

Break End Simulation

Waveform Compare Profile

; : Profile On – 9Profile Off Profile Clear – ( View hierarchical profile(

;

) )-

; View ranked profile(

)-

; Source Coverage

; Code Coverage 171

ё Breakpoints

; "Setting file-line breakpoints"

Execute Macro Macro Helper

.do

.tcl

UNIX "The Macro Helper" Tcl , TDebug; . Debugger" TclPro Debugger Scriptics ® , TclPro Transcript File:

;

.

Tcl Debugger TclPro Debugger Options(

)

Command History: , Save File: Save Transcript As Saved Lines: ( Line Prefix: Update Rate:

"The Tcl . Scriptics

Save Transcript,

5000)

ModelSim Prompt: ModelSim VSIM Prompt: Paused Prompt: HTML Viewer:

VSIM Paused ;

Edit Preferences

Save Preferences

; http://www.model.com/resources/pref_variables/frameset.htm ModelSim Tcl; http://www.model.com/resources/pref_variables/frameset.htm

(

)

Start Comparison Comparison Wizard Run Comparison End Comparison Add

: Compare by Signal (

)-

Compare by Region(

)172

Clocks(

)-

,

Clear ( Show (

))-

Options Differences

: Wave Main Save -

,

Write Report(

)-

Rules

: Show (

)–

Save – Reload

ё

Initial Layout

Cascade Tile Horizontally Tile Vertically : Layout Style

Default –

5.5

Classic 5.5 Cascade Horizontal Vertical Icon Children

Main

Icon All Deicon All Customize

(deicon) The Button Adder(

),

173



; , Source

;

, , ;

"View menu" view (CR-261)

,

Layout Style,

. ModelSim.

Layout Style ,

ё

Tools > Save Preferences,

PrefMain (layoutStyle).

Help About ModelSim

ModelSim ( . .

)

Release Notes

notepad (CR-174) ModelSim

Enable Welcome

Welcome ,

Welcome Menu SE PDF (HTML) Documentation

ModelSim

Welcome PDF Adode ModelSim CD

ModelSim HTML; PDF Acrobat reader , www.adobe.com

Tcl Help

Tcl (

)

Windows Tcl Syntax

Tcl

Tcl Man Pages

Tcl /Tk 8.3

Technotes

HTML HTML

,

The Main window toolbar(

)

ModelSim.

174

Compile > Compile Compile HDL Source

vcom < arguments >, vlog < arguments > .: vcom (CR-250) vlog (CR-286)

Files

Simulate > Simulate

vsim < arguments > .: vsim (CR-296)

Simulate , Edit > Copy

.: " "

Edit > Paste

.: " "

Simulate > Run > Restart

restart .: restart (CR-147)

Simulate > Simulation Options

run .: : run (CR-208)

Simulate >Run > Run

run (no arguments) .: run (CR-208)

Simulate >Run > Continue

run -continue

, , ,

WLF file Run Length

.: run (CR-208)

175

Run > Run -All

-

run –all .: run (CR-208), * ."Assertions tab ( )"

Simulate > Break

Simulate >Run > Step

Step .: step (CR-220)

HDL Simulate >Run > Step -Over

HDL ,

step -over

.: step (CR-220)

The Main window status bar(

)

:

Project Now

,

(

ё "Simulating with the graphic interface", ,

Delta

(

,

)

176

Mouse and keyboard shortcuts (

) , .

, notepad ModelSim,

Notepad ( ). - UNIX

Source

- Windows

< left-button - click > < left-button - press > + drag < shift - left-button - press > < left-button - double-click > < left-button - double-click > + drag

+

< control - left-button - click > < left-button - click > ModelSim

VSIM

< middle-button -click >

none

< middle-button - press > + drag

none

UNIX < left | right - arrow >

Windows |

< control > < left | right - arrow > | < shift > < left | right | up | down arrow > < control > < shift > < left | right - arrow > < up | down arrow > (

Source, |

)

< control > < up | down > 177

| < control > < home > < control > < end > < backspace >, < control-h > < delete >, < control-d >

< backspace >

none < alt >

esc

< delete >

< alt > < F4 > < control - a >, < home > < control - b >

< home >

< control - d > < control - e >, < end >

< end >

< control - f >

< control - k > < control - n >

< control - o >

Source

( Windows)

Source

( Windows)

none

< control - p >

< control - s >

< control - f >

< F3 > < control - t >

< control - u > < control - v > PageDn

PageDn

< control - w >

< control - x >

< control - x >, < control - s> < control - y >, F18

< control - s > < control - v >

178

none

< control - a > (widget)

< control - \ > < control - ->, < control < control - Z > -/> Source < meta - "" >

none

< meta - v > , PageUp

PageUp

< Meta - w>

< control - c >

< F8 > ,

( Main) < F9> < F10 > < F11 > < F12>

;

, .

Dataflow window ( Dataflow) Dataflow

"

"

;

,

; .

;

,

,

;

.

Adding items to the window (

ё

) : 179

• • •

Navigate add button (CR-45 ) Navigate

Dataflow ,

.

: View region — Add region — View all nets — , ,

. Navigate > Expand net

, to readers.

, .

Links to other windows(

)

Dataflow

:

Main window

Dataflow, Structure,

Process window

,

Signals window Wave window

, •

Dataflow, Wave

•

Wave, Dataflow Dataflow, ,

Source window Source

Dataflow window menu bar (

Dataflow) Dataflow. (

3-

).

New Window Print Print Postscript Page setup Close

ё

Dataflow Dataflow(

Windows) / Dataflow Dataflow;

postscript ,

/ , 180

Undo ё

Redo Cut

( )

Copy

( )

Paste ( ) Erase selected Select all Unselect all ё

Erase highlight Erase all Regenerate

,

Find Find Next

Show Wave Select

,

Zoom

Pan

Default

Expand net to drivers Expand net to readers

( )

, ( )

,

181

Expand net

( )

( )

, Hide selected

Show selected

, ё

View region Add region View all nets Add ports

TM

TraceX

(X) TM

(X)

Chase X Trace next event , Trace event set Trace event reset

Load built-in symbol map Load symlib library Create symlib index

ё

.bsm "Symbol mapping" ё ё

Options

;

Dataflow

Window Initial Layout

Cascade Tile Horizontally Tile Vertically : Layout Style

Default –

5.5

Classic 5.5 182

Cascade Horizontal Vertical Icon Children

Main

Icon All Deicon All

(deicon)

Customize

The Button Adder(

),

; , Source

;

, , ;

"View menu" view (CR-261) . ModelSim.

,

Layout Style, ё

Layout Style ,

Tools > Save Preferences, PrefMain (layoutStyle).

The Dataflow window toolbar(

Dataflow) .

File > Print (Windows) File > Print Postscript (UNIX) View > Select

View > Zoom

View > Pan

Edit > Cut

Edit > Copy

Edit > Paste

183

Edit > Undo

Edit > Redo

Edit > Find

Trace input net to event -

Trace > Trace next event

,

Trace > Trace event set

Trace > Trace event reset Trace > TraceX

Navigate > Expand net to drivers Navigate > Expand net

Navigate > Expand net to readers Edit > Erase highlight

Edit > Erase all

Edit > Regenerate

none

none

none 184

none

View > Show Wave

Exploring the connectivity of your design( ) Dataflow,

"

.

"

– .

ё

/

,

,

.

, .

, ,

,

,

ё

,

,

.

,

, , ,

. ,

, ,

, : Navigate > Expand net to drivers Navigate > Expand net

Navigate > Expand net to readers

,

,

"

"

.

,

-

.

. nb

,

,

,

. Edit > Erase highlight.

185

, Dataflow

.

, window" )

,

" Wave

Wave ( ). View > Show Wave

,

Dataflow,

, ,

.

, (

"Using time cursors in the Wave window"

),

Dataflow.

Dataflow, ,

.

"Tracing events (causality)" .

Zooming and panning (

)

Dataflow . И :

186

И , Zoom Mode,

View > Zoom .

, : • •

: :

( )

• •

: : .

,

10

.

Pan Mode View > Pan.

.

Tracing events (causality)(

(

))

Dataflow

,

. " The embedded wave viewer ( ).

Dataflow ( )"

,

Dataflow ,

,

. : (

1 2 Dataflow 3

log -r / *). ,

. ,

Dataflow (

,

).

,

, . 187

;

4 ,

.

5

Trace > Trace next event.

. 6

Trace > Trace next event .

,

,

.

7

Trace > Trace set..

Dataflow "

"

(

).

, .

, .

,

,

8,

5

. ,

Trace > Trace

reset.

Tracing the source of an unknown (X)( (X)) (X). Wave – , .

: .

1 2

, (log -r /* ). Wave

3

, .

4 5 6

, , Trace > TraceX

Trace > TraceX — Trace > ChaseX — "

. Dataflow,. Trace > ChaseX. :

"

Finding items by name in the Dataflow window( Dataflow)

188

,

Edit > Find, . , (Signal), ё ,

,

a

,

(Instance),

,

(Any). Zoom To. Find Next.

Printing and saving the display(

)

a .eps

UNIX

File > Print Postscript ,

Dataflow UNIX, .

.eps :

Print Postscript

• Print command UNIX

UNIX.

• File name Postscript (.eps) .eps

; .

• Paper size . • Border width . • Font .

"Printer Page Setup" Windows Dataflow

File > Print, . :

• Name . Properties. • Status . • Type . ,

"Print to file" .

• Where 189

. • Comment . • Print to file ,

. . PostScript

, PostScript

P stscript (.ps)

.prn

. File > Print Postscript .

Postscript (.eps)

Configuring page setup(

)

Setup

Postscript (

Print

-

,

File > Page setup)).

:

Dataflow Page Setup • View Full (

)

Current View (

,

).

• Highlight ,

( )")

" Tracking your path through the design ( .

• Color Mode Color (256 (

), Invert Color (

)

Mono

).

• Orientation Landscape (

)

Portrait (

).

• Paper ,

.

Symbol mapping( Dataflow , , ,

) Verilog (

. .).

Verilog, . ,

, ,( DUname. Processname),

, -

. : xorg(only).p1 XOR org(only).p1 OR andg(only).p1 AND 190

: AND1 AND AND2 AND # A 2-input and gate AND3 AND AND4 AND AND5 AND AND6 AND xnor(test) XNOR

,

,

.

Dataflow

dataflow.bsm,

(.bsm 0

" Built-in Symbol Map).

.

, ASCII

. NlviewTM Symlib.

, www.model.com/products/documentation/nlviewSymlib.html. Dataflow

, ,

dataflow .sym ".

Nlview, DU

.

, ,

, .

: symbol adder(structural) * DEF \ port a in -loc -12 -15 0 -15 \ pinattrdsp @name -cl 2 -15 8 \ port b in -loc -12 15 0 15 \ pinattrdsp @name -cl 2 15 8 \ port cin in -loc 20 -40 20 -28 \ pinattrdsp @name -uc 19 -26 8 \ port cout out -loc 20 40 20 28 \ pinattrdsp @name -lc 19 26 8 \ port sum out -loc 63 0 51 0 \ pinattrdsp @name -cr 49 0 8 \ path 10 0 0 7 \ path 0 7 0 35 \ path 0 35 51 17 \ path 51 17 51 -17 \ path 51 -17 0 -35 \ path 0 -35 0 -7 \ 191

path 0 -7 10 0 , Entity|Module|Process ( ,

,

/

). symlib,

: . , , symlib.

Tools > Create Symbol Index, ( ,

Dataflow) .

Configuring window options(

) ,

Dataflow

,

. . Dataflow Options.

Tools > Options,

:

Dataflow Options • Keep Dataflow . • Show Hierarchy ,

.

,

,

. • Bottom inout pins -

,

. • Disable Sprout /

.

Dataflow

,

5.6.

• Select equivalent nets ,

ModelSim

. • Log nets ,

.

List window(

) , ,

.

, ,

.

192

HDL items you can view(

HDL) VHDL

Verilog HDL

: •

VHDL

•

Verilog

• ;

11 - Waveform Comparison

. •

,

:

(

)

-

List

Wave.

Adding HDL items to the List window( List ) ( List) " ).

HDL

List " Setting List window display properties ( List

. Д List Wave, or Structure.

, ,

Signals, Source, Process,Variables, List.

,

. Д

Main add list (CR-48), ;

:

add list : add list * : add list -r /* 193

Д

List List, . ,

DO

,

List.

: HDL

•

List.

•

, ( "Editing and formatting HDL items in the List window") • , File > Save Form, ( ,

,

List). List,

DO

: •

do (CR-137)

,

:

do •

List.

> Load Format List ,

:

-

; .

,ModelSim HDL,

.

The List window menu bar (

) List.

New Window

List

Open Dataset

WLF

Save Dataset WLF Load Format

DO

Save Format

List, Save Format List DO ( )

;

DO List , , Close View > New

DO List; "The Main window menu bar"

194

Cut

;

. "Editing and

formatting HDL items in the List window" Copy Paste , Delete Select All Unselect All Add Marker

List List

Delete Marker Find... Search...

List List

,

Signal Properties

, \

,

,

Goto

,

Combine Signals

; ;

" Combining items List) "

in the List window ( Window Preferences

:

, ,

Properties

,

, ,

\

,

,

Initial Layout Cascade Tile Horizontally Tile Vertically Layout Style

: Default –

5.5

195

Classic 5.5 Cascade Horizontal Vertical Icon Children Icon All Deicon All Customize

The Button Adder,

;

, ,

;

Source ;

"View menu" (CR-261)

, ,

view

Layout Style,

. ModelSim.

ё

Layout Style ,

Tools > Save Preferences, PrefMain (layoutStyle).

Editing and formatting HDL items in the List window( HDL List) ,

, List , ,, "Adding HDL items to the List

HDL,. ( window(

HDL

List)") :

,

List ,

,

. List Edit menu

. click+drag,

.

: View > Signal Properties (

List List).

, List Signal

Properties ,

,

,

. :

List Signal Properties • Signal . • Display Name List .

196

• ,

. ,

,

List .

, radix (CR-198). ,

Simulate > Simulation Options (

,

,

Main)

DefaultRadix (UM-447) modelsim.ini , , , ASCII .

.

, modelsim.tcl, ,

,

,

,

. List.

( (

) ).

• Width . . • Trigger: Triggers line( : , List. • Trigger: Does not trigger line( ,

ё

– )

:

) List. ,"

. Setting List window display properties (

List) ".

Combining items in the List window( List

List) .

, . , Tools > Combine Signals.

Combine Selected Signals

List,

:

• Name . • Order of Indexes Specifies in which order the selected signals are indexed in the bus. If set to, the first signal selected in the List window will be assigned an index of 0. If set to , the first signal selected will be assigned the highest index number. , . Ascending ( ), , List 0. Descending( ), . 197

• Remove selected signals after combining( ) , .

List ,

Setting List window display properties( ) ,

List

. , Tools > Window Preferences ( List). Properties Window Properties

List, Modify Display Triggers.

Window Properties :

Window Properties • Signal Names ,

List.

. "1"

, "0"

.

• Max Title Rows . :

• Dataset Prefix: Always Show Dataset Prefixes( ) ,

. .

• Dataset Prefix: Show Dataset Prefix if 2 or more( , 2 ) , . • Dataset Prefix: Never Show Dataset Prefixes( )

: 2 : .

Trigger List.

Triggers ,

HDL

List Trigger on: Signal Change,

,

. . .

, Signal Change

Strobe

. :

Triggers • Deltas:Expand Deltas ,

Trigger on: Signals Change , , . 198

• Deltas:Collapse Deltas . • Deltas:No Deltas (

).

• Trigger On: Signals Change .

. ,

View

,

> Signals Properties -notrigger

add list (CR-48).

• Trigger On: Strobe Strobe Period

;

First Strobe at:.

• Trigger Gating: Use Gating Expression( )

: (

1)

(

0)

Expression. • Trigger Gating: Expression , , .

,

• Use Expression Builder ( ) Expression Builder ( . . "The GUI Expression Builder"(" GUI

.

), ")

• Expression , Builder ( List ).

Expression ,

Use Expression Builder). (

• Trigger Gating: On Duration(

:

)

, ,

;

x

. ,

. List

,

. : .list.tbl config -usegating 1 .list.tbl config -gateduration 100 199

.list.tbl config -gateexpr {}

Finding items by name in the List window( List) Find Find ( List) Enter a text string and

List.

Edit >

Find.

ё, List.

(

" Setting List window display properties ( List ") Auto Wrap .

.

,

Searching for item values in the List window ( ) List.

Edit > Search List

( List ) Signal Search.

(

,

) .

• Search Type: Any Transition ( :

List. :

) ( ).

• Search Type: Rising Edge ( :

) ( ).

• Search Type: Falling Edge ( :

) ( ). 200

• Search Type: Search for Signal Value ( : ) , Value; , VHDL Verilog; . "Numbering conventions"( " " (CR-12). ,

: . see "Searching for binary signal values in the GUI( GUI) " (CR-21,)) , std_logic. • Search Type: Search for Expression ( : ) , . Builder )" Builder( GUI

Expression , "The GUI Expression . ,

. .

,

(

, , DO . "Expression syntax .

.

) " (CR-22))

• Search Options: Match Count ( :

) .

n-

n-

.

• Search Options: Ignore Glitches ( :

) VHDL

Search Results(

Verilog. .

)

Setting time markers in the List window ( Markers > Add Marker (

)

List)

. . , ,

. Edit> Delete Marker.

201

gj (

,

,

Goto)

Saving List window data to a file ( File > Write List ( :

View> Goto. .

)

List)

List

• , ns delta /a 0 +0 X 0 +1 0 2 +0 0

/b X 1 1

/cin U 0 0

/sum X X X

/cout U U U

• , @0 +0 /a X /b X /cin U /sum X /cout U @0 +1 /a 0 /b 1 /cin 0 • TSSI TSSI;

.

,

write tssi

(CR-327) 0 00000000000000010????????? 2 00000000000000010???????1? 3 00000000000000010??????010 4 00000000000000010000000010 100 00000001000000010000000010

. List,

write list (CR-323).

List window keyboard shortcuts ( List) ,

List,

: 202

< left arrow >

( )

< right arrow >

( )

< up arrow > < down arrow >



(

) (

) ( HP)

extends selection left/right

Windows UNIX

/

Find,

Process window(

ё

) ,

.

,

View > Active ,

.

Region,

, View > In .

HDL : •
,

, 203

. • < > , VHDL Verilog

ё .

• < > , VHDL . . "Ready",

. Process ,

:

Dataflow Signals Source Structure Variables

VHDL Verilog

The Process window menu bar(

Process) Process.

Process

New Window

notepad

Save List (CR-174) ModelSim Environment

Follow Context Selection ( ): Fix to Current Context(

; ): ,

Close

Process; 204

File > New > Window "The Main window menu bar"

Copy Process

Select All

Process

Unselect All

;

Find Status ( ,

,

),

Process,

:

,

Active

,

In Region

,

,

Sort

,

Initial Layout

Cascade Tile Horizontally Tile Vertically :

Layout Style

Default – Classic Cascade -

5.5 5.5

205

Horizontal Vertical Icon Children Icon All Deicon All The Button Adder ,

Customize

;

, Source

, ;

, ,

; ,

"View menu" the view (CR-261)

Layout Style,

. ModelSim.

Layout Style ,

ё

Tools > Save Preferences,

PrefMain (layoutStyle).

Signals window(

)

Signals

.

HDL

(

). HDL

. Wave ,

, (

ё

Source, ,

, Wave. Source

). List

Wave

. . . HDL

,

,

. HDL

VHDL

Verilog HDL :

VHDL 206

,

(

),

Verilog ,

, ,

( ) ,

.

"Virtual signals" ("

")

VHDL (

) . Verilog

Verilog (

.(

,

.)

ModelSim ), ( ), . "Tree window hierarchical view"( " .

(

). ")

The Signals window menu bar(

Signals) Signals.

New Window

ё

Signals ,

Save List

notepad

(CR-174) ModelSim Environment

Close

Copy

,

ё Signals; "The Main window menu bar" File > New > Window

Signals 207

Signals

Select All

Signals

Unselect All Expand Selected Collapse Selected Expand All

,

ё

ё

Collapse All

;

Force Kind (Freeze/Drive/Deposit), Delay, . force (CR-154)

force (CR-154) noforce (CR-171) , ,

Noforce HDL

;

.

Clock ,

Value,

Cancel;

, . see"Defining clock

, signals"( "

") Signals;

Find Name ;

Value,

: the search (CR-210 )

.

Source,

Signal Declaration

,

Sort

,

Justify Values ,

Filter

(

, InOut

,

)

Wave

,

,

,

,

,

,

Wave List List Log WLF

;

Breakpoints

"

" 208

Initial Layout Cascade Tile Horizontally Tile Vertically : Default – Classic Cascade Horizontal Vertical -

Layout Style

5.5 5.5

Icon Children Icon All Deicon All The Button Adder ,

Customize

;

,

, ;

,

,

;

"View menu"

,

view (CR-

261) . ModelSim.

Layout Style, Layout Style ,

ё

Tools > Save Preferences,

PrefMain (layoutStyle).

Selecting HDL item types to view( )

HDL,

View > Filter , HDL

. .

209

Forcing signal and net values(

) ,

Edit > Force . ; ,

,

force ,

force,

Edit > NoF.

. force (CR-95).

.

:

Force • Signal Name . • Value ,

,

. ,

(

VHDL

Verilog,

): base#value -or- b|o|d|h’value 16#EE

h'EE,

• Kind: Freeze ( :

,

EE.

) (unforced)

Freeze( VHDL,

modelsim.ini;

.

)Drive Freeze ,

, noforce (CR-171). ё

Verilog .

-

ModelSim s. 210

• Kind : Drive , noforce (CR-171).

ё

VHDL.

• Kind : Deposit .

ё

, ,

noforce (CR-171).

• Delay For , . • Cancel After force (CR-154)

.

• OK force (CR-154) .

OK, , ,

,

,

OK. .

Adding HDL items to the Wave and List windows or a WLF file ( HDL Wave List WLF)

Add, Signals

Wave , (WLF

List,

).

, . WLF , Wave

List

, . WLF

211

Wave

. - view , ModelSim List.

, WLF

vsim (CR-296) ,

Add: • Selected Signals ( ),

Signals

• Signals in Region ,

Structure.

• Signals in Design .

Wave , add list (CR-48), add _ wave (CR-57),,

WLF VSIM ( log (CR-164)): List,

add list | add wave | log : add list | add wave | log * : add list | add wave | log -r /* (Wave

List)

, ModelSim

,

.

Finding HDL items in the Signals window ( ) Signals, : Down

HDL Name

Value

Up.

212

. ,

ё

Signals

(

,

) .

Setting signal breakpoints(

)

" Signal breakpoints ( , ,

)"

Signal.

, . , UNIX)

Windows;

,

(2Insert Breakpoint. "Creating and

, .

managing breakpoints( .

)"

Defining clock signals(

) ,

Edit > Clock ,

,

, .

, .

, ,

,

- std_logic, std_ulogic, , 1 0

, ,

:

,

verilog, ,

verilog,

1213

,

0-

.

, .

Source window(

)

Source

HDL

.

, Source

,

. ,

Structure File > Open (

Source) ,

security and -nodebug ( ,

Main .( " Source code

; –nodebug) " . .

:

• • •

-

, –

–

• •

Process ;

, -

,

. ,

Edit > read only.

The Source window menu bar (

Source) Source.

New

(VHDL, Verilog

)

Open Open Design Source Close File

,

Use Source

, ; ;

Source Directory

SourceDir modelsim.tcl

Save Save_As Print 214

Close

Source

,

,

read only

Edit.

: Undo, Cut, Copy, Paste, Select All, Unselect All

Clear highlights Comment Selected

, ,

Uncomment Selected Find ; Find Next

ё

, Find

Replace

,

Previous Coverage Miss Next Coverage Miss read only

Code Coverage, , Code Coverage, ,

Show line numbers Show coverage data

(

)

,

Code Coverage Show language templates Properties

; ,

,

,

Examine

HDL

;

examine (CR-148); Describe

HDL

;

describe (CR-133); Compile Breakpoints

HDL ,

,

-

, 215

" Creating ; and managing breakpoints (

)"

Options

Source;

Colorize Source Highlight Executable Lines Middle Mouse Button Paste Verilog Highlighting VHDL Highlighting Freeze File

,

/

,

, VerilogVHDLSource ( Source; )

Structure, Freeze View Process Auto-Indent Mode

Initial Layout Cascade Tile Horizontally Tile Vertically : Layout Style

Default – Classic Cascade Horizontal Vertical -

5.5 5.5

Icon Children Icon All Deicon All Customize

The Button Adder ,

; ,

,

, ; 216

,

; "View menu"

,

view (CR-261) Layout Style,

. ModelSim.

Layout Style ,

ё

Tools > Save Preferences,

PrefMain (layoutStyle).

The Source window toolbar(

Source) Source

ModelSim. Source

Tools > Compile

Compile this file

vcom VSIM

vlog Compile HDL Source

:

vcom (CR-250)

vlog (CR-286) File > Open

Open Source File

HDL ,

Open File ( Source Source) Save Source File

File > Save

Source Print

File > Print

Print

Cut

Edit > Cut

. : " Mouse and keyboard shortcuts ( )"

Edit > Copy

. : " Mouse and keyboard shortcuts ( )"

Edit > Paste

. : " Mouse and keyboard shortcuts ( )"

Source Copy

Source Paste

Undo

Edit > Undo

217

Find

Edit > Find

(Windows) (UNIX)

Main: Simulate > Run > Restart

restart


.: restart (CR-202) , , , WLF Run Length

Main: Simulate > Simulation Options

run


.: run (CR-208) Run ё Continue Run

Main: Simulate ¾ Run

run
Run > Continue

run -continue

>

.: run (CR-208)

.: run (CR-208)

Run -All

Main: Simulate > Run > Run -All

run -all

, .: run (CR-208) ; tab"

. "Assertions

Main: Simulate > Break

Break

: Simulate > Run > Step

Step

.:

step VSIM step (CR-220)

HDL Step Over

:

step -over 218

HDL

Simulate > Run > Step -Over

VSIM step (CR-220)

.:

,

ё

View > Show Language Templates

Show Language Templates

Setting file-line breakpoints( "

-

-

) "

Source,

.

Source, . ,

-

;

,

. , Remove Breakpoint.

, :

• Disable/Enable breakpoint . • Edit breakpoint ,

;

" Adding a Breakpoint( • Edit all breakpoints "

)"

.

".

Checking HDL item values and descriptions ( HDL

) HDL

,

Source: •

, Source

Tools > Examine

•

Tools > Description

, . examine (CR-148), -

describe (CR-133)

.

219

Finding and replacing in the Source window( Source) Find Source. Find.

Edit > Find Edit > Find,

Edit > Replace , Replace

. Find.

, Replace.

-

.

Regular expression .

Setting tab stops in the Source window and Main window Transcript ( Source Main) Source

Main , Tcl

Edit Preferences PrefSource(tabs) . GUI. Tools > Edit Preferences (Main window).

1 2

By Name.. Source,

3 4

"tabs".

Change Value.

5

,

,

"n"

,

n ,

, .

:

( .

)

c, cm m, mm i, in p u char, chars 220

, . : • •

5, 10c,

5

. 10

•

.

,

: 21 49 77 105 133 161 189 217 245 273 301 329 357 385 413 441 469 : {21 49});

ё

(

, " 21 49 "

GUI.

221

Structure window( :

)

ModelSim

5.5

,

Structure Structure , Structure

, Main. Structure

. Main).

View > Structure (

. . ,

, –nodebug)".

HDL .( . see "Source code security and -nodebug(

HDL HDL

VHDL

Verilog Structure. VHDL ( )

, ,

, Verilog (

) ,

, ,

,

(

)

, . "Virtual Objects (User-defined buses, and more)( ( , ) ") .

, , "+"

"-".

"+" -

.

.

Structure , Structure.

"-"

.

, 222

Structure Structure

,

:

• , . • ,

.

• ,

;

Source

(

Verilog).

Structure, Signals .

, ,

, ,

,

, ,

. Structure, In Region Variables.

Process ;

Process

The Structure window menu bar(

) Structure. Structure

Main.

New window Save List Environment

Close

Copy Expand Selected Collapse Selected Expand All Collapse All Find

ё

Structure notepad

(CR-174) ModelSim 1) ;2) ;3)

,

,

Structure

Structure

ё

ё

, ;

. 223

"Finding items in the Structure window"( " ")

Sort

,

,

Initial Layout Cascade Tile Horizontally Tile Vertically : Default – Classic Cascade Horizontal Vertical -

Layout Style

Icon Children Icon All Deicon All Customize

5.5 5.5

The Button Adder , ; ,

,

, ;

,

;

"View menu" the view (CR-261)

,

Layout Style,

. ModelSim.

Layout Style ,

ё

Tools > Save Preferences, PrefMain (layoutStyle).

Structure window context menu( Structure

, , UNIX-3-

(Windows-2-

Structure) , )

-

Structure

. Structure

.

• View Source Source. . • Add Dataflow, List

Wave

• Sort HDL

Structure

(

), • Find he Find .

"Finding items in the Structure window"

. 224

• Expand Selected HDL

.

• Collapse Selected HDL

.

• Expand All HDL

.

• Collapse All HDL

.

• Save List HDL

Structure

.

• Save Dataset WLF e. • End Simulation .


Structure • Close

.

Finding items in the Structure window( ) Find Edit > Find (

.

Structure Structure)

Find.

Find . , ,

/ . , .

Auto

Wrap, .

Variables window( Variables HDL

) . .

( )

. .( . see "Source code security and -nodebug"( "

, -nodebug " ).

HDL 225

HDL VHDL Verilog Variables. VHDL , generics(

),

Verilog

VHDL (

) .

Verilog. (Verilog , .) ModelSim, ( ) ( ё ). . See "Tree window hierarchical view"( " ") . VHDL Verilog, .

,

, ,

Edit >Change (

,

) .

,

" , VHDL

(

" VHDL Verilog. . ). . Process,

,

Variables.

The Variables window menu bar(

) Variables.

New window Save List Environment

ё

Variables ,

notepad

(CR-174) ModelSim Follow Context Selection ( ): Fix to Context(

Process; ):

, 226

Variables

Close

Variables

Copy

Variables

Select All

Variables

Unselect All Expand Selected Collapse Selected Expand All

,

ё ё

Collapse All

HDL

Change

;

Find Name ;

Value,

:

,

Sort

,

Justify Values

Wave/List/Log

Selected Variables Wave, List,

Variables in Region WLF

Initial Layout Cascade Tile Horizontally Tile Vertically Icon Children : Layout Style

Default – Classic Cascade -

5.5 5.5

227

Horizontal Vertical Icon All Deicon All The Button Adder ,

Customize

; ,

,

, ;

,

;

"View menu" (CR-261)

,

the view

Layout Style,

. ModelSim.

Layout Style ,

ё

Tools > Save Preferences, PrefMain (layoutStyle).

Finding HDL items in the Variables window( Variables )

Ч

Variables, Value

Name : Down

.К , ,

HDL

Up.

Variables

,

ё

Wave window(

)

, .

, ,

,

HDL

.

.

.

, .

Pathname pane(

) .

, ё

, . . 228

.

( . Splitting Wave window panes(

Wave)).

Values pane(

) . ,

,

, ,

, ,

ASCII

. ,

( options"( "

)(

Simulate > Simulation Options . see "Setting default simulation " )).

Signals,

, , (

)

.

Waveform pane(

) , .

20

.

, ,

,

.

,

, .

. , .

. Wave Window Properties (

Cursor panes(

. ." Setting Wave window display properties " )

) 229

. . . "Using time cursors in the Wave indow(

.

20

Wave )"

HDL items you can view( HDL

)

VHDL (

)

Verilog (

) ,

,

(

)

, , "Virtual Objects , (User-defined buses, and more) ( ( .

(

,

. .) "

) ;

:

, generics,

.

11-

Waveform

-

List

Wave . , ,

, ,

.

230

, ,

.

,

, . , .

Format menu. , , (

, . "Adding items with a Wave window format file )".

Adding HDL items in the Wave window( Wave) ( Wave" ).

HDL

Wave . "Setting Wave window display properties( Wave

.

Wave Structure, Wave.

Variables.

List, Process, Signals, Source, ,

,

,

.

HDL

,

(

): VSIM>add wave : VSIM>add wave * : VSIM>add wave -r /* Wave Wave .

: 231

1

,

Wave

2 the Wave window(

, ,

.

. "Editing and formatting HDL items in HDL Wave )",

. 3

,

File > Save Format ( Wave). Wave,

,

DO

: •

DO (CR-137)

,

:

VSIM>do •

File > Load Format (

Wave)

Wave

:

-

,

Wave,

; .

Edit > Select All Edit > Delete, delete (CR-132 )

wave.

The Wave window menu bar( .

)

-

, Wave

New Window

ё

Wave

Open Dataset WLF

Save Dataset Wave .DO

Save Format .DO (

);

Wave,

,

,

.DO (.DO) Save Format

Load Format

Wave, , ;

Page Setup , Print (Windows only)

,

, Wave

,

: ,

, ;

: All signals Current View Selected 232

Print Postscript Postscript; All signals Current View -

:

Selected Close

Wave; "The Main window menu bar(

View > New )"

Wave;

Cut see "Editing and formatting HDL items in the Wave window( HDL

. )"

Copy Paste Delete Edit Cursor Delete Cursor Delete Window Pane Select All Unselect All

,

,

Find Search ;

, . "Searching for item

values in the Wave window"

Zoom

: Full, In, Out, Last, ё

Range ), ,

Mouse Mode Source,

Signal Declaration Cursors Bookmarks

, , ;

Sort ; Justify Values

233

Refresh Display

Wave,

Signal Properties

,

, ,

,

,

( Format,

)

Divider Group

-

,

, (

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;

Breakpoint breakpoints(

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Bookmark ; bookmarks(

." Saving zoom range and scroll position with )"

Cursor Window Pane

, waveset

Radix -

Format Literal, Logic, Event,Analog Color Height

Waveform Compare Breakpoints

Bookmarks

;

.

, , Creating and managing breakpoints ( )" , , ё zoom range and scroll position with bookmarks (

;

;

."

. " Saving )" WLF

Dataset Snapshot Combine Signals ,

Window Preferences

,

,

,

,

234

Start Comparison Comparison Wizard Run Comparison End Comparison :

Add Compare by Signal Compare by Region Clocks-

,

Options :

Differences Clear Show-

Wave

Save-

,

Write Report:

Rules Show-

,

SaveReload

Initial Layout Cascade Tile Horizontally Tile Vertically : Layout Style

Default – Classic Cascade Horizontal Vertical -

5.5 5.5

Icon Children Icon All Deicon All 235

The Button Adder ,

Customize

;

,

,

,

,

; ;

"View menu"

,

view (CR-

200) Layout Style,

. ModelSim.

Layout Style ,

ё

Tools > Save Preferences,

PrefMain (layoutStyle).

The Wave window toolbar(

Wave)

Wave

ModelSim

.

Wave

File > Load Format

Load Wave Format (DO)

do wave.do .

Wave ,

Save Format Save Wave Format Wave DO (

-

do (CR-137)

File > Save Format

)

Print Waveform

File > Print

Wave ,

Cut

Edit > Cut > Cut

Wave

Copy

Edit > Copy > Copy

Paste

Edit > Paste > Paste

Add Cursor

Insert > Cursor wave

236

Edit > Delete Cursor

Delete Cursor

Find Previous Transition

Find Next Transition

wave

Edit > Search (Search Reverse)

: Shift + Tab left . left (CR-162)

Edit > Search (Search Forward)

: Tab right . right (CR-206)

View > Mouse Mode > Select Mode

Select Mode

View > Mouse Mode > Zoom Mode

Zoom Mode

View > Zoom > Zoom In

Zoom in 2x 2

:iI +

View > Zoom > Zoom Out -

Zoom out 2x 2

View > Zoom > Zoom Full

Zoom Full

> Zoom In :oO

> Zoom Out :f F

> Zoom Full .wave.tree interrupt

Stop Wave Drawing

, Wave :

Restart ,

Simulate > Run > Restart

,

restart .: restart (CR-202)

,

WLF :

Run ,

Simulate >

run VSIM 237

Run > Run

.: run (CR-208)

: Simulate > Run > Continue

Continue Run

run continue VSIM .: run (CR-208)

:

Run -All ,

run - all

Simulate > Run > Run -All

ё

VSIM .: run (CR-208), "Assertions tab ( )"

Break

Using Dividers(

) ,

,

Insert > Divider ( , .

,

).

,

.

"New Divider." , "Gold." . . , (

, ),

,

.

To move a divider— To change a divider’s name and size — (UNIX)

(Windows) Divider Properties ,

To delete a divider—

Delete

Splitting Wave window panes( ё

Wave)

,

, Insert > Window Pane (

Wave . Wave) .( .)

238

,

, " sim ",

–

"gold." Гл

7 - WLF

лы (

ры д

ы )

, virtuals.

Combining items in the Wave window ( Wave) Wave . -

. , Wave Tools >Combine Signals. Combine Selected Signals : • Name

• Order of Indexes . 0.

Ascending, Descending , .

,

• Remove selected signals after combining , . , Bus1. Wave . ё , .

Wave

Wave , , .

)

Wave . "Virtual Objects (User-defined buses, and more)( , ) )" Wave.

(

239

Editing and formatting HDL items in the Wave window ( HDL HDL, .(

. Wave" ).

Wave)

Wave, , "Setting Wave window display properties(

:

Edit click+drag,

. Wave.

,

,

,

: • Control+click,

:

•

: ,

:

,

View > Signal Properties ( Wave Signal Properties

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Compare. :

View • Display Name (

)

.

• Radix ( ). , ,

, radix ,

Symbolic.

• Wave Color .

,

. • Name Color .

,

. (

Format ):

240

• Format: Literal ,

(

).

-

,

. • Format: Logic U, X, 0, 1, Z, W, L, H, or -. • Format: Event . • Format: Analog [Step | Interpolated | Backstep] .

. (Backstep) backstep

.

.

,

ё

-

. .

(

1)

(

1)

. Analog: VHDL: - std

,

,

,

Verilog:

• Height (

)

. .

Compare "Adding signals, regions and/or clocks" ). Options (

Add Signal

Setting Wave window display properties ( Wave) Wave ,

Tools > Window 241

Preferences ( Preferences (

Wave) . Main).

,

Tools > Save

:

Window Preferences • Display Signal Path , ( , sim:/top/clk)

(

, sim:clk). .

, - Full Path( ). SignalNameWidth. "Preference variables located in Tcl files"

,

Tcl

.

• Justify Value , . • Snap Distance , (0

).

• Row Margin . • Child Row Margin . • Waveform Popup \

,

,

• Dataset Prefix , Always Show Dataset Prefixes(

. )

("sim"). Show Dataset Prefixes if 2 or more( )

, ,

2

2

.

" sim " -

.

Never Show No Dataset Prefixes( ) .

,

.

Sorting a group of HDL items(

HDL)

View > Sort,

Setting signal breakpoints( "Signal breakpoints (

) )"

Wave. 242

,

,

,

. ,

(2-

Windows; 3-

, UNIX),

Insert Breakpoint. " Creating and

. managing breakpoints ( .

")

Finding items by name or value in the Wave window( Wave) Edit > Find (

Find Wave)

Wave. Find.

Name Value, Find .

ё

Wave. Auto Wrap ( ) . .

Searching for item values in the Wave window ( Wave) Wave, Wave Signal Search.

Edit > Search ,

243

:

Wave Signal Search (

)

,

. : • Search Type: Any Transition ( : ) ( ). • Search Type: Rising Edge(

) ( ).

• Search Type: Falling Edge(

) ( ).

• Search Type: Search for Signal Value( , Value; , VHDL Verilog conventions ( ) " (CR-12).

) . "Numbering

;

,

: . "Searching for binary signal values in the GUI(" GUI) " (CR-21) , std_logic. • Search Type: Search for Expression( , . "The GUI Expression Builder(

) Expression Builder, GUI)"

.

, Wave. DO syntax (

,

.

,

• Search Options: Match Count( n-

. )

n-

; Match Count ,

Search Results(

.

)" (CR-22)

, . "Expression

)

. .

Using time cursors in the Wave window( Wave)

244

Wave .

,

,

.

, Add Cursor, ; , ).

Insert > Cursor ( . Delete Cursor,

(

). Edit> Delete Cursor

Add Cursor

Delete Cursor

Finding a cursor(

) . View > Cursors. .

, ,

Making cursor measurements(

) ,

.

, . ModelSim

, . ,

ё

, .

, . .

-

, 10 Window Preferences(

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.

Find Previous Transition

Find Next Transition

:

245

Zooming - changing the waveform display range( ) . ,

,

,

,

. Zoom

View

, .

:

Zoom • Zoom Full(

) ,

0 .

• Zoom In(

) , .

• Zoom Out(

) , .

• Zoom Last(

) , .

• Zoom Range (

) , ,

.

, Zoom in 2x

: Zoom out 2x

Zoom Full

Zoom Mode , zoom ; 0

246

View > Mouse Mode > ZoomMode ( 3 : • Down-Right: Zoom Area (In)( • Up-Right: Zoom Out( : • Up-Left: Zoom Fit( : )

, Wave).

zoom , ()

– ё

:

) )

ё

, .

10

,

. ,

,

. " Wave window keyboard shortcuts(

Wave )" Wave .

Saving zoom range and scroll position with bookmarks ( ) .

. ,

Bookmark. Wave window format file( , ё . ,

Wave (

" Adding items with a Wave)")

. . bookmark add wave (CR-64 ) Insert > Bookmark ( Wave).

Bookmark Properties

.

.

• Bookmark Name , ё View > Bookmarksmarks.

.

• Zoom Range , . • Top Index , 15, Wave

. ,

15-

, .

• Save zoom range with bookmark . 247

• Save scroll location with bookmark . ,

View > Bookmarks, . Tools > Bookmarks ( Wave).

Wave ,

Bookmark Selection • Add (

. )

• Modify

• Delete (

• Goto (

)

) Wave,

Wave window mouse and keyboard shortcuts (

Wave)

,

Wave.

a

< control - left-button - drag down and right> < control - left-button - drag up and right> < control - left-button - drag up and left> < middle-button - drag>

zoom fit( ё ) moves closest cursor ( )

< control - left-button - click on a scroll arrow > (

) ( )

< middle mouse-button - click in scroll bar trough> (UNIX)

a. Mode > Zoom Mode,

,

View > Mouse .

248

i I or +

( )

o O or -

( )

f or F

( )

l or L

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r or R

( )

< up arrow >/

, /

/

;

, \ ,



, ,

(

(

Windows

UNIX

)

-

)

-

; ( ) ,

,

,

,

Printing and saving waveforms( ) a .eps

.eps

UNIX

File > Print Postscript ( Wave) Wave UNIX, .(

write wave (CR-329)). ,

.

249

:

Write Postscript

•

Print UNIX,

UNIX

.

• File name Postscript (.eps), .eps

; .

• All signals . • Current View . • Selected

• Full Range . • Current view . • Custom .

. "Printer Page Setup(

)" Windows

250

File > Print ( Wave,

Wave)

(

). ,

.

• Name .

• Status . • Type . ,

,

"Print to file".

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) ,

Postscript

. , (.ps),

. File > Print Postscript.

.

Postscript .prn (.eps)

251

• All signals . • Current View . • Selected .

• Full Range . • Current view . • Custom .

. "Printer Page Setup(

Setup

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Write Postscript ( File > Page setup).

Print , ,

• ; . • );

Margin

Scale

Page.

• Auto Adjust ,

, .

• . • . • ,

-

.

252

• –

Fixed ; , ;

Fit to,

,

–

. • , Portrait

Landscape.

Compiling with the graphic interface ( ) VHDL

Verilog ,

)". Compile (

Compile HDL Source Files, . " Getting started with projects ( Compile HDL Source Files, Compile >

Main). Compile HDL Source Files

• • •

:

, VHDL

Verilog ,

Default Options, default compile options( . Compiler Options Compile > Compile Options ( ) Project.

. "Setting )" ,

Compile Properties

Edit Source, . "Source window(

Compile.

)" .

Locating source errors during compilation( ) , .

, Source

.

Setting default compile options( ) 253

),

Compile > Compile Options ( Compiler Options . Compiler Options .

,

,

VHDL

VHDL •

: 1993

VHDL93 .

, VHDL93

. 1987vcom (CR-250).

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.

, . , –nodebug(

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Simulating with the graphic interface( ) , Simulate,. ё . Simulate, Simulate >, Simulate ( Main). - Design, VHDL, Verilog, Libraries, SDF, Options . , ,

Library

Library

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Load. ,

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Design • Simulate ( )

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.

Verilog

VHDL :

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( .

,

,

)

,

/

: [ < Library_name >.] 257

-

,

-

Add.

,

(

). • Simulator Resolution (-time []) (

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VHDL tab(

VHDL)

:

VHDL Generics(

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)

Add

(

), ;

Generics. ,

Delete

Edit.

. Specify a Generic . • Generic Name (-g ) . 258

VHDL (

).

• Generic Value

(

)

(

). .

( )

.

• Override Instance - specific Values ( -

)(-G < Name=Value >) ,

.

, Override

. Generics.

VITAL

• Disable Timing Checks (

) (+notimingchecks) ,

•

VITAL.

VITAL 2.2b SDF (-vital2.2b) SDF VITAL 2.2b (

• Disable Glitch Generation (

– Vital2000).

)(-noglitch) VITAL.

TEXTIO • STD_INPUT (-std_input < , Browse • STD_OUTPUT (-std_output < , Browse

>) VHDL

textio STD_INPUT. .

>) VHDL textio STD_OUTPUT. .

259

Verilog tab (

Verilog) :

Verilog И

• Disable pulse error and warning messages (

) (+no_pulse_msg) .

• Rejection Limit(

) (+pulse_r / < percent>) .

• Error Limit(

) (+pulse_e / < percent >) .

Д • Enable Hazard Checking (

) (-hazards) Verilog.

• Disable Timing Checks in Specify Blocks ( )(+notimingchecks)

ё ($setup, $hold, ...)

ё

.

• Delay Selection(

) (+mindelays | +typdelays | +maxdelays) ,

min:typ:max. • User Defined Arguments ( “ +” , Verilog PLI mc_scan_plusargs. , ModelSim

) (+ < plusarg >) ,

"+" . 260

Libraries tab(

)

:

Libraries • Search Libraries (-L) ,

Verilog.

• Search Libraries First (-Lf) Search Libraries, ).

SDF tab(

‘ uselib(

SDF)

SDF(

)

SDF ё

Add ,

SDF

,

;

Region/File. ,

(

). .

Add SDF File • SDF

([] = ) SDF , .

.

• Apply to region ([] = ) ,

Browse,

SDF.

• Delay (-sdfmin | -sdftyp | -sdfmax) max), simulation(

SDF. SDF

(min, typ , "Specifying SDF files for

. )" .

SDF

261

• Disable SDF warnings SDF (-sdfnowarn) SDF. • Reduce SDF errors to warnings SDF SDF

(-sdfnoerror) ,

.

• Multi-Source Delay (-multisource_delay < sdf_option >) ,

. , .

(Module Input Port Delay-MIPD) SDF . .

Options tab(

, ,

)

:

Options • Enable source file coverage

(-coverage) .

(К

10 - Code Coverage

).

• Treat non-existent VHDL files ... ( (-absentisempty) VHDL , ModelSim

VHDL

)

, .

• Do not share file descriptors... ( (-nofileshare) ModelSim

) VHDL .

,

,

. • WLF File (-wlf ) (WLF)

..

- vsim.WLF. • Assert File (

modelsim.ini (

)(-assertfile ) , " Creating a transcript file (

. TranscriptFile )" ).

• Other options vsim (CR-296). 262

Setting default simulation options( ) Simulate > Simulation Options ( Simulation Options, . :

,

)

Simulation Options – . , modelsim.ini;

,

.

: • Default Radix

.

radix (CR-198), . ,

. (CR-154), examine (CR-148), change (CR-72)Signals, Variables, Dataflow, List,

DefaultRadix

modelsim.ini (force

) Wave.

• Suppress Warnings From Synopsys Packages, Synopsys std_arith. StdArithNoWarnings modelsim.ini , . From IEEE Numeric Std Packages, numeric_std and numeric_bit. NumericStdNoWarnings modelsim.ini , . • Default Run Run 263

RunLength modelsim.ini .

.

,

• Iteration Limit

, IterationLimit

. ,

modelsim.ini .

• Default Force Type . DefaultForceKind modelsim.ini .

,

:

Assertions • Break on Assertion

, BreakOnAssertion

.

,

modelsim.ini

.

• Ignore Assertions For ,

.

. IgnoreWarning, IgnoreNote modelsim.ini .

IgnoreFailure, IgnoreError, ,

,

,

(

).

:

, , . WLF :

WLF Files • WLF File Size Limit WLF WLF

(

)

. , WLFSizeLimit modelsim.ini .

, 0.

.

,

264

• WLF File Time Limit WLF WLF

(

)

.

, .

, WLFTimeLimit modelsim.ini .

. • Compress WLF data WLF WLF,

0. ,

. .

WLFCompress .

,

modelsim.ini

• Delete WLF file on exit WLF , WLF , WLFDeleteOnQuit modelsim.ini

. ,

• Design Hierarchy ,

WLF .

WLFSaveAllRegions .

,

modelsim.ini

Creating and managing breakpoints( ) ModelSim

,

(

,

)

-

.

GUI .

Signal breakpoints(

) (

,

) .

(

when (CR-312) , , .

ModelSim , ). Main

when (CR-312), VSIM >. К

,

. GUI 265

Signals , —UNIX),

3-

(2Insert Breakpoint

Wave. - Windows, .

Breakpoints. Breakpoints .

File-line breakpoints(

-

)

-

, .

,

.

bp (CR-68), VSIM>.

-

К

.

Source.

GUI ,

ё

Source, . -

;

,

. , Breakpoint.

, -

Remove Breakpoints.

Breakpoints dialog(

)

Breakpoints File-line breakpoints. Tools > Breakpoints Wave, .

Signal breakpoints Main,Signals, Source,

:

Breakpoints • Breakpoints

. GUI,

,

.

, • Add

ё

’X‘ .

-

. • Modify . • Disable/Enable . 266

• Delete . • Label .

• Condition . • Command , Д ё Add Add Breakpoint.

,

Next. , .

,

,

. :

Signals Breakpoints • Breakpoint Label

. • Breakpoint Condition ( ), . • Breakpoint Commands ( ), ModelSim Tcl run (CR-208)

(

),

when (CR-312) . ,

. ,

-

.

File Breakpoints • File

• Line . . • Instance Name , . 267

• Breakpoint Condition , • Breakpoint Commands ( ), ModelSim run (CR-208)

.

,

.

Tcl

,

-

.

Miscellaneous tools and add-ons( ) ModelSim.

.

• GUI Edit > Search > Search for Expression > Builder ( Wave List "GUI_expression_format(

Wave)

. GUI)" (CR-18).

• View > Show language templates ( VHDL • Window > Customize (

List

Source) Verilog

)

. • Tools > Macro Helper ( , UNIX ( Linux). • Tcl Tools > Tcl Debugger (

Main) .

Main) Tcl

• Debug Detective ™ Debug Detective -

, ,

(IBD ™),

,

. , ,

, ,

-

-

. 268

ModelSim. Debug Detective, ModelSim ,

. Start Menu , www.mentor.com/hdldesigner/ debug/detective .

Debug Detective, .

The GUI Expression Builder ( GUI) GUI(GUI Expression Builder) Wave List Signal Search, ). "GUI_EXPRESSION_FORMAT" (CR-18).

List trigger properties( ,

: •

Edit > Search (

List

Wave)

•

Search for Expression

•

Builder

EXPRESSION BUILDER , GUI . , , , Wave List Insert Reference Signal Expression Builder. , . Expression Builder "Expression syntax( )" (CR-22). ,

Signal

ё

==.

&&

Insert Selected

AND Wave

’ rising.

ё

Wave,

. ё

Insert Selected Signal . 269

. "Expression syntax(

( )" (CR-22)),

.

"Configuring a List trigger with Expression Builder( List )" .

Language templates(

)

ModelSim

Verilog (wizards) , ,

, :

, ,

VHDL. , . .

,

HDL

.

" VHDL

.

" Verilog, ,

HDL. , File > New ( Source) View > Show language templates . .

,

HDL .

, ,

,

, Verilog

VHDL

Source,

. ,

. ,

. HDL

, ,

.

. .

,

, "

".

,

.

. ё .

,

(

, "block_label" ,

)

. , .

,

"block_declarations" , .

" DELETE ". HDL,

.

270

(

) .

The Button Adder (

)

ё

Button Adder

ё ModelSim.

,

,

, , ( "Making the button persistent( Button Adder ModelSim: Window > Customize

)"

).

: •

, .

•

-

• Run

Step

, ModelSim. Wave.

,

: • Toolbar

.

• Footer(

)

. /

: • Right

/

• Left

.

/

• Top

.

/

.

• Bottom .

/

Button Adder, .

, .

1

,

:

Button Adder.

271

Tcl modelsim.tcl

2 modelsim.tcl

, MODELSIM_TCL

modelsim.tcl

3 Tcl user_hook http://www.model.com/resources/pref_variables/frameset.htm Tcl . .

. .

.

,

Wave, Wave.

: _add_menu wave controls right SystemMenu SystemWindowFrame AddWaves {add wave *}

Tcl PrefWave (user_hook). :

modelsim.tcl modelsim.tcl

proc AddWaves winname { _add_menu wave controls right SystemMenu SystemWindowFrame AddWaves {add wave *} } lappend PrefWave(user_hook) AddWaves

,

ModelSim "AddWaves" ,

Wave, "add wave *".

The Macro Helper ( ) UNIX ( Macro Helper

Linux).

,

, . play (CR-181) .

, Macro Helper ,

( ,

,

, GUI ModelSim , ). Macro Helper,

run (CR-208) .

Tools > Macro Helper (

)

. Macro Helper

• Record a macro , Record. Pause

Stop .

• Play a macro 272

Macro Helper ,

Play.

Macro Helper

notepad (CR-174).

Record/Stop

,

Insert Pause

.5 ,

Play

; ;

Macro Helper,

.

macro_option (CR-168 )

, .

The Tcl Debugger ( Tcl

)

Gregor Schmid . ,

TDebug , ,

; .

Tools > Tcl Debugger ( ModelSim TDebug

)

.

,

,

. TDebug

Help > Technotes > tdebug. README

,

TDebug.

Tdebug ‘td_eval( )’

Tcl/Tk, . . TDebug

, ,

, ,

,

, ,

. .

. . . Tcl’

,

. 273

. .

TDebug. , TDebug . , , vsim.op _.

Tools> Tcl Debugger (

)

.

. ,

ё

ё . ,

ё . ,

ё

, . ,

(Exit) TDebug. vsim.op _, .

TDebug

Popup Chooser,

(Rescan) ,

Popup ModelSim,

.

274

,

(Proc), (Result) (Variables)

, ,

Eval .

, , ) (

,

. (< -1 >, Selection >Restore Proc

, Selection > Prepare Proc ^P ^R). ‘Prepare’( , (

)

‘Restore’( .

,

), )

, ,

.

,

. ! ‘switch (

‘bind (

)’

)’,

, , . ,

(

)’

‘waiting(

‘idle

)’ ,

.

:

,

Stop

,

slow/fast/nonstop ,

Next Slow

, ; ‘ ‘+’

,

’;

‘-’ ,

Fast Nonstop Break

ё ,

,

‘ wmwithdraw( , Debugger > Close.

)’. .

275

/

,

.

, .

ё

.

Eval

,

. ; .

.

, . , Variables (

ё

‘global td_priv ’ , , ).

TDebug, .tdebugrc . . TDebug README Help > Technotes > tdebug TDebug. TclPro Tools TclPro Scriptics . ё ,

, TclPro: 1

Scriptics.

ё

2.

TclPro,

3

ModelSim

,

TclPro Remote Debugging Tools > TclPro Debugger (

Main) 276

,

4 ,

,

TclPro

1.4

. .

ModelSim.

Graphic interface commands( ) , .

; . ModelSim ModelSim).

К

Command Reference(

batch_mode (CR-62)

1, 0;

,

ModelSim

configure (CR-110) List

List Wave

Wave

down (CR-138)

List , Wave

getactivecursortime (CR-157) getactivemarkertime (CR-158) left (CR-162)

List Wave

notepad (CR-174) play (CR-181)

; ASCII Linux) -

UNIX (

property list (CR-193)

HDL

property wave (CR194)

HDL

record (CR-199)

,

, record (CR-199) List

Wave UNIX (

Linux) -

right (CR-206)

Wave

search (CR-210)

ё

seetime (CR-214)

List

, (

transcribe (CR-226)

)

Wave, , 277

up (CR-229)

List ,

write preferences (CR324)

GUI Tcl

Add button (CR-45) Add_menu (CR-51) Add_menucb(CR-53)

ё

ё

Add_menuitem (CR54) Add_separator (CR-55) Add_submenu (CR-56)

ё

,

Change_menu_cmd (CR-73) Disable_menu (CR-136) Disable_menuitem (CR-136) Enable_menu (CR-145) Enable_menuitem (CR146)

-

ё ,

ё

,

;

ё ; , ModelSim

, ModelSim -

278

9 - Performance Analyzer (

Under(%)

)

In(%).

279

, ,

.

-

,

-

, .

,

ASIC

FPGA

.

Introducing Performance Analysis (

) ,

ё ,

ModelSim

.

. . ,

.

•

VITAL

•

,

ё

•

-

,

•

, . ,

VHDL

Verilog,

. 280

A Statistical Sampling Profiler ( ) . ,

,

. ,

,

,

, .

, ,

,

,

. ,

.

,

-nodebug

vsim,

.

,

Samples ,

.

Getting Started (

)

Performance Analyzer, , , run, ,

(

run ModelSim . Tools > Profile > Profile On ( Main). , run . ё Performance Analyzer , .

Performance Analyzer, run ModelSim,

Main).

Tools > Profile > Profile Off ,

. . ON, ,

,

Tools >Profile > Clear Profile Data (

run , . Main ).

281

Interpreting the data(

) , /

.

, 60 % ,

, X.

,

X

,

.

,

, Y,

X, 25 %

30 % 20 %

Z.

, . , ,

, 1%

.

, ,

.

Viewing Performance Analyzer Results ( ) Performance Analyzer

– , Tools > Profile > ) view_profile VSIM. , Tools > Profile > View ranked profile view_profile_ranked VSIM. , view_profile VSIM.

. View hierarchical profile (

Hierarchical Profile ,

, , /

’- ’,

. ’+‘,

.

.

, ,

. (store.vhd:43

retrieve.vhd:35)

.

282

. . .

, . ,

Return

. . ,

, 1% . hierCutoff

rankCutoff

. " Performance Analyzer preference variables ( )". . ,

Ranked and Hierarchical Profile . , . . . profile report (CR-191) .

Interpreting the Name Field( Name, Under(%) .

,

) ,

In(%)

, .

HDL VHDL C,

. Verilog.

PLI/VPI

FLI,

,

. vsim -

,

,

,

. . ,

.

, ,

, .

,

,

,

.

283

Interpreting the Under(%) and In(%) Fields( Under(%) In(%)) In(%) Under(%) , In(%)

Name.

Under(%)

,

. In(%)

,

VHDL. Under(%)

ё .

, ,

%

% , VHDL/Verilog

,

Source

. ,

, retrieve.vhd:35, .

,

Differences in the Ranked and Hierarchical Views (

)

. •

Name

,

,

.

•

%Parent . Name

,

. , , .

, ,

,

3

.

, ,

60 % ,

ё

.

,

.

, 3

,

VHDL . .

%Parent , .

, 284

,

. 10 % 80 % ,

, 10 %,

, , , 80 %

8 %. , ,

,

, ,

. ,

.

Reporting results (

)

save profile report (CR-191 ),

Performance

Analyzer. profile report [] [-hierarchical | -ranked] [-file] [-cutoff ]. , profile report -hierarchical -file hier.rpt -cutoff 4 ё

,

hier.rpt,

.

Performance Analyzer preference variables ( ) 285

Tcl , Hierarchical Profile . Tools > Edit Preferences >By Name > Profile ( Main). Apply, , Save modelsim.tcl. , , . http:// www.model.com/resources/pref_variables/frameset.htm . Profile

Ranked ,

Performance Analyzer commands( ) . .

ModelSim Command Reference

profile clear (CR-186) ,

run; ,

profile interval (CR187)

-

,

profile off (CR-188) profile on (CR-189)

ё

profile option (CR-190) profile report (CR-191)

,

,

286

10 - Code Coverage(

)

Source

overage_summary (

_

)

coverage_summary

, . ModelSim: •

ModelSim, (instrumented)

-

HDL

,

. • (

5 %).

•

, .

ModelSim

5.3

,

.

287

Enabling Code Coverage ( "Options tab" (CR-296).

) Enable Source File Coverage - coverage

Simulate,

vsim

, ModelSim (

). .

Source

coverage_summary .

, (

). : ,

-O0 (

),

.

.

The coverage_summary window (

_

)

overage_summary

. overage_summary, VSIM.

view_coverage

Tools > Source Coverage (

:

"Summary information" Misses

;

ё overage_summary Source) " . Excluded. , Source. coverage_summary

Excluded. " Coverage data in the Source window( , , , Source

Summary information(

Pathname

•

Lines

•

Hits

.

)

coverage_summary . •

Main)

, : . . ,

. •

Percentage –

. .

288

90 %,

( PrefCoverage(cutoff). , , ё

,

. , Lines, Hits, %).

( .

Misses tab(

) .

Misses overage_summary,

,

. . , ,

( ), ,

,

Exclude Selected Lines. Excluded ( " Coverage data in the Source window (

Excluded tab(

"X"

Source Source )" .334)).

)

Excluded .

, Source.

Misses Excluded

.

ё

-

, : : • Include Entire Selected Files . , . ,

Source.

• Revert To Initial Filter

• Clear Out Current Filter

• Load a New Filter

• Disable/Enable Filtering /

.

.

, . • Cancel . 289

The coverage_summary window menu bar( coverage_summary ) overage_summary

Open > Coverage > Merge Coverage Open > Coverage > Apply a Previous Coverage Open > Load a New Filter

: File, Coverage, and Report. .

. " Merging coverage report files ( )" -

. files (

" Exclusion filter

)"

Save > Line Coverage Save > Current Filter

, " Exclusion filter files

. (

)" coverage_summary

Close

Clear Current Coverage Revert To Initial Filter Clear out Current Filter Disable/Enable Filtering

/

. .

Save Summary Coverage Save Line Coverage

,

Save Excluded Lines

,

,

Save Zeroed Lines

Line Coverage, ,

Save Totals

, ,

Save As

ё

Coverage data in the Source window( Source ) 290

Source

, (

,

); "X"

,

.

, coverage_summary. View > Show coverage data ( Source). " " Coverage Miss Edit > Next Coverage Miss, , ) ( ).

,

ё .

.,

Edit > Previous - (

Excluding lines and files(

) ,

.

Source, ё

(

)

:

: • Exclude Coverage Line # . • Exclude Entire File . • Do Not Exclude Coverage Line # . • Do Not Exclude Entire File

Excluded

. Source,

, overage_summary.

Merging coverage report files( ) . > Coverage > Merge Coverage

Merge Coverage Reports

File > Open

coverage_summary .

:

• Coverage File Name to Read From

291

, . • Clear out accumulated coverage data , . • Keep coverage data for files not in the current design , . ё Source, .

,

, Open Source,

Exclusion filter files(

) , .

Source,

coverage_summary. File > Open > Load a New

File > Save > Current Filter ,

Filter.

Syntax(

)

[[ ...] [ ...]] | all ...

Arguments(

)

.

. ,

.

, ... .

.

" # - # ". , 32 - 35.

,

.

, ... ,

.

.

, all ,

.

,

.

Example(

)

control.vhd 72 - 76 84 93 292

testring.vhd all

Default filter file(

)

Tcl

PrefCoverage (pref_InitFilterFrom) ,

,

--coverage. " Code Coverage )"

"Exclude.cov". preference variables( .

Code Coverage preference variables( ) Tcl

, ,

By Name > Coverage ( , ,

Main). Save .

. Options > Edit Preferences > Apply, modelsim.tcl. http://www.model.com/resources/

pref_variables/frameset.htm .

Code Coverage commands (

)

,

Code Coverage –coverage vsim (CR-296).

.

; . .

ModelSim

.

coverage clear (CR-115)

,

coverage reload (CR-120) coverage report coverage report (CR-121)

, ,

coverage exclude clear (CR-116) coverage exclude disable (CR-117) coverage exclude enable (CR-118) coverage exclude load (CR-119)

293

11 - Waveform Comparison(

,

)

-

Wave List

294

Introduction(

)

Waveform Comparison ModelSim (.wlf

),

, .

Wave

List

Main. Waveform Comparison

•

:

,

,

•

,

•

,

•

,

• Wave. , Waveform Comparison ,

. , . - when compare add (CR-83).

,

ё

, ,

,

.

, Wave

List (

Shift- Tab

Main. " Wave window display " Wave . , , .

" Compare objects in the List window ". Tab

,

compare info (CR-

. 93).

295

Two modes of comparison(

)

Waveform Comparison .

:

,

(

(

-

) )

. Wave

List. , .

,

. -

. .

,

-

.

,

, . ,

. (

)

.

, . (

)

Wave.

Comparing hierarchical and flattened designs( ) , ,

, -

. Waveform Comparison ModelSim. •

, ,

, compare add (CR-83),

.

296

•

, compare add (CR-83)

,

, .

•

,

,

, " compare add (CR-83), .

-rebuild

",

.

– ,-

,

Waveform Comparison .

(

,

), Waveform Comparison

.

Graphic interface to Waveform Comparison( Waveform Comparison) Waveform Comparison Tools >Waveform Compare > Start Comparison.

Main

Opening dataset comparison(

Wave,

)

Start Comparison

Reference

Test.

Э

.wlf,

.

, , .

.

.wlf, , 297

,

, .

• Use Current Simulation , . . • Specify Dataset .wlf

,

. ,

, ,

ё

,

Browse. Browse

Select Dataset File, . Reference

Compare Dataset ( -

Test Compare

,

"OK" Main.

, " Adding signals, regions and/or clocks ( )" ), Wave List.

,

Adding signals, regions and/or clocks( ) , Main

, , Tools > Waveform Compare > Add Wave, ( ) .

,

,

-

,

298

ё Tools > Waveform Compare > Add > Compare by Signal Wave structure_browser,

. ё Options . "Comparison Method tab( )" .

ё

Tools > Waveform Compare > Add > Compare by Region Add Comparison by Region, .

Wave

Region Data • ,

.

• , . • All Types Selected Types (In, Out, InOut, Internal, Port). 299

• ,

.

, "When". •

. , Clocks, . Clocks Comparison Clocks. ,

ё

Add, Add Clocks, , ,

,

.

Expression Builder , " " 1

when, . •

, .

. -

. .

, .

• GUI )",

When " The GUI Expression Builder( when , .

"

Setting compare options( Tools > Waveform Compare > Options Main Comparison Options. General Options Comparison Method ( " Comparison Method tab ( )" ).

"

1

) Wave,

• General Options

300

Comparison Limit Count –– -

. ,

VHDL Matching –– X

VHDL

Z VHDL. ,

Verilog Matching –– X

Verilog

Z Verilog.

Verilog

.

Save as Default — . Reset to Default — . Automatically add comparisons to the wave window?— Wave.

Wave window display (

Wave)

Wave

. ё .

. /\refSignalNametestSignalName\. , . , . . .

301

, ,

. Wave Window Properties

. . "Setting Wave window display properties (

( Wave )" ).

Wave

"

"

"

"

, "

.

" -

"

. " .

Compare . • Start Comparison Compare Dataset . • Comparison Wizard , . • Run Comparison , ,

, . Main compare run (CR-101):

compare_info.txt. • End Comparison

. • Add Compare by Signal —

structure_browser .

Compare by Region —

Add Comparison by Region . . 302

Clocks —

Comparison Clocks .

• Options e Comparison Options , . • Differences Clear —

Wave .

compare reset (CR-100) .

Show — Main. Save —

compare info (CR-93). Specify Differences File

, "compare.dif". Write Report— .

ModelSim. ё

,

• Rules Show — .

compare list (CR-95). Specify Rule File

Save — ,

. "compare.rul."

• Reload Reload and Redisplay Compare Differences .

Printing compare differences(

)

, Wave " Printing and saving waveforms ( .

Postscript. )"

Compare objects in the List window(

List) List.

. (

). .

: Diff Info, Annotate Diff,

Ignore/Noignore

. ,

, . 303

Waveform Comparison preference variables ( Waveform Comparison) Tcl . , Main). -Save

(

,

Tools > Edit Preferences > By Name > Compare Apply, modelsim.tcl. ,

, ,

, http://www.model.com/resources/

. pref_variables/frameset.htm

Waveform Comparison commands ( Waveform Comparison) . .

К

.

ModelSim

compare add (CR-83) ,

compare annotate (CR-86)

;

compare clock (CR87)

,

-

-delete,

compare configure (CR-89)

,

ompare continue (CR-90)

compare delete (CR91)

compare end (CR-92) , ;

compare info (CR-93) -write

compare add

compare list (CR-95) compare options (CR-96)

Tcl; , ,

compare reload (CR-

,

99)

,

compare reset (CR100)

start ,

compare run (CR101)

compare

; ,

compare savediffs (CR-102)

compare saverules

(

"

") 304

(CR-103)

,

, ; ,

compare see (CR-104) wave, compare start (CR106)

compare stop (CR108) compare update (CR-109)

compare stop,

.wlf

12 - Signal Spy(

)

init_signal_driver init_signal_spy signal_force signal_release $init_signal_driver $init_signal_spy $signal_force $signal_release Signal Spy TM ,

,

. VHDL

.

305

Introduction(

)

Verilog .

,

testbench. Verilog testbench Verilog , ,

.

VHDL VHDL. VHDL , .

,

,

, .

Signal Spy

. ( VHDL

VHDL modelsim_lib. ,

),

, .

,

" Util package (

)" ,

VHDL

:

library modelsim_lib; use modelsim_lib.util.all; Verilog

"

".

VHDL

Verilog.

Designed for testbenches( Signal Spy

testbenches) . ModelSim, Signal Spy

testbenches,

HDL

Signal Spy .

, .

init_signal_driver 306

init_signal_driver () ( src_object) dest_object).

VHDL VHDL VHDL (

Verilog Verilog (

, testbench).

init_signal_driver

, HDL. , init_signal_driver

Call only once(

, .

)

init_signal_driver .

,

init_signal_driver init_signal_driver,

.

. ,

,

VHDL.

VHDL

init_signal_driver ,

. VHDL init_signal_driver .

Syntax(

wait. .

)

init_signal_driver(src_object, dest_object, delay, delay_type, verbose)

Returns(

)

Arguments(

src_object

)

string

.

( )

VHDL

Verilog.

, (

dest_object

string

,"/"

. VHDL

"."). "/" . ( )

".".

Verilog.

,

(

,"/" "/"

"."). ".".

. delay

time

.

, src_object. . 307

, delay_type

del_mode

.

, mti_inertial mti_inertial. -0 1.

. mti_transport. verbose

integer

. ,

,

src_object - 0,

Related procedures(

dest_object. .

)

init_signal_spy , signal_force , signal_release

Limitations(

)

•

Verilog,

delay_type. ,

mti_transport, mti_inertial. •

, ;

.

•

HDL.

Example(

)

library IEEE, modelsim_lib; use IEEE.std_logic_1164.all; use modelsim_lib.util.all; entity testbench is end; architecture only of testbench is signal clk0 : std_logic; begin gen_clk0 : process begin clk0 -sdftyp [ =] < filename> -sdfmax [ =] < filename> SDF . , -sdfmax, SDF .

, -sdftyp, ,

Instance specification ( SDF

)

,

,

, - ASIC

.

, -sdfmin,

SDF

.

FPGA

, SDF

myasic.SDF

U1

,

testbench :

vsim -sdfmax /testbench/u1=myasic.sdf testbench ,

.Э

SDF

–

, . , .

, ,

SDF

SDF .

,

vsim -sdfmax /system/u1=asic1.sdf -sdfmax /system/u2=asic2.sdf system

SDF specification with the GUI( SDF

GUI) ,

Simulate

SDF

SDF.

321

, , Simulate > Simulate ( ). SDF , "The $sdf_annotate system task( $sdf_annotate )" .

Errors and warnings( ,

Verilog, $sdf_annotate. .

)

SDF , -sdfnoerror vsim (CR-296) , ,

. SDF

,

.

, -sdfnowarn

(

vsim

+nosdfwarn.

). , . " Troubleshooting(

SDF Simulate Disable SDF warnings (-sdfnowarn, +nosdfwarn) Reduce SDF errors to warnings (-sdfnoerror), . )" , .

VHDL VITAL SDF VHDL SDF 1076.4 VITAL ASIC SDF . ,

VITAL. ,

,

, VITAL SDF . , , . VITAL, . " Obtaining the VITAL specification and source code VITAL )" .

(

SDF to VHDL generic matching( SDF

,

VHDL)

SDF . VHDL)

(

.

SDF

VITAL. SDF

.

-

, .

SDF

-

:

SDF

VHDL

( IOPATH y (3))

tpd_a_y

( IOPATH (posedge clk) q (1) (2))

tpd_clk_q_posedge

322

(INTERCONNECT u1/y u2/a (5))

tipd_a

(SETUP d (posedge clk) (5))

tsetup_d_clk_noedge_posedge

(HOLD (negedge d) (posedge clk) (5))

thold_d_clk_negedge_posedge

( SETUPHOLD d clk (5) (5))

tsetup_d_clk & thold_d_clk

(WIDTH (COND (reset== 1’b0) clk) (5))

tpw_clk_reset_eq_0

Resolving errors(

) ,

,

. , ** Error (vsim-SDF-3240) myasic.sdf(18): Instance ’/testbench/dut/u1’ does not have a generic named ’tpd_a_y’

,

,

VITAL. VITAL.

,

SDF .

VHDL, . VITAL

,

VITAL VITAL ,

.

: •

VITAL.

• SDF

.

, ,

SDF

,

.

•

SDF

VITAL 2.2b. ,

. vsim (CR-296)

-vital2.2b:

vsim -vital2.2b -sdfmax /testbench/u1=myasic.sdf testbench . "Troubleshooting(

)".

Verilog SDF Verilog

, ,

$sdf_annotate ( Verilog). , , 323

. Verilog.

$sdf_annotate ,

.

The $sdf_annotate system task(

$sdf_annotate)

$sdf_annotate:

$sdf_annotate ( [" "], [], [" "], [" "],[ " < Mtm_spec > "], [" < scale_factor > "], [" < scale_type > "]);

" " ,

SDF

.

.

,

. $ sdf_annotate.

, " " , , " " ,

" " , " ", "

(

.

.

.

. logfile. .

.

. ", " - "tool_control".

,

. "tool_control". "tool_control" +mindelays, +typdelays, ",

+maxdelays

+typdelays).

" " , " : : ". , . " " , . < mtm _spec> , ,

, min/typ/max SDF . ё - "from_min", "from_minimum", "from_typ", "from_typical", "from_max",

.

.

SDF

.

324

"from_maximum", "from_mtm",

"from_mtm".

, .

, ,

,

.

,

SDF

: $sdf_annotate ("myasic.sdf", testbench.u1); : $sdf_annotate ("myasic.sdf", testbench.u1,,, "

");

SDF to Verilog construct matching( SDF Verilog) SDF . ё

,

Verilog , SDF,

. ,

.

SDF

, SDF

. SDF Verilog

:

,

IOPATH

:

SDF

Verilog

( IOPATH (posedge clk) q (3) (4))

(posedge clk = > q) = 0;

( IOPATH y (3) (4))

buf u1 (y, a);

IOPATH , . INTERCONNECT SDF

PORT

. ,

,

,

: Verilog

(INTERCONNECT u1.y u2.a (5))

input a;

(PORT u2.a (5))

input a;

inout .

, (MIPD- Module Input Port Delay).

,

ё 325

ё

,

,

, PATHPULSE SDF

MIPD. , Verilog

GLOBALPATHPULSE

:

( PATHPULSE y (5) (10))

( = > y) = 0;

( GLOBALPATHPULSE y (30) (60))

( = > y) = 0; SDF,

. :

DEVICE SDF

Verilog

(DEVICE y (5))

and u1 (y, a, b);

(DEVICE y (5))

(a= > y) = 0; (b = > y) = 0;

SDF –

,

.

, ,

DEVICE (

,

).

,

, (

, SETUP SDF

, ).

$setup

$setuphold: Verilog

(SETUP d (posedge clk) (5))

$setup (d, posedge clk, 0);

(SETUP d (posedge clk) (5))

$setuphold (posedge clk, d, 0, 0);

HOLD SDF

$hold

$setuphold: Verilog

(HOLD d (posedge clk) (5))

$hold (posedge clk, d, 0);

(HOLD d (posedge clk) (5))

$setuphold (posedge clk, d, 0, 0);

SETUPHOLD SDF

$setup, $hold,

( SETUPHOLD d (posedge clk) (5) (5))

$SETUPHOLD: Verilog $setup (d, posedge clk, 0); 326

( SETUPHOLD d (posedge clk) (5) (5))

$hold (posedge clk, d, 0);

( SETUPHOLD d (posedge clk) (5) (5))

$SETUPHOLD (posedge clk, d, 0, 0);

)

RECOVERY( SDF

$recovery: Verilog

(RECOVERY (negedge reset) (posedge clk) (5))

REMOVAL( SDF

$removal: Verilog

)

(REMOVAL (negedge reset) (posedge clk) (5))

RECREM SDF ( RECREM (negedge (5)) ( RECREM (negedge (5)) ( RECREM (negedge (5))

$recovery(negedge reset, posedge clk, 0);

$recovery, $removal,

$removal(negedge reset, posedge clk, 0);

$recrem: Verilog

) (posedge clk) (5)

$recovery (negedge reset, posedge clk, 0);

) (posedge clk) (5)

$removal (negedge reset, posedge clk, 0);

) (posedge clk) (5)

$recrem( negedge reset, posedge clk, 0);

SKEW( ) $skew: SDF (SKEW (posedge clk1) (posedge clk2) (5))

Verilog $skew (posedge clk1, posedge clk2, 0);

WIDTH $width: SDF (WIDTH (posedge clk) (5))

Verilog $width (posedge clk, 0);

PERIOD $period: SDF (PERIOD (posedge clk) (5))

Verilog $period (posedge clk, 0);

NOCHANGE $nochange: SDF (NOCHANGE (negedge write) addr (5) (5))

Verilog $nochange(negedge write, addr, 0, 0);

Optional edge specifications(

)

. 327

, •

,

•

,

•

,

:

SDF

. . SDF

. •

, SDF

. SDF , SDF

Verilog.

, Verilog

, ,

SDF :

SDF

Verilog

(SETUP data (posedge clock) (5))

$setup(posedge data, posedge clk, 0);

(SETUP data (posedge clock) (5))

$setup(negedge data, posedge clk, 0);

,

, ,

SDF

, .

, SDF

,

.

SDF

Verilog

(SETUP (posedge data) (posedge clock) (4))

$setup(data, posedge clk, 0);

(SETUP (negedge data) (posedge clock) (6))

$setup(data, posedge clk, 0);

,

SDF ,

, SDF posedge 10, 1x, x0, x1. [01, 0x, x1] negedge.

, . posedge (+ negedge . posedge , ,

)

,

negedge(-

). - 01, 0x, [10, 1x, x0] SDF

. ,

SDF

Verilog

328

(SETUP data (posedge clock) (5))

$setup(data, edge[01, 0x] clk, 0);

Optional conditions(

)

.

, :

•

,

SDF

.

•

, .

•

,

SDF

SDF

. , ,

.

, SDF

Verilog

(SETUP data (COND (reset!=1) (posedge clock)) (5))

$setup(data, posedge clk &&& (reset==0), 0);

,

.

,

. , SDF

Verilog

(COND (r1 || r2) (IOPATH clk q (5)))

if (r1 || r2) (clk => q) = 5; // matches

(COND (r1 || r2) (IOPATH clk q (5)))

if (r2 || r1) (clk => q) = 5; // does not match

, r2

r1

.

Rounded timing values( ) SDF TIMESCALE , 10ps ( 16ps

SDF .

.016 timescale), 20ps. , MIPD.

.

SDF SDF TIMESCALE - 1ns,

, ,

20ps.

SDF

,

329

SDF for Mixed VHDL and Verilog Designs( SDF VHDL Verilog) VHDL

Verilog

. VHDL VITAL SDF

Verilog SDF $sdf_annotate Verilog Verilog . .

.

.

vsim (CR-296) .

SDF

Interconnect delays(

)

. ModelSim Verilog, VHDL/VITAL,

..

vsim .

. , ,

.

,

,

, ,

.

Troubleshooting(

)

Specifying the wrong instance(

) SDF

SDF ,

.

.

-

, ASIC

SDF

FPGA, . VHDL

Verilog

.

, ,

.

VHDL testbench entity testbench is end; architecture only of testbench is component myasic 330

end component; begin dut : myasic; end; Verilog testbench module testbench; myasic dut(); endmodule - myasic,

- dut.

, :

vsim -sdfmax /testbench/dut=myasic.sdf testbench ,

:

vsim -sdfmax /dut=myasic.sdf testbench , , SDF ,

SDF

. ,

,

ё,

, environment (CR-146).

, SDF.

Mistaking a component or module name for an instance label (

) ,

.

,

testbenches: vsim -sdfmax /testbench/myasic=myasic.sdf testbench : ** Error (vsim-SDF-3250) myasic.sdf(0): Failed to find INSTANCE ’/testbench/myasic’.

Forgetting to specify the instance(

)

, SDF,

.

,

vsim -sdfmax myasic.sdf testbench 331

: ** Error (vsim-SDF-3250) myasic.sdf(0): Failed to find INSTANCE ’/testbench/u1’ ( ЕЦ) ** Error (vsim-SDF-3250) myasic.sdf(0): Failed to find INSTANCE ’/testbench/u2’ ** Error (vsim-SDF-3250) myasic.sdf(0): Failed to find INSTANCE ’/testbench/u3’ ** Error (vsim-SDF-3250) myasic.sdf(0): Failed to find INSTANCE ’/testbench/u4’ ** Error (vsim-SDF-3250) myasic.sdf(0): Failed to find INSTANCE ’/testbench/u5’ ** Warning (vsim-SDF-3432) myasic.sdf: This file is probably applied to the wrong instance. (Э

).

** Warning (vsim-SDF-3432) myasic.sdf: Ignoring subsequent missing instances from this file. ( .) ,

,

, :

** Warning (vsim-SDF-3440) myasic.sdf: Failed to find any of the 358 instances from this file. ( 358 ). ** Warning (vsim-SDF-3442) myasic.sdf: Try instance ’/testbench/dut’ - it contains all instance paths from this file.( ’/testbench/dut ’ – ) ,

ё . " Resolving errors( VHDL VITAL SDF.

. )"

332

14 - Value Change Dump (VCD) Files ( (VCD))

VCD ModelSim

VCD

VCD -

1— 2— 3—

ё

VCD VCD VCD

Verilog VHDL HDL

VCD VHDL VCD VCD 333

TSSI

VCD

VCD dumpports

Verilog VCD Model Technology’s VCD

1364. ,

ModelSim. ASCII

,

. VCD VCD

Verilog , Verilog. ModelSim VCD Verilog VHDL.

VHDL;

ModelSim

: ASIC , ASIC.

,

VCD,

ModelSim VCD commands and VCD tasks ( ModelSim VCD VCD )_ ModelSim VCD VCD VCD

1364 VCD . .

VCD vcd add (CR-231) vcd checkpoint (CR-232)

VCD $dumpvars $dumpall $dumpfile

vcd file(CR-241) vcd flush (CR-245)

$dumpflush

vcd limit (CR-246)

$dumplimit

vcd off (CR-247)

$dumpoff

vcd on(CR-248)

$dumpon 334

ModelSim 5.5 dumpports). .

VCD ( dumpports VCD

dumpports VCD

VCD

vcd dumpports (CR-234)

$dumpports

vcd dumpportsall (CR-236)

$dumpportsall

vcd dumpportsflush (CR-237)

$dumpportsflush

vcd dumpportslimit (CR-238)

$dumpportslimit

vcd dumpportsoff (CR-239)

$dumpportsoff

vcd dumpportson (CR-240)

$dumpportson

ModelSim

5.5

VCD . Std 1364. $dumpfile, $dumpvar, , ,

, , $fdumpfile, VCD,

. .

.

VCD

VCD

vcd add (CR-231) -file

$dumpvars

vcd checkpoint (CR-232)

$dumpall $dumpfile

vcd files(CR-243) vcd flush (CR-245)

$dumpflush

vcd limit (CR-246)

$dumplimit

vcd off (CR-247)

$dumpoff

vcd on(CR-248)

$dumpon

:

,

(vcd file

vcd files)

, 335

VCD. Vcd file VCD ModelSim

5.5. Vcd files ,

VCD 5.5

ModelSim

Creating a VCD file(

.

VCD)

ModelSim

VCD

.

VCD

0, 1, x, ;

z

VCD . , . К

, .

ё

Flow for four-state VCD file( VCD) % % % %

:

cd ~/modeltech/examples vlib work vlog counter.v tcounter.v vsim test_counter

,

,

VSIM VSIM VSIM VSIM

1> 2> 3> 4>

vcd file (CR-

VCD vcd add (CR-231):

241) vcd file myvcdfile.vcd vcd add /test_counter/dut/* run quit -f

VCD

.

Flow for extended VCD file( % % % %

ModelSim.

VCD) :

cd ~/modeltech/examples vlib work vlog counter.v tcounter.v vsim test_counter

,

, vcd dumpports (CR-234):

VCD

,

VSIM 1> vcd dumpports -file myvcdfile.vcd /test_counter/dut/* VSIM 3> run VSIM 4> quit –f

VCD

Case sensitivity(

.

)

336

VHDL

, , ,

ModelSim ё VCD .

ModelSim

, Verilog ,

Resimulating a design from a VCD file ( VCD :

ё VCD

.

)

ModelSim 5.5c . www.model.com/products/documentation/resim_vcd.pdf , . VCD

, .

VHDL, Verilog,

HDL. . VCD VCD

1

:

vcd dumpports (CR-234).

,

,

2

-vcdstim vsim (CR-296).

Example 1 — Verilog counter( -

,

VCD

1-

ё

Verilog )

vcd dumpports:

% cd ~/modeltech/examples % vlib work % vlog counter.v tcounter.v % vsim test_counter VSIM 1> vcd dumpports -file counter.vcd /test_counter/dut/* VSIM 2> run VSIM 3> quit -f

ё

-vcdstim:

% vsim -vcdstim counter.vcd counter VSIM 1> add wave /* VSIM 2> run 200

Example 2 — VHDL adder( -

,

VCD

2-

VHDL)

vcd dumpports:

% cd ~/modeltech/examples % vlib work % vcom gates.vhd adder.vhd stimulus.vhd % vsim testbench VSIM 1> vcd dumpports -file addern.vcd /testbench/uut/* VSIM 2> run 1000 VSIM 3> quit -f

ё

-vcdstim

% vsim -vcdstim addern.vcd addern -gn=8 -do "add wave /*; run 1000"

337

Example 3 — Mixed-HDL design( -

,

3-

VCD ,

HDL

)

:

% cd ~/modeltech/examples/mixedHDL % vlib work % vlog cache.v memory.v proc.v % vcom util.vhd set.vhd top.vhd % vsim top VSIM 1> vcd dumpports -file proc.vcd /top/p/* VSIM 2> vcd dumpports -file cache.vcd /top/c/* VSIM 3> vcd dumpports -file memory.vcd /top/m/* VSIM 4> run 1000 VSIM 5> quit -f

,

VCD :

% vsim -vcdstim proc.vcd proc -do "add wave /*; run 1000" VSIM 1> quit -f % vsim -vcdstim cache.vcd cache -do "add wave /*; run 1000" VSIM 1> quit -f % vsim -vcdstim memory.vcd memory -do "add wave /*; run 1000" VSIM 1> quit -f

A VCD file from source to output(VCD ) VHDL,

,

VCD.

VHDL source code( VHDL:

VHDL) ,

338

library IEEE; use IEEE.STD_LOGIC_1164.all; entity SHIFTER_MOD is port (CLK, RESET, data_in : IN STD_LOGIC; Q : INOUT STD_LOGIC_VECTOR(8 downto 0)); END SHIFTER_MOD ; architecture RTL of SHIFTER_MOD is begin process (CLK,RESET) begin if (RESET = ’1’) then Q ’0’) ; elsif (CLK’event and CLK = ’1’) then Q

:

(testfixture)

(dut)

D

L

U

H

N

X

Z

T

0 1 ? f

C b B

(

) (

) ( ( ( ( ( ( (

) ) ) ) ) ) ) 340

Strength values(

)

< strength > Strength(

Verilog

)

0 highz( 1 2 3 4 5 pull( 6 7 supply

: std_logic VHDL

)

’Z‘

)

’W‘, ’H‘, ’L‘ ’U‘, ’X‘, ’0‘, ’1‘, ’- ’

Port identifier code ( -

) ,

sml.vhd % vlib lmc % vcom -work lmc sml.vhd

344

SmartModels SmartModels. sml ( ),

VHDL, , :

lmc

% sm_entity -all -c -xe -xa > smlcomp.vhd ,

smlcomp.vhd SmartModel

:

library ieee; use ieee.std_logic_1164.all; package sml is

end sml; lmc : % vcom -work lmc smlcomp.vhd SmartModels library

, use

:

library lmc; use lmc.sml.all;

y7c285 SmartModel.

,

sm_entity

library ieee; use ieee.std_logic_1164.all; entity cy7c285 is generic (TimingVersion : STRING := "CY7C285-65"; DelayRange : STRING := "Max"; MemoryFile : STRING := "memory" ); port ( A0 : in std_logic; A1 : in std_logic; A2 : in std_logic; A3 : in std_logic; A4 : in std_logic; A5 : in std_logic; A6 : in std_logic; A7 : in std_logic; A8 : in std_logic; A9 : in std_logic; A10 : in std_logic; A11 : in std_logic; A12 : in std_logic;

345

A13 : in std_logic; A14 : in std_logic; A15 : in std_logic; CS : in std_logic; O0 : out std_logic; O1 : out std_logic; O2 : out std_logic; O3 : out std_logic; O4 : out std_logic; O5 : out std_logic; O6 : out std_logic; O7 : out std_logic; WAIT_PORT : inout std_logic ); end; architecture SmartModel of cy7c285 is attribute FOREIGN : STRING; attribute FOREIGN of SmartModel : architecture is "sm_init $MODEL_TECH/libsm.sl ; cy7c285"; begin end SmartModel;

•

-

SmartModel (

). •

-

, SmartModel

). sm_entity -93,

SmartModel ( .

, -93

93

, , wait

•

WAIT WAIT, VHDL.

. \WAIT\. WAIT_PORT,

- std_logic. SmartModel.

•

DelayRange, TimingVersion, MemoryFile . SmartModel ( ). Sm_entity SmartModel. , SmartModel

•

VHDL, sm_entity

(sm_init) -

SmartModel

sm_entity.

SmartModels. 346

• modelsim.ini. •

($MODEL_TECH/libsm.sl

(cy7c285 SmartModel

,

libsm

SmartModel. .

Vector ports(

)

,

-

sm_entity

,

. , SmartModel SWIFT ,

ModelSim . , ,

. . ,

!

-

, CY7C285 SmartModel:

Command channel(

)

-

ModelSim

SmartModel, SmartModel . " SmartModel"(http://www.synopsys.com/products/lm/docs/swift_r41/intro.html). . SmartModel:

lmc |-all "" instance_name (

.

SmartModel. environment (CR-147)). SmartModel /top/u1:

,

lmc /top/u1 "SetConstraints Off" -all,

SmartModel. 347

, SmartModel: lmc -all "SetConstraints Off" , SmartModel:

SmartModel, , ,

.

lmcsession "" SmartModel "(http://

, " www.synopsys.com/products/lm/docs/swift_r41/intro.html) .

SmartModel Windows(

Windows) SmartModel SmartModel Windows. SmartModel(

web

site Synopsys’) . . Windows

, , \z1I10. GSR.OR\ (

.

5.3c ModelSim, VHDL Verilog VHDL. z1I10. GSR.OR, Modelsim , lmcwin, add wave, examine). . ,

add wave /top/swift_model/\z1I10.GSR.OR\ ,

.

ReportStatus ReportStatus ,

,

.

lmc /top/u1 ReportStatus SmartModel Windows: WA "Read-Only (Read Only)" WB "1-bit" WC "64-bit" ,

wa, wb, wc. (lmcwin).

348

lmcwin SmartModel : • lmcwin read [-] • lmcwin write • lmcwin enable • lmcwin disable • lmcwin release , . , /top/u1/wa

wa

/top/u1.

lmcwin read

. -hexadecimal )( , wc

lmcwin read (-

,

-binary, -decimal, -

,

,

64-

). std_logic.

: lmcwin read /top/u1/wc –h

lmcwin write .

lmcwin write , ,

, 1

. wb,

1’

wc:

lmcwin write /top/u1/wb 1 lmcwin write /top/u1/wc X"FFFFFFFFFFFFFFFF" lmcwin enable .

lmcwin enable, ( std_logic add list (CR-48)

std_logic_vector. , . .

) , ,

,

wa:

349

lmcwin enable /top/u1/wa add list /top/u1/wa lmcwin disable .

lmcwin disable, , . ,

, wa:

lmcwin disable /top/u1/wa lmcwin release -

, . lmcwin write

Memory arrays (

lmcwin write lmcwin release .

) .

,

. . ,

5

mem:

lmcwin read /top/u2/mem(5) 0.

,

. .

Verilog SmartModel interface(Verilog ) SWIFT SmartModel,

r40b, PLI,

Verilog PLI

SWIFT. , , Logic Modeling's SmartInstall.

Verilog (LMTV). "Verilog",

Linking the LMTV interface to the simulator( LMTV ) 350

Synopsys ModelSim

, LMTV.

5, "

Synopsys, " " Synopsys " ( ,

MTI Verilog

Synopsys) .

16 - Logic Modeling Hardware Models (

)

VHDL hm_entity

ModelSim VHDL Verilog.

, 351

, . ,

.

, ModelSim.

,

: .

ModelSim SE.

VHDL Hardware Model interface ( VHDL) ModelSim VHDL

. , .

, .

ModelSim , hm_entity (

modelsim.ini. )

. 352

[lmc]

modelsim.ini, ModelSim. :

[lmc] ; ModelSim’s interface to Logic Modeling’s hardware modeler SFI software libhm = $MODEL_TECH/libhm.sl ; ModelSim’s interface to Logic Modeling’s hardware modeler SFI software (Windows NT) ; libhm = $MODEL_TECH/libhm.dll ; Logic Modeling’s hardware modeler SFI software (HP 9000 Series 700) ; libsfi = /lib/hp700/libsfi.sl ; Logic Modeling’s hardware modeler SFI software (IBM RISC System/6000) ; libsfi = /lib/rs6000/libsfi.a ; Logic Modeling’s hardware modeler SFI software (Sun4 Solaris) ; libsfi = /lib/sun4.solaris/libsfi.so ; Logic Modeling’s hardware modeler SFI software (Window NT) ; libsfi = /lib/pcnt/lm_sfi.dll ; Logic Modeling’s hardware modeler SFI software (Linux) ; libsfi = /lib/linux/libsfi.so

ModelSim,

libhm

. libsfi ,

. libhm .

, ModelSim ,

libsfi

libhm libhm.sl, MODEL_TECH. ModelSim MODEL_TECH

,

, .

Windows , libhm ( libhm

";")

Windows. ,

libsfi

. M_LIB

, .

LM_DIR

Creating foreign architectures with hm_entity ( hm_entity) hm_ entity ModelSim . : С hm_entity [-xe] [-xa] [-c] [-93] 353

ы -xe . -xa . -c . -93 .

(

.

). , stdout

hm_entity . (-xe),

(-c),

, (-xa). ,

.

, LMTEST:

% hm_entity LMTEST.MDL > lmtest.vhd % vlib lmc % vcom -work lmc lmtest.vhd VHDL, .

, , .

stdout

LMTEST.

% hm_entity -c -xe -xa LMTEST.MDL . CY7C285

,

hm_entity

:

CY7C285 library ieee; use ieee.std_logic_1164.all; entity cy7c285 is generic ( DelayRange : STRING := "Max" ); port ( A0 : in std_logic;

354

A1 : in std_logic; A2 : in std_logic; A3 : in std_logic; A4 : in std_logic; A5 : in std_logic; A6 : in std_logic; A7 : in std_logic; A8 : in std_logic; A9 : in std_logic; A10 : in std_logic; A11 : in std_logic; A12 : in std_logic; A13 : in std_logic; A14 : in std_logic; A15 : in std_logic; CS : in std_logic; O0 : out std_logic; O1 : out std_logic; O2 : out std_logic; O3 : out std_logic; O4 : out std_logic; O5 : out std_logic; O6 : out std_logic; O7 : out std_logic; W : inout std_logic ); end; architecture Hardware of cy7c285 is attribute FOREIGN : STRING; attribute FOREIGN of Hardware : architecture is "hm_init $MODEL_TECH/libhm.sl ; CY7C285.MDL"; begin end Hardware;

•

-

(

). •

-

,

). VHDL, hm_entity hm_entity

( . -93,

, -93. ,. . •

•

- std_logic.

,

DelayRange .

-" ).

, ", " "

",

"

"(

".

355

•

(hm_init) – .

•

($MODEL_TECH/libhm.sl) , modelsim.ini.

•

libhm

(CY7C285. MDL) -

. .

Vector ports(

)

,

-

hm_entity

,

. ,

, , . .

,

! -

, CY7C285:

component cy7c285 generic ( DelayRange : STRING := "Max"); port ( A : in std_logic_vector (15 downto 0); CS : in std_logic; O : out std_logic_vector (7 downto 0); WAIT_PORT : inout std_logic ); end component; for all: cy7c285 use entity work.cy7c285 port map (A0 => A(0), A1 => A(1), A2 => A(2), A3 => A(3), A4 => A(4), A5 => A(5), A6 => A(6), A7 => A(7), A8 => A(8), A9 => A(9), A10 => A(10), A11 => A(11), A12 => A(12), A13 => A(13), A14 => A(14), A15 => A(15), CS => CS, O0 => O(0), O1 => O(1), O2 => O(2), O3 => O(3), O4 => O(4), O5 => O(5), O6 => O(6), O7 => O(7), WAIT_PORT => W );

356

Hardware model commands(

) .

. Lm_vectors on|off [] /

.

Lm_measure_timing on|off [] / . Lm_timing_checks on|off / . Lm_loop_patterns on|off / . Lm_unknowns on|off /

.

17- Tcl and macros (DO files) ( Tcl (DO files)) Tcl

ModelSim

Tcl Tcl Tcl if 357

set .

Tcl

ModelSim Tcl ModelSim Tcl

Ma

Tcl (DO DO

) DO files DO Tcl ( ModelSim.

) ModelSim Tcl. Tcl

ModelSim ,

Tcl ,

ModelSim. ModelSim C.

Tcl

,

Tcl

ё

;

Tcl ModelSim . ,

,

ModelSim Tcl,

Tcl features within ModelSim (

, .

Tcl

Tcl ModelSim • •

(

ModelSim) :

,

C) C

• • • • 358

• •

(

)

ё

•

Tcl References(

Tcl)

Tcl - Tcl Tk К , Addison-Wesley Publishing Company, Inc., Practical Programming in Tcl Tk ,Brent Welch , Prentice Hall.

.

: •

Help > Tcl Man Pages (

).

• Model Technology www.model.com/resources/tcltk.asp

Tcl tutorial(

Tcl:

Tcl ) Tcl ModelSim,

. " Tcl/Tk

ModelSim "

ModelSim SE.

Tcl commands (

Tcl) Tcl,

( Tcl "

).

Help > Tcl Man Pages

."

, Tcl.

ModelSim,

Tcl, Tcl.

ы щ я ModelSim continue format list | wave if

.

: я

run (CR-208)

я)

(

-continue

write format (CR-321) wave Tcl if,

list ."

if " 359

list

add list (CR-48)

nolist | nowave

delete (CR-132)

list

set

Tcl set,

wave

."

set " source

vsource (CR-311)

wave

add wave (CR-57)

Tcl command syntax(

Tcl) Tcl. set

if . 1 Tcl

-

,

. .

("]") ( .

2 ё

, .

.

)

.

Tcl

.

,

,

. ,

,

,

,

,

Tcl.

,

3

,

.

(

,

). (""")

4

,

. ,

(

, )

, .

,

,

, . .

5

-

("{") , ("}"). : (

, 360

, ). , ,

,

,

,

,

. , . ("["), Tcl

6

Tcl,

. ,

Tcl. , ("]").

ё

(

) . . ,

.

("$")

7

Tcl,

: . :

$name -

; ,

,

,

.

$name (index) .

, .

,

,

, .

${name} -

.

, . . ,

8

.

("\") .

,

,

, .

,

,

,

. , ,

,

.

\a \b

(

) (0x7). (0x8). 361

\f

(0xc).

\n

(0xa).

\r

(0xd).

\t

(0x9).

\v

(0xb).

\ whiteSpace

, ,

. , .

,

, , , . \\

("\"). ooo (

\ooo

,

,

)

. \xhh

hh .

.

, backslash-newline

,

. ("#")

9

,

,

Tcl ,

,

, . .

,

Tcl

10 .

,

,

, ;

.

, Tcl; . .

11 (

)

,

,

,

, .

if command syntax (

if) 362

Tcl if

.

, "?"-

,

.

if expr1 ?then? body1 elseif expr2 ?then? body2 elseif ... ?else? ?bodyN?

.

expr1

if (

,

0

else,

,

,

,

);

body1,

Tcl. ,

body2 then

, ",

"

else .

expr2, . .

bodyN

. BodyN

elseif, ,

.

else

,

,

, bodyN.

set command syntax(

set )

Tcl set

.

,

"?"

.

set varName ?value?

,

varName. ,

varName ,

, .

varName

, -

ё

: , varName

. .

ё ), .

, varName

,

(

ё ё (

varName

,

), . ё (

, ё ).

varName ,

ё ,

varName

,

363

, variable Tcl,

,

varName varName

Command substitution (

ё .

) []

ё

,

.

: set a 25 set b 11 set c 3 echo "the result is [expr ($a + $b)/$c]" : "the result is 12" VHDL,

Verilog

: [examine - name] %name

. %name [examine - name], .

Command separator(

, .

)

(;) .

.

Multiple-line commands(

)

Tcl , .

(

C)

. ,

{, if

else.

,

Tcl

,

, ,

.

if { [exa sig_a] == "0011ZZ"} { echo "Signal value matches" do macro_1.do 364

} else { echo "Signal value fails" do macro_2.do }

Evaluation order (

) Tcl , {}

,

,

,

ё

. ,

.

Tcl relational expression evaluation( Tcl) ,

:

• Tcl

, .

,

,

.

if {[exa var_1] == 345}... : if {[exa var_1] == "345"}... • , , Tcl . :

,

if {[exa var_2] == 001Z}... . if {[exa var_2] == "001Z"}... . •

:

if {[exa var_3] == ’X’}... . if {[exa var_3] == "X"}... . •

, -

,

Variable substitution(

C "==". C "! = ".

)

365

$ , , .

Tcl ,

ModelSim

: Tcl

. ,

:

$env() echo My user name is $env(USER) ,

env:

set env(SHELL) /bin/csh ."

" .

ModelSim-

System commands (

) UNIX

DOS,

exec Tcl : echo The date is [exec date]

List processing ( Tcl "

)

"-

,

Tcl

. ,

,

,

С

К

.

:

ы

lappend var_name val1 val2 ...

val1, val2,

. .

var_name lindex list_name index linsert list_name index val1 val2 ... list val1, val2 ... llength list_name

- th -0 val1, val2, . . list_name Tcl,

list_name; - th val1, val2,

. .

list_name

366

lrange list_name first last

list_name, ; "end",

lreplace list_name first last val1, val2,... , lsearch .

.

val1, val2, . . lsort,

Tcl Man Pages) . ModelSim Tcl: lecho (CR-161)

.

ModelSim Tcl commands (

ModelSim Tcl) Tcl

ModelSim.

; ModelSim .

К

ы

alias (CR-61)

Tcl, ;

find (CR-152)

incrTcl

lecho (CR-161) lshift (CR-166)

ё

,

Tcl Tcl 367

,

0-

lsublist (CR-167)

Tcl, Tcl glob

printenv (CR-186)

ModelSim Tcl time commands (

ModelSim Tcl)

ModelSim Tcl ,

Tcl. , (

. 10ns, " 10 ns "). , Time Scale Units.

64-

, UserTimeScale. .

, 0.

Conversions(

)

368

intToTime

32) 64-

( (

ModelSim - 64-

)

RealToTime

64-

scaleTime

,

Relations( К

)

ы

eqTime neqTime gtTime gteTime ltTime lteTime

1

0

, Tcl.

,

-

, if {[eqTime $Now 1750ns]} { ... }

Arithmetic ( К

)

ы

addTime divTime mulTime

6464-

subTime

369

Tcl examples(

Tcl)

Example 1(

1) Tcl/ModelSim

UNIX ё

, VHDL

. Tcl

,

Verilog HDL, VHDL

STRING. (DO_ECHO) , :

(

Windows, ,

, VHDL. exec Tcl , .

VHDL):

370

signal datime : string(1 to 28) := " spaces (

";# 28

VSIM):

proc set_date {} { global env set do_the_echo [set env(DO_ECHO)] set s [exec date] force -deposit datime $s if {do_the_echo} { echo "New time is [examine -value datime]" } } bp src/waveadd.vhd 133 {set_date; continue} --sets the breakpoint to call set_date

-

while Tcl , :

b, set b "" set i [expr[llength $a]-1] while {$i >= 0} { lappend b [lindex $a $i] incr i -1 }

...

for Tcl , :

b,

set b "" for {set i [expr [llength $a] -1]} {$i >= 0} {incr i -1} { lappend b [lindex $a $i] } foreach Tcl, (

b,

foreach

): set b "" foreach i $a { set b [linsert $b 0 $i] } 371

, break Tcl :

,

,

set b "" foreach i $a { if {$i = "ZZZ"} break set b [linsert $b 0 $i] }

-

,

,

continue Tcl: set b "" foreach i $a { if {$i = "ZZZ"} continue set b [linsert $b 0 $i] } switch Tcl: switch a b c }

$x { {incr t1} {incr t2} {incr t3}

Example 2(

2) Tcl ,

Wave

, ,

, .

. Main, ModelSim SE.

## This file contains procedures to manage multiple wave files. ## Source this file from the command line or as a startup script. ## source /wave_mgr.tcl ## add_wave_buttons ## Add wave management buttons to the main toolbar (new, save and load) ## new_wave ## Dialog box creates a new wave window with the user provided name ## named_wave ## Creates a new wave window with the specified title ## save_wave ## Saves name, window location and contents for all open ## wave windows ## Creates .do file for each window where is 1 ## to the number of windows. Default file-root is "wave". Also ## creates windowSet.do file that contains title and geometry info.

372

## load_wave ## Opens and loads wave windows for all files matching .do ## where are the numbers from 1-9. Default is "wave". ## Also runs windowSet.do file if it exists. ## Add wave management buttons to the main toolbar proc add_wave_buttons {} { _add_menu main controls right SystemMenu SystemWindowFrame {Load Waves} load_wave _add_menu main controls right SystemMenu SystemWindowFrame {Save Waves} save_wave _add_menu main controls right SystemMenu SystemWindowFrame {New Wave} new_wave } ## Simple Dialog requests name of new wave window. Defaults to Wave proc new_wave {} { global dialog_prompt vsimPriv set defaultName "Wave[llength $vsimPriv(WaveWindows)]" set dialog_prompt(result) $defaultName set windowName [GetValue . "Create Named Wave Window:" ] ## Debug puts "Window name: $windowName\n"; if {$windowName == "{}"} { set windowName "" } if {$windowName != ""} { named_wave $windowName } else { named_wave $defaultName } } ## Creates a new wave window with the provided name (defaults to "Wave") proc named_wave {{name "Wave"}} { global vsimPriv view -new wave set newWave [lindex $vsimPriv(WaveWindows) [expr [llength $vsimPriv(WaveWindows)] - 1]] wm title $newWave $name } ## Writes out format of all wave windows, stores geometry and title info in ## windowSet.do file. Removes any extra files with the same fileroot. ## Default file name is wave starting from 1. proc save_wave {{fileroot "wave"}} { global vsimPriv set n 1 set fileId [open windowSet_$fileroot.do w 755] foreach w $vsimPriv(WaveWindows) { echo "Saving: [wm title $w]" set filename $fileroot$n.do write format wave -window $w $filename puts $fileId "wm title $w \"[wm title $w]\"" puts $fileId "wm geometry $w [wm geometry $w]" puts $fileId "mtiGrid_colconfig $w.grid name -width / [mtiGrid_colcget $w.grid name -width]" puts $fileId "mtiGrid_colconfig $w.grid value -width / [mtiGrid_colcget $w.grid value -width]"

373

flush $fileId incr n } if {![catch {glob $fileroot\[$n-9\].do}]} { foreach f [lsort [glob $fileroot\[$n-9\].do]] { echo "Removing: $f" exec rm $f } } } ## Provide file root argument and load_wave restores all saved widows. ## Default file root is "wave". proc load_wave {{fileroot "wave"}} { global vsimPriv foreach f [lsort [glob $fileroot\[1-9\].do]] { echo "Loading: $f" view -new wave do $f } if {[file exists windowSet_$fileroot.do]} { do windowSet_$fileroot.do } }

Macros (DO files)(

(DO

))

ModelSim ( DO ModelSim , , Tcl. ( Main) Tools > Execute Macro

Creating DO files(

DO

DO

)do (CR-137).

)

,

Tcl, .

MAIN Main " ). -

DO

,

DO

(

,

,

" Main. ModelSim. DO

Wave, ,

.

add wave ld add wave rst add wave clk add wave d add wave q force -freeze clk 0 0, 1 {50 ns} -r 100 force rst 1 force rst 0 10 force ld 0 force d 1010 run 1700 force ld 1 run 100 force ld 0 run 400 force rst 1

374

run 200 force rst 0 10 run 1500

Using Parameters with DO files( ) DO

DO ,

.

, $1

$9 bp $ 1 $ 2.

.

,

"testfile" ,

design.vhd

127:

do testfile design.vhd 127

, ,

. shift (CR-215),

.

Making macro parameters optional( ) If you want to make macro parameters optional (i.e., be able to specify fewer parameter values with the command than the number of parameters referenced in the macro), you must use the argc (UM-455) simulator state variable. The argc simulator state variable returns the number of parameters passed. The examples below show several ways of using argc. ( , do, ), argc. argc . argc.

,

1

0-2 ModelSim

ё

.

,

.

switch $argc { 0 {vcom file1.vhd file2.vhd file3.vhd } 1 {vcom $1 file1.vhd file2.vhd file3.vhd } 2 {vcom $1 $2 file1.vhd file2.vhd file3.vhd } default {echo Too many arguments. The macro accepts 0-2 args. } }

2

. variable Files "" set nbrArgs $argc for {set x 1} {$x / < Project_Name > .mpf). .

,

(
500 ); . " see "Improve performance by locking memory n HPUX 10.2( , HPUX 10.2 )"

1,

(0) numeric_std

PathSeparator

numeric_bit ;

/

Datapath 389

Resolution

fs, ps, ns, us, ms, sec –

ns ; t; , ;

1, 10 100

(

, 10fs,

10 fs)

RunLength

100 UserTimeUnit

Startup

= do ;

ModelSim; do (CR-137)

.

(;)

StdArithNoWarnin gs

(do) 0, 1

1,

(0) Synopsys std_arith

TranscriptFile

UnbufferedOutput

;

0, 1

VHDL ;0=

Verilog ,

0 ,

1=

UserTimeUnit

fs, ps, ns, us, ms, sec

ns ,

, force (CR-154) run (CR-208); , , , Resolution ,

Veriuser Verilog PLI/VPI; . " Verilog PLI/VPI"

(;)

ё 390

WaveSignalName Width

0,

0 , Wave; ,

ё (

WLFCompress

0, 1

)

WLF

.(1)

1

.(0) WLFDeleteOnQuit 0, 1

,

WLF

, 0, 1, , WLF

WLFSaveAllRegio 0, 1 ns

0 ; ; 0

(1) ,

,

(0)

WLFSizeLimit

0–

WLF WLF (

;

,

0

) ;

MB ; WLFTimeLimit

0(

0 WLF; WLF ) .

,

0

MB ;

0

[lmc] Logic Modeling variables( [lmc] )

ModelSim’s

VHDL) " HDL "

, ё [lmc] INI/MPF . " "VHDL SmartModel interface ( " VHDL Hardware Model interface ( .

Setting variables in INI files (

INI

;

) 391

, . : = (;). : INI

vmap (CR-295) .

Reading variable values from the INI file( INI ) Tcl

modelsim.ini.

GetIniInt . GetIniReal . GetProfileString [] ё

.

,

.

Tcl

modelsim.ini Tcl

.

,

set MyCheckpointCompressMode [GetIniInt "CheckpointCompressMode" 1] set PrefMain(file) [GetProfileString vsim TranscriptFile ""]

Commonly used INI variables (

INI) modelsim.ini

.

. ($)

.

:

[Library] work = $HOME/work_lib test_lib = ./$TESTNUM/work ... [vsim] 392

IgnoreNote = $IGNORE_ASSERTS IgnoreWarning = $IGNORE_ASSERTS IgnoreError = 0 IgnoreFailure = 0 , MODEL_TECH, . MODEL_TECH Model Technology. ё VCOM VLOG . MODEL_TECH Technology, .

-

—

" others"

, , VSIM Model

modelsim.ini, . modelSim.ini,

,

ModelSim " others".

[Library] asic_lib = /cae/asic_lib work = my_work others = /install_dir/modeltech/modelsim.ini ,

" others"

" others", INI

.

, :

, , TranscriptFile modelsim.ini , ModelSim. ; Save the command window contents to this file TranscriptFile = trnscrpt . .

,

,

,

do ,

.

,

:

; VSIM Startup command Startup = do mystartup.do ,

ModelSim mystartup.do.

; VSIM Startup command Startup = run –all 393

,

VSIM .

.,

do (CR-137)

do

.

VHDL, , .

modelsim.ini.

[vsim] IgnoreNote = 1 IgnoreWarning = 1 IgnoreError = 1 IgnoreFailure = 1 . " Preference variables TCL )" .

Tcl; located in TCL files(

,

[vsim]

synopsys modelsim.ini.

,

[vsim] NumericStdNoWarnings = 1 StdArithNoWarnings = 1 Tcl; variables located in TCL files( )".

,

. " Preference TCL

Force force ). ,

-freeze, -drive, , -drive

–deposit(

, - freeze,

,.

4.1 . -freeze ,

modelsim.ini

. [vsim] ; Default Force Kind ; The choices are freeze, drive, or deposit DefaultForceKind = freeze

restart

-force, -nobreakpoint, -nolist, -nolog,

-nowave. 394

, modelsim.ini: DefaultRestartOptions = < options > nowave.

-force, -nobreakpoint, -nolist, -nolog,

-

: DefaultRestartOptions = -nolog -force : Tcl

modelsim.Tcl. .ini . VHDL93 VHDL93 INI

:

[vcom] ; Turn on VHDL-1993 as the default. Default is off (VHDL-1987). VHDL93 = 1 VHDL VHDL VHDL DelayFileOpen .

,

INI

.

,

. ,

[vsim] DelayFileOpen = 1

Preference variables located in TCL files ( , )

TCL

ModelSim TCL ,

,

, .

, ,

Tcl , ,

, . Tcl,

.

URL(uniform resource locator ):

http://www.model.com/resources/pref_variables/frameset.htm ModelSim

, 395

pref.tcl. GUI ModelSim (Tools > Edit Preferences ( ( Tcl ), ,

Main)),

. - modelsim.tcl. :

modelsim.tcl • MODELSIM_TCL

ModelSim

MODELSIM_TCL, ,

ModelSim

( ,

); •

./modelsim.tcl;

•

$ (HOME)/ /modelsim.tcl, :

modelsim.tcl , , MODELSIM_TCL .

User-defined variables (

)

,

set

Tcl.

, ,

.

set: set user1 7 : ECHO " user1 = $user1 "

ё

More preferences(

modelsim.ini ; files(

) . " Preference variables located in INI , INI )" .

Variable precedence(

)

,

.tcl

.ini. A

.tcl .ini .

,

modelsim.ini : TranscriptFile = transcript modelsim.tcl: set PrefMain(file) {} modelsim.tcl .

modelsim.ini

,

396

Simulator state variables( ) ,

,

. ,

DO

(

)

ModelSim.

argc

,

architecture

, Verilog

; configuration

,

, ;

delta entity

VHDL

library MacroNestingLevel n

Verilog

,

,

n

1-9 Now

, (

, 1000 ns)

now (

, 1000)

resolution

Referencing simulator state variables( ) , $. now

resolution

echo

,

:

echo "The time is $now $resolution." , : The time is 12390 10ps. ё "\".

,

, , \$now .

Special considerations for $now(

$now) 397

ModelSim

$now

, –

,

vsim (CR-296). , , 1ps),. :

-t $now ( ModelSim> vsim -t 1ps VSIM > echo $now # 0 ,

(

, 10ps), .

- 500ps, 500ps?

, - 10ps, ModelSim

, $now 3-

50

500 .

: ModelSim> vsim -t 10ps VSIM > echo $now # 0 ps ,

when (CR-312), $now. 100,

" when { $now = 100} ... ", ,

.

B - ModelSim shortcuts (

ModelSim) .Wave List

Main

-

Source

, 398

ModelSim GUI.

Wave window mouse and keyboard shortcuts( Wave) ,

< control - left-button - drag down and right>a < control - left-button - drag up and right> < control - left-button - drag up and left> < middle-button - drag> < control - left-button - click on a scroll arrow >

Wave

zoom fit (

) ,

(

) ( )

< middle mouse-button - click in scroll bar trough> (UNIX) a. , Mode > Zoom Mode,

iI

,

+

View > Mouse .

( )

oO

-

( )

f

F

l

L

r

R

( ) ( ) ( )

< up arrow >/ < down arrow >

,

, < left arrow > < right arrow >



Windows UNIX

( (

),

-

),

-

;

399



,

,

,

,

,

,

List window keyboard shortcuts( List) ,

List,

:

(

< left arrow >

) (

< right arrow >

) < up arrow > < down arrow >



(

),

(

),

(

HP)

Windows UNIX

/ ё

Command shortcuts(

Find,

) , , , ModelSim

, .

ё

ё

.

. . .

Command history shortcuts( )

400

, , ModelSim/VSIM:

!! !n

n; n (

,

!abc ^xyz^ab^

VSIM : VSIM 12 >, n =12) , " abc"

"xyz"

"ab"

up and down arrows click on prompt

( ModelSim

)

VSIM ,

-

,

his or history

(

50)

Mouse and keyboard shortcuts in the Main and Source windows( Main Source) , . notepad

, ModelSim ,

- UNIX < left-button - click >

Source

Notepad ( Notepad).

- Windows

< left-button - press > + drag < shift - left-button - press > < left-button - double-click > < left-button - double-click > + drag < control - left-button - click >

< left-button - click > VSIM

+

ModelSim

401

< middle-button - click > < middle-button - press > + drag

UNIX Windows < left | right arrow > < control > < left | right arrow > < shift > < left | right | up | down arrow > < control > < shift > < left | right arrow > < up | down arrow >

| |

(

Source, )

| < control > < up | down > < control > < home > < control > < end > < backspace >, < control-h> < delete >, < control-d > none < alt > < alt > < F4 > < control - a >, < home > < control - b > < control - d > < control - e >, < end > < control - f > < control - k > < control - n >

UNIX < control - o > < control - p > < control - s > < F3 > < control - t > < control - u > < control - v >, PageDn < control - w >, < control - x >,< control -s> < control - y >, F18 none

|

< backspace > < delete > esc

< home >

< end >

( Source

Windows)

Source

Windows)

Windows none ( < control - f >

PageDn < control - x > < control - s > < control - v > < control - a >

widget ( )

< control - \ >

widget 402

< control - - >,< control /> < meta - "" > < meta - v > , PageUp < Meta - w>

< control - Z > Source none none PageUp < control - c >

< F8 > ( Main) < F9> < F10 > < F11 > < F12>

(step-over)

Main

; (

, )

.

Right mouse button(

) .

8 - Graphic Interface(

ModelSim)

C - ModelSim messages(

.

ModelSim)

ModelSim . VCOM VLOG VSIM

403

Tcl

2

,

ё ModelSim.

ModelSim message system(

ModelSim)

ModelSim . Main. (

, "Saving the Main window transcript file( ).

Message format(

Main)"

) :

** : ([[-]]-) :

404

-

Note Warning

,

Error Fatal -

, [email protected] ModelSim , vcom, vdel, vsim, . . .

ERROR ,

Tool Group FLI,PLI, VCD,

,

.

. .

# ** Error: (vsim-PLI-3071) ./src/19/testfile(77): $fdumplimit : .

Getting more information(

) Tool-MsgNum. ,

verror (CR-258).

:

% verror 3071 Message # 3071: Not enough arguments are being passed to the specified system task or function( ).

Suppressing warning messages( ) .

, ,

.

Suppressing VCOM warning messages( VCOM) –nowarn

.

vcom (CR-250), :

vcom -nowarn 1 . , modelsim.ini (

"[vcom] VHDL compiler control variables( [vcom] VHDL )". : 405

1 2 ) 3 4 5

= unbound component( = process without a wait statement(

) wait

= null range( ) = no space in time literal( = multiple drivers on unresolved signal( ) 6 = compliance checks( ) 7 = optimization messages(

)

)

Suppressing VLOG warning messages( VLOG) +nowarn vlog (CR-286), . ,

, .

: vlog +nowarnDECAY

Suppressing VSIM warning messages( VSIM) +nowarn vsim (CR-296), . ,

, .

: vlog +nowarnTFMPC ..

Exit codes(

) ,

ModelSim. Exit code 0 1 2 3

Description (

(execv, ,

4 5 6 7 8

)

,

. .)

create/open/find/read/write create/open/find/read/write open/read/write/dup (open, lseek, write, mmap, munmap,fopen, fdopen, fread, dup2, etc. , ,

9 10 406

11 12 13 14 15

(

create/read/write/close

/

) 16 19 found/unreadable/unexecutable (vlm/mgvlm) 42 43 44

(

)

Modeltech

#44 45

(

) #45 (SEVERITY_QUIT)

90

Modeltech

99 202

(SIGINT)

204

(SIGILL)

205

(SIGTRAP)

206

(SIGABRT)

208 Exit code 210

(SIGFPE) Description (SIGBUS)

211

(SIGSEGV)

213

(SIGPIPE)

214

(SIGALRM)

215 (SIGTERM) 216

1 (SIGUSR1)

217 218

2 (SIGUSR2) (SIGCHLD)

(

)

230 (SIGXCPU) 231

(SIGXFSZ) 407

Miscellaneous messages(

) ,

ModelSim.

Lock message(

)

"waiting for lock by user@user. Lockfile is /_lock"

ё ,

_lock

,

, .

.

,

, ModelSim _lock..

,

_lock .

Tcl Initialization error 2(

2

Tcl_Init Error 2 : : ./. ./tcl/tcl8.3.

Tcl)

Init.tcl

, ModelSim,

Unix.

3

ftp. : • modeltech-base.tar.gz • modeltech-docs.tar.gz • modeltech-.exe.gz < platform >,

Tcl,

. 408

, .

ModelSim

.

Too few port connections(

)

# ** Warning (vsim-3017): foo.v(1422): [TFMPC] # 2, found 1. Region: /foo/tb

.

, . ,

–

;

, ,

Verilog, .

-

, .

,

, , .

: module foo (a, b, c, d); ,

,

:

foo inst1(e, f, g, ); – positional association foo inst1(.a(e), .b(f), .c(g), .d()); – named association ,

,

:

foo inst1(e, f, g); – positional association foo inst1(.a(e), .b(f), .c(g)); – named association d -

,

.

:

foo inst1(e, , g, h); foo inst1(.a(e), .b(), .c(g), .d(h));

•

, (a, b,)).

.( ,

Verilog .

,

,

409

•,

, ,

+nowarnTFMPC

vsim.

D - Using the FLEXlm License Manager (

FLEXlm)

daemon

FLEXlm

daemon

410

Lmstat lmdown lmremove lmreread Windows Model Technology's FLEXlm ModelSim. Globetrotter (FLEXlm Globetrotter Software’s Flexible License Manager) -

,

,

.

FLEXlm FLEXlm Model Technology's. FLEXlm End User’s, Globetrotter: http://www.globetrotter.com/manual.htm

,

Starting the license server daemon( )

daemon

Locating the license file(

)

daemon . c:\flexlm\license.dat ,

, - /usr/local/flexlm/licenses/license.dat , daemon

Windows.

•

: , LM_LICENSE_FILE

•

to find our documentation( [email protected].

Unix

-c . .

ModelSim Model Technology's Start Here for ModelSim, )", email

. " Where

Controlling the license file search(

) 411

Technology

, ModelSim Mentor Graphics.

Model vsim

, MTI,

MGC

vsim (CR-296) :

.

,

-lic_nomgc

MGC

-lic_nomti

MTI ,

-lic_noqueue -lic_plus

PLUS

-lic_vlog

VLOG

-lic_vhdl -lic_viewsim

VHDL ,

License [vsim]

.

modelsim.ini ,

;

.

, License. License nomgc

, -lic_plus

, vsim

MTI SE/PLUS.

Manual start(

)

Unix daemon , //modeltech/

:

cd //modeltech/ lmgrd -c license.dat >& report.log

linux.

sunos5, hp700_1020, hp700, hppa64, rs6000, rs64,

; . Windows daemon modeltech cd \\modeltech\win32 lmgrd -app -c license.dat

Windows, :

412

Automatic start at boot time( ) Unix daemon ,

/etc/rc.boot /etc/rc.local: : //modeltech//lmgrd -c / /license.dat & Windows FLEXlm, .

. FLEXlm End

.

What to do if another application uses FLEXlm( FLEXlm) 1: , ,

SERVER DAEMON, FEATURE,

FEATURESET . / /license/license.dat .

,

2: , . LM_LICENSE_FILE ,

, ,

:

setenv LM_LICENSE_FILE \ lic_file1:lic_file2://license.dat (;)

Windows

. daemon

-c,

.

: lmgrd > report.log

Format of the license file( DAEMON,

ModelSim FEATURE.

) :

SERVER,

:

SERVER hostname hostid [TCP_portnumber] DAEMON daemon-name path-to-daemon [path-to-options-file] FEATURE name daemon-name version exp_date #users_code \ “description” [hostid] : 413

• hostname(

)

• TCP_portnumber •

-daemon

DAEMON

• •

DAEMON -

daemon (

Feature names(

)

)

ModelSim. . ’_c ’

,

dataflow hdlcom, hdlcom_c hdlsim, hdlsim_c vcom, vcom_c vlog, vlog_c vsim, vsim_c vsim-vlog, vsimvlog_c vsim-compare, vsimcompare_c vsim-coverage, vsimcoverage_c vsim-profile, vsimprofile_c vsim-viewer, vsimviewer_c

daemon MGCLD.

(vhdl

verilog)

vhdl verilog vhdl verilog

GUI

Format of the daemon options file( daemon) ModelSim, , ModelSim,

daemon.

, .

RESERVE(

) ,

ModelSim .

INCLUDE(

) , ModelSim.

414

INCLUDE(

) ModelSim

GROUP(

.

) .

NOLOG(

)

daemon's. daemon, daemon DAEMON modeltech. daemon

, :

RESERVE number feature {USER | HOST | DISPLAY | GROUP} name INCLUDE feature {USER | HOST | DISPLAY | GROUP} name EXCLUDE feature {USER | HOST | DISPLAY | GROUP} name GROUP name NOLOG {IN | OUT | DENIED | QUEUED} REPORTLOG file ,

(#) REPORTLOG

logfile

. (+),

. ,

vsim , hostname

, QUEUED vsim.

,

logfile.

RESERVE 1 vsim USER walter RESERVE 3 vsim USER john RESERVE 1 vsim HOST bob EXCLUDE vsim USER rita NOLOG QUEUED : /usr/local/options DAEMON

:

DAEMON modeltech ///modeltech \ /usr/local/options

License administration tools( ) 415

lmstat lmstat. lmstat FLEXlm ,. lmstat

, ,

•

daemons

:

;

•

;

•

,

DAEMON. :

lmstat -a -A -S -c -f -s -t

-a

ё.

-A . -S ,

daemon's.

-c ,

.

-f ( ). -s (

)

.

-t < value > lmstat

.

lmdown lmdown daemons

daemons ( lmgrd )

. 416

lmdown -c [< license_file_path >] , /user/local/flexlm/licenses/license.dat, LM_LICENSE_FILE . ,

lmdown, . since shutting down the servers will cause loss of licenses. .

lmremove lmremove .

, , ,

. . lmremove .

lmremove -c lmremove )c . -c , lmremove, .

(

, . ,

lmreread daemon ,

lmreread daemons daemons

.

,

.

lmreread [daemon] [ -c < license_file >] : daemon, , lmreread

-c, ,

lmgrd. lmgrd

.

, 417

.

daemons

lmreread.

Administration tools for Windows ( Windows) Unix, . , Windows, "lmutil".

Windows ,

lmstat, :

lmutil lmstat [-args] Windows -

,

Unix.

E - System initialization(

)

ModelSim

, .

, , ,

,

. .

Files accessed during startup( ) 418

,

.

,

.

modelsim.ini

; "

,

INI " modelsim.INI location map file

ModelSim ,

, " soft ";

- mgc_location_map;

" How location mapping )"

works( pref.tcl

, , , " Preference variables located in Tcl files , Tcl)" pref.tcl

, ; ( modelsim.tcl ,

,

,

, ;

" Preference variables ,

located in Tcl files ( Tcl)" modelsim.tcl

Environment variables accessed during startup( ) , , ,

. . " Environment variables (

)"

. MODEL_TECH

ModelSim

, (

, ../modeltech /

platform < > /) MODEL_TECH_ OVERRIDE MODELSIM MGC_WD MGC_LOCATION_MAP

; MODEL_TECH – modelsim.ini Mentor Graphics ; ModelSim,

MODEL_TECH_TCL

Tcl, ModelSim

HOME MGC_HOME TCL_LIBRARY

( MGC ModelSim

UNIX)

Tcl; MODEL_TECH_TCL; 419

,

Model Technology Tk; ModelSim MODEL_TECH_TCL; , Model Technology [incr] Tcl; ModelSim MODEL_TECH_TCL; , Model Technology [incr] Tk; ModelSim MODEL_TECH_TCL; , Model Technology Tcl, ModelSim; ModelSim MODEL_TECH_TCL; , Model Technology mti_trace_cosim, FLI/PLI/VPI; . Tcl, ModelSim modelsim.tcl ; ё , (Windows) (UNIX)

TK_LIBRARY

ITCL_LIBRARY

ITK_LIBRARY

VSIM_LIBRARY

MTI_COSIM_TRACE

MTI_LIB_DIR MODELSIM_TCL (

Initialization sequence(

) ModelSim. ,

. , (

MTI_LIB_DIR, ,

Tcl). $(NAME) $ (MTI_LIB_DIR)

( Tcl).

1 MODEL_TECH , , MODEL_TECH MODEL_TECH_OVERRIDE 2 • • • • • •

(../modeltech / < platform > /). MODEL_TECH_OVERRIDE

modelsim.ini,

:

MODELSIM ; $(MGC_WD)/modelsim.ini; ./modelsim.ini; $(MODEL_TECH)/modelsim.ini; $(MODEL_TECH)/../modelsim.ini; $(MGC_HOME)/lib/modelsim.ini; 420

•

,

. /modelsim.ini ,

3 •

:

MGC_LOCATION_MAP "no_map", ModelSim

• • • • • • • •

(

);

mgc_location_map ; $(HOME)/mgc/mgc_location_map; $(HOME)/mgc_location_map; $(MGC_HOME)/etc/mgc_location_map; $(MGC_HOME)/shared/etc/mgc_location_map; $(MODEL_TECH)/mgc_location_map; $(MODEL_TECH)/../mgc_location_map; no map [vsim] modelsim.ini "

4 " [vsim]

. .

, .

5 ModelSim

,

:

6 • • • • • • •

MODEL_TECH_TCL ; MODEL_TECH_TCL=$(MODEL_TECH)/../tcl TCL_LIBRARY=$(MODEL_TECH_TCL)/tcl8.3 TK_LIBRARY=$(MODEL_TECH_TCL)/tk8.3 ITCL_LIBRARY=$(MODEL_TECH_TCL)/itcl3.0 ITK_LIBRARY=$(MODEL_TECH_TCL)/itk3.0 VSIM_LIBRARY=$(MODEL_TECH_TCL)/vsim Tcl

7

.

(

8

, ).

modelsim.ini .

Tcl "MTI_LIB_DIR"=MODEL_TECH_TCL

9 10

$(MTI_LIB_DIR)/pref.tcl. , project init , , (Windows) $ (HOME) /.modelsim (UNIX).

11 12

:

modelsim.tcl,

•

MODELSIM_TCL , ,

(

MODELSIM_TCL ,

); •

./modelsim.tcl; 421

•

$(HOME)/modelsim.tcl .

modelsim.ini : • [vcom],

ModelSim, modelsim.ini.

[vlog]

[

],

vmap, . • pref.tcl [GetPrivateProfileString]. .ini, , pref.tcl.

.ini

Tcl ,

F - Tips and Techniques(

) /

–nodebug

(DO

)

bit_vector 32-

64422

HP-UX 10.2 Sun/Solaris

VHDL

, , .

How to use checkpoint/restore( / ) checkpoint (CR-82)

restore (CR-204) vsim

vsim. restore (CR-

vsim, 204) ,

" warm restore(

) ". -

vsim , -restore

vsim (CR-296)

" cold restore(

) ".

423

/

: ,

, .

, , .

, :

restore • • vsim.wlf •

,

•

VHDL

•

,

Verilog $fopen

• •

PLI ,

:

• •

,

( Tcl)

• • ,

,

checkpoint , ,

:

restore ModelSim, : vsim -restore [-nocompress]

vsim

. , ,

Tcl.

:

424

set CheckpointCompressMode 0 ,

:

set CheckpointCompressMode 1 , 0

[vsim] (

modelsim.ini 1):

[vsim] CheckpointCompressMode = , ,

checkpoint/restore. .

FLI

The difference between checkpoint/restore and restarting ( / ) , VHDL

restart (CR-202) ,

,

Verilog $fopen. . ,

. ,

,

checkpoint/restore.

Using macros with restart and checkpoint/restore (

checkpoint/restore.) ,

restart (CR-202) , .

restart

.. ,

. ,

, . checkpoint/restore

checkpoint (CR-82)

,

ModelSim, restore (CR-

204) . ,

checkpoint

restore

.

Running command-line and batch-mode simulations ( ) 425

ModelSim GUI (

:

).

ModelSim: GUI, . •

,

:

GUI -

;

, .

,

,

-

.

• ,

; .

vsim UNIX

c

, DOS WINDOWS .

-

• UNIX ,

,

, , vsim

. ,

“ Windows , vsim

-

”.

-c. WINDOWS .

“here-

document”: vsim ent arch / < Project_Name > .mpf).

MODELSIM

Batch mode(

) ModelSim

,

,

stdout. ,

stdin –c vsim ,

-c .

Tcl user_hook

Tcl

. "Making the button persistent(

)"

.

Source code security and -nodebug( nodebug) -nodebug .

vcom (CR-250)

–

vlog (CR-286) -

. :

-nodebug ,

. Verilog,

protect Cadence,

ModelSim , Model Technology. 427

,

Source

-nodebug, Structure

, Signals Process

),

( ,

Variables

. , Dataflow

ModelSim. ,

-nodebug -nodebug

.

, vsim (CR-296) .

, , ,

-nodebug ,

-nodebug. , .

-nodebug,

vcom -nodebug=ports vlog -nodebug=ports vlog -nodebug=pli

VHDL Verilog PLI

vlog nodebug=ports+pli ( =pli+ports)

-nodebug=ports

:

-nodebug=pli

,

=ports ;

,

.

, -nodebug=ports , -nodebug. vcom (VHDL ). PLI Verilog.

= pli

,

Saving and viewing waveforms in batch mode( ) ,

vsim . 1

vsim, WLF (wave log format),

,

-wlf, stdin, :

.

vsim - wlf wavesav1.wlf counter < command.do command.do,

log (CR-164), ,

428

,

.

,

vsim

,

. ,

2

,

vsim :

.wlf vsim -view wavesav1.wlf

Waveform

List

.

Setting up libraries for group use ( “

”

, ModelSim

modelsim.ini . modelsim.ini, “

,

)

”

.

: [library] asic_lib = /cae/asic_lib work = my_work others = /usr/modeltech/modelsim.ini

Using a DO file to test for assertions ( DO

)

onbreak (CR-177) DO .

,

, BreakOnAssertion ( " ). ;

" [vsim] .

,

onbreak

: set broken 0 onbreak { set broken 1 resume } run -all if { $broken } { puts "failure" } else { puts "success" }

Sampling signals at a clock change( ) 429

add list (CR-48 )

, notrigger. -notrigger

-

.

:

add list clk -notrigger a b c ,

List

clk, a, b,

.

clk

,

:

List

1

, .

2 , Builder(

"

"

List, " Configuring a List trigger with Expression )"

. List

Converting signal values to strings( ) . " idle(

) ".

, virtual type (CR-283)

, .

,

GUI.

: ,

1

:

virtual type { state0 state1 state2 state3} myState 2 virtual function {(mystate)mysignal} myConvertedSignal 3 add wave myConvertedSignal myConvertedSignal "state0" mysignal == 0, "state1" mysignal == 2, . . virtual type (CR-283) .

Wave, List Signals, mysignal == 1, "state2" К

ModelSim

Converting an integer into a bit_vector( bit_vector) ,

bit_vector.

library ieee; 430

use ieee.numeric_bit.ALL; entity test is end test; architecture only of test is signal s1 : bit_vector(7 downto 0); signal int : integer := 45; begin p:process begin wait for 10 ns; s1 Simulation Options , modelsim.ini , , Tcl IterationLimit . . " Preference variables located in INI files( , INI )" modelsim.ini. . " Preference variables 434

located in TCL files(

,

TCL

Tcl

)"

.

,

.

,

,

.

, .

-

,

,

,

.

Referencing source files with location maps (

) ,

. . ModelSim, , •

: , .

•

,

, .

, . , .

,

,

-

Using location mapping(

) , . .

ModelSim , MGC_LOCATION_MAP. MGC_LOCATION_MAP , ModelSim , "mgc_location_map" ,

:

• • • •

,

ModelSim ModelSim

435

,

:

1

MGC_LOCATION_MAP

. 2

:

$SRC /home/vhdl/src /usr/vhdl/src $IEEE /usr/modeltech/ieee

Pathname syntax(

) $,

/. .

, (

).

How location mapping works( ) ,

, .

, ,

. , "/usr/vhdl/src/test.vhd"

. ,

" $SRC/test.vhd ". ,

.

. , ModelSim , (

). ModelSim

,

. , ModelSim

. ,

ё "/home/vhdl/src".

Mapping with Tcl variables( Tcl SourceMap.

SRC, ModelSim

Tcl)

, ; SourceDir . http://www.model.com/resources/pref_variables/frameset.htm. 436

Improve performance by locking memory on HP-UX 10.2 ( UX 10.2) ModelSim 5.3 10.2

,

HPHP-UX

. -

500

(.

>

2x

.)

Configuring memory locking(

)

,

HP-UX 10.2,

. .

1 ,

,

.

MLOCK,

, ModelSim:

/usr/sbin/setprivgrp -g MLOCK MLOCK,

:

/usr/sbin/setprivgrp MLOCK .

.

MLOCK,

2 modelsim.ini,

[vsim]:

LockedMemory = ,

, , vsim

.

, .ini).

(

Limitations(

)

ModelSim

. ,

( ModelSim , ,

: ) - 100 , ,

=

. . . 437

System parameter setting(

)

,

/ (

)

"sam" ,

, HP-UX. "Kernel Configuration"). .

"Configurable Parameters" ( ,

,

. "shmmin"

"shmmax" "shmseg"

"shmem"

1.

. ,

ok. .

Improve performance of large simulations on Sun/Solaris( Sun/Solaris) ModelSim 5.5b Sun/Solaris

. Verilog, .

Enabling shared memory( ) ,

: ,

1 /etc/system: set shmsys:shminfo_shmmax=0xffffffff .

2 ,

3 vshminit (

, modeltech).

.

,

, vshminit

,

:

/sunos5/vshminit 700 700 ё.

. ,

,

: vshminit .(

ё

,

.)

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Run (

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License Agreement(

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