Verilog Basics Handout_MEC [1]

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BASICS OF VERILOG Faculty: Jagadeesh Kumar P

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The People

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Linux Distributions

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Hardware Description Language (HDL)

A hardware description language (HDL) is a specialized computer language used to describe the structure and behavior of electronic circuits, and most commonly, digital logic circuits. A hardware description language enables a precise, formal description of an electronic circuit that allows for the automated analysis and simulation of an electronic circuit. It also allows for the synthesis of an HDL description into a netlist (a specification of physical electronic components and how they are connected together), -

which can then be placed and routed to produce the set of masks used to create an integrated circuit.

source: https://en.wikipedia.org/wiki/Hardware_description_language# 8

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Icarus Verilog with GTKWave

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edaplayground.com

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Design Entry Verilog module A module is a block of Verilog code that implements certain functionality. Modules can be embedded within other modules, and a higher level module can communicate with its lower-level modules using their input and output ports. Syntax. A module should be enclosed within a module and endmodule keywords.

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Design Entry Design entry creates an HDL-based description of the functionality that is to be implemented in hardware.

Depending on the HDL, the description can be in a variety of forms: -

Boolean logic equations, truth tables, a netlist of interconnected gates or an abstract behavioral model.

The HDL model may also represent a partition of a larger circuit into smaller interconnected and interacting functional units. 13

Logic Simulation

Logic simulation displays the behavior of a digital system through the use of a computer. A simulator interprets the HDL description and either producer readable output, such as a time ordered sequence of input and output signal values or displays waveforms of the signals. The simulation of a circuit predicts how the hardware will behave before it is actually fabricated. Simulation allows the detection of functional errors in a design without having to physically create and operate the circuit. 14

Logic Simulation - Readable Output

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Logic Simulation - Display Waveform user@user-HP-Laptop-15s-gr0xxx:~/MEC/BTech_2022_23/LCD_BTech_2022/Verilog_Codes/2_Ha lf_Adder$ gtkwave dump.vcd

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Design Entry - Half Adder Half adders are a basic building block for new digital designers. A half-adder shows how two bits can be added together with a few simple logic gates.

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Design Entry Verilog module - half_adder.v

user@user-HP-Laptop-15s-gr0xxx:~/MEC/BTech_2022_23/LCD_BTech_2022/Verilog_Codes/2_ Half_Adder$ nano half_adder.v

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Design Entry Verilog module - half_adder.v i_bit1, i_bit2, o_sum, and o_carry are the ports or connections to the module. Every module end with the keyword endmodule. In the beginning of a module, we have to declare all ports as input, output or inout. By default, ports will have one pin or one bit.

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Design Entry Verilog module - half_adder.v Using 'assign' statement, we connected inputs and outputs via gates. i_bit1 will be XOR ed with i_bit2 and will be connected to o_sum. Here, we are not going to store the values, and hence we did not declare any registers. By default, all the ports will be considered as wires. If we want the output to be latched, we have to declare it using the keyword 'reg'.

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Design Entry - Half Adder - Test Bench Next write a testbench to test the module that we have created.

Testbench is another verilog code that creates a circuit involving the circuit to be tested.

This code will send different inputs to the code under test and get the output and displays to check the accuracy.

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Design Entry - Half Adder Test Bench

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Design Entry - Half Adder Test Bench Verilog module - half_adder_tb

Here we have created another module half_adder_tb which will include the module half_adder.

We have to give values to input, so we need to store or latch the input data.

So, r_BIT1 and r_BIT2 are declared as reg and w_SUM and w_CARRY as wire to get the output value from the gate.

Now, we create an instance of half_adder. i.e., we are placing the module that we created previously inside this module.

We can use two different notations to connect the ports. 23

Design Entry - Half Adder Test Bench Verilog module - half_adder_tb We can use two different notations to connect the ports. 1.

Instantiating by order.

half_adder half_adder_inst

( r_BIT1, r_BIT2, w_SUM,

w_CARRY); Here, all the ports should be in the order as we declared in the module definition. 2.

Instantiating by name.

half_adder half_adder_inst

( .i_bit1(r_BIT1),

.i_bit2(r_BIT2), .o_sum(w_SUM), .o_carry(w_CARRY) );

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Design Entry - Half Adder Test Bench i_bit1 in the half_adder will be connected to r_BIT1 in the half_adder_tb and so on. If some of the statements in our code is to be executed only in the beginning of the execution, we can write them using initial block. initial block executes only once and starts at time=0. We can have any number of initial blocks. initial block begins with begin and ends with end. Inside an initial block, statements will execute sequentially.

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Design Entry - Half Adder Test Bench $monitor is a system task used to display the values in variable whenever value of one of its arguments changes. After that we will assign different values to r_BIT1 and r_BIT2. Here 1'b0 indicates a low signal and 1'b1 represents a high signal. Similarly we can also indicate decimal, hex, octal numbers as follows. #10 indicates a delay of 10ns. To observe the changes in the output waveform, we need to include this delay. 26

Design Entry - Half Adder Test Bench Similarly we can also indicate decimal, hex, octal numbers as follows. Rules: ●

1: Active high bit

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0: Active low bit

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z: high impedance

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x: Uncertain/ Don't care

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If not mentioned, length is 32 bit and data type is integer by default.

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If value is larger than the length, left most bits will be truncated

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If value is smaller, ○

0's are filled to the left if left most bit is 0 or 1

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'z' are filled if left most bit is z

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'x' are filled if left most bit is x

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Design Entry - Half Adder Test Bench $dumpfile("dump.vcd");

The $dumpvars is used to dump the changes in the values of nets and registers in a file that is named as its argument. For example $dumpfile("dump.vcd") will dump the changes in a file named dump.vcd. The changes are recorded in a file called VCD file that stands for value change dump. A VCD (value change dump) stores all the information about value changes. We can not have more than one $dumpfile statements in verilog simulation.

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Design Entry - Half Adder Test Bench The $dumpvars is used to specify which variables are to be dumped ( in the file mentioned by $dumpfile).

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Hardware Description Language (HDL)

A hardware description language looks much like a programming language such as C or ALGOL; it is a textual description consisting of expressions, statements and control structures. One important difference between most programming languages and HDLs is that HDLs explicitly include the notion of time. HDLs form an integral part of electronic design automation (EDA) systems, especially for complex circuits, such as -

application-specific integrated circuits, microprocessors, and programmable logic devices.

source: https://en.wikipedia.org/wiki/Hardware_description_language# 30

Hardware Description Language (HDL) Due to the exploding complexity of digital electronic circuits since the 1970s (see Moore's law), circuit designers needed digital logic descriptions to be performed at a high level -

without being tied to a specific electronic technology, such as ECL, TTL or CMOS.

HDLs were created to implement register-transfer level abstraction, a model of the data flow and timing of a circuit. There are two major hardware description languages: VHDL and Verilog. There are different types of description in them: "dataflow, behavioral and structural".

source: https://en.wikipedia.org/wiki/Hardware_description_language# 31

Verilog - Hardware Description Language (HDL)

Verilog is a HARDWARE DESCRIPTION LANGUAGE (HDL). It is a language used for describing a digital system like a network switch or a microprocessor or a memory or a flip−flop. By using a HDL we can describe any digital hardware at any level. Designs, which are described in HDL are independent of technology, very easy for designing and debugging, and are normally more useful than schematics, particularly for large circuits.

source: https://www.tutorialspoint.com/vlsi_design/vlsi_design_verilog_introduction.htm# 32

Verilog - Hardware Description Language (HDL)

Verilog supports a design at many levels of abstraction. The major three are − ● Behavioral level ● Register-transfer level ● Gate level

source: https://www.tutorialspoint.com/vlsi_design/vlsi_design_verilog_introduction.htm# 33

Verilog - Hardware Description Language (HDL) Behavioral level

This level describes a system by concurrent algorithms (Behavioural). Every algorithm is sequential, which means it consists of a set of instructions that are executed one by one. Functions, tasks and blocks are the main elements. There is no regard to the structural realization of the design.

Source: https://www.tutorialspoint.com/vlsi_design/vlsi_design_verilog_introduction.htm# 34

Verilog - Hardware Description Language (HDL) Register−Transfer Level

Designs using the Register−Transfer Level specify the characteristics of a circuit using operations and the transfer of data between the registers. Modern definition of an RTL code is "Any code that is synthesizable is called RTL code".

source: https://www.tutorialspoint.com/vlsi_design/vlsi_design_verilog_introduction.htm# 35

Verilog - Hardware Description Language (HDL)

Gate Level Modelling Verilog has built-in primitives like logic gates, transmission gates and switches. These are rarely used for design work -

but they are used in post synthesis world for modelling of ASIC/FPGA cells.

Gate level modelling exhibits two properties -

Drive strength

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Delays

source: https://www.tutorialspoint.com/vlsi_design/vlsi_design_verilog_introduction.htm#

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Verilog - Hardware Description Language (HDL)

Gate Level Modelling Gate level modelling exhibits two properties − Drive strength − The strength of the output gates is defined by drive strength. The output is strongest if there is a direct connection to the source. The strength decreases if the connection is via a conducting transistor and least when connected via a pull-up/down resistive. The drive strength is usually not specified, in which case the strengths defaults to strong1 and strong0. source: https://www.tutorialspoint.com/vlsi_design/vlsi_design_verilog_introduction.htm#

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Verilog - Hardware Description Language (HDL)

Gate Level Modelling Gate level modelling exhibits two properties − Delays − If delays are not specified, then the gates do not have propagation delays; if two delays are specified, then first one represents the rise delay and the second one, fall delay; if only one delay is specified, then both, rise and fall are equal. Delays can be ignored in synthesis.

source: https://www.tutorialspoint.com/vlsi_design/vlsi_design_verilog_introduction.htm#

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Verilog - Hardware Description Language (HDL)

Gate Level Modelling Within the logical level, the characteristics of a system are described by logical links and their timing properties. All signals are discrete signals. They can only have definite logical values (`0', `1', `X', `Z`). The usable operations are predefined logic primitives (basic gates). Gate level modelling may not be a right idea for logic design. Gate level code is generated using tools like synthesis tools and his netlist is used for gate level simulation and for backend. source: https://www.tutorialspoint.com/vlsi_design/vlsi_design_verilog_introduction.htm#

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Verilog - Hardware Description Language (HDL) Gate Primitives The basic logic gates using one output and many inputs are used in Verilog. GATE uses one of the keywords - and, nand, or, nor, xor, xnor for use in Verilog for N number of inputs and 1 output.

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Verilog - Hardware Description Language (HDL) Gate Primitives

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Verilog - Hardware Description Language (HDL) Transmission Gate Primitives

Transmission gate primitives include both, buffers and inverters. They have single input and one or more outputs. In the gate instantiation syntax shown below, GATE stands for either the keyword buf or NOT gate.

Example: Not, buf, bufif0, bufif1, notif0, notif1 Not – n outout inverter Buf – n output buffer Bufifo – tristate buffer, active low enable Bufif1 – tristate buffer, active high enable Notifo – tristate inverter, active low enable Notif1 – tristate inverter, active high enable

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Verilog - Hardware Description Language (HDL)

Transmission Gate Primitives Transmission gates tran and rtran are permanently on and do not have a control line. Tran can be used to interface two wires with seperate drives, and rtran can be used to weaken signals.

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Verilog - Hardware Description Language (HDL) Switch Primitives

Six different switch primitives (transistor models) are used in Verilog, -

nmos, pmos and cmos and the corresponding three resistive versions rnmos, rpmos and rcmos.

The cmos type of switches have two gates and so have two control signals. Syntax: keyword unique_name (drain. source, gate)

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Verilog - Hardware Description Language (HDL) Switch Primitives

All the switches only pass signals from source to drain, incorrect wiring of the devices will result in high impedance outputs. 45

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Verilog Data Types - Value Set

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Verilog Data Types - Wire A wire is used to represent a physical wire in a circuit and it is used for connection of gates or modules.

The value of a wire can only be read and not assigned in a function or block.

A wire cannot store value but is always driven by a continuous assignment statement or by connecting wire to output of a gate/module.

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Verilog Data Types - Wire Other specific types of wires are − Wand (wired-AND) − here value of Wand is dependent on logical AND of all the device drivers connected to it. Wor (wired-OR) − here value of a Wor is dependent on logical OR of all the device drivers connected to it. Tri (three-state) − here all drivers connected to a tri must be z, except only one (which determines value of tri).

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Verilog Data Types - Register A reg (register) is a data object, which is holding the value from one procedural assignment to next one and -

are used only in different functions and procedural blocks.

A reg is a simple Verilog, variable-type register and can’t imply a physical register. In multi-bit registers, the data is stored in the form of unsigned numbers and sign extension is not used. Example − reg c; // single 1-bit register variable reg [5:0] gem; // a 6-bit vector; reg [6:0] d, e; // two 7-bit variables

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Verilog Data Types - Input, Output, Inout These keywords are used to declare input, output and bidirectional ports of a task or module. Here input and inout ports, which are of wire type and output port is configured to be of wire, reg, wand, wor or tri type. Always, default is wire type.

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Verilog Data Types - Parameter A parameter is defining a constant which can be set when we use a module - which allows customization of module during the instantiation process.

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Verilog HDL - Lexical Tokens Verilog language source text files are a stream of lexical tokens. The tokens can be keywords, comments, numbers, white space, or strings. Verilog is case sensitive. All the key words are in lower case.

White Space White space characters are Blank space, Tabs, Carriage returns, New line, and Form feeds.

These characters are ignored except when they serve to separate tokens.

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Verilog HDL - Lexical Tokens Comments There are two forms to represent the comments ●

1) Single line comments begin with the token // and end with carriage return.

Ex.: //this is single line syntax ●

2) Multiline comments begins with the token /* and end with token */

Ex.: /* this is multiline Syntax*/

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Verilog HDL - Lexical Tokens Numbers We can specify a number in binary, octal, decimal or hexadecimal format. Negative numbers are represented in 2’s complement numbers. Verilog allows integers, real numbers and signed & unsigned numbers. The syntax is given by − Size or unsized number can be defined in and defines whether it is binary, octal, hexadecimal or decimal.

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Verilog HDL - Lexical Tokens

Identifiers Identifier is the name used to define the object, such as a function, module or register. Identifiers are names that are given to elements such as modules, registers, ports, wires, instances, and procedural blocks. An identifier is any sequence of letters, digits, and the underscore (_) symbol except that: - the first character must not be a digit, and the identifier must be 1024 characters or less. 57

Verilog HDL - Lexical Tokens

Identifiers Identifier is the name used to define the object, such as a function, module or register. Identifiers should begin with an alphabetical characters or underscore characters. Ex. A_Z, a_z, _ Identifiers are a combination of alphabetic, numeric, underscore and $ characters. They can be up to 1024 characters long. 58

Verilog HDL - Lexical Tokens Verilog Keywords

Words that have special meaning in Verilog are called the Verilog keywords. For example, assign, case, while, wire, reg, and, or, nand, and module. They should not be used as identifiers. Verilog keywords also include compiler directives, and system tasks and functions.

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Verilog HDL - Lexical Tokens Verilog Keywords

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Verilog HDL - Lexical Tokens Operators Operators are special characters used to put conditions or to operate the variables. There are three sorts of operators: unary, binary, and ternary. The operand is preceded by unary operators. Between two operands, binary operators occur. Two operators split three operands into ternary operators. X = ~ Y; // X = Y && Z; X = Y ? Z : A;

~ is unary operator // && is binary operator // ?: is ternary operator 61

Verilog HDL - Lexical Tokens X = Y ? Z : A;

// ?: is ternary operator

The question mark is known in Verilog as a conditional operator though in other programming languages it also is referred to as a ternary operator, an inline if, or a ternary if. It is used as a short-hand way to write a conditional expression in Verilog (rather than using if/else statements). condition ? value_if_true : value_if_false Here, condition is the check that the code is performing. This condition might be things like, “Is the value in A greater than the value in B?” or “Is A=1?”. Depending on if this condition evaluates to true, the first expression is chosen. If the condition evaluates to false, the part after the colon is chosen. I wrote an example of this. 62

Verilog HDL - Lexical Tokens X = Y ? Z : A;

// ?: is ternary operator

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Verilog HDL - Arithmetic Operators

The Operators which are included in arithmetic operation are − + (addition),

−(subtraction),

/ (division),

% (modulus)

* (multiplication),

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Verilog HDL - Relational Operators These operators compare two operands and return the result in a single bit, 1 or 0. Wire and reg variables are positive. The Operators which are included in relational operation are − ●

== (equal to)

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!= (not equal to)

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> (greater than)

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>= (greater than or equal to)

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< (less than)

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