SEPTEMBER 2010 IEEE MTT-V058-I09 (2010-09) [58, 9 ed.]

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SEPTEMBER 2010

VOLUME 58

NUMBER 9

IETMAB

(ISSN 0018-9480)

Editorial: Message From the Outgoing Editors ... ........ ......... ......... ........ ......... .. A. Mortazawi and D. Williams

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PAPERS

Linear and Nonlinear Device Modeling Temperature-Dependent RF Small-Signal and Noise Characteristics of SOI Dynamic Threshold Voltage MOSFETs .. .. .. ........ ......... . S.-C. Wang, P. Su, K.-M. Chen, K.-H. Liao, B.-Y. Chen, S.-Y. Huang, C.-C. Hung, and G.-W. Huang Active Circuits, Semiconductor Devices, and ICs A Direct-Conversion CMOS RF Receiver Reconfigurable From 2 to 6 GHz ... . J. Park, S.-N. Kim, Y.-S. Roh, and C. Yoo A 20-Gs/s Track-and-Hold Amplifier in InP HBT Technology .. .......... ........ .. S. Yamanaka, K. Sano, and K. Murata Wideband Common-Gate CMOS LNA Employing Dual Negative Feedback With Simultaneous Noise, Gain, and Bandwidth Optimization ....... ......... ......... ........ ......... ......... ........ J. Kim, S. Hoyos, and J. Silva-Martinez

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Ferroelectric and Ferrite Components Microwave Power Limiting Devices Based on the Semiconductor–Metal Transition in Vanadium–Dioxide Thin Films .. .. ........ ....... J. Givernaud, A. Crunteanu, J.-C. Orlianges, A. Pothier, C. Champeaux, A. Catherinot, and P. Blondy

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Wireless Communication Systems Digitally Driven Antenna for HF Transmission .. ........ ......... ......... .... S. D. Keller, W. D. Palmer, and W. T. Joines A Technique for Implementing Wide Dynamic-Range Polar Transmitters .... J.-H. Chen, H.-S. Yang, and Y.-J. E. Chen

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CAD Algorithms and Numerical Techniques An Efficient Bilateral Dual-Grid-FDTD Approach Applied to On-Body Transmission Analysis and Specific Absorption Rate Computation ...... ........ ......... ......... ........ ......... ......... ........ ...... C. Miry, R. Loison, and R. Gillard

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(Contents Continued on Back Cover)

(Contents Continued from Front Cover) Filters and Multiplexers Generalized Miniaturization Method for Coupled-Line Bandpass Filters by Reactive Loading . ... ..... S. Lee and Y. Lee Group-Delay Engineered Noncommensurate Transmission Line All-Pass Network for Analog Signal Processing ...... .. .. ........ ......... ......... ........ ......... ......... S. Gupta, A. Parsa, E. Perret, R. V. Snyder, R. J. Wenzel, and C. Caloz Packaging, Interconnects, MCMs, Hybrids, and Passive Circuit Elements Flip-Chip-Based Multichip Module for Low Phase-Noise -Band Frequency Generation ...... ........ ......... ......... .. .. ........ . L.-H. Hsu, D. Kuylenstierna, R. Kozhuharov, M. Gavell, C. Kärnfelt, W.-C. Lim, H. Zirath, and E. Y. Chang A Waveguide to Unenclosed Coplanar Waveguide Transition ... ......... ........ . T. Reck, R. M. Weikle, and N. S. Barker 65-, 45-, and 32-nm Aluminium and Copper Transmission-Line Model at Millimeter-Wave Frequencies ...... ......... .. .. ........ ......... ......... ........ ......... ......... ........ .... T. Quémerais, L. Moquillon, J.-M. Fournier, and P. Benech Physics-Based Inductance Extraction for Via Arrays in Parallel Planes for Power Distribution Network Design ........ .. .. ........ ......... ......... ........ ......... ......... ........ ......... ......... ........ ......... ....... J. Kim, L. Ren, and J. Fan A Methodology for Combined Modeling of Skin, Proximity, Edge, and Surface Roughness Effects ... ......... ......... .. .. ........ ......... ......... ........ ......... ......... ........ ......... ........ B. Curran, I. Ndip, S. Guttowski, and H. Reichl -Band Reduced-Height Waveguide-to-Microstrip Transition With a Short Transition Length ........ ......... .. A Full .. ........ ......... ......... ........ ......... ......... ........ ......... ......... ........ ......... ....... H.-S. Oh and K.-W. Yeom Impedance-Transforming Symmetric and Asymmetric DC Blocks ....... ........ ......... ......... ... H.-R. Ahn and T. Itoh Pole-Perturbation Theory for Nonlinear Noise Analysis of All-Pole RF MEMS Tunable Filters ........ ......... ......... .. .. ........ ......... ......... ........ ......... ......... ........ ......... ......... ........ ......... ........ V. Sekar and K. Entesari Instrumentation and Measurement Techniques Characterization of GaN HEMT Low-Frequency Dispersion Through a Multiharmonic Measurement System ......... .. .. ........ ......... ......... ........ ......... ......... ........ ......... ........ A. Raffo, S. D. Falco, V. Vadalà, and G. Vannini Accuracy Improvement for Line-Series-Shunt Calibration in Broadband Scattering-Parameter Measurements With Applications of On-Wafer Device Characterization ... ......... ........ C. C. Huang, Y. H. Lin, and M. Y. Chang-Chien Ultra-Wideband Chip Attenuator for Precise Noise Measurements at Cryogenic Temperatures . ........ ......... ......... .. .. ........ ......... ......... ........ ......... ......... ........ ......... ...... J. L. Cano, N. Wadefalk, and J. D. Gallego-Puyol Microwave Photonics New CMOS-Compatible Micromachined Embedded Coplanar Waveguide ..... ......... ......... . C.-P. Lin and C. F. Jou

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LETTERS

Comments on “A Novel Vector Network Analyzer” ..... ......... ......... ........ ......... ......... ........ ..... U. C. Hasar Authors’ Reply ... ......... ........ ......... ......... ....... .. ......... ......... ........ ......... ...... K. Hoffmann and Z. Skvor Corrections to “Modified Adaptive Prototype Inclusive of the External Couplings for the Design of Coaxial Filters” .. .. .. ........ ......... ......... ........ ......... ......... ........ ......... ......... ........ ......... .... A. Morini and G. Venanzoni

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Information for Authors .. ........ ......... ......... ........ ......... .......... ........ ......... ......... ........ ......... ......... .

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CALLS FOR PAPERS

Special Issue on RF Nanoelectronics ..... ......... ........ ......... ......... ........ ......... ......... ........ ......... ......... .

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Editorial: Message From the Outgoing Editors

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OME FOUR years ago, we took the responsibility for editing this TRANSACTIONS. Our editorial duties have now ended. It has been a privilege and honor to serve our readers and our authors. Throughout the last four years, our greatest concern has been to maintain the high standards and quality of our society’s flagship publication. While this has been a rewarding experience, it has not been without its challenges. Obtaining reliable and timely reviews from true experts in the field is one of the greatest challenges that archival journals face. This TRANSACTIONS has been most fortunate to have a large number of dedicated experts as members of its Editorial Board who spend countless hours helping the editors in evaluating hundreds of manuscripts. During our term as Editors-in-Chief of this TRANSACTIONS, to better show our gratitude for all the help from our reviewers, we initiated a reviewers’ reception at the 2007 IEEE Microwave Theory and Techniques Society (IEEE MTT-S) International Microwave Symposium (IMS), Honolulu, HI. This venue has given us the opportunity to meet and thank in person many of our Editorial Board members. To further recognize our most active reviewers, we have decided to publish the names of 200 of our outstanding reviewers Digital Object Identifier 10.1109/TMTT.2010.2059211

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Outstanding Reviewers 2006–2010

H. R. Ahn S. Aksoy S. Amari K. S. Ang J. Archer F. Arndt A. Atia A. Aydiner A. Babakhani I. Bahl B. Bakkaloglu A. Banai S. Banba I. Bardi S. Barker M. Berroth M. Bialkowski E. Biebl P. Blondy L. Boglione V. Boria Esbert O. Boric-Lubecke J. Bornemann S. Boumaiza T. Brazil K. Breuer P. Cabral E. Camargo R. Cameron C. Campbell N. B. Carvalho K. Chang H. Chapell J. Chen K. K. Cheng Y. C. Chiang Y.-C. Chiou J. Choi H. R. Chuang P. Colantonio

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A. Hung T. Itoh R. Jackson A. Jacob J. Jeong S. Jeon S. Kanamaluru R. Kaul A. Khalil A. Khanna B. Kim J.-H. Kim R. Knoechel J. Komiak J. Krupka D. Kryger C.-N. Kuo J.-T. Kuo G. Kyriacou L. Larson D. Leenaerts R. Levy E. Limiti J. Lin Y. S. Lin C. Liu L. H. Lu V. Lubecke S. Lucyszyn G. Lyons S. Maas G. Macchariella M. Madihian R. Mansour D. Manstretta S. G. Mao G. Matthaei S. Mazumder A. Mazzanti F. Medina

W. Menzel F. Miranda R. Miyamoto S. Mohammadi M. Mongiardo A. Morini A. Morris J. C. Nallatamby S. Nam A. M. Niknejad K. Nishikawa M. Odyniec A. Omar B. L. Ooi S. Ortiz D. Pasquet J. C. Pedro R. Pengelly A. V. Pham M. Pirola C. Plett M. Pospieszalski F. Raab V. Radisic J. Rautio G. Rebeiz J. Rebollar V. Rizzoli I. Robertson U. Rohde D. Root U. Rosenberg T. Rozzi M. Rudolph P. Russer C. Saavedra J. Schoebl D. Schreurs L. Schulwitz I. Shapir

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Temperature-Dependent RF Small-Signal and Noise Characteristics of SOI Dynamic Threshold Voltage MOSFETs Sheng-Chun Wang, Pin Su, Member, IEEE, Kun-Ming Chen, Kuo-Hsiang Liao, Bo-Yuan Chen, Sheng-Yi Huang, Cheng-Chou Hung, and Guo-Wei Huang, Member, IEEE

Abstract—In this paper, temperature-dependent RF small-signal and noise characteristics of silicon-on-insulator (SOI) dynamic threshold voltage (DT) MOSFETs are experimentally examined. In the low-voltage regime, both the cutoff and maximum oscillation frequencies ( and max ) tend to increase with temperature. In addition, the inherent body-related parasitics and the series resistance have much more impact on max than . Besides, we found that the noise stemmed from the body resistance ( ) would contribute to the output noise current, and degrade the minimum noise figure (NFmin ). Our study may provide insights for RF circuit design using advanced SOI DT MOSFETs. Index Terms—Body resistance, dynamic threshold voltage (DT) MOSFETs, noise, RF, silicon-on-insulator (SOI), small signal, temperature dependence.

I. INTRODUCTION UE TO its larger current driving ability with low leakage current, the dynamic threshold voltage (DT) MOSFET is attractive for low-power applications [1]. Hence, the dc characteristics and modeling of the DT MOSFET have been widely studied since its introduction [2]–[4]. Moreover, the temperature effect on its dc characteristic has also been well investigated [4]. Several optimized silicon-on-insulator (SOI)- or bulk-based DT MOS fabrication processes with improved performance have been demonstrated [5], [6], and its ability of RF applicaand maximum oscillation tions with high cutoff frequency has been reported as well [7]–[9]. However, frequency the temperature effect on the RF characteristics of DT MOSFETs is rarely known.

To avoid a large leakage current flowing through the source–body junction, a DT MOSFET is usually biased in the region. Therefore, it is crucial to low gate overdrive examine the RF small-signal and noise characteristics under this regime. This paper is an experimental investigation on the RF small-signal and noise characteristics of SOI DT MOSFETs and is organized as follows. The measurement environment and device structures/geometries are described in Section II. In Section III, the temperarue effect of body-related parasitics will then be investigated. and series resistances on and In Section IV, the RF noise behavior and its temperature dependence will be discussed for the first time. The temperature dependences of the equivalent thermal resistance and minimum noise figure will be examined as well. Finally, conclusions will be drawn in Section V.

D

Manuscript received March 02, 2010; revised April 06, 2010; accepted June 08, 2010. Date of publication August 03, 2010; date of current version September 10, 2010. This work was supported in part by the National Science Council of Taiwan. S.-C. Wang and G.-W. Huang are with the National Nano Device Laboratories (NDL), Hsinchu 300, Taiwan, and also with the Department of Electronics Engineering, National Chiao Tung University, Hsinchu 300, Taiwan (e-mail: [email protected]; [email protected]). P. Su is with the Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu 300, Taiwan (e-mail: [email protected]). K.-M. Chen, K.-H. Liao, and B.-Y. Chen are with the National Nano Device Laboratories (NDL), Hsinchu 300, Taiwan (e-mail: [email protected]; [email protected]; [email protected]). S.-Y. Huang and C.-C. Hung are with the United Microelectronics Corporation (UMC), Hsinchu 300, Taiwan (e-mail: [email protected]; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2010.2057175

II. DEVICES AND EXPERIMENTS The RF SOI DT MOSFETs used in this work were fabricated using UMC 65-nm SOI technology. These RF devices were laid out in the multifinger (eight fingers) and multigroup (16 groups) structure with 1- m channel width per finger. and On-wafer two-port common-source high-frequency noise parameters were measured using an ATN NP5B noise measurement system with Cascade microwave probes. Besides, to eliminate the inevitable parasitic accompanied with the probing pads, the -parameters of the devices’ corresponding dummy were measured and then used to perform the and noise parameters’ de-embedding procedure. Fig. 1 shows the temperature dependences of threshold extracted by the constant current voltage nA W/L method. Due to the negative temperature exhibits coefficient of the device’s Fermi potential [4], the negative temperature dependence for each channel length device. The equivalent circuit for both RF small-signal and noise behaviors is depicted in Fig. 2. The inherent body-related parasitics include the source- and drain-side junction capacitances and , respectively), the junction resistance , ( , and the body-transconductance . the body resistace , , and were determined using The series resistances the proposed zero method [10], and the other parameters along can be extracted by the exwith the channel noise current traction method presented in [11]. Note that to keep the device

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Fig. 1. Temperature dependence of the threshold voltage for SOI DT MOSFETs.

Fig. 2. RF small-signal and noise equivalent circuit for the SOI DT MOSFET.

operating in the saturation region, we let in our experiments. III. RF SMALL-SIGNAL CHARACTERIZATION and maximum oscillation freThe cutoff frequency quency are two common figures of merit used to characterize the RF performance of a device. Based on the equivalent circuit shown in Fig. 2 and neglecting the series , , and , the “intrinsic” and for resistances the DT MOSFET biased in the low regime can be approximately expressed as the following [12]: (1)

(2) In (1) and (2),

, (3)

and (4)

H

U

Fig. 3. (a) Short-circuit current gain j j and (b) unilateral power gain with and without considering the series resistance effect (symbols: measured data; solid and dash lines: modeled results with and without considering the series resistance effect, respectively).

is the input resistance, which can be extracted by opwhere timizing . The approximation in (1) and (2) holds in the low regime, where , , , around . and Equation (1) implies that the inherent body-related parasitics of the DT MOSFET would have little influence on . In the low regime, since tends to increase with temperature [4], [13], would have a positive temperature coefficient. On the other hand, due to the less temperature-dependent behavior of and the degradation factor , tends to have the same temperature dependence as [12]. That is, in the low regime, both intrinsic and would increase with temperature. To investigate the overall performance, however, the impact and should be examof the series resistance effect on ined. Fig. 3 shows that the series resistance has much more significant effect on the unilateral power gain (involved in the ) than the short-circuit current gain determination of (involved in the determination of ) at V. Compared to the series resistances, the much larger input and output regime would dominate , and impedance in the low can be also hence, . The little series resistance effect on deduced from Fig. 4(a) and (b), where has nearly the same temperature coefficient as for each channel length device.

WANG et al.: TEMPERATURE-DEPENDENT RF SMALL-SIGNAL AND NOISE CHARACTERISTICS OF SOI DT VOLTAGE MOSFETs

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Fig. 5. Temperature dependences for: (a)  and (b) f . (Data normalized with respect to their corresponding values at T C.)

= 25

Fig. 4. Temperature dependences for: (a) f and (b) g . (Data normalized with respect to their corresponding values at T C.)

= 25

This coincides with the implication in (1), which has assumed the series resistance is insignificant. The input and output impedance matching for the maximum , however, can be greatly available power gain, and hence, influenced by the series resistances. Moreover, since the degrais found to be nearly temperature independation factor dent for each channel length device, as shown in Fig. 5(a), the , shown in Fig. 5(b), degraded temperature dependence of would be mostly caused by the series resistance effect. That is, the larger resistances at higher temperatures would severely de. grade IV. RF NOISE CHARACTERIZATION

Fig. 6. Channel noise versus VDD.

A. Channel Noise and Equivalent Thermal Resistance The extracted power spectral density for the channel noise current (denoted as ) is shown in Fig. 6, and is usually expressed as follows [14]: (5) J/K is the Boltzmann constant, where is the ambient temperature in kelvin, is the channel conductance at zero drain–source voltage, and is the noise factor.

Besides, [15] has shown that has a weak temperature dependence, and the temperature dependence of is dominated by and . that of Fig. 7(a) and (b), respectively, shows the temperature depenand . In the low regime, since tends dences of to increase with temperature [12], would increase accordingly as predicted by (5). Note that (5) was originally derived for the device operating in the strong inversion region. However,

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Fig. 8. Temperature dependences for: (a) R and (b) g . (Data normalized C.) with respect to their corresponding values at T

= 25

Fig. 7. Temperature dependences for: (a) S and (b) g . (Data normalized C.) with respect to their corresponding values at T

= 25

in our experiments, the consistent prediction results for the temshows that it seems to remain valid perature dependence of even for the medium or weak inversion applications. The channel noise has a significant effect on the equivalent for conventioanl MOSFETs. In fact, by thermal resistance for DT MOSFETs neglecting the body trans-conductance, would be approximately the same as that for conventional MOSFETs as expressed in the following: (6) where K is the reference temperature. Note that (6) regime, the body-related paraindicates that in the low . sitics would have little influence on Fig. 8(a) shows versus temperature curves for each for nm device is about channel length device. Since nm and nm 0.1 V higher than those for devices in the whole temperature range (see Fig. 1), we first V for nm and nm consider V for the nm device to devices, and keep approximately the same gate overdrive voltage. In this in case, one can compare the temperature dependence for

Fig. 7(a) and that for in Fig. 8(b). Since tends to have , according to (6), the similar temperature coefficient as tends to increase with temperature mainly due to the increase and . of nm device operating at weaker bias condition, For an V; however, tends to more deeply increase i.e., with increasing temperature than . This could compete with . Therefore, or even overwhelm the contribution from “hot” tends to decrease with increasing temperature. This also , shows the existence of the zero temperature coefficient for which occurs between V and V for nm device. the B. Output Noise Current and Minimum Noise Figure may be strongly Unlike , the minimum noise figure influenced by . Although the analytical expression for is not easily derived, the noise contribution arising from to the output noise current flowing into the drain terminal can be analyzed and regarded as an important factor determining . (denoted as The noise power spectral density arising from ) is considered as thermal noise, and can be expressed as follows: (7)

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Fig. 10. Sensitivity analysis of the body resistance with respect to its noise contribution.

Fig. 9. (a) Extracted body resistance as a function of V DD . (b) Noise contrito the output noise current with respect to that bution from the body noise S from the channel noise.

The extracted values and their corresponding contricounterpart to the output noise current bution with respect to and are shown in Fig. 9(a) and (b), respectively. We found that in the low regime would have less noise larger contribution for each length device. This figure also shows that would have more contrithe shorter device with larger bution. It is worth noting that the smaller body cross-sectional area seen in the direction perpendicular to the channel current present in the shorter device. flow can account for the larger to its Through the sensitivity analysis of the variation of noise contribution, as shown in Fig. 10, we can see that its noise contribution could be reduced with increasing . In fact, the noise equivalent circuit for DT MOSFETs would be equivaapproaches lent to that for conventional MOSFETs when infinity and can be removed in the equivalent circuit. Therefore, would play an insignificant role in determining the larger . versus is shown in The minimum noise figure Fig. 11. is sharply increased towards the weak inversion region, and this trend is consistent with that for the conventional bulk MOSFET [16]. Moreover, our experimental results show has less temperature dependence in the low that regime. As shown in Fig. 10, in the low regime, since the to the output noise current for each noise contribution of would have little effect on the temperature is not significant, . temperature dependence of

Fig. 11. NF as a function of V DD at different temperatures for various channel length devices. (Data normalized with respect to their corresponding values at T = 25 C.)

V. CONCLUSIONS We have investigated the temperature dependences of RF small-signal and noise behaviors for the DT MOSFET. In the regime, since tends to increase with temperature, low would have a positive temperature coefficient. On the other hand, due to the less temperature-dependent behavior of and , is found to increase with temperature as well. Moreover, the body-related parasitics and the series than . resistances are found to have more impact on regime, the channel noise has a posiIn the low tive temperature coefficient due to larger at higher tempera, the much higher toward ture. In addition, compared to to have a negative the weaker inversion region can cause temperature coefficient. Finally, it shows that, in the low regime, the large would have little impact on the temperature . dependence of ACKNOWLEDGMENT The authors would like to thank the United Microelectronics Corporation (UMC), Hsinchu, Taiwan, for providing the devices used in this study.

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REFERENCES [1] F. Assaderaghi, D. Sinitsky, S. A. Parke, J. Bokor, P. K. Ko, and C. Hu, “Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI,” IEEE Trans. Electron Devices, vol. 44, no. 3, pp. 414–422, Mar. 1997. [2] S. S. Rofail and K. S. Yeo, “Experimentally-based analytical model of deep submicron LDD MOSFETs in a Bi-MOS hybrid-mode environment,” IEEE Trans. Electron Devices, vol. 44, no. 9, pp. 1473–1482, Sep. 1997. [3] J. B. Kuo, K. H. Yuan, and S. C. Lin, “Compact threshold-voltage model for short-channel partially-depleted (PD) SOI dynamicthreshold MOS (DTMOS) devices,” IEEE Trans. Electron Devices, vol. 49, no. 1, pp. 190–196, Jan. 2002. [4] J.-K. Lee, N.-J. Choi, C.-G. Yu, J.-P. Colinge, and J.-T. Park, “Temperature dependence of DTMOS transistor characteristics,” Solid State Electron., vol. 48, pp. 183–187, 2004. [5] C. Wann, F. Assaderaghi, R. Dennard, C. Hu, G. Shahidi, and Y. Taur, “Channel profile optimization and device design for low-power highperformance dynamic threshold MOSFET,” in Int. Electron. Device Meeting Tech. Dig., Dec. 1996, pp. 113–116. [6] A. Shibata, T. Matsuoka, S. Kakimoto, H. Kotaki, M. Nakono, K. Adachi, K. Ohta, and N. Hashizume, “Ultra low power supply voltage (0.3 V) operation with extreme high speed using bulk dynamic threshold voltage MOSFET (B-DTMOS) with advanced fast-signal-transmission shallow well,” in Proc. VLSI Technol. Tech. Symp. Dig., 1998, pp. 76–77. [7] Y. Momiyama, T. Hirose, H. Kurata, K. Goto, Y. Watanabe, and T. Sugii, “A 140 GHz f and 60 GHz f DTMOS integrated with high-performance SOI logic technology,” in Int. Electron. Device Meeting Tech. Dig., 2000, pp. 451–454. [8] T. Hirose, Y. Momiyama, M. Kosuhi, H. Kano, Y. Watanabe, and T. SOI DTMOS with a new metallic overlaySugii, “A 185 GHz f gate for low-power RF applications,” in Int. Electron. Device Meeting Tech. Dig., 2001, pp. 33.5.1–33.5.3. [9] C.-Y. Chang, J.-G. Su, H.-M. Hsu, S.-C. Wong, T.-Y. Huang, and Y.-C. Sun, “Investigation of bulk dynamic threshold-voltage MOSFET with 65 GHz ‘nomal mode’ ft and 220 GHz ‘over-drive mode’ ft for RF applications,” in VLSI Technol. Tech. Symp. Dig., 2001, pp. 89–90. [10] S.-C. Wang, P. Su, K.-M. Chen, C.-T. Lin, V. Liang, and G.-W. Huang, “On the RF extrinsic resistance extraction for partially-depleted SOI MOSFETs,” IEEE Microw. Wireless Compon. Lett., vol. 17, no. 5, pp. 364–366, May 2007. [11] S.-C. Wang, P. Su, K.-M. Chen, S.-Y. Huang, C.-C. Hung, V. Liang, C.-Y. Tzeng, and G.-W. Huang, “RF small-signal and noise modeling for SOI dynamic threshold voltage MOSFETs,” in Int. Solid-State Devices Mater. Conf. , Sep. 2008, pp. 414–415. [12] S.-C. Wang, P. Su, K.-M. Chen, S.-Y. Huang, C.-C. Hung, and G.-W. Huang, “Temperature dependences of RF small-signal characteristics for the SOI dynamic threshold voltage MOSFET,” in Proc. 4th Eur. Micro. Integr. Circuits Conf., Sep. 2009, pp. 69–72. [13] A. A. Osman and M. A. Osman, “Investigation of high temperature effects on MOSFET transconductance (gm),” in Proc. 4th Int. High-Temperature Electron. Conf., Albuquerque, NM, Jun. 1998, pp. 301–304. [14] A. F. Tong, W. M. Lim, K. S. Yeo, C. B. Sia, and W. C. Zhou, “A scalable RFCMOS noise model,” IEEE Trans. Microw. Theory Tech., vol. 57, no. 5, pp. 1009–1019, May 2009. [15] S.-C. Wang, P. Su, K.-M. Chen, C.-T. Lin, V. Liang, and G.-W. Huang, “Temperature dependence of high frequency noise behaviors for RF MOSFETs,” IEEE Microw. Wireless Compon. Lett., vol. 18, no. 8, pp. 530–532, Aug. 2008. [16] K.-H. To, Y.-B. Park, T. Rainer, W. Brown, and M. W. Huang, “High frequency noise characteristics of RF MOSFET’s in subthreshold region,” in IEEE RF Integr. Circuits Symp. Dig., Jun. 2003, pp. 163–167.

Pin Su (S’98–M’02) received the B.S. and M.S. degrees in electronics engineering from National Chiao Tung University, Hsinchu, Taiwan, in 1992 and 1994, respectively, and the Ph.D. degree in electrical engineering and computer sciences from the University of California at Berkeley, in 2002. From 1997 to 2003, he conducted his doctoral and postdoctoral research in SOI devices at the University of California at Berkeley. He was also one of the major contributors to the unified BSIMSOI model, the first industrial standard SOI MOSFET model for circuit design. Since August 2003, he has been with the Department of Electronics Engineering, National Chiao Tung University, where he is currently an Associate Professor. He has authored or coauthored about 100 research papers in refereed journals and international conference proceedings. His research interests include silicon-based nanoelectronics, modeling and design for advanced CMOS devices, and device/circuit interactions in nano-CMOS.

Kun-Ming Chen received the M.S. degree and Ph.D. degree in electronics engineering from National Chiao Tung University, Hsinchu, Taiwan, in 1996 and 2000, respectively. In 2000, he joined the National Nano Device Laboratories, Hsinchu, Taiwan, as an Associate Researcher, and in 2007, became a Researcher. He was engaged in research on microwave device processes and characterization.

max

Sheng-Chun Wang received the B.S. and M.S. degrees in electrical engineering from National Cheng Kung University, Tainan, Taiwan, in 1999 and 2001, respectively, and is currently working toward the Ph.D. degree at Chiao Tung University, Hsinchu, Taiwan. In 2001, he joined the National Nano Device Laboratories, Hsinchu, Taiwan, as an Assistant Researche. His current research interests focus on the small-signal and noise characterization and modeling for RF CMOS devices.

Kuo-Hsiang Liao received the M.S. degree in electronic engineering from National Changhua University of Education, Taiwan, Taiwan, in 2005. In 2005, he joined the National Nano Device Laboratories, Hsinchu, Taiwan, as an Assistant Researcher. He was engaged in research on RF device characterization and modeling.

Bo-Yuan Chen was born in Miaoli, Taiwan, in 1980. He received the M.S. degree in materials science and engineering from National Dong Hwa University, Hualien, Taiwan, in 2006. In 2006, he joined the National Nano Device Laboratories, Hsinchu, Taiwan, as an Assistant Researcher. He was engaged in research on III–V compound semiconductors and RF device characterization.

Sheng-Yi Huang received the B.S. degree in electrical engineering from National Cheng Kung University, Tainan, Taiwan, in 2001, and the M.S. and Ph.D. degrees in electronics engineering from National Chiao Tung University Hsinchu, Taiwan, in 2003 and 2007, respectively. Since 2003, he has been with the Advanced Technology Development Division, United Microelectronics Corporation (UMC), Hsinchu, Taiwan, where he is involved with RF-related technologies. His current research focuses on advanced mixed-mode and RF CMOS design including device modeling, noise characterization, power behavior, and reliability studies.

WANG et al.: TEMPERATURE-DEPENDENT RF SMALL-SIGNAL AND NOISE CHARACTERISTICS OF SOI DT VOLTAGE MOSFETs

Cheng-Choug Hung received the B.S. and M.S.E.E. degree in electrical engineering from National Cheng Kung University, Tainan, Taiwan, in 1996 and 1999, respectively. He is currently an RF Device Development Manager with the Advanced Technology Department, United Microelectronics Corporation (UMC), Hsinchu, Taiwan. His current responsibility/research focuses on RF CMOS technology characterization/delivery, including active and passive devices.

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Guo-Wei Huang (S’94–M’97) was born in Taipei, Taiwan, in 1969. He received the B.S. degree and Ph.D. degree in electronics engineering from National Chiao Tung University, Hsinchu, Taiwan, in 1991 and 1997, respectively. In 1997, he joined National Nano Device Laboratories (NDL), Hsinchu, Taiwan, where he is currently a Researcher and Manager of the High-Frequency Technology Division. Since August 2008, he has been an Adjunct Associate Professor with the Department of Electronics Engineering, National Chiao Tung University. His current research interests focus on characterization and modeling techniques of high-frequency devices, and characterization and verification of RF integrated circuits (RFICs)/monolithic microwave integrated circuits (MMICs).

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A Direct-Conversion CMOS RF Receiver Reconfigurable From 2 to 6 GHz Jaewoo Park, Student Member, IEEE, Shin-Nyoung Kim, Student Member, IEEE, Yong-Seong Roh, Student Member, IEEE, and Changsik Yoo, Member, IEEE

Abstract—A CMOS direct-conversion receiver with only one signal path is reconfigurable from 2 to 6 GHz in the RF band and from 3.6 to 54 MHz in the channel bandwidth. By employing a voltage feedback in a common-gate low-noise amplifier (LNA), the input matching of the LNA can be reconfigured for each RF band by simply changing the resonant frequency of the load network. The frequency characteristics of the active-RC channel selection filter with an R-2R ladder is automatically tuned by a one-shot tuning circuit. Implemented in 0.18- m RF CMOS technology, the whole receive path shows 4.6–5.6-dB noise figure while consuming 65–75 mA from a 1.8-V supply depending on the mode of operation. Index Terms—CMOS, IEEE802.11b/g/n, low-noise amplifier (LNA), low-pass filter (LPF), mobile WiMax, multimode, RF receiver, WiBro, WiMax.

I. INTRODUCTION

D

URING THE last few years, various wireless communication standards and services have been emerging and launched on the market. This creates an increasing demand for a mobile communication device that can support multiple wireless communication standards for access to wireless network at any time and any place. For this, an RF transceiver supporting multiple wireless communication standards has been investigated with the focus on the cost effectiveness [1]–[6]. Generally, it is much more challenging to implement a multimode RF transceiver than a single-mode RF transceiver because of the increasing cost (die area and package pins) and power loss due to mode-selection switches and/or circuits [2]. In an RF receiver, it is relatively easy to design a baseband analog circuit comprising a programmable gain amplifier (PGA) and channel selection filter (CSF) to be reconfigurable into multiple wireless communication standards. On the other hand, because the performance of the RF front-end is heavily dependent on various parasitic effects, it is very challenging to have a reconfigurable RF front-end.

Manuscript received October 20, 2009; revised May 03, 2010; accepted June 02, 2010. Date of publication August 09, 2010; date of current version September 10, 2010. This work was supported by the Research Fund of Hanyang University (HY-2007-S) and by the Center for Advanced Transceiver Systems (CATS). J. Park, Y.-S. Roh, and C. Yoo are with the Integrated Circuits Laboratory, Department of Electronic Engineering, Hanyang University, Seoul 133-791, Korea (e-mail: [email protected]). S.-N. Kim was with the Integrated Circuits Laboratory, Department of Electronic Engineering, Hanyang University, Seoul 133-791, Korea. She is now with the Department of Communications and Computer Engineering, Kyoto University, Kyoto 606-8501, Japan. Digital Object Identifier 10.1109/TMTT.2010.2057173

Fig. 1. Multimode RF front-end. (a) Multiple narrowband RF front-ends. (b) Wideband RF front-end. (c) Reconfigurable narrowband RF front-end.

Fig. 1 illustrates three possible ways of implementing an RF front-end supporting multiple wireless communication standards. Multiple narrowband RF front-ends in Fig. 1(a) for multiple wireless communication standards is the simplest method and each narrowband RF front-end can be optimized for each standard [3]–[5]. In [4], two separate low-noise amplifiers (LNAs) are used for the 2.4- and 5-GHz bands, respectively, for optimum performance at each band. The implementation cost, however, will be high and proportional to the number of modes to be supported. Fig. 1(b) shows a wideband RF front-end, which can support all the frequency bands with a single signal chain. Since

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Fig. 2. Block diagram of reconfigurable RF transceiver.

all the wireless communication standards are supported with only one RF front-end, the performance cannot be optimized for a specific mode and band. This means the performance could be worse than that of multiple narrowband RF front-ends in Fig. 1(a). Another drawback of this approach is the stringent requirement on linearity. Since the wideband LNA amplifies not only the signal in the band of interest, but also the signals in the other bands, which are out-of-band interferers, the linearity requirement on the following stage can be very tough. If we can have a reconfigurable narrowband RF front-end, as shown in Fig. 1(c), the cost would be minimized and the performance can also be optimized for each operation mode [7], [8]. The key to this approach is how to design a reconfigurable narrowband LNA [9]. In this paper, a direct-conversion CMOS RF receiver reconfigurable from 2 to 6 GHz in the frequency band and from 3.6 to 54 MHz in the channel bandwidth is described. Section II explains the reconfigurable RF receiver architecture and system requirement. In Section III, the reconfigurable RF front-end is described with emphasis on the LNA. Section IV deals with the analog baseband circuits. Experimental results of the reconfigurable receiver implemented in a 0.18- m CMOS RF technology are given in Section V and a conclusion follows in Section VI. II. RECONFIGURABLE RF RECEIVER ARCHITECTURE The goal of this work is an RF receiver enabling the seamless connection of wireless data networks supporting the following standards: • WiBro : 2.3-GHz mobile Internet service in Korea; • IEEE 802.11-b/g/n : 2.4 and 5–6 GHz; • mobile WiMax : 2.5 GHz and 3.5 GHz; • WiMax : 5.8 GHz. Thus, the RF band extends from 2 to 6 GHz and the channel bandwidths of these standards are 5, 7.2, 8.75, 10, 17.5, 20, and 36.6 MHz. In order to simplify the frequency planning, a direct-conversion architecture has been chosen, which is also advantageous in terms of the level of integration [10]. The block diagram of the reconfigurable CMOS RF directconversion receiver is shown in Fig. 2. The RF front-end module (FEM) consisting of band selection switches, RF filters, and an Rx/Tx selection switch connects the RF integrated circuit (IC)

Fig. 3. (a) Common source degenerated LNA with tunable matching network. (b) Common gate LNA with capacitive feedback.

to the multiband antenna. The signal in the RF band of interest is pre-selected by the RF FEM and the reconfigurable narrowband LNA follows. To minimize the flicker noise, an ac-coupled passive mixer is used for down-conversion, while a pre-amplifier compensates for the signal loss of the passive mixer. The down-converted baseband signal is amplified by a three-stage PGA whose gain is controllable from 0 to 60 dB in 1-dB steps. For baseband channel selection, a fifth-order Chebyshev active-RC filter is used, which provides better than 30-dB adjacent channel rejection at all operation modes. In order to improve the noise performance, one PGA stage is located in front of the CSF. III. RECONFIGURABLE RF FRONT-END CIRCUITS A. LNA It is well known that the source degenerated LNA shown in Fig. 3(a) provides the best performance among various narrowband LNA architectures. However, because of the narrowband frequency characteristic of its input matching network, it is not easy to have a reconfigurable input matching network. Either internal MOS or external MEMS switches can be used to change the resonant frequency of the input matching network [8]. However, any switch in the input matching network degrades the noise figure (NF) due to its loss and external microelectromechanical systems (MEMS) switch can increase the cost and form factor of the system [11]. Another solution for the reconfigurable narrowband LNA is the common-gate LNA with capacitive feedback, as shown in Fig. 3(b). Unlike the conventional common-gate stage, the LNA shows narrowband input matching characteristics due to the caand [12]. The input pacitive voltage feedback formed by is given as impedance

(1)

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where and are the transconductance of the input transistor and the load impedance at the frequency , respectively. Equation (1) shows that the input matching network can be easily reconfigured by controlling the resonant frequency of . the load impedance The noise factor can be derived as

(2) where is a noise parameter and is the equivalent load . The noise factor in (2) has the same form resistance of of equation as for a conventional common-gate LNA, but for is fixed to be conventional common gate topology, for input matching, and thus, the NF cannot be better than 3 dB [13]. For the common-gate LNA with capacitive feedback to be higher than in Fig. 3(b), the voltage feedback allows , and thus, the NF can be greatly improved. If the parasitic and secondary effects are considered, the input of the LNA in Fig. 3(b) is given as impedance

Fig. 4. Proposed feedback LNA with switchable cascode transistor.

(3) and are the gate–drain parasitic capacitance where and the output resistance of , respectively. The gate–drain changes the feedback factor and the output capacitance provides unwanted feedback. For low NF, the resistance of the transistor is desired to be transconductance as large as possible, which means large size of , and in . Larger means lower effective load turn, large impedance, which can limit the achievable gain of the LNA. Therefore, there must be a tradeoff between the NF and gain. The LNA in Fig. 3(b) can be reconfigured by controlling the resonant frequency of the load network. If the load network is implemented with fixed inductance and switchable capacitor bank, the load impedance would be too small for the lower RF band, which means smaller gain. To avoid this problem, the inductance should also be controllable by employing a switchable inductor bank, but any switch in series with an inductor degrades the quality factor of the load network and the achievable load impedance is limited. In this work, multiple load networks with different resonant frequencies are used as shown in Fig. 4. The signal current from is switched to a suitable load netthe input transistor work by cascode transistors . The switching of the cascode transistor is done by toggling its gate voltage between 0 V and the bias voltage. Since the gates of the cascode transistors are ac grounded, the feedback factor is not affected by parasitic capacitance and the input impedance is given as (4) This equation shows that the third term of (3) due to the unwanted feedback by is reduced by the cascode transistor.

Fig. 5. Implemented LNA schematic.

The cascode transistor eliminates the need for the tradeoff between the gain and NF. For low NF, the size of the input trancan now be freely chosen. Since the size of the cassistor code transistor can be smaller than the input transistor, the effect of the parasitic capacitance of the cascode transistor on the gain is not severe. Therefore, the performance optimization toward lower NF and larger gain becomes much easier. Fig. 5 shows the detailed schematic of the LNA, which has three load networks for 2-, 3-, and 5-GHz bands, respectively, to have an optimum impedance level at the output. Since the cascode transistors act as a switch, the input transistor could be shared for all the frequency bands. However, in the current design, we use two input transistors: one for the 2–3-GHz band and one for the 5-GHz bands in order to reduce the parasitic capacitance on the drain node of the input transistor.

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The LNA has dual gain modes to relieve the linearity requirements on the following stages. If the bias condition and/or load network are changed to control the gain, the input matching condition is changed because the load impedance and bias level determine the input impedance. Thus, the low-gain mode output is and , which is obtained by the capacitive voltage divider always connected to the load network, and thus, does not change the load impedance at the low gain mode. Since the capacitance is very small, the effect of the capacitive divider and of on the load impedance is negligible. The LNA has four outputs: LNAo2G, LNAo3G, LNAo5G, and LNAoLG, which are 2-, 3-, and 5-GHz high-gain mode outputs and low-gain mode output, respectively. The LNA has 23-dB/1 dB voltage gain and 2.5-dB NF at high-gain mode while consuming 10 mA from a 1.8-V supply. B. Down-Conversion Mixer The three high-gain mode outputs and one low-gain mode output of the LNA are applied to the down-conversion mixer with a pre-amplifier shown in Fig. 6. To minimize the flicker noise, an ac-coupled passive mixer is used [14]. The pre-amplifier and switching pairs of the mixer are separated for the low band (2 and 3 GHz) and high band (5 GHz) to have sufficient voltage gain for all the frequency bands. The pre-amplifier connects one of the four outputs of the LNA to one of the two switching pairs by controlling the gate voltage of the cascode transistor similar to that of the LNA. By using this signal path selection scheme, we can reduce the loss of signal power helping to achieve the required performance in multimode and multiband operation. The passive mixer with a pre-amplifier has 11-dB voltage gain and 3.7 nV/ Hz input referred noise while consuming 6 mA from 1.8-V supply.

Fig. 6. Passive down conversion mixer with pre-amplifier.

IV. RECONFIGURABLE ANALOG BASEBAND CIRCUIT A. PGA The output of the reconfigurable RF front-end is filtered and amplified by the analog baseband consisting of a CSF and PGA, as shown in Fig. 7. The PGA is composed of three unit cells: PGA1, PGA2, and PGA3, each of which has 20-dB gain control range with 10-, 5-, and 1-dB gain control steps, respectively. The CSF is preceded by PGA1 whose voltage gain relieves the requirement on the noise performance of the CSF. B. DC-Offset Cancelling (DOC) Loop The dc offset is cancelled by a DOC loop whose cutoff frequency is set to 10 kHz with an external capacitor to minimize the effect on the signal quality. When switching from the transmit mode to the receive mode, however, the time for the DOC loop to settle down is impractical. To prevent this, the cutoff frequency of the DOC loop is temporarily increased to 100 kHz at the transition and then switched back to 10 kHz during the normal operation, as shown in Fig. 7. C. CSF The channel selection is performed by an activefifth-order Chebyshev filter. The highest design challenge for the CSF is the wide range of cutoff frequency while satisfying

Fig. 7. Block diagram of analog baseband with PGA gain tuning strategy.

the demanding noise performance. For an active filter, there are two tunable elements, i.e., the resistor and capacitor. Fig. 8(a) and (b) illustrates the case of tuning the cutoff frequency in one octave with either a variable resistor or capacitor, respectively. Both the resistor- and capacitor-based schemes give the same frequency characteristics, but the noise performance can differ. is given as The noise factor of the CSF (5)

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Fig. 8. Filter cutoff frequency tuning methods, its noise characteristics and frequency responses. (a) Resistor-based tuning. (b) Capacitor-based tuning.

where the voltage gain of the CSF is set to unity and and are the input and CSF noise integrated over the channel bandwidth, respectively. With the resistor-based tuning shown in Fig. 8(a), the thermal noise floor gets doubled when the cutoff frequency is halved, but the integrated noise ) remains constant. On the other hand, power of the CSF ( is halved. Therefore, the integrated input noise power the noise factor of the CSF increases, which is not desirable for the multimode receiver because the overall system NF becomes a function of the bandwidth. With the capacitor-based tuning shown in Fig. 8(b), the noise factor of the filter remains and constant regardless of the bandwidth because decrease by the same amount for lower bandwidth. This makes the system noise budgeting much simpler. Generally, to save the silicon area, the capacitance of the filter is set to the minimum value while satisfying the required noise performance, but for accurate frequency tuning, the required resolution of capacitance control may become too small. For example, if a capacitor of 0.5 pF and resistor of 16 k are used to have 20-MHz cutoff frequency and the required frequency tuning accuracy is 100 kHz, the capacitance should be controllable in a 3-fF step, which is not practical. Therefore, this work combines the resistor- and capacitor-based tuning, as shown in Fig. 9. The 8-bit capacitor array coarsely controls the cutoff frequency and the 6-bit R-2R ladder is used for fine control of the cutoff frequency [15]. In order to minimize the variation of the system NF with the resistor-based fine frequency tuning, the strategy shown in Fig. 10 is taken. For the target cutoff frequency of 18.3 MHz, the tunable cutoff frequency ranges from 50% to 50% of 18.3 MHz. This wide range is divided into three sub-bands, which are coarsely tuned by the capacitor array, and in each sub-band, the R-2R ladder finely tunes the cutoff frequency. This tuning strategy restricts the variation of the noise factor of the CSF to be less than 16% while providing 100-kHz tuning resolution. Fig. 11 shows the operational amplifier (op-amp) used for the CSF. To achieve high bandwidth with low power consumption, the frequency response of the op-amp is compensated by a feedforward transmission zero instead of a conventional Miller capacitor [14]. To save power, the bias current and size of the

Fig. 9. Active-RC integrator with 6-bit R-2R ladder for fine control and 8-bit capacitor array for coarse control.

Fig. 10. Cutoff frequency tuning strategy to minimize the variation of system NF with the resistor-based fine tuning.

transistors are programmed according to the required performance of the op-amp, which may differ depending on the wireless communication standard. As shown in Fig. 11, the transistors of the first stage are implemented as a transistor array, which may be activated or deactivated. The size and bias current level of the transistors are determined to provide the required gain and bandwidth while dissipating minimum power. With this scheme, the current consumption of the op-amp is reduced from 3.5 to 2.6 mA when the cutoff frequency of the CSF is lowest.

PARK et al.: DIRECT-CONVERSION CMOS RF RECEIVER RECONFIGURABLE FROM 2 TO 6 GHz

Fig. 11. Reconfigurable operational amplifier using feedforward transmission zero technique for frequency compensation.

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Fig. 13. Measured voltage gain of the reconfigurable RF front-end (LNA + mixer) for all settings.

Fig. 14. Measured voltage gain of the analog baseband versus the PGA gain code. Fig. 12. Chip microphotograph.

V. EXPERIMENTAL RESULTS The reconfigurable receiver is implemented in a 0.18- m CMOS RF process, with an active area is 2.1 mm . The micrograph is shown in Fig. 12. The measured gain of the reconfigurable RF front-end (LNA mixer) for all settings is shown in Fig. 13. The upper side of the figure represents the voltage gain when the LNA is set to the high gain mode and the bottom one is for the low gain mode. Fig. 14 shows the measured gain of the analog baseband for all PGA gain settings. The gain is controllable from 0.12 to 58.47 dB in 1-dB steps and the absolute gain error is smaller than 1.53 dB, while the maximum gain step error is smaller than 0.15 dB. The linearity of the receiver chain was evaluated by the two-tone test, as shown in Fig. 15. The LNA and PGA are set to the low-gain mode as the linearity is most critical when the desired signal is weak and strong out-of-band interferers are present. The voltage gains of the PGA and LNA are 0 and 1 dB, respectively, and the passive mixer with a pre-amplifier has 11-dB voltage gain. Therefore, the total gain of the receiver is 12 dB. Since the internal signals of the receiver are all differential voltage signals and cannot drive the 50- input impedance of spectrum analyzer, an external active differential probe is

used to convert the differential voltage signal to a single-ended power signal with 0-dB voltage gain. Fig. 15(a) shows the baseband output spectrum in the WiMAX mode for 32-dBm two-tone input. Fig. 15(b) shows the third-order input intercept point (IIP3) plot for all operation modes. The receiver shows the IIP3 better than 7 dBm in all modes. Fig. 16 shows the measured frequency response of the CSF. While occupying only 0.35 mm , the cutoff frequency can be tuned from 1.8 to 27 MHz with 100-kHz steps. The gain flatness of the CSF in the passband was originally designed to be better than 0.1 dB, but the high-frequency peaking of 1 dB is observed when the cutoff frequency is higher than 18.3 MHz. This is because the parasitic capacitance of the op-amp is larger than the expected value, which degrades the gain bandwidth of the op-amp. The measured performance of the reconfigurable receiver is summarized in Table I. The whole receive path shows 4.6–5.6-dB NF. The receiver consumes 65–75 mA from a 1.8-V supply. The difference of the current consumption for each mode is due to the difference in the bias current level of the operational amplifier used in the CSF. In Table II, the performance of the reconfigurable receiver is compared with previous works. The slightly higher NF of this receiver is caused by using a single RF input port, but because

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TABLE I PERFORMANCE SUMMARY

TABLE II COMPARISON OF RECEIVER PERFORMANCE

Fig. 15. Two-tone test results. (a) Output spectrum in WiMAX mode. (b) IIP3s in all modes.

external MEMS switch is used to reconfigure the input matching network, which can degrade the system NF. VI. CONCLUSION Fig. 16. Measured frequency responses of CSF.

the receiver of this work does not require any external switch, the overall noise performance of the whole receive chain would be similar. Since the receiver of this work has only one RF input port and a single signal chain from the RF input to the analog baseband output, it has the smallest silicon area where the silicon area of each receiver is calculated assuming a single receive chain. The receiver in [7] also has only one RF input port, but an

A direct-conversion receiver with only one signal path can be reconfigured from 2 to 6 GHz in the RF band and from 3.6 to 54 MHz in the channel bandwidth. The LNA has a common-gate architecture with voltage feedback and its input matching can be simply reconfigured by changing the resonant frequency of the load network. The CSF using a novel tuning strategy and R-2R ladder minimize the variation of system NF while providing a fine frequency tuning resolution. The measured NF of the receiver implemented in a 0.18- m CMOS process is 4.6–5.6 dB. The proposed receiver and its architecture can be easily applied to other frequency bands.

PARK et al.: DIRECT-CONVERSION CMOS RF RECEIVER RECONFIGURABLE FROM 2 TO 6 GHz

ACKNOWLEDGMENT The authors would like to thank J.-R. Lee and Dr. K.-H. Lim, both with Future Communication IC Inc., Sungnam, Korea, for their generous support of this work. The computer-aided design (CAD) tools were provided by IDEC, Daegeon, Korea. REFERENCES [1] J. Ryynänen, S. Lindfors, K. Stadius, and K. A. I. Halonen, “Integrated circuits for multi-band multi-mode receivers,” IEEE Circuits Syst. Mag., vol. 6, pp. 5–16, 2006. [2] M. Brandolini, P. Rossi, D. Manstretta, and F. Svelto, “Toward multistandard mobile terminals-full integrated requirements and architectures,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 3, pp. 1026–1038, Mar. 2005. [3] M. Zannoth, T. Rühlicke, and B.-U. Klepser, “A highly integrated dualband multimode wireless LAN transceiver,” IEEE J. Solid-State Circuits, vol. 39, no. 7, pp. 1191–1195, Jul. 2004. [4] M. Zargari et al., “A single-chip dual-band tri-mode transceiver for IEEE 802.11a/b/g wireless LAN,” IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2239–2249, Dec. 2004. [5] B. Bakkaloglu et al., “A 1.5-V multimode quad-band RF receiver for GSM/EDGE/CDMA2K in 90-nm digital CMOS process,” IEEE J. Solid-State Circuits, vol. 41, no. 5, pp. 1149–1159, May 2006. [6] T. K. Nquyen et al., “CMOS low-noise amplifier design optimization techniques,” IEEE Trans. Microw. Theory Tech., vol. 52, no. 5, pp. 1433–1442, May 2006. [7] J. Craninckx et al., “A fully reconfigurable software defined radio transceiver in 0.13 m CMOS,” in IEEE Int. Solid-State Circuits Conf., 2007, pp. 346–347. [8] T. Maeda et al., “A low-power dual-band triple-mode WLAN CMOS transceiver,” IEEE J. Solid-State Circuits, vol. 41, no. 11, pp. 2481–2490, Nov. 2006. [9] J. Park et al., “A direct-conversion CMOS RF receiver reconfigurable from 2 GHz to 6 GHz,” in VLSI Circuits Tech. Symp. Dig., Jun. 2008, pp. 38–39. [10] T. Manku et al., “A single chip direct conversion CMOS transceiver for quad-band GSM/GPRS/EDGE and WLAN with integrated VCOs and fractional-N synthesizer,” in IEEE RF IC Symp., 2004, pp. 423–426. [11] Q. Li and Y. P. Zhang, “CMOS T/R switch design: Towards ultra-wideband and higher frequency,” IEEE J. Solid-State Circuits, vol. 42, no. 3, pp. 563–570, Mar. 2007. [12] R. Rossi et al., “A variable gain RF front-end, based on a voltagevoltage feedback LNA for multistandard applications,” IEEE J. SolidState Circuits, vol. 40, no. 3, pp. 690–697, Mar. 2005. [13] A. Amer et al., “A low-power wideband CMOS LNA for WiMAX,” IEEE Trans. Circuits Syst., vol. 54, no. 1, pp. 835–841, Sep. 2001. [14] S. Zhou and M. F. Chang, “A CMOS passive mixer with low flicker noise for low-power direct-conversion receiver,” IEEE J. Solid-State Circuits, vol. 40, no. 5, pp. 1084–1093, May 2005. [15] H. A. Alzaher and M. Ismail, “Digitally tuned analogue integrated filters using R-2R ladder,” Electron. Lett., vol. 36, no. 15, pp. 1278–1280, Jul. 2000. [16] J. H. Hwang and C. Yoo, “A low-power wide-bandwidth fully differential operational amplifier with current re-using feedforward frequency compensation,” in IEEE AP ASIC’04, Aug. 2004, pp. 32–35. [17] L. Lin et al., “A fully integrated 2 2 MIMO dual-band dual-mode direct-conversion CMOS transceiver for WiMAX/WLAN applications,” in IEEE Int. Solid-State Circuits Conf., 2009, pp. 416–417. [18] A. Behzad et al., “A fully integrated MIMO multiband direct conversion CMOS transceiver for WLAN application (802.11n),” IEEE J. Solide-State Circuits, vol. 42, no. 12, pp. 2795–2808, Dec. 2007.

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Jaewoo Park (S’05) received the B.S. degree in electrical engineering from the University of Incheon, Incheon, Korea, in 2005, the M.S. degree in electrical and computer engineering from Hanyang University, Seoul, Korea, in 2007, and is currently working toward the Ph.D. degree at Hanyang University. Since 2009, he has been with Future Communication IC Inc., Sungnam, Korea, where he designs CMOS RF IC products for CDMA systems. His research interests include transceiver architectures and RF/analog circuit design for wireless applications.

Shin-Nyoung Kim (S’06) received the B.S. and M.S. degrees in electrical and computer engineering from Hanyang University, Seoul, Korea, in 2006 and 2009, respectively, and is currently working toward the Ph.D. degree in communications and computer engineering at the Graduate School of Informatics, Kyoto University, Kyoto, Japan. Her current research interests include silicon device modeling and mixed-signal CMOS circuit design.

Yong-Seong Roh (S’07) received the B.S. (with highest honor) and M.S. degrees in electrical and computer engineering from Hanyang University, Seoul, Korea, in 2007 and 2009, respectively, and is currently working toward the Ph.D. degree at Hanyang University. His research interests include RF communication and power management circuits.

Changsik Yoo (S’92–M’00) received the B.S. (with highest honor), M.S., and Ph.D. degrees from Seoul National University, Seoul, Korea, in 1992, 1994, and 1998, respectively, all in electronics engineering. From 1998 to 1999, he was with the Integrated Systems Laboratory (IIS), Swiss Federal Institute of Technology (ETH), Zürich, Switzerland, as a Member of Research Staff involved with CMOS RF circuits. From 1999 to 2002, he was with Samsung Electronics, Hwasung, Korea. Since 2002, he has been an Associate Professor with Hanyang University, Seoul, Korea. His main research interests include CMOS RF transceiver design, mixed-mode CMOS circuit design, and high-speed interface circuit design. Dr. Yoo is a member of the Technical Committee of the IEEE International Solid-State Circuits Conference (ISSCC), the Very Large Scale Integration (VLSI) Circuits Symposium (SOVC), and the European Solid-State Circuits Conference (ESSCIRC). He was the recipient or corecipient of several technical awards including the Samsung Best Paper Bronze Award of the 2006 International System-on-Chip (SoC) Design Conference, the Silver Award of the 2006 IDEC Chip Design Contest, the Best Paper Award of the 2006 Silicon RF IC Workshop, and the Golden Prize for research achievement in next-generation DRAM design from Samsung Electronics in 2002.

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A 20-Gs/s Track-and-Hold Amplifier in InP HBT Technology Shogo Yamanaka, Member, IEEE, Kimikazu Sano, Member, IEEE, and Koichi Murata, Member, IEEE

Abstract—This paper presents a 20-Gs/s track-and-hold amplifier (THA) fabricated InP HBT technology. This THA is capable of operating under relatively high input voltages. The THA uses a fully differential architecture with a switched emitter–follower. To mitigate the pedestal error due to the feedthrough attenuation network, we added degeneration resistors in the feedthrough attenuation block. Measured total harmonic distortion is below 40 dB at low input frequencies, and 18 dB at frequency of 9.9 GHz. Index Terms—Feedthrough, InP HBT, pedestal, track-and-hold amplifier (THA).

Fig. 1. Block diagram of time-interleaved ADC.

I. INTRODUCTION

IGITAL signal processing (DSP)-based coherent detection technology has received significant attention for 100-Gb/s/ch long-haul optical communication systems [1]–[3]. Analog-to-digital converters (ADCs) are critical components in digital coherent systems. The ADC performance requirements for constructing 100-Gb/s/ch optical systems may have resolution of up to 5–6 bits and conversion rates of up to 60 Gs/s [4]. Reports have been published on high-speed ADCs with InP heterojunction bipolar transistors (HBTs) [5], SiGe HBTs [6], [7], and CMOS [8]. Although some ADCs have achieved highspeed operations by using a single ADC [5]–[7], it seems to be difficult to achieve 60 Gs/s with 5–6 bits with a lone ADC. On the other hand, a time-interleaved approach looks more hopeful [8]. In time-interleaved architecture, track-and-hold amplifiers (THAs), used as front-ends in ADCs, are key building blocks because they reduce input capacitance and improve the highfrequency performance of ADCs (Fig. 1). High-speed ( 10 Gs/s) THAs have been reported based on InP, SiGe HBTs, and CMOS technology. Table I shows an overview of these THAs comparing their sampling frequency, total harmonic distortions (THDs) for a low input frequency, as well as the Nyquist frequency, and input and output amplitudes for which the respective THDs are specified. The first over 10-Gs/s operating THA was implemented in InP HBT [9]. Its THDs were 38 and 31 dB for input signals of 1 and 6 GHz

D

Manuscript received December 11, 2009; revised June 07, 2010; accepted June 10, 2010. Date of publication August 05, 2010; date of current version September 10, 2010. S. Yamanaka is with NTT Network Innovation Laboratories, NTT Corporation, Kanagawa 239-0847, Japan (e-mail: [email protected]). K. Sano and K. Murata are with NTT Photonics Laboratories, NTT Corporation, Kanagawa 239-0198, Japan (e-mail: [email protected]; murata@aecl. ntt.co.jp). Digital Object Identifier 10.1109/TMTT.2010.2057174

with 1000 mVpp. Faster THAs were designed with the SiGe HBT process [10], [11]; however, the input amplitude was 1000 mVpp, and the output was only 120 mV with 16-GS/s operation [10]. In the case of [11], the output was less than 100 mVpp for a 6-GHz 1000-mVpp input signal. 40- and 30-Gs/s operations were also achieved using SiGe and CMOS technologies [12], [13], but THDs were measured for relatively low-voltage input signals (from 8 to 16.5 dBm). Although a report was published on a THA operating at input and output voltages of 500 mVpp [14], its dynamic characteristics were measured only in the track mode. The input amplitude range is an important parameter for ADCs, as well as sampling rate and resolution. ADCs need sufficiently large voltage to quantize an input signal properly, while large voltage causes distortions in the front-end amplifiers. Thus, there are appropriate ranges for an input full scale for ADCs. A main condition to determine sufficiently large-input full-scale voltage is a comparator’s offset mismatches. Fig. 2 shows the simulation results for the effective number of bits (ENOB) as a function of mismatch voltages for a 6-bit ADC obtained through numerical analysis. We assumed the comparator’s offset voltages showed normal distribution. The circles represents the average values, and the bars indicate standard deviations of 100 times simulation results. To maintain ENOB over 5.8 bits, the offset mismatch should be , where ( is the less than 0.15 number of bits). To get over 5.6 bits, it should be smaller . For instance, a recent developed low-noise than 0.24 comparator can achieve offset voltage of 1.69 mV with the calibration technique [15]. Using this value, we can calculate the desirable input full scale voltages for ADCs, which are 700 mV for 5.8 bits and 450 mV for 5.6 bits, respectively. Next, we consider the voltages for the front-end amplifiers. Although front-end amplifiers for 100-Gb/s optical systems

0018-9480/$26.00 © 2010 IEEE

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TABLE I PERFORMANCE OVERVIEW OF PUBLISHED HIGH-SPEED THAs AND THIS WORK

Fig. 3. Block diagram of THA. Fig. 2. ENOB versus offset mismatch voltages.

are not yet commercially available, output voltages of amplifiers for 10-Gb/s1 and 40-Gb/s optical systems [16] are 400 and 300 mVpp. Considering the tradeoff between effective resolution and nonlinearity in front-end amplifiers, we set that the input amplitude for ADCs should be in the range from 400–500 mVpp. However, the high-speed THAs presented in Table I do not operate under these voltages, except for [9] and [14]. However, dynamic characteristics were evaluated only in track operation in [14]. This paper presents a 20-Gs/s THA that operates under an amplitude of 500 mVpp. Thus, this THA is suitable for use in an ADC front-end circuit. We discuss circuit design considerations and describe how the THA was fabricated using InP HBT technology. The measurements results show that THDs are less than 40 dB for low frequencies, and 18 dB at frequency of 9.9 GHz sampled at 20 Gs/s with 500-mVpp input voltages. II. CIRCUIT DESIGN A. Circuit Architecture We used a fully differential architecture with a switched emitter–follower (SEF) generally used for high-speed THAs fabricated in bipolar technologies [9]–[14], [17], [18] because it offered high-speed operation and required only n-p-n transistors. Fig. 3 shows the block diagram of a fully differential THA. It consists of an input buffer, a feedthrough attenuation block, an SEF, hold capacitors ( ), and an output buffer. The input 1[Online].

Available: http://www.inphi-corp.com/index.php

buffer is a highly linear amplifier to decouple the input signal source and hold capacitors. Feedthrough is a phenomenon in which an input signal appears on hold capacitors during the hold mode due to the base–emitter junction capacitance of switching transistors. The feedthrough attenuation block suppresses the feedthrough from the input signal. The SEF is an analog switch that connects the input buffer to hold capacitors in the track mode, and separates them in the hold mode. The output buffer is a linear amplifier that drives 50- loads. B. Input Buffer and Feedthrough Attenuation Fig. 4 shows the circuit detail of the input buffer and the feedthrough attenuation block. The input buffer is implemented as a highly linear emitter–degeneration amplifier proposed in modulation of the differential [19]. Its main problem is the pair (Q1 and Q2), which results in nonlinearity in their collect currents. To compensate for this nonlinearity, Q5 and Q6 are added to the emitter–follower. As they generate the replica collector currents of Q1 and Q2, and as these currents are used as bias currents for Q3 and Q4, counter modulation occurs in the base–emitter voltage of Q3 and Q4. This modulation cancels the original modulation, and thus, high linearity is achieved. Since high-speed THAs use small hold capacitors to prevent bandwidth reduction, the input signal feedthrough is critical for high-speed THAs. Thus, we used the feedthrough attenuation block [18]. The differential pair (Q11 and Q12) in the feedthrough attenuation generates currents equal to those produced by Q1 and Q2 with reverse phase. In the track mode, Q8 and Q9 are turned on, and collector currents of Q11 and

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Fig. 5. Pedestal compensation circuit proposed in [18].

Fig. 4. Input buffer and feedthrough attenuation.

Q12 flow through Q8 and Q9. Thus, the feedthrough attenuation block does not affect signal paths of the input buffer. In the hold mode, collector currents of Q11 and Q12 are provided to load resistors ( ) in the input buffer through Q7 and Q10. Since the current signals of Q11 and Q12 are in reverse phase compared with those of Q1 and Q2, the base nodes of Q3 and Q4 maintain a constant level, resulting in feedthrough reduction during the hold mode. The feedthrough attenuation technique suppresses the input signal feedthrough; however, it causes increased pedestal error due to excess level reductions at the base node of Q3 and Q4 during the track-to-hold transition. To mitigate the pedestal error, the compensation circuit (Fig. 5) was presented in [18]. It makes use of the hold voltage as the feedback signal to compensate pedestal error, but this feedback circuit causes large voltage swings at the base nodes of Q3 and Q4. Thus, it is difficult for the input buffer to follow the input signal quickly during the hold-to-track transition for high-speed operations. Instead of the pedestal compensation circuit, we inserted resistors in the Q7 and Q10 emitter nodes. By introducing emitter–degeneration resistors, the excess voltage reductions can be reduced at the Q3 and Q4 base nodes, resulting in the pedestal error mitigation. Fig. 6(a) and (b) presents, respectively, the simulated waveforms at input buffer (solid lines) and SEF (dash lines) outputs in the case of without emitter–degeneration resistors in Q7 and Q10 and with resistors operating at 5 Gs/s. Excess level reductions at the input buffer output nodes are well reduced thanks to degeneration resistors, which results in small pedestal error. Also, we did not place any emitter–degeneration resistors for Q8 and Q9 so as to completely turn them off in the track mode.

Fig. 6. Simulated waveforms at the output nodes of input buffer (solid lines) and SEF (dash lines) in the case of: (a) without degeneration resistors and (b) with resistors.

C. SEF Fig. 7 represents the schematic of SEF and hold capacitors ( ). During the track mode, the tail current flows through Q14 and QS1, which act as emitter–followers. As a result, the voltage at the node of the hold capacitor follows the input signal

in the track mode. In the hold mode, the tail current of the transistor QS1 is switched off. In addition, the base voltage of this transistor is lowered because the feedthrough attenuation circuit maintains the base node of Q3 at lower level during the hold

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Fig. 9. Measurement setup.

Fig. 7. SEF.

Fig. 8. Photograph of THA. Fig. 10. Measured THA outputs in: (a) track mode and (b) track-and-hold operation.

mode. Thus, the switching transistor QS1 is nonconducting, and the hold capacitor is isolated from the input buffer. ) [17] to We also added the feed-forward capacitors ( suppress the feedthrough due to the feedthrough attenuation block. Since it is still active in the hold mode, the Q3 and Q4 base–emitter voltages depend on the input signal, and thus, undesirable signals appear at the Q3 and Q4 emitter nodes. These unwanted signals pass through the QS1 and QS2 ’s transfer the same base–emitter junction capacitances. unwanted signals, but with the opposite sign so that the overall feedthrough is reduced. D. Output Driver The output buffer is a simple emitter-degenerated amplifier biased at relatively large currents to achieve high linearity. This buffer also reduces the second-order harmonic distortion. III. MEASUREMENT RESULTS This THA has been fabricated using InP HBT technology with a cutoff frequency ( ) of 175 GHz [20]. The lateral

Fig. 11. Measured signal spectrum for f

= 2 GHz, f = 20 GHz.

emitter dimension of the HBTs is 1 m 4 m. The chip area is 2 mm 2 mm, and the chip photograph is shown in Fig. 8. The power dissipation is 735 mW with a power supply of 5.2 V. Measurements were performed on the wafer using high-frequency probes. Fig. 9 shows the measurement setup. Two

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and THD increases to 18 dB at 9.9 GHz. As this THA is designed to operate under relatively high-voltage operations to maintain ENOB at over 5 bits, it can be used as the front end of an ADC in a digital coherent receiver.

Fig. 12. Measured THD as function of input frequency at 20 Gs/s.

REFERENCES [1] D. L. Gagnon, S. Tsukamoto, K. Katoh, and K. Kikuchi, “Coherent detection of optical quadrature phase-shift keying signal with carrier phase estimation,” J. Lightw. Technol., vol. 24, no. 1, pp. 12–21, Jan. 2006. [2] H. Sun, K. T. Wu, and K. Roberts, “Real-time measurements of a 40 G/s coherent system,” Opt. Exp., vol. 16, no. 2, pp. 873–879, Jan. 2008. [3] H. Masuda, E. Yamazaki, A. Sano, T. Yoshimatsu, T. Kobayashi, E. Yoshida, Y. Miyamoto, S. Matsuoka, Y. Takatori, M. Mizoguchi, K. Okada, K. Hagimoto, T. Yamada, and S. Kamei, “13.5-Tb/s (135 111-Gb/s/ch) no-guard-interval coherent OFDM Transmission over 6,248 km using SNR maximized second-order DRA in the extended L-band,” in OFC/NFOEC, Mar. 2009, Paper PDPB5. [4] J. Lee, “High-speed analog-to-digital converters in SiGe technologies,” in Proc. IEEE Compound Semicond. Integr. Circuit Symp., 2007, pp. 1–4. [5] H. Nosaka, M. Nakamura, M. Ida, K. Kurishima, T. Shibata, M. Tokumitsu, and M. Muraguchi, “A 24-Gs/s 3-bit Nyquist ADC using InP HBTs for electronic dispersion compensation,” in IEEE MTT-S Int. Microw. Symp. Dig., 2004, pp. 101–104. [6] J. Lee, P. Roux, U. V. Koc, T. Link, Y. Baeyens, and Y. K. Chen, “A 5-b 10-GSample/s A/D converter for 10-Gb/s optical receivers,” IEEE J. Solid-State Circuits, vol. 39, no. 10, pp. 1671–1679, Oct. 2004. [7] P. Schvan, D. Pollex, S. C. Wang, C. Falt, and N. Ben-Hamida, “A 22 GS/s 5b ADC in 0.13 m SiGe BiCMOS,” in IEEE Int. Solid-State Circuits Conf. Tech. Dig., 2006, pp. 572–573. [8] P. Schvan, J. Bach, C. Falt, P. Flemke, R. Gibbins, Y. Greshishchev, N. Ben-Hamida, D. Pollex, J. Sitch, S. C. Wang, and J. Wolczanski, “A 24 GS/s 6b ADC in 90 nm CMOS,” in IEEE Int. Solid-State Circuits Conf. Tech. Dig., 2008, pp. 544–545. [9] J. Lee, A. Leven, J. S. Weiner, Y. Baeyens, Y. Yang, W.-J. Sung, J. Frackoviak, R. F. Kopf, and Y.-K. Chen, “A 6-b 12-Gsample/s trackand-hold amplifier in InP DHBT technology,” IEEE J. Solid-State Circuits, vol. 38, no. 9, pp. 1533–1539, Sep. 2003. [10] X. Li, W.-M. L. Kuo, Y. Lu, R. Krithivasan, J. D. Cressler, and A. J. Joseph, “A 5-bit, 18 GS/sec SiGe HBT track-and-hold amplifier,” in IEEE Compound Semicond. Integr. Circuits Symp., 2005, pp. 105–108. [11] X. Li, W.-M. L. Kuo, and J. D. Cressler, “A 40 GS/s SiGe track-andhold amplifier,” in Proc. Bipolar/BiCMOS Circuits Technol. Meeting, 2008, pp. 1–4. [12] S. Shahramian, A. C. Carusone, and S. P. Voinigescu, “A 40-GSample/Sec track & hold amplifier in 0.18 m SiGe BiCMOS technology,” in Proc. IEEE Compound Semicond. Integrated Circuits Symp., 2005, pp. 101–104. [13] S. Shahramian, S. P. Voinigescu, and A. C. Carusone, “A 30-GS/sec track and hold amplifier in 0.13-m CMOS technology,” in Proc. IEEE Custom Integr. Circuits Conf., 2006, pp. 493–496. [14] Y. Bouvier, A. Konczykowska, A. Ouslimani, F. Jorge, M. Riet, and J. Godin, “A 20-Gsamples/s track-hold amplifier in InP DHBT technology,” in Proc. 2nd Eur. Microw. Integr. Circuits Conf., 2007, pp. 1–4. [15] M. Miyahara, Y. Asada, D. Paik, and A. Matsuzawa, “A low-noise self-calibrating dynamic comparator for high-speed ADCs,” in Proc. IEEE Asian Solid-State Circuits Conf. Tech. Dig., 2008, pp. 269–272. [16] H. Fukuyama, T. Itoh, T. Furuta, K. Kurishima, M. Tokumitsu, and K. Murata, “Two-channel InP HBT differential automatic-gain-controlled transimpedance amplifier IC for 43-Gbit/s DQPSK photoreceiver,” in Proc. IEEE Compound Semicond. Integr. Circuit Symp., 2008, pp. 145–148. [17] P. Vorenkamp and J. P. M. Verdaasdonk, “Fully bipolar, 120Msample/s 10-b track-and-hold circuit,” IEEE J. Solid-State Circuits, vol. 27, no. 7, pp. 988–992, Jul. 1992. [18] T. Baumheinrich, B. Prégardier, and U. Langmann, “A 1-Gsample/s 10-b full Nyquist silicon bipolar track & hold IC,” IEEE J. Solid-State Circuits, vol. 32, no. 12, pp. 1951–1960, Dec. 1997. [19] T. Miki, H. Kouno, T. Kumamoto, Y. Kinoshita, T. Igarashi, and K. Okada, “A 10-b 50 MS/s 500-mW A/D converter using a differentialvoltage subconverter,” IEEE J. Solid-State Circuits, vol. 29, no. 4, pp. 516–522, Apr. 1994. [20] M. Ida, K. Kurishima, H. Nakajima, N. Watanabe, and S. Yamahata, “Undoped-emitter InP/InGaAs HBTs for high-speed and low-power applications,” in IEEE Int. Electron Device Meeting, Dec. 2000, pp. 854–856.

2

TABLE II MAIN THA CHARACTERISTICS

synchronized frequency synthesizers generate analog input and clock signals. The analog input signal is split into a differential signal by the 180 hybrid coupler before it is applied to the THA. THA outputs are then captured with an oscilloscope to observe time-domain waveforms and a spectrum analyzer is used to measure spectral characteristics. Fig. 10(a) and (b) represents THA output waveforms for a 500-mVpp 2-GHz input sinusoidal signal sampled at 20 GHz in the case of track mode and track-and-hold operation, respectively. Although we designed the THA to have the unity gain, the fabricated test chip unfortunately had 1-dB gain and 450-mVpp output in the track mode. We guess this loss arises from a small difference of the base–emitter resistance value between the transistor model and real transistors. Fig. 11 shows the output spectrum in the track-and-hold operation. The second-order harmonic distortion is well suppressed thanks to the differential architecture, symmetrical layout, and output buffer. Fig. 12 shows the measured THD under track-and-hold operation as a function of input signal frequency. For low input frequencies, the THDs are below 40 dB, 36 dB at input frequency of 4.9 GHz, and 18 dB at 9.9 GHz. For high frequencies, THD increases and the third-order harmonic distortion is dominant on THD. The circuit simulation indicates that this is mainly due to the nonlinearity of the output buffer. The THA specifications are summarized in Table II IV. CONCLUSION A 20-Gs/s THA has been designed and fabricated using InP HBT technology. A fully differential architecture with SEF provides high sampling rates. High-linear buffers suppress harmonic distortions. We also added degeneration resistors to the feedthrough attenuation block so as to suppress pedestal errors. The THA shows THD of less than 40 dB at low frequencies,

YAMANAKA et al.: 20-Gs/s THA AMPLIFIER IN InP HBT TECHNOLOGY

Shogo Yamanaka (M’09) received the B.S. and M.S. degrees in electrical engineering from Osaka University, Osaka, Japan, in 2004 and 2006, respectively. In 2006, he joined NTT Photonics Laboratories, Atsugi, Japan, where he had been engaged in research and development of mixed-signal ICs for optical communication systems. He is currently with NTT Network Innovation Laboratories, NTT Corporation, Kanagawa, Japan. His current research interests include coherent optical communication systems employing DSP. Mr. Yamanaka is a member of the Information and Communication Engineers (IEICE) of Japan.

Kimikazu Sano (M’97) received the B.E., M.E., and Ph.D. degrees in electrical engineering from Waseda University, Tokyo, Japan, in 1994, 1996, and 2004, respectively. In 1996, he joined NTT Photonics Laboratories, NTT Corporation, Kanagawa, Japan, where he has been engaged in the design of high-speed digital/analog circuits using GaAs MESFETs, InP tunneling diodes, InP HEMTs, and InP HBTs. Dr. Sano was the recipient of the 2000 Young Engineer Award presented by the Institute of Electronics, Information and Communication Engineers (IEICE), Japan, and the Young Researcher Award presented at the 2003 International Conference on Solid-State Devices and Materials (SSDM).

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Koichi Murata (M’92) received the B.S. and M.S. degrees in mechanical engineering and Dr. Eng. degree in electrical and electronics engineering from Nagoya University, Nagoya, Japan, in 1987 and 1989, and 2003, respectively. In 1989, he joined NTT LSI Laboratories, Atsugi, Japan. He is currently a Senior Research Engineer, Supervisor with NTT Photonics Laboratories, Kanagawa, Japan. He has been engaged in research and development of ultra-high speed mixed-signal ICs for optical communication systems. His current research interest includes opto-electronic IC design and high-speed optical transmission systems. Dr. Murata is a member of the Information and Communication Engineers (IEICE) of Japan.

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Wideband Common-Gate CMOS LNA Employing Dual Negative Feedback With Simultaneous Noise, Gain, and Bandwidth Optimization Jusung Kim, Student Member, IEEE, Sebastian Hoyos, and Jose Silva-Martinez, Fellow, IEEE

Abstract—This paper presents a wideband common-gate (CG) LNA architecture that overcomes the fundamental tradeoff between power and noise match without compromising its stability. The proposed architecture can achieve the minimum noise figure (NF) over the previously reported feedback amplifiers in a CG configuration. The proposed architecture achieves broadband impedance matching, low noise, large gain, enhanced linearity, and wide bandwidth concurrently by employing an efficient and reliable dual negative-feedback. An amplifier prototype was realized in 0.18- m CMOS, operates from 1.05 to 3.05 GHz, and dissipates 12.6 mW from 1.8-V supply while occupying a 0.073-mm2 active area. The LNA provides 16.9-dB maximum voltage gain, 2.57-dB minimum NF, better than 10-dB input matching, and 0.7-dBm minimum IIP3 across the entire bandwidth. Index Terms—CMOS, common gate (CG), feedback amplifier, low-noise amplifier (LNA), multistandard, noise match, power match, wideband LNA.

I. INTRODUCTION

F

UTURE wireless communication devices must support multiple standards and features on a single chip. In particular, the low-noise amplifier (LNA) must have low noise and high linearity over a wide frequency range. The conventional solution is to employ several LC-tuned LNAs in parallel [1], [2]. This approach requires significant die area for several narrowband LNAs and RF switches for band selection, which hurts the sensitivity and complicates the receiver design. Reconfigurable LNAs [3]–[5] enable hardware sharing and reduce form factor, cost, and power with respect to parallel narrowband LNAs. However, simultaneous operation of several signal channels (e.g., cellular communications at 900 and 1800 MHz, global positioning system at 1.2 and 1.5 GHz, and WiFi at 2.4 and 5.2 GHz) is prohibited with the reconfigurable operation. The concurrent dual-band architecture was proposed in [6], which requires multiple LC resonance circuitry at the input and output increasing the die area, cost, and more importantly noise due to the finite of the inductors at the input. Furthermore, input Manuscript received February 18, 2010; revised April 29, 2010; accepted May 13, 2010. Date of publication August 09, 2010; date of current version September 10, 2010. This work was supported in part by the National Science Foundation (NSF) under Contract ECCS-0824031. The authors are with the Analog and Mixed Signal Center, Texas A&M University, College Station, TX 77843 USA (e-mail: [email protected]; [email protected]; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2010.2057790

match and band selection due to the LC resonators must occur at the same frequency to achieve the optimum performance. This is difficult to achieve without extremely accurate passive device models. The trend toward software-defined radio (SDR) requires flexible and efficient RF building blocks, which justifies the adoption of wideband LNAs in modern and future communication systems. Wideband LNAs significantly reduce cost, area, pins, and power, and can process several signal channels simultaneously. However, the design of wideband LNAs is challenging in several aspects. One challenge is to achieve a low noise figure (NF) ( 3 dB) while satisfying impedance dB over several gigahertz bandwidth. matching The inductor-degenerated LNA used in conventional wireless receivers can offer simultaneous noise and power match by to the desired shifting the optimum noise impedance value, but only in a narrowband around a single frequency [7]. Reducing the factor for the input-matching network can increase the bandwidth at the cost of a higher NF [8]. Another challenge is the high linearity requirement due to several channels received without any filtering. Chen et al. [9] reported a broadband linearization scheme, but, due to the higher order nonlinear terms of the MOSFET, their linearization scheme is dBm . not effective for a high input power signal The common-gate (CG) LNA’s NF is no better than at the input matched condition, and recent research as of yet cannot fully decouple the tradeoff between noise and power match [3], [4], [10]–[12]. In this paper, we demonstrate that a dual negative-feedback amplifier in a CG configuration can achieve low noise and high gain in a wideband fashion. The proposed CG-LNA with dual negative-feedback achieves simultaneous noise and power match without compromising other design parameters. Due to the nature of negative feedback, the LNA enhances the linearity regardless of variations in input power. We also show that the proposed LNA is able to achieve the orthogonality of design parameters between impedance matching, linearity, noise, gain, and bandwidth. The proposed techniques can also be used for bipolar junction transistors (BJTs) and MESFETs and are compatible with device scaling and technology evolution trends. This paper is organized as follows. Section II reviews the properties of CG-LNA and low-noise techniques employing feedback. Section III describes the proposed dual negative-feedback LNA and derives analytical expressions for . The amplifier input impedance, gain, bandwidth, NF, and design and layout issues are discussed in Section IV. Section V

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use. The NF including channel noise, induced gate noise, and resistive load under the input-matching condition is expressed as [10] (2) where , , and are bias-dependent parameters [13], is the is the source impedance, and and are load impedance, operating and unity current gain frequencies, respectively. The dominant noise source in the CG-LNA is due to the channel of the MOSFET device. The gate induced noise noise in a CG-LNA is usually negligible in contrast to an inductor-degenerated LNA under simultaneous noise and power match condition [14]. The fourth term shows that a large resistive load is desirable for low NF, but this condition is usually detrimental for wideband operation of LNAs. In summary, CG-LNAs achieve a broadband impedance match, superior reverse isolation, stability, and a high linearity. Recently reported CG feedback amplifiers aim at decoupling the noise and power (input) match tradeoff without degrading other relevant LNA parameters. Fig. 1. Conventional CG-LNA and low-noise techniques employing feedback.

provides measurement results, and concluding remarks are given in Section VI. II. PROPERTIES OF CG-LNA AND ITS LOW-NOISE TECHNIQUES As increases with the scaling of CMOS devices, it becomes more promising to employ feedback in the design of wideband LNAs. Before exploring the design details of the dual negative-feedback CG-LNA, it is helpful to review the properties of CG-LNAs and their low-noise techniques. A. Properties of CG-LNA Fig. 1(a) shows the conventional CG-LNA where the inductor resonates with the parasitic capacitance of the impedance-matching device and the input pad. Within the signal bandwidth, the reactive part of the input impedance is then canceled and the real part of the input impedance is de. Also, the input-matching network termined by of the CG-LNA is a parallel resonance as opposed to the series resonance of the inductor-degenerated LNA. Hence, a low (quality factor) of the input-matching network results in a wider bandwidth and the CG-LNA is more robust to process, voltage, and temperature (PVT) variations. The power gain of CG-LNAs is relatively low due to the impedance-matching constraint. Ignoring the transconductance , input impedance matching reof the back-gate transistor and the CG-LNA’s effective transconducquires tance under an input-matching condition is (1) CG-LNAs exhibit superior stability and reverse isolation due to the absence of the Miller effect by . Although CG-LNAs feature desirable properties for wideband operation, their high NF under the input-matching condition prevents its extensive

B. Low-Noise Techniques Employing Feedback in CG-LNA The capacitor cross-coupled CG-LNA [10] in Fig. 1(b) reduces its NF and power consumption by employing negative -boosting with inverting amplification, , feedback. reduces the noise contribution due to the channel noise by a under input-matching condition. At the same factor of time, the intrinsic transconductance of the impedance-matching device can be halved, which reduces the power consumption by the same factor. The drawbacks of the capacitor cross-coupled -boosting dictates that the CG-LNA are that the passive inverting amplification must be less than 1 taking into account . Furthermore, the unilateral the parasitic capacitance behavior of the CG-LNA is affected by the scheme where input–output feedthrough and stability are deteriorated. In [3], shunt–shunt positive feedback is used to add a degree of the impedance-matching of freedom in determining the device, as shown in Fig. 1(c). However, the amplifier’s stability must be carefully evaluated when the positive feedback is employed. Also, increasing the loop gain in positive feedback reduces the overdrive voltage of the transistor, and consequently, its linearity. Negative-feedback around a common-base amplifier has been employed to break the lower bound of noise performance in [4]. The simplified CMOS version schematic of the LNA is shown in Fig. 1(d). In this topology, the feedback network is passive, of the impedance-matching device. limiting the choice of the Low gain and a large parasitic capacitance at the output node makes this approach unsuitable for wideband LNAs. Woo et al. [12] demonstrated that positive feedback in combiboosting can achieve the best theoretical nation with passive noise performance with low power. Compared to [3], this work, shown in Fig. 1(e), requires half the power consumption for the same power gain and features further suppression of channel noise from the impedance-matching device. All the reported works are based on feedback amplifiers of scaled CMOS devices. taking advantage of the high

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TABLE I COMPARISON OF CHARACTERISTIC IN FEEDBACK-BASED CG-LNA

To minimize the power consumption, we employ a singleended configuration and use only NMOS transistors, as they have a higher than PMOS for a given current. Note that while our proposed architecture allows for a single-ended implementation, those in [10] and [12] do not, as they rely on capacitor cross-coupling to achieve sign inversion with passive devices. Hence, those previous approaches require a balun worsening the NF due to its insertion loss, thus offsetting the advantage of low-noise techniques. A. Input Match The in-band LNA input impedance can be found as Fig. 2. (a) Simplified LNA model and (b) schematic of the dual negative-feedback CG-LNA (biasing not shown).

However, none of these designs achieve the full decoupling of noise and power match in CG-LNAs. Also, other design parameters (e.g., stability, reverse isolation, and wide bandwidth) are sacrificed in order to improve noise performance. The main properties of feedback based CG-LNA topologies are summarized in Table I. III. DUAL NEGATIVE-FEEDBACK WIDEBAND CG-LNA Fig. 2 shows the proposed wideband CG-LNA with dual negative feedback (shunt-series) along with its simplified model. The impedance-matching device amplifies the signal and provides the main forward signal path. The common-source amin Fig. 2(a) boosts ( of ). The source plifier controls the LNA input impedance with the ratio follower , which governs the amount of boosting, as well as to the LNA input impedance. sets the contribution of the loop gain and supplies the difference in bias current between and .

(3) where parasitic capacitor arises from the input pad, , and . The input-matching network is a parallel resonance where the quality factor of the parallel LC resonator is (4) results in a wider bandwidth since the senA lower to parasitic components is proportional to the sitivity of quality factor of the matching network [15]. The parasitic cais absorbed into the LC network and the imaginary pacitor is negligible within the bandwidth. The real part of part of mainly depends on , which is transformed to the input through the embedded dual negative feedback. Therefore, is no longer constrained by the input match condition and can . be chosen B. Noise Analysis Noise cancellation using feed-forward techniques [9], [16], [17] can decouple the input matching from the NF by cancelling

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the impedance-matching device’s noise. However, mismatch and parasitic effects limit the performance of the technique, and the effective bandwidth of noise cancellation is limited. In feedback-based approaches [3], [4], [10]–[12], the noise cancellation of the impedance-matching device comes from the degree of freedom provided by the feedback network. , The dominant noise sources in the proposed LNA are , , and . Within the LNA’s bandwidth, the power spectral density components at the output can be obtained as (5) (6) (7) (8)

at R

= 370 ,

with different LNA current levels at R

= 370 ,

Fig. 3. NF countour plot with different g g =g , = , and  : .

(

) = 5 = (4 3)

=08

and g

(9) where

is (10)

Thus, the total NF is approximately (11) (12)

(13)

The second term in (13) represents the noise contribution of the and is minimized when and main transistor are large. The third term accounts for the noise contribution of and and is minimized if . The . Under last term represents the thermal noise contribution of the same bandwidth condition, the proposed LNA presents the when compared to other lowest noise contribution due to LNAs. With an unconstrained power specification, the proposed LNA can achieve the theoretical minimum NF. With a constrained power specification, the power budget determines the NF, which, in this topology, is decoupled from other design parameters. , , From (13), the LNA NF improves by increasing , and while determining the ratio from the input-matching condition. The maximum values for design parameters, however, are bounded by two constraints: available voltage headroom, and of the input-matching network. Fig. 3 and given that shows the NF contour by varying is unaltered and is maximized. The dashed line in

Fig. 4. NF and g , g =g

(

) = 5 = (4=3), and  = 0:8.

Fig. 3 corresponds to a constant current consumption of 6 mA for and under the same condition. The LNA power consumption factor, or equivalently , can be taken into consideration by substituting with . Hence, (13) can be rewritten as

(14) Fig. 4 shows the theoretical NF with respect to LNA current convalues. As expected, the plot shows sumption for different an inverse relationship with current. The thermal noise due to is minimized, regardless of current, by the dual feedback factor . Notice that at lower current levels, the NF for shows better performance since, in this region, feedsmall and dominate the noise performance. back transistors ’s noise As current increases, the noise contribution due to becomes more prominent, indicating that large is desirable

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, , and attenuate low-freAC coupling capacitors attenuate quency signals, and the parasitic capacitors high-frequency signals. In the mid-band frequency, ac coupling capacitors and parasitic capacitors can be ignored yielding

(16)

Fig. 5. (a) Proposed LNA with parasitic capacitors. (b) Equivalent-circuit model for voltage gain and bandwidth analysis. (c) Design parameters.

for low noise performance. Regardless of current levels, ’s noise imposes the lower bound on the NF. Based on the trend of noise performance with respect to current consumption levels, a power-efficient region of operation can be found by equating . Hence, (15) . Increasing current beyond this point where results in diminishing marginal returns. C. Gain and Bandwidth Analysis Like other topologies, conventional CG-LNAs must trade gain for bandwidth. In [3] and [12], active current gain is added by employing positive-feedback, thereby increasing the gain by a factor of 2 compared to conventional CG-LNA and the topology reported in [10] for input matched condition. Still, gain, bandwidth, impedance matching, and NF cannot be optimized simultaneously, as depicted in Table I. However, the dual negative feedback in the proposed architecture can simultaneously optimize all these parameters. The high transconductance provides a high voltage gain and allows us to use ratio , as shown by the impedance-matching larger output load gives a low NF and does not condition given in (3). Large affect the 3-dB bandwidth because the bandwidth is chiefly a and the parasitic capacitances at the LNA function of only output. To derive the voltage gain and bandwidth of the proposed ampflifier, we consider two dominant parastitic capacitances, as shown in Fig. 5(a) and its ac model in Fig. 5(b). The parasitic are canceled by LC resonance, capacitors at the input node is the total capacitance due and thus, are not considered. , , and the input capacitance of the next stage. is to the parastitic effects at the drain of and source of . In dominates because the practical implementation, includes the appreciable parasitic capacitance of the next stage. and create an undesired feedback path. Impedance matching and low NF condition dicand be much larger than , thus, . tate that in the following analysis. Hence, for simplicity, we neglect on the LNA frequency response is included The effects of in Appendix A.

Note that the mid-band gain of the amplifier is mainly determined by the dual feedback transconductance ratio rather than the load and source impedance ratio . Small-signal analysis of Fig. 5(b) shows that the high-frequency voltage gain is approximately given by

(17) , , , and are circuit-dependent parameters where defined in Fig. 5(c). Depending on the relative location of the two poles, the pole, zero, and values for each case change and are shown or is much greater than the in Table II. When either other, the dominant pole is shifted away from the origin by . When no dominant pole exists (i.e., two the factor of poles are close to each other), the transfer function becomes second order and has complex poles. The natural frequency is and the system is given in Table II. Regardless of the location of the poles, dual negative feedback increases the amplifier’s bandwidth. Fig. 6 displays the surface versus the plots of normalized 3-dB bandwidth and the feedback loop gain forward path gain for . As seen in the figure, the feedback loop gain does not change the bandwidth appreciably, provided that it is sufficiently high. This behavior occurs because the loop gain only affects the zero, while the forward path gain determines the pole shifting. In all cases, when (normal operation), demonstrating higher bandwidth than the conventional CG-LNA. The bandwidth enhancement due to the dual negative feedof the device and the LNA’s driving back is limited by the capability. When the proposed LNA is realized in a receiver, due to the parathe dominant pole is located at sitic capacitance of the next stage (e.g., mixer or off-chip surface-acoustic wave (SAW) filter). Hence, the expression for the dominant pole can be derived as

(18) where is the capacitance of the next stage and is the proportionality constant between the parasitic capacitance of the . Therefore, the bandwidth enhanceamplifier output and is effective only when the ment is dominant. If not, the domLNA’s driving capacitance inant pole is limited .

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TABLE II

POLE, ZERO, AND

!

Natural frequency (

Q PARAMETERS VERSUS RELATIVE LOCATION OF TWO POLES

)

Fig. 7. Equivalent model for nonlinearity computation in the proposed LNA. Fig. 6. Bandwidth dependence on feedback characteristics. (a) . (b) = . (c) =2 . (d) =4 . (1 2)

= !

!

!

!

!

!

!

!

=

D. LNA’s Linearity The LNA linearity is typically described using and 1-dB compression point, where the former is the metric for smallsignal power and the latter is for large-signal power. Multigate transistor (MGTR)-based linearization methods for MOSderivative’s poFETs rely on the fact that the second-order larity is different in weak and strong inversions. The MGTR scheme is not effective for large-input signals because of higher order nonlinearity. Although the published works in [9], [18], values, they typically work only for and [19] report large dBm. On the other hand, feedback suppresses all the harmonic terms [20], [21] and, therefore, is effective regardless of the input signal power. Consider a single NMOS transistor in the saturation region with drain current given by (19) where models mobility degradation. Its nonlinear transconductance is represented by a power series around the bias point (20) where

is the transconductance, and and are higher order nonlinear coefficients. For simplicity, we

neglect dependence of the drain current and assume linear intrinsic NMOS capacitances. An intuitive, but frequency-independent explanation of the enhanced linearity of a closed-loop feedback system is provided inherently linearizes in [20]. The source degeneration due to the amplifier. The dual feedback network in the proposed cir. The cuit further linearizes the system with a loop gain of , denoted as analytical expression for the overall amplifier , is given by (21) where is the open-loop amplifier without the dual negative feedback loops. To verify the preceding analysis, the circuits shown in Fig. 2(a) were simulated in Spectre RF and , showing 6.2-dB imwith ideal linear elements for provement at the designed bias point. However, the linearity of the closed-loop LNA has an upper bound that is set by the linearity of the feedback amplifier. The final LNA has a linearity enhancement of 2 dB compared to the open-loop CG-LNA. , we apply a To calculate the frequency dependency of Volterra analysis [22] (detailed in Appendix B) to the simplified versus circuit shown in Fig. 7. Fig. 8 plots the resultant of . has a large overthe gate overdrive voltages drive voltage, and hence, a much smaller distortion. The device parameters used in the simulation are from the final LNA demV and mV for sign bias point at and , respectively. The performance is better with and , and is large effective gate voltage for the transistors , as expected. Fig. 9 more sensitive with the main transistor

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Fig. 8. Theoretical IIP3 at 2.4 GHz versus V

= V 0V

of M and M .

Fig. 10. Schematic of the proposed LNA with the buffer (biasing not shown).

TABLE III DEVICE DIMENSION

Fig. 9. Theoretical (solid line) and simulated (dots) IIP3 at 2.4 GHz versus: V V and (b) V V V . (a) V

=

0

=

0

shows the theoretical and simulated when the effective gate or is varied and the other is fixed at the devoltage of signed LNA bias point. In the simulation for Fig. 9(a), the power of the transistor is fixed supply is adjusted such that drop due to resistive load. The theoretical and simafter an match very well within a 2-dB difference. ulated IV. CIRCUIT DESIGN AND LAYOUT ISSUES A. Circuit Design A dual negative feedback CG-LNA targeted for 1.2–5.2 GHz was designed with triple-well RF transistors and metal–insulator–metal (MIM) capacitors in TSMC 0.18- m CMOS. Fig. 10 shows the final wideband CG-LNA with the source–follower buffer. The target specifications are: 1) 17-dB voltage dB; 3) current budget of 10 mA; and gain; 2) dBm. In this design, we set , i.e., the 4) conventional impedance-match value for a CG-LNA. The specifications require mV and mV. , we maximize to minimize its noise contribution. Given From the voltage headroom constraint, we choose ensuring operates in saturation region with a sufficient margin. Based on the NF target specification, the total current consumption of 6 mA is determined where (13) shows 2.4 dB of NF. The induced gate noise and gate resistance increases the predicted NF and this safety margin is necessary to achieve the is determined from the targeted NF. Finally, the ratio and . The LNA is biinput-matching condition given ased with a current mirror, which is not shown in Fig. 10 for

simplicity. The final values of the device sizes are summarized in Table III. We added a source follower to drive the 50- external meaof the source follower is intentionsurement equipment. The with smaller device size to ally designed to be less than improve at high frequency. A separate 1.8-V power supply is used with independent current mirror biasing for the design of the buffer. B. Layout Issues Wide-use of RF-MIM coupling capacitors gives design flexibility, but causes signal loss because of parasitic substrate capacitance. Hence, we minimize ac coupling capacitance size to maximize the LNA’s bandwidth. Shielded pads [23] are employed for RF input and output to prevent signal loss and noise from the resistive substrate. Shielded RF pads exhibit more capacitance to RF ground (Metal 1 shorted to ground), but this is not a major issue since it is resonated out with an off-chip inductor. The schematic in Fig. 11 shows the pads and bondwire inductors. On-chip bypass capacitors null the effects of bondwire inand . Bondwire inductance requires careful ductances consideration since it alters the input impedance with a parasitic pole-zero pair. Assuming other parasitic effects are cancelled by the input-mathcing LC resonator yields the following expression for input impedance: (22) Multiple pads are then connected, but not in adjacent pads, to and mutual inductance. decrease effective

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Fig. 13. Measured and simulated S .

Fig. 11. Schematic of the proposed LNA with bondwire inductors.

Fig. 14. Measured and simulated voltage gain versus frequency. Fig. 12. Die photograph of the LNA.

V. MEASUREMENT RESULTS The circuit was designed and fabricated in TSMC 0.18- m CMOS technology and encapsulated in a quad flat no-lead (QFN) package. Fig. 12 shows the die photograph of the LNA. The active area is only 0.073 mm since no inductor is used on-chip. The chip was measured on FR-4 printed circuit board (PCB). . The meaFig. 13 shows the measured and simulated is close to simulation up to 2.5 GHz, but degrades sured rapidly above the point. The measured is below 10 dB between 1.05–3.1 GHz. We attribute the discrepancey to: 1) insufficient self-resonant frequency ( 10 GHz) of off-chip and 2) board parasitics in FR-4 substrate. Fig. 14 inductor shows the measured voltage gain versus simulated voltage gain after deembedding the buffer effect. We measure a maximum voltage gain of 16.9 dB and remaining 1-dB flatness from 1.1 to 2.5 GHz. The lower and upper 3-dB bandwidth is measured at 0.8 and 3.05 GHz. The gain rolloff also starts at 2.5 GHz where impedance matching degrades due to the board parasitics. Note that the 3-dB bandwidth (3.05 GHz) almost exactly corresponds bandwidth (3.1 GHz). with the 10 dB

Fig. 15. Measured and simulated NF versus frequency.

The NF is measured within the amplifier’s 3-dB bandwidth. As shown in Fig. 15, the NF varies between 2.57 to 3.15 dB measurement was perwithin the amplifier’s bandwidth. formed with the LNA and buffer, as shown in Fig. 16. Two tones are applied with equal amplitude and a frequency spacing of is 0.3 dBm at 2.2 GHz. Fig. 17 4 MHz. The measured

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dissipating 7 mA from a 1.8-V supply. A comparison of measurement results with the recently published wideband LNAs shows that the proposed dual negative-feedback CG LNA achieves superior noise and linearity performance with moderate power consumption using a mainstream technology.

EFFECT OF

APPENDIX A AMPLIFIER’S BANDWIDTH

ON

Including the effect of becomes

, the high-frequency voltage gain

(A.1) where Fig. 16. Two-tone IIP measurement results (f

= 2:2

and

are

GHz).

(A.2)

(A.3) , , and , (A.1) Assuming can be approximated as shown in (A.4) at bottom of the following page. An additional zero is created by the feed-forward path from the input to the output due to parasitic capacitance . Therefore, small in the design should be ensured not to hurt the reverse isolation and stability. The pole location under dominant pole assumption can be derived as (A.5) Fig. 17. Measured IIP versus frequency.

or displays the as the location of the two tones are varied within the bandwidth. has a minimum of 0.7 dBm for GHz. The measured performance of the dual negative-feedback LNA is summarized in Table IV. Recently published works in wideband LNAs are compared with the proposed architecture. The circuit benefits from low NF and high linearity with moderate power consumption. VI. CONCLUSIONS This paper has proposed a new wideband CG-LNA architecture, and provides a detailed analysis and design guidelines. Theoretical analysis of the amplifier architecture demonstrated that the fundamental tradeoff between noise match (NF) and can be overcome without degrading other power match design parameters. Measurement results of the dual negative-feedback CG-LNA realized in 0.18- m CMOS demonstrate 16.9-dB maximum voltage gain, 2.57-dB minimum NF, better than 10-dB input matching, and 0.7-dBm minimum third-order intermodulation intercept point (IIP3) from 1.05 to 3.05 GHz, while

(A.6) where is the dominant pole and Coefficient is given by

is the nondominant pole.

(A.7) In the first case, (A.5), bandwidth is enhanced by the factor of forward path gain for as before. The nondomto inant pole is shifted down from with included in the analysis. In the second case, (A.6), the dominant pole at the feedback summing node is enhanced by , the design dependent parameter. APPENDIX B NONLINEAR ANALYSIS USING VOLTERRA SERIES Here, the numerical computation of the Volterra series up to the third-order coefficients is evaluated with the direct calculation method.

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TABLE IV COMPARISON TO RECENTLY PUBLISHED WORKS

First, the small-signal gate–source voltages for nonlinear transistor , , and is modeled by the Volterra kernels in terms of the excitation voltage

-order Volterra kernels [18]. As in (20), noncorresponding linear drain current for , , and can be expanded by power series (B.4) (B.5) (B.6)

(B.1) Applying the Kirchhoff’s current law equations for each node of the circuit in Fig. 7, we have (B.2)

(B.7) (B.3) (B.8) is the Laplace variable, and the operator “ ” where means that the magnitude and phase of each spectral compois to be changed by the magnitude and phase of the nent of

(B.9)

(A.4)

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(B.15)

where (B.19) (B.10) (B.11) (B.12)

where the bar indicates the averaging of the transfer function over all possible permutations of the Laplace variables [18]. and are the first- and second-order transfer function of the corresponding gate–source voltage. For a two-tone as the available power of the signal excitation at and , generator at the third-order intercept point is given by [18]

(B.13) (B.20) Regardless of the order of the Volterra kernel, the calculation can be represented by the solution of the following general matrix equation [22]: (B.14) where is the admittance matrix of the circuit, is the -order Volterra kernel, and is the vector vector of the -order nonlinear current sources. The maof excitations and trix equation for the proposed LNA is derived from (B.7)–(B.9), as shown in (B.15) at top of this page. , , and , To find the linear transfer function and nonlinear current sources set excitation voltage . , , and determines the desired transfer function after the matrix inversion. To find the second-order transfer function, nonlinear current sources of order 2 is applied to the linearized network . Nonlinear in (B.15) with short-circuited excitation voltage transconductance of order 2 is as follows: (B.16) where is the second-order nonlinearity coefficient for the transistor . is the first-order transfer function of the corresponding gate–source voltage for the transistor . Second-order volterra kernels , , and are then derived from (B.17) The computation of third-order kernels are similar to the second-order computation. The desired third-order output is derived from the solution of the voltage kernel following matrix equation with nonlinear current source shown as follows:

(B.18)

ACKNOWLEDGMENT The authors would like to thank the Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu, Taiwan, for chip fabrication support. The authors would also like to thank R. Kulkarni, M. Onabajo, J. Wardlaw, E. Pankratz, H. Zhang, and M. López, all with Texas A&M University, College Station, for their technical discussions. REFERENCES [1] K. Vavelidis, I. Vassiliou, T. Georgantas, A. Yamanaka, S. Kavadias, G. Kamoulakos, C. Kapnistis, Y. Kokolakis, A. Kyranas, P. Merakos, I. Bouras, S. Bouras, S. Plevridis, and N. Haralabidis, “A dual-band 5.15–5.35-GHz, 2.4–2.5-GHz 0.18 m CMOS transceiver for 802.11a/b/g wireless LAN,” IEEE J. Solid-State Circuits, vol. 39, no. 7, pp. 1180–1184, Jul. 2004. [2] M. Zargari, M. Terrovitis, S. H.-M. Jen, B. J. Kaczynski, M. Lee, M. P. Mack, S. S. Mehta, S. Mendis, K. Onodera, H. Samavati, W. W. Si, K. Singh, A. Tabatabaei, D. Weber, D. K. Su, and B. A. Wooley, “A single-chip dual-band tri-mode CMOS transceiver for IEEE 802. 11a/b/g wireless LAN,” IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2239–2249, Dec. 2004. [3] A. Liscidini, M. Brandolini, D. Sanzogni, and R. Castello, “A 0.13 m CMOS front-end for DCS1800/UMTS/802.11b-g with multi-band positive feedback LNA,” IEEE J. Solid-State Circuits, vol. 41, no. 4, pp. 981–988, Apr. 2006. [4] P. Rossi, A. Liscidini, M. Brandolini, and F. Svelto, “A variable gain RF front-end, based on a voltage-voltage feedback LNA, for multistandard applications,” IEEE J. Solid-State Circuits, vol. 39, no. 2, pp. 368–374, Feb. 2004. [5] M. El-Nozahi, E. Sánchez-Sinencio, and K. Entesari, “A CMOS lownoise amplifier with reconfigurable input matching network,” IEEE Trans. Microw. Theory Tech., vol. 57, no. 5, pp. 1054–1062, May 2009. [6] H. Hashemi and A. Hajimiri, “Concurrent multiband low-noise amplifiers—Theory, design, and applications,” IEEE Trans. Microw. Theory Tech., vol. 50, no. 1, pp. 288–301, Jan. 2002. [7] T.-K. Nquyen, G. Ihm, M. Yang, and S. Lee, “CMOS low-noise amplifier design optimization techniques,” IEEE Trans. Microw. Theory Tech., vol. 52, no. 5, pp. 1433–1442, May 2004. [8] C. Kim, M. Kang, P.-T. Ahn, H. Kim, and S. Lee, “An ultra-wideband CMOS low-noise amplifier for 3–5-GHz UWB system,” IEEE J. SolidState Circuits, vol. 40, no. 2, pp. 544–547, Feb. 2005. [9] W.-H. Chen, G. Liu, B. Zdravko, and A. Niknejad, “A highly linear broadband CMOS LNA employing noise and distortion cancellation,” IEEE J. Solid-State Circuits, vol. 43, no. 5, pp. 1164–1176, May 2008.

KIM et al.: WIDEBAND CG CMOS LNA

[10] W. Zhuo, X. Li, S. Shekhar, S. H. K. Embabi, J. P. de Gyvez, D. J. Allstot, and E. Sánchez-Sinencio, “A capacitor cross-coupled commongate low-noise amplifier,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 52, no. 12, pp. 875–879, Dec. 2005. [11] X. Guan and A. Hajimiri, “A 24 GHz CMOS front-end,” IEEE J. SolidState Circuits, vol. 39, no. 2, pp. 368–374, Feb. 2004. [12] S. Woo, W. Kim, C. Lee, K. Lim, and J. Laskar, “A 3.6 mW differential common-gate CMOS LNA with positive-negative feedback,” in IEEE Int. Solid-State Circuits Conf. Tech. Dig., Feb. 2009, pp. 218–219. [13] Y. Cheng, C.-H. Chen, M. Matloubian, and M. J. Deen, “High-frequency small signal ac and noise modeling of MOSFETs for RF IC design,” IEEE Trans. Electron Devices, vol. 49, no. 3, pp. 400–408, Mar. 2002. [14] D. K. Shaeffer and T. H. Lee, “A 1.5-V, 1.5-GHz CMOS low noise amplifier,” IEEE J. Solid-State Circuits, vol. 32, no. 5, pp. 745–759, May 1997. [15] Q. Huang, F. Piazza, P. Orsatti, and T. Ohguro, “The impact of scaling down to deep submicron on CMOS RF circuits,” IEEE J. Solid-State Circuits, vol. 33, no. 7, pp. 1023–1036, Jul. 1998. [16] F. Bruccoleri, E. Klumperink, and B. Nauta, “Wide-band CMOS lownoise amplifier exploiting thermal-noise cancelling,” IEEE J. SolidState Circuits, vol. 39, no. 2, pp. 275–282, Feb. 2004. [17] C.-F. Liao and S.-I. Liu, “A broadband noise-canceling CMOS LNA for 3.1–10.6-GHz UWB receivers,” IEEE Trans. Microw. Theory Tech., vol. 42, no. 2, pp. 329–339, Feb. 2007. [18] V. Aparin and L. E. Larson, “Modified derivative superposition method for linearizing FET low-noise amplifier,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 2, pp. 571–581, Feb. 2005. [19] T. W. Kim, B. Kim, and K. Lee, “Highly linear receiver front-end adopting MOSFET linearization by multiple gated transistors,” IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 223–229, Jan. 2004. [20] W. Sansen, “Distortion in elementary transistor circuits,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 46, no. 3, pp. 315–325, Mar. 1999. [21] P. R. Gray, P. J. Hurst, S. H. Lewis, and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, 4th ed. New York: Wiley, 2001. [22] P. Wambacq and W. Sansen, Distortion Analysis of Analog Integrated Circuits. Norwell, MA: Kluwer, 1998. [23] A. Rofougaran, J. Y.-C. Chang, M. Rofougaran, and A. A. Abidi, “A 1-GHz CMOS RF front-end IC for a direct-conversion wireless receiver,” IEEE J. Solid-State Circuits, vol. 31, no. 7, pp. 880–889, Jul. 1996. [24] R. Ramzan, S. Andersson, J. Dabrowski, and C. Svensson, “A 1.4 V 25 mW inductorless wideband LNA in 0.13 m CMOS,” in IEEE Int. Solid-State Circuits Conf. Tech. Dig., Feb. 2007, pp. 424–425. [25] J. Borremans, P. Wambacq, and D. Linten, “An ESD-protected DC-to-6 GHz 9.7 mW LNA in 90 nm digital CMOS,” in IEEE Int. Solid-State Circuits Conf. Tech. Dig., Feb. 2007, pp. 422–423. [26] J.-H. C. Zhan and S. S. Taylor, “A 5 GHz resistive feedback CMOS LNA for low-cost multi-standard applications,” in IEEE Int. Solid-State Circuits Conf. Tech. Dig., Feb. 2006, pp. 721–730. [27] A. Bevilacqua and A. M. Niknejad, “An ultrawideband CMOS lownoise amplifier for 3.1–10.6-GHz wireless receivers,” IEEE J. SolidState Circuits, vol. 39, no. 12, pp. 2259–2268, Dec. 2004. [28] S. C. Blaakmeer, E. A. M. Klumperink, D. M. W. Leenaerts, and B. Nauta, “A wideband Balun-LNA with simultaneous output balancing, noise-canceling and distortion-canceling,” IEEE J. Solid-State Circuits, vol. 43, no. 6, pp. 1341–1350, Jun. 2008. Jusung Kim (S’10) received the B.S. degree in electrical engineering (with highest honors) from Yonsei University, Seoul, Korea in 2006, and is currently working toward the Ph.D. degree at Texas A&M University, College Station. In Summer 2008, he was a Design Intern with Texas Instrument Incorporated, Dallas, TX, where he designed an RF front-end for multistandard analog and digital TV silicon tuners. His research interests include transceiver system and circuit design at RF and millimeter-wave frequencies.

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Sebastian Hoyos received the B.S. degree from the Pontificia Universidad Javeriana (PUJ), Bogota, Colombia, in 2000, and the M.S. and Ph.D. degrees from the University of Delaware, Newark, in 2002 and 2004, respectively, all in electrical engineering. From 1999 to 2000, he was with Lucent Technologies Inc., during which time he was involved with the Andean region, South America. Simultaneously, he was a Lecturer with the PUJ, where he lectured on microelectronics and control theory. In Fall 2000, he joined the Department of Electrical and Computer Engineering, University of Delaware. During his master and Ph.D. studies, he worked under PMC-Sierra Inc., the Delaware Research Partnership Program, and the Army Research Laboratory (ARL) Collaborative Technology Alliance (CTA) in Communications and Networks. In Fall 2004, he joined the Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, where he was a Postdoctoral Researcher with the Berkeley Wireless Research Center. He is currently an Assistant Professor with the Department of Electrical and Computer Engineering, Texas A&M University, College Station. His research interests include communication systems, wireless communications, robust signal processing, and mixed-signal high-performance and low-power systems and circuit design.

Jose Silva-Martinez (SM’98–F’10) was born in Tecamachalco, Puebla, México. He received the M.Sc. degree from the Instituto Nacional de Astrofísica Optica y Electrónica (INAOE), Puebla, México, in 1981, and the Ph.D. degree from the Katholieke Univesiteit Leuven, Leuven Belgium in 1992. From 1981 to 1983, he was with the Electrical Engineering Department, INAOE, where he was involved with switched-capacitor circuit design. In 1983, he joined the Department of Electrical Engineering, Universidad Autónoma de Puebla, where he remained until 1993. In 1992, he pioneered the graduate program on opto-electronics. In 1993, he rejoined the Electronics Department, INAOE, and from May 1995 to December 1998, was the Head of the Electronics Department. In 1993, he was a cofounder of the Ph.D. program on electronics. He is currently a Professor with the Department of Electrical and Computer Engineering (Analog and Mixed Signal Center), Texas A&M University, College Station. He has authored or coauthored over 82 and 140 journal and conference papers, respectively, and one book and nine book chapters. His current field of research is in the design and fabrication of integrated circuits for communication and biomedical applications. Dr. Silva-Martinez was the IEEE Circuits and Systems Society (CASS) vice president of Region-9 (1997–1998). He was an associate Editor for the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—PART II: ANALOG AND DIGITAL SIGNAL PROCESSING (1997–1998 and 2002–2003), associate editor of the IEEE IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—PART I: REGULAR PAPERS (2004–2005 and 2007–2009), and currently serves on the Board of Editors of six other major journals. He was the inaugural holder of the Texas Instruments Professorship-I in Analog Engineering, Texas A&M University (2002-2008). Among other recongnitions, he was the recipient of the 2005 Outstanding Professor Award of the Electrical and Computer Engineering (ECE) Department, Texas A&M University, corecipient of the RF-IC 2005 Best Student Paper Award, and corecipient of the 1990 European Solid-State Circuits Conference Best Paper Award.

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Microwave Power Limiting Devices Based on the Semiconductor–Metal Transition in Vanadium–Dioxide Thin Films Julien Givernaud, Aurelian Crunteanu, Jean-Cristophe Orlianges, Arnaud Pothier, Corinne Champeaux, Alain Catherinot, and Pierre Blondy, Member, IEEE

Abstract—We present a novel concept of microwave (MW) power-limiting devices based on reversible semiconductor-tometal transition (SMT) of vanadium–dioxide thin films integrated on coplanar waveguides. We designed, simulated, and fabricated devices, which can be reversibly driven from a low-loss ( 0.7 dB) transmission state into an attenuating state ( 20 dB) as the VO2 material is changing from semiconductor to the metal state when the incident MW power exceeds a threshold value. These devices are broadband and present a tunable threshold power value. They could be easily integrated as protection circuits from excess power in a large variety of MW components. Index Terms—Coplanar waveguide (CPW) waveguide, microwave (MW) limiters, power dividers and combiners, semiconductor–metal transition (SMT), vanadium dioxide.

I. INTRODUCTION HE ever-increasing demand of high RF/microwave (MW) power capabilities in telecommunication and/or tracking systems raised the need for high-performance protection devices, which are able to limit the power densities or high-power transient signals incoming on low-power components of communication receiver front-ends (e.g., low-noise amplifiers that withstand no more that 20 dBm). The most common protection components for the RF/MWs domain are semiconductor power limiter devices that are limiting the input power to a specific designed value and for a specific frequency domain [1]. The most widely used solid-state passive power limiters (PPL) are based on semiconductor components like p-i-n diodes or MESFET transistors or combinations of the two [2]. However, the rapid development of advanced RF/MW components and systems in

T

Manuscript received September 09, 2009; revised April 02, 2010; accepted June 03, 2010. Date of publication August 09, 2010; date of current version September 10, 2010. This work was supported by the French National Research Agency (ANR) under Research Grant “Admos-VO2” ANR-07-JCJC-0047. J. Givernaud, A. Crunteanu, J.-C. Orlianges, A. Pothier, and P. Blondy are with the XLIM Laboratory, Unité Mixte de Recherche (UMR) 6172 University of Limoges/Centre National de la Recherche Scientifique (CNRS), 87060 Limoges, France (e-mail: [email protected]; [email protected]; [email protected]; [email protected]; [email protected]). C. Champeaux and A. Catherinot are with the Sciences des Procédés Céramiques et de Traitements de Surface (SPCTS) Laboratory, Unité Mixte de Recherche (UMR) 6638, University of Limoges/Centre National de la Recherche Scientifique (CNRS), 87060 Limoges, France (e-mail: [email protected]; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2010.2057172

terms of power and agility adds new demands for these control devices in terms of low power consumption, higher incident power control, high reliability, etc. Alternative promising solutions based on superconductor thin-film integration in coplanar MW waveguides have already been proposed [3], but these devices required supplementary cryogenic equipments. Our approach for fabrication of high-reliability/high-repeatability power limiter devices on a broadband frequency domain is based on the integration of vanadium–dioxide VO thin films in a coplanar waveguide (CPW) transmission line. Vanadium dioxide is one of the most interesting and studied members of the vanadates family performing a semiconductor–metal transition (SMT) phase [4]. Thus, at room temperature (low temperature state), VO is a highly resistive semiconductor with a bandgap of 1 eV. At temperatures higher than 68 C (341 K) the VO undergoes an abrupt transformation to a metallic state (low resistive phase), which is reversible when lowering the temperature below 65 C (the material again becomes a semiconductor) [4]–[7]. The phase transition is accompanied by a large modification of its electrical and optical properties: the electrical resistivity decreases by 3–5 orders of magnitude between the semiconductor and metallic states while the reflectivity in the optical domain increases. The reversible SMT can be rapidly triggered by different external excitations: temperature, optically, electrically—by charge injection, and even pressure [4]–[6]. Recent studies showed that the optically and electrically induced transitions can be very fast (in the range of hundreds of femtoseconds) and that the transition is more typical of a rearrangement of the electrons in the solid (electron–electron correlations) than an atomic rearrangement (crystalline phase transition from semiconductor monoclinic to a metallic rutile structure) [4], [5]. The transition temperature of the VO ’s SMT can be increased or decreased by doping with metals like W, Cr, Ta, or Al [8]. VO thin films also have a high voltage breakdown, which can be exploited for transmission of high power levels in MW devices. We used this characteristic for designing simple RF/MW passive power limiting components, which may be further developed as more complex devices. II. FABRICATION OF A POWER-INDUCE SWITCHING DEVICE A. Deposition of the VO Thin Layers VO layers of almost 250 nm in thickness were deposited on 500- m-thick C-type sapphire substrates by using the reactive pulsed laser deposition (PLD) technique. This technique

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GIVERNAUD et al.: MW POWER LIMITING DEVICES BASED ON SMT IN VANADIUM–DIOXIDE THIN FILMS

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Fig. 2. Image of a CPW waveguide loaded with VO patterns.

Fig. 1. Relative resistivity = versus temperature for a VO layer.

employs the laser ablation (KrF excimer laser at 248 nm, 25-ns pulse radiation) of a pure vanadium target under oxygen atmosphere and the deposition of the ablated and reactive species on a nearby substrate. The typical deposition parameters for obtaining crystalline, oriented VO layers are: laser fluency: 3.5 J/cm , distance target-substrate 50 mm, O2 pressure during deposition: 2.2 10 mbar, temperature of the substrates: 500 C [7], [9], [10]. After deposition, the VO layers were found to be crystalline by DRX characterization (monoclinic structure) with low roughness ( 10 nm rms). The VO resistivity values were measured by four-point resistivity measurements of the as-deposited layers as a function of temperature. Typical variation of the thin-film resistivity, with temperature (normalized to the resitivity at room temperature, ) is presented in Fig. 1. A typical hysteresis cycle of the resistivity is observed when the VO thin film is heated forward and backward around its transition temperature ( 70 C for the specific layer presented in Fig. 1) and one may notice a resistivity changes of around three orders of magnitude during the phase transition cycle.

Fig. 3. Measurements of transmission parameter S21 at 23 C of a CPW waveguide loaded with different VO patterns lengths (100 m: curve 1, 200 m: curve 2, 450 m: curve 3) and reflection parameter S11 (100 m: curve 1 , 200 m: curve 2 , 450 m: curve 3 ).

VO layer performs the phase transition (mainly induced by MW heating [11], [12]) and goes to its low-resistive metallic state. The RF/MW signal is thus shunted to the CPW ground and highly attenuated.

B. Fabrication of a MW Power Induce Switching Device (“Fuse”-Type Device)

C.

An optical microscopy image of the switching power device is presented in Fig. 2. As observed, it is based on an MW CPW with a VO thin-film pattern, which fills the gap between the signal line and ground lines. The components were fabricated in a clean-room environment using classical microfabrication technology [10]. The as-deposited VO layer was patterned using wet etching. It follows a thermal evaporation step of a Ti/Au seed layer and the electrolytic deposition of a 1.5- m-thick gold layer that is finally photolitographically patterned and wet etched for defining the CPW transmission line (Fig. 2). The operating principle of the component can be described as follows: at low incident MW power levels and room temperature, the VO is in its semiconducting state having a high resistivity and allows the signal to pass through the CPW line with almost no attenuation; when the power level of the in, the coming RF/MW signal exceeds a threshold value

Before testing the fabricated devices for their RF/MW power capabilities, we measured their -parameters for two extreme temperatures (room temperature at 23 C and heated at 100 C) for estimating, respectively, the transmitted losses when VO is in the semiconductor state (at room temperature) and the isolation of the transmission lines when VO is in the metallic transmission paramestate (when heated). The measured ters for a CPW loaded with VO patterns of different lengths (100, 200, and 450 m) are represented in Fig. 3 at room temperature [(VO in semiconductor state) and in Fig. 4 at 100 C (VO in the metallic state)]. As observed in Fig. 3, at room temperature, VO is in a semim) conductor state with a high resistivity (about allowing the RF signal to be transmitted through the CPW line with a very small attenuation from 100 MHz to 40 GHz (lower than 0.7 dB, depending on the VO patterns length). The reflecalso depend on the VO pattern lengths; tion parameters

-Parameters and Power Characteristics Measurements

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Fig. 4. Measurements of transmission parameter S 21 at 100 C of a CPW waveguide loaded with different VO patterns lengths (100 m: curve 1, 200 m: curve 2, 450 m: curve 3) and reflection parameter S 11 (100 m: curve 1 , 200 m: curve 2 , 450 m: curve 3 ).

Fig. 6. Transmitted 10-GHz RF power as a function of the incident power through a CPW line “loaded” with a 450-m-long VO film.

Fig. 5. Measurements of the dissipated signal when VO is in the metallic state of a CPW loaded with different VO patterns lengths (100 m: curve 1, 200 m: curve 2, 450 m: curve 3).

when VO is in the semiconducting state, is lower than 10 dB (Fig. 3). When the temperature is increased to 100 C (Fig. 4), VO passes in the metallic state and its resistivity decreases quickly m. The incident RF signal is reflected to backwards (attenuation higher than 32 dB from 100 MHz to values, 40 GHz), as indicated by the reflection parameters’ which are higher than 4 dB (on Fig. 4). On Fig. 5 is represented the part of the incident signal dissipated in a CPW line loaded with different VO patterns lengths (dissipation expressed as ) when VO is in the metallic state (dissipaand results on Fig. 4). tion curves associated with the measurements show The dissipation curves along with the that the signal is both dissipated and reflected in the devices when the VO patterns are in the metallic state. The MW power characterization of the devices, expressed as the characteristic transmitted power versus incident power (CW ] was realized in an MW power at 10 GHz) [ RF probe station with a controlled temperature under a dry

Fig. 7. Optical microscopy images of a CPW line loaded with a 450-m-long VO film at low incident power (a) P < P , and VO pattern activation when the incident power is superior to the threshold level (b) P > P .

atmosphere. A typical result is presented in Fig. 6 for a CPW loaded with a 450- m-long VO pattern. The incident RF power is transmitted through the CPW waveguide at low incident powers until a threshold value is reached W in the presented case, the value depends on the ( , through the combined VO thin-film pattern geometry). At action of the MW thermal dissipation/MW currents, VO transforms rapidly in a metallic state [7] and highly attenuates the incident signals with powers higher than this threshold value. The power-induced transition of the VO layer can be easily visualized by optical microscopy in the reflective mode since there is a relatively high optical contrast between the metallic and semiconducting states of the VO thin film. Fig. 7 presents optical microscopy images of a compound loaded with a 450- m-long VO film pattern being exposed to two different levels of MW

GIVERNAUD et al.: MW POWER LIMITING DEVICES BASED ON SMT IN VANADIUM–DIOXIDE THIN FILMS

Fig. 8. Transmitted 10-GHz MW power as a function of the incident power through different CPW lines charged with VO patterns of different length.

power. In the image on Fig. 7(a), the input power is inferior to , the entire VO pattern is still in its the threshold power semiconducting state (VO on the image), and the output power level is quasi-equal to the incident power one. As the in[see Fig. 7(b)], part of the cident power become higher than on Fig. 7(b), VO film is turn out to its metallic state (VO the darker color as compared to the VO part), the incident power is reflected (and partly dissipated) and the output power decrease to zero. The totality of the VO pattern becomes metallic as the power is increased over a value of 1 W (for this specific device). For incident signal power levels as high as 5 W, the device is still operational. When the RF/MW power value is decreased back at a sufficient low level (close to 0.05 W), the device is allowed to cool down and the VO patterns turn again in a semiconductor state with its initial resistance value. This power induced VO transition behavior can be repeated indefinitely for a large number of cycles. We have fabricated simple switching power devices with different VO patterns lengths of 50, 100, 200, 400, and 600 m. Since these VO patterns do not have the same electrical resistances (and thermal capacitances), the incident MW power value needed to switch the device to the metallic state of VO is decreasing with increasing the VO pattern dimensions (Fig. 8). One may adjust the power threshold value of such a device (between 0.25 up to 1.2 W) by simply modifying the dimensions (and thus, the overall resistance) of the VO pattern. We also determined the impact of external parameters on the threshold power values of the fabricated devices (such as the temperature or a dc bias voltage applied across the VO patterns between the signal and the ground branches of the transmission line since the SMT of such VO patterns can be electrically triggered, as shown in [7] and [9]). It may be seen that the incident MW power needed for triggering the SMT in a VO film is lower when increasing the external temperature applied to the device (Fig. 9) or the dc voltage bias across the VO patterns (Fig. 10). Thus, one may tune the threshold power value of these devices by changing the environ-

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Fig. 9. Transmitted 10-GHz RF power versus the incident power through a CPW line “loaded” with a 100-m–long VO patterns for three different external temperatures (300, 313, and 323 K).

Fig. 10. Transmitted 10-GHz RF power versus the incident power through a CPW line “loaded” with a 400-m-long VO pattern for four different dc-bias voltages 10, 15, 20, and 22 V.

ment temperature or, in an easier way, the dc-bias voltage across the VO patterns. The devices can be used in a passive way by sizing the VO pattern dimensions for obtaining the desired threshold power values (as shown in Fig. 8), or in an active way, by applying a dc-bias voltage or temperature on the VO patterns to fine tune the threshold values (Figs. 9 and 10). In the light of the results presented thus far, the VO -based devices can be described as reconfigurable RF/MW power-induce switching devices (or simply, RF/MW “power fuses”) on a broadband frequency domain (100 MHz–40 GHz, as measured by us, but with potentially the same characteristics for even higher frequencies up to the terahertz domain) [7]. D. Identical Distributed VO Patterns on CPW Waveguide In order to realize a real power-limiter device (i.e., to obtain a relatively constant level of the transmitted power after reaching

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Z

Fig. 11. Optical microscopy image of a switching power device based on a CPW line “loaded” with four VO patterns 40-m long.

N

Fig. 13. Equivalent circuit of an -times dividers/combiners-based power is the impedance of the main CPW transmission line, is the limiters. impedance of a first branch, is the impedance of the second branch, and is the resistance of the active part of the device.

Z

Z

R

the incident signal along the transmission line. They act like small attenuators distributed along the CPW line. Although the transmitted power level is not constant, as with an ideal power limiter, the design can be improved by combining VO patterns having different lengths (and thus, different incident power attenuation capabilities). Yet an improved approach for realizing a true VO -based MW power limiter device is presented in Section III. It is based on a transmission line design including power dividers and combiners. III. FABRICATION AND MEASUREMENT OF VO -BASED POWER LIMITERS INCLUDING POWER DIVIDERS AND COMBINERS

Fig. 12. Measurement of transmitted versus incident MW power (at 10 GHz) of a four-pattern-type VO switching power device.

a threshold power value), we investigated a new design based on a CPW line loaded with several distributed VO patterns. We may expect that the incident MW power will be unevenly reflected/dissipated in the distributed patterns and that a certain fraction of the incident power will still be transmitted after each of the sequentially activated patterns. A first approach to fabricate a solid-state PPL, which can limit the transmitted power level at a constant value, is illustrated in Fig. 11. As observed in Fig. 12, when the incident power increases, the transmitted power also increases, until reaching a first threshold power value (at 0.35 W) corresponding to the first VO -distributed pattern, which pass to the metallic state (the incident RF power is partly reflected afterwards and the level of the transmitted power decreases). By further increasing the incident power from 0.35 to 0.6 W, the transmitted power also increases until the incoming power becomes sufficiently high to switch on the second VO pattern to its metallic state. The transmitted power drops off again and so on for the rest of the VO patterns. It may be noticed that the incident MW signal is not completely attenuated by the sequential actuation in the metallic state of the VO patterns. In such a configuration, the VO patterns with smaller dimensions (hence, higher resistances) will allow to pass some fraction of

The main idea of this new design methodology approach is that one of the two branches of a divider implemented on a CPW line will be connected to the ground line of the CPW by a VO -based thin-film pattern. The incident power will travel through the two branches of the divider and the two parts will be combined at the end of the CPW line. When the VO pattern of the loaded branch will be actuated, the power traveling in this part of the divider will be reflected/dissipated, while the other branch of the divider will transmit its power. This will result in transmitted power attenuation at the exit part of the CPW line. The transmitted power level depends on the number of diand of the viders/combiners and on the impedance ratio two branches of the dividers, ratios that can be simply expressed as (1) where are the characteristic impedances of the two branches of the divider, respectively. The equivalent circuit of the proposed device is presented in Fig. 13. In this equivalent circuit, is the resistance of the active part of the device composed of the VO resistance in series with a . nickel-doped carbon thin-film resistance VO is the incident power applied at the input of the device, is the output power, and and are the powers in the and impedance branches, respectively. As briefly described above, the working principle of the device considering only one divider/combiner ring and by neglecting the transmission losses is as follows.

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Fig. 15. Simulated (dashed curves 1 and 4) and measurements (full-line curves 2 and 3) of transmission parameters of the power limiter when VO is in a semiconductor state (curves 1 and 2) and in a metallic state (curves 3 and 4).

Fig. 14. Microphotograph of two-divider/combiner-based power limiters using two identical distributed VO and Ni-doped carbon patterns forming the active part of the device.

• When (VO highly reVO sistive, in semiconducting state), the signal passes through . the two branches with low losses • When VO transforms to the metallic state, will match the characteristic VO impedance of the active branch , the power impedance branch is reflected (part of the in the signal may be dissipated in the resistance ). The only signal coming out from the divider/combiner ring is the characteristic impedance branch with a signal in the . The output power of value of the device is thus limited with a ratio of . If the value would be much more lower than the characteristic of impedance , the incoming signal would . be completely reflected and We designed the VO -based power-limiter devices based on dividers/combiners rings using an ADS Momentum simulator by following the methodology presented in [13] for different models of ring couplers. Our design does not take into account the phase shifting of the signal in the devices [13] since we are not interested by this characteristic in our study. The ADS Momentum simulations show that the use of ground bridges in these CPW impedance transformer rings (for a uniform ground plane) does not significantly modify their -parameter responses. For keeping the fabrication process as simple as possible, we decided to avoid the use of such structures. An example of a fabricated device is presented in Fig. 14. The device presented in Fig. 14 (fabricated in a similar manner as described above for the power-induce switching devices) is composed of a 50- central linear transmission line and two rings (divider/combiner components). Each signal-dividing component has a 100- characteristic impedance branch ( with a smaller linewidth) and a 50- characteristic impedance

branch ( with a larger line width). The impedance difference of the two branches makes the incident power to be divided in (in the 100- branches) and each ring with the ratio in the 50- branches. The 100- branches of each of the rings are connected to the ground plane using a VO pattern in series with an additional Ni-doped carbon pattern (acting as a series resistance and added in order to match as accurate as , similar possible an equivalent resistance VO with the line impedance, of 100 ). At low incident power , the VO pattern is in a semisquare), the conducting state and highly resistive (70 600 RF signal is transmitted with small attenuation through the two rings (Fig. 15 curve 1: measurements and curve 2: simulations). At incident powers higher than a threshold value, the VO pass . The in the metallic state and VO resistance of the VO pattern in its metallic form VO plus the resistance of the Ni-doped carbon pattern are designed to match the value of 100 , the same impedance as the thinnest branch of the rings. Thus, one third of the incident signal is attenuated by each ring (2-dB attenuation/ring), as indicated in Fig. 15: curve 3 (measurements) and curve 4 (simulations). The small differences between the simulations and measurement results when the VO is in the metallic state are due to the Ni-doped C resistances, which are slightly more resistive than designed and induced an impedance mismatch with the 100- branches. Indeed, not enough power is attenuated, the measurements showing an attenuation of only 3 dB. In Fig. 16, we can see that the device presents a quite good adaptation when VO is in the metallic state, with reflections lower than 12 dB on a wide frequency band. The optimization of the design (lineswidths, rings dimensions, their position, etc.) has been done for minimizing as much as possible the reflecparameter) in the most critical case, when VO is tions ( in the metallic state. When VO is in the semiconductor state, the reflections are lower than 15 dB. The resonance peak noted as “a” on the graphs in Fig. 15 comes from the resonance of the inter-ring line, while the peaks noted as “b” and “c” comes

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Fig. 16. Simulated (curves 1 and 4) and measurements (curves 2 and 3) of the S 11 reflection parameters of the power limiter in Fig. 13 when VO is in the semiconductor state (curves 1 and 2) and in the metallic state (curves 3 and 4).

Fig. 17. Measurements of the transmitted power versus the incident power (at 10 GHz) for a two-dividers/combiners-based power limiter (at 340 K).

from the resonance of the rings itself. The diameter of the rings and the inter-ring lines dimensions have been chosen in order to shift away these resonance peaks towards frequencies higher than 19 GHz while preserving device compactness. The characterization under incident power of the fabricated broadband power limiter device is presented in Fig. 17. As observed in the figure, at low incident power signals, when the power increases (the red curve in online version), the transmitted power increases proportionately until a threshold value (point 1 in Fig. 17). This threshold corresponds to a first VO pattern actuation in the first ring, attenuating a part of the incident signal. The VO patterns actuation behavior is the same as the one described in the previous section (switching power device). By further increasing the incident power, the transmitted power increases proportionately again until reaching a second threshold power value (point 2 in Fig. 17). This second threshold point corresponds to the VO pattern actuation in the second ring that attenuates a part of the incident signal. When

Fig. 18. Measurements of the transmitted power versus the incident power (at 10 GHz) for a two-dividers-based power limiter at different dc-bias voltages (40, 42, and 43.5 V) at room temperature.

decreasing the incident power, the VO patterns become again a semiconducting (the blue curve in online version of Fig. 17). The VO patterns actuation is sequential, insuring, as expected, a progressive limitation of the incident power. We must notice that these measurements were made at 340 K (“temperature bias” to the device) for ensuring low thresholds power values to the VO patterns. Indeed, our RF/MW power cycling setup is limited to 5 W maximum, which do not allow reaching the level of MW power required to switch on the VO patterns in the metallic state at room temperature. Nevertheless this can be circumvented by properly adjusting the device geometry (splitting ratios of the signal in the dividers), by adjusting the material properties, or by simply applying a dc-bias voltage across the patterns. Indeed, as previously shown for the switching power devices, different dc-bias voltages applied across the VO patterns allows to tune the characteristic of the device under cycled incident power (Fig. 18). The measurements depicted in Fig. 18 are realized by applying a dc-bias voltage between the central line and the ground line of the device. The incident power required switching the VO patterns to the metallic state decreases when the dc-bias voltage increases. Setting a dc-bias voltage between the central line and the ground of the CPW waveguide can trigger a specific threshold power value for the device. The power limitation obtained with this device is not perfectly constant, but we would expect that by increasing the number of the rings and by resizing precisely the resistance of the active part of the device in order to optimize the sequential activation of the VO patterns, we should achieve a quasi-constant transmitted power level. As an example, we present in Fig. 19 a similar fabricated device based on a three-dividers/combiners with a split ratio of 50/50 (two equal impedances branches of 70.7 per loop) integrated in series on a CPW line. The simulated and measured ) and, respectively, the reflection ( ) patransmission ( rameters are presented in Figs. 20 and 21, respectively. We observed experimentally that the transmitted power is highly lim-

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Fig. 19. Optical microscopy image of a three-dividers/combiners based power limiters using three identical distributed VO and Ni-doped carbon patterns forming the active part of the device. Fig. 21. Simulated (curves 1 and 4) and measurements (curves 2 and 3) of the reflection S 11 parameters for the three-rings type power limiter when VO is in the semiconductor state (curves 1 and 2) and in the metallic state (curves 3 and 4).

Fig. 20. Simulated (dashed curves 1 and 4) and measurements (full-line curves 2 and 3) of S 21 transmission parameters of the power limiter presented in Fig. 18, when VO is in a semiconductor state (curves 1 and 2) and in the metallic state (curves 3 and 4).

ited at almost constant values on a more extensive power range (Fig. 22). From the graphs in Fig. 21, we may notice a calculated decharacteriscrease of almost 25% in the slope of the tics after every VO patterns actuation (lines 1–3, respectively, in Fig. 22). In principle, by adding another seven identical rings to the device will allow to reach a quasi-constant output power (line 10 in Fig. 22) for a wide working device power range. In practice, the design of such VO -based power limiters will depend on a specific demand, but the large possibilities of the design variables (number of combiners/dividers, their split ratios, the material characteristics, the device tuning capabilities, etc.) allow considering such devices for a broad area of applications. Work is ongoing for assessing the time response of these types of devices (by applying pulsed MW power), as well as their reliability (maximum number of cycles under different levels of power, different bias, etc.).

Fig. 22. Measurements of the transmitted power versus the incident power (at 10 GHz) for a three-dividers based power limiter device (shown in the insert) at 340 K.

IV. CONCLUSION We have designed and fabricated new passive RF/MW power limiters based on semiconductor to metal transition in vanadium–dioxide thin films on CPW transmission lines. Firstly, we proposed a simple design composed of a CPW line loaded with VO patterns, which fill the gap between the signal line and the grounds lines of the CPW. This power-induced switching device behaves like an MW “fuse” on a very broad frequency band, from 100 MHz to 40 GHz. It can be used either in a passive or in an active way by changing external parameters like temperature or by applying a dc-bias voltage across the VO pattern to modify the threshold power values. We also proposed a more complex device based on a CPW line on which are implemented power dividers/combiners associated with VO and Ni-doped carbon patterns. These simple PPL devices can limit the RF/MW incident power on a large band of frequency and

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could be easily implemented as broadband protection devices from excess power in different types of MW circuitry. REFERENCES [1] R. F. Bilotta, “Receiver protections: A technology update,” Microw. J., vol. 40, no. 8, pp. 90–96, Aug. 1997. [2] A. Phommahaxay, G. Lissorgues, L. Rousseau, T. Bourouinaand, and P. Nicole, “Towards a frequency-selective microwave power limiter for defense and aerospace applications,” in Proc. 4th Eur. Radar Conf., Munich, Germany, Oct. 2007, pp. 335–338. [3] J. C. Booth, K. Leong, and S. A. Schima, “A superconducting microwave power limiter for high-performance receiver protection,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2004, pp. 139–142. [4] F. Morin, “Oxide which shows a metal-to-insulator transition at the high temperature,” Phys. Rev. Lett., vol. 3, pp. 34–36, 1959. [5] G. Stefanovich, A. Pergament, and D. Stefanovich, “Electrical switching and Mott transition in VO2,” J. Phys., Condens. Matter, vol. 12, pp. 8837–8845, 2000. [6] A. Cavalleri et al., “Femtosecond structural dynamics in VO during an ultrafast solid-solid phase transition,” Phys. Rev. Lett., vol. 87, no. 23, pp. 237401-1–237401-4, 2001. [7] F. Dumas-Bouchiat, C. Champeaux, A. Catherinot, A. Crunteanu, and P. Blondy, “RF-microwave switches based on reversible semiconductor–metal transition of VO thin films synthesized by pulsed-laser deposition,” Appl. Phys. Lett., vol. 91, pp. 223505-1–223505-3, 2007. [8] I. Kitahiro and A. Watanabe, “Shift of transition temperature of vanadium dioxide crystals,” Jpn. J. Appl. Phys., vol. 6, pp. 1023–1024, 1967. [9] J. Givernaud, C. Champeaux, A. Catherinot, A. Pothier, P. Blondy, and A. Crunteanu, “Tunable band stop filters based on metal insulator transition in vanadium dioxide thin films,” presented at the IEEE MTT-S Int. Microw. Symp., Atlanta, GA, Jun. 15–20, 2008, Paper WEP1D-02. [10] J. Givernaud, C. Champeaux, A. Catherinot, A. Pothier, P. Blondy, and A. Crunteanu, “CPW self-resetting power limiting devices based on microwave power induced semiconductor–metal transition in vanadium dioxide,” presented at the IEEE MTT-S Int. Microw. Symp., Boston, MA, Jun. 6–12, 2009, Paper TUE2-5. [11] J. Geist, J. J. Shah, M. V. Rao, and M. Gaitan, “Microwave power absorption in low-reflectance, complex, lossy transmission lines,” J. Res. Nat. Stand. Technol., vol. 112, pp. 177–189, Aug. 2007. [12] J. J. Shah, S. G. Sundaresan, J. Geist, D. R. Reyes, J. C. Booth, M. V. Rao, and M. Gaitan, “Microwave dielectric heating of fluids in an integrated microfluidic device,” J. Micromech. Microeng., vol. 17, pp. 2224–2230, Oct. 2007. [13] C.-H. Ho, L. Fan, and K. Chang, “New uniplanar coplanar waveguide hybrid-ring couplers and magic-T’s,” IEEE Trans. Microw. Theory Tech., vol. 42, no. 12, pp. 2440–2448, Dec. 1994. [14] G. Ponchak and J. Papapolymerou, “180 degree hybrid (rat race) junction on CMOS grade silicon with a polyimide interface layer,” in IEEE Si Monolithic Integr. Circuits RF Syst. Top. Meeting Dig., Grainau, Germany, Apr. 2003, pp. 96–99.

Julien Givernaud received the Bachelor degree in material science from the Engineering National School of Limoges (ENSIL), Limoges, France, in 2006, and is currently working toward the Ph.D degree at the University of Limoges, Limoges, France. Since 2007, he has been with the XLIM Research Institute, Centre National de la Recherche Scientifique (CNRS)/University of Limoges. His research interests include the integration of smart materials (mainly VO ) in RF-MW devices.

Aurelian Crunteanu received the Phys. Eng. degree in optics and optical technologies, Master’s degree, and Ph.D. degree in physics from the University of Bucharest, Bucharest, Romania, in 1995, 1996, and 2000, respectively, and the Ph.D. degree in material sciences from the Claude Bernard University, Lyon 1, France, in 2001. From 2001 to 2003, as a Post-Doctoral Fellow with the Institute of Imaging and Applied Optics, Swiss Federal Institute of Technology, Lausanne, Switzerland, his research was oriented on the fabrication and characterization of microstructures and nanostructures in laser host materials, and laser-assisted thin-film deposition. Since 2003, he has been a Researcher with the Centre National de la Recherche Scientifique (CNRS), XLIM Research Institute, University of Limoges, Limoges, France. His current research activities are focused on the development of new materials for microelectronics and optics, RF microelectromechanical systems (MEMS) reliability, and optical switching using MEMS technology. Jean-Christophe Orlianges received the Ph.D. degree in material sciences from the University of Limoges, Limoges, France, in 2003. From 2008 to 2009, he was with the Centre National de la Recherche Scientifique (CNRS), as a Research Engineer with the XLIM Laboratory. He is currently an Assistant Professor with the Faculty of Science, University of Limoges. He conducts research with the Sciences des Procédés Céramiques et de Traitements de Surface (SPCTS) Laboratory, Unité Mixte de Recherche (UMR) 6638, CNRS/University of Limoges. His main research interests are pulsed-laser thin-films deposition techniques, nanostructured materials, and development and integration of new materials in electronic and optic devices. Arnaud Pothier received the Ph.D. degree in electrical engineering from the University of Limoges, Limoges, France, in 2003. He is currently a Full-Time Researcher with the Centre National de la Recherche Scientifique (CNRS), XLIM, University of Limoges. His current research activity in focused on tunable functions developments and implementation for analog communication modules using RF MEMS components like filters and phase shifters.

Corinne Champeaux received the Ph.D. degree in electrical engineering from the University of Limoges, Limoges, France, in 1992. Since 1992, she has been an Assistant Professor with the Faculty of Science, University of Limoges. She currently conducts research with the Sciences des Procédés Céramiques et de Traitements de Surface (SPCTS) Laboratory, Unité Mixte de Recherche (UMR) 6638, Centre National de la Recherche Scientifique (CNRS), University of Limoges. Her main research interests are laser–matter interactions and pulsed-laser thin-films deposition techniques. She is involved with the development and fabrication of MEMS components through the elaboration of new materials and fabrication processes. Alain Catherinot received the Doctorate degree in physical sciences from the University of Orléans, Orléans, France, in 1980. He is currently a Professor with the Process and Material Sciences Department, University of Limoges, Limoges, France, where he conducts research on pulsed laser deposition (PLD) techniques with the Sciences des Procédés Céramiques et de Traitements de Surface (SPCTS) Laboratory, Unité Mixte de Recherche (UMR), Centre National de la Recherche Scientifique (CNRS). His research interests include plasma and laser materials interactions, PLD of thin films and nanostructured materials, and their characterizations. He is also involved in MEMS fabrication using innovative deposition methods and materials.

GIVERNAUD et al.: MW POWER LIMITING DEVICES BASED ON SMT IN VANADIUM–DIOXIDE THIN FILMS

Pierre Blondy (M’00) received the Ph.D. and Habilitation degrees from the University of Limoges, Limoges, France, in 1998 and 2003, respectively. From 1998 to 2006, he was with the Centre National de la Recherche Scientifique (CNRS), as a Research Engineer with the XLIM Laboratory, where he began research on RF MEMS technology and applications to MW circuits. He is currently a Professor with the University of Limoges, where he leads a research group on RF MEMS. He was a Visiting Researcher with The University of Michigan at Ann Arbor (1997) and the University of California at San Diego, La Jolla (2006 and 2008). Dr. Blondy was an associate editor for the IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS in 2006. He has been a member of the IEEE International Microwave Conference Technical Program Committee since 2003.

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Digitally Driven Antenna for HF Transmission Steven D. Keller, Member, IEEE, W. Devereux Palmer, Senior Member, IEEE, and William T. Joines, Life Fellow, IEEE

Abstract—An electrically small antenna connected directly to a complementary pair of switching transistors is driven with a pulsewidth modulated HF signal, eliminating the requirement for a frequency-dependent impedance-matching network. The intrinsic reactance of the transmit and receive antennas acts as a filter to recover the HF signal from the digital pulse train. This is defined here as the digitally driven antenna architecture. A circuit simulator with broadband equivalent-circuit models for the transmit and receive antennas is used to predict the received signal in the time domain, and the expected received spectrum is calculated using Maxwell’s equations and the fast Fourier transform. The simulated circuit is realized using a highly capacitive electrically small dipole antenna driven at 1 MHz with a 10-MHz reference signal on the pulsewidth modulator as the transmitter and a highly inductive 470- H ferrite-loaded loop as the receive antenna. The 1-MHz signal is clearly evident in the time-domain received signal on an oscilloscope, and also in the received spectrum, as observed on a spectrum analyzer. This demonstrates that indeed it may be possible to produce efficient radiation across a wide bandwidth from an electrically small antenna by driving the antenna directly with a digital pulse train. Index Terms—Antenna, communication system, electrically small, HF, pulsewidth modulation, switching amplifier, VHF.

I. INTRODUCTION S semiconductor technology has matured over the years, the incorporation of active devices such as transistor amplifiers with passive antenna elements has become an increasingly fertile topic of interest, enabling increased system bandwidth and reduced system size [1]. Extensive research has been conducted on the integration of antenna structures with linear push–pull power amplifiers [2], such as Class AB [3] and Class B [4] amplifiers, to yield fully integrated active antennas that offer efficiencies of between 55%–65%. While this research has yielded some significant advances in the area of active antennas, the limitation of its scope to linear amplifier classes has, in turn, limited the maximum achievable power efficiencies of the resulting active antenna systems.

A

Manuscript received January 15, 2010; revised May 16, 2010; accepted May 25, 2010. Date of publication August 16, 2010; date of current version September 10, 2010. This work was supported in part by the U.S. Army Research Laboratory and by the U.S. Army Research Office under Agreement W911NF-04-D-0001, Delivery Order 0003. S. D. Keller was with the Electrical and Computer Engineering Department, Duke University, Durham, NC 27708 USA. He is now with the U.S. Army Research Laboratory, Adelphi, MD 20783 USA (e-mail: [email protected]. mil). W. D. Palmer is with the U.S. Army Research Office, Research Triangle Park, NC 27703 USA (e-mail: [email protected]). W. T. Joines is with the Electrical and Computer Engineering Department, Duke University, Durham, NC 27708 USA (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2010.2058553

A chief concern of merging an antenna structure with a higher efficiency amplifier, such as a switching Class D amplifier driven by an RF carrier modulated with a desired information signal and then encoded into a digital pulse train, is that a narrowband filtering mechanism still is needed between the amplifier output and the load in order to suppress the switching signal and harmonics and recover the modulated carrier. Additionally, if the antenna is electrically small compared to the wavelength of the radiated signal [5], it has been shown that under traditional linear operation, such an antenna can only operate over a moderate bandwidth with very low efficiency [6], [7]. However, the capacitive reactance of the electrically small antenna serves as an effective output filter that aides in recovery of the original baseband signal at the output of the switching amplifier without using a narrowband filtering circuit, and consequently provides high-efficiency power transfer to the antenna without reducing its operational bandwidth or radiation efficiency. This technique was first proposed by Merenda [8], [9], who developed the theory and initially demonstrated the concept at audio frequencies. Its application at RF frequencies, where it will have the most impact on the size and performance of a communication system, is the focus of this paper. A proof-of-concept that the digitally driven antenna (DDA) architecture can be used with an electrically small antenna to transmit an HF signal without the need for conjugate impedance matching will be presented. A quantitative evaluation of the DDA architecture efficiency is under investigation and will be reported in a future paper. The circuit in Fig. 1 defines the difference between the standard heterodyne radio architecture and the new architecture, which is formally established in this work as the DDA architecture. The generation of the modulated carrier is the same in both architectures, as is the antenna. The distinguishing difference is that while in the heterodyne architecture the signal remains analog and is amplified using a linear amplifier with an impedance matching network, in the DDA architecture the antenna is driven by an encoded digital pulse train whose power is amplified by a complementary pair of switching transistors. This circuit draws from techniques developed for modern Class D power amplifiers in order to drive an antenna with a pulsewidth modulated HF signal at maximized power efficiency. The proposed communication system will begin with an HF band RF signal, amplitude modulated with a desired information signal. This RF signal is then pulsewidth modulated and sent to the base terminals of two semiconductor switching devices, such as bipolar junction transistors (BJTs) or MOSFETs. Since the transistor switches operate in either cutoff or saturation due to the digital pulsewidth modulation bias signal, there is no quiescent transistor bias current and the power efficiency for the system is increased.

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TABLE I DDA SYSTEM CLASS-D AMPLIFIER COMPONENT LIST

Fig. 1. (top) DDA architecture versus (bottom) standard heterodyne radio transmitter architecture. Note that the power amplifier and matching network in the standard circuit are replaced by a pulsewidth modulator (PWM) and switching transistors in the DDA system.

The spectrum of this output digital signal is composed of the original modulated carrier signal, the sampling clock signal for the pulsewidth modulator (typically a sawtooth or triangle wave), and various harmonics and intermodulation products. A filtering mechanism at the amplifier output prior to the load, typically in the form of an L–C low-pass filter, is traditionally employed to suppress the switching signal and its harmonics within the amplified output signal and to pass only an amplified form of the modulated carrier signal to the load. In this experiment, however, no discrete filtering mechanism will be included. Instead, the implicit reactance of the antenna system will be used as the filtering mechanism through which the modulated carrier signal is recovered.

Fig. 2. Electrically small dipole antenna with a cylindrical balun.

II. SYSTEM DESIGN AND MODELING A. System Design A DDA system was designed to transmit an unmodulated 1-MHz carrier and system performance was modeled using a circuit simulator. The crux of the DDA system is the pulsewidth modulator and the complementary pair of switching transistors. The fidelity of the recovered signal on the receiver end relies strongly on the accuracy of the pulsewidth modulator output and the switching capabilities of the transistors. Thus, great care must be taken in the design of this circuit to ensure the proper functionality of the complete DDA system. The discrete passive and active components for this design are shown in Table I. The Maxim MAX999 comparator was chosen for its high-speed operation with 2.3-ns rise and fall times and a maximum propagation delay of 8.5 ns. The decoupling capacitor values, 0.1 and 1 F, were selected based on the recommendations found in [10] in order to stabilize the power supply voltage at the comparator chip. The Fairchild MMBT5770 NPN BJT and the Fairchild MMBTH81 PNP BJT were selected based on their switching capabilities, each with an of 600 MHz, fast enough for operation in the HF/VHF frequency range. SPICE

Fig. 3.

S

plot for DDA system transmit dipole antenna.

models that accurately predict device performance are readily available for these parts. A dipole antenna with a cylindrical balun was selected as the transmit antenna, as shown in Fig. 2. The dipole arms have a radius of 0.15 cm and a total length of approximately 9.1 cm. The reflection coefficient plot for this antenna, shown in Fig. 3, indicates that under traditional operation, the antenna has a resonant frequency of about 1.26 GHz. However, at the DDA carrier in frequency of 1 MHz, this antenna is approximately length, which certainly qualifies it as electrically small. A ferrite rod loop antenna, typically used for reception of low-frequency AM radio signals between 520–1610 kHz, was

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Fig. 4. Discrete component model of electrically small dipole transmit antenna, including the balun capacitance, and the inductance of the loop stick receive antenna.

selected as the receive antenna. This type of antenna is highly inductive; the antenna used in this experiment can be modeled as a 470- H inductor. B. System Circuit Model A variety of models have been developed for electrically small antennas such as one based on spherical waves [11] and another utilizing broadband lumped elements [12]. However, according to [13], these models have greater than 30% error when compared for antennas with a dipole length less than with analytical solutions from [14] and [15]. The empirical formulas determined in [13] and [16] may be used to establish a four-element model of an electrically small dipole antenna that is highly accurate for an antenna with length less than . Based on the existing literature, the optimal model dipole antenna used in available for simulation of the the DDA system experiment is shown in [13, Fig. 3]. Using cm and radius cm, a dipole arm length the final lumped-element model has the corresponding values fF, nH, , and fF. Additional capacitance must be added to this model to account for the capacitance of the cylindrical balun structure. Using the balun radius of 0.5 cm and length of 8 cm, the added capacitance can be approximated by using the formula for the capacitance between two concentric cylinders pF

(1)

Thus, at least 8.5 pF of extra capacitance needs to be added to the existing circuit model of the dipole antenna in order to produce an accurate simulation of the DDA system. By examining the spectral simulation results for added capacitance ranging from 8.5 to 40 pF, it was found that 20 pF produced the closest match to the experimental results. The additional 11.5 pF likely is due to the fringing fields between the tuning slots along two sides of the balun and from the balun edge at the dipole antenna junction. The complete circuit model of the transmit dipole antenna with added balun capacitance and the output inductive loop antenna is shown in Fig. 4. Performance of the complete circuit including the transmit and receive antennas was modeled using National Instruments’

Fig. 5. Schematic of complete DDA system as represented in National Instruments’ Multisim Circuit Design program. Transmit and receive antenna models from Fig. 4 are substituted for the 50- resistor R4 in the simulation of the full DDA system.

Multisim Circuit Design program. The schematic is shown in Fig. 5. The XFG1 device generates a 1-MHz sine wave that is sent to the noninverting input of the MAX999 comparator, while the XFG2 device generates a 10-MHz triangle wave that , is sent to the inverting input. Both input signals were set to 1 consistent with the operating parameters of the comparator. The comparator output is a digital pulsewidth modulated signal with a duty cycle that varies according to the amplitude of the 1-MHz carrier signal. This signal is then fed into the base terminals of an NPN/PNP transistor pair arranged in a push–pull configuraV, is contion. A dual voltage power supply, nected to the system with the positive voltage connected to the collector terminal of the NPN transistor and the negative voltage connected to the collector terminal of the PNP transistor. Since it was not possible to explicitly simulate the radiation of the time-domain input signal from the electrically small dipole to the ferrite rod loop antenna, the approximate simulated spectrum of the received signal was calculated from the current . First, this passing through the antenna system output current was recorded for 100 cycles of the 1-MHz input signal. Next, this data was used to yield an approximation of the spectrum of the received signal by applying Maxwell’s equations governing antenna radiation and reception and the fast Fourier transform (FFT). From Ampere’s Law, (2) it is seen that the magnetic field is proportional to the current in the Multisim density , which can be associated with simulation such that (3) From Faraday’s Law, the voltage at the terminals of the receive antenna is (4)

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Fig. 6. Diagram of the experimental setup used to evaluate the performance of the complete DDA system.

and so the following approximation is obtained by substituting for in (4): Received signal

Fig. 7. Comparison of measured and simulated output with the dipole antenna disconnected and the switching transistors terminated with a 50- resistor. Pulsewidth modulation by the 1-MHz carrier signal is clearly visible.

(5)

Thus, by taking the time derivative of the simulated current to properly scale through the antenna model, multiplying by the value for free-space radiation, and performing an FFT on the resulting signal, an approximate frequency-domain representation of the received signal was obtained for the simulated DDA system. Simulation results will be shown and compared to experimental measurements in Section III. III. EXPERIMENTAL SETUP AND RESULTS Fig. 6 shows a diagram of the experimental setup used to evaluate the performance of the DDA system. The Tektronix AWG520 arbitrary waveform generator simultaneously provides a 1-MHz carrier signal and a 10-MHz triangle wave PWM reference signal, both with a peak-to-peak voltage of 1 V, to the comparator listed in Section II in order to achieve pulse modulation. The pulsewidth modulated signal is amplified by the switching transistors and used to drive the electrically small dipole antenna. The signal transmitted by the dipole is received by the ferrite rod loop antenna a short distance away. For an electrically small transmitting antenna, far-field measurement of a 1-MHz carrier would require the transmit and receive antennas to be m

(6)

With the existing laboratory space, the experimental measurements were limited to the reactive near field and were made with the dipole antenna approximately 15–20 cm away from the ferrite rod loop antenna in order to minimize additional amplification components on the receive end of the system. The received signal is displayed on Agilent’s E4446A spectrum analyzer and Tektronix’s DSA 602A digitizing signal analyzer in order to simultaneously observe the spectrum and time-domain waveform of the received signal. To evaluate the performance of the pulsewidth modulator and the switching transistors separately, the antenna models in the simulation both were replaced with a single 50- resistor and

Fig. 8. Measured time-domain output of full DDA system.

the model output was recorded for 10 s. The dipole antenna was disconnected and the experimental output of the switching transistors also was recorded on the DSA 602A. A comparison of the simulated and measured results is shown in Fig. 7. The pulsewidth modulation corresponding to the 1-MHz carrier signal is clearly visible. Due to variability in the experimental load impedance, the amplitude of the measured signal is slightly higher than the Multisim simulation results. Some slight ringing is observed at the pulse transition points from low to high and high to low, but the amplified pulses are generally stable and compare favorably with the simulated results. With the key component performance validated through modeling and experiment, the dipole was reconnected and the complete DDA system was tested by measuring the signal received by the ferrite rod loop antenna. The time-domain received signal is shown in Fig. 8. The received nonamplified signal is relatively small at approximately 3-mV peak-to-peak. This is most likely due to the large impedance mismatch between the receive antenna, apat 1 MHz, and the 50- instrumentation proximately

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signal amplitudes down to acceptable levels. While many unanswered questions about this technique remain, this proof of concept experiment demonstrates the possibility of achieving a dramatic reduction in the size and signature of antennas for mobile wireless communications systems. Further exploration of this technique through refinement of the proposed model and experimentation may lead to a revolutionary transceiver system capable of efficient radiation across a wide bandwidth from an electrically small antenna. REFERENCES

Fig. 9. Comparison of measured and normalized simulation spectrum data from the complete DDA system.

inputs. Despite the small amplitude of the received signal, the original 1-MHz baseband signal is distinctly visible within this measured data. A comparison of the normalized measured spectrum with the expected received spectrum as calculated from the circuit simulator output described in Section II is shown in Fig. 9. The simulation results validate the amplitude and frequency of the 1-MHz carrier wave, harmonics, and intermodulation products. As expected from the time-domain measurements, the 1-MHz carrier signal again is dominant. The harmonics and intermodulation products associated with the pulsewidth modulation of the carrier signal still are evident in the final received signal spectrum, although they are considerably reduced in amplitude. The strongest of these higher frequency signals is the 10-MHz pulsewidth modulator reference signal at about 12 dB down from the 1-MHz carrier.

IV. CONCLUSION This paper has defined the DDA architecture as first proposed by Merenda and demonstrates the viability of the technique at HF frequencies through simulation and measurement of a DDA system designed to transmit a 1-MHz signal through an elec) antenna. In this experitrically small (approximately ment, the power amplifier and matching network used in the typical heterodyne radio architecture were replaced by a pulsewidth modulator and a pair of switching transistors. Transmission of the 1-MHz carrier was clearly evident in both the simulated and measured data. Additionally, a circuit model for a DDA system has been developed and time-domain simulation results of this model validate the experimental data. Since the measured amplitudes of the harmonics and intermodulation products associated with the pulsewidth modulation of the carrier signal in this first design are much higher than those necessary to meet standard Federal Communications Commission (FCC) transmission requirements, future research of this technique and refinement of this circuit design should focus on techniques to reduce these

[1] J. Lin and T. Itoh, “Active integrated antennas,” IEEE Trans. Microw. Theory Tech., vol. 42, no. 12, pp. 2186–2194, Dec. 1994. [2] V. Radisic, Y. Qian, and T. Itoh, “Novel architectures for high efficiency amplifiers for wireless applications,” IEEE Trans. Microw. Theory Tech., vol. 46, no. 11, pp. 1901–1909, Nov. 1998. [3] W. R. Deal, V. Radisic, Y. Qian, and T. Itoh, “Integrated-antenna push–pull power amplifiers,” IEEE Trans. Microw. Theory Tech., vol. 47, no. 8, pp. 1418–1424, Aug. 1999. [4] V. Radisic, S. T. Chew, Y. Qian, and T. Itoh, “High-efficiency power amplifier integrated with antenna,” IEEE Microw. Guided Wave Lett., vol. 7, no. 2, pp. 39–41, Feb. 1997. [5] H. A. Wheeler, “Fundamental limitations of small antennas,” Proc. IRE, vol. 35, no. 12, pp. 1479–1484, Dec. 1947. [6] R. C. Hansen, “Fundamental limitations in antennas,” Proc. IEEE, vol. 69, no. 2, pp. 170–182, Feb. 1981. [7] S. R. Best, “A discussion on the quality factor of impedance matched electrically small wire antennas,” IEEE Trans. Antennas Propag., vol. 53, no. 1, pp. 502–508, Jan. 2005. [8] J. T. Merenda, “Synthesizer radiating systems and methods,” U.S. Patent 5,402,133, Mar. 28, 1995. [9] J. T. Merenda, “Digital wideband small antenna systems,” IEEE Antennas Propag. Mag., vol. 48, no. 5, p. 105, Oct. 2006. [10] “Max961 single, ultra-high-speed, 3 V= 5 V, beyond-the-rails comparator (datasheet),” Maxim, Sunnyvale, CA, Tech. Rep., 2007. [11] C. J. Chu, “Physical limitations of omnidirectional antennas,” J. Appl. Phys., vol. 19, pp. 1163–1175, Dec. 1948. [12] G. W. Streable and L. W. Pearson, “A numerical study on realizable broad-band and equivalent admittances for dipole and loop antennas,” IEEE Trans. Antennas Propag., vol. AP-29, no. 5, pp. 707–717, Sep. 1981. [13] T. G. Tang, Q. M. Tieng, and M. W. Gunn, “Equivalent circuit of a dipole antenna using frequency-independent lumped elements,” IEEE Trans. Antennas Propag., vol. 41, no. 1, pp. 100–103, Jan. 1993. [14] S. A. Schelkunoff and H. T. Friis, Antennas—Theory and Practice. New York: Wiley, 1952. [15] M. Kanda, “Analytical and numerical techniques for analyzing an electrically short dipole with a nonlinear load,” IEEE Trans. Antennas Propag., vol. AP-28, no. 1, pp. 71–78, Jan. 1980. [16] S. B. Wang, A. M. Niknejad, and R. W. Brodersen, “Modeling omnidirectional small antennas for uwb applications,” in IEEE AP-S Int. Symp Conf. Rec., 2004, pp. 1295–1298.

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Steven D. Keller (M’01) was born in Syracuse, NY, in 1982. He received the B.S. degree in electrical and computer engineering from Cornell University, Ithaca, NY, in 2004, and the M.S. and Ph.D. degrees in electrical and computer engineering from Duke University, Durham, NC, in 2006 and 2008, respectively. From 2002 to 2004, he was a Summer Intern with the Air Traffic Control Division, Sensis Corporation, Dewitt, NY. In 2006 and 2007, he was a Summer Intern with the Antennas and RF Technology Branch, Sensors and Electron Devices Directorate, U.S. Army Research Laboratory (ARL), Adelphi, MD. Since 2008, he has been an Electronics Engineer with the ARL, where he conducts research on electronic scanning arrays for SATCOM and radar systems, electrically small and low-profile/conformal antennas, and novel materials for antenna design.

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W. Devereux Palmer (S’89–M’91–SM’01) received the Ph.D. degree in electrical engineering from Duke University, Durham, NC, in 1991 He is currently a Program Manager with the U.S. Army Research Office, Research Triangle Park NC, where he is responsible for extramural basic research in computational electromagnetics, antennas, RF circuit integration, and power electronics. From 1991 to 2001, he was a Member of Technical Staff with the MCNC Research and Development Institute. He is currently engaged in antenna research as a member of the Duke University Graduate Faculty and occasionally teaches introductory electromagnetics. Dr. Palmer is a Registered Professional Engineer in the State of North Carolina. Since 2009, he has been chair of the Eastern NC Section.

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William T. Joines (M’61–SM’94–LSM’97–LF’08) was born in Granite Falls, NC. He received the B.S.E.E. degree (with high honors) from North Carolina State University, Raleigh, in 1959, and the M.S. and Ph.D. degrees in electrical engineering from Duke University, Durham, NC, in 1961 and 1964, respectively. From 1959 to 1966, he was a Member of Technical Staff with Bell Telephone Laboratories, Winston-Salem, NC, where he was engaged in research and development of microwave components and systems for military applications. In 1966, he joined the faculty of Duke University, where he is currently a Professor of electrical and computer engineering. He has authored or coauthored over 100 technical papers on electromagnetic-wave theory and applications. He holds 20 U.S. patents. His research and teaching interests are in the area of electromagnetic-wave interactions with structures and materials, mainly at microwave and optical frequencies. Dr. Joines was the recipient of the Scientific and Technical Achievement Award presented by the Environmental Protection Agency in 1982, 1985, and 1990.

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A Technique for Implementing Wide Dynamic-Range Polar Transmitters Jau-Horng Chen, Member, IEEE, Hao-Shun Yang, Student Member, IEEE, and Yi-Jan Emery Chen, Senior Member, IEEE

Abstract—This paper presents a technique for implementing wide dynamic-range polar transmitters based on the envelope elimination and restoration technique. The fast-varying instantaneous output power level is controlled by a switch that modulates the input signal of the power amplifier (PA), whereas the slow-varying average power level is controlled by changing the dc voltage of the drain of the PA. A cellular band prototype transmitter system is constructed using commercially available components. Using a CDMA2000 1 signal with 4.5-dB peak-to-average power ratio at 836.5 MHz, the prototype transmitter achieved a dynamic range of over 80 dB while passing the adjacent and alternate channel power ratios for the CDMA2000 standard without the use of digital pre-distortion or calibration.

Fig. 1. Block diagram of a conventional EER transmitter.

Index Terms—DC–DC power conversion, microwave amplifiers, power amplifiers (PAs), radio transmitters.

I. INTRODUCTION HE power amplifier (PA) is the most power-consuming component in an RF transceiver. Many efforts have been made to enhance the power efficiency of the PA by improving the PA design itself such as the class-E or class-F designs. However, the linearity requirements of certain communication standards forbid the use of such nonlinear PAs. Another way of improving PA efficiency can be achieved through system-level architectural improvements discussed in [1]. The envelope elimination and restoration (EER) technique is one such method that has been demonstrated in [2]–[4]. The basic block diagram of a conventional EER transmitter is shown in Fig. 1. An EER transmitter uses a high-efficiency switch-mode amplifier, or an envelope amplifier, to modulate the collector or drain of a power-efficient nonlinear RF PA. For modern communication standards such as the IS-95, CDMA2000, and W-CDMA standards, the PA must respond to not only the fast-varying instantaneous power level that changes in the order of microseconds,

T

Manuscript received March 12, 2010; revised June 10, 2010; accepted June 10, 2010. Date of publication August 05, 2010; date of current version September 10, 2010. This work was supported in part by the National Science Council, Taiwan, under Grant NSC 98-2220-E-002-030 and Grant 98-2220-E-002-031, and by the National Taiwan University (NTU) Excellence Research Project under Grant 98R0062-03. J.-H. Chen is with the Department of Engineering Science and Ocean Engineering, National Taiwan University, Taipei, Taiwan (e-mail: [email protected]. tw). H.-S. Yang and Y.-J. E. Chen are with the Department of Electrical Engineering, Graduate Institute of Electronics Engineering, and Graduate Institute of Communication Engineering, National Taiwan University, Taipei, Taiwan (e-mail: [email protected]; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2010.2057810

Fig. 2. Block diagram of a pulse-modulated EER transmitter.

but also the slow-varying average power level that changes in the order of 1 ms. For an EER transmitter, both the fast- and slow-varying output power levels are controlled by the envelope amplifier, which leads to limited dynamic range of below 20 dB, as shown in [5]–[10]. Therefore, the conventional EER technique is not capable of meeting the 80-dB power control range defined in [11] and [12] for the CDMA2000 and W-CDMA standards, respectively. High-efficiency transmitters based on the modified EER technique that pulses the input signal of the RF PA and filters the unwanted spurs with a bandpass filter (BPF) have been demonstrated in [13]–[15]. The basic block diagram of such a technique is shown in Fig. 2. In this paper, a polar transmitter capable of meeting the dynamic-range requirements of the CDMA2000 standard based on the pulse modulation technique is demonstrated. The pulse-modulated input signal is used to control the fast-varying instantaneous power level, whereas, a dc–dc converter is used to modulate the drain voltage of the RF PA according to the slow-varying average power level, which is called the power-level tracking (PT) technique or the slow envelope tracking (ET) technique in [16]–[20]. The separation of the instantaneous power control and the average power control enables the pulse-modulated polar transmitter to achieve wide dynamic range. Moreover, high peak efficiency can be achieved concurrently, which is not seen in the fast ET technique reported

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in [21] due to the loss incurred from using a linear PA and a wideband envelope amplifier. II. THEORY OF OPERATION The EER technique has been a proven technique that is capable of improving the efficiency of the PA at power levels close to the maximum output power. Demonstrations for various standards with efficiencies in the 50% region have been reported in [7]–[10]. However, when operating under back off, the envelope amplifier must still operate under full speed, which degrades the overall efficiency. As a result, the efficiency of a conventional EER transmitter for wide bandwidth applications may drop almost as much as a linear PA under back off. The PAs for modern communication standards rarely operate close to the maximum output power level. Therefore, to achieve high peak efficiency and high average efficiency at the same time, a polar transmitter using concurrent dynamic supply modulation and input pulse modulation is proposed. The proposed transmitter seeks to combine the benefits of both a conventional EER transmitter and a PT PA. For a conventional EER transmitter, the output signal can be expressed as (1) where is the envelope signal, is the up-converted RF phase signal, is the gain of the RF PA is the magthat is dependent on the envelope signal, and nitude of the RF phase signal. For an ideal EER transmitter, is completely linear. However, in an actual implementation, becomes highly nonlinear when approaches the knee voltage of the RF power transistor. As a result, conventional EER transmitters may require digital pre-distortion or calibration for communication standards with zero-crossing signals or when highly backed off. For the modified EER transmitter used in this work, the output after filtering can be expressed as signal (2) is the gain of the RF PA that is dependent on where from the dc–dc converter, and , the supply voltage the magnitude of the RF phase signal. Unlike a conventional EER transmitter, the supply voltage does not change with respect to the instantaneous power level of the signal being transmitted. Therefore, the proposed transmitter does not have linearity concerns even when the supply voltage drops below the knee voltage. However, it is still desirable to keep the supply voltage over the knee voltage to ensure a positive PA power gain. Equation (2) also suggests that the average power level and can be completely separated from control using the instantaneous power control using , as proposed in this paper. III. SYSTEM IMPLEMENTATION The proposed polar transmitter uses an on–off modulator to generate a pulse-modulated constant-envelope RF signal, which is phase modulated by the polar phase of the in-phase/quadrature (IQ) signals, to control the instantaneous output power with

Fig. 3. Block diagram of the proposed wide dynamic-range pulse-modulated polar transmitter.

high efficiency. The on–off modulator is controlled by a digital pulsewidth modulator (DPWM). The duty cycle of the DPWM signal is generated by the polar magnitude or envelope of the IQ signals. Therefore, the pulse-modulated constant-envelope RF signal can be amplified by a highly efficient PA. The desired RF signal is restored by filtering out the harmonics of the pulse-modulated signal coming out of the RF PA using a BPF. Since the drain of the PA is freed from using the pulse-modulated architecture, the supply can then be adjusted according to the average power level like a PT PA using a conventional highly efficient dc–dc converter. The block diagram of the proposed transmitter architecture is shown in Fig. 3. The dynamic range of the pulse-modulated polar transmitter achieved by adjusting the supply voltage can be predicted as dB

(3)

and are the maximum and minimum where supply voltages applied to the RF PA, respectively. For this imV and V; thereplementation, fore, the power control of the pulse-modulated polar transmitter is about 11 dB. To meet the 80-dB power control requirement of the CDMA2000 or W-CDMA standards, the magnitude of the constant-envelope RF signal is controlled by a variable gain amplifier (VGA) before entering the on–off modulator. A detailed schematic of the RF PA, the dc–dc converter, and the RF switch in Fig. 3 is shown in Fig. 4. The input RF phase signal is first split by a power splitter before entering a pair of RF switches. The pair of commercially available switches [22] is internally matched to 50 , is connected to the input of a pair of two-stage PAs, and is used to modulate the constant envelope RF input signal. The pair of two-stage PAs uses commercially available cascaded enhancement-mode pseudomorphic high electron mobility transistors (PHEMTs) [23] biased slightly above the threshold voltage to operate under class AB. The output power of the pair of two-stage PAs was then combined using a power combiner. When close to the peak power level, the RF PAs are highly overdriven such that the PAs are switching to increase efficiency. Using a single-tone signal at 836.5 MHz, the two-stage PA delivered over 29 dBm of output power with over 20 dB of gain and 74% power-added efficiency (PAE). The dc–dc converter is constructed using a commercially available high-efficiency synchronous Buck converter operating with a 1-MHz

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Fig. 5. Implementation of the complete wide dynamic-range pulse-modulated polar transmitter. Fig. 4. Detailed schematic of the two-stage RF PA, dc–dc converter, and RF switch.

switching frequency [24]. The output voltage of the dc–dc converter was set by a digitally programmable resistor controlled through a field programmable gate array (FPGA) chip to form a digitally programmable power supply. The envelope signal was calculated using the formula (4) while the normalized IQ signals were generated using (5) and (6) The RF phase signal was then generated by vector modulating the and signals. The envelope signal is converted to a 18.75-MHz DPWM signal with MATLAB and loaded into a Rohde & Schwarz AFQ digital pattern generator, as in [15], without using any linearization such as pre-distortion or calibration. The DPWM signal of the pair of two-stage PAs is interleaved, as demonstrated in [8], such that the effective sampling frequency is doubled. The sampling frequency picked is sufficiently high for the DPWM aliasing components to be filtered by the output BPF. The sampling frequency is determined mainly by the BPF, which is a lot higher than the sampling frequency that may affect the ACLR. The BPF used is a commercially available surface-acoustic-wave (SAW) filter for CDMA handsets at 824–849 MHz, which has 1.9-dB insertion loss and 30–45-dB out-of-band suppression. The block diagram of the measurement setup is shown in Fig. 5. For testing purposes, the input power is controlled by the vector modulator instead of an actual VGA. IV. MEASUREMENT RESULTS AND DISCUSSIONS To assess the performance of the implemented transmitter system, an 836.5-MHz CDMA2000 1 signal with 4.5-dB peak-to-average power ratio is used for testing. Using a 3.6-V , to the dc–dc converter, the maximum PA supply, supply voltage is 3.45 V. The transmitter has a maximum

Fig. 6. Comparison of the PAE of the proposed transmitter without the dc–dc ), efficiency of the dc–dc converter alone ( – ), and the converter ( ) using a CDMA2000 1 overall PAE of the proposed transmitter ( signal at 836.5 MHz.

2

Fig. 7. Supply voltages to the RF PA and input power levels used for the proof 3.6 V. posed transmitter over an 80-dB range using a V

, of 25 dBm with an input of average output power, 4 dBm, which achieved a PAE of 40%. To achieve the desired power control range of 80 dB, the PA supply voltage is first lowered from 3.45 to 1.0 V. By lowering the supply voltage, the proposed transmitter attained a range of 11 dB similar to a conventional EER transmitter. However, unlike a conventional

CHEN et al.: TECHNIQUE FOR IMPLEMENTING WIDE DYNAMIC-RANGE POLAR TRANSMITTERS

Fig. 8. Measured ACPR results over an 80-dB average output power level range using a CDMA2000 1 signal at 836.5 MHz.

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Fig. 10. ACPR1 comparison of the proposed pulse-modulated polar transmitter : V using a CDMA2000 and a commercial CDMA PA with V 1 signal at 836.5 MHz.

=36

2

TABLE I DYNAMIC-RANGE COMPARISON OF EER AND POLAR TRANSMITTERS

Fig. 11. Output spectrum comparison of the proposed polar transmitter and a commercial cellular band CDMA PA normalized to the respective maximum : V using a CDMA2000 1 signal average output power with V at 836.5 MHz.

=36

2

Fig. 9. PAE comparison of the proposed pulse-modulated polar transmitter and : V using a CDMA2000 1 signal at a commercial CDMA PA with V 836.5 MHz.

=36

2

EER transmitter, the input power level can then be reduced like a linear PA to achieve the desired power control range of 80 dB. The DPWM remains operating at back-off power levels such that modulation accuracy can be maintained. A comparison of the PAE of the polar transmitter alone, the dc–dc converter efficiency, and the overall PAE of the proposed polar transmitter over the 80-dB dynamic power control range is , and shown in Fig. 6. The average input power levels, power supply voltages for controlling the average output power , are shown in Fig. 7. It is found that at a PA levels, supply voltage of 1.0 V, decreases monotonically with

Fig. 12. Wideband output spectrum of the proposed polar transmitter using a CDMA2000 1 signal at 836.5 MHz.

2

decreased . Therefore, the power control for this region can be achieved using a conventional automatic gain control (AGC) loop.

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TABLE II AVERAGE EFFICIENCY COMPARISON OF VARIOUS EFFICIENCY ENHANCEMENT SCHEMES FOR CDMA AND W-CDMA

TABLE III COMPARISON OF VARIOUS EER/ET TECHNIQUES AND CONVENTIONAL PA

The adjacent channel power ratio (ACPR1) and alternate channel power ratio (ACPR2) of the CDMA2000 standard are defined as the power difference between the integrated 1.23-MHz channel and the integrated power over a 30-kHz bandwidth at an 885-kHz and a 1.98-MHz offset, respectively. For the CDMA2000 standard defined in [11], the ACPR1 is required to be below 42 dBc over a 30-kHz bandwidth or 54 dBm over a 1.23-MHz bandwidth, whichever is easier. While the ACPR2 is required to be below 54 dBc over a 30-kHz bandwidth or 54 dBm over a 1.23-MHz bandwidth, whichever is easier. The ACPR measurements, shown in Fig. 8, are made using a spectrum analyzer, and seen to meet the stringent ACPR requirements over the entire range of 80 dB. For comparison, several transmitters using the EER or polar architecture with reported dynamic-range measurement results are compared in Table I. It is shown that highly efficient transmitters using the EER technique normally have dynamic ranges lower than 20 dB. To compare the performance of the proposed polar transmitter with a conventional PA, a commercial fixed bias cellular band PA is measured. The efficiencies over a 40-dB range below the of the proposed transmitter and the commermaximum cial PA are compared in Fig. 9. The measured results clearly show the advantage of using the proposed technique to improve . the efficiency of power levels close to the maximum The adjacent channel power ratios over an 80-dB range were compared in Fig. 10. For both the proposed transmitter and the commercial PA, the ACPR1 specification was passed with plenty of margin. Comparison of the output spectrums at their respective maximum average output power levels is shown in

Fig. 11. The measured wideband output spectrum of the pulsemodulated polar transmitter is shown in Fig. 12. The probability density functions (pdfs) of the PA output power levels for IS-95 CDMA and W-CDMA standards have been reported in [19]–[21]. Depending on the communication standard, the output power changes each burst, slot, or frame. The average efficiency can be derived as (7) where is the added power, is the output power level, is the input power level, is the probability density , and is the dc power at the output power level . Using the pdf consumption at the output power level of reported in [17], the average efficiency of the proposed transmitter, a cellular band commercial PA, and several PT/ET PAs recently reported were compared in Table II. Comparisons of various EER/ET techniques, including this work, with a conventional linear PA are summarized in Table III. Compared to the methods that require wideband envelope amplifiers to amplify the envelope signal, the proposed technique is simpler to implement. An off-the-shelf dc–dc converter can be used as long as its response time is within the requirement defined by the communication standard. For W-CDMA, the maximum response time is 25 s. Therefore, a 100-kHz bandwidth is more than sufficient for the dc–dc converter. For a regular CDMA EER transmitter, the envelope amplifier bandwidth is required to be about 5 MHz. Moreover, the proposed technique shows superior linearity without the use of digital pre-distortion or calibration, while showing high efficiency.

CHEN et al.: TECHNIQUE FOR IMPLEMENTING WIDE DYNAMIC-RANGE POLAR TRANSMITTERS

V. CONCLUSIONS A technique for implementing wide dynamic-range polar transmitters has been proposed. Using the technique, a highly efficient wide dynamic-range polar transmitter for cellular-band CDMA2000 1 application is designed and implemented. Using a pulse-modulated polar transmitter architecture and dynamic drain biasing concurrently, wide dynamic range for a polar transmitter can be achieved without compromising efficiency and linearity. The proposed polar transmitter system is experimentally verified to pass the stringent ACPR requirements for both the adjacent and alternate channels of the CDMA2000 standard for the entire 80-dB power control range at 836.5 MHz. Measurement results have also shown the proposed transmitter to be more than five times better than a fixed bias commercial linear PA in average efficiency.

ACKNOWLEDGMENT The authors would like to thank Rohde & Schwarz Taiwan Ltd., Taipei, Taiwan, and Prof. R.-B. Wu, National Taiwan University, Taipei, Taiwan, for measurement support in this work.

REFERENCES [1] F. H. Raab, P. Asbeck, S. Cripps, P. B. Kenington, Z. B. Popovic, N. Pothecary, J. F. Sevic, and N. O. Sokal, “Power amplifier and transmitters for RF and microwave,” IEEE Trans. Microw. Theory Tech., vol. 50, no. 3, pp. 814–826, Mar. 2002. [2] L. R. Kahn, “Single-sideband transmission by envelope elimination and restoration,” Proc. IRE, vol. 40, no. 7, pp. 803–806, Jul. 1952. [3] Y. Wang, “An improved Kahn transmitter architecture based on delta–sigma modulation,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2003, vol. 3, pp. 1327–1330. [4] M. Taromaru, N. Ando, T. Kodera, and K. Yano, “An EER transmitter architecture with burst-width envelope modulation based on trianglewave comparison PWM,” in Proc. IEEE Int. Symp. PIMRC, Sep. 2007, pp. 1–5. [5] S. C. Cripps, Advanced Techniques in RF Power Amplifier Design. Norwood, MA: Artech House, 2002. [6] F. H. Raab, B. E. Sigmon, R. G. Myers, and R. M. Jackson, “L-band transmitter using Kahn EER technique,” IEEE Trans. Microw. Theory Tech., vol. 46, no. 12, pp. 2220–2225, Dec. 1998. [7] J.-H. Chen, K. U-yen, and J. S. Kenney, “An envelope elimination and restoration power amplifier using a CMOS dynamic power supply circuit,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2004, vol. 3, pp. 1519–1522. [8] J.-H. Chen, P. Fedorenko, and J. S. Kenney, “A low voltage W-CDMA polar transmitter with digital envelope path gain compensation,” IEEE Microw. Wireless Compon. Lett., vol. 16, no. 7, pp. 428–431, Jul. 2006. [9] C.-T. Chen, C.-J Li, T.-S. Horng, J.-K. Jau, and J.-Y Li, “Design and linearization of class-E power amplifier for nonconstant envelope modulation,” IEEE Trans. Microw. Theory Tech., vol. 57, no. 4, pp. 956–967, Apr. 2009. [10] J. Choi, D. Kim, D. Kang, and B. Kim, “A polar transmitter with CMOS programmable hysteretic-controlled hybrid switching supply modulator for multistandard applications,” IEEE Trans. Microw. Theory Tech., vol. 57, no. 7, pp. 1675–1684, Jul. 2009. [11] Recommended Minimum Performance Standards for CDMA2000 Spread Spectrum Mobile Stations, Standard TIA/EIA/98-E, Feb. 2003. [12] “User equipment (UE) radio transmission and reception (FDD),” The 3rd Generation Partnership Project Tech. Specification Group, Valbonne, France, 3GPP TS 25.101, 2009. [13] H.-S. Yang, H.-L. Shih, J.-H. Chen, and Y.-J. E. Chen, “A pulse modulated polar transmitter for CDMA handsets,” in IEEE MTT-S Int. Microw. Symp. Dig., May 2010, pp. 808–811.

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[14] C. Berland, I. Hibon, J. F. Bercher, M. Villegas, D. Belot, D. Pache, and V. L. Goascoz, “A transmitter architecture for nonconstant envelope modulation,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 1, pp. 13–17, Jan. 2006. [15] J.-H. Chen, H.-S. Yang, and Y.-J. E. Chen, “A multi-level pulse modulated polar transmitter using digital pulse-width modulation,” IEEE Microw. Wireless Compon. Lett., vol. 20, no. 5, pp. 295–297, May 2010. [16] J. Staudinger, T. Quach, and R. Sherman, “Gate and drain power tracking methods enhance efficiency in reverse link CDMA amplifiers,” Appl. Microw. Wireless Mag., pp. 28–38, Mar. 2002. [17] J. Staudinger, B. Gilsdorf, D. Newman, G. Norris, G. Sadowniczak, R. Sherman, and T. Quach, “High efficiency CDMA power amplifier using dynamic envelope tracking technique,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2000, vol. 2, pp. 873–876. [18] J. Deng, P. S. Gudem, L. E. Larson, and P. M. Asbeck, “A high averageefficiency SiGe HBT power amplifier for WCDMA handset applications,” IEEE Trans. Microw. Theory Tech., vol. 52, no. 2, pp. 529–537, Feb. 2005. [19] B. Sahu and G. A. Rincón-Mora, “A high-efficiency, linear RF power amplifier with a dynamically adaptive buck-boost supply,” IEEE Trans. Microw. Theory Tech., vol. 52, no. 1, pp. 112–120, Jan. 2004. [20] B. Sahu and G. A. Rincón-Mora, “A high-efficiency WCDMA RF power amplifier with adaptive, dual-mode buck–boost supply and biascurrent control,” IEEE Microw. Wireless Compon. Lett., vol. 17, no. 3, pp. 238–240, Mar. 2007. [21] G. Hanington, P. Chen, P. M. Asbeck, and L. E. Larson, “High-efficiency power amplifier using dynamic power-supply voltage for CDMA applications,” IEEE Trans. Microw. Theory Tech., vol. 47, no. 8, pp. 1471–1476, Aug. 1999. [22] “ADG901/ADG902 wideband, 40 dB isolation at 1 GHz, CMOS 1.65 V to 2.75 V, SPST switches, data sheet,” Analog Devices Inc., Norwood, MA, 2005. [23] “ATF-501P8 high linearity enhancement mode pseudomorphic HEMT, data sheet,” Avago Technol., San Jose, CA, 2009. [24] “LTC3411 1.25A, 4 MHz, synchronous step-down DC/DC converter, data sheet,” Linear Technol. Corporation, Milpitas, CA, 2002. [25] J. Jeong, D. F. Kimball, M. Kwak, C. Hsia, P. Draxler, and P. M. Asbeck, “Wideband envelope tracking power amplifiers with reduced bandwidth power supply waveforms and adaptive digital predistortion techniques,” IEEE Trans. Microw. Theory Tech., vol. 57, no. 12, pp. 3307–3314, Dec. 2009. [26] F. Wang, A. H. Yang, D. F. Kimball, L. E. Larson, and P. M. Asbeck, “Design of wide-bandwidth envelope-tracking power amplifiers for OFDM applications,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 8, pp. 1244–1255, Aug. 2005. [27] I. Kim, Y. Woo, J. Kim, J. Moon, and B. Kim, “High-efficiency hybrid EER transmitter using optimized power amplifiers,” IEEE Trans. Microw. Theory Tech., vol. 56, no. 11, pp. 2582–2593, Nov. 2008. [28] P. M. Cabral, J. C. Pedro, J. A. Garcia, and L. Cabria, “A linearized polar transmitter for wireless applications,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2008, vol. 2, pp. 935–938. [29] F. Wang, D. F. Kimball, J. D. Popp, A. H. Yang, D. Y. Lie, P. M. Asbeck, and L. E. Larson, “An improved power-added efficiency 19-dBm hybrid envelope elimination and restoration power amplifier for 802.11g WLAN applications,” IEEE Trans. Microw. Theory Tech., vol. 54, no. 12, pp. 4086–4099, Dec. 2006.

Jau-Horng Chen (M’09) received the B.S. degree in electrical engineering from National Taiwan University, Taipei, Taiwan, in 2001, and the M.S. and Ph.D. degrees in electrical and computer engineering from the Georgia Institute of Technology, Atlanta, in 2002 and 2006, respectively. He was a Design Engineer for Freescale Semiconductor, Tempe, AZ, where he was involved in designing dc–dc converters and predistortion linearizers for cell phone PAs. In 2008, he joined National Taiwan University, where he is currently an Assistant Professor with the Department of Engineering Science and Ocean Engineering. His research interests include analog/RF integrated circuit (IC) design and high-efficiency PAs. He holds one U.S. patent with three pending.

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Hao-Shun Yang (S’09) received the B.S. degree in electronics engineering from Chang Gung University, Taoyuan, Taiwan, in 2001, the M.S. degree in electronics engineering from National Tsing Hua University, Hsinchu, Taiwan, in 2002, and is currently working toward the Ph.D. degree at the Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan. In 2002, he joined the Republic of China Army, where he held the rank of Second Lieutenant. In 2006, he joined Compal Communication, Taipei, Taiwan, as a Hardware Engineer, where he was involved in designing cellular phones. His research interests include analog and RF IC design.

Yi-Jan Emery Chen (S’97–M’01–SM’07) received the B.S. degree in electrical engineering from National Taiwan University, Taipei, Taiwan, in 1987, the M.S. degree in electrical and computer engineering from the University of California at Santa Barbara, in 1991, and the Ph.D. degree in electrical engineering from the Georgia Institute of Technology, Atlanta, in 2001. From 1992 to 1993, he was a Software Engineer with Siemens Telecommunication, where he was involved with synchronous optical network (SONET)

equipment development. From 1993 to 1996, he was with Tektronix, where he was responsible for electronic test and measurement solutions. From 2000 to 2002, he was with National Semiconductor, where he was involved with RF transceiver and RF PA design. In 2002, he joined the Georgia Institute of Technology, as a member of the research faculty. Since 2003, he has been with National Taiwan University, where he is currently an Associate Professor. He has authored or coauthored over 80 refereed journal and conference papers. His recent research focuses on the design of RF integrated circuits (RFICs), RF PAs, LCD/LED drivers, and power management ICs. Dr. Chen currently serves on the Technical Program Committees of the IEEE Microwave Theory and Techniques Society (IEEE MTT–S) International Microwave Symposium (IMS), and the IEEE Radio and Wireless Symposium (RWS). Since 2004, he has been on the IC Implementation Review Committee, National Chip Implementation Center, Hsinchu, Taiwan. He was the corecipient of the 2000 IEEE MTT-S IMS Best Paper Award and the corecipient of the 2008 University Team Award for Contribution to Industrial Economics of the Ministry of Economic Affairs.

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An Efficient Bilateral Dual-Grid-FDTD Approach Applied to On-Body Transmission Analysis and Specific Absorption Rate Computation Céline Miry, Renaud Loison, and Raphaël Gillard, Member, IEEE

Abstract—This paper presents a new simulation strategy based on the finite-difference time-domain (FDTD) method. This new approach aims at simulating efficiently a full-duplex link where both the transmitting and receiving antennas require a precise description, while their environment does not imply a particularly fine mesh. Typical application fields of the bilateral dual-grid-FDTD are the analysis of transmission between two on-body or implanted antennas. It can also be applied to the computation of specific absorption rate (SAR) in a precise location of the human body. The principle of this method consists in splitting the overall simulation into three FDTD simulations sequentially executed with an appropriate mesh. The radiator is first characterized using a fine mesh. All the elements of the problem are then represented using a coarse mesh. Finally, that element requiring a high resolution is finely described. This approach is applied to the analysis of a 2.4-GHz transmission between two on-body devices and to the computation of the SAR in the fetal brain of a pregnant woman at 900 MHz. The bilateral dual-grid-FDTD technique proves to be accurate compared to FDTD while being fast, stable, and simple to implement. Index Terms—Dosimetry, finite-difference time-domain (FDTD) method, on-body transmission.

I. INTRODUCTION

T

HE RECENT advances in the development of wireless miniaturized devices for body area network applications [1] make it essential to simulate these devices in the presence of the human body. Indeed the placement of such devices close to the human body might affect their performance. In addition, knowledge of on-body radio channel characteristics is necessary to ensure an efficient transmission link between body area network nodes. Finally, the specific absorption rate (SAR) is also a very important quantity that needs to be taken into consideration to avoid overexposure. The finite-difference time-domain (FDTD) method has been widely used for the simulation of electromagnetic problems involving the human body as the propagation channel since it allows a precise treatment of complex and heterogeneous structures [2]. However, a high spatial resolution is often required Manuscript received March 06, 2010; revised May 27, 2010; accepted June 27, 2010. Date of publication August 23, 2010; date of current version September 10, 2010. This work was supported by the Région Bretagne. The authors are with the National Institute of Applied Sciences (INSA), Electronics and Telecommunications Institute of Rennes (IETR), UMR 6164, Université Européenne de Bretagne, F-35708 Rennes, France (e-mail: [email protected]; [email protected]; [email protected]). Digital Object Identifier 10.1109/TMTT.2010.2058270

for the description of on-body devices, which usually present very small geometrical features. Such a resolution might also be necessary for the description of a specific part of a body where the SAR is to be determined. Therefore, considering the size of a human body and the uniform meshing scheme of the FDTD technique, high accuracy leads to large oversampled areas, considerably increasing the computation time and memory requirements. In order to overcome these issues, several techniques based on the FDTD method have been introduced. For instance, subgridding FDTD schemes have been applied to the analysis of medical implants [3] and to SAR computation [4]. This method consists of using different resolutions for the description of different areas in one unique computational volume. Although this method allows a reduction in simulation time and memory requirements, it presents some drawbacks such as instabilities [5] and reflections from the grid–subgrid interface [6]. Based on the same principle of using different meshes to describe different elements, the dual-grid FDTD (DG-FDTD) method [7] can overcome the above mentioned subgridding problems. It combines a fine FDTD simulation of the transmitting antenna with a coarse FDTD simulation of the whole problem. The two steps are sequentially run so that the interpolation process to obtain the field components in the coarse mesh is performed only once. Thus, instabilities are avoided and reflections are reduced. The DG-FDTD technique has been successfully applied to the study of various configurations where the performance of a transmitting antenna is affected by its environment [8]. However, as the mesh size is gradually increased when moving away from the radiator, it is no longer possible to study a full-duplex link where both the transmitting and receiving antennas require a fine grid. To overcome this limitation, here we propose to split a classical FDTD simulation of the problem into three FDTD simulations sequentially run with an appropriate mesh. This principle of adding a third step to the original DG-FDTD approach will be called the “bilateral DG-FDTD.” The third step is intended to accurately describe a receiving antenna or a certain part of the body. Hence, the bilateral DG-FDTD allows an efficient computation of on/in-body transmission or SAR. This paper is organized as follows. In Section II, the principle of the method is exposed and details on its implementation are given. In Section III, the proposed technique is validated using a simplified on-body transmission case between two planar inverted-F antennas operating at 2.4 GHz. The accuracy and performance of the new approach are demonstrated by comparison

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Fig. 1. Bilateral dual-grid-FDTD principle.

to classical FDTD and DG-FDTD simulations of the problem. Finally, in Section IV, the bilateral DG-FDTD technique is applied to the calculation of SAR in the fetal brain of a pregnant woman at 900 MHz using the whole-body model described in [9]. II. DESCRIPTION OF THE BILATERAL DG-FDTD METHOD A. Principle We first consider a classical problem of on-body transmission between two antennas with very small geometrical features [10], as illustrated in Fig. 1. It is important to correctly describe the two antennas for accurate characterization of the on-body radio channel. On-body devices often require a spatial resolution much finer than 1 mm. However, the description of the human body does not demand such accuracy and most of the numerical models are designed with a minimum voxel size of 2 2 2 mm [11]. As shown in Fig. 1, the bilateral DG-FDTD approach consists of splitting the simulation of such a problem into three different FDTD simulations, each sequentially run. The first step aims at accurately characterizing the transmitting antenna and recording its primary radiation by the use of a near-field surface placed around it. Thus the antenna is described using a fine mesh directly related to its geometrical features. This first FDTD volume may also include the nearby surroundings of the antenna, especially when the antenna lies directly on the body or is implanted within it. Indeed, in this case, the body strongly affects the antenna performance, and the first-order coupling effects should be taken into account using a fine mesh. The volume is terminated by uniaxial Gedney perfectly matched layers (PMLs) and if a part of the body is considered, it is immersed into the PMLs so as to simulate an infinite open problem. This first step starts at and ends at when all the electromagnetic energy is outside this volume. The second step corresponds to the coarse FDTD simulation of the whole problem in which both the antennas and human

body are represented. It aims at characterizing the on-body radio channel while taking into account all the coupling effects between the antennas and human body. The excitation of this volume is realized with an excitation surface based on the total-field/scattered-field decomposition principle [2], as explained in Section II-B. The applied incident field on the excitation surface is the one that has been recorded during and ends at the first step. This second step also starts at generally longer than to allow the propagation of the electromagnetic energy into the whole FDTD volume. The spatial resolution of the second step is chosen in order to correctly represent the human body, but it only provides a coarse description of the antennas. More specifically, it is not fine enough to compute precisely the received signal (recall that the near-field around the transmitting antenna has already been accounted for in the first step). As a result, a third and final step is required, which must be anticipated in the second step by defining a closed surface around the receiving antenna, to record the incoming field. The third step is to provide the precise interaction of the transmitted wave with the receiving antenna. The corresponding FDTD volume contains the receiving antenna described using a fine mesh related to its geometrical features. The excitation of the volume is realized by means of an excitation surface based on the total-field/scattered-field decomposition principle. The applied incident field on the excitation surface is the one that has been recorded during the second step. Although it has been recorded in the total field region in the second step, it is now considered as the incident field of this volume and the total-field/scattered-field decomposition principle is not changed. The FDTD volume is terminated by PMLs and if a part of the environment is represented, it is immersed into the PMLs so as to consider an infinite open problem. This last step , generally equal to , so that starts at and ends at the complete electromagnetic fields from the second step can be transmitted to the receiving antenna. To summarize, the bilateral DG-FDTD is intended to enable efficient analysis of transmission between two antennas located in a large and heterogeneous environment like the human body. The fact to add a third step to the DG-FDTD, which constitutes an extension of the original approach, permits to obtain much more accurate results, as will be shown below. Note that the receiving antenna can be replaced by a specific part of the body in the case of SAR calculations without any change to the principle of the method. B. Implementation The bilateral DG-FDTD method necessitates some modifications to the standard FDTD code. First, an interpolation process of the field components is realized between two successive steps. The total-field/scattered-field decomposition principle then needs to be implemented in the code. Both these functionalities are detailed below, as well as the post-processing for the coefficient. computation of the 1) Interpolation Process: Once the field components have been saved on the near-field surface in the first or second step, they have to be interpolated to spatially and temporally match the grid of the corresponding next step (second or third one).

MIRY et al.: EFFICIENT BILATERAL DUAL-GRID-FDTD APPROACH

Fig. 2. Fine-to-coarse grid interpolation. (a) (b) H component interpolation.

E

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component interpolation.

First, a fine-to-coarse grid interpolation is used between the first and second steps. As explained in [7] and illustrated in and are, respectively, obtained Fig. 2(a) and (b), and components using the considering the nearest following equation:

(1)

Fig. 3. Coarse-to-fine grid interpolation. (a) (b) H component interpolation.

E

component interpolation.

A coarse-to-fine grid interpolation is then applied between the second and third steps. Its principle is illustrated in Fig. 3(a) and (b). The fine field components are obtained considering the and components using nearest

where can be either an electric or magnetic field component, corresponds to the number of fine field components and and in a coarse cell. Thus, in Fig. 2(a) and (b), are obtained considering the nearest six and four components. The fine-to-coarse time interpolation consists of a simple linear interpolation using (2) (5)

with (3) where represents the integer part of , corresponds repto the instant when the field component is calculated, resents the fine time step, and (4)

where represents either an electric or magnetic field component. The coarse-to-fine time interpolation principle is based on a simple linear interpolation, as was done for the fine-to-coarse time interpolation. Note that several interpolation schemes have been tested like splines and cubic interpolations. However, these higher order interpolation schemes involve more complicated calculations and do not permit to improve the accuracy of the electric or

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magnetic components calculations. Thus, the linear interpolation presented here turns out to be the most well-suited scheme for the proposed approach. 2) Excitation Surface Principle: The interpolated components from first and second steps are used, respectively, for the excitation of the second and third FDTD volumes by means of the total-field/scattered-field decomposition principle detailed in [2] and in [7]. The general principle consists in modifying the FDTD equations of the field components tangential to the different surfaces of the excitation volume by adding a correction term related to the field saved during the previous step. The excitation of the second and third steps differs in one way: in the second step, the field is injected outside of the excitation surface, whereas in the third step, it is injected inside the surface. The general principle remains the same, but the total-field area and scattered-field area are switched with respect to the excitation surface. Thus, electric field components tangential to the excitation surface are corrected by the use of interior magnetic field components in the case of an outside excitation, whereas exterior magnetic field components are employed in the case of an inside excitation. Note that the surfaces are aligned with the electric field components. Once the three steps are completed, some post-processing is carried out to determine the transmission coefficient between transmitting and receiving antennas. -parameter 3) Transmission Coefficient Calculation: The is determined using

Fig. 4. Bilateral dual-grid-FDTD decomposition of the problem.

(6) where and correspond, respectively, to the voltage and current at the transmitting antenna terminal collected during the and first and second steps, with . The terms and represent, respectively, the voltage and current at the receiving antenna terminal collected during the last step. As the field injected during the third step comes from the second step (where the whole environment was considered), the effect of the environment on the received signal is directly taken into account during the last step. Thus, it is not and from the second step to and neccessary to add from the third step. represents the characteristic impedance at the antennas terminals. In Section III, the proposed technique is compared to the classical FDTD and DG-FDTD methods in order to validate its performance. III. VALIDATION USING ON-BODY TRANSMISSION CASE A. Description of the Problem The bilateral DG-FDTD approach is first validated using a simplified transmission between two on-body antennas at 2.4 GHz. The results are compared to those obtained with classical FDTD and DG-FDTD simulations. An FDTD simulation is used as the reference, as it has already been successfully applied to such problems [2]. In order to perform an FDTD simulation within a reasonable time, we consider a

= 35 = 25 mm, h = =5

Fig. 5. Planar inverted-F antenna description. L mm, l mm, W mm, d mm, d : mm, e mm.

3

= 10

=2

= 19 5

simple parallelepipedic homogeneous partial body model. The complete problem is described in Fig. 4. The receiving and transmitting antennas are identical planar inverted-F antennas taken from [12] and illustrated in Fig. 5. The distance between the antennas is 5 cm. They are placed on the human body model, which is made up of muscle tissue. Its constants, given in [13], and S/m at 2.4 GHz. The extremities of the are body model are extended within the PMLs so as to consider an infinite homogeneous medium in the - and -directions. The simplified body model shape does not require a particularly fine mesh; however, the geometrical features of the antennas imply an FDTD cell size of 0.5 mm . The entire problem is simulated using the three different approaches presented in Table I. The fine FDTD simulation is used as the reference. Its fine at 2.4 GHz) correctly despatial mesh (corresponding to scribes the antenna geometries. The structure is also simulated using the DG-FDTD and bilateral DG-FDTD. For the latter simulations, the first step corresponds to the fine simulation of the transmitting antenna. The nearby surroundings of the body are taken into account and extended within ten cells of PMLs. The second step corresponds to the coarse FDTD simulation of the whole structure (both the antennas and body). Note that the

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TABLE I DESCRIPTION OF THE DIFFERENT SIMULATIONS

transmitting antenna is switched off during this step and terminated with a matched load, as the incident power is already provided by the excitation surface [7]. The mesh used to describe this second FDTD volume is times coarser than the fine mesh. represents the ratio between fine and coarse meshes and it varies from 2 to 10. Thus, several mesh ratios are tested in order to analyze the change of transmission coefficient versus mesh size of the second step. In the case of the bilateral DG-FDTD, a third step is performed, which corresponds to the fine FDTD simulation of the receiving antenna with the nearby surroundings of the body extended within ten cells of PMLs. B. Numerical Results The methods are compared in terms of the coefficient. between 2–3 GHz is The variation of the magnitude of shown in Fig. 6(a) for the DG-FDTD, and in Fig. 6(b) for the bilateral DG-FDTD. It is seen that whatever the value of the ratio between fine and coarse meshes, the results obtained with the bilateral DG-FDTD are close to those of the reference case. results obtained with the DG-FDTD method are However, shifted in frequency. This disagreement increases with . The accuracy of the two techniques is evaluated by calculating the mean absolute error (MAE) over the [2–3] GHz frequency band, as defined by

(7) where subscript denotes the reference value, GHz, and . The MAE versus the ratio is given in Fig. 7. The error is generally seen to increase with . This error is mainly due to the approximate representation of the different elements in the second step. The interpolation process applied between each step is also a source of approximations of the field components and may cause some errors. However, the third step of bilateral DG-FDTD significantly limits this error. Indeed, even for a ratio of 10 between fine and coarse meshes, the MAE does not exceed 1.5 dB. Note that a mesh ten times coarser than the fine mesh corresponds to an at 2.4 GHz and does not permit a FDTD cell size of proper representation of the antennas. To conclude, this new method proves its accuracy even when a very coarse mesh is used in the second step. However, its ad-

Fig. 6. jS j parameter versus the ratio N between fine and coarse meshes. (a) Dual-grid-FDTD simulations. (b) Bilateral dual-grid-FDTD simulations.

vantages in terms of computational time have not been demonstrated in this section, as we only considered a small part of the body model in the second step. Indeed, the method becomes more attractive when a large second step volume is considered, as shown in Section IV. IV. APPLICATION TO A DOSIMETRY PROBLEM A. Description of the Problem In Section III, the bilateral DG-FDTD method was validated on a transmission case between two on-body antennas. In

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Fig. 7. MAE for the classical and bilateral dual-grid-FDTD (DG-FDTD) between fine and coarse meshes. versus the ratio

N

this section, we propose to apply the new approach to the calculation of the SAR in a fetal brain at 900 MHz using a numerical heterogeneous model of a 26-gestational-week pregnant Japanese woman [9]. The problem, taken from [14], is presented in Fig. 8(b). The radiator is a 900-MHz half-wave dipole antenna. It is placed 40 mm from the mother’s body and centered on the fetal brain. The radiated power is normalized to 1 W. The original numerical model is described using a 2 2 2 mm cell size. However, considering the size of the model, such an accuracy involves large time resources. Besides, this accuracy is not necessary in the whole FDTD volume as the SAR is only determined in the fetal brain. Indeed, only the radiating element and the fetal brain require such a fine description. A mesh twice as coarse is sufficient to correctly evaluate the propagation of the electromagnetic field inside the human tissues. Thus, the bilateral DG-FDTD seems to be well suited for the simulation of this problem. The four simulation approaches applied to this problem are presented in Table II. The fine FDTD simulation constitutes the reference case. A fine spatial mesh is used to describe the complete structure. This simulation yields results similar to those found in [14]. A coarse FDTD simulation of the entire problem is also performed using a spatial mesh twice as coarse. Finally, the DG-FDTD and bilateral DG-FDTD are used to simulate the problem. For the latter two methods, the first step corresponds to the fine FDTD simulation of the antenna without its environment [see Fig. 8(a)]. The FDTD volume is extended within ten cells of the PMLs in order to consider an infinite open problem. The near-field surface placed around the antenna stores the accurate radiation of the isolated antenna. The second step corresponds to the coarse FDTD simulation of the whole problem [see Fig. 8(b)]. The FDTD cell size is twice as coarse in the three spatial directions than in the previous case. The electric properties of the coarse body model are obtained by averaging the electric properties of the fine original model. The antenna radiation stored in the previous step is used as the excitation of the volume after it has been interpolated to match the coarse mesh. It is injected outside of the excitation surface using the total-field/scattered-field decomposition principle. A new near-field surface is placed around the fetal brain to store the radiation coming from the antenna. The third step of the bilateral DG-FDTD corresponds to the fine FDTD simulation of the fetal brain [see

Fig. 8. Bilateral dual-grid-FDTD description of a dosimetry problem. (a) First step. (b) Second step. (c) Third step.

Fig. 8(c)]. The closest part of the body surrounding the fetal brain is also taken into account and it is extended within the PMLs. The part of the body under consideration corresponds to the original fine body model. The field stored in the previous step is interpolated to match the fine mesh and is injected inside the excitation surface to illuminate the fetal brain. B. Numerical Results The accuracy of the bilateral DG-FDTD is compared to the FDTD and DG-FDTD methods by calculating the averaged SAR at 900 MHz in the fetal brain. The SAR is determined using the following equation: W kg

(8)

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TABLE II DESCRIPTION OF THE DIFFERENT SIMULATIONS

TABLE III NUMERICAL RESULTS FOR SAR CALCULATION

where is the conductivity of the tissue (S/m), is the mass density of the tissue kg/m , and is the electric field distribution (V/m) inside the tissue. Note that at the end of the third step, the electric field components are interpolated at the center of each FDTD cell in the fetal brain. The constants of the woman and fetus model studied at 900 MHz are the same as those used in [14]. The characteristics of the fetal brain at 900 MHz are S/m and kg/m . Table III presents the different simulations results. The methods are compared using their relative error given by (9) represents the value obtained with the fine FDTD where method. Since the radiating element used here is a simple halfwave dipole, the coarse mesh (which corresponds to a ratio of at 900 MHz) is accurate enough to correctly describe the radiation of the dipole. Thus, the first step of the DG-FDTD does not improve the results compared to the coarse FDTD. However, the third step of the bilateral DG-FDTD allows a reduction of the relative error to 12% and gives results close to the reference FDTD. It also provides a computational time gain of 7.6 compared to the fine FDTD simulation of the complete problem. Thus, the bilateral DG-FDTD method proves to be well suited to the analysis of numerical dosimetry problems. Although the third step implies a slight increase in computational time compared to the DG-FDTD, it considerably improves the accuracy of the SAR computation. Besides, it gives a good order of magnitude on the SAR value inside a particular part of the body. As dosimetry problems are subject specific, a good order of magnitude on the SAR value considering a particular body model is usually informative enough. V. CONCLUSION An efficient numerical technique to evaluate the transmission between devices located in a human body environment has been proposed. It has been validated through comparisons with the

FDTD technique for the analysis of the 2.4-GHz transmission between two planar inverted-F antennas located on a simplified human body model. Furthermore, the approach has been successfully applied to the computation of SAR at 900 MHz inside the fetal brain of a pregnant woman. For this example, a computational time gain of 7.5 has been obtained for a relative error of around 10%. To conclude, it appears that adding a third fine step to the coDG-FDTD method improves the accuracy of both the efficient and SAR calculations. At the same time, the method remains competitive in terms of computational time gain compared to FDTD. In addition, the proposed technique is stable since the interpolation process is performed only once at the end of each step. Finally, this principle is simple to implement as it is based on the use of near-field surfaces and excitation surfaces. ACKNOWLEDGMENT The authors would like to thank Prof. L. Roy, Carleton University, Ottawa, ON, Canada, for very beneficial advice. The authors would also like to thank the National Institute of Information and Communications Technology (NICT), Japan, for having provided the whole database of pregnant Japanese woman model. REFERENCES [1] P. S. Hall and Y. Hao, Antennas and Propagation for Body-Centric Wireless Communications. Norwood, MA: Artech House, 2006. [2] A. Taflove and S. C. Hagness, Computational Electrodynamics: The Finite-Difference Time-Domain Method, Third ed. Norwood, MA: Artech House, 2005. [3] A. Johansson, “Wave-propagation from medical implants-influence of body shape on radiation pattern,” in Proc. 2nd Joint Eng. Med. Biol. 24th Annu. Conf./Annu. Fall Biomed. Eng. Soc. Conf. Meeting, Oct. 2002, pp. 1409–1410. [4] J. Wiart, R. Mittra, S. Chaillou, and Z. Altman, “The analysis of human head interaction with a hand-held mobile using the non-uniform FDTD,” in IEEE AP-S Antennas Propag. Wireless Commun. Conf., Nov. 1998, pp. 77–80. [5] J. P. Bérenger, “A Huygens subgridding for the FDTD method,” IEEE Trans. Antennas Propag., vol. 54, no. 12, pp. 3797–3804, Dec. 2006.

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[6] R. A. Chilton and R. Lee, “Explicit 3D FDTD subgridding with provable stability and conservative properties,” in IEEE AP-S Int. Antennas Propag. Symp., Honolulu, HI, Jun. 2007, pp. 3069–3072. [7] R. Pascaud, R. Gillard, R. Loison, J. Wiart, and M. F. Wong, “Dual grid finite-difference time-domain scheme for the fast simulation of surrounded antennas,” IET Microw. Antennas Propag., vol. 1, no. 3, pp. 700–706, Jun. 2007. [8] C. Miry, R. Gillard, and R. Loison, “An application of the multi-level DG-FDTD to the analysis of the transmission between a dipole in freespace and an implanted antenna in a simplified body model with various positions,” in 3rd Eur. Antennas Propag. Conf., Mar. 2009, pp. 67–70. [9] T. Nagaoka, T. Togashi, K. Saito, M. Takahashi, K. Ito, and S. Watanabe, “An anatomical realistic whole-body pregnant-woman model and specific absorption rates for pregnant-woman exposure to electromagnetic plane waves from 10 MHz to 2 GHz,” Phys. Med. Biol., no. 52, pp. 6731–6745, 2007. [10] Y. Rahmat-Samii and J. Kim, Implanted Antennas in Medical Wireless Communications. San Rafael, CA: Morgan and Claypool, 2006. [11] K. Ito, “Numerical and experimental human body phantoms,” in IET Antennas Propag. Body-Centric Wireless Commun. Seminar, Apr. 2007, pp. 6–12. [12] T. Alves, R. Augustine, M. Grzeskowiak, B. Poussot, D. Delcroix, S. Protat, J.-M. Laheurte, and P. Queffelec, “BAN antenna design using ferrite polymer composite,” in 3rd Eur. Antennas Propag. Conf., Mar. 2009, pp. 965–968. [13] “An Internet resource for the calculation of the dielectric properties of body tissues,” Italian Nat. Res. Council, Florence, Italy, 1997–2000. [Online]. Available: http://niremf.ifac.cnr.it/tissprop/ [14] T. Togashi, T. Nagaoka, S. Kikuchi, K. Saito, S. Watanabe, M. Takahashi, and K. Ito, “FDTD calculations of specific absorption rate in fetus caused by electromagnetic waves from mobile radio terminal using pregnant woman model,” IEEE Trans. Microw. Theory Tech., vol. 56, no. 2, pp. 554–559, Feb. 2008. Céline Miry was born on October 8, 1984. She received the Engineer Diploma (Master level) degree in electronic and communication systems from the National Institute of Applied Sciences (INSA), Rennes, France, in 2007, and is currently working toward the Ph.D. degree in electronics at the Electronics and Telecommunications Institute of Rennes (IETR), Rennes, France. Her research interests are computational electromagnetics for wireless body area networks (WBANs).

Renaud Loison was bornin Saint-Brieuc, France, on January 16, 1974. He received the Diplôme d’Ingénieur and Ph.D. degrees from the National Institute of Applied Sciences (INSA), Rennes, France, in 1996 and 2000, respectively. In 2000, he joined the Institute of Electronics and Telecommunications of Rennes (IETR), Rennes, France, as an Associate Professor. Since 2009, he has been a Professor with the Antenna and Microwave Group, IETR. His research interests concern reflectarrays and numerical methods applied to the computer-aided design (CAD) and optimization of microwave circuits and antennas.

Raphaël Gillard (M’04) was born in July 1966. He received the Ph.D. degree in electronics from the National Institute of Applied Sciences (INSA), Rennes, France, in 1992. He initially worked as a Research Engineer with the IPSIS Company, Cesson-Sévigné, France, where he developed a commercial method of moments (MoM) code for the simulation of microwave circuits and antennas. In 19923, he joined the National Institute of Applied Sciences (INSA), Rennes, France, as an Assistant Professor. Since 2001, he has been a Full Professor with the Antenna and Microwave Group, Electronics and Telecommunications Institute of Rennes (IETR), Rennes, France,where he was in charge of electromagnetic (EM) modeling and optimization activity. Since 2006, he has been leading the Antenna and Microwave Group. He has coauthored 130 conference papers and 44 journal papers. He has also contributed to a book about active antenna modules. He holds six patents. He has been involved in numerous research projects with industries (Thales Alenia Space, Orange Laboratories, Thales Airborne Systems, Nortel Communications, Thomson) and research centers (French and European Space Agencies, CNES, and ESA). His current main research interests are computational electromagnetics and reflectarrays. Prof. Gillard was a member of both the Executive and Governing Boards of the European Antenna Centre of Excellence (ACE) from 2004 to 2008. He was co-leader of its antenna software activity (in charge of the software benchmarking work package). He is member of several scientific committees and review boards (EuCAP, EuMC, etc.). He is also chairman of the Antenna and Propagation Sub-Committee, French National Microwave Conference (JNM) and co-chairman of the French URSI-B section.

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Generalized Miniaturization Method for Coupled-Line Bandpass Filters by Reactive Loading Seungku Lee and Yongshik Lee, Member, IEEE

Abstract—This paper presents a generalized miniaturization method for coupled-line bandpass filters by reactive loading, including the series-inductive loading method that is proposed in this work. It is shown that bandwidth reduction seen in the previous miniaturization method of shunt-capacitive loading is a special case. In fact, one can choose a coupled-line filter to be miniaturized with its bandwidth reduced, expanded, or maintained after miniaturization. The ratio of the bandwidths before and after miniaturization plays an important role in determining the even-/odd-mode impedance, as well as the reactance levels after miniaturization. Therefore, the freedom in choosing the bandwidth ratio provides a great flexibility in miniaturizing coupled-line filters since one can choose an appropriate bandwidth ratio to maintain the impedance and reactance at practical levels after miniaturization. The proposed generalized miniaturization method enables filter designs focused on size reduction, improved stopband response, low-cost fabrication, or a combination of these, which are verified by experimental results. Index Terms—Coupled line, coupled-line bandpass filter, filter bandwidth, miniaturization, miniaturized filter, reactive loading, series inductor, shunt capacitor.

I. INTRODUCTION

M

INIATURIZATION has been a key issue for microwave components [1]–[4]. For bandpass filters, various methods have been reported, especially for miniaturization of coupled-line filters, one of the most popular methods to construct bandpass filters [5]–[9]. Among them, the method in [7] and [8] that rely on loading grounded coupled lines with shunt capacitors is considered to be the most attractive method due to its simplicity. However, the method is reported to lead to reduced bandwidth after miniaturization. When all coupled-line sections are miniaturized to the same electrical length, the reduced bandwidth can be compensated by the method in [8]. The analysis using image impedance and propagation constants for the same structure, however, enables to miniaturize a filter with the bandwidth intact [9]. Therefore, the bandwidth reduction in Manuscript received March 04, 2010; revised May 19, 2010 and May 31, 2010; accepted June 19, 2010. Date of publication August 05, 2010; date of current version September 10, 2010. This work was supported by the Low Observable Technology Research Center, Defense Acquisition Program Administration, by the Agency for Defense Development of Korea, and by the Korea Communications Commission (KCC) under the CPRC Program supervised by the Institute for Information Technology Advancement (IITA) (IITA-2009-C10910901-0007). The authors are with the Department of Electrical and Electronic Engineering, Yonsei University, Seoul 120-749, Korea (e-mail: [email protected]; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2010.2058281

Fig. 1. Schematics of (b) Open-ended.

=4

coupled lines with two ports. (a) Grounded.

[8] is not due to miniaturization by reactive loading, but rather a special phenomenon. This paper presents a generalized miniaturization method for coupled-line bandpass filters by reactive loading. The proposed series-inductive loading serves as an alternative for the previous capacitive loading. Most of all, the generalized miniaturization method of reactive loading allows one to miniaturize a coupledline filter with its bandwidth reduced, expanded, or maintained. The bandwidth ratio before and after miniaturization plays an important role in determining the even-/odd-mode impedance, as well as the reactance levels after miniaturization. Therefore, the freedom in choosing the bandwidth ratio provides great design flexibility since one can control the even-/odd-mode impedance of coupled lines and the reactance to be at practical levels after miniaturization. Moreover, the generalized miniaturization method does not restrict each coupled-line section to be of the same electrical length. Each section can be miniaturized to a different electrical length. This provides even greater design flexibility and improved stopband performance in terms of suppressing the spurious response. In Section II, a new miniaturization method of series-inductive loading is presented. The method completely eliminates grounding, therefore minimizes parasitic effects and provides low-cost solution. In Section III, the relationship between the bandwidths of a filter before and after miniaturization by reactive loading is analyzed. The effects of the bandwidth ratio on the design parameters of miniaturized filters are discussed. In Section IV, complete sets of design equations are provided for the two miniaturization methods of reactive loading. In Section V, experimental results are provided that show the design flexibility that the generalized miniaturization method provides. Section VI concludes this paper. II. VIA-HOLE-FREE MINIATURIZED FILTERS Fig. 1 shows the schematics of two types of coupled lines, both of which can be used to construct conventional coupled-line bandpass filters. Using duality, i.e., by replacing the impedance quantities with the admittance quantities, the design equations for the filters based on grounded coupled lines can be

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Fig. 2. Schematics of reduced-length ( < 90 ) coupled lines. (a) Shuntcapacitive loading for grounded coupled lines (admittance type) [8]. (b) Seriesinductive loading for open-ended coupled lines (impedance type) proposed in this work. Fig. 3. Schematics of conventional coupled line. (a) =4 grounded coupled line. (b) Equivalent circuit.

derived from those based on the more popular open-ended coupled lines, and vice versa [10]. For (1a) (1b) the -parameters of the two coupled lines in Fig. 1 will be of the , where the same magnitude, but opposite phase, i.e., superscripts and denote grounded and open-ended, respecis the system impedance. In this case, the -patively. rameters of the two coupled lines have the following relationship: (2a) (2b) Fig. 2 shows the schematics of two types of reduced-length coupled lines . The method in Fig. 2(a) utilizes shuntcapacitive loading for miniaturization of a coupled line with two ports grounded [8]. In [11], the idle port(s) of a coupled line is loaded with series inductors for equalization of even-/odd-mode phase velocities. In this work, the input and the output ports of an open-ended coupled line is loaded with series inductors for size reduction. Although a transmission line section can be miniaturized by either reactive loading methods [12] or a combination of them, a coupled-line section can be miniaturized by one method only depending on the termination condition. The conditions for the miniaturization method in Fig. 2(b) can be de-paramerived through the relationship of duality. The ters for the structure in Fig. 2(a) is (3) where the superscript denotes capacitive loading. , , , and are given in (2a) and . When the two coupled-line sections in Fig. 2 have the re-parameters for the structure in lationship in (1), the Fig. 2(b) is

(4)

where the superscript denotes inductive loading and . With the conditions in (1) and or , the -parameters of the two structures in Fig. 2 now have the relationship in (2). This completes the mathematical formulation of the duality relationship between the two dual structures in Fig. 2. Using this, the design equations for the miniaturization method in Fig. 2(b) can be derived from those in [8] for the method in Fig. 2(a). The proposed method of series-inductive loading in Fig. 2(b) can serve as an alternative for the method of shunt-capacitive loading in Fig. 2(a) for miniaturization of coupled-line filters. For the same filter specification, in general, the even-/odd-mode impedance of the coupled-line section are lower for the series-inductive loading method than the shunt-capacitive loading method. Therefore, when only the coupled-line sections are considered, the method is more suitable for thinner substrates with higher permittivity. The complete elimination of via-holes not only provides cost-effective fabrication, but also minimizes parasitic effects. The via-holes required for the shunt-capacitive loading method generally provide parasitic effects that may be problematic, especially at high frequencies. In addition, accurate fabrication processes for via-holes may not be available depending on the substrate. Thus, the series-inductive loading method is far more attractive, especially at high frequencies. Simulation and experimental results for the proposed miniaturization method of series inductive loading will be presented in Sections IV and V.

III. GENERALIZED MINIATURIZATION METHOD This section presents a generalized miniaturization method by reactively loading parallel coupled lines. The analysis is based on -inverters and shunt resonators, focusing on the method of shunt-capacitive loading method in Fig. 2(a). Similar analysis based on -inverters and series resonators can be applied to the method in Fig. 2(b). couShown in Fig. 3 are the schematics of a conventional pled line and its equivalent circuit that consists of a -inverter and two shunt resonators sections. The subscript denotes conventional. In a very similar way, the miniaturized coupled line in Fig. 4(a) can be decomposed into a -inverter and two shunt resonators sections, as shown in Fig. 4(b), where the subscript denotes miniaturized.

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Fig. 5. Block diagram of general bandpass filters [5].

Fig. 4. Schematics of miniaturized coupled line. (a) Grounded coupled line loaded with shunt capacitors. (b) Equivalent circuit.

and the susceptance slope parameters of Fig. 5 can be expressed with those of coupled-line sections as (10)

It can be shown that the -inverter values and the impedance of the stubs of the equivalent circuits in Figs. 3(b) and 4(b) are as follows:

. By applying (10) to the general filter dewhere sign equations in [10], the following relationships are obtained for the -inverters:

(5a) (11a) (5b) (6a) (6b)

(11b) (11c)

When a filter is developed by cascading these coupled lines, the susceptance of each resonator must be zero at the center frequency so that the resonators resonate

(12a)

(7a)

(12b)

(7b) (12c) where denotes the th coupled-line section for an th-order filter. Since the electrical length of each coupled-line section in a conventional filter is 90 at the center frequency, resonance is always guaranteed. For the resonator in the miniaturized coupled-line section to resonate, the following condition must be satisfied at the center frequency:

. and are the fractional bandwidth where (FBW) and the low-pass prototype values, respectively. The most general relationship between the conventional and the miniaturized filter is (13a) (13b)

(8) where . From (7) and (8), the susceptance slope parameter th section is

of the (9a) (9b)

where . Now that the equivalent circuits in Figs. 3(b) and 4(b) are fully characterized, the conventional filter synthesis method based on the block diagram in Fig. 5 [10] can be applied directly to construct a bandpass filter. The th -inverter in Fig. 5 corresponds to the -inverter of the th coupled-line section, whereas the th resonator in Fig. 5 is the combination of the resonators of the th and th coupled-line sections. Therefore, the susceptance

where . and are constants, which are the ratios of the -inverter values and the susceptance slope parameters, respectively, of the th section before and after miniaturization. The mathematical formulation can be simplified greatly by allowing the -inverter values to be maintained , while the ratios of the slope parameters of all , i.e., sections are to be the same (14a) (14b) In this case, from (5) and (9), the following relationships are required: (15a)

(15b)

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Also, by applying (14) to (11) and (12), it can be shown that the following relationship can be obtained for the bandwidths before and after miniaturization without changing the prototype values : (16) Equation (16) indicates that is not only the ratio of the susceptance slope parameters, but also the ratio of the bandwidths coubefore and after miniaturization. When a conventional pled-line filter is miniaturized under the condition in (14), the bandwidths of the two filters will have the relationship in (16). arbiOne can miniaturize a bandpass filter by choosing trarily. In fact, not only , but also or even is possible. The change in the bandwidth after miniaturization , the bandcan be compensated easily. For instance, for width of the miniaturized filter will be 1.2 times larger than the bandwidth of its conventional counterpart. In this case, for the bandwidth of the miniaturized filter to have an FBW of, for instance, 10%, the conventional filter must be designed to have an . FBW of The bandwidth reduction in [8] is a very special case under and . It the conditions can be easily shown that by inserting these conditions into (15b), the following is obtained:

Fig. 6. Circuit simulation results for third-order Chebyshev filters with 0.05-dB passband ripple level and 5% FBW. Each coupled line is miniaturized to 20 , 85 , 15 , and 25 .

(17) which agrees perfectly with the bandwidth reduction ratio in [8]. Therefore, bandwidth reduction in [8] is not due to miniaturization, but is rather due to choosing a specific to be smaller than 1 . This also applies to filters that are based on reduced-length coupled lines, such as those in also provides the same design parameters that the [13]. analysis based on image impedance and propagation constants provides [9]. Along with the degree of miniaturization , plays an important role in determining the even-/odd-mode impedance and the reactance of each coupled-line section after miniaturization. This will be seen in the complete sets of design equations in Section IV. The freedom in provides great design flexibility since a filter can be miniaturized with practical impedance and reactance levels at the cost of change in the bandwidth, which can be compensated easily. The method in [8] is also valid only for miniaturized filters with coupled lines of uniform electrical lengths. When each coupled-line section is reduced to a different electrical length, the method is no longer valid. On the other hand, the proposed method provides accurate design parameters even in this case, as far as remains the same for each section. Fig. 6 compares the ideal circuit simulation results of a conventional third-order Chebyshev filter with those of filters miniaturized by shunt-capacitive loading when the electrical lengths of coupled-line sections are 20 , 85 , 15 , and 25 . As can be seen, the proposed method provides far more accurate results than the method in coupled-line [8], and the agreement with the conventional filters is nearly perfect.

Fig. 7. Schematics of admittance-type bandpass filters. (a) Conventional. (b) Miniaturized [8].

Designing each coupled-line section to have a different electrical length provides more design flexibility in determining the reactance levels. Moreover, this technique can be utilized for suppression of spurious response in the stopband. This is due to the different spurious resonant frequency of each coupled-line section, when each section is of different electrical length [14], [15]. IV. COMPLETE SETS OF DESIGN EQUATIONS The two reduced-length coupled lines in Fig. 2 can be cascaded to develop miniaturized bandpass filters. Fig. 7 shows the schematics of admittance-type conventional and miniaturized filters, and Fig. 8 shows those of impedance-type conventional and miniaturized filters. The miniaturization procedure is as follows. First, a prototype filter is designed with a bandwidth of in (16) for the target bandwidth of after miniaturization and the predetermined bandwidth ratio . The design parameters of and for admittance-type filters a conventional filter ( and for impedance-type filters) are then calcuor lated using the well-known method [16], [17]. Based on these design parameters of the conventional filter and the degree of miniaturization for each section, the design parameters for the miniaturized filter can be obtained.

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Fig. 8. Schematics of impedance-type bandpass filters. (a) Conventional. (b) Miniaturized.

The complete design equation set for an th-order admittance-type miniaturized filters can be derived from (8) and (15), and are as follows:

(18a)

(18b) (19a)

(19b) (19c) In a similar way, the complete design equation set for an th-order impedance-type miniaturized filters can be derived

(20a)

(20b) (21a)

(21b) (21c) Fig. 9 shows an example of the effect of on the design parameters. This figure shows the geometric mean of the even-/

Fig. 9. Design parameters with respect to R for a third-order Chebyshev filter with 0.1-dB passband ripple level and 10% FBW at 3 GHz. (a) Geometric mean of even-/odd-mode impedance. (b) Reactance.

odd-mode impedance and the lumped-element values of each coupled-line section of a miniaturized filter with respect to . Although shown only for a Chebyshev filter with 0.1-dB passband ripple level and 10% FBW at 3 GHz, a similar tendency is observed for different filter specifications. For instance, as the degree of miniaturization increases (smaller ), the impedance of each coupled-line section increases for capacitively loaded filters. The width of the coupled line may then be impractically [see narrow. This can be overcome by choosing a smaller Fig. 9(a)] at the cost of increased capacitance [see Fig. 9(b)]. Fig. 10(a) shows the ideal circuit simulation results for the conventional and the miniaturized filters for various . Results for both the shunt-capacitive and series-inductive loading methods are shown, which agree perfectly with each other. For simplicity, the length of all coupled-line section is chosen as and accompany bandwidth reduction and 45 . maintains the bandexpansion, respectively, whereas width before and after miniaturization. is the special case in [8]. As can be seen, miniaturized filters have nearly the same performance as the conventional filter, regardless of the miniaturization method and/or . This validates the proposed method mathematically. The first spurious response of the miniaturized filters occurs when the resonators in Fig. 4(b) resonate, or at the frequency at which (8) is satisfied. For the filters in Fig. 10(a), this occurs around 12.9 GHz regardless of

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filters are designed to show the design flexibility the proposed method offers. Table I summarizes the design parameters of all the fabricated filters, as well as the measured figures of merit: , FBW, minimum passband insertion loss center frequency (IL), and the lowest frequency at which the specified rejection level is obtained in the upper stopband . Surface mount device (SMD) inductors are used for Filter A, whereas the reactive elements are realized in distributed forms in Filters B, C, D, and E. Although lumped elements generally provide better spurious response in the stopband, the tolerance, parasitic components, and low quality factor of practical lumped elements may be problematic, especially at high frequencies. Moreover, as will be seen, the proposed miniaturization method has a unique characteristic that when the reactive elements are realized in distributed forms, they can be bent to result in a more compact form. Finally, a method will be demonstrated to obtain superior stopband response even in purely distributed forms. A. Reactive Loading by Lumped Elements

Fig. 10. Ideal circuit simulation results for conventional and miniaturized thirdorder Chebyshev filters with 0.1-dB passband ripple level and 10% FBW at 3 GHz with various R: admittance-type (bold line) and impedance-type (thin line). All coupled-line sections of miniaturized filters are 45 long. (a) S -parameters in passband. (b) S in wideband.

the miniaturization method and/or , as seen in the wideband response in Fig. 10(b). From the performance aspect, the method is less practical when is too low. This is because the validity of the design parameters for the conventional coupled-line filter deteriorates dramatically due to the extremely wide bandwidth. On the other hand, when is too high, (18b) or (20b) may provide negative is the admittance or impedance. In general, practical range. Although the proposed miniaturization method based on -inverters and slope parameters guarantees very accurate results for narrowband designs [10], for wideband designs, the performance may deviate somewhat from the specification. Also, similar to the conventional filters, very wideband designs require coupled lines with extremely tight coupling levels. This may set a practical limitation of the proposed method since such lines are difficult to fabricate. V. EXPERIMENTAL RESULTS The generalized miniaturization method for coupled-line filters enables filter designs to be focused on various aspects: miniaturization, via-hole-free structure for minimum parasitic effects and low-cost fabrication, improved stopband response, or a combination of these. For experimental verification, various

The first demonstration of the proposed generalized miniaturization method is for a filter loaded with lumped elements. As the design equations indicate, the reactance levels are different for each section when all the coupled-line sections are of the same electrical length. From the manufacturing aspect, this may lead to increased cost. However, the proposed miniaturization method allows each coupled-line section to be miniaturized to a different electrical length so that all reactance are identical. This technique is especially effective since lumped element values, in general, are discrete. Fig. 11(a) shows a filter miniaturized by series-inductive loading. The filter is a third-order Chebyshev-type with 0.1-dB passband ripple level and 10% bandwidth at 0.9 GHz. For for and for with , the filter can be miniaturized with eight identical 6.8-nH inductors. The filter is fabricated in an RF-35 substrate from Taconic with a relative permittivity of 3.5 and a thickness of 0.76 mm. 2012-sized SMD-type inductors are used. For comparison, a conventional open-ended coupled-line filter is also fabricated in the same substrate, as shown in the same figure. Layout optimization is achieved with a full-wave simulator, the High Frequency Structure Simulator (HFSS) [18], for both filters. The filters are measured in the 0.4–9-GHz range with an MS4624D vector network analyzer (VNA) from Anritsu. Fig. 11(b) and (c) shows the measured and full-wave simulated -parameters and group delay. The relatively high passband IL of the miniaturized filter is mostly due to the low of the soldered lumped inductors. The measured passband performance agrees very well with the filter specification while achieving 36% size reduction. Moreover, the spurious response is far more desirable, as seen in Fig. 11(c). B. Reactive Loading by Distributed Elements Fig. 12 shows various miniaturized third-order Chebyshevtype filters with 0.1-dB passband ripple level and 10% bandwidth at 2 GHz. The filters are fabricated in the same substrate

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TABLE I DEMONSTRATED THIRD-ORDER CHEBYSHEV FILTERS WITH 0.1-dB PASSBAND RIPPLE LEVEL

2

Fig. 12. Photograph of fabricated filters. (a) Conventional filter (10 cm 2.5 cm). (b) Filter B (4.5 cm 2.5 cm). (c) Filter C (3.5 cm 2.5 cm). (d) Filter D (3.5 cm 2.5 cm). (e) Filter E (4.5 cm 2.5 cm).

2

Fig. 11. Photograph and measured (bold line) and full-wave simulated (thin line) results for Filter A and its conventional counterpart. (a) Photograph of fabricated filters: conventional (22 cm 2.5 cm) and Filter A (14 cm 2.5 cm). (b) S -parameters and group delay in passband. (c) Wideband S .

2

2

but with a 0.5-mm thickness. Series inductors in Filter C are implemented by short sections of a high-impedance (107 ) transmission line. Shunt capacitors are implemented by short sections of a low-impedance (20 in filters B and D and 15

2

2

2

in Filter E) transmission line. The distributed inductors and capacitors facilitate to modify the filter structure to a hairpin type, to result in a more compact form. In this case, the distributed reactance sections must be designed with minimum coupling between the adjacent coupled-line sections and excitation of higher order modes at the junction discontinuities. Finally, the layout is optimized by the full-wave simulator HFSS [18] to minimize any parasitic effects. Although the proposed filters look similar, they are completely different from the hairpin filters in [19]. Instead of bending the coupled-line sections as for hairpin filters, the distributed inductors or capacitors are bent for the proposed filters. Most of all, the hairpin filters require calculation of coupling coefficients through full-wave simulations, whereas the proposed filters can be designed simply by the closed-form design equations in Section IV. The proposed miniaturized filters with distributed elements may also look similar to the filters based on stepped-impedance resonators [20], [21]. The difference between the two can be clearly seen in the equivalent circuits. For the stepped-impedance filters, the th resonator is constructed by the th and th coupled-line sections that are connected with a transmission line section with a different characteristic impedance (therefore, stepped impedance). On the other hand, the th resonator in the proposed filter is simply a combination of the resonators of the th and th coupled-line sections that resonate at the same frequency. Moreover, as seen in Section V-A, the proposed filter can be realized with lumped

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Fig. 14. Measured wideband S .

Fig. 13. Measured (bold line) and full-wave simulated (thin line) passband response. (a) S and group delay. (b) S .

elements, whereas the stepped-impedance filter cannot be. The outstanding out-of-band performance in Fig. 11(c) cannot be obtained with stepped-impedance filters, as indicated in [20, Figs. 10 and 11]. Filters B–E, and its conventional counterpart are measured in the 1–20-GHz range with an 37247D VNA from Anritsu. Fig. 13 shows the measured and full-wave simulated -parameters and group delay in the passband. The maximum error in the 0.1-dB ripple-level bandwidth, estimated based on the 16.4-dB return-loss bandwidth, is 0.8%. remains below 10 dB in the passbands of all demonstrated filters. Filter B is admittance type and Filter C is impedance type. Since and all coupled-line sections are 45 long in both filters, the two are dual structures. In terms of the size, however, Filter C is smaller than Filter B since the distributed inductors occupy smaller areas than the distributed capacitors. Further size reduction can be obtained for the admittance-type filters by increasing since this decreases the required capacitance. However, should not be too large to maintain the impedance of the grounded coupled-line sections in a practical range. This is the case of Filter D, which is designed with , but with . The size of Filter D is smaller than the size of Filter B and is approximately the same as that of Filter C without performance degradation.

In contrast, increasing to achieve further miniaturization for impedance-type filters (Filter C) is relatively difficult, especially in a planar structure. As increases, as seen in Fig. 9(a), the impedance levels of open-ended coupled-line sections become too low to realize in a planar form. This may be overcome by using multilayered substrates such as a low-temperature co-fired ceramic (LTCC) substrate on which broadside coupling technology facilitates to implement such low-impedance coupled lines. Another interesting point is the ability of the proposed method to control the spurious response in the stopband. The electrical length of each coupled-line section in the admittance-type Filter E is 34.5 , 37 , 24 , and 26.5 . Compared with Filter B and Filter D, the further miniaturization (shorter ) for Filter E requires the impedance of coupled lines to be higher. However, as seen in Fig. 9, the impedance levels can be lowered by choosing a smaller , at the cost of increased capacitance. Therefore, is chosen for Filter E. As seen in Fig. 12, although the coupled-line sections of Filter E are shorter than those of Filter B and Filter D , the size of Filter E is larger than the size of Filter D and is comparable to the size of Filter B. This is mostly due to the larger capacitance for Filter E that occupy a larger area. However, Fig. 14 shows that Filter E provides the most desirable spurious response level while maintaining nearly the same passband performance as other filters, as shown in Fig. 13. More than 40-dB suppression of spurious response is achieved until . This is because the electrical length of 13.13 GHz coupled lines in Filter E is shorter than other filters and also because the spurious resonant frequencies of coupled lines with different electrical lengths are different. This shows that the proposed generalized miniaturization method also provides a means to improve the stopband response in a relatively simple manner. The electrical length of each coupled-line section of Filter E is not optimal since it is chosen based on trial and error. Further improvement in the out-of-band response is expected by optimizing each electrical length through rigorous analysis. Moreover, by replacing one or more distributed reactance sections of Filter E with interdigital capacitors, a further improvement in the stopband response is expected, which remains as future work.

LEE AND LEE: GENERALIZED MINIATURIZATION METHOD FOR COUPLED-LINE BANDPASS FILTERS BY REACTIVE LOADING

VI. CONCLUSION A generalized miniaturization method has been demonstrated for bandpass filters based on popular open-ended coupled lines, as well as grounded coupled lines. The method provides great flexibility since one can choose either the shunt-capacitive loading or the series-inductive loading for miniaturization. Moreover, with the bandwidth ratio before and after miniaturization, one can control the impedance and the reactance levels after miniaturization. Experimental results show that the proposed method allows filter design to be focused on size reduction, improved stopband response, low-cost fabrication, or a combination of these. REFERENCES [1] F. Aryanfar and K. Sarabandi, “Compact millimeter-wave filters using distributed capacitively loaded CPW resonators,” IEEE Trans. Microw. Theory Tech., vol. 54, no. 3, pp. 1161–1165, Mar. 2006. [2] S.-C. Lin, C.-H. Wang, and C. H. Chen, “Novel patch-via-spiral resonators for the development of miniaturized bandpass filters with transmission zeros,” IEEE Trans. Microw. Theory Tech., vol. 55, no. 1, pp. 137–146, Jan. 2007. [3] H.-Y. Chien, T.-M. Shen, T.-Y. Huang, W.-H. Wnag, and R.-B. Wu, “Miniaturized bandpass filters with double-folded substrate integrated waveguide resonators in LTCC,” IEEE Trans. Microw. Theory Tech., vol. 57, no. 7, pp. 1774–1782, Jul. 2009. [4] C.-H. Liang and C.-Y. Chang, “Compact wideband bandpass filters using stepped-impedance resonators and interdigital coupling structures,” IEEE Microw. Wireless Compon. Lett., vol. 19, no. 9, pp. 551–553, Sep. 2009. [5] P. Cheong, S.-W. Fok, and K.-W. Tam, “Miniaturized parallel coupledline bandpass filter with spurious-response suppression,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 5, pp. 1810–1816, May 2005. [6] S.-M. Wang, C.-H. Chi, M.-Y. Hsieh, and C.-Y. Chang, “Miniaturized spurious passband suppression microstrip filter using meandered parallel coupled lines,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 2, pp. 747–753, Feb. 2005. [7] S.-S. Myoung and J.-G. Yook, “Miniaturisation and harmonic suppression method of parallel coupled-line filters using lumped capacitors and grounding,” Electron. Lett., vol. 41, no. 15, pp. 849–851, Jul. 2005. [8] S.-S. Myoung, Y. Lee, and J.-G. Yook, “Bandwidth-compensation method for miniaturized parallel coupled-line filters,” IEEE Trans. Microw. Theory Tech., vol. 55, no. 7, pp. 1531–1538, Jul. 2007. [9] S. Lee and Y. Lee, “Improved miniaturization method for coupled-line filters,” Microw. Opt. Technol. Lett., to be published. [10] G. L. Matthaei, L. Young, and E. M. Jones, Microwave Filters, Impedance-Matching Network, and Coupling Structures. Dedham, MA: Artech House, 1980. [11] R. Phromloungsri, M. Chongcheawchamnan, and I. D. Robertson, “Inductively compensated parallel coupled microstrip lines and their applications,” IEEE Trans. Microw. Theory Tech., vol. 54, no. 9, pp. 3571–3582, Sep. 2006.

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[12] K. Hettak, G. A. Morin, and M. G. Stubbs, “The integration of thin-film microstrip and coplanar technologies for reduced-size MMICs,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 1, pp. 283–291, Jan. 2005. [13] S. Lee and Y. Lee, “A planar dual-band filter based on reduced-length parallel coupled lines,” IEEE Microw. Wireless Compon. Lett., vol. 20, no. 1, pp. 16–18, Jan. 2010. [14] C.-F. Chen, T.-Y. Huang, and R.-B. Wu, “Design of microstrip bandpass filters with multiorder spurious-mode suppression,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 12, pp. 3788–3793, Dec. 2005. [15] J.-T. Kuo and J.-P. Lin, “Dual-band bandpass filter with improved performance in extended upper rejection band,” IEEE Trans. Microw. Theory Tech., vol. 57, no. 4, pp. 824–829, Apr. 2009. [16] S. B. Cohn, “Parallel-coupled transmission-line-resonator filters,” IRE Trans. Microw. Theory Tech., vol. MTT-6, no. 2, pp. 223–231, Apr. 1958. [17] G. L. Matthaei, “Design of wide-band (and narrow-band) band-pass microwave filters on the insertion loss basis,” IRE Trans. Microw. Theory Tech., vol. MTT-6, no. 6, pp. 580–593, Nov. 1960. [18] High Frequency Structure Simulator. ver. 10.0, Ansoft Corporation, Pittsburgh, PA, 2005. [19] J.-S. Hong and M. J. Lancaster, Microstrip Filters for RF/Microwave Applications. New York: Wiley, 2001. [20] M. Makimoto and S. Yamashita, “Bandpass filters using parallel coupled stripline stepped impedance resonators,” IEEE Trans. Microw. Theory Tech., vol. MTT-28, no. 12, pp. 1413–1417, Dec. 1980. [21] Y. P. Zhang and M. Sun, “Dual-band microstrip bandpass filter using stepped-impedance resonators with new coupling schemes,” IEEE Trans. Microw. Theory Tech., vol. 54, no. 10, pp. 3779–3785, Oct. 2006. Seungku Lee was born in Seoul, Korea, in 1982. He received the B.S. and M.S. degrees from Yonsei University, Seoul, Korea, in 2008 and 2010, respectively. He is currently with the Radio Communication Research Center, Yonsei University. His current research interests include multiband planar circuits for microwave applications. Mr. Lee was the recipient of the Bronze Award in the Samsung Human-Tech Paper Competition in 2008 and the Silver Award in 2010.

Yongshik Lee (S’00–M’04) was born in Seoul, Korea. He received the B.S. degree from Yonsei University, Seoul, Korea, in 1998, and the M.S. and Ph.D. degrees in electrical engineering from The University of Michigan at Ann Arbor, in 2001 and 2004, respectively. In 2004, he was a Post-Doctoral Research Associate with Purdue University, West Lafayette, IN. From 2004 to 2005, he was with EMAG Technologies Inc., Ann Arbor, MI, as a Research Engineer. In September 2005, he joined Yonsei University, as an Assistant Professor. His current research interests include passive and active circuitry for microwave and millimeter-wave applications and electromagnetic metamaterials.

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Group-Delay Engineered Noncommensurate Transmission Line All-Pass Network for Analog Signal Processing Shulabh Gupta, Student Member, IEEE, Armin Parsa, Member, IEEE, Etienne Perret, Member, IEEE, Richard V. Snyder, Life Fellow, IEEE, Robert J. Wenzel, Life Fellow, IEEE, and Christophe Caloz, Fellow, IEEE

Abstract—A group-delay engineered noncommensurate transmission line two-port all-pass network for analog signal-processing applications is presented, analytically modeled, and experimentally demonstrated. This network consists of transversally cascaded C-sections, which are distributed implementations of the bridged-T equalizer lumped circuit. It is obtained by interconnecting the alternate ports of adjacent lines of a 2 -port coupled transmission line network with transmission line sections, and it is modeled using multiconductor transmission line theory with per-unit-length capacitance matrix C and inductance matrix L. By allowing the different C-sections of the network to exhibit different lengths, a generalized group-delay engineering procedure is proposed, where quasi-arbitrary group-delay responses are achieved by combining the group-delay responses of C-sections with different lengths. A computer design approach based on genetic algorithms is applied for synthesis, which consists of determining the structural parameters of the different C-section groups. Using this approach, noncommensurate networks are group-delay engineered in edge-coupled stripline technology, and Gaussian, linear and quadratic group-delay responses are realized. The theoretical results are validated by experiment. Finally, two application examples of analog signal processing—a tunable impulse delay line and a real-time frequency discriminator—using the proposed dispersive noncommensurate all-pass networks are presented. Index Terms—All-pass circuits, analog signal processing, dispersive media, genetic algorithms (GAs), group-delay engineering, multiconductor transmission lines, noncommensurate networks.

I. INTRODUCTION

W

ITH THE ever-increasing demand on higher spectral efficiencies and the related emergence of ultra-wideband (UWB) systems, monitoring RF environments in real time has become of paramount interest [1]. This is traditionally done

Manuscript received April 06, 2010; revised June 01, 2010; accepted June 08, 2010. Date of publication August 16, 2010; date of current version September 10, 2010. S. Gupta and C. Caloz are with the Department of Electrical Engineering, PolyGrames Research Center, École Polytechnique de Montréal, Montréal, QC, Canada H3T 1J4 (e-mail: [email protected]). A. Parsa was with the Department of Electrical Engineering, PolyGrames Research Center, École Polytechnique de Montréal, Montréal, Québec, Canada H3T 1J4. He is now with Rutter Inc., St. John’s, NL, Canada A1E 3T9. E. Perret is with the Laboratoire de Conception et d’Intégration des Systémes (LCIS)/Grenoble Institute of Technology, Valence 38031, France. R. V. Synder is with RS Microwave, Butler, NJ 07405 USA. R. J. Wenzel resides in Woodland Hills, CA 91367 USA. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2010.2058933

using real-time signal-processing techniques based on either digital or analog approaches. Digital devices are most attractive at low frequencies due to their high flexibility, compact size, low cost, and strong reliability. However, at higher frequencies, such as millimeter-wave frequencies, digital devices suffer of fundamental issues, such as poor performance, high cost for A/D and D/A converters, and excessive power consumption. At such frequencies, analog devices and systems are required for real-time signal-processing applications [2] such as analog real-time spectrum analyzers for the measurement and characterization of complex nonstationary signals [3], tunable delay lines [4], compressive receivers [5], real-time Fourier transformers, convolvers, and convoluters [6]. The core of an analog real-time signal processor is a dispersive structure. In a dispersive structure, the group velocity is a function of frequency, which results in a frequency-dependent group delay. Consequently, a wide-band signal traveling along such a structure experiences time spreading since its different spectral components travel with different group velocities and are, therefore, temporally rearranged [7]. By exploiting this temporal rearrangement, the various spectral components of a wideband signal can be directly mapped onto time domain and can then be processed in real time for various applications. At microwaves, dispersion can be achieved using different technologies. Surface acoustic wave devices [8], thanks to their slow-wave characteristic, provide large delays ( 1 s), and hence, a large time-bandwidth product, while exhibiting a compact size. However, they are restricted to narrowband (2 GHz) and low-frequency applications ( 2 GHz) due to limitations of photolythography. Magnetostatic-wave devices [9] offer high-frequency and wideband operation along with large time-bandwidth product. However, in addition to being lossy, they require a bulky and nonplanar permanent magnet. Reflection-type structures, such as multisection coupler-based structures and microstrip lines, have also been reported [10]. These structures are composed of series-connected coupled-line couplers operating at contiguous frequencies, and may achieve high frequency ( 10 GHz) and wideband ( 3 GHz) operation. However, their bandwidth is proportional to the size of the structure, which leads to long and extremely lossy structures for high bandwidth. In order to decrease loss, high-temperature superconductors (HTSs), requiring cryogenics, must be utilized, which results in complex and expensive devices [11]. On the other hand, the chirped microstrip line [12], [13] is a simple and planar structure, which utilizes Bragg reflections based on

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impedance mismatch. However, due to multiple internal reflections, as a result of Bragg phenomenon at the impedance steps, the group delay and magnitude response always fundamentally exhibit undesired ripples resulting in uneven responses. None of these technologies provide ideal solutions for analog signal processing and more research is required in this direction. An ideal dispersive structure should provide a flat magnitude response with a smooth and a continuous group-delay profile within the operation frequency range. Achieving such characteristics requires an independent control over the magnitude and group delay of the structure, which is only possible with nonminimum phase filters exhibiting an all-pass response [14]. These structures typically operate in transmission mode, where smooth group-delay responses can be achieved and arbitrary operational frequencies with arbitrary operational bandwidth are attainable, including in planar monolithic microwave integrated circuit (MMIC) compatible technologies. They possess many degrees of freedom for group-delay engineering. For example, an exact synthesis of cascaded commensurate transmission line (same length for all the lines) C-section all-pass network was reported in [15] to realize prescribed phase characteristics. However, the synthesis presented in [15] is limited to a maximum of three C-sections and is demonstrated only for narrowband phase-shifting applications. Many related works on the design of phase shifters based on coupled transmission lines have been later reported such, as for instance, [16]–[18]. Similarly, an allpass filter design method for equalizing acoustic signals is presented in [19] and another one using a lumped lattice circuit model is presented in [20]. In this work, we thus exploit the properties of all-pass microwave C-sections to elaborate a systematic group-delay synthesis procedure using edge-coupled noncommensurate all-pass network for real-time signal-processing applications. We show the equivalence between a bridged-T equalizer and a C-section implemented using coupled-line couplers, which are the fundamental building blocks of the final noncommensurate networks. These networks are rigorously analyzed using multiconductor transmission line theory in conjunction with the method-of-moments technique. A computer design approach is then applied to synthesize this network for wide variety of group-delay responses. We also further demonstrate the usefulness of such group-delay engineered dispersive structures in two impulse regime system examples: a tunable delay line and a real-time frequency discriminator. The essence of this all-pass network approach was suggested by Hewitt back in 1967 [21]. However, the following distinctions exist between the present work and the one of Hewitt. 1) Hewitt’s structure was a volumetric folded tape meander line, which was nonplanar, and therefor,e incompatible with MMICs; it is also difficult to fabricate and suffers from high loss and from severe requirements on dimensional tolerances that tend to limit the upper frequency range of operation to about 5 GHz. In contrast, the proposed stripline (or microstrip) structure is much simpler, completely planar and fully compatible with MMICs, and may be realized easily in the millimeter-wave range.

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2) The structure of Hewitt used commensurate folded sections, and the different group delay–frequency states were achieved by the heavy and impractical insertion of dielectric slabs of different thicknesses between the folded sections; in contrast, the proposed structure achieves different delay–frequency states by simply modulating the lengths of the different sections. 3) Hewitt mentions only a folded tape meander line and does not establish the equivalence between the folded line pairs and C-section all-pass equalizers; in contrast, this equivalence is demonstrated in this paper, and it may be exploited for more efficient designs based on simple lumped element circuit models. 4) Hewitt uses approximate and empirical design formulas; in contrast, this paper presents an accurate numerical technique, based on the method of moments (MoM). 5) In addition, this work proposes a systematic and automated design procedure, using genetic algorithms (GAs), which allows the efficient design for complex group-delay responses, as demonstrated in this paper. This paper is organized as follows. Section II presents the principle of group-delay engineering using a cascaded microwave C-section based on bridged-T equalizer circuit model. Section III provides the derivation of the scattering -port commensurate coupled line and the matrix of the corresponding two-port all-pass network using multiconductor transmission line theory. Section IV extends the multiconductor transmission line analysis applied to a commensurate network to noncommensurate transmission line network. Based on the corresponding two-port all-pass network, this section also presents various group-delay synthesis examples along with experimental results using GA design. Section V presents two system examples based on dispersive all-pass networks and conclusions are provided in Section VI. Finally, the Appendix derives some of the analytical results of this paper. II. GROUP-DELAY ENGINEERING USING ALL-PASS FILTERING SECTIONS A typical bridged-T equalizer is shown in Fig. 1(a). It is a lumped-element all-pass filter circuit utilizing a bridged-T topology that passes all frequencies equally in terms of magnitude, but changes the phase relationship between them [14]. It is generally used to compensate for undesired phase shifts that arise in systems due to the various group-delay responses of the different components. In microwave applications, it is convenient to replace the lumped-element bridge-T by an equivalent distributed network consisting of transmission line sections. One possible distributed implementation of the bridged-T equalizer of Fig. 1(a) is the shorted coupled-line pair shown in Fig. 1(b), which is known as a C-section. Its transfer function may be obtained by prescribing and in the 4 4 scattering matrix of a coupled-line pair (as derived in Section VII-A), and reads (1)

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Fig. 2. Principle of group-delay engineering using cascaded all-pass network sections, illustrated here for the case of a linear positive-slope group delay (positive chirp).

Fig. 1. Shorted coupled transmission line all-pass network. (a) Bridge-T circuit model. (b) Stripline layout. (c) Typical group-delay response. (d) Group delay  versus the electrical length  and the coupling coefficient k . Circuit parameters: L : nH, C : pF, L : nH, and C : pF, and the coupler parameters: k : ;f : GHz and " : in (2).

= 7 82

= 1 15 = 0 91

= 3 52 = 2 31

= 1 57 =22

where with at the frequency of the delay peak, is the coupling coefficient of the coupler, and is the propagation constant of the transmission lines building the coupler. It may be easily verified that this function satisfies the magnitude of an all-pass response. condition The group delay of the coupled-line all-pass network of 1(b), obtained by deriving the phase of (1), is given by the expression

delay characteristics strongly depend on the coupling coefficient , as apparent in (2). As increases, the full-width halfdecreases and the absomaximum group-delay bandwidth lute group-delay swing increases, as shown in Fig. 1(d). In area is constant and unity, as demonstrated in fact, the Section VII-B. To verify that the distributed all-pass network of Fig. 1(b) follows the model of the bridged-T equalizer, Richard’s transformation is applied to the lumped element model of Fig. 1(a) [22]. This is achieved by replacing the inductive elements with a short-circuited stub with impedance and the capacitive elements with an open-circuited stub with , where impedance and is the propagation constant of the stubs. Fig. 1(c) shows the corresponding response with curve-fitted parameters to obtain the group delay of a coupled-line all-pass network. Perfect agreement is observed between the two responses, establishing the equivalence between the two systems. Upon this basis, a coupled-line all-pass network can be used to implement various group-delay responses similar to those achieved by bridged-T equalizers in fully distributed form. For this purpose, a series of individual all-pass filtering sections with different parameters are cascaded to realize a wide range of group-delay characteristics. This principle of group-delay engineering is illustrated in Fig. 2, where a desired group-delay response is achieved as a superposition of various group-delay functions provided by coupled-line all-pass networks with peak centered at . group delays III. COMMENSURATE COUPLED-LINE NETWORKS

with (2) and a typical group-delay response is shown in Fig. 1(c). Due to the distributed nature of the network, the group-delay response is periodic in frequency with maxima occurring at odd multiples of the fundamental coupling frequency , i.e., for , where is an integer, or equivalently, . The group-delay responses at harmonic frequencies will naturally contribute to the overall group delay of the all-pass network; specifically, compared to a lumped bridge-T equalizer, it will increase the delay at higher frequencies cor. Furthermore, the groupresponding to odd multiples of

The commensurate (or uniform) versions of the noncommensurate group-delay networks, which will be described in Section IV, are shown in Fig. 3, where Fig. 3(a) represents -port initial network, while Fig. 3(b) represents the the two-port network obtained by short circuiting the appropriate ports so as to build a meandered line structure to achieve a desired peak delay at the frequency where the couplers are a quarter-wavelength long. A. Derivation of the Scattering Matrix of the -Port Network Using Multiconductor Transmission Line Analysis -port structure Let us first consider the commensurate of Fig. 3(a), which may also be seen as a multiconductor

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structure, can be obtained assuming TEM wave propagation along the structure. These equations take the form [24]

(4a) (4b)

(4c)

N

Fig. 3. Commensurate (uniform-length) coupled-line network. (a) 2 -port structure. (b) Two-port structure obtained by interconnecting all adjacent lines, except at the first and th ports.

N

transmission line network, and which includes transmission lines of length . We call the input and output voltage vectors of the network (at ) and at , respectively. The corresponding input and and output current vectors are at and , -port network can be characterized respectively. Such a and an inductance by a per-unit-length capacitance matrix per matrix [23]. The entries of relate the total charge unit of line length on the th conductor to all the line voltages or producing it by

where is the relative permittivity of the stripline substrate and and are the characteristic admittance and impedance matrices, respectively, of the lines. Applying the at and boundary conditions at in (4) yields, assuming a lossless structure, (5a) (5b) (5c) Inverting the first two equations of (5) yields the following matrix relation: (6a) with (6b)

(3)

The diagonal elements are the per-unit-length self-capaciwith are the tances of the th line, while the elements per-unit-length capacitance between the th and th line. Similarly, the entries of relate the total per-unit-length magnetic around the th line to all the line currents producing it flux . by The matrices and may be determined as static transverse field solutions for perfect line conductors using, in general, an approximate numerical method. The corresponding MoM approach is outlined in Section VII-C. Furthermore, closed-form analytical expressions for stripline configurations, which will be used for group-delay synthesis in Section IV, are also provided in the Appendix. Once the and matrices have been determined for a given -coupled-lines configuration, the generalized telegrapher’s equations, which completely determine the behavior of the

where is the identity matrix. The trans-port mission line network can then be analyzed as a network using (6), from which other network matrices can readily be derived using standard transformations. The corresponding scattering matrix, which will be used in the sections evaluating the group-delay response of the network, is shown in (7a) and (7b) at the bottom of this page, where denotes the inverse of a is the reference impedance common to all the matrix and ports (assumed 50 throughout this paper). B. Transformation Into a Two-Port All-Pass Network As pointed out in Section II, a four-port coupled-line pair consisting of two lines can be transformed into an all-pass network by connecting the ends of two lines, which converts it into a two-port network. Similarly, the -port transmission line network of Fig. 3(a) can be converted into an all-pass two-port network by interconnecting adjacent lines, except at the first and

(7a) (7b)

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In general, the transfer matrices of the different commensuhave dimensions that differ from . rate sections Therefore, the individual wave-transmission matrices cannot be simply cascaded due to incompatible dimensions. The matrices are, therefore, forced to bewith dimensions less than matrices by the introduction of fictitious transmiscome sion lines of zero length with perfect amplitude transmittance and ) and no couplings between adjacent (i.e., lines, as shown in Fig. 4(a). -port network The wave transmission matrix of the overall is next obtained by cascading the individual transmission matrices as (10)

N

Fig. 4. Noncommensurate coupled-line network. (a) 2 -port structure. (b) Two-port structure obtained as in Fig. 3 from (a).

th ports, as shown in Fig. 3(b). This is achieved via (7), where the shorting sections are modeled by small transmission line and length [22], following the procedure sections of width described in Section VII-D. Once the two-port scattering matrix is computed by has been obtained, the group delay (8) where is the unwrapped transmission phase of the two. port network with phase origin at

where is the total number of commensurate subsections in -port scattering matrix of the overall nonthe structure. The commensurate network is then obtained by the reverse transformation [25]

(11) Finally, the -port configuration of Fig. 4(a) is transformed into the two-port all-pass network of Fig. 4(b) by introducing the connections indicated in the figure. The final two-port scatis obtained from -port scattering parametering matrix as ters (12)

IV. GROUP-DELAY DESIGN USING NONCOMMENSURATE TRANSMISSION LINE NETWORKS This section extends the multiconductor transmission line transmission lines (or analysis applied to equal-length a commensurate or uniform network) in Section III to noncommensurate transmission lines (or a nonuniform network). Following the principles described in Section II, this allows to engineer desired group-delay responses. The design is performed here using GAs and is verified experimentally for several responses. A. Derivation of the Two-Port Scattering Matrix of the All-Pass Network A generic noncommensurate transmission line network of lines is shown in Fig. 4(a), where the line pairs may have different lengths. The new task is to obtain the scattering matrix of such a configuration, analogous to that obtained in (7) for the commensurate network. This structure of Fig. 4(a) can be considered as a longitudinal ( direction) cascade of commensurate networks of different -port wave-transmission matrix of the lengths . The th commensurate section may be obtained by standard transformation of the -matrix of (7) [25]

(9)

to which is derived in Section VII.D along with the matrices , which are not repeated here. To confirm the validity of the proposed approach, the scattering matrix and group-delay response of both a commensurate and noncommensurate coupled-line all-pass networks, in stripline configurations, are compared with full-wave results in Fig. 5. Excellent agreement is found for the two cases, which validates the theoretical approach. The minor discrepancies obat higher frequencies are maybe attributed to inacserved in curacies of the theoretical results not taking into account corner discontinuities and subsequent small diffraction effects. Since coupling is generally very low (typically less than 10 dB) in edge-coupled couplers [26], i.e., between adjacent transmission lines, it is expected that the capacitive and inductive coupling between the nonadjacent lines of the coupled-line networks of Figs. 3 and 4 should be negligible. In order to both confirm this expectation and quantify the minor effects of nonadjacent coupling, Fig. 6 compares the results obtained of (3) and complete by using complete capacitance matrix and by setting to zero corresponding inductance matrix all the coupling elements between the nonadjacent lines in this matrices. Fig. 6(a) confirms that the effects of coupling between nonadjacent lines are minor: the group-delay response responses are almost undistinguishable between the and two cases when the linewidth and gapwidth are relatively large, in the order of the dimensions used throughout this paper; these

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(b)

Fig. 5. Comparison of the S -parameters and group delay obtained by theory using (30) and (8) and by full-wave simulation (Ansoft Designer) for stripline configurations. (a) Commensurate coupled-line network. (b) Noncommensurate coupled-line network using randomly chosen section lenghts. The structural pamil, gapwidth g mil, " : , and rameters are: linewidth w mil. substrate thickness h

= 16 = 50

= 16

= 6 15

Fig. 7.

GA-based design procedure.

coupling effects may play a significant role. This problem will be investigated separately and reported elsewhere. B. GA Design

(a)

(b)

Fig. 6. Effect of couplings between nonadjacent transmission lines on the S -parameter and group-delay responses, shown here for the case of stripline commensurate all-pass networks. (a) Weak coupling associated with large : ;h linewidth and gapwidth (w g mil). (b) Tighter mil, " coupling associated with smaller (half) linewidth and gapwidth (w g mil, " : , substrate thickness h mil). mil, and w

= = 16

= 6 15

= 6 15 = 50 =9 = 50

= =8

effects become naturally more apparent for smaller linewidths and gapwidths, as seen in Fig. 6(b). Nevertheless, the complete multiconductor approach used here proves useful to accurately for optimal matching, model the low magnitude levels of ) and as seen by comparing Figs. 5 (good accuracy even in , but poor accuracy 6(a) and (b) (acceptable accuracy in ). It should be noted that the situation may be different in in the case of complex vertical structures using combinations of edge- and broadside-coupled sections, where nonadjacent

The commensurate coupled-line network of Fig. 3 exhibits a fixed group-delay response of the type shown in Fig. 1 and given for one C-section by (2), depending on the length and coupling factor , as discussed in Section II. However, flexibility in the group-delay design can be introduced by allowing the different transmission line C-sections in the all-pass network, thereby making the network noncommensurate, to exhibit different lengths , as shown in Fig. 4 and illustrated in Fig. 5(b) for a random choice of the lengths. In fact, by varying the lengths of the different C-sections, quasi-arbitrary group-delay responses—such as linear nonconstant, Gaussian, or quadratic responses—may be achieved with the noncommensurate all-pass network of Fig. 4(b). To the authors’ knowledge, no closed-form solutions are available for the design of group delay in a noncommensurate all-pass network. Therefore, a computer design approach is required to determine the structural parameters of the individual C-sections to realize a desired group-delay response. Since the solution set is a priori unknown and may be potentially relatively complex, an efficient global optimization technique is required. GAs are a convenient approach to solve such global optimization problems, where the fitness landscape is complex discontinuous noisy variant in time or exhibits several local optima [27]. They provide a quick scan of a vast solution set, particularly suitable for large-space problems, where testing of all possible solutions in serial fashion would be too time

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TABLE I TARGET GROUP-DELAY RESPONSES

Fig. 8. Various group-delay responses corresponding to the target responses of Table I and obtained by GA design (without any dielectric and conductor losses). (a) Intrinsic response of the commensurate network. (b) Gaussian group delay. (c) Linear group delay with a slope of 0.125 ns/GHz. (d) Linear group delay with a slope of 0.25 ns/GHz. (e) Quadratic group delay.

consuming. However, a drawback of GAs is that they do not necessarily guarantee convergence to the optimal solution. Thus, the noncommensurate all-pass networks presented below are not necessarily optimal, although they essentially meet the design specifications. A GA is now applied to the noncommensurate coupled-line network of Fig. 4 for group-delay design. This is done with the Genetic Algorithm and Direct Search Toolbox from MATLAB,1 with two sets of variables to be determined: and , where represents the set of number of C-sections corresponding to the lengths of the set . In the following designs, the width of the lines, the width of the end connecting transmission line sections, the gap between them, the substrate thickness , and the substrate permittivity are assumed to be fixed, and and are equal for all the lines. These parameters may also be varied, at little computational expense, but this was not found 1Genetic

Algorithm and Direct Search Toolbox 2.4.2.

necessary. The parameter sets by minimizing the fitness function

and are determined , defined as

(13) where is iterative group delay computed by (8) and is the target group-delay function. Fig. 7 outlines the complete GA-based design procedure. C. Analytical and Experimental Results The analytical results for the target group-delay responses listed in Table I and with the parameters mil, mil, mil, mil, and are plotted in Fig. 8 for stripline configurations. The chosen line gapwidth and linewidth corresponds to a coupling level of 16.8 dB. Fig. 8(b)–(e) shows the structures obtained, while Fig. 8(a) shows the group-delay response of a simple commensurate

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Fig. 9. Illustration of the problematic of harmonics for the realizations of the negative-slope group delays with the specification:  (! ) =  and  (! ) =  . (a) Positive group-delay scenario with ! = 3 ! . (b) Negative group-delay scenario with ! = 3 ! , which is unrealizable. (c) Negative group-delay scenario with ! = 2 ! , where ! = 3! does not fall within the frequency range of interest.

structure for reference. Excellent agreement is observed between the target group-delay functions and corresponding group delays of the noncommensurate all-pass network structures. dB) is achieved in Moreover, acceptable matching ( all the cases. The group-delay profiles in Fig. 8 all exhibit a positive slope. In this case, the distributed nature of the noncommensurate lines benefits the compactness of the structure, whereas it may prohibit the realization of negative slope group-delay profiles, as a consequence of the fact that C-sections exhibit maximal delay , at all odd harmonics of , i.e., at as shown in Fig. 1. This is illustrated in Fig. 9. Fig. 9(a) shows , where the third hara positive slope scenario, with monic of the longer C-section strongly contributes to the delay at , thereby reducing the number of required shorter C-sections. Fig. 9(b) shows a negative slope scenario, also with , which cannot be realized with the proposed network since the larger C-section imposes the same delay at as at , which adds to the delay provided there by the shorter C-section. Fig. 9(c) shows a negative slope scenario, this time with , which can be realized by the proposed network if the third harmonic of the longer C-section falls above the frequency range of interest. However, this realization is inherently restricted to a smaller frequency range, as compared to what can be achieved in the positive slope case of Fig. 9(a). The harmonic issue illustrated in Fig. 9(b) may be solved either by using a combinations of distributed transmission line C-sections for the shorter sections and lumped (chip) element equalizers for the longer sections or by using the technique of mixer inversion [5]. It may be observed that the commensurate structure of Fig. 8(a) exhibits a fairly regular return loss pattern versus frequency across the whole operation bandwidth, somewhat like a transmission line, except for slightly different distances between attenuation zeros due to dispersion. As the structure deviates from the commensurate configuration, and its group delay subsequently deviates from that of this configuration, as in Fig. 8(b)–(e), the return-loss pattern loses its regularity in terms of frequency. The higher the degree of “commensurateness,” the lower the degree of regularity. This demonstrates the capability of noncommensurate all-pass network for

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group-delay engineering and the appropriateness and accuracy of the proposed multiconductor transmission line analysis and GA design approach. Fig. 10 shows the measurement results for the fabricated noncommensurate all-pass network stripline prototypes corresponding to the structures of Fig. 8(b)–(e). The photogrpah of one of the prototypes, namely, the one of Fig. 8(d) is shown in Fig. 11. The prototypes are shown in the insets of Fig. 10(a)–(d). The noncommensurate strip structures are sandwiched between two dielectric layers (Rogers Duroid 3006, 25-mil thickness) and closely spaced via-holes are placed along the contours of these structures to provide proper connection between the two stripline ground planes and to avoid spurious radiation and resonances. The prototypes include a microstrip-to-stripline transition (not shown in the figure). The experimental results may be compared to the analytical results of Fig. 8. All the prototypes exhibit a perfectly smooth transmission phase response resulting in a smooth group-delay profile. The various targeted group-delay profiles (Gaussian, linear, and quadratic) are successfully achieved with reasonable dB and dB insertion and return losses (RL in all cases). However, discrepancies are observed between the experimental results and theoretical predictions. First, the experimental group-delay swing exceeds the design group delay (following the specifications of Table I, based on MoM results without conductor and dielectric losses) by 20%–30%. Second, the experimental insertion loss is higher by 1–2 dB than that predicted by full-wave simulations (not shown here), especially toward higher frequencies. In fact, the prototype is a complex multilayer structure. It includes a 5–22- m thick (exact thickness unknown in the fabrication process used) lossy and ) to hold the two epoxy layer ( substrates of the stripline structure together (not taken into account in above GA designs). Furthermore, the thickness of the metal strips (17 m) is not negligible with respect to the epoxy layer (the metal thickness was set to zero in above GA designs), and may therefore have caused the formation of air gaps and slight substrate deformations. Thus, a significant level of uncertainty exists regarding the exact fabricated structure, and prevents its exact modeling. In the mathematical and analytical (MoM) results of Figs. 8 and 10, several of the aforementioned detailed features of the fabricated prototype were not taken into account, namely, the presence of the vias (with their exact locations), adhesion epoxy layer, strips copper thickness, and two microtrip-to-stripline transitions. To confirm that the observed discrepancies are due to these experimental parameters, one of the prototypes, which was arbitrarily chosen as the prototype of Fig. 10(c) [or 8(d)], was subjected to extensive full-wave analyses taking them all into account. Fig. 12(a) shows the corresponding group-delay response results. In these results, a significant increase in the group delay is observed over the bandwith of interest (1.2 ns) compared with the idealized theoretical model (1.0 ns). Various parametric simulations (not shown here) have revealed that the slight variation in the group-delay swing was mostly due to the epoxy layer. This may be explained from the fact that the phase velocities of the even and odd modes of the coupled-line C-sections differ

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Fig. 10. Experimental group-delay responses of the prototypes. The group-delay smoothing option of the vector network analyzer was used here to obtain a slope that can be clearly measured and compared with the ideal design. (a) Gaussian group delay. (b) Linear group delay with a slope of 0.15 ns/GHz. (c) Linear group delay with a slope of 0.32 ns/GHz. (d) Quadratic group delay.

Fig. 11. Photographs of fabricated prototype. (a) Overall view showing the array of via-holes and microstrip-stripline transitions. (b) Internal view of the printed C-section trace. (c) Zoom of a small region of the C-section trace illustrating the etching inaccuracies of the strips.

from each other due to the difference between the permittiviand of the surrounding subties of the epoxy layer , whereas these velocities are equal in the strate case of the homogeneous dielectric considered in the GA designs. Since the structure includes a large number of cascaded C-sections, these discrepancies add up along the structure and finally lead to a significant deviation of the group-delay response compared to the original design. The large difference between

measured and simulated data, shown in Fig. 9, was further investigated. The data of Fig. 12(a) compare measured data with a very detailed and time-consuming full-wave simulation incorporating all of the details (epoxy, via location, etc.), on the network illustrated in Fig. 10(c). Given that the resulting difference between measured and full-wave-simulated results is only about 5% (1.26 ns measured versus 1.2 ns simulated) and considering that etching tolerance [as apparent in Fig. 11(c)] also contributes to deviations from the computed coupling values, especially for the low coupling levels considered here ( 16.8 dB), it is asserted that the proposed theory is reasonably accurate, and therefore, is appropriate for the design of cascaded section networks exhibiting a wide variety of group-delay characteristics, i.e., group-delay engineered networks. It is also evident that there is a room for improvement in implementation methods. Full-wave simulations further indicated (not shown here) that , as the presence of relatively lossy epoxy layer ( compared to of the surrounding substrate) also contributes to the extra insertion loss, which is essentially dissipative, as they did not evidence any leakage between the vias or any other type of radiation, as shown by the electric and magnetic field distributions in Fig. 12(b) and (c). A high-quality industrial-class fabrication process would naturally alleviate these issues. As mentioned above, the group-delay designs of Figs. 8 and 10 are not necessarily optimal. An ideal design would be the one achieving a maximum group-delay swing bandwidth product over the smallest footprint—which typically requires a of C-sections and small strip widths and small number

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V. APPLICATION EXAMPLES This section demonstrates two application examples of the group-delay engineered all-pass networks: a tunable impulse delay line and a real-time frequency discriminator. A. Tunable Impulse Delay Line The most useful property of a dispersive structure is its frequency-dependent group delay. The time delay experienced by a modulated signal propagating along a dispersive structure depends on its center (or carrier) frequency , and may therefore be tuned by varying this frequency. A frequency-tunable delay line system, similar to the system presented in [4], but with an all-pass network replacing the CRLH dispersive delay line, is shown in Fig. 13(a). This system works both for continuous-wave or narrowband signals and impulse-wave or broadband signals. It constitutes a fundamental block in various analog signal-processing systems, such pulse-position modulators (PPMs) [28], dispersion compensators, convolvers, and convoluters [6]. This system offers several advantages compared to conventional systems (e.g., surface acoustic wave and magnetostatic wave system), including good matching over a broad bandwidth, high operation frequencies, and compatibility with planar microwave integrated circuits. Fig. 13(b) shows results for two different delays of a Gaussian input pulse using a simple commensurate all-pass network. The output pulses are spread in time, with a spreading proportional to the group-delay slope, as a consequence of frequency-dependent phase velocity, which incur different travel times to the different spectral components of the input pulse. However, they can be perfectly compressed back to their original width while retaining the different delays by using either a second all-pass network with the opposite group-delay slope [29] or mixer inversion [5]. Fig. 12. Full-wave [finite-element method (FEM) High Frequency Structure Simulator (HFSS)] and experimental results explaining the slight discrepancies observed in Fig. 10, specifically for the case of Fig. 10(c), and clarifying the nature of loss in the structure. The simulation results take into account conductor and dielectric losses, the microstrip-to-stripline transitions, the 17-m copper thickness, the 22-m epoxy layer, and the exact array of via-holes of the prototype. (a) Group-delay response. The measured result does not include any smoothing. (b) Electric field distribution (magnitude) at 5 GHz. (c) Magnetic field distribution (magnitude) at 5 GHz. The field distributions (both taken in the middle of the stripline structure) indicate that radiation losses are negligible.

gaps —and with the lowest possible insertion and return losses. These requirements are clearly incompatible and tradeoffs are subsequently necessary. In the designs of Figs. 8 and 10, all the strip widths and gap spacings were fixed to mil in order to achieve a minimum insertion loss, which are required for the specified group-delay swings and bandand 13 C-sections for the designs of widths Fig. 10(a)–(d). According to extensive GA tests with additional and the lengths degrees of freedom ( and in addition to of the C-sections), the number of C-sections can be dramatically reduced in all the cases. However, this is at the expense of higher insertion loss and poorer return loss. This issue may find good solutions in multilayer configurations with broadside-coupled (as opposed to edge-coupled) C-sections, where tight coupling is easily achieved and cross coupling between nonadjacent C-sections could become available.

B. Real-Time Frequency Discriminator A classical analog signal-processing application of dispersive structures is the compressive receiver, mostly used in radar applications [30]. A typical system schematic of this receiver is shown in Fig. 14(a). The system operates as follows. It employs two dispersive structures—here, two noncommensurate all-pass networks—with identical group-delay response (e.g., up-chirped function). The RF incoming frequencies to be discriminated at the receiving antenna are mixed with moda down-chirped (negative frequency ramp) pulse ulated at a fixed frequency , retaining only the lower side sideband using a bandpass filter. This chirped pulse is obtained by injecting a pulse into dispersive network #1, which is followed by a mixer inversion block to generate a down chirp. The mixed signal is then injected into dispersive network #2 with an exact group-delay response as the first. As the down-chirped signal propagates through network #2, the signal is compressed in time as a result of chirp cancelation. This leads to distinct compressed pulses, corresponding to the respective frequencies occurring at times . Thus, each frequency is thus mapped onto time according to the , where is the dispersion slope mapping function of the dispersive networks. As an example, Fig. 14(b) shows the response of the system using dispersive noncommensurate

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= =

Fig. 13. Impulse delay line system with carrier frequency tunability. (a) System. (b) Mixed analytical-circuit simulation results for the parameters w g mil, w mil, h mil, " : ;` mil [(a) represents a general noncommensurate all-pass network, but (b) shows results for the particular . case of a commensurate all-pass network, with constant length `], and N

16

=9

= 50

= 6 15 = 250

= 100

Fig. 14. Real-time frequency discriminator. (a) System. (b) Circuit simulation results. (c) Incomplete chirp cancellation in case of nonlinear dispersion. (d) Complete chirp cancellation in case of linear dispersion.

all-pass networks with a linear group delay using a threefold cascade repetition of the network of Fig. 8(d) with the two GHz and GHz. incoming test frequencies ns The system outputs two impulses occurring at ns, which are used to deduce the two incoming and . frequencies via the mapping The frequency resolution (distance between the two closest frequencies that may be discriminated) and the operation bandwidth of the system critically depend on the group-delay characteristics of the dispersive structures. Two necessary conditions

required for optimal system performance are the complete cancellation of frequency chirp by the second dispersive structure centered at in order to achieve compression of the pulse to its initial width, and the realization of compression by a second dispersive structure independent of the mixed frequency in order to avoid distortion after frequency translation. These two important conditions are considered in Fig. 14(c) and (d). Fig. 14(c) illustrates the pulse problem, which occurs in the compressive receiver when the dispersive structures exhibit a nonlinear group-delay response, as in [5]. In this case,

GUPTA et al.: GROUP-DELAY ENGINEERED NONCOMMENSURATE TRANSMISSION LINE ALL-PASS NETWORK

the slope of the group-delay function, , is a function of frequency. Therefore, the pulse at the input of the second dispersive structure, after the frequency translation of the mixer connected to the antenna, does not exhibit chirp perfectly opposite to that of the dispersive structure #2, which leads to imperfect chirp cancellation, and therefore, imperfect pulse shape restoration, as shown in Fig. 14(c). In contrast, if a dispersive structure exhibiting a linear group-delay response [e.g., the one employed in Fig. 14(b)] is used, this problem is perfectly solved since the chirp shape is independent of the frequency translation, as illustrated in Fig. 14(d). This example illustrate an application where the linearity of the group delay is of paramount importance in the analog signal-processing system, and further demonstrates the usefulness of the proposed noncommensurate all-pass network system, which allows the design of such responses. Other analog signal-processing systems requiring a linear group delay are real-time Fourier transformers [31] and time lenses [32].

VI. CONCLUSION A group-delay engineered noncommensurate transmission line two-port all-pass network for analog signal-processing applications has been presented, along with an analytical modeling procedure and experimental demonstrations. A computer design approach based on GAs has been proposed to synthesize quasi-arbitrary group-delay responses, i.e., to determine the structural parameters of the individual C-sections of the network. Edge-coupled stripline implementations have been demonstrated with Gaussian, linear, and quadratic group-delay responses, and these results have been validated experimentally. Finally, two analog signal-processing applications based on the proposed dispersive network—a tunable impulse delay line and a real-time frequency discriminator—have been presented. The proposed noncommensurate C-section networks are suitable for analog signal processing of broad bandwidth (a few gigahertz bandwidth) signals, where relatively low group-delay values (up to a few tens of nanoseconds) are required. In narrow bandwidth applications, such as pulse compressive radar [30], delays in the order of microseconds are needed. In such cases, the proposed networks would become excessively large and would suffer of prohibitive losses. A solution to this issue, involving an active feedback loop system, is currently being investigated by some of the authors. Considering that GAs do not necessarily guarantee an optimum design, optimization efforts will be made in the future by introducing additional goals, such as, for instance, minimizing the total length of the structure and the number of C-sections. This will reduce the insertion loss in addition to improving compactness. Moreover, more design flexibility will be introduced by using hybrid edge- and broadside-coupled lines structures, possibly in a multilayer configuration, where nonadjacent line couplings may significantly contribute to the phase response for optimal results.

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APPENDIX A A. Derivation of the C-Section Transfer Functions (1) Consider an ideal lossless, perfectly matched, and perfectly isolated TEM backward-wave coupled-line coupler, shown in Fig. 1(b). The four-port scattering matrix is [26] (14)

where (15a) (15b) and is the voltage coupling coefficient. Prescribing and to model the shorting transmission line at the 3–4 port of the coupler in (14) transforms the four-port coupled-line coupler into a two-port C-section described by the following set of equations: and . These equations lead to the two-port transfer function (16) Finally, substituting (15) into (16), and rearranging the terms, we obtain the C-section transfer function (17) B. Demonstration That the Time-Bandwidth Product of a C-Section Is Constant and Unitary at which the length of the Consider the frequency . The electrical C-section represented in Fig. 1(b) is is length of a transmission line at so that . Therefore, the electrical length of a transmission line as versus frequency may be written as a function of . Using (2) curve with this expression for , the area under the is obtained as follows: between the limits

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Finally, the elements of the per-unit-length capacitance matrix are obtained as a function of the block matrices as (21) and, for the considered case of an homogeneous dielectric medium surrounding the conductors, the inductance matrix is given by [23], [24] (22)

Fig. 15. Coupled-line transmission line network, or equivalently, multiconductor transmission line (cross-sectional view) in stripline technology.

Thus, the area under the curve of a C-section is independent of the coupling coefficient (and thus, ) and is always equal to unity.

where is the capacitance matrix without dielectric, which shows that may be computed directly from . The problem is now to determine in (18). For the stripline structures considered in this work, consider Fig. 15(b), which represents two infinitely long and thin th and th filaments located midway between the ground planes separated by the discreated by the th filament, carrying tance . The potential a per-unit-length charge of 1 (C/m), on the th filament, is given by [23], [25]

C. Determination of the Capacitance and Inductance Matrices coupled-line stripline structure shown in Consider the Fig. 15(a), which may also be regarded as a multiconductor transmission line, embedded in a homogenous dielectric of thickness of dielectric constant . The lines are assumed to have zero thickness, infinite conductivity, a width , and to be infinitely long in the longitudinal direction. To compute the capacitance matrix for this structure, the MoM with the point-matching technique is applied, following [23]. This leads to a relationship between the total per-unit-length charge on the th conductor due to all the line voltages, which may be expressed in matrix form as . For this computation, each line is divided into segments, as shown in Fig. 15(a), and the auxiliary matrix

where

and (23)

and where (24) Once all the potentials ’s have been computed for a given stripline configuration using (23) and (24), the final capacitance and inductance matrices are readily computed using (21) and (22).

(18) D. Conversion Between the -Port Coupled-Line Structure and the Two-Port All-Pass Network is invoked, where is the potential at the center of the th segment due to a constant charge distribution of unit value (1 C/m ) over the th segment, which may or may not be on the same conductor. The matrix can be rewritten in terms of block as matrices

(19) where the block matrix entries in

are given by

(20)

-port network shown in Fig. 3(a) and 4(a) Consider the given by (7) and (11), respecwith the scattering matrix tively. This matrix relates the reflected wave and transmitted wave of the th port as

GUPTA et al.: GROUP-DELAY ENGINEERED NONCOMMENSURATE TRANSMISSION LINE ALL-PASS NETWORK

(25)

have been rearranged so as to isolate where the matrix terms the first and last ports. This equation can be split up in two matrix equations as (26a)

(26b) where and are the sub-matrices of indicated in (25). -port network can now be converted into a two-port The network by introducing the end connections shown in Fig. 3(b) and 4(b). Specifically, the th port (except the first and the th port) is connected to the th port using a short transmission line section so that (27) where is the 2 2 scattering matrix of a transmission line of length (gapwidth) and width . The scattering matrix may be obtained from the transmission matrix given by

where is the impedance of the striplines of width substituting (27) in (26), we obtain

. Next,

(28) Finally, (29) where scattering matrix is thus

. The final two-port

(30) REFERENCES [1] “U.S. frequency allocation chart as of October 2003,” Nat. Telecommun. Inform. Admin., Boulder, CO, Oct. 2003. [Online]. Available: http://www.ntia.doc.gov/osmhome/allochrt.pdf [2] M. Lewis, “SAW and optical signal processing,” in Proc. IEEE Ultrason. Symp., Rotterdam, The Netherlands, Sep. 2005, pp. 800–809.

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[3] S. Gupta, S. Abielmona, and C. Caloz, “Microwave analog real-time spectrum analyzer (RTSA) based on the spatial-spectral decomposition property of leaky-wave structures,” IEEE Trans. Microw. Theory Tech., vol. 57, no. 12, pp. 2989–2999, Dec. 2009. [4] S. Abielmona, S. Gupta, and C. Caloz, “Experimental demonstration and characterization of a tunable CRLH delay line system for impulse/ continuous wave,” IEEE Antennas Wireless Propag. Lett., vol. 17, no. 12, pp. 864–866, Dec. 2007. [5] S. Abielmona, S. Gupta, and C. Caloz, “Compressive receiver using a CRLH-based dispersive delay line for analog signal processing,” IEEE Trans. Microw. Theory Tech., vol. 57, no. 11, pp. 2617–2618, Nov. 2009. [6] C. Campbell, Surface Acoustic Wave Devices and Their Signal Processing Applications. New York: Academic, 1989. [7] G. P. Agarwal, Nonlinear Fiber Optics. New York: Academic, 2005. [8] V. S. Dolat and R. C. Williamson, “A continuouslty variable delay-line system,” in Proc. IEEE Ultrason. Symp., Annapolis, MD, Sep. 1976, pp. 419–423. [9] W. S. Ishak, “Magnetostatic wave technology: A review,” Proc. IEEE, vol. 76, no. 2, pp. 171–187, Feb. 1998. [10] M. J. Lancaster, Passive Microwave Device Applications of High-Temperature Superconductors, 1st ed. Cambridge, U.K.: Cambridge Univ. Press, 2006. [11] R. S. Withers, A. C. Anderson, P. V. Wright, and S. A. Reible, “Superconductive tapped delay lines for microwave analog signal processing,” IEEE Trans. Magn., vol. MAG-19, no. 3, pp. 480–484, Mar. 1983. [12] M. A. G. Laso, T. Lopetegi, M. J. Erro, D. Benito, M. J. Garde, M. A. Muriel, M. Sorolla, and M. Guglielmi, “Real-time spectrum analysis in microstrip technology,” IEEE Trans. Microw. Theory Tech., vol. 51, no. 3, pp. 705–717, Mar. 2003. [13] M. Coulombe and C. Caloz, “Reflection-type artificial dielectric substrate microstrip dispersive delay line (DDL) for analog signal processing,” IEEE Trans. Microw. Theory Tech., vol. 57, no. 7, pp. 1714–1723, Jul. 2009. [14] G. L. Matthaei, L. Young, and E. M. T. Jones, Microwave Filters, Impedance Matching Networks and Coupling Structures. New York: McGraw-Hill, 1965. [15] E. G. Cristal, “Analysis and exact design of cascaded commensurate transmission-line C-section all-pass networks,” IEEE Trans. Microw. Theory Tech., vol. MTT-14, no. 6, pp. 285–291, Jun. 1966. [16] V. P. Meschanov, I. V. Metelnikova, V. D. Tupikin, and G. G. Chumaevskaya, “A new structure of microwave ultrawide-band differential phase shifter,” IEEE Trans. Microw. Theory Tech., vol. 42, no. 5, pp. 762–765, May 1994. [17] J. L. Ramos Quirarte and J. P. Starski, “Synthesis of Schiffman phase shifters,” IEEE Trans. Microw. Theory Tech., vol. 39, no. 11, pp. 1885–1889, Nov. 1991. [18] T.-C. Mu, H. Ogawa, and T. Itoh, “Characteristics of multiconductor, asymmetric, slow-wave microstrip transmission lines,” IEEE Trans. Microw. Theory Tech., vol. 34, no. 12, pp. 1471–1477, Dec. 1986. [19] J. S. Abel and J. O. Smith, “Robust design of very high order all pass filters,” in Proc. 9th Int. Digital Audio Effects Conf., Montreal, QC, Canada, Sep. 18–20, 2006, pp. 13–18. [20] R. L. Crane, “All-pass network synthesis,” IEEE Trans. Circuit Theory, vol. 15, no. 4, pp. 474–477, Dec. 1968. [21] H. S. Hewitt, “A computer designed, 720 to 1 microwave compression filter,” IEEE Trans. Microw. Theory Tech., vol. MTT-15, no. 12, pp. 687–694, Dec. 1967. [22] D. M. Pozar, Microwave Engineering. New York: Academic, 2008. [23] P. R. Clayton, Analysis of Multiconductor Transmission Lines, 2nd ed. New York: Wiley, 2008. [24] J. O. Scanlan, “Theory of microwave coupled-line networks,” Proc. IEEE, vol. 68, no. 2, pp. 209–231, Feb. 1980. [25] R. E. Collin, Foundations for Microwave Engineering, 2nd ed. New York: Wiley, 2000. [26] R. K. Mongia, I. J. Bahl, P. Bhartia, and J. Hong, RF and Microwave Coupled-Line Circuits, 2nd ed. Norwood, MA: Artech House, 2007. [27] D. E. Goldberg, Genetic Algorithms in Search, Optimization, and Machine Learning. Reading, MA: Addison-Wesley, 1989. [28] H. V. Nguyen and C. Caloz, “Composite right/left-handed delay line pulse position modulation transmitter,” Microw. Wireless Compon. Lett., vol. 18, no. 5, pp. 527–529, Aug. 2008. [29] J. D. Schwartz, I. Arnedo, M. A. G. Laso, T. Lopetegi, J. Azaña, and D. Plant, “An electronic UWB continuously tunable time-delay system with nanosecond delays,” IEEE Microw. Wireless Compon. Lett., vol. 18, no. 2, pp. 103–105, Feb. 2008.

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[30] M. l. Skolnik, Introduction to Radar Systems, 3rd ed. New York: McGraw-Hill, 2001. [31] M. A. Muriel, J. Azaña, and A. Carballar, “Real-time Fourier transformer based on fiber gratings,” Opt. Lett., vol. 24, no. 1, pp. 1–3, 1999. [32] J. Azaña and L. R. Chen, “General temporal self-imaging phenomena,” J. Opt. Soc. Amer. B, Opt. Phys., vol. 20, pp. 1447–1458, 2003.

Shulabh Gupta (S’09) was born on December 14, 1982, in Etah, India. He received the Bachelors in Technology (B.Tech.) degree in electronics from the Indian School of Mines, Dhanbad, India, in 2004, the Masters of Science (M.S.) degree in telecommunications from INRS-EMT, Université du Quebec, Montréal, QC, Canada, in 2006, and is currently working toward the Doctoral degree at the École Polytechnique of Montréal, Montréal, QC, Canada.. His M.S. thesis research concerned optical signal processing related to the propagation of light in linear and nonlinear optical fibers and fiber Bragg gratings. From December 2009 to May 2010, he was a Visiting Research Fellow with the Tokyo Institute of Technology, Tokyo, Japan, where he was involved with the application of artificial magnetic surfaces for oversized slotted waveguide antennas. His current research interests are traveling-wave antennas, dispersion engineered structures for UWB systems and devices, nonlinear effects, and Fourier optics inspired leaky-wave structures and systems. Mr. Gupta was a recipient of the Young Scientist Award of EMTS Ottawa’07 and URSI-GA, Chicago’08. He was the second finalist in the Most Creative and Original Measurements Setup or Procedure Contest of the 2008 IEEE Microwave Theory and Techniques Society (IEEE MTT-S) International Microwave Symposium (IMS), Atlanta, GA, in 2008.

Armin Parsa (S’02–M’08) received the B.S. degree from the Amirkabir University of Technology, Tehran, Iran, in 1997, the M.S. degree from Tarbiat Modarres University, Tehran, Iran, in 2001, and the Ph.D. degree from Concordia University, Montréal, QC, Canada, in 2008, all in electrical engineering. During his doctoral dissertation, he was involved with the development of a Green’s function for modeling a finite and electrically thick reinforced concrete slab. From May 2008 to May 2010, he was a Post-Doc Research Fellow with the École Polytechnique de Montréal. He is currently a Research Engineer with Rutter Inc., St. John’s, NF, Canada. His main research interests include propagation and scattering of waves, UWB and leaky wave antennas, high-frequency techniques, and computational electromagnetics.

Etienne Perret (S’02–M’06) was born in Albertville, Savoie, France, on October 30, 1979. He received the Eng. Dipl. in electrical engineering from the École Nationale Suprieure d’lectronique, d’lectrotechnique, d’Informatique, d’Hydraulique, et des Tlcommunications, Toulouse, France, in 2002, and the M.Sc. and Ph.D. degrees from the Polytechnic Institute of Toulouse, Toulouse, France, in 2002 and 2005, respectively, all in electrical engineering. From 2005 to 2006, he held a post-doc position with the Institute of Fundamental Electronics (IEF), Orsay, France. Since September 2006, he has been an Assistant Professor of electronic with the Grenoble Institute of Technology, Valence, France. His research activities concern the electromagnetic modeling of passive devices for millimeter and submillimeter-wave applications. His current research interests are in the field of wireless communications, especially RF identification (RFID) with the design and development of antennas for RFID tags. His interests also involve advanced computer-aided design techniques based on the development of an automated co-design synthesis computational approach.

Richard V. Snyder (S’58–M’63–SM’80–F’97– LF’05) received the B.S. degree from Loyola-Marymount University, Los Angeles, CA, the M.S. degree from the University of Southern California, Los Angeles, and the Ph.D. degree from the Polytechnic Institute of New York (PINY), Brooklyn, NY. He is President of RS Microwave, Butler, NJ. He teaches and advises at the New Jersey Institute of Technology (NJIT), Newark, NJ. He is a Visiting Professor with The University of Leeds, Leeds, U.K. He was Chief Engineer for Premier Microwave. He has authored 76 papers and three book chapters. He holds 18 patents. He is a Reviewer for Microwave Journal. His research interests include electromagnetic (EM) simulation, network synthesis, dielectric and suspended resonators, high power notch and bandpass filters, and active filters. Dr. Snyder has served the IEEE North Jersey Section as chairman and 14-year chair of the MTT-AP Chapter. He chaired the IEEE North Jersey EDS and CAS chapters for ten years. He was general chairman for IMS2003, Philadelphia, PA. He was elected to the Administrative Committee (AdCom) in 2004, He is the 2010 president-elect for the IEEE Microwave Theory and Techniques Society (IEEE MTT-S). Within the AdCom, he was chair of the TCC and liaison to the European Microwave Association (EuMA). From 2007 to 2010, he was an IEEE MTT-S Distinguished Lecturer, as well as a member of the Speakers Bureau. He served seven years as chair of MTT-8 and continues in MTT-8/TPC work. He is a member of the American Physical Society, the American Association for the Advancement of Science (AAAS), and the New York Academy of Science. He is an associate editor for the IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, responsible for most of the filter papers submitted. He is also a reviewer for IEEE MTT-S publications. He was the two-time recipient of the Region 1 Award. In January 2000, he was the recipient of the IEEE Millennium Medal.

Robert J. Wenzel (S’61–M’62–SM’82–F’83– LF’05) received the B.S. degree in electrical engineering from Marquette University, Milwaukee, WI, in 1961, and the M.S. degree in electrical engineering from the Massachusetts Institute of Technology (MIT), Cambridge, in 1962. In 1962, he joined Bendix Research Laboratories, Southfield, MI, where he was involved in the design of microwave filters based on classic insertion loss synthesis methods. This research led to published papers giving exact synthesis procedures for a broad class of transmission line filters including combline and interdigital filters and general design methods for microwave contiguous band diplexers and multiplexers. In 1970, he joined Wavecom, Northridge, CA, where he engaged in the design and development of microwave filters and networks for specialized high-reliability aircraft and spacecraft applications. While with Wavecom, he developed exact synthesis methods for cross-coupled filters with arbitrary amplitude and time-delay characteristics. In 1975, he co-founded Wenzel/Erlinger Associates Inc. The consulting firm’s design capability provided theoretical and practical design experience and sophisticated computer programs for exact synthesis and optimization of microwave networks. He has worked with over 50 companies on all types of passive components. He has made significant contributions to the design of waveguide and coaxial contiguous multiplexers and to the theory of both narrowband and wideband filters with arbitrary amplitude and time-delay response (cross-coupled structures). He has also taught graduate courses in circuit theory and microwave networks at California State University and the University of California at Los Angeles (UCLA). Since 2003, he has been semiretired, but he does consult for a select group of clients and continues to be active in the microwave community. Dr. Wenzel is a member of Sigma XI, Eta Kappa Nu, and Tau Beta Pi. He has lectured at many IEEE chapter meetings and at IEEE Microwave Theory and Techniques Society (IEEE MTT-S) International Microwave Symposium (IMS) gatherings. From 1974 to 1995, he was a principle lecturer at over 50 short courses on microwave circuit design in both the US and Europe. He was the recipient of the 1967 Microwave Prize of the IEEE MTT-S Society. He has served for many years on the Editorial Board of the IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES and has served on numerous IEEE MTT-S IMS Technical Program Committees. He was the recipient of the 2007 Microwave Career Award of the IEEE MTT-S.

GUPTA et al.: GROUP-DELAY ENGINEERED NONCOMMENSURATE TRANSMISSION LINE ALL-PASS NETWORK

Christophe Caloz (S’00–M’03–SM’06–F’10) received the Diplôme d’Ingénieur en Électricité and Ph.D. degree from the École Polytechnique Fédérale de Lausanne (EPFL), Lausanne, Switzerland, in 1995 and 2000, respectively. From 2001 to 2004, he was a Postdoctoral Research Engineer with the Microwave Electronics Laboratory, University of California at Los Angeles (UCLA). In June 2004, he joined the École Polytechnique of Montréal, where he is currently a Full Professor, a member of the Poly-Grames Microwave Research Center, and the Holder of a Canada Research Chair (CRC). He has authored or coauthored over 360 technical conference, letter, and journal papers, three books, and eight book chapters. He holds several patents. He is a member of the Editorial Board of the International Journal of

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Numerical Modelling (IJNM), the International Journal of RF and Microwave Computer-Aided Engineering (RFMiCAE), the International Journal of Antennas and Propagation (IJAP), and Metamaterials of the Metamorphose Network of Excellence. His research interests include all fields of theoretical, computational, and technological electromagnetics engineering with a strong emphasis on emergent and multidisciplinary topics. Dr. Caloz is a member of the IEEE Microwave Theory and Techniques Society (IEEE MTT-S) Technical Committees MTT-15 (Microwave Field Theory) and MTT-25 (RF Nanotechnology). He is a speaker of the MTT-15 Speaker Bureau and the chair of Commission D (Electronics and Photonics) of the Canadian Union de Radio Science Internationale (URSI). He was the recipient of several awards including UCLA’s 2004 Chancellors Award for post-doctoral research and the 2007 IEEE MTT-S Outstanding Young Engineer Award.

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Flip-Chip-Based Multichip Module for Low Phase-Noise V -Band Frequency Generation Li-Han Hsu, Dan Kuylenstierna, Student Member, IEEE, Rumen Kozhuharov, Marcus Gavell, Camilla Kärnfelt, Member, IEEE, Wee-Chin Lim, Herbert Zirath, Senior Member, IEEE, and Edward Yi Chang, Senior Member, IEEE

Abstract—This paper reports on a flip-chip (FC)-based multichip module (MCM) for low phase-noise (PN) -band frequency generation. A high-performance 8 GaAs metamorphic high-electron mobility transistor monolithic microwave integrated circuit (MMIC) multiplier and a low PN 7-GHz GaAs InGaP heterojunction bipolar transistor (HBT) MMIC oscillator were used in the module. The microstrip MMICs were FC bonded to an Al2 O3 carrier with patterns optimized for low-loss transitions. The FC-based module was experimentally characterized to have a PN of 88 dBc/Hz @ 100-kHz offset and 112 dBc/Hz @ 1-MHz offset with an output power of 11 dBm. For comparison, the MMICs were also FC bonded as individual chips and the performance was compared with the bare dies without FC bonding. It was verified that the FC bonding has no detrimental effect on the MMIC performance. The tests revealed that the FC module provided improved performance. To our best knowledge, this is the first FC-based module for millimeter-wave frequency generation. The module also presents one of the best PN reported for millimeter-wave frequency sources. Index Terms—Flip-chip (FC), frequency generation, interconnection, millimeter wave, monolithic microwave integrated circuit (MMIC), multichip module (MCM), multiplier, oscillator, phase noise (PN), -band. Manuscript received July 27, 2009; revised May 10, 2010; accepted June 16, 2010. Date of publication August 03, 2010; date of current version September 10, 2010. This work was supported by the Swedish Agency of Innovation Systems (VINNOVA), Chalmers University of Technology, Ericsson AB, Sivers IMA AB, Krisberedskapsmyndigheten (KBM), Försvarets materielverk (FMV), and by the National Science Council of Taiwan and Ministry of Economic Affairs, Taiwan under Contract NSC 96-2752-E-009-001-PAE and Contract NSC 95-EC-17-A-05-S1-020. L.-H. Hsu is with the Department of Materials Science and Engineering, National Chiao Tung University, Hsinchu 300, Taiwan, and also with the Microwave Electronics Laboratory, Department of Microtechnology and Nanoscience, MC2, Chalmers University of Technology, Göteborg SE-412 96, Sweden (e-mail: [email protected]; [email protected]). D. Kuylenstierna, R. Kozhuharov, and H. Zirath are with the Gigahertz Centre, Microwave Electronics Laboratory, Department of Microtechnology and Nanoscience, MC2, Chalmers University of Technology, Göteborg SE-412 96, Sweden (e-mail: [email protected]; [email protected]; [email protected]). M. Gavell is with the the Microwave Electronics Laboratory, Chalmers University of Technology, Göteborg SE-412 96, Sweden (e-mail: marcus. [email protected]). C. Kärnfelt was with the Gigahertz Centre, Microwave Electronics Laboratory, Chalmers University of Technology, Göteborg SE-412 96, Sweden. She is now with the Microwave Départment, Télécom Bretagne, Brest CS 83818, France (e-mail: [email protected]). W.-C. Lim and E. Y. Chang are with the Department of Materials Science and Engineering, National Chiao Tung University, Hsinchu 300, Taiwan (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2010.2057135

I. INTRODUCTION

L

OW phase-noise (PN) millimeter-wave frequency generation is a critical issue for future multigigabit/second wireless communication systems. The millimeter-wave frequency bands are capable of carrying high data rates thanks to the large amount of bandwidth available, e.g., the license-free industrial, scientific, and medical (ISM) bands around 60 GHz [1], or the recently allocated -band (71–76 and 81–86 GHz) [2]. Further increased data rates may be reached with spectral efficient modulation formats, e.g., higher order quadrature amplitude modulation (QAM) [2]. However, the spectral-efficient modulation also puts stringent requirements on signal purity, i.e., low PN, which is challenging at millimeter-wave frequencies. One solution could be to operate the local oscillator (LO) at a lower frequency and use frequency multipliers [3] to reach the target frequency. It is believed that the overall PN will be lower with this approach as the factor of the resonant tank in the oscillator is reduced with increased frequency [4]. The use of frequency multipliers to create millimeter-wave signals also decrease or even totally diminish the need of frequency dividers for phase locking. Although it is possible to design single-chip solutions where the oscillator and multiplier are integrated on the same monolithic microwave integrated circuit (MMIC), it may be advantageous to address a multichip module (MCM) [5]–[7] approach enabling higher flexibility in choice of technology for each chip. However, MCM packaging at millimeter-wave frequencies is also challenging, the interconnections between the MMIC chips and the MCM carrier may decay the assembly performance, e.g., conventional bond-wires give a significant contribution to the parasitic inductance, and thus, induce unwanted effects at millimeter-wave frequencies [8]. In this respect, flip-chip (FC) interconnection has been regarded as a promising packaging technology for cost-effective module assembly in millimeter-wave systems due to its shorter interconnect length, higher throughput, and smaller package size [9]–[16]. Furthermore, considering large-scale production with small chip ( 5 5 mm ) and pad ( 1 1 mm ) size and good wafer-bumping yield, the FC is cheaper than bond-wire [16]. For millimeter-wave applications, the regular chip and pad size is normally smaller than this range. For these reasons, the FC-based multichip module (FC-MCM) is considered as the most promising packaging scheme for millimeter-wave wireless applications.

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Fig. 1. Block diagram of the V -band frequency source realized in this study.

Fig. 3. Illustrations of the important parameters for the FC interconnect.

Fig. 2. Simulated FC interconnect structure (single transition).

In this paper, we report on an FC-MCM for -band frequency generation. Fig. 1 illustrates the block diagram of the -band frequency source realized in this study. The module consists of the high-performance -band 8 metamorphic high-electron mobility transistor (mHEMT) MMIC multiplier reported in [3] and the 7-GHz low PN cross-coupled InGaP HBT MMIC oscillator reported in [17]. This paper is organized as follows. In Section II, the optimum FC design by electromagnetic (EM) simulation will be presented and discussed. In Section III, the in-house process flow of FC assembly will be presented. Sections IV and V present the measurement setups and measurement results for the MMIC circuits, respectively. Finally, this work is concluded in Section VI. II. DESIGN AND OPTIMIZATION OF THE FC TRANSITIONS In this work, the oscillator and 8 multiplier MMICs were designed with microstrip (MS) transmission lines as most of the commercial available MMICs. However, most of the reported FC studies have been made using coplanar waveguide (CPW) MMICs [9]–[14], which is considered to be more compatible with FC technology. Hence, the FC structure design for MS MMICs needs to be investigated. The design and optimization of the interconnect structure was carried out by using the simulation tool, Ansoft High Frequency Simulation Software (HFSS) 11 for the 3-D EM field analysis, which predicts a reliable -parameter of the millimeter-wave interconnect structures [18]–[20]. Fig. 2 shows the simulated FC interconnect structure with the MS transmission line on the GaAs chip and CPW transmission line on the Al O carrier. The important parameters of the FC design such as bump diameter, bump height, metal pad overlap, and compensation have been discussed and investigated in [9], [11], and [12]. Among these parameters, the compensation, reducing the excess parasitic capacitance at the vertical bump transition by adding an

inductive counterpart, is the most effective way to optimize the interconnect performances since extra process steps and fabrication cost are not needed [11]. Two approaches, one with staggered bumps and the other one employs a high impedance-line section, were proposed to reduce the return loss of the FC interconnect [9], [11]. The staggered-bumps approach needs an additional chip area and requires customized chip design. Therefore, the approach of employing a high-impedance line section before the bump transitions is more advantageous. During the EM simulation, the bump dimensions and metal pad overlap were fixed by the fabrication process. The diameter of the bump was 50 m, the bump height was 40 m, and the metal pad overlap was 70 m. The center-to-center distance between signal and ground bumps was 150 m. The illustrations of these parameters are indicated in Fig. 3. Figs. 4 and 5 ) and insertion loss ( ), show the simulated return loss ( respectively, of the FC interconnect with different compensation widths. As can be seen, the thinner the high-impedance line compensation, the better the interconnect performance. From Fig. 4, the return loss was improved about 3 dB per transition at 60 GHz compared to the structure without compensation. Besides, the insertion loss was about 0.5 dB per transition at 60 GHz after optimization (Fig. 5). The final dimensions of the compensation line were 30 m in width and 50 m in length, which is acceptable for commercial low-cost film mask processes. Table I shows the parameters of the optimized FC design. III. FABRICATION OF THE FC-BASED MODULES One of the advantages with MCMs compared to highly integrated single chips is the flexibility to adapt technology for the individual chip functions; in a single-chip solution, the technology is a tradeoff between the different chip functions. The -band LO module reported in this work is assembled from a low-PN 7-GHz fixed-frequency cross-coupled oscillator designed and implemented in a GaAs InGaP HBT [17] process and a 8 GaAs mHEMT multiplier chain optimized for input frequency in the range of 6.5–8 GHz [3]. The InGaP HBT process

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Fig. 4. Simulated return loss (S 11) of the FC interconnect (single transition) with different compensation widths. Fig. 6. Process flow of the Al O carrier for FC assembly.

[4]. The cross-coupled topology is chosen for its relatively good PN properties and ease of startup [21]. To simplify the bias scheme, a fixed-frequency oscillator is used instead of a voltagecontrolled oscillator (VCO) as the major goal is to demonstrate the concept of building practice providing a low PN at -band. A. Process Technology for the Al O Carrier

Fig. 5. Simulated insertion loss (S 21) of the FC interconnect (single transition) with different compensation widths.

TABLE I PARAMETERS OF THE OPTIMIZED FC DESIGN

is an excellent choice for low PN oscillators thanks to the good low-frequency noise properties and the high breakdown voltage

The Al O carrier used for FC assembly of the MMICs was in-house fabricated in the Compound Semiconductor Laboratory (CSDLab), National Chiao Tung University (NCTU), Hsinchu, Taiwan [15]. Alumina (Al O ) was chosen as the packaging carrier because of its good electrical charand acteristics for high-frequency applications ( ). Moreover, Al O has a thermal expansion ppm/ C) very close to that of GaAs coefficient ( ( ppm/ C), which can minimize potential thermal stress between the MMICs and the carrier, e.g., caused by temperature variations. The thickness of the Al O carrier used in this study is about 254 m (10 mil). Fig. 6 shows the process flow of the Al O carrier used for FC assemblies. Gold (Au) metal, formed by cyanide-based electroplating, was used as the metallization of the transmission line and the vertical transition bumps. Firstly, Ti and gold metal were in-situ deposited using an E-gun evaporator onto the Al O carrier with the thickness of 300 and 500 Å to form a continuous seed layers for gold electroplating. Ti was used as an adhesion layer. A thin photoresist (PR) was then patterned on the carrier for electroplating of the CPW circuits. After the electroplating of the gold circuits, the thin PR was removed. The wafer was then covered by a thick PR patterned to define the positions of the gold bumps that were formed by electroplating. By controlling the electroplating current density and time, the required bump height was achieved. The gold-bump height and diameter in this study were 40 and 50 m, respectively. The seed layers were then removed with a KI/I solution for the removal of

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Fig. 7. (a) Cross-sectional SEM image of the thick PR profile before gold bump electroplating. (b) SEM image of the electroplated gold circuits and bumps on the Al O carrier.

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Fig. 8. (a) Chip photograph (right-hand side) and (b) circuit schematic of the cross-coupled HBT oscillator.

gold metal and HF dilute solution for the removal of the Ti metal. Fig. 7 shows the scanning electron microscope (SEM) image of the thick PR profile and the electroplated gold circuits and bumps on the Al O carrier. B. Chip Assembly Process The MMIC oscillator and the 8 multiplier chips were FC bonded onto the Al O carrier by the Au-to-Au thermo-compression method using a PP-5 TSV assembly machine from JFP Microtechnic, Marcoussis, France. After optimization, the temperature of the work holder was set to 300 C and the bonding force was adjusted to 20 grams per bump, which was maintained for a bonding time of 60 s. As reference to the FC bonded module, the oscillator and multiplier were also attached using silver epoxy on a piece of brass and connected with conventional bond-wire technology. For further comparison, the individual oscillator and multiplier MMICs were also FC bonded and compared with the bare chip performances.

Fig. 9. Photograph of the FC bonded HBT oscillator.

IV. CIRCUIT CHARACTERIZATION All the measurements were performed in the Microwave Electronics Laboratory (MEL), Department of Microtechnology and Nanoscience (MC2), Chalmers University of Technology, Göteborg, Sweden. The output power, oscillation frequency, and PN of the oscillators were measured using an HP8565EC spectrum analyzer. For characterization of the 8 multiplier, an HP83650B frequency synthesizer was used as the input signal source and the HP8565EC spectrum analyzer complemented with HP11974V -band external mixers was used for measuring output power, PN, and oscillation frequency. -parameter measurements of the 8 multiplier were also carried out using an Agilent precision network analyzer (PNA) E8361A. For comparison, the MMIC chips were measured before and after FC assembly. The FC mounted -band LO modules were characterized using the same spectrum analyzer and mixers as used for the 8 multiplier. V. MEASUREMENT RESULTS AND DISCUSSIONS A. 7-GHz Cross-Coupled HBT Oscillators Fig. 8 shows the chip photograph and circuit schematic of the cross-coupled HBT oscillator. There are two circuits in the same chip. The circuit on the right side is the fixed-frequency oscillator used in this study. Since the two circuits were not sepa-

Fig. 10. Cross-sectional view of the simulated resonant tank of the oscillator taking the FC effect into account.

rated by dicing, the circuit on the left side was used as additional support by designing dummy bumps underneath its pads. The total chip area is 1.8 2 mm . Fig. 9 shows the photograph of the FC bonded HBT oscillator. To investigate the influence of the FC mounting, an EM simulation was carried out in ADS Momentum. Fig. 10 shows a cross-sectional view of the simulated resonant tank of the oscillator with the effect from the FC carrier taken into account. A 40- m-thick layer of air layer and a 254- m-thick Al O layer were added to represent the FC carrier in the Momentum substrate definition. Fig. 11 versus shows the simulated phase of the input impedance frequency before and after FC assembly. From the phase-frequency curve in Fig. 11, the factor can be calculated as (1) The calculated factors before and after the FC are estimated to be 28 and 33, respectively, i.e., 18% improvement in factor

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Fig. 11. Simulated phase of the input impedance (Z ) of the oscillator versus frequency before and after FC assembly.

Fig. 13. Measured output power and frequency of the oscillator as function of the base voltage (V bb) before and after FC.

Fig. 12. Measured collector current of the oscillator before and after FC assembly. The collector bias voltage is V cc = 8 V. Fig. 14. Measured and simulated PN of the oscillator before and after FC assembly. The collector bias voltage is V cc = 8 V.

of the resonant tank after FC assembly. In both cases, the resonant-frequency was 7.2 GHz, the shift in resonant frequency due to Al O is negligible. As seen in Fig. 8, the cross-coupled oscillator has a balanced output. The characterization of the circuit was accomplished by measuring one of the outputs, while the other was terminated in a 50- load. Both outputs were also externally attenuated 3 dB to reduce the loading of the oscillator. Fig. 12 shows the meaversus sured dc current consumption of the oscillator, i.e., at V, before and after FC assembly. After the FC, the current consumption was lower. Although the reduction was marginally within the range of the measurement accuracy, a slight reduction could be expected due to the improved tank . Fig. 13 shows the measured output power and oscillation ). After FC assembly, the frequency versus base voltage ( output power remained the same and the oscillation frequency was shifted as little as 25 MHz (0.35%). To predict the oscillator PN, the -parameters from the Momentum simulation were inserted into the oscillator equivalent circuit and the PN simulated with the harmonic balance tool in Agilent Technologies Advanced Design System (ADS). Fig. 14 shows measured and simulated PN for the flip-chipped oscillator and the probed MMIC oscillator compared to simulations. As

can be seen in Fig. 14, the PN was improved after FC assembly, factor resulting from the mounting probably due to the better effect of the FC. The simulation and measurement results corV. Above V, the simrespond well below ulated results do not agree with the measurements, the reduced PN in simulation is most likely an artifact from model limitations when the oscillator goes into the voltage limited region. After FC assembly, the lowest PN are 112 dBc/Hz @ 100-kHz offset and 128 dBc/Hz @ 1-MHz offset. Compared to the previous publications [22]–[29], this is the lowest PN reported for an FC assembled oscillator. Table II presents the key figures of the FC oscillator in this work compared to FC oscillators in the open literature. To be able to compare PN of oscillators operating at different frequencies, the results are bench-marked after at 1-GHz and 100-kHz offset, cala normalized PN culated using Leeson’s equation [30]

(2)

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TABLE II FC OSCILLATOR IN THIS WORK COMPARED TO FC OSCILLATORS IN OPEN LITERATURE

where is the oscillation frequency in gigahertz and is PN measured at an offset frequency (in kilohertz). The figure-of-merit (FOM) resembles the conventional oscillator FOM [30] apart from the fact that it does not include the power consumption, which is intentionally omitted as it mixes up two parameters into the same FOM. The dc power consump(in tion of the oscillator in this work is milliwatts), which would yield a FOM of 187 using the definition in [31], which is very competitive. However, it is better to present PN and power consumption individually. The requirements on PN must first be fulfilled. It must then be verified that the power consumption is not too high for the application in mind. Despite normalization in terms of oscillation and offset frequency, the comparison in Table II has limitations, e.g., it does not differ between fixed-frequency oscillators and VCOs. It is reasonable to question whether the good result is reached for our FC demonstrator (see Table II), thanks to the fact of using a fixed-frequency oscillator instead of a MMIC VCO. Most likely, a similar demonstrator based on a VCO would have about 6–8-dB higher PN, the difference between a MMIC oscillator and a VCO [17]. In this regard, our demonstrator would still be well placed in the comparison, none of the VCOs in Table II achieves PN better than this range. Another interesting aspect worth mentioning in the discussion of Table II is that most of the cited works are using high- passives on the FC motherboard, while this work demonstrates the FC of a bare-die MMIC oscillator so it is easy to see that FC assembly does not degrade the PN (see Fig. 14). It should be mentioned that data compared in this work are measured with the HP8565EC spectrum analyzer, the MMIC oscillator was also measured using a dedicated PN measurement system Agilent 5500A with better noise floor. A PN as low as 117 dBc/Hz at 100 kHz off-set was then reached [17]. However, the Agilent 5500A system cannot be used at -band frequencies. For this reason, we refer to the result from the spectrum analyzer in order to have a fair comparison to the -band measurements.

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-Band 8 mHEMT Multiplier Fig. 15 shows the circuit schematic of the mHEMT multiplier by eight ( 8). It includes an input matching common-gate stage followed by a quadruper ( 4), a feedback amplifier, a doubler ( 2), and a buffer amplifier at the output. The topology was chosen for realization of a highly integrated -band LO chain with high output power and good harmonic suppression. The input matching and interstage amplification were designed to occupy minimum chip area [3]. For measurements, the ampliV and V; the fiers were biased at V and quadrupler and doubler were biased at V. Fig. 16 shows a photograph of the 8 multiplier before and after FC assembly. As can be seen, the lower circuit is the 8 multiplier used in this study. Since the circuits were not separated by dicing, the upper circuit (useless part) was used as additional support by designing dummy bumps underneath its pads. The total chip area is 2.8 4.2 mm . To investigate the input and output matching of the multiplier, the -parameter of the 8 multiplier was measured and compared before and after FC assembly. As can be seen in Fig. 17, in the frequency range of 7–12 GHz, the input matching is better than 15 dB, which is an improvement compared to the data was imbefore the FC. Similarly, the output return loss proved 5–10 dB (from 53 to 67 GHz) after FC assembly (see Fig. 18). The significant improvement is due to the flipping onto the CPW line, which ameliorates the matching to probes a lot at higher frequencies. In our later designs, the output RF pads on the chip were simulated, optimized, and modified to a short part of the CPW with a couple of via-holes to each ground plane (for frequencies higher than 50 GHz). There are many publications dedicated to a similar mollified RF pad. In conclusion, we would define the improvement as a consequence of connection to the CPW and the improvement according to the graph, which demonstrates the influence of compensation at high frequencies. After the -parameter measurements, the output power characteristics as function of input power and frequency were investigated. Fig. 19 presents the comparison of the measured output power versus input power before and after FC assembly. The input frequency was set at 7 GHz instead of 8.1 GHz, where the was obtained according to Fig. 17. The reason for using best 7 GHz is that it is the oscillation frequency of the cross-coupled HBT oscillator that is connected to the input of the 8 multiplier in the -band MCM frequency source. Fig. 19 shows that the output power was essentially unaffected by FC assembly. Only a small shift in the saturation point was detected. After the FC, the saturation occurs at lower input power, probably due to better input and output matching. Under variation of the input fredBm (see Fig. 20), quency with constant input power the peak-output power shifted to lower frequency (from 56 to 54 GHz). An increased bandwidth was also observed, as expected, which is due to the improvement in the output matching (Fig. 18).

B.

C. FC-Based -Band MCM Frequency Source It is now demonstrated that the FC does not have any significant negative effect on either the cross-coupled oscillator MMIC or the 8 multiplier MMIC. The next step is to combine the two into one FC MCM frequency source with hybrid device

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Fig. 15. Circuit schematic of the

Fig. 16. Photographs of the (b) after FC assembly.

28 mHEMT MMIC multiplier.

28 mHEMT MMIC multiplier (a) before and Fig. 18. Measured output return loss S 22 of the FC assembly.

Fig. 17. Measured input return loss S 11 of the FC assembly.

28 multiplier before and after

28 multiplier before and after

technology on the Al O carrier. Meanwhile, a bond-wire connected module was also realized for comparison. Fig. 21 shows the photographs of the FC and bond-wire assembled -band LO MCMs. For the FC scheme, there are three transitions in the module, which are: 1) oscillator output to CPW on Al O (7 GHz); 2) CPW on Al O to 8 input (7 GHz); and 3) 8 output to CPW on Al O (55 GHz). For the bond-wire scheme, the measurements were carried out by probing directly on the MMIC circuits, which means that there is only one bond-wire transition from the oscillator output to the 8 input (7 GHz) in the module. In Fig. 13, the output power of the oscillator is around 7 dBm. Moreover, the loss from the oscillator output to the 8 input at 7 GHz can almost be ignored for both FC and bond-wire schemes since the output power of the oscillator is

2

Fig. 19. Measured output power of the 8 multiplier versus input power before and after FC assembly (Input frequency = 7 GHz).

6 dBm and the loss of about 1 dB due to the chip-to-chip transmission still keeps the 8 in compression at 0 dBm, as shown in Fig. 19. The bond-wire version, as a result, was expected to have higher output power at the 8 output because, in this case, the transition from the MMIC to Al O carrier was not included in the measurement. Fig. 22 presents a comparison of the measured output power and oscillation frequency versus oscil) of the FC and bond-wire assembled LO lator base-voltage ( MCMs. As indicated in Fig. 21(a), the carrier for the FC-based module is prepared for the termination of the nonused output.

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Fig. 22. Measured power and frequency characteristics of the FC and bondwire assembled MCM LO module.

Fig. 20. Measured output power of the 8 multiplier versus frequency before dBm). and after FC assembly (Input power TABLE III SUMMARY OF THE FC AND BOND-WIRE MCM LO MODULES

Fig. 21. Photograph of the: (a) FC and (b) bond-wire assembled V -band LO MCM module.

In principle, this output could be connected to a phase-locked loop (PLL) for phase locking. However, in the measurements, it was terminated in a 50- load preceded by 3-dB attenuation. For the bond-wire module shown in Fig. 21(b), there is no possibility to terminate the nonused output. To ensure that this would not affect the result, the FC-based module was measured both with and without termination and no significant difference was observed in the results. As expected, the bond-wire version had about 1-dBm higher output power compared to the FC version due to the excluded transition at the output port. The best PN V and was measured at an oscillator base–voltage V. The bond-wire version exhibited collector–voltage dBc/Hz @ a PN of 86 dBc/Hz @ 100-kHz offset and 1-MHz offset; while the FC version exhibited a PN of 88 dBc @ 100 kHz and 112 dBc @ 1 MHz. The 2-dB lower PN for the FC mounted version can be explained by the better factor providing lower oscillator PN, as is demonstrated in Section V-A. In Fig. 22, it is seen that the oscillation frequency can be altered 1% with the base voltage, but the signal stability is good V, where the only for a few discrete bias points, e.g., best PN is measured. The sensitivity to the applied base voltage is likely resulting in the fact that the 8 multiplier loads the oscillator output. A buffer amplifier at the output of the oscillator could alleviate this problem.

Table III summarizes the performance of the FC and bondwire LO MCMs. The PN obtained for the FC-MCM frequency source is the lowest reported for -band frequency sources in the open literature [32]–[43]. A comparison to other publications is given in Table IV, the results are bench-marked after the normalized PN presented in (2). The power consumption of the multiplier is in the order of 200 mW. Adding the power consumption of the oscillator, the total power consumption is , still below 400 mW, yielding a PN-power FOM which is excellent for a -band frequency source [31]. For applications, the assembled MMIC module has to be packaged into a metal house with coaxial connectors or waveguide interfaces, which might cause instability of the output signal due to the cavity resonances. For a rectangular cavity, as shown in Fig. 23, the cavity resonances could happen in the following frequencies [44]: (3) where is the material permittivity, is the material permeand are integers. Here, the mode ability, and is the dominant mode since it occurs at the lowest frequency of the FC at which a cavity resonance can exist [45]. module and bond-wire module are found to be 43 and 48 GHz, respectively. This means that the resonances could occur if the

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TABLE IV SUMMARY AND COMPARISON OF MILLIMETER-WAVE FREQUENCY SOURCES IN OPEN LITERATURE

Fig. 23. Rectangular cavity with correspondinga; b; and c in (3).

operating frequencies of the modules are higher than 43 and 48 GHz. Due to smaller cavity size, of the bond-wire is higher than that of the FC. However, the bond-wire module excludes the other oscillator output for PLL implementation, which also occupies some additional space and increases the size of the bond-wire module. Moreover, the FC has a smaller footprint than the bond-wire. After considering these issues, we of the FC module would be higher than could expect the that of the bond-wire module.

Unfortunately, if we take the other components such as dc bias, protection circuits, connectors, and waveguide flanges will be further reduced. One solution into consideration, is aligning the MMICs in as narrow a row as possible, which results in higher resonance frequencies. Otherwise, another promising approach is using an absorber material to dampen the resonances [45]. It is worth mentioning that both the oscillator and multiplier chip have two circuits on the same chip. The module size can be reduced significantly if the circuits were separated by dicing. VI. CONCLUSION This work has successfully demonstrated FC assembly of a 7-GHz low PN cross-coupled HBT oscillator and a 8 mHEMT multiplier into an ultra-low PN -band MCM frequency source. It has been a shown that FC bonding is an excellent assembly technology for the implementation of millimeter-wave frequency sources. Compared with the bare-die

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measurements, the FC technology does not have any detrimental effect on the chip performance, neither for oscillators, nor for multipliers. On the contrary, the chip performance was improved. After the FC, the PN of the cross-coupled InGaP HBT oscillator was improved due to an increased factor of the resonant tank. A properly designed FC transition can also act as an additional matching network; an improved input and output matching was obtained for the 8 mHEMT multiplier chain using FC assembly. The FC assembled -band MCM frequency source exhibits a PN of 88 dBc/Hz @ 100-kHz offset and 112 dBc/Hz @ 1-MHz offset. To the authors’ best knowledge, this is the lowest PN ever reported for a -band free-running frequency source. ACKNOWLEDGMENT This research was carried out at the GigaHertz Centre, Chalmers University of Technology, Göteborg, Sweden. The authors would like to thank to C.-T. Wang and S.-P. Tsai, both with the Compound Semiconductor Laboratory, National Chiao-Tung University, Hsinchu, Taiwan, for their help with the Al O carrier fabrication. REFERENCES [1] P. Smulders, “Exploiting the 60 GHz band for local wireless multimedia access: Prospects and future directions,” IEEE Commun. Mag., vol. 40, no. 1, pp. 140–147, Jan. 2002. [2] V. Dyadyuk, J. D. Bunton, J. Pathikulangara, R. Kendall, O. Sevimli, L. Stokes, and D. A. Abbott, “A multigigabit millimeter-wave communication system with improved spectral efficiency,” IEEE Trans. Microw. Theory Tech., vol. 55, no. 12, pp. 2813–2821, Dec. 2007. [3] C. Kärnfelt, R. Kozhuharov, H. Zirath, and I. Angelov, “High-purity 60-GHz-band single-chip 8 multipliers in pHEMT and mHEMT technology,” IEEE Trans. Microw. Theory Tech., vol. 54, no. 6, pp. 2887–2898, Jun. 2006. [4] H. Zirath, R. Kozhuharov, and M. Ferndahl, “Balanced colpitt oscillator MMICs designed for ultra-low phase noise,” IEEE J. Solid-State Circuits, vol. 40, no. 10, pp. 2077–2086, Oct. 2005. [5] K. K. Samanta, D. Stephens, and I. D. Robertson, “60 GHz multichip-module receiver with substrate integrated waveguide antenna and filter,” Electron. Lett., vol. 42, pp. 701–702, Jun. 2006. [6] L. Suthar, V. N. Singh, and A. Kumar, “Design & simulation of MCM technology based MM wave transceiver,” in Int. Recent Adv. Microw. Theory Appl. Conf. , Jaipur, India, Nov. 2008, pp. 533–535, 21–24. [7] J. Heyen and A. F. Jacob, “A novel package approach for multichip modules based on anisotropic conductive adhesives,” in Eur. Gallium Arsenide Other Semicond. Appl. Symp., Oct. 3–4, 2005, pp. 553–556. [8] G. Baumann, H. Richter, A. Baumgärtner, D. Ferling, and R. Heilig, “51 GHz front-end with flip-chip and wire bond interconnections from GaAs MMIC’s to a planar patch antenna,” in IEEE MTT-S Int. Microw. Symp. Dig., Orlando, FL, May 16–20, 1995, vol. 3, pp. 1639–1642. [9] C. L. Wang and R. B. Wu, “Modeling and design for electrical performance of wideband flip-chip transition,” IEEE Trans. Adv. Packag., vol. 26, no. 4, pp. 385–391, Nov. 2003. [10] K. Maruhashi, M. Ito, H. Kusamitsu, Y. Morishita, and K. Ohata, “RF performance of a 77 GHz monolithic CPW amplifier with flip-chip interconnections,” in IEEE MTT-S Int. Microw. Symp. Dig., Baltimore, MD, Jun. 7–12, 1998, vol. 2, pp. 1095–1098. [11] A. Jentzsch and W. Heinrich, “Theory and measurements of flip-chip interconnects for frequencies up to 100 GHz,” IEEE Trans. Microw. Theory Tech., vol. 49, no. 5, pp. 871–878, May 2001. [12] D. Staiculescu, J. Laskar, and E. M. Tentzeris, “Design rule development for microwave flip-chip applications,” IEEE Trans. Microw. Theory Tech., vol. 48, no. 9, pp. 1476–1481, Sep. 2000. [13] Z. Feng, W. Zhang, B. Su, K. C. Gupta, and Y. C. Lee, “RF and mechanical characterization of flip-chip interconnects in CPW circuits with underfill,” IEEE Trans. Microw. Theory Tech., vol. 46, no. 12, pt. 2, pp. 2269–2275, Dec. 1999.

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[14] H. Kusamitsu, Y. Morishita, K. Maruhasi, M. Ito, and K. Ohata, “The flip-chip bump interconnection for millimeter-wave GaAs MMIC,” IEEE Trans. Electron., Packag., Manuf., vol. 22, no. 1, pp. 23–28, Jan. 1999. [15] W. C. Wu, H. T. Hsu, E. Y. Chang, C. S. Lee, C. H. Huang, Y. C. Hu, L. H. Hsu, and Y. C. Lien, “Flip-chip packaged In Al As/InGaAs metamorphic HEMT device for millimeter wave application,” in Proc. CS-MAX, Compound Semicond. Manuf. Expo., Palm Spring, CA, Nov. 2005, pp. 94–97. [16] J. H. Lau, “Cost analysis: Solder bumped flip chip versus wire bonding,” IEEE Trans. Electron., Packag., Manuf., vol. 23, no. 1, pp. 4–11, Jan. 2000. [17] D. Kuylenstierna, H. Zirath, R. Kozuharov, M. Bao, and T. C. Tsai, “Low phase noise MMIC oscillators in InGaP HBT technology,” in Asia–Pacific Microw. Conf., Hong Kong, Dec. 2008, pp. 1–4. [18] Y. K. Song and C. C. Lee, “Flip-chip packaging configuration with coplanar strip lines for millimeter electromagnetic waves,” in 56th Proc. Electron. Compon. Technol. Conf., San Diego, CA, 2006, pp. 1700–1705. [19] N. Jayesh and S. Soora, “Design and optimization of coax-to-microstrip transition and through-hole signal via on multilayer printed circuit boards,” in Eur. Microw. Conf., Munich, Germany, Oct. 9–12, 2007, pp. 134–137. [20] D. Peyrou, P. Pons, A. Nicolas, J.-W. Tao, H. Granier, and R. Plana, “Foturan cap and BCB sealing-ring for RF MEMS packaging applications,” in 1st Eur. Microw. Integr. Circuits Conf., Manchester, U.K., Sep. 10–13, 2006, pp. 456–459. [21] A. Hajimiri and T. H. Lee, “Design issues in CMOS differential LC oscillators,” IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 717–724, May 1999. [22] X. Huo, G.-W. Xiao, P. C. H. Chan, and K. J. Chen, “Silicon-on-organic integration of a 2.4-GHz oscillator using high-Q copper inductors and solder-bumped flip chip technology,” IEEE Trans. Compon. Packag. Technol., vol. 32, no. 1, pp. 191–196, Mar. 2009. [23] K. Stadius and K. Halonen, “Development of 4-GHz flip-chip oscillator module,” in IEEE Int. Circuits Syst. Symp., Kobe, Japan, May 23–26, 2005, vol. 3, pp. 2687–2690. [24] Y. M. Hsin, Y. A. Liu, C. M. Wang, W. K. Huang, and T. J. Yeh, “27 GHz flip-chip assembled pHEMT oscillator,” in Proc. CS-MAX, Compound Semicond. Manuf. Expo., Vancouver, BC, Canada, Apr. 24–27, 2006, pp. 127–129. [25] W. K. Huang, Y. A. Liu, C. M. Wang, Y. M. Hsin, C. Y. Liu, and T. J. Yeh, “Flip-chip assembled GaAs pHEMT Ka-band oscillator,” IEEE Microw. Wireless Compon. Lett., vol. 17, no. 1, pp. 67–69, Jan. 2007. [26] M. Ito, K. Maruhashi, S. Kishimoto, T. Hashiguchi, and K. Ohata, “A 30 GHz-band oscillator coupled with a dielectric resonator using flipchip bonding technique,” in IEEE MTT-S Int. Microw. Symp. Dig., Fort Worth, TX, Jun. 6–11, 2004, vol. 3, pp. 1995–1998. [27] T. Yoshida, T. Deguchi, K. Kawaguchi, and A. Nakagawa, “Ka-band planar Gunn oscillators using flip-chip GaAs Gunn diodes fabricated by boron ion implantation,” in 22nd Annu. Gallium Arsenide Integr. Circuit Symp., Seattle, WA, Nov. 5–8, 2000, pp. 165–168. [28] K. Watanabe, T. Deguchi, and A. Nakagawa, “V -band planar Gunn oscillators and VCOs on AlN substrates using flip-chip bonding technology,” in IEEE MTT-S Int. Microw. Symp. Dig., Anaheim, CA, Jun. 13–19, 1999, vol. 1, pp. 13–16. [29] T. Yoshida, Y. Fukasawa, T. Deguchi, K. Kawaguchi, T. Sugiyama, and A. Nakagawa, “A low-phase-noise 76-GHz planar Gunn oscillator using flip-chip bonding technology,” in Eur. Microw. Conf., Paris, France, Oct. 4–6, 2005, vol. 1. [30] D. B. Leeson, “A simple model of feedback oscillator noise spectrum,” Proc. IEEE, vol. 54, no. 2, pp. 329–330, Feb. 1966. [31] M. Q. Bao, Y. G. Li, and H. Jacobsson, “A 21.5/43-GHz dual-frequency balanced Colpitts VCO in SiGe technology,” IEEE J. SolidState Circuits, vol. 39, no. 8, pp. 1352–1355, Aug. 2004. [32] H. Li and H. M. Rein, “Millimeter-wave VCOs with wide tuning range and low phase noise, fully integrated in a SiGe bipolar production technology,” IEEE J. Solid-State Circuits, vol. 38, no. 2, pp. 184–191, Feb. 2003. [33] A. Kurdoghlian, M. Sokolich, M. Case, M. Micovic, S. Thomas, III, and C. H. Fields, “38 GHz low phase noise CPW monolithic VCOs implemented in manufacturable AlInAs/InGaAs HBT IC technology,” in 22nd Annu. Gallium Arsenide Integr. Circuit Symp., Seattle, WA, Nov. 5–8, 2000, pp. 99–102. [34] D. K. Shaeffer and S. Kudszus, “Performance-optimized microstrip coupled VCOs for 40-GHz and 43-GHz OC-768 optical transmission,” IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 1130–1138, Jul. 2003.

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[35] D. K. Hien, M. Stubs, T. Laneve, C. Glaser, and D. Drolet, “ -band MMIC voltage-controlled oscillators,” in Proc. Asia–Pacific Microw. Conf., Hong Kong, Dec. 2–5, 1997, vol. 2, pp. 545–548. [36] M. S. Heins, D. W. Barlage, M. T. Fresina, D. A. Ahmari, Q. J. Hartmann, G. E. Stillman, and M. Feng, “Low phase noise -band VCOs using InGaP/GaAs HBTs and coplanar waveguide,” in IEEE Radio Freq. Integr. Circuits Symp., Denver, CO, Jun. 8–11, 1997, pp. 215–218. [37] F. Herzel, C. S. Choi, and E. Grass, “Frequency synthesis for 60-GHz OFDM transceivers,” in Eur. Wireless Technol. Conf., Amsterdam, The Netherlands, Oct. 27–28, 2008, pp. 77–80. [38] A. Kanda, T. Hirota, H. Okazaki, and M. Nakamae, “An MMIC chip set for a -band phase-locked local oscillator,” in 17th Annu. IEEE Gallium Arsenide Integr. Symp. Tech. Dig., San Diego, CA, 29 Oct.–1 Nov. 1995, pp. 259–262. [39] T. Kashiwa, T. Ishida, T. Katoh, H. Kurusu, H. Hoshi, and Y. Mitsui, “ -band high-power low phase-noise monolithic oscillators and investigation of low phase-noise performance high drain bias,” IEEE Trans. Microw. Theory Tech., vol. 46, no. 10, pp. 1559–1565, Oct. 1998. [40] P. C. Huang, M. D. Tsai, G. D. Vendelin, H. Wang, C. H. Chen, and C. S. Chang, “A low-power 114-GHz push–push CMOS VCO using source degeneration,” IEEE J. Solid-State Circuits, vol. 42, no. 6, pp. 1230–1239, Jun. 2007. [41] T. Mitomo, R. Fujimoto, N. Ono, R. Tachibana, H. Hoshino, Y. Yoshihara, Y. Tsutsumi, and I. Seto, “A 60-GHz CMOS receiver front-end with frequency synthesizer,” IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 1030–1037, Apr. 2008. [42] H. Wang, K. W. Chang, D. C.-W. Lo, L. T. Tran, J. C. Cowles, T. R. Block, G. S. Dow, A. Oki, D. C. Streit, and B. R. Allen, “A 62-GHz monolithic InP-based HBT VCO,” IEEE Microw. Guided Wave Lett., vol. 5, no. 11, pp. 388–390, Nov. 1995. [43] V. Jain, B. Javid, and P. Heydari, “A 24/77 GHz dual-band BiCMOS frequency synthesizer,” in IEEE Custom Integr. Circuits Conf., San Jose, CA, Sep. 21–24, 2008, pp. 487–490. [44] R. Harrington, Time Harmonic Electromagnetic Fields. New York: McGraw-Hill, 1961, pp. 155–158. [45] P. Dixon, “Cavity-resonance dampening,” IEEE Microw. Mag., vol. 6, no. 2, pp. 74–84, Jun. 2005.

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Rumen Kozhuharov was born in Sofia, Bulgaria. He received B.S. and M.S. degrees in electronic engineering from the Institute of Mechanical and Electrical Engineering, Sofia, Bulgaria, in 1972, and the Ph.D. degree in physics from the Institute of Electronics, Bulgarian Academy of Sciences, Sofia, Bulgaria, in 1977. He was a Research Associate with the Institute of Electronics—Sofia, and has been involved in design and investigation of Gunn diode and field-effect transistor (FET) oscillators. Since 1984, he has been Project Supervisor involved with design and development of transceivers used for environmental tests of radio relay stations. He was also involved in research projects connected with radar stations, radiometers, and satellite reception. In 1998, he became a Senior Research Associate with the Institute of Electronics. He was a Visiting Researcher for a short time with the University “Claude Bernard” (microwave industrial applications), Lyon, France (1981), the Institute of Radiolectronics, Prage, Czech Republic (1987–1989), and with the Chalmers University, Göteborg, Sweden (1996–2000). Since 2000, he has been with the Department of Microtechnology and Nanoscience (MC2), Chalmers University of Technology, where he has been involved with the design and investigation of low-noise hybrid oscillators, stabilized with HTSC resonators, HEMT and HBT MMIC millimeter-wave VCOs and multipliers for high data - and -band front-end receivers rate communication links, and MMIC for radiometers measuring and imaging applications. He has authored or coauthored over 70 papers in international journals and conference proceedings and one book. He holds one patent.

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Marcus Gavell was born in Eskilstuna, Sweden, 1981. He received the M.Sc. degree in electrical engineering from the Chalmers University of Technology, Göteborg, Sweden, in 2005. In 2007, he joined the Department of Microtechnology and Nanoscience, Chalmers University of Technology, following two years as a Consultant, initially involved with electric power distribution with Projektel AB and then as a Verification Engineer with Ericsson AB. His research interests concern millimeter-wave MMIC design and building practice.

Li-Han Hsu was born in Tainan, Taiwan, in 1981. He received the B.S. and M.S. degrees in materials science and engineering from the National Chiao Tung University, Hsinchu, Taiwan, in 2003 and 2005, respectively, and is currently working toward the dual Ph.D. degrees in materials science and engineering at National Chiao Tung University, Hsinchu, Taiwan and in microtechnology and nanoscience at MC2, Chalmers University of Technology, Göteborg, Sweden. His main research interest is millimeter-wave packaging technology including flip-chip interconnects, hot-via interconnects, and integration of -/ -band MCM transceiver modules.

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Dan Kuylenstierna (S’04) was born in Göteborg, Sweden, in 1976. He received the M.Sc. degree in physics and engineering physics and Ph.D. degree in electrical engineering in microtechnology and nanoscience from the Chalmers University of Technology, MC2, Göteborg, Sweden, in 2001 and 2007, respectively. His main scientific interests are frequency generation, MMIC design, packaging technologies, and reconfigurable MMICs. Dr. Kuylenstierna was the recipient of the Second Prize of the Student Paper Award Competition at the 2004 IEEE Microwave Theory and Techniques Society (IEEE MTT-S) International Microwave Symposium (IMS).

Camilla Kärnfelt (M’05) was born in Dragsmark, Sweden, in 1965. She received the M.Sc. degree in engineering physics from the Chalmers University of Technology, Göteborg, Sweden, in 2001. From 1987 to 2001, she was with Ericsson Microwave Systems as a Preproduction Engineer with a specialization in microwave hybrid manufacturing. In September 2001, she joined the startup company Optillion as a Research Engineer. From 2002 to 2007, she was with the Microwave Electronics Laboratory, Chalmers University of Technology, as a Research Engineer. She is currently with the Microwave Départment, Télécom Bretagne, Brest, France. Her research interests concern millimeter-wave MMIC design.

Wee-Chin Lim was born in Johor, Malaysia, in 1986. She received the B.S. degree in materials science from the National University of Malaysia (UKM), Kuala Lumpur, Malaysia, in 2008, and is currently working toward the Master degree’s student in materials science and engineering at the National Chiao Tung University (NCTU), Hsinchu, Taiwan. She is currently a member of the Compound Semiconductor Device Laboratory, National Chiao Tung University (NCTU), Hsinchu, Taiwan.

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Herbert Zirath (S’84–M’86–SM’08) was born in Göteborg, Sweden, on March 20, 1955. He received the M.Sc. and Ph.D. degrees from Chalmers University of Technology, Göteborg, Sweden, in 1980 and 1986, respectively. He is currently a Professor of High Speed Electronics with the Department of Microtechnology and Nanoscience, Chalmers University of Technology. During 2001, he became the Head of the Microwave Electronics Laboratory, Chalmers University of Technology. He currently leads a group of approximately 30 researchers in the area of high-frequency semiconductor devices and circuits. He has authored or coauthored over 220 papers in international journals and conference proceedings and one book. He holds four patents. His main research interests include InP-HEMT devices and circuits, SiC- and GaN-based transistors for high-power applications, device modeling including noise and large-signal models for FET and bipolar devices, and foundry-related monolithic microwave ICs for millimeter-wave applications based on both III–V and silicon devices. He also works part-time with Ericsson AB, Mölndal, Sweden, as a Microwave Circuit Expert.

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Edward Yi Chang (S’85–M’85–SM’04) received the B.S. degree in materials science and engineering from National Tsing Hua University, Hsinchu, Taiwan, in 1977, and the Ph.D. degree in materials science and engineering from the University of Minnesota at Minneapolis–St. Paul, in 1985. From 1985 to 1988, he was with the GaAs Component Group, Unisys Corporation, Eagan, MN. From 1988 to 1992, he was with the Comsat Labs Microelectronic Group. He was involved with GaAs MMIC programs with both groups. In 1992, he was with National Chiao Tung University (NCTU), Hsinchu, Taiwan. In 1994, he helped set up the first GaAs MMIC production line in Taiwan, and in 1995, became the President of Hexawave Inc., Hsinchu, Taiwan. In 1999, he returned to NCTU with a teaching position, where he is currently a Professor with the Department of Materials Science and Engineering. His research interests include new device and process technologies for compound semiconductor RFICs for wireless communication. Dr. Chang is a Senior Member and a Distinguished Lecturer of the IEEE Electronic Device Society.

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A Waveguide to Unenclosed Coplanar Waveguide Transition Theodore Reck, Student Member, IEEE, Robert M. Weikle, Senior Member, IEEE, and N. Scott Barker, Member, IEEE

Abstract—A transition from rectangular waveguide to unenclosed coplanar waveguide (CPW) is designed and tested at -band. Full-wave finite-element analysis is applied to the design and optimization trends are shown for the critical parameters. A stepped-impedance filter suppresses a parasitic mode, which is generated as the circuit emerges from the waveguide block, and a rejection of 20 dB is achieved. A back-to-back structure is used to characterize the performance of the transition and an insertion loss of 1.6 dB from 75 to 100 GHz is measured. Removing line losses, a single transition insertion loss of 0.46 dB is obtained. Index Terms—Coplanar waveguide (CPW), rectangular waveguides, transitions, waveguide filters, waveguide transitions, -band.

I. INTRODUCTION

R

ECTANGULAR waveguide continues to be an important transmission line due to its low loss, simple topology, high power-handing capability, and interconnectability [1]. The primary drawback is that most active circuits rely on planar fabrication processes, and thus a transition between the planar transmission line and waveguide is required. Many transitions have been designed to bridge this gap, but most depend on enclosing the planar circuit in the waveguide block. This simplifies the transition by cutting off any parasitic modes that might be coupled from the waveguide in a reduced height waveguide [2]. While this is attractive from an electromagnetic perspective, this enclosure complicates routing of bias or control lines to the circuit and eliminates the possibility of wafer-probe measurements. An unenclosed circuit has the clear advantage of enabling the connection of many control lines to the device without complicating the routing through the waveguide block, but very few transitions that directly link waveguide to a planar transmission line in an unenclosed structure have been reported. Clearly, a technique that couples from waveguide to an unenclosed transmission line would be useful for monolithic microwave integrated circuits (MMICs), as well as other microwave devices Manuscript received January 28, 2010; accepted June 08, 2010. Date of publication August 16, 2010; date of current version September 10, 2010. This work was supported by the National Science Foundation (NSF) under Grant ECS-0501391. The authors are with the Charles L. Brown Department of Electrical Engineering, University of Virginia, Charlottesville, VA 22903 USA (e-mail: [email protected]; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2010.2058550

that require multiple bond-wires or probing such as RF microelectromechanical systems (RF-MEMS) [3]. The primary approach reported in the literature for coupling to an unenclosed planar transmission line is based on an aperture-coupled patch antenna mounted to the end of the waveguide [4]. Variations on this design have been presented in both microstrip and coplanar waveguides (CPWs) [5], [6]. This approach significantly simplifies the waveguide design and could even permit hermetic sealing between the planar circuit and waveguide. The cost paid is that the fractional bandwidth of the patch antenna is only 7%–12%. If a broadband match is required, transverse -plane probes are the preferred method [7], [8]. Simple and well characterized, this approach can often cover the entire waveguide band. These probes generally couple into a reduced height waveguide to reject any spurious modes, confining the circuit to the interior of the waveguide block. In this paper we take advantage of the wide bandwidth of the transverse -plane probe and create a transition from rectangular waveguide to CPW. By routing the transmission line through a small channel in the waveguide block wall, the bulk of the circuit operates in an unenclosed region. Parasitic modes are rejected by a stepped impedance filter integrated into the ground-plane formed by the waveguide block. Similar structures have been applied to suppress spurious radiation in open-ended waveguide systems [9]. By suppressing the parasitic mode injected as the CPW emerged from the waveguide, the performance of the transition was able to be measured. A back-to-back configuration shows good coverage of the -band with a fractional bandwidth of 33%, defined by a return loss below 15 dB. II. DESIGN Fig. 1 shows the structure of the waveguide to CPW transition. The -plane probe couples to a tightly enclosed CPW mode that is strongly coupled to the walls of the channel. Emerging from the channel injects a parasitic mode into the substrate, which is rejected by a stepped-impedance filter formed by grooves cut into the waveguide block. The following sections detail the design of the CPW transmission line, waveguide probe, and the CPW channel. A. Substrate Dimensions First the substrate and CPW dimensions must be chosen. Since the enclosed section will be connected to the waveguide, the first concern is to ensure that the mode is not coupled to the substrate. To avoid this potential problem, the width of

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TABLE I CPW PARAMETERS (REFER TO FIG. 2)

Fig. 1. Waveguide to unenclosed CPW transition with the top half of the split block shown in the wire frame. The probe, fabricated on 700 m 175 m thick fused quartz, emerges from the waveguide block to the left. Underneath the unenclosed CPW line are the trenches cut into the waveguide block that constitute the parasitic mode filter. The opening above the CPW as the chip passes through the wall of the waveguide is 200 m 200 m.

2

2

Fig. 3. Model used to optimize the waveguide probe design and the enclosed CPW channel with the optimized dimensions labeled. For clarity, the top half of the waveguide block is drawn in wire frame.

C. CPW Channel Tuning Fig. 2. Design of the CPW line. Chosen dimensions are listed in Table I.

the substrate was chosen such that the cutoff frequency of the mode in the substrate was above the band of interest

where the

is the width of the substrate, and to select mode. Quartz was chosen for this design with an . The maximum chip width is determined when GHz, which provides a 700- m-wide substrate. The substrate thickness of 175 m was chosen to make it as thin as possible to reduce coupling between the transmission line and substrate modes, while still being thick enough to be easily handled. B. Transmission Line Design The CPW was designed to be suspended slightly above the ground plane to reduce the effect of the ground plane on the characteristic impedance. This was achieved by supporting the device by the area clamped by the block. The impedance of the CPW line shown in Fig. 2 was designed to be 50 using Ansoft’s High Frequency Structure Simulator (HFSS); the chosen dimensions are given in Table I. The design of the line was verified from measurements with a thru-reflect-line (TRL) calibration [10]. The line was measured to be 47 with an and a line loss of 1.4 dB/cm at 85 GHz.

The height and width of the channel were found by analyzing the impedance of the CPW mode in a tightly enclosed channel. Clearly, we wish to minimize the area of the channel to avoid any spurious radiation, but still maintain the CPW mode. Referring and the to the lower insert in Fig. 3, we varied the width height of the channel and analyzed the impedance seen at Port 2. It is found that the CPW mode was not strongly affected by the dimensions of the channel beyond 200 m for the width and 100 m for the height, as shown in Fig. 4. The height and width were both chosen to be 200 m to provide some margin of error for machining. This results in an impedance inside the channel of 52 , providing a good match to the unenclosed CPW line. D. Waveguide Probe With the substrate, transmission line, and waveguide opening chosen, the waveguide probe could be designed. The model in Fig. 3 is used to optimize the parameters of the waveguide probe shown in the upper insert. To begin the optimization, the 110- m CPW center conductor was simply extended to the center of the waveguide. The substrate was chosen to end 50 m away from the end of the probe to provide for dicing error and the distance between the center of the probe. The waveguide ) was then simulated at various lengths backshort ( around 1 mm, which is at 92.5 GHz, and was found to have the widest bandwidth at 0.9 mm. Next, the length ( ) and width ( ) of the probe head were varied. A width of 200 m was arbitrarily chosen as a starting point for the optimization and was swept from 200 to 600 m.

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Fig. 6. Fig. 4. Impedance of the the enclosed CPW mode through the channel with the geometry shown in the bottom insert of Fig. 3. The width (w ) is varied with the channel height set at 200 m and the height (h ) is varied with the width set at 200 m.

Fig. 5.

S

S

for various widths (w ) of the probe with the length set to 600 m.

Table II WAVEGUIDE PROBE DESIGN PARAMETERS (REFER TO FIG. 3)

for various lengths (l ) of the probe with the width set to 200 m.

Fig. 5 shows that a length of 600 m minimized the return loss to the waveguide port. Finally, was swept from 100 to 400 m and a width of 200 m was found to provide the best of these simulations for between match. Fig. 6 shows the 150–250 m. The length of the channel through the waveguide wall was determined next. To minimize loss through the transition, the length should be as short a possible. The channel also needs to be long enough to avoid potential radiative coupling out of the channel. The length of the CPW channel was swept and it was found that if the length was over 75 m, then radiation through the opening was negligible. Based on this, the channel was chosen to be 550 m, which creates a firm mechanical connection for the device chip in the waveguide and allows for machining tolerances. Simulation shows that this length only adds 0.07 dB of loss to the transition.

Fig. 7. Measurement of the transition in a back-to-back configuration without the substrate mode filter. Resonances are clearly seen at 82.5 and 100 GHz.

III. MEASUREMENTS WITHOUT THE PARASITIC MODE FILTER With the primary components designed, the transition was fabricated and tested without the parasitic mode filter. Dimensions of the probe and channel are listed in Table II and the measurements are shown in Fig. 7. Resonances are clearly visible at 82.5 and 100 GHz. The presence of these resonances is likely a result of the back-to-back configuration. However, the frequencies of the resonances do not correspond to quarter-wavelengths of the CPW mode so this indicates there could be coupling to another mode. To verify this hypothesis, the model was modified to monitor other modes at the CPW port after it emerged from the CPW channel in the waveguide block wall. Along with the expected

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Fig. 9. Stepped-impedance filter design showing the length, depth, and spacing of the two trenches. Not shown is the minimum width of the trenches of 5 mm. A minimum air gap of 50 m between the substrate and ground plane is required to ensure the impedance of the CPW line is not effected. The top half of the waveguide block has been removed for clarity.

Fig. 8. Comparison of the simulated insertion loss into the parasitic mode with no filter, the optimized filter, and the realized filter.

slotline mode, a microstrip mode was also found. Coupling to this parasitic microstrip mode was 11 dB (see Fig. 8) and seemed a likely source of the resonance. Looking at the guided wavelength of this mode at 85 and 100 GHz, we found that the length of the transmission line connecting the two transitions of at 85 GHz and the back-to-back test setup is at 100 GHz. IV. PARASITIC MICROSTRIP MODE FILTER To reduce coupling to this parasitic mode, a steppedimpedance filter was designed to deter the mode from propagating. This classic filter approach lends itself to this problem since the impedance of the parasitic microstrip mode is more dependant on the distance to the ground plane than the CPW mode. In addition, the impedance of the CPW mode can be decoupled almost entirely by lifting the substrate away from the ground plane slightly, as shown in Fig. 2. Thus, the parasitic mode impedance can be changed by cutting trenches under the substrate without altering the CPW mode impedance. Fig. 9 shows a side view of the proposed filter. The parasitic mode filter design begins with investigating the effect of a single trench cut under the fused quartz substrate on the parasitic mode impedance in an effort to increase the impedance of the mode as much as possible. Fig. 10 shows the simulated impedance of the parasitic mode as the width and depth of the trench are increased. At a certain point, increasing the width of the trench had a minimal effect and a width of 5 mm is chosen. A depth of 1 mm was chosen since the depth of milling a trench is limited to an aspect ratio of around 3:1. Once the trench width and depth were specified, the tunable parameters are the length of the trenches and the spacing between them. At first, a single trench placed directly at the point where the CPW emerges from the enclosed section was simulated and the length was varied, as shown in Fig. 11. Trench lengths between 200–500 m resulted in a coupling below 20 dB. However, due to the minimum length being limited by the machining aspect ratio of 3:1, the length of 500 m was chosen for the design.

Fig. 10. Simulated impedance of the parasitic mode as the width and depth of the trench is increased.

With the first trench length found, another trench of the same length was added, producing a structure similar to Fig. 9. The structure was simulated at several distances between the two trenches and the coupling to the parasitic mode is shown in Fig. 12. A trench spacing of 300 m was found to have the best rejection across the band. Finally, the width of the second trench was swept to see if the rejection at the upper end of the band can be improved, but simulation showed that it had minimal effect on the coupling. 700 m was chosen since it showed a slight decrease in the coupling at the upper end of the band. A higher attenuation of the parasitic mode would seem possible with a greater number of sections, but it was found that energy was coupled back into the substrate at each discontinuity in the ground plane so additional sections failed to further reduce the overall coupling. Fig. 9 shows a side view of the parasitic mode filter noting the designed depth and length of the trenches. Machining errors resulted in trench depths of 820 m. The simulated coupling to the parasitic mode through the transition without the filter is compared to the designed and realized filter in Fig. 8. A reduction in coupling to the parasitic microstrip mode of at least 10 dB is achieved across the band. In summary, the design process is as follows. mode cutoff. 1) find substrate dimensions based on

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Fig. 13. Bottom half of the waveguide block with the back-to-back transition mounted. Fig. 11. Simulated coupling to the parasitic mode with a single trench located where the transmission line emerges from the enclosed channel. The width is varied from 100 to 900 m.

Fig. 14. Measurements (solid line) of the back-to-back transition compared to the full wave simulation (dashed line). The simulation does not include the waveguide losses. Fig. 12. Simulated coupling to the parasitic mode where the distance between two 500-m-wide trenches is varied. A distance of 300 m gives the best rejection across the band.

2) Choose CPW lines dimensions. 3) Choose minimum channel height and width to support CPW mode. 4) Optimize probe dimensions. 5) Design parasitic mode filter. V. FABRICATION AND MEASUREMENTS The parasitic mode filter was added to the block measured in Section III with standard milling techniques. The back-to-back transition was fabricated by evaporating 0.6 m of gold onto fused quartz. The substrate was then lapped to 175 m and the devices were diced. The block with the back-to-back chip mounted is shown in Fig. 13. Measurements of the back-to-back transition were taken with an HP 8510 network analyzer and are shown in Fig. 14. An insertion loss of 1.6 dB was achieved from 75 to 100 GHz. The loss of the 4.02 mm of CPW between the transitions was calculated from the measured loss of the line to be 0.56 dB at 85 GHz. Each section of waveguide connecting the transition to the reference planes of the measurement

Fig. 15. Comparison of the loss (1 parasitic mode filter.

0 jS j 0 jS j ) with and without the

added additional loss. This loss was calculated using the perturbation method to be 0.06 dB per port, neglecting the surface roughness of the waveguide [1]. Removing these losses from the

RECK et al.: WAVEGUIDE TO UNENCLOSED CPW TRANSITION

back-to-back measurements, an insertion loss for a single transition of 0.46 dB was achieved. The slight ripple around 101 GHz is due to the parasitic mode resonating, but due to the parasitic mode filter, it has a minimal effect on the performance of the transition. To verify the operation of the parasitic mode filter, the loss across the back-to-back transition is compared with and without the filter in place, as shown in Fig. 15. The loss to the resonance at 82.5 GHz was reduced from 5 to 10.5 dB, and at 100 GHz, the loss was reduced from 6 to 9 dB. VI. CONCLUSION This paper has outlined a design procedure for a waveguide to unenclosed CPW transition utilizing finite-element simulations. Parametric simulations of the structure were run to achieve the best performance within the limitations of the waveguide block and chip fabrication techniques. A stepped-impedance filter enabled the circuit to emerge from the enclosure by rejecting a parasitic microstrip mode that is coupled to the CPW as it emerges from the waveguide block. Loss measurements of the back-toback transition with and without the filter demonstrate the effectiveness of this approach. Back-to-back measurements of the completed design match well with simulation and show an insertion loss 1.6 dB. After removing line losses, an insertion loss of 0.46 dB per transition is achieved. REFERENCES [1] D. M. Pozar, Microwave Engineering, 3rd ed. New York: Wiley, 2005. [2] L. Yoke-Choy and S. Weinreb, “Full band waveguide-to-microstrip probe transitions,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 1999, vol. 4, pp. 1435–1438. [3] T. Reck, R. Weikle, and N. S. Barker, “The development of a MEMS six-port reflectometer calibration standard,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2009, pp. 1313–1319. [4] W. Grabherr, W. G. B. Huder, and W. Menzel, “Microstrip to waveguide transition compatible with mm-wave integrated circuits,” IEEE Trans. Microw. Theory Tech., vol. 42, no. 9, pp. 1842–1843, Sep. 1994. [5] W. Simon, M. Werthen, and I. Wolff, “A novel coplanar transmission line to rectangular waveguide transition,” in IEEE MTT-S Int. Microw. Symp. Dig., 1998, vol. 1, pp. 257–260. [6] L. Hyvonen and A. Hujanen, “A compact mmic-compatible microstrip to waveguide transition,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 1996, vol. 2, pp. 875–878. [7] T. Q. Ho, Y. C. Shih, and Y.-C. Shih, “Spectral-domain analysis of E -plane waveguide to microstrip transitions,” IEEE Trans. Microw. Theory Tech., vol. 37, no. 2, pp. 388–392, Feb. 1989. [8] J. W. Kooi, G. Chattopadhyay, S. Withington, F. Rice, J. Zmuidzinas, C. Walker, and G. Yassin, “A full-height waveguide to thin-film microstrip transition with exceptional RF bandwidth and coupling efficiency,” Int. J. Infrared Millimeter Waves, vol. 24, no. 3, pp. 261–284, Mar. 2003.

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[9] P. Soto, V. E. Boria, J. M. Catala-Civera, N. Chouaib, M. Guglielmi, and B. Gimeno, “Analysis, design, and experimental verification of microwave filters for safety issues in open-ended waveguide systems,” IEEE Trans. Microw. Theory Tech., vol. 48, no. 11, pp. 2133–2140, Nov. 2000. [10] R. B. Marks, “A multiline method of network analyzer calibration,” IEEE Trans. Microw. Theory Tech., vol. 39, no. 7, pp. 1205–1215, Jul. 1991. Theodore Reck (S’00) received the B.S.E.E. degree from The University of Texas at Austin, in 2000, and is currently working toward the Ph.D. degree in electrical and computer engineering at the University of Virginia, Charlottesville. He is currently with the Charles L. Brown Department of Electrical and Computer Engineering, University of Virginia. His research interests include submillimeter metrology and RF-MEMS.

Robert M. Weikle (S’90–M’91–SM’05) was born in Tacoma, WA, in 1963. He received the B.S. degree in electrical engineering and physics from Rice University, Houston, TX, in 1986, and the M.S. and Ph.D. degrees in electrical engineering from the California Institute of Technology, Pasadena, in 1987 and 1992, respectively. During 1992, he was a Post-Doctoral Research Scientist with the Department of Applied Electron Physics, Chalmers University of Technology, Göteborg, Sweden. In 1993, he joined the faculty of the University of Virginia, where he is currently a Professor with the Department of Electrical and Computer Engineering. His current research interests include submillimeter electronics, high-frequency instrumentation and metrology, and quasi-optical techniques for millimeter-wave power combining and imaging.

N. Scott Barker (S’94–M’99) received the B.S.E.E. degree from the University of Virginia, Charlottesville, in 1994, and the M.S.E.E. and Ph.D. degrees in electrical engineering from The University of Michigan at Ann Arbor, in 1996 and 1999 respectively. From 1999 to 2000, he was a Staff Scientist with the Naval Research Laboratory. In January 2001, he joined the Charles L. Brown Department of Electrical and Computer Engineering, University of Virginia, where he is currently an Associate Professor. His research interests include applying MEMS to the development of microwave and millimeter-wave circuits and components. He also investigates micromachining techniques for submillimeter-wave circuits and RF system and circuit design. Prof. Barker was a recipient of the 2003 National Science Foundation (NSF) CAREER Award, the 2000 IEEE Microwave Prize, and First and Second Place in the 1999 and 1997 Student Paper Competition of the IEEE Microwave Theory and Techniques Society (IEEE MTT-S) International Microwave Symposium (IMS).

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65-, 45-, and 32-nm Aluminium and Copper Transmission-Line Model at Millimeter-Wave Frequencies Thomas Quémerais, Student Member, IEEE, Laurence Moquillon, Jean-Michel Fournier, and Philippe Benech

Abstract—An improved analytical model of the CMOS 65-, 45-, and 32-nm silicon technology integrated transmission line is proposed. This model is derived from previous classical ones used for printed circuits board lines. Improvements have been performed to take into account the size of integrated lines. The study is validated up to millimeter-wave frequencies for different linewidths realized with various metal levels. Accurate results allow the model to be implemented in commercial computer-aided design software commonly used for millimeter-wave designs. A comparison with commercial tools is carried out. Index Terms—CMOS 65 nm, 45- and 32-nm technologies, interconnect levels, microstrip lines, millimeter-wave frequency.

I. INTRODUCTION

Fig. 1. Cross section of the STMicroelectronics CMOS 65-, 45-, and 32-nm overall processes.

HE MARKET of wireless transmission systems is growing and new industrial, scientific, and medical bands will be available for new applications in the millimeter-wave frequency range. In parallel, silicon technologies offer transistors with transition frequency (fT) greater than 100 GHz. This allows the realization of full integrated RF analog circuits on silicon, which is a key feature for future millimeter-wave communication systems. In this context, propagation lines used mainly for interconnections must be well modeled in the millimeter range for every geometrical parameter (length, width, oxide thickness, ) and available in computer-aided design software commonly used by designers. Comparable works up to 60 GHz are presented in the literature [1]–[3], but are not demonstrated to be included in computer-aided design tools or are limited to 40 GHz. The presented model could easily be implemented in a design kit for designers. Microstrip lines were designed in the interconnect levels with metal and insulator layers (the back-end of line) of the STMicroelectronics 65-, 45-, and 32-nm CMOS

process nodes. Afterwards, a model previously used for interconnection lines of printed circuits board [4] is analyzed and then improved to consider the specific case of thin layers on a silicon substrate. A method to integrate the model in circuit design simulators [Cadence, Mentor Graphics Eldo, Spectre, and Advanced Design System (ADS)] is also proposed. Finally, simulations resulting from the developed analytical model are compared with measurements of extracted line parameters: attenuation and propagation constant and characteristic impedance for two linewidths. These parameters, instead of conventional and , are used by millimeter-wave integrated-circuit designers. The proposed model is then compared with simulation results from Momentum and an ADS Multilayer commercial tool. Differences, advantages, and drawbacks of each tool are discussed before concluding.

T

Manuscript received January 12, 2010; accepted June 01, 2010. Date of publication August 09, 2010; date of current version September 10, 2010. T. Quémerais is with STMicroelectronics, 38920 Crolles, France, and also with IMEP-LAHC, UMR INPG/UJF/US/CNRS, 38016 Grenoble, France (e-mail: [email protected]). L. Moquillon is with STMicroelectronics, 38920 Crolles, France (e-mail: [email protected]). J.-M. Fournier and P. Benech are with IMEP-LAHC, UMR INPG/ UJF/US/CNRS, 38016 Grenoble, France (e-mail: [email protected]; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2010.2058277

II. INTERCONNECT LEVELS DESCRIPTION AND TRANSMISSION LINE DESIGN The STMicroelectronics 65-, 45-, and 32-nm bulk CMOS processes offers seven copper metal layers 5 thin 2 thick and one thick aluminium metal layer (alucap), as shown Fig. 1. Each metal layer is separated by one silicon–oxide layer and a nitride passivation layer is placed above the alucap to protect the circuits. The three different CMOS technologies have different metal thicknesses. The replacement of aluminium by copper allows a lower resistance for conductors, but it requires a new process called damascene. Dummy fills need to be inserted in the damascene copper process to respect metal density rules and guarantee component integrity. This is due to the chemical–mechanical

0018-9480/$26.00 © 2010 IEEE

QUÉMERAIS et al.: 65-, 45-, AND 32-nm ALUMINIUM AND COPPER TRANSMISSION-LINE MODEL

Fig. 2. Schematic of an: (a) integrated alucap strip metal (AP) and (b) alucap over metal 7 (AP/M7) microstrip line with a metal1/ metal2 (M1/M2) ground plane.

Fig. 3. Microstrip line scheme showing geometrical parameters.

polishing process, which is very sensitive to the metal density [5], and can create topographical and electrical defects called erosion in high-density areas and dishing in wide lines [6]. To provide a uniform surface planarity, more or less severe density rules are applied to every metal layers [7]. The density rule imposes metal density between 20%–80%. The direct consequence is to make holes for large metal areas. This is not necessary for the conducting metal strip, but only for large ground plane usually designed in the two first metal layers. The integrated microstrip line (Fig. 2) is composed of one alucap metal ribbon and a ground plane made of metal1 and metal2 stacked layers. The ground plane includes holes that respect the metal density rules in such a way that the two metal layers shield completely the high-resistivity silicon substrate [8]. The gap between the metal ribbon and ground plane is composed of a silicon–oxide layer. For the design of the line, an exemption to the rule was authorized around the metal trip of the line. When the strip metal is only composed of alucap, this configuration [see Fig. 2(a)] results in propagation lines with characteristic impedances from 15 to 69 in compliance with the CMOS 45-nm technology recommended rules, from 15 to 62 in 32 nm and from 15 to 65 in 65 nm. When the strip metal is composed of alucap and metal 7 stacked [see Fig. 2(b)], the resulting characteristic impedances are from 25 to 50 in 65 nm, from 20 to 52 in 45 nm, and from 25 to 53 in 32 nm. III. MODEL CHOICE AND DESCRIPTION Fig. 3 shows the geometrical parameters of a microstrip line. Currently, three main models or approximate solutions are available to describe the behavior of such a line as a function of the frequency and its characteristic parameters. These three main analytical models were formulated respectively by Wheeler [9], Schneider [10], and Hammerstad and Jensen [4]. Each of these models has advantages and drawbacks and we can find in the literature several papers that point out the

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limitations in different cases and some improvements to match model with measurements [11], [12]. However, these models can be used as a basis to approach a real case of application. The more important problem reported in literature is the determination or the representation of the dielectric constant over a wide range of frequencies. For this purpose, one possibility is to use microstrip lines, and for this reason papers using this configuration [13] can be found in the literature. An important consideration is that the thin-film microstrip line is quite different from classical microstrip lines in terms of dimensions. First, the widths of integrated lines are in the range of a few micrometers and not hundreds of micrometers, as in printed circuit boards, and secondly, the metal layer thicknesses are in the range of micrometers or less, increasing conductor losses. Some papers present transmission line models, but the used technology is not clearly presented and the frequency range is generally limited to a few gigahertz [5]–[9]. The three models are quickly analyzed to detect the more accurate one in our conditions of design tools and technology. On the Wheeler model, the synthesis and analysis equations are based upon a conformal mapping’s approximation of the dielectric boundary with parallel conductor strips separated by a dielectric sheet. Moreover, this model can only be applicable to alumina type substrates with relative permittivity in the range . For this reason, the of 8–12, not to silicon substrates model is unusable for our purposes. The Schneider model defines two operating regions according to the geometrical parameters of the line, mainly width and is loheight. The separation region determined by cated in the range of our application. This limitation implies a noncontinuity of the model, which makes it unusable here. Aforementioned limitations lead to choosing the Hammerstad and Jensen model [4] because it allows a wide range perratio values. Furthermore, it fits well with mittivity and the realistic conditions of integrated lines and provides the best accuracy. Moreover, this model has to be improved to take into account back-end effects in CMOS technologies. The basis of the model proposed in [4] is to consider the nonquasi-TEM mode. With this assumption, the characteristic impedance and effective permittivity of the line are expressed as a nonlinear function that depends on physical dimensions of the line. of the integrated line is First of all, the static resistance added to the model, which does not take it into account, as it is negligible in lines on the printed circuit board. The resistance is expressed by

(1) where , , , and are, respectively, the resistivity, width, thickness, and length of the metal strip. and effective perThe characteristic impedance that depend only on the physical and mittivity geometrical parameters of the line are then established from multiplies ( 4, in this [4]. A fitting parameter case) to fit measurements. For the 65-, 45-, and 32-nm technolo. This result is not surprising because gies,

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the three technologies have the same physical parameters, only the dimensions change. Furthermore, this result is in accordance with the literature [14], [15]. The correction parameter takes into deaccount the effect of the nitride passivation layer posited above the highest metal strip of the line and which inparameter. creases the and asSince the equations for sume that the metal strip thickness is null m , the linewidth must be corrected. Indeed, growing the strip thickness is physically equivalent to enlarging the strip width so that becomes [4]. Since line geometries are different between silicon and on printed circuit boards, a correction paramfor the 45-nm technology eter, whose value is and 0.55 for the 65- and the 32-nm technologies (whose metal to fit measurelayers have larger thickness), is applied on ments. A similar correction of the effective width value has been done in [2]. Thus, modified formulas for the characteristic impedance and the effective permittivity applied to thin-film microstrip lines are established. The second step is to take into account the wave dispersion by making these parameters dependent on the freand established from [4] are then written as quency.

Fig. 4. Scheme of the T line model.

create a black box with and component description format parameters and make this object point to the netlist including the model. This allows an easy correspondence between the layout and the schematic for millimeter-wave designers. To include the matrix (4) in either Eldo, Spectre, or an ADS netlist, its components have to be identified as a T model presented in Fig. 4. , and are described by

(5) and

(6)

(2) and

(3)

The last step is to establish from those equations the wave propagation constant , where and parameters are, respectively, the attenuation and propagation constant. These expressions are established from [4] as a function of the and and corrected the microstrip line physical and geometrical parameters (Fig. 3). matrix can be written as The microstrip line

(4) where each parameters depend on and . To use the developed model in the Cadence framework for Eldo, Spectre, or ADS simulations, the designer has to first

Equations (5) and (6) are written into a netlist for the simulators. As Eldo and Spectre only accept , , and passive pa[see (5) and (6)] should be written in a comrameters, and and identified with and in the model plex form netlist. Furthermore, Spectre cannot support frequency-dependent components. With this simulator, the frequency has to be fixed: this implies that the model is valid only at the chosen frequency. For an ADS simulator, (5) and (6) can be directly written in the netlist using complex form. IV. MEASUREMENTS AND PARAMETER EXTRACTION To develop an accurate model of thin-film microstrip lines in 65-, 45-, and 32-nm technologies, ten lines were designed as reported in Table I. The lines are 500- and 800- m long to enable an accurate extraction of the attenuation constant without parasitics up to 110 GHz. Furthermore, all the lines have a metal1/metal2 ground plane. The accesses to the line are composed of RF pads and 50- m length accesses on each end of the line (Fig. 5). Measurements of the -parameters of the lines are performed using an ANRITSU ME7808C Broadband vector network analyzer (VNA) and a semiautomatic Cascade S300 station. The measurement RF probes are Cascade Microtech Infinity probes in a ground–signal–ground (GSG) configuration. For the calibration of the VNA, we had at our disposal the Cascade impedance standard substrate (ISS) with the reference 104–783. The calibration can be performed by using other calibration devices like on-wafer standards or the GaAs substrate. The last one is used for the National Institute of Standards and

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TABLE I LINES REALIZED IN CMOS 65, 45 , AND 32 nm

Fig. 6. Measured reflection coefficient of a 45-nm technology microstrip line with different VNA calibrations.

Fig. 7. Measured transmission coefficient of a 45-nm technology microstrip line with different VNA calibrations.

Fig. 5. Microphotography of a 9.2-m-wide line 800-m long, each with metal1/metal2 ground plane in 45-nm technology with the RF pads and accesses.

Technology (NIST) multiline [line-reflect-line (LRL)] calibration. We have tried to find the best possible calibration procedure. With the Cascade ISS, three calibrations are possible: short-open-load-thru (SOLT) [16], load-reflect-match (LRM) [18] and load-reflect-reflect-match (LRRM) [17]. After each of the calibration, the reflection and transmission coefficient of an Alucap line of 9.2- m width and 800- m length in a 45-nm CMOS technology were measured. The measurement results are presented in Figs. 6 and 7. The SOLT calibration is very noisy, as it can be observed on the transmission coefficient in Fig. 7. Thus, this calibration was eliminated. The LRM and LRRM calibrations give very close results. However, as it is stated in [19] and [20], the LRM calibration technique requires a match load for each ports of the VNA. If the two match loads are not equal, the measurement accuracy is reduced. Moreover, the probe placement error has less influence when LRRM calibration is used [17]. For these reasons, we decided to use the LRRM calibration. To extract the -parameters of the line from measurements, the accesses (RF pad and 50- m access) are de-embedded using the method presented in [21]. This method that removes pad parasitics and pad-line discontinuities is used for the characterization of lossy integrated transmission lines and enables an accurate characteristic impedance measurement. The characteristic

impedance (7), propagation constant (8), and attenuation constant (9) of the microstrip line have been established from [21] using the corrected parameters

(7)

(8) (9) where is the line length.

V. VALIDATION OF THE MODEL The improved model is compared to the other models and measurements on Figs. 8–10. For this purpose, an alucap/metal7 line of 9- m width and 800- m length in a 65-nm technology is chosen. The characteristic impedance obtained with the Schneider and Wheeler models are much larger than the measured one. The improvements obtained with the presented model are clearly visible on Figs. 8–10. Figs. 11–13 show, respectively, the characteristic impedance, propagation constant, and attenuation constant measured and simulated for two alucap/metal7 metal strips of 4.4- and 9- m width and 800- m length in 65-nm technology.

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Fig. 8. Simulated and measured characteristic impedance of a 65-nm technology microstrip line.

Fig. 12. Simulated and measured propagation constant of 65-nm technology microstrip lines.

Fig. 9. Simulated and measured propagation constant of a 65-nm technology microstrip line.

Fig. 13. Simulated and measured attenuation constant of 65-nm technology microstrip lines.

Fig. 10. Simulated and measured attenuation constant of a 65-nm technology microstrip line.

Fig. 14. Simulated and measured characteristic impedance of 45-nm technology microstrip lines.

Fig. 11. Simulated and measured characteristic impedance of 65-nm technology microstrip lines.

Figs. 14–16 show, respectively, the characteristic impedance, propagation constant, and attenuation constant measured and simulated for two alucap metal strips of 3- and 9.2- m width and 800- m length in 45-nm technology.

Figs. 17–19 show, respectively, the characteristic impedance, propagation constant, and attenuation constant measured and simulated for two alucap metal strips of 3- and 9- m width and 500- m length in 32-nm technology. The results (Figs. 11–19) show good agreement between measurements and simulations: the model is, therefore, validated millimeter-wave frequencies for different linewidths and different technologies. The resonance frequency observed at 100 GHz on the characteristic impedance depends on length, on loading impedance, length line. Thin-film microstrip lines and appears for a often used in millimeter-wave designs have a maximum length of 500 m to avoid this frequency resonance. Nevertheless, the difference between measurement and simulation observed from 70 to 110 GHz on the characteristic impedances curves comes from the model [see (5) and (6)], which does not well describe the resonance of the lines.

QUÉMERAIS et al.: 65-, 45-, AND 32-nm ALUMINIUM AND COPPER TRANSMISSION-LINE MODEL

Fig. 15. Simulated and measured propagation constant of 45-nm technology microstrip lines.

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Fig. 19. Simulated and measured attenuation constant of 32-nm technology microstrip lines.

TABLE II COMPARISON MEASUREMENTS VERSUS SIMULATION OF THE LINES CHARACTERISTIC PARAMETERS AT 60 GHz

Fig. 16. Simulated and measured attenuation constant of 45-nm technology microstrip lines.

Fig. 17. Simulated and measured characteristic impedance of 32-nm technology microstrip lines.

Fig. 20. Characteristic impedance measured and from simulators.

The results show good agreement between measurements and model for all the lines. The developed model is valid for linewidths between 4.4–25 m in 65 nm and between 3–25 m in 45- and 32-nm technologies. VI. COMPARISON BETWEEN ELECTROMAGNETIC SIMULATORS Fig. 18. Simulated and measured attenuation constant of 32-nm technology microstrip lines.

Table II presents the measured and simulated characteristic parameters of the realized lines at 60 GHz. This frequency is one of the most used for millimeter-wave applications.

Figs. 20–22 show a comparison between measurements and simulations performed with Momentum, ADS Multilayer, and this work simulated with Eldo of a 9.2- m width alucap metal strip and 800- m length in 45-nm technology. The line simulated with Momentum is 100- m long to avoid time-consuming simulations. Moreover, the physical and geometrical parameters of the metal and oxide layers result from

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VII. CONCLUSION

Fig. 21. Propagation constant measured and from simulators.

The model of thin-film microstrip line is improved using CMOS 65-, 45-, and 32-nm STMicroelectronics processes, and validated at millimeter-wave frequencies. It takes physical parameters like conductor dimensions and material properties into account. A good agreement between simulations and measurements is observed for the main line parameters (attenuation and propagation constants and characteristic impedance) as compared to commercial softwares. Some design restriction for the designer is also pointed out like the line length or linewidth that must be chosen carefully to avoid the line resonance frequency. The insertion of the model into Cadence allows an easy correspondence between the layout and schematic for millimeter-wave designers. This model can be developed and implemented in the three main computer-aided design simulators for any technologies using the same fit parameters.

ACKNOWLEDGMENT

Fig. 22. Attenuation constant measured and from simulators.

TABLE III COMPARISON BETWEEN SIMULATORS

the process description of CMOS 45-nm technology from the STMicroelectronics. The same comparisons have been made in 65- and 32-nm technologies, but not presented here, and have given similar results. An excellent agreement is obtained between the analytical model compared to the other softwares up to 110 GHz. Table III presents the benefits and the drawbacks of each simulation tool. Simulation time and integration into a Cadence environment have been compared. These results show the interest of using the proposed analytical model to simulate the transmission line frequency behavior. In further development, this model will be used to design matching lines for amplifiers in order to validate the model in the context of circuit design.

The authors want to thank S. Pruvost, P. Garcia and D. Pache, all with STMicroelectronics, Crolles, France, for their help during the modeling work. The authors would also like to thank N. Corrao, IMEP-LAHC, Grenoble, France, for the measurements.

REFERENCES [1] M. V. Schneider, “Microstrip dispersion,” Proc. IEEE, vol. 60, no. 1, pp. 144–146, Jan. 1972. [2] L. N. Tran, D. Pasquet, E. Bourdel, and S. Quintanel, “CAD-oriented model of a coplanar line on a silicon substrate including eddy-current effects and skin effect,” IEEE Trans. Microw. Theory Tech., vol. 56, no. 4, pp. 663–670, Apr. 2008. [3] J. Zheng, Y.-C. Hahm, V. K. Tripathi, and A. Weisshaar, “Cad-oriented equivalent-circuit modeling of on-chip interconnects on lossy silicon substrate,” IEEE Trans. Microw. Theory Tech., vol. 48, no. 9, pp. 1443–1451, Sep. 2000. [4] E. Hammerstad and Ø Jensen, “Accurate models for microstrip computer-aided design,” IEEE Trans. Microw. Theory Tech., vol. MTT-28, no. 6, pp. 407–409, Jun. 1980. [5] S. Kordic, H. Banvillet, and R. M. Gonella, “CMP of metals,” in Mater. Res. Soc. Symp., San Francisco, CA, Apr. 2000, pp. 110–113. [6] T. Park, T. Tugbawa, J. Yoon, D. Boning, J. Chung, R. Muralidhar, S. Hymes, Y. Gotkis, S. Alamgir, R. Walesa, L. Shumway, G. Wu, F. Zhang, and R. Kistler, “Pattern and process dependencies in copper damascene chemical mechanical polishing processes,” in VLSI Multilevel Interconnect Conf., Santa Clara, CA, Jun. 1998, pp. 437–442. [7] A. B. Kahng, G. Robins, A. Singh, and A. Zelikovsky, “Filling algorithms and analyses for layout density control,” IEEE Trans. Comput.Aided Design Integr. Circuits Syst., vol. 18, no. 4, pp. 445–462, Apr. 1999. [8] L. F. Tiemeijer, R. M. T. Pijper, R. J. Havens, and O. Hubert, “Low-loss patterned ground shield interconnect transmission lines in advanced IC processes,” IEEE Trans. Microw. Theory Tech., vol. 55, no. 3, pp. 561–570, Mar. 2007. [9] H. A. Wheeler, “Transmission-line properties of parallel strips separated by a dielectric sheet,” IEEE Trans. Microw. Theory Tech., vol. MTT-13, no. 2, pp. 172–185, Mar. 1965. [10] M. V. Schneider, “Microstrip lines for microwave integrated circuits,” Bell Syst. Tech. J., vol. 48, pp. 1421–1444, May 1969. [11] F. Schnieder and W. Heinrich, “Model of thin-film microstrip line for circuit design,” IEEE Trans. Microw. Theory Tech., vol. 49, no. 1, pp. 104–110, Jan. 2001. [12] K. S. R. Krishna, J. L. Narayana, and L. P. Reddy, “ANN models for microstrip line synthesis and analysis,” Int. J. Elect. Syst. Sci. Eng., vol. 1, no. 3, pp. 196–200, 2008.

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[13] E. Semouchkina, W. Cao, M. Lanagan, R. Mittra, and W. Yu, “Combining FDTD simulations with measurements of microstrip ring dielectrics at resonators for characterization of low- and highmicrowaves,” Microw. Opt. Technol. Lett., vol. 29, no. 1, pp. 21–24, Apr. 2001. [14] C. Warns, W. Menzel, and H. Schumacher, “Transmission lines and passive elements for multilayer coplanar circuits on silicon,” IEEE Trans. Microw. Theory Tech., vol. 46, no. 5, pp. 616–622, May 1998. [15] H. Ishii, N. Sahri, T. Nagatsuma, K. Machida, K. Saito, S. Yagi, M. Yano, K. Kudo, and H. Kyuragi, “New fabrication process for low-loss millimeter-wave transmission lines on silicon,” Jpn. J. Appl. Phys, vol. 39, pp. 1982–1986, 2000. [16] Safwat, A. M. E. Hayden, and Leonard, “Sensitivity analysis of calibration standards for SOLT and LRRM,” in 58th ARFTG Microw. Meas. Conf., San Diego, CA, Nov. 2001, pp. 1–10. [17] L. Hayden, “An enhanced line–reflect–reflect–match calibration,” in 67th ARFTG Microw. Meas. Conf., San Francisco, CA, Jun. 2006, pp. 143–149. [18] D. F. Williams and R. B. Marks, “LRM probe-tip calibrations using non ideal standards,” IEEE Trans. Microw. Theory Tech., vol. 43, no. 2, pp. 466–469, Feb. 1995. [19] A. Davidson, K. Jones, and E. Strid, “LRM and LRRM calibrations with automatic determination of load inductance,” in 36th ARTFG Conf. Dig, Nov. 1990, pp. 57–63. [20] F. Purroy and L. Pradell, “New theoretical analysis of the LRRM calibration technique for vector network analyzers,” IEEE Trans. Instrum. Meas., vol. 50, no. 5, pp. 1307–1314, Oct. 2001. [21] A. M. Mangan, S. P. Voinigescu, and M.-T. Y. Tazlauanu, “De-embedding transmission line measurements for accurate modeling of IC designs,” IEEE Trans. Electron Devices, vol. 53, no. 2, pp. 235–241, Feb. 2006.

Laurence Moquillon received the M.S. and Ph.D. degrees from the University of Limoges, Limoges, France, in 2001. Her doctoral research with the Microwave and Optical Communication Research Institute (now XLIM), Limoges, France, concerned the study of microwave planar ring resonator multipole active filters. Since 2001, she has been with STMicroelectronics, Crolles, France. Her principal research interests are RF and millimeter-wave circuit designs for wireless communication using SiGe BiCMOS and advanced

K

Thomas Quémerais (S’10) was born in Guérande, France, in May 1982. He received the M.S. degree in physics of semiconductors and microwaves from the Grenoble Institute of Technology (INPG), Grenoble, France in 2007, and is currently working toward the Ph.D. degree at STMicroelectronics and the IMEP-LAHC Institute, the Microelectronics, Electromagnetism and Photonic Laboratory, INPG, Grenoble, France, as part of the Microwaves and RFIC Design and Modeling Team, INPG. His research concerns the domain of passive and active device modeling and integrated circuit (IC) design at millimeter-wave frequencies in advanced CMOS technologies and devices and circuits reliability at high frequencies.

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CMOS technologies.

Jean-Michel Fournier received the Electronic Engineering degree from the National Engineer School (ENSEEIHT), Toulouse, France, in 1974, and the M.S. and Ph.D. degrees in solid-state physic from the University Claude Bernard, Lyon, France, in 1975 and 1979, respectively. In 1979, he joined Research and Development of the Microelectronic Department, France Telecom, Grenoble, France, where he was involved with analog MOS application-specific integrated circuit (ASIC) development (high-speed video amplifiers, Gmc filters, device modeling). From 1992 to 1996, he was in charge of the Analog Design Group, during which time he focused his interest on the BiCMOS process for RF applications. Since 1996, he has been a Professor with the School of Electronic and Physic of INPG (PHELMA), Grenoble, France. With the IMEP-LAHC Laboratory, his main research interest is the design of analog RF and millimeter-wave integrated circuits in CMOS technology.

Philippe Benech received the M.S. degree in microelectronics from the University of Montpellier, Montpellier, France, in 1987, and the Ph.D. degree in instrumentation from the University Joseph Fourier, Grenoble, France, in 1990. Since 2000, he has been a Professor with the University Joseph Fourier and a Rsearcher with IMEPLAHC, Grenoble, France. His field of interest is in the domain of integration of passive components and functions for telecommunications.

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Physics-Based Inductance Extraction for Via Arrays in Parallel Planes for Power Distribution Network Design Jingook Kim, Member, IEEE, Liehui Ren, Student Member, IEEE, and Jun Fan, Senior Member, IEEE

Abstract—A systematic approach for inductance extraction for via arrays between two parallel planes is presented. Both self and mutual inductance values are obtained based on a cavity model. The physics associated with the via inductances is analyzed, and a rigorous method is developed to derive an equivalent total inductance for multiple via arrays. Analytical equations for the equivalent total inductance are derived in closed forms for simple cases. The proposed method is corroborated with measurements, and application of the method for power distribution network designs is demonstrated. Index Terms—Cavity model, decoupling capacitor, equivalent total inductance, integrated circuit (IC) pin layout, parallel planes, power distribution network (PDN), via inductance extraction.

I. INTRODUCTION

C

URRENT integrated circuits (ICs) can operate at internal clock frequencies well into the gigahertz range, and draw currents up to tens of amperes including both dc and high-frequency components. The current flowing through the power, logic circuits and buffers, and power return (often denoted “ground” in designs) gives rise to significant voltage drop and ripple, i.e., unwanted noise, in the supply voltage, which can significantly impact signal and power integrity, and can also lead to electromagnetic interference problems [1]. The noise in the supply voltage results from the parasitic resistances and inductances in the power distribution network (PDN), both on and off the IC chip [2]. The parasitic resistances causing – drop are mostly contributed by the metal lines on-chip and the bond wires or ball-grid-array (BGA) contacts, whereas the parasitic inductances causing voltage ripple are mainly associated with the vias, traces, pads, and other metal interconnects both on-package and on the printed circuit board (PCB). Decoupling capacitors have been widely used to stabilize the power supply voltage levels by effectively providing charge to meet the current demand of the IC. However, the parasitic inductance associated with a decoupling capacitor limits the rate of charge supply from the capacitor [3]. Mutual inductive coupling between closely spaced vias of the IC and decoupling capacitors, as well as the self-inductances determine the rate at which Manuscript received January 06, 2010; revised June 18, 2010; accepted June 18, 2010. Date of publication August 12, 2010; date of current version September 10, 2010. The authors are with the Missouri S&T Electromagnetic Compatibility Laboratory, Missouri University of Science and Technology, Rolla, MO 65401 USA (e-mail: [email protected]; [email protected]; [email protected]). Digital Object Identifier 10.1109/TMTT.2010.2058278

Fig. 1. (a) Typical PDN in high-speed PCBs with decoupling capacitors providing charge to an IC. (b) Schematic representation showing an equivalent total inductance that combines all inductances for the decoupling capacitors and IC interconnects.

charge can be transferred from the decoupling capacitor to the IC. Therefore, calculating via inductances in a multilayer PCB is important to evaluate the effectiveness of decoupling capacitors. In addition, there are usually multiple decoupling capacitors in practical designs, often in close proximity to each other, to provide sufficient charge to an IC, as shown in Fig. 1(a). Additionally, the IC may have multiple power and power-return (ground) pins as well. In order to quickly quantify the effectiveness of the decoupling layout and the IC pin map, and facilitate engineering design, it is desirable to have an equivalent total inductance that combines all the decoupling capacitor and IC interconnects for many pins and capacitors, as depicted in Fig. 1(b). The equivalent total inductance of a power bus structure between a pair of parallel planes is addressed herein; however, the results and approach can be extended to multiple layers, and the parasitic inductances within any parallel planes can be considered together. The structure of the power bus under study includes a pair of parallel planes, and an impedance matrix for specific locations or ports is calculated. Full-wave electromagnetic modeling methods have been used for studying this problem, including

0018-9480/$26.00 © 2010 IEEE

KIM et al.: PHYSICS-BASED INDUCTANCE EXTRACTION FOR VIA ARRAYS IN PARALLEL PLANES

the finite-element method (FEM) [4], partial-element equivalent-circuit (PEEC) method [5], [6], and the finite-difference time-domain (FDTD) method [7], [8]. In addition, a straightforward and fast transmission-line grid method (TLM) suitable for SPICE implementation has demonstrated the distributed behavior and the impact of resonances of a parallel-plane power bus [9]. Another fast method has been developed based on the cavity model for calculating the input impedance and transfer impedance for arbitrarily shaped parallel planes [10], combined with the segmentation technique [11], [12]. Extraction of via inductance has also been extensively investigated. Calculation of via inductance in a microstrip line has been studied using various approaches, and formulas or design curves for inductance values were reported in [13]–[15]. When a via is located between a pair of conducting parallel planes, the portion of the current on the planes that crowds down to the via can also contribute magnetic flux wrapping the via, thus change the via inductance value [16]. An inductance extraction approach for vias in a rectangular power bus has been proposed based on a PEEC-type formulation, and a closed-form expression for via self-inductance that includes the effect of current congestion has been derived [17]. An approach to calculate both self-inductance and mutual inductance of multiple vias between a pair of rectangular conducting parallel planes is presented in this paper based on a cavity model [10]. In addition, closed-form expressions for the via inductances are also developed from the perspective of energy conservation. The physics associated with the mutual inductance between vias in the planes is also investigated, which can be negative in a confined area bounded by perfect magnetic conductor (PMC) boundaries. The equivalent total inductance of multiple vias is then derived, and the values of some example geometries are shown using 2-D contour plots. The equivalent total inductances are calculated through matrix simplification by grouping corresponding inductance terms together. Closed-form expressions for the equivalent total inductance are derived for a three-via structure to quantify the extent to which the mutual inductance between vias between conducting planes impacts the overall performance of the interconnects. Finally, the proposed approach is corroborated by measurements, and applied to the analysis of decoupling capacitor layout and IC pin map designs. Various I/O patterns are simulated before taping out an electronic system including ICs and packages/boards in current industry practice, to ensure that the core and simultaneous switching noise (SSN) of the system is within specifications. Since the I/O driver model is usually given in a nonlinear I/O Buffer Information Specification (IBIS) file or as an active device model using a SPICE library, the interaction among the nonlinear devices, signal lines, and PDN can only be captured through a time-domain simulation. Since the performance of a PDN is typically analyzed in the frequency domain and its specifications are given in terms of a target impedance [29], conversion of the frequency-domain PDN model into the time domain suitable for circuit simulation using the modified nodal analysis is necessary. However, common pole-zero fitting

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methods for the conversion do not maintain a physical relationship between the geometry and the equivalent-circuit model. For design purposes, it is desirable for the model of the power bus to be physics based, with passivity and causality enforced. There is then a one-to-one correspondence between the geometry model response that can guide design and discovery. Among previous methods, those based on the PEEC or TLM can further result in the physics-based SPICE models of the power bus with large planes [5], [6], [9]. In [28], the cavity resonator model has also been directly represented as a circuit model using ideal transformers. However, these models are still quite complicated and require numerous elements to obtain an acceptable accuracy. An approach for extracting a physics-based SPICE circuit model from the first principles for via arrays between two parallel plates and the physical understanding is proposed herein. The method reduces a large number of vias between two parallel plates into a few equivalent inductances through analytical reduction. Although it is a reduced model, the essential physics for providing design insights and directions are retained. The approach also has significant advantages in the analysis and simulation of the practical applications with multiple via arrays between parallel planes. In terms of accuracy, the proposed equivalent-circuit model compares well to the resonant cavity model in the frequency range before the first cavity resonance. Although the developed circuit models do not capture the distributed cavity resonances in the planar structure, it is acceptable in power integrity studies since the distributed resonances are usually in the frequency range where on-chip decoupling capacitance dominates the PDN performance. II. VIA INDUCTANCE EXTRACTION An approach to calculate the self-inductance and mutual inductance of vias between a pair of rectangular parallel planes is presented in this section based on a cavity model formulation. These expressions can also be developed from the perspective of energy conservation. The physics associated with the mutual inductance among vias is investigated. A. Inductance Extraction From Cavity Model The ports are defined across the via antipads, as shown in Fig. 2(a), when the vias are implemented in the actual package geometry and PCBs. The impedance then represents the voltage across the antipad of “via ” divided by the current into “via .” To solve the impedance matrix between these well-defined ports, the actual via geometries guiding the vertical current is replaced by impressed current sources, as shown on the left of Fig. 2(b). During this step, the perfect electric conductor (PEC) boundary condition on the vias is lost, which means the multiple scattering among vias and the fringing capacitance between via barrel and planes are neglected. The impedance matrix is then directly solved from Maxwell’s equations, whose solution is the resonant cavity model as [10]–[12], (1)

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are the permeability, permittivity, and the loss tangent is the skin depth, of the dielectric material, where is the conductivity of the metal planes, and the constant if if . Most practical via designs have the ratios of via spacing to plane spacing, and via spacing to the antipad radius larger than 1.6. Under these geometrical constraints, the multiple scattering among vias is negligible [21], [33]. PMC boundary conditions are applied at the plane pair boundaries in deriving (1). In other words, the fringing electric fields at the edges are neglected. For typical PDN design problems, where area fills have numerous vias and/or a significant area, and the broadband performance is of concern, the incremental increase in the effective electrical size of the area fill is negligible. The impedance (1) is also given for rectangular ports; however, the impedance exited by the ports in other shapes can be computed by using an equivalent length or area [30], [31]. The impedance (1) calculated from the cavity model represents the – relations between the ports in the actual via structure of Fig. 2(a), and results in a network model that can be handled in the network fashion, as shown on the right of Fig. 2(b). Each individual term in the series summation of (1) represents an individual mode of the cavity. The first term with the mode can be separated from the other resonumber nant modes as

Fig. 2. (a) Geometry of the ports across the antipads of vias between parallel planes. (b) Structure used to solve the impedance Z , where actual via geometries is replaced by impressed current sources. (c) Physic-based L–C lumped circuit model for the actual geometry.

where

(2) where is the parallel-plate capacitance of the mode with low loss, and can planes for the be treated as an equivalent inductance as

(3)

and are the plane dimensions in the - and -directions, respectively, is the dielectric thickness or the separation beand are the coordinates tween the two planes, of the center of the th and th ports, respectively, and represent the widths of the th and th ports, respecand tively, with as the mode numbers along the - and -directions, respectively, , , and

is purely real in the frequency range from dc to the where . first cavity resonance frequency; in other words, when The resonance frequencies can be determined as (4) Below the first cavity resonance frequency, all the modes in (3) are evanescent modes that contribute only to the inductance.

KIM et al.: PHYSICS-BASED INDUCTANCE EXTRACTION FOR VIA ARRAYS IN PARALLEL PLANES

The frequency-dependent inductive term (3) is nearly constant in the frequency range below approximately 60% of the first cavity resonance frequency [22]. Thus, it can be approximated as a frequency-independent value in the low-frequency range as

(5) Alternatively, the double series summation for also be approximated as

in (3) can

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over the cross-sectional area of rectangular via barrels because the impedance (1) is derived from a uniform impressed current distribution over the port areas. The lumped circuit model and the inductance expressions are applicable below the first parallel-plate resonance, and directly reflect the physics. B. Energy Perspective and Negative Mutual Inductance The lumped circuit model and the inductance formula derived based on the cavity model can also be derived from an energy perspective. Assuming the dimension along the -direction is small enough to neglect the -directional electromagnetic field variation between the two planes, the electric field has only a , and the magnetic field normal component to the planes . Injecting a current only has tangential components into a port at induces an electromagnetic field between as [24] the two planes at

(6) using a Chebyshev expansion, where (7)

and is the radius of a circular port with the same cross-sectional area of the rectangular port. A single summation is required over the entire frequency range with the result that the series is now frequency independent, and for calculation purposes, rather than calculating a slowly converging double summation at every frequency point [30], [32]. The infinite summation in (5) and (6) converges when a sufficient number of terms are used. It converges slowly when the two ports of and are very close to each other. The convergence also depends on the plane size. The computation time is several seconds per via in a practical geometry. In particular, for the plane size of 254 mm 267 mm, which is used in this paper, the mode number is necesvalue within 5% of the converged value, and sary to reach an the computation time is approximately 3 s. However, the focus of this work is not in accelerating the convergence of the calculations, but rather on the physics and a physics-based SPICE model extraction, as well as the resulting design insights and guidance. The impedance (2) can be directly represented with the – lumped circuit model shown in Fig. 2(c). The ports in the circuit model correspond to the ports in the geometry, as shown in Fig. 2(a). The circuit model is drawn to have a one-to-one correspondence to the geometry. The value of the capacitance is obtained from the parallel-plate capacitance, and the inductance values are given by (5). The inductances are related to the currents on both the vertical via barrels and the parallel planes. Fig. 2(c) illustrates that some portion of the inductance is due to the current on the vertical via barrel, and the other portion is due to the current on the parallel planes. In particular, the inductance value given in (5) is for a uniform current distribution

(8) The total electromagnetic field induced by many current sources is the vector sum of the fields due to each individual current source. Therefore,

(9)

The total energy stored in the magnetic field is then

(10)

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The total energy stored in the magnetic field can be calculated as that stored in the self-inductance and mutual inductance in Fig. 2(b) as

(11) The first and second summations are the energy stored in the self-inductance and mutual inductance, respectively [18]. Comparing (10) and (11) results in

(12)

(13) in the If the wavenumber is negligible as compared to frequency range below the first cavity resonance frequency, then substituting (8) into (12) and (13) leads to the exact inductance formula in (5). The contour plot of the via self-inductance obtained using , is shown in (5) versus the via location in the plane pair, Fig. 3(a). In this example, the dimensions of the rectangular planes are 254 mm 267 mm (10 in 10.5 in), the distance between the planes is 0.089 mm (3.5 mil), and the via is in the rectangular shape of 0.2 mm 0.2 mm. The value of the via self-inductance is predominantly constant over the planes, but increases rapidly near the edges and corners of the planes. , has a larger The mutual inductance between two vias, value when the two vias are in proximity, as shown in Fig. 3(b), where Via 1 is fixed at (88.9, 109.2) (mm) from the lower left corner and Via 2 is moved around in the plane pair. The mutual inductance can also be negative. As shown in Fig. 3(b), the mutual inductance in most of the area, except the left-bottom portion, is negative. The negative mutual inductance in the parallel-plate geometry is different from the conventional understanding of the mutual inductance in an open region where the value is always positive [18]. The partial mutual inductance between the vertical via portions is always positive, and is given as [19]

Fig. 3. (a) Contour plot of self-inductance L (pH) versus via location over the plane for a single via. (b) Contour plot of mutual inductance L (pH) from Via 1 to Via 2. Mutual inductance is positive only in the area close to Via 1.

(14)

An equivalent total inductance for a three-via structure is derived in this section, and the values of some example geometries are shown using 2-D contour plots. Closed-form expressions for the equivalent total inductance are also derived to quantify the extent to which the mutual inductance among vias between conducting planes impacts the overall performance of the interconnects.

where is the distance between two vertical conductor filaments whose length is . It can be shown that the value in (14) goes to zero from a positive direction as goes to infinity. However, when the horizontal plane currents are considered, the total mutual inductance between two ports on vias can be negative. , then also. When From (13), if the spacing between two vias is sufficiently large, vector plots of the -fields from each current source injected on each via

show the directions of the two -fields are predominantly opposite to each other in the area between the two sources, and thus the integral of their inner products is negative. On the other hand, when the two vias are closely spaced, the -fields are in the same direction in most of the area, and thus the integral in (13) is positive. III. CALCULATION OF EQUIVALENT TOTAL INDUCTANCE FOR A THREE-VIA STRUCTURE

A. Equivalent Total Inductance A test case to extract an equivalent total inductance for multiple vias is illustrated in Fig. 4. A current is injected at a port at Via 1, with a rectangular dimension of 0.2 mm 0.2 mm, which is a typical size used in practical designs. The two parallel planes

KIM et al.: PHYSICS-BASED INDUCTANCE EXTRACTION FOR VIA ARRAYS IN PARALLEL PLANES

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, which is marked as . Therefore, the voltages and Via 3, currents at all the inductances in the circuit model are related through an inductance matrix as

(15)

Fig. 4. Test structure for calculating an equivalent total inductance. The equivalent total inductance is seen looking into a port at Via 1. Via 2 is a fixed shorting via, and Via 3 is another shorting via moved around.

where the inductance components are obtained from the inductance formula (5); the subscript indicates a port, and the subscript indicates a shorting via, as shown in Fig. 5(b). The values in (15) are physics-based quantities extracted from a first-principles Maxwell’s equation formulation, and represent the inductances associated with both the currents on the vias, as well as the currents on the planes at and between the vias. Since and the locations of Via 1 and Via 2 are fixed, are constant, but and vary when the location of Via 3 changes. and are the same as , and the The voltages across total current flowing through the two shorting vias is the return current of the source current into the port at Via 1. Equation (15) can then be modified as

(16) where

and inverting the 2 as

2 equivalent

referring to Fig. 5(b). By further matrix, (16) can be expressed

(17) Fig. 5. (a) Test geometry shown in Fig. 4. (b) Its corresponding lumped circuit model.

are shorted by the shorting Via 2. An additional shorting Via 3 is also added to investigate the reduction in inductance when adding multiple decoupling capacitors. The shorting via(s) provides a return path for the injected current. The dimensions of the planes are the same as those in Fig. 3. Via 1 is fixed at (88.9, 109.2) (mm) from the lower left corner, and Via 2 is also fixed at (88.9, 121.9) (mm), while Via 3 is moved around in the plane pair. The ports at Via 2 and Via 3 are shorted in the lumped circuit model in Fig. 2(c), which results in the modified circuit model, as shown in Fig. 5. The inductances for the shorting vias are extracted from the first-principles Maxwell’s equation formulation and the cavity model, and then the shorts are applied to the network expressions for these inductances. The circuit model in Fig. 5(b) indicates that the voltage across the inductance associ, should be the same as that associated with ated with Via 2,

In this way, the contributions of the two shorting vias that share the return current are combined, and the 3 3 inductance matrix in (15) is now transformed into a 2 2 equivalent inductance and then denote the equivamatrix in (17). lent self-inductance of Via 1, the equivalent self-inductance of the two parallel shorting vias, and the equivalent mutual inductance between Via 1 and the two shorting vias, respectively. An ” seen looking into the port at equivalent total inductance “ Via 1 can then be computed as (18) The effect of an additional shorting Via 3 can be demonstrated by normalizing the equivalent total inductance calculated using (15)–(18) with regard to that with just Via 1 and shorting Via 2, which is 167.4 pH calculated as . The normalized value of the equivalent total inductance as a function of the location of Via 3 is shown in Fig. 6. As Via 3, the second shorting via is moved in proximity to Via 1, the equivalent total inductance becomes smaller. This is due to the increased mutual

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The inductance matrix with the two shorting vias, as in (15), is approximated in the closed form as

(21)

represents the self-inductance of a via, and, where and represent the mutual inductances between Via 1 and Via 2, between Via 1 and Via 3, and between Via 2 and Via 3, respectively. Since Via 1 and Via 2 are fixed, and Via 3 is moved, is constant, but and vary. If the distance between Via 1 and Via 2 is , (20) is the expression for the mutual inductance . The expressions for and can be rewritten as

(22) Fig. 6. Contour plot of the normalized equivalent total inductance. It is normalized to the equivalent total inductance with just Via 1 and shorting Via 2, 167.4 pH. Via 1 and Via 2 are fixed, while Via 3 is moved around in the parallel-plane pair.

inductance between Via 1 and Via 3 that results in a smaller equivalent total inductance since the currents on the two vias are in the opposite directions. Conversely, the equivalent total inductance increases abruptly as the second shorting via, Via 3, is moved close to the first shorting via, Via 2. This is also due to the increased mutual inductance between the two shorting vias that results in a larger equivalent total inductance since the currents on the two shorting vias are in the same direction. The effect of the mutual inductance will be discussed in detail using closed-form equations in Section III-B.

(23) where and represent the distances between Via 1 and Via 3, and between Via 2 and Via 3, respectively. Following the same procedures from (15) to (18) and substituting the self-inductance and mutual inductance with the closed-form expressions in (19), (20), (22), and (23), the 2 2 equivalent inductance maand the equivalent total inductance are derived in trix closed form as

(24) and

B. Closed-Form Expressions for Simple Cases Closed-form expressions for the equivalent total inductance can be derived for simple cases. As seen in Fig. 3(a), the self-inductance of a via between two parallel planes is almost the same regardless of the via location if the planes are sufficiently large and the via location is not adjacent to the corners or edges. Closed-form expressions can then be used instead of (5) within approximately 10% difference, when the distance between a via and plane edges is larger than a quarter of the plane dimensions and . Under these conditions, the closed-form expressions for the self via inductance and mutual via inductance in a rectangular parallel-plane pair have been developed in [20] as

(19) (20) where and represent the plane dimensions, is the dielectric is the distance thickness, is the radius of the via(s), and between two vias.

(25) Equation (25) can be used to estimate the value of the equivalent total inductance seen into the port at Via 1 with two shorting vias at any locations, if the planes are sufficiently large, and the vias are located away from the plane edges and corners. The equivalent inductances in (24) and (25) illuminate some essential physics with regard to the equivalent inductance when adding decoupling capacitors in a PDN design in multilayer PCBs with planes for power and power return. Consider the two shorting vias located in a circle with its center at Via 1. Via 2 is fixed, and Via 3 is moved along the circle, as shown in Fig. 7. Since the distance between Via 1 and Via 3 is the same is equal to , as that between Via 1 and Via 2,

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Fig. 7. Simple case where two shorting vias, Via 2 and Via 3, are located in a circle with its center at Via 1. Via 2 is fixed, and Via 3 is moved around the circle.

and

can be written as a function of the rotation angle as . Equation (24) can be further simplified to

(26) and the equivalent total inductance (25) is expressed with only as

(27) From (26), is just equal to , the self via inductance, and and are also just equal to , the mutual inductance between Via 1 and a shorting via. The important physics is that , the equivalent self-inductance of two parallel shorting vias, which carry currents in the same direction, is larger than , the mutual inducone-half . It is increased by one-half tance between the two shorting vias. It indicates that, when adding another parallel via, the effect of mutual inductance be, is added. Therefore, when the vias tween the vias, are located close to each other, and the mutual inductance between vias is close to the via self-inductance, the number of vias dehas very little effect. From a design perspective, adding coupling capacitors does not reduce the equivalent self-induc, by tance of the parallel vias for the capacitor connection, , the number of capacitors, rather, something greater. The equivalent total inductance as a function of is plotted in Fig. 8 for , and mm, respectively. The inductance values at 0 are calculated assuming there is only one shorting Via 2, in other words, Via 3 is not present. The lines are calculated directly from (27), and the circles represent the values obtained through the procedures from (15)–(18) using the cavity inductance expression (5). The two methods agree very well, indicating the assumptions of large planes and central via locations are satisfied in these test cases. with the two The equivalent total inductance value and shorting vias decreases as increases since decrease. decreases logarithmically, but never goes to one-half of that with a single shorting Via 2 because both

Fig. 8. Equivalent total inductance calculated from the closed-form expression (27) and calculated through the procedures from (15)–(18) using the cavityinductance formula (5) for the test case shown in Fig. 7. Three different radii R for the rotation of Via 3 are considered.

do not change at all. Even when the two shorting and , the equivalent vias are on the opposite sides, i.e., total inductance value is approximately 70% of that with one shorting via for the three values. On the other hands, when the radius for the via rotation decreases, the mutual inductance increases. between Via 1 and two shorting vias then decreases, as given in (27). It physically indicates the equivalent total inductance decreases, as the vias that carrying currents in the opposite directions are in proximity. Two practical cases are also tested, as shown in Fig. 9. The second shorting via of Via 3 is moved away from the first shorting via of Via 2 either horizontally, as in Fig. 9(a), or vertically, as in Fig. 9(b). The equivalent total inductances in between Via 2 and both cases as a function of the distance Via 3 are plotted in Fig. 10. In both cases, the values from the closed-form expression (25) are in good agreement with those obtained using the cavity inductance formula. Similarly, the equivalent total inductance increases when the second shorting via is moved close to the first shorting via. Equations (25) and (27) give a quick guideline for the placement of two vias with the same current direction, and can be used for engineering designs. IV. EXPERIMENTAL VALIDATION AND DISCUSSIONS Test patterns were manufactured to corroborate the extraction approach of via inductances presented earlier. Each test vehicle consists of a 10 cm 10 cm board with a single plane pair, as shown in Fig. 11(a). The separation between the planes was 0.8 mm. The -parameters were measured at a port located at (5 cm, 5 cm) from the lower left corner using a GS microprobe with a 250- m pitch, and a vector network analyzer (VNA), and the input impedance was then extracted. The parasitic effects of the probe and cable for measurement were removed with a short, open, load, thru (SOLT) calibration method. The vias consist of a circular thru-hole barrel with a diameter

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Fig. 9. Other test cases for two shorting vias of Via 2 and Via 3, where: (a) Via 3 is moved away from Via 2 horizontally and, (b) Via 3 is moved away from Via 2 vertically.

Fig. 10. Comparison of the equivalent total inductance calculated from the closed-form expression (25) and calculated through the procedures from (15)–(18) using the cavity-inductance formula (5) for the test cases shown in Fig. 9.

of 300 m, and the diameters for the via pad and via antipad are 600 and 900 m, respectively. Four different test patterns, as illustrated in Fig. 11(b), were studied. One pattern only consists of a thru-hole via at the measurement port. The other patterns include a single shorting via, or two shorting vias with a 30 angle, or two shorting vias with a 180 angle, in addition to the via at the measurement port. The input impedances for the four cases were determined from measurements, and inductance values were extracted from the resonance frequencies of the measured impedance to corroborate the calculated inductances from the cavity model. The lumped circuit model is simply given as a series – circuit for the first test pattern including the measurement port only, according to Fig. 2(c). The input impedance has the characteristics of a series – circuit, as shown in Fig. 12(a), with a series resonance frequency of (28) The capacitance is calculated as 487 pF from the geometry using the parallel-plate capacitance expression. The values of the inductance can then be extracted from the measured resonance frequency using (28). The inductance value extracted from the

Fig. 11. Test patterns for corroboration with measurement. (a) Test board geometry. (b) Four different test patterns.

measurement was 925 pH, and is larger than the via self-inductance of 839 pH, calculated from (5) using the test geometry. The difference is due to the nonideal excitation of energy into the via port. The nonideal effect was investigated using a 3-D FEM full-wave solver for two different port excitation conditions. One excitation consisted of a small lumped port across the via antipad, and the other was a waveguide port injecting the energy into the overall area of the antipad, as shown in Fig. 12(b). The port condition with the small lumped port is similar to the probing in the measurement, whereas the waveguide port corresponds to the current distribution in the analytical (5), where the current distribution at the port is uniform around the periphery of the via. The inductance value simulated with the lumped port was larger than that simulated with the waveguide port by 50–120 pH, depending on the size of the lumped port.

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Fig. 12. (a) Input impedance plots of the test pattern in Fig. 11 including the measurement port only. One is from measurement, and the other is from the series L–C circuit model. (b) Two-port conditions investigated using a 3-D FEM full-wave solver. (c) Lumped circuit model of the test pattern with the measurement port only.

The difference between the inductance extracted from measurement and the via self-inductance calculated from (5) arises from the different current distributions at the excitation port between the measurement and theory, which is calculated as 86 pH, as depicted in Fig. 12(c). In Fig. 12(a), the measurement agrees well with the lumped circuit model with a capacitance of 487 pF and an inductance of 925 pH, which should be the sum of the via and the inductance from the probing disself-inductance . continuity The lumped circuit model topology is shown in Fig. 13(a) for the test patterns with shorting via(s). The contributions of and , which the two shorting vias are combined into represent the equivalent self-inductance of the two shorting vias, and the equivalent mutual inductance between Via 1 and the two shorting vias, respectively, as expressed in (26) for the structure with large planes. The input impedance is inductive at low frequencies, which is the equivalent total inductance defined

Fig. 13. (a) Equivalent lumped circuit model for the test pattern in Fig. 11 including both Port 1 and shorting via(s). (b) Magnitude curves of the input impedance from the measurements and the circuit model. (c) Phase curves of the input impedance from the measurements and the circuit model.

in (18). The total inductance for the circuit in Fig. 13(a) also includes the additional probing inductance. As the frequency increases, there is a parallel – resonance followed by a series – resonance, as shown in Fig. 13(b). The resonance frequencies are determined as

(29) (30)

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TABLE I EQUIVALENT INDUCTANCES (L ;L ) FROM CALCULATION, MEASUREMENTS, AND A 3-D FEM SOLVER

Fig. 14. Test geometry for decoupling placement and IC pin map study.

and can then also be calculated from the resonance , and frequencies of (29) and (30) using the values of shown in Fig. 12(c). The extracted and values are summarized in Table I for the three different shorting-via configurations, where the 0 angle case refers to the case with one shorting via only. The measured values are in good agreement with the calculated values using (5) and (15)–(18) for all the cases. In addition, the same procedure has been done using the impedance curves obtained from a full-wave solver in order to corroborate more completely. The inductance values extracted using the full-wave solver are also compared in Table I. Finally, the magnitude and phase of the impedance values from the measurement and lumped circuit model using the calculated inductance values are plotted in Fig. 13(b) and (c). The inductive im” are also plotted together. The measurepedances from “ ment and circuit models agree well, except for the peak values at the resonance frequencies, because losses were neglected in the circuit model. The sensitivity of the – parallel resonance (29) with regard , can be to the mutual inductance between two shorting vias, derived as (31) Equation (31) indicates that the sensitivity of the parallel resonance frequency (29) with regard to is from around 0.13 to 0.25, depending on the value of . It means a 1% difference in the resonance frequency value corresponds values. If the to a 4%–8% difference in the extracted factor is large for the resonances, it is possible to measure the resonance frequency accurately with a fine frequency steps from the VNA. Since a frequency step of 250 kHz was used in the measurements to find the first parallel resonance frequency near 250 MHz, the resolution ratio for the resonance frequency is approximately 0.1%. The inductive input impedance at the low-frequency range , below resonance frequencies is equal to the impedance of as shown in Fig. 13(b). As described in Section III, it is shown

and decreases, as inin Fig. 13(b) and Table I that is not a function of since the distance becreases, but tween Via 1 and the two shorting vias is constant. However, if the distance between Via 1 and the two shorting vias decreases, increases and decreases, as expressed in (27). then Meaningful design guidance can then be developed for the multiple via arrays in PCBs. Multiple parallel vias carrying currents at the same direction should be placed as far away from each other as possible, without increasing the distance to the via carrying the opposite current. Conversely, the vias carrying opposite currents should be placed as closely as possible for more effective decoupling. V. APPLICATION TO DECOUPLING AND IC PIN MAP DESIGN The procedures developed in the previous sections for the equivalent inductances can be generalized and extended to the cases with multiple vias. An example geometry consisting of two via groups is illustrated in Fig. 14. The vias in Group 1 are densely located at a position, and the vias in Group 2 are located around the periphery of the first via group. The corresponding lumped circuit model is shown in Fig. 15(a), where a mutual inductance exists between any two vias. The vias in each group have a current in the same direction and constitutes a parallel merged port. If the number of vias in and , the relationship between the voltages each group is and via currents are expressed as

(32)

where the elements in the matrix are calculated using (5). Referring to Fig. 15(a), the voltages across the set of inductors , and that in Group 2 is denoted as in Group 1 is denoted as . If Group 1 shares the current , and Group 2 shares the matrix can be reduced to a current , the 2 2 matrix, similar to (15)–(18) as

(33)

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Fig. 16. Test cases with: (a) different configurations of decoupling layout and (b) different configurations of IC power pins.

Fig. 15. (a) Lumped circuit model for the geometry shown in Fig. 14. (b) Simplified equivalent lumped circuit model with multiple vias in each group combined.

where Equation (33) is rewritten using a 2 matrix as

TABLE II EQUIVALENT INDUCTANCE MATRICES FOR THE TEST CASES SHOWN IN FIG. 16

, and . 2 equivalent inductance

(34) The lumped circuit model corresponding to (34) is shown in Fig. 15(b). and denote the equivalent via self-inductance of Group 1, the equivalent via self-inductance of Group 2, and the equivalent mutual inductance between the two via groups, respectively. Test cases with different configurations of Group 1 and Group 2 are shown in Fig. 16(a) and (b), respectively. The top and bottom planes of the PCB are power return and power layers, respectively. The Group 1 vias correspond to power vias connected to an IC, and Group 2 correspond to power vias connected to decoupling capacitors. The IC has a package size of 35 mm 35 mm and it is connected to the bottom power plane by 38 power vias. Decoupling capacitors are located 12.7 mm away from the IC package and are also connected to the bottom power plane in order to provide charge for IC switching. The power-return vias for the IC and decoupling capacitors are not considered because they are connected to the top plane and do not contribute to the field between the two parallel plates in these test cases. The values of the equivalent inductance matrix and the equivalent total inductance are summarized in Table II for all the conis the equivalent inductance associfigurations in Fig. 16. ated with the multiple IC power vias, while is the equivalent inductance associated with the multiple power vias for decoupling capacitors. Comparing the inductance matrices of changes significantly, while the three cases in Fig. 16(a),

remains the same. In addition, the change in the equivalent mutual inductance is negligible. With four decoupling cais pacitors located around the periphery of the IC pins, reduced to approximately one-quarter of that of a single decoupling capacitor because the mutual inductance between the capacitor vias is quite small, but when the four decoupling capacis much itors are located in proximity, the reduction in smaller because the relatively large mutual inductance between the capacitor vias, which carry the currents in the same directions, is added as shown in (26). Similarly, for the cases shown in Fig. 16(b), 21 densely packed vias has a similar value of to seven vias spaced around the periphery of a rectangle, which is 57.4 and 57.0 pH. The 21 densely packed case has more vias than the seven sparse case, but the mutual inductance among vias is also larger since they are densely located. Consequently, the mutual inductance cancels the effect of the number of vias, as explained in Section III-B, and the equivalent inresults in similar values for both cases. These ductance observations confirm again that multiple parallel vias carrying currents in the same direction should be placed as far away from is approximately each other as possible. In all the cases, the same because the average distance between the IC vias and the decoupling capacitor vias are approximately constant. The structure of Fig. 14 includes only one pair of parallel plates, and

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there are no power-return vias. For the multilayer case, which has multiple parallel planes and the power-return vias as well, an alternating and dense configuration of power and power-return vias has a better performance since the currents are opposite, and their mutual inductances reduce the total inductance. This study indicates that not only the number of decoupling capacitors or the number of IC power pins is a dominant factor that determines the high-frequency performance of the PDN, but also their placement. The approach developed in this paper can provide an engineering direction to facilitate such designs. VI. CONCLUSION Parasitic via inductances are important for signal/power integrity and electromagnetic interference analyses. An extraction approach for via inductances is proposed in this paper based on the cavity model. Both self-inductance and mutual inductance can be systematically obtained with closed-form expressions. In a bounded cavity, mutual inductance between two vias can be negative. The related physics is explained from the perspective of magnetic field energy. An equivalent total inductance is introduced to combine the contributions of multiple vias to quickly assess the effectiveness of multiple via arrays. Procedures have been developed to obtain the equivalent total inductance from the extracted via inductances. In addition, closed-form expressions of the equivalent total inductance are derived for some simple cases, and their engineering implications are discussed. The approach proposed in this paper is corroborated with test vehicles, and the accuracy of measurements is analyzed. The application of the approach in PDN design is illustrated. Multiple vias carrying currents in the same direction should not be placed close to each other, but the vias carrying opposite currents should be placed as closely as possible for more effective decoupling. The approach proposed in this paper can be used as a tool to facilitate engineering designs, and can be applied to a larger and more complex power bus. Combined with the segmentation technique, the lumped circuit model for a multilayer planar power bus with arbitrary shapes can be built by connecting circuit models for each rectangular parallel plate in a manner that the field continuity conditions are enforced in a circuit manner. The equivalent inductance matrices between multiple via groups can also be used when connecting each segment, which greatly reduces the model complexity. REFERENCES [1] T. Sudo, H. Sasaki, N. Masuda, and J. L. Drewniak, “Electromagnetic interference (EMI) of system-on-package (SOP),” IEEE Trans. Adv. Packag., vol. 27, no. 2, pp. 304–314, May 2004. [2] L. D. Smith, R. E. Anderson, D. W. Forehand, T. J. Pelc, and T. Roy, “Power distribution system design methodology and capacitor selection for modern CMOS technology,” IEEE Trans. Adv. Packag., vol. 22, no. 3, pp. 284–291, Aug. 1999. [3] T. H. Hubing, J. L. Drewniak, T. P. Van Doren, and D. M. Hockanson, “Power bus decoupling on multilayer printed circuit boards,” IEEE Trans. Electromagn. Compat., vol. 37, no. 2, pp. 155–166, May 1995. [4] X. D. Cai, G. L. Costache, R. Laroussi, and R. Crawhall, “Numerical extraction of partial inductance of package reference (power/ground) planes,” in Proc. IEEE Int. Electromagn. Compat. Symp., Aug. 1995, pp. 12–15.

[5] A. E. Ruehli and A. C. Cangellaris, “Application of the partial element equivalent circuit (PEEC) method to realistic printed circuit board problem,” in Proc. IEEE Int. Electromagn. Compat. Symp., Aug. 1998, pp. 182–187. [6] B. Archambeault, “Using the partial element equivalent circuit (PEEC) simulation technique to properly analyze power/ground plane EMI decoupling performance,” in Proc. 16th Annu. Rev. Progr. Appl. Comput. Electromagn., Mar. 2000, vol. 1, pp. 423–430. [7] X. Ye, D. M. Hockanson, M. Li, Y. Ren, W. Cui, J. L. Drewniak, and R. E. DuBroff, “EMI mitigation with multilayer power-bus stacks and via stitching of reference planes,” IEEE Trans. Electromagn. Compat., vol. 43, no. 4, pp. 538–548, Nov. 2001. [8] K. Li, M. A. Tassoudji, S. Y. Poh, M. Tsuk, R. T. Shin, and J. A. Kong, “FDTD analysis of electromagnetic radiation from modules-on-back plane configuration,” IEEE Trans. Electromagn. Compat., vol. 37, no. 3, pp. 326–332, Aug. 1995. [9] K. Lee and A. Barber, “Modeling and analysis of multichip module power supply planes,” IEEE Trans. Compon., Packag., Manuf. Technol. B, vol. 18, no. 4, pp. 628–639, Nov. 1995. [10] Y. T. Lo, W. Solomon, and W. F. Richards, “Theory and experiment in microstrip antennas,” IEEE Trans. Antennas Propag., vol. AP-7, no. 2, pp. 137–145, Mar. 1979. [11] Y. Jeong, A. C. W. Lu, L. L. Wai, W. Fan, B. K. Lok, H. Park, and J. Kim, “Hybrid analytical modeling method for split power bus in multilayered package,” IEEE Trans. Electromagn. Compat., vol. 48, no. 1, pp. 82–94, Feb. 2006. [12] J. Kim, Y. Jeong, J. Kim, J. Lee, C. Ryu, J. Shim, M. Shin, and J. Kim, “Modeling and measurement of interlevel electromagnetic coupling and fringing effect in a hierarchical power distribution network using segmentation method with resonant cavity model,” IEEE Trans. Adv. Packag., vol. 31, no. 3, pp. 544–557, Aug. 2008. [13] S. Hsu and R. Wu, “Full-wave characterization of a through hole via in multilayered packaging,” IEEE Trans. Microw. Theory Tech., vol. 43, no. 5, pp. 1073–1081, May 1995. [14] P. C. Cherry and M. F. Iskander, “FDTD analysis of high frequency electronic interconnection effects,” IEEE Trans. Microw. Theory Tech., vol. 43, no. 10, pp. 2445–2451, Oct. 1995. [15] H. Kim, J. Kim, Y. Jeong, J. Park, and J. Kim, “Analysis of via distribution effect on multi-layered power/ground transfer impedance of high-performance packages,” in Proc. IEEE 11th Electr. Perform. Electron. Packag. Top. Meeting, Oct. 2002, pp. 171–174. [16] C. L. Holloway and E. F. Kuester, “Net and partial inductance of a microstrip ground plane,” Proc. IEEE Trans. Electromagn. Compat., vol. 40, no. 1, pp. 33–46, Feb. 1998. [17] J. Fan, J. L. Drewniak, and J. L. Knighten, “Lumped circuit model extraction for vias in multilayer substrates,” IEEE Trans. Electromagn. Compat., vol. 45, no. 2, pp. 272–280, May 2003. [18] C. R. Paul, Introduction to Electromagnetic Fields. New York: WCB/ McGraw-Hill, 1997. [19] F. W. Grover, Inductance Calculations: Working Formulas and Tables. New York: Dover, 1946. [20] J. Fan, W. Cui, J. L. Drewniak, T. P. Van Doren, and J. L. Knighten, “Estimating the noise mitigation effect of local decoupling in printed circuit boards,” IEEE Trans. Adv. Packag., vol. 25, no. 2, pp. 154–165, May 2002. [21] Y. Zhang, J. Fan, A. R. Chada, and J. L. Drewniak, “A concise multiple scattering method for via array analysis in a circular plate pair,” in Proc. Elect. Design Adv. Packag. Syst. Symp., Dec. 2008, pp. 143–146. [22] L. Ren, J. Kim, G. Feng, B. Archambeault, J. L. Knighten, J. Drewniak, and J. Fan, “Frequency-dependent via inductances for accurate power distribution network modeling,” in Proc. IEEE Int. Electromagn. Compat. Symp., Aug. 2009, pp. 63–68. [23] J. Kim, J. Kim, L. Ren, J. Fan, J. Kim, and J. L. Drewniak, “Extraction of equivalent inductance in package-PCB hierarchical power distribution network,” in Proc. IEEE 18th Elect. Perform. Electron. Packag. Syst. Conf., Oct. 2009, pp. 109–112. [24] J. Kim, M. D. Rotaru, S. Baek, J. Park, M. K. Iyer, and J. Kim, “Analysis of noise coupling from a power distribution network to signal traces in high-speed multilayer printed circuit boards,” IEEE Trans. Electromagn. Compat., vol. 48, no. 2, pp. 319–330, May 2006. [25] M. Mondal, S. Connor, B. Archambeault, and V. Jandhyala, “Including the impact of connecting vias in the performance metric evaluation for board-level optimization of decoupling capacitors,” in Proc. IEEE Elect. Perform. Electron. Packag. Top. Meeting, Oct. 2008, pp. 177–180.

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[26] C. Wang, J. Mao, G. Selli, S. Luan, L. Zhang, J. Fan, D. J. Pommerenke, R. E. Dubroff, and J. L. Drewniak, “An efficient approach for power delivery network design with closed-form expressions for parasitic interconnect inductance,” IEEE Trans. Adv. Packag., vol. 29, no. 2, pp. 320–334, May 2006. [27] T. Okishi, Y. Uehara, and T. Takeuchi, “The segmentation method-an approach to the analysis of microwave planar circuit,” IEEE Trans. Microw. Theory Tech., vol. MTT-24, no. 10, pp. 662–668, Oct. 1976. [28] S. Chun, M. Swaminathan, L. Smith, J. Srinivasan, Z. Jin, and M. K. Iyer, “Modeling of simultaneous switching noise in high speed systems,” IEEE Trans. Adv. Packag., vol. 24, no. 2, pp. 132–142, May 2001. [29] M. Swaminathan and A. E. Engin, Power Integrity Modeling and Design for Semiconductors and Systems. Westford, MA: Prentice-Hall, 2007, ch. 1. [30] C. Wang, J. Mao, G. Selli, S. Luan, L. Zhang, J. Fan, D. J. Pommerenke, R. E. Dubroff, and J. L. Drewniak, “An efficient approach for power delivery network design with closed-form expressions for parasitic interconnect inductances,” IEEE Trans. Adv. Packag., vol. 29, no. 2, pp. 320–334, May 2006. [31] K. F. Lee and W. Chen, Advances in Microstrip and Printed Antennas. New York: Wiley, 1997, ch. 5. [32] W. F. Richards and Y. T. Lo, “A wide-band multiport theory for thin microstrip antennas,” in Proc. IEEE Int. Antennas Propag. Symp., Jun. 1981, pp. 7–10. [33] Y. Zhang and J. Fan, “An intrinsic circuit model for multiple vias in an irregular plate pair through rigorous electromagnetic analysis,” IEEE Trans. Microw. Theory Tech., 2010, accepted for publication.

Jingook Kim (M’09) received the B.S., M.S., and Ph.D. degrees in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 2000, 2002, and 2006, respectively. He has worked on power/signal integrity, package modeling in gigahertz systems, as well as electromagnetic interference (EMI)/EMC design. From 2006 to 2008, he was a member of the DRAM design team, Memory Division, Samsung Electronics, as a Senior Engineer, where his main responsibilities in-

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clude high-speed I/O circuit designs with a focus on power and signal integrity. In 2009, he joined theMissouri S&T EMC Laboratory, Missouri University of Science and Technology (formerly University of Missouri–Rolla), Rolla, as a Postdoc Fellow. His current research interests include PDN modeling and design at the chip/package/PCB levels, IC EMC, and RF interference.

Liehui Ren (S’09) received the B.S. degree in electrical engineering from the University of Science and Technology of China, Hefei, China, in 1998, the M.S. degree from the Chinese Academy of Sciences, Beijing, China, in 2001, and currently working toward the Ph.D. degree in the electrical and computer engineering from the Missouri University of Science and Technology (formerly University of Missouri–Rolla), Rolla. His research interests include PDN analysis and design, power integrity, and RF interference.

Jun Fan (S’97–M’00–SM’06) received the B.S. and M.S. degrees in electrical engineering from Tsinghua University, Beijing, China, in 1994 and 1997, respectively, and the Ph.D. degree in electrical engineering from the University of Missouri–Rolla in 2000. From 2000 to 2007, he was with the NCR Corporation, San Diego, CA, as a Consultant Engineer. In July 2007, he joined the Missouri University of Science and Technology (formerly the University of Missouri–Rolla), where he is currently an Assistant Professor with the Missouri S&T EMC Laboratory. His research interests include signal integrity and EMI designs in high-speed digital systems, dc power-bus modeling, intra-system EMI and RF interference, PCB noise reduction, differential signaling, and cable/connector designs. Dr. Fan was the chair of the IEEE EMC Society TC-9 Computational Electromagnetics Committee from 2006 to 2008. He was a Distinguished Lecturer of the IEEE EMC Society in 2007 and 2008. He is currently vice chair of the Technical Advisory Committee of the IEEE EMC Society. He was the recipient of an IEEE EMC Society Technical Achievement Award in 2009.

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A Methodology for Combined Modeling of Skin, Proximity, Edge, and Surface Roughness Effects Brian Curran, Member, IEEE, Ivan Ndip, Member, IEEE, Stephan Guttowski, Member, IEEE, and Herbert Reichl, Fellow, IEEE

Abstract—A methodology is introduced for modeling resistive losses in planar transmission lines that support the transverse electromagnetic mode. The methodology aims to accurately and systematically account for these losses by modeling the skin, proximity, edge, and surface roughness effects in a combined way. The results show a correlation with three measurements within 5%, and offer insight into the different sources of resistive losses at high frequencies. Considering a printed coplanar line as an example, approximately 8% of the resistive loss come from surface roughness, and 30% from the edge effects at 60 GHz. However, for a line with a higher conductivity metallization, this increases to 38% and 30%, respectively, from surface roughness and edge effects at only 20 GHz. Index Terms—Conductor modeling, edge effects, surface roughness, transmission line.

I. INTRODUCTION N RECENT years, not only integrated circuit (IC) technology, but also packaging and assembly have shown a trend toward greater miniaturization. The speed of electronic products has increased as well, with data rates approaching 100 Gb/s. At higher frequencies, skin and proximity effect can cause current crowding, in some cases, into narrow angles and surface roughness profiles. Since these effects may lead to signal integrity problems, especially at microwave frequencies, they must be accurately modeled at the beginning of the design process. Surface roughness effects were first modeled by Hammerstad and Jensen [1]. In these models, the surface roughness is represented by a series of pyramids, with 60 angles, along a conductor surface. As the skin-depth decreases below the height of the surface roughness, the current meanders over and around the peaks and valleys. Hall et al. uses a similar approach, with hemispheres instead of pyramids [3]. Hammerstad and Jensen [1], Groiss et al. [2], Hall et al. [3], and Luki’c and Filipovic [4] all

I

Manuscript received January 22, 2010; revised May 26, 2010; accepted May 30, 2010. Date of publication August 09, 2010; date of current version September 10, 2010. This work was supported in part by the Fraunhofer Society. B. Curran is with the Fraunhofer Institute for Reliability and Microintegration (IZM), Berlin 13355, Germany (e-mail: [email protected]). I. Ndip, S. Guttowski, and H. Reichl are with the Fraunhofer Institute for Reliability and Microintegration (IZM), Berlin 13355, Germany, and also with the School of Electrical Engineering and Computer Sciences, Technical University Berlin, Berlin 10623, Germany. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2010.2058271

introduce correction factors that can be applied to the conductor attenuation or surface resistivity to model the effect of surface roughness. Some full-wave techniques have also been proposed. For example, Luki’c and Filipovic [4] and Chen [5] have simulated roughness profiles in a box using full-wave solvers. The full-wave techniques presented until now (that discretize roughness in 3-D) simulate a tiny piece of a specific roughness profile, not arbitrary transmission line structures. Furthermore, full-wave techniques have very long computation times. Analytical models also have various limitations, for example: 1) each has a saturation frequency [3]; 2) modeling heterogeneous roughness can be challenging; 3) roughness on the reference conductor, which is often different to the signal conductor roughness, is often neglected or assumed to be the same as the roughness on the signal conductor; 4) any low-frequency effects of surface roughness are neglected; and 5) current models are not adaptable to different shapes of roughness. Hall et al. and Luki’c and Filipovic both present photographs of roughness profiles with many different shapes and characteristics. Roughness can be triangular, rounded, or square, and it is often inhomogeneous over a cross section or in the longitudinal direction [3], [4]. For example, a printed line on ceramic may have roughness on the top, but not the bottom, or a dielectric may have roughness added to improve adhesion. A summary of the state-of-the-art models and their limitations is presented by the authors in [6]. An adapted filament model was proposed by the authors in [7] and [8] to be applied outside the limitations of the other models and will be discussed more later. Accounting for edge effects (nonrectangular cross sections) has also been a topic of research. Barsotti et al. uses a modified incremental induction rule to account for edge effects [9], [10]. Holloway and Kuester [11] and Ghione et al. [12] use a conformal mapping technique. In [13], Guo et al. use an analytical model. These techniques are often cumbersome and impractical, or they have questionable bandwidths and neglect various effects. Most commonly, edge effects are modeled with a full-wave solver, which has its own limitations. For example: 1) very narrow angles or large aspect ratios can lead to very long computations times and solutions that do not converge; 2) they lack the physical insight for analysis of results and optimization; and 3) full-wave simulations, in general, are more time intensive than analytical solutions. It is not always clear when and where the different techniques can be applied. The goal of this paper is to introduce a broad methodology that includes the different modeling techniques, dependent on examined frequency band and conductor geometry, for modeling and analysis of resistive loss mechanisms. A

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skin-effect models. The combination of these models must coincide with their capabilities. The methodology is a way of balancing accuracy and simplicity, but without neglecting an effect that contributes to the conductor losses in a structure. A. Define Transmission Line Structure and Determine the Transmission Line Effects

Fig. 1. Methodology for modeling nonideal transmission lines.

state-of-the-art model is used to demonstrate the methodology by showing the different loss mechanisms over a large frequency range.

II. METHODOLOGY FOR MODELING ROUGH TRAPEZOIDAL TRANSMISSION LINES Based on a complete evaluation of state-of-the-art modeling techniques for surface roughness and transmission lines with nonrectangular cross sections, a modeling methodology has been developed. The methodology, shown in Fig. 1, is necessary because the various models have different limitations, advantages, and disadvantages. Another reason why a methodology is necessary is that the different surface roughness models must be used together with

The first step to modeling a transmission line with a nonideal conductor is to define the transmission line segment to be modeled. An input port and output port, where the segment begins and ends, are assigned. The goal of this step in the methodology is to determine each of the effects in the transmission line segment that will affect the conductor losses. These effects have been divided into three categories. 1) Determination of the Surface Roughness Heights and Shapes: The root-mean-square surface roughness heights can be measured, or in the case of another configuration where the line surface is not exposed, like a stripline or embedded microstrip, then a cross section of the line can be cut and the height can be measured or approximated. In some cases, the manufacturer specifications provide this information for the fabrication technology. If the height of roughness is much smaller than the distance between the peaks, then the conductor can be called a smooth conductor. Since this is not normally determined with rms surface roughness height measurements, it is often best understood with a scanning electron microscope image of the surface of the conductor. The shape of the roughness can be determined by looking at a cross section or the surface of the conductor. For example, some technologies will result in spherical nanoparticle agglomerates [14] on the conductor surface or some treatments will result in rounded roughness rather than triangular. 2) Determination of Roughness Distribution: Roughness may be measured on the top face of the conductor, which normally will not match the bottom of the conductor. Measurements or approximations of the roughness on each face of the conductor must be made separately. The roughness distribution will play a role in its impact. Longitudinal roughness (roughness in the direction of propagation) changes are also examined. Often, with uniform transmission line geometries, the roughness characteristics will not change in the longitudinal direction, but, if it changes, then it needs to be included during modeling. 3) Determination of the Current Distribution: In some cases, this step is very simple. With a quick calculation of the skin depth at the highest operating frequency, if it is much larger than the thickness of the conductor, nothing more may be necessary. Ideally, a cross-sectional current distribution plot of the transmission line with the proximity effects and edge effects for the highest applicable frequency is generated. For example, just by glancing at the current distribution of a wide microstrip, one can see that roughness on the bottom surface will have more impact on the transmission line parameters. B. Combined Transmission Line Analysis With Appropriate Techniques Based on the information in the previous steps, a technique or techniques for transmission line analysis can be chosen. The

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Fig. 3. (top) Current distribution in a microstrip with substrate height = 2:5 m, conductor width = 10 m, and conductor thickness = 2 m, f = 50 GHz. (middle) Same microstrip with a disturbed current flow on the

top surface. (bottom) Same microstrip with a disturbed current flow on the bottom surface.

H = 0:5 m and f = 1 GHz. (b) Current f = 50 GHz (darker areas have more current

Fig. 2. (a) Current distribution for distribution for m and and lighter areas less).

H = 1

analysis can also be divided into different frequency ranges and the analysis separately conducted. Essentially, there are three cases. Case 1: Over a frequency range that the skin depth is much larger than the height of the surface roughness ( >> ), surface roughness can be neglected altogether. This also applies in a case where current only minimally flows through the surface with roughness. In this case, the surface roughness will not significantly affect the transmission line parameters. Even for electrically thin conductors with significant roughness, the average height can be used to model the conductor losses. The Ansoft High Frequency Structure Simulator (HFSS) current density diagrams shown in Fig. 2 demonstrate this difference. The figures are a side view of a conductor where the current is flowing in the direction of the arrow. In Fig. 2(a), the current flows through the bulk of the conductor because the skin depth, 2 m, is about four times the peak-to-peak surface roughness height, 0.5 m. In contrast, Fig. 2(b) shows a skin depth that is about 1/3 the peak-to-peak surface roughness height. In Fig. 2(b), the roughness peaks and valleys act as discontinuities to the current propagation, which will affects the conductor resistance. Therefore, in the second case, the surface roughness must be accounted for, and we can move to another case. Case 2: In the first case, the roughness was neglected. In the second case, it can no longer be neglected, but it can be broadly and the curapproximated. When the skin-depth rent propagates almost exclusively through one roughness profile, then an analytic technique can be separately applied to analyze the conductor losses. In this case, the skin and proximity effects can be modeled in a traditional way, either with analytical equations or a numerical solver. The surface roughness can then be accounted for with a correction factor formula like the Hammerstad or Groiss models. The skin depth must be less

than 0.75 because above this frequency, the traditional surface roughness correction factors begin to saturate [6]. The current can only travel through one roughness profile because the roughness is being modeled separately from the current distribution in the conductor. An example of this case is shown in Fig. 3 (the diagrams are generated with a filament model programmed in MATLAB). Fig. 3 (top) shows the current density in a microstrip transmission line. If we disturb the current flow along the top surface, to approximate roughness only on the top surface, as in Fig. 3 (middle), there is almost no difference from the ideal case in Fig. 3 (top). However, when the current flow is disturbed along the bottom surface, there is a significant difference. In this example, we could apply an analytical correction factor to the ideal line resistance using only the bottom surface roughness height (ignoring the roughness on the top surface) because a large majority of the current flows on the bottom surface. Another example where this applies is a symmetrical stripline or coplanar line with the same roughness profiles on the top and bottom of the line. In this case, the current is evenly distributed on the top and bottom surfaces so only that roughness profile is necessary for analysis. In practical transmission lines, these cases are not common. Higher permittivity dielectrics have led to narrower microstrips. Asymmetric striplines and adjacent conductors are common in modern microelectric devices. Therefore, another case is necessary. Case 3: In the final case, we must still make approximations to model the roughness, but the calculations are more rigorous. When the environment inside the conductor is more complex (inhomogeneous roughness, arbitrary proximity effects, edge shape effects, etc.) and the frequencies are higher, other modeling techniques must be used. A modeling approach that models the roughness and the current density in a combined way must be used to model the transmission line nonidealities. For example, the microstrip in Fig. 3 was a wide micristrip, and therefore, the current was concentrated almost completely on the bottom surface. Fig. 4 shows microstrip current densities at different substrate heights. The largest height, Fig. 4 (top),

CURRAN et al.: METHODOLOGY FOR COMBINED MODELING OF SKIN, PROXIMITY, EDGE, AND SURFACE ROUGHNESS EFFECTS

Fig. 4. Current density in a microstrip with different heights (f : . (middle) h=w (top) h=w : . (bottom) h=w : .

=15

=05

= 0 33

= 20 GHz).

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The frequency range under examination must lie in the region where skin depth is smaller than the conductor thickness, but that solution is only valid until the frequency where the correction factor begins to saturate—the technique only works inside that frequency window. Solving inside the conductor will significantly extend the simulation time. In some cases, achieving a converged solution for the conductor attenuation while solving inside the conductor exceeds the computations capabilities of commercial solvers. In general, this approach is not practical. For Case B, when the transmission line structure lies outside the limitation of the full-wave modeling technique, the adapted filament model has been presented by the authors in [7] and is very briefly summarized in Section II-C. Other approaches have been presented. For example, another technique that partially models inhomogeneous roughness, combined with current distribution, was presented in [15]. This model, however, is only applicable to stripline structures. C. Validations and Development of Technology and Structure Specific Circuit Models

Fig. 5. Transmission lines requiring simultaneous roughness current density modeling. (a) Uneven stripline. (b) Trapezoidal coplanar. (c) Asymmetric coplanar.

shows a more even distribution between the bottom and top surfaces, as does the microstrip in Fig. 4 (middle). Therefore, in the case of a narrower microstrip line, when these different conductor surfaces have different surface roughness heights, they must be separately considered. Furthermore, until now we have only considered microstrip configurations, but, other structures like, but not limited to, Fig. 5(a), an asymmetrical stripline, Fig. 5(c), an asymmetrical coplanar line, or Fig. 5(b), a trapezoidal coplanar would also require a model that simultaneously models the current distribution and roughness. There are different possibilities to do this. In Case A, full-wave simulations can be used. Using a fullwave solver, a correction factor can be applied to the surface resistivity. In this case, a new correction factor should be applied to the surfaces separately wherever there are different roughness characteristics. The rule applies again, that the skin depth >0.75 for the Hammerstad and Groiss formulas because they begin to saturate. However, the simulation must be very carefully designed so that the conductor characteristics converge to a stable solution. For example, for transmission lines with large width to thickness ratios, these simulations could last a very long time and still not produce results that are accurate over a broad frequency band. Additionally, when only the surface of the conductor is solved (and no mesh is generated inside the conductor) during a full-wave simulation, the conductor losses are not correctly modeled for lower frequencies.

After the transmission line segment has been modeled, the predicted characteristics can be compared with -parameter measurements. At this point, a correction factor can be extracted for future applications. The adapted filament model offers the flexibility to alter the model for different types of roughness profiles. The Hall roughness correction factor, for example, can also be applied as more geometrical information about the roughness is assembled. These updated and refined models can then be applied during simulations of a specific fabrication technology or for specific structures. III. COMBINED CONDUCTOR CURRENT DENSITY AND SURFACE ROUGHNESS ANALYSIS In this section, the traditional filament model and the adapted filament model will be summarized because this is the technique that is used to model the transmission lines during the validation. One method that is used to determine the current density in the cross section of the conductor is the filament method. This method, for example, generated the diagrams in Figs. 3 and 4. A review of skin effect and proximity effect modeling, including the filament method, is presented by the authors in [16]. Vu Dinh first presented the filament method to model the skin effect in [17] and subsequently the skin and proximity effect in [18]. Mei and Ismail have proposed model order reduction techniques for the filament model in [19]. Mido and Asada uses the filament model to model ideal microstrip lines with reflection theory in [20]. The filament model divides the cross section of a conductor into elementary volume cells. These conductors are small enough that the current distribution of each of these conductors can be approximated as uniform. The filament model calculates the resistance and inductance in each of these branches, which is an impedance representation of each volume cell, and uses Kirchoff’s Voltage Rule to solve for the total impedance of the conductor. From the self-inductances and mutual inductances, and the resistances of each volume, a ladder circuit can be constructed and computed for the conductor.

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Fig. 6. Approximate 2-D discretization of a trapezoidal coplanar transmission line [8]. Fig. 8. Photograph of transmission line 1.

Fig. 7. Discretization on the surface of a conductor with surface roughness [8].

The filament model can be altered for a planar transmission line with a nonrectangular cross section, as in Fig. 6. In Section IV, the discretizations are similar to Fig. 6. A computer program can then solve for resistance and inductance after a ladder circuit is constructed. For small transmission line geometries, the filament model can compute the current distribution, resistance, and inductance for a transmission line into the multigigahertz range with an accuracy of over 90% [16]. To account for surface roughness, another alteration can be applied to the filament model. As described by the authors in [7], the resistance of the outside filaments can be altered, in the form of a resistance gradient. To account for the roughness profiles in the lateral and the longitudinal direction, the resistance gradient increases exponentially as it approaches the surface of the conductor. The technique is conceptually similar to the Hammerstad model. However, while the Hammerstad model calculates a modified conductor attenuation (or an effective resistance) for the entire conductor or conductor face at high frequencies, the adapted filament model calculates a modified resistance only for the individual filaments that are affected by the surface roughness profile. For example, if the surface roughness profile height was equal to one filament height, and homogeneous across the conductor top surface, then the shaded filaments in Fig. 6 would have an effective resistance higher than their ideal resistance. Model validation up to 20 GHz is shown by the authors in [8]. The model functions as long as the filament heights and widths are smaller than the skin depth. A systematic approach for building the resistance gradient is presented by the authors in [7]. This gradient was designed for a typical roughness profile that is approximately sawtooth shaped, as in Fig. 7. However, when the roughness has a unique shape that results from a specific technological process or treatment, then a custom gradient can be designed for that technology. IV. MEASUREMENTS AND MODELING OF THE TRANSMISSION LINE RESISTANCE In this section, two transmission lines are used to demonstrate various elements of the methodology. The transmission lines

are printed coplanar lines on glass substrates. Profile measurements of the transmission lines with topography measurement tools (using a mechanical probe for the first transmission line, an interferometer for the second transmission line) have determined the roughness characteristics. Since they are printed, the lines have trapezoidal cross sections. The lower angles have also been determined with the profile measurement. Conductivities of the metallization pastes were determined with dc measurements, using the Van Der Pauw method [21]. We have assumed that the bottom roughness of the metallization is similar to the roughness of the glass, which is very small (less than 50 nm), but the measured roughness across the top of the metallization ranges from 0.25 to 0.5 m. Therefore, the transmission lines have inhomogeneous roughness. For these reasons, the transmission lines fall under Case 1 or Case 3 during the combined analysis part of the methodology in Fig. 1, depending on the frequency range during the analysis. This section examines a large frequency range to differentiate through modeling and measurements Case 1 and Case 3. The modeling in this section uses the adapted filament model for two reasons, which are: 1) the large frequency range begins where >> , excluding a 3-D full-wave simulation where only the surface of the conductor is meshed (leading to Case 3B in the methodology) and 2) we aim to examine the per-unit-length resistance of the TEM mode, which is very easily calculated with the adapted filament model (1) -parameters were measured with an Agilent vector network analyzer (VNA) using ground–signal–ground (GSG) probes with 150- m pitch from Cascade. The analyzer was calibrated with a standard impedance substrate from Cascade using the line-reflect-reflect-match (LRRM) method. The transmission lines were 30 and 15 mm in length, respectively, on a 1-mm-thick glass substrate that was placed directly on the chuck. The resistance of the measured lines was extracted from the -parameter measurements with (1). A moving avwas erage program was then applied to the measurements. calculated analytically. Note that in the modeling, because the dc and high-frequency ohmic losses are very high, and the dielectric loss tangent is , the dielectric losses from the meavery low surements have been neglected. Quick analytical calculations suggest that, at the highest modeled frequencies, the dielectric losses would constitute less than 2% of the overall losses. Fig. 8 shows the first coplanar waveguide that will be modS/m. The dimeneled. The measured conductivity sions are reflected in the diagram. The thickness m.

CURRAN et al.: METHODOLOGY FOR COMBINED MODELING OF SKIN, PROXIMITY, EDGE, AND SURFACE ROUGHNESS EFFECTS

Fig. 9. Modeling and measurement of transmission line 1. (1) Iideal transmission line. (2) Trapezoidal transmission line. (3) Trapezoidal line with roughness. (4) Measurement.

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Fig. 11. Modeling and measurement of the coplanar waveguide from Fig. 12. (1) Only skin-depth. (2) Ideal transmission line. (3) Trapezoidal transmission line. (4) Trapezoidal line with roughness. (5) Measurement [8].

line and frequencies are very high, it can be neglected when the . skin depth is more than approximately 5 V. MEASUREMENTS AND MODELING OF THE TRANSMISSION LINE INDUCTANCE Fig. 10. Third printed coplanar-waveguide sample.

The surface roughness on the top is 0.46 m and the lower angles of the metallization are 25 (based on profile measurements). Fig. 9 shows the modeling and measurement of the first coplanar line. The modeling shows that, despite the fact that the surface roughness height is significant; the roughness has only a small effect, even into the multigigahertz range because the conductivity is smaller, meaning a smaller skin and proximity effect. In Fig. 9, the roughness begins to show an effect around 40 GHz. At 40 GHz, the skin depth is approximately ( peak-to-peak rms surface roughness height). The edge effects first play a role at 20 GHz. Fig. 10 shows the second coplanar-waveguide sample that is investigated. This line has a much higher conductivity, S/m. In this case, the angles were 4.8 , the roughness was 0.5 m, and the thickness, , was 3 m. These results are the same transmission line sample used by the authors in [8], to validate the model, but with a higher diecretization in the return current conductors, to achieve better matching. In this case, one can expect that the different effects will begin at much lower frequencies than with transmission lines 1 and 2. Fig. 11 shows this phenomenon. In this coplanar waveguide, the surface roughness effect is ) and the introduced as early as 2 GHz (at this point, edge effects at 500 MHz. In fact, skin depth alone accounts for only a small fraction of losses at 20 GHz and transmission line nonidealities account for a majority of losses at around 7 GHz. These investigations differentiate Case 1 in the methodology. Even when roughness is a significant part of the transmission

In circuit modeling, the conductor of a transmission line is represented by two parameters, the resistance, dealt with in Section IV, and the inductance. Inductance is closely related to the delay of a transmission line, and a proper relationship between the resistance and inductance is necessary to preserve causality for wide band transient simulations of high-speed digital circuits. We begin with a high-frequency inductance for an ideal conductor slab, calculated using the filament model. This . Using the seed inductance is assigned the variable inductance and the frequency dependent resistance , to ensure causality, the frequency dependent inductance should follow (2). Reference [22] is the frequency-dependent resistance that was calculated in Section IV (2) To verify the inductance, a different transmission line was used than in the resistance example. The lateral dimensions were identical to the coplanar line in Fig. 3, but a shorter line length mm was used. This short line was used to be cerof tain that it was electrically short enough so that the quasi-static approximation could be applied when the inductance was extracted from the measurements. The inductance was extracted from -parameter measurements using a -model (3). The disadvantage of the short coplanar line is that the measurement is not a smooth curve (3) The results of the modeling and the measurement are shown in Fig. 12. We see a much closer agreement between the modeling and the measurements when the roughness and the trape-

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Fig. 12. Inductance of a coplanar transmission line. (1) Measured values. (2) Calculated values including surface roughness and edge shape effects. (3) Calculated values assuming an ideal rectangular transmission line without surface roughness.

zoidal cross section are included in the calculations. The difference is largest at low frequencies and decreases at higher frequencies. At 200 MHz, 1 GHz, and 20 GHz, the roughness and nonrectangular cross sections result in an inductance that is 22%, 12%, and 6% higher, respectively. VI. CONCLUSION When modeling conductor losses in a transmission line at high frequencies, it is necessary to consider all of the different effects that contribute to the losses. Furthermore, it is important to understand the limitations of the available modeling options. Therefore, in this work, a methodology has been introduced based on a complete investigation of state-of-the-art modeling techniques. This methodology has been illustrated using three modeling examples for coplanar lines. The investigations show that when accurate geometrical information is available, then accurate modeling is possible, but only when the limitations of modeling techniques are considered and the response is predicted with techniques that are appropriate for that structure. Roughness, for example, can be neglected when the skin depth . At higher frequenis more than approximately five times cies, the distribution of the roughness and the bandwidths of the transmission line models and roughness models are all important considerations. ACKNOWLEDGMENT The authors thank V. Zoellmer and C. Werner, both with the Fraunhofer Institute for Manufacturing Technology and Applied Materials Research, Bremen, Germany, for providing the printed test structures. The authors would also like to thank H. Wolf and H. Gieser, both with the Fraunhofer Institute for Reliability and Microintegration, Munich, Germany, for their measurement results. REFERENCES [1] E. Hammerstad and O. Jensen, “Accurate models for microstrip computer-aided design,” in IEEE MTT-S Int. Microw. Symp. Dig., May 1980, pp. 407–409.

[2] S. Groiss, I. Bardi, O. Biro, K. Preis, and K. R. Richter, “Parameters of lossy cavity resonators calculated by the finite element method,” IEEE Trans. Magn., vol. 32, no. 1, pp. 894–897, May 1996. [3] S. Hall, S. G. Pytel, P. G. Huray, D. Hua, A. Moonshiram, G. A. Brist, and E. Sijercic, “Multigigahertz causal transmission line modeling methodology using a 3-D hemispherical surface roughness approach,” IEEE Trans. Microw. Theory Tech., vol. 55, no. 12, pp. 2614–2624, Dec. 2007. [4] M. V. Lukic and D. S. Filipovic, “Modeling of 3-D surface roughness effects with application to -coaxial lines,” IEEE Trans. Microw. Theory Tech., vol. 55, no. 3, pp. 518–525, Mar. 2007. [5] X. Chen, “Em modeling of microstrip conductor losses including surface roughness effect,” IEEE Microw. Wireless Compon. Lett., vol. 17, no. 2, pp. 94–96, Feb. 2007. [6] B. Curran, I. Ndip, S. Guttowski, and H. Reichl, “On the quantification and improvement of the models for surface roughness,” presented at the IEEE Signal Propag. Interconnects Workshop, Strasbourg, France, May 2009. [7] B. Curran, I. Ndip., S. Guttowski, and H. Reichl, “The combined modeling of skin, proximity, and surface roughness effects with an adapted filament model,” presented at the 7th Int. IEEE Electromagn. Compat. Integr. Circuits Workshop, Toulouse, France, Nov. 2009. [8] B. Curran, I. Ndip, S. Guttowski, and H. Recihl, “Modeling and measurement of coplanar transmission lines with signficant proximity and surface roughness effects,” presented at the Eur. Microw. Conf., Rome, Italy, Oct. 2009. [9] E. L. Barsotti, J. M. Dunn, and E. F. Kuester, “Strip edge shape effects on conductor loss calculations using the Lewin/Vainshtein method,” Electron. Lett., vol. 26, pp. 983–985, Jul. 1990. [10] E. L. Barsotti, E. F. Kuester, and J. M. Dunn, “A simple method to account for edge shape in the conductor loss in microstrip,” IEEE Trans. Microw. Theory Tech., vol. 39, no. 1, pp. 98–106, Jan. 1991. [11] C. L. Holloway and E. F. Kuester, “A quasi-closed form expression for the conductor loss of CPW lines, with an investigation of edge shape effects,” IEEE Trans. Microw. Theory Tech., vol. 43, no. 12, pp. 2695–2701, Dec. 1995. [12] G. Ghione, M. Goano, and M. Pirola, “Exact, conformal-mapping models for the high-frequency losses of coplanar waveguides with thick electrodes of rectangular or trapezoidal cross section,” presented at the IEEE MTT-S Int. Microw. Symp., Jun. 1999. [13] J. Guo, A. W. Glisson, and D. Kajfez, “Skin-effect resistance of conductors with a trapezoidal cross section,” Microw. Opt. Technol. Lett., vol. 18, no. 2, pp. 387–389, Feb. 1998. [14] C. Werner, V. Ruttkowski, M. Maiwald, V. Zoellmer, J. Bahr, G. Domann, H. Wolf, H. Gieser, B. Curran, I. Ndip, and F. Oehler, “Design, direct write deposition and characterization of multilayer systems for customized electronic test applications,” presented at the Eur. Adv. Mater. Congr. Exhibition, Glasgow, U.K., Sep. 2009. [15] A. Koul, P. K. R. Anmula, M. Y. Koledintseva, J. L. Drewniak, and S. Hinaga, “Improved technique for extracting parameters of low-loss dielectrics on printed circuit boards,” in IEEE Int. Electromagn. Compat. Symp., Aug. 2000, pp. 191–19. [16] B. Curran, I. Ndip, S. Guttowski, and H. Reichl, “On the quantification of the state-of-the-art models for skin-effect in conductors, including those with non-rectangular cross-sections,” presented at the IEEE Electromagn. Compat. Symp., Austin, TX, Aug. 2009. [17] T. Vu Dinh, B. Cabon, and J. Chilo, “New skin-effect equivalent circuit,” Electron. Lett., vol. 26, pp. 1582–1584, Sep. 1990. [18] T. Vu Dinh, B. Cabon, and J. Chilo, “Time domain analysis of skin effect on lossy interconnections,” Electron. Lett., vol. 26, pp. 2057–2058, Dec. 1990. [19] S. Mei and Y. I. Ismail, “Modeling skin effect with reduced decoupled R–L circuits,” in Proc. Int. Circuits Syst. Symp., May 2003, pp. IV-588–IV-591. [20] T. Mido and K. Asada, “An analysis on VLSI interconnection considering skin effect,” in Proc. Asia and South Pacific Design Automat. Conf., Feb. 1998, pp. 403–408. [21] L. J. van der Pauw, “A method of measuring the resistivity and Hall coefficient on Lamellae and arbitrary shape,”,” Philips Tech. Rev. J., vol. 20, no. 8, pp. 220–224, 1958/59. [22] T. Liang, S. Hall, H. Heck, and G. Brist, “A practical method for modeling PCB transmission lines with conductor surface roughness and wideband dielectric properties,” in IEEE MTT-S Int. Microw. Symp. Dig., 2006, pp. 1780–1783.

CURRAN et al.: METHODOLOGY FOR COMBINED MODELING OF SKIN, PROXIMITY, EDGE, AND SURFACE ROUGHNESS EFFECTS

Brian Curran (M’09) received the B.S. degree in electrical engineering from the University of Rochester, Rochester, NY, in 2001, the M.Sc. degree in electrical communications engineering from the University of Kassel, Kassel, Germany, in 2008, and is currently working toward the Ph.D. degree at the Technical University of Berlin, Berlin, Germany. Since 2008, he has been a Research Engineer in the RF and High-Speed System Design Group, Fraunhofer Institute for Reliability and Microintegration (IZM) Berlin. His main research interest is interconnect modeling, analysis and design for RF/high-speed applications.

Ivan Ndip (M’05) received the M.Sc. (Dipl.-Ing.) degree and Ph.D. (Dr.-Ing.) degree (with the highest distinction, summa cum laude) in electrical engineering from the Technical University (TU) Berlin, Berlin, Germany, in 2002 and 2006, respectively. In 2002, he joined the Fraunhofer-Institute for Reliability and Microintegration (IZM), Berlin, Germany, as a Research Engineer, where he was involved in signal integrity modeling and design of system packages and boards, as well as on antenna design and integration. From 2003 to 2005, he was also affiliated with the Chair for High-Frequency Electronics, University of Paderborn, Paderborn, Germany. In 2005, he became a Group Manager. He developed novel concepts that led to the formation of a new research group at Fraunhofer IZM, the RF and High-Speed System Design Group, in February 2006. Since then, he has head this group, where he is responsible for leading a team of research engineers, as well as for developing and leading research projects that focus on modeling, design, and optimization of RF/high-speed modules, integrated antennas, and passive RF front-end components. Since 2008, he has also been a Lecturer with the Department of High-Frequency and Semiconductor System Technologies, School of Electrical Engineering and Computer Sciences, TU Berlin. He is currently engaged in teaching graduates courses on the application of electromagnetic field theory for high-frequency design and measurement of electronic packaging and system-integration structures. He has authored or coauthored over 70 publications. He is a Reviewer for many international journals including the Journal on the Progress in Electromagnetics Research (PIER), Wiley’s International Journal of Numerical Modeling: Electronics Networks, Devices and Fields, and the Institution of Engineering and Technology (IET)’s Electronic Letters. Dr. Ndip cochairs the Signal and Power Integrity Committee of the International Microelectronic and Packaging Society (IMAPS). He is a reviewer for the IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY. He is a member of the European Microwave Association (EuMA) and the German Association for Electrical, Electronic and Information Technologies (VDE). He is also a member of the Technical Program Committee of the IEEE Electrical Design of Advanced Package and Systems Symposium (EDAPS), the IEEE Asia–Pacific EMC Symposium (APEMC), and the International Symposium on Microelectronics. He was the recipient of five Best Paper Awards presented at leading international conferences. He was also a recipient of the Tiburtius Prize, awarded yearly for outstanding Ph.D. dissertations of Berlin, Germany.

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Stephan Guttowski (M’95) received the M.Sc. (Dipl.-Ing.) and Ph.D. (Dr.-Ing.) degrees in electrical engineering from the Technical University (TU), Berlin, Germany, in 1994 and 1998, respectively. From 1998 to 1999, he was a Postdoctoral Research Fellow with the Massachusetts Institute of Technology (MIT), where was the Head of the research unit that explored the consequences of the new 42-V-systems on the electromagnetic compatibility within future passenger cars. In 1999, he joined the Research Laboratory for Electric Drives, DaimlerChrysler AG, Berlin, Germany, where he was involved with the prediction of electromagnetic emission of electrically driven vehicles. In October 2001, he joined the Fraunhofer Institute for Reliability and Microintegration (IZM), Berlin, Germany, where he was the Head of the Advanced System Development Group from 2002 to 2005, and since January 2006, has been the Head of the Department of System Design and Integration. He has authored or coauthored extensively in the area of electrical design of electronic packages and boards for high-performance miniaturized systems.

Herbert Reichl (M’89–SM’97–F’01) received the M.S. and Ph.D. degrees in electrical engineering from the Technical University, Munich, Germany. He is currently the Director of Fraunhofer Institute for Reliability and Microintegration (IZM), Berlin, Germany, with over 260 full-time employees—one of the leading institutes in the field of microelectronics and microsystem packaging worldwide. He is also a Professor of Electronic Packaging and Interconnection Technologies, Technical University, Berlin, Germany, where he also heads the Research Center for Microperipheric Technologies. For the past two decades, he has been engaged in the development and application of innovative packaging and system integration technologies with activities in the field of material and characterization, design, and simulation, as well as high-density interconnect and wafer-level packaging, chip and board interconnection technologies, 3-D-packaging and vertical chip integration, mechatronics, micromechanical systems, reliability and failure analysis, environmental engineering, polymer materials and composites, and polytronic and flexible systems. He has authored or coauthored over 900 papers and six books. Dr. Reichl is a member of the Program Committees and a member of Advisory Boards of a number of national and international conferences. He chairs the SMT/hybrid/Packaging Conference and Exhibition. He is also the Head of the working group “Heterogeneous Integration” of the Nanoelectronics Platform European Nanoelectronics Initiative Advisory Council (ENIAC) and a member of the Scientific Committee of the EUREKA Industrial Initiative MEDEA . He was the recipient of the Order of Merit of the Federal Republic of Germany in 2000. For his eminent contribution to research and development with Fraunhofer-Gesellschaft, he was the recipient of its highest award, the Fraunhofer Muenze in 2005. Also in 2005, the IEEE Components, Packaging and Manufacturing Technology Society awarded him with a Special Presidential Recognition (in recognition of his lifetime of technical achievement in microelectronics as a scholar, mentor, and global leader). In recognition of his contributions to the international electronics industry, he was presented with the iNEMI International Recognition Award in 2005. In 2006, he was the recipient of the highest German Association for Electrical, Electronic, and Information Technologies (VDE) Award, and in 2007, he was the recipient of the Electronics Manufacturing Technology Award.

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Ku

A Full -Band Reduced-Height Waveguide-to-Microstrip Transition With a Short Transition Length Hyun-Seok Oh and Kyung-Whan Yeom, Member, IEEE

Abstract—A systematic design of a full -band reduced-height waveguide-to-microstrip transition using commercial High Frequency Structure Simulator software is presented. The basic transition is composed of a shorted microstrip probe to a 50ridge waveguide. An impedance transformer necessary to adapt the 50- ridge waveguide to a reduced-height waveguide was designed using multistage short-length ridge waveguides connected in cascade. The resulting transition length is 6.2 mm. The separately designed shorted microstrip probe transition and impedance transformer were combined and adjusted for -band operation. The combined transition was fabricated fulland measured. The measured insertion and return losses are about 0.41 dB and below 15 dB for the full-band, respectively.





Index Terms— -plane probe, reduced-height waveguide, ridge waveguide, transition.

I. INTRODUCTION AVEGUIDES are widely used as radiating elements in array antennas due to their low-loss characteristic. A reduced-height waveguide is formed by reducing the height of a standard waveguide, providing a drastic size reduction of a waveguide array antenna while preserving the waveguide mode. The width and height of our reduced-height waveguide are 15.6 and 2 mm for the -band, respectively. However, most microwave integrated circuits for processing received signals from an array antenna have generally been constructed based on a microstrip design. For the connection between a microwave integrated circuit and waveguide array antenna, a reduced-height waveguide-to-microstrip transition is essential. Depending on their application, waveguide-to-microstrip transitions can be largely categorized into two types: straight transitions and right-angle transitions [1]. In our application, a right-angle reduced-height waveguide-to-microstrip transition with a transition length shorter than 9 mm is required. In a right-angle transition, the thickness of the microwave integrated circuit module is determined by the transition length. A thicker microwave integrated circuit module generally results

W

Manuscript received March 18, 2010; revised June 21, 2010; accepted June 29, 2010. Date of publication August 09, 2010; date of current version September 10, 2010. This work was supported by the Korean Government under National Research Foundation of Korea Grant KRF-2010-0016934. The authors are with the Department of Radio Science and Engineering, Chungnam National University, Daejeon 305-764, Korea (e-mail: [email protected]; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2010.2058251

in a thicker array antenna assembly. In a mechanically driven antenna, a thicker array antenna assembly often creates limitations, particularly on the search angle, which is one of the most important parameters in an array antenna. A similar application can be found in [2]. The insertion loss of a transition below 0.5 dB and return loss below 15 dB were required over the full -band for system interface and sensitivity. The design of a reduced-height waveguide-to-microstrip transition does not require a new concept, as most of the design aspects come from a standard waveguide-to-microstrip transi. However, the bandtion since the dominant mode is still widths of a reduced-height waveguide-to-microstrip transition tend to be narrow to cover the full waveguide band [3]–[6], and performances close to a standard waveguide-to-microstrip transition have rarely been achieved. The narrow bandwidth of reduced-height waveguide-to-microstrip transitions is believed to come from a backshort appearing in the transitions. The tolerance is also critical in a reduced-height waveguide-to-microstrip transition due to the drastically reduced height. In this paper, we begin by presenting the design of a microstrip-to-50- -ridge-waveguide transition with a shorted microstrip probe. A multistage short-length ridge waveguide transformer is then employed for the desired reduced-height waveguide input. The design was mostly carried out using a High Frequency Structure Simulator (HFSS), a commercial electromagnetic (EM) simulation software package from the Ansoft Corporation [7]. A full-band transition can be successfully obtained through a coupling adjustment between the transformer and probe transition.

II. TRANSITION DESIGN

A. Design of a Shorted Microstrip Probe Transition For a wideband transition, the field shapes and characteristic impedances of the two guides defined on a voltage-to-current basis should be close. The voltage-to-current definition is adopted because it is known to work best in transition designs [8]. Thus, the electric field distributions of a ridge waveguide, reduced-height waveguide, and microstrip were investigated.Fig. 1(a) shows a ridge waveguide formed in a of the reduced-height waveguide. Width and height ridge were chosen to yield a 50- impedance. Fig. 1(b) shows a sectional view of a 50- microstrip enclosed in a metal

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= 14 = = 3 45 =4 = 08 = 0 254 +

Fig. 1. (a) Sectional view of a ridge waveguide: width a mm, height b : mm, spacing d : mm, and ridge width s : mm. (b) Microstrip : mm, mm, height H enclosed in a metal box: metal box width W microstrip width w : : mm, substrate thickness h mm (10 mil), and permittivity " : . (c) Electric field distributions of jE j jE j at 1-W input power. A reduced-height waveguide (RHWG) with the same a and b values is employed in the computation.

15

= 0 59 = 0 408 =22

box. The substrate used for the microstrip has a thickness of 0.254 mm (10 mil) and permittivity of 2.2. The electric fields of the reduced-height waveguide, ridge waveguide, and microstrip were computed using Ansoft’s HFSS at a frequency of 15 GHz. The electric field intensity of the ridge , and waveguide along the -axis at a ridge height of that of the reduced-height waveguide at the center height, are shown in Fig. 1(c). In plotting the electric field intensities, the -axis normalized by was used. The dominant mode of the mode as in a stanreduced-height waveguide is still the dard waveguide, and its electric field intensity shows a half-period sinusoidal distribution, although the intensity is increased more than in a standard waveguide. Unlike the reduced-height waveguide, the electric field of the ridge waveguide is found to be concentrated around the ridge, and the peak electric field appears at the ridge edges. For the electric field intensity plot of the is used for microstrip, the -axis normalized by box width the microstrip. The microstrip shows a similar shape of electric field intensity as in the ridge waveguide; however, the electric field is more concentrated at the microstrip edges. Furthermore, the characteristic impedance of the ridge waveguide is generally almost constant and less dependent on the frequency than that of the reduced-height waveguide. The ridge waveguide can also be designed to be 50 , which is adequate for easy matching with a microstrip. Thus, the implementation of a wideband ridge-waveguide-to-microstrip transition is considered to be easier than a reduced-height waveguide-to-microstrip transition. Fig. 2(a) shows a front view of a ridge-waveguide-to-microstrip transition with a shorted microstrip probe. The substrate

Fig. 2. (a) Front and (b) side views of a ridge-waveguide-to-microstrip tran: mm, mm, height b : mm, probe width w sition: width a : mm, probe slot height h : mm and width, probe height h : mm, and RHWG backshort length l : mm. Other dimenw sions are given in Fig. 1.

= 0 24

= 14 = 0 65

= 15

= 0 36 = 4 85

= 39

used for the shorted microstrip probe is the same as that in Fig. 1(b). Microstrip width was set for a 50- impedance. is slightly wider than the ridge width. The wider Probe width probe width is used to provide a close field match between the probe and ridge waveguide because the peak value of the electric field of the ridge waveguide shown in Fig. 1(c) appears at a position slightly away from the ridge edge. Another field in the probe was match can be obtained using slot . Slot chosen considering that the electric field intensity at the center of the ridge is smaller than that of the ridge edges. This leads to a possible removal of part of the conductor pattern at the probe center. Fig. 2(b) shows a sectional side view of the transition. Note that the backside metal of the microstrip exposed to the was designed waveguide was removed. Backshort length to be about a quarter-wavelength so as to maximize the electric can be determined field at the microstrip probe. Length by the distance where the maximum electric field intensity appears using the standing wave pattern plot for the given reduced-height waveguide. of the microstrip metal enclosure was first set so Width cutoff frequency of the rectangular waveguide that the formed by and is sufficiently higher than 18 GHz, which -band. The width was set to is the high-end frequency of a 4 mm, which provides a second-order mode cutoff frequency of about 34.7 GHz. The second-order mode cutoff frequency was

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obtained using the port calculation utility in HFSS. The aperture of the microstrip enclosure perturbs the maximum electric field position to the backshort. To select an appropriate height , EM simulation was carried out for an empty metal enclosure where the microstrip substrate was removed with the port set to the radiation condition. Height was set to minimize the maximum electric field position difference to the backshort. Thus, the height was determined to be 0.8 mm. and the aperture size, probe height After fixing length can be tuned using HFSS so that impedance seen from the microstrip port yields close to 50 . The reference plane was chosen, as shown in Fig. 2(b). Initially, was determined without a slot. Further improvement in the return-loss bandwidth was achieved by tuning the probe slot dimensions using was fixed to 0.24 mm and a fixed . In tuning, slot width slot height was tuned. Fig. 3(a) shows the insertion and return losses of the transition shown in Fig. 2 (Transition A). For comparison, the insertion and return losses were also plotted for a transition composed of a 50- ridge waveguide backshort and a probe without a probe slot (Transition B). Transition A shows a smaller insertion loss for a wider bandwidth, and the return loss at the band edge is improved, although the return loss is degraded at the center compared with Transition B. Transition B shows that the return loss was above 15 dB at the band edge due to the low impedance of a 50- ridge waveguide. The reduced-height waveguide backshort provides generally higher impedance than the 50- ridge waveguide backshort, which helps to implement a wider return-loss bandwidth. A backshort implemented with a waveguide of larger height yields larger characteristic impedance and may be better for a wider bandwidth transition; however, this may result in a transition oversized in height. Taking the size increase of a microwave integrated circuit module into consideration, the backshort was implemented using a reduced-height waveguide, as shown in Fig. 2(b). Apart from the consideration of the oversized microwave integrated circuit module, an increase of backshort height does not always provide a wider 15-dB returnloss bandwidth. This is shown in Fig. 3(b). A 20-dB return-loss bandwidth is used in the plot rather than a 15-dB bandwidth in order to more easily see the trends. From Fig. 3(b), a wider return loss is obtained with an increase of height up to 2.5 mm, but a height increase above 2.5 mm is not good for a wider bandwidth. B. Design of an Impedance Transformer The previously designed transition has a ridge waveguide input, which is not a desired input type, and a transformer is necessary for the desired reduced-height waveguide input. The return loss of a simple quarter-wavelength ridge waveguide transformer is shown in Fig. 5, which shows a quite narrower 15-dB return-loss bandwidth compared with the transition in Fig. 2. Since our application requires a short transition length below 9 mm, a quarter-wavelength ridge waveguide was replaced by a cascade of short ridge waveguides whose lengths are below a quarter-wavelength for obtaining a wider bandwidth. The front and side views of the transformer are shown in Fig. 4(a) and (b). Section F is a 50- ridge waveguide,

Fig. 3. (a) Insertion and return losses of the transitions. The structure of transition A is shown in Fig. 2. Transition B has a 50- -ridge-waveguide backshort of length l = 5:2 mm and no probe slot. (b) 20-dB return-loss bandwidth for back-short height. Our design point is shown by the hollow rectangle.

and section A is a reduced-height waveguide of about 120 at the center frequency. Variables , , , and denote the waveguide’s width, height, length, and ridge spacing to height, respectively. A subscript corresponding to each subsection is added for distinction. An analytical method has not yet been developed for our ridge waveguide transformer shown in Fig. 4 [10] because of the unknown step discontinuities and inhomogeneous properties of waveguides. Thus, the transformer was designed by tuning the initial design. First, the geometrical mean of the reduced-height waveguide and 50- ridge waveguide impedances, given by , was calculated. The impedance of subsection B, , was then determined using . Similarly, the impedance in subsection D, , was de. With these impedances, termined based on the waveguide widths and ridge heights in subsections B and D can be determined using similar plots to those in Fig. 4(b) for a given and . A fixed ridge width was used in all sections. The waveguide width, height, and ridge height are summarized . Subin Table I. The lengths were set at approximately sections C and E were inserted to improve the bandwidth, and the lengths were set to zero in the initial design. Curve #1 in Fig. 5 shows the simulated return loss for the initial design with . Due to the step discontinuities,

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TABLE II LENGTH VALUES FOR THE TRANSFORMERS IN FIG. 5

Fig. 4. (a) Front and (b) side views of a ridge waveguide transformer.

TABLE I DIMENSIONS OF RIDGE WAVEGUIDES IN THE TRANSFORMER

Fig. 6. (a) Return loss of the combined transition and reactances X and X without tuning. (b) Reactance X and X for optimum return loss. The reactances X and X are the imaginary parts of the impedances when seeing into the transformer and shorted microstrip probe, respectively.

Fig. 5. Return loss of the quarter-wavelength ridge waveguide transformer and return-loss change of the modified ridge waveguide transformer for the tuning of lengths l , l , l , and l . The dimensions of the quarter-wavelength ridge : mm, d : mm, b : mm, and waveguide transformer are a l : mm.

= 68

= 14 5

= 0 960

= 1 75

the return loss at the center frequency was degraded; however, a wider bandwidth possibility is demonstrated. For more degree of freedom, subsections C and E are inserted. After inserting and , lengths and were tuned. This small lengths

is shown in curve #2. Some appreciable bandwidth improvements were found. It should be noted that bandwidth improvement appears mainly above the center frequency. The resulting total length of the transformer was 8.2 mm. Table II summarizes the resulting length values. A separately designed transformer and shorted microstrip probe transition were combined and simulated using HFSS. Due to the combining, the bandwidth becomes narrower than the separate frequency responses. Fig. 6(a) shows the return loss of the combined transition, which is observed to be above 15 dB near the high frequency end. The center frequency is also lowered to about 14.2 GHz. Cohn [8] proposed a method of widening the bandwidth for a coaxial-to-waveguide transition using a cascade of quarter-wavelength ridge waveguide transformers. At probe plane , shown in Fig. 2(b), the backshort shows a parallel resonance and the transformer shows a series resonance. Since the two slopes are converse in frequency, the imaginary parts

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TABLE III LENGTH VALUES IN FIG. 6

of the two impedances can be cancelled, and consequently, a wider bandwidth can be obtained. The separation of two parts, such as the transition and transformer, is not well defined at the probe plane. Thus, the reference plane was receded back into plane , shown in Figs. 2(b) and 4(b). Such a reference plane as clearly defines two parts in an EM simulation. Defining the impedance seeing into the transformer from the reference as the impedance seeing into the backshort inplane and cluding the shorted microstrip probe, the imaginary parts of and were computed using EM simulation and are plotted in and . Fig. 6(a). In Fig. 6(a), shows a negative frequency slope due to the Reactance parallel resonance of the backshort. The negative value of is . plotted in order to find the intersection point of At the intersection point, matching is achieved, which shows a minimum return loss. In Fig. 6(a), matching is found to occur at one point, and the corresponding return loss shows a single minimum value. The return loss at a higher band edge is about 12 dB, which does not satisfy our design objective of a return loss below 15 dB over the -band. On the other hand, when the intersection point full was tuned to a center frequency of 15 GHz, the return loss at the lower band edge was poorer, which again failed to meet our design objective. In order to obtain a wider bandwidth, backshort length was first shortened. The shortened backshort length shifts to the right along the frequency and causes to cut at two points. In order to place two intersection points at a further distance apart, the length of the transformer should be decreased. For this purpose, lengths and were first decreased with lengths and fixed, as in the previous transformer deand makes sign. However, a simple decrease of lengths bend more upward for the frequency. Length was correspondingly increased to prohibit a serious upward bending. This is shown in Fig. 6(b). The corresponding return loss is -band. The length values found to be below 20 dB for a full are summarized in Table III. The resulting total length of the transformer is found to be 6.6 mm, which is shorter than the quarter-wavelength ridge waveguide transformer. C. Structure of Transition The designed transition was constructed, as shown in Fig. 7. The sectional view is shown in Fig. 7(a). The ridge waveguide transformer was implemented in the bottom assembly. The shorted microstrip probe was realized using a 10-mil RT-5880 substrate. The RT-5880 substrate [11] was selected due to its low anisotropy and low-loss characteristics [12]. A microstrip printed circuit board (PCB) was mounted on the top assembly,

Fig. 7. (a) Sectional view of the transition. (b) Front views of the probe assembly.

which acts as a cover for the ridge waveguide in the bottom assembly. A connector assembly composed of a K-connector and glass bead was mounted on a metallic carrier and screwed to the top assembly. The microstrip probe was inserted into a slot machined into the ridge. Both sides of the inserted section of the microstrip probe PCB were plated by metal, and four via-holes were made for a solid connection, as shown in Fig. 7(b). Silver epoxy was filled into the slot and used for a connection between the microstrip probe and ridge. In the previous process, the waveguide and microstrip losses were neglected in the EM simulation. The losses arose from the microstrip PCB, and metallic walls were considered and re-simulated. In the simulation, the corners appearing in the waveguide were rounded with a radius of 0.05 mm for practical machining. The EM simulated frequency response was computed considering the loss and rounding effects. Minor changes appeared in the frequency response. In the EM simulation, the reference plane is set as shown in Fig. 7(a). The HFSS simulation does not include the K-connectors; however, the glass bead is included. The effects of the K-connectors can be removed using thru-reflect-line (TRL) calibration. In the exact sense, the glass bead should not be included because it is not used in the microwave integrated circuit assembly. However, the connection between the glass bead and microstrip does not seem to provide a repeatable performance

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Fig. 8. Photograph of the fabricated transition. The size of the standard -band flange is 33 mm 37 mm. The width and height of RHWG are 15.6 and 2 mm, respectively.

Ku

2

that is sufficient for calibration through an external assembly. Therefore, it was included in the EM simulation.

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Fig. 9. Comparison of the measured and simulated return and insertion losses.

where (2)

III. MEASUREMENT AND COMPARISON

(3)

Fig. 8 shows a photograph of a fabricated transition. For -band standard waveguide flange the transition flange, a was used. For evaluation, two transitions are connected back-to-back. The measured -parameters for the back-to-back connection contain the loss of the K-connectors, which is not necessary for the transition assessment. The effects of the K-connectors can be removed using a TRL calibration in an N5230 network analyzer, [13]. Since a standard K-connector TRL cal kit for this purpose was not available, the back-to-back connection of the K-connectors was used as a thru-measurement, and an open K-connector was used as a reflect measurement. A glass bead was used as a line and was inserted between the two K-connectors for a line measurement. After calibration, the measurement was carried out for a thru connection to check the calibration accuracy. The return loss was below 40 dB. Considering that the return loss for the designed transition is about 20 dB, such calibration accuracy provides reliable measurement results. With the TRL calibration, the -parameters for a back-to-back connection without K-connectors can be obtained. Conventionally, half of the insertion loss for the back-to-back measured results was assessed as transition loss. However, precise -parameters of the transition cannot be obtained because the back-to-back connection prevents information on a mismatch between the two transitions. Thus, a reduced-height waveguide line of 2.5 mm, which is below a quarter-wavelength at 18 GHz, was prepared. The back-to-back connection was measured for the thru data. The connection with the reduced-height waveguide line inserted between the two transitions was measured for the line data. Defining the -parameters and , the electrical of the thru and line measurements as length of the inserted reduced-height waveguide line of length can be computed using [14]

(1)

With the electrical length given by (1), tained as

and

can be ob-

(4) (5) Port 2 was assigned for the coaxial connector side, and the principal values of the square root were chosen for (3) and (5). The sign in (1) is chosen to yield positive real and negative imaginary at parts because length in (1) was chosen to be below 18 GHz. Fig. 9 also shows the measured and EM simulation results when a glass bead is considered. The lower minimum frequency of the return loss shifted to a higher frequency compared with -band, except near 12.4 GHz, Fig. 6(b). However, for a full most of the return loss is found to be below about 20 dB and the insertion loss is flat at about 0.15 dB. The shift is because of the slope due to the added small series reactance when lowered the glass bead is included. Due to the decreased slope, the lower intersection point in Fig. 6(b) moves toward a higher frequency. The measured insertion loss was about 0.43 dB at 15 GHz, which is a reduction of 0.28 dB. We believe this was caused by both the glass-bead-to-microstrip transition and an extra microstrip loss, which is difficult to account for precisely through EM simulation. The measured return-loss trends are similar to those found in the simulation, although the measured return loss shows some discrepancy. The lower null in the return loss moved upward to some degree. The reason for this is believed again to be from the mismatch by the glass-bead-to-microstrip transition, which is not precisely accounted for in the simulation. Fig. 10 shows a comparison with transitions proposed by other researchers. However, some of the transitions were implemented at other waveguide bands. Shevalkova et al.’s transition was for 9–10 GHz [3] and Ahlborn et al.’s transition was for

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Fig. 10. Comparison of the voltage-standing wave ratio (VSWR) of this work with those of previous transitions [3]–[6].

3–5 GHz [5]. Liao et al. implemented a transition for 5–10 GHz [6]. For comparison, a frequency normalization of (6) was carried out. Here, defining the lower and higher frequencies and , and and are given of the waveguide band as by (7) (8) Such normalization as in (7) gives a value of 0.5 for the lower frequency end and 0.5 for the higher frequency end of the waveguide band. Thus, one can ascertain whether the transition is a full-band transition. Using the frequency normalization, our transition shows a full-band characteristic, while the other transitions work only near the center frequency. IV. CONCLUSION A full -band reduced-height waveguide-to-microstrip transition was designed using HFSS, and its performance was demonstrated. The transition was composed of an impedance transformer and shorted microstrip probe. In order to obtain a full-band transition, we separately designed and tuned the transformer and shorted probe. Although the separate designs did not provide a full-band performance, in combination a full-band performance was achieved. We believe the design can be extended to a transition for waveguides with different heights or for other frequency band waveguides. REFERENCES [1] J. S. Izadian and S. M. Izadian, Microwave Transition Design. Norwood, MA: Artech House, 1988, pp. 53–64.

[2] “The RADAR antenna and gimbal of the ALQ-170,” U.S. Navy/Tactical Electronic Warefare Squadron Three-Four (Vaq34), NAS Point Mugu, CA, 1983. [Online]. Available: http://www.vaq34.com/vaq34/ vaqfewsg1.htm [3] L. V. Shebalkova and V. B. Romodin, “Waveguide-to-coaxial transition of reduced height,” in IEEE MEMIA Conf., Novosibirsk, Russia, 2001, pp. 224–225. [4] K. W. Kim, D. S. Woo, and Y. K. Cho, “A conically coupled waveguide-to-coaxial line transition in a reduced-height waveguide reduced height waveguide for compact transceivers,” Microw. Opt. Technol. Lett., pp. 669–673, Apr. 2006. [5] W. G. Ahlborn, H. F. Lenzig, and Y. S. Wu, “Reduced-height waveguide-to-microstrip transition,” U. S. Patent 4901040, Feb. 13, 1990. [6] A. Liao, Q. Wang, B. Wang, and Z. Wang, “Broad-band transition from a coaxial-line to a rectangular waveguide with reduced-height,” in ICMMT ’08, Apr. 2008, pp. 333–334. [7] High Frequency Structure Simulator (HFSS). ver. 11, Ansoft Corporation, Pittsburgh, PA, 2007. [Online]. Available: www.ansoft.com [8] S. B. Cohn, “Design of simple broad-band waveguide-to-coaxial-line junctions,” Proc. IRE, vol. 35, no. 9, pp. 920–926, Sep. 1947. [9] J. Helszajn, Ridge Waveguides and Passive Microwave Components. Piscataway, NJ: IEEE Press, 1988. [10] G. L. Matthaei, L. Young, and E. M. T. Jones, Microwave Filters, Impedance-Matching Networks, and Coupling Structures. New York: McGraw-Hill, 1964. [11] “High Frequency Circuit Material Product Selector Guide,” Rogers Corporation, Rogers, CT, May 2005. [12] “The advantage of nearly isotropic dielectric constant for RT/Duroid 5870-5880 glass microfiber-PTFE composite,” Rogers Corporation, Rogers, CT, Mar. 2003. [13] “Agilent 2-port PNA-L microwave network analyzer N5230A datasheet,” Agilent Technol., Santa Clara, CA, May 2008. [14] D. M. Pozar, Microwave Engineering, 2nd ed. New York: Wiley, 1998, pp. 217–222. Hyun-Seok Oh was born in Seoul, Korea, in 1979. He received the B.S. and M.S. degrees in radio science and engineering from Chungnam National University, Daejeon, Korea, in 2003 and 2007, respectively, and is currently working toward the Ph.D. degree in radio science and engineering at Chungnam National University. His research interests are in the design of hybrid and monolithic microwave circuits and systems.

Kyung-Whan Yeom (M’95) was born in Seoul, Korea, in 1957. He received the B.S. degree in electronics from Seoul National University, Seoul, Korea, in 1980, and the M.S. and Ph.D. degrees in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 1982 and 1988, respectively. From 1985 to 1991, he was with LG Precision, as a Principal Engineer. He worked with the MIC team as a team leader and was involved subsequently in military electronics division for electronic warfare (EW) equipments. From 1991 to 1995, he was with LTI, where he was involved with power amplifier modules for analog cellular phones. In 1995, he joined Chungnam National University as an Assistant Professor. He is currently a Professor with the Department of Radio Science and Engineering, Chungnam National University, Daejeon, Korea. He was the Editor-in-Chief of the Korean Institute of Electromagnetic Engineering and Science (KIEES) from 2004 to 2006. His research interests are in the design of hybrid and monolithic microwave circuits and microwave systems. Prof. Yeom has been a member of KIEES since 1995. He was the recipient of the IR-52 Jang Youg-Sil Prize from MOST of Korea for his research on cell phone power amplifiers at 1994. He was also the recipient of the Academic Award from KIEES for “Design and fabrication of a novel 60 GHz GaAs pHEMT resistive double balanced star MMIC mixer” in 2004.

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Impedance-Transforming Symmetric and Asymmetric DC Blocks Hee-Ran Ahn, Senior Member, IEEE, and Tatsuo Itoh, Life Fellow, IEEE

Abstract—Design formulas of symmetric and asymmetric dc blocks are presented for achieving Chebyshev and Butterworth frequency responses. They can also be used for impedance transformers. Design formulas of symmetric dc blocks are first derived and those of asymmetric dc blocks are also computed based on the symmetric ones. For easy derivation of design formulas of the symmetric dc blocks, coupling coefficient, being proportional to bandwidth, is defined. It is then clarified that symmetric Chebyshev dc blocks are not possible for the impedance transforming. For the symmetric Butterworth dc blocks, three design methods are exploited. To verify the symmetric Butterworth dc blocks, a microstrip dc block with 50- and 25- termination impedances designed at a center frequency of 2 GHz was fabricated. The measured 12 21 and 11 22 are 0.19 and 57 dB around 2 GHz, showing quite good agreement with simulation results. Based on synthesized symmetric dc blocks, the coefficients of transfer function 12 2 are calculated and design formulas of the asymmetric dc blocks are derived based on the symmetric ones. Asymmetric Chebyshev dc blocks are verified by the measurements provided in a previously published paper and asymmetric Butterworth dc blocks by the symmetric Butterworth dc block measured in this paper.

=

=



Index Terms—Impedance-transforming dc blocks, Chebyshev and Butterworth types of dc blocks, coupled-line dc blocks, impedance transformers, symmetric and asymmetric dc blocks.

I. INTRODUCTION

T

HE DC block is a passive component preventing dc current flow, while permitting RF power to flow through. As dc blocks, compact capacitors have been used for many applications. However, as operating frequencies increase, the capacitors have disadvantages, one of which is to produce parasitic elements, which is difficult to handle. In this paper, to overcome the disadvantage, distributed dc blocks with coupled transmission-line sections are proposed for impedance transforming. If the dc blocks can transform termination impedances, the total size of circuits can be reduced [1]–[3]. Impedance-transforming dc blocks are discussed in [4]–[9] and appear with symmetric or asymmetric coupled transmission-line sections for Chebyshev or Butterworth response. For the ring hybrids and branch-line hybrids, symmetric and asymmetric structures [10], [11] are determined depending on the Manuscript received October 20, 2009; revised March 02, 2010; accepted May 10, 2010. Date of publication August 26, 2010; date of current version September 10, 2010. The authors are with the Department of Electrical Engineering, University of California at Los Angeles (UCLA), Los Angeles, CA 90095 USA (e-mail: [email protected]; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2010.2058936

termination impedances. In the dc blocks in this paper, however, the termination impedances are already fixed at asymmetric real values for the impedance transforming and the name of asymmetric or symmetric dc blocks is determined depending on the coupled transmission-line sections used. For the impedance transforming, the employment of the asymmetric coupled transmission-line sections is natural [12]–[15] and it is, therefore, more difficult to design the symmetric dc blocks. The use of the symmetric coupled transmission-line sections is, however, inevitable because the maximum coupling can be achieved with the symmetric coupled transmission-line sections [14], [16]. Due to the design difficulty of impedance-transforming symmetric dc blocks, correct design formulas of the dc blocks have never been derived to date. To avoid confusion in this paper, if the impedance-transforming dc blocks consist of symmetric coupled transmission-line sections for the Chebyshev or Butterworth response, they are called symmetric Chebyshev or Butterworth dc blocks. With the asymmetric coupled transmission-line sections for the Chebyshev or Butterworth response, they are called asymmetric Chebyshev or Butterworth dc blocks. Symmetric or asymmetric dc blocks indicate symmetric or asymmetric dc blocks for both responses. Several attempts have been made for the design of impedance-transforming dc blocks [4]–[9]. In [4], the coupling coefficient is proportional to the square root of the impedance transformation ratio, by which the coupling coefficient can be greater than unity. In [5], there is no design formula provided. In [6], asymmetric Chebyshev dc blocks are very briefly introduced and additional capacitances are found needed for perfect matching. In [7], symmetric Butterworth dc blocks are discussed very briefly in a Korean journal written in Korean. In [8], the symmetric dc blocks are synthesized and it is mentioned that only Chebyshev dc blocks are possible for the impedance transforming. In [9], both symmetric and asymmetric dc blocks are discussed and it is suggested that only asymmetric dc blocks are possible for the impedance transforming. However, neither type of response can be obtained from the proposed design formulas [8] for the impedance transforming. In [9], since no design formula is available, it seems to be very hard to design the suggested dc blocks. References [8] and [9] will be discussed in more detail as regards the verification that only one of two examples of the asymmetric designs in [9] is correct and all the design equations in [8] seem to be incorrect even with equal termination impedances. In this paper, correct design formulas of symmetric and asymmetric dc blocks are derived. It is clarified that the symmetric Chebyshev dc blocks are not possible for the impedance transforming. To derive design formulas of all types of dc blocks,

0018-9480/$26.00 © 2010 IEEE

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symmetric dc blocks are first synthesized and design equations of asymmetric dc blocks are computed based on the transfer of symmetric dc blocks. function To derive the design equations of the symmetric Chebyshev dc blocks, a calculation method is proposed, in contrast to the very complicated calculation process required with the conventional design method and lack of solution for the symmetric Chebyshev dc blocks [8]. For this purpose, the coupling coefficient is defined for a two-port circuit composed of symmetric coupled transmission-line sections. With the ripple condition at the center frequency and the coupling coefficient defined, two sets of design equations of symmetric Chebyshev dc blocks are calculated easily, but only one can satisfy the condition that a perfect matching frequency should exist in a desired bandwidth. For the symmetric Butterworth dc blocks, three design methods are presented; using one-port equivalent resonance circuit [17], [18], transmission scattering parameter, and two-port equivalent circuit. Based on the three methods, design formulas are derived and verified with a microstrip symmetric Butterworth dc block terminated in 50 and 25 . The microstrip dc block designed at a design center frequency of 2 GHz is fabricated on a substrate (RT6202, mm) and measured. The measured and are 0.19 and 57 dB around 2 GHz, having quite good agreement with simulation results. In this way, design formulas of symmetric dc blocks are derived. Using the design formulas derived, the coefficients of the are also calculated. Since has transfer function the same form in the symmetric and asymmetric dc blocks, design equations of asymmetric dc blocks may be obtained by equating the known coefficients of symmetric dc blocks to unknown coefficients of the asymmetric structures. The coupling power between two coupled transmission-line sections is maximum when they are identical [14], [16], [19]. For the design of asymmetric dc blocks, at least two sets of even- and odd-mode impedances are required. To realize the asymmetric dc blocks to have the same frequency performance as the symmetric ones, the even-mode impedance of one of two sets should be very high and the other set should have very tight coupling. In a practical case, the asymmetric dc blocks are, therefore, not recommended. Through the examples of the asymmetric Butterworth dc blocks given in this paper, this fact is proven. The derived design equations of asymmetric Chebyshev dc blocks are verified by the measurements provided in [9] and those of asymmetric Butterworth dc blocks are also validated by the symmetric Butterworth dc block measured in this paper.

II. CONVENTIONAL IMPEDANCE-TRANSFORMING DC BLOCKS

A. Introduction of DC Blocks An asymmetric dc block terminated in and and its equivalent circuit are depicted in Fig. 1(a) and (b), respectively. The impedance parameters are easily obtained by applying an

Fig. 1. Asymmetric dc block and its equivalent circuit. (a) Asymmetric dc block with real termination impedances of R and R . (b) Equivalent circuit.

open boundary condition to a four-port asymmetric directional coupler and given as

(1) For the reciprocity,

should be satisfied and yields (2)

The impedance parameters may be rewritten as (3) The impedance parameters in (3) indicate that one series open , a transmission-line secstub with characteristic impedance , and another series open tion with characteristic impedance are connected in casstub with characteristic impedance cade, as shown in Fig. 1(b). Calculating the scattering parameters with the impedance parameters, the transfer function of has the following form: (4) and pure TEM and lossless propagation are where and in assumed for simplicity. The general coefficients (4) are determined depending on frequency responses (Chebyshev or Butterworth response). Chebyshev and Butterworth frequency responses are deand are maximum scribed in Fig. 2(a) and (b), where and cutoff points. To have the Chebyshev ripple response [see has the value of at and Fig. 2(a)], and unity at , where is the ripple value. The first with respect to is zero at and . derivative of should be positive Furthermore, the second derivative of

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TABLE I DESIGN DATA FOR SYMMETRIC CHEBYSHEV RESPONSE USED IN [8]

Fig. 2. DC block frequency responses. (a) Chebyshev ripple response. (b) Butterworth response.

at and negative at . The conditions for the Chebyshev ripple response are summarized in (5) as follows: (5a) (5b) (5c)

(5d)

Fig. 3. Simulation results of symmetric Chebyshev dc blocks suggested in [8]. S . (b) S S . (a) S

=

For the Butterworth response [see Fig. 2(b)], the function of has unity at and at , where is generally 1/2, but may be different according to the requirewith respect to is zero at ment. The first derivative of , but nonzero at any other values of . Finally, the second . The conditions for the Butterderivative is negative at worth response are also summarized as (6a) (6b) and

for any (6c) (6d)

B. Conventional Design Problems For the better understanding of the present work, the two previously published papers [8], [9] are worth discussing. Reference [8] suggests that symmetric Chebyshev dc blocks are possible, but symmetric Butterworth dc blocks are not for the impedance transforming. On the other hand, [9] proposes that the symmetric dc blocks are not possible and only asymmetric ones are possible for the impedance transforming. However, it is found that [8] is incorrect and [9] is partially correct only in one of two design examples. In [8], two conditions in (5a) and (5c) are considered for the Chebyshev response, but two others

=

are missed. For the Butterworth response in [8], only two conditions in (6a) and (6b) are counted and two other conditions in (6c) and (6d) are utilized incorrectly. In [8], two sets of design equations are given for the Chebyshev response, but only one has positive values of even- and oddmode impedances. Based on the equations given in [8], symmetric Chebyshev dc blocks were simulated for 0.1-dB ripple response and 60% bandwidth. To have the performance, and (Table I), where is the standingwave ratio. Simulated scattering parameters are plotted in Fig. 3 where solid lines indicate frequency responses with equal termination impedances and dotted ones are those with different termination impedances. In this case, the operating center frequency is 1 GHz. Only equal termination impedance case shows the Chebyshev ripple response (Fig. 3) and the other one looks like a Butterworth response with mismatch at the design center frequency. In the case of the Chebyshev response [see Fig. 3(a)], the scattering parameter of should be 0.1 dB at 0.7 GHz to have the 60% bandwidth, but more bandwidth is found. The design equations given in [8], therefore, do not seem to be correct for the Chebyshev response even with equal termination impedances. Fig. 4 shows the process to derive the equivalent circuit of an asymmetric dc blocks in [9]. Reference [9] starts with the circuit [see Fig. 4(a)], consisting of a series open stub with characteristic impedance , and a transmission-line section with characteristic impedance . This circuit refers to a prototype

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Fig. 4. Circuits for the derivation of equivalent asymmetric dc block in [9]. (a) Series open stub connected with a transmission-line section. (b) Dividing one open stub into two. (c) Application of Kuroda’s identity. (d) Equivalent circuit of an asymmetric dc block.

TABLE II DESIGN DATA FOR SYMMETRIC AND ASYMMETRIC DC BLOCKS SUGGESTED IN [9]

Fig. 5. Simulation results of the examples given in [9]. (a) (b)S S .

=

S

=

S

.

TABLE III CONCLUSION ABOUT THE CONVENTIONAL DESIGNS IN [8] AND [9]

terminated in and [see Fig. 4(a)]. The characteristic impedance of the open stub is divided into two, and [see Fig. 4(b)]. Then, one open stub with is moved to behind the transmission-line section [see Fig. 4(c)] using Kuroda’s identity. Finally, the termination impedance of [see Fig. 4(c)] is transformed into [see Fig. 4(d)]. The final circuit [see Fig. 4(d)] is the same as the equivalent circuit of the dc block in Fig. 1(b). The main purpose of this paper [9] is to determine [see Fig. 4(a)] using a Chebyshev or Butterworth transfer function. The transfer function has the same forms in both prototype and equivalent circuit [see Fig. 4(a) and (d)], but the coefficients and in (4) should be different from each other. However, the coefficients used for the Butterworth prototype in [9] are those of the dc block [see Fig. 4(d)] provided in [8]. The correct Butterworth response of the dc block is, therefore, hard to obtain in [9]. Substituting into the equation in (32) in [8] results in the same denominator in (9) in [9]. Two types of examples of the symmetric and asymmetric dc blocks given in [9] are listed in Table II and simulation results are plotted in Fig. 5 where frequency responses of and are in Fig. 5(a) and (b). Solid lines are the frequency responses of asymmetric dc blocks with notation “Asy Cheby.” (asymmetric Chebyshev response) and “Asy Butt.” (asymmetric Butterworth response), while

dotted lines are those of symmetric ones. For the simulation, a commercial circuit simulator, Agilent Technologies’ Advanced Design System (ADS) was employed for the symmetric dc blocks and mathematical software (MATLAB) for the asymmetric ones. From the simulation results (Fig. 5), only asymmetric Chebyshev dc block shows perfect Chebyshev response. It can, therefore, be concluded that only one example of the asymmetric Chebyshev dc block [9] is correctly designed. The items suggested by conventional methods [8], [9] and verification are listed in Table III where “Cheby.” or “Butt.” denotes the Chebyshev or Butterworth response. In Table III, “o or x in Suggestion” expresses the suggestion with possibility of impedance transforming or not, and “o or x in Verification” does the correct suggestion or not. To sum up, in [8], it is suggested the possibility of the symmetric Chebyshev dc blocks and the improbability of the symmetric Butterworth dc blocks. The symmetric Chebyshev ones [8] were, however, verified to be incorrect even with equal termination impedances (Fig. 3). The possibility of the symmetric Butterworth dc blocks will be verified later in Section IV. In [9], it is proposed that symmetric dc blocks are not possible and asymmetric ones are possible for the impedance transforming, but only one of the asymmetric design examples was verified to be correct (Fig. 5). In this paper, correct design formulas of symmetric and asymmetric dc blocks will be derived for impedance transforming and it will be clarified that the symmetric Chebyshev dc blocks are not possible for the impedance transforming.

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the capacitances per unit length between one conductor and represents the capacitance per unit length beground, while tween two strip conductors. In this case, coupling coefficient is defined as (10) Fig. 6. Cross-sectional view of a pair of symmetric coupled transmission-line sections.

III. SYMMETRIC CHEBYSHEV DC BLOCKS For the symmetric case, applying and [see Fig. 1(a)], scattering parameters (see the Appendix) are calculated as

where it is assumed that the two coupled transmission lines are identical and waves are propagating in the pure TEM mode. and are expressed with even- and The capacitances odd-mode impedances as (11a) (11b)

(7a)

(7b)

and are effective permittivity and permeability of where the substrate, respectively. From (10) and (11), the coupling coefficient is given by (12)

(7c) of the dc block in (12) is independent of The defined (Fig. 1) and equal to the maximum coupling coefficient of the symmetric directional coupler in (9).

where

B. Design Formulas of Symmetric Chebyshev DC Blocks Letting in (7) and computing as (4) is obtained. Applying of gives

, the same form in (5a)

(8a)

The next step is to derive the condition satisfying in (5b) since, if any solution to exists, there is no at or need to get first and second derivatives of (Fig. 2). No insertion loss at indicates perfect matching at and and are both required to be zero, from which the following equations should be satisfied:

(8b) To determine and , another equation involving and is needed, for example, the first derivative of at or or solutions to (5c) or (5d). However, very a complicated calculation process is needed. To make it simpler, a coupling coefficient consisting of even- and odd-mode impedances will be defined for a set of symmetric coupled transmission-line sections. A. Definition of Coupling Coefficient In a symmetric directional coupler, the coupling coefficient indicates the coupled scattering parameter and is expressed as

(13a)

(13b) With the different termination impedances and , in (13b) is not possible at in any . Therefore, it is impossible case due to the nonzero value of to design symmetric Chebyshev dc blocks for the impedance transforming. Below we will provide design equations for equal termination impedances. With (8) and (12), two sets of design equations are obtained and the first one is

(9) (14a) which varies with the change in and has a maximum value at . However, the meaning of the coupling power of the dc block [see Fig. 1(a)] is somewhat different. Fig. 6 shows a cross-sectional view of a pair of symmetric coupled transmission-line sections where and denote

(14b) where

.

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TABLE IV NORMALIZED EVEN- AND ODD-MODE IMPEDANCES FOR SYMMETRIC CHEBYSHEV DC BLOCKS

The second one is

(15a)

Fig. 7. Frequency responses of symmetric Chebyshev dc blocks with different ripples.

(15b) To check which set of design equations is suitable for the Chebyor may be shev response, used. From (13a), is calculated as (16) Substituting the two sets of even- and odd-mode impedances and in (14) and (15) into (16), using the relation between and applying , the correct solution satisis only the first one in (14). fying the condition of Substituting the normalized even- and odd-mode impedances in is expressed as (14) into the equation in (16), (17a) where (17b) Applying

gives (18)

C. Frequency Response of Symmetric Chebyshev DC Blocks To design the symmetric Chebyshev dc blocks, normalized and even- and odd-mode impedances were calculated as are varied and given in Table IV. Using the data (Table IV) with a fixed coupling coefficient of 5 dB, three dc blocks with 0.05-, 0.1-, and 0.2-dB ripples were designed as the electrical length is varied. For ripple value in decibels, the following conversion equation may be used: (dB)

(19)

Their frequency responses were plotted in Fig. 7 where the scattering parameters of show 0.05, 0.1, and 0.2 , while their bandwidths are not so different. dB at

Fig. 8. Frequency responses of symmetric Chebyshev dc blocks. (a) . (b) S S .

S

=

S

=

With a fixed ripple of 0.1 dB, several symmetric Chebyshev dc blocks were designed at the center frequency of 1 GHz and the simulation results are plotted in Fig. 8 as is varied. The value of (Fig. 2) specifies the frequency bandwidth, as defined by the lower and upper cutoff frequencies (18). For example (Fig. 8), the frequency response of the scattering with dB intersects a parallel parameters of line of 0.1 dB at two points, 0.58 and 1.42 GHz [see Fig. 8(a)]. In this case, its upper frequency is 1.42 GHz and its lower one is 0.58 GHz, and the bandwidth is . Upon

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Fig. 9. Symmetric dc blocks. (a) Symmetric dc block. (b) Input impedance expressed as a one-port resonance circuit.

the value of expressed as

, the lower and upper frequencies

and

are

(20a) (20b) where is a design center frequency, unit of is degrees. Its relative bandwidth and is between

, and the and the relation

(21)

IV. SYMMETRIC BUTTERWORTH DC BLOCKS Independent of the conditions in (6) for the Butterworth response, three easy design methods will be introduced using a one-port resonant equivalent circuit, transmission scattering parameter, and two-port equivalent circuit. A. Using One-Port Resonant Equivalent Circuit An impedance-transforming symmetric dc block is again deis the input impedance looking picted in Fig. 9(a) where into a pair of coupled transmission-line sections terminated with . How much power excited at port [see Fig. 9(a)] that depends on the coupling struccan be transmitted into port may ture. Therefore, the coupled-line sections terminated in be equivalent to a one-port resonant circuit [17] where its resonance type (parallel or series) is determined by input impedance variation with frequency. Input impedance magnitudes normalized to the reference were simulated with a coupling termination impedance fixed at 0.6. Their responses coefficient varied and are plotted in Fig. 10(a). Since the symmetric dc block [see Fig. 9(a)] is obtained by terminating two ports of an impedance-transforming symmetric directional coupler [3], and even-mode impedance odd-mode impedance suggested in [3] were used for this simulation. From the simulation , input impedance results [see Fig. 10(a)], when normalized to the reference impedance magnitude is unity only with dB and more or less than unity in two other cases. That indicates perfect dB and design equations matching appears only with for the impedance-transforming directional coupler [3] are dB. When the electrical length effective only with

Fig. 10. Input impedance magnitudes of dc blocks with conventional design 0:6. (a) Input impedance normalized to referequations [3] having R =R ence impedance R . (b) Input impedance normalized to resonance resistance R appearing at resonance angular frequency ! (! ; operating angular frequency).

=

[see Fig. 9(a)] is 90 , resonance occurs and only resistance exists in the resonance circuit [see Fig. 9(b)]. To see which type was also simulated of resonance is available, depending on frequency and plotted in Fig. 10(b) where the solid line indicates the series resonance type and dotted lines are the parallel resonance type [17]. It means that one circuit has two resonance circuits, which is unreasonable. Therefore, the design equations suggested in [3] should be modified. To have one resonance circuit for each symmetric dc block and perfect matching at a design center frequency with no rewas calculated and given striction on , input impedance as (22) where

(22a) (22b) where

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TABLE V EVEN- AND ODD-MODE IMPEDANCES OF SYMMETRIC BUTTERWORTH DC BLOCKS WITH FIXED TERMINATION IMPEDANCES OF 50 AND 25

TABLE VI FABRICATION DATA OF A MICROSTRIP SYMMETRIC BUTTERWORTH DC BLOCK TERMINATED IN 50 AND 25

Fig. 11. Input impedance magnitude of dc blocks with impedances transformation ratio of 0.6 (! and ! ; operating and resonance angular frequencies).

When resistance

in (22b), remains as

as expected, and only

(23) For the dc block to be perfectly matched, should be satisfied (Fig. 9). With (23) and (12), design formulas for the symmetric Butterworth dc blocks are given as

into another one satisfied:

. Therefore, the following equation is

(24a)

(26)

(24b)

With (12) and (26), the same design equations in (24) are also obtained.

where . With the design equations derived in (24), input impedance magnitudes of a symmetric Butterworth dc block terminated were simulated and the results were plotted in 50 and 30 in Fig. 11 as the coupling coefficient is varied. Independent of the coupling coefficient, all the symmetric ones are perand have a fectly matched at the resonance frequency of parallel resonance frequency response. Their bandwidths are proportional to coupling strength and bandwidth is defined as a frequency separation of the two points that a parallel line of intersects.

D. Frequency Responses of Symmetric Butterworth DC Blocks Based on the design equations in (24), even- and odd-mode impedances are calculated as is varied (Table V). In this case, the termination impedances are fixed at 50 and 25 . As becomes weaker (Table V), even- and odd-impedances are gradually increased. Using the data (Table V), several dc blocks were simulated at a center frequency of 1 GHz and the simulation results were plotted in Fig. 12 where the scattering parameters are described depending on coupling power. The simulation results show that all are perfectly matched and that the bandwidths are proportional to .

B. Using Scattering Parameters To have Butterworth response, should be satisfied (Fig. 2) from which the following equation is obtained as: (25) In a similar way, with (25) and (12), the same design equations as those in (24) are obtained. C. Using Two-Port Equivalent Circuit For the symmetric case with (Fig. 1), two open stubs disappear and only one transmission-line section is left. For this circuit to be perfectly matched, the transmission-line should be an section with the characteristic impedance of impedance transformer to transform a termination impedance

E. Measurements of Symmetric Butterworth DC Block To verify the design equations in (24), a microstrip dc block terminated in 50 and 25 designed at the center frequency of , 2 GHz was fabricated on a substrate (RT 6202 with mm, and ) and tested. Since even- and odd-mode design equations were derived under the assumption of TEM mode propagation, the mean value of even- and odd-mode phase velocities, or any commercial circuit simulator may be used. Since the gap of the coupled transmission lines is limited to 0.15 mm with standard printed circuit board (PCB) technology, linewidth , gap , and length of the symmetric Butterworth dc blocks were investigated dB was chosen for depending on (Table VI) and the fabrication. With different termination impedances of 50 and 25 , an additional impedance transformer to transform

AHN AND ITOH: IMPEDANCE-TRANSFORMING SYMMETRIC AND ASYMMETRIC DC BLOCKS

Fig. 13. Fabricated dc block with

Fig. 12. Simulated frequency response of symmetric Butterworth dc blocks. S . (b) S S . (a) S

=

=

25 into 50 is needed and its characteristic impedance is (Table VI). The fabricated circuit is shown in Fig. 13 where termination and are indicated as 50 and 25 . For the impedances measurements, the circuit simulations with ADS and the field simulations with the High Frequency Structure Simulator 11 (HFSS 11) were carried out and the simulation results are compared with measured ones in Fig. 14. Measured scattering paand are 0.19 and 57 dB rameters of around the design center frequency, showing quite good agreement with simulation results. Measured scattering parameter of shows symmetric property with respect to the center frequency, while both simulation results are asymmetric. The is very similar to measured scattering parameter of that with ADS in the lower frequency region, whereas it is about same as that with HFSS in the higher frequency region (Fig. 14).

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09-dB coupling power.

Fig. 14. Results measured and simulated are compared.

(27b) (27c) where . and (27) and obtained The unknown variables are and , where and by equating are those of symmetric dc blocks and already known from (14) and (24). Once the unknown variables are solved, two sets of even- and odd-mode impedances are easily obtained such as (28a) (28b) (28c) (28d)

V. ASYMMETRIC DC BLOCKS With the impedance parameters given in (1), scattering parameters of the asymmetric dc blocks were calculated and the in (4) are given as coefficients of (27)

A. Asymmetric Chebyshev DC Blocks is already known. With Among the variables, (Fig. 1), only the transmission-line section with characteristic (Fig. 1) remains. The value is impedance (29a)

with

where (27a)

(29b)

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in (29a) is the same as that in (8a) and the upper subscript of corresponds to the Chebyshev response. Using the even- and odd-mode impedances in (14), the coefficients of the symmetric Chebyshev dc blocks are calculated as

TABLE VII EVEN- AND ODD-MODE IMPEDANCES OF ASYMMETRIC BUTTERWORTH 50 AND R = 25

DC BLOCKS FOR R

=

(30a) (30b) (30c) Equating the coefficients in (27) to those in (30) results in (31a) (31b) where

(33a) (33b) where

Finally, two sets of design formulas of even- and odd- mode impedances for the asymmetric Chebyshev dc blocks are (32a)

The subscript in (33) expresses the Butterworth response. In a similar way, the design equations of asymmetric Butterworth dc blocks are (34a)

(32b) (34b) (32c) (32d) The coupling coefficient defined in the symmetric coupled transmission-line sections does not contain the physical meaning any more in (32), but determines the bandwidths identically. The characteristic impedances of the coupled transmission-line sections of the asymmetric dc blocks are mainly determined by the termination impedances connected and are generdB, ally too high to be realized. In the case of dB, and (Fig. 1), , , , and can be calculated. Two sets of even- and odd-mode impedances calculated are about the same as those verified by experiments in [9]. B. Asymmetric Butterworth DC Blocks The symmetric Butterworth dc blocks provide the following coefficients:

(34c) (34d) If the obtained values of the even- or odd-mode impedances are negative in (34), less value of is taken. Four sets of evenand odd-mode impedances are available and two sets are for the symmetric dc blocks and another two are for the asymmetric ones. Based on the equations in (34), four sets of even- and odd-mode impedances are listed in Table VII for and (Fig. 1). The first and second two sets (Table VII) are for the symdB metric and asymmetric dc blocks, respectively. For (Table VII), even- and odd-mode impedances required are 135 and 64.3 for the symmetric dc block, but those for the asymmetric one are (234.7 and 163.9 ) and (85.2 and 14.5 ). The even- and odd-mode impedances of 135 and 64.3 are the same as those of the symmetric Butterworth dc block in Table V. The maximum coupling can be achieved with the symmetric coupled transmission-line sections [14], [16], and to have the same performance using the asymmetric coupled transmission-line sections, one of two even-mode impedances should be very high and another is lower than the symmetric one. What is worse, one of two sets of coupled transmission-line sections should have

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very tight coupling, as in the examples in Table VII. In practical application, therefore, the asymmetric dc blocks are not recommended.

(A2a)

VI. CONCLUSION In this paper, impedance–transforming symmetric and asymmetric dc blocks were presented and their design equations were derived. For this purpose, symmetric Chebyshev dc blocks were first analyzed and the coupling coefficient of the symmetric dc blocks was defined for easy derivation of the design formulas. It was also clarified that the symmetric Chebyshev dc blocks were not possible for the impedance transforming. As for symmetric Butterworth dc blocks, three different design approaches were applied and design formulas, mainly consisting of coupling coefficients, were derived. Using the fact that the transfer funchas the same forms in both symmetric and asymtion metric dc blocks, design formulas of the asymmetric dc blocks of were derived by equating the known coefficients of the symmetric dc blocks to unknown coefficients of the asymmetric dc blocks. Through the design examples of the asymmetric Butterworth dc blocks, the fact was suggested that one of two even-mode impedances should be too high to be realized and the other set of coupled transmission-line sections should have very tight coupling to have the same performance as the symmetric dc blocks. Since the suggested symmetric dc blocks may be designed with no restriction on coupling power, many applications can be expected without any realization problem. Since the dc blocks can be terminated in different termination impedances, it can also be expected to reduce the total size of microwave integrated circuits. APPENDIX Since the two-port circuit is terminated in arbitrary real imand , the well-known even- and odd-mode expedances citation analyses [1] cannot be applied. The formulas of the current-based scattering parameters [2] are given as (A1a) (A1b) (A1c) (A1d) where

For the symmetric coupled transmission-line sections and , applying (Fig. 1), the impedance parameters in (1) to the equations in (A1), and numerators of and are calculated as

(A2b) (A2c) and are the numerators of and . where The relation between normalized and current-based scattering parameters [2] is (A3a) (A3b) (A3c) (A3d) With the equations in (A2) and the relations in (A3), scattering parameters of symmetric dc blocks terminated in real impedand may be computed as those in (7). ances REFERENCES [1] H.-R. Ahn, Asymmetric Passive Components in Microwave Integrated Circuits. New York: Wiley, 2006, ch. 1, pp. 1–9. [2] H.-R. Ahn and B. Kim, “Toward integrated circuit size reduction,” IEEE Microw. Mag., vol. 9, no. 1, pp. 65–75, Feb. 2008. [3] H.-R. Ahn and B. Kim, “Transmission-line directional couplers for impedance transforming,” IEEE Microw. Wireless Compon. Lett., vol. 16, no. 10, pp. 537–539, Oct. 2006. [4] R. Mongia, I. Bahl, and P. Bhartia, RF and Microwave Coupled-Line Circuits. Boston, MA: Artech House, 1999. [5] S. R. Borgaonkar and S. N. Rao, “Analysis and design of DC blocks,” Electron. Lett., vol. 17, no. 2, pp. 101–103, Jan. 1981. [6] D. Kajfez, S. Bodda, and C. E. Smith, “Asymmetric microstrip DC blocks with rippled response,” in IEEE MTT-S Int. Microw. Symp. Dig., 1981, pp. 301–303. [7] H.-R. Ahn and B. Kim, “Perfectly-matched DC blocks terminated in arbitrary impedances,” (in Korean) J. Korean Inst. Electromagn. Eng. Sci., vol. 18, no. 8, pp. 895–903, Aug. 2007. [8] D. Kajfez and B. S. Vidula, “Design equations for symmetric microstrip DC blocks,” IEEE Trans. Microwave Theory Tech., vol. MTT-28, no. 9, pp. 974–981, Sep. 1980. [9] A. Podcameni, “Symmetrical and asymmetrical edge-coupled-line impedance transformers with a prescribed insertion loss design,” IEEE Trans. Microw. Theory Tech., vol. MTT-34, no. 1, pp. 1–7, Jan. 1986. [10] H.-R. Ahn and I. Wolff, “Asymmetric four-port and branch-line hybrids,” IEEE Trans. Microw. Theory Tech., vol. 48, no. 9, pp. 1585–1588, Sep. 2000. [11] H.-R. Ahn, I. Wolff, and I.-S. Chang, “Arbitrary termination impedances, arbitrary power division, and small-sized ring hybrids,” IEEE Trans. Microw. Theory Tech., vol. 45, no. 12, pp. 2241–2247, Dec. 1997. [12] E. G. Cristal, “Coupled-transmission-line directional couplers with coupled lines of unequal characteristic impedances,” IEEE Trans. Microw. Theory Tech., vol. MTT-14, no. 7, pp. 337–346, Jul. 1966. [13] V. K. Tripathi and Y. K. Chin, “Analysis of the general nonsymmetrical directional coupler with arbitrary terminations,” Proc. Inst. Elect. Eng. —Microw., Antennas, Propag., vol. 129, pt. H, pp. 360–362, Jun. 1982. [14] K. Sachse, “The scattering parameters and directional coupler analysis of characteristically terminated asymmetric coupled transmission lines in an inhomogeneous medium,” IEEE Trans. Microw. Theory Tech., vol. 38, no. 4, pp. 417–425, Apr. 1990.

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[15] N. A. El-Deeb, E. A. F. Abdallah, and M. B. Saleh, “Design parameters of inhomogeneous asymmetrical coupled transmission lines,” IEEE Trans. Microw. Theory Tech., vol. MTT-31, no. 7, pp. 592–596, Jul. 1983. [16] H.-R. Ahn, I.-S. Chang, and S.-W. Yun, “Miniaturized 3-dB ring hybrid terminated by arbitrary impedances,” IEEE Trans. Microw. Theory Tech., vol. 42, no. 12, pp. 2216–2221, Dec. 1994. [17] H.-R. Ahn, “Resonators,” in Encyclopedia of RF and Microwave Engineering. New York: Wiley, 2005. [18] D. M. Pozar, Microwave Engineering, 2nd ed. New York: Wiley, 1998. [19] R. H. Jansen, “Fast accurate hybrid mode computation of nonsymmetrical coupled microstrip characteristics,” in Proc. 7th Eur. Microw. Conf., Copenhagen, Denmark, 1977, pp. 135–139.

Hee-Ran Ahn (S’90–M’95–SM’99) received the B. S., M. S., and Ph.D. degrees in electronic engineering from Sogang University, Seoul, Korea, in 1988, 1990 and 1994, respectively. She is currently a Visiting Scholar with the Department of Electrical Engineering, University of California at Los Angeles (UCLA). From July 2005 to August 2009, she was with the Department of Electronics and Electrical Engineering, Pohang University of Science and Technology (POSTECH), Pohang, Korea. From March 2003 to February 2005, she was with the Division of Electrical Engineering, Department of Electrical Engineering and Computer Science (EECS), Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, as a Visiting Professor. From 1996 to 2002, she was with the Department of Electrical Engineering, Duisburg-Essen University, Duisburg, Germany, where she was involved with the habilitation dealing with asymmetric passive components in microwave circuits. From 1991 to 1995, she was a Part-Time Lecturer with Sogang University, Seoul, Korea. Her interests include high-frequency and microwave circuit design and biomedical application using microwave theory and techniques. She

authored Asymmetric Passive Component in Microwave Integrated Circuits (Wiley, 2006).

Tatsuo Itoh (S’69–M’69–SM’74–F’82–LF’06) received the Ph.D. Degree in electrical engineering from the University of Illinois at Urbana-Champaign, in 1969. After working for the University of Illinois at Urbana-Champaign, SRI, and the University of Kentucky, he joined the faculty of The University of Texas at Austin in 1978, where he became a Professor of electrical engineering in 1981. In September 1983, he was selected to hold the Hayden Head Centennial Professorship of Engineering with The University of Texas at Austin. In January 1991, he joined the University of California at Los Angeles (UCLA), as a Professor of electrical engineering and Holder of the TRW Endowed Chair in Microwave and Millimeter Wave Electronics (currently Northrop Grumman Endowed Chair). He has authored or coauthored 375 journal publications, 775 refereed conference presentations, and 43 books/book chapters in the area of microwaves, millimeter waves, antennas, and numerical electromagnetics. He has generated 70 Ph.D. students. Dr. Itoh is a member of the Institute of Electronics and Communication Engineers of Japan and Commissions B and D of USNC/URSI. He was the editor-in-chief of the IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES (1983–1985). He was president of the IEEE Microwave Theory and Techniques Society (IEEE MTT-S) in 1990. He was the editor-in-chief of the IEEE MICROWAVE AND GUIDED WAVE LETTERS from 1991 to 1994. He was elected an Honorary Life Member of the IEEE MTT-S in 1994. He was the chairman of Commission D of the International URSI from 1993 to 1996. He serves on advisory boards and committees of a number of organizations. He was a Distinguished Microwave Lecturer on Microwave Applications of Metamaterial Structures of the IEEE MTT-S from 2004 to 2006. He was elected a member of the National Academy of Engineering in 2003. He was the recipient of numerous awards including the IEEE Third Millennium Medal in 2000, and the IEEE MTT-S Distinguished Educator Award in 2000.

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Pole-Perturbation Theory for Nonlinear Noise Analysis of All-Pole RF MEMS Tunable Filters Vikram Sekar, Student Member, IEEE, and Kamran Entesari, Member, IEEE

Abstract—This paper presents a theoretical approach to predict the effect of nonlinear noise mechanisms in all-pole RF microelectromechanical systems (MEMS) tunable filters. It is shown that both nonlinearity and noise can be expressed as perturbations of poles of the filter transfer function. Perturbations in the bandpass filter are mapped into its equivalent ladder network as perturbations in the prototype element values. Closed-form equations are derived to calculate pole-perturbations in Butterworth and Chebyshev filters using prototype perturbations. The proposed method is then used to calculate the effect of nonlinear noise phenomena due to Brownian motion in RF MEMS tunable filters for different input power levels. As a result, the filter phase noise is calculated as a function of input power, tuning state, fractional bandwidth, filter order, and frequency offset. The effect of filter nonidealities and their implications on phase noise are discussed. Finally, it is shown that signal-to-noise ratio degradation due to filter phase noise is most significant in MEMS tunable filters with low bandwidth, high order, and high quality factor. Index Terms—Brownian motion, nonlinearity, phase noise, pole-perturbation, RF microelectromechanical systems (MEMS), signal-to-noise ratio (SNR).

I. INTRODUCTION ICROWAVE bandpass filters are essential components in modern wireless communication systems as band-select filters. Typically, band-select filters appear between the antenna and the low-noise amplifier (LNA) in a receiver system. Intrinsic noise mechanisms in bandpass filters can severely degrade the receiver signal-to-noise ratio (SNR) since there is no signal amplification before the LNA. With the advent of multiband multistandard wireless communication systems [1], tunable microwave filters are becoming increasingly important in RF front-end systems. RF microelectromechanical systems (MEMS) switches have low loss, out– dBm) and do not require any standing linearity ( dc current, and hence, offer a very low power solution for tuning applications [2]. However, RF MEMS switches are prone to thermal-mechanical noise due to Brownian motion, which results in noise at the output of the switch [3]. Since RF MEMS switches exhibit nonlinear behavior at high input power, switch noise is a nonlinear function of input power, which is not considered in the small-signal analysis presented in [3].

M

Manuscript received March 23, 2010; revised May 30, 2010; accepted June 06, 2010. Date of publication August 16, 2010; date of current version September 10, 2010. This work was supported by the National Science Foundation (NSF) under Grant 0901088. The authors are with the Analog and Mixed Signal Center, Department of Electrical and Computer Engineering, Texas A&M University, College Station, TX 77843 USA (e-mail: [email protected]; [email protected]). Digital Object Identifier 10.1109/TMTT.2010.2058595

N

Fig. 1. (a) Generalized all-pole bandpass filter of order with ideal admittance inverters and lossless shunt resonators. (b) Equivalent low-pass ladder network.

Thus far, the effect of nonlinear noise in RF MEMS tunable filters has been studied only using computer-aided design (CAD)-based simulation techniques in [4] and [5]. The goal of this paper is to develop a theory to predict the effect of nonlinear noise in all-pole RF MEMS tunable filters. This is achieved by calculating variations in the filter transfer function due to presence of nonlinear noise by perturbing poles of the filter transfer function in the complex plane. The pole-perturbation approach has been previously used to study the effect of coefficient accuracy in the implementation of digital filters [6]. Pole-perturbations have also been used for passivity enforcement of nonpassive rational models [7]. In this work, a pole-perturbation approach is introduced to calculate nonlinear noise due to Brownian motion in RF MEMS tunable filters for the first time. To find the effect of nonlinearity, a generalized iterative approach is presented to find the peak internal voltages in nonlinear microwave filters. The variation in filter response due to nonlinear noise is used to theoretically predict filter phase noise as a function of input power, tuning state, fractional bandwidth, filter order, and frequency offset, and is compared to results of the CAD-based methods in [4] and [5]. The effects of nonidealities arising from practical realizations of filter components on filter phase noise are also considered. Finally, it is shown that filter phase noise is most significant in MEMS tunable filters with low bandwidth, high order, and high quality factor. II. PERTURBATION THEORY Fig. 1(a) shows a generalized Butterworth or Chebyshev with ideal admittance inverters bandpass filter of order , lossless shunt resonators, and terminafor which all formulations are presented tion admittances in this paper. Similar results can be derived for the filter with impedance inverters and series resonators. The discussion is limited to synchronous filters in which all resonators are tuned to for . are

0018-9480/$26.00 © 2010 IEEE

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the node voltages across each resonator due to the applied input excitation . Fig. 1(b) shows the equivalent low-pass ladder are network starting with a series element where the prototype element values for all-pole filters. Each resonator in the bandpass filter or reactive low-pass prototype value in the ladder network represents a pole on the left-half of the com, plex plane, which is located at an angle , from the imaginary axis for Butterworth and Chebyshev filters.

. The value of is perturbation of the center frequency is given by of resonator . The constant for Butterworth filters for Chebyshev filters and for a Chebyshev filter with a ripple of

dB, (4)

A. Methodology

Substituting (1) in (2) results in

The pole-perturbation approach in microwave filters presented here involves mapping any change in the component values of the bandpass filter into the perturbation of the reactive low-pass prototype element values of the equivalent ladder network. Perturbations may arise due to nonlinear device behavior inside the filter at high input power or internal noise sources. Thus, the position of the th pole in the complex plane at a given angular frequency, input power, and time instant may be represented by the complex quantity . If the perturbations in the microwave filter are due to changes in the reactive elements only, then it will be shown later that the perturbation of low-pass prototype values may be completely represented in terms of an angular . Since the driving point impedance of displacement the prototype filter must always be a positive real function [8], the pole-perturbations are restricted as follows. 1) The complex conjugate property of complex poles is maintained during perturbation. 2) Perturbed poles always have negative or zero real parts. In general, the pole-perturbation may be decomposed into perturbations along the real ( -axis) and imaginary ( -axis) directions represented by and , respectively, so that the overall pole-perturbation is given by

(5)

Thus, the transmission response of the filter is easily determined from (5) once the perturbations in the reactive low-pass prototype values are known and decomposed into real and imaginary pole-perturbation components. B. Prototype Perturbation In this section, explicit formulas are derived for the equivalent perturbations of reactive low-pass prototype values due to component variations in the bandpass filter. The values of -inverters in Fig. 1 for a filter with fractional bandwidth are given by [9]

(6)

(1) on the filter transfer The impact of perturbations function can be obtained from rational polynomial approximations for Butterworth and Chebyshev filters, which is expressed as [9]

where the susceptance slope of each resonator is represented by . Reactive variations in resonators and admittance inverters result in and inverter values changing susceptance slopes , respectively. The perturbations of the prototype values are obtained by rearranging (6) as (see Appendix A)

(2)

(7) where

where (3)

(8)

is the low-pass angular frequency corresponding to the angular frequency of a bandpass filter with a fractional bandwidth of

refers to the floor function. is the where impedance normalization factor for the th low-pass prototype.

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Fig. 2. Distribution of poles on the complex s-plane for Butterworth filters with: (a) odd order (e.g., N ) and (b) even order (e.g., N ).

=5

=4

Fig. 3. Distribution of poles on the complex s-plane for Chebyshev filters with: ) and (b) even order (e.g., N (a) odd order (e.g., N ).

=5

=4

C. Pole Perturbation The prototype perturbations due to reactive variations in the bandpass filter are used to find the real and imaginary pole-perturbation components for Butterworth and Chebyshev filters as follows. 1) Butterworth Filters: Fig. 2 shows the poles of a Butterworth filter arranged in a circle of unit radius in the complex -plane. For Butterworth filters, the general formula for a pole in terms of its angular location is given as [9]

(9) Thus, the pole-perturbations are limited to points on the unit circle and may be completely defined in terms of angular displacements . In odd-order filters, the component of pole-perturbation causes the purely real pole to deviate from the real-axis. In this case, the driving point impedance of the prototype filter is no longer a positive real function implying that the filter output may be complex when the input is purely real. Clearly, this is untrue when the filter is composed of only component RLC elements. Also, any perturbations by the leads to deviation from the unit circle and violates (9). Hence, the real-axis poles remain unperturbed in odd-order filter realizations. To obtain a direct relation between pole-perturbation and , reactive prototype values of the ladder network filter (9) is rewritten in terms of low-pass prototype values using [9]

By trigonometric manipulation, (12) can also be written as

(13) Here, perturbations result in pole displacements along the ellipse and are completely defined in terms of angular displace. However, real-axis poles in odd-order filters ments remain unperturbed, as in the case of Butterworth filters. To determine pole-perturbations in a Chebyshev filter, a relaand the tionship between the angular pole locations normalized low-pass prototype values is derived in Appendix B. The resulting expression is given by (14) where

(15) with

(10) so that the real and imaginary components of the pole-perturbation for are expressed as

(16) Using (14) in (13), the real and imaginary components of poleperturbation are given by

(11) 2) Chebyshev Filters: Fig. 3 shows the distribution of poles of a Chebyshev filter in the complex -plane. The poles lie on an and minor axis . For Chebyellipse with major axis shev filters, the general formula for a pole in terms of its angular location is given as [9] (12)

(17) Since the pole-perturbation components are known explicitly for variations in the bandpass filter, the perturbed response of Butterworth or Chebyshev filters is calculated from (5). This methodology can be used to find the filter response due to any reactive perturbation in all-pole microwave bandpass filters.

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D. Discussion The analysis presented thus far shows that the perturbation of poles is along the unit circle or ellipse in Butterworth or Chebyshev filters, respectively, only when the changes in the filter components are purely reactive in nature. This assumption is valid for the analysis of RF MEMS tunable filters because the dominant source of perturbations arise in the capacitance of the MEMS switches. If the quality factor of the resonator varies due to resistive perturbations, then the poles are laterally displaced, as explained in Section V-A. Since the resonator quality factor is time invariant for a particular filter tuning state, more emphasis is given to purely reactive perturbations in tunable filters. In odd-order filters, the presence of an unperturbed real-axis pole seems to imply that its contribution to filter nonlinearity and noise is zero. However, this is not true because the perturbations of the filter transfer function arise from variations in the associated with the real-axis low-pass frequency variable pole, and hence, contributes to the filter nonlinearity and noise. III. NONLINEAR NOISE PERTURBATION IN RF MEMS TUNABLE FILTERS The exact nature of pole-perturbation components depends on the nonlinear noise mechanisms in the filter implementation. In RF MEMS tunable filters, Brownian, acceleration, acoustic, and power-supply noise in MEMS switches [3] cause pole-perturbations. The perturbations also depend on the nonlinear behavior of the MEMS switch. In this section, the nonlinear noise perturbations in RF MEMS tunable filters are discussed. A. Nonlinear Analysis The perturbation of an arbitrary pole on the complex plane is a function of the RF drive level in nonlinear microwave filters. Tunable filters employing RF MEMS switches exhibit nonlinear behavior due to nonlinear reactance change of the tuning element at high input power [10]. As a result, the resonance frequency of each resonator shifts and causes distortions in the amplitude and phase response of the tunable filter [11]. The degree of nonlinearity typically depends on the peak voltage appearing across the nonlinear element in the tunable filter. It is customary to use a power series expansion of the nonlinear capacitance variation in tuning elements expressed as [12]

Fig. 4. (a) Generalized all-pole Butterworth/Chebyshev bandpass tunable filter with nonlinear tuning elements, ideal admittance inverters and lossless shunt resonators. (b) Equivalent low-pass filter for a particular tuning state.

Also, since is proportional to , the prototype perturbation [see (7)] and consequently pole-perturbation comand [see (11) and (17)] are functions of input ponents power. Hence, to find the nonlinear perturbation of the filter refor the bandpass sponse using (5), the node voltages filter must be known. A method to calculate node voltages from the low-pass prototype network of a linear microwave filter has been described in [13]. Here, this approach is extended to a nonlinear microwave filter to calculate internal voltages at filter center frequency. The low-pass prototype filter corresponding to a tunable bandpass filter for a particular tuning state is shown in Fig. 4(b), where unit capacitors are coupled through lossless, linear, and fre. The values of quency-invariant admittance inverters and are the voltages across node and the input voltage in low-pass filter, respectively. The bandpass voltages are greater than the low-pass voltages by a factor of , where is a power-independent quantity that equalizes the susceptance slopes of the low-pass and bandpass filters [13]. is the nonlinear reactance perturbation of node in a low-pass filter due to nonlinearity, when a bandpass voltage appears across the resonator. The low-pass internal node voltages are found by solving the nonlinear system of nodal equations of the equivalent low-pass filter, expressed as (20) where for for for

(18) for where are constant coefficients obtained by curve fitting a polynomial to the characteristic function of the nonlinear tuning element. Fig. 4(a) shows a generalized all-pole tunable Butterworth or Chebyshev filter employing nonlinear tuning elements. The perturbation of each resonator depends on the node voltages , and consequently, the perturbation in the angular resonance frequency of each resonator due to capacitive nonlinearity is expressed as (19)

(21) represents the frequency-dependent admittance matrix as a nonlinear function of the node voltages of the equivalent low-pass filter. The values of represent the node currents in the equivalent low-pass filter and the low-pass frequency is the bandpass frequency transformed around filter center frequency using (3). At filter center frequency, . To solve (20), an independent expression for must be known. The nonlinear angular frequency perturbation

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of the th resonator in (19) may be expressed in terms of an equivalent shift in the low-pass frequency variable using (3) as (22) where is the low-pass frequency corresponding to bandpass frequency around center frequency . At filter is calculated by rearranging (22) center frequency, using (3), and evaluating the resulting expression at , as (23) is known, When voltage at node for a current filter is given by

is found and the driving the equivalent low-pass

(24) depends on the voltage across the However, since th resonator in the bandpass filter, the bandpass voltage at filter center frequency for an applied voltage , is expressed as [13] (25) for , where is the reflection parameter found from at [9]. The system of nonlinear algebraic equations in (20)–(25) does not have a purely analytical solution, and hence, is solved by iterative methods described in [14] to obtain node voltages across each resonator. At high input power, the voltages may be high enough to cause pull-down in MEMS switches [2]. In this case, the system of nonlinear equations will not have convergent solutions due to drastic change in the nonlinear capacitance–voltage relationship of the tuning element. Once is known, the capacitance and angular frequency variations in (18) and (19), respectively, are used to find the nonlinear perturbations in the real and imaginary directions using (7), (11), and (17). B. Noise Analysis The time-varying nature of pole-perturbations is due to noise sources that cause random capacitance variations in an LC resonator employing shunt capacitive MEMS switches [2]. It is important to derive expressions for random capacitance variations in a MEMS resonator in the presence of nonlinearity. Here, the approach is presented for Brownian noise and similar equations corresponding to other noise sources in MEMS switches can be derived accordingly. and anFig. 5(a) shows an RF signal with peak voltage gular frequency applied across the resonator. The MEMS switch has an up-state capacitance of , bridge inductance , and switch resistance . The resonator inductance is assumed lossless and has a value of . Fig. 5(b) shows various displacements in a MEMS switch, under the influence of an applied RF signal. In the absence of a biasing voltage and RF signal, the bridge height is . When the RF signal is applied, the self-biasing effect [2] causes beam deflection of resulting in a static

Fig. 5. (a) Tunable RF MEMS shunt resonator. (b) Various displacements in an RF MEMS shunt capacitive switch.

bridge height of . Brownian motion results in random diswhen an RF signal is absent, and placements of when an RF signal is present so that the overall bridge displacement is . A MEMS switch with an effective area , spring constant , damping factor , and mechanical self-resonant frequency has a thermally induced root-mean-square (rms) mechanical force acting on the bridge given by , where is the Boltzmann constant and is the temperature in kelvin. The power spectral density of Brownian motion displacement noise is given by [3] (26)

where is the mechanical offset frequency and is the mechanical quality factor. In the absence of an RF signal, a sinusoidal component of Brownian noise in a 1-Hz bandwidth is expressed as [3] around (27) where at low mechanical offset frequencies . If the MEMS switch capacitance has a parallel-plate capacand a fringing capacitance , itance , then where is the fringing factor and is the stored energy when the rms voltage across the MEMS switch is . However, in an LC resonator, is a time-varying function due to energy transfer between the capacitor and inductor. The instantaneous electrostatic force with reon the MEMS switch is obtained by differentiating spect to . The bridge displacements in the presence of an RF signal are then obtained by equating the electrostatic and spring restoring force to the total applied noise force and is expressed as (28) is the applied noise force that causes where noisy displacements. , (28) is solved In the absence of Brownian noise to find the static bridge height . Random displacements in the presence of Brownian noise are obtained by dividing (28) by spring constant and using binomial approximations to find as (29)

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Fig. 7. Nonlinear electromechanical CAD model of the RF MEMS switch. Fig. 6. Tunable MEMS resonator implemented with P switched capacitors.

where . The overall capacitance variation in the MEMS resonator is given by

phase noise [3], the effect of phase variations at the filter output when will be considered. Using (5), the phase variations of the th pole is perturbed due to noise in the th switch is expressed as

(30) in (29) and reIn the absence of an RF signal, . The noisy displacements in (29) are accurate at duces to low input power levels. When the rms voltage across the switch approaches pull-down voltage at high input power, and so that the denominator of (29) approaches zero. Clearly, this is unrealistic, and hence, higher order binomial terms must be considered in (28) for calculating when the switch is close to self-actuation at high input power. In practice, tunable MEMS resonators are realized with a parallel combination of switched capacitors, as shown in Fig. 6. Each switched capacitor is a series combination of a MEMS switch and a fixed metal–air–metal capacitor [15]. The noisy capacitance variation of each MEMS switch is calculated using must be used (29) and (30), but the voltage for calculation of static bridge displacement due to capacitive voltage division. Thus, the overall capacitance variation of a capacitor bank is the superposition of the noisy contribution of each MEMS switch. Since the Brownian noise sources are independent of each other, the resulting capacitance variations in each switch are also uncorrelated to each other [3]. Thus, noise sources in the resonator result in a time-varying capacitance that can be mapped to prototype perturbations using (7) and the corresponding time-varying pole-perturbations. The time-varying in (3) and low-pass frequencies are calculated using the perturbed filter response is found using (5). C. Phase Noise Calculations If the pole-perturbations due to nonlinearity and noise in the tunable filter are known, then the response of the filter to these variations can be calculated. The uncorrelated nature of independent Brownian noise sources implies that the noise power contribution due to each noise source must be calculated independently. For example, in a tunable filter with ideal inverters, which employs MEMS resonators with MEMS switches per resonator (Fig. 6), the perturbation of the th resonator only due is calculated, while to noise in the th switch assuming all other switches are noiseless. Since the amplitude noise of RF MEMS switches is at least 20 dB lower than its

(31) is the imaginary component of pole where is the signum function devariation described in (1) and fined as if if if In odd-order filters, the real-axis pole is unperturbed, and thus, and has a constant value independent of input power and noise. The signal at the filter output is expressed as (32) The phase noise power due to th switch in resonator , normalized to the output carrier power, is obtained by taking . The overall filter phase the Fourier transform of noise is obtained by summing the phase-noise contributions of each switch in every resonator in the filter topology, and is given by (33) Fig. 7 shows the nonlinear electromechanical CAD model of the RF MEMS switch [4]. The model is implemented in Agilent Technologies’ Advanced Design System (ADS)1 by using equation-based blocks to define: (A) static force generation in the switch, (B) Brownian noise source, (C) low-pass filtering of the MEMS bridge, and (D) a capacitor. The power-dependent noisy behavior of a MEMS switch is described by this nonlinear CAD model and is used in a resonator or inverter to find the tunable filter phase noise by performing harmonic balance noise simulation in ADS, and provides an independent means to verify the theory presented in this paper. 1ADS,

2006, Agilent Technologies, Palo Alto, CA.

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TABLE II MEMS SWITCH MODEL PARAMETERS

N

Fig. 8. (a) -pole lossless Butterworth/Chebyshev tunable filter with ideal admittance inverters. (b) Variable capacitor implementation using 2-bit RF MEMS switched capacitor banks. (c) Simulated S -parameters of a lossless two-pole tunable Butterworth filter with 1% fractional bandwidth.

TABLE I RESONATOR MODEL ELEMENT VALUES USED FOR ADS SIMULATIONS

IV. RF MEMS TUNABLE FILTER EXAMPLE In this section, the theory of pole-perturbations developed thus far will be applied to an RF MEMS tunable filter. The effect of nonlinearity on the pole distributions will be discussed and verified by group-delay calculations. Phase noise due to Brownian noise will be evaluated for different filter parameters and verified by harmonic balance noise simulations. A. Design A lossless -pole Butterworth/Chebyshev filter with a tunable center frequency from 14 to 18 GHz is shown in Fig. 8(a). In Fig. 8(b), the resonator capacitance is implemented as a 2-bit RF MEMS capacitor bank. The values of ideal lossless -inverters are calculated for a given fractional bandwidth using , formulas in [9]. Table I shows the resonator inductance and up/down-state cafixed metal–air–metal capacitors for each switched capacitor using the pacitances MEMS switch parameters in Table II. This switch could be the standard capacitive switch with a center pull-down electrode developed by [16] or a capacitive switch developed by The University of Michigan at Ann Arbor [15]. Fig. 8(c) shows the ADS -parameters for a two-pole lossless 1% Buttersimulation of worth filter. States 1 and 4 represent the situation where all the switches are in the up- and down-state, respectively.

is the rms voltage across the MEMS switch. The where nonlinear expression in (34) is valid as long as is less than of the MEMS switch. The resonator the pull-down voltage in Fig. 8 are calculated using (34) voltages in the nonlinear system of nodal equations, as described in Section III-A. The resulting prototype perturbations due to nonlinearity are evaluated using (7) corresponding to resonator . perturbations Fig. 9(a) shows nonlinear pole displacements in the absence of noise in a two-pole Butterworth and three-pole Chebyshev filter. As input power increases, higher resonator capacitance and susceptance slope implies that complex conjugate poles are toward the real-axis along the circle angularly displaced by or ellipse. However, the real-axis pole of the three-pole Chebyshev filter is unperturbed. The angular displacements calculated using (10) and (14) are shown in Fig. 9(b) as a function of input power for different fractional bandwidths. Filters with smaller fractional bandwidth exhibit greater nonlinearity due to larger resonator voltages , and consequently, have higher angular displacements for the same input power. The small angular pole-perturbations caused by filter nonlinearity do not noticeably affect the amplitude response of the filter. However, changes in the phase response affect the group delay of the bandpass filter. Nonlinear pole displacements are used to derive an analytical expression for power-dependent group delay at filter center frequency in the absence of noise by differentiating (31) with respect to , which is given by

(35) B. Nonlinearity Using the switch parameters in Table II, the capacitance–voltage variation in the up-state position is obtained by solving (28) in the absence of noise and curve fitting to a power-series approximation as in fF

(34)

where the summation includes the group-delay contribution of is the power-indepeneach complex-conjugate pole and dent group-delay contribution of the real-axis pole in odd-order filters, which is given by for Butterworth (36) for Chebyshev

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Fig. 9. (a) Nonlinear pole displacements in a two-pole Butterworth and three-pole Chebyshev filter. (b) Angular displacements of poles as a function of applied input power for different filter fractional bandwidths. (c) Group delay as a function of input power in two-pole Butterworth and three-pole Chebyshev filters for different filter fractional bandwidths. Theoretical values are compared to large-signal S -parameter (LSSP) simulations in ADS.

For even-order filters, due to the absence of a real-axis pole. To verify (35) and (36), group-delay values are calculated using large-signal -parameter simulations in Agilent ADS for lossless Butterworth and Chebyshev filters in Fig. 8 and the results show good agreement between theory and simulation [see Fig. 9(c)]. Small discrepancies between theory and simulation are due to the nonlinear approximation in (34). Since group delay is inversely proportional to filter , filters with small fractional bandwidth have bandwidth higher and rapidly changing group-delay values as input power is increased. Filters with larger group delay also have greater sensitivity to noise [5]. Hence, similar trends are expected in tunable filter phase noise as a function of input power. This is discussed in Section IV-C. C. Phase Noise

Fig. 10. Phase noise of lossless two-pole Butterworth and three-pole Chebyshev filters as a function of input power for different fractional bandwidths, eval kHz ! < ! around f GHz. uated at an offset of !

The nonlinear noise perturbations in RF MEMS tunable filters are used to calculate phase noise, as described in Section III-C. Phase noise is evaluated at a mechanical offset kHz from the filter center frequency frequency of dBm, unless otherof a particular tuning state with wise specified. The frequency offset is an arbitrary choice and gives the same phase noise values for other frequency offsets as . In the graphs that follow, all results obtained long as from harmonic balance simulations are denoted by “HB.” and Chebyshev The phase noise of Butterworth filters versus input power for different fractional bandwidths are shown in Fig. 10. In both cases, only two poles are fluctuating since real-axis poles are unperturbed. Smaller bandwidth filters also exhibit higher phase noise and increasing the input power results in higher phase noise. This is because smaller bandwidth filters have higher group delay and increasing input power results in higher values of group delay, as explained in Section IV-B. When the input power exceeds a , the resonator voltages results in threshold value the pull-down of MEMS switches in the tunable filter (shaded region in Fig. 10) [5]. Phase-noise values calculated around

filter center frequency in this region are invalid due to change in the filter tuning state. Fig. 11 shows the variation of phase noise with the filter tuning state in lossless Butterworth and Chebyshev filters for different fractional bandwidths. MEMS switches in the downstate position are not affected by Brownian noise because the bridge is fixed [3], and hence, state 4 does not exhibit phase noise. For states 2 and 3, phase noise decreases because the fluctuation of each pole is reduced due to the presence of only one Brownian noise source in the resonator. However, compared to state 2, state 3 exhibits lower phase noise because the resonator capacitance variation is smaller due to a higher fixed capacitance in series with the MEMS switch [see Fig. 8(b)]. Fig. 12 shows the variation of phase noise with mechanical for different fractional bandwidths. As frequency offset the mechanical frequency offset is increased, the magnitude of pole fluctuations follow the low-pass displacement noise spectrum described in (26). Consequently, phase noise remains apand decreases at a rate of proximately constant for 40 dB/decade for .

= 2 29

(

)

= 18

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Fig. 11. Phase noise of lossless two-pole Butterworth and three-pole Chebyshev filters versus tuning state for different fractional bandwidths, evaluated at an offset !  kHz ! < ! from the center frequency of that tuning dBm. state with P

= 2 29 = 020

(

)

Fig. 14. (a) Displacement of poles to the left by  due to losses present in the versus Q for different resonators of the tunable filter. (b) Phase noise P fractional bandwidths in a two-pole Butterworth and three-pole Chebyshev filter  kHz ! < with noise calculation performed at a frequency offset ! ! around f GHz with P dBm and normalized to the phase noise of the equivalent lossless filter.

( )

)

=

Fig. 12. Phase noise as a function of mechanical frequency offset around f GHz in lossless two-pole Butterworth and three-pole Chebyshev filters for dBm. different fractional bandwidths at P

18

= 020

= 18

= 020

= 2 29

(

V. FILTER NONIDEALITIES A. Resonator

Factor

In the practical realization of tunable filters, energy dissipation due to resistive losses in the resonator results in a finite un. If losses in the filter transfer loaded resonator factor function are taken into account, each pole on the left-half of the complex plane is moved to the left by a constant value , as shown in Fig. 14(a). For a lossy bandpass filter with fractional bandwidth , the dissipation factor is calculated as [17] (37)

Fig. 13. Phase noise as a function of filter order for different fractional bandwidths of lossless Butterworth and Chebyshev filters, evaluated at an offset  kHz ! < ! around f GHz with P dBm. !

=2 29

(

)

= 18

= 020

For higher filter orders, the group delay given by (35) and (36) increases due to greater number of positive summation terms, resulting in higher filter phase noise, as shown in Fig. 13, for the lossless case. Phase noise increases with filter order more rapidly in Chebyshev filters compared to Butterworth filters due to rapid increase of group delay with filter order in Chebyshev filters, which can be found using (35) and (36). In practice, filter resonators and inverters always dissipate energy due to loss mechanisms. Inverters also exhibit frequencydependent behavior as the filter center frequency is tuned. These bandpass filter nonidealities affect the pole-perturbations of the equivalent prototype filter and need to be considered in greater detail.

is obtained by the Thus, the real-axis component of pole . The filter transformation group delay obtained by including time variance in (35) deis approximately proportional to creases because . The reduction in group delay is more drastic in filters with small fractional bandwidth. Hence, as the filter , reduced filter group insertion loss increases due to lower delay at center frequency causes phase noise to decrease, as shown in Fig. 14(b). The phase noise values obtained from theory are in good agreement with harmonic balance simulations of the tunable filter shown in Fig. 8 with a resistance in parallel with each resonator. All phase-noise calculations are performed at a frequency offset kHz around GHz with dBm and normalized to the phase noise of an equivalent lossless filter. However, reducing filter phase noise by lowering resonator factors is impractical because the resulting filters have poor insertion loss, especially for filters with small fractional bandwidth. For has example, a three-pole 1% Chebyshev filter with

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Fig. 15. Variation of phase noise versus input power in a two-pole Butterworth and three-pole Chebyshev filter with 1% fractional bandwidths for and . Phase noise is evaulated at a frequency offset kHz around GHz.

Q = 500 (! < ! )

f = 18

Q = 100 ! = 229

an insertion loss of around 17 dB, which is not a realistic value for practical applications. When resistive losses are present, there is a thermal noise voltage associated with the equivalent resistance in each resonator. Thermal noise does not alter the level of filter phase noise because it does not result in any changes in the reactance of filter components. However, it results in an overall increase in the amplitude noise level at the filter output and is estimated using harmonic balance simulation. For all the cases considered here, the presence of thermal noise increases the amplitude noise level by a maximum value of 5 dB for high fractional bandwidth filters. However, the resulting amplitude noise is still insignificant compared to the phase noise at the filter output. As input power is increased, the internal node voltages must be calculated as described in Section III-A by shunting each node in the low-pass filter [see Fig. 4(b)] by a conductance . Nonlinear pole displacements due to internal voltages in lossy filters must be considered in phase-noise computation. Fig. 15 shows the variation of phase noise versus input power for diffor 1% Butterworth and Chebyferent values of filters. Phase noise is relatively insensitive to shev input power at low in 1% filters because the pole displacement by due to loss makes the group-delay function relatively insensitive to nonlinear pole displacements. In filters with 8% fractional bandwidth, phase noise increases with input because phase power, as shown in Fig. 10, even for for high bandwidth filters. noise is relatively insensitive to B. Nonideal Inverters Equivalent -models for inductive and capacitive implementations of admittance inverters are shown in Fig. 16(a) and (b). Practical inverter networks exhibit frequency dependence and dissipate energy due to resistive losses. A generalized frequency-dependent admittance inverter including loss mechanisms is shown in Fig. 16(c) [18]. Tunable inverter networks have also been implemented to achieve constant fractional bandwidth or good input matching over the filter tuning range [19]. In this section, the effect of inverter implementation on RF MEMS filter phase noise is investigated using the pole-perturbation method. 1) Frequency Dependence: In practical filters, inverters are designed at the filter center frequency and are considered to be frequency independent within the filter passband in narrowband ( 10%) filters. However, as the filter is tuned to frequencies away from the design frequency, the change in -inverter values



Fig. 16. Equivalent -models for admittance inverters using: (a) inductors and (b) capacitors. (c) Generalized lossy admittance inverter.

result in bandwidth variation as the filter is tuned. As a result, the filter phase noise also exhibits frequency-dependent behavior based on the inverter implementation. The inductive inverter in Fig. 16(a) is commonly implemented as a transformer with coupling coefficient [20], while the capacitive inverter in Fig. 16(b) is implemented as a series capacitor [19]. In both cases, the negative shunt elements are absorbed into adjacent resonators. For an -pole tunable filter, the expressions for half-admittance input/output -inverters ) and inter-resonator -inverters are expressed as [21] (38) where, for inductive inverters,

(39) and for capacitive inverters,

(40) for . For inductive inverters, and are the coupling coefficients for the input/output and inter-resis the self-inductance onator transformers, respectively, and and are seof each transformer winding. Similarly, ries capacitors in capacitive inverters. The expressions for frequency-dependent inverters are used as a to calculate the impedance normalization factor function of frequency using (8). The resulting frequency-dependent pole displacements are calculated from (7) and used to compute phase noise due to Brownian motion in the resonators. Fig. 17 shows the phase-noise variation in lossless Butterand Chebyshev filters [see Fig. 8] with worth 1% and 8% fractional bandwidths versus tuning state for different inverter implementations. Phase noise is evaluated with dBm at a frequency offset kHz around the center frequency of that tuning state. For inductive inverters, the -inverter values are monotonically decreasing functions of frequency so that fractional bandwidth increases as the filter is tuned to lower frequencies. Consequently, lower filter group delay causes a rapid decrease of phase noise as the filter is tuned compared to the ideal case. For capacitive inverters, fractional bandwidth decreases as the filter

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TABLE III TUNABLE FILTER MODEL ELEMENT VALUES

Fig. 17. Comparison of phase noise versus tuning state in lossless Butterworth ( = 2) and Chebyshev ( = 3) filters with: (a) 1% and (b) 8% fractional bandwidths employing ideal, capacitive, and inductive inverters. Phase noise is evaluated with P = 20 dBm at a frequency offset ! = 2 9 kHz around the center frequency of that tuning state.

N

N

0

2

Fig. 19. Variation of phase noise with tuning state in a two-pole Chebyshev filter with a constant fractional bandwidth of 8 0.1% considering only noisy inverters, only noisy resonators, and both noisy inverters and resonators. Phase noise is evaluated with P = 20 dBm at a frequency offset ! = 2 9 kHz around the center frequency of that tuning state. The MEMS switch combinations for each state are also shown in the figure where “0” and “1” represent up- and down-state positions, respectively.

6

0

Fig. 18. (a) Lossless two-pole Chebyshev filter tunable from 15 to 18 GHz with a constant fractional bandwidth of 8 0:1% with 2-bit switched-capacitor bank implementations of: (b) input/output capacitor C , (c) resonator capacitance C , and (d) inter-resonator capacitance C .

6

is tuned to lower frequencies resulting in slower decrease of phase noise compared to the ideal case. In all cases, increasing the input power increases phase noise for all tuning states, which depends on the nonlinear behavior of resonators of that tuning state, as discussed earlier. 2) Tunability: Filters with inductively coupled resonators and capacitive tuning mechanisms exhibit relatively constant fractional bandwidth as the filter is tuned, but exhibit degradation of input matching in wideband tunable filters [15]. Instead, tunable MEMS capacitive inverters may be employed to adjust the -inverter values to maintain constant fractional bandwidth and good input matching simultaneously [19]. Fig. 18 shows a lossless two-pole Chebyshev filter tunable from 15–18 GHz implemented with 2-bit switched capacitor banks in the resonators and inverters, and has fractional bandwidths of 8 0.1% over all tuning states. The parameters of the MEMS switch are the same as the one in Table II and the values of inductors and fixed capacitors are given in Table III. The resonator implementation is different compared to Fig. 8(b), and hence, a corresponding change in phase noise is expected for the same filter bandwidth.

2

MEMS tunable inverters are additional sources of noise in a tunable filter that increase the level of phase noise at the filter and result output. The noisy inverter capacitors and in noisy inverter values, [see (38) and (40)], where and are the voltages across the respective inverters. Thus, the impedance normalization and the resulting pole displacements obfactor tained are used to calculate phase noise. Fig. 19 shows the phase-noise values obtained from theory and harmonic balance simulation. Phase noise is evaluated with dBm at a frequency offset kHz around the center frequency of that tuning state. In case 1, the resonators are assumed to be noiseless and phase noise only due to noisy inverters is calculated and results in around 4–6-dB lower phase noise than the filter with noiseless inverters and noisy resonators (case 2) for all tuning states. When the input power is changed from 20 to 20 dBm for case 1, the phase noise increases by less than 0.1 dB, implying that MEMS tunable inverter nonlinearity is not a significant factor in phase-noise calculation. Noise from tunable inverters increases the overall phase noise of the dBm. tunable filter (case 3) by just around 1.1 dB for This analysis shows that the dominant source of nonlinear noise in tunable filters is the fluctuations in the resonators and the effect of nonlinear noise in inverters is relatively insignificant. 3) Loss: Inverter losses result in a resistive signal path between two resonators besides a reactive path and is represented by a complex admittance inverter with susceptance and conas , as shown in Fig. 16(c). If the ductance , then series element of the inverter has a quality factor of . The negative loss associated with the shunt elements is absorbed by an adjacent lossy microwave resonator

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for which this happens is termed the thermal-noise range of region and the resulting SNR in a 1-Hz noise bandwidth is (43) However, if the received signal is strong, the filter phase noise dominates so that and , as is termed shown in Fig. 20(c). The corresponding range of the phase-noise region and the resulting SNR in a 1-Hz noise bandwidth is Fig. 20. (a) Antenna and tunable filter in a 50- system. (b) Thermal and phase noise when the received signal is weak (thermal noise region: P P ). (c) Thermal and phase noise when the received signal is strong (phase noise P ). region: P





[18]. Assuming resonators have a finite factor, and that all inverters have the same quality factor , phase noise calculations for Butterworth and Chebyshev tunable filters with different fractional bandwidths using complex values of admittance inverters indicate that filter phase-noise variation due to inverter . Since typical realizations of loss is insignificant for fixed/tunable inverters in MEMS filters (interdigital capacitors, coupled inductors, tunable capacitor banks, etc.) have quality factors much greater than 10, phase-noise variation due to inverter losses is negligible.

(44) Since the quantity is inversely related to the relative phase , the SNR remains relatively constant at noise of the filter low power, but decreases slightly when MEMS switches are close to pull-down due to increase in filter phase noise. SNR lower given by (44) is valid only for offset frequencies of the MEMS than the mechanical resonant frequency . For , the phase noise decreases bridge at a rate of 40 dB/dec and is eventually limited by the thermal . noise floor, and SNR is given by (43) for is The received signal strength for which , and determines the input termed critical input power power for which the transition occurs from the thermal-noise to and using phase-noise region. Equating (42) to at , the critical input power is given by

VI. SNR ANALYSIS

(45)

In this section, the implications of phase noise on the SNR at the output of the MEMS tunable filter are discussed. Fig. 20(a) shows an antenna connected to the input of a MEMS tunable bandpass filter in a 50- system. The equivalent noise resistance of the antenna is assumed to be 50 . All power values are expressed in watts unless otherwise specified. A. Basics The antenna receives a sinusoidal signal at the center freof the tunable filter so that the signal strength at the quency input of the tunable filter is and thermal noise in a 1-Hz band. The filter output power is , width around is is the fraction of power transmitted from the input to where output of the filter, and is related to the filter quality factor and order. The tunable filter is assumed to have both thermal and phase noise so that the total noise at the filter output is (41) is the total thermal noise power and is the where absolute level of phase noise power at the filter output in a 1-Hz given by bandwidth around dBc/Hz

(42)

where is the phase-noise power in dBc/Hz calculated as discussed in Section III-C. The output SNR of the filter is the and . ratio of is weak, then the filter phase If the received signal noise lies below the thermal noise floor of the system so that and , as shown in Fig. 20(b). The

Here, and the resulting SNR value lies in between the weak and strong signal cases. B. Results Fig. 21 shows the noise power and SNR calculated using the harmonic balance method in a 1-Hz bandwidth around GHz. The analysis is performed for Butterworth and Chebyshev filters introduced in Section IV as a for different fractional function of received signal power bandwidths and quality factors when all switches are in the up-state position. The filter insertion loss is also specified for each case. The results in each region are discussed as follows. , the output noise • In the thermal-noise region floor is a constant value and SNR increases with according to (43). For filters with high quality factor , the output SNR is insensitive to filter type, order, bandwidth, and mechanical properties of the MEMS . Lowering the filter quality switch as long as factor decreases the output SNR due to two reasons, which are: 1) the output signal is attenuated due to filter losses and 2) the resistive losses in the filter raises the thermal noise floor, as shown in Fig. 21. For example, in a 1% , the SNR degradation in the Butterworth filter is changed from 500 to 100 thermal noise region when is 17.5 dB. , the noise power begins to increase due to filter • At has lower values for smaller phase noise. From (45), and larger factors. Filters with lower bandwidth and higher order have a higher value of , which corresponds to smaller factor. On the other hand, higher quality factor

SEKAR AND ENTESARI: POLE-PERTURBATION THEORY FOR NONLINEAR NOISE ANALYSIS OF ALL-POLE RF MEMS TUNABLE FILTERS

= 18

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( = 2)

Fig. 21. Total noise power and SNR calculated using harmonic balance in a 1-Hz bandwidth around f GHz for: (a) Butterworth N and (b) Chebyshev filters versus received signal power P for different fractional bandwidths and quality factors when all switches are in the up-state position. The filter N insertion loss for each case is also listed.

( = 3)

( )

filters have a large factor. Therefore, such filters result in low values of critical input power. For example, dBm and dBm for 1% and 4% Butterworth filters, respectively, with , and dBm for 1% Butterworth filters with . , the SNR reaches a • In the phase noise region maximum value defined by (44) because the phase noise increases at the same rate as the signal power level . The SNR saturation level is lower for lower bandwidth is higher (see Fig. 10). However, lowfilters because ering the filter quality factor increases the output SNR beis lower for filters with lower quality factor (see cause , Fig. 14). For example, in a 1% Butterworth filter is changed the SNR improvement is around 3 dB when from 500 to 100. is lowered, the SNR degradation in the thermal-noise reAs gion is drastic compared to the improvement in the phase-noise region. SNR degradation is critical in the thermal-noise region because the received signal is already weak. Thus, a MEMS tunvalue to achieve the best SNR able filter must have a high in the thermal region at the cost of slightly lower SNR in the phase-noise region.

of filter phase noise can be safely ignored in MEMS tunable filters with wider bandwidth and moderate quality factor since the phase-noise region occurs at higher input power where SNR degradation is not critical to the receiver performance. VII. CONCLUSION This paper has presented a new methodology to predict the effect of nonlinear noise in all-pole RF MEMS tunable filters. The variations in the filter output signal due to noise were entirely described in terms of pole-perturbations of the filter transfer function. Closed-form equations were derived to find the perturbations of poles in Butterworth and Chebyshev filters due to nonlinearity and noise. The pole-perturbation theory was applied to calculate nonlinear noise in RF MEMS tunable filters due to Brownian motion as a function of filter input power, tuning state, fractional bandwidth, filter order, and frequency offset. Higher order filters with small fractional bandwidth exhibited maximum phase noise, which increased with input power. Lowering the filter quality factor resulted in decreasing phase noise while increasing the insertion loss. The frequency-dependence of nonideal fixed and tunable inverters also had an insignificant effect on filter phase noise. The maximum output SNR degradation occurs at low input powers in filters with low fractional bandwidth, high order, and high quality factor.

C. Discussion The existence of phase noise in MEMS tunable filters imposes an upper bound on the maximum achievable SNR at the filter output, for a given filter topology. However, the relative importance of this phenomena in a MEMS tunable filter application is evaluated by calculating the critical input power . imply that the maximum achievable SNR is Lower values of lower and that the phase-noise region occurs at lower values of received signal power. Both these effects are critical if the received signal is already weak, and are dominant in filters with higher phase noise. Therefore, filters with low fractional bandwidth, high order, and high quality factor are most prone to SNR degradation at low values of received input power. The effect

APPENDIX A DERIVATION OF (7) For synchronously tuned filters [see Fig. 1(a)], the susceptance slope of resonators are equal and are expressed as . The shunt capacitance of the th resonator is obtained from the low-pass prototype element value of the , where is ladder network in Fig. 1(b) as an impedance normalization factor, which may be rewritten in terms of as (A.1)

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where is the susceptance slope of the resonator. The expressions in (6) may be rewritten in terms of prototype element values as

Substituting for

and subsequent rearrangement gives

(B.7) (A.2) and so on. Comparing (A.1) and (A.2), a generalized expression for is given by (8), and (7) is obtained from .

APPENDIX B DERIVATION OF (14)

REFERENCES

The general expressions for low-pass prototype values of a Chebyshev filter are given by [9] (B.1) and are given by (16). Using where above equation may be rearranged to obtain comparison with (14) results in

, the , and

(B.2)

A. Case 1: Is Odd The recurring relation for in (B.1) is used to calculate a general expression for by considering the ratio of the product of prototype values expressed as

(B.3) in (B.3) using (B.1) and subsequent reSubstituting for arrangement gives (B.4) and comparison of (B.4) with (14) results in (B.5)

B. Case 2: Is Even Similarly, a general expression for

Using (B.2), (B.5), and (B.7), a generalized expression for is given by (15) so that the angular pole locations in a Chebyshev filter satisfy (14).

may be calculated as

(B.6)

[1] A. Tasic, A. Serdijn, and J. R. Long, “Adaptive multi-standard circuits and systems for wireless communications,” IEEE Circuits Syst. Mag., vol. 6, no. 1, pp. 29–37, Jan. 2006. [2] G. M. Rebeiz, RF MEMS Theory, Design and Technology. New York: Wiley, 2003. [3] G. M. Rebeiz, “Phase-noise analysis of MEMS-based circuits and phase shifters,” IEEE Trans. Microw. Theory Tech., vol. 50, no. 5, pp. 1316–1323, May 2002. [4] L. Dussopt and G. M. Rebeiz, “Intermodulation distortion and power handling in RF MEMS switches, varactors and tunable filters,” IEEE Trans. Microw. Theory Tech., vol. 51, no. 4, pp. 1247–1256, Apr. 2003. [5] V. Sekar and K. Entesari, “Effect of filter parameters on the phase noise of RF MEMS tunable filters employing shunt capacitive switches,” Int. J. RF Microw. Comput.-Aided Eng., vol. 20, no. 1, pp. 114–121, Jan. 2010. [6] A. G. Place and G. H. Allen, “Generalized pole sensitivity analysis due to parameter perturbation,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 44, no. 10, pp. 869–873, Oct. 1997. [7] D. Deschrijver and T. Dhaene, “Fast passivity enforcement of S -parameter macromodels by pole perturbation,” IEEE Trans. Microw. Theory Tech., vol. 57, no. 3, pp. 620–626, Mar. 2009. [8] M. E. Van Valkenberg, Modern Network Synthesis. New York: Wiley, 1960. [9] J. S. Hong and M. J. Lancaster, Microstrip Filters for RF/Microwave Applications. New York: Wiley, 2001. [10] K. Entesari and G. M. Rebeiz, “RF MEMS, BST, and GaAs varactor system-level response in complex modulation systems,” Int. J. RF Microw. Comput.-Aided Eng., vol. 18, no. 1, pp. 86–98, Sep. 2007. [11] M. Koochakzadeh and A. Abbaspour-Tamijani, “Closed-form formulas for predicting the nonlinear behavior of all-pole bandpass filters,” IEEE Trans. Microw. Theory Tech., vol. 56, no. 3, pp. 575–586, Mar. 2008. [12] I. Bahl and P. Bhartia, Microwave Solid State Circuit Design. New York: Wiley, 1988. [13] A. Sivadas, M. Yu, and R. Cameron, “A simplified analysis for high power microwave bandpass filter structures,” in IEEE MTT-S Int. Microw. Symp. Dig., 2000, vol. 3, pp. 1771–1774. [14] W. C. Rheinboldt, Methods for Solving Systems of Nonlinear Equations. Philadelphia, PA: Soc. Ind. Appl. Math., 1998. [15] K. Entesari and G. M. Rebeiz, “A 12–18 GHz three pole RF MEMS tunable filter,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 8, pp. 2566–2571, Aug. 2005. [16] C. L. Goldsmith, Z. Yao, S. Eshelman, and D. Denniston, “Performance of low-loss RF MEMS capacitive switches,” IEEE Microw. Guided Wave Lett., vol. 8, no. 8, pp. 269–271, Aug. 1998. [17] R. J. Cameron, C. M. Kudsia, and R. R. Mansour, Microwave Filters for Communication Systems: Fundamentals, Design and Applications. New York: Wiley, 2007. [18] V. Miraftab and M. Yu, “Advanced coupling matrix and admittance function synthesis techniques for dissipative microwave filters,” IEEE Trans. Microw. Theory Tech., vol. 57, no. 10, pp. 2429–2438, Oct. 2009. [19] K. Entesari and G. M. Rebeiz, “A 25–75-MHz RF MEMS tunable filter,” IEEE Trans. Microw. Theory Tech., vol. 55, no. 11, pp. 2399–2405, Nov. 2007. [20] K. Entesari and G. M. Rebeiz, “A differential 4-bit 6.5–10-GHz RF MEMS tunable filter,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 3, pp. 1103–1110, Mar. 2005.

SEKAR AND ENTESARI: POLE-PERTURBATION THEORY FOR NONLINEAR NOISE ANALYSIS OF ALL-POLE RF MEMS TUNABLE FILTERS

[21] G. L. Matthaei, E. Young, and E. M. T. Jones, Microwave Filters, Impedance-Matching Networks, and Coupling Structures. Norwood, MA: Artech House, 1980. Vikram Sekar (S’07–M’09) received the Bachelors degree in electrical engineering from Visveswariah Technological University, Belgaum, India, in 2006, the M.S. degree in electrical engineering from Texas A&M University, College Station, in 2008, and is currently working toward the Ph.D. degree in electrical engineering at Texas A&M University. He was an Intern with Texas Instruments Incorporated, Dallas, TX, during the summers of 2007 and 2008, where he was involved with signal integrity issues and system-level electromagnetic analysis of printed-circuit boards for wireless handsets. His research interests include design of tunable RF components, microwave filter theory, and development of microwave-based platforms for biosensing applications.

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Kamran Entesari (S’03–M’06) received the B.S. degree in electrical engineering from the Sharif University of Technology, Tehran, Iran, in 1995, the M.S. degree in electrical engineering from Tehran Polytechnic University, Tehran, Iran, in 1999, and the Ph.D. degree from The University of Michigan at Ann Arbor, in 2005. In 2006, he joined the Department of Electrical and Computer Engineering, Texas A&M University, College Station, where he is currently an Assistant Professor. His research interests include design of RF/microwave/millimeter-wave integrated circuits and systems, RF MEMS, related front-end analog electronic circuits, and medical electronics. Dr. Entesari was the corecipient of the 2009 Semiconductor Research Corporation (SRC) Design Contest Second Project Award for his work on dual-band millimeter-wave receivers on silicon.

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Characterization of GaN HEMT Low-Frequency Dispersion Through a Multiharmonic Measurement System Antonio Raffo, Member, IEEE, Sergio Di Falco, Student Member, IEEE, Valeria Vadalà, Student Member, IEEE, and Giorgio Vannini, Member, IEEE

Abstract—In this paper, the experimental characterization of low-frequency dispersion (i.e., long-term memory effects) affecting microwave GaN HEMTs is carried out by adopting a new nonlinear measurement system, which is based on low-frequency multiharmonic signal sources. The proposed setup, which has been fully automated by a control software procedure, enables given source/load device terminations at fundamental and harmonic frequencies to be synthesized. Different experimental results are provided to characterize well-known effects related to low-frequency dispersion (e.g., knee walkout and drain current collapse) and to demonstrate the validity of assumptions commonly adopted for electron device modeling. Index Terms—Field-effect transistors (FETs), microwave amplifiers, semiconductor device measurements, semiconductor device modeling, time-domain measurements.

I. INTRODUCTION LECTRON device traps and thermal effects (i.e., low-frequency dispersion phenomena) represent a critical issue in microwave device nonlinear modeling and circuit design, especially when new technologies (e.g., GaN) are investigated. Although latest technologies are not ready for large-scale production, they strongly attract the interest of the research community. As a consequence, it is necessary to provide modeling and design tools also in the presence of important low-frequency dispersion effects, which would be unacceptable for practical applications. An example is provided by the GaN technology: although preliminary devices showed a 70% current collapse under dynamic operation, GaN technology and related topics have immediately dominated the most important microwave conferences and journals due to the GaN promising performance. When dealing with the empirical characterization of electron device low-frequency dispersion a widely adopted approach is represented by pulsed I/V setups [1]. Although pulsed measurements have the unique capability of providing iso-thermal and

E

Manuscript received December 18, 2009; revised May 18, 2010; accepted June 04, 2010. Date of publication August 09, 2010; date of current version September 10, 2010. This work was supported in part by the Italian Ministry of Instruction, University and Research (MIUR). The authors are with the Department of Engineering, University of Ferrara, 44100-Ferrara, Italy (e-mail: [email protected]; [email protected]; [email protected]; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2010.2058934

iso-dynamic device characteristics, they exhibit different critical aspects. Conventional pulse generators can easily satisfy their specifications, in terms of duration and amplitude of the pulse, in a 50- environment. However, such an operating condition is not representative for a microwave transistor, which is a nonlinear dynamic load. As a matter of fact, this leads to critical and device-dependent calibration procedures. Moreover, pulsed waveforms present a very small energetic content (ideally zero), a condition that is very far from microwave circuit actual operation. An alternative measurement system based on sinusoidal excitation was presented in [2], and extended in [3], where two signal sources were exploited to obtain automatic load synthesis capability. In particular, in [3], the electron device resistive core (i.e., the part of the intrinsic device, which is subject to the most important dispersive, thermal and nonlinear effects and is responsible for output power delivery) was characterized and exploited, in conjunction with a lookup-table model of the device capacitances, to successfully design class-A/AB power amplifiers. In this paper, the measurement system proposed in [2] and [3] is extended by adopting multiharmonic signal sources. The new setup has been fully automated by a control software procedure, which synthesizes given source and load device terminations both at fundamental and harmonic frequencies. Such a device characterization has been exploited in this work as a valuable tool to investigate GaN HEMT low-frequency dispersion effects. High-efficiency classes of operation for power amplifiers have become strategic topics since power efficiency represents a key issue to meet the severe performance required by modern microwave systems. As is well known, more- (e.g., class B) or less-conventional (e.g., class F) high-efficiency amplifier modes [4], [5] need the appropriate source and load terminations not only at the fundamental, but also at harmonic frequencies. The setups adopted in [2] and [3], where only the fundamental harmonic component is controlled, are not useful in this context; on the contrary, the measurement system here proposed can be used for accurate I/V device modeling under strongly nonlinear regimes or even exploited for high-efficiency power-amplifier design by using an approach similar to the one proposed in [3]. Although high-frequency time-domain measurement systems have been largely and successfully adopted to investigate lowfrequency dispersive effects and high-efficiency operation (e.g., [5]–[15]), the new idea of exploiting a low-frequency setup to

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RAFFO et al.: CHARACTERIZATION OF GaN HEMT LOW-FREQUENCY DISPERSION

Fig. 1. Block diagram of the proposed measurement system.

directly investigate the device resistive core behavior [3] under realistic load lines provides, as will be shown in the following, a number of advantages. II. NEW LARGE-SIGNAL MEASUREMENT SETUP The architecture of the proposed large-signal low-frequency measurement system is shown in Fig. 1. In particular, the function generator has two 50- channels that can independently provide arbitrary waveforms in the frequency range (1 mHz–120 MHz). To overcome the power limitation of the function generator, a 30-W power amplifier is cascaded to the channel devoted to the device output port excitation. Two wideband (10 kHz-400 MHz) dual directional couplers monitor the device-under-test (DUT) incident and reflected waves, which are acquired by means of a four-channel digital oscilloscope (4 GSamples/s). A high-resolution (4 V; 20 fA) and accurate (V: 0.05%, I: 0.2%) dc source provides the bias for the DUT. To ensure dc and RF path isolation, two wideband (200 kHz–12 GHz) bias-tees are used. In order to characterize only the device resistive core [3], it is necessary to operate at frequencies where the dynamic effects associated to charge storage variations and/or finite transit times can be neglected. Moreover, it is of primary interest to characterize device response above the cutoff of low-frequency dispersion (this is why pulsed setups exploit very short pulse duration). To this end, a 2-MHz fundamental frequency has been found adequate for the electron devices considered in this work. The validity of such a choice has been verified on the basis of -parameter measurements carried out, in the frequency range (300 kHz–98 MHz), by exploiting a low-frequency vector network analyzer (VNA) (HP4195A). More precisely, Fig. 2 shows the measured output conductance for a 0.25- m GaN HEMT device having a periphery of 400 m, under two different bias conditions corresponding, respectively, to class-A and class-AB operation. In the same figure, the output conductance dc values are also reported to highlight that frequency variations in the range (2 MHz–98 MHz) are negligible. This confirms that a 2-MHz frequency is sufficient to operate above the cutoff of low-frequency dispersion coherently with the large number of papers (e.g., [16]) devoted to microwave device characterization where pulsed measurements with a pulsewidth of 500 ns or longer have been adopted. In the selected frequency range, all the measurement setup components satisfy linear nondistortion conditions. This

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Fig. 2. 400-m GaN HEMT output conductance versus frequency for two difV, V V (triangles), and V V, ferent bias conditions: V V (circles). The filled symbols represent the output conductance V value at 2 MHz.

= 25

= 03

= 20

= 02

greatly simplifies the setup calibration procedure, which practically consists in the experimental characterization of the two and ) shown in Fig. 1. The charfour-port networks ( acterization can be carried out by adopting the same procedure that has been fully detailed in [2] or, alternatively, by simply exploiting a low-frequency VNA (HP4195A). By observing the block diagram shown in Fig. 1, it is evident that the proposed setup looks similar to a large-signal network analyzer (LSNA) [8]–[14]. The similarity becomes more pronounced by considering the LSNA architecture recently proposed by Mesuro Limited1 [15], which is based on a sampling oscilloscope operating at microwave frequencies. Nevertheless, the setup proposed in this paper is specifically oriented to the characterization of dispersion affecting I/V dynamic characteristics. In this context, the low-frequency operation makes the required instrumentation inexpensive and avoids complex calibration procedures, which are essentially related to microwave operation [10], [17]. The measurement setup has been automated via an IEEE488 standard interface by means of a commercial instrument automation software. The graphical user interface (Fig. 3) of the control software enables measurements to be carried out in an automated way: the user can define the dc parameters, in terms of a bias grid (voltage or current) and related compliances, in accordance with the device safe operating area. The two channels of the signal generator, which sets the incident signals applied to the device ports, are controlled in an independent way: for each one, the user can define the fundamental frequency component and the number of harmonics. For a maximum level of flexibility, the user can arbitrarily define amplitude and phase for each spectral component.

III. EXPERIMENTAL RESULTS To highlight the capabilities of the described setup, largesignal measurements, oriented to high-efficiency power amplifier design [4]–[6], were carried out on a 0.7 800 m GaN V and V HEMT. The bias condition was (class B operation), whereas the incident signals applied at the 1Mesuro Limited, Cardiff, U.K. [Online]. Available: http://www.mesuro. com/

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Fig. 3. Graphical user interface of the control software. TABLE I MAGNITUDE AND PHASE OF THE RF SIGNALS APPLIED TO THE DUT

DUT ports are summarized in Table I in terms of their spectral components. Fig. 4(a) shows the dynamic load line corresponding to the described measurement condition. It is evident that a typical high-efficiency operation is obtainable by simply controlling the amplitude and phase of the fundamental, second, and third harmonic components of the incident signal at the drain terminal of the DUT. In this particular case study, an output power of 2.2 W was measured, corresponding to a drain efficiency of 74%. At a few megahertz, the input port of a field-effect transistor (FET) behaves as an open circuit until the off-state of the gate–source diode is preserved. This greatly simplifies the control of the gate incident signal. In the present case, a 4-V amplitude of the gate input voltage is imposed, which leads to a peak-value equal to 0 V. In Fig. 4(a), the device dc characV V are shown: it is well evident teristics that, due to the current collapse [7], the load-line is not able to dynamically reach the drain-current values corresponding to V. Moreover, an important knee the dc characteristic at walkout [7], [9] is present. It is evident how the proposed setup effectively characterizes the limits of the given technology. Time-domain waveforms at the drain port of the electron device are shown in Fig. 4(b). The dynamic current looks like an half-wave rectified sine-wave, which is different from zero where the drain voltage is minimum, according with high-efficiency power-amplifier operation modes [4], [5]. In this context, the capability of synthesizing a given load-line and get information on suitable drain and gate terminations for the device resistive core can be exploited not only for I/V modeling under realistic operation, but also for amplifier design following approaches like the one proposed in [3]. It is of interest to investigate some commonly accepted assumptions related to power amplifier design. Computer-aided design (CAD)-based amplifier design techniques are based on

Fig. 4. Measurements performed by exploiting the proposed large-signal measurement system on a 800-m GaN HEMT device, quiescent condition (V = 4 V; V = 25 V). (a) The measured load line is superimposed to dc charac0 V; step 0:5 V). (b) Time-domain voltage (continteristics ( 4 V V uous line) and current (triangles) waveforms at the device drain terminal, corresponding to the synthesized high-efficiency operation.

0

0





the accurate knowledge of the device intrinsic resistive core. A clear example is provided by the Cripps’ load-line theory [4], which identifies the optimum device operation by analyzing the device dc characteristics and defining the optimum loading condition as the resistance that maximizes voltage and current excursions. As a matter of fact, all amplifier design techniques, from class-A to high efficiency (e.g., class F), are de facto based on the definition of the optimum waveforms of the electrical quantities at the device intrinsic current source, i.e., the device resistive core. However, due to traps and thermal effects [18], [19], the transistor resistive core shows under dynamic operation a behavior that is very different with respect to the static one. The proposed setup has the unique capability of directly and exhaustively characterizing such a behavior. As a case study we investigate the behavior of a 0.25 400 m GaN HEMT under high-efficiency operation. In particular, Fig. 5 shows three different load lines providing the different performance levels reported in Table II. Also in this case, the impact of low-frequency dispersion on the device performance is well evident. The device is not able to V and the I/V dynamically reach the dc characteristic at knee under dynamic operation is quite far from the dc one. Both these phenomena, by limiting the drain current and voltage excursions, reduce the deliverable output power with respect to the one predictable on the basis of the dc characteristics. By observing the load lines in Fig. 5, at a first glance it is well evident which is the best one. Efficiency and power are the worst

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Fig. 5. Different load lines synthesized by exploiting the proposed large-signal measurement system on a 400-m GaN HEMT device, quiescent condition (V = 4 V; V = 30 V). Amplitude of the gate incident signal fundamental phasor A = 2:5 V. Relative phase between gate and drain incident signal fundamental phasors 1' = 180 . The measured load lines are super1 V; step 0:5 V). imposed to dc characteristics ( 6 V V

0

0





TABLE II PERFORMANCE RELATED TO THE DIFFERENT LOAD LINES SHOWN IN FIG. 5

ones for the thick load line since it involves the highest dissipation path and minimizes the drain current excursion. Similar considerations indicate that the thin load line is the best one. Such a simplicity in stating the best operating condition has to be regarded as peculiar to the proposed setup since a similar information cannot be drawn by observing extrinsic load lines carried out at microwave frequencies. Theoretical considerations can be also carried out by observing the intrinsic drain voltage waveforms corresponding to the considered load lines; they are shown in Fig. 6 with their harmonic components. Fig. 6(a) refers to the thick load line; in this case, only the fundamental tones of the input and output incident signals have been controlled. This is evident by looking at the second and third harmonics, which assume very low amplitudes. Fig. 6(b) refers to the circles load line; in this case, the amplitude and phase of the third harmonic of the output incident signal have also been manipulated. It is evident the contribution of the third-harmonic, which, being out-of-phase with respect to the fundamental one, raises the amplifier performance according to class-F operation [5]. Nevertheless, class-F operation requires also a short loading condition at the second harmonic, this condition can be simply obtained by also manipulating the second harmonic of the output incident signal. The result is shown in Fig. 6(c), where the amplitude of the second harmonic has been halved. In Table III, the load impedances synthesized for the different load lines are reported. The impedances at the second and third harmonics differ from 50 although, for the thick load line, only the fundamental phasor of the incident signals has been exploited. This can be explained by considering that the values in Table III refer to the DUT planes and account for the nonidealities of the measurement setup (e.g., 30-W power amplifier

Fig. 6. Measurements performed by exploiting the proposed large-signal measurement system on a 400-m GaN HEMT device, quiescent condition (V = = 30 V). Time-domain voltage waveform (bold line) and its har4 V; V monic components (fundamental—fine line, second harmonic—dots, and third harmonic—triangles) corresponding to the three load lines reported in Fig. 5. (a) Thick line. (b) Circles. (c) Thin line.

0

TABLE III SYNTHESIZED LOAD TERMINATIONS FOR THE DIFFERENT LOAD LINES SHOWN IN FIG. 5

output impedance, attenuation, and delay provided by the signal paths). By looking at the impedance values in Table III, it is evident how the impedances synthesized for the thin load line are the nearest ones to the ideal class-F amplifier behavior (i.e., a short circuit at the second harmonic and an open circuit at the third harmonic).

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Fig. 7. Measurements performed by exploiting the new large-signal measureV ment system on a 800-m GaN HEMT device, quiescent condition V V (dotted line), V V (continuous thin line), V and V V (continuous thick line). The measured load lines are superimposed to dc V. The crosses in the enlarged view within the inset characteristics at V : V. V; v correspond to the same instantaneous voltage pair v

Fig. 8. Measurements performed by exploiting the new large-signal measureV ment system on a 800-m GaN HEMT device, quiescent condition V and V V (continuous lines), V V (dotted lines). Amplitude of : V. Relative phase between gate and the gate incident signal phasor A . Different load lines are obtained by drain incident signal phasors ' varying the amplitude of the output incident signal phasor. Measurements are V. superimposed to dc characteristics at V

Measurements carried out by adopting the proposed setup, besides representing a valid tool for the design of power amplifiers, may result extremely useful in the identification phase of nonlinear electron device models. As a matter of fact, the operating conditions exploited in the identification phase are privileged in terms of the accuracy that the model can guarantee. As a consequence, nonlinear models extracted by adopting measurements under actual device operations unquestionably offer an higher level of accuracy. The proposed measurement setup can be effectively used for in-depth investigation of the complex mechanisms related to low-frequency dispersion. For example, the low-frequency measurements shown in Fig. 7, carried out on a 0.7 800 m GaN HEMT, highlight the current collapse dependence on the . The crosses in the enaverage value of the gate voltage larged view within the inset correspond to the same values of V V ; if low-frethe instantaneous voltages quency dispersion were not present, the same instantaneous current value (corresponding to the dc one) should be measured. Instead, it is well evident that as the quiescent gate voltage moves into the off state region, the instantaneous drain current goes down. Moreover, also the knee walkout [7], [9] can be simply characterized. In Fig. 8, different measurement sets are reported to characterize such a phenomenon; measurements were carried out with different drain voltage quiescent conditions and setting the amplitude of the input incident signals in order to dyV. It is well evident how the namically reach the value knee region is subject to a shift as the average value of the drain voltage increases. By adopting the proposed characterization technique, more complex device behavior can be investigated, which can be particularly useful for discussing and defining assumptions typically adopted in the framework of nonlinear modeling. To this end, a 0.25- m GaN HEMT device having a periphery of 150 m, biased under class-A operation V V , was considered. In particular, the device was excited with very different waveform shapes, under the constraint of dynamically reaching the 0-V gate voltage

TABLE IV MAGNITUDE AND PHASE OF THE INCIDENT SIGNALS APPLIED TO THE DUT INPUT PORT

05

= 03

= 25

= 04

=0

( =0

=

=54 )

= 25

= 35 =15 1 = 180 =0

= 03

value. The incident signals applied to the DUT input port are shown in terms of their spectral components (Table IV), and corresponding time-domain voltage waveforms [see Fig. 9(a)]. The phase of the incident signals applied at the DUT output port have been set to achieve a 180 displacement with respect to the input signal (such a choice corresponds to a resistive-like load line), whereas the corresponding amplitudes were properly chosen to dynamically hit the device knee region. The corresponding load lines, evidencing the knee walkout, are shown in Fig. 9(b). The crosses in the enlarged view within the inset correspond, for the different load lines, to dynamic points having V: the same value of the instantaneous gate voltage it is evident that these points trace a unique dynamic characteristic. This confirms the empirical results presented in [7] and the theoretical assumption adopted in [18] and [19]: when no important deviations influence the device thermal state (this is true under class A due to the low-efficiency operation involved), the trapping state can be assumed univocally defined by the average values of the voltages applied at the device ports and no dependence is observed on the voltage waveforms. The results provided in this paper could be indirectly obtained also by means of high-frequency time-domain measurement systems [6]–[15]. Nevertheless two reasons make the proposed characterization technique preferable when electron device low-frequency dispersion is dealt with. The first one is that parasitic and reactive effects, under high-frequency operation, tend to hide the response of the intrinsic “algebraic” part of the device (i.e., the resistive core), and the second one is the simplicity and definitely low cost of the proposed measurement technique.

RAFFO et al.: CHARACTERIZATION OF GaN HEMT LOW-FREQUENCY DISPERSION

Fig. 9. Measurements performed on a 150-m GaN HEMT by exploiting the proposed large-signal measurement system, quiescent condition (V = 2 V; V = 25 V). (a) Time-domain voltage waveforms at the device gate port. (b) Measured load lines. Three load lines are shown for the same gate voltage condition (thin, thick, and dotted lines) by varying the amplitude of the output incident signal phasors. Also the dc characteristic for V = 0 V is shown.

0

IV. CONCLUSION In this paper, an extensive characterization of low-frequency dispersion affecting GaN HEMTs has been carried out. In particular, a new multiharmonic measurement system specifically devoted to the investigation and characterization of low-frequency dispersion has been proposed. By exploiting different experimental examples, the unique capabilities of providing useful information for device characterization, modeling, and circuit design have been definitely demonstrated.

REFERENCES [1] J. Rodriguez-Tellez, T. Fernandez, A. Mediavilla, and A. Tazon, “Characterization of thermal and frequency-dispersion effects in GaAs MESFET devices,” IEEE Trans. Microw. Theory Tech., vol. 49, no. 7, pp. 1352–1355, Jul. 2001. [2] A. Raffo, A. Santarelli, P. A. Traverso, M. Pagani, G. Vannini, and F. Filicori, “Accurate modelling of electron device I/V characteristics through a simplified large-signal measurement setup,” Int. J. RF Microw. Comput.-Aided Eng., vol. 15, no. 5, pp. 441–452, Sep. 2005. [3] A. Raffo, F. Scappaviva, and G. Vannini, “A new approach to microwave power amplifier design based on the experimental characterization of the intrinsic electron-device load line,” IEEE Trans. Microw. Theory Tech., vol. 57, no. 7, pp. 1743–1752, Jul. 2009.

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[4] S. C. Cripps, RF Power Amplifiers for Wireless Communication. Norwood, MA: Artech House, 1999. [5] P. Colantonio, F. Giannini, and E. Limiti, High Efficiency RF and Microwave Solid State Power Amplifiers. New York: Wiley, 2009. [6] P. Colantonio, F. Giannini, E. Limiti, and V. Teppati, “An approach to harmonic load– and source–pull measurements for high-efficiency PA design,” IEEE Trans. Microw. Theory Tech., vol. 52, no. 1, pp. 191–198, Jan. 2004. [7] P. McGovern, J. Benedikt, P. J. Tasker, J. Powell, K. P. Hilton, J. L. Glasper, R. S. Balmer, T. Martin, and M. J. Uren, “Analysis of DC–RF dispersion in ALGaN/GaN HFETs using pulsed I–V and time-domain waveform measurements,” in IEEE MTT-S Int. Microw. Symp. Dig., Long Beach, CA, 2005, [CD ROM]. [8] D. Schreurs, K. Van der Zanden, J. Verspecht, W. De Raedt, and B. Nauwelaers, “Real-time measurement of InP HEMTS during large-signal RF overdrive stress,” in Proc. Eur. Gallium Arsenide Relat. III–V Compounds Appl. Symp., Amsterdam, The Netherlands, 1998, pp. 545–550. [9] P. J. Tasker, “Practical waveform engineering,” IEEE Microw. Mag., vol. 10, no. 7, pp. 65–76, Dec. 2009. [10] T. van den Broeck and J. Verspecht, “Calibrated vectorial nonlinear-network analyzers,” in IEEE MTT-S Int. Microw. Symp. Dig., San Diego, CA, 1994, pp. 1069–1072. [11] J. M. Horn, J. Verspecht, D. Gunyan, L. Betts, D.E. Root, and J. Eriksson, “X -parameter measurement and simulation of a GSM handset amplifier,” in Proc. Microw. Integr. Circuit Conf., Amsterdam, The Netherlands, 2008, pp. 135–138. [12] J. Verspecht, D. Gunyan, J. Horn, X. Jianjun, A. Cognata, and D. E. Root, “Multi-tone, multi-port, and dynamic memory enhancements to PHD nonlinear behavioral models from large-signal measurements and simulations,” in IEEE MTT-S Int. Microw. Symp. Dig., Honolulu, HI, 2007, pp. 969–972. [13] F. De Groote, J.-P. Teyssier, J. Verspecht, and J. Faraj, “High power on-wafer capabilities of a time domain load–pull setup,” in IEEE MTT-S Int. Microw. Symp. Dig., Atlanta, GA, 2008, pp. 100–102. [14] D. Vye, “Fundamentally changing nonlinear microwave design,” Microw. J., vol. 53, no. 3, pp. 22–44, Mar. 2010. [15] D. McCarthy and W. Arceneaux, “Greener wireless: Non-linear analysis applied to wireless device characterization,” Microw. J. Apr. 2009 [Online]. Available: http://www.mwjournal.com/Resources/TechLib.asp [16] W. Ciccognani, F. Giannini, E. Limiti, P. E. Longhi, M. A. Nanni, A. Serino, C. Lanzieri, M. Peroni, P. Romanini, V. Camarchia, M. Pirola, and G. Ghione, “GaN device technology: Manufacturing, characterization, modelling and verification,” in Proc. IEEE 14th Microw. Tech. Conf., Prague, Czech Republic, 2008, pp. 1–6. [17] D. Williams, P. Hale, and K. A. Remley, “The sampling oscilloscope as a microwave instrument,” IEEE Microw. Mag., vol. 8, no. 4, pp. 59–68, Aug. 2007. [18] A. Santarelli, F. Filicori, G. Vannini, and P. Rinaldi, “Backgating model including self-heating for low-frequency dispersive effects in III–V FETs,” Electron. Lett., vol. 34, no. 20, pp. 1974–1976, Oct. 1998. [19] A. Raffo, V. Vadalà, D. M. M.-P. Schreurs, G. Crupi, G. Avolio, A. Caddemi, and G. Vannini, “Nonlinear dispersive modeling of electron devices oriented to GaN power amplifier design,” IEEE Trans. Microw. Theory Tech., vol. 58, no. 4, pp. 710–718, Apr. 2010.

Antonio Raffo (S’04–M’07) was born in Taranto, Italy, in 1976. He received the M.S. degree (with honors) in electronic engineering and Ph.D. degree in information engineering from the University of Ferrara, Ferrara, Italy, in 2002 and 2006, respectively. Since 2002, he has been with the Engineering Department, University of Ferrara, where he is currently a Contract Professor of Electronic Instrumentation and Measurement. His research activity is mainly oriented to nonlinear electron device characterization and modeling and circuit-design techniques for nonlinear microwave and millimeter-wave applications. Dr. Raffo is a member of the Italian Association for Electrical and Electronic Measurements and the IEEE MTT-11 Technical Committee.

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Sergio Di Falco (S’08) was born in Licata (AG), Italy, in 1983. He received the M.S. degree in electronic engineering from the University of Ferrara, Ferrara, Italy, in 2008, and is currently working toward the Ph.D. degree at the University of Ferrara. In 2009, he joined the Engineering Department, University of Ferrara. His research activity is mainly oriented to nonlinear characterization and modeling of microwave electron devices and hybrid microwave integrated circuit (HMIC) and monolithic microwave integrated circuit (MMIC) design.

Valeria Vadalà (S’07) was born in Reggio Calabria, Italy, in 1982. She received the M. S. degree (with honors) in electronic engineering from the “Mediterranea” University of Reggio Calabria, Reggio Calabria, Italy, in 2006 and the Ph.D. degree in information engineering from the University of Ferrara, Ferrara, Italy, in 2010. She is currently with the Department of Engineering, University of Ferrara. Her research interests include nonlinear electron–device characterization and modeling for microwave applications.

Giorgio Vannini (S’87–M’92) received the Laurea degree in electronic engineering and Ph.D. degree in electronic and computer science engineering, from the University of Bologna, Bologna, Italy, in 1987 and 1992, respectively. In 1993, he joined the Department of Electronics, University of Bologna, as a Research Associate. From 1994 to 1998, he was with the Research Centre on Electronics, Computer science and Telecommunication Engineering, National Research Council (CSITE), Bologna, Italy, where he was responsible for MMIC testing and the Computer-Aided Design (CAD) Laboratory. In 1998, he joined the University of Ferrara, Farrara, Italy, as an Associate Professor, and since 2005, as a Full Professor of electronics. He is currently Head of the Engineering Department. During his academic career, he has been a Teacher of applied electronics, electronics for communications and industrial electronics. He was a cofounder of the academic spin-off Microwave Electronics for Communications (MEC). He has coauthored over 180 papers devoted to electron device modeling, computer-aided design techniques for MMICs, and nonlinear circuit analysis and design. Dr. Vannini is a member of the Gallium Arsenide Application Symposium (GAAS) Association. He was the recipient of the Best Paper Awards presented at the 25th European Microwave Conference, GAAS98 Conference, and GAAS2001 Conference.

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Accuracy Improvement for Line-Series-Shunt Calibration in Broadband Scattering-Parameter Measurements With Applications of On-Wafer Device Characterization Chien-Chang Huang, Member, IEEE, Yuan-Hong Lin, and Min-Yu Chang-Chien

Abstract—In this paper, error analysis and accuracy improvement for on-wafer line-series-shunt calibration in broadband scattering parameter ( -parameter) measurements are presented with complete modeling of the resistive series/shunt standards, rather than the simple lumped assumptions that were basic requirements in previous studies. The associated parasitic effects in the models are estimated by the first-run results using lumped assumption. They are further updated iteratively, where higher order errors are analytically identified. Additionally, the de-embedded -parameters are transformed for the reference impedance, based on the acquired characteristic impedance, which may differ from the measurement system in broadband operations. The proposed algorithm and calibration data are demonstrated by pseudomorphic high electron-mobility transistors with conductor-back coplanar waveguides built on GaAs substrates with verifications of the thrureflect-line calibration results. Index Terms—Calibration, error analysis, microwave measurement, scattering parameter ( -parameter), transmission lines.

I. INTRODUCTION

B

ROADBAND scattering parameter ( -parameter) calibration is essential for on-wafer device characterization and modeling in microwave/millimeter-wave circuit designs. The commercial impedance standard substrate (ISS) [1], [2] is typically utilized to shift the measured reference plane to the probe tips using line-reflect-match (LRM) or short-open-load-thru (SOLT) calibration methods [3]. The probe pads and the associated interconnects to the device-under-test (DUT) cannot, however, be removed with the probe-tip calibration alone. Additional de-embedding methods, using short/open dummy structures, are proposed to solve the problem; this is based on the ideal characteristics for short/open dummies and lumped component modeling in series/shunt

Manuscript received January 11, 2010; revised February 19, 2010; accepted June 04, 2010. Date of publication August 12, 2010; date of current version September 10, 2010. This work was supported in part by the National Science Council (NSC), Taiwan, under Grant NSC 97-2221-E-155-009 and Grant NSC 98-2221-E-155-010. C.-C. Huang and M.-Y. Chang-Chien are with the Department of Communication Engineering, Yuan Ze University, Taoyuan 320, Taiwan (e-mail: [email protected]). Y.-H. Lin was with the Department of Communication Engineering, Yuan Ze University, Taoyuan 320, Taiwan. He is now with the NeWeb Corporation, Hsinchu 308, Taiwan. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2010.2058570

configurations for probe pads and interconnects [4]–[6]. These assumptions are not easy to achieve for high-frequency operations. The demands for more easy-to-use de-embedding methods with good accuracy still exist for on-wafer device characterization. The traditional thru-reflect-line (TRL) calibration [3] approach is also available for on-wafer device measurements, provided that the calibration standards are built on the same substrate with DUTs. The broadband operation, however, requires two or more lines by using the multiline algorithm [7]. On the other hand, the broadband LRM or SOLT methods need very precise features for their calibration standards, thus making inconvenience for designing the user’s own calibration kit. An alternative calibration approach with easier standard characterization [8] is proposed by using a series resistor that is characterized by the dc resistance and the capacitive parasitic measurements, but an additional series-open test key is required. Recently, a broadband calibration algorithm [9], using a nonzero length transmission line, series resistor, and shunt resistor as standards with characteristics that do not need to be known, should be suitable for applications of on-wafer device characterization. This calibration algorithm is based on two assumptions. First is the same impedance for the transmission line and the measurement system. Second is the lumped feature for the series and the shunt standards. These conditions may be invalid as the operating frequencies from a few gigahertz to millimeter-wave regions. This paper presents the error source analysis and accuracy improvement approaches for line-series-shunt calibration built on the GaAs substrate with device characterization of AlGaAs/InGaAs pseudomorphic high electron-mobility transistors (pHEMTs) from 1 to 50 GHz. The complete - and -model, instead of simple series/shunt lumped components for the series/shunt standards, are then given with the modified self-calibration expressions; the high-order error terms contributed by the parasitic effects can be analytically identified. The parasitic effects can be evaluated as long as the series/shunt resistors follow some simple design rules. In addition, the characteristic impedance of the transmission line is acquired to find the impedance discrepancies between the measurement system and transmission lines. This is because of fabrication variation and frequency dispersion. The final de-embedded data are converted for the reference impedance change based on the acquired characteristic impedance. To demonstrate the accuracy improvements of the proposed method, the measured

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pHEMT data, using the plain line-series-shunt calibration, are shown with additional TRL calibration results for verifications. II. GENERAL FORMULATIONS FOR LINE-SERIES-SHUNT CALIBRATION A. Reference Impedance Change for On-Wafer Measurements At first, the probe tip calibration using the commercial ISS is performed; the measurement system can then be modeled as the DUT embedded two error boxes in the cascading connection re[9]. If the transmission line ferred to the system impedance differs from , the measured cascharacteristic impedance cading matrix of the DUT, referred to as , is expressed as [10] (1) where (2) The error boxes can then absorb the cascading matrices into new ones to take advantage of the simple representations for standards referred to in the transmission line impedance . Obviously, the de-embedded results of the DUT are based on , which may be unknown. The final -parameter should be transformed back to (usually in 50 ) after the characteristic impedance evaluation of the transmission line. B. Nonlumped Features for Series/Shunt Standards

Fig. 1. Schematics and equivalent circuits of: (a) series and (b) shunt calibration standards and their corresponding cascading matrices.

trace

If the lengths of the series/shunt resistors in the line-seriesshunt calibration are not small when compared with the operating wavelength, the lumped assumption will then introduce apparent errors for the corrected -parameters. We modified the circuit models for the series and the shunt resistors using the -parameter and -parameter, respectively, where all transmission line effects can be completely considered. The - and -parameter equivalent circuits can be further reduced to the - and -network for the series/shunt resistors; this is due to their reciprocal property [11]. Fig. 1 shows this with its corresponding cascading matrices given. One can recognize that the and for the series standard and parasitic elements are and for the shunt standard, respectively, when compared with the plain line-series-shunt calibration [9]. The traces of the three cascading matrix manipulations as the determining equations for the calibration parameters are modified as trace

(3b) trace

(3c)

(3a)

The above expressions have been categorized into the calibration terms and various orders of errors to show the nonzero lengths effects of the resistive standards. However, the additional parasitic elements make the self-calibration process in an under-determined solving system in which the seven unknowns should be solved by only three equations in (3). Section II-C shows a simple approach to overcome this problem.

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Fig. 2. Designed structures for: (a) series and (b) shunt calibration standards and their transmission line equivalent circuit models.

C. Parasitic Evaluations If the series resistor is designed at the same width as the signal strip of the transmission line, the nonzero length resistor can be approximated as a lossy transmission line; all the unit-length parameters are the same as the interconnect transmission line, , as shown in Fig. 2(a). except for the larger resistance In addition, the lossy line is represented by an equivalent -network, shown in Fig. 1(a), with the component values as [12]

Fig. 3. Flowchart of on-wafer device characterization using line-series-shunt calibration.

(6b) (4a) (4b) Similarly, the shunt resistor can be approximated as a lossy transmission line with the same unit-length parameters; an excompared with the interconnect transmission ception is line, provided the metal structures are maintained in the same dimensions for the shunt resistor, as shown in Fig. 2(b). The shunt resistor is also equal to a -network, as shown in Fig. 1(b), with the component values as [12] (5a) (5b) Usually the lengths of the series and the shunt resistors are small; the parasitic element values can be expanded as Taylor series for (4b) and (5b) with neglect of the high-order terms as

(6a)

The expressions in (6) can be further simplified into normalized and , readmittance and impedance, as spectively. Thus, the nonzero length effects for the series/shunt standards are easily acquired from the transmission line propagation constant, which is evaluated in the self-calibration procedure. The operation procedures for the on-wafer line-seriesshunt calibration for the device characterization are described in detail in Section III. III. OPERATION PROCEDURES FOR ON-WAFER DEVICE CHARACTERIZATION Fig. 3 shows the operation procedures for on-wafer device characterization using the line-series-shunt calibration. The measured cascading matrices, corrected to the probe-tip using the commercial ISS, are set to the characteristic impedance of the transmission line in the following calibration procedures, as described in Section II-A. The characteristic impedance can be further evaluated after calibration by using the methods described in [13] and [14]. The line-series-shunt self-calibration, using the simple lumped assumption, is run in a first-time trial to find the transmission line propagation constant. The parasitic element

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Fig. 4. Microphotographs of calibration standards and DUT.

values and are estimated based on (6) using the former solved propagation constant. With the known parasitic effects, the modified self-calibration equations are again utilized to solve the three unknowns for more accurate results, where and in (3). Note that the variable convention is the same as the previous studies [9] as and with the same equation numbering as (3). The associated Jacobian, in the iteration process of the self-calibration, is changed for the matrix elements due to the parasitic terms. Details of the expressions are listed in and are calculated accordingly Appendix A. Modified and are then compared with previous results to determine the need for further iterations, as shown in Fig. 3. Once all of the parameters in the calibration standards are determined, the contents of the embedded error boxes can be solved in an overdetermined condition; this is helpful for improving the solution stabilities against measurement uncertainties and noises. Note that the contents of the matrix manipulations become different due to the parasitic terms compared with previous studies [9]. The details are given in Appendix B. The de-embedding process can then be applied to acquire the . The reference DUT -parameters, which are referred to as based on the acimpedance should be converted back to for the final -parameter representation. quired IV. MEASUREMENT RESULTS A. Calibration Parameters The examined calibration standards are fabricated on a GaAs substrate with backside plating for better heat-sinking performances of the active devices. The conductor-backed coplanar waveguide (CPW) is chosen as the transmission line for the test structures to meet the convenient grounding requirements for the shunt standard. To suppress the parallel-modes of conductor-backed CPW, the via-holes are placed along the line for the upper two-sided ground planes [15]. The series and shunt resistors are built by the active layer of GaAs substrates in 20 m of length ( and in Fig. 2), resulting in 55 and 200 in dc resistances, respectively. The DUT is a two-finger AlGaAs/ InGaAs pHEMT device in 0.15- m gate length and 100- m gatewidth. The microphotographs of the calibration kit and the pHEMT DUT are shown in Fig. 4.

Fig. 5. Solved effective dielectric constants for conductor-backed CPW using plain LST (line-series-shunt) calibration, the improved accuracy method, and TRL calibration.

Fig. 6. Solved normalized impedances/admittance for series/shunt standards using plain LST (line-series-shunt) calibration and the improved accuracy method.

Through self-calibration and substantial calculations, the calibration parameters, including the effective dielectric constant and the normalized impedance/admittance in the frequencies from 1 to 50 GHz, are acquired; this is shown in Figs. 5 and 6, respectively. Comparisons of the first-trial results are also shown where the iterations are within three times for the convergent criterion in 0.1% for the successive differences of the parasitic values. One can find that major improvements occur in the phase responses represented in the effective dielectric constant or the imaginary parts of the normalized impedance/ admittance. To verify the solved effective dielectric constant, an independent TRL calibration is performed in the same conductor-backed CPW structure from 6 to 50 GHz with only one transmission line. There is a little difference for frequencies higher than 22 GHz. This discrepancy is due to the ohmic contact between the bulk resistor and metal strip; the ohmic contact would get extra resistance and inductance rather than the uniform lossy transmission line model for the series/shunt resistor. Fortunately, this effect is small compared with the series/shunt impedance, and may be neglected for device characterization applications.

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by the propagation constant obtained from the TRL calibration in the frequency range of 6–50 GHz. Good agreement between the two calibration approaches is achieved, thus validating the proposed theories and the de-embedded results. V. CONCLUSION

Fig. 7. Solved parasitic impedance/admittance for series/shunt standards using the improved accuracy LST (line-series-shunt) calibration method.

Fig. 8. Solved transmission line characteristic impedances for plain LST (lineseries-shunt) calibration and the improved accuracy method.

Fig. 7 shows the solved parasitic impedance and admittance using the developed method; the reactive features of the parasitic effects for the series/shunt standards are obvious. In addition, the characteristic impedance of the conductor-backed CPW, determined by the propagation constant [13], is shown in Fig. 8; the first-trial and improved data are compared where the discrepancies within the entire band are about 1 .

The error analysis and accuracy improvement of the line-series-shunt calibration, with applications for the on-wafer device characterization, are presented in this paper. Various orders of errors, due to the nonzero lengths of the resistive series/shunt standards, are described analytically. With a simple design rule for the series/shunt standards, the error terms can be evaluated iteratively from an ideal calibration operation, while the characteristic impedance is also calculated. The final de-embedded -parameters of the DUT are transformed back to the system impedance based on the acquired characteristic impedance. This step is quite important, as the transmission line characteristic impedance differs from the measurement system impedance. This is because of fabrication variation or frequency dispersion for the transmission lines. The shown measured device is an AlGaAs/InGaAs pHEMT in the conductor-backed CPW test structure, working at the frequency range of 1–50 GHz. To validate the proposed method and the de-embedded data, an independent TRL calibration for the same DUT is done with quite close results. The shown method, and the associated measured data, can be applied to device characterization and modeling for microwave/millimeter-wave integrated-circuit designs.

APPENDIX A DETAIL EXPRESSIONS OF JACOBIAN IN SELF-CALIBRATION PROCESS The matrix elements of the Jacobian for (3) in the Newton–Raphson iteration are listed as follows: (A.1)

(A.2)

B. Measurements of pHEMT Devices The final de-embedded -parameters for the measured pHEMT in the bias condition of 3.0 V in and 75 mA in the drain current are shown in Fig. 9 in which the uncorrected data (but calibrated to the probe tips), plain line-series-shunt calibration results referred to , and the improved accuracy results referred to , are listed simultaneously. Again, the phase differences between the plain and improved line-series-shunt calibrations are clearer than the magnitude responses; this is due to the parasitic effects for nonzero lengths of the series/shunt standards. On the other hand, the influences of the reference impedance changes show different magnitude responses for the forward transmission coefficients. This is especially true for the low-frequency bands in this study case. To further verify these measured data, the TRL calibration is performed again for the same pHEMT DUT with the reference impedance transformation based on the characteristic impedance evaluated

(A.3)

(A.4)

(A.5)

(A.6)

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Fig. 9. Measured: (a) input reflection, (b) forward transmission, (c) reverse transmission, and (d) output reflection for pHEMT device in the bias condition of 3.0 V in V and 75 mA in drain current with uncorrected, plain LST (line-series-shunt) calibration, improved accuracy version, and TRL calibration results.

(B.1b)

(A.7) Note, the parasitic effects are recognized as the expressions enclosed by the braces following the original terms in the plain line-series-shunt self-calibration.

APPENDIX B ERROR BOX EVALUATIONS Since the parasitic effects are included for the series/shunt standards, the cascading matrices become the following expressions after the simplification described in Section II-C:

(B.1a)

Recall the error box evaluation procedures in [9], the matrix manipulations for the three calibration standards, namely, and , are utilized to find the contents of error box . The other matrix combinations and are used for error box . These matrices can then be explicitly derived, based on (B.1), and the error box contents are solved in the same operations described in [9]. ACKNOWLEDGMENT The authors would like to thank the National Chip Implementation Center (CIC), Hsinchu, Taiwan, for arranging the schedule of Win Semiconductors in the pHEMT process. The authos would also like to thank Dr. D.-M. Lin, National Central University, Jhongli City, Taiwan, for performing the measurements.

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REFERENCES

[1] Impedance Standard Substrate. Cascade Microtech, Inc., Beaverton, OR, 2010. [Online]. Available: http://www.cmicro.com/products/calibration-tools [2] Impedance Standard Substrate. GGB Industries Inc., Naples, FL, 2010. [Online]. Available: http://www.ggb.com/calsel.html [3] S. A. Wartenberg, RF Measurements of Die and Packages. Boston, MA: Artech House, 2002, pp. 33–43. [4] L. F. Tiemeijer and R. J. Havens, “A calibrated lumped-element de-embedding technique for on-wafer RF characterization of high-quality inductors and high-speed transistors,” IEEE Trans. Electron Devices, vol. 50, no. 3, pp. 822–829, Mar. 2003. [5] Y. Tretiakov, J. Rascoe, K. Vaed, W. Woods, S. Venkatadri, and T. Zwick, “A new on-wafer de-embedding technique for on-chip RF transmission line interconnect characterization,” in Proc. 63rd ARFTG Conf., Jun. 2004, pp. 69–72. [6] T. Zwick, Y. Tretiakov, and D. Goren, “On-chip SiGe transmission line measurements and model verification up to 110 GHz,” IEEE Microw. Wireless Compon. Lett., vol. 15, no. 2, pp. 65–67, Feb. 2005. [7] R. B. Marks, “A multiline method of network analyzer calibration,” IEEE Trans. Microw. Theory Tech., vol. 39, no. 7, pp. 1205–1215, Jul. 1991. [8] D. F. Williams and D. K. Walker, “Series-resistor calibration,” in Proc. 50th ARFTG Conf., Dec. 1997, pp. 131–137. [9] C.-C. Huang and H.-C. Lin, “A novel calibration algorithm with unknown line-series-shunt standards for broadband S -parameter measurements,” IEEE Trans. Instrum. Meas., vol. 57, no. 5, pp. 891–896, May 2008. [10] R. B. Marks and D. F. Williams, “A general waveguide circuit theory,” J. Res. Nat. Inst. Standard Technol., vol. 97, pp. 533–562, Sep.–Oct. 1992. [11] C. A. Desoer and E. S. Kuh, Basic Circuit Theory. New York: McGraw-Hill, 1969, pp. 735–741. [12] T. C. Edward and M. B. Steer, Foundations of Interconnect and Microstrip Design, 3rd ed. New York: Wiley, 2000, pp. 438–439. [13] R. B. Marks and D. F. Williams, “Characteristic impedance determination using propagation constant measurement,” IEEE Microw. Guided Wave Lett., vol. 1, no. 6, pp. 141–143, Jun. 1991. [14] D. F. Williams, U. Arz, and H. Grabinski, “Characteristic-impedance measurement error on lossy substrate,” IEEE Microw. Wireless Compon. Lett., vol. 7, no. 7, pp. 299–301, Jul. 2001.

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[15] W. H. Haydl, “On the use of conductor-backed coplanar circuits,” IEEE Trans. Microw. Theory Tech., vol. 50, no. 6, pp. 1571–1577, Jun. 2002. Chien-Chang Huang (S’92–M’95) received the M.S. and Ph.D. degrees in electrical engineering from National Taiwan University, Taipei, Taiwan, in 1990 and 1994, respectively. From 1994 to 1996, he was an Associate Researcher with the Transmission Laboratory, Telecommunication Laboratories, Taoyuan, Taiwan, where he developed RF circuits and subsystems for personal communications systems. He is currently with the Department of Communication Engineering, Yuan Ze University, Taoyuan, Taiwan. His research interests include microwave device characterization and modeling, computer-aided analysis of RF/microwave circuits, and wireless communications.

Yuan-Hong Lin received the B.S. degree in electrical engineering from National Taiwan Ocean University, Keelung, Taiwan, in 2006, and the M.S. degree in communication engineering from Yuan Ze University, Taoyuan, Taiwan, in 2008. He is currently with the Wistron NeWeb Corporation, Hsinchu, Taiwan. His research interests include miniaturized antenna designs and microwave measurements.

Min-Yu Chang-Chien received the B.S. degree in electronic engineering from Chung Yuan Christian University, Taoyuan, Taiwan, in 2007, and the M.S. degree in communication engineering from Yuan Ze University, Taoyuan, Taiwan, in 2009. His research interests are microwave measurements and calibration techniques.

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Ultra-Wideband Chip Attenuator for Precise Noise Measurements at Cryogenic Temperatures Juan Luis Cano, Niklas Wadefalk, and Juan Daniel Gallego-Puyol, Member, IEEE

Abstract—A 20-dB chip attenuator designed for cryogenic noise measurements from dc up to 40 GHz is presented. The chip is based on the use of temperature-stable tantalum–nitride thin-film resistors, a high thermal conductivity substrate such as crystal quartz (z-cut), and a suitable design that avoids inner conductor thermal heating, which is an important limiting factor for the precision of cryogenic noise measurements. A high-accuracy temperature sensor installed inside the attenuator module provides precise temperature characterization close to the chip location. The high thermal conductivity of the chip substrate in the designed attenuator assures a negligible temperature gradient between the resistive elements in the chip and the sensor, thus improving the measurement accuracy. The attenuator also shows an excellent electrical performance with insertion losses of 19.9 dB 0.65 dB and return losses better than 20.6 dB in the whole frequency range at 296 K. The insertion loss change when cooled to 15 K is less than 0.25 dB, which demonstrates its temperature stability. Index Terms—Attenuators, cold-attenuator technique, cryogenics, noise measurement, Y-factor method.

I. INTRODUCTION

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OISE measurement of low-noise devices or systems at cryogenic temperature presents a challenge for microwave engineers due to the low measured values and the required uncertainty. These low noise values are more conveat niently expressed as effective input noise temperature cryogenic temperatures rather than the noise factor (or noise K for figure), commonly used at room temperature characterizing noise properties of the device-under-test (DUT). for low-noise systems at cryogenic Common values of temperature are below 20 K. Some techniques have been proposed and used for meain cooled systems. Among them, the cold-attenuator suring technique gives a good compromise between precision and test speed [1]–[3] in opposition to other accurate, but slow or narrowband techniques [4]. In this technique, a noise diode is used as a noise source outside the cryostat and an attenuator is placed and cooled in front of the DUT, inside the cryostat,

Manuscript received March 24, 2010; revised June 08, 2010; accepted June 09, 2010. Date of publication August 05, 2010; date of current version September 10, 2010. This work was supported in part by the Ministerio de Educación y Ciencia, Spain, under FPI Grant BES-2005-6730. J. L. Cano is with the Departamento de Ingeniería de Comunicaciones, Laboratorios I D Telecomunicaciones, Universidad de Cantabria, Santander 39005, Spain (e-mail: [email protected]). N. Wadefalk is with the Department of Microtechnology and Nanoscience (MC2), Chalmers University of Technology, Göteborg 41265, Sweden (e-mail: [email protected]). J. D. Gallego-Puyol is with the Centro Astronómico de Yebes, Observatorio Astronómico Nacional, Yebes 19141, Spain (e-mail: [email protected]). Digital Object Identifier 10.1109/TMTT.2010.2058276

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Fig. 1. Noise measurement setup of cooled systems with the cold-attenuator technique.

providing adequate levels of noise powers at the DUT input for applying the Y-factor method. Fig. 1 shows a simplified sketch of this measurement setup. The advantages of this technique are the absence of mechanical switches, enabling fast broadband measurements, negligible effect of the noise source output reflection coefficient variation when changing from one state to the other, and reduction of the error produced by the insertion loss variations of the coaxial input line when cooled. In order to take precise measurements using the cold-attenuator technique, the physical temperature of the attenuator must be precisely known. Moreover, in most cases, the uncertainty in the temperature of the sensor calibration is the greatest error source in the measurement [2], [3], [5]. For thermal characterization, a temperature sensor is attached to the attenuator body. A problem arises when using coaxial attenuators since the temperature of the inner conductor, where the resistive elements are placed, cannot be directly measured. This is relevant since the temperature of these resistive elements is often raised due to the heat transferred through the inner conductor of the coaxial cable connected to the ambient port of the cryostat. If the sensor reading is used directly for the calculations, will be overestimated by approximately the same amount as the error in physical temperature, i.e. 1-K error in physical temperature gives 1-K error in . In order to overcome this problem, one option is to correct the reading of the physical temperature with an offset determined from a calibration performed by noise measurements of a known device. Another alternative is to insert an additional element in the input line to provide some thermal isolation of the coaxial line inner conductor. In the first case, the error in the measurement would have a magnitude close to the accuracy of the calibration performed; while in the second case, the additional element introduces more uncertainty in the measurement of the insertion loss of the input line, increases the ripple of the transmission, and deteriorates the reflection. A possibility to build an attenuator not heated through the coaxial inner conductor is using a lossy magnetic dielectric, such as in the filter described in [6]. However, this yields an attenuation strongly dependant on the frequency, making it usable only in a relatively narrow band. The approach presented

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in this work is to use an attenuator with a much better cryogenic thermal link to its body to avoid the drawbacks of the previous approaches. This improved thermal link is accomplished through the use of a high thermal-conductivity substrate and high thermal-stability thin-film resistors in the attenuator chip design, thus avoiding the resistors heating through the inner conductor. The 20-dB insertion loss chip designed in this work is assembled in a module designed to operate from dc to 40 GHz, which is equipped with a high-precision temperature sensor that provides temperature measurement close to the chip location. The high thermal conductivity of the substrate and the module material used in the attenuator design minimizes the temperature gradient between the attenuator chip and the temperature sensor, and therefore, the noise measurement precision is improved.

where is the ratio between noise powers measured in the noise figure meter with the noise source in the ON and OFF states ( and , respectively). To obtain the optimum insertion loss unfor the attenuator, it is needed to calculate the minimum certainty due to the uncertainty in , produced by the fluctuations in noise power measurements. Equation (2) gives the stan, in terms of standard deviation of , dard deviation of ,

(2) For this simple approach, it can be considered that is a and , function of two uncorrelated random variables, can be calculated from (3) as follows: and therefore, (3)

II. CHIP DESIGN AND MEASUREMENT A. Study of the Optimum Attenuation Value One of the advantages of the cold-attenuator technique is that the attenuator provides a cold noise temperature reference (close to the noise temperature of the DUT) when the noise diode is in the OFF state. There are many factors that influence the accuracy of the noise measurement with the cold-attenuator technique, but in many cases, the error in the value of the cold reference becomes dominant [5]. A high value of the insertion loss in the attenuator will help in providing a well-defined cold reference; however, this value should be kept within adequate limits in order to improve the noise measurement accuracy. It is clear that small attenuation values should not be used in order to avoid the influence of the noise source output reflection coefficient variation in the measurement. Moreover, small attenuation values increase the effects of the input coaxial line on the entire input path. Input coaxial lines for cryogenic applications are generally made of stainless steel, which has low thermal conductivity and high electrical losses. If the attenuator insertion losses are not large enough compared to input line attenuation, then the total input path insertion loss cannot be considered to be concentrated in the attenuator, and therefore, the temperature distribution along this input path should be known in order to make precise calculations of its noise contribution. On the other hand, large attenuation values produce small differences between the hot and cold temperatures ( and , respectively) at the DUT input. The random nature of noise signals produce fluctuations in the power measured by the noise figure meter. These small fluctuations may generate a large measurement error when calculating the Y-factor if the differences between hot and cold temperatures are small [7]. Therefore, there should be an optimum value of the attenuator insertion loss, which may be dependent on the measurement setup. In the following calculation, a simple setup is considered where only the fluctuations in received noise powers, due to limited receiver bandwidth and integration time, are taken into account. The effective input noise temperature of a DUT using the cold-attenuator technique can be calculated applying (1) (1)

Fluctuations in the measured powers are dependent on the noise figure meter bandwidth, , and integration time, , stated in (4) as follows: (4) where is the Boltzmann’s constant and is the DUT transducer gain. Introducing (3) and (4) into (2), the standard deviais obtained as a function of and (5), which are tion of dependent on the attenuator insertion loss (6) [8] (5) (6) and are noise temperatures at the noise source output in the ON and OFF states [7]. is the physical temperature of the lossy elements in the input path (including attenuis the insertion loss of this input path. As stated ator), while above, attenuation of the input coaxial line should be negligible regarding the attenuator insertion loss in order to reduce the uncertainty in the input path temperature profile. Combining (5) and (6), the optimum value for the attenuator insertion loss, for a given setup, can be obtained. In Fig. 2, is plotted as a function of total path attenuation for the following MHz, s, K, K, and setup: K. The excess noise ratio (ENR) of noise sources changes with frequency. In the broadband noise source available in our laboratory, Agilent Technologies Inc.1 model 346CK01, the ENR ranges from almost 20 dB at 1 GHz to less than 12 dB at 40 GHz. According to Fig. 2, the optimum attenuation value is related to the ENR of the noise source. Therefore, the best results should be found with a 15-dB attenuator at high frequencies and a 20-dB attenuator at low frequencies. Two versions of the chip attenuator were designed, one with 15-dB insertion loss and the other one with 20-dB insertion loss. 1Agilent

Technologies Inc., Santa Clara, CA.

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Fig. 4. Layout of the chip attenuator. Resistors are 20% larger and via-holes are independent for laser trimming. Coplanar-to-microstrip transitions designed for testing in a probe station. Dimensions are 9 2 mm .

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1T

Fig. 2. (coverage factor of 3) versus total input path insertion loss for two different values of source ENR: ENR = 20 dB (solid line) and ENR = 12 dB (dashed line).

Fig. 3. T-network basic cell.

This paper only presents the design process and results of the 20-dB attenuator unit for clarity. B. 20-dB Attenuator Chip Design The 20-dB insertion loss is accomplished by cascading four basic T-network [9], [10] cells of 5-dB attenuation each. Therefore, the electrical design process is simplified to the design of one basic cell. If only one cell is implemented to achieve the 20-dB insertion loss, then the parasitic capacitance to ground of the large series resistors would reduce the chip bandwidth. Fig. 3 shows the schematic of this cell with the resistive elements forming a T-network. The shunt element in this configuration is divided into two parallel resistors to maintain symmetry in the structure and to reduce the inductance to ground. and can be found applying (7) and Values for resistors (8) [9], [10] (7)

needed. The attenuator was designed using American Technical Ceramics (ATC)2 thin-film technology. Crystal quartz (z-cut, and mil) was selected as the substrate since it has a high thermal conductivity of 1000 W m K at 10 K [11]. For comparison, Teflon has a thermal conductivity of 0.1 W m K at 10 K [12] and alumina has a thermal conductivity of 7 W m K at 10 K [11], [13]. For the resistors, a nickel–chromium (NiCr) thin film would have been preferred due to its low-resistivity variation with temperature, but only tantalum–nitride (TaN) resistors were available for the ATC process with this substrate. However, TaN resistors also show a low temperature coefficient of resistance K to 100 10 K in the 248–398-K (TCR) from 50 10 K for NiCr resistors), temperature range (from 0 to 50 10 which make them suitable for large temperature gradients. In order to check the low TCR of TaN resistors at cryogenic temperatures, some dc measurements were carried out once the attenuator was finished. These results are presented in Section IV. Electrical performance of the attenuator depends on the resistors accuracy; therefore, resistors were designed with 20% resistance values for laser trimming, with 1% tolerance, during chip processing. Individual via-holes enable the trimming of each resistor individually before via-holes thru plating. Two versions of the attenuator were designed, one with microstrip ports, for mounting in the attenuator module, and another with coplanar-to-microstrip transitions to perform roomtemperature chip tests in a coplanar probe station. The layout of the latter is shown in Fig. 4. The attenuator was designed using AWR Corporation’s3 Microwave Office both for schematic optimization and electromagnetic verification. Electromagnetic simulation results of the chip with full-length microstrip accesses and without coplanar-tomicrostrip transitions are shown in Figs. 5 and 6, together with on-wafer measurement results at room temperature. On-wafer chip measurements show an insertion loss of 19.55 dB 0.75 dB in the dc to 40-GHz range with a return loss better than 25 dB. These measurements also demonstrate that this chip can be used at higher frequencies if needed, designing a suitable assembly.

(8) where is the characteristic impedance (50 ) and is the desired insertion loss (linear). For 5-dB attenuation, and . One of the key aspects in the chip design is the substrate selection. To minimize the temperature difference between the resistive elements in the chip and attenuator body, a substrate with high thermal conductivity at cryogenic temperatures is

III. ATTENUATOR MODULE ASSEMBLY The attenuator is intended to be used up to 40 GHz, therefore, the module is designed accordingly. The module has been machined in brass (thermal conductivity of 10 W m K at 10 K [13]) using a numerically controlled milling machine and then 2American Technical Ceramics (ATC) Thin Film Technologies, Jacksonville, FL. 3AWR

Corporation, El Segundo, CA.

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Fig. 5. Simulated (dashed line) and measured (solid line) reflection of the chip at room temperature. Measurement includes coplanar-to-microstrip transitions, which are not taken into account in simulation.

thermal conductivity of brass, gold, and crystal quartz, make the temperature gradient negligible between them, minimizing the uncertainty in the determination of the attenuator temperature. Sensor terminals are directly soldered to a hermetic dc header to provide current bias and voltage measurement. The attenuator chip is attached to the module using Indalloy2905 (97% In, 3% Ag) paste, which produces a soft joint between parts and avoids cracks during thermal cycles. Due to its high indium content, Indalloy290 takes advantage of indium ductility [14] and high thermal conductance [15] at cryogenic temperatures. Moreover, indium-based solders produce less scavenging damage than tin-based solders for use on gold films; therefore, the formation of brittle intermetallic layers is minimized. The module is fitted with K-connectors (2.92 mm). The low temperatures produce the contraction of the materials. Since the coefficients of thermal expansion (CTEs) are different for the different parts, cracks may be produced in the joints; therefore, sliding contacts are installed in the glass bead pins of the connectors. These sliding contacts are soldered to the microstrip lines with tin-lead solder, but they are free to move along glass bead pins minimizing problems produced by thermal stress. Finally, two holes are drilled on one side in order to thermally anchor the module to the cold plate in the cryostat. IV. ATTENUATOR MODULE CHARACTERIZATION

Fig. 6. Simulated (dashed line) and measured (solid line) transmission of the chip at room temperature. Measurement includes coplanar-to-microstrip transitions, which are not taken into account in simulation.

Fig. 7. Attenuator module with cover removed. Dimensions are 20.5 7.7 mm , excluding connectors.

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nickel and gold plated to avoid oxidation and to provide a solderable surface. A LakeShore Cryotronics Inc.4 temperature sensor model DT-670 with an uncertainty of 0.25 K has been soldered close to the chip location, as shown in Fig. 7. The proximity between the sensor and attenuator chip, and especially the high 4Lake

Shore Cryotronics Inc., Westerville, OH.

Attenuator characterization was carried out at room temperature, while additional measurements at cryogenic temperature were taken in order to obtain performance variations upon cooling. At room temperature, measurements have been made using PNA E8364C from Agilent Technologies together with short, open, load, and thru (SOLT) standards calibration. Results obtained with these measurements are shown via solid lines in Figs. 8 and 9. These results show return losses better than 20.6 dB (voltage standing-wave ratio (VSWR) of 1.20) and 0.65 dB in the dc–40-GHz insertion losses of 19.9 dB frequency range. At cryogenic temperature, the measurement of accurate -parameters is difficult due to direct inaccessibility to DUT ports, which complicates an appropriate system calibration. Cryogenic measurements have been carried out using the existing setup at the Centro Astronómico de Yebes, Guadalajara, Spain. For the cryogenic -parameters measurement, the reference plane is set inside the cryostat at the point of the connection of the DUT. The calibration is performed at room temperature using an Agilent Technologies’ electronic calibration kit (ECAL) connected at the same position as the DUT. After that, cryogenic measurements of two short and one thru standards are taken in different cool-downs and used to make the small corrections needed in the previous calibration for accurate cryogenic measurements. Moreover, time domain gating is used to eliminate the small variations in reflection produced in the input and output cryostat transitions when cooled. This measurement is limited to 20 GHz due to the limited bandwidth of electromechanic switches installed in the existing setup. Cryogenic reflection results, shown in Fig. 8 by a dashed line, are further limited to 18 GHz to avoid 5Indium

Corporation of America, Utica, NY.

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Fig. 8. Measured reflection of attenuator module at room temperature (solid line) and at cryogenic temperature (T = 15 K) up to 18 GHz (dashed line).

Fig. 10. Measured transmission of the attenuator module at room temperature (solid line) and modeled transmission at cryogenic temperature (T = 15 K) (dashed line). The modeled values are obtained applying the correction factor given by (9) to the room-temperature measurement. For comparison, HFSS simulation results of the chip attenuator insertion losses are plotted at room temperature (solid line with circles) and at cryogenic temperature (dashed line with triangles). The electrical conductivity of gold at cryogenic temperatures was increased an order of magnitude from its room-temperature value [16]

a solid line in Fig. 10, obtaining a model of the insertion loss at 15 K plotted with a dashed line in Fig. 10 Fig. 9. Setups for the characterization of the: (a) input lines and (b) attenuator both at room and cryogenic temperatures. The auxiliary line is the same for both setups and it is characterized previously at both temperatures.

nonconsistent results produced at band edges by the time-domain gating. These results show small reflection variation upon cooling in the measured range, which is expected to be maintained up to 40 GHz. The attenuation at cryogenic temperature should be characterized up to 40 GHz since its value is a key factor for obtaining meaningful noise measurements with the cold-attenuator technique. As the previously described system did not allow measurements over 18 GHz, another strategy was chosen. A different cryostat with K-connectors (2.92 mm) and stainless-steel transitions was used. First, the input and output coaxial lines in the cryostat were measured in a back-to-back configuration both at room and cryogenic temperatures, as shown in Fig. 9(a). From these measurements, the change in the coaxial lines insertion losses was measured and modeled as a function of frequency. The attenuator was then inserted between the coaxial lines and the overall insertion loss of all elements was measured both at room and cryogenic temperatures [see Fig. 9(b)]. Finally, the effect of the coaxial lines was subtracted and the insertion loss of the attenuator was obtained at both temperatures. These results were used to model the variation of the attenuation with temperature since the measurements inside of the cryostat are affected by ripples produced by reflections in the input lines. From the previous results, it was determined that a simple correction factor of the form given by (9) could be used to model the reduction of loss experienced when cooling either the input lines or the attenuator. This correction factor is applied to the room-temperature attenuation measurement, taken outside of the cryostat using SOLT calibration, and depicted with

(9) where is the frequency in gigahertz, is 0.0083 for the stainless-steel coaxial lines of the available setup and 0.0019 for the attenuator, is 1.472 for the coaxial lines and 1 for the attenuator, and is 1 for both the coaxial lines and attenuator. From the extracted model of attenuation change, an increasing reduction of the attenuator insertion loss with frequency is clearly seen. This effect is explained with the improvement of electrical conductivity of gold in the microstrip lines and connectors upon cooling. In order to prove this assumption, an electromagnetic simulation of the attenuator chip, excluding connectors, was performed in HFSS6 varying the electrical conductivity of gold and the simulation results, presented in Fig. 10, were found to be similar to the measured results. The value of the electrical conductivity of gold at cryogenic temperatures was increased by an order of magnitude from its room-temperature value [16]. Finally, the thermal stability of TaN resistors has been investigated with dc measurements. The dc resistance at one port of the attenuator with the other port open was carefully measured correcting for the change of resistance of the connecting cables when cooling. This measurement has shown an increase of dc K, resistivity in the chip of 2% at 15 K, i.e., a TCR of 70 10 practically constant in the 15–290-K temperature range, which confirms the good thermal stability of TaN resistors at cryogenic temperature. This small variation has a very small effect in the change of the attenuator losses and matching. The simulation of the attenuator with this small dc resistivity increment shows a negligible change of the insertion loss (below 0.03 dB) and a variation of the return loss of less than 2 dB at the worst matched 6Ansoft

LLC. Pittsburgh, PA.

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Fig. 11 shows similar results for the setups that minimize the inner conductor heating. The same sensor (LakeShore model DT-470), attached to the attenuators body, was used in all the measurements in order to eliminate its influence in noise results due to different calibrations. The small differences between the setups with heat-block and with the designed attenuator shown in Fig. 11 demonstrate that this new design does not suffer from appreciable heating through the input lines. On the other hand, in the classical setup with coaxial attenuators and without any heat-block, the error in the noise measurement is noticeable with an excess of measured noise of 3.1 K, as is demonstrated in Fig. 11. B. Uncertainty Calculation Fig. 11. Noise temperature measurement of the ALMA prototype LNA at cryogenic temperature. Measurement result with commercial attenuators 6 dB) plus a homemade heat-block is shown in solid line while the (10 measurement result with the new attenuator is plotted via a dashed line. The measurement result with commercial coaxial attenuators and without the heat-block is plotted via circles. (Ripples are inherent to the amplifier.)

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frequency point. The dominant effect in the observed variation of the attenuation is the change of the connecting microstrip lines. V. NOISE MEASUREMENT UNCERTAINTY A. Low-Noise Amplifier (LNA) Noise Measurement To demonstrate the performance of the designed attenuator, a well-known LNA is measured both with the new attenuator and with the classical noise setup available at the Centro Astronómico de Yebes, taking into account the loss variation extracted in Section IV. The selected DUT is a prototype of the cryogenic IF LNAs (4–12 GHz) designed at Centro Astronómico de Yebes for band 9 of the ALMA project [17]. The classical noise setup uses cascaded 6- and 10-dB commercial coaxial attenuators up to 40 GHz. In these attenuators, the outer conductor, where the temperature sensor is attached, is directly connected to the cold plate and it is probably colder than the inner conductor, which is heated through the coaxial lines. At the Centro Astronómico de Yebes, this problem is reduced using a homemade heat-block before the first coaxial attenuator. This heat-block is comprised of a series of two K-female sparkplug launcher transitions interconnected by a glass bead so the contact makes a relatively high thermal resistance connection at cryogenic temperature. The noise measurement result7 obtained with this classical setup is plotted via the solid line in Fig. 11. For the measurement with the new attenuator, both the coaxial attenuators and the heat-block are replaced by the new attenuator module. The result of this new measurement is shown via a dashed line in Fig. 11. In order to demonstrate the increase of noise measurement error produced by the inner conductor heating, the amplifier is measured with the commercial coaxial attenuators and without the heat-block. The result of this latter measurement is plotted via circles in Fig. 11. 7Note that ripples in the noise plot are inherent to the amplifier, which is a prototype designed to test the effect of a long input matching line.

To complement the results given in Section V-A, an uncertainty calculation of the noise measurement is carried out. This calculation is based on Monte Carlo analysis [5] to take into account uncertainties not considered in Section II-A. In Section II-A, only the radiometric noise produced by finite bandwidth and integration time of the receiver was taken into account. As well as this, uncertainties in the noise source ENR, physical temperatures, and nonzero reflection coefficients are considered here. Differences between transducer and insertion gains and the effect of noise parameters are also included. Finally, receiver variations from calibration to measurement and receiver nonlinearity are taken into account in this calculation. From this analysis, the total uncertainty is 1.7 K considering sensor DT-470 (uncertainty 1 K). This total uncertainty can be lowered to 1.3 K if the temperature value from sensor DT-670 (uncertainty 0.25 K) is used. This total uncertainty is defined with a coverage factor of 2, which means a 95.45% confidence [18]. VI. CONCLUSIONS The design of a 20-dB ultra-wideband chip attenuator to be used for noise measurements at cryogenic temperatures has been presented. The attenuator design, based on the classic T-network configuration, is optimized for operation in a cryogenic environment through the use of temperature-stable TaN resistors and a high thermal conductivity crystal quartz substrate. The designed chip has an insertion loss of 19.55 dB 0.75 dB in the dc to 40-GHz range with a return loss better than 25 dB VSWR at room temperature. The use of this chip can be extended up to 60 GHz with good results. The module where the chip is assembled includes a high-accuracy temperature sensor (uncertainty 0.25 K), which provides precise temperature readings close to the chip location. Room-temperature results of the attenuator module with connectors show a return loss better than 20.6 dB (VSWR 0.65 dB in the of 1.20) and insertion losses of 19.9 dB dc to 40-GHz frequency range. At cryogenic temperature K , the reduction in the insertion loss is 0.25 dB maximum, which is produced by the increased electrical conductivity of gold upon cooling. The thermal stability of TaN resistors has been demonstrated through dc measurements K. showing a TCR of 70 10 The high thermal conductivity of the substrate (1000 W m K at 10 K) enables effective cooling of the

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resistive elements in the attenuator chip, and therefore, negligible temperature gradient between them and the temperature sensor. Noise results obtained with this new attenuator are similar to those measured with a cascaded heat-block and coaxial attenuator, which demonstrates the effective cooling of the attenuator chip, avoiding thermal heating of its resistive elements through input lines. The attenuator presented provides an improvement in terms of cryogenic noise measurement accuracy compared to classical setups without any heat-block. Moreover, it also simplifies the measurement setup avoiding the need of a heat-block for precise noise measurements. The elimination of this component in the input line reduces the uncertainty in the input line insertion-loss characterization, as well as improving the level of ripples in the gain and return loss. ACKNOWLEDGMENT The authors would like to thank C. Díez and I. López-Fernández, both with the Centro Astronómico de Yebes, Guadalajara, Spain, for their advice, fruitful discussions, and assistance with the attenuator module test campaign. REFERENCES [1] J. E. Fernandez, “A noise-temperature measurement system using a cryogenic attenuator,” Jet Propulsion Lab. (JPL), Pasadena, CA, TMO Progress Rep. 42-135, Nov. 1998. [2] J. D. Gallego and I. López, “Definition of measurements of performance of band cryogenic amplifiers Centro Astronóm. Yebes, Observatorio Astronóm. Nac.,, Yebes, Spain, Tech. Rep. C.A.Y. 2000-4, Jul. 2000. [3] N. Wadefalk et al., “Cryogenic wide-band ultra-low-noise IF amplifiers operating at ultra-low DC power,” IEEE Trans. Microw. Theory Tech., vol. 51, no. 6, pp. 1705–1711, Jun. 2003. [4] P. R. Jordan, “A novel microwave noise temperature generator having an output temperature of from below 40 to above 370 K,” Rev. Sci. Instrum., vol. 41, no. 11, pp. 1649–1651, Nov. 1970. [5] J. D. Gallego and M. W. Pospieszalski, “Accuracy of noise temperature measurement of cryogenic amplifiers,” NRAO, Charlottesville, VA, Electron. Div. Internal Rep. 285, 1990. [6] D. H. Slichter, O. Naaman, and I. Siddiqui, “Millikelvin thermal and electrical performance of lossy transmission line filters,” Appl. Phys. Lett., vol. 94, no. 19, pp. 192508–192508-3, 2009. [7] “Fundamentals of RF and microwave noise figure measurements,” Agilent Technol., Santa Clara, CA, Appl. Note 57-1, 2006. [8] C. T. Stelzried, “Microwave thermal noise standards,” IEEE Trans. Microw. Theory Tech., vol. MTT-16, no. 9, pp. 646–655, Sep. 1968. [9] R. E. Collin, Foundations for Microwave Engineering, 2nd ed. New York: McGraw-Hill, 1992, pp. 400–401. [10] Y. Sun, L. Li, H. Lin, Z. Yu, M. Huang, and L. Wan, “Attenuators using thin film resistors for RF applications,” in Int. Electron. Packag. Technol. High Density Packag. Conf., Shangai, China, Jul. 2008, pp. 1–3.

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[11] N. J. Simon, “Cryogenic properties of inorganic insulation materials for ITER magnets; A review,” NIST, Boulder, CO, NISTIR 5030, Dec. 1994. [12] E. D. Marquardt, J. P. Le, and R. Radebaugh, “Cryogenic material properties database,” in 11th Int. Cryocooler Conf., Keystone, CO, Jun. 20–22, 2000. [Online]. Available: http://cryogenics.nist.gov/Publications/publications.htm [13] “Temperature Measurement and Control Catalog” Lake Shore Cryotron. Inc., Westerville, OH, 2004. [Online]. Available: www.lakeshore.com [14] M. Plötner, B. Donat, and A. Benke, “Deformation properties of indium-based solders at 294 and 77 K,” Cryogenics, vol. 31, pp. 159–162, Mar. 1991. [15] R. Radebaugh, “Thermal conductance of indium solder joints at low temperatures,” Rev. Sci. Instrum., vol. 48, no. 1, pp. 93–94, Jan. 1977. [16] R. A. Matula, “Electrical resistivity of copper, gold, palladium and silver,” J. Phys. Chem. Ref. Data, vol. 8, no. 4, pp. 1147–1298, 1979. [17] I. López-Fernández, J. D. Gallego, C. Diez, and A. Barcia, “Development of cryogenic IF low-noise 4–12 GHz amplifiers for ALMA radio astronomy receivers,” in IEEE MTT-S Int. Microw. Symp. Dig., San Francisco, CA, 2006, pp. 1907–1910. [18] B. N. Taylor and C. E. Kuyatt, “Guidelines for evaluating and expressing the uncertainty of NIST measurement results,” NIST, Boulder, CO, NIST Tech. Note 1297, 1994. Juan Luis Cano was born in Torrelavega, Spain, in 1979. He received the Telecommunications Engineering degree and Ph.D. degree from the University of Cantabria, Santander, Spain, in 2004 and 2010, respectively. His research activity is related to the design of very low-noise LNAs in microwave integrated circuit (MIC) and monolithic microwave integrated circuit (MMIC) technologies at room and cryogenic temperatures. He has collaborated in the development and measurement of LNAs and waveguide components for different radio astronomy and satellite communications projects.

Niklas Wadefalk, photograph and biography not available at time of publication.

Juan Daniel Gallego-Puyol (M’91) was born in Madrid, Spain, in 1960. He received the Ph.D. degree in physics from the Universidad Complutense de Madrid, Madrid, Spain, in 1992. Since 1985, he has been with the Observatorio Astronómico Nacional (OAN), Yebes, Spain. In 1989, he spent one year with the National Radio Astronomy Observatory. His main research activity has been the development of cryogenic LNAs. He has been involved in numerous international projects in this field. Among others, he has been in charge of the development and construction of the cryogenic amplifiers of the Herschel ESA mission and of the amplifiers for the European contribution to ALMA.

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New CMOS-Compatible Micromachined Embedded Coplanar Waveguide Chih-Peng Lin and Christina F. Jou

Abstract—This paper proposes a new robust micromachined embedded coplanar waveguide (CPW). The central and ground plates are partially bent and overlapped within the trench, and due to tight coupling of the -field between the overlapped plates, the micromachined embedded CPW line is capable of a wide range characteristic impedance (17.9–92.3 ), in a compact size. Furthermore, the area in which the -field radiates into the substrate of the micromachined embedded CPW is quite narrow compared to conventional CPWs, and therefore, the dielectric loss of the micromachined embedded CPW can be effectively suppressed. Compared with conventional CPW lines, the embedded CPW lines have shown a marked reduction in loss, especially in the low-impedance range. The micromachined embedded CPW lines on the high-resistivity silicon substrate ( = 15 000 cm) achieve a measured loss as low as 0.81 dB/cm at 50 GHz. Moreover, the fabrication process of the micromachined embedded CPW line is compatible with the CMOS process. These features make micromachined embedded CPW a promising transmission line for RF integrated circuit application. Index Terms—Coplanar waveguide (CPW), micromachining technology, transmission line.

I. INTRODUCTION OPLANAR waveguides (CPWs) are often preferred by circuit designers and used extensively in high-density RF and monolithic microwave integrated circuits because their various advantages such as uniplanar configuration and ease of fabrication. However, CPW-based transmission lines generally suffer from a limited usable impedance ranges, especially at high and low characteristic impedance , and the loss of CPW lines tend to increase rapidly at higher frequencies [1], [2]. In order to solve these issues, a variety of modified CPW transmission lines with a number promising features have been proposed during the last decade. The main functions of the modified CPW lines are to reduce loss and increase the usable range of . Silicon as a microwave substrate, has many advantages including its low cost and the fact that it is a mature technology. However, transmission lines and integrated passive devices generally suffer significant losses due to high dielectric loss of low-

C

Manuscript received April 09, 2010; revised June 06, 2010; accepted June 07, 2010. Date of publication August 16, 2010; date of current version September 10, 2010. The authors are with the Communication Engineering Department, National Chiao Tung University, Hsinchu, Taiwan (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2010.2058552

resistivity silicon substrate at RF frequency. The dielectric loss is the obstacle to the design of distributed passive components in integrated circuits of silicon. To solve this problem, a high-resistivity silicon substrate is widely used for microwave application because of its low dielectric loss. The performance comparison of various RF passive components on different substrates is presented in [3], and high-resistivity silicon has proven an excellent candidate for a substrate in RF integrated circuit (RFIC) design [3]–[5]. range Another approach to loss reduction and increased is to modify the geometry of the transmission lines. For instance, by using membrane technology, the inner conductor can be suspended in the air, thus eliminating the dielectric loss at millimeter-wave frequencies for high- lines. This design is classified as microshield lines [6]. The micromachining technique is considered the most practical method in this regard [7]–[12]. One micromachined CPW is called channelized CPW lines [7], the material underneath the coupled aperture is partially removed to form the free-space V-shaped grooves. The total propagation loss is minimized because most of the electromagnetic (EM) fields are distributed in the free-space V-shaped region and current density flow on the conductor is reduced. Another micromachined CPW, called an overlay CPW, has been proposed [8], wherein the edges of the central conductor are partially elevated and overlaid with the two outer ground plates. It dB cm at 50 GHz) achieves low-loss characteristics ( through the redistribution of the current over a broad area, and at the same time as the range widens 25–80 . However, as is commonly known, no present studies have yet achieved a robust structure and wide range with a corresponding low loss by means of a simple fabrication process, which is also compatible with CMOS technology. This paper demonstrates a robust new micromachined CPW structure called the embedded CPW. A schematic of the micromachined embedded CPW line is shown in Fig. 1(a): the central and ground plates are partially bent and overlapped within the substrate. The loss of the embedded CPW line can be kept to a fairly low degree even on a lossy silicon substrate. Therefore, high-resistivity silicon was selected to be the substrate in the following design, purely to show a comparable contrast of losses between the conventional CPW and the embedded CPW lines. The loss characteristics of the embedded CPW lines were studied in detail for various trench widths and overlapped metal lengths. Field simulations and comparative experiments have demonstrated the characteristics of the embedded CPW lines. The embedded CPW lines were fabricated on a high-resistivity silicon substrate showing a capacity of wide range characteristic

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Fig. 2. Comparison of simulated losses for the conventional CPW and the micromachined embedded CPW lines fabricated on both the low-resistivity silicon 1 cm) and high-resistivity silicon (HRS,  1 cm) (LRS,  substrates.

= 50

= 15000

Fig. 1. Schematic diagrams of: (a) micromachined embedded CPW and (b) conventional CPW with associated parameters.

impedance from 17.9 to 92.3 with low measured loss (minimum 0.89 dB/cm at 50 GHz). The low loss was due to tight coupling of the -field between the overlapped plates, effectively suppressing the dielectric loss. II. DESIGN AND SIMULATION Fig. 1(a) and (b) shows the schematic structures of the embedded CPW and the conventional CPW, respectively. In the embedded CPW design, the signal linewidth is defined as “ ”, and “ ” is the trench width. The total trench depth is , which is the length of overlapped metal plates within the trench and represents the remainder of the is defined as aspect ratio . In this trench depth. design, the total trench depth was selected as 250 m in order to reach a compromise between minimum loss and robustness. The simulation was carried out at 50 GHz using a full-wave finite-element method, implemented through Ansoft Technologies’ High Frequency Structure Simulator (HFSS). The simulation results of the loss in decibels/centimeters are shown in Fig. 2 in which both of the CPW and embedded CPW lines are designed to be 50 and fabricated on both the lossy silicon cm) and the high-resis(low-resistivity silicon, cm substrates. In Fig. 2, the emtivity silicon ( bedded CPW lines showed low-loss performance on both lossy silicon and high-resistivity silicon substrate (below 1.7 dB/cm at 50 GHz). In contrast to the embedded CPW line, the loss of the conventional CPW line increased dramatically while it was on the lossy standard CMOS silicon substrate (more than 8 dB/cm at 50 GHz). A 1-cm-long conventional CPW fabricated on the lossy silicon substrate is impractical that the loss of the conventional CPW is significant higher than the embedded CPW, especially at a low-impedance range. Therefore, a high-resistivity silicon substrate was chosen in the following design to show a comparable contrast of losses between the conventional CPW and the embedded CPW lines. All transmission lines were fabricated by using a 525- m-thick high-resistivity silicon substrate and cm). ( was fixed at 10, 20, 30, and 40 m, of In Fig. 3, when the embedded CPW line could be designed by varying the aspect ratio. Low-impedance lines could be implanted by increasing

(

)

Fig. 3. Simulation results of aspect ratio D =W as function of characteristics impedance of the micromachined embedded CPW lines. Curve 1–4 is rep; ; ; and m, respectively. resented as W

= 10 20 30

40

the aspect ratio. On the other hand, high lines could also be implanted by reducing the aspect ratio without additional process difficulty. As shown in Fig. 3, the embedded CPW line is capable of a wide impedance range from 17.9 to 92.3 . As is fixed at 10 m with aspect ratio , can reach as low is fixed at 40 m with aspect ratio , as 17.9 . As can reach up to 92.3 . III. PARAMETER STUDY The simulated losses as a function of were shown in Fig. 4. The associated dimension of both the conventional CPW lines and embedded CPW lines is as follows. m for each 1) Conventional CPW: and m m for each m, 2) Embedded CPW: and m, m, m, m, m, m, m. As shown in Fig. 4, the characteristic impedance of the conventional CPW line could not be reduced below 26 due to the limitations of photolithography. Moreover, the loss of the conwas below 37 , ventional CPW line increased rapidly when which showed that the conventional CPW line was impractical application. In contrast with the conventional CPW in low line, the embedded CPW line has no difficulty to reach low and maintain low loss at the same time. For the embedded CPW m, the loss can be maintained below 1 dB/cm line, as for the entire range of from 19.3 to 92.3 m.

LIN AND JOU: NEW CMOS-COMPATIBLE MICROMACHINED EMBEDDED CPW

Fig. 4. Comparison of simulated losses as a function of Z for different dimensions of the conventional CPW and the micromachined embedded CPW ; ; ; and m that the aspect ratio D =W is varied from (as W 0.5 to 6 for each W ) on the 525-m-thick high-resistivity silicon substrate.

= 10 20 30

40

(

)

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Fig. 6. Attenuation of the micromachined embedded CPW lines with variation on parameter S as S m, S m, and S , respectively (W m, and D m for each line). m, D

30

= 120

= 10

= 20 = 130

= 30

=

Fig. 5. Cross-sectional schematic of electric field distribution for: (a) conventional CPW and (b) micromachined embedded CPW.

In Fig. 5, the electric field distribution in the embedded CPW lines are simulated and shown in the cross-sectional view. m Fig. 5(a) shows the conventional CPW line with and m, and Fig. 5(b) shows the embedded CPW m, m, m, and line with m. As shown in Fig. 5(a), the -field radiates into the substrate directly causing considerable dielectric loss. In contrast with the conventional CPW, the embedded CPW shows that the reduction of dielectric loss can be accomplished by confining most of the electric field to the air between the within the trench (Fig. 5(b) shows overlapped plates the cross-sectional schematic of -field distribution for the embedded CPW). The rest of the -field will radiate into the . Since the area in which the -field bottom of the trench radiates into the substrate of the embedded CPW is quite narrow compared to the conventional CPW, the dielectric loss of the embedded CPW can be suppressed efficiently. It is worth noticing in Fig. 5(b) that the -fields radiating into the center are the of the substrate underneath the signal plate major causes of the loss in the embedded CPW. Therefore, by reducing the size of , we cannot only reduce the dielectric loss, but also shrink the size. As we can see in Fig. 6, the simulation indicates that smaller led to lower loss. In this paper, due to m fabrication concerns, the length of was selected to be in order to reach a compromise between loss performance and fabrication difficulties.

Fig. 7. Attenuation of the micromachined embedded CPW lines with variation m, m, and on parameter: (a) D , curve 1–3 is represented as D m for each m, respectively (S m, W m, and D m, m, and m, line). (b) D , curve 1–3 is represented as D respectively (S m, W m, and D m for each line).

20

= 20

= 20

= 30

= 30

= 80 = 250

= 0 10 = 120 90 100

Fig. 7(a) shows that as m and is fixed at increases (total trench depth 160 m, the loss decreases as increases) due to a reduction in the dielectric loss. Fig. 7(b) m and m, the loss decreased shows that as increased (ohmic loss decreases). Comparing Fig. 7(a) as with Fig. 7(b), it can also be observed that the loss varied dra, while the loss reduction contributed by inmatically with was relatively small. Consequently, the loss mechcreasing anisms of the embedded CPW lines was dominated by the dielectric loss. Miniaturization in RFIC design is considered a significant can be adissue. For the embedded CPW lines, as is fixed, justed simply by varying the aspect ratio without increasing the

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Fig. 8. Fabrication process flows for the micromachined embedded CPW line. (a) Photoresist coating. (b) Lithography (mask-1) then inductively coupled plasma deep etching of high-resistivity silicon substrate and photoresist removal. (c) Sputtering of Ti and Cu. (d) Lithography (mask-2) then electroplating of Cu. (e) Remove photoresist then stripping of Cu in unwanted position.

surface area . Unlike the embedded CPW lines, of the conventional CPW was mainly affected by the geometrical parameters of and . As a result, to reach the same , the conventional CPW consumed a larger surface area than the embedded CPW did, especially at high : for instance, when m, the totally surface area of the conventional CPW was 2 80 20 m, while the embedded CPW could achieve using only 2 10 20 m surface area. These rethe same sults demonstrated that the embedded CPW lines could be very compact.

IV. FABRICATION The embedded CPW lines were fabricated on 525- m-thick cm with the high-resistivity silicon substrates length of 1 cm. Fig. 8 illustrates the entire fabrication process flow of the embedded CPW line. The fabrication of the embedded CPW is as follows. 1) Photoresist AZ4620 was spin-coated on the substrate [see Fig. 8(a)]. 2) The desired trench position was defined by photolithography in which the hard-bake step was skipped for better trench formation. The trench was formed through inductively coupled plasma etching [see Fig. 8(b)]. For inductively coupled plasma etching, the etching selectivity between photoresist and silicon was 1:50. Therefore, the desired trench depth of 250- m trench depth with very sharp sidewalls was easily achieved. 3) Metallization was performed through sputtering and electroplating technology. a) A 15-nm titanium-adhesion-layer and a 40-nm copper-seed-layer were sputtered [see Fig. 8(c)]. b) The desired position to deposit was patterned with photoresit AZ 4620. c) Electroplating of copper to a thickness of about 6 m [see Fig. 8(d)]. It is worth mentioning that while sputtering metal into the trench, if the aspect ratio of the trench were greater than the metal step coverage, the metal would only deposit on the

Fig. 9. Scanning electron microscope (SEM) photograph of different aspect ratio in the micromachined embedded CPW lines with corresponding process : ; Ti: 5 mtorr, 5 min and Cu: 10 mtorr, parameters. (a) Aspect ratio : ; Ti: 5 mtorr, 10 min and Cu: 10 mtorr, 20 min. 5 min. (b) Aspect ratio (c) Aspectratio : ; Ti: 10 mtorr, 10 min and Cu: 20 mtorr, 10 min. : ; Ti: 10 mtorr, 10 min and Cu: 20 mtorr, 20 min. (d) Aspect ratio

= 18 = 33 = 46 =54

sidewalls of the trench instead of covering the entire trench. This phenomenon was used to form the overlapping plate structure within the trench. Moreover, the desired depth of the sputtered metal on the sidewalls within the trench could be well controlled by adjusting chamber pressure and sputtering time, as shown in Fig. 9, with associated process parameters in the figure caption. In the final step, after the photoresist had been removed, a Cu stripper was used to remove the Cu from the unwanted areas [see Fig. 8(e)]. The fabrication process of the embedded CPW line was fairly simple; only two masks were required. Additionally, the fabrication process followed the CMOS process, showing the capability of integration with RFICs. V. MEASUREMENT A microphotograph of the fabricated embedded CPW line on the high-resistivity silicon substrate is shown in Fig. 10(a) and a cross-sectional view of the embedded CPW is shown in Fig. 10(c). The -parameters of all the 1-cm-long lines were measured up to 60 GHz using an Agilent E8361A network analyzer and cascade wafer probe station. The system was calibrated by a short-open-load-thru (SOLT) to remove systematic errors in the test system and to define measurement reference. A set of open coplanar pads was also designed and fabricated adjacent to the lines, in order to de-embed the parasitic effects of the transmission line pads. Thirteen sets of lines fabricated on high-resistivity silicon substrate have been measured to obtain -parameters, including m, m, the embedded CPW lines ( and m, m, m, and m) and the conventional CPW lines ( m, and m). The measured

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Fig. 11. Measured and simulated losses for the CPW (S = 20 m, W = 5; 10; 20; 30; 80; and 100 m) and the micromachined embedded CPW (S = 20 m, W = 30 m, D = 10; 30; 100; and 150 m; W = 40 m, D = 40; 120; and 200 m).

Fig. 10. SEM photograph of the micromachined embedded CPW line. (a) Probing pad from the top view. (b) Enlargement in the circled region in (a). (c) Cross-sectional view.

The real part of is the attenuation constant that represents conductor and dielectric loss of the measured transmission lines. The measured loss as a function of is shown in Fig. 11. The measured results of the embedded CPW lines showed strong correlation with the simulated results. The discrepancy between simulation and measured losses should be caused by variations in the fabrication process. The measured loss of the embedded CPW lines was below 1.67 dB/cm of impedance range from 24.9 to 76.2 . The minimum loss is 0.81 dB/cm was ( m, m, m). Compared with the conventional CPW lines, the embedded CPW lines showed a substantial improvement on loss, especially in the low-impedance range. Fig. 11 clearly shows the advantage of the applications. As , embedded CPW lines for low there is a noticeable reduction in loss of 1.2 dB/cm in the embedded CPW versus 7 dB/cm of loss in the conventional CPW line. Due to the minimal dielectric loss of the embedded CPW to low lines, the gradual loss reduction from high in this study may be attributed to an enhanced spreading of the current across a wider area as the aspect ratio increased. VI. CONCLUSION

-parameters are converted to the following formula [14]:

-parameters, and using

(1a) (1b) (1a) to obtain , and then extract propagation constant from , and are the characteristic impedance, the (1b). Where propagation constant and length of the transmission line, respectively. Therefore, the propagation constant could be determined as

In this paper, a new CPW structure called the micromachined embedded CPW was demonstrated. The embedded structure was proposed to provide such promising features, such as a wide characteristic impedance range with low loss, while at the same time ensuring compact size and strong mechanical support. EM simulation and comparative experiments were utilized to fully characterize the embedded CPW lines. The embedded CPW lines on both a lossy silicon and high-resistivity silicon substrate showed fairly low losses. With the implementation of the high-resistivity silicon substrate, the embedded CPW lines showed relatively low measured loss below 1.67 dB/cm from at 50 GHz (minimum loss of 0.81 dB/cm as 24.9 to 76.2 ). Compared with conventional CPW lines, the embedded CPW lines showed a marked improvement on loss, especially in the low-impedance range. Moreover, the fabrication process of the embedded CPW lines was fairly simple and compatible with the CMOS fabrication process. These promising

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features confirm the embedded CPW as a promising uniplanar transmission line base for RFIC applications.

ACKNOWLEDGMENT The authors would like to thank Chip Implementation Center (CIC), Hsinchu, Taiwan, for their technical measurement support, National Science Council of Taiwan, Hsinchu, Taiwan, for their support, and the Nano Facility Center, National Chiao Tung University, Hsinchu, Taiwan, for offering the experimental equipment. The authors would also like to thank Dr. C.-U. Huang for bringing up the concept of this novel structure when he was studying for his doctorate at the Institute of Electronics Engineering, National Tsing Hua University, Hsinchu, Taiwan.

REFERENCES [1] R. W. Jackson, “Considerations in the use of coplanar waveguide for millimeter-wave integrated circuits,” IEEE Trans. Microw. Theory Tech., vol. MTT-34, no. 12, pp. 1450–1456, Dec. 1986. [2] K. C. Gupta, R. Garg, I. Bahl, and P. Bhartia, Microstrip Lines and Slotlines. Norwood, MA: Artech House, 1996, ch. 7. [3] A. C. Reyes, S. M. El-Ghazaly, S. Dorn, M. Dydyk, and D. K. Schroder, “Silicon as a microwave substrate,” in IEEE MTT-S Int. Microw. Symp. Dig,., May 1994, pp. 1759–1762. [4] C. Warns, W. Menzel, and H. Schumacher, “Transmission lines and passive elements for multilayer coplanar circuits on silicon,” IEEE Trans. Microw. Theory Tech., vol. 46, no. 5, pp. 616–622, May 1998. [5] A. Reyes et al., “Coplanar waveguides and microwave inductors on silicon substrates,” IEEE Trans. Microw. Theory Tech., vol. 43, no. 9, pp. 2016–2021, Sep. 1995. [6] N. I. Dib, W. P. Harokopus , Jr, L. P. B. Katehi, C. C. Ling, and G. M. Rebeiz, “Study of a novel planar transmission line,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 1991, pp. 623–626. [7] K. J. Herrick, T. A. Schwarz, and L. P. B. Katehi, “Si-micromachined coplanar waveguides for use in high-frequency circuits,” IEEE Trans. Microw. Theory Tech., vol. 46, no. 6, pp. 762–768, Jun. 1998. [8] H. T. Kim, S. Jung, J. H. Park, C. W. Baek, Y. K. Kim, and Y. Kwon, “A new micromachined overlay CPW structure with low loss over wide impedance ranges and its application to low-pass filters,” IEEE Trans. Microw. Theory Tech., vol. 49, no. 9, pp. 1634–1639, Sep. 2001. [9] V. Milanovic, M. Gaitan, E. D. Bowen, and M. E. Zaghloul, “Micromachined microwave transmission lines in CMOS technology,” IEEE Trans. Microw. Theory Tech., vol. 45, no. 5, pp. 630–635, May 1997.

[10] Z. R. Hu, V. F. Fusco, J. A. C. Stewart, Y. Wu, H. S. Gamble, B. M. Armstrong, and N. B. Buchanan, “Characteristics of trenched coplanar waveguide for Si MMIC applications,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 1997, pp. 735–738. [11] G. E. Ponchak, A. Margomenos, and L. P. B. Katehi, “Low-loss CPW on low-resistivity Si substrates with a micromachined polyimide interface layer for RFIC interconnects,” IEEE Trans. Microw. Theory Tech., vol. 49, no. 5, pp. 866–870, May 2001. [12] L. L. W. Leung, W.-C. Hon, J. Zhang, and K. J. Chen, “Characterization and attenuation mechanism of CMOS-compatible micromachined edge-suspended coplanar waveguides on low-resistivity silicon substrate,” IEEE Trans. Adv. Packag., vol. 29, no. 3, pp. 496–503, Aug. 2006. [13] G. F. Engen and C. A. Hoer, “Thru-reflect-line: An improved technique for calibrating the dual six-port automatic network analyzer,” IEEE Trans. Microw. Theory Tech., vol. MTT-27, no. 12, pp. 987–993, Dec. 1979. [14] W. R. Eisenstadtand and Y. Eo, “Experimental analysis of transmission line parameters in high-speed GaAs digital circuit interconnects,” IEEE Trans. Microw. Theory Tech., vol. 39, no. 8, pp. 1361–1367, Aug. 1991. [15] G. Matthaei, L. Young, and E. Jones, Microwave Filters, Impedance Matching Networks, and Coupling Structures. Norwood, MA: Artech House, 1980. Chih-Peng Lin was born in Chiayi, Taiwan, in 1983. He received the B.S. degree in electronic engineering from Feng-Chia University, Taichung, Taiwan, in 2005, the M.S. degree in communication engineering from the National Chiao-Tung University, Hsinchu, Taiwan, in 2007, and is currently working toward the Ph.D. degree in communication engineering at the National Chiao-Tung University. His research interests include RF microelectromechanical systems (MEMS) interconnections, filters, inductors, and antenna.

Christina F. Jou was born in Taipei, Taiwan, in 1957. She received the B.S., M.S., and Ph.D. degrees in electrical engineering from the University of California at Los Angeles (UCLA), in 1980, 1982, and 1987, respectively. Her doctoral dissertation concerned the millimeter-wave monolithic Schottky diode-grid frequency doubler. From 1987 to 1990, she was with Hughes Aircraft Company, Torrance, CA, as a Member of the Technical Staff with the Microwave Products Division, where she was responsible for microwave device modeling. In 1990, she joined National Chiao-Tung University, Hsinchu, Taiwan, where she is currently an Associate Professor of communication engineering. Her current research concerns the development of RF and microwave active circuits and RF MEMS.

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Letters Comments on “A Novel Vector Network Analyzer” Ugur Cem Hasar In the above paper [1], Hoffmann and Skvor concluded that six independent parameters are needed to fully map the complex reflection coefficient of an unknown sample (S ) to amplitude-only reflection measurements (jM j) by a scalar vector network analyzer using a characteristic equation [see (1)]. In this letter, we demonstrate that, in fact, five independent parameters in that equation are sufficient to fully map complex S into jM j. In the above paper [1], this characteristic equation, for convenience, is given

M j = jS11 + S12 S21 S =(1 0 S22 S )j

j

(1)

where j  j denotes the amplitude of “.” Defining 1 = S11 S22 S12 S21 = det(S ) [2], [3] reduces (1) to

0

transformation between S and jM j, these parameters are not sufficient to fully characterize a reciprocal error perturbation two-port matrix, which is shown in the above paper [1, Fig. 4]. This can easily be found if we try to determine S21 using the above five scalar parameters 2 from 1 = S11 S22 0 S12 S21 = S11 S22 0 S21 . It is important to discuss that even though only five scalar parameters are needed for the conformal transformation between S and jM j, it does not necessarily mean that only five independent measurements are sufficient for this transformation because the characteristic equation in (5) is a nonlinear equation. Therefore, additional measurements are necessary to distinguish the correct value of S . This is a general problem of determining the value of a complex variable from measured amplitudes of reflection and/or transmission coefficients [4]–[7]. As a result, the selection of appropriate calibration standards becomes an important factor for this conformal transformation. We think that the characteristic equation in (5) gives insight into this selection more than that in the above paper [1, eq. (3)] and hope that this discussion is helpful on noncoherent vector network analyzer applications [8].

REFERENCES M j = j(S11 0 1S )=(1 0 S22 S )j :

j

(2)

Substituting the following complex parameters into (2):

Sm = jSm jej

S = jS jej

j ;

1 = j1je

m = 11; 22 (3)

we obtain

S11 j2 + j1j2 jS j2 0 2jS11 jj1jjS j cos(11 0 1 0 s ) : 1+ jS22 j2 jS j2 0 2jS22 jjS j cos(22 + s ) (4) To demonstrate that only five unknown parameters in (1) or (4) are sufficient to measure complex S using jM j, we expand the cosine trigonometric terms in (4) in terms of s , T = 11 0 1 , and 22 . jM j can then be found in (5), shown at the bottom of this page. It is obvious from (5) that the following five scalar variables jS11 j, jS22 j, j1j, 22 , and T can allow one to map the known complex S into jM j. It should be noted that although it has been demonstrated that only the above five scalar parameters are sufficient to define a conformal M j2 =

j

j

[1] K. Hoffmann and Z. Skvor, “A novel vector network analyzer,” IEEE Trans. Microw. Theory Tech., vol. 46, no. 2, pp. 2520–2523, Dec. 1998. [2] C. Wan, B. Nauwelaers, W. De Raedt, and M. Van Rossum, “Two new measurement methods for explicit determination of complex permittivity,” IEEE Trans. Microw. Theory Tech., vol. 46, no. 11, pp. 1614–1619, Nov. 1998. [3] U. C. Hasar, “A new microwave method for electrical characterization of low-loss materials,” IEEE Microw. Wireless Compon. Lett., vol. 19, no. 12, pp. 801–803, Dec. 2009. [4] U. C. Hasar, “Two novel amplitude-only methods for complex permittivity determination of medium- and low-loss materials,” Meas. Sci. Technol., vol. 19, no. 5, p. 055706, May 2008, 10 pp. [5] U. C. Hasar, “A generalized formulation for permittivity extraction of low-to-high-loss materials from transmission measurement,” IEEE Trans. Microw. Theory Tech., vol. 58, no. 2, pp. 411–418, Feb. 2010. [6] U. C. Hasar and C. R. Westgate, “A broadband and stable method for unique complex permittivity determination of low-loss materials,” IEEE Trans. Microw. Theory Tech., vol. 57, no. 2, pp. 471–477, Feb. 2009. [7] U. C. Hasar, “A fast and accurate amplitude-only transmission-reflection method for complex permittivity determination of lossy materials,” IEEE Trans. Microw. Theory Tech., vol. 56, no. 9, pp. 2125–2135, Sep. 2008. [8] M. A. Abou-Khousa, M. A. Baumgartner, S. Kharkovsky, and R. Zoughi, “Novel and simple high-frequency single-port vector network analyzer,” IEEE Trans. Instrum. Meas., vol. 59, no. 3, pp. 534–542, Mar. 2010.

Manuscript received December 11, 2009; revised January 22, 2010; accepted June 02, 2010. Date of publication August 16, 2010; date of current version September 10, 2010. The author is with the Department of Electrical and Electronics Engineering, Ataturk University, 25240 Erzurum, Turkey (e-mail: [email protected]). Digital Object Identifier 10.1109/TMTT.2010.2058585

M j2

j

=

S11 j2 + j1j2 jS j2 0 2jS11 jj1jjS j(cos T cos s + sin T sin s ) 1 + jS22 j2 jS j2 + 2jS22 jjS j(sin 22 sin s 0 cos 22 cos s )

j

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Authors’ Reply

Corrections to “Modified Adaptive Prototype Inclusive of the External Couplings for the Design of Coaxial Filters”

Karel Hoffmann and Zbynek Skvor

Antonio Morini and G. Venanzoni In his comments to the above paper [1], Dr. Hasar provides an elegant mathematical description of the number of parameters to be determined during calibration, e.g., five. This agrees with our statements that: 1) there are six unknown parameters (three complex numbers S11 , S12 ; S21 ; and S22 ) altogether in [1, eq. (2)]; 2) where one of these cannot be determined using scalar measurements only, but; 3) (fortunately), this parameter does not need to be known for the measurement process. We did not conclude in the above paper [1] that six independent parameters are needed to fully map the complex reflection coefficient of an unknown sample (S ) to amplitude-only reflection measurements (jM j). In order to obtain results in the above paper [1], we used five parameters. According to our statement that inserting a transmission line between the scalar analyzer and a perturbation two-port would not affect measured values, we imposed the condition that the argument of S11 is zero during calibration and data correction. Any other real value would do the same job. We also note that the relation between S and jM j is not a conformal transformation.

There are typographical errors in the above paper [1, eq. (4)]. The correct equation is as follows:

!0 L =

1

Im Re

S 1

S

0

1

K

2

2 = (!0 L) +

1

Re

S

Re

S

1

+1 0

1

:

REFERENCES [1] A. Morini, G. Venanzoni, M. Farina, and T. Rozzi, “Modified adaptive prototype inclusive of the external coupling for the design of coaxial filters,” IEEE Trans. Microw. Theory Tech., vol. 55, no. 9, pp. 1905–1911, Sep. 2007.

REFERENCES [1] K. Hoffmann and Z. Skvor, “A novel vector network analyzer,” IEEE Trans. Microw. Theory Tech., vol. 46, no. 12, pp. 2520–2523, Dec. 1998. Manuscript received May 25, 2010; accepted June 02, 2010. Date of publication August 23, 2010; date of current version September 10, 2010. This work was supported by the Ministry of Education, Youth and Sports of the Czech Republic under Research Program MSMT6840770015 (“Research of Methods and Systems for Measurement of Physical Quantities and Measured Data Processing” of the Czech Technical University). The authors are with the Faculty of Electrical Engineering, Czech Technical University, 166 27 Prague 6, Czech Republic (e-mail: [email protected]; [email protected]). Digital Object Identifier 10.1109/TMTT.2010.2058583

Manuscript received June 05, 2010; revised June 05, 2010; accepted June 05, 2010. Date of publication August 16, 2010; date of current version September 10, 2010. The authors are with the Dipartimento di Elettromagnetismo e Bioingegneria, Università Politecnica delle Marche, I60131 Ancona, Italy (e-mail: [email protected]; [email protected]). Digital Object Identifier 10.1109/TMTT.2010.2058935

0018-9480/$26.00 © 2010 IEEE

Digital Object Identifier 10.1109/TMTT.2010.2074010

Digital Object Identifier 10.1109/TMTT.2010.2074030

EDITORIAL BOARD Editor-in-Chief: GEORGE E. PONCHAK Associate Editors: H. ZIRATH, W. VAN MOER, J.-S. RIEH, Q. XUE, L. ZHU, K. J. CHEN, M. YU, C.-W. TANG, B. NAUWELAERS, J. PAPAPOLYMEROU, N. S. BARKER, C. D. SARRIS, C. FUMEAUX, D. HEO

P. Aaen A. Abbaspour-Tamijani A. Abbosh D. Abbott A. Abdipour M. Abe M. Abegaonkar R. Abhari A. Abramowicz M. Acar L. Accatino R. Achar E. Ackerman J. Adam K. Agawa M. Ahmad H.-R. Ahn B. Ai M. Aikawa J. Aikio C. Aitchison M. Akaike T. Akin S. Aksoy I. Aksun A. Akyurtlu G. Ala L. Albasha A. Alexanian W. Ali-Ahmad F. Alimenti R. Allam K. Allen A. Alphones A. Alu A. Álvarez-Melcon A. Al-Zayed S. Amari H. Amasuga R. Amaya H. An D. Anagnostou M. Andersen K. Andersson M. Ando Y. Ando P. Andreani M. Andrés W. Andress K. Ang C. Angell I. Angelov Y. Antar G. Antonini H. Aoki V. Aparin F. Apollonio R. Araneo J. Archer F. Ares F. Ariaei T. Arima M. Armendariz L. Arnaut F. Arndt E. Artal H. Arthaber F. Aryanfar U. Arz M. Asai Y. Asano A. Asensio-Lopez K. Ashby H. Ashoka A. Atalar A. Atia S. Auster I. Awai A. Aydiner M. Ayza K. Azadet R. Azaro A. Babakhani P. Baccarelli M. Baginski I. Bahl S. Bajpai J. Baker-Jarvis B. Bakkaloglu M. Bakr A. Baladin C. Balanis S. Balasubramaniam J. Balbastre J. Ball P. Balsara Q. Balzano A. Banai S. Banba R. Bansal D. Barataud A. Barbosa F. Bardati I. Bardi J. Bardin A. Barel S. Barker F. Barnes J. Barr G. Bartolucci R. Bashirullan S. Bastioli A. Basu B. Bates R. Baxley Y. Bayram J.-B. Bégueret N. Behdad F. Belgacem H. Bell D. Belot J. Benedikt T. Berceli C. Berland M. Berroth G. Bertin E. Bertran A. Bessemoulin M. Beurden A. Bevilacqua A. Beyer M. Bialkowski

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H. Chiu A. Chizh C. Cho K. Cho T. Cho A. Choffrut C. Choi J. Choi W. Choi C. Chong M. Chongcheawchamnan C. Chou D. Choudhury E. Chow Y. Chow C. Christodoulou C. Christopoulos Q. Chu T. Chu H. Chuang M. Chuang Y. Chun S. Chung Y. Chung D. Chye A. Cidronali T. Cisco C. Cismaru O. Civi S. Clavijo M. Clénet D. Cogan P. Colantonio M. Cole J. Coleman J. Collantes R. Collin C. Collins B. Colpitts R. Compton G. Conciauro M. Condon D. Consonni A. Constanzo M. Converse K. Cools F. Cooray I. Corbella A. Costanzo S. Cotton C. Courtney G. Coutts J. Cowles J. Craninckx C. Crespo-Cadenas J. Cressler S. Cripps T. Crowe J. Cruz T. Cui E. Cullens T. Cunha W. Curtice J. Dabrowski W. Dai G. Dambrine P. Dankov F. Danneville I. Darwazeh A. Darwish N. Das M. Davidovich L. Davis D. Dawn J. Dawson H. Dayal F. De Flaviis D. De Zutter B. Deal A. Dearn J. Deen M. Dehan C. Dehollain C. Deibele G. Dejean M. DeLisio N. Deltimple S. Demir V. Demir J. Deng A. Dengi T. Denidni W. DeRaedt H. Deshpande Y. Deval R. Dey T. Dhaene L. Diaz A. Diaz-Morcillo L. Ding M. Dionigi C. Diskus A. Djordjevi T. Djordjevic J. Dobrowolski H. Dogan S. Donati X. Dong A. Dounavis P. Draxler R. Drayton A. Dreher J. Drewniak J. Duchamp A. Duffy L. Dunleavy J. Dunsmore S. Durden L. Dussopt C. Duvanaud J. East J. Ebel K. Eccleston I. Ederra R. Egri I. Ehrenberg N. Ehsan T. Eibert H. Eisele W. Eisenstadt G. Eleftheriades

F. Ellinger G. Ellis T. Ellis M. El-Nozahi M. Elsbury S. Elschner M. El-Shenawee T. Enoki K. Entesari L. Epp I. Erdin O. Ergul T. Eriksson C. Ernst D. Erricolo I. Eshrah M. Essaaidi H. Esteban C. Eswarappa W. Eyssa A. Ezzeddine C. Fager M. Fahmi Y. Fan D. Fang M. Farina A. Fathy M. Faulkner P. Fay A. Fazzi E. Fear P. Fedorenko D. Feld Y. Feng A. Feresidis A. Fernandez T. Fernandez M. Fernández-Barciela M. Ferndahl F. Fernez P. Ferrari E. Ferre-Pikal A. Ferrero M. Ferriss H. Fetterman J. Fiedziuszko S. Fiedziuszko G. Fikioris J. Fikioris I. Filanovsky F. Filicori D. Filipovic R. Fletcher B. Floyd H. Foltz N. Fong B. Fornberg F. Fortes K. Foster P. Foster P. Franzon A. Frappe J. Freire M. Freire A. Freundorfer F. Frezza I. Frigyes R. Frye J. Fu O. Fu R. Fujimoto O. Fujiwara C. Fumeaux C. Furse V. Fusco D. Gabbay E. Gad M. Gadringer N. Gagnon J. Gajadharsing A. Gala C. Galbraith B. Galwas J. Gambini A. Gameiro O. Gandhi B. Gao J. Gao S. Gao C. Gaquiere H. Garbe J. Garcia M. Garcia P. Garcia-Ducar F. Garcia-Vidal K. Gard P. Gardner P. Garland P. Gaudo J. Gautier S. Gedney B. Geelen F. Gekat B. Geller R. Genov A. Georgiadis N. Georgieva J. Gerdes W. Gerhard S. Gevorgian H. Ghali M. Ghanevati F. Ghannouchi K. Gharaibeh R. Gharpurey G. Ghione M. Ghovanloo F. Giannini A. Gibson I. Gil P. Gilabert B. Gimeno D. Ginste A. Goacher E. Godshalk A. Goel C. Goldsmith M. Golio M. Golosovsky R. Gómez-García A. Goncharenko X. Gong

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Digital Object Identifier 10.1109/TMTT.2010.2073853

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