MT6359 PMIC Datasheet [1.5 ed.]

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MT6359 PMIC Datasheet Confidential A

MT6359 PMIC Datasheet

Version:

1.5

Release date:

2020-04-06

Use of this document and any information contained therein is subject to the terms and conditions set forth in Exhibit 1. This document is subject to change without notice.

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MT6359 PMIC Datasheet Confidential A

Document Revision History Revision 1.0

Date 2018-11-21

Author Vincent Chiang

1.1

2019-03-12

Tim Lee

1.2

2019-06-12

Tim Lee

1.3

2019-09-09

Tim Lee

2019-11-15

Tim Lee

Description Official release 1. Added spec of accuracy at PFM in Table 2-17. 2. Changed column naming of Table 3-2. 3. Modified quiescent current in Table 2-6. 4. Modified Figure 3-4. 5. Added new order part and top marking. 6. Modified OVLO spec in Table 2-4. 1. Added new order part and top marking. 2. Added descriptions in Table 2-5. 3. Added descriptions in Table 3-1, 3-2. 4. Added new part’s power-on sequence figure. 5. Added descriptions for VRFCK/VRFCK_1 and fixed typo in the following: 5.1. Table 2-19, 2-20, 3-2 5.2. Page 76, 78, 80, 151 6. Added chapter 1.6 to distinguish between 6359VP/A and 6359VPP/B. 7. Added register table for GroupA & GroupB 1. Modified dcxo phase noise to align measurement results. 2. Added new part, MT6359VMP/B in Group B. 3. Modified VRFCK voltage. 4. Added 1 uH efficiency curves on p31~32. 5. Added MT6359VMP/B’s information in 1.6 and Table 3-1, Table 3-2. 6. In Table 2-5, PFM accuracy spec change at VCORE/VPROC1/VPROC2/VGPU align to VMODEM’s. Table3-2, VEMC default-V modified at 2.5V. 1. Added MT6359VUP/B & MT6359UP/B information in section 1.4/1.5/1.6 and Table 3-1, Table 3-2. 2. Added the power-on sequence figure for MT6359VUP/B & MT6359UP/B in Fig.3-4

1.4

3. Added the frequency spec while BUCK uses 0.24uH 2020-01-15

Tim Lee

4. In Table 3-1, updated VS2 IP_Imax up to 2.5A 5. In Table 2-5, updated VS2 OC spec in accordance with the change of Imax to 2.5A 6. Modified VRFCK & VBBCK default voltage 7. In Table 3-1, updated VS1 IP_Imax up to 2.2A

1.5

2020-04-06

Tim Lee

1. Added MT6359VNP/B & MT6359NP/B information in section 1.4/1.5/1.6 and Table 3-1, Table 3-2. 2. Added the power-on sequence figure for MT6359VNP/B & MT6359NP/B in Fig.3-5

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MT6359 PMIC Datasheet Confidential A

Table of Contents Document Revision History .............................................................................................................................. 2 Table of Contents............................................................................................................................................. 3 1

2

Overview ............................................................................................................................................... 7 1.1

Features............................................................................................................................................. 7

1.2

Applications ....................................................................................................................................... 7

1.3

General Description .......................................................................................................................... 7

1.4

Ordering Information ........................................................................................................................ 8

1.5

Top Marking Definition ..................................................................................................................... 9

1.6

Main Differences between Group A and Group B........................................................................... 11

1.7

Pin Assignments and Description .................................................................................................... 13

Electrical Characteristics ...................................................................................................................... 18 2.1

Absolute Maximum Ratings over Operating Free-Air Temperature Range .................................... 18

2.2

Thermal Characteristics ................................................................................................................... 19

2.3

Pin Voltage Range ........................................................................................................................... 20

2.4

Recommended Operating Range .................................................................................................... 24

2.5

Electrical Characteristics ................................................................................................................. 25

2.6

Regulator Output ............................................................................................................................ 26

2.7

Vibrator ........................................................................................................................................... 39

2.8

Audio CODEC ................................................................................................................................... 40

2.9

Charger-in Detection ....................................................................................................................... 46

2.10 AUXADC ........................................................................................................................................... 47 2.11 Fuel Gauge....................................................................................................................................... 48 2.12 BIF.................................................................................................................................................... 49 2.13 DCXO ............................................................................................................................................... 50 2.13.1 3

Reference Output Buffer(s) Specifications ....................................................................... 50

Functional Description ......................................................................................................................... 52 3.1

General Description ........................................................................................................................ 52

3.2

PMIC Functional Blocks ................................................................................................................... 53 3.2.1

Power-on/off Sequence ................................................................................................... 53

3.2.2

Buck Converter and Application Reference ..................................................................... 59

3.2.3

Low Dropout Regulator (LDOs) and Application Reference ............................................. 61

3.2.4

Vibrator ............................................................................................................................ 62

3.2.5

Audio CODEC and Accessory Detection ........................................................................... 62

3.2.6

AUXADC ............................................................................................................................ 65

3.2.7

Fuel Gauge ....................................................................................................................... 65

3.2.8

BIF .................................................................................................................................... 66

3.2.9

Real-Time Clock ................................................................................................................ 67

3.2.10

DCXO ................................................................................................................................ 67

3.2.11

Interrupt and Watchdog .................................................................................................. 68

3.2.12

SPI Interface ..................................................................................................................... 69

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MT6359 PMIC Datasheet Confidential A 3.2.13

4

3.3

Register Table and Description (Group A) ....................................................................................... 73

3.4

Register Table and Description (Group B) ..................................................................................... 301

Application Notes ............................................................................................................................ 1064 4.1

5

GPIO ................................................................................................................................. 71

Configuration for Unused Buck Converter .................................................................................. 1064

MT6359 Packaging........................................................................................................................... 1065 5.1

Package Dimension ..................................................................................................................... 1065

Appendix ................................................................................................................................................... 1066 Exhibit 1 Terms and Conditions.................................................................................................................. 1067

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MT6359 PMIC Datasheet Confidential A Lists of Figures Figure 1-1. MT6359 WLCSP 203 (5.65 x 5.29 mm) pin assignment (top view) ..................................................... 13 Figure 2-1. VPROC1/VPROC2 efficiency ................................................................................................................ 33 Figure 2-2. VGPU efficiency .................................................................................................................................. 33 Figure 2-3. VCORE efficiency (MT6359/A) ............................................................................................................ 33 Figure 2-4. VCORE efficiency (MT6359/B) ............................................................................................................ 33 Figure 2-5. VMODEM efficiency (MT6359/A) ....................................................................................................... 33 Figure 2-6. VMODEM efficiency (MT6359/B) ....................................................................................................... 33 Figure 2-7. VPU efficiency (MT6359/A) ................................................................................................................ 34 Figure 2-8. VPU efficiency (MT6359/B) ................................................................................................................ 34 Figure 2-9. VS1 efficiency ...................................................................................................................................... 34 Figure 2-10. VS2 efficiency .................................................................................................................................... 34 Figure 2-11. VPA efficiency ................................................................................................................................... 34 Figure 2-12. Audio path THD + N vs. frequency .................................................................................................... 43 Figure 2-13. Audio path Xtalk vs. frequency @POUT = 10 mW ............................................................................... 43 Figure 3-1. MT6359 block diagram ....................................................................................................................... 52 Figure 3-2. (MT6359VP/A, Group A) Power-on/off control sequence without XTAL by charger plug-in or pressing PWRKEY .................................................................................................................................................. 54 Figure 3-3. (MT6359VPP/B & MT6359VMP/B, Group B) Power-on/off control sequence without XTAL by charger plug-in or pressing PWRKEY .................................................................................................................................. 55 Figure 3-4. (MT6359VUP/B & MT6359UP/B, Group B) Power-on/off control sequence without XTAL by charger plug-in or pressing PWRKEY .................................................................................................................................. 56 Figure 3-5. (MT6359VNP/B & MT6359NP/B, Group B) Power-on/off control sequence without XTAL by charger plug-in or pressing PWRKEY .................................................................................................................................. 57 Figure 3-6. Audio CODEC block diagram ............................................................................................................... 64 Figure 3-7. Fuel gauge block diagram and external connection ........................................................................... 66 Figure 3-8. BIF application diagram ...................................................................................................................... 67 Figure 4-1. Configuration for unused DC/DC .................................................................................................... 1064 Figure 5-1. Package dimension ......................................................................................................................... 1065

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MT6359 PMIC Datasheet Confidential A Lists of Tables Table 1-1. MT6359 pin description........................................................................................................................ 13 Table 2-1. Absolute maximum ratings .................................................................................................................. 18 Table 2-2. Pin voltage range ................................................................................................................................. 20 Table 2-3. Operation condition ............................................................................................................................. 24 Table 2-4. General electrical specification ............................................................................................................ 25 Table 2-5. Buck specifications ............................................................................................................................... 26 Table 2-6. LDO specifications ................................................................................................................................ 35 Table 2-7. Vibrator specification ........................................................................................................................... 39 Table 2-8. Audio downlink specifications .............................................................................................................. 40 Table 2-9. Audio uplink specifications .................................................................................................................. 43 Table 2-10. MICBIAS specifications ....................................................................................................................... 45 Table 2-11. ACCDET specifications ........................................................................................................................ 45 Table 2-12. Charger-in specifications .................................................................................................................... 46 Table 2-13. AUXADC specifications ....................................................................................................................... 47 Table 2-14. BATADC specifications ........................................................................................................................ 47 Table 2-15. Fuel gauge specifications ................................................................................................................... 48 Table 2-16. BIF specifications ................................................................................................................................ 49 Table 2-17. XO specifications ................................................................................................................................ 50 Table 2-18. Reference input buffer specifications (XTAL1, buffer mode) .............................................................. 50 Table 2-19. RF clock output buffer specifications (XO_CEL, XO_WCN) ................................................................. 50 Table 2-20. BB clock output buffer specifications (XO_NFC, XO_EXT, XO_SOC) ................................................... 51 Table 3-1. Buck converter brief specifications ...................................................................................................... 59 Table 3-2. LDO types and brief specifications ....................................................................................................... 61 Table 3-3. Application and input range of ADC channels ...................................................................................... 65 Table 3-4. MT6359 GPIO list ................................................................................................................................. 71 Table 3-5. MT6359 GPIO electrical characteristics ............................................................................................... 72

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MT6359 PMIC Datasheet Confidential A

1

Overview stay alive without a battery for several hours.

1.1

Features

 Handles smart phone baseband power management

MT6359 adopts SPI interface and two SRCLKEN control pins to control buck converters, LDOs, and various drivers; it provides enhanced safety control

 Input range: 2.6~5V  9 buck converters and 33 LDOs optimized for specific smart phone subsystems  Full-set high-quality audio feature: Supports uplink/downlink audio CODEC.  32K-Crystal-less RTC oscillator for system

and protocol for handshaking with baseband. MT6359 is available in a 203-pin WLCSP package. The operating temperature ranges from -30°C to +85°C.

timing, 1.8 clock buffer output  SPI interface  Over-current and thermal overload protection  Programmable under voltage lockout protection  Watchdog reset  Flexibility hardware PMIC reset function  Power-on reset and start-up timer  Precision voltage, temperature, and current measurement fuel gauge  Storage card plug-out protection  203-pin WLCSP package

1.2

Applications

MT6359 is ideal for power management of smart phones and other portable systems.

1.3

General Description

MT6359 is a power management system chip optimized for handsets and smart phones, containing 9 buck converters and 33 LDOs optimized for spe Sophisticated controls are available for power-up and the RTC alarm. MT6359 is optimized for maximum battery life, allowing the RTC circuit to

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MT6359 PMIC Datasheet Confidential A

1.4

Ordering Information

Group A: Order # MT6359P/A MT6359KP/A MT6359VP/A MT6359VKP/A Group B: Order # MT6359VPP/B MT6359VMP/B MT6359VUP/B MT6359UP/B MT6359VNP/B MT6359NP/B

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Marking

Temp. range -30 ~ +85°C -30 ~ +85°C -30 ~ +85°C -30 ~ +85°C

Package WLCSP 203 pins WLCSP 203 pins WLCSP 203 pins WLCSP 203 pins

Marking

Temp. range -30 ~ +85°C -30 ~ +85°C -30 ~ +85°C -30 ~ +85°C -30 ~ +85°C -30 ~ +85°C

Package WLCSP 203 pins WLCSP 203 pins WLCSP 203 pins WLCSP 203 pins WLCSP 203 pins WLCSP 203 pins

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MT6359 PMIC Datasheet Confidential A

1.5

Top Marking Definition

Group A: MT6359P/A

MT6359KP/A

MT6359VP/A

MT6359VKP/A

Group B: MT6359VPP/B

MT6359VMP/B

MT6359VUP/B

MT6359UP/B

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MT6359 PMIC Datasheet Confidential A MT6359VNP/B

MT6359NP/B

YYWW: Date code $: Random code

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MT6359 PMIC Datasheet Confidential A

1.6

Main Differences between Group A and Group B BUCK name

VPROC1

VPROC2

VGPU11 + VGPU12

VCORE

VMODEM

VPU

LDO name

VA09

Part number MT6359VP/A MT6359VPP/B MT6359VMP/B MT6359VUP/B MT6359VNP/B MT6359VP/A MT6359VPP/B MT6359VMP/B MT6359VUP/B MT6359VNP/B MT6359VP/A MT6359VPP/B MT6359VMP/B MT6359VUP/B MT6359VNP/B MT6359VP/A MT6359PVPP/B MT6359VMP/B MT6359VUP/B MT6359VNP/B MT6359VP/A MT6359VPP/B MT6359VMP/B MT6359VNP/B MT6359VUP/B MT6359VP/A MT6359VPP/B MT6359VMP/B MT6359VUP/B MT6359VNP/B Part Number MT6359VP/A MT6359VPP/B MT6359VMP/B MT6359VUP/B MT6359VNP/B MT6359VPP/B

VRFCK

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MT6359VUP/B MT6359VNP/B MT6359VMP/B

Default voltage (V) 0.8 0.75 0.75

Default on (Y/N) Processor Y Y

0.8 0.75

Application

VPU GPU Processor

Y

DLA VPU Processor GPU

0.75

Y

0.55 0.725 0.75

Y

0.75

Y

Processor

0.8

Y

Digital core always on

1.3

N

RF

0.75

Y

Digital core always on

0.85

Y

Modem

0.9

N

RF

0.75 0.55

Y

Processor VPU

0.7 Default voltage (V) 0.8 0.85

Y

Digital core always on

RF DIG

Default on (Y/N)

Application

Y

AP

Y

MT6359VPP/B internal use (DCXO)

1.24 1.4

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MT6359 PMIC Datasheet Confidential A VRFCK_1

VEMC

VSRAM_PROC1

VSRAM_PROC2

VSRAM_OTHERS

VSRAM_MD

MT6359VP/A MT6359VP/A MT6359VMP/B MT6359VUP/B MT6359VNP/B MT6359VPP/B MT6359VP/A MT6359VPP/B MT6359VMP/B MT6359VUP/B MT6359VNP/B MT6359VP/A MT6359VMP/B MT6359VPP/B MT6359VUP/B MT6359VNP/B MT6359VP/A MT6359VPP/B MT6359VMP/B MT6359VUP/B MT6359VNP/B MT6359VP/A MT6359VPP/B MT6359VMP/B MT6359VUP/B MT6359VNP/B

1.6

3

N

MT6359VP/A internal use (DCXO)

Y

eMMC and UFS

Y

SRAM

Y

SRAM

Y

SRAM

Y

SRAM

Y

SRAM

2.55 0.9 0.85

0.9 0.85 0.9 0.85 0.75 0.9 0.85

Note: MT6359VP/A stands for Group A.

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put voltage

MT6359 PMIC Datasheet Confidential A

1.7

Pin Assignments and Description

Figure 1-1. MT6359 WLCSP 203 (5.65 x 5.29 mm) pin assignment (top view)

Table 1-1. MT6359 pin description Balls N8 R7 N9 R10 R11 R9 P8 R8 M10 N10 P7 N8 N11 R13 N13 R15 P11 R14 R12 C3 B2

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Symbol VAUX18 VBIF28 VFE28 VCN33_1 VCN33_2 VEMC VSIM1 VSIM2 VIBR VIO28 VUSB VAUD18 VCAMIO VCN18 VEFUSE VIO18 VM18 VUFS VA09 VA12

I/O O O O O O O O O O O O O O O O O O O O O

Description VAUX18 output voltage VBIF28 output voltage VFE28 output voltage VCN33_1 output voltage VCN33_2 output voltage VEMC33 output voltage VSIM1 output voltage VSIM2 output voltage VIBR output voltage VIO28 output voltage VUSB output voltage VAUD18 output voltage VCAMIO output voltage VCN18 output voltage VEFUSE output voltage VIO18 output voltage VM18 output voltage VUFS output voltage VA09 output voltage VA12 output voltage

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MT6359 PMIC Datasheet Confidential A

C1 A2 B1 D3 E2 D4 D1 P12 P13 D2 C2 P10 P9 K4 H4 G3 J3 J4 F4 F3 L5 M4 M5 G4 L2 L1 N2 M2 N3 M3 L3 L4 K3 E1 H2 K1 J1 G2 J2 F1 G1

Balls

Symbol VCN13 VRF12 VRF12_S VSRAM_PROC1 VSRAM_PROC2 VSRAM_OTHERS VSRAM_MD VS1_LDO1 VS1_LDO2 VS2_LDO1 VS2_LDO2 VSYS_LDO1 VSYS_LDO2 ACCDET AU_HPL AU_HPR AU_HSN AU_HSP AU_LOLN AU_LOLP AU_MICBIAS0 AU_MICBIAS1 AU_MICBIAS2 AU_REFN AU_VIN0_N AU_VIN0_P AU_VIN1_N AU_VIN1_P AU_VIN2_N AU_VIN2_P AU_VIN3_N AU_VIN3_P HP_EINT AU_V18N AVDD18_AUD AVDD18_CODEC AVDD30_AUD AVSS18_AUD AVSS30_AUD FLYN FLYP

L7

BATADC_P

M8 L8

AUXADC_VIN1 AVSS18_AUXADC

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I/O O O I O O O O PWR PWR PWR PWR PWR PWR I O O O O O O O O O GND I I I I I I I I I PWR PWR PWR PWR GND GND O O I I GND

Description VCN13 output voltage VRF12 output voltage LDO VRF12 feedback pin VSRAM_PROC1 output voltage VSRAM_PROC2 output voltage VSRAM_OTHERS output voltage VSRAM_MD output voltage 2V power supply of SLDO1 2V power supply of SLDO1 1.35V power supply of SLDO2 1.35V power supply of SLDO2 Power supply input of LDO group 1 Power supply input of LDO group 2 Accessory detection input Earphone left channel output Earphone right channel output Handset negative output Handset positive output Lineout negative output Lineout positive output Microphone bias 0 Microphone bias 1 Microphone bias 2 Audio reference ground Microphone channel 0 negative input Microphone channel 0 positive input Microphone channel 1 negative input Microphone channel 1 positive input Microphone channel 2 negative input Microphone channel 2 positive input Microphone channel 3 negative input Microphone channel 3 positive input HPL detection Audio -1.8V supply 1.8V power supply of audio 1.8V power supply of CODEC Power supply of audio UL Audio DL ground Audio UL ground Flying capacitor bottom Flying capacitor top AUXADC + input pin for monitoring battery voltage AUXADC input 1 (GPS CO-CLK) AUXADC ground

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MT6359 PMIC Datasheet Confidential A

Balls C6 C4 K15, K16 K14 L15, L16 M14 M15, M16 A14, B14 C12 A13, B13 C14 A12, B12 B7 C8 A8, B8 C9 A7 A9, B9 C10 A10, B10 C11 A11, B11 B5 A6, B6 C7 A5 P15 N15, N16 P14 P16 B4 A3, B3 C5 A4 C15, C16 D14 B15, B16 F14 A15, A16 J15, J16 nse on ground of VGPU11 J14 H15, H16 f VGPU11 G14 G15, G16 D15, D16

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Symbol GND_SMPS VSYS_SMPS GND_VCORE GND_VCORE_FB VCORE VCORE_FB VSYS_VCORE GND_VPROC2 GND_VPROC2_FB VPROC2 VPROC2_FB VSYS_VPROC2 GND_VPU GND_VPU_FB VPU VPU_FB VSYS_VPU GND_VMODEM GND_VMODEM_FB VMODEM VMODEM_FB VSYS_VMODEM GND_VPA VPA VPA_FB VSYS_VPA GND_VS1 VS1 VS1_FB VSYS_VS1 GND_VS2 VS2 VS2_FB VSYS_VS2 GND_VPROC1 GND_VPROC1_FB VPROC1 VPROC1_FB VSYS_VPROC1 GND_VGPU11

I/O GND PWR GND I O I PWR GND I O I PWR GND I O I PWR GND I O I PWR GND O I PWR GND O I PWR GND O I PWR GND I O I PWR GND

Description GND of buck controller Power supply of buck controller Ground of CORE Remote sense on ground of VCORE SW node of VCORE BUCK VCORE feedback pin on Vout Power supply of VCORE Ground of VPROC2 Remote sense on ground of VPROC2 SW node of VPROC2 BUCK VPROC2 feedback pin on Vout Power supply of VPROC2 Ground of VPU Remote sense on ground of VPU SW node of VPU BUCK VPU feedback pin on Vout Power supply of VPU Ground of VMODEM Remote sense on ground of VMODEM SW node of VMODEM BUCK VMODEM feedback pin on Vout Power supply of VMODEM Ground of VPA SW node of VPA BUCK VPA feedback pin on Vout Power supply of VPA Ground of VS1 SW node of VS1 BUCK VS1 feedback pin on Vout Power supply of VS1 Ground of VS2 SW node of VS2 BUCK VS2 feedback pin on Vout Power supply of VS2 Ground of VPROC1 Remote sense on ground of VPROC1 SW node of VPROC1 BUCK VPROC1 feedback pin on Vout Power supply of VPROC1 Ground of VGPU11

VGPU11_FB VSYS_VGPU11 GND_VGPU12

I PWR GND

BUCK VGPU11 feedback pin on Vout Power supply of VGPU11 Ground of VGPU12

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button

MT6359 PMIC Datasheet Confidential A Balls E15, E16 F15, F16 P2, R1 N1 N4 N5 R3 R4 P3 P5 P4 P6 R6 R5 M6 P1 R2 F6 H7 H6 G7 J7 J6 K6 K7 G6 F7 K10 K11 J11 G12 H12 J12 E11 E12 E13 F12 H13 G13

Symbol VGPU12 VSYS_VGPU12 AVSS_XO AVSS_XO_ISO AVSS_RFCK AVSS_BBCK VXO22 VRFCK VRFCK_1 VBBCK XO_CEL XO_EXT XO_NFC XO_SOC XO_WCN XTAL1 XTAL2 AUD_NLE_MOSI0 AUD_CLK_MOSI AUD_DAT_MISO0 AUD_DAT_MISO1 AUD_DAT_MISO2 AUD_DAT_MOSI0 AUD_DAT_MOSI1 AUD_DAT_MOSI2 AUD_NLE_MOSI1 AUD_SYNC_MOSI DVDD18_DIG DVDD18_IO DVSS18_IO FSOURCE RTC32K_1V8_0 RTC32K_1V8_1 SPI_CLK SPI_CSN SPI_MISO SPI_MOSI SRCLKEN_IN0 SRCLKEN_IN1

K12

SCP_VREQ_VAO

I

D13 J13 L10 L9

WDTRSTB_IN CS_N CS_P

I I I

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I/O O PWR GND GND GND GND O O O O O O O O O I/O I/O I I O O O I I I I I PWR PWR GND PWR O O I I/O I/O I/O I I

Description SW node of VGPU12 Power supply of VGPU12 Ground for XO Connect to GSUB for DCXO noise isolation Ground for RF clock buffer Ground for baseband clock buffer VXO22 output voltage RF clock buffer power source RF clock buffer power source Baseband clock buffer power source RF clock buffer output to Cell. RF Baseband clock buffer output to UFS Baseband clock buffer output to NFC Baseband clock buffer output to SOC RF clock buffer output to Conn. RF XTAL input 1 XTAL input 2 Audio control interface Audio control interface Audio control interface Audio control interface Audio control interface Audio control interface Audio control interface Audio control interface Audio control interface Audio control interface VDIG18 output voltage Digital IO power Digital IO power GND EFUSE power source VIO18 domain 32 kHz clock output VIO18 domain 32 kHz clock output SPI control interface SPI control interface SPI control interface SPI control interface Source clock enable pin 0 Source clock enable pin 1 Voltage source request input pin, connected to SOC Watchdog reset from AP Fuel gauge ADC input pin Fuel gauge ADC input pin

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MT6359 PMIC Datasheet Confidential A

D7 D6 D5 D10

Balls

Symbol EXT_PMIC_EN1 EXT_PMIC_EN2 EXT_PMIC_PG CHRDETB

D11

PMU_TESTMODE

I

D8 E3

PWRKEY RESETB

I O

M12

BATON

I

L11 M13 L12

GND_VREF UVLO_VTH VREF

M11

VSYSSNS

I

L13

VRTC28

O

D_GND

GND

DUMMY

NC

E6, E7, E8, E9, E10, F8, F9, F10, G8, G9, G10 A1, R16

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I/O O O I I

GND I O

Description Ext PMIC enable pin 1 Ext PMIC enable pin 2 Ext PMIC power-good pin Charger detection signal from sub PMIC PMU test mode signal (tied to GND in normal operation) PWRKEY button System reset release signal Battery NTC pin for battery and its temperature sensing Ground for bandgap UVLO threshold control pin Bandgap reference voltage VSYS supply input for internal block and UVLO detection RTC LDO output. Supply of RTC macro where backup battery can be added. Ground NC

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MT6359 PMIC Datasheet Confidential A

2 2.1

Electrical Characteristics Absolute Maximum Ratings over Operating Free-Air Temperature Range

Stresses beyond those listed in Table 2-1 may cause permanent damage to the device. These numbers are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect the device reliability.

Table 2-1. Absolute maximum ratings Parameter Free-air temperature range Storage temperature range Battery pin input (1) Non-battery power pin (2) Signal pins (3) ESD robustness

Conditions

Steady state Transient (< 10 ms) Steady state Steady state HBM

Min. -40 -65 -0.5 -0.5 -0.5 -0.5 2,000

Typical

Max. 85 150 6 7 5 Vxx+0.5(3)

Unit °C °C V V V V V

Note: 1. VSYS_XXX/Vxxx (BUCK SW node)/VSYSSNS/BATADC -> battery input pin 2. Non-battery power input -> reference Table 2-1 (PWR pin but not connected with battery) 3. Vxx = Max. operation voltage (refer to Table 2-2)

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Page 18 of 1067

MT6359 PMIC Datasheet Confidential A

2.2

Thermal Characteristics

Parameter Thermal resistance from junction to ambient

Conditions In free air

Min.

Typical

Max.

38.6

Unit °C/W

Note: The device is mounted on an 8-metal-layer PCB and modeled per JEDEC51-9 condition.

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Page 19 of 1067

~ +2.1

MT6359 PMIC Datasheet Confidential A

2.3

Pin Voltage Range

The table below lists the operation rang voltages for all MT6359 I/O pins.

Table 2-2. Pin voltage range Balls N8 R7 N9 R10 R11 R9 P8 R8 M10 N10 P7 N12 N11 R13 N13 R15 P11 R14 R12 C3 B2 C1 A2 B1 D3 E2 D4 D1 P12 P13 D2 C2 P10 P9 K4 H4 G3 J3 J4

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Symbol VAUX18 VBIF28 VFE28 VCN33_1 VCN33_2 VEMC VSIM1 VSIM2 VIBR VIO28 VUSB VAUD18 VCAMIO VCN18 VEFUSE VIO18 VM18 VRF18 VUFS VA09 VA12 VCN13 VRF12 VRF12_S VSRAM_PROC1 VSRAM_PROC2 VSRAM_OTHERS VSRAM_MD VS1_LDO1 VS1_LDO2 VS2_LDO1 VS2_LDO2 VSYS_LDO1 VSYS_LDO2 ACCDET

Voltage Range 0 ~ 1.98 0~5 0~5 0~5 0~5 0~5 0~5 0~5 0~5 0~5 0~5 0 ~ 2.2 0 ~ 2.2 0 ~ 2.2 0 ~ 2.2 0 ~ 2.2 0 ~ 2.2 0 ~ 2.2 0 ~ 2.2 0 ~ 2.2 0 ~ 2.2 0 ~ 2.2 0 ~ 2.2 0 ~ 2.2 0 ~ 1.4 0 ~ 1.4 0 ~ 1.4 0 ~ 1.4 0 ~ 2.2 0 ~ 2.2 0 ~ 2.2 0 ~ 2.2 0~5 0~5 0 ~ 3.3

AU_HPR AU_HSN AU_HSP

-2.1 ~ +2.1 -2.1 ~ +2.1 -2.1 ~ +2.1

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Unit V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V

Page 20 of 1067

MT6359 PMIC Datasheet Confidential A Balls F4 F3 L5 M4 M5 G4 L2 L1 N2 M2 N3 M3 L3 L4 K3 E1 H2 K1 J1 G2 J2 F1 G1 L7 M8 L8 C6 C4 K15, K16 K14 L15, L16 M14 M15, M16 A14, B14 C12 A13, B13 C14 A12, B12 B7 C8 A8, B8 C9 A7 A9, B9 C10

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Symbol AU_LOLN AU_LOLP AU_MICBIAS0 AU_MICBIAS1 AU_MICBIAS2 AU_REFN AU_VIN0_N AU_VIN0_P AU_VIN1_N AU_VIN1_P AU_VIN2_N AU_VIN2_P AU_VIN3_N AU_VIN3_P HP_EINT AU_V18N AVDD18_AUD AVDD18_CODEC AVDD30_AUD AVSS18_AUD AVSS30_AUD FLYN FLYP BATADC_P AUXADC_VIN1 AVSS18_AUXADC GND_SMPS VSYS_SMPS GND_VCORE GND_VCORE_FB VCORE VCORE_FB VSYS_VCORE GND_VPROC2 GND_VPROC2_FB VPROC2 VPROC2_FB VSYS_VPROC2 GND_VPU GND_VPU_FB

Voltage Range -2.1 ~ +2.1 -2.1 ~ +2.1 0 ~ 3.3 0 ~ 3.3 0 ~ 3.3 0 0 ~ 3.3 0 ~ 3.3 0 ~ 3.3 0 ~ 3.3 0 ~ 3.3 0 ~ 3.3 0 ~ 3.3 0 ~ 3.3 -2.1 ~ 3.3 -2.1 ~ 0 0 ~ 2.1 0 ~ 1.98 0 ~ 3.3 0 0 -2.1 ~ 0 0 ~ 2.1 0~5 0 ~ 1.84 0 0 0~5 0 0 0~5 0~5 0~5 0 0 0~5 0~5 0~5 0 0

VSYS_VPU GND_VMODEM GND_VMODEM_FB

0~5 0 0

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Unit V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V

Page 21 of 1067

76 ~ 2.2

MT6359 PMIC Datasheet Confidential A Balls A10, B10 C11 A11, B11 B5 A6, B6 C7 A5 P15 N15, N16 P14 P16 B4 A3, B3 C5 A4 C15, C16 D14 B15, B16 F14 A15, A16 J15, J16 J14 H15, H16 G14 G15, G16 D15, D16 E15, E16 F15, F16 P2, R1 N1 N4 N5 R3 R4 P3 P5 P4 P6 R6 R5 M6 P1 R2 F6 H7

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Symbol VMODEM VMODEM_FB VSYS_VMODEM GND_VPA VPA VPA_FB VSYS_VPA GND_VS1 VS1 VS1_FB VSYS_VS1 GND_VS2 VS2 VS2_FB VSYS_VS2 GND_VPROC1 GND_VPROC1_FB VPROC1 VPROC1_FB VSYS_VPROC1 GND_VGPU11 GND_VGPU11_FB VGPU11 VGPU11_FB VSYS_VGPU11 GND_VGPU12 VGPU12 VSYS_VGPU12 AVSS_XO AVSS_XO_ISO AVSS_RFCK AVSS_BBCK VXO22 VRFCK VRFCK_1 VBBCK XO_CEL XO_EXT XO_NFC XO_SOC

Voltage Range 0~5 0~5 0~5 0 0~5 0~5 0~5 0 0~5 0~5 0~5 0 0~5 0~5 0~5 0 0 0~5 0~5 0~5 0 0 0~5 0~5 0~5 0 0~5 0~5 0 0 0 0 0 ~ 2.42 0 ~ 1.76 0 ~ 1.76 0 ~ 1.32 0 ~ 1.76 0 ~ 1.32 0 ~ 1.32 0 ~ 1.32

XTAL2 AUD_NLE_MOSI0 AUD_CLK_MOSI

0.2 ~ 1.7 0 ~ 1.98 0 ~ 1.98

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Unit V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V

Page 22 of 1067

MT6359 PMIC Datasheet Confidential A

H6 G7 J7 J6 K6 K7 G6 F7 K10 K11 J11 G12 H12 J12 E11 E12 E13 F12 H13 G13 K12 D13 J13 L10 L9 D7 D6 D5 D10 D11 D8 E3 M12 L11 M13 L12

Balls

Symbol AUD_DAT_MISO0 AUD_DAT_MISO1 AUD_DAT_MISO2 AUD_DAT_MOSI0 AUD_DAT_MOSI1 AUD_DAT_MOSI2 AUD_NLE_MOSI1 AUD_SYNC_MOSI DVDD18_DIG DVDD18_IO DVSS18_IO FSOURCE RTC32K_1V8_0 RTC32K_1V8_1 SPI_CLK SPI_CSN SPI_MISO SPI_MOSI SRCLKEN_IN0 SRCLKEN_IN1 SCP_VREQ_VAO HOMEKEY WDTRSTB_IN CS_N CS_P EXT_PMIC_EN1 EXT_PMIC_EN2 EXT_PMIC_PG CHRDETB PMU_TESTMODE PWRKEY RESETB BATON GND_VREF UVLO_VTH VREF

Voltage Range 0 ~ 1.98 0 ~ 1.98 0 ~ 1.98 0 ~ 1.98 0 ~ 1.98 0 ~ 1.98 0 ~ 1.98 0 ~ 1.98 0 ~ 1.98 0 ~ 1.98 0 0 ~ 1.98 0 ~ 1.98 0 ~ 1.98 0 ~ 1.98 0 ~ 1.98 0 ~ 1.98 0 ~ 1.98 0 ~ 1.98 0 ~ 1.98 0 ~ 1.98 0 ~ 1.98 0 ~ 1.98 -0.1 ~ 1.8 -0.1 ~ 1.8 0~5 0~5 0~5 0~5 0~5

M11

VSYSSNS

0~5

V

L13 E6, E7, E8, E9, E10, F8, F9, F10, G8, G9, G10 A1, R16

VRTC28

0 ~ 2.98

V

D_GND

0

V

MediaTek Proprietary and Confidential.

0~5 0 ~ 1.98 0 ~ 3.08 0 0 ~ 3.3 0 ~ 1.32

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Unit V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V

V

Page 23 of 1067

MT6359 PMIC Datasheet Confidential A

2.4

Recommended Operating Range Table 2-3. Operation condition

Parameter Ambient temperature (TA) Junction temperature (TJ) Operating input voltage

Conditions

Min. -30 -30 3.15 (note)

Typical

Max. 85 125 5

Unit °C °C V

Note: This minimum input voltage still needs to check the detailed test conditions for each function in specification table.

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Page 24 of 1067

MT6359 PMIC Datasheet Confidential A

2.5

Electrical Characteristics

 VBAT = 2.6~5V, minimum loads applied on all outputs, unless otherwise noted.  Typical values are at TA = 25°C.

Table 2-4. General electrical specification Parameter Operation Ground Current Standby without 32K XTAL Power down leakage current without 32K XTAL Under Voltage Lock-out (UVLO) Under voltage falling threshold Under voltage rising threshold Over Voltage Lock-out (OVLO) Over voltage falling threshold Over voltage rising threshold Reset Generator Output high Output low PWRKEY High voltage Low voltage

Min.

VBAT = 4V, low-power mode VBAT = 4V Temp = 25°C

R = 200K

Typical

Max.

Unit

510

665

μA

85

uA

2.55 2.95

2.6 3.0

2.65 3.05

V V

5.1 5.5

5.2 5.6

5.3 5.7

V V

VIO - 0.4

V 0.2

V

0.3

V V

1.45

De-bounce time Control Input Voltage Control input high (SPI, SRCLKEN related) Control input low (SPI, SRCLKEN related) Thermal Shut-down PMIC shut-down threshold Shut-down release threshold

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Conditions

32

ms

0.75*VIO

V 0.25*VIO

150 110

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V

°C °C

Page 25 of 1067

MT6359 PMIC Datasheet Confidential A

2.6

Regulator Output Table 2-5. Buck specifications

L = 0.47 uH (Typ.), COUT = 88 uF (Typ.), VOUT = 0.8V, VBAT = 3.1~5.0V, TA = -40~85°C, Typ. values at VBAT = 3.8V, TA = 25°C unless otherwise specified Buck - VPROC1 Parameter Conditions Min. Typical Turn-on overshoot No load OCP (over-current Peak Inductor current 5.8 protection) Soft start No load Load > 2A 2.52 2.8 Switching frequency L = 0.24 uH, COUT = 44/88 uF 1.89 2.1 L = 0.47 uH, COUT = 66 uF Load = 0.5*Imax Output ripple voltage (CCM) 20 MHz measurement BW Load = 0A Output ripple voltage (PFM) 20 MHz measurement BW Load = 1,360~3,260 mA 5.65%*VOUT Load transient (Tr/Tf = 1 us) +11 mV VBAT = 4.3~5V 5.65%*VOUT Line transient Load = 0.5*Imax +11 mV (Tr/Tf = 15 us) DC accuracy -6 (includes line/load regulation, CCM load) DC accuracy -6 (includes line/load regulation, PFM load) Output discharge switch on resistance L = 0.47 uH (Typ.), COUT = 88 uF (Typ.), VOUT = 0.8V, VBAT = 3.1~5.0V, TA = -40~85°C, Typ. values at VBAT = 3.8V, TA = 25°C unless otherwise specified Buck - VPROC2 Parameter Conditions Min. Typical Turn-on overshoot No load OCP (over-current Peak Inductor current 5.8 protection) Soft start No load Load > 0.8A 2.52 2.8 Switching frequency L = 0.24 uH, COUT = 44/88 uF 1.89 2.1 L = 0.47 uH, COUT = 66 uF Load = 0.5*Imax Output ripple voltage (CCM) 20 MHz measurement BW Load = 0A Output ripple voltage

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Max. 10

Unit %

8.5

A

1,000

us

3.08 2.31

MHz

10

mVpp

45

mVpp

+7.4%*VO UT -11 mV +7.4%*VO UT -11 mV

%

%

6

mV

28.5

mV

90

Ω

Max. 10

Unit %

8.5

A

1000

us

3.08 2.31

MHz

10

mVpp

43.1

mVpp

Page 26 of 1067

MT6359 PMIC Datasheet Confidential A Buck - VPROC2 Parameter (PFM) Load transient Line transient DC accuracy (includes line/load regulation, CCM load) DC accuracy (includes line/load regulation, PFM load) Output discharge switch on resistance

Conditions 20 MHz measurement BW Load = 10~880 mA (Tr/Tf = 1 us) VBAT = 4.3~5V Load = 0.5*Imax (Tr/Tf = 15 us)

Min.

Typical

Max.

Unit

-5.65%*VOUT +11 mV

+7.4%*VOUT -11 mV

%

-5.65%*VOUT +11 mV

+7.4%*VOUT -11 mV

%

-6

+6

mV

-6

28.5

mV

90

Ω

L = 0.47 uH (Typ.), COUT = 66 uF (Typ.), VOUT = 0.8V, VBAT = 3.1~5.0V, TA = -40~85°C, Typ. values at VBAT = 3.8V, TA = 25°C unless otherwise specified Buck - VGPU Parameter Conditions Min. Typical Max. Turn-on overshoot No load 10 OCP (over-current Peak Inductor current 9.6 12 protection) Soft start No load 1,000 Load > 0.8A 2.34 2.6 2.86 Switching frequency L = 0.24 uH, COUT = 88 uF 2.16 2.4 2.64 L = 0.47 uH, COUT = 66 uF Load = 0.5*Imax Output ripple voltage 10 (CCM) 20 MHz measurement BW Load = 0A Output ripple voltage 45 (PFM) 20 MHz measurement BW Load = 1,400~4,100 mA -5.65%*VOUT +7.4%*VOUT Load transient +11 mV -11 mV (Tr/Tf = 1 us) VBAT = 4.3~5V -5.65%*VOUT +7.4%*VOUT Line transient Load = 0.5*Imax +11 mV -11 mV (Tr/Tf = 15 us) DC accuracy -6 6 (includes line/load regulation, CCM load) DC accuracy -6 28.5 (includes line/load regulation, PFM load) Output discharge 70 switch on resistance

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Unit % A us MHz mVpp mVpp % %

mV

mV Ω

Page 27 of 1067

MT6359 PMIC Datasheet Confidential A L = 0.47 uH (Typ.), COUT = 44 uF (Typ.), VOUT = 0.85V, VBAT = 3.1~5.0V, TA = -40~85°C, Typ. values at VBAT = 3.8V, TA=25°C unless otherwise specified Buck - VCORE Parameter Conditions Min. Typical Turn-on overshoot No load OCP (over-current Peak Inductor current 5.8 protection) Soft start

Switching frequency Output ripple voltage (CCM) Output ripple voltage (PFM) Load transient Line transient

Max. 10

Unit %

8.5

A

1,000

us

3.08 2.31 3.08

MHz

10

mVpp

45

mVpp

-5.65%*VOUT +11 mV

+7.4%*VOUT -11 mV

%

-5.65%*VOUT +11 mV

+7.4%*VOUT -11 mV

%

-6

6

mV

-6

28.5

mV

90

Ω

Max. 10

Unit %

8.2

A

900

us

3.08 2.31 3.08

MHz

10

mVpp

45

mVpp

No load Load > 0.8A, L = 0.24 uH, COUT = 88 uF L = 0.47 uH, COUT = 44 uF L = 1 uH, COUT = 22 uF Load = 0.5*Imax 20MHz measurement BW Load = 0A 20 MHz measurement BW Load = 1,000~3,500 mA (Tr/Tf = 1 us) VBAT = 4.3~5V Load = 0.5*Imax (Tr/Tf = 15 us)

DC accuracy (includes line/load regulation, CCM load) DC accuracy (includes line/load regulation, PFM load) Output discharge switch on resistance

2.52 1.89 2.52

2.8 2.1 2.8

L = 0.47 uH (Typ.), COUT = 44 uF (Typ.), VOUT = 0.85V, VBAT = 3.1~5.0V, TA = -40~85°C, Typ. values at VBAT = 3.8V, TA = 25°C unless otherwise specified Buck - VMODEM Parameter Conditions Min. Typical Turn-on overshoot No load OCP (over-current Peak Inductor current 5.8 protection) Soft start No load Load > 0.8A, 2.52 2.8 L = 0.24 uH, COUT = 66 uF Switching frequency 1.89 2.1 L = 0.47 uH, COUT = 44 uF 2.52 2.8 L = 1 uH, COUT = 22 uF Load = 0.5*Imax Output ripple voltage 5 (CCM) 20 MHz measurement BW Load = 0A Output ripple voltage (PFM) 20 MHz measurement BW Load transient

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Load = 35~1,537 mA

-5.65% +11 mV

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+7.4% -11 mV

Page 28 of 1067

MT6359 PMIC Datasheet Confidential A Buck - VMODEM Parameter

Line transient DC accuracy (includes line/load regulation, CCM load) DC accuracy (includes line/load regulation, PFM load) Output discharge switch on resistance

Conditions (Tr/Tf = 1 us) VBAT = 3.8~4.5V Load = 0.5*Imax (Tr/Tf = 15 us)

Min.

Typical

Max.

Unit

-5.65% +11 mV

+7.4% -11 mV

-6

+6

mV

-6

+28.5

mV

150

Ω

L = 0.47 uH (Typ.), COUT = 44 uF (Typ.), VOUT = 0.8V, VBAT = 3.1~5.0V, TA = -40~85°C, Typ. values at VBAT = 3.8V, TA = 25°C unless otherwise specified Buck - VPU Parameter Conditions Min. Typical Max. Turn-on overshoot No load 10 OCP (over-current Peak Inductor current 2.8 4.6 protection) Soft start No load 200 Load > 0.8A, Switching frequency L = 0.47 uH, COUT = 44 uF 1.89 2.1 2.31 L = 1 uH, COUT = 22 uF 2.52 2.8 3.08 Load = 0.5*Imax Output ripple voltage 5 10 (CCM) 20 MHz measurement BW Load = 0A Output ripple voltage 45 (PFM) 20 MHz measurement BW Load = 10~1,310 mA Load transient -5.65% +11 mV +7.4% -11 mV (Tr/Tf=1 us) VBAT=3.8~4.5V Line transient Load = 0.5*Imax -5.65% +11 mV +7.4% -11 mV (Tr/Tf = 15 us) DC accuracy -6 +6 (includes line/load regulation, CCM load) DC accuracy -6 +28.5 (includes line/load regulation, PFM load) Output discharge 300 switch on resistance

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Unit % A us MHz mVpp mVpp

mV

mV Ω

Page 29 of 1067

MT6359 PMIC Datasheet Confidential A L = 1 uH (Typ.), COUT = 44 uF (Typ.), VOUT = 2.0V, VBAT = 3.1~5.0V, TA = -40~85°C, Typ. values at VBAT = 3.8V, TA = 25°C unless otherwise specified Buck - VS1 Parameter Conditions Min. Typical Turn-on overshoot No load OCP (over-current Peak Inductor current 2.5 protection) Soft start No load Switching frequency Load > 0.8A 1.8 2 Load = 0.5*Imax Output ripple voltage (CCM) 20 MHz measurement BW Load = 0A Output ripple voltage (PFM) 20 MHz measurement BW Load = 20~1,200mA Load transient -3.8 (Tr/Tf = 10 us) VBAT = 4.3~5V Line transient Load = 0.5*Imax -3.8 (Tr/Tf = 15 us) DC accuracy -0.9 (includes line/load regulation, CCM load) DC accuracy -0.9 (includes line/load regulation, PFM load) Output discharge switch on resistance

Max. 70

Unit mV

4.2

A

1,000 2.2

us MHz

0.6

%

50

mVpp

3.8

%

3.8

%

+0.9

%

+3.5

%

100

Ω

Max. 70

Unit mV

4.5

A

1,000 2.2

us MHz

0.6

%

50

mVpp

-3.8

3.8

%

-3.8

3.8

%

-0.9

+0.9

%

L = 1 uH (Typ.), COUT = 44 uF (Typ.), VOUT = 1.35V, VBAT = 3.1~5.0V, TA = -40~85°C, Typ. values at VBAT = 3.8V, TA = 25°C unless otherwise specified Buck - VS2 Parameter Turn-on overshoot OCP (over-current protection) Soft start Switching frequency Output ripple voltage (CCM) Output ripple voltage (PFM) Load transient Line transient DC accuracy (includes line/load

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Conditions

Min.

Typical

No load Peak Inductor current No load Load > 0.8A Load = 0.5*Imax 20 MHz measurement BW Load = 0A 20 MHz measurement BW Load = 20~1,200mA (Tr/Tf = 10 us) VBAT = 4.3~5V Load = 0.5*Imax (Tr/Tf = 15 us)

2.8 1.8

2

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Page 30 of 1067

MT6359 PMIC Datasheet Confidential A Buck - VS2 Parameter regulation, CCM load) DC accuracy (includes line/load regulation, PFM load) Output discharge switch on resistance

MediaTek Proprietary and Confidential.

Conditions

Min.

Typical

-0.9

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Max.

Unit

+3.5

%

100

Ω

Page 31 of 1067

MT6359 PMIC Datasheet Confidential A L = 1.0 uH (Typ.), COUT = 1 + 14 uF (Typ.), VBAT = 3.1~5.0V, TA = -40~85°C, Typ. values at VBAT = 3.8V, TA = 25°C unless otherwise specified Buck - VPA Parameter Turn-on overshoot OCP (over-current protection) Soft start Switching Frequency Output ripple voltage (PFM) Output ripple voltage (PWM) Output ripple voltage (Skip mode) Load transient

Line transient DC accuracy (includes line/load regulation, CCM load) DC accuracy (includes line/load regulation, PFM load) Output discharge switch on resistance

MediaTek Proprietary and Confidential.

Conditions VOUT = 3.4V No load VOUT = 3.4V Peak Inductor current VOUT = 0.5V/3.4V No load VOUT = 3.4V Load > 0.8A

Min.

Typical

Max.

Unit

10

%

3.2

A 300

us

2.2

MHz

20 MHz measurement BW

95

mVpp

20 MHz measurement BW

50

mVpp

70

mVpp

400

mV

200

mV

1.8

2

0.2V < VBAT - VOUT < 1V 20 MHz measurement BW Load = 50~800 mA (Tr/Tf = 1.6 us) VOUT = 1.7V VBAT = 3.8~4.5V Load = 200 mA (Tr/Tf = 15 us) VBAT - VOUT ≥ 600 mV VOUT ≥ 1V

-2

+2

%

VOUT = 0.5~1V

-20

+40

mV

VOUT ≥ 1V

-10

+60

mV

600

Ω

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Page 32 of 1067

MT6359 PMIC Datasheet Confidential A Efficiency with condition of VIN = 3.7V, TA = 25°C and in Auto-Mode are shown as below.

VOUT = 0.8V, L = 0.47 uH (DCR typ. 17 mohm), COUT = 22 uF*4

VOUT = 0.8V, L = 0.47 uH*2 (DCR typ. 17 mohm), COUT = 22 uF*2*2

Figure 2-1. VPROC1/VPROC2 efficiency

Figure 2-2. VGPU efficiency

VOUT = 0.8V, L = 0.47 uH (DCR typ. 17 mohm), COUT = 22 uF*2

VOUT = 1.3V, L = 1.0 uH (DCR typ. 26 mohm), COUT = 22 uF*1

Figure 2-3. VCORE efficiency (MT6359/A)

Figure 2-4. VCORE efficiency (MT6359/B)

VOUT = 0.85V, L = 0.47 uH (DCR typ. 17 mohm), COUT = 22 uF*2

VOUT = 0.9V, L = 1.0 uH (DCR typ. 26 mohm), COUT = 22 uF*1

2-5. (MT6359/B) VMODEM efficiency (MT6359/A) ure 2-6. VMODEMFigure efficiency

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Page 33 of 1067

MT6359 PMIC Datasheet Confidential A

VOUT = 0.8V, L = 0.47 uH (DCR typ. 17 mohm), COUT = 22 uF*2

VOUT = 0.7V, L = 1.0 uH (DCR typ. 26 mohm), COUT = 22 uF*1

Figure 2-7. VPU efficiency (MT6359/A)

Figure 2-8. VPU efficiency (MT6359/B)

VOUT = 2.0V, L = 1 uH (DCR typ. 26 mohm), COUT = 22 uF*2

VOUT = 1.35V, L = 1 uH (DCR typ. 26 mohm), COUT = 22 uF*2

Figure 2-9. VS1 efficiency

Figure 2-10. VS2 efficiency

VOUT = 3.4V, L = 1.0 uH (DCR typ. 44 mohm), COUT = 1 uF + 14 uF

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Page 34 of 1067

MT6359 PMIC Datasheet Confidential A Table 2-6. LDO specifications Parameter

Comments Controller All LDOs power ALDOs from VSYSxx DLDOs from Power source VSYSxx Input power SLDOs from VS1_LDOx SLDOs from VS2_LDOx Normal ALDOs from mode VSYSxx Normal DLDOs from mode VSYSxx Drop out voltage Normal SLDOs from mode VS1_LDOx Normal SLDOs from mode VS2_LDOx ALDO_50mA ALDO_200mA DLDO_200mA DLDO_800mA SLDO_300mA Bypass mode Normal Rdson mode SLDO_350mA SLDO_450mA SLDO_600mA SLDO_800mA SLDO_1200mA ALDO_50mA ALDO_200mA DLDO_200mA DLDO_800mA SLDO_300mA Normal Rated load mode SLDO_350mA current SLDO_450mA (I_rated) SLDO_600mA SLDO_800mA SLDO_1200mA Low-power All LDOs mode Normal mode Overall DC error at All LDOs Low-power default mode voltage

MediaTek Proprietary and Confidential.

Conditions

Min.

Typical

Max.

Unit

-

3.1

-

5

V

-

5

V

-

5

V

-

2.1

V

-

1.4175

V

-

3.1 **note(1.1) 3.1 **note(1.1) 1.9 **note(1.2) 1.2825 **note(1.3)

**note(1.1)

-

-

0.35

V

**note(1.1)

-

-

0.35

V

**note(1.2)

-

-

0.15

V

**note(1.3)

-

-

0.1

V

I_rated ≤ 50 mA I_rated ≤ 200mA I_rated ≤ 200mA I_rated ≤ 800mA I_rated ≤ 300mA I_rated ≤ 350mA I_rated ≤ 450mA I_rated ≤ 600mA I_rated ≤ 800mA I_rated ≤ 1200mA

-

-

3,400 900 1,500 400 310 150 150 150 150 110 50 200 200 800 300 350 450 600 800 1,200

mΩ mΩ mΩ mΩ mΩ mΩ mΩ mΩ mΩ mΩ mA mA mA mA mA mA mA mA mA mA

I_rated ≤ 10mA

-

-

10

mA

Included 1. DC voltage error 2. Load and line regulations 3. Temperature:

-2

-

+2

%

-4

-

+4

%

Input power voltage ≦ Vo-0.1V

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Page 35 of 1067

MT6359 PMIC Datasheet Confidential A Parameter

Overall DC error at nondefault voltage

Comments

Normal mode Low-power mode

I_rated ≤ 200mA

Normal Load transient mode response

Turn-on rise time Turn-on overshoot Turn-on overshoot

Discharger resister

All LDOs

I_rated > 200mA

Low-power mode Normal mode Normal mode Normal mode

Normal mode

All LDOs All LDOs

Quiescent current

Normal mode Normal mode Normal mode Normal mode Normal mode Low-power mode Low-power mode Low-power mode Low-power mode

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1mA 0.5x I_rated (15 mA/us) 0.01x I_rated 0.5 x I_rated (100 mA /us) 1 mA 10 mA (10 mA/us) In typical capacitor **note(1.4)

Min.

Typical

Max.

Unit

-3

-

+3

%

-5

-

+5

%

-4

-

+4

%

-4

-

+4

%

-5

-

+5

%

-

-

280

us

-

Vo x +10%

V

-

Vo +100 mV 510 510 770

Ω Ω Ω

460

Ω

Vo > 1V

In typical capacitor

Vo x -10%

Vo ≤ 1V

In typical capacitor

Vo-100 mV

ALDOs DLDOs SLDOs

All type ALDOs All type DLDOs All type SLDOs VSRAM_PROC1; VSRAM_PROC2; VSRAM_OTHERS; VSRAM_MD; Freq = 10 Hz ~ 10 MHz All rated load current All rated load current

-

SLDOs

Special LDOs

Output noise

Conditions -40~85°C 4. Process Included 1. DC voltage error 2. Load and line regulations 3. Temperature: -40~85°C 4. Process

All LDOs

V

-

-

1

mV

-

47

55

uA

-

26.5

31

uA

I_rated ≤ 800 mA

-

115

175.5

uA

SLDOs

I_rated ≥ 1,200 mA

-

165

247

uA

ALDOs

All type ALDOs

-

6.6

8.5

uA

DLDOs

All type DLDOs

-

10.5

13

uA

SLDOs

I_rated ≤ 800 mA

-

18

22.5

uA

SLDOs

I_rated ≥ 1,000 mA

-

18

39

uA

ALDOs DLDOs

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Page 36 of 1067

MT6359 PMIC Datasheet Confidential A Parameter

Comments Conditions Min. Typical Max. Normal All LDOs OC 1.2 x I_rated 3 x I_rated mode Normal All LDOs OCFB 0.2 x I_rated I_rated mode Short current Normal VSIM1/VSIM2/VIB 2.5 x Special LDOs 1.2 x I_rated mode R I_rated Low-power All LDOs OC **note(1.5) 10 I_rated mode Note 1 **note(1.1) ALDOs and DLDOs Vi ( Input power ) ≥ Max {Vo + 0.35V; 3.1V} Example 1: If Vo = 3V; Vi ≥ 3.35V Example 2: If V o =2V; Vi ≥ 3.1V **note(1.2) SLDOs is from VS1_LDOx Vi (input power) ≥ Max {Vo + 0.15V; 1.9V} Example 1: If Vo = 1.85V; Vi ≥ 2V Example 2: If Vo = 1.5V; Vi ≥ 1.9V **note(1.3) SLDOs is from VS2_LDOx Vi (input power) ≥ Max {Vo + 0.1V; 1.2825V} Example 1: If Vo = 1.2V; Vi ≥ 1.3V Example 2: If Vo = 1V; Vi ≥ 1.2825.V **note(1.4) For typical capacitor, refer to design notice. **note(1.5) The low-power mode OC range is closed to normal mode OCFB range.

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Unit mA mA mA mA

Page 37 of 1067

MT6359 PMIC Datasheet Confidential A Table 2-7. LDO specifications Parameter

Comments Normal mode Normal mode Normal mode Normal mode Normal mode Normal mode

PSRR Normal mode Normal mode Normal mode Normal mode Normal mode Normal mode

Conditions 1. I load ≤ I_rated 2. Freq = 50 Hz ~ 1kHz 1. I load ≤ I_rated 2. Freq = 1~10 kHz ALDOs **note (2.1) 1. I load ≤ I_rated 2. Freq = 10~100 kHz 1. I load ≤ I_rated 2. Freq = 100 kHz ~ 1 MHz 1. I load ≤ I_rated 2. Freq = 50 Hz ~ 1 kHz 1. I load ≤ I_rated 2. Freq = 1~10 kHz DLDOs **note (2.1) 1. I load ≤ I_rated 2. Freq = 10~100 kHz 1. I load ≤ I_rated 2. Freq = 100 kHz ~ 1 MHz 1. I load ≤ I_rated 2. Freq = 50 Hz ~ 1 kHz 1. I load ≤ I_rated 2. Freq = 1~10 kHz SLDOs **note (2.2) 1. I load ≤ I_rated 2. Freq = 10~100 kHz 1. I load ≤ I_rated 2. Freq = 100 kHz ~ 1 MHz

Min.

Typical

Max.

Unit

-

60

-

dB

-

40

-

dB

-

23

-

dB

-

12

-

dB

-

54

-

dB

-

34

-

dB

-

22

-

dB

-

8

-

dB

-

46

-

dB

-

29

-

dB

-

15

-

dB

-

2

-

dB

Note 2 **note(2.1) ALDOs and DLDOs Vi (input power) ≥ Max {Vo + 0.45V; 3.2V}; ripple = ±100 mV Example 1: If Vo = 3V; Vi ≥ 3.45V Example 2: If Vo = 2V; Vi ≥ 3.2V **note(2.2) SLDOs is from VS1_LDOx Vi (input power) ≥ Max {Vo + 0.2V; 1.95V}; ripple = ±50 mV Example 1: If Vo = 1.9V; Vi ≥ 2V Example 2: If Vo = 1.5V; Vi ≥ 1.95V ** SLDOs is from VS2_LDOx Vi (input power) ≥ Max {Vo + 0.15V; 1.3325V}; ripple = ±50 mV Example 1: If Vo = 1.2V; Vi ≥ 1.35V Example 2: If Vo = 1V; Vi ≥ 1.3325V

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Page 38 of 1067

MT6359 PMIC Datasheet Confidential A

2.7

Vibrator Table 2-7. Vibrator specification Parameter

Conditions

Min.

Typical

Max.

Unit

VIBR

Output voltage

Output current

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VIBR_VOSEL = 1000 VIBR_VOSEL = 1001 VIBR_VOSEL = 1011 VIBR_VOSEL = 1101

2.7 2.8 3.0 3.3 200

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V V V V mA

Page 39 of 1067

MT6359 PMIC Datasheet Confidential A

2.8

Audio CODEC Table 2-8. Audio downlink specifications

Symbol Parameter Min. Typ. Max. Unit DAC to audio buffer output high performance mode (single-ended output, AU_HPL/R; RLOAD = 32) Temp = 25 deg, 1 kHz sinusoid signal, FS,DL = 48 kHz, Gain = +6 dB, 24-bit audio data (default) POUT Max. output power@< 0.1% THD 35.71 mW SNR (1) Signal to noise ratio (A-weighted) 114 dB(A) Total harmonic distortion (THD) @POUT = 2 mW -100 THD dB @POUT = 10 mW -100 @POUT = 22.5 mW -98 THD plus noise (THD + N) @POUT = 2 mW -96 THD + N dB @POUT = 10 mW -96 @POUT = 22.5 mW -96 NFOUT Output noise floor (A-weighted) 1.8 μVrms (A) RLOAD Output resistor load (headphone) 14.4 32 Ω CLOAD Output capacitor load 250 pF APGRDL Analog programmable gain range -22 +8 dB APGSDL Analog programmable gain step 1 dB XTLR L/R channel crosstalk@1 kHz -110 dB Power supply rejection ratio PSRR -96 dB (From AVDD18_AUD to AU_HPL/R)@1 kHz Glitch Click-and-Pop (CnP) suppression -80 -75 dBVpp (rms) DC offset Output DC offset measured at silent input 0.3 mV DAC to audio buffer output high performance mode (single-ended output, AU_HPL/R; RLOAD = 16) Temp = 25 deg, 1 kHz sinusoid signal, FS,DL = 48 kHz, Gain = +5 dB, 24-bit audio data (default) POUT Maximum output power@< 0.1% THD 50.69 mW SNR (1) Signal to noise ratio (A-weighted) 113 dB (A) Total harmonic distortion (THD) @POUT = 2 mW -97 THD dB @POUT = 10 mW -98 @POUT = 22.5 mW -99 THD plus noise (THD + N) @POUT = 2 mW -95 THD + N dB @POUT = 10 mW -96 @POUT = 22.5 mW -96 NFOUT Output noise floor (A-weighted) 1.8 μVrms (A)

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Page 40 of 1067

MT6359 PMIC Datasheet Confidential A Symbol Parameter Min. Typ. Max. DAC to audio buffer output low power mode (single-ended output, AU_HPL/R; RLOAD = 32) Temp = 25 deg, 1 kHz sinusoid signal, FS,DL = 48 kHz, Gain = +6 dB, 24-bit audio data (default) POUT Max. output power@< 0.1% THD 35.57 (1) SNR Signal to noise ratio (A-weighted) 112 Total Harmonic distortion (THD) @POUT = 2 mW -95 THD @POUT = 10 mW -97 @POUT = 22.5 mW -97 THD plus noise (THD + N) @POUT = 2 mW -92 THD + N @POUT = 10 mW -95 @POUT = 22.5 mW -95 NFOUT Output noise floor (A-weighted) 2.2 RLOAD Output resistor load (headphone) 14.4 32 CLOAD Output capacitor load 250 APGRDL Analog programmable gain range -22 +8 APGSDL Analog programmable gain step 1 XTLR L/R channel crosstalk@1 kHz -110 Power supply rejection ratio PSRR -96 (From AVDD18_AUD to AU_HPL/R)@1 kHz Glitch

Click-and-Pop (CnP) suppression

-80

-75

DC offset Output DC offset measured at silent input 0.3 DAC to audio buffer output Low Power mode (single-ended output, AU_HPL/R; RLOAD = 16) Temp = 25 deg, 1 kHz sinusoid signal, FS,DL = 48 kHz, Gain = +5 dB, 24-bit audio data (default)

Unit

mW dB(A) dB

dB μVrms (A) Ω pF dB dB dB dB dBVpp (rms) mV

POUT

Max. output power@< 0.1% THD

50.43

mW

SNR (1)

Signal to noise ratio (A-weighted) Total harmonic distortion (THD) @POUT = 2 mW @POUT = 10 mW @POUT = 22.5 mW THD plus noise (THD + N) @POUT = 2 mW @POUT = 10 mW @POUT = 22.5 mW Output noise floor (A-weighted)

111

dB(A)

THD

THD + N NFOUT

-91 -94 -96 -90 -92 -94 2.1

dB

dB μVrms(A)

Note 1: Ratio of output level with 1 kHz full-scale sine wave input, to the output level with the inputs short circuited, measured A-weighted over a 20 Hz to 20 kHz bandwidth using an audio analyzer Note 2: The output voltage range of both audio and voice buffer outputs are within [AU_V18N, AVDD18_AUD].

Symbol Parameter Min. Typ. Max. DAC to line-out output (differential outputs, AU_LOLP/N; RLOAD = 560) Temp = 25 deg, 1 kHz sinusoid signal, FS,DL = 48 kHz, PGADL gain = + 7dB, 24-bit audio data Max. output swing@< 1% THD VOUT 7.7 @PGADL gain = +5 dB gain SNR (1) Signal to noise ratio (A-weighted) 112

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Unit

dBV dB (A)

Page 41 of 1067

MT6359 PMIC Datasheet Confidential A Symbol THD THD + N NFOUT RLOAD CLOAD APGRDL APGSDL PSRR

Parameter Total harmonic distortion (THD)@PGADL gain = +5 dB gain THD plus noise (THD + N) @POUT = 3.2 mW Output noise floor (A-weighted) Output resistor load (headphone) Output capacitor load Analog programmable gain range Analog programmable gain step Power supply rejection ratio (from AVDD18_AUD to AU_LOLP/N)@1 kHz

Min.

Typ.

Max.

Unit

-98

dB

-96 5.8 560

1

dB μVrms (A) Ω pF dB dB

-96

dB

500 +8

-10

Note 1: Ratio of output level with 1 kHz full-scale sine wave input, to the output level with the inputs short circuited, measured A-weighted over a 20 Hz to 20 kHz bandwidth using an audio analyzer Note 2: The output voltage range of both audio and voice buffer outputs are within [AU_V18N, AVDD18_AUD].

Symbol Parameter Min. Typ. Max. DAC to voice buffer output (differential outputs, AU_HSP/N; R LOAD = 32) Temp = 25 deg, 1 kHz sinusoid signal, FS,DL = 48 kHz, Gain = +6 dB, 16-bit audio data (default) POUT Max. output power@S

5

4

3

2

1

1 5

1 4

1 3

Dummy

1 2

1 1

1 0

9

8

7

6

5

4

3

2

1

0

Dual I/O Read

CS CK SIO0 SIO1

DATA, S->M

1 5

1 3

1 1

9

7

5

3

1

1 5

1 3

1 1

9

7

5

3

1

R 1 W 2

1 0

8

6

4

2

0

1 4

1 2

1 0

8

6

4

2

0

ADR, M->S

(Dummy: default 16T)

Dummy

DATA, S->M

(Dummy: default 16T)

SPI parameter configuration 1.5+CSLEXT_END

1+EXT_CK (2)

1.5+CSLEXT_START 1+RDDMY

1+CSHEXT

CS CK

ADR, M->S

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Dummy

DATA, S->M

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Page 70 of 1067

MT6359 PMIC Datasheet Confidential A

3.2.13

GPIO

3.2.13.1

GPIO List

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Table 3-4. MT6359 GPIO list

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Page 71 of 1067

MT6359 PMIC Datasheet Confidential A 3.2.13.2

GPIO Specification Table 3-5. MT6359 GPIO electrical characteristics

Parameters Inputs VIH VIL Rpu Rpd Outputs VOH (DC) VOL (DC) Leakage

Descriptions

Min.

Input logic low voltage Input logic high voltage Input pull-up resistance Input pull-down resistance

0.75*VIO -0.3 40 40

DC Output logic low voltage DC Output logic high voltage

0.75*VIO

Typ.

Max.

Unit

75 75

VIO + 0.3 0.25*VIO 190 190

V V KΩ KΩ

0.25*VIO

V V

IIN

Input leakage current (any input 0V < VIN < VDDIO)

-5

5

uA

IOZ

Tri-state output leakage current

-5

5

uA

-10

10

uA

-10

10

uA

IIN IOZ

Input leakage current (VIN = 3.3V/0V) for floating nwell IO Tri-state output leakage current for for floating nwell IO

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Page 72 of 1067

MT6359 PMIC Datasheet Confidential A

3.3

Register Table and Description (Group A)

Module name: MT6359_PMIC_Register_Mapping (E2) Base address: (+0h) Address 0000000C 0000000E 00000010 00000012 00000014 00000016 00000018 0000001A 0000001C 0000001E 00000022 0000002A 0000002C 0000002E 00000030 00000032 00000034 00000036 00000038 0000003A 0000003C 0000003E 00000040 00000042 00000044 00000046 00000048 0000004A 00000088 0000008A 0000008C 0000008E 00000090 00000092 00000094 00000096 00000098 0000009A 0000009C 0000009E 000000A0 000000A2 000000A4 000000A6 000000A8 000000AA

Name PONSTS POFFSTS PSTSCTL PG_DEB_STS0 PG_DEB_STS1 PG_SDN_STS0 PG_SDN_STS1 OC_SDN_STS0 OC_SDN_STS1 THERMALSTATUS TEST_OUT TOPSTATUS TDSEL_CON RDSEL_CON SMT_CON0 SMT_CON1 TOP_RSV0 TOP_RSV1 DRV_CON0 DRV_CON1 DRV_CON2 DRV_CON3 DRV_CON4 FILTER_CON0 FILTER_CON1 FILTER_CON2 FILTER_CON3 TOP_STATUS GPIO_DIR0 GPIO_DIR0_SET GPIO_DIR0_CLR GPIO_DIR1 GPIO_DIR1_SET GPIO_DIR1_CLR GPIO_PULLEN0 GPIO_PULLEN0_SET GPIO_PULLEN0_CLR GPIO_PULLEN1 GPIO_PULLEN1_SET GPIO_PULLEN1_CLR GPIO_PULLSEL0 GPIO_PULLSEL0_SET GPIO_PULLSEL0_CLR GPIO_PULLSEL1 GPIO_PULLSEL1_SET GPIO_PULLSEL1_CLR

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Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

Register Function Power on Source Record Register Power off Source Record Register Power on/off Status Control Power Good Debounce Status Register 0 Power Good Debounce Status Register 1 Power Good Shutdown Status Register 0 Power Good Shutdown Status Register 1 BUCK OC Shutdown Status Register 0 BUCK OC Shutdown Status Register 1 Thermal Status TEST_OUT TOP Status TDSEL_CON RDSEL_CON SMT_CON0 SMT_CON1 TOP_RSV0 TOP_RSV1 DRV_CON0 DRV_CON1 DRV_CON2 DRV_CON3 DRV_CON4 FILTER_CON0 FILTER_CON1 FILTER_CON2 FILTER_CON3 TOP_Status GPIO Direction Control Register 0 GPIO_DIR0 Register SET GPIO_DIR0 Register CLR GPIO Direction Control Register 1 GPIO_DIR1 Register SET GPIO_DIR1 Register CLR GPIO Pull-up/Pull-down Enable Register 0 GPIO_PULLEN0 Register SET GPIO_PULLEN0 Register CLR GPIO Pull-up/Pull-down Enable Register 1 GPIO_PULLEN1 Register SET GPIO_PULLEN1 Register CLR GPIO Pull-up/Pull-down Selection Register 0 GPIO_PULLSEL0 Register SET GPIO_PULLSEL0 Register CLR GPIO Pull-up/Pull-down Selection Register 1 GPIO_PULLSEL1 Register SET GPIO_PULLSEL1 Register CLR

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Page 73 of 1067

MT6359 PMIC Datasheet Confidential A Address 000000AC 000000AE 000000B0 000000B2 000000B4 000000B6 000000B8 000000BA 000000BC 000000BE 000000C0 000000C2 000000C4 000000C6 000000C8 000000CA 000000CC 000000CE 000000D0 000000D2 000000D4 000000D6 000000D8 000000DA 000000DC 000000DE 000000E0 000000E2 000000E4 000000E6 000000E8 000000EA 00000108 0000010A 0000010C 0000010E 00000110 00000112 00000114 00000116 00000118 0000011A 0000011C 00000120 00000122 00000124 00000126 00000128 0000012A

Name GPIO_DINV0 GPIO_DINV0_SET GPIO_DINV0_CLR GPIO_DINV1 GPIO_DINV1_SET GPIO_DINV1_CLR GPIO_DOUT0 GPIO_DOUT0_SET GPIO_DOUT0_CLR GPIO_DOUT1 GPIO_DOUT1_SET GPIO_DOUT1_CLR GPIO_PI0 GPIO_PI1 GPIO_POE0 GPIO_POE1 GPIO_MODE0 GPIO_MODE0_SET GPIO_MODE0_CLR GPIO_MODE1 GPIO_MODE1_SET GPIO_MODE1_CLR GPIO_MODE2 GPIO_MODE2_SET GPIO_MODE2_CLR GPIO_MODE3 GPIO_MODE3_SET GPIO_MODE3_CLR GPIO_MODE4 GPIO_MODE4_SET GPIO_MODE4_CLR GPIO_RSV TOP_PAM0 TOP_PAM1 TOP_CKPDN_CON0 TOP_CKPDN_CON0_SET TOP_CKPDN_CON0_CLR TOP_CKPDN_CON1 TOP_CKPDN_CON1_SET TOP_CKPDN_CON1_CLR TOP_CKSEL_CON0 TOP_CKSEL_CON0_SET TOP_CKSEL_CON0_CLR TOP_CKSEL_CON1_SET TOP_CKSEL_CON1_CLR TOP_CKDIVSEL_CON0 TOP_CKDIVSEL_CON0_SET TOP_CKDIVSEL_CON0_CLR TOP_CKHWEN_CON0

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Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

Register Function GPIO Data Inversion Control Register 0 GPIO_DINV0 Register SET GPIO_DINV0 Register CLR GPIO Data Inversion Control Register 1 GPIO_DINV1 Register SET GPIO_DINV1 Register CLR GPIO Data Output Register 0 GPIO_DOUT0 Register SET GPIO_DOUT0 Register CLR GPIO Data Output Register 1 GPIO_DOUT1 Register SET GPIO_DOUT1 Register CLR GPIO Data Input Register 0 GPIO Data Input Register 1 GPIO Data Direction Register 0 GPIO Data Direction Register 1 GPIO Mode Control Register 0 GPIO_MODE0 Register SET GPIO_MODE0 Register CLR GPIO Mode Control Register 1 GPIO_MODE1 Register SET GPIO_MODE1 Register CLR GPIO Mode Control Register 2 GPIO_MODE2 Register SET GPIO_MODE2 Register CLR GPIO Mode Control Register 3 GPIO_MODE3 Register SET GPIO_MODE3 Register CLR GPIO Mode Control Register 4 GPIO_MODE4 Register SET GPIO_MODE4 Register CLR GPIO Reserved TOP Parameter 0 TOP Parameter 1 TOP_CKPDN Control Register 0 TOP_CKPDN_CON0 Register SET TOP_CKPDN_CON0 Register CLR TOP_CKPDN Control Register 1 TOP_CKPDN_CON1 Register SET TOP_CKPDN_CON1 Register CLR TOP_CKSEL Control Register 0 TOP_CKSEL_CON0 Register SET TOP_CKSEL_CON0 Register CLR TOP_CKSEL_CON1 Register SET TOP_CKSEL_CON1 Register CLR TOP_CKDIVSEL Control Register 0 TOP_CKDIVSEL_CON0 Register SET TOP_CKDIVSEL_CON0 Register CLR TOP_CKHWEN Control Register 0

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Page 74 of 1067

MT6359 PMIC Datasheet Confidential A Address 0000012C 0000012E 0000014A 0000014C 0000014E 00000188 0000018E 00000194 00000196 00000198 0000019A 0000019C 0000019E 000001A0 00000388 0000038A 0000038C 0000038E 00000390 00000392 00000394 00000396 00000398 0000039A 0000039C 0000039E 000003A0 000003A2 000003A4 000003A6 00000514 00000516 00000518 0000051A 0000051C 0000051E 00000528 0000052E 00000534 00000538 00000588 0000058A 0000058C 0000058E 00000590 00000592

Name TOP_CKHWEN_CON0_SET TOP_CKHWEN_CON0_CLR TOP_RST_MISC TOP_RST_MISC_SET TOP_RST_MISC_CLR MISC_TOP_INT_CON0 MISC_TOP_INT_MASK_CON0 MISC_TOP_INT_STATUS0 MISC_TOP_INT_RAW_STATU S0 TOP_INT_MASK_CON0 TOP_INT_MASK_CON0_SET TOP_INT_MASK_CON0_CLR TOP_INT_STATUS0 TOP_INT_RAW_STATUS0 TOP_CLK_TRIM OTP_CON0 OTP_CON1 OTP_CON2 OTP_CON3 OTP_CON4 OTP_CON5 OTP_CON6 OTP_CON7 OTP_CON8 OTP_CON9 OTP_CON10 OTP_CON11 OTP_CON12 OTP_CON13 OTP_CON14 SCK_TOP_CKPDN_CON0 SCK_TOP_CKPDN_CON0_SET SCK_TOP_CKPDN_CON0_CLR SCK_TOP_CKHWEN_CON0 SCK_TOP_CKHWEN_CON0_S ET SCK_TOP_CKHWEN_CON0_C LR SCK_TOP_INT_CON0 SCK_TOP_INT_MASK_CON0 SCK_TOP_INT_STATUS0 SCK_TOP_INT_MISC_CON RTC_BBPU RTC_IRQ_STA RTC_IRQ_EN RTC_CII_EN RTC_AL_MASK RTC_TC_SEC

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Width 16 16 16 16 16 16 16 16 16

Register Function TOP_CKHWEN_CON0 Register SET TOP_CKHWEN_CON0 Register CLR Reset Control MISC Reset Control MISC SET Reset Control MISC CLR TOP INT Control Register 0 MISC INT Mask Control Register 0 MISC TOP INT Status Register 0

16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

TOP_INT_MASK Control Register 0 TOP_INT_MASK Control Register SET TOP_INT_MASK Control Register CLR TOP_INT_STATUS Register 0 TOP_INT_RAQ_STATUS Register 0 TOP_CLK_TRIM Register OTP Control Register 0 OTP Control Register 1 OTP Control Register 2 OTP Control Register 3 OTP Control Register 4 OTP Control Register 5 OTP Control Register 6 OTP Control Register 7 OTP Control Register 8 OTP Control Register 9 OTP Control Register 10 OTP Control Register 11 OTP Control Register 12 OTP Control Register 13 OTP Control Register 14 SCK_CKPDN Control Register 0 SCK_CKPDN Control Register 0 SET SCK_CKPDN Control Register 0 CLR SCK_CKHWEN Control Register 0

16 16 16 16 16 16 16 16 16 16 16

MISC TOP INT Raw Status Register 0

SCK_CKHWEN_CON Register 0 SET SCK_CKHWEN_CON Register 0 CLR SCK_TOP INT Control Register 0 SCK_TOP INT Mask Control Register 0 SCK_TOP INT Status Register 0 SCK_TOP INT MISC Control Register Baseband Power Up RTC IRQ Status RTC IRQ Enable Counter Increment IRQ Enable RTC Alarm Mask RTC Seconds Time Counter Register

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Page 75 of 1067

MT6359 PMIC Datasheet Confidential A Address 00000594 00000596 00000598 0000059A 0000059C 0000059E 000005A0 000005A2 000005A4 000005A6 000005A8 000005AA 000005AC 000005AE 000005B0 000005B2 000005B4 000005B6 000005B8 000005BA 000005BC 000005BE 000005C0 000005C2 000005C4 00000608 0000060A 0000060C 0000060E 00000610 00000612 00000614 00000616 00000618 00000788 0000078A 0000078C 0000078E 00000790 00000792 00000794 00000796 00000798 0000079C 0000079E 000007A0 000007A2 000007A4 000007A6

Name RTC_TC_MIN RTC_TC_HOU RTC_TC_DOM RTC_TC_DOW RTC_TC_MTH RTC_TC_YEA RTC_AL_SEC RTC_AL_MIN RTC_AL_HOU RTC_AL_DOM RTC_AL_DOW RTC_AL_MTH RTC_AL_YEA RTC_OSC32CON RTC_POWERKEY1 RTC_POWERKEY2 RTC_PDN1 RTC_PDN2 RTC_SPAR0 RTC_SPAR1 RTC_PROT RTC_DIFF RTC_CALI RTC_WRTGR RTC_CON RTC_TC_SEC_SEC RTC_TC_MIN_SEC RTC_TC_HOU_SEC RTC_TC_DOM_SEC RTC_TC_DOW_SEC RTC_TC_MTH_SEC RTC_TC_YEA_SEC RTC_SEC_CK_PDN RTC_SEC_WRTGR DCXO_CW00 DCXO_CW00_SET DCXO_CW00_CLR DCXO_CW01 DCXO_CW02 DCXO_CW03 DCXO_CW04 DCXO_CW05 DCXO_CW06 DCXO_CW08 DCXO_CW09 DCXO_CW09_SET DCXO_CW09_CLR DCXO_CW10 DCXO_CW11

MediaTek Proprietary and Confidential.

Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

Register Function RTC Minutes Time Counter Register RTC Hours Time Counter Register RTC Day-of-month Time Counter Register RTC Day-of-week Time Counter Register RTC month time counter register RTC Year Time Counter Register RTC Second Alarm Setting Register RTC Minute Alarm Setting Register RTC Hour Alarm Setting Register RTC Day-of-month Alarm Setting Register RTC Day-of-week Alarm Setting Register RTC Month Alarm Setting Register RTC Year Alarm Setting Register OSC32 Control RTC_POWERKEY1 Register RTC_POWERKEY2 Register PDN1 PDN2 Spare Register for Specific Purpose_0 Spare Register for Specific Purpose_1 Lock/Unlock Scheme to Prevent RTC Miswriting One-time Calibration Offset Repeat Calibration Offset Enable Transfers from Core to RTC in Queue Other RTC Control Register Security RTC Seconds Time Counter Register Security RTC Minutes Time Counter Register Security RTC Hours Time Counter Register Security RTC Day-of-month Time Counter Register Security RTC Day-of-week Time Counter Register Security RTC Month Time Counter Register Security RTC Year Time Counter Register Security RTC Clock Control Register Enable Transfers from Core to Security RTC in Queue DCXO Code Word 0 DCXO Code Word 0 Set DCXO Code Word 0 Clear DCXO Code Word 1 DCXO Code Word 2 DCXO Code Word 3 DCXO Code Word 4 DCXO Code Word 5 DCXO Code Word 6 DCXO Code Word 8 DCXO Code Word 9 DCXO Code Word 9 Set DCXO Code Word 9 Clear DCXO Code Word 10 DCXO Code Word 11

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Page 76 of 1067

MT6359 PMIC Datasheet Confidential A Address 000007A8 000007AA 000007AC 000007B6 00000910 00000912 00000914 00000916 00000918 0000091A 0000091C 0000091E 0000098A 0000098C 0000098E 00000A08 00000A12 00000A14 00000A1A 00000A20 00000A88 00000A8C 00000A90 00000A92 00000A94 00000A96 00000A9E 00000C32 00000C34 00000C36 00000C38 00000C3A 00000C3C 00000C3E 00000C40 00000C42 00000C44 00000C46 00000C48 00000C4A 00000C4C 00000C4E

Name DCXO_CW12 DCXO_CW13 DCXO_CW14 DCXO_CW19 PSC_TOP_INT_CON0 PSC_TOP_INT_CON0_SET PSC_TOP_INT_CON0_CLR PSC_TOP_INT_MASK_CON0 PSC_TOP_INT_MASK_CON0_ SET PSC_TOP_INT_MASK_CON0_ CLR PSC_TOP_INT_STATUS0 PSC_TOP_INT_RAW_STATUS 0 STRUP_ANA_CON1 STRUP_ANA_CON2 STRUP_ANA_CON3 PPCCTL0 STRUP_CON12 STRUP_CON13 STRUP_CON4 STRUP_CON5 CHR_CON0 CHR_CON2 PCHR_VREF_ANA_CON0 PCHR_VREF_ANA_CON1 PCHR_VREF_ANA_CON2 PCHR_VREF_ANA_CON3 PCHR_VREF_ELR_0 BM_TOP_INT_CON0 BM_TOP_INT_CON0_SET BM_TOP_INT_CON0_CLR BM_TOP_INT_CON1 BM_TOP_INT_CON1_SET BM_TOP_INT_CON1_CLR BM_TOP_INT_MASK_CON0 BM_TOP_INT_MASK_CON0_ SET BM_TOP_INT_MASK_CON0_ CLR BM_TOP_INT_MASK_CON1 BM_TOP_INT_MASK_CON1_ SET BM_TOP_INT_MASK_CON1_ CLR BM_TOP_INT_STATUS0 BM_TOP_INT_STATUS1 BM_TOP_INT_RAW_STATUS0

MediaTek Proprietary and Confidential.

Width 16 16 16 16 16 16 16 16 16 16

Register Function DCXO Code Word 12 DCXO Code Word 13 DCXO Code Word 14 DCXO Code Word 19 PSC_TOP INT Control Register 0 PSC_TOP INT Control Register 0 SET PSC_TOP INT Control Register 0 CLR PSC_TOP INT Mask Control Register 0 PSC_TOP INT Mask Control Register 0 SET PSC_TOP INT Mask Control Register 0 CLR

16 16

PSC_TOP INT Status Register 0

16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

STRUP Control Register 1 STRUP Control Register 2 STRUP Control Register 3 PPC Control 0 Register STRUP DIG Control Register 12 STRUP DIG Control Register 13 STRUP DIG Control Register N4 STRUP DIG Control Register N5 Charger Control Register 0 Charger Control Register 2 PCHR_VREF Control Register 0 PCHR_VREF Control Register 1 PCHR_VREF Control Register 2 PCHR_VREF Control Register 3 PCHR_VREF ELR 0 Register BM_TOP_INT Control Register 0 BM_TOP_INT Control Register 0 SET BM_TOP_INT Control Register 0 CLR BM_TOP_INT Control Register 1 BM_TOP_INT Control Register 1 SET BM_TOP_INT Control Register 1 CLR BM_TOP_INT_MASK Control Register 0

16 16 16 16 16 16 16

PSC_TOP INT Raw Status Register 0

BM_TOP_INT Mask Control Register 0 SET BM_TOP_INT Mask Control Register 0 CLR BM_TOP_INT_MASK Control Register 1 BM_TOP_INT Mask Control Register 1 SET BM_TOP_INT Mask Control Register 1 CLR BM_TOP_INT Status Register 0 BM_TOP_INT Status Register 1 BM_TOP_INT Raw Status Register 0

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Page 77 of 1067

MT6359 PMIC Datasheet Confidential A Address 00000C50 00000C52 00000D16 00000D18 00000D24 00000D26 00000D2C 00000D2E 00000D38 00000D3A 00000D8A 00000E08 00000E88 00000F08 00000F0A 00000F0C 00000F0E 00000F10 00000F12 00000F14 00000F16 00000F18 00000F1A 00000F1C 00000F1E 00000F20 00000F22 00000F24 00000F26 00000F28 00000F2A 00000F2C 00000F2E 00000F30 00000F32 00000F34 00000F36 00000F38 00000F3A 00000F3C 00000F3E 00000F40 00000F42 00000F46 00000F48 00000F50 00000F52 00000F54 00000F92

Name BM_TOP_INT_RAW_STATUS1 BM_TOP_INT_MISC_CON FGADC_CAR_CON0 FGADC_CAR_CON1 FGADC_NCAR_CON0 FGADC_NCAR_CON1 FGADC_IAVG_CON0 FGADC_IAVG_CON1 FGADC_NTER_CON0 FGADC_NTER_CON1 FGADC_CUR_CON0 BATON_ANA_CON0 BATON_CON0 BIF_CON0 BIF_CON1 BIF_CON2 BIF_CON3 BIF_CON4 BIF_CON5 BIF_CON6 BIF_CON7 BIF_CON8 BIF_CON9 BIF_CON10 BIF_CON11 BIF_CON12 BIF_CON13 BIF_CON14 BIF_CON15 BIF_CON16 BIF_CON17 BIF_CON18 BIF_CON19 BIF_CON20 BIF_CON21 BIF_CON22 BIF_CON23 BIF_CON24 BIF_CON25 BIF_CON26 BIF_CON27 BIF_CON28 BIF_CON29 BIF_CON31 BIF_CON32 BIF_CON36 BIF_CON37 BIF_CON38 HK_TOP_INT_CON0

MediaTek Proprietary and Confidential.

Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

Register Function BM_TOP_INT Raw Status Register 1 BM_TOP_INT MISC Control Register FGADC_CAR Control Register 0 FGADC_CAR Control Register 1 FGADC_NCAR Control Register 0 FGADC_NCAR Control Register 1 FGADC_IAVG Control Register 0 FGADC_IAVG Control Register 1 FGADC_NTER Control Register 0 FGADC_NTER Control Register 1 FGADC_CUR Control Register 0 BATON Analog Control Register 0 BATON Control Register 0 BIF Control Register 0 BIF Control Register 1 BIF Control Register 2 BIF Control Register 3 BIF Control Register 4 BIF Control Register 5 BIF Control Register 6 BIF Control Register 7 BIF Control Register 8 BIF Control Register 9 BIF Control Register 10 BIF Control Register 11 BIF Control Register 12 BIF Control Register 13 BIF Control Register 14 BIF Control Register 15 BIF Control Register 16 BIF Control Register 17 BIF Control Register 18 BIF Control Register 19 BIF Control Register 20 BIF Control Register 21 BIF Control Register 22 BIF Control Register 23 BIF Control Register 24 BIF Control Register 25 BIF Control Register 26 BIF Control Register 27 BIF Control Register 28 BIF Control Register 29 BIF Control Register 31 BIF Control Register 32 BIF Control Register 36 BIF Control Register 37 BIF Control Register 38 HK_TOP_INT_CON0

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Page 78 of 1067

MT6359 PMIC Datasheet Confidential A Address 00000F94 00000F96 00000F98 00000F9A 00000F9C 00000F9E 00000FA0 00001088 0000108A 0000108C 0000108E 00001090 00001092 00001094 00001096 00001098 0000109A 0000109C 0000109E 000010A0 000010A2 000010A4 000010A6 000010A8 000010AA 000010AC 000010AE 000010B0 000010B2 000010B4 000010B6 000010B8 000010BA 000010BC 000010BE 000010C0 000010C2 000010C4 000010C6 000010C8 000010CA 000010CC 000010CE 000011D2 000011D4 0000120E 00001210

Name HK_TOP_INT_CON0_SET HK_TOP_INT_CON0_CLR HK_TOP_INT_MASK_CON0 HK_TOP_INT_MASK_CON0_S ET HK_TOP_INT_MASK_CON0_C LR HK_TOP_INT_STATUS0 HK_TOP_INT_RAW_STATUS0 AUXADC_ADC0 AUXADC_ADC1 AUXADC_ADC2 AUXADC_ADC3 AUXADC_ADC4 AUXADC_ADC5 AUXADC_ADC6 AUXADC_ADC7 AUXADC_ADC8 AUXADC_ADC9 AUXADC_ADC10 AUXADC_ADC11 AUXADC_ADC12 AUXADC_ADC15 AUXADC_ADC16 AUXADC_ADC17 AUXADC_ADC18 AUXADC_ADC19 AUXADC_ADC20 AUXADC_ADC21 AUXADC_ADC22 AUXADC_ADC23 AUXADC_ADC24 AUXADC_ADC26 AUXADC_ADC27 AUXADC_ADC30 AUXADC_ADC32 AUXADC_ADC33 AUXADC_ADC34 AUXADC_ADC37 AUXADC_ADC38 AUXADC_ADC39 AUXADC_ADC40 AUXADC_STA0 AUXADC_STA1 AUXADC_STA2 AUXADC_NAG_10 AUXADC_NAG_11 AUXADC_IMP3 AUXADC_IMP4

MediaTek Proprietary and Confidential.

Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

Register Function HK_TOP_INT_CON0_SET HK_TOP_INT_CON0_CLR HK_TOP_INT_MASK_CON0 HK_TOP_INT_MASK_CON0_SET HK_TOP_INT_MASK_CON0_CLR HK_TOP_INT_STATUS0 HK_TOP_INT_RAW_STATUS0 AUXADC ADC Register 0 AUXADC ADC Register 1 AUXADC ADC Register 2 AUXADC ADC Register 3 AUXADC ADC Register 4 AUXADC ADC Register 5 AUXADC ADC Register 6 AUXADC ADC Register 7 AUXADC ADC Register 8 AUXADC ADC Register 9 AUXADC ADC Register 10 AUXADC ADC Register 11 AUXADC ADC Register 12 AUXADC ADC Register 15 AUXADC ADC Register 16 AUXADC ADC Register 17 AUXADC ADC Register 18 AUXADC ADC Register 19 AUXADC ADC Register 20 AUXADC ADC Register 21 AUXADC ADC Register 22 AUXADC ADC Register 23 AUXADC ADC Register 24 AUXADC ADC Register 26 AUXADC ADC Register 27 AUXADC ADC Register 30 AUXADC ADC Register 32 AUXADC ADC Register 33 AUXADC ADC Register 34 AUXADC ADC Register 37 AUXADC ADC Register 38 AUXADC ADC Register 39 AUXADC ADC Register 40 AUXADC_STA0 AUXADC_STA1 AUXADC_STA2 AUXADC_NAG_10 AUXADC_NAG_11 AUXADC_IMP3 AUXADC_IMP4

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Page 79 of 1067

MT6359 PMIC Datasheet Confidential A Address 00001212 00001222 00001224 00001236 00001238 00001248 0000124A 0000125A 0000125C 00001266 00001268 0000126E 00001270 00001418 0000141A 0000141C 0000141E 00001420 00001422 00001424 00001426 00001430 00001488 0000148E 000014AC 00001508 0000150E 00001534 00001588 0000158E 000015AC 00001688 0000168E 000016AE 00001708 0000170E 0000172E 00001788 0000178E 000017B2 00001808 00001888 00001908 0000190E 0000198E 000019A4

Name AUXADC_IMP5 AUXADC_LBAT7 AUXADC_LBAT8 AUXADC_BAT_TEMP_8 AUXADC_BAT_TEMP_9 AUXADC_LBAT2_7 AUXADC_LBAT2_8 AUXADC_THR7 AUXADC_THR8 AUXADC_MDRT_4 AUXADC_MDRT_5 AUXADC_DCXO_MDRT_3 AUXADC_DCXO_MDRT_4 BUCK_TOP_INT_CON0 BUCK_TOP_INT_CON0_SET BUCK_TOP_INT_CON0_CLR BUCK_TOP_INT_MASK_CON0 BUCK_TOP_INT_MASK_CON 0_SET BUCK_TOP_INT_MASK_CON 0_CLR BUCK_TOP_INT_STATUS0 BUCK_TOP_INT_RAW_STATU S0 BUCK_TOP_OC_CON0 BUCK_VPU_CON0 BUCK_VPU_CON1 BUCK_VPU_ELR0 BUCK_VCORE_CON0 BUCK_VCORE_CON1 BUCK_VCORE_ELR0 BUCK_VGPU11_CON0 BUCK_VGPU11_CON1 BUCK_VGPU11_ELR0 BUCK_VMODEM_CON0 BUCK_VMODEM_CON1 BUCK_VMODEM_ELR0 BUCK_VPROC1_CON0 BUCK_VPROC1_CON1 BUCK_VPROC1_ELR0 BUCK_VPROC2_CON0 BUCK_VPROC2_CON1 BUCK_VPROC2_ELR0 BUCK_VS1_CON0 BUCK_VS2_CON0 BUCK_VPA_CON0 BUCK_VPA_CON1 VGPUVCORE_ANA_CON2 VGPUVCORE_ANA_CON13

MediaTek Proprietary and Confidential.

Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

Register Function AUXADC_IMP5 AUXADC_LBAT7 AUXADC_LBAT8 AUXADC_BAT_TEMP_8 AUXADC_BAT_TEMP_9 AUXADC_LBAT2_7 AUXADC_LBAT2_8 AUXADC_THR7 AUXADC_THR8 AUXADC_MDRT_4 AUXADC_MDRT_5 AUXADC_DCXO_MDRT_3 AUXADC_DCXO_MDRT_4 BUCK_TOP Interrupt Enable Control 0 BUCK_TOP Interrupt Enable Control 0 SET BUCK_TOP Interrupt Enable Control 0 CLR BUCK_TOP Interrupt Mask Control 0 BUCK_TOP Interrupt Mask Control 0 SET BUCK_TOP Interrupt Mask Control 0 CLR

16 16

BUCK_TOP Interrupt Status 0

16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

BUCK_TOP OC Control Register 0 BUCK VPU Control 0 BUCK VPU Control 1 BUCK_VPU ELR 0 Register BUCK VCORE Control 0 BUCK VCORE Control 1 BUCK_VCORE ELR 0 Register BUCK VGPU11 Control 0 BUCK VGPU11 Control 1 BUCK_VGPU11 ELR 0 Register BUCK VMODEM CONTROL 0 BUCK VMODEM CONTROL 1 BUCK_VMODEM ELR 0 register BUCK VPROC1 Control 0 BUCK VPROC1 Control 1 BUCK_VPROC1 ELR 0 Register BUCK VPROC2 Control 0 BUCK VPROC2 Control 1 BUCK_VPROC2 ELR 0 Register BUCK VS1 Control 0 BUCK VS2 Control 0 BUCK VPA Control 0 BUCK VPA Control 1 VGPUVCORE Control Register 2 VGPUVCORE Control Register 13

BUCK_TOP Interrupt Raw Status 0

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Page 80 of 1067

MT6359 PMIC Datasheet Confidential A Address 000019B2 00001A0E 00001A1A 00001A26 00001A2C 00001A32 00001A34 00001A3A 0000230C 00002312 00002328 0000232A 0000232C 0000232E 00002330 00002332 00002334 00002336 00002338 0000233A 00002388 0000238A 0000238C 0000238E 00002390 00002392 00002394 00002396 00002398 0000239A 0000239C 0000239E 000023A0 000023A2 000023A4 000023A6 000023A8 000023AA 000023AC 000023AE 000023B0 000023B2 000023B4 000023B6 000023B8 000023D8

Name VPROC1_ANA_CON3 VPROC2_ANA_CON3 VMODEM_ANA_CON3 VPU_ANA_CON3 VS1_ANA_CON0 VS1_ANA_CON3 VS2_ANA_CON0 VS2_ANA_CON3 AUD_TOP_CKPDN_CON0 AUD_TOP_CKSEL_CON0 AUD_TOP_INT_CON0 AUD_TOP_INT_CON0_SET AUD_TOP_INT_CON0_CLR AUD_TOP_INT_MASK_CON0 AUD_TOP_INT_MASK_CON0 _SET AUD_TOP_INT_MASK_CON0 _CLR AUD_TOP_INT_STATUS0 AUD_TOP_INT_RAW_STATU S0 AUD_TOP_INT_MISC_CON0 AUD_TOP_MON_CON0 AFE_UL_DL_CON0 AFE_DL_SRC2_CON0_L AFE_UL_SRC_CON0_H AFE_UL_SRC_CON0_L AFE_ADDA6_L_SRC_CON0_H AFE_ADDA6_UL_SRC_CON0_L AFE_TOP_CON0 AUDIO_TOP_CON0 AFE_MON_DEBUG0 AFUNC_AUD_CON0 AFUNC_AUD_CON1 AFUNC_AUD_CON2 AFUNC_AUD_CON3 AFUNC_AUD_CON4 AFUNC_AUD_CON5 AFUNC_AUD_CON6 AFUNC_AUD_CON7 AFUNC_AUD_CON8 AFUNC_AUD_CON9 AFUNC_AUD_CON10 AFUNC_AUD_CON11 AFUNC_AUD_CON12 AFUNC_AUD_MON0 AFUNC_AUD_MON1 AUDRC_TUNE_MON0 AFE_SGEN_CFG0

MediaTek Proprietary and Confidential.

Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

Register Function VPROC1 Control Register 3 VPROC2 Control Register 3 VMODEM Control Register 3 VPU Control Register 3 VS1 Control Register 0 VS1 Control Register 3 VS2 Control Register 0 VS2 Control Register 3 AUDIO CLK Power Down Register 0 AUDIO CKSEL Control Register 0 AUDIO INT Control Register 0 AUD_TOP_INT Control Register 0 SET AUD_TOP_INT Control Register 0 CLR AUDIO INT MASK Control Register 0 AUD_TOP_INT Mask Control Register 0 SET AUD_TOP_INT Mask Control Register 0 CLR

16 16

AUDIO INT STATUS0 Control Register

16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

AUD_TOP_INT_MISC Control Register 0 AUD_TOP_MON control register 0 Audio UL and DL Control Register 0 AFE_DL_SRC2 Control Register 0 Low Part AFE Uplink SRC Control Register 0 High Part AFE Uplink SRC Control Register 0 Low Part AFE Uplink2 SRC Control Register 0 High Part AFE Uplink2 SRC Control Register 0 Low Part AFE Top Control Register 0 AUDIO Top Control Register 0 AFE Monitor Output Debug Register 0 A_FUNC AUDIO Control Register 0 A_FUNC AUDIO Control Register 1 A_FUNC AUDIO Control Register 2 A_FUNC AUDIO Control Register 3 A_FUNC AUDIO Control Register 4 A_FUNC AUDIO Control Register 5 A_FUNC AUDIO Control Register 6 A_FUNC AUDIO Control Register 7 A_FUNC AUDIO Control Register 8 A_FUNC AUDIO Control Register 10 A_FUNC AUDIO Control Register 11 A_FUNC AUDIO Control Register 12 A_FUNC AUDIO Control Register 18 A_FUNC AUDIO Monitor Register 0 A_FUNC AUDIO Monitor Register 1 Analog Monitor Register 0 AFE SGEN CON0

AUD_TOP_INT_RAW_STATUS0 Register

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Page 81 of 1067

MT6359 PMIC Datasheet Confidential A Address 000023DA 000023DC 000023DE 000023E0 000023E2 000023F8 000023FA 0000240A 0000240C 0000240E

Name AFE_SGEN_CFG1 AFE_ADC_ASYNC_FIFO_CFG AFE_ADC_ASYNC_FIFO_CFG1 AFE_DCCLK_CFG0 AFE_DCCLK_CFG1 AFE_CHOP_CFG0 AFE_MTKAIF_MUX_CFG AFE_VOW_TOP_CON0 AFE_VOW_TOP_CON1 AFE_VOW_TOP_CON2

00002410

AFE_VOW_TOP_CON3

00002414 00002416 00002418 0000241A 0000241C 0000241E 00002420 00002422 00002424 00002426 00002428 0000242A 0000242C 0000242E 00002448 0000244A 0000244C 0000244E 00002488 0000248A 0000248C 0000248E 00002490 00002492 00002494 00002496 00002498 0000249A 0000249C 0000249E 000024A0 Periodic Configuration 13000024A2 000024A4 000024A6 000024A8 000024AA 000024AC

AFE_VOW_TOP_MON0 AFE_VOW_VAD_CFG0 AFE_VOW_VAD_CFG1 AFE_VOW_VAD_CFG2 AFE_VOW_VAD_CFG3 AFE_VOW_VAD_CFG4 AFE_VOW_VAD_CFG5 AFE_VOW_VAD_CFG6 AFE_VOW_VAD_CFG7 AFE_VOW_VAD_CFG8 AFE_VOW_VAD_CFG9 AFE_VOW_VAD_CFG10 AFE_VOW_VAD_CFG11 AFE_VOW_VAD_CFG12 AFE_VOW_TGEN_CFG0 AFE_VOW_TGEN_CFG1 AFE_VOW_HPF_CFG0 AFE_VOW_HPF_CFG1 AFE_VOW_PERIODIC_CFG0 AFE_VOW_PERIODIC_CFG1 AFE_VOW_PERIODIC_CFG2 AFE_VOW_PERIODIC_CFG3 AFE_VOW_PERIODIC_CFG4 AFE_VOW_PERIODIC_CFG5 AFE_VOW_PERIODIC_CFG6 AFE_VOW_PERIODIC_CFG7 AFE_VOW_PERIODIC_CFG8 AFE_VOW_PERIODIC_CFG9 AFE_VOW_PERIODIC_CFG10 AFE_VOW_PERIODIC_CFG11 AFE_VOW_PERIODIC_CFG12

16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

Register Function AFE SGEN CON1 AFE_ADC_SYNC_FIFO_CFG AFE_ADC_SYNC_FIFO_CFG1 AFE_DCCLK_CFG0 AFE_DCCLK_CFG1 AFE_CHOP_CFG0 AFE_MTKAIF_MUX_CFG AFE VOW Top Control for Dual Channels AFE VOW Top Control for Left Channel AFE VOW Top Control for Right Channel AFE Vow Top Control for Test Clock and MTKAIF Settings AFE Vow Top Monitor Out AFE Vow vad Configurations 0 AFE Vow vad Configurations 1 AFE Vow vad Configurations 2 AFE Vow vad Configurations 3 AFE Vow vad Configurations 4 AFE Vow vad Configurations 5 AFE Vow vad Configurations 6 AFE Vow vad Configurations 7 AFE Vow vad Configurations 8 AFE Vow vad Configurations 9 AFE Vow vad Configurations 10 AFE Vow vad Configurations 11 AFE Vow vad Configurations 12 AFE Vow Trigen Configuration 0 AFE Vow Trigen Configuration 1 AFE Vow hpf Configuration 0 AFE Vow hpf Configuration 1 AFE Vow Periodic Configuration 0 AFE Vow Periodic Configuration 1 AFE Vow Periodic Configuration 2 AFE Vow Periodic Configuration 3 AFE Vow Periodic Configuration 4 AFE Vow Periodic Configuration 5 AFE Vow Periodic Configuration 6 AFE Vow Periodic Configuration 7 AFE Vow Periodic Configuration 8 AFE Vow Periodic Configuration 9 AFE Vow Periodic Configuration 10 AFE Vow Periodic Configuration 11 AFE Vow Periodic Configuration 12

AFE_VOW_PERIODIC_CFG14 AFE_VOW_PERIODIC_CFG15 AFE_VOW_PERIODIC_CFG16 AFE_VOW_PERIODIC_CFG17 AFE_VOW_PERIODIC_CFG18

16 16 16 16 16

AFE Vow Periodic Configuration 14 AFE Vow Periodic Configuration 15 AFE Vow Periodic Configuration 16 AFE Vow Periodic Configuration 17 AFE Vow Periodic Configuration 18

MediaTek Proprietary and Confidential.

Width 16 16 16 16 16 16 16 16 16 16 16

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Page 82 of 1067

MT6359 PMIC Datasheet Confidential A Address 000024AE 000024B0 000024B2 000024B4 000024B6 000024B8 000024BA 000024BC 000024BE 000024C0 000024C2 000024C4 000024C6 000024C8 000024CA 000024CC 000024CE 000024D0 000024D2 000024D4 000024D6 000024D8 000024DA 000024DC 000024DE 000024E0 000024E2 00002508 0000250A 0000250C 0000250E 00002510 00002512 00002514 00002516 00002518 0000251A 0000251C 0000251E 00002520 00002522 00002524 00002526 00002528 0000252A 0000252C 0000252E 00002530 00002532

Name AFE_VOW_PERIODIC_CFG19 AFE_VOW_PERIODIC_CFG20 AFE_VOW_PERIODIC_CFG21 AFE_VOW_PERIODIC_CFG22 AFE_VOW_PERIODIC_CFG23 AFE_VOW_PERIODIC_CFG24 AFE_VOW_PERIODIC_CFG25 AFE_VOW_PERIODIC_CFG26 AFE_VOW_PERIODIC_CFG27 AFE_VOW_PERIODIC_CFG28 AFE_VOW_PERIODIC_CFG29 AFE_VOW_PERIODIC_CFG30 AFE_VOW_PERIODIC_CFG31 AFE_VOW_PERIODIC_CFG32 AFE_VOW_PERIODIC_CFG33 AFE_VOW_PERIODIC_CFG34 AFE_VOW_PERIODIC_CFG35 AFE_VOW_PERIODIC_CFG36 AFE_VOW_PERIODIC_CFG37 AFE_VOW_PERIODIC_CFG38 AFE_VOW_PERIODIC_CFG39 AFE_VOW_PERIODIC_MON0 AFE_VOW_PERIODIC_MON1 AFE_VOW_PERIODIC_MON2 AFE_NCP_CFG0 AFE_NCP_CFG1 AFE_NCP_CFG2 AUDENC_ANA_CON0 AUDENC_ANA_CON1 AUDENC_ANA_CON2 AUDENC_ANA_CON3 AUDENC_ANA_CON4 AUDENC_ANA_CON5 AUDENC_ANA_CON6 AUDENC_ANA_CON7 AUDENC_ANA_CON8 AUDENC_ANA_CON9 AUDENC_ANA_CON10 AUDENC_ANA_CON11 AUDENC_ANA_CON12 AUDENC_ANA_CON13 AUDENC_ANA_CON14 AUDENC_ANA_CON15 AUDENC_ANA_CON16 AUDENC_ANA_CON17 AUDENC_ANA_CON18 AUDENC_ANA_CON19 AUDENC_ANA_CON20 AUDENC_ANA_CON21

MediaTek Proprietary and Confidential.

Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

Register Function AFE Vow Periodic Configuration 19 AFE Vow Periodic Configuration 20 AFE Vow Periodic Configuration 21 AFE Vow Periodic Configuration 22 AFE Vow Periodic Configuration 23 AFE Vow Periodic Configuration 24 AFE Vow Periodic Configuration 25 AFE Vow Periodic Configuration 26 AFE Vow Periodic Configuration 27 AFE Vow Periodic Configuration 28 AFE Vow Periodic Configuration 29 AFE Vow Periodic Configuration 30 AFE Vow Periodic Configuration 31 AFE Vow Periodic Configuration 32 AFE Vow Periodic Configuration 33 AFE Vow Periodic Configuration 34 AFE Vow Periodic Configuration 35 AFE Vow Periodic Configuration 36 AFE Vow Periodic Configuration 37 AFE Vow Periodic Configuration 38 AFE Vow Periodic Configuration 39 AFE Vow Periodic Monitor 0 AFE Vow Periodic Monitor 1 AFE Vow Periodic Monitor 2 AFE_NCP_CFG0 AFE_NCP_CFG1 AFE_NCP_CFG2 AUDENC Control Register 0 AUDENC Control Register 1 AUDENC Control Register 2 AUDENC Control Register 3 AUDENC Control Register 4 AUDENC Control Register 5 AUDENC Control Register 6 AUDENC Control Register 7 AUDENC Control Register 8 AUDENC Control Register 9 AUDENC Control Register 10 AUDENC Control Register 11 AUDENC Control Register 12 AUDENC Control Register 13 AUDENC Control Register 14 AUDENC Control Register 15 AUDENC Control Register 16 AUDENC Control Register 17 AUDENC Control Register 18 AUDENC Control Register 19 AUDENC Control Register 20 AUDENC Control Register 21

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Page 83 of 1067

MT6359 PMIC Datasheet Confidential A Address 00002534 00002536 00002588 0000258A 0000258C 0000258E 00002590 00002592 00002594 00002596 00002598 0000259A 0000259C 0000259E 000025A0 000025A2 000025A4 00002608 0000260A 0000260C 0000260E 00002610 00002612 00002688 0000268A 0000268C 0000268E 00002690 00002692 00002694 00002696 00002698 0000269A 0000269C 0000269E 000026A4 000026A6 000026AC 000026AE 000026D8

Name AUDENC_ANA_CON22 AUDENC_ANA_CON23 AUDDEC_ANA_CON0 AUDDEC_ANA_CON1 AUDDEC_ANA_CON2 AUDDEC_ANA_CON3 AUDDEC_ANA_CON4 AUDDEC_ANA_CON5 AUDDEC_ANA_CON6 AUDDEC_ANA_CON7 AUDDEC_ANA_CON8 AUDDEC_ANA_CON9 AUDDEC_ANA_CON10 AUDDEC_ANA_CON11 AUDDEC_ANA_CON12 AUDDEC_ANA_CON13 AUDDEC_ANA_CON14 ZCD_CON0 ZCD_CON1 ZCD_CON2 ZCD_CON3 ZCD_CON4 ZCD_CON5 ACCDET_CON0 ACCDET_CON1 ACCDET_CON2 ACCDET_CON3 ACCDET_CON4 ACCDET_CON5 ACCDET_CON6 ACCDET_CON7 ACCDET_CON8 ACCDET_CON9 ACCDET_CON10 ACCDET_CON11 ACCDET_CON14 ACCDET_CON15 ACCDET_CON18 ACCDET_CON19 ACCDET_CON40

MediaTek Proprietary and Confidential.

Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

Register Function AUDENC Control Register 22 AUDENC Control Register 23 AUDDEC Control Register 0 AUDDEC Control Register 1 AUDDEC Control Register 2 AUDDEC Control Register 3 AUDDEC Control Register 4 AUDDEC Control Register 5 AUDDEC Control Register 6 AUDDEC Control Register 7 AUDDEC Control Register 8 AUDDEC Control Register 9 AUDDEC Control Register 10 AUDDEC Control Register 11 AUDDEC Control Register 12 AUDDEC Control Register 13 AUDDEC Control Register 14 ZCD Control Register 0 ZCD Control Register 1 ZCD Control Register 2 ZCD Control Register 3 ZCD Control Register 4 ZCD Control Register 5 ACCDET control register 0 ACCDET control register 1 ACCDET control register 2 ACCDET Control Register 3 ACCDET Control Register 4 ACCDET Control Register 5 ACCDET Control Register 6 ACCDET Control Register 7 ACCDET Control Register 8 ACCDET Control Register 9 ACCDET Control Register 10 ACCDET Control Register 11 ACCDET Control Register 14 ACCDET Control Register 15 ACCDET Control Register 18 ACCDET Control Register 19 ACCDET Control Register 40

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Page 84 of 1067

MT6359 PMIC Datasheet Confidential A 0000000C

PONSTS 15

Bit

14

Power on Source Record Register 13

12

11

10

9

8

7

6

5

Type Reset Name STS_RBOOT STS_SPAR STS_CHRIN STS_RTCA STS_PWRKEY

0000000E

Type Reset

14

0

0

0

0

0

4

3

2

1

Power off Source Record Register

13

12

11

10

0

0

0

0

Name STS_OVLO STS_PKSP STS_KEYPWR STS_PUPSRC STS_WDT STS_DDLO STS_BWDT STS_NORMOFF STS_PKEYLP STS_CRST STS_WRST STS_THRDN STS_PSOC STS_PGFAIL STS_UVLO

00000010

0

0

9

8

7

6

5

0000 0

PSTSCTL 15

14

0

0

0

0

0

0

0

0

3

2

1

Power on/off Status Control 13

Type Reset Name RG_PONSTS_CLR RG_POFFSTS_CLR

MediaTek Proprietary and Confidential.

0

0

Description Power off for OVLO event PWRKEY short press Critical power is turned off during system on. Power off for power source missing AP WDT DDLO occurs after system on. Power off for BWDT Power off for PWRHOLD clear Power off for power key(s) long press Power off for cold reset Power reset for warm reset Power off for thermal shutdown Power off for default on BUCK OC Power off for PWRGOOD failure Power off for UVLO event

Name

Bit(s) 8 0

1

STS_N STS_O STS_PK STS_KE STS_PU STS_W STS_DD STS_B STS_PK STS_CR STS_W STS_TH STS_PS STS_PG STS_U ORMO VLO SP YPWR PSRC DT LO WDT EYLP ST RST RDN OC FAIL VLO FF RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO

Name

Bit

2

Description Power on for cold reset Power on for SPAR event Power on for charger insertion Power on for RTC alarm Power on for PWREKY press

POFFSTS 15

Bit

Bit(s) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

3

STS_RB STS_SP STS_CH STS_RT STS_P OOT AR RIN CA WRKEY RO RO RO RO RO

Name

Bit(s) 4 3 2 1 0

0000 4

12

11

10

9

8

7

6

0000 5

4

0

RG_PO NSTS_C LR RW

RG_PO FFSTS_ CLR RW

0

0

Description Clears PONSTS Clears POFFSTST and PG/OC status

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Page 85 of 1067

MT6359 PMIC Datasheet Confidential A 00000012 Bit

PG_DEB_STS0 15

14

13

Power Good Debounce Status Register 0 12

11

10

9

8

7

6

5

4

FFFF 3

2

1

0

VXO22 VAUX1 VCORE VGPU1 VGPU1 VMOD VA09_ VA12_ VRFCK_ VBBCK VUFS_ VIO18_ VM18_ VPU_P VS2_P VS1_P EM_PG PG_DE PG_DE 1_PG_ _PG_D PG_DE PG_DE PG_DE Name _PG_D 8_PG_ _PG_D 1_PG_ 2_PG_ G_DEB G_DEB G_DEB EB DEB EB DEB DEB _DEB B B DEB EB B B B RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Reset

Bit(s) 15

Name VXO22_PG_DEB

14

VAUX18_PG_DEB

13

VCORE_PG_DEB

12

VGPU11_PG_DEB

11

VGPU12_PG_DEB

10

VPU_PG_DEB

9

VMODEM_PG_DEB

8

VS2_PG_DEB

7

VA09_PG_DEB

6

VA12_PG_DEB

5

VS1_PG_DEB

4

VRFCK_1_PG_DEB

3

VBBCK_PG_DEB

2

VUFS_PG_DEB

1

VIO18_PG_DEB

MediaTek Proprietary and Confidential.

Description PG status (dynamic change with HW) 0: Power not good 1: Power good PG status (dynamic change with HW) 0: Power not good 1: Power good PG status (dynamic change with HW) 0: Power not good 1: Power good PG status (dynamic change with HW) 0: Power not good 1: Power good PG status (dynamic change with HW) 0: Power not good 1: Power good PG status (dynamic change with HW) 0: Power not good 1: Power good PG status (dynamic change with HW) 0: Power not good 1: Power good PG status (dynamic change with HW) 0: Power not good 1: Power good PG status (dynamic change with HW) 0: Power not good 1: Power good PG status (dynamic change with HW) 0: Power not good 1: Power good PG status (dynamic change with HW) 0: Power not good 1: Power good PG status (dynamic change with HW) (MT6359P VRFCK_1/MT6359PP VRFCK) 0: Power not good 1: Power good PG status (dynamic change with HW) 0: Power not good 1: Power good PG status (dynamic change with HW) 0: Power not good 1: Power good PG status (dynamic change with HW) 0: Power not good 1: Power good

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Page 86 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 0

Name VM18_PG_DEB

00000014 Bit

Description PG status (dynamic change with HW) 0: Power not good 1: Power good

PG_DEB_STS1 15

14

13

Power Good Debounce Status Register 1 12

11

10

9

8

7

6

5

4

FFE0 3

2

1

0

VSRAM VSRAM VSRAM EXT_P VEMC_ VSRAM VPROC VPROC VAUD1 VUSB_ VRF18_ _OTHE _PROC _PROC Name MIC_P PG_DE RS_PG _MD_P 2_PG_ 2_PG_ 1_PG_ 1_PG_ 8_PG_ PG_DE PG_DE G_DEB B G_DEB DEB DEB DEB B B _DEB DEB DEB RO RO RO RO RO RO RO RO RO RO RO Type

Reset Bit(s) 15

1

1

1

1

Name EXT_PMIC_PG_DEB

14

VEMC_PG_DEB

13

VSRAM_OTHERS_PG_DEB

12

VSRAM_MD_PG_DEB

11

VPROC2_PG_DEB

10

VSRAM_PROC2_PG_DEB

9

VPROC1_PG_DEB

8

VSRAM_PROC1_PG_DEB

7

VAUD18_PG_DEB

6

VUSB_PG_DEB

5

VRF18_PG_DEB

MediaTek Proprietary and Confidential.

1

1

1

1

1

1

1

Description PG status (dynamic change with HW) 0: Power not good 1: Power good PG status (dynamic change with HW) 0: Power not good 1: Power good PG status (dynamic change with HW) 0: Power not good 1: Power good PG status (dynamic change with HW) 0: Power not good 1: Power good PG status (dynamic change with HW) 0: Power not good 1: Power good PG status (dynamic change with HW) 0: Power not good 1: Power good PG status (dynamic change with HW) 0: Power not good 1: Power good PG status (dynamic change with HW) 0: Power not good 1: Power good PG status (dynamic change with HW) 0: Power not good 1: Power good PG status (dynamic change with HW) 0: Power not good 1: Power good PG status (dynamic change with HW) 0: Power not good 1: Power good

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Page 87 of 1067

MT6359 PMIC Datasheet Confidential A 00000016 Bit

PG_SDN_STS0 15

STRUP _VXO2 Name 2_PG_ STATU S RO Type 1 Reset

14

13

Power Good Shutdown Status Register 0 12

11

STRUP STRUP STRUP STRUP _VAUX _VCOR _VGPU _VGPU 18_PG_ E_PG_S 11_PG_ 12_PG_ STATUS TATUS STATUS STATUS RO 1

RO 1

RO 1

RO 1

Bit(s) 15

Name STRUP_VXO22_PG_STATUS

14

STRUP_VAUX18_PG_STATUS

13

STRUP_VCORE_PG_STATUS

12

STRUP_VGPU11_PG_STATUS

11

STRUP_VGPU12_PG_STATUS

10

STRUP_VPU_PG_STATUS

9

STRUP_VMODEM_PG_STATUS

8

STRUP_VS2_PG_STATUS

7

STRUP_VA09_PG_STATUS

6

STRUP_VA12_PG_STATUS

5

STRUP_VS1_PG_STATUS

4

STRUP_VRFCK_1_PG_STATUS

3

STRUP_VBBCK_PG_STATUS

2

STRUP_VUFS_PG_STATUS

1

STRUP_VIO18_PG_STATUS

MediaTek Proprietary and Confidential.

10

9

STRUP _VPU_ PG_ST ATUS RO 1

8

7

6

5

4

FFFF 3

2

1

0

STRUP STRUP STRUP STRUP STRUP STRUP STRUP STRUP STRUP STRUP _VMO _VS2_P _VA09 _VA12 _VS1_P _VRFCK _VBBC _VUFS_ _VIO18 _VM18 DEM_P G_STA _PG_ST _PG_ST G_STA _1_PG_ K_PG_S PG_ST _PG_ST _PG_ST G_STA TUS ATUS ATUS TUS STATUS TATUS ATUS ATUS ATUS TUS RO RO RO RO RO RO RO RO RO RO 1 1 1 1 1 1 1 1 1 1

Description Shutdown PG status (cleared by SW) 0: Power not good 1: Power good Shutdown PG status (cleared by SW) 0: Power not good 1: Power good Shutdown PG status (cleared by SW) 0: Power not good 1: Power good Shutdown PG status (cleared by SW) 0: Power not good 1: Power good Shutdown PG status (cleared by SW) 0: Power not good 1: Power good Shutdown PG status (cleared by SW) 0: Power not good 1: Power good Shutdown PG status (cleared by SW) 0: Power not good 1: Power good Shutdown PG status (cleared by SW) 0: Power not good 1: Power good Shutdown PG status (cleared by SW) 0: Power not good 1: Power good Shutdown PG status (cleared by SW) 0: Power not good 1: Power good Shutdown PG status (cleared by SW) 0: Power not good 1: Power good Shutdown PG status (cleared by SW) (MT6359P VRFCK_1/MT6359PP VRFCK) 0: Power not good 1: Power good Shutdown PG status (cleared by SW) 1: Power good Shutdown PG status (cleared by SW) 0: Power not good 1: Power good Shutdown PG status (cleared by SW)

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Page 88 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

0

Name

STRUP_VM18_PG_STATUS

00000018 Bit

PG_SDN_STS1 15

14

13

Power Good Shutdown Status Register 1 12

STRUP STRUP STRUP STRUP _VSRA _EXT_P _VSRA _VEMC M_OTH M_MD Name MIC_P _PG_ST ERS_PG G_STA _PG_ST ATUS _STAT TUS ATUS US RO RO RO RO Type

Reset Bit(s) 15

Description 0: Power not good 1: Power good Shutdown PG status (cleared by SW) 0: Power not good 1: Power good

1

1

1

11

9

STRUP STRUP _VSRA _VPRO M_PRO C2_PG C2_PG _STAT _STAT US US RO RO

1

1

Name STRUP_EXT_PMIC_PG_STATUS

14

STRUP_VEMC_PG_STATUS

13

STRUP_VSRAM_OTHERS_PG_STATUS

12

STRUP_VSRAM_MD_PG_STATUS

11

STRUP_VPROC2_PG_STATUS

10

STRUP_VSRAM_PROC2_PG_STATUS

9

STRUP_VPROC1_PG_STATUS

8

STRUP_VSRAM_PROC1_PG_STATUS

7

STRUP_VAUD18_PG_STATUS

6

STRUP_VUSB_PG_STATUS

5

STRUP_VRF18_PG_STATUS

MediaTek Proprietary and Confidential.

10

1

8

7

6

5

4

FFE0 3

2

1

0

STRUP STRUP _VSRA STRUP STRUP STRUP _VPRO M_PRO _VAUD _VUSB _VRF18 C1_PG C1_PG 18_PG_ _PG_ST _PG_ST _STAT _STAT STATUS ATUS ATUS US US RO RO RO RO RO 1

1

1

1

1

Description Shutdown PG status (cleared by SW) 0: Power not good 1: Power good Shutdown PG status (cleared by SW) 0: Power not good 1: Power good Shutdown PG status (cleared by SW) 0: Power not good 1: Power good Shutdown PG status (cleared by SW) 0: Power not good 1: Power good Shutdown PG status (cleared by SW) 0: Power not good 1: Power good Shutdown PG status (cleared by SW) 0: Power not good 1: Power good Shutdown PG status (cleared by SW) 0: Power not good 1: Power good Shutdown PG status (cleared by SW) 0: Power not good 1: Power good Shutdown PG status (cleared by SW) 0: Power not good 1: Power good Shutdown PG status (cleared by SW) 0: Power not good 1: Power good Shutdown PG status (cleared by SW) 0: Power not good 1: Power good

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 89 of 1067

MT6359 PMIC Datasheet Confidential A 0000001A Bit

OC_SDN_STS0 15

STRUP _VXO2 Name 2_OC_ STATU S RO Type 0 Reset

14

13

BUCK OC Shutdown Status Register 0 12

STRUP STRUP STRUP _VAUX _VGPU _VCOR 18_OC 11_OC E_OC_S _STAT _STAT TATUS US US RO RO RO 0 0 0

11 STRUP _VGPU 12_OC _STAT US RO 0

Bit(s) 15

Name STRUP_VXO22_OC_STATUS

14

STRUP_VAUX18_OC_STATUS

13

STRUP_VCORE_OC_STATUS

12

STRUP_VGPU11_OC_STATUS

11

STRUP_VGPU12_OC_STATUS

10

STRUP_VPU_OC_STATUS

9

STRUP_VMODEM_OC_STATUS

8

STRUP_VS2_OC_STATUS

7

STRUP_VA09_OC_STATUS

6

STRUP_VA12_OC_STATUS

5

STRUP_VS1_OC_STATUS

4

STRUP_VRFCK_1_OC_STATUS

3

STRUP_VBBCK_OC_STATUS

2

STRUP_VUFS_OC_STATUS

1

STRUP_VIO18_OC_STATUS

MediaTek Proprietary and Confidential.

10

9

STRUP _VPU_ OC_ST ATUS RO 0

STRUP _VMO DEM_O C_STAT US RO 0

8 STRUP _VS2_ OC_ST ATUS RO 0

7

6

STRUP STRUP _VA09 _VA12 _OC_ST _OC_ST ATUS ATUS RO 0

RO 0

5 STRUP _VS1_ OC_ST ATUS RO 0

4

0000 3

2

1

0

STRUP STRUP STRUP STRUP STRUP _VRFCK _VBBC _VUFS_ _VIO18 _VM18 _1_OC K_OC_ OC_ST _OC_ST _OC_S _STAT STATUS ATUS ATUS TATUS US RO RO RO RO RO 0 0 0 0 0

Description Shutdown OC status (cleared by SW) 0: No OC 1: OC occurs. Shutdown OC status (cleared by SW) 0: No OC 1: OC occurs. Shutdown OC status (cleared by SW) 0: No OC 1: OC occurs. Shutdown OC status (cleared by SW) 0: No OC 1: OC occurs. Shutdown OC status (cleared by SW) 0: No OC 1: OC occurs. Shutdown OC status (cleared by SW) 0: No OC 1: OC occurs. Shutdown OC status (cleared by SW) 0: No OC 1: OC occurs. Shutdown OC status (cleared by SW) 0: No OC 1: OC occurs. Shutdown OC status (cleared by SW) 0: No OC 1: OC occurs. Shutdown OC status (cleared by SW) 0: No OC 1: OC occurs. Shutdown OC status (cleared by SW) 0: No OC 1: OC occurs. Shutdown OC status (cleared by SW) (MT6359P VRFCK_1/MT6359PP VRFCK) 0: No OC 1: OC occurs. Shutdown OC status (cleared by SW) 1: OC occurs. Shutdown OC status (cleared by SW) 0: No OC 1: OC occurs. Shutdown OC status (cleared by SW)

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 90 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

0

Name

STRUP_VM18_OC_STATUS

0000001C Bit

Description 0: No OC 1: OC occurs. Shutdown OC status (cleared by SW) 0: No OC 1: OC occurs.

OC_SDN_STS1 15

14

13

BUCK OC Shutdown Status Register 1 12

11

STRUP STRUP STRUP STRUP STRUP _VSRA _VSRA _VSRA _VPRO _VEMC M_OTH M_PRO M_MD C2_OC Name _OC_S ERS_O C2_OC _OC_ST _STAT TATUS C_STAT _STAT ATUS US US US RO RO RO RO RO Type

Reset Bit(s) 15

0

0

0

0

10

8

7

6

5

4

0000 3

2

1

0

STRUP STRUP STRUP _VSRA STRUP STRUP _VPRO _VAUD M_PRO _VUSB _VRF18 C1_OC 18_OC C1_OC _OC_ST _OC_ST _STAT _STAT _STAT ATUS ATUS US US US RO RO RO RO RO

0

Name STRUP_VEMC_OC_STATUS

14

STRUP_VSRAM_OTHERS_OC_STATUS

13

STRUP_VSRAM_MD_OC_STATUS

12

STRUP_VPROC2_OC_STATUS

11

STRUP_VSRAM_PROC2_OC_STATUS

10

STRUP_VPROC1_OC_STATUS

9

STRUP_VSRAM_PROC1_OC_STATUS

8

STRUP_VAUD18_OC_STATUS

7

STRUP_VUSB_OC_STATUS

6

STRUP_VRF18_OC_STATUS

MediaTek Proprietary and Confidential.

9

0

0

0

0

0

Description Shutdown OC status (cleared by SW) 0: No OC 1: OC occurs. Shutdown OC status (cleared by SW) 0: No OC 1: OC occurs. Shutdown OC status (cleared by SW) 0: No OC 1: OC occurs. Shutdown OC status (cleared by SW) 0: No OC 1: OC occurs. Shutdown OC status (cleared by SW) 0: No OC 1: OC occurs. Shutdown OC status (cleared by SW) 0: No OC 1: OC occurs. Shutdown OC status (cleared by SW) 0: No OC 1: OC occurs. Shutdown OC status (cleared by SW) 0: No OC 1: OC occurs. Shutdown OC status (cleared by SW) 0: No OC 1: OC occurs. Shutdown OC status (cleared by SW) 0: No OC 1: OC occurs.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 91 of 1067

MT6359 PMIC Datasheet Confidential A 0000001E

THERMALSTATUS 15

Bit

14

13

12

Thermal Status 11

10

9

8

0000 7

6

5

4

3

2

1

0

STRUP PMU_T _THER HERMA Name MAL_S L_DEB TATUS RO RO Type

Reset Bit(s) 15

14

0

0

Name STRUP_THERMAL_STATUS

PMU_THERMAL_DEB

00000022

TEST_OUT 15

Bit

14

TEST_OUT

13

12

Name Type Reset Bit(s) 11:0

Description Shutdown thermal status (cleared by SW) 0: No thermal 1: Thermal occurs. Debounced thermal status

11

10

9

0000 8

7

6

5

4

3

2

1

0

0

TEST_OUT RO 0

0

Name TEST_OUT

0000002A

14

0

0

0

0

0

0

0

0

7

6

5

4

3

2

1

Description Monitor

TOPSTATUS 15

Bit

0

13

TOP Status 12

11

10

9

8

0000

Name Type Reset Bit(s) 3 2 1

0

Name HOMEKEY_DEB CHRDET_DEB PWRKEY_DEB

0000002C Bit

TDSEL_CON 15

14

0

0

Description HOMEKEY status (dynamic change with HW) CHRDET status (dynamic change with HW) PWRKEY status (dynamic change with HW)

13

TDSEL_CON 12

11

10

9

8

0000 7

6

5

4

3

2

1

0

RG_E32 RG_AU RG_PM RG_SPI CAL_TD D_TDS U_TDS _TDSEL SEL EL EL RW RW RW RW

Name Type Reset Bit(s) 3 2 1 0

0

HOME CHRDE PWRKE KEY_DE T_DEB Y_DEB B RO RO RO

0

Name RG_E32CAL_TDSEL RG_AUD_TDSEL RG_SPI_TDSEL RG_PMU_TDSEL

MediaTek Proprietary and Confidential.

0

0

0

Description TDSEL TDSEL TDSEL TDSEL

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 92 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

0000002E

RDSEL_CON 15

Bit

Description

14

13

RDSEL_CON 12

11

10

9

8

0000 7

6

5

4

Type Reset

0

Name RG_E32CAL_RDSEL RG_AUD_RDSEL RG_SPI_RDSEL RG_PMU_RDSEL

00000030 Bit

1

0

SMT_CON0 15

14

0

0

0

Description RDSEL RDSEL RDSEL RDSEL

13

SMT_CON0 12

11

10

9

8

005E 7

6

5

4

3

2

1

0

RG_SM RG_SM RG_SM RG_SM RG_SM RG_SM RG_SM T_SCP_ T_RTC_ T_RTC_ T_SRCL T_SRCL T_WDT T_HOM VREQ_ 32K1V8 32K1V8 KEN_IN KEN_IN RSTB_I EKEY VAO _1 _0 1 0 N RW RW RW RW RW RW RW

Name Type Reset Bit(s) 6

2

RG_E32 RG_AU RG_PM RG_SPI CAL_R D_RDS U_RDS _RDSEL DSEL EL EL RW RW RW RW

Name

Bit(s) 3 2 1 0

3

1

Name RG_SMT_SCP_VREQ_VAO

5

RG_SMT_HOMEKEY

4

RG_SMT_RTC_32K1V8_1

3

RG_SMT_RTC_32K1V8_0

2

RG_SMT_SRCLKEN_IN1

1

RG_SMT_SRCLKEN_IN0

0

RG_SMT_WDTRSTB_IN

MediaTek Proprietary and Confidential.

0

1

1

1

1

0

Description SMT 0: Disable 1: Enable SMT 0: Disable 1: Enable SMT 0: Disable 1: Enable SMT 0: Disable 1: Enable SMT 0: Disable 1: Enable SMT 0: Disable 1: Enable SMT 0: Disable 1: Enable

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 93 of 1067

MT6359 PMIC Datasheet Confidential A 00000032 Bit

SMT_CON1 15

14

13

SMT_CON1 12

11

10

9

8

0000 7

6

5

4

3

2

1

0

RG_SM RG_SM RG_SM RG_SM RG_SM RG_SM RG_SM RG_SM RG_SM RG_SM RG_SM RG_SM RG_SM RG_SM T_AUD T_AUD T_AUD T_AUD T_AUD T_AUD T_AUD T_AUD T_AUD T_AUD T_SPI_ T_SPI_ T_SPI_ T_SPI_ _DAT_ _DAT_ _DAT_ _NLE_ _NLE_ _SYNC_ _DAT_ _DAT_ _DAT_ _CLK_ MISO MOSI CSN CLK MISO2 MISO1 MISO0 MOSI1 MOSI0 MOSI MOSI2 MOSI1 MOSI0 MOSI RW RW RW RW RW RW RW RW RW RW RW RW RW RW

Name Type Reset

0

0

Bit(s) 13

Name RG_SMT_AUD_DAT_MISO2

12

RG_SMT_AUD_DAT_MISO1

11

RG_SMT_AUD_DAT_MISO0

10

RG_SMT_AUD_NLE_MOSI1

9

RG_SMT_AUD_NLE_MOSI0

8

RG_SMT_AUD_SYNC_MOSI

7

RG_SMT_AUD_DAT_MOSI2

6

RG_SMT_AUD_DAT_MOSI1

5

RG_SMT_AUD_DAT_MOSI0

4

RG_SMT_AUD_CLK_MOSI

3

RG_SMT_SPI_MISO

2

RG_SMT_SPI_MOSI

1

RG_SMT_SPI_CSN

0

RG_SMT_SPI_CLK

MediaTek Proprietary and Confidential.

0

0

0

0

0

0

0

0

0

0

0

0

Description SMT 0: Disable 1: Enable SMT 0: Disable 1: Enable SMT 0: Disable 1: Enable SMT 0: Disable 1: Enable SMT 0: Disable 1: Enable SMT 0: Disable 1: Enable SMT 0: Disable 1: Enable SMT 0: Disable 1: Enable SMT 0: Disable 1: Enable SMT 0: Disable 1: Enable SMT 0: Disable 1: Enable SMT 0: Disable 1: Enable SMT 0: Disable 1: Enable SMT 0: Disable 1: Enable

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 94 of 1067

MT6359 PMIC Datasheet Confidential A 00000034

TOP_RSV0 15

Bit

14

TOP_RSV0

13

12

11

10

9

0000 8

7

6

5

4

3

2

1

Name Type Reset Bit(s) 0

0

Name RG_TOP_RSV0

00000036

Description Do not modify this. Conflicts with MT6337.

TOP_RSV1 15

Bit

14

TOP_RSV1

13

12

11

10

9

0000 8

7

6

5

4

3

2

1

Type Reset

0

Name RG_TOP_RSV1

00000038

Bit(s) 15:12 11:8 7:4 3:0

14

13

DRV_CON0 12

RG_OCTL_RTC_32K1V8_1 RW 1 0 0 0

11

10

14

13

RG_OCTL_SPI_MISO RW 1 0 0 0

MediaTek Proprietary and Confidential.

7

6

5

4

3

2

1

0

RG_OCTL_SRCLKEN_IN1 RW 1 0 0 0

RG_OCTL_SRCLKEN_IN0 RW 1 0 0 0

7

3

DRV_CON1 12

Name RG_OCTL_SPI_MISO RG_OCTL_SPI_MOSI RG_OCTL_SPI_CSN

8

8888

Description OC CTL OC CTL OC CTL OC CTL

DRV_CON1 15

9

RG_OCTL_RTC_32K1V8_0 RW 1 0 0 0

Name RG_OCTL_RTC_32K1V8_1 RG_OCTL_RTC_32K1V8_0 RG_OCTL_SRCLKEN_IN1 RG_OCTL_SRCLKEN_IN0

0000003A Bit Name Type Reset

Description Do not modify this. Conflicts with MT6337.

DRV_CON0 15

Bit Name Type Reset Bit(s) 15:12 11:8 7:4 3:0

0 RG_TO P_RSV 1 RO

Name

Bit(s) 0

0 RG_TO P_RSV 0 RO

11

10

9

8

RG_OCTL_SPI_MOSI RW 1 0 0 0

8888 6

5

4

RG_OCTL_SPI_CSN RW 1 0 0 0

2

1

0

RG_OCTL_SPI_CLK RW 1 0 0 0

Description OC CTL OC CTL OC CTL

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 95 of 1067

MT6359 PMIC Datasheet Confidential A 0000003C

DRV_CON2 15

Name RG_OCTL_AUD_DAT_MOSI2 RG_OCTL_AUD_DAT_MOSI1 RG_OCTL_AUD_DAT_MOSI0 RG_OCTL_AUD_CLK_MOSI

0000003E

DRV_CON3

Bit Name Type Reset

RG_OCTL_AUD_DAT_MISO0 RW 1 0 0 0

Bit(s) 15:12 11:8 7:4 3:0

Name RG_OCTL_AUD_DAT_MISO0 RG_OCTL_AUD_NLE_MOSI1 RG_OCTL_AUD_NLE_MOSI0 RG_OCTL_AUD_SYNC_MOSI

15

14

13

11

10

14

12

13

Bit(s) 15:12 11:8 7:4 3:0

Name RG_OCTL_SCP_VREQ_VAO RG_OCTL_HOMEKEY RG_OCTL_AUD_DAT_MISO2 RG_OCTL_AUD_DAT_MISO1

13

6

5

4

RG_OCTL_AUD_DAT_MOSI0 RW 1 0 0 0

3

2

1

11

10

9

8

RG_OCTL_AUD_NLE_MOSI1 RW 1 0 0 0

8888 7

6

5

4

RG_OCTL_AUD_NLE_MOSI0 RW 1 0 0 0

3

2

1

0

RG_OCTL_AUD_SYNC_MOSI RW 1 0 0 0

Description OC CTL OC CTL OC CTL OC CTL

11

10

9

8

RG_OCTL_HOMEKEY RW 1 0 0 0

8888 7

6

5

4

RG_OCTL_AUD_DAT_MISO2 RW 1 0 0 0

3

2

1

0

RG_OCTL_AUD_DAT_MISO1 RW 1 0 0 0

Description OC CTL OC CTL OC CTL OC CTL

FILTER_CON0 12

0

RG_OCTL_AUD_CLK_MOSI RW 1 0 0 0

Description OC CTL OC CTL OC CTL OC CTL

FILTER_CON0 14

8888 7

DRV_CON4 12

RG_OCTL_SCP_VREQ_VAO RW 1 0 0 0

15

8

RG_OCTL_AUD_DAT_MOSI1 RW 1 0 0 0

DRV_CON4 15

9

DRV_CON3

Bit Name Type Reset

Bit

0

DRV_CON2 12

Bit(s) 15:12 11:8 7:4 3:0

00000042

0

13

RG_OCTL_AUD_DAT_MOSI2 RW 1 0 0 0

00000040

0

14

Bit Name Type Reset

11

10

9

8

0000 7

6

5

4

3

2

1

0

RG_AU RG_AU RG_AU RG_AU RG_AU RG_AU RG_AU RG_AU RG_RT RG_RT RG_SR RG_SPI RG_SPI RG_SPI RG_SPI RG_SR D_DAT D_DAT D_DAT D_SYN D_DAT D_DAT D_DAT D_CLK_ C32K_1 C32K_1 CLKEN _MISO _MOSI _CSN_F _CLK_F CLKEN_ V8_1_F V8_0_F _IN0_F Name _MISO _MISO _MISO C_MOS _MOSI _MOSI _MOSI MOSI_ _FILTER _FILTER ILTER_ ILTER_ IN1_FIL 2_FILTE 1_FILTE 0_FILTE I_FILTE 2_FILTE 1_FILTE 0_FILTE FILTER_ ILTER_ ILTER_ ILTER_ _EN _EN EN EN TER_EN R_EN R_EN R_EN R_EN R_EN R_EN R_EN EN EN EN EN RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type 0 0 0 0 Reset

Bit(s) 15

Name RG_AUD_DAT_MISO2_FILTER_EN

14

RG_AUD_DAT_MISO1_FILTER_EN

MediaTek Proprietary and Confidential.

Description FILTER function 0: Disable 1: Enable FILTER function

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 96 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

13

RG_AUD_DAT_MISO0_FILTER_EN

12

RG_AUD_SYNC_MOSI_FILTER_EN

11

RG_AUD_DAT_MOSI2_FILTER_EN

10

RG_AUD_DAT_MOSI1_FILTER_EN

9

RG_AUD_DAT_MOSI0_FILTER_EN

8

RG_AUD_CLK_MOSI_FILTER_EN

7

RG_SPI_MISO_FILTER_EN

6

RG_SPI_MOSI_FILTER_EN

5

RG_SPI_CSN_FILTER_EN

4

RG_SPI_CLK_FILTER_EN

3

RG_RTC32K_1V8_1_FILTER_EN

2

RG_RTC32K_1V8_0_FILTER_EN

1

RG_SRCLKEN_IN1_FILTER_EN

0

RG_SRCLKEN_IN0_FILTER_EN

MediaTek Proprietary and Confidential.

Description 0: Disable 1: Enable FILTER function 0: Disable 1: Enable FILTER function 0: Disable 1: Enable FILTER function 0: Disable 1: Enable FILTER function 0: Disable 1: Enable FILTER function 0: Disable 1: Enable FILTER function 0: Disable 1: Enable FILTER function 0: Disable 1: Enable FILTER function 0: Disable 1: Enable FILTER function 0: Disable 1: Enable FILTER function 0: Disable 1: Enable FILTER function 0: Disable 1: Enable FILTER function 0: Disable 1: Enable FILTER function 0: Disable 1: Enable FILTER function 0: Disable 1: Enable

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 97 of 1067

MT6359 PMIC Datasheet Confidential A 00000044

FILTER_CON1 15

Bit

14

13

FILTER_CON1 12

11

10

9

8

0000 7

6

5

3

2

1

0

RG_AU RG_AU RG_SC RG_W RG_HO D_NLE_ D_NLE_ P_VRE DTRST MEKEY MOSI1 MOSI0 Q_VAO B_IN_F _FILTER _FILTER _FILTER _FILTER ILTER_ _EN _EN _EN _EN EN RW RW RW RW RW

Name Type Reset Bit(s) 4

Name RG_AUD_NLE_MOSI1_FILTER_EN

3

RG_AUD_NLE_MOSI0_FILTER_EN

2

RG_SCP_VREQ_VAO_FILTER_EN

1

RG_HOMEKEY_FILTER_EN

0

RG_WDTRSTB_IN_FILTER_EN

00000046 Bit

4

14

13

0

0

0

4

3

2

1

FILTER_CON2 12

11

0

Description FILTER function 0: Disable 1: Enable FILTER function 0: Disable 1: Enable FILTER function 0: Disable 1: Enable FILTER function 0: Disable 1: Enable FILTER function 0: Disable 1: Enable

FILTER_CON2 15

0

10

9

8

0000 7

6

5

0

RG_AU RG_AU RG_AU RG_AU RG_AU RG_AU RG_AU RG_AU RG_RT RG_RT RG_SR RG_SR D_DAT D_DAT D_DAT D_SYN D_DAT D_DAT D_DAT RG_SPI RG_SPI RG_SPI RG_SPI D_CLK_ C32K_1 C32K_1 CLKEN_ CLKEN _MISO _MOSI _CSN_ _CLK_R Name _MISO _MISO _MISO C_MOS _MOSI _MOSI _MOSI MOSI_ V8_1_R V8_0_R IN1_RC _IN0_R 2_RCSE 1_RCSE 0_RCSE I_RCSE 2_RCSE 1_RCSE 0_RCSE _RCSEL _RCSEL RCSEL CSEL RCSEL CSEL CSEL SEL CSEL L L L L L L L RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

Bit(s) 15

Name RG_AUD_DAT_MISO2_RCSEL

14

RG_AUD_DAT_MISO1_RCSEL

13

RG_AUD_DAT_MISO0_RCSEL

12

RG_AUD_SYNC_MOSI_RCSEL

11

RG_AUD_DAT_MOSI2_RCSEL

10

RG_AUD_DAT_MOSI1_RCSEL

MediaTek Proprietary and Confidential.

Description FILTER function 0: Disable 1: Enable FILTER function 0: Disable 1: Enable FILTER function 0: Disable 1: Enable FILTER function 0: Disable 1: Enable FILTER function 0: Disable 1: Enable FILTER function

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 98 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

9

RG_AUD_DAT_MOSI0_RCSEL

8

RG_AUD_CLK_MOSI_RCSEL

7

RG_SPI_MISO_RCSEL

6

RG_SPI_MOSI_RCSEL

5

RG_SPI_CSN_RCSEL

4

RG_SPI_CLK_RCSEL

3

RG_RTC32K_1V8_1_RCSEL

2

RG_RTC32K_1V8_0_RCSEL

1

RG_SRCLKEN_IN1_RCSEL

0

RG_SRCLKEN_IN0_RCSEL

00000048 Bit

Description 0: Disable 1: Enable FILTER function 0: Disable 1: Enable FILTER function 0: Disable 1: Enable FILTER function 0: Disable 1: Enable FILTER function 0: Disable 1: Enable FILTER function 0: Disable 1: Enable FILTER function 0: Disable 1: Enable FILTER function 0: Disable 1: Enable FILTER function 0: Disable 1: Enable FILTER function 0: Disable 1: Enable FILTER function 0: Disable 1: Enable

FILTER_CON3 15

14

13

FILTER_CON3 12

11

10

9

8

0000 7

6

5

4

3

2

1

0

RG_AU RG_AU RG_SC RG_W RG_HO D_NLE_ D_NLE_ P_VRE DTRST MEKEY MOSI1 MOSI0 Q_VAO B_IN_R _RCSEL _RCSEL _RCSEL _RCSEL CSEL RW RW RW RW RW

Name Type Reset

0

Bit(s) 4

Name RG_AUD_NLE_MOSI1_RCSEL

3

RG_AUD_NLE_MOSI0_RCSEL

2

RG_SCP_VREQ_VAO_RCSEL

1

RG_HOMEKEY_RCSEL

MediaTek Proprietary and Confidential.

0

0

0

0

Description FILTER function 0: Disable 1: Enable FILTER function 0: Disable 1: Enable FILTER function 0: Disable 1: Enable FILTER function

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 99 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

0

Name

Description 0: Disable 1: Enable FILTER function 0: Disable 1: Enable

RG_WDTRSTB_IN_RCSEL

0000004A

TOP_STATUS 15

Bit

14

13

TOP_Status 12

11

10

9

8

0000 7

6

5

4

Name Type Reset Bit(s) 3:0

Name TOP_STATUS

0

0

Bit(s) 15:0

0

13

0

14

0

0

0

11

0

10

0

13

0

12

0

9

0

8

7

0

GPIO_DIR0 RW 0 0

0000

6

5

4

3

2

1

0

0

0

0

0

0

0

0

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

GPIO_DIR0 Register SET 11

0

10

0

9

0

8

7

GPIO_DIR0_SET W1 0 0

0000

Description 1'b0: Not set 1'b1: Set

GPIO_DIR0_CLR 14

0

Description GPIO direction control 1'b0: Input 1'b1: Output

Name GPIO_DIR0_SET

15

0

GPIO Direction Control Register 0 12

GPIO_DIR0_SET 15

0000008C

0

14

Name GPIO_DIR0

Bit Name Type Reset

0

0

Description Reserved

GPIO_DIR0 15

0000008A

Bit Name Type 0 Reset

1 RW

Bit Name Type Reset

Bit(s) 15:0

2

TOP_STATUS

00000088

Bit(s) 15:0

3

13

12

GPIO_DIR0 Register CLR 11

10

9

8

7

6

0000 5

4

3

2

1

0

0

0

0

GPIO_DIR0_CLR W1

Name GPIO_DIR0_CLR

MediaTek Proprietary and Confidential.

Description 1'b0: Not clear 1'b1: Clear

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 100 of 1067

MT6359 PMIC Datasheet Confidential A 0000008E

GPIO_DIR1 15

Bit

14

13

GPIO Direction Control Register 1 12

11

10

9

8

7

6

5

0000 4

Name Type Reset Bit(s) 3:0

Name GPIO_DIR1

0

14

0

13

0

12

0

0

10

0

0

14

0

13

0

12

0

11

0

10

0

0

14

1

Name GPIO_PULLEN0

MediaTek Proprietary and Confidential.

0

9

0

8

7

GPIO_DIR1_SET W1 0 0

0000

6

5

4

3

2

1

0

0

0

0

0

0

0

0

9

0

8

7

GPIO_DIR1_CLR W1 0 0

0000

6

5

4

3

2

1

0

0

0

0

0

0

0

0

Description 1'b0: Not clear 1'b1: Clear

GPIO_PULLEN0 15

0

GPIO_DIR1 Register CLR

Name GPIO_DIR1_CLR

00000094

0

Description 1'b0: Not set 1'b1: Set

GPIO_DIR1_CLR 15

0

GPIO_DIR1 Register SET 11

Name GPIO_DIR1_SET

Bit Name Type Reset

Bit(s) 15:0

0

Description GPIO direction control 1'b0: Input 1'b1: Output

GPIO_DIR1_SET 15

00000092

Bit Name Type Reset

1 RW

Bit Name Type Reset

Bit(s) 15:0

2

GPIO_DIR1

00000090

Bit(s) 15:0

3

13

1

12

1

GPIO Pull-up/Pull-down Enable Register 0 11

1

10

1

9

1

8

7

GPIO_PULLEN0 RW 1 0

7F33

6

5

4

3

2

1

0

0

1

1

0

0

1

1

Description Enables GPIO pull-up/pull-down 1'b0: Disable 1'b1: Enable

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 101 of 1067

er CLR

MT6359 PMIC Datasheet Confidential A 00000096

Bit(s) 15:0

GPIO_PULLEN0_SET 15

Bit Name Type Reset

0

0

13

12

0

0

GPIO_PULLEN0 Register SET 11

0

9

6

5

4

3

2

1

0

0

GPIO_PULLEN0_SET W1 0 0 0 0

0

0

0

0

0

0

Bit Name Type Reset

0

14

0

13

12

0

0

GPIO_PULLEN0 Register CLR 11

0

9

6

5

4

3

2

1

0

0

GPIO_PULLEN0_CLR W1 0 0 0 0

0

0

0

0

0

0

14

13

7

Description 1'b0: Not clear 1'b1: Clear

GPIO_PULLEN1 15

Bit

8

0000

10

Name GPIO_PULLEN0_CLR

0000009A

7

Description 1'b0: Not set 1'b1: Set

GPIO_PULLEN0_CLR 15

8

0000

10

Name GPIO_PULLEN0_SET

00000098

Bit(s) 15:0

14

12

GPIO Pull-up/Pull-down Enable Register 1 11

10

9

8

7

6

5

4

Name Type Reset Bit(s) 3:0

3

2

1 RW

1

Name GPIO_PULLEN1

0

14

0

1

0

0

Description Enables GPIO pull-up/pull-down 1'b0: Disable 1'b1: Enable

GPIO_PULLEN1_SET 15

Bit Name Type Reset

13

12

0

0

GPIO_PULLEN1 Register SET 11

0

10

9

6

5

4

3

2

1

0

0

GPIO_PULLEN1_SET W1 0 0 0 0

0

0

0

0

0

0

Name GPIO_PULLEN1_SET

8

7

0000

Description 1'b0: Not set 1'b1: Set

0000009E Bit Name Type Reset

0

GPIO_PULLEN1

0000009C

Bit(s) 15:0

000C

0000 15

0

14

0

MediaTek Proprietary and Confidential.

13

0

12

0

11

0

10

9

8

7

6

5

4

3

2

1

0

0

GPIO_PULLEN1_CLR W1 0 0 0 0

0

0

0

0

0

0

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 102 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 15:0

Name GPIO_PULLEN1_CLR

000000A0

Bit(s) 15:0

GPIO_PULLSEL0 15

Bit Name Type Reset

0

0

12

0

0

GPIO Pull-up/Pull-down Selection Register 0 11

0

10

0

14

0

13

12

Bit Name Type Reset

0

14

0

14

GPIO_PULLSEL0 RW 0 0

5

4

3

2

1

0

0

1

0

0

0

0

1

0

0

0

13

13

7

0000

6

5

4

3

2

1

0

0

GPIO_PULLSEL0_SET W1 0 0 0 0

0

0

0

0

0

0

Description 1'b0: Not set 1'b1: Set

12

0

8

0

GPIO_PULLSEL0 Register CLR 11

0

8

7

0000

10

9

6

5

4

3

2

1

0

0

GPIO_PULLSEL0_CLR W1 0 0 0 0

0

0

0

0

0

0

Description 1'b0: Not clear 1'b1: Clear

12

GPIO Pull-up/Pull-down Selection Register 1 11

10

9

8

7

6

5

4

Name Type Reset Bit(s) 3:0

0021

6

9

GPIO_PULLSEL1 15

7

10

Name GPIO_PULLSEL0_CLR

000000A6

0

8

GPIO_PULLSEL0 Register SET 11

GPIO_PULLSEL0_CLR 15

9

Description Selects GPIO pull-up/pull-down 1'b0: Pull-down 1'b1: Pull-up

Name GPIO_PULLSEL0_SET

000000A4

Bit

0

13

GPIO_PULLSEL0_SET 15

Bit Name Type Reset

Bit(s) 15:0

14

Name GPIO_PULLSEL0

000000A2

Bit(s) 15:0

Description 1'b0: Not clear 1'b1: Clear

3

0004 2

1

0

GPIO_PULLSEL1 RW 0

Name GPIO_PULLSEL1

MediaTek Proprietary and Confidential.

1

0

0

Description Selects GPIO pull-up/pull-down 1'b0: Pull-down 1'b1: Pull-up

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 103 of 1067

MT6359 PMIC Datasheet Confidential A 000000A8

Bit(s) 15:0

GPIO_PULLSEL1_SET 15

Bit Name Type Reset

0

0

0

0

14

0

13

9

0

14

0

13

0

6

5

4

3

2

1

0

0

GPIO_PULLSEL1_SET W1 0 0 0 0

0

0

0

0

0

0

0

GPIO_PULLSEL1 Register CLR 11

0

9

6

5

4

3

2

1

0

0

GPIO_PULLSEL1_CLR W1 0 0 0 0

0

0

0

0

0

0

0

14

0

GPIO Data Inversion Control Register 0 12

0

11

0

10

0

0

14

0

MediaTek Proprietary and Confidential.

0

8

7

GPIO_DINV0 RW 0 0

6

5

4

3

2

1

0

0

0

0

0

0

0

0

13

0

12

0

GPIO_DINV0 Register SET 11

0

10

0

13

0

9

0

8

7

GPIO_DINV0_SET W1 0 0

0000

6

5

4

3

2

1

0

0

0

0

0

0

0

0

6

5

4

3

2

1

0

0

0

0

0

0

0

0

Description 1'b0: Not set 1'b1: Set

GPIO_DINV0_CLR 15

9

0000

Description GPIO inversion control 1'b0: Disable 1'b1: Enable

Name GPIO_DINV0_SET

000000B0

7

Description 1'b0: Not clear 1'b1: Clear

GPIO_DINV0_SET 15

Bit Name Type Reset

8

0000

10

Name GPIO_DINV0

000000AE

7

Description 1'b0: Not set 1'b1: Set

12

0

8

0000

10

GPIO_DINV0 15

Bit Name Type Reset

Bit Name Type Reset

0

GPIO_PULLSEL1 Register SET 11

Name GPIO_PULLSEL1_CLR

000000AC

Bit(s) 15:0

12

GPIO_PULLSEL1_CLR 15

Bit Name Type Reset

Bit(s) 15:0

0

13

Name GPIO_PULLSEL1_SET

000000AA

Bit(s) 15:0

14

12

0

GPIO_DINV0 Register CLR 11

0

10

0

9

0

8

7

GPIO_DINV0_CLR W1 0 0

0000

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 104 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 15:0

Name GPIO_DINV0_CLR

000000B2

GPIO_DINV1 15

Bit

Description 1'b0: Not clear 1'b1: Clear

14

13

GPIO Data Inversion Control Register 1 12

11

10

9

8

7

6

5

4

Name Type Reset Bit(s) 3:0

Name GPIO_DINV1

0

14

0

13

12

0

0

0

10

0

0

14

0

13

12

0

0

0

10

0

0

14

0

Name GPIO_DOUT0

MediaTek Proprietary and Confidential.

0

13

0

9

0

8

7

GPIO_DINV1_SET W1 0 0

0000

6

5

4

3

2

1

0

0

0

0

0

0

0

0

9

0

8

7

6

5

4

3

2

1

0

GPIO_DINV1_CLR W1 0 0

0

0

0

0

0

0

0

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0000

Description 1'b0: Not clear 1'b1: Clear

GPIO_DOUT0 15

0

GPIO_DINV1 Register CLR 11

Name GPIO_DINV1_CLR

000000B8

0

Description 1'b0: Not set 1'b1: Set

GPIO_DINV1_CLR 15

0

GPIO_DINV1 Register SET 11

Name GPIO_DINV1_SET

Bit Name Type Reset

Bit(s) 15:0

0

Description GPIO inversion control 1'b0: Disable 1'b1: Enable

GPIO_DINV1_SET 15

000000B6

Bit Name Type Reset

1 RW

Bit Name Type Reset

Bit(s) 15:0

2

GPIO_DINV1

000000B4

Bit(s) 15:0

0000 3

GPIO Data Output Register 0 12

0

11

0

10

0

9

0

8

7

GPIO_DOUT0 RW 0 0

0000

Description GPIO data output value 1'b0: Output 0 1'b1: Output 1

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 105 of 1067

MT6359 PMIC Datasheet Confidential A 000000BA

Bit(s) 15:0

GPIO_DOUT0_SET 15

Bit Name Type Reset

0

0

13

12

0

0

GPIO_DOUT0 Register SET 11

0

10

9

0

GPIO_DOUT0_SET W1 0 0 0

Name GPIO_DOUT0_SET

000000BC

0

14

0

13

12

14

0

13

0000

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

8

7

0000

10

9

6

5

4

3

2

1

0

0

GPIO_DOUT0_CLR W1 0 0 0 0

0

0

0

0

0

0

Description 1'b0: Not clear 1'b1: Clear

GPIO_DOUT1 15

Bit

7

GPIO_DOUT0 Register CLR 11

Name GPIO_DOUT0_CLR

000000BE

8

Description 1'b0: Not set 1'b1: Set

GPIO_DOUT0_CLR 15

Bit Name Type Reset Bit(s) 15:0

14

GPIO Data Output Register 1 12

11

10

9

8

7

6

0000 5

4

Name Type Reset Bit(s) 3:0

1

0

Name GPIO_DOUT1

0

14

0

0

0

Description GPIO data output value 1'b0: Output 0 1'b1: Output 1

GPIO_DOUT1_SET 15

0

13

0

12

0

GPIO_DOUT1 Register SET 11

0

10

9

0

GPIO_DOUT1_SET W1 0 0 0

Name GPIO_DOUT1_SET

8

7

0000

6

5

4

3

2

1

0

0

0

0

0

0

0

0

Description 1'b0: Not set 1'b1: Set

000000C2 Bit Name Type Reset

0

RW

Bit Name Type Reset

CLR

2

GPIO_DOUT1

000000C0

Bit(s) 15:0

3

0000 15

0

14

0

MediaTek Proprietary and Confidential.

13

0

12

0

11

0

10

9

8

7

6

5

4

3

2

1

0

0

GPIO_DOUT1_CLR W1 0 0 0 0

0

0

0

0

0

0

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 106 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 15:0

Name GPIO_DOUT1_CLR

000000C4

Bit(s) 15:0

GPIO_PI0 15

Bit Name Type Reset

Description 1'b0: Not clear 1'b1: Clear

14

0

0

GPIO Data Input Register 0

13

12

0

0

11

0

10

0

Name GPIO_PI0

000000C6

8

7

6

5

4

3

2

1

0

0

GPIO_PI0 RO 0 0

0

0

0

0

0

0

0

5

4

3

2

1

Description GPIO data input value

GPIO_PI1 15

Bit

0000

9

14

GPIO Data Input Register 1

13

12

11

10

9

8

7

6

0000

Name Type Reset Bit(s) 3:0

RO

Name GPIO_PI1

000000C8

0

14

0

13

0

0

11

0

10

14

9

0

0

8

7

GPIO_POE0 RO 0 0

0000

5

4

3

2

1

0

0

0

0

0

0

0

0

13

4

3

2

1

GPIO Data Direction Register 1 12

11

10

9

8

7

6

5

0000 0

GPIO_POE1 RO

Name GPIO_POE1

000000CC Bit

0

6

Name Type Reset Bit(s) 3:0

0

Description GPIO direction value

GPIO_POE1 15

Bit

0

GPIO Data Direction Register 0 12

Name GPIO_POE0

000000CA

0

Description GPIO data input value

GPIO_POE0 15

Bit Name Type Reset Bit(s) 15:0

0

GPIO_PI1

14

Name Type Reset

MediaTek Proprietary and Confidential.

0

0

3

2

1

0

Description GPIO direction value

GPIO_MODE0 15

0

13

GPIO Mode Control Register 0 12

11

0

10

9

8

7

6

5

0249 4

GPIO3_MODE

GPIO2_MODE

GPIO1_MODE

RW

RW

RW

0

1

0

0

1

0

0

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

0

GPIO0_MODE RW 1

0

0

1

Page 107 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 11:9

Name GPIO3_MODE

8:6

GPIO2_MODE

5:3

GPIO1_MODE

2:0

GPIO0_MODE

000000CE Bit Name Type Reset Bit(s) 15:0

Description Selects GPIO 3 mode 0: GPIO3 (IO) 1: RTC_32K1V8_1 (O) 2: INT_1 (O) 3: Reserved 4: Reserved 5: Reserved 6: TEST_IN3 (I) 7: TEST_OUT3 (O) Selects GPIO 2 mode 0: GPIO2 (IO) 1: RTC_32K1V8_0 (O) 2: Reserved 3: Reserved 4: Reserved 5: Reserved 6: TEST_IN2 (I) 7: TEST_OUT2 (O) Selects GPIO 1 mode 0: GPIO1 (IO) 1: SRCLKEN_IN1 (I) 2: Reserved 3: Reserved 4: Reserved 5: Reserved 6: TEST_IN1 (I) 7: TEST_OUT1 (O) Selects GPIO 0 mode 0: GPIO0 (IO) 1: SRCLKEN_IN0 (I) 2: Reserved 3: Reserved 4: Reserved 5: Reserved 6: TEST_IN0 (I) 7: TEST_OUT0 (O)

GPIO_MODE0_SET 15

0

14

0

13

0

Name GPIO_MODE0_SET

MediaTek Proprietary and Confidential.

12

0

GPIO_MODE0 Register SET 11

0

8

7

0000

10

9

6

5

4

3

2

1

0

0

GPIO_MODE0_SET W1 0 0 0 0

0

0

0

0

0

0

Description 1'b0: Not set

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 108 of 1067

MT6359 PMIC Datasheet Confidential A 000000D0

Bit(s) 15:0

GPIO_MODE0_CLR 15

Bit Name Type Reset

0

0

13

12

0

0

GPIO_MODE0 Register CLR 11

0

9

6

5

4

3

2

1

0

0

GPIO_MODE0_CLR W1 0 0 0 0

0

0

0

0

0

0

14

Name Type Reset

13

4

3

2

1

GPIO Mode Control Register 1 12

11

0

Bit(s) 11:9

Name GPIO7_MODE

8:6

GPIO6_MODE

5:3

GPIO5_MODE

2:0

GPIO4_MODE

MediaTek Proprietary and Confidential.

7

Description 1'b0: Not clear 1'b1: Clear

GPIO_MODE1 15

8

0000

10

Name GPIO_MODE0_CLR

000000D2 Bit

14

10

9

8

7

6

5

0249

GPIO7_MODE

GPIO6_MODE

GPIO5_MODE

RW

RW

RW

0

1

0

0

1

0

0

0

GPIO4_MODE RW 1

0

0

1

Description Selects GPIO 7 mode 0: GPIO7 (IO) 1: SPI_MISO (IO) 2: Reserved 3: Reserved 4: Reserved 5: Reserved 6: Reserved 7: Reserved Selects GPIO 6 mode 0: GPIO6 (IO) 1: SPI_MOSI (IO) 2: Reserved 3: Reserved 4: Reserved 5: Reserved 6: Reserved 7: Reserved Selects GPIO 5 mode 0: GPIO5 (IO) 1: SPI_CSN (I) 2: Reserved 3: Reserved 4: Reserved 5: Reserved 6: Reserved 7: Reserved Selects GPIO 4 mode 0: GPIO4 (IO) 1: SPI_CLK (I) 2: Reserved 3: Reserved 4: Reserved 5: Reserved 6: Reserved © 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 109 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

000000D4

Bit(s) 15:0

GPIO_MODE1_SET 15

Bit Name Type Reset

0

0

13

12

0

0

GPIO_MODE1 Register SET 11

0

0

14

0

9

6

5

4

3

2

1

0

0

GPIO_MODE1_SET W1 0 0 0 0

0

0

0

0

0

0

13

12

0

0

GPIO_MODE1 Register CLR 11

0

14

Name Type Reset

13

9

Name GPIO11_MODE

8:6

GPIO10_MODE

5:3

GPIO9_MODE

MediaTek Proprietary and Confidential.

7

6

5

4

3

2

1

0

0

GPIO_MODE1_CLR W1 0 0 0 0

0

0

0

0

0

0

4

3

2

1

Description 1'b0: Not clear 1'b1: Clear

GPIO Mode Control Register 2 12

11

10

9

8

7

6

5

0249

GPIO11_MODE

GPIO10_MODE

GPIO9_MODE

GPIO8_MODE

RW

RW

RW

RW

0

Bit(s) 11:9

8

0000

10

GPIO_MODE2 15

7

Description 1'b0: Not set 1'b1: Set

Name GPIO_MODE1_CLR

000000D8

8

0000

10

GPIO_MODE1_CLR 15

Bit Name Type Reset

Bit

14

Name GPIO_MODE1_SET

000000D6

Bit(s) 15:0

Description 7: Reserved

0

1

0

0

1

0

0

1

0

0

0

1

Description Selects GPIO 11 mode 0: GPIO11 (IO) 1: AUD_DATA_MOSI2 (I) 2: Reserved 3: Reserved 4: Reserved 5: Reserved 6: TEST_IN6(I) 7: TEST_OUT6(O) Selects GPIO 10 mode 0: GPIO10 (IO) 1: AUD_DAT_MOSI1 (I) 2: Reserved 3: Reserved 4: Reserved 5: Reserved 6: TEST_IN5(I) 7: TEST_OUT5(O) Selects GPIO 9 mode © 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 110 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

2:0

Name

GPIO8_MODE

000000DA

GPIO_MODE2_SET 15

Bit Name Type Reset Bit(s) 15:0

0

0

0

12

0

0

GPIO_MODE2 Register SET 11

0

14

0

9

6

5

4

3

2

1

0

0

GPIO_MODE2_SET W1 0 0 0 0

0

0

0

0

0

0

14

13

12

0

Name Type Reset

13

0

GPIO_MODE2 Register CLR 11

0

MediaTek Proprietary and Confidential.

8

7

0000

10

9

6

5

4

3

2

1

0

0

GPIO_MODE2_CLR W1 0 0 0 0

0

0

0

0

0

0

4

3

2

1

Description 1'b0: Not clear 1'b1: Clear

GPIO Mode Control Register 3 12

11

10

9

8

7

6

0249

5

0

GPIO15_MODE

GPIO14_MODE

GPIO13_MODE

GPIO12_MODE

RW

RW

RW

RW

0

Name GPIO15_MODE

7

Description 1'b0: Not set 1'b1: Set

GPIO_MODE3 15

8

0000

10

Name GPIO_MODE2_CLR

000000DE

Bit(s) 11:9

13

GPIO_MODE2_CLR 15

Bit Name Type Reset

Bit

14

Name GPIO_MODE2_SET

000000DC

Bit(s) 15:0

Description 0: GPIO9 (IO) 1: AUD_DAT_MOSI0 (I) 2: Reserved 3: Reserved 4: Reserved 5: Reserved 6: TEST_IN4(I) 7: TEST_OUT4(O) Selects GPIO 8 mode 0: GPIO8 (IO) 1:AUD_CLK_MOSI (I) 2: Reserved 3: Reserved 4: Reserved 5: TEST_CK0 (I) 6: Reserved 7: Reserved

0

1

0

0

1

0

0

1

0

0

1

Description Selects GPIO 15 mode 0: GPIO13 (IO) 1: AUD_DAT_MISO0 (O) © 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 111 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

8:6

GPIO14_MODE

5:3

GPIO13_MODE

2:0

GPIO12_MODE

000000E0

Bit(s) 15:0

GPIO_MODE3_SET 15

Bit Name Type Reset

0

14

0

13

0

12

0

GPIO_MODE3 Register SET 11

0

9

6

5

4

3

2

1

0

0

GPIO_MODE3_SET W1 0 0 0 0

0

0

0

0

0

0

0

14

0

MediaTek Proprietary and Confidential.

13

0

7

Description 1'b0: Not set 1'b1: Set

GPIO_MODE3_CLR 15

8

0000

10

Name GPIO_MODE3_SET

000000E2 Bit Name Type Reset

Description 2: Reserved 3: Dummy 0 4: VOW_DAT_MISO (O) 5: Reserved 6: TEST_IN10(I) 7: TEST_OUT10(O) Selects GPIO 14 mode 0: GPIO15 (IO) 1: AUD_NLE_MOSI1 (I) 2: AUD_CLK_MISO (O) 3: Reserved 4: Reserved 5: Reserved 6: TEST_IN9(I) 7: TEST_OUT9(O) Selects GPIO 13 mode 0: GPIO15 (IO) 1: AUD_NLE_MOSI0 (I) 2: AUD_SYNC_MISO (O) 3: Reserved 4: Reserved 5: Reserved 6: TEST_IN8(I) 7: TEST_OUT8(O) Selects GPIO 12 mode 0: GPIO12 (IO) 1:AUD_SYNC_MOSI (I) 2: Reserved 3: Reserved 4: Reserved 5: Reserved 6: TEST_IN7 (I) 7: TEST_OUT7 (O)

12

0

GPIO_MODE3 Register CLR 11

0

8

7

0000

10

9

6

5

4

3

2

1

0

0

GPIO_MODE3_CLR W1 0 0 0 0

0

0

0

0

0

0

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 112 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 15:0

Name GPIO_MODE3_CLR

000000E4 Bit

Description 1'b0: Not clear 1'b1: Clear

GPIO_MODE4 15

14

Name Type Reset

13

GPIO Mode Control Register 4 12

11

10

9

GPIO19_MODE

8

Bit(s) 11:9

Name GPIO19_MODE

8:6

GPIO18_MODE

5:3

GPIO17_MODE

2:0

GPIO16_MODE

MediaTek Proprietary and Confidential.

0

6

GPIO18_MODE

RW 0

7

0249

5

0

0

3

GPIO17_MODE

RW 1

4

2

0

0

0

GPIO16_MODE

RW 1

1 RW

1

0

0

1

Description Selects GPIO 19 mode 0: GPIO18 (IO) 1: SCP_VREQ_VAO (I) 2: Reserved 3: Reserved 4: Reserved 5: TEST_CK3 6: Reserved 7: Reserved Selects GPIO 18 mode 0: GPIO18 (IO) 1: HOMEKEY (I) 2: Reserved 3: Reserved 4: Reserved 5: TEST_CK2 6: Reserved 7: Reserved Selects GPIO 17 mode 0: GPIO14 (IO) 1: AUD_DAT_MISO2 (O) 2: Reserved 3: Reserved 4: Reserved 5: Reserved 6: TEST_IN11(I) 7: TEST_OUT11(O) Selects GPIO 16 mode 0: GPIO14 (IO) 1: AUD_DAT_MISO1 (O) 2: Reserved 3: Dummy 1 4: VOW_CLK_MISO (O) 5: TEST_CK1 (I) 6: Reserved 7: Reserved

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 113 of 1067

MT6359 PMIC Datasheet Confidential A 000000E6

Bit(s) 15:0

GPIO_MODE4_SET 15

Bit Name Type Reset

0

0

13

12

0

0

GPIO_MODE4 Register SET 11

0

9

6

5

4

3

2

1

0

0

GPIO_MODE4_SET W1 0 0 0 0

0

0

0

0

0

0

Bit Name Type Reset

0

14

0

13

12

0

0

GPIO_MODE4 Register CLR 11

0

9

6

5

4

3

2

1

0

0

GPIO_MODE4_CLR W1 0 0 0 0

0

0

0

0

0

0

14

7

Description 1'b0: Not clear 1'b1: Clear

GPIO_RSV 15

Bit

8

0000

10

Name GPIO_MODE4_CLR

000000EA

7

Description 1'b0: Not set 1'b1: Set

GPIO_MODE4_CLR 15

8

0000

10

Name GPIO_MODE4_SET

000000E8

Bit(s) 15:0

14

GPIO Reserved

13

12

11

10

9

8

0000 7

6

5

4

3

2

1

Name Type Reset Bit(s) 0

0

Name GPIO_RSV

00000108

0

14

0

13

TOP Parameter 0 12

11

TOP_RST_OFFSET RU 1 1

1

10

1

Name TOP_RST_OFFSET TOP_CLK_OFFSET

0000010A Bit Name Type Reset

Description

TOP_PAM0 15

Bit Name Type Reset Bit(s) 15:8 7:0

0 GPIO_ RSV RW

0

14

0

MediaTek Proprietary and Confidential.

13

0

1

8

0

3E0C 7

6

5

0

0

0

7

6

5

4

3

TOP_CLK_OFFSET RU 0 1

2

1

0

1

0

0

2

1

0

0

0

0

Description Reset setting offset Clock setting offset

TOP_PAM1 15

9

TOP Parameter 1 12

11

TOP_INT_LEN RU 0 0

10

0

9

0

8

1

0188

1

0

0

4

3

TOP_INT_OFFSET RU 0 1

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 114 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 15:8 7:0

Name TOP_INT_LEN TOP_INT_OFFSET

0000010C Bit

Description Interrupt setting length Interrupt setting offset

TOP_CKPDN_CON0 15

14

13

12

RG_RT RG_PM RG_RT C26M_ U128K Name C32K_C CK_PD _CK_P K_PDN N DN RW RW RW Type

Reset

0

0

1

11

Name RG_RTC32K_CK_PDN

14

RG_RTC26M_CK_PDN

13

RG_PMU128K_CK_PDN

11

RG_FQMTR_CK_PDN

10

RG_FQMTR_32K_CK_PDN

9

RG_PMU32K_CK_PDN

8

RG_CK_PDN_RSV2

7

RG_SPI_CK_PDN

6

RG_CK_PDN_RSV1

5

RG_CK_PDN_RSV0

4

RG_EFUSE_CK_PDN

2

RG_INTRP_CK_PDN

0

RG_SCK32K_CK_PDN

10

9

8

7

6

5

2C20 4

RG_FQ RG_PM RG_FQ RG_CK RG_SPI RG_CK RG_CK RG_EF MTR_3 U32K_ MTR_C _PDN_ _CK_P _PDN_ _PDN_ USE_CK 2K_CK_ CK_PD K_PDN RSV2 DN RSV1 RSV0 _PDN PDN N RW RW RW RW RW RW RW RW 1

Bit(s) 15

MediaTek Proprietary and Confidential.

TOP_CKPDN Control Register 0

1

0

0

0

0

1

0

3

2

1

0

RG_INT RP_CK_ PDN

RG_SC K32K_C K_PDN

RW

RW

0

0

Description Powers down RTC32K CK 0: Power on 1: Power down Powers down PMU_26M_CK 0: Power on 1: Power down Powers down PMU128K_CK 0: Power on 1: Power down Powers down FQMTR CK 0: Power on 1: Power down Powers down FQMTR_32K_CK 0: Power on 1: Power down Powers down PMU32K_CK 0: Power on 1: Power down Powers down reserved 0: Power on 1: Power down Powers down SPI_CK 0: Power on 1: Power down Powers down reserved 0: Power on 1: Power down Powers down reserved 0: Power on 1: Power down Powers down EFUSE_CK 0: Power on 1: Power down Powers down INTRP_CK 0: Power on 1: Power down Powers down SCK32K_CK 0: Power on 1: Power down

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 115 of 1067

MT6359 PMIC Datasheet Confidential A 0000010E

Bit(s) 15:0

TOP_CKPDN_CON0_SET 15

Bit Name Type Reset

0

12

0

0

11

0

TOP_CKPDN_CON0 Register SET

0

14

0

13

12

0

0

9

6

5

4

3

2

1

0

0

TOP_CKPDN_CON0_SET W1 0 0 0 0

0

0

0

0

0

0

11

0

TOP_CKPDN_CON0 Register CLR

14

13

12

8

7

0000

10

9

6

5

4

3

2

1

0

0

TOP_CKPDN_CON0_CLR W1 0 0 0 0

0

0

0

0

0

0

Description Clears TOP_CKPDN_CON0 1'b0: Not clear 1'b1: Clear

TOP_CKPDN_CON1 15

7

Description Sets up TOP_CKPDN_CON0 1'b0: Not set 1'b1: Set

Name TOP_CKPDN_CON0_CLR

00000112

8

0000

10

TOP_CKPDN_CON0_CLR 15

Bit Name Type Reset

Bit

0

13

Name TOP_CKPDN_CON0_SET

00000110

Bit(s) 15:0

14

TOP_CKPDN Control Register 1 11

10

9

8

7

6

5

001A 4

3

2

1

0

RG_PC RG_BG RG_TRI RG_RT RG_RT HR_TES R_TEST M_128 C32K_1 C32K_1 T_CK_P _CK_P K_CK_P V8_1_P V8_0_P DN DN DN DN DN RW RW RW RW RW

Name Type Reset

1

Bit(s) 4

Name RG_PCHR_TEST_CK_PDN

3

RG_BGR_TEST_CK_PDN

2

RG_TRIM_128K_CK_PDN

1

RG_RTC32K_1V8_1_PDN

0

RG_RTC32K_1V8_0_PDN

MediaTek Proprietary and Confidential.

1

0

1

0

Description Powers down BGR_TEST_CK 0: Power on 1: Power down Powers down BGR_TEST_CK 0: Power on 1: Power down Powers down TRIM_128K_CK 0: Power on 1: Power down Powers down RTC32K_1V8_1 0: Power on 1: Power down Powers down RTC32K_1V8_0 0: Power on 1: Power down

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 116 of 1067

MT6359 PMIC Datasheet Confidential A 00000114

Bit(s) 15:0

TOP_CKPDN_CON1_SET 15

Bit Name Type Reset

0

12

0

0

0

0

TOP_CKPDN_CON1 Register SET

14

0

13

12

0

0

9

6

5

4

3

2

1

0

0

TOP_CKPDN_CON1_SET W1 0 0 0 0

0

0

0

0

0

0

14

13

12

Name

RG_TOP_CKSEL_CON0_RSV

Type Reset

RW 0

0

0

0

Name RG_TOP_CKSEL_CON0_RSV RG_PMU32K_CK_CKSEL

3

RG_RTC_32K1V8_SEL

2:0

RG_FQMTR_CK_CKSEL

MediaTek Proprietary and Confidential.

7

Description Sets up TOP_CKPDN_CON1 1'b0: Not set 1'b1: Set

11

0

TOP_CKPDN_CON1 Register CLR 8

7

0000

10

9

6

5

4

3

2

1

0

0

TOP_CKPDN_CON1_CLR W1 0 0 0 0

0

0

0

0

0

0

Description Clears TOP_CKPDN_CON1 1'b0: Not clear 1'b1: Clear

TOP_CKSEL_CON0 15

8

0000

10

Name TOP_CKPDN_CON1_CLR

00000118

Bit(s) 15:11 10

11

TOP_CKPDN_CON1_CLR 15

Bit Name Type Reset

Bit

0

13

Name TOP_CKPDN_CON1_SET

00000116

Bit(s) 15:0

14

TOP_CKSEL Control Register 0 11

10

9

8

7

6

0008 5

4

RG_PM U32K_ CK_CKS EL RW 0

0

3

2

1

0

RG_RT C_32K1 RG_FQMTR_CK_CKSEL V8_SEL RW 1

RW 0

0

0

Description Selects TOP clock Selects RTC 32K clock 1'b0: R_RTC_32K_CK 1'b1: R_PMU32K_CK Selects RTC_32K1V8_CK clock 1'b0: R_PMU32K_CK 1'b1: R_RTC32K_CK Selects FQMTR_CK clock 3'b000: R_RTC_26M_CK 3'b001: R_XOSC32_CK_DETECTION 3'b010: R_EOSC32_CK 3'b011: R_RTC32K_CK 3'b100: R_DCXO1M_CK 3'b101: R_RTC_TICK_SEC 3'b11x: R_PMU32K_CK

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 117 of 1067

MT6359 PMIC Datasheet Confidential A 0000011A

Bit(s) 15:0

TOP_CKSEL_CON0_SET 15

Bit Name Type Reset

0

0

0

0

TOP_CKSEL_CON0 Register SET

14

0

13

9

0

14

0

0

13

6

5

4

3

2

1

0

0

TOP_CKSEL_CON0_SET W1 0 0 0 0

0

0

0

0

0

0

11

0

TOP_CKSEL_CON0 Register CLR 9

6

5

4

3

2

1

0

0

TOP_CKSEL_CON0_CLR W1 0 0 0 0

0

0

0

0

0

0

0

11

0

0

14

0

13

9

6

5

4

3

2

1

0

0

TOP_CKSEL_CON1_SET W1 0 0 0 0

0

Name TOP_CKSEL_CON1_CLR

MediaTek Proprietary and Confidential.

7

0

0

0

0

0

0

Description Sets up TOP_CKSEL_CON2 1'b0: Not set 1'b1: Set

12

0

8

0000

10

TOP_CKSEL_CON1_CLR 15

7

TOP_CKSEL_CON1 Register SET

Name TOP_CKSEL_CON1_SET

00000122

8

0000

10

Description Clears TOP_CKSEL_CON0 1'b0: Not clear 1'b1: Clear

12

0

7

Description Sets up TOP_CKSEL_CON0 1'b0: Not set 1'b1: Set

12

0

8

0000

10

TOP_CKSEL_CON1_SET 15

Bit Name Type Reset

Bit(s) 15:0

0

11

Name TOP_CKSEL_CON0_CLR

00000120

Bit Name Type Reset

12

TOP_CKSEL_CON0_CLR 15

Bit Name Type Reset

Bit(s) 15:0

0

13

Name TOP_CKSEL_CON0_SET

0000011C

Bit(s) 15:0

14

11

0

TOP_CKSEL_CON1 Register CLR 8

7

0000

10

9

6

5

4

3

2

1

0

0

TOP_CKSEL_CON1_CLR W1 0 0 0 0

0

0

0

0

0

0

Description Clears TOP_CKSEL_CON2 1'b0: Not clear 1'b1: Clear

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 118 of 1067

MT6359 PMIC Datasheet Confidential A 00000124

TOP_CKDIVSEL_CON0 15

Bit Name

0

9

8

7

6

5

0000 4

3

2

0

0

0

0

14

0

13

0

12

0

0

14

0

13

0

11

0

TOP_CKDIVSEL_CON0 Register SET

14

13

7

6

5

4

3

2

1

0

0

TOP_CKDIVSEL_CON0_SET W1 0 0 0 0

0

0

0

0

0

0

Description Sets up TOP_CKDIVSEL_CON0 1'b0: Not set 1'b1: Set

11

0

12

8

0000

9

0

TOP_CKDIVSEL_CON0 Register CLR 10

0

9

8

7

0000

6

5

4

3

2

1

0

TOP_CKDIVSEL_CON0_CLR W1 0 0 0 0

0

0

0

0

0

0

Description Clears TOP_CKDIVSEL_CON0 1'b0: Not clear 1'b1: Clear

TOP_CKHWEN_CON0 15

11

TOP_CKHWEN Control Register 0 10

9

8

7

6

5

002C 4

RG_RT C26M_ CK_PD N_HWE N RW

Name

Type Reset

1

Name RG_RTC26M_CK_PDN_HWEN

MediaTek Proprietary and Confidential.

0

10

Name TOP_CKDIVSEL_CON0_CLR

0000012A

0

Selects REG_CK divider 2'b00: DIV1 2'b01: DIV2 2'b10: DIV4 2'b11: DIV8

0

12

0

Description

TOP_CKDIVSEL_CON0_CLR 15

1

RG_REG_CK_DI VSEL RW

Name TOP_CKDIVSEL_CON0_SET

Bit Name Type Reset

Bit(s) 5

TOP_CKDIVSEL Control Register 0 10

TOP_CKDIVSEL_CON0_SET 15

00000128

Bit

11

Name TOP_CKDIVSEL_CON0_RSV RG_REG_CK_DIVSEL

Bit Name Type Reset

Bit(s) 15:0

12

RW 0

00000126

Bit(s) 15:0

13

TOP_CKDIVSEL_CON0_RSV

Type Reset Bit(s) 15:10 1:0

14

3

2

1

0

RG_EIN RG_EF T_32K_ USE_CK CK_PD _PDN_ N_HWE HWEN N RW RW 1

1

Description RTC26M_CK power down control 0: SW mode

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 119 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

3

RG_EINT_32K_CK_PDN_HWEN

2

RG_EFUSE_CK_PDN_HWEN

0000012C

Bit(s) 15:0

TOP_CKHWEN_CON0_SET 15

Bit Name Type Reset

0

0

13

12

0

0

11

0

TOP_CKHWEN_CON0 Register SET

0

14

0

13

12

0

0

9

6

5

4

3

2

1

0

0

TOP_CKHWEN_CON0_SET W1 0 0 0 0

0

0

0

0

0

0

11

0

TOP_CKHWEN_CON0 Register CLR

14

13

12

RG_PWRKEY_R ST_TD

Name Type Reset

RW 0

0

Bit(s) 13:12

Name RG_PWRKEY_RST_TD

9

RG_PWRKEY_RST_EN

8

RG_PWRKEY_KEY_MODE

MediaTek Proprietary and Confidential.

8

7

0000

10

9

6

5

4

3

2

1

0

0

TOP_CKHWEN_CON0_CLR W1 0 0 0 0

0

0

0

0

0

0

5

4

3

2

1

Description Clears TOP_CKHWEN_CON0 1'b0: Not clear 1'b1: Clear

TOP_RST_MISC 15

7

Description Sets up TOP_CKHWEN_CON0 1'b0: Not set 1'b1: Set

Name TOP_CKHWEN_CON0_CLR

0000014A

8

0000

10

TOP_CKHWEN_CON0_CLR 15

Bit Name Type Reset

Bit

14

Name TOP_CKHWEN_CON0_SET

0000012E

Bit(s) 15:0

Description 1: HW mode EINT_32K_CK power down control 0: SW mode 1: HW mode EFUSE_CK power down control 0: SW mode 1: HW mode

Reset Control MISC 11

10

9

8

RG_PW RG_PW RKEY_K RKEY_R EY_MO ST_EN DE RW RW 1

1

7

0300 6

RG_W DTRST B_DEB RW 0

WDTRS WDTRS TB_STA TB_STA TUS_CL TUS R RW RO 0

0

0 RG_W DTRST B_EN RW 0

Description Long pressed time to issue reset 2'b00: 8 sec 2'b01: 11 sec 2'b10: 14 sec 2'b11: 5 sec Enables PWRKEY long pressed reset 1'b1: Enable reset 1'b0: Disable reset Selects long pressed key mode

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 120 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

5

RG_WDTRSTB_DEB

3

WDTRSTB_STATUS_CLR

2

WDTRSTB_STATUS

0

RG_WDTRSTB_EN

0000014C

Bit(s) 15:0

TOP_RST_MISC_SET 15

Bit Name Type Reset

0

0

13

12

0

0

11

0

0

14

0

13

9

6

5

4

3

2

1

0

0

TOP_RST_MISC_SET W1 0 0 0 0

0

0

0

0

0

0

0

Reset Control MISC CLR 11

0

9

6

5

4

3

2

1

0

0

TOP_RST_MISC_CLR W1 0 0 0 0

0

0

0

0

0

0

14

13

7

5

4

3

2

1

Description Clears TOP_RST_MISC 1'b0: Not clear 1'b1: Clear

MISC_TOP_INT_CON0 15

8

0000

10

Name TOP_RST_MISC_CLR

00000188

7

Description Sets up TOP_RST_MISC 1'b0: Not set 1'b1: Set

12

0

8

0000

10

TOP_RST_MISC_CLR 15

Bit Name Type Reset

Bit

14

Reset Control MISC SET

Name TOP_RST_MISC_SET

0000014E

Bit(s) 15:0

Description 1'b0: PWRKEY 1'b1:PWRKEY + HOMEKEY Enables WDTRSTB debounce 1'b0: No debounce 1'b1: Add debounce 1.6ms Write 1 to clear WDTRSTB_STATUS. 0: No function 1: Clear WDTRSTB_STATUS WDTRSTB reset status 1'b0: Not occur 1'b1: Occur WDTRSTB (external watchdog) reset from AP 1'b0: Disable 1'b1: Enable

12

11

TOP INT Control Register 0 10

9

8

7

6

0000 RG_INT _EN_S PI_CM D_ALE RT RW

Name Type Reset Bit(s) 0

0

0

Name RG_INT_EN_SPI_CMD_ALERT

MediaTek Proprietary and Confidential.

Description SPI_CMD_ALERT interrupt enable

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 121 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

0000018E

MISC_TOP_INT_MASK_CON0 MISC INT Mask Control Register 0 15

Bit

Description 0: Not issue interrupt 1: Issue interrupt

14

13

12

11

10

9

8

7

6

5

0000 4

3

2

1

Name

Type Reset Bit(s) 0

0

Name RG_INT_MASK_SPI_CMD_ALERT

00000194

Description Masks SPI_CMD_ALERT interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status

MISC_TOP_INT_STATUS0 15

Bit

14

13

12

11

MISC TOP INT Status Register 0 10

9

8

7

6

5

0000 4

3

2

1

Type Reset

0

Name RG_INT_STATUS_SPI_CMD_ALERT

00000196 Bit

Description SPI_CMD_ALERT interrupt status 0: No interrupt issued 1: Interrupt issued

MISC_TOP_INT_RAW_STATU MISC TOP INT Raw Status Register 0 S0 15

14

13

12

11

10

9

8

7

6

5

0000 4

3

2

1

0 RG_INT _RAW_ STATU S_SPI_ CMD_ ALERT RO

Name

Type Reset Bit(s) 0

0 RG_INT _STAT US_SPI _CMD_ ALERT W1C

Name

Bit(s) 0

0 RG_INT _MASK _SPI_C MD_AL ERT RW

0

Name RG_INT_RAW_STATUS_SPI_CMD_AL ERT

MediaTek Proprietary and Confidential.

Description SPI_CMD_ALERT raw interrupt status 0: No interrupt issued 1: Interrupt issued

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 122 of 1067

MT6359 PMIC Datasheet Confidential A 00000198

TOP_INT_MASK_CON0 15

Bit

14

13

12

11

TOP_INT_MASK Control Register 0 10

9

7

6

5

01FF 4

3

2

1

0

RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT _MASK _MASK _MASK _MASK _MASK _MASK _MASK _MASK _MASK _MISC_ _AUD_ _XPP_T _HK_T _BM_T _SCK_T _PSC_T _LDO_ _BUCK TOP TOP OP OP OP OP OP TOP _TOP RW RW RW RW RW RW RW RW RW

Name Type Reset

1

Bit(s) 8

Name RG_INT_MASK_MISC_TOP

7

RG_INT_MASK_AUD_TOP

6

RG_INT_MASK_XPP_TOP

5

RG_INT_MASK_HK_TOP

4

RG_INT_MASK_BM_TOP

3

RG_INT_MASK_SCK_TOP

2

RG_INT_MASK_PSC_TOP

1

RG_INT_MASK_LDO_TOP

0

RG_INT_MASK_BUCK_TOP

0000019A

0

14

0

13

0

12

0

11

0

TOP_INT_MASK_CON0_CLR

MediaTek Proprietary and Confidential.

1

1

1

1

1

1

TOP_INT_MASK Control Register SET

10

Name TOP_INT_MASK_CON0_SET

0000019C

1

1

Description Interrupt mask for TOP 0: Unmask interrupt 1: Mask interrupt Interrupt mask for AUD 0: Unmask interrupt 1: Mask interrupt Interrupt mask for XPP 0: Unmask interrupt 1: Mask interrupt Interrupt mask for HK 0: Unmask interrupt 1: Mask interrupt Interrupt mask for BM 0: Unmask interrupt 1: Mask interrupt Interrupt mask for SCK 0: Unmask interrupt 1: Mask interrupt Interrupt mask for LDO 0: Unmask interrupt 1: Mask interrupt Interrupt mask for BUCK 0: Unmask interrupt 1: Mask interrupt Sets up TOP_INTM_CON0 0: Unmask interrupt 1: Mask interrupt

TOP_INT_MASK_CON0_SET 15

Bit Name Type Reset Bit(s) 15:0

8

0

9

8

7

6

TOP_INT_MASK_CON0_SET W1 0 0 0 0

0000

5

4

3

2

1

0

0

0

0

0

0

0

Description Clears TOP_INTM_CON0 1'b0: Not set 1'b1: Set

TOP_INT_MASK Control Register CLR

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

0000

Page 123 of 1067

MT6359 PMIC Datasheet Confidential A 15

Bit Name Type Reset Bit(s) 15:0

0

0

13

12

0

0

11

0

10

0

Name TOP_INT_MASK_CON0_CLR

0000019E Bit

14

14

13

12

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

5

4

3

2

1

Description 1'b0: Not clear 1'b1: Clear

TOP_INT_STATUS0 15

9

TOP_INT_MASK_CON0_CLR W1 0 0 0 0

TOP_INT_STATUS Register 0 11

10

9

8

7

6

0000 0

INT_ST INT_ST INT_ST INT_ST INT_ST INT_ST INT_ST INT_ST INT_ST ATUS_ ATUS_ ATUS_ ATUS_ ATUS_ ATUS_S ATUS_ ATUS_L ATUS_ MISC_T AUD_T XPP_T HK_TO BM_TO CK_TO PSC_T DO_TO BUCK_ OP OP OP P P P OP P TOP RO RO RO RO RO RO RO RO RO

Name Type Reset

0

Bit(s) 8

Name INT_STATUS_MISC_TOP

7

INT_STATUS_AUD_TOP

6

INT_STATUS_XPP_TOP

5

INT_STATUS_HK_TOP

4

INT_STATUS_BM_TOP

3

INT_STATUS_SCK_TOP

2

INT_STATUS_PSC_TOP

1

INT_STATUS_LDO_TOP

0

INT_STATUS_BUCK_TOP

MediaTek Proprietary and Confidential.

0

0

0

0

0

0

0

0

Description Interrupt mask for TOP 0: Unmask interrupt 1: Mask interrupt Interrupt mask for AUD 0: Unmask interrupt 1: Mask interrupt Interrupt mask for XPP 0: Unmask interrupt 1: Mask interrupt Interrupt mask for HK 0: Unmask interrupt 1: Mask interrupt Interrupt mask for BM 0: Unmask interrupt 1: Mask interrupt Interrupt mask for SCK 0: Unmask interrupt 1: Mask interrupt Interrupt mask for LDO 0: Unmask interrupt 1: Mask interrupt Interrupt mask for BUCK 0: Unmask interrupt 1: Mask interrupt Sets up TOP_INTM_CON0 0: Unmask interrupt 1: Mask interrupt

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 124 of 1067

MT6359 PMIC Datasheet Confidential A 000001A0

TOP_INT_RAW_STATUS0 15

Bit

14

13

12

11

TOP_INT_RAQ_STATUS Register 0 10

9

7

6

5

0000 4

3

2

1

0

INT_RA INT_RA INT_RA INT_RA INT_RA INT_RA INT_RA INT_RA INT_RA W_STA W_STA W_STA W_STA W_STA W_STA W_STA W_STA W_STA TUS_M TUS_A TUS_X TUS_B TUS_H TUS_B TUS_SC TUS_PS TUS_LD ISC_TO UD_TO PP_TO UCK_T K_TOP M_TOP K_TOP C_TOP O_TOP P P P OP RO RO RO RO RO RO RO RO RO

Name Type Reset

0

Bit(s) 8

Name INT_RAW_STATUS_MISC_TOP

7

INT_RAW_STATUS_AUD_TOP

6

INT_RAW_STATUS_XPP_TOP

5

INT_RAW_STATUS_HK_TOP

4

INT_RAW_STATUS_BM_TOP

3

INT_RAW_STATUS_SCK_TOP

2

INT_RAW_STATUS_PSC_TOP

1

INT_RAW_STATUS_LDO_TOP

0

INT_RAW_STATUS_BUCK_TOP

00000388 Bit

8

14

13

0

Bit(s) 14:9

Name DA_OSC_128K_TRIM

0

0

0

0

0

5

4

3

2

1

TOP_CLK_TRIM Register

12

Name Type Reset

0

0

Description Interrupt mask for TOP 0: Unmask interrupt 1: Mask interrupt Interrupt mask for AUD 0: Unmask interrupt 1: Mask interrupt Interrupt mask for XPP 0: Unmask interrupt 1: Mask interrupt Interrupt mask for HK 0: Unmask interrupt 1: Mask interrupt Interrupt mask for BM 0: Unmask interrupt 1: Mask interrupt Interrupt mask for SCK 0: Unmask interrupt 1: Mask interrupt Interrupt mask for LDO 0: Unmask interrupt 1: Mask interrupt Interrupt mask for BUCK 0: Unmask interrupt 1: Mask interrupt Sets up TOP_INTM_CON0 0: Unmask interrupt 1: Mask interrupt

TOP_CLK_TRIM 15

0

11

10

9

0

0

8

7

6

00C0 0

DA_OSC_128K_TRIM RO

MediaTek Proprietary and Confidential.

0

0

0

Description 128kHz OSC trimming bit

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 125 of 1067

MT6359 PMIC Datasheet Confidential A 0000038A

OTP_CON0 15

Bit

14

13

OTP Control Register 0 12

11

10

9

8

Name Type Reset Bit(s) 7:0

0000 6

5

4

3

2

1

0

0

RG_OTP_PA RW 0

Name RG_OTP_PA

0000038C

14

0

0

0

0

0

0

6

5

4

3

2

1

0

0

Description OTP PA

OTP_CON1 15

Bit

13

OTP Control Register 1 12

11

10

9

8

Name Type Reset Bit(s) 7:0

7

7

0000 RG_OTP_PDIN RW

0

Name RG_OTP_PDIN

0000038E

14

0

0

0

0

0

6

5

4

3

2

1

Description OTP PDIN

OTP_CON2 15

Bit

0

13

OTP Control Register 2 12

11

10

9

8

7

0000

Name Type Reset Bit(s) 1:0

RG_OTP_PTM RW 0

Name RG_OTP_PTM

00000390

14

13

OTP Control Register 3 12

11

10

9

8

7

0000 6

5

4

3

2

Name Type Reset

0 RW

0

Name RG_OTP_PWE

OTP_CON4 15

14

0

Description OTP PWE

13

OTP Control Register 4 12

11

10

9

8

7

0000 6

5

4

3

2

1

0 RG_OT P_PPR OG RW

Name Type Reset Bit(s) 0

1

RG_OTP_PWE

00000392 Bit

0

Description OTP PTM

OTP_CON3 15

Bit

Bit(s) 1:0

0

0

Name RG_OTP_PPROG

MediaTek Proprietary and Confidential.

Description OTP PPROG

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 126 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00000394

OTP_CON5 15

Bit

Description

14

13

OTP Control Register 5 12

11

10

9

8

7

0000 6

5

4

3

2

1

Name Type Reset Bit(s) 0

0

Name RG_OTP_PWE_SRC

00000396

0

0

13

OTP Control Register 6 12

0

0

11

0

0

14

0

13

9

6

5

4

3

2

1

0

0

RG_OTP_PROG_PKEY RW 0 0 0 0

0

0

0

0

0

0

OTP Control Register 7

0

11

0

9

6

5

4

3

2

1

0

0

RG_OTP_RD_PKEY RW 0 0 0 0

0

0

0

0

0

0

14

13

7

Description OTP read match key

OTP_CON8 15

8

0000

10

Name RG_OTP_RD_PKEY

0000039A

7

Description OTP write (fusing) match key

12

0

8

0000

10

OTP_CON7 15

Bit Name Type Reset

Bit

14

Name RG_OTP_PROG_PKEY

00000398

Bit(s) 15:0

Description Selects OTP write (fusing) PWE source 0: From IO pad 1: From register

OTP_CON6 15

Bit Name Type Reset Bit(s) 15:0

OTP Control Register 8 12

11

10

9

8

7

0000 6

5

4

3

2

1

0 RG_OT P_RD_ TRIG RW

Name Type Reset Bit(s) 0

0 RG_OT P_PWE _SRC RW

0

Name RG_OTP_RD_TRIG

MediaTek Proprietary and Confidential.

Description Triggers OTP SW read

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 127 of 1067

MT6359 PMIC Datasheet Confidential A 0000039C

OTP_CON9 15

Bit

14

13

OTP Control Register 9 12

11

10

9

8

7

0000 6

5

4

3

2

1

Name Type Reset Bit(s) 0

0

Name RG_RD_RDY_BYPASS

0000039E

Description Bypasses OTP read ready delay 0: Not bypass 1: Bypass

OTP_CON10 15

Bit

14

13

OTP Control Register 10 12

11

10

9

8

7

6

0000 5

4

3

2

1

Type Reset

0

Name RG_SKIP_OTP_OUT

000003A0

Description Skips reading from EFUSE macro 0: Not skip 1: Skip

OTP_CON11 15

Bit

14

13

OTP Control Register 11 12

11

10

9

8

7

6

0000 5

4

3

2

1

Type Reset

0

Name RG_OTP_RD_SW

000003A2

0

0

0

Bit Name Type 0 Reset Bit(s) 15:0

0 RG_OT P_RD_ SW RW

Name

Bit(s) 0

0 RG_SKI P_OTP _OUT RW

Name

Bit(s) 0

0 RG_RD _RDY_ BYPAS S RW

Description SW trigger read mode 0: Not SW trigger read mode 1: SW trigger read mode

OTP_CON12 15

14

13

OTP Control Register 12 12

11

10

9

8

7

6

0000 5

4

3

2

1

0

0

0

0

RG_OTP_DOUT_SW RO

Name RG_OTP_DOUT_SW

MediaTek Proprietary and Confidential.

Description Current SW trigger read value

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Page 128 of 1067

MT6359 PMIC Datasheet Confidential A 000003A4

OTP_CON13 15

Bit

14

13

OTP Control Register 13 12

11

10

9

8

7

6

0000 5

4

3

Name Type Reset Bit(s) 2 0

Name RG_OTP_RD_ACK RG_OTP_RD_BUSY

000003A6

14

13

11

10

9

8

7

6

0

0

0000 5

4

3

2

1

0

0

RO 0

Name RG_OTP_PA_SW

SCK_TOP_CKPDN_CON0 15

14

0

0

0

0

0

4

3

2

1

Description Current SW trigger read row

13

12

11

SCK_CKPDN Control Register 0 10

9

8

7

6

5

004B 0

RG_RT RG_EO RG_RT RG_RT RG_RT RG_RT RG_RT RG_RT C_2SEC RG_RT SC_CAL C_INTR C_26M C_32K_ C_SEC_ C_EOSC C_SEC_ _OFF_ C_MCL I_TEST P_CK_P _CK_P CK_PD 32K_CK 32_CK_ MCLK_ DET_P K_PDN _CK_P DN DN N _PDN PDN PDN DN DN RW RW RW RW RW RW RW RW RW

Name

Type Reset Bit(s) 8

RG_OT P_RD_ BUSY RO

RG_OTP_PA_SW

00000514 Bit

0

RG_OT P_RD_ ACK RO

OTP Control Register 14 12

Name Type Reset Bit(s) 6:0

1

Description OTP read ack OTP busy status

OTP_CON14 15

Bit

2

0

Name RG_RTC_INTRP_CK_PDN

7

RG_RTC_2SEC_OFF_DET_PDN

6

RG_RTC_26M_CK_PDN

5

RG_RTC_32K_CK_PDN

4

RG_RTC_MCLK_PDN

3

RG_RTC_SEC_32K_CK_PDN

2

RG_RTC_EOSC32_CK_PDN

MediaTek Proprietary and Confidential.

0

1

0

0

1

0

1

1

Description Powers down RTC_2SEC_OFF_DET 0: Power on 1: Power down Powers down RTC_26M_CK 0: Power on 1: Power down Powers down RTC_26M_CK 0: Power on 1: Power down Powers down RTC_32K_CK 0: Power on 1: Power down Powers down RTC_MCLK 0: Power on 1: Power down Powers down RTC_SEC_32K_CK 0: Power on 1: Power down Powers down RTC_EOSC32_CK 0: Power on

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Page 129 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

1

RG_EOSC_CALI_TEST_CK_PDN

0

RG_RTC_SEC_MCLK_PDN

00000516

SCK_TOP_CKPDN_CON0_SET SCK_CKPDN Control Register 0 SET 15

Bit

Description 1: Power down Powers down EOSC_CALI_TEST_CK 0: Power on 1: Power down Powers down RTC_SEC_MCLK 0: Power on 1: Power down

14

13

12

11

10

9

8

Name Type Reset Bit(s) 7:0

Name SCK_TOP_CKPDN_CON0_SET

0000 4

3

2

1

0

0

0

0

0

0

0

0

4

3

2

1

0

0

Description Sets up SCK_TOP_CKPDN_CON0 1'b0: Not set 1'b1: Set

SCK_TOP_CKPDN_CON0_CLR SCK_CKPDN Control Register 0 CLR 15

14

13

12

11

10

9

8

Name Type Reset

7

6

5

0000

SCK_TOP_CKPDN_CON0_CLR W1 0

Name SCK_TOP_CKPDN_CON0_CLR

0000051A

14

13

12

11

9

8

0

0

0

Bit(s) 15:10

Name RG_RTC_CLK_PDN_HWEN_RSV_0

9:5

RG_RTC_CLK_PDN_HWEN_RSV_1

4

RG_RTC_INTRP_CK_PDN_HWEN

MediaTek Proprietary and Confidential.

7

6

5

RG_RTC_CLK_PDN_HWEN_RSV_1

RW 0

0

0

0

0

0

4

3

2

1

SCK_CKHWEN Control Register 0 10

RG_RTC_CLK_PDN_HWEN_RSV_0

0

0

Description Clears SCK_TOP_CKPDN_CON0 1'b0: Not clear 1'b1: Clear

SCK_TOP_CKHWEN_CON0 15

Name Type Reset

5

W1 0

Bit

Bit

6

SCK_TOP_CKPDN_CON0_SET

00000518

Bit(s) 7:0

7

0

1

1

RW 1

1

1

03F1 0

RG_RT RG_RT RG_RT RG_RT RG_RT C_INTR C_SEC_ C_SEC_ C_26M C_MCL P_CK_P MCLK_ 32K_CK _CK_P K_PDN DN_H PDN_H _PDN_ DN_H _HWEN WEN WEN HWEN WEN RW RW RW RW RW 1 0 0 0 1

Description RESERVED_0 0: SW mode 1: HW mode RESERVED_1 0: SW mode 1: HW mode RESERVED_1 0: SW mode

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Page 130 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

3

RG_RTC_SEC_MCLK_PDN_HWEN

2

RG_RTC_SEC_32K_CK_PDN_HWEN

1

RG_RTC_MCLK_PDN_HWEN

0

RG_RTC_26M_CK_PDN_HWEN

0000051C

Bit(s) 15:0

SCK_TOP_CKHWEN_CON0_SE SCK_CKHWEN_CON Register 0 SET T 15

Bit Name Type Reset

0

13

0

0

12

0

11

0

10

0

9

8

7

6

SCK_TOP_CKHWEN_CON_SET W1 0 0 0 0

0000

5

4

3

2

1

0

0

0

0

0

0

0

Description Sets up SCK_CKHWEN_CON 1'b0: Not set 1'b1: Set

SCK_TOP_CKHWEN_CON0_CL SCK_CKHWEN_CON Register 0 CLR R 15

0

14

13

0

0

12

0

11

0

10

0

Name SCK_TOP_CKHWEN_CON_CLR

00000528 Bit

14

Name SCK_TOP_CKHWEN_CON_SET

0000051E Bit Name Type Reset Bit(s) 15:0

Description 1: HW mode RTC_SEC_MCLK power down control 0: SW mode 1: HW mode RTC_SEC_32K_CK power down control 0: SW mode 1: HW mode RTC_MCLK power down control 0: SW mode 1: HW mode RTC_26M_CK power down control 0: SW mode 1: HW mode

14

13

12

8

7

6

SCK_TOP_CKHWEN_CON_CLR W1 0 0 0 0

5

4

3

2

1

0

0

0

0

0

0

0

4

3

2

1

Description Clears SCK_CKHWEN_CON 1'b0: Not clear 1'b1: Clear

SCK_TOP_INT_CON0 15

9

0000

SCK_TOP INT Control Register 0 11

10

9

8

7

6

5

0000

Name Type Reset Bit(s) 0

0 RG_INT _EN_R TC RW 0

Name RG_INT_EN_RTC

MediaTek Proprietary and Confidential.

Description Enables RTC interrupt 0: Not issue interrupt 1: Issue interrupt © 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 131 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

0000052E

SCK_TOP_INT_MASK_CON0 SCK_TOP INT Mask Control Register 0 15

Bit

Description

14

13

12

11

10

9

8

7

6

5

4

0000 3

2

1

Name Type Reset Bit(s) 0

0

Name RG_INT_MASK_RTC

00000534

Description Masks RTC interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status

SCK_TOP_INT_STATUS0 15

Bit

14

13

12

11

SCK_TOP INT Status Register 0 10

9

8

7

6

5

0000 4

3

2

1

Type Reset

0

Name RG_INT_STATUS_RTC

00000538

Description RTC interrupt status 0: No interrupt issued 1: Interrupt issued

SCK_TOP_INT_MISC_CON 15

Bit

14

13

12

11

SCK_TOP INT MISC Control Register 10

9

8

7

6

5

0000 4

3

2

1

Type Reset

0

Name SCK_TOP_POLARITY

00000588 Bit

Description Inverts interrupt source polarity 0: Not invert interrupt source 1: Invert interrupt source

RTC_BBPU 15

14

13

Name Type Reset

0 SCK_T OP_PO LARITY RW

Name

Bit(s) 0

0 RG_INT _STAT US_RT C W1C

Name

Bit(s) 0

0 RG_INT _MASK _RTC RW

Baseband Power Up 12

11

10

9

8

WO 0

MediaTek Proprietary and Confidential.

0

0

0

0000 6

5

4

3

2

1

0

ALARM RELOA _STAT CBUSY CLRPKY D US RO RO WO WO

KEY_BBPU

0

7

0

0

0

0

0

0

0

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Page 132 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 15:8 7

Name KEY_BBPU ALARM_STATUS

6

CBUSY

5

RELOAD

4

CLRPKY

0000058A

RTC_IRQ_STA 15

Bit

Description A bus write is acceptable only when KEY_BBPU = 0x43. Records ALARM status 1: ALARM had happened. The read/write channels between RTC/Core is busy. This bit indicates high after software program sequence to anyone of RTC data registers and enable the transfer by RTC_WRTGR = 1. It will be high after the reset from low to high because of RTC reload process. Reloads the values from RTC domain to core domain RTC will reload synchronizing the data from RTC to core when reset from 0 to 1. This bit can be treated as a debug bit. Clears powerkey1 and powerkey2 at the same time In some cases, software may clear powerkey1 & powerkey2. BBWAKEUP depends on the matching specific patterns of powerkey1 and powerkey2. If any one of powerkey1 or powerkey2 or BBPU is cleared, BBWAKEUP will be low immediately. Software cannot program other control bits without power. By programming RTC_BBPU with CLRPKY = 1 and BBPU = 0 condition, RTC can clear powerkey1, powerkey2 and BBPU at the same moment.

14

13

RTC IRQ Status 12

11

10

9

8

0000 7

6

5

4

Name Type Reset Name LPSTA

1

TCSTA

0

ALSTA

0000058C

RTC_IRQ_EN 15

14

13

0

TCSTA ALSTA

RO

RO

RO

0

0

0

RTC IRQ Enable 12

11

10

9

8

0000 7

6

5

4

3

2

1

0

ONESH LP_EN TC_EN AL_EN OT RW RW RW RW

Type Reset

2

1

Description Indicates IRQ status and whether or not LPD is asserted 0: No IRQ occurred; the 32K clock is good. 1: IRQ occurred; the 32K clock stops. This can be masked by LP_EN or cleared by initializing LPD. Indicates IRQ status and whether or not the tick condition has been met 0: No IRQ occurred; the tick condition has not been met. 1: IRQ occurred; the tick condition has been met. Indicates IRQ status and whether or not the alarm condition has been met 0: No IRQ occurred; the alarm condition has not been met. 1: IRQ occurred; the alarm condition has been met.

Name

Bit(s) 3

2

LPSTA

Bit(s) 3

Bit

3

0

Name LP_EN

ONESHOT

MediaTek Proprietary and Confidential.

0

0

0

Description Enables the control bit for IRQ generation if low power is detected (32k clock off) 0: Disable IRQ generations 1: Enable the LPD Controls automatic reset of AL_EN and TC_EN

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Page 133 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 1

Name TC_EN

0

AL_EN

0000058E

RTC_CII_EN 15

Bit

Description Enables the control bit for IRQ generation if the tick condition has been met 0: Disable IRQ generations 1: Enable tick time match interrupt. Clear the interrupt when ONESHOT is high upon generation of the corresponding IRQ. Enables the control bit for IRQ generation if the alarm condition has been met 0: Disable IRQ generations 1: Enable alarm time match interrupt. Clear the interrupt when ONESHOT is high upon generation of the corresponding IRQ.

14

13

Counter Increment IRQ Enable 12

11

10

Type Reset

0

Name SECCII_1_8 SECCII_1_4 SECCII_1_2 YEACII MTHCII DOWCII DOMCII HOUCII MINCII SECCII

00000590 Bit

8

7

6

5

0000 4

3

2

1

0

SECCII_ SECCII_ SECCII_ DOWCI DOMCI YEACII MTHCII HOUCII MINCII SECCII 1_8 1_4 1_2 I I RW RW RW RW RW RW RW RW RW RW

Name

Bit(s) 9 8 7 6 5 4 3 2 1 0

9

14

0

0

0

0

0

0

0

0

Description Set the bit to 1 to activate the IRQ at each one-eighth of a second update. Set the bit to 1 to activate the IRQ at each one-fourth of a second update. Set the bit to 1 to activate the IRQ at each one-half of a second update. Set the bit to 1 to activate the IRQ at each year update. Set the bit to 1 to activate the IRQ at each month update. Set the bit to 1 to activate the IRQ at each day-of-week update. Set the bit to 1 to activate the IRQ at each day-of-month update. Set the bit to 1 to activate the IRQ at each hour update. Set the bit to 1 to activate the IRQ at each minute update. Set this bit to 1 to activate the IRQ at each second update.

RTC_AL_MASK 15

0

13

12

RTC Alarm Mask 11

10

9

8

0000 7

6

5

4

3

2

1

0

YEA_M MTH_ DOW_ DOM_ HOU_ MIN_M SEC_M SK MSK MSK MSK MSK SK SK RW RW RW RW RW RW RW

Name Type Reset

0

Bit(s) 6

Name YEA_MSK

5

MTH_MSK

4

DOW_MSK

3

DOM_MSK

MediaTek Proprietary and Confidential.

0

0

0

0

0

0

Description 0: Condition (RTC_TC_YEA = RTC_AL_YEA) is checked to generate the alarm signal. 1: Condition (RTC_TC_YEA = RTC_AL_YEA) is masked, i.e. the value of RTC_TC_YEA does not affect the alarm IRQ generation. 0: Condition (RTC_TC_MTH = RTC_AL_MTH) is checked to generate the alarm signal. 1: Condition (RTC_TC_MTH = RTC_AL_MTH) is masked, i.e. the value of RTC_TC_MTH does not affect the alarm IRQ generation. 0: Condition (RTC_TC_DOW = RTC_AL_DOW) is checked to generate the alarm signal. 1: Condition (RTC_TC_DOW = RTC_AL_DOW) is masked, i.e. the value of RTC_TC_DOW does not affect the alarm IRQ generation. 0: Condition (RTC_TC_DOM = RTC_AL_DOM) is checked to generate the alarm signal.

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Page 134 of 1067

e counter

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

2

HOU_MSK

1

MIN_MSK

0

SEC_MSK

00000592

RTC_TC_SEC 15

Bit

Description 1: Condition (RTC_TC_DOM = RTC_AL_DOM) is masked, i.e. the value of RTC_TC_DOM does not affect the alarm IRQ generation. 0: Condition (RTC_TC_HOU = RTC_AL_HOU) is checked to generate the alarm signal. 1: Condition (RTC_TC_HOU = RTC_AL_HOU) is masked, i.e. the value of RTC_TC_HOU does not affect the alarm IRQ generation. 0: Condition (RTC_TC_MIN = RTC_AL_MIN) is checked to generate the alarm signal. 1: Condition (RTC_TC_MIN = RTC_AL_MIN) is masked, i.e. the value of RTC_TC_MIN does not affect the alarm IRQ generation. 0: Condition (RTC_TC_SEC = RTC_AL_SEC) is checked to generate the alarm signal. 1: Condition (RTC_TC_SEC = RTC_AL_SEC) is masked, i.e. the value of RTC_TC_SEC does not affect the alarm IRQ generation.

14

13

RTC Seconds Time Counter Register 12

11

10

9

8

7

6

Name Type Reset Bit(s) 5:0

0

Name TC_SECOND

2

1

0

0

RTC_TC_MIN 15

14

0

0

0

0

4

3

2

1

0

0

Description Second initial value for time counter Range: 0~59

13

RTC Minutes Time Counter Register 12

11

10

9

8

7

6

Name Type Reset

5

0000 TC_MINUTE RW

0

Name TC_MINUTE

00000596

RTC_TC_HOU 15

14

0

0

0

0

4

3

2

1

0

0

0

Description Minute initial value for time counter Range: 0~59

13

RTC Hours Time Counter Register 12

11

10

9

Name Type Reset Bit(s) 4:0

3 RW

Bit

Bit

4

TC_SECOND

00000594

Bit(s) 5:0

5

0000

8

7

6

5

0000 TC_HOUR RW 0

Name

MediaTek Proprietary and Confidential.

0

0

Description

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Page 135 of 1067

MT6359 PMIC Datasheet Confidential A 00000598

RTC_TC_DOM 15

Bit

14

13

RTC Day-of-month Time Counter Register 12

11

10

9

8

7

6

5

Name Type Reset Bit(s) 4:0

4

0000 3

2

Name TC_DOM

14

0

0

13

RTC Day-of-week Time Counter Register 12

11

10

9

8

7

6

5

4

0000 3

2

1

0

TC_DOW RW

Name TC_DOW

0000059C

14

0

0

2

1

0

Description Day-of-week initial value for time counter Range: 1~7

RTC_TC_MTH 15

Bit

13

RTC month time counter register 12

11

10

9

8

7

6

5

0700 4

Name Type Reset

3

0

TC_MONTH RW 0

Name TC_MONTH

0000059E 15

14

0

0

0

Description Month initial value for time counter Range: 1~12

RTC_TC_YEA

Name Type Reset Bit(s) 6:0

0

Description Day-of-month initial value for time counter The day-of-month maximum value depends on the leap year condition, i.e. 2 LSB of year time counter are 0.

RTC_TC_DOW 15

Bit

Bit

0

RW 0

Name Type Reset

Bit(s) 3:0

0

TC_DOM

0000059A

Bit(s) 2:0

1

13

RTC Year Time Counter Register 12

11

10

9

8

7

6

5

0000 4

3

2

1

0

0

0

0

TC_YEAR RW 0

Name TC_YEAR

MediaTek Proprietary and Confidential.

0

0

0

Description Year initial value for time counter Range: 0~127 (2000~2127) Software can bias the year as multiples of 4 for the internal leap-year formula. Here are 3 examples: 2000-2127, 1972~2099, 1904~2031.To simplify, RTC hardware treats all 4-multiple as leap years. If the range you define includes non-leap 4-multiple year (e.g. 2100), you have to adjust to correct date by yourselves (e.g. change Feb. 29th, 2100 to Mar. 1st, 2100). We suggest you bias the range large than 1900 and less than 2100 to evade the manual adjustment, i.e. the bias values are suggested to be in the range of [-28, -96], that are (1972~2099) ~ (1904~2031). The formal leap formula:

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Page 136 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

000005A0 Bit

Description if year modulo 400 is 0 then leap else if year modulo 100 is 0 then no_leap else if year modulo 4 is 0 then leap else no_leap

RTC_AL_SEC 15

14

13

RTC Second Alarm Setting Register 12

11

10

9

8

7

6

K_EOS BBPU_ BBPU_ BBPU_ BBPU_ BBPU_ C32_VT 2SEC_S 2SEC_S BBPU_2SEC_M AUTO_ RTC_LPD_OPT 2SEC_E 2SEC_C Name CXO_O TAT_ST TAT_CL ODE PDN_S N K_SEL N_SEL A EAR EL RW RW RO WO RW RW RW RW Type 0 0 0 0 0 0 0 0 0 0 Reset

Bit(s) 15

Name K_EOSC32_VTCXO_ON_SEL

14:13

RTC_LPD_OPT

12

BBPU_2SEC_STAT_STA

11

BBPU_2SEC_STAT_CLEAR

10:9

BBPU_2SEC_MODE

8

BBPU_2SEC_EN

7

BBPU_2SEC_CK_SEL

6

BBPU_AUTO_PDN_SEL

5:0

AL_SECOND

MediaTek Proprietary and Confidential.

5

0000 4

3

2

1

0

0

0

AL_SECOND RW 0

0

0

0

Description The bit will only be valid when EMBCK_SEL_MODE is set to EMB_K_EOSC32 mode. 0: VTCXO controlled by HW 1: VTCXO always on f32k_ck_alive setting (rstb of LPSTA_RAW) Depends on XOSC LPDETB (xosc32_ck_alive) or EOSC LPDETB (eosc32_ck_alive). 2'b11: Always 1 2'b10: xosc32_ck_alive (triggered when clock stops) 2'b01: eosc32_ck_alive (triggered when VRTC low-V) 2'b00: xosc32_ck_alive & eosc32_ck_alive Bbwakeup SPAR status 1'b0: SPAR reboot had not happened before. 1'b1: SPAR reboot had happened before. Clears Bbwakeup SPAR event Read back as BBPU_2SEC_STAT. Selects the battery removal time to trigger power mode 2'b11: Never power down 2'b10: 1.6sec power down after battery is removed 2'b01: 0.6sec power down after battery is removed 2'b00: 0.1sec power down after battery is removed Selects power mode 0: Legacy mode 1: 2sec power down mode Selects the clock source in the power down mode 0: embck_ck 1: eosc32_ck Selects the SPAR reboot method 0: Original SPAR reboot feature 1: Support both SPAR reboot and auto_pdn Second value of alarm counter setting

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Page 137 of 1067

MT6359 PMIC Datasheet Confidential A 000005A2

RTC_AL_MIN 15

Bit

14

RTC Minute Alarm Setting Register

13

12

11

10

9

8

7

6

Name Type Reset Bit(s) 5:0

Name AL_MINUTE

Bit(s) 15:8

1

0

0

14

0

0

0

0

13

4

3

2

1

0

0

0

RTC Hour Alarm Setting Register 12

11

10

9

8

7

6

5

0000

NEW_SPARE0

AL_HOUR

RW 0

0

0

0

RW 0

0

Name NEW_SPARE0

RTC_AL_DOM 15

0

14

0

Name NEW_SPARE1

0

0

0

0

0

Description NEW_SPARE0[7]: WO: Reset bat status by writing 1, auto cleared to 0 NEW_SPARE0[6]: RO: 0 = No bat now/1 = bat installed properly NEW_SPARE0[5]: RO: 0 = Battery always exists/1 = Battery has been removed NEW_SPARE0[4:0]: Battery removed time counter (unit: minute), stopped when counting to 5'd30, reset to 0 by SPARE0[7] Hour value of alarm counter setting Range: 0~23

AL_HOUR

000005A6 Bit

2

Description Minute value of alarm counter setting Range: 0~59

RTC_AL_HOU 15

Name Type Reset

Name Type Reset

3 RW

0

Bit

4:0

0000 4

AL_MINUTE

000005A4

Bit(s) 15:8

5

13

0

RTC Day-of-month Alarm Setting Register 12

11

10

9

8

7

6

5

4

0000 3

2

NEW_SPARE1

AL_DOM

RW

RW

0

0

0

0

0

0

0

0

1

0

0

0

Description NEW_SPARE1[7:6]: RO: spar_state[1:0] 2'b00: ST_PWR_OFF 2'b01: ST_PWR_ON 2'b10: ST_PWR_ON2OFF 2'b11: ST_SPAR_EN NEW_SPARE1[5]: RO: additional_spar_en 1'b0: No spar happend NEW_SPARE1[4]: RO: uvlo_except_sync 1'b0: The battery voltage is over the uvlo threshold. 1'b1: The battery voltage is under the uvlo threshold. NEW_SPARE1[3]: Reserved NEW_SPARE1[2]: Reserved

MediaTek Proprietary and Confidential.

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Page 138 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

4:0

Name

AL_DOM

000005A8

2:0

RTC_AL_DOW 15

Bit Name Type Reset Bit(s) 15:8 7:5

11

10

15

0

14

0

7

6

5

4

0

0

0

0

0

0

1

1

0

0

0

0

0

Description Reserved for specific purposes RTC EOSC calibration period setting 0x0: N/A 0x1: N/A 0x2: N/A 0x3: 1 sec 0x4: 2 sec 0x5: 4 sec 0x6: 8sec 0x7: 16sec Day-of-week value of alarm counter setting Range: 1~7

13

RTC Month Alarm Setting Register 12

0

11

10

9

8

7

6

5

0000 4

3

2

1

NEW_SPARE3

AL_MONTH

RW

RW

0

0

0

0

0

0

0

0

0

0

3

2

1

0

0

0

0

Description Reserved for specific purposes Month value of alarm counter setting Range: 1~12

13

0

Name RTC_K_EOSC_RSV

MediaTek Proprietary and Confidential.

1 RW

RTC Year Alarm Setting Register 12

11

10

9

8

7

6

5

0000 4

AL_YEAR

RW 0

2

RW

RTC_K_EOSC_RSV 0

3

RW

RTC_AL_YEA 14

8

AL_DOW

Name NEW_SPARE3 AL_MONTH

15

9

RG_EOSC_CALI_TD

RTC_AL_MTH

000005AC

Bit(s) 15:8

12

00C0

NEW_SPARE2

AL_DOW

Bit

Name Type Reset

0

13

RTC Day-of-week Alarm Setting Register

Name NEW_SPARE2 RG_EOSC_CALI_TD

Name Type Reset

Bit

14

0

000005AA

Bit(s) 15:8 3:0

Description NEW_SPARE1[1]: Reserved NEW_SPARE1[0]: RW: Enables ALARM signal to be clear by sysreset 1'b0: Disable 1'b1: Enable Day-of-month value of alarm counter setting The day-of-month maximum value depends on the leap year condition, i.e. 2 LSB of year time counter are 0.

0

RW 0

0

0

0

0

0

0

0

Description RTC_TEST_RSV[7:3]: Reserved

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Page 139 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

6:0

Name

AL_YEAR

000005AE Bit

Description RTC_TEST_RSV[2]: Indicates the system is normally or abnormally off. This bit will be checked when solution 2 is enabled and the system is off. 0: Abnormal off 1: Normal off RTC_TEST_RSV[1]: Enable solution 2 (eosc cali function is off when the system is off by the exception) 0: Disable 1: Enable RTC_TEST_RSV[0]: RTC internal clock switch from dcxo32k_ck to eosc32k_ck configuration at 32kless platform 0: By ddlo or bwdt_ddlo 1: By system_resetb Year value of alarm counter setting Range: 0~127 (2000~2127)

RTC_OSC32CON 15

14

13

12

OSC32 Control 11

RTC_RE RTC_E RTC_E G_XOS RTC_GP_OSC32 OSC32_ OSC32_ Name C32_E _CON CHOP_ VCT_E NB EN N RW RW RW RW Type 0 0 0 0 0 Reset

Bit(s) 15

Name RTC_REG_XOSC32_ENB

14:13

RTC_GP_OSC32_CON

12

RTC_EOSC32_CHOP_EN

11

RTC_EOSC32_VCT_EN

10

RTC_GPS_CKOUT_EN

9

RTC_EMBCK_SEL_OPTION

8

RTC_EMBCK_SRC_SEL

MediaTek Proprietary and Confidential.

10

9

RTC_G PS_CK OUT_E N RW 1

8

0400 7

6

5

RTC_E RTC_E RTC_X MBCK_ MBCK_ RTC_EMBCK_S OSC32_ SEL_OP SRC_SE EL_MODE ENB TION L RW RW RW RO 0 0 0 0 0

4

3

2

1

0

0

0

XOSCCALI

0

0

RW 0

Description XOSC32_ENB = 0 (32k crystal exists.) XOSC32_ENB = 1 (32k crystal does not exist.) EOSC32 RSV registers [14]: Select clock source to GPS [13]: Adjust the current when eosc is powered up Enables EOSC32 chopper When chopper is disabled, the current consumption can become lower. However, eosc32_ck might become unstable. When powerkeys do not match, the chopper will be enabled 0: Disable 1: Enable Enables EOSC32 threshold tracking 0: Disable 1: Enable Powers up EOSC When PAD_RTC_32K_2V8 is in buffer mode, the suggested value of this bit will be 1'b0 in order not to interfere the input clock. 1'b0: Power down 1'b1: Power up Embedded clock selection option after battery removal Note: Setting this bit to 1'b1 can extend the embedded clock life time after battery removal with a poorer clock source. EOSC32 can only keep the spec before LPD. After LPD, the frequency drift will become larger. 0: Embedded clock switch back to dcxo decided by (eosc32_ck_alive & powerkey_match) 1: Embedded clock switch back to dcxo decided by (powerkey_match) Selects embedded clock source in EMB_K_EOSC32 mode (RTC_OSC32CON[7:6] = 2'b01) 0: f32k_ck src = dcxo_ck 1: f32k_ck src = eosc32_ck

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Page 140 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 7:6

5

4:0

Name RTC_EMBCK_SEL_MODE

RTC_XOSC32_ENB

XOSCCALI

000005B0

RTC_POWERKEY1 15

Bit Name Type Reset Bit(s) 15:0

0

0

13

0

12

0

RTC_POWERKEY1 Register 11

0

10

0

0

14

0

13

0

12

0

0

10

0

0

14

0

MediaTek Proprietary and Confidential.

13

0

7

0000

6

5

4

3

2

1

0

0

0

0

0

0

0

0

6

5

4

3

2

1

0

0

0

0

0

0

0

0

7

6

5

4

3

2

1

0

RTC_PDN1 RW 0 0

0

0

0

0

0

0

0

RTC_POWERKEY1 RW 0 0

9

0

8

7

RTC_POWERKEY2 RW 0 0

0000

Description

RTC_PDN1 15

0

8

RTC_POWERKEY2 Register 11

Name RTC_POWERKEY2

000005B4

9

Description

RTC_POWERKEY2 15

Bit Name Type Reset

Bit Name Type Reset

14

Name RTC_POWERKEY1

000005B2

Bit(s) 15:0

Description Embedded clock source selection mode 00: EMB_HW (embedded HW) mode.Initial f32k_ck source = DCXO, and hardware automatically switches to EOSC32 at VBAT LV level 01: EMB_K_EOSC32 mode.Initial f32k_ck source = DCXO, and SW can configure the f32k_ck src by configuring RTC_OSC32CON[8] (EMBCK_SEL). HW automatically switches f32k_ck src to eosc32_ck at VBAT LV level 10: EMB_SW_DCXO mode (from bit 6).f32_ck_src=dcxo_ck 11: EMB_SW_EOSC32 mode(from bit 6).f32k_ck src = eosc32_ck Read: XOSC32_ENB Pin configuration of 32k crystal is used or not. 0: Use 32k crystal, f32k_ck source = XOSC32 1: No 32k crystal, f32k_ck source = embedded 32k sources (DCXO or EOSC32) Write: Manual clock during reloading, for debugging. SW can toggle this bit to generate SW clock. This clock is used as RTC registers' clock source only during the reload procedure. When power-on without 32k's existence, this bit can be used to finish the reload procedure, then SW will be capable of reading the RTC registers contents. Calibrates GM Default: 4'b0111 Suggested setting for 2nd step: 4'b0000 EOSC_CALI = Charging cap calibration

PDN1 12

0

11

0

10

0

9

0

0000 8

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Page 141 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 15:0

Name RTC_PDN1

000005B6

Bit(s) 15:0

RTC_PDN2 15

Bit Name Type Reset

0

0

0

0

11

0

10

0

14

0

15

0

14

0

13

0

0

11

0

10

0

0

0

Name RTC_PROT

MediaTek Proprietary and Confidential.

7

6

5

4

3

2

1

0

RTC_PDN2 RW 0 0

0

0

0

0

0

0

0

9

0

8

7

RTC_SPAR0 RW 0 0

0000

6

5

4

3

2

1

0

0

0

0

0

0

0

0

Description Reserved for specific purposes

13

0

Spare Register for Specific Purpose_1 12

0

11

0

10

0

9

0

8

7

RTC_SPAR1 RW 0 0

0000

6

5

4

3

2

1

0

0

0

0

0

0

0

0

Description Reserved for specific purposes

RTC_PROT 14

0

0000 8

Spare Register for Specific Purpose_0 12

Name RTC_SPAR1

15

9

Description Spare registers for software to keep power-on and power-off state information

RTC_SPAR1

000005BC

Bit(s) 15:0

12

Name RTC_SPAR0

000005BA

Bit Name Type Reset

0

PDN2

13

RTC_SPAR0 15

Bit Name Type Reset

Bit Name Type Reset Bit(s) 15:0

14

Name RTC_PDN2

000005B8

Bit(s) 15:0

Description Spare registers for software to keep power-on and power-off state information

13

0

Lock/Unlock Scheme to Prevent RTC Miswriting 12

0

11

0

10

0

9

0

8

0000

7

6

5

4

3

2

1

0

RTC_PROT RW 0 0

0

0

0

0

0

0

0

Description The RTC write interface is protected by RTC_PROT. Whether the RTC writing interface is enabled or not is decided by RTC_PROT contents. When RTC_POWERKEY1 and RTC_POWERKEY2 are not equal to the correct values, the RTC writing interface will always be enabled. However, when they match, perform the unlock flow to enable the writing interface. Unlock flow: 1 *RTC_PROT=0x586a; 2. *RTC_WRTGR=1; 3. While(*RTC_BBPU & 0x40) {}; // Timeout period: 120usec 4. *RTC_PROT=0x9136; © 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 142 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

000005BE

RTC_DIFF 15

Bit

Description 5. *RTC_WRTGR=1; 6. While(*RTC_BBPU & 0x40) {}; // Timeout period: 120usec Note: Always keep RTC in unlock state in power-on mode. Once the normal RTC content writing is completed, do not modify the RTC_PROT content to lock RTC. The RTC_PROT contents will be cleared automatically when powered off immediately.

14

One-time Calibration Offset

13

12

K_EOS CALI_R C32_RS Name D_SEL V RW RW Type

Reset

0

0

0

Name CALI_RD_SEL

14 12 11:0

K_EOSC32_RSV POWER_DETECTED RTC_DIFF

Bit

14

Name K_EOSC32_OVERFLOW

MediaTek Proprietary and Confidential.

7

6

0000 5

4

3

2

1

0

0

0

0

0

0

RW 0

0

0

0

0

0

0

Description Selects which RTC_CALI is to be read when read RTC_CALI register 0: Normal RTC_CALI 1: K_EOSC32_RTC_CALI Reserved bit for EMB_K_EOSC32 mode Read new powerkey match status Adjusts internal counter of RTC This affects once and returns to 0 when done. In some cases, you observe the RTC is faster or slower than the standard. Changing RTC_TC_SEC is coarse and may cause alarm problems. RTC_DIFF provides a finer time unit. An internal 15-bit counter accumulates in each 32768Hz clock. Entering a non-zero value into RTC_DIFF will cause the internal RTC counter to increase or decrease RTC_DIFF when RTC_DIFF changes to 0 again. RTC_DIFF is represented in 2's complement. For example, if you fill 0xfff into RTC_DIFF, the internal counter will decrease 1 when RTC_DIFF returns to 0. In other words, you can only use RTC_DIFF continuously if RTC_DIFF is equal to 0 now. Note: RTC_DIFF ranges from 0x800 (-2048) to 0x7fd (2045). 0x7ff & 0x7fe are forbidden to use.

12

Bit(s) 15

CALI_WR_SEL

8

Repeat Calibration Offset

13

Type Reset

14

9

RTC_DIFF

RTC_CALI 15

K_EOS CALI_ C32_O WR_SE VERFL L OW RW RW 0 0

Name

10

POWER _DETEC TED RO

Bit(s) 15

000005C0

11

11

10

9

8

7

6

0000 5

4

3

2

1

0

0

0

0

0

0

0

RTC_CALI RW 0

0

0

0

0

0

0

0

Description EOSC32 calibration overflow (EOSC32 RTC_CALI update result from PMU rtc_eosc_cali module overflow) 0: Not overflow 1: Overflow Enables EOSC32 Cali value write Only takes effect in RTC_CALI write operation. 0: Normal RTC_CALI 1: K_EOSC32_RTC_CALI

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Page 143 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 13:0

Name RTC_CALI

000005C2

RTC_WRTGR 15

Bit

Description These registers provide a repeat calibration scheme. RTC_CALI provides two types of calibration: 1. 7-bit calibration capability in 8-second duration, i.e. 5-bit calibration capability in each second. RTC_CALI is represented in 2's complement, such that you can adjust RTC increasing or decreasing. Due to RTC_CALI is revealed in 8 seconds, the resolution is less than a 1/32768 clock. Avg. resolution: 1/32768/8=3.81us Avg. adjustment range: -0.244~0.240ms/sec in 2's complement: 0x40~0x3f (-64~63) 2. 14-bit calibration capability in 1-second duration in EMB_K_EOSC32 mode (K_EOSC32_RTC_CALI). This type of usage is with resolution 1/32768=30.52us.

14

13

Enable Transfers from Core to RTC in Queue 12

11

10

9

8

7

6

5

4

3

0000 2

1

Name Type Reset Bit(s) 0

0

Name WRTGR

000005C4 Bit

Description Enables transfers from core to RTC After you modify all RTC registers you are to change, write 1 to RTC_WRTGR to trigger the transfer. The prior writing operations are queued at core power domain. The pending data will not be transferred to RTC domain until WRTGR=1. After WRTGR=1, the pending data will be transferred to RTC domain sequentially in order of register address, from low to high, e.g. RTC_BBPU -> RTC_IRQ_EN -> RTC_CII_EN -> RTC_AL_MASK -> RTC_TC_SEC -> .... CBUSY in RTC_BBPU is equal to 1 in the writing process. You can observe CBUSY to determine when the transmission will be completed.

RTC_CON 15

14

Other RTC Control Register

13

12

11

Name

LPSTA_ RAW

GPI

GE8

GE4

GPU

Type Reset

RO 0

RO 0

RW 0

RW 0

RW 0

Bit(s) 15

0 WRTG R WO

Name LPSTA_RAW

14 13 12 11 10

GPI GE8 GE4 GPU GPEN

9

GSMT

MediaTek Proprietary and Confidential.

10

9

GPEN GSMT RW 0

RW 0

8

7

6

GSR

GOE

GPO

RW 0

RW 0

RW 0

0000 5

4

3

2

1

0

VBAT_ F32KO XOSC3 EOSC32 CDBO LPRST LPSTA_ B 2_LPEN _LPEN RAW RW RW RW RW RW RW 0 0 0 0 0 0

Description Raw status of LP_STA You can re-initialize LPD to clear this bit. Note: This bit is always high before LPD initialization sequence after the first power-on. Input value of RTC_GPIO when GOE = 0 (input mode) Driving capability of RTC_GPIO. Driving capability of RTC_GPIO Pull-up of RTC_GPIO Pull enable of RTC_GPIO When GPEN=1, RTC_GPIO will be pulled up if GPU=1 and pulled down if GPU=0. SMT of RTC_GPIO

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Page 144 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

8

GSR

7

GOE

6

GPO

5

F32KOB

4

CDBO

3

LPRST

2

XOSC32_LPEN

1

EOSC32_LPEN

0

VBAT_LPSTA_RAW

MediaTek Proprietary and Confidential.

Description Control pin for Schmitt trigger circuit 0: RTC_GPIO Schmitt trigger off 1: RTC_GPIO Schmitt trigger on SR of RTC_GPIO Controls output slew rate. High asserted. SR = 0, slower slew. SR = 1. 0: RTC_GPIO higher slew output 1: RTC_GPIO slower slew output OE of RTC_GPIO 1'b0: RTC_GPIO is in input mode. 1'b1: RTC_GPIO is in output mode. Output value of RTC_GPIO when OE = 1 and COREDETB = 0 Selects to output pdn_flat_out signal or tick_sec to RTC_GPIO when OE = 1 and COREDETB = 1. Exports 32.768kHz clock on RTC_GPIO in analog IO mode 1'b0: Analog IO mode 1'b1: Digital IO mode Exports signal on RTC_GPIO 1'b0: Export GPO value 1'b1: When LPD_OPT = 1, export LPDETB. When LPD_OPT = 0 and GPO = 0, export pdn_flat_out signal. When LPD_OPT = 0 and GPO = 1, export tick_sec. Resets LPDETB This only takes effect when LPEN = 1. When LPEN = 0, the internal LPRST signal to XOSC32 is always 0. Enables XOSC LPDETB function LP initialization sequence to enable LPDETB: 1. Write XOSC32_LPEN = 1, LPRST = 0. Write RTC_WRTGR = 1. wait cbusy down. 2. Write XOSC32_LPEN = 1, LPRST = 1. Write RTC_WRTGR = 1. wait cbusy down. 3. Write XOSC32_LPEN = 1, LPRST = 0. Write RTC_WRTGR = 1. wait cbusy down. XOSC32 LPD will occur when 32k stops. It can be applied both at XOSC32 and EOSC32. Enables EOSC LPDETB function LP initialization sequence to enable LPDETB: 1. Write EOSC32_LPEN = 1, LPRST = 0. Write RTC_WRTGR = 1. wait cbusy down. 2. Write EOSC32_LPEN = 1, LPRST = 1. Write RTC_WRTGR = 1. wait cbusy down. 3. Write EOSC32_LPEN = 1, LPRST = 0. Write RTC_WRTGR = 1. wait cbusy down. EOSC32 LPD will occur when VRTC~=1.7V. It can be applied both at XOSC32 and EOSC32. Indicates the battery has been in LP state When the embedded hardware mode is used, the flag also indicates that hardware has switched the clock source from DCXO to EOSC32. Software needs to clear this bit for the use next time. Note: VBAT LP state = VBAT < 2.5V (DDLO) 0: VBAT has not been in LP state. 1: VBAT has been in LP state.

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Page 145 of 1067

MT6359 PMIC Datasheet Confidential A 00000608

RTC_TC_SEC_SEC 15

Bit

14

13

12

Security RTC Seconds Time Counter Register 11

10

9

8

7

6

Name Type Reset Bit(s) 5:0

Name TC_SECOND_SEC

RTC_TC_MIN_SEC 15

1

0

14

13

0

0

0

0

0

12

2

1

0

0

0

Security RTC Minutes Time Counter Register 11

10

9

8

7

6

5

4

0000

3

TC_MINUTE_SEC RW 0

Name TC_MINUTE_SEC

0000060C

RTC_TC_HOU_SEC 15

Bit

14

13

0

0

0

Description Minute initial value for time counter Range: 0~59

12

Security RTC Hours Time Counter Register 11

10

9

8

7

6

5

Name Type Reset

4

0000 3

2

1

0

0

0

TC_HOUR_SEC RW 0

Name TC_HOUR_SEC

0000060E 15

14

0

0

Description Hour initial value for time counter Range: 0~23

RTC_TC_DOM_SEC

Name Type Reset Bit(s) 4:0

2

Description Second initial value for time counter Range: 0~59

Name Type Reset

Bit

0000

3 RW

0

Bit

Bit(s) 4:0

4

TC_SECOND_SEC

0000060A

Bit(s) 5:0

5

13

12

Security RTC Day-of-month Time Counter Register 11

10

9

8

7

6

5

4

0000 3

2

1

0

0

0

TC_DOM_SEC RW 0

Name TC_DOM_SEC

MediaTek Proprietary and Confidential.

0

0

Description Day-of-month initial value for time counter The day-of-month maximum value depends on the leap year condition, i.e. 2 LSB of year time counter are 0.

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Page 146 of 1067

MT6359 PMIC Datasheet Confidential A 00000610

RTC_TC_DOW_SEC 15

Bit

14

13

12

Security RTC Day-of-week Time Counter Register 11

10

9

8

7

6

5

4

3

Name Type Reset Bit(s) 2:0

Name TC_DOW_SEC

RTC_TC_MTH_SEC 15

14

0

0

2

1

0

Description Day-of-week initial value for time counter Range: 1~7

13

12

Security RTC Month Time Counter Register 11

10

9

8

7

6

5

4

0000 3

Name Type Reset

0

TC_MONTH_SEC RW 0

Name TC_MONTH_SEC

00000614 15

14

13

0

0

0

Description Month initial value for time counter Range: 1~12

RTC_TC_YEA_SEC

Name Type Reset Bit(s) 6:0

0

RW

Bit

Bit

1 TC_DOW_SEC

00000612

Bit(s) 3:0

0000 2

12

Security RTC Year Time Counter Register 11

10

9

8

7

6

5

4

0000 3

2

1

0

0

0

0

TC_YEAR_SEC RW 0

Name TC_YEAR_SEC

MediaTek Proprietary and Confidential.

0

0

0

Description Year initial value for time counter Range: 0~127 (2000~2127) Software can bias the year as multiples of 4 for the internal leap-year formula. Here are 3 examples: 2000-2127, 1972~2099, 1904~2031.To simplify, RTC hardware treats all 4-multiple as leap years. If the range you define includes non-leap 4-multiple year (e.g. 2100), you have to adjust to correct date by yourselves (e.g. change Feb. 29th, 2100 to Mar. 1st, 2100). We suggest you bias the range large than 1900 and less than 2100 to evade manual adjustment, i.e. the bias values are suggested to be in the range of [-28,-96], that are (1972~2099) ~ (1904~2031). Formal leap formula: if year modulo 400 is 0 then leap else if year modulo 100 is 0 then no_leap else if year modulo 4 is 0 then leap else no_leap

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Page 147 of 1067

MT6359 PMIC Datasheet Confidential A 00000616

RTC_SEC_CK_PDN 15

Bit

14

13

12

Security RTC Clock Control Register 11

10

9

8

7

6

5

0000 4

3

2

1

Name Type Reset Bit(s) 0

0

Name RTC_SEC_CK_PDN

00000618

Description Controls security RTC clock 0: Turn off clock 1: Turn on clock

RTC_SEC_WRTGR 15

Bit

14

13

12

Enable Transfers from Core to Security RTC in Queue 11

10

9

8

7

6

5

4

3

0000 2

1

Type Reset

0

Name RTC_SEC_WRTGR

00000788 Bit

0 RTC_SE C_WRT GR WO

Name

Bit(s) 0

0 RTC_SE C_CK_P DN RW

Description Enables transfers from core to security RTC After you modify all RTC registers you are to change, write RTC_WRTGR to 1 to trigger the transfer. The prior writing operations are queued at core power domain. The pending data will not be transferred to RTC domain until WRTGR = 1. After WRTGR = 1, the pending data will be transferred to RTC domain sequentially in order of register address, from low to high. e.g. RTC_TC_SEC_SEC -> RTC_TC_MIN_SEC -> RTC_TC_HOU_SEC.

DCXO_CW00 15

14

13

DCXO Code Word 0 12

11

10

9

8

7

6B6D 6

5

4

3

2

1

0

Type Reset

XO_CL XO_EN XO_EN XO_BB XO_EX XO_EX XO_EX XO_EX XO_EXTBUF4_ XO_EXTBUF3_ XO_EXTBUF2_ XO_EXTBUF1_ KSEL_ BB_EN BB_MA _LPM_ TBUF4_ TBUF3_ TBUF2_ TBUF1_ MODE MODE MODE MODE MAN _M N EN_M EN_M EN_M EN_M EN_M RW RW RW RW RW RW RW RW RW RW RW RW 0 1 1 0 1 0 1 1 0 1 1 0 1 1 0 1

Bit(s) 15

Name XO_CLKSEL_MAN

14

XO_ENBB_EN_M

13

XO_ENBB_MAN

12

XO_BB_LPM_EN_M

11 10:9

XO_EXTBUF4_EN_M XO_EXTBUF4_MODE

Name

MediaTek Proprietary and Confidential.

Description 0: XO2~4 are controlled by pin (CLK_SEL/SRCLKEN_IN1). 1: XO2~4 are controlled by register XO_CLKSEL_EN_M (default). 0: XO_SOC will be disabled if manual (register) control. 1: XO_SOC will be enabled if manual (register) control (default). 0: XO_SOC is controlled by pin (EN_BB/SRCLKEN_IN0). 1: XO_SOC is controlled by register XO_ENBB_EN_M (default). SW controlled LPM for saving power during transceiver standby Must be EN_BB = 1, CLK_SEL = 0. Enables/Disables XO_CEL during manual (register) control 00: Register controlled by XO_EXTBUF4_EN_M 01: EN_BB

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 148 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

8 7:6

XO_EXTBUF3_EN_M XO_EXTBUF3_MODE

5 4:3

XO_EXTBUF2_EN_M XO_EXTBUF2_MODE

2 1:0

XO_EXTBUF1_EN_M XO_EXTBUF1_MODE

0000078A

Bit(s) 15:0

DCXO_CW00_SET 15

Bit Name Type Reset

0

Bit(s) 15:0

14

0

13

0

12

0

DCXO Code Word 0 Set 11

0

10

0

Name DCXO_CW00_SET

0000078C Bit Name Type Reset

Description 10: CLK_SEL 11: XO_EXTBUF2_EN_M or XO_EXTBUF3_EN_M or CLK_SEL Enables/Disables XO_NFC during manual (register) control 00: Register controlled by XO_EXTBUF3_EN_M 01: EN_BB 10: CLK_SEL 11: XO_EXTBUF2_EN_M or XO_EXTBUF3_EN_M or CLK_SEL Enables/Disables XO_WCN during manual (register) control 00: Register controlled by XO_EXTBUF2_EN_M 01: EN_BB 10: CLK_SEL 11: XO_EXTBUF2_EN_M or XO_EXTBUF3_EN_M or CLK_SEL Enables/Disables XO_SOC during manual (register) control 00: Register controlled by XO_EXTBUF1_EN_M 01: EN_BB 10: CLK_SEL 11: EN_BB or CLK_SEL

0

14

0

13

0

Name DCXO_CW00_CLR

MediaTek Proprietary and Confidential.

0

8

7

DCXO_CW00_SET W1 0 0

0000 6

5

4

3

2

1

0

0

0

0

0

0

0

0

Description Sets up DCXO Code Word 0 0: Not set 1: Set

DCXO_CW00_CLR 15

9

12

0

DCXO Code Word 0 Clear 11

0

10

0

9

0

8

7

DCXO_CW00_CLR W1 0 0

0000

6

5

4

3

2

1

0

0

0

0

0

0

0

0

Description Clears DCXO Code Word 0 0: Not clear 1: Clear

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 149 of 1067

MT6359 PMIC Datasheet Confidential A 0000078E

DCXO_CW01 15

Bit

14

13

DCXO Code Word 1 12

11

10

9

8

7

6D55 6

5

4

3

2

1

0

XO_BB XO_LV XO_HV XO_HV XO_EX XO_EX XO_EX XO_EX XO_EX XO_EX XO_EX XO_EX XO_LV XO_LV XO_HV XO_CL LPM_C _PBUF _PBUF _PBUF TBUF4_ TBUF4_ TBUF3_ TBUF3_ TBUF2_ TBUF2_ TBUF1_ TBUF1_ _PBUF _PBUF _PBUF KSEL_E Name KSEL_ BIAS_E BIAS_E _EN_SY CKG_E CKG_M CKG_E CKG_M CKG_E CKG_M CKG_E CKG_M _EN_M _MAN _MAN N_M M N_M N_M NC_M N_M AN N_M AN N_M AN N_M AN RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type 0 1 1 0 1 1 0 1 0 1 0 1 0 1 0 1 Reset

Bit(s) 15

Name XO_BBLPM_CKSEL_M

14 13 12 11 10 9 8

XO_LV_PBUF_EN_M XO_LV_PBUFBIAS_EN_M XO_LV_PBUF_MAN XO_HV_PBUFBIAS_EN_M XO_HV_PBUF_EN_SYNC_M XO_HV_PBUF_MAN XO_EXTBUF4_CKG_EN_M

7

XO_EXTBUF4_CKG_MAN

6

XO_EXTBUF3_CKG_EN_M

5

XO_EXTBUF3_CKG_MAN

4

XO_EXTBUF2_CKG_EN_M

3

XO_EXTBUF2_CKG_MAN

2

XO_EXTBUF1_CKG_EN_M

1

XO_EXTBUF1_CKG_MAN

0

XO_CLKSEL_EN_M

00000790 Bit Name Type Reset

Description XO_WCN and XO_CEL LPM frequency manually switched if XO_LPMBUF_MAN = 1 Enables XO low power buffer manually if XO_LV_PBUF_MAN = 1 Enables XO low power buffer bias manually if XO_LPMBUF_MAN = 1 XO low power buffer enable manual mode Enables XO FPM (HV) prebuffer bias circuit if XO_HV_PBUF_MAN = 1 Enables XO pre-buffer manually if XO_HV_PBUF_MAN = 1 XO pre-buffer enable manual mode XO_CEL 26MHz output enable when in manual mode 0: Disable XO_CEL buffer if XO_EXTBUF4_CKG_MAN = 1 1: Enable XO_CEL buffer if XO_EXTBUF4_CKG_MAN = 1 XO_CEL 26MHz output enable manual mode 0: Software control 1: Manual control XO_EXTBUF4_CKG_EN_M XO_NFC 26MHz output enable when in manual mode 0: Disable XO_NFC buffer if XO_EXTBUF3_CKG_MAN = 1 1: Enable XO_NFC buffer if XO_EXTBUF3_CKG_MAN = 1 XO_NFC 26MHz output enable manual mode 0: Software control 1: Manual control XO_EXTBUF3_CKG_EN_M XO_WCN 26MHz output enable when in manual mode 0: Disable XO_WCN buffer if XO_EXTBUF2_CKG_MAN = 1 1: Enable XO_WCN buffer if XO_EXTBUF2_CKG_MAN = 1 XO_WCN 26MHz output enable manual mode 0: Software control 1: Manual control XO_EXTBUF2_CKG_EN_M XO_SOC 26MHz output enable when in manual mode 0: Disable XO_SOC buffer if XO_EXTBUF1_CKG_MAN = 1 1: Enable XO_SOC buffer if XO_EXTBUF1_CKG_MAN = 1 XO_SOC 26MHz output enable manual mode 0: Software control 1: Manual control XO_EXTBUF1_CKG_EN_M 0: XO2~4 will be disabled if manual (register) control. 1: XO2~4 will be enabled if manual (register) control (default).

DCXO_CW02 15

14

13

DCXO Code Word 2 12

11

10

9

8

7

A00E 6

5

4

XO_PC XO_CB XO_PC XO_EN TAT_E N_MA YNC_D N_M N YN RW RW RW 1

0

MediaTek Proprietary and Confidential.

1

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

3

2

1

0

RG_XO XO_EN _CBAN 32K_M 32K_M K_POL AN RW

RW

RW

1

1

0

Page 150 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 15

Name XO_PCTAT_EN_M

14

XO_PCTAT_EN_MAN

13

XO_CBANK_SYNC_DYN

2

RG_XO_CBANK_POL

1

XO_EN32K_M

0

XO_EN32K_MAN

00000792

DCXO_CW03 15

Bit

Description Enables/Disables temperature compensation when XO_PCTAT_EN_MAN = 1 0: Disable if XO_PCTAT_EN_MAN = 1 1: Enable if XO_PCTAT_EN_MAN = 1 Temperature compensation enable manual mode 0: Software control 1: Manual control XO_PCTAT_EN_M 0: Update clock of CBANK always turned on 1: Update clock of CBANK only turned on when CDAC is updated XO control signal of clock polarity for CBank control local synchronization 0: Positive edge 1: Falling edge 0: EN_32K_G will be disabled if manual (register) control. 1: EN_32K_G will be enabled if manual (register) control (default) 0: EN_32K_G is controlled by pin (XO32K_EN) (default). 1: EN_32K_G is controlled by register XO_EN32K_M.

14

13

DCXO Code Word 3 12

11

10

9

8

7

Name

XO_FPM_ISEL_M

RG_XO_CORE_LPM_ISEL

Type Reset

RW

RW

0

1

1

1

Bit(s) 15:11 10:6 5

Name XO_FPM_ISEL_M RG_XO_CORE_LPM_ISEL XO_EXTBUF7_CKG_EN_M

4

XO_EXTBUF7_CKG_MAN

00000794 Bit Name Type Reset Bit(s) 15:8 7:0

1

0

1

14

1

Name XO_CDAC_LPM XO_CDAC_FPM

MediaTek Proprietary and Confidential.

13

1

1

1

6

5

4

3

2

1

1

1

0

DCXO Code Word 4 12

0

XO_EX XO_EX TBUF7_ TBUF7_ CKG_E CKG_M N_M AN RW RW

Description XO core FPM current settings if XO_AAC_ISEL_MAN = 1 XO core LPM current register settings XO_EXT 26MHz output enable when in manual mode 0: Disable XO_EXT buffer if XO_EXTBUF7_CKG_MAN = 1 1: Enable XO_EXT buffer if XO_EXTBUF7_CKG_MAN = 1 XO_EXT 26MHz output enable manual mode 0: Software control 1: Manual control XO_EXTBUF7_CKG_EN_M

DCXO_CW04 15

1

7BE9

11

XO_CDAC_LPM RW 1 1

10

1

9

1

8

1

7

1

FF88 6

0

5

0

4

3

XO_CDAC_FPM RW 0 1

2

1

0

0

0

0

Description XO CDAC code (complement) during LPM XO CDAC code (complement) during FPM

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Page 151 of 1067

MT6359 PMIC Datasheet Confidential A 00000796

DCXO_CW05 15

Bit

14

13

DCXO Code Word 5 12

Type Reset

XO_COFST_FP M RW 0 0

Bit(s) 15:14 13:0

Name XO_COFST_FPM XO_32KDIV_NFRAC_FPM

Name

00000798

14

1

13

Name XO_COFST_LPM XO_32KDIV_NFRAC_LPM

0

1

14

6

5

4

3

2

1

0

1

1

0

1

1

0

0

0

0

0

Description XO CDAC offset code during FPM 32K divider fractional input during FPM; clk = 6.5MHz

11

10

9

8

1760

7

6

5

4

3

2

1

0

0

0

0

0

0

2

1

XO_32KDIV_NFRAC_LPM RW 0

1

0

1

13

1

1

0

1

1

Description XO CDAC offset code during LPM 32K divider fractional input during LPM; clk = 6.5MHz

DCXO_CW08 15

1760

7

DCXO Code Word 6 12

Bit(s) 15:14 13:0

Bit

8

RW 0

Type Reset

0000079C

9

XO_32KDIV_NFRAC_FPM

XO_COFST_LP M RW 0 0

Name

10

DCXO_CW06 15

Bit

11

DCXO Code Word 8 12

11

10

9

8

7

1C5E 6

5

4

3

RW

XO_PM IC_TOP _DIG_S W RW

0

1

XO_AA

Name C_FPM _SWEN

Type Reset Bit(s) 15

2

Name XO_AAC_FPM_SWEN

Bit Name

Description SW trigger AAC during FPM 0: Disable 1: SW trigger AAC during FPM 0: Mode and buffer control from AP 1: Mode and buffer control from srclken0

XO_PMIC_TOP_DIG_SW

0000079E

DCXO_CW09 15

14

13

DCXO Code Word 9 12

11

10

9

8

7

5BF0 6

5

4

XO_EX XO_EX XO_EXTBUF7_ XO_EXTBUF6_ TBUF7_ TBUF6_ MODE MODE EN_M EN_M

Type Reset

RW

Bit(s) 14 13:12

Name XO_EXTBUF7_EN_M XO_EXTBUF7_MODE

1

MediaTek Proprietary and Confidential.

RW 0

RW 1

0

1

RW 0

1

3

2

1

0

XO_32 XO_32 XO_32 KDIV_R KDIV_T KDIV_S ATIO_ EST_EN WRST MAN RW RW RW 0

0

0

Description Enables/Disables XO_EXT during manual (register) control 00: Register controlled by XO_EXTBUF7_EN_M 01: EN_BB

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 152 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

11 10:9

XO_EXTBUF6_EN_M XO_EXTBUF6_MODE

2 1 0

XO_32KDIV_TEST_EN XO_32KDIV_RATIO_MAN XO_32KDIV_SWRST

000007A0

DCXO_CW09_SET 15

Bit Name Type Reset Bit(s) 15:0

0

0

13

12

0

0

0

0

14

0

13

12

14

0

13

0

8

7

DCXO_CW09_SET W1 0 0

0

0

10

0

9

0

8

7

DCXO_CW09_CLR W1 0 0

5

4

3

2

1

0

0

0

0

0

0

0

0

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0000

Description Clears DCXO Code Word 9 0: Not clear 1: Clear

DCXO Code Word 10 12

11

10

9

8

7 XO_TH ADC_E N

Type Reset

RW 0

Name XO_THADC_EN XO_CAL_EN_M XO_CAL_EN_MAN XO_VIO18PG_BUFEN XO_EXTBUF4_CLKSEL_MAN

MediaTek Proprietary and Confidential.

0000 6

DCXO Code Word 9 Clear 11

DCXO_CW10 15

9

Description Sets up DCXO Code Word 9 0: Not set 1: Set

Name

4 3 2 1

0

10

Name DCXO_CW09_CLR

000007A4

Bit(s) 7

DCXO Code Word 9 Set 11

DCXO_CW09_CLR 15

Bit Name Type Reset

Bit

14

Name DCXO_CW09_SET

000007A2

Bit(s) 15:0

Description 10: CLK_SEL 11: EN_BB or CLK_SEL Enables/Disables XO_PD during manual (register) control 00: Register controlled by XO_EXTBUF6_EN_M 01: EN_BB 10: CLK_SEL 11: EN_BB or CLK_SEL DCXO 32K divider testing output thru DCXO_AUXOUT Manually sets the ratio of 32K divider high 32k digital divider software reset

8C14 6

5

4

3

2

1

0

XO_VI XO_EX XO_M XO_CA XO_CA O18PG TBUF4_ DB_TB L_EN_ L_EN_ _BUFE CLKSEL O_EN_ M MAN N _MAN SEL RW RW RW RW RW 1

0

1

0

0

Description Enables Vbe monitor by AUXADC For XO temperature sensing when XO_THADC_EN_MAN = 1. Enables CAL_EN manual when XO_CAL_EN_MAN = 1 CAL_EN manual control mux Buffer enable is gated by VIO18_PG or not 0: Enable/Disable XO_CEL from pin control

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Page 153 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 0

Name

Description 1: Enable/Disable XO_CEL from register Selects MDB tri-state buffer output enable control 0: From DIR TOP 1: From DCXO local control

XO_MDB_TBO_EN_SEL

000007A6

DCXO_CW11 15

Bit

14

13

DCXO Code Word 11 12

11

10

Type Reset

0

Name RG_XO_VOW_EN RG_XO_RESERVED6 RG_XO_HEATER_SEL

000007A8 Bit

Name

Type Reset

8

4821

7

6

5

4

3

2

1

4

3

2

1

0

RG_XO RG_XO RG_XO_HEATE _VOW_ _RESER R_SEL EN VED6 RW RW RW

Name

Bit(s) 9 8 7:6

9

14

13

RW 0

DCXO Code Word 12 12

11

RW

RW

RW

0

0

0

Bit(s) 15:14 13 12 11 6

Name RG_XO_AUDIO_ATTEN RG_XO_AUDIO_EN XO_EXTBUF2_CLKSEL_MAN XO_THADC_EN_MAN XO_EXTBUF7_BBLPM_EN_MASK

5

XO_EXTBUF6_BBLPM_EN_MASK

4

XO_EXTBUF4_BBLPM_EN_MASK

3

XO_EXTBUF3_BBLPM_EN_MASK

2

XO_EXTBUF2_BBLPM_EN_MASK

1

XO_EXTBUF1_BBLPM_EN_MASK

0

XO_BB_LPM_EN_SEL

MediaTek Proprietary and Confidential.

0

Setting to generate heat for calibration 00: No power 01: 133mW under VBAT = 4V 10: 266mW under VBAT = 4V 11: 400mW under VBAT = 4V

XO_EX XO_TH RG_XO RG_XO_AUDIO TBUF2_ ADC_E _AUDI _ATTEN CLKSEL N_MA O_EN _MAN N

1

0

Description 26MHz clk for VOW use

DCXO_CW12 15

0

10

9

8

7

8380 6

5

0

XO_EX XO_EX XO_EX XO_EX XO_EX XO_EX TBUF7_ TBUF6_ TBUF4_ TBUF3_ TBUF2_ TBUF1_ XO_BB BBLPM BBLPM BBLPM BBLPM BBLPM BBLPM _LPM_ _EN_M _EN_M _EN_M _EN_M _EN_M _EN_M EN_SEL ASK ASK ASK ASK ASK ASK RW RW RW RW RW RW RW 0

0

0

0

0

0

0

Description XO control signal of RC filter for internal audio output XO_AUDIO_EN_M XO_EXTBUF2_CLKSEL_MAN THADC enable manual mode 0: Non-mask 1: Masked BBLPM HW request 0: non-Mask 1: Masked BBLPM HW request 0: Non-mask 1: Masked BBLPM HW request 0: Non-mask 1: Masked BBLPM HW request 0: Non-mask 1: Masked BBLPM HW request 0: Non-mask 1: Masked BBLPM HW request BBLPM enable arbiter with enable mask 0: XO_BB_LPM_EN 1: HW bblpm arbiter

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 154 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

000007AA Bit

Description

DCXO_CW13 15

14

13

DCXO Code Word 13 12

11

10

9

8

7

004C 6

5

4

3

2

1

0

RG_XO RG_XO _DIG26 RG_XO_EXTBU RG_XO_EXTBU RG_XO_EXTBU RG_XO_EXTBU RG_XO_EXTBUF4_SRSE _DIG26 RG_XO_EXTBUF2_SRSE M_DIV Name F7_HD F6_HD F3_HD F1_HD L M_DEG L 2_SW_ LITCH MAN RW RW RW RW RW RW RW RW Type 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 Reset

Bit(s) 15:14

Name RG_XO_EXTBUF7_HD

13:12 11:10

RG_XO_EXTBUF6_HD RG_XO_EXTBUF3_HD

9:8

RG_XO_EXTBUF1_HD

7

RG_XO_DIG26M_DIV2_SW_MAN

6:4

RG_XO_EXTBUF4_SRSEL

3 2:0

RG_XO_DIG26M_DEGLITCH RG_XO_EXTBUF2_SRSEL

MediaTek Proprietary and Confidential.

Description XO control signal of EXTBUF7 output driving strength 2'b00: 26 sets 2'b01: 16 sets 2'b10: 8 sets 2'b11: 2 sets Not used in MT6359 XO control signal of EXTBUF3 output driving strength 2'b00: 26 sets 2'b01: 16 sets 2'b10: 8 sets 2'b11: 2 sets XO control signal of EXTBUF1 output driving strength 2'b00: 26 sets 2'b01: 16 sets 2'b10: 8 sets 2'b11: 2 sets CK_dig DIV2 control option 0: SW 1: HW XO control signal of EXTBUF4 output driving strength 3'b000: 0ohm 3'b001: 90ohm 3'b010: 160ohm 3'b011: 230ohm 3'b100: 390ohm 3'b101: 600ohm 3'b110: 830ohm 3'b111: 1100ohm Enables CK_dig deglitch XO control signal of EXTBUF2 output driving strength 3'b000: 0 ohm 3'b001: 90 ohm 3'b010: 160 ohm 3'b011: 230 ohm 3'b100: 390 ohm 3'b101: 600 ohm 3'b110: 830 ohm 3'b111: 1100 ohm

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 155 of 1067

MT6359 PMIC Datasheet Confidential A 000007AC

DCXO_CW14 15

Bit

14

13

DCXO Code Word 14 12

11

10

9

8

7

0F04 6

5

4

3

2

1

Name

XO_STA_CTL_M

Type Reset

0

1

0

3

2

1

Bit(s) 3:1 0

RW

Name XO_STA_CTL_M XO_STA_CTL_MAN

000007B6 Bit

14

0

Description Manual control value for DCXO mode from AP Manual control for DCXO mode from AP

DCXO_CW19 15

0 XO_ST A_CTL_ MAN RW

13

DCXO Code Word 19 12

11

10

9

8

7

9248 6

5

4

0

Name RG_XO_EXTBUF7_RSEL RG_XO_EXTBUF4_RSEL RG_XO_EXTBUF3_RSEL RG_XO_EXTBUF2_RSEL RG_XO_EXTBUF1_RSEL RW RW RW RW RW Type 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 Reset Bit(s) 15:13

Name RG_XO_EXTBUF7_RSEL

12:10

RG_XO_EXTBUF4_RSEL

9:7

RG_XO_EXTBUF3_RSEL

6:4

RG_XO_EXTBUF2_RSEL

MediaTek Proprietary and Confidential.

Description Selects XO_EXT output impedance for impedance matching 000: 70ohm 001: 60ohm 010: 55ohm 011: 50ohm 100: 45ohm 101: 35ohm 110: 30ohm 111: 25ohm Selects XO_CEL output impedance for impedance matching 000: 50ohm 001: 45ohm 010: 40ohm 011: 35ohm 100: 30ohm 101: 25ohm 110: 20ohm 111: 15ohm Selects XO_NFC output impedance for impedance matching 000: 70ohm 001: 60ohm 010: 55ohm 011: 50ohm 100: 45ohm 101: 35ohm 110: 30ohm 111: 25ohm Selects XO_WCN output impedance for impedance matching 000: 50ohm 001: 45ohm 010: 40ohm 011: 35ohm 100: 30ohm

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 156 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

3:1

Name

Description 101: 25ohm 110: 20ohm 111: 15ohm Selects XO_SOC output impedance for impedance matching 000: 70ohm 001: 60ohm 010: 55ohm 011: 50ohm 100: 45ohm 101: 35ohm 110: 30ohm 111: 25ohm

RG_XO_EXTBUF1_RSEL

00000910

PSC_TOP_INT_CON0 15

Bit

14

13

12

PSC_TOP INT Control Register 0 11

10

9

8

7

6

Type Reset

1

Name RG_INT_EN_CHRDET_EDGE

4

RG_INT_EN_NI_LBAT_INT

3

RG_INT_EN_HOMEKEY_R

2

RG_INT_EN_PWRKEY_R

1

RG_INT_EN_HOMEKEY

0

RG_INT_EN_PWRKEY

00000912 Bit Name Type Reset Bit(s) 15:0

4

3

2

1

0

RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT _EN_C _EN_NI _EN_H _EN_P _EN_H _EN_P HRDET _LBAT_ OMEKE WRKEY OMEKE WRKEY _EDGE INT Y_R _R Y RW RW RW RW RW RW

Name

Bit(s) 5

5

0025

0

14

0

13

12

0

0

Name PSC_INT_CON0_SET

MediaTek Proprietary and Confidential.

0

1

0

1

Description Enables CHRDET_EDGE interrupt 0: Not issue interrupt 1: Issue interrupt Enables NI_LBAT_INT interrupt 0: Not issue interrupt 1: Issue interrupt Enables HOMEKEY_R interrupt 0: Not issue interrupt 1: Issue interrupt Enables PWRKEY_R interrupt 0: Not issue interrupt 1: Issue interrupt Enables HOMEKEY interrupt 0: Not issue interrupt 1: Issue interrupt Enables PWRKEY interrupt 0: Not issue interrupt 1: Issue interrupt

PSC_TOP_INT_CON0_SET 15

0

11

0

PSC_TOP INT Control Register 0 SET 8

7

0000

10

9

6

5

4

3

2

1

0

0

PSC_INT_CON0_SET W1 0 0 0 0

0

0

0

0

0

0

Description Enables N0_SET interrupt

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 157 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00000914

Bit(s) 15:0

PSC_TOP_INT_CON0_CLR 15

Bit Name Type Reset

0

14

0

13

12

0

0

0

PSC_TOP INT Control Register 0 CLR 8

7

0000

10

9

6

5

4

3

2

1

0

0

PSC_INT_CON0_CLR W1 0 0 0 0

0

0

0

0

0

0

3

2

1

Description _INT_CON0_ SW 1'b0: Not clear 1'b1: Clear

PSC_TOP_INT_MASK_CON0 PSC_TOP INT Mask Control Register 0 15

14

13

12

11

10

9

8

7

6

5

4

0000 0

RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT _MASK _MASK _MASK _MASK _MASK _MASK _CHRD _NI_LB _HOME _PWRK _HOME _PWRK ET_ED AT_INT KEY_R EY_R KEY EY GE RW RW RW RW RW RW

Name

Type Reset Bit(s) 5

11

Name PSC_INT_CON0_CLR

00000916 Bit

Description 1'b0: Not set 1'b1: Set

0

Name RG_INT_MASK_CHRDET_EDGE

4

RG_INT_MASK_NI_LBAT_INT

3

RG_INT_MASK_HOMEKEY_R

2

RG_INT_MASK_PWRKEY_R

1

RG_INT_MASK_HOMEKEY

0

RG_INT_MASK_PWRKEY

MediaTek Proprietary and Confidential.

0

0

0

0

0

Description Masks CHRDET_EDGE interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks NI_LBAT_INT interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks HOMEKEY_R interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks PWRKEY_R interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks HOMEKEY interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks PWRKEY interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 158 of 1067

MT6359 PMIC Datasheet Confidential A 00000918 15

Bit Name Type Reset Bit(s) 15:0

PSC_TOP_INT_MASK_CON0_SPSC_TOP INT Mask Control Register 0 SET ET

0

0

12

0

11

0

0

0

9

8

7

6

PSC_INT_MASK_CON0_SET W1 0 0 0 0

5

4

3

2

1

0

0

0

0

0

0

0

Description 1'b0: Not set 1'b1: Set

14

0

13

0

12

0

11

0

10

0

Name PSC_INT_MASK_CON0_CLR

0000091C

PSC_TOP_INT_STATUS0 15

14

13

12

9

8

7

6

PSC_INT_MASK_CON0_CLR W1 0 0 0 0

0000

5

4

3

2

1

0

0

0

0

0

0

0

4

3

2

1

Description 1'b0: Not clear 1'b1: Clear

11

PSC_TOP INT Status Register 0 10

9

8

7

6

5

0000 0

RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT _STAT _STAT _STAT _STAT _STAT _STAT US_CH US_NI_ US_HO US_PW US_HO US_PW RDET_E LBAT_I MEKEY RKEY_R MEKEY RKEY DGE NT _R W1C W1C W1C W1C W1C W1C

Name

Type Reset Bit(s) 5

10

PSC_TOP_INT_MASK_CON0_ PSC_TOP INT Mask Control Register 0 CLR CLR 15

Bit Name Type Reset

Bit

0

13

Name PSC_INT_MASK_CON0_SET

0000091A

Bit(s) 15:0

14

0000

0

Name RG_INT_STATUS_CHRDET_EDGE

4

RG_INT_STATUS_NI_LBAT_INT

3

RG_INT_STATUS_HOMEKEY_R

2

RG_INT_STATUS_PWRKEY_R

1

RG_INT_STATUS_HOMEKEY

0

RG_INT_STATUS_PWRKEY

MediaTek Proprietary and Confidential.

0

0

0

0

0

Description CHRDET_EDGE interrupt status 0: No interrupt issued 1: Interrupt issued NI_LBAT_INT interrupt status 0: No interrupt issued 1: Interrupt issued HOMEKEY_R interrupt status 0: No interrupt issued 1: Interrupt issued PWRKEY_R interrupt status 0: No interrupt issued 1: Interrupt issued HOMEKEY interrupt status 0: No interrupt issued 1: Interrupt issued PWRKEY interrupt status 0: No interrupt issued 1: Interrupt issued

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 159 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

0000091E

PSC_TOP_INT_RAW_STATUS0 PSC_TOP INT Raw Status Register 0 15

Bit

Description

14

13

12

11

10

9

8

7

6

Type Reset

4

3

2

1

0

0

STRUP_ANA_CON1 15

14

13

Type Reset

2

1

0

0

0

0

4

3

2

1

STRUP Control Register 1 11

10

9

0

Bit(s) 9

Name RG_EN2_DRVSEL

8

RG_EN1_DRVSEL

6:3

12

8

7

6

RG_EN RG_EN RG_RS 2_DRV 1_DRV T_DRV SEL SEL SEL RW RW RW

Name

7

3

0

0

Name Description RG_INT_RAW_STATUS_CHRDET_EDGE CHRDET_EDGE raw interrupt status 0: No interrupt issued 1: Interrupt issued RG_INT_RAW_STATUS_NI_LBAT_INT NI_LBAT_INT raw interrupt status 0: No interrupt issued 1: Interrupt issued RG_INT_RAW_STATUS_HOMEKEY_R HOMEKEY_R raw interrupt status 0: No interrupt issued 1: Interrupt issued RG_INT_RAW_STATUS_PWRKEY_R PWRKEY_R raw interrupt status 0: No interrupt issued 1: Interrupt issued RG_INT_RAW_STATUS_HOMEKEY HOMEKEY raw interrupt status 0: No interrupt issued 1: Interrupt issued RG_INT_RAW_STATUS_PWRKEY PWRKEY raw interrupt status 0: No interrupt issued 1: Interrupt issued

0000098A Bit

0000 4

RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT _RAW_ _RAW_ _RAW_ _RAW_ _RAW_ _RAW_ STATUS STATUS STATUS STATUS STATUS STATU _CHRD _NI_LB _HOME _PWRK _HOME S_PWR ET_ED AT_INT KEY_R EY_R KEY KEY GE RO RO RO RO RO RO

Name

Bit(s) 5

5

RG_RST_DRVSEL

RG_PMU_RSV

MediaTek Proprietary and Confidential.

0

0

0

0020 5

0

RG_PMU_RSV

RGS_ANA_CHIP_ID

RW

RO

1

0

0

0

0

0

Description Selects EXT_PMIC_EN2 pin output driving capability 0: 7.5mA (default) 1: 15mA Selects EXT_PMIC_EN1 pin output driving capability 1: 15mA Selects reset pin output driving capability 0: 7.5mA (default) 1: 15mA Reserved bits

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 160 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

2:0

Name

RGS_ANA_CHIP_ID

0000098C

STRUP_ANA_CON2 15

Bit

Type Reset

RO 0

13

12

RO 0

RO 0

RO 0

10

14

13

12

9

8

7

RGS_V RGS_V RGS_V RGS_V SRAM_ SRAM_ SRAM_ SRAM_ PROC2 PROC1 OTHER MD_PG _PG_ST _PG_ST S_PG_S _STAT ATUS ATUS TATUS US RO RO RO RO 0 0 0 0

6

0000 5

4

3

2

1

RGS_V RGS_VI RGS_V RGS_V RGS_V RGS_V UFS_P O18_P EMC_P XO22_ AUD18 AUX18 G_STA G_STA G_STA PG_ST _PG_ST _PG_ST TUS TUS TUS ATUS ATUS ATUS RO 0

RO 0

RO 0

RO 0

RO 0

RO 0

STRUP Control Register 3 11

10

9

8

7

6

0

0

0

0

Name RGS_VS2_PG_STATUS RGS_VGPU12_PG_STATUS RGS_VGPU11_PG_STATUS RGS_VPU_PG_STATUS

Description VS2 PG status VGPU12 PG status VGPU11 PG status VCORE12 PG status

RGS_VPROC1_PG_STATUS RGS_VMODEM_PG_STATUS RGS_VS1_PG_STATUS RGS_VRF18_PG_STATUS RGS_VBBCK_PG_STATUS

VPROC1 PG status VMODEM PG status VS1 PG status VRF18 PG status VBBCK PG status

MediaTek Proprietary and Confidential.

RGS_V USB_P G_STA TUS RO 0

0000 5

4

3

2

1

RGS_V RGS_V RGS_V RGS_V RGS_V RGS_V RGS_V RGS_V RGS_V RGS_V GPU12 GPU11 PU_PG CORE_ PROC2 PROC1 MODE RF18_P S2_PG_ S1_PG_ _PG_ST _PG_ST _STAT PG_ST _PG_ST _PG_ST M_PG_ G_STA STATUS STATUS ATUS ATUS US ATUS ATUS ATUS STATUS TUS RO RO RO RO RO RO RO RO RO RO

Type Reset

0

Description VRFCK_1 PG status (MT6359P VRFCK_1/MT6359PP VRFCK) VM18 PG status VA09 PG status VA12 PG status VSRAM_PROC2 PG status VSRAM_PROC1 PG status VSRAM_OTHERS PG status VSRAM_MD PG status VUFS PG status VIO18 PG status VEMC PG status VXO22 PG status VAUD18 PG status VAUX18 PG status VUSB33 PG status

STRUP_ANA_CON3 15

Name

Bit(s) 10 9 8 7 6 5 4 3 2 1 0

STRUP Control Register 2 11

Name RGS_VRFCK_1_PG_STATUS RGS_VM18_PG_STATUS RGS_VA09_PG_STATUS RGS_VA12_PG_STATUS RGS_VSRAM_PROC2_PG_STATUS RGS_VSRAM_PROC1_PG_STATUS RGS_VSRAM_OTHERS_PG_STATUS RGS_VSRAM_MD_PG_STATUS RGS_VUFS_PG_STATUS RGS_VIO18_PG_STATUS RGS_VEMC_PG_STATUS RGS_VXO22_PG_STATUS RGS_VAUD18_PG_STATUS RGS_VAUX18_PG_STATUS RGS_VUSB_PG_STATUS

0000098E Bit

14

RGS_V RGS_V RGS_V RGS_V RFCK_1 M18_P A09_P A12_P _PG_ST G_STA G_STA G_STA ATUS TUS TUS TUS

Name

Bit(s) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description RG_PMU_RSV[2] is for PMIC BJT thermal sensor function on/off control 1'b0: Turn off BJT thermal sensor function 1'b1: Turn on BJT thermal sensor function Chip ID

0

0

0

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

0

0

0

0 RGS_V BBCK_ PG_ST ATUS RO 0

Page 161 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00000A08

PPCCTL0 15

Bit

Description

14

13

PPC Control 0 Register 12

11

10

9

8

7

5

4

3

2

1

RG_US RG_WDTRST_A BDL_M CT ODE RW RW

Name Type Reset

0

Bit(s) 6:5

Name RG_WDTRST_ACT

4

RG_USBDL_MODE

0

RG_PWRHOLD

00000A12 Bit

0000 6

14

13

RG_PW RHOLD RW

0

0

Description PSEQ WDT action 00: PMIC reg reset 01: Warm reset 10: Cold reset 11: Reserved For disabling BWDT in USBDL mode 0: Normal mode 1: USBDL mode -> disable BWDT Power hold 0->1: Power hold 1->0: Power down

STRUP_CON12 15

0

0

12

STRUP DIG Control Register 12 11

10

9

8

7

6

5

4000 4

3

2

1

0

RG_ST RUP_L RG_STRUP_LO RG_STRUP_LO ONG_P NG_PRESS_EXT NG_PRESS_EXT RESS_E _TD _SEL XT_EN RW RW RW

Name

Type Reset

0

Bit(s) 4

Name RG_STRUP_LONG_PRESS_EXT_EN

3:2

RG_STRUP_LONG_PRESS_EXT_TD

1:0

RG_STRUP_LONG_PRESS_EXT_SEL

MediaTek Proprietary and Confidential.

0

0

0

0

Description Enables re-power-on scenario function 1'b0: Disable long_press re-power on case 1'b1: Enable long_press re-power on case Selects delay time 2'b00: 0.5s 2'b01: 1s 2'b10: 2s Selects re-power-on scenario 2'b00: Debounce pwrkey 2'b01: After releasing pwrkey 2'b10: After releasing pwrkey and pressing pwrkey again

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 162 of 1067

MT6359 PMIC Datasheet Confidential A 00000A14

STRUP_CON13 15

Bit

14

13

12

STRUP DIG Control Register 13 11

10

9

8

7

6

5

0000 4

3

2

1

Name

Type Reset Bit(s) 0

0

Name RG_STRUP_PWRKEY_COUNT_RESET

00000A1A

Description Resets long press shut-down counter 1'b1: Reset long press counter 1'b0: Not reset long press counter

STRUP_CON4 15

Bit

14

13

STRUP DIG Control Register N4 12

11

10

9

8

7

6

5

0000 4

3

Type Reset

0

Name JUST_PWRKEY_RST JUST_SMART_RST

00000A20 Bit

2

1

0

JUST_P JUST_S WRKEY MART_ _RST RST RO RO

Name

Bit(s) 2 1

0 RG_ST RUP_P WRKEY _COUN T_RESE T RW

Description Long pressed reset indicator Smart reset indicator

STRUP_CON5 15

14

13

STRUP DIG Control Register N5 12

11

10

9

8

DA_EX DA_EX T_PMIC T_PMIC _EN2 _EN1 RO RO

Name Type Reset

0

Bit(s) 9

Name DA_EXT_PMIC_EN2

8

DA_EXT_PMIC_EN1

6

RGS_EXT_PMIC_PG

MediaTek Proprietary and Confidential.

0

0

7

6

5

0000 4

3

2

1

0

RGS_E XT_PM IC_PG RO 0

Description External PMIC power on signal 0: External PMIC shut-down 1: External PMIC power on External PMIC power on signal 0: External PMIC shutdown 1: External PMIC power on External PG status

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 163 of 1067

MT6359 PMIC Datasheet Confidential A 00000A88

CHR_CON0 15

Bit

14

13

Charger Control Register 0 12

11

10

9

8

7

6

0000 5

4

3

2

1

Name Type Reset Bit(s) 0

0

Name RGS_CHRDET

00000A8C

Description Detects charger-in after debounce 0: No valid charger detected 1: Valid charger detected

CHR_CON2 15

Bit

14

13

Charger Control Register 2 12

11

10

9

8

7

6

0000 5

4

3

2

Type Reset Name RG_ENVTEM_EN

0

RG_ENVTEM_D

00000A90

PCHR_VREF_ANA_CON0 15

14

0

Description Blocks CHR_DET signal to start_up 0: N/A 1: Write enable Blocks CHR_DET signal to start_up 0: Not block 1: Block

13

12

11

PCHR_VREF Control Register 0 10

9

8

7

6

5

0000 4

3

2

1

0

RG_BG RG_BG R_TEST R_TEST _EN _RSTB RW RW

Name Type Reset

1

0

0

Bit(s) 1

Bit(s) 2

1

RG_EN RG_EN VTEM_ VTEM_ EN D RW RW

Name

Bit

0 RGS_C HRDET RO

0

Name RG_BGR_TEST_EN

RG_BGR_TEST_RSTB

MediaTek Proprietary and Confidential.

0

Description Bandgap reference FT test mode enable signal 0: Normal_mode 1: Test mode (should combine PMU_TESTMODE = 1) Bandgap reference FT test mode resetb signal (also gated by RG_BGR_TEST_EN = 0 & PMU_TESTMODE = 0) -> GPIO control in test mode 0: Reset 1: Not reset

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Page 164 of 1067

MT6359 PMIC Datasheet Confidential A 00000A92

PCHR_VREF_ANA_CON1 15

Bit

14

13

12

11

PCHR_VREF Control Register 1 10

9

8

7

6

Name

1 0

Name RG_UVLO_VTHL

2

RG_BGR_UNCHOP_PH RG_BGR_UNCHOP

PCHR_VREF_ANA_CON2 15

14

13

0

1

0

RG_BG RG_BG R_UNC R_UNC HOP_P HOP H RW RW

0

1

0

0

4

3

2

1

0

Description Selects UVLO low threshold 00000: 2.5V 00001: 2.55V 00010: 2.6V (default) 00011: 2.65V 00100: 2.7V 00101: 2.75V 00110: 2.8V 00111: 2.85V 01000: 2.9V Selects BGR unchop mode phase BGR unchop mode 0: Chop 1: Unchop

12

11

PCHR_VREF Control Register 2 10

9

8

7

6

Name Type Reset Bit(s) 4:0

3

RW 0

00000A94 Bit

4

RG_UVLO_VTHL

Type Reset Bit(s) 6:2

0008

5

5

0003 0

RG_LBAT_INT_VTH RW 0

Name RG_LBAT_INT_VTH

MediaTek Proprietary and Confidential.

0

0

1

1

Description LBAT_INT threshold voltage 00000: 2.5V 00001: 2.55V 00010: 2.6V 00011: 2.65V (default) 00100: 2.7V 00101: 2.75V 00110: 2.8V 00111: 2.85V 01000: 2.9V 01001: 2.95V 01010: 3.0V 01011: 3.05V 01100: 3.1V 01101: 3.15V 01110: 3.2V 01111: 3.25V 10000: 3.3V 10001: 3.35V 10010: 3.4V

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 165 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00000A96

PCHR_VREF_ANA_CON3 15

Bit

Description

14

13

12

11

PCHR_VREF Control Register 3 10

9

8

7

6

5

0001 4

3

2

Name Type Reset Bit(s) 2:0

RW 0

Name RG_OVLO_VTH_SEL

PCHR_VREF_ELR_0 15

14

13

12

PCHR_VREF ELR 0 Register 11

10

9

RW 0

Name RG_BGR_RSEL

MediaTek Proprietary and Confidential.

1

0

0

8

7

6

0500 5

4

RG_BG R_TRI M_EN RW

RG_BGR_RSEL

Type Reset

0

Description OVLO VTH SEL bits 000: SD: 5.4V, recover: 5.0V 001: SD: 5.6V, recover: 5.2V (default) 010: SD: 5.8V, recover: 5.4V 011: SD: 6.0V, recover: 5.6V 100: SD: 5.4V, recover: 5.0V 101: SD: 5.6V, recover: 5.2V 110: SD: 5.8V, recover: 5.4V 111: SD: 6.0V, recover: 5.6V

Name

Bit(s) 13:9

0

RG_OVLO_VTH_SEL

00000A9E Bit

1

1

0

1

3

2

1

0

0

0

RG_BGR_TRIM RW 0

0

0

0

Description Selects BGR resistor (R0 = R1) (Trim TC curve) (add one bit LSB @ MT6359) R2 = 8.5*Runit, and VBG = (R0/R2)*dVBE + VBE 11111: R0 = 59.3*Runit, VBG = 1.091V 11110: R0 = 60.3*Runit, VBG = 1.098V 11101: R0 = 61.3*Runit, VBG = 1.104V 11100: R0 = 62.3*Runit, VBG = 1.111V 11011: R0 = 63.3*Runit, VBG = 1.117V 11010: R0 = 64.3*Runit, VBG = 1.124V 11001: R0 = 65.3*Runit, VBG = 1.130V 11000: R0 = 66.3*Runit, VBG = 1.136V 10111: R0 = 67.3*Runit, VBG = 1.143V 10110: R0 = 68.3*Runit, VBG = 1.149V 10101: R0 = 69.3*Runit, VBG = 1.156V 10100: R0 = 70.3*Runit, VBG = 1.162V 10011: R0 = 71.3*Runit, VBG = 1.169V 10010: R0 = 72.3*Runit, VBG = 1.175V 10001: R0 = 73.3*Runit, VBG = 1.181V 10000: R0 = 74.3*Runit, VBG = 1.188V 00000: R0 = 75.3*Runit, VBG = 1.194V 00001: R0 = 76.3*Runit, VBG = 1.201V 00010: R0 = 77.3*Runit, VBG = 1.207V (default) 00011: R0 = 78.3*Runit, VBG = 1.214V © 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 166 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

8 5:0

Name

RG_BGR_TRIM_EN RG_BGR_TRIM

00000C32 Bit

Description 00100: R0 = 79.3*Runit, VBG = 1.220V 00101: R0 = 80.3*Runit, VBG = 1.226V 00110: R0 = 81.3*Runit, VBG = 1.233V 00111: R0 = 82.3*Runit, VBG = 1.239V 01000: R0 = 83.3*Runit, VBG = 1.246V 01001: R0 = 84.3*Runit, VBG = 1.252V 01010: R0 = 85.3*Runit, VBG = 1.259V 01011: R0 = 86.3*Runit, VBG = 1.265V 01100: R0 = 87.3*Runit, VBG = 1.271V 01101: R0 = 88.3*Runit, VBG = 1.278V 01110: R0 = 89.3*Runit, VBG = 1.284V 01111: R0 = 90.3*Runit, VBG = 1.291V 0: Disable BG trimming and bypass voltage buffer 1: Enable BG trimming and voltage buffer Trims BGR buffer output voltage (add one bit and change LSB from 5mV to 2.5mV @ MT6359) Default: 1.205V @ 00000 10000~11111: VBG = 1.125V~1.200V with 2.5mV/step 00000~01111: VBG = 1.205V~1.280V with 2.5mV/step

BM_TOP_INT_CON0 15

14

13

12

RG_INT RG_INT _EN_F _EN_F G_CHA G_DISC RGE HARGE

Name

Type Reset Bit(s) 12

BM_TOP_INT Control Register 0 11

RW

RW

0

0

Name RG_INT_EN_FG_CHARGE

11

RG_INT_EN_FG_DISCHARGE

9

RG_INT_EN_FG_IAVG_L

8

RG_INT_EN_FG_IAVG_H

7

RG_INT_EN_FG_N_CHARGE_L

4

RG_INT_EN_FG_ZCV

3

RG_INT_EN_FG_CUR_L

2

RG_INT_EN_FG_CUR_H

MediaTek Proprietary and Confidential.

10

9

8

7

6

5

RG_INT RG_INT RG_INT _EN_F _EN_F _EN_F G_N_C G_IAV G_IAV HARGE G_L G_H _L RW RW RW 0

0

0

0000 4

3

2

1

0

RG_INT RG_INT RG_INT RG_INT RG_INT _EN_F _EN_F _EN_F _EN_F _EN_F G_CUR G_CUR G_BAT G_BAT G_ZCV _L _H _L _H RW

RW

RW

RW

RW

0

0

0

0

0

Description Enables FG_CHARGE interrupt 1'b0: Not issue interrupt 1'b1: Issue interrupt Enables FG_DISCHARGE interrupt 1'b0: Not issue interrupt 1'b1: Issue interrupt Enables FG_IAVG_L interrupt 1'b0: Not issue interrupt 1'b1: Issue interrupt Enables FG_IAVG_H interrupt 1'b0: Not issue interrupt 1'b1: Issue interrupt Enables FG_N_CHARGE_L interrupt 1'b0: Not issue interrupt 1'b1: Issue interrupt Enables FG_ZCV interrupt 1'b0: Not issue interrupt 1'b1: Issue interrupt Enables FG_CUR_L interrupt 1'b0: Not issue interrupt 1'b1: Issue interrupt Enables FG_CUR_H interrupt

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 167 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

1

RG_INT_EN_FG_BAT_L

0

RG_INT_EN_FG_BAT_H

00000C34

Bit(s) 15:0

BM_TOP_INT_CON0_SET 15

Bit Name Type Reset

0

0

13

0

12

0

11

0

BM_TOP_INT Control Register 0 SET

0

14

0

13

0

12

0

9

6

5

4

3

2

1

0

0

BM_TOP_INT_CON0_SET W1 0 0 0 0

0

0

0

0

0

0

11

0

BM_TOP_INT Control Register 0 CLR

14

13

12

8

7

9

6

5

4

3

2

1

0

0

BM_TOP_INT_CON0_CLR W1 0 0 0 0

0

0

0

0

0

0

Description Clears BM_TOP_INT_CON0 1'b0: Not clear 1'b1: Clear

BM_TOP_INT Control Register 1 11

10

9

8

7

6

5

0000 4

3

2

RG_INT RG_INT RG_INT _EN_B _EN_B _EN_BI ATON_ ATON_ F BAT_O BAT_IN UT RW RW RW

Name Type Reset Bit(s) 4

0000

10

BM_TOP_INT_CON1 15

7

Description Sets up BM_TOP_INT_CON0 1'b0: Not set 1'b1: Set

Name BM_TOP_INT_CON0_CLR

00000C38

8

0000

10

BM_TOP_INT_CON0_CLR 15

Bit Name Type Reset

Bit

14

Name BM_TOP_INT_CON0_SET

00000C36

Bit(s) 15:0

Description 1'b0: Not issue interrupt 1'b1: Issue interrupt Enables FG_BAT_L interrupt 1'b0: Not issue interrupt 1'b1: Issue interrupt Enables FG_BAT_H interrupt 1'b0: Not issue interrupt 1'b1: Issue interrupt

0

Name RG_INT_EN_BIF

3

RG_INT_EN_BATON_BAT_OUT

2

RG_INT_EN_BATON_BAT_IN

MediaTek Proprietary and Confidential.

0

0

1

0 RG_INT _EN_B ATON_ LV RW 0

Description Enables BIF interrupt 1'b0: Not issue interrupt 1'b1: Issue interrupt Enables BATON_BAT_OUT interrupt 1'b0: Not issue interrupt 1'b1: Issue interrupt Enables BATON_BAT_IN interrupt

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 168 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

0

Name

RG_INT_EN_BATON_LV

00000C3A

BM_TOP_INT_CON1_SET 15

Bit Name Type Reset Bit(s) 15:0

0

0

0

0

12

0

11

BM_TOP_INT Control Register 1 SET 9

6

5

4

3

2

1

0

0

BM_TOP_INT_CON1_SET W1 0 0 0 0

0

0

0

0

0

0

0

14

0

13

0

12

0

14

13

12

11

BM_TOP_INT Control Register 1 CLR

Type Reset

0

9

7

6

5

4

3

2

1

0

0

BM_TOP_INT_CON1_CLR W1 0 0 0 0

0

0

0

0

0

0

Description Clears BM_TOP_INT_CON1 1'b0: Not clear 1'b1: Clear

11

0

Name RG_INT_MASK_FG_CHARGE

11

RG_INT_MASK_FG_DISCHARGE

9

RG_INT_MASK_FG_IAVG_L

8

RG_INT_MASK_FG_IAVG_H

MediaTek Proprietary and Confidential.

8

0000

10

0

RG_INT RG_INT _MASK _MASK _FG_DI _FG_C SCHAR HARGE GE RW RW

Name

7

Description Sets up BM_TOP_INT_CON1 1'b0: Not set 1'b1: Set

BM_TOP_INT_MASK_CON0 15

8

0000

10

Name BM_TOP_INT_CON1_CLR

00000C3E

Bit(s) 12

13

BM_TOP_INT_CON1_CLR 15

Bit Name Type Reset

Bit

14

Name BM_TOP_INT_CON1_SET

00000C3C

Bit(s) 15:0

Description 1'b0: Not issue interrupt 1'b1: Issue interrupt Enables BATON_LV interrupt 1'b0: Not issue interrupt 1'b1: Issue interrupt

10

BM_TOP_INT_MASK Control Register 0 9

8

7

RG_INT RG_INT RG_INT _MASK _MASK _MASK _FG_N _FG_IA _FG_IA _CHAR VG_L VG_H GE_L RW RW RW 0

0

6

5

4

0000 3

2

1

0

RG_INT RG_INT RG_INT RG_INT RG_INT _MASK _MASK _MASK _MASK _MASK _FG_ZC _FG_C _FG_C _FG_B _FG_B V UR_L UR_H AT_L AT_H

0

RW

RW

RW

RW

RW

0

0

0

0

0

Description Masks FG_CHARGE interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks FG_DISCHARGE interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks FG_IAVG_L interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks FG_IAVG_H interrupt status

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 169 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

7

RG_INT_MASK_FG_N_CHARGE_L

4

RG_INT_MASK_FG_ZCV

3

RG_INT_MASK_FG_CUR_L

2

RG_INT_MASK_FG_CUR_H

1

RG_INT_MASK_FG_BAT_L

0

RG_INT_MASK_FG_BAT_H

BM_TOP_INT_MASK_CON0_S BM_TOP_INT Mask Control Register 0 SET ET

00000C40 15

Bit Name Type Reset Bit(s) 15:0

0

Bit(s) 15:0

14

0

13

0

12

0

11

0

10

0

Name BM_TOP_INT_MASK_CON0_SET

00000C42 Bit Name Type Reset

Description 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks FG_N_CHARGE_L interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks FG_ZCV interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks FG_CUR_L interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks FG_CUR_H interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks FG_BAT_L interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks FG_BAT_H interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status

9

8

7

6

BM_TOP_INT_MASK_CON0_SET W1 0 0 0 0

0000

5

4

3

2

1

0

0

0

0

0

0

0

Description Sets up BM_TOP_INT_MASK_CON0 1'b0: Not set 1'b1: Set

BM_TOP_INT_MASK_CON0_C BM_TOP_INT Mask Control Register 0 CLR LR 15

0

14

0

13

0

12

0

11

0

Name BM_TOP_INT_MASK_CON0_CLR

MediaTek Proprietary and Confidential.

10

0

9

8

7

6

BM_TOP_INT_MASK_CON0_CLR W1 0 0 0 0

0000

5

4

3

2

1

0

0

0

0

0

0

0

Description Clears BM_TOP_INT_MASK_CON0 1'b0: Not clear 1'b1: Clear

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 170 of 1067

MT6359 PMIC Datasheet Confidential A 00000C44

BM_TOP_INT_MASK_CON1 15

Bit

14

13

12

11

BM_TOP_INT_MASK Control Register 1

10

9

8

7

6

5

Type Reset

0

Name RG_INT_MASK_BIF

3

RG_INT_MASK_BATON_BAT_OUT

2

RG_INT_MASK_BATON_BAT_IN

0

RG_INT_MASK_BATON_LV

00000C46

0

Bit(s) 15:0

1

0

14

0

13

0

12

0

11

0

RG_INT _MASK _BATO N_LV RW

0

0

10

0

9

8

7

6

BM_TOP_INT_MASK_CON1_SET W1 0 0 0 0

0000

5

4

3

2

1

0

0

0

0

0

0

0

Description Sets up BM_TOP_INT_MASK_CON1 1'b0: Not set 1'b1: Set

BM_TOP_INT_MASK_CON1_C BM_TOP_INT Mask Control Register 1 CLR LR 15

0

14

0

13

0

12

0

11

0

Name BM_TOP_INT_MASK_CON1_CLR

MediaTek Proprietary and Confidential.

0

Description Masks BIF interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks BATON_BAT_OUT interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks BATON_BAT_IN interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks BATON_LV interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status

Name BM_TOP_INT_MASK_CON1_SET

00000C48 Bit Name Type Reset

2

BM_TOP_INT_MASK_CON1_S BM_TOP_INT Mask Control Register 1 SET ET 15

Bit Name Type Reset Bit(s) 15:0

0000 3

RG_INT RG_INT RG_INT _MASK _MASK _MASK _BATO _BATO _BIF N_BAT N_BAT _OUT _IN RW RW RW

Name

Bit(s) 4

4

10

0

9

8

7

6

BM_TOP_INT_MASK_CON1_CLR W1 0 0 0 0

0000

5

4

3

2

1

0

0

0

0

0

0

0

Description Clears BM_TOP_INT_MASK_CON1 1'b0: Not clear 1'b1: Clear

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 171 of 1067

MT6359 PMIC Datasheet Confidential A 00000C4A

BM_TOP_INT_STATUS0 15

Bit

14

13

11

Type Reset

W1C

W1C

0

0

RG_INT_STATUS_FG_DISCHARGE

9

RG_INT_STATUS_FG_IAVG_L

8

RG_INT_STATUS_FG_IAVG_H

7

RG_INT_STATUS_FG_N_CHARGE_L

4

RG_INT_STATUS_FG_ZCV

3

RG_INT_STATUS_FG_CUR_L

2

RG_INT_STATUS_FG_CUR_H

1

RG_INT_STATUS_FG_BAT_L

0

RG_INT_STATUS_FG_BAT_H

00000C4C

0

14

Name

Type Reset

MediaTek Proprietary and Confidential.

13

12

11

8

7

6

5

0

0000 4

3

2

1

0

RG_INT RG_INT RG_INT RG_INT RG_INT _STAT _STAT _STAT _STAT _STAT US_FG US_FG US_FG US_FG US_FG _CUR_ _BAT_ _ZCV _CUR_L _BAT_L H H

0

W1C

W1C

W1C

W1C

W1C

0

0

0

0

0

4

3

2

1

Description FG_CHARGE interrupt status 1'b0: No interrupt issued 1'b1: Interrupt issued FG_DISCHARGE interrupt status 1'b0: No interrupt issued 1'b1: Interrupt issued FG_IAVG_L interrupt status 1'b0: No interrupt issued 1'b1: Interrupt issued FG_IAVG_H interrupt status 1'b0: No interrupt issued 1'b1: Interrupt issued FG_N_CHARGE_L interrupt status 1'b0: No interrupt issued 1'b1: Interrupt issued FG_ZCV interrupt status 1'b0: No interrupt issued 1'b1: Interrupt issued FG_CUR_L interrupt status 1'b0: No interrupt issued 1'b1: Interrupt issued FG_CUR_H interrupt status 1'b0: No interrupt issued 1'b1: Interrupt issued FG_BAT_L interrupt status 1'b0: No interrupt issued 1'b1: Interrupt issued FG_BAT_H interrupt status 1'b0: No interrupt issued 1'b1: Interrupt issued

BM_TOP_INT_STATUS1 15

9

RG_INT RG_INT RG_INT _STAT _STAT _STAT US_FG US_FG US_FG _N_CH _IAVG_ _IAVG_ ARGE_ L H L W1C W1C W1C

Name RG_INT_STATUS_FG_CHARGE

11

Bit

BM_TOP_INT Status Register 0 10

RG_INT RG_INT _STAT _STAT US_FG US_FG _CHAR _DISCH GE ARGE

Name

Bit(s) 12

12

BM_TOP_INT Status Register 1 10

9

8

7

6

5

0000 RG_INT RG_INT _STAT RG_INT _STAT US_BA _STAT US_BA TON_B US_BIF TON_B AT_OU AT_IN T W1C W1C W1C 0

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

0

0

0 RG_INT _STAT US_BA TON_L V W1C 0

Page 172 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 4

Name RG_INT_STATUS_BIF

3

RG_INT_STATUS_BATON_BAT_OUT

2

RG_INT_STATUS_BATON_BAT_IN

0

RG_INT_STATUS_BATON_LV

00000C4E Bit

BM_TOP_INT_RAW_STATUS0 BM_TOP_INT Raw Status Register 0 15

14

Type Reset

11

9

8

7

4

3

2

1

0

13

12

11

RG_INT RG_INT _RAW_ _RAW_ STATUS STATUS _FG_DI _FG_C SCHAR HARGE GE RO RO

Name

Bit(s) 12

Description BIF interrupt status 1'b0: No interrupt issued 1'b1: Interrupt issued BATON_BAT_OUT interrupt status 1'b0: No interrupt issued 1'b1: Interrupt issued BATON_BAT_IN interrupt status 1'b0: No interrupt issued 1'b1: Interrupt issued BATON_LV interrupt status 1'b0: No interrupt issued 1'b1: Interrupt issued

0

0

10

9

8

7

RG_INT RG_INT RG_INT _RAW_ _RAW_ _RAW_ STATUS STATUS STATUS _FG_N _FG_IA _FG_IA _CHAR VG_L VG_H GE_L RO RO RO 0

0

6

5

0000 4

3

2

1

0

RG_INT RG_INT RG_INT RG_INT RG_INT _RAW_ _RAW_ _RAW_ _RAW_ _RAW_ STATUS STATUS STATUS STATUS STATU _FG_ZC _FG_C _FG_C _FG_B S_FG_B V UR_L UR_H AT_L AT_H

0

RO

RO

RO

RO

RO

0

0

0

0

0

Name RG_INT_RAW_STATUS_FG_CHARGE

Description FG_CHARGE raw interrupt status 1'b0: No interrupt issued 1'b1: Interrupt issued RG_INT_RAW_STATUS_FG_DISCHARGE FG_DISCHARGE raw interrupt status 1'b0: No interrupt issued 1'b1: Interrupt issued RG_INT_RAW_STATUS_FG_IAVG_L FG_IAVG_L raw interrupt status 1'b0: No interrupt issued 1'b1: Interrupt issued RG_INT_RAW_STATUS_FG_IAVG_H FG_IAVG_H raw interrupt status 1'b0: No interrupt issued 1'b1: Interrupt issued RG_INT_RAW_STATUS_FG_N_CHARGE FG_N_CHARGE_L raw interrupt status _L 1'b0: No interrupt issued 1'b1: Interrupt issued RG_INT_RAW_STATUS_FG_ZCV FG_ZCV raw interrupt status 1'b0: No interrupt issued 1'b1: Interrupt issued RG_INT_RAW_STATUS_FG_CUR_L FG_CUR_L raw interrupt status 1'b0: No interrupt issued 1'b1: Interrupt issued RG_INT_RAW_STATUS_FG_CUR_H FG_CUR_H raw interrupt status 1'b0: No interrupt issued 1'b1: Interrupt issued RG_INT_RAW_STATUS_FG_BAT_L FG_BAT_L raw interrupt status 1'b0: No interrupt issued 1'b1: Interrupt issued RG_INT_RAW_STATUS_FG_BAT_H FG_BAT_H raw interrupt status

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 173 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00000C50

BM_TOP_INT_RAW_STATUS1 BM_TOP_INT Raw Status Register 1 15

Bit

Description 1'b0: No interrupt issued 1'b1: Interrupt issued

14

13

12

11

10

9

8

7

6

5

3

2

1

RG_INT RG_INT RG_INT _RAW_ _RAW_ _RAW_ STATUS STATUS STATUS _BATO _BATO _BIF N_BAT N_BAT _OUT _IN RO RO RO

Name

Type Reset Bit(s) 4

0000 4

Name RG_INT_RAW_STATUS_BIF

3

RG_INT_RAW_STATUS_BATON_BAT_ OUT

2

RG_INT_RAW_STATUS_BATON_BAT_ IN

0

RG_INT_RAW_STATUS_BATON_LV

00000C52

14

13

12

11

0

0

4

3

2

RG_INT _RAW_ STATU S_BAT ON_LV RO 0

Description BIF raw interrupt status 1'b0: No interrupt issued 1'b1: Interrupt issued BATON_BAT_OUT raw interrupt status 1'b0: No interrupt issued 1'b1: Interrupt issued BATON_BAT_IN raw interrupt status 1'b0: No interrupt issued 1'b1: Interrupt issued BATON_LV raw interrupt status 1'b0: No interrupt issued 1'b1: Interrupt issued

BM_TOP_INT_MISC_CON 15

Bit

0

BM_TOP_INT MISC Control Register 10

9

8

7

6

5

0000 1

Type Reset

0

Name POLARITY

00000D16

0

0

0

Bit Name Type 0 Reset Bit(s) 15:0

0 POLARI TY RW

Name

Bit(s) 0

0

Description Inverts interrupt source polarity 1'b0: Not invert interrupt source polarity 1'b1: Invert interrupt source polarity

FGADC_CAR_CON0 15

14

13

12

FGADC_CAR Control Register 0 11

10

9

8

7

6

5

0000 4

3

2

1

0

0

0

0

FG_CAR_15_00 RO

Name FG_CAR_15_00

MediaTek Proprietary and Confidential.

Description Current charge value [15:0] (signed value)

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 174 of 1067

MT6359 PMIC Datasheet Confidential A 00000D18

Bit(s) 15:0

FGADC_CAR_CON1 15

Bit Name Type Reset

0

0

0

0

14

13

0

14

0

13

0

14

12

0

13

0

14

0

8

7

FG_CAR_31_16 RO 0 0

0

0

10

0

0

13

9

0

8

7

FG_NCAR_15_00 RO 0 0

Name FG_IAVG_VLD

MediaTek Proprietary and Confidential.

5

4

3

2

1

0

0

0

0

0

0

0

0

0000

6

5

4

3

2

1

0

0

0

0

0

0

0

0

Description Current n_charge value[15:0] (signed value)

12

0

FGADC_NCAR Control Register 1 11

0

10

0

9

0

8

7

FG_NCAR_31_16 RO 0 0

0000

6

5

4

3

2

1

0

0

0

0

0

0

0

0

Description Current n_charge value[31:16] (signed value)

12

0

FGADC_IAVG Control Register 0 11

0

10

0

9

0

8

7

FG_IAVG_15_00 RO 0 0

0000

6

5

4

3

2

1

0

0

0

0

0

0

0

0

Description Current FGADC average current [15:0] (signed value) Unit of FG_IAVG is [LSB of charge/32].

12

FGADC_IAVG Control Register 1 11

10

9

8

7

FG_IAV G_VLD RO 0

0000

6

FGADC_NCAR Control Register 0 11

FGADC_IAVG_CON1 15

9

Description Current charge value [31:16] (signed value)

Name FG_IAVG_15_00

00000D2E

Bit(s) 15

0

FGADC_IAVG_CON0 15

Bit Name Type Reset

Type Reset

0

Name FG_NCAR_31_16

00000D2C

Name

0

10

FGADC_NCAR_CON1 15

Bit Name Type Reset

Bit

0

FGADC_CAR Control Register 1 11

Name FG_NCAR_15_00

00000D26

Bit(s) 15:0

0

12

FGADC_NCAR_CON0 15

Bit Name Type Reset

Bit(s) 15:0

13

Name FG_CAR_31_16

00000D24

Bit(s) 15:0

14

6

5

0000 4

3

2

1

0

0

0

0

0

0

FG_IAVG_27_16 RO 0

0

0

0

0

0

0

Description FGADC average current valid

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 175 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

11:0

FG_IAVG_27_16

00000D38

Bit(s) 15:0

FGADC_NTER_CON0 15

Bit Name Type Reset

0

14

13

0

0

14

0

10

0

9

0

8

7

FG_NTER_15_00 RO 0 0

0000

6

5

4

3

2

1

0

0

0

0

0

0

0

0

5

4

3

2

1

0

0

0

0

0

0

0

Description Time value [15:0]

13

Name Type Reset

12

FGADC_NTER Control Register 1 11

10

9

8

7

6

0000

FG_NTER_29_16 RO 0

0

0

0

Name FG_NTER_29_16

00000D8A

0

14

0

13

12

14

0

0

0

0

0

13

8

7

0000

10

9

6

5

4

3

2

1

0

0

FG_CURRENT_OUT RO 0 0 0 0

0

0

0

0

0

0

Description Current output charge of first CIC stage [15:0] (signed value)

BATON_ANA_CON0 15

0

FGADC_CUR Control Register 0 11

Name FG_CURRENT_OUT

00000E08

0

Description Time value [29:16]

FGADC_CUR_CON0 15

Bit Name Type Reset

Bit

0

FGADC_NTER Control Register 0 11

FGADC_NTER_CON1 15

Bit

Bit(s) 15:0

12

Name FG_NTER_15_00

00000D3A

Bit(s) 13:0

Description 1'b0: Invalid 1'b1: Valid Current FGADC average current [27:16] (signed value)

12

BATON Analog Control Register 0 11

10

9

8

7

6

5

0005 4

3

Name Type Reset Bit(s) 2

0

Name RG_QI_BATON_LT_EN

RG_BATON_EN

MediaTek Proprietary and Confidential.

2

1

0

RG_QI_ BATON _LT_EN RW

RG_BA TON_E N RW

1

1

Description Enables battery-on HW low temperature detection 0: Disable 1: Enable Enables BATON battery detection comparator 0: Disable 1: Enable (default)

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 176 of 1067

MT6359 PMIC Datasheet Confidential A 00000E88

BATON_CON0 15

Bit

14

13

BATON Control Register 0 12

11

10

9

8

7

6

0001 5

4

Type Reset

0

Bit(s) 3:2

Name RG_BATON_DEBOUNCE_THD

1:0

RG_BATON_DEBOUNCE_WND

00000F08

14

13

11

10

0

Name BIF_COMMAND_0

BIF_CON1 15

9

8

7

0000 6

5

4

3

2

1

0

14

13

0

0

0

0

0

0

0

0

0

0

6

5

4

3

2

1

0

0

0

0

0

BIF Control Register 1 12

11

10

9

8

7

0000 BIF_COMMAND_1 RW

0

Name BIF_COMMAND_1

00000F0C

14

13

0

0

0

0

0

Description Command queue 1

BIF_CON2 15

0

BIF Control Register 2 12

11

10

9

8

Name Type 0 Reset Bit(s) 10:0

1

Description Command queue 0

Name Type Reset

0

0

RW

Bit

0

0

BIF_COMMAND_0

00000F0A

0

0

BIF Control Register 0 12

Name Type Reset

Bit

1

Description Battery status debounce threshold setting in decision windows 2'b00: 4/8 2'b01: 3/8 2'b10: 2/8 2'b11: 1/8 Battery status debounce decision window setting 2'b00: 6T of 32kHz clock 2'b01: 11T of 32kHz clock 2'b10: 21T of 32kHz clock 2'b11: 41T of 32kHz clock

BIF_CON0 15

Bit

Bit(s) 10:0

2

RG_BATON_DE RG_BATON_DE BOUNCE_THD BOUNCE_WND RW RW

Name

Bit(s) 10:0

3

7

0000 6

5

4

3

2

1

0

0

0

0

BIF_COMMAND_2 RW

Name BIF_COMMAND_2

MediaTek Proprietary and Confidential.

Description Command queue 2

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 177 of 1067

MT6359 PMIC Datasheet Confidential A 00000F0E

BIF_CON3 15

Bit

14

13

BIF Control Register 3 12

11

Name Type Reset Bit(s) 10:0

Name BIF_COMMAND_3

BIF_CON4 15

14

13

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

6

5

4

3

2

1

0

0

BIF Control Register 4 12

11

10

9

8

7

0000

RW 0

Name BIF_COMMAND_4

14

13

0

0

0

0

0

0

0

0

0

6

5

4

3

2

1

0

0

Description Command queue 4

BIF_CON5 15

Bit

BIF Control Register 5 12

11

Name Type Reset

10

9

8

7

0000 BIF_COMMAND_5 RW

0

Name BIF_COMMAND_5

00000F14

14

13

0

0

0

0

0

0

0

0

0

6

5

4

3

2

1

0

0

Description Command queue 5

BIF_CON6 15

Bit

BIF Control Register 6 12

11

Name Type Reset

10

9

8

7

0000 BIF_COMMAND_6 RW

0

Name BIF_COMMAND_6

00000F16

14

13

0

0

0

0

0

0

0

0

0

6

5

4

3

2

1

0

0

0

0

0

Description Command queue 6

BIF_CON7 15

Name Type Reset Bit(s) 10:0

0000 6

BIF_COMMAND_4

00000F12

Bit

7

Description Command queue 3

Name Type Reset

Bit(s) 10:0

8

RW 0

Bit

Bit(s) 10:0

9

BIF_COMMAND_3

00000F10

Bit(s) 10:0

10

BIF Control Register 7 12

11

10

9

8

7

0000 BIF_COMMAND_7 RW

0

Name BIF_COMMAND_7

MediaTek Proprietary and Confidential.

0

0

0

0

0

0

Description Command queue 7

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 178 of 1067

MT6359 PMIC Datasheet Confidential A 00000F18

BIF_CON8 15

Bit

14

BIF Control Register 8

13

12

11

Name Type Reset Bit(s) 10:0

Name BIF_COMMAND_8

BIF_CON9 15

14

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

6

5

4

3

2

1

0

0

BIF Control Register 9

13

12

11

10

9

8

0000

7

RW 0

Name BIF_COMMAND_9

14

0

0

0

0

0

0

0

0

0

6

5

4

3

2

1

0

0

Description Command queue 9

BIF_CON10 15

Bit

13

BIF Control Register 10 12

11

Name Type Reset

10

9

8

7

0000

BIF_COMMAND_10 RW 0

Name BIF_COMMAND_10

00000F1E

14

13

0

0

0

0

0

0

0

0

0

6

5

4

3

2

1

0

0

Description Command queue 10

BIF_CON11 15

Bit

BIF Control Register 11 12

11

Name Type Reset

10

9

8

7

0000

BIF_COMMAND_11 RW 0

Name BIF_COMMAND_11

00000F20

14

13

0

0

0

0

0

0

0

0

0

6

5

4

3

2

1

0

0

0

0

0

Description Command queue 11

BIF_CON12 15

BIF Control Register 12 12

Name Type Reset Bit(s) 10:0

6

BIF_COMMAND_9

00000F1C

Bit

0000

7

Description Command queue 8

Name Type Reset

Bit(s) 10:0

8

RW 0

Bit

Bit(s) 10:0

9

BIF_COMMAND_8

00000F1A

Bit(s) 10:0

10

11

10

9

8

7

0000

BIF_COMMAND_12 RW 0

Name BIF_COMMAND_12

MediaTek Proprietary and Confidential.

0

0

0

0

0

0

Description Command queue 12

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 179 of 1067

MT6359 PMIC Datasheet Confidential A 00000F22

BIF_CON13 15

Bit

14

13

BIF Control Register 13 12

11

Name Type Reset Bit(s) 10:0

Name BIF_COMMAND_13

BIF_CON14 15

14

13

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

11

10

9

8

7

6

5

4

3

2

1

0

0

0000

RW

Name BIF_COMMAND_14

14

13

11

10

1

0

0

0

14

0

13

0

0

0

0

0

8

7

6

5

4

3

2

1

3

2

1

4000

BIF Control Register 16 12

11

10

9

8

7

1431 6

5

BIF_LOGIC_1_SET

RW

RW

0

BIF_LOGIC_1_SET

0

0

BIF_STOP_SET

Name BIF_STOP_SET

MediaTek Proprietary and Confidential.

0

Description Total transfer number in command queue Command type 2'b00: Write 2'b01: Read data 2'b10: Read response

BIF_CON16 15

9

0

Name BIF_TRASFER_NUM BIF_COMMAND_TYPE

00000F28

0

BIF_COMMAN D_TYPE RW

RW 0

0

BIF Control Register 15 12

BIF_TRASFER_NUM

Type Reset

0

Description Command queue 14

BIF_CON15 15

Name

8:4

5

BIF Control Register 14 12

0

Bit

Bit(s) 15:10

0000 6

BIF_COMMAND_14

00000F26

Name Type Reset

7

Description Command queue 13

Name Type Reset

Bit

8

RW 0

Bit

Bit(s) 15:12 9:8

9

BIF_COMMAND_13

00000F24

Bit(s) 10:0

10

1

0

1

0

0

0

4

0

BIF_LOGIC_0_SET RW

1

1

0

0

0

1

Description Sets up stop signal spec 6'd0: 0T 6'd1: 1T 6'd2: 2T 6'dN: NT Sets up logic '1' period spec 5'd0: 0T 5'd1: 1T 5'd2: 2T

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 180 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 3:0

Name

Description 5'dN: NT Sets up logic '0' period spec 4'd0: 0T 4'd1: 1T 4'd2: 2T 4'dN: NT

BIF_LOGIC_0_SET

00000F2A

BIF_CON17 15

Bit

14

BIF Control Register 17

13

12

Name

BIF_READ_EXPECT_NUM

Type Reset

RW

Bit(s) 15:12

4

0

0

10

7

1010 6

5

4

3

2

1

3

2

1

Description Expects the number of read back data 1'b0: 0 1'b1: 1 data package No function 1'b0: Disable 1'b1: Enable

BIF Control Register 18

13

12

11

10

9

8

7

0000 6

5

4

Type Reset

0

Name BIF_TRASACT_TRIGGER

00000F2E Bit

14

13

BIF Control Register 19 12

11

10

9

8

7

0000 6

5

4

3

BIF_RE SPONS E RO

Type Reset

3:0

Description Trigger signal 1'b1: Trigger BIF module

BIF_CON19 15

Name

Bit(s) 12

0 BIF_TR ASACT _TRIGG ER RW

Name

Bit(s) 0

0

1

BIF_CON18 14

8

1

BIF_DEBOUNCE_EN

15

9

BIF_DE BOUNC E_EN RW

Name BIF_READ_EXPECT_NUM

00000F2C Bit

0

11

BIF_DATA_NUM

MediaTek Proprietary and Confidential.

1

0

BIF_DATA_NUM RO

0

Name BIF_RESPONSE

2

0

0

0

0

Description Response result 1'b1: Positive response 1'b0: Negative response Number of read back data

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 181 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00000F30

BIF_CON20 15

Bit

Description

14

13

BIF Control Register 20 12

11

10

9

BIF_ER Name R_0 RO Type

Reset Bit(s) 15

8 7:0

1

Name BIF_ERR_0

14

Bit(s) 15

8 7:0

13

12

11

10

9

Bit

Bit(s) 15

8 7:0

0

Name BIF_ERR_2

BIF_ACK_2 BIF_DATA_2

MediaTek Proprietary and Confidential.

1

0

0

0

0

RO 0

0

0

0

0

7

0100 6

5

4

3

2

1

0

0

BIF_DATA_1 RO 0

0

0

0

0

0

0

6

5

4

3

2

1

0

0

0

0

Read back data

BIF_CON22 14

2

Description Error happens or not 1'b1: Error exists. 1'b0: No error

BIF_ACK_1 BIF_DATA_1

BIF_ER Name R_2 RO Type

Reset

8

1

Name BIF_ERR_1

15

3

BIF_DATA_0

BIF_AC K_1 RO

0

00000F34

4

BIF Control Register 21

BIF_ER Name R_1 RO Type

Reset

5

Read back data

BIF_CON21 15

0100 6

Description Error happens or not 1'b1: Error exists. 1'b0: No error

BIF_ACK_0 BIF_DATA_0

Bit

7

BIF_AC K_0 RO

0

00000F32

8

13

BIF Control Register 22 12

11

10

9

8

7

0100

BIF_AC K_2 RO 1

BIF_DATA_2 RO 0

0

0

0

0

Description Error happens or not 1'b1: Error exists. 1'b0: No error Read back data

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 182 of 1067

MT6359 PMIC Datasheet Confidential A 00000F36

BIF_CON23 15

Bit

14

13

BIF Control Register 23 12

11

10

9

BIF_ER Name R_3 RO Type

Reset Bit(s) 15

8 7:0

1

Name BIF_ERR_3

14

Bit(s) 15

8 7:0

13

12

11

10

9

13

Bit(s) 15

8 7:0

11

10

9

Bit

0

0

0

MediaTek Proprietary and Confidential.

0

0

0

7

0100 6

5

4

3

2

1

0

0

BIF_DATA_4 RO 0

0

0

0

0

0

0

7

6

5

4

3

2

1

0

0

0100 BIF_DATA_5 RO

0

0

0

0

0

0

0

6

5

4

3

2

1

0

0

0

0

Read back data

BIF_CON26 14

0

Description Error happens or not 1'b1: Error exists. 1'b0: No error

BIF_ACK_5 BIF_DATA_5

BIF_ER Name R_6 RO Type

Reset

8

1

Name BIF_ERR_5

15

0

RO 0

BIF_AC K_5 RO

0

00000F3C

0

BIF Control Register 25 12

BIF_ER Name R_5 RO Type

Reset

1

Read back data

BIF_CON25 14

2

Description Error happens or not 1'b1: Error exists. 1'b0: No error

BIF_ACK_4 BIF_DATA_4

15

8

1

Name BIF_ERR_4

Bit

3

BIF_DATA_3

BIF_AC K_4 RO

0

00000F3A

4

BIF Control Register 24

BIF_ER Name R_4 RO Type

Reset

5

Read back data

BIF_CON24 15

0100 6

Description Error happens or not 1'b1: Error exists. 1'b0: No error

BIF_ACK_3 BIF_DATA_3

Bit

7

BIF_AC K_3 RO

0

00000F38

8

13

BIF Control Register 26 12

11

10

9

8

7

0100

BIF_AC K_6 RO 1

BIF_DATA_6 RO 0

0

0

0

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

0

Page 183 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 15

Name BIF_ERR_6

8 7:0

BIF_ACK_6 BIF_DATA_6

00000F3E

Type Reset Bit(s) 15

8 7:0

Read back data

BIF_CON27 15

Bit Name

Description Error happens or not 1'b1: Error exists. 1'b0: No error

14

13

BIF Control Register 27 12

11

10

9

BIF_ER R_7 RO

BIF_AC K_7 RO

0

1

Name BIF_ERR_7

14

13

8 7:0

11

10

9

Bit

Name BIF_ERR_8

Reset Bit(s) 15

8 7:0

0

Name BIF_ERR_9

BIF_ACK_9 BIF_DATA_9

MediaTek Proprietary and Confidential.

2

1

0

0

RO 0

0

0

0

0

0

0

7

6

5

4

3

2

1

0

0

0

0

0100 BIF_DATA_8 RO

0

0

0

0

0

Read back data

BIF_CON29 14

3

Description Error happens or not 1'b1: Error exists. 1'b0: No error

BIF_ACK_8 BIF_DATA_8

15

8

1

BIF_ER Name R_9 RO Type

4

BIF_DATA_7

BIF_AC K_8 RO

0

00000F42

5

BIF Control Register 28 12

BIF_ER Name R_8 RO Type

Reset

0100 6

Read back data

BIF_CON28 15

Bit

7

Description Error happens or not 1'b1: Error exists. 1'b0: No error

BIF_ACK_7 BIF_DATA_7

00000F40

Bit(s) 15

8

13

BIF Control Register 29 12

11

10

9

8

7

0100 6

5

BIF_AC K_9 RO 1

4

3

2

1

0

0

0

0

BIF_DATA_9 RO 0

0

0

0

0

Description Error happens or not 1'b1: Error exists. 1'b0: No error Read back data

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 184 of 1067

MT6359 PMIC Datasheet Confidential A 00000F46

BIF_CON31 15

Bit

14

13

BIF Control Register 31 12

11

10

9

8

7

0000 6

5

4

3

2

BIF_BU BIF_TO BIF_BA BIF_TI BIF_IR Name S_STAT TAL_V T_UND MEOUT Q US ALID ET RO RO RO RO RO Type

Reset

0

0

0

0

Bit(s) 15

Name BIF_BUS_STATUS

14

BIF_TOTAL_VALID

13

BIF_BAT_UNDET

12

BIF_TIMEOUT

11

BIF_IRQ

1

BIF_IRQ_CLR

0

BIF_BACK_NORMAL

00000F48 Bit

14

13

0

0

Bit(s) 15 4:0

BIF Control Register 32 12

11

10

9

8

7

0010 6

5

4

3

2

1

0

BIF_POWER_UP_COUNT RW

0

1

Name BIF_POWER_UP BIF_POWER_UP_COUNT

MediaTek Proprietary and Confidential.

0

Description Busy: BIF is still in action 1'b0: Complete 1'b1: Busy Error happens or not in all read data 1'b1: Error exists (for all data) 1'b0: No error Battery status 1'b0: Battery exists 1'b1: Battery undetected Timeout status 1'b1: Time out BIF interrupt status Because this register is cleared by the hardware, the interrupt edgesensitive scheme should be adopted for this design. 1'b1: Interrupt issue Clears BIF interrupt status When BIF interrupt is asserted, IRQ_CLR must be set to 1 to clear the interrupt status. Finishes interrupt mode 1'b1: Abort interrupt mode

BIF_PO Name WER_U P RW Type

Reset

0

BIF_BA BIF_IR CK_NO Q_CLR RMAL RW RW

BIF_CON32 15

1

0

0

0

0

Description Powers up trigger 1'b1: Power up slave device Powers up counter setting 5'd0: 0 5'd1: 1T 5'd2: 2T 5'dN: NT

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 185 of 1067

MT6359 PMIC Datasheet Confidential A 00000F50

BIF_CON36 15

Bit

14

13

BIF Control Register 36 12

11

10

9

8

0000

7

6

5

4

3

2

1

0

RG_BA RG_BA TON_H TON_H Name T_EN_ T_EN_P DLY_TI RE ME RW RW Type

Reset Bit(s) 15

14

0

Name RG_BATON_HT_EN_DLY_TIME

BIF_CON37 15

Bit Name Type Reset

0

14

13

0

BIF Control Register 37 12

0

0

11

0

9

6

5

4

3

2

1

0

0

BIF_TIMEOUT_SET RW 0 0 0 0

0

0

1

0

1

1

14

13

7

Description Sets up timeout spec 16'd0: 0T 16'd1: 1T 16'd2: 2T 16'dN: NT

BIF_CON38 15

8

BIF Control Register 38 12

11

10

9

8

7

BIF_RX Name _DEG_ EN RW Type

Reset

1

Bit(s) 15

Name BIF_RX_DEG_EN

10:0

BIF_RX_DEG_WND

MediaTek Proprietary and Confidential.

000B

10

Name BIF_TIMEOUT_SET

00000F54 Bit

Description Not used 1'b0: 6T 1'b1: 12T Not used 1'b0: Disable 1'b1: Enable

RG_BATON_HT_EN_PRE

00000F52

Bit(s) 15:0

0

8031 6

5

4

3

2

1

0

0

0

0

1

BIF_RX_DEG_WND RW 0

0

0

0

0

1

1

Description Enables deglitch function 1'b0: Bypass 1'b1: Enable HW deglitch function Filter window 10'd0: 1T 10'd1: 2T 10'd2: 3T 10'dN: (N + 1)T

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 186 of 1067

MT6359 PMIC Datasheet Confidential A 00000F92

HK_TOP_INT_CON0 15

Bit

14

13

12

HK_TOP_INT_CON0 11

10

Type Reset

0

Bit(s) 9

Name RG_INT_EN_NAG_C_DLTV

8

RG_INT_EN_AUXADC_IMP

7

RG_INT_EN_THR_L

6

RG_INT_EN_THR_H

5

RG_INT_EN_BAT_TEMP_L

4

RG_INT_EN_BAT_TEMP_H

3

RG_INT_EN_BAT2_L

2

RG_INT_EN_BAT2_H

1

RG_INT_EN_BAT_L

0

RG_INT_EN_BAT_H

00000F94

Bit(s) 15:0

8

7

0000 6

5

4

3

2

1

0

RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT _EN_N _EN_A _EN_B _EN_B _EN_T _EN_T _EN_B _EN_B _EN_B _EN_B AG_C_ UXADC AT_TE AT_TE HR_L HR_H AT2_L AT2_H AT_L AT_H DLTV _IMP MP_L MP_H RW RW RW RW RW RW RW RW RW RW

Name

Bit Name Type Reset

9

0

14

0

13

12

0

0

Name HK_INT_CON0_SET

MediaTek Proprietary and Confidential.

0

0

0

0

0

0

0

0

Description Enables NAG_C_DLTV interrupt 0: Not issue interrupt 1: Issue interrupt Enables AUXADC_IMP interrupt 0: Not issue interrupt 1: Issue interrupt Enables THR_L interrupt 0: Not issue interrupt 1: Issue interrupt Enables THR_H interrupt 0: Not issue interrupt 1: Issue interrupt Enables BAT_TEMP_L interrupt 0: Not issue interrupt 1: Issue interrupt Enables BAT_TEMP_H interrupt 0: Not issue interrupt 1: Issue interrupt Enables BAT2_L interrupt 0: Not issue interrupt 1: Issue interrupt Enables BAT2_H interrupt 0: Not issue interrupt 1: Issue interrupt Enables BAT_L interrupt 0: Not issue interrupt 1: Issue interrupt Enables BAT_H interrupt 0: Not issue interrupt 1: Issue interrupt

HK_TOP_INT_CON0_SET 15

0

11

0

HK_TOP_INT_CON0_SET 8

7

0000

10

9

6

5

4

3

2

1

0

0

HK_INT_CON0_SET W1 0 0 0 0

0

0

0

0

0

0

Description 0: Not set 1: Set

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 187 of 1067

MT6359 PMIC Datasheet Confidential A 00000F96

Bit(s) 15:0

HK_TOP_INT_CON0_CLR 15

Bit Name Type Reset

0

0

13

12

0

0

11

0

HK_TOP_INT_CON0_CLR 9

6

5

4

3

2

1

0

0

HK_INT_CON0_CLR W1 0 0 0 0

0

0

0

0

0

0

14

13

7

5

4

3

2

1

Description 0: Not clear 1: Clear

HK_TOP_INT_MASK_CON0 15

8

0000

10

Name HK_INT_CON0_CLR

00000F98 Bit

14

12

11

HK_TOP_INT_MASK_CON0 10

9

8

7

6

0000 0

RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT _MASK RG_INT RG_INT _MASK _MASK _MASK _MASK _MASK _MASK _MASK _AUXA _MASK _MASK _NAG_ _THR_ _BAT_T _BAT_T _BAT2_ _BAT2_ _BAT_ DC_IM _THR_L _BAT_L C_DLTV H EMP_L EMP_H L H H P RW RW RW RW RW RW RW RW RW RW

Name Type Reset

0

Bit(s) 9

Name RG_INT_MASK_NAG_C_DLTV

8

RG_INT_MASK_AUXADC_IMP

7

RG_INT_MASK_THR_L

6

RG_INT_MASK_THR_H

5

RG_INT_MASK_BAT_TEMP_L

4

RG_INT_MASK_BAT_TEMP_H

3

RG_INT_MASK_BAT2_L

2

RG_INT_MASK_BAT2_H

1

RG_INT_MASK_BAT_L

0

RG_INT_MASK_BAT_H

MediaTek Proprietary and Confidential.

0

0

0

0

0

0

0

0

0

Description Masks NAG_C_DLTV interrupt status 0: Unmask interrupt status 1: Mask interrupt status Masks AUXADC_IMP interrupt status 0: Unmask interrupt status 1: Mask interrupt status Masks THR_L interrupt status 0: Unmask interrupt status 1: Mask interrupt status Masks THR_H interrupt status 0: Unmask interrupt status 1: Mask interrupt status Masks BAT_TEMP_L interrupt status 0: Unmask interrupt status 1: Mask interrupt status Masks BAT_TEMP_H interrupt status 0: Unmask interrupt status 1: Mask interrupt status Masks BAT2_L interrupt status 0: Unmask interrupt status 1: Mask interrupt status Masks BAT2_H interrupt status 0: Unmask interrupt status 1: Mask interrupt status Masks BAT_L interrupt status 0: Unmask interrupt status 1: Mask interrupt status Masks BAT_H interrupt status 0: Unmask interrupt status 1: Mask interrupt status

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 188 of 1067

MT6359 PMIC Datasheet Confidential A 00000F9A 15

Bit Name Type Reset Bit(s) 15:0

HK_TOP_INT_MASK_CON0_S HK_TOP_INT_MASK_CON0_SET ET

0

Bit(s) 15:0

12

0

11

0

0

10

9

8

7

6

5

4

3

2

1

0

0

HK_INT_MASK_CON0_SET W1 0 0 0 0

0

0

0

0

0

0

Description 0: Not set 1: Set

HK_TOP_INT_MASK_CON0_C HK_TOP_INT_MASK_CON0_CLR LR 15

0

14

0

13

12

0

11

0

0

9

6

5

4

3

2

1

0

0

HK_INT_MASK_CON0_CLR W1 0 0 0 0

0

0

0

0

0

0

14

13

12

7

5

4

3

2

1

Description 0: Not clear 1: Clear

HK_TOP_INT_STATUS0 15

8

0000

10

Name HK_INT_MASK_CON0_CLR

00000F9E Bit

0

13

Name HK_INT_MASK_CON0_SET

00000F9C Bit Name Type Reset

14

0000

11

HK_TOP_INT_STATUS0 10

9

8

7

0000 6

0

RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT _STAT _STAT _STAT _STAT _STAT _STAT _STAT _STAT _STAT _STAT US_NA US_AU US_BA US_BA US_TH US_TH US_BA US_BA US_BA US_BA G_C_D XADC_I T_TEM T_TEM R_L R_H T2_L T2_H T_L T_H LTV MP P_L P_H W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C

Name

Type Reset

0

Bit(s) 9

Name RG_INT_STATUS_NAG_C_DLTV

8

RG_INT_STATUS_AUXADC_IMP

7

RG_INT_STATUS_THR_L

6

RG_INT_STATUS_THR_H

5

RG_INT_STATUS_BAT_TEMP_L

4

RG_INT_STATUS_BAT_TEMP_H

MediaTek Proprietary and Confidential.

0

0

0

0

0

0

0

0

0

Description NAG_C_DLTV interrupt status 0: No interrupt issued 1: Interrupt issued AUXADC_IMP interrupt status 0: No interrupt issued 1: Interrupt issued THR_L interrupt status 0: No interrupt issued 1: Interrupt issued THR_H interrupt status 0: No interrupt issued 1: Interrupt issued BAT_TEMP_L interrupt status 0: No interrupt issued 1: Interrupt issued BAT_TEMP_H interrupt status 0: No interrupt issued 1: Interrupt issued

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 189 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 3

Name RG_INT_STATUS_BAT2_L

2

RG_INT_STATUS_BAT2_H

1

RG_INT_STATUS_BAT_L

0

RG_INT_STATUS_BAT_H

00000FA0 Bit

Description BAT2_L interrupt status 0: No interrupt issued 1: Interrupt issued BAT2_H interrupt status 0: No interrupt issued 1: Interrupt issued BAT_L interrupt status 0: No interrupt issued 1: Interrupt issued BAT_H interrupt status 0: No interrupt issued 1: Interrupt issued

HK_TOP_INT_RAW_STATUS0 HK_TOP_INT_RAW_STATUS0 15

14

13

12

11

10

9

8

7

6

0000 5

4

3

2

1

0

RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT _RAW_ RG_INT RG_INT _RAW_ _RAW_ _RAW_ _RAW_ _RAW_ _RAW_ _RAW_ STATUS _RAW_ _RAW_ STATUS STATUS STATUS STATUS STATUS STATUS STATU _AUXA STATUS STATUS _NAG_ _THR_ _BAT_T _BAT_T _BAT2_ _BAT2_ S_BAT_ DC_IM _THR_L _BAT_L C_DLTV H EMP_L EMP_H L H H P RO RO RO RO RO RO RO RO RO RO

Name

Type Reset

0

Bit(s) 9

Name RG_INT_RAW_STATUS_NAG_C_DLTV

8

RG_INT_RAW_STATUS_AUXADC_IMP

7

RG_INT_RAW_STATUS_THR_L

6

RG_INT_RAW_STATUS_THR_H

5

RG_INT_RAW_STATUS_BAT_TEMP_L

4

RG_INT_RAW_STATUS_BAT_TEMP_H

3

RG_INT_RAW_STATUS_BAT2_L

2

RG_INT_RAW_STATUS_BAT2_H

1

RG_INT_RAW_STATUS_BAT_L

0

RG_INT_RAW_STATUS_BAT_H

MediaTek Proprietary and Confidential.

0

0

0

0

0

0

0

0

0

Description NAG_C_DLTV raw interrupt status 0: No interrupt issued 1: Interrupt issued AUXADC_IMP raw interrupt status 0: No interrupt issued 1: Interrupt issued THR_L raw interrupt status 0: No interrupt issued 1: Interrupt issued THR_H raw interrupt status 0: No interrupt issued 1: Interrupt issued BAT_TEMP_L raw interrupt status 0: No interrupt issued 1: Interrupt issued BAT_TEMP_H raw interrupt status 0: No interrupt issued 1: Interrupt issued BAT2_L raw interrupt status 0: No interrupt issued 1: Interrupt issued BAT2_H raw interrupt status 0: No interrupt issued 1: Interrupt issued BAT_L raw interrupt status 0: No interrupt issued 1: Interrupt issued BAT_H raw interrupt status

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 190 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001088

AUXADC_ADC0 15

Bit

Description 0: No interrupt issued 1: Interrupt issued

AUXAD C_ADC Name _RDY_ CH0 RO Type 0 Reset

14

13

12

0

0

0

Name AUXADC_ADC_RDY_CH0

14:0

AUXADC_ADC_OUT_CH0

AUXAD C_ADC Name _RDY_ CH1 RO Type 0 Reset

14

13

12

0

0

0

Name AUXADC_ADC_RDY_CH1

14:0

AUXADC_ADC_OUT_CH1

0000108C

Name Type Reset

0

8

7

0000

6

5

4

3

2

1

0

0

0

RO 0

0

0

0

0

0

0

0

5

4

3

2

1

0

0

0

0

0

0

0

4

3

2

1

0

0

0

0

0

Description AUXADC channel 0 output data ready 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 0 output data

AUXADC ADC Register 1 11

10

0

0

9

8

7

0000

6

14

13

12

0

0

0

AUXADC ADC Register 2 11

10

9

8

AUXAD C_ADC _RDY_ CH2 RO

7

0000

6

5

AUXADC_ADC_OUT_CH2 RO

0

0

Bit(s) 15

Name AUXADC_ADC_RDY_CH2

11:0

AUXADC_ADC_OUT_CH2

MediaTek Proprietary and Confidential.

RO 0

Description AUXADC channel 1 output data ready 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 1 output data

AUXADC_ADC2 15

9

AUXADC_ADC_OUT_CH1

Bit(s) 15

Bit

0

AUXADC_ADC1 15

Bit

10

AUXADC_ADC_OUT_CH0

Bit(s) 15

0000108A

AUXADC ADC Register 0 11

0

0

0

0

0

0

0

Description AUXADC channel 2 output data ready 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 2 output data

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 191 of 1067

MT6359 PMIC Datasheet Confidential A 0000108E

AUXADC_ADC3 15

Bit

14

13

12

AUXADC ADC Register 3 11

10

9

8

AUXAD C_ADC Name _RDY_ CH3 RO Type

Reset

Name AUXADC_ADC_RDY_CH3

11:0

AUXADC_ADC_OUT_CH3

0

14

13

12

0

0

11

0

Name AUXADC_ADC_RDY_CH4

11:0

AUXADC_ADC_OUT_CH4

Bit Name Type Reset

1

0

0

0

0

0

0

0

0

0

10

9

8

7

0000

6

5

4

3

2

1

0

0

0

0

0

0

4

3

2

1

0

0

0

0

0

RO

Bit(s) 15

0

14

13

12

0

0

0

0

AUXADC ADC Register 5 11

10

9

8

AUXAD C_ADC _RDY_ CH5 RO

7

0000

6

5

AUXADC_ADC_OUT_CH5 RO

0

0

Bit(s) 15

Name AUXADC_ADC_RDY_CH5

11:0

AUXADC_ADC_OUT_CH5

MediaTek Proprietary and Confidential.

0

Description AUXADC channel 4 output data ready 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 4 output data

AUXADC_ADC5 15

2

AUXADC_ADC_OUT_CH4

0

00001092

3

AUXADC ADC Register 4

AUXAD C_ADC Name _RDY_ CH4 RO Type

Reset

4

Description AUXADC channel 3 output data ready 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 3 output data

AUXADC_ADC4 15

5

RO 0

Bit(s) 15

Bit

0000

6

AUXADC_ADC_OUT_CH3

0

00001090

7

0

0

0

0

0

0

0

Description AUXADC channel 5 output data ready 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 5 output data

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 192 of 1067

MT6359 PMIC Datasheet Confidential A 00001094

AUXADC_ADC6 15

Bit

14

13

12

AUXADC ADC Register 6 11

10

9

8

AUXAD C_ADC Name _RDY_ CH6 RO Type

Reset

Name AUXADC_ADC_RDY_CH6

11:0

AUXADC_ADC_OUT_CH6

15

14

13

12

0

0

0

Name AUXADC_ADC_RDY_CH7

14:0

AUXADC_ADC_OUT_CH7

00001098

0

0

2

1

0

0

0

0

0

0

0

0

0

AUXADC ADC Register 7 11

10

9

8

0

0

14

13

12

0

0

7

0000

6

5

4

3

2

1

0

0

0

0

0

0

0

0

4

3

2

1

0

0

0

0

0

AUXADC ADC Register 8 11

10

9

8

7

0000

6

5

AUXADC_ADC_OUT_CH8 RO

0

0

Bit(s) 15

Name AUXADC_ADC_RDY_CH8

11:0

AUXADC_ADC_OUT_CH8

MediaTek Proprietary and Confidential.

RO 0

Description AUXADC channel 7 output data ready 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 7 output data

AUXAD C_ADC Name _RDY_ CH8 RO Type

Reset

3

Description AUXADC channel 6 output data ready 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 6 output data

AUXADC_ADC8 15

4

AUXADC_ADC_OUT_CH7

Bit(s) 15

Bit

0

AUXADC_ADC7

AUXAD C_ADC Name _RDY_ CH7 RO Type 0 Reset

5

RO 0

Bit(s) 15

Bit

0000

6

AUXADC_ADC_OUT_CH6

0

00001096

7

0

0

0

0

0

0

0

Description AUXADC channel 8 output data ready 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 8 output data

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 193 of 1067

MT6359 PMIC Datasheet Confidential A 0000109A

AUXADC_ADC9 15

Bit

AUXAD C_ADC Name _RDY_ CH9 RO Type 0 Reset

14

13

12

0

0

0

Name AUXADC_ADC_RDY_CH9

14:0

AUXADC_ADC_OUT_CH9

AUXAD C_ADC Name _RDY_ CH10 RO Type 0 Reset

14

13

12

0

0

0

Name AUXADC_ADC_RDY_CH10

14:0

AUXADC_ADC_OUT_CH10

0000109E

0

8

0

0

0000

6

5

4

3

2

1

0

RO 0

0

0

0

0

0

0

0

5

4

3

2

1

0

0

0

0

0

0

0

4

3

2

1

0

0

0

0

0

AUXADC ADC Register 10 11

10

9

8

0

0

14

13

12

0

0

7

0000

6

0

AUXADC ADC Register 11 11

10

9

8

7

0000

6

5

AUXADC_ADC_OUT_CH11 RO

0

0

Bit(s) 15

Name AUXADC_ADC_RDY_CH11

11:0

AUXADC_ADC_OUT_CH11

MediaTek Proprietary and Confidential.

RO 0

Description AUXADC channel 10 output data ready 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 10 output data

AUXAD C_ADC Name _RDY_ CH11 RO Type

Reset

7

Description AUXADC channel 9 output data ready 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 9 output data

AUXADC_ADC11 15

9

AUXADC_ADC_OUT_CH10

Bit(s) 15

Bit

0

AUXADC_ADC10 15

Bit

10

AUXADC_ADC_OUT_CH9

Bit(s) 15

0000109C

AUXADC ADC Register 9 11

0

0

0

0

0

0

0

Description AUXADC channel 11 output data ready (used for BIF) 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 11 output data (used for BIF)

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 194 of 1067

MT6359 PMIC Datasheet Confidential A 000010A0

AUXADC_ADC12 15

Bit

AUXAD C_ADC Name _RDY_ CH12_ 15 RO Type 0 Reset

14

13

12

0

0

0

Name AUXADC_ADC_RDY_CH12_15

14:0

AUXADC_ADC_OUT_CH12_15

0

AUXAD C_ADC Name _RDY_ CH7_B Y_GPS RO Type 0 Reset

14

13

12

11

0

0

0

0

AUXADC_ADC_OUT_CH7_BY_GPS

Bit(s) 15

10

0

6

0000 5

4

3

2

1

0

0

0

RO 0

0

0

0

0

0

0

0

9

8

7

6

0000 5

4

3

2

1

0

14

13

12

0

0

RO 0

0

0

0

0

0

0

0

Description AUXADC channel 7 output data ready (requested by GPS) 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 7 output data (requested by GPS)

AUXADC_ADC16

AUXAD C_ADC Name _RDY_ CH7_B Y_MD RO Type 0 Reset

7

AUXADC_ADC_OUT_CH7_BY_GPS

14:0

15

8

AUXADC ADC Register 15

Name AUXADC_ADC_RDY_CH7_BY_GPS

000010A4

9

Description AUXADC channel 12_15 output data ready 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 12_15 output data

Bit(s) 15

Bit

0

AUXADC_ADC15 15

Bit

10

AUXADC_ADC_OUT_CH12_15

Bit(s) 15

000010A2

AUXADC ADC Register 12 11

AUXADC ADC Register 16 11

10

9

8

7

6

0000 5

4

3

2

1

0

0

0

0

0

0

AUXADC_ADC_OUT_CH7_BY_MD

0

0

0

0

Name AUXADC_ADC_RDY_CH7_BY_MD

0

0

0

RO 0

0

0

Description AUXADC channel 7 output data ready (requested by MD) 0: AUXADC data proceeding 1: AUXADC data ready

ut data (requested by MD) 14:0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 195 of 1067

MT6359 PMIC Datasheet Confidential A 000010A6

AUXADC_ADC17 15

Bit

AUXAD C_ADC Name _RDY_ CH7_B Y_AP RO Type 0 Reset

14

13

12

AUXADC ADC Register 17 11

0

0

0

0

Name AUXADC_ADC_RDY_CH7_BY_AP

14:0

AUXADC_ADC_OUT_CH7_BY_AP

0

8

14

13

12

0

0

11

Name AUXADC_ADC_RDY_CH4_BY_MD

11:0

AUXADC_ADC_OUT_CH4_BY_MD

10

0

15

3

2

1

0

RO 0

0

0

0

0

0

0

0

9

8

7

0000

6

5

4

3

2

1

0

14

13

12

0

0

0

0

0

0

0

0

0

0

Description AUXADC channel 4 output data ready (requested by MD) 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 4 output data (requested by MD)

AUXADC_ADC19

AUXAD C_ADC _RDY_ Name PWRO N_PCH R RO Type 0 Reset

4

RO 0

Bit(s) 15

Bit

5

AUXADC_ADC_OUT_CH4_BY_MD

0

000010AA

0000

6

AUXADC ADC Register 18

AUXAD C_ADC Name _RDY_ CH4_B Y_MD RO Type

Reset

7

Description AUXADC channel 7 output data ready (requested by AP) 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 7 output data (requested by AP)

AUXADC_ADC18 15

Bit

9

AUXADC_ADC_OUT_CH7_BY_AP

Bit(s) 15

000010A8

10

AUXADC ADC Register 19 11

10

9

8

7

6

0000 5

4

3

2

1

0

0

0

0

0

0

AUXADC_ADC_OUT_PWRON_PCHR

0

0

0

0

Bit(s) 15

Name AUXADC_ADC_RDY_PWRON_PCHR

14:0

AUXADC_ADC_OUT_PWRON_PCHR

MediaTek Proprietary and Confidential.

0

0

0

RO 0

0

0

Description AUXADC channel 0 power-on ZCV output data ready 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 0 power-on ZCV output data

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 196 of 1067

MT6359 PMIC Datasheet Confidential A 000010AC

AUXADC_ADC20 15

Bit

AUXAD C_ADC _RDY_ Name WAKE UP_PC HR RO Type 0 Reset

14

13

12

AUXADC ADC Register 20 11

0

0

0

0

Name AUXADC_ADC_RDY_WAKEUP_PCHR

14:0

AUXADC_ADC_OUT_WAKEUP_PCHR

AUXAD C_ADC Name _RDY_ CH0_B Y_MD RO Type 0 Reset

14

13

12

0

0

0

0

14:0

AUXADC_ADC_OUT_CH0_BY_MD

15

Bit(s) 15

6

0000 5

4

3

2

1

0

0

0

RO 0

0

0

0

0

0

0

0

Description AUXADC channel 0 wakeup ZCV output data ready 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 0 wakeup ZCV output data

10

0

9

8

7

6

0000 5

4

3

2

1

0

14

13

12

0

0

RO 0

0

0

0

0

0

0

0

Description AUXADC channel 0 output data ready (requested by MD) 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 0 output data (requested by MD)

AUXADC_ADC22

AUXAD C_ADC Name _RDY_ CH0_B Y_AP RO Type 0 Reset

7

AUXADC_ADC_OUT_CH0_BY_MD

Name AUXADC_ADC_RDY_CH0_BY_MD

000010B0

8

AUXADC ADC Register 21 11

Bit(s) 15

Bit

0

AUXADC_ADC21 15

Bit

9

AUXADC_ADC_OUT_WAKEUP_PCHR

Bit(s) 15

000010AE

10

AUXADC ADC Register 22 11

10

9

8

7

6

0000 5

4

3

2

1

0

0

0

0

0

0

AUXADC_ADC_OUT_CH0_BY_AP

0

0

0

0

Name AUXADC_ADC_RDY_CH0_BY_AP

0

0

0

RO 0

0

0

Description AUXADC channel 0 output data ready (requested by AP) 0: AUXADC data proceeding 1: AUXADC data ready

ut data (requested by AP) 14:0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 197 of 1067

MT6359 PMIC Datasheet Confidential A 000010B2

AUXADC_ADC23 15

Bit

AUXAD C_ADC Name _RDY_ CH1_B Y_MD RO Type 0 Reset

14

13

12

AUXADC ADC Register 23 11

0

0

0

0

Name AUXADC_ADC_RDY_CH1_BY_MD

14:0

AUXADC_ADC_OUT_CH1_BY_MD

AUXAD C_ADC Name _RDY_ CH1_B Y_AP RO Type 0 Reset

14

13

12

11

0

0

0

0

14:0

AUXADC_ADC_OUT_CH1_BY_AP

AUXAD C_ADC Name _RDY_ FGADC _PCHR RO Type 0 Reset

Bit(s) 15

6

0000 5

4

3

2

1

0

0

0

RO 0

0

0

0

0

0

0

0

Description AUXADC channel 1 output data ready (requested by MD) 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 1 output data (requested by MD)

10

0

9

8

7

6

0000 5

4

3

2

1

0

14

13

12

0

0

RO 0

0

0

0

0

0

0

0

Description AUXADC channel 1 output data ready (requested by AP) 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 1 output data (requested by AP)

AUXADC_ADC26 15

7

AUXADC_ADC_OUT_CH1_BY_AP

Name AUXADC_ADC_RDY_CH1_BY_AP

000010B6

8

AUXADC ADC Register 24

Bit(s) 15

Bit

0

AUXADC_ADC24 15

Bit

9

AUXADC_ADC_OUT_CH1_BY_MD

Bit(s) 15

000010B4

10

AUXADC ADC Register 26 11

10

9

8

7

6

0000 5

4

3

2

1

0

0

0

0

0

0

AUXADC_ADC_OUT_FGADC_PCHR

0

0

0

0

Name AUXADC_ADC_RDY_FGADC_PCHR

0

0

0

RO 0

0

0

Description AUXADC channel 0 ZCV output data ready (requested by FGADC) 0: AUXADC data proceeding 1: AUXADC data ready

output data (requested14:0 by FGADC)

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 198 of 1067

MT6359 PMIC Datasheet Confidential A 000010B8

AUXADC_ADC27 15

Bit

AUXAD C_ADC _RDY_ Name BAT_PL UGIN_ PCHR RO Type 0 Reset

Bit(s) 15

14:0

13

12

AUXADC ADC Register 27 11

9

8

7

6

0000 5

4

3

2

1

0

0

0

0

0

0

AUXADC_ADC_OUT_BAT_PLUGIN_PCHR

0

0

0

0

0

AUXADC_ADC30 15

Bit Name Type Reset

0

0

RO 0

0

0

14

13

12

AUXADC ADC Register 30 11

10

9

8

7

6

0000 5

4

3

2

1

0

0

0

0

0

0

0

5

4

3

2

1

0

0

0

0

0

0

AUXADC_ADC_OUT_RAW RO 0

0

0

0

0

Name AUXADC_ADC_OUT_RAW

000010BC AUXAD C_ADC _RDY_ Name DCXO_ BY_GP S RO Type 0 Reset

14

13

12

0

0

0

0

14:0

AUXADC_ADC_OUT_DCXO_BY_GPS

10

0

0

9

8

7

6

0000

14

13

12

0

0

RO 0

0

0

Description AUXADC channel 10 DCXO output data ready (requested by GPS) 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 10 DCXO output data (requested by GPS)

AUXADC_ADC33

AUXAD C_ADC Name _RDY_ DCXO_ BY_MD RO Type 0 Reset

0

AUXADC_ADC_OUT_DCXO_BY_GPS

Name AUXADC_ADC_RDY_DCXO_BY_GPS

15

0

AUXADC ADC Register 32 11

Bit(s) 15

000010BE

0

Description AUXADC channel output raw data

AUXADC_ADC32 15

Bit

Bit

10

Name Description AUXADC_ADC_RDY_BAT_PLUGIN_PCHR AUXADC channel 0 ZCV output data ready (requested by BAT PLUGIN) 0: AUXADC data proceeding 1: AUXADC data ready AUXADC_ADC_OUT_BAT_PLUGIN_PCHR AUXADC channel 0 ZCV output data (requested by BAT PLUGIN)

000010BA

Bit(s) 14:0

14

AUXADC ADC Register 33 11

10

9

8

7

6

0000 5

4

3

2

1

0

0

0

0

0

0

AUXADC_ADC_OUT_DCXO_BY_MD

0

MediaTek Proprietary and Confidential.

0

0

0

0

0

0

RO 0

0

0

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 199 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 15

Name AUXADC_ADC_RDY_DCXO_BY_MD

14:0

AUXADC_ADC_OUT_DCXO_BY_MD

000010C0

AUXADC_ADC34 15

Bit

AUXAD C_ADC Name _RDY_ DCXO_ BY_AP RO Type 0 Reset

14

13

12

AUXADC ADC Register 34 11

0

0

0

0

Name AUXADC_ADC_RDY_DCXO_BY_AP

14:0

AUXADC_ADC_OUT_DCXO_BY_AP

000010C2

10

0

8

14

13

12

0

0

Name AUXADC_ADC_RDY_BATID

11:0

AUXADC_ADC_OUT_BATID

10

0

9

8

14

13

12

0

0

Bit(s) 15

2

1

0

RO 0

0

0

0

0

0

0

0

7

0000

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

10

9

8

7

3

2

1

0

0

0

0

0

0000

6

5

4

AUXADC_ADC_OUT_CH4_BY_THR1

RO 0

Name AUXADC_ADC_RDY_CH4_BY_THR1

MediaTek Proprietary and Confidential.

0

AUXADC ADC Register 38 11

AUXAD C_ADC _RDY_ Name CH4_B Y_THR 1 RO Type

Reset

3

Description AUXADC channel 3 BATID output data ready 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 3 BATID output data

AUXADC_ADC38 15

4

RO 0

Bit(s) 15

Bit

5

AUXADC_ADC_OUT_BATID

0

000010C4

6

AUXADC ADC Register 37 11

AUXAD C_ADC Name _RDY_ BATID RO Type

Reset

7

Description AUXADC channel 10 DCXO output data ready (requested by AP) 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 10 DCXO output data (requested by AP)

AUXADC_ADC37 15

9

0000

AUXADC_ADC_OUT_DCXO_BY_AP

Bit(s) 15

Bit

Description AUXADC channel 10 DCXO output data ready (requested by MD) 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 10 DCXO output data (requested by MD)

0

0

0

0

0

0

0

Description AUXADC channel 4 THR1 output data ready 0: AUXADC data proceeding 1: AUXADC data ready

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 200 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 11:0

Name AUXADC_ADC_OUT_CH4_BY_THR1

000010C6

AUXADC_ADC39 15

Bit

Description AUXADC channel 4 THR1 output data

14

13

12

AUXADC ADC Register 39 11

10

9

8

AUXAD C_ADC _RDY_ Name CH4_B Y_THR 2 RO Type

Reset

Name AUXADC_ADC_RDY_CH4_BY_THR2

11:0

AUXADC_ADC_OUT_CH4_BY_THR2

Bit

0

13

12

11:0

AUXADC_ADC_OUT_CH4_BY_THR3

0

10

9

0

8

0

0

0

0

0

0

0

0

0

7

3

2

1

0

0

0

0

0

3

2

1

0

0

0

0

0

0000

6

5

4

13

12

0

0

0

0

AUXADC_STA0 11

10

9

8

0000 7

6

5

4

AUXADC_ADC_BUSY_IN

RO

0

0

Bit(s) 15

Name AUXADC_ADC_BUSY_IN_WAKEUP

11:0

AUXADC_ADC_BUSY_IN

MediaTek Proprietary and Confidential.

0

Description AUXADC channel 4 THR3 output data ready 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 4 THR3 output data

AUXADC_STA0 14

0

AUXAD C_ADC Name _BUSY _IN_W AKEUP RO Type

Reset

1

RO 0

Name AUXADC_ADC_RDY_CH4_BY_THR3

15

2

AUXADC ADC Register 40 11

Bit(s) 15

Bit

3

AUXADC_ADC_OUT_CH4_BY_THR3

0

000010CA

4

Description AUXADC channel 4 THR2 output data ready 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 4 THR2 output data

AUXADC_ADC40 14

0

AUXAD C_ADC _RDY_ Name CH4_B Y_THR 3 RO Type

Reset

5

RO 0

Bit(s) 15

15

6

AUXADC_ADC_OUT_CH4_BY_THR2

0

000010C8

7

0000

0

0

0

0

0

0

0

Description ADC busy status 0: Idle 1: Busy AUXADC ADC busy status

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 201 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

000010CC Bit

Description bit[11] = CH11 ~ bit[0] = CH0 0: Idle (for each bit) 1: Busy (for each bit)

AUXADC_STA1 15

14

Bit(s) 15

13

12

11

9

7

3

2

1

AUXADC_STA1

12

11

10

9

RO

RO

RO

RO

AUXAD C_ADC _BUSY _IN_FG ADC_P CHR RO

0

0

0

0

0

AUXAD C_ADC Name _BUSY _IN_TH R_MD

Type Reset

13

AUXAD AUXAD AUXAD C_ADC C_ADC C_ADC _BUSY _BUSY _BUSY _IN_GP _IN_GP _IN_GP S S_MD S_AP

8

0000 7

6

5

4

AUXAD C_ADC _BUSY _IN_SH ARE RO 0

3

2

1

0

AUXAD AUXAD AUXAD C_ADC C_ADC C_ADC _BUSY _BUSY _BUSY _IN_DC _IN_DC _IN_DC XO_GP XO_GP XO_GP S S_MD S_AP RO RO RO 0

0

0

Name AUXADC_ADC_BUSY_IN_THR_MD

Description ADC busy status 0: Idle 1: Busy AUXADC_ADC_BUSY_IN_GPS ADC busy status 0: Idle 1: Busy AUXADC_ADC_BUSY_IN_GPS_MD ADC busy status 0: Idle 1: Busy AUXADC_ADC_BUSY_IN_GPS_AP ADC busy status 0: Idle 1: Busy AUXADC_ADC_BUSY_IN_FGADC_PCHR ADC busy status 0: Idle 1: Busy AUXADC_ADC_BUSY_IN_SHARE ADC busy status 0: Idle 1: Busy AUXADC_ADC_BUSY_IN_DCXO_GPS ADC busy status 0: Idle 1: Busy AUXADC_ADC_BUSY_IN_DCXO_GPS_ ADC busy status MD 0: Idle 1: Busy AUXADC_ADC_BUSY_IN_DCXO_GPS_ ADC busy status AP 0: Idle 1: Busy

MediaTek Proprietary and Confidential.

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Page 202 of 1067

MT6359 PMIC Datasheet Confidential A 000010CE

AUXADC_STA2 15

Bit

14

13

AUXADC_STA2

12

11

9

8

0000 7

6

5

4

Type Reset

RO

RO

RO

0

0

0

0

0

AUXADC_ADC_BUSY_IN_THR2

11

AUXADC_ADC_BUSY_IN_THR1

3

AUXADC_ADC_BUSY_IN_PWRON

2

AUXADC_ADC_BUSY_IN_BATID

0

AUXADC_ADC_BUSY_IN_BAT_PLUGI N_PCHR

AUXAD AUXAD C_ADC C_ADC _BUSY _BUSY _IN_P _IN_BA WRON TID

Description ADC busy status 0: Idle 1: Busy ADC busy status 0: Idle 1: Busy ADC busy status 0: Idle 1: Busy ADC busy status 0: Idle 1: Busy ADC busy status 0: Idle 1: Busy ADC busy status 0: Idle 1: Busy

AUXADC_NAG_10 14

0

RO

12

15

1

0

Name AUXADC_ADC_BUSY_IN_THR3

AUXAD C_ADC Name _RDY_ NAG RO Type 0 Reset

2

RO

Bit(s) 13

000011D2

3

AUXAD C_ADC _BUSY _IN_BA T_PLU GIN_PC HR RO

AUXAD AUXAD AUXAD C_ADC C_ADC C_ADC _BUSY _BUSY _BUSY _IN_TH _IN_TH _IN_TH R3 R2 R1

Name

Bit

10

13

12

AUXADC_NAG_10 11

10

9

8

7

0000 6

5

4

3

2

1

0

0

0

0

0

0

0

AUXADC_ADC_OUT_NAG

0

0

0

Bit(s) 15

Name AUXADC_ADC_RDY_NAG

14:0

AUXADC_ADC_OUT_NAG

MediaTek Proprietary and Confidential.

0

0

0

0

RO 0

0

Description AUXADC channel 0 NAG output data ready 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 0 NAG output data

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 203 of 1067

MT6359 PMIC Datasheet Confidential A 000011D4

AUXADC_NAG_11 15

Bit

14

13

12

AUXADC_NAG_11 11

10

9

8

0003

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

0

0

0

0

0

0

AUXAD C_ADC Name _BUSY _IN_N AG RO Type

Reset Bit(s) 15

0

Name AUXADC_ADC_BUSY_IN_NAG

0000120E

AUXADC_IMP3 15

Bit

Description ADC busy status 0: Idle 1: Busy

AUXAD C_ADC _RDY_I MP RO Type 0 Reset

14

13

AUXADC_IMP3

12

11

10

9

Name

0

0

0

Name AUXADC_ADC_RDY_IMP

14:0

AUXADC_ADC_OUT_IMP

Bit

0

0

15

14

13

0

0

RO 0

0

Description AUXADC channel 0 IMP/PTIM output data ready (each trigger) 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 0 IMP/PTIM output data (each trigger)

AUXADC_IMP4

AUXAD C_ADC Name _RDY_I MP_AV G RO Type 0 Reset

0000

AUXADC_ADC_OUT_IMP

Bit(s) 15

00001210

8

AUXADC_IMP4

12

11

10

9

8

0000 7

6

5

4

3

2

1

0

0

0

0

0

0

0

AUXADC_ADC_OUT_IMP_AVG

0

0

0

Bit(s) 15

Name AUXADC_ADC_RDY_IMP_AVG

14:0

AUXADC_ADC_OUT_IMP_AVG

MediaTek Proprietary and Confidential.

0

0

0

0

RO 0

0

Description AUXADC channel 0 IMP/PTIM output data ready (after average) 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 0 IMP/PTIM output data (after average)

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Page 204 of 1067

MT6359 PMIC Datasheet Confidential A 00001212

AUXADC_IMP5 15

Bit

14

13

12

AUXADC_IMP5 11

10

9

8

0003 7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

0

0

0

0

2

1

AUXAD C_ADC Name _BUSY _IN_IM P RO Type

Reset Bit(s) 15

0

Name AUXADC_ADC_BUSY_IN_IMP

00001222

Name Type Reset

AUXADC_LBAT7 15

Bit

14

13

12

AUXADC_LBAT7 11

10

9

8

AUXAD C_ADC _RDY_L BAT RO

RO

0

0

Name AUXADC_ADC_RDY_LBAT

11:0

AUXADC_ADC_OUT_LBAT

00001224

0

14

13

12

0

0

0

0

0

0

Description AUXADC channel 0 low battery output data ready 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 0 low battery output data

AUXADC_LBAT8 15

0000

AUXADC_ADC_OUT_LBAT

Bit(s) 15

Bit

Description ADC busy status 0: Idle 1: Busy

AUXADC_LBAT8 11

10

9

8

0003 7

6

5

4

3

0

AUXAD C_ADC Name _BUSY _IN_LB AT RO Type

Reset Bit(s) 15

0

Name AUXADC_ADC_BUSY_IN_LBAT

MediaTek Proprietary and Confidential.

Description ADC busy status 0: Idle 1: Busy

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Page 205 of 1067

MT6359 PMIC Datasheet Confidential A 00001236

AUXADC_BAT_TEMP_8 15

Bit

14

13

12

11

AUXADC_BAT_TEMP_8 10

9

8

AUXAD C_ADC Name _RDY_ BAT_T EMP RO Type

Reset

Name AUXADC_ADC_RDY_BAT_TEMP

11:0

AUXADC_ADC_OUT_BAT_TEMP

0

4

3

2

1

0

14

13

12

11

0

0

0

0

0

0

0

0

0

0

Description AUXADC channel 3 BAT_TEMP output data ready 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 3 BAT_TEMP output data

AUXADC_BAT_TEMP_9 15

5

RO 0

Bit(s) 15

Bit

0000 6

AUXADC_ADC_OUT_BAT_TEMP

0

00001238

7

AUXADC_BAT_TEMP_9 10

9

8

7

0003 6

5

4

3

2

1

0

6

5

4

3

2

1

0

0

0

0

0

AUXAD C_ADC _BUSY Name _IN_BA T_TEM P RO Type

Reset Bit(s) 15

0

Name AUXADC_ADC_BUSY_IN_BAT_TEMP

00001248 Bit

Description ADC busy status 0: Idle 1: Busy

AUXADC_LBAT2_7 15

14

13

12

AUXADC_LBAT2_7 11

10

9

8

AUXAD C_ADC Name _RDY_L BAT2 RO Type

Reset

0000

AUXADC_ADC_OUT_LBAT2 RO

0

0

Bit(s) 15

Name AUXADC_ADC_RDY_LBAT2

11:0

AUXADC_ADC_OUT_LBAT2

MediaTek Proprietary and Confidential.

7

0

0

0

0

0

0

0

Description AUXADC channel 0 low battery 2 output data ready 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 0 low battery 2 output data

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 206 of 1067

MT6359 PMIC Datasheet Confidential A 0000124A

AUXADC_LBAT2_8 15

Bit

14

13

12

AUXADC_LBAT2_8 11

10

9

8

0003

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

0

0

0

0

AUXAD C_ADC Name _BUSY _IN_LB AT2 RO Type

Reset Bit(s) 15

0

Name AUXADC_ADC_BUSY_IN_LBAT2

0000125A

AUXADC_THR7 15

Bit

Description ADC busy status 0: Idle 1: Busy

14

13

12

AUXADC_THR7 11

10

9

8

AUXAD C_ADC Name _RDY_ THR_H W RO Type

Reset

AUXADC_ADC_OUT_THR_HW

RO

0

0

Bit(s) 15

Name AUXADC_ADC_RDY_THR_HW

11:0

AUXADC_ADC_OUT_THR_HW

0000125C Bit

0

14

13

12

0

0

0

0

0

0

Description AUXADC thermal output data ready 0: AUXADC data proceeding 1: AUXADC data ready AUXADC thermal output data

AUXADC_THR8 15

0000

AUXADC_THR8 11

10

9

8

0003 7

6

5

4

3

2

1

0

AUXAD C_ADC Name _BUSY _IN_TH R_HW RO Type

Reset Bit(s) 15

0

Name AUXADC_ADC_BUSY_IN_THR_HW

MediaTek Proprietary and Confidential.

Description ADC busy status 0: Idle 1: Busy

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 207 of 1067

MT6359 PMIC Datasheet Confidential A 00001266

AUXADC_MDRT_4 15

Bit

AUXAD C_ADC Name _RDY_ MDRT RO Type 0 Reset

14

13

12

0

0

0

Name AUXADC_ADC_RDY_MDRT

14:0

AUXADC_ADC_OUT_MDRT

0

0

9

8

7

0000 6

5

4

3

2

1

0

14

13

12

0

0

RO 0

0

0

0

0

0

0

0

3

2

1

Description AUXADC channel 7 MDRT output data ready 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 7 MDRT output data

AUXADC_MDRT_5 15

Bit

10

AUXADC_ADC_OUT_MDRT

Bit(s) 15

00001268

AUXADC_MDRT_4 11

AUXADC_MDRT_5 11

10

9

8

7

0001 6

5

4

0

AUXAD C_ADC Name _BUSY _IN_M DRT RO Type

Reset Bit(s) 15

0

Name AUXADC_ADC_BUSY_IN_MDRT

0000126E Bit

Description ADC busy status 0: Idle 1: Busy

AUXADC_DCXO_MDRT_3 15

AUXAD C_ADC Name _RDY_ DCXO_ MDRT RO Type 0 Reset

14

13

12

11

AUXADC_DCXO_MDRT_3 10

9

8

7

6

0000 5

4

3

2

1

0

0

0

0

0

0

AUXADC_ADC_OUT_DCXO_MDRT

0

0

0

0

Bit(s) 15

Name AUXADC_ADC_RDY_DCXO_MDRT

14:0

AUXADC_ADC_OUT_DCXO_MDRT

MediaTek Proprietary and Confidential.

0

0

0

RO 0

0

0

Description AUXADC channel 10 wakeup DCXO output data ready 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 10 wakeup DCXO output data

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 208 of 1067

MT6359 PMIC Datasheet Confidential A 00001270

AUXADC_DCXO_MDRT_4 15

Bit

14

13

12

11

AUXADC_DCXO_MDRT_4 10

9

8

7

6

0000 5

4

3

2

1

3

2

1

0

AUXAD C_ADC _BUSY Name _IN_DC XO_M DRT RO Type

Reset Bit(s) 15

0

Name AUXADC_ADC_BUSY_IN_DCXO_MDRT

00001418

BUCK_TOP_INT_CON0 15

Bit

Description ADC busy status 0: Idle 1: Busy

14

13

12

11

BUCK_TOP Interrupt Enable Control 0 10

Type Reset

0

Name RG_INT_EN_VPA_OC RG_INT_EN_VS2_OC RG_INT_EN_VS1_OC RG_INT_EN_VPROC2_OC RG_INT_EN_VPROC1_OC RG_INT_EN_VMODEM_OC RG_INT_EN_VGPU12_OC RG_INT_EN_VGPU11_OC RG_INT_EN_VCORE_OC RG_INT_EN_VPU_OC

0000141A

0

6

5

4

0000

14

0

13

0

12

0

0

0

14

0

MediaTek Proprietary and Confidential.

13

0

12

0

0

0

0

0

0

0

0

0

9

8

7

6

0000

11

10

5

4

3

2

1

0

0

RG_BUCK_TOP_INT_EN_CON0_SET W1 0 0 0 0 0 0

0

0

0

0

0

Description

BUCK_TOP_INT_CON0_CLR 15

0

BUCK_TOP Interrupt Enable Control 0 SET

Name RG_BUCK_TOP_INT_EN_CON0_SET

0000141C Bit Name Type Reset

7

Description

BUCK_TOP_INT_CON0_SET 15

Bit Name Type Reset Bit(s) 15:0

8

RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT _EN_V _EN_V _EN_V _EN_V _EN_V _EN_V _EN_V _EN_V _EN_V _EN_V PROC2 PROC1 MODE GPU12 GPU11 CORE_ PA_OC S2_OC S1_OC PU_OC _OC _OC M_OC _OC _OC OC RW RW RW RW RW RW RW RW RW RW

Name

Bit(s) 9 8 7 6 5 4 3 2 1 0

9

BUCK_TOP Interrupt Enable Control 0 CLR 9

8

7

6

0000

11

10

5

4

3

2

1

0

0

RG_BUCK_TOP_INT_EN_CON0_CLR W1 0 0 0 0 0 0

0

0

0

0

0

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 209 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 15:0

Name RG_BUCK_TOP_INT_EN_CON0_CLR

0000141E

BUCK_TOP_INT_MASK_CON0 BUCK_TOP Interrupt Mask Control 0 15

Bit

Description

14

13

12

11

10

Type Reset

0

Name RG_INT_MASK_VPA_OC RG_INT_MASK_VS2_OC RG_INT_MASK_VS1_OC RG_INT_MASK_VPROC2_OC RG_INT_MASK_VPROC1_OC RG_INT_MASK_VMODEM_OC RG_INT_MASK_VGPU12_OC RG_INT_MASK_VGPU11_OC RG_INT_MASK_VCORE_OC RG_INT_MASK_VPU_OC

00001420

0

Bit(s) 15:0

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

14

0

13

0

12

0

9

8

7

6

0000

11

10

5

4

3

2

1

0

0

RG_BUCK_TOP_INT_MASK_CON0_SET W1 0 0 0 0 0 0

0

0

0

0

0

Description

BUCK_TOP_INT_MASK_CON0 BUCK_TOP Interrupt Mask Control 0 CLR _CLR 15

0

14

0

13

0

12

0

0

Description

Name RG_BUCK_TOP_INT_MASK_CON0_SET

00001422 Bit Name Type Reset

7

BUCK_TOP_INT_MASK_CON0 BUCK_TOP Interrupt Mask Control 0 SET _SET 15

Bit Name Type Reset Bit(s) 15:0

8

RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT _MASK _MASK _MASK _MASK _MASK _MASK _MASK _MASK _MASK _MASK _VMO _VPA_ _VS2_ _VS1_ _VPRO _VPRO _VGPU _VGPU _VCOR _VPU_ DEM_O OC OC OC C2_OC C1_OC 12_OC 11_OC E_OC OC C RW RW RW RW RW RW RW RW RW RW

Name

Bit(s) 9 8 7 6 5 4 3 2 1 0

9

0000

9

8

7

6

0000

11

10

5

4

3

2

1

0

0

RG_BUCK_TOP_INT_MASK_CON0_CLR W1 0 0 0 0 0 0

0

0

0

0

0

Name Description RG_BUCK_TOP_INT_MASK_CON0_CLR

MediaTek Proprietary and Confidential.

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Page 210 of 1067

MT6359 PMIC Datasheet Confidential A 00001424

BUCK_TOP_INT_STATUS0 15

Bit

14

13

12

11

BUCK_TOP Interrupt Status 0 10

Type Reset

0

Name RG_INT_STATUS_VPA_OC RG_INT_STATUS_VS2_OC RG_INT_STATUS_VS1_OC RG_INT_STATUS_VPROC2_OC RG_INT_STATUS_VPROC1_OC RG_INT_STATUS_VMODEM_OC RG_INT_STATUS_VGPU12_OC RG_INT_STATUS_VGPU11_OC RG_INT_STATUS_VCORE_OC RG_INT_STATUS_VPU_OC

00001426

6

0000 5

4

3

2

1

0

0

0

0

0

0

0

0

0

14

13

12

11

0

Description

10

9

8

7

6

5

0000 4

3

2

1

0

RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT _RAW_ _RAW_ _RAW_ _RAW_ _RAW_ _RAW_ _RAW_ _RAW_ _RAW_ _RAW_ STATUS STATUS STATUS STATUS STATUS STATUS STATUS STATUS STATUS STATU _VMO _VPA_ _VS2_ _VS1_ _VPRO _VPRO _VGPU _VGPU _VCOR S_VPU DEM_O OC OC OC C2_OC C1_OC 12_OC 11_OC E_OC _OC C RO RO RO RO RO RO RO RO RO RO

Name

Type Reset

0

Name RG_INT_RAW_STATUS_VPA_OC RG_INT_RAW_STATUS_VS2_OC RG_INT_RAW_STATUS_VS1_OC RG_INT_RAW_STATUS_VPROC2_OC RG_INT_RAW_STATUS_VPROC1_OC RG_INT_RAW_STATUS_VMODEM_OC RG_INT_RAW_STATUS_VGPU12_OC RG_INT_RAW_STATUS_VGPU11_OC RG_INT_RAW_STATUS_VCORE_OC RG_INT_RAW_STATUS_VPU_OC

00001430 Bit

7

BUCK_TOP_INT_RAW_STATU BUCK_TOP Interrupt Raw Status 0 S0 15

Bit

Bit(s) 9 8 7 6 5 4 3 2 1 0

8

RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT _STAT _STAT _STAT _STAT _STAT _STAT _STAT _STAT _STAT _STAT US_VP US_VP US_VM US_VG US_VG US_VC US_VP US_VS2 US_VS1 US_VP ROC2_ ROC1_ ODEM_ PU12_ PU11_ ORE_O A_OC _OC _OC U_OC OC OC OC OC OC C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C

Name

Bit(s) 9 8 7 6 5 4 3 2 1 0

9

14

Name

MediaTek Proprietary and Confidential.

13

12

11

0

0

0

0

0

0

0

0

4

3

2

1

0

RG_BU CK_VG PU11_ OC_SD N_STA TUS

RG_BU CK_VC ORE_O C_SDN _STAT US

RG_BU CK_VP U_OC_ SDN_S TATUS

Description

BUCK_TOP_OC_CON0 15

0

BUCK_TOP OC Control Register 0 10

9

8

7

6

RG_BU RG_BU RG_BU RG_BU CK_VP CK_VP CK_VS2 CK_VS1 ROC2_ A_OC_ _OC_S _OC_S OC_SD SDN_S DN_ST DN_ST N_STA TATUS ATUS ATUS TUS

5

0000

RG_BU RG_BU RG_BU CK_VP CK_VM CK_VG ROC1_ ODEM_ PU12_ OC_SD OC_SD OC_SD N_STA N_STA N_STA TUS TUS TUS

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 211 of 1067

MT6359 PMIC Datasheet Confidential A Type Reset Bit(s) 9

8

7

6

5

4

3

2

1

0

W1C

W1C

W1C

W1C

W1C

W1C

W1C

W1C

W1C

0

0

0

0

0

0

0

0

0

0

Name RG_BUCK_VPA_OC_SDN_STATUS

Description OC status condition (write 1 clear) 0: No OC 1: OC occurs. RG_BUCK_VS2_OC_SDN_STATUS OC status condition (write 1 clear) 0: No OC 1: OC occurs. RG_BUCK_VS1_OC_SDN_STATUS OC status condition (write 1 clear) 0: No OC 1: OC occurs. RG_BUCK_VPROC2_OC_SDN_STATUS OC status condition (write 1 clear) 0: No OC 1: OC occurs. RG_BUCK_VPROC1_OC_SDN_STATUS OC status condition (write 1 clear) 0: No OC 1: OC occurs. RG_BUCK_VMODEM_OC_SDN_STATUS OC status condition (write 1 clear) 0: No OC 1: OC occurs. RG_BUCK_VGPU12_OC_SDN_STATUS OC status condition (write 1 clear) 0: No OC 1: OC occurs. RG_BUCK_VGPU11_OC_SDN_STATUS OC status condition (write 1 clear) 0: No OC 1: OC occurs. RG_BUCK_VCORE_OC_SDN_STATUS OC status condition (write 1 clear) 0: No OC 1: OC occurs. RG_BUCK_VPU_OC_SDN_STATUS OC status condition (write 1 clear) 0: No OC 1: OC occurs.

00001488 Bit

W1C

BUCK_VPU_CON0 15

14

13

12

BUCK VPU Control 0 11

10

9

8

7

0001 6

5

4

3

2

1

0

RG_BU RG_BU CK_VP CK_VP U_LP U_EN RW RW

Name Type Reset

0

Bit(s) 1

Name RG_BUCK_VPU_LP

0

RG_BUCK_VPU_EN

MediaTek Proprietary and Confidential.

1

Description Enter low power mode Valid once RG_BUCK_VPU_SW_OP_EN = 1'b1 0: No LP 1: LP Enable control Valid once RG_BUCK_VPU_SW_OP_EN = 1'b1 0: Off 1: On

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 212 of 1067

MT6359 PMIC Datasheet Confidential A 0000148E

BUCK_VPU_CON1 15

Bit

14

13

12

BUCK VPU Control 1 11

10

9

8

7

Name Type Reset Bit(s) 6:0

4

3

2

1

0

0

RW 0

Name RG_BUCK_VPU_VOSEL_SLEEP

14

13

12

0

1

1

0

0

5

4

3

2

1

0

0

0

Description Selects VOUT in sleep mode Vout = 0.4V + 6.25 mV*code

BUCK_VPU_ELR0 15

Bit

BUCK_VPU ELR 0 Register 11

10

9

8

7

Name Type Reset

6

0018 RG_BUCK_VPU_VOSEL RW

0

Name RG_BUCK_VPU_VOSEL

00001508 Bit

5

RG_BUCK_VPU_VOSEL_SLEEP

000014AC

Bit(s) 6:0

0018 6

14

13

1

1

0

Description Selects VOUT in normal mode Vout = 0.4V + 6.25 mV*code

BUCK_VCORE_CON0 15

0

12

BUCK VCORE Control 0 11

10

9

8

7

0001 6

5

4

3

2

1

0

RG_BU RG_BU CK_VC CK_VC ORE_E ORE_LP N RW RW

Name Type Reset

0

Bit(s) 1

Name RG_BUCK_VCORE_LP

0

RG_BUCK_VCORE_EN

MediaTek Proprietary and Confidential.

1

Description Enter low power mode Valid once RG_BUCK_VCORE_SW_OP_EN = 1'b1 0: No LP 1: LP Enable control Valid once RG_BUCK_VCORE_SW_OP_EN = 1'b1 0: Off 1: On

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 213 of 1067

MT6359 PMIC Datasheet Confidential A 0000150E

BUCK_VCORE_CON1 15

Bit

14

13

12

BUCK VCORE Control 1 11

10

9

8

7

Name Type Reset Bit(s) 6:0

5

4

3

2

Name RG_BUCK_VCORE_VOSEL_SLEEP

BUCK_VCORE_ELR0 15

14

13

12

0

0

0

0

0

5

4

3

2

1

0

0

0

BUCK_VCORE ELR 0 Register 11

0

Description Selects VOUT in sleep mode Vout = 0.4V + 6.25 mV*code

10

9

8

7

Name Type Reset

6

0040 RG_BUCK_VCORE_VOSEL RW

1

Name RG_BUCK_VCORE_VOSEL

00001588

14

13

12

0

0

0

0

Description Selects VOUT in normal mode Vout = 0.4V + 6.25 mV*code

BUCK_VGPU11_CON0 15

Bit

11

BUCK VGPU11 Control 0 10

9

8

7

6

0001 5

4

3

2

1

0

RG_BU RG_BU CK_VG CK_VG PU11_L PU11_ P EN RW RW

Name Type Reset

0

Bit(s) 1

Name RG_BUCK_VGPU11_LP

0

RG_BUCK_VGPU11_EN

0000158E

BUCK_VGPU11_CON1 15

14

13

1

Description Enter low power mode Valid once RG_BUCK_VGPU11_SW_OP_EN = 1'b1 0: No LP 1: LP Enable control Valid once RG_BUCK_VGPU11_SW_OP_EN = 1'b1 0: Off 1: On

12

11

Name Type Reset Bit(s) 6:0

0

RW 1

Bit

Bit

1

RG_BUCK_VCORE_VOSEL_SLEEP

00001534

Bit(s) 6:0

0040 6

BUCK VGPU11 Control 1 10

9

8

7

6

0018 5

4

3

2

1

0

RG_BUCK_VGPU11_VOSEL_SLEEP RW 0

Name RG_BUCK_VGPU11_VOSEL_SLEEP

MediaTek Proprietary and Confidential.

0

1

1

0

0

0

Description Selects VOUT in sleep mode Vout = 0.4V + 6.25 mV*code

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 214 of 1067

MT6359 PMIC Datasheet Confidential A 000015AC

BUCK_VGPU11_ELR0 15

Bit

14

13

12

BUCK_VGPU11 ELR 0 Register 11

10

9

8

7

Name Type Reset Bit(s) 6:0

6

0018 5

4

3

2

Name RG_BUCK_VGPU11_VOSEL

14

13

12

1

1

0

0

5

4

3

2

1

Description Selects VOUT in normal mode Vout = 0.4V + 6.25 mV*code

BUCK_VMODEM_CON0 15

0

11

BUCK VMODEM CONTROL 0 10

9

8

7

6

0001 0

RG_BU RG_BU CK_VM CK_VM ODEM_ ODEM LP _EN RW RW

Name Type Reset

0

Bit(s) 1

Name RG_BUCK_VMODEM_LP

0

RG_BUCK_VMODEM_EN

0000168E

14

13

12

1

Description Enter low power mode Valid once RG_BUCK_VMODEM_SW_OP_EN = 1'b1 0: No LP 1: LP Enable control Valid once RG_BUCK_VMODEM_SW_OP_EN = 1'b1 0: Off 1: On

BUCK_VMODEM_CON1 15

Bit

11

BUCK VMODEM CONTROL 1 10

9

8

7

Name Type Reset

6

0048 5

4

3

2

1

0

RG_BUCK_VMODEM_VOSEL_SLEEP RW 1

Name RG_BUCK_VMODEM_VOSEL_SLEEP

000016AE

14

13

12

11

0

0

1

0

0

0

4

3

2

1

0

0

0

Description Selects VOUT in sleep mode Vout = 0.4V + 6.25 mV*code

BUCK_VMODEM_ELR0 15

Name Type Reset Bit(s) 6:0

0

RW 0

Bit

Bit

0

RG_BUCK_VGPU11_VOSEL

00001688

Bit(s) 6:0

1

BUCK_VMODEM ELR 0 register 10

9

8

7

6

5

0048 RG_BUCK_VMODEM_VOSEL RW

1

Name RG_BUCK_VMODEM_VOSEL

MediaTek Proprietary and Confidential.

0

0

1

0

Description Selects VOUT in normal mode Vout = 0.4V + 6.25 mV*code

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 215 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001708

BUCK_VPROC1_CON0 15

Bit

Description

14

13

12

11

BUCK VPROC1 Control 0 10

9

8

7

6

0001 5

4

3

2

Type Reset

0

Bit(s) 1

Name RG_BUCK_VPROC1_LP

0

RG_BUCK_VPROC1_EN

0000170E

14

13

12

11

BUCK VPROC1 Control 1 10

9

8

7

Name Type Reset

6

0040 5

4

3

2

1

0

RG_BUCK_VPROC1_VOSEL_SLEEP RW 1

Name RG_BUCK_VPROC1_VOSEL_SLEEP

0000172E

14

13

12

0

0

0

0

0

5

4

3

2

1

0

0

0

BUCK_VPROC1 ELR 0 Register 11

0

Description Selects VOUT in sleep mode Vout = 0.4V + 6.25 mV*code

BUCK_VPROC1_ELR0 15

Name Type Reset Bit(s) 6:0

1

Description Enter low power mode Valid once RG_BUCK_VPROC1_SW_OP_EN = 1'b1 0: No LP 1: LP Enable control Valid once RG_BUCK_VPROC1_SW_OP_EN = 1'b1 0: Off 1: On

BUCK_VPROC1_CON1 15

Bit

Bit

0

RG_BU RG_BU CK_VP CK_VP ROC1_L ROC1_ P EN RW RW

Name

Bit(s) 6:0

1

10

9

8

7

6

0040 RG_BUCK_VPROC1_VOSEL RW

1

Name RG_BUCK_VPROC1_VOSEL

MediaTek Proprietary and Confidential.

0

0

0

0

Description Selects VOUT in normal mode Vout = 0.4V + 6.25 mV*code

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 216 of 1067

MT6359 PMIC Datasheet Confidential A 00001788

BUCK_VPROC2_CON0 15

Bit

14

13

12

11

BUCK VPROC2 Control 0 10

9

8

7

6

0001 5

4

3

2

Type Reset

0

Bit(s) 1

Name RG_BUCK_VPROC2_LP

0

RG_BUCK_VPROC2_EN

0000178E

14

13

12

11

BUCK VPROC2 Control 1 10

9

8

7

Name Type Reset

6

0040 5

4

2

1

0

RW 1

Name RG_BUCK_VPROC2_VOSEL_SLEEP

14

13

12

0

0

0

0

0

5

4

3

2

1

0

0

BUCK_VPROC2 ELR 0 Register 11

0

Description Selects VOUT in sleep mode Vout = 0.4V + 6.25 mV*code

BUCK_VPROC2_ELR0 15

Bit

10

9

8

7

Name Type Reset

6

0040 RG_BUCK_VPROC2_VOSEL RW

1

Name RG_BUCK_VPROC2_VOSEL

00001808

14

13

12

0

0

0

0

5

4

3

2

1

Description Selects VOUT in normal mode Vout = 0.4V + 6.25 mV*code

BUCK_VS1_CON0 15

0

BUCK VS1 Control 0 11

10

9

8

7

0001 6

0

RG_BU RG_BU CK_VS1 CK_VS _LP 1_EN RW RW

Name Type Reset Bit(s) 1

3

RG_BUCK_VPROC2_VOSEL_SLEEP

000017B2

Bit

1

Description Enter low power mode Valid once RG_BUCK_VPROC2_SW_OP_EN = 1'b1 0: No LP 1: LP Enable control Valid once RG_BUCK_VPROC2_SW_OP_EN = 1'b1 0: Off 1: On

BUCK_VPROC2_CON1 15

Bit

Bit(s) 6:0

0

RG_BU RG_BU CK_VP CK_VP ROC2_L ROC2_ P EN RW RW

Name

Bit(s) 6:0

1

0

Name RG_BUCK_VS1_LP

MediaTek Proprietary and Confidential.

1

Description Enter low power mode

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 217 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

0

Name

Description Valid once RG_BUCK_VS1_SW_OP_EN = 1'b1 0: No LP 1: LP Enable control Valid once RG_BUCK_VS1_SW_OP_EN = 1'b1 0: Off 1: On

RG_BUCK_VS1_EN

00001888

BUCK_VS2_CON0 15

Bit

14

13

12

BUCK VS2 Control 0 11

10

9

8

7

0001 6

5

4

3

2

Type Reset

0

Bit(s) 1

Name RG_BUCK_VS2_LP

0

RG_BUCK_VS2_EN

00001908

14

13

12

BUCK VPA Control 0 11

10

9

8

7

0000 6

5

4

3

2

Type Reset

0

Bit(s) 1

Name RG_BUCK_VPA_LP

0

RG_BUCK_VPA_EN

0000190E 3Bit

1

0

RG_BU RG_BU CK_VP CK_VP A_LP A_EN RW RW

Name

4

1

Description Enter low power mode Valid once RG_BUCK_VS2_SW_OP_EN = 1'b1 0: No LP 1: LP Enable control Valid once RG_BUCK_VS2_SW_OP_EN = 1'b1 0: Off 1: On

BUCK_VPA_CON0 15

Bit

5

0

RG_BU RG_BU CK_VS2 CK_VS _LP 2_EN RW RW

Name

6

1

2

Description Enters low power mode 0: No LP 1: LP Enable control 0: Off 1: On

BUCK_VPA_CON1

BUCK VPA Control 1

0000 0

1

Name Type Reset

MediaTek Proprietary and Confidential.

0

RG_BUCK_VPA_VOSEL RW 0

0

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

0

0

0

0

Page 218 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 5:0

Name RG_BUCK_VPA_VOSEL

0000198E

VGPUVCORE_ANA_CON2 15

Bit

Description Selects VOUT in normal mode (SW mode) VOUT = 0.5V + 50 mV*code

14

13

12

10

RG_VG PU11_ NONA UDIBLE _EN RW

Name

Type Reset Bit(s) 11 9

11

VGPUVCORE Control Register 2

14

13

12

11

4

2

1

0

10

9

8

7

6

5

FF00 4

3

2

1

0

RG_VC ORE_N RG_VC ONAU ORE_F DIBLE_ CCM EN RW RW 0

Name RG_VCORE_NONAUDIBLE_EN RG_VCORE_FCCM

000019B2

Description Enables PFM frequency > 25 kHz 1'b0: Auto-mode (default) 1'b1: Force PWM

VPROC1_ANA_CON3 15

14

13

12

0

VPROC1 Control Register 3 11

10

9

8

7

6

0000 5

4

3

2

1

0

RG_VP ROC1_ RG_VP NONA ROC1_ UDIBLE FCCM _EN RW RW

Name

Type Reset Bit(s) 2 1

3

VGPUVCORE Control Register 13

Type Reset

Bit

5

Description Enables PFM frequency > 25 kHz 1'b0: Auto-mode (default) 1'b1: Force PWM

Name

Bit(s) 6 5

6

0

VGPUVCORE_ANA_CON13 15

7

RW

Name RG_VGPU11_NONAUDIBLE_EN RG_VGPU11_FCCM

Bit

8

RG_VG PU11_F CCM

0

000019A4

9

0005

0

Name RG_VPROC1_NONAUDIBLE_EN RG_VPROC1_FCCM

MediaTek Proprietary and Confidential.

0

Description Enables PFM frequency > 25 kHz 1'b0: Auto-mode (default) 1'b1: Force PWM

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 219 of 1067

MT6359 PMIC Datasheet Confidential A 00001A0E

VPROC2_ANA_CON3 15

Bit

14

13

12

VPROC2 Control Register 3 11

10

9

8

7

6

0000 5

4

3

Type Reset Name RG_VPROC2_NONAUDIBLE_EN RG_VPROC2_FCCM

00001A1A

14

13

12

11

9

8

7

6

0

2

1

0000 5

4

3

0

RG_VM ODEM_ RG_VM NONA ODEM_ UDIBLE FCCM _EN RW RW

Type Reset Name RG_VMODEM_NONAUDIBLE_EN RG_VMODEM_FCCM

00001A26

14

13

12

0

0

2

1

Description Enables PFM frequency > 25 kHz 1'b0: Auto-mode (default) 1'b1: Force PWM

VPU_ANA_CON3 15

Bit

VPU Control Register 3 11

10

9

8

7

0000 6

5

4

3

0

RG_VP RG_VP U_NON U_FCC AUDIBL M E_EN RW RW

Name Type Reset

0

Name RG_VPU_NONAUDIBLE_EN RG_VPU_FCCM

00001A2C Bit

0

VMODEM Control Register 3 10

Name

Bit(s) 2 1

0

Description Enables PFM frequency > 25 kHz 1'b0: Auto-mode (default) 1'b1: Force PWM

VMODEM_ANA_CON3 15

Bit

Bit(s) 2 1

1

RG_VP ROC2_ RG_VP NONA ROC2_ UDIBLE FCCM _EN RW RW

Name

Bit(s) 2 1

2

Description Enables PFM frequency > 25 kHz 1'b0: Auto-mode (default) 1'b1: Force PWM

VS1_ANA_CON0 15

14

13

12

VS1 Control Register 0 11

10

9

8

7

5044 6

5

4

3

2

1

0

RG_VS 1_FPW M RW

Name Type Reset

MediaTek Proprietary and Confidential.

0

0

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 220 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 3

Name RG_VS1_FPWM

00001A32

VS1_ANA_CON3 15

Bit

Description 1'b0: Auto-mode (default) 1'b1: Force PWM

14

13

12

VS1 Control Register 3 11

10

9

8

7

0150 6

5

4

3

2

Type Reset

0

Name RG_VS1_NONAUDIBLE_EN

00001A34

Description Enables PFM frequency > 25 kHz

VS2_ANA_CON0 15

Bit

14

13

12

VS2 Control Register 0 11

10

9

8

7

5044 6

5

4

3

2

1

2

1

Type Reset

0

Name RG_VS2_FPWM

00001A3A

Description 1'b0: Auto-mode (default) 1'b1: Force PWM

VS2_ANA_CON3 15

Bit

14

13

12

VS2 Control Register 3 11

10

9

8

7

0150 6

5

4

3

Type Reset

0

Name RG_VS2_NONAUDIBLE_EN

0000230C Bit

0

RG_VS 2_NON AUDIBL E_EN RW

Name

Bit(s) 1

0

RG_VS 2_FPW M RW

Name

Bit(s) 3

0

RG_VS 1_NON AUDIBL E_EN RW

Name

Bit(s) 1

1

Description Enables PFM frequency > 25 kHz

AUD_TOP_CKPDN_CON0 15

14

13

12

11

AUDIO CLK Power Down Register 0 10

9

8

7

6

5

0000 4

3

2

1

0

RG_PA

G_AU RG_ZC

Name

RG_AC W13M W32K_ _CK_P CK_PD DN N

Type Reset

MediaTek Proprietary and Confidential.

RW

RW

0

0

D_INTR _CLK_ DNCP_ D13M_ P_CK_P MISO_ CK_PD CK_PD DN CK_PD N N N RW RW RW RW 0

0

0

0

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

RG_AU RG_AU CDET_ DIF_CK D_CK_ CK_PD _PDN PDN N RW

RW

RW

0

0

0

Page 221 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 13

Name RG_VOW13M_CK_PDN

12

RG_VOW32K_CK_PDN

8

RG_AUD_INTRP_CK_PDN

7

RG_PAD_AUD_CLK_MISO_CK_PDN

6

RG_AUDNCP_CK_PDN

5

RG_ZCD13M_CK_PDN

2

RG_AUDIF_CK_PDN

1

RG_AUD_CK_PDN

0

RG_ACCDET_CK_PDN

00002312 Bit

Description VOW13M_CK power down 0: Power on 1: Power down VOW32K_CK power down 0: Power on 1: Power down AUD_INTRP_CK power down 0: Power on 1: Power down PAD_AUD_CLK_MISO_CK power down 0: Power on 1: Power down AUDNCP_CK power down 0: Power on 1: Power down ZCD13M_CK power down 0: Power on 1: Power down AUDIF_CK power down 0: Power on 1: Power down AUD_CK power down 0: Power on 1: Power down ACCDET_CK power down 0: Power on 1: Power down

AUD_TOP_CKSEL_CON0 15

14

13

12

11

AUDIO CKSEL Control Register 0 10

9

8

7

6

5

0000 4

Type Reset

2

2

1

0

RG_AU RG_AU DIF_CK D_CK_ _CKSEL CKSEL RW RW

Name

Bit(s) 3

3

0

Name RG_AUDIF_CK_CKSEL

RG_AUD_CK_CKSEL

MediaTek Proprietary and Confidential.

0

Description AUDIF_CK clock selection 1'b0: R_AUD_CLK_MOSI 1'b1: R_AUD26M_CK AUD_CK clock selection 1'b0: R_AUD26M_CK 1'b1: R_AUD_CLK_MOSI

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 222 of 1067

MT6359 PMIC Datasheet Confidential A 00002328

AUD_TOP_INT_CON0 15

Bit

14

13

12

AUDIO INT Control Register 0

11

10

9

8

Type Reset

0

Bit(s) 7

Name RG_INT_EN_ACCDET_EINT1

6

RG_INT_EN_ACCDET_EINT0

5

RG_INT_EN_ACCDET

0

RG_INT_EN_AUDIO

0000232A

0

4

3

2

1

14

0

13

0

12

0

11

0

14

0

13

0

12

0

Name RG_AUD_INT_CON0_CLR

MediaTek Proprietary and Confidential.

RW

0

0

0

8

7

0000

10

9

6

5

4

3

2

1

0

0

RG_AUD_INT_CON0_SET W1 0 0 0 0

0

0

0

0

0

0

Description 1'b0: Not set 1'b1: Set

AUD_TOP_INT_CON0_CLR 15

0

0 RG_INT _EN_A UDIO

AUD_TOP_INT Control Register 0 SET

Name RG_AUD_INT_CON0_SET

0000232C

Bit(s) 15:0

0000 5

Description ACCDET_EINT1 interrupt enable 0: Not issue interrupt 1: Issue interrupt ACCDET_EINT0 interrupt enable 0: Not issue interrupt 1: Issue interrupt ACCDET interrupt enable 0: Not issue interrupt 1: Issue interrupt AUDIO interrupt enable 0: Not issue interrupt 1: Issue interrupt

AUD_TOP_INT_CON0_SET 15

Bit Name Type Reset

Bit Name Type Reset

6

RG_INT RG_INT RG_INT _EN_A _EN_A _EN_A CCDET_ CCDET_ CCDET EINT1 EINT0 RW RW RW

Name

Bit(s) 15:0

7

11

0

AUD_TOP_INT Control Register 0 CLR 8

7

0000

10

9

6

5

4

3

2

1

0

0

RG_AUD_INT_CON0_CLR W1 0 0 0 0

0

0

0

0

0

0

Description 1'b0: Not clear 1'b1: Clear

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 223 of 1067

MT6359 PMIC Datasheet Confidential A 0000232E

AUD_TOP_INT_MASK_CON0 AUDIO INT MASK Control Register 0 15

Bit

14

13

12

11

10

9

8

Type Reset

0

Bit(s) 7

Name RG_INT_MASK_ACCDET_EINT1

6

RG_INT_MASK_ACCDET_EINT0

5

RG_INT_MASK_ACCDET

0

RG_INT_MASK_AUDIO

00002330

0000 4

3

2

1

0

14

13

12

11

0 RG_INT _MASK _AUDI O RW

0

0

Description Masks ACCDET_EINT1 interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks ACCDET_EINT0 interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks ACCDET interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks AUDIO interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status

10

9

8

Name Type Reset

7

6

5

4

3

0000 2

1

0

0

0

RG_AUD_INT_MASK_CON0_SET W1 0

Name RG_AUD_INT_MASK_CON0_SET

00002332

0

0

0

0

0

Description 1'b0: Not set 1'b1: Set

AUD_TOP_INT_MASK_CON0_ AUD_TOP_INT Mask Control Register 0 CLR CLR 15

14

13

12

11

10

9

8

Name Type Reset Bit(s) 7:0

5

AUD_TOP_INT_MASK_CON0_ AUD_TOP_INT Mask Control Register 0 SET SET 15

Bit

Bit

6

RG_INT RG_INT RG_INT _MASK _MASK _MASK _ACCD _ACCD _ACCD ET_EIN ET_EIN ET T1 T0 RW RW RW

Name

Bit(s) 7:0

7

7

6

5

4

3

0000 2

1

0

0

0

RG_AUD_INT_MASK_CON0_CLR W1 0

Name RG_AUD_INT_MASK_CON0_CLR

MediaTek Proprietary and Confidential.

0

0

0

0

0

Description 1'b0: Not clear 1'b1: Clear

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 224 of 1067

MT6359 PMIC Datasheet Confidential A 00002334

AUD_TOP_INT_STATUS0 15

Bit

14

13

12

11

AUDIO INT STATUS0 Control Register 10

9

8

Type Reset

0

Bit(s) 7

Name RG_INT_STATUS_ACCDET_EINT1

6

RG_INT_STATUS_ACCDET_EINT0

5

RG_INT_STATUS_ACCDET

0

RG_INT_STATUS_AUDIO

00002336 15

14

5

0

4

0000 3

2

1

0

13

12

11

0 RG_INT _STAT US_AU DIO W1C

0

0

Description ACCDET_EINT1 interrupt status 0: No interrupt issued 1: Interrupt issued ACCDET_EINT0 interrupt status 0: No interrupt issued 1: Interrupt issued ACCDET interrupt status 0: No interrupt issued 1: Interrupt issued AUDIO interrupt status 0: No interrupt issued 1: Interrupt issued

10

9

8

7

6

5

4

RG_INT RG_INT RG_INT _RAW_ _RAW_ _RAW_ STATUS STATUS STATUS _ACCD _ACCD _ACCD ET_EIN ET_EIN ET T1 T0 RO RO RO

Type Reset

6

5

AUD_TOP_INT_RAW_STATUS AUD_TOP_INT_RAW_STATUS0 Register 0

Name

Bit(s) 7

6

RG_INT RG_INT RG_INT _STAT _STAT _STAT US_AC US_AC US_AC CDET_E CDET_E CDET INT1 INT0 W1C W1C W1C

Name

Bit

7

0

0

0

0000 3

2

1

0 RG_INT _RAW_ STATU S_AUDI O RO 0

Name Description RG_INT_RAW_STATUS_ACCDET_EINT1 ACCDET_EINT1 raw interrupt status 0: No interrupt issued 1: Interrupt issued RG_INT_RAW_STATUS_ACCDET_EINT0 ACCDET_EINT0 raw interrupt status 0: No interrupt issued 1: Interrupt issued RG_INT_RAW_STATUS_ACCDET ACCDET raw interrupt status 0: No interrupt issued 1: Interrupt issued RG_INT_RAW_STATUS_AUDIO AUDIO raw interrupt status 0: No interrupt issued 1: Interrupt issued

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 225 of 1067

MT6359 PMIC Datasheet Confidential A 00002338

AUD_TOP_INT_MISC_CON0 AUD_TOP_INT_MISC Control Register 0 15

Bit

14

13

12

11

10

9

8

7

6

5

4

0000 3

2

1

Name Type Reset Bit(s) 0

0

Name RG_AUD_TOP_INT_POLARITY

0000233A

14

13

12

Type Reset

0

14

13

12

8

7

6

5

0000 4

3

0

0

4

3

1

0

0

0

0

0

0

2

1

Description Enables ACCDET monitor flag Selects ACCDET monitor flag

Audio UL and DL Control Register 0 11

0

10

9

8

7

6

5

0000

RW

0

0

Description Audio UL L/R channel swap before UL SRC Audio DL L/R channel swap before DAC FIFO Turns on audio UL and DL

AFE_DL_SRC2_CON0_L 14

0 AFE_O N

Name AFE_UL_LR_SWAP AFE_DL_LR_SWAP AFE_ON

15

0

RW

13

12

11

AFE_DL_SRC2 Control Register 0 Low Part 10

9

8

7

6

5

4

0000 3

2

1

0 DL_2_S RC_ON _TMP_ CTL_PR E RW

Name

Type Reset Bit(s)

2

AFE_UL AFE_DL _LR_S _LR_S WAP WAP RW RW

0000238A Bit

9

RG_AUD_CLK_INT_MON_FLAG_SEL

AFE_UL_DL_CON0 15

Bit

Bit(s) 15 14 0

AUD_TOP_MON control register 0 10

Name RG_AUD_CLK_INT_MON_FLAG_EN RG_AUD_CLK_INT_MON_FLAG_SEL

00002388

Type Reset

11 RG_AU D_CLK_ INT_M ON_FL AG_EN RW

Name

Name

Description aud_top interrupt polarity select bit 0: aud_top_intr is high active 1: aud_top_intr is high active

AUD_TOP_MON_CON0 15

Bit

Bit(s) 11 10:3

0 RG_AU D_TOP _INT_P OLARIT Y RW

0

Name

MediaTek Proprietary and Confidential.

Description © 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 226 of 1067

MT6359 PMIC Datasheet Confidential A 0

DL_2_SRC_ON_TMP_CTL_PRE

0000238C

AFE_UL_SRC_CON0_H 15

Bit

14

Type Reset

12

0

11

0

0

Bit(s) 15:14

0

9

8

7

6

5

4

3

0000 2

1

2

1

0

14

13

12

11

0

0

AFE Uplink SRC Control Register 0 Low Part 10

9

8

7

6

0

Name DMIC_LOW_POWER_MODE_CTL

6

DIGMIC_4P33M_SEL_CTL

5

DIGMIC_3P25M_1P625M_SEL_CTL

2

UL_LOOP_BACK_MODE_CTL

1

UL_SDM_3_LEVEL_CTL

0

UL_SRC_ON_TMP_CTL

MediaTek Proprietary and Confidential.

0

5

4

DIGMI DIGMI C_3P25 C_4P33 M_1P6 M_SEL 25M_S _CTL EL_CTL RW RW

RW 0

0

Description Selects 8 input phase latch Selects 8 input phase latch Turns on dual digital microphones mode 0: Turn off 1: Turn on

AFE_UL_SRC_CON0_L 15

DMIC_LOW_P Name OWER_MODE_ CTL

Type Reset

AFE Uplink SRC Control Register 0 High Part 10

Name C_DIGMIC_PHASE_SEL_CH1_CTL C_DIGMIC_PHASE_SEL_CH2_CTL C_TWO_DIGITAL_MIC_CTL

0000238E Bit

13

C_TWO C_DIGMIC_PHASE_SEL_ C_DIGMIC_PHASE_SEL_ _DIGIT CH1_CTL CH2_CTL AL_MIC _CTL RW RW RW

Name

Bit(s) 13:11 10:8 7

Turns on down-link

0

3

0000 0

UL_LO UL_SD UL_SR OP_BA M_3_L C_ON_ CK_MO EVEL_C TMP_C DE_CTL TL TL RW

RW

RW

0

0

0

Description Digital mic low power mode 0: Original mode 1: 1.625m 48k mode 2: 812.5k low power mode 3: 406.25k low power mode Digmic 4p33m mode 0: Turn off 1: Turn on Digmic input mode 1 0: 3.25M mode 1: 1.625M mode Enables loopback mode from DL 0: Normal UL 1: Loopback from DL Selects SDM 3-level mode (digital MIC data path), first priority choice 0: De-select SDM 3-level mode 1: Select SDM 3-level mode Turns on uplink SRC 0: Turn off 1: Turn on

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 227 of 1067

MT6359 PMIC Datasheet Confidential A 00002390

AFE_ADDA6_L_SRC_CON0_H AFE Uplink2 SRC Control Register 0 High Part 15

Bit

14

Type Reset

10:8 7

0

11

0

0

Bit(s) 15:14

9

8

7

6

5

4

3

0000 2

1

0

0

0

2

1

0

0

Description Selects 8 input phase latch Selects 8 input phase latch Turns on dual digital microphones mode 0: Turn off 1: Turn on

AFE_ADDA6_UL_SRC_CON0_L AFE Uplink2 SRC Control Register 0 Low Part 15

14

13

12

11

RW 0

0

9

8

7

6

0

Name ADDA6_DMIC_LOW_POWER_MODE _CTL

6

ADDA6_DIGMIC_4P33M_SEL_CTL

5

ADDA6_DIGMIC_3P25M_1P625M_S EL_CTL

2

ADDA6_UL_LOOP_BACK_MODE_CTL

1

ADDA6_UL_SDM_3_LEVEL_CTL

0

ADDA6_UL_SRC_ON_TMP_CTL

MediaTek Proprietary and Confidential.

10

5

4

ADDA6 ADDA6 _DIGMI _DIGMI C_3P25 C_4P33 M_1P6 M_SEL 25M_S _CTL EL_CTL RW RW

ADDA6_DMIC_ Name LOW_POWER_ MODE_CTL

Type Reset

10

Name ADDA6_C_DIGMIC_PHASE_SEL_CH1 _CTL ADDA6_C_DIGMIC_PHASE_SEL_CH2 _CTL ADDA6_C_TWO_DIGITAL_MIC_CTL

00002392 Bit

12

ADDA6 _C_TW ADDA6_C_DIGMIC_PH ADDA6_C_DIGMIC_PH O_DIGI ASE_SEL_CH1_CTL ASE_SEL_CH2_CTL TAL_MI C_CTL RW RW RW

Name

Bit(s) 13:11

13

0

3

0000 0

ADDA6 ADDA6 ADDA6 _UL_LO _UL_SD _UL_SR OP_BA M_3_L C_ON_ CK_MO EVEL_C TMP_C DE_CTL TL TL RW

RW

RW

0

0

0

Description Digital mic low power mode 0: Original mode 1: 1.625m 48k mode 2: 812.5k low power mode 3: 406.25k low power mode Digmic 4p33m mode 0: Turn off 1: Turn on Digmic input mode 1 0: 3.25M mode 1: 1.625M mode Enables loopback mode from DL 0: Normal UL 1: Loopback from DL Selects SDM 3-level mode (digital MIC data path), first priority choice 0: De-select SDM 3-level mode 1: Select SDM 3-level mode Turns on uplink SRC 0: Turn off 1: Turn on

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 228 of 1067

MT6359 PMIC Datasheet Confidential A 00002394

AFE_TOP_CON0 15

Bit

14

13

12

AFE Top Control Register 0 11

10

9

8

7

6

0000 5

Type Reset

0

Name ADDA6_MTKAIF_SINE_ON

3

ADDA6_UL_SINE_ON

2

MTKAIF_SINE_ON

1

UL_SINE_ON

0

DL_SINE_ON

00002396 Bit

3

2

1

0

ADDA6 ADDA6 MTKAI _MTKA UL_SIN DL_SIN _UL_SI F_SINE IF_SINE E_ON E_ON NE_ON _ON _ON RW RW RW RW RW

Name

Bit(s) 4

4

14

13

12

0

0

0

Description Enables mtkaif sine table 0: MTKAIF from adda6 ul_fifo normal path 1: MTKAIF from sinetable Enables UL2 sine table 0: UL2 from normal path 1: UL2 from sinetable Enables mtkaif sine table 0: MTKAIF from ul_fifo normal path. 1: MTKAIF from sinetable Enables UL sine table 0: UL from up8x_rxif normal path 1: UL from sine table Enables DL sine table 0: DL from up8x_rxif normal path. 1: DL from sinetable

AUDIO_TOP_CON0 15

0

AUDIO Top Control Register 0 11

10

9

8

7

6

0000 5

4

3

2

1

0

PDN_A PDN_A PDN_I2 PWR_C PDN_R PDN_A PDN_D PDN_A DDA6_ FE_TES S_DL_C LK_DIS ESERVE FE_CTL AC_CTL DC_CTL ADC_C TMODE TL _CTL D TL L_CTL RW RW RW RW RW RW RW RW

Name Type Reset

0

Bit(s) 7

Name PDN_AFE_CTL

6

PDN_DAC_CTL

5

PDN_ADC_CTL

4

PDN_ADDA6_ADC_CTL

3 2

PDN_I2S_DL_CTL PWR_CLK_DIS_CTL

1

PDN_AFE_TESTMODEL_CTL

MediaTek Proprietary and Confidential.

0

0

0

0

0

0

0

Description Powers down afe 0: Not power down 1: Power down Powers down down-link 0: Not power down 1: Power down Powers down adda up-link 0: Not power down 1: Power down Powers down adda6 up-link 0: Not power down 1: Power down Reserved Disables total audio clk 0: Not power down 1: Power down Powers down some built-in testing model clock sources 0: Not power down

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 229 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 0

Name

Description 1: Power down 0: Not power down 1: Power down

PDN_RESERVED

00002398

AFE_MON_DEBUG0 15

Bit

14

13

12

AUDIO_SYS_T Name OP_MON_SWA P RW Type

Reset

0

0

12:8 7:0

AUDIO_SYS_TOP_MON_SEL AFE_MON_SEL

0

0

14

8

7

6

5

13

12

0000

4

3

2

1

0

0

0

0

2

1

AFE_MON_SEL RW

0

0

0

0

0

0

0

Description Monitors output swap from 32 bits to 8 bits 0: mon_out[7:0] 1: mon_out[15:8] 2: mon_out[23:16] 3: mon_out[31:24] Monitors output selection of audio system top level Monitors output selection of afe level

AFUNC_AUD_CON0 15

9

RW

0

Name AUDIO_SYS_TOP_MON_SWAP

Bit

10

AUDIO_SYS_TOP_MON_SEL

Bit(s) 15:14

0000239A

AFE Monitor Output Debug Register 0 11

A_FUNC AUDIO Control Register 0 11

10

9

8

7

6

5

D821 4

3

0

CCI_SC CCI_SP CCI_SP CCI_AU CCI_ZE CCI_AU CCI_AU CCI_AU CCI_AU CCI_AU CCI_SC CCI_AUDIO_FIFO_WPT RAMBL CCI_LC CCI_RA LT_SCR LT_SCR D_IDAC RO_PA D_SPLI D_SDM D_SDM D_SDM RAMBL Name D_ANA R ER_CG H_INV ND_EN MB_CL MB_O _TEST_ D_DISA T_TEST _MUTE _MUTE _7BIT_ CK_SEL ER_EN _EN K_ON N EN BLE _EN L R SEL RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type 1 1 0 1 1 0 0 0 0 0 1 0 0 0 0 1 Reset

Bit(s) 15

Name CCI_AUD_ANACK_SEL

14:12 11

CCI_AUDIO_FIFO_WPTR CCI_SCRAMBLER_CG_EN

10

CCI_LCH_INV

9

CCI_RAND_EN

8

CCI_SPLT_SCRMB_CLK_ON

7

CCI_SPLT_SCRMB_ON

6

CCI_AUD_IDAC_TEST_EN

MediaTek Proprietary and Confidential.

Description Analog 13m source inversion option 0: Not invert of AD_AUDDEC_13M_D5N_VCORE (or GPI) 1: Invert audio_fifo write pointer initial value Enables scrambler PA 0: Disable scrambler PA 1: Enable scrambler PA Selects sdm left channel out of phase 0: In-phase with right channel 1: Out-of-phase with right channel Enables scrambler random 0: Not random 1: Random Scrambler clock on 1: On Enables scrambler output 0: Off 1: On Enables scrambler output test

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Page 230 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

5

CCI_ZERO_PAD_DISABLE

4

CCI_AUD_SPLIT_TEST_EN

3

CCI_AUD_SDM_MUTEL

2

CCI_AUD_SDM_MUTER

1

CCI_AUD_SDM_7BIT_SEL

0

CCI_SCRAMBLER_EN

0000239C

Bit(s) 15:8 7:0

AFUNC_AUD_CON1 15

Bit Name Type Reset

0

12

A_FUNC AUDIO Control Register 1

14

13

11

0

AUD_SDM_TEST_L RW 0 0 0 0

AFUNC_AUD_CON2 15

14

13

9

0

8

0

7

0

5

2

1

0

0

AUD_SDM_TEST_R RW 0 0 0 0

0

0

12

4

3

A_FUNC AUDIO Control Register 2 11

10

9

8

7

6

CCI_AU CCI_AU D_DAC D_DAC _ANA_ _ANA_ RSTB_S MUTE EL RW RW

Type Reset

0

Name CCI_AUD_DAC_ANA_MUTE

6

CCI_AUD_DAC_ANA_RSTB_SEL

4

CCI_AUDIO_FIFO_CLKIN_INV

MediaTek Proprietary and Confidential.

0000

6

Description SDM mute test value for left channel SDM mute test value for right channel

Name

Bit(s) 7

10

Name AUD_SDM_TEST_L AUD_SDM_TEST_R

0000239E Bit

Description 0: Normal path 1: From test_in Disables scrambler zero padding 0: Zero padding 1: Disable zero padding Enables splitter test 0: Normal path 1: From test_in ([12:8]/[7:4]/[2:0]) Enables sdm output mute for left channel Controlled by AFUNC_AUD_CON1[15:8] 0: Not control by AFUNC_AUD_CON1 1: Control by AFUNC_AUD_CON1 Enables sdm output mute for right channel Controlled by AFUNC_AUD_CON1[7:0] 0: Not control by AFUNC_AUD_CON1 1: Control by AFUNC_AUD_CON1 Selects splitter 0: From splitter1 1: From splitter3 Enables scrambler 0: Disable 1: Enable

0

5

0000 4

3

2

1

0

CCI_AU CCI_AU CCI_AC CCI_AFI CCI_AC DIO_FI DIO_FI D_MO FO_CLK D_FUN FO_CLK FO_EN DE _PWDB C_RSTB IN_INV ABLE RW

RW

RW

RW

RW

0

0

0

0

0

Description Analog DAC interface mute (RG) control 0: Analog DAC interface input from aud_dac_ana output (normal) 1: Analog DAC interface input from fixed mute patterns Enables aud_dac_ana soft_rstb source selection 0: aud_dac_ana reset by global rstb 1: aud_dac_ana reset by global rstb and cci_acd_func_rstb Selects sdm 6.5M clock phase

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 231 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

3

CCI_AUDIO_FIFO_ENABLE

2

CCI_ACD_MODE

1

CCI_AFIFO_CLK_PWDB

0

CCI_ACD_FUNC_RSTB

000023A0 Bit

Description 0: In-phase 1: Out-of-phase Enables sdm audio_fifo 0: Disable 1: Enable sdm audio_fifo analog FT test mode 0: Normal path 1: Test path from GPI, clock and data will be from GPI. See sdm_testck_src_sel for selection. sdm audio_fifo clock power down bit 0: Power down 1: Power on sdm audio_fifo rstb bit 0: Reset 1: Released

AFUNC_AUD_CON3 15

14

13

12

A_FUNC AUDIO Control Register 3 11

SDM_A NA13 SDM_ANA13M_TESTCK Name M_TES _SRC_SEL TCK_SE L RW RW Type

Reset

0

0

0

0

Bit(s) 15

Name SDM_ANA13M_TESTCK_SEL

14:12

SDM_ANA13M_TESTCK_SRC_SEL

10:8

SDM_TESTCK_SRC_SEL

6:4

DIGMIC_TESTCK_SRC_SEL

MediaTek Proprietary and Confidential.

10

9

8

7

6

5

0000 4

3

2

1

0

SDM_TESTCK_SRC_SEL

DIGMIC_TESTCK_SRC_S EL

DIGMI C_TEST CK_SEL

RW

RW

RW

0

0

0

0

0

0

0

Description Selects SDM testck from GPI 0: Normal path from digital output 1: Testing path from GPI. See the descriptions of sdm_ana13M_testck_src_sel for details. Selects different GPI as SDM testck source 0: test_ck_i[3] 1: test_ck_i[2] 2: test_ck_i[1] 3: test_ck_i[0] 4: test_in_i[0] 5: test_in_i[1] 6: test_in_i[3] 7: test_in_i[5] Selects different GPI as SDM testck source 0: test_ck_i[3] 1: test_ck_i[2] 2: test_ck_i[1] 3: test_ck_i[0] 4: test_in_i[0] 5: test_in_i[1] 6: test_in_i[3] 7: test_in_i[5] Selects different GPI as digmic testck source 0: test_ck_i[3] 1: test_ck_i[2] 2: test_ck_i[1]

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 232 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

0

Name

DIGMIC_TESTCK_SEL

000023A2 Bit

Description 3: test_ck_i[0] 4: test_in_i[2] 5: test_in_i[4] 6: test_in_i[6] 7: test_in_i[7] Selects digmic testck from GPI 0: Normal path from digital output 1: Testing path from GPI. See the descriptions of digmic_testck_src_sel for details.

AFUNC_AUD_CON4 15

14

13

12

A_FUNC AUDIO Control Register 4 11

Type Reset

8

RW 0

Name UL_FIFO_WCLK_INV

6

UL_FIFO_DIGMIC_WDATA_TESTSRC_ SEL

5

UL_FIFO_WDATA_TESTEN

4

UL_FIFO_WDATA_TESTSRC_SEL

3

UL_FIFO_WCLK_6P5M_TESTCK_SEL

2:0

9

UL_FIF O_WCL K_INV

Name

Bit(s) 8

10

UL_FIFO_WCLK_6P5M_TESTCK_SRC_ SEL

MediaTek Proprietary and Confidential.

7

6

5

0000 4

3

2

1

0

UL_FIF UL_FIF UL_FIF O_DIG UL_FIF O_WCL O_WD MIC_W O_WD K_6P5 UL_FIFO_WCLK_6P5M_ ATA_TE DATA_ ATA_TE M_TES TESTCK_SRC_SEL STSRC_ TESTSR STEN TCK_SE SEL C_SEL L RW RW RW RW RW 0

0

0

0

0

0

0

Description Selects to invert UL FIFO wclk 0: Not invert 1: Invert UL FIFO wclk Selects UL FIFO digmic wdata from GPI (Test_in[1:0]) or tri-gen ch1: Test_in[1] ch2: Test_in[0] 0: Testing path from test input GPI, i.e. left channel ch1 = test_in[1]; right channel ch2 = test_in[0] 1: Testing path from built-in tri-gen, ch1 uses tri_out[1], ch2 uses tri_out[0] Selects UL FIFO wdata from others 0: Normal path from analog output 1: Testing path from test input. See the descriptions of ul_fifo_wdata_testsrc_sel for details. Enables GPI as UL FIFO write testck source 0: Test input from GPI, i.e. left channel ch1[4:0] = test_in[4:0]; right channel ch2[4:0] = test_in[4:0] 1: Test input from tri-gen; both ch1 and ch2 use the same inputs from trigen. Enables GPI as UL FIFO write testck source 0: Normal path from analog 6p5M 1: From testck described in ul_fifo_wclk_6p5m_testck_src_sel Selects different GPI as UL FIFO write testck source 0: test_ck_i[2] 1: test_ck_i[2] 2: test_ck_i[1] 3: test_ck_i[0] 4: test_in_i[5] 5: test_in_i[6] 6: test_in_i[7] 7: test_in_i[0]

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 233 of 1067

MT6359 PMIC Datasheet Confidential A

000023A4

Bit(s) 15:8 7:0

AFUNC_AUD_CON5 15

Bit Name Type Reset

0

Bit(s) 15:12 11:8 7:6 5:4 3

12

14

13

12

9

0

8

0

5

0000

7

6

4

3

2

0

R_AUD_DAC_NEG_LARGE_MONO RW 0 0 0 0 0

0

0

0

11

10

0

0

Name R_AUD_DAC_POS_SMALL_MONO R_AUD_DAC_NEG_SMALL_MONO R_AUD_DAC_POS_TINY_MONO R_AUD_DAC_NEG_TINY_MONO R_AUD_DAC_MONO_SEL

R_AUD_DAC_SW_RSTB

000023A8

14

13

12

9

8

0

0

Type Reset

11

10

RW 0

Name UL2_DIGMIC_TESTCK_SRC_SEL

MediaTek Proprietary and Confidential.

0

7

6

5

0001 4

3

2

0

0

0

0

1

0

0

R_AUD R_AUD _DAC_ _DAC_ 3TH_SE SW_RS L TB RW RW

0

0

A_FUNC AUDIO Control Register 7 9

8

UL2_DI UL2_FI UL2_DIGMIC_TESTCK_S GMIC_ FO_WC RC_SEL TESTCK LK_INV _SEL

Name

0

1

Description pos_small to DAC neg_small to DAC pos_tiny to DAC neg_tiny to DAC Uses mono register value to test DAC 0: Not use mono register value 1: Use mono register value Selects 3rd aud dac channel 0: LCH 1: RCH DAC sgen sync soft reset 0: Reset dac sgen 1: Not reset dac sgen

AFUNC_AUD_CON7 15

0

A_FUNC AUDIO Control Register 6

0

0

1

Description pos_lareg to DAC neg_lareg to DAC

R_AUD R_AUD_DAC_P R_AUD_DAC_N R_AUD_DAC_POS_SMALL_MO R_AUD_DAC_NEG_SMALL_MO _DAC_ OS_TINY_MON EG_TINY_MON NO NO MONO O O _SEL RW RW RW RW RW

R_AUD_DAC_3TH_SEL

Bit(s) 12:10

10

R_AUD_DAC_POS_LARGE_MONO RW 0 0 0 0

1

Bit

A_FUNC AUDIO Control Register 5 11

AFUNC_AUD_CON6 15

Bit

Type Reset

0

13

Name R_AUD_DAC_POS_LARGE_MONO R_AUD_DAC_NEG_LARGE_MONO

000023A6

Name

14

0

RW

RW

0

0

7

6

5

0000 4

3

2

1

0

UL2_FI UL2_FI UL2_FI FO_DIG UL2_FI FO_WC FO_WD MIC_W FO_WD LK_6P5 UL2_FIFO_WCLK_6P5M ATA_TE DATA_ ATA_TE M_TES _TESTCK_SRC_SEL STSRC_ TESTSR STEN TCK_SE SEL C_SEL L RW RW RW RW RW 0

0

0

0

0

0

0

Description Selects different GPI as digmic testck source 0: test_ck_i[3] 1: test_ck_i[2] 2: test_ck_i[1] 3: test_ck_i[0]

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Page 234 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

9

UL2_DIGMIC_TESTCK_SEL

8

UL2_FIFO_WCLK_INV

6

UL2_FIFO_DIGMIC_WDATA_TESTSRC _SEL

5

UL2_FIFO_WDATA_TESTEN

4

UL2_FIFO_WDATA_TESTSRC_SEL

3

UL2_FIFO_WCLK_6P5M_TESTCK_SEL

2:0

UL2_FIFO_WCLK_6P5M_TESTCK_SRC _SEL

000023AA Bit

Description 4: test_in_i[2] 5: test_in_i[4] 6: test_in_i[6] 7: test_in_i[7] Selects digmic testck from GPI 0: Normal path from digital output 1: Testing path from GPI. See descriptions of digmic_testck_src_sel for details. Selects to invert ul2 FIFO wclk 0: Not invert 1: Invert ul fifo wclk Selects ul2 FIFO digmic wdata from GPI (Test_in[1:0]) or tri-gen: ch1: Test_in[1] ch2: Test_in[0] 0: Testing path from test input GPI, i.e. left channel ch1 = test_in[1]; right channel ch2 = test_in[0] 1: Testing path from built-in tri-gen, ch1 uses tri_out[1], ch2 uses tri_out[0] Selects ul2 FIFO wdata from others 0: Normal path from analog output 1: Testing path from test input. See descriptions of ul_fifo_wdata_testsrc_sel for details. Enables GPI as ul2 FIFO write testck source 0: Test input from GPI, i.e. left channel ch1[4:0] = test_in[4:0]; right channel ch2[4:0] = test_in[4:0] 1: Test input from tri-gen, both ch1 and ch2 use the same inputs from trigen. Enables GPI as ul2 FIFO write testck source 0: Normal path from analog 6p5M 1: From testck described in ul_fifo_wclk_6p5m_testck_src_sel Selects different GPI as ul2 FIFO write testck source 0: test_ck_i[2] 1: test_ck_i[2] 2: test_ck_i[1] 3: test_ck_i[0] 4: test_in_i[5] 5: test_in_i[6] 6: test_in_i[7] 7: test_in_i[0]

AFUNC_AUD_CON8 15

14

13

12

A_FUNC AUDIO Control Register 8 11

10

9

8

SPLITTE SPLITTE R2_DIT R1_DIT HER_E HER_E N N RW RW

Name Type Reset

0

Bit(s) 9

Name SPLITTER2_DITHER_EN

8

SPLITTER1_DITHER_EN

MediaTek Proprietary and Confidential.

0

7

6

5

0000 4

SPLITTER2_DITHER_GAIN

3

2

0

0

SPLITTER1_DITHER_GAIN

RW 0

1

RW 0

0

0

0

0

0

Description Enables splitter2 dither 0: Disable 1: Enable Enables splitter1 dither

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 235 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

7:4 3:0

Name

SPLITTER2_DITHER_GAIN SPLITTER1_DITHER_GAIN

000023AC Bit

Description 0: Disable 1: Enable Splitter2 dither gain Splitter1 dither gain

AFUNC_AUD_CON9 15

14

13

12

A_FUNC AUDIO Control Register 10 11

10

9

CCI_SC CCI_AU RAMBL CCI_LC CCI_RA D_ANA CCI_AUDIO_FIFO_WPT ER_CG H_INV_ ND_EN Name CK_SEL R_2ND _EN_2 2ND _2ND _2ND ND RW RW RW RW RW Type 1 1 0 1 1 0 0 Reset

Bit(s) 15

Name CCI_AUD_ANACK_SEL_2ND

14:12 11

CCI_AUDIO_FIFO_WPTR_2ND CCI_SCRAMBLER_CG_EN_2ND

10

CCI_LCH_INV_2ND

9

CCI_RAND_EN_2ND

8

CCI_SPLT_SCRMB_CLK_ON_2ND

7

CCI_SPLT_SCRMB_ON_2ND

6

CCI_AUD_IDAC_TEST_EN_2ND

5

CCI_ZERO_PAD_DISABLE_2ND

4

CCI_AUD_SPLIT_TEST_EN_2ND

3

CCI_AUD_SDM_MUTEL_2ND

2

CCI_AUD_SDM_MUTER_2ND

1

CCI_AUD_SDM_7BIT_SEL_2ND

MediaTek Proprietary and Confidential.

8 CCI_SP LT_SCR MB_CL K_ON_ 2ND RW 0

7

6

5

D821 4

3

2

1

0

CCI_AU CCI_ZE CCI_AU CCI_AU CCI_SP CCI_AU CCI_AU CCI_SC D_IDAC RO_PA D_SPLI D_SDM LT_SCR D_SDM D_SDM RAMBL _TEST_ D_DISA T_TEST _7BIT_ MB_O _MUTE _MUTE ER_EN EN_2N BLE_2N _EN_2 SEL_2N N_2ND L_2ND R_2ND _2ND D D ND D RW RW RW RW RW RW RW RW 0 0 1 0 0 0 0 1

Description Analog 13m source inversion option 0: Not invert AD_AUDDEC_13M_D5N_VCORE (or GPI) 1: Invert audio_fifo write pointer initial value Enables scrambler PA 0: Disable scrambler PA 1: Enable scrambler PA Selects SDM left channel out of phase 0: In-phase with right channel 1: Out-of-phase with right channel Enables scrambler random 0: Not random 1: Random Scrambler clock on 0: Off 1: On Enables scrambler output 0: Off 1: On Enables scrambler output test 0: Normal path 1: From test_in Disables scrambler zero padding 0: Zero padding 1: Disable zero padding Enables splitter test 0: Normal path 1: From test_in ([12:8]/[7:4]/[2:0]) Enables SDM output mute for left channel Controlled by AFUNC_AUD_CON10[15:8] 0: Not control by AFUNC_AUD_CON10 1: Control by AFUNC_AUD_CON10 Enables SDM output mute for right channel Controlled by AFUNC_AUD_CON10[7:0] 0: Not control by AFUNC_AUD_CON10 1: Control by AFUNC_AUD_CON10 Selects splitter

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Page 236 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

0

Name

CCI_SCRAMBLER_EN_2ND

000023AE

AFUNC_AUD_CON10 15

Bit Name Type Reset Bit(s) 15:8 7:0

0

12

A_FUNC AUDIO Control Register 11

14

13

0

AUD_SDM_TEST_L_2ND RW 0 0 0 0

11

AFUNC_AUD_CON11 15

14

13

12

9

0

8

0

7

0

6

5

2

1

0

0

AUD_SDM_TEST_R_2ND RW 0 0 0 0

0

0

4

3

A_FUNC AUDIO Control Register 12 11

10

9

8

7

6

CCI_AU CCI_AU D_DAC D_DAC _ANA_ _ANA_ RSTB_S MUTE_ EL_2N 2ND D RW RW

Type Reset

0

Name CCI_AUD_DAC_ANA_MUTE_2ND

6

CCI_AUD_DAC_ANA_RSTB_SEL_2ND

4

CCI_AUDIO_FIFO_CLKIN_INV_2ND

3

CCI_AUDIO_FIFO_ENABLE_2ND

2

CCI_ACD_MODE_2ND

1

CCI_AFIFO_CLK_PWDB_2ND

0

CCI_ACD_FUNC_RSTB_2ND

MediaTek Proprietary and Confidential.

0000

Description SDM mute test value for left channel SDM mute test value for right channel

Name

Bit(s) 7

10

Name AUD_SDM_TEST_L_2ND AUD_SDM_TEST_R_2ND

000023B0 Bit

Description 0: From splitter1 1: From splitter3 Enables scrambler 0: Disable 1: Enable

0

5

0000 4

3

2

1

0

CCI_AU CCI_AU CCI_AC CCI_AFI CCI_AC DIO_FI DIO_FI D_MO FO_CLK D_FUN FO_CLK FO_EN DE_2N _PWDB C_RSTB IN_INV ABLE_2 D _2ND _2ND _2ND ND RW

RW

RW

RW

RW

0

0

0

0

0

Description Analog DAC interface mute (RG) control 0: Analog DAC interface input from aud_dac_ana output (normal) 1: Analog DAC interface input from fixed mute patterns. Enables aud_dac_ana soft_rstb source selection 0: aud_dac_ana reset by global rstb 1: aud_dac_ana reset by global rstb and cci_acd_func_rstb Selects SDM 6.5M clock phase 0: In-phase 1: Out-of-phase Enables SDM audio_fifo 0: Disable 1: Enable sdm audio_fifo analog FT test mode 0: Normal path 1: Test path from GPI, clock and data will be from GPI. See sdm_testck_src_sel for selection. SDM audio_fifo clock power down bit 0: Power down 1: Power on SDM audio_fifo rstb bit 0: Reset 1: Released

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 237 of 1067

MT6359 PMIC Datasheet Confidential A 000023B2

AFUNC_AUD_CON12 15

Bit

14

13

12

A_FUNC AUDIO Control Register 18 11

10

Type Reset

0

Bit(s) 9

Name SPLITTER2_DITHER_EN_2ND

8

SPLITTER1_DITHER_EN_2ND

AFUNC_AUD_MON0 15

Bit Name Type Reset

0

0

Type Reset

0

13

0

12

11

AUD_SCR_OUT_L RO 0 0

10

0

5

0000 4

3

2

1

0

13

0

AUD_SCR_OUT_L_2ND RO 0 0 0 0

14

13

12

11

12

11

0

0

0

0

0

0

9

0

8

0

7

0

6

0

5

0

0000 4

3

AUD_SCR_OUT_R RO 0 0

10

9

0

8

0

7

2

1

0

0

0

0

0

0000

6

5

4

2

1

0

0

AUD_SCR_OUT_R_2ND RO 0 0 0 0

0

0

3

Analog Monitor Register 0 10

9

8

7

6

0000 5

4

RGS_AUDRCTUNE1READ

CK RU

MediaTek Proprietary and Confidential.

0

Description Scrambler/splitter debug output to read bus Scrambler/splitter debug output to read bus

ASYNC _TEST_

0

0

A_FUNC AUDIO Monitor Register 1

14

AUDRC_TUNE_MON0 15

0

Description Scrambler/splitter debug output to read bus Scrambler/splitter debug output to read bus

Name AUD_SCR_OUT_L_2ND AUD_SCR_OUT_R_2ND

000023B8

Name

14

AFUNC_AUD_MON1 15

Bit Name Type Reset

Bit

6

A_FUNC AUDIO Monitor Register 0

Name AUD_SCR_OUT_L AUD_SCR_OUT_R

000023B6

Bit(s) 15:8 7:0

7

Description Enables splitter2 dither 0: Disable 1: Enable Enables splitter1 dither 0: Disable 1: Enable Splitter2 dither gain Splitter1 dither gain

SPLITTER2_DITHER_GAIN_2ND SPLITTER1_DITHER_GAIN_2ND

000023B4

Bit(s) 15:8 7:0

8

SPLITTE SPLITTE R2_DIT R1_DIT SPLITTER2_DITHER_GAIN_2ND SPLITTER1_DITHER_GAIN_2ND HER_E HER_E N_2ND N_2ND RW RW RW RW

Name

7:4 3:0

9

3

0

0

1

0

RGS_AUDRCTUNE0READ

RU 0

2

RU 0

0

0

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

0

0

0

0

Page 238 of 1067

CH H data

MT6359 PMIC Datasheet Confidential A Bit(s) 15 12:8 4:0

Name ASYNC_TEST_OUT_BCK RGS_AUDRCTUNE1READ RGS_AUDRCTUNE0READ

000023D8 Bit

Bit(s) 15:12

AUDIOEN RC TUNE OUTPUT TO READ for 1 channel AUDIOEN RC TUNE OUTPUT TO READ for 0 channel

AFE_SGEN_CFG0 15

Name Type Reset

Description

14

13

12

RW 0

0

10

9

8

0000 7

6

5

4

3

2

1

0

R_AUD R_AUD R_AUD R_AUD C_DAC C_MUT _SDM_ _SDM_ _SDM_ _SDM_ _EN_CT E_SW_ MUTE_ MUTE_ MUTE_ MUTE_ L CTL L R L_2ND R_2ND RW RW RW RW RW RW

C_AMP_DIV_CH1_CTL

0

AFE SGEN CON0 11

0

Name C_AMP_DIV_CH1_CTL

7

C_DAC_EN_CTL

6

C_MUTE_SW_CTL

5

R_AUD_SDM_MUTE_L

4

R_AUD_SDM_MUTE_R

3

R_AUD_SDM_MUTE_L_2ND

0

0

0

0

0

0

Description Amplitude setting of channel 1 (SGEN) 0: 0dB full scale 1: -6dB 2: -12dB 3: -18dB 4: -24dB 5: -30dB 6: -36dB 7: -42dB 8: -48dB 9: -54dB 10: -60dB 11: -66dB 12: -72dB 13: -78dB 14: -84dB 15: -90dB Makes voice DAC output the test sine wave Configures signal generator (SGEN). 0: Disable sine waves output 1: Voice DAC inputs are sine waves Mutes switch (SGEN) 0: Turn on sine wave output in this test mode 1: Mute sine wave output Mutes aud_sdm lch data 0: Not mute 1: Mute aud_sdm lch Mutes aud_sdm rch data 0: Not mute 1: Mute aud_sdm RCH Mutes aud_sdm_2nd LCH data 0: Not mute

2 0: Not mute 1: Mute aud_sdm_2nd RCH

MediaTek Proprietary and Confidential.

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Page 239 of 1067

MT6359 PMIC Datasheet Confidential A 000023DA

AFE_SGEN_CFG1 15

Bit

14

13

12

AFE SGEN CON1 11

10

9

8

0001 7

6

5

4

C_SGE C_SGE N_RCH N_RCH Name _INV_5 _INV_8 BIT BIT RW RW Type

Reset Bit(s) 15 14 4:0

0

14

0

13

12

11

0

10

Name RG_UL_ASYNC_FIFO_SOFT_RST_EN

RG_UL_ASYNC_FIFO_SOFT_RST

1

RG_AMIC_UL_ADC_CLK_SEL

9

8

7

6

5

4

3

2

1

14

13

12

11

RW

1

0

Description Selects UL async FIFO soft reset 0: UL async FIFO uses global reset. 1: UL async FIFO uses soft reset. UL soft reset control 0: UL FIFO soft reset 1: Normal Selects ADC 0/1 channel latch clk 0: Select ana_ch0 ck 1: Select ana_ch1 ck

10

9

8

7

6

0010 5

RG_UL 2_ASY NC_FIF O_SOF T_RST_ EN RW

Name

Type Reset

0

Name RG_UL2_ASYNC_FIFO_SOFT_RST_EN

MediaTek Proprietary and Confidential.

0

RG_AM IC_UL_ ADC_C LK_SEL

AFE_ADC_ASYNC_FIFO_CFG1 AFE_ADC_SYNC_FIFO_CFG1 15

1

0010

0

4

Bit(s) 5

0

Description Inverts RCH sgen 5-bit data output Inverts RCH sgen 8-bit data output Frequency setting of channel 1 1X~15X for voice, 1X~31X for audio Frequency = Sampling rate/64*FREQ_DIV (SGEN) Sample rate: UL (8K/16K/32K -> 64K; 48K -> 96K); DL (8xFS)

Type Reset

Bit

0

RG_UL RG_UL _ASYN _ASYN C_FIFO C_FIFO _SOFT_ _SOFT_ RST_EN RST RW RW

000023DE

0

RW

0

Name

Bit(s) 5

1

AFE_ADC_ASYNC_FIFO_CFG AFE_ADC_SYNC_FIFO_CFG 15

Bit

2

C_FREQ_DIV_CH1_CTL

Name C_SGEN_RCH_INV_5BIT C_SGEN_RCH_INV_8BIT C_FREQ_DIV_CH1_CTL

000023DC

3

4

3

2

1

0

RG_UL 2_ASY NC_FIF O_SOF T_RST RW 1

Description Selects UL2 async FIFO soft reset 0: UL2 async FIFO uses global reset. 1: UL2 async FIFO uses soft reset.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 240 of 1067

se

MT6359 PMIC Datasheet Confidential A Bit(s) 4

Name RG_UL2_ASYNC_FIFO_SOFT_RST

000023E0

AFE_DCCLK_CFG0 15

Bit

14

13

12

AFE_DCCLK_CFG0 11

Name

4 3:2

0

0

0

0

0

DCCLK_GEN_ON

000023E2

9

8

7

0FE2 6

5

AFE_DCCLK_CFG1 15

14

13

1

1

1

1

1

4

3

2

1

0

DCCLK DCCLK_ DCCLK_REF_CK DCCLK_ _GEN_ INV _SEL PDN ON RW RW RW RW 0 0 0 1 0

Description dcclk divider: dcclk = 13M(12.854M)/(div + 1) dcclk inverter Selects dcclk reference clock 00: Normal 26M/2 01: Vow 12.854M dcclk power down control 0: dcclk output 1: dcclk power down Enables dcclk generation 0: Disable 1: Enable

12

AFE_DCCLK_CFG1 11

10

9

8

7

DCCLK_ RESYN RESYNC_SRC_S RESYN C_SRC_ EL C_BYP CK_INV ASS RW RW RW

Name Type Reset

9 8

RW 1

DCCLK_INV DCCLK_REF_CK_SEL

DCCLK_PDN

Bit(s) 11:10

1

Name DCCLK_DIV

1

Bit

10 DCCLK_DIV

Type Reset Bit(s) 15:5

Description UL2 soft reset control 0: UL2 FIFO soft reset 1: Normal

0

Name RESYNC_SRC_SEL

RESYNC_SRC_CK_INV DCCLK_RESYNC_BYPASS

0

0

1

0100 6

5

4

3

2

1

0

DCCLK_PHASE_SEL RW 0

0

0

0

Description Selects dcclk resync clock 00: adcsync_clk 01: vow 12.854M 10: buck_oscclk 11: 26m clock dcclk resync clock inverter dcclk bypass resync 0: Resync 1: Bypass resync

7:4

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Page 241 of 1067

MT6359 PMIC Datasheet Confidential A 000023F8

AFE_CHOP_CFG0 15

Bit

14

13

12

AFE_CHOP_CFG0 11

10

9

8

Name

6

5

4

2

1

Name RG_CHOP_DIV_SEL

0

RG_CHOP_DIV_EN

000023FA

14

13

12

11

Type Reset Name RG_ADDA6_EN_SEL

9:8

RG_ADDA6_CH1_SEL

4

RG_ADDA_EN_SEL

3:2

RG_ADDA_CH2_SEL

1:0

RG_ADDA_CH1_SEL

0000240A

14

13

9

8

7

6

5

4

0

MediaTek Proprietary and Confidential.

0

3

2

1

0

RG_AD RG_ADDA_CH2 RG_ADDA_CH1 DA_EN _SEL _SEL _SEL RW RW RW

0

0

0

1

0

0

Description Selects input en for MTKAIF MISO2 0: ADDA FS 1: ADDA6 FS Selects input source for MTKAIF MISO2 0: ADDA CH1 1: ADDA CH2 2: ADDA6 CH1 3: ADDA6 CH2 Selects input en for MTKAIF MISO0&MISO1 0: ADDA FS 1: ADDA6 FS Selects input source for MTKAIF MISO0 0: ADDA CH1 1: ADDA CH2 2: ADDA6 CH1 3: ADDA6 CH2 Selects input source for MTKAIF MISO1 0: ADDA CH1 1: ADDA CH2 2: ADDA6 CH1 3: ADDA6 CH2

12

11

AFE VOW Top Control for Dual Channels 10

9

8

7

6

5

4

MAIN_ VOW_L VOW_I VOW_S VOW_I PDN_V VOW_DMIC_C DMIC_ VOW_CIC_MO OOP_B NTR_S DM_3_ NTR_S Name OW K_SEL CK_VO DE_SEL ACK_M W_MO LEVEL W_VAL W_SEL ODE DE RW RW RW RW RW RW RW RW Type 1

0

1E04

RW 1

AFE_VOW_TOP_CON0 15

0

RG_ADDA6_CH 1_SEL

1

Bit(s) 12

1

AFE_MTKAIF_MUX_CFG 10

RG_AD DA6_E N_SEL RW

Name

0

Description Chopping clock divider (26M/2)/(2^N), N = 0~31 Enables chopping clock divider

AFE_MTKAIF_MUX_CFG 15

Bit

1

0 RG_CH OP_DI V_EN RW

RW 1

Bit(s) 8:4

Reset

3

RG_CHOP_DIV_SEL

Type Reset

Bit

01A0 7

0

0

0

0

0

0

0

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

8000 3

2

1

0

RG_VOW_INTR _MODE_SEL RW 0

0

Page 242 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 15

Name PDN_VOW

14:13

VOW_DMIC_CK_SEL

12

MAIN_DMIC_CK_VOW_SEL

11:10

VOW_CIC_MODE_SEL

9

VOW_SDM_3_LEVEL

8

VOW_LOOP_BACK_MODE

7

VOW_INTR_SW_MODE

6 3:2

VOW_INTR_SW_VAL RG_VOW_INTR_MODE_SEL

0000240C Bit

Name Type Reset

Description Powers down VOW source clock 0: Normal 1: Power down VOW clk Selects DMIC clock rate 00: 1.625M rate 01: 812.5K rate 10: 541.67K rate Uses normal or VOW DMIC clock 0: Normal digital mic clock (1.625m/3.25m) 1: Vow digital mic clock Selects vow cic mode 00: Down 102x 01: Down 102x 10: Down 51x 11: Down 34x Selects SDM 3-level mode (digital MIC data path), first priority choice 0: De-select SDM 3-level mode 1: Select SDM 3-level mode Vow loopback test mode 0: Normal path 1: Source from dl SDM output Enables vow intr software mode 0: HW mode 1: SW mode Vow intr software mode value Selects vow interrupt mode 00: vow_intr equals vow_intr_ch1 or vow_intr_ch2 01: vow_intr equals vow_intr_ch1 and vow_intr_ch2 10: vow_intr eqauls vow_intr_ch1 11: vow_intr equals vow_intr_ch2

AFE_VOW_TOP_CON1 15

14

13

12

11

VOW_ VOW_ VOW_ VOW_ VOW_ DMIC0 DIGMI CK_DIV ADC_C CK_PD _CK_P C_ON_ _RST_C K_PDN N_CH1 DN CH1 H1 _CH1 RW 0

RW 0

RW 0

RW 0

Bit(s) 15

Name VOW_DMIC0_CK_PDN

14

VOW_DIGMIC_ON_CH1

13

VOW_CK_DIV_RST_CH1

12

VOW_ADC_CK_PDN_CH1

MediaTek Proprietary and Confidential.

RW 0

AFE VOW Top Control for Left Channel 10

9

8

7

6

5

VOW_DIGMIC_CK_PHASE_SEL_CH1

VOW_ ADC_C LK_INV _CH1

RW 0

RW 0

0

0

0

0

4

0000 3

2

1

0

VOW_I S_N_V SAMPL NTR_S VOW_I VOW_ ALUE_ E_BASE OURCE NTR_CL ON_CH RST_CH _MODE _SEL_C R_CH1 1 1 _CH1 H1 RW RW RW RW RW 0 0 0 0 0

Description Powers down vow digital mic clock for left channel 0: Power on 1: Power down Vow dmic or amic switcher for left channel 0: Analog mic 1: Digital mic Vow digmic output clock (to analog) clock division circuit reset bit for left channel 0: Not reset clock divider 1: Reset clock divider VOW ADC clock gated for left channel

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 243 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

11

10:6 5 4

Name

VOW_CK_PDN_CH1

VOW_DIGMIC_CK_PHASE_SEL_CH1 VOW_ADC_CLK_INV_CH1 VOW_INTR_SOURCE_SEL_CH1

3 2

VOW_INTR_CLR_CH1 S_N_VALUE_RST_CH1

1

SAMPLE_BASE_MODE_CH1

0

VOW_ON_CH1

0000240E Bit

AFE_VOW_TOP_CON2 15

14

13

12

11

VOW_ VOW_ VOW_ VOW_ VOW_ DMIC1 DIGMI CK_DIV ADC_C

Name _CK_P C_ON_ _RST_C K_PDN CK_PD Type Reset

DN

CH2

H2

_CH2

RW 0

RW 0

RW 0

RW 0

Bit(s) 15

Name VOW_DMIC1_CK_PDN

14

VOW_DIGMIC_ON_CH2

13

VOW_CK_DIV_RST_CH2

12

VOW_ADC_CK_PDN_CH2

11

VOW_CK_PDN_CH2

10:6 5 4

Description 0: Turn on VOW ADC clock for left channel 1: Turn off VOW ADC clock for left channel VOW clock gated for left channel 0: Turn on VOW clock for left channel 1: Turn off VOW clock for left channel Selects vow digmic input phase latch for left channel Inverts VOW ADC clock for left channel Selects vow interrupt source for left channel 0: Bias base IRQ source 1: No bias IRQ source Vow interrupt clear for left channel S, N value reset for left channel 0: Keep the last N 1: Reset to 'h64 Selects vow base mode for left channel 0: Window base 1: Sample base Powers on VOW for left channel 0: Disable VOW 1: Enable VOW

9

8

7

6

RW 0

5

VOW_DIGMIC_CK_PHASE_SEL_CH2

VOW_ ADC_C LK_INV _CH2

RW 0

RW 0

N_CH2

VOW_DIGMIC_CK_PHASE_SEL_CH2 VOW_ADC_CLK_INV_CH2 VOW_INTR_SOURCE_SEL_CH2

MediaTek Proprietary and Confidential.

AFE VOW Top Control for Right Channel 10

0

0

0

0

4

0000 3

2

1

0

VOW_I S_N_V SAMPL NTR_S VOW_I VOW_ ALUE_ E_BASE OURCE NTR_CL ON_CH RST_CH _MODE _SEL_C R_CH2 2 2 _CH2 H2 RW RW RW RW RW 0 0 0 0 0

Description Powers down vow digital mic clock for right channel 0: Power on 1: Power down Vow dmic or amic switcher for left channel 0: Analog mic 1: Digital mic Vow digmic output clock (to analog) clock division circuit reset bit for right channel 0: Not reset clock divider 1: Reset clock divider VOW ADC clock gated for right channel 0: Turn on VOW ADC clock for right channel 1: Turn off VOW ADC clock for right channel VOW clock gated for right channel 0: Turn on VOW clock for right channel 1: Turn off VOW clock for right channel Vow digmic 8 input phase latch selections for right channel Inverts VOW ADC clock for right channel Selects vow interrupt source for right channel 0: Bias base IRQ source 1: No bias IRQ source

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 244 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 3 2

Name VOW_INTR_CLR_CH2 S_N_VALUE_RST_CH2

1

SAMPLE_BASE_MODE_CH2

0

VOW_ON_CH2

00002410 Bit

Description Clears vow interrupt for right channel S, N value reset for right channel 0: Keep the last N 1: Reset to 'h64 Selects vow base mode for right channel 0: Window base 1: Sample base Powers on VOW for right channel 0: Disable VOW 1: Enable VOW

AFE_VOW_TOP_CON3 15

14

13

12

11

VOW_ VOW_ VOW_ADC_TESTCK_SR ADC_T Name TXIF_S C_SEL ESTCK_ CK_INV SEL

Type Reset Bit(s) 15 14:12

RW 0

RW 0

0

9

VOW_TXIF_MONO

8:4 0

0

VOW_P2_SNRDET_AUTO_PDN

8

VOW_T XIF_M ONO RW

VOW_TXIF_SCK_DIV

MediaTek Proprietary and Confidential.

9

0

Name VOW_TXIF_SCK_INV VOW_ADC_TESTCK_SRC_SEL

VOW_ADC_TESTCK_SEL

10

RW 0

11

AFE Vow Top Control for Test Clock and MTKAIF Settings 7

6

5

4

RW 0

1

1

2

1

0 VOW_ P2_SN RDET_ AUTO_ PDN RW

VOW_TXIF_SCK_DIV

0

3

0060

0

0

Description Inverts vow txif sck Selects different GPI as vow adc testck source 0: test_ck_i[2] 1: test_ck_i[2] 2: test_ck_i[1] 3: test_ck_i[0] 4: test_in_i[5] 5: test_in_i[6] 6: test_in_i[7] 7: test_in_i[0] Selects vow adc testck from GPI 0: Normal path from digital output 1: Testing path from GPI. See descriptions of vow_adc_testck_src_sel for details. Vow mtkaif mono transmit configure 0: Stereo 1: Mono Vow txif sck divider txif sck = vow_mck/(div*2) Switch of SNRDET automatic power down 0: Enable auto power down SNRDET 1: Disable auto power down SNRDET

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 245 of 1067

MT6359 PMIC Datasheet Confidential A 00002414

AFE_VOW_TOP_MON0 15

Bit

14

13

12

11

AFE Vow Top Monitor Out 10

9

8

7

6

0000 5

4

3

2

1

Name Type Reset Bit(s) 0

0

Name VOW_INTR_FLAG_CH2

00002416

0

0

0

11

0

AFE Vow vad Configurations 0 10

0

14

0

0

14

0

13

0

12

0

11

0

0

0

14

0

Name TIMERINI_CH2

MediaTek Proprietary and Confidential.

7

AMPREF_CH1 RW 0 0

0000

6

5

4

3

2

1

0

0

0

0

0

0

0

0

9

0

8

7

AMPREF_CH2 RW 0 0

0000

6

5

4

3

2

1

0

0

0

0

0

0

0

0

Description Vow bias remove reference value for right channel

13

0

12

0

11

0

AFE Vow vad Configurations 2 10

1

9

0

8

7

TIMERINI_CH1 RW 0 0

0400

6

5

4

3

2

1

0

0

0

0

0

0

0

0

Description A, B timeout initial value for left channel

AFE_VOW_VAD_CFG3 15

0

8

AFE Vow vad Configurations 1 10

Name TIMERINI_CH1

0000241C

9

Description Vow bias remove reference value for left channel

AFE_VOW_VAD_CFG2 15

Bit Name Type Reset

Bit(s) 15:0

0

12

Name AMPREF_CH2

0000241A

Bit Name Type Reset

0

13

AFE_VOW_VAD_CFG1 15

Bit Name Type Reset

Bit(s) 15:0

14

Name AMPREF_CH1

00002418

Bit(s) 15:0

Description Vow interrupt flag for read out for left channel

AFE_VOW_VAD_CFG0 15

Bit Name Type Reset Bit(s) 15:0

0 VOW_I NTR_FL AG_CH 2 RO

13

0

12

0

11

0

AFE Vow vad Configurations 3 10

1

9

0

8

7

TIMERINI_CH2 RW 0 0

0400

6

5

4

3

2

1

0

0

0

0

0

0

0

0

Description A, B timeout initial value for right channel

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 246 of 1067

MT6359 PMIC Datasheet Confidential A 0000241E

AFE_VOW_VAD_CFG4 15

Bit

VOW_I RQ_LA Name TCH_S NR_EN _CH1 RW Type

Reset Bit(s) 15 14:12 10:8 6:4 2:0

1

VOW_I RQ_LA Name TCH_S NR_EN _CH2 RW Type

Reset

1

11

B_DEFAULT_CH1

AFE Vow vad Configurations 4 10

RW 0

14

8

7

6

0

0

13

12

11

1

5

A323 4

3

2

B_INI_CH1

RW

1

0

1

RW 0

0

1

2

1

AFE Vow vad Configurations 5 10

9

8

7

6

5

3

A_DEFAULT_CH2

B_INI_CH2

A_INI_CH2

RW

RW

RW

RW

1

0

14

13

12

K_BETA_RISE_CH1 RW 1 0 1 0

0

Name K_BETA_RISE_CH1 K_BETA_FALL_CH1 K_ALPHA_RISE_CH1 K_ALPHA_FALL_CH1

MediaTek Proprietary and Confidential.

11

1

A323 4

B_DEFAULT_CH2

0

0

A_INI_CH1

RW 1

1

Description Latch S and N value when IRQ trigger for left channel B default value for left channel A default value for left channel B initial value for left channel A initial value for left channel

1

1

0

1

0

0

1

0

1

Description Latch S and N value when IRQ trigger for right channel B default value for right channel A default value for right channel B initial value for right channel A initial value for right channel

AFE_VOW_VAD_CFG6 15

9

A_DEFAULT_CH1

Name VOW_IRQ_LATCH_SNR_EN_CH2 B_DEFAULT_CH2 A_DEFAULT_CH2 B_INI_CH2 A_INI_CH2

00002422

Bit(s) 15:12 11:8 7:4 3:0

12

AFE_VOW_VAD_CFG5 15

Bit

Bit Name Type Reset

13

Name VOW_IRQ_LATCH_SNR_EN_CH1 B_DEFAULT_CH1 A_DEFAULT_CH1 B_INI_CH1 A_INI_CH1

00002420

Bit(s) 15 14:12 10:8 6:4 2:0

14

AFE Vow vad Configurations 6 10

9

8

K_BETA_FALL_CH1 RW 1 0 0 0

7

6

5

A879 4

K_ALPHA_RISE_CH1 RW 0 1 1 1

3

2

1

0

K_ALPHA_FALL_CH1 RW 1 0 0 1

Description Beta K rise value for left channel Beta K fall value for left channel Alpha K rise value for left channel Alpha K fall value for left channel

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 247 of 1067

MT6359 PMIC Datasheet Confidential A 00002424

Bit(s) 15:12 11:8 7:4 3:0

AFE_VOW_VAD_CFG7 15

Bit Name Type Reset

15

0

AFE Vow vad Configurations 7 10

14

0

13

0

0

14

0

12

0

11

0

10

0

15

14

6

5

A879 4

K_ALPHA_RISE_CH2 RW 0 1 1 1

3

2

1

0

K_ALPHA_FALL_CH2 RW 1 0 0 1

9

0

8

7

N_MIN_CH1 RW 1 0

0100

6

5

4

3

2

1

0

0

0

0

0

0

0

0

Description N min value for left channel

13

0

12

0

11

0

AFE Vow vad Configurations 9 10

0

9

0

8

7

N_MIN_CH2 RW 1 0

0100

6

5

4

3

2

1

0

0

0

0

0

0

0

0

Description N min value for right channel

AFE_VOW_VAD_CFG10

VOW_ SN_INI Name _CFG_E N_CH1 RW Type 0 Reset

7

AFE Vow vad Configurations 8

Name N_MIN_CH2

0000242A

8

Description Beta K rise value for right channel Beta K fall value for right channel Alpha K rise value for right channel Alpha K fall value for right channel

AFE_VOW_VAD_CFG9 15

9

K_BETA_FALL_CH2 RW 1 0 0 0

Name N_MIN_CH1

Bit Name Type Reset

Bit(s) 15 14:0

11

AFE_VOW_VAD_CFG8

00002428

Bit

12

Name K_BETA_RISE_CH2 K_BETA_FALL_CH2 K_ALPHA_RISE_CH2 K_ALPHA_FALL_CH2

Bit Name Type Reset

Bit(s) 15:0

13

K_BETA_RISE_CH2 RW 1 0 1 0

00002426

Bit(s) 15:0

14

13

12

11

AFE Vow vad Configurations 10 10

9

8

7

6

0000

5

4

3

2

1

0

0

0

0

0

0

0

VOW_SN_INI_CFG_VAL_CH1

0

0

0

Name VOW_SN_INI_CFG_EN_CH1 VOW_SN_INI_CFG_VAL_CH1

MediaTek Proprietary and Confidential.

0

0

0

0

RW 0

0

Description Vow S and N initial value configure enable for left channel Vow S and N initial value for left channel

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 248 of 1067

MT6359 PMIC Datasheet Confidential A 0000242C

AFE_VOW_VAD_CFG11 15

Bit

VOW_ SN_INI Name _CFG_E N_CH2 RW Type 0 Reset

Bit(s) 15 14:0

14

13

12

0

0

0

14

13

12

Name Type Reset

7

6

0000

5

4

3

2

1

0

0

0

0

0

RW 0

0

0

0

0

0

0

0

Description Vow S and N initial value configure enable for right channel Vow S and N initial value for right channel

11

AFE Vow vad Configurations 12 10

9

8

7

6

5

0C0C 4

3

2

1

1

Name K_GAMMA_CH1 K_GAMMA_CH2

AFE_VOW_TGEN_CFG0 14

Type Reset

VOW_ TGEN_ EN_CH 1 RW 0

VOW_T GEN_M UTE_S W_CH1 RW 0

Bit(s) 15 14 13:0

Name VOW_TGEN_EN_CH1 VOW_TGEN_MUTE_SW_CH1 VOW_TGEN_FREQ_DIV_CH1

13

12

11

RW 0

0

1

1

0

4

3

2

1

0

0

0

0

0

0

AFE Vow Trigen Configuration 0 10

0

9

8

7

6

5

0000

VOW_TGEN_FREQ_DIV_CH1 RW 0

0

0

0

15

14

Type Reset

VOW_ TGEN_ EN_CH 2 RW 0

VOW_T GEN_M UTE_S W_CH2 RW 0

13

12

Bit(s) 15 14 13:0

Name VOW_TGEN_EN_CH2 VOW_TGEN_MUTE_SW_CH2 VOW_TGEN_FREQ_DIV_CH2

0

0

0

0

0

Description Enables vow tri-gen for left channel Vow tri-gen SW mute for left channel Vow tri-gen freq div for left channel

AFE_VOW_TGEN_CFG1

MediaTek Proprietary and Confidential.

0

Description Gamma K value for left channel Gamma K value for right channel

15

0000244A

1

K_GAMMA_CH2

RW

Bit

Name

8

K_GAMMA_CH1

00002448

Bit

9

VOW_SN_INI_CFG_VAL_CH2

AFE_VOW_VAD_CFG12 15

Bit

Name

AFE Vow vad Configurations 11 10

Name VOW_SN_INI_CFG_EN_CH2 VOW_SN_INI_CFG_VAL_CH2

0000242E

Bit(s) 11:8 3:0

11

11

AFE Vow Trigen Configuration 1 10

9

8

7

6

5

0000 4

3

2

1

0

0

0

0

0

0

VOW_TGEN_FREQ_DIV_CH2 RW 0

0

0

0

0

0

0

0

0

Description Enables vow tri-gen for right channel Vow tri-gen sw mute for right channel Vow tri-gen freq div for right channel

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 249 of 1067

period

MT6359 PMIC Datasheet Confidential A 0000244C

AFE_VOW_HPF_CFG0 15

Bit

14

13

12

Name

VOW_HPF_DC_TEST_CH1

Type Reset

0

Bit(s) 15:12 7:4 2 1 0

11

AFE Vow hpf Configuration 0 10

9

8

7

6

0

0

Bit

14

13

12

11

1

0

9

8

7

6

4

Type Reset

RW

RW

Bit(s) 15:12 7:4 2 1 0

Bit

0

15

14

13

12

2

1

0

1

0

3

0

RG_MT RG_SN KAIF_H RDET_ RG_HP PF_BYP HPF_B F_ON_ ASS_C YPASS_ CH2 H2 CH2 RW RW RW

1

0

0

0

AFE Vow Periodic Configuration 0 10

9

8

7

6

5

0000 4

3

2

1

0

0

0

0

0

0

RG_PERIODIC_CNT_PERIOD RW 0

0

Name RG_PERIODIC_EN RG_PERIODIC_CNT_CLR

MediaTek Proprietary and Confidential.

11

0

Description Vow hpf test mode for right channel Configures vow hpf order for right channel Vow mtkaif bypass hpf filter for right channel snr detector bypass hpf filter Enables vow hpf filter for right channel

AFE_VOW_PERIODIC_CFG0

RG_PE RG_PE RIODIC Name RIODIC _CNT_ _EN CLR RW RW Type 0 0 Reset

Bit(s) 15 14 13:0

0

Name VOW_HPF_DC_TEST_CH2 RG_BASELINE_ALPHA_ORDER_CH2 RG_MTKAIF_HPF_BYPASS_CH2 RG_SNRDET_HPF_BYPASS_CH2 RG_HPF_ON_CH2

00002488

0

0050 5

VOW_HPF_DC_TEST_CH2

0

0

AFE Vow hpf Configuration 1 10

Name

0

1

RG_MT RG_SN KAIF_H RDET_ RG_HP PF_BYP HPF_B F_ON_ ASS_C YPASS_ CH1 H1 CH1 RW RW RW

1

RG_BASELINE_ALPHA_ORDER_ CH2

0

2

Description Vow hpf test mode for left channel Configures vow hpf order for left channel Vow mtkaif bypass hpf filter for left channel snr detector bypass hpf filter for left channel Enables vow hpf filter for left channel

AFE_VOW_HPF_CFG1 15

3

RW 0

Name VOW_HPF_DC_TEST_CH1 RG_BASELINE_ALPHA_ORDER_CH1 RG_MTKAIF_HPF_BYPASS_CH1 RG_SNRDET_HPF_BYPASS_CH1 RG_HPF_ON_CH1

0000244E

4

RG_BASELINE_ALPHA_ORDER_ CH1

RW 0

0050 5

0

0

0

0

0

0

0

Description Enables vow periodic Clears vow periodic count

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 250 of 1067

MT6359 PMIC Datasheet Confidential A 0000248A

AFE_VOW_PERIODIC_CFG1 15

Bit

RG_PE RIODIC Name _CNT_ SET RW Type 0 Reset

Bit(s) 15 14 13:0

14 RG_PE RIODIC _CNT_ PAUSE RW 0

13

12

11

AUDPR EAMPL ON_PE Name RIODIC _MOD E RW Type 0 Reset

14 AUDPR EAMPL ON_PE RIODIC _INVER SE RW 0

0

0

13

12

11

0

0

14 13:0

AUDPREAMPLON_PERIODIC_INVERSE AUDPREAMPLON_PERIODIC_ON_CY CLE

AUDPR EAMPL DCPRE Name CHARG E_PERI ODIC_ MODE

Type Reset

RW 0

AUDPR EAMPL DCPRE CHARG E_PERI ODIC_I NVERS E RW 0

13

12

11

0000 4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

Description Vow periodic count set a value when count is paused Pauses vow periodic count Vow periodic count set value

AFE Vow Periodic Configuration 2 10

9

8

7

6

5

0000 4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

4

3

2

1

0

0

0

0

0

Description Selects audpreamplon periodic mode 0: RG mode 1: Periodic mode Inverts audpreamplon periodic signal audpreamplon periodic turn on cycle

AFE Vow Periodic Configuration 3 10

9

8

7

6

5

0000

RW 0

0

0

Name AUDPREAMPLDCPRECHARGE_PERIO DIC_MODE

14

AUDPREAMPLDCPRECHARGE_PERIO DIC_INVERSE AUDPREAMPLDCPRECHARGE_PERIO DIC_ON_CYCLE

MediaTek Proprietary and Confidential.

5

AUDPREAMPLDCPRECHARGE_PERIODIC_ON_CYCLE

Bit(s) 15

13:0

0

AFE_VOW_PERIODIC_CFG3 14

6

RW 0

Name AUDPREAMPLON_PERIODIC_MODE

15

7

AUDPREAMPLON_PERIODIC_ON_CYCLE

Bit(s) 15

0000248E

8

RW 0

AFE_VOW_PERIODIC_CFG2 15

Bit

9

RG_PERIODIC_CNT_SET_VALUE

Name RG_PERIODIC_CNT_SET RG_PERIODIC_CNT_PAUSE RG_PERIODIC_CNT_SET_VALUE

0000248C

Bit

AFE Vow Periodic Configuration 1 10

0

0

0

0

0

0

0

Description Selects audpreampldcprecharge periodic mode 0: RG mode 1: Periodic mode Inverts audpreampldcprecharge periodic signal audpreampldcprecharge periodic turn on cycle

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 251 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00002490

AFE_VOW_PERIODIC_CFG4 15

Bit

Description

14

AUDAD AUDAD CLPWR CLPWR UP_PE UP_PE Name RIODIC RIODIC _MOD _INVER E SE RW RW Type 0 0 Reset

13

12

11

0

0

14 13:0

AUDADCLPWRUP_PERIODIC_INVERSE AUDADCLPWRUP_PERIODIC_ON_CY CLE

Bit

AUDGL AUDGL BVOW BVOWL LPWEN PWEN_ Name _PERIO PERIOD DIC_M IC_INV ODE ERSE RW RW Type 0 0 Reset

13

12

11

0

0

14

AUDGLBVOWLPWEN_PERIODIC_INV ERSE AUDGLBVOWLPWEN_PERIODIC_ON_ CYCLE

Bit

AUDDI GMICE Name N_PERI ODIC_ MODE

Type Reset

RW 0

14 AUDDI GMICE N_PERI ODIC_I NVERS E RW 0

MediaTek Proprietary and Confidential.

5

0000 4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

4

3

2

1

0

0

0

0

0

0

4

3

2

1

0

0

0

0

0

0

Description Selects audadclpwrup periodic mode 0: RG mode 1: Periodic mode Inverts audadclpwrup periodic signal Audadclpwrup periodic turn on cycle

AFE Vow Periodic Configuration 5 10

0

9

8

7

6

5

0000

13

12

11

0

0

0

0

0

Description Selects audglbvowlpwen periodic mode 0: RG mode 1: Periodic mode Inverts audglbvowlpwen periodic signal audglbvowlpwen periodic turn on cycle

AFE_VOW_PERIODIC_CFG6 15

6

RW 0

Name AUDGLBVOWLPWEN_PERIODIC_MO DE

00002494

7

AUDGLBVOWLPWEN_PERIODIC_ON_CYCLE

Bit(s) 15

13:0

0

AFE_VOW_PERIODIC_CFG5 14

8

RW 0

Name AUDADCLPWRUP_PERIODIC_MODE

15

9

AUDADCLPWRUP_PERIODIC_ON_CYCLE

Bit(s) 15

00002492

AFE Vow Periodic Configuration 4 10

AFE Vow Periodic Configuration 6 10

9

8

7

6

5

0000

AUDDIGMICEN_PERIODIC_ON_CYCLE

RW 0

0

0

0

0

0

0

0

0

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 252 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 15

Name AUDDIGMICEN_PERIODIC_MODE

14 13:0

AUDDIGMICEN_PERIODIC_INVERSE AUDDIGMICEN_PERIODIC_ON_CYCLE

00002496

AFE_VOW_PERIODIC_CFG7 15

Bit

AUDP WDBM ICBIAS Name 0_PERI ODIC_ MODE

Type Reset Bit(s) 15

14 13:0

RW 0

Bit(s) 15

14 13:0

AUDP WDBM ICBIAS 0_PERI ODIC_I NVERS E RW 0

13

12

11

AFE Vow Periodic Configuration 7 10

9

8

7

6

5

0000 4

3

2

1

0

0

0

0

0

AUDPWDBMICBIAS0_PERIODIC_ON_CYCLE

RW 0

0

0

0

0

0

0

0

0

0

Description Selects audpwdbmicbias0 periodic mode 0: RG mode 1: Periodic mode AUDPWDBMICBIAS0_PERIODIC_INVER Inverts audpwdbmicbias0 periodic signal SE AUDPWDBMICBIAS0_PERIODIC_ON_C audpwdbmicbias0 periodic turn on cycle YCLE

AFE_VOW_PERIODIC_CFG8 15

AUDP WDBM ICBIAS Name 1_PERI ODIC_ MODE

Type Reset

14

Name AUDPWDBMICBIAS0_PERIODIC_MOD E

00002498 Bit

Description Selects auddigmicen periodic mode 0: RG mode 1: Periodic mode Inverts auddigmicen periodic signal auddigmicen periodic turn on cycle

RW 0

14 AUDP WDBM ICBIAS 1_PERI ODIC_I NVERS E RW 0

13

12

11

AFE Vow Periodic Configuration 8 10

9

8

7

6

5

0000 4

3

2

1

0

0

0

0

0

AUDPWDBMICBIAS1_PERIODIC_ON_CYCLE

RW 0

0

0

0

0

0

0

0

0

0

Name Description AUDPWDBMICBIAS1_PERIODIC_MODE Selects audpwdbmicbias1 periodic mode 0: RG mode 1: Periodic mode AUDPWDBMICBIAS1_PERIODIC_INVE Inverts audpwdbmicbias1 periodic signal RSE AUDPWDBMICBIAS1_PERIODIC_ON_ audpwdbmicbias1 periodic turn on cycle

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 253 of 1067

MT6359 PMIC Datasheet Confidential A 0000249A

AFE_VOW_PERIODIC_CFG9 15

Bit

XO_VO W_CK_ EN_PE Name RIODIC _MOD E RW Type 0 Reset

Bit(s) 15

14 13:0

14 XO_VO W_CK_ EN_PE RIODIC _INVER SE RW 0

9

8

7

6

5

0000 4

3

2

1

0

0

0

0

0

0

4

3

2

1

0

0

0

0

0

XO_VOW_CK_EN_PERIODIC_ON_CYCLE

RW 0

0

0

0

0

0

0

0

0

14

13

12

11

10

9

8

7

6

5

0000

AUDGLB_PWRDN_PERIODIC_ON_CYCLE

RW 0

0

0

0

0

0

0

0

0

0

Name AUDGLB_PWRDN_PERIODIC_MODE

Description Selects audglb_pwrdn periodic mode 0: RG mode 1: Periodic mode AUDGLB_PWRDN_PERIODIC_INVERSE Inverts audglb_pwrdn periodic signal AUDGLB_PWRDN_PERIODIC_ON_CYCLE audglb_pwrdn periodic turn on cycle

0000249E

AFE_VOW_PERIODIC_CFG11 AFE Vow Periodic Configuration 11 15

VOW_ ON_CH Name 1_PERI ODIC_ MODE

Type Reset

AFE Vow Periodic Configuration 9 10

AFE_VOW_PERIODIC_CFG10 AFE Vow Periodic Configuration 10 15

AUDGL AUDGL B_PWR B_PWR DN_PE DN_PE Name RIODIC RIODIC _MOD _INVER E SE RW RW Type 0 0 Reset

Bit

11

Description Selects xo_vow_ck_en periodic mode 0: RG mode 1: Periodic mode XO_VOW_CK_EN_PERIODIC_INVERSE Inverts xo_vow_ck_en periodic signal XO_VOW_CK_EN_PERIODIC_ON_CYCLE xo_vow_ck_en periodic turn on cycle

Bit

14 13:0

12

Name XO_VOW_CK_EN_PERIODIC_MODE

0000249C

Bit(s) 15

13

RW 0

14 VOW_ ON_CH 1_PERI ODIC_I NVERS E RW 0

13

12

11

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

VOW_ON_CH1_PERIODIC_ON_CYCLE

RW 0

0

0

Bit(s) 15

Name VOW_ON_CH1_PERIODIC_MODE

14 13:0

VOW_ON_CH1_PERIODIC_INVERSE VOW_ON_CH1_PERIODIC_ON_CYCLE

MediaTek Proprietary and Confidential.

10

0000

0

0

0

0

0

0

Description Selects vow_on_ch1 periodic mode 0: RG mode 1: Periodic mode Inverts vow_on_ch1 periodic signal vow_on_ch1 periodic turn on cycle

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 254 of 1067

MT6359 PMIC Datasheet Confidential A 000024A0

AFE_VOW_PERIODIC_CFG12 AFE Vow Periodic Configuration 12 15

Bit

DMIC_ ON_CH Name 1_PERI ODIC_ MODE

Type Reset

RW 0

14 DMIC_ ON_CH 1_PERI ODIC_I NVERS E RW 0

13

12

11

0

0

14 13:0

DMIC_ON_CH1_PERIODIC_INVERSE DMIC_ON_CH1_PERIODIC_ON_CYCLE

0

14

13

12

11

0000 4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

10

0

0

0

13:0

AUDPREAMPLON_PERIODIC_OFF_CY CLE

000024A4

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

4

3

2

1

0

0

0

0

0

8000

RW

1

Name PDN_VOW_F32K_CK

0

0

0

0

0

0

Description Powers down periodic on/off 32k clock 0: Power on 1: Power down audpreamplon periodic turn off cycle

AFE_VOW_PERIODIC_CFG14 AFE Vow Periodic Configuration 14 15

14

13

12

11

10

VOW_ SNRDE Name T_PERI ODIC_C FG RW Type

Bit(s) 15 13:0

5

AUDPREAMPLON_PERIODIC_OFF_CYCLE

Bit(s) 15

Reset

6

Description Selects dmic_on_ch1 periodic mode 0: RG mode 1: Periodic mode Inverts dmic_on_ch1 periodic signal dmic_on_ch1 periodic turn on cycle

PDN_V Name OW_F3 2K_CK RW Type

Bit

7

AFE_VOW_PERIODIC_CFG13 AFE Vow Periodic Configuration 13 15

Reset

8

RW 0

Name DMIC_ON_CH1_PERIODIC_MODE

Bit

9

DMIC_ON_CH1_PERIODIC_ON_CYCLE

Bit(s) 15

000024A2

10

0

8

7

6

5

0000

AUDPREAMPLDCPRECHARGE_PERIODIC_OFF_CYCLE

RW 0

0

0

Name VOW_SNRDET_PERIODIC_CFG AUDPREAMPLDCPRECHARGE_PERIO

MediaTek Proprietary and Confidential.

9

0

0

0

0

0

0

0

Description Vow snrdet latch S/N value configure in periodic mode audpreampldcprecharge periodic turn off cycle

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 255 of 1067

MT6359 PMIC Datasheet Confidential A 000024A6

AFE_VOW_PERIODIC_CFG15 AFE Vow Periodic Configuration 15 15

Bit

14

Name Type Reset Bit(s) 13:0

9

8

7

6

5

0000 4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

4

3

2

1

0

0

0

0

0

Description audadclpwrup periodic turn off cycle

AFE_VOW_PERIODIC_CFG16 AFE Vow Periodic Configuration 16 15

14

13

12

11

10

9

8

7

6

5

0000

AUDGLBVOWLPWEN_PERIODIC_OFF_CYCLE RW 0

0

0

0

Name AUDGLBVOWLPWEN_PERIODIC_OFF _CYCLE

000024AA 15

Bit

0

0

0

0

0

0

Description audglbvowlpwen periodic turn off cycle

AFE_VOW_PERIODIC_CFG17 AFE Vow Periodic Configuration 17 14

Name Type Reset

13

12

11

10

9

8

7

6

5

0000 4

3

2

1

0

0

0

0

0

0

AUDDIGMICEN_PERIODIC_OFF_CYCLE RW 0

0

0

0

Name AUDDIGMICEN_PERIODIC_OFF_CYCLE

000024AC 15

Bit

0

0

0

0

0

Description auddigmicen periodic turn off cycle

AFE_VOW_PERIODIC_CFG18 AFE Vow Periodic Configuration 18 14

Name Type Reset

13

12

11

10

9

8

7

6

5

0000 4

3

2

1

0

0

0

0

0

AUDPWDBMICBIAS0_PERIODIC_OFF_CYCLE RW 0

0

0

0

0

0

0

0

0

0

Name Description AUDPWDBMICBIAS0_PERIODIC_OFF_C audpwdbmicbias0 periodic turn off cycle YCLE

000024AE Bit

10

Name AUDADCLPWRUP_PERIODIC_OFF_CY CLE

Name Type Reset

Bit(s) 13:0

11

RW 0

Bit

Bit(s) 13:0

12

AUDADCLPWRUP_PERIODIC_OFF_CYCLE

000024A8

Bit(s) 13:0

13

AFE_VOW_PERIODIC_CFG19 AFE Vow Periodic Configuration 19 15

14

Name Type Reset

MediaTek Proprietary and Confidential.

13

12

11

10

9

8

7

6

5

0000 4

3

2

1

0

0

0

0

0

AUDPWDBMICBIAS1_PERIODIC_OFF_CYCLE RW 0

0

0

0

0

0

0

0

0

0

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Page 256 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 13:0

Name Description AUDPWDBMICBIAS1_PERIODIC_OFF_C audpwdbmicbias1 periodic turn off cycle YCLE

000024B0

AFE_VOW_PERIODIC_CFG20 AFE Vow Periodic Configuration 20 15

Bit

14

13

12

11

10

CLKSQ _EN_V OW_PE Name RIODIC _MOD E RW Type

Reset

0

0

Name CLKSQ_EN_VOW_PERIODIC_MODE

13:0

XO_VOW_CK_EN_PERIODIC_OFF_CY CLE

15

14

13

0000 4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

Description Selects clksq_en_vow periodic mode 0: RG mode 1: Periodic mode xo_vow_ck_en periodic turn off cycle

12

11

10

9

8

7

6

5

0000 4

3

2

1

0

0

0

0

0

RW 0

0

0

0

Name AUDGLB_PWRDN_PERIODIC_OFF_CY CLE

15

Bit

0

0

0

0

0

0

Description audglb_pwrdn periodic turn off cycle

AFE_VOW_PERIODIC_CFG22 AFE Vow Periodic Configuration 22 14

Name Type Reset

13

12

11

10

9

8

7

6

5

0000 4

3

2

1

0

0

0

0

0

0

VOW_ON_CH1_PERIODIC_OFF_CYCLE RW 0

0

0

0

Name VOW_ON_CH1_PERIODIC_OFF_CYCLE

000024B6 Bit

5

AUDGLB_PWRDN_PERIODIC_OFF_CYCLE

000024B4

Bit(s) 13:0

6

AFE_VOW_PERIODIC_CFG21 AFE Vow Periodic Configuration 21

Name Type Reset Bit(s) 13:0

7

RW 0

Bit(s) 15

Bit

8

XO_VOW_CK_EN_PERIODIC_OFF_CYCLE

0

000024B2

9

0

0

0

0

0

Description vow_on_ch1 periodic turn off cycle

AFE_VOW_PERIODIC_CFG23 AFE Vow Periodic Configuration 23 15

14

Name Type Reset

MediaTek Proprietary and Confidential.

13

12

11

10

9

8

7

6

5

0000 4

3

2

1

0

0

0

0

0

0

DMIC_ON_CH1_PERIODIC_OFF_CYCLE RW 0

0

0

0

0

0

0

0

0

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 257 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 13:0

Name DMIC_ON_CH1_PERIODIC_OFF_CYCLE

000024B8

AFE_VOW_PERIODIC_CFG24 AFE Vow Periodic Configuration 24 15

Bit

14

AUDPR AUDPR EAMPR EAMPR ON_PE ON_PE Name RIODIC RIODIC _MOD _INVER E SE RW RW Type 0 0 Reset

13

12

11

10

0

0

0

14 13:0

AUDPREAMPRON_PERIODIC_INVERSE AUDPREAMPRON_PERIODIC_ON_CY CLE

14

13

12

11

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

4

3

2

1

0

0

0

0

0

3

2

1

0

0

0

0

0

Description Selects audpreampron periodic mode 0: RG mode 1: Periodic mode Inverts audpreampron periodic signal audpreampron periodic turn on cycle

9

8

7

6

5

0000

RW 0

0

0

Name AUDPREAMPRDCPRECHARGE_PERIO DIC_MODE

14

AUDPREAMPRDCPRECHARGE_PERIO DIC_INVERSE AUDPREAMPRDCPRECHARGE_PERIO DIC_ON_CYCLE

000024BC

10

AUDPREAMPRDCPRECHARGE_PERIODIC_ON_CYCLE

Bit(s) 15

Bit

7

AFE_VOW_PERIODIC_CFG25 AFE Vow Periodic Configuration 25 15

AUDPR AUDPR EAMPR EAMPR DCPRE DCPRE CHARG Name CHARG E_PERI E_PERI ODIC_I ODIC_ NVERS MODE E RW RW Type 0 0 Reset

13:0

8

RW 0

Name AUDPREAMPRON_PERIODIC_MODE

000024BA

9

0000

AUDPREAMPRON_PERIODIC_ON_CYCLE

Bit(s) 15

Bit

Description dmic_on_ch1 periodic turn off cycle

0

0

0

0

0

0

0

Description Selects audpreamprdcprecharge periodic mode 0: RG mode 1: Periodic mode Inverts audpreamprdcprecharge periodic signal audpreamprdcprecharge periodic turn on cycle

AFE_VOW_PERIODIC_CFG26 AFE Vow Periodic Configuration 26 15

14

AUDAD AUDAD CRPWR CRPWR UP_PE UP_PE Name RIODIC RIODIC _MOD _INVER E SE RW RW Type 0 0 Reset MediaTek Proprietary and Confidential.

13

12

11

10

9

8

7

6

5

0000 4

AUDADCRPWRUP_PERIODIC_ON_CYCLE

RW 0

0

0

0

0

0

0

0

0

0

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 258 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 15

Name AUDADCRPWRUP_PERIODIC_MODE

14 13:0

AUDADCRPWRUP_PERIODIC_INVERSE AUDADCRPWRUP_PERIODIC_ON_CY CLE

000024BE

AFE_VOW_PERIODIC_CFG27 AFE Vow Periodic Configuration 27 15

Bit

AUDGL BRVO WLPW Name EN_PE RIODIC _MOD E RW Type 0 Reset

14 AUDGL BRVO WLPW EN_PE RIODIC _INVER SE RW 0

13

12

11

0

0

14

AUDGLBRVOWLPWEN_PERIODIC_IN VERSE AUDGLBRVOWLPWEN_PERIODIC_ON _CYCLE

Bit

14 13:0

8

7

6

5

0000 4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

Description Selects audglbrvowlpwen periodic mode 0: RG mode 1: Periodic mode Inverts audglbrvowlpwen periodic signal audglbrvowlpwen periodic turn on cycle

AFE_VOW_PERIODIC_CFG28 AFE Vow Periodic Configuration 28 15

AUDDI GMIC1 EN_PE Name RIODIC _MOD E RW Type 0 Reset

Bit(s) 15

9

RW 0

Name AUDGLBRVOWLPWEN_PERIODIC_M ODE

000024C0

10

AUDGLBRVOWLPWEN_PERIODIC_ON_CYCLE

Bit(s) 15

13:0

Description Selects audadcrpwrup periodic mode 0: RG mode 1: Periodic mode Inverts audadcrpwrup periodic signal audadcrpwrup periodic turn on cycle

14 AUDDI GMIC1 EN_PE RIODIC _INVER SE RW 0

13

12

11

10

9

8

7

6

5

0000 4

3

2

1

0

0

0

0

0

0

AUDDIGMIC1EN_PERIODIC_ON_CYCLE

RW 0

0

0

0

0

0

0

0

0

Name AUDDIGMIC1EN_PERIODIC_MODE

Description Selects auddigmic1en periodic mode 0: RG mode 1: Periodic mode AUDDIGMIC1EN_PERIODIC_INVERSE Inverts auddigmic1en periodic signal AUDDIGMIC1EN_PERIODIC_ON_CYCLE auddigmic1en periodic turn on cycle

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 259 of 1067

MT6359 PMIC Datasheet Confidential A 000024C2

AFE_VOW_PERIODIC_CFG29 AFE Vow Periodic Configuration 29 15

Bit

AUDP WDBM ICBIAS Name 2_PERI ODIC_ MODE

Type Reset Bit(s) 15

14 13:0

RW 0

VOW_ ON_CH Name 2_PERI ODIC_ MODE

Type Reset

RW 0

11

0

0

14 VOW_ ON_CH 2_PERI ODIC_I NVERS E RW 0

13

12

11

7

6

5

0000 4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

10

9

8

7

6

5

0000 4

3

2

1

0

0

0

0

0

0

4

3

2

1

0

0

0

0

RW 0

0

0

VOW_ON_CH2_PERIODIC_INVERSE VOW_ON_CH2_PERIODIC_ON_CYCLE

0

0

0

0

0

0

Description Selects vow_on_ch2 periodic mode 0: RG mode 1: Periodic mode Inverts vow_on_ch2 periodic signal vow_on_ch2 periodic turn on cycle

AFE_VOW_PERIODIC_CFG31 AFE Vow Periodic Configuration 31 15

DMIC_ ON_CH Name 2_PERI ODIC_ MODE

Bit(s) 15

8

VOW_ON_CH2_PERIODIC_ON_CYCLE

14 13:0

Type 0 Reset

9

RW 0

Name VOW_ON_CH2_PERIODIC_MODE

Bit

10

AUDPWDBMICBIAS2_PERIODIC_ON_CYCLE

Bit(s) 15

000024C6

0

12

AFE_VOW_PERIODIC_CFG30 AFE Vow Periodic Configuration 30 15

Bit

0

AUDP WDBM ICBIAS 2_PERI ODIC_I NVERS E RW 0

13

Name Description AUDPWDBMICBIAS2_PERIODIC_MODE Selects audpwdbmicbias2 periodic mode 0: RG mode 1: Periodic mode AUDPWDBMICBIAS2_PERIODIC_INVER Inverts audpwdbmicbias2 periodic signal SE AUDPWDBMICBIAS2_PERIODIC_ON_C audpwdbmicbias2 periodic turn on cycle YCLE

000024C4

0

14

RW

14

13

12

11

DMIC_ ON_CH 2_PERI ODIC_I NVERS E RW

9

8

7

6

5

0000

DMIC_ON_CH2_PERIODIC_ON_CYCLE

RW

Name DMIC_ON_CH2_PERIODIC_MODE

MediaTek Proprietary and Confidential.

10

Description Selects dmic_on_ch2 periodic mode 0: RG mode 1: Periodic mode

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 260 of 1067

ic turn off cycle

MT6359 PMIC Datasheet Confidential A Bit(s) 14 13:0

Name DMIC_ON_CH2_PERIODIC_INVERSE DMIC_ON_CH2_PERIODIC_ON_CYCLE

000024C8

AFE_VOW_PERIODIC_CFG32 AFE Vow Periodic Configuration 32 15

Bit

14

Name Type Reset Bit(s) 13:0

0

10

9

8

7

6

5

0000 4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

4

3

2

1

0

0

0

0

0

3

2

1

0

0

0

0

0

0

4

3

2

1

0

0

0

0

0

Description audpreampron periodic turn off cycle

AFE_VOW_PERIODIC_CFG33 AFE Vow Periodic Configuration 33 15

14

13

12

11

10

9

8

7

6

5

0000

AUDPREAMPRDCPRECHARGE_PERIODIC_OFF_CYCLE RW 0

0

0

0

Name AUDPREAMPRDCPRECHARGE_PERIO DIC_OFF_CYCLE

000024CC

0

0

0

0

0

0

Description audpreamprdcprecharge periodic turn off cycle

AFE_VOW_PERIODIC_CFG34 AFE Vow Periodic Configuration 34 15

Bit

14

Name Type Reset

13

12

11

10

9

8

7

6

5

0000 4

AUDADCRPWRUP_PERIODIC_OFF_CYCLE RW 0

0

0

0

Name AUDADCRPWRUP_PERIODIC_OFF_CY CLE

000024CE

0

0

0

0

0

Description audadcrpwrup periodic turn off cycle

AFE_VOW_PERIODIC_CFG35 AFE Vow Periodic Configuration 35 15

14

Name Type Reset Bit(s) 13:0

11

Name AUDPREAMPRON_PERIODIC_OFF_CY CLE

Name Type Reset

Bit

12

RW

Bit

Bit(s) 13:0

13

AUDPREAMPRON_PERIODIC_OFF_CYCLE

000024CA

Bit(s) 13:0

Description Inverts dmic_on_ch2 periodic signal dmic_on_ch2 periodic turn on cycle

13

12

11

10

9

8

7

6

5

0000

AUDGLBRVOWLPWEN_PERIODIC_OFF_CYCLE RW 0

Name

0

0

0

0

0

0

0

0

0

Description

F_CYCLE

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 261 of 1067

MT6359 PMIC Datasheet Confidential A 000024D0

AFE_VOW_PERIODIC_CFG36 AFE Vow Periodic Configuration 36 15

Bit

14

Name Type Reset Bit(s) 13:0

14

8

7

6

5

0000 4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

4

3

2

1

0

0

0

0

0

Description auddigmic1en periodic turn off cycle

13

12

11

10

9

8

7

6

5

0000

AUDPWDBMICBIAS2_PERIODIC_OFF_CYCLE RW 0

0

0

0

Name AUDPWDBMICBIAS2_PERIODIC_OFF _CYCLE

15

Bit

0

0

0

0

0

0

Description audpwdbmicbias2 periodic turn off cycle

AFE_VOW_PERIODIC_CFG38 AFE Vow Periodic Configuration 38 14

Name Type Reset

13

12

11

10

9

8

7

6

5

0000 4

3

2

1

0

0

0

0

0

0

VOW_ON_CH2_PERIODIC_OFF_CYCLE RW 0

0

0

0

Name VOW_ON_CH2_PERIODIC_OFF_CYCLE

000024D6 15

Bit

0

0

0

0

0

Description vow_on_ch2 periodic turn off cycle

AFE_VOW_PERIODIC_CFG39 AFE Vow Periodic Configuration 39 14

Name Type Reset

13

12

11

10

9

8

7

6

5

0000 4

3

2

1

0

0

0

0

0

0

DMIC_ON_CH2_PERIODIC_OFF_CYCLE RW 0

0

0

0

Name DMIC_ON_CH2_PERIODIC_OFF_CYCLE

000024D8

Bit(s) 15:0

9

AFE_VOW_PERIODIC_CFG37 AFE Vow Periodic Configuration 37 15

000024D4

Bit Name Type Reset

10

Name AUDDIGMIC1EN_PERIODIC_OFF_CYC LE

Name Type Reset

Bit(s) 13:0

11

RW 0

Bit

Bit(s) 13:0

12

AUDDIGMIC1EN_PERIODIC_OFF_CYCLE

000024D2

Bit(s) 13:0

13

0

0

0

0

0

Description dmic_on_ch2 periodic turn off cycle

AFE_VOW_PERIODIC_MON0 AFE Vow Periodic Monitor 0 15

0

14

0

13

12

0

0

Name VOW_PERIODIC_MON0

MediaTek Proprietary and Confidential.

11

0

8

7

0000

10

9

6

5

4

3

2

1

0

0

VOW_PERIODIC_MON0 RO 0 0 0 0

0

0

0

0

0

0

Description Vow periodic control monitor 0

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 262 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

000024DA

Bit(s) 15:0

AFE_VOW_PERIODIC_MON1 AFE Vow Periodic Monitor 1 15

Bit Name Type Reset

0

14

0

0

14

0

14

Name

1

Bit(s) 15

7

6

5

4

3

2

1

0

0

VOW_PERIODIC_MON1 RO 0 0 0 0

0

0

0

0

0

0

5

4

3

2

1

0

0

0

0

0

0

0

4

3

2

1

Description Vow periodic control monitor 1

13

12

0

11

0

0

10

0

13

9

0

7

6

VOW_PERIODIC_COUNT_MON RO 0 0 0 0

0000

Description Vow periodic control count monitor

AFE_NCP_CFG0

12

RW 1

1

8

11

10

9

0

0

0

8

B000 7

6

5

0

RG_NC RG_NC RG_NCP_DITHER_FIXE RG_NCP_DITHER_FIXE RG_NC P_ADIT P_DITH D_CK0_ACK1_2P D_CK0_ACK2_2P P_ON H ER_EN RW RW RW RW RW 0 0 0 0 0 0 0 0 0

Name RG_NCP_CK1_VALID_CNT RG_NCP_ADITH

Description Configures ncp soft start time Selects CK dither 0: fixed 1: rnd RG_NCP_DITHER_EN Enables rnd dither RG_NCP_DITHER_FIXED_CK0_ACK1_2P CK1 fixed dither value RG_NCP_DITHER_FIXED_CK0_ACK2_2P CK2 fixed dither value RG_NCP_ON Enables NCP

000024E0

Type Reset

0

9

RG_NCP_CK1_VALID_CNT

Type Reset

Name

0

8

0000

10

AFE_NCP_CFG0 15

Bit

Bit

0

11

Name VOW_PERIODIC_COUNT_MON

000024DE

7 6:4 3:1 0

12

AFE_VOW_PERIODIC_MON2 AFE Vow Periodic Monitor 2 15

Bit Name Type Reset

Bit(s) 15:9 8

13

Name VOW_PERIODIC_MON1

000024DC

Bit(s) 15:0

Description

AFE_NCP_CFG1 15

14

13

AFE_NCP_CFG1

12

RG_XY _VAL_ CFG_E

10

9

8

1515 7

6

5

RG_X_VAL_CFG

RW 0

11

4

0

1

Name RG_XY_VAL_CFG_EN

MediaTek Proprietary and Confidential.

0

2

1

0

0

1

RG_Y_VAL_CFG

RW 0

3

RW 1

0

1

0

0

1

0

1

Description Configures NCP CK1/CK2 pulse width SW mode

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 263 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

14:8 6:0

RG_X_VAL_CFG RG_Y_VAL_CFG

000024E2

AFE_NCP_CFG2 15

Bit

Description 0: fixed 1: sw mode Configures NCP CK1 pulse width Configures NCP CK2 pulse width

14

13

12

AFE_NCP_CFG2 11

10

9

8

0000 7

6

5

4

3

2

Name Type Reset Bit(s) 1

0

0

Name RG_NCP_NONCLK_SET

Name

Type Reset Bit(s) 14:13

14

13

12

AUDENC Control Register 0

11

10

9

8

7

6

0000 5

4

3

2

RG_AU RG_AU RG_AU RG_BU DPREA RG_AUDADCLI RG_AUDPREA RG_AUDPREA DPREA DADCL LKL_VC RG_AUDPREAMPLGAIN MPLDC NPUTSEL MPLINPUTSEL MPLVSCALE MPLPG PWRUP M_EN PRECH ATEST ARGE RW RW RW RW RW RW RW RW 0

0

0

Name RG_AUDADCLINPUTSEL

RG_AUDADCLPWRUP

11

RG_BULKL_VCM_EN

7:6

0

Description NCP non-overlap timing option control 0: 1T 1: 3T

AUDENC_ANA_CON0 15

12

10:8

0

RG_NCP_PDDIS_EN

00002508 Bit

1

RG_NC RG_NC P_NON P_PDDI CLK_SE S_EN T RW RW

RG_AUDPREAMPLGAIN

RG_AUDPREAMPLINPUTSEL

MediaTek Proprietary and Confidential.

0

0

0

0

0

0

0

0

0

0

1

0

RG_AU RG_AU DPREA DPREA MPLDC MPLO CEN N RW

RW

0

0

Description Selects audio L ADC input 00: Idle 01: AIN0 10: Left preamplifier 11: Idle Powers upaudio L ADC 0: Power down 1: Power on Audio L preamplifier PGA switch bulk tied to VCM or supply rail control 0: Tied to supply rail 1: Tied to VCM Adjusts audio L preamplifier gain 000: 0dB 001: 6dB 011: 18dB 100: 24dB Selects audio L preamplifier input 00: None 01: AIN0

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 264 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

5:4 3

Name

RG_AUDPREAMPLVSCALE RG_AUDPREAMPLPGATEST

2

RG_AUDPREAMPLDCPRECHARGE

1

RG_AUDPREAMPLDCCEN

0

RG_AUDPREAMPLON

0000250A Bit

Name

Type Reset Bit(s) 14:13

Description 10: AIN1 11: None Audio L preamplifier PGA DC output voltage scale Enables audio L preamplifier PGA test 0: Disable 1: Enable Audio L preamplifier PGA DC couple input precharge 0: Disable 1: Enable Audio L DC couple input 0: AC couple input 1: DC couple input Enables audio L preamplifier 0: Disable 1: Enable

AUDENC_ANA_CON1 15

14

13

12

AUDENC Control Register 1

11

10

9

8

7

6

0000 5

4

3

2

1

0

RG_AU RG_AU RG_AU RG_AU RG_AU RG_BU DPREA RG_AUDADCRI RG_AUDPREAMPRGAI RG_AUDPREA RG_AUDPREA DPREA DPREA DPREA DADCR LKR_VC MPRDC NPUTSEL N MPRINPUTSEL MPRVSCALE MPRPG MPRDC MPRO PWRUP M_EN PRECH ATEST CEN N ARGE RW RW RW RW RW RW RW RW RW RW 0

0

0

Name RG_AUDADCRINPUTSEL

12

RG_AUDADCRPWRUP

11

RG_BULKR_VCM_EN

10:8

RG_AUDPREAMPRGAIN

7:6

RG_AUDPREAMPRINPUTSEL

5:4 3

RG_AUDPREAMPRVSCALE RG_AUDPREAMPRPGATEST

MediaTek Proprietary and Confidential.

0

0

0

0

0

0

0

0

0

0

0

0

Description Selects audio R ADC input 00: Idle 01: AIN2 10: Right preamplifier 11: Idle Powers up audio R ADC 0: Power down 1: Power on Audio R preamplifier PGA switch bulk tied to VCM or supply rail control 0: Tied to supply rail 1: Tied to VCM Adjusts audio R preamplifier gain 000: 0dB 001: 6dB 010: 12dB 011: 18dB 100: 24dB Selects audio R preamplifier input 00: None 01: AIN2 10: AIN3 11: AIN0 Audio R preamplifier PGA DC output voltage scale Enables audio R preamplifier PGA test 0: Disable 1: Enable

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 265 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 2

Name RG_AUDPREAMPRDCPRECHARGE

1

RG_AUDPREAMPRDCCEN

0

RG_AUDPREAMPRON

0000250C Bit

Name

Type Reset Bit(s) 14:13

Description Audio R preamplifier PGA DC couple input precharge 0: Disable 1: Enable Audio R DC couple input 0: AC couple input 1: DC couple input Enables audio R preamplifier 0: Disable 1: Enable

AUDENC_ANA_CON2 15

14

13

12

AUDENC Control Register 2

11

10

9

8

7

6

0000 5

4

3

2

1

0

RG_AU RG_AU RG_AU RG_AU RG_AU RG_BU DPREA RG_AUDADC3I RG_AUDPREAMP3GAI RG_AUDPREA RG_AUDPREA DPREA DPREA DPREA DADC3 LK3_VC MP3DC NPUTSEL N MP3INPUTSEL MP3VSCALE MP3PG MP3DC MP3O PWRUP M_EN PRECH ATEST CEN N ARGE RW RW RW RW RW RW RW RW RW RW 0

0

0

0

Name RG_AUDADC3INPUTSEL

12

RG_AUDADC3PWRUP

11

RG_BULK3_VCM_EN

10:8

RG_AUDPREAMP3GAIN

7:6

RG_AUDPREAMP3INPUTSEL

5:4 3

RG_AUDPREAMP3VSCALE RG_AUDPREAMP3PGATEST

2

RG_AUDPREAMP3DCPRECHARGE

1

RG_AUDPREAMP3DCCEN

MediaTek Proprietary and Confidential.

0

0

0

0

0

0

0

0

0

0

0

Description Selects audio 3rd ADC input 00: Idle 01: AIN3 10: 3rd preamplifier 11: Idle Audio 3rd ADC power up 0: Power down 1: Power on Audio 3rd preamplifier PGA switch bulk tied to VCM or supply rail control 0: Tied to supply rail 1: Tied to VCM Adjusts audio 3rd preamplifier gain 000: 0dB 001: 6dB 010: 12dB 011: 18dB 100: 24dB Selects audio 3rd preamplifier input 00: None 01: AIN3 10: AIN2 11: None Audio 3rd preamplifier PGA DC output voltage scale Enables audio 3 preamplifier PGA test 0: Disable 1: Enable Audio 3 preamplifier PGA DC couple input precharge 0: Disable 1: Enable Audio 3 DC couple input 0: AC couple input

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 266 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 0

Name RG_AUDPREAMP3ON

0000250E Bit

Description 1: DC couple input Enables audio 3 preamplifier 0: Disable 1: Enable

AUDENC_ANA_CON3 15

14

13

12

11

AUDENC Control Register 3 10

9

8

7

6

0000 5

4

3

2

RG_AU RG_AU RG_AU RG_AU RG_AUDADC2N RG_AUDADC1S DADC2 RG_AUDADCFL RG_AUDADCRE RG_AUDPREA DADCF DADC1 DPREA DSTAGEIDDTES TSTAGEIDDTES NDSTA Name ASHIDDTEST FBUFIDDTEST MPIDDTEST LASHLP STSTAG MPLPE T T GELPE EN ELPEN N N RW RW RW RW RW RW RW RW RW Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

Bit(s) 15:14

Name RG_AUDADCFLASHIDDTEST

13:12

RG_AUDADCREFBUFIDDTEST

11:10

RG_AUDADC2NDSTAGEIDDTEST

9:8

RG_AUDADC1STSTAGEIDDTEST

7:6

RG_AUDPREAMPIDDTEST

5

RG_AUDADCFLASHLPEN

4

RG_AUDADC2NDSTAGELPEN

3

RG_AUDADC1STSTAGELPEN

2

RG_AUDPREAMPLPEN

MediaTek Proprietary and Confidential.

1

0

RG_AU RG_AU DGLBV DULHA OWLP LFBIAS WEN RW 0

RW 0

Description Selects audio ADC flash Idd current test 00: 100% 01: 80% 10: 120% 11: 140% Selects audio ADC reference buffer Idd current test 00: 100% 01: 80% 10: 120% 11: 140% Audio ADC 2nd & 3rd stage Idd adjust bits 00: 100% 01: 80% 10: 120% 11: 140% Audio ADC 1st stage Idd adjust bits 00: 100% 01: 80% 10: 120% 11: 140% Audio preamplifier Idd adjust bits 00: 100% 01: 75% 10: 125% 11: 150% Enables audio ADC flash low power 0: Normal 1: Enable Enables audio ADC 2nd & 3rd low power 0: Normal 1: Enable Enables audio ADC 1st stage low power 0: Normal 1: Enable Audio preamplifier PGA low power mode 0: Disable 1: Enable

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 267 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 1

0

Name RG_AUDGLBVOWLPWEN

RG_AUDULHALFBIAS

00002510 Bit

Description Enables audio uplink globe bias VOW low power mode 0: Normal 1: Enable Enables audio uplink halfbias 0: Normal 1: Enable

AUDENC_ANA_CON4 15

14

13

12

11

AUDENC Control Register 4 10

9

8

7

6

0000 5

4

3

2

1

0

RG_AU RG_AU RG_AU RG_AU RG_AU RG_AU RG_AUDRADC2 RG_AUDRADC1 DRADC DRADC RG_AUDRADCF RG_AUDRADCR RG_AUDRPREA DRADC DRPRE DGLBR DRULH NDSTAGEIDDTE STSTAGEIDDTE 2NDST 1STSTA Name LASHIDDTEST EFBUFIDDTEST MPIDDTEST FLASHL AMPLP VOWLP ALFBIA ST ST AGELPE GELPE PEN EN WEN S N N RW RW RW RW RW RW RW RW RW RW RW Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

Bit(s) 15:14

Name RG_AUDRADCFLASHIDDTEST

13:12

RG_AUDRADCREFBUFIDDTEST

11:10

RG_AUDRADC2NDSTAGEIDDTEST

9:8

RG_AUDRADC1STSTAGEIDDTEST

7:6

RG_AUDRPREAMPIDDTEST

5

RG_AUDRADCFLASHLPEN

4

RG_AUDRADC2NDSTAGELPEN

3

RG_AUDRADC1STSTAGELPEN

2

RG_AUDRPREAMPLPEN

MediaTek Proprietary and Confidential.

Description Selects audio ADC flash Idd current test 00: 100% 01: 80% 10: 120% 11: 140% Selects audio ADC reference buffer Idd current test 00: 100% 01: 80% 10: 120% 11: 140% Audio ADC 2nd & 3rd stage Idd adjust bits 00: 100% 01: 80% 10: 120% 11: 140% Audio ADC 1st stage Idd adjust bits 00: 100% 01: 80% 10: 120% 11: 140% Audio preamplifier Idd adjust bits 00: 100% 01: 75% 10: 125% 11: 150% Enables audio ADC flash low power 0: Normal 1: Enable Enables audio ADC 2nd & 3rd low power 0: Normal 1: Enable Enables audio ADC 1st stage low power 0: Normal 1: Enable Audio preamplifier PGA low power mode

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 268 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

1

RG_AUDGLBRVOWLPWEN

0

RG_AUDRULHALFBIAS

00002512 Bit

AUDENC_ANA_CON5 15

Name Type Reset Bit(s) 15:11

14

13

12

AUDENC Control Register 5

11

RG_AUDSPAREPGA

0

0

RW 0

0

Name RG_AUDSPAREPGA

10 9 8

RG_DCCVCMBUFLPSWEN RG_DCCVCMBUFLPMODSEL RG_AUDPREAMPAAFEN

7

RG_AUDPREAMP_ACCFS

6:5

RG_AUDADCCLKGENMODE

4:3

RG_AUDADCCLKSOURCE

2:1

RG_AUDADCCLKSEL

0

Description 0: Disable 1: Enable Enables audio uplink globe bias VOW low power mode 0: Normal 1: Enable Enables audio uplink halfbias 0: Normal 1: Enable

RG_AUDADCCLKRSTB

MediaTek Proprietary and Confidential.

0

10

9

8

7

6

0000 5

4

3

2

1

0

RG_DC RG_DC RG_AU RG_AU RG_AU CVCMB CVCMB DPREA DPREA RG_AUDADCCL RG_AUDADCCL RG_AUDADCCL DADCC UFLPS UFLPM MPAAF MP_AC KGENMODE KSOURCE KSEL LKRSTB WEN ODSEL EN CFS RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0

Description ->RG_NNP_EN_VA25 ->SWenh1_VA25 ->SWenh2_VA25 ->OP_CMFBEN_VA25 Audio preamplifier PGA DCC VCM buffer SW EN Audio preamplifier PGA DCC VCM buffer LP MODSEL Audio preamplifier PGA with AAF input in DC couple mode 0: Disable 1: Enable Audio preamplifier's fast settling technique for ACC mode 0: Disable 1: Enable Audio ADC clock gen. mode 00: Divided by 2 (normal) 01: Divided by 4 10: Divided by 8 11: Not divided Audio ADC clock source 00: 13MHz from CLKSQ 01: 3.25MHz from CLKSQ 10: 12.58MHz from 32kHz PLL 11: 12MHz ring oscillator Selects audio ADC's filter adjustment for clock 00: For 13MHz clock in, 6.5MHz data out 10: For 26MHz clock in, 13MHz data out 01: For 6.5MHz clock in, 3.25MHz data out 11: NA Audio ADC clock RSTB 0: Reset 1: Enable

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 269 of 1067

MT6359 PMIC Datasheet Confidential A 00002514 Bit

AUDENC_ANA_CON6 15

14

13

12

11

AUDENC Control Register 6 10

9

8

7

6

0800 5

4

3

2

1

0

RG_AU RG_AU RG_AU RG_AU RG_AU RG_AU RG_AU RG_AU RG_AU RG_AU RG_AU RG_AU DADCD RG_AU RG_AU DADC3 DADC2 DADC1 DADCR DADCD RG_AUDADCD DADCF DADCN DADC Name DAC0P AC0P25 DADCD DADCN DADCD ACIDDTEST ACFBC FBYPAS DADCB OPATE WIDEC DADCF RDSTA NDSTA STSTA ACTEST ODEM ACNRZ URREN YPASS SRESET GERESE GERESE GESDE 25FS FS S ST M T T T NB RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 Reset

Bit(s) 15

Name RG_AUDADCRDAC0P25FS

14

RG_AUDADCDAC0P25FS

13

RG_AUDADCDACTEST

12 11

RG_AUDADCNODEM RG_AUDADCDACNRZ

10:9

RG_AUDADCDACIDDTEST

8 7

RG_AUDADCDACFBCURRENT RG_AUDADCFFBYPASS

6

RG_AUDADCBYPASS

5

RG_AUDADCNOPATEST

4

RG_AUDADCWIDECM

3 2

RG_AUDADCFSRESET RG_AUDADC3RDSTAGERESET

1

RG_AUDADC2NDSTAGERESET

0

RG_AUDADC1STSTAGESDENB

MediaTek Proprietary and Confidential.

Description Enables audio ADCR FBDAC 0.25FS 0: 13MHz clock in, 6.5MHz data out 1: 3.25MHz clock in, 1.625MHz data out Enables audio ADCL FBDAC 0.25FS 0: 13MHz clock in, 6.5MHz data out 1: 3.25MHz clock in, 1.625MHz data out Audio ADC DAC test 0: Disable 1: Enable the data in RG_AUDADCTESTDATA[15:0] to be passed to DAC Audio ADC DEM test Audio ADC DAC in non return to zero mode 0: RZ mode (2I) 1: NRZ mode (I) Audio ADC-DAC Idd current test selection 00: Normal 11: -20% DAC f/b current Audio ADC feedback coefficient Bypasses audio ADC feed forward 0: No bypass. Allow feedforward coefficient to pass signal to ADC flash. 1: Bypass. Not allow ADC i/p signal to feedforward flash. Enables audio ADC input resistor bypass 0: Disable 1: Enable Audio ADC no preamp test 0: Normal ADC gain 1: 6dB ADC gain Enables audio ADC wide common mode 0: Normal 1: Enable Selects audio encoder FS reset block model Audio ADC 3rd stage reset 0: Normal 1: Reset Audio ADC 2nd stage reset 0: Normal 1: Reset Audio ADC 1st stage source degenerate enableb 0: Enable 1: Disable

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 270 of 1067

MT6359 PMIC Datasheet Confidential A 00002516

Bit(s) 15:0

AUDENC_ANA_CON7 15

Bit Name Type Reset

0

14

0

13

12

0

0

14

13

Type Reset

12

0

Name RG_AUDRCTUNERSEL

12:8

RG_AUDRCTUNER

4:0

4

3

2

1

0

0

RG_AUDADCTESTDATA RW 0 0 0 0

0

0

0

0

0

0

10

14

13

1

0

RW 0

12

0

Name RG_AUD3SPARE RGS_AUDRCTUNE3READ RG_AUD3CTUNELSEL

RG_AUD3CTUNEL

MediaTek Proprietary and Confidential.

7

0

1515

6

5

4

RG_AU DRCTU NELSEL RW 1

3

2

1

0

RG_AUDRCTUNEL RW

0

1

0

1

0

6

5

4

3

2

1

1

RG_AU D3CTU NELSEL RW 0

1

Description Selects audio R ADC RC tuning 0: Use auto cal tune bits 1: Use RG_AUDRCTUNEL[4:0] Audio R ADC RC tuned value See RG_AUDRCTUNELSE. Selects audio L ADC RC tuning 0: Use auto cal tune bits 1: Use RG_AUDRCTUNEL[4:0] Audio L ADC RC tuned value See RG_AUDRCTUNELSE.

AUDENC Control Register 9

11

10

RG_AUD3SPARE

0

8

RW 0

AUDENC_ANA_CON9 15

9

RG_AUDRCTUNER

RG_AUDRCTUNEL

Name

Bit(s) 15:11 10:6 5

5

RG_AUDRCTUNELSEL

0000251A

Type Reset

6

AUDENC Control Register 8

11

1

Bit(s) 13

7

Description Audio ADC test data bits Audio ADC test data bits for both phases of DRTZ DAC. Can enable any current source you choose.

RG_AU DRCTU NERSEL RW

Name

Bit

9

AUDENC_ANA_CON8 15

Bit

4:0

0

8

0000

10

Name RG_AUDADCTESTDATA

00002518

5

AUDENC Control Register 7

11

9

8

7

RGS_AUDRCTUNE3READ

0

1

1

RO 1

1

07D5 0

RG_AUD3CTUNEL

1

0

RW 1

0

1

Description Spare RG Audio 3 RC tune read data Selects audio 3rd ADC RC tuning 0: Use auto cal tune bits 1: Use RG_AUD3RCTUNEL[4:0] Audio 3rd ADC RC tuned value See RG_AUDRCTUNELSE.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 271 of 1067

MT6359 PMIC Datasheet Confidential A 0000251C

AUDENC_ANA_CON10 15

Bit

14

13

12

Name Type Reset

1

Bit(s) 12:8 4:0

Name RGS_AUDRCTUNERREAD RGS_AUDRCTUNELREAD

1

1

0

13

12

11

0

RG_AUDSPAREVA18 RW 0 0 0 0

6

1F1F 5

4

3

10

AUDENC_ANA_CON12 15

14

13

0

0

12

0

11

0

0

0

1

1

1

1

1

4

3

14

13

12

9

0

9

RW 0

11

8

0

7

0

0000

6

5

2

1

0

0

RG_AUDSPAREVA30 RW 0 0 0 0

0

0

8

7

6

0000 5

4

3

9

RG_DMICMONSEL

Type Reset

RW 0

RG_AUDDIGMICNDUTY RG_AUDDIGMICPDUTY

MediaTek Proprietary and Confidential.

0

0

0

0

0

0

2

1

0

RG_AU RG_AU RG_AU DPGA_ DPGA_ DPGA_ ACCCM CAPRA DECAP P RW RW RW 0 0 0

AUDENC Control Register 13 10

Name

Name RG_DMICMONSEL RG_DMICMONEN

1

Description AUDENC spare2 3.3V domain, enable ACC mode feedback compensation capacitor 3.3V domain, enable cap re-arrange 3.3V domain, enable decoupling cap for 1MHz interference

AUDENC_ANA_CON13 15

0

RO 1

AUDENC Control Register 12 10

Name RG_AUDENC_SPARE2 RG_AUDPGA_ACCCMP RG_AUDPGA_CAPRA RG_AUDPGA_DECAP

00002522

1

RGS_AUDRCTUNELREAD

RG_AUDENC_SPARE2

Type Reset

2

Description Spare control bits for AVDD18 voltage domain Spare control bits for AVDD30 voltage domain

Name

7:6 5:4

7

AUDENC Control Register 11

14

Name RG_AUDSPAREVA18 RG_AUDSPAREVA30

Bit

Bit(s) 11:9 8

8

Description Audio R RC tune read data Audio L RC tune read data

AUDENC_ANA_CON11 15

00002520

Bit

9

RO

Bit Name Type Reset

Bit(s) 15:3 2 1 0

AUDENC Control Register 10 10

RGS_AUDRCTUNERREAD

0000251E

Bit(s) 15:8 7:0

11

0

0

8

7

6

0004 5

4

3

2

1

0

RG_D RG_D RG_AU RG_AUDDIGMI RG_AUDDIGMI RG_AUDDIGMI MICM MICHP DDIGM CNDUTY CPDUTY CBIAS ONEN CLKEN ICEN RW RW RW RW RW RW 0

0

0

0

0

0

1

0

0

Description Enables digital microphone monitor path Enables digital microphone monitor path 0: Disable 1: Enable Digital microphone negative duty control Digital microphone positive duty control

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 272 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 3

2:1 0

Name RG_DMICHPCLKEN

RG_AUDDIGMICBIAS RG_AUDDIGMICEN

00002524

AUDENC_ANA_CON14 15

Bit Name

14

13

12

RG_AUDSPAREVMIC

Type Reset Bit(s) 15:12 11:9 8

Description Enables digital microphone monitor path selection 0: Digital CLK 1: CLKSQ Digital microphone slew rate control 11 > 10 > 01 > 00 Enables digital microphone 0: Disable 1: Enable

RW 0

0

0

0

2:1

RG_AUDDIGMICBIAS1

Type Reset

RW 0

AUDENC_ANA_CON15 15

14

13

12

11

RG_AU RG_AU RG_AU DMICBI DMICBI DMICBI AS0DC AS0DC AS0DC SW2NE SW2P2 SW2P1 N EN EN RW RW RW 0

0

0

Bit(s) 14

Name RG_AUDMICBIAS0DCSW2NEN

13

RG_AUDMICBIAS0DCSW2P2EN

12

RG_AUDMICBIAS0DCSW2P1EN

MediaTek Proprietary and Confidential.

9

0

8

7

0004

6

5

4

3

2

1

0

RG_D RG_D RG_AU RG_AUDDIGMI RG_AUDDIGMI RG_AUDDIGMI MIC1M MIC1H DDIGM C1NDUTY C1PDUTY CBIAS1 ONEN PCLKEN IC1EN RW RW RW RW RW RW 0 0 0 0 0 0 1 0 0

Description Spare control bits for AVDD25MIC voltage domain Enables digital microphone monitor path Enables digital microphone monitor path 0: Disable 1: Enable Digital microphone negative duty control Digital microphone positive duty control Enables digital microphone monitor path selection 0: Digital CLK 1: CLKSQ Digital microphone slew rate control 11 > 10 > 01 > 00 Enables digital microphone 0: Disable 1: Enable

RG_AUDDIGMIC1EN

00002526

Name

0

Name RG_AUDSPAREVMIC RG_DMIC1MONSEL RG_DMIC1MONEN

RG_AUDDIGMIC1NDUTY RG_AUDDIGMIC1PDUTY RG_DMIC1HPCLKEN

Bit

AUDENC Control Register 14 10

RG_DMIC1MONSEL

7:6 5:4 3

0

11

AUDENC Control Register 15 10

9

8

RG_AU RG_AU RG_AU DMICBI DMICBI DMICBI AS0DC AS0DC AS0DC SW0NE SW0P2 SW0P1 N EN EN RW RW RW 0

0

0

7

0000

6

5

4

3

2

1

0

RG_AU RG_AU RG_AU RG_AU DPWD DMICBI DMICBI DPWD RG_AUDMICBIAS0VREF BMICBI AS0LO AS0BYP BMICBI AS3 WPEN ASSEN AS0 RW 0

0

0

RW

RW

RW

RW

0

0

0

0

Description MIC Bias 0 DC couple switch 2N 0: Off 1: On MIC Bias 0 DC couple switch 2P2 0: Off 1: On MIC Bias 0 DC couple switch 2P1

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Page 273 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

10

RG_AUDMICBIAS0DCSW0NEN

9

RG_AUDMICBIAS0DCSW0P2EN

8

RG_AUDMICBIAS0DCSW0P1EN

6:4

RG_AUDMICBIAS0VREF

3

RG_AUDPWDBMICBIAS3

2

RG_AUDMICBIAS0LOWPEN

1

RG_AUDMICBIAS0BYPASSEN

0

RG_AUDPWDBMICBIAS0

00002528 Bit

AUDENC_ANA_CON16 15

14

13

12

RG_AU RG_AU DMICBI DMICBI AS1HV AS1HV VREF EN

Name

Type Reset Bit(s) 13

Description 0: Off 1: On MIC Bias 0 DC couple switch 0N 0: Off 1: On MIC Bias 0 DC couple switch 0P2 0: Off 1: On MIC Bias 0 DC couple switch 0P1 0: Off 1: On Selects MIC Bias 0/2 Output voltage 000: 1.7V 001: 1.8V 010: 1.9V 011: 2.0V 100: 2.1V 101: 2.5V 110: 2.6V 111: 2.7V MIC Bias 3 power down 0: Power down 1: Power on Enables MIC Bias 0 LowPower 0: Normal mode 1: Low power mode Enables MIC Bias 0 BYPASS 0: Disable 1: Enable Powers down MIC Bias 0 0: Power down 1: Power on

RW

RW

0

0

Name RG_AUDMICBIAS1HVVREF

12

RG_AUDMICBIAS1HVEN

10

RG_BANDGAPGEN

MediaTek Proprietary and Confidential.

11

AUDENC Control Register 16 10

9

8

RG_AU RG_AU RG_BA DMICBI DMICBI NDGAP AS1DC AS1DC GEN SW1NE SW1PE N N RW RW RW 0

0

0

7

6

0000 5

4

RG_AUDMICBIAS1VREF

RW 0

0

0

3

2

1

0

RG_AU RG_AU RG_AU DMICBI DMICBI DPWD AS1LO AS1BYP BMICBI WPEN ASSEN AS1 RW

RW

RW

0

0

0

Description Selects high voltage output voltage 0: 2.85V 1: 2.8V High voltage enable for micdetection 0: Disable 1: Enable Remote sense to bandgap ground 0: Disable

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Page 274 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

9

RG_AUDMICBIAS1DCSW1NEN

8

RG_AUDMICBIAS1DCSW1PEN

6:4

RG_AUDMICBIAS1VREF

2

RG_AUDMICBIAS1LOWPEN

1

RG_AUDMICBIAS1BYPASSEN

0

RG_AUDPWDBMICBIAS1

0000252A Bit

Name Type Reset

Description 1: Enable MIC Bias 1 DC couple switch 1N 0: Off 1: On MIC Bias 1 DC couple switch 1P 0: Off 1: On Selects MIC Bias 1 output voltage 000: 1.7V 001: 1.8V 010: 1.9V 011: 2.0V 100: 2.1V 101: 2.5V 110: 2.6V 111: 2.7V Enables MIC Bias 1 LowPower 0: Normal mode 1: Low power mode MIC Bias 1 BYPASS 0: Disable 1: Enable MIC Bias 1 power down 0: Power down 1: Power on

AUDENC_ANA_CON17 15

14

13

12

11

RG_AUDMICBIASSPARE

RW 0

0

0

0

Bit(s) 15:12 10

Name RG_AUDMICBIASSPARE RG_AUDMICBIAS2DCSW3NEN

9

RG_AUDMICBIAS2DCSW3P2EN

8

RG_AUDMICBIAS2DCSW3P1EN

6:4

RG_AUDMICBIAS2VREF

MediaTek Proprietary and Confidential.

AUDENC Control Register 17 10

9

8

RG_AU RG_AU RG_AU DMICBI DMICBI DMICBI AS2DC AS2DC AS2DC SW3NE SW3P2 SW3P1 N EN EN RW RW RW 0

0

0

7

6

0000 5

4

RG_AUDMICBIAS2VREF

RW 0

0

0

3

2

1

0

RG_AU RG_AU RG_AU DMICBI DMICBI DPWD AS2LO AS2BYP BMICBI WPEN ASSEN AS2 RW

RW

RW

0

0

0

Description MIC bias spare registers MIC Bias 2 DC couple switch 3N 0: Off 1: On MIC Bias 2 DC couple switch 3P2 0: Off 1: On MIC Bias 2 DC couple switch 3P1 0: Off 1: On Selects MIC Bias 2 output voltage 000: 1.7V 001: 1.8V 010: 1.9V 011: 2.0V

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 275 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

2

RG_AUDMICBIAS2LOWPEN

1

RG_AUDMICBIAS2BYPASSEN

0

RG_AUDPWDBMICBIAS2

0000252C Bit

Description 100: 2.1V 101: 2.5V 110: 2.6V 111: 2.7V Enables MIC Bias 2 LowPower 0: Normal mode 1: Low power mode MIC Bias 2 BYPASS 0: Disable 1: Enable MIC Bias 2 power down 0: Power down 1: Power on

AUDENC_ANA_CON18 15

14

13

12

11

AUDENC Control Register 18 10

9

8

7

6

0000 5

RG_AU RG_AC DACCD RG_AC RG_EIN RG_AU RG_AU CDET2 RG_EIN RG_EIN RG_SW RG_SW RG_AC ETMIC CDET2 T0CON DACCD DACCD AUXRE T0HIRE T0NOH BUFSW BUFM CDETSE Name BIAS3P AUXSW FIGACC ETTVDE ETVTH SBYPAS NB YS EN ODSEL L ULLLO EN DET T BCAL S W RW RW RW RW RW RW RW RW RW RW RW Type 0 0 0 0 0 0 0 0 0 0 0 Reset

Bit(s) 15

Name RG_AUDACCDETMICBIAS3PULLLOW

14

RG_ACCDET2AUXSWEN

13

RG_ACCDET2AUXRESBYPASS

12

RG_EINT0HIRENB

11

RG_EINT0CONFIGACCDET

10

RG_EINT0NOHYS

9

RG_SWBUFSWEN

8

RG_SWBUFMODSEL

7

RG_ACCDETSEL

MediaTek Proprietary and Confidential.

4

3

2

RG_AU RG_AU RG_AU DACCD DACCD DACCD ETMIC ETVIN1 ETVTH BIAS2P PULLLO ACAL ULLLO W W RW RW RW 0 0 0

1

0

RG_AU DACCD ETMIC BIAS1P ULLLO W RW 0

RG_AU DACCD ETMIC BIAS0P ULLLO W RW 0

Description Pulls low MIC Bias 3 pads when MICBIAS is off 0: Disable 1: Enable Enables switch of ACCDET to AUXADC 0: Off 1: On Bypasses ACCDET to AUXADC resistors 0: Normal 1: Bypass Selects EINT0 High R 0: 2M 1: 500k Internal connection between HP_EINT and VDD 0: Disable 1: Enable EINT0 comparator no hysteresis 0: Disable (with hysteresis) 1: Enable (without hysteresis) Switch buffer turn on SW mode control for ACCDET to AUXADC 0: Power down 1: Power on Buffer power control 0: Hardware mode 1: Software mode Selects ACCDET input 0: ACCDET pin 1: MICP pin

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Page 276 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 6

Name RG_AUDACCDETTVDET

5 4 3

RG_AUDACCDETVTHBCAL RG_AUDACCDETVTHACAL RG_AUDACCDETVIN1PULLLOW

2

RG_AUDACCDETMICBIAS2PULLLOW

1

RG_AUDACCDETMICBIAS1PULLLOW

0

RG_AUDACCDETMICBIAS0PULLLOW

0000252E Bit

AUDENC_ANA_CON19 15

14

13

12

RG_FD RG_FD RG_FD RG_AN VIN1PP ALOGF Name EINT1T EINT0T ULLLO YPE YPE DEN W RW RW RW RW Type

Reset

0

0

0

0

Bit(s) 15

Name RG_FDEINT1TYPE

14

RG_FDEINT0TYPE

13

RG_FDVIN1PPULLLOW

12

RG_ANALOGFDEN

10

RG_MTEST_CURRENT

9

RG_MTEST_SEL

8

RG_MTEST_EN

7:4

2

Description Puts audio accessory detection into TV mode 0: Disable 1: Enable Audio accessory detection voltage threshold B calibration Audio accessory detection voltage threshold A calibration Pulls low VIN1 pads when MICBIAS is off 0: Disable 1: Enable Pulls low MIC Bias 2 pads when MICBIAS is off 0: Disable 1: Enable Pulls low MIC Bias 1 pads when MICBIAS is off 0: Disable 1: Enable Pulls low MIC Bias 0 pads when MICBIAS is off 0: Disable 1: Enable

RG_EINTCOMPVTH

RG_EINT1NOHYS

MediaTek Proprietary and Confidential.

11

AUDENC Control Register 19 10

9

8

7

RG_MT RG_MT RG_MT EST_CU EST_SE EST_EN RRENT L RW

RW

RW

0

0

0

6

0000 5

4

RW 0

0

2

1

0

RG_EIN RG_EIN RG_EIN T1CON T1NOH T1HIRE FIGACC YS NB DET RW RW RW

RG_EINTCOMPVTH

0

3

0

0

0

0

Description Analog path fast discharge: EINT1 type 0: Default open 1: Default close Analog path fast discharge: EINT0 type 0: Default open 1: Default close Analog path fast discharge: pull low VIN1P with ESD MOS 0: Disable 1: Enable Analog path fast discharge 0: Disable 1: Enable Moisture test mode using current mode 0: Normal mode 1: Current sinks to PAD_HP_EINT Selects moisture test mode 0: PAD_HP_EINT 1: PAD_ACCDET Enables moisture test mode 0: Normal mode 1: Moisture test current mode (ACCDET to AUXADC should be off.) EINT comparator threshold 0: 6/8 => 2.4V 1: 5/8 => 2V EINT1 comparator no hysteresis

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Page 277 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

1

RG_EINT1HIRENB

0

RG_EINT1CONFIGACCDET

00002530

AUDENC_ANA_CON20 15

Bit

14

13

Name

RG_EINT1CTURBO

Type Reset

0

Bit(s) 15:13 12 11 10 9 8 7:5 4 3 2 1 0

0

AUDENC Control Register 20 10

14

0

0

13

0

0

12

0

11

7

6

0000 5

RG_EINT0CTURBO

0

RW 0

0

4

3

2

1

0

RG_EIN RG_EIN RG_EIN RG_EIN RG_EIN T0INVE T0CMP T0CMP T0CEN T0EN N MEN EN RW RW RW RW RW 0 0 0 0 0

0

AUDENC Control Register 21 8

7

0000

10

9

6

5

4

3

2

1

0

0

RG_ACCDETSPARE RW 0 0 0 0

0

0

0

0

0

0

6

5

4

3

2

1

0

0

RG_AUDENCSPAREVA30 RW 0 0 0 0

0

0

Description Spare control bits for ACCDET

12

13

0

RG_AUDENCSPAREVA18 RW 0 0 0 0

Name RG_AUDENCSPAREVA18 RG_AUDENCSPAREVA30

11

AUDENC Control Register 22

14

MediaTek Proprietary and Confidential.

8

Description

AUDENC_ANA_CON22 15

9

RG_EIN RG_EIN RG_EIN RG_EIN RG_EIN T1INVE T1CMP T1CMP T1CEN T1EN N MEN EN RW RW RW RW RW 0 0 0 0 0

Name RG_ACCDETSPARE

00002534

Bit(s) 15:8 7:0

11

AUDENC_ANA_CON21 15

Bit Name Type Reset

Bit Name Type Reset

RW 0

12

Name RG_EINT1CTURBO RG_EINT1INVEN RG_EINT1CEN RG_EINT1EN RG_EINT1CMPMEN RG_EINT1CMPEN RG_EINT0CTURBO RG_EINT0INVEN RG_EINT0CEN RG_EINT0EN RG_EINT0CMPMEN RG_EINT0CMPEN

00002532

Bit(s) 15:0

Description 0: Disable (with hysteresis) 1: Enable (without hysteresis) Selects EINT1 High R 0: 2M 1: 500k Internal connection between PAD_ACCDET and VDD 0: Disable 1: Enable (EINT1 connected with ACCDET pin and ACCDETSEL should be 1.)

10

9

0

8

0

7

0

0000

Description Spare control bits for AVDD18 voltage domain Spare control bits for AVDD30 voltage domain

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 278 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00002536

AUDENC_ANA_CON23 15

Bit

Description

14

13

12

11

AUDENC Control Register 23 10

9

8

7

Name

RG_SPARE_VOW

Type Reset

RW

Bit(s) 9:7 6

0

Name RG_SPARE_VOW RG_VOWCLK_SEL_EN_VOW

5

RG_CLKAND_EN_VOW

4

RG_CLKSQ_EN_VOW

3

RG_AUDIO_VOW_EN

2

RG_CM_REFGENSEL

1

RG_CLKSQ_IN_SEL_TEST

0

RG_CLKSQ_EN

00002588 Bit

RG_AU DHPRB SCCUR Name RENT_ VAUDP 32 RW Type 0 Reset

Bit(s) 15 14 13 12 11:10

14

13

12

0

0000 5

4

3

1

0

RG_VO RG_CLK RG_AU RG_CLK RG_CLK RG_CM RG_CL WCLK_ AND_E DIO_V SQ_IN_ SQ_EN _REFGE KSQ_E SEL_EN N_VO OW_E SEL_TE _VOW NSEL N _VOW W N ST RW RW RW RW RW RW RW 0

0

0

0

0

0

11

4

3

2

1

AUDDEC Control Register 0 10

9

8

7

6

0

0000 5

RG_AU RG_AU RG_AU RG_AU RG_AU RG_AU RG_AU RG_AU DHPLB DHPRP DHPLP DHPRS DHPLS RG_AUDHPRM RG_AUDHPLM DHPRP DHPLP D_DAC SCCUR WRUP_ WRUP_ CDISAB CDISAB UXINPUTSEL_V UXINPUTSEL_V WRUP_ WRUP_ _PWL_ RENT_ IBIAS_ IBIAS_ LE_VA LE_VA AUDP32 AUDP32 VAUDP VAUDP UP_VA VAUDP VAUDP VAUDP UDP32 UDP32 32 32 32 32 32 32 RW RW RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0

Name RG_AUDHPRBSCCURRENT_VAUDP32 RG_AUDHPLBSCCURRENT_VAUDP32 RG_AUDHPRSCDISABLE_VAUDP32 RG_AUDHPLSCDISABLE_VAUDP32 RG_AUDHPRMUXINPUTSEL_VAUDP32

MediaTek Proprietary and Confidential.

2

Description VOW spare Selects VOW CLK source 0: AND gate out 1: VOW CLKSQ out Enables VOW AND gate CLK 0: Disable 1: Enable Enables VOW CLK 0: Disable 1: Enable Enables AUDENC XO VOW 0: Disable 1: Enable Selects audio uplink common voltage 0: Default 1: Selection Audio CLK source 0: Use internal CLK (DCXO) 1: Use external CLK Enables CLKSQ 0: Off 1: On

AUDDEC_ANA_CON0 15

0

6

0

RG_AU RG_AU RG_AU D_DAC DDACR DDACL _PWR_ PWRUP PWRU UP_VA _VAUD P_VAU 32 P32 DP32 RW 0

RW 0

RW 0

Description Audio right headphone BSC current Audio left headphone BSC current Disables headphone right short circuit protection Disables headphone left short circuit protection Selects audio right headphone input multiplexor Positive/negative pins:

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 279 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

9:8

RG_AUDHPLMUXINPUTSEL_VAUDP32

7 6 5 4 3

RG_AUDHPRPWRUP_IBIAS_VAUDP32 RG_AUDHPLPWRUP_IBIAS_VAUDP32 RG_AUDHPRPWRUP_VAUDP32 RG_AUDHPLPWRUP_VAUDP32 RG_AUD_DAC_PWL_UP_VA32

2

RG_AUD_DAC_PWR_UP_VA32

1

RG_AUDDACRPWRUP_VAUDP32

0

RG_AUDDACLPWRUP_VAUDP32

0000258A Bit

Name

Type Reset

Description 00: Open/Open 01: LOLP/LOLN 10: IDACRP/IDACRN 11: HSP/HSN (test mode) Selects audio left headphone input multiplexor Positive/negative pins: 00: Open/Open 01: LOLP/LOLN 10: IDACRP/IDACRN 11: HSP/HSN (test mode) Powers up audio right headphone bias Powers up audio left headphone bias Powers up audio right headphone Powers up audio left headphone Power down control for left channel audio biasgen 0: Power down 1: Enable Power down control for right channel audio biasgen 0: Power down 1: Enable Power down control for right-channel audio DAC 0: Power down 1: Enable Power down control for left-channel audio DAC 0: Power down 1: Enable

AUDDEC_ANA_CON1 15

14

13

12

11

RG_HPROUTSTGCTRL_ VAUDP32

RW 0

0

0

Bit(s) 14:12

Name RG_HPROUTSTGCTRL_VAUDP32

10:8

RG_HPLOUTSTGCTRL_VAUDP32

MediaTek Proprietary and Confidential.

AUDDEC Control Register 1 10

9

8

7

6

0000 5

RG_HP RG_HP RG_HP RSHOR LSHOR RAUXF RG_HPLOUTSTGCTRL_V T2HPR T2HPLA BRSW_ AUDP32 AUX_E UX_EN EN_VA N_VAU _VAUD UDP32 DP32 P32 RW RW RW RW 0

0

0

0

0

0

4

3

2

1

0

RG_AU RG_AU RG_AU RG_HP RG_AU DHPRO DHPLO DHPLO LAUXF DHPRO UTAUX UTAUX UTPW BRSW_ UTPWR PWRUP PWRUP RUP_V EN_VA UP_VA _VAUD _VAUD AUDP3 UDP32 UDP32 P32 P32 2 RW RW RW RW RW 0

0

0

0

0

Description Selects audio right headphone output stage 000: 1x 001: 2x 010: 3x 011: 4x 100: 5x 101: 6x 110: 7x 111: 8x Selects audio left headphone output stage 000: 1x 001: 2x 010: 3x 011: 4x

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 280 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

7 6 5 4 3 2 1 0

Name

RG_HPRSHORT2HPRAUX_EN_VAUDP32 RG_HPLSHORT2HPLAUX_EN_VAUDP32 RG_HPRAUXFBRSW_EN_VAUDP32 RG_HPLAUXFBRSW_EN_VAUDP32 RG_AUDHPROUTAUXPWRUP_VAUDP32 RG_AUDHPLOUTAUXPWRUP_VAUDP32 RG_AUDHPROUTPWRUP_VAUDP32 RG_AUDHPLOUTPWRUP_VAUDP32

0000258C Bit

AUDDEC_ANA_CON2 15

14

13

12

Description 100: 5x 101: 6x 110: 7x 111: 8x Audio right headphone main & aux output stages short enable Audio left headphone main and aux output stages short enable Enables audio right headphone aux feedback resistor for audio depop Enables audio left headphone aux feedback resistor Powers up audio right headphone aux output stage Powers up audio left headphone aux output stage Powers up audio right headphone main output stage Powers up audio left headphone main output stage

AUDDEC Control Register 2

11

10

9

8

7

6

0000 5

4

3

RG_AU RG_AU RG_HP RG_HPI RG_HPI RG_AU DREFN DHPTRI OUTPU NPUTR NPUTS DHPST RG_HPPSHORT2VCM_V _DERES RG_HPROUTPUTSTBEN TRESET ESET0_ TBENH ARTUP Name M_EN_ AUDP32 _EN_V H_VAUDP32 VAUDP 0_VAU VAUDP _VAUD _VAUD AUDP3 32 DP32 32 P32 P32 2 RW RW RW RW RW RW RW RW Type

Reset

0

0

0

0

0

Bit(s) 15

Name RG_AUDHPTRIM_EN_VAUDP32

14:12 11

RG_HPPSHORT2VCM_VAUDP32 RG_HPOUTPUTRESET0_VAUDP32

10

RG_HPINPUTRESET0_VAUDP32

9

RG_HPINPUTSTBENH_VAUDP32

8 7 6:4

RG_AUDREFN_DERES_EN_VAUDP32 RG_AUDHPSTARTUP_VAUDP32 RG_HPROUTPUTSTBENH_VAUDP32

2:0

RG_HPLOUTPUTSTBENH_VAUDP32

0

0

0

0

0

0

0

2

1

0

RG_HPLOUTPUTSTBEN H_VAUDP32

RW 0

0

0

Description Enable control of trim circuit of HP 0: Disable trim circuit 1: Enable trim circuit HP driver positive output stage short to AU_REFN HPL/R driver SE output reset to 0V ground 0: No reset 1: Reset HP driver input reset to ground 0: No reset 1: Reset HP driver input stability enhancement option 0: No enhancement 1: Enhance HP ESD resistor @AU_REFN short enable Forces a startup mode in HP Amps if required Enhances HPR output stage STB [2]: Not used [1]: HPRN 800ohm to GND [0]: HPRP 450ohm to GND Enhances HPL output stage STB [2]: Not used [1]: HPLN 800ohm to GND

D

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 281 of 1067

MT6359 PMIC Datasheet Confidential A 0000258E

AUDDEC_ANA_CON3 15

Bit

14

13

12

AUDDEC Control Register 3

11

Type Reset

RG_AUDHPRFINETRIM _VAUDP32 RW 0 0 0

Bit(s) 15:13

Name RG_AUDHPRFINETRIM_VAUDP32

12:8

RG_AUDHPRTRIM_VAUDP32

7:5

RG_AUDHPLFINETRIM_VAUDP32

4:0

RG_AUDHPLTRIM_VAUDP32

Name

00002590 Bit

14

0

13

0

RW 0

0

8

12

0

0

7

6

0000 5

RG_AUDHPLFINETRIM_ VAUDP32 RW 0 0 0

4

3

2

1

0

RG_AUDHPLTRIM_VAUDP32

0

0

RW 0

0

2

1

0

Description Fine-trims offset voltage of HPR. sign bit format 000~011: 0V~0.12 mV, 0.04 mV/step 100~111: 0V~-0.12 mV, 0.04 mV/step Trims offset voltage of HPR. sign bit format 00000~01111: 0V~2.7 mV, 0.18 mV/step 10000~11111: 0V~-2.7 mV, 0.18 mV/step Fine-trims offset voltage of HPL. sign bit format 000~011: 0V~0.12 mV, 0.04 mV/step 100~111: 0V~-0.12 mV, 0.04 mV/step Trims offset voltage of HPL. sign bit format 00000~01111: 0V~2.7 mV, 0.18 mV/step 10000~11111: 0V~-2.7 mV, 0.18 mV/step

AUDDEC Control Register 4

11

10

9

8

7

6

0000 5

4

3

0

RG_AUDHPHFC OMPBUFGAINS EL_VAUDP32

RG_AUDHPHFCOMPRE SSEL_VAUDP32

RG_AUDHPLFCOMPRES SEL_VAUDP32

RG_AUDHPDIFFINPBIA SADJ_VAUDP32

RW

RW

RW

RW

0

0

Bit(s) 15 13:12

Name RG_AUDHPCOMP_EN_VAUDP32 RG_AUDHPHFCOMPBUFGAINSEL_VA UDP32

10:8 6:4 2:0

RG_AUDHPHFCOMPRESSEL_VAUDP32 RG_AUDHPLFCOMPRESSEL_VAUDP32 RG_AUDHPDIFFINPBIASADJ_VAUDP32

MediaTek Proprietary and Confidential.

9

RG_AUDHPRTRIM_VAUDP32

AUDDEC_ANA_CON4 15

RG_AU DHPCO Name MP_EN _VAUD P32 RW Type

Reset

10

0

0

0

0

0

0

0

0

0

Description Reserved Selects HP feedback cap 00: 15 pF 01: 10.5 pF 10: 7.5 pF 11: 3 pF Reserved Reserved Selects HP driver input differential pair bias current 000: 20u 001: 40u 010: 80u 011: 160u 100: 240u 101: 280u 110: 320u 111: 360u

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Page 282 of 1067

MT6359 PMIC Datasheet Confidential A 00002592

AUDDEC_ANA_CON5 15

Bit

14

13

12

AUDDEC Control Register 5

11

10

9

8

7

Type Reset

0

Name RG_AUDHPDEDMGAINADJ_VAUDP32 RG_AUDHPDECMGAINADJ_VAUDP32

00002594 Bit

4

3

15

14

13

12

11

10

9

8

7

6

5

RW

RW

RW

RW

RW

RW

0

0

0

0

0

0

0

10

RG_HSOUTPUTRESET0_VAUDP32

9

RG_HSINPUTRESET0_VAUDP32

8

RG_HSINPUTSTBENH_VAUDP32

7

RG_HSOUTPUTSTBENH_VAUDP32

6 5 4 3:2

RG_AUDHSSTARTUP_VAUDP32 RG_AUDHSBSCCURRENT_VAUDP32 RG_AUDHSSCDISABLE_VAUDP32 RG_AUDHSMUXINPUTSEL_VAUDP32

1 0

RG_AUDHSPWRUP_IBIAS_VAUDP32 RG_AUDHSPWRUP_VAUDP32

0

RG_AUDHPDECMGAIN ADJ_VAUDP32 RW

0

0

0

0

0000 RG_AU DHSBS CCURR ENT_V AUDP3 2 RW

Name RG_HSOUT_SHORTVCM_VAUDP32

MediaTek Proprietary and Confidential.

1

AUDDEC Control Register 6

RG_HS RG_HS RG_HSI RG_HSI RG_HS RG_AU OUT_S OUTPU NPUTR NPUTS OUTPU DHSST HORTV TRESET ESET0_ TBENH TSTBEN ARTUP CM_VA 0_VAU VAUDP _VAUD H_VAU _VAUD UDP32 DP32 32 P32 DP32 P32

Type Reset

0

2

Description Reserved Reserved

AUDDEC_ANA_CON6

Name

Bit(s) 11

0000 5

RG_AUDHPDEDMGAIN ADJ_VAUDP32 RW

Name

Bit(s) 6:4 2:0

6

4

3

2

1

0

RG_AU RG_AU RG_AU DHSSC RG_AUDHSMU DHSPW DHSP DISABL XINPUTSEL_VA RUP_IB WRUP E_VAU UDP32 IAS_VA _VAUD DP32 UDP32 P32 RW 0

RW 0

0

RW

RW

0

0

Description Short HS output to VCM (DCC: 0V; ACC: 1.4V) 0: Not short to VCM 1: Short to VCM HS driver DE outputs reset to 0V ground 0: No reset 1: Reset HS driver DE inputs reset to 0V ground 0: No reset 1: Reset HS driver input stability enhancement option 0: No enhancement 1: Enhance HS driver output stability enhancement option 0: No enhancement 1: Enhance Forces a startup mode in HS Amp if required Audio handset BSC current Disables headset short circuit protection Selects audio handset input multiplexor Positive/negative pins: 00: Open/Open 01: Voice playback (T-DAC) 10: Voice playback (L-DAC) 11: LOLP/LOLN (test mode) Powers up audio headset bias Powers up audio headset

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 283 of 1067

MT6359 PMIC Datasheet Confidential A 00002596 Bit

AUDDEC_ANA_CON7 15

14

12

AUDDEC Control Register 7

11

10

9

8

7

6

0000 5

4

3

2

1

0

RG_AU RG_AU RG_AU RG_AU RG_LO RG_LO RG_LOI RG_LO RG_LOI RG_AU RG_AU RG_AU DLOLBS DLOLP D_DAC DDACT OUT_S OUTPU NPUTR OUTPU NPUTS DLOST DLOLSC RG_AUDLOLM DLOLP CCURR WRUP_ _PWT_ PWRUP HORTV TRESET ESET0_ TSTBEN TBENH ARTUP DISABL UXINPUTSEL_V WRUP ENT_V IBIAS_ UP_VA _VAUD CM_VA 0_VAU VAUDP H_VAU _VAUD _VAUD E_VAU AUDP32 _VAUD AUDP3 VAUDP 32 P32 UDP32 DP32 32 DP32 P32 P32 DP32 P32 2 32 RW RW RW RW RW RW RW RW RW RW RW RW RW

Name

Type Reset Bit(s) 13

13

0

0

0

Name RG_AUD_DAC_PWT_UP_VA32

12

RG_AUDDACTPWRUP_VAUDP32

11

RG_LOOUT_SHORTVCM_VAUDP32

10

RG_LOOUTPUTRESET0_VAUDP32

9

RG_LOINPUTRESET0_VAUDP32

8

RG_LOOUTPUTSTBENH_VAUDP32

7

RG_LOINPUTSTBENH_VAUDP32

6 5 4 3:2

RG_AUDLOSTARTUP_VAUDP32 RG_AUDLOLBSCCURRENT_VAUDP32 RG_AUDLOLSCDISABLE_VAUDP32 RG_AUDLOLMUXINPUTSEL_VAUDP32

1 0

RG_AUDLOLPWRUP_IBIAS_VAUDP32 RG_AUDLOLPWRUP_VAUDP32

MediaTek Proprietary and Confidential.

0

0

0

0

0

0

0

0

0

0

0

Description Power down control for third channel audio biasgen 0: Power down 1: Enable Power down control for third channel audio DAC 0: Power down 1: Enable Short LO output to VCM (DCC: 0V; ACC: 1.4V) 0: Not short to VCM 1: Short to VCM LOL/R driver SE output reset to 0V ground 0: No reset 1: Reset LO driver input reset to ground 0: No reset 1: Reset LO driver output stability enhancement option 0: No enhancement 1: Enhance LO driver input stability enhancement option 0: No enhancement 1: Enhance Forces a startup mode in LO Amps if required Audio left LO buffer BSC current Disables LO buffer left short circuit protection Selects audio left LO buffer input multiplexor Positive/negative pins: 00: Open/Open 01: Audio playback (L-DAC) 10: Audio playback (T-DAC) 11: HPL/HPR (test mode) Powers up audio left LO buffer bias power up Powers up audio left LO buffer

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 284 of 1067

MT6359 PMIC Datasheet Confidential A 00002598

AUDDEC_ANA_CON8 15

Bit

14

13

AUDDEC Control Register 8

11

Type Reset

0

0

RG_AUDHPSPKDET_INPUTMUXSEL_V AUDP32

6 5:4

RG_AUDTRIMBUF_EN_VAUDP32 RG_AUDTRIMBUF_GAINSEL_VAUDP3 2

3:0

RG_AUDTRIMBUF_INPUTMUXSEL_V AUDP32

0000259A

Bit(s) 15:8

9

0

Name RG_AUDHPSPKDET_EN_VAUDP32 RG_AUDHPSPKDET_OUTPUTMUXSEL_V AUDP32

9:8

Bit Name Type Reset

10

8

7

RG_AU RG_AUDHPSPK DHPSP RG_AUDHPSPK DET_OUTPUTM KDET_E DET_INPUTMU UXSEL_VAUDP N_VAU XSEL_VAUDP32 32 DP32 RW RW RW

Name

Bit(s) 12 11:10

12

AUDDEC_ANA_CON9 15

0

14

0

13

12

0000 5

4

3

2

1

0

RG_AU DTRIM RG_AUDTRIMB RG_AUDTRIMBUF_INPUTMUXS BUF_E UF_GAINSEL_V EL_VAUDP32 N_VAU AUDP32 DP32 RW RW RW

0

0

0

0

0

0

0

0

Description Enables audio headphone speaker detection Selects audio headphone speaker detection output mux 00: Open 01: HPL 10: HPR 11: Unused Enables audio headphone speaker detection input mux 00: Open 01: DACLP 10: DACLN 11: DACRP Enables audio offset trimming buffer Selects audio offset trimming buffer gain 00: 0dB 01: 6dB 10: 12dB 11: 18dB Selects audio offset trimming buffer mux 0000: Open 0001: HPL 0010: HPR 0011: HSP 0100: HSN 0101: LOLP 0110: LOLN 0111: LORP 1000: LORN 1001: AVSS32 1010~1111: Unused

AUDDEC Control Register 9 10

9

RG_ABIDEC_RSVD0_VAUDP32 RW 0 0 0 0

Name RG_ABIDEC_RSVD0_VAUDP32

MediaTek Proprietary and Confidential.

11

0

6

0

8

0

7

0

0000

6

5

2

1

0

0

RG_ABIDEC_RSVD0_VA32 RW 0 0 0 0

4

3

0

0

Description Reserved one byte in VAUDP32 domain [7:4]: HP aux loop gain setting [3]: Enable HPR aux CMFB loop [2]: Enable HPL aux CMFB loop [1]: Enable HPR/L main CMFB loop [0]: Enable HPR/L main2 CMFB loop

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 285 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 7:0

Name RG_ABIDEC_RSVD0_VA32

0000259C Bit Name Type Reset

Description Reserved one byte in VA32 domain [6:4]: NV-regulator vout selection [3:1]: LDO vout selection 000: 1.607V 001: 1.456V 010: 1.506V 011: 1.557V 100: 1.657V 101: 1.707V 110: 1.757V 111: 1.807V [0]: Enable low-noise mode of DAC

AUDDEC_ANA_CON10 15

0

14

0

13

12

AUDDEC Control Register 10 10

9

RG_ABIDEC_RSVD2_VAUDP32 RW 0 0 0 0

Bit(s) 15:8

Name RG_ABIDEC_RSVD2_VAUDP32

7:0

RG_ABIDEC_RSVD1_VAUDP32

MediaTek Proprietary and Confidential.

11

0

8

0

7

0

6

0

0000 5

4

3

2

RG_ABIDEC_RSVD1_VAUDP32 RW 0 0 0 0

1

0

0

0

Description Reserved one byte in VAUDP32 domain [7]: Select HP feedback switch bulk 0: Internal NCP 1: External NCP [6:4]: Select HS output stage 000: 1x 001: 2x 010: 3x 011: 4x 100: 5x 101: 6x 110: 7x 111: 8x [3]: DAC low-noise filter switch toggle bit (SW mode) [2]: Select DAC low-noise filter switch control 0: HW mode 1: SW mode [1]: Enable DAC low-noise filter low-leakage switch [0]: Enable DAC low-noise filter Reserved one byte in VAUDP32 domain [7]: Enable HPN output 4kohm to GND [6:5]: Select HP damping adjustment 00: 10kohm 01: 20kohm 10: 30kohm 11: 50kohm [4:3]: Select HP Input diff pair bias 00: 40uA 01: 80uA 10: 120uA 11: 160uA [2]: Enable HP damping circuit [1]: Select HPR CMFB resister PW 0: AC 1: DC

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Page 286 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

0000259E

AUDDEC_ANA_CON11 15

Bit

Description [0]: Select HPL CMFB resister PW 0: AC 1: DC

14

13

Name

12

11

9

8

7

6

5

4

1

0

0

1

Name RG_AUDBIASADJ_0_VAUDP32

3

RG_AUDZCDCLKSEL_VAUDP32

2:0

RG_AUDZCDMUXSEL_VAUDP32

000025A0

0

14

13

12

11

0

1

0

0

Type Reset

9

8

1

Name RG_AUDIBIASPWRDN_VAUDP32

MediaTek Proprietary and Confidential.

1

0

0

0

2

1

0

0

1

AUDDEC Control Register 12 10

7

6

RG_AU DIBIAS PWRD N_VAU DP32 RW

Name

2

0

Description Audio bias adjustment 0 Bits: [2:0] Headphone Left/Right DR bias current setting [5:3] Handset DR bias current setting. DR bias settings [8:6] Line-out DR bias current setting. DR bias settings 000: 4 uA 001: 5 uA 010: 6 uA 011: 7 uA 100: 8 uA 101: 9A 110: 10 uA 111: 11 uA Increases ZCD comparator speed 0: Normal speed 1: Improved speed Selects zero crossing detection mux 000: LOL 001: Unused 010: Handset 011: Unused 100: Bypass ZCD

AUDDEC_ANA_CON12 15

3

RG_AU DZCDC RG_AUDZCDMUXSEL_V LKSEL_ AUDP32 VAUDP 32 RW RW

RW 0

Bit(s) 15:7

Bit(s) 8

10

4900

RG_AUDBIASADJ_0_VAUDP32

Type Reset

Bit

AUDDEC Control Register 11

0155 5

4

3

RG_AUDBIASADJ_1_VAUDP32

RW 0

1

0

1

0

1

Description Power down control for IbiasDistrib circuit 0: Enable 1: Disable

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 287 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 7:0

Name RG_AUDBIASADJ_1_VAUDP32

000025A2 Bit

Description Audio bias adjustment 1 Bits: [7:6] ZCD bias current setting 00: 3 uA 01: 4 uA 10: 5 uA 11: 6 uA [5:4] LOL/R ibias setting 00: 4 uA 01: 5 uA 10: 6 uA 11: 7 uA [3:2] HS ibias setting 00: 4 uA 01: 5 uA 10: 6 uA 11: 7 uA [1:0] HPL/R ibias setting 00: 4 uA 01: 5 uA 10: 6 uA 11: 7 uA

AUDDEC_ANA_CON13 15

14

13

12

11

AUDDEC Control Register 13 10

9

8

7

6

0010 5

4

RG_AU RG_AU RG_AU DGLB_L DGLB_L DGLB_ P2_VO P_VO PWRD W_EN_ W_EN_ N_VA3 VA32 VA32 2 RW RW RW

Name

Type Reset

0

Bit(s) 6

Name RG_AUDGLB_LP2_VOW_EN_VA32

5

RG_AUDGLB_LP_VOW_EN_VA32

4

RG_AUDGLB_PWRDN_VA32

2

RG_SEL_DELAY_VCORE

1

RG_SEL_DECODER_96K_VA32

0

RG_RSTB_DECODER_VA32

MediaTek Proprietary and Confidential.

0

1

3

2

1

0

RG_SEL RG_SEL RG_RS _DECO _DELAY TB_DE DER_96 _VCOR CODER K_VA3 E _VA32 2 RW RW RW 0

0

0

Description Enable for AUDGLB VOW low-power mode2: OP and self-bias will be down and IREF from PMU_TOP Enable for AUDGLB VOW low-power mode: OP and self-bias should be on, IREF to VOW is 1/4. Power down control for audio global bias circuit 0: Enable 1: Disable; default on Selects AFIFO read clock delay 0: 5 ns 1: 10 ns Selects audio DAC clock 0: 6.5 MHz 1: 13 MHz Audio decoder reset 0: Reset 1: Normal

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 288 of 1067

MT6359 PMIC Datasheet Confidential A 000025A4

AUDDEC_ANA_CON14 15

Bit

14

Name

12

11

0

0

0

0

0

Name RG_AUDPMU_RSVD_VA18

RG_NVREG_PULL0V_VAUDP32 RG_NVREG_EN_VAUDP32 RG_LCLDO_DEC_REMOTE_SENSE_VA 18

1 0

RG_LCLDO_DEC_PDDIS_EN_VA18 RG_LCLDO_DEC_EN_VA32

00002608

8

7

6

14

13

0000 5

4

3

0

RW

RW

0

0

1

0

0

2

1

ZCD Control Register 0 12

11

0

RG_LCL RG_LCL DO_DE RG_LCL DO_DE C_REM DO_DE C_PDDI OTE_SE C_EN_ S_EN_ NSE_V VA32 VA18 A18 RW RW RW

RG_NV RG_NV REG_P REG_E ULL0V_ N_VAU VAUDP DP32 32

0

2

0

Description Reserved 1 byte for VA18 domain [7:4] => NCP SW1~SW4 individual off control 4'b0000: On (normal operation) 4'b1111: All off [3:2] => Reserved [1:0] => CLDO power MOS on/off control 2'b00: Normal operation 2'b11: CLDO Vout = AVDD18_AUD NVREG output pulled to 0V when PD Enable for NVREG Selects LCLDO_DEC remote sense function 0: Local sense 1: Remote sense Enables LCLDO_DEC power down discharge Enable for LCLDO_DEC

ZCD_CON0 15

10

9

8

7

0000 6

5

4

3

0

RG_AU DZCDTI RG_AU RG_AUDZCDGA RG_AUDZCDGAINSTEP MEOUT DZCDE INSTEPSIZE TIME MODES NABLE EL RW RW RW RW

Name Type Reset Bit(s) 6

9

RW 0

5 4 2

Bit

AUDDEC Control Register 14 10

RG_AUDPMU_RSVD_VA18

Type Reset Bit(s) 15:8

13

0

Name RG_AUDZCDTIMEOUTMODESEL

5:4

RG_AUDZCDGAINSTEPSIZE

3:1

RG_AUDZCDGAINSTEPTIME

MediaTek Proprietary and Confidential.

0

0

0

0

0

0

Description If no zero crossings are detected over a period of 30ms/5ms, a timeout will occur and the ZCD block enter SILENT mode. 0: 30 ms 1: 5 ms Gain step size to change the internal gain of ZCD 00: 1 dB 01: 2 dB 10: 4 dB 11: 8 dB Gain step time to change the internal gain of ZCD 000: 0u s 001: 250 us 010: 500 us 011: 1 ms 100: 2 ms 101: 4 ms

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 289 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

0

Name

Description 110: 8 ms 111: 16 ms Enables zero crossing detection (ZCD) function 0: Disable 1: Enable

RG_AUDZCDENABLE

0000260A

ZCD_CON1 15

Bit

14

13

ZCD Control Register 1 12

Name Type Reset

10

9

8

0F9F 6

5

4

3

1

4:0

RG_AUDLOLGAIN

0000260C

14

1

13

1

1

1

1

1

11

10

9

8

7

4

3

2

1

5

1

RG_AUDHPLGAIN

0000260E

1

14

13

RW 1

1

1

1

1

1

1

Description 00000: +8 dB 00001: +7 dB 10010:-10 dB 11111: -40 dB (mute) 00000: +8 dB 00001: +7 dB 10010:-10 dB 11111: -40 dB (mute)

ZCD_CON3 15

1

0

RG_AUDHPLGAIN

RW

4:0

1

0F9F 6

RG_AUDHPRGAIN

Name RG_AUDHPRGAIN

0

RW 1

ZCD Control Register 2 12

Name Type Reset Bit(s) 11:7

1

Description 00000: +8 dB 00001: +7 dB 10010:-10 dB 11111: -40 dB (mute) 00000: +8 dB 00001: +7 dB 10010:-10 dB 11111: -40 dB (mute)

ZCD_CON2 15

Bit

1

2

RG_AUDLOLGAIN

RW

Name RG_AUDLORGAIN

ZCD Control Register 3 12

11

10

9

8

Name Type Reset Bit(s) 4:0

7

RG_AUDLORGAIN

Bit(s) 11:7

Bit

11

7

001F 6

5

4

3

2

1

0

RG_AUDHSGAIN RW 1

Name RG_AUDHSGAIN

MediaTek Proprietary and Confidential.

1

1

1

1

Description 00000: +8 dB 00001: +7 dB

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 290 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00002610

ZCD_CON4 15

Bit

Description 10010:-10 dB 11111: -40 dB (mute)

14

13

ZCD Control Register 4 12

11

10

Name Type Reset

8

7

0707 6

5

4

3

2

RG_AUDIVRGAIN 1

Name RG_AUDIVRGAIN

2:0

RG_AUDIVLGAIN

00002612

14

13

Name Type Reset

1

Bit(s) 13:8 5:0

Name RG_AUDINTGAIN2 RG_AUDINTGAIN1

RW 1

1

1

2

1

0

1

1

ZCD Control Register 5 12

11

10

9

8

7

1

3F3F 6

5

4

RG_AUDINTGAIN2

3

RG_AUDINTGAIN1

RO

MediaTek Proprietary and Confidential.

0

Description 000: +5 dB 001: +4 dB 010: +3 dB 011: +2 dB 100: +1 dB 101: 0 dB 110: -1 dB 111: -2 dB 000: +5 dB 001: +4 dB 010: +3 dB 011: +2 dB 100: +1 dB 101: 0 dB 110: -1 dB 111: -2 dB

ZCD_CON5 15

1

1

RG_AUDIVLGAIN

RW

Bit(s) 10:8

Bit

9

1

1

RO 1

1

1

1

1

1

1

Description Monitor signal: Internal gain 2 Monitor signal: Internal gain 1

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 291 of 1067

MT6359 PMIC Datasheet Confidential A 00002688

ACCDET_CON0 15

Bit

14

13

12

ACCDET control register 0 11

10

Type Reset

8

0

Name AUDACCDETAUXADCSWCTRL_SEL

ACCDET_CON1

6

0000 5

4

3

2

1

0

15

14

13

12

0

ACCDET control register 1 11

10

9

8

7

6

0000 5

4

3

2

1

0

ACCDE ACCDE ACCDE ACCDE T_EINT T_EINT ACCDE ACCDE ACCDE ACCDE T_EINT T_EINT ACCDE ACCDE 1_INVE 0_INVE T_EINT T_EINT T_EINT T_EINT 1_INVE 0_INVE T_SEQ_ T_SW_ RTER_S RTER_S 1_SEQ_ 1_SW_ 0_SEQ_ 0_SW_ RTER_S RTER_S INIT EN EQ_INI EQ_INI INIT EN INIT EN W_EN W_EN T T RW RW RW RW RW RW RW RW RW RW

Name

Type Reset Bit(s) 9

7

Description Test control 1'b0: HW mode 1'b1: SW mode Selection signal of which AUXADC or ACCDET to trigger ANA voltage measurement 1'b0: AUXADC 1'b1: ACCDET

ACCDET_AUXADC_ANASWCTRL_SEL

0000268A Bit

8

ACCDE AUDAC T_AUX CDETA ADC_A UXADC NASWC SWCTR TRL_SE L_SEL L RW RW

Name

Bit(s) 9

9

0

Name ACCDET_EINT1_INVERTER_SEQ_INIT

8

ACCDET_EINT1_INVERTER_SW_EN

7

ACCDET_EINT0_INVERTER_SEQ_INIT

6

ACCDET_EINT0_INVERTER_SW_EN

5

ACCDET_EINT1_SEQ_INIT

4

ACCDET_EINT1_SW_EN

3

ACCDET_EINT0_SEQ_INIT

2

ACCDET_EINT0_SW_EN

MediaTek Proprietary and Confidential.

0

0

0

0

0

0

0

0

0

Description Initializes EINT1 inverter status default value 1'b0: Disable 1'b1: Enable Enables EINT1 inverter detection 1'b0: Disable 1'b1: Enable Initializes EINT0 inverter status default value 1'b0: Disable 1'b1: Enable Enables EINT0 inverter detection 1'b0: Disable 1'b1: Enable Initializes EINT1 status default value 1'b0: Disable 1'b1: Enable Enables EINT1 detection 1'b1: Enable Initializes EINT0 status default value 1'b0: Disable 1'b1: Enable Enables EINT0 detection

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 292 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

1

ACCDET_SEQ_INIT

0

ACCDET_SW_EN

0000268C Bit

Description 1'b0: Disable 1'b1: Enable Initializes ACCDET status default value 1'b0: normal mode 1'b1: initialized mode Enables ACCDET 1'b0: Disable 1'b1: Enable

ACCDET_CON2 15

14

13

12

ACCDET control register 2 11

10

9

8

7

6

0000 5

ACCDE ACCDE T_EINT T_EINT _CMP _CTUR MEN_P BO_PW WM_E M_EN N RW RW

Name

Type Reset

0

Bit(s) 6

Name ACCDET_EINT_CTURBO_PWM_EN

5

ACCDET_EINT_CMPMEN_PWM_EN

4

ACCDET_EINT_CMPEN_PWM_EN

3

ACCDET_EINT_EN_PWM_EN

2

ACCDET_MBIAS_PWM_EN

1

ACCDET_VTH_PWM_EN

0

ACCDET_CMP_PWM_EN

MediaTek Proprietary and Confidential.

0

4

3

2

1

0

ACCDE T_EINT _CMPE N_PW M_EN

ACCDE T_EINT _EN_P WM_E N

ACCDE T_MBI AS_PW M_EN

RW

RW

RW

RW

RW

0

0

0

0

0

ACCDE ACCDE T_VTH T_CMP _PWM _PWM _EN _EN

Description Enables PWM of DA_CTURBO 1'b0: Disable 1'b1: Enable Enables PWM of DA_EINTCMPMEN 1'b0: Disable 1'b1: Enable Enables PWM of DA_EINTCMPEN 1'b0: Disable 1'b1: Enable Enables PWM of DA_EINTEN 1'b0: Disable 1'b1: Enable Enables PWM of ACCDET MBIAS unit 1'b0: Disable 1'b1: Enable Enables PWM of ACCDET voltage threshold unit 1'b0: Disable 1'b1: Enable Enables PWM of ACCDET comparator 1'b0: Disable 1'b1: Enable

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 293 of 1067

MT6359 PMIC Datasheet Confidential A 0000268E

Bit(s) 15:0

ACCDET_CON3 15

Bit Name Type Reset

0

0

13

0

0

11

0

0

14

0

13

6

5

4

3

2

1

0

0

ACCDET_PWM_WIDTH RW 0 0 0 0

0

0

0

0

0

0

ACCDE T_FALL Name _DELA Y RW Type 0 Reset

14

ACCDET Control Register 4

12

0

0

13

11

0

9

7

6

5

4

3

2

1

0

0

ACCDET_PWM_THRESH RW 0 0 0 0

0

0

0

0

0

0

ACCDET Control Register 5 11

10

9

8

7

6

0101 5

4

3

2

1

0

0

0

0

0

0

1

ACCDET_RISE_DELAY

0

0

0

Name ACCDET_FALL_DELAY

14:0

ACCDET_RISE_DELAY

0

0

14

13

0

1

RW 0

0

Description Falling delay cycle compared to PWM waveform To make sure the plug state is stable after ACCDET is disabled, the suitable falling delay cycle is necessary. Rising delay cycle compared to PWM waveform To make sure the plug state is stable before ACCDET is enabled, the suitable rising delay cycle is necessary.

ACCDET_CON6 15

8

0000

10

Description ACCDET PWM threshold PWM output duty cycle = (PWM_THRESH + 1)/(PWM_WIDTH + 1) PWM output high time = (PWM_THRESH + 1)/32,768 sec

12

Bit(s) 15

00002694

7

Description ACCDET PWM width PWM output frequency = 32,768/(PWM_WIDTH + 1) Hz

ACCDET_CON5 15

Bit

12

ACCDET Control Register 6 11

10

9

8

7

6

0000 5

4

ACCDET_EINT_CMPME N_PWM_WIDTH RW

Name Type Reset Bit(s) 6:4

9

Name ACCDET_PWM_THRESH

00002692

8

0000

10

ACCDET_CON4 15

Bit Name Type Reset

Bit

ACCDET Control Register 3

12

Name ACCDET_PWM_WIDTH

00002690

Bit(s) 15:0

14

0

Name ACCDET_EINT_CMPMEN_PWM_WID TH

MediaTek Proprietary and Confidential.

0

0

3

2

1

0

ACCDET_EINT_CMPME N_PWM_THRESH RW 0

0

0

Description ACCDET DA_EINTCMPMEN PWM width 3'b000: 50 ms 3'b001: 80 ms 3'b010: 100 ms

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 294 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

2:0

Name

ACCDET_EINT_CMPMEN_PWM_THR ESH

00002696 Bit

Description 3'b011: 200 ms 3'b100: 400 ms 3'b101: 500 ms 3'b110: 800 ms 3'b111: 1,000 ms ACCDET DA_EINTCMPMEN PWM threshold 3'b000: 1 ms 3'b001: 2 ms 3'b010: 4 ms 3'b011: 5 ms 3'b100: 8 ms 3'b101: 10 ms 3'b110: 20 ms 3'b111: 30 ms

ACCDET_CON7 15

14

13

ACCDET Control Register 7

12

11

ACCDET_EINT_ CMPEN_PWM_ WIDTH RW

Name Type Reset

0

10

8

ACCDET_EINT_CMPEN_ PWM_THRESH

0

Bit(s) 13:12

Name ACCDET_EINT_CMPEN_PWM_WIDTH

10:8

ACCDET_EINT_CMPEN_PWM_THRESH

5:4

ACCDET_EINT_EN_PWM_WIDTH

2:0

ACCDET_EINT_EN_PWM_THRESH

MediaTek Proprietary and Confidential.

9

RW 0

0

0

7

6

0000 5

4

ACCDET_EINT_ EN_PWM_WID TH RW 0

0

3

2

1

0

ACCDET_EINT_EN_PW M_THRESH RW 0

0

0

Description ACCDET DA_EINTCMPEN PWM width 2'b00: 4 ms 2'b01: 8 ms 2'b10: 16 ms 2'b11: 32 ms ACCDET DA_EINTCMPEN PWM threshold 3'b000: 0.5 ms 3'b001: 1 ms 3'b010: 2 ms 3'b011: 3 ms 3'b100: 4 ms 3'b101: 8 ms 3'b110: 16 ms 3'b111: 32 ms ACCDET DA_EINTEN PWM width 2'b00: 4 ms 2'b01: 8 ms 2'b10: 16 ms 2'b11: 32 ms ACCDET DA_EINTEN PWM threshold 3'b000: 0.5 ms 3'b001: 1 ms 3'b010: 2 ms 3'b011: 3 ms 3'b100: 4 ms 3'b101: 8 ms 3'b110: 16 ms 3'b111: 32 ms

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 295 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00002698

Bit(s) 15:0

ACCDET_CON8 15

Bit Name Type Reset

0

0

ACCDET Control Register 8

12

0

0

11

0

14

0

13

9

6

5

4

3

2

1

0

0

ACCDET_DEBOUNCE0 RW 0 0 0 0

0

1

0

0

0

0

ACCDET Control Register 9

0

11

0

Bit Name Type Reset

0

14

0

13

9

6

5

4

3

2

1

0

0

ACCDET_DEBOUNCE1 RW 0 0 0 0

0

1

0

0

0

0

0

ACCDET Control Register 10 11

0

9

6

5

4

3

2

1

0

0

ACCDET_DEBOUNCE2 RW 0 0 0 0

0

1

0

0

0

0

0

14

0

13

12

0

0

Name ACCDET_DEBOUNCE3

000026A4

ACCDET_CON14

MediaTek Proprietary and Confidential.

7

Description De-bounce time control of state 2 De-bounce time = (DEBOUNCE/freq) sec In the TV mode, freq is bus clock 32,768 Hz in the MIC mode.

ACCDET_CON11 15

Bit Name Type Reset

8

0010

10

Name ACCDET_DEBOUNCE2

0000269E

7

Description De-bounce time control of state 1 De-bounce time = (DEBOUNCE/freq) sec In the TV mode, freq is bus clock and 32,768 Hz in the MIC mode.

12

0

8

0010

10

ACCDET_CON10 15

7

Description De-bounce time control of state 0 De-bounce time = (DEBOUNCE/freq) sec In the TV mode, freq is bus clock and 32,768 Hz in the MIC mode.

12

0

8

0010

10

Name ACCDET_DEBOUNCE1

0000269C

Bit(s) 15:0

0

13

ACCDET_CON9 15

Bit Name Type Reset

Bit(s) 15:0

14

Name ACCDET_DEBOUNCE0

0000269A

Bit(s) 15:0

Description

ACCDET Control Register 11 11

0

8

7

0010

10

9

6

5

4

3

2

1

0

0

ACCDET_DEBOUNCE3 RW 0 0 0 0

0

1

0

0

0

0

Description De-bounce time control of state 3 De-bounce time = (DEBOUNCE/freq) sec In the TV mode, freq is bus clock 32,768 Hz in the MIC mode.

ACCDET Control Register 14

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

EEEE Page 296 of 1067

MT6359 PMIC Datasheet Confidential A 15

14

13

12

Bit Name Type Reset

ACCDET_EINT_DEBOUNCE3 RW 1 1 1 0

Bit(s) 15:12

Name ACCDET_EINT_DEBOUNCE3

11:8

ACCDET_EINT_DEBOUNCE2

7:4

ACCDET_EINT_DEBOUNCE1

MediaTek Proprietary and Confidential.

11

10

9

8

ACCDET_EINT_DEBOUNCE2 RW 1 1 1 0

7

6

5

4

ACCDET_EINT_DEBOUNCE1 RW 1 1 1 0

3

2

1

0

ACCDET_EINT_DEBOUNCE0 RW 1 1 1 0

Description ACCDET EINT debounce time 4'd0: 0 ms (bypass) 4'd1: 0.12 ms 4'd2: 0.25 ms 4'd3: 0.5 ms 4'd4: 0.75 ms 4'd5: 1 ms 4'd6: 2 ms 4'd7: 4 ms 4'd8: 8 ms 4'd9: 16 ms 4'd10: 32 ms 4'd11: 48 ms 4'd12: 64 ms 4'd13: 128 ms 4'd14: 256 ms 4'd15: 512 ms ACCDET EINT debounce time 4'd0: 0 ms (bypass) 4'd1: 0.5 ms 4'd2: 0.75 ms 4'd3: 0.9 ms 4'd4: 1.5 ms 4'd5: 1.8 ms 4'd6: 3 ms 4'd7: 3.5 ms 4'd8: 3.8 ms 4'd9: 4 ms 4'd10: 4.5 ms 4'd11: 5 ms 4'd12: 7 ms 4'd13: 9 ms 4'd14: 19 ms 4'd15: 25 ms ACCDET EINT debounce time 4'd0: 0 ms (bypass) 4'd1: 0.5 ms 4'd2: 0.75 ms 4'd3: 0.9 ms 4'd4: 1.5 ms 4'd5: 1.8 ms 4'd6: 3 ms 4'd7: 3.5 ms 4'd8: 3.8 ms 4'd9: 4 ms 4'd10: 4.5 ms 4'd11: 5 ms

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Page 297 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

3:0

Name

ACCDET_EINT_DEBOUNCE0

000026A6 Bit

Description 4'd12: 7 ms 4'd13: 9 ms 4'd14: 19 ms 4'd15: 25 ms ACCDET EINT debounce time 4'd0: 0 ms (bypass) 4'd1: 0.12 ms 4'd2: 0.25 ms 4'd3: 0.5 ms 4'd4: 0.75 ms 4'd5: 1 ms 4'd6: 2 ms 4'd7: 4 ms 4'd8: 8 ms 4'd9: 16 ms 4'd10: 32 ms 4'd11: 48 ms 4'd12: 64 ms 4'd13: 128 ms 4'd14: 256 ms 4'd15: 512 ms

ACCDET_CON15 15

14

13

12

ACCDET Control Register 15 11

10

9

8

7

6

000E 5

4

2

1

0

ACCDET_EINT_INVERTER_DEB OUNCE RW

Name Type Reset Bit(s) 3:0

3

1

Name ACCDET_EINT_INVERTER_DEBOUNCE

MediaTek Proprietary and Confidential.

1

1

0

Description ACCDET EINT INVERTER debounce time 4'd0: 0 ms (bypass) 4'd1: 0.12 ms 4'd2: 0.25 ms 4'd3: 0.5 ms 4'd4: 0.75 ms 4'd5: 1 ms 4'd6: 2 ms 4'd7: 4 ms 4'd8: 8 ms 4'd9: 16 ms 4'd10: 32 ms 4'd11: 48 ms 4'd12: 64 ms 4'd13: 128 ms 4'd14: 256 ms 4'd15: 512 ms

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 298 of 1067

e control control

MT6359 PMIC Datasheet Confidential A 000026AC

ACCDET_CON18 15

Bit

13

12

Type Reset

0

0

0

ACCDET_EINT0_IRQ_CLR

8

ACCDET_IRQ_CLR

4 3 2 0

ACCDET_EINT_IN_INVERSE ACCDET_EINT1_IRQ ACCDET_EINT0_IRQ ACCDET_IRQ

000026AE

0

9

14

13

12

8

7

6

0000 5

RW 0

3

2

1

0

0

ACCDE T_IRQ RO

0

0

ACCDET Control Register 19 11

Type Reset

0

Description After number of eint_m_plug_in is received, the interrupt will be valid. Clears ACCDET_EINT1 interrupt status When ACCDET_EINT1 interrupt is asserted, IRQ_CLR must be set to 1 to clear the interrupt status. This bit will pause all activities of ACCDET_EINT1 design until both the interrupt status and IRQ_CLR are cleared. Clears ACCDET_EINT0 interrupt status When ACCDET_EINT0 interrupt is asserted, IRQ_CLR must be set to 1 to clear the interrupt status. This bit will pause all activities of ACCDET_EINT design until both the interrupt status and IRQ_CLR are cleared. Clears ACCDET interrupt status When ACCDET interrupt is asserted, IRQ_CLR must be set to 1 to clear the interrupt status. This bit will pause all activities of ACCDET design until both the interrupt status and IRQ_CLR are cleared. When EINT default close: inverse = 1 Clears ACCDET_EINT1 interrupt status Clear ACCDET_EINT0 interrupt status ACCDET interrupt status Due to this register is cleared by the hardware, the interrupt edgesensitive scheme should be adopted for this design.

10

9

ACCDE ACCDE T_EINT T_EINT 1_CTU 1_CEN_ RBO_S STABLE TABLE RW RW 0

0

8 ACCDE T_EINT 1_CMP MEN_S TABLE RW 0

7

6

0000 5

4

ACCDE ACCDE ACCDE ACCDE T_EINT T_EINT T_EINT T_EINT 1_CMP 0_CTU 1_EN_S 0_CEN_ EN_ST RBO_S TABLE STABLE ABLE TABLE RW RW RW RW 0

0

0

Name ACCDET_EINT1_CEN_STABLE ACCDET_EINT1_CTURBO_STABLE ACCDET_EINT1_CMPMEN_STABLE ACCDET_EINT1_CMPEN_STABLE ACCDET_EINT1_EN_STABLE ACCDET_EINT0_CEN_STABLE ACCDET_EINT0_CTURBO_STABLE

Description DA_EINT1CEN stable control DA_EINT1CTURBO stable control DA_EINT1CMPMEN stable control DA_EINT1CMPEN stable control DA_EINT1EN stable control DA_EINT0CEN stable control DA_EINT0CTURBO stable control

ACCDET_EINT0_EN_STABLE ACCDET_DA_STABLE

DA_EINT0EN stable control ACCDET DA signal stable control

MediaTek Proprietary and Confidential.

4

ACCDE ACCDE ACCDE T_EINT T_EINT T_EINT _IN_IN 1_IRQ 0_IRQ VERSE RW RO RO

ACCDE T_IRQ_ CLR

0

ACCDET_CON19 15

Name

Bit(s) 10 9 8 7 6 5 4 3 2 1 0

10

Name ACCDET_EINT_M_PLUG_IN_NUM ACCDET_EINT1_IRQ_CLR

10

Bit

ACCDET Control Register 18 11

ACCDE ACCDE ACCDET_EINT_M_PLUG T_EINT T_EINT _IN_NUM 1_IRQ_ 0_IRQ_ CLR CLR RW RW RW

Name

Bit(s) 14:12 11

14

0

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

3 ACCDE T_EINT 0_CMP MEN_S TABLE RW 0

2

1

0

ACCDE ACCDE T_EINT ACCDE T_EINT 0_CMP T_DA_ 0_EN_S EN_ST STABLE TABLE ABLE RW RW RW 0

0

0

Page 299 of 1067

MT6359 PMIC Datasheet Confidential A 000026D8 Bit

ACCDET_CON40 15

14

13

12

ACCDET Control Register 40 11

10

9

8

7

6

0000 5

4

Name

ACCDET_MON_FLAG_SEL

Type Reset

0

Bit(s) 7:4 0

RW

Name ACCDET_MON_FLAG_SEL ACCDET_MON_FLAG_EN

MediaTek Proprietary and Confidential.

0

0

0

3

2

1

0 ACCDE T_MO N_FLA G_EN RW 0

Description Selects ACCDET monitor flag Enables ACCDET monitor flag

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Page 300 of 1067

MT6359 PMIC Datasheet Confidential A

3.4

Register Table and Description (Group B)

Module name: MT6359_PMIC_Register_Mapping_E3 Base address: (+0x0)

Address 00000000 00000002 00000004 00000006 00000008 0000000A 0000000C 0000000E 00000010 00000012 00000014 00000016 00000018 0000001A 0000001C 0000001E 00000020 00000022 00000024 00000026 00000028 0000002A 0000002C 0000002E 00000030 00000032 00000034 00000036 00000038 0000003A 0000003C 0000003E 00000040 00000042 00000044 00000046 00000048 0000004A 0000004C 0000004E 00000050 00000080 00000082 00000084 sign Extra Information Register 00000086 00000088 0000008A 0000008C 0000008E 00000090

Name TOP0_ID TOP0_REV0 TOP0_DSN_DBI TOP0_DSN_DXI HWCID SWCID PONSTS POFFSTS PSTSCTL PG_DEB_STS0 PG_DEB_STS1 PG_SDN_STS0 PG_SDN_STS1 OC_SDN_STS0 OC_SDN_STS1 THERMALSTATUS TOP_CON TEST_OUT TEST_CON0 TEST_CON1 TESTMODE_SW TOPSTATUS TDSEL_CON RDSEL_CON SMT_CON0 SMT_CON1 TOP_RSV0 TOP_RSV1 DRV_CON0 DRV_CON1 DRV_CON2 DRV_CON3 DRV_CON4 FILTER_CON0 FILTER_CON1 FILTER_CON2 FILTER_CON3 TOP_STATUS TOP_STATUS_SET TOP_STATUS_CLR TOP_TRAP TOP1_ID TOP1_REV0 TOP1_DSN_DBI GPIO_DIR0 GPIO_DIR0_SET GPIO_DIR0_CLR GPIO_DIR1 GPIO_DIR1_SET

MediaTek Proprietary and Confidential.

Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

Register Function TOP0 Design ID Register TOP0 Design Revision Register 0 TOP0 Design Bank Information Register TOP0 Design Extra Information Register HW Chip ID Status SW Chip ID Status Power on Source Record Register Power off Source Record Register Power on/off Status Control Power Good Debounce Status Register 0 Power Good Debounce Status Register 1 Power Good Shutdown Status Register 0 Power Good Shutdown Status Register 1 BUCK OC Shutdown Status Register 0 BUCK OC Shutdown Status Register 1 Thermal Status Top Control Register TEST_OUT Test Control 0 Test Control 2 TESTMODE_SW TOP Status TDSEL_CON RDSEL_CON SMT_CON0 SMT_CON1 TOP_RSV0 TOP_RSV1 DRV_CON0 DRV_CON1 DRV_CON2 DRV_CON3 DRV_CON4 FILTER_CON0 FILTER_CON1 FILTER_CON2 FILTER_CON3 TOP_Status TOP_Status Register SET TOP_Status Register CLR Top VM Trap Value TOP1 Design ID Register TOP1 Design Revision Register 0 TOP1 Design Bank Information Register GPIO Direction Control Register 0 GPIO_DIR0 Register SET GPIO_DIR0 Register CLR GPIO Direction Control Register 1 GPIO_DIR1 Register SET

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 301 of 1067

MT6359 PMIC Datasheet Confidential A

Address 00000092 00000094 00000096 00000098 0000009A 0000009C 0000009E 000000A0 000000A2 000000A4 000000A6 000000A8 000000AA 000000AC 000000AE 000000B0 000000B2 000000B4 000000B6 000000B8 000000BA 000000BC 000000BE 000000C0 000000C2 000000C4 000000C6 000000C8 000000CA 000000CC 000000CE 000000D0 000000D2 000000D4 000000D6 000000D8 000000DA 000000DC 000000DE 000000E0 000000E2 000000E4 000000E6 000000E8 000000EA 00000100 00000102 00000104 sign Bank Information Register 00000106 sign Extra Information Register 00000108 0000010A 0000010C 0000010E

Name GPIO_DIR1_CLR GPIO_PULLEN0 GPIO_PULLEN0_SET GPIO_PULLEN0_CLR GPIO_PULLEN1 GPIO_PULLEN1_SET GPIO_PULLEN1_CLR GPIO_PULLSEL0 GPIO_PULLSEL0_SET GPIO_PULLSEL0_CLR GPIO_PULLSEL1 GPIO_PULLSEL1_SET GPIO_PULLSEL1_CLR GPIO_DINV0 GPIO_DINV0_SET GPIO_DINV0_CLR GPIO_DINV1 GPIO_DINV1_SET GPIO_DINV1_CLR GPIO_DOUT0 GPIO_DOUT0_SET GPIO_DOUT0_CLR GPIO_DOUT1 GPIO_DOUT1_SET GPIO_DOUT1_CLR GPIO_PI0 GPIO_PI1 GPIO_POE0 GPIO_POE1 GPIO_MODE0 GPIO_MODE0_SET GPIO_MODE0_CLR GPIO_MODE1 GPIO_MODE1_SET GPIO_MODE1_CLR GPIO_MODE2 GPIO_MODE2_SET GPIO_MODE2_CLR GPIO_MODE3 GPIO_MODE3_SET GPIO_MODE3_CLR GPIO_MODE4 GPIO_MODE4_SET GPIO_MODE4_CLR GPIO_RSV TOP2_ID TOP2_REV0

TOP_PAM0 TOP_PAM1 TOP_CKPDN_CON0 TOP_CKPDN_CON0_SET

MediaTek Proprietary and Confidential.

Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

16 16 16 16

Register Function GPIO_DIR1 Register CLR GPIO Pull-up/Pull-down Enable Register 0 GPIO_PULLEN0 Register SET GPIO_PULLEN0 Register CLR GPIO Pull-up/Pull-down Enable Register 1 GPIO_PULLEN1 Register SET GPIO_PULLEN1 Register CLR GPIO Pull-up/Pull-down Selection Register 0 GPIO_PULLSEL0 Register SET GPIO_PULLSEL0 Register CLR GPIO Pull-up/Pull-down Selection Register 1 GPIO_PULLSEL1 Register SET GPIO_PULLSEL1 Register CLR GPIO Data Inversion Control Register 0 GPIO_DINV0 Register SET GPIO_DINV0 Register CLR GPIO Data Inversion Control Register 1 GPIO_DINV1 Register SET GPIO_DINV1 Register CLR GPIO Data Output Register 0 GPIO_DOUT0 Register SET GPIO_DOUT0 Register CLR GPIO Data Output Register 1 GPIO_DOUT1 Register SET GPIO_DOUT1 Register CLR GPIO Data Input Register 0 GPIO Data Input Register 1 GPIO Data Direction Register 0 GPIO Data Direction Register 1 GPIO Mode Control Register 0 GPIO_MODE0 Register SET GPIO_MODE0 Register CLR GPIO Mode Control Register 1 GPIO_MODE1 Register SET GPIO_MODE1 Register CLR GPIO Mode Control Register 2 GPIO_MODE2 Register SET GPIO_MODE2 Register CLR GPIO Mode Control Register 3 GPIO_MODE3 Register SET GPIO_MODE3 Register CLR GPIO Mode Control Register 4 GPIO_MODE4 Register SET GPIO_MODE4 Register CLR GPIO Reserved TOP2 Design ID Register TOP2 Design Revision Register 0

TOP Parameter 0 TOP Parameter 1 TOP_CKPDN Control Register 0 TOP_CKPDN_CON0 Register SET

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 302 of 1067

MT6359 PMIC Datasheet Confidential A Address 00000110 00000112 00000114 00000116 00000118 0000011A 0000011C 0000011E 00000120 00000122 00000124 00000126 00000128 0000012A 0000012C 0000012E 00000130 00000132 00000134 00000136 00000138 0000013A 0000013C 0000013E 00000140 00000142 00000144 00000146 00000148 0000014A 0000014C 0000014E 00000150 00000152 00000154 00000156 00000158 0000015A 0000015C 00000180 00000182 00000184 00000186 00000188 0000018A 0000018C 0000018E 00000190 00000192 00000194 00000196

Name TOP_CKPDN_CON0_CLR TOP_CKPDN_CON1 TOP_CKPDN_CON1_SET TOP_CKPDN_CON1_CLR TOP_CKSEL_CON0 TOP_CKSEL_CON0_SET TOP_CKSEL_CON0_CLR TOP_CKSEL_CON1 TOP_CKSEL_CON1_SET TOP_CKSEL_CON1_CLR TOP_CKDIVSEL_CON0 TOP_CKDIVSEL_CON0_SET TOP_CKDIVSEL_CON0_CLR TOP_CKHWEN_CON0 TOP_CKHWEN_CON0_SET TOP_CKHWEN_CON0_CLR TOP_CKTST_CON0 TOP_CKTST_CON1 TOP_CLK_CON0 TOP_CLK_CON1 TOP_CLK_DCM0 TOP_RST_CON0 TOP_RST_CON0_SET TOP_RST_CON0_CLR TOP_RST_CON1 TOP_RST_CON1_SET TOP_RST_CON1_CLR TOP_RST_CON2 TOP_RST_CON3 TOP_RST_MISC TOP_RST_MISC_SET TOP_RST_MISC_CLR TOP_RST_STATUS TOP_RST_STATUS_SET TOP_RST_STATUS_CLR TOP_CLK_EN_MON TOP2_ELR_NUM TOP2_ELR0 TOP2_ELR1 TOP3_ID TOP3_REV0 TOP3_DSN_DBI TOP3_DSN_DXI MISC_TOP_INT_CON0 MISC_TOP_INT_CON0_SET MISC_TOP_INT_CON0_CLR MISC_TOP_INT_MASK_CON0 MISC_TOP_INT_MASK_CON0 _SET MISC_TOP_INT_MASK_CON0 _CLR MISC_TOP_INT_STATUS0 MISC_TOP_INT_RAW_STATU S0

MediaTek Proprietary and Confidential.

Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

Register Function TOP_CKPDN_CON0 Register CLR TOP_CKPDN Control Register 1 TOP_CKPDN_CON1 Register SET TOP_CKPDN_CON1 Register CLR TOP_CKSEL Control Register 0 TOP_CKSEL_CON0 Register SET TOP_CKSEL_CON0 Register CLR TOP_CKSEL Control Register 1 TOP_CKSEL_CON1 Register SET TOP_CKSEL_CON1 Register CLR TOP_CKDIVSEL Control Register 0 TOP_CKDIVSEL_CON0 Register SET TOP_CKDIVSEL_CON0 Register CLR TOP_CKHWEN Control Register 0 TOP_CKHWEN_CON0 Register SET TOP_CKHWEN_CON0 Register CLR TOP_CKTST Control Register 0 TOP_CKTST Control Register 1 TOP_CLK Register 0 TOP_CLK Register 1 TOP_CLK DCM Control Register 0 TOP_RST Control Register 0 TOP_RST_CON0 Register SET TOP_RST_CON0 Register CLR TOP_RST Control Register 1 TOP_RST_CON1 Register SET TOP_RST_CON1 Register CLR TOP_RST Control Register 2 TOP_RST Control Register 3 Reset Control Misc Reset Control Misc SET Reset Control Misc CLR TOP_RST_STATUS Register TOP_RST_STATUS Register SET TOP_RST_STATUS Register CLR TOP CLK 26M 1M CKEN MON TOP2 Number of ELR Register TOP2 ELR 0 Register TOP2 ELR 1 Register TOP3 Design ID Register TOP3 Design Revision Register 0 TOP3 Design Bank Information Register TOP3 Design Extra Information Register TOP INT Control Register 0 TOP INT Control Register 0 SET TOP INT Control Register 0 CLR misc INT Mask Control Register 0

16

MISC TOP INT Mask Control Register 0 SET

16

MISC TOP INT Mask Control Register 0 CLR

16

MISC TOP INT Status Register 0

16

MISC TOP INT Raw Status Register 0

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Mode Enable t

MT6359 PMIC Datasheet Confidential A Address 00000198 0000019A 0000019C 0000019E 000001A0 000001A2 000001A4 000001A6 000001A8 000001AA 000001AC 000001AE 000001B0 000001B2 00000380 00000382 00000384 00000386 00000388 0000038A 0000038C 0000038E 00000390 00000392 00000394 00000396 00000398 0000039A 0000039C 0000039E 000003A0 000003A2 000003A4 000003A6 000003A8 000003AA 000003AC 000003AE 000003B0 000003B2 000003B4 00000400 00000402 00000404 00000406 00000408 0000040A 0000040C 0000040E 00000410 00000412 00000414 00000416

Name TOP_INT_MASK_CON0 TOP_INT_MASK_CON0_SET TOP_INT_MASK_CON0_CLR TOP_INT_STATUS0 TOP_INT_RAW_STATUS0 TOP_INT_CON0 TOP_DCXO_CKEN_SW PMRC_CON0 PMRC_CON0_SET PMRC_CON0_CLR PMRC_CON1 PMRC_CON1_SET PMRC_CON1_CLR PMRC_CON2 PLT0_ID PLT0_REV0 PLT0_REV1 PLT0_DSN_DXI TOP_CLK_TRIM OTP_CON0 OTP_CON1 OTP_CON2 OTP_CON3 OTP_CON4 OTP_CON5 OTP_CON6 OTP_CON7 OTP_CON8 OTP_CON9 OTP_CON10 OTP_CON11 OTP_CON12 OTP_CON13 OTP_CON14 TOP_TMA_KEY TOP_MDB_CONF0 TOP_MDB_CONF1 TOP_MDB_CONF2 TOP_MDB_CONF3 PLT0_ELR_NUM PLT0_ELR0 SPISLV_ID SPISLV_REV0 SPISLV_REV1 SPISLV_DSN_DXI RG_SPI_CON0 RG_SPI_RECORD0

DEW_WRITE_TEST DEW_CRC_SWRST DEW_CRC_EN DEW_CRC_VAL

MediaTek Proprietary and Confidential.

Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

16 16 16 16

Register Function TOP_INT_MASK Control Register 0 TOP_INT_MASK Control Register SET TOP_INT_MASK Control Register CLR TOP_INT_STATUS Register 0 TOP_INT_RAQ_STATUS Register 0 TOP_INT_CONTROL Register 0 DCXO CKEN SW Mode Register 0 PMRC Control Register 0 PMRC CON0 Register SET PMRC CON0 Register CLR PMRC Control Register 1 PMRC CON1 Register SET PMRC CON1 Register CLR PMRC Control Register 2 PLT0 Design ID Register PLT0 Design Revision Register 0 PLT0 Design Revision Register 1 PLT0 Design Extra Information Register TOP_CLK_TRIM Register OTP Control Register 0 OTP Control Register 1 OTP Control Register 2 OTP Control Register 3 OTP Control Register 4 OTP Control Register 5 OTP Control Register 6 OTP Control Register 7 OTP Control Register 8 OTP Control Register 9 OTP Control Register 10 OTP Control Register 11 OTP Control Register 12 OTP Control Register 13 OTP Control Register 14 Top Specific Write Protection Key TOP MDB Configuration 0 TOP MDB Configuration 1 TOP MDB Configuration 2 TOP MDB Configuration 3 PLT0 Number of ELR Register OSC 128k TRIM SPISLV Design ID Register SPISLV Design Revision Register 0 SPISLV Design Revision Register 1 SPISLV Design Extra Information Register SPI Control Register 0 SPI Record Control Register 0

Write Test CRC_SWRST CRC Enable CRC Value

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MT6359 PMIC Datasheet Confidential A Address 00000418 0000041A 0000041C 0000041E 00000420 00000422 00000424 00000426 00000428 0000042A 0000042C 0000042E 00000430 00000432 00000434 00000436 00000438 0000043A 0000043C 0000043E 00000440 00000442 00000444 00000446 00000448 0000044A 0000044C 0000044E 00000450 00000452 00000454 00000456 00000458 00000500 00000502 00000504 00000506 00000508 0000050A 0000050C 0000050E 00000510 00000512 00000514 00000516 00000518 0000051A 0000051C 0000051E 00000520 00000522 00000524

Name DEW_CIPHER_KEY_SEL DEW_CIPHER_IV_SEL DEW_CIPHER_EN DEW_CIPHER_RDY DEW_CIPHER_MODE DEW_CIPHER_SWRST DEW_RDDMY_NO RG_SPI_CON2 RECORD_CMD0 RECORD_CMD1 RECORD_CMD2 RECORD_CMD3 RECORD_CMD4 RECORD_CMD5 RECORD_WDATA0 RECORD_WDATA1 RECORD_WDATA2 RECORD_WDATA3 RECORD_WDATA4 RECORD_WDATA5 RG_SPI_CON9 RG_SPI_CON10 RG_SPI_CON11 RG_SPI_CON12 RG_SPI_CON13 SPISLV_KEY INT_TYPE_CON0 INT_TYPE_CON0_SET INT_TYPE_CON0_CLR INT_STA RG_SPI_CON1 TOP_SPI_CON0 TOP_SPI_CON1 SCK_TOP_DSN_ID SCK_TOP_DSN_REV0 SCK_TOP_DBI SCK_TOP_DXI SCK_TOP_TPM0 SCK_TOP_TPM1 SCK_TOP_CON0 SCK_TOP_CON1 SCK_TOP_TEST_OUT SCK_TOP_TEST_CON0 SCK_TOP_CKPDN_CON0 SCK_TOP_CKPDN_CON0_SET SCK_TOP_CKPDN_CON0_CLR SCK_TOP_CKHWEN_CON0 SCK_TOP_CKHWEN_CON0_S ET SCK_TOP_CKHWEN_CON0_C LR SCK_TOP_CKTST_CON SCK_TOP_RST_CON0 SCK_TOP_RST_CON0_SET

MediaTek Proprietary and Confidential.

Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

Register Function CIPHER Key Selection CIPHER Initial Vector Selection CIPHER Engine Enable CIPHER Data Ready CIPHER Mode Enable CIPHER Soft Reset Read Dummy Cycle Number SPI Control Register 2 SPI Record Command 0 SPI Record Command 1 SPI Record Command 2 SPI Record Command 3 SPI Record Command 4 SPI Record Command 5 SPI Record Data 0 SPI Record Data 1 SPI Record Data 2 SPI Record Data 3 SPI Record Data 4 SPI Record Data 5 SPI Control Register 9 SPI Control Register 10 SPI Control Register 11 SPI Control Register 12 SPI Control Register 13 SPISLV Specific Write Protection Key Interrupt Type Configuration 0 Interrupt Type Configuration 0 Set Interrupt Type Configuration 0 Clear SPI Interrupt Status SPI Control Register 1 Top SPI Domain Control Register 0 Top SPI Domain Control Register 1 SCK TOP Design ID Register SCK TOP Design Revision Register 0 SCK TOP Design Bank Information Register SCK TOP Design Extra Information Register SCK_TOP Parameter 0 SCK_TOP Parameter 1 SCK_TOP_CON0 Control Register SCK_TOP_CON1 Control Register SCK_TOP Test Output SCK_TOP Test Control Register 0 SCK_CKPDN Control Register 0 SCK_CKPDN Control Register 0 SET SCK_CKPDN Control Register 0 CLR SCK_CKHWEN Control Register 0 SCK_CKHWEN_CON Register 0 SET SCK_CKHWEN_CON Register 0 CLR SCK_CKTST Control Register SCK_TOP_RST Control Register 0 SCK_TOP_RST_CON Register 0 SET

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MT6359 PMIC Datasheet Confidential A Address 00000526 00000528 0000052A 0000052C 0000052E 00000530 00000532 00000534 00000536

00000538 0000053A 0000053C 0000053E 00000540 00000542 00000544 00000546 00000548 0000054A 0000054C 0000054E 00000550 00000552 00000554 00000556 00000580 00000582 00000584 00000586 00000588 0000058A 0000058C 0000058E 00000590 00000592 00000594 00000596 00000598 0000059A 0000059C 0000059E 000005A0 000005A2 000005A4 000005A6 000005A8 of-week Alarm Setting Register 000005AA 000005AC 000005AE 000005B0 000005B2

Name SCK_TOP_RST_CON0_CLR SCK_TOP_INT_CON0 SCK_TOP_INT_CON0_SET SCK_TOP_INT_CON0_CLR SCK_TOP_INT_MASK_CON0 SCK_TOP_INT_MASK_CON0_ SET SCK_TOP_INT_MASK_CON0_ CLR SCK_TOP_INT_STATUS0 SCK_TOP_INT_RAW_STATUS 0 SCK_TOP_INT_MISC_CON EOSC_CALI_CON0 EOSC_CALI_CON1 RTC_MIX_CON0 RTC_MIX_CON1 RTC_MIX_CON2 RTC_DIG_CON0 FQMTR_CON0 FQMTR_CON1 FQMTR_CON2 XO_BUF_CTL0 XO_BUF_CTL1 XO_BUF_CTL2 XO_BUF_CTL3 XO_BUF_CTL4 XO_CONN_BT0 RTC_DSN_ID RTC_DSN_REV0 RTC_DBI RTC_DXI RTC_BBPU RTC_IRQ_STA RTC_IRQ_EN RTC_CII_EN RTC_AL_MASK RTC_TC_SEC RTC_TC_MIN RTC_TC_HOU RTC_TC_DOM RTC_TC_DOW RTC_TC_MTH RTC_TC_YEA RTC_AL_SEC RTC_AL_MIN RTC_AL_HOU RTC_AL_DOM RTC_AL_MTH RTC_AL_YEA RTC_OSC32CON RTC_POWERKEY1 RTC_POWERKEY2

MediaTek Proprietary and Confidential.

Width 16 16 16 16 16

Register Function SCK_TOP_RST_CON Register 0 CLR SCK_TOP INT Control Register 0 SCK_TOP INT Control Register 0 SET SCK_TOP INT Control Register 0 CLR SCK_TOP INT Mask Control Register 0

16

SCK_TOP INT Mask Control Register 0 SET

16

SCK_TOP INT Mask Control Register 0 CLR

16

SCK_TOP INT Status Register 0

16

SCK_TOP INT Raw Status Register 0

16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

SCK_TOP INT MISC Control Register RTC EOSC CALI Control Registers 0 RTC EOSC CALI Control Registers 1 RTC Analog test Control Registers 0 RTC Analog Test Control Registers 1 RTC Analog Test Control Registers 2 RTC Digital Test Control Register 0 Frequency Meter Control Register 0 Frequency Meter Control Register 1 Frequency Meter Control Register 2 XO SOC Buffer Control Register XO WCN Buffer Control Register XO NFC Buffer Control Register XO CEL Buffer Control Register XO EXT Buffer Control Register XO CONN BT Control Register RTC Design ID register RTC Design Revision Register 0 RTC Design Bank Information Register RTC Design Extra Information Register Baseband Power Up RTC IRQ Status RTC IRQ Enable Counter Increment IRQ Enable RTC Alarm Mask RTC Seconds Time Counter Register RTC Minutes Time Counter Register RTC Hours Time Counter Register RTC Day-of-month Time Counter Register RTC Day-of-week Time Counter Register RTC Month Time Counter Register RTC Year Time Counter Register RTC Second Alarm Setting Register RTC Minute Alarm Setting Register RTC Hour Alarm Setting Register RTC Day-of-month Alarm Setting Register

16 16 16 16 16

RTC Month Alarm Setting Register RTC Year Alarm Setting Register OSC32 Control RTC_POWERKEY1 Register RTC_POWERKEY2 Register

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de Word 12 de Word 13

MT6359 PMIC Datasheet Confidential A Address 000005B4 000005B6 000005B8 000005BA 000005BC 000005BE 000005C0 000005C2 000005C4 000005C6 000005C8 000005CA 000005CC 000005CE 00000600 00000602 00000604 00000606 00000608 0000060A 0000060C 0000060E 00000610 00000612 00000614 00000616 00000618 00000780 00000782 00000784 00000786 00000788 0000078A 0000078C 0000078E 00000790 00000792 00000794 00000796 00000798 0000079A 0000079C 0000079E 000007A0 000007A2 000007A4 000007A6 000007A8 000007AA 000007AC 000007AE 000007B0 000007B2

Name RTC_PDN1 RTC_PDN2 RTC_SPAR0 RTC_SPAR1 RTC_PROT RTC_DIFF RTC_CALI RTC_WRTGR RTC_CON RTC_SEC_CTRL RTC_INT_CNT RTC_SEC_DAT0 RTC_SEC_DAT1 RTC_SEC_DAT2 RTC_SEC_DSN_ID RTC_SEC_DSN_REV0 RTC_SEC_DBI RTC_SEC_DXI RTC_TC_SEC_SEC RTC_TC_MIN_SEC RTC_TC_HOU_SEC RTC_TC_DOM_SEC RTC_TC_DOW_SEC RTC_TC_MTH_SEC RTC_TC_YEA_SEC RTC_SEC_CK_PDN RTC_SEC_WRTGR DCXO_DSN_ID DCXO_DSN_REV0 DCXO_DSN_DBI DCXO_DSN_DXI DCXO_CW00 DCXO_CW00_SET DCXO_CW00_CLR DCXO_CW01 DCXO_CW02 DCXO_CW03 DCXO_CW04 DCXO_CW05 DCXO_CW06 DCXO_CW07 DCXO_CW08 DCXO_CW09 DCXO_CW09_SET DCXO_CW09_CLR DCXO_CW10 DCXO_CW11

DCXO_CW14 DCXO_CW15 DCXO_CW16 DCXO_CW17

MediaTek Proprietary and Confidential.

Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

16 16 16 16

Register Function PDN1 PDN2 Spare Register for Specific Purpose_0 Spare Register for Specific Purpose_1 Lock/Unlock Scheme to Prevent RTC Miswriting One-time Calibration Offset Repeat Calibration Offset Enable Transfers from Core to RTC in Queue Other RTC Control Register Write Lock for RTC SEC Data RTC Internal Counter RTC SEC Data 0 RTC SEC Data 1 RTC SEC Data 2 RTC_SEC Design ID Register RTC_SEC Design Revision Register 0 RTC_SEC Design Bank Information Register RTC_SEC Design Extra Information Register Security RTC Seconds Time Counter Register Security RTC Minutes Time Counter Register Security RTC Hours Time Counter Register Security RTC Day-of-month Time Counter Register Security RTC Day-of-week Time Counter Register Security RTC Month Time Counter Register Security RTC Year Time Counter Register Security RTC Clock Control Register Enable Transfers from Core to Security RTC in Queue DCXO Design ID Register DCXO Design Revision Register 0 DCXO Design Bank Information Register DCXO Design Extra Information Register DCXO Code Word 0 DCXO Code Word 0 Set DCXO Code Word 0 Clear DCXO Code Word 1 DCXO Code Word 2 DCXO Code Word 3 DCXO Code Word 4 DCXO Code Word 5 DCXO Code Word 6 DCXO Code Word 7 DCXO Code Word 8 DCXO Code Word 9 DCXO Code Word 9 Set DCXO Code Word 9 Clear DCXO Code Word 10 DCXO Code Word 11

DCXO Code Word 14 DCXO Code Word 15 DCXO Code Word 16 DCXO Code Word 17

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MT6359 PMIC Datasheet Confidential A Address 000007B4 000007B6 000007B8 000007BA 00000900 00000902 00000904 00000906 00000908 0000090A 0000090C 0000090E 00000910 00000912 00000914 00000916 00000918 0000091A 0000091C 0000091E 00000920 00000922 00000924

G Control Register 12

00000926 00000980 00000982 00000984 00000986 00000988 0000098A 0000098C 0000098E 00000990 00000992 00000A00 00000A02 00000A04 00000A06 00000A08 00000A0A 00000A0C 00000A0E 00000A10 00000A12 00000A14 00000A16 00000A18 00000A1A 00000A1C

Name DCXO_CW18 DCXO_CW19 DCXO_ELR_NUM DCXO_ELR0 PSC_TOP_ID PSC_TOP_REV0 PSC_TOP_DBI PSC_TOP_DXI PSC_TPM0 PSC_TPM1 PSC_TOP_CLKCTL_0 PSC_TOP_RSTCTL_0 PSC_TOP_INT_CON0 PSC_TOP_INT_CON0_SET PSC_TOP_INT_CON0_CLR PSC_TOP_INT_MASK_CON0 PSC_TOP_INT_MASK_CON0_ SET PSC_TOP_INT_MASK_CON0_ CLR PSC_TOP_INT_STATUS0 PSC_TOP_INT_RAW_STATUS 0 PSC_TOP_INT_MISC_CON PSC_TOP_INT_MISC_CON_SE T PSC_TOP_INT_MISC_CON_CL R PSC_TOP_MON_CTL STRUP_ID STRUP_REV0 STRUP_DBI STRUP_DSN_FPI STRUP_ANA_CON0 STRUP_ANA_CON1 STRUP_ANA_CON2 STRUP_ANA_CON3 STRUP_ELR_NUM STRUP_ELR_0 PSEQ_ID PSEQ_REV0 PSEQ_DBI PSEQ_DXI PPCCTL0 PPCCTL1 PPCCFG0 STRUP_CON9 STRUP_CON11 STRUP_CON13 PWRKEY_PRESS_STS PORFLAG STRUP_CON4 STRUP_CON1

MediaTek Proprietary and Confidential.

Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

Register Function DCXO Code Word 18 DCXO Code Word 19 DCXO Number of ELR Register DCXO ELR 0 Register PSC TOP Design ID Register PSC TOP Design Revision Register 0 PSC TOP Design Bank Information Register PSC TOP Design Extra Information Register PSC_TOP Parameter 0 PSC_TOP Parameter 1 PSC Clock Control Register 0 PSC Reset Control Register 0 PSC_TOP INT Control Register 0 PSC_TOP INT Control Register 0 SET PSC_TOP INT Control Register 0 CLR PSC_TOP INT Mask Control Register 0

16

PSC_TOP INT Mask Control Register 0 SET

16

PSC_TOP INT Mask Control Register 0 CLR

16

PSC_TOP INT Status Register 0

16

PSC_TOP INT Raw Status Register 0

16

PSC_TOP INT MISC Control Register

16

PSC_TOP INT MISC Control SET Register

16

PSC_TOP INT MISC Control CLR Register

16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

PSC TOP Debug Monitor Control STRUP Design ID Register STRUP Design Revision Register 0 STRUP Design Bank Information Register STRUP Design Extra Information Register STRUP Control Register 0 STRUP Control Register 1 STRUP Control Register 2 STRUP Control Register 3 STRUP Number of ELR Register STRUP ELR 0 Register PSEQ Design ID Register PSEQ Design Revision Register 0 PSEQ Design Bank Information Register PSEQ Design Extra Information Register PPC Control 0 Register PPC Control 1 Register PPC Configuration 0 Register STRUP DIG Control Register N9 STRUP DIG Control Register 11

16 16 16 16 16

STRUP DIG Control Register 13 PWRKEY Long Press Counter Status Power Reset Flag STRUP DIG Control Register N4 STRUP DIG Control Register 1

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Control Register 2 EF DA Register 0

MT6359 PMIC Datasheet Confidential A Address 00000A1E 00000A20 00000A22 00000A24 00000A26 00000A28 00000A2A 00000A2C 00000A2E 00000A30 00000A32 00000A34 00000A36 00000A38 00000A3A 00000A3C 00000A3E 00000A40 00000A42 00000A44 00000A46 00000A48 00000A4A 00000A4C 00000A4E 00000A50 00000A52 00000A54 00000A56 00000A58 00000A5A 00000A5C 00000A5E 00000A60 00000A62 00000A64 00000A66 00000A68 00000A6A 00000A6C 00000A6E 00000A80 00000A82 00000A84 00000A86 00000A88 00000A8A 00000A8C 00000A8E 00000A90 00000A92 00000A94 00000A96

Name STRUP_CON2 STRUP_CON5 STRUP_CON19 STRUP_PGDEB0 STRUP_PGDEB1 STRUP_PGENB0 STRUP_PGENB1 STRUP_OCENB0 STRUP_OCENB1 PPCTST0 PPCCTL2 STRUP_CON10 STRUP_CON3 STRUP_CON6 CPSWKEY CPSCFG0 CPSDSA0 CPSDSA1 CPSDSA2 CPSDSA3 CPSDSA4 CPSDSA5 CPSDSA6 CPSDSA7 CPSDSA8 CPSDSA9 PSEQ_ELR_NUM PSEQ_ELR0 PSEQ_ELR1 PSEQ_ELR2 PSEQ_ELR3 CPSUSA_ELR0 CPSUSA_ELR1 CPSUSA_ELR2 CPSUSA_ELR3 CPSUSA_ELR4 CPSUSA_ELR5 CPSUSA_ELR6 CPSUSA_ELR7 CPSUSA_ELR8 CPSUSA_ELR9 CHRDET_ID CHRDET_REV0 CHRDET_DBI CHRDET_DXI CHR_CON0 CHR_CON1

PCHR_VREF_ANA_CON0 PCHR_VREF_ANA_CON1 PCHR_VREF_ANA_CON2 PCHR_VREF_ANA_CON3

MediaTek Proprietary and Confidential.

Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

16 16 16 16

Register Function STRUP DIG Control Register 2 STRUP DIG Control Register N5 STRUP DIG Control Register 20 STRUP PG Debounce Control Register 0 STRUP PG Debounce Control Register 1 STRUP PG Enable Control Register 0 STRUP PG Enable Control Register 1 BUCK OC SDN Control Register 0 BUCK OC SDN Control Register 1 PPCTST0 PPC Control 2 Register STRUP DIG Control Register 10 STRUP DIG Control Register 3 STRUP DIG Control Register 6 CPS Write Key Register CPS Configuration 0 Register CPS Power Down Assignment 0 Register CPS Power Down Assignment 1 Register CPS Power Down Assignment 2 Register CPS Power Down Assignment 3 Register CPS Power Down Assignment 4 Register CPS Power Down Assignment 5 Register CPS Power Down Assignment 6 Register CPS Power Down Assignment 7 Register CPS Power Down Assignment 8 Register CPS Power Down Assignment 9 Register PSEQ Number of ELR Register BWDT Control 0 Register PSEQ_ELR Control Register 8 Reserve ELR Register 0 Reserve ELR Register 1 CPS Power Up Assignment 0 Register CPS Power Up Assignment 1 Register CPS Power Up Assignment 2 Register CPS Power Up Assignment 3 Register CPS Power Up Assignment 4 Register CPS Power Up Assignment 5 Register CPS Power Up Assignment 6 Register CPS Power Up Assignment 7 Register CPS Power Up Assignment 8 Register CPS Power Up Assignment 9 Register CHRDET Design ID Register CHRDET Design Revision Register 0 CHRDET Design Bank Information Register CHRDET Design Extra Information Register Charger Control Register 0 Charger Control Register 1

PCHR_VREF Control Register 0 PCHR_VREF Control Register 1 PCHR_VREF Control Register 2 PCHR_VREF Control Register 3

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MT6359 PMIC Datasheet Confidential A Address 00000A98 00000A9A 00000A9C 00000A9E 00000C00 00000C02 00000C04 00000C06 00000C08 00000C0A 00000C0C 00000C0E 00000C10 00000C12 00000C14 00000C16 00000C18 00000C1A 00000C1C 00000C1E 00000C20 00000C22 00000C24 00000C26 00000C28 00000C2A 00000C2C 00000C2E 00000C30 00000C32 00000C34 00000C36 00000C38 00000C3A 00000C3C 00000C3E 00000C40 00000C42 00000C44 00000C46 00000C48 00000C4A 00000C4C 00000C4E

Name PCHR_VREF_ANA_CON4 PCHR_VREF_ELR_NUM PCHR_VREF_ELR_0 PCHR_VREF_ELR_1 BM_TOP_DSN_ID BM_TOP_DSN_REV0 BM_TOP_DBI BM_TOP_DXI BM_TPM0 BM_TPM1 BM_TOP_CKPDN_CON0 BM_TOP_CKPDN_CON0_SET BM_TOP_CKPDN_CON0_CLR BM_TOP_CKSEL_CON0 BM_TOP_CKSEL_CON0_SET BM_TOP_CKSEL_CON0_CLR BM_TOP_CKDIVSEL_CON0 BM_TOP_CKDIVSEL_CON0_S ET BM_TOP_CKDIVSEL_CON0_C LR BM_TOP_CKHWEN_CON0 BM_TOP_CKHWEN_CON0_SE T BM_TOP_CKHWEN_CON0_CL R BM_TOP_CKTST_CON0 BM_TOP_RST_CON0 BM_TOP_RST_CON0_SET BM_TOP_RST_CON0_CLR BM_TOP_RST_CON1 BM_TOP_RST_CON1_SET BM_TOP_RST_CON1_CLR BM_TOP_INT_CON0 BM_TOP_INT_CON0_SET BM_TOP_INT_CON0_CLR BM_TOP_INT_CON1 BM_TOP_INT_CON1_SET BM_TOP_INT_CON1_CLR BM_TOP_INT_MASK_CON0 BM_TOP_INT_MASK_CON0_ SET BM_TOP_INT_MASK_CON0_ CLR BM_TOP_INT_MASK_CON1 BM_TOP_INT_MASK_CON1_ SET BM_TOP_INT_MASK_CON1_ CLR BM_TOP_INT_STATUS0 BM_TOP_INT_STATUS1 BM_TOP_INT_RAW_STATUS 0

MediaTek Proprietary and Confidential.

Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

Register Function PCHR_VREF Control Register 4 PCHR_VREF Number of ELR Register PCHR_VREF ELR 0 Register PCHR_VREF ELR 1 Register BM_TOP ID Register BM_TOP Revision Register 0 BM_TOP Design Bank Information Register BM_TOP Design Extra Information Register BM_TOP Parameter 0 BM_TOP Parameter 1 BM_TOP_CKPDN Control Register 0 BM_TOP_CKPDN_CON0 Register SET BM_TOP_CKPDN_CON0 Register CLR BM_TOP_CKSEL Control Register 0 BM_TOP_CKSEL_CON0 Register SET BM_TOP_CKSEL_CON0 Register CLR BM_TOP_CKDIVSEL Control Register 0

16

BM_TOP_CKDIVSEL_CON0 Register SET

16

BM_TOP_CKDIVSEL_CON0 Register CLR

16

BM_TOP_CKHWEN Control Register 0

16

BM_TOP_CKHWEN_CON0 Register SET

16

BM_TOP_CKHWEN_CON0 Register CLR

16 16 16 16 16 16 16 16 16 16 16 16 16 16

BM_TOP_CKTST Control Register 0 BM_TOP_RST Control Register 0 BM_TOP_RST_CON0 Register SET BM_TOP_RST_CON0 Register CLR BM_TOP_RST Control Register 1 BM_TOP_RST_CON1 Register SET BM_TOP_RST_CON1 Register CLR BM_TOP_INT Control Register 0 BM_TOP_INT Control Register 0 SET BM_TOP_INT Control Register 0 CLR BM_TOP_INT Control Register 1 BM_TOP_INT Control Register 1 SET BM_TOP_INT Control Register 1 CLR BM_TOP_INT_MASK Control Register 0

16

BM_TOP_INT Mask Control Register 0 SET

16

BM_TOP_INT Mask Control Register 0 CLR

16

BM_TOP_INT_MASK Control Register 1

16

BM_TOP_INT Mask Control Register 1 SET

16

BM_TOP_INT Mask Control Register 1 CLR

16 16

BM_TOP_INT Status Register 0 BM_TOP_INT Status Register 1

16

BM_TOP_INT Raw Status Register 0

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MT6359 PMIC Datasheet Confidential A Address 00000C50

00000C52 00000C54 00000C56 00000C58 00000C5A 00000C5C 00000C80 00000C82 00000C84 00000C86 00000C88 00000C8A 00000C8C 00000C8E 00000D00 00000D02 00000D04 00000D06 00000D08 00000D0A 00000D0C 00000D0E 00000D10 00000D12 00000D14 00000D16 00000D18 00000D1C 00000D1E 00000D20 00000D22 00000D24 00000D26 00000D28 00000D2A 00000D2C 00000D2E 00000D30 00000D32 00000D34 00000D36 00000D38 00000D3A 00000D3E 00000D40 ON Control Register 2 00000D42 OFF Control Register 0 00000D44 00000D46 00000D48 00000D4A 00000D4C 00000D4E

Name BM_TOP_INT_RAW_STATUS 1 BM_TOP_INT_MISC_CON BM_TOP_DBG_CON BM_TOP_RSV0 BM_WKEY0 BM_WKEY1 BM_WKEY2 FGADC_ANA_DSN_ID FGADC_ANA_DSN_REV0 FGADC_ANA_DSN_DBI FGADC_ANA_DSN_DXI FGADC_ANA_CON0 FGADC_ANA_TEST_CON0 FGADC_ANA_ELR_NUM FGADC_ANA_ELR0 FGADC0_DSN_ID FGADC0_DSN_REV0 FGADC0_DSN_DBI FGADC0_DSN_DXI FGADC_CON0 FGADC_CON1 FGADC_CON2 FGADC_CON3 FGADC_CON4 FGADC_CON5 FGADC_RST_CON0 FGADC_CAR_CON0 FGADC_CAR_CON1 FGADC_CARTH_CON0 FGADC_CARTH_CON1 FGADC_CARTH_CON2 FGADC_CARTH_CON3 FGADC_NCAR_CON0 FGADC_NCAR_CON1 FGADC_NCAR_CON2 FGADC_NCAR_CON3 FGADC_IAVG_CON0 FGADC_IAVG_CON1 FGADC_IAVG_CON2 FGADC_IAVG_CON3 FGADC_IAVG_CON4 FGADC_IAVG_CON5 FGADC_NTER_CON0 FGADC_NTER_CON1 FGADC_SON_CON0 FGADC_SON_CON1

FGADC_SOFF_CON1 FGADC_SOFF_CON2 FGADC_SOFF_CON3 FGADC_SOFF_CON4 FGADC_ZCV_CON0

MediaTek Proprietary and Confidential.

Width

Register Function

16

BM_TOP_INT Raw Status Register 1

16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

BM_TOP_INT MISC Control Register BM_TOP_DBG_CON BM_TOP Reserved Register 0 BM Write Protection Key 0 BM Write Protection Key 1 BM Write Protection Key 2 FGADC_ANA Design ID Register FGADC_ANA Design Revision Register 0 FGADC_ANA Design Bank Information Register FGADC_ANA Design Extra Information Register FGADC_ANA Control Register 0 FGADC_ANA_TEST Control Register 0 FGADC_ANA Number of ELR Register FGADC_ANA ELR Register 0 FGADC0 Design ID Register FGADC0 Design Revision Register 0 FGADC0 Design Bank Information Register FGADC0 Design Extra Information Register FGADC Control Register 0 FGADC Control Register 1 FGADC Control Register 2 FGADC Control Register 3 FGADC Control Register 4 FGADC Control Register 5 FGADC_RST Control Register 0 FGADC_CAR Control Register 0 FGADC_CAR Control Register 1 FGADC_CARTH Control Register 0 FGADC_CARTH Control Register 1 FGADC_CARTH Control Register 2 FGADC_CARTH Control Register 3 FGADC_NCAR Control Register 0 FGADC_NCAR Control Register 1 FGADC_NCAR Control Register 2 FGADC_NCAR Control Register 3 FGADC_IAVG Control Register 0 FGADC_IAVG Control Register 1 FGADC_IAVG Control Register 2 FGADC_IAVG Control Register 3 FGADC_IAVG Control Register 4 FGADC_IAVG Control Register 5 FGADC_NTER Control Register 0 FGADC_NTER Control Register 1 FGADC_SON Control Register 0 FGADC_SON Control Register 1

16 16 16 16 16

FGADC_SOFF Control Register 1 FGADC_SOFF Control Register 2 FGADC_SOFF Control Register 3 FGADC_SOFF Control Register 4 FGADC_ZCV Control Register 0

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Page 311 of 1067

ol Register 8 ol Register 9

MT6359 PMIC Datasheet Confidential A Address 00000D50 00000D52 00000D54 00000D58 00000D5A 00000D80 00000D82 00000D84 00000D86 00000D88 00000D8A 00000D8C 00000D8E 00000D90 00000D92 00000D94 00000D96 00000D98 00000D9A 00000D9C 00000D9E 00000E00 00000E02 00000E04 00000E06 00000E08 00000E0A 00000E0C 00000E80 00000E82 00000E84 00000E86 00000E88 00000E8A 00000E8C 00000F00 00000F02 00000F04 00000F06 00000F08 00000F0A 00000F0C 00000F0E 00000F10 00000F12 00000F14 00000F16 00000F18 00000F1A 00000F1C 00000F1E 00000F20 00000F22

Name FGADC_ZCV_CON1 FGADC_ZCV_CON2 FGADC_ZCV_CON3 FGADC_ZCVTH_CON0 FGADC_ZCVTH_CON1 FGADC1_DSN_ID FGADC1_DSN_REV0 FGADC1_DSN_DBI FGADC1_DSN_DXI FGADC_R_CON0 FGADC_CUR_CON0 FGADC_CUR_CON1 FGADC_CUR_CON2 FGADC_CUR_CON3 FGADC_OFFSET_CON0 FGADC_OFFSET_CON1 FGADC_GAIN_CON0 FGADC_TEST_CON0 SYSTEM_INFO_CON0 SYSTEM_INFO_CON1 SYSTEM_INFO_CON2 BATON_ANA_DSN_ID BATON_ANA_DSN_REV0 BATON_ANA_DSN_DBI BATON_ANA_DSN_DXI BATON_ANA_CON0 BATON_ANA_MON0 BIF_ANA_MON0 BATON_DSN_ID BATON_DSN_REV0 BATON_DSN_DBI BATON_DSN_DXI BATON_CON0 BATON_CON1 BATON_CON2 BIF_DSN_ID BIF_DSN_REV0 BIF_DSN_DBI BIF_DSN_DXI BIF_CON0 BIF_CON1 BIF_CON2 BIF_CON3 BIF_CON4 BIF_CON5 BIF_CON6 BIF_CON7

BIF_CON10 BIF_CON11 BIF_CON12 BIF_CON13

MediaTek Proprietary and Confidential.

Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

16 16 16 16

Register Function FGADC_ZCV Control Register 1 FGADC_ZCV Control Register 2 FGADC_ZCV Control Register 3 FGADC_ZCVTH Control Register 0 FGADC_ZCVTH Control Register 1 FGADC1 Design ID Register FGADC1 Design Revision Register 0 FGADC1 Design Bank Information Register FGADC1 Design Extra Information Register FGADC_R Control Register 0 FGADC_CUR Control Register 0 FGADC_CUR Control Register 1 FGADC_CUR Control Register 2 FGADC_CUR Control Register 3 FGADC_OFFSET Control Register 0 FGADC_OFFSET Control Register 1 FGADC_GAIN Control Register 0 FGADC_TEST Control Register 0 SYSTEM_INFO Control Register 0 SYSTEM_INFO Control Register 1 SYSTEM_INFO Control Register 2 BATON_ANA Design ID Register BATON_ANA Design Revision Register 0 BATON_ANA Design Bank Information Register BATON_ANA Design Extra Information Register BATON Analog Control Register 0 BATON Analog Monitor Register 0 BIF Analog Monitor Register 0 BATON Design ID Register BATON Design Revision Register 0 BATON Design Bank Information Register BATON Design Extra Information Register BATON Control Register 0 BATON Control Register 1 BATON Control Register 2 BIF Design ID Register BIF Design Revision Register 0 BIF Design Bank Information Register BIF Design Extra Information Register BIF Control Register 0 BIF Control Register 1 BIF Control Register 2 BIF Control Register 3 BIF Control Register 4 BIF Control Register 5 BIF Control Register 6 BIF Control Register 7

BIF Control Register 10 BIF Control Register 11 BIF Control Register 12 BIF Control Register 13

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Page 312 of 1067

MON_CON2 CHR_CON

MT6359 PMIC Datasheet Confidential A Address 00000F24 00000F26 00000F28 00000F2A 00000F2C 00000F2E 00000F30 00000F32 00000F34 00000F36 00000F38 00000F3A 00000F3C 00000F3E 00000F40 00000F42 00000F44 00000F46 00000F48 00000F4A 00000F4C 00000F4E 00000F50 00000F52 00000F54 00000F56 00000F80 00000F82 00000F84 00000F86 00000F88 00000F8A 00000F8C 00000F8E 00000F90 00000F92 00000F94 00000F96 00000F98 00000F9A 00000F9C 00000F9E 00000FA0 00000FA2 00000FA4 00000FA6 00000FA8 00000FAA 00000FAC 00000FAE 00000FB0 00000FB2

Name BIF_CON14 BIF_CON15 BIF_CON16 BIF_CON17 BIF_CON18 BIF_CON19 BIF_CON20 BIF_CON21 BIF_CON22 BIF_CON23 BIF_CON24 BIF_CON25 BIF_CON26 BIF_CON27 BIF_CON28 BIF_CON29 BIF_CON30 BIF_CON31 BIF_CON32 BIF_CON33 BIF_CON34 BIF_CON35 BIF_CON36 BIF_CON37 BIF_CON38 BIF_CON39 HK_TOP_ID HK_TOP_REV0 HK_TOP_DBI HK_TOP_DXI HK_TPM0 HK_TPM1 HK_TOP_CLK_CON0 HK_TOP_CLK_CON1 HK_TOP_RST_CON0 HK_TOP_INT_CON0 HK_TOP_INT_CON0_SET HK_TOP_INT_CON0_CLR HK_TOP_INT_MASK_CON0 HK_TOP_INT_MASK_CON0_S ET HK_TOP_INT_MASK_CON0_C LR HK_TOP_INT_STATUS0 HK_TOP_INT_RAW_STATUS0 HK_TOP_MON_CON0 HK_TOP_MON_CON1

HK_TOP_ANA_CON HK_TOP_AUXADC_ANA HK_TOP_STRUP HK_TOP_LDO_CON HK_TOP_LDO_STATUS

MediaTek Proprietary and Confidential.

Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

Register Function BIF Control Register 14 BIF Control Register 15 BIF Control Register 16 BIF Control Register 17 BIF Control Register 18 BIF Control Register 19 BIF Control Register 20 BIF Control Register 21 BIF Control Register 22 BIF Control Register 23 BIF Control Register 24 BIF Control Register 25 BIF Control Register 26 BIF Control Register 27 BIF Control Register 28 BIF Control Register 29 BIF Control Register 30 BIF Control Register 31 BIF Control Register 32 BIF Control Register 33 BIF Control Register 34 BIF Control Register 35 BIF Control Register 36 BIF Control Register 37 BIF Control Register 38 BIF Control Register 39 Register HK_TOP Design ID Register Register HK_TOP Design Revision Register 0 HK_TOP Design Bank Information Register HK_Design Extra Information Register HK_TOP Parameter 0 HK_TOP Parameter 1 HK_TOP_CLK_CON0 HK_TOP_CLK_CON1 HK_TOP_RST_CON0 HK_TOP_INT_CON0 HK_TOP_INT_CON0_SET HK_TOP_INT_CON0_CLR HK_TOP_INT_MASK_CON0

16

HK_TOP_INT_MASK_CON0_SET

16

HK_TOP_INT_MASK_CON0_CLR

16 16 16 16

HK_TOP_INT_STATUS0 HK_TOP_INT_RAW_STATUS0 HK_TOP_MON_CON0 HK_TOP_MON_CON1

16 16 16 16 16

HK_TOP_ANA_CON HK_TOP_AUXADC_ANA HK_TOP_STRUP HK_TOP_LDO_CON HK_TOP_LDO_STATUS

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Page 313 of 1067

ADC Register 40 _STA0

MT6359 PMIC Datasheet Confidential A Address 00000FB4 00001000 00001002 00001004 00001006 00001008 0000100A 0000100C 0000100E 00001080 00001082

Name HK_TOP_WKEY AUXADC_DSN_ID AUXADC_DSN_REV0 AUXADC_DSN_DBI AUXADC_DSN_FPI AUXADC_ANA_CON0 AUXADC_ANA_CON1 AUXADC_ELR_NUM AUXADC_ELR_0 AUXADC_DIG_1_DSN_ID AUXADC_DIG_1_DSN_REV0

00001084

AUXADC_DIG_1_DSN_DBI

16

00001086

AUXADC_DIG_1_DSN_DXI

16

00001088 0000108A 0000108C 0000108E 00001090 00001092 00001094 00001096 00001098 0000109A 0000109C 0000109E 000010A0 000010A2 000010A4 000010A6 000010A8 000010AA 000010AC 000010AE 000010B0 000010B2 000010B4 000010B6 000010B8 000010BA 000010BC 000010BE 000010C0 000010C2 000010C4 000010C6 000010C8 000010CA 000010CC 000010CE 00001100 00001102

AUXADC_ADC0 AUXADC_ADC1 AUXADC_ADC2 AUXADC_ADC3 AUXADC_ADC4 AUXADC_ADC5 AUXADC_ADC6 AUXADC_ADC7 AUXADC_ADC8 AUXADC_ADC9 AUXADC_ADC10 AUXADC_ADC11 AUXADC_ADC12 AUXADC_ADC15 AUXADC_ADC16 AUXADC_ADC17 AUXADC_ADC18 AUXADC_ADC19 AUXADC_ADC20 AUXADC_ADC21 AUXADC_ADC22 AUXADC_ADC23 AUXADC_ADC24 AUXADC_ADC26 AUXADC_ADC27 AUXADC_ADC30 AUXADC_ADC32 AUXADC_ADC33 AUXADC_ADC34 AUXADC_ADC37 AUXADC_ADC38 AUXADC_ADC39

16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

Register Function HK_TOP_WKEY Register AUXADC Design ID Register Register AUXADC Design Revision Register 0 Register AUXADC Design Bank Information Register AUXADC Design Extra Information Register AUXADC Control Register 0 AUXADC Control Register 1 AUXADC Number of ELR Register AUXADC ELR 0 Register Register AUXADC_DIG_1 Design ID Register Register AUXADC_DIG_1 Design Revision Register 0 Register AUXADC_DIG_1 Design Bank Information Register Register AUXADC_DIG_1 Design Extra Information Register AUXADC ADC Register 0 AUXADC ADC Register 1 AUXADC ADC Register 2 AUXADC ADC Register 3 AUXADC ADC Register 4 AUXADC ADC Register 5 AUXADC ADC Register 6 AUXADC ADC Register 7 AUXADC ADC Register 8 AUXADC ADC Register 9 AUXADC ADC Register 10 AUXADC ADC Register 11 AUXADC ADC Register 12 AUXADC ADC Register 15 AUXADC ADC Register 16 AUXADC ADC Register 17 AUXADC ADC Register 18 AUXADC ADC Register 19 AUXADC ADC Register 20 AUXADC ADC Register 21 AUXADC ADC Register 22 AUXADC ADC Register 23 AUXADC ADC Register 24 AUXADC ADC Register 26 AUXADC ADC Register 27 AUXADC ADC Register 30 AUXADC ADC Register 32 AUXADC ADC Register 33 AUXADC ADC Register 34 AUXADC ADC Register 37 AUXADC ADC Register 38 AUXADC ADC Register 39

AUXADC_STA1 AUXADC_STA2 AUXADC_DIG_2_DSN_ID AUXADC_DIG_2_DSN_REV0

16 16 16 16

AUXADC_STA1 AUXADC_STA2 Register AUXADC_DIG_2 Design ID Register Register AUXADC_DIG_2 Design Revision Register 0

MediaTek Proprietary and Confidential.

Width 16 16 16 16 16 16 16 16 16 16 16

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 314 of 1067

_NAG_9

MT6359 PMIC Datasheet Confidential A Address

Name

00001104

AUXADC_DIG_2_DSN_DBI

16

00001106

AUXADC_DIG_2_DSN_DXI

16

00001108 0000110A 00001180 00001182

AUXADC_RQST0 AUXADC_RQST1 AUXADC_DIG_3_DSN_ID AUXADC_DIG_3_DSN_REV0

16 16 16 16

00001184

AUXADC_DIG_3_DSN_DBI

16

00001186

AUXADC_DIG_3_DSN_DXI

16

00001188 0000118A 0000118C 0000118E 00001190 00001192 00001194 00001196 00001198 0000119A 0000119C 0000119E 000011A0 000011A2 000011A4 000011A6 000011A8 000011AA 000011AC 000011AE 000011B0 000011B2 000011B4 000011B6 000011B8 000011BA 000011BC 000011BE 000011C0 000011C2 000011C4 000011C6 000011C8 000011CA 000011CC 000011CE 000011D0 000011D2 000011D4 000011D6 000011D8 000011DA

AUXADC_CON0 AUXADC_CON0_SET AUXADC_CON0_CLR AUXADC_CON1 AUXADC_CON2 AUXADC_CON3 AUXADC_CON4 AUXADC_CON5 AUXADC_CON6 AUXADC_CON7 AUXADC_CON8 AUXADC_CON9 AUXADC_CON10 AUXADC_CON11 AUXADC_CON12 AUXADC_CON13 AUXADC_CON14 AUXADC_CON15 AUXADC_CON16 AUXADC_CON17 AUXADC_CON18 AUXADC_CON19 AUXADC_CON20 AUXADC_CON21 AUXADC_AUTORPT0 AUXADC_ACCDET AUXADC_DBG0 AUXADC_NAG_0 AUXADC_NAG_1 AUXADC_NAG_2 AUXADC_NAG_3 AUXADC_NAG_4 AUXADC_NAG_5 AUXADC_NAG_6 AUXADC_NAG_7 AUXADC_NAG_8

16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

Register Function Register AUXADC_DIG_2 Design Bank Information Register Register AUXADC_DIG_2 Design Extra Information Register AUXADC_RQST0 AUXADC_RQST1 Register AUXADC_DIG_3 Design ID Register Register AUXADC_DIG_3 Design Revision Register 0 Register AUXADC_DIG_3 Design Bank Information Register Register AUXADC_DIG_3 Design Extra Information Register AUXADC_CON0 AUXADC_CON0_SET AUXADC_CON0_CLR AUXADC_CON1 AUXADC_CON2 AUXADC_CON3 AUXADC_CON4 AUXADC_CON5 AUXADC_CON6 AUXADC_CON7 AUXADC_CON8 AUXADC_CON9 AUXADC_CON10 AUXADC_CON11 AUXADC_CON12 AUXADC_CON13 AUXADC_CON14 AUXADC_CON15 AUXADC_CON16 AUXADC_CON17 AUXADC_CON18 AUXADC_CON19 AUXADC_CON20 AUXADC_CON21 AUXADC_AUTORPT0 AUXADC_ACCDET AUXADC_DBG0 AUXADC_NAG_0 AUXADC_NAG_1 AUXADC_NAG_2 AUXADC_NAG_3 AUXADC_NAG_4 AUXADC_NAG_5 AUXADC_NAG_6 AUXADC_NAG_7 AUXADC_NAG_8

AUXADC_NAG_10 AUXADC_NAG_11 AUXADC_DIG_3_ELR_NUM AUXADC_DIG_3_ELR0 AUXADC_DIG_3_ELR1

16 16 16 16 16

AUXADC_NAG_10 AUXADC_NAG_11 Register AUXADC_DIG_3 Number of ELR Register AUXADC_DIG_3_ELR0 AUXADC_DIG_3_ELR1

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Width

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Page 315 of 1067

_LBAT2_1 _LBAT2_2

MT6359 PMIC Datasheet Confidential A Address 000011DC 000011DE 000011E0 000011E2 000011E4 000011E6 000011E8 000011EA 000011EC 000011EE 000011F0 000011F2 000011F4 000011F6 000011F8 00001200 00001202

Name AUXADC_DIG_3_ELR2 AUXADC_DIG_3_ELR3 AUXADC_DIG_3_ELR4 AUXADC_DIG_3_ELR5 AUXADC_DIG_3_ELR6 AUXADC_DIG_3_ELR7 AUXADC_DIG_3_ELR8 AUXADC_DIG_3_ELR9 AUXADC_DIG_3_ELR10 AUXADC_DIG_3_ELR11 AUXADC_DIG_3_ELR12 AUXADC_DIG_3_ELR13 AUXADC_DIG_3_ELR14 AUXADC_DIG_3_ELR15 AUXADC_DIG_3_ELR16 AUXADC_DIG_4_DSN_ID AUXADC_DIG_4_DSN_REV0

00001204

AUXADC_DIG_4_DSN_DBI

16

00001206

AUXADC_DIG_4_DSN_DXI

16

00001208 0000120A 0000120C 0000120E 00001210 00001212 00001214 00001216 00001218 0000121A 0000121C 0000121E 00001220 00001222 00001224 00001226 00001228 0000122A 0000122C 0000122E 00001230 00001232 00001234 00001236 00001238 0000123A 0000123C 0000123E 00001240 00001242 00001244 00001246 00001248

AUXADC_IMP0 AUXADC_IMP1 AUXADC_IMP2 AUXADC_IMP3 AUXADC_IMP4 AUXADC_IMP5 AUXADC_LBAT0 AUXADC_LBAT1 AUXADC_LBAT2 AUXADC_LBAT3 AUXADC_LBAT4 AUXADC_LBAT5 AUXADC_LBAT6 AUXADC_LBAT7 AUXADC_LBAT8 AUXADC_BAT_TEMP_0 AUXADC_BAT_TEMP_1 AUXADC_BAT_TEMP_2 AUXADC_BAT_TEMP_3 AUXADC_BAT_TEMP_4 AUXADC_BAT_TEMP_5 AUXADC_BAT_TEMP_6 AUXADC_BAT_TEMP_7 AUXADC_BAT_TEMP_8 AUXADC_BAT_TEMP_9 AUXADC_LBAT2_0

16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

Register Function AUXADC_DIG_3_ELR2 AUXADC_DIG_3_ELR3 AUXADC_DIG_3_ELR4 AUXADC_DIG_3_ELR5 AUXADC_DIG_3_ELR6 AUXADC_DIG_3_ELR7 AUXADC_DIG_3_ELR8 AUXADC_DIG_3_ELR9 AUXADC_DIG_3_ELR10 AUXADC_DIG_3_ELR11 AUXADC_DIG_3_ELR12 AUXADC_DIG_3_ELR13 AUXADC_DIG_3_ELR14 AUXADC_DIG_3_ELR15 AUXADC_DIG_3_ELR16 Register AUXADC_DIG_4 Design ID Register Register AUXADC_DIG_4 Design Revision Register 0 Register AUXADC_DIG_4 Design Bank Information Register Register AUXADC_DIG_4 Design Extra Information Register AUXADC_IMP0 AUXADC_IMP1 AUXADC_IMP2 AUXADC_IMP3 AUXADC_IMP4 AUXADC_IMP5 AUXADC_LBAT0 AUXADC_LBAT1 AUXADC_LBAT2 AUXADC_LBAT3 AUXADC_LBAT4 AUXADC_LBAT5 AUXADC_LBAT6 AUXADC_LBAT7 AUXADC_LBAT8 AUXADC_BAT_TEMP_0 AUXADC_BAT_TEMP_1 AUXADC_BAT_TEMP_2 AUXADC_BAT_TEMP_3 AUXADC_BAT_TEMP_4 AUXADC_BAT_TEMP_5 AUXADC_BAT_TEMP_6 AUXADC_BAT_TEMP_7 AUXADC_BAT_TEMP_8 AUXADC_BAT_TEMP_9 AUXADC_LBAT2_0

AUXADC_LBAT2_3 AUXADC_LBAT2_4 AUXADC_LBAT2_5 AUXADC_LBAT2_6 AUXADC_LBAT2_7

16 16 16 16 16

AUXADC_LBAT2_3 AUXADC_LBAT2_4 AUXADC_LBAT2_5 AUXADC_LBAT2_6 AUXADC_LBAT2_7

MediaTek Proprietary and Confidential.

Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

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Page 316 of 1067

MT6359 PMIC Datasheet Confidential A Address 0000124A 0000124C 0000124E 00001250 00001252 00001254 00001256 00001258 0000125A 0000125C 0000125E 00001260 00001262 00001264 00001266 00001268 0000126A 0000126C 0000126E 00001270 00001272 00001274 00001276 00001278 0000127A 00001400 00001402 00001404 00001406 00001408 0000140A 0000140C 0000140E 00001410 00001412 00001414 00001416 00001418 0000141A 0000141C 0000141E 00001420 00001422 00001424 00001426 00001428 0000142A

Name AUXADC_LBAT2_8 AUXADC_THR0 AUXADC_THR1 AUXADC_THR2 AUXADC_THR3 AUXADC_THR4 AUXADC_THR5 AUXADC_THR6 AUXADC_THR7 AUXADC_THR8 AUXADC_MDRT_0 AUXADC_MDRT_1 AUXADC_MDRT_2 AUXADC_MDRT_3 AUXADC_MDRT_4 AUXADC_MDRT_5 AUXADC_DCXO_MDRT_1 AUXADC_DCXO_MDRT_2 AUXADC_DCXO_MDRT_3 AUXADC_DCXO_MDRT_4 AUXADC_RSV_1 AUXADC_PRI_NEW AUXADC_SPL_LIST_0 AUXADC_SPL_LIST_1 AUXADC_SPL_LIST_2 BUCK_TOP_DSN_ID BUCK_TOP_DSN_REV0 BUCK_TOP_DBI BUCK_TOP_DXI BUCK_TOP_PAM0 BUCK_TOP_PAM1 BUCK_TOP_CLK_CON0 BUCK_TOP_CLK_CON0_SET BUCK_TOP_CLK_CON0_CLR BUCK_TOP_CLK_HWEN_CON 0 BUCK_TOP_CLK_HWEN_CON 0_SET BUCK_TOP_CLK_HWEN_CON 0_CLR BUCK_TOP_INT_CON0 BUCK_TOP_INT_CON0_SET BUCK_TOP_INT_CON0_CLR BUCK_TOP_INT_MASK_CON 0 BUCK_TOP_INT_MASK_CON 0_SET BUCK_TOP_INT_MASK_CON 0_CLR BUCK_TOP_INT_STATUS0 BUCK_TOP_INT_RAW_STATU S0 BUCK_TOP_VOW_CON BUCK_TOP_STB_CON

MediaTek Proprietary and Confidential.

Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

Register Function AUXADC_LBAT2_8 AUXADC_THR0 AUXADC_THR1 AUXADC_THR2 AUXADC_THR3 AUXADC_THR4 AUXADC_THR5 AUXADC_THR6 AUXADC_THR7 AUXADC_THR8 AUXADC_MDRT_0 AUXADC_MDRT_1 AUXADC_MDRT_2 AUXADC_MDRT_3 AUXADC_MDRT_4 AUXADC_MDRT_5 AUXADC_DCXO_MDRT_1 AUXADC_DCXO_MDRT_2 AUXADC_DCXO_MDRT_3 AUXADC_DCXO_MDRT_4 AUXADC_RSV_1 AUXADC_PRI_NEW AUXADC_SPL_LIST_0 AUXADC_SPL_LIST_1 AUXADC_SPL_LIST_2 BUCK_TOP Design ID Register BUCK_TOP Design Revision Register 0 BUCK_TOP Design Bank Information Register BUCK_TOP Design Extra Information Register BUCK_TOP Parameter 0 BUCK_TOP Parameter 1 BUCK_TOP Clock Control 0 BUCK_TOP Clock Control 0 SET BUCK_TOP Clock Control 0 CLR

16

BUCK_TOP Clock HWEN Control 0

16

BUCK_TOP Clock HWEN Control 0 SET

16

BUCK_TOP Clock HWEN Control CLR

16 16 16

BUCK_TOP Interrupt Enable Control 0 BUCK_TOP Interrupt Enable Control 0 SET BUCK_TOP Interrupt Enable Control 0 CLR

16

BUCK_TOP Interrupt Mask Control 0

16

BUCK_TOP Interrupt Mask Control 0 SET

16

BUCK_TOP Interrupt Mask Control 0 CLR

16

BUCK_TOP Interrupt Status 0

16

BUCK_TOP Interrupt Raw Status 0

16 16

BUCK_TOP VOW Control Register BUCK_TOP STB Control Resister

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Page 317 of 1067

MT6359 PMIC Datasheet Confidential A Address 0000142C 0000142E

ORE Config 0 ORE Operation Enable

00001430 00001432 00001434 00001436 00001438 0000143A 0000143C 0000143E 00001440 00001442 00001444 00001480 00001482 00001484 00001486 00001488 0000148A 0000148C 0000148E 00001490 00001492 00001494 00001496 00001498 0000149A 0000149C 0000149E 000014A0 000014A2 000014A4 000014A6 000014A8 000014AA 000014AC 00001500 00001502 00001504 00001506 00001508 0000150A 0000150C 0000150E 00001510 00001512 00001514 00001516 00001518 0000151A 0000151C 0000151E

Name BUCK_TOP_VGP2_MINFREQ _CON BUCK_TOP_VPA_MINFREQ_ CON BUCK_TOP_OC_CON0 BUCK_TOP_KEY_PROT BUCK_TOP_WDTDBG0 BUCK_TOP_WDTDBG1 BUCK_TOP_WDTDBG2 BUCK_TOP_WDTDBG3 BUCK_TOP_WDTDBG4 BUCK_TOP_ELR_NUM BUCK_TOP_ELR0 BUCK_TOP_ELR1 BUCK_TOP_ELR2 BUCK_VPU_DSN_ID BUCK_VPU_DSN_REV0 BUCK_VPU_DSN_DBI BUCK_VPU_DSN_DXI BUCK_VPU_CON0 BUCK_VPU_CON0_SET BUCK_VPU_CON0_CLR BUCK_VPU_CON1 BUCK_VPU_SLP_CON BUCK_VPU_CFG0 BUCK_VPU_OP_EN BUCK_VPU_OP_EN_SET BUCK_VPU_OP_EN_CLR BUCK_VPU_OP_CFG BUCK_VPU_OP_CFG_SET BUCK_VPU_OP_CFG_CLR BUCK_VPU_OP_MODE BUCK_VPU_OP_MODE_SET BUCK_VPU_OP_MODE_CLR BUCK_VPU_DBG0 BUCK_VPU_DBG1 BUCK_VPU_ELR_NUM BUCK_VPU_ELR0 BUCK_VCORE_DSN_ID BUCK_VCORE_DSN_REV0 BUCK_VCORE_DSN_DBI BUCK_VCORE_DSN_DXI BUCK_VCORE_CON0 BUCK_VCORE_CON0_SET BUCK_VCORE_CON0_CLR BUCK_VCORE_CON1 BUCK_VCORE_SLP_CON

Width

BUCK_VCORE_OP_EN_SET BUCK_VCORE_OP_EN_CLR BUCK_VCORE_OP_CFG BUCK_VCORE_OP_CFG_SET BUCK_VCORE_OP_CFG_CLR

MediaTek Proprietary and Confidential.

Register Function

16

BUCK_TOP VGP2 MINFREQ Control Resister

16

BUCK_TOP VPA MINFREQ Control Resister

16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

BUCK_TOP OC Control Register 0 BUCK_TOP Write Protect Key BUCK_TOP WDTDBG0 BUCK_TOP WDTDBG1 BUCK_TOP WDTDBG2 BUCK_TOP WDTDBG3 BUCK_TOP WDTDBG4 BUCK_TOP Number of ELR Register BUCK_TOP ELR 0 Register BUCK_TOP ELR 1 Register BUCK_TOP ELR 2 Register BUCK VPU Design ID Register BUCK VPU Design Revision Register 0 BUCK VPU Design Bank Information Register BUCK_VPU Design Extra Information Register BUCK VPU Control 0 BUCK VPU Control 0 SET BUCK VPU Control 0 CLR BUCK VPU Control 1 BUCK VPU Sleep Control BUCK VPU Config 0 BUCK VPU Operation Enable BUCK VPU Operation Enable SET BUCK VPU Operation Enable CLR BUCK VPU Operation Config BUCK VPU Operation Config SET BUCK VPU Operation Config CLR BUCK VPU Operation Mode BUCK VPU Operation Mode SET BUCK VPU Operation Mode CLR BUCK VPU Debug 0 BUCK VPU Debug 1 BUCK_VPU Number of ELR Register BUCK_VPU ELR 0 Register BUCK VCORE Design ID Register BUCK VCORE Design Revision Register 0 BUCK VCORE Design Bank Information Register BUCK_VCORE Design Extra Information Register BUCK VCORE Control 0 BUCK VCORE Control 0 SET BUCK VCORE Control 0 CLR BUCK VCORE Control 1 BUCK VCORE Sleep Control

16 16 16 16 16

BUCK VCORE Operation Enable SET BUCK VCORE Operation Enable CLR BUCK VCORE Operation Config BUCK VCORE Operation Config SET BUCK VCORE Operation Config CLR

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 318 of 1067

PU12 Sleep Control

MT6359 PMIC Datasheet Confidential A Address 00001520 00001522 00001524 00001526 00001528 0000152A 0000152C 00001580 00001582 00001584 00001586 00001588 0000158A 0000158C 0000158E 00001590 00001592 00001594 00001596 00001598 0000159A 0000159C 0000159E 000015A0 000015A2 000015A4 000015A6 000015A8 000015AA 000015AC 000015AE 000015B0 000015B2 000015B4 00001600 00001602 00001604 00001606 00001608 0000160A 0000160C 0000160E 00001610 00001612 00001614 00001616 00001618 0000161A

Name BUCK_VCORE_OP_MODE BUCK_VCORE_OP_MODE_SE T BUCK_VCORE_OP_MODE_CL R BUCK_VCORE_DBG0 BUCK_VCORE_DBG1 BUCK_VCORE_ELR_NUM BUCK_VCORE_ELR0 BUCK_VGPU11_DSN_ID BUCK_VGPU11_DSN_REV0 BUCK_VGPU11_DSN_DBI BUCK_VGPU11_DSN_DXI BUCK_VGPU11_CON0 BUCK_VGPU11_CON0_SET BUCK_VGPU11_CON0_CLR BUCK_VGPU11_CON1 BUCK_VGPU11_SLP_CON BUCK_VGPU11_CFG0 BUCK_VGPU11_OP_EN BUCK_VGPU11_OP_EN_SET BUCK_VGPU11_OP_EN_CLR BUCK_VGPU11_OP_CFG BUCK_VGPU11_OP_CFG_SET BUCK_VGPU11_OP_CFG_CLR BUCK_VGPU11_OP_MODE BUCK_VGPU11_OP_MODE_S ET BUCK_VGPU11_OP_MODE_C LR BUCK_VGPU11_DBG0 BUCK_VGPU11_DBG1 BUCK_VGPU11_SSHUB_CON 0 BUCK_VGPU11_SPI_CON0 BUCK_VGPU11_BT_LP_CON0 BUCK_VGPU11_STALL_TRAC K0 BUCK_VGPU11_ELR_NUM BUCK_VGPU11_ELR0 BUCK_VGPU12_DSN_ID BUCK_VGPU12_DSN_REV0 BUCK_VGPU12_DSN_DBI BUCK_VGPU12_DSN_DXI BUCK_VGPU12_CON0 BUCK_VGPU12_CON0_SET BUCK_VGPU12_CON0_CLR BUCK_VGPU12_CON1

Width 16

BUCK_VGPU12_CFG0 BUCK_VGPU12_OP_EN BUCK_VGPU12_OP_EN_SET BUCK_VGPU12_OP_EN_CLR BUCK_VGPU12_OP_CFG

MediaTek Proprietary and Confidential.

Register Function BUCK VCORE Operation Mode

16

BUCK VCORE Operation Mode SET

16

BUCK VCORE Operation Mode CLR

16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

BUCK VCORE Debug 0 BUCK VCORE Debug 1 BUCK_VCORE Number of ELR Register BUCK_VCORE ELR 0 Register BUCK VGPU11 Design ID Register BUCK VGPU11 Design Revision Register 0 BUCK VGPU11 Design Bank Information Register BUCK_VGPU11 Design Extra Information Register BUCK VGPU11 Control 0 BUCK VGPU11 Control 0 SET BUCK VGPU11 Control 0 CLR BUCK VGPU11 Control 1 BUCK VGPU11 Sleep Control BUCK VGPU11 Config 0 BUCK VGPU11 Operation Enable BUCK VGPU11 Operation Enable SET BUCK VGPU11 Operation Enable CLR BUCK VGPU11 Operation Config BUCK VGPU11 Operation Config SET BUCK VGPU11 Operation Config CLR BUCK VGPU11 Operation Mode

16

BUCK VGPU11 Operation Mode SET

16

BUCK VGPU11 Operation Mode CLR

16 16

BUCK VGPU11 Debug 0 BUCK VGPU11 Debug 1

16

BUCK VGPU11 Sensor Hub Control Resister 0

16 16

BUCK VGPU11 SPI Control Resister 0 BUCK VGPU11 BT_LPControl Resister 0

16

BUCK_VGPU11 HW Stall Tracking Register 0

16 16 16 16 16 16 16 16 16 16

BUCK_VGPU11 Number of ELR Register BUCK_VGPU11 ELR 0 Register BUCK VGPU12 Design ID Register BUCK VGPU12 Design Revision Register 0 BUCK VGPU12 Design Bank Information Register BUCK_VGPU12 Design Extra Information Register BUCK VGPU12 Control 0 BUCK VGPU12 Control 0 SET BUCK VGPU12 Control 0 CLR BUCK VGPU12 Control 1

16 16 16 16 16

BUCK VGPU12 Config 0 BUCK VGPU12 Operation Enable BUCK VGPU12 Operation Enable SET BUCK VGPU12 Operation Enable CLR BUCK VGPU12 Operation Config

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Page 319 of 1067

ROC1 Control 0 CLR ROC1 Control 1

MT6359 PMIC Datasheet Confidential A Address 0000161C 0000161E 00001620 00001622 00001624 00001626 00001628 0000162A 0000162C 00001680 00001682 00001684 00001686 00001688 0000168A 0000168C 0000168E 00001690 00001692 00001694 00001696 00001698 0000169A 0000169C 0000169E 000016A0 000016A2 000016A4 000016A6 000016A8 000016AA 000016AC 000016AE 00001700 00001702 00001704 00001706 00001708 0000170A 0000170C 0000170E 00001710 00001712 00001714 00001716

Name BUCK_VGPU12_OP_CFG_SET BUCK_VGPU12_OP_CFG_CLR BUCK_VGPU12_OP_MODE BUCK_VGPU12_OP_MODE_S ET BUCK_VGPU12_OP_MODE_C LR BUCK_VGPU12_DBG0 BUCK_VGPU12_DBG1 BUCK_VGPU12_ELR_NUM BUCK_VGPU12_ELR0 BUCK_VMODEM_DSN_ID BUCK_VMODEM_DSN_REV0 BUCK_VMODEM_DSN_DBI BUCK_VMODEM_DSN_DXI BUCK_VMODEM_CON0 BUCK_VMODEM_CON0_SET BUCK_VMODEM_CON0_CLR BUCK_VMODEM_CON1 BUCK_VMODEM_SLP_CON BUCK_VMODEM_CFG0 BUCK_VMODEM_OP_EN BUCK_VMODEM_OP_EN_SE T BUCK_VMODEM_OP_EN_CL R BUCK_VMODEM_OP_CFG BUCK_VMODEM_OP_CFG_SE T BUCK_VMODEM_OP_CFG_CL R BUCK_VMODEM_OP_MODE BUCK_VMODEM_OP_MODE _SET BUCK_VMODEM_OP_MODE _CLR BUCK_VMODEM_DBG0 BUCK_VMODEM_DBG1 BUCK_VMODEM_STALL_TRA CK0 BUCK_VMODEM_ELR_NUM BUCK_VMODEM_ELR0 BUCK_VPROC1_DSN_ID BUCK_VPROC1_DSN_REV0 BUCK_VPROC1_DSN_DBI BUCK_VPROC1_DSN_DXI BUCK_VPROC1_CON0 BUCK_VPROC1_CON0_SET

BUCK_VPROC1_SLP_CON BUCK_VPROC1_CFG0 BUCK_VPROC1_OP_EN BUCK_VPROC1_OP_EN_SET

MediaTek Proprietary and Confidential.

Width 16 16 16

Register Function BUCK VGPU12 Operation Config SET BUCK VGPU12 Operation Config CLR BUCK VGPU12 Operation Mode

16

BUCK VGPU12 Operation Mode SET

16

BUCK VGPU12 Operation Mode CLR

16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

BUCK VGPU12 Debug 0 BUCK VGPU12 Debug 1 BUCK_VGPU12 Number of ELR Register BUCK_VGPU12 ELR 0 Register BUCK VMODEM Design ID Register BUCK VMODEM Design Revision Register 0 BUCK VMODEM Design Bank Information Register BUCK_VMODEM Design Extra Information Register BUCK VMODEM Control 0 BUCK VMODEM Control 0 SET BUCK VMODEM Control 0 CLR BUCK VMODEM Control 1 BUCK VMODEM Sleep Control BUCK VMODEM Config 0 BUCK VMODEM Operation Enable

16

BUCK VMODEM Operation Enable SET

16

BUCK VMODEM Operation Enable CLR

16

BUCK VMODEM Operation Config

16

BUCK VMODEM Operation Config SET

16

BUCK VMODEM Operation Config CLR

16

BUCK VMODEM Operation Mode

16

BUCK VMODEM Operation Mode SET

16

BUCK VMODEM Operation Mode CLR

16 16

BUCK VMODEM Debug 0 BUCK VMODEM Debug 1

16

BUCK_VMODEM HW Stall Tracking Register 0

16 16 16 16 16 16 16 16

BUCK_VMODEM Number of ELR Register BUCK_VMODEM ELR 0 Register BUCK VPROC1 Design ID register BUCK VPROC1 Design Revision Register 0 BUCK VPROC1 Design Bank Information Register BUCK_VPROC1 Design Extra Information Register BUCK VPROC1 Control 0 BUCK VPROC1 Control 0 SET

16 16 16 16

BUCK VPROC1 Sleep Control BUCK VPROC1 CONFIG 0 BUCK VPROC1 Operation Enable BUCK VPROC1 Operation Enable SET

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 320 of 1067

1 Control 0

MT6359 PMIC Datasheet Confidential A Address 00001718 0000171A 0000171C 0000171E 00001720 00001722 00001724 00001726 00001728 0000172A 0000172C 0000172E 00001780 00001782 00001784 00001786 00001788 0000178A 0000178C 0000178E 00001790 00001792 00001794 00001796 00001798 0000179A 0000179C 0000179E 000017A0 000017A2 000017A4 000017A6 000017A8 000017AA 000017AC 000017AE 000017B0 000017B2 00001800 00001802 00001804 00001806 00001808 0000180A 0000180C 0000180E 00001810 00001812

Name BUCK_VPROC1_OP_EN_CLR BUCK_VPROC1_OP_CFG BUCK_VPROC1_OP_CFG_SET BUCK_VPROC1_OP_CFG_CLR BUCK_VPROC1_OP_MODE BUCK_VPROC1_OP_MODE_S ET BUCK_VPROC1_OP_MODE_C LR BUCK_VPROC1_DBG0 BUCK_VPROC1_DBG1 BUCK_VPROC1_STALL_TRAC K0 BUCK_VPROC1_ELR_NUM BUCK_VPROC1_ELR0 BUCK_VPROC2_DSN_ID BUCK_VPROC2_DSN_REV0 BUCK_VPROC2_DSN_DBI BUCK_VPROC2_DSN_DXI BUCK_VPROC2_CON0 BUCK_VPROC2_CON0_SET BUCK_VPROC2_CON0_CLR BUCK_VPROC2_CON1 BUCK_VPROC2_SLP_CON BUCK_VPROC2_CFG0 BUCK_VPROC2_OP_EN BUCK_VPROC2_OP_EN_SET BUCK_VPROC2_OP_EN_CLR BUCK_VPROC2_OP_CFG BUCK_VPROC2_OP_CFG_SET BUCK_VPROC2_OP_CFG_CLR BUCK_VPROC2_OP_MODE BUCK_VPROC2_OP_MODE_S ET BUCK_VPROC2_OP_MODE_C LR BUCK_VPROC2_DBG0 BUCK_VPROC2_DBG1 BUCK_VPROC2_TRACK0 BUCK_VPROC2_TRACK1 BUCK_VPROC2_STALL_TRAC K0 BUCK_VPROC2_ELR_NUM BUCK_VPROC2_ELR0 BUCK_VS1_DSN_ID BUCK_VS1_DSN_REV0 BUCK_VS1_DSN_DBI BUCK_VS1_DSN_DXI BUCK_VS1_CON0_SET BUCK_VS1_CON0_CLR BUCK_VS1_CON1 BUCK_VS1_SLP_CON BUCK_VS1_CFG0

MediaTek Proprietary and Confidential.

Width 16 16 16 16 16

Register Function BUCK VPROC1 Operation Enable CLR BUCK VPROC1 Operation Config BUCK VPROC1 Operation Config SET BUCK VPROC1 Operation Config CLR BUCK VPROC1 Operation Mode

16

BUCK VPROC1 Operation Mode SET

16

BUCK VPROC1 Operation Mode CLR

16 16

BUCK VPROC1 Debug 0 BUCK VPROC1 Debug 1

16

BUCK_VPROC1 HW Stall Tracking Register 0

16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

BUCK_VPROC1 Number of ELR Register BUCK_VPROC1 ELR 0 Register BUCK VPROC2 Design ID Register BUCK VPROC2 Design Revision Register 0 BUCK VPROC2 Design Bank Information Register BUCK_VPROC2 Design Extra Information Register BUCK VPROC2 Control 0 BUCK VPROC2 Control 0 SET BUCK VPROC2 Control 0 CLR BUCK VPROC2 Control 1 BUCK VPROC2 Sleep Control BUCK VPROC2 Config 0 BUCK VPROC2 Operation Enable BUCK VPROC2 Operation Enable SET BUCK VPROC2 Operation Enable CLR BUCK VPROC2 Operation Config BUCK VPROC2 Operation Config SET BUCK VPROC2 Operation Config CLR BUCK VPROC2 Operation Mode

16

BUCK VPROC2 Operation Mode SET

16

BUCK VPROC2 Operation Mode CLR

16 16 16 16

BUCK VPROC2 Debug 0 BUCK VPROC2 Debug 1 BUCK_VPROC2 HW Tracking Register 0 BUCK_VPROC2 HW Tracking Register 1

16

BUCK_VPROC2 HW Stall Tracking Register 0

16 16 16 16 16 16

BUCK_VPROC2 Number of ELR Register BUCK_VPROC2 ELR 0 Register BUCK VS1 Design ID Register BUCK VS1 Design Revision Register 0 BUCK VS1 Design Bank Information Register BUCK_VS1 Design Extra Information Register

16 16 16 16 16

BUCK VS1 Control 0 SET BUCK VS1 Control 0 CLR BUCK VS1 Control 1 BUCK VS1 Sleep Control BUCK VS1 Config 0

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Page 321 of 1067

MT6359 PMIC Datasheet Confidential A

Address 00001814 00001816 00001818 0000181A 0000181C 0000181E 00001820 00001822 00001824 00001826 00001828 0000182A 0000182C 0000182E 00001830 00001832 00001834 00001880 00001882 00001884 00001886 00001888 0000188A 0000188C 0000188E 00001890 00001892 00001894 00001896 00001898 0000189A 0000189C 0000189E 000018A0 000018A2 000018A4 000018A6 000018A8 000018AA 000018AC 000018AE 000018B0 000018B2 000018B4 00001900 00001902 00001904 00001906 A Design Extra Information Register 00001908 A Control 0 0000190A 0000190C 0000190E 00001910

Name BUCK_VS1_OP_EN BUCK_VS1_OP_EN_SET BUCK_VS1_OP_EN_CLR BUCK_VS1_OP_CFG BUCK_VS1_OP_CFG_SET BUCK_VS1_OP_CFG_CLR BUCK_VS1_OP_MODE BUCK_VS1_OP_MODE_SET BUCK_VS1_OP_MODE_CLR BUCK_VS1_DBG0 BUCK_VS1_DBG1 BUCK_VS1_VOTER BUCK_VS1_VOTER_SET BUCK_VS1_VOTER_CLR BUCK_VS1_VOTER_CFG BUCK_VS1_ELR_NUM BUCK_VS1_ELR0 BUCK_VS2_DSN_ID BUCK_VS2_DSN_REV0 BUCK_VS2_DSN_DBI BUCK_VS2_DSN_DXI BUCK_VS2_CON0 BUCK_VS2_CON0_SET BUCK_VS2_CON0_CLR BUCK_VS2_CON1 BUCK_VS2_SLP_CON BUCK_VS2_CFG0 BUCK_VS2_OP_EN BUCK_VS2_OP_EN_SET BUCK_VS2_OP_EN_CLR BUCK_VS2_OP_CFG BUCK_VS2_OP_CFG_SET BUCK_VS2_OP_CFG_CLR BUCK_VS2_OP_MODE BUCK_VS2_OP_MODE_SET BUCK_VS2_OP_MODE_CLR BUCK_VS2_DBG0 BUCK_VS2_DBG1 BUCK_VS2_VOTER BUCK_VS2_VOTER_SET BUCK_VS2_VOTER_CLR BUCK_VS2_VOTER_CFG BUCK_VS2_ELR_NUM BUCK_VS2_ELR0 BUCK_VPA_DSN_ID BUCK_VPA_DSN_REV0 BUCK_VPA_DSN_DBI

BUCK_VPA_CON0_SET BUCK_VPA_CON0_CLR BUCK_VPA_CON1 BUCK_VPA_CFG0

MediaTek Proprietary and Confidential.

Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

16 16 16 16

Register Function BUCK VS1 Operation Enable BUCK VS1 Operation Enable SET BUCK VS1 Operation Enable CLR BUCK VS1 Operation Config BUCK VS1 Operation Config SET BUCK VS1 Operation Config CLR BUCK VS1 Operation Mode BUCK VS1 Operation Mode SET BUCK VS1 Operation Mode CLR BUCK VS1 Debug 0 BUCK VS1 Debug 1 BUCK VS1 VOTER BUCK VS1 VOTER SET BUCK VS1 VOTER CLR BUCK VS1 VOTER Configure BUCK_VS1 Number of ELR Register BUCK_VS1 ELR 0 Register BUCK VS2 Design ID Register BUCK VS2 Design Revision Register 0 BUCK VS2 Design Bank Information Register BUCK_VS2 Design Extra Information Register BUCK VS2 Control 0 BUCK VS2 Control 0 SET BUCK VS2 Control 0 CLR BUCK VS2 Control 1 BUCK VS2 Sleep Control BUCK VS2 Config 0 BUCK VS2 Operation Enable BUCK VS2 Operation Enable SET BUCK VS2 Operation Enable CLR BUCK VS2 Operation Config BUCK VS2 Operation Config SET BUCK VS2 Operation Config CLR BUCK VS2 Operation Mode BUCK VS2 Operation Mode SET BUCK VS2 Operation Mode CLR BUCK VS2 Debug 0 BUCK VS2 Debug 1 BUCK VS2 VOTER BUCK VS2 VOTER SET BUCK VS2 VOTER CLR BUCK VS2 VOTER Configure BUCK_VS2 Number of ELR Register BUCK_VS2 ELR 0 Register BUCK VPA Design ID Register BUCK VPA Design Revision Register 0 BUCK VPA Design Bank Information Register

BUCK VPA Control 0 SET BUCK VPA Control 0 CLR BUCK VPA Control 1 BUCK VPA CONFIG 0

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Page 322 of 1067

Control Register 0

MT6359 PMIC Datasheet Confidential A Address 00001912 00001914 00001916 00001918 0000191A 0000191C 0000191E 00001920 00001922 00001924 00001926

Name BUCK_VPA_CFG1 BUCK_VPA_DBG0 BUCK_VPA_DBG1 BUCK_VPA_DLC_CON0 BUCK_VPA_DLC_CON1 BUCK_VPA_DLC_CON2 BUCK_VPA_MSFG_CON0 BUCK_VPA_MSFG_CON1 BUCK_VPA_MSFG_RRATE0 BUCK_VPA_MSFG_RRATE1 BUCK_VPA_MSFG_RRATE2

Width 16 16 16 16 16 16 16 16 16 16 16

00001928

BUCK_VPA_MSFG_RTHD0

16

0000192A

BUCK_VPA_MSFG_RTHD1

16

0000192C

BUCK_VPA_MSFG_RTHD2

16

0000192E 00001930 00001932

BUCK_VPA_MSFG_FRATE0 BUCK_VPA_MSFG_FRATE1 BUCK_VPA_MSFG_FRATE2

16 16 16

00001934

BUCK_VPA_MSFG_FTHD0

16

00001936

BUCK_VPA_MSFG_FTHD1

16

00001938

BUCK_VPA_MSFG_FTHD2

16

00001980 00001982 00001984 00001986 00001988 0000198A 0000198C 0000198E 00001990 00001992 00001994 00001996 00001998 0000199A 0000199C 0000199E 000019A0 000019A2 000019A4 000019A6 000019A8 000019AA 000019AC 000019AE 000019B0 000019B2 000019B4 000019B6

BUCK_ANA0_DSN_ID BUCK_ANA0_DSN_REV0 BUCK_ANA0_DSN_DBI BUCK_ANA0_DSN_FPI SMPS_ANA_CON0 VGPUVCORE_ANA_CON0 VGPUVCORE_ANA_CON1 VGPUVCORE_ANA_CON2 VGPUVCORE_ANA_CON3 VGPUVCORE_ANA_CON4 VGPUVCORE_ANA_CON5 VGPUVCORE_ANA_CON6 VGPUVCORE_ANA_CON7 VGPUVCORE_ANA_CON8 VGPUVCORE_ANA_CON9 VGPUVCORE_ANA_CON10 VGPUVCORE_ANA_CON11 VGPUVCORE_ANA_CON12 VGPUVCORE_ANA_CON13 VGPUVCORE_ANA_CON14 VGPUVCORE_ANA_CON15 VGPUVCORE_ANA_CON16

16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

Register Function BUCK VPA CONFIG 1 BUCK VPA Debug 0 BUCK VPA Debug 1 BUCK VPA DLC Control Register 0 BUCK VPA DLC Control Register 1 BUCK VPA DLC Control Register 2 BUCK VPA Multi-Soft-Chang Control Register 0 BUCK VPA Multi-Soft-Chang Control Register 1 BUCK VPA Multi-Soft-Chang Rising Rate Register 0 BUCK VPA Multi-Soft-Chang Rising Rate Register 1 BUCK VPA Multi-Soft-Chang Rising Rate Register 2 BUCK VPA Multi-Soft-Chang Rising Threshold Register 0 BUCK VPA Multi-Soft-Chang Rising Threshold Register 1 BUCK VPA Multi-Soft-Chang Rising Threshold Register 2 BUCK VPA Multi-Soft-Chang Falling Rate Register 0 BUCK VPA Multi-Soft-Chang Falling Rate Register 1 BUCK VPA Multi-Soft-Chang Falling Rate Register 2 BUCK VPA Multi-Soft-Chang Falling Threshold Register 0 BUCK VPA Multi-Soft-Chang Falling Threshold Register 1 BUCK VPA Multi-Soft-Chang Falling Threshold Register 2 BUCK_ANA0 Design ID register BUCK_ANA0 Design Revision Register 0 BUCK_ANA0 Design Bank Information Register BUCK_ANA0 Design Extra Information Register SMPS Control Register 0 VGPUVCORE Control Register 0 VGPUVCORE Control Register 1 VGPUVCORE Control Register 2 VGPUVCORE Control Register 3 VGPUVCORE Control Register 4 VGPUVCORE Control Register 5 VGPUVCORE Control Register 6 VGPUVCORE Control Register 7 VGPUVCORE Control Register 8 VGPUVCORE Control Register 9 VGPUVCORE Control Register 10 VGPUVCORE Control Register 11 VGPUVCORE Control Register 12 VGPUVCORE Control Register 13 VGPUVCORE Control Register 14 VGPUVCORE Control Register 15 VGPUVCORE Control Register 16

VPROC1_ANA_CON1 VPROC1_ANA_CON2 VPROC1_ANA_CON3 VPROC1_ANA_CON4 VPROC1_ANA_CON5

16 16 16 16 16

VPROC1 Control Register 1 VPROC1 Control Register 2 VPROC1 Control Register 3 VPROC1 Control Register 4 VPROC1 Control Register 5

MediaTek Proprietary and Confidential.

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rol Register 1 rol Register 2

MT6359 PMIC Datasheet Confidential A Address 000019B8 000019BA 000019BC 000019BE 000019C0 000019C2 000019C4 000019C6 000019C8 000019CA 000019CC 000019CE 000019D0 000019D2 000019D4 000019D6 000019D8 000019DA 000019DC 000019DE 00001A00 00001A02 00001A04 00001A06 00001A08 00001A0A 00001A0C 00001A0E 00001A10 00001A12 00001A14 00001A16 00001A18 00001A1A 00001A1C 00001A1E 00001A20 00001A22 00001A24 00001A26 00001A28 00001A2A 00001A2C 00001A2E 00001A30 00001A32 00001A34 00001A36 00001A38 00001A3A 00001A3C 00001A3E 00001A40

Name BUCK_ANA0_ELR_NUM SMPS_ELR_0 SMPS_ELR_1 SMPS_ELR_2 SMPS_ELR_3 SMPS_ELR_4 SMPS_ELR_5 SMPS_ELR_6 SMPS_ELR_7 SMPS_ELR_8 SMPS_ELR_9 SMPS_ELR_10 SMPS_ELR_11 SMPS_ELR_12 SMPS_ELR_13 SMPS_ELR_14 SMPS_ELR_15 SMPS_ELR_16 SMPS_ELR_17 SMPS_ELR_18 BUCK_ANA1_DSN_ID BUCK_ANA1_DSN_REV0 BUCK_ANA1_DSN_DBI BUCK_ANA1_DSN_FPI VPROC2_ANA_CON0 VPROC2_ANA_CON1 VPROC2_ANA_CON2 VPROC2_ANA_CON3 VPROC2_ANA_CON4 VPROC2_ANA_CON5 VMODEM_ANA_CON0 VMODEM_ANA_CON1 VMODEM_ANA_CON2 VMODEM_ANA_CON3 VMODEM_ANA_CON4 VMODEM_ANA_CON5 VPU_ANA_CON0 VPU_ANA_CON1 VPU_ANA_CON2 VPU_ANA_CON3 VPU_ANA_CON4 VPU_ANA_CON5 VS1_ANA_CON0 VS1_ANA_CON1 VS1_ANA_CON2 VS1_ANA_CON3 VS2_ANA_CON0

VS2_ANA_CON3 VPA_ANA_CON0 VPA_ANA_CON1 VPA_ANA_CON2

MediaTek Proprietary and Confidential.

Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

16 16 16 16

Register Function BUCK_ANA0 Number of ELR Register SMPS ELR 0 Register SMPS ELR 1 Register SMPS ELR 2 Register SMPS ELR 3 Register SMPS ELR 4 Register SMPS ELR 5 Register SMPS ELR 6 Register SMPS ELR 7 Register SMPS ELR 8 Register SMPS ELR 9 Register SMPS ELR 10 Register SMPS ELR 11 Register SMPS ELR 12 Register SMPS ELR 13 Register SMPS ELR 14 Register SMPS ELR 15 Register SMPS ELR 16 Register SMPS ELR 17 Register SMPS ELR 18 Register BUCK_ANA1 Design ID Register BUCK_ANA1 Design Revision Register 0 BUCK_ANA1 Design Bank Information Register BUCK_ANA1 Design Extra Information Register VPROC2 Control Register 0 VPROC2 Control Register 1 VPROC2 Control Register 2 VPROC2 Control Register 3 VPROC2 Control Register 4 VPROC2 Control Register 5 VMODEM Control Register 0 VMODEM Control Register 1 VMODEM Control Register 2 VMODEM Control Register 3 VMODEM Control Register 4 VMODEM Control Register 5 VPU Control Register 0 VPU Control Register 1 VPU Control Register 2 VPU Control Register 3 VPU Control Register 4 VPU Control Register 5 VS1 Control Register 0 VS1 Control Register 1 VS1 Control Register 2 VS1 Control Register 3 VS2 Control Register 0

VS2 Control Register 3 VPA Control Register 0 VPA Control Register 1 VPA Control Register 2

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Page 324 of 1067

MT6359 PMIC Datasheet Confidential A Address 00001A42 00001A44 00001A46 00001A48 00001A4A 00001A4C 00001A4E 00001A50 00001A52 00001A54 00001A56 00001A58 00001A5A 00001A5C 00001A5E 00001A60 00001A62 00001A64 00001A66 00001B00 00001B02 00001B04 00001B06 00001B08 00001B0A 00001B0C 00001B0E 00001B10 00001B12 00001B14 00001B16 00001B18 00001B1A 00001B1C 00001B1E 00001B20 00001B22 00001B24 00001B26 00001B28 00001B2A 00001B2C 00001B2E 00001B30 00001B32 00001B34 00001B36

Name VPA_ANA_CON3 VPA_ANA_CON4 BUCK_ANA1_ELR_NUM VPROC2_ELR_0 VPROC2_ELR_1 VPROC2_ELR_2 VPROC2_ELR_3 VPROC2_ELR_4 VPROC2_ELR_5 VPROC2_ELR_6 VPROC2_ELR_7 VPROC2_ELR_8 VPROC2_ELR_9 VPROC2_ELR_10 VPROC2_ELR_11 VPROC2_ELR_12 VPROC2_ELR_13 VPROC2_ELR_14 VPROC2_ELR_15 LDO_TOP_ID LDO_TOP_REV0 LDO_TOP_DBI LDO_TOP_DXI LDO_TPM0 LDO_TPM1 LDO_TOP_CKPDN_CON0 TOP_TOP_CKHWEN_CON0 LDO_TOP_CLK_DCM_CON0 LDO_TOP_CLK_VSRAM_CON 0 LDO_TOP_INT_CON0 LDO_TOP_INT_CON0_SET LDO_TOP_INT_CON0_CLR LDO_TOP_INT_CON1 LDO_TOP_INT_MASK_CON0 LDO_TOP_INT_MASK_CON0_ SET LDO_TOP_INT_MASK_CON0_ CLR LDO_TOP_INT_MASK_CON1 LDO_TOP_INT_MASK_CON1_ SET LDO_TOP_INT_MASK_CON1_ CLR LDO_TOP_INT_STATUS0 LDO_TOP_INT_STATUS1 LDO_TOP_INT_RAW_STATUS 0 LDO_TOP_INT_RAW_STATUS 1 LDO_TEST_CON0 LDO_TOP_CON VRTC28_CON VAUX18_ACK

MediaTek Proprietary and Confidential.

Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

Register Function VPA Control Register 3 VPA Control Register 4 BUCK_ANA1 Number of ELR Register VPROC2 ELR 0 Register VPROC2 ELR 1 Register VPROC2 ELR 2 Register VPROC2 ELR 3 Register VPROC2 ELR 4 Register VPROC2 ELR 5 Register VPROC2 ELR 6 Register VPROC2 ELR 7 Register VPROC2 ELR 8 Register VPROC2 ELR 9 Register VPROC2 ELR 10 Register VPROC2 ELR 11 Register VPROC2 ELR 12 Register VPROC2 ELR 13 Register VPROC2 ELR 14 Register VPROC2 ELR 15 Register LDO_TOP Design ID Register LDO_TOP Design Revision Register 0 LDO_TOP Design Bank Information Register LDO_TOP Design Extra Information Register LDO_TOP Parameter 0 LDO_TOP Parameter 1 LDO_TOP_CKPDN Control Register 0 LDO_TOP_CKHWEN Control Register 0 LDO DCM Control Register 0

16

LDO VSRAM Clock Gating Control Register 0

16 16 16 16 16

LDO_TOP INT Control Register 0 LDO_TOP INT Control Register 0 SET LDO_TOP INT Control Register 0 CLR LDO_TOP INT Control Register 1 LDO_TOP INT Mask Control Register 0

16

LDO_TOP INT Mask Control Register 0 SET

16

LDO_TOP INT Mask Control Register 0 CLR

16

LDO_TOP INT Mask Control Register 1

16

LDO_TOP INT Mask Control Register 1 SET

16

LDO_TOP INT Mask Control Register 1 CLR

16 16

LDO_TOP INT Status Register 0 LDO_TOP INT Status Register 1

16

LDO_TOP INT Raw Status Register 0

16

LDO_TOP INT Raw Status Register 1

16 16 16 16

LDO Test Control 0 LDO Top Control Register VRTC28 Control Register 0 VAUX18 acktime Register 0

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 325 of 1067

MT6359 PMIC Datasheet Confidential A

Address 00001B38 00001B3A 00001B3C 00001B3E 00001B40 00001B42 00001B44 00001B46 00001B48 00001B4A 00001B4C 00001B4E 00001B80 00001B82 00001B84 00001B86 00001B88 00001B8A 00001B8C 00001B8E 00001B90 00001B92 00001B94 00001B96 00001B98 00001B9A 00001B9C 00001B9E 00001BA0 00001BA2 00001BA4 00001BA6 00001BA8 00001BAA 00001BAC 00001BAE 00001BB0 00001BB2 00001BB4 00001BB6 00001BB8 00001BBA 00001BBC 00001BBE 00001BC0 00001BC2 00001BC4 12 Operation Enable SET 00001BC6 12 Operation Enable CLR 00001BC8 00001BCA 00001BCC 00001BCE 00001BD0

Name VBIF28_ACK VOW_DVS_CON VXO22_CON LDO_TOP_ELR_NUM LDO_VRFCK_ELR LDO_VSRAM_VLIMIT_ELR LDO_VSRAM_PROC1_ELR LDO_VSRAM_PROC2_ELR LDO_VSRAM_OTHERS_ELR LDO_VSRAM_MD_ELR LDO_VEMC_ELR_0 LDO_VEMC_ELR_1 LDO_GNR0_DSN_ID LDO_GNR0_DSN_REV0 LDO_GNR0_DSN_DBI LDO_GNR0_DSN_DXI LDO_VFE28_CON0 LDO_VFE28_CON1 LDO_VFE28_MON LDO_VFE28_OP_EN LDO_VFE28_OP_EN_SET LDO_VFE28_OP_EN_CLR LDO_VFE28_OP_CFG LDO_VFE28_OP_CFG_SET LDO_VFE28_OP_CFG_CLR LDO_VXO22_CON0 LDO_VXO22_CON1 LDO_VXO22_MON LDO_VXO22_OP_EN LDO_VXO22_OP_EN_SET LDO_VXO22_OP_EN_CLR LDO_VXO22_OP_CFG LDO_VXO22_OP_CFG_SET LDO_VXO22_OP_CFG_CLR LDO_VRF18_CON0 LDO_VRF18_CON1 LDO_VRF18_MON LDO_VRF18_OP_EN LDO_VRF18_OP_EN_SET LDO_VRF18_OP_EN_CLR LDO_VRF18_OP_CFG LDO_VRF18_OP_CFG_SET LDO_VRF18_OP_CFG_CLR LDO_VRF12_CON0 LDO_VRF12_CON1 LDO_VRF12_MON LDO_VRF12_OP_EN

Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

LDO_VRF12_OP_CFG LDO_VRF12_OP_CFG_SET LDO_VRF12_OP_CFG_CLR LDO_VEFUSE_CON0

16 16 16 16

MediaTek Proprietary and Confidential.

Register Function VBIF28 acktime Register 0 VOW dvs Register 0 VXO22 Test Register 0 LDO_TOP Number of ELR Register LDO VRFCK eFuse Bit0 LDO VSRAM_VLIMIT eFuse Bit0 LDO VSRAM_PROC1 eFuse Bit0 LDO VSRAM_PROC2 eFuse Bit0 LDO VSRAM_OTHERS eFuse Bit0 LDO VSRAM_MD eFuse Bit0 LDO VEMC eFuse Bit0 LDO VEMC eFuse Bit3 LDO_GNR0 Design ID Register LDO_GNR0 Design Revision Register 0 LDO_GNR0 Design Bank Information Register LDO_GNR0 Design Extra Information Register LDO VFE28 Control 0 LDO VFE28 Control 1 LDO VFE28 Monitor LDO VFE28 Operation Enable LDO VFE28 Operation Enable SET LDO VFE28 Operation Enable CLR LDO VFE28 Operation Config LDO VFE28 Operation Config SET LDO VFE28 Operation Config CLR LDO VXO22 Control 0 LDO VXO22 Control 1 LDO VXO22 Monitor LDO VXO22 Operation Enable LDO VXO22 Operation Enable SET LDO VXO22 Operation Enable CLR LDO VXO22 Operation Config LDO VXO22 Operation Config SET LDO VXO22 Operation Config CLR LDO VRF18 Control 0 LDO VRF18 Control 1 LDO VRF18 Monitor LDO VRF18 Operation Enable LDO VRF18 Operation Enable SET LDO VRF18 Operation Enable CLR LDO VRF18 Operation Config LDO VRF18 Operation Config SET LDO VRF18 Operation Config CLR LDO VRF12 Control 0 LDO VRF12 Control 1 LDO VRF12 Monitor LDO VRF12 Operation Enable

LDO VRF12 Operation Config LDO VRF12 Operation Config SET LDO VRF12 Operation Config CLR LDO VEFUSE Control 0

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Page 326 of 1067

MT6359 PMIC Datasheet Confidential A

Address 00001BD2 00001BD4 00001BD6 00001BD8 00001BDA 00001BDC 00001BDE 00001BE0 00001BE2 00001BE4 00001BE6 00001BE8 00001BEA 00001BEC 00001BEE 00001BF0 00001BF2 00001BF4 00001C00 00001C02 00001C04 00001C06 00001C08 00001C0A 00001C0C 00001C0E 00001C10 00001C12 00001C14 00001C16 00001C18 00001C1A 00001C1C 00001C1E 00001C20 00001C22 00001C24 00001C26 00001C28 00001C2A 00001C2C 00001C2E 00001C30 00001C32 00001C34 00001C36 00001C38 00001C3A 18 Operation Config 18 Operation Config SET 00001C3C 00001C3E 00001C40 00001C42 00001C44

Name LDO_VEFUSE_CON1 LDO_VEFUSE_MON LDO_VEFUSE_OP_EN LDO_VEFUSE_OP_EN_SET LDO_VEFUSE_OP_EN_CLR LDO_VEFUSE_OP_CFG LDO_VEFUSE_OP_CFG_SET LDO_VEFUSE_OP_CFG_CLR LDO_VCN33_1_CON0 LDO_VCN33_1_CON1 LDO_VCN33_1_MON LDO_VCN33_1_OP_EN LDO_VCN33_1_OP_EN_SET LDO_VCN33_1_OP_EN_CLR LDO_VCN33_1_OP_CFG LDO_VCN33_1_OP_CFG_SET LDO_VCN33_1_OP_CFG_CLR LDO_VCN33_1_MULTI_SW LDO_GNR1_DSN_ID LDO_GNR1_DSN_REV0 LDO_GNR1_DSN_DBI LDO_GNR1_DSN_DXI LDO_VCN33_2_CON0 LDO_VCN33_2_CON1 LDO_VCN33_2_MON LDO_VCN33_2_OP_EN LDO_VCN33_2_OP_EN_SET LDO_VCN33_2_OP_EN_CLR LDO_VCN33_2_OP_CFG LDO_VCN33_2_OP_CFG_SET LDO_VCN33_2_OP_CFG_CLR LDO_VCN33_2_MULTI_SW LDO_VCN13_CON0 LDO_VCN13_CON1 LDO_VCN13_MON LDO_VCN13_OP_EN LDO_VCN13_OP_EN_SET LDO_VCN13_OP_EN_CLR LDO_VCN13_OP_CFG LDO_VCN13_OP_CFG_SET LDO_VCN13_OP_CFG_CLR LDO_VCN18_CON0 LDO_VCN18_CON1 LDO_VCN18_MON LDO_VCN18_OP_EN LDO_VCN18_OP_EN_SET LDO_VCN18_OP_EN_CLR

LDO_VCN18_OP_CFG_CLR LDO_VA09_CON0 LDO_VA09_CON1 LDO_VA09_MON

MediaTek Proprietary and Confidential.

Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

16 16 16 16

Register Function LDO VEFUSE Control 1 LDO VEFUSE Monitor LDO VEFUSE Operation Enable LDO VEFUSE Operation Enable SET LDO VEFUSE Operation Enable CLR LDO VEFUSE Operation Config LDO VEFUSE Operation Config SET LDO VEFUSE Operation Config CLR LDO VCN33_1 Control 0 LDO VCN33_1 Control 1 LDO VCN33_1 Monitor LDO VCN33_1 Operation Enable LDO VCN33_1 Operation Enable SET LDO VCN33_1 Operation Enable CLR LDO VCN33_1 Operation Config LDO VCN33_1 Operation Config SET LDO VCN33_1 Operation Config CLR LDO VCN33_1 Multi-SW User LDO_GNR1 Design ID Register LDO_GNR1 Design Revision Register 0 LDO_GNR1 Design Bank Information Register LDO_GNR1 Design Extra Information Register LDO VCN33_2 Control 0 LDO VCN33_2 Control 1 LDO VCN33_2 Monitor LDO VCN33_2 Operation Enable LDO VCN33_2 Operation Enable SET LDO VCN33_2 Operation Enable CLR LDO VCN33_2 Operation Config LDO VCN33_2 Operation Config SET LDO VCN33_2 Operation Config CLR LDO VCN33_2 Multi-SW User LDO VCN13 Control 0 LDO VCN13 Control 1 LDO VCN13 Monitor LDO VCN13 Operation Enable LDO VCN13 Operation Enable SET LDO VCN13 Operation Enable CLR LDO VCN13 Operation Config LDO VCN13 Operation Config SET LDO VCN13 Operation Config CLR LDO VCN18 Control 0 LDO VCN18 Control 1 LDO VCN18 Monitor LDO VCN18 Operation Enable LDO VCN18 Operation Enable SET LDO VCN18 Operation Enable CLR

LDO VCN18 Operation Config CLR LDO VA09 Control 0 LDO VA09 Control 1 LDO VA09 Monitor

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 327 of 1067

18 Control 1 18 Monitor

MT6359 PMIC Datasheet Confidential A Address 00001C46 00001C48 00001C4A 00001C4C 00001C4E 00001C50 00001C52 00001C54 00001C56 00001C58 00001C5A 00001C5C 00001C5E 00001C60 00001C62 00001C64 00001C66 00001C68 00001C6A 00001C6C 00001C6E 00001C70 00001C72 00001C74 00001C80 00001C82 00001C84 00001C86 00001C88 00001C8A 00001C8C 00001C8E 00001C90 00001C92 00001C94 00001C96 00001C98 00001C9A 00001C9C 00001C9E 00001CA0 00001CA2 00001CA4 00001CA6 00001CA8 00001CAA 00001CAC 00001CAE 00001CB0 00001CB2 00001CB4 00001CB6 00001CB8

Name LDO_VA09_OP_EN LDO_VA09_OP_EN_SET LDO_VA09_OP_EN_CLR LDO_VA09_OP_CFG LDO_VA09_OP_CFG_SET LDO_VA09_OP_CFG_CLR LDO_VCAMIO_CON0 LDO_VCAMIO_CON1 LDO_VCAMIO_MON LDO_VCAMIO_OP_EN LDO_VCAMIO_OP_EN_SET LDO_VCAMIO_OP_EN_CLR LDO_VCAMIO_OP_CFG LDO_VCAMIO_OP_CFG_SET LDO_VCAMIO_OP_CFG_CLR LDO_VA12_CON0 LDO_VA12_CON1 LDO_VA12_MON LDO_VA12_OP_EN LDO_VA12_OP_EN_SET LDO_VA12_OP_EN_CLR LDO_VA12_OP_CFG LDO_VA12_OP_CFG_SET LDO_VA12_OP_CFG_CLR LDO_GNR2_DSN_ID LDO_GNR2_DSN_REV0 LDO_GNR2_DSN_DBI LDO_GNR2_DSN_DXI LDO_VAUX18_CON0 LDO_VAUX18_CON1 LDO_VAUX18_MON LDO_VAUX18_OP_EN LDO_VAUX18_OP_EN_SET LDO_VAUX18_OP_EN_CLR LDO_VAUX18_OP_CFG LDO_VAUX18_OP_CFG_SET LDO_VAUX18_OP_CFG_CLR LDO_VAUD18_CON0 LDO_VAUD18_CON1 LDO_VAUD18_MON LDO_VAUD18_OP_EN LDO_VAUD18_OP_EN_SET LDO_VAUD18_OP_EN_CLR LDO_VAUD18_OP_CFG LDO_VAUD18_OP_CFG_SET LDO_VAUD18_OP_CFG_CLR LDO_VIO18_CON0

LDO_VIO18_OP_EN LDO_VIO18_OP_EN_SET LDO_VIO18_OP_EN_CLR LDO_VIO18_OP_CFG

MediaTek Proprietary and Confidential.

Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

16 16 16 16

Register Function LDO VA09 Operation Enable LDO VA09 Operation Enable SET LDO VA09 Operation Enable CLR LDO VA09 Operation Config LDO VA09 Operation Config SET LDO VA09 Operation Config CLR LDO VCAMIO Control 0 LDO VCAMIO Control 1 LDO VCAMIO Monitor LDO VCAMIO Operation Enable LDO VCAMIO Operation Enable SET LDO VCAMIO Operation Enable CLR LDO VCAMIO Operation Config LDO VCAMIO Operation Config SET LDO VCAMIO Operation Config CLR LDO VA12 Control 0 LDO VA12 Control 1 LDO VA12 Monitor LDO VA12 Operation Enable LDO VA12 Operation Enable SET LDO VA12 Operation Enable CLR LDO VA12 Operation Config LDO VA12 Operation Config SET LDO VA12 Operation Config CLR LDO_GNR2 Design ID Register LDO_GNR2 Design Revision Register 0 LDO_GNR2 Design Bank Information Register LDO_GNR2 Design Extra Information Register LDO VAUX18 Control 0 LDO VAUX18 Control 1 LDO VAUX18 Monitor LDO VAUX18 Operation Enable LDO VAUX18 Operation Enable SET LDO VAUX18 Operation Enable CLR LDO VAUX18 Operation Config LDO VAUX18 Operation Config SET LDO VAUX18 Operation Config CLR LDO VAUD18 Control 0 LDO VAUD18 Control 1 LDO VAUD18 Monitor LDO VAUD18 Operation Enable LDO VAUD18 Operation Enable SET LDO VAUD18 Operation Enable CLR LDO VAUD18 Operation Config LDO VAUD18 Operation Config SET LDO VAUD18 Operation Config CLR LDO VIO18 Control 0

LDO VIO18 Operation Enable LDO VIO18 Operation Enable SET LDO VIO18 Operation Enable CLR LDO VIO18 Operation Config

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Page 328 of 1067

MT6359 PMIC Datasheet Confidential A

Address 00001CBA 00001CBC 00001CBE 00001CC0 00001CC2 00001CC4 00001CC6 00001CC8 00001CCA 00001CCC 00001CCE 00001CD0 00001CD2 00001CD4 00001CD6 00001CD8 00001CDA 00001CDC 00001CDE 00001CE0 00001CE2 00001CE4 00001CE6 00001CE8 00001CEA 00001CEC 00001CEE 00001CF0 00001CF2 00001D00 00001D02 00001D04 00001D06 00001D08 00001D0A 00001D0C 00001D0E 00001D10 00001D12 00001D14 00001D16 00001D18 00001D1A 00001D1C 00001D1E 00001D20 00001D22 CK Operation Enable SET 00001D24 CK Operation Enable CLR 00001D26 00001D28 00001D2A 00001D2C 00001D2E

Name LDO_VIO18_OP_CFG_SET LDO_VIO18_OP_CFG_CLR LDO_VEMC_CON0 LDO_VEMC_CON1 LDO_VEMC_MON LDO_VEMC_OP_EN LDO_VEMC_OP_EN_SET LDO_VEMC_OP_EN_CLR LDO_VEMC_OP_CFG LDO_VEMC_OP_CFG_SET LDO_VEMC_OP_CFG_CLR LDO_VSIM1_CON0 LDO_VSIM1_CON1 LDO_VSIM1_MON LDO_VSIM1_OP_EN LDO_VSIM1_OP_EN_SET LDO_VSIM1_OP_EN_CLR LDO_VSIM1_OP_CFG LDO_VSIM1_OP_CFG_SET LDO_VSIM1_OP_CFG_CLR LDO_VSIM2_CON0 LDO_VSIM2_CON1 LDO_VSIM2_MON LDO_VSIM2_OP_EN LDO_VSIM2_OP_EN_SET LDO_VSIM2_OP_EN_CLR LDO_VSIM2_OP_CFG LDO_VSIM2_OP_CFG_SET LDO_VSIM2_OP_CFG_CLR LDO_GNR3_DSN_ID LDO_GNR3_DSN_REV0 LDO_GNR3_DSN_DBI LDO_GNR3_DSN_DXI LDO_VUSB_CON0 LDO_VUSB_CON1 LDO_VUSB_MON LDO_VUSB_OP_EN LDO_VUSB_OP_EN_SET LDO_VUSB_OP_EN_CLR LDO_VUSB_OP_CFG LDO_VUSB_OP_CFG_SET LDO_VUSB_OP_CFG_CLR LDO_VUSB_MULTI_SW LDO_VRFCK_CON0 LDO_VRFCK_CON1 LDO_VRFCK_MON LDO_VRFCK_OP_EN

Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

LDO_VRFCK_OP_CFG LDO_VRFCK_OP_CFG_SET LDO_VRFCK_OP_CFG_CLR LDO_VBBCK_CON0

16 16 16 16

MediaTek Proprietary and Confidential.

Register Function LDO VIO18 Operation Config SET LDO VIO18 Operation Config CLR LDO VEMC Control 0 LDO VEMC Control 1 LDO VEMC Monitor LDO VEMC Operation Enable LDO VEMC Operation Enable SET LDO VEMC Operation Enable CLR LDO VEMC Operation Config LDO VEMC Operation Config SET LDO VEMC Operation Config CLR LDO VSIM1 Control 0 LDO VSIM1 Control 1 LDO VSIM1 Monitor LDO VSIM1 Operation Enable LDO VSIM1 Operation Enable SET LDO VSIM1 Operation Enable CLR LDO VSIM1 Operation Config LDO VSIM1 Operation Config SET LDO VSIM1 Operation Config CLR LDO VSIM2 Control 0 LDO VSIM2 Control 1 LDO VSIM2 Monitor LDO VSIM2 Operation Enable LDO VSIM2 Operation Enable SET LDO VSIM2 Operation Enable CLR LDO VSIM2 Operation Config LDO VSIM2 Operation Config SET LDO VSIM2 Operation Config CLR LDO_GNR3 Design ID register LDO_GNR3 Design Revision Register 0 LDO_GNR3 Design Bank Information Register LDO_GNR3 Design Extra Information Register LDO VUSB Control 0 LDO VUSB Control 1 LDO VUSB Monitor LDO VUSB Operation Enable LDO VUSB Operation Enable SET LDO VUSB Operation Enable CLR LDO VUSB Operation Config LDO VUSB Operation Config SET LDO VUSB Operation Config CLR LDO VUSB Multi-SW User LDO VRFCK Control 0 LDO VRFCK Control 1 LDO VRFCK Monitor LDO VRFCK Operation Enable

LDO VRFCK Operation Config LDO VRFCK Operation Config SET LDO VRFCK Operation Config CLR LDO VBBCK Control 0

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Page 329 of 1067

MT6359 PMIC Datasheet Confidential A

Address 00001D30 00001D32 00001D34 00001D36 00001D38 00001D3A 00001D3C 00001D3E 00001D40 00001D42 00001D44 00001D46 00001D48 00001D4A 00001D4C 00001D4E 00001D50 00001D52 00001D54 00001D56 00001D58 00001D5A 00001D5C 00001D5E 00001D60 00001D62 00001D64 00001D66 00001D68 00001D6A 00001D6C 00001D6E 00001D70 00001D72 00001D74 00001D80 00001D82 00001D84 00001D86 00001D88 00001D8A 00001D8C 00001D8E 00001D90 00001D92 00001D94 00001D96 8 Operation Config CLR 00001D98 00001D9A S Control 0 00001D9C 00001D9E 00001DA0 00001DA2

Name LDO_VBBCK_CON1 LDO_VBBCK_MON LDO_VBBCK_OP_EN LDO_VBBCK_OP_EN_SET LDO_VBBCK_OP_EN_CLR LDO_VBBCK_OP_CFG LDO_VBBCK_OP_CFG_SET LDO_VBBCK_OP_CFG_CLR LDO_VBIF28_CON0 LDO_VBIF28_CON1 LDO_VBIF28_MON LDO_VBIF28_OP_EN LDO_VBIF28_OP_EN_SET LDO_VBIF28_OP_EN_CLR LDO_VBIF28_OP_CFG LDO_VBIF28_OP_CFG_SET LDO_VBIF28_OP_CFG_CLR LDO_VIBR_CON0 LDO_VIBR_CON1 LDO_VIBR_MON LDO_VIBR_OP_EN LDO_VIBR_OP_EN_SET LDO_VIBR_OP_EN_CLR LDO_VIBR_OP_CFG LDO_VIBR_OP_CFG_SET LDO_VIBR_OP_CFG_CLR LDO_VIO28_CON0 LDO_VIO28_CON1 LDO_VIO28_MON LDO_VIO28_OP_EN LDO_VIO28_OP_EN_SET LDO_VIO28_OP_EN_CLR LDO_VIO28_OP_CFG LDO_VIO28_OP_CFG_SET LDO_VIO28_OP_CFG_CLR LDO_GNR4_DSN_ID LDO_GNR4_DSN_REV0 LDO_GNR4_DSN_DBI LDO_GNR4_DSN_DXI LDO_VM18_CON0 LDO_VM18_CON1 LDO_VM18_MON LDO_VM18_OP_EN LDO_VM18_OP_EN_SET LDO_VM18_OP_EN_CLR LDO_VM18_OP_CFG LDO_VM18_OP_CFG_SET

LDO_VUFS_CON1 LDO_VUFS_MON LDO_VUFS_OP_EN LDO_VUFS_OP_EN_SET

MediaTek Proprietary and Confidential.

Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

16 16 16 16

Register Function LDO VBBCK Control 1 LDO VBBCK Monitor LDO VBBCK Operation Enable LDO VBBCK Operation Enable SET LDO VBBCK Operation Enable CLR LDO VBBCK Operation Config LDO VBBCK Operation Config SET LDO VBBCK Operation Config CLR LDO VBIF28 Control 0 LDO VBIF28 Control 1 LDO VBIF28 Monitor LDO VBIF28 Operation Enable LDO VBIF28 Operation Enable SET LDO VBIF28 Operation Enable CLR LDO VBIF28 Operation Config LDO VBIF28 Operation Config SET LDO VBIF28 Operation Config CLR LDO VIBR Control 0 LDO VIBR Control 1 LDO VIBR Monitor LDO VIBR Operation Enable LDO VIBR Operation Enable SET LDO VIBR Operation Enable CLR LDO VIBR Operation Config LDO VIBR Operation Config SET LDO VIBR Operation Config CLR LDO VIO28 Control 0 LDO VIO28 Control 1 LDO VIO28 Monitor LDO VIO28 Operation Enable LDO VIO28 Operation Enable SET LDO VIO28 Operation Enable CLR LDO VIO28 Operation Config LDO VIO28 Operation Config SET LDO VIO28 Operation Config CLR LDO_GNR4 Design ID register LDO_GNR4 Design Revision Register 0 LDO_GNR4 Design Bank Information Register LDO_GNR4 Design Extra Information Register LDO VM18 Control 0 LDO VM18 Control 1 LDO VM18 Monitor LDO VM18 Operation Enable LDO VM18 Operation Enable SET LDO VM18 Operation Enable CLR LDO VM18 Operation Config LDO VM18 Operation Config SET

LDO VUFS Control 1 LDO VUFS Monitor LDO VUFS Operation Enable LDO VUFS Operation Enable SET

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 330 of 1067

MT6359 PMIC Datasheet Confidential A Address 00001DA4 00001DA6 00001DA8 00001DAA 00001E00 00001E02 00001E04 00001E06 00001E80 00001E82 00001E84 00001E86 00001E88 00001E8A 00001E8C 00001E8E 00001E90 00001E92 00001E94 00001E96 00001E98 00001E9A 00001E9C 00001E9E 00001EA0 00001EA2 00001EA4 00001EA6 00001EA8 00001EAA 00001EAC 00001EAE 00001EB0 00001EB2 00001EB4 00001EB6 00001EB8 00001EBA 00001EBC

Name LDO_VUFS_OP_EN_CLR LDO_VUFS_OP_CFG LDO_VUFS_OP_CFG_SET LDO_VUFS_OP_CFG_CLR LDO_GNR5_DSN_ID LDO_GNR5_DSN_REV0 LDO_GNR5_DSN_DBI LDO_GNR5_DSN_DXI LDO_VSRAM0_DSN_ID LDO_VSRAM0_DSN_REV0 LDO_VSRAM0_DSN_DBI LDO_VSRAM0_DSN_DXI LDO_VSRAM_PROC1_CON0 LDO_VSRAM_PROC1_CON1 LDO_VSRAM_PROC1_MON LDO_VSRAM_PROC1_VOSEL 0 LDO_VSRAM_PROC1_VOSEL 1 LDO_VSRAM_PROC1_SFCHG LDO_VSRAM_PROC1_DVS LDO_VSRAM_PROC1_OP_EN LDO_VSRAM_PROC1_OP_EN _SET LDO_VSRAM_PROC1_OP_EN _CLR LDO_VSRAM_PROC1_OP_CF G LDO_VSRAM_PROC1_OP_CF G_SET LDO_VSRAM_PROC1_OP_CF G_CLR LDO_VSRAM_PROC1_TRACK 0 LDO_VSRAM_PROC1_TRACK 1 LDO_VSRAM_PROC1_TRACK 2 LDO_VSRAM_PROC2_CON0 LDO_VSRAM_PROC2_CON1 LDO_VSRAM_PROC2_MON LDO_VSRAM_PROC2_VOSEL 0 LDO_VSRAM_PROC2_VOSEL 1 LDO_VSRAM_PROC2_SFCHG LDO_VSRAM_PROC2_DVS LDO_VSRAM_PROC2_OP_EN LDO_VSRAM_PROC2_OP_EN _SET LDO_VSRAM_PROC2_OP_EN _CLR LDO_VSRAM_PROC2_OP_CF G

MediaTek Proprietary and Confidential.

Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

Register Function LDO VUFS Operation Enable CLR LDO VUFS Operation Config LDO VUFS Operation Config SET LDO VUFS Operation Config CLR LDO_GNR5 Design ID register LDO_GNR5 Design Revision Register 0 LDO_GNR5 Design Bank Information Register LDO_GNR5 Design Extra Information Register LDO_VSRAM0 Design ID Register LDO_VSRAM0 Design Revision Register 0 LDO_VSRAM0 Design Bank Information Register LDO_VSRAM0 Design Extra Information Register LDO VSRAM_PROC1 Control 0 LDO VSRAM_PROC1 Control 1 LDO VSRAM_PROC1 Monitor

16

LDO VSRAM_PROC1 VOSEL 0

16

LDO VSRAM_PROC1 VOSEL 1

16 16 16

LDO VSRAM_PROC1 Soft Change LDO VSRAM_PROC1 DVS LDO VSRAM_PROC1 Operation Enable

16

LDO VSRAM_PROC1 Operation Enable SET

16

LDO VSRAM_PROC1 Operation Enable CLR

16

LDO VSRAM_PROC1 Operation Config

16

LDO VSRAM_PROC1 Operation Config SET

16

LDO VSRAM_PROC1 Operation Config CLR

16

LDO VSRAM_PROC1 HW Tracking 0

16

LDO VSRAM_PROC1 HW Tracking 1

16

LDO VSRAM_PROC1 HW Tracking 2

16 16 16

LDO VSRAM_PROC2 Control 0 LDO VSRAM_PROC2 Control 1 LDO VSRAM_PROC2 Monitor

16

LDO VSRAM_PROC2 VOSEL 0

16

LDO VSRAM_PROC2 VOSEL 1

16 16 16

LDO VSRAM_PROC2 Soft Change LDO VSRAM_PROC2 DVS LDO VSRAM_PROC2 Operation Enable

16

LDO VSRAM_PROC2 Operation Enable SET

16

LDO VSRAM_PROC2 Operation Enable CLR

16

LDO VSRAM_PROC2 Operation Config

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 331 of 1067

AM_MD VOSEL 0

MT6359 PMIC Datasheet Confidential A Address 00001EBE 00001EC0 00001EC2 00001EC4 00001EC6 00001F00 00001F02 00001F04 00001F06 00001F08 00001F0A 00001F0C 00001F0E 00001F10 00001F12 00001F14 00001F16 00001F18 00001F1A 00001F1C 00001F1E 00001F20 00001F22 00001F24 00001F26 00001F28 00001F2A 00001F2C 00001F2E 00001F30 00001F32 00001F34 00001F36 00001F38 00001F3A 00001F3C

Name LDO_VSRAM_PROC2_OP_CF G_SET LDO_VSRAM_PROC2_OP_CF G_CLR LDO_VSRAM_PROC2_TRACK 0 LDO_VSRAM_PROC2_TRACK 1 LDO_VSRAM_PROC2_TRACK 2 LDO_VSRAM1_DSN_ID LDO_VSRAM1_DSN_REV0 LDO_VSRAM1_DSN_DBI LDO_VSRAM1_DSN_DXI LDO_VSRAM_OTHERS_CON0 LDO_VSRAM_OTHERS_CON1 LDO_VSRAM_OTHERS_MON LDO_VSRAM_OTHERS_VOSE L0 LDO_VSRAM_OTHERS_VOSE L1 LDO_VSRAM_OTHERS_SFCH G LDO_VSRAM_OTHERS_DVS LDO_VSRAM_OTHERS_OP_E N LDO_VSRAM_OTHERS_OP_E N_SET LDO_VSRAM_OTHERS_OP_E N_CLR LDO_VSRAM_OTHERS_OP_C FG LDO_VSRAM_OTHERS_OP_C FG_SET LDO_VSRAM_OTHERS_OP_C FG_CLR LDO_VSRAM_OTHERS_TRAC K0 LDO_VSRAM_OTHERS_TRAC K1 LDO_VSRAM_OTHERS_TRAC K2 LDO_VSRAM_OTHERS_SSHU B LDO_VSRAM_OTHERS_BT LDO_VSRAM_OTHERS_SPI LDO_VSRAM_MD_CON0 LDO_VSRAM_MD_CON1 LDO_VSRAM_MD_MON LDO_VSRAM_MD_VOSEL1 LDO_VSRAM_MD_SFCHG LDO_VSRAM_MD_DVS LDO_VSRAM_MD_OP_EN

MediaTek Proprietary and Confidential.

Width

Register Function

16

LDO VSRAM_PROC2 Operation Config SET

16

LDO VSRAM_PROC2 Operation Config CLR

16

LDO VSRAM_PROC2 HW Tracking 0

16

LDO VSRAM_PROC2 HW Tracking 1

16

LDO VSRAM_PROC2 HW Tracking 2

16 16 16 16 16 16 16

LDO_VSRAM1 Design ID Register LDO_VSRAM1 Design Revision Register 0 LDO_VSRAM1 Design Bank Information Register LDO_VSRAM1 Design Extra Information Register LDO VSRAM_OTHERS Control 0 LDO VSRAM_OTHERS Control 1 LDO VSRAM_OTHERS Monitor

16

LDO VSRAM_OTHERS VOSEL 0

16

LDO VSRAM_OTHERS VOSEL 1

16

LDO VSRAM_OTHERS Soft Change

16

LDO VSRAM_OTHERS DVS

16

LDO VSRAM_OTHERS Operation Enable

16

LDO VSRAM_OTHERS Operation Enable SET

16

LDO VSRAM_OTHERS Operation Enable CLR

16

LDO VSRAM_OTHERS Operation Config

16

LDO VSRAM_OTHERS Operation Config SET

16

LDO VSRAM_OTHERS Operation Config CLR

16

LDO VSRAM_OTHERS HW Tracking 0

16

LDO VSRAM_OTHERS HW Tracking 1

16

LDO VSRAM_OTHERS HW Tracking 2

16

LDO VSRAM_OTHERS Sensor Hub 0

16 16 16 16 16

LDO VSRAM_OTHERS BT 0 LDO VSRAM_OTHERS SPI 0 LDO VSRAM_MD Control 0 LDO VSRAM_MD Control 1 LDO VSRAM_MD Monitor

16 16 16 16

LDO VSRAM_MD VOSEL 1 LDO VSRAM_MD Soft Change LDO VSRAM_MD DVS LDO VSRAM_MD Operation Enable

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 332 of 1067

MT6359 PMIC Datasheet Confidential A Address 00001F3E 00001F40 00001F42 00001F44 00001F46

00001F48 00001F4A 00001F4C 00001F80 00001F82 00001F84 00001F86 00001F88 00001F8A 00001F8C 00001F8E 00001F90 00001F92 00001F94 00001F96 00001F98 00001F9A 00001F9C 00001F9E 00001FA0 00001FA2 00001FA4 00001FA6 00001FA8 00001FAA 00001FAC 00001FAE 00001FB0 00001FB2 00001FB4 00001FB6 00001FB8 00001FBA 00001FBC 00001FBE 00001FC0 00002000 00002002 00002004 A1 Design Extra Information Register 00002006 00002008 0000200A 0000200C 0000200E 00002010

Name LDO_VSRAM_MD_OP_EN_SE T LDO_VSRAM_MD_OP_EN_CL R LDO_VSRAM_MD_OP_CFG LDO_VSRAM_MD_OP_CFG_S ET LDO_VSRAM_MD_OP_CFG_C LR LDO_VSRAM_MD_TRACK0 LDO_VSRAM_MD_TRACK1 LDO_VSRAM_MD_TRACK2 LDO_ANA0_DSN_ID LDO_ANA0_DSN_REV0 LDO_ANA0_DSN_DBI LDO_ANA0_DSN_FPI VFE28_ANA_CON0 VFE28_ANA_CON1 VAUX18_ANA_CON0 VAUX18_ANA_CON1 VUSB_ANA_CON0 VUSB_ANA_CON1 VBIF28_ANA_CON0 VBIF28_ANA_CON1 VCN33_1_ANA_CON0 VCN33_1_ANA_CON1 VCN33_2_ANA_CON0 VCN33_2_ANA_CON1 VEMC_ANA_CON0 VSIM1_ANA_CON0 VSIM1_ANA_CON1 VSIM2_ANA_CON0 VSIM2_ANA_CON1 VIO28_ANA_CON0 VIO28_ANA_CON1 VIBR_ANA_CON0 VIBR_ANA_CON1 ADLDO_ANA_CON0 VA12_ANA_CON0 LDO_ANA0_ELR_NUM VFE28_ELR_0 VFE28_ELR_1 VFE28_ELR_2 VFE28_ELR_3 VFE28_ELR_4 LDO_ANA1_DSN_ID LDO_ANA1_DSN_REV0 LDO_ANA1_DSN_DBI VRF18_ANA_CON0 VRF18_ANA_CON1 VEFUSE_ANA_CON0 VEFUSE_ANA_CON1 VCN18_ANA_CON0

MediaTek Proprietary and Confidential.

Width

Register Function

16

LDO VSRAM_MD Operation Enable SET

16

LDO VSRAM_MD Operation Enable CLR

16

LDO VSRAM_MD Operation Config

16

LDO VSRAM_MD Operation Config SET

16

LDO VSRAM_MD Operation Config CLR

16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

LDO VSRAM_MD HW Tracking 0 LDO VSRAM_MD HW Tracking 1 LDO VSRAM_MD HW Tracking 2 LDO_ANA0 Design ID register LDO_ANA0 Design Revision Register 0 LDO_ANA0 Design Bank Information Register LDO_ANA0 Design Extra Information Register VFE28 Control Register 0 VFE28 Control Register 1 VAUX18 Control Register 0 VAUX18 Control Register 1 VUSB Control Register 0 VUSB Control Register 1 VBIF28 Control Register 0 VBIF28 Control Register 1 VCN33_1 Control Register 0 VCN33_1 Control Register 1 VCN33_2 Control Register 0 VCN33_2 Control Register 1 VEMC Control Register 0 VSIM1 Control Register 0 VSIM1 Control Register 1 VSIM2 Control Register 0 VSIM2 Control Register 1 VIO28 Control Register 0 VIO28 Control Register 1 VIBR Control Register 0 VIBR Control Register 1 ADLDO Control Register 0 VA12 Control Register 0 LDO_ANA0 Number of ELR Register VFE28 ELR 0 Register VFE28 ELR 1 Register VFE28 ELR 2 Register VFE28 ELR 3 Register VFE28 ELR 4 Register LDO_ANA1 Design ID Register LDO_ANA1 Design Revision Register 0 LDO_ANA1 Design Bank Information Register

16 16 16 16 16

VRF18 Control Register 0 VRF18 Control Register 1 VEFUSE Control Register 0 VEFUSE Control Register 1 VCN18 Control Register 0

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 333 of 1067

MT6359 PMIC Datasheet Confidential A

Address 00002012 00002014 00002016 00002018 0000201A 0000201C 0000201E 00002020 00002022 00002024 00002026 00002028 0000202A 0000202C 0000202E 00002030 00002032 00002034 00002036 00002038 0000203A 0000203C 0000203E 00002040 00002042 00002044 00002046 00002048 0000204A 0000204C 0000204E 00002080 00002082 00002084 00002086 00002088 0000208A 0000208C 0000208E 00002090 00002092 00002094 00002096 00002098 0000209A 0000209C 0000209E OAD Design ID Register 00002100 00002102 OAD Design Revision Register 0 00002104 00002106 00002108 0000210A

Name VCN18_ANA_CON1 VCAMIO_ANA_CON0 VCAMIO_ANA_CON1 VAUD18_ANA_CON0 VAUD18_ANA_CON1 VIO18_ANA_CON0 VIO18_ANA_CON1 VM18_ANA_CON0 VM18_ANA_CON1 VUFS_ANA_CON0 VUFS_ANA_CON1 SLDO20_ANA_CON0 VRF12_ANA_CON0 VRF12_ANA_CON1 VCN13_ANA_CON0 VCN13_ANA_CON1 VA09_ANA_CON0 VSRAM_PROC1_ANA_CON0 VSRAM_PROC1_ANA_CON1 VSRAM_PROC2_ANA_CON0 VSRAM_PROC2_ANA_CON1 VSRAM_OTHERS_ANA_CON0 VSRAM_OTHERS_ANA_CON1 VSRAM_MD_ANA_CON0 VSRAM_MD_ANA_CON1 SLDO14_ANA_CON0 LDO_ANA1_ELR_NUM VRF18_ELR_0 VRF18_ELR_1 VRF18_ELR_2 VRF18_ELR_3 LDO_ANA2_DSN_ID LDO_ANA2_DSN_REV0 LDO_ANA2_DSN_DBI LDO_ANA2_DSN_FPI VXO22_ANA_CON0 VXO22_ANA_CON1 VRFCK_ANA_CON0 VRFCK_ANA_CON1 VRFCK_ANA_CON2 VRFCK_1_ANA_CON0 VRFCK_1_ANA_CON1 VBBCK_ANA_CON0 VBBCK_ANA_CON1 LDO_ANA2_ELR_NUM DCXO_ADLDO_BIAS_ELR_0 DCXO_ADLDO_BIAS_ELR_1

DUMMYLOAD_DSN_DBI DUMMYLOAD_DSN_FPI DUMMYLOAD_ANA_CON0 ISINK0_CON1

MediaTek Proprietary and Confidential.

Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

16 16 16 16

Register Function VCN18 Control Register 1 VCAMIO Control Register 0 VCAMIO Control Register 1 VAUD18 Control Register 0 VAUD18 Control Register 1 VIO18 Control Register 0 VIO18 Control Register 1 VM18 Control Register 0 VM18 Control Register 1 VUFS Control Register 0 VUFS Control Register 1 SLDO20 Control Register 0 VRF12 Control Register 0 VRF12 Control Register 1 VCN13 Control Register 0 VCN13 Control Register 1 VA09 Control Register 0 VSRAM_PROC1 Control Register 0 VSRAM_PROC1 Control Register 1 VSRAM_PROC2 Control Register 0 VSRAM_PROC2 Control Register 1 VSRAM_OTHERS Control Register 0 VSRAM_OTHERS Control Register 1 VSRAM_MD Control Register 0 VSRAM_MD Control Register 1 SLDO14 Control Register 0 LDO_ANA1 Number of ELR Register VRF18 ELR 0 Register VRF18 ELR 1 Register VRF18 ELR 2 Register VRF18 ELR 3 Register LDO_ANA2 Design ID Register LDO_ANA2 Design Revision Register 0 LDO_ANA2 Design Bank Information Register LDO_ANA2 Design Extra Information Register VXO22 Control Register 0 VXO22 Control Register 1 VRFCK Control Register 0 VRFCK Control Register 1 VRFCK Control Register 2 VRFCK_1 Control Register 0 VRFCK_1 Control Register 1 VBBCK Control Register 0 VBBCK Control Register 1 LDO_ANA2 Number of ELR Register DCXO_ADLDO_BIAS ELR 0 Register DCXO_ADLDO_BIAS ELR 1 Register

DUMMYLOAD Design Bank Information Register DUMMYLOAD Design Extra Information Register DUMMYLOAD Control Register 0 ISINK0 Control Register 1

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 334 of 1067

MT6359 PMIC Datasheet Confidential A Address 0000210C 0000210E 00002110 00002112 00002114 00002300 00002302 00002304 00002306 00002308 0000230A 0000230C 0000230E 00002310 00002312 00002314 00002316 00002318 0000231A 0000231C 0000231E 00002320 00002322 00002324 00002326 00002328 0000232A 0000232C 0000232E 00002330 00002332 00002334 00002336 00002338 0000233A 00002380 00002382 00002384 00002386 00002388 0000238A 0000238C 0000238E 00002390 00002392 00002394

Name ISINK1_CON1 ISINK_ANA1_SMPL ISINK_EN_CTRL_SMPL DUMMYLOAD_ELR_NUM DUMMYLOAD_ELR_0 AUD_TOP_ID AUD_TOP_REV0 AUD_TOP_DBI AUD_TOP_DXI AUD_TOP_CKPDN_TPM0 AUD_TOP_CKPDN_TPM1 AUD_TOP_CKPDN_CON0 AUD_TOP_CKPDN_CON0_SE T AUD_TOP_CKPDN_CON0_CL R AUD_TOP_CKSEL_CON0 AUD_TOP_CKSEL_CON0_SET AUD_TOP_CKSEL_CON0_CLR AUD_TOP_CKTST_CON0 AUD_TOP_CLK_HWEN_CON0 AUD_TOP_CLK_HWEN_CON0 _SET AUD_TOP_CLK_HWEN_CON0 _CLR AUD_TOP_RST_CON0 AUD_TOP_RST_CON0_SET AUD_TOP_RST_CON0_CLR AUD_TOP_RST_BANK_CON0 AUD_TOP_INT_CON0 AUD_TOP_INT_CON0_SET AUD_TOP_INT_CON0_CLR AUD_TOP_INT_MASK_CON0 AUD_TOP_INT_MASK_CON0 _SET AUD_TOP_INT_MASK_CON0 _CLR AUD_TOP_INT_STATUS0 AUD_TOP_INT_RAW_STATU S0 AUD_TOP_INT_MISC_CON0 AUD_TOP_MON_CON0 AUDIO_DIG_DSN_ID AUDIO_DIG_DSN_REV0 AUDIO_DIG_DSN_DBI AUDIO_DIG_DSN_DXI AFE_UL_DL_CON0 AFE_DL_SRC2_CON0_L AFE_UL_SRC_CON0_H AFE_UL_SRC_CON0_L AFE_ADDA6_L_SRC_CON0_H AFE_ADDA6_UL_SRC_CON0_ L AFE_TOP_CON0

MediaTek Proprietary and Confidential.

Width 16 16 16 16 16 16 16 16 16 16 16 16

Register Function ISINK1 Control Register 1 ISINKS ACD Interface 1 SIMPLE ISINK Enable Control Simple DUMMYLOAD Number of ELR Register DUMMYLOAD ELR 0 Register AUD_TOP Design ID Register AUD_TOP Design Revision Register 0 AUD_TOP Design Bank Information Register AUD_TOP Design Extra Information Register AUD_TOP Parameter 0 AUD_TOP Parameter 1 AUDIO CLK Power Down Register 0

16

AUDIO CLK Power Down Register 0 SET

16

AUDIO CLK Power Down Register 0 CLR

16 16 16 16 16

AUDIO CKSEL Control Register 0 AUDIO CKSEL Control Register 0 SET AUDIO CKSEL Control Register 0 CLR AUDIO CKTST Control Register 0 AUD_TOP CLOCK HWEN CON0TROL 0

16

AUD_TOP CLOCK HWEN CON0TROL 0 SET

16

AUD_TOP CLOCK HWEN CON0TROL 0 CLR

16 16 16 16 16 16 16 16

AUDIO RST Control Register 0 AUD RST Control Register 0 SET AUD RST Control Register 0 CLR AUD RST BANK Control Register 0 AUDIO INT Control Register 0 AUD_TOP_INT Control Register 0 SET AUD_TOP_INT Control Register 0 CLR AUDIO INT MASK Control Register 0

16

AUD_TOP_INT Mask Control Register 0 SET

16

AUD_TOP_INT Mask Control Register 0 CLR

16

AUDIO INT STATUS0 Control Register

16

AUD_TOP_INT_RAW_STATUS0 Register

16 16 16 16 16 16 16 16 16 16 16

AUD_TOP_INT_MISC Control Register 0 AUD_TOP_MON Control Register 0 AUD_DIG Design ID Register AUD_DIG Design Revision Register 0 AUD_DIG Design Bank Information Register AUD_DIG Design Extra Information Register Audio UL and DL Control Register 0 AFE_DL_SRC2 Control Register 0 Low Part AFE Uplink SRC Control Register 0 High Part AFE Uplink SRC Control Register 0 Low Part AFE Uplink2 SRC Control Register 0 High Part

16

AFE Uplink2 SRC Control Register 0 Low Part

16

AFE Top Control Register 0

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 335 of 1067

MT6359 PMIC Datasheet Confidential A Address 00002396 00002398 0000239A 0000239C 0000239E 000023A0 000023A2 000023A4 000023A6 000023A8 000023AA 000023AC 000023AE 000023B0 000023B2 000023B4 000023B6 000023B8 000023BA 000023BC 000023BE 000023C0 000023C2 000023C4 000023C6 000023C8 000023CA 000023CC 000023CE 000023D0 000023D2 000023D4 000023D6

000023D8 000023DA 000023DC 000023DE 000023E0 000023E2 000023E4 ADDA NEWIF Top Control000023E6 Register 1 000023E8 000023EA 000023EC 000023EE 000023F0

Name AUDIO_TOP_CON0 AFE_MON_DEBUG0 AFUNC_AUD_CON0 AFUNC_AUD_CON1 AFUNC_AUD_CON2 AFUNC_AUD_CON3 AFUNC_AUD_CON4 AFUNC_AUD_CON5 AFUNC_AUD_CON6 AFUNC_AUD_CON7 AFUNC_AUD_CON8 AFUNC_AUD_CON9 AFUNC_AUD_CON10 AFUNC_AUD_CON11 AFUNC_AUD_CON12 AFUNC_AUD_MON0 AFUNC_AUD_MON1 AUDRC_TUNE_MON0 AFE_ADDA_MTKAIF_FIFO_CF G0 AFE_ADDA_MTKAIF_FIFO_L OG_MON1 AFE_ADDA_MTKAIF_MON0 AFE_ADDA_MTKAIF_MON1 AFE_ADDA_MTKAIF_MON2 AFE_ADDA6_MTKAIF_MON3 AFE_ADDA_MTKAIF_MON4 AFE_ADDA_MTKAIF_MON5 AFE_ADDA_MTKAIF_CFG0 AFE_ADDA_MTKAIF_RX_CFG 0 AFE_ADDA_MTKAIF_RX_CFG 1 AFE_ADDA_MTKAIF_RX_CFG 2 AFE_ADDA_MTKAIF_RX_CFG 3 AFE_ADDA_MTKAIF_SYNCW ORD_CFG0 AFE_ADDA_MTKAIF_SYNCW ORD_CFG1 AFE_SGEN_CFG0 AFE_SGEN_CFG1 AFE_ADC_ASYNC_FIFO_CFG AFE_ADC_ASYNC_FIFO_CFG1 AFE_DCCLK_CFG0 AFE_DCCLK_CFG1 AUDIO_DIG_CFG AFE_AUD_PAD_TOP AFE_AUD_PAD_TOP_MON AFE_AUD_PAD_TOP_MON1 AFE_AUD_PAD_TOP_MON2 AFE_DL_NLE_CFG

MediaTek Proprietary and Confidential.

Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

Register Function Audio Top Control Register 0 AFE Monitor Output Debug Register 0 A_FUNC Audio Control Register 0 A_FUNC Audio Control Register 1 A_FUNC Audio Control Register 2 A_FUNC Audio Control Register 3 A_FUNC Audio Control Register 4 A_FUNC Audio Control Register 5 A_FUNC Audio Control Register 6 A_FUNC Audio Control Register 7 A_FUNC Audio Control Register 8 A_FUNC Audio Control Register 10 A_FUNC Audio Control Register 11 A_FUNC Audio Control Register 12 A_FUNC Audio Control Register 18 A_FUNC Audio Monitor Register 0 A_FUNC Audio Monitor Register 1 Analog Monitor Register 0

16

AFE MTKAIF FIFO Register 0

16

AFE MTKAIF FIFO Monitor 0

16 16 16 16 16 16 16

AFEMTKAIF_V3 Monitor Register 0 AFEMTKAIF_V3 Monitor Register 1 AFEMTKAIF_V3 Monitor Register 2 AFEMTKAIF_V3 Monitor Register 3 AFEMTKAIF_V3 Monitor Register 4 AFEMTKAIF_V3 Monitor Register 5 AFE MTKAIF_V3 Control Register 0

16

AFEMTKAIF_V3 RXIF Protocol 1 Control Register 0

16

AFEMTKAIF_V3 RXIF Protocol 2 Control Register 0

16

AFEMTKAIF_V3 RXIF Protocol 2 Control Register 2

16

AFEMTKAIF_V3 RXIF Protocol 2 Control Register 3

16 16 16 16 16 16 16

AFEMTKAIF_V3 Protocol 2 Syncword Control Register0 AFEMTKAIF_V3 Protocol 2 Syncword Control Register1 AFE SGEN CON0 AFE SGEN CON1 AFE_ADC_SYNC_FIFO_CFG AFE_ADC_SYNC_FIFO_CFG1 AFE_DCCLK_CFG0 AFE_DCCLK_CFG1 AFE MTK ADDA NEWIF Top Control Register 0

16 16 16 16 16

AFE MTK ADDA NEWIF Top Control Register 2 AFE MTK ADDA NEWIF Top Monitor Register 0 AFE MTK ADDA NEWIF Top Monitor Register 1 AFE MTK ADDA NEWIF Top Monitor Register 2 AFE NLE Control Register

16 16

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 336 of 1067

MT6359 PMIC Datasheet Confidential A Address 000023F2 000023F4 000023F6 000023F8 000023FA 00002400 00002402 00002404 00002406 00002408 0000240A 0000240C 0000240E

Name AFE_DL_NLE_MON AFE_CG_EN_MON AFE_MIC_ARRAY_CFG AFE_CHOP_CFG0 AFE_MTKAIF_MUX_CFG AUDIO_DIG_2ND_DSN_ID AUDIO_DIG_2ND_DSN_REV0 AUDIO_DIG_2ND_DSN_DBI AUDIO_DIG_2ND_DSN_DXI AFE_PMIC_NEWIF_CFG3 AFE_VOW_TOP_CON0 AFE_VOW_TOP_CON1 AFE_VOW_TOP_CON2

00002410

AFE_VOW_TOP_CON3

16

AFE_VOW_TOP_CON4 AFE_VOW_TOP_MON0 AFE_VOW_VAD_CFG0 AFE_VOW_VAD_CFG1 AFE_VOW_VAD_CFG2 AFE_VOW_VAD_CFG3 AFE_VOW_VAD_CFG4 AFE_VOW_VAD_CFG5 AFE_VOW_VAD_CFG6 AFE_VOW_VAD_CFG7 AFE_VOW_VAD_CFG8 AFE_VOW_VAD_CFG9 AFE_VOW_VAD_CFG10 AFE_VOW_VAD_CFG11 AFE_VOW_VAD_CFG12 AFE_VOW_VAD_MON0 AFE_VOW_VAD_MON1 AFE_VOW_VAD_MON2 AFE_VOW_VAD_MON3 AFE_VOW_VAD_MON4 AFE_VOW_VAD_MON5 AFE_VOW_VAD_MON6 AFE_VOW_VAD_MON7 AFE_VOW_VAD_MON8 AFE_VOW_VAD_MON9 AFE_VOW_VAD_MON10 AFE_VOW_VAD_MON11 AFE_VOW_TGEN_CFG0 AFE_VOW_TGEN_CFG1 AFE_VOW_HPF_CFG0 AFE_VOW_HPF_CFG1 AUDIO_DIG_3RD_DSN_ID

16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

Register Function AFE_DL_NLE_MON AFE_CG_EN_MON Mic Array Control Register AFE_CHOP_CFG0 AFE_MTKAIF_MUX_CFG AUD_DIG_2ND Design ID Register AUD_DIG_2ND Design Revision Register 0 AUD_DIG_2ND Design Bank Information Register AUD_DIG_2ND Design Extra Information Register AFE MTK ADDA NEWIF Control Register 3 AFE VOW Top Control for Dual Channels AFE VOW Top Control for Left Channel AFE VOW Top Control for Right Channel AFE VOW Top Control for Test Clock and MTKAIF Settings AFE VOW AMIC Array AFE VOW Top Monitor Out AFE VOW VAD Configuration 0 AFE VOW VAD Configuration 1 AFE VOW VAD Configuration 2 AFE VOW VAD Configuration 3 AFE VOW VAD Configuration 4 AFE VOW VAD Configuration 5 AFE VOW VAD Configuration 6 AFE VOW VAD Configuration 7 AFE VOW VAD Configuration 8 AFE VOW VAD Configuration 9 AFE VOW VAD Configuration 10 AFE VOW VAD Configuration 11 AFE VOW VAD Configuration 12 AFE VOW VAD Monitor 0 AFE VOW VAD Monitor 1 AFE VOW VAD Monitor 2 AFE VOW VAD Monitor 3 AFE VOW VAD Monitor 4 AFE VOW VAD Monitor 5 AFE VOW VAD Monitor 6 AFE VOW VAD Monitor 7 AFE VOW VAD Monitor 8 AFE VOW VAD Monitor 9 AFE VOW VAD Monitor 10 AFE VOW VAD Monitor 11 AFE VOW Trigen Configuration 0 AFE VOW Trigen Configuration 1 AFE VOW HPF Configuration 0 AFE VOW HPF Configuration 1 AUD_DIG_3RD Design ID Register

AUDIO_DIG_3RD_DSN_DXI AFE_VOW_PERIODIC_CFG0 AFE_VOW_PERIODIC_CFG1 AFE_VOW_PERIODIC_CFG2 AFE_VOW_PERIODIC_CFG3

16 16 16 16 16

AUD_DIG_3RD Design Extra Information Register AFE Vow Periodic Configuration 0 AFE Vow Periodic Configuration 1 AFE Vow Periodic Configuration 2 AFE Vow Periodic Configuration 3

00002412 00002414 00002416 00002418 0000241A 0000241C 0000241E 00002420 00002422 00002424 00002426 00002428 0000242A 0000242C 0000242E 00002430 00002432 00002434 00002436 00002438 0000243A 0000243C 0000243E 00002440 00002442 00002444 00002446 00002448 0000244A 0000244C 0000244E 00002480 _3RD Design Revision Register 0 00002482 _3RD Design Bank Information Register 00002484 00002486 00002488 0000248A 0000248C 0000248E

MediaTek Proprietary and Confidential.

Width 16 16 16 16 16 16 16 16 16 16 16 16 16

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 337 of 1067

Control Register 1 Control Register 2

MT6359 PMIC Datasheet Confidential A Address 00002490 00002492 00002494 00002496 00002498 0000249A 0000249C 0000249E 000024A0 000024A2 000024A4 000024A6 000024A8 000024AA 000024AC 000024AE 000024B0 000024B2 000024B4 000024B6 000024B8 000024BA 000024BC 000024BE 000024C0 000024C2 000024C4 000024C6 000024C8 000024CA 000024CC 000024CE 000024D0 000024D2 000024D4 000024D6 000024D8 000024DA 000024DC 000024DE 000024E0 000024E2 00002500 00002502 00002504 00002506 00002508 0000250A 0000250C 0000250E 00002510 00002512 00002514

Name AFE_VOW_PERIODIC_CFG4 AFE_VOW_PERIODIC_CFG5 AFE_VOW_PERIODIC_CFG6 AFE_VOW_PERIODIC_CFG7 AFE_VOW_PERIODIC_CFG8 AFE_VOW_PERIODIC_CFG9 AFE_VOW_PERIODIC_CFG10 AFE_VOW_PERIODIC_CFG11 AFE_VOW_PERIODIC_CFG12 AFE_VOW_PERIODIC_CFG13 AFE_VOW_PERIODIC_CFG14 AFE_VOW_PERIODIC_CFG15 AFE_VOW_PERIODIC_CFG16 AFE_VOW_PERIODIC_CFG17 AFE_VOW_PERIODIC_CFG18 AFE_VOW_PERIODIC_CFG19 AFE_VOW_PERIODIC_CFG20 AFE_VOW_PERIODIC_CFG21 AFE_VOW_PERIODIC_CFG22 AFE_VOW_PERIODIC_CFG23 AFE_VOW_PERIODIC_CFG24 AFE_VOW_PERIODIC_CFG25 AFE_VOW_PERIODIC_CFG26 AFE_VOW_PERIODIC_CFG27 AFE_VOW_PERIODIC_CFG28 AFE_VOW_PERIODIC_CFG29 AFE_VOW_PERIODIC_CFG30 AFE_VOW_PERIODIC_CFG31 AFE_VOW_PERIODIC_CFG32 AFE_VOW_PERIODIC_CFG33 AFE_VOW_PERIODIC_CFG34 AFE_VOW_PERIODIC_CFG35 AFE_VOW_PERIODIC_CFG36 AFE_VOW_PERIODIC_CFG37 AFE_VOW_PERIODIC_CFG38 AFE_VOW_PERIODIC_CFG39 AFE_VOW_PERIODIC_MON0 AFE_VOW_PERIODIC_MON1 AFE_VOW_PERIODIC_MON2 AFE_NCP_CFG0 AFE_NCP_CFG1 AFE_NCP_CFG2 AUDENC_DSN_ID AUDENC_DSN_REV0 AUDENC_DSN_DBI AUDENC_DSN_FPI AUDENC_ANA_CON0

AUDENC_ANA_CON3 AUDENC_ANA_CON4 AUDENC_ANA_CON5 AUDENC_ANA_CON6

MediaTek Proprietary and Confidential.

Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

16 16 16 16

Register Function AFE Vow Periodic Configuration 4 AFE Vow Periodic Configuration 5 AFE Vow Periodic Configuration 6 AFE Vow Periodic Configuration 7 AFE Vow Periodic Configuration 8 AFE Vow Periodic Configuration 9 AFE Vow Periodic Configuration 10 AFE Vow Periodic Configuration 11 AFE Vow Periodic Configuration 12 AFE Vow Periodic Configuration 13 AFE Vow Periodic Configuration 14 AFE Vow Periodic Configuration 15 AFE Vow Periodic Configuration 16 AFE Vow Periodic Configuration 17 AFE Vow Periodic Configuration 18 AFE Vow Periodic Configuration 19 AFE Vow Periodic Configuration 20 AFE Vow Periodic Configuration 21 AFE Vow Periodic Configuration 22 AFE Vow Periodic Configuration 23 AFE Vow Periodic Configuration 24 AFE Vow Periodic Configuration 25 AFE Vow Periodic Configuration 26 AFE Vow Periodic Configuration 27 AFE Vow Periodic Configuration 28 AFE Vow Periodic Configuration 29 AFE Vow Periodic Configuration 30 AFE Vow Periodic Configuration 31 AFE Vow Periodic Configuration 32 AFE Vow Periodic Configuration 33 AFE Vow Periodic Configuration 34 AFE Vow Periodic Configuration 35 AFE Vow Periodic Configuration 36 AFE Vow Periodic Configuration 37 AFE Vow Periodic Configuration 38 AFE Vow Periodic Configuration 39 AFE Vow Periodic Monitor 0 AFE Vow Periodic Monitor 1 AFE Vow Periodic Monitor 2 AFE_NCP_CFG0 AFE_NCP_CFG1 AFE_NCP_CFG2 AUDENC Design ID Register AUDENC Design Revision Register 0 AUDENC Design Bank Information Register AUDENC Design Extra Information Register AUDENC Control Register 0

AUDENC Control Register 3 AUDENC Control Register 4 AUDENC Control Register 5 AUDENC Control Register 6

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 338 of 1067

MT6359 PMIC Datasheet Confidential A

Address 00002516 00002518 0000251A 0000251C 0000251E 00002520 00002522 00002524 00002526 00002528 0000252A 0000252C 0000252E 00002530 00002532 00002534 00002536 00002580 00002582 00002584 00002586 00002588 0000258A 0000258C 0000258E 00002590 00002592 00002594 00002596 00002598 0000259A 0000259C 0000259E 000025A0 000025A2 000025A4 00002600 00002602 00002604 00002606 00002608 0000260A 0000260C 0000260E 00002610 00002612 00002680 Design Revision Register 000002682 00002684 Design Bank Information Register 00002686 00002688 0000268A 0000268C

Name AUDENC_ANA_CON7 AUDENC_ANA_CON8 AUDENC_ANA_CON9 AUDENC_ANA_CON10 AUDENC_ANA_CON11 AUDENC_ANA_CON12 AUDENC_ANA_CON13 AUDENC_ANA_CON14 AUDENC_ANA_CON15 AUDENC_ANA_CON16 AUDENC_ANA_CON17 AUDENC_ANA_CON18 AUDENC_ANA_CON19 AUDENC_ANA_CON20 AUDENC_ANA_CON21 AUDENC_ANA_CON22 AUDENC_ANA_CON23 AUDDEC_DSN_ID AUDDEC_DSN_REV0 AUDDEC_DSN_DBI AUDDEC_DSN_FPI AUDDEC_ANA_CON0 AUDDEC_ANA_CON1 AUDDEC_ANA_CON2 AUDDEC_ANA_CON3 AUDDEC_ANA_CON4 AUDDEC_ANA_CON5 AUDDEC_ANA_CON6 AUDDEC_ANA_CON7 AUDDEC_ANA_CON8 AUDDEC_ANA_CON9 AUDDEC_ANA_CON10 AUDDEC_ANA_CON11 AUDDEC_ANA_CON12 AUDDEC_ANA_CON13 AUDDEC_ANA_CON14 AUDZCD_DSN_ID AUDZCD_DSN_REV0 AUDZCD_DSN_DBI AUDZCD_DSN_FPI ZCD_CON0 ZCD_CON1 ZCD_CON2 ZCD_CON3 ZCD_CON4 ZCD_CON5 ACCDET_DSN_DIG_ID

ACCDET_DSN_FPI ACCDET_CON0 ACCDET_CON1 ACCDET_CON2

MediaTek Proprietary and Confidential.

Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

Register Function AUDENC Control Register 7 AUDENC Control Register 8 AUDENC Control Register 9 AUDENC Control Register 10 AUDENC Control Register 11 AUDENC Control Register 12 AUDENC Control Register 13 AUDENC Control Register 14 AUDENC Control Register 15 AUDENC Control Register 16 AUDENC Control Register 17 AUDENC Control Register 18 AUDENC Control Register 19 AUDENC Control Register 20 AUDENC Control Register 21 AUDENC Control Register 22 AUDENC Control Register 23 AUDDEC Design ID Register AUDDEC Design Revision Register 0 AUDDEC Design Bank Information Register AUDDEC Design Extra Information Register AUDDEC Control Register 0 AUDDEC Control Register 1 AUDDEC Control Register 2 AUDDEC Control Register 3 AUDDEC Control Register 4 AUDDEC Control Register 5 AUDDEC Control Register 6 AUDDEC Control Register 7 AUDDEC Control Register 8 AUDDEC Control Register 9 AUDDEC Control Register 10 AUDDEC Control Register 11 AUDDEC Control Register 12 AUDDEC Control Register 13 AUDDEC Control Register 14 AUDZCD Design ID Register AUDZCD Design Revision Register 0 AUDZCD Design Bank Information Register AUDZCD Design Extra Information Register ZCD Control Register 0 ZCD Control Register 1 ZCD Control Register 2 ZCD Control Register 3 ZCD Control Register 4 ZCD Control Register 5 ACCDET Design ID Register

16 16 16 16

ACCDET Design Extra Information Register ACCDET Control Register 0 ACCDET Control Register 1 ACCDET Control Register 2

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 339 of 1067

MT6359 PMIC Datasheet Confidential A Address 0000268E 00002690 00002692 00002694 00002696 00002698 0000269A 0000269C 0000269E 000026A0 000026A2 000026A4 000026A6 000026A8 000026AA 000026AC 000026AE 000026B0 000026B2 000026B4 000026B6 000026B8 000026BA 000026BC 000026BE 000026C0 000026C2 000026C4 000026C6 000026C8 000026CA 000026CC 000026CE 000026D0 000026D2 000026D4 000026D6 000026D8

Name ACCDET_CON3 ACCDET_CON4 ACCDET_CON5 ACCDET_CON6 ACCDET_CON7 ACCDET_CON8 ACCDET_CON9 ACCDET_CON10 ACCDET_CON11 ACCDET_CON12 ACCDET_CON13 ACCDET_CON14 ACCDET_CON15 ACCDET_CON16 ACCDET_CON17 ACCDET_CON18 ACCDET_CON19 ACCDET_CON20 ACCDET_CON21 ACCDET_CON22 ACCDET_CON23 ACCDET_CON24 ACCDET_CON25 ACCDET_CON26 ACCDET_CON27 ACCDET_CON28 ACCDET_CON29 ACCDET_CON30 ACCDET_CON31 ACCDET_CON32 ACCDET_CON33 ACCDET_CON34 ACCDET_CON35 ACCDET_CON36 ACCDET_CON37 ACCDET_CON38 ACCDET_CON39 ACCDET_CON40

MediaTek Proprietary and Confidential.

Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

Register Function ACCDET Control Register 3 ACCDET Control Register 4 ACCDET Control Register 5 ACCDET Control Register 6 ACCDET Control Register 7 ACCDET Control Register 8 ACCDET Control Register 9 ACCDET Control Register 10 ACCDET Control Register 11 ACCDET Control Register 12 ACCDET Control Register 13 ACCDET Control Register 14 ACCDET Control Register 15 ACCDET Control Register 16 ACCDET Control Register 17 ACCDET Control Register 18 ACCDET Control Register 19 ACCDET Control Register 20 ACCDET Control Register 21 ACCDET Control Register 22 ACCDET Control Register 23 ACCDET Control Register 24 ACCDET Control Register 25 ACCDET Control Register 26 ACCDET Control Register 27 ACCDET Control Register 28 ACCDET Control Register 29 ACCDET Control Register 30 ACCDET Control Register 31 ACCDET Control Register 32 ACCDET Control Register 33 ACCDET Control Register 34 ACCDET Control Register 35 ACCDET Control Register 36 ACCDET Control Register 37 ACCDET Control Register 38 ACCDET Control Register 39 ACCDET Control Register 40

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 340 of 1067

MT6359 PMIC Datasheet Confidential A 00000000

TOP0_ID

TOP0 Design ID Register

00002800

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000002

Description

TOP0_REV0

TOP0 Design Revision Register 0

00001000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000004

Description

TOP0_DSN_DBI

TOP0 Design Bank Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000006

Description

TOP0_DSN_DXI

TOP0 Design Extra Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

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Page 341 of 1067

ess

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00000008

Description

HWCID

HW Chip ID Status

00005930

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000000A

Description

SWCID

SW Chip ID Status

00005920

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

20

19

18

17

0000000C

Description

PONSTS

Power on Source Record Register

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

Bit

15

14

13

12

11

10

9

8

7

6

5

Name Type Reset Bit(s) 4 3 2 1 0

00000000

4 3 2 1 0 STS_RB STS_SP STS_CH STS_RT STS_P OOT AR RIN CA WRKEY RO RO RO RO RO 0

Name STS_RBOOT STS_SPAR STS_CHRIN STS_RTCA

MediaTek Proprietary and Confidential.

16

0

0

0

0

Description Power on for cold reset Power on for SPAR event Power on for charger insertion Power on for RTC alarm

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 342 of 1067

MT6359 PMIC Datasheet Confidential A 0000000E

POFFSTS

Power off Source Record Register

Bit Name Type Reset

31

30

29

28

27

26

25

24

Bit

15

14

13

12

11

10

9

8

0

0

0

0

0

0

0

Name Type Reset Bit(s) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

22

21

00000000 20

19

18

17

16

7 6 5 4 3 2 1 0 STS_N STS_O STS_PK STS_KE STS_PU STS_W STS_DD STS_B STS_PK STS_CR STS_W STS_TH STS_PS STS_PG STS_U ORMO VLO SP YPWR PSRC DT LO WDT EYLP ST RST RDN OC FAIL VLO FF RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO

Name STS_OVLO STS_PKSP STS_KEYPWR STS_PUPSRC STS_WDT STS_DDLO STS_BWDT STS_NORMOFF STS_PKEYLP STS_CRST STS_WRST STS_THRDN STS_PSOC STS_PGFAIL STS_UVLO

00000010

23

0

0

0

0

0

0

0

0

Description Power off for OVLO event PWRKEY short press Critical power is turned off during system on. Power off for power source missing AP WDT DDLO occurs after system on. Power off for BWDT Power off for PWRHOLD clear Power off for power key(s) long press Power off for cold reset Power reset for warm reset Power off for thermal shutdown Power off for default on BUCK OC Power off for PWRGOOD failure Power off for UVLO event

PSTSCTL

Power on/off Status Control

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8 RG_PO NSTS_C LR RW

7

6

5

4

3

2

1

0 RG_PO FFSTS_ CLR RW

Name Type Reset Bit(s) 8 0

0

Name RG_PONSTS_CLR RG_POFFSTS_CLR

MediaTek Proprietary and Confidential.

0

Description Clears PONSTS Clears POFFSTST and PG/OC status

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 343 of 1067

MT6359 PMIC Datasheet Confidential A 00000012

PG_DEB_STS0

Power Good Debounce Status Register 0

0000FFFF

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000014

Description

PG_DEB_STS1

Power Good Debounce Status Register 1

0000FFF8

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000016

Description

PG_SDN_STS0

Power Good Shutdown Status Register 0

0000FFFF

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000018

Description

PG_SDN_STS1

Power Good Shutdown Status Register 1

0000FFF8

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

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Page 344 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

0000001A

Description

OC_SDN_STS0

BUCK OC Shutdown Status Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000001C

Description

OC_SDN_STS1

BUCK OC Shutdown Status Register 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000001E Bit Name Type Reset

Description

THERMALSTATUS 31

30

15 14 STRUP PMU_T _THER HERMA Name MAL_S L_DEB TATUS RO RO Type

Bit

Reset Bit(s) 15

14

0

Thermal Status

00000000

29

28

27

26

25

24

23

22

21

20

19

18

17

16

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

Name STRUP_THERMAL_STATUS

PMU_THERMAL_DEB

MediaTek Proprietary and Confidential.

Description Shutdown thermal status (cleared by SW) 0: No thermal 1: Thermal occurs. Debounced thermal status

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 345 of 1067

MT6359 PMIC Datasheet Confidential A 00000020

TOP_CON

Top Control Register

00000105

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

22

21

20

19

18

17

16

6

5

4

3

2

1

0

0

00000022

Description

TEST_OUT

TEST_OUT

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

Bit(s) 11:0

TEST_OUT RO 0

0

Name TEST_OUT

00000024

0

0

0

0

0

0

0

0

0

Description Monitor

TEST_CON0

Test Control 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000026

Description

TEST_CON1

Test Control 2

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

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Page 346 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00000028

Description

TESTMODE_SW

TESTMODE_SW

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

19

18

17

0000002A

Description

TOPSTATUS

TOP Status

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

Bit

15

14

13

12

11

10

9

8

7

6

5

4

Name Type Reset Bit(s) 3 2 1

Name HOMEKEY_DEB CHRDET_DEB PWRKEY_DEB

0000002C

0

0

0

19

18

17

TDSEL_CON

TDSEL_CON

00000000

31

30

29

28

27

26

25

24

23

22

21

20

Bit

15

14

13

12

11

10

9

8

7

6

5

4

Name Type Reset Name RG_E32CAL_TDSEL RG_AUD_TDSEL RG_SPI_TDSEL RG_PMU_TDSEL

16

3 2 1 0 RG_E32 RG_AU RG_PM RG_SPI CAL_TD D_TDS U_TDS _TDSEL SEL EL EL RW RW RW RW 0

MediaTek Proprietary and Confidential.

0

Description HOMEKEY status (dynamic change with HW) CHRDET status (dynamic change with HW) PWRKEY status (dynamic change with HW)

Bit Name Type Reset

Bit(s) 3 2 1 0

3 2 1 HOME CHRDE PWRKE KEY_DE T_DEB Y_DEB B RO RO RO

16

0

0

0

Description TDSEL TDSEL TDSEL TDSEL

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 347 of 1067

MT6359 PMIC Datasheet Confidential A 0000002E

RDSEL_CON

RDSEL_CON

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

Bit

15

14

13

12

11

10

9

8

7

6

5

4

Name Type Reset Bit(s) 3 2 1 0

Name RG_E32CAL_RDSEL RG_AUD_RDSEL RG_SPI_RDSEL RG_PMU_RDSEL

00000030

18

17

16

3 2 1 0 RG_E32 RG_AU RG_PM RG_SPI CAL_R D_RDS U_RDS _RDSEL DSEL EL EL RW RW RW RW 0

0

0

19

18

17

0

Description RDSEL RDSEL RDSEL RDSEL

SMT_CON0

SMT_CON0

0000005E

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

Bit

15

14

13

12

11

10

9

8

7

Name Type Reset Bit(s) 6

19

22

5

RG_SMT_HOMEKEY

4

RG_SMT_RTC_32K1V8_1

3

RG_SMT_RTC_32K1V8_0

2

RG_SMT_SRCLKEN_IN1

20

16

6 5 4 3 2 1 0 RG_SM RG_SM RG_SM RG_SM RG_SM RG_SM RG_SM T_SCP_ T_RTC_ T_RTC_ T_SRCL T_SRCL T_WDT T_HOM VREQ_ 32K1V8 32K1V8 KEN_IN KEN_IN RSTB_I EKEY VAO _1 _0 1 0 N RW RW RW RW RW RW RW 1

Name RG_SMT_SCP_VREQ_VAO

21

0

1

1

1

1

0

Description SMT 0: Disable 1: Enable SMT 0: Disable 1: Enable SMT 0: Disable 1: Enable SMT 0: Disable 1: Enable SMT 0: Disable 1: Enable

1

0

RG_SMT_WDTRSTB_IN

MediaTek Proprietary and Confidential.

0: Disable 1: Enable SMT 0: Disable 1: Enable

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 348 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00000032

Description

SMT_CON1

Bit Name Type Reset

31

30

Bit

15

14

Name Type Reset

29

SMT_CON1 28

26

25

24

23

22

21

20

19

18

17

16

13 12 11 10 9 8 7 6 5 4 3 2 1 0 RG_SM RG_SM RG_SM RG_SM RG_SM RG_SM RG_SM RG_SM RG_SM RG_SM RG_SM RG_SM RG_SM RG_SM T_AUD T_AUD T_AUD T_AUD T_AUD T_AUD T_AUD T_AUD T_AUD T_AUD T_SPI_ T_SPI_ T_SPI_ T_SPI_ _DAT_ _DAT_ _DAT_ _NLE_ _NLE_ _SYNC_ _DAT_ _DAT_ _DAT_ _CLK_ MISO MOSI CSN CLK MISO2 MISO1 MISO0 MOSI1 MOSI0 MOSI MOSI2 MOSI1 MOSI0 MOSI RW RW RW RW RW RW RW RW RW RW RW RW RW RW 0

0

Bit(s) 13

Name RG_SMT_AUD_DAT_MISO2

12

RG_SMT_AUD_DAT_MISO1

11

RG_SMT_AUD_DAT_MISO0

10

RG_SMT_AUD_NLE_MOSI1

9

RG_SMT_AUD_NLE_MOSI0

8

RG_SMT_AUD_SYNC_MOSI

7

RG_SMT_AUD_DAT_MOSI2

6

RG_SMT_AUD_DAT_MOSI1

5

RG_SMT_AUD_DAT_MOSI0

4

RG_SMT_AUD_CLK_MOSI

3

RG_SMT_SPI_MISO

2

RG_SMT_SPI_MOSI

1

RG_SMT_SPI_CSN

MediaTek Proprietary and Confidential.

27

00000000

0

0

0

0

0

0

0

0

0

0

0

0

Description SMT 0: Disable 1: Enable SMT 0: Disable 1: Enable SMT 0: Disable 1: Enable SMT 0: Disable 1: Enable SMT 0: Disable 1: Enable SMT 0: Disable 1: Enable SMT 0: Disable 1: Enable SMT 0: Disable 1: Enable SMT 0: Disable 1: Enable SMT 0: Disable 1: Enable SMT 0: Disable 1: Enable SMT 0: Disable 1: Enable SMT 0: Disable

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 349 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 0

Name

Description 1: Enable SMT 0: Disable 1: Enable

RG_SMT_SPI_CLK

00000034

TOP_RSV0

TOP_RSV0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0 RG_TO P_RSV 0 RO

Name Type Reset Bit(s) 0

0

Name RG_TOP_RSV0

00000036

Description Do not modify this. Conflicts with MT6337.

TOP_RSV1

TOP_RSV1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0 RG_TO P_RSV 1 RO

Name Type Reset Bit(s) 0

0

Name RG_TOP_RSV1

00000038

Description Do not modify this. Conflicts with MT6337.

DRV_CON0

DRV_CON0

00008888

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s) 15:12

RG_OCTL_RTC_32K1V8_1 RW 1 0 0 0

Name RG_OCTL_RTC_32K1V8_1

MediaTek Proprietary and Confidential.

RG_OCTL_RTC_32K1V8_0 RW 1 0 0 0

RG_OCTL_SRCLKEN_IN1 RW 1 0 0 0

RG_OCTL_SRCLKEN_IN0 RW 1 0 0 0

Description OC CTL

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 350 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 11:8 7:4 3:0

Name RG_OCTL_RTC_32K1V8_0 RG_OCTL_SRCLKEN_IN1 RG_OCTL_SRCLKEN_IN0

0000003A

Description OC CTL OC CTL OC CTL

DRV_CON1

DRV_CON1

00008888

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s) 15:12 11:8 7:4 3:0

RG_OCTL_SPI_MISO RW 1 0 0 0

Name RG_OCTL_SPI_MISO RG_OCTL_SPI_MOSI RG_OCTL_SPI_CSN RG_OCTL_SPI_CLK

0000003C Bit Name Type Reset

DRV_CON2 30

29

28

15

14

13

12

RG_OCTL_AUD_DAT_MOSI2 RW 1 0 0 0

Bit(s) 15:12 11:8 7:4 3:0

Name RG_OCTL_AUD_DAT_MOSI2 RG_OCTL_AUD_DAT_MOSI1 RG_OCTL_AUD_DAT_MOSI0 RG_OCTL_AUD_CLK_MOSI

27

26

25

24

11

10

9

8

RG_OCTL_AUD_DAT_MOSI1 RW 1 0 0 0

23

22

21

20

19

18

17

16

7

6

5

4

3

2

1

0

00008888

RG_OCTL_AUD_DAT_MOSI0 RW 1 0 0 0

RG_OCTL_AUD_CLK_MOSI RW 1 0 0 0

Description OC CTL OC CTL OC CTL OC CTL

DRV_CON3

DRV_CON3

31

30

29

28

15

14

13

12

Bit Name Type Reset

RG_OCTL_AUD_DAT_MISO0 RW 1 0 0 0

Bit(s) 15:12 11:8

Name RG_OCTL_AUD_DAT_MISO0 RG_OCTL_AUD_NLE_MOSI1

MediaTek Proprietary and Confidential.

RG_OCTL_SPI_CLK RW 1 0 0 0

DRV_CON2

31

0000003E

RG_OCTL_SPI_CSN RW 1 0 0 0

Description OC CTL OC CTL OC CTL OC CTL

Bit Name Type Reset

Bit Name Type Reset

RG_OCTL_SPI_MOSI RW 1 0 0 0

27

26

25

24

11

10

9

8

RG_OCTL_AUD_NLE_MOSI1 RW 1 0 0 0

00008888 23

22

21

20

7

6

5

4

RG_OCTL_AUD_NLE_MOSI0 RW 1 0 0 0

19

18

17

16

3

2

1

0

RG_OCTL_AUD_SYNC_MOSI RW 1 0 0 0

Description OC CTL OC CTL

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 351 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 7:4 3:0

Name RG_OCTL_AUD_NLE_MOSI0 RG_OCTL_AUD_SYNC_MOSI

00000040 Bit Name Type Reset

DRV_CON4

DRV_CON4

31

30

29

28

27

26

25

24

15

14

13

12

11

10

9

8

Bit Name Type Reset

RG_OCTL_SCP_VREQ_VAO RW 1 0 0 0

Bit(s) 15:12 11:8 7:4 3:0

Name RG_OCTL_SCP_VREQ_VAO RG_OCTL_HOMEKEY RG_OCTL_AUD_DAT_MISO2 RG_OCTL_AUD_DAT_MISO1

00000042 Bit Name Type Reset

Description OC CTL OC CTL

RG_OCTL_HOMEKEY RW 1 0 0 0

30

29

22

21

20

7

6

5

4

RG_OCTL_AUD_DAT_MISO2 RW 1 0 0 0

19

18

17

16

3

2

1

0

RG_OCTL_AUD_DAT_MISO1 RW 1 0 0 0

Description OC CTL OC CTL OC CTL OC CTL

FILTER_CON0 31

00008888 23

FILTER_CON0 28

27

26

25

24

00000000 23

22

21

20

19

18

17

16

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RG_AU RG_AU RG_AU RG_AU RG_AU RG_AU RG_AU RG_AU RG_RT RG_RT RG_SR RG_SPI RG_SPI RG_SPI RG_SPI RG_SR D_DAT D_DAT D_DAT D_SYN D_DAT D_DAT D_DAT D_CLK_ C32K_1 C32K_1 CLKEN _MISO _MOSI _CSN_F _CLK_F CLKEN_ V8_1_F V8_0_F _IN0_F Name _MISO _MISO _MISO C_MOS _MOSI _MOSI _MOSI MOSI_ _FILTER _FILTER ILTER_ ILTER_ IN1_FIL 2_FILTE 1_FILTE 0_FILTE I_FILTE 2_FILTE 1_FILTE 0_FILTE FILTER_ ILTER_ ILTER_ ILTER_ _EN _EN EN EN TER_EN R_EN R_EN R_EN R_EN R_EN R_EN R_EN EN EN EN EN RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

Bit

Bit(s) 15

Name RG_AUD_DAT_MISO2_FILTER_EN

14

RG_AUD_DAT_MISO1_FILTER_EN

13

RG_AUD_DAT_MISO0_FILTER_EN

12

RG_AUD_SYNC_MOSI_FILTER_EN

11

RG_AUD_DAT_MOSI2_FILTER_EN

10

RG_AUD_DAT_MOSI1_FILTER_EN

MediaTek Proprietary and Confidential.

Description FILTER function 0: Disable 1: Enable FILTER function 0: Disable 1: Enable FILTER function 0: Disable 1: Enable FILTER function 0: Disable FILTER function 0: Disable 1: Enable FILTER function 0: Disable

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 352 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

9

RG_AUD_DAT_MOSI0_FILTER_EN

8

RG_AUD_CLK_MOSI_FILTER_EN

7

RG_SPI_MISO_FILTER_EN

6

RG_SPI_MOSI_FILTER_EN

5

RG_SPI_CSN_FILTER_EN

4

RG_SPI_CLK_FILTER_EN

3

RG_RTC32K_1V8_1_FILTER_EN

2

RG_RTC32K_1V8_0_FILTER_EN

1

RG_SRCLKEN_IN1_FILTER_EN

0

RG_SRCLKEN_IN0_FILTER_EN

00000044

Description 1: Enable FILTER function 0: Disable 1: Enable FILTER function 0: Disable 1: Enable FILTER function 0: Disable 1: Enable FILTER function 0: Disable 1: Enable FILTER function 0: Disable 1: Enable FILTER function 0: Disable 1: Enable FILTER function 0: Disable 1: Enable FILTER function 0: Disable 1: Enable FILTER function 0: Disable 1: Enable FILTER function 0: Disable 1: Enable

FILTER_CON1

FILTER_CON1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

Bit

15

14

13

12

11

10

9

8

7

6

5

Name

Type Reset

20

Name RG_AUD_NLE_MOSI1_FILTER_EN

3

RG_AUD_NLE_MOSI0_FILTER_EN

MediaTek Proprietary and Confidential.

18

17

16

4 3 2 1 0 RG_AU RG_AU RG_SC RG_W RG_HO D_NLE_ D_NLE_ P_VRE DTRST MEKEY MOSI1 MOSI0 Q_VAO B_IN_F _FILTER _FILTER _FILTER _FILTER ILTER_ _EN _EN _EN _EN EN RW RW RW RW RW 0

Bit(s) 4

19

0

0

0

0

Description FILTER function 0: Disable 1: Enable FILTER function 0: Disable 1: Enable

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 353 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 2

Name RG_SCP_VREQ_VAO_FILTER_EN

1

RG_HOMEKEY_FILTER_EN

0

RG_WDTRSTB_IN_FILTER_EN

00000046 Bit Name Type Reset

Description FILTER function 0: Disable 1: Enable FILTER function 0: Disable 1: Enable FILTER function 0: Disable 1: Enable

FILTER_CON2 31

30

29

FILTER_CON2 28

27

26

25

24

00000000 23

22

21

20

19

18

17

16

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RG_AU RG_AU RG_AU RG_AU RG_AU RG_AU RG_AU RG_AU RG_RT RG_RT RG_SR RG_SR D_DAT D_DAT D_DAT D_SYN D_DAT D_DAT D_DAT RG_SPI RG_SPI RG_SPI RG_SPI D_CLK_ C32K_1 C32K_1 CLKEN_ CLKEN Name _MISO _MISO _MISO C_MOS _MOSI _MOSI _MOSI MOSI_ _MISO _MOSI _CSN_ _CLK_R V8_1_R V8_0_R IN1_RC _IN0_R 2_RCSE 1_RCSE 0_RCSE I_RCSE 2_RCSE 1_RCSE 0_RCSE _RCSEL _RCSEL RCSEL CSEL RCSEL CSEL CSEL SEL CSEL L L L L L L L RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

Bit

Bit(s) 15

Name RG_AUD_DAT_MISO2_RCSEL

14

RG_AUD_DAT_MISO1_RCSEL

13

RG_AUD_DAT_MISO0_RCSEL

12

RG_AUD_SYNC_MOSI_RCSEL

11

RG_AUD_DAT_MOSI2_RCSEL

10

RG_AUD_DAT_MOSI1_RCSEL

9

RG_AUD_DAT_MOSI0_RCSEL

8

RG_AUD_CLK_MOSI_RCSEL

7

RG_SPI_MISO_RCSEL

6

RG_SPI_MOSI_RCSEL

MediaTek Proprietary and Confidential.

Description FILTER function 0: Disable 1: Enable FILTER function 0: Disable 1: Enable FILTER function 0: Disable 1: Enable FILTER function 0: Disable 1: Enable FILTER function 0: Disable 1: Enable FILTER function 0: Disable 1: Enable FILTER function 0: Disable 1: Enable FILTER function 0: Disable 1: Enable FILTER function 0: Disable 1: Enable FILTER function

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 354 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

5

RG_SPI_CSN_RCSEL

4

RG_SPI_CLK_RCSEL

3

RG_RTC32K_1V8_1_RCSEL

2

RG_RTC32K_1V8_0_RCSEL

1

RG_SRCLKEN_IN1_RCSEL

0

RG_SRCLKEN_IN0_RCSEL

00000048

Description 0: Disable 1: Enable FILTER function 0: Disable 1: Enable FILTER function 0: Disable 1: Enable FILTER function 0: Disable 1: Enable FILTER function 0: Disable 1: Enable FILTER function 0: Disable 1: Enable FILTER function 0: Disable 1: Enable

FILTER_CON3

FILTER_CON3

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

Bit

15

14

13

12

11

10

9

8

7

6

5

Name Type Reset

20

Name RG_AUD_NLE_MOSI1_RCSEL

3

RG_AUD_NLE_MOSI0_RCSEL

2

RG_SCP_VREQ_VAO_RCSEL

1

RG_HOMEKEY_RCSEL

0

RG_WDTRSTB_IN_RCSEL

MediaTek Proprietary and Confidential.

18

17

16

4 3 2 1 0 RG_AU RG_AU RG_SC RG_W RG_HO D_NLE_ D_NLE_ P_VRE DTRST MEKEY MOSI1 MOSI0 Q_VAO B_IN_R _RCSEL _RCSEL _RCSEL _RCSEL CSEL RW RW RW RW RW 0

Bit(s) 4

19

0

0

0

0

Description FILTER function 0: Disable 1: Enable FILTER function 0: Disable 1: Enable FILTER function 0: Disable 1: Enable FILTER function 0: Disable 1: Enable FILTER function 0: Disable 1: Enable

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 355 of 1067

MT6359 PMIC Datasheet Confidential A 0000004A

TOP_STATUS

TOP_Status

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

Bit(s) 3:0

18

17

16

2

1

0

TOP_STATUS RW

Name TOP_STATUS

0000004C

0

0

0

0

Description Reserved

TOP_STATUS_SET

TOP_Status Register SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000004E

Description

TOP_STATUS_CLR

TOP_Status Register CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000050

Description

TOP_TRAP

Top VM Trap Value

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 356 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00000080

Description

TOP1_ID

TOP1 Design ID Register

00002900

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000082

Description

TOP1_REV0

TOP1 Design Revision Register 0

00001000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000084

Description

TOP1_DSN_DBI

TOP1 Design Bank Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 357 of 1067

MT6359 PMIC Datasheet Confidential A 00000086

TOP1_DSN_DXI

TOP1 Design Extra Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000088

Description

GPIO_DIR0

GPIO Direction Control Register 0

Bit Name Type Reset

31

30

29

28

27

26

25

Bit Name Type Reset

15

14

13

12

11

10

9

Bit(s) 15:0

0

0

0

0

0

0

Name GPIO_DIR0

0000008A

0

GPIO_DIR0_SET 30

29

28

27

26

25

Bit Name Type Reset

15

14

13

12

11

10

9

Bit(s) 15:0

Name GPIO_DIR0_SET

MediaTek Proprietary and Confidential.

22

21

20

19

18

17

16

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

GPIO_DIR0 RW 0 0

GPIO_DIR0 Register SET

31

0

23

Description GPIO direction control 1'b0: Input 1'b1: Output

Bit Name Type Reset

0

00000000

24

0

0

0

0

0

00000000

24

23

22

21

20

19

18

17

16

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

GPIO_DIR0_SET W1 0 0

Description 1'b0: Not set 1'b1: Set

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 358 of 1067

MT6359 PMIC Datasheet Confidential A 0000008C

GPIO_DIR0_CLR

GPIO_DIR0 Register CLR

Bit Name Type Reset

31

30

29

28

27

26

25

Bit Name Type Reset

15

14

13

12

11

10

9

Bit(s) 15:0

0

0

0

0

0

0

Name GPIO_DIR0_CLR

0000008E

0

00000000

24

23

22

21

20

19

18

17

16

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

GPIO_DIR0_CLR W1 0 0

Description 1'b0: Not clear 1'b1: Clear

GPIO_DIR1

GPIO Direction Control Register 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s) 3:0

GPIO_DIR1 RW

Name GPIO_DIR1

00000090

GPIO_DIR1_SET 30

29

28

27

26

25

Bit Name Type Reset

15

14

13

12

11

10

9

Bit(s) 15:0

Name GPIO_DIR1_SET

MediaTek Proprietary and Confidential.

0

GPIO_DIR1 Register SET

31

0

0

0

Description GPIO direction control 1'b0: Input 1'b1: Output

Bit Name Type Reset

0

0

0

0

0

0

0

00000000

24

23

22

21

20

19

18

17

16

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

GPIO_DIR1_SET W1 0 0

Description 1'b0: Not set 1'b1: Set

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 359 of 1067

MT6359 PMIC Datasheet Confidential A 00000092

GPIO_DIR1_CLR

GPIO_DIR1 Register CLR

Bit Name Type Reset

31

30

29

28

27

26

25

Bit Name Type Reset

15

14

13

12

11

10

9

Bit(s) 15:0

0

0

0

0

0

0

Name GPIO_DIR1_CLR

00000094

0

00000000

24

23

22

21

20

19

18

17

16

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

GPIO_DIR1_CLR W1 0 0

Description 1'b0: Not clear 1'b1: Clear

GPIO_PULLEN0

GPIO Pull-up/Pull-down Enable Register 0

00007F33

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

1

1

0

0

1

1

Bit(s) 15:0

0

1

1

1

1

1

Name GPIO_PULLEN0

00000096

1

GPIO_PULLEN0 RW 1 0

Description Enables GPIO pull-up/pull-down 1'b0: Disable 1'b1: Enable

GPIO_PULLEN0_SET

GPIO_PULLEN0 Register SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

GPIO_PULLEN0_SET W1 0 0 0 0

0

0

0

0

0

0

Bit(s) 15:0

0

0

0

0

Name GPIO_PULLEN0_SET

MediaTek Proprietary and Confidential.

0

Description 1'b0: Not set 1'b1: Set

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 360 of 1067

MT6359 PMIC Datasheet Confidential A 00000098

GPIO_PULLEN0_CLR

GPIO_PULLEN0 Register CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

GPIO_PULLEN0_CLR W1 0 0 0 0

0

0

0

0

0

0

Bit(s) 15:0

0

0

0

0

0

Name GPIO_PULLEN0_CLR

0000009A

Description 1'b0: Not clear 1'b1: Clear

GPIO_PULLEN1

GPIO Pull-up/Pull-down Enable Register 1

0000000C

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s) 3:0

GPIO_PULLEN1 RW

Name GPIO_PULLEN1

0000009C

1

1

0

0

Description Enables GPIO pull-up/pull-down 1'b0: Disable 1'b1: Enable

GPIO_PULLEN1_SET

GPIO_PULLEN1 Register SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

GPIO_PULLEN1_SET W1 0 0 0 0

0

0

0

0

0

0

Bit(s) 15:0

0

0

0

0

Name GPIO_PULLEN1_SET

MediaTek Proprietary and Confidential.

0

Description 1'b0: Not set 1'b1: Set

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 361 of 1067

MT6359 PMIC Datasheet Confidential A 0000009E

GPIO_PULLEN1_CLR

GPIO_PULLEN1 Register CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

GPIO_PULLEN1_CLR W1 0 0 0 0

0

0

0

0

0

0

Bit(s) 15:0

0

0

0

0

0

Name GPIO_PULLEN1_CLR

000000A0

Description 1'b0: Not clear 1'b1: Clear

GPIO_PULLSEL0

GPIO Pull-up/Pull-down Selection Register 0

00000021

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

1

0

0

0

0

1

Bit(s) 15:0

0

0

0

0

0

0

Name GPIO_PULLSEL0

000000A2

0

GPIO_PULLSEL0 RW 0 0

Description Selects GPIO pull-up/pull-down 1'b0: Pull-down 1'b1: Pull-up

GPIO_PULLSEL0_SET

GPIO_PULLSEL0 Register SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

GPIO_PULLSEL0_SET W1 0 0 0 0

0

0

0

0

0

0

Bit(s) 15:0

0

0

0

0

Name GPIO_PULLSEL0_SET

MediaTek Proprietary and Confidential.

0

Description 1'b0: Not set 1'b1: Set

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 362 of 1067

MT6359 PMIC Datasheet Confidential A 000000A4

GPIO_PULLSEL0_CLR

GPIO_PULLSEL0 Register CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

GPIO_PULLSEL0_CLR W1 0 0 0 0

0

0

0

0

0

0

Bit(s) 15:0

0

0

0

0

0

Name GPIO_PULLSEL0_CLR

000000A6

Description 1'b0: Not clear 1'b1: Clear

GPIO_PULLSEL1

GPIO Pull-up/Pull-down Selection Register 1

00000004

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s) 3:0

GPIO_PULLSEL1 RW

Name GPIO_PULLSEL1

000000A8

0

1

0

0

Description Selects GPIO pull-up/pull-down 1'b0: Pull-down 1'b1: Pull-up

GPIO_PULLSEL1_SET

GPIO_PULLSEL1 Register SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

GPIO_PULLSEL1_SET W1 0 0 0 0

0

0

0

0

0

0

Bit(s) 15:0

0

0

0

0

Name GPIO_PULLSEL1_SET

MediaTek Proprietary and Confidential.

0

Description 1'b0: Not set 1'b1: Set

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 363 of 1067

MT6359 PMIC Datasheet Confidential A 000000AA

GPIO_PULLSEL1_CLR

GPIO_PULLSEL1 Register CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

GPIO_PULLSEL1_CLR W1 0 0 0 0

0

0

0

0

0

0

Bit(s) 15:0

0

0

0

0

0

Name GPIO_PULLSEL1_CLR

000000AC

Description 1'b0: Not clear 1'b1: Clear

GPIO_DINV0

GPIO Data Inversion Control Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

Bit(s) 15:0

0

0

0

0

0

0

Name GPIO_DINV0

000000AE

0

Description GPIO inversion control 1'b0: Disable 1'b1: Enable

GPIO_DINV0_SET

GPIO_DINV0 Register SET

Bit Name Type Reset

31

30

29

28

27

26

25

Bit Name Type Reset

15

14

13

12

11

10

9

Bit(s) 15:0

0

0

0

Name GPIO_DINV0_SET

MediaTek Proprietary and Confidential.

GPIO_DINV0 RW 0 0

0

0

0

0

00000000

24

23

22

21

20

19

18

17

16

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

GPIO_DINV0_SET W1 0 0

Description 1'b0: Not set 1'b1: Set

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 364 of 1067

MT6359 PMIC Datasheet Confidential A 000000B0

GPIO_DINV0_CLR

GPIO_DINV0 Register CLR

Bit Name Type Reset

31

30

29

28

27

26

25

Bit Name Type Reset

15

14

13

12

11

10

9

Bit(s) 15:0

0

0

0

0

0

0

Name GPIO_DINV0_CLR

000000B2

0

00000000

24

23

22

21

20

19

18

17

16

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

GPIO_DINV0_CLR W1 0 0

Description 1'b0: Not clear 1'b1: Clear

GPIO_DINV1

GPIO Data Inversion Control Register 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s) 3:0

GPIO_DINV1 RW

Name GPIO_DINV1

000000B4

GPIO_DINV1_SET 30

29

28

27

26

25

Bit Name Type Reset

15

14

13

12

11

10

9

Bit(s) 15:0

0

Name GPIO_DINV1_SET

MediaTek Proprietary and Confidential.

0

GPIO_DINV1 Register SET

31

0

0

0

Description GPIO inversion control 1'b0: Disable 1'b1: Enable

Bit Name Type Reset

0

0

0

0

0

0

00000000

24

23

22

21

20

19

18

17

16

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

GPIO_DINV1_SET W1 0 0

Description 1'b0: Not set 1'b1: Set

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 365 of 1067

MT6359 PMIC Datasheet Confidential A 000000B6

GPIO_DINV1_CLR

GPIO_DINV1 Register CLR

Bit Name Type Reset

31

30

29

28

27

26

25

Bit Name Type Reset

15

14

13

12

11

10

9

Bit(s) 15:0

0

0

0

0

0

0

Name GPIO_DINV1_CLR

000000B8

0

00000000

24

23

22

21

20

19

18

17

16

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

GPIO_DINV1_CLR W1 0 0

Description 1'b0: Not clear 1'b1: Clear

GPIO_DOUT0

GPIO Data Output Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

Bit(s) 15:0

0

0

0

0

0

0

Name GPIO_DOUT0

000000BA

0

GPIO_DOUT0 RW 0 0

Description GPIO data output value 1'b0: Output 0 1'b1: Output 1

GPIO_DOUT0_SET

GPIO_DOUT0 Register SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

GPIO_DOUT0_SET W1 0 0 0

0

0

0

0

0

0

0

Bit(s) 15:0

0

0

0

Name GPIO_DOUT0_SET

MediaTek Proprietary and Confidential.

0

0

Description 1'b0: Not set 1'b1: Set

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 366 of 1067

MT6359 PMIC Datasheet Confidential A 000000BC

GPIO_DOUT0_CLR

GPIO_DOUT0 Register CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

GPIO_DOUT0_CLR W1 0 0 0 0

0

0

0

0

0

0

Bit(s) 15:0

0

0

0

0

0

Name GPIO_DOUT0_CLR

000000BE

Description 1'b0: Not clear 1'b1: Clear

GPIO_DOUT1

GPIO Data Output Register 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s) 3:0

GPIO_DOUT1 RW

Name GPIO_DOUT1

000000C0

0

0

0

0

Description GPIO data output value 1'b0: Output 0 1'b1: Output 1

GPIO_DOUT1_SET

GPIO_DOUT1 Register SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

GPIO_DOUT1_SET W1 0 0 0

0

0

0

0

0

0

0

Bit(s) 15:0

0

0

0

Name GPIO_DOUT1_SET

MediaTek Proprietary and Confidential.

0

0

Description 1'b0: Not set 1'b1: Set

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 367 of 1067

MT6359 PMIC Datasheet Confidential A 000000C2

GPIO_DOUT1_CLR

GPIO_DOUT1 Register CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

GPIO_DOUT1_CLR W1 0 0 0 0

0

0

0

0

0

0

Bit(s) 15:0

0

0

0

0

0

Name GPIO_DOUT1_CLR

000000C4

Description 1'b0: Not clear 1'b1: Clear

GPIO_PI0

GPIO Data Input Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

GPIO_PI0 RO 0 0

0

0

0

0

0

0

0

18

17

16

2

1

0

Bit(s) 15:0

0

0

0

0

0

0

Name GPIO_PI0

000000C6

Description GPIO data input value

GPIO_PI1

GPIO Data Input Register 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

Bit(s) 3:0

GPIO_PI1 RO 0

Name GPIO_PI1

MediaTek Proprietary and Confidential.

0

0

0

Description GPIO data input value

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 368 of 1067

MT6359 PMIC Datasheet Confidential A 000000C8

GPIO_POE0

GPIO Data Direction Register 0

Bit Name Type Reset

31

30

29

28

27

26

25

Bit Name Type Reset

15

14

13

12

11

10

9

Bit(s) 15:0

0

0

0

0

0

0

Name GPIO_POE0

000000CA

0

00000000

24

23

22

21

20

19

18

17

16

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

GPIO_POE0 RO 0 0

Description GPIO direction value

GPIO_POE1

GPIO Data Direction Register 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s) 3:0

GPIO_POE1 RO

Name GPIO_POE1

000000CC

0

0

0

0

Description GPIO direction value

GPIO_MODE0

GPIO Mode Control Register 0

00000249

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

GPIO3_MODE

GPIO2_MODE

RW 0

Bit(s) 11:9

Name GPIO3_MODE

8:6

GPIO2_MODE

MediaTek Proprietary and Confidential.

0

GPIO1_MODE

RW 1

0

0

GPIO0_MODE

RW 1

0

0

RW 1

0

0

1

Description Selects GPIO 3 mode 0: GPIO3 (IO) 1: RTC_32K1V8_1 (O) 2: INT_1 (O) 3: Reserved 4: Reserved 5: Reserved 6: TEST_IN3 (I) 7: TEST_OUT3 (O) Selects GPIO 2 mode 0: GPIO2 (IO) 1: RTC_32K1V8_0 (O) 2: Reserved © 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 369 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

5:3

GPIO1_MODE

2:0

GPIO0_MODE

000000CE

Description 3: Reserved 4: Reserved 5: Reserved 6: TEST_IN2 (I) 7: TEST_OUT2 (O) Selects GPIO 1 mode 0: GPIO1 (IO) 1: SRCLKEN_IN1 (I) 2: Reserved 3: Reserved 4: Reserved 5: Reserved 6: TEST_IN1 (I) 7: TEST_OUT1 (O) Selects GPIO 0 mode 0: GPIO0 (IO) 1: SRCLKEN_IN0 (I) 2: Reserved 3: Reserved 4: Reserved 5: Reserved 6: TEST_IN0 (I) 7: TEST_OUT0 (O)

GPIO_MODE0_SET

GPIO_MODE0 Register SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

GPIO_MODE0_SET W1 0 0 0 0

0

0

0

0

0

0

Bit(s) 15:0

0

0

0

0

0

Name GPIO_MODE0_SET

000000D0

Description 1'b0: Not set 1'b1: Set

GPIO_MODE0_CLR

GPIO_MODE0 Register CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

GPIO_MODE0_CLR W1 0 0 0 0

0

0

0

0

0

0

Bit(s) 15:0

0

0

0

Name GPIO_MODE0_CLR

MediaTek Proprietary and Confidential.

0

0

Description 1'b0: Not clear © 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 370 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

000000D2

Description 1'b1: Clear

GPIO_MODE1

GPIO Mode Control Register 1

00000249

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

Bit(s) 11:9

Name GPIO7_MODE

8:6

GPIO6_MODE

5:3

GPIO5_MODE

2:0

GPIO4_MODE

MediaTek Proprietary and Confidential.

GPIO7_MODE

GPIO6_MODE

GPIO5_MODE

GPIO4_MODE

RW

RW

RW

RW

0

1

0

0

1

0

0

1

0

0

1

Description Selects GPIO 7 mode 0: GPIO7 (IO) 1: SPI_MISO (IO) 2: Reserved 3: Reserved 4: Reserved 5: Reserved 6: Reserved 7: Reserved Selects GPIO 6 mode 0: GPIO6 (IO) 1: SPI_MOSI (IO) 2: Reserved 3: Reserved 4: Reserved 5: Reserved 6: Reserved 7: Reserved Selects GPIO 5 mode 0: GPIO5 (IO) 1: SPI_CSN (I) 2: Reserved 3: Reserved 4: Reserved 5: Reserved 6: Reserved 7: Reserved Selects GPIO 4 mode 0: GPIO4 (IO) 1: SPI_CLK (I) 2: Reserved 3: Reserved 4: Reserved 5: Reserved 6: Reserved 7: Reserved

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 371 of 1067

MT6359 PMIC Datasheet Confidential A 000000D4

GPIO_MODE1_SET

GPIO_MODE1 Register SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

GPIO_MODE1_SET W1 0 0 0 0

0

0

0

0

0

0

Bit(s) 15:0

0

0

0

0

0

Name GPIO_MODE1_SET

000000D6

Description 1'b0: Not set 1'b1: Set

GPIO_MODE1_CLR

GPIO_MODE1 Register CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

GPIO_MODE1_CLR W1 0 0 0 0

0

0

0

0

0

0

Bit(s) 15:0

0

0

0

0

0

Name GPIO_MODE1_CLR

000000D8

Description 1'b0: Not clear 1'b1: Clear

GPIO_MODE2

GPIO Mode Control Register 2

00000249

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

GPIO11_MODE

GPIO10_MODE

RW 0

Bit(s) 11:9

Name GPIO11_MODE

8:6

GPIO10_MODE

MediaTek Proprietary and Confidential.

0

GPIO9_MODE

RW 1

0

0

GPIO8_MODE

RW 1

0

0

RW 1

0

0

1

Description Selects GPIO 11 mode 0: GPIO11 (IO) 1: AUD_DATA_MOSI2 (I) 2: Reserved 3: Reserved 4: Reserved 5: Reserved 6: TEST_IN6(I) 7: TEST_OUT6(O) Selects GPIO 10 mode 0: GPIO10 (IO) © 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 372 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

5:3

GPIO9_MODE

2:0

GPIO8_MODE

000000DA

Description 1: AUD_DAT_MOSI1 (I) 2: Reserved 3: Reserved 4: Reserved 5: Reserved 6: TEST_IN5(I) 7: TEST_OUT5(O) Selects GPIO 9 mode 0: GPIO9 (IO) 1: AUD_DAT_MOSI0 (I) 2: Reserved 3: Reserved 4: Reserved 5: Reserved 6: TEST_IN4(I) 7: TEST_OUT4(O) Selects GPIO 8 mode 0: GPIO8 (IO) 1:AUD_CLK_MOSI (I) 2: Reserved 3: Reserved 4: Reserved 5: TEST_CK0 (I) 6: Reserved 7: Reserved

GPIO_MODE2_SET

GPIO_MODE2 Register SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

GPIO_MODE2_SET W1 0 0 0 0

0

0

0

0

0

0

Bit(s) 15:0

0

0

0

0

0

Name GPIO_MODE2_SET

000000DC

Description 1'b0: Not set 1'b1: Set

GPIO_MODE2_CLR

GPIO_MODE2 Register CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

GPIO_MODE2_CLR W1 0 0 0 0

0

0

0

0

0

0

0

0

MediaTek Proprietary and Confidential.

0

0

0

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 373 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 15:0

Name GPIO_MODE2_CLR

000000DE

Description 1'b0: Not clear 1'b1: Clear

GPIO_MODE3

GPIO Mode Control Register 3

00000249

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

GPIO15_MODE

GPIO14_MODE

GPIO13_MODE

RW

RW

RW

0

Bit(s) 11:9

Name GPIO15_MODE

8:6

GPIO14_MODE

5:3

GPIO13_MODE

2:0

GPIO12_MODE

0

1

0

0

1

0

0

GPIO12_MODE RW

1

0

0

1

Description Selects GPIO 15 mode 0: GPIO13 (IO) 1: AUD_DAT_MISO0 (O) 2: Reserved 3: Dummy 0 4: VOW_DAT_MISO (O) 5: Reserved 6: TEST_IN10(I) 7: TEST_OUT10(O) Selects GPIO 14 mode 0: GPIO15 (IO) 1: AUD_NLE_MOSI1 (I) 2: AUD_CLK_MISO (O) 3: Reserved 4: Reserved 5: Reserved 6: TEST_IN9(I) 7: TEST_OUT9(O) Selects GPIO 13 mode 0: GPIO15 (IO) 1: AUD_NLE_MOSI0 (I) 2: AUD_SYNC_MISO (O) 3: Reserved 4: Reserved 5: Reserved 6: TEST_IN8(I) 7: TEST_OUT8(O) Selects GPIO 12 mode 0: GPIO12 (IO) 1:AUD_SYNC_MOSI (I) 2: Reserved 4: Reserved 5: Reserved 6: TEST_IN7 (I) 7: TEST_OUT7 (O)

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 374 of 1067

MT6359 PMIC Datasheet Confidential A 000000E0

GPIO_MODE3_SET

GPIO_MODE3 Register SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

GPIO_MODE3_SET W1 0 0 0 0

0

0

0

0

0

0

Bit(s) 15:0

0

0

0

0

0

Name GPIO_MODE3_SET

000000E2

Description 1'b0: Not set 1'b1: Set

GPIO_MODE3_CLR

GPIO_MODE3 Register CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

GPIO_MODE3_CLR W1 0 0 0 0

0

0

0

0

0

0

Bit(s) 15:0

0

0

0

0

0

Name GPIO_MODE3_CLR

000000E4

Description 1'b0: Not clear 1'b1: Clear

GPIO_MODE4

GPIO Mode Control Register 4

00000249

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

GPIO19_MODE

GPIO18_MODE

RW 0

Bit(s) 11:9

Name GPIO19_MODE

8:6

GPIO18_MODE

MediaTek Proprietary and Confidential.

0

GPIO17_MODE

RW 1

0

0

GPIO16_MODE

RW 1

0

0

RW 1

0

0

1

Description Selects GPIO 19 mode 0: GPIO18 (IO) 1: SCP_VREQ_VAO (I) 2: Reserved 3: Reserved 4: Reserved 5: TEST_CK3 6: Reserved 7: Reserved Selects GPIO 18 mode 0: GPIO18 (IO) © 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 375 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

5:3

GPIO17_MODE

2:0

GPIO16_MODE

000000E6

Description 1: HOMEKEY (I) 2: Reserved 3: Reserved 4: Reserved 5: TEST_CK2 6: Reserved 7: Reserved Selects GPIO 17 mode 0: GPIO14 (IO) 1: AUD_DAT_MISO2 (O) 2: Reserved 3: Reserved 4: Reserved 5: Reserved 6: TEST_IN11(I) 7: TEST_OUT11(O) Selects GPIO 16 mode 0: GPIO14 (IO) 1: AUD_DAT_MISO1 (O) 2: Reserved 3: Dummy 1 4: VOW_CLK_MISO (O) 5: TEST_CK1 (I) 6: Reserved 7: Reserved

GPIO_MODE4_SET

GPIO_MODE4 Register SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

GPIO_MODE4_SET W1 0 0 0 0

0

0

0

0

0

0

Bit(s) 15:0

0

0

0

0

0

Name GPIO_MODE4_SET

000000E8

Description 1'b0: Not set 1'b1: Set

GPIO_MODE4_CLR

GPIO_MODE4 Register CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

GPIO_MODE4_CLR W1 0 0 0 0

0

0

0

0

0

0

0

0

MediaTek Proprietary and Confidential.

0

0

0

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 376 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 15:0

Name GPIO_MODE4_CLR

000000EA

Description 1'b0: Not clear 1'b1: Clear

GPIO_RSV

GPIO Reserved

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0 GPIO_ RSV RW

Name Type Reset Bit(s) 0

0

Name GPIO_RSV

00000100

Description

TOP2_ID

TOP2 Design ID Register

00002A00

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000102

Description

TOP2_REV0

TOP2 Design Revision Register 0

00001000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 377 of 1067

MT6359 PMIC Datasheet Confidential A 00000104

TOP2_DSN_DBI

TOP2 Design Bank Information Register

00005800

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000106

Description

TOP2_DSN_DXI

TOP2 Design Extra Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

20

19

18

17

16

4

3

2

1

0

1

0

0

00000108

Description

TOP_PAM0

Bit Name Type Reset

31

30

29

Bit Name Type Reset

15

14

13

Bit(s) 15:8 7:0

0

0

TOP Parameter 0 27

26

25

24

23

22

21

12

11

10

9

8

7

6

5

TOP_RST_OFFSET RU 1 1

1

1

Name TOP_RST_OFFSET TOP_CLK_OFFSET

0000010A 31

30

29

Bit Name Type Reset

15

14

13

0

0

MediaTek Proprietary and Confidential.

0

1

0

0

0

0

TOP_CLK_OFFSET RU 0 1

Description Reset setting offset Clock setting offset

TOP_PAM1

Bit Name Type Reset

00003E0C

28

TOP Parameter 1

00000188

28

27

26

25

24

23

22

21

12

11

10

9

8

7

6

5

TOP_INT_LEN RU 0 0

0

0

1

1

0

0

20

19

18

17

16

4

3

2

1

0

0

0

0

TOP_INT_OFFSET RU 0 1

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 378 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 15:8 7:0

Name TOP_INT_LEN TOP_INT_OFFSET

0000010C Bit Name Type Reset

Description Interrupt setting length Interrupt setting offset

TOP_CKPDN_CON0 31

30

29

14 13 RG_RT RG_PM RG_RT C26M_ U128K Name C32K_C CK_PD _CK_P K_PDN N DN RW RW RW Type

Bit

Reset

15

0

0

27

12

11

1

Name RG_RTC32K_CK_PDN

14

RG_RTC26M_CK_PDN

13

RG_PMU128K_CK_PDN

11

RG_FQMTR_CK_PDN

10

RG_FQMTR_32K_CK_PDN

9

RG_PMU32K_CK_PDN

8

RG_CK_PDN_RSV2

7

RG_SPI_CK_PDN

6

RG_CK_PDN_RSV1

5

RG_CK_PDN_RSV0

4

RG_EFUSE_CK_PDN

2

RG_INTRP_CK_PDN

26

25

24

23

22

21

00002C20 20

10 9 8 7 6 5 4 RG_FQ RG_PM RG_FQ RG_CK RG_SPI RG_CK RG_CK RG_EF MTR_3 U32K_ MTR_C _PDN_ _CK_P _PDN_ _PDN_ USE_CK 2K_CK_ CK_PD K_PDN RSV2 DN RSV1 RSV0 _PDN PDN N RW RW RW RW RW RW RW RW 1

Bit(s) 15

MediaTek Proprietary and Confidential.

TOP_CKPDN Control Register 0

28

1

0

0

0

0

1

0

19

18

17

16

3

2

1

0

RG_INT RP_CK_ PDN

RG_SC K32K_C K_PDN

RW

RW

0

0

Description Powers down RTC32K CK 0: Power on 1: Power down Powers down PMU_26M_CK 0: Power on 1: Power down Powers down PMU128K_CK 0: Power on 1: Power down Powers down FQMTR CK 0: Power on 1: Power down Powers down FQMTR_32K_CK 0: Power on 1: Power down Powers down PMU32K_CK 0: Power on 1: Power down Powers down reserved 0: Power on 1: Power down Powers down SPI_CK 0: Power on 1: Power down Powers down reserved 0: Power on 1: Power down Powers down reserved 0: Power on 1: Power down Powers down EFUSE_CK 0: Power on 1: Power down Powers down INTRP_CK 0: Power on 1: Power down

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 379 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 0

Name RG_SCK32K_CK_PDN

0000010E

Description Powers down SCK32K_CK 0: Power on 1: Power down

TOP_CKPDN_CON0_SET

TOP_CKPDN_CON0 Register SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

TOP_CKPDN_CON0_SET W1 0 0 0 0

0

0

0

0

0

0

Bit(s) 15:0

0

0

0

0

0

Name TOP_CKPDN_CON0_SET

00000110

Description Sets up TOP_CKPDN_CON0 1'b0: Not set 1'b1: Set

TOP_CKPDN_CON0_CLR

TOP_CKPDN_CON0 Register CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

TOP_CKPDN_CON0_CLR W1 0 0 0 0

0

0

0

0

0

0

20

19

18

17

Bit(s) 15:0

0

0

0

0

0

Name TOP_CKPDN_CON0_CLR

00000112

Description Clears TOP_CKPDN_CON0 1'b0: Not clear 1'b1: Clear

TOP_CKPDN_CON1

TOP_CKPDN Control Register 1

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

Bit

15

14

13

12

11

10

9

8

7

6

5

Name Type Reset Bit(s) 4

0000001A

4 3 2 1 0 RG_PC RG_BG RG_TRI RG_RT RG_RT HR_TES R_TEST M_128 C32K_1 C32K_1 T_CK_P _CK_P K_CK_P V8_1_P V8_0_P DN DN DN DN DN RW RW RW RW RW 1

Name RG_PCHR_TEST_CK_PDN

MediaTek Proprietary and Confidential.

16

1

0

1

0

Description Powers down BGR_TEST_CK

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 380 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

3

RG_BGR_TEST_CK_PDN

2

RG_TRIM_128K_CK_PDN

1

RG_RTC32K_1V8_1_PDN

0

RG_RTC32K_1V8_0_PDN

00000114

Description 0: Power on 1: Power down Powers down BGR_TEST_CK 0: Power on 1: Power down Powers down TRIM_128K_CK 0: Power on 1: Power down Powers down RTC32K_1V8_1 0: Power on 1: Power down Powers down RTC32K_1V8_0 0: Power on 1: Power down

TOP_CKPDN_CON1_SET

TOP_CKPDN_CON1 Register SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

TOP_CKPDN_CON1_SET W1 0 0 0 0

0

0

0

0

0

0

Bit(s) 15:0

0

0

0

0

0

Name TOP_CKPDN_CON1_SET

00000116

Description Sets up TOP_CKPDN_CON1 1'b0: Not set 1'b1: Set

TOP_CKPDN_CON1_CLR

TOP_CKPDN_CON1 Register CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

TOP_CKPDN_CON1_CLR W1 0 0 0 0

0

0

0

0

0

0

Bit(s) 15:0

0

0

0

0

Name TOP_CKPDN_CON1_CLR

MediaTek Proprietary and Confidential.

0

Description Clears TOP_CKPDN_CON1 1'b0: Not clear 1'b1: Clear

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 381 of 1067

MT6359 PMIC Datasheet Confidential A 00000118

TOP_CKSEL_CON0

TOP_CKSEL Control Register 0

00000008

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10 RG_PM U32K_ CK_CKS EL RW

9

8

7

6

5

4

3

2

1

0

Name

RG_TOP_CKSEL_CON0_RSV

Type Reset Bit(s) 15:11 10

RW 0

0

0

0

0

RG_RTC_32K1V8_SEL

2:0

RG_FQMTR_CK_CKSEL

0000011A

RW

0

Name RG_TOP_CKSEL_CON0_RSV RG_PMU32K_CK_CKSEL

3

RG_RT C_32K1 RG_FQMTR_CK_CKSEL V8_SEL RW

1

0

0

0

Description Selects TOP clock Selects RTC 32K clock 1'b0: R_RTC_32K_CK 1'b1: R_PMU32K_CK Selects RTC_32K1V8_CK clock 1'b0: R_PMU32K_CK 1'b1: R_RTC32K_CK Selects FQMTR_CK clock 3'b000: R_RTC_26M_CK 3'b001: R_XOSC32_CK_DETECTION 3'b010: R_EOSC32_CK 3'b011: R_RTC32K_CK 3'b100: R_DCXO1M_CK 3'b101: R_RTC_TICK_SEC 3'b11x: R_PMU32K_CK

TOP_CKSEL_CON0_SET

TOP_CKSEL_CON0 Register SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

TOP_CKSEL_CON0_SET W1 0 0 0 0

0

0

0

0

0

0

Bit(s) 15:0

0

0

0

0

Name TOP_CKSEL_CON0_SET

MediaTek Proprietary and Confidential.

0

Description Sets up TOP_CKSEL_CON0 1'b0: Not set 1'b1: Set

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 382 of 1067

MT6359 PMIC Datasheet Confidential A 0000011C

TOP_CKSEL_CON0_CLR

TOP_CKSEL_CON0 Register CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

TOP_CKSEL_CON0_CLR W1 0 0 0 0

0

0

0

0

0

0

Bit(s) 15:0

0

0

0

0

0

Name TOP_CKSEL_CON0_CLR

0000011E

Description Clears TOP_CKSEL_CON0 1'b0: Not clear 1'b1: Clear

TOP_CKSEL_CON1

TOP_CKSEL Control Register 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000120

Description

TOP_CKSEL_CON1_SET

TOP_CKSEL_CON1 Register SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

TOP_CKSEL_CON1_SET W1 0 0 0 0

0

0

0

0

0

0

Bit(s) 15:0

0

0

0

0

Name TOP_CKSEL_CON1_SET

MediaTek Proprietary and Confidential.

0

Description Sets up TOP_CKSEL_CON2 1'b0: Not set 1'b1: Set

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 383 of 1067

MT6359 PMIC Datasheet Confidential A 00000122

TOP_CKSEL_CON1_CLR

TOP_CKSEL_CON1 Register CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

TOP_CKSEL_CON1_CLR W1 0 0 0 0

0

0

0

0

0

0

17

Bit(s) 15:0

0

0

0

0

0

Name TOP_CKSEL_CON1_CLR

00000124

Description Clears TOP_CKSEL_CON2 1'b0: Not clear 1'b1: Clear

TOP_CKDIVSEL_CON0

TOP_CKDIVSEL Control Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

Name

TOP_CKDIVSEL_CON0_RSV

Type Reset Bit(s) 15:10 1:0

RW 0

0

0

0

0

0

Name TOP_CKDIVSEL_CON0_RSV RG_REG_CK_DIVSEL

00000126

TOP_CKDIVSEL_CON0_SET

TOP_CKDIVSEL_CON0 Register SET

30

29

28

27

26

Bit Name Type Reset

15

14

13

12

11

Bit(s) 15:0

0

0

Name TOP_CKDIVSEL_CON0_SET

MediaTek Proprietary and Confidential.

0

0

Selects REG_CK divider 2'b00: DIV1 2'b01: DIV2 2'b10: DIV4 2'b11: DIV8

31

0

1 0 RG_REG_CK_DI VSEL RW

Description

Bit Name Type Reset

0

16

0

00000000

25

24

23

22

21

20

19

18

17

16

10

9

8

7

6

5

4

3

2

1

0

0

TOP_CKDIVSEL_CON0_SET W1 0 0 0 0

0

0

0

0

0

0

Description Sets up TOP_CKDIVSEL_CON0 1'b0: Not set 1'b1: Set

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 384 of 1067

MT6359 PMIC Datasheet Confidential A 00000128

TOP_CKDIVSEL_CON0_CLR

TOP_CKDIVSEL_CON0 Register CLR

Bit Name Type Reset

31

30

29

28

27

26

Bit Name Type Reset

15

14

13

12

11

10

Bit(s) 15:0

0

0

0

0

0

0

Name TOP_CKDIVSEL_CON0_CLR

0000012A

00000000

25

24

23

22

21

20

19

18

17

16

9

8

7

6

5

4

3

2

1

0

TOP_CKDIVSEL_CON0_CLR W1 0 0 0 0

0

0

0

0

0

0

19

18

17

16

1

0

Description Clears TOP_CKDIVSEL_CON0 1'b0: Not clear 1'b1: Clear

TOP_CKHWEN_CON0

TOP_CKHWEN Control Register 0

0000002C

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

Bit

15

14

13

12

11

10

9

8

7

6

5 RG_RT C26M_ CK_PD N_HWE N RW

4

Name Type Reset

1

Bit(s) 5

Name RG_RTC26M_CK_PDN_HWEN

3

RG_EINT_32K_CK_PDN_HWEN

2

RG_EFUSE_CK_PDN_HWEN

0000012C

TOP_CKHWEN_CON0_SET 30

29

28

27

26

Bit Name Type Reset

15

14

13

12

11

MediaTek Proprietary and Confidential.

0

0

1

TOP_CKHWEN_CON0 Register SET

31

0

1

Description RTC26M_CK power down control 0: SW mode 1: HW mode EINT_32K_CK power down control 0: SW mode 1: HW mode EFUSE_CK power down control 0: SW mode 1: HW mode

Bit Name Type Reset

0

3 2 RG_EIN RG_EF T_32K_ USE_CK CK_PD _PDN_ N_HWE HWEN N RW RW

0

00000000

25

24

23

22

21

20

19

18

17

16

10

9

8

7

6

5

4

3

2

1

0

0

TOP_CKHWEN_CON0_SET W1 0 0 0 0

0

0

0

0

0

0

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 385 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 15:0

Name TOP_CKHWEN_CON0_SET

0000012E

Description Sets up TOP_CKHWEN_CON0 1'b0: Not set 1'b1: Set

TOP_CKHWEN_CON0_CLR

TOP_CKHWEN_CON0 Register CLR

Bit Name Type Reset

31

30

29

28

27

26

Bit Name Type Reset

15

14

13

12

11

Bit(s) 15:0

0

0

0

0

0

24

23

22

21

20

19

18

17

16

10

9

8

7

6

5

4

3

2

1

0

0

TOP_CKHWEN_CON0_CLR W1 0 0 0 0

0

0

0

0

0

0

Name TOP_CKHWEN_CON0_CLR

00000130

00000000

25

Description Clears TOP_CKHWEN_CON0 1'b0: Not clear 1'b1: Clear

TOP_CKTST_CON0

TOP_CKTST Control Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000132

Description

TOP_CKTST_CON1

TOP_CKTST Control Register 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 386 of 1067

MT6359 PMIC Datasheet Confidential A 00000134

TOP_CLK_CON0

TOP_CLK Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000136

Description

TOP_CLK_CON1

TOP_CLK Register 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000138

Description

TOP_CLK_DCM0

TOP_CLK DCM Control Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000013A

Description

TOP_RST_CON0

TOP_RST Control Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 387 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

0000013C

Description

TOP_RST_CON0_SET

TOP_RST_CON0 Register SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000013E

Description

TOP_RST_CON0_CLR

TOP_RST_CON0 Register CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000140

Description

TOP_RST_CON1

TOP_RST Control Register 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 388 of 1067

MT6359 PMIC Datasheet Confidential A 00000142

TOP_RST_CON1_SET

TOP_RST_CON1 Register SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000144

Description

TOP_RST_CON1_CLR

TOP_RST_CON1 Register CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000146

Description

TOP_RST_CON2

TOP_RST Control Register 2

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000148

Description

TOP_RST_CON3

TOP_RST Control Register 3

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 389 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

0000014A

Description

TOP_RST_MISC

Reset Control Misc

00000200

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

Bit

15

14

13

12

11

10

9

8

7

6

5

4

RG_W DTRST B_DEB

Name Type Reset Bit(s) 5

RW

19

3 2 WDTRS WDTRS TB_STA TB_STA TUS_CL TUS R RW RO

0

Name RG_WDTRSTB_DEB

3

WDTRSTB_STATUS_CLR

2

WDTRSTB_STATUS

0

RG_WDTRSTB_EN

0000014C

18

0

0

17

16

1

0 RG_W DTRST B_EN RW 0

Description Enables WDTRSTB debounce 1'b0: No debounce 1'b1: Add debounce 1.6ms Write 1 to clear WDTRSTB_STATUS. 0: No function 1: Clear WDTRSTB_STATUS WDTRSTB reset status 1'b0: Not occur 1'b1: Occur WDTRSTB (external watchdog) reset from AP 1'b0: Disable 1'b1: Enable

TOP_RST_MISC_SET

Reset Control Misc SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

TOP_RST_MISC_SET W1 0 0 0 0

0

0

0

0

0

0

Bit(s) 15:0

0

0

0

0

Name TOP_RST_MISC_SET

MediaTek Proprietary and Confidential.

0

Description Sets up TOP_RST_MISC 1'b0: Not set 1'b1: Set

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 390 of 1067

MT6359 PMIC Datasheet Confidential A 0000014E

TOP_RST_MISC_CLR

Reset Control Misc CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

TOP_RST_MISC_CLR W1 0 0 0 0

0

0

0

0

0

0

Bit(s) 15:0

0

0

0

0

0

Name TOP_RST_MISC_CLR

00000150

Description Clears TOP_RST_MISC 1'b0: Not clear 1'b1: Clear

TOP_RST_STATUS

TOP_RST_STATUS Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000152

Description

TOP_RST_STATUS_SET

TOP_RST_STATUS Register SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 391 of 1067

MT6359 PMIC Datasheet Confidential A 00000154

TOP_RST_STATUS_CLR

TOP_RST_STATUS Register CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000156

Description

TOP_CLK_EN_MON

TOP CLK 26M 1M CKEN MON

000033F7

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000158

Description

TOP2_ELR_NUM

TOP2 Number of ELR Register

00000004

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000015A

Description

TOP2_ELR0

TOP2 ELR 0 Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 392 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

0000015C

Description

TOP2_ELR1

TOP2 ELR 1 Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000180

Description

TOP3_ID

TOP3 Design ID Register

00002B00

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000182

Description

TOP3_REV0

TOP3 Design Revision Register 0

00001000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 393 of 1067

MT6359 PMIC Datasheet Confidential A 00000184

TOP3_DSN_DBI

TOP3 Design Bank Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000186

Description

TOP3_DSN_DXI

TOP3 Design Extra Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000188

Description

MISC_TOP_INT_CON0

TOP INT Control Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0 RG_INT _EN_S PI_CM D_ALE RT RW

Name Type Reset Bit(s) 0

0

Name RG_INT_EN_SPI_CMD_ALERT

MediaTek Proprietary and Confidential.

Description SPI_CMD_ALERT interrupt enable 0: Not issue interrupt 1: Issue interrupt

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 394 of 1067

MT6359 PMIC Datasheet Confidential A 0000018A

MISC_TOP_INT_CON0_SET

TOP INT Control Register 0 SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000018C

Description

MISC_TOP_INT_CON0_CLR

TOP INT Control Register 0 CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000018E

Description

MISC_TOP_INT_MASK_CON0 MISC INT Mask Control Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0 RG_INT _MASK _SPI_C MD_AL ERT RW

Name Type Reset Bit(s) 0

0

Name RG_INT_MASK_SPI_CMD_ALERT

MediaTek Proprietary and Confidential.

Description Masks SPI_CMD_ALERT interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 395 of 1067

MT6359 PMIC Datasheet Confidential A 00000190

MISC_TOP_INT_MASK_CON0 MISC TOP INT Mask Control Register 0 SET _SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000192

Description

MISC_TOP_INT_MASK_CON0 MISC TOP INT Mask Control Register 0 CLR _CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000194

Description

MISC_TOP_INT_STATUS0

MISC TOP INT Status Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0 RG_INT _STAT US_SPI _CMD_ ALERT W1C

Name

Type Reset Bit(s) 0

0

Name RG_INT_STATUS_SPI_CMD_ALERT

MediaTek Proprietary and Confidential.

Description SPI_CMD_ALERT interrupt status 0: No interrupt issued 1: Interrupt issued

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 396 of 1067

MT6359 PMIC Datasheet Confidential A 00000196

MISC_TOP_INT_RAW_STATU MISC TOP INT Raw Status Register 0 S0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0 RG_INT _RAW_ STATU S_SPI_ CMD_ ALERT RO

Name

Type Reset Bit(s) 0

0

Name Description RG_INT_RAW_STATUS_SPI_CMD_ALERT SPI_CMD_ALERT raw interrupt status 0: No interrupt issued 1: Interrupt issued

00000198

TOP_INT_MASK_CON0

TOP_INT_MASK Control Register 0

Bit Name Type Reset

31

30

29

28

27

26

25

Bit

15

14

13

12

11

10

9

Name Type Reset

24

Name RG_INT_MASK_MISC_TOP

7

RG_INT_MASK_AUD_TOP

6

RG_INT_MASK_XPP_TOP

5

RG_INT_MASK_HK_TOP

4

RG_INT_MASK_BM_TOP

3

RG_INT_MASK_SCK_TOP

MediaTek Proprietary and Confidential.

22

21

000001FF 20

19

18

17

16

8 7 6 5 4 3 2 1 0 RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT _MASK _MASK _MASK _MASK _MASK _MASK _MASK _MASK _MASK _MISC_ _AUD_ _XPP_T _HK_T _BM_T _SCK_T _PSC_T _LDO_ _BUCK TOP TOP OP OP OP OP OP TOP _TOP RW RW RW RW RW RW RW RW RW 1

Bit(s) 8

23

1

1

1

1

1

1

1

1

Description Interrupt mask for TOP 0: Unmask interrupt 1: Mask interrupt Interrupt mask for AUD 0: Unmask interrupt 1: Mask interrupt Interrupt mask for XPP 0: Unmask interrupt 1: Mask interrupt Interrupt mask for HK 0: Unmask interrupt 1: Mask interrupt Interrupt mask for BM 0: Unmask interrupt 1: Mask interrupt Interrupt mask for SCK 0: Unmask interrupt 1: Mask interrupt

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 397 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 2

Name RG_INT_MASK_PSC_TOP

1

RG_INT_MASK_LDO_TOP

0

RG_INT_MASK_BUCK_TOP

0000019A

Description Interrupt mask for LDO 0: Unmask interrupt 1: Mask interrupt Interrupt mask for BUCK 0: Unmask interrupt 1: Mask interrupt Sets up TOP_INTM_CON0 0: Unmask interrupt 1: Mask interrupt

TOP_INT_MASK_CON0_SET

TOP_INT_MASK Control Register SET

Bit Name Type Reset

31

30

29

28

27

26

Bit Name Type Reset

15

14

13

12

11

10

Bit(s) 15:0

0

0

0

0

0

0

Name TOP_INT_MASK_CON0_SET

0000019C

TOP_INT_MASK_CON0_CLR 30

29

28

27

26

Bit Name Type Reset

15

14

13

12

11

10

Bit(s) 15:0

0

0

Name TOP_INT_MASK_CON0_CLR

MediaTek Proprietary and Confidential.

23

22

21

20

19

18

17

16

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

TOP_INT_MASK_CON0_SET W1 0 0 0 0

TOP_INT_MASK Control Register CLR

31

0

24

Description Clears TOP_INTM_CON0 1'b0: Not set 1'b1: Set

Bit Name Type Reset

0

00000000

25

0

0

00000000

25

24

23

22

21

20

19

18

17

16

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

TOP_INT_MASK_CON0_CLR W1 0 0 0 0

Description 1'b0: Not clear 1'b1: Clear

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 398 of 1067

MT6359 PMIC Datasheet Confidential A 0000019E

TOP_INT_STATUS0

TOP_INT_STATUS Register 0

Bit Name Type Reset

31

30

29

28

27

26

25

Bit

15

14

13

12

11

10

9

Name Type Reset

24

Name INT_STATUS_MISC_TOP

7

INT_STATUS_AUD_TOP

6

INT_STATUS_XPP_TOP

5

INT_STATUS_HK_TOP

4

INT_STATUS_BM_TOP

3

INT_STATUS_SCK_TOP

2

INT_STATUS_PSC_TOP

1

INT_STATUS_LDO_TOP

0

INT_STATUS_BUCK_TOP

MediaTek Proprietary and Confidential.

22

00000000 21

20

19

18

17

16

8 7 6 5 4 3 2 1 0 INT_ST INT_ST INT_ST INT_ST INT_ST INT_ST INT_ST INT_ST INT_ST ATUS_ ATUS_ ATUS_ ATUS_ ATUS_ ATUS_S ATUS_ ATUS_L ATUS_ MISC_T AUD_T XPP_T HK_TO BM_TO CK_TO PSC_T DO_TO BUCK_ OP OP OP P P P OP P TOP RO RO RO RO RO RO RO RO RO 0

Bit(s) 8

23

0

0

0

0

0

0

0

0

Description Interrupt mask for TOP 0: Unmask interrupt 1: Mask interrupt Interrupt mask for AUD 0: Unmask interrupt 1: Mask interrupt Interrupt mask for XPP 0: Unmask interrupt 1: Mask interrupt Interrupt mask for HK 0: Unmask interrupt 1: Mask interrupt Interrupt mask for BM 0: Unmask interrupt 1: Mask interrupt Interrupt mask for SCK 0: Unmask interrupt 1: Mask interrupt Interrupt mask for LDO 0: Unmask interrupt 1: Mask interrupt Interrupt mask for BUCK 0: Unmask interrupt 1: Mask interrupt Sets up TOP_INTM_CON0 0: Unmask interrupt 1: Mask interrupt

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 399 of 1067

MT6359 PMIC Datasheet Confidential A 000001A0

TOP_INT_RAW_STATUS0

TOP_INT_RAQ_STATUS Register 0

Bit Name Type Reset

31

30

29

28

27

26

25

Bit

15

14

13

12

11

10

9

Name

Type Reset

24

Name INT_RAW_STATUS_MISC_TOP

7

INT_RAW_STATUS_AUD_TOP

6

INT_RAW_STATUS_XPP_TOP

5

INT_RAW_STATUS_HK_TOP

4

INT_RAW_STATUS_BM_TOP

3

INT_RAW_STATUS_SCK_TOP

2

INT_RAW_STATUS_PSC_TOP

1

INT_RAW_STATUS_LDO_TOP

0

INT_RAW_STATUS_BUCK_TOP

000001A2

22

21

00000000 20

19

18

17

16

8 7 6 5 4 3 2 1 0 INT_RA INT_RA INT_RA INT_RA INT_RA INT_RA INT_RA INT_RA INT_RA W_STA W_STA W_STA W_STA W_STA W_STA W_STA W_STA W_STA TUS_M TUS_A TUS_X TUS_B TUS_H TUS_B TUS_SC TUS_PS TUS_LD ISC_TO UD_TO PP_TO UCK_T K_TOP M_TOP K_TOP C_TOP O_TOP P P P OP RO RO RO RO RO RO RO RO RO 0

Bit(s) 8

23

0

0

0

0

0

0

0

0

Description Interrupt mask for TOP 0: Unmask interrupt 1: Mask interrupt Interrupt mask for AUD 0: Unmask interrupt 1: Mask interrupt Interrupt mask for XPP 0: Unmask interrupt 1: Mask interrupt Interrupt mask for HK 0: Unmask interrupt 1: Mask interrupt Interrupt mask for BM 0: Unmask interrupt 1: Mask interrupt Interrupt mask for SCK 0: Unmask interrupt 1: Mask interrupt Interrupt mask for LDO 0: Unmask interrupt 1: Mask interrupt Interrupt mask for BUCK 0: Unmask interrupt 1: Mask interrupt Sets up TOP_INTM_CON0 0: Unmask interrupt 1: Mask interrupt

TOP_INT_CON0

TOP_INT_CONTROL Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 400 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

000001A4

Description

TOP_DCXO_CKEN_SW

DCXO CKEN SW Mode Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000001A6

Description

PMRC_CON0

PMRC Control Register 0

00005FFF

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000001A8

Description

PMRC_CON0_SET

PMRC CON0 Register SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 401 of 1067

MT6359 PMIC Datasheet Confidential A 000001AA

PMRC_CON0_CLR

PMRC CON0 Register CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000001AC

Description

PMRC_CON1

PMRC Control Register 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000001AE

Description

PMRC_CON1_SET

PMRC CON1 Register SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000001B0

Description

PMRC_CON1_CLR

PMRC CON1 Register CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 402 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

000001B2

Description

PMRC_CON2

PMRC Control Register 2

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000380

Description

PLT0_ID

PLT0 Design ID Register

00002C00

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000382

Description

PLT0_REV0

PLT0 Design Revision Register 0

00001000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 403 of 1067

MT6359 PMIC Datasheet Confidential A 00000384

PLT0_REV1

PLT0 Design Revision Register 1

00003200

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000386

Description

PLT0_DSN_DXI

PLT0 Design Extra Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000388

Description

TOP_CLK_TRIM

TOP_CLK_TRIM Register

000000C0

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

20

19

18

17

16

4

3

2

1

0

0

0

0

Bit(s) 14:9

DA_OSC_128K_TRIM RO 0

0

0

0

Name DA_OSC_128K_TRIM

0000038A

Description 128 kHz OSC trimming bit

OTP_CON0

OTP Control Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

MediaTek Proprietary and Confidential.

RG_OTP_PA RW 0

0

0

0

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

0

Page 404 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 7:0

Name RG_OTP_PA

0000038C

Description OTP PA

OTP_CON1

OTP Control Register 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

Bit(s) 7:0

RG_OTP_PDIN RW 0

Name RG_OTP_PDIN

0000038E

0

0

0

0

0

0

17

16

1

0

Description OTP PDIN

OTP_CON2

OTP Control Register 2

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

Bit(s) 1:0

RG_OTP_PTM RW 0

Name RG_OTP_PTM

00000390

Description OTP PTM

OTP_CON3

OTP Control Register 3

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

Bit(s) 1:0

0

17

16

1

0

RG_OTP_PWE RW 0

Name RG_OTP_PWE

MediaTek Proprietary and Confidential.

0

Description OTP PWE

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 405 of 1067

MT6359 PMIC Datasheet Confidential A 00000392

OTP_CON4

OTP Control Register 4

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0 RG_OT P_PPR OG RW

Name Type Reset Bit(s) 0

0

Name RG_OTP_PPROG

00000394

Description OTP PPROG

OTP_CON5

OTP Control Register 5

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0 RG_OT P_PWE _SRC RW

Name Type Reset Bit(s) 0

0

Name RG_OTP_PWE_SRC

00000396

Description Selects OTP write (fusing) PWE source 0: From I/O pad 1: From register

OTP_CON6

OTP Control Register 6

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

RG_OTP_PROG_PKEY RW 0 0 0 0

0

0

0

0

0

0

Bit(s) 15:0

0

0

0

0

Name RG_OTP_PROG_PKEY

MediaTek Proprietary and Confidential.

0

Description OTP write (fusing) match key

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 406 of 1067

MT6359 PMIC Datasheet Confidential A 00000398

OTP_CON7

OTP Control Register 7

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

RG_OTP_RD_PKEY RW 0 0 0 0

0

0

0

0

0

0

Bit(s) 15:0

0

0

0

0

0

Name RG_OTP_RD_PKEY

0000039A

Description OTP read match key

OTP_CON8

OTP Control Register 8

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0 RG_OT P_RD_ TRIG RW

Name Type Reset Bit(s) 0

0

Name RG_OTP_RD_TRIG

0000039C

Description Triggers OTP SW read

OTP_CON9

OTP Control Register 9

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0 RG_RD _RDY_ BYPAS S RW

Name Type Reset Bit(s) 0

0

Name RG_RD_RDY_BYPASS

MediaTek Proprietary and Confidential.

Description Bypasses OTP read ready delay 0: Not bypass 1: Bypass

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 407 of 1067

value

MT6359 PMIC Datasheet Confidential A 0000039E

OTP_CON10

OTP Control Register 10

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0 RG_SKI P_OTP _OUT RW

Name Type Reset Bit(s) 0

0

Name RG_SKIP_OTP_OUT

000003A0

Description Skips reading from EFUSE macro 0: Not skip 1: Skip

OTP_CON11

OTP Control Register 11

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0 RG_OT P_RD_ SW RW

Name Type Reset Bit(s) 0

0

Name RG_OTP_RD_SW

000003A2

Description SW trigger read mode 0: Not SW trigger read mode 1: SW trigger read mode

OTP_CON12

OTP Control Register 12

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

RG_OTP_DOUT_SW RO 0 0 0 0

0

0

0

0

0

0

0

0

0

0

0

Bit(s) 15:0

MediaTek Proprietary and Confidential.

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Page 408 of 1067

MT6359 PMIC Datasheet Confidential A 000003A4

OTP_CON13

OTP Control Register 13

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2 RG_OT P_RD_ ACK RO

1

0 RG_OT P_RD_ BUSY RO

Name Type Reset Bit(s) 2 0

0

Name RG_OTP_RD_ACK RG_OTP_RD_BUSY

000003A6

0

Description OTP read ack OTP busy status

OTP_CON14

OTP Control Register 14

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

Bit(s) 6:0

RG_OTP_PA_SW RO 0

Name RG_OTP_PA_SW

000003A8

0

0

0

0

0

Description Current SW trigger read row

TOP_TMA_KEY

Top Specific Write Protection Key

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 409 of 1067

MT6359 PMIC Datasheet Confidential A 000003AA

TOP_MDB_CONF0

TOP MDB Configuration 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000003AC

Description

TOP_MDB_CONF1

TOP MDB Configuration 1

0000FFFF

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000003AE

Description

TOP_MDB_CONF2

TOP MDB Configuration 2

00000005

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000003B0

Description

TOP_MDB_CONF3

TOP MDB Configuration 3

00000300

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 410 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

000003B2

Description

PLT0_ELR_NUM

PLT0 Number of ELR Register

00000002

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000003B4

Description

PLT0_ELR0

OSC 128k TRIM

00000037

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000400

Description

SPISLV_ID

SPISLV Design ID Register

00002D00

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 411 of 1067

MT6359 PMIC Datasheet Confidential A 00000402

SPISLV_REV0

SPISLV Design Revision Register 0

00001100

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000404

Description

SPISLV_REV1

SPISLV Design Revision Register 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000406

Description

SPISLV_DSN_DXI

SPISLV Design Extra Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000408

Description

RG_SPI_CON0

SPI Control Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 412 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

0000040A

Description

RG_SPI_RECORD0

SPI Record Control Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000040C

Description

DEW_DIO_EN

Dual I/O Mode Enable

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000040E

Description

DEW_READ_TEST

Read Test

00005AA5

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

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Page 413 of 1067

MT6359 PMIC Datasheet Confidential A 00000410

DEW_WRITE_TEST

Write Test

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000412

Description

DEW_CRC_SWRST

CRC_SWRST

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000414

Description

DEW_CRC_EN

CRC Enable

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000416

Description

DEW_CRC_VAL

CRC Value

00000083

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 414 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00000418

Description

DEW_CIPHER_KEY_SEL

CIPHER Key Selection

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000041A

Description

DEW_CIPHER_IV_SEL

CIPHER Initial Vector Selection

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000041C

Description

DEW_CIPHER_EN

CIPHER Engine Enable

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

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Page 415 of 1067

MT6359 PMIC Datasheet Confidential A 0000041E

DEW_CIPHER_RDY

CIPHER Data Ready

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000420

Description

DEW_CIPHER_MODE

CIPHER Mode Enable

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000422

Description

DEW_CIPHER_SWRST

CIPHER Soft Reset

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000424

Description

DEW_RDDMY_NO

Read Dummy Cycle Number

0000000F

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 416 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00000426

Description

RG_SPI_CON2

SPI Control Register 2

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000428

Description

RECORD_CMD0

SPI Record Command 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000042A

Description

RECORD_CMD1

SPI Record Command 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 417 of 1067

MT6359 PMIC Datasheet Confidential A 0000042C

RECORD_CMD2

SPI Record Command 2

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000042E

Description

RECORD_CMD3

SPI Record Command 3

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000430

Description

RECORD_CMD4

SPI Record Command 4

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000432

Description

RECORD_CMD5

SPI Record Command 5

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 418 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00000434

Description

RECORD_WDATA0

SPI Record Data 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000436

Description

RECORD_WDATA1

SPI Record Data 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000438

Description

RECORD_WDATA2

SPI Record Data 2

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 419 of 1067

MT6359 PMIC Datasheet Confidential A 0000043A

RECORD_WDATA3

SPI Record Data 3

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000043C

Description

RECORD_WDATA4

SPI Record Data 4

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000043E

Description

RECORD_WDATA5

SPI Record Data 5

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000440

Description

RG_SPI_CON9

SPI Control Register 9

00000002

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 420 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00000442

Description

RG_SPI_CON10

SPI Control Register 10

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000444

Description

RG_SPI_CON11

SPI Control Register 11

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000446

Description

RG_SPI_CON12

SPI Control Register 12

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 421 of 1067

MT6359 PMIC Datasheet Confidential A 00000448

RG_SPI_CON13

SPI Control Register 13

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000044A

Description

SPISLV_KEY

SPISLV Specific Write Protection Key

0000BADE

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000044C

Description

INT_TYPE_CON0

Interrupt Type Configuration 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000044E

Description

INT_TYPE_CON0_SET

Interrupt Type Configuration 0 Set

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 422 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00000450

Description

INT_TYPE_CON0_CLR

Interrupt Type Configuration 0 Clear

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000452

Description

INT_STA

SPI Interrupt Status

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000454

Description

RG_SPI_CON1

SPI Control Register 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 423 of 1067

MT6359 PMIC Datasheet Confidential A 00000456

TOP_SPI_CON0

Top SPI Domain Control Register 0

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000458

Description

TOP_SPI_CON1

Top SPI Domain Control Register 1

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000500

Description

SCK_TOP_DSN_ID

SCK TOP Design ID Register

00003700

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000502

Description

SCK_TOP_DSN_REV0

SCK TOP Design Revision Register 0

00001000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 424 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00000504

Description

SCK_TOP_DBI

SCK TOP Design Bank Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000506

Description

SCK_TOP_DXI

SCK TOP Design Extra Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000508

Description

SCK_TOP_TPM0

SCK_TOP Parameter 0

00002214

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 425 of 1067

MT6359 PMIC Datasheet Confidential A 0000050A

SCK_TOP_TPM1

SCK_TOP Parameter 1

00000128

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000050C

Description

SCK_TOP_CON0

SCK_TOP_CON0 Control Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000050E

Description

SCK_TOP_CON1

SCK_TOP_CON1 Control Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000510

Description

SCK_TOP_TEST_OUT

SCK_TOP Test Output

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 426 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00000512

Description

SCK_TOP_TEST_CON0

SCK_TOP Test Control Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

20

19

18

17

00000514

Description

SCK_TOP_CKPDN_CON0

SCK_CKPDN Control Register 0

Bit Name Type Reset

31

30

29

28

27

26

25

24

Bit

15

14

13

12

11

10

9

8

Name Type Reset Bit(s) 8

7

RG_RTC_2SEC_OFF_DET_PDN

6

RG_RTC_26M_CK_PDN

5

RG_RTC_32K_CK_PDN

4

RG_RTC_MCLK_PDN

3

RG_RTC_SEC_32K_CK_PDN

2

RG_RTC_EOSC32_CK_PDN

1

RG_EOSC_CALI_TEST_CK_PDN

MediaTek Proprietary and Confidential.

22

21

0000004B 16

7 6 5 4 3 2 1 0 RG_RT RG_EO RG_RT RG_RT RG_RT RG_RT RG_RT RG_RT C_2SEC RG_RT SC_CAL C_INTR C_26M C_32K_ C_SEC_ C_EOSC C_SEC_ _OFF_ C_MCL I_TEST P_CK_P _CK_P CK_PD 32K_CK 32_CK_ MCLK_ DET_P K_PDN _CK_P DN DN N _PDN PDN PDN DN DN RW RW RW RW RW RW RW RW RW 0

Name RG_RTC_INTRP_CK_PDN

23

0

1

0

0

1

0

1

1

Description Powers down RTC_2SEC_OFF_DET 0: Power on 1: Power down Powers down RTC_26M_CK 0: Power on 1: Power down Powers down RTC_26M_CK 0: Power on 1: Power down Powers down RTC_32K_CK 0: Power on 1: Power down Powers down RTC_MCLK 0: Power on 1: Power down Powers down RTC_SEC_32K_CK 1: Power down Powers down RTC_EOSC32_CK 0: Power on 1: Power down Powers down EOSC_CALI_TEST_CK

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 427 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

0

Name

Description 0: Power on 1: Power down Powers down RTC_SEC_MCLK 0: Power on 1: Power down

RG_RTC_SEC_MCLK_PDN

00000516

SCK_TOP_CKPDN_CON0_SET SCK_CKPDN Control Register 0 SET

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

Bit(s) 7:0

00000000

21

20

19

18

17

16

5

4

3

2

1

0

0

SCK_TOP_CKPDN_CON0_SET W1 0

Name SCK_TOP_CKPDN_CON0_SET

00000518

0

0

0

0

0

0

Description Sets up SCK_TOP_CKPDN_CON0 1'b0: Not set 1'b1: Set

SCK_TOP_CKPDN_CON0_CLR SCK_CKPDN Control Register 0 CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

Bit(s) 7:0

SCK_TOP_CKPDN_CON0_CLR W1 0

Name SCK_TOP_CKPDN_CON0_CLR

MediaTek Proprietary and Confidential.

0

0

0

0

0

Description Clears SCK_TOP_CKPDN_CON0 1'b0: Not clear 1'b1: Clear

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 428 of 1067

MT6359 PMIC Datasheet Confidential A 0000051A

SCK_TOP_CKHWEN_CON0

SCK_CKHWEN Control Register 0

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

Bit

15

14

13

12

11

10

9

8

7

6

5

Name

RG_RTC_CLK_PDN_HWEN_RSV_0

Type Reset

RG_RTC_CLK_PDN_HWEN_RSV_1

RW 0

0

0

0

0

Bit(s) 15:10

Name RG_RTC_CLK_PDN_HWEN_RSV_0

9:5

RG_RTC_CLK_PDN_HWEN_RSV_1

4

RG_RTC_INTRP_CK_PDN_HWEN

3

RG_RTC_SEC_MCLK_PDN_HWEN

2

RG_RTC_SEC_32K_CK_PDN_HWEN

1

RG_RTC_MCLK_PDN_HWEN

0

RG_RTC_26M_CK_PDN_HWEN

0000051C

0

1

RW 1

1

1

19

18

31

30

29

28

27

26

Bit Name Type Reset

15

14

13

12

11

10

0

0

0

Name SCK_TOP_CKHWEN_CON_SET

MediaTek Proprietary and Confidential.

0

16

4 3 2 1 0 RG_RT RG_RT RG_RT RG_RT RG_RT C_INTR C_SEC_ C_SEC_ C_26M C_MCL P_CK_P MCLK_ 32K_CK _CK_P K_PDN DN_H PDN_H _PDN_ DN_H _HWEN WEN WEN HWEN WEN RW RW RW RW RW 1 0 0 0 1

SCK_TOP_CKHWEN_CON0_SE SCK_CKHWEN_CON Register 0 SET T

0

17

Description RESERVED_0 0: SW mode 1: HW mode RESERVED_1 0: SW mode 1: HW mode RESERVED_1 0: SW mode 1: HW mode RTC_SEC_MCLK power down control 0: SW mode 1: HW mode RTC_SEC_32K_CK power down control 0: SW mode 1: HW mode RTC_MCLK power down control 0: SW mode 1: HW mode RTC_26M_CK power down control 0: SW mode 1: HW mode

Bit Name Type Reset

Bit(s) 15:0

1

000003F1 20

0

00000000

25

24

23

22

21

20

19

18

17

16

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

SCK_TOP_CKHWEN_CON_SET W1 0 0 0 0

Description Sets up SCK_CKHWEN_CON 1'b0: Not set 1'b1: Set

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 429 of 1067

MT6359 PMIC Datasheet Confidential A 0000051E

SCK_TOP_CKHWEN_CON0_CL SCK_CKHWEN_CON Register 0 CLR R

Bit Name Type Reset

31

30

29

28

27

26

Bit Name Type Reset

15

14

13

12

11

10

Bit(s) 15:0

0

0

0

0

0

0

Name SCK_TOP_CKHWEN_CON_CLR

00000520

00000000

25

24

23

22

21

20

19

18

17

16

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

SCK_TOP_CKHWEN_CON_CLR W1 0 0 0 0

Description Clears SCK_CKHWEN_CON 1'b0: Not clear 1'b1: Clear

SCK_TOP_CKTST_CON

SCK_CKTST Control Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000522

Description

SCK_TOP_RST_CON0

SCK_TOP_RST Control Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 430 of 1067

MT6359 PMIC Datasheet Confidential A 00000524

SCK_TOP_RST_CON0_SET

SCK_TOP_RST_CON Register 0 SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000526

Description

SCK_TOP_RST_CON0_CLR

SCK_TOP_RST_CON Register 0 CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000528

Description

SCK_TOP_INT_CON0

SCK_TOP INT Control Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0 RG_INT _EN_R TC RW

Name Type Reset Bit(s) 0

0

Name RG_INT_EN_RTC

MediaTek Proprietary and Confidential.

Description Enables RTC interrupt 0: Not issue interrupt 1: Issue interrupt

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 431 of 1067

MT6359 PMIC Datasheet Confidential A 0000052A

SCK_TOP_INT_CON0_SET

SCK_TOP INT Control Register 0 SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000052C

Description

SCK_TOP_INT_CON0_CLR

SCK_TOP INT Control Register 0 CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000052E

Description

SCK_TOP_INT_MASK_CON0 SCK_TOP INT Mask Control Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0 RG_INT _MASK _RTC RW

Name Type Reset Bit(s) 0

0

Name RG_INT_MASK_RTC

MediaTek Proprietary and Confidential.

Description Masks RTC interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 432 of 1067

MT6359 PMIC Datasheet Confidential A 00000530

SCK_TOP_INT_MASK_CON0_ SCK_TOP INT Mask Control Register 0 SET SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000532

Description

SCK_TOP_INT_MASK_CON0_ SCK_TOP INT Mask Control Register 0 CLR CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000534

Description

SCK_TOP_INT_STATUS0

SCK_TOP INT Status Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0 RG_INT _STAT US_RT C W1C

Name Type Reset Bit(s) 0

0

Name RG_INT_STATUS_RTC

MediaTek Proprietary and Confidential.

Description RTC interrupt status 0: No interrupt issued 1: Interrupt issued

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 433 of 1067

MT6359 PMIC Datasheet Confidential A 00000536

SCK_TOP_INT_RAW_STATUS0 SCK_TOP INT Raw Status Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000538

Description

SCK_TOP_INT_MISC_CON

SCK_TOP INT MISC Control Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0 SCK_T OP_PO LARITY RW

Name Type Reset Bit(s) 0

0

Name SCK_TOP_POLARITY

0000053A

Description Inverts interrupt source polarity 0: Not invert interrupt source 1: Invert interrupt source

EOSC_CALI_CON0

RTC EOSC CALI Control Registers 0

000000C0

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 434 of 1067

MT6359 PMIC Datasheet Confidential A 0000053C

EOSC_CALI_CON1

RTC EOSC CALI Control Registers 1

00000002

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000053E

Description

RTC_MIX_CON0

RTC Analog test Control Registers 0

00000788

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000540

Description

RTC_MIX_CON1

RTC Analog Test Control Registers 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000542

Description

RTC_MIX_CON2

RTC Analog Test Control Registers 2

00000200

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 435 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00000544

Description

RTC_DIG_CON0

RTC Digital Test Control Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000546

Description

FQMTR_CON0

Frequency Meter Control Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000548

Description

FQMTR_CON1

Frequency Meter Control Register 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

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Page 436 of 1067

MT6359 PMIC Datasheet Confidential A 0000054A

FQMTR_CON2

Frequency Meter Control Register 2

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000054C

Description

XO_BUF_CTL0

XO SOC Buffer Control Register

00000006

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000054E

Description

XO_BUF_CTL1

XO WCN Buffer Control Register

00000078

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000550

Description

XO_BUF_CTL2

XO NFC Buffer Control Register

00000100

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 437 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00000552

Description

XO_BUF_CTL3

XO CEL Buffer Control Register

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000554

Description

XO_BUF_CTL4

XO EXT Buffer Control Register

00000200

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000556

Description

XO_CONN_BT0

XO CONN BT Control Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

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Page 438 of 1067

MT6359 PMIC Datasheet Confidential A 00000580

RTC_DSN_ID

RTC Design ID Register

00003000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000582

Description

RTC_DSN_REV0

RTC Design Revision Register 0

00003010

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000584

Description

RTC_DBI

RTC Design Bank Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000586

Description

RTC_DXI

RTC Design Extra Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 439 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00000588

Description

RTC_BBPU

Baseband Power Up

Bit Name Type Reset

31

30

29

28

27

26

25

24

Bit

15

14

13

12

11

10

9

8

0

0

0

Name

KEY_BBPU

Type Reset Bit(s) 15:8 7

WO 0

0

0

0

0

Name KEY_BBPU ALARM_STATUS

6

CBUSY

5

RELOAD

4

CLRPKY

0000058A

23

00000000 22

21

20

7 6 5 4 ALARM RELOA _STAT CBUSY CLRPKY D US RO RO WO WO 0

0

0

19

18

17

16

3

2

1

0

0

Description A bus write is acceptable only when KEY_BBPU = 0x43. Records ALARM status 1: ALARM had happened. The read/write channels between RTC/Core is busy. This bit indicates high after software program sequence to anyone of RTC data registers and enable the transfer by RTC_WRTGR = 1. It will be high after the reset from low to high because of RTC reload process. Reloads the values from RTC domain to core domain RTC will reload synchronizing the data from RTC to core when reset from 0 to 1. This bit can be treated as a debug bit. Clears powerkey1 and powerkey2 at the same time In some cases, software may clear powerkey1 & powerkey2. BBWAKEUP depends on the matching specific patterns of powerkey1 and powerkey2. If any one of powerkey1 or powerkey2 or BBPU is cleared, BBWAKEUP will be low immediately. Software cannot program other control bits without power. By programming RTC_BBPU with CLRPKY = 1 and BBPU = 0 condition, RTC can clear powerkey1, powerkey2 and BBPU at the same moment.

RTC_IRQ_STA

RTC IRQ Status

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s) 3

Name LPSTA

1

TCSTA

LPSTA

MediaTek Proprietary and Confidential.

TCSTA ALSTA

RO

RO

RO

0

0

0

Description Indicates IRQ status and whether or not LPD is asserted 0: No IRQ occurs; the 32K clock is good. 1: IRQ occurs; the 32K clock stops. This can be masked by LP_EN or cleared by initializing LPD. Indicates IRQ status and whether or not the tick condition has been met 0: No IRQ occurs; the tick condition has not been met. 1: IRQ occurs; the tick condition has been met.

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Page 440 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 0

Name ALSTA

0000058C

Description Indicates IRQ status and whether or not the alarm condition has been met 0: No IRQ occurs; the alarm condition has not been met. 1: IRQ occurs; the alarm condition has been met.

RTC_IRQ_EN

RTC IRQ Enable

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

Name Type Reset Bit(s) 3

2 1

ONESHOT TC_EN

0

AL_EN

0000058E

RTC_CII_EN 30

29

28

27

26

Bit

15

14

13

12

11

10

Bit(s) 9 8 7 6 5 4

25

MediaTek Proprietary and Confidential.

0

0

24

23

22

21

00000000 20

19

18

17

16

9 8 7 6 5 4 3 2 1 0 SECCII_ SECCII_ SECCII_ DOWCI DOMCI YEACII MTHCII HOUCII MINCII SECCII 1_8 1_4 1_2 I I RW RW RW RW RW RW RW RW RW RW 0

Name SECCII_1_8 SECCII_1_4 SECCII_1_2 YEACII MTHCII DOWCII

0

Counter Increment IRQ Enable

31

Type Reset

16

Description Enables the control bit for IRQ generation if low power is detected (32K clock off) 0: Disable IRQ generations 1: Enable the LPD Controls automatic reset of AL_EN and TC_EN Enables the control bit for IRQ generation if the tick condition has been met 0: Disable IRQ generations 1: Enable tick time match interrupt. Clear the interrupt when ONESHOT is high upon generation of the corresponding IRQ. Enables the control bit for IRQ generation if the alarm condition has been met 0: Disable IRQ generations 1: Enable alarm time match interrupt. Clear the interrupt when ONESHOT is high upon generation of the corresponding IRQ.

Bit Name Type Reset Name

17

2 1 0 ONESH LP_EN TC_EN AL_EN OT RW RW RW RW 0

Name LP_EN

18

0

0

0

0

0

0

0

0

0

Description Set the bit to 1 to activate the IRQ at each 1/8 of a second update. Set the bit to 1 to activate the IRQ at each 1/4 of a second update. Set the bit to 1 to activate the IRQ at each 1/2 of a second update. Set the bit to 1 to activate the IRQ at each year update. Set the bit to 1 to activate the IRQ at each month update. Set the bit to 1 to activate the IRQ at each day-of-week update.

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Page 441 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 3 2 1 0

Name DOMCII HOUCII MINCII SECCII

00000590

Description Set the bit to 1 to activate the IRQ at each day-of-month update. Set the bit to 1 to activate the IRQ at each hour update. Set the bit to 1 to activate the IRQ at each minute update. Set this bit to 1 to activate the IRQ at each second update.

RTC_AL_MASK

RTC Alarm Mask

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

Bit

15

14

13

12

11

10

9

8

7

Name Type Reset

22

Name YEA_MSK

5

MTH_MSK

4

DOW_MSK

3

DOM_MSK

2

HOU_MSK

1

MIN_MSK

0

SEC_MSK

MediaTek Proprietary and Confidential.

20

19

18

17

16

6 5 4 3 2 1 0 YEA_M MTH_ DOW_ DOM_ HOU_ MIN_M SEC_M SK MSK MSK MSK MSK SK SK RW RW RW RW RW RW RW 0

Bit(s) 6

21

0

0

0

0

0

0

Description 0: Condition (RTC_TC_YEA = RTC_AL_YEA) is checked to generate the alarm signal. 1: Condition (RTC_TC_YEA = RTC_AL_YEA) is masked, i.e. the value of RTC_TC_YEA does not affect the alarm IRQ generation. 0: Condition (RTC_TC_MTH = RTC_AL_MTH) is checked to generate the alarm signal. 1: Condition (RTC_TC_MTH = RTC_AL_MTH) is masked, i.e. the value of RTC_TC_MTH does not affect the alarm IRQ generation. 0: Condition (RTC_TC_DOW = RTC_AL_DOW) is checked to generate the alarm signal. 1: Condition (RTC_TC_DOW = RTC_AL_DOW) is masked, i.e. the value of RTC_TC_DOW does not affect the alarm IRQ generation. 0: Condition (RTC_TC_DOM = RTC_AL_DOM) is checked to generate the alarm signal. 1: Condition (RTC_TC_DOM = RTC_AL_DOM) is masked, i.e. the value of RTC_TC_DOM does not affect the alarm IRQ generation. 0: Condition (RTC_TC_HOU = RTC_AL_HOU) is checked to generate the alarm signal. 1: Condition (RTC_TC_HOU = RTC_AL_HOU) is masked, i.e. the value of RTC_TC_HOU does not affect the alarm IRQ generation. 0: Condition (RTC_TC_MIN = RTC_AL_MIN) is checked to generate the alarm signal. 1: Condition (RTC_TC_MIN = RTC_AL_MIN) is masked, i.e. the value of RTC_TC_MIN does not affect the alarm IRQ generation. 0: Condition (RTC_TC_SEC = RTC_AL_SEC) is checked to generate the alarm signal. 1: Condition (RTC_TC_SEC = RTC_AL_SEC) is masked, i.e. the value of RTC_TC_SEC does not affect the alarm IRQ generation.

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Page 442 of 1067

MT6359 PMIC Datasheet Confidential A 00000592

RTC_TC_SEC

RTC Seconds Time Counter Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

Bit(s) 5:0

18

17

16

3

2

1

0

0

TC_SECOND RW 0

Name TC_SECOND

00000594

0

0

0

0

19

18

17

16

3

2

1

0

0

Description Second initial value for time counter Range: 0~59

RTC_TC_MIN

RTC Minutes Time Counter Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

Bit(s) 5:0

19

TC_MINUTE RW 0

Name TC_MINUTE

00000596

0

0

0

0

Description Minute initial value for time counter Range: 0~59

RTC_TC_HOU

RTC Hours Time Counter Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

Bit(s) 4:0

TC_HOUR RW 0

Name TC_HOUR

MediaTek Proprietary and Confidential.

0

0

Description Hour initial value for time counter Range: 0~23

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Page 443 of 1067

MT6359 PMIC Datasheet Confidential A 00000598

RTC_TC_DOM

RTC Day-of-month Time Counter Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

Bit(s) 4:0

18

17

16

2

1

0

0

0

TC_DOM RW 0

Name TC_DOM

0000059A

0

0

Description Day-of-month initial value for time counter The day-of-month maximum value depends on the leap year condition, i.e. 2 LSB of year time counter are 0.

RTC_TC_DOW

RTC Day-of-week Time Counter Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

Bit(s) 2:0

16

1

0

TC_DOW RW

Name TC_DOW

0000059C

0

0

0

18

17

16

2

1

0

Description Day-of-week initial value for time counter Range: 1~7

RTC_TC_MTH

RTC Month Time Counter Register

00000700

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

Bit(s) 3:0

17

TC_MONTH RW 0

Name TC_MONTH

MediaTek Proprietary and Confidential.

0

0

0

Description Month initial value for time counter Range: 1~12

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Page 444 of 1067

MT6359 PMIC Datasheet Confidential A 0000059E

RTC_TC_YEA

RTC Year Time Counter Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

Bit(s) 6:0

17

16

3

2

1

0

0

0

0

RW 0

Name TC_YEAR

RTC_AL_SEC 31

30

29

0

0

RTC Second Alarm Setting Register 28

27

26

25

24

23

22

15 14 13 12 11 10 9 8 7 6 K_EOS BBPU_ BBPU_ BBPU_ BBPU_ BBPU_ C32_VT 2SEC_S 2SEC_S BBPU_2SEC_M AUTO_ RTC_LPD_OPT 2SEC_E 2SEC_C Name CXO_O TAT_ST TAT_CL ODE PDN_S N K_SEL N_SEL A EAR EL RW RW RO WO RW RW RW RW Type 0 0 0 0 0 0 0 0 0 0 Reset

Bit(s) 15

Name K_EOSC32_VTCXO_ON_SEL

14:13

RTC_LPD_OPT

BBPU_2SEC_STAT_STA

MediaTek Proprietary and Confidential.

0

Description Year initial value for time counter Range: 0~127 (2000~2127) Software can bias the year as multiples of 4 for the internal leap-year formula. Here are 3 examples: 2000-2127, 1972~2099, 1904~2031.To simplify, RTC hardware treats all 4-multiple as leap years. If the range you define includes non-leap 4-multiple year (e.g. 2100), you have to adjust to correct date by yourselves (e.g. change Feb. 29th, 2100 to Mar. 1st, 2100). We suggest you bias the range large than 1900 and less than 2100 to evade the manual adjustment, i.e. the bias values are suggested to be in the range of [-28, -96], that are (1972~2099) ~ (1904~2031). The formal leap formula: if year modulo 400 is 0 then leap else if year modulo 100 is 0 then no_leap else if year modulo 4 is 0 then leap else no_leap

Bit

12

18

TC_YEAR

000005A0 Bit Name Type Reset

19

00000000

21

20

19

18

17

16

5

4

3

2

1

0

0

0

AL_SECOND RW 0

0

0

0

Description The bit will only be valid when EMBCK_SEL_MODE is set to EMB_K_EOSC32 mode. 0: VTCXO controlled by HW 1: VTCXO always on f32k_ck_alive setting (rstb of LPSTA_RAW) Depends on XOSC LPDETB (xosc32_ck_alive) or EOSC LPDETB (eosc32_ck_alive). 2'b11: Always 1 2'b10: xosc32_ck_alive (triggered when clock stops) 2'b01: eosc32_ck_alive (triggered when VRTC low-V) 2'b00: xosc32_ck_alive & eosc32_ck_alive Bbwakeup SPAR status

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Page 445 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

11 10:9

Name

BBPU_2SEC_STAT_CLEAR BBPU_2SEC_MODE

8

BBPU_2SEC_EN

7

BBPU_2SEC_CK_SEL

6

BBPU_AUTO_PDN_SEL

5:0

Description 1'b0: SPAR reboot had not happened before. 1'b1: SPAR reboot had happened before. Clears Bbwakeup SPAR event Read back as BBPU_2SEC_STAT. Selects the battery removal time to trigger powermode 2'b11: Never power down 2'b10: 1.6 sec power down after battery is removed 2'b01: 0.6 sec power down after battery is removed 2'b00: 0.1 sec power down after battery is removed Selects power mode 0: Legacy mode 1: 2 sec power down mode Selects the clock source in the power down mode 0: embck_ck 1: eosc32_ck Selects the SPAR reboot method 0: Original SPAR reboot feature 1: Support both SPAR reboot and auto_pdn Second value of alarm counter setting Range: 0~59

AL_SECOND

000005A2

RTC_AL_MIN

RTC Minute Alarm Setting Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

Bit(s) 5:0

AL_MINUTE RW 0

Name AL_MINUTE

000005A4

0

0

0

18

17

16

2

1

0

0

0

Description Minute value of alarm counter setting Range: 0~59

RTC_AL_HOU

Bit Name Type Reset

31

30

29

Bit Name Type Reset

15

14

13

Bit(s) 15:8

0

RTC Hour Alarm Setting Register

00000000

28

27

26

25

24

23

22

21

20

19

12

11

10

9

8

7

6

5

4

3

NEW_SPARE0

AL_HOUR

RW 0

0

Name NEW_SPARE0

MediaTek Proprietary and Confidential.

0

0

RW 0

0

0

0

0

0

0

Description NEW_SPARE0[7]: WO: Reset bat status by writing 1, auto cleared to 0 NEW_SPARE0[6]: RO: 0 = No bat now/1 = bat installed properly

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 446 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

4:0

Name

Description NEW_SPARE0[5]: RO: 0 = Battery always exists/1 = Battery has been removed NEW_SPARE0[4:0]: Battery removed time counter (unit: minute), stopped when counting to 5'd30, reset to 0 by SPARE0[7] Hour value of alarm counter setting Range: 0~23

AL_HOUR

000005A6

RTC_AL_DOM

RTC Day-of-month Alarm Setting Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

Bit(s) 15:8

4:0

NEW_SPARE1

AL_DOM

RW 0

0

Name NEW_SPARE1

AL_DOM

MediaTek Proprietary and Confidential.

0

0

RW 0

0

0

0

0

0

0

Description NEW_SPARE1[7:6]: RO: spar_state[1:0] 2'b00: ST_PWR_OFF 2'b01: ST_PWR_ON 2'b10: ST_PWR_ON2OFF 2'b11: ST_SPAR_EN NEW_SPARE1[5]: RO: additional_spar_en 1'b0: No spar happend 1'b1: Spar happened NEW_SPARE1[4]: RO: uvlo_except_sync 1'b0: The battery voltage is over the uvlo threshold. 1'b1: The battery voltage is under the uvlo threshold. NEW_SPARE1[3]: Reserved NEW_SPARE1[2]: Reserved NEW_SPARE1[1]: Reserved NEW_SPARE1[0]: RW: Enables ALARM signal to be clear by sysreset 1'b0: Disable 1'b1: Enable Day-of-month value of alarm counter setting The day-of-month maximum value depends on the leap year condition, i.e. 2 LSB of year time counter are 0.

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Page 447 of 1067

MT6359 PMIC Datasheet Confidential A 000005A8

RTC_AL_DOW

Bit Name Type Reset

31

30

29

Bit Name Type Reset

15

14

13

Bit(s) 15:8 7:5

2:0

0

0

27

26

25

24

12

11

10

9

8

29

Bit Name Type Reset

15

14

13

20

19

18

7

6

5

4

3

2

0

0

0

0

0

0

1

1

0

0

0

18

17

16

2

1

0

RTC Month Alarm Setting Register

00000000

28

27

26

25

24

23

22

21

20

19

12

11

10

9

8

7

6

5

4

3

AL_MONTH

0

RW 0

0

RTC_AL_YEA 31

30

29

Bit Name Type Reset

15

14

13

0

0

0

0

0

19

18

17

16

3

2

1

0

0

0

0

00000000

27

26

25

24

23

22

21

20

12

11

10

9

8

7

6

5

4

AL_YEAR

RW

MediaTek Proprietary and Confidential.

0

RTC Year Alarm Setting Register 28

RTC_K_EOSC_RSV 0

0

Description Reserved for specific purposes Month value of alarm counter setting Range: 1~12

Bit Name Type Reset

0

0

Description Reserved for specific purposes RTC EOSC calibration period setting 0x0: N/A 0x1: N/A 0x2: N/A 0x3: 1 sec 0x4: 2 sec 0x5: 4 sec 0x6: 8 sec 0x7: 16 sec Day-of-week value of alarm counter setting Range: 1~7

Name NEW_SPARE3 AL_MONTH

000005AC

1 RW

RW 0

16

RW

NEW_SPARE3 0

17

RW

RTC_AL_MTH 30

21

AL_DOW

AL_DOW

31

22

RG_EOSC_CALI_TD

0

Bit Name Type Reset

000000C0

23

NEW_SPARE2

Name NEW_SPARE2 RG_EOSC_CALI_TD

000005AA

Bit(s) 15:8 3:0

RTC Day-of-week Alarm Setting Register 28

0

0

RW 0

0

0

0

0

0

0

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0

Page 448 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 15:8

6:0

Name RTC_K_EOSC_RSV

AL_YEAR

000005AE Bit Name Type Reset

Description RTC_TEST_RSV[7:3]: Reserved RTC_TEST_RSV[2]: Indicates the system is normally or abnormally off. This bit will be checked when solution 2 is enabled and the system is off. 0: Abnormal off 1: Normal off RTC_TEST_RSV[1]: Enable solution 2 (EOSC calibration function is off when the system is off by the exception.) 0: Disable 1: Enable RTC_TEST_RSV[0]: RTC internal clock switch from dcxo32k_ck to eosc32k_ck configuration at 32kless platform 0: By ddlo or bwdt_ddlo 1: By system_resetb Year value of alarm counter setting Range: 0~127 (2000~2127)

RTC_OSC32CON 31

30

29

28

OSC32 Control 27

15 14 13 12 11 RTC_RE RTC_E RTC_E G_XOS RTC_GP_OSC32 OSC32_ OSC32_ Name C32_E _CON CHOP_ VCT_E NB EN N RW RW RW RW Type 0 0 0 0 0 Reset

Bit

Bit(s) 15

Name RTC_REG_XOSC32_ENB

14:13

RTC_GP_OSC32_CON

12

RTC_EOSC32_CHOP_EN

11

RTC_EOSC32_VCT_EN

10

RTC_GPS_CKOUT_EN

9

RTC_EMBCK_SEL_OPTION

MediaTek Proprietary and Confidential.

26

25

10 RTC_G PS_CK OUT_E N RW 1

24

00000400 23

22

21

9 8 7 6 5 RTC_E RTC_E RTC_X MBCK_ MBCK_ RTC_EMBCK_S OSC32_ SEL_OP SRC_SE EL_MODE ENB TION L RW RW RW RO 0 0 0 0 0

20

19

18

17

16

4

3

2

1

0

0

0

XOSCCALI

0

0

RW 0

Description XOSC32_ENB = 0 (32k crystal exists.) XOSC32_ENB = 1 (32k crystal does not exist.) EOSC32 RSV registers [14]: Select clock source to GPS [13]: Adjust the current when eosc is powered up Enables EOSC32 chopper When chopper is disabled, the current consumption can become lower. However, eosc32_ck might become unstable. When powerkeys do not match, the chopper will be enabled 0: Disable 1: Enable Enables EOSC32 threshold tracking 0: Disable 1: Enable Powers up EOSC When PAD_RTC_32K_2V8 is in buffer mode, the suggested value of this bit will be 1'b0 in order not to interfere the input clock. 1'b0: Power down 1'b1: Power up Embedded clock selection option after battery removal Note: Setting this bit to 1'b1 can extend the embedded clock life time after battery removal with a poorer clock source. EOSC32 can only keep the spec before LPD. After LPD, the frequency drift will become larger. 0: Embedded clock switch back to dcxo decided by (eosc32_ck_alive & powerkey_match)

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Page 449 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 8

7:6

5

4:0

Name

Description 1: Embedded clock switch back to dcxo decided by (powerkey_match) Selects embedded clock source in EMB_K_EOSC32 mode (RTC_OSC32CON[7:6] = 2'b01) 0: f32k_ck src = dcxo_ck 1: f32k_ck src = eosc32_ck Embedded clock source selection mode 00: EMB_HW (embedded HW) mode.Initial f32k_ck source = DCXO, and hardware automatically switches to EOSC32 at VBAT LV level 01: EMB_K_EOSC32 mode.Initial f32k_ck source = DCXO, and SW can configure the f32k_ck src by configuring RTC_OSC32CON[8] (EMBCK_SEL). HW automatically switches f32k_ck src to eosc32_ck at VBAT LV level 10: EMB_SW_DCXO mode (from bit6). f32_ck_src = dcxo_ck 11: EMB_SW_EOSC32 mode (from bit6). f32k_ck src = eosc32_ck Read: XOSC32_ENB Pin configuration of 32k crystal is used or not. 0: Use 32k crystal, f32k_ck source = XOSC32 1: No 32k crystal, f32k_ck source = embedded 32k sources (DCXO or EOSC32) Write: Manual clock during reloading, for debugging. SW can toggle this bit to generate SW clock. This clock is used as RTC registers' clock source only during the reload procedure. When power-on without 32k's existence, this bit can be used to finish the reload procedure, then SW will be capable of reading the RTC registers contents. Calibrates GM Default: 4'b0111 Suggested setting for 2nd step: 4'b0000 EOSC_CALI = Charging cap calibration

RTC_EMBCK_SRC_SEL

RTC_EMBCK_SEL_MODE

RTC_XOSC32_ENB

XOSCCALI

000005B0

RTC_POWERKEY1

RTC_POWERKEY1 Register

Bit Name Type Reset

31

30

29

28

27

26

25

Bit Name Type Reset

15

14

13

12

11

10

9

Bit(s) 15:0

0

0

0

0

0

0

Name RTC_POWERKEY1

000005B2

0

RTC_POWERKEY2 30

29

28

27

26

25

Bit Name Type Reset

15

14

13

12

11

10

9

MediaTek Proprietary and Confidential.

0

22

21

20

19

18

17

16

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

RTC_POWERKEY1 RW 0 0

RTC_POWERKEY2 Register

31

0

23

Description

Bit Name Type Reset

0

00000000

24

0

0

0

0

00000000

24

23

22

21

20

19

18

17

16

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

RTC_POWERKEY2 RW 0 0

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Page 450 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 15:0

Name RTC_POWERKEY2

000005B4

Description

RTC_PDN1

PDN1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

RTC_PDN1 RW 0 0

0

0

0

0

0

0

0

Bit(s) 15:0

0

0

0

0

0

0

Name RTC_PDN1

000005B6

0

Description Spare registers for software to keep power-on and power-off state information

RTC_PDN2

PDN2

Bit Name Type Reset

31

30

29

28

27

26

25

Bit Name Type Reset

15

14

13

12

11

10

9

Bit(s) 15:0

0

0

0

0

0

0

Name RTC_PDN2

000005B8

0

RTC_SPAR0 30

29

28

27

26

25

Bit Name Type Reset

15

14

13

12

11

10

9

Bit(s) 15:0

Name RTC_SPAR0

MediaTek Proprietary and Confidential.

22

21

20

19

18

17

16

8

7

6

5

4

3

2

1

0

RTC_PDN2 RW 0 0

0

0

0

0

0

0

0

Spare Register for Specific Purpose_0

31

0

23

Description Spare registers for software to keep power-on and power-off state information

Bit Name Type Reset

0

00000000 24

0

0

0

0

0

00000000

24

23

22

21

20

19

18

17

16

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

RTC_SPAR0 RW 0 0

Description Reserved for specific purposes

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Page 451 of 1067

MT6359 PMIC Datasheet Confidential A 000005BA

RTC_SPAR1

Spare Register for Specific Purpose_1

Bit Name Type Reset

31

30

29

28

27

26

25

Bit Name Type Reset

15

14

13

12

11

10

9

Bit(s) 15:0

0

0

0

0

0

0

Name RTC_SPAR1

000005BC

0

00000000

24

23

22

21

20

19

18

17

16

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

RTC_SPAR1 RW 0 0

Description Reserved for specific purposes

RTC_PROT

Lock/Unlock Scheme to Prevent RTC Miswriting

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

RTC_PROT RW 0 0

0

0

0

0

0

0

0

Bit(s) 15:0

0

0

Name RTC_PROT

MediaTek Proprietary and Confidential.

0

0

0

0

0

Description The RTC write interface is protected by RTC_PROT. Whether the RTC writing interface is enabled or not is decided by RTC_PROT contents. When RTC_POWERKEY1 and RTC_POWERKEY2 are not equal to the correct values, the RTC writing interface will always be enabled. However, when they match, perform the unlock flow to enable the writing interface. Unlock flow: 1 *RTC_PROT=0x586a; 2. *RTC_WRTGR=1; 3. While(*RTC_BBPU & 0x40) {}; // Timeout period: 120usec 4. *RTC_PROT=0x9136; 5. *RTC_WRTGR=1; 6. While(*RTC_BBPU & 0x40) {}; // Timeout period: 120usec Note: Always keep RTC in unlock state in power-on mode. Once the normal RTC content writing is completed, do not modify the RTC_PROT content to lock RTC. The RTC_PROT contents will be cleared automatically when powered off immediately.

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Page 452 of 1067

MT6359 PMIC Datasheet Confidential A 000005BE

RTC_DIFF 31

Bit Name Type Reset

30

15

14 K_EOS CALI_R C32_RS Name D_SEL V RW RW Type

Bit

Reset

0

One-time Calibration Offset 28

27

26

25

24

23

22

21

20

19

18

17

16

13

12 POWER _DETEC TED RO

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

Bit(s) 15

Name CALI_RD_SEL

14 12 11:0

K_EOSC32_RSV POWER_DETECTED RTC_DIFF

000005C0 Bit Name Type Reset

30

MediaTek Proprietary and Confidential.

0

0

0

Description Selects which RTC_CALI is to be read when read RTC_CALI register 0: Normal RTC_CALI 1: K_EOSC32_RTC_CALI Reserved bit for EMB_K_EOSC32 mode Read new powerkey match status Adjusts internal counter of RTC This affects once and returns to 0 when done. In some cases, you observe the RTC is faster or slower than the standard. Changing RTC_TC_SEC is coarse and may cause alarm problems. RTC_DIFF provides a finer time unit. An internal 15-bit counter accumulates in each 32768Hz clock. Entering a non-zero value into RTC_DIFF will cause the internal RTC counter to increase or decrease RTC_DIFF when RTC_DIFF changes to 0 again. RTC_DIFF is represented in 2's complement. For example, if you fill 0xfff into RTC_DIFF, the internal counter will decrease 1 when RTC_DIFF returns to 0. In other words, you can only use RTC_DIFF continuously if RTC_DIFF is equal to 0 now. Note: RTC_DIFF ranges from 0x800 (-2048) to 0x7fd (2045). 0x7ff & 0x7fe are forbidden to use.

Repeat Calibration Offset

00000000

26

25

24

23

22

21

20

19

18

17

16

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

Name K_EOSC32_OVERFLOW

CALI_WR_SEL

0

27

Bit(s) 15

14

0

28

Type Reset

Name

RW 0

29

15 14 K_EOS CALI_ C32_O WR_SE VERFL L OW RW RW 0 0

Bit

RTC_DIFF

RTC_CALI 31

00000000

29

RTC_CALI RW 0

0

0

0

0

0

0

0

Description EOSC32 calibration overflow (EOSC32 RTC_CALI update result from PMU rtc_eosc_cali module overflow) 1: Overflow Enables EOSC32 Cali value write Only takes effect in RTC_CALI write operation. 0: Normal RTC_CALI 1: K_EOSC32_RTC_CALI

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Page 453 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 13:0

Name RTC_CALI

000005C2

Description These registers provide a repeat calibration scheme. RTC_CALI provides two types of calibration: 1. 7-bit calibration capability in 8-second duration, i.e. 5-bit calibration capability in each second. RTC_CALI is represented in 2's complement, such that you can adjust RTC increasing or decreasing. Due to RTC_CALI is revealed in 8 seconds, the resolution is less than a 1/32768 clock. Avg. resolution: 1/32,768/8 = 3.81 us Avg. adjustment range: -0.244~0.240 ms/sec in 2's complement: 0x40~0x3f (-64~63) 2. 14-bit calibration capability in 1-second duration in EMB_K_EOSC32 mode (K_EOSC32_RTC_CALI). This type of usage is with resolution 1/32,768 = 30.52 us.

RTC_WRTGR

Enable Transfers from Core to RTC in Queue

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0 WRTG R WO

Name Type Reset Bit(s) 0

0

Name WRTGR

000005C4

0

0

0

Description Enables transfers from core to RTC After you modify all RTC registers you are to change, write 1 to RTC_WRTGR to trigger the transfer. The prior writing operations are queued at core power domain. The pending data will not be transferred to RTC domain until WRTGR = 1. After WRTGR = 1, the pending data will be transferred to RTC domain sequentially in order of register address, from low to high, e.g. RTC_BBPU -> RTC_IRQ_EN -> RTC_CII_EN -> RTC_AL_MASK -> RTC_TC_SEC -> .... CBUSY in RTC_BBPU is equal to 1 in the writing process. You can observe CBUSY to determine when the transmission will be completed.

RTC_CON

Other RTC Control Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

Name

LPSTA_ RAW

GPI

GE8

GE4

GPU

GSR

GOE

GPO

RW

RW

RW

RW

RW

RW

Type 0 Reset

0

Bit(s) 15

Name LPSTA_RAW

RO

RO 0

MediaTek Proprietary and Confidential.

GPEN GSMT RW

RW

16

0 VBAT_ F32KO XOSC3 EOSC32 CDBO LPRST LPSTA_ B 2_LPEN _LPEN RAW RW RW RW RW RW RW

0

Description Raw status of LP_STA Reinitialize LPD to clear this bit.

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Page 454 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

14 13 12 11 10

GPI GE8 GE4 GPU GPEN

9

GSMT

8

GSR

7

GOE

6

GPO

5

F32KOB

4

CDBO

3

LPRST

2

XOSC32_LPEN

1

EOSC32_LPEN

0

VBAT_LPSTA_RAW

MediaTek Proprietary and Confidential.

Description Note: This bit is always high before LPD initialization sequence after the first power-on. Input value of RTC_GPIO when GOE = 0 (input mode) Driving capability of RTC_GPIO. Driving capability of RTC_GPIO Pull-up of RTC_GPIO Enables pull of RTC_GPIO When GPEN = 1, RTC_GPIO will be pulled up if GPU = 1 and pulled down if GPU = 0. SMT of RTC_GPIO Control pin for Schmitt trigger circuit 0: RTC_GPIO Schmitt trigger off 1: RTC_GPIO Schmitt trigger on SR of RTC_GPIO Controls output slew rate. High asserted. SR = 0, slower slew. SR = 1. 0: RTC_GPIO higher slew output 1: RTC_GPIO slower slew output OE of RTC_GPIO 1'b0: RTC_GPIO is in input mode. 1'b1: RTC_GPIO is in output mode. Output value of RTC_GPIO when OE = 1 and COREDETB = 0 Selects to output pdn_flat_out signal or tick_sec to RTC_GPIO when OE = 1 and COREDETB = 1. Exports 32.768 kHz clock on RTC_GPIO in analog I/O mode 1'b0: Analog I/O mode 1'b1: Digital I/O mode Exports signal on RTC_GPIO 1'b0: Export GPO value 1'b1: When LPD_OPT = 1, export LPDETB. When LPD_OPT = 0 and GPO = 0, export pdn_flat_out signal. When LPD_OPT = 0 and GPO = 1, export tick_sec. Resets LPDETB This only takes effect when LPEN = 1. When LPEN = 0, the internal LPRST signal to XOSC32 is always 0. Enables XOSC LPDETB function LP initialization sequence to enable LPDETB: 1. Write XOSC32_LPEN = 1, LPRST = 0. Write RTC_WRTGR = 1. wait cbusy down. 2. Write XOSC32_LPEN = 1, LPRST = 1. Write RTC_WRTGR = 1. wait cbusy down. 3. Write XOSC32_LPEN = 1, LPRST = 0. Write RTC_WRTGR = 1. wait cbusy down. XOSC32 LPD will occur when 32k stops. It can be applied both at XOSC32 and EOSC32. Enables EOSC LPDETB function LP initialization sequence to enable LPDETB: 1. Write EOSC32_LPEN = 1, LPRST = 0. Write RTC_WRTGR = 1. wait cbusy down. 2. Write EOSC32_LPEN = 1, LPRST = 1. Write RTC_WRTGR = 1. wait cbusy down. 3. Write EOSC32_LPEN = 1, LPRST = 0. Write RTC_WRTGR = 1. wait cbusy down. EOSC32 LPD will occur when VRTC~=1.7V. It can be applied both at XOSC32 and EOSC32. Indicates the battery has been in LP state

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Page 455 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

000005C6

Description When the embedded hardware mode is used, the flag also indicates that hardware has switched the clock source from DCXO to EOSC32. Software needs to clear this bit for the use next time. Note: VBAT LP state = VBAT < 2.5V (DDLO) 0: VBAT has not been in LP state. 1: VBAT has been in LP state.

RTC_SEC_CTRL

Write Lock for RTC SEC Data

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000005C8

Description

RTC_INT_CNT

RTC Internal Counter

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000005CA

Description

RTC_SEC_DAT0

RTC SEC Data 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

MediaTek Proprietary and Confidential.

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Page 456 of 1067

MT6359 PMIC Datasheet Confidential A 000005CC

RTC_SEC_DAT1

RTC SEC Data 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000005CE

Description

RTC_SEC_DAT2

RTC SEC Data 2

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000600

Description

RTC_SEC_DSN_ID

RTC_SEC Design ID Register

00003200

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000602

Description

RTC_SEC_DSN_REV0

RTC_SEC Design Revision Register 0

00001000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 457 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00000604

Description

RTC_SEC_DBI

RTC_SEC Design Bank Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000606

Description

RTC_SEC_DXI

RTC_SEC Design Extra Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000608

Description

RTC_TC_SEC_SEC

Security RTC Seconds Time Counter Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

Bit(s) 5:0

TC_SECOND_SEC RW 0

Name TC_SECOND_SEC

MediaTek Proprietary and Confidential.

0

0

0

Description Second initial value for time counter Range: 0~59

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 458 of 1067

MT6359 PMIC Datasheet Confidential A 0000060A

RTC_TC_MIN_SEC

Security RTC Minutes Time Counter Register

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

Bit(s) 5:0

00000000

19

18

17

16

3

2

1

0

0

TC_MINUTE_SEC RW 0

Name TC_MINUTE_SEC

0000060C

0

0

0

0

Description Minute initial value for time counter Range: 0~59

RTC_TC_HOU_SEC

Security RTC Hours Time Counter Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

Bit(s) 4:0

TC_HOUR_SEC RW 0

Name TC_HOUR_SEC

0000060E

0

0

Description Hour initial value for time counter Range: 0~23

RTC_TC_DOM_SEC

Security RTC Day-of-month Time Counter Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

Bit(s) 4:0

TC_DOM_SEC RW 0

Name TC_DOM_SEC

MediaTek Proprietary and Confidential.

0

0

Description Day-of-month initial value for time counter The day-of-month maximum value depends on the leap year condition, i.e. 2 LSB of year time counter are 0.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 459 of 1067

MT6359 PMIC Datasheet Confidential A 00000610

RTC_TC_DOW_SEC

Security RTC Day-of-week Time Counter Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s) 2:0

TC_DOW_SEC RW

Name TC_DOW_SEC

00000612

0

0

18

17

16

2

1

0

Description Day-of-week initial value for time counter Range: 1~7

RTC_TC_MTH_SEC

Security RTC Month Time Counter Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

Bit(s) 3:0

0

TC_MONTH_SEC RW

Name TC_MONTH_SEC

00000614

0

0

0

0

Description Month initial value for time counter Range: 1~12

RTC_TC_YEA_SEC

Security RTC Year Time Counter Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

Bit(s) 6:0

TC_YEAR_SEC RW 0

Name TC_YEAR_SEC

MediaTek Proprietary and Confidential.

0

0

0

Description Year initial value for time counter Range: 0~127 (2000~2127) Software can bias the year as multiples of 4 for the internal leap-year formula. Here are 3 examples: 2000-2127, 1972~2099, 1904~2031.To simplify, RTC hardware treats all 4-multiple as leap years. If the range you define includes non-leap 4-multiple year (e.g. 2100), you have to adjust to correct date by yourselves (e.g. change Feb. 29th, 2100 to Mar. 1st, 2100). We suggest you bias the range large than 1900 and less than 2100 to evade manual adjustment, i.e. the bias values are suggested to be in the range of [-28,-96], that are (1972~2099) ~ (1904~2031).

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 460 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00000616

Description Formal leap formula: if year modulo 400 is 0 then leap else if year modulo 100 is 0 then no_leap else if year modulo 4 is 0 then leap else no_leap

RTC_SEC_CK_PDN

Security RTC Clock Control Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0 RTC_SE C_CK_P DN RW

Name Type Reset Bit(s) 0

0

Name RTC_SEC_CK_PDN

00000618

Description Controls security RTC clock 0: Turn off clock 1: Turn on clock

RTC_SEC_WRTGR

Enable Transfers from Core to Security RTC in Queue

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0 RTC_SE C_WRT GR WO

Name Type Reset Bit(s) 0

0

Name RTC_SEC_WRTGR

Description Enables transfers from core to security RTC After you modify all RTC registers you are to change, write RTC_WRTGR to 1 to trigger the transfer. The prior writing operations are queued at core power domain. The pending data will not be transferred to RTC domain until WRTGR = 1. After WRTGR = 1, the pending data will be transferred to RTC domain sequentially in order of register address, from low to high. e.g.

_TC_MIN_SEC -> RTC_TC_HOU_SEC ...

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 461 of 1067

MT6359 PMIC Datasheet Confidential A 00000780

DCXO_DSN_ID

DCXO Design ID Register

00002018

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000782

Description

DCXO_DSN_REV0

DCXO Design Revision Register 0

00001010

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000784

Description

DCXO_DSN_DBI

DCXO Design Bank Information Register

00003800

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000786

Description

DCXO_DSN_DXI

DCXO Design Extra Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 462 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00000788 Bit Name Type Reset

Description

DCXO_CW00 31

30

29

DCXO Code Word 0 28

27

26

25

24

23

00006B6D 22

21

20

19

18

17

16

Type Reset

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 XO_CL XO_EN XO_EN XO_BB XO_EX XO_EX XO_EX XO_EX XO_EXTBUF4_ XO_EXTBUF3_ XO_EXTBUF2_ XO_EXTBUF1_ KSEL_ BB_EN BB_MA _LPM_ TBUF4_ TBUF3_ TBUF2_ TBUF1_ MODE MODE MODE MODE MAN _M N EN_M EN_M EN_M EN_M EN_M RW RW RW RW RW RW RW RW RW RW RW RW 0 1 1 0 1 0 1 1 0 1 1 0 1 1 0 1

Bit(s) 15

Name XO_CLKSEL_MAN

14

XO_ENBB_EN_M

13

XO_ENBB_MAN

12

XO_BB_LPM_EN_M

11 10:9

XO_EXTBUF4_EN_M XO_EXTBUF4_MODE

8 7:6

XO_EXTBUF3_EN_M XO_EXTBUF3_MODE

5 4:3

XO_EXTBUF2_EN_M XO_EXTBUF2_MODE

2 1:0

XO_EXTBUF1_EN_M XO_EXTBUF1_MODE

Bit Name

MediaTek Proprietary and Confidential.

Description 0: XO2~4 are controlled by pin (CLK_SEL/SRCLKEN_IN1). 1: XO2~4 are controlled by register XO_CLKSEL_EN_M (default). 0: XO_SOC will be disabled if manual (register) control. 1: XO_SOC will be enabled if manual (register) control (default). 0: XO_SOC is controlled by pin (EN_BB/SRCLKEN_IN0). 1: XO_SOC is controlled by register XO_ENBB_EN_M (default). SW controlled LPM for saving power during transceiver standby Must be EN_BB = 1, CLK_SEL = 0. Enables/Disables XO_CEL during manual (register) control 00: Register controlled by XO_EXTBUF4_EN_M 01: EN_BB 10: CLK_SEL 11: XO_EXTBUF2_EN_M or XO_EXTBUF3_EN_M or CLK_SEL Enables/Disables XO_NFC during manual (register) control 00: Register controlled by XO_EXTBUF3_EN_M 01: EN_BB 10: CLK_SEL 11: XO_EXTBUF2_EN_M or XO_EXTBUF3_EN_M or CLK_SEL Enables/Disables XO_WCN during manual (register) control 00: Register controlled by XO_EXTBUF2_EN_M 01: EN_BB 10: CLK_SEL 11: XO_EXTBUF2_EN_M or XO_EXTBUF3_EN_M or CLK_SEL Enables/Disables XO_SOC during manual (register) control 00: Register controlled by XO_EXTBUF1_EN_M 01: EN_BB 10: CLK_SEL 11: EN_BB or CLK_SEL

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 463 of 1067

MT6359 PMIC Datasheet Confidential A 0000078A

DCXO_CW00_SET

DCXO Code Word 0 Set

Bit Name Type Reset

31

30

29

28

27

26

25

Bit Name Type Reset

15

14

13

12

11

10

9

Bit(s) 15:0

0

0

0

0

0

0

Name DCXO_CW00_SET

0000078C

0

DCXO_CW00_CLR

Bit Name Type Reset

29

28

27

26

25

Bit Name Type Reset

15

14

13

12

11

10

9

Bit(s) 15:0

Bit Name Type Reset

0

0

0

0

Name DCXO_CW00_CLR

0000078E

30

29

21

20

19

18

17

16

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

DCXO_CW00_SET W1 0 0

0

00000000

24

23

22

21

20

19

18

17

16

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

22

21

20

19

18

17

DCXO_CW00_CLR W1 0 0

Description Clears DCXO Code Word 0 0: Not clear 1: Clear

DCXO_CW01 31

22

DCXO Code Word 0 Clear

30

0

23

Description Sets up DCXO Code Word 0 0: Not set 1: Set

31

0

00000000

24

DCXO Code Word 1 28

27

26

25

24

23

00006D55 16

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 XO_BB XO_LV XO_HV XO_HV XO_EX XO_EX XO_EX XO_EX XO_EX XO_EX XO_EX XO_EX XO_LV XO_LV XO_HV XO_CL LPM_C _PBUF _PBUF _PBUF TBUF4_ TBUF4_ TBUF3_ TBUF3_ TBUF2_ TBUF2_ TBUF1_ TBUF1_ Name KSEL_ _PBUF BIAS_E _PBUF BIAS_E _EN_SY _PBUF CKG_E CKG_M CKG_E CKG_M CKG_E CKG_M CKG_E CKG_M KSEL_E _EN_M _MAN _MAN N_M M N_M N_M NC_M N_M AN N_M AN N_M AN N_M AN RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type 0 1 1 0 1 1 0 1 0 1 0 1 0 1 0 1 Reset

Bit

Bit(s) Name M frequency manually switched if 15 14 13 12 11 10

Description

XO_LV_PBUF_EN_M XO_LV_PBUFBIAS_EN_M XO_LV_PBUF_MAN XO_HV_PBUFBIAS_EN_M XO_HV_PBUF_EN_SYNC_M

MediaTek Proprietary and Confidential.

Enables XO low power buffer manually if XO_LV_PBUF_MAN = 1 Enables XO low power buffer bias manually if XO_LPMBUF_MAN = 1 XO low power buffer enable manual mode Enables XO FPM (HV) prebuffer bias circuit if XO_HV_PBUF_MAN = 1 Enables XO pre-buffer manually if XO_HV_PBUF_MAN = 1

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 464 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 9 8

Name XO_HV_PBUF_MAN XO_EXTBUF4_CKG_EN_M

7

XO_EXTBUF4_CKG_MAN

6

XO_EXTBUF3_CKG_EN_M

5

XO_EXTBUF3_CKG_MAN

4

XO_EXTBUF2_CKG_EN_M

3

XO_EXTBUF2_CKG_MAN

2

XO_EXTBUF1_CKG_EN_M

1

XO_EXTBUF1_CKG_MAN

0

XO_CLKSEL_EN_M

00000790

DCXO_CW02

Bit Name Type Reset

31

Bit

15

Name Type Reset Bit(s) 15

Description XO pre-buffer enable manual mode XO_CEL 26 MHz output enable when in manual mode 0: Disable XO_CEL buffer if XO_EXTBUF4_CKG_MAN = 1 1: Enable XO_CEL buffer if XO_EXTBUF4_CKG_MAN = 1 XO_CEL 26 MHz output enable manual mode 0: Software control 1: Manual control XO_EXTBUF4_CKG_EN_M XO_NFC 26 MHz output enable when in manual mode 0: Disable XO_NFC buffer if XO_EXTBUF3_CKG_MAN = 1 1: Enable XO_NFC buffer if XO_EXTBUF3_CKG_MAN = 1 XO_NFC 26 MHz output enable manual mode 0: Software control 1: Manual control XO_EXTBUF3_CKG_EN_M XO_WCN 26 MHz output enable when in manual mode 0: Disable XO_WCN buffer if XO_EXTBUF2_CKG_MAN = 1 1: Enable XO_WCN buffer if XO_EXTBUF2_CKG_MAN = 1 XO_WCN 26 MHz output enable manual mode 0: Software control 1: Manual control XO_EXTBUF2_CKG_EN_M XO_SOC 26 MHz output enable when in manual mode 0: Disable XO_SOC buffer if XO_EXTBUF1_CKG_MAN = 1 1: Enable XO_SOC buffer if XO_EXTBUF1_CKG_MAN = 1 XO_SOC 26 MHz output enable manual mode 0: Software control 1: Manual control XO_EXTBUF1_CKG_EN_M 0: XO2~4 will be disabled if manual (register) control. 1: XO2~4 will be enabled if manual (register) control (default).

30

29

14 13 XO_PC XO_CB XO_PC TAT_E ANK_S TAT_E N_MA YNC_D N_M N YN RW RW RW 1

0

0000A00E

27

26

25

24

23

22

21

20

19

18

17

16

12

11

10

9

8

7

6

5

4

3

2

1

0

RG_XO XO_EN XO_EN _CBAN 32K_M 32K_M K_POL AN

1

Name XO_PCTAT_EN_M

14

XO_PCTAT_EN_MAN

13

XO_CBANK_SYNC_DYN

2

RG_XO_CBANK_POL

MediaTek Proprietary and Confidential.

DCXO Code Word 2 28

RW

RW

RW

1

1

0

Description Enables/Disables temperature compensation when XO_PCTAT_EN_MAN = 1 0: Disable if XO_PCTAT_EN_MAN = 1 1: Enable if XO_PCTAT_EN_MAN = 1 Temperature compensation enable manual mode 0: Software control 1: Manual control XO_PCTAT_EN_M 0: Update clock of CBANK always turned on 1: Update clock of CBANK only turned on when CDAC is updated XO control signal of clock polarity for CBank control local synchronization

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 465 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

1

XO_EN32K_M

0

XO_EN32K_MAN

00000792

Description 0: Positive edge 1: Falling edge 0: EN_32K_G will be disabled if manual (register) control. 1: EN_32K_G will beenabled if manual (register) control (default) 0: EN_32K_G is controlled by pin (XO32K_EN) (default). 1: EN_32K_G is controlled by register XO_EN32K_M.

DCXO_CW03

DCXO Code Word 3

00007BE9

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

Bit

15

14

13

12

11

10

9

8

7

6

Name

XO_FPM_ISEL_M

Type Reset

RW 0

1

RW

1

1

Bit(s) 15:11 10:6 5

Name XO_FPM_ISEL_M RG_XO_CORE_LPM_ISEL XO_EXTBUF7_CKG_EN_M

4

XO_EXTBUF7_CKG_MAN

00000794

1

0

31

30

29

Bit Name Type Reset

15

14

13

1

1

Name XO_CDAC_LPM XO_CDAC_FPM

MediaTek Proprietary and Confidential.

1

1

1

1

1

20

5 4 XO_EX XO_EX TBUF7_ TBUF7_ CKG_E CKG_M N_M AN RW RW 1

19

18

17

16

3

2

1

0

0

Description XO core FPM current settings if XO_AAC_ISEL_MAN = 1 XO core LPM current register settings XO_EXT 26 MHz output enable when in manual mode 0: Disable XO_EXT buffer if XO_EXTBUF7_CKG_MAN = 1 1: Enable XO_EXT buffer if XO_EXTBUF7_CKG_MAN = 1 XO_EXT 26 MHz output enable manual mode 0: Software control 1: Manual control XO_EXTBUF7_CKG_EN_M

DCXO_CW04

Bit Name Type Reset

Bit(s) 15:8 7:0

RG_XO_CORE_LPM_ISEL

21

DCXO Code Word 4

0000FF88

28

27

26

25

24

23

22

21

12

11

10

9

8

7

6

5

XO_CDAC_LPM RW 1 1

1

1

1

1

0

0

20

19

18

17

16

4

3

2

1

0

0

0

0

XO_CDAC_FPM RW 0 1

Description XO CDAC code (complement) during LPM XO CDAC code (complement) during FPM

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 466 of 1067

MT6359 PMIC Datasheet Confidential A 00000796

DCXO_CW05 31

Bit Name Type Reset

30

DCXO Code Word 5 28

27

26

25

24

23

22

21

20

19

18

17

16

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

Type Reset

15 14 XO_COFST_FP M RW 0 0

Bit(s) 15:14 13:0

Name XO_COFST_FPM XO_32KDIV_NFRAC_FPM

Bit Name

00000798

XO_32KDIV_NFRAC_FPM RW 0

1

30

1

0

1

1

Description XO CDAC offset code during FPM 32K divider fractional input during FPM clk = 6.5 MHz

DCXO Code Word 6

00001760

27

26

25

24

23

22

21

20

19

18

17

16

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

Bit(s) 15:14 13:0

Name XO_COFST_LPM XO_32KDIV_NFRAC_LPM

0000079A

1

28

Type Reset

Name

1

29

15 14 XO_COFST_LP M RW 0 0

Bit

0

DCXO_CW06 31

Bit Name Type Reset

00001760

29

XO_32KDIV_NFRAC_LPM RW 0

1

0

1

1

1

0

1

1

Description XO CDAC offset code during LPM 32K divider fractional input during LPM clk = 6.5 MHz

DCXO_CW07

DCXO Code Word 7

0000F59E

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 467 of 1067

are reset

MT6359 PMIC Datasheet Confidential A 0000079C

DCXO_CW08

DCXO Code Word 8

00001C5E

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

1

0

RW

2 XO_PM IC_TOP _DIG_S W RW

0

1

XO_AA

Name C_FPM _SWEN

Type Reset Bit(s) 15

2

Name XO_AAC_FPM_SWEN

Description SW trigger AAC during FPM 0: Disable 1: SW trigger AAC during FPM 0: Mode and buffer control from AP 1: Mode and buffer control from srclken0

XO_PMIC_TOP_DIG_SW

0000079E

DCXO_CW09

DCXO Code Word 9

00005BF0

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

Name

XO_EX XO_EX XO_EXTBUF7_ XO_EXTBUF6_ TBUF7_ TBUF6_ MODE MODE EN_M EN_M

Type Reset

RW

Bit(s) 14 13:12

Name XO_EXTBUF7_EN_M XO_EXTBUF7_MODE

11 10:9

XO_EXTBUF6_EN_M XO_EXTBUF6_MODE

2 1 0

1

RW 0

RW 1

XO_32KDIV_TEST_EN XO_32KDIV_RATIO_MAN

MediaTek Proprietary and Confidential.

1

RW 0

1

17

16

1 0 XO_32 XO_32 XO_32 KDIV_R KDIV_T KDIV_S ATIO_ EST_EN WRST MAN RW RW RW 0

0

0

Description Enables/Disables XO_EXT during manual (register) control 00: Register controlled by XO_EXTBUF7_EN_M 01: EN_BB 10: CLK_SEL 11: EN_BB or CLK_SEL Enables/Disables XO_PD during manual (register) control 00: Register controlled by XO_EXTBUF6_EN_M 01: EN_BB 10: CLK_SEL 11: EN_BB or CLK_SEL DCXO 32K divider testing output thru DCXO_AUXOUT Manually sets the ratio of 32K divider high

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Page 468 of 1067

MT6359 PMIC Datasheet Confidential A 000007A0

DCXO_CW09_SET

DCXO Code Word 9 Set

Bit Name Type Reset

31

30

29

28

27

26

25

Bit Name Type Reset

15

14

13

12

11

10

9

Bit(s) 15:0

0

0

0

0

0

0

Name DCXO_CW09_SET

000007A2

0

DCXO_CW09_CLR

Bit Name Type Reset

29

28

27

26

25

Bit Name Type Reset

15

14

13

12

11

10

9

Bit(s) 15:0

0

0

0

0

Name DCXO_CW09_CLR

000007A4

22

21

20

19

18

17

16

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

DCXO_CW09_SET W1 0 0

DCXO Code Word 9 Clear

30

0

23

Description Sets up DCXO Code Word 9 0: Not set 1: Set

31

0

00000000

24

0

00000000

24

23

22

21

20

19

18

17

16

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

18

17

DCXO_CW09_CLR W1 0 0

Description Clears DCXO Code Word 9 0: Not clear 1: Clear

DCXO_CW10

DCXO Code Word 10

00008C14

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

1

0

XO_TH ADC_E N

Name Type Reset Bit(s) 7 4 3 2 1

RW 0

Name XO_THADC_EN XO_CAL_EN_M XO_CAL_EN_MAN XO_VIO18PG_BUFEN XO_EXTBUF4_CLKSEL_MAN

MediaTek Proprietary and Confidential.

16

2 1 0 XO_VI XO_EX XO_M XO_CA XO_CA O18PG TBUF4_ DB_TB L_EN_ L_EN_ _BUFE CLKSEL O_EN_ M MAN N _MAN SEL RW RW RW RW RW 1

0

0

Description Enables Vbe monitor by AUXADC For XO temperature sensing when XO_THADC_EN_MAN = 1. Enables CAL_EN manual when XO_CAL_EN_MAN = 1 CAL_EN manual control mux Buffer enable is gated by VIO18_PG or not 0: Enable/Disable XO_CEL from pin control 1: Enable/Disable XO_CEL from register

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Page 469 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 0

Name XO_MDB_TBO_EN_SEL

000007A6

Description Selects MDB tri-state buffer output enable contorl 0: From DIR TOP 1: From DCXO local control

DCXO_CW11

DCXO Code Word 11

Bit Name Type Reset

31

30

29

28

27

26

Bit

15

14

13

12

11

10

Name Type Reset Bit(s) 9 8 7:6

25

000007A8

0

29

28

27

26

25

24

23

Bit

15

14

13

12

11

10

9

8

7

XO_EX XO_TH RG_XO RG_XO_AUDIO TBUF2_ ADC_E _AUDI Name _ATTEN CLKSEL N_MA O_EN _MAN N RW

RW

RW

0

0

0

Bit(s) 15:14 13 12 11 6

Name RG_XO_AUDIO_ATTEN RG_XO_AUDIO_EN XO_EXTBUF2_CLKSEL_MAN XO_THADC_EN_MAN XO_EXTBUF7_BBLPM_EN_MASK

5

XO_EXTBUF6_BBLPM_EN_MASK

4

XO_EXTBUF4_BBLPM_EN_MASK

3

XO_EXTBUF3_BBLPM_EN_MASK

MediaTek Proprietary and Confidential.

19

18

17

16

5

4

3

2

1

0

20

19

18

17

0

DCXO Code Word 12

30

0

20

Setting to generate heat for calibration 00: No power 01: 133 mW under VBAT = 4V 10: 266 mW under VBAT = 4V 11: 400 mW under VBAT = 4V

DCXO_CW12

RW

21

Description 26 MHz clk for VOW use

31

1

22

0

Bit Name Type Reset

Type Reset

00004821

23

9 8 7 6 RG_XO RG_XO RG_XO_HEATE _VOW_ _RESER R_SEL EN VED6 RW RW RW 0

Name RG_XO_VOW_EN RG_XO_RESERVED6 RG_XO_HEATER_SEL

24

00008380 22

21

16

6 5 4 3 2 1 0 XO_EX XO_EX XO_EX XO_EX XO_EX XO_EX TBUF7_ TBUF6_ TBUF4_ TBUF3_ TBUF2_ TBUF1_ XO_BB BBLPM BBLPM BBLPM BBLPM BBLPM BBLPM _LPM_ _EN_M _EN_M _EN_M _EN_M _EN_M _EN_M EN_SEL ASK ASK ASK ASK ASK ASK RW RW RW RW RW RW RW 0

0

0

0

0

0

0

Description XO control signal of RC filter for internal audio output XO_AUDIO_EN_M XO_EXTBUF2_CLKSEL_MAN THADC enable manual mode 0: Non-mask 1: Masked BBLPM HW request 0: Non-Mask 1: Masked BBLPM HW request 0: Non-mask 1: Masked BBLPM HW request 0: Non-mask

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Page 470 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

2

XO_EXTBUF2_BBLPM_EN_MASK

1

XO_EXTBUF1_BBLPM_EN_MASK

0

XO_BB_LPM_EN_SEL

000007AA Bit Name Type Reset

Description 1: Masked BBLPM HW request 0: Non-mask 1: Masked BBLPM HW request 0: Non-mask 1: Masked BBLPM HW request BBLPM enable arbiter with enable mask 0: XO_BB_LPM_EN 1: HW bblpm arbiter

DCXO_CW13

DCXO Code Word 13

31

30

29

28

27

26

25

24

15

14

13

12

11

10

9

8

23

0000004C 22

21

20

19

18

17

16

7 6 5 4 3 2 1 0 RG_XO RG_XO _DIG26 RG_XO_EXTBU RG_XO_EXTBU RG_XO_EXTBU RG_XO_EXTBU RG_XO_EXTBUF4_SRSE _DIG26 RG_XO_EXTBUF2_SRSE M_DIV Name F7_HD F6_HD F3_HD F1_HD L M_DEG L 2_SW_ LITCH MAN RW RW RW RW RW RW RW RW Type 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 Reset

Bit

Bit(s) 15:14

Name RG_XO_EXTBUF7_HD

13:12 11:10

RG_XO_EXTBUF6_HD RG_XO_EXTBUF3_HD

9:8

RG_XO_EXTBUF1_HD

7

6:4

3

RG_XO_DIG26M_DIV2_SW_MAN

RG_XO_EXTBUF4_SRSEL

RG_XO_DIG26M_DEGLITCH

MediaTek Proprietary and Confidential.

Description XO control signal of EXTBUF7 output driving strength 2'b00: 26 sets 2'b01: 16 sets 2'b10: 8 sets 2'b11: 2 sets Not used in MT6359 XO control signal of EXTBUF3 output driving strength 2'b00: 26 sets 2'b01: 16 sets 2'b10: 8 sets 2'b11: 2 sets XO control signal of EXTBUF1 output driving strength 2'b00: 26 sets 2'b01: 16 sets 2'b10: 8 sets 2'b11: 2 sets CK_dig DIV2 control option 0: SW 1: HW XO control signal of EXTBUF4 output driving strength 3'b000: 0 ohm 3'b001: 90 ohm 3'b010: 160 ohm 3'b011: 230 ohm 3'b100: 390 ohm 3'b101: 600 ohm 3'b110: 830 ohm 3'b111: 1,100 ohm Enables CK_dig deglitch

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Page 471 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 2:0

Name RG_XO_EXTBUF2_SRSEL

000007AC

Description XO control signal of EXTBUF2 output driving strength 3'b000: 0 ohm 3'b001: 90 ohm 3'b010: 160 ohm 3'b011: 230 ohm 3'b100: 390 ohm 3'b101: 600 ohm 3'b110: 830 ohm 3'b111: 1,100 ohm

DCXO_CW14

DCXO Code Word 14

00000F04

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0 XO_ST A_CTL_ MAN RW

Name

XO_STA_CTL_M

Type Reset

0

1

0

Bit(s) 3:1 0

RW

Name XO_STA_CTL_M XO_STA_CTL_MAN

000007AE

0

Description Manual control value for DCXO mode from AP Manual control for DCXO mode from AP

DCXO_CW15

DCXO Code Word 15

00000F0F

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000007B0

Description

DCXO_CW16

DCXO Code Word 16

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

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Page 472 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

000007B2

Description

DCXO_CW17

DCXO Code Word 17

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000007B4

Description

DCXO_CW18

DCXO Code Word 18

0000E1C1

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

22

21

20

19

18

17

000007B6 Bit Name Type Reset

Description

DCXO_CW19 31

30

29

DCXO Code Word 19 28

27

26

25

24

23

00009248

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit Name RG_XO_EXTBUF7_RSEL RG_XO_EXTBUF4_RSEL RG_XO_EXTBUF3_RSEL RG_XO_EXTBUF2_RSEL RG_XO_EXTBUF1_RSEL RW RW RW RW RW Type 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 Reset

Bit(s) 15:13

Name RG_XO_EXTBUF7_RSEL

12:10

RG_XO_EXTBUF4_RSEL

MediaTek Proprietary and Confidential.

16

0

Description Selects XO_EXT output impedance for impedance matching 000: 70 ohm 001: 60 ohm 010: 55 ohm 011: 50 ohm 100: 45 ohm 101: 35 ohm 110: 30 ohm 111: 25 ohm Selects XO_CEL output impedance for impedance matching 000: 50 ohm

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 473 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

9:7

RG_XO_EXTBUF3_RSEL

6:4

RG_XO_EXTBUF2_RSEL

3:1

RG_XO_EXTBUF1_RSEL

000007B8

Description 001: 45 ohm 010: 40 ohm 011: 35 ohm 100: 30 ohm 101: 25 ohm 110: 20 ohm 111: 15 ohm Selects XO_NFC output impedance for impedance matching 000: 70 ohm 001: 60 ohm 010: 55 ohm 011: 50 ohm 100: 45 ohm 101: 35 ohm 110: 30 ohm 111: 25 ohm Selects XO_WCN output impedance for impedance matching 000: 50 ohm 001: 45 ohm 010: 40 ohm 011: 35 ohm 100: 30 ohm 101: 25 ohm 110: 20 ohm 111: 15 ohm Selects XO_SOC output impedance for impedance matching 000: 70 ohm 001: 60 ohm 010: 55 ohm 011: 50 ohm 100: 45 ohm 101: 35 ohm 110: 30 ohm 111: 25 ohm

DCXO_ELR_NUM

DCXO Number of ELR Register

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

MediaTek Proprietary and Confidential.

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Page 474 of 1067

MT6359 PMIC Datasheet Confidential A 000007BA

DCXO_ELR0

DCXO ELR 0 Register

0000000C

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000900

Description

PSC_TOP_ID

PSC TOP Design ID Register

00000900

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000902

Description

PSC_TOP_REV0

PSC TOP Design Revision Register 0

00001000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000904

Description

PSC_TOP_DBI

PSC TOP Design Bank Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

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Page 475 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00000906

Description

PSC_TOP_DXI

PSC TOP Design Extra Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000908

Description

PSC_TPM0

PSC_TOP Parameter 0

00000E0C

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000090A

Description

PSC_TPM1

PSC_TOP Parameter 1

00000110

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 476 of 1067

MT6359 PMIC Datasheet Confidential A 0000090C

PSC_TOP_CLKCTL_0

PSC Clock Control Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000090E

Description

PSC_TOP_RSTCTL_0

PSC Reset Control Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

20

19

18

17

00000910

Description

PSC_TOP_INT_CON0

PSC_TOP INT Control Register 0

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

Bit

15

14

13

12

11

10

9

8

7

6

Name Type Reset Bit(s) 5

21

4

RG_INT_EN_NI_LBAT_INT

3

RG_INT_EN_HOMEKEY_R

2

RG_INT_EN_PWRKEY_R

MediaTek Proprietary and Confidential.

16

5 4 3 2 1 0 RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT _EN_C _EN_NI _EN_H _EN_P _EN_H _EN_P HRDET _LBAT_ OMEKE WRKEY OMEKE WRKEY _EDGE INT Y_R _R Y RW RW RW RW RW RW 1

Name RG_INT_EN_CHRDET_EDGE

00000025

0

0

1

0

1

Description Enables CHRDET_EDGE interrupt 0: Not issue interrupt 1: Issue interrupt Enables NI_LBAT_INT interrupt 0: Not issue interrupt 1: Issue interrupt Enables HOMEKEY_R interrupt 0: Not issue interrupt 1: Issue interrupt Enables PWRKEY_R interrupt 0: Not issue interrupt 1: Issue interrupt

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 477 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 1

0

Name RG_INT_EN_HOMEKEY

Description Enables HOMEKEY interrupt 0: Not issue interrupt 1: Issue interrupt Enables PWRKEY interrupt 0: Not issue interrupt 1: Issue interrupt

RG_INT_EN_PWRKEY

00000912

PSC_TOP_INT_CON0_SET

PSC_TOP INT Control Register 0 SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

PSC_INT_CON0_SET W1 0 0 0 0

0

0

0

0

0

0

Bit(s) 15:0

0

0

0

0

0

Name PSC_INT_CON0_SET

00000914

Description Enables N0_SET interrupt 1'b0: Not set 1'b1: Set

PSC_TOP_INT_CON0_CLR

PSC_TOP INT Control Register 0 CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

PSC_INT_CON0_CLR W1 0 0 0 0

0

0

0

0

0

0

Bit(s) 15:0

0

0

0

0

Name PSC_INT_CON0_CLR

MediaTek Proprietary and Confidential.

0

Description _INT_CON0_ SW 1'b0: Not clear 1'b1: Clear

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 478 of 1067

MT6359 PMIC Datasheet Confidential A 00000916

PSC_TOP_INT_MASK_CON0 PSC_TOP INT Mask Control Register 0

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

Bit

15

14

13

12

11

10

9

8

7

6

Name

Type Reset Bit(s) 5

Name RG_INT_MASK_CHRDET_EDGE

RG_INT_MASK_NI_LBAT_INT

3

RG_INT_MASK_HOMEKEY_R

2

RG_INT_MASK_PWRKEY_R

1

RG_INT_MASK_HOMEKEY

0

RG_INT_MASK_PWRKEY

00000918

20

00000000 19

18

0

0

0

Bit Name Type Reset

31

30

29

28

27

26

Bit Name Type Reset

15

14

13

12

11

10

0

0

0

Name PSC_INT_MASK_CON0_SET

MediaTek Proprietary and Confidential.

16

0

0

Description Masks CHRDET_EDGE interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks NI_LBAT_INT interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks HOMEKEY_R interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks PWRKEY_R interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks HOMEKEY interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks PWRKEY interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status

PSC_TOP_INT_MASK_CON0_SPSC_TOP INT Mask Control Register 0 SET ET

0

17

5 4 3 2 1 0 RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT _MASK _MASK _MASK _MASK _MASK _MASK _CHRD _NI_LB _HOME _PWRK _HOME _PWRK ET_ED AT_INT KEY_R EY_R KEY EY GE RW RW RW RW RW RW 0

4

Bit(s) 15:0

21

0

0

00000000

25

24

23

22

21

20

19

18

17

16

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

PSC_INT_MASK_CON0_SET W1 0 0 0 0

Description 1'b0: Not set 1'b1: Set

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 479 of 1067

MT6359 PMIC Datasheet Confidential A 0000091A

PSC_TOP_INT_MASK_CON0_ PSC_TOP INT Mask Control Register 0 CLR CLR

Bit Name Type Reset

31

30

29

28

27

26

Bit Name Type Reset

15

14

13

12

11

10

Bit(s) 15:0

0

0

0

0

0

0

Name PSC_INT_MASK_CON0_CLR

0000091C

25

24

23

22

21

20

19

18

17

16

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

20

19

18

17

PSC_INT_MASK_CON0_CLR W1 0 0 0 0

Description 1'b0: Not clear 1'b1: Clear

PSC_TOP_INT_STATUS0

PSC_TOP INT Status Register 0

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

Bit

15

14

13

12

11

10

9

8

7

6

Name Type Reset Bit(s) 5

21

Name RG_INT_STATUS_CHRDET_EDGE

RG_INT_STATUS_NI_LBAT_INT

3

RG_INT_STATUS_HOMEKEY_R

2

RG_INT_STATUS_PWRKEY_R

1

RG_INT_STATUS_HOMEKEY

0

RG_INT_STATUS_PWRKEY

MediaTek Proprietary and Confidential.

00000000 16

5 4 3 2 1 0 RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT _STAT _STAT _STAT _STAT _STAT _STAT US_CH US_NI_ US_HO US_PW US_HO US_PW RDET_E LBAT_I MEKEY RKEY_R MEKEY RKEY DGE NT _R W1C W1C W1C W1C W1C W1C 0

4

00000000

0

0

0

0

0

Description CHRDET_EDGE interrupt status 0: No interrupt issued 1: Interrupt issued NI_LBAT_INT interrupt status 0: No interrupt issued 1: Interrupt issued HOMEKEY_R interrupt status 0: No interrupt issued 1: Interrupt issued PWRKEY_R interrupt status 0: No interrupt issued 1: Interrupt issued HOMEKEY interrupt status 0: No interrupt issued 1: Interrupt issued PWRKEY interrupt status 0: No interrupt issued 1: Interrupt issued

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 480 of 1067

MT6359 PMIC Datasheet Confidential A 0000091E

PSC_TOP_INT_RAW_STATUS0 PSC_TOP INT Raw Status Register 0

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

Bit

15

14

13

12

11

10

9

8

7

6

Name

Type Reset Bit(s) 5

4

3

2

1

0

21

00000000 20

19

18

17

16

5 4 3 2 1 0 RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT _RAW_ _RAW_ _RAW_ _RAW_ _RAW_ _RAW_ STATUS STATUS STATUS STATUS STATUS STATU _CHRD _NI_LB _HOME _PWRK _HOME S_PWR ET_ED AT_INT KEY_R EY_R KEY KEY GE RO RO RO RO RO RO 0

0

0

0

0

0

Name Description RG_INT_RAW_STATUS_CHRDET_EDGE CHRDET_EDGE raw interrupt status 0: No interrupt issued 1: Interrupt issued RG_INT_RAW_STATUS_NI_LBAT_INT NI_LBAT_INT raw interrupt status 0: No interrupt issued 1: Interrupt issued RG_INT_RAW_STATUS_HOMEKEY_R HOMEKEY_R raw interrupt status 0: No interrupt issued 1: Interrupt issued RG_INT_RAW_STATUS_PWRKEY_R PWRKEY_R raw interrupt status 0: No interrupt issued 1: Interrupt issued RG_INT_RAW_STATUS_HOMEKEY HOMEKEY raw interrupt status 0: No interrupt issued 1: Interrupt issued RG_INT_RAW_STATUS_PWRKEY PWRKEY raw interrupt status 0: No interrupt issued 1: Interrupt issued

00000920

PSC_TOP_INT_MISC_CON

PSC_TOP INT MISC Control Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

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Page 481 of 1067

MT6359 PMIC Datasheet Confidential A 00000922

PSC_TOP_INT_MISC_CON_SE PSC_TOP INT MISC Control SET Register T

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000924

Description

PSC_TOP_INT_MISC_CON_CL PSC_TOP INT MISC Control CLR Register R

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000926

Description

PSC_TOP_MON_CTL

PSC TOP Debug Monitor Control

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000980

Description

STRUP_ID

STRUP Design ID Register

0000A001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 482 of 1067

MT6359 PMIC Datasheet Confidential A

Bit(s)

Name

00000982

Description

STRUP_REV0

STRUP Design Revision Register 0

00000010

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000984

Description

STRUP_DBI

STRUP Design Bank Information Register

00001000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000986

Description

STRUP_DSN_FPI

STRUP Design Extra Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 483 of 1067

MT6359 PMIC Datasheet Confidential A 00000988

STRUP_ANA_CON0

STRUP Control Register 0

00004700

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

22

21

20

19

18

17

16

6

5

4

3

2

1

0

0000098A

Description

STRUP_ANA_CON1

STRUP Control Register 1

Bit Name Type Reset

31

30

29

28

27

26

Bit

15

14

13

12

11

10

Name Type Reset

25

Name RG_EN2_DRVSEL

8

RG_EN1_DRVSEL

7

RG_RST_DRVSEL

6:3

RG_PMU_RSV

2:0

RGS_ANA_CHIP_ID

MediaTek Proprietary and Confidential.

23

9 8 7 RG_EN RG_EN RG_RS 2_DRV 1_DRV T_DRV SEL SEL SEL RW RW RW 0

Bit(s) 9

24

0

0

0

00000020

RG_PMU_RSV

RGS_ANA_CHIP_ID

RW

RO

1

0

0

0

0

0

Description Selects EXT_PMIC_EN2 pin output driving capability 0: 7.5 mA (default) 1: 15 mA Selects EXT_PMIC_EN1 pin output driving capability 0: 7.5 mA (default) 1: 15 mA Selects reset pin output driving capability 0: 7.5 mA (default) 1: 15 mA Reserved bits RG_PMU_RSV[2] is for PMIC BJT thermal sensor function on/off control 1'b0: Turn off BJT thermal sensor function 1'b1: Turn on BJT thermal sensor function Chip ID

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 484 of 1067

MT6359 PMIC Datasheet Confidential A 0000098C

STRUP_ANA_CON2

STRUP Control Register 2

Bit Name Type Reset

31

30

29

28

27

Bit

15

14

13

12

11

RGS_V RGS_V RGS_V RGS_V RGS_V RFCK_P RFCK_1 M18_P A09_P A12_P Name G_STA _PG_ST G_STA G_STA G_STA TUS ATUS TUS TUS TUS

Type Reset Bit(s) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RO 0

RO 0

RO 0

RO 0

31

30

29

28

Bit

15

14

13

12

Name Type Reset

24

23

21

20

19

18

17

16

6

5

4

3

2

1

0

RGS_V RGS_VI RGS_V RGS_V RGS_V RGS_V UFS_P O18_P EMC_P XO22_ AUD18 AUX18 G_STA G_STA G_STA PG_ST _PG_ST _PG_ST TUS TUS TUS ATUS ATUS ATUS RO 0

RO 0

RO 0

RO 0

RO 0

RO 0

21

20

19

18

17

STRUP Control Register 3 27

26

25

24

23

22

RGS_V USB_P G_STA TUS RO 0

00000000

11 10 9 8 7 6 5 4 3 2 1 RGS_V RGS_V RGS_V RGS_V RGS_V RGS_V RGS_V RGS_V RGS_V RGS_V RGS_V RF12_P GPU12 GPU11 PU_PG CORE_ PROC2 PROC1 MODE RF18_P S2_PG_ S1_PG_ G_STA _PG_ST _PG_ST _STAT PG_ST _PG_ST _PG_ST M_PG_ G_STA STATUS STATUS TUS ATUS ATUS US ATUS ATUS ATUS STATUS TUS RO RO RO RO RO RO RO RO RO RO RO 0

0

0

0

0

Name RGS_VRF12_PG_STATUS RGS_VS2_PG_STATUS

Description VRF12 PG status VS2 PG status

RGS_VPU_PG_STATUS RGS_VCORE_PG_STATUS RGS_VPROC2_PG_STATUS RGS_VPROC1_PG_STATUS RGS_VMODEM_PG_STATUS

VCORE12 PG status VCORE11 PG status VPROC1 PG status VPROC1 PG status VMODEM PG status

MediaTek Proprietary and Confidential.

00000000

22

Description VRFCK2 PG status VRFCK1 PG status VM18 PG status VA09 PG status VA12 PG status VSRAM_PROC2 PG status VSRAM_PROC1 PG status VSRAM_OTHERS PG status VSRAM_MD PG status VUFS PG status VIO18 PG status VEMC PG status VXO22 PG status VAUD18 PG status VAUX18 PG status VUSB33 PG status

STRUP_ANA_CON3

Bit Name Type Reset

25

10 9 8 7 RGS_V RGS_V RGS_V RGS_V SRAM_ SRAM_ SRAM_ SRAM_ PROC2 PROC1 OTHER MD_PG _PG_ST _PG_ST S_PG_S _STAT ATUS ATUS TATUS US RO RO RO RO 0 0 0 0

Name RGS_VRFCK_PG_STATUS RGS_VRFCK_1_PG_STATUS RGS_VM18_PG_STATUS RGS_VA09_PG_STATUS RGS_VA12_PG_STATUS RGS_VSRAM_PROC2_PG_STATUS RGS_VSRAM_PROC1_PG_STATUS RGS_VSRAM_OTHERS_PG_STATUS RGS_VSRAM_MD_PG_STATUS RGS_VUFS_PG_STATUS RGS_VIO18_PG_STATUS RGS_VEMC_PG_STATUS RGS_VXO22_PG_STATUS RGS_VAUD18_PG_STATUS RGS_VAUX18_PG_STATUS RGS_VUSB_PG_STATUS

0000098E

Bit(s) 11 10 9 8 7 6 5 4 3

RO 0

26

0

0

0

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

0

0

0

16

0 RGS_V BBCK_ PG_ST ATUS RO 0

Page 485 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 2 1 0

Name RGS_VS1_PG_STATUS RGS_VRF18_PG_STATUS RGS_VBBCK_PG_STATUS

00000990

Description VS1 PG status VRF18 PG status VBBCK PG status

STRUP_ELR_NUM

STRUP Number of ELR Register

00000002

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000992

Description

STRUP_ELR_0

STRUP ELR 0 Register

00000100

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000A00

Description

PSEQ_ID

PSEQ Design ID Register

00000800

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

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Page 486 of 1067

MT6359 PMIC Datasheet Confidential A 00000A02

PSEQ_REV0

PSEQ Design Revision Register 0

00001300

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000A04

Description

PSEQ_DBI

PSEQ Design Bank Information Register

00005200

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000A06

Description

PSEQ_DXI

PSEQ Design Extra Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

20

19

18

17

16

3

2

1

0

00000A08

Description

PPCCTL0

PPC Control 0 Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

Bit

15

14

13

12

11

10

9

8

7

6

5

Name Type Reset

MediaTek Proprietary and Confidential.

4 RG_US RG_WDTRST_A BDL_M CT ODE RW RW 0

0

0

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

RG_PW RHOLD RW 0

Page 487 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 6:5

Name RG_WDTRST_ACT

4

RG_USBDL_MODE

0

RG_PWRHOLD

00000A0A

Description PSEQ WDT action 00: PMIC reg reset 01: Warm reset 10: Cold reset 11: Reserved Disables BWDT in USBDL mode 0: Normal mode 1: USBDL mode -> disable BWDT Power hold 0 -> 1: Power hold 1 -> 0: Power down

PPCCTL1

PPC Control 1 Register

00000600

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000A0C

Description

PPCCFG0

PPC Configuration 0 Register

00000301

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000A0E

Description

STRUP_CON9

STRUP DIG Control Register N9

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

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Page 488 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00000A10

Description

STRUP_CON11

STRUP DIG Control Register 11

00004000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

20

19

18

17

00000A12

Description

STRUP_CON12

STRUP DIG Control Register 12

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

Bit

15

14

13

12

11

10

9

8

7

6

5

Name Type Reset

RG_PW RG_PW RG_PWRKEY_R RKEY_K RKEY_R ST_TD EY_MO ST_EN DE RW 0

0

RW

RW

1

1

Bit(s) 15:14

Name RG_PWRKEY_RST_TD

13

RG_PWRKEY_RST_EN

12

RG_PWRKEY_KEY_MODE

4

RG_STRUP_LONG_PRESS_EXT_EN

3:2

RG_STRUP_LONG_PRESS_EXT_TD

1:0

RG_STRUP_LONG_PRESS_EXT_SEL

MediaTek Proprietary and Confidential.

00003000 16

4 3 2 1 0 RG_ST RUP_L RG_STRUP_LO RG_STRUP_LO ONG_P NG_PRESS_EXT NG_PRESS_EXT RESS_E _TD _SEL XT_EN RW RW RW 0

0

0

0

0

Description Long pressed time to issue reset 2'b00: 8 sec 2'b01: 11 sec 2'b10: 14 sec 2'b11: 5 sec Enables PWRKEY long pressed reset 1'b0: Disable reset 1'b1: Enable reset Selects long pressed key mode 1'b0: PWRKEY 1'b1: PWRKEY + HOMEKEY Enables re-power-on scenario function 1'b0: Disable long_press re-power on case 1'b1: Enable long_press re-power on case Selects delay time 2'b00: 0.5s 2'b10: 2s Selects re-power-on scenario 2'b00: Debounce pwrkey 2'b01: After releasing pwrkey 2'b10: After releasing pwrkey and pressing pwrkey again

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 489 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00000A14

Description

STRUP_CON13

STRUP DIG Control Register 13

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0 RG_ST RUP_P WRKEY _COUN T_RESE T RW

Name

Type Reset Bit(s) 0

0

Name RG_STRUP_PWRKEY_COUNT_RESET

00000A16

Description Resets long press shut-down counter 1'b0: Not reset long press counter 1'b1: Reset long press counter

PWRKEY_PRESS_STS

PWRKEY Long Press Counter Status

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000A18

Description

PORFLAG

Power Reset Flag

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 490 of 1067

MT6359 PMIC Datasheet Confidential A 00000A1A

STRUP_CON4

STRUP DIG Control Register N4

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

Name Type Reset Bit(s) 2 1

Name JUST_PWRKEY_RST JUST_SMART_RST

00000A1C

18

17

2 1 JUST_P JUST_S WRKEY MART_ _RST RST RO RO 0

0

16

0

Description Long pressed reset indicator Smart reset indicator

STRUP_CON1

STRUP DIG Control Register 1

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000A1E

Description

STRUP_CON2

STRUP DIG Control Register 2

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 491 of 1067

MT6359 PMIC Datasheet Confidential A 00000A20

STRUP_CON5

STRUP DIG Control Register N5

Bit Name Type Reset

31

30

29

28

27

26

Bit

15

14

13

12

11

10

Name Type Reset

25

24

9 8 DA_EX DA_EX T_PMIC T_PMIC _EN2 _EN1 RO RO 0

Bit(s) 9

Name DA_EXT_PMIC_EN2

8

DA_EXT_PMIC_EN1

6

RGS_EXT_PMIC_PG

00000A22

00000000

23

22

21

20

19

18

17

16

7

6 RGS_E XT_PM IC_PG RO

5

4

3

2

1

0

0

0

Description External PMIC power on signal 0: External PMIC shutdown 1: External PMIC power on External PMIC power on signal 0: External PMIC shutdown 1: External PMIC power on External PG status

STRUP_CON19

STRUP DIG Control Register 20

00000300

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000A24

Description

STRUP_PGDEB0

STRUP PG Debounce Control Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 492 of 1067

MT6359 PMIC Datasheet Confidential A 00000A26

STRUP_PGDEB1

STRUP PG Debounce Control Register 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000A28

Description

STRUP_PGENB0

STRUP PG Enable Control Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000A2A

Description

STRUP_PGENB1

STRUP PG Enable Control Register 1

00008000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000A2C

Description

STRUP_OCENB0

BUCK OC SDN Control Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 493 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00000A2E

Description

STRUP_OCENB1

BUCK OC SDN Control Register 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000A30

Description

PPCTST0

PPCTST0

00000002

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000A32

Description

PPCCTL2

PPC Control 2 Register

00000130

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 494 of 1067

MT6359 PMIC Datasheet Confidential A 00000A34

STRUP_CON10

STRUP DIG Control Register 10

00008000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000A36

Description

STRUP_CON3

STRUP DIG Control Register 3

00002000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000A38

Description

STRUP_CON6

STRUP DIG Control Register 6

00000003

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000A3A

Description

CPSWKEY

CPS Write Key Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 495 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00000A3C

Description

CPSCFG0

CPS Configuration 0 Register

00001D03

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000A3E

Description

CPSDSA0

CPS Power Down Assignment 0 Register

00003F61

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000A40

Description

CPSDSA1

CPS Power Down Assignment 1 Register

00003C42

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

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Page 496 of 1067

MT6359 PMIC Datasheet Confidential A 00000A42

CPSDSA2

CPS Power Down Assignment 2 Register

000018E6

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000A44

Description

CPSDSA3

CPS Power Down Assignment 3 Register

00002D4F

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000A46

Description

CPSDSA4

CPS Power Down Assignment 4 Register

0000358C

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000A48

Description

CPSDSA5

CPS Power Down Assignment 5 Register

000075EE

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 497 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00000A4A

Description

CPSDSA6

CPS Power Down Assignment 6 Register

00002251

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000A4C

Description

CPSDSA7

CPS Power Down Assignment 7 Register

00003DF0

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000A4E

Description

CPSDSA8

CPS Power Down Assignment 8 Register

0000734F

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

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Page 498 of 1067

MT6359 PMIC Datasheet Confidential A 00000A50

CPSDSA9

CPS Power Down Assignment 9 Register

00003D2F

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000A52

Description

PSEQ_ELR_NUM

PSEQ Number of ELR Register

0000001C

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000A54

Description

PSEQ_ELR0

BWDT Control 0 Register

00006956

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000A56

Description

PSEQ_ELR1

PSEQ_ELR Control Register 8

00005000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

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Page 499 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00000A58

Description

PSEQ_ELR2

Reserve ELR Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000A5A

Description

PSEQ_ELR3

Reserve ELR Register 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000A5C

Description

CPSUSA_ELR0

CPS Power Up Assignment 0 Register

00007C20

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

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Page 500 of 1067

MT6359 PMIC Datasheet Confidential A 00000A5E

CPSUSA_ELR1

CPS Power Up Assignment 1 Register

00007C63

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000A60

Description

CPSUSA_ELR2

CPS Power Up Assignment 2 Register

00001904

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000A62

Description

CPSUSA_ELR3

CPS Power Up Assignment 3 Register

0000317F

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000A64

Description

CPSUSA_ELR4

CPS Power Up Assignment 4 Register

000041EE

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 501 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00000A66

Description

CPSUSA_ELR5

CPS Power Up Assignment 5 Register

00004BF2

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000A68

Description

CPSUSA_ELR6

CPS Power Up Assignment 6 Register

000026F6

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000A6A

Description

CPSUSA_ELR7

CPS Power Up Assignment 7 Register

000053F5

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

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Page 502 of 1067

MT6359 PMIC Datasheet Confidential A 00000A6C

CPSUSA_ELR8

CPS Power Up Assignment 8 Register

00006B1F

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000A6E

Description

CPSUSA_ELR9

CPS Power Up Assignment 9 Register

00007D5F

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000A80

Description

CHRDET_ID

CHRDET Design ID Register

00001400

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000A82

Description

CHRDET_REV0

CHRDET Design Revision Register 0

00001000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 503 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00000A84

Description

CHRDET_DBI

CHRDET Design Bank Information Register

00001A00

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000A86

Description

CHRDET_DXI

CHRDET Design Extra Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000A88

Description

CHR_CON0

Charger Control Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0 RGS_C HRDET RO

Name Type Reset Bit(s) 0

0

Name RGS_CHRDET

MediaTek Proprietary and Confidential.

Description Detects charger-in after debounce 0: No valid charger detected 1: Valid charger detected

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 504 of 1067

MT6359 PMIC Datasheet Confidential A 00000A8A

CHR_CON1

Charger Control Register 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

17

00000A8C

Description

CHR_CON2

Charger Control Register 2

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

Name Type Reset

1 0 RG_EN RG_EN VTEM_ VTEM_ EN D RW RW 0

Bit(s) 1

Name RG_ENVTEM_EN

0

RG_ENVTEM_D

00000A8E

16

0

Description Blocks CHR_DET signal to start_up 0: N/A 1: Write enable Blocks CHR_DET signal to start_up 0: Not block 1: Block

PCHR_VREF_ANA_DA0

PCHR_VREF DA Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

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Page 505 of 1067

MT6359 PMIC Datasheet Confidential A 00000A90

PCHR_VREF_ANA_CON0

PCHR_VREF Control Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

Name Type Reset Bit(s) 2

1

18

PCHR_VREF_ANA_CON1

PCHR_VREF Control Register 1

31

30

29

28

27

26

25

24

23

22

21

20

19

18

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

Name

RG_UVLO_VTHL

Type Reset

RW

1 0

0

Name RG_UVLO_VTHL

RG_BGR_UNCHOP_PH RG_BGR_UNCHOP

MediaTek Proprietary and Confidential.

0

00000008

Bit Name Type Reset

Bit(s) 6:2

0

Description Bandgap reference FT test mode enable signal 0: Normal_mode 1: Test mode (should combine PMU_TESTMODE = 1) Bandgap reference FT test mode resetb signal (also gated by RG_BGR_TEST_EN = 0 & PMU_TESTMODE = 0) -> GPIO control in test mode 0: Reset 1: Not reset

RG_BGR_TEST_RSTB

00000A92

16

2 1 RG_BG RG_BG R_TEST R_TEST _EN _RSTB RW RW 0

Name RG_BGR_TEST_EN

17

0

0

1

0

17

16

1 0 RG_BG RG_BG R_UNC R_UNC HOP_P HOP H RW RW 0

0

Description Selects UVLO low threshold 00000: 2.5V 00001: 2.55V 00010: 2.6V (default) 00011: 2.65V 00100: 2.7V 00101: 2.75V 00110: 2.8V 00111: 2.85V 01000: 2.9V Selects BGR unchop mode phase BGR unchop mode 0: Chop 1: Unchop

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 506 of 1067

MT6359 PMIC Datasheet Confidential A 00000A94

PCHR_VREF_ANA_CON2

PCHR_VREF Control Register 2

00000003

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

Bit(s) 4:0

19

18

17

16

3

2

1

0

RG_LBAT_INT_VTH RW

Name RG_LBAT_INT_VTH

00000A96

0

0

0

1

1

Description LBAT_INT threshold voltage 00000: 2.5V 00001: 2.55V 00010: 2.6V 00011: 2.65V (default) 00100: 2.7V 00101: 2.75V 00110: 2.8V 00111: 2.85V 01000: 2.9V 01001: 2.95V 01010: 3.0V 01011: 3.05V 01100: 3.1V 01101: 3.15V 01110: 3.2V 01111: 3.25V 10000: 3.3V 10001: 3.35V 10010: 3.4V

PCHR_VREF_ANA_CON3

PCHR_VREF Control Register 3

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s) 2:0

RG_OVLO_VTH_SEL RW 0

Name RG_OVLO_VTH_SEL

MediaTek Proprietary and Confidential.

0

1

Description OVLO VTH SEL bits 000: SD: 5.4V, recover: 5.0V 001: SD: 5.6V, recover: 5.2V (default) 010: SD: 5.8V, recover: 5.4V 011: SD: 6.0V, recover: 5.6V 100: SD: 5.4V, recover: 5.0V 101: SD: 5.6V, recover: 5.2V 110: SD: 5.8V, recover: 5.4V

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 507 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00000A98

Description 111: SD: 6.0V, recover: 5.6V

PCHR_VREF_ANA_CON4

PCHR_VREF Control Register 4

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000A9A

Description

PCHR_VREF_ELR_NUM

PCHR_VREF Number of ELR Register

00000004

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000A9C

Description

PCHR_VREF_ELR_0

PCHR_VREF ELR 0 Register

00000500

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8 RG_BG R_TRI M_EN RW

7

6

5

4

3

2

1

0

0

0

Name

RG_BGR_RSEL

Type Reset Bit(s) 13:9

RW 0

Name RG_BGR_RSEL

MediaTek Proprietary and Confidential.

0

0

1

0

1

RG_BGR_TRIM RW 0

0

0

0

Description Selects BGR resistor (R0 = R1) (Trim TC curve) (add one bit LSB@MT6359) R2 = 8.5*Runit, and VBG = (R0/R2)*dVBE + VBE 11111: R0 = 59.3*Runit, VBG = 1.091V 11110: R0 = 60.3*Runit, VBG = 1.098V 11101: R0 = 61.3*Runit, VBG = 1.104V 11100: R0 = 62.3*Runit, VBG = 1.111V 11011: R0 = 63.3*Runit, VBG = 1.117V 11010: R0 = 64.3*Runit, VBG = 1.124V © 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 508 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

8 5:0

Name

Description 11001: R0 = 65.3*Runit, VBG = 1.130V 11000: R0 = 66.3*Runit, VBG = 1.136V 10111: R0 = 67.3*Runit, VBG = 1.143V 10110: R0 = 68.3*Runit, VBG = 1.149V 10101: R0 = 69.3*Runit, VBG = 1.156V 10100: R0 = 70.3*Runit, VBG = 1.162V 10011: R0 = 71.3*Runit, VBG = 1.169V 10010: R0 = 72.3*Runit, VBG = 1.175V 10001: R0 = 73.3*Runit, VBG = 1.181V 10000: R0 = 74.3*Runit, VBG = 1.188V 00000: R0 = 75.3*Runit, VBG = 1.194V 00001: R0 = 76.3*Runit, VBG = 1.201V 00010: R0 = 77.3*Runit, VBG = 1.207V (default) 00011: R0 = 78.3*Runit, VBG = 1.214V 00100: R0 = 79.3*Runit, VBG = 1.220V 00101: R0 = 80.3*Runit, VBG = 1.226V 00110: R0 = 81.3*Runit, VBG = 1.233V 00111: R0 = 82.3*Runit, VBG = 1.239V 01000: R0 = 83.3*Runit, VBG = 1.246V 01001: R0 = 84.3*Runit, VBG = 1.252V 01010: R0 = 85.3*Runit, VBG = 1.259V 01011: R0 = 86.3*Runit, VBG = 1.265V 01100: R0 = 87.3*Runit, VBG = 1.271V 01101: R0 = 88.3*Runit, VBG = 1.278V 01110: R0 = 89.3*Runit, VBG = 1.284V 01111: R0 = 90.3*Runit, VBG = 1.291V 0: Disable BG trimming and bypass voltage buffer 1: Enable BG trimming and voltage buffer Trims BGR buffer output voltage (add one bit and change LSB from 5 mV to 2.5 mV@MT6359) Default: 1.205V@00000 10000~11111: VBG = 1.125~1.200V with 2.5 mV/step 00000~01111: VBG = 1.205~1.280V with 2.5 mV/step

RG_BGR_TRIM_EN RG_BGR_TRIM

00000A9E

PCHR_VREF_ELR_1

PCHR_VREF ELR 1 Register

00006C04

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 509 of 1067

MT6359 PMIC Datasheet Confidential A 00000C00

BM_TOP_DSN_ID

BM_TOP ID Register

00005F00

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000C02

Description

BM_TOP_DSN_REV0

BM_TOP Revision Register 0

00001200

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000C04

Description

BM_TOP_DBI

BM_TOP Design Bank Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000C06

Description

BM_TOP_DXI

BM_TOP Design Extra Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 510 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00000C08

Description

BM_TPM0

BM_TOP Parameter 0

0000260C

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000C0A

Description

BM_TPM1

BM_TOP Parameter 1

00000232

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000C0C

Description

BM_TOP_CKPDN_CON0

BM_TOP_CKPDN Control Register 0

000021E4

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

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Page 511 of 1067

MT6359 PMIC Datasheet Confidential A 00000C0E

BM_TOP_CKPDN_CON0_SET BM_TOP_CKPDN_CON0 Register SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000C10

Description

BM_TOP_CKPDN_CON0_CLR BM_TOP_CKPDN_CON0 Register CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000C12

Description

BM_TOP_CKSEL_CON0

BM_TOP_CKSEL Control Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000C14

Description

BM_TOP_CKSEL_CON0_SET

BM_TOP_CKSEL_CON0 Register SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 512 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00000C16

Description

BM_TOP_CKSEL_CON0_CLR

BM_TOP_CKSEL_CON0 Register CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000C18

Description

BM_TOP_CKDIVSEL_CON0

BM_TOP_CKDIVSEL Control Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000C1A

Description

BM_TOP_CKDIVSEL_CON0_SET BM_TOP_CKDIVSEL_CON0 Register SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 513 of 1067

MT6359 PMIC Datasheet Confidential A 00000C1C

BM_TOP_CKDIVSEL_CON0_CLR BM_TOP_CKDIVSEL_CON0 Register CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000C1E

Description

BM_TOP_CKHWEN_CON0

BM_TOP_CKHWEN Control Register 0

0000000F

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000C20

Description

BM_TOP_CKHWEN_CON0_SET BM_TOP_CKHWEN_CON0 Register SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000C22

Description

BM_TOP_CKHWEN_CON0_CLR BM_TOP_CKHWEN_CON0 Register CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 514 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00000C24

Description

BM_TOP_CKTST_CON0

BM_TOP_CKTST Control Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000C26

Description

BM_TOP_RST_CON0

BM_TOP_RST Control Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000C28

Description

BM_TOP_RST_CON0_SET

BM_TOP_RST_CON0 Register SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 515 of 1067

MT6359 PMIC Datasheet Confidential A 00000C2A

BM_TOP_RST_CON0_CLR

BM_TOP_RST_CON0 Register CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000C2C

Description

BM_TOP_RST_CON1

BM_TOP_RST Control Register 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000C2E

Description

BM_TOP_RST_CON1_SET

BM_TOP_RST_CON1 Register SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000C30

Description

BM_TOP_RST_CON1_CLR

BM_TOP_RST_CON1 Register CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 516 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00000C32

Description

BM_TOP_INT_CON0

BM_TOP_INT Control Register 0

Bit Name Type Reset

31

30

29

28

27

26

25

24

Bit

15

14

13

12

11

10

9

8

RG_INT RG_INT _EN_F _EN_F G_CHA G_DISC RGE HARGE

Name Type Reset Bit(s) 12

RW

RW

0

0

Name RG_INT_EN_FG_CHARGE

11

RG_INT_EN_FG_DISCHARGE

9

RG_INT_EN_FG_IAVG_L

8

RG_INT_EN_FG_IAVG_H

7

RG_INT_EN_FG_N_CHARGE_L

4

RG_INT_EN_FG_ZCV

3

RG_INT_EN_FG_CUR_L

2

RG_INT_EN_FG_CUR_H

1

RG_INT_EN_FG_BAT_L

0

RG_INT_EN_FG_BAT_H

MediaTek Proprietary and Confidential.

23

7 RG_INT RG_INT RG_INT _EN_F _EN_F _EN_F G_N_C G_IAV G_IAV HARGE G_L G_H _L RW RW RW 0

0

00000000

22

21

20

19

18

17

16

6

5

4

3

2

1

0

0

RG_INT RG_INT RG_INT RG_INT RG_INT _EN_F _EN_F _EN_F _EN_F _EN_F G_CUR G_CUR G_BAT G_BAT G_ZCV _L _H _L _H RW

RW

RW

RW

RW

0

0

0

0

0

Description Enables FG_CHARGE interrupt 1'b0: Not issue interrupt 1'b1: Issue interrupt Enables FG_DISCHARGE interrupt 1'b0: Not issue interrupt 1'b1: Issue interrupt Enables FG_IAVG_L interrupt 1'b0: Not issue interrupt 1'b1: Issue interrupt Enables FG_IAVG_H interrupt 1'b0: Not issue interrupt 1'b1: Issue interrupt Enables FG_N_CHARGE_L interrupt 1'b0: Not issue interrupt 1'b1: Issue interrupt Enables FG_ZCV interrupt 1'b0: Not issue interrupt 1'b1: Issue interrupt Enables FG_CUR_L interrupt 1'b0: Not issue interrupt 1'b1: Issue interrupt Enables FG_CUR_H interrupt 1'b0: Not issue interrupt 1'b1: Issue interrupt Enables FG_BAT_L interrupt 1'b0: Not issue interrupt 1'b1: Issue interrupt Enables FG_BAT_H interrupt 1'b0: Not issue interrupt 1'b1: Issue interrupt

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 517 of 1067

MT6359 PMIC Datasheet Confidential A 00000C34

BM_TOP_INT_CON0_SET

BM_TOP_INT Control Register 0 SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

BM_TOP_INT_CON0_SET W1 0 0 0 0

0

0

0

0

0

0

Bit(s) 15:0

0

0

0

0

0

Name BM_TOP_INT_CON0_SET

00000C36

Description Sets up BM_TOP_INT_CON0 1'b0: Not set 1'b1: Set

BM_TOP_INT_CON0_CLR

BM_TOP_INT Control Register 0 CLR

Bit Name Type Reset

31

30

29

28

27

26

Bit Name Type Reset

15

14

13

12

11

Bit(s) 15:0

0

0

0

0

0

24

23

22

21

20

19

18

17

16

10

9

8

7

6

5

4

3

2

1

0

0

BM_TOP_INT_CON0_CLR W1 0 0 0 0

0

0

0

0

0

0

19

18

17

16

1

0

Name BM_TOP_INT_CON0_CLR

00000C38

00000000

25

Description Clears BM_TOP_INT_CON0 1'b0: Not clear 1'b1: Clear

BM_TOP_INT_CON1

BM_TOP_INT Control Register 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

Bit

15

14

13

12

11

10

9

8

7

6

5

4

Name

Type Reset Bit(s) 4

3

3 2 RG_INT RG_INT RG_INT _EN_B _EN_B _EN_BI ATON_ ATON_ F BAT_O BAT_IN UT RW RW RW 0

Name RG_INT_EN_BIF

RG_INT_EN_BATON_BAT_OUT

MediaTek Proprietary and Confidential.

0

0

RG_INT _EN_B ATON_ LV RW 0

Description Enables BIF interrupt 1'b0: Not issue interrupt 1'b1: Issue interrupt Enables BATON_BAT_OUT interrupt 1'b0: Not issue interrupt 1'b1: Issue interrupt

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 518 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 2

0

Name RG_INT_EN_BATON_BAT_IN

Description Enables BATON_BAT_IN interrupt 1'b0: Not issue interrupt 1'b1: Issue interrupt Enables BATON_LV interrupt 1'b0: Not issue interrupt 1'b1: Issue interrupt

RG_INT_EN_BATON_LV

00000C3A

BM_TOP_INT_CON1_SET

BM_TOP_INT Control Register 1 SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

BM_TOP_INT_CON1_SET W1 0 0 0 0

0

0

0

0

0

0

Bit(s) 15:0

0

0

0

0

0

Name BM_TOP_INT_CON1_SET

00000C3C

Description Sets up BM_TOP_INT_CON1 1'b0: Not set 1'b1: Set

BM_TOP_INT_CON1_CLR

BM_TOP_INT Control Register 1 CLR

Bit Name Type Reset

31

30

29

28

27

26

Bit Name Type Reset

15

14

13

12

11

Bit(s) 15:0

0

0

0

0

Name BM_TOP_INT_CON1_CLR

MediaTek Proprietary and Confidential.

0

00000000

25

24

23

22

21

20

19

18

17

16

10

9

8

7

6

5

4

3

2

1

0

0

BM_TOP_INT_CON1_CLR W1 0 0 0 0

0

0

0

0

0

0

Description Clears BM_TOP_INT_CON1 1'b0: Not clear 1'b1: Clear

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 519 of 1067

MT6359 PMIC Datasheet Confidential A 00000C3E

BM_TOP_INT_MASK_CON0

Bit Name Type Reset

31

30

29

28

Bit

15

14

13

12

Name

Type Reset Bit(s) 12

27

11 RG_INT RG_INT _MASK _MASK _FG_DI _FG_C SCHAR HARGE GE RW RW 0

0

Name RG_INT_MASK_FG_CHARGE

11

RG_INT_MASK_FG_DISCHARGE

9

RG_INT_MASK_FG_IAVG_L

8

RG_INT_MASK_FG_IAVG_H

7

RG_INT_MASK_FG_N_CHARGE_L

4

RG_INT_MASK_FG_ZCV

3

RG_INT_MASK_FG_CUR_L

2

RG_INT_MASK_FG_CUR_H

1

RG_INT_MASK_FG_BAT_L

0

RG_INT_MASK_FG_BAT_H

MediaTek Proprietary and Confidential.

BM_TOP_INT_MASK Control Register 0

26

25

24

10

9

8

23

7 RG_INT RG_INT RG_INT _MASK _MASK _MASK _FG_N _FG_IA _FG_IA _CHAR VG_L VG_H GE_L RW RW RW 0

0

00000000

22

21

20

19

18

17

16

6

5

4

3

2

1

0

RG_INT RG_INT RG_INT RG_INT RG_INT _MASK _MASK _MASK _MASK _MASK _FG_ZC _FG_C _FG_C _FG_B _FG_B V UR_L UR_H AT_L AT_H RW

RW

RW

RW

RW

0

0

0

0

0

0

Description Masks FG_CHARGE interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks FG_DISCHARGE interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks FG_IAVG_L interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks FG_IAVG_H interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks FG_N_CHARGE_L interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks FG_ZCV interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks FG_CUR_L interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks FG_CUR_H interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks FG_BAT_L interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks FG_BAT_H interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 520 of 1067

MT6359 PMIC Datasheet Confidential A 00000C40

BM_TOP_INT_MASK_CON0_SET

Bit Name Type Reset

31

30

29

28

27

26

Bit Name Type Reset

15

14

13

12

11

10

Bit(s) 15:0

0

0

0

0

0

0

Name BM_TOP_INT_MASK_CON0_SET

00000C42

23

22

21

20

19

18

17

16

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

BM_TOP_INT_MASK_CON0_SET W1 0 0 0 0

BM_TOP_INT_MASK_CON0_CLR

Bit Name Type Reset

30

29

28

27

26

Bit Name Type Reset

15

14

13

12

11

10

0

0

0

0

0

0

Name BM_TOP_INT_MASK_CON0_CLR

00000C44

BM_TOP_INT Mask Control Register 0 CLR 24

23

22

21

20

19

18

17

16

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

19

18

17

16

1

0

BM_TOP_INT_MASK_CON0_CLR W1 0 0 0 0

Description Clears BM_TOP_INT_MASK_CON0 1'b0: Not clear 1'b1: Clear

BM_TOP_INT_MASK_CON1

BM_TOP_INT_MASK Control Register 1

31

30

29

28

27

26

25

24

23

22

21

20

Bit

15

14

13

12

11

10

9

8

7

6

5

4

Type Reset Bit(s) 4

3

RG_INT_MASK_BATON_BAT_OUT

MediaTek Proprietary and Confidential.

00000000

3 2 RG_INT RG_INT RG_INT _MASK _MASK _MASK _BATO _BATO _BIF N_BAT N_BAT _OUT _IN RW RW RW 0

Name RG_INT_MASK_BIF

00000000

25

Bit Name Type Reset

Name

00000000

24

Description Sets up BM_TOP_INT_MASK_CON0 1'b0: Not set 1'b1: Set

31

Bit(s) 15:0

BM_TOP_INT Mask Control Register 0 SET 25

0

0

RG_INT _MASK _BATO N_LV RW 0

Description Masks BIF interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks BATON_BAT_OUT interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 521 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 2

0

Name RG_INT_MASK_BATON_BAT_IN

Description Masks BATON_BAT_IN interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks BATON_LV interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status

RG_INT_MASK_BATON_LV

00000C46

BM_TOP_INT_MASK_CON1_SET

BM_TOP_INT Mask Control Register 1 SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

Bit(s) 15:0

0

0

0

0

0

0

Name BM_TOP_INT_MASK_CON1_SET

00000C48

Description Sets up BM_TOP_INT_MASK_CON1 1'b0: Not set 1'b1: Set

BM_TOP_INT_MASK_CON1_CLR BM_TOP_INT Mask Control Register 1 CLR

Bit Name Type Reset

31

30

29

28

27

26

Bit Name Type Reset

15

14

13

12

11

10

Bit(s) 15:0

BM_TOP_INT_MASK_CON1_SET W1 0 0 0 0

0

0

0

0

0

Name BM_TOP_INT_MASK_CON1_CLR

MediaTek Proprietary and Confidential.

0

00000000

25

24

23

22

21

20

19

18

17

16

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

BM_TOP_INT_MASK_CON1_CLR W1 0 0 0 0

Description Clears BM_TOP_INT_MASK_CON1 1'b0: Not clear 1'b1: Clear

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 522 of 1067

MT6359 PMIC Datasheet Confidential A 00000C4A

BM_TOP_INT_STATUS0

BM_TOP_INT Status Register 0

Bit Name Type Reset

31

30

29

28

27

26

25

24

Bit

15

14

13

12

11

10

9

8

RG_INT RG_INT _STAT _STAT US_FG US_FG _CHAR _DISCH GE ARGE

Name

Type Reset Bit(s) 12

W1C

W1C

0

0

Name RG_INT_STATUS_FG_CHARGE

11

RG_INT_STATUS_FG_DISCHARGE

9

RG_INT_STATUS_FG_IAVG_L

8

RG_INT_STATUS_FG_IAVG_H

7

RG_INT_STATUS_FG_N_CHARGE_L

4

RG_INT_STATUS_FG_ZCV

3

RG_INT_STATUS_FG_CUR_L

2

RG_INT_STATUS_FG_CUR_H

1

RG_INT_STATUS_FG_BAT_L

0

RG_INT_STATUS_FG_BAT_H

MediaTek Proprietary and Confidential.

23

7 RG_INT RG_INT RG_INT _STAT _STAT _STAT US_FG US_FG US_FG _N_CH _IAVG_ _IAVG_ ARGE_ L H L W1C W1C W1C 0

0

00000000

22

21

20

19

18

17

16

6

5

4

3

2

1

0

0

RG_INT RG_INT RG_INT RG_INT RG_INT _STAT _STAT _STAT _STAT _STAT US_FG US_FG US_FG US_FG US_FG _CUR_ _BAT_ _ZCV _CUR_L _BAT_L H H W1C

W1C

W1C

W1C

W1C

0

0

0

0

0

Description FG_CHARGE interrupt status 1'b0: No interrupt issued 1'b1: Interrupt issued FG_DISCHARGE interrupt status 1'b0: No interrupt issued 1'b1: Interrupt issued FG_IAVG_L interrupt status 1'b0: No interrupt issued 1'b1: Interrupt issued FG_IAVG_H interrupt status 1'b0: No interrupt issued 1'b1: Interrupt issued FG_N_CHARGE_L interrupt status 1'b0: No interrupt issued 1'b1: Interrupt issued FG_ZCV interrupt status 1'b0: No interrupt issued 1'b1: Interrupt issued FG_CUR_L interrupt status 1'b0: No interrupt issued 1'b1: Interrupt issued FG_CUR_H interrupt status 1'b0: No interrupt issued 1'b1: Interrupt issued FG_BAT_L interrupt status 1'b0: No interrupt issued 1'b1: Interrupt issued FG_BAT_H interrupt status 1'b0: No interrupt issued 1'b1: Interrupt issued

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Page 523 of 1067

MT6359 PMIC Datasheet Confidential A 00000C4C

BM_TOP_INT_STATUS1

BM_TOP_INT Status Register 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

Bit

15

14

13

12

11

10

9

8

7

6

5

4

Name

Type Reset Bit(s) 4

Name RG_INT_STATUS_BIF

3

RG_INT_STATUS_BATON_BAT_OUT

2

RG_INT_STATUS_BATON_BAT_IN

0

RG_INT_STATUS_BATON_LV

00000C4E Bit Name Type Reset

30

29

28

Bit

15

14

13

12

Name

Type Reset

11

9

18

3 2 RG_INT RG_INT _STAT RG_INT _STAT US_BA _STAT US_BA TON_B US_BIF TON_B AT_OU AT_IN T W1C W1C W1C 0

0

0

27

11 RG_INT RG_INT _RAW_ _RAW_ STATUS STATUS _FG_DI _FG_C SCHAR HARGE GE RO RO 0

0

17

16

1

0 RG_INT _STAT US_BA TON_L V W1C 0

Description BIF interrupt status 1'b0: No interrupt issued 1'b1: Interrupt issued BATON_BAT_OUT interrupt status 1'b0: No interrupt issued 1'b1: Interrupt issued BATON_BAT_IN interrupt status 1'b0: No interrupt issued 1'b1: Interrupt issued BATON_LV interrupt status 1'b0: No interrupt issued 1'b1: Interrupt issued

BM_TOP_INT_RAW_STATUS0 BM_TOP_INT Raw Status Register 0 31

Bit(s) 12

19

26

25

24

10

9

8

23

7 RG_INT RG_INT RG_INT _RAW_ _RAW_ _RAW_ STATUS STATUS STATUS _FG_N _FG_IA _FG_IA _CHAR VG_L VG_H GE_L RO RO RO 0

0

00000000

22

21

20

19

18

17

16

6

5

4

3

2

1

0

0

RG_INT RG_INT RG_INT RG_INT RG_INT _RAW_ _RAW_ _RAW_ _RAW_ _RAW_ STATUS STATUS STATUS STATUS STATU _FG_ZC _FG_C _FG_C _FG_B S_FG_B V UR_L UR_H AT_L AT_H RO

RO

RO

RO

RO

0

0

0

0

0

Name RG_INT_RAW_STATUS_FG_CHARGE

Description FG_CHARGE raw interrupt status 1'b0: No interrupt issued 1'b1: Interrupt issued RG_INT_RAW_STATUS_FG_DISCHARGE FG_DISCHARGE raw interrupt status 1'b0: No interrupt issued 1'b1: Interrupt issued RG_INT_RAW_STATUS_FG_IAVG_L FG_IAVG_L raw interrupt status 1'b0: No interrupt issued 1'b1: Interrupt issued

MediaTek Proprietary and Confidential.

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Page 524 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 8

7

4

3

2

1

0

Name RG_INT_RAW_STATUS_FG_IAVG_H

Description FG_IAVG_H raw interrupt status 1'b0: No interrupt issued 1'b1: Interrupt issued RG_INT_RAW_STATUS_FG_N_CHARGE_ FG_N_CHARGE_L raw interrupt status L 1'b0: No interrupt issued 1'b1: Interrupt issued RG_INT_RAW_STATUS_FG_ZCV FG_ZCV raw interrupt status 1'b0: No interrupt issued 1'b1: Interrupt issued RG_INT_RAW_STATUS_FG_CUR_L FG_CUR_L raw interrupt status 1'b0: No interrupt issued 1'b1: Interrupt issued RG_INT_RAW_STATUS_FG_CUR_H FG_CUR_H raw interrupt status 1'b0: No interrupt issued 1'b1: Interrupt issued RG_INT_RAW_STATUS_FG_BAT_L FG_BAT_L raw interrupt status 1'b0: No interrupt issued 1'b1: Interrupt issued RG_INT_RAW_STATUS_FG_BAT_H FG_BAT_H raw interrupt status 1'b0: No interrupt issued 1'b1: Interrupt issued

00000C50

BM_TOP_INT_RAW_STATUS1 BM_TOP_INT Raw Status Register 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

Bit

15

14

13

12

11

10

9

8

7

6

5

4

Name

Type Reset Bit(s) 4

3

2

0

19

18

3 2 RG_INT RG_INT RG_INT _RAW_ _RAW_ _RAW_ STATUS STATUS STATUS _BATO _BATO _BIF N_BAT N_BAT _OUT _IN RO RO RO 0

0

0

17

16

1

0 RG_INT _RAW_ STATU S_BAT ON_LV RO 0

Name RG_INT_RAW_STATUS_BIF

Description BIF raw interrupt status 1'b0: No interrupt issued 1'b1: Interrupt issued RG_INT_RAW_STATUS_BATON_BAT_OU BATON_BAT_OUT raw interrupt status T 1'b0: No interrupt issued 1'b1: Interrupt issued RG_INT_RAW_STATUS_BATON_BAT_IN BATON_BAT_IN raw interrupt status 1'b0: No interrupt issued 1'b1: Interrupt issued RG_INT_RAW_STATUS_BATON_LV BATON_LV raw interrupt status 1'b0: No interrupt issued 1'b1: Interrupt issued

MediaTek Proprietary and Confidential.

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Page 525 of 1067

MT6359 PMIC Datasheet Confidential A 00000C52

BM_TOP_INT_MISC_CON

BM_TOP_INT MISC Control Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0 POLARI TY RW

Name Type Reset Bit(s) 0

0

Name POLARITY

00000C54

Description Inverts interrupt source polarity 1'b0: Not invert interrupt source polarity 1'b1: Invert interrupt source polarity

BM_TOP_DBG_CON

BM_TOP_DBG_CON

000000FF

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000C56

Description

BM_TOP_RSV0

BM_TOP Reserved Register 0

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

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Page 526 of 1067

MT6359 PMIC Datasheet Confidential A 00000C58

BM_WKEY0

BM Write Protection Key 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000C5A

Description

BM_WKEY1

BM Write Protection Key 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000C5C

Description

BM_WKEY2

BM Write Protection Key 2

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000C80

Description

FGADC_ANA_DSN_ID

FGADC_ANA Design ID Register

00004222

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

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Page 527 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00000C82

Description

FGADC_ANA_DSN_REV0

FGADC_ANA Design Revision Register 0

00001312

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000C84

Description

FGADC_ANA_DSN_DBI

FGADC_ANA Design Bank Information Register

00000C00

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000C86

Description

FGADC_ANA_DSN_DXI

FGADC_ANA Design Extra Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

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Page 528 of 1067

MT6359 PMIC Datasheet Confidential A 00000C88

FGADC_ANA_CON0

FGADC_ANA Control Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000C8A

Description

FGADC_ANA_TEST_CON0

FGADC_ANA_TEST Control Register 0

00000500

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000C8C

Description

FGADC_ANA_ELR_NUM

FGADC_ANA Number of ELR Register

00000002

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000C8E

Description

FGADC_ANA_ELR0

FGADC_ANA ELR Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

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Page 529 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00000D00

Description

FGADC0_DSN_ID

FGADC0 Design ID Register

00005500

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000D02

Description

FGADC0_DSN_REV0

FGADC0 Design Revision Register 0

00001200

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000D04

Description

FGADC0_DSN_DBI

FGADC0 Design Bank Information Register

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 530 of 1067

MT6359 PMIC Datasheet Confidential A 00000D06

FGADC0_DSN_DXI

FGADC0 Design Extra Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000D08

Description

FGADC_CON0

FGADC Control Register 0

00002159

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000D0A

Description

FGADC_CON1

FGADC Control Register 1

00000030

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000D0C

Description

FGADC_CON2

FGADC Control Register 2

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 531 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00000D0E

Description

FGADC_CON3

FGADC Control Register 3

00000708

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000D10

Description

FGADC_CON4

FGADC Control Register 4

00005101

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000D12

Description

FGADC_CON5

FGADC Control Register 5

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 532 of 1067

MT6359 PMIC Datasheet Confidential A 00000D14

FGADC_RST_CON0

FGADC_RST Control Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000D16

Description

FGADC_CAR_CON0

FGADC_CAR Control Register 0

Bit Name Type Reset

31

30

29

28

27

26

25

Bit Name Type Reset

15

14

13

12

11

10

9

Bit(s) 15:0

0

0

0

0

0

0

Name FG_CAR_15_00

00000D18

0

FGADC_CAR_CON1 30

29

28

27

26

25

Bit Name Type Reset

15

14

13

12

11

10

9

Bit(s) 15:0

0

0

0

0

Name FG_CAR_31_16

00000D1C

22

21

20

19

18

17

16

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

FG_CAR_15_00 RO 0 0

FGADC_CAR Control Register 1

31

0

23

Description Current charge value [15:0] (signed value)

Bit Name Type Reset

0

00000000

24

0

00000000

24

23

22

21

20

19

18

17

16

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

FG_CAR_31_16 RO 0 0

Description Current charge value [31:16] (signed value)

FGADC_CARTH_CON0

FGADC_CARTH Control Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 533 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00000D1E

Description

FGADC_CARTH_CON1

FGADC_CARTH Control Register 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000D20

Description

FGADC_CARTH_CON2

FGADC_CARTH Control Register 2

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000D22

Description

FGADC_CARTH_CON3

FGADC_CARTH Control Register 3

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 534 of 1067

MT6359 PMIC Datasheet Confidential A 00000D24

FGADC_NCAR_CON0

FGADC_NCAR Control Register 0

Bit Name Type Reset

31

30

29

28

27

26

25

Bit Name Type Reset

15

14

13

12

11

10

9

Bit(s) 15:0

0

0

0

0

0

0

Name FG_NCAR_15_00

00000D26

0

00000000

24

23

22

21

20

19

18

17

16

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

FG_NCAR_15_00 RO 0 0

Description Current n_charge value [15:0] (signed value)

FGADC_NCAR_CON1

FGADC_NCAR Control Register 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

Bit(s) 15:0

0

0

0

0

0

0

Name FG_NCAR_31_16

00000D28

0

FG_NCAR_31_16 RO 0 0

Description Current n_charge value [31:16] (signed value)

FGADC_NCAR_CON2

FGADC_NCAR Control Register 2

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000D2A

Description

FGADC_NCAR_CON3

FGADC_NCAR Control Register 3

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 535 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00000D2C

Description

FGADC_IAVG_CON0

FGADC_IAVG Control Register 0

Bit Name Type Reset

31

30

29

28

27

26

25

Bit Name Type Reset

15

14

13

12

11

10

9

Bit(s) 15:0

0

0

0

0

0

0

Name FG_IAVG_15_00

00000D2E

15 FG_IAV Name G_VLD RO Type

Bit

Reset

23

22

21

20

19

18

17

16

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

FG_IAVG_15_00 RO 0 0

FGADC_IAVG Control Register 1

00000000

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

FG_IAVG_27_16 RO

0

0

Bit(s) 15

Name FG_IAVG_VLD

11:0

FG_IAVG_27_16

00000D30

24

Description Current FGADC average current [15:0] (signed value) Unit of FG_IAVG is [LSB of charge/32].

FGADC_IAVG_CON1 31

Bit Name Type Reset

0

00000000

0

0

0

0

0

0

Description FGADC average current valid 1'b0: Invalid 1'b1: Valid Current FGADC average current [27:16] (signed value)

FGADC_IAVG_CON2

FGADC_IAVG Control Register 2

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 536 of 1067

MT6359 PMIC Datasheet Confidential A 00000D32

FGADC_IAVG_CON3

FGADC_IAVG Control Register 3

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000D34

Description

FGADC_IAVG_CON4

FGADC_IAVG Control Register 4

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000D36

Description

FGADC_IAVG_CON5

FGADC_IAVG Control Register 5

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000D38

Description

FGADC_NTER_CON0

FGADC_NTER Control Register 0

Bit Name Type Reset

31

30

29

28

27

26

25

Bit Name Type Reset

15

14

13

12

11

10

9

0

0

MediaTek Proprietary and Confidential.

0

0

0

0

0

00000000

24

23

22

21

20

19

18

17

16

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

FG_NTER_15_00 RO 0 0

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 537 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 15:0

Name FG_NTER_15_00

00000D3A

Description Time value [15:0]

FGADC_NTER_CON1

FGADC_NTER Control Register 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

Bit(s) 13:0

FG_NTER_29_16 RO 0

0

0

0

Name FG_NTER_29_16

00000D3E

0

0

0

0

Description Time value [29:16]

FGADC_SON_CON0

FGADC_SON Control Register 0

0000001F

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000D40

Description

FGADC_SON_CON1

FGADC_SON Control Register 1

00000014

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 538 of 1067

MT6359 PMIC Datasheet Confidential A 00000D42

FGADC_SON_CON2

FGADC_SON Control Register 2

000000FF

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000D44

Description

FGADC_SOFF_CON0

FGADC_SOFF Control Register 0

0000001F

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000D46

Description

FGADC_SOFF_CON1

FGADC_SOFF Control Register 1

00000014

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000D48

Description

FGADC_SOFF_CON2

FGADC_SOFF Control Register 2

000000FF

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 539 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00000D4A

Description

FGADC_SOFF_CON3

FGADC_SOFF Control Register 3

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000D4C

Description

FGADC_SOFF_CON4

FGADC_SOFF Control Register 4

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000D4E

Description

FGADC_ZCV_CON0

FGADC_ZCV Control Register 0

00000006

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 540 of 1067

MT6359 PMIC Datasheet Confidential A 00000D50

FGADC_ZCV_CON1

FGADC_ZCV Control Register 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000D52

Description

FGADC_ZCV_CON2

FGADC_ZCV Control Register 2

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000D54

Description

FGADC_ZCV_CON3

FGADC_ZCV Control Register 3

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000D58

Description

FGADC_ZCVTH_CON0

FGADC_ZCVTH Control Register 0

0000BCAC

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 541 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00000D5A

Description

FGADC_ZCVTH_CON1

FGADC_ZCVTH Control Register 1

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000D80

Description

FGADC1_DSN_ID

FGADC1 Design ID Register

00005500

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000D82

Description

FGADC1_DSN_REV0

FGADC1 Design Revision Register 0

00001200

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 542 of 1067

MT6359 PMIC Datasheet Confidential A 00000D84

FGADC1_DSN_DBI

FGADC1 Design Bank Information Register

00000005

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000D86

Description

FGADC1_DSN_DXI

FGADC1 Design Extra Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000D88

Description

FGADC_R_CON0

FGADC_R Control Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000D8A

Description

FGADC_CUR_CON0

FGADC_CUR Control Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

FG_CURRENT_OUT RO 0 0 0 0

0

0

0

0

0

0

0

0

MediaTek Proprietary and Confidential.

0

0

0

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 543 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 15:0

Name FG_CURRENT_OUT

00000D8C

Description Current output charge of first CIC stage [15:0] (signed value)

FGADC_CUR_CON1

FGADC_CUR Control Register 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000D8E

Description

FGADC_CUR_CON2

FGADC_CUR Control Register 2

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000D90

Description

FGADC_CUR_CON3

FGADC_CUR Control Register 3

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 544 of 1067

MT6359 PMIC Datasheet Confidential A 00000D92

FGADC_OFFSET_CON0

FGADC_OFFSET Control Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000D94

Description

FGADC_OFFSET_CON1

FGADC_OFFSET Control Register 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000D96

Description

FGADC_GAIN_CON0

FGADC_GAIN Control Register 0

00000400

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000D98

Description

FGADC_TEST_CON0

FGADC_TEST Control Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 545 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00000D9A

Description

SYSTEM_INFO_CON0

SYSTEM_INFO Control Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000D9C

Description

SYSTEM_INFO_CON1

SYSTEM_INFO Control Register 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000D9E

Description

SYSTEM_INFO_CON2

SYSTEM_INFO Control Register 2

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 546 of 1067

MT6359 PMIC Datasheet Confidential A 00000E00

BATON_ANA_DSN_ID

BATON_ANA Design ID Register

0000A028

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000E02

Description

BATON_ANA_DSN_REV0

BATON_ANA Design Revision Register 0

00000013

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000E04

Description

BATON_ANA_DSN_DBI

BATON_ANA Design Bank Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000E06

Description

BATON_ANA_DSN_DXI

BATON_ANA Design Extra Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 547 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00000E08

Description

BATON_ANA_CON0

BATON Analog Control Register 0

00000005

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2 RG_QI_ BATON _LT_EN RW

1

0 RG_BA TON_E N RW

Name Type Reset Bit(s) 2

0

1

Name RG_QI_BATON_LT_EN

Description Enables Battery-on HW low temperature detection 0: Disable 1: Enable Enables BATON battery detection comparator 0: Disable 1: Enable (default)

RG_BATON_EN

00000E0A

1

BATON_ANA_MON0

BATON Analog Monitor Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000E0C

Description

BIF_ANA_MON0

BIF Analog Monitor Register 0

00000002

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

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Page 548 of 1067

MT6359 PMIC Datasheet Confidential A 00000E80

BATON_DSN_ID

BATON Design ID Register

00005900

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000E82

Description

BATON_DSN_REV0

BATON Design Revision Register 0

00002000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000E84

Description

BATON_DSN_DBI

BATON Design Bank Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000E86

Description

BATON_DSN_DXI

BATON Design Extra Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 549 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00000E88

Description

BATON_CON0

BATON Control Register 0

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

Bit

15

14

13

12

11

10

9

8

7

6

5

4

Name Type Reset

19

Name RG_BATON_DEBOUNCE_THD

1:0

RG_BATON_DEBOUNCE_WND

00000E8A

17

16

3 2 1 0 RG_BATON_DE RG_BATON_DE BOUNCE_THD BOUNCE_WND RW RW 0

Bit(s) 3:2

18

0

0

1

Description Battery status debounce threshold setting in decision windows 2'b00: 4/8 2'b01: 3/8 2'b10: 2/8 2'b11: 1/8 Battery status debounce decision window setting 2'b00: 6T of 32 kHz clock 2'b01: 11T of 32 kHz clock 2'b10: 21T of 32 kHz clock 2'b11: 41T of 32 kHz clock

BATON_CON1

BATON Control Register 1

0000FA00

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000E8C

Description

BATON_CON2

BATON Control Register 2

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 550 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00000F00

Description

BIF_DSN_ID

BIF Design ID Register

00005800

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000F02

Description

BIF_DSN_REV0

BIF Design Revision Register 0

00001000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000F04

Description

BIF_DSN_DBI

BIF Design Bank Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

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Page 551 of 1067

MT6359 PMIC Datasheet Confidential A 00000F06

BIF_DSN_DXI

BIF Design Extra Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

22

21

20

19

18

17

16

6

5

4

3

2

1

0

0

00000F08

Description

BIF_CON0

BIF Control Register 0

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

Bit(s) 10:0

BIF_COMMAND_0 RW 0

Name BIF_COMMAND_0

00000F0A

0

0

0

0

0

0

0

0

0

22

21

20

19

18

17

16

6

5

4

3

2

1

0

0

0

0

0

Description Command queue 0

BIF_CON1

BIF Control Register 1

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

Bit(s) 10:0

00000000

00000000

BIF_COMMAND_1 RW 0

Name BIF_COMMAND_1

00000F0C

0

0

0

0

0

Description Command queue 1

BIF_CON2

BIF Control Register 2

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

MediaTek Proprietary and Confidential.

0

00000000 22

21

20

19

18

17

16

6

5

4

3

2

1

0

0

0

0

0

BIF_COMMAND_2 RW 0

0

0

0

0

0

0

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 552 of 1067

MT6359 PMIC Datasheet Confidential A

Bit(s) 10:0

Name BIF_COMMAND_2

00000F0E

Description Command queue 2

BIF_CON3

BIF Control Register 3

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

Bit(s) 10:0

BIF_COMMAND_3 RW 0

Name BIF_COMMAND_3

00000F10

0

0

0

BIF_CON4

0

0

0

0

22

21

20

19

18

17

16

6

5

4

3

2

1

0

0

BIF Control Register 4

31

30

29

28

27

26

25

24

23

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

00000000

BIF_COMMAND_4 RW 0

Name BIF_COMMAND_4

00000F12

0

0

0

0

0

0

0

0

0

22

21

20

19

18

17

16

6

5

4

3

2

1

0

0

0

0

0

Description Command queue 4

BIF_CON5

BIF Control Register 5

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

Bit(s) 10:0

0

Description Command queue 3

Bit Name Type Reset

Bit(s) 10:0

0

00000000

BIF_COMMAND_5 RW 0

Name BIF_COMMAND_5

MediaTek Proprietary and Confidential.

0

0

0

0

0

0

Description Command queue 5

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 553 of 1067

MT6359 PMIC Datasheet Confidential A 00000F14

BIF_CON6

BIF Control Register 6

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

Bit(s) 10:0

00000000 22

21

20

19

18

17

16

6

5

4

3

2

1

0

0

BIF_COMMAND_6 RW 0

Name BIF_COMMAND_6

00000F16

0

0

0

0

0

0

0

0

0

Description Command queue 6

BIF_CON7

BIF Control Register 7

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

Bit(s) 10:0

BIF_COMMAND_7 RW 0

Name BIF_COMMAND_7

00000F18

0

0

0

0

0

0

0

0

22

21

20

19

18

17

16

6

5

4

3

2

1

0

0

0

0

0

Description Command queue 7

BIF_CON8

BIF Control Register 8

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

Bit(s) 10:0

0

00000000

BIF_COMMAND_8 RW 0

Name BIF_COMMAND_8

MediaTek Proprietary and Confidential.

0

0

0

0

0

0

Description Command queue 8

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 554 of 1067

MT6359 PMIC Datasheet Confidential A 00000F1A

BIF_CON9

BIF Control Register 9

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

Bit(s) 10:0

00000000 22

21

20

19

18

17

16

6

5

4

3

2

1

0

0

BIF_COMMAND_9 RW 0

Name BIF_COMMAND_9

00000F1C

0

0

0

0

0

0

0

0

0

Description Command queue 9

BIF_CON10

BIF Control Register 10

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

Bit(s) 10:0

BIF_COMMAND_10 RW 0

Name BIF_COMMAND_10

00000F1E

0

0

0

0

0

0

0

0

22

21

20

19

18

17

16

6

5

4

3

2

1

0

0

0

0

0

Description Command queue 10

BIF_CON11

BIF Control Register 11

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

Bit(s) 10:0

0

00000000

BIF_COMMAND_11 RW 0

Name BIF_COMMAND_11

MediaTek Proprietary and Confidential.

0

0

0

0

0

0

Description Command queue 11

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 555 of 1067

MT6359 PMIC Datasheet Confidential A 00000F20

BIF_CON12

BIF Control Register 12

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

Bit(s) 10:0

00000000 22

21

20

19

18

17

16

6

5

4

3

2

1

0

0

BIF_COMMAND_12 RW 0

Name BIF_COMMAND_12

00000F22

0

0

0

0

0

0

0

0

0

Description Command queue 12

BIF_CON13

BIF Control Register 13

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

Bit(s) 10:0

BIF_COMMAND_13 RW 0

Name BIF_COMMAND_13

00000F24

0

0

0

0

0

0

0

0

22

21

20

19

18

17

16

6

5

4

3

2

1

0

0

0

0

0

Description Command queue 13

BIF_CON14

BIF Control Register 14

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

Bit(s) 10:0

0

00000000

BIF_COMMAND_14 RW 0

Name BIF_COMMAND_14

MediaTek Proprietary and Confidential.

0

0

0

0

0

0

Description Command queue 14

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 556 of 1067

MT6359 PMIC Datasheet Confidential A 00000F26

BIF_CON15

BIF Control Register 15

Bit Name Type Reset

31

30

29

28

27

26

Bit

15

14

13

12

11

10

Name

BIF_TRASFER_NUM

Type Reset

RW

Bit(s) 15:12 9:8

0

1

0

31

30

Bit Name Type Reset

15

14

22

21

20

19

18

17

16

7

6

5

4

3

2

1

0

18

17

16

2

1

0

0

BIF Control Register 16

29

28

27

26

25

24

13

12

11

10

9

8

BIF_STOP_SET 0

0

Name BIF_STOP_SET

8:4

BIF_LOGIC_1_SET

3:0

BIF_LOGIC_0_SET

MediaTek Proprietary and Confidential.

00001431

23

22

21

20

19

7

6

5

4

3

BIF_LOGIC_1_SET

RW 0

00004000

23

Description Total transfer number in command queue Command type 2'b00: Write 2'b01: Read data 2'b10: Read response

BIF_CON16

Bit Name Type Reset

24

9 8 BIF_COMMAN D_TYPE RW 0

Name BIF_TRASFER_NUM BIF_COMMAND_TYPE

00000F28

Bit(s) 15:10

0

25

BIF_LOGIC_0_SET

RW 1

0

1

0

0

0

RW 1

1

0

0

0

1

Description Sets up stop signal spec 6'd0: 0T 6'd1: 1T 6'd2: 2T 6'dN: NT Sets up logic '1' period spec 5'd0: 0T 5'd1: 1T 5'd2: 2T 5'dN: NT Sets up logic '0' period spec 4'd0: 0T 4'd1: 1T 4'd2: 2T 4'dN: NT

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 557 of 1067

MT6359 PMIC Datasheet Confidential A 00000F2A

BIF_CON17

BIF Control Register 17

00001010

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4 BIF_DE BOUNC E_EN RW

3

2

1

0

Name

BIF_READ_EXPECT_NUM

Type Reset

0

Bit(s) 15:12

4

RW 0

0

1

1

Name BIF_READ_EXPECT_NUM

Description Expects the number of read back data 1'b0: 0 1'b1: 1 data package No function 1'b0: Disable 1'b1: Enable

BIF_DEBOUNCE_EN

00000F2C

BIF_CON18

BIF Control Register 18

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0 BIF_TR ASACT _TRIGG ER RW

Name Type Reset Bit(s) 0

0

Name BIF_TRASACT_TRIGGER

00000F2E

Description Trigger signal 1'b1: Trigger BIF module

BIF_CON19

BIF Control Register 19

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12 BIF_RE SPONS E RO

11

10

9

8

7

6

5

4

3

2

1

0

Name Type Reset Bit(s) 12

BIF_DATA_NUM RO

0

Name BIF_RESPONSE

MediaTek Proprietary and Confidential.

0

0

0

0

Description Response result

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 558 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

3:0

Name

BIF_DATA_NUM

00000F30

BIF_CON20 31

Bit Name Type Reset

15 BIF_ER Name R_0 RO Type

Bit

Reset Bit(s) 15

8 7:0

8 7:0

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8 BIF_AC K_0 RO

7

6

5

4

3

2

1

0

1

0

0

BIF_DATA_0 RO 0

0

0

0

0

0

Description Error happens or not 1'b0: No error 1'b1: Error exists. Read back data

BIF_CON21

15 BIF_ER Name R_1 RO Type

Bit(s) 15

28

BIF_ACK_0 BIF_DATA_0

31

00000100

29

Name BIF_ERR_0

Bit

Reset

BIF Control Register 20

30

0

00000F32 Bit Name Type Reset

Description 1'b1: Positive response 1'b0: Negative response Number of read back data

BIF Control Register 21

00000100

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8 BIF_AC K_1 RO

7

6

5

4

3

2

1

0

1

0

0

0

0

0

Name BIF_ERR_1

BIF_ACK_1 BIF_DATA_1

MediaTek Proprietary and Confidential.

BIF_DATA_1 RO 0

0

0

0

Description Error happens or not 1'b0: No error 1'b1: Error exists. Read back data

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 559 of 1067

MT6359 PMIC Datasheet Confidential A 00000F34

BIF_CON22 31

Bit Name Type Reset

15 BIF_ER Name R_2 RO Type

Bit

Reset Bit(s) 15

8 7:0

Reset

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8 BIF_AC K_2 RO

7

6

5

4

3

2

1

0

1

0

0

0

0

0

0

0

0

BIF Control Register 23

00000100

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8 BIF_AC K_3 RO

7

6

5

4

3

2

1

0

1

0

0

BIF_DATA_3 RO 0

0

0

0

0

0

Description Error happens or not 1'b0: No error 1'b1: Error exists. Read back data

BIF_CON24

15 BIF_ER Name R_4 RO Type

RO

Read back data

BIF_ACK_3 BIF_DATA_3

31

BIF_DATA_2

Description Error happens or not 1'b0: No error 1'b1: Error exists.

Name BIF_ERR_3

Bit

Bit(s) 15

25

0

00000F38

Reset

26

BIF_CON23 31

15 BIF_ER Name R_3 RO Type

Bit Name Type Reset

27

BIF_ACK_2 BIF_DATA_2

Bit

8 7:0

28

Name BIF_ERR_2

Bit Name Type Reset

00000100

29

0

00000F36

Bit(s) 15

BIF Control Register 22

30

BIF Control Register 24

00000100

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8 BIF_AC K_4 RO

7

6

5

4

3

2

1

0

1

0

0

0

0

0

Name BIF_ERR_4

MediaTek Proprietary and Confidential.

BIF_DATA_4 RO 0

0

0

0

Description Error happens or not 1'b0: No error 1'b1: Error exists. © 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 560 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 8 7:0

Name BIF_ACK_4 BIF_DATA_4

00000F3A

15 BIF_ER Name R_5 RO Type

Bit

Reset Bit(s) 15

8 7:0

8 7:0

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8 BIF_AC K_5 RO

7

6

5

4

3

2

1

0

1

0

0

0

0

0

0

0

BIF Control Register 26

00000100

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8 BIF_AC K_6 RO

7

6

5

4

3

2

1

0

1

0

0

BIF_DATA_6 RO 0

0

0

0

0

0

Description Error happens or not 1'b0: No error 1'b1: Error exists. Read back data

BIF_CON27

15 BIF_ER Name R_7 RO Type

RO 0

Read back data

BIF_ACK_6 BIF_DATA_6

31

BIF_DATA_5

Description Error happens or not 1'b0: No error 1'b1: Error exists.

Name BIF_ERR_6

Bit

Reset

26

0

00000F3E Bit Name Type Reset

27

BIF_CON26

15 BIF_ER Name R_6 RO Type

Bit(s) 15

28

BIF_ACK_5 BIF_DATA_5

31

00000100

29

Name BIF_ERR_5

Bit

Reset

BIF Control Register 25

30

0

00000F3C Bit Name Type Reset

Read back data

BIF_CON25 31

Bit Name Type Reset

Description

BIF Control Register 27

00000100

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8 BIF_AC K_7 RO

7

6

5

4

3

2

1

0

1

0

0

0

0

0

MediaTek Proprietary and Confidential.

BIF_DATA_7 RO 0

0

0

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

0

Page 561 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 15

8 7:0

Name BIF_ERR_7

BIF_ACK_7 BIF_DATA_7

00000F40

15 BIF_ER Name R_8 RO Type

Bit

Reset

8 7:0

8 7:0

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8 BIF_AC K_8 RO

7

6

5

4

3

2

1

0

1

0

0

BIF_DATA_8 RO 0

0

0

0

0

0

Description Error happens or not 1'b0: No error 1'b1: Error exists. Read back data

BIF_CON29

15 BIF_ER Name R_9 RO Type

Bit(s) 15

28

BIF_ACK_8 BIF_DATA_8

31

00000100

29

Name BIF_ERR_8

Bit

Reset

BIF Control Register 28

30

0

00000F42 Bit Name Type Reset

Read back data

BIF_CON28 31

Bit Name Type Reset

Bit(s) 15

Description Error happens or not 1'b0: No error 1'b1: Error exists.

BIF Control Register 29

00000100

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8 BIF_AC K_9 RO

7

6

5

4

3

2

1

0

1

0

0

0

0

0

Name BIF_ERR_9

BIF_ACK_9 BIF_DATA_9

MediaTek Proprietary and Confidential.

BIF_DATA_9 RO 0

0

0

0

Description Error happens or not 1'b0: No error 1'b1: Error exists. Read back data

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 562 of 1067

MT6359 PMIC Datasheet Confidential A 00000F44

BIF_CON30

BIF Control Register 30

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000F46 Bit Name Type Reset

Description

BIF_CON31 31

30

29

BIF Control Register 31 28

27

15 14 13 12 11 BIF_BU BIF_TO BIF_BA BIF_TI BIF_IR Name S_STAT TAL_V T_UND MEOUT Q US ALID ET RO RO RO RO RO Type

Bit

Reset

0

0

0

0

Bit(s) 15

Name BIF_BUS_STATUS

14

BIF_TOTAL_VALID

13

BIF_BAT_UNDET

12

BIF_TIMEOUT

11

BIF_IRQ

1

BIF_IRQ_CLR

0

BIF_BACK_NORMAL

MediaTek Proprietary and Confidential.

00000000

26

25

24

23

22

21

20

19

18

17

10

9

8

7

6

5

4

3

2

1

0

16

0 BIF_BA BIF_IR CK_NO Q_CLR RMAL RW RW 0

0

Description Busy: BIF is still in action 1'b0: Complete 1'b1: Busy Error happens or not in all read data 1'b0: No error 1'b1: Error exists (for all data). Battery status 1'b0: Battery exists. 1'b1: Battery undetected Timeout status 1'b1: Time out BIF interrupt status Because this register is cleared by the hardware, the interrupt edgesensitive scheme should be adopted for this design. 1'b1: Interrupt issue Clears BIF interrupt status When BIF interrupt is asserted, IRQ_CLR must be set to 1 to clear the interrupt status. Finishes interrupt mode 1'b1: Abort interrupt mode

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 563 of 1067

MT6359 PMIC Datasheet Confidential A 00000F48

BIF_CON32 31

Bit Name Type Reset

15 BIF_PO Name WER_U P RW Type

Bit

Reset Bit(s) 15 4:0

BIF Control Register 32

00000010

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

BIF_POWER_UP_COUNT RW

0

Name BIF_POWER_UP

0

0

0

0

Description Powers up trigger 1'b1: Power up slave device Powers up counter setting 5'd0: 0 5'd1: 1T 5'd2: 2T 5'dN: NT

BIF_POWER_UP_COUNT

00000F4A

1

BIF_CON33

BIF Control Register 33

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000F4C

Description

BIF_CON34

BIF Control Register 34

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 564 of 1067

MT6359 PMIC Datasheet Confidential A 00000F4E

BIF_CON35

BIF Control Register 35

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000F50

BIF_CON36 31

Bit Name Type Reset

Description

30

15 14 RG_BA RG_BA TON_H TON_H T_EN_ Name T_EN_P DLY_TI RE ME RW RW Type

Bit

Reset Bit(s) 15

14

0

BIF Control Register 36 28

27

26

25

24

23

22

21

20

19

18

17

16

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

Name RG_BATON_HT_EN_DLY_TIME

Description Not used 1'b0: 6T 1'b1: 12T Not used 1'b0: Disable 1'b1: Enable

RG_BATON_HT_EN_PRE

00000F52

00000000

29

BIF_CON37

BIF Control Register 37

0000000B

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

BIF_TIMEOUT_SET RW 0 0 0 0

0

0

1

0

1

1

Bit(s) 15:0

0

0

0

Name BIF_TIMEOUT_SET

MediaTek Proprietary and Confidential.

0

0

Description Sets up timeout spec 16'd0: 0T 16'd1: 1T 16'd2: 2T 16'dN: NT

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 565 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00000F54

BIF_CON38 31

Bit Name Type Reset

15 BIF_RX Name _DEG_ EN RW Type

Bit

Reset

Description

BIF Control Register 38

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

0

0

0

1

BIF_RX_DEG_WND RW

1

0

Bit(s) 15

Name BIF_RX_DEG_EN

10:0

BIF_RX_DEG_WND

00000F56

00008031

0

0

0

0

1

Description Enables deglitch function 1'b0: Bypass 1'b1: Enable HW deglitch function Filter window 10'd0: 1T 10'd1: 2T 10'd2: 3T 10'dN: (N + 1)T

BIF_CON39

BIF Control Register 39

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000F80

Description

HK_TOP_ID

Register HK_TOP Design ID Register

00004F00

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 566 of 1067

MT6359 PMIC Datasheet Confidential A 00000F82

HK_TOP_REV0

Register HK_TOP Design Revision Register 0

00002000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000F84

Description

HK_TOP_DBI

HK_TOP Design Bank Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000F86

Description

HK_TOP_DXI

HK_Design Extra Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000F88

Description

HK_TPM0

HK_TOP Parameter 0

0000100C

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 567 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00000F8A

Description

HK_TPM1

HK_TOP Parameter 1

00000112

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000F8C

Description

HK_TOP_CLK_CON0

HK_TOP_CLK_CON0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000F8E

Description

HK_TOP_CLK_CON1

HK_TOP_CLK_CON1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 568 of 1067

MT6359 PMIC Datasheet Confidential A 00000F90

HK_TOP_RST_CON0

HK_TOP_RST_CON0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

22

21

20

19

18

17

00000F92

Description

HK_TOP_INT_CON0

HK_TOP_INT_CON0

Bit Name Type Reset

31

30

29

28

27

26

Bit

15

14

13

12

11

10

Name Type Reset

25

Name RG_INT_EN_NAG_C_DLTV

8

RG_INT_EN_AUXADC_IMP

7

RG_INT_EN_THR_L

6

RG_INT_EN_THR_H

5

RG_INT_EN_BAT_TEMP_L

4

RG_INT_EN_BAT_TEMP_H

3

RG_INT_EN_BAT2_L

2

RG_INT_EN_BAT2_H

1

RG_INT_EN_BAT_L

MediaTek Proprietary and Confidential.

23

00000000 16

9 8 7 6 5 4 3 2 1 0 RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT _EN_N _EN_A _EN_B _EN_B _EN_T _EN_T _EN_B _EN_B _EN_B _EN_B AG_C_ UXADC AT_TE AT_TE HR_L HR_H AT2_L AT2_H AT_L AT_H DLTV _IMP MP_L MP_H RW RW RW RW RW RW RW RW RW RW 0

Bit(s) 9

24

0

0

0

0

0

0

0

0

0

Description Enables NAG_C_DLTV interrupt 0: Not issue interrupt 1: Issue interrupt Enables AUXADC_IMP interrupt 0: Not issue interrupt 1: Issue interrupt Enables THR_L interrupt 0: Not issue interrupt 1: Issue interrupt Enables THR_H interrupt 0: Not issue interrupt 1: Issue interrupt Enables BAT_TEMP_L interrupt 0: Not issue interrupt 1: Issue interrupt Enables BAT_TEMP_H interrupt 0: Not issue interrupt 1: Issue interrupt Enables BAT2_L interrupt 0: Not issue interrupt 1: Issue interrupt Enables BAT2_H interrupt 0: Not issue interrupt 1: Issue interrupt Enables BAT_L interrupt 0: Not issue interrupt 1: Issue interrupt

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 569 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 0

Name RG_INT_EN_BAT_H

00000F94

Description Enables BAT_H interrupt 0: Not issue interrupt 1: Issue interrupt

HK_TOP_INT_CON0_SET

HK_TOP_INT_CON0_SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

HK_INT_CON0_SET W1 0 0 0 0

0

0

0

0

0

0

Bit(s) 15:0

0

0

0

0

0

Name HK_INT_CON0_SET

00000F96

Description 0: Not set 1: Set

HK_TOP_INT_CON0_CLR

HK_TOP_INT_CON0_CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

HK_INT_CON0_CLR W1 0 0 0 0

0

0

0

0

0

0

21

20

19

18

17

Bit(s) 15:0

0

0

0

0

0

Name HK_INT_CON0_CLR

00000F98

Description 0: Not clear 1: Clear

HK_TOP_INT_MASK_CON0

HK_TOP_INT_MASK_CON0

Bit Name Type Reset

31

30

29

28

27

26

25

Bit

15

14

13

12

11

10

9

Name

Type Reset Bit(s) 9

MediaTek Proprietary and Confidential.

23

22

00000000 16

8 7 6 5 4 3 2 1 0 RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT _MASK RG_INT RG_INT _MASK _MASK _MASK _MASK _MASK _MASK _MASK _AUXA _MASK _MASK _NAG_ _THR_ _BAT_T _BAT_T _BAT2_ _BAT2_ _BAT_ DC_IM _THR_L _BAT_L C_DLTV H EMP_L EMP_H L H H P RW RW RW RW RW RW RW RW RW RW 0

Name RG_INT_MASK_NAG_C_DLTV

24

0

0

0

0

0

0

0

0

0

Description Masks NAG_C_DLTV interrupt status 0: Unmask interrupt status

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 570 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

8

RG_INT_MASK_AUXADC_IMP

7

RG_INT_MASK_THR_L

6

RG_INT_MASK_THR_H

5

RG_INT_MASK_BAT_TEMP_L

4

RG_INT_MASK_BAT_TEMP_H

3

RG_INT_MASK_BAT2_L

2

RG_INT_MASK_BAT2_H

1

RG_INT_MASK_BAT_L

0

RG_INT_MASK_BAT_H

00000F9A

Description 1: Mask interrupt status Masks AUXADC_IMP interrupt status 0: Unmask interrupt status 1: Mask interrupt status Masks THR_L interrupt status 0: Unmask interrupt status 1: Mask interrupt status Masks THR_H interrupt status 0: Unmask interrupt status 1: Mask interrupt status Masks BAT_TEMP_L interrupt status 0: Unmask interrupt status 1: Mask interrupt status Masks BAT_TEMP_H interrupt status 0: Unmask interrupt status 1: Mask interrupt status Masks BAT2_L interrupt status 0: Unmask interrupt status 1: Mask interrupt status Masks BAT2_H interrupt status 0: Unmask interrupt status 1: Mask interrupt status Masks BAT_L interrupt status 0: Unmask interrupt status 1: Mask interrupt status Masks BAT_H interrupt status 0: Unmask interrupt status 1: Mask interrupt status

HK_TOP_INT_MASK_CON0_SET

HK_TOP_INT_MASK_CON0_SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

HK_INT_MASK_CON0_SET W1 0 0 0 0

0

0

0

0

0

0

Bit(s) 15:0

0

0

0

0

Name HK_INT_MASK_CON0_SET

MediaTek Proprietary and Confidential.

0

Description 0: Not set 1: Set

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 571 of 1067

MT6359 PMIC Datasheet Confidential A 00000F9C

HK_TOP_INT_MASK_CON0_CLR

Bit Name Type Reset

31

30

29

28

27

26

Bit Name Type Reset

15

14

13

12

11

Bit(s) 15:0

0

0

0

0

0

23

22

21

20

19

18

17

16

10

9

8

7

6

5

4

3

2

1

0

0

HK_INT_MASK_CON0_CLR W1 0 0 0 0

0

0

0

0

0

0

21

20

19

18

17

Description 0: Not clear 1: Clear

HK_TOP_INT_STATUS0

HK_TOP_INT_STATUS0

Bit Name Type Reset

31

30

29

28

27

26

Bit

15

14

13

12

11

10

Name

Type Reset

25

Bit(s) 9

Name RG_INT_STATUS_NAG_C_DLTV

8

RG_INT_STATUS_AUXADC_IMP

7

RG_INT_STATUS_THR_L

6

RG_INT_STATUS_THR_H

5

RG_INT_STATUS_BAT_TEMP_L

4

RG_INT_STATUS_BAT_TEMP_H

3

RG_INT_STATUS_BAT2_L

2

RG_INT_STATUS_BAT2_H

24

23

00000000 22

16

9 8 7 6 5 4 3 2 1 0 RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT _STAT _STAT _STAT _STAT _STAT _STAT _STAT _STAT _STAT _STAT US_NA US_AU US_BA US_BA US_TH US_TH US_BA US_BA US_BA US_BA G_C_D XADC_I T_TEM T_TEM R_L R_H T2_L T2_H T_L T_H LTV MP P_L P_H W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C 0

MediaTek Proprietary and Confidential.

00000000

24

Name HK_INT_MASK_CON0_CLR

00000F9E

HK_TOP_INT_MASK_CON0_CLR 25

0

0

0

0

0

0

0

0

0

Description NAG_C_DLTV interrupt status 0: No interrupt issued 1: Interrupt issued AUXADC_IMP interrupt status 0: No interrupt issued 1: Interrupt issued THR_L interrupt status 0: No interrupt issued 1: Interrupt issued THR_H interrupt status 0: No interrupt issued 1: Interrupt issued BAT_TEMP_L interrupt status 0: No interrupt issued 1: Interrupt issued BAT_TEMP_H interrupt status 0: No interrupt issued 1: Interrupt issued BAT2_L interrupt status 0: No interrupt issued 1: Interrupt issued BAT2_H interrupt status 0: No interrupt issued 1: Interrupt issued

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 572 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 1

Name RG_INT_STATUS_BAT_L

0

RG_INT_STATUS_BAT_H

00000FA0

Description BAT_L interrupt status 0: No interrupt issued 1: Interrupt issued BAT_H interrupt status 0: No interrupt issued 1: Interrupt issued

HK_TOP_INT_RAW_STATUS0 HK_TOP_INT_RAW_STATUS0

Bit Name Type Reset

31

30

29

28

27

26

25

Bit

15

14

13

12

11

10

9

Name

Type Reset Name RG_INT_RAW_STATUS_NAG_C_DLTV

8

RG_INT_RAW_STATUS_AUXADC_IMP

7

RG_INT_RAW_STATUS_THR_L

6

RG_INT_RAW_STATUS_THR_H

5

RG_INT_RAW_STATUS_BAT_TEMP_L

4

RG_INT_RAW_STATUS_BAT_TEMP_H

3

RG_INT_RAW_STATUS_BAT2_L

2

RG_INT_RAW_STATUS_BAT2_H

1

RG_INT_RAW_STATUS_BAT_L

0

RG_INT_RAW_STATUS_BAT_H

MediaTek Proprietary and Confidential.

23

22

00000000 21

20

19

18

17

16

8 7 6 5 4 3 2 1 0 RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT _RAW_ RG_INT RG_INT _RAW_ _RAW_ _RAW_ _RAW_ _RAW_ _RAW_ _RAW_ STATUS _RAW_ _RAW_ STATUS STATUS STATUS STATUS STATUS STATUS STATU _AUXA STATUS STATUS _NAG_ _THR_ _BAT_T _BAT_T _BAT2_ _BAT2_ S_BAT_ DC_IM _THR_L _BAT_L C_DLTV H EMP_L EMP_H L H H P RO RO RO RO RO RO RO RO RO RO 0

Bit(s) 9

24

0

0

0

0

0

0

0

0

0

Description NAG_C_DLTV raw interrupt status 0: No interrupt issued 1: Interrupt issued AUXADC_IMP raw interrupt status 0: No interrupt issued 1: Interrupt issued THR_L raw interrupt status 0: No interrupt issued 1: Interrupt issued THR_H raw interrupt status 0: No interrupt issued 1: Interrupt issued BAT_TEMP_L raw interrupt status 0: No interrupt issued 1: Interrupt issued BAT_TEMP_H raw interrupt status 0: No interrupt issued 1: Interrupt issued BAT2_L raw interrupt status 0: No interrupt issued 1: Interrupt issued BAT2_H raw interrupt status 0: No interrupt issued 1: Interrupt issued BAT_L raw interrupt status 0: No interrupt issued 1: Interrupt issued BAT_H raw interrupt status 0: No interrupt issued 1: Interrupt issued

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 573 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00000FA2

Description

HK_TOP_MON_CON0

HK_TOP_MON_CON0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000FA4

Description

HK_TOP_MON_CON1

HK_TOP_MON_CON1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000FA6

Description

HK_TOP_MON_CON2

HK_TOP_MON_CON2

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 574 of 1067

MT6359 PMIC Datasheet Confidential A 00000FA8

HK_TOP_CHR_CON

HK_TOP_CHR_CON

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000FAA

Description

HK_TOP_ANA_CON

HK_TOP_ANA_CON

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000FAC

Description

HK_TOP_AUXADC_ANA

HK_TOP_AUXADC_ANA

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000FAE

Description

HK_TOP_STRUP

HK_TOP_STRUP

000000A2

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 575 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00000FB0

Description

HK_TOP_LDO_CON

HK_TOP_LDO_CON

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000FB2

Description

HK_TOP_LDO_STATUS

HK_TOP_LDO_STATUS

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00000FB4

Description

HK_TOP_WKEY

HK_TOP_WKEY

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 576 of 1067

MT6359 PMIC Datasheet Confidential A 00001000

AUXADC_DSN_ID

Register AUXADC Design ID Register

0000A020

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001002

Description

AUXADC_DSN_REV0

Register AUXADC Design Revision Register 0

00000020

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001004

Description

AUXADC_DSN_DBI

Register AUXADC Design Bank Information Register

00000C00

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001006

Description

AUXADC_DSN_FPI

AUXADC Design Extra Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 577 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001008

Description

AUXADC_ANA_CON0

AUXADC Control Register 0

0000F000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000100A

Description

AUXADC_ANA_CON1

AUXADC Control Register 1

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000100C

Description

AUXADC_ELR_NUM

AUXADC Number of ELR Register

00000002

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 578 of 1067

MT6359 PMIC Datasheet Confidential A 0000100E

AUXADC_ELR_0

AUXADC ELR 0 Register

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001080

Description

AUXADC_DIG_1_DSN_ID

Register AUXADC_DIG_1 Design ID Register

00004800

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001082

Description

AUXADC_DIG_1_DSN_REV0 Register AUXADC_DIG_1 Design Revision Register 0

00002000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001084

Description

AUXADC_DIG_1_DSN_DBI

Register AUXADC_DIG_1 Design Bank Information Register

00000003

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 579 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001086

Description

AUXADC_DIG_1_DSN_DXI

Register AUXADC_DIG_1 Design Extra Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001088

AUXADC_ADC0 31

Bit Name Type Reset

Description

15 AUXAD C_ADC Name _RDY_ CH0 RO Type 0 Reset

Bit

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

AUXADC_ADC_OUT_CH0

0

0

0

Name AUXADC_ADC_RDY_CH0

14:0

AUXADC_ADC_OUT_CH0

Bit Name Type Reset

15 AUXAD C_ADC Name _RDY_ CH1 RO Type 0 Reset

Bit

Bit(s) 15

0

0

0

0

RO 0

0

Description AUXADC channel 0 output data ready 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 0 output data

AUXADC_ADC1 31

00000000

29

Bit(s) 15

0000108A

AUXADC ADC Register 0

30

AUXADC ADC Register 1

00000000

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

AUXADC_ADC_OUT_CH1

0

0

0

Name AUXADC_ADC_RDY_CH1

MediaTek Proprietary and Confidential.

0

0

0

0

RO 0

0

Description AUXADC channel 1 output data ready 0: AUXADC data proceeding

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 580 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

14:0

AUXADC_ADC_OUT_CH1

0000108C

AUXADC_ADC2 31

Bit Name Type Reset

15 AUXAD C_ADC Name _RDY_ CH2 RO Type

Bit

Reset

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

AUXADC_ADC_OUT_CH2 RO 0

Name AUXADC_ADC_RDY_CH2

11:0

AUXADC_ADC_OUT_CH2

15 AUXAD C_ADC Name _RDY_ CH3 RO Type

Bit

Reset

0

0

0

0

0

0

Description AUXADC channel 2 output data ready 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 2 output data

AUXADC_ADC3 31

00000000

29

0

0000108E

AUXADC ADC Register 2

30

Bit(s) 15

Bit Name Type Reset

Description 1: AUXADC data ready AUXADC channel 1 output data

AUXADC ADC Register 3

00000000

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

AUXADC_ADC_OUT_CH3 RO

0

0

Bit(s) 15

Name AUXADC_ADC_RDY_CH3

11:0

AUXADC_ADC_OUT_CH3

MediaTek Proprietary and Confidential.

0

0

0

0

0

0

0

Description AUXADC channel 3 output data ready 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 3 output data

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 581 of 1067

MT6359 PMIC Datasheet Confidential A 00001090

AUXADC_ADC4 31

Bit Name Type Reset

15 AUXAD C_ADC Name _RDY_ CH4 RO Type

Bit

Reset

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

AUXADC_ADC_OUT_CH4 RO 0

Bit(s) 15

Name AUXADC_ADC_RDY_CH4

11:0

AUXADC_ADC_OUT_CH4

15 AUXAD C_ADC Name _RDY_ CH5 RO Type

Bit

Reset

Reset

0

Description AUXADC channel 4 output data ready 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 4 output data

AUXADC ADC Register 5

00000000

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

AUXADC_ADC_OUT_CH5 RO 0

AUXADC_ADC_OUT_CH5

0

0

0

0

0

0

Description AUXADC channel 5 output data ready 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 5 output data

AUXADC_ADC6

15 AUXAD C_ADC Name _RDY_ CH6 RO Type

0

27

11:0

Bit

0

28

Name AUXADC_ADC_RDY_CH5

31

0

29

0

00001094

0

30

Bit(s) 15

Bit Name Type Reset

0

AUXADC_ADC5 31

Bit Name Type Reset

00000000

29

0

00001092

AUXADC ADC Register 4

30

AUXADC ADC Register 6

00000000

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

MediaTek Proprietary and Confidential.

AUXADC_ADC_OUT_CH6 RO 0

0

0

0

0

0

0

0

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 582 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 15

Name AUXADC_ADC_RDY_CH6

11:0

AUXADC_ADC_OUT_CH6

00001096

AUXADC_ADC7 31

Bit Name Type Reset

15 AUXAD C_ADC Name _RDY_ CH7 RO Type 0 Reset

Bit

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

AUXADC_ADC_OUT_CH7

0

0

0

14:0

AUXADC_ADC_OUT_CH7

15 AUXAD C_ADC Name _RDY_ CH8 RO Type

Bit

Reset

0

0

0

0

RO 0

0

Description AUXADC channel 7 output data ready 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 7 output data

AUXADC_ADC8 31

00000000

29

Name AUXADC_ADC_RDY_CH7

00001098

AUXADC ADC Register 7

30

Bit(s) 15

Bit Name Type Reset

Description AUXADC channel 6 output data ready 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 6 output data

AUXADC ADC Register 8

00000000

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

AUXADC_ADC_OUT_CH8 RO

0

0

Bit(s) 15

Name AUXADC_ADC_RDY_CH8

11:0

AUXADC_ADC_OUT_CH8

MediaTek Proprietary and Confidential.

0

0

0

0

0

0

0

Description AUXADC channel 8 output data ready 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 8 output data

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 583 of 1067

MT6359 PMIC Datasheet Confidential A 0000109A

AUXADC_ADC9 31

Bit Name Type Reset

15 AUXAD C_ADC Name _RDY_ CH9 RO Type 0 Reset

Bit

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

AUXADC_ADC_OUT_CH9

0

0

0

Name AUXADC_ADC_RDY_CH9

14:0

AUXADC_ADC_OUT_CH9

15 AUXAD C_ADC Name _RDY_ CH10 RO Type 0 Reset

Bit

15 AUXAD C_ADC Name _RDY_ CH11 RO Type

0

Description AUXADC channel 9 output data ready 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 9 output data

AUXADC ADC Register 10

00000000

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

AUXADC_ADC_OUT_CH10

0

0

0

0

0

0

0

RO 0

0

Description AUXADC channel 10 output data ready 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 10 output data

AUXADC_ADC11

Bit

RO 0

27

AUXADC_ADC_OUT_CH10

31

0

28

14:0

0000109E

0

29

Name AUXADC_ADC_RDY_CH10

Reset

0

30

Bit(s) 15

Bit Name Type Reset

0

AUXADC_ADC10 31

Bit Name Type Reset

00000000

29

Bit(s) 15

0000109C

AUXADC ADC Register 9

30

AUXADC ADC Register 11

00000000

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

MediaTek Proprietary and Confidential.

AUXADC_ADC_OUT_CH11 RO 0

0

0

0

0

0

0

0

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 584 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 15

Name AUXADC_ADC_RDY_CH11

11:0

AUXADC_ADC_OUT_CH11

000010A0

AUXADC_ADC12 31

Bit Name Type Reset

15 AUXAD C_ADC Name _RDY_ CH12_ 15 RO Type 0 Reset

Bit

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

AUXADC_ADC_OUT_CH12_15

0

0

0

14:0

AUXADC_ADC_OUT_CH12_15

15 AUXAD C_ADC Name _RDY_ CH7_B Y_GPS RO Type 0 Reset

Bit

0

0

0

0

RO 0

0

Description AUXADC channel 12_15 output data ready 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 12_15 output data

AUXADC_ADC15 31

00000000

29

Name AUXADC_ADC_RDY_CH12_15

000010A2

AUXADC ADC Register 12

30

Bit(s) 15

Bit Name Type Reset

Description AUXADC channel 11 output data ready (used for BIF) 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 11 output data (used for BIF)

AUXADC ADC Register 15

00000000

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

AUXADC_ADC_OUT_CH7_BY_GPS

0

0

0

0

Bit(s) 15

Name AUXADC_ADC_RDY_CH7_BY_GPS

14:0

AUXADC_ADC_OUT_CH7_BY_GPS

MediaTek Proprietary and Confidential.

0

0

0

RO 0

0

0

Description AUXADC channel 7 output data ready (requested by GPS) 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 7 output data (requested by GPS)

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 585 of 1067

MT6359 PMIC Datasheet Confidential A 000010A4

AUXADC_ADC16 31

Bit Name Type Reset

15 AUXAD C_ADC Name _RDY_ CH7_B Y_MD RO Type 0 Reset

Bit

AUXADC ADC Register 16

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

AUXADC_ADC_OUT_CH7_BY_MD

0

0

0

0

Bit(s) 15

Name AUXADC_ADC_RDY_CH7_BY_MD

14:0

AUXADC_ADC_OUT_CH7_BY_MD

000010A6

15 AUXAD C_ADC Name _RDY_ CH7_B Y_AP RO Type 0 Reset

Bit

Reset

0

Description AUXADC channel 7 output data ready (requested by MD) 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 7 output data (requested by MD)

AUXADC ADC Register 17

00000000

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

AUXADC_ADC_OUT_CH7_BY_AP

0

0

0

0

0

0

0

RO 0

0

0

Description AUXADC channel 7 output data ready (requested by AP) 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 7 output data (requested by AP)

AUXADC_ADC18

15 AUXAD C_ADC Name _RDY_ CH4_B Y_MD RO Type

0

27

AUXADC_ADC_OUT_CH7_BY_AP

Bit

RO 0

28

14:0

31

0

29

Name AUXADC_ADC_RDY_CH7_BY_AP

000010A8

0

30

Bit(s) 15

Bit Name Type Reset

0

AUXADC_ADC17 31

Bit Name Type Reset

00000000

30

AUXADC ADC Register 18

00000000

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

MediaTek Proprietary and Confidential.

AUXADC_ADC_OUT_CH4_BY_MD

RO 0

0

0

0

0

0

0

0

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 586 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 15

Name AUXADC_ADC_RDY_CH4_BY_MD

11:0

AUXADC_ADC_OUT_CH4_BY_MD

000010AA

AUXADC_ADC19 31

Bit Name Type Reset

15 AUXAD C_ADC _RDY_ Name PWRO N_PCH R RO Type 0 Reset

Bit

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

AUXADC_ADC_OUT_PWRON_PCHR

0

0

0

0

14:0

AUXADC_ADC_OUT_PWRON_PCHR

15 AUXAD C_ADC _RDY_ Name WAKE UP_PC HR RO Type 0 Reset

Bit

Bit(s) 15

0

0

0

RO 0

0

0

Description AUXADC channel 0 power-on ZCV output data ready 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 0 power-on ZCV output data

AUXADC_ADC20 31

00000000

29

Name AUXADC_ADC_RDY_PWRON_PCHR

000010AC

up ZCV output data

AUXADC ADC Register 19

30

Bit(s) 15

Bit Name Type Reset

Description AUXADC channel 4 output data ready (requested by MD) 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 4 output data (requested by MD)

AUXADC ADC Register 20

00000000

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

AUXADC_ADC_OUT_WAKEUP_PCHR

0

0

0

0

Name AUXADC_ADC_RDY_WAKEUP_PCHR

0

0

0

RO 0

0

0

Description AUXADC channel 0 wakeup ZCV output data ready 0: AUXADC data proceeding 1: AUXADC data ready

14:0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 587 of 1067

MT6359 PMIC Datasheet Confidential A 000010AE

AUXADC_ADC21 31

Bit Name Type Reset

15 AUXAD C_ADC Name _RDY_ CH0_B Y_MD RO Type 0 Reset

Bit

AUXADC ADC Register 21

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

AUXADC_ADC_OUT_CH0_BY_MD

0

0

0

0

Bit(s) 15

Name AUXADC_ADC_RDY_CH0_BY_MD

14:0

AUXADC_ADC_OUT_CH0_BY_MD

000010B0

15 AUXAD C_ADC Name _RDY_ CH0_B Y_AP RO Type 0 Reset

Bit

0

Description AUXADC channel 0 output data ready (requested by MD) 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 0 output data (requested by MD)

AUXADC ADC Register 22

00000000

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

AUXADC_ADC_OUT_CH0_BY_AP

0

0

0

0

0

0

0

RO 0

0

0

Description AUXADC channel 0 output data ready (requested by AP) 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 0 output data (requested by AP)

AUXADC_ADC23

15 AUXAD C_ADC Name _RDY_ CH1_B Y_MD RO Type 0 Reset

0

27

AUXADC_ADC_OUT_CH0_BY_AP

Bit

RO 0

28

14:0

31

0

29

Name AUXADC_ADC_RDY_CH0_BY_AP

000010B2

0

30

Bit(s) 15

Bit Name Type Reset

0

AUXADC_ADC22 31

Bit Name Type Reset

00000000

30

AUXADC ADC Register 23

00000000

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

AUXADC_ADC_OUT_CH1_BY_MD

0

MediaTek Proprietary and Confidential.

0

0

0

0

0

0

RO 0

0

0

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 588 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 15

Name AUXADC_ADC_RDY_CH1_BY_MD

14:0

AUXADC_ADC_OUT_CH1_BY_MD

000010B4

AUXADC_ADC24 31

Bit Name Type Reset

15 AUXAD C_ADC Name _RDY_ CH1_B Y_AP RO Type 0 Reset

Bit

AUXADC ADC Register 24

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

AUXADC_ADC_OUT_CH1_BY_AP

0

0

0

0

Name AUXADC_ADC_RDY_CH1_BY_AP

14:0

AUXADC_ADC_OUT_CH1_BY_AP

000010B6

15 AUXAD C_ADC Name _RDY_ FGADC _PCHR RO Type 0 Reset

Bit

0

0

0

RO 0

0

0

Description AUXADC channel 1 output data ready (requested by AP) 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 1 output data (requested by AP)

AUXADC_ADC26 31

00000000

30

Bit(s) 15

Bit Name Type Reset

Description AUXADC channel 1 output data ready (requested by MD) 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 1 output data (requested by MD)

AUXADC ADC Register 26

00000000

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

AUXADC_ADC_OUT_FGADC_PCHR

0

0

0

0

Bit(s) 15

Name AUXADC_ADC_RDY_FGADC_PCHR

14:0

AUXADC_ADC_OUT_FGADC_PCHR

MediaTek Proprietary and Confidential.

0

0

0

RO 0

0

0

Description AUXADC channel 0 ZCV output data ready (requested by FGADC) 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 0 ZCV output data (requested by FGADC)

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 589 of 1067

MT6359 PMIC Datasheet Confidential A 000010B8

AUXADC_ADC27 31

Bit Name Type Reset

15 AUXAD C_ADC _RDY_ Name BAT_PL UGIN_ PCHR RO Type 0 Reset

Bit

Bit(s) 15

14:0

AUXADC ADC Register 27

00000000

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

AUXADC_ADC_OUT_BAT_PLUGIN_PCHR

0

0

0

0

0

0

0

RO 0

0

0

Name Description AUXADC_ADC_RDY_BAT_PLUGIN_PCHR AUXADC channel 0 ZCV output data ready (requested by BAT PLUGIN) 0: AUXADC data proceeding 1: AUXADC data ready AUXADC_ADC_OUT_BAT_PLUGIN_PCHR AUXADC channel 0 ZCV output data (requested by BAT PLUGIN)

000010BA

AUXADC_ADC30

AUXADC ADC Register 30

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

Bit(s) 14:0

AUXADC_ADC_OUT_RAW RO 0

Bit(s) 15

0

0

31

0

0

0

0

Description AUXADC channel output raw data

AUXADC_ADC32

15 AUXAD C_ADC _RDY_ Name DCXO_ BY_GP S RO Type 0 Reset

Bit

0

Name AUXADC_ADC_OUT_RAW

000010BC Bit Name Type Reset

0

AUXADC ADC Register 32

00000000

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

AUXADC_ADC_OUT_DCXO_BY_GPS

0

0

0

0

Name AUXADC_ADC_RDY_DCXO_BY_GPS

MediaTek Proprietary and Confidential.

0

0

0

RO 0

0

0

Description AUXADC channel 10 DCXO output data ready (requested by GPS) 0: AUXADC data proceeding

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 590 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

14:0

AUXADC_ADC_OUT_DCXO_BY_GPS

000010BE

AUXADC_ADC33 31

Bit Name Type Reset

15 AUXAD C_ADC Name _RDY_ DCXO_ BY_MD RO Type 0 Reset

Bit

AUXADC ADC Register 33

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

AUXADC_ADC_OUT_DCXO_BY_MD

0

0

0

0

Name AUXADC_ADC_RDY_DCXO_BY_MD

14:0

AUXADC_ADC_OUT_DCXO_BY_MD

000010C0

15 AUXAD C_ADC Name _RDY_ DCXO_ BY_AP RO Type 0 Reset

Bit

0

0

0

RO 0

0

0

Description AUXADC channel 10 DCXO output data ready (requested by MD) 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 10 DCXO output data (requested by MD)

AUXADC_ADC34 31

00000000

30

Bit(s) 15

Bit Name Type Reset

Description 1: AUXADC data ready AUXADC channel 10 DCXO output data (requested by GPS)

AUXADC ADC Register 34

00000000

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

AUXADC_ADC_OUT_DCXO_BY_AP

0

0

0

0

Bit(s) 15

Name AUXADC_ADC_RDY_DCXO_BY_AP

14:0

AUXADC_ADC_OUT_DCXO_BY_AP

MediaTek Proprietary and Confidential.

0

0

0

RO 0

0

0

Description AUXADC channel 10 DCXO output data ready (requested by AP) 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 10 DCXO output data (requested by AP)

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 591 of 1067

MT6359 PMIC Datasheet Confidential A 000010C2

AUXADC_ADC37 31

Bit Name Type Reset

15 AUXAD C_ADC Name _RDY_ BATID RO Type

Bit

Reset

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

AUXADC_ADC_OUT_BATID RO 0

Bit(s) 15

Name AUXADC_ADC_RDY_BATID

11:0

AUXADC_ADC_OUT_BATID

Bit Name Type Reset

15 AUXAD C_ADC _RDY_ Name CH4_B Y_THR 1 RO Type

Bit

Reset

0

0

0

0

0

0

0

Description AUXADC channel 3 BATID output data ready 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 3 BATID output data

AUXADC_ADC38 31

00000000

29

0

000010C4

AUXADC ADC Register 37

30

AUXADC ADC Register 38

00000000

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

AUXADC_ADC_OUT_CH4_BY_THR1

RO 0

Bit(s) 15

Name AUXADC_ADC_RDY_CH4_BY_THR1

11:0

AUXADC_ADC_OUT_CH4_BY_THR1

MediaTek Proprietary and Confidential.

0

0

0

0

0

0

0

Description AUXADC channel 4 THR1 output data ready 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 4 THR1 output data

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 592 of 1067

MT6359 PMIC Datasheet Confidential A 000010C6

AUXADC_ADC39 31

Bit Name Type Reset

15 AUXAD C_ADC _RDY_ Name CH4_B Y_THR 2 RO Type

Bit

Reset

AUXADC ADC Register 39

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

AUXADC_ADC_OUT_CH4_BY_THR2

RO

0

0

Bit(s) 15

Name AUXADC_ADC_RDY_CH4_BY_THR2

11:0

AUXADC_ADC_OUT_CH4_BY_THR2

000010C8 Bit Name Type Reset

15 AUXAD C_ADC _RDY_ Name CH4_B Y_THR 3 RO Type

Bit

Reset

0

0

0

0

0

0

0

Description AUXADC channel 4 THR2 output data ready 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 4 THR2 output data

AUXADC_ADC40 31

00000000

30

AUXADC ADC Register 40

00000000

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

AUXADC_ADC_OUT_CH4_BY_THR3

RO 0

Bit(s) 15

Name AUXADC_ADC_RDY_CH4_BY_THR3

11:0

AUXADC_ADC_OUT_CH4_BY_THR3

MediaTek Proprietary and Confidential.

0

0

0

0

0

0

0

Description AUXADC channel 4 THR3 output data ready 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 4 THR3 output data

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 593 of 1067

MT6359 PMIC Datasheet Confidential A 000010CA

AUXADC_STA0 31

Bit Name Type Reset

15 AUXAD C_ADC Name _BUSY _IN_W AKEUP RO Type

Bit

Reset

AUXADC_STA0

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

AUXADC_ADC_BUSY_IN

RO

0

0

Bit(s) 15

Name AUXADC_ADC_BUSY_IN_WAKEUP

11:0

AUXADC_ADC_BUSY_IN

000010CC

00000000

30

0

0

0

0

0

0

0

0

0

0

19

18

17

Description ADC busy status 0: Idle 1: Busy AUXADC ADC busy status bit[11] = CH11 ~ bit[0] = CH0 0: Idle (for each bit) 1: Busy (for each bit)

AUXADC_STA1

AUXADC_STA1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

Bit

15

14

13

12

11

10

8

7

6

5

4

RO

RO

RO

RO

9 AUXAD C_ADC _BUSY _IN_FG ADC_P CHR RO

0

0

0

0

0

AUXAD C_ADC Name _BUSY _IN_TH R_MD

Type Reset Bit(s) 15

13

12

11

9

AUXAD AUXAD AUXAD C_ADC C_ADC C_ADC _BUSY _BUSY _BUSY _IN_GP _IN_GP _IN_GP S S_MD S_AP

AUXAD C_ADC _BUSY _IN_SH ARE RO 0

3 2 1 AUXAD AUXAD AUXAD C_ADC C_ADC C_ADC _BUSY _BUSY _BUSY _IN_DC _IN_DC _IN_DC XO_GP XO_GP XO_GP S S_MD S_AP RO RO RO 0

0

16

0

0

Name AUXADC_ADC_BUSY_IN_THR_MD

Description ADC busy status 0: Idle 1: Busy AUXADC_ADC_BUSY_IN_GPS ADC busy status 0: Idle 1: Busy AUXADC_ADC_BUSY_IN_GPS_MD ADC busy status 0: Idle 1: Busy AUXADC_ADC_BUSY_IN_GPS_AP ADC busy status 0: Idle 1: Busy AUXADC_ADC_BUSY_IN_FGADC_PCHR ADC busy status 0: Idle 1: Busy

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 594 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 7

3

2

1

Name AUXADC_ADC_BUSY_IN_SHARE

Description ADC busy status 0: Idle 1: Busy AUXADC_ADC_BUSY_IN_DCXO_GPS ADC busy status 0: Idle 1: Busy AUXADC_ADC_BUSY_IN_DCXO_GPS_MD ADC busy status 0: Idle 1: Busy AUXADC_ADC_BUSY_IN_DCXO_GPS_AP ADC busy status 0: Idle 1: Busy

000010CE

AUXADC_STA2

AUXADC_STA2

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

Type Reset

12

11

3

2

0

RO

RO

RO

RO

0

0

0

0

0

0

AUXAD AUXAD AUXAD C_ADC C_ADC C_ADC _BUSY _BUSY _BUSY _IN_TH _IN_TH _IN_TH R3 R2 R1

Name

Bit(s) 13

RO

0 AUXAD C_ADC _BUSY _IN_BA T_PLU GIN_PC HR RO

AUXAD AUXAD C_ADC C_ADC _BUSY _BUSY _IN_P _IN_BA WRON TID

Name AUXADC_ADC_BUSY_IN_THR3

Description ADC busy status 0: Idle 1: Busy AUXADC_ADC_BUSY_IN_THR2 ADC busy status 0: Idle 1: Busy AUXADC_ADC_BUSY_IN_THR1 ADC busy status 0: Idle 1: Busy AUXADC_ADC_BUSY_IN_PWRON ADC busy status 0: Idle 1: Busy AUXADC_ADC_BUSY_IN_BATID ADC busy status 0: Idle 1: Busy AUXADC_ADC_BUSY_IN_BAT_PLUGIN_P ADC busy status CHR 1: Busy

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 595 of 1067

MT6359 PMIC Datasheet Confidential A 00001100

AUXADC_DIG_2_DSN_ID

Register AUXADC_DIG_2 Design ID Register

00004800

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001102

Description

AUXADC_DIG_2_DSN_REV0 Register AUXADC_DIG_2 Design Revision Register 0

00002000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001104

Description

AUXADC_DIG_2_DSN_DBI

Register AUXADC_DIG_2 Design Bank Information Register

00000007

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 596 of 1067

MT6359 PMIC Datasheet Confidential A 00001106

AUXADC_DIG_2_DSN_DXI

Register AUXADC_DIG_2 Design Extra Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001108

Description

AUXADC_RQST0

AUXADC_RQST0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000110A

Description

AUXADC_RQST1

AUXADC_RQST1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001180

Description

AUXADC_DIG_3_DSN_ID

Register AUXADC_DIG_3 Design ID Register

00004800

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 597 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001182

Description

AUXADC_DIG_3_DSN_REV0 Register AUXADC_DIG_3 Design Revision Register 0

00002000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001184

Description

AUXADC_DIG_3_DSN_DBI

Register AUXADC_DIG_3 Design Bank Information Register

0000560B

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001186

Description

AUXADC_DIG_3_DSN_DXI

Register AUXADC_DIG_3 Design Extra Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 598 of 1067

MT6359 PMIC Datasheet Confidential A 00001188

AUXADC_CON0

AUXADC_CON0

00008014

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000118A

Description

AUXADC_CON0_SET

AUXADC_CON0_SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000118C

Description

AUXADC_CON0_CLR

AUXADC_CON0_CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000118E

Description

AUXADC_CON1

AUXADC_CON1

000002F4

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 599 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001190

Description

AUXADC_CON2

AUXADC_CON2

00000080

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001192

Description

AUXADC_CON3

AUXADC_CON3

00000030

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001194

Description

AUXADC_CON4

AUXADC_CON4

00000003

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 600 of 1067

MT6359 PMIC Datasheet Confidential A 00001196

AUXADC_CON5

AUXADC_CON5

00004000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001198

Description

AUXADC_CON6

AUXADC_CON6

0000000B

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000119A

Description

AUXADC_CON7

AUXADC_CON7

00000030

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000119C

Description

AUXADC_CON8

AUXADC_CON8

0000000B

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 601 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

0000119E

Description

AUXADC_CON9

AUXADC_CON9

00004462

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000011A0

Description

AUXADC_CON10

AUXADC_CON10

00002437

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000011A2

Description

AUXADC_CON11

AUXADC_CON11

000095D0

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 602 of 1067

MT6359 PMIC Datasheet Confidential A 000011A4

AUXADC_CON12

AUXADC_CON12

00004055

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000011A6

Description

AUXADC_CON13

AUXADC_CON13

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000011A8

Description

AUXADC_CON14

AUXADC_CON14

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000011AA

Description

AUXADC_CON15

AUXADC_CON15

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 603 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

000011AC

Description

AUXADC_CON16

AUXADC_CON16

00000020

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000011AE

Description

AUXADC_CON17

AUXADC_CON17

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000011B0

Description

AUXADC_CON18

AUXADC_CON18

00004244

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 604 of 1067

MT6359 PMIC Datasheet Confidential A 000011B2

AUXADC_CON19

AUXADC_CON19

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

23

22

21

20

19

18

17

000011B4 Bit Name

Description

AUXADC_CON20 31

30

MediaTek Proprietary and Confidential.

29

28

AUXADC_CON20 27

26

25

24

000000FF

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in part, is strictly prohibited.

16

Page 605 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

000011BA

Description

AUXADC_ACCDET

AUXADC_ACCDET

000000FC

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000011BC

Description

AUXADC_DBG0

AUXADC_DBG0

00003C00

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000011BE

Description

AUXADC_NAG_0

AUXADC_NAG_0

00000010

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 606 of 1067

MT6359 PMIC Datasheet Confidential A 000011C0

AUXADC_NAG_1

AUXADC_NAG_1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000011C2

Description

AUXADC_NAG_2

AUXADC_NAG_2

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000011C4

Description

AUXADC_NAG_3

AUXADC_NAG_3

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000011C6

Description

AUXADC_NAG_4

AUXADC_NAG_4

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 607 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

000011C8

Description

AUXADC_NAG_5

AUXADC_NAG_5

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000011CA

Description

AUXADC_NAG_6

AUXADC_NAG_6

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000011CC

Description

AUXADC_NAG_7

AUXADC_NAG_7

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 608 of 1067

MT6359 PMIC Datasheet Confidential A 000011CE

AUXADC_NAG_8

AUXADC_NAG_8

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000011D0

Description

AUXADC_NAG_9

AUXADC_NAG_9

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000011D2 Bit Name Type Reset

AUXADC_NAG_10 31

15 AUXAD C_ADC Name _RDY_ NAG RO Type 0 Reset

Bit

Description

AUXADC_NAG_10

00000000

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

AUXADC_ADC_OUT_NAG

0

0

0

Bit(s) 15

Name AUXADC_ADC_RDY_NAG

14:0

AUXADC_ADC_OUT_NAG

MediaTek Proprietary and Confidential.

0

0

0

0

RO 0

0

Description AUXADC channel 0 NAG output data ready 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 0 NAG output data

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 609 of 1067

MT6359 PMIC Datasheet Confidential A 000011D4

AUXADC_NAG_11 31

Bit Name Type Reset

15 AUXAD C_ADC Name _BUSY _IN_N AG RO Type

Bit

Reset Bit(s) 15

AUXADC_NAG_11

00000003

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

Name AUXADC_ADC_BUSY_IN_NAG

000011D6

Description ADC busy status 0: Idle 1: Busy

AUXADC_DIG_3_ELR_NUM

Register AUXADC_DIG_3 Number of ELR Register

00000022

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000011D8

Description

AUXADC_DIG_3_ELR0

AUXADC_DIG_3_ELR0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 610 of 1067

MT6359 PMIC Datasheet Confidential A 000011DA

AUXADC_DIG_3_ELR1

AUXADC_DIG_3_ELR1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000011DC

Description

AUXADC_DIG_3_ELR2

AUXADC_DIG_3_ELR2

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000011DE

Description

AUXADC_DIG_3_ELR3

AUXADC_DIG_3_ELR3

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000011E0

Description

AUXADC_DIG_3_ELR4

AUXADC_DIG_3_ELR4

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 611 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

000011E2

Description

AUXADC_DIG_3_ELR5

AUXADC_DIG_3_ELR5

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000011E4

Description

AUXADC_DIG_3_ELR6

AUXADC_DIG_3_ELR6

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000011E6

Description

AUXADC_DIG_3_ELR7

AUXADC_DIG_3_ELR7

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 612 of 1067

MT6359 PMIC Datasheet Confidential A 000011E8

AUXADC_DIG_3_ELR8

AUXADC_DIG_3_ELR8

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000011EA

Description

AUXADC_DIG_3_ELR9

AUXADC_DIG_3_ELR9

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000011EC

Description

AUXADC_DIG_3_ELR10

AUXADC_DIG_3_ELR10

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000011EE

Description

AUXADC_DIG_3_ELR11

AUXADC_DIG_3_ELR11

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 613 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

000011F0

Description

AUXADC_DIG_3_ELR12

AUXADC_DIG_3_ELR12

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000011F2

Description

AUXADC_DIG_3_ELR13

AUXADC_DIG_3_ELR13

0000006A

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000011F4

Description

AUXADC_DIG_3_ELR14

AUXADC_DIG_3_ELR14

00002040

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 614 of 1067

MT6359 PMIC Datasheet Confidential A 000011F6

AUXADC_DIG_3_ELR15

AUXADC_DIG_3_ELR15

00000127

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000011F8

Description

AUXADC_DIG_3_ELR16

AUXADC_DIG_3_ELR16

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001200

Description

AUXADC_DIG_4_DSN_ID

Register AUXADC_DIG_4 Design ID Register

00004800

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001202

Description

AUXADC_DIG_4_DSN_REV0 Register AUXADC_DIG_4 Design Revision Register 0

00002000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 615 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001204

Description

AUXADC_DIG_4_DSN_DBI

Register AUXADC_DIG_4 Design Bank Information Register

0000000F

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001206

Description

AUXADC_DIG_4_DSN_DXI

Register AUXADC_DIG_4 Design Extra Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001208

Description

AUXADC_IMP0

AUXADC_IMP0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 616 of 1067

MT6359 PMIC Datasheet Confidential A 0000120A

AUXADC_IMP1

AUXADC_IMP1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000120C

Description

AUXADC_IMP2

AUXADC_IMP2

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000120E Bit Name Type Reset

AUXADC_IMP3 31

15 AUXAD C_ADC Name _RDY_I MP RO Type 0 Reset

Bit

Description

AUXADC_IMP3

00000000

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

AUXADC_ADC_OUT_IMP

0

0

0

Bit(s) 15

Name AUXADC_ADC_RDY_IMP

14:0

AUXADC_ADC_OUT_IMP

MediaTek Proprietary and Confidential.

0

0

0

0

RO 0

0

Description AUXADC channel 0 IMP/PTIM output data ready (each trigger) 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 0 IMP/PTIM output data (each trigger)

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 617 of 1067

MT6359 PMIC Datasheet Confidential A 00001210

AUXADC_IMP4 31

Bit Name Type Reset

15 AUXAD C_ADC Name _RDY_I MP_AV G RO Type 0 Reset

Bit

AUXADC_IMP4

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

AUXADC_ADC_OUT_IMP_AVG

0

0

0

Bit(s) 15

Name AUXADC_ADC_RDY_IMP_AVG

14:0

AUXADC_ADC_OUT_IMP_AVG

00001212

15 AUXAD C_ADC Name _BUSY _IN_IM P RO Type

Bit

Reset Bit(s) 15

0

0

0

0

RO 0

0

Description AUXADC channel 0 IMP/PTIM output data ready (after average) 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 0 IMP/PTIM output data (after average)

AUXADC_IMP5 31

Bit Name Type Reset

00000000

30

AUXADC_IMP5

00000003

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

Name AUXADC_ADC_BUSY_IN_IMP

00001214

Description ADC busy status 0: Idle 1: Busy

AUXADC_LBAT0

AUXADC_LBAT0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 618 of 1067

MT6359 PMIC Datasheet Confidential A 00001216

AUXADC_LBAT1

AUXADC_LBAT1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001218

Description

AUXADC_LBAT2

AUXADC_LBAT2

00008000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000121A

Description

AUXADC_LBAT3

AUXADC_LBAT3

00008000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000121C

Description

AUXADC_LBAT4

AUXADC_LBAT4

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 619 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

0000121E

Description

AUXADC_LBAT5

AUXADC_LBAT5

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001220

Description

AUXADC_LBAT6

AUXADC_LBAT6

00008000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001222 Bit Name Type Reset

AUXADC_LBAT7 31

15 AUXAD C_ADC Name _RDY_L BAT RO Type

Bit

Reset

Description

AUXADC_LBAT7

00000000

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

AUXADC_ADC_OUT_LBAT RO

0

0

Bit(s) 15

Name AUXADC_ADC_RDY_LBAT

11:0

AUXADC_ADC_OUT_LBAT

MediaTek Proprietary and Confidential.

0

0

0

0

0

0

0

Description AUXADC channel 0 low battery output data ready 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 0 low battery output data

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 620 of 1067

MT6359 PMIC Datasheet Confidential A 00001224

AUXADC_LBAT8 31

Bit Name Type Reset

15 AUXAD C_ADC Name _BUSY _IN_LB AT RO Type

Bit

Reset Bit(s) 15

AUXADC_LBAT8

00000003

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

Name AUXADC_ADC_BUSY_IN_LBAT

00001226

Description ADC busy status 0: Idle 1: Busy

AUXADC_BAT_TEMP_0

AUXADC_BAT_TEMP_0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001228

Description

AUXADC_BAT_TEMP_1

AUXADC_BAT_TEMP_1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 621 of 1067

MT6359 PMIC Datasheet Confidential A 0000122A

AUXADC_BAT_TEMP_2

AUXADC_BAT_TEMP_2

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000122C

Description

AUXADC_BAT_TEMP_3

AUXADC_BAT_TEMP_3

00008000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000122E

Description

AUXADC_BAT_TEMP_4

AUXADC_BAT_TEMP_4

00008000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001230

Description

AUXADC_BAT_TEMP_5

AUXADC_BAT_TEMP_5

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 622 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001232

Description

AUXADC_BAT_TEMP_6

AUXADC_BAT_TEMP_6

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001234

Description

AUXADC_BAT_TEMP_7

AUXADC_BAT_TEMP_7

00008000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001236 Bit Name Type Reset

AUXADC_BAT_TEMP_8 31

15 AUXAD C_ADC Name _RDY_ BAT_T EMP RO Type

Bit

Reset

Description

AUXADC_BAT_TEMP_8

00000000

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

AUXADC_ADC_OUT_BAT_TEMP

RO 0

Bit(s) 15

Name AUXADC_ADC_RDY_BAT_TEMP

11:0

AUXADC_ADC_OUT_BAT_TEMP

MediaTek Proprietary and Confidential.

0

0

0

0

0

0

0

Description AUXADC channel 3 BAT_TEMP output data ready 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 3 BAT_TEMP output data

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 623 of 1067

MT6359 PMIC Datasheet Confidential A 00001238

AUXADC_BAT_TEMP_9 31

Bit Name Type Reset

15 AUXAD C_ADC _BUSY Name _IN_BA T_TEM P RO Type

Bit

Reset Bit(s) 15

AUXADC_BAT_TEMP_9

00000003

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

Name AUXADC_ADC_BUSY_IN_BAT_TEMP

0000123A

Description ADC busy status 0: Idle 1: Busy

AUXADC_LBAT2_0

AUXADC_LBAT2_0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000123C

Description

AUXADC_LBAT2_1

AUXADC_LBAT2_1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 624 of 1067

MT6359 PMIC Datasheet Confidential A 0000123E

AUXADC_LBAT2_2

AUXADC_LBAT2_2

00008000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001240

Description

AUXADC_LBAT2_3

AUXADC_LBAT2_3

00008000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001242

Description

AUXADC_LBAT2_4

AUXADC_LBAT2_4

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001244

Description

AUXADC_LBAT2_5

AUXADC_LBAT2_5

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 625 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001246

Description

AUXADC_LBAT2_6

AUXADC_LBAT2_6

00008000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001248

AUXADC_LBAT2_7 31

Bit Name Type Reset

15 AUXAD C_ADC Name _RDY_L BAT2 RO Type

Bit

Reset

Description

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

AUXADC_ADC_OUT_LBAT2 RO 0

Bit(s) 15

Name AUXADC_ADC_RDY_LBAT2

11:0

AUXADC_ADC_OUT_LBAT2

Bit Name Type Reset

15 AUXAD C_ADC Name _BUSY _IN_LB AT2 RO Type

Bit

Reset Bit(s) 15

0

0

0

0

0

0

0

Description AUXADC channel 0 low battery 2 output data ready 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 0 low battery 2 output data

AUXADC_LBAT2_8 31

00000000

29

0

0000124A

AUXADC_LBAT2_7

30

AUXADC_LBAT2_8

00000003

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

Name AUXADC_ADC_BUSY_IN_LBAT2

MediaTek Proprietary and Confidential.

Description ADC busy status 0: Idle

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 626 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

0000124C

Description 1: Busy

AUXADC_THR0

AUXADC_THR0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000124E

Description

AUXADC_THR1

AUXADC_THR1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001250

Description

AUXADC_THR2

AUXADC_THR2

00008000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 627 of 1067

MT6359 PMIC Datasheet Confidential A 00001252

AUXADC_THR3

AUXADC_THR3

00008000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001254

Description

AUXADC_THR4

AUXADC_THR4

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001256

Description

AUXADC_THR5

AUXADC_THR5

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001258

Description

AUXADC_THR6

AUXADC_THR6

00008000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

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Page 628 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

0000125A

AUXADC_THR7 31

Bit Name Type Reset

15 AUXAD C_ADC Name _RDY_ THR_H W RO Type

Bit

Reset

Description

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

AUXADC_ADC_OUT_THR_HW

RO 0

Bit(s) 15

Name AUXADC_ADC_RDY_THR_HW

11:0

AUXADC_ADC_OUT_THR_HW

15 AUXAD C_ADC Name _BUSY _IN_TH R_HW RO Type

Bit

Reset Bit(s) 15

0

0

0

0

0

0

Description AUXADC thermal output data ready 0: AUXADC data proceeding 1: AUXADC data ready AUXADC thermal output data

AUXADC_THR8 31

Bit Name Type Reset

00000000

30

0

0000125C

AUXADC_THR7

AUXADC_THR8

00000003

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

Name AUXADC_ADC_BUSY_IN_THR_HW

0000125E

Description ADC busy status 0: Idle 1: Busy

AUXADC_MDRT_0

AUXADC_MDRT_0

00000002

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

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Page 629 of 1067

MT6359 PMIC Datasheet Confidential A

Bit(s)

Name

00001260

Description

AUXADC_MDRT_1

AUXADC_MDRT_1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001262

Description

AUXADC_MDRT_2

AUXADC_MDRT_2

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001264

Description

AUXADC_MDRT_3

AUXADC_MDRT_3

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 630 of 1067

MT6359 PMIC Datasheet Confidential A 00001266

AUXADC_MDRT_4 31

Bit Name Type Reset

15 AUXAD C_ADC Name _RDY_ MDRT RO Type 0 Reset

Bit

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

AUXADC_ADC_OUT_MDRT

0

0

0

Name AUXADC_ADC_RDY_MDRT

14:0

AUXADC_ADC_OUT_MDRT

15 AUXAD C_ADC Name _BUSY _IN_M DRT RO Type

Bit

Reset Bit(s) 15

0

0

0

0

RO 0

0

Description AUXADC channel 7 MDRT output data ready 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 7 MDRT output data

AUXADC_MDRT_5 31

Bit Name Type Reset

00000000

29

Bit(s) 15

00001268

AUXADC_MDRT_4

30

AUXADC_MDRT_5

00000001

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

Name AUXADC_ADC_BUSY_IN_MDRT

0000126A

Description ADC busy status 0: Idle 1: Busy

AUXADC_DCXO_MDRT_1

AUXADC_DCXO_MDRT_1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 631 of 1067

MT6359 PMIC Datasheet Confidential A 0000126C

AUXADC_DCXO_MDRT_2

AUXADC_DCXO_MDRT_2

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000126E

AUXADC_DCXO_MDRT_3 31

Bit Name Type Reset

Description

15 AUXAD C_ADC Name _RDY_ DCXO_ MDRT RO Type 0 Reset

Bit

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

AUXADC_ADC_OUT_DCXO_MDRT

0

0

0

0

Name AUXADC_ADC_RDY_DCXO_MDRT

14:0

AUXADC_ADC_OUT_DCXO_MDRT

Bit Name Type Reset

15 AUXAD C_ADC _BUSY Name _IN_DC XO_M DRT RO Type

Bit

Reset Bit(s) 15

0

0

0

RO 0

0

0

Description AUXADC channel 10 wakeup DCXO output data ready 0: AUXADC data proceeding 1: AUXADC data ready AUXADC channel 10 wakeup DCXO output data

AUXADC_DCXO_MDRT_4 31

00000000

29

Bit(s) 15

00001270

AUXADC_DCXO_MDRT_3

30

AUXADC_DCXO_MDRT_4

00000000

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

Name AUXADC_ADC_BUSY_IN_DCXO_MDRT

MediaTek Proprietary and Confidential.

Description ADC busy status 0: Idle 1: Busy

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 632 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001272

Description

AUXADC_RSV_1

AUXADC_RSV_1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001274

Description

AUXADC_PRI_NEW

AUXADC_PRI_NEW

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001276

Description

AUXADC_SPL_LIST_0

AUXADC_SPL_LIST_0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 633 of 1067

MT6359 PMIC Datasheet Confidential A 00001278

AUXADC_SPL_LIST_1

AUXADC_SPL_LIST_1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000127A

Description

AUXADC_SPL_LIST_2

AUXADC_SPL_LIST_2

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001400

Description

BUCK_TOP_DSN_ID

BUCK_TOP Design ID Register

0000D000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001402

Description

BUCK_TOP_DSN_REV0

BUCK_TOP Design Revision Register 0

00001100

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

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Page 634 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001404

Description

BUCK_TOP_DBI

BUCK_TOP Design Bank Information Register

00003E00

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001406

Description

BUCK_TOP_DXI

BUCK_TOP Design Extra Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001408

Description

BUCK_TOP_PAM0

BUCK_TOP Parameter 0

0000000C

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 635 of 1067

MT6359 PMIC Datasheet Confidential A 0000140A

BUCK_TOP_PAM1

BUCK_TOP Parameter 1

00000A18

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000140C

Description

BUCK_TOP_CLK_CON0

BUCK_TOP Clock Control 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000140E

Description

BUCK_TOP_CLK_CON0_SET

BUCK_TOP Clock Control 0 SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001410

Description

BUCK_TOP_CLK_CON0_CLR

BUCK_TOP Clock Control 0 CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

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Page 636 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001412

Description

BUCK_TOP_CLK_HWEN_CON0

BUCK_TOP Clock HWEN Control 0

00000006

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001414

Description

BUCK_TOP_CLK_HWEN_CON0_SET

BUCK_TOP Clock HWEN Control 0 SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001416

Description

BUCK_TOP_CLK_HWEN_CON0_CLR BUCK_TOP Clock HWEN Control CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 637 of 1067

MT6359 PMIC Datasheet Confidential A 00001418

BUCK_TOP_INT_CON0

BUCK_TOP Interrupt Enable Control 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000141A

Description

BUCK_TOP_INT_CON0_SET

BUCK_TOP Interrupt Enable Control 0 SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000141C

Description

BUCK_TOP_INT_CON0_CLR

BUCK_TOP Interrupt Enable Control 0 CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000141E

Description

BUCK_TOP_INT_MASK_CON0 BUCK_TOP Interrupt Mask Control 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

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Page 638 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001420

Description

BUCK_TOP_INT_MASK_CON0_SET BUCK_TOP Interrupt Mask Control 0 SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001422

Description

BUCK_TOP_INT_MASK_CON0_CLR

BUCK_TOP Interrupt Mask Control 0 CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001424

Description

BUCK_TOP_INT_STATUS0

BUCK_TOP Interrupt Status 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 639 of 1067

MT6359 PMIC Datasheet Confidential A 00001426

BUCK_TOP_INT_RAW_STATUS0

BUCK_TOP Interrupt Raw Status 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001428

Description

BUCK_TOP_VOW_CON

BUCK_TOP VOW Control Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000142A

Description

BUCK_TOP_STB_CON

BUCK_TOP STB Control Resister

000000C8

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000142C

Description

BUCK_TOP_VGP2_MINFREQ_CON BUCK_TOP VGP2 MINFREQ Control Resister

00000428

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 640 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

0000142E

Description

BUCK_TOP_VPA_MINFREQ_CON

BUCK_TOP VPA MINFREQ Control Resister

00000624

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

20

19

18

17

16

2 RG_BU CK_VG PU11_ OC_SD N_STA TUS W1C

1 RG_BU CK_VC ORE_O C_SDN _STAT US W1C

0 RG_BU CK_VP U_OC_ SDN_S TATUS

0

0

0

00001430

Description

BUCK_TOP_OC_CON0

BUCK_TOP OC Control Register 0

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

Bit

15

14

13

12

11

10

9

8

7

Name

Type Reset Bit(s) 9

8

7

6

5

4

3

2

22

6 RG_BU RG_BU RG_BU RG_BU CK_VP CK_VP CK_VS2 CK_VS1 ROC2_ A_OC_ _OC_S _OC_S OC_SD SDN_S DN_ST DN_ST N_STA TATUS ATUS ATUS TUS W1C W1C W1C W1C 0

0

0

0

21

00000000

5 4 3 RG_BU RG_BU RG_BU CK_VP CK_VM CK_VG ROC1_ ODEM_ PU12_ OC_SD OC_SD OC_SD N_STA N_STA N_STA TUS TUS TUS W1C W1C W1C 0

0

0

W1C

Name RG_BUCK_VPA_OC_SDN_STATUS

Description OC status condition (write 1 clear) 0: No OC 1: OC occurs. RG_BUCK_VS2_OC_SDN_STATUS OC status condition (write 1 clear) 0: No OC 1: OC occurs. RG_BUCK_VS1_OC_SDN_STATUS OC status condition (write 1 clear) 0: No OC 1: OC occurs. RG_BUCK_VPROC2_OC_SDN_STATUS OC status condition (write 1 clear) 0: No OC 1: OC occurs. RG_BUCK_VPROC1_OC_SDN_STATUS OC status condition (write 1 clear) 0: No OC 1: OC occurs. RG_BUCK_VMODEM_OC_SDN_STATUS OC status condition (write 1 clear) 0: No OC 1: OC occurs. RG_BUCK_VGPU12_OC_SDN_STATUS OC status condition (write 1 clear) 0: No OC 1: OC occurs. RG_BUCK_VGPU11_OC_SDN_STATUS OC status condition (write 1 clear)

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 641 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

1

RG_BUCK_VCORE_OC_SDN_STATUS

0

RG_BUCK_VPU_OC_SDN_STATUS

00001432

Description 0: No OC 1: OC occurs. OC status condition (write 1 clear) 0: No OC 1: OC occurs. OC status condition (write 1 clear) 0: No OC 1: OC occurs.

BUCK_TOP_KEY_PROT

BUCK_TOP Write Protect Key

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001434

Description

BUCK_TOP_WDTDBG0

BUCK_TOP WDTDBG0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001436

Description

BUCK_TOP_WDTDBG1

BUCK_TOP WDTDBG1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 642 of 1067

MT6359 PMIC Datasheet Confidential A 00001438

BUCK_TOP_WDTDBG2

BUCK_TOP WDTDBG2

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000143A

Description

BUCK_TOP_WDTDBG3

BUCK_TOP WDTDBG3

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000143C

Description

BUCK_TOP_WDTDBG4

BUCK_TOP WDTDBG4

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000143E

Description

BUCK_TOP_ELR_NUM

BUCK_TOP Number of ELR Register

00000006

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

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Page 643 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001440

Description

BUCK_TOP_ELR0

BUCK_TOP ELR 0 Register

000005FF

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001442

Description

BUCK_TOP_ELR1

BUCK_TOP ELR 1 Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001444

Description

BUCK_TOP_ELR2

BUCK_TOP ELR 2 Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 644 of 1067

MT6359 PMIC Datasheet Confidential A 00001480

BUCK_VPU_DSN_ID

BUCK VPU Design ID Register

00007949

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001482

Description

BUCK_VPU_DSN_REV0

BUCK VPU Design Revision Register 0

00001110

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001484

Description

BUCK_VPU_DSN_DBI

BUCK VPU Design Bank Information Register

00002A00

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001486

Description

BUCK_VPU_DSN_DXI

BUCK_VPU Design Extra Information Register

00000010

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

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Page 645 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001488

Description

BUCK_VPU_CON0

BUCK VPU Control 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

Name Type Reset Name RG_BUCK_VPU_LP

0

RG_BUCK_VPU_EN

0000148A

BUCK_VPU_CON0_SET

BUCK VPU Control 0 SET

31

30

29

28

27

26

Bit Name Type Reset

15

14

13

12

11

10

0

0

0

0

0

Name RG_BUCK_VPU_CON0_SET

0000148C 31

30

29

28

27

26

Bit Name Type Reset

15

14

13

12

11

10

MediaTek Proprietary and Confidential.

0

0

24

23

22

21

20

19

18

17

16

9

8

7

6

5

4

3

2

1

0

RG_BUCK_VPU_CON0_SET W1 0 0 0 0

0

0

0

0

0

0

BUCK VPU Control 0 CLR

Bit Name Type Reset

0

00000000

25

Description Sets up BUCK_VPU_CON0 1'b0: Not set 1'b1: Set

BUCK_VPU_CON0_CLR

0

0

Description Enter low power mode Valid once RG_BUCK_VPU_SW_OP_EN = 1'b1. 0: No LP 1: LP Enable control Valid once RG_BUCK_VPU_SW_OP_EN = 1'b1. 0: Off 1: On

Bit Name Type Reset

0

16

1 0 RG_BU RG_BU CK_VP CK_VP U_LP U_EN RW RW 0

Bit(s) 1

Bit(s) 15:0

17

0

0

00000000

25

24

23

22

21

20

19

18

17

16

9

8

7

6

5

4

3

2

1

0

RG_BUCK_VPU_CON0_CLR W1 0 0 0 0

0

0

0

0

0

0

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 646 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 15:0

Name RG_BUCK_VPU_CON0_CLR

0000148E

Description Clears BUCK_VPU_CON0 1'b0: Not clear 1'b1: Clear

BUCK_VPU_CON1

BUCK VPU Control 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

Bit(s) 6:0

RG_BUCK_VPU_VOSEL_SLEEP RW 0

Name RG_BUCK_VPU_VOSEL_SLEEP

00001490

0

0

0

0

0

Description Selects VOUT in sleep mode Vout = 0.4V + 6.25 mV*code

BUCK_VPU_SLP_CON

BUCK VPU Sleep Control

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001492

Description

BUCK_VPU_CFG0

BUCK VPU Config 0

00008F9F

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 647 of 1067

MT6359 PMIC Datasheet Confidential A 00001494

BUCK_VPU_OP_EN

BUCK VPU Operation Enable

00008000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001496

Description

BUCK_VPU_OP_EN_SET

BUCK VPU Operation Enable SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001498

Description

BUCK_VPU_OP_EN_CLR

BUCK VPU Operation Enable CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000149A

Description

BUCK_VPU_OP_CFG

BUCK VPU Operation Config

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 648 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

0000149C

Description

BUCK_VPU_OP_CFG_SET

BUCK VPU Operation Config SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000149E

Description

BUCK_VPU_OP_CFG_CLR

BUCK VPU Operation Config CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000014A0

Description

BUCK_VPU_OP_MODE

BUCK VPU Operation Mode

00007FFF

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 649 of 1067

MT6359 PMIC Datasheet Confidential A 000014A2

BUCK_VPU_OP_MODE_SET

BUCK VPU Operation Mode SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000014A4

Description

BUCK_VPU_OP_MODE_CLR

BUCK VPU Operation Mode CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000014A6

Description

BUCK_VPU_DBG0

BUCK VPU Debug 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000014A8

Description

BUCK_VPU_DBG1

BUCK VPU Debug 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 650 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

000014AA

Description

BUCK_VPU_ELR_NUM

BUCK_VPU Number of ELR Register

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000014AC

Description

BUCK_VPU_ELR0

BUCK_VPU ELR 0 Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

Bit(s) 6:0

RG_BUCK_VPU_VOSEL RW 0

Name RG_BUCK_VPU_VOSEL

00001500

0

0

0

0

0

Description Selects VOUT in normal mode (SW mode) Vout = 0.4V + 6.25 mV*code

BUCK_VCORE_DSN_ID

BUCK VCORE Design ID Register

00007949

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 651 of 1067

MT6359 PMIC Datasheet Confidential A 00001502

BUCK_VCORE_DSN_REV0

BUCK VCORE Design Revision Register 0

00001110

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001504

Description

BUCK_VCORE_DSN_DBI

BUCK VCORE Design Bank Information Register

00002A00

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001506

Description

BUCK_VCORE_DSN_DXI

BUCK_VCORE Design Extra Information Register

00000010

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001508

Description

BUCK_VCORE_CON0

BUCK VCORE Control 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

Name Type Reset MediaTek Proprietary and Confidential.

0 RG_BU RG_BU CK_VC CK_VC ORE_E ORE_LP N RW RW 0

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

16

0

Page 652 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 1

Name RG_BUCK_VCORE_LP

0

RG_BUCK_VCORE_EN

0000150A

Description Enter low power mode Valid once RG_BUCK_VCORE_SW_OP_EN = 1'b1. 0: No LP 1: LP Enable control Valid once RG_BUCK_VCORE_SW_OP_EN = 1'b1. 0: Off 1: On

BUCK_VCORE_CON0_SET

BUCK VCORE Control 0 SET

Bit Name Type Reset

31

30

29

28

27

26

Bit Name Type Reset

15

14

13

12

11

10

Bit(s) 15:0

0

0

0

0

0

0

Name RG_BUCK_VCORE_CON0_SET

0000150C

BUCK_VCORE_CON0_CLR

Bit Name Type Reset

29

28

27

26

Bit Name Type Reset

15

14

13

12

11

10

Bit(s) 15:0

0

0

Name RG_BUCK_VCORE_CON0_CLR

MediaTek Proprietary and Confidential.

23

22

21

20

19

18

17

16

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

RG_BUCK_VCORE_CON0_SET W1 0 0 0 0

BUCK VCORE Control 0 CLR

30

0

24

Description Sets up BUCK_VCORE_CON0 1'b0: Not set 1'b1: Set

31

0

00000000

25

0

0

00000000

25

24

23

22

21

20

19

18

17

16

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

RG_BUCK_VCORE_CON0_CLR W1 0 0 0 0

Description Clears BUCK_VCORE_CON0 1'b0: Not clear 1'b1: Clear

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 653 of 1067

MT6359 PMIC Datasheet Confidential A 0000150E

BUCK_VCORE_CON1

BUCK VCORE Control 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s) 6:0

RG_BUCK_VCORE_VOSEL_SLEEP RW 0

Name RG_BUCK_VCORE_VOSEL_SLEEP

00001510

0

0

0

0

0

0

Description Selects VOUT in sleep mode Vout = 0.50625V + 6.25 mV*code

BUCK_VCORE_SLP_CON

BUCK VCORE Sleep Control

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001512

Description

BUCK_VCORE_CFG0

BUCK VCORE Config 0

00008F9F

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001514

Description

BUCK_VCORE_OP_EN

BUCK VCORE Operation Enable

00008000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 654 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001516

Description

BUCK_VCORE_OP_EN_SET

BUCK VCORE Operation Enable SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001518

Description

BUCK_VCORE_OP_EN_CLR

BUCK VCORE Operation Enable CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000151A

Description

BUCK_VCORE_OP_CFG

BUCK VCORE Operation Config

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 655 of 1067

MT6359 PMIC Datasheet Confidential A 0000151C

BUCK_VCORE_OP_CFG_SET

BUCK VCORE Operation Config SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000151E

Description

BUCK_VCORE_OP_CFG_CLR

BUCK VCORE Operation Config CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001520

Description

BUCK_VCORE_OP_MODE

BUCK VCORE Operation Mode

00007FFF

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001522

Description

BUCK_VCORE_OP_MODE_SET BUCK VCORE Operation Mode SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 656 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001524

Description

BUCK_VCORE_OP_MODE_CLR

BUCK VCORE Operation Mode CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001526

Description

BUCK_VCORE_DBG0

BUCK VCORE Debug 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001528

Description

BUCK_VCORE_DBG1

BUCK VCORE Debug 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 657 of 1067

MT6359 PMIC Datasheet Confidential A 0000152A

BUCK_VCORE_ELR_NUM

BUCK_VCORE Number of ELR Register

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

20

19

18

17

16

4

3

2

1

0

0

0000152C

Description

BUCK_VCORE_ELR0

BUCK_VCORE ELR 0 Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

Bit(s) 6:0

RG_BUCK_VCORE_VOSEL RW 0

Name RG_BUCK_VCORE_VOSEL

00001580

0

0

0

0

0

Description Selects VOUT in normal mode (SW mode) Vout = 0.50625V + 6.25 mV*code

BUCK_VGPU11_DSN_ID

BUCK VGPU11 Design ID Register

00007848

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001582

Description

BUCK_VGPU11_DSN_REV0

BUCK VGPU11 Design Revision Register 0

00001110

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 658 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001584

Description

BUCK_VGPU11_DSN_DBI

BUCK VGPU11 Design Bank Information Register

00003200

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001586

Description

BUCK_VGPU11_DSN_DXI

BUCK_VGPU11 Design Extra Information Register

00000013

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

17

00001588

Description

BUCK_VGPU11_CON0

BUCK VGPU11 Control 0

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

Name Type Reset

1 0 RG_BU RG_BU CK_VG CK_VG PU11_L PU11_ P EN RW RW 0

Bit(s) 1

Name RG_BUCK_VGPU11_LP

0

RG_BUCK_VGPU11_EN

MediaTek Proprietary and Confidential.

16

1

Description Enter low power mode Valid once RG_BUCK_VGPU11_SW_OP_EN = 1'b1. 0: No LP 1: LP Enable control Valid once RG_BUCK_VGPU11_SW_OP_EN = 1'b1. 0: Off 1: On

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 659 of 1067

MT6359 PMIC Datasheet Confidential A 0000158A

BUCK_VGPU11_CON0_SET

BUCK VGPU11 Control 0 SET

Bit Name Type Reset

31

30

29

28

27

26

Bit Name Type Reset

15

14

13

12

11

10

Bit(s) 15:0

0

0

0

0

0

0

Name RG_BUCK_VGPU11_CON0_SET

0000158C

BUCK_VGPU11_CON0_CLR

Bit Name Type Reset

29

28

27

26

Bit Name Type Reset

15

14

13

12

11

10

Bit(s) 15:0

0

0

0

0

Name RG_BUCK_VGPU11_CON0_CLR

0000158E

23

22

21

20

19

18

17

16

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

RG_BUCK_VGPU11_CON0_SET W1 0 0 0 0

BUCK VGPU11 Control 0 CLR

30

0

24

Description Sets up BUCK_VGPU11_CON0 1'b0: Not set 1'b1: Set

31

0

00000000

25

00000000

25

24

23

22

21

20

19

18

17

16

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

RG_BUCK_VGPU11_CON0_CLR W1 0 0 0 0

Description Clears BUCK_VGPU11_CON0 1'b0: Not clear 1'b1: Clear

BUCK_VGPU11_CON1

BUCK VGPU11 Control 1

00000034

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s) 6:0

RG_BUCK_VGPU11_VOSEL_SLEEP RW 0

Name RG_BUCK_VGPU11_VOSEL_SLEEP

MediaTek Proprietary and Confidential.

1

1

0

1

0

0

Description Selects VOUT in sleep mode Vout = 0.4V + 6.25 mV*code

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 660 of 1067

MT6359 PMIC Datasheet Confidential A 00001590

BUCK_VGPU11_SLP_CON

BUCK VGPU11 Sleep Control

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001592

Description

BUCK_VGPU11_CFG0

BUCK VGPU11 Config 0

00008F9F

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001594

Description

BUCK_VGPU11_OP_EN

BUCK VGPU11 Operation Enable

00008000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001596

Description

BUCK_VGPU11_OP_EN_SET BUCK VGPU11 Operation Enable SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 661 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001598

Description

BUCK_VGPU11_OP_EN_CLR BUCK VGPU11 Operation Enable CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000159A

Description

BUCK_VGPU11_OP_CFG

BUCK VGPU11 Operation Config

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000159C

Description

BUCK_VGPU11_OP_CFG_SET BUCK VGPU11 Operation Config SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 662 of 1067

MT6359 PMIC Datasheet Confidential A 0000159E

BUCK_VGPU11_OP_CFG_CLR BUCK VGPU11 Operation Config CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000015A0

Description

BUCK_VGPU11_OP_MODE

BUCK VGPU11 Operation Mode

00007FFF

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000015A2

Description

BUCK_VGPU11_OP_MODE_S BUCK VGPU11 Operation Mode SET ET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000015A4

Description

BUCK_VGPU11_OP_MODE_CLR BUCK VGPU11 Operation Mode CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 663 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

000015A6

Description

BUCK_VGPU11_DBG0

BUCK VGPU11 Debug 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000015A8

Description

BUCK_VGPU11_DBG1

BUCK VGPU11 Debug 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000015AA

Description

BUCK_VGPU11_SSHUB_CON0 BUCK VGPU11 Sensor Hub Control Resister 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 664 of 1067

MT6359 PMIC Datasheet Confidential A 000015AC

BUCK_VGPU11_SPI_CON0

BUCK VGPU11 SPI Control Resister 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000015AE

Description

BUCK_VGPU11_BT_LP_CON0 BUCK VGPU11 BT_LPControl Resister 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000015B0

Description

BUCK_VGPU11_STALL_TRACK0

BUCK_VGPU11 HW Stall Tracking Register 0

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0 RG_BU CK_VG PU11_ TRACK _STALL _BYPA SS RW

Name

Type Reset Bit(s) 0

1

Name Description RG_BUCK_VGPU11_TRACK_STALL_BYPA Enables VGPU11 tracking stall bypass function SS 1'b0: HW mode 1'b1: bypass mode

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 665 of 1067

MT6359 PMIC Datasheet Confidential A 000015B2

BUCK_VGPU11_ELR_NUM

BUCK_VGPU11 Number of ELR Register

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

20

19

18

17

16

4

3

2

1

0

0

000015B4

Description

BUCK_VGPU11_ELR0

BUCK_VGPU11 ELR 0 Register

00000034

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

Bit(s) 6:0

RG_BUCK_VGPU11_VOSEL RW 0

Name RG_BUCK_VGPU11_VOSEL

00001600

1

1

0

1

0

Description Selects VOUT in normal mode (SW mode) Vout = 0.4V + 6.25 mV*code

BUCK_VGPU12_DSN_ID

BUCK VGPU12 Design ID Register

00007848

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001602

Description

BUCK_VGPU12_DSN_REV0

BUCK VGPU12 Design Revision Register 0

00001110

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 666 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001604

Description

BUCK_VGPU12_DSN_DBI

BUCK VGPU12 Design Bank Information Register

00002A00

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001606

Description

BUCK_VGPU12_DSN_DXI

BUCK_VGPU12 Design Extra Information Register

00000010

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

17

00001608

Description

BUCK_VGPU12_CON0

BUCK VGPU12 Control 0

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

Name Type Reset

1 0 RG_BU RG_BU CK_VG CK_VG PU12_L PU12_ P EN RW RW 0

Bit(s) 1

Name RG_BUCK_VGPU12_LP

0

RG_BUCK_VGPU12_EN

MediaTek Proprietary and Confidential.

16

1

Description Enter low power mode Valid once RG_BUCK_VGPU12_SW_OP_EN = 1'b1. 0: No LP 1: LP Enable control Valid once RG_BUCK_VGPU12_SW_OP_EN = 1'b1. 0: Off 1: On

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 667 of 1067

MT6359 PMIC Datasheet Confidential A 0000160A

BUCK_VGPU12_CON0_SET

BUCK VGPU12 Control 0 SET

Bit Name Type Reset

31

30

29

28

27

26

Bit Name Type Reset

15

14

13

12

11

10

Bit(s) 15:0

0

0

0

0

0

0

Name RG_BUCK_VGPU12_CON0_SET

0000160C

BUCK_VGPU12_CON0_CLR

Bit Name Type Reset

29

28

27

26

Bit Name Type Reset

15

14

13

12

11

10

Bit(s) 15:0

0

0

0

0

Name RG_BUCK_VGPU12_CON0_CLR

0000160E

23

22

21

20

19

18

17

16

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

RG_BUCK_VGPU12_CON0_SET W1 0 0 0 0

BUCK VGPU12 Control 0 CLR

30

0

24

Description Sets up BUCK_VGPU12_CON0 1'b0: Not set 1'b1: Set

31

0

00000000

25

00000000

25

24

23

22

21

20

19

18

17

16

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

RG_BUCK_VGPU12_CON0_CLR W1 0 0 0 0

Description Clears BUCK_VGPU12_CON0 1'b0: Not clear 1'b1: Clear

BUCK_VGPU12_CON1

BUCK VGPU12 Control 1

00000034

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s) 6:0

RG_BUCK_VGPU12_VOSEL_SLEEP RW 0

Name RG_BUCK_VGPU12_VOSEL_SLEEP

MediaTek Proprietary and Confidential.

1

1

0

1

0

0

Description Selects VOUT in sleep mode Vout = 0.4V + 6.25 mV*code

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 668 of 1067

MT6359 PMIC Datasheet Confidential A 00001610

BUCK_VGPU12_SLP_CON

BUCK VGPU12 Sleep Control

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001612

Description

BUCK_VGPU12_CFG0

BUCK VGPU12 Config 0

00008F9F

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001614

Description

BUCK_VGPU12_OP_EN

BUCK VGPU12 Operation Enable

00008000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001616

Description

BUCK_VGPU12_OP_EN_SET BUCK VGPU12 Operation Enable SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 669 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001618

Description

BUCK_VGPU12_OP_EN_CLR BUCK VGPU12 Operation Enable CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000161A

Description

BUCK_VGPU12_OP_CFG

BUCK VGPU12 Operation Config

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000161C

Description

BUCK_VGPU12_OP_CFG_SET BUCK VGPU12 Operation Config SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 670 of 1067

MT6359 PMIC Datasheet Confidential A 0000161E

BUCK_VGPU12_OP_CFG_CLR BUCK VGPU12 Operation Config CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001620

Description

BUCK_VGPU12_OP_MODE

BUCK VGPU12 Operation Mode

00007FFF

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001622

Description

BUCK_VGPU12_OP_MODE_SET

BUCK VGPU12 Operation Mode SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001624

Description

BUCK_VGPU12_OP_MODE_CLR

BUCK VGPU12 Operation Mode CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 671 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001626

Description

BUCK_VGPU12_DBG0

BUCK VGPU12 Debug 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001628

Description

BUCK_VGPU12_DBG1

BUCK VGPU12 Debug 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000162A

Description

BUCK_VGPU12_ELR_NUM

BUCK_VGPU12 Number of ELR Register

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 672 of 1067

MT6359 PMIC Datasheet Confidential A 0000162C

BUCK_VGPU12_ELR0

BUCK_VGPU12 ELR 0 Register

00000034

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

Bit(s) 6:0

20

19

18

17

16

4

3

2

1

0

0

RG_BUCK_VGPU12_VOSEL RW 0

Name RG_BUCK_VGPU12_VOSEL

00001680

1

1

0

1

0

Description Selects VOUT in normal mode (SW mode) Vout = 0.4V + 6.25 mV*code

BUCK_VMODEM_DSN_ID

BUCK VMODEM Design ID Register

00006333

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001682

Description

BUCK_VMODEM_DSN_REV0 BUCK VMODEM Design Revision Register 0

00001110

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 673 of 1067

MT6359 PMIC Datasheet Confidential A 00001684

BUCK_VMODEM_DSN_DBI

BUCK VMODEM Design Bank Information Register

00002C00

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001686

Description

BUCK_VMODEM_DSN_DXI

BUCK_VMODEM Design Extra Information Register

00000012

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

17

00001688

Description

BUCK_VMODEM_CON0

BUCK VMODEM Control 0

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

Name Type Reset

1 0 RG_BU RG_BU CK_VM CK_VM ODEM_ ODEM LP _EN RW RW 0

Bit(s) 1

Name RG_BUCK_VMODEM_LP

0

RG_BUCK_VMODEM_EN

MediaTek Proprietary and Confidential.

16

1

Description Enter low power mode Valid once RG_BUCK_VMODEM_SW_OP_EN = 1'b1. 0: No LP 1: LP Enable control Valid once RG_BUCK_VMODEM_SW_OP_EN = 1'b1. 0: Off 1: On

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 674 of 1067

MT6359 PMIC Datasheet Confidential A 0000168A

BUCK_VMODEM_CON0_SET BUCK VMODEM Control 0 SET

Bit Name Type Reset

31

30

29

28

27

26

Bit Name Type Reset

15

14

13

12

11

10

Bit(s) 15:0

0

0

0

0

0

0

Name RG_BUCK_VMODEM_CON0_SET

0000168C

24

23

22

21

20

19

18

17

16

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

RG_BUCK_VMODEM_CON0_SET W1 0 0 0 0

Description Sets up BUCK_VMODEM_CON0 1'b0: Not set 1'b1: Set

BUCK_VMODEM_CON0_CLR BUCK VMODEM Control 0 CLR

Bit Name Type Reset

31

30

29

28

27

26

Bit Name Type Reset

15

14

13

12

11

10

Bit(s) 15:0

00000000

25

0

0

0

0

0

0

Name RG_BUCK_VMODEM_CON0_CLR

0000168E

00000000

25

24

23

22

21

20

19

18

17

16

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

RG_BUCK_VMODEM_CON0_CLR W1 0 0 0 0

Description Clears BUCK_VMODEM_CON0 1'b0: Not clear 1'b1: Clear

BUCK_VMODEM_CON1

BUCK VMODEM Control 1

00000030

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s) 6:0

RG_BUCK_VMODEM_VOSEL_SLEEP RW 0

Name RG_BUCK_VMODEM_VOSEL_SLEEP

MediaTek Proprietary and Confidential.

1

1

0

0

0

0

Description Selects VOUT in sleep mode Vout = 0.4V + 6.25 mV*code

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 675 of 1067

MT6359 PMIC Datasheet Confidential A 00001690

BUCK_VMODEM_SLP_CON

BUCK VMODEM Sleep Control

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001692

Description

BUCK_VMODEM_CFG0

BUCK VMODEM Config 0

00008585

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001694

Description

BUCK_VMODEM_OP_EN

BUCK VMODEM Operation Enable

00008000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001696

Description

BUCK_VMODEM_OP_EN_SET BUCK VMODEM Operation Enable SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 676 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001698

Description

BUCK_VMODEM_OP_EN_CLR BUCK VMODEM Operation Enable CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000169A

Description

BUCK_VMODEM_OP_CFG

BUCK VMODEM Operation Config

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000169C

Description

BUCK_VMODEM_OP_CFG_SE BUCK VMODEM Operation Config SET T

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 677 of 1067

MT6359 PMIC Datasheet Confidential A 0000169E

BUCK_VMODEM_OP_CFG_CLR

BUCK VMODEM Operation Config CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000016A0

Description

BUCK_VMODEM_OP_MODE BUCK VMODEM Operation Mode

00007FFF

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000016A2

Description

BUCK_VMODEM_OP_MODE_SET BUCK VMODEM Operation Mode SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000016A4

Description

BUCK_VMODEM_OP_MODE_CLR BUCK VMODEM Operation Mode CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 678 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

000016A6

Description

BUCK_VMODEM_DBG0

BUCK VMODEM Debug 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000016A8

Description

BUCK_VMODEM_DBG1

BUCK VMODEM Debug 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000016AA

Description

BUCK_VMODEM_STALL_TRACK0 BUCK_VMODEM HW Stall Tracking Register 0

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0 RG_BU CK_VM ODEM _TRAC K_STAL L_BYP ASS RW

Name

Type Reset Bit(s) 0

1

Name Description RG_BUCK_VMODEM_TRACK_STALL_BYP Enables VMODEM tracking stall bypass function ASS 1'b0: HW mode 1'b1: bypass mode

MediaTek Proprietary and Confidential.

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Page 679 of 1067

MT6359 PMIC Datasheet Confidential A 000016AC

BUCK_VMODEM_ELR_NUM BUCK_VMODEM Number of ELR Register

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

20

19

18

17

16

4

3

2

1

0

0

000016AE

Description

BUCK_VMODEM_ELR0

BUCK_VMODEM ELR 0 Register

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

Bit(s) 6:0

00000030

RG_BUCK_VMODEM_VOSEL RW 0

Name RG_BUCK_VMODEM_VOSEL

00001700

1

1

0

0

0

Description Selects VOUT in normal mode (SW mode) Vout = 0.4V + 6.25 mV*code

BUCK_VPROC1_DSN_ID

BUCK VPROC1 Design ID Register

00007848

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001702

Description

BUCK_VPROC1_DSN_REV0

BUCK VPROC1 Design Revision Register 0

00001110

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 680 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001704

Description

BUCK_VPROC1_DSN_DBI

BUCK VPROC1 Design Bank Information Register

00002C00

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001706

Description

BUCK_VPROC1_DSN_DXI

BUCK_VPROC1 Design Extra Information Register

00000012

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

17

00001708

Description

BUCK_VPROC1_CON0

BUCK VPROC1 Control 0

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

Name Type Reset

1 0 RG_BU RG_BU CK_VP CK_VP ROC1_L ROC1_ P EN RW RW 0

Bit(s) 1

Name RG_BUCK_VPROC1_LP

0

RG_BUCK_VPROC1_EN

MediaTek Proprietary and Confidential.

16

1

Description Enter low power mode Valid once RG_BUCK_VPROC1_SW_OP_EN = 1'b1. 0: No LP 1: LP Enable control Valid once RG_BUCK_VPROC1_SW_OP_EN = 1'b1. 0: Off 1: On

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 681 of 1067

MT6359 PMIC Datasheet Confidential A 0000170A

BUCK_VPROC1_CON0_SET

BUCK VPROC1 Control 0 SET

Bit Name Type Reset

31

30

29

28

27

26

Bit Name Type Reset

15

14

13

12

11

10

Bit(s) 15:0

0

0

0

0

0

0

Name RG_BUCK_VPROC1_CON0_SET

0000170C

BUCK_VPROC1_CON0_CLR

Bit Name Type Reset

29

28

27

26

Bit Name Type Reset

15

14

13

12

11

10

Bit(s) 15:0

0

0

0

0

Name RG_BUCK_VPROC1_CON0_CLR

0000170E

23

22

21

20

19

18

17

16

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

RG_BUCK_VPROC1_CON0_SET W1 0 0 0 0

BUCK VPROC1 Control 0 CLR

30

0

24

Description Sets up BUCK_VPROC1_CON0 1'b0: Not set 1'b1: Set

31

0

00000000

25

00000000

25

24

23

22

21

20

19

18

17

16

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

RG_BUCK_VPROC1_CON0_CLR W1 0 0 0 0

Description Clears BUCK_VPROC1_CON0 1'b0: Not clear 1'b1: Clear

BUCK_VPROC1_CON1

BUCK VPROC1 Control 1

00000038

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s) 6:0

RG_BUCK_VPROC1_VOSEL_SLEEP RW 0

Name RG_BUCK_VPROC1_VOSEL_SLEEP

MediaTek Proprietary and Confidential.

1

1

1

0

0

0

Description Selects VOUT in sleep mode Vout = 0.4V + 6.25 mV*code

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 682 of 1067

MT6359 PMIC Datasheet Confidential A 00001710

BUCK_VPROC1_SLP_CON

BUCK VPROC1 Sleep Control

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001712

Description

BUCK_VPROC1_CFG0

BUCK VPROC1 Config 0

00008F9F

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001714

Description

BUCK_VPROC1_OP_EN

BUCK VPROC1 Operation Enable

00008000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001716

Description

BUCK_VPROC1_OP_EN_SET

BUCK VPROC1 Operation Enable SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

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Page 683 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001718

Description

BUCK_VPROC1_OP_EN_CLR BUCK VPROC1 Operation Enable CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000171A

Description

BUCK_VPROC1_OP_CFG

BUCK VPROC1 Operation Config

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000171C

Description

BUCK_VPROC1_OP_CFG_SET BUCK VPROC1 Operation Config SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 684 of 1067

MT6359 PMIC Datasheet Confidential A 0000171E

BUCK_VPROC1_OP_CFG_CLR BUCK VPROC1 Operation Config CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001720

Description

BUCK_VPROC1_OP_MODE

BUCK VPROC1 Operation Mode

00007FFF

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001722

Description

BUCK_VPROC1_OP_MODE_SET

BUCK VPROC1 Operation Mode SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001724

Description

BUCK_VPROC1_OP_MODE_CLR

BUCK VPROC1 Operation Mode CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 685 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001726

Description

BUCK_VPROC1_DBG0

BUCK VPROC1 Debug 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001728

Description

BUCK_VPROC1_DBG1

BUCK VPROC1 Debug 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000172A

Description

BUCK_VPROC1_STALL_TRACK BUCK_VPROC1 HW Stall Tracking Register 0 0

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0 RG_BU CK_VP ROC1_ TRACK _STALL _BYPA SS RW

Name

Type Reset Bit(s) 0

1

Name Description RG_BUCK_VPROC1_TRACK_STALL_BYPA Enables VPROC1 tracking stall bypass function SS 1'b0: HW mode 1'b1: bypass mode

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 686 of 1067

MT6359 PMIC Datasheet Confidential A 0000172C

BUCK_VPROC1_ELR_NUM

BUCK_VPROC1 Number of ELR Register

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

20

19

18

17

16

4

3

2

1

0

0

0000172E

Description

BUCK_VPROC1_ELR0

BUCK_VPROC1 ELR 0 Register

00000038

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

Bit(s) 6:0

RG_BUCK_VPROC1_VOSEL RW 0

Name RG_BUCK_VPROC1_VOSEL

00001780

1

1

1

0

0

Description Selects VOUT in normal mode (SW mode) Vout = 0.4V + 6.25 mV*code

BUCK_VPROC2_DSN_ID

BUCK VPROC2 Design ID Register

00007848

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001782

Description

BUCK_VPROC2_DSN_REV0

BUCK VPROC2 Design Revision Register 0

00001110

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 687 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001784

Description

BUCK_VPROC2_DSN_DBI

BUCK VPROC2 Design Bank Information Register

00003000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001786

Description

BUCK_VPROC2_DSN_DXI

BUCK_VPROC2 Design Extra Information Register

00000012

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

17

00001788

Description

BUCK_VPROC2_CON0

BUCK VPROC2 Control 0

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

Name Type Reset

1 0 RG_BU RG_BU CK_VP CK_VP ROC2_L ROC2_ P EN RW RW 0

Bit(s) 1

Name RG_BUCK_VPROC2_LP

0

RG_BUCK_VPROC2_EN

MediaTek Proprietary and Confidential.

16

1

Description Enter low power mode Valid once RG_BUCK_VPROC2_SW_OP_EN = 1'b1. 0: No LP 1: LP Enable control Valid once RG_BUCK_VPROC2_SW_OP_EN = 1'b1. 0: Off 1: On

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 688 of 1067

MT6359 PMIC Datasheet Confidential A 0000178A

BUCK_VPROC2_CON0_SET

BUCK VPROC2 Control 0 SET

Bit Name Type Reset

31

30

29

28

27

26

Bit Name Type Reset

15

14

13

12

11

10

Bit(s) 15:0

0

0

0

0

0

0

Name RG_BUCK_VPROC2_CON0_SET

0000178C

00000000

25

24

23

22

21

20

19

18

17

16

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

RG_BUCK_VPROC2_CON0_SET W1 0 0 0 0

Description Sets up BUCK_VPROC2_CON0 1'b0: Not set 1'b1: Set

BUCK_VPROC2_CON0_CLR

BUCK VPROC2 Control 0 CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

Bit(s) 15:0

0

0

0

0

0

0

Name RG_BUCK_VPROC2_CON0_CLR

0000178E

RG_BUCK_VPROC2_CON0_CLR W1 0 0 0 0

Description Clears BUCK_VPROC2_CON0 1'b0: Not clear 1'b1: Clear

BUCK_VPROC2_CON1

BUCK VPROC2 Control 1

00000038

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s) 6:0

RG_BUCK_VPROC2_VOSEL_SLEEP RW 0

Name RG_BUCK_VPROC2_VOSEL_SLEEP

MediaTek Proprietary and Confidential.

1

1

1

0

0

0

Description Selects VOUT in sleep mode Vout = 0.4V + 6.25 mV*code

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 689 of 1067

MT6359 PMIC Datasheet Confidential A 00001790

BUCK_VPROC2_SLP_CON

BUCK VPROC2 Sleep Control

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001792

Description

BUCK_VPROC2_CFG0

BUCK VPROC2 Config 0

00008F9F

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001794

Description

BUCK_VPROC2_OP_EN

BUCK VPROC2 Operation Enable

00008000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001796

Description

BUCK_VPROC2_OP_EN_SET

BUCK VPROC2 Operation Enable SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

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Page 690 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001798

Description

BUCK_VPROC2_OP_EN_CLR BUCK VPROC2 Operation Enable CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000179A

Description

BUCK_VPROC2_OP_CFG

BUCK VPROC2 Operation Config

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000179C

Description

BUCK_VPROC2_OP_CFG_SET BUCK VPROC2 Operation Config SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 691 of 1067

MT6359 PMIC Datasheet Confidential A 0000179E

BUCK_VPROC2_OP_CFG_CLR BUCK VPROC2 Operation Config CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000017A0

Description

BUCK_VPROC2_OP_MODE

BUCK VPROC2 Operation Mode

00007FFF

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000017A2

Description

BUCK_VPROC2_OP_MODE_SET

BUCK VPROC2 Operation Mode SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000017A4

Description

BUCK_VPROC2_OP_MODE_CLR

BUCK VPROC2 Operation Mode CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 692 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

000017A6

Description

BUCK_VPROC2_DBG0

BUCK VPROC2 Debug 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000017A8

Description

BUCK_VPROC2_DBG1

BUCK VPROC2 Debug 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000017AA

Description

BUCK_VPROC2_TRACK0

BUCK_VPROC2 HW Tracking Register 0

00000002

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0 RG_BU CK_VP ROC2_ TRACK _EN RW

Name

Type Reset Bit(s) 0

0

Name RG_BUCK_VPROC2_TRACK_EN

MediaTek Proprietary and Confidential.

Description Enables VPROC2 tracking function 1'b0: Disable 1'b1: Enable

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 693 of 1067

MT6359 PMIC Datasheet Confidential A 000017AC

BUCK_VPROC2_TRACK1

BUCK_VPROC2 HW Tracking Register 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000017AE

Description

BUCK_VPROC2_STALL_TRACK0

BUCK_VPROC2 HW Stall Tracking Register 0

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0 RG_BU CK_VP ROC2_ TRACK _STALL _BYPA SS RW

Name

Type Reset Bit(s) 0

1

Name Description RG_BUCK_VPROC2_TRACK_STALL_BYPA Enables VPROC2 tracking stall bypass function SS 1'b0: HW mode 1'b1: bypass mode

000017B0

BUCK_VPROC2_ELR_NUM

BUCK_VPROC2 Number of ELR Register

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 694 of 1067

MT6359 PMIC Datasheet Confidential A 000017B2

BUCK_VPROC2_ELR0

BUCK_VPROC2 ELR 0 Register

00000038

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

Bit(s) 6:0

20

19

18

17

16

4

3

2

1

0

0

RG_BUCK_VPROC2_VOSEL RW 0

Name RG_BUCK_VPROC2_VOSEL

00001800

1

1

1

0

0

Description Selects VOUT in normal mode (SW mode) Vout = 0.4V + 6.25 mV*code

BUCK_VS1_DSN_ID

BUCK VS1 Design ID Register

00006030

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001802

Description

BUCK_VS1_DSN_REV0

BUCK VS1 Design Revision Register 0

00001110

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001804

Description

BUCK_VS1_DSN_DBI

BUCK VS1 Design Bank Information Register

00003200

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

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Page 695 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001806

Description

BUCK_VS1_DSN_DXI

BUCK_VS1 Design Extra Information Register

00000018

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

17

00001808

Description

BUCK_VS1_CON0

BUCK VS1 Control 0

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

Name Type Reset Name RG_BUCK_VS1_LP

0

RG_BUCK_VS1_EN

0000180A

BUCK_VS1_CON0_SET

BUCK VS1 Control 0 SET

31

30

29

28

27

26

Bit Name Type Reset

15

14

13

12

11

0

0

0

0

Name RG_BUCK_VS1_CON0_SET

MediaTek Proprietary and Confidential.

1

Description Enter low power mode Valid once RG_BUCK_VS1_SW_OP_EN = 1'b1. 0: No LP 1: LP Enable control Valid once RG_BUCK_VS1_SW_OP_EN = 1'b1. 0: Off 1: On

Bit Name Type Reset

Bit(s) 15:0

1 0 RG_BU RG_BU CK_VS1 CK_VS _LP 1_EN RW RW 0

Bit(s) 1

16

0

00000000

25

24

23

22

21

20

19

18

17

16

10

9

8

7

6

5

4

3

2

1

0

0

RG_BUCK_VS1_CON0_SET W1 0 0 0 0

0

0

0

0

0

0

Description Sets up BUCK_VS1_CON0 1'b0: Not set

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 696 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

0000180C

Description 1'b1: Set

BUCK_VS1_CON0_CLR

BUCK VS1 Control 0 CLR

Bit Name Type Reset

31

30

29

28

27

26

Bit Name Type Reset

15

14

13

12

11

Bit(s) 15:0

0

0

0

0

0

24

23

22

21

20

19

18

17

16

10

9

8

7

6

5

4

3

2

1

0

0

RG_BUCK_VS1_CON0_CLR W1 0 0 0 0

0

0

0

0

0

0

Name RG_BUCK_VS1_CON0_CLR

0000180E

00000000

25

Description Clears BUCK_VS1_CON0 1'b0: Not clear 1'b1: Clear

BUCK_VS1_CON1

BUCK VS1 Control 1

00000060

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

Bit(s) 6:0

RG_BUCK_VS1_VOSEL_SLEEP RW 1

Name RG_BUCK_VS1_VOSEL_SLEEP

00001810

1

0

0

0

0

Description Selects VOUT in sleep mode VOUT = 2*(0.4V + 6.25 mV*code)

BUCK_VS1_SLP_CON

BUCK VS1 Sleep Control

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 697 of 1067

MT6359 PMIC Datasheet Confidential A 00001812

BUCK_VS1_CFG0

BUCK VS1 Config 0

000099E7

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001814

Description

BUCK_VS1_OP_EN

BUCK VS1 Operation Enable

00008000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001816

Description

BUCK_VS1_OP_EN_SET

BUCK VS1 Operation Enable SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001818

Description

BUCK_VS1_OP_EN_CLR

BUCK VS1 Operation Enable CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 698 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

0000181A

Description

BUCK_VS1_OP_CFG

BUCK VS1 Operation Config

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000181C

Description

BUCK_VS1_OP_CFG_SET

BUCK VS1 Operation Config SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000181E

Description

BUCK_VS1_OP_CFG_CLR

BUCK VS1 Operation Config CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 699 of 1067

MT6359 PMIC Datasheet Confidential A 00001820

BUCK_VS1_OP_MODE

BUCK VS1 Operation Mode

00007FFF

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001822

Description

BUCK_VS1_OP_MODE_SET

BUCK VS1 Operation Mode SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001824

Description

BUCK_VS1_OP_MODE_CLR

BUCK VS1 Operation Mode CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001826

Description

BUCK_VS1_DBG0

BUCK VS1 Debug 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 700 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001828

Description

BUCK_VS1_DBG1

BUCK VS1 Debug 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000182A

Description

BUCK_VS1_VOTER

BUCK VS1 VOTER

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000182C

Description

BUCK_VS1_VOTER_SET

BUCK VS1 VOTER SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 701 of 1067

MT6359 PMIC Datasheet Confidential A 0000182E

BUCK_VS1_VOTER_CLR

BUCK VS1 VOTER CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001830

Description

BUCK_VS1_VOTER_CFG

BUCK VS1 VOTER Configure

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001832

Description

BUCK_VS1_ELR_NUM

BUCK_VS1 Number of ELR Register

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

20

19

18

17

16

4

3

2

1

0

0

0

00001834

Description

BUCK_VS1_ELR0

BUCK_VS1 ELR 0 Register

00000060

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

MediaTek Proprietary and Confidential.

RG_BUCK_VS1_VOSEL RW 1

1

0

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

0

0

Page 702 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 6:0

Name RG_BUCK_VS1_VOSEL

00001880

Description Selects VOUT in normal mode (SW mode) VOUT = 2*(0.4V + 6.25 mV*code)

BUCK_VS2_DSN_ID

BUCK VS2 Design ID Register

00006030

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001882

Description

BUCK_VS2_DSN_REV0

BUCK VS2 Design Revision Register 0

00001110

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001884

Description

BUCK_VS2_DSN_DBI

BUCK VS2 Design Bank Information Register

00003200

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

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Page 703 of 1067

MT6359 PMIC Datasheet Confidential A 00001886

BUCK_VS2_DSN_DXI

BUCK_VS2 Design Extra Information Register

00000018

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

17

00001888

Description

BUCK_VS2_CON0

BUCK VS2 Control 0

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

Name Type Reset Name RG_BUCK_VS2_LP

0

RG_BUCK_VS2_EN

0000188A

BUCK_VS2_CON0_SET

BUCK VS2 Control 0 SET

31

30

29

28

27

26

Bit Name Type Reset

15

14

13

12

11

0

0

0

0

Name RG_BUCK_VS2_CON0_SET

MediaTek Proprietary and Confidential.

1

Description Enter low power mode Valid once RG_BUCK_VS2_SW_OP_EN = 1'b1. 0: No LP 1: LP Enable control Valid once RG_BUCK_VS2_SW_OP_EN = 1'b1. 0: Off 1: On

Bit Name Type Reset

Bit(s) 15:0

1 0 RG_BU RG_BU CK_VS2 CK_VS _LP 2_EN RW RW 0

Bit(s) 1

16

0

00000000

25

24

23

22

21

20

19

18

17

16

10

9

8

7

6

5

4

3

2

1

0

0

RG_BUCK_VS2_CON0_SET W1 0 0 0 0

0

0

0

0

0

0

Description Sets up BUCK_VS2_CON0 1'b0: Not set 1'b1: Set

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 704 of 1067

MT6359 PMIC Datasheet Confidential A 0000188C

BUCK_VS2_CON0_CLR

BUCK VS2 Control 0 CLR

Bit Name Type Reset

31

30

29

28

27

26

Bit Name Type Reset

15

14

13

12

11

Bit(s) 15:0

0

0

0

0

0

24

23

22

21

20

19

18

17

16

10

9

8

7

6

5

4

3

2

1

0

0

RG_BUCK_VS2_CON0_CLR W1 0 0 0 0

0

0

0

0

0

0

20

19

18

17

16

4

3

2

1

0

0

Name RG_BUCK_VS2_CON0_CLR

0000188E

00000000

25

Description Clears BUCK_VS2_CON0 1'b0: Not clear 1'b1: Clear

BUCK_VS2_CON1

BUCK VS2 Control 1

0000002C

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

Bit(s) 6:0

RG_BUCK_VS2_VOSEL_SLEEP RW 0

Name RG_BUCK_VS2_VOSEL_SLEEP

00001890

1

0

1

1

0

Description Selects VOUT in sleep mode VOUT = 2*(0.4V + 6.25 mV*code)

BUCK_VS2_SLP_CON

BUCK VS2 Sleep Control

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 705 of 1067

MT6359 PMIC Datasheet Confidential A 00001892

BUCK_VS2_CFG0

BUCK VS2 Config 0

000099E7

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001894

Description

BUCK_VS2_OP_EN

BUCK VS2 Operation Enable

00008000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001896

Description

BUCK_VS2_OP_EN_SET

BUCK VS2 Operation Enable SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001898

Description

BUCK_VS2_OP_EN_CLR

BUCK VS2 Operation Enable CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 706 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

0000189A

Description

BUCK_VS2_OP_CFG

BUCK VS2 Operation Config

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000189C

Description

BUCK_VS2_OP_CFG_SET

BUCK VS2 Operation Config SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000189E

Description

BUCK_VS2_OP_CFG_CLR

BUCK VS2 Operation Config CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 707 of 1067

MT6359 PMIC Datasheet Confidential A 000018A0

BUCK_VS2_OP_MODE

BUCK VS2 Operation Mode

00007FFF

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000018A2

Description

BUCK_VS2_OP_MODE_SET

BUCK VS2 Operation Mode SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000018A4

Description

BUCK_VS2_OP_MODE_CLR

BUCK VS2 Operation Mode CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000018A6

Description

BUCK_VS2_DBG0

BUCK VS2 Debug 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 708 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

000018A8

Description

BUCK_VS2_DBG1

BUCK VS2 Debug 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000018AA

Description

BUCK_VS2_VOTER

BUCK VS2 VOTER

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000018AC

Description

BUCK_VS2_VOTER_SET

BUCK VS2 VOTER SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 709 of 1067

MT6359 PMIC Datasheet Confidential A 000018AE

BUCK_VS2_VOTER_CLR

BUCK VS2 VOTER CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000018B0

Description

BUCK_VS2_VOTER_CFG

BUCK VS2 VOTER Configure

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000018B2

Description

BUCK_VS2_ELR_NUM

BUCK_VS2 Number of ELR Register

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

20

19

18

17

16

4

3

2

1

0

0

0

000018B4

Description

BUCK_VS2_ELR0

BUCK_VS2 ELR 0 Register

0000002C

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

MediaTek Proprietary and Confidential.

RG_BUCK_VS2_VOSEL RW 0

1

0

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

1

1

Page 710 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 6:0

Name RG_BUCK_VS2_VOSEL

00001900

Description Selects VOUT in normal mode (SW mode) VOUT = 2*(0.4V + 6.25 mV*code)

BUCK_VPA_DSN_ID

BUCK VPA Design ID Register

00006232

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001902

Description

BUCK_VPA_DSN_REV0

BUCK VPA Design Revision Register 0

00001010

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001904

Description

BUCK_VPA_DSN_DBI

BUCK VPA Design Bank Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

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Page 711 of 1067

MT6359 PMIC Datasheet Confidential A 00001906

BUCK_VPA_DSN_DXI

BUCK_VPA Design Extra Information Register

00000030

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

17

00001908

Description

BUCK_VPA_CON0

BUCK VPA Control 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

Name Type Reset Name RG_BUCK_VPA_LP

0

RG_BUCK_VPA_EN

0000190A

BUCK_VPA_CON0_SET

BUCK VPA Control 0 SET

31

30

29

28

27

26

Bit Name Type Reset

15

14

13

12

11

10

0

0

0

0

Name RG_BUCK_VPA_CON0_SET

MediaTek Proprietary and Confidential.

0

Description Enter low power mode (SW mode) 0: No LP 1: LP Enable control (SW mode) 0: Off 1: On

Bit Name Type Reset

Bit(s) 15:0

1 0 RG_BU RG_BU CK_VP CK_VP A_LP A_EN RW RW 0

Bit(s) 1

16

0

0

00000000

25

24

23

22

21

20

19

18

17

16

9

8

7

6

5

4

3

2

1

0

RG_BUCK_VPA_CON0_SET W1 0 0 0 0

0

0

0

0

0

0

Description Sets up BUCK_VPA_CON0 1'b0: Not set 1'b1: Set

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 712 of 1067

MT6359 PMIC Datasheet Confidential A 0000190C

BUCK_VPA_CON0_CLR

BUCK VPA Control 0 CLR

Bit Name Type Reset

31

30

29

28

27

26

Bit Name Type Reset

15

14

13

12

11

10

Bit(s) 15:0

0

0

0

0

0

0

Name RG_BUCK_VPA_CON0_CLR

0000190E

00000000

25

24

23

22

21

20

19

18

17

16

9

8

7

6

5

4

3

2

1

0

RG_BUCK_VPA_CON0_CLR W1 0 0 0 0

0

0

0

0

0

0

Description Clears BUCK_VPA_CON0 1'b0: Not clear 1'b1: Clear

BUCK_VPA_CON1

BUCK VPA Control 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

Bit(s) 5:0

RG_BUCK_VPA_VOSEL RW 0

Name RG_BUCK_VPA_VOSEL

00001910

0

0

0

0

Description Selects VOUT in normal mode (SW mode) VOUT = 0.5V + 50 mV*code

BUCK_VPA_CFG0

BUCK VPA Config 0

00008181

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 713 of 1067

MT6359 PMIC Datasheet Confidential A 00001912

BUCK_VPA_CFG1

BUCK VPA Config 1

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

19

18

17

16

3

2

1

0

0

00001914

Description

BUCK_VPA_DBG0

BUCK VPA Debug 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

Bit(s) 13:8 5:0

DA_VPA_VOSEL_GRAY

DA_VPA_VOSEL

RO 0

0

0

RO 0

Name DA_VPA_VOSEL_GRAY DA_VPA_VOSEL

00001916

0

0

0

0

0

0

0

Description Selects BUCK VPA VOUT in gray format Selects BUCK VPA VOUT in binary format VOUT = 0.5V + 50 mV*code

BUCK_VPA_DBG1

BUCK VPA Debug 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 714 of 1067

MT6359 PMIC Datasheet Confidential A 00001918

BUCK_VPA_DLC_CON0

BUCK VPA DLC Control Register 0

00002E14

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000191A

Description

BUCK_VPA_DLC_CON1

BUCK VPA DLC Control Register 1

00000E00

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000191C

Description

BUCK_VPA_DLC_CON2

BUCK VPA DLC Control Register 2

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000191E

Description

BUCK_VPA_MSFG_CON0

BUCK VPA Multi-Soft-Chang Control Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 715 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001920

Description

BUCK_VPA_MSFG_CON1

BUCK VPA Multi-Soft-Chang Control Register 1

00000505

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001922

Description

BUCK_VPA_MSFG_RRATE0

BUCK VPA Multi-Soft-Chang Rising Rate Register 0

00000202

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001924

Description

BUCK_VPA_MSFG_RRATE1

BUCK VPA Multi-Soft-Chang Rising Rate Register 1

00000202

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 716 of 1067

MT6359 PMIC Datasheet Confidential A 00001926

BUCK_VPA_MSFG_RRATE2

BUCK VPA Multi-Soft-Chang Rising Rate Register 2

00000202

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001928

Description

BUCK_VPA_MSFG_RTHD0

BUCK VPA Multi-Soft-Chang Rising Threshold Register 0

0000000A

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000192A

Description

BUCK_VPA_MSFG_RTHD1

BUCK VPA Multi-Soft-Chang Rising Threshold Register 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 717 of 1067

MT6359 PMIC Datasheet Confidential A 0000192C

BUCK_VPA_MSFG_RTHD2

BUCK VPA Multi-Soft-Chang Rising Threshold Register 2

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000192E

Description

BUCK_VPA_MSFG_FRATE0

BUCK VPA Multi-Soft-Chang Falling Rate Register 0

00000202

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001930

Description

BUCK_VPA_MSFG_FRATE1

BUCK VPA Multi-Soft-Chang Falling Rate Register 1

00000202

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 718 of 1067

MT6359 PMIC Datasheet Confidential A 00001932

BUCK_VPA_MSFG_FRATE2

BUCK VPA Multi-Soft-Chang Falling Rate Register 2

00002202

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001934

Description

BUCK_VPA_MSFG_FTHD0

BUCK VPA Multi-Soft-Chang Falling Threshold Register 0

00000032

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001936

Description

BUCK_VPA_MSFG_FTHD1

BUCK VPA Multi-Soft-Chang Falling Threshold Register 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 719 of 1067

MT6359 PMIC Datasheet Confidential A 00001938

BUCK_VPA_MSFG_FTHD2

BUCK VPA Multi-Soft-Chang Falling Threshold Register 2

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001980

Description

BUCK_ANA0_DSN_ID

BUCK_ANA0 Design ID Register

00000034

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001982

Description

BUCK_ANA0_DSN_REV0

BUCK_ANA0 Design Revision Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001984

Description

BUCK_ANA0_DSN_DBI

BUCK_ANA0 Design Bank Information Register

00003800

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 720 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001986

Description

BUCK_ANA0_DSN_FPI

BUCK_ANA0 Design Extra Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001988

Description

SMPS_ANA_CON0

SMPS Control Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000198A

Description

VGPUVCORE_ANA_CON0

VGPUVCORE Control Register 0

00000621

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 721 of 1067

MT6359 PMIC Datasheet Confidential A 0000198C

VGPUVCORE_ANA_CON1

VGPUVCORE Control Register 1

00000511

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000198E

Description

VGPUVCORE_ANA_CON2

VGPUVCORE Control Register 2

00000005

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11 RG_VG PU11_ NONA UDIBLE _EN RW

10

9

8

7

6

5

4

3

2

1

0

Name

Type Reset Bit(s) 11 9

RG_VG PU11_F CCM RW

0

0

Name RG_VGPU11_NONAUDIBLE_EN RG_VGPU11_FCCM

00001990

Description Enables PFM frequency > 25 kHz 1'b0: Auto-mode (default) 1'b1: Force PWM

VGPUVCORE_ANA_CON3

VGPUVCORE Control Register 3

000000FF

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 722 of 1067

MT6359 PMIC Datasheet Confidential A 00001992

VGPUVCORE_ANA_CON4

VGPUVCORE Control Register 4

00000010

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001994

Description

VGPUVCORE_ANA_CON5

VGPUVCORE Control Register 5

00000090

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001996

Description

VGPUVCORE_ANA_CON6

VGPUVCORE Control Register 6

00000621

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001998

Description

VGPUVCORE_ANA_CON7

VGPUVCORE Control Register 7

00005511

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 723 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

0000199A

Description

VGPUVCORE_ANA_CON8

VGPUVCORE Control Register 8

0000FF00

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000199C

Description

VGPUVCORE_ANA_CON9

VGPUVCORE Control Register 9

00004000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000199E

Description

VGPUVCORE_ANA_CON10

VGPUVCORE Control Register 10

00000082

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 724 of 1067

MT6359 PMIC Datasheet Confidential A 000019A0

VGPUVCORE_ANA_CON11

VGPUVCORE Control Register 11

0000028B

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000019A2

Description

VGPUVCORE_ANA_CON12

VGPUVCORE Control Register 12

00003322

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

20

19

18

17

16

4

3

2

1

0

000019A4

Description

VGPUVCORE_ANA_CON13

VGPUVCORE Control Register 13

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

Bit

15

14

13

12

11

10

9

8

7

Name Type Reset Bit(s) 6 5

22

6 5 RG_VC ORE_N RG_VC ONAU ORE_F DIBLE_ CCM EN RW RW 0

Name RG_VCORE_NONAUDIBLE_EN RG_VCORE_FCCM

MediaTek Proprietary and Confidential.

21

0000FF00

0

Description Enables PFM frequency > 25 kHz 1'b0: Auto-mode (default) 1'b1: Force PWM

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 725 of 1067

MT6359 PMIC Datasheet Confidential A 000019A6

VGPUVCORE_ANA_CON14

VGPUVCORE Control Register 14

00001000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000019A8

Description

VGPUVCORE_ANA_CON15

VGPUVCORE Control Register 15

00000082

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000019AA

Description

VGPUVCORE_ANA_CON16

VGPUVCORE Control Register 16

00000006

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000019AC

Description

VPROC1_ANA_CON0

VPROC1 Control Register 0

00000C86

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 726 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

000019AE

Description

VPROC1_ANA_CON1

VPROC1 Control Register 1

000019C4

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000019B0

Description

VPROC1_ANA_CON2

VPROC1 Control Register 2

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

18

17

000019B2

Description

VPROC1_ANA_CON3

VPROC1 Control Register 3

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

Name

Type Reset Bit(s) 2 1

2 1 RG_VP ROC1_ RG_VP NONA ROC1_ UDIBLE FCCM _EN RW RW 0

Name RG_VPROC1_NONAUDIBLE_EN RG_VPROC1_FCCM

MediaTek Proprietary and Confidential.

16

0

0

Description Enables PFM frequency > 25 kHz 1'b0: Auto-mode (default) 1'b1: Force PWM

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 727 of 1067

MT6359 PMIC Datasheet Confidential A 000019B4

VPROC1_ANA_CON4

VPROC1 Control Register 4

000000FF

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000019B6

Description

VPROC1_ANA_CON5

VPROC1 Control Register 5

00000014

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000019B8

Description

BUCK_ANA0_ELR_NUM

BUCK_ANA0 Number of ELR Register

00000026

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000019BA

Description

SMPS_ELR_0

SMPS ELR 0 Register

0000888B

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 728 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

000019BC

Description

SMPS_ELR_1

SMPS ELR 1 Register

0000888B

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000019BE

Description

SMPS_ELR_2

SMPS ELR 2 Register

00008693

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000019C0

Description

SMPS_ELR_3

SMPS ELR 3 Register

00000008

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 729 of 1067

MT6359 PMIC Datasheet Confidential A 000019C2

SMPS_ELR_4

SMPS ELR 4 Register

00000008

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000019C4

Description

SMPS_ELR_5

SMPS ELR 5 Register

00000008

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000019C6

Description

SMPS_ELR_6

SMPS ELR 6 Register

00000008

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000019C8

Description

SMPS_ELR_7

SMPS ELR 7 Register

00000008

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 730 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

000019CA

Description

SMPS_ELR_8

SMPS ELR 8 Register

00000008

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000019CC

Description

SMPS_ELR_9

SMPS ELR 9 Register

00000008

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000019CE

Description

SMPS_ELR_10

SMPS ELR 10 Register

00008693

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 731 of 1067

MT6359 PMIC Datasheet Confidential A 000019D0

SMPS_ELR_11

SMPS ELR 11 Register

00000008

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000019D2

Description

SMPS_ELR_12

SMPS ELR 12 Register

00000008

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000019D4

Description

SMPS_ELR_13

SMPS ELR 13 Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000019D6

Description

SMPS_ELR_14

SMPS ELR 14 Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 732 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

000019D8

Description

SMPS_ELR_15

SMPS ELR 15 Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000019DA

Description

SMPS_ELR_16

SMPS ELR 16 Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000019DC

Description

SMPS_ELR_17

SMPS ELR 17 Register

00000820

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 733 of 1067

MT6359 PMIC Datasheet Confidential A 000019DE

SMPS_ELR_18

SMPS ELR 18 Register

00008120

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001A00

Description

BUCK_ANA1_DSN_ID

BUCK_ANA1 Design ID Register

00000034

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001A02

Description

BUCK_ANA1_DSN_REV0

BUCK_ANA1 Design Revision Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001A04

Description

BUCK_ANA1_DSN_DBI

BUCK_ANA1 Design Bank Information Register

00004600

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 734 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001A06

Description

BUCK_ANA1_DSN_FPI

BUCK_ANA1 Design Extra Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001A08

Description

VPROC2_ANA_CON0

VPROC2 Control Register 0

00000C86

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001A0A

Description

VPROC2_ANA_CON1

VPROC2 Control Register 1

000019C4

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 735 of 1067

MT6359 PMIC Datasheet Confidential A 00001A0C

VPROC2_ANA_CON2

VPROC2 Control Register 2

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

18

17

00001A0E

Description

VPROC2_ANA_CON3

VPROC2 Control Register 3

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

Name

Type Reset Bit(s) 2 1

Name RG_VPROC2_NONAUDIBLE_EN RG_VPROC2_FCCM

00001A10

2 1 RG_VP ROC2_ RG_VP NONA ROC2_ UDIBLE FCCM _EN RW RW 0

0

16

0

Description Enables PFM frequency > 25 kHz 1'b0: Auto-mode (default) 1'b1: Force PWM

VPROC2_ANA_CON4

VPROC2 Control Register 4

000000FF

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 736 of 1067

MT6359 PMIC Datasheet Confidential A 00001A12

VPROC2_ANA_CON5

VPROC2 Control Register 5

00000014

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001A14

Description

VMODEM_ANA_CON0

VMODEM Control Register 0

00000C86

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001A16

Description

VMODEM_ANA_CON1

VMODEM Control Register 1

000019C4

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001A18

Description

VMODEM_ANA_CON2

VMODEM Control Register 2

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 737 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001A1A

Description

VMODEM_ANA_CON3

VMODEM Control Register 3

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

Name Type Reset Bit(s) 2 1

Name RG_VMODEM_NONAUDIBLE_EN RG_VMODEM_FCCM

00001A1C

18

17

2 1 RG_VM ODEM_ RG_VM NONA ODEM_ UDIBLE FCCM _EN RW RW 0

0

16

0

Description Enables PFM frequency > 25 kHz 1'b0: Auto-mode (default) 1'b1: Force PWM

VMODEM_ANA_CON4

VMODEM Control Register 4

000000FF

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001A1E

Description

VMODEM_ANA_CON5

VMODEM Control Register 5

00000014

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 738 of 1067

MT6359 PMIC Datasheet Confidential A 00001A20

VPU_ANA_CON0

VPU Control Register 0

00000C86

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001A22

Description

VPU_ANA_CON1

VPU Control Register 1

000019A2

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001A24

Description

VPU_ANA_CON2

VPU Control Register 2

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

18

17

00001A26

Description

VPU_ANA_CON3

VPU Control Register 3

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

Name Type Reset MediaTek Proprietary and Confidential.

2 1 RG_VP RG_VP U_NON U_FCC AUDIBL M E_EN RW RW 0

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

16

0

0

Page 739 of 1067

t)

MT6359 PMIC Datasheet Confidential A Bit(s) 2 1

Name RG_VPU_NONAUDIBLE_EN RG_VPU_FCCM

00001A28

Description Enables PFM frequency > 25 kHz 1'b0: Auto-mode (default) 1'b1: Force PWM

VPU_ANA_CON4

VPU Control Register 4

000000FF

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001A2A

Description

VPU_ANA_CON5

VPU Control Register 5

00000014

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001A2C

Description

VS1_ANA_CON0

VS1 Control Register 0

00005044

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3 RG_VS 1_FPW M RW

2

1

0

Name Type Reset Bit(s) 3

0

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 740 of 1067

MT6359 PMIC Datasheet Confidential A 00001A2E

VS1_ANA_CON1

VS1 Control Register 1

00001820

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001A30

Description

VS1_ANA_CON2

VS1 Control Register 2

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001A32

Description

VS1_ANA_CON3

VS1 Control Register 3

00000150

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1 RG_VS 1_NON AUDIBL E_EN RW

0

Name Type Reset Bit(s) 1

0

Name RG_VS1_NONAUDIBLE_EN

MediaTek Proprietary and Confidential.

Description Enables PFM frequency > 25 kHz

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 741 of 1067

MT6359 PMIC Datasheet Confidential A 00001A34

VS2_ANA_CON0

VS2 Control Register 0

00005044

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3 RG_VS 2_FPW M RW

2

1

0

Name Type Reset Bit(s) 3

0

Name RG_VS2_FPWM

00001A36

Description 1'b0: Auto-mode (default) 1'b1: Force PWM

VS2_ANA_CON1

VS2 Control Register 1

00001820

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001A38

Description

VS2_ANA_CON2

VS2 Control Register 2

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 742 of 1067

MT6359 PMIC Datasheet Confidential A 00001A3A

VS2_ANA_CON3

VS2 Control Register 3

00000150

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1 RG_VS 2_NON AUDIBL E_EN RW

0

Name Type Reset Bit(s) 1

0

Name RG_VS2_NONAUDIBLE_EN

00001A3C

Description Enables PFM frequency > 25 kHz

VPA_ANA_CON0

VPA Control Register 0

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001A3E

Description

VPA_ANA_CON1

VPA Control Register 1

00000094

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 743 of 1067

MT6359 PMIC Datasheet Confidential A 00001A40

VPA_ANA_CON2

VPA Control Register 2

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001A42

Description

VPA_ANA_CON3

VPA Control Register 3

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001A44

Description

VPA_ANA_CON4

VPA Control Register 4

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001A46

Description

BUCK_ANA1_ELR_NUM

BUCK_ANA1 Number of ELR Register

00000020

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 744 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001A48

Description

VPROC2_ELR_0

VPROC2 ELR 0 Register

00008693

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001A4A

Description

VPROC2_ELR_1

VPROC2 ELR 1 Register

00000008

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001A4C

Description

VPROC2_ELR_2

VPROC2 ELR 2 Register

00000008

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 745 of 1067

MT6359 PMIC Datasheet Confidential A 00001A4E

VPROC2_ELR_3

VPROC2 ELR 3 Register

00008693

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001A50

Description

VPROC2_ELR_4

VPROC2 ELR 4 Register

00000008

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001A52

Description

VPROC2_ELR_5

VPROC2 ELR 5 Register

00000008

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001A54

Description

VPROC2_ELR_6

VPROC2 ELR 6 Register

00008693

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 746 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001A56

Description

VPROC2_ELR_7

VPROC2 ELR 7 Register

00000008

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001A58

Description

VPROC2_ELR_8

VPROC2 ELR 8 Register

00000008

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001A5A

Description

VPROC2_ELR_9

VPROC2 ELR 9 Register

00009998

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 747 of 1067

MT6359 PMIC Datasheet Confidential A 00001A5C

VPROC2_ELR_10

VPROC2 ELR 10 Register

00000088

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001A5E

Description

VPROC2_ELR_11

VPROC2 ELR 11 Register

000099D8

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001A60

Description

VPROC2_ELR_12

VPROC2 ELR 12 Register

00000088

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001A62

Description

VPROC2_ELR_13

VPROC2 ELR 13 Register

00000820

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 748 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001A64

Description

VPROC2_ELR_14

VPROC2 ELR 14 Register

00000820

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001A66

Description

VPROC2_ELR_15

VPROC2 ELR 15 Register

00000020

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001B00

Description

LDO_TOP_ID

LDO_TOP Design ID Register

0000E000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 749 of 1067

MT6359 PMIC Datasheet Confidential A 00001B02

LDO_TOP_REV0

LDO_TOP Design Revision Register 0

00001000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001B04

Description

LDO_TOP_DBI

LDO_TOP Design Bank Information Register

00003E00

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001B06

Description

LDO_TOP_DXI

LDO_TOP Design Extra Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001B08

Description

LDO_TPM0

LDO_TOP Parameter 0

0000000C

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 750 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001B0A

Description

LDO_TPM1

LDO_TOP Parameter 1

00000250

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001B0C

Description

LDO_TOP_CKPDN_CON0

LDO_TOP_CKPDN Control Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001B0E

Description

TOP_TOP_CKHWEN_CON0

LDO_TOP_CKHWEN Control Register 0

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 751 of 1067

errupt

MT6359 PMIC Datasheet Confidential A 00001B10

LDO_TOP_CLK_DCM_CON0

LDO DCM Control Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001B12

Description

LDO_TOP_CLK_VSRAM_CON0 LDO VSRAM Clock Gating Control Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

20

19

18

17

00001B14 Bit Name Type Reset

Description

LDO_TOP_INT_CON0 31

30

29

28

LDO_TOP INT Control Register 0 27

26

25

24

23

22

21

00000000 16

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT _EN_V _EN_VI _EN_V _EN_V _EN_V _EN_V _EN_V _EN_V _EN_V _EN_V _EN_V _EN_V _EN_V _EN_V _EN_V _EN_V Name SRAM_ O18_O AUD18 AUX18 A12_O CAMIO A09_O CN18_ CN13_ CN33_ CN33_ EFUSE_ RF12_ RF18_ XO22_ FE28_O PROC1 C _OC _OC C _OC C OC OC 2_OC 1_OC OC OC OC OC C _OC RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

Bit

Bit(s) 15

14

Name RG_INT_EN_VSRAM_PROC1_OC

RG_INT_EN_VIO18_OC

Description Enables VSRAM_PROC1_OC interrupt 0: Not issue interrupt 1: Issue interrupt Enables VIO18_OC interrupt 0: Not issue interrupt

13

12

RG_INT_EN_VAUX18_OC

MediaTek Proprietary and Confidential.

0: Not issue interrupt 1: Issue interrupt Enables VAUX18_OC interrupt 0: Not issue interrupt

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 752 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

11

RG_INT_EN_VA12_OC

10

RG_INT_EN_VCAMIO_OC

9

RG_INT_EN_VA09_OC

8

RG_INT_EN_VCN18_OC

7

RG_INT_EN_VCN13_OC

6

RG_INT_EN_VCN33_2_OC

5

RG_INT_EN_VCN33_1_OC

4

RG_INT_EN_VEFUSE_OC

3

RG_INT_EN_VRF12_OC

2

RG_INT_EN_VRF18_OC

1

RG_INT_EN_VXO22_OC

0

RG_INT_EN_VFE28_OC

00001B16

Description 1: Issue interrupt Enables VA12_OC interrupt 0: Not issue interrupt 1: Issue interrupt Enables VCAMIO_OC interrupt 0: Not issue interrupt 1: Issue interrupt Enables VA09_OC interrupt 0: Not issue interrupt 1: Issue interrupt Enables VCN18_OC interrupt 0: Not issue interrupt 1: Issue interrupt Enables VCN13_OC interrupt 0: Not issue interrupt 1: Issue interrupt Enables VCN33_2_OC interrupt 0: Not issue interrupt 1: Issue interrupt Enables VCN33_1_OC interrupt 0: Not issue interrupt 1: Issue interrupt Enables VEFUSE_OC interrupt 0: Not issue interrupt 1: Issue interrupt Enables VRF12_OC interrupt 0: Not issue interrupt 1: Issue interrupt Enables VRF18_OC interrupt 0: Not issue interrupt 1: Issue interrupt Enables VXO22_OC interrupt 0: Not issue interrupt 1: Issue interrupt Enables VFE28_OC interrupt 0: Not issue interrupt 1: Issue interrupt

LDO_TOP_INT_CON0_SET

LDO_TOP INT Control Register 0 SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 753 of 1067

MT6359 PMIC Datasheet Confidential A 00001B18

LDO_TOP_INT_CON0_CLR

LDO_TOP INT Control Register 0 CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

18

17

00001B1A

Description

LDO_TOP_INT_CON1

LDO_TOP INT Control Register 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

0

0

0

0

0

0

0

0

0

0

0

Name

Type Reset

2 1 0 RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT _EN_V _EN_V _EN_V _EN_V _EN_V _EN_VI _EN_V _EN_V _EN_V _EN_V _EN_V _EN_V _EN_V _EN_VI SRAM_ SRAM_ SRAM_ UFS_O M18_O O28_O BIF28_ BBCK_ RFCK_ USB_O SIM2_ SIM1_ EMC_O BR_OC MD_O OTHER PROC2 C C C OC OC OC C OC OC C C S_OC _OC RW RW RW RW RW RW RW RW RW RW RW RW RW RW

Bit(s) 13

Name RG_INT_EN_VUFS_OC

12

RG_INT_EN_VM18_OC

11

RG_INT_EN_VIO28_OC

10

RG_INT_EN_VIBR_OC

9

RG_INT_EN_VBIF28_OC

8

RG_INT_EN_VBBCK_OC

7

RG_INT_EN_VRFCK_OC

6

RG_INT_EN_VUSB_OC

5

RG_INT_EN_VSIM2_OC

MediaTek Proprietary and Confidential.

16

0

0

0

Description Enables VUFS_OC interrupt 0: Not issue interrupt 1: Issue interrupt Enables VM18_OC interrupt 0: Not issue interrupt 1: Issue interrupt Enables VIO28_OC interrupt 0: Not issue interrupt 1: Issue interrupt Enables VIBR_OC interrupt 0: Not issue interrupt 1: Issue interrupt Enables VBIF28_OC interrupt 0: Not issue interrupt 1: Issue interrupt Enables VBBCK_OC interrupt 0: Not issue interrupt 1: Issue interrupt Enables VRFCK_OC interrupt 0: Not issue interrupt 1: Issue interrupt Enables VUSB_OC interrupt 0: Not issue interrupt 1: Issue interrupt Enables VSIM2_OC interrupt 0: Not issue interrupt

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 754 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

4

RG_INT_EN_VSIM1_OC

3

RG_INT_EN_VEMC_OC

2

RG_INT_EN_VSRAM_MD_OC

1

RG_INT_EN_VSRAM_OTHERS_OC

0

RG_INT_EN_VSRAM_PROC2_OC

00001B1C Bit Name Type Reset

Description 1: Issue interrupt Enables VSIM1_OC interrupt 0: Not issue interrupt 1: Issue interrupt Enables VEMC_OC interrupt 0: Not issue interrupt 1: Issue interrupt Enables VSRAM_MD_OC interrupt 0: Not issue interrupt 1: Issue interrupt Enables VSRAM_OTHERS_OC interrupt 0: Not issue interrupt 1: Issue interrupt Enables VSRAM_PROC2_OC interrupt 0: Not issue interrupt 1: Issue interrupt

LDO_TOP_INT_MASK_CON0 LDO_TOP INT Mask Control Register 0 31

30

29

28

27

26

25

24

23

22

21

20

00000000 19

18

17

16

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RG_INT RG_INT RG_INT _MASK RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT _MASK _MASK _VSRA _MASK _MASK _MASK _MASK _MASK _MASK _MASK _MASK _MASK _MASK _MASK _MASK _MASK _VCN3 _VCN3 Name M_PR _VIO18 _VAUD _VAUX _VA12 _VCAM _VA09 _VCN1 _VCN1 _VEFUS _VRF12 _VRF18 _VXO2 _VFE28 3_2_O 3_1_O OC1_O _OC 18_OC 18_OC _OC IO_OC _OC 8_OC 3_OC E_OC _OC _OC 2_OC _OC C C C RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

Bit

Bit(s) 15

Name RG_INT_MASK_VSRAM_PROC1_OC

14

RG_INT_MASK_VIO18_OC

13

RG_INT_MASK_VAUD18_OC

12

RG_INT_MASK_VAUX18_OC

11

RG_INT_MASK_VA12_OC

10

RG_INT_MASK_VCAMIO_OC

9

RG_INT_MASK_VA09_OC

MediaTek Proprietary and Confidential.

Description Masks VSRAM_PROC1_OC interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks VIO18_OC interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks VAUD18_OC interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks VAUX18_OC interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks VA12_OC interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks VCAMIO_OC interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks VA09_OC interrupt status 1'b0: Unmask interrupt status

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 755 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

8

RG_INT_MASK_VCN18_OC

7

RG_INT_MASK_VCN13_OC

6

RG_INT_MASK_VCN33_2_OC

5

RG_INT_MASK_VCN33_1_OC

4

RG_INT_MASK_VEFUSE_OC

3

RG_INT_MASK_VRF12_OC

2

RG_INT_MASK_VRF18_OC

1

RG_INT_MASK_VXO22_OC

0

RG_INT_MASK_VFE28_OC

00001B1E

Description 1'b1: Mask interrupt status Masks VCN18_OC interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks VCN13_OC interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks VCN33_2_OC interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks VCN33_1_OC interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks VEFUSE_OC interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks VRF12_OC interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks VRF18_OC interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks VXO22_OC interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks VFE28_OC interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status

LDO_TOP_INT_MASK_CON0_ LDO_TOP INT Mask Control Register 0 SET SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 756 of 1067

MT6359 PMIC Datasheet Confidential A 00001B20

LDO_TOP_INT_MASK_CON0_ LDO_TOP INT Mask Control Register 0 CLR CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

17

00001B22

Description

LDO_TOP_INT_MASK_CON1 LDO_TOP INT Mask Control Register 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

0

0

0

0

0

0

0

0

0

0

0

0

Name

Type Reset

1 0 RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT _MASK _MASK _MASK _MASK _MASK _MASK _MASK _MASK _MASK _MASK _MASK _MASK _MASK _MASK _VSRA _VSRA _VSRA _VUFS_ _VM18 _VIO28 _VIBR_ _VBIF2 _VBBC _VRFCK _VUSB _VSIM _VSIM _VEMC M_OTH M_PR M_MD OC _OC _OC OC 8_OC K_OC _OC _OC 2_OC 1_OC _OC ERS_O OC2_O _OC C C RW RW RW RW RW RW RW RW RW RW RW RW RW RW

Bit(s) 13

Name RG_INT_MASK_VUFS_OC

12

RG_INT_MASK_VM18_OC

11

RG_INT_MASK_VIO28_OC

10

RG_INT_MASK_VIBR_OC

9

RG_INT_MASK_VBIF28_OC

8

RG_INT_MASK_VBBCK_OC

7

RG_INT_MASK_VRFCK_OC

6

RG_INT_MASK_VUSB_OC

MediaTek Proprietary and Confidential.

16

0

0

Description Masks VUFS_OC interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks VM18_OC interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks VIO28_OC interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks VIBR_OC interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks VBIF28_OC interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks VBBCK_OC interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks VRFCK_OC interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks VUSB_OC interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 757 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 5

Name RG_INT_MASK_VSIM2_OC

4

RG_INT_MASK_VSIM1_OC

3

RG_INT_MASK_VEMC_OC

2

RG_INT_MASK_VSRAM_MD_OC

1

RG_INT_MASK_VSRAM_OTHERS_OC

0

RG_INT_MASK_VSRAM_PROC2_OC

00001B24

Description Masks VSIM2_OC interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks VSIM1_OC interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks VEMC_OC interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks VSRAM_MD_OC interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks VSRAM_OTHERS_OC interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks VSRAM_PROC2_OC interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status

LDO_TOP_INT_MASK_CON1_ LDO_TOP INT Mask Control Register 1 SET SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001B26

Description

LDO_TOP_INT_MASK_CON1_ LDO_TOP INT Mask Control Register 1 CLR CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 758 of 1067

MT6359 PMIC Datasheet Confidential A 00001B28 Bit Name Type Reset

LDO_TOP_INT_STATUS0 31

30

29

28

27

LDO_TOP INT Status Register 0 26

25

24

23

22

21

00000000 20

19

18

17

16

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT _STAT RG_INT RG_INT RG_INT RG_INT RG_INT _STAT _STAT _STAT _STAT _STAT _STAT _STAT _STAT _STAT _STAT US_VS _STAT _STAT _STAT _STAT _STAT US_VA US_VA US_VC US_VC US_VC US_VC US_VC US_VEF US_VX US_VF Name RAM_P US_VIO US_VA US_VA US_VR US_VR UD18_ UX18_ AMIO_ N18_O N13_O N33_2_ N33_1_ USE_O O22_O E28_O ROC1_ 18_OC 12_OC 09_OC F12_OC F18_OC OC OC OC C C OC OC C C C OC W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

Bit

Bit(s) 15

Name RG_INT_STATUS_VSRAM_PROC1_OC

14

RG_INT_STATUS_VIO18_OC

13

RG_INT_STATUS_VAUD18_OC

12

RG_INT_STATUS_VAUX18_OC

11

RG_INT_STATUS_VA12_OC

10

RG_INT_STATUS_VCAMIO_OC

9

RG_INT_STATUS_VA09_OC

8

RG_INT_STATUS_VCN18_OC

7

RG_INT_STATUS_VCN13_OC

6

RG_INT_STATUS_VCN33_2_OC

5

RG_INT_STATUS_VCN33_1_OC

4

RG_INT_STATUS_VEFUSE_OC

3

RG_INT_STATUS_VRF12_OC

2

RG_INT_STATUS_VRF18_OC

MediaTek Proprietary and Confidential.

Description VSRAM_PROC1_OC interrupt status 0: No interrupt issued 1: Interrupt issued VIO18_OC interrupt status 0: No interrupt issued 1: Interrupt issued VAUD18_OC interrupt status 0: No interrupt issued 1: Interrupt issued VAUX18_OC interrupt status 0: No interrupt issued 1: Interrupt issued VA12_OC interrupt status 0: No interrupt issued 1: Interrupt issued VCAMIO_OC interrupt status 0: No interrupt issued 1: Interrupt issued VA09_OC interrupt status 0: No interrupt issued 1: Interrupt issued VCN18_OC interrupt status 0: No interrupt issued 1: Interrupt issued VCN13_OC interrupt status 0: No interrupt issued 1: Interrupt issued VCN33_2_OC interrupt status 0: No interrupt issued 1: Interrupt issued VCN33_1_OC interrupt status 0: No interrupt issued 1: Interrupt issued VEFUSE_OC interrupt status 0: No interrupt issued 1: Interrupt issued VRF12_OC interrupt status 0: No interrupt issued 1: Interrupt issued VRF18_OC interrupt status

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 759 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

1

RG_INT_STATUS_VXO22_OC

0

RG_INT_STATUS_VFE28_OC

00001B2A

Description 0: No interrupt issued 1: Interrupt issued VXO22_OC interrupt status 0: No interrupt issued 1: Interrupt issued VFE28_OC interrupt status 0: No interrupt issued 1: Interrupt issued

LDO_TOP_INT_STATUS1

LDO_TOP INT Status Register 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

0

0

0

0

0

0

0

0

0

0

0

Name

Type Reset

17

16

2 1 0 RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT _STAT _STAT _STAT _STAT _STAT _STAT _STAT _STAT _STAT _STAT _STAT _STAT _STAT _STAT US_VS US_VS US_VS US_VB US_VR US_VU US_VM US_VIO US_VIB US_VBI US_VU US_VSI US_VSI US_VE RAM_ RAM_ RAM_P BCK_O FCK_O FS_OC 18_OC 28_OC R_OC F28_OC SB_OC M2_OC M1_OC MC_OC MD_O OTHER ROC2_ C C C S_OC OC W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C

Bit(s) 13

Name RG_INT_STATUS_VUFS_OC

12

RG_INT_STATUS_VM18_OC

11

RG_INT_STATUS_VIO28_OC

10

RG_INT_STATUS_VIBR_OC

9

RG_INT_STATUS_VBIF28_OC

8

RG_INT_STATUS_VBBCK_OC

7

RG_INT_STATUS_VRFCK_OC

6

RG_INT_STATUS_VUSB_OC

5

RG_INT_STATUS_VSIM2_OC

4

RG_INT_STATUS_VSIM1_OC

MediaTek Proprietary and Confidential.

18

0

0

0

Description VUFS_OC interrupt status 0: No interrupt issued 1: Interrupt issued VM18_OC interrupt status 0: No interrupt issued 1: Interrupt issued VIO28_OC interrupt status 0: No interrupt issued 1: Interrupt issued VIBR_OC interrupt status 0: No interrupt issued 1: Interrupt issued VBIF28_OC interrupt status 0: No interrupt issued 1: Interrupt issued VBBCK_OC interrupt status 0: No interrupt issued 1: Interrupt issued VRFCK_OC interrupt status 0: No interrupt issued 1: Interrupt issued VUSB_OC interrupt status 0: No interrupt issued 1: Interrupt issued VSIM2_OC interrupt status 0: No interrupt issued 1: Interrupt issued VSIM1_OC interrupt status

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 760 of 1067

pt status

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

3

RG_INT_STATUS_VEMC_OC

2

RG_INT_STATUS_VSRAM_MD_OC

1

RG_INT_STATUS_VSRAM_OTHERS_OC

0

RG_INT_STATUS_VSRAM_PROC2_OC

00001B2C Bit Name Type Reset

Description 0: No interrupt issued 1: Interrupt issued VEMC_OC interrupt status 0: No interrupt issued 1: Interrupt issued VSRAM_MD_OC interrupt status 0: No interrupt issued 1: Interrupt issued VSRAM_OTHERS_OC interrupt status 0: No interrupt issued 1: Interrupt issued VSRAM_PROC2_OC interrupt status 0: No interrupt issued 1: Interrupt issued

LDO_TOP_INT_RAW_STATUS LDO_TOP INT Raw Status Register 0 0 31

30

29

28

27

26

25

24

23

22

21

00000000 20

19

18

17

16

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RG_INT RG_INT RG_INT _RAW_ RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT _RAW_ _RAW_ STATU _RAW_ _RAW_ _RAW_ _RAW_ _RAW_ _RAW_ _RAW_ _RAW_ _RAW_ _RAW_ _RAW_ _RAW_ _RAW_ STATUS STATUS STATUS STATUS STATUS STATUS STATU Name S_VSR STATUS STATUS STATUS STATUS STATUS STATUS STATUS STATUS _VCN3 _VCN3 AM_PR _VIO18 _VAUD _VAUX _VA12 _VCAM _VA09 _VCN1 _VCN1 _VEFUS _VRF12 _VRF18 _VXO2 S_VFE2 3_2_O 3_1_O OC1_O _OC 18_OC 18_OC _OC IO_OC _OC 8_OC 3_OC E_OC _OC _OC 2_OC 8_OC C C C RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

Bit

Bit(s) 15

14

13

12

11

Name Description RG_INT_RAW_STATUS_VSRAM_PROC1_ VSRAM_PROC1_OC raw interrupt status OC 0: No interrupt issued 1: Interrupt issued RG_INT_RAW_STATUS_VIO18_OC VIO18_OC raw interrupt status 0: No interrupt issued 1: Interrupt issued RG_INT_RAW_STATUS_VAUD18_OC VAUD18_OC raw interrupt status 0: No interrupt issued 1: Interrupt issued RG_INT_RAW_STATUS_VAUX18_OC VAUX18_OC raw interrupt status 0: No interrupt issued 1: Interrupt issued RG_INT_RAW_STATUS_VA12_OC VA12_OC raw interrupt status 0: No interrupt issued

10

9

RG_INT_RAW_STATUS_VA09_OC

MediaTek Proprietary and Confidential.

0: No interrupt issued 1: Interrupt issued VA09_OC raw interrupt status 0: No interrupt issued

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 761 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

8

RG_INT_RAW_STATUS_VCN18_OC

7

RG_INT_RAW_STATUS_VCN13_OC

6

RG_INT_RAW_STATUS_VCN33_2_OC

5

RG_INT_RAW_STATUS_VCN33_1_OC

4

RG_INT_RAW_STATUS_VEFUSE_OC

3

RG_INT_RAW_STATUS_VRF12_OC

2

RG_INT_RAW_STATUS_VRF18_OC

1

RG_INT_RAW_STATUS_VXO22_OC

0

RG_INT_RAW_STATUS_VFE28_OC

00001B2E

Description 1: Interrupt issued VCN18_OC raw interrupt status 0: No interrupt issued 1: Interrupt issued VCN13_OC raw interrupt status 0: No interrupt issued 1: Interrupt issued VCN33_2_OC raw interrupt status 0: No interrupt issued 1: Interrupt issued VCN33_1_OC raw interrupt status 0: No interrupt issued 1: Interrupt issued VEFUSE_OC raw interrupt status 0: No interrupt issued 1: Interrupt issued VRF12_OC raw interrupt status 0: No interrupt issued 1: Interrupt issued VRF18_OC raw interrupt status 0: No interrupt issued 1: Interrupt issued VXO22_OC raw interrupt status 0: No interrupt issued 1: Interrupt issued VFE28_OC raw interrupt status 0: No interrupt issued 1: Interrupt issued

LDO_TOP_INT_RAW_STATUS LDO_TOP INT Raw Status Register 1 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

0

0

0

0

0

0

0

0

0

0

0

0

Name

Type Reset

16

1 0 RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT RG_INT _RAW_ _RAW_ _RAW_ _RAW_ _RAW_ _RAW_ _RAW_ _RAW_ _RAW_ _RAW_ _RAW_ _RAW_ _RAW_ _RAW_ STATUS STATU STATUS STATUS STATUS STATUS STATUS STATUS STATUS STATUS STATUS STATUS STATUS STATUS _VSRA S_VSR _VSRA _VUFS_ _VM18 _VIO28 _VIBR_ _VBIF2 _VBBC _VRFCK _VUSB _VSIM _VSIM _VEMC M_OTH AM_PR M_MD OC _OC _OC OC 8_OC K_OC _OC _OC 2_OC 1_OC _OC ERS_O OC2_O _OC C C RO RO RO RO RO RO RO RO RO RO RO RO RO RO

Bit(s) 13

Name RG_INT_RAW_STATUS_VUFS_OC

12

RG_INT_RAW_STATUS_VM18_OC

MediaTek Proprietary and Confidential.

17

0

0

Description VUFS_OC raw interrupt status 0: No interrupt issued 1: Interrupt issued VM18_OC raw interrupt status 0: No interrupt issued 1: Interrupt issued

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 762 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 11

Name RG_INT_RAW_STATUS_VIO28_OC

10

RG_INT_RAW_STATUS_VIBR_OC

9

RG_INT_RAW_STATUS_VBIF28_OC

8

RG_INT_RAW_STATUS_VBBCK_OC

7

RG_INT_RAW_STATUS_VRFCK_OC

6

RG_INT_RAW_STATUS_VUSB_OC

5

RG_INT_RAW_STATUS_VSIM2_OC

4

RG_INT_RAW_STATUS_VSIM1_OC

3

RG_INT_RAW_STATUS_VEMC_OC

2

RG_INT_RAW_STATUS_VSRAM_MD_ OC

1

RG_INT_RAW_STATUS_VSRAM_OTHE RS_OC

0

RG_INT_RAW_STATUS_VSRAM_PROC 2_OC

00001B30

Description VIO28_OC raw interrupt status 0: No interrupt issued 1: Interrupt issued VIBR_OC raw interrupt status 0: No interrupt issued 1: Interrupt issued VBIF28_OC raw interrupt status 0: No interrupt issued 1: Interrupt issued VBBCK_OC raw interrupt status 0: No interrupt issued 1: Interrupt issued VRFCK_OC raw interrupt status 0: No interrupt issued 1: Interrupt issued VUSB_OC raw interrupt status 0: No interrupt issued 1: Interrupt issued VSIM2_OC raw interrupt status 0: No interrupt issued 1: Interrupt issued VSIM1_OC raw interrupt status 0: No interrupt issued 1: Interrupt issued VEMC_OC raw interrupt status 0: No interrupt issued 1: Interrupt issued VSRAM_MD_OC raw interrupt status 0: No interrupt issued 1: Interrupt issued VSRAM_OTHERS_O C raw interrupt status 0: No interrupt issued 1: Interrupt issued VSRAM_PROC2_OC raw interrupt status 0: No interrupt issued 1: Interrupt issued

LDO_TEST_CON0

LDO Test Control 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 763 of 1067

MT6359 PMIC Datasheet Confidential A 00001B32

LDO_TOP_CON

LDO Top Control Register

00000F00

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001B34

Description

VRTC28_CON

VRTC28 Control Register 0

00008002

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001B36

Description

VAUX18_ACK

VAUX18 acktime Register 0

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001B38

Description

VBIF28_ACK

VBIF28 acktime Register 0

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 764 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001B3A

Description

VOW_DVS_CON

VOW dvs Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001B3C

Description

VXO22_CON

VXO22 Test Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001B3E

Description

LDO_TOP_ELR_NUM

LDO_TOP Number of ELR Register

00000010

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 765 of 1067

MT6359 PMIC Datasheet Confidential A 00001B40

LDO_VRFCK_ELR

LDO VRFCK eFuse Bit0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001B42

Description

LDO_VSRAM_VLIMIT_ELR

LDO VSRAM_VLIMIT eFuse Bit0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001B44

Description

LDO_VSRAM_PROC1_ELR

LDO VSRAM_PROC1 eFuse Bit0

00000038

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s) 6:0

RG_LDO_VSRAM_PROC1_VOSEL RW 0

Name RG_LDO_VSRAM_PROC1_VOSEL

00001B46

1

1

1

0

0

0

Description Selects VOUT in normal mode (SW mode) Vout = 0.5V + 6.25 mV*code

LDO_VSRAM_PROC2_ELR

LDO VSRAM_PROC2 eFuse Bit0

00000038

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

RG_LDO_VSRAM_PROC2_VOSEL RW 0

1

1

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

1

0

0

0

Page 766 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 6:0

Name RG_LDO_VSRAM_PROC2_VOSEL

00001B48

Description Selects VOUT in normal mode (SW mode) Vout = 0.5V + 6.25 mV*code

LDO_VSRAM_OTHERS_ELR

LDO VSRAM_OTHERS eFuse Bit0

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

Bit(s) 6:0

00000038

21

20

19

18

17

16

5

4

3

2

1

0

RG_LDO_VSRAM_OTHERS_VOSEL RW 0

Name RG_LDO_VSRAM_OTHERS_VOSEL

00001B4A

1

1

1

0

0

0

Description Selects VOUT in normal mode (SW mode) Vout = 0.5V + 6.25 mV*code

LDO_VSRAM_MD_ELR

LDO VSRAM_MD eFuse Bit0

00000038

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

Bit(s) 6:0

RG_LDO_VSRAM_MD_VOSEL RW 0

Name RG_LDO_VSRAM_MD_VOSEL

00001B4C

1

1

1

0

0

18

17

16

2

1

0

Description Selects VOUT in normal mode (SW mode) Vout = 0.5V + 6.25 mV*code

LDO_VEMC_ELR_0

LDO VEMC eFuse Bit0

0000000B

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

Bit(s) 3:0

RG_VEMC_VOSEL_0 RW 1

Name RG_VEMC_VOSEL_0

MediaTek Proprietary and Confidential.

0

1

1

Description Selects output voltage 4'b1000: 2.5V 4'b1001: 2.8V 4'b1010: 2.9V 4'b1011: 3.0V

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 767 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001B4E

Description 4'b1100: 3.1V 4'b1101: 3.3V

LDO_VEMC_ELR_1

LDO VEMC eFuse Bit3

00000008

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

Bit(s) 3:0

18

17

16

2

1

0

RG_VEMC_VOSEL_1 RW

Name RG_VEMC_VOSEL_1

00001B80

1

0

0

0

Description Selects output voltage 4'b1000: 2.5V 4'b1001: 2.8V 4'b1010: 2.9V 4'b1011: 3.0V 4'b1100: 3.1V 4'b1101: 3.3V

LDO_GNR0_DSN_ID

LDO_GNR0 Design ID Register

0000E100

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001B82

Description

LDO_GNR0_DSN_REV0

LDO_GNR0 Design Revision Register 0

00001000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 768 of 1067

MT6359 PMIC Datasheet Confidential A 00001B84

LDO_GNR0_DSN_DBI

LDO_GNR0 Design Bank Information Register

00000002

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001B86

Description

LDO_GNR0_DSN_DXI

LDO_GNR0 Design Extra Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

17

00001B88

Description

LDO_VFE28_CON0

LDO VFE28 Control 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

Name Type Reset

1 0 RG_LD RG_LD O_VFE O_VFE 28_LP 28_EN RW RW 0

Bit(s) 1

Name RG_LDO_VFE28_LP

0

RG_LDO_VFE28_EN

MediaTek Proprietary and Confidential.

16

0

Description SW enter low power mode Valid once RG_LDO_VFE28_SW_OP_EN = 1'b1, 1'b0: No LP 1'b1: LP SW enable control Valid once RG_LDO_VFE28_SW_OP_EN = 1'b1, 1'b0: Off 1'b1: On

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 769 of 1067

MT6359 PMIC Datasheet Confidential A 00001B8A

LDO_VFE28_CON1

LDO VFE28 Control 1

00009C01

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

Bit

15

14

13

12

11

10

9

8

7

6 RG_LD O_VFE 28_OC _TSEL RW

Name Type Reset Bit(s) 6

0

Name RG_LDO_VFE28_OC_TSEL

5

RG_LDO_VFE28_OC_MODE

4

RG_LDO_VFE28_OCFB_EN

2

RG_LDO_VFE28_ULP

1:0

LDO_VFE28_MON

5 4 RG_LD RG_LD O_VFE O_VFE 28_OC 28_OCF _MODE B_EN RW RW 0

30

29

28

27

26

25

24

23

22

Bit

15

14

13

12

11

10

9

8

7

6

Name Type Reset

21

DA_VFE28_L_STB

3

DA_VFE28_L_EN

MediaTek Proprietary and Confidential.

17

16

3

2

1

0

RG_LD RG_LDO_VFE2 O_VFE 8_STBTD 28_ULP RW

0

0

RW 0

1

20

19

18

17

16

5 4 3 2 1 0 DA_VF DA_VF DA_VF DA_VF DA_VF DA_VF E28_O E28_L_ E28_L_ E28_B_ E28_B_ E28_B_ CFB_EN STB EN LP STB EN RO RO RO RO RO RO 0

4

18

00000000

31

Name DA_VFE28_OCFB_EN

19

LDO VFE28 Monitor

Bit Name Type Reset

Bit(s) 5

20

Description Selects VFE28 OC debounce time 1'b0: 60 us 1'b1: 120 us Selects VFE28 OCFB/OC shutdown 1'b0: OCFB 1'b1: OC shutdown Enables VFE28 OCFB/OC shutdown function 1'b0: Disable 1'b1: Enable Selects VFE28 LP/ULP when entering low power mode 1'b0: No ULP 1'b1: ULP Selects VFE28 soft start time 2'b00: 120 us 2'b01: 240 us 2'b10: 480 us 2'b11: 960 us

RG_LDO_VFE28_STBTD

00001B8C

21

0

0

0

0

0

Description VFE28 OCFB status 1'b0: OCFB not activated 1'b1: OCFB activated VFE28 ULP soft-start status 1'b0: STB not ready 1'b1: STB ready VFE28 ULP enable status 1'b0: Disable

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 770 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

2

DA_VFE28_B_LP

1

DA_VFE28_B_STB

0

DA_VFE28_B_EN

00001B8E

Description 1'b1: Enable VFE28 low power mode status 1'b0: Normal mode 1'b1: Low power mode VFE28 NM soft start status 1'b0: STB not ready 1'b1: STB ready VFE28 NM enable status 1'b0: Disable 1'b1: Enable

LDO_VFE28_OP_EN

LDO VFE28 Operation Enable

00008000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

Name

Type Reset Bit(s) 2

Name RG_LDO_VFE28_HW2_OP_EN

1

RG_LDO_VFE28_HW1_OP_EN

0

RG_LDO_VFE28_HW0_OP_EN

00001B90

18

17

16

2 1 0 RG_LD RG_LD RG_LD O_VFE O_VFE O_VFE 28_HW 28_HW 28_HW 2_OP_E 1_OP_E 0_OP_ N N EN RW RW RW 0

0

0

Description hw_ctrl[2] OPERATION ENABLE HW1: SRCLKEN2/PMRC_EN[2] 1'b0: Disable 1'b1: Enable hw_ctrl[1] OPERATION ENABLE HW1: SRCLKEN1/PMRC_EN[1] 1'b0: Disable 1'b1: Enable hw_ctrl[0] OPERATION ENABLE HW0: SRCLKEN0/PMRC_EN[0] 1'b0: Disable 1'b1: Enable

LDO_VFE28_OP_EN_SET

LDO VFE28 Operation Enable SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 771 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001B92

Description

LDO_VFE28_OP_EN_CLR

LDO VFE28 Operation Enable CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

18

17

00001B94

Description

LDO_VFE28_OP_CFG

LDO VFE28 Operation Config

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

Name Type Reset

2 1 0 RG_LD RG_LD RG_LD O_VFE O_VFE O_VFE 28_HW 28_HW 28_HW 2_OP_ 1_OP_ 0_OP_ CFG CFG CFG RW RW RW 0

Bit(s) 2

Name RG_LDO_VFE28_HW2_OP_CFG

1

RG_LDO_VFE28_HW1_OP_CFG

0

RG_LDO_VFE28_HW0_OP_CFG

MediaTek Proprietary and Confidential.

16

0

0

Description hw_ctrl[2] OPERATION CONFIG HW1: SRCLKEN2/PMRC_EN[2] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low) hw_ctrl[1] OPERATION CONFIG HW1: SRCLKEN1/PMRC_EN[1] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low) hw_ctrl[0] OPERATION CONFIG HW0: SRCLKEN0/PMRC_EN[0] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low)

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 772 of 1067

MT6359 PMIC Datasheet Confidential A 00001B96

LDO_VFE28_OP_CFG_SET

LDO VFE28 Operation Config SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001B98

Description

LDO_VFE28_OP_CFG_CLR

LDO VFE28 Operation Config CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

17

00001B9A

Description

LDO_VXO22_CON0

LDO VXO22 Control 0

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

Name Type Reset

1 0 RG_LD RG_LD O_VXO O_VXO 22_LP 22_EN RW RW 0

Bit(s) 1

Name RG_LDO_VXO22_LP

0

RG_LDO_VXO22_EN

MediaTek Proprietary and Confidential.

16

1

Description SW enter low power mode Valid once RG_LDO_VXO22_SW_OP_EN = 1'b1. 1'b0: No LP 1'b1: LP SW enable control Valid once RG_LDO_VXO22_SW_OP_EN = 1'b1. 1'b0: Off 1'b1: On

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 773 of 1067

MT6359 PMIC Datasheet Confidential A 00001B9C

LDO_VXO22_CON1

LDO VXO22 Control 1

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

Bit

15

14

13

12

11

10

9

8

7

Name Type Reset Bit(s) 6

Name RG_LDO_VXO22_OC_TSEL

RG_LDO_VXO22_OC_MODE

4

RG_LDO_VXO22_OCFB_EN

2

RG_LDO_VXO22_ULP

LDO_VXO22_MON

0

30

29

28

27

26

25

24

23

22

Bit

15

14

13

12

11

10

9

8

7

6

Name Type Reset

21

DA_VXO22_L_STB

3

DA_VXO22_L_EN

MediaTek Proprietary and Confidential.

17

16

3

2

1

0

RG_LD RG_LDO_VXO2 O_VXO 2_STBTD 22_ULP RW

0

0

RW 1

0

20

19

18

17

16

5 4 3 2 1 0 DA_VX DA_VX DA_VX DA_VX DA_VX DA_VX O22_O O22_L_ O22_L_ O22_B O22_B O22_B CFB_EN STB EN _LP _STB _EN RO RO RO RO RO RO 0

4

18

00000000

31

Name DA_VXO22_OCFB_EN

19

LDO VXO22 Monitor

Bit Name Type Reset

Bit(s) 5

20

Description Selects VXO22 OC debounce time 1'b0: 60 us 1'b1: 120 us Selects VXO22 OCFB/OC shutdown 1'b0: OCFB 1'b1: OC shutdown Enables VXO22 OCFB/OC shutdown function 1'b0: Disable 1'b1: Enable Selects VXO22 LP/ULP when entering low power mode 1'b0: No ULP 1'b1: ULP Selects VXO22 soft start time 2'b00: 120 us 2'b01: 240 us 2'b10: 480 us 2'b11: 960 us

RG_LDO_VXO22_STBTD

00001B9E

21

6 5 4 RG_LD RG_LD RG_LD O_VXO O_VXO O_VXO 22_OC 22_OC 22_OCF _TSEL _MODE B_EN RW RW RW 0

5

1:0

00009C02 22

0

0

0

0

0

Description VXO22 OCFB status 1'b0: OCFB not activated 1'b1: OCFB activated VXO22 ULP soft-start status 1'b0: STB not ready 1'b1: STB ready VXO22 ULP enable status 1'b0: Disable

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 774 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

2

DA_VXO22_B_LP

1

DA_VXO22_B_STB

0

DA_VXO22_B_EN

00001BA0

Description 1'b1: Enable VXO22 low power mode status 1'b0: Normal mode 1'b1: Low power mode VXO22 NM soft start status 1'b0: STB not ready 1'b1: STB ready VXO22 NM enable status 1'b0: Disable 1'b1: Enable

LDO_VXO22_OP_EN

LDO VXO22 Operation Enable

00008000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

Name

Type Reset Bit(s) 2

Name RG_LDO_VXO22_HW2_OP_EN

1

RG_LDO_VXO22_HW1_OP_EN

0

RG_LDO_VXO22_HW0_OP_EN

00001BA2

18

17

16

2 1 0 RG_LD RG_LD RG_LD O_VXO O_VXO O_VXO 22_HW 22_HW 22_HW 2_OP_E 1_OP_E 0_OP_ N N EN RW RW RW 0

0

0

Description hw_ctrl[2] OPERATION ENABLE HW1: SRCLKEN2/PMRC_EN[2] 1'b0: Disable 1'b1: Enable hw_ctrl[1] OPERATION ENABLE HW1: SRCLKEN1/PMRC_EN[1] 1'b0: Disable 1'b1: Enable hw_ctrl[0] OPERATION ENABLE HW0: SRCLKEN0/PMRC_EN[0] 1'b0: Disable 1'b1: Enable

LDO_VXO22_OP_EN_SET

LDO VXO22 Operation Enable SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

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Page 775 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001BA4

Description

LDO_VXO22_OP_EN_CLR

LDO VXO22 Operation Enable CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

18

17

00001BA6

Description

LDO_VXO22_OP_CFG

LDO VXO22 Operation Config

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

Name Type Reset

2 1 0 RG_LD RG_LD RG_LD O_VXO O_VXO O_VXO 22_HW 22_HW 22_HW 2_OP_ 1_OP_ 0_OP_ CFG CFG CFG RW RW RW 0

Bit(s) 2

Name RG_LDO_VXO22_HW2_OP_CFG

1

RG_LDO_VXO22_HW1_OP_CFG

0

RG_LDO_VXO22_HW0_OP_CFG

MediaTek Proprietary and Confidential.

16

0

0

Description hw_ctrl[2] OPERATION CONFIG HW1: SRCLKEN2/PMRC_EN[2] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low) hw_ctrl[1] OPERATION CONFIG HW1: SRCLKEN1/PMRC_EN[1] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low) hw_ctrl[0] OPERATION CONFIG HW0: SRCLKEN0/PMRC_EN[0] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low)

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 776 of 1067

MT6359 PMIC Datasheet Confidential A 00001BA8

LDO_VXO22_OP_CFG_SET

LDO VXO22 Operation Config SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001BAA

Description

LDO_VXO22_OP_CFG_CLR

LDO VXO22 Operation Config CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

17

00001BAC

Description

LDO_VRF18_CON0

LDO VRF18 Control 0

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

Name Type Reset

1 0 RG_LD RG_LD O_VRF O_VRF 18_LP 18_EN RW RW 0

Bit(s) 1

Name RG_LDO_VRF18_LP

0

RG_LDO_VRF18_EN

MediaTek Proprietary and Confidential.

16

1

Description SW enter low power mode Valid once RG_LDO_VRF18_SW_OP_EN = 1'b1. 1'b0: No LP 1'b1: LP SW enable control Valid once RG_LDO_VRF18_SW_OP_EN = 1'b1. 1'b0: Off 1'b1: On

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 777 of 1067

MT6359 PMIC Datasheet Confidential A 00001BAE

LDO_VRF18_CON1

LDO VRF18 Control 1

00009C01

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

Bit

15

14

13

12

11

10

9

8

7

6 RG_LD O_VRF 18_OC _TSEL RW

Name Type Reset Bit(s) 6

0

Name RG_LDO_VRF18_OC_TSEL

5

RG_LDO_VRF18_OC_MODE

4

RG_LDO_VRF18_OCFB_EN

2

RG_LDO_VRF18_ULP

1:0

LDO_VRF18_MON

5 4 RG_LD RG_LD O_VRF O_VRF 18_OC 18_OCF _MODE B_EN RW RW 0

30

29

28

27

26

25

24

23

22

Bit

15

14

13

12

11

10

9

8

7

6

Name Type Reset

21

DA_VRF18_L_STB

3

DA_VRF18_L_EN

MediaTek Proprietary and Confidential.

17

16

3

2

1

0

RG_LD RG_LDO_VRF1 O_VRF 8_STBTD 18_ULP RW

0

0

RW 0

1

20

19

18

17

16

5 4 3 2 1 0 DA_VR DA_VR DA_VR DA_VR DA_VR DA_VR F18_OC F18_L_ F18_L_ F18_B_ F18_B_ F18_B_ FB_EN STB EN LP STB EN RO RO RO RO RO RO 0

4

18

00000000

31

Name DA_VRF18_OCFB_EN

19

LDO VRF18 Monitor

Bit Name Type Reset

Bit(s) 5

20

Description Selects VRF18 OC debounce time 1'b0: 60 us 1'b1: 120 us Selects VRF18 OCFB/OC shutdown 1'b0: OCFB 1'b1: OC shutdown Enables VRF18 OCFB/OC shutdown function 1'b0: Disable 1'b1: Enable Selects VRF18 LP/ULP when entering low power mode 1'b0: No ULP 1'b1: ULP Selects VRF18 soft start time 2'b00: 120 us 2'b01: 240 us 2'b10: 480 us 2'b11: 960 us

RG_LDO_VRF18_STBTD

00001BB0

21

0

0

0

0

0

Description VRF18 OCFB status 1'b0: OCFB not activated 1'b1: OCFB activated VRF18 ULP soft-start status 1'b0: STB not ready 1'b1: STB ready VRF18 ULP enable status 1'b0: Disable

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 778 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

2

DA_VRF18_B_LP

1

DA_VRF18_B_STB

0

DA_VRF18_B_EN

00001BB2

Description 1'b1: Enable VRF18 low power mode status 1'b0: Normal mode 1'b1: Low power mode VRF18 NM soft start status 1'b0: STB not ready 1'b1: STB ready VRF18 NM enable status 1'b0: Disable 1'b1: Enable

LDO_VRF18_OP_EN

LDO VRF18 Operation Enable

00008000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

Name

Type Reset Bit(s) 2

Name RG_LDO_VRF18_HW2_OP_EN

1

RG_LDO_VRF18_HW1_OP_EN

0

RG_LDO_VRF18_HW0_OP_EN

00001BB4

18

17

16

2 1 0 RG_LD RG_LD RG_LD O_VRF O_VRF O_VRF 18_HW 18_HW 18_HW 2_OP_E 1_OP_E 0_OP_ N N EN RW RW RW 0

0

0

Description hw_ctrl[2] OPERATION ENABLE HW1: SRCLKEN2/PMRC_EN[2] 1'b0: Disable 1'b1: Enable hw_ctrl[1] OPERATION ENABLE HW1: SRCLKEN1/PMRC_EN[1] 1'b0: Disable 1'b1: Enable hw_ctrl[0] OPERATION ENABLE HW0: SRCLKEN0/PMRC_EN[0] 1'b0: Disable 1'b1: Enable

LDO_VRF18_OP_EN_SET

LDO VRF18 Operation Enable SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

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Page 779 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001BB6

Description

LDO_VRF18_OP_EN_CLR

LDO VRF18 Operation Enable CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

18

17

00001BB8

Description

LDO_VRF18_OP_CFG

LDO VRF18 Operation Config

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

Name Type Reset

2 1 0 RG_LD RG_LD RG_LD O_VRF O_VRF O_VRF 18_HW 18_HW 18_HW 2_OP_ 1_OP_ 0_OP_ CFG CFG CFG RW RW RW 0

Bit(s) 2

Name RG_LDO_VRF18_HW2_OP_CFG

1

RG_LDO_VRF18_HW1_OP_CFG

0

RG_LDO_VRF18_HW0_OP_CFG

MediaTek Proprietary and Confidential.

16

0

0

Description hw_ctrl[2] OPERATION CONFIG HW1: SRCLKEN2/PMRC_EN[2] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low) hw_ctrl[1] OPERATION CONFIG HW1: SRCLKEN1/PMRC_EN[1] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low) hw_ctrl[0] OPERATION CONFIG HW0: SRCLKEN0/PMRC_EN[0] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low)

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 780 of 1067

MT6359 PMIC Datasheet Confidential A 00001BBA

LDO_VRF18_OP_CFG_SET

LDO VRF18 Operation Config SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001BBC

Description

LDO_VRF18_OP_CFG_CLR

LDO VRF18 Operation Config CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

17

00001BBE

Description

LDO_VRF12_CON0

LDO VRF12 Control 0

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

Name Type Reset

1 0 RG_LD RG_LD O_VRF O_VRF 12_LP 12_EN RW RW 0

Bit(s) 1

Name RG_LDO_VRF12_LP

0

RG_LDO_VRF12_EN

MediaTek Proprietary and Confidential.

16

1

Description SW enter low power mode Valid once RG_LDO_VRF12_SW_OP_EN = 1'b1. 1'b0: No LP 1'b1: LP SW enable control Valid once RG_LDO_VRF12_SW_OP_EN = 1'b1. 1'b0: Off 1'b1: On

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 781 of 1067

MT6359 PMIC Datasheet Confidential A 00001BC0

LDO_VRF12_CON1

LDO VRF12 Control 1

00009C02

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

Bit

15

14

13

12

11

10

9

8

7

6 RG_LD O_VRF 12_OC _TSEL RW

Name Type Reset Bit(s) 6

0

Name RG_LDO_VRF12_OC_TSEL

5

RG_LDO_VRF12_OC_MODE

4

RG_LDO_VRF12_OCFB_EN

2

RG_LDO_VRF12_ULP

1:0

LDO_VRF12_MON

5 4 RG_LD RG_LD O_VRF O_VRF 12_OC 12_OCF _MODE B_EN RW RW 0

30

29

28

27

26

25

24

23

22

Bit

15

14

13

12

11

10

9

8

7

6

Name Type Reset

21

DA_VRF12_L_STB

3

DA_VRF12_L_EN

MediaTek Proprietary and Confidential.

17

16

3

2

1

0

RG_LD RG_LDO_VRF1 O_VRF 2_STBTD 12_ULP RW

0

0

RW 1

0

20

19

18

17

16

5 4 3 2 1 0 DA_VR DA_VR DA_VR DA_VR DA_VR DA_VR F12_OC F12_L_ F12_L_ F12_B_ F12_B_ F12_B_ FB_EN STB EN LP STB EN RO RO RO RO RO RO 0

4

18

00000000

31

Name DA_VRF12_OCFB_EN

19

LDO VRF12 Monitor

Bit Name Type Reset

Bit(s) 5

20

Description Selects VRF12 OC debounce time 1'b0: 60 us 1'b1: 120 us Selects VRF12 OCFB/OC shutdown 1'b0: OCFB 1'b1: OC shutdown Enables VRF12 OCFB/OC shutdown function 1'b0: Disable 1'b1: Enable Selects VRF12 LP/ULP when entering low power mode 1'b0: No ULP 1'b1: ULP Selects VRF12 soft start time 2'b00: 120 us 2'b01: 240 us 2'b10: 480 us 2'b11: 960 us

RG_LDO_VRF12_STBTD

00001BC2

21

0

0

0

0

0

Description VRF12 OCFB status 1'b0: OCFB not activated 1'b1: OCFB activated VRF12 ULP soft-start status 1'b0: STB not ready 1'b1: STB ready VRF12 ULP enable status 1'b0: Disable

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 782 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

2

DA_VRF12_B_LP

1

DA_VRF12_B_STB

0

DA_VRF12_B_EN

00001BC4

Description 1'b1: Enable VRF12 low power mode status 1'b0: Normal mode 1'b1: Low power mode VRF12 NM soft start status 1'b0: STB not ready 1'b1: STB ready VRF12 NM enable status 1'b0: Disable 1'b1: Enable

LDO_VRF12_OP_EN

LDO VRF12 Operation Enable

00008000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

Name

Type Reset Bit(s) 2

Name RG_LDO_VRF12_HW2_OP_EN

1

RG_LDO_VRF12_HW1_OP_EN

0

RG_LDO_VRF12_HW0_OP_EN

00001BC6

18

17

16

2 1 0 RG_LD RG_LD RG_LD O_VRF O_VRF O_VRF 12_HW 12_HW 12_HW 2_OP_E 1_OP_E 0_OP_ N N EN RW RW RW 0

0

0

Description hw_ctrl[2] OPERATION ENABLE HW1: SRCLKEN2/PMRC_EN[2] 1'b0: Disable 1'b1: Enable hw_ctrl[1] OPERATION ENABLE HW1: SRCLKEN1/PMRC_EN[1] 1'b0: Disable 1'b1: Enable hw_ctrl[0] OPERATION ENABLE HW0: SRCLKEN0/PMRC_EN[0] 1'b0: Disable 1'b1: Enable

LDO_VRF12_OP_EN_SET

LDO VRF12 Operation Enable SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

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Page 783 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001BC8

Description

LDO_VRF12_OP_EN_CLR

LDO VRF12 Operation Enable CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

18

17

00001BCA

Description

LDO_VRF12_OP_CFG

LDO VRF12 Operation Config

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

Name Type Reset

2 1 0 RG_LD RG_LD RG_LD O_VRF O_VRF O_VRF 12_HW 12_HW 12_HW 2_OP_ 1_OP_ 0_OP_ CFG CFG CFG RW RW RW 0

Bit(s) 2

Name RG_LDO_VRF12_HW2_OP_CFG

1

RG_LDO_VRF12_HW1_OP_CFG

0

RG_LDO_VRF12_HW0_OP_CFG

MediaTek Proprietary and Confidential.

16

0

0

Description hw_ctrl[2] OPERATION CONFIG HW1: SRCLKEN2/PMRC_EN[2] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low) hw_ctrl[1] OPERATION CONFIG HW1: SRCLKEN1/PMRC_EN[1] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low) hw_ctrl[0] OPERATION CONFIG HW0: SRCLKEN0/PMRC_EN[0] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low)

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 784 of 1067

MT6359 PMIC Datasheet Confidential A 00001BCC

LDO_VRF12_OP_CFG_SET

LDO VRF12 Operation Config SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001BCE

Description

LDO_VRF12_OP_CFG_CLR

LDO VRF12 Operation Config CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001BD0

Description

LDO_VEFUSE_CON0

LDO VEFUSE Control 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

Name Type Reset

0 RG_LD RG_LD O_VEF O_VEF USE_E USE_LP N RW RW 0

Bit(s) 1

Name RG_LDO_VEFUSE_LP

0

RG_LDO_VEFUSE_EN

MediaTek Proprietary and Confidential.

16

0

Description SW enter low power mode Valid once RG_LDO_VEFUSE_SW_OP_EN = 1'b1. 1'b0: No LP 1'b1: LP SW enable control Valid once RG_LDO_VEFUSE_SW_OP_EN = 1'b1. 1'b0: Off 1'b1: On

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Page 785 of 1067

MT6359 PMIC Datasheet Confidential A 00001BD2

LDO_VEFUSE_CON1

LDO VEFUSE Control 1

00009C01

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

4

3

2

1

0

RG_LD O_VEF USE_O CFB_EN

RW

5 RG_LD O_VEF USE_O C_MO DE RW

RW

RW

0

0

0

0

RG_LD O_VEF USE_O C_TSEL

Name

Type Reset Bit(s) 6

Name RG_LDO_VEFUSE_OC_TSEL

5

RG_LDO_VEFUSE_OC_MODE

4

RG_LDO_VEFUSE_OCFB_EN

2

RG_LDO_VEFUSE_ULP

1:0

LDO_VEFUSE_MON

LDO VEFUSE Monitor

31

30

29

28

27

26

25

24

23

22

Bit

15

14

13

12

11

10

9

8

7

6

Name Type Reset

4

21

Name

Description

DA_VEFUSE_L_STB

1'b0: OCFB not activated 1'b1: OCFB activated VEFUSE ULP soft-start status 1'b0: STB not ready 1'b1: STB ready

20

19

18

17

16

5 4 3 2 1 0 DA_VE DA_VE DA_VE DA_VE DA_VE DA_VE FUSE_ FUSE_L FUSE_L FUSE_B FUSE_B FUSE_B OCFB_ _STB _EN _LP _STB _EN EN RO RO RO RO RO RO 0

MediaTek Proprietary and Confidential.

1

00000000

Bit Name Type Reset

Bit(s) 5

RW 0

Description Selects VEFUSE OC debounce time 1'b0: 60 us 1'b1: 120 us Selects VEFUSE OCFB/OC shutdown 1'b0: OCFB 1'b1: OC shutdown Enables VEFUSE OCFB/OC shutdown function 1'b0: Disable 1'b1: Enable Selects VEFUSE LP/ULP when entering low power mode 1'b0: No ULP 1'b1: ULP Selects VEFUSE soft start time 2'b00: 120 us 2'b01: 240 us 2'b10: 480 us 2'b11: 960 us

RG_LDO_VEFUSE_STBTD

00001BD4

RG_LD O_VEF RG_LDO_VEFU USE_UL SE_STBTD P

0

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0

0

0

0

Page 786 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 3

Name DA_VEFUSE_L_EN

2

DA_VEFUSE_B_LP

1

DA_VEFUSE_B_STB

0

DA_VEFUSE_B_EN

00001BD6

Description VEFUSE ULP enable status 1'b0: Disable 1'b1: Enable VEFUSE low power mode status 1'b0: Normal mode 1'b1: Low power mode VEFUSE NM soft start status 1'b0: STB not ready 1'b1: STB ready VEFUSE NM enable status 1'b0: Disable 1'b1: Enable

LDO_VEFUSE_OP_EN

LDO VEFUSE Operation Enable

00008000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

Name Type Reset Bit(s) 2

Name RG_LDO_VEFUSE_HW2_OP_EN

1

RG_LDO_VEFUSE_HW1_OP_EN

0

RG_LDO_VEFUSE_HW0_OP_EN

00001BD8

18

17

16

2 1 0 RG_LD RG_LD RG_LD O_VEF O_VEF O_VEF USE_H USE_H USE_H W2_OP W1_OP W0_OP _EN _EN _EN RW RW RW 0

0

0

Description hw_ctrl[2] OPERATION ENABLE HW1: SRCLKEN2/PMRC_EN[2] 1'b0: Disable 1'b1: Enable hw_ctrl[1] OPERATION ENABLE HW1: SRCLKEN1/PMRC_EN[1] 1'b0: Disable 1'b1: Enable hw_ctrl[0] OPERATION ENABLE HW0: SRCLKEN0/PMRC_EN[0] 1'b0: Disable 1'b1: Enable

LDO_VEFUSE_OP_EN_SET

LDO VEFUSE Operation Enable SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 787 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001BDA

Description

LDO_VEFUSE_OP_EN_CLR

LDO VEFUSE Operation Enable CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

18

17

00001BDC

Description

LDO_VEFUSE_OP_CFG

LDO VEFUSE Operation Config

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

Name Type Reset

2 1 0 RG_LD RG_LD RG_LD O_VEF O_VEF O_VEF USE_H USE_H USE_H W2_OP W1_OP W0_OP _CFG _CFG _CFG RW RW RW 0

Bit(s) 2

Name RG_LDO_VEFUSE_HW2_OP_CFG

1

RG_LDO_VEFUSE_HW1_OP_CFG

0

RG_LDO_VEFUSE_HW0_OP_CFG

MediaTek Proprietary and Confidential.

16

0

0

Description hw_ctrl[2] OPERATION CONFIG HW1: SRCLKEN2/PMRC_EN[2] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low) hw_ctrl[1] OPERATION CONFIG HW1: SRCLKEN1/PMRC_EN[1] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low) hw_ctrl[0] OPERATION CONFIG HW0: SRCLKEN0/PMRC_EN[0] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low)

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Page 788 of 1067

MT6359 PMIC Datasheet Confidential A 00001BDE

LDO_VEFUSE_OP_CFG_SET

LDO VEFUSE Operation Config SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001BE0

Description

LDO_VEFUSE_OP_CFG_CLR

LDO VEFUSE Operation Config CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

17

00001BE2

Description

LDO_VCN33_1_CON0

LDO VCN33_1 Control 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

Name Type Reset Bit(s) 1

0

1 0 RG_LD RG_LD O_VCN O_VCN 33_1_L 33_1_E P N_0 RW RW 0

Name RG_LDO_VCN33_1_LP

RG_LDO_VCN33_1_EN_0

MediaTek Proprietary and Confidential.

16

0

Description SW enter low power mode Valid once RG_LDO_VCN33_1_SW_OP_EN = 1'b1. 1'b0: No LP 1'b1: LP SW enable control Valid once RG_LDO_VCN33_1_SW_OP_EN = 1'b1. 1'b0: Off 1'b1: On

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Page 789 of 1067

MT6359 PMIC Datasheet Confidential A 00001BE4

LDO_VCN33_1_CON1

LDO VCN33_1 Control 1

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

Bit

15

14

13

12

11

10

9

8

7

6

Name

Type Reset Bit(s) 6

5

RG_LDO_VCN33_1_OC_MODE

4

RG_LDO_VCN33_1_OCFB_EN

2

RG_LDO_VCN33_1_ULP

1:0

LDO_VCN33_1_MON 30

29

28

27

26

25

24

23

22

Bit

15

14

13

12

11

10

9

8

7

6

Name Type Reset

21

16

3

2

1

0

RG_LD O_VCN RG_LDO_VCN3 33_1_U 3_1_STBTD LP RW

0

0

RW 0

1

Name

Description

DA_VCN33_1_L_STB

1'b0: OCFB not activated 1'b1: OCFB activated VCN33_1 ULP soft-start status 1'b0: STB not ready 1'b1: STB ready

20

19

18

17

16

5 4 3 2 1 0 DA_VC DA_VC DA_VC DA_VC DA_VC DA_VC N33_1_ N33_1_ N33_1_ N33_1_ N33_1_ N33_1 OCFB_ L_STB L_EN B_LP B_STB _B_EN EN RO RO RO RO RO RO 0

MediaTek Proprietary and Confidential.

17

00000000

31

4

18

LDO VCN33_1 Monitor

Bit Name Type Reset

Bit(s) 5

0

19

Description Selects VCN33_1 OC debounce time 1'b0: 60 us 1'b1: 120 us Selects VCN33_1 OCFB/OC shutdown 1'b0: OCFB 1'b1: OC shutdown Enables VCN33_1 OCFB/OC shutdown function 1'b0: Disable 1'b1: Enable Selects VCN33_1 LP/ULP when entering low power mode 1'b0: No ULP 1'b1: ULP Selects VCN33_1 soft start time 2'b00: 120 us 2'b01: 240 us 2'b10: 480 us 2'b11: 960 us

RG_LDO_VCN33_1_STBTD

00001BE6

20

5 4 RG_LD RG_LD RG_LD O_VCN O_VCN O_VCN 33_1_O 33_1_O 33_1_O C_MO C_TSEL CFB_EN DE RW RW RW 0

Name RG_LDO_VCN33_1_OC_TSEL

00009C01 21

0

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0

0

0

0

Page 790 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 3

Name DA_VCN33_1_L_EN

2

DA_VCN33_1_B_LP

1

DA_VCN33_1_B_STB

0

DA_VCN33_1_B_EN

00001BE8

Description VCN33_1 ULP enable status 1'b0: Disable 1'b1: Enable VCN33_1 low power mode status 1'b0: Normal mode 1'b1: Low power mode VCN33_1 NM soft start status 1'b0: STB not ready 1'b1: STB ready VCN33_1 NM enable status 1'b0: Disable 1'b1: Enable

LDO_VCN33_1_OP_EN

LDO VCN33_1 Operation Enable

00008000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

Name Type Reset Bit(s) 2

Name RG_LDO_VCN33_1_HW2_OP_EN

1

RG_LDO_VCN33_1_HW1_OP_EN

0

RG_LDO_VCN33_1_HW0_OP_EN

00001BEA

18

17

16

2 1 0 RG_LD RG_LD RG_LD O_VCN O_VCN O_VCN 33_1_H 33_1_H 33_1_ W2_OP W1_OP HW0_ _EN _EN OP_EN RW RW RW 0

0

0

Description hw_ctrl[2] OPERATION ENABLE HW1: SRCLKEN2/PMRC_EN[2] 1'b0: Disable 1'b1: Enable hw_ctrl[1] OPERATION ENABLE HW1: SRCLKEN1/PMRC_EN[1] 1'b0: Disable 1'b1: Enable hw_ctrl[0] OPERATION ENABLE HW0: SRCLKEN0/PMRC_EN[0] 1'b0: Disable 1'b1: Enable

LDO_VCN33_1_OP_EN_SET

LDO VCN33_1 Operation Enable SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

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Page 791 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001BEC

Description

LDO_VCN33_1_OP_EN_CLR

LDO VCN33_1 Operation Enable CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001BEE

Description

LDO_VCN33_1_OP_CFG

LDO VCN33_1 Operation Config

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

Name

Type Reset Bit(s) 2

Name RG_LDO_VCN33_1_HW2_OP_CFG

1

RG_LDO_VCN33_1_HW1_OP_CFG

0

RG_LDO_VCN33_1_HW0_OP_CFG

MediaTek Proprietary and Confidential.

16

0 RG_LD RG_LD RG_LD O_VCN O_VCN O_VCN 33_1_ 33_1_H 33_1_H HW0_ W2_OP W1_OP OP_CF _CFG _CFG G RW RW RW 0

Description hw_ctrl[2] OPERATION CONFIG HW1: SRCLKEN2/PMRC_EN[2] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low) hw_ctrl[1] OPERATION CONFIG HW1: SRCLKEN1/PMRC_EN[1] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low) hw_ctrl[0] OPERATION CONFIG HW0: SRCLKEN0/PMRC_EN[0] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low)

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Page 792 of 1067

MT6359 PMIC Datasheet Confidential A 00001BF0

LDO_VCN33_1_OP_CFG_SET LDO VCN33_1 Operation Config SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001BF2

Description

LDO_VCN33_1_OP_CFG_CLR LDO VCN33_1 Operation Config CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001BF4 Bit Name Type Reset

LDO_VCN33_1_MULTI_SW 31

15 RG_LD O_VCN Name 33_1_E N_1 RW Type

Bit

Reset Bit(s) 15

Description

LDO VCN33_1 Multi-SW User

00000000

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

Name RG_LDO_VCN33_1_EN_1

MediaTek Proprietary and Confidential.

Description Enable control (SW mode) Valid once RG_LDO_VCN33_1_SW_OP_EN = 1'b1. 1'b0: Off 1'b1: On

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 793 of 1067

MT6359 PMIC Datasheet Confidential A 00001C00

LDO_GNR1_DSN_ID

LDO_GNR1 Design ID Register

0000E100

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001C02

Description

LDO_GNR1_DSN_REV0

LDO_GNR1 Design Revision Register 0

00001000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001C04

Description

LDO_GNR1_DSN_DBI

LDO_GNR1 Design Bank Information Register

00000002

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001C06

Description

LDO_GNR1_DSN_DXI

LDO_GNR1 Design Extra Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 794 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001C08

Description

LDO_VCN33_2_CON0

LDO VCN33_2 Control 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

Name Type Reset Bit(s) 1

0

16

1 0 RG_LD RG_LD O_VCN O_VCN 33_2_L 33_2_E P N_0 RW RW 0

Name RG_LDO_VCN33_2_LP

LDO_VCN33_2_CON1

LDO VCN33_2 Control 1

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

Bit

15

14

13

12

11

10

9

8

7

6

Name

Type Reset

5

RG_LDO_VCN33_2_OC_MODE

4

RG_LDO_VCN33_2_OCFB_EN

2

RG_LDO_VCN33_2_ULP

MediaTek Proprietary and Confidential.

00009C01 21

20

5 4 RG_LD RG_LD RG_LD O_VCN O_VCN O_VCN 33_2_O 33_2_O 33_2_O C_MO C_TSEL CFB_EN DE RW RW RW 0

Name RG_LDO_VCN33_2_OC_TSEL

0

Description SW enter low power mode Valid once RG_LDO_VCN33_2_SW_OP_EN = 1'b1. 1'b0: No LP 1'b1: LP SW enable control Valid once RG_LDO_VCN33_2_SW_OP_EN = 1'b1. 1'b0: Off 1'b1: On

RG_LDO_VCN33_2_EN_0

00001C0A

Bit(s) 6

17

0

0

19

18

17

16

3

2

1

0

RG_LD O_VCN RG_LDO_VCN3 33_2_U 3_2_STBTD LP RW 0

RW 0

1

Description Selects VCN33_2 OC debounce time 1'b0: 60 us 1'b1: 120 us Selects VCN33_2 OCFB/OC shutdown 1'b0: OCFB 1'b1: OC shutdown Enables VCN33_2 OCFB/OC shutdown function 1'b0: Disable 1'b1: Enable Selects VCN33_2 LP/ULP when entering low power mode 1'b0: No ULP 1'b1: ULP

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 795 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 1:0

Name RG_LDO_VCN33_2_STBTD

00001C0C

Description Selects VCN33_2 soft start time 2'b00: 120 us 2'b01: 240 us 2'b10: 480 us 2'b11: 960 us

LDO_VCN33_2_MON

LDO VCN33_2 Monitor

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

Bit

15

14

13

12

11

10

9

8

7

6

Name Type Reset Bit(s) 5

21

4

DA_VCN33_2_L_STB

3

DA_VCN33_2_L_EN

2

DA_VCN33_2_B_LP

1

DA_VCN33_2_B_STB

0

DA_VCN33_2_B_EN

MediaTek Proprietary and Confidential.

19

18

17

16

5 4 3 2 1 0 DA_VC DA_VC DA_VC DA_VC DA_VC DA_VC N33_2_ N33_2_ N33_2_ N33_2_ N33_2_ N33_2 OCFB_ L_STB L_EN B_LP B_STB _B_EN EN RO RO RO RO RO RO 0

Name DA_VCN33_2_OCFB_EN

20

0

0

0

0

0

Description VCN33_2 OCFB status 1'b0: OCFB not activated 1'b1: OCFB activated VCN33_2 ULP soft-start status 1'b0: STB not ready 1'b1: STB ready VCN33_2 ULP enable status 1'b0: Disable 1'b1: Enable VCN33_2 low power mode status 1'b0: Normal mode 1'b1: Low power mode VCN33_2 NM soft start status 1'b0: STB not ready 1'b1: STB ready VCN33_2 NM enable status 1'b0: Disable 1'b1: Enable

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 796 of 1067

MT6359 PMIC Datasheet Confidential A 00001C0E

LDO_VCN33_2_OP_EN

LDO VCN33_2 Operation Enable

00008000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

Name

Type Reset Bit(s) 2

Name RG_LDO_VCN33_2_HW2_OP_EN

1

RG_LDO_VCN33_2_HW1_OP_EN

0

RG_LDO_VCN33_2_HW0_OP_EN

00001C10

18

17

16

2 1 0 RG_LD RG_LD RG_LD O_VCN O_VCN O_VCN 33_2_H 33_2_H 33_2_ W2_OP W1_OP HW0_ _EN _EN OP_EN RW RW RW 0

0

0

Description hw_ctrl[2] OPERATION ENABLE HW1: SRCLKEN2/PMRC_EN[2] 1'b0: Disable 1'b1: Enable hw_ctrl[1] OPERATION ENABLE HW1: SRCLKEN1/PMRC_EN[1] 1'b0: Disable 1'b1: Enable hw_ctrl[0] OPERATION ENABLE HW0: SRCLKEN0/PMRC_EN[0] 1'b0: Disable 1'b1: Enable

LDO_VCN33_2_OP_EN_SET

LDO VCN33_2 Operation Enable SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001C12

Description

LDO_VCN33_2_OP_EN_CLR

LDO VCN33_2 Operation Enable CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 797 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001C14

Description

LDO_VCN33_2_OP_CFG

LDO VCN33_2 Operation Config

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

Name

Type Reset Bit(s) 2

Name RG_LDO_VCN33_2_HW2_OP_CFG

1

RG_LDO_VCN33_2_HW1_OP_CFG

0

RG_LDO_VCN33_2_HW0_OP_CFG

00001C16

16

0 RG_LD RG_LD RG_LD O_VCN O_VCN O_VCN 33_2_ 33_2_H 33_2_H HW0_ W2_OP W1_OP OP_CF _CFG _CFG G RW RW RW 0

Description hw_ctrl[2] OPERATION CONFIG HW1: SRCLKEN2/PMRC_EN[2] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low) hw_ctrl[1] OPERATION CONFIG HW1: SRCLKEN1/PMRC_EN[1] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low) hw_ctrl[0] OPERATION CONFIG HW0: SRCLKEN0/PMRC_EN[0] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low)

LDO_VCN33_2_OP_CFG_SET LDO VCN33_2 Operation Config SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 798 of 1067

de

MT6359 PMIC Datasheet Confidential A 00001C18

LDO_VCN33_2_OP_CFG_CLR LDO VCN33_2 Operation Config CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001C1A

LDO_VCN33_2_MULTI_SW 31

Bit Name Type Reset

15 RG_LD O_VCN Name 33_2_E N_1 RW Type

Bit

Reset Bit(s) 15

Description

LDO VCN33_2 Multi-SW User

00000000

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

17

0

Name RG_LDO_VCN33_2_EN_1

00001C1C

Description Enable control (SW mode) Valid once RG_LDO_VCN33_2_SW_OP_EN = 1'b1. 1'b0: Off 1'b1: On

LDO_VCN13_CON0

LDO VCN13 Control 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

Name Type Reset Bit(s) 1

0

1 0 RG_LD RG_LD O_VCN O_VCN 13_LP 13_EN RW RW 0

Name

0

Description

RG_LDO_VCN13_EN

MediaTek Proprietary and Confidential.

16

Valid once RG_LDO_VCN13_SW_OP_EN = 1'b1. 1'b0: No LP 1'b1: LP SW enable control Valid once RG_LDO_VCN13_SW_OP_EN = 1'b1. 1'b0: Off

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 799 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001C1E

Description 1'b1: On

LDO_VCN13_CON1

LDO VCN13 Control 1

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

Bit

15

14

13

12

11

10

9

8

7

Name Type Reset Bit(s) 6

Name RG_LDO_VCN13_OC_TSEL

RG_LDO_VCN13_OC_MODE

4

RG_LDO_VCN13_OCFB_EN

2

RG_LDO_VCN13_ULP

LDO_VCN13_MON

Bit Name Type Reset

29

28

27

26

25

24

23

22

Bit

15

14

13

12

11

10

9

8

7

6

Name Type Reset

21

DA_VCN13_L_STB

MediaTek Proprietary and Confidential.

17

16

3

2

1

0

RG_LD RG_LDO_VCN1 O_VCN 3_STBTD 13_ULP RW

0

0

RW 0

1

20

19

18

17

16

5 4 3 2 1 0 DA_VC DA_VC DA_VC DA_VC DA_VC DA_VC N13_O N13_L_ N13_L_ N13_B N13_B N13_B CFB_EN STB EN _LP _STB _EN RO RO RO RO RO RO 0

Name DA_VCN13_OCFB_EN

18

00000000

30

4

0

19

LDO VCN13 Monitor

31

Bit(s) 5

20

Description Selects VCN13 OC debounce time 1'b0: 60 us 1'b1: 120 us Selects VCN13 OCFB/OC shutdown 1'b0: OCFB 1'b1: OC shutdown Enables VCN13 OCFB/OC shutdown function 1'b0: Disable 1'b1: Enable Selects VCN13 LP/ULP when entering low power mode 1'b0: No ULP 1'b1: ULP Selects VCN13 soft start time 2'b00: 120 us 2'b01: 240 us 2'b10: 480 us 2'b11: 960 us

RG_LDO_VCN13_STBTD

00001C20

21

6 5 4 RG_LD RG_LD RG_LD O_VCN O_VCN O_VCN 13_OC 13_OC 13_OCF _TSEL _MODE B_EN RW RW RW 0

5

1:0

00009C01 22

0

0

0

0

0

Description VCN13 OCFB status 1'b0: OCFB not activated 1'b1: OCFB activated VCN13 ULP soft-start status

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 800 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

3

DA_VCN13_L_EN

2

DA_VCN13_B_LP

1

DA_VCN13_B_STB

0

DA_VCN13_B_EN

00001C22

Description 1'b0: STB not ready 1'b1: STB ready VCN13 ULP enable status 1'b0: Disable 1'b1: Enable VCN13 low power mode status 1'b0: Normal mode 1'b1: Low power mode VCN13 NM soft start status 1'b0: STB not ready 1'b1: STB ready VCN13 NM enable status 1'b0: Disable 1'b1: Enable

LDO_VCN13_OP_EN

LDO VCN13 Operation Enable

00008000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

Name

Type Reset

18

Name RG_LDO_VCN13_HW2_OP_EN

1

RG_LDO_VCN13_HW1_OP_EN

0

RG_LDO_VCN13_HW0_OP_EN

MediaTek Proprietary and Confidential.

16

2 1 0 RG_LD RG_LD RG_LD O_VCN O_VCN O_VCN 13_HW 13_HW 13_HW 2_OP_E 1_OP_E 0_OP_ N N EN RW RW RW 0

Bit(s) 2

17

0

0

Description hw_ctrl[2] OPERATION ENABLE HW1: SRCLKEN2/PMRC_EN[2] 1'b0: Disable 1'b1: Enable hw_ctrl[1] OPERATION ENABLE HW1: SRCLKEN1/PMRC_EN[1] 1'b0: Disable 1'b1: Enable hw_ctrl[0] OPERATION ENABLE HW0: SRCLKEN0/PMRC_EN[0] 1'b0: Disable 1'b1: Enable

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 801 of 1067

MT6359 PMIC Datasheet Confidential A 00001C24

LDO_VCN13_OP_EN_SET

LDO VCN13 Operation Enable SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001C26

Description

LDO_VCN13_OP_EN_CLR

LDO VCN13 Operation Enable CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

18

17

00001C28

Description

LDO_VCN13_OP_CFG

LDO VCN13 Operation Config

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

Name Type Reset

2 1 0 RG_LD RG_LD RG_LD O_VCN O_VCN O_VCN 13_HW 13_HW 13_HW 2_OP_ 1_OP_ 0_OP_ CFG CFG CFG RW RW RW 0

Bit(s) 2

Name RG_LDO_VCN13_HW2_OP_CFG

1

RG_LDO_VCN13_HW1_OP_CFG

16

0

0

Description hw_ctrl[2] OPERATION CONFIG HW1: SRCLKEN2/PMRC_EN[2] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low) hw_ctrl[1] OPERATION CONFIG

EN[1]

0

RG_LDO_VCN13_HW0_OP_CFG

MediaTek Proprietary and Confidential.

1'b0: On (high), off (low) 1'b1: No LP (high), LP (low) hw_ctrl[0] OPERATION CONFIG HW0: SRCLKEN0/PMRC_EN[0] 1'b0: On (high), off (low)

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 802 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001C2A

Description 1'b1: No LP (high), LP (low)

LDO_VCN13_OP_CFG_SET

LDO VCN13 Operation Config SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001C2C

Description

LDO_VCN13_OP_CFG_CLR

LDO VCN13 Operation Config CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

17

00001C2E

Description

LDO_VCN18_CON0

LDO VCN18 Control 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

Name Type Reset

1 0 RG_LD RG_LD O_VCN O_VCN 18_LP 18_EN RW RW 0

Bit(s) 1

Name RG_LDO_VCN18_LP

0

RG_LDO_VCN18_EN

MediaTek Proprietary and Confidential.

16

0

Description SW enter low power mode Valid once RG_LDO_VCN18_SW_OP_EN = 1'b1. 1'b0: No LP 1'b1: LP SW enable control Valid once RG_LDO_VCN18_SW_OP_EN = 1'b1. 1'b0: Off 1'b1: On

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 803 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001C30

Description

LDO_VCN18_CON1

LDO VCN18 Control 1

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

Bit

15

14

13

12

11

10

9

8

7

Name Type Reset Bit(s) 6

22

Name RG_LDO_VCN18_OC_TSEL

RG_LDO_VCN18_OC_MODE

4

RG_LDO_VCN18_OCFB_EN

2

RG_LDO_VCN18_ULP

LDO_VCN18_MON

Bit Name Type Reset

29

28

27

26

25

24

23

22

Bit

15

14

13

12

11

10

9

8

7

6

Name Type Reset

21

DA_VCN18_L_STB

MediaTek Proprietary and Confidential.

17

16

3

2

1

0

RG_LD RG_LDO_VCN1 O_VCN 8_STBTD 18_ULP RW

0

0

RW 0

1

20

19

18

17

16

5 4 3 2 1 0 DA_VC DA_VC DA_VC DA_VC DA_VC DA_VC N18_O N18_L_ N18_L_ N18_B N18_B N18_B CFB_EN STB EN _LP _STB _EN RO RO RO RO RO RO 0

Name DA_VCN18_OCFB_EN

18

00000000

30

4

0

19

LDO VCN18 Monitor

31

Bit(s) 5

20

Description Selects VCN18 OC debounce time 1'b0: 60 us 1'b1: 120 us Selects VCN18 OCFB/OC shutdown 1'b0: OCFB 1'b1: OC shutdown Enables VCN18 OCFB/OC shutdown function 1'b0: Disable 1'b1: Enable Selects VCN18 LP/ULP when entering low power mode 1'b0: No ULP 1'b1: ULP Selects VCN18 soft start time 2'b00: 120 us 2'b01: 240 us 2'b10: 480 us 2'b11: 960 us

RG_LDO_VCN18_STBTD

00001C32

21

6 5 4 RG_LD RG_LD RG_LD O_VCN O_VCN O_VCN 18_OC 18_OC 18_OCF _TSEL _MODE B_EN RW RW RW 0

5

1:0

00009C01

0

0

0

0

0

Description VCN18 OCFB status 1'b0: OCFB not activated 1'b1: OCFB activated VCN18 ULP soft-start status 1'b0: STB not ready

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 804 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

3

DA_VCN18_L_EN

2

DA_VCN18_B_LP

1

DA_VCN18_B_STB

0

DA_VCN18_B_EN

00001C34

Description 1'b1: STB ready VCN18 ULP enable status 1'b1: enable 1'b0: disable VCN18 low power mode status 1'b0: Normal mode 1'b1: Low power mode VCN18 NM soft start status 1'b0: STB not ready 1'b1: STB ready VCN18 NM enable status 1'b0: Disable 1'b1: Enable

LDO_VCN18_OP_EN

LDO VCN18 Operation Enable

00008000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

Name

Type Reset Bit(s) 2

Name RG_LDO_VCN18_HW2_OP_EN

1

RG_LDO_VCN18_HW1_OP_EN

0

RG_LDO_VCN18_HW0_OP_EN

00001C36

18

17

16

2 1 0 RG_LD RG_LD RG_LD O_VCN O_VCN O_VCN 18_HW 18_HW 18_HW 2_OP_E 1_OP_E 0_OP_ N N EN RW RW RW 0

0

0

Description hw_ctrl[2] OPERATION ENABLE HW1: SRCLKEN2/PMRC_EN[2] 1'b0: Disable 1'b1: Enable hw_ctrl[1] OPERATION ENABLE HW1: SRCLKEN1/PMRC_EN[1] 1'b0: Disable 1'b1: Enable hw_ctrl[0] OPERATION ENABLE HW0: SRCLKEN0/PMRC_EN[0] 1'b0: Disable 1'b1: Enable

LDO_VCN18_OP_EN_SET

LDO VCN18 Operation Enable SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 805 of 1067

MT6359 PMIC Datasheet Confidential A

Bit(s)

Name

00001C38

Description

LDO_VCN18_OP_EN_CLR

LDO VCN18 Operation Enable CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

18

17

00001C3A

Description

LDO_VCN18_OP_CFG

LDO VCN18 Operation Config

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

Name Type Reset

2 1 0 RG_LD RG_LD RG_LD O_VCN O_VCN O_VCN 18_HW 18_HW 18_HW 2_OP_ 1_OP_ 0_OP_ CFG CFG CFG RW RW RW 0

Bit(s) 2

Name RG_LDO_VCN18_HW2_OP_CFG

1

RG_LDO_VCN18_HW1_OP_CFG

0

RG_LDO_VCN18_HW0_OP_CFG

MediaTek Proprietary and Confidential.

16

0

0

Description hw_ctrl[2] OPERATION CONFIG HW1: SRCLKEN2/PMRC_EN[2] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low) hw_ctrl[1] OPERATION CONFIG HW1: SRCLKEN1/PMRC_EN[1] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low) hw_ctrl[0] OPERATION CONFIG HW0: SRCLKEN0/PMRC_EN[0] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low)

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 806 of 1067

MT6359 PMIC Datasheet Confidential A 00001C3C

LDO_VCN18_OP_CFG_SET

LDO VCN18 Operation Config SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001C3E

Description

LDO_VCN18_OP_CFG_CLR

LDO VCN18 Operation Config CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

17

00001C40

Description

LDO_VA09_CON0

LDO VA09 Control 0

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

Name Type Reset

1 0 RG_LD RG_LD O_VA0 O_VA0 9_LP 9_EN RW RW 0

Bit(s) 1

Name RG_LDO_VA09_LP

0

RG_LDO_VA09_EN

MediaTek Proprietary and Confidential.

16

1

Description SW enter low power mode Valid once RG_LDO_VA09_SW_OP_EN = 1'b1. 1'b0: No LP 1'b1: LP SW enable control Valid once RG_LDO_VA09_SW_OP_EN = 1'b1. 1'b0: Off 1'b1: On

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 807 of 1067

MT6359 PMIC Datasheet Confidential A 00001C42

LDO_VA09_CON1

LDO VA09 Control 1

00009C03

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6 RG_LD O_VA0 9_OC_ TSEL RW

5 RG_LD O_VA0 9_OC_ MODE RW

4 RG_LD O_VA0 9_OCF B_EN RW

3

2

1

0

0

0

0

Name Type Reset Bit(s) 6

Name RG_LDO_VA09_OC_TSEL

5

RG_LDO_VA09_OC_MODE

4

RG_LDO_VA09_OCFB_EN

2

RG_LDO_VA09_ULP

1:0

LDO_VA09_MON 30

29

28

27

26

25

24

23

22

Bit

15

14

13

12

11

10

9

8

7

6

Name Type Reset

21

DA_VA09_L_STB

3

DA_VA09_L_EN

MediaTek Proprietary and Confidential.

1

20

19

18

17

16

5 4 3 2 1 0 DA_VA DA_VA DA_VA DA_VA DA_VA DA_VA 09_OCF 09_L_S 09_L_E 09_B_L 09_B_S 09_B_E B_EN TB N P TB N RO RO RO RO RO RO 0

4

RW 1

00000000

31

Name DA_VA09_OCFB_EN

0

LDO VA09 Monitor

Bit Name Type Reset

Bit(s) 5

RW

Description Selects VA09 OC debounce time 1'b0: 60 us 1'b1: 120 us Selects VA09 OCFB/OC shutdown 1'b0: OCFB 1'b1: OC shutdown Enables VA09 OCFB/OC shutdown function 1'b0: Disable 1'b1: Enable Selects VA09 LP/ULP when entering low power mode 1'b0: No ULP 1'b1: ULP Selects VA09 soft start time 2'b00: 120 us 2'b01: 240 us 2'b10: 480 us 2'b11: 960 us

RG_LDO_VA09_STBTD

00001C44

RG_LD RG_LDO_VA09 O_VA0 _STBTD 9_ULP

0

0

0

0

0

Description VA09 OCFB status 1'b0: OCFB not activated 1'b1: OCFB activated VA09 ULP soft-start status 1'b0: STB not ready 1'b1: STB ready VA09 ULP enable status 1'b0: Disable

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 808 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

2

DA_VA09_B_LP

1

DA_VA09_B_STB

0

DA_VA09_B_EN

00001C46

Description 1'b1: Enable VA09 low power mode status 1'b0: Normal mode 1'b1: Low power mode VA09 NM soft start status 1'b0: STB not ready 1'b1: STB ready VA09 NM enable status 1'b0: Disable 1'b1: Enable

LDO_VA09_OP_EN

LDO VA09 Operation Enable

00008000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

Name

Type Reset Bit(s) 2

Name RG_LDO_VA09_HW2_OP_EN

1

RG_LDO_VA09_HW1_OP_EN

0

RG_LDO_VA09_HW0_OP_EN

00001C48

18

17

16

2 1 0 RG_LD RG_LD RG_LD O_VA0 O_VA0 O_VA0 9_HW2 9_HW1 9_HW0 _OP_E _OP_E _OP_E N N N RW RW RW 0

0

0

Description hw_ctrl[2] OPERATION ENABLE HW1: SRCLKEN2/PMRC_EN[2] 1'b0: Disable 1'b1: Enable hw_ctrl[1] OPERATION ENABLE HW1: SRCLKEN1/PMRC_EN[1] 1'b0: Disable 1'b1: Enable hw_ctrl[0] OPERATION ENABLE HW0: SRCLKEN0/PMRC_EN[0] 1'b0: Disable 1'b1: Enable

LDO_VA09_OP_EN_SET

LDO VA09 Operation Enable SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

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Page 809 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001C4A

Description

LDO_VA09_OP_EN_CLR

LDO VA09 Operation Enable CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

18

17

00001C4C

Description

LDO_VA09_OP_CFG

LDO VA09 Operation Config

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

Name Type Reset

2 1 0 RG_LD RG_LD RG_LD O_VA0 O_VA0 O_VA0 9_HW2 9_HW1 9_HW0 _OP_CF _OP_CF _OP_C G G FG RW RW RW 0

Bit(s) 2

Name RG_LDO_VA09_HW2_OP_CFG

1

RG_LDO_VA09_HW1_OP_CFG

0

RG_LDO_VA09_HW0_OP_CFG

MediaTek Proprietary and Confidential.

16

0

0

Description hw_ctrl[2] OPERATION CONFIG HW1: SRCLKEN2/PMRC_EN[2] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low) hw_ctrl[1] OPERATION CONFIG HW1: SRCLKEN1/PMRC_EN[1] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low) hw_ctrl[0] OPERATION CONFIG HW0: SRCLKEN0/PMRC_EN[0] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low)

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Page 810 of 1067

MT6359 PMIC Datasheet Confidential A 00001C4E

LDO_VA09_OP_CFG_SET

LDO VA09 Operation Config SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001C50

Description

LDO_VA09_OP_CFG_CLR

LDO VA09 Operation Config CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

17

00001C52

Description

LDO_VCAMIO_CON0

LDO VCAMIO Control 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

Name Type Reset

1 0 RG_LD RG_LD O_VCA O_VCA MIO_L MIO_E P N RW RW 0

Bit(s) 1

Name RG_LDO_VCAMIO_LP

0

RG_LDO_VCAMIO_EN

MediaTek Proprietary and Confidential.

16

0

Description SW enter low power mode Valid once RG_LDO_VCAMIO_SW_OP_EN = 1'b1. 1'b0: No LP 1'b1: LP SW enable control Valid once RG_LDO_VCAMIO_SW_OP_EN = 1'b1. 1'b0: Off 1'b1: On

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Page 811 of 1067

MT6359 PMIC Datasheet Confidential A 00001C54

LDO_VCAMIO_CON1

LDO VCAMIO Control 1

00009C01

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

Bit

15

14

13

12

11

10

9

8

7

6 RG_LD O_VCA MIO_O C_TSEL

Name

Type Reset Bit(s) 6

RW 0

Name RG_LDO_VCAMIO_OC_TSEL

5

RG_LDO_VCAMIO_OC_MODE

4

RG_LDO_VCAMIO_OCFB_EN

2

RG_LDO_VCAMIO_ULP

1:0

LDO_VCAMIO_MON

0

30

29

28

27

26

25

24

23

22

Bit

15

14

13

12

11

10

9

8

7

6

Name Type Reset

21

17

16

3

2

1

0

RG_LD O_VCA RG_LDO_VCA MIO_U MIO_STBTD LP RW

0

0

RW 0

1

Name

Description

DA_VCAMIO_L_STB

1'b0: OCFB not activated 1'b1: OCFB activated VCAMIO ULP soft-start status 1'b0: STB not ready 1'b1: STB ready

20

19

18

17

16

5 4 3 2 1 0 DA_VC DA_VC DA_VC DA_VC DA_VC DA_VC AMIO_ AMIO_ AMIO_ AMIO_ AMIO_ AMIO_ OCFB_ L_STB L_EN B_LP B_STB B_EN EN RO RO RO RO RO RO 0

MediaTek Proprietary and Confidential.

18

00000000

31

4

5 4 RG_LD RG_LD O_VCA O_VCA MIO_O MIO_O C_MO CFB_EN DE RW RW

19

LDO VCAMIO Monitor

Bit Name Type Reset

Bit(s) 5

20

Description Selects VCAMIO OC debounce time 1'b0: 60 us 1'b1: 120 us Selects VCAMIO OCFB/OC shutdown 1'b0: OCFB 1'b1: OC shutdown Enables VCAMIO OCFB/OC shutdown function 1'b0: Disable 1'b1: Enable Selects VCAMIO LP/ULP when entering low power mode 1'b0: No ULP 1'b1: ULP Selects VCAMIO soft start time 2'b00: 240 us 2'b01: 480 us 2'b10: 1920 us 2'b11: 3840 us

RG_LDO_VCAMIO_STBTD

00001C56

21

0

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

0

0

0

0

Page 812 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 3

Name DA_VCAMIO_L_EN

2

DA_VCAMIO_B_LP

1

DA_VCAMIO_B_STB

0

DA_VCAMIO_B_EN

00001C58

Description VCAMIO ULP enable status 1'b0: Disable 1'b1: Enable VCAMIO low power mode status 1'b0: Normal mode 1'b1: Low power mode VCAMIO NM soft start status 1'b0: STB not ready 1'b1: STB ready VCAMIO NM enable status 1'b0: Disable 1'b1: Enable

LDO_VCAMIO_OP_EN

LDO VCAMIO Operation Enable

00008000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

Name Type Reset Bit(s) 2

Name RG_LDO_VCAMIO_HW2_OP_EN

1

RG_LDO_VCAMIO_HW1_OP_EN

0

RG_LDO_VCAMIO_HW0_OP_EN

00001C5A

18

17

16

2 1 0 RG_LD RG_LD RG_LD O_VCA O_VCA O_VCA MIO_H MIO_H MIO_H W2_OP W1_OP W0_OP _EN _EN _EN RW RW RW 0

0

0

Description hw_ctrl[2] OPERATION ENABLE HW1: SRCLKEN2/PMRC_EN[2] 1'b0: Disable 1'b1: Enable hw_ctrl[1] OPERATION ENABLE HW1: SRCLKEN1/PMRC_EN[1] 1'b0: Disable 1'b1: Enable hw_ctrl[0] OPERATION ENABLE HW0: SRCLKEN0/PMRC_EN[0] 1'b0: Disable 1'b1: Enable

LDO_VCAMIO_OP_EN_SET

LDO VCAMIO Operation Enable SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

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Page 813 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001C5C

Description

LDO_VCAMIO_OP_EN_CLR

LDO VCAMIO Operation Enable CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

18

17

00001C5E

Description

LDO_VCAMIO_OP_CFG

LDO VCAMIO Operation Config

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

Name Type Reset

2 1 0 RG_LD RG_LD RG_LD O_VCA O_VCA O_VCA MIO_H MIO_H MIO_H W2_OP W1_OP W0_OP _CFG _CFG _CFG RW RW RW 0

Bit(s) 2

Name RG_LDO_VCAMIO_HW2_OP_CFG

1

RG_LDO_VCAMIO_HW1_OP_CFG

0

RG_LDO_VCAMIO_HW0_OP_CFG

MediaTek Proprietary and Confidential.

16

0

0

Description hw_ctrl[2] OPERATION CONFIG HW1: SRCLKEN2/PMRC_EN[2] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low) hw_ctrl[1] OPERATION CONFIG HW1: SRCLKEN1/PMRC_EN[1] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low) hw_ctrl[0] OPERATION CONFIG HW0: SRCLKEN0/PMRC_EN[0] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low)

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Page 814 of 1067

MT6359 PMIC Datasheet Confidential A 00001C60

LDO_VCAMIO_OP_CFG_SET LDO VCAMIO Operation Config SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001C62

Description

LDO_VCAMIO_OP_CFG_CLR LDO VCAMIO Operation Config CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

17

00001C64

Description

LDO_VA12_CON0

LDO VA12 Control 0

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

Name Type Reset

1 0 RG_LD RG_LD O_VA1 O_VA1 2_LP 2_EN RW RW 0

Bit(s) 1

Name RG_LDO_VA12_LP

0

RG_LDO_VA12_EN

MediaTek Proprietary and Confidential.

16

1

Description SW enter low power mode Valid once RG_LDO_VA12_SW_OP_EN = 1'b1. 1'b0: No LP 1'b1: LP SW enable control Valid once RG_LDO_VA12_SW_OP_EN = 1'b1. 1'b0: Off 1'b1: On

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Page 815 of 1067

MT6359 PMIC Datasheet Confidential A 00001C66

LDO_VA12_CON1

LDO VA12 Control 1

00009C03

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6 RG_LD O_VA1 2_OC_ TSEL RW

5 RG_LD O_VA1 2_OC_ MODE RW

4 RG_LD O_VA1 2_OCF B_EN RW

3

2

1

0

0

0

0

Name Type Reset Bit(s) 6

Name RG_LDO_VA12_OC_TSEL

5

RG_LDO_VA12_OC_MODE

4

RG_LDO_VA12_OCFB_EN

2

RG_LDO_VA12_ULP

1:0

LDO_VA12_MON 30

29

28

27

26

25

24

23

22

Bit

15

14

13

12

11

10

9

8

7

6

Name Type Reset

21

DA_VA12_L_STB

3

DA_VA12_L_EN

MediaTek Proprietary and Confidential.

1

20

19

18

17

16

5 4 3 2 1 0 DA_VA DA_VA DA_VA DA_VA DA_VA DA_VA 12_OCF 12_L_S 12_L_E 12_B_L 12_B_S 12_B_E B_EN TB N P TB N RO RO RO RO RO RO 0

4

RW 1

00000000

31

Name DA_VA12_OCFB_EN

0

LDO VA12 Monitor

Bit Name Type Reset

Bit(s) 5

RW

Description Selects VA12 OC debounce time 1'b0: 60 us 1'b1: 120 us Selects VA12 OCFB/OC shutdown 1'b0: OCFB 1'b1: OC shutdown Enables VA12 OCFB/OC shutdown function 1'b0: Disable 1'b1: Enable Selects VA12 LP/ULP when entering low power mode 1'b0: No ULP 1'b1: ULP Selects VA12 soft start time 2'b00: 120 us 2'b01: 240 us 2'b10: 480 us 2'b11: 960 us

RG_LDO_VA12_STBTD

00001C68

RG_LD RG_LDO_VA12 O_VA1 _STBTD 2_ULP

0

0

0

0

0

Description VA12 OCFB status 1'b0: OCFB not activated 1'b1: OCFB activated VA12 ULP soft-start status 1'b0: STB not ready 1'b1: STB ready VA12 ULP enable status 1'b0: Disable

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 816 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

2

DA_VA12_B_LP

1

DA_VA12_B_STB

0

DA_VA12_B_EN

00001C6A

Description 1'b1: Enable VA12 low power mode status 1'b0: Normal mode 1'b1: Low power mode VA12 NM soft start status 1'b0: STB not ready 1'b1: STB ready VA12 NM enable status 1'b0: Disable 1'b1: Enable

LDO_VA12_OP_EN

LDO VA12 Operation Enable

00008000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

Name

Type Reset Bit(s) 2

Name RG_LDO_VA12_HW2_OP_EN

1

RG_LDO_VA12_HW1_OP_EN

0

RG_LDO_VA12_HW0_OP_EN

00001C6C

18

17

16

2 1 0 RG_LD RG_LD RG_LD O_VA1 O_VA1 O_VA1 2_HW2 2_HW1 2_HW0 _OP_E _OP_E _OP_E N N N RW RW RW 0

0

0

Description hw_ctrl[2] OPERATION ENABLE HW1: SRCLKEN2/PMRC_EN[2] 1'b0: Disable 1'b1: Enable hw_ctrl[1] OPERATION ENABLE HW1: SRCLKEN1/PMRC_EN[1] 1'b0: Disable 1'b1: Enable hw_ctrl[0] OPERATION ENABLE HW0: SRCLKEN0/PMRC_EN[0] 1'b0: Disable 1'b1: Enable

LDO_VA12_OP_EN_SET

LDO VA12 Operation Enable SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

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Page 817 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001C6E

Description

LDO_VA12_OP_EN_CLR

LDO VA12 Operation Enable CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

18

17

00001C70

Description

LDO_VA12_OP_CFG

LDO VA12 Operation Config

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

Name Type Reset

2 1 0 RG_LD RG_LD RG_LD O_VA1 O_VA1 O_VA1 2_HW2 2_HW1 2_HW0 _OP_CF _OP_CF _OP_C G G FG RW RW RW 0

Bit(s) 2

Name RG_LDO_VA12_HW2_OP_CFG

1

RG_LDO_VA12_HW1_OP_CFG

0

RG_LDO_VA12_HW0_OP_CFG

MediaTek Proprietary and Confidential.

16

0

0

Description hw_ctrl[2] OPERATION CONFIG HW1: SRCLKEN2/PMRC_EN[2] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low) hw_ctrl[1] OPERATION CONFIG HW1: SRCLKEN1/PMRC_EN[1] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low) hw_ctrl[0] OPERATION CONFIG HW0: SRCLKEN0/PMRC_EN[0] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low)

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 818 of 1067

MT6359 PMIC Datasheet Confidential A 00001C72

LDO_VA12_OP_CFG_SET

LDO VA12 Operation Config SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001C74

Description

LDO_VA12_OP_CFG_CLR

LDO VA12 Operation Config CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001C80

Description

LDO_GNR2_DSN_ID

LDO_GNR2 Design ID Register

0000E100

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001C82

Description

LDO_GNR2_DSN_REV0

LDO_GNR2 Design Revision Register 0

00001000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

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Page 819 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001C84

Description

LDO_GNR2_DSN_DBI

LDO_GNR2 Design Bank Information Register

00000002

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001C86

Description

LDO_GNR2_DSN_DXI

LDO_GNR2 Design Extra Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001C88

Description

LDO_VAUX18_CON0

LDO VAUX18 Control 0

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

Name Type Reset

0 RG_LD RG_LD O_VAU O_VAU X18_E X18_LP N RW RW 0

Bit(s) 1

Name RG_LDO_VAUX18_LP

0

RG_LDO_VAUX18_EN

MediaTek Proprietary and Confidential.

16

1

Description SW enter low power mode Valid once RG_LDO_VAUX18_SW_OP_EN = 1'b1. 1'b0: No LP 1'b1: LP SW enable control Valid once RG_LDO_VAUX18_SW_OP_EN = 1'b1. 1'b0: Off 1'b1: On

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Page 820 of 1067

MT6359 PMIC Datasheet Confidential A 00001C8A

LDO_VAUX18_CON1

LDO VAUX18 Control 1

00009C01

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

Bit

15

14

13

12

11

10

9

8

7

6

Name

Type Reset Bit(s) 6

5

RG_LDO_VAUX18_OC_MODE

4

RG_LDO_VAUX18_OCFB_EN

2

RG_LDO_VAUX18_ULP

1:0

LDO_VAUX18_MON 30

29

28

27

26

25

24

23

22

Bit

15

14

13

12

11

10

9

8

7

6

Name Type Reset

4

21

MediaTek Proprietary and Confidential.

16

3

2

1

0

RG_LD O_VAU RG_LDO_VAUX X18_UL 18_STBTD P RW

0

0

RW 0

1

20

19

18

17

16

5 4 3 2 1 0 DA_VA DA_VA DA_VA DA_VA DA_VA DA_VA UX18_ UX18_L UX18_L UX18_ UX18_ UX18_ OCFB_ _STB _EN B_LP B_STB B_EN EN RO RO RO RO RO RO 0

DA_VAUX18_L_STB

17

00000000

31

Name DA_VAUX18_OCFB_EN

18

LDO VAUX18 Monitor

Bit Name Type Reset

Bit(s) 5

0

19

Description Selects VAUX18 OC debounce time 1'b0: 60 us 1'b1: 120 us Selects VAUX18 OCFB/OC shutdown 1'b0: OCFB 1'b1: OC shutdown Enables VAUX18 OCFB/OC shutdown function 1'b0: Disable 1'b1: Enable Selects VAUX18 LP/ULP when entering low power mode 1'b0: No ULP 1'b1: ULP Selects VAUX18 soft start time 2'b00: 120 us 2'b01: 240 us 2'b10: 480 us 2'b11: 960 us

RG_LDO_VAUX18_STBTD

00001C8C

20

5 4 RG_LD RG_LD RG_LD O_VAU O_VAU O_VAU X18_O X18_O X18_O C_MO C_TSEL CFB_EN DE RW RW RW 0

Name RG_LDO_VAUX18_OC_TSEL

21

0

0

0

0

0

Description VAUX18 OCFB status 1'b0: OCFB not activated 1'b1: OCFB activated VAUX18 ULP soft-start status 1'b0: STB not ready 1'b1: STB ready

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 821 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 3

Name DA_VAUX18_L_EN

2

DA_VAUX18_B_LP

1

DA_VAUX18_B_STB

0

DA_VAUX18_B_EN

00001C8E

Description VAUX18 ULP enable status 1'b0: Disable 1'b1: Enable VAUX18 low power mode status 1'b0: Normal mode 1'b1: Low power mode VAUX18 NM soft start status 1'b0: STB not ready 1'b1: STB ready VAUX18 NM enable status 1'b0: Disable 1'b1: Enable

LDO_VAUX18_OP_EN

LDO VAUX18 Operation Enable

00008000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

Name Type Reset Bit(s) 2

Name RG_LDO_VAUX18_HW2_OP_EN

1

RG_LDO_VAUX18_HW1_OP_EN

0

RG_LDO_VAUX18_HW0_OP_EN

00001C90

18

17

16

2 1 0 RG_LD RG_LD RG_LD O_VAU O_VAU O_VAU X18_H X18_H X18_H W2_OP W1_OP W0_OP _EN _EN _EN RW RW RW 0

0

0

Description hw_ctrl[2] OPERATION ENABLE HW1: SRCLKEN2/PMRC_EN[2] 1'b0: Disable 1'b1: Enable hw_ctrl[1] OPERATION ENABLE HW1: SRCLKEN1/PMRC_EN[1] 1'b0: Disable 1'b1: Enable hw_ctrl[0] OPERATION ENABLE HW0: SRCLKEN0/PMRC_EN[0] 1'b0: Disable 1'b1: Enable

LDO_VAUX18_OP_EN_SET

LDO VAUX18 Operation Enable SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 822 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001C92

Description

LDO_VAUX18_OP_EN_CLR

LDO VAUX18 Operation Enable CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

18

17

00001C94

Description

LDO_VAUX18_OP_CFG

LDO VAUX18 Operation Config

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

Name Type Reset

2 1 0 RG_LD RG_LD RG_LD O_VAU O_VAU O_VAU X18_H X18_H X18_H W2_OP W1_OP W0_OP _CFG _CFG _CFG RW RW RW 0

Bit(s) 2

Name RG_LDO_VAUX18_HW2_OP_CFG

1

RG_LDO_VAUX18_HW1_OP_CFG

0

RG_LDO_VAUX18_HW0_OP_CFG

MediaTek Proprietary and Confidential.

16

0

0

Description hw_ctrl[2] OPERATION CONFIG HW1: SRCLKEN2/PMRC_EN[2] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low) hw_ctrl[1] OPERATION CONFIG HW1: SRCLKEN1/PMRC_EN[1] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low) hw_ctrl[0] OPERATION CONFIG HW0: SRCLKEN0/PMRC_EN[0] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low)

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 823 of 1067

MT6359 PMIC Datasheet Confidential A 00001C96

LDO_VAUX18_OP_CFG_SET

LDO VAUX18 Operation Config SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001C98

Description

LDO_VAUX18_OP_CFG_CLR

LDO VAUX18 Operation Config CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001C9A

Description

LDO_VAUD18_CON0

LDO VAUD18 Control 0

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

Name Type Reset

0 RG_LD RG_LD O_VAU O_VAU D18_E D18_LP N RW RW 0

Bit(s) 1

Name RG_LDO_VAUD18_LP

0

RG_LDO_VAUD18_EN

MediaTek Proprietary and Confidential.

16

1

Description SW enter low power mode Valid once RG_LDO_VAUD18_SW_OP_EN = 1'b1. 1'b0: No LP 1'b1: LP SW enable control Valid once RG_LDO_VAUD18_SW_OP_EN = 1'b1. 1'b0: Off 1'b1: On

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Page 824 of 1067

MT6359 PMIC Datasheet Confidential A 00001C9C

LDO_VAUD18_CON1

LDO VAUD18 Control 1

00009C01

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

Bit

15

14

13

12

11

10

9

8

7

6

Name

Type Reset Bit(s) 6

5

RG_LDO_VAUD18_OC_MODE

4

RG_LDO_VAUD18_OCFB_EN

2

RG_LDO_VAUD18_ULP

1:0

LDO_VAUD18_MON 30

29

28

27

26

25

24

23

22

Bit

15

14

13

12

11

10

9

8

7

6

Name Type Reset

21

16

3

2

1

0

RG_LD O_VAU RG_LDO_VAUD D18_U 18_STBTD LP RW

0

0

RW 0

1

Name

Description

DA_VAUD18_L_STB

1'b0: OCFB not activated 1'b1: OCFB activated VAUD18 ULP soft-start status 1'b0: STB not ready 1'b1: STB ready

20

19

18

17

16

5 4 3 2 1 0 DA_VA DA_VA DA_VA DA_VA DA_VA DA_VA UD18_ UD18_ UD18_ UD18_ UD18_ UD18_ OCFB_ L_STB L_EN B_LP B_STB B_EN EN RO RO RO RO RO RO 0

MediaTek Proprietary and Confidential.

17

00000000

31

4

18

LDO VAUD18 Monitor

Bit Name Type Reset

Bit(s) 5

0

19

Description Selects VAUD18 OC debounce time 1'b0: 60 us 1'b1: 120 us Selects VAUD18 OCFB/OC shutdown 1'b0: OCFB 1'b1: OC shutdown Enables VAUD18 OCFB/OC shutdown function 1'b0: Disable 1'b1: Enable Selects VAUD18 LP/ULP when entering low power mode 1'b0: No ULP 1'b1: ULP Selects VAUD18 soft start time 2'b00: 120 us 2'b01: 240 us 2'b10: 480 us 2'b11: 960 us

RG_LDO_VAUD18_STBTD

00001C9E

20

5 4 RG_LD RG_LD RG_LD O_VAU O_VAU O_VAU D18_O D18_O D18_O C_MO C_TSEL CFB_EN DE RW RW RW 0

Name RG_LDO_VAUD18_OC_TSEL

21

0

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

0

0

0

0

Page 825 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 3

Name DA_VAUD18_L_EN

2

DA_VAUD18_B_LP

1

DA_VAUD18_B_STB

0

DA_VAUD18_B_EN

00001CA0

Description VAUD18 ULP enable status 1'b0: Disable 1'b1: Enable VAUD18 low power mode status 1'b0: Normal mode 1'b1: Low power mode VAUD18 NM soft start status 1'b0: STB not ready 1'b1: STB ready VAUD18 NM enable status 1'b0: Disable 1'b1: Enable

LDO_VAUD18_OP_EN

LDO VAUD18 Operation Enable

00008000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

Name Type Reset Bit(s) 2

Name RG_LDO_VAUD18_HW2_OP_EN

1

RG_LDO_VAUD18_HW1_OP_EN

0

RG_LDO_VAUD18_HW0_OP_EN

00001CA2

18

17

16

2 1 0 RG_LD RG_LD RG_LD O_VAU O_VAU O_VAU D18_H D18_H D18_H W2_OP W1_OP W0_OP _EN _EN _EN RW RW RW 0

0

0

Description hw_ctrl[2] OPERATION ENABLE HW1: SRCLKEN2/PMRC_EN[2] 1'b0: Disable 1'b1: Enable hw_ctrl[1] OPERATION ENABLE HW1: SRCLKEN1/PMRC_EN[1] 1'b0: Disable 1'b1: Enable hw_ctrl[0] OPERATION ENABLE HW0: SRCLKEN0/PMRC_EN[0] 1'b0: Disable 1'b1: Enable

LDO_VAUD18_OP_EN_SET

LDO VAUD18 Operation Enable SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 826 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001CA4

Description

LDO_VAUD18_OP_EN_CLR

LDO VAUD18 Operation Enable CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

18

17

00001CA6

Description

LDO_VAUD18_OP_CFG

LDO VAUD18 Operation Config

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

Name Type Reset

2 1 0 RG_LD RG_LD RG_LD O_VAU O_VAU O_VAU D18_H D18_H D18_H W2_OP W1_OP W0_OP _CFG _CFG _CFG RW RW RW 0

Bit(s) 2

Name RG_LDO_VAUD18_HW2_OP_CFG

1

RG_LDO_VAUD18_HW1_OP_CFG

0

RG_LDO_VAUD18_HW0_OP_CFG

MediaTek Proprietary and Confidential.

16

0

0

Description hw_ctrl[2] OPERATION CONFIG HW1: SRCLKEN2/PMRC_EN[2] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low) hw_ctrl[1] OPERATION CONFIG HW1: SRCLKEN1/PMRC_EN[1] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low) hw_ctrl[0] OPERATION CONFIG HW0: SRCLKEN0/PMRC_EN[0] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low)

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 827 of 1067

MT6359 PMIC Datasheet Confidential A 00001CA8

LDO_VAUD18_OP_CFG_SET

LDO VAUD18 Operation Config SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001CAA

Description

LDO_VAUD18_OP_CFG_CLR LDO VAUD18 Operation Config CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

17

00001CAC

Description

LDO_VIO18_CON0

LDO VIO18 Control 0

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

Name Type Reset

1 0 RG_LD RG_LD O_VIO O_VIO 18_LP 18_EN RW RW 0

Bit(s) 1

Name RG_LDO_VIO18_LP

0

RG_LDO_VIO18_EN

MediaTek Proprietary and Confidential.

16

1

Description SW enter low power mode Valid once RG_LDO_VIO18_SW_OP_EN = 1'b1. 1'b0: No LP 1'b1: LP SW enable control Valid once RG_LDO_VIO18_SW_OP_EN = 1'b1. 1'b0: Off 1'b1: On

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 828 of 1067

MT6359 PMIC Datasheet Confidential A 00001CAE

LDO_VIO18_CON1

LDO VIO18 Control 1

00009C02

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

Bit

15

14

13

12

11

10

9

8

7

6 RG_LD O_VIO 18_OC _TSEL RW

Name Type Reset Bit(s) 6

0

Name RG_LDO_VIO18_OC_TSEL

5

RG_LDO_VIO18_OC_MODE

4

RG_LDO_VIO18_OCFB_EN

2

RG_LDO_VIO18_ULP

1:0

LDO_VIO18_MON

5 4 RG_LD RG_LD O_VIO O_VIO 18_OC 18_OCF _MODE B_EN RW RW 0

30

29

28

27

26

25

24

23

22

Bit

15

14

13

12

11

10

9

8

7

6

Name Type Reset

21

DA_VIO18_L_STB

3

DA_VIO18_L_EN

MediaTek Proprietary and Confidential.

17

16

3

2

1

0

RG_LD RG_LDO_VIO1 O_VIO 8_STBTD 18_ULP RW

0

0

RW 1

0

20

19

18

17

16

5 4 3 2 1 0 DA_VI DA_VI DA_VI DA_VI DA_VI DA_VI O18_O O18_L_ O18_L_ O18_B O18_B O18_B CFB_EN STB EN _LP _STB _EN RO RO RO RO RO RO 0

4

18

00000000

31

Name DA_VIO18_OCFB_EN

19

LDO VIO18 Monitor

Bit Name Type Reset

Bit(s) 5

20

Description Selects VIO18 OC debounce time 1'b0: 60 us 1'b1: 120 us Selects VIO18 OCFB/OC shutdown 1'b0: OCFB 1'b1: OC shutdown Enables VIO18 OCFB/OC shutdown function 1'b0: Disable 1'b1: Enable Selects VIO18 LP/ULP when entering low power mode 1'b0: No ULP 1'b1: ULP Selects VIO18 soft start time 2'b00: 240 us 2'b01: 480 us 2'b10: 960 us 2'b11: 4320 us

RG_LDO_VIO18_STBTD

00001CB0

21

0

0

0

0

0

Description VIO18 OCFB status 1'b0: OCFB not activated 1'b1: OCFB activated VIO18 ULP soft-start status 1'b0: STB not ready 1'b1: STB ready VIO18 ULP enable status 1'b0: Disable

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 829 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

2

DA_VIO18_B_LP

1

DA_VIO18_B_STB

0

DA_VIO18_B_EN

00001CB2

Description 1'b1: Enable VIO18 low power mode status 1'b0: Normal mode 1'b1: Low power mode VIO18 NM soft start status 1'b0: STB not ready 1'b1: STB ready VIO18 NM enable status 1'b0: Disable 1'b1: Enable

LDO_VIO18_OP_EN

LDO VIO18 Operation Enable

00008000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

Name

Type Reset Bit(s) 2

Name RG_LDO_VIO18_HW2_OP_EN

1

RG_LDO_VIO18_HW1_OP_EN

0

RG_LDO_VIO18_HW0_OP_EN

00001CB4

18

17

16

2 1 0 RG_LD RG_LD RG_LD O_VIO O_VIO O_VIO 18_HW 18_HW 18_HW 2_OP_E 1_OP_E 0_OP_ N N EN RW RW RW 0

0

0

Description hw_ctrl[2] OPERATION ENABLE HW1: SRCLKEN2/PMRC_EN[2] 1'b0: Disable 1'b1: Enable hw_ctrl[1] OPERATION ENABLE HW1: SRCLKEN1/PMRC_EN[1] 1'b0: Disable 1'b1: Enable hw_ctrl[0] OPERATION ENABLE HW0: SRCLKEN0/PMRC_EN[0] 1'b0: Disable 1'b1: Enable

LDO_VIO18_OP_EN_SET

LDO VIO18 Operation Enable SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 830 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001CB6

Description

LDO_VIO18_OP_EN_CLR

LDO VIO18 Operation Enable CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

18

17

00001CB8

Description

LDO_VIO18_OP_CFG

LDO VIO18 Operation Config

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

Name Type Reset

2 1 0 RG_LD RG_LD RG_LD O_VIO O_VIO O_VIO 18_HW 18_HW 18_HW 2_OP_ 1_OP_ 0_OP_ CFG CFG CFG RW RW RW 0

Bit(s) 2

Name RG_LDO_VIO18_HW2_OP_CFG

1

RG_LDO_VIO18_HW1_OP_CFG

0

RG_LDO_VIO18_HW0_OP_CFG

MediaTek Proprietary and Confidential.

16

0

0

Description hw_ctrl[2] OPERATION CONFIG HW1: SRCLKEN2/PMRC_EN[2] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low) hw_ctrl[1] OPERATION CONFIG HW1: SRCLKEN1/PMRC_EN[1] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low) hw_ctrl[0] OPERATION CONFIG HW0: SRCLKEN0/PMRC_EN[0] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low)

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 831 of 1067

MT6359 PMIC Datasheet Confidential A 00001CBA

LDO_VIO18_OP_CFG_SET

LDO VIO18 Operation Config SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001CBC

Description

LDO_VIO18_OP_CFG_CLR

LDO VIO18 Operation Config CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

17

00001CBE

Description

LDO_VEMC_CON0

LDO VEMC Control 0

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

Name Type Reset

1 0 RG_LD RG_LD O_VEM O_VEM C_LP C_EN RW RW 0

Bit(s) 1

Name RG_LDO_VEMC_LP

0

RG_LDO_VEMC_EN

MediaTek Proprietary and Confidential.

16

1

Description SW enter low power mode Valid once RG_LDO_VEMC_SW_OP_EN = 1'b1. 1'b0: No LP 1'b1: LP SW enable control Valid once RG_LDO_VEMC_SW_OP_EN = 1'b1. 1'b0: Off 1'b1: On

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 832 of 1067

MT6359 PMIC Datasheet Confidential A 00001CC0

LDO_VEMC_CON1

LDO VEMC Control 1

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

Bit

15

14

13

12

11

10

9

8

7

Name Type Reset Bit(s) 6

Name RG_LDO_VEMC_OC_TSEL

RG_LDO_VEMC_OC_MODE

4

RG_LDO_VEMC_OCFB_EN

2

RG_LDO_VEMC_ULP

LDO_VEMC_MON

0

30

29

28

27

26

25

24

23

22

Bit

15

14

13

12

11

10

9

8

7

6

Name Type Reset

21

DA_VEMC_L_STB

3

DA_VEMC_L_EN

MediaTek Proprietary and Confidential.

17

16

3

2

1

0

RG_LD RG_LDO_VEMC O_VEM _STBTD C_ULP RW

0

0

RW 1

0

20

19

18

17

16

5 4 3 2 1 0 DA_VE DA_VE DA_VE DA_VE DA_VE DA_VE MC_OC MC_L_ MC_L_ MC_B_ MC_B_ MC_B_ FB_EN STB EN LP STB EN RO RO RO RO RO RO 0

4

18

00000000

31

Name DA_VEMC_OCFB_EN

19

LDO VEMC Monitor

Bit Name Type Reset

Bit(s) 5

20

Description Selects VEMC OC debounce time 1'b0: 60 us 1'b1: 120 us Selects VEMC OCFB/OC shutdown 1'b0: OCFB 1'b1: OC shutdown Enables VEMC OCFB/OC shutdown function 1'b0: Disable 1'b1: Enable Selects VEMC LP/ULP when entering low power mode 1'b0: No ULP 1'b1: ULP Selects VEMC soft start time 2'b00: 60 us 2'b01: 240 us 2'b10: 480 us 2'b11: 960 us

RG_LDO_VEMC_STBTD

00001CC2

21

6 5 4 RG_LD RG_LD RG_LD O_VEM O_VEM O_VEM C_OC_ C_OC_ C_OCF TSEL MODE B_EN RW RW RW 0

5

1:0

00009C02 22

0

0

0

0

0

Description VEMC OCFB status 1'b0: OCFB not activated 1'b1: OCFB activated VEMC ULP soft-start status 1'b0: STB not ready 1'b1: STB ready VEMC ULP enable status 1'b0: Disable

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 833 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

2

DA_VEMC_B_LP

1

DA_VEMC_B_STB

0

DA_VEMC_B_EN

00001CC4

Description 1'b1: Enable VEMC low power mode status 1'b0: Normal mode 1'b1: Low power mode VEMC NM soft start status 1'b0: STB not ready 1'b1: STB ready VEMC NM enable status 1'b0: Disable 1'b1: Enable

LDO_VEMC_OP_EN

LDO VEMC Operation Enable

00008000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

Name

Type Reset Bit(s) 2

Name RG_LDO_VEMC_HW2_OP_EN

1

RG_LDO_VEMC_HW1_OP_EN

0

RG_LDO_VEMC_HW0_OP_EN

00001CC6

18

17

16

2 1 0 RG_LD RG_LD RG_LD O_VEM O_VEM O_VEM C_HW2 C_HW1 C_HW0 _OP_E _OP_E _OP_E N N N RW RW RW 0

0

0

Description hw_ctrl[2] OPERATION ENABLE HW1: SRCLKEN2/PMRC_EN[2] 1'b0: Disable 1'b1: Enable hw_ctrl[1] OPERATION ENABLE HW1: SRCLKEN1/PMRC_EN[1] 1'b0: Disable 1'b1: Enable hw_ctrl[0] OPERATION ENABLE HW0: SRCLKEN0/PMRC_EN[0] 1'b0: Disable 1'b1: Enable

LDO_VEMC_OP_EN_SET

LDO VEMC Operation Enable SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 834 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001CC8

Description

LDO_VEMC_OP_EN_CLR

LDO VEMC Operation Enable CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

18

17

00001CCA

Description

LDO_VEMC_OP_CFG

LDO VEMC Operation Config

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

Name Type Reset

2 1 0 RG_LD RG_LD RG_LD O_VEM O_VEM O_VEM C_HW2 C_HW1 C_HW0 _OP_CF _OP_CF _OP_C G G FG RW RW RW 0

Bit(s) 2

Name RG_LDO_VEMC_HW2_OP_CFG

1

RG_LDO_VEMC_HW1_OP_CFG

0

RG_LDO_VEMC_HW0_OP_CFG

MediaTek Proprietary and Confidential.

16

0

0

Description hw_ctrl[2] OPERATION CONFIG HW1: SRCLKEN2/PMRC_EN[2] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low) hw_ctrl[1] OPERATION CONFIG HW1: SRCLKEN1/PMRC_EN[1] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low) hw_ctrl[0] OPERATION CONFIG HW0: SRCLKEN0/PMRC_EN[0] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low)

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 835 of 1067

MT6359 PMIC Datasheet Confidential A 00001CCC

LDO_VEMC_OP_CFG_SET

LDO VEMC Operation Config SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001CCE

Description

LDO_VEMC_OP_CFG_CLR

LDO VEMC Operation Config CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

17

00001CD0

Description

LDO_VSIM1_CON0

LDO VSIM1 Control 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

Name Type Reset

1 0 RG_LD RG_LD O_VSI O_VSI M1_LP M1_EN RW RW 0

Bit(s) 1

Name RG_LDO_VSIM1_LP

0

RG_LDO_VSIM1_EN

MediaTek Proprietary and Confidential.

16

0

Description SW enter low power mode Valid once RG_LDO_VSIM1_SW_OP_EN = 1'b1. 1'b0: No LP 1'b1: LP SW enable control Valid once RG_LDO_VSIM1_SW_OP_EN = 1'b1. 1'b0: Off 1'b1: On

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 836 of 1067

MT6359 PMIC Datasheet Confidential A 00001CD2

LDO_VSIM1_CON1

LDO VSIM1 Control 1

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

Bit

15

14

13

12

11

10

9

8

7

Name Type Reset Bit(s) 6

Name RG_LDO_VSIM1_OC_TSEL

RG_LDO_VSIM1_OC_MODE

4

RG_LDO_VSIM1_OCFB_EN

2

RG_LDO_VSIM1_ULP

LDO_VSIM1_MON

0

30

29

28

27

26

25

24

23

22

Bit

15

14

13

12

11

10

9

8

7

6

Name Type Reset

21

DA_VSIM1_L_STB

3

DA_VSIM1_L_EN

MediaTek Proprietary and Confidential.

17

16

2 1 0 RG_LD O_VSI RG_LDO_VSIM M1_UL 1_STBTD P RW RW

0

0

1

0

20

19

18

17

16

5 4 3 2 1 0 DA_VSI DA_VSI DA_VSI DA_VSI DA_VSI DA_VSI M1_OC M1_L_ M1_L_ M1_B_ M1_B_ M1_B_ FB_EN STB EN LP STB EN RO RO RO RO RO RO 0

4

3

18

00000000

31

Name DA_VSIM1_OCFB_EN

19

LDO VSIM1 Monitor

Bit Name Type Reset

Bit(s) 5

20

Description Selects VSIM1 OC debounce time 1'b0: 60 us 1'b1: 120 us Selects VSIM1 OCFB/OC shutdown 1'b0: OCFB 1'b1: OC shutdown Enables VSIM1 OCFB/OC shutdown function 1'b0: Disable 1'b1: Enable Selects VSIM1 LP/ULP when entering low power mode 1'b0: No ULP 1'b1: ULP Selects VSIM1 soft start time 2'b00: 120 us 2'b01: 240 us 2'b10: 480 us 2'b11: 960 us

RG_LDO_VSIM1_STBTD

00001CD4

21

6 5 4 RG_LD RG_LD RG_LD O_VSI O_VSI O_VSI M1_OC M1_OC M1_OC _TSEL _MODE FB_EN RW RW RW 0

5

1:0

00009C02 22

0

0

0

0

0

Description VSIM1 OCFB status 1'b0: OCFB not activated 1'b1: OCFB activated VSIM1 ULP soft-start status 1'b0: STB not ready 1'b1: STB ready VSIM1 ULP enable status 1'b0: Disable

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 837 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

2

DA_VSIM1_B_LP

1

DA_VSIM1_B_STB

0

DA_VSIM1_B_EN

00001CD6

Description 1'b1: Enable VSIM1 low power mode status 1'b0: Normal mode 1'b1: Low power mode VSIM1 NM soft start status 1'b0: STB not ready 1'b1: STB ready VSIM1 NM enable status 1'b0: Disable 1'b1: Enable

LDO_VSIM1_OP_EN

LDO VSIM1 Operation Enable

00008000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

Name

Type Reset Bit(s) 2

Name RG_LDO_VSIM1_HW2_OP_EN

1

RG_LDO_VSIM1_HW1_OP_EN

0

RG_LDO_VSIM1_HW0_OP_EN

00001CD8

18

17

16

2 1 0 RG_LD RG_LD RG_LD O_VSI O_VSI O_VSI M1_H M1_H M1_H W2_OP W1_OP W0_OP _EN _EN _EN RW RW RW 0

0

0

Description hw_ctrl[2] OPERATION ENABLE HW1: SRCLKEN2/PMRC_EN[2] 1'b0: Disable 1'b1: Enable hw_ctrl[1] OPERATION ENABLE HW1: SRCLKEN1/PMRC_EN[1] 1'b0: Disable 1'b1: Enable hw_ctrl[0] OPERATION ENABLE HW0: SRCLKEN0/PMRC_EN[0] 1'b0: Disable 1'b1: Enable

LDO_VSIM1_OP_EN_SET

LDO VSIM1 Operation Enable SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 838 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001CDA

Description

LDO_VSIM1_OP_EN_CLR

LDO VSIM1 Operation Enable CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

18

17

00001CDC

Description

LDO_VSIM1_OP_CFG

LDO VSIM1 Operation Config

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

Name Type Reset

2 1 0 RG_LD RG_LD RG_LD O_VSI O_VSI O_VSI M1_H M1_H M1_H W2_OP W1_OP W0_OP _CFG _CFG _CFG RW RW RW 0

Bit(s) 2

Name RG_LDO_VSIM1_HW2_OP_CFG

1

RG_LDO_VSIM1_HW1_OP_CFG

0

RG_LDO_VSIM1_HW0_OP_CFG

MediaTek Proprietary and Confidential.

16

0

0

Description hw_ctrl[2] OPERATION CONFIG HW1: SRCLKEN2/PMRC_EN[2] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low) hw_ctrl[1] OPERATION CONFIG HW1: SRCLKEN1/PMRC_EN[1] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low) hw_ctrl[0] OPERATION CONFIG HW0: SRCLKEN0/PMRC_EN[0] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low)

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 839 of 1067

MT6359 PMIC Datasheet Confidential A 00001CDE

LDO_VSIM1_OP_CFG_SET

LDO VSIM1 Operation Config SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001CE0

Description

LDO_VSIM1_OP_CFG_CLR

LDO VSIM1 Operation Config CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

17

00001CE2

Description

LDO_VSIM2_CON0

LDO VSIM2 Control 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

Name Type Reset

1 0 RG_LD RG_LD O_VSI O_VSI M2_LP M2_EN RW RW 0

Bit(s) 1

Name RG_LDO_VSIM2_LP

0

RG_LDO_VSIM2_EN

MediaTek Proprietary and Confidential.

16

0

Description SW enter low power mode Valid once RG_LDO_VSIM2_SW_OP_EN = 1'b1. 1'b0: No LP 1'b1: LP SW enable control Valid once RG_LDO_VSIM2_SW_OP_EN = 1'b1. 1'b0: Off 1'b1: On

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 840 of 1067

MT6359 PMIC Datasheet Confidential A 00001CE4

LDO_VSIM2_CON1

LDO VSIM2 Control 1

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

Bit

15

14

13

12

11

10

9

8

7

Name Type Reset Bit(s) 6

Name RG_LDO_VSIM2_OC_TSEL

RG_LDO_VSIM2_OC_MODE

4

RG_LDO_VSIM2_OCFB_EN

2

RG_LDO_VSIM2_ULP

LDO_VSIM2_MON

0

30

29

28

27

26

25

24

23

22

Bit

15

14

13

12

11

10

9

8

7

6

Name Type Reset

21

DA_VSIM2_L_STB

3

DA_VSIM2_L_EN

MediaTek Proprietary and Confidential.

17

16

2 1 0 RG_LD O_VSI RG_LDO_VSIM M2_UL 2_STBTD P RW RW

0

0

1

0

20

19

18

17

16

5 4 3 2 1 0 DA_VSI DA_VSI DA_VSI DA_VSI DA_VSI DA_VSI M2_OC M2_L_ M2_L_ M2_B_ M2_B_ M2_B_ FB_EN STB EN LP STB EN RO RO RO RO RO RO 0

4

3

18

00000000

31

Name DA_VSIM2_OCFB_EN

19

LDO VSIM2 Monitor

Bit Name Type Reset

Bit(s) 5

20

Description Selects VSIM2 OC debounce time 1'b0: 60 us 1'b1: 120 us Selects VSIM2 OCFB/OC shutdown 1'b0: OCFB 1'b1: OC shutdown Enables VSIM2 OCFB/OC shutdown function 1'b0: Disable 1'b1: Enable Selects VSIM2 LP/ULP when entering low power mode 1'b0: No ULP 1'b1: ULP Selects VSIM2 soft start time 2'b00: 120 us 2'b01: 240 us 2'b10: 480 us 2'b11: 960 us

RG_LDO_VSIM2_STBTD

00001CE6

21

6 5 4 RG_LD RG_LD RG_LD O_VSI O_VSI O_VSI M2_OC M2_OC M2_OC _TSEL _MODE FB_EN RW RW RW 0

5

1:0

00009C02 22

0

0

0

0

0

Description VSIM2 OCFB status 1'b0: OCFB not activated 1'b1: OCFB activated VSIM2 ULP soft-start status 1'b0: STB not ready 1'b1: STB ready VSIM2 ULP enable status 1'b0: Disable

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 841 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

2

DA_VSIM2_B_LP

1

DA_VSIM2_B_STB

0

DA_VSIM2_B_EN

00001CE8

Description 1'b1: Enable VSIM2 low power mode status 1'b0: Normal mode 1'b1: Low power mode VSIM2 NM soft start status 1'b0: STB not ready 1'b1: STB ready VSIM2 NM enable status 1'b0: Disable 1'b1: Enable

LDO_VSIM2_OP_EN

LDO VSIM2 Operation Enable

00008000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

Name

Type Reset Bit(s) 2

Name RG_LDO_VSIM2_HW2_OP_EN

1

RG_LDO_VSIM2_HW1_OP_EN

0

RG_LDO_VSIM2_HW0_OP_EN

00001CEA

18

17

16

2 1 0 RG_LD RG_LD RG_LD O_VSI O_VSI O_VSI M2_H M2_H M2_H W2_OP W1_OP W0_OP _EN _EN _EN RW RW RW 0

0

0

Description hw_ctrl[2] OPERATION ENABLE HW1: SRCLKEN2/PMRC_EN[2] 1'b0: Disable 1'b1: Enable hw_ctrl[1] OPERATION ENABLE HW1: SRCLKEN1/PMRC_EN[1] 1'b0: Disable 1'b1: Enable hw_ctrl[0] OPERATION ENABLE HW0: SRCLKEN0/PMRC_EN[0] 1'b0: Disable 1'b1: Enable

LDO_VSIM2_OP_EN_SET

LDO VSIM2 Operation Enable SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

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Page 842 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001CEC

Description

LDO_VSIM2_OP_EN_CLR

LDO VSIM2 Operation Enable CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

18

17

00001CEE

Description

LDO_VSIM2_OP_CFG

LDO VSIM2 Operation Config

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

Name Type Reset

2 1 0 RG_LD RG_LD RG_LD O_VSI O_VSI O_VSI M2_H M2_H M2_H W2_OP W1_OP W0_OP _CFG _CFG _CFG RW RW RW 0

Bit(s) 2

Name RG_LDO_VSIM2_HW2_OP_CFG

1

RG_LDO_VSIM2_HW1_OP_CFG

0

RG_LDO_VSIM2_HW0_OP_CFG

MediaTek Proprietary and Confidential.

16

0

0

Description hw_ctrl[2] OPERATION CONFIG HW1: SRCLKEN2/PMRC_EN[2] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low) hw_ctrl[1] OPERATION CONFIG HW1: SRCLKEN1/PMRC_EN[1] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low) hw_ctrl[0] OPERATION CONFIG HW0: SRCLKEN0/PMRC_EN[0] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low)

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 843 of 1067

MT6359 PMIC Datasheet Confidential A 00001CF0

LDO_VSIM2_OP_CFG_SET

LDO VSIM2 Operation Config SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001CF2

Description

LDO_VSIM2_OP_CFG_CLR

LDO VSIM2 Operation Config CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001D00

Description

LDO_GNR3_DSN_ID

LDO_GNR3 Design ID register

0000E100

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001D02

Description

LDO_GNR3_DSN_REV0

LDO_GNR3 Design Revision Register 0

00001000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

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Page 844 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001D04

Description

LDO_GNR3_DSN_DBI

LDO_GNR3 Design Bank Information Register

00000002

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001D06

Description

LDO_GNR3_DSN_DXI

LDO_GNR3 Design Extra Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001D08

Description

LDO_VUSB_CON0

LDO VUSB Control 0

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

Name Type Reset Bit(s) 1

0

0 RG_LD RG_LD O_VUS O_VUS B_EN_ B_LP 0 RW RW 0

Name RG_LDO_VUSB_LP

RG_LDO_VUSB_EN_0

MediaTek Proprietary and Confidential.

16

1

Description SW enter low power mode Valid once RG_LDO_VUSB_SW_OP_EN = 1'b1. 1'b0: No LP 1'b1: LP SW enable control Valid once RG_LDO_VUSB_SW_OP_EN = 1'b1. 1'b0: Off 1'b1: On

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 845 of 1067

MT6359 PMIC Datasheet Confidential A 00001D0A

LDO_VUSB_CON1

LDO VUSB Control 1

00009C03

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6 RG_LD O_VUS B_OC_ TSEL RW

5 RG_LD O_VUS B_OC_ MODE RW

4 RG_LD O_VUS B_OCF B_EN RW

3

2

1

0

0

0

0

Name Type Reset Bit(s) 6

Name RG_LDO_VUSB_OC_TSEL

5

RG_LDO_VUSB_OC_MODE

4

RG_LDO_VUSB_OCFB_EN

2

RG_LDO_VUSB_ULP

1:0

LDO_VUSB_MON 30

29

28

27

26

25

24

23

22

Bit

15

14

13

12

11

10

9

8

7

6

Name Type Reset

21

DA_VUSB_L_STB

3

DA_VUSB_L_EN

MediaTek Proprietary and Confidential.

1

20

19

18

17

16

5 4 3 2 1 0 DA_VU DA_VU DA_VU DA_VU DA_VU DA_VU SB_OCF SB_L_S SB_L_E SB_B_L SB_B_S SB_B_E B_EN TB N P TB N RO RO RO RO RO RO 0

4

RW 1

00000000

31

Name DA_VUSB_OCFB_EN

0

LDO VUSB Monitor

Bit Name Type Reset

Bit(s) 5

RW

Description Selects VUSB OC debounce time 1'b0: 60 us 1'b1: 120 us Selects VUSB OCFB/OC shutdown 1'b0: OCFB 1'b1: OC shutdown Enables VUSB OCFB/OC shutdown function 1'b0: Disable 1'b1: Enable Selects VUSB LP/ULP when entering low power mode 1'b0: No ULP 1'b1: ULP Selects VUSB soft start time 2'b00: 120 us 2'b01: 240 us 2'b10: 480 us 2'b11: 960 us

RG_LDO_VUSB_STBTD

00001D0C

RG_LD RG_LDO_VUSB O_VUS _STBTD B_ULP

0

0

0

0

0

Description VUSB OCFB status 1'b0: OCFB not activated 1'b1: OCFB activated VUSB ULP soft-start status 1'b0: STB not ready 1'b1: STB ready VUSB ULP enable status 1'b0: Disable

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 846 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

2

DA_VUSB_B_LP

1

DA_VUSB_B_STB

0

DA_VUSB_B_EN

00001D0E

Description 1'b1: Enable VUSB low power mode status 1'b0: Normal mode 1'b1: Low power mode VUSB NM soft start status 1'b0: STB not ready 1'b1: STB ready VUSB NM enable status 1'b0: Disable 1'b1: Enable

LDO_VUSB_OP_EN

LDO VUSB Operation Enable

00008000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

Name

Type Reset Bit(s) 2

Name RG_LDO_VUSB_HW2_OP_EN

1

RG_LDO_VUSB_HW1_OP_EN

0

RG_LDO_VUSB_HW0_OP_EN

00001D10

18

17

16

2 1 0 RG_LD RG_LD RG_LD O_VUS O_VUS O_VUS B_HW2 B_HW1 B_HW0 _OP_E _OP_E _OP_E N N N RW RW RW 0

0

0

Description hw_ctrl[2] OPERATION ENABLE HW1: SRCLKEN2/PMRC_EN[2] 1'b0: Disable 1'b1: Enable hw_ctrl[1] OPERATION ENABLE HW1: SRCLKEN1/PMRC_EN[1] 1'b0: Disable 1'b1: Enable hw_ctrl[0] OPERATION ENABLE HW0: SRCLKEN0/PMRC_EN[0] 1'b0: Disable 1'b1: Enable

LDO_VUSB_OP_EN_SET

LDO VUSB Operation Enable SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 847 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001D12

Description

LDO_VUSB_OP_EN_CLR

LDO VUSB Operation Enable CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

18

17

00001D14

Description

LDO_VUSB_OP_CFG

LDO VUSB Operation Config

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

Name Type Reset

2 1 0 RG_LD RG_LD RG_LD O_VUS O_VUS O_VUS B_HW2 B_HW1 B_HW0 _OP_CF _OP_CF _OP_C G G FG RW RW RW 0

Bit(s) 2

Name RG_LDO_VUSB_HW2_OP_CFG

1

RG_LDO_VUSB_HW1_OP_CFG

0

RG_LDO_VUSB_HW0_OP_CFG

MediaTek Proprietary and Confidential.

16

0

0

Description hw_ctrl[2] OPERATION CONFIG HW1: SRCLKEN2/PMRC_EN[2] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low) hw_ctrl[1] OPERATION CONFIG HW1: SRCLKEN1/PMRC_EN[1] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low) hw_ctrl[0] OPERATION CONFIG HW0: SRCLKEN0/PMRC_EN[0] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low)

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 848 of 1067

MT6359 PMIC Datasheet Confidential A 00001D16

LDO_VUSB_OP_CFG_SET

LDO VUSB Operation Config SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001D18

Description

LDO_VUSB_OP_CFG_CLR

LDO VUSB Operation Config CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001D1A Bit Name Type Reset

LDO_VUSB_MULTI_SW 31

15 RG_LD O_VUS Name B_EN_ 1 RW Type

Bit

Reset Bit(s) 15

Description

LDO VUSB Multi-SW User

00008000

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

Name RG_LDO_VUSB_EN_1

MediaTek Proprietary and Confidential.

Description Enable control (SW mode) Valid once RG_LDO_VUSB_SW_OP_EN = 1'b1. 1'b0: Off 1'b1: On

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 849 of 1067

MT6359 PMIC Datasheet Confidential A 00001D1C

LDO_VRFCK_CON0

LDO VRFCK Control 0

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

Name Type Reset

17

16

1 0 RG_LD RG_LD O_VRF O_VRF CK_LP CK_EN RW RW 0

Bit(s) 1

Name RG_LDO_VRFCK_LP

0

RG_LDO_VRFCK_EN

00001D1E

1

Description SW enter low power mode Valid once RG_LDO_VRFCK_SW_OP_EN = 1'b1. 1'b0: No LP 1'b1: LP SW enable control Valid once RG_LDO_VRFCK_SW_OP_EN = 1'b1. 1'b0: Off 1'b1: On

LDO_VRFCK_CON1

LDO VRFCK Control 1

00009C02

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6 RG_LD O_VRF CK_OC _TSEL RW

5 RG_LD O_VRF CK_OC _MODE RW

4 RG_LD O_VRF CK_OC FB_EN RW

3

2

1

0

0

0

0

Name Type Reset Bit(s) 6

Name RG_LDO_VRFCK_OC_TSEL

5

RG_LDO_VRFCK_OC_MODE

4

RG_LDO_VRFCK_OCFB_EN

2

RG_LDO_VRFCK_ULP

1:0

RG_LDO_VRFCK_STBTD

MediaTek Proprietary and Confidential.

RG_LD RG_LDO_VRFC O_VRF K_STBTD CK_ULP RW 0

RW 1

0

Description Selects VRFCK OC debounce time 1'b0: 60 us 1'b1: 120 us Selects VRFCK OCFB/OC shutdown 1'b0: OCFB 1'b1: OC shutdown Enables VRFCK OCFB/OC shutdown function 1'b0: Disable 1'b1: Enable Selects VRFCK LP/ULP when entering low power mode 1'b0: No ULP 1'b1: ULP Selects VRFCK soft start time 2'b00: 120 us 2'b01: 240 us 2'b10: 480 us 2'b11: 960 us

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 850 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001D20

Description

LDO_VRFCK_MON

LDO VRFCK Monitor

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

Bit

15

14

13

12

11

10

9

8

7

6

Name Type Reset Bit(s) 5

Name DA_VRFCK_OCFB_EN

4

DA_VRFCK_L_STB

3

DA_VRFCK_L_EN

2

DA_VRFCK_B_LP

1

DA_VRFCK_B_STB

0

DA_VRFCK_B_EN

00001D22

21

20

19

0

0

0

0

0

16

18

17

0

Description VRFCK OCFB status 1'b0: OCFB not activated 1'b1: OCFB activated VRFCK ULP soft-start status 1'b0: STB not ready 1'b1: STB ready VRFCK ULP enable status 1'b0: Disable 1'b1: Enable VRFCK low power mode status 1'b0: Normal mode 1'b1: Low power mode VRFCK NM soft start status 1'b0: STB not ready 1'b1: STB ready VRFCK NM enable status 1'b0: Disable 1'b1: Enable

LDO_VRFCK_OP_EN

LDO VRFCK Operation Enable

00008000

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

Name

Type Reset Name RG_LDO_VRFCK_HW2_OP_EN

16

2 1 0 RG_LD RG_LD RG_LD O_VRF O_VRF O_VRF CK_HW CK_HW CK_HW 2_OP_E 1_OP_E 0_OP_ N N EN RW RW RW 0

MediaTek Proprietary and Confidential.

17

5 4 3 2 1 0 DA_VR DA_VR DA_VR DA_VR DA_VR DA_VR FCK_O FCK_L_ FCK_L_ FCK_B_ FCK_B_ FCK_B_ CFB_EN STB EN LP STB EN RO RO RO RO RO RO

Bit Name Type Reset

Bit(s) 2

18

0

0

Description hw_ctrl[2] OPERATION ENABLE HW1: SRCLKEN2/PMRC_EN[2] 1'b0: Disable

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 851 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

1

RG_LDO_VRFCK_HW1_OP_EN

0

RG_LDO_VRFCK_HW0_OP_EN

00001D24

Description 1'b1: Enable hw_ctrl[1] OPERATION ENABLE HW1: SRCLKEN1/PMRC_EN[1] 1'b0: Disable 1'b1: Enable hw_ctrl[0] OPERATION ENABLE HW0: SRCLKEN0/PMRC_EN[0] 1'b0: Disable 1'b1: Enable

LDO_VRFCK_OP_EN_SET

LDO VRFCK Operation Enable SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001D26

Description

LDO_VRFCK_OP_EN_CLR

LDO VRFCK Operation Enable CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

18

17

00001D28

Description

LDO_VRFCK_OP_CFG

LDO VRFCK Operation Config

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

Name

Type Reset

MediaTek Proprietary and Confidential.

2 1 0 RG_LD RG_LD RG_LD O_VRF O_VRF O_VRF CK_HW CK_HW CK_HW 2_OP_ 1_OP_ 0_OP_ CFG CFG CFG RW RW RW 0

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

16

0

0

Page 852 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 2

Name RG_LDO_VRFCK_HW2_OP_CFG

1

RG_LDO_VRFCK_HW1_OP_CFG

0

RG_LDO_VRFCK_HW0_OP_CFG

00001D2A

Description hw_ctrl[2] OPERATION CONFIG HW1: SRCLKEN2/PMRC_EN[2] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low) hw_ctrl[1] OPERATION CONFIG HW1: SRCLKEN1/PMRC_EN[1] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low) hw_ctrl[0] OPERATION CONFIG HW0: SRCLKEN0/PMRC_EN[0] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low)

LDO_VRFCK_OP_CFG_SET

LDO VRFCK Operation Config SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001D2C

Description

LDO_VRFCK_OP_CFG_CLR

LDO VRFCK Operation Config CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 853 of 1067

MT6359 PMIC Datasheet Confidential A 00001D2E

LDO_VBBCK_CON0

LDO VBBCK Control 0

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

Name Type Reset Name RG_LDO_VBBCK_LP

0

RG_LDO_VBBCK_EN

00001D30

1 0 RG_LD RG_LD O_VBB O_VBB CK_LP CK_EN RW RW

LDO_VBBCK_CON1

LDO VBBCK Control 1

00009C02

31

30

29

28

27

26

25

24

23

22

Bit

15

14

13

12

11

10

9

8

7

6 RG_LD O_VBB CK_OC _TSEL RW

Name Type Reset

0

Name RG_LDO_VBBCK_OC_TSEL

5

RG_LDO_VBBCK_OC_MODE

4

RG_LDO_VBBCK_OCFB_EN

2

RG_LDO_VBBCK_ULP

RG_LDO_VBBCK_STBTD

MediaTek Proprietary and Confidential.

1

Description SW enter low power mode Valid once RG_LDO_VBBCK_SW_OP_EN = 1'b1. 1'b0: No LP 1'b1: LP SW enable control Valid once RG_LDO_VBBCK_SW_OP_EN = 1'b1. 1'b0: Off 1'b1: On

Bit Name Type Reset

1:0

16

0

Bit(s) 1

Bit(s) 6

17

21

20

5 4 RG_LD RG_LD O_VBB O_VBB CK_OC CK_OC _MODE FB_EN RW RW 0

0

19

18

17

16

3

2

1

0

RG_LD RG_LDO_VBBC O_VBB K_STBTD CK_ULP RW 0

RW 1

0

Description Selects VBBCK OC debounce time 1'b0: 60 us 1'b1: 120 us Selects VBBCK OCFB/OC shutdown 1'b0: OCFB 1'b1: OC shutdown Enables VBBCK OCFB/OC shutdown function 1'b0: Disable 1'b1: Enable Selects VBBCK LP/ULP when entering low power mode 1'b0: No ULP 1'b1: ULP Selects VBBCK soft start time 2'b00: 120 us 2'b01: 240 us 2'b10: 480 us 2'b11: 960 us

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 854 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001D32

Description

LDO_VBBCK_MON

LDO VBBCK Monitor

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

Bit

15

14

13

12

11

10

9

8

7

6

Name Type Reset Bit(s) 5

Name DA_VBBCK_OCFB_EN

4

DA_VBBCK_L_STB

3

DA_VBBCK_L_EN

2

DA_VBBCK_B_LP

1

DA_VBBCK_B_STB

0

DA_VBBCK_B_EN

00001D34

21

20

19

0

0

0

0

0

16

18

17

0

Description VBBCK OCFB status 1'b0: OCFB not activated 1'b1: OCFB activated VBBCK ULP soft-start status 1'b0: STB not ready 1'b1: STB ready VBBCK ULP enable status 1'b0: Disable 1'b1: Enable VBBCK low power mode status 1'b0: Normal mode 1'b1: Low power mode VBBCK NM soft start status 1'b0: STB not ready 1'b1: STB ready VBBCK NM enable status 1'b0: Disable 1'b1: Enable

LDO_VBBCK_OP_EN

LDO VBBCK Operation Enable

00008000

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

Name

Type Reset Name RG_LDO_VBBCK_HW2_OP_EN

16

2 1 0 RG_LD RG_LD RG_LD O_VBB O_VBB O_VBB CK_HW CK_HW CK_HW 2_OP_E 1_OP_E 0_OP_ N N EN RW RW RW 0

MediaTek Proprietary and Confidential.

17

5 4 3 2 1 0 DA_VB DA_VB DA_VB DA_VB DA_VB DA_VB BCK_O BCK_L_ BCK_L_ BCK_B_ BCK_B_ BCK_B CFB_EN STB EN LP STB _EN RO RO RO RO RO RO

Bit Name Type Reset

Bit(s) 2

18

0

0

Description hw_ctrl[2] OPERATION ENABLE HW1: SRCLKEN2/PMRC_EN[2] 1'b0: Disable

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 855 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

1

RG_LDO_VBBCK_HW1_OP_EN

0

RG_LDO_VBBCK_HW0_OP_EN

00001D36

Description 1'b1: Enable hw_ctrl[1] OPERATION ENABLE HW1: SRCLKEN1/PMRC_EN[1] 1'b0: Disable 1'b1: Enable hw_ctrl[0] OPERATION ENABLE HW0: SRCLKEN0/PMRC_EN[0] 1'b0: Disable 1'b1: Enable

LDO_VBBCK_OP_EN_SET

LDO VBBCK Operation Enable SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001D38

Description

LDO_VBBCK_OP_EN_CLR

LDO VBBCK Operation Enable CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

18

17

00001D3A

Description

LDO_VBBCK_OP_CFG

LDO VBBCK Operation Config

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

Name

Type Reset

MediaTek Proprietary and Confidential.

2 1 0 RG_LD RG_LD RG_LD O_VBB O_VBB O_VBB CK_HW CK_HW CK_HW 2_OP_ 1_OP_ 0_OP_ CFG CFG CFG RW RW RW 0

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

16

0

0

Page 856 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 2

Name RG_LDO_VBBCK_HW2_OP_CFG

1

RG_LDO_VBBCK_HW1_OP_CFG

0

RG_LDO_VBBCK_HW0_OP_CFG

00001D3C

LDO_VBBCK_OP_CFG_SET

Bit Name Type Reset

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

Description

LDO_VBBCK_OP_CFG_CLR

LDO VBBCK Operation Config CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

22

21

20

19

18

17

Bit Name Type Reset 4

00000000

30

00001D40

5

LDO VBBCK Operation Config SET

31

00001D3E

6

Description hw_ctrl[2] OPERATION CONFIG HW1: SRCLKEN2/PMRC_EN[2] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low) hw_ctrl[1] OPERATION CONFIG HW1: SRCLKEN1/PMRC_EN[1] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low) hw_ctrl[0] OPERATION CONFIG HW0: SRCLKEN0/PMRC_EN[0] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low)

Description

LDO_VBIF28_CON0 31

30

29

28

LDO VBIF28 Control 0 27

26

25

24

23

00000000

2

3Bit

Name Type Reset

MediaTek Proprietary and Confidential.

1 0 RG_LD RG_LD O_VBIF O_VBIF 28_LP 28_EN RW RW 0

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

16

0

Page 857 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 1

Name RG_LDO_VBIF28_LP

0

RG_LDO_VBIF28_EN

00001D42

Description SW enter low power mode Valid once RG_LDO_VBIF28_SW_OP_EN = 1'b1. 1'b0: No LP 1'b1: LP SW enable control Valid once RG_LDO_VBIF28_SW_OP_EN = 1'b1. 1'b0: Off 1'b1: On

LDO_VBIF28_CON1

LDO VBIF28 Control 1

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

Bit

15

14

13

12

11

10

9

8

7

Name Type Reset Bit(s) 6

Name RG_LDO_VBIF28_OC_TSEL

RG_LDO_VBIF28_OC_MODE

4

RG_LDO_VBIF28_OCFB_EN

2

RG_LDO_VBIF28_ULP

RG_LDO_VBIF28_STBTD

MediaTek Proprietary and Confidential.

21

20

6 5 4 RG_LD RG_LD RG_LD O_VBIF O_VBIF O_VBIF 28_OC 28_OC 28_OCF _TSEL _MODE B_EN RW RW RW 0

5

1:0

00009C01 22

0

0

19

18

17

16

3

2

1

0

RG_LD RG_LDO_VBIF2 O_VBIF 8_STBTD 28_ULP RW 0

RW 0

1

Description Selects VBIF28 OC debounce time 1'b0: 60 us 1'b1: 120 us Selects VBIF28 OCFB/OC shutdown 1'b0: OCFB 1'b1: OC shutdown Enables VBIF28 OCFB/OC shutdown function 1'b0: Disable 1'b1: Enable Selects VBIF28 LP/ULP when entering low power mode 1'b0: No ULP 1'b1: ULP Selects VBIF28 soft start time 2'b00: 120 us 2'b01: 240 us 2'b10: 480 us 2'b11: 960 us

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 858 of 1067

MT6359 PMIC Datasheet Confidential A 00001D44

LDO_VBIF28_MON

LDO VBIF28 Monitor

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

Bit

15

14

13

12

11

10

9

8

7

6

Name Type Reset Bit(s) 5

Name DA_VBIF28_OCFB_EN

4

DA_VBIF28_L_STB

3

DA_VBIF28_L_EN

2

DA_VBIF28_B_LP

1

DA_VBIF28_B_STB

0

DA_VBIF28_B_EN

00001D46

21

20

19

18

16

5 4 3 2 1 0 DA_VBI DA_VBI DA_VBI DA_VBI DA_VBI DA_VB F28_OC F28_L_ F28_L_ F28_B_ F28_B_ IF28_B FB_EN STB EN LP STB _EN RO RO RO RO RO RO 0

0

0

0

0

18

17

0

Description VBIF28 OCFB status 1'b0: OCFB not activated 1'b1: OCFB activated VBIF28 ULP soft-start status 1'b0: STB not ready 1'b1: STB ready VBIF28 ULP enable status 1'b0: Disable 1'b1: Enable VBIF28 low power mode status 1'b0: Normal mode 1'b1: Low power mode VBIF28 NM soft start status 1'b0: STB not ready 1'b1: STB ready VBIF28 NM enable status 1'b0: Disable 1'b1: Enable

LDO_VBIF28_OP_EN

LDO VBIF28 Operation Enable

00008000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

Name Type Reset Bit(s) 2

Name RG_LDO_VBIF28_HW2_OP_EN

1

RG_LDO_VBIF28_HW1_OP_EN

16

2 1 0 RG_LD RG_LD RG_LD O_VBIF O_VBIF O_VBIF 28_HW 28_HW 28_HW 2_OP_E 1_OP_E 0_OP_ N N EN RW RW RW 0

MediaTek Proprietary and Confidential.

17

0

0

Description hw_ctrl[2] OPERATION ENABLE HW1: SRCLKEN2/PMRC_EN[2] 1'b0: Disable 1'b1: Enable hw_ctrl[1] OPERATION ENABLE HW1: SRCLKEN1/PMRC_EN[1]

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 859 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

0

Name

Description 1'b0: Disable 1'b1: Enable hw_ctrl[0] OPERATION ENABLE HW0: SRCLKEN0/PMRC_EN[0] 1'b0: Disable 1'b1: Enable

RG_LDO_VBIF28_HW0_OP_EN

00001D48

LDO_VBIF28_OP_EN_SET

LDO VBIF28 Operation Enable SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001D4A

Description

LDO_VBIF28_OP_EN_CLR

LDO VBIF28 Operation Enable CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

18

17

00001D4C

Description

LDO_VBIF28_OP_CFG

LDO VBIF28 Operation Config

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

Name

Type Reset Bit(s) 2

2 1 0 RG_LD RG_LD RG_LD O_VBIF O_VBIF O_VBIF 28_HW 28_HW 28_HW 2_OP_ 1_OP_ 0_OP_ CFG CFG CFG RW RW RW 0

Name RG_LDO_VBIF28_HW2_OP_CFG

MediaTek Proprietary and Confidential.

16

0

0

Description hw_ctrl[2] OPERATION CONFIG HW1: SRCLKEN2/PMRC_EN[2]

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 860 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

1

RG_LDO_VBIF28_HW1_OP_CFG

0

RG_LDO_VBIF28_HW0_OP_CFG

00001D4E

Description 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low) hw_ctrl[1] OPERATION CONFIG HW1: SRCLKEN1/PMRC_EN[1] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low) hw_ctrl[0] OPERATION CONFIG HW0: SRCLKEN0/PMRC_EN[0] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low)

LDO_VBIF28_OP_CFG_SET

LDO VBIF28 Operation Config SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001D50

Description

LDO_VBIF28_OP_CFG_CLR

LDO VBIF28 Operation Config CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001D52

Description

LDO_VIBR_CON0

LDO VIBR Control 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1 RG_LD O_VIBR _LP RW

0 RG_LD O_VIB R_EN RW

0

0

Name Type Reset

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 861 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 1

Name RG_LDO_VIBR_LP

0

RG_LDO_VIBR_EN

00001D54

Description SW enter low power mode Valid once RG_LDO_VIBR_SW_OP_EN = 1'b1. 1'b0: No LP 1'b1: LP SW enable control Valid once RG_LDO_VIBR_SW_OP_EN = 1'b1. 1'b0: Off 1'b1: On

LDO_VIBR_CON1

LDO VIBR Control 1

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

Bit

15

14

13

12

11

10

9

8

7

Name Type Reset Bit(s) 6

Name RG_LDO_VIBR_OC_TSEL

RG_LDO_VIBR_OC_MODE

4

RG_LDO_VIBR_OCFB_EN

2

RG_LDO_VIBR_ULP

LDO_VIBR_MON 30

29

28

27

26

25

24

23

22

Bit

15

14

13

12

11

10

9

8

7

6

MediaTek Proprietary and Confidential.

18

17

16

3

2

1

0

RG_LD RG_LDO_VIBR_ O_VIBR STBTD _ULP RW

0

RW

0

0

18

17

1

00000000

31

Type

0

19

LDO VIBR Monitor

Bit Name Type Reset

Name

20

Description Selects VIBR OC debounce time 1'b0: 60 us 1'b1: 120 us Selects VIBR OCFB/OC shutdown 1'b0: OCFB 1'b1: OC shutdown Enables VIBR OCFB/OC shutdown function 1'b0: Disable 1'b1: Enable Selects VIBR LP/ULP when entering low power mode 1'b0: No ULP 1'b1: ULP Selects VIBR soft start time 2'b00: 60 us 2'b01: 240 us 2'b10: 480 us 2'b11: 960 us

RG_LDO_VIBR_STBTD

00001D56

21

6 5 4 RG_LD RG_LD RG_LD O_VIBR O_VIBR O_VIBR _OC_TS _OC_M _OCFB EL ODE _EN RW RW RW 0

5

1:0

00009C01 22

21

20

19

16

5 4 3 2 1 0 DA_VIB DA_VIB DA_VIB DA_VI DA_VIB DA_VIB R_OCF R_L_ST R_B_ST BR_B_ R_L_EN R_B_LP B_EN B B EN RO RO RO RO RO RO

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 862 of 1067

MT6359 PMIC Datasheet Confidential A Reset Bit(s) 5

Name DA_VIBR_OCFB_EN

4

DA_VIBR_L_STB

3

DA_VIBR_L_EN

2

DA_VIBR_B_LP

1

DA_VIBR_B_STB

0

DA_VIBR_B_EN

00001D58

0

0

0

0

0

Description VIBR OCFB status 1'b0: OCFB not activated 1'b1: OCFB activated VIBR ULP soft-start status 1'b0: STB not ready 1'b1: STB ready VIBR ULP enable status 1'b0: Disable 1'b1: Enable VIBR low power mode status 1'b0: Normal mode 1'b1: Low power mode VIBR NM soft start status 1'b0: STB not ready 1'b1: STB ready VIBR NM enable status 1'b0: Disable 1'b1: Enable

LDO_VIBR_OP_EN

LDO VIBR Operation Enable

00008000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

Name

Type Reset Bit(s) 2

Name RG_LDO_VIBR_HW2_OP_EN

1

RG_LDO_VIBR_HW1_OP_EN

0

RG_LDO_VIBR_HW0_OP_EN

MediaTek Proprietary and Confidential.

0

16

0 RG_LD RG_LD RG_LD O_VIB O_VIBR O_VIBR R_HW0 _HW2_ _HW1_ _OP_E OP_EN OP_EN N RW RW RW 0

Description hw_ctrl[2] OPERATION ENABLE HW1: SRCLKEN2/PMRC_EN[2] 1'b0: Disable 1'b1: Enable hw_ctrl[1] OPERATION ENABLE HW1: SRCLKEN1/PMRC_EN[1] 1'b0: Disable 1'b1: Enable hw_ctrl[0] OPERATION ENABLE HW0: SRCLKEN0/PMRC_EN[0] 1'b0: Disable 1'b1: Enable

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 863 of 1067

MT6359 PMIC Datasheet Confidential A 00001D5A

LDO_VIBR_OP_EN_SET

LDO VIBR Operation Enable SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001D5C

Description

LDO_VIBR_OP_EN_CLR

LDO VIBR Operation Enable CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

18

17

00001D5E

Description

LDO_VIBR_OP_CFG

LDO VIBR Operation Config

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

Name Type Reset

2 1 0 RG_LD RG_LD RG_LD O_VIBR O_VIBR O_VIB _HW2_ _HW1_ R_HW0 OP_CF OP_CF _OP_C G G FG RW RW RW 0

Bit(s) 2

Name RG_LDO_VIBR_HW2_OP_CFG

1

RG_LDO_VIBR_HW1_OP_CFG

16

0

0

Description hw_ctrl[2] OPERATION CONFIG HW1: SRCLKEN2/PMRC_EN[2] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low) hw_ctrl[1] OPERATION CONFIG

EN[1]

0

RG_LDO_VIBR_HW0_OP_CFG

MediaTek Proprietary and Confidential.

1'b0: On (high), off (low) 1'b1: No LP (high), LP (low) hw_ctrl[0] OPERATION CONFIG HW0: SRCLKEN0/PMRC_EN[0] 1'b0: On (high), off (low)

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 864 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001D60

Description 1'b1: No LP (high), LP (low)

LDO_VIBR_OP_CFG_SET

LDO VIBR Operation Config SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001D62

Description

LDO_VIBR_OP_CFG_CLR

LDO VIBR Operation Config CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

17

00001D64

Description

LDO_VIO28_CON0

LDO VIO28 Control 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

Name Type Reset

1 0 RG_LD RG_LD O_VIO O_VIO 28_LP 28_EN RW RW 0

Bit(s) 1

Name RG_LDO_VIO28_LP

0

RG_LDO_VIO28_EN

MediaTek Proprietary and Confidential.

16

0

Description SW enter low power mode Valid once RG_LDO_VIO28_SW_OP_EN = 1'b1. 1'b0: No LP 1'b1: LP SW enable control Valid once RG_LDO_VIO28_SW_OP_EN = 1'b1. 1'b0: Off 1'b1: On

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 865 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001D66

Description

LDO_VIO28_CON1

LDO VIO28 Control 1

00009C01

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

Bit

15

14

13

12

11

10

9

8

7

6 RG_LD O_VIO 28_OC _TSEL RW

Name Type Reset Bit(s) 6

0

Name RG_LDO_VIO28_OC_TSEL

5

RG_LDO_VIO28_OC_MODE

4

RG_LDO_VIO28_OCFB_EN

2

RG_LDO_VIO28_ULP

1:0

LDO_VIO28_MON

0

Bit Name Type Reset

29

28

27

26

25

24

23

22

Bit

15

14

13

12

11

10

9

8

7

6

Name Type Reset

21

DA_VIO28_L_STB

MediaTek Proprietary and Confidential.

17

16

3

2

1

0

RG_LD RG_LDO_VIO2 O_VIO 8_STBTD 28_ULP RW

0

RW

0

0

18

17

1

20

19

16

5 4 3 2 1 0 DA_VI DA_VI DA_VI DA_VI DA_VI DA_VI O28_O O28_L_ O28_L_ O28_B O28_B O28_B CFB_EN STB EN _LP _STB _EN RO RO RO RO RO RO 0

Name DA_VIO28_OCFB_EN

18

00000000

30

4

5 4 RG_LD RG_LD O_VIO O_VIO 28_OC 28_OCF _MODE B_EN RW RW

19

LDO VIO28 Monitor

31

Bit(s) 5

20

Description Selects VIO28 OC debounce time 1'b0: 60 us 1'b1: 120 us Selects VIO28 OCFB/OC shutdown 1'b0: OCFB 1'b1: OC shutdown Enables VIO28 OCFB/OC shutdown function 1'b0: Disable 1'b1: Enable Selects VIO28 LP/ULP when entering low power mode 1'b0: No ULP 1'b1: ULP Selects VIO28 soft start time 2'b00: 240 us 2'b01: 480 us 2'b10: 1920 us 2'b11: 3840 us

RG_LDO_VIO28_STBTD

00001D68

21

0

0

0

0

0

Description VIO28 OCFB status 1'b0: OCFB not activated 1'b1: OCFB activated VIO28 ULP soft-start status 1'b0: STB not ready

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 866 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

3

DA_VIO28_L_EN

2

DA_VIO28_B_LP

1

DA_VIO28_B_STB

0

DA_VIO28_B_EN

00001D6A

Description 1'b1: STB ready VIO28 ULP enable status 1'b0: Disable 1'b1: Enable VIO28 low power mode status 1'b0: Normal mode 1'b1: Low power mode VIO28 NM soft start status 1'b0: STB not ready 1'b1: STB ready VIO28 NM enable status 1'b0: Disable 1'b1: Enable

LDO_VIO28_OP_EN

LDO VIO28 Operation Enable

00008000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

Name

Type Reset Bit(s) 2

Name RG_LDO_VIO28_HW2_OP_EN

1

RG_LDO_VIO28_HW1_OP_EN

0

RG_LDO_VIO28_HW0_OP_EN

00001D6C

18

17

16

2 1 0 RG_LD RG_LD RG_LD O_VIO O_VIO O_VIO 28_HW 28_HW 28_HW 2_OP_E 1_OP_E 0_OP_ N N EN RW RW RW 0

0

0

Description hw_ctrl[2] OPERATION ENABLE HW1: SRCLKEN2/PMRC_EN[2] 1'b0: Disable 1'b1: Enable hw_ctrl[1] OPERATION ENABLE HW1: SRCLKEN1/PMRC_EN[1] 1'b0: Disable 1'b1: Enable hw_ctrl[0] OPERATION ENABLE HW0: SRCLKEN0/PMRC_EN[0] 1'b0: Disable 1'b1: Enable

LDO_VIO28_OP_EN_SET

LDO VIO28 Operation Enable SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 867 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001D6E

Description

LDO_VIO28_OP_EN_CLR

LDO VIO28 Operation Enable CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

18

17

Bit(s)

Name

00001D70

Description

LDO_VIO28_OP_CFG

LDO VIO28 Operation Config

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

Name Type Reset

2 1 0 RG_LD RG_LD RG_LD O_VIO O_VIO O_VIO 28_HW 28_HW 28_HW 2_OP_ 1_OP_ 0_OP_ CFG CFG CFG RW RW RW 0

Bit(s) 2

Name RG_LDO_VIO28_HW2_OP_CFG

1

RG_LDO_VIO28_HW1_OP_CFG

0

RG_LDO_VIO28_HW0_OP_CFG

MediaTek Proprietary and Confidential.

16

0

0

Description hw_ctrl[2] OPERATION CONFIG HW1: SRCLKEN2/PMRC_EN[2] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low) hw_ctrl[1] OPERATION CONFIG HW1: SRCLKEN1/PMRC_EN[1] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low) hw_ctrl[0] OPERATION CONFIG HW0: SRCLKEN0/PMRC_EN[0] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low)

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Page 868 of 1067

MT6359 PMIC Datasheet Confidential A 00001D72

LDO_VIO28_OP_CFG_SET

LDO VIO28 Operation Config SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001D74

Description

LDO_VIO28_OP_CFG_CLR

LDO VIO28 Operation Config CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001D80

Description

LDO_GNR4_DSN_ID

LDO_GNR4 Design ID Register

0000E100

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001D82

Description

LDO_GNR4_DSN_REV0

LDO_GNR4 Design Revision Register 0

00001000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

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Page 869 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001D84

Description

LDO_GNR4_DSN_DBI

LDO_GNR4 Design Bank Information Register

00000002

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001D86

Description

LDO_GNR4_DSN_DXI

LDO_GNR4 Design Extra Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001D88

Description

LDO_VM18_CON0

LDO VM18 Control 0

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1 RG_LD O_VM1 8_LP RW

0 RG_LD O_VM 18_EN RW

0

1

Name Type Reset Bit(s) 1

Name RG_LDO_VM18_LP

0

RG_LDO_VM18_EN

MediaTek Proprietary and Confidential.

Description SW enter low power mode Valid once RG_LDO_VM18_SW_OP_EN = 1'b1. 1'b0: No LP 1'b1: LP SW enable control Valid once RG_LDO_VM18_SW_OP_EN = 1'b1. 1'b0: Off 1'b1: On

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Page 870 of 1067

MT6359 PMIC Datasheet Confidential A 00001D8A

LDO_VM18_CON1

LDO VM18 Control 1

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

Bit

15

14

13

12

11

10

9

8

7

Name Type Reset Bit(s) 6

Name RG_LDO_VM18_OC_TSEL

RG_LDO_VM18_OC_MODE

4

RG_LDO_VM18_OCFB_EN

2

RG_LDO_VM18_ULP

LDO_VM18_MON

0

30

29

28

27

26

25

24

23

22

Bit

15

14

13

12

11

10

9

8

7

6

Name Type Reset

21

DA_VM18_L_STB

3

DA_VM18_L_EN

MediaTek Proprietary and Confidential.

17

16

3

2

1

0

RG_LD RG_LDO_VM18 O_VM1 _STBTD 8_ULP RW

0

0

RW 1

0

20

19

18

17

16

5 4 3 2 1 0 DA_VM DA_VM DA_VM DA_VM DA_VM DA_V 18_OCF 18_L_S 18_L_E 18_B_L 18_B_S M18_B B_EN TB N P TB _EN RO RO RO RO RO RO 0

4

18

00000000

31

Name DA_VM18_OCFB_EN

19

LDO VM18 Monitor

Bit Name Type Reset

Bit(s) 5

20

Description Selects VM18 OC debounce time 1'b0: 60 us 1'b1: 120 us Selects VM18 OCFB/OC shutdown 1'b0: OCFB 1'b1: OC shutdown Enables VM18 OCFB/OC shutdown function 1'b0: Disable 1'b1: Enable Selects VM18 LP/ULP when entering low power mode 1'b0: No ULP 1'b1: ULP Selects VM18 soft start time 2'b00: 240 us 2'b01: 480 us 2'b10: 1920 us 2'b11: 3840 us

RG_LDO_VM18_STBTD

00001D8C

21

6 5 4 RG_LD RG_LD RG_LD O_VM1 O_VM1 O_VM1 8_OC_ 8_OC_ 8_OCF TSEL MODE B_EN RW RW RW 0

5

1:0

00009C02 22

0

0

0

0

0

Description VM18 OCFB status 1'b0: OCFB not activated 1'b1: OCFB activated VM18 ULP soft-start status 1'b0: STB not ready 1'b1: STB ready VM18 ULP enable status 1'b0: Disable

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 871 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

2

DA_VM18_B_LP

1

DA_VM18_B_STB

0

DA_VM18_B_EN

00001D8E

Description 1'b1: Enable VM18 low power mode status 1'b0: Normal mode 1'b1: Low power mode VM18 NM soft start status 1'b0: STB not ready 1'b1: STB ready VM18 NM enable status 1'b0: Disable 1'b1: Enable

LDO_VM18_OP_EN

LDO VM18 Operation Enable

00008000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

Name

Type Reset Bit(s) 2

Name RG_LDO_VM18_HW2_OP_EN

1

RG_LDO_VM18_HW1_OP_EN

0

RG_LDO_VM18_HW0_OP_EN

00001D90

18

17

16

2 1 0 RG_LD RG_LD RG_LD O_VM1 O_VM1 O_VM 8_HW2 8_HW1 18_HW _OP_E _OP_E 0_OP_ N N EN RW RW RW 0

0

0

Description hw_ctrl[2] OPERATION ENABLE HW1: SRCLKEN2/PMRC_EN[2] 1'b0: Disable 1'b1: Enable hw_ctrl[1] OPERATION ENABLE HW1: SRCLKEN1/PMRC_EN[1] 1'b0: Disable 1'b1: Enable hw_ctrl[0] OPERATION ENABLE HW0: SRCLKEN0/PMRC_EN[0] 1'b0: Disable 1'b1: Enable

LDO_VM18_OP_EN_SET

LDO VM18 Operation Enable SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 872 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001D92

Description

LDO_VM18_OP_EN_CLR

LDO VM18 Operation Enable CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

18

17

Bit(s)

Name

00001D94

Description

LDO_VM18_OP_CFG

LDO VM18 Operation Config

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

Name Type Reset

2 1 0 RG_LD RG_LD RG_LD O_VM1 O_VM1 O_VM 8_HW2 8_HW1 18_HW _OP_CF _OP_CF 0_OP_ G G CFG RW RW RW 0

Bit(s) 2

Name RG_LDO_VM18_HW2_OP_CFG

1

RG_LDO_VM18_HW1_OP_CFG

0

RG_LDO_VM18_HW0_OP_CFG

MediaTek Proprietary and Confidential.

16

0

0

Description hw_ctrl[2] OPERATION CONFIG HW1: SRCLKEN2/PMRC_EN[2] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low) hw_ctrl[1] OPERATION CONFIG HW1: SRCLKEN1/PMRC_EN[1] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low) hw_ctrl[0] OPERATION CONFIG HW0: SRCLKEN0/PMRC_EN[0] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low)

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Page 873 of 1067

MT6359 PMIC Datasheet Confidential A 00001D96

LDO_VM18_OP_CFG_SET

LDO VM18 Operation Config SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001D98

Description

LDO_VM18_OP_CFG_CLR

LDO VM18 Operation Config CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

17

Bit(s)

Name

00001D9A

Description

LDO_VUFS_CON0

LDO VUFS Control 0

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

Name Type Reset

1 0 RG_LD RG_LD O_VUF O_VUF S_LP S_EN RW RW 0

Bit(s) 1

Name RG_LDO_VUFS_LP

0

RG_LDO_VUFS_EN

MediaTek Proprietary and Confidential.

16

1

Description SW enter low power mode Valid once RG_LDO_VUFS_SW_OP_EN = 1'b1. 1'b0: No LP 1'b1: LP SW enable control Valid once RG_LDO_VUFS_SW_OP_EN = 1'b1. 1'b0: Off 1'b1: On

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Page 874 of 1067

MT6359 PMIC Datasheet Confidential A 00001D9C

LDO_VUFS_CON1

LDO VUFS Control 1

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

Bit

15

14

13

12

11

10

9

8

7

Name Type Reset Bit(s) 6

Name RG_LDO_VUFS_OC_TSEL

RG_LDO_VUFS_OC_MODE

4

RG_LDO_VUFS_OCFB_EN

2

RG_LDO_VUFS_ULP

LDO_VUFS_MON

0

30

29

28

27

26

25

24

23

22

Bit

15

14

13

12

11

10

9

8

7

6

Name Type Reset

21

DA_VUFS_L_STB

3

DA_VUFS_L_EN

MediaTek Proprietary and Confidential.

17

16

3

2

1

0

RG_LD RG_LDO_VUFS O_VUF _STBTD S_ULP RW

0

0

RW 1

0

20

19

18

17

16

5 4 3 2 1 0 DA_VU DA_VU DA_VU DA_VU DA_VU DA_VU FS_OCF FS_L_S FS_L_E FS_B_L FS_B_S FS_B_E B_EN TB N P TB N RO RO RO RO RO RO 0

4

18

00000000

31

Name DA_VUFS_OCFB_EN

19

LDO VUFS Monitor

Bit Name Type Reset

Bit(s) 5

20

Description Selects VUFS OC debounce time 1'b0: 60 us 1'b1: 120 us Selects VUFS OCFB/OC shutdown 1'b0: OCFB 1'b1: OC shutdown Enables VUFS OCFB/OC shutdown function 1'b0: Disable 1'b1: Enable Selects VUFS LP/ULP when entering low power mode 1'b0: No ULP 1'b1: ULP Selects VUFS soft start time 2'b00: 240 us 2'b01: 480 us 2'b10: 1920 us 2'b11: 3840 us

RG_LDO_VUFS_STBTD

00001D9E

21

6 5 4 RG_LD RG_LD RG_LD O_VUF O_VUF O_VUF S_OC_T S_OC_ S_OCFB SEL MODE _EN RW RW RW 0

5

1:0

00009C02 22

0

0

0

0

0

Description VUFS OCFB status 1'b0: OCFB not activated 1'b1: OCFB activated VUFS ULP soft-start status 1'b0: STB not ready 1'b1: STB ready VUFS ULP enable status 1'b0: Disable

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 875 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

2

DA_VUFS_B_LP

1

DA_VUFS_B_STB

0

DA_VUFS_B_EN

00001DA0

Description 1'b1: Enable VUFS low power mode status 1'b0: Normal mode 1'b1: Low power mode VUFS NM soft start status 1'b0: STB not ready 1'b1: STB ready VUFS NM enable status 1'b0: Disable 1'b1: Enable

LDO_VUFS_OP_EN

LDO VUFS Operation Enable

00008000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

Name

Type Reset Bit(s) 2

Name RG_LDO_VUFS_HW2_OP_EN

1

RG_LDO_VUFS_HW1_OP_EN

0

RG_LDO_VUFS_HW0_OP_EN

00001DA2

18

17

16

2 1 0 RG_LD RG_LD RG_LD O_VUF O_VUF O_VUF S_HW2 S_HW1 S_HW0 _OP_E _OP_E _OP_E N N N RW RW RW 0

0

0

Description hw_ctrl[2] OPERATION ENABLE HW1: SRCLKEN2/PMRC_EN[2] 1'b0: Disable 1'b1: Enable hw_ctrl[1] OPERATION ENABLE HW1: SRCLKEN1/PMRC_EN[1] 1'b0: Disable 1'b1: Enable hw_ctrl[0] OPERATION ENABLE HW0: SRCLKEN0/PMRC_EN[0] 1'b0: Disable 1'b1: Enable

LDO_VUFS_OP_EN_SET

LDO VUFS Operation Enable SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 876 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001DA4

Description

LDO_VUFS_OP_EN_CLR

LDO VUFS Operation Enable CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

18

17

Bit(s)

Name

00001DA6

Description

LDO_VUFS_OP_CFG

LDO VUFS Operation Config

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

Name Type Reset

2 1 0 RG_LD RG_LD RG_LD O_VUF O_VUF O_VUF S_HW2 S_HW1 S_HW0 _OP_CF _OP_CF _OP_C G G FG RW RW RW 0

Bit(s) 2

Name RG_LDO_VUFS_HW2_OP_CFG

1

RG_LDO_VUFS_HW1_OP_CFG

0

RG_LDO_VUFS_HW0_OP_CFG

MediaTek Proprietary and Confidential.

16

0

0

Description hw_ctrl[2] OPERATION CONFIG HW1: SRCLKEN2/PMRC_EN[2] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low) hw_ctrl[1] OPERATION CONFIG HW1: SRCLKEN1/PMRC_EN[1] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low) hw_ctrl[0] OPERATION CONFIG HW0: SRCLKEN0/PMRC_EN[0] 1'b0: On (high), off (low) 1'b1: No LP (high), LP (low)

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 877 of 1067

MT6359 PMIC Datasheet Confidential A 00001DA8

LDO_VUFS_OP_CFG_SET

LDO VUFS Operation Config SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001DAA

Description

LDO_VUFS_OP_CFG_CLR

LDO VUFS Operation Config CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001E00

Description

LDO_GNR5_DSN_ID

LDO_GNR5 Design ID Register

0000E100

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001E02

Description

LDO_GNR5_DSN_REV0

LDO_GNR5 Design Revision Register 0

00001000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 878 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001E04

Description

LDO_GNR5_DSN_DBI

LDO_GNR5 Design Bank Information Register

00000002

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001E06

Description

LDO_GNR5_DSN_DXI

LDO_GNR5 Design Extra Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001E80

Description

LDO_VSRAM0_DSN_ID

LDO_VSRAM0 Design ID Register

0000E100

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 879 of 1067

MT6359 PMIC Datasheet Confidential A 00001E82

LDO_VSRAM0_DSN_REV0

LDO_VSRAM0 Design Revision Register 0

00001000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001E84

Description

LDO_VSRAM0_DSN_DBI

LDO_VSRAM0 Design Bank Information Register

00000002

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001E86

Description

LDO_VSRAM0_DSN_DXI

LDO_VSRAM0 Design Extra Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001E88

Description

LDO_VSRAM_PROC1_CON0

LDO VSRAM_PROC1 Control 0

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 880 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001E8A

Description

LDO_VSRAM_PROC1_CON1

LDO VSRAM_PROC1 Control 1

00001C01

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

21

20

19

18

17

Bit(s)

Name

00001E8C

Description

LDO_VSRAM_PROC1_MON

LDO VSRAM_PROC1 Monitor

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

Bit

15

14

13

12

11

10

9

8

7

6

Name Type Reset Bit(s) 5

00000000

5 4 3 2 1 0 DA_VS DA_VS DA_VS DA_VS DA_VS DA_VS RAM_P RAM_P RAM_P RAM_P RAM_P RAM_P ROC1_ ROC1_L ROC1_L ROC1_ ROC1_ ROC1_ OCFB_ _STB _EN B_LP B_STB B_EN EN RO RO RO RO RO RO 0

Name DA_VSRAM_PROC1_OCFB_EN

4

DA_VSRAM_PROC1_L_STB

3

DA_VSRAM_PROC1_L_EN

2

DA_VSRAM_PROC1_B_LP

1

DA_VSRAM_PROC1_B_STB

0

DA_VSRAM_PROC1_B_EN

MediaTek Proprietary and Confidential.

16

0

0

0

0

0

Description VSRAM_PROC1 OCFB status 1'b0: OCFB not activated 1'b1: OCFB activated VSRAM_PROC1 ULP soft-start status 1'b0: STB not ready 1'b1: STB ready VSRAM_PROC1 ULP enable status 1'b0: Disable 1'b1: Enable VSRAM_PROC1 LP mode status 1'b0: Normal mode 1'b1: Low power mode VSRAM_PROC1 NM soft-start status 1'b0: STB not ready 1'b1: STB ready VSRAM_PROC1 NM enable status

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 881 of 1067

MT6359 PMIC Datasheet Confidential A 00001E8E

LDO_VSRAM_PROC1_VOSEL0 LDO VSRAM_PROC1 VOSEL 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

21

20

19

18

17

16

5

4

3

2

1

0

Bit(s)

Name

00001E90

Description

LDO_VSRAM_PROC1_VOSEL1 LDO VSRAM_PROC1 VOSEL 1

Bit Name Type Reset

31

30

29

Bit Name Type Reset

15

14

13

Bit(s) 14:8 6:0

28

27

26

25

24

23

22

12

11

10

9

8

7

6

DA_VSRAM_PROC1_VOSEL

00000000

DA_VSRAM_PROC1_VOSEL_GRAY

RO 0

0

0

0

RO 0

Name DA_VSRAM_PROC1_VOSEL DA_VSRAM_PROC1_VOSEL_GRAY

00001E92

0

0

0

0

0

0

0

0

0

Description Selects VOUT in binary format Selects VOUTn in gray format

LDO_VSRAM_PROC1_SFCHG LDO VSRAM_PROC1 Soft Change

00008888

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001E94

Description

LDO_VSRAM_PROC1_DVS

LDO VSRAM_PROC1 DVS

00000011

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 882 of 1067

MT6359 PMIC Datasheet Confidential A

Bit(s)

Name

00001E96

Description

LDO_VSRAM_PROC1_OP_EN LDO VSRAM_PROC1 Operation Enable

00008000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001E98

Description

LDO_VSRAM_PROC1_OP_EN_LDO VSRAM_PROC1 Operation Enable SET SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001E9A

Description

LDO_VSRAM_PROC1_OP_EN_LDO VSRAM_PROC1 Operation Enable CLR CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 883 of 1067

MT6359 PMIC Datasheet Confidential A 00001E9C

LDO_VSRAM_PROC1_OP_CFG LDO VSRAM_PROC1 Operation Config

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001E9E

Description

LDO_VSRAM_PROC1_OP_CFG LDO VSRAM_PROC1 Operation Config SET _SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001EA0

Description

LDO_VSRAM_PROC1_OP_CFG LDO VSRAM_PROC1 Operation Config CLR _CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 884 of 1067

MT6359 PMIC Datasheet Confidential A 00001EA2

LDO_VSRAM_PROC1_TRACK0 LDO VSRAM_PROC1 HW Tracking 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

Name

Type Reset Bit(s) 1

0

0

Name Description RG_LDO_VSRAM_PROC1_TRACK_MODE Selects VSRAM_PROC1 track mode 1'b0: Always tracking 1'b1: Tracking in no LP mode only RG_LDO_VSRAM_PROC1_TRACK_EN Enables VSRAM_PROC1 track control 1'b0: Disable 1'b1: Enable

LDO_VSRAM_PROC1_TRACK1 LDO VSRAM_PROC1 HW Tracking 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

Bit

15

14

13

12

11

10

9

8

7

6

5

4

Name

RG_LDO_VSRAM_PROC1_VOSEL_OFFSET

Type Reset

RW

3:0

16

1 0 RG_LD RG_LD O_VSR O_VSR AM_PR AM_PR OC1_T OC1_T RACK_ RACK_ MODE EN RW RW 0

00001EA4

Bit(s) 14:8

17

0

0

0

0

0

Name RG_LDO_VSRAM_PROC1_VOSEL_OFFSE T RG_LDO_VSRAM_PROC1_VOSEL_DELTA

00001EA6

0

0

19

18

Bit Name Type Reset

30

Bit Name Type Reset

15

14

0

0

0

29

28

27

26

25

24

23

22

13

12

11

10

9

8

7

6

00000000

21

20

19

18

17

16

5

4

3

2

1

0

RG_LDO_VSRAM_PROC1_VOSEL_LB

RW

MediaTek Proprietary and Confidential.

0

0

0

0

Description VSRAM track voltage offset VOUT = 6.25 mV*VOSEL VSRAM voltage adjustment amount VOUT = 6.25 mV*VOSEL

RG_LDO_VSRAM_PROC1_VOSEL_HB 0

16

3 2 1 0 RG_LDO_VSRAM_PROC1_VOSE L_DELTA RW

LDO_VSRAM_PROC1_TRACK2 LDO VSRAM_PROC1 HW Tracking 2 31

17

RW 0

0

0

0

0

0

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

0

0

0

0

Page 885 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 14:8

Name RG_LDO_VSRAM_PROC1_VOSEL_HB

6:0

RG_LDO_VSRAM_PROC1_VOSEL_LB

00001EA8

Description VSRAM voltage low bound VOUT = 0.5V + 6.25 mV*VOSEL VSRAM voltage high bound VOUT = 0.5V + 6.25 mV*VOSEL

LDO_VSRAM_PROC2_CON0

LDO VSRAM_PROC2 Control 0

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001EAA

Description

LDO_VSRAM_PROC2_CON1

LDO VSRAM_PROC2 Control 1

00001C01

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

21

20

19

18

17

Bit(s)

Name

00001EAC

Description

LDO_VSRAM_PROC2_MON

LDO VSRAM_PROC2 Monitor

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

Bit

15

14

13

12

11

10

9

8

7

6

Name

Type Reset Bit(s) 5

4

00000000

5 4 3 2 1 0 DA_VS DA_VS DA_VS DA_VS DA_VS DA_VS RAM_P RAM_P RAM_P RAM_P RAM_P RAM_P ROC2_ ROC2_L ROC2_L ROC2_ ROC2_ ROC2_ OCFB_ _STB _EN B_LP B_STB B_EN EN RO RO RO RO RO RO 0

Name DA_VSRAM_PROC2_OCFB_EN

DA_VSRAM_PROC2_L_STB

MediaTek Proprietary and Confidential.

16

0

0

0

0

0

Description VSRAM_PROC2 OCFB status 1'b0: OCFB not activated 1'b1: OCFB activated VSRAM_PROC2 ULP soft-start status

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 886 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

3

DA_VSRAM_PROC2_L_EN

2

DA_VSRAM_PROC2_B_LP

1

DA_VSRAM_PROC2_B_STB

0

DA_VSRAM_PROC2_B_EN

00001EAE

Description 1'b0: STB not ready 1'b1: STB ready VSRAM_PROC2 ULP enable status 1'b0: Disable 1'b1: Enable VSRAM_PROC2 LP mode status 1'b0: Normal mode 1'b1: Low power mode VSRAM_PROC2 NM soft-start status 1'b0: STB not ready 1'b1: STB ready VSRAM_PROC2 NM enable status 1'b0: Disable 1'b1: Enable

LDO_VSRAM_PROC2_VOSEL0 LDO VSRAM_PROC2 VOSEL 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

21

20

19

18

17

16

5

4

3

2

1

0

Bit(s)

Name

00001EB0

Description

LDO_VSRAM_PROC2_VOSEL1 LDO VSRAM_PROC2 VOSEL 1

Bit Name Type Reset

31

30

29

Bit Name Type Reset

15

14

13

Bit(s) 14:8 6:0

28

27

26

25

24

23

22

12

11

10

9

8

7

6

DA_VSRAM_PROC2_VOSEL

00000000

DA_VSRAM_PROC2_VOSEL_GRAY

RO 0

0

0

0

Name DA_VSRAM_PROC2_VOSEL DA_VSRAM_PROC2_VOSEL_GRAY

MediaTek Proprietary and Confidential.

RO 0

0

0

0

0

0

0

0

0

0

Description Selects VOUT in binary format Selects VOUT in gray format

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 887 of 1067

MT6359 PMIC Datasheet Confidential A 00001EB2

LDO_VSRAM_PROC2_SFCHG LDO VSRAM_PROC2 Soft Change

00008888

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001EB4

Description

LDO_VSRAM_PROC2_DVS

LDO VSRAM_PROC2 DVS

00000011

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001EB6

Description

LDO_VSRAM_PROC2_OP_EN LDO VSRAM_PROC2 Operation Enable

00008000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001EB8

Description

LDO_VSRAM_PROC2_OP_EN_LDO VSRAM_PROC2 Operation Enable SET SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 888 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001EBA

Description

LDO_VSRAM_PROC2_OP_EN_LDO VSRAM_PROC2 Operation Enable CLR CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001EBC

Description

LDO_VSRAM_PROC2_OP_CFG LDO VSRAM_PROC2 Operation Config

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001EBE

Description

LDO_VSRAM_PROC2_OP_CFG LDO VSRAM_PROC2 Operation Config SET _SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 889 of 1067

MT6359 PMIC Datasheet Confidential A 00001EC0

LDO_VSRAM_PROC2_OP_CFG LDO VSRAM_PROC2 Operation Config CLR _CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

17

Bit(s)

Name

00001EC2

Description

LDO_VSRAM_PROC2_TRACK0 LDO VSRAM_PROC2 HW Tracking 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

Name

Type Reset Bit(s) 1

0

LDO_VSRAM_PROC2_TRACK1 LDO VSRAM_PROC2 HW Tracking 1

00000000

31

30

29

28

27

26

25

24

23

22

21

20

Bit

15

14

13

12

11

10

9

8

7

6

5

4

Name

3:0

0

Name Description RG_LDO_VSRAM_PROC2_TRACK_MODE Selects VSRAM_PROC2 track mode 1'b0: Always tracking 1'b1: Tracking in no LP mode only RG_LDO_VSRAM_PROC2_TRACK_EN Enables VSRAM_PROC2 track control 1'b0: Disable 1'b1: Enable

Bit Name Type Reset

Bit(s) 14:8

1 0 RG_LD RG_LD O_VSR O_VSR AM_PR AM_PR OC2_T OC2_T RACK_ RACK_ MODE EN RW RW 0

00001EC4

Type Reset

16

RG_LDO_VSRAM_PROC2_VOSEL_OFFSET RW 0

0

0

0

0

Name RG_LDO_VSRAM_PROC2_VOSEL_OFFSE T RG_LDO_VSRAM_PROC2_VOSEL_DELTA

MediaTek Proprietary and Confidential.

0

0

19

18

17

16

3 2 1 0 RG_LDO_VSRAM_PROC2_VOSE L_DELTA RW 0

0

0

0

Description VSRAM track voltage offset VOUT = 6.25 mV*VOSEL VSRAM voltage adjustment amount

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 890 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001EC6

Description VOUT = 6.25 mV*VOSEL

LDO_VSRAM_PROC2_TRACK2 LDO VSRAM_PROC2 HW Tracking 2

Bit Name Type Reset

31

30

Bit Name Type Reset

15

14

29

28

27

26

25

24

23

22

13

12

11

10

9

8

7

6

RG_LDO_VSRAM_PROC2_VOSEL_HB

00000000

21

20

19

18

17

16

5

4

3

2

1

0

RG_LDO_VSRAM_PROC2_VOSEL_LB

RW 0

0

0

0

Bit(s) 14:8

Name RG_LDO_VSRAM_PROC2_VOSEL_HB

6:0

RG_LDO_VSRAM_PROC2_VOSEL_LB

00001F00

RW 0

0

0

0

0

0

0

0

0

0

Description VSRAM voltage low bound VOUT = 0.5V + 6.25 mV*VOSEL VSRAM voltage high bound VOUT = 0.5V + 6.25 mV*VOSEL

LDO_VSRAM1_DSN_ID

LDO_VSRAM1 Design ID Register

0000E100

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001F02

Description

LDO_VSRAM1_DSN_REV0

LDO_VSRAM1 Design Revision Register 0

00001000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

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Page 891 of 1067

MT6359 PMIC Datasheet Confidential A 00001F04

LDO_VSRAM1_DSN_DBI

LDO_VSRAM1 Design Bank Information Register

00000002

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001F06

Description

LDO_VSRAM1_DSN_DXI

LDO_VSRAM1 Design Extra Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001F08

Description

LDO_VSRAM_OTHERS_CON0 LDO VSRAM_OTHERS Control 0

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001F0A

Description

LDO_VSRAM_OTHERS_CON1 LDO VSRAM_OTHERS Control 1

00001C01

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 892 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001F0C

Description

LDO_VSRAM_OTHERS_MON LDO VSRAM_OTHERS Monitor

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

Bit

15

14

13

12

11

10

9

8

7

6

Name Type Reset Bit(s) 5

21

4

DA_VSRAM_OTHERS_L_STB

3

DA_VSRAM_OTHERS_L_EN

2

DA_VSRAM_OTHERS_B_LP

1

DA_VSRAM_OTHERS_B_STB

0

DA_VSRAM_OTHERS_B_EN

00001F0E

20

5 4 DA_VS DA_VS RAM_ RAM_ OTHER OTHER S_OCFB S_L_ST _EN B RO RO 0

Name DA_VSRAM_OTHERS_OCFB_EN

00000000

0

19

18

17

16

3

2

DA_VS RAM_ OTHER S_L_EN

DA_VS RAM_ OTHER S_B_LP

RO

RO

1 DA_VS RAM_ OTHER S_B_ST B RO

0 DA_VS RAM_ OTHER S_B_E N RO

0

0

0

0

Description VSRAM_OTHERS OCFB status 1'b0: OCFB not activated 1'b1: OCFB activated VSRAM_OTHERS ULP soft-start status 1'b0: STB not ready 1'b1: STB ready VSRAM_OTHERS ULP enable status 1'b0: Disable 1'b1: Enable VSRAM_OTHERS LP mode status 1'b0: Normal mode 1'b1: Low power mode VSRAM_OTHERS NM soft-start status 1'b0: STB not ready 1'b1: STB ready VSRAM_OTHERS NM enable status 1'b0: Disable 1'b1: Enable

LDO_VSRAM_OTHERS_VOSEL LDO VSRAM_OTHERS VOSEL 0 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 893 of 1067

MT6359 PMIC Datasheet Confidential A 00001F10

LDO_VSRAM_OTHERS_VOSEL LDO VSRAM_OTHERS VOSEL 1 1

Bit Name Type Reset

31

30

29

Bit Name Type Reset

15

14

13

Bit(s) 14:8 6:0

0

0

28

27

26

25

24

23

22

12

11

10

9

8

7

6

21

20

19

18

17

16

5

4

3

2

1

0

DA_VSRAM_OTHERS_VOSEL

DA_VSRAM_OTHERS_VOSEL_GRAY

RO

RO

0

0

0

Name DA_VSRAM_OTHERS_VOSEL DA_VSRAM_OTHERS_VOSEL_GRAY

00001F12

00000000

0

0

0

0

0

0

0

0

0

Description Selects VOUT in binary format Selects VOUT in gray format

LDO_VSRAM_OTHERS_SFCHG LDO VSRAM_OTHERS Soft change

00008888

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001F14

Description

LDO_VSRAM_OTHERS_DVS

LDO VSRAM_OTHERS DVS

00000011

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 894 of 1067

MT6359 PMIC Datasheet Confidential A 00001F16

LDO_VSRAM_OTHERS_OP_E LDO VSRAM_OTHERS Operation Enable N

00008000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001F18

Description

LDO_VSRAM_OTHERS_OP_E LDO VSRAM_OTHERS Operation Enable SET N_SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001F1A

Description

LDO_VSRAM_OTHERS_OP_E LDO VSRAM_OTHERS Operation Enable CLR N_CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 895 of 1067

MT6359 PMIC Datasheet Confidential A 00001F1C

LDO_VSRAM_OTHERS_OP_CFG

LDO VSRAM_OTHERS Operation Config

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001F1E

Description

LDO_VSRAM_OTHERS_OP_CF LDO VSRAM_OTHERS Operation Config SET G_SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001F20

Description

LDO_VSRAM_OTHERS_OP_CF LDO VSRAM_OTHERS Operation Config CLR G_CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 896 of 1067

MT6359 PMIC Datasheet Confidential A 00001F22

LDO_VSRAM_OTHERS_TRACK0 LDO VSRAM_OTHERS HW Tracking 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1 RG_LD O_VSR AM_OT HERS_T RACK_ MODE RW

0 RG_LD O_VSR AM_O THERS _TRAC K_EN RW

0

0

Name

Type Reset Bit(s) 1

0

Name Description RG_LDO_VSRAM_OTHERS_TRACK_MOD Selects VSRAM_OTHERS track mode E 1'b0: Always tracking 1'b1: Tracking in no LP mode only RG_LDO_VSRAM_OTHERS_TRACK_EN Enables VSRAM_OTHERS track control 1'b0: Disable 1'b1: Enable

00001F24

LDO_VSRAM_OTHERS_TRACK1 LDO VSRAM_OTHERS HW Tracking 1

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

Bit

15

14

13

12

11

10

9

8

7

6

5

4

Name

RG_LDO_VSRAM_OTHERS_VOSEL_OFFSET

Type Reset Bit(s) 14:8 3:0

RW 0

0

0

0

0

Name RG_LDO_VSRAM_OTHERS_VOSEL_OFFS ET RG_LDO_VSRAM_OTHERS_VOSEL_DELT A

00001F26

0

00000000 19

18

17

16

3 2 1 0 RG_LDO_VSRAM_OTHERS_VOS EL_DELTA RW

0

0

0

0

0

Description VSRAM track voltage offset VOUT = 6.25 mV*VOSEL VSRAM voltage adjustment amount VOUT = 6.25 mV*VOSEL

LDO_VSRAM_OTHERS_TRACK2

LDO VSRAM_OTHERS HW Tracking 2

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

RG_LDO_VSRAM_OTHERS_VOSEL_HB

RG_LDO_VSRAM_OTHERS_VOSEL_LB

RW 0

MediaTek Proprietary and Confidential.

0

0

0

RW 0

0

0

0

0

0

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

0

0

0

0

Page 897 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 14:8

Name RG_LDO_VSRAM_OTHERS_VOSEL_HB

6:0

RG_LDO_VSRAM_OTHERS_VOSEL_LB

00001F28

Description VSRAM voltage low bound VOUT = 0.5V + 6.25 mV*VOSEL VSRAM voltage high bound VOUT = 0.5V + 6.25 mV*VOSEL

LDO_VSRAM_OTHERS_SSHUB LDO VSRAM_OTHERS Sensor Hub 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8 RG_LD O_VSR AM_OT HERS_S SHUB_ SLEEP_ VOSEL_ EN RW 0

7

6

5

4

3

2

1

0

Name

RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_SLEEP

Type Reset

0

Bit(s) 15:9 8 7:1 0

0

0

RW 0

0

0

Name RG_LDO_VSRAM_OTHERS_SSHUB_VO SEL_SLEEP RG_LDO_VSRAM_OTHERS_SSHUB_SLE EP_VOSEL_EN RG_LDO_VSRAM_OTHERS_SSHUB_VO SEL RG_LDO_VSRAM_OTHERS_SSHUB_EN

00001F2A

LDO_VSRAM_OTHERS_BT

0

RG_LD O_VSR AM_O THERS _SSHU B_EN

RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL

0

0

0

RW 0

0

0

0

RW 0

Description VSRAM_OTHERS SSHUB VOSEL for SLEEP (no use) VSRAM_OTHERS SSHUB SLEEP VOLTAGE ENABLE HW control: PAD_VREG (no use) VSRAM_OTHERS SSHUB VOSEL VSRAM_OTHERS SSHUB ENABLE HW control: PAD_VREG 1'b0: Disable 1'b1: Enable

LDO VSRAM_OTHERS BT 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0 RG_LD O_VSR AM_O THERS _BT_LP _EN RW

0

0

Name

RG_LDO_VSRAM_OTHERS_BT_LP_VOSEL

Type Reset Bit(s) 7:1 0

RW 0

0

0

0

0

0

Name Description RG_LDO_VSRAM_OTHERS_BT_LP_VOSE VSRAM_OTHERS BT LP VOSEL L RG_LDO_VSRAM_OTHERS_BT_LP_EN VSRAM_OTHERS BT LP ENABLE

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 898 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001F2C

Description HW control: PMRC 1'b0: Disable 1'b1: Enable

LDO_VSRAM_OTHERS_SPI

LDO VSRAM_OTHERS SPI 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0 RG_LD O_VSR AM_O THERS _SPI_E N RW 0

Name

RG_LDO_VSRAM_OTHERS_SPI_VOSEL

Type Reset

RW

Bit(s) 7:1 0

0

Name RG_LDO_VSRAM_OTHERS_SPI_VOSEL RG_LDO_VSRAM_OTHERS_SPI_EN

00001F2E

LDO_VSRAM_MD_CON0

0

0

0

0

0

0

Description VSRAM_OTHERS SPI VOSEL VSRAM_OTHERS SPI ENABLE HW control: PAD_VREG 1'b0: Disable 1'b1: Enable

LDO VSRAM_MD Control 0

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001F30

Description

LDO_VSRAM_MD_CON1

LDO VSRAM_MD Control 1

00001C01

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 899 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001F32

Description

LDO_VSRAM_MD_MON

LDO VSRAM_MD Monitor

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

Bit

15

14

13

12

11

10

9

8

7

6

Name Type Reset Bit(s) 5

00000000 21

4

DA_VSRAM_MD_L_STB

3

DA_VSRAM_MD_L_EN

2

DA_VSRAM_MD_B_LP

1

DA_VSRAM_MD_B_STB

0

DA_VSRAM_MD_B_EN

00001F34

19

18

17

16

5 4 3 2 1 0 DA_VS DA_VS DA_VS DA_VS DA_VS DA_VS RAM_ RAM_ RAM_ RAM_ RAM_ RAM_ MD_O MD_L_ MD_L_ MD_B_ MD_B_ MD_B_ CFB_EN STB EN LP STB EN RO RO RO RO RO RO 0

Name DA_VSRAM_MD_OCFB_EN

20

0

0

0

0

0

Description VSRAM_MD OCFB status 1'b0: OCFB not activated 1'b1: OCFB activated VSRAM_MD ULP soft-start status 1'b0: STB not ready 1'b1: STB ready VSRAM_MD ULP enable status 1'b0: Disable 1'b1: Enable VSRAM_MD LP mode status 1'b0: Normal mode 1'b1: Low power mode VSRAM_MD NM soft-start status 1'b0: STB not ready 1'b1: STB ready VSRAM_MD NM enable status 1'b0: Disable 1'b1: Enable

LDO_VSRAM_MD_VOSEL0

LDO VSRAM_MD VOSEL 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 900 of 1067

MT6359 PMIC Datasheet Confidential A 00001F36

LDO_VSRAM_MD_VOSEL1

Bit Name Type Reset

31

30

29

Bit Name Type Reset

15

14

13

Bit(s) 14:8 6:0

0

0

LDO VSRAM_MD VOSEL 1

27

26

25

24

23

22

21

20

19

18

17

16

12

11

10

9

8

7

6

5

4

3

2

1

0

0

DA_VSRAM_MD_VOSEL

DA_VSRAM_MD_VOSEL_GRAY

RO

RO

0

0

0

Name DA_VSRAM_MD_VOSEL DA_VSRAM_MD_VOSEL_GRAY

00001F38

00000000

28

0

0

0

0

0

0

0

0

Description Selects VOUT in binary format Selects VOUT in gray format

LDO_VSRAM_MD_SFCHG

LDO VSRAM_MD Soft change

00008888

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001F3A

Description

LDO_VSRAM_MD_DVS

LDO VSRAM_MD DVS

00000011

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001F3C

Description

LDO_VSRAM_MD_OP_EN

LDO VSRAM_MD Operation Enable

00008000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 901 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001F3E

Description

LDO_VSRAM_MD_OP_EN_SET LDO VSRAM_MD Operation Enable SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001F40

Description

LDO_VSRAM_MD_OP_EN_CLR

LDO VSRAM_MD Operation Enable CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001F42

Description

LDO_VSRAM_MD_OP_CFG

LDO VSRAM_MD Operation Config

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

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Page 902 of 1067

MT6359 PMIC Datasheet Confidential A 00001F44

LDO_VSRAM_MD_OP_CFG_SET LDO VSRAM_MD Operation Config SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001F46

Description

LDO_VSRAM_MD_OP_CFG_CLR LDO VSRAM_MD Operation Config CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

17

Bit(s)

Name

00001F48

Description

LDO_VSRAM_MD_TRACK0

LDO VSRAM_MD HW Tracking 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

Name

Type Reset Bit(s) 1

0

1 0 RG_LD RG_LD O_VSR O_VSR AM_M AM_M D_TRA D_TRA CK_MO CK_EN DE RW RW 0

Name RG_LDO_VSRAM_MD_TRACK_MODE

RG_LDO_VSRAM_MD_TRACK_EN

MediaTek Proprietary and Confidential.

16

0

Description Selects VSRAM_MD track mode 1'b0: Always tracking 1'b1: Tracking in no LP mode only Enables VSRAM_MD track control

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 903 of 1067

MT6359 PMIC Datasheet Confidential A 00001F4A

LDO_VSRAM_MD_TRACK1

LDO VSRAM_MD HW Tracking 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

Bit

15

14

13

12

11

10

9

8

7

6

5

4

Name

RG_LDO_VSRAM_MD_VOSEL_OFFSET

Type Reset

RW 0

0

0

0

0

Bit(s) 14:8

Name RG_LDO_VSRAM_MD_VOSEL_OFFSET

3:0

RG_LDO_VSRAM_MD_VOSEL_DELTA

00001F4C

0

0

19

18

17

16

3 2 1 0 RG_LDO_VSRAM_MD_VOSEL_ DELTA RW 0

0

0

0

Description VSRAM track voltage offset VOUT = 6.25 mV*VOSEL VSRAM voltage adjustment amount VOUT = 6.25 mV*VOSEL

LDO_VSRAM_MD_TRACK2

LDO VSRAM_MD HW Tracking 2

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

RG_LDO_VSRAM_MD_VOSEL_HB

RG_LDO_VSRAM_MD_VOSEL_LB

RW 0

0

0

0

Bit(s) 14:8

Name RG_LDO_VSRAM_MD_VOSEL_HB

6:0

RG_LDO_VSRAM_MD_VOSEL_LB

00001F80

RW 0

0

0

0

0

0

0

0

0

0

Description VSRAM voltage low bound VOUT = 0.5V + 6.25 mV*VOSEL VSRAM voltage high bound VOUT = 0.5V + 6.25 mV*VOSEL

LDO_ANA0_DSN_ID

LDO_ANA0 Design ID register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

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Page 904 of 1067

MT6359 PMIC Datasheet Confidential A 00001F82

LDO_ANA0_DSN_REV0

LDO_ANA0 Design Revision Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001F84

Description

LDO_ANA0_DSN_DBI

LDO_ANA0 Design Bank Information register

00003600

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001F86

Description

LDO_ANA0_DSN_FPI

LDO_ANA0 Design Extra Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

18

17

16

2

1

0

Bit(s)

Name

00001F88

Description

VFE28_ANA_CON0

VFE28 Control Register 0

00000A00

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

MediaTek Proprietary and Confidential.

RG_VFE28_VOCAL RW 0

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

0

0

0

Page 905 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 3:0

Name RG_VFE28_VOCAL

00001F8A

Description Calibrates output voltage 4'b0000: +00 mV 4'b0001: +10 mV 4'b0010: +20 mV 4'b0011: +30 mV 4'b0100: +40 mV 4'b0101: +50 mV 4'b0110: +60 mV 4'b0111: +70 mV 4'b1000: +80 mV 4'b1001: +90 mV 4'b1010: +100 mV

VFE28_ANA_CON1

VFE28 Control Register 1

00000019

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0 RG_VF E28_N DIS_EN RW

Name Type Reset Bit(s) 0

1

Name RG_VFE28_NDIS_EN

00001F8C

Description Enables output power-down 1'b0: Disable output power-down 1'b1: Enable output power-down

VAUX18_ANA_CON0

VAUX18 Control Register 0

00000004

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

Bit(s) 3:0

18

17

16

2

1

0

RG_VAUX18_VOCAL RW 0

Name RG_VAUX18_VOCAL

MediaTek Proprietary and Confidential.

1

0

0

Description Calibrates output voltage 4'b0000: +00 mV 4'b0001: +10 mV 4'b0010: +20 mV 4'b0011: +30 mV 4'b0100: +40 mV 4'b0101: +50 mV 4'b0110: +60 mV 4'b0111: +70 mV

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 906 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001F8E

Description 4'b1000: +80 mV 4'b1001: +90 mV 4'b1010: +100 mV

VAUX18_ANA_CON1

VAUX18 Control Register 1

00000019

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0 RG_VA UX18_ NDIS_E N RW

Name Type Reset Bit(s) 0

1

Name RG_VAUX18_NDIS_EN

00001F90

Description Enables output power-down 1'b0: Disable output power-down 1'b1: Enable output power-down

VUSB_ANA_CON0

VUSB Control Register 0

00000C07

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

Bit(s) 3:0

18

17

16

2

1

0

RG_VUSB_VOCAL RW 0

Name RG_VUSB_VOCAL

MediaTek Proprietary and Confidential.

1

1

1

Description Calibrates output voltage 4'b0000: +00 mV 4'b0001: +10 mV 4'b0010: +20 mV 4'b0011: +30 mV 4'b0100: +40 mV 4'b0101: +50 mV 4'b0110: +60 mV 4'b0111: +70 mV 4'b1000: +80 mV 4'b1001: +90 mV 4'b1010: +100 mV

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 907 of 1067

MT6359 PMIC Datasheet Confidential A 00001F92

VUSB_ANA_CON1

VUSB Control Register 1

00000019

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0 RG_VU SB_NDI S_EN RW

Name Type Reset Bit(s) 0

1

Name RG_VUSB_NDIS_EN

00001F94

Description Enables output power-down 1'b0: Disable output power-down 1'b1: Enable output power-down

VBIF28_ANA_CON0

VBIF28 Control Register 0

00000A00

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

Bit(s) 3:0

18

17

16

2

1

0

RG_VBIF28_VOCAL RW 0

Name RG_VBIF28_VOCAL

MediaTek Proprietary and Confidential.

0

0

0

Description Calibrates output voltage 4'b0000: +00 mV 4'b0001: +10 mV 4'b0010: +20 mV 4'b0011: +30 mV 4'b0100: +40 mV 4'b0101: +50 mV 4'b0110: +60 mV 4'b0111: +70 mV 4'b1000: +80 mV 4'b1001: +90 mV 4'b1010: +100 mV

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 908 of 1067

MT6359 PMIC Datasheet Confidential A 00001F96

VBIF28_ANA_CON1

VBIF28 Control Register 1

00000019

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0 RG_VBI F28_N DIS_EN RW

Name Type Reset Bit(s) 0

1

Name RG_VBIF28_NDIS_EN

00001F98

Description Enables output power-down 1'b0: Disable output power-down 1'b1: Enable output power-down

VCN33_1_ANA_CON0

VCN33_1 Control Register 0

00000F00

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

Bit(s) 3:0

18

17

16

2

1

0

RG_VCN33_1_VOCAL RW 0

Name RG_VCN33_1_VOCAL

MediaTek Proprietary and Confidential.

0

0

0

Description Calibrates output voltage 4'b0000: +00 mV 4'b0001: +10 mV 4'b0010: +20 mV 4'b0011: +30 mV 4'b0100: +40 mV 4'b0101: +50 mV 4'b0110: +60 mV 4'b0111: +70 mV 4'b1000: +80 mV 4'b1001: +90 mV 4'b1010: +100 mV

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 909 of 1067

MT6359 PMIC Datasheet Confidential A 00001F9A

VCN33_1_ANA_CON1

VCN33_1 Control Register 1

00000061

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0 RG_VC N33_1 _NDIS_ EN RW

Name Type Reset Bit(s) 0

1

Name RG_VCN33_1_NDIS_EN

00001F9C

Description Enables output power-down 1'b0: Disable output power-down 1'b1: Enable output power-down

VCN33_2_ANA_CON0

VCN33_2 Control Register 0

00000F00

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

Bit(s) 3:0

18

17

16

2

1

0

RG_VCN33_2_VOCAL RW 0

Name RG_VCN33_2_VOCAL

MediaTek Proprietary and Confidential.

0

0

0

Description Calibrates output voltage 4'b0000: +00 mV 4'b0001: +10 mV 4'b0010: +20 mV 4'b0011: +30 mV 4'b0100: +40 mV 4'b0101: +50 mV 4'b0110: +60 mV 4'b0111: +70 mV 4'b1000: +80 mV 4'b1001: +90 mV 4'b1010: +100 mV

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 910 of 1067

MT6359 PMIC Datasheet Confidential A 00001F9E

VCN33_2_ANA_CON1

VCN33_2 Control Register 1

00000061

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0 RG_VC N33_2 _NDIS_ EN RW

Name Type Reset Bit(s) 0

1

Name RG_VCN33_2_NDIS_EN

00001FA0

Description Enables output power-down 1'b0: Disable output power-down 1'b1: Enable output power-down

VEMC_ANA_CON0

VEMC Control Register 0

00000031

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0 RG_VE MC_N DIS_EN RW

Name Type Reset Bit(s) 0

1

Name RG_VEMC_NDIS_EN

00001FA2

Description Enables output power-down 1'b0: Disable output power-down 1'b1: Enable output power-down

VSIM1_ANA_CON0

VSIM1 Control Register 0

00000406

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

Bit(s) 3:0

18

17

16

2

1

0

RG_VSIM1_VOCAL RW 0

Name RG_VSIM1_VOCAL

MediaTek Proprietary and Confidential.

1

1

0

Description Calibrates output voltage 4'b0000: +00 mV 4'b0001: +10 mV 4'b0010: +20 mV 4'b0011: +30 mV © 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 911 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001FA4

Description 4'b0100: +40 mV 4'b0101: +50 mV 4'b0110: +60 mV 4'b0111: +70 mV 4'b1000: +80 mV 4'b1001: +90 mV 4'b1010: +100 mV

VSIM1_ANA_CON1

VSIM1 Control Register 1

00000019

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0 RG_VSI M1_N DIS_EN RW

Name Type Reset Bit(s) 0

1

Name RG_VSIM1_NDIS_EN

00001FA6

Description Enables output power-down 1'b0: Disable output power-down 1'b1: Enable output power-down

VSIM2_ANA_CON0

VSIM2 Control Register 0

00000406

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

Bit(s) 3:0

18

17

16

2

1

0

RG_VSIM2_VOCAL RW 0

Name RG_VSIM2_VOCAL

MediaTek Proprietary and Confidential.

1

1

0

Description Calibrates output voltage 4'b0000: +00 mV 4'b0001: +10 mV 4'b0010: +20 mV 4'b0011: +30 mV 4'b0100: +40 mV 4'b0101: +50 mV 4'b0110: +60 mV 4'b0111: +70 mV 4'b1000: +80 mV 4'b1001: +90 mV 4'b1010: +100 mV

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 912 of 1067

MT6359 PMIC Datasheet Confidential A 00001FA8

VSIM2_ANA_CON1

VSIM2 Control Register 1

00000019

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0 RG_VSI M2_N DIS_EN RW

Name Type Reset Bit(s) 0

1

Name RG_VSIM2_NDIS_EN

00001FAA

Description Enables output power-down 1'b0: Disable output power-down 1'b1: Enable output power-down

VIO28_ANA_CON0

VIO28 Control Register 0

00000900

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

Bit(s) 3:0

18

17

16

2

1

0

RG_VIO28_VOCAL RW 0

Name RG_VIO28_VOCAL

MediaTek Proprietary and Confidential.

0

0

0

Description Calibrates output voltage 4'b0000: +00 mV 4'b0001: +10 mV 4'b0010: +20 mV 4'b0011: +30 mV 4'b0100: +40 mV 4'b0101: +50 mV 4'b0110: +60 mV 4'b0111: +70 mV 4'b1000: +80 mV 4'b1001: +90 mV 4'b1010: +100 mV

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 913 of 1067

MT6359 PMIC Datasheet Confidential A 00001FAC

VIO28_ANA_CON1

VIO28 Control Register 1

00000019

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0 RG_VI O28_N DIS_EN RW

Name Type Reset Bit(s) 0

1

Name RG_VIO28_NDIS_EN

00001FAE

Description Enables output power-down 1'b0: Disable output power-down 1'b1: Enable output power-down

VIBR_ANA_CON0

VIBR Control Register 0

00000900

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

Bit(s) 3:0

18

17

16

2

1

0

RG_VIBR_VOCAL RW 0

Name RG_VIBR_VOCAL

MediaTek Proprietary and Confidential.

0

0

0

Description Calibrates output voltage 4'b0000: +00 mV 4'b0001: +10 mV 4'b0010: +20 mV 4'b0011: +30 mV 4'b0100: +40 mV 4'b0101: +50 mV 4'b0110: +60 mV 4'b0111: +70 mV 4'b1000: +80 mV 4'b1001: +90 mV 4'b1010: +100 mV

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 914 of 1067

MT6359 PMIC Datasheet Confidential A 00001FB0

VIBR_ANA_CON1

VIBR Control Register 1

00000019

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0 RG_VIB R_NDIS _EN RW

Name Type Reset Bit(s) 0

1

Name RG_VIBR_NDIS_EN

00001FB2

Description Enables output power-down 1'b0: Disable output power-down 1'b1: Enable output power-down

ADLDO_ANA_CON0

ADLDO Control Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001FB4

Description

VA12_ANA_CON0

VA12 Control Register 0

00000005

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 915 of 1067

MT6359 PMIC Datasheet Confidential A 00001FB6

LDO_ANA0_ELR_NUM

LDO_ANA0 Number of ELR Register

0000000A

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001FB8

Description

VFE28_ELR_0

VFE28 ELR 0 Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001FBA

Description

VFE28_ELR_1

VFE28 ELR 1 Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001FBC

Description

VFE28_ELR_2

VFE28 ELR 2 Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 916 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00001FBE

Description

VFE28_ELR_3

VFE28 ELR 3 Register

00004000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00001FC0

Description

VFE28_ELR_4

VFE28 ELR 4 Register

00000600

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00002000

Description

LDO_ANA1_DSN_ID

LDO_ANA1 Design ID register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

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Page 917 of 1067

MT6359 PMIC Datasheet Confidential A 00002002

LDO_ANA1_DSN_REV0

LDO_ANA1 Design Revision Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00002004

Description

LDO_ANA1_DSN_DBI

LDO_ANA1 Design Bank Information register

00004600

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00002006

Description

LDO_ANA1_DSN_FPI

LDO_ANA1 Design Extra Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00002008

Description

VRF18_ANA_CON0

VRF18 Control Register 0

00000600

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 918 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

0000200A

Description

VRF18_ANA_CON1

VRF18 Control Register 1

00000021

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000200C

Description

VEFUSE_ANA_CON0

VEFUSE Control Register 0

00000C00

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s) 3:0

RG_VEFUSE_VOCAL RW 0

Name RG_VEFUSE_VOCAL

MediaTek Proprietary and Confidential.

0

0

0

Description Calibrates output voltage 4'b0000: +00 mV 4'b0001: +10 mV 4'b0010: +20 mV 4'b0011: +30 mV 4'b0100: +40 mV 4'b0101: +50 mV 4'b0110: +60 mV 4'b0111: +70 mV 4'b1000: +80 mV 4'b1001: +90 mV 4'b1010: +100 mV

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 919 of 1067

MT6359 PMIC Datasheet Confidential A 0000200E

VEFUSE_ANA_CON1

VEFUSE Control Register 1

00000009

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0 RG_VE FUSE_ NDIS_E N RW

Name Type Reset Bit(s) 0

1

Name RG_VEFUSE_NDIS_EN

00002010

Description Enables output power-down 1'b0: Disable output power-down 1'b1: Enable output power-down

VCN18_ANA_CON0

VCN18 Control Register 0

00000C00

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00002012

Description

VCN18_ANA_CON1

VCN18 Control Register 1

00000009

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 920 of 1067

MT6359 PMIC Datasheet Confidential A 00002014

VCAMIO_ANA_CON0

VCAMIO Control Register 0

00000C00

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

Bit(s) 3:0

18

17

16

2

1

0

RG_VCAMIO_VOCAL RW

Name RG_VCAMIO_VOCAL

00002016

0

0

0

0

Description Calibrates output voltage 4'b0000: +00 mV 4'b0001: +10 mV 4'b0010: +20 mV 4'b0011: +30 mV 4'b0100: +40 mV 4'b0101: +50 mV 4'b0110: +60 mV 4'b0111: +70 mV 4'b1000: +80 mV 4'b1001: +90 mV 4'b1010: +100 mV

VCAMIO_ANA_CON1

VCAMIO Control Register 1

00000009

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0 RG_VC AMIO_ NDIS_E N RW

Name Type Reset Bit(s) 0

1

Name RG_VCAMIO_NDIS_EN

MediaTek Proprietary and Confidential.

Description Enables output power-down 1'b0: Disable output power-down 1'b1: Enable output power-down

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 921 of 1067

MT6359 PMIC Datasheet Confidential A 00002018

VAUD18_ANA_CON0

VAUD18 Control Register 0

00000C00

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000201A

Description

VAUD18_ANA_CON1

VAUD18 Control Register 1

00000009

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000201C

Description

VIO18_ANA_CON0

VIO18 Control Register 0

00000C00

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000201E

Description

VIO18_ANA_CON1

VIO18 Control Register 1

00000009

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 922 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00002020

Description

VM18_ANA_CON0

VM18 Control Register 0

00000C00

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00002022

Description

VM18_ANA_CON1

VM18 Control Register 1

00000009

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00002024

Description

VUFS_ANA_CON0

VUFS Control Register 0

00000C06

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

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Page 923 of 1067

MT6359 PMIC Datasheet Confidential A 00002026

VUFS_ANA_CON1

VUFS Control Register 1

00000009

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00002028

Description

SLDO20_ANA_CON0

SLDO20 Control Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000202A

Description

VRF12_ANA_CON0

VRF12 Control Register 0

00000300

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000202C

Description

VRF12_ANA_CON1

VRF12 Control Register 1

00000021

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 924 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

0000202E

Description

VCN13_ANA_CON0

VCN13 Control Register 0

00000400

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00002030

Description

VCN13_ANA_CON1

VCN13 Control Register 1

00000021

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00002032

Description

VA09_ANA_CON0

VA09 Control Register 0

00000005

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 925 of 1067

MT6359 PMIC Datasheet Confidential A 00002034

VSRAM_PROC1_ANA_CON0 VSRAM_PROC1 Control Register 0

00002B90

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00002036

Description

VSRAM_PROC1_ANA_CON1 VSRAM_PROC1 Control Register 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00002038

Description

VSRAM_PROC2_ANA_CON0 VSRAM_PROC2 Control Register 0

00002B90

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000203A

Description

VSRAM_PROC2_ANA_CON1 VSRAM_PROC2 Control Register 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 926 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

0000203C

Description

VSRAM_OTHERS_ANA_CON0 VSRAM_OTHERS Control Register 0

00002B90

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000203E

Description

VSRAM_OTHERS_ANA_CON1 VSRAM_OTHERS Control Register 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00002040

Description

VSRAM_MD_ANA_CON0

VSRAM_MD Control Register 0

00002B90

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 927 of 1067

MT6359 PMIC Datasheet Confidential A 00002042

VSRAM_MD_ANA_CON1

VSRAM_MD Control Register 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00002044

Description

SLDO14_ANA_CON0

SLDO14 Control Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00002046

Description

LDO_ANA1_ELR_NUM

LDO_ANA1 Number of ELR Register

00000008

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00002048

Description

VRF18_ELR_0

VRF18 ELR 0 Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 928 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

0000204A

Description

VRF18_ELR_1

VRF18 ELR 1 Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000204C

Description

VRF18_ELR_2

VRF18 ELR 2 Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000204E

Description

VRF18_ELR_3

VRF18 ELR 3 Register

00000300

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 929 of 1067

MT6359 PMIC Datasheet Confidential A 00002080

LDO_ANA2_DSN_ID

LDO_ANA2 Design ID Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00002082

Description

LDO_ANA2_DSN_REV0

LDO_ANA2 Design Revision Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00002084

Description

LDO_ANA2_DSN_DBI

LDO_ANA2 Design Bank Information Register

00001A00

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00002086

Description

LDO_ANA2_DSN_FPI

LDO_ANA2 Design Extra Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 930 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00002088

Description

VXO22_ANA_CON0

VXO22 Control Register 0

00000404

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

Bit(s) 3:0

18

17

16

2

1

0

RG_VXO22_VOCAL RW

Name RG_VXO22_VOCAL

0000208A

0

1

0

0

Description Calibrates output voltage 4'b0000: +00 mV 4'b0001: +10 mV 4'b0010: +20 mV 4'b0011: +30 mV 4'b0100: +40 mV 4'b0101: +50 mV 4'b0110: +60 mV 4'b0111: +70 mV 4'b1000: +80 mV 4'b1001: +90 mV 4'b1010: +100 mV

VXO22_ANA_CON1

VXO22 Control Register 1

00000008

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

18

17

16

2

1

0

Bit(s)

Name

0000208C

Description

VRFCK_ANA_CON0

VRFCK Control Register 0

00000100

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

MediaTek Proprietary and Confidential.

RG_VRFCK_VOCAL RW 0

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

0

0

0

Page 931 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 3:0

Name RG_VRFCK_VOCAL

0000208E

Description No connection

VRFCK_ANA_CON1

VRFCK Control Register 1

00002020

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00002090

Description

VRFCK_ANA_CON2

VRFCK Control Register 2

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

18

17

16

2

1

0

Bit(s)

Name

00002092

Description

VRFCK_1_ANA_CON0

VRFCK_1 Control Register 0

00000F00

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

Bit(s) 3:0

RG_VRFCK_1_VOCAL RW 0

Name RG_VRFCK_1_VOCAL

MediaTek Proprietary and Confidential.

0

0

0

Description Calibrates output voltage 4'b0000: +00 mV 4'b0001: +10 mV 4'b0010: +20 mV 4'b0011: +30 mV 4'b0100: +40 mV 4'b0101: +50 mV 4'b0110: +60 mV 4'b0111: +70 mV 4'b1000: +80 mV

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 932 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00002094

Description 4'b1001: +90 mV 4'b1010: +100 mV

VRFCK_1_ANA_CON1

VRFCK_1 Control Register 1

00000008

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00002096

Description

VBBCK_ANA_CON0

VBBCK Control Register 0

000080C0

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00002098

Description

VBBCK_ANA_CON1

VBBCK Control Register 1

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 933 of 1067

MT6359 PMIC Datasheet Confidential A 0000209A

LDO_ANA2_ELR_NUM

LDO_ANA2 Number of ELR Register

00000003

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000209C

Description

DCXO_ADLDO_BIAS_ELR_0

DCXO_ADLDO_BIAS ELR 0 Register

00000890

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11 RG_VR FCK_N DIS_EN RW

10

9

8

7

6

5

4 RG_VX O22_N DIS_EN RW

3

2

1

0

Name Type Reset

1

Bit(s) 11

Name RG_VRFCK_NDIS_EN

4

RG_VXO22_NDIS_EN

0000209E

1

Description Enables output power-down 1'b0: Disable output power-down 1'b1: Enable output power-down Enables output power-down 1'b0: Disable output power-down 1'b1: Enable output power-down

DCXO_ADLDO_BIAS_ELR_1

DCXO_ADLDO_BIAS ELR 1 Register

00000006

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

RW

0 RG_VR FCK_1_ NDIS_E N RW

1

0

RG_VB BCK_N DIS_EN

Name Type Reset Bit(s) 2

0

Name RG_VBBCK_NDIS_EN

RG_VRFCK_1_NDIS_EN

MediaTek Proprietary and Confidential.

Description LDO enables output power-down 1'b0: Disable output power-down 1'b1: Enable output power-down Enables output power-down 1'b0: Disable output power-down

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 934 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00002100

Description 1'b1: Enable output power-down

DUMMYLOAD_DSN_ID

DUMMYLOAD Design ID Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00002102

Description

DUMMYLOAD_DSN_REV0

DUMMYLOAD Design Revision Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00002104

Description

DUMMYLOAD_DSN_DBI

DUMMYLOAD Design Bank Information Register

00001200

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 935 of 1067

MT6359 PMIC Datasheet Confidential A 00002106

DUMMYLOAD_DSN_FPI

DUMMYLOAD Design Extra Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00002108

Description

DUMMYLOAD_ANA_CON0

DUMMYLOAD Control Register 0

00003300

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000210A

Description

ISINK0_CON1

ISINK0 Control Register 1

00007000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000210C

Description

ISINK1_CON1

ISINK1 Control Register 1

00007000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 936 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

0000210E

Description

ISINK_ANA1_SMPL

ISINKS ACD Interface 1 SIMPLE

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00002110

Description

ISINK_EN_CTRL_SMPL

ISINK Enable Control Simple

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00002112

Description

DUMMYLOAD_ELR_NUM

DUMMYLOAD Number of ELR Register

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 937 of 1067

MT6359 PMIC Datasheet Confidential A 00002114

DUMMYLOAD_ELR_0

DUMMYLOAD ELR 0 Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00002300

Description

AUD_TOP_ID

AUD_TOP Design ID Register

0000C800

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00002302

Description

AUD_TOP_REV0

AUD_TOP Design Revision Register 0

00001000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00002304

Description

AUD_TOP_DBI

AUD_TOP Design Bank Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 938 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00002306

Description

AUD_TOP_DXI

AUD_TOP Design Extra Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00002308

Description

AUD_TOP_CKPDN_TPM0

AUD_TOP Parameter 0

00001A0C

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000230A

Description

AUD_TOP_CKPDN_TPM1

AUD_TOP Parameter 1

00000122

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 939 of 1067

MT6359 PMIC Datasheet Confidential A 0000230C

AUD_TOP_CKPDN_CON0

AUDIO CLK Power Down Register 0

Bit Name Type Reset

31

30

29

28

27

26

25

24

Bit

15

14

13

12

11

10

9

8

RG_VO RG_VO W13M W32K_ _CK_P CK_PD DN N

Name

Type Reset

RW

RW

0

0

Name RG_VOW13M_CK_PDN

12

RG_VOW32K_CK_PDN

8

RG_AUD_INTRP_CK_PDN

7

RG_PAD_AUD_CLK_MISO_CK_PDN

6

RG_AUDNCP_CK_PDN

5

RG_ZCD13M_CK_PDN

2

RG_AUDIF_CK_PDN

1

RG_AUD_CK_PDN

0

RG_ACCDET_CK_PDN

0000230E

22

21

00000000 20

19

18

17

16

4

3

2

1

0

7 6 5 RG_PA RG_AU D_AUD RG_AU RG_ZC D_INTR _CLK_ DNCP_ D13M_ P_CK_P MISO_ CK_PD CK_PD DN CK_PD N N N RW RW RW RW 0

Bit(s) 13

23

0

0

RG_AC RG_AU RG_AU CDET_ DIF_CK D_CK_ CK_PD _PDN PDN N

0

RW

RW

RW

0

0

0

Description Powers down VOW13M_CK 0: Power on 1: Power down Powers down VOW32K_CK 0: Power on 1: Power down Powers down AUD_INTRP_CK 0: Power on 1: Power down Powers down PAD_AUD_CLK_MISO_CK 0: Power on 1: Power down Powers down AUDNCP_CK 0: Power on 1: Power down Powers down ZCD13M_CK 0: Power on 1: Power down Powers down AUDIF_CK 0: Power on 1: Power down Powers down AUD_CK 0: Power on 1: Power down Powers down ACCDET_CK 0: Power on 1: Power down

AUD_TOP_CKPDN_CON0_SET AUDIO CLK Power Down Register 0 SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 940 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00002310

Description

AUD_TOP_CKPDN_CON0_CLR AUDIO CLK Power Down Register 0 CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

19

18

17

16

1

0

Bit(s)

Name

00002312

Description

AUD_TOP_CKSEL_CON0

AUDIO CKSEL Control Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

Bit

15

14

13

12

11

10

9

8

7

6

5

4

Name Type Reset Bit(s) 3

2

Name RG_AUDIF_CK_CKSEL

0

0

Description Selects AUDIF_CK clock 1'b0: R_AUD_CLK_MOSI 1'b1: R_AUD26M_CK Selects AUD_CK clock 1'b0: R_AUD26M_CK 1'b1: R_AUD_CLK_MOSI

RG_AUD_CK_CKSEL

00002314

3 2 RG_AU RG_AU DIF_CK D_CK_ _CKSEL CKSEL RW RW

AUD_TOP_CKSEL_CON0_SET AUDIO CKSEL Control Register 0 SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 941 of 1067

MT6359 PMIC Datasheet Confidential A 00002316

AUD_TOP_CKSEL_CON0_CLR AUDIO CKSEL Control Register 0 CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00002318

Description

AUD_TOP_CKTST_CON0

AUDIO CKTST Control Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000231A

Description

AUD_TOP_CLK_HWEN_CON0 AUD_TOP Clock HWEN Control 0

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000231C

Description

AUD_TOP_CLK_HWEN_CON0 AUD_TOP Clock HWEN Control 0 SET _SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 942 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

0000231E

Description

AUD_TOP_CLK_HWEN_CON0 AUD_TOP Clock HWEN Control 0 CLR _CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00002320

Description

AUD_TOP_RST_CON0

AUDIO RST Control Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00002322

Description

AUD_TOP_RST_CON0_SET

AUD RST Control Register 0 SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 943 of 1067

MT6359 PMIC Datasheet Confidential A 00002324

AUD_TOP_RST_CON0_CLR

AUD RST Control Register 0 CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00002326

Description

AUD_TOP_RST_BANK_CON0 AUD RST BANK Control Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

21

20

19

18

17

16

4

3

2

1

0

Bit(s)

Name

00002328

Description

AUD_TOP_INT_CON0

AUDIO INT Control Register 0

Bit Name Type Reset

31

30

29

28

27

26

25

24

Bit

15

14

13

12

11

10

9

8

Name Type Reset

23

Name RG_INT_EN_ACCDET_EINT1

6

RG_INT_EN_ACCDET_EINT0

5

RG_INT_EN_ACCDET

0

RG_INT_EN_AUDIO

MediaTek Proprietary and Confidential.

00000000

7 6 5 RG_INT RG_INT RG_INT _EN_A _EN_A _EN_A CCDET_ CCDET_ CCDET EINT1 EINT0 RW RW RW 0

Bit(s) 7

22

0

0

RG_INT _EN_A UDIO RW 0

Description Enables ACCDET_EINT1 interrupt 0: Not issue interrupt 1: Issue interrupt Enables ACCDET_EINT0 interrupt 0: Not issue interrupt 1: Issue interrupt Enables ACCDET interrupt 0: Not issue interrupt 1: Issue interrupt Enables AUDIO interrupt 0: Not issue interrupt 1: Issue interrupt

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 944 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

0000232A

Description

AUD_TOP_INT_CON0_SET

AUD_TOP_INT Control Register 0 SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

RG_AUD_INT_CON0_SET W1 0 0 0 0

0

0

0

0

0

0

Bit(s) 15:0

0

0

0

0

0

Name RG_AUD_INT_CON0_SET

0000232C

Description 1'b0: Not set 1'b1: Set

AUD_TOP_INT_CON0_CLR

AUD_TOP_INT Control Register 0 CLR

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

RG_AUD_INT_CON0_CLR W1 0 0 0 0

0

0

0

0

0

0

20

19

18

17

16

4

3

2

1

0

Bit(s) 15:0

0

0

0

0

0

Name RG_AUD_INT_CON0_CLR

0000232E

Description 1'b0: Not clear 1'b1: Clear

AUD_TOP_INT_MASK_CON0 AUDIO INT MASK Control Register 0

Bit Name Type Reset

31

30

29

28

27

26

25

24

Bit

15

14

13

12

11

10

9

8

Name

Type Reset

23

Name RG_INT_MASK_ACCDET_EINT1

6

RG_INT_MASK_ACCDET_EINT0

MediaTek Proprietary and Confidential.

21

7 6 5 RG_INT RG_INT RG_INT _MASK _MASK _MASK _ACCD _ACCD _ACCD ET_EIN ET_EIN ET T1 T0 RW RW RW 0

Bit(s) 7

22

0

00000000

0

RG_INT _MASK _AUDI O RW 0

Description Masks ACCDET_EINT1 interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks ACCDET_EINT0 interrupt status 1'b0: Unmask interrupt status

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 945 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

5

RG_INT_MASK_ACCDET

0

RG_INT_MASK_AUDIO

00002330

Description 1'b1: Mask interrupt status Masks ACCDET interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status Masks AUDIO interrupt status 1'b0: Unmask interrupt status 1'b1: Mask interrupt status

AUD_TOP_INT_MASK_CON0_ AUD_TOP_INT Mask Control Register 0 SET SET

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

Bit(s) 7:0

RG_AUD_INT_MASK_CON0_SET W1 0

Name RG_AUD_INT_MASK_CON0_SET

00002332

0

0

0

0

Description 1'b0: Not set 1'b1: Set

AUD_TOP_INT_MASK_CON0_ AUD_TOP_INT Mask Control Register 0 CLR CLR

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

Bit(s) 7:0

0

00000000

21

20

19

18

17

16

5

4

3

2

1

0

0

0

RG_AUD_INT_MASK_CON0_CLR W1 0

Name RG_AUD_INT_MASK_CON0_CLR

MediaTek Proprietary and Confidential.

0

0

0

0

0

Description 1'b0: Not clear 1'b1: Clear

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 946 of 1067

MT6359 PMIC Datasheet Confidential A 00002334

AUD_TOP_INT_STATUS0

AUDIO INT STATUS0 Control Register

Bit Name Type Reset

31

30

29

28

27

26

25

24

Bit

15

14

13

12

11

10

9

8

Name

Type Reset Name RG_INT_STATUS_ACCDET_EINT1

6

RG_INT_STATUS_ACCDET_EINT0

5

RG_INT_STATUS_ACCDET

0

RG_INT_STATUS_AUDIO

00002336

0

00000000

20

19

18

17

16

4

3

2

1

0 RG_INT _STAT US_AU DIO W1C

0

0

AUD_TOP_INT_RAW_STATUS AUD_TOP_INT_RAW_STATUS0 Register 0 31

30

29

28

27

26

25

24

Bit

15

14

13

12

11

10

9

8

Name

Type Reset

5

21

Description ACCDET_EINT1 interrupt status 0: No interrupt issued 1: Interrupt issued ACCDET_EINT0 interrupt status 0: No interrupt issued 1: Interrupt issued ACCDET interrupt status 0: No interrupt issued 1: Interrupt issued AUDIO interrupt status 0: No interrupt issued 1: Interrupt issued

Bit Name Type Reset

6

22

7 6 5 RG_INT RG_INT RG_INT _STAT _STAT _STAT US_AC US_AC US_AC CDET_E CDET_E CDET INT1 INT0 W1C W1C W1C 0

Bit(s) 7

Bit(s) 7

23

23

22

21

7 6 5 RG_INT RG_INT RG_INT _RAW_ _RAW_ _RAW_ STATUS STATUS STATUS _ACCD _ACCD _ACCD ET_EIN ET_EIN ET T1 T0 RO RO RO 0

0

00000000

20

19

18

17

16

4

3

2

1

0

0

RG_INT _RAW_ STATU S_AUDI O RO 0

Name Description RG_INT_RAW_STATUS_ACCDET_EINT1 ACCDET_EINT1 raw interrupt status 0: No interrupt issued 1: Interrupt issued RG_INT_RAW_STATUS_ACCDET_EINT0 ACCDET_EINT0 raw interrupt status 0: No interrupt issued 1: Interrupt issued RG_INT_RAW_STATUS_ACCDET ACCDET raw interrupt status 0: No interrupt issued 1: Interrupt issued

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 947 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 0

Name RG_INT_RAW_STATUS_AUDIO

00002338

Description AUDIO raw interrupt status 0: No interrupt issued 1: Interrupt issued

AUD_TOP_INT_MISC_CON0 AUD_TOP_INT_MISC Control Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0 RG_AU D_TOP _INT_P OLARIT Y RW

Name Type Reset Bit(s) 0

0

Name RG_AUD_TOP_INT_POLARITY

0000233A

Description aud_top interrupt polarity select bit 0: aud_top_intr is high active 1: aud_top_intr is high active

AUD_TOP_MON_CON0

AUD_TOP_MON Control Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11 RG_AU D_CLK_ INT_M ON_FL AG_EN RW

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

Name Type Reset Bit(s) 11 10:3

Name RG_AUD_CLK_INT_MON_FLAG_EN RG_AUD_CLK_INT_MON_FLAG_SEL

MediaTek Proprietary and Confidential.

RG_AUD_CLK_INT_MON_FLAG_SEL

RW 0

0

0

0

0

Description Enables ACCDET monitor flag Selects ACCDET monitor flag

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 948 of 1067

MT6359 PMIC Datasheet Confidential A 00002380

AUDIO_DIG_DSN_ID

AUD_DIG Design ID Register

0000C900

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00002382

Description

AUDIO_DIG_DSN_REV0

AUD_DIG Design Revision Register 0

00001000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00002384

Description

AUDIO_DIG_DSN_DBI

AUD_DIG Design Bank Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00002386

Description

AUDIO_DIG_DSN_DXI

AUD_DIG Design Extra Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 949 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00002388

AFE_UL_DL_CON0 31

Bit Name Type Reset

Description

30

15 14 AFE_UL AFE_DL Name _LR_S _LR_S WAP WAP RW RW Type

Bit

Reset Bit(s) 15 14 0

0

Audio UL and DL Control Register 0

29

28

27

26

25

24

23

22

21

20

19

18

17

16

13

12

11

10

9

8

7

6

5

4

3

2

1

0 AFE_O N RW

0

0

Name AFE_UL_LR_SWAP AFE_DL_LR_SWAP AFE_ON

0000238A

00000000

Description Swaps audio UL L/R channel before UL SRC Swaps audio DL L/R channel before DAC FIFO Turns on audio UL and DL

AFE_DL_SRC2_CON0_L

AFE_DL_SRC2 Control Register 0 Low Part

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0 DL_2_S RC_ON _TMP_ CTL_PR E RW

Name Type Reset Bit(s) 0

0

Name DL_2_SRC_ON_TMP_CTL_PRE

0000238C

Description Turns on downlink

AFE_UL_SRC_CON0_H

AFE Uplink SRC Control Register 0 High Part

Bit Name Type Reset

31

30

29

28

27

26

25

24

Bit

15

14

13

12

11

10

9

8

0

0

0

0

0

0

Name Type Reset Bit(s) 13:11

7 C_TWO C_DIGMIC_PHASE_SEL_ C_DIGMIC_PHASE_SEL_ _DIGIT CH1_CTL CH2_CTL AL_MIC _CTL RW RW RW

Name C_DIGMIC_PHASE_SEL_CH1_CTL

MediaTek Proprietary and Confidential.

23

00000000

22

21

20

19

18

17

16

6

5

4

3

2

1

0

0

Description Selects 8 input phase latch

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 950 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 10:8 7

Name C_DIGMIC_PHASE_SEL_CH2_CTL C_TWO_DIGITAL_MIC_CTL

0000238E

Description Selects 8 input phase latch Turns on dual digital microphones mode 0: Turn off 1: Turn on

AFE_UL_SRC_CON0_L

AFE Uplink SRC Control Register 0 Low Part

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

Bit

15

14

13

12

11

10

9

8

7

6

DMIC_LOW_P Name OWER_MODE_ CTL

Type Reset Bit(s) 15:14

RW 0

0

6

DIGMIC_4P33M_SEL_CTL

5

DIGMIC_3P25M_1P625M_SEL_CTL

2

UL_LOOP_BACK_MODE_CTL

1

UL_SDM_3_LEVEL_CTL

0

UL_SRC_ON_TMP_CTL

MediaTek Proprietary and Confidential.

5 DIGMI DIGMI C_3P25 C_4P33 M_1P6 M_SEL 25M_S _CTL EL_CTL RW RW 0

Name DMIC_LOW_POWER_MODE_CTL

21

00000000

20

19

18

17

16

4

3

2

1

0

0

UL_LO UL_SD UL_SR OP_BA M_3_L C_ON_ CK_MO EVEL_C TMP_C DE_CTL TL TL RW

RW

RW

0

0

0

Description Digital mic low power mode 0: Original mode 1: 1.625M 48K mode 2: 812.5K low power mode 3: 406.25K low power mode Digmic 4P33M mode 0: Turn off 1: Turn on Digmic input mode 1 0: 3.25M mode 1: 1.625M mode Enables loopback mode from DL 0: Normal UL 1: Loopback from DL Selects SDM 3-level mode (digital MIC data path), first priority choice 0: Deselect SDM 3-level mode 1: Select SDM 3-level mode Turns on uplink SRC 0: Turn off 1: Turn on

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 951 of 1067

MT6359 PMIC Datasheet Confidential A 00002390

AFE_ADDA6_L_SRC_CON0_H AFE Uplink2 SRC Control Register 0 High Part

Bit Name Type Reset

31

30

29

28

27

26

25

24

Bit

15

14

13

12

11

10

9

8

0

0

0

0

0

0

Name

Type Reset Bit(s) 13:11 10:8 7

7 ADDA6 _C_TW ADDA6_C_DIGMIC_PH ADDA6_C_DIGMIC_PH O_DIGI ASE_SEL_CH1_CTL ASE_SEL_CH2_CTL TAL_MI C_CTL RW RW RW

Name ADDA6_C_DIGMIC_PHASE_SEL_CH1 _CTL ADDA6_C_DIGMIC_PHASE_SEL_CH2 _CTL ADDA6_C_TWO_DIGITAL_MIC_CTL

00002392

23

21

20

19

18

17

16

6

5

4

3

2

1

0

0

Description Selects 8 input phase latch Selects 8 input phase latch Turns on dual digital microphones mode 0: Turn off 1: Turn on

AFE_ADDA6_UL_SRC_CON0_L AFE Uplink2 SRC Control Register 0 Low Part

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

Bit

15

14

13

12

11

10

9

8

7

6

ADDA6_DMIC_ Name LOW_POWER_ MODE_CTL

Type Reset Bit(s) 15:14

00000000

22

RW 0

0

6

ADDA6_DIGMIC_4P33M_SEL_CTL

5

ADDA6_DIGMIC_3P25M_1P625M_S EL_CTL

2

ADDA6_UL_LOOP_BACK_MODE_CTL

1

ADDA6_UL_SDM_3_LEVEL_CTL

MediaTek Proprietary and Confidential.

5 ADDA6 ADDA6 _DIGMI _DIGMI C_3P25 C_4P33 M_1P6 M_SEL 25M_S _CTL EL_CTL RW RW 0

Name ADDA6_DMIC_LOW_POWER_MODE _CTL

21

00000000

20

19

18

17

16

4

3

2

1

0

0

ADDA6 ADDA6 ADDA6 _UL_LO _UL_SD _UL_SR OP_BA M_3_L C_ON_ CK_MO EVEL_C TMP_C DE_CTL TL TL RW

RW

RW

0

0

0

Description Digital mic low power mode 0: Original mode 1: 1.625M 48K mode 2: 812.5K low power mode 3: 406.25K low power mode Digmic 4P33M mode 0: Turn off 1: Turn on Digmic input mode 1 0: 3.25M mode 1: 1.625M mode Enables loopback mode from DL 0: Normal UL 1: Loopback from DL Selects SDM 3-level mode (digital MIC data path), first priority choice

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 952 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

0

Name

Description 0: Deselect SDM 3-level mode 1: Select SDM 3-level mode Turns on uplink SRC 0: Turn off 1: Turn on

ADDA6_UL_SRC_ON_TMP_CTL

00002394

AFE_TOP_CON0

AFE Top Control Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

Bit

15

14

13

12

11

10

9

8

7

6

5

Name Type Reset Bit(s) 4

Name ADDA6_MTKAIF_SINE_ON

ADDA6_UL_SINE_ON

2

MTKAIF_SINE_ON

1

UL_SINE_ON

0

DL_SINE_ON

00002396

AUDIO_TOP_CON0 29

28

27

26

25

24

23

22

21

Bit

15

14

13

12

11

10

9

8

7

6

5

0

0

0

MediaTek Proprietary and Confidential.

16

0

0

19

18

17

0

00000000

30

Name PDN_AFE_CTL

17

0

Audio Top Control Register 0

31

Type Reset

18

Description Enables MTKAIF sine table 0: MTKAIF from adda6 ul_fifo normal path 1: MTKAIF from sinetable Enables UL2 sine table 0: UL2 from normal path 1: UL2 from sinetable Enables MTKAIF sine table 0: MTKAIF from ul_fifo normal path. 1: MTKAIF from sinetable Enables UL sine table 0: UL from up8x_rxif normal path 1: UL from sine table Enables DL sine table 0: DL from up8x_rxif normal path. 1: DL from sinetable

Bit Name Type Reset

Name

19

4 3 2 1 0 ADDA6 ADDA6 MTKAI _MTKA UL_SIN DL_SIN _UL_SI F_SINE IF_SINE E_ON E_ON NE_ON _ON _ON RW RW RW RW RW 0

3

Bit(s) 7

20

20

16

4 3 2 1 0 PDN_A PDN_A PDN_I2 PWR_C PDN_R PDN_A PDN_D PDN_A DDA6_ FE_TES S_DL_C LK_DIS ESERVE FE_CTL AC_CTL DC_CTL ADC_C TMODE TL _CTL D TL L_CTL RW RW RW RW RW RW RW RW 0

0

0

0

0

Description Powers down AFE © 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 953 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

6

PDN_DAC_CTL

5

PDN_ADC_CTL

4

PDN_ADDA6_ADC_CTL

3 2

PDN_I2S_DL_CTL PWR_CLK_DIS_CTL

1

PDN_AFE_TESTMODEL_CTL

0

PDN_RESERVED

00002398 Bit Name Type Reset

AFE_MON_DEBUG0 31

30

15 14 AUDIO_SYS_T Name OP_MON_SWA P RW Type

Bit

Reset

Description 0: Not power down 1: Power down Powers down downlink 0: Not power down 1: Power down Powers down ADDA uplink 0: Not power down 1: Power down Powers down ADDA6 uplink 0: Not power down 1: Power down Reserved Disables total audio clk 0: Not power down 1: Power down Powers down some built-in testing model clock sources 0: Not power down 1: Power down 0: Not power down 1: Power down

0

0

AFE Monitor Output Debug Register 0

28

27

26

25

24

23

22

21

20

19

18

17

16

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

AUDIO_SYS_TOP_MON_SEL

AFE_MON_SEL

RW

RW

0

Bit(s) 15:14

Name AUDIO_SYS_TOP_MON_SWAP

12:8 7:0

AUDIO_SYS_TOP_MON_SEL AFE_MON_SEL

MediaTek Proprietary and Confidential.

00000000

29

0

0

0

0

0

0

0

0

0

Description Swaps monitor output from 32 bits to 8 bits 0: mon_out[7:0] 1: mon_out[15:8] 2: mon_out[23:16] 3: mon_out[31:24] Monitor output selection of audio system top level Monitor output selection of AFE level

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 954 of 1067

MT6359 PMIC Datasheet Confidential A 0000239A Bit Name Type Reset

AFUNC_AUD_CON0 31

30

29

28

15

14

13

12

A_FUNC Audio Control Register 0 27

26

25

24

23

22

21

0000D821 20

19

18

17

16

11 10 9 8 7 6 5 4 3 2 1 0 CCI_SC CCI_SP CCI_SP CCI_AU CCI_ZE CCI_AU CCI_AU CCI_AU CCI_AU CCI_AU CCI_SC CCI_AUDIO_FIFO_WPT RAMBL CCI_LC CCI_RA LT_SCR LT_SCR D_IDAC RO_PA D_SPLI D_SDM D_SDM D_SDM RAMBL Name D_ANA R ER_CG H_INV ND_EN MB_CL MB_O _TEST_ D_DISA T_TEST _MUTE _MUTE _7BIT_ CK_SEL ER_EN _EN K_ON N EN BLE _EN L R SEL RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type 1 1 0 1 1 0 0 0 0 0 1 0 0 0 0 1 Reset

Bit

Bit(s) 15

Name CCI_AUD_ANACK_SEL

14:12 11

CCI_AUDIO_FIFO_WPTR CCI_SCRAMBLER_CG_EN

10

CCI_LCH_INV

9

CCI_RAND_EN

8

CCI_SPLT_SCRMB_CLK_ON

7

CCI_SPLT_SCRMB_ON

6

CCI_AUD_IDAC_TEST_EN

5

CCI_ZERO_PAD_DISABLE

4

CCI_AUD_SPLIT_TEST_EN

3

CCI_AUD_SDM_MUTEL

2

CCI_AUD_SDM_MUTER

Description Analog 13M source inversion option 0: Not invert of AD_AUDDEC_13M_D5N_VCORE (or GPI) 1: Invert audio_fifo write pointer initial value Enables scrambler PA 0: Disable scrambler PA 1: Enable scrambler PA Selects SDM left channel out of phase 0: In-phase with right channel 1: Out-of-phase with right channel Enables scrambler random 0: Not random 1: Random Scrambler clock on 0: Off 1: On Enables scrambler output 0: Off 1: On Enables scrambler output test 0: Normal path 1: From test_in Disables scrambler zero padding 0: Zero padding 1: Disable zero padding Enables splitter test 0: Normal path 1: From test_in ([12:8]/[7:4]/[2:0]) Enables SDA output mute for left channel Controlled by AFUNC_AUD_CON1[15:8]. 0: Not control by AFUNC_AUD_CON1 1: Control by AFUNC_AUD_CON1 Enables sdm output mute for right channel Controlled by AFUNC_AUD_CON1[7:0] 0: Not control by AFUNC_AUD_CON1

D_CON1 1

0

CCI_SCRAMBLER_EN

MediaTek Proprietary and Confidential.

0: From splitter 1 1: From splitter 3 Enables scrambler 0: Disable

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 955 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

0000239C

Description 1: Enable

AFUNC_AUD_CON1

A_FUNC Audio Control Register 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

AUD_SDM_TEST_L RW 0 0 0 0

0

AUD_SDM_TEST_R RW 0 0 0 0

0

0

Bit(s) 15:8 7:0

0

Name AUD_SDM_TEST_L AUD_SDM_TEST_R

0000239E

0

0

0

Description SDM mute test value for left channel SDM mute test value for right channel

AFUNC_AUD_CON2

A_FUNC Audio Control Register 2

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

Bit

15

14

13

12

11

10

9

8

7

Name

Type Reset Bit(s) 8

6 CCI_AU R_SPLI CCI_AU D_DAC TTER_T D_DAC _ANA_ RUNC_ _ANA_ RSTB_S RND MUTE EL RW RW RW 1

Name R_SPLITTER_TRUNC_RND

7

CCI_AUD_DAC_ANA_MUTE

6

CCI_AUD_DAC_ANA_RSTB_SEL

4

CCI_AUDIO_FIFO_CLKIN_INV

3

CCI_AUDIO_FIFO_ENABLE

2

CCI_ACD_MODE

1

CCI_AFIFO_CLK_PWDB

MediaTek Proprietary and Confidential.

22

0

0

00000100

21

20

19

18

17

16

5

4

3

2

1

0

CCI_AU CCI_AU CCI_AC CCI_AFI CCI_AC DIO_FI DIO_FI D_MO FO_CLK D_FUN FO_CLK FO_EN DE _PWDB C_RSTB IN_INV ABLE RW

RW

RW

RW

RW

0

0

0

0

0

Description Splitter trunction uses round mode. 0: No round 1: Round Analog DAC interface mute (RG) control 0: Analog DAC interface input from aud_dac_ana output (normal) 1: Analog DAC interface input from fixed mute patterns Enables aud_dac_ana soft_rstb source selection 0: aud_dac_ana reset by global rstb 1: aud_dac_ana reset by global rstb and cci_acd_func_rstb Selects SDM 6.5M clock phase 0: In-phase 1: Out-of-phase Enables SDM audio_fifo 0: Disable 1: Enable SDM audio_fifo analog FT test mode 0: Normal path 1: Test path from GPI, clock and data will be from GPI. See sdm_testck_src_sel for selection. SDM audio_fifo clock power down bit

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 956 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

0

Name

CCI_ACD_FUNC_RSTB

000023A0 Bit Name Type Reset

Description 0: Power down 1: Power on SDM audio_fifo rstb bit 0: Reset 1: Released

AFUNC_AUD_CON3 31

30

29

28

15 14 13 12 SDM_A NA13 SDM_ANA13M_TESTCK Name M_TES _SRC_SEL TCK_SE L RW RW Type

Bit

Reset

0

0

0

A_FUNC Audio Control Register 3 26

25

24

23

22

21

20

19

18

17

16

11

10

9

8

7

6

5

4

3

2

1

0

0

Bit(s) 15

Name SDM_ANA13M_TESTCK_SEL

14:12

SDM_ANA13M_TESTCK_SRC_SEL

10:8

SDM_TESTCK_SRC_SEL

6:4

DIGMIC_TESTCK_SRC_SEL

MediaTek Proprietary and Confidential.

00000000

27

SDM_TESTCK_SRC_SEL

DIGMIC_TESTCK_SRC_S EL

DIGMI C_TEST CK_SEL

RW

RW

RW

0

0

0

0

0

0

0

Description Selects SDM testck from GPI 0: Normal path from digital output 1: Testing path from GPI. See the descriptions of sdm_ana13M_testck_src_sel for details. Selects different GPI as SDM testck source 0: test_ck_i[3] 1: test_ck_i[2] 2: test_ck_i[1] 3: test_ck_i[0] 4: test_in_i[0] 5: test_in_i[1] 6: test_in_i[3] 7: test_in_i[5] Selects different GPI as sdm testck source 0: test_ck_i[3] 1: test_ck_i[2] 2: test_ck_i[1] 3: test_ck_i[0] 4: test_in_i[0] 5: test_in_i[1] 6: test_in_i[3] 7: test_in_i[5] Selects different GPI as digmic testck source 0: test_ck_i[3] 1: test_ck_i[2] 2: test_ck_i[1] 3: test_ck_i[0] 4: test_in_i[2] 5: test_in_i[4] 6: test_in_i[6] 7: test_in_i[7]

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 957 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 0

Name DIGMIC_TESTCK_SEL

000023A2

Description Selects digmic testck from GPI 0: Normal path from digital output 1: Testing path from GPI. See the descriptions of digmic_testck_src_sel for details.

AFUNC_AUD_CON4

A_FUNC Audio Control Register 4

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

Bit

15

14

13

12

11

10

9

8

7

UL_FIF O_WCL K_INV

Name

Type Reset Bit(s) 8

RW 0

Name UL_FIFO_WCLK_INV

6

UL_FIFO_DIGMIC_WDATA_TESTSRC_ SEL

5

UL_FIFO_WDATA_TESTEN

4

UL_FIFO_WDATA_TESTSRC_SEL

3

UL_FIFO_WCLK_6P5M_TESTCK_SEL

2:0

UL_FIFO_WCLK_6P5M_TESTCK_SRC_ SEL

MediaTek Proprietary and Confidential.

22

21

00000000 20

19

18

17

16

6 5 4 3 2 1 0 UL_FIF UL_FIF UL_FIF O_DIG UL_FIF O_WCL O_WD MIC_W O_WD K_6P5 UL_FIFO_WCLK_6P5M_ ATA_TE DATA_ ATA_TE M_TES TESTCK_SRC_SEL STSRC_ TESTSR STEN TCK_SE SEL C_SEL L RW RW RW RW RW 0

0

0

0

0

0

0

Description Selects to invert UL FIFO wclk 0: Not invert 1: Invert UL FIFO wclk Selects UL FIFO digmic WDATA from GPI (test_in[1:0]) or tri-gen ch1: test_in[1] ch2: test_in[0] 0: Testing path from test input GPI, i.e. left channel ch1 = test_in[1]; right channel ch2 = test_in[0] 1: Testing path from built-in tri-gen. ch1 uses tri_out[1]; ch2 uses tri_out[0]. Selects UL FIFO wdata from others 0: Normal path from analog output 1: Testing path from test input. See the descriptions of ul_fifo_wdata_testsrc_sel for details. Enables GPI as UL FIFO write testck source 0: Test input from GPI, i.e. left channel ch1[4:0] = test_in[4:0]; right channel ch2[4:0] = test_in[4:0] 1: Test input from tri-gen; both ch1 and ch2 use the same inputs from trigen. Enables GPI as UL FIFO write testck source 0: Normal path from analog 6p5M 1: From testck described in ul_fifo_wclk_6p5m_testck_src_sel Selects different GPI as UL FIFO write testck source 0: test_ck_i[2] 1: test_ck_i[2] 2: test_ck_i[1] 3: test_ck_i[0] 4: test_in_i[5] 5: test_in_i[6] 6: test_in_i[7] 7: test_in_i[0]

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 958 of 1067

MT6359 PMIC Datasheet Confidential A 000023A4

AFUNC_AUD_CON5

Bit Name Type Reset

31

30

Bit Name Type Reset

15

14

Bit(s) 15:8 7:0

0

0

A_FUNC Audio Control Register 5

28

27

26

25

24

23

22

21

20

19

18

17

16

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

R_AUD_DAC_NEG_LARGE_MONO RW 0 0 0 0 0

0

0

R_AUD_DAC_POS_LARGE_MONO RW 0 0 0 0

Name R_AUD_DAC_POS_LARGE_MONO R_AUD_DAC_NEG_LARGE_MONO

000023A6

00000000

29

0

0

Description pos_lareg to DAC neg_lareg to DAC

AFUNC_AUD_CON6

A_FUNC Audio Control Register 6

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

Bit

15

14

13

12

11

10

9

8

7

6

5

4

0

0

0

0

0

0

0

0

0

0

0

0

Name Type Reset Bit(s) 15:12 11:8 7:6 5:4 3

19

3 R_AUD R_AUD_DAC_P R_AUD_DAC_N R_AUD_DAC_POS_SMALL_MO R_AUD_DAC_NEG_SMALL_MO _DAC_ OS_TINY_MON EG_TINY_MON NO NO MONO O O _SEL RW RW RW RW RW

Name R_AUD_DAC_POS_SMALL_MONO R_AUD_DAC_NEG_SMALL_MONO R_AUD_DAC_POS_TINY_MONO R_AUD_DAC_NEG_TINY_MONO R_AUD_DAC_MONO_SEL

1

R_AUD_DAC_3TH_SEL

0

R_AUD_DAC_SW_RSTB

MediaTek Proprietary and Confidential.

0

18

2

17

16

1 0 R_AUD R_AUD _DAC_ _DAC_ 3TH_SE SW_RS L TB RW RW 0

1

Description pos_small to DAC neg_small to DAC pos_tiny to DAC neg_tiny to DAC Uses mono register value to test DAC 0: Not use mono register value 1: Use mono register vaule Selects 3rd aud DAC channel 0: LCH 1: RCH DAC sgen sync soft reset 0: Reset DAC sgen 1: Not reset DAC sgen

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 959 of 1067

MT6359 PMIC Datasheet Confidential A 000023A8

AFUNC_AUD_CON7

A_FUNC Audio Control Register 7

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

Bit

15

14

13

12

11

10

9

8

7

UL2_DI UL2_FI UL2_DIGMIC_TESTCK_S GMIC_ FO_WC RC_SEL TESTCK LK_INV _SEL

Name

Type Reset Bit(s) 12:10

RW 0

0

Name UL2_DIGMIC_TESTCK_SRC_SEL

9

UL2_DIGMIC_TESTCK_SEL

8

UL2_FIFO_WCLK_INV

6

UL2_FIFO_DIGMIC_WDATA_TESTSRC _SEL

5

UL2_FIFO_WDATA_TESTEN

4

UL2_FIFO_WDATA_TESTSRC_SEL

3

UL2_FIFO_WCLK_6P5M_TESTCK_SEL

in ul_fifo_wclk_6p5m_testck_src_sel 2:0 UL2_FIFO_WCLK_6P5M_TESTCK_SRC _SEL

MediaTek Proprietary and Confidential.

0

RW

RW

0

0

22

21

00000000 20

19

18

17

16

6 5 4 3 2 1 0 UL2_FI UL2_FI UL2_FI FO_DIG UL2_FI FO_WC FO_WD MIC_W FO_WD LK_6P5 UL2_FIFO_WCLK_6P5M ATA_TE DATA_ ATA_TE M_TES _TESTCK_SRC_SEL STSRC_ TESTSR STEN TCK_SE SEL C_SEL L RW RW RW RW RW 0

0

0

0

0

0

0

Description Selects different GPI as digmic testck source 0: test_ck_i[3] 1: test_ck_i[2] 2: test_ck_i[1] 3: test_ck_i[0] 4: test_in_i[2] 5: test_in_i[4] 6: test_in_i[6] 7: test_in_i[7] Selects digmic testck from GPI 0: Normal path from digital output 1: Testing path from GPI. See descriptions of digmic_testck_src_sel for details. Selects to invert UL2 FIFO wclk 0: Not invert 1: Invert UL FIFO wclk Selects ul2 FIFO digmic WDATA from GPI (test_in[1:0]) or tri-gen: ch1: test_in[1] ch2: test_in[0] 0: Testing path from test input GPI, i.e. left channel ch1 = test_in[1]; right channel ch2 = test_in[0] 1: Testing path from built-in tri-gen, ch1 uses tri_out[1]; ch2 uses tri_out[0]. Selects UL2 FIFO WDATA from others 0: Normal path from analog output 1: Testing path from test input. See descriptions of ul_fifo_wdata_testsrc_sel for details. Enables GPI as UL2 FIFO write testck source 0: Test input from GPI, i.e. left channel ch1[4:0] = test_in[4:0]; right channel ch2[4:0] = test_in[4:0] 1: Test input from tri-gen; both ch1 and ch2 use the same inputs from trigen. Enables GPI as UL2 FIFO write testck source 0: Normal path from analog 6P5M Selects different GPI as UL2 FIFO write testck source 0: test_ck_i[2] 1: test_ck_i[2] 2: test_ck_i[1] 3: test_ck_i[0]

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 960 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

000023AA

Description 4: test_in_i[5] 5: test_in_i[6] 6: test_in_i[7] 7: test_in_i[0]

AFUNC_AUD_CON8

A_FUNC Audio Control Register 8

Bit Name Type Reset

31

30

29

28

27

26

Bit

15

14

13

12

11

10

Name Type Reset Name SPLITTER2_DITHER_EN

8

SPLITTER1_DITHER_EN

Bit Name Type Reset

AFUNC_AUD_CON9 31

30

29

28

15

14

13

12

22

21

20

19

18

17

16

7

6

5

4

3

2

1

0

SPLITTER2_DITHER_GAIN

SPLITTER1_DITHER_GAIN

RW

RW

0

0

0

0

0

0

0

20

19

18

17

A_FUNC Audio Control Register 10 27

26

25

11 10 9 CCI_SC CCI_AU RAMBL CCI_LC CCI_RA D_ANA CCI_AUDIO_FIFO_WPT ER_CG H_INV_ ND_EN Name CK_SEL R_2ND _EN_2 2ND _2ND _2ND ND RW RW RW RW RW Type 1 1 0 1 1 0 0 Reset

Bit

0

00000000

23

24

23

8 CCI_SP LT_SCR MB_CL K_ON_ 2ND RW 0

7

22

21

0000D821

Name CCI_AUD_ANACK_SEL_2ND

Description Analog 13M source inversion option 0: Not invert AD_AUDDEC_13M_D5N_VCORE (or GPI)

14:12 11

CCI_AUDIO_FIFO_WPTR_2ND CCI_SCRAMBLER_CG_EN_2ND

audio_fifo write pointer initial value Enables scrambler PA 0: Disable scrambler PA 1: Enable scrambler PA Selects SDM left channel out of phase

CCI_LCH_INV_2ND

MediaTek Proprietary and Confidential.

16

6 5 4 3 2 1 0 CCI_AU CCI_ZE CCI_AU CCI_AU CCI_SP CCI_AU CCI_AU CCI_SC D_IDAC RO_PA D_SPLI D_SDM LT_SCR D_SDM D_SDM RAMBL _TEST_ D_DISA T_TEST _7BIT_ MB_O _MUTE _MUTE ER_EN EN_2N BLE_2N _EN_2 SEL_2N N_2ND L_2ND R_2ND _2ND D D ND D RW RW RW RW RW RW RW RW 0 0 1 0 0 0 0 1

Bit(s) 15

10

0

Description Enables splitter 2 dither 0: Disable 1: Enable Enables splitter 1 dither 0: Disable 1: Enable Splitter 2 dither gain Splitter 1 dither gain

SPLITTER2_DITHER_GAIN SPLITTER1_DITHER_GAIN

000023AC

24

9 8 SPLITTE SPLITTE R2_DIT R1_DIT HER_E HER_E N N RW RW 0

Bit(s) 9

7:4 3:0

25

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 961 of 1067

left channel right channel

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

9

CCI_RAND_EN_2ND

8

CCI_SPLT_SCRMB_CLK_ON_2ND

7

CCI_SPLT_SCRMB_ON_2ND

6

CCI_AUD_IDAC_TEST_EN_2ND

5

CCI_ZERO_PAD_DISABLE_2ND

4

CCI_AUD_SPLIT_TEST_EN_2ND

3

CCI_AUD_SDM_MUTEL_2ND

2

CCI_AUD_SDM_MUTER_2ND

1

CCI_AUD_SDM_7BIT_SEL_2ND

0

CCI_SCRAMBLER_EN_2ND

000023AE

Description 0: In-phase with right channel 1: Out-of-phase with right channel Enables scrambler random 0: Not random 1: Random Scrambler clock on 0: Off 1: On Enables scrambler output 0: Off 1: On Enables scrambler output test 0: Normal path 1: From test_in Disables scrambler zero padding 0: Zero padding 1: Disable zero padding Enables splitter test 0: Normal path 1: From test_in ([12:8]/[7:4]/[2:0]) Enables SDM output mute for left channel Controlled by AFUNC_AUD_CON10[15:8]. 0: Not control by AFUNC_AUD_CON10 1: Control by AFUNC_AUD_CON10 Enables sdm output mute for right channel Controlled by AFUNC_AUD_CON10[7:0] 0: Not control by AFUNC_AUD_CON10 1: Control by AFUNC_AUD_CON10 Selects splitter 0: From splitter 1 1: From splitter 3 Enables scrambler 0: Disable 1: Enable

AFUNC_AUD_CON10

A_FUNC Audio Control Register 11

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

AUD_SDM_TEST_L_2ND RW 0 0 0 0

0

AUD_SDM_TEST_R_2ND RW 0 0 0 0

0

0

Bit(s) 15:8 7:0

0

Name

MediaTek Proprietary and Confidential.

0

0

0

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 962 of 1067

MT6359 PMIC Datasheet Confidential A 000023B0

AFUNC_AUD_CON11

A_FUNC Audio Control Register 12

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

Bit

15

14

13

12

11

10

9

8

7

Name

Type Reset Bit(s) 8

6 CCI_AU R_SPLI CCI_AU D_DAC TTER_T D_DAC _ANA_ RUNC_ _ANA_ RSTB_S RND_2 MUTE_ EL_2N ND 2ND D RW RW RW 1

Name R_SPLITTER_TRUNC_RND_2ND

7

CCI_AUD_DAC_ANA_MUTE_2ND

6

CCI_AUD_DAC_ANA_RSTB_SEL_2ND

4

CCI_AUDIO_FIFO_CLKIN_INV_2ND

3

CCI_AUDIO_FIFO_ENABLE_2ND

2

CCI_ACD_MODE_2ND

1

CCI_AFIFO_CLK_PWDB_2ND

0

CCI_ACD_FUNC_RSTB_2ND

000023B2

AFUNC_AUD_CON12

Bit Name Type Reset

29

28

27

26

Bit

15

14

13

12

11

10

MediaTek Proprietary and Confidential.

20

19

18

17

16

5

4

3

2

1

0

CCI_AU CCI_AU CCI_AC CCI_AFI CCI_AC DIO_FI DIO_FI D_MO FO_CLK D_FUN FO_CLK FO_EN DE_2N _PWDB C_RSTB IN_INV ABLE_2 D _2ND _2ND _2ND ND

0

RW

RW

RW

RW

RW

0

0

0

0

0

A_FUNC Audio Control Register 18

30

Type Reset

0

00000100

21

Description Splitter trunction use round mode 0: No round 1: Round Analog DAC interface mute (RG) control 0: Analog DAC interface input from aud_dac_ana output (normal) 1: Analog DAC interface input from fixed mute patterns. Enables aud_dac_ana soft_rstb source selection 0: aud_dac_ana reset by global rstb 1: aud_dac_ana reset by global rstb and cci_acd_func_rstb Selects SDM 6.5M clock phase 0: In-phase 1: Out-of-phase Enables SDM audio_fifo 0: Disable 1: Enable SDM audio_fifo analog FT test mode 0: Normal path 1: Test path from GPI, clock and data will be from GPI. See sdm_testck_src_sel for selection. SDM audio_fifo clock power down bit 0: Power down 1: Power on SDM audio_fifo RSTB bit 0: Reset 1: Released

31

Name

22

25

24

23

22

21

00000000 20

19

18

17

16

9 8 7 6 5 4 3 2 1 0 SPLITTE SPLITTE R2_DIT R1_DIT SPLITTER2_DITHER_GAIN_2ND SPLITTER1_DITHER_GAIN_2ND HER_E HER_E N_2ND N_2ND RW RW RW RW 0

0

0

0

0

0

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

0

0

0

0

Page 963 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 9

Name SPLITTER2_DITHER_EN_2ND

8

SPLITTER1_DITHER_EN_2ND

7:4 3:0

SPLITTER2_DITHER_GAIN_2ND SPLITTER1_DITHER_GAIN_2ND

000023B4

AFUNC_AUD_MON0

Bit Name Type Reset

31

30

29

Bit Name Type Reset

15

14

13

Bit(s) 15:8 7:0

Description Enables splitter 2 dither 0: Disable 1: Enable Enables splitter 1 dither 0: Disable 1: Enable Splitter 2 dither gain Splitter 1 dither gain

0

0

0

A_FUNC Audio Monitor Register 0

28

27

26

25

24

23

22

21

12

11

10

9

8

7

6

5

AUD_SCR_OUT_L RO 0 0

0

Name AUD_SCR_OUT_L AUD_SCR_OUT_R

000023B6

0

0

0

0

0

00000000 20

19

18

17

16

4

3

2

1

0

0

0

0

AUD_SCR_OUT_R RO 0 0

Description Scrambler/splitter debug output to read bus Scrambler/splitter debug output to read bus

AFUNC_AUD_MON1

A_FUNC Audio Monitor Register 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

AUD_SCR_OUT_L_2ND RO 0 0 0 0

0

AUD_SCR_OUT_R_2ND RO 0 0 0 0

0

0

Bit(s) 15:8 7:0

0

Name AUD_SCR_OUT_L_2ND AUD_SCR_OUT_R_2ND

000023B8 Bit Name Type Reset

15 ASYNC _TEST_ Name OUT_B CK RU Type

Bit

Reset

0

0

Description Scrambler/splitter debug output to read bus Scrambler/splitter debug output to read bus

AUDRC_TUNE_MON0 31

0

Analog Monitor Register 0

00000000

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

MediaTek Proprietary and Confidential.

RGS_AUDRCTUNE1READ

RGS_AUDRCTUNE0READ

RU 0

0

0

RU 0

0

0

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

0

0

0

0

Page 964 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 15 12:8 4:0

Name ASYNC_TEST_OUT_BCK RGS_AUDRCTUNE1READ RGS_AUDRCTUNE0READ

000023BA

Description AUDIOEN RC TUNE OUTPUT TO READ for 1 channel AUDIOEN RC TUNE OUTPUT TO READ for 0 channel

AFE_ADDA_MTKAIF_FIFO_CF AFE MTKAIF FIFO Register 0 G0

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000023BC

Description

AFE_ADDA_MTKAIF_FIFO_LO AFE MTKAIF FIFO Monitor 0 G_MON1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000023BE

Description

AFE_ADDA_MTKAIF_MON0

AFEMTKAIF_V3 Monitor Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 965 of 1067

MT6359 PMIC Datasheet Confidential A 000023C0

AFE_ADDA_MTKAIF_MON1

AFEMTKAIF_V3 Monitor Register 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000023C2

Description

AFE_ADDA_MTKAIF_MON2

AFEMTKAIF_V3 Monitor Register 2

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000023C4

Description

AFE_ADDA6_MTKAIF_MON3 AFEMTKAIF_V3 Monitor Register 3

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000023C6

Description

AFE_ADDA_MTKAIF_MON4

AFEMTKAIF_V3 Monitor Register 4

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 966 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

000023C8

Description

AFE_ADDA_MTKAIF_MON5

AFEMTKAIF_V3 Monitor Register 5

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000023CA

Description

AFE_ADDA_MTKAIF_CFG0

AFE MTKAIF_V3 Control Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000023CC

Description

AFE_ADDA_MTKAIF_RX_CFG AFEMTKAIF_V3 RXIF Protocol 1 Control Register 0 0

00000730

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

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Page 967 of 1067

MT6359 PMIC Datasheet Confidential A 000023CE

AFE_ADDA_MTKAIF_RX_CFG AFEMTKAIF_V3 RXIF Protocol 2 Control Register 1 0

00004330

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000023D0

Description

AFE_ADDA_MTKAIF_RX_CFG AFEMTKAIF_V3 RXIF Protocol 2 Control Register 2 2

00000003

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000023D2

Description

AFE_ADDA_MTKAIF_RX_CFG AFEMTKAIF_V3 RXIF Protocol 2 Control Register 3 3

00000030

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 968 of 1067

MT6359 PMIC Datasheet Confidential A 000023D4

AFE_ADDA_MTKAIF_SYNCW AFEMTKAIF_V3 Protocol 2 Syncword Control ORD_CFG0 Register0

00000063

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000023D6

Description

AFE_ADDA_MTKAIF_SYNCW AFEMTKAIF_V3 Protocol 2 Syncword Control ORD_CFG1 Register1

00006363

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

21

20

19

18

17

16

3 R_AUD _SDM_ MUTE_ L_2ND RW

2 R_AUD _SDM_ MUTE_ R_2ND RW

1

0

0

0

Bit(s)

Name

000023D8

Description

AFE_SGEN_CFG0

AFE SGEN CON0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

Bit

15

14

13

12

11

10

9

8

7

6

0

0

Name Type Reset Bit(s) 15:12

C_AMP_DIV_CH1_CTL RW 0

0

0

0

Name C_AMP_DIV_CH1_CTL

MediaTek Proprietary and Confidential.

5 4 R_AUD R_AUD C_DAC C_MUT _SDM_ _SDM_ _EN_CT E_SW_ MUTE_ MUTE_ L CTL L R RW RW RW RW 0

0

Description Amplitude setting of channel 1 (SGEN) 0: 0 dB full scale 1: -6 dB 2: -12 dB 3: -18 dB 4: -24 dB 5: -30 dB 6: -36 dB 7: -42 dB 8: -48 dB

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 969 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

7

C_DAC_EN_CTL

6

C_MUTE_SW_CTL

5

R_AUD_SDM_MUTE_L

4

R_AUD_SDM_MUTE_R

3

R_AUD_SDM_MUTE_L_2ND

2

R_AUD_SDM_MUTE_R_2ND

000023DA Bit Name Type Reset

AFE_SGEN_CFG1 31

30

15 14 C_SGE C_SGE N_RCH N_RCH Name _INV_5 _INV_8 BIT BIT RW RW Type

Bit

Reset Bit(s) 15 14 4:0

Description 9: -54 dB 10: -60 dB 11: -66 dB 12: -72 dB 13: -78 dB 14: -84 dB 15: -90 dB Makes voice DAC output the test sine wave Configures signal generator (SGEN). 0: Disable sine waves output 1: Voice DAC inputs are sine waves Mutes switch (SGEN) 0: Turn on sine wave output in this test mode 1: Mute sine wave output Mutes aud_sdm lch data 0: Not mute 1: Mute aud_sdm lch Mutes aud_sdm rch data 0: Not mute 1: Mute aud_sdm rch Mutes aud_sdm_2nd lch data 0: Not mute 1: Mute aud_sdm_2nd lch Mutes aud_sdm_2nd rch data 0: Not mute 1: Mute aud_sdm_2nd rch

0

AFE SGEN CON1

00000001

29

28

27

26

25

24

23

22

21

20

19

18

17

16

13

12

11

10

9

8

7

6

5

4

3

2

1

0

C_FREQ_DIV_CH1_CTL RW

0

0

Name C_SGEN_RCH_INV_5BIT C_SGEN_RCH_INV_8BIT C_FREQ_DIV_CH1_CTL

0

0

0

1

Description Inverts RCH sgen 5-bit data output Inverts RCH sgen 8-bit data output Frequency setting of channel 1 1X~15X for voice, 1X~31X for audio Frequency = Sampling rate/64*FREQ_DIV (SGEN)

32K -> 64K; 48K -> 96K); DL (8xFS)

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 970 of 1067

MT6359 PMIC Datasheet Confidential A 000023DC

AFE_ADC_ASYNC_FIFO_CFG AFE_ADC_SYNC_FIFO_CFG

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

Bit

15

14

13

12

11

10

9

8

7

6

Name

Type Reset Bit(s) 5

00000010 21

5 4 RG_UL RG_UL _ASYN _ASYN C_FIFO C_FIFO _SOFT_ _SOFT_ RST_EN RST RW RW 0

Name RG_UL_ASYNC_FIFO_SOFT_RST_EN

4

RG_UL_ASYNC_FIFO_SOFT_RST

1

RG_AMIC_UL_ADC_CLK_SEL

000023DE

20

19

18

17

16

3

2

1

0

RG_AM IC_UL_ ADC_C LK_SEL RW

1

0

Description Selects UL async FIFO soft reset 0: UL async FIFO uses global reset. 1: UL async FIFO uses soft reset. UL soft reset control 0: UL FIFO soft reset 1: Normal Selects ADC 0/1 channel latch clk 0: Select ana_ch0 ck 1: Select ana_ch1 ck

AFE_ADC_ASYNC_FIFO_CFG1 AFE_ADC_SYNC_FIFO_CFG1

00000010

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5 RG_UL 2_ASY NC_FIF O_SOF T_RST_ EN RW

4

3

2

1

0

RG_UL 2_ASY NC_FIF O_SOF T_RST

0

1

Name

Type Reset Bit(s) 5

4

Name RG_UL2_ASYNC_FIFO_SOFT_RST_EN

RG_UL2_ASYNC_FIFO_SOFT_RST

MediaTek Proprietary and Confidential.

RW

Description Selects UL2 async FIFO soft reset 0: UL2 async FIFO uses global reset. 1: UL2 async FIFO uses soft reset. UL2 soft reset control 0: UL2 FIFO soft reset 1: Normal

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 971 of 1067

MT6359 PMIC Datasheet Confidential A 000023E0

AFE_DCCLK_CFG0

AFE_DCCLK_CFG0

00000FE2

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

1

1

1

1

1

Name

DCCLK_DIV

Type Reset Bit(s) 15:5 4 3:2

0

0

0

0

1

RW 1

Name DCCLK_DIV

DCCLK_PDN

0

DCCLK_GEN_ON

000023E2

AFE_DCCLK_CFG1

AFE_DCCLK_CFG1

Bit Name Type Reset

31

30

29

28

27

26

25

Bit

15

14

13

12

11

10

9

Name Type Reset Bit(s) 11:10

9 8

7:4

Name RESYNC_SRC_SEL

RESYNC_SRC_CK_INV DCCLK_RESYNC_BYPASS

MediaTek Proprietary and Confidential.

24

8 DCCLK_ RESYN RESYNC_SRC_S RESYN C_SRC_ EL C_BYP CK_INV ASS RW RW RW 0

DCCLK_PHASE_SEL

0 DCCLK DCCLK_ DCCLK_REF_CK DCCLK_ _GEN_ INV _SEL PDN ON RW RW RW RW 0 0 0 1 0

Description DCCLK divider: DCCLK = 13M(12.854M)/(div + 1) dcclk inverter Selects DCCLK reference clock 00: Normal 26M/2 01: VOW 12.854M DCCLK power down control 0: DCCLK output 1: DCCLK power down Enables DCCLK generation 0: Disable 1: Enable

DCCLK_INV DCCLK_REF_CK_SEL

1

16

0

0

1

00000100

23

22

21

20

19

18

17

16

7

6

5

4

3

2

1

0

DCCLK_PHASE_SEL RW 0

0

0

0

Description Selects DCCLK resync clock 00: adcsync_clk 01: VOW 12.854M 10: buck_oscclk 11: 26M clock DCCLK resync clock inverter DCCLK bypass resync 0: Resync 1: Bypass resync Selects DCCLK resync phase

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 972 of 1067

MT6359 PMIC Datasheet Confidential A 000023E4

AUDIO_DIG_CFG

AFE MTK ADDA NEWIF Top Control Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000023E6

Description

AUDIO_DIG_CFG1

AFE MTK ADDA NEWIF Top Control Register 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000023E8

Description

AFE_AUD_PAD_TOP

AFE MTK ADDA NEWIF Top Control Register 2

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000023EA

Description

AFE_AUD_PAD_TOP_MON

AFE MTK ADDA NEWIF Top Monitor Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 973 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

000023EC

Description

AFE_AUD_PAD_TOP_MON1 AFE MTK ADDA NEWIF Top Monitor Register 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000023EE

Description

AFE_AUD_PAD_TOP_MON2 AFE MTK ADDA NEWIF Top Monitor Register 2

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000023F0

Description

AFE_DL_NLE_CFG

AFE NLE Control Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 974 of 1067

MT6359 PMIC Datasheet Confidential A 000023F2

AFE_DL_NLE_MON

AFE_DL_NLE_MON

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000023F4

Description

AFE_CG_EN_MON

AFE_CG_EN_MON

0000003F

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000023F6

Description

AFE_MIC_ARRAY_CFG

Mic Array Control Register

00000186

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000023F8

Description

AFE_CHOP_CFG0

AFE_CHOP_CFG0

000001A0

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0 RG_CH OP_DI V_EN RW

Name Type Reset

MediaTek Proprietary and Confidential.

RG_CHOP_DIV_SEL RW 1

1

0

1

0

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

0

Page 975 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 8:4

Name RG_CHOP_DIV_SEL

0

RG_CHOP_DIV_EN

000023FA

Description Chopping clock divider (26M/2)/(2^N), N = 0~31 Enables chopping clock divider

AFE_MTKAIF_MUX_CFG

AFE_MTKAIF_MUX_CFG

00001E04

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

Bit

15

14

13

12 RG_AD DA6_E N_SEL RW

11

10

9

8

7

6

5

Name Type Reset

RG_ADDA6_CH 1_SEL RW

1

Bit(s) 12

Name RG_ADDA6_EN_SEL

9:8

RG_ADDA6_CH1_SEL

4

RG_ADDA_EN_SEL

3:2

RG_ADDA_CH2_SEL

1:0

RG_ADDA_CH1_SEL

00002400

1

20

19

18

17

16

4 3 2 1 0 RG_AD RG_ADDA_CH2 RG_ADDA_CH1 DA_EN _SEL _SEL _SEL RW RW RW

0

0

0

1

0

0

Description Selects input en for MTKAIF MISO2 0: ADDA FS 1: ADDA6 FS Selects input source for MTKAIF MISO2 0: ADDA CH1 1: ADDA CH2 2: ADDA6 CH1 3: ADDA6 CH2 Selects input en for MTKAIF MISO0&MISO1 0: ADDA FS 1: ADDA6 FS Selects input source for MTKAIF MISO0 0: ADDA CH1 1: ADDA CH2 2: ADDA6 CH1 3: ADDA6 CH2 Selects input source for MTKAIF MISO1 0: ADDA CH1 1: ADDA CH2 2: ADDA6 CH1 3: ADDA6 CH2

AUDIO_DIG_2ND_DSN_ID

AUD_DIG_2ND Design ID Register

0000CD00

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 976 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00002402

Description

AUDIO_DIG_2ND_DSN_REV0 AUD_DIG_2ND Design Revision Register 0

00001000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00002404

Description

AUDIO_DIG_2ND_DSN_DBI

AUD_DIG_2ND Design Bank Information Register

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00002406

Description

AUDIO_DIG_2ND_DSN_DXI

AUD_DIG_2ND Design Extra Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 977 of 1067

MT6359 PMIC Datasheet Confidential A 00002408

AFE_PMIC_NEWIF_CFG3

AFE MTK ADDA NEWIF Control Register 3

0000F872

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000240A Bit Name Type Reset

Description

AFE_VOW_TOP_CON0 31

30

29

15

14

13

28

27

AFE VOW Top Control for Dual Channels 26

25

24

23

22

12 11 10 9 8 7 6 MAIN_ VOW_L VOW_I VOW_S VOW_I PDN_V VOW_DMIC_C DMIC_ VOW_CIC_MO OOP_B NTR_S DM_3_ NTR_S Name OW K_SEL CK_VO DE_SEL ACK_M W_MO LEVEL W_VAL W_SEL ODE DE RW RW RW RW RW RW RW RW Type

Bit

Reset

1

0

0

0

Bit(s) 15

Name PDN_VOW

14:13

VOW_DMIC_CK_SEL

12

MAIN_DMIC_CK_VOW_SEL

11:10

VOW_CIC_MODE_SEL

9

VOW_SDM_3_LEVEL

8

VOW_LOOP_BACK_MODE

7

VOW_INTR_SW_MODE

6 3:2

VOW_INTR_SW_VAL RG_VOW_INTR_MODE_SEL

MediaTek Proprietary and Confidential.

0

0

0

0

0

00008000

21

20

19

18

17

16

5

4

3

2

1

0

0

RG_VOW_INTR _MODE_SEL RW 0

0

Description Powers down VOW source clock 0: Normal 1: Power down VOW clk Selects DMIC clock rate 00: 1.625M rate 01: 812.5K rate Uses normal or VOW DMIC clock 0: Normal digital mic clock (1.625M/3.25M) 1: VOW digital mic clock Selects VOW CIC mode 00: Down 102x 01: Down 102x 10: Down 51x Selects SDM 3-level mode (digital MIC data path), first priority choice 0: Deselect SDM 3-level mode 1: Select SDM 3-level mode VOW loopback test mode 0: Normal path 1: Source from dl SDM output Enables VOW INTR software mode 0: HW mode 1: SW mode VOW INTR software mode value Selects VOW interrupt mode 00: vow_intr equals vow_intr_ch1 or vow_intr_ch2 01: vow_intr equals vow_intr_ch1 and vow_intr_ch2 10: vow_intr eqauls vow_intr_ch1

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 978 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

0000240C

Description 11: vow_intr equals vow_intr_ch2

AFE_VOW_TOP_CON1

AFE VOW Top Control for Left Channel

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

Bit

15

14

13

12

11

10

9

8

7

6

5

Name Type Reset

VOW_ VOW_ VOW_ VOW_ VOW_ DMIC0 DIGMI CK_DIV ADC_C CK_PD _CK_P C_ON_ _RST_C K_PDN N_CH1 DN CH1 H1 _CH1 RW 0

RW 0

RW 0

RW 0

Bit(s) 15

Name VOW_DMIC0_CK_PDN

14

VOW_DIGMIC_ON_CH1

13

VOW_CK_DIV_RST_CH1

12

VOW_ADC_CK_PDN_CH1

11

VOW_CK_PDN_CH1

10:6 5 4

RW 0

VOW_DIGMIC_CK_PHASE_SEL_CH1 VOW_ADC_CLK_INV_CH1 VOW_INTR_SOURCE_SEL_CH1

3 2

VOW_INTR_CLR_CH1 S_N_VALUE_RST_CH1

1

SAMPLE_BASE_MODE_CH1

0

VOW_ON_CH1

MediaTek Proprietary and Confidential.

VOW_DIGMIC_CK_PHASE_SEL_CH1

VOW_ ADC_C LK_INV _CH1

RW 0

RW 0

0

0

0

0

20

00000000 19

18

17

16

4 3 2 1 0 VOW_I S_N_V SAMPL NTR_S VOW_I VOW_ ALUE_ E_BASE OURCE NTR_CL ON_CH RST_CH _MODE _SEL_C R_CH1 1 1 _CH1 H1 RW RW RW RW RW 0 0 0 0 0

Description Powers down VOW digital mic clock for left channel 0: Power on 1: Power down VOW dmic or amic switcher for left channel 0: Analog mic 1: Digital mic VOW digmic output clock (to analog) clock division circuit reset bit for left channel 0: Not reset clock divider 1: Reset clock divider VOW ADC clock gated for left channel 0: Turn on VOW ADC clock for left channel 1: Turn off VOW ADC clock for left channel VOW clock gated for left channel 0: Turn on VOW clock for left channel 1: Turn off VOW clock for left channel Selects VOW digmic input phase latch for left channel Inverts VOW ADC clock for left channel Selects VOW interrupt source for left channel 0: Bias base IRQ source 1: No bias IRQ source VOW interrupt clear for left channel S, N value reset for left channel 0: Keep the last N 1: Reset to 'h64 Selects vow base mode for left channel 0: Window base 1: Sample base Powers on VOW for left channel 0: Disable VOW

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 979 of 1067

MT6359 PMIC Datasheet Confidential A 0000240E

AFE_VOW_TOP_CON2

AFE VOW Top Control for Right Channel

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

Bit

15

14

13

12

11

10

9

8

7

6

5

Name Type Reset

VOW_ VOW_ VOW_ VOW_ VOW_ DMIC1 DIGMI CK_DIV ADC_C CK_PD _CK_P C_ON_ _RST_C K_PDN N_CH2 DN CH2 H2 _CH2 RW 0

RW 0

RW 0

RW 0

Bit(s) 15

Name VOW_DMIC1_CK_PDN

14

VOW_DIGMIC_ON_CH2

13

VOW_CK_DIV_RST_CH2

12

VOW_ADC_CK_PDN_CH2

11

VOW_CK_PDN_CH2

10:6 5 4

RW 0

VOW_DIGMIC_CK_PHASE_SEL_CH2 VOW_ADC_CLK_INV_CH2 VOW_INTR_SOURCE_SEL_CH2

3 2

VOW_INTR_CLR_CH2 S_N_VALUE_RST_CH2

1

SAMPLE_BASE_MODE_CH2

0

VOW_ON_CH2

MediaTek Proprietary and Confidential.

VOW_DIGMIC_CK_PHASE_SEL_CH2

VOW_ ADC_C LK_INV _CH2

RW 0

RW 0

0

0

0

0

20

00000000 19

18

17

16

4 3 2 1 0 VOW_I S_N_V SAMPL NTR_S VOW_I VOW_ ALUE_ E_BASE OURCE NTR_CL ON_CH RST_CH _MODE _SEL_C R_CH2 2 2 _CH2 H2 RW RW RW RW RW 0 0 0 0 0

Description Powers down VOW digital mic clock for right channel 0: Power on 1: Power down VOW dmic or amic switcher for left channel 0: Analog mic 1: Digital mic VOW digmic output clock (to analog) clock division circuit reset bit for right channel 0: Not reset clock divider 1: Reset clock divider VOW ADC clock gated for right channel 0: Turn on VOW ADC clock for right channel 1: Turn off VOW ADC clock for right channel VOW clock gated for right channel 0: Turn on VOW clock for right channel 1: Turn off VOW clock for right channel Selects VOW digmic 8 input phase latch for right channel Inverts VOW ADC clock for right channel Selects VOW interrupt source for right channel 0: Bias base IRQ source 1: No bias IRQ source Clears VOW interrupt for right channel S, N value reset for right channel 0: Keep the last N 1: Reset to 'h64 Selects VOW base mode for right channel 0: Window base 1: Sample base Powers on VOW for right channel 0: Disable VOW 1: Enable VOW

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 980 of 1067

MT6359 PMIC Datasheet Confidential A 00002410

AFE_VOW_TOP_CON3

AFE VOW Top Control for Test Clock and MTKAIF Settings

00000060

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0 VOW_ P2_SN RDET_ AUTO_ PDN RW

VOW_ VOW_ VOW_ADC_TESTCK_SR ADC_T Name TXIF_S C_SEL ESTCK_ CK_INV SEL

Type Reset Bit(s) 15 14:12

RW 0

RW 0

0

0

VOW_ADC_TESTCK_SEL

9

VOW_TXIF_MONO

0

RW

RW

0

0

Name VOW_TXIF_SCK_INV VOW_ADC_TESTCK_SRC_SEL

11

8:4

VOW_T XIF_M ONO

RW 0

0

1

1

0

0

Description Inverts VOW TXIF SCK Selects different GPI as VOW ADC testck source 0: test_ck_i[2] 1: test_ck_i[2] 2: test_ck_i[1] 3: test_ck_i[0] 4: test_in_i[5] 5: test_in_i[6] 6: test_in_i[7] 7: test_in_i[0] Selects VOW ADC testck from GPI 0: Normal path from digital output 1: Testing path from GPI. See descriptions of vow_adc_testck_src_sel for details. Configures VOW MTKAIF mono transmit 0: Stereo 1: Mono VOW TXIF SCK divider TXIF SCK = vow_mck/(div*2) Switch of SNRDET automatic power down 0: Enable auto power down SNRDET 1: Disable auto power down SNRDET

VOW_TXIF_SCK_DIV VOW_P2_SNRDET_AUTO_PDN

00002412

VOW_TXIF_SCK_DIV

AFE_VOW_TOP_CON4

AFE VOW AMIC Array

00000001

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 981 of 1067

MT6359 PMIC Datasheet Confidential A 00002414

AFE_VOW_TOP_MON0

AFE VOW Top Monitor Out

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0 VOW_I NTR_FL AG_CH 2 RO

Name Type Reset Bit(s) 0

0

Name VOW_INTR_FLAG_CH2

00002416

Description VOW interrupt flag for read out for left channel

AFE_VOW_VAD_CFG0

AFE VOW VAD Configuration 0

Bit Name Type Reset

31

30

29

28

27

26

25

Bit Name Type Reset

15

14

13

12

11

10

9

Bit(s) 15:0

0

0

0

0

0

0

Name AMPREF_CH1

00002418

0

31

30

29

28

27

26

25

Bit Name Type Reset

15

14

13

12

11

10

9

Bit(s) 15:0

Name AMPREF_CH2

MediaTek Proprietary and Confidential.

22

21

20

19

18

17

16

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

AMPREF_CH1 RW 0 0

AFE VOW VAD Configuration 1

Bit Name Type Reset

0

23

Description VOW bias remove reference value for left channel

AFE_VOW_VAD_CFG1

0

00000000

24

0

0

0

0

0

00000000

24

23

22

21

20

19

18

17

16

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

AMPREF_CH2 RW 0 0

Description VOW bias remove reference value for right channel

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 982 of 1067

nnel

MT6359 PMIC Datasheet Confidential A 0000241A

AFE_VOW_VAD_CFG2

AFE VOW VAD Configuration 2

Bit Name Type Reset

31

30

29

28

27

26

25

Bit Name Type Reset

15

14

13

12

11

10

9

Bit(s) 15:0

0

0

0

0

0

1

Name TIMERINI_CH1

0000241C

0

00000400

24

23

22

21

20

19

18

17

16

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

TIMERINI_CH1 RW 0 0

Description A, B timeout initial value for left channel

AFE_VOW_VAD_CFG3

AFE VOW VAD Configuration 3

00000400

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

Bit(s) 15:0

0

0

0

0

0

1

Name TIMERINI_CH2

0000241E

Description A, B timeout initial value for right channel

AFE_VOW_VAD_CFG4

AFE VOW VAD Configuration 4

0000A323

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15 VOW_I RQ_LA Name TCH_S NR_EN _CH1 RW Type

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Reset

0

Bit Name Type Reset

31

0

TIMERINI_CH2 RW 0 0

Bit

Bit(s) 15 14:12 10:8 6:4 2:0

1

B_DEFAULT_CH1

A_DEFAULT_CH1

RW 1

RW 0

Name VOW_IRQ_LATCH_SNR_EN_CH1 B_DEFAULT_CH1 A_DEFAULT_CH1 B_INI_CH1

MediaTek Proprietary and Confidential.

B_INI_CH1

0

1

A_INI_CH1

RW 1

0

1

RW 0

0

1

1

Description Latches S and N value when IRQ trigger for left channel B default value for left channel A default value for left channel B initial value for left channel

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 983 of 1067

MT6359 PMIC Datasheet Confidential A 00002420

AFE_VOW_VAD_CFG5 31

28

27

26

25

24

23

22

21

20

19

18

17

16

15 VOW_I RQ_LA Name TCH_S NR_EN _CH2 RW Type

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Reset

0

Bit(s) 15 14:12 10:8 6:4 2:0

1

A_DEFAULT_CH2

RW

B_INI_CH2

RW

1

0

0

1

A_INI_CH2

RW 1

0

1

RW 0

0

1

1

Description Latches S and N value when IRQ trigger for right channel B default value for right channel A default value for right channel B initial value for right channel A initial value for right channel

AFE_VOW_VAD_CFG6

AFE VOW VAD Configuration 6

0000A879

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s) 15:12 11:8 7:4 3:0

K_BETA_RISE_CH1 RW 1 0 1 0

K_BETA_FALL_CH1 RW 1 0 0 0

Name K_BETA_RISE_CH1 K_BETA_FALL_CH1 K_ALPHA_RISE_CH1 K_ALPHA_FALL_CH1

00002424

29

AFE VOW VAD Configuration 7

0000A879

27

26

25

24

23

22

21

20

19

18

17

16

15 14 13 12 Bit K_BETA_RISE_CH2 Name RW Type 1 0 0 1 Reset

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s) 15:12 11:8 7:4 3:0

30

K_ALPHA_FALL_CH1 RW 1 0 0 1

Description Beta K rise value for left channel Beta K fall value for left channel Alpha K rise value for left channel Alpha K fall value for left channel

AFE_VOW_VAD_CFG7 31

K_ALPHA_RISE_CH1 RW 0 1 1 1

28

Bit Name Type Reset

1

B_DEFAULT_CH2

Name VOW_IRQ_LATCH_SNR_EN_CH2 B_DEFAULT_CH2 A_DEFAULT_CH2 B_INI_CH2 A_INI_CH2

00002422

1

0000A323

29

Bit

1

AFE VOW VAD Configuration 5

30

Bit Name Type Reset

Name K_BETA_RISE_CH2 K_BETA_FALL_CH2 K_ALPHA_RISE_CH2 K_ALPHA_FALL_CH2

MediaTek Proprietary and Confidential.

K_BETA_FALL_CH2 RW

K_ALPHA_RISE_CH2 RW

K_ALPHA_FALL_CH2 RW

Description Beta K rise value for right channel Beta K fall value for right channel Alpha K rise value for right channel Alpha K fall value for right channel

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 984 of 1067

e for left channel

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00002426

Description

AFE_VOW_VAD_CFG8

AFE VOW VAD Configuration 8

Bit Name Type Reset

31

30

29

28

27

26

25

Bit Name Type Reset

15

14

13

12

11

10

9

Bit(s) 15:0

0

0

0

0

0

0

Name N_MIN_CH1

00002428

0

AFE_VOW_VAD_CFG9 30

29

28

27

26

25

Bit Name Type Reset

15

14

13

12

11

10

9

Bit(s) 15:0

Bit Name Type Reset

Bit(s) 15 14:0

0

0

0

22

21

20

19

18

17

16

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

N_MIN_CH1 RW 1 0

0

00000100

24

23

22

21

20

19

18

17

16

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

N_MIN_CH2 RW 1 0

Description N min value for right channel

AFE_VOW_VAD_CFG10 31

15 VOW_ SN_INI Name _CFG_E N_CH1 RW Type 0 Reset

Bit

0

Name N_MIN_CH2

0000242A

23

AFE VOW VAD Configuration 9

31

0

24

Description N min value for left channel

Bit Name Type Reset

0

00000100

AFE VOW VAD Configuration 10

00000000

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

VOW_SN_INI_CFG_VAL_CH1

0

0

0

Name VOW_SN_INI_CFG_EN_CH1

MediaTek Proprietary and Confidential.

0

0

0

0

RW 0

0

Description VOW S and N initial value configure enable for left channel

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 985 of 1067

MT6359 PMIC Datasheet Confidential A 0000242C

AFE_VOW_VAD_CFG11 31

Bit Name Type Reset

15 VOW_ SN_INI Name _CFG_E N_CH2 RW Type 0 Reset

Bit

Bit(s) 15 14:0

AFE VOW VAD Configuration 11

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

VOW_SN_INI_CFG_VAL_CH2

0

0

0

0

0

Name VOW_SN_INI_CFG_EN_CH2 VOW_SN_INI_CFG_VAL_CH2

0000242E

00000000

30

0

0

RW 0

0

Description VOW S and N initial value configure enable for right channel VOW S and N initial value for right channel

AFE_VOW_VAD_CFG12

AFE VOW VAD Configuration 12

00000C0C

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s) 11:8 3:0

K_GAMMA_CH1

K_GAMMA_CH2

RW 1

1

Name K_GAMMA_CH1 K_GAMMA_CH2

00002430

RW 0

0

1

1

0

0

Description Gamma K value for left channel Gamma K value for right channel

AFE_VOW_VAD_MON0

AFE VOW VAD Monitor 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 986 of 1067

MT6359 PMIC Datasheet Confidential A 00002432

AFE_VOW_VAD_MON1

AFE VOW VAD Monitor 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00002434

Description

AFE_VOW_VAD_MON2

AFE VOW VAD Monitor 2

00001C00

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00002436

Description

AFE_VOW_VAD_MON3

AFE VOW VAD Monitor 3

00001C00

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00002438

Description

AFE_VOW_VAD_MON4

AFE VOW VAD Monitor 4

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 987 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

0000243A

Description

AFE_VOW_VAD_MON5

AFE VOW VAD Monitor 5

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000243C

Description

AFE_VOW_VAD_MON6

AFE VOW VAD Monitor 6

00000014

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

0000243E

Description

AFE_VOW_VAD_MON7

AFE VOW VAD Monitor 7

00000014

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 988 of 1067

MT6359 PMIC Datasheet Confidential A 00002440

AFE_VOW_VAD_MON8

AFE VOW VAD Monitor 8

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00002442

Description

AFE_VOW_VAD_MON9

AFE VOW VAD Monitor 9

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00002444

Description

AFE_VOW_VAD_MON10

AFE VOW VAD Monitor 10

00000014

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00002446

Description

AFE_VOW_VAD_MON11

AFE VOW VAD Monitor 11

00000014

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 989 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00002448

Description

AFE_VOW_TGEN_CFG0

AFE Vow Trigen Configuration 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15 VOW_ TGEN_ EN_CH 1 RW 0

14 VOW_T GEN_M UTE_S W_CH1 RW 0

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

Name Type Reset Bit(s) 15 14 13:0

VOW_TGEN_FREQ_DIV_CH1 RW 0

0

0

0

Name VOW_TGEN_EN_CH1 VOW_TGEN_MUTE_SW_CH1 VOW_TGEN_FREQ_DIV_CH1

0000244A

0

0

0

0

0

Description Enables VOW trigen for left channel VOW trigen SW mute for left channel VOW trigen freq div for left channel

AFE_VOW_TGEN_CFG1

AFE Vow Trigen Configuration 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15 VOW_ TGEN_ EN_CH 2 RW 0

14 VOW_T GEN_M UTE_S W_CH2 RW 0

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

18

17

Name Type Reset Bit(s) 15 14 13:0

VOW_TGEN_FREQ_DIV_CH2 RW 0

0

0

0

Name VOW_TGEN_EN_CH2 VOW_TGEN_MUTE_SW_CH2 VOW_TGEN_FREQ_DIV_CH2

0000244C

0

0

0

0

0

Description Enables VOW trigen for right channel VOW trigen SW mute for right channel VOW trigen freq div for right channel

AFE_VOW_HPF_CFG0

AFE Vow HPF Configuration 0

00000050

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

Name

VOW_HPF_DC_TEST_CH1

Type Reset

0

RG_BASELINE_ALPHA_ORDER_ CH1

RW 0

MediaTek Proprietary and Confidential.

RW 0

0

0

1

0

1

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

16

2 1 0 RG_MT RG_SN KAIF_H RDET_ RG_HP PF_BYP HPF_B F_ON_ ASS_C YPASS_ CH1 H1 CH1 RW RW RW 0

0

0

Page 990 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 15:12 7:4 2 1 0

Name VOW_HPF_DC_TEST_CH1 RG_BASELINE_ALPHA_ORDER_CH1 RG_MTKAIF_HPF_BYPASS_CH1 RG_SNRDET_HPF_BYPASS_CH1 RG_HPF_ON_CH1

0000244E

Description VOW HPF test mode for left channel Configures VOW HPF order for left channel VOW MTKAIF bypasses HPF filter for left channel. SNR detector bypasses HPF filter for left channel. Enables VOW HPF filter for left channel

AFE_VOW_HPF_CFG1

AFE Vow HPF Configuration 1

00000050

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

Name

VOW_HPF_DC_TEST_CH2

RG_BASELINE_ALPHA_ORDER_ CH2

Type Reset

RW

RW

Bit(s) 15:12 7:4 2 1 0

0

0

0

0

0

Name VOW_HPF_DC_TEST_CH2 RG_BASELINE_ALPHA_ORDER_CH2 RG_MTKAIF_HPF_BYPASS_CH2 RG_SNRDET_HPF_BYPASS_CH2 RG_HPF_ON_CH2

00002480

1

0

1

18

17

16

2 1 0 RG_MT RG_SN KAIF_H RDET_ RG_HP PF_BYP HPF_B F_ON_ ASS_C YPASS_ CH2 H2 CH2 RW RW RW 0

0

0

Description VOW HPF test mode for right channel Configures VOW HPF order for right channel VOW MTKAIF bypasses HPF filter for right channel. SNR detector bypasses HPF filter. Enables VOW HPF filter for right channel

AUDIO_DIG_3RD_DSN_ID

AUD_DIG_3RD Design ID Register

0000CD00

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00002482

Description

AUDIO_DIG_3RD_DSN_REV0 AUD_DIG_3RD Design Revision Register 0

00001000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 991 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00002484

Description

AUDIO_DIG_3RD_DSN_DBI

AUD_DIG_3RD Design Bank Information Register

00000005

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00002486

Description

AUDIO_DIG_3RD_DSN_DXI

AUD_DIG_3RD Design Extra Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00002488 Bit Name Type Reset

Description

AFE_VOW_PERIODIC_CFG0 31

30

14 RG_PE RG_PE RIODIC Name RIODIC _CNT_ _EN CLR RW RW Type 0 0 Reset

Bit

Bit(s) 15 14 13:0

15

00000000

28

27

26

25

24

23

22

21

20

19

18

17

16

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

RG_PERIODIC_CNT_PERIOD RW 0

0

Name RG_PERIODIC_EN RG_PERIODIC_CNT_CLR RG_PERIODIC_CNT_PERIOD

MediaTek Proprietary and Confidential.

AFE Vow Periodic Configuration 0

29

0

0

0

0

0

0

0

Description Enables VOW periodic Clears VOW periodic count Configures VOW periodic period

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 992 of 1067

MT6359 PMIC Datasheet Confidential A 0000248A

AFE_VOW_PERIODIC_CFG1 31

Bit Name Type Reset

15 RG_PE RIODIC Name _CNT_ SET RW Type 0 Reset

Bit

Bit(s) 15 14 13:0

15 AUDPR EAMPL ON_PE Name RIODIC _MOD E RW Type 0 Reset

Bit

Bit(s) 15

14 13:0

28

27

26

25

24

23

22

21

20

19

18

17

16

14 RG_PE RIODIC _CNT_ PAUSE RW 0

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

RG_PERIODIC_CNT_SET_VALUE RW 0

0

0

0

0

0

0

0

0

Description VOW periodic count sets a value when count is paused. Pauses VOW periodic count VOW periodic count set value

AFE_VOW_PERIODIC_CFG2 31

00000000

29

Name RG_PERIODIC_CNT_SET RG_PERIODIC_CNT_PAUSE RG_PERIODIC_CNT_SET_VALUE

0000248C Bit Name Type Reset

AFE Vow Periodic Configuration 1

30

AFE Vow Periodic Configuration 2

00000000

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14 AUDPR EAMPL ON_PE RIODIC _INVER SE RW 0

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

AUDPREAMPLON_PERIODIC_ON_CYCLE

RW 0

0

0

0

0

0

0

0

0

0

Name AUDPREAMPLON_PERIODIC_MODE

Description Selects audpreamplon periodic mode 0: RG mode 1: Periodic mode AUDPREAMPLON_PERIODIC_INVERSE Inverts audpreamplon periodic signal AUDPREAMPLON_PERIODIC_ON_CYCLE audpreamplon periodic turn on cycle

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 993 of 1067

MT6359 PMIC Datasheet Confidential A 0000248E

AFE_VOW_PERIODIC_CFG3

AFE Vow Periodic Configuration 3

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14 AUDPR EAMPL DCPRE CHARG E_PERI ODIC_I NVERS E RW 0

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

AUDPR EAMPL DCPRE Name CHARG E_PERI ODIC_ MODE

Type Reset

RW 0

AUDPREAMPLDCPRECHARGE_PERIODIC_ON_CYCLE

RW 0

0

0

Bit(s) 15

Name AUDPREAMPLDCPRECHARGE_PERIO DIC_MODE

14

AUDPREAMPLDCPRECHARGE_PERIO DIC_INVERSE AUDPREAMPLDCPRECHARGE_PERIO DIC_ON_CYCLE

13:0

00002490 Bit Name Type Reset

30

15 14 AUDAD AUDAD CLPWR CLPWR UP_PE UP_PE Name RIODIC RIODIC _MOD _INVER E SE RW RW Type 0 0 Reset

14 13:0

0

0

0

0

0

0

Description Selects audpreampldcprecharge periodic mode 0: RG mode 1: Periodic mode Inverts audpreampldcprecharge periodic signal audpreampldcprecharge periodic turn on cycle

AFE_VOW_PERIODIC_CFG4 31

Bit

Bit(s) 15

0

AFE Vow Periodic Configuration 4

00000000

29

28

27

26

25

24

23

22

21

20

19

18

17

16

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

AUDADCLPWRUP_PERIODIC_ON_CYCLE

RW 0

0

0

0

0

0

0

0

0

0

Name AUDADCLPWRUP_PERIODIC_MODE

Description Selects audadclpwrup periodic mode 0: RG mode 1: Periodic mode AUDADCLPWRUP_PERIODIC_INVERSE Inverts audadclpwrup periodic signal AUDADCLPWRUP_PERIODIC_ON_CYCLE audadclpwrup periodic turn on cycle

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 994 of 1067

MT6359 PMIC Datasheet Confidential A 00002492

AFE_VOW_PERIODIC_CFG5 31

Bit Name Type Reset

30

15 14 AUDGL AUDGL BVOW BVOWL LPWEN PWEN_ Name _PERIO PERIOD DIC_M IC_INV ODE ERSE RW RW Type 0 0 Reset

Bit

27

26

25

24

23

22

21

20

19

18

17

16

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

AUDGLBVOWLPWEN_PERIODIC_ON_CYCLE

RW 0

0

0

Name AUDGLBVOWLPWEN_PERIODIC_MO DE

14

AUDGLBVOWLPWEN_PERIODIC_INV ERSE AUDGLBVOWLPWEN_PERIODIC_ON_ CYCLE

00002494

00000000

28

Bit(s) 15

13:0

AFE Vow Periodic Configuration 5

29

0

0

0

0

0

0

Description Selects audglbvowlpwen periodic mode 0: RG mode 1: Periodic mode Inverts audglbvowlpwen periodic signal audglbvowlpwen periodic turn on cycle

AFE_VOW_PERIODIC_CFG6

AFE Vow Periodic Configuration 6

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14 AUDDI GMICE N_PERI ODIC_I NVERS E RW 0

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

AUDDI GMICE Name N_PERI ODIC_ MODE

Type Reset

RW 0

AUDDIGMICEN_PERIODIC_ON_CYCLE

RW 0

0

0

Bit(s) 15

Name AUDDIGMICEN_PERIODIC_MODE

14 13:0

AUDDIGMICEN_PERIODIC_INVERSE AUDDIGMICEN_PERIODIC_ON_CYCLE

MediaTek Proprietary and Confidential.

0

0

0

0

0

0

Description Selects auddigmicen periodic mode 0: RG mode 1: Periodic mode Inverts auddigmicen periodic signal auddigmicen periodic turn on cycle

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 995 of 1067

MT6359 PMIC Datasheet Confidential A 00002496

AFE_VOW_PERIODIC_CFG7

AFE Vow Periodic Configuration 7

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14 AUDP WDBM ICBIAS 0_PERI ODIC_I NVERS E RW 0

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

AUDP WDBM ICBIAS Name 0_PERI ODIC_ MODE

Type Reset

RW 0

AUDPWDBMICBIAS0_PERIODIC_ON_CYCLE

RW 0

0

0

Bit(s) 15

Name AUDPWDBMICBIAS0_PERIODIC_MO DE

14

AUDPWDBMICBIAS0_PERIODIC_INVE RSE AUDPWDBMICBIAS0_PERIODIC_ON_ CYCLE

13:0

00002498

0

0

0

0

0

0

0

Description Selects audpwdbmicbias0 periodic mode 0: RG mode 1: Periodic mode Inverts audpwdbmicbias0 periodic signal audpwdbmicbias0 periodic turn on cycle

AFE_VOW_PERIODIC_CFG8

AFE Vow Periodic Configuration 8

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14 AUDP WDBM ICBIAS 1_PERI ODIC_I NVERS E RW 0

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

AUDP WDBM ICBIAS Name 1_PERI ODIC_ MODE

Type Reset

RW 0

AUDPWDBMICBIAS1_PERIODIC_ON_CYCLE

RW 0

0

0

Bit(s) 15

Name AUDPWDBMICBIAS1_PERIODIC_MO DE

14

AUDPWDBMICBIAS1_PERIODIC_INVE RSE AUDPWDBMICBIAS1_PERIODIC_ON_

13:0

MediaTek Proprietary and Confidential.

0

0

0

0

0

0

0

Description Selects audpwdbmicbias1 periodic mode 0: RG mode 1: Periodic mode Inverts audpwdbmicbias1 periodic signal audpwdbmicbias1 periodic turn on cycle

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 996 of 1067

MT6359 PMIC Datasheet Confidential A 0000249A

AFE_VOW_PERIODIC_CFG9 31

Bit Name Type Reset

15 XO_VO W_CK_ EN_PE Name RIODIC _MOD E RW Type 0 Reset

Bit

Bit(s) 15

14 13:0

28

27

26

25

24

23

22

21

20

19

18

17

16

14 XO_VO W_CK_ EN_PE RIODIC _INVER SE RW 0

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

RW 0

0

0

0

0

0

0

0

0

AFE_VOW_PERIODIC_CFG10 AFE Vow Periodic Configuration 10 31

30

15 14 AUDGL AUDGL B_PWR B_PWR DN_PE DN_PE Name RIODIC RIODIC _MOD _INVER E SE RW RW Type 0 0 Reset

14 13:0

XO_VOW_CK_EN_PERIODIC_ON_CYCLE

Description Selects xo_vow_ck_en periodic mode 0: RG mode 1: Periodic mode XO_VOW_CK_EN_PERIODIC_INVERSE Inverts xo_vow_ck_en periodic signal XO_VOW_CK_EN_PERIODIC_ON_CYCLE xo_vow_ck_en periodic turn on cycle

Bit

Bit(s) 15

00000000

29

Name XO_VOW_CK_EN_PERIODIC_MODE

0000249C Bit Name Type Reset

AFE Vow Periodic Configuration 9

30

00000000

29

28

27

26

25

24

23

22

21

20

19

18

17

16

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

AUDGLB_PWRDN_PERIODIC_ON_CYCLE

RW 0

0

0

0

0

0

0

0

0

0

Name AUDGLB_PWRDN_PERIODIC_MODE

Description Selects audglb_pwrdn periodic mode 0: RG mode 1: Periodic mode AUDGLB_PWRDN_PERIODIC_INVERSE Inverts audglb_pwrdn periodic signal AUDGLB_PWRDN_PERIODIC_ON_CYCLE audglb_pwrdn periodic turn on cycle

MediaTek Proprietary and Confidential.

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Page 997 of 1067

MT6359 PMIC Datasheet Confidential A 0000249E

AFE_VOW_PERIODIC_CFG11 AFE Vow Periodic Configuration 11

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14 VOW_ ON_CH 1_PERI ODIC_I NVERS E RW 0

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

VOW_ ON_CH Name 1_PERI ODIC_ MODE

Type Reset

RW 0

VOW_ON_CH1_PERIODIC_ON_CYCLE

RW 0

0

0

Bit(s) 15

Name VOW_ON_CH1_PERIODIC_MODE

14 13:0

VOW_ON_CH1_PERIODIC_INVERSE VOW_ON_CH1_PERIODIC_ON_CYCLE

000024A0

0

0

0

0

0

0

Description Selects vow_on_ch1 periodic mode 0: RG mode 1: Periodic mode Inverts vow_on_ch1 periodic signal vow_on_ch1 periodic turn on cycle

AFE_VOW_PERIODIC_CFG12 AFE Vow Periodic Configuration 12

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14 DMIC_ ON_CH 1_PERI ODIC_I NVERS E RW 0

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

DMIC_ ON_CH Name 1_PERI ODIC_ MODE

Type Reset

RW 0

DMIC_ON_CH1_PERIODIC_ON_CYCLE

RW 0

0

0

Bit(s) 15

Name DMIC_ON_CH1_PERIODIC_MODE

14 13:0

DMIC_ON_CH1_PERIODIC_INVERSE DMIC_ON_CH1_PERIODIC_ON_CYCLE

MediaTek Proprietary and Confidential.

0

0

0

0

0

0

Description Selects dmic_on_ch1 periodic mode 0: RG mode 1: Periodic mode Inverts dmic_on_ch1 periodic signal dmic_on_ch1 periodic turn on cycle

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 998 of 1067

MT6359 PMIC Datasheet Confidential A 000024A2

AFE_VOW_PERIODIC_CFG13 AFE Vow Periodic Configuration 13 31

Bit Name Type Reset

15 PDN_V Name OW_F3 2K_CK RW Type

Bit

Reset Bit(s) 15

13:0

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

AUDPREAMPLON_PERIODIC_OFF_CYCLE RW 0

0

0

0

0

0

0

0

0

AFE_VOW_PERIODIC_CFG14 AFE Vow Periodic Configuration 14 31

15 VOW_ SNRDE Name T_PERI ODIC_C FG RW Type

Reset

00000000

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

AUDPREAMPLDCPRECHARGE_PERIODIC_OFF_CYCLE

RW

0

0

0

0

0

Name VOW_SNRDET_PERIODIC_CFG AUDPREAMPLDCPRECHARGE_PERIO DIC_OFF_CYCLE

000024A6

0

27

Description Powers down periodic on/off 32K clock 0: Power on 1: Power down AUDPREAMPLON_PERIODIC_OFF_CYCLE Audpreamplon periodic turn off cycle

Bit

0

28

Name PDN_VOW_F32K_CK

Bit Name Type Reset

0

29

1

000024A4

Bit(s) 15 13:0

00008000

30

0

0

0

0

0

0

Description VOW SNRDET latch S/N value configure in periodic mode audpreampldcprecharge periodic turn off cycle

AFE_VOW_PERIODIC_CFG15 AFE Vow Periodic Configuration 15

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type 0 Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

Bit(s) 13:0

AUDADCLPWRUP_PERIODIC_OFF_CYCLE RW

Name AUDADCLPWRUP_PERIODIC_OFF_CY CLE

MediaTek Proprietary and Confidential.

Description audadclpwrup periodic turn off cycle

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 999 of 1067

MT6359 PMIC Datasheet Confidential A 000024A8

AFE_VOW_PERIODIC_CFG16 AFE Vow Periodic Configuration 16

Bit Name Type Reset

31

30

29

28

27

26

Bit Name Type Reset

15

14

13

12

11

10

Bit(s) 13:0

00000000

25

24

23

22

21

20

19

18

17

16

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

AUDGLBVOWLPWEN_PERIODIC_OFF_CYCLE RW 0

0

0

0

Name AUDGLBVOWLPWEN_PERIODIC_OFF _CYCLE

000024AA

0

0

0

0

0

Description audglbvowlpwen periodic turn off cycle

AFE_VOW_PERIODIC_CFG17 AFE Vow Periodic Configuration 17

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

Bit(s) 13:0

AUDDIGMICEN_PERIODIC_OFF_CYCLE RW 0

0

0

0

Name AUDDIGMICEN_PERIODIC_OFF_CYCLE

000024AC

0

0

0

0

Description auddigmicen periodic turn off cycle

AFE_VOW_PERIODIC_CFG18 AFE Vow Periodic Configuration 18

Bit Name Type Reset

31

30

29

28

27

26

Bit Name Type Reset

15

14

13

12

11

10

Bit(s) 13:0

0

00000000

25

24

23

22

21

20

19

18

17

16

9

8

7

6

5

4

3

2

1

0

0

0

0

0

AUDPWDBMICBIAS0_PERIODIC_OFF_CYCLE RW 0

0

0

Name AUDPWDBMICBIAS0_PERIODIC_OFF _CYCLE

MediaTek Proprietary and Confidential.

0

0

0

0

0

0

0

Description audpwdbmicbias0 periodic turn off cycle

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 1000 of 1067

MT6359 PMIC Datasheet Confidential A 000024AE

AFE_VOW_PERIODIC_CFG19 AFE Vow Periodic Configuration 19

Bit Name Type Reset

31

30

29

28

27

26

Bit Name Type Reset

15

14

13

12

11

10

Bit(s) 13:0

00000000

25

24

23

22

21

20

19

18

17

16

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

AUDPWDBMICBIAS1_PERIODIC_OFF_CYCLE RW 0

0

0

0

Name AUDPWDBMICBIAS1_PERIODIC_OFF _CYCLE

000024B0

15 CLKSQ _EN_V OW_PE Name RIODIC _MOD E RW Type

Bit

Reset

0

0

0

0

Description audpwdbmicbias1 periodic turn off cycle

AFE_VOW_PERIODIC_CFG20 AFE Vow Periodic Configuration 20 31

Bit Name Type Reset

0

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

XO_VOW_CK_EN_PERIODIC_OFF_CYCLE

RW

0

0

0

0

Bit(s) 15

Name CLKSQ_EN_VOW_PERIODIC_MODE

13:0

XO_VOW_CK_EN_PERIODIC_OFF_CY CLE

000024B2

00000000

30

0

0

0

0

0

0

Description Selects clksq_en_vow periodic mode 0: RG mode 1: Periodic mode xo_vow_ck_en periodic turn off cycle

AFE_VOW_PERIODIC_CFG21 AFE Vow Periodic Configuration 21

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

Bit(s) 13:0

AUDGLB_PWRDN_PERIODIC_OFF_CYCLE RW 0

0

0

Name AUDGLB_PWRDN_PERIODIC_OFF_CY CLE

MediaTek Proprietary and Confidential.

0

0

0

0

0

0

0

Description audglb_pwrdn periodic turn off cycle

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 1001 of 1067

MT6359 PMIC Datasheet Confidential A 000024B4

AFE_VOW_PERIODIC_CFG22 AFE Vow Periodic Configuration 22

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

Bit(s) 13:0

VOW_ON_CH1_PERIODIC_OFF_CYCLE RW 0

0

0

0

Name VOW_ON_CH1_PERIODIC_OFF_CYCLE

000024B6

0

0

0

0

0

Description vow_on_ch1 periodic turn off cycle

AFE_VOW_PERIODIC_CFG23 AFE Vow Periodic Configuration 23

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

Bit(s) 13:0

DMIC_ON_CH1_PERIODIC_OFF_CYCLE RW 0

30

15 14 AUDPR AUDPR EAMPR EAMPR ON_PE ON_PE Name RIODIC RIODIC _MOD _INVER E SE RW RW Type 0 0 Reset

14 13:0

0

0

0

0

0

0

Description dmic_on_ch1 periodic turn off cycle

AFE_VOW_PERIODIC_CFG24 AFE Vow Periodic Configuration 24 31

Bit

Bit(s) 15

0

Name DMIC_ON_CH1_PERIODIC_OFF_CYCLE

000024B8 Bit Name Type Reset

0

00000000

29

28

27

26

25

24

23

22

21

20

19

18

17

16

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

AUDPREAMPRON_PERIODIC_ON_CYCLE

RW 0

0

0

0

0

0

0

0

0

0

Name AUDPREAMPRON_PERIODIC_MODE

Description Selects audpreampron periodic mode 0: RG mode 1: Periodic mode AUDPREAMPRON_PERIODIC_INVERSE Inverts audpreampron periodic signal AUDPREAMPRON_PERIODIC_ON_CYCLE audpreampron periodic turn on cycle

MediaTek Proprietary and Confidential.

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Page 1002 of 1067

MT6359 PMIC Datasheet Confidential A 000024BA

AFE_VOW_PERIODIC_CFG25 AFE Vow Periodic Configuration 25 31

Bit Name Type Reset

30

15

14 AUDPR AUDPR EAMPR EAMPR DCPRE DCPRE CHARG Name CHARG E_PERI E_PERI ODIC_I ODIC_ NVERS MODE E RW RW Type 0 0 Reset

Bit

28

27

26

25

24

23

22

21

20

19

18

17

16

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

AUDPREAMPRDCPRECHARGE_PERIODIC_ON_CYCLE

RW 0

0

0

Bit(s) 15

Name AUDPREAMPRDCPRECHARGE_PERIO DIC_MODE

14

AUDPREAMPRDCPRECHARGE_PERIO DIC_INVERSE AUDPREAMPRDCPRECHARGE_PERIO DIC_ON_CYCLE

13:0

000024BC Bit Name Type Reset

30

15 14 AUDAD AUDAD CRPWR CRPWR UP_PE UP_PE Name RIODIC RIODIC _MOD _INVER E SE RW RW Type 0 0 Reset

14 13:0

0

0

0

0

0

0

0

Description Selects audpreamprdcprecharge periodic mode 0: RG mode 1: Periodic mode Inverts audpreamprdcprecharge periodic signal audpreamprdcprecharge periodic turn on cycle

AFE_VOW_PERIODIC_CFG26 AFE Vow Periodic Configuration 26 31

Bit

Bit(s) 15

00000000

29

00000000

29

28

27

26

25

24

23

22

21

20

19

18

17

16

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

AUDADCRPWRUP_PERIODIC_ON_CYCLE

RW 0

0

0

0

0

0

0

0

0

0

Name AUDADCRPWRUP_PERIODIC_MODE

Description Selects audadcrpwrup periodic mode 0: RG mode 1: Periodic mode AUDADCRPWRUP_PERIODIC_INVERSE Inverts audadcrpwrup periodic signal AUDADCRPWRUP_PERIODIC_ON_CYCLE audadcrpwrup periodic turn on cycle

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 1003 of 1067

MT6359 PMIC Datasheet Confidential A 000024BE

AFE_VOW_PERIODIC_CFG27 AFE Vow Periodic Configuration 27 31

Bit Name Type Reset

15 AUDGL BRVO WLPW Name EN_PE RIODIC _MOD E RW Type 0 Reset

Bit

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14 AUDGL BRVO WLPW EN_PE RIODIC _INVER SE RW 0

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

AUDGLBRVOWLPWEN_PERIODIC_ON_CYCLE

RW 0

0

0

Bit(s) 15

Name AUDGLBRVOWLPWEN_PERIODIC_M ODE

14

AUDGLBRVOWLPWEN_PERIODIC_IN VERSE AUDGLBRVOWLPWEN_PERIODIC_ON _CYCLE

13:0

000024C0 Bit Name Type Reset

Bit(s) 15

14 13:0

0

0

0

0

0

0

0

Description Selects audglbrvowlpwen periodic mode 0: RG mode 1: Periodic mode Inverts audglbrvowlpwen periodic signal audglbrvowlpwen periodic turn on cycle

AFE_VOW_PERIODIC_CFG28 AFE Vow Periodic Configuration 28 31

15 AUDDI GMIC1 EN_PE Name RIODIC _MOD E RW Type 0 Reset

Bit

00000000

30

00000000

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14 AUDDI GMIC1 EN_PE RIODIC _INVER SE RW 0

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

AUDDIGMIC1EN_PERIODIC_ON_CYCLE

RW 0

0

0

0

0

0

0

0

0

Name AUDDIGMIC1EN_PERIODIC_MODE

Description Selects auddigmic1en periodic mode 0: RG mode 1: Periodic mode AUDDIGMIC1EN_PERIODIC_INVERSE Inverts auddigmic1en periodic signal AUDDIGMIC1EN_PERIODIC_ON_CYCLE auddigmic1en periodic turn on cycle

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 1004 of 1067

MT6359 PMIC Datasheet Confidential A 000024C2

AFE_VOW_PERIODIC_CFG29 AFE Vow Periodic Configuration 29

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14 AUDP WDBM ICBIAS 2_PERI ODIC_I NVERS E RW 0

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

AUDP WDBM ICBIAS Name 2_PERI ODIC_ MODE

Type Reset Bit(s) 15

14 13:0

RW 0

AUDPWDBMICBIAS2_PERIODIC_ON_CYCLE

RW 0

0

0

0

0

0

0

0

0

0

Name Description AUDPWDBMICBIAS2_PERIODIC_MODE Selects audpwdbmicbias2 periodic mode 0: RG mode 1: Periodic mode AUDPWDBMICBIAS2_PERIODIC_INVER Inverts audpwdbmicbias2 periodic signal SE AUDPWDBMICBIAS2_PERIODIC_ON_C audpwdbmicbias2 periodic turn on cycle YCLE

000024C4

AFE_VOW_PERIODIC_CFG30 AFE Vow Periodic Configuration 30

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14 VOW_ ON_CH 2_PERI ODIC_I NVERS E RW 0

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

VOW_ ON_CH Name 2_PERI ODIC_ MODE

Type Reset

RW 0

VOW_ON_CH2_PERIODIC_ON_CYCLE

RW 0

0

0

Bit(s) 15

Name VOW_ON_CH2_PERIODIC_MODE

14 13:0

VOW_ON_CH2_PERIODIC_INVERSE VOW_ON_CH2_PERIODIC_ON_CYCLE

MediaTek Proprietary and Confidential.

0

0

0

0

0

0

Description Selects vow_on_ch2 periodic mode 0: RG mode 1: Periodic mode Inverts vow_on_ch2 periodic signal vow_on_ch2 periodic turn on cycle

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 1005 of 1067

MT6359 PMIC Datasheet Confidential A 000024C6

AFE_VOW_PERIODIC_CFG31 AFE Vow Periodic Configuration 31

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14 DMIC_ ON_CH 2_PERI ODIC_I NVERS E RW 0

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

DMIC_ ON_CH Name 2_PERI ODIC_ MODE

Type Reset

RW 0

DMIC_ON_CH2_PERIODIC_ON_CYCLE

RW 0

0

0

0

Bit(s) 15

Name DMIC_ON_CH2_PERIODIC_MODE

14 13:0

DMIC_ON_CH2_PERIODIC_INVERSE DMIC_ON_CH2_PERIODIC_ON_CYCLE

000024C8

0

0

0

0

0

Description Selects dmic_on_ch2 periodic mode 0: RG mode 1: Periodic mode Inverts dmic_on_ch2 periodic signal dmic_on_ch2 periodic turn on cycle

AFE_VOW_PERIODIC_CFG32 AFE Vow Periodic Configuration 32

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

Bit(s) 13:0

AUDPREAMPRON_PERIODIC_OFF_CYCLE RW 0

0

0

0

Name AUDPREAMPRON_PERIODIC_OFF_CY CLE

000024CA

0

0

0

0

0

Description audpreampron periodic turn off cycle

AFE_VOW_PERIODIC_CFG33 AFE Vow Periodic Configuration 33

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

Bit(s) 13:0

AUDPREAMPRDCPRECHARGE_PERIODIC_OFF_CYCLE RW 0

0

0

Name AUDPREAMPRDCPRECHARGE_PERIO DIC_OFF_CYCLE

MediaTek Proprietary and Confidential.

0

0

0

0

0

0

0

Description audpreamprdcprecharge periodic turn off cycle

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 1006 of 1067

MT6359 PMIC Datasheet Confidential A 000024CC

AFE_VOW_PERIODIC_CFG34 AFE Vow Periodic Configuration 34

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

Bit(s) 13:0

AUDADCRPWRUP_PERIODIC_OFF_CYCLE RW 0

0

0

0

Name AUDADCRPWRUP_PERIODIC_OFF_CY CLE

000024CE

0

0

0

0

Description audadcrpwrup periodic turn off cycle

AFE_VOW_PERIODIC_CFG35 AFE Vow Periodic Configuration 35

Bit Name Type Reset

31

30

29

28

27

26

Bit Name Type Reset

15

14

13

12

11

10

Bit(s) 13:0

0

00000000

25

24

23

22

21

20

19

18

17

16

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

AUDGLBRVOWLPWEN_PERIODIC_OFF_CYCLE RW 0

0

0

0

Name AUDGLBRVOWLPWEN_PERIODIC_OF F_CYCLE

000024D0

0

0

0

0

0

Description audglbrvowlpwen periodic turn off cycle

AFE_VOW_PERIODIC_CFG36 AFE Vow Periodic Configuration 36

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

Bit(s) 13:0

AUDDIGMIC1EN_PERIODIC_OFF_CYCLE RW 0

0

0

0

0

0

0

0

0

0

Name Description AUDDIGMIC1EN_PERIODIC_OFF_CYCLE auddigmic1en periodic turn off cycle

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 1007 of 1067

MT6359 PMIC Datasheet Confidential A 000024D2

AFE_VOW_PERIODIC_CFG37 AFE Vow Periodic Configuration 37

Bit Name Type Reset

31

30

29

28

27

26

Bit Name Type Reset

15

14

13

12

11

10

Bit(s) 13:0

00000000

25

24

23

22

21

20

19

18

17

16

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

AUDPWDBMICBIAS2_PERIODIC_OFF_CYCLE RW 0

0

0

0

Name AUDPWDBMICBIAS2_PERIODIC_OFF _CYCLE

000024D4

0

0

0

0

0

Description audpwdbmicbias2 periodic turn off cycle

AFE_VOW_PERIODIC_CFG38 AFE Vow Periodic Configuration 38

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

Bit(s) 13:0

VOW_ON_CH2_PERIODIC_OFF_CYCLE RW 0

0

0

0

Name VOW_ON_CH2_PERIODIC_OFF_CYCLE

000024D6

0

0

0

0

0

Description vow_on_ch2 periodic turn off cycle

AFE_VOW_PERIODIC_CFG39 AFE Vow Periodic Configuration 39

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

Bit(s) 13:0

DMIC_ON_CH2_PERIODIC_OFF_CYCLE RW 0

0

0

0

Name DMIC_ON_CH2_PERIODIC_OFF_CYCLE

MediaTek Proprietary and Confidential.

0

0

0

0

0

Description dmic_on_ch2 periodic turn off cycle

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 1008 of 1067

MT6359 PMIC Datasheet Confidential A 000024D8

AFE_VOW_PERIODIC_MON0 AFE Vow Periodic Monitor 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

VOW_PERIODIC_MON0 RO 0 0 0 0

0

0

0

0

0

0

Bit(s) 15:0

0

0

0

0

0

Name VOW_PERIODIC_MON0

000024DA

Description VOW periodic control monitor 0

AFE_VOW_PERIODIC_MON1 AFE Vow Periodic Monitor 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

VOW_PERIODIC_MON1 RO 0 0 0 0

0

0

0

0

0

0

Bit(s) 15:0

0

0

0

0

0

Name VOW_PERIODIC_MON1

000024DC

Description VOW periodic control monitor 1

AFE_VOW_PERIODIC_MON2 AFE Vow Periodic Monitor 2

Bit Name Type Reset

31

30

29

28

27

26

Bit Name Type Reset

15

14

13

12

11

10

Bit(s) 15:0

0

0

0

0

0

Name VOW_PERIODIC_COUNT_MON

MediaTek Proprietary and Confidential.

0

00000000

25

24

23

22

21

20

19

18

17

16

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

VOW_PERIODIC_COUNT_MON RO 0 0 0 0

Description VOW periodic control count monitor

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 1009 of 1067

MT6359 PMIC Datasheet Confidential A 000024DE

AFE_NCP_CFG0

AFE_NCP_CFG0

Bit Name Type Reset

31

30

29

28

27

26

25

Bit

15

14

13

12

11

10

9

0

0

Name

RG_NCP_CK1_VALID_CNT

Type Reset Bit(s) 15:9 8

7 6:4 3:1 0

1

0

RW 1

1

0

24

0000B000 23

22

21

20

19

18

17

16

8 7 6 5 4 3 2 1 0 RG_NC RG_NC RG_NCP_DITHER_FIXE RG_NCP_DITHER_FIXE RG_NC P_ADIT P_DITH D_CK0_ACK1_2P D_CK0_ACK2_2P P_ON H ER_EN RW RW RW RW RW 0 0 0 0 0 0 0 0 0

Name RG_NCP_CK1_VALID_CNT RG_NCP_ADITH

Description Configures NCP soft start time Selects CK dither 0: Fixed 1: RND RG_NCP_DITHER_EN Enables RND dither RG_NCP_DITHER_FIXED_CK0_ACK1_2P CK1 fixed dither value RG_NCP_DITHER_FIXED_CK0_ACK2_2P CK2 fixed dither value RG_NCP_ON Enables NCP

000024E0

AFE_NCP_CFG1

AFE_NCP_CFG1

00001515

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15 RG_XY _VAL_ CFG_E N RW

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

1

Name Type Reset

RG_X_VAL_CFG

RG_Y_VAL_CFG

RW 0

1

Bit(s) 15

Name RG_XY_VAL_CFG_EN

14:8 6:0

RG_X_VAL_CFG RG_Y_VAL_CFG

MediaTek Proprietary and Confidential.

0

RW 1

0

1

0

0

1

0

1

Description Configures NCP CK1/CK2 pulse width SW mode 0: Fixed 1: SW mode Configures NCP CK1 pulse width Configures NCP CK2 pulse width

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 1010 of 1067

MT6359 PMIC Datasheet Confidential A 000024E2

AFE_NCP_CFG2

AFE_NCP_CFG2

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

Name Type Reset Bit(s) 1

0

17

1 0 RG_NC RG_NC P_NON P_PDDI CLK_SE S_EN T RW RW 0

Name RG_NCP_NONCLK_SET

16

0

Description NCP non-overlap timing option control 0: 1T 1: 3T

RG_NCP_PDDIS_EN

00002500

AUDENC_DSN_ID

AUDENC Design ID Register

0000A084

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00002502

Description

AUDENC_DSN_REV0

AUDENC Design Revision Register 0

00000010

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 1011 of 1067

MT6359 PMIC Datasheet Confidential A 00002504

AUDENC_DSN_DBI

AUDENC Design Bank Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00002506

Description

AUDENC_DSN_FPI

AUDENC Design Extra Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00002508

Description

AUDENC_ANA_CON0

AUDENC Control Register 0

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

1

0

RW

2 RG_AU DPREA MPLDC PRECH ARGE RW

0

0

Name Type Reset Bit(s) 14:13

RG_AU RG_AU RG_BU RG_AUDADCLI RG_AUDPREA RG_AUDPREA DPREA DADCL LKL_VC RG_AUDPREAMPLGAIN NPUTSEL MPLINPUTSEL MPLVSCALE MPLPG PWRUP M_EN ATEST RW 0

RW

RW

0

0

0

Name RG_AUDADCLINPUTSEL

12

RG_AUDADCLPWRUP

11

RG_BULKL_VCM_EN

MediaTek Proprietary and Confidential.

RW 0

0

RW 0

0

RW 0

0

0

RG_AU RG_AU DPREA DPREA MPLDC MPLO CEN N RW

RW

0

0

Description Selects audio L ADC input 00: Idle 01: AIN0 10: Left preamplifier 11: Idle Powers upaudio L ADC 0: Power down 1: Power on Audio L preamplifier PGA switch bulk tied to VCM or supply rail control 0: Tied to supply rail 1: Tied to VCM

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 1012 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 10:8

Name RG_AUDPREAMPLGAIN

7:6

RG_AUDPREAMPLINPUTSEL

5:4 3

RG_AUDPREAMPLVSCALE RG_AUDPREAMPLPGATEST

2

RG_AUDPREAMPLDCPRECHARGE

1

RG_AUDPREAMPLDCCEN

0

RG_AUDPREAMPLON

0000250A

Description Adjusts audio L preamplifier gain 000: 0 dB 001: 6 dB 010: 12 dB 011: 18 dB 100: 24 dB Selects audio L preamplifier input 00: None 01: AIN0 10: AIN1 11: None Audio L preamplifier PGA DC output voltage scale Enables audio L preamplifier PGA test 0: Disable 1: Enable Audio L preamplifier PGA DC couple input precharge 0: Disable 1: Enable Audio L DC couple input 0: AC couple input 1: DC couple input Enables audio L preamplifier 0: Disable 1: Enable

AUDENC_ANA_CON1

AUDENC Control Register 1

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

0

0

0

0

0

0

0

0

0

0

0

0

Name Type Reset Bit(s) 14:13

17

16

2 1 0 RG_AU RG_AU RG_AU RG_AU RG_AU RG_BU DPREA RG_AUDADCRI RG_AUDPREAMPRGAI RG_AUDPREA RG_AUDPREA DPREA DPREA DPREA DADCR LKR_VC MPRDC NPUTSEL N MPRINPUTSEL MPRVSCALE MPRPG MPRDC MPRO PWRUP M_EN PRECH ATEST CEN N ARGE RW RW RW RW RW RW RW RW RW RW

Name RG_AUDADCRINPUTSEL

12

RG_AUDADCRPWRUP

11

RG_BULKR_VCM_EN

10:8

18

RG_AUDPREAMPRGAIN

MediaTek Proprietary and Confidential.

0

0

0

Description Selects audio R ADC input 00: Idle 01: AIN2 10: Right preamplifier 11: Idle Powers up audio R ADC 0: Power down 1: Power on Audio R preamplifier PGA switch bulk tied to VCM or supply rail control 0: Tied to supply rail 1: Tied to VCM Adjusts audio R preamplifier gain 000: 0 dB

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 1013 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

7:6

RG_AUDPREAMPRINPUTSEL

5:4 3

RG_AUDPREAMPRVSCALE RG_AUDPREAMPRPGATEST

2

RG_AUDPREAMPRDCPRECHARGE

1

RG_AUDPREAMPRDCCEN

0

RG_AUDPREAMPRON

0000250C

Description 001: 6 dB 010: 12 dB 011: 18 dB 100: 24 dB Selects audio R preamplifier input 00: None 01: AIN2 10: AIN3 11: AIN0 Audio R preamplifier PGA DC output voltage scale Enables audio R preamplifier PGA test 0: Disable 1: Enable Audio R preamplifier PGA DC couple input precharge 0: Disable 1: Enable Audio R DC couple input 0: AC couple input 1: DC couple input Enables audio R preamplifier 0: Disable 1: Enable

AUDENC_ANA_CON2

AUDENC Control Register 2

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

0

0

0

0

0

0

0

0

0

0

0

0

Name

Type Reset Bit(s) 14:13

17

16

2 1 0 RG_AU RG_AU RG_AU RG_AU RG_AU RG_BU DPREA RG_AUDADC3I RG_AUDPREAMP3GAI RG_AUDPREA RG_AUDPREA DPREA DPREA DPREA DADC3 LK3_VC MP3DC NPUTSEL N MP3INPUTSEL MP3VSCALE MP3PG MP3DC MP3O PWRUP M_EN PRECH ATEST CEN N ARGE RW RW RW RW RW RW RW RW RW RW

Name RG_AUDADC3INPUTSEL

12

RG_AUDADC3PWRUP

11

RG_BULK3_VCM_EN

10:8

18

RG_AUDPREAMP3GAIN

MediaTek Proprietary and Confidential.

0

0

0

Description Selects audio 3rd ADC input 00: Idle 01: AIN3 10: 3rd preamplifier 11: Idle Audio 3rd ADC power up 0: Power down 1: Power on Audio 3rd preamplifier PGA switch bulk tied to VCM or supply rail control 0: Tied to supply rail 1: Tied to VCM Adjusts audio 3rd preamplifier gain 000: 0 dB 001: 6 dB

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 1014 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

7:6

RG_AUDPREAMP3INPUTSEL

5:4 3

RG_AUDPREAMP3VSCALE RG_AUDPREAMP3PGATEST

2

RG_AUDPREAMP3DCPRECHARGE

1

RG_AUDPREAMP3DCCEN

0

RG_AUDPREAMP3ON

0000250E Bit Name Type Reset

Description 010: 12 dB 011: 18 dB 100: 24 dB Selects audio 3rd preamplifier input 00: None 01: AIN3 10: AIN2 11: None Audio 3rd preamplifier PGA DC output voltage scale Enables audio 3 preamplifier PGA test 0: Disable 1: Enable Audio 3 preamplifier PGA DC couple input precharge 0: Disable 1: Enable Audio 3 DC couple input 0: AC couple input 1: DC couple input Enables audio 3 preamplifier 0: Disable 1: Enable

AUDENC_ANA_CON3

AUDENC Control Register 3

00000000

31

30

29

28

27

26

25

24

23

22

21

15

14

13

12

11

10

9

8

7

6

5

20

19

18

4 3 2 RG_AU RG_AU RG_AU RG_AU RG_AUDADC2N RG_AUDADC1S DADC2 RG_AUDADCFL RG_AUDADCRE RG_AUDPREA DADCF DADC1 DPREA DSTAGEIDDTES TSTAGEIDDTES NDSTA Name ASHIDDTEST FBUFIDDTEST MPIDDTEST LASHLP STSTAG MPLPE T T GELPE EN ELPEN N N RW RW RW RW RW RW RW RW RW Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

Bit

Bit(s) 15:14

Name RG_AUDADCFLASHIDDTEST

13:12

RG_AUDADCREFBUFIDDTEST

11:10

RG_AUDADC2NDSTAGEIDDTEST

9:8

RG_AUDADC1STSTAGEIDDTEST

MediaTek Proprietary and Confidential.

17

16

1

0

RG_AU RG_AU DGLBV DULHA OWLP LFBIAS WEN RW 0

RW 0

Description Selects audio ADC flash Idd current test 00: 100% 01: 80% 10: 120% 11: 140% Selects audio ADC reference buffer Idd current test 00: 100% 01: 80% 10: 120% 11: 140% Audio ADC 2nd & 3rd stage Idd adjust bits 00: 100% 01: 80% 10: 120% 11: 140% Audio ADC 1st stage Idd adjust bits

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 1015 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

7:6

RG_AUDPREAMPIDDTEST

5

RG_AUDADCFLASHLPEN

4

RG_AUDADC2NDSTAGELPEN

3

RG_AUDADC1STSTAGELPEN

2

RG_AUDPREAMPLPEN

1

RG_AUDGLBVOWLPWEN

0

RG_AUDULHALFBIAS

00002510 Bit Name Type Reset

Description 00: 100% 01: 80% 10: 120% 11: 140% Audio preamplifier Idd adjust bits 00: 100% 01: 75% 10: 125% 11: 150% Enables audio ADC flash low power 0: Normal 1: Enable Enables audio ADC 2nd & 3rd low power 0: Normal 1: Enable Enables audio ADC 1st stage low power 0: Normal 1: Enable Audio preamplifier PGA low power mode 0: Disable 1: Enable Enables audio uplink globe bias VOW low power mode 0: Normal 1: Enable Enables audio uplink halfbias 0: Normal 1: Enable

AUDENC_ANA_CON4

AUDENC Control Register 4

00000000

31

30

29

28

27

26

25

24

23

22

21

15

14

13

12

11

10

9

8

7

6

5

20

19

18

17

16

4 3 2 1 0 RG_AU RG_AU RG_AU RG_AU RG_AU RG_AU RG_AUDRADC2 RG_AUDRADC1 DRADC DRADC RG_AUDRADCF RG_AUDRADCR RG_AUDRPREA DRADC DRPRE DGLBR DRULH NDSTAGEIDDTE STSTAGEIDDTE 2NDST 1STSTA Name LASHIDDTEST EFBUFIDDTEST MPIDDTEST FLASHL AMPLP VOWLP ALFBIA ST ST AGELPE GELPE PEN EN WEN S N N RW RW RW RW RW RW RW RW RW RW RW Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

Bit

Bit(s) 15:14

Name RG_AUDRADCFLASHIDDTEST

13:12

RG_AUDRADCREFBUFIDDTEST

MediaTek Proprietary and Confidential.

Description Selects audio ADC flash Idd current test 00: 100% 01: 80% 10: 120% 11: 140% Selects audio ADC reference buffer Idd current test 00: 100% 01: 80% 10: 120% 11: 140%

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 1016 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 11:10

Name RG_AUDRADC2NDSTAGEIDDTEST

9:8

RG_AUDRADC1STSTAGEIDDTEST

7:6

RG_AUDRPREAMPIDDTEST

5

RG_AUDRADCFLASHLPEN

4

RG_AUDRADC2NDSTAGELPEN

3

RG_AUDRADC1STSTAGELPEN

2

RG_AUDRPREAMPLPEN

1

RG_AUDGLBRVOWLPWEN

0

RG_AUDRULHALFBIAS

00002512

AUDENC_ANA_CON5

Bit Name Type Reset

31

30

29

28

27

Bit

15

14

13

12

11

Name Type Reset Bit(s) 15:11

10

Description Audio ADC 2nd & 3rd stage Idd adjust bits 00: 100% 01: 80% 10: 120% 11: 140% Audio ADC 1st stage Idd adjust bits 00: 100% 01: 80% 10: 120% 11: 140% Audio preamplifier Idd adjust bits 00: 100% 01: 75% 10: 125% 11: 150% Enables audio ADC flash low power 0: Normal 1: Enable Enables audio ADC 2nd & 3rd low power 0: Normal 1: Enable Enables audio ADC 1st stage low power 0: Normal 1: Enable Audio preamplifier PGA low power mode 0: Disable 1: Enable Enables audio uplink globe bias VOW low power mode 0: Normal 1: Enable Enables audio uplink halfbias 0: Normal 1: Enable

RG_AUDSPAREPGA

0

0

RW 0

0

Name RG_AUDSPAREPGA

RG_DCCVCMBUFLPSWEN

MediaTek Proprietary and Confidential.

0

AUDENC Control Register 5 26

25

24

23

22

00000000 21

20

19

18

17

16

10 9 8 7 6 5 4 3 2 1 0 RG_DC RG_DC RG_AU RG_AU RG_AU CVCMB CVCMB DPREA DPREA RG_AUDADCCL RG_AUDADCCL RG_AUDADCCL DADCC UFLPS UFLPM MPAAF MP_AC KGENMODE KSOURCE KSEL LKRSTB WEN ODSEL EN CFS RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0

Description RG_NNP_EN_VA25 SWenh1_VA25 SWenh2_VA25 OP_CMFBEN_VA25 Audio preamplifier PGA DCC VCM buffer SW EN

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 1017 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 9 8

7

Name RG_DCCVCMBUFLPMODSEL RG_AUDPREAMPAAFEN

RG_AUDPREAMP_ACCFS

6:5

RG_AUDADCCLKGENMODE

4:3

RG_AUDADCCLKSOURCE

2:1

RG_AUDADCCLKSEL

0

RG_AUDADCCLKRSTB

00002514 Bit Name Type Reset

Description Audio preamplifier PGA DCC VCM buffer LP MODSEL Audio preamplifier PGA with AAF input in DC couple mode 0: Disable 1: Enable Audio preamplifier's fast settling technique for ACC mode 0: Disable 1: Enable Audio ADC clock gen. mode 00: Divided by 2 (normal) 01: Divided by 4 10: Divided by 8 11: Not divided Audio ADC clock source 00: 13 MHz from CLKSQ 01: 3.25 MHz from CLKSQ 10: 12.58 MHz from 32 kHz PLL 11: 12 MHz ring oscillator Selects audio ADC's filter adjustment for clock 00: For 13 MHz clock in, 6.5 MHz data out 10: For 26 MHz clock in, 13 MHz data out 01: For 6.5 MHz clock in, 3.25 MHz data out 11: NA Audio ADC clock RSTB 0: Reset 1: Enable

AUDENC_ANA_CON6

AUDENC Control Register 6

31

30

29

28

27

26

25

15

14

13

12

11

10

9

24

23

22

00000800 21

20

19

18

17

16

8 7 6 5 4 3 2 1 0 RG_AU RG_AU RG_AU RG_AU RG_AU RG_AU RG_AU RG_AU RG_AU RG_AU RG_AU RG_AU DADCD RG_AU RG_AU DADC3 DADC2 DADC1 DADCR DADCD RG_AUDADCD DADCF DADCN DADC DADCD DADCN DADCD ACFBC DADCB DADCF RDSTA NDSTA STSTA Name DAC0P AC0P25 ACIDDTEST FBYPAS OPATE WIDEC ACTEST ODEM ACNRZ URREN YPASS SRESET GERESE GERESE GESDE 25FS FS S ST M T T T NB RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 Reset

Bit

Bit(s) 15

Name RG_AUDADCRDAC0P25FS

14

RG_AUDADCDAC0P25FS

13

RG_AUDADCDACTEST

12 11

RG_AUDADCNODEM RG_AUDADCDACNRZ

MediaTek Proprietary and Confidential.

Description Enables audio ADCR FBDAC 0.25FS 0: 13 MHz clock in, 6.5 MHz data out 1: 3.25 MHz clock in, 1.625 MHz data out Enables audio ADCL FBDAC 0.25FS 0: 13 MHz clock in, 6.5 MHz data out 1: 3.25 MHz clock in, 1.625 MHz data out Audio ADC DAC test 0: Disable 1: Enable the data in RG_AUDADCTESTDATA[15:0] to be passed to DAC Audio ADC DEM test Audio ADC DAC in non return to zero mode 0: RZ mode (2I)

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 1018 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

10:9

RG_AUDADCDACIDDTEST

8 7

RG_AUDADCDACFBCURRENT RG_AUDADCFFBYPASS

6

RG_AUDADCBYPASS

5

RG_AUDADCNOPATEST

4

RG_AUDADCWIDECM

3 2

RG_AUDADCFSRESET RG_AUDADC3RDSTAGERESET

1

RG_AUDADC2NDSTAGERESET

0

RG_AUDADC1STSTAGESDENB

00002516

Description 1: NRZ mode (I) Selects audio ADC-DAC Idd current test 00: Normal 11: -20% DAC f/b current Audio ADC feedback coefficient Bypasses audio ADC feed forward 0: No bypass. Allow feedforward coefficient to pass signal to ADC flash. 1: Bypass. Not allow ADC i/p signal to feedforward flash. Enables audio ADC input resistor bypass 0: Disable 1: Enable Audio ADC no preamp test 0: Normal ADC gain 1: 6 dB ADC gain Enables audio ADC wide common mode 0: Normal 1: Enable Selects audio encoder FS reset block model Audio ADC 3rd stage reset 0: Normal 1: Reset Audio ADC 2nd stage reset 0: Normal 1: Reset Audio ADC 1st stage source degenerate enableb 0: Enable 1: Disable

AUDENC_ANA_CON7

AUDENC Control Register 7

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

RG_AUDADCTESTDATA RW 0 0 0 0

0

0

0

0

0

0

Bit(s) 15:0

0

0

0

0

Name RG_AUDADCTESTDATA

MediaTek Proprietary and Confidential.

0

Description Audio ADC test data bits Audio ADC test data bits for both phases of DRTZ DAC. Can enable any current source you choose.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 1019 of 1067

MT6359 PMIC Datasheet Confidential A 00002518

AUDENC_ANA_CON8

AUDENC Control Register 8

00001515

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13 RG_AU DRCTU NERSEL RW

12

11

10

9

8

7

6

5 RG_AU DRCTU NELSEL RW

4

3

2

1

0

0

1

0

1

0

1

0

Name Type Reset Bit(s) 13

Name RG_AUDRCTUNERSEL

12:8

RG_AUDRCTUNER

5

4:0

RG_AUDRCTUNER RW 0

1

1

RW 1

Description Selects audio R ADC RC tuning 0: Use auto cal tune bits 1: Use RG_AUDRCTUNEL[4:0] Audio R ADC RC tuned value See RG_AUDRCTUNELSE. Selects audio L ADC RC tuning 0: Use auto cal tune bits 1: Use RG_AUDRCTUNEL[4:0] Audio L ADC RC tuned value See RG_AUDRCTUNELSE.

RG_AUDRCTUNELSEL

RG_AUDRCTUNEL

0000251A

0

RG_AUDRCTUNEL

AUDENC_ANA_CON9

AUDENC Control Register 9

00000015

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5 RG_AU D3CTU NELSEL RW 0

4

3

2

1

0

Name Type Reset Bit(s) 15:11 10:6 5

4:0

RG_AUD3SPARE

0

0

RW 0

0

Name RG_AUD3SPARE RGS_AUDRCTUNE3READ RG_AUD3CTUNELSEL

RG_AUD3CTUNEL

MediaTek Proprietary and Confidential.

RGS_AUDRCTUNE3READ

0

0

0

RO 0

0

0

RG_AUD3CTUNEL

1

0

RW 1

0

1

Description Spare RG Audio 3 RC tune read data Selects audio 3rd ADC RC tuning 0: Use auto cal tune bits 1: Use RG_AUD3RCTUNEL[4:0] Audio 3rd ADC RC tuned value See RG_AUDRCTUNELSE.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 1020 of 1067

MT6359 PMIC Datasheet Confidential A 0000251C

AUDENC_ANA_CON10

Bit Name Type Reset

31

30

29

28

Bit Name Type Reset

15

14

13

12

Bit(s) 12:8 4:0

0

AUDENC Control Register 10 26

25

24

23

22

21

20

11

10

9

8

7

6

5

4

19

18

17

16

3

2

1

0

RGS_AUDRCTUNERREAD

RGS_AUDRCTUNELREAD

RO

RO

0

0

Name RGS_AUDRCTUNERREAD RGS_AUDRCTUNELREAD

0000251E

00000000

27

0

0

0

0

0

0

0

Description Audio R RC tune read data Audio L RC tune read data

AUDENC_ANA_CON11

AUDENC Control Register 11

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

RG_AUDSPAREVA18 RW 0 0 0 0

0

RG_AUDSPAREVA30 RW 0 0 0 0

0

0

Bit(s) 15:8 7:0

0

Name RG_AUDSPAREVA18 RG_AUDSPAREVA30

00002520

0

0

0

Description Spare control bits for AVDD18 voltage domain Spare control bits for AVDD30 voltage domain

AUDENC_ANA_CON12

AUDENC Control Register 12

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

0

0

0

0

0

Name Type Reset Bit(s) 15:3 2

RG_AUDENC_SPARE2

0

0

0

0

Name RG_AUDENC_SPARE2 RG_AUDPGA_ACCCMP

1

RG_AUDPGA_CAPRA

0

RG_AUDPGA_DECAP

MediaTek Proprietary and Confidential.

0

0

RW 0

0

18

17

16

2 1 0 RG_AU RG_AU RG_AU DPGA_ DPGA_ DPGA_ ACCCM CAPRA DECAP P RW RW RW 0 0 0

Description AUDENC spare2 3.3V domain Enables ACC mode feedback compensation capacitor. 3.3V domain Enables cap rearrange. 3.3V domain Enables decoupling cap for 1 MHz interference.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 1021 of 1067

MT6359 PMIC Datasheet Confidential A 00002522

AUDENC_ANA_CON13

AUDENC Control Register 13

Bit Name Type Reset

31

30

29

28

27

26

25

Bit

15

14

13

12

11

10

9

Name

RG_DMICMONSEL

Type Reset

0

Bit(s) 11:9 8

RW

Name RG_DMICMONSEL RG_DMICMONEN

7:6 5:4 3

RG_AUDDIGMICNDUTY RG_AUDDIGMICPDUTY RG_DMICHPCLKEN

2:1

RG_AUDDIGMICBIAS

0

0

AUDENC_ANA_CON14 31

30

29

28

27

26

25

Bit

15

14

13

12

11

10

9

Type Reset Bit(s) 15:12 11:9 8

RG_AUDSPAREVMIC

RG_DMIC1MONSEL

RW 0

0

0

0

Name RG_AUDSPAREVMIC RG_DMIC1MONSEL RG_DMIC1MONEN

7:6 5:4 3

RG_AUDDIGMIC1NDUTY RG_AUDDIGMIC1PDUTY RG_DMIC1HPCLKEN

2:1

RG_AUDDIGMICBIAS1

0

RG_AUDDIGMIC1EN

MediaTek Proprietary and Confidential.

22

00000004 21

20

19

18

17

16

8 7 6 5 4 3 2 1 0 RG_D RG_D RG_AU RG_AUDDIGMI RG_AUDDIGMI RG_AUDDIGMI MICM MICHP DDIGM CNDUTY CPDUTY CBIAS ONEN CLKEN ICEN RW RW RW RW RW RW 0

0

0

0

0

0

1

0

18

17

AUDENC Control Register 14

Bit Name Type Reset

Name

23

0

Description Enables digital microphone monitor path Enables digital microphone monitor path 0: Disable 1: Enable Digital microphone negative duty control Digital microphone positive duty control Enables digital microphone monitor path selection 0: Digital CLK 1: CLKSQ Digital microphone slew rate control 11 > 10 > 01 > 00 Enables digital microphone 0: Disable 1: Enable

RG_AUDDIGMICEN

00002524

0

24

0

RW 0

0

24

23

22

00000004 21

20

19

16

8 7 6 5 4 3 2 1 0 RG_D RG_D RG_AU RG_AUDDIGMI RG_AUDDIGMI RG_AUDDIGMI MIC1M MIC1H DDIGM C1NDUTY C1PDUTY CBIAS1 ONEN PCLKEN IC1EN RW RW RW RW RW RW 0 0 0 0 0 0 1 0 0

Description Spare control bits for AVDD25MIC voltage domain Enables digital microphone monitor path Enables digital microphone monitor path 0: Disable 1: Enable Digital microphone negative duty control Digital microphone positive duty control Enables digital microphone monitor path selection 0: Digital CLK 1: CLKSQ Digital microphone slew rate control 11 > 10 > 01 > 00 Enables digital microphone

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 1022 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00002526

AUDENC_ANA_CON15

Bit Name Type Reset

31

Bit

15

Name

Type Reset

Description 0: Disable 1: Enable

30

29

28

14 13 12 RG_AU RG_AU RG_AU DMICBI DMICBI DMICBI AS0DC AS0DC AS0DC SW2NE SW2P2 SW2P1 N EN EN RW RW RW 0

0

27

11

0

Bit(s) 14

Name RG_AUDMICBIAS0DCSW2NEN

13

RG_AUDMICBIAS0DCSW2P2EN

12

RG_AUDMICBIAS0DCSW2P1EN

10

RG_AUDMICBIAS0DCSW0NEN

9

RG_AUDMICBIAS0DCSW0P2EN

8

RG_AUDMICBIAS0DCSW0P1EN

6:4

RG_AUDMICBIAS0VREF

3

RG_AUDPWDBMICBIAS3

2

RG_AUDMICBIAS0LOWPEN

1

RG_AUDMICBIAS0BYPASSEN

MediaTek Proprietary and Confidential.

AUDENC Control Register 15 26

25

24

10 9 8 RG_AU RG_AU RG_AU DMICBI DMICBI DMICBI AS0DC AS0DC AS0DC SW0NE SW0P2 SW0P1 N EN EN RW RW RW 0

0

0

00000000

23

22

21

20

19

18

17

16

7

6

5

4

3

2

1

0

RG_AU RG_AU RG_AU RG_AU DPWD DMICBI DMICBI DPWD RG_AUDMICBIAS0VREF BMICBI AS0LO AS0BYP BMICBI AS3 WPEN ASSEN AS0 RW 0

0

0

RW

RW

RW

RW

0

0

0

0

Description MIC bias 0 DC couple switch 2N 0: Off 1: On MIC bias 0 DC couple switch 2P2 0: Off 1: On MIC bias 0 DC couple switch 2P1 0: Off 1: On MIC bias 0 DC couple switch 0N 0: Off 1: On MIC bias 0 DC couple switch 0P2 0: Off 1: On MIC bias 0 DC couple switch 0P1 0: Off 1: On Selects MIC bias 0/2 Output voltage 000: 1.7V 001: 1.8V 010: 1.9V 011: 2.0V 100: 2.1V 101: 2.5V 110: 2.6V 111: 2.7V Powers down MIC bias 3 0: Power down 1: Power on Enables MIC bias 0 low power 0: Normal mode 1: Low power mode Enables MIC bias 0 bypass 0: Disable

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 1023 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 0

Name

Description 1: Enable Powers down MIC bias 0 0: Power down 1: Power on

RG_AUDPWDBMICBIAS0

00002528

AUDENC_ANA_CON16

AUDENC Control Register 16

Bit Name Type Reset

31

30

29

28

27

26

Bit

15

14

13

12

11

10

RG_AU RG_AU DMICBI DMICBI AS1HV AS1HV VREF EN

Name

Type Reset Bit(s) 13

RW

RW

0

0

Name RG_AUDMICBIAS1HVVREF

12

RG_AUDMICBIAS1HVEN

10

RG_BANDGAPGEN

9

RG_AUDMICBIAS1DCSW1NEN

8

RG_AUDMICBIAS1DCSW1PEN

6:4

RG_AUDMICBIAS1VREF

2

RG_AUDMICBIAS1LOWPEN

1

RG_AUDMICBIAS1BYPASSEN

0

RG_AUDPWDBMICBIAS1

MediaTek Proprietary and Confidential.

25

24

9 8 RG_AU RG_AU RG_BA DMICBI DMICBI NDGAP AS1DC AS1DC GEN SW1NE SW1PE N N RW RW RW 0

0

0

00000000

23

22

21

20

19

18

17

16

7

6

5

4

3

2

1

0

RG_AUDMICBIAS1VREF

RW 0

0

0

RG_AU RG_AU RG_AU DMICBI DMICBI DPWD AS1LO AS1BYP BMICBI WPEN ASSEN AS1 RW

RW

RW

0

0

0

Description Selects high voltage output voltage 0: 2.85V 1: 2.8V High voltage enable for micdetection 0: Disable 1: Enable Remote sense to bandgap ground 0: Disable 1: Enable MIC bias 1 DC couple switch 1N 0: Off 1: On MIC bias 1 DC couple switch 1P 0: Off 1: On Selects MIC bias 1 output voltage 000: 1.7V 001: 1.8V 010: 1.9V 011: 2.0V 100: 2.1V 101: 2.5V 110: 2.6V 111: 2.7V Enables MIC bias 1 low power 0: Normal mode 1: Low power mode Bypasses MIC bias 1 0: Disable 1: Enable Powers down MIC bias 1 0: Power down 1: Power on

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 1024 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

0000252A

Description

AUDENC_ANA_CON17

Bit Name Type Reset

31

30

29

28

27

Bit

15

14

13

12

11

Name

RG_AUDMICBIASSPARE

Type Reset

RW 0

0

0

0

Bit(s) 15:12 10

Name RG_AUDMICBIASSPARE RG_AUDMICBIAS2DCSW3NEN

9

RG_AUDMICBIAS2DCSW3P2EN

8

RG_AUDMICBIAS2DCSW3P1EN

6:4

RG_AUDMICBIAS2VREF

2

RG_AUDMICBIAS2LOWPEN

1

RG_AUDMICBIAS2BYPASSEN

0

RG_AUDPWDBMICBIAS2

MediaTek Proprietary and Confidential.

AUDENC Control Register 17 26

25

24

10 9 8 RG_AU RG_AU RG_AU DMICBI DMICBI DMICBI AS2DC AS2DC AS2DC SW3NE SW3P2 SW3P1 N EN EN RW RW RW 0

0

0

00000000

23

22

21

20

19

18

17

16

7

6

5

4

3

2

1

0

RG_AUDMICBIAS2VREF

RW 0

0

0

RG_AU RG_AU RG_AU DMICBI DMICBI DPWD AS2LO AS2BYP BMICBI WPEN ASSEN AS2 RW

RW

RW

0

0

0

Description MIC bias spare registers MIC bias 2 DC couple switch 3N 0: Off 1: On MIC bias 2 DC couple switch 3P2 0: Off 1: On MIC bias 2 DC couple switch 3P1 0: Off 1: On Selects MIC bias 2 output voltage 000: 1.7V 001: 1.8V 010: 1.9V 011: 2.0V 100: 2.1V 101: 2.5V 110: 2.6V 111: 2.7V Enables MIC bias 2 low power 0: Normal mode 1: Low power mode Bypasses MIC bias 2 0: Disable 1: Enable Powers down MIC bias 2 0: Power down 1: Power on

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 1025 of 1067

MT6359 PMIC Datasheet Confidential A 0000252C Bit Name Type Reset

AUDENC_ANA_CON18 31

30

29

28

27

AUDENC Control Register 18 26

25

24

23

22

00000000 21

15 14 13 12 11 10 9 8 7 6 5 RG_AU RG_AC DACCD RG_AC RG_EIN RG_AU RG_AU CDET2 RG_EIN RG_EIN RG_SW RG_SW RG_AC ETMIC CDET2 T0CON DACCD DACCD AUXRE T0HIRE T0NOH BUFSW BUFM CDETSE Name BIAS3P AUXSW FIGACC ETTVDE ETVTH SBYPAS NB YS EN ODSEL L ULLLO EN DET T BCAL S W RW RW RW RW RW RW RW RW RW RW RW Type 0 0 0 0 0 0 0 0 0 0 0 Reset

Bit

Bit(s) 15

Name RG_AUDACCDETMICBIAS3PULLLOW

14

RG_ACCDET2AUXSWEN

13

RG_ACCDET2AUXRESBYPASS

12

RG_EINT0HIRENB

11

RG_EINT0CONFIGACCDET

10

RG_EINT0NOHYS

9

RG_SWBUFSWEN

8

RG_SWBUFMODSEL

7

RG_ACCDETSEL

6

RG_AUDACCDETTVDET

5 4 3

RG_AUDACCDETVTHBCAL RG_AUDACCDETVTHACAL RG_AUDACCDETVIN1PULLLOW

2

RG_AUDACCDETMICBIAS2PULLLOW

1

RG_AUDACCDETMICBIAS1PULLLOW

MediaTek Proprietary and Confidential.

20

19

4

3

18

2 RG_AU RG_AU RG_AU DACCD DACCD DACCD ETMIC ETVIN1 ETVTH BIAS2P PULLLO ACAL ULLLO W W RW RW RW 0 0 0

17

16

1 RG_AU DACCD ETMIC BIAS1P ULLLO W RW 0

0 RG_AU DACCD ETMIC BIAS0P ULLLO W RW 0

Description Pulls low MIC bias 3 pads when MICBIAS is off 0: Disable 1: Enable Enables switch of ACCDET to AUXADC 0: Off 1: On Bypasses ACCDET to AUXADC resistors 0: Normal 1: Bypass Selects EINT0 High R 0: 2M 1: 500k Internal connection between HP_EINT and VDD 0: Disable 1: Enable EINT0 comparator no hysteresis 0: Disable (with hysteresis) 1: Enable (without hysteresis) Switch buffer turn on SW mode control for ACCDET to AUXADC 0: Power down 1: Power on Buffer power control 0: Hardware mode 1: Software mode Selects ACCDET input 0: ACCDET pin 1: MICP pin Puts audio accessory detection into TV mode 0: Disable 1: Enable Audio accessory detection voltage threshold B calibration Audio accessory detection voltage threshold A calibration Pulls low VIN1 pads when MICBIAS is off 0: Disable 1: Enable Pulls low MIC bias 2 pads when MICBIAS is off 0: Disable 1: Enable Pulls low MIC bias 1 pads when MICBIAS is off 0: Disable

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 1026 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 0

Name RG_AUDACCDETMICBIAS0PULLLOW

0000252E Bit Name Type Reset

AUDENC_ANA_CON19 31

30

15

14

29

28

13 12 RG_FD RG_FD RG_FD RG_AN VIN1PP Name EINT1T EINT0T ULLLO ALOGF YPE YPE DEN W RW RW RW RW Type

Bit

Reset

0

0

0

0

Bit(s) 15

Name RG_FDEINT1TYPE

14

RG_FDEINT0TYPE

13

RG_FDVIN1PPULLLOW

12

RG_ANALOGFDEN

10

RG_MTEST_CURRENT

9

RG_MTEST_SEL

8

RG_MTEST_EN

7:4

Description 1: Enable Pulls low MIC bias 0 pads when MICBIAS is off 0: Disable 1: Enable

RG_EINTCOMPVTH

2

RG_EINT1NOHYS

1

RG_EINT1HIRENB

0

RG_EINT1CONFIGACCDET

MediaTek Proprietary and Confidential.

AUDENC Control Register 19

00000000

27

26

25

24

23

22

21

20

19

18

17

11

10

9

8

7

6

5

4

3

2

1

0

0

RG_MT RG_MT RG_MT EST_CU EST_SE EST_EN RRENT L RW

RW

RW

0

0

0

RG_EINTCOMPVTH RW 0

0

0

0

16

0 RG_EIN RG_EIN RG_EIN T1CON T1NOH T1HIRE FIGACC YS NB DET RW RW RW 0

Description Analog path fast discharge: EINT1 type 0: Default open 1: Default close Analog path fast discharge: EINT0 type 0: Default open 1: Default close Analog path fast discharge: pull low VIN1P with ESD MOS 0: Disable 1: Enable Analog path fast discharge 0: Disable 1: Enable Moisture test mode using current mode 0: Normal mode 1: Current sinks to PAD_HP_EINT Selects moisture test mode 0: PAD_HP_EINT 1: PAD_ACCDET Enables moisture test mode 0: Normal mode 1: Moisture test current mode (ACCDET to AUXADC should be off.) EINT comparator threshold 0: 6/8 => 2.4V 1: 5/8 => 2V EINT1 comparator no hysteresis 0: Disable (with hysteresis) 1: Enable (without hysteresis) Selects EINT1 High R 0: 2M 1: 500k Internal connection between PAD_ACCDET and VDD 0: Disable 1: Enable (EINT1 connected with ACCDET pin and ACCDETSEL should be 1.)

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 1027 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00002530

Description

AUDENC_ANA_CON20

Bit Name Type Reset

31

30

29

Bit

15

14

13

Name

RG_EINT1CTURBO

Type Reset

0

Bit(s) 15:13 12 11 10 9 8 7:5 4 3 2 1 0

RW 0

28

27

AUDENC Control Register 20 26

24

12 11 10 9 8 RG_EIN RG_EIN RG_EIN RG_EIN RG_EIN T1INVE T1CMP T1CMP T1CEN T1EN N MEN EN RW RW RW RW RW 0 0 0 0 0

0

Name RG_EINT1CTURBO RG_EINT1INVEN RG_EINT1CEN RG_EINT1EN RG_EINT1CMPMEN RG_EINT1CMPEN RG_EINT0CTURBO RG_EINT0INVEN RG_EINT0CEN RG_EINT0EN RG_EINT0CMPMEN RG_EINT0CMPEN

00002532

25

00000000

23

22

21

7

6

5

RG_EINT0CTURBO

0

RW 0

0

20

19

18

17

16

4 3 2 1 0 RG_EIN RG_EIN RG_EIN RG_EIN RG_EIN T0INVE T0CMP T0CMP T0CEN T0EN N MEN EN RW RW RW RW RW 0 0 0 0 0

Description

AUDENC_ANA_CON21

AUDENC Control Register 21

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

RG_ACCDETSPARE RW 0 0 0 0

0

0

0

0

0

0

Bit(s) 15:0

0

0

0

0

0

Name RG_ACCDETSPARE

00002534

Description Spare control bits for ACCDET

AUDENC_ANA_CON22

AUDENC Control Register 22

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

RG_AUDENCSPAREVA18 RW 0 0 0 0

0

RG_AUDENCSPAREVA30 RW 0 0 0 0

0

0

0

MediaTek Proprietary and Confidential.

0

0

0

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 1028 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 15:8 7:0

Name RG_AUDENCSPAREVA18 RG_AUDENCSPAREVA30

00002536

Description Spare control bits for AVDD18 voltage domain Spare control bits for AVDD30 voltage domain

AUDENC_ANA_CON23

AUDENC Control Register 23

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

Bit

15

14

13

12

11

10

9

8

7

Name

RG_SPARE_VOW

Type Reset

0

Bit(s) 9:7 6

RW

Name RG_SPARE_VOW RG_VOWCLK_SEL_EN_VOW

5

RG_CLKAND_EN_VOW

4

RG_CLKSQ_EN_VOW

3

RG_AUDIO_VOW_EN

2

RG_CM_REFGENSEL

1

RG_CLKSQ_IN_SEL_TEST

0

RG_CLKSQ_EN

00002580

0

0

22

00000000 21

20

19

18

17

16

6 5 4 3 2 1 0 RG_VO RG_CLK RG_AU RG_CLK RG_CLK RG_CM RG_CL WCLK_ AND_E DIO_V SQ_IN_ SQ_EN _REFGE KSQ_E SEL_EN N_VO OW_E SEL_TE _VOW NSEL N _VOW W N ST RW RW RW RW RW RW RW 0

0

0

0

0

0

0

Description VOW spare Selects VOW CLK source 0: AND gate out 1: VOW CLKSQ out Enables VOW AND gate CLK 0: Disable 1: Enable Enables VOW CLK 0: Disable 1: Enable Enables AUDENC XO VOW 0: Disable 1: Enable Selects audio uplink common voltage 0: Default 1: Selection Audio CLK source 0: Use internal CLK (DCXO) 1: Use external CLK Enables CLKSQ 0: Off 1: On

AUDDEC_DSN_ID

AUDDEC Design ID Register

0000B180

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 1029 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00002582

Description

AUDDEC_DSN_REV0

AUDDEC Design Revision Register 0

00001010

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00002584

Description

AUDDEC_DSN_DBI

AUDDEC Design Bank Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00002586

Description

AUDDEC_DSN_FPI

AUDDEC Design Extra Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 1030 of 1067

MT6359 PMIC Datasheet Confidential A 00002588 Bit Name Type Reset

AUDDEC_ANA_CON0 31

15 RG_AU DHPRB SCCUR Name RENT_ VAUDP 32 RW Type 0 Reset

Bit

30

29

28

27

AUDDEC Control Register 0 26

25

24

23

22

00000000 21

20

19

14 13 12 11 10 9 8 7 6 5 4 3 RG_AU RG_AU RG_AU RG_AU RG_AU RG_AU RG_AU RG_AU DHPLB DHPRP DHPLP DHPRS DHPLS RG_AUDHPRM RG_AUDHPLM DHPRP DHPLP D_DAC SCCUR WRUP_ WRUP_ CDISAB CDISAB UXINPUTSEL_V UXINPUTSEL_V WRUP_ WRUP_ _PWL_ RENT_ IBIAS_ IBIAS_ LE_VA LE_VA AUDP32 AUDP32 VAUDP VAUDP UP_VA VAUDP VAUDP VAUDP UDP32 UDP32 32 32 32 32 32 32 RW RW RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) 15 14 13 12 11:10

Name RG_AUDHPRBSCCURRENT_VAUDP32 RG_AUDHPLBSCCURRENT_VAUDP32 RG_AUDHPRSCDISABLE_VAUDP32 RG_AUDHPLSCDISABLE_VAUDP32 RG_AUDHPRMUXINPUTSEL_VAUDP32

9:8

RG_AUDHPLMUXINPUTSEL_VAUDP32

7 6 5 4 3

RG_AUDHPRPWRUP_IBIAS_VAUDP32 RG_AUDHPLPWRUP_IBIAS_VAUDP32 RG_AUDHPRPWRUP_VAUDP32 RG_AUDHPLPWRUP_VAUDP32 RG_AUD_DAC_PWL_UP_VA32

2

RG_AUD_DAC_PWR_UP_VA32

1

RG_AUDDACRPWRUP_VAUDP32

0

RG_AUDDACLPWRUP_VAUDP32

MediaTek Proprietary and Confidential.

18

17

16

2

1

0

RG_AU RG_AU RG_AU D_DAC DDACR DDACL _PWR_ PWRUP PWRU UP_VA _VAUD P_VAU 32 P32 DP32 RW 0

RW 0

RW 0

Description Audio right headphone BSC current Audio left headphone BSC current Disables headphone right short circuit protection Disables headphone left short circuit protection Selects audio right headphone input multiplexor Positive/negative pins: 00: Open/Open 01: LOLP/LOLN 10: IDACRP/IDACRN 11: HSP/HSN (test mode) Selects audio left headphone input multiplexor Positive/negative pins: 00: Open/Open 01: LOLP/LOLN 10: IDACRP/IDACRN 11: HSP/HSN (test mode) Powers up audio right headphone bias Powers up audio left headphone bias Powers up audio right headphone Powers up audio left headphone Power down control for left channel audio biasgen 0: Power down 1: Enable Power down control for right channel audio biasgen 0: Power down 1: Enable Power down control for right-channel audio DAC 0: Power down 1: Enable Power down control for left-channel audio DAC 0: Power down 1: Enable

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 1031 of 1067

MT6359 PMIC Datasheet Confidential A 0000258A

AUDDEC_ANA_CON1

AUDDEC Control Register 1

Bit Name Type Reset

31

30

29

28

27

26

25

24

Bit

15

14

13

12

11

10

9

8

0

0

0

Name

Type Reset

RG_HPROUTSTGCTRL_ VAUDP32

RW 0

0

0

Bit(s) 14:12

Name RG_HPROUTSTGCTRL_VAUDP32

10:8

RG_HPLOUTSTGCTRL_VAUDP32

7 6 5 4 3 2 1 0

22

00000000 21

7 6 5 RG_HP RG_HP RG_HP RSHOR LSHOR RAUXF RG_HPLOUTSTGCTRL_V T2HPR T2HPLA BRSW_ AUDP32 AUX_E UX_EN EN_VA N_VAU _VAUD UDP32 DP32 P32 RW RW RW RW

RG_HPRSHORT2HPRAUX_EN_VAUDP32 RG_HPLSHORT2HPLAUX_EN_VAUDP32 RG_HPRAUXFBRSW_EN_VAUDP32 RG_HPLAUXFBRSW_EN_VAUDP32 RG_AUDHPROUTAUXPWRUP_VAUDP32 RG_AUDHPLOUTAUXPWRUP_VAUDP32 RG_AUDHPROUTPWRUP_VAUDP32 RG_AUDHPLOUTPWRUP_VAUDP32

MediaTek Proprietary and Confidential.

23

0

0

0

20

19

18

17

16

4

3 2 1 0 RG_AU RG_AU RG_AU RG_HP RG_AU DHPRO DHPLO DHPLO LAUXF DHPRO UTAUX UTAUX UTPW BRSW_ UTPWR PWRUP PWRUP RUP_V EN_VA UP_VA _VAUD _VAUD AUDP3 UDP32 UDP32 P32 P32 2 RW RW RW RW RW 0

0

0

0

0

Description Selects audio right headphone output stage 000: 1x 001: 2x 010: 3x 011: 4x 100: 5x 101: 6x 110: 7x 111: 8x Selects audio left headphone output stage 000: 1x 001: 2x 010: 3x 011: 4x 100: 5x 101: 6x 110: 7x 111: 8x Audio right headphone main & aux output stages short enable Audio left headphone main and aux output stages short enable Enables audio right headphone aux feedback resistor for audio depop Enables audio left headphone aux feedback resistor Powers up audio right headphone aux output stage Powers up audio left headphone aux output stage Powers up audio right headphone main output stage Powers up audio left headphone main output stage

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 1032 of 1067

MT6359 PMIC Datasheet Confidential A 0000258C Bit Name Type Reset

AUDDEC_ANA_CON2

AUDDEC Control Register 2

31

30

29

28

27

26

25

15

14

13

12

11

10

9

24

23

22

00000000 21

20

8 7 6 5 4 RG_AU RG_AU RG_HP RG_HPI RG_HPI RG_AU DREFN DHPTRI OUTPU NPUTR NPUTS DHPST RG_HPPSHORT2VCM_V _DERES RG_HPROUTPUTSTBEN TRESET ESET0_ TBENH ARTUP Name M_EN_ AUDP32 _EN_V H_VAUDP32 VAUDP 0_VAU VAUDP _VAUD _VAUD AUDP3 32 DP32 32 P32 P32 2 RW RW RW RW RW RW RW RW Type

Bit

Reset

0

0

14:12 11

RG_HPPSHORT2VCM_VAUDP32 RG_HPOUTPUTRESET0_VAUDP32

10

RG_HPINPUTRESET0_VAUDP32

9

RG_HPINPUTSTBENH_VAUDP32

8 7 6:4

RG_AUDREFN_DERES_EN_VAUDP32 RG_AUDHPSTARTUP_VAUDP32 RG_HPROUTPUTSTBENH_VAUDP32

2:0

RG_HPLOUTPUTSTBENH_VAUDP32

Bit Name 0

0

Name RG_AUDHPTRIM_EN_VAUDP32

Bit Name Type Reset

0

0

Bit(s) 15

0000258E

0

0

Type 0 Reset Bit(s) 15:13

0

30

29

15 14 13 RG_AUDHPRFINETRIM _VAUDP32 RW 0 0 0

0

0

0

17

16

3

2

1

0

RG_HPLOUTPUTSTBEN H_VAUDP32

RW

0

0

0

AUDDEC Control Register 3

28

27

26

25

24

12

11

10

9

8

RG_AUDHPRTRIM_VAUDP32

Name RG_AUDHPRFINETRIM_VAUDP32

MediaTek Proprietary and Confidential.

0

18

0

Description Enable control of trim circuit of HP 0: Disable trim circuit 1: Enable trim circuit HP driver positive output stage short to AU_REFN HPL/R driver SE output reset to 0V ground 0: No reset 1: Reset HP driver input reset to ground 0: No reset 1: Reset HP driver input stability enhancement option 0: No enhancement 1: Enhance HP ESD resistor@AU_REFN short enable Forces a startup mode in HP Amps if required Enhances HPR output stage STB [2]: Not used [1]: HPRN 800 ohm to GND [0]: HPRP 450 ohm to GND Enhances HPL output stage STB [2]: Not used [1]: HPLN 800 ohm to GND [0]: HPLP 450 ohm to GND

AUDDEC_ANA_CON3 31

0

19

RW

23

22

00000000 21

7 6 5 RG_AUDHPLFINETRIM_ VAUDP32 RW

20

19

18

17

16

4

3

2

1

0

RG_AUDHPLTRIM_VAUDP32 RW

Description Fine-trims offset voltage of HPR. sign bit format 000~011: 0V~0.12 mV, 0.04 mV/step

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 1033 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

12:8

RG_AUDHPRTRIM_VAUDP32

7:5

RG_AUDHPLFINETRIM_VAUDP32

4:0

RG_AUDHPLTRIM_VAUDP32

00002590 Bit Name Type Reset

AUDDEC_ANA_CON4 31

15 RG_AU DHPCO Name MP_EN _VAUD P32 RW Type

Bit

Reset

Description 100~111: 0V~-0.12 mV, 0.04 mV/step Trims offset voltage of HPR. sign bit format 00000~01111: 0V~2.7 mV, 0.18 mV/step 10000~11111: 0V~-2.7 mV, 0.18 mV/step Fine-trims offset voltage of HPL. sign bit format 000~011: 0V~0.12 mV, 0.04 mV/step 100~111: 0V~-0.12 mV, 0.04 mV/step Trims offset voltage of HPL. sign bit format 00000~01111: 0V~2.7 mV, 0.18 mV/step 10000~11111: 0V~-2.7 mV, 0.18 mV/step

AUDDEC Control Register 4

00000000

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

RG_AUDHPHFC OMPBUFGAINS EL_VAUDP32

RG_AUDHPHFCOMPRE SSEL_VAUDP32

RW 0

RW 0

0

Bit(s) 15 13:12

Name RG_AUDHPCOMP_EN_VAUDP32 RG_AUDHPHFCOMPBUFGAINSEL_VAUD P32

10:8 6:4 2:0

RG_AUDHPHFCOMPRESSEL_VAUDP32 RG_AUDHPLFCOMPRESSEL_VAUDP32 RG_AUDHPDIFFINPBIASADJ_VAUDP32

MediaTek Proprietary and Confidential.

RG_AUDHPLFCOMPRES SEL_VAUDP32

0

RG_AUDHPDIFFINPBIA SADJ_VAUDP32

RW 0

0

0

RW 0

0

0

0

Description Reserved Selects HP feedback cap 00: 15 pF 01: 10.5 pF 10: 7.5 pF 11: 3 pF Reserved Reserved Selects HP driver input differential pair bias current 000: 20u 001: 40u 010: 80u 011: 160u 100: 240u 101: 280u 110: 320u 111: 360u

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 1034 of 1067

MT6359 PMIC Datasheet Confidential A 00002592

AUDDEC_ANA_CON5

AUDDEC Control Register 5

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

Bit

15

14

13

12

11

10

9

8

7

Name Type Reset Bit(s) 6:4 2:0

22

00002594

20

19

6 5 4 RG_AUDHPDEDMGAIN ADJ_VAUDP32 RW 0

Name RG_AUDHPDEDMGAINADJ_VAUDP32 RG_AUDHPDECMGAINADJ_VAUDP32

00000000 21

0

0

3

18

17

16

2 1 0 RG_AUDHPDECMGAIN ADJ_VAUDP32 RW 0

0

0

Description Reserved Reserved

AUDDEC_ANA_CON6

AUDDEC Control Register 6

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

4

3

2

1

0

RW

RW

RW

RW

RW

0

0

0

0

0

0

0

RG_HS RG_HS RG_HSI RG_HSI RG_HS RG_AU OUT_S OUTPU NPUTR NPUTS OUTPU DHSST HORTV TRESET ESET0_ TBENH TSTBEN ARTUP CM_VA 0_VAU VAUDP _VAUD H_VAU _VAUD UDP32 DP32 32 P32 DP32 P32

Name

Type Reset Bit(s) 11

RW

5 RG_AU DHSBS CCURR ENT_V AUDP3 2 RW

Name RG_HSOUT_SHORTVCM_VAUDP32

10

RG_HSOUTPUTRESET0_VAUDP32

9

RG_HSINPUTRESET0_VAUDP32

8

RG_HSINPUTSTBENH_VAUDP32

7

RG_HSOUTPUTSTBENH_VAUDP32

6 5 4 3:2

RG_AUDHSSTARTUP_VAUDP32 RG_AUDHSBSCCURRENT_VAUDP32 RG_AUDHSSCDISABLE_VAUDP32 RG_AUDHSMUXINPUTSEL_VAUDP32

MediaTek Proprietary and Confidential.

RG_AU RG_AU RG_AU DHSSC RG_AUDHSMU DHSPW DHSP DISABL XINPUTSEL_VA RUP_IB WRUP E_VAU UDP32 IAS_VA _VAUD DP32 UDP32 P32 RW 0

RW 0

0

RW

RW

0

0

Description Short HS output to VCM (DCC: 0V; ACC: 1.4V) 0: Not short to VCM 1: Short to VCM HS driver DE outputs reset to 0V ground 0: No reset 1: Reset HS driver DE inputs reset to 0V ground 0: No reset 1: Reset HS driver input stability enhancement option 0: No enhancement 1: Enhance HS driver output stability enhancement option 0: No enhancement 1: Enhance Forces a startup mode in HS Amp if required Audio handset BSC current Disables headset short circuit protection Selects audio handset input multiplexor Positive/negative pins: 00: Open/Open 01: Voice playback (T-DAC) 10: Voice playback (L-DAC)

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 1035 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 1 0

Name

Description 11: LOLP/LOLN (test mode) Powers up audio headset bias Powers up audio headset

RG_AUDHSPWRUP_IBIAS_VAUDP32 RG_AUDHSPWRUP_VAUDP32

00002596

AUDDEC_ANA_CON7

AUDDEC Control Register 7

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

Bit

15

14

13

12

11

10

9

8

7

6

RG_AU RG_AU RG_LO RG_LO RG_LOI RG_LO RG_LOI D_DAC DDACT OUT_S OUTPU NPUTR OUTPU NPUTS _PWT_ PWRUP HORTV TRESET ESET0_ TSTBEN TBENH UP_VA _VAUD CM_VA 0_VAU VAUDP H_VAU _VAUD 32 P32 UDP32 DP32 32 DP32 P32

Name

Type Reset Bit(s) 13

RW

RW

RW

RW

RW

RW

RW

0

0

0

0

0

0

0

Name RG_AUD_DAC_PWT_UP_VA32

12

RG_AUDDACTPWRUP_VAUDP32

11

RG_LOOUT_SHORTVCM_VAUDP32

10

RG_LOOUTPUTRESET0_VAUDP32

9

RG_LOINPUTRESET0_VAUDP32

8

RG_LOOUTPUTSTBENH_VAUDP32

7

RG_LOINPUTSTBENH_VAUDP32

6 5 4 3:2

RG_AUDLOSTARTUP_VAUDP32 RG_AUDLOLBSCCURRENT_VAUDP32 RG_AUDLOLSCDISABLE_VAUDP32 RG_AUDLOLMUXINPUTSEL_VAUDP32

00000000 21

20

19

18

17

16

5 4 3 2 1 0 RG_AU RG_AU RG_AU RG_AU RG_AU DLOLBS DLOLP DLOST DLOLSC RG_AUDLOLM DLOLP CCURR WRUP_ ARTUP DISABL UXINPUTSEL_V WRUP ENT_V IBIAS_ _VAUD E_VAU AUDP32 _VAUD AUDP3 VAUDP P32 DP32 P32 2 32 RW RW RW RW RW RW 0

0

0

0

0

0

0

Description Power down control for third channel audio biasgen 0: Power down 1: Enable Power down control for third channel audio DAC 0: Power down 1: Enable Short LO output to VCM (DCC: 0V; ACC: 1.4V) 0: Not short to VCM 1: Short to VCM LOL/R driver SE output reset to 0V ground 0: No reset 1: Reset LO driver input reset to ground 0: No reset 1: Reset LO driver output stability enhancement option 0: No enhancement 1: Enhance LO driver input stability enhancement option 0: No enhancement 1: Enhance Forces a startup mode in LO Amps if required Audio left LO buffer BSC current Disables LO buffer left short circuit protection Selects audio left LO buffer input multiplexor Positive/negative pins: 00: Open/Open

C)

1 0

RG_AUDLOLPWRUP_IBIAS_VAUDP32 RG_AUDLOLPWRUP_VAUDP32

MediaTek Proprietary and Confidential.

10: Audio playback (T-DAC) 11: HPL/HPR (test mode) Powers up audio left LO buffer bias power up Powers up audio left LO buffer

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 1036 of 1067

MT6359 PMIC Datasheet Confidential A 00002598

AUDDEC_ANA_CON8

Bit Name Type Reset

31

30

29

Bit

15

14

13

Name

Type Reset

28

27

25

24

12 11 10 9 8 RG_AU RG_AUDHPSPK DHPSP RG_AUDHPSPK DET_OUTPUTM KDET_E DET_INPUTMU UXSEL_VAUDP N_VAU XSEL_VAUDP32 32 DP32 RW RW RW 0

0

Bit(s) 12 11:10

Name RG_AUDHPSPKDET_EN_VAUDP32 RG_AUDHPSPKDET_OUTPUTMUXSEL _VAUDP32

9:8

RG_AUDHPSPKDET_INPUTMUXSEL_V AUDP32

6 5:4

RG_AUDTRIMBUF_EN_VAUDP32 RG_AUDTRIMBUF_GAINSEL_VAUDP3 2

3:0

RG_AUDTRIMBUF_INPUTMUXSEL_V AUDP32

MediaTek Proprietary and Confidential.

AUDDEC Control Register 8 26

0

0

0

23

7

22

00000000 21

20

19

18

17

16

6 5 4 3 2 1 0 RG_AU DTRIM RG_AUDTRIMB RG_AUDTRIMBUF_INPUTMUXS BUF_E UF_GAINSEL_V EL_VAUDP32 N_VAU AUDP32 DP32 RW RW RW 0

0

0

0

0

0

0

Description Enables audio headphone speaker detection Selects audio headphone speaker detection output mux 00: Open 01: HPL 10: HPR 11: Unused Enables audio headphone speaker detection input mux 00: Open 01: DACLP 10: DACLN 11: DACRP Enables audio offset trimming buffer Selects audio offset trimming buffer gain 00: 0 dB 01: 6 dB 10: 12 dB 11: 18 dB Selects audio offset trimming buffer mux 0000: Open 0001: HPL 0010: HPR 0011: HSP 0100: HSN 0101: LOLP 0110: LOLN 0111: LORP 1000: LORN 1001: AVSS32 1010~1111: Unused

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 1037 of 1067

MT6359 PMIC Datasheet Confidential A 0000259A

AUDDEC_ANA_CON9

Bit Name Type Reset

31

30

Bit Name Type Reset

15

14

Bit(s) 15:8

7:0

0

0

28

27

26

25

24

23

22

13

12

11

10

9

8

7

RG_ABIDEC_RSVD0_VAUDP32 RW 0 0 0 0

Name RG_ABIDEC_RSVD0_VAUDP32

AUDDEC_ANA_CON10

Bit Name Type Reset

31

30

Bit Name Type Reset

15

14

0

0

0

0

20

19

18

17

16

6

5

4

3

2

1

0

0

RG_ABIDEC_RSVD0_VA32 RW 0 0 0 0

0

0

AUDDEC Control Register 10

29

28

27

26

25

24

23

22

13

12

11

10

9

8

7

6

RG_ABIDEC_RSVD2_VAUDP32 RW 0 0 0 0

Name RG_ABIDEC_RSVD2_VAUDP32

MediaTek Proprietary and Confidential.

0

00000000 21

Description Reserved one byte in VAUDP32 domain [7:4]: HP aux loop gain setting [3]: Enable HPR aux CMFB loop [2]: Enable HPL aux CMFB loop [1]: Enable HPR/L main CMFB loop [0]: Enable HPR/L main2 CMFB loop Reserved one byte in VA32 domain [6:4]: NV-regulator vout selection [3:1]: LDO vout selection 000: 1.607V 001: 1.456V 010: 1.506V 011: 1.557V 100: 1.657V 101: 1.707V 110: 1.757V 111: 1.807V [0]: Enable low-noise mode of DAC

RG_ABIDEC_RSVD0_VA32

0000259C

Bit(s) 15:8

AUDDEC Control Register 9

29

0

0

0

0

00000000 21

20

19

18

17

16

5

4

3

2

1

0

0

0

RG_ABIDEC_RSVD1_VAUDP32 RW 0 0 0 0

Description Reserved one byte in VAUDP32 domain [7]: Select HP feedback switch bulk 0: Internal NCP 1: External NCP [6:4]: Select HS output stage 000: 1x 001: 2x 010: 3x 011: 4x 100: 5x 101: 6x 110: 7x 111: 8x [3]: DAC low-noise filter switch toggle bit (SW mode)

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 1038 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

7:0

Name

Description [2]: Select DAC low-noise filter switch control 0: HW mode 1: SW mode [1]: Enable DAC low-noise filter low-leakge swich [0]: Enable DAC low-noise filter Reserved one byte in VAUDP32 domain [7]: Enable HPN output 4 kohm to GND [6:5]: Select HP damping adjustment 00: 10 kohm 01: 20 kohm 10: 30 kohm 11: 50 kohm [4:3]: Select HP Input diff pair bias 00: 40 uA 01: 80 uA 10: 120 uA 11: 160 uA [2]: Enable HP damping circuit [1]: Select HPR CMFB resister PW 0: AC 1: DC [0]: Select HPL CMFB resister PW 0: AC 1: DC

RG_ABIDEC_RSVD1_VAUDP32

0000259E

AUDDEC_ANA_CON11

AUDDEC Control Register 11

00004900

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

Bit

15

14

13

12

11

10

9

8

7

6

5

4

0

1

0

Name

Type Reset

RG_AUDBIASADJ_0_VAUDP32

RW 0

1

0

0

Bit(s) 15:7

Name RG_AUDBIASADJ_0_VAUDP32

3

RG_AUDZCDCLKSEL_VAUDP32

MediaTek Proprietary and Confidential.

1

0

19

18

17

16

3 2 1 0 RG_AU DZCDC RG_AUDZCDMUXSEL_V LKSEL_ AUDP32 VAUDP 32 RW RW 0

0

0

0

Description Audio bias adjustment 0 Bits: [2:0] Headphone Left/Right DR bias current setting [5:3] Handset DR bias current setting. DR bias settings [8:6] Line-out DR bias current setting. DR bias settings 000: 4 uA 001: 5 uA 010: 6 uA 011: 7 uA 100: 8 uA 101: 9A 110: 10 uA 111: 11 uA Increases ZCD comparator speed 0: Normal speed

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 1039 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 2:0

Name

Description 1: Improved speed Selects zero crossing detection mux 000: LOL 001: Unused 010: Handset 011: Unused 100: Bypass ZCD

RG_AUDZCDMUXSEL_VAUDP32

000025A0

AUDDEC_ANA_CON12

AUDDEC Control Register 12

00000155

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8 RG_AU DIBIAS PWRD N_VAU DP32 RW

7

6

5

4

3

2

1

0

1

0

0

1

Name

Type Reset Bit(s) 8

7:0

Name RG_AUDIBIASPWRDN_VAUDP32

RG_AUDBIASADJ_1_VAUDP32

MediaTek Proprietary and Confidential.

RG_AUDBIASADJ_1_VAUDP32

RW 1

0

1

0

1

Description Power down control for IbiasDistrib circuit 0: Enable 1: Disable Audio bias adjustment 1 Bits: [7:6] ZCD bias current setting 00: 3 uA 01: 4 uA 10: 5 uA 11: 6 uA [5:4] LOL/R ibias setting 00: 4 uA 01: 5 uA 10: 6 uA 11: 7 uA [3:2] HS ibias setting 00: 4 uA 01: 5 uA 10: 6 uA 11: 7 uA [1:0] HPL/R ibias setting 00: 4 uA 01: 5 uA 10: 6 uA

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 1040 of 1067

MT6359 PMIC Datasheet Confidential A 000025A2

AUDDEC_ANA_CON13

AUDDEC Control Register 13

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

Bit

15

14

13

12

11

10

9

8

7

Name

Type Reset

22

Name RG_AUDGLB_LP2_VOW_EN_VA32

5

RG_AUDGLB_LP_VOW_EN_VA32

4

RG_AUDGLB_PWRDN_VA32

2

RG_SEL_DELAY_VCORE

1

RG_SEL_DECODER_96K_VA32

0

RG_RSTB_DECODER_VA32

000025A4

20

6 5 4 RG_AU RG_AU RG_AU DGLB_L DGLB_L DGLB_ P2_VO P_VO PWRD W_EN_ W_EN_ N_VA3 VA32 VA32 2 RW RW RW 0

Bit(s) 6

00000010 21

0

19

18

3

2

1

AUDDEC_ANA_CON14

AUDDEC Control Register 14

29

28

27

26

25

24

23

22

21

20

19

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

Name

RG_AUDPMU_RSVD_VA18

Type Reset

RW

Bit(s) 15:8

0

Name RG_AUDPMU_RSVD_VA18

MediaTek Proprietary and Confidential.

0

0

00000000

30

0

0

Description Enable for AUDGLB VOW low-power mode2: OP and self-bias will be down and IREF from PMU_TOP Enable for AUDGLB VOW low-power mode: OP and self-bias should be on, IREF to VOW is 1/4. Power down control for audio global bias circuit 0: Enable 1: Disable; default on Selects AFIFO read clock delay 0: 5ns 1: 10ns Selects audio DAC clock 0: 6.5 MHz 1: 13 MHz Audio decoder reset 0: Reset 1: Normal

31

0

16

1 0 RG_SEL RG_SEL RG_RS _DECO _DELAY TB_DE DER_96 _VCOR CODER K_VA3 E _VA32 2 RW RW RW 0

Bit Name Type Reset

0

17

0

RG_NV RG_NV REG_P REG_E ULL0V_ N_VAU VAUDP DP32 32

0

0

RW

RW

0

0

18

17

16

2 1 0 RG_LCL RG_LCL DO_DE RG_LCL DO_DE C_REM DO_DE C_PDDI OTE_SE C_EN_ S_EN_ NSE_V VA32 VA18 A18 RW RW RW 0

0

0

Description Reserved 1 byte for VA18 domain [7:4] => NCP SW1~SW4 individual off control 4'b0000: On (normal operation) 4'b1111: All off [3:2] => Reserved [1:0] => CLDO power MOS on/off control 2'b00: Normal operation

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 1041 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 5 4 2

1 0

Name

Description 2'b11: CLDO Vout = AVDD18_AUD RG_NVREG_PULL0V_VAUDP32 NVREG output pulled to 0V when PD RG_NVREG_EN_VAUDP32 Enable for NVREG RG_LCLDO_DEC_REMOTE_SENSE_VA18 Selects LCLDO_DEC remote sense function 0: Local sense 1: Remote sense RG_LCLDO_DEC_PDDIS_EN_VA18 Enables LCLDO_DEC power down discharge RG_LCLDO_DEC_EN_VA32 Enable for LCLDO_DEC

00002600

AUDZCD_DSN_ID

AUDZCD Design ID Register

0000CC00

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00002602

Description

AUDZCD_DSN_REV0

AUDZCD Design Revision Register 0

00001000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00002604

Description

AUDZCD_DSN_DBI

AUDZCD Design Bank Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

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Page 1042 of 1067

MT6359 PMIC Datasheet Confidential A 00002606

AUDZCD_DSN_FPI

AUDZCD Design Extra Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

22

21

20

19

18

17

Bit(s)

Name

00002608

Description

ZCD_CON0

ZCD Control Register 0

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

Bit

15

14

13

12

11

10

9

8

7

Name

Type Reset Bit(s) 6

Name RG_AUDZCDTIMEOUTMODESEL

RG_AUDZCDGAINSTEPSIZE

3:1

RG_AUDZCDGAINSTEPTIME

RG_AUDZCDENABLE

MediaTek Proprietary and Confidential.

16

6 5 4 3 2 1 0 RG_AU DZCDTI RG_AU RG_AUDZCDGA RG_AUDZCDGAINSTEP MEOUT DZCDE INSTEPSIZE TIME MODES NABLE EL RW RW RW RW 0

5:4

0

00000000

0

0

0

0

0

0

Description If no zero crossings are detected over a period of 30 ms/5 ms, a timeout will occur and ZCD block enter SILENT mode. 0: 30 ms 1: 5 ms Gain step size to change the internal gain of ZCD 00: 1 dB 01: 2 dB 10: 4 dB 11: 8 dB Gain step time to change the internal gain of ZCD 000: 0 us 001: 250 us 010: 500 us 011: 1 ms 100: 2 ms 101: 4 ms 110: 8 ms 111: 16 ms Enables zero crossing detection (ZCD) function 0: Disable 1: Enable

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Page 1043 of 1067

MT6359 PMIC Datasheet Confidential A 0000260A

ZCD_CON1

ZCD Control Register 1

00000F9F

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

1

Bit(s) 11:7

Name RG_AUDLORGAIN

4:0

RG_AUDLOLGAIN

0000260C

19

18

17

16

3

2

1

0

RG_AUDLORGAIN

RG_AUDLOLGAIN

RW

RW

1

1

1

1

1

1

1

1

1

Description 00000: +8 dB 00001: +7 dB 10010:-10 dB 11111: -40 dB (mute) 00000: +8 dB 00001: +7 dB 10010:-10 dB 11111: -40 dB (mute)

ZCD_CON2

ZCD Control Register 2

00000F9F

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

RG_AUDHPRGAIN

RG_AUDHPLGAIN

RW 1

Bit(s) 11:7

Name RG_AUDHPRGAIN

4:0

RG_AUDHPLGAIN

0000260E

1

1

RW 1

1

1

1

1

1

1

Description 00000: +8 dB 00001: +7 dB 10010:-10 dB 11111: -40 dB (mute) 00000: +8 dB 00001: +7 dB 10010:-10 dB 11111: -40 dB (mute)

ZCD_CON3

ZCD Control Register 3

0000001F

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

RG_AUDHSGAIN RW 1

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

1

1

1

1

Page 1044 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 4:0

Name RG_AUDHSGAIN

00002610

Description 00000: +8 dB 00001: +7 dB 10010:-10 dB 11111: -40 dB (mute)

ZCD_CON4

ZCD Control Register 4

00000707

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

RG_AUDIVLGAIN

RW

RW

1

Bit(s) 10:8

Name RG_AUDIVRGAIN

2:0

RG_AUDIVLGAIN

00002612

ZCD_CON5

Bit Name Type Reset

29

28

Bit Name Type Reset

15

14

13

12

Name RG_AUDINTGAIN2 RG_AUDINTGAIN1

MediaTek Proprietary and Confidential.

1

1

1

19

18

17

16

3

2

1

0

1

1

ZCD Control Register 5

30

1

1

1

Description 000: +5 dB 001: +4 dB 010: +3 dB 011: +2 dB 100: +1 dB 101: 0 dB 110: -1 dB 111: -2 dB 000: +5 dB 001: +4 dB 010: +3 dB 011: +2 dB 100: +1 dB 101: 0 dB 110: -1 dB 111: -2 dB

31

Bit(s) 13:8 5:0

RG_AUDIVRGAIN

1

00003F3F

27

26

25

24

23

22

21

20

11

10

9

8

7

6

5

4

RG_AUDINTGAIN2

RG_AUDINTGAIN1

RO

RO

1

1

1

1

1

1

1

1

Description Monitor signal: Internal gain 2 Monitor signal: Internal gain 1

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 1045 of 1067

MT6359 PMIC Datasheet Confidential A 00002680

ACCDET_DSN_DIG_ID

ACCDET Design ID Register

0000CA00

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00002682

Description

ACCDET_DSN_DIG_REV0

ACCDET Design Revision Register 0

00001000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00002684

Description

ACCDET_DSN_DBI

ACCDET Design Bank Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

00002686

Description

ACCDET_DSN_FPI

ACCDET Design Extra Information Register

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 1046 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

00002688

Description

ACCDET_CON0

ACCDET Control Register 0

Bit Name Type Reset

31

30

29

28

27

26

25

Bit

15

14

13

12

11

10

9

Name

Type Reset Bit(s) 9

8

ACCDET_CON1

22

21

20

19

18

17

16

7

6

5

4

3

2

1

0

0

ACCDET Control Register 1

Bit Name Type Reset

31

30

29

28

27

26

Bit

15

14

13

12

11

10

Name

Type Reset

25

Name ACCDET_EINT1_INVERTER_SEQ_INIT

8

ACCDET_EINT1_INVERTER_SW_EN

7

ACCDET_EINT0_INVERTER_SEQ_INIT

6

ACCDET_EINT0_INVERTER_SW_EN

24

23

22

00000000 21

20

19

18

17

16

9 8 7 6 5 4 3 2 1 0 ACCDE ACCDE ACCDE ACCDE T_EINT T_EINT ACCDE ACCDE ACCDE ACCDE T_EINT T_EINT ACCDE ACCDE 1_INVE 0_INVE T_EINT T_EINT T_EINT T_EINT 1_INVE 0_INVE T_SEQ_ T_SW_ RTER_S RTER_S 1_SEQ_ 1_SW_ 0_SEQ_ 0_SW_ RTER_S RTER_S INIT EN EQ_INI EQ_INI INIT EN INIT EN W_EN W_EN T T RW RW RW RW RW RW RW RW RW RW 0

MediaTek Proprietary and Confidential.

23

Description Test control 1'b0: HW mode 1'b1: SW mode Selection signal of which AUXADC or ACCDET to trigger ANA voltage measurement 1'b0: AUXADC 1'b1: ACCDET

ACCDET_AUXADC_ANASWCTRL_SEL

0000268A

Bit(s) 9

8 ACCDE AUDAC T_AUX CDETA ADC_A UXADC NASWC SWCTR TRL_SE L_SEL L RW RW 0

Name AUDACCDETAUXADCSWCTRL_SEL

24

00000000

0

0

0

0

0

0

0

0

0

Description Initializes EINT1 inverter status default value 1'b0: Disable 1'b1: Enable Enables EINT1 inverter detection 1'b0: Disable 1'b1: Enable Initializes EINT0 inverter status default value 1'b0: Disable 1'b1: Enable Enables EINT0 inverter detection 1'b0: Disable

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 1047 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

5

ACCDET_EINT1_SEQ_INIT

4

ACCDET_EINT1_SW_EN

3

ACCDET_EINT0_SEQ_INIT

2

ACCDET_EINT0_SW_EN

1

ACCDET_SEQ_INIT

0

ACCDET_SW_EN

0000268C

Description 1'b1: Enable Initializes EINT1 status default value 1'b0: Disable 1'b1: Enable Enables EINT1 detection 1'b0: Disable 1'b1: Enable Initializes EINT0 status default value 1'b0: Disable 1'b1: Enable Enables EINT0 detection 1'b0: Disable 1'b1: Enable Initializes ACCDET status default value 1'b0: normal mode 1'b1: initialized mode Enables ACCDET 1'b0: Disable 1'b1: Enable

ACCDET_CON2

ACCDET Control Register 2

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

Bit

15

14

13

12

11

10

9

8

7

6

Name

Type Reset

5 ACCDE ACCDE T_EINT T_EINT _CMP _CTUR MEN_P BO_PW WM_E M_EN N RW RW 0

Bit(s) 6

Name ACCDET_EINT_CTURBO_PWM_EN

5

ACCDET_EINT_CMPMEN_PWM_EN

4

ACCDET_EINT_CMPEN_PWM_EN

3

ACCDET_EINT_EN_PWM_EN

2

ACCDET_MBIAS_PWM_EN

1

ACCDET_VTH_PWM_EN

MediaTek Proprietary and Confidential.

00000000 21

0

20

19

18

17

16

4

3

2

1

0

ACCDE T_EINT _CMPE N_PW M_EN

ACCDE T_EINT _EN_P WM_E N

ACCDE T_MBI AS_PW M_EN

RW

RW

RW

RW

RW

0

0

0

0

0

ACCDE ACCDE T_VTH T_CMP _PWM _PWM _EN _EN

Description Enables PWM of DA_CTURBO 1'b0: Disable 1'b1: Enable Enables PWM of DA_EINTCMPMEN 1'b0: Disable 1'b1: Enable Enables PWM of DA_EINTCMPEN 1'b0: Disable 1'b1: Enable Enables PWM of DA_EINTEN 1'b0: Disable 1'b1: Enable Enables PWM of ACCDET MBIAS unit 1'b0: Disable 1'b1: Enable Enables PWM of ACCDET voltage threshold unit 1'b0: Disable

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 1048 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 0

Name

Description 1'b1: Enable Enables PWM of ACCDET comparator 1'b0: Disable 1'b1: Enable

ACCDET_CMP_PWM_EN

0000268E

ACCDET_CON3

ACCDET Control Register 3

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

ACCDET_PWM_WIDTH RW 0 0 0 0

0

0

0

0

0

0

Bit(s) 15:0

0

0

0

0

0

Name ACCDET_PWM_WIDTH

00002690

Description ACCDET PWM width PWM output frequency = 32,768/(PWM_WIDTH + 1) Hz

ACCDET_CON4

ACCDET Control Register 4

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

ACCDET_PWM_THRESH RW 0 0 0 0

0

0

0

0

0

0

Bit(s) 15:0

0

Bit(s) 15

0

0

Description ACCDET PWM threshold PWM output duty cycle = (PWM_THRESH + 1)/(PWM_WIDTH + 1) PWM output high time = (PWM_THRESH + 1)/32,768 sec

ACCDET_CON5 31

15 ACCDE T_FALL Name _DELA Y RW Type 0 Reset

Bit

0

Name ACCDET_PWM_THRESH

00002692 Bit Name Type Reset

0

ACCDET Control Register 5

00000101

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

1

ACCDET_RISE_DELAY

0

0

0

Name ACCDET_FALL_DELAY

MediaTek Proprietary and Confidential.

0

0

0

1

RW 0

0

Description Falling delay cycle compared to PWM waveform

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 1049 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

14:0

ACCDET_RISE_DELAY

00002694

Description To make sure the plug state is stable after ACCDET is disabled, the suitable falling delay cycle is necessary. Rising delay cycle compared to PWM waveform To make sure the plug state is stable before ACCDET is enabled, the suitable rising delay cycle is necessary.

ACCDET_CON6

ACCDET Control Register 6

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

Bit

15

14

13

12

11

10

9

8

7

Name Type Reset Bit(s) 6:4

2:0

00000000 21

20

6 5 4 ACCDET_EINT_CMPME N_PWM_WIDTH RW 0

0

19

3

0

18

17

16

2 1 0 ACCDET_EINT_CMPME N_PWM_THRESH RW 0

0

0

19

18

17

16

3

2

1

0

Name Description ACCDET_EINT_CMPMEN_PWM_WIDTH ACCDET DA_EINTCMPMEN PWM width 3'b000: 50 ms 3'b001: 80 ms 3'b010: 100 ms 3'b011: 200 ms 3'b100: 400 ms 3'b101: 500 ms 3'b110: 800 ms 3'b111: 1,000 ms ACCDET_EINT_CMPMEN_PWM_THRESH ACCDET DA_EINTCMPMEN PWM threshold 3'b000: 1 ms 3'b001: 2 ms 3'b010: 4 ms 3'b011: 5 ms 3'b100: 8 ms 3'b101: 10 ms 3'b110: 20 ms 3'b111: 30 ms

00002696

EN_PWM_WID

22

ACCDET_CON7

Bit Name Type Reset

31

30

Bit

15

14

29

28

13 12 ACCDET_EINT_

Name Type Reset

MediaTek Proprietary and Confidential.

WIDTH RW 0

0

ACCDET Control Register 7 27

26

25

24

23

22

11

10

9

8

7

6

ACCDET_EINT_CMPEN_ PWM_THRESH

00000000 21

5 4 ACCDET_EINT_ TH RW

RW 0

0

0

20

0

ACCDET_EINT_EN_PW M_THRESH RW

0

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

0

0

0

Page 1050 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s) 13:12

Name ACCDET_EINT_CMPEN_PWM_WIDTH

10:8

ACCDET_EINT_CMPEN_PWM_THRESH

5:4

ACCDET_EINT_EN_PWM_WIDTH

2:0

ACCDET_EINT_EN_PWM_THRESH

00002698

ACCDET_CON8

Description ACCDET DA_EINTCMPEN PWM width 2'b00: 4 ms 2'b01: 8 ms 2'b10: 16 ms 2'b11: 32 ms ACCDET DA_EINTCMPEN PWM threshold 3'b000: 0.5 ms 3'b001: 1 ms 3'b010: 2 ms 3'b011: 3 ms 3'b100: 4 ms 3'b101: 8 ms 3'b110: 16 ms 3'b111: 32 ms ACCDET DA_EINTEN PWM width 2'b00: 4 ms 2'b01: 8 ms 2'b10: 16 ms 2'b11: 32 ms ACCDET DA_EINTEN PWM threshold 3'b000: 0.5 ms 3'b001: 1 ms 3'b010: 2 ms 3'b011: 3 ms 3'b100: 4 ms 3'b101: 8 ms 3'b110: 16 ms 3'b111: 32 ms

ACCDET Control Register 8

00000010

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

ACCDET_DEBOUNCE0 RW 0 0 0 0

0

1

0

0

0

0

Bit(s) 15:0

0

0

0

0

Name ACCDET_DEBOUNCE0

MediaTek Proprietary and Confidential.

0

Description Debounce time control of state 0 Debounce time = (DEBOUNCE/freq) sec In the TV mode, freq is bus clock and 32,768 Hz in the MIC mode.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 1051 of 1067

MT6359 PMIC Datasheet Confidential A 0000269A

ACCDET_CON9

ACCDET Control Register 9

00000010

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

ACCDET_DEBOUNCE1 RW 0 0 0 0

0

1

0

0

0

0

Bit(s) 15:0

0

0

0

0

0

Name ACCDET_DEBOUNCE1

0000269C

Description Debounce time control of state 1 Debounce time = (DEBOUNCE/freq) sec In the TV mode, freq is bus clock and 32,768 Hz in the MIC mode.

ACCDET_CON10

ACCDET Control Register 10

00000010

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

ACCDET_DEBOUNCE2 RW 0 0 0 0

0

1

0

0

0

0

Bit(s) 15:0

0

0

0

0

0

Name ACCDET_DEBOUNCE2

0000269E

Description Debounce time control of state 2 Debounce time = (DEBOUNCE/freq) sec In the TV mode, freq is bus clock 32,768 Hz in the MIC mode.

ACCDET_CON11

ACCDET Control Register 11

00000010

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

ACCDET_DEBOUNCE3 RW 0 0 0 0

0

1

0

0

0

0

Bit(s) 15:0

0

0

0

0

Name ACCDET_DEBOUNCE3

MediaTek Proprietary and Confidential.

0

Description Debounce time control of state 3 Debounce time = (DEBOUNCE/freq) sec In the TV mode, freq is bus clock 32,768 Hz in the MIC mode.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 1052 of 1067

MT6359 PMIC Datasheet Confidential A 000026A0

ACCDET_CON12

ACCDET Control Register 12

00000005

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000026A2

Description

ACCDET_CON13

ACCDET Control Register 13

00000004

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

19

18

17

16

3

2

1

0

Bit(s)

Name

000026A4 Bit Name Type Reset Bit Name Type Reset Bit(s) 15:12

Description

ACCDET_CON14 31

30

29

28

15

14

13

12

ACCDET_EINT_DEBOUNCE3 RW 1 1 1 0

Name ACCDET_EINT_DEBOUNCE3

ACCDET Control Register 14 27

26

25

24

11

10

9

8

ACCDET_EINT_DEBOUNCE2 RW 1 1 1 0

0000EEEE

23

22

21

20

7

6

5

4

ACCDET_EINT_DEBOUNCE1 RW 1 1 1 0

ACCDET_EINT_DEBOUNCE0 RW 1 1 1 0

Description ACCDET EINT debounce time 4'd0: 0 ms (bypass) 4'd1: 0.12 ms 4'd2: 0.25 ms 4'd3: 0.5 ms 4'd4: 0.75 ms 4'd5: 1 ms 4'd6: 2 ms 4'd8: 8 ms 4'd9: 16 ms 4'd10: 32 ms 4'd11: 48 ms 4'd12: 64 ms

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 1053 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

11:8

ACCDET_EINT_DEBOUNCE2

7:4

ACCDET_EINT_DEBOUNCE1

3:0

ACCDET_EINT_DEBOUNCE0

MediaTek Proprietary and Confidential.

Description 4'd13: 128 ms 4'd14: 256 ms 4'd15: 512 ms ACCDET EINT debounce time 4'd0: 0 ms (bypass) 4'd1: 0.5 ms 4'd2: 0.75 ms 4'd3: 0.9 ms 4'd4: 1.5 ms 4'd5: 1.8 ms 4'd6: 3 ms 4'd7: 3.5 ms 4'd8: 3.8 ms 4'd9: 4 ms 4'd10: 4.5 ms 4'd11: 5 ms 4'd12: 7 ms 4'd13: 9 ms 4'd14: 19 ms 4'd15: 25 ms ACCDET EINT debounce time 4'd0: 0 ms (bypass) 4'd1: 0.5 ms 4'd2: 0.75 ms 4'd3: 0.9 ms 4'd4: 1.5 ms 4'd5: 1.8 ms 4'd6: 3 ms 4'd7: 3.5 ms 4'd8: 3.8 ms 4'd9: 4 ms 4'd10: 4.5 ms 4'd11: 5 ms 4'd12: 7 ms 4'd13: 9 ms 4'd14: 19 ms 4'd15: 25 ms ACCDET EINT debounce time 4'd0: 0 ms (bypass) 4'd1: 0.12 ms 4'd2: 0.25 ms 4'd3: 0.5 ms 4'd4: 0.75 ms 4'd5: 1 ms 4'd6: 2 ms 4'd7: 4 ms 4'd8: 8 ms 4'd9: 16 ms 4'd10: 32 ms 4'd11: 48 ms 4'd12: 64 ms 4'd13: 128 ms 4'd14: 256 ms

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 1054 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

000026A6

Description 4'd15: 512 ms

ACCDET_CON15

ACCDET Control Register 15

0000000E

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

Bit

15

14

13

12

11

10

9

8

7

6

5

4

Name Type Reset Bit(s) 3:0

Name ACCDET_EINT_INVERTER_DEBOUNCE

000026A8

19

18

17

16

3 2 1 0 ACCDET_EINT_INVERTER_DEB OUNCE RW 1

1

1

0

Description ACCDET EINT INVERTER debounce time 4'd0: 0 ms (bypass) 4'd1: 0.12 ms 4'd2: 0.25 ms 4'd3: 0.5 ms 4'd4: 0.75 ms 4'd5: 1 ms 4'd6: 2 ms 4'd7: 4 ms 4'd8: 8 ms 4'd9: 16 ms 4'd10: 32 ms 4'd11: 48 ms 4'd12: 64 ms 4'd13: 128 ms 4'd14: 256 ms 4'd15: 512 ms

ACCDET_CON16

ACCDET Control Register 16

00000ABF

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

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Page 1055 of 1067

MT6359 PMIC Datasheet Confidential A 000026AA

ACCDET_CON17

ACCDET Control Register 17

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

20

19

18

17

16

1

0

Bit(s)

Name

000026AC

Description

ACCDET_CON18

Bit Name Type Reset

31

30

29

28

Bit

15

14

13

12

Name Type Reset Bit(s) 14:12 11

ACCDET Control Register 18 27

26

11 10 ACCDE ACCDE ACCDET_EINT_M_PLUG T_EINT T_EINT _IN_NUM 1_IRQ_ 0_IRQ_ CLR CLR RW RW RW 0

0

0

0

Name ACCDET_EINT_M_PLUG_IN_NUM ACCDET_EINT1_IRQ_CLR

10

ACCDET_EINT0_IRQ_CLR

8

ACCDET_IRQ_CLR

4 3 2 0

ACCDET_EINT_IN_INVERSE ACCDET_EINT1_IRQ ACCDET_EINT0_IRQ ACCDET_IRQ

MediaTek Proprietary and Confidential.

0

00000000

25

24

23

22

21

9

8

7

6

5

ACCDE T_IRQ_ CLR RW 0

4 3 2 ACCDE ACCDE ACCDE T_EINT T_EINT T_EINT _IN_IN 1_IRQ 0_IRQ VERSE RW RO RO 0

0

0

ACCDE T_IRQ RO 0

Description After number of eint_m_plug_in is received, the interrupt will be valid. Clears ACCDET_EINT1 interrupt status When ACCDET_EINT1 interrupt is asserted, IRQ_CLR must be set to 1 to clear the interrupt status. This bit will pause all activities of ACCDET_EINT1 design until both the interrupt status and IRQ_CLR are cleared. Clears ACCDET_EINT0 interrupt status When ACCDET_EINT0 interrupt is asserted, IRQ_CLR must be set to 1 to clear the interrupt status. This bit will pause all activities of ACCDET_EINT design until both the interrupt status and IRQ_CLR are cleared. Clears ACCDET interrupt status When ACCDET interrupt is asserted, IRQ_CLR must be set to 1 to clear the interrupt status. This bit will pause all activities of ACCDET design until both the interrupt status and IRQ_CLR are cleared. When EINT default close: inverse = 1 Clears ACCDET_EINT1 interrupt status Clear ACCDET_EINT0 interrupt status ACCDET interrupt status Due to this register is cleared by the hardware, the interrupt edgesensitive scheme should be adopted for this design.

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Page 1056 of 1067

MT6359 PMIC Datasheet Confidential A 000026AE

ACCDET_CON19

ACCDET Control Register 19

Bit Name Type Reset

31

30

29

28

27

26

Bit

15

14

13

12

11

10

Name

Type Reset Bit(s) 10 9 8 7 6 5 4 3 2 1 0

9 ACCDE ACCDE T_EINT T_EINT 1_CTU 1_CEN_ RBO_S STABLE TABLE RW RW 0

Name ACCDET_EINT1_CEN_STABLE ACCDET_EINT1_CTURBO_STABLE ACCDET_EINT1_CMPMEN_STABLE ACCDET_EINT1_CMPEN_STABLE ACCDET_EINT1_EN_STABLE ACCDET_EINT0_CEN_STABLE ACCDET_EINT0_CTURBO_STABLE ACCDET_EINT0_CMPMEN_STABLE ACCDET_EINT0_CMPEN_STABLE ACCDET_EINT0_EN_STABLE ACCDET_DA_STABLE

000026B0

25

0

24

8 ACCDE T_EINT 1_CMP MEN_S TABLE RW 0

23

22

00000000 21

20

7 6 5 4 ACCDE ACCDE ACCDE ACCDE T_EINT T_EINT T_EINT T_EINT 1_CMP 0_CTU 1_EN_S 0_CEN_ EN_ST RBO_S TABLE STABLE ABLE TABLE RW RW RW RW 0

0

0

19

3 ACCDE T_EINT 0_CMP MEN_S TABLE RW

18

17

16

2 1 0 ACCDE ACCDE T_EINT ACCDE T_EINT 0_CMP T_DA_ 0_EN_S EN_ST STABLE TABLE ABLE RW RW RW

0

0

0

0

0

Description DA_EINT1CEN stable control DA_EINT1CTURBO stable control DA_EINT1CMPMEN stable control DA_EINT1CMPEN stable control DA_EINT1EN stable control DA_EINT0CEN stable control DA_EINT0CTURBO stable control DA_EINT0CMPMEN stable control DA_EINT0CMPEN stable control DA_EINT0EN stable control ACCDET DA signal stable control

ACCDET_CON20

ACCDET Control Register 20

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000026B2

Description

ACCDET_CON21

ACCDET Control Register 21

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 1057 of 1067

MT6359 PMIC Datasheet Confidential A 000026B4

ACCDET_CON22

ACCDET Control Register 22

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000026B6

Description

ACCDET_CON23

ACCDET Control Register 23

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000026B8

Description

ACCDET_CON24

ACCDET Control Register 24

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000026BA

Description

ACCDET_CON25

ACCDET Control Register 25

000000FF

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 1058 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

000026BC

Description

ACCDET_CON26

ACCDET Control Register 26

000000AB

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000026BE

Description

ACCDET_CON27

ACCDET Control Register 27

000000AB

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000026C0

Description

ACCDET_CON28

ACCDET Control Register 28

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

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Page 1059 of 1067

MT6359 PMIC Datasheet Confidential A 000026C2

ACCDET_CON29

ACCDET Control Register 29

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000026C4

Description

ACCDET_CON30

ACCDET Control Register 30

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000026C6

Description

ACCDET_CON31

ACCDET Control Register 31

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000026C8

Description

ACCDET_CON32

ACCDET Control Register 32

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

© 2018 - 2020 MediaTek Inc. All rights reserved. Unauthorized reproduction or disclosure of this document, in whole or in

Page 1060 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

000026CA

Description

ACCDET_CON33

ACCDET Control Register 33

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000026CC

Description

ACCDET_CON34

ACCDET Control Register 34

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000026CE

Description

ACCDET_CON35

ACCDET Control Register 35

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

MediaTek Proprietary and Confidential.

Description

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Page 1061 of 1067

MT6359 PMIC Datasheet Confidential A 000026D0

ACCDET_CON36

ACCDET Control Register 36

0000006F

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000026D2

Description

ACCDET_CON37

ACCDET Control Register 37

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000026D4

Description

ACCDET_CON38

ACCDET Control Register 38

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit(s)

Name

000026D6

Description

ACCDET_CON39

ACCDET Control Register 39

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit Name Type Reset

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MediaTek Proprietary and Confidential.

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Page 1062 of 1067

MT6359 PMIC Datasheet Confidential A Bit(s)

Name

000026D8

Description

ACCDET_CON40

ACCDET Control Register 40

00000000

Bit Name Type Reset

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0 ACCDE T_MO N_FLA G_EN RW

Name

ACCDET_MON_FLAG_SEL

Type Reset

0

Bit(s) 7:4 0

RW

Name ACCDET_MON_FLAG_SEL ACCDET_MON_FLAG_EN

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0

0

0

0

Description Selects ACCDET monitor flag Enables ACCDET monitor flag

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MT6359 PMIC Datasheet Confidential A

4

Application Notes

4.1

Configuration for Unused Buck Converter

The figure below shows the configuration for MT6359 buck converters that is not used.  Configuration for VPA not in use: – Connect VSYS_VPA to VBAT; connect GND_VPA to GND – VPA & VPA_FB: Floating – RG_BUCK_VPA_EN = 0 & RG_VPA_NDIS_EN = 1 (software setting)

Figure 4-1. Configuration for unused DC/DC

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MT6359 PMIC Datasheet Confidential A

5 5.1

MT6359 Packaging Package Dimension

Figure 5-1. Package dimension

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MT6359 PMIC Datasheet Confidential A

Appendix

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MT6359 PMIC Datasheet Confidential A

Exhibit 1 Terms and Conditions Your access to and use of this document and the information contained herein (collectively this “Document”) is subject to your (including the corporation or other legal entity you represent, collectively “You”) acceptance of the terms and conditions set forth below (“T&C”). By using, accessing or downloading this Document, You are accepting the T&C and agree to be bound by the T&C. If You don’t agree to the T&C, You may not use this Document and shall immediately destroy any copy thereof. This Document contains information that is confidential and proprietary to MediaTek Inc. and/or its affiliates (collectively “MediaTek”) or its licensors and is provided solely for Your internal use with MediaTek’s chipset(s) described in this Document and shall not be used for any other purposes (including but not limited to identifying or providing evidence to support any potential patent infringement claim against MediaTek or any of MediaTek’s suppliers and/or direct or indirect customers). Unauthorized use or disclosure of the information contained herein is prohibited. You agree to indemnify MediaTek for any loss or damages suffered by MediaTek for Your unauthorized use or disclosure of this Document, in whole or in part. MediaTek and its licensors retain titles and all ownership rights in and to this Document and no license (express or implied, by estoppels or otherwise) to any intellectual propriety rights is granted hereunder. This Document is subject to change without further notification. MediaTek does not assume any responsibility arising out of or in connection with any use of, or reliance on, this Document, and specifically disclaims any and all liability, including, without limitation, consequential or incidental damages. THIS DOCUMENT AND ANY OTHER MATERIALS OR TECHNICAL SUPPORT PROVIDED BY MEDIATEK IN CONNECTION WITH THIS DOCUMENT, IF ANY, ARE PROVIDED “AS IS” WITHOUT WARRANTY OF ANY KIND, WHETHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE. MEDIATEK SPECIFICALLY DISCLAIMS ALL WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, COMPLETENESS OR ACCURACY AND ALL WARRANTIES ARISING OUT OF TRADE USAGE OR OUT OF A COURSE OF DEALING OR COURSE OF PERFORMANCE. MEDIATEK SHALL NOT BE RESPONSIBLE FOR ANY MEDIATEK DELIVERABLES MADE TO MEET YOUR SPECIFICATIONS OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM. Without limiting the generality of the foregoing, MediaTek makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does MediaTek assume any liability arising out of the application or use of any product, circuit or software. You agree that You are solely responsible for the designing, validating and testing Your product incorporating MediaTek’s product and ensure such product meets applicable standards and any safety, security or other requirements. The above T&C and all acts in connection with the T&C or this Document shall be governed, construed and interpreted in accordance with the laws of Taiwan, without giving effect to the principles of conflicts of law.

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