MicroSystem Based on SiP Technology 9811900825, 9789811900822
121 53 53MB
English Pages [867]
Preface
Brief Introduction of the New Book
Contents
About the Author
Part I Concept and Technology
1 From Moore's Law to Function Density Law
1.1 Moore's Law
1.2 Two Problems Facing Moore's Law
1.2.1 Reduction of Micro-Scale
1.2.2 Consumption of Macro-Resources
1.3 Function Density Law
1.3.1 Description of Function Density Law
1.3.2 Six Level Classification of Electronic Systems
1.3.3 Comparison of Moore's Law and Function Density Law
1.3.4 Applications of Function Density Law
1.3.5 Extension of Function Density Law
1.4 General Function Density Law
1.4.1 System Space Definition
1.4.2 Earth Space and Human Cosmic Space
1.4.3 General Function Density Law
2 From SiP to Si3P
2.1 Concept Deepening: From SiP to Si3P
2.2 Integration of Si3P
2.2.1 Chip Level Integration
2.2.2 PCB Level Integration
2.2.3 Package Level Integration
2.2.4 Summary of Integration
2.3 Interconnection of Si3P
2.3.1 Interconnection of EM
2.3.2 Interconnection of Thermo
2.3.3 Interconnection of Force
2.3.4 Summary of Interconnection
2.4 Intelligence of Si3P
2.4.1 System Function Definition
2.4.2 Product Application Scenario
2.4.3 Testing and Debugging
2.4.4 Software and Algorithm
2.4.5 Summary of Intelligence
2.5 Summary of Si3P
2.5.1 History Review of Integration
2.5.2 Associative Metaphor
2.5.3 Prospect Forecast
3 SiP and MicroSystem
3.1 SiP Technology
3.1.1 Definition of SiP Technology
3.1.2 SiP and Related Technologies
3.1.3 SiP or SOP?
3.1.4 Application Fields of SiP Technology
3.1.5 Selection of SiP Process and Materials
3.2 MicroSystem
3.2.1 Natural and Man-Made System
3.2.2 Definition and Features of System
3.2.3 New Definition of MicroSystem
4 From 2D to 4D Integration
4.1 Development of Integration Technology
4.1.1 Scale of Integration
4.1.2 One-Step Integration and Two-Step Integration
4.1.3 Classified Naming for Package Internal Integration
4.2 2D Integration Technology
4.2.1 Definition of 2D Integration
4.2.2 Application of 2D Integration
4.3 2D+ Integration Technology
4.3.1 Definition of 2D+ Integration
4.3.2 Application of 2D+ Integration
4.4 2.5D Integration Technology
4.4.1 Definition of 2.5D Integration
4.4.2 Application of 2.5D Integration
4.5 3D Integration Technology
4.5.1 Definition of 3D Integration
4.5.2 Application of 3D Integration
4.6 4D Integration Technology
4.6.1 Definition of 4D Integration
4.6.2 Application of 4D Integration
4.6.3 The Significance of 4D Integration
4.7 Cavity Integration Technology
4.7.1 Definition of Cavity Integration
4.7.2 Application of Cavity Integration
4.8 Planar Integration Technology
4.8.1 Definition of Planar Integration
4.8.2 Application of Planar Integration
4.9 Summary of Integration Technology
5 SiP and Advanced Packaging Technology
5.1 SiP Substrate and Package
5.1.1 Organic Substrate
5.1.2 Ceramic Substrate
5.1.3 Silicon Substrate
5.2 Advanced Packaging Technology
5.2.1 TSV Technology
5.2.2 RDL Technology
5.2.3 IPD Technology
5.2.4 Chiplet Technology
5.3 Advanced Packaging Technology
5.3.1 Advanced Packaging Based on XY Plane Extension
5.3.2 Advanced Packaging Based on Z-Axis Extension
5.3.3 Summary of Advanced Packaging Technology
5.3.4 Elements: RDL, TSV, Bump and Wafer
5.4 Features and Design Requirements of HDAP
5.4.1 Features of Advanced Packaging (HDAP)
5.4.2 Relationship Between Advanced Packaging and SiP
5.4.3 Advanced Packaging and SiP Design Requirements
References and Notes
References
Notes
Part II Design and Simulation
6 SiP Design and Simulation Platform
6.1 Development of SiP Design Technology
6.2 Two Sets of SiP Design Flow
6.3 General SiP Design Flow
6.3.1 Schematic Design Input
6.3.2 Multi-layout Design Collaboration
6.3.3 Functions of SiP Layout Design
6.4 SiP Design Flow Based on HDAP
6.4.1 XSI-Design Integration and Net Optimization Tool
6.4.2 XPD-HDAP Layout Design Tool
6.5 Which Design Flow is Suitable for Designers?
6.6 SiP Simulation and Verification Flow
6.6.1 Electromagnetic Simulation
6.6.2 Thermal Simulation
6.6.3 Mechanical Simulation
6.6.4 Design Verification
6.7 Advanced Natures of SiP/HDAP Platform
7 Central Library Creation and Management
7.1 Structure of Central Library
7.2 Dashboard Introduction
7.3 Schematic Symbol Creation
7.4 Layout Cell Creation
7.4.1 Bare Chip Cell Creation
7.5 Create Bare Chip Padstack
7.6 Create Bare Chip Cell
7.6.1 SiP Package Cell Creation
7.7 Part Creation and Application
7.7.1 Mapping Part
7.7.2 Create Cell from Part Data
7.8 Central Library Maintenance and Management
7.8.1 Common Settings of Central Library
7.8.2 Import and Export Central Library Data
8 SiP Schematic Design Input
8.1 Netlist Input
8.2 Schematic Design Input
8.2.1 Schematic Tool Introduction
8.2.2 Create Schematic Project
8.2.3 Schematic Basic Operation
8.2.4 Schematic Design Check
8.2.5 Design Package
8.2.6 Output Partlist
8.2.7 Schematic Chinese Menu and Chinese Input
8.3 Schematic Input Based on DataBook
8.3.1 Introduction to DataBook
8.3.2 How to Use DataBook
8.3.3 Verify and Update Component Properties
8.4 File Input and Output
8.4.1 Common Input and Output
8.4.2 Output to Simulation Tool
9 Layout Creation and Setup
9.1 Create Layout Template
9.1.1 Layout Template Definition
9.1.2 Create SiP Layout Template
9.2 Create Layout Project
9.2.1 Create New SiP Project
9.2.2 Enter Layout Design Environment
9.3 Layout Settings and Operations
9.3.1 Layout License Control
9.3.2 Mouse Operation Methods
9.3.3 Four Common Operating Modes
9.3.4 Display Control
9.3.5 Editor Control
9.3.6 Smart Cursor Tips
9.4 Layout Design
9.4.1 Component Placement
9.4.2 View Schematic in Layout
9.5 Package Pin Optimization
9.6 Layout Chinese Input
10 Management of Design Rules
10.1 Constraint Manager
10.2 Scheme
10.2.1 Create Scheme
10.2.2 Apply Scheme in Layout Design
10.3 Net Class
10.3.1 Create Net Class and Assign Nets to Net Class
10.3.2 Define Net Class Rules
10.4 Clearance
10.4.1 Create and Setup Clearance Rules
10.4.2 General Clearance Rule
10.4.3 Net Class to Net Class Clearance Rule
10.5 Constraint Class
10.5.1 Create Constraint Class and Assign Nets
10.5.2 Classification of Electrical Constraints
10.5.3 Edit Constraint Group
10.6 Constraint Manager and Layout Data Interaction
10.6.1 Update Layout Data
10.6.2 Interact with Layout Data
10.7 Rule Setting Instances
10.7.1 Equal Length Setting
10.7.2 Differential Pairs Setting
10.7.3 Z-Axis Clearance Setting
11 Wire Bonding Design in Detail
11.1 Overview of Wire Bonding
11.2 Bond Wire Model
11.2.1 Bond Wire Model Definition
11.2.2 Bond Wire Model Parameters
11.3 Wire Bonding Toolbar and Its Application
11.3.1 Add Bond Wire Manually
11.3.2 Move, Push and Rotate Bond Finger
11.3.3 Generate Bond Wire Automatically
11.3.4 Add Bond Wire Through Guide
11.3.5 Add Power Ring
11.4 Bond Wire Rules Setting
11.4.1 Settings for Component
11.4.2 Settings for Die Pins
11.4.3 Add Multiple Bond Wires Between Die Pin and Bond Finger
11.4.4 Fan Out from Single Die Pin to Multiple Bond Fingers
11.4.5 Bond Multiple Die Pins to One Bond Finger
11.4.6 Die to Die Bonding
11.5 Wire Model Editor and Wire Instance Editor
12 Cavity, Chip Stack and TSV Design
12.1 Cavity Design
12.1.1 Definition of Cavity
12.1.2 Cavity Creation
12.1.3 Place Component into Cavity
12.1.4 Bonding in Cavity
12.1.5 Embedding Chip into Substrate with Cavity
12.1.6 Embedding Chip by Adding Cavity to Die Cell
12.2 Chip Stack Design
12.2.1 The Concept of Chip Stack
12.2.2 Chip Stack Creation
12.2.3 Stack Chips Side by Side
12.2.4 Chip Stack Adjustment and Bonding
12.2.5 Chip and Cavity Combination Design
12.3 Concept and Design of 2.5D TSV
12.4 Concept and Design of 3D TSV
12.4.1 Concept of 3D TSV
12.4.2 3D TSV Cell Creation
12.4.3 Pin Alignment Principle Between Chip Stack
12.4.4 3D TSV Stacking and Interconnection
12.4.5 3D Pin Model Setup
12.4.6 Net Optimization and Route
12.4.7 DRC Check and Complete 3D TSV Design
13 RDL and Flip Chip Design
13.1 Concept and Applications of RDL
13.1.1 Fan-In RDL
13.1.2 Fan-Out RDL
13.2 Concept and Features of Flip Chip
13.3 RDL Design
13.3.1 Build Bare Die and RDL Library
13.3.2 RDL Schematic Design
13.3.3 RDL Layout Design
13.4 Flip Chip Design
13.4.1 Flip Chip Schematic Design
13.4.2 Flip Chip Layout Design
14 Route and Plane
14.1 Route
14.1.1 Route Overview
14.1.2 Manual Route
14.1.3 Semi-auto Route
14.1.4 Auto Route
14.1.5 Differential Pair Route
14.1.6 Length Control Route
14.1.7 Circuit Copy
14.2 Plane
14.2.1 Definition of Plane
14.2.2 Plane Setting
14.2.3 Plane Shape and Plane Data
14.2.4 Generate Outgassing Voids
14.2.5 Verify Plane Data
15 Embedded Passives Design
15.1 Development of Embedded Technology
15.1.1 Discrete Embedded Technology
15.1.2 Planar Embedded Technology
15.2 Process and Materials for Embedded Passive
15.2.1 Embedding Processes
15.2.2 Materials
15.2.3 Nonlinear Characteristics of Resistance Materials
15.3 Automatic Synthesis of Passive Devices
15.3.1 Prepare for Automatic Synthesis
15.3.2 Automatic Synthesis of Resistors
15.3.3 Automatic Synthesis of Capacitor
15.3.4 Synchronization of Layout and Schematic
16 RF Circuit Design
16.1 RF SiP Technology
16.2 RF Design Flow
16.3 Configuration of RF Component Library
16.3.1 Import RF Symbols into Design Central Library
16.3.2 Central Library Partition Search Path Setting
16.4 RF Schematic Design
16.4.1 RF Schematic Toolbar
16.4.2 RF Schematic Input
16.5 RF Parameters Transfer
16.6 RF Layout Design
16.6.1 RF Layout Toolbox
16.6.2 Three Types of RF Unit
16.6.3 Draw and Edit Meander
16.6.4 Create User-Defined RF Units
16.6.5 Via Add Function
16.6.6 Introduction to RF Group
16.6.7 Auto Arrange Function
16.6.8 Connect RF Units with Bond Wire
16.7 Transfer Data with RF Simulation Tools
16.7.1 Connect RF Simulation Tools
16.7.2 Schematic RF Data Transfer
16.7.3 Layout RF Data Transfer
17 Rigid-Flex Circuits and 4D SiP Design
17.1 Introduction to Rigid-Flex Circuits
17.2 Rigid-Flex Circuits Design
17.2.1 Design Flow of Rigid-Flex Circuits
17.2.2 Layer Type Unique to Rigid-Flex Circuits
17.2.3 Rigid-Flex Circuits Design Steps
17.3 Complex Substrate Technology
17.3.1 Definition of Complex Substrate
17.3.2 Application of Complex Substrate
17.4 SiP Design Based on 4D Integration
17.4.1 4D SiP Substrate Definition
17.4.2 4D SiP Design Flow
17.5 Significance of 4D SiP Design
18 Multi-layout Project and Concurrent Design
18.1 Multi-layout Project
18.1.1 Multi-layout Project Design Requirements
18.1.2 Multi-layout Project Design Flow
18.2 Schematic Multi-person Concurrent Design
18.2.1 Schematic Concurrent Design Ideas
18.2.2 Operation Method of Schematic Concurrent Design
18.3 Layout Multi-person Real-Time Concurrent Design
18.3.1 Configuration of Layout Real-Time Concurrent Software
18.3.2 Apply Layout Real-Time Concurrent Design
19 SiP Design Flow Based on Advanced Package (HDAP)
19.1 Advanced Package Design Flow Introduction
19.1.1 Technical Indicators for HDAP Design Environment
19.1.2 HDAP Design Flow
19.1.3 Design Task: HBM (3D + 2.5D)
19.2 XSI Design Environment
19.2.1 Design Data Preparation
19.2.2 Introduction to XSI Working Windows
19.2.3 Create Projects and Design then Add Components
19.3 Add Bare Chip Device
19.3.1 Optimize Net Connection Through XSI
19.3.2 Layout Template Selection
19.3.3 Design Data Transfer
19.4 XPD Design Environment
19.4.1 Interposer Data Synchronization Check
19.4.2 Interposer Layout and Routing
19.4.3 Substrate Data Synchronization Check
19.4.4 Substrate Layout and Routing
19.5 3D Digital Prototype Simulation
19.5.1 The Concept of Digital Prototype
19.5.2 Introduction to 3D View Environment
19.5.3 Build HDAP Digital Prototype Model
20 Design Check and Production Data Output
20.1 Online DRC
20.2 Batch DRC
20.2.1 DRC Settings
20.2.2 Connectivity and Special Rules
20.2.3 Batch DRC Scheme
20.3 Introduction to Hazard Explorer
20.4 Design Library Check
20.5 Production Data Classification
20.6 Gerber and Drill Data Output
20.6.1 Drill Data Output
20.6.2 Gerber Machine Format
20.6.3 Gerber Data Output
20.6.4 Import and Check Gerber Data
20.7 GDS File and Color Map Output
20.7.1 GDS File Output
20.7.2 Color Map Output
20.8 Other Production Data Output
20.8.1 Component and Bond Wire Coordinate Output
20.8.2 DXF File Output
20.8.3 Layout Design Status Output
20.8.4 BOM Output
21 SiP Simulation and Verification
21.1 Overview of SiP Simulation and Verification
21.2 Signal Integrity Simulation
21.2.1 Introduction to HyperLynx SI
21.2.2 Signal Integrity Simulation Example
21.3 Power Integrity Simulation
21.3.1 Introduction to HyperLynx PI
21.3.2 Power Integrity Simulation Example
21.4 Thermal Simulation
21.4.1 Introduction to HyperLynx Thermal
21.4.2 Thermal Simulation Example
21.4.3 Introduction to FloTHERM Software
21.4.4 Introduction to T3Ster
21.5 Advanced 3D Solver
21.5.1 Introduction to HyperLynx Full-Wave Solver
21.5.2 Introduction to HyperLynx Fast 3D Solver
21.6 Simulation of Digital-Analog Mixed Circuit
21.7 Electrical Rules Verification
21.7.1 Introduction to HyperLynx DRC
21.7.2 Examples of Electrical Verification
21.8 HDAP Physical Verification
21.8.1 Introduction to Calibre 3DSTACK
21.8.2 HDAP Physical Verification Example
References and Notes
References
Notes
Part III Projects and Cases
22 Mass Storage Chip Design Case
22.1 Application of Mass Storage Chip in Space
22.2 Feasibility Analysis of SiP Application
22.2.1 Bare Chip Selection
22.2.2 Selection of Design and Simulation Tools
22.2.3 Selection of Manufacturing and Testing Factory
22.3 Design of Mass Storage Chip
22.3.1 Scheme Design
22.3.2 Detailed Design
22.4 Packaging and Testing of Mass Storage Chip
22.4.1 Packaging
22.4.2 Machine Test
22.4.3 System Test
22.4.4 Follow-Up Testing and Cost Ratio
22.5 Comparison of Technical Parameters
23 SiP Project Planning and Design Case
23.1 SiP Project Planning
23.1.1 Characteristics and Applicability of SiP
23.1.2 Factors That Need to Be Identified for SiP Projects
23.2 Design Rule Import
23.2.1 Project Requirements and Scheme Analysis
23.2.2 Implementation Scheme of SiP
23.3 The Design of SiP Products
23.3.1 Symbol and Cell Library Creation
23.3.2 Schematic Design
23.3.3 Layout Design
23.3.4 Product Packaging and Testing
24 2.5D TSV Technology and Design Case
24.1 2.5D Integration Requirement
24.2 Comparison of Traditional Packaging with 2.5D
24.2.1 Flip Chip Process
24.2.2 Wire Bonding Process
24.2.3 Advantage and Disadvantage of Traditional Package and 2.5D
24.3 2.5D TSV Interposer Design
24.3.1 2.5D TSV Interposer Package Structure
24.3.2 2.5D Interposer Package Design
24.4 Process Comparison of Interposer and Organic Substrates
24.4.1 Si Interposer
24.4.2 Glass Interposer
24.4.3 Organic Substrate
24.4.4 Process Capability Comparison
24.5 Mask Porcess Introduction
24.6 2.5D Interposer Design, Simulation and Manfacture
24.6.1 Package Structure Design
24.6.2 Package Layout, Signal and Structure Simulation
24.6.3 Production Data Tape Out and Mask Preparation
24.6.4 Interposer Manufacture and Assembly
25 Digital T/R Module SiP Design Case
25.1 Introduction to Radar System
25.2 SiP Technology Adoption
25.3 Design of Digital T/R Module
25.3.1 Function Introduction of Digital T/R Module
25.3.2 Structure and Principle Design of Digital T/R
25.3.3 Digital T/R Module SiP Layout Design
25.4 Metal Shell and Integrated Packaging Design
26 MEMS Verification SiP Design Case
26.1 Project Introduction
26.2 SiP Scheme Design
26.3 SiP Circuit Design
26.3.1 Library Build and Schematic Design
26.3.2 SiP Layout Design
26.4 Assembly and Testing Board
27 Rigid-Flex SiP Design Case
27.1 Introduction of Rigid-Flex Substrate
27.2 RF Front-End Architecture and RF SiP Scheme
27.2.1 System Architecture of Micro Base Station RF Front-End
27.2.2 RF SiP Package Design
27.2.3 RF SiP Substrate Stack-Up Design
27.3 Electrical Simulation of the Rigid-Flex Substrate
27.3.1 Design and Simulation of Signal Transmission
27.3.2 Design and Simulation of Power Distribution Network
27.4 Thermal Management Evaluation of RF SiP
27.4.1 Thermal Resistance Analysis of the Package Structure
27.4.2 Thermal Management Simulation of RF SiP
27.5 Assembly Flow of RF SiP
28 RF System Integrated SiP Design Case
28.1 RF System Integration Technology
28.1.1 RF System Introduction
28.1.2 Miniaturization Trend for RF System Integration
28.1.3 RF SiP Versus RF SoC
28.2 Design and Simulation of RF SiP
28.2.1 RF SiP Structure Design
28.2.2 RF SiP Electrical Design and Simulation
28.2.3 Thermal Management of RF SiP
28.3 Assembly and Test of RF SiP
28.3.1 Assembly of RF SiP
28.3.2 RF SiP Testing
29 PoP RF SiP Design Case
29.1 Introduction to PoP Technology
29.2 RF System Architecture and Indicators
29.3 RF SiP Structure and Substrate Design
29.3.1 Structure Design
29.3.2 Substrate Design
29.4 Signal Integrity and Power Integrity Simulation
29.4.1 Signal Integrity (SI) Simulation
29.4.2 Power Integrity (PI) Simulation
29.5 Thermal Design Simulation
29.6 Assembly and Testing
30 SiP Production Data Processing Case
30.1 LTCC, Thick Film and Heterogeneous Integration
30.1.1 LTCC Technology
30.1.2 Thick Film Technology
30.1.3 Heterogeneous Integration Technologies
30.2 Gerber and Drill Data Generation
30.2.1 Gerber Data Generation and Checking
30.2.2 Drill Data Generation and Comparison
30.3 Layout Panel Generation
30.4 Multiple Masks Generation
30.4.1 Mask Generator
30.4.2 Examples of Mask Generation
References
References
Postscript and Thanks
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Suny Li Editor
MicroSystem Based on SiP Technology
MicroSystem Based on SiP Technology
Suny Li Editor
MicroSystem Based on SiP Technology
Editor Suny Li Beijing, China
ISBN 978-981-19-0082-2 ISBN 978-981-19-0083-9 (eBook) https://doi.org/10.1007/978-981-19-0083-9 Jointly published with Publishing House of Electronics Industry, Beijing, China The print edition is not for sale in China (Mainland). Customers from China (Mainland) please order the print book from: Publishing House of Electronics Industry. © Publishing House of Electronics Industry 2022 This work is subject to copyright. All rights are solely and exclusively licensed by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. The publishers, the authors, and the editors are safe to assume that the advice and information in this book are believed to be true and accurate at the date of publication. Neither the publishers nor the authors or the editors give a warranty, express or implied, with respect to the material contained herein or for any errors or omissions that may have been made. The publishers remain neutral with regard to jurisdictional claims in published maps and institutional affiliations. This Springer imprint is published by the registered company Springer Nature Singapore Pte Ltd. The registered company address is: 152 Beach Road, #21-01/04 Gateway East, Singapore 189721, Singapore
Preface
The integration of electronic system is mainly divided into three levels: integration on chip, integration in package and integration on PCB board level. In 1958, Jack Kilby invented the first integrated circuit on the earth, which contained five components. From then on, the integration on chip start. Sixty years later, more than 100 million transistors can be integrated on a square millimeter area of chip and the number of transistors on a single chip has reached 10 billion magnitudes. As the transistor feature size progresses toward 1 nm, the integration on chip becomes difficult to continue and Moore’s Law will end. In 1936, Paul Eisler invented the world’s first PCB, the main purpose of which is also for integration. Today, the routing density and assembly density on PCB gradually tend to the limit, which has not been significantly improved for many years. Moreover, due to the influence of chip package size, it is difficult to continue to improve the density of device assembly on PCB. In 1947, the first electronic package appeared. Unlike IC and PCB, package did not have the concept of integration at first. Its main purpose is chip protection, scale amplification and electrical interconnection, almost all packages are single-chip packages then. Until more than 40 years later that the concept of integration began to appear in package in the 1980s, among which MCM (multi-chip module) is the most representative. With the expansion of integration scale in package, the enhancement of function and the application of 3D integration technology, the concept of SiP (system in package) technology appears and is gradually accepted and widely used by people. The important index of the advanced nature of modern electronic products is to integrate more functions in smaller space, that is, having higher function density. Today, the integration on chip and on PCB is unsustainable due to technical reasons, but the integration in package has broad space and flexible implementation methods. This is the main reason why SiP and advanced packaging technology have attracted much attention in recent years. SiP is not only a package but also a system, which requires a more systematic understanding of SiP. The system scale implemented in SiP is relatively small, so we can call it a MicroSystem, which is the book’s name comes from. v
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Preface
The author has been engaged in the research of SiP technology, R&D and technical support of SiP projects for about 15 years, and has participated in dozens of SiP products in China. In the process of taking part in these projects, the author understands that more and more technicians are urgently in need of SiP design, simulation and validation. Designers want their SiP project to be successful, so a comprehensive guide book for SiP technology is urgently needed. That’s why we wrote this book. The book is divided into three major parts: Concept and Technology, Design and Simulation, Project and Case, with a total of 30 chapters. The Part I and the Part II are all written by Suny Li (Li, Yang). The Part III is written by different authors. All manuscripts of this book are finally reviewed and finalized by Suny Li.
Part I Concept and Technology In view of the development of SiP and advanced packaging technology, as well as the author’s years of experience, brand new ideas and original concepts are put forward for SiP and related technologies, which cover the introduction of SiP and the latest advanced packaging technology, including five chapters. • Chapter 1: From Moore’s Law to Function Density Law. The author puts forward for a new original concept: Function Density Law, and elaborates the hierarchical division of electronic systems. • Chapter 2: From SiP to Si3 P. Based on comprehensive understanding of the concept of SiP, the author proposes a new concept and thinking: Si3 P, and explain Si3 P in detail. • Chapter 3: SiP Technology and MicroSystem. Describes the relationship between SiP and MicroSystem, and the impact of SiP on the concept development of MicroSystem. • Chapter 4: From 2D to 4D Integration. Introduces the concept and evolution of electronic integration technologies, covers a variety of integrations (5 + 2), defines and classifies them. • Chapter 5: SiP and Advanced Packaging Technology. Describes SiP-related substrate technology and integration technology, and introduces the most popular types of advanced packaging technology today.
Part II Design and Simulation Based on latest EDA software platform, Part II describes the design, simulation and verification methods for SiP and HDAP, including the design of Wire Bonding, Cavity, Chip Stack, 2.5D TSV, 3D TSV, RDL, Fan-In, Fan-Out, Flip Chip, Discrete
Preface
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Embedded Technology, Planar Embedded passive, RF, Rigid-Flex, 4D SiP, multilayout project and multi-person concurrent design, as well as various simulation methods for SiP and HDAP, electrical and physical verification, including 16 chapters. The specific contents of each chapter are as follows: • Chapter 6: SiP Design, Simulation and Verification Platform. Introduces the general SiP design flow, SiP design flow based on advanced packaging and SiP simulation and verification flow. • Chapter 7: Central Library Creation and Management. Introduces the creation methods of Symbols, Cell and Part, as well as the maintenance and management of the central library. • Chapter 8: SiP Schematic Design Input. Introduces SiP schematic design, review and data input and output. • Chapter 9: Layout Creation and Setup. Introduces various types SiP layout creation, including organic substrate, ceramic substrate, silicon substrate, layout design environment settings and operations, as well as component placement and net optimization methods in layout. • Chapter 10: Management of Design Rules. Introduces the design rules management in SiP project and the typical design rules setting. • Chapter 11: Wire Bonding Design in Detail. Introduces Bond Wire model definition, parameter settings and detailed Wire Bonding design methods and techniques. • Chapter 12: Cavity, Chip Stacking and TSV design. Introduces the concept, definition and design methods of Cavity and Die Stack, as well as the concept and detailed design methods of 2.5D TSV and 3D TSV. • Chapter 13: RDL and Flip Chip design. Introduces the concept and application of RDL, Fan-In and Fan-Out and the design methods of RDL and Flip Chip. • Chapter 14: Route and Plane. Introduces various operations and applications of SiP layout route and plane. • Chapter 15: Embedded Passive Design. Introduces the process, materials and design methods of Embedded Passive Device. • Chapter 16: RF Circuit Design. Introduces RF SiP technology and design process, RF schematic and layout design methods, RF simulation tools link. • Chapter 17: Rigid-Flex Circuits and 4D SiP design. Introduces the concept and design method of Rigid-Flex circuit and 4D SiP design based on complex rigidflexible substrate. • Chapter 18: Multi-Layout Project and Concurrent Design. Introduces the concept and design method of Multi-Layout Project, multi-person concurrent design technology and the implementation method of schematic and layout concurrent design. • Chapter 19: SiP Design Flow Based on Advanced Packaging (HDAP). Introduces the detailed design process of High-Density Advanced Packaging (HDAP) and the application of the latest 3D digital prototype in HDAP design.
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Preface
• Chapter 20: Design Check and Production Data Output. Introduces DRC design rules inspection method after design completion and the output of various production data. • Chapter 21: SiP Simulation and Verification. Introduces various common simulation and verification technologies used in SiP and HDAP.
Part III Project and Case Based on the actual SiP projects and product cases, Part III introduces the design, simulation, and implementation methods of different types of SiP. It has an important reference significance for the development of SiP projects, including nine chapters. • Chapter 22: Mass Storage Chip Design Case. Introduces the research and development process of a mass storage chip based on SiP technology, from scheme, detailed design to production, testing and application, the author are Suny Li (Li, Yang) and Junshe An. • Chapter 23: SiP Project Planning and Design Case. Introduces the planning of SiP Project, the import of design rules, and two actual project cases, the author are Tianrui Zhu and Xiaohong Wang. • Chapter 24: 2.5D TSV Technology and Design Cases. Introduces the characteristics, process flow, design methods and actual case of 2.5D TSV technology, the author is Jian Xu. • Chapter 25: Digital T/R Module SiP Design Case. Introduces the features, functions, schematic and layout design, structural integration and implementation of digital T/R module, the author are Mengjian Bao, Pei Li and Wenbin Lu. • Chapter 26: MEMS Verification SiP Design Case. Introduces the design scheme, schematic and layout design, assembly and testing of a SiP applied to the MEMS Verification technology. The author is Boyuan Zhou. • Chapter 27: Rigid-Flex SiP Design Case. Introduces the principle, design scheme, electrical simulation, thermal simulation and process assembly of a RF SiP based on Rigid-Flex substrate, the author are Liqiang Cao, Peng Wu, Fengman Liu and Huimin He. • Chapter 28: RF System Integrated SiP Design Case. Introduces RF system integration technology, RF SiP design and Simulation, assembly and test, the author are Liqiang Cao and Gengxin Tian. • Chapter 29: PoP RF SiP Design Case. Introduces a RF SiP design based on PoP technology, the RF SiP SI/PI simulation, thermal simulation, assembly and test. The author are Liqiang Cao and Yi He. • Chapter 30: SiP Production Data Processing Case. Introduces the processing technologies of LTCC and thick-film substrate in SiP project, including production data generation, panel generation, mask generation and data optimization. The author is He Hanbo.
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The 30 chapters of the 3 parts in this book basically cover most of the situations and problems that may be encountered in SiP projects and products development. Through original concepts, hot spot technologies and actual project cases, this book provides a comprehensive and in-depth description of the entire SiP process from conception to final implementation, and benefits the readers. We are committed to writing this book as a comprehensive technical guide for SiP and MicroSystem design. Although we do our best to achieve perfection, due to limitations in the level and knowledge of authors, faults and errors will inevitably occur in this book. Experts and readers are encouraged to give corrections so that the faults and errors can be corrected in subsequent versions. I hope that the publication of this book will play a certain role in promoting the development of SiP, Advanced Packaging and MicroSystem technology.
Beijing, China December 2021
Suny Li
Brief Introduction of the New Book
This book is divided into three parts: Concept and Technology, Design and Simulation, Project and Case, total of 30 chapters. In Part I, the author puts forward some new original concepts and thoughts such as Function Density Law, Si3 P and 4D integration. Part I also covers the latest technology of SiP and Advanced Packaging. It contains five chapters. Part II covers the latest SiP and Advanced Packaging design, simulation and verification based on the latest EDA software platform. Such as wire bonding, multi-step cavity, chip stack, 2.5D TSV, 3D TSV, RDL, Fan-In, Fan-Out, Flip Chip, Embedded Passive, Embedded Chip, RF design, Rigid-Flex design, 4D SiP design, Multilayout project and concurrent team design, as well as SI, PI, and thermal simulation, electrical verification and physical verification. Includes 16 chapters. Part III introduces the design, simulation and implementation methods of different types of SiP based on real design case, which has an import reference significance for the research and development of SiP projects. Includes nine chapters. This book is suitable for SiP designer, advanced packaging designer, subject leaders interested in SiP and advanced packaging, as well as those people seeking system miniaturization, low power consumption and high performance.
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Contents
Part I
Concept and Technology
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From Moore’s Law to Function Density Law . . . . . . . . . . . . . . . . . . . . . Suny Li
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2
From SiP to Si3 P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Suny Li
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SiP and MicroSystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Suny Li
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From 2D to 4D Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Suny Li
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SiP and Advanced Packaging Technology . . . . . . . . . . . . . . . . . . . . . . . . 117 Suny Li
References and Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Part II
Design and Simulation
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SiP Design and Simulation Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Suny Li
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Central Library Creation and Management . . . . . . . . . . . . . . . . . . . . . 185 Suny Li
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SiP Schematic Design Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 Suny Li
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Layout Creation and Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 Suny Li
10 Management of Design Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 Suny Li
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11 Wire Bonding Design in Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 Suny Li 12 Cavity, Chip Stack and TSV Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 Suny Li 13 RDL and Flip Chip Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399 Suny Li 14 Route and Plane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 Suny Li 15 Embedded Passives Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457 Suny Li 16 RF Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491 Suny Li 17 Rigid-Flex Circuits and 4D SiP Design . . . . . . . . . . . . . . . . . . . . . . . . . . 523 Suny Li 18 Multi-layout Project and Concurrent Design . . . . . . . . . . . . . . . . . . . . . 547 Suny Li 19 SiP Design Flow Based on Advanced Package (HDAP) . . . . . . . . . . . . 567 Suny Li 20 Design Check and Production Data Output . . . . . . . . . . . . . . . . . . . . . . 603 Suny Li 21 SiP Simulation and Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635 Suny Li References and Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685 Part III Projects and Cases 22 Mass Storage Chip Design Case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689 Suny Li and Junshe An 23 SiP Project Planning and Design Case . . . . . . . . . . . . . . . . . . . . . . . . . . . 715 Tianrui Zhu and Xiaohong Wang 24 2.5D TSV Technology and Design Case . . . . . . . . . . . . . . . . . . . . . . . . . . 737 Jian Xu 25 Digital T/R Module SiP Design Case . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759 Mengjian Bao, Pei Li, and Wenbin Lu 26 MEMS Verification SiP Design Case . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773 Boyuan Zhou
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27 Rigid-Flex SiP Design Case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785 Liqiang Cao, Peng Wu, Fengman Liu, and Huimin He 28 RF System Integrated SiP Design Case . . . . . . . . . . . . . . . . . . . . . . . . . . 811 Liqiang Cao and Gengxin Tian 29 PoP RF SiP Design Case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 831 Liqiang Cao and Yi He 30 SiP Production Data Processing Case . . . . . . . . . . . . . . . . . . . . . . . . . . . 849 Hanbo He References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 869 Postscript and Thanks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 873
About the Author
Mr. Suny Li (Li, Yang) is a SiP Technical Specialist in China, he has 22 years of working experience of SiP and related technology. He has participated and guided more than 40 SiP projects in China. At present, he has published three technical books of SiP. • “SiP Design and Simulation: Mentor Expedition Enterprise Flow Advanced Design guide” PHEI, 2012.5 • “SiP System-in-Package Design and Simulation”, English Version, WILEY, 2017.7 • “Micro Systems Based on SiP Technology”, PHEI, 2021.5. He has worked in NSSC (National Space Science Center) of the CAS (Chinese Academy of Sciences), and participated in the ShenZhou series of Manned Space Flight Program and the DSP (Double Star Exploration Program), an ESA and NSSC cooperative space science project. Then, he joined SIEMENS China. In 2007, He joined AcconSys. He is a senior member of IEEE, senior member of Chinese Institute of Electronics and senior member of China Graphics society. He has obtained more than 10 national patents and published more than 10 papers. He graduated from BEIHANG University with master’s degree in Aerospace Science and technology.
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About the Author
At present, he acts as a Technical Specialist, responsible for SiP and MicroSystem product development, as well as EDA software technical support related to SiP and IC packaging design. He owns WeChat public account: SiPTechnology, and has published more than 50 original technical articles.
Part I
Concept and Technology
Chapter 1
From Moore’s Law to Function Density Law Suny Li
1.1 Moore’s Law As we all know, the Feature size of IC chip manufacturing process has reached 5 nm. With the Feature size of IC manufacturing technology moving towards 3 nm or even 1 nm, Moore’s law has come to end. The period after the end of Moore’s Law is called the post-Moore’s Law era. So, is there any law that can replace Moore’s law? In this chapter, we propose a new law what’s named Function Density Law, Referred to as FD Law. The author believes that Function Density Law will be a universal law in the era of post-Moore’s law. First of all, let’s understand Moore’s law and analyze the problems faced by Moore’s law from two aspects. Moore’s law was proposed by Gordon Moore, one of the founders of Intel, in 1965 and has been 56 years since then. Moore’s Law: when the price remains unchanged, the numbers of components that can be accommodated on integrated circuit will double every 18–24 months, and the performance will also be doubled. In other words, computer performance for every dollar will be four times of the original every 18–24 months. Generally speaking, Moore’s law has the following three statements: (1) (2) (3)
The number of components on an integrated circuit chip doubles every 18– 24 months. The performance of microprocessors will be increased doubly every 18– 24 months, while the price will be declined doubly. Computer performance for each dollar will be doubled every 18–24 months.
Among the above three statements, the first one is the most common. The second and the third are related to the price factor, and their essence is the same. Each of the S. Li (B) Beijing, China e-mail: [email protected] © Publishing House of Electronics Industry 2022 S. Li (ed.), MicroSystem Based on SiP Technology, https://doi.org/10.1007/978-981-19-0083-9_1
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three statements has its own merits. But they are in common, that is, the period of “doubling” cycle is 18–24 months. As for doubling (or quadrupling) the “number of components on an integrated circuit chip”, whether the “computer performance” as a whole, or “the performance that can be bought by one US dollar”, different people have different opinions. Moore’s law reveals the speed of information technology progress. Although this trend has lasted for more than half a century, Moore’s law has always been regarded as an observation or speculation rather than a physical or natural law. Is Moore’s law accurate? Let’s first look at Fig. 1.1. From the figure, we can see that the sampling points in reality are basically located near the curve, which shows that Moore’s law is basically accurate. Figure 1.1 shows the growth curve of Moore’s law, because the vertical axis uses logarithmic coordinates, which is actually an exponential curve. Moore’s law is not a law of mathematics or physics, but a prediction of the development trend of integrated circuit technology. Therefore, both literal expression and quantitative calculation should allow a certain margin. In this sense, Moore’s prediction is quite accurate, so it is recognized by the industry and has a huge repercussion. It has been 56 years since Moore’s law came into being. We know that the geometric size of components on a chip cannot be reduced without limit, which means that one day, the number of transistors that can be integrated per unit area of a chip will reach the limit. From a technical point of view, with the increase of the density of circuits on silicon, the complexity and error rate will also increase exponentially. At the same time, comprehensive and thorough chip testing is almost impossible to complete. Once the Feature size of the chip reaches 1 nm, it is equivalent to the size of only several silicon atoms. In this case, the physical and chemical properties of the
Fig. 1.1 Moore’s law
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material will change in quality, resulting in the failure of semiconductor devices using the current technology, and Moore’s law will come to its end.
1.2 Two Problems Facing Moore’s Law When Gordon Moore first proposed Moore’s law in 1965, it was that the number of transistors integrated on semiconductor chips would double every year. Ten years later, he revised Moore’s law according to the actual situation at that time, changing “doubling every year” to “doubling every 18 to 24 months”. In 1975, Moore presented a paper at the IEEE International Conference on electronic devices. According to the actual situation at that time, Moore’s law was revised, changing “doubling every year” to “doubling every two years”, and the popular saying was “doubling every 18–24 months”. More than 56 years have passed since the development of Moore’s law. In these years, some people haven’t optimistic, and some even put forward the view that “Moore’s law is dead”. In this chapter, we look at the reasons for the end of Moore’s law from two aspects: one is from the Micro-view, and the other is from the Macro-view. We can call them two problems faced by Moore’s law.
1.2.1 Reduction of Micro-Scale Chipmakers have used various means to keep up with Moore’s law, such as adding more cores, driving threads inside chips, and using accelerators. However, we cannot avoid the fact that the doubling effect of Moore’s law has begun to slow down. At present, the Feature size of the latest process is only 5 nm, while the lattice constant of silicon atom is 0.54 nm (the diameter of silicon atom is 0.117 nm). That is to say, the Feature size of transistors in 5 nm process can only place 10 silicon atoms side by side. With the further reduction of Feature size, the number will be further reduced. In the same area, with the integration of more and more transistor circuits, it is difficult to solve the problems such as the increase of leakage current, the problem of heat dissipation and the slow growth of clock frequency. 1.
Definition of Feature Size
First, let’s look at the microstructure of transistors, Fig. 1.2 shows the structure of the most popular FinFET transistor on the left, and the FinFET transistor under electron microscope on the right. It is generally believed that in CMOS technology, Feature size refers to the gate width, that is, the channel length of MOS devices. At present, in the most advanced chip manufacturing process, the Feature size of transistor is 5 nm.
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Fig. 1.2 Definition and microstructure of transistor Feature size
From Fig. 1.2, we can see that the Feature size is not the minimum size in the transistor, and the fin width is at least smaller than the Feature size. Therefore, according to the standard definition, the minimum size required to be manufactured in a transistor with a Feature size of 5 nm is actually less than 5 nm. In addition, there is a saying that when transistors are transformed from planar FET to FinFET, the Feature size is no longer measured by gate width, but by the smallest size in semiconductor devices. At this time, we need to find the minimum size in transistors. In fact, different semiconductor manufacturers have different definitions of Feature size. For example, Intel and TSMC have different definitions. It is generally believed that planar transistor planar FET can be used when the Feature size is more than 22 nm. When the Feature size is below 22 nm, FinFET should be used. When it reaches 3 nm, stacked nanosheet FET should be used. Figure 1.3 shows the microstructure comparison of Planar FET, FinFET and Stacked nanosheet FET. When the Feature size is reduced to 3 nm, stacked nanosheet FET structure is needed. According to standard definition, Feature size is equal to Gate Width. From Fig. 1.3, we can see that the minimum size (such as the thickness of the nanosheets)
Fig. 1.3 Microstructure comparison of three kinds of transistors
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in transistors with a Feature size of 3 nm is less than 3 nm, or even less than 1 nm. This estimation assumes that the scale relationship between Fig. 1.3 and the real objects is correct. Of course, such estimation is not strict, and it needs to be confirmed by the real stacked nanosheets transistors. In addition, according to another view, the Feature size refers to the minimum size in semiconductor devices. For example, when the thickness of nanosheets is less than the Gate Width, the thickness of nanosheets can be called Feature size. But in any case, there is always a limit to the reduction of scale. 2.
Physical Structure of Silicon Atoms
Next, let’s look at the physical structure of silicon atoms. The unit cell structure of silicon is shown on the left side of Fig. 1.4, which is the smallest unit of silicon crystal. In the unit cell of a face centered cube composed of silicon atoms, there are one silicon atom in each of the eight vertices and six faces, and there are four silicon atoms, which are located at 1/4 of the four spatial diagonal lines respectively. The average number of atoms in each silicon cell is 8 (8 × 1/8 + 6 × 1/2 + 4 = 8). The cell side length of silicon is a (lattice constant). At 300 K, a = 5.4305 Å (0.543 nm). 1 nm is equivalent to less than 2a, which means that both unit cells cannot be placed in the width of 1 nm. The space utilization rate of silicon atom = the volume of silicon atom/the volume occupied by atom in the unit cell. The space utilization rate of silicon is about 34%, that is, 1/3 of the unit cell space is atoms and 2/3 is the gap, as shown on the right side of Fig. 1.4. In other words, the silicon we see is no longer smooth and continuous, but composed of discrete atomic clusters. At this time, many laws and rules applicable in continuous system will fail, and the transistor will not work normally. Therefore, from the Micro-view, Moore’s law is unsustainable.
Fig. 1.4 Unit cell structure of silicon and space utilization rate of silicon atoms
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1.2.2 Consumption of Macro-Resources The problem of silicon consumption has not been discussed before, because it is generally believed that silicon on earth is inexhaustible. But that’s not the case if we calculate the increasing consumption according to Moore’s law. Here we give a conclusion first: all the exponential growth curves are not sustainable in the physical sense. And Moore’s law is exactly an exponential curve, so Moore’s law is not sustainable also. In the process of demonstrating whether Moore’s law is sustainable or not, we need to answer the following questions. 1.
How Many Silicon Atoms Are There on Earth?
Silicon is a very common element, widely exists in rocks, gravel and dust. In Earth’s crust, silicon is the second most abundant element, accounting for 26.4% of the total mass of Earth’s crust, second only to oxygen (49.4%). Sitting on the beach, looking at the boundless sea, and holding up a handful of sand in both hands, then let the sand slide slowly between fingers, we may think that the sand should be inexhaustible. Then let’s just figure out how many silicon atoms are there on Earth? First of all, we know the total mass of Earth: 5.965 × 1024 kg. The crust accounts for about 0.42% of the total mass of Earth, and silicon accounts for 26.4% of the total mass of Earth’s crust. Therefore, we can get the total mass of silicon on Earth: 5.965 × 1024 × 0.42% × 26.4% = 6.614 × 1021 kg. This is about one thousandth of the total mass of Earth. Secondly, we know that the mass of silicon atom is equal to the atomic weight of silicon times the mass of hydrogen atom. 28 × 1.674 × 10−27 kg = 4.687 × 10−26 kg. So we can get the number of silicon atoms by dividing the total mass of silicon on earth by the mass of silicon atoms. 6.614 × 1021 ÷ 4.687 × 10–26 = 1.41 × 1047 . So, the total number of silicon atoms on earth is 1.41 × 1047 . 2.
How Many Silicon Atoms Do We Need to Make a Transistor?
Transistors are different in size, so the number of silicon atoms consumed varies greatly. We need to select a typical transistor for macro estimation. First of all, we need to know the volume of transistors. People often say 7 nm, 5 nm and 3 nm refer to the Feature size of transistors. The Feature size is the smallest size in the transistor, which usually refers to the Gate Width in CMOS process. However, the volume or side length of the transistor is naturally much larger than the Feature size. What should it be? We take Huawei Kirin 990 5G chip as an example. Kirin 990 5G chip is a new generation mobile phone processor developed by Huawei. It is manufactured by TSMC 7 nm FinFET plus EUV process. It integrates 10.3 billion transistors and covers an area of 113.3 mm2 .
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Table 1.1 Technical parameters of Kirin series chips Kirin 990 5G
Kirin 990
Kirin 980
Kirin 970
Feature size
7 nm + EUV
7 nm
7 nm
10 nm
Transistor number
10.3 billion
~ 8.0 billion
6.9 billion
5.5 billion
Die size
113.3 mm2
~ 90 mm2
75.6 mm2
96.7 mm2
From Table 1.1, we can see the Kirin 990 5G parameters. By dividing the number of transistors by the chip area, we get 91 million transistors per square millimeter. (10.3 × 109) ÷ (113.3 mm2 ) = 91 × 106 /mm2 . By dividing the chip size by the number of transistors, we can get the size of the transistor. (113.3 square mm) ÷ (10.3 × 109) = 1.1 × 10–8 mm2 . 1.1 × 10–8 mm2 = 1.1 × 104 nm2 Therefore, for Kirin 990 5G, one transistor area is about 11,000 nm2 . In Table 1.1, we can obtain almost the same transistor area for other 7 nm Feature size chips. We assume that the height of the transistor is about 100 nm, so the volume of the transistor is 1.1 × 106 nm3 . We know that the density of silicon is 2328.3 kg/m3 , and the mass of silicon atom is 28 × 1.674 × 10–27 kg , so we can get the number of silicon atoms in 1 nm3 . 2328.3 × 10–27 ÷ (28 × 1.674 × 10–27 ) = 49.7 ≈ 50. Therefore, the number of silicon atoms in a transistor should be 50 × 1.1 ×106 = 55 million. So is it possible to calculate how many transistors silicon on earth can produce? We also need to understand the structure of silicon wafers, as shown in Fig. 1.5 below. As can be seen in Fig. 1.5, although the height of the transistor itself is about 100 nm, and the thickness of the active layer of the silicon chip is less than 10 µm, the silicon body supported by the transistor is about 1 mm. How can we get it? First of all, the thickness of silicon wafer is generally 800 µm, the cutting loss of silicon wafer is about 200 µm, then 800 + 200 = 1000 µm = 1 mm.
Fig. 1.5 Silicon wafer structure
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Therefore, the number of silicon atoms consumed by a transistor manufacture is 50 × 110 nm (length) × 100 nm (width) × 106 nm (wafer thickness) = 5.5 × 1011 = 550 billion. It can be concluded that each transistor produced by TSMC 7 nm technology consumes not 55 million silicon atoms, but 550 billion silicon atoms. So we can equate transistors with the corresponding silicon atoms: one transistor = 550 billion silicon atoms. 3.
How Many Transistors Can Be Produced by Silicon on Earth?
According to TSMC 7 nm FinFET + EUV process, the number of transistors produced by silicon on earth is: the number of silicon atoms on earth divided by the number of silicon atoms consumed by each transistor, as follows: (1.41 × 1047 ) ÷ (5.5 × 1011 ) = 2.56 × 1035 . With that answer, is that the end of the question? No, it’s just the beginning. 4.
How Many Chips Can Be Made from Silicon on Earth?
As mentioned above, the Kirin 990 5G processor contains about 10.3 billion transistors with an area of about 113.3 square millimeters. In fact, silicon consumption is not related to the number of transistors, but to the area of the silicon chip. Due to different process parameters, the size of the transistor and the number of silicon atoms consumed by each transistor are also different. When the wafer thickness remains unchanged, the area of the chip is directly related to the number of silicon atoms. Previously, we deduced that the number of atom in 1 nm3 silicon material is 50, so the atom number in 1 mm3 silicon is 50 × 1018 , which is equivalent to the wafer with thickness of 1 mm, and contains 50 × 1018 silicon atoms per 1mm2 . For a 100 mm2 chip (slightly smaller than 113.3 square millimeter of Kirin 990 5G processor), the number of silicon atoms consumed by a chip is 100 × 50 × 1018 , that is, 5 × 1021 silicon atoms. For example with such kind of chips, the total number of chips that can be designed and manufactured on Earth is: 1.41 × 1047 ÷ (5 × 1021 ) = 2.82 × 1025 . 5.
How Long Can Silicon on Earth Last?
This is what we really need to pay attention to! In 2019, a total of 20.182 billion chips have been produced in China, accounting for 10% of the global chip production. According to this estimate, the global chip production in 2019 will be 201.82 billion chips, about 2 × 1012 chips. The area of common chip is more than or less than 100 square millimeter. If we take 100 square millimeter as the median of the chip and estimate it in turn, the number of silicon atoms needed to produce the chip per year is (2 × 1012 ) × (5 × 1021 ) = 1034 . If we assume that the annual production of chips remains the same, then what is the available time of silicon on Earth:
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1.41 × 1047 ÷ 1034 = 1.41 × 1013 years, or 14.1 trillion years, which is a very long time. It seems that we don’t have to worry. The life span of Earth is not necessarily that long. However, the reality is that the demand and production of chips will continue to increase every year. In 2019, the global chip output value is 437.6 billion US dollars, and the output is about 2 × 1012 (2018.2 billion chips). Here, we assume that the global output value of chips is basically unchanged, but the price of chips will become cheaper and cheaper. The number of chips purchased by one dollar will double every 9–12 months. We can get the following formula: 2 × 1012 × (1 + 2 + 22 + 23 + … + 2n) = 2.82 × 1025 . “n” in the formula represents the number of years on earth that silicon chips can be produced from 2019. (1 + 2 + 22 + 23 + … + 2n ) = 1.41 × 1013 . [2(n + 1) −1] = 1.41 × 1013 . 2n = 7.05 × 1012 . n = 42.68 < 43. That is to say, if the number of chips in the same dollar doubles every 9–12 months, from now on, in 43 cycles, we will run out of silicon atoms on Earth. Is that possible? There must be something wrong with our hypothesis. At this time, we heard a saying: “a dollar can buy computer performance, every 18–24 months quadruple.“ This is what Moore’s law says. Quadrupling every 18–24 months and doubling every 9–12 months should be the same thing. Even if the performance of a computer is not exactly equal to the number of chips or transistors, there is a strong correlation. Will silicon on Earth last 14 trillion years or 43 years? Moreover, we only consider the application of silicon in chip manufacturing, that is, silicon is only used to make high-purity silicon semiconductors. In fact, in addition, silicon is widely used in high temperature resistant materials, optical fiber communication materials, silicone compounds, alloys, etc. silicon is also widely used in aerospace, transportation, energy, chemical industry, textile, food, light industry, medical treatment, agriculture and other industries. In addition, we haven’t considered other applications, such as road building, bridge building, house building, etc., where silicon compounds such as stone and sand are widely used. 6.
Why is Moore’s Law not Sustainable?
Moore’s law, whether it was put forward in 1965: “the number of transistors integrated on semiconductor chips will double every year”, or revised in 1975: “double every 18 to 24 months”, its curve is exponentially increasing. Assuming that at a certain time point, the number of transistors integrated on the chip is x, then it will be 2 × after 18 months, 4 × after 2 18 months, and 2n × X after n 18 months. From now on, we can estimate the number of transistors produced by human beings: Y = X (1 + 2 + 4 + 8… + 2n ), if both sides of the formula are multiplied by (2–1), y = x (2 (n + 1) − 1) can be obtained.
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From the formula 1 + 2 + 4 + 8… + 2n = 2(n + 1) − 1, we can see that no matter how many quantities were produced before, in the next cycle, the production (consumption) quantity in one cycle will be 1 more than the sum of all previous production cycles. On the other hand, as long as the growth of the number of transistors continues to follow the exponential curve, every generation in the future will look back and see that the past era will be an era of almost no progress, which is actually a paradox. The number of atoms in the universe is only 1080 . If the number of transistors increases according to the exponential curve, it only takes a century and a half (about 150 years), and the atoms in the universe will be exhausted, which is obviously impossible! It should be noted that we have made some assumptions in this section. The actual values will be related to the changes of the preconditions, but will not change in the order of magnitude. Therefore, the estimation in this section is of certain reference significance. Let’s go back to the conclusion we gave at the beginning: all curves that grow exponentially are physically unsustainable, so Moore’s law is also unsustainable. I think of a story: A asked B: “do you think a newspaper can be folded in half for 40 times?” B said, “I think so.“ then he found the biggest newspaper and folded it up. What was the result? This is actually an impossible task, because the thickness of a newspaper folded 40 times is more than 110,000 km, far more than two and a half circles around Earth. If a newspaper is folded in half for 27 times, its thickness will exceed the height of Mount Everest. If folded 36 times, it will exceed the distance from the northernmost point to the southernmost point of China. If folded in half for 42 times, it will exceed the distance from Earth to Moon. Why does a thin newspaper have such amazing thickness after being folded in half? This is the magic of the exponential curve, because the thickness of a newspaper after being folded in half is also an exponential curve. The growth of exponential curve is so amazing, the later, the more amazing its growth, all the growth in front of relative to the growth of the latter can be ignored! Now that Moore’s law is coming to an end, there needs to be a new law to replace Moore’s law. So what law can replace Moore’s law? In my opinion, this is the “Function Density Law” that we will talk about below.
1.3 Function Density Law 1.3.1 Description of Function Density Law In this chapter, we propose a new law: “Function Density Law “.
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Fig. 1.6 Function density law curve
Function Density Law: For all electronic systems, along the time axis, the Function Density in System Space is constantly increasing and will continue. Figure 1.6 shows the curve description of the Function Density Law. It can be seen from the curve of Function Density Law that the Function Density of electronic system will continue to increase with time, and its growth rate will be different in different historical periods. If there is a breakthrough in new technology, its growth will be faster, otherwise, its growth will be relatively slow, but the general trend is continuous growth. In addition, Moore’s Law is also included in the curve of Function Density Law, which belongs to the initial stage of Function Density Curve. In some areas of the curve, for example, in the Moore’s Law region, the curve will grow exponentially, but in the long run, it should grow monotonically as a non-exponential curve. To understand Function Density Law, we first need to understand what is Function Density? Function density: The number of Function UNITs contained in a unit volume is called Function Density. The key word of Function Density is Function units, so what are Function UNITs? We need to understand the six level function classification of electronic systems.
1.3.2 Six Level Classification of Electronic Systems A system is an organic whole with specific functions, which is composed of several components that interact and depend on each other, and this organic whole is a component of a larger system to which it belongs. People study systems, design systems, and use them to serve human beings.
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System is usually composed of several Function UNITs, so is the electronic system. At present, there is no clear hierarchical classification method for system. In this book, we first propose the 6-level classification of electrical system to classify the electronic system hierarchically. Please refer to Fig. 1.7. Level 1: Function Cell (FC). Function Cell is the smallest Function UNITs of the electronic system, and cannot be separated. If it is split, the function will be lost and cannot be restored. For example, transistor, resistor, capacitor and inductor belong to Function Cell. Function Cell is the most basic Function UNITs. Level 2: Function Block (FB). Function Block is composed of Function Cells and has certain logical functions. For example, six transistors can form a SRAM storage Function Block, one transistor and one capacitor can form a DRAM storage Function Block, and four MOS transistors can form a NAND gate or NOR gate. Function Block is a Function UNITs with specific functions. Level 3: Function Unit (FU). Function Unit is composed of Function Blocks, which can complete complex functions, such as Arithmetic Logic Unit (ALU), IO Control Unit, Central Processing Unit (CPU), DSP, FPGA, Memory, etc. can all belong to the Function Unit. Function Unit is the highest level of Function UNITs. Level 4: MicroSystem (MS). At this level, we begin to define the concept of system. MS can perform system functions independently and are small in size, and usually do not directly deal with end users, such as SiP (System in Package), SoC (System on Chip), SoP (system on PCB), etc. MS are usually composed of Function Units, Function Blocks, or Function Cells. Level 5: Common System (CS), we can also call it Conventional System, that is, the system that common people can contact. Generally, it refers to the system directly dealing with the end user, and the end user here refers to the common people. For
Fig. 1.7 6-level classification of electronic system
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example, mobile phones, computers, household appliances and so on can be called Common System, which are usually composed of MicroSystems and Function Units. Level 6: Giant System (GS), GS generally refers to complex and huge system, such as wireless communication network system, Internet system, Manned space system, Space station system, etc. Giant System is usually composed of Common Systems, MicroSystems, etc. In above definition, Function Cell (FC), Function Block (FB), and Function Unit (FU), which can all be called Function UNITs (FUs). Each of them belong to different level of Function UNITs. Here, let’s review the definition of Function Density: the number of Function UNITs contained in a unit volume is called Function Density. Function UNITs can be Function Cell, Function Block, or function Unit. Here, what we need to pay attention to is: when comparing the Function Density of the same type of system, we need to use the same level of Function UNITs to define the Function Density. For example, comparing the Function Density of system A, B and C, A uses Function Block as Function UNITs to define Function Density, and B and C also need to use Function Block as Function UNITs to define Function Density. In the same way, when the system changes along the time axis, the same level of Function UNITs should be used to define its Function Density in different time periods. Some readers may ask why the definition of Function Density is not defined by a certain Function UNITs, but by three level of Function UNITs (Function Cell FC, Function Block FB and Function Unit FU)? This is due to the complexity and uncertainty of system function definition itself. For example, with the development of new technology, the structure of Function Blocks has evolved, and only smaller Function Blocks are needed to achieve the same function. In this way, even if the number of transistor (Function Cell at the bottom layer) does not change, the Function Density is also increased. For example, the SRAM that we usually use requires six transistors to implement a memory cell, called 6 T. If a new technology appears, it is possible to realize a SRAM memory cell with two transistors, called 2 T. In this way, even if the number of transistors per unit volume remains unchanged, the Function Density of SRAM can be increased by three times. In addition, there are many kinds of systems with different functions. It is more reasonable and targeted to use different Function UNITs for different systems. For example, some SoC or sip systems can use the number of transistors per unit volume to define their Function Density. Some systems are suitable to use Function Block (FB) to describe their Function Density. For example, the number of storage cells per unit volume can be used to describe the Function Density of some storage systems. Some systems are more suitable to describe the Function Density with Function Unit (FU). For example, the number of CPU, GPU or FPGA in unit volume can be used to define the Function Density of Giant System or Common System. Therefore, the three level of Function UNITs (FUs) are more flexible and more convenient to define the Function Density for different types of systems. It just needs
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the reader’s attention that the same Function UNITs should be used in horizontal or vertical comparison.
1.3.3 Comparison of Moore’s Law and Function Density Law Here, let’s compare Moore’s law with Function Density Law. (1)
(2) (3)
(4) (5)
6)
The object of Moore’s law is semiconductor wafer plane, and the object of Function Density Law is electronic System Space. One is two-dimensional plane, the other is three-dimensional space; Moore’s law describes the number of transistors per unit area, and Function Density Law describes the number of Function UNITs per unit volume; Moore’s law was put forward 56 years ago and has been proved by history, Function Density Law has just been put forward, which is the expectation for the future; Moore’s law is coming to an end, like the sunset, Function Density Law is in its infancy, like the sunrise; If the Function UNITs in the definition of Function Density is defined as a Function Cell (transistor), its space is two-dimensional and its time is specific, then Function Density Law will be reduced to Moore’s law; If the transistor integration on IC is expanded from two-dimensional plane to three-dimensional space, transistor is extended to Function UNITs, and time is changed from concrete to trend, then Moore’s law will be extended to Function Density Law.
For the integration of electronic systems, we can understand that Moore’s law is a special case of Function Density Law in integrated circuits, while Function Density Law is an extension of Moore’s law in the whole electronic system. Figure 1.8 shows the relationship between Moore’s law and Function Density Law. Fig. 1.8 Relationship of Moore’s law and Function Density Law
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Moore’s law is the law of human creativity, which is actually the law of human belief. When people believe that something can be done, they will strive to achieve it. When Moore first presented his observation report, he actually gave people a belief that the trend he predicted would continue. Function Density Law is also the law of human creativity and human belief. When people believe that the Function Density in the space of electronic system will continue to increase, they will also strive to achieve it. Instead of focusing on the scaling of transistors on the two-dimensional plane scale, we put our thinking into a broader space, from multi-dimensional integration, from structured innovation, from a more flexible scale to judge and develop. If we understand and apply Function Density Law, we will not be entangled with the end of Moore’s law, because new space has been opened up for us, and it is wider. Function Density Law was first formally proposed by the author on January 20, 2020. After 20 years of electronic system design and more than 10 years SiP research and design, the author has accumulated rich project experience and obtained the conclusion through long-term analysis and independent thinking. Function Density Law will predict the trend of integration of electronic systems and will become an important indicator for judging the advanced nature of electronic systems. Will Function Density Law become the most important law of electronic system integration like Moore’s law? Here, we are not in a hurry to come to a conclusion. It will take time to verify.
1.3.4 Applications of Function Density Law Let’s look at several examples of the application of Function Density Law: 1.
Giant-Chip Cerebras WSE
On August 20, 2019, the giant-chip WSE (wafer scale engine) from the US start-up cerebras attracted enough attention. The chip’s size reached an astonishing 46,225 square mm, about 22 cm (8.5 inches) on each side, larger than iPad. Cerebras WSE is the world’s first wafer class processor, making only one chip on a 12 inch wafer. The amazing parameters of WSE also include 1.2 trillion transistors (the mainstream chips of the same era are still at the level of 10 billion), and it has 400,000 AI cores, 18 GB SRAM cache, 9 PB/s memory bandwidth, 100Pb/s interconnection bandwidth, etc. in addition, its power consumption is 15000 watts, more than the power of six electromagnetic furnaces, which also shocked the industry. WSE was manufactured by TSMC 16 nm process, which can be used for basic and applied science and medical research. It can give full play to the advantages of its super large-scale AI and cooperate with traditional supercomputers to accelerate AI work.
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Fig. 1.9 Cerebras WSE, the world’s largest chip (2019)
Since the power consumption of WSE chip is more than the power of six induction cooker, it is no exaggeration to say that this chip can be used for dozens of people to eat hot pot together (Fig. 1.9). However, this product can only be classified as a niche product. In addition to attracting attention, it should have no large market in practical application and can only be limited to certain specific application fields. Why? First of all, the chip itself is very fragile and needs to be protected, so it needs to be packaged. In addition to the difficulty of packaging and testing, such a giant chip will also be very large after packaging. In addition, considering its large power consumption, its cooling system will be very complex and huge, so the whole system works together, the volume must be very large. From the perspective of Function Density Law, the Function Density of this chip will be far lower than that of ordinary chip, so it does not conform to Function Density Law. Therefore, WSE has no vitality in most of the markets. We can pay attention to the follow-up development of WSE, how to cool the WSE, and how large the whole system volume of WSE is in actual work, and then use Function Density Law to evaluate it. Because WSE does not conform to Function Density Law, so I think it is no vitality in reality. 2.
Development of Electronic Packaging Technology
Let’s review the development of electronic packaging technology. In 1947, the first electronic package appeared in the world; In 1955, TO type circular metal package appeared with 3–12 pins; DIP (Dual In-line Package) appeared in 1965. The number of pins in package is 6–64, and the pin pitch is 2.54 mm;
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TO package and DIP package generally belong to THT package. The package area and thickness are relatively large, and the pin is easy to be damaged in the process of plug-in, which has a certain impact on reliability. In 1980, devices supporting SMT technology appeared. In device packaging form, there are SOT, SOP, SOJ, PLCC, QFP, etc. the number of pins is 3–300, and the pin pitch is 1.27-3 mm. Among them, QFP is the most widely used. In order to reduce the parasitic effect caused by pins and improve the high frequency performance, people directly use land as connecting pins, thus evolved the QFN package (Quad Flat No-lead Package). With the rapid increase of the number of pins, BGA package has been widely used. The pins of BGA are solder balls, which are distributed on the bottom of the package in the form of array. The ball pitch is 0.8–1.27 mm, which can support more than 2000 pins. With the technology innovation, the driving force of advanced package is becoming stronger and stronger. Packaging technology has gradually changed from the traditional medium and low-end forms such as DIP, PLCC, QFP to BGA, CSP, SiP and other high-end forms. In CSP (Chip Scale Package), the proportion of silicon chip area to package area is more than 80%. In DIP package, the chip area accounts for less than 5% of the package area, while in the CSP chip size package, the silicon chip area accounts for 80% ~ 100% of the package area. Please refer to Fig. 1.10 below. The number of integrated transistors (Function Cells) per unit volume of CSP package is much larger than that of DIP package. That is to say, the Function Density of CSP is much greater than that of DIP, which is in accordance with Function Density Law. With the development of packaging technology, from TO, DIP to PLCC, QFP then to BGA and CSP, there are more and more Function Cells per unit volume, and their Function Density is increasing, which is in line with Function Density Law. We can understand that the development of integrated circuit technology is in line with Moore’s law, while the development of integrated circuit technology and electronic packaging technology both conform to Function Density Law. 3.
Development of 3D NAND Technology
Fig. 1.10 Comparison of DIP package and CSP package
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Fig. 1.11 Physical structure comparison between 2D NAND and 3D NAND
The transistors on ordinary IC are still in a plane layer. In order to improve the Function Density per unit volume, can we stack the transistors in multiple layers? The answer is yes, the following 3D NAND is a typical example. In 2D NAND, memory cells are arranged in a plane, such as a bungalow, while in 3D NAND, memory cells are stacked, just like a skyscraper (Fig. 1.11). Previous flash memory mostly belongs to planar NAND, while 3D NAND refers to the flash memory with three-dimensional structure. From 2D NAND to 3D NAND is like from a bungalow to a skyscraper, so the storage space will be increased significantly. The three-dimensional storage cell means that more storage cells can be contained in unit volume. Now, the 96 layer 3D NAND is very mature. The thickness of each layer of transistor is about 60 nm, and the thickness of the overall flash memory stack is only about 6 µm. NAND flash integration to 3D direction, in the unit volume integration of more memory units (Function UNITs), is in line with Function Density Law. At present, 3D integration at IC level is only limited to 3D NAND. Other types of chips are basically planar 2D integration, that is, all transistors are located in the same plane, and then 3D integration is performed by stacking chips. In addition, it should be noted that the 3D NAND and 3D IC we usually hear are not the same concept, readers should not be confused. 3D IC generally refers to 3D integration through chip stacks. It belongs to the category of package or SiP that the wafer is thinned and then stacked after the IC process finished. 4.
Development of SiP and Advanced Package
The rapid development of consumer electronics and communication electronics puts forward higher requirements for electronic system integration. SiP and HDAP (High Density Advanced Package) can integrate different function chips on a single substrate in 2D plane or stacking in 3D space, and then package all of them into one package to form a complete and independent MicroSystem. The emergence of SiP and HDAP has greatly increased the Function Density of the system. Therefore, SiP and HDAP have been paid more and more attention and have been widely used in industry in recent years. The emergence and development of SiP and HDAP is the most direct embodiment of Function Density Law.
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Now, we can even say that almost everyone can’t do without SiP technology. Because each mobile phone uses SiP technology, and SiP has begun to be more widely used in various fields of national production and life. So why are SiP and HDAP receiving so much attention and rapid development in the short term? Before SiP technology is available, all chips are usually individually packaged and integrated on PCB. The chip package itself occupies a lot of space, so the Function UNITs in unit volume of PCB are relatively small, that is, the Function Density is relatively low. After the emergence of SiP technology, many chips are packaged together, and the Function UNITs integrated per unit volume is higher, that is to say, it has higher Function Density. HDAP adopts more advanced packaging technology. Through RDL and TSV, the integration degree in the package is higher, and the Function Density in the package is further improved. The microstructure of IC on wafers has reached its limit, while SiP and 3D Integration in advanced package have broad space. From the above four examples, we can see that the “ Function Density Law” is indeed the trend of electronic technology development, and will become the most important law of electronic system integration. Although Function Density Law has just been proposed, it has not been verified by long-term practice. However, the author predicts that Function Density Law itself has strong vitality, which will represent the development trend of electronic technology. Of course, can FD Law really represent the development trend of electronic technology? Let’s wait and see.
1.3.5 Extension of Function Density Law Function Density Law is proposed for electronic systems. It can cover MicroSystems such as SiP and SoC, Common Systems such as mobile phones and computers, or Giant Systems such as mobile communication network and the Internet. Looking at the various systems around us, most of their functions have become more and more rich. Some systems are getting more and more functions, and their volume is getting smaller and smaller, while others are getting more and more functions, their volume is not significantly reduced.
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Here we extend Function Density Law in three ways. (1)
All integration will increase the Function Density of the system
Integration here refers to System Integration, which combines different Function UNITs or subsystems together and coordinates their work organically, exerts overall effectiveness and achieves the goal of overall optimization. (2)
All man-made systems will continuously increase in Function Density
Here refers to man-made systems rather than man-made objects, some of which have remained functionally unchanged for thousands of years. Man-made system is an organic whole with specific functions created by human beings by combining several components. It will evolve with the progress of human beings. During the process of development and evolution, its Function Density will continuously increase. (3)
The definition of Function UNITs also needs to include software units.
When we described Function Density earlier, we did not include software. For the same hardware system, if different software is installed, the Function Density will be different. For example, for the same mobile phone, the more software features installed, the more Function Density, i.e. more functions are integrated in the same space, where the Function UNITs are the software units or modules. Finally, we need to remind the reader that the evolution of the system is irreversible, as is the increase in the Function Density of system, so systems that do not conform to the Function Density Law will eventually be phased out.
1.4 General Function Density Law In the vast universe, will human be the dominant? The Cognitive Revolution, which began 70,000 years ago, distinguished humans from animals and made Sapient, the ancestor of modern humans, stand out among at least six humans, jumping to the top of the food chain and dominating the planet. The Scientific Revolution, which began 500 years ago, raised human understanding of the objective world to a new level and proposed new principles for understanding the objective world. The importance of the scientific revolution is to acknowledge human ignorance, centering on observation, mathematics and experimentation. In fact, the scientific revolution has made the thinking mode of human beings, from worship fathers, saints and emperors, to revere the facts, practice and results of law, thus promoting the great progress of human civilization. 63 years ago (1958), the invention of integrated circuits could be seen as an “Electronic technology revolution”. From then on, the scale of transistors, the Function cell of electronic systems, gradually changed from macro to micro, and Moore’s Law became the most important law for the development of integrated circuits.
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Sixty years ago, about 1 billion transistors were produced annually around the world. Today, more than 10 billion transistors can be integrated in a single cell phone chip. The average number of transistors integrated per square millimeter is over 100 million. As the Feature size in the transistor approaches 1 nm, which is equivalent to the diameter of only a few silicon atoms, the laws in the continuous system will be invalidated and the existing transistor structure will be completely invalidated. So what should we do? There are roughly two ways to go: one is to completely change the existing structure of the electronic system Function Cells (Transistors) to create a brand new Function Cells; the other is to integrate more Function UNITs in the space of the electronic system from the perspective of the entire electronic system, where the Function UNITs can be Function Cells (Transistor) or other Function UNITs (Function Blocks, Function Units). At this point, we need to have a deep understanding of Function Density Law.
1.4.1 System Space Definition Function Density Law is described as follows: For all electronic systems, along the time axis, the Function Density in System Space always increases continuously and will continue. There is a keyword in the description of Function Density Law: “System Space”. How do we define System Space? Let’s start with an example. In 1946, the world’s first computer was launched, using 18,000 electronic tubes, covering 170 square meters, weighing 30 tons, consuming 150 kW of power and performing 5,000 operations per second. The volume of this computer can be defined as its System Space. Its Function Density is: number of Function UNITs / computer volume, we can see that this computer’s Function UNITs (Function Cells) are 18,000 transistors, because the computer is so large, its Function Density is very small. In 2020, the number of transistors integrated in a mobile phone reached 10 billion orders of magnitude, while the size of the mobile phone was just palm size. In comparison with the world’s first computer, we can see how the Function Density in System Space has increased beyond imagination in just over 70 years. Next, we give the definition of System Space. System Space Definition: The space occupied by the volume of an independent system when it is in operation is called its System Space. The System Space of SiP is the volume of its package, the System Space of mobile phone is the volume of mobile phone, the System Space of notebook computer is the space occupied by its working state, the System Space of mobile communication network is the area space covered by it, etc.… The definition of System Space has some flexibility. What we need to ensure is that, for any independent system, the definition of System Space does not change along the time axis.
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1.4.2 Earth Space and Human Cosmic Space We can use our imagination to enlarge the system to a larger extent, such as an office, a building, a neighborhood area, a city, a region, a country, or even the whole earth. The Function Density Law can be used to judge the progress of technology. In 1947, human invented the first transistor. In 1958, human invented the first integrated circuit. Since then, electronic technology has produced a huge revolution, and has been widely used in various industries such as electronics, communications, aeronautics, space, ships, vehicles, constructions, services and so on. All in all, the number of transistors on Earth has been increasing tremendously. Let’s imagine wrapping the entire earth around with a sphere and using it as a System Space, where the Functions Density is always increasing and will continue for the foreseeable future of human beings. 1.
Earth Space
Earth Space: Here, we define Earth Space as the space contained in a sphere centered on Earth and radius from Earth’s center to the orbit of a geosynchronous satellite (36,000 km from the ground). As shown in Fig. 1.12, the white dots represent satellites. From Fig. 1.12, it can be seen that the vast majority of satellites are in the Earth Space, which also follows Function Density Law, that is, along the time axis, the Function Density in the Earth Space continues to increase. Before 1900, there were almost no electronic components on Earth. One hundred and twenty years later, electronic systems have spread across Earth surface, gone deep Fig. 1.12 Earth space definition
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into Earth interior and expanded into Earth space. With the exploit of the universe by human beings, the Function Density Law will cover more widely space. 2.
Human Cosmic Space
Next, we will define the next space, Human Cosmic Space. Human Cosmic Space: Draws a sphere with Earth as the center and the radius of the average distance from Earth to the farthest planet on which human has landed. The space contained in such a sphere is called Human Cosmic Space. At present, human has landed on Moon, so currently Human Cosmic Space is the volume of a sphere centered on Earth and the radius based on the average distance from Earth to Moon. If humans successfully land on Mars in the future, the Human Cosmic Space will expand to a sphere centered on Earth, with the average distance from the orbit of Earth to the orbit of Mars as the radius. Because the rotation cycle of Mars is different from that of the Earth, the distance between Earth and Mars is calculated as the point at which Mars crosses the sun, so the average distance from the Earth to Mars is calculated as the average distance between their orbits (Fig. 1.13). With the further exploration of the universe, the sphere of Human Cosmic Space will become larger and larger. Since human landing on a new planet can only be done step by step, each step will take a long time to complete. Therefore, in a relatively long time zone, Human Cosmic Space is relatively fixed, which makes it easy to define the Function Density in its space. When humans land on a new planet, the extent of Human Cosmic Space needs to be redefined. Fig. 1.13 Diagram of human cosmic space
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1.4.3 General Function Density Law On the basis of Function Density Law and Human Cosmic Space, we define General Function Density Law. General Function Density Law: In Human Cosmic Space, along the time axis, the Function Density continuously increases, this is General Function Density Law. How Function UNITs is defined in General Function Density Law? Based on Function Density Law, Function UNITs can be extended accordingly. Therefore, in General Function Density Law, the Function UNITs can be Function Cells, Function Blocks, or Function Units, and can also be extended to MicroSystems, Common Systems, or even Giant Systems. It is important for readers to note that the same definition needs to be maintained when making longitudinal comparisons along the time axis. Why should the farthest planet on which human landed be defined as Human Cosmic Space? Defining Human Cosmic Space in this way has relative certainty. Moreover, as human beings successfully board other planets, it is necessary to gradually establish bases on this planet, and there will be more and more spacecraft to and from Earth. At the same time, ancillary communication or service transfer stations will be gradually established in this space, so in the sphere contained in Human Cosmic Space, their Function UNITs will inevitably increase, and the Function Density will continue to increase. Why not define the General Function Density Law at the farthest distance that a human cosmic detector can reach? This is due to the uncertainty of its space, such as the fact that Voyager 1 is currently flying out of the solar system and is continually flying, that its space is constantly changing. Such spacecraft is currently very sparse, and the Function UNITs in such space are so sparse that it does not need to be defined by Function Density. In the Human Cosmic Space, with the progress of human civilization, its Function Density will also increase, that is, the number of Function UNITs in the unit space will continue to increase. With the progress of human exploration of the universe, Human Cosmic Space will become larger and larger, and the Function Density in each Human Cosmic Space will continue to increase, which is the meaning of General Function Density Law. From Earth to Moon to Mars, from the Solar System to Galaxy to the wider space, the human exploration will never stop, and the General Function Density Law will be applied to a vaster space (Fig. 1.14).
1 From Moore’s Law to Function Density Law Fig. 1.14 Diagram of 8 planets of solar system
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Chapter 2
From SiP to Si3 P Suny Li
2.1 Concept Deepening: From SiP to Si3 P The two keywords of System in Package are System and Package, the word “in” seems insignificant but also plays an important role, indicating that the whole system is contained within a package. In this chapter, we propose a new concept: Si3 P, which is used to enhance the understanding of SiP. Of course, this is not to rename SiP, but to understand the meaning of SiP more deeply and comprehensively. With the following five diagrams, we can clearly understand what Si3 P means. First, let’s look at Figure 1 (see Fig. 2.1), by expanding an “i” to three “iii”, which represent integration, interconnection, and intelligence. Figure 2 (see Fig. 2.2), integrations are the first level of insight into SiP. The main concerns are the packaging structure used by SiP, the advanced technology used by SiP, and the advanced materials used by SiP. The Key Words related to integration include: FOWLP, InFO, CoWos, HBM, HMC, Wide-IO, TSV, Flip Chip, AiP, Chiplet, Cavity, Die stack, Heterogeneous etc. Integration needs to understand SiP more from the perspective of “physical structure”. Integration is just like building a construction. Whether building a flat or a tall building, it requires detailed planning of the structure, materials, and process of the building, and strictly in accordance with the specifications. Integration is also the focus of SiP technology today. Every advanced packaging structure, advanced process technology and advanced materials will become the focus of attention in the industry .
S. Li (B) Beijing, China e-mail: [email protected] © Publishing House of Electronics Industry 2022 S. Li (ed.), MicroSystem Based on SiP Technology, https://doi.org/10.1007/978-981-19-0083-9_2
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Fig. 2.1 SiP → SiiiP
Fig. 2.2 Integration
Integration is the basis of SiP implementation and the most intuitive understanding of SiP by most people. Figure 3 (see Fig. 2.3), interconnection, which represents the meaning of “interconnection, and transmission”, is the second level of insight into SiP. The main concerns are Interconnection of EM in SiP, Interconnection of Thermo in SiP, and Interconnection of Force in SiP. The Key words related to interconnection include: Die pin, Bond wire, Trace, Via, RDL, Bump, Interposer, Substrate, Model, Impedance, Loss, Crosstalk, Thermal resistance, Thermal capacity, External force, Internal force and etc.
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Fig. 2.3 Interconnection
Interconnection needs to understand SiP more from the perspective of “energy transfer”, which is like urban transportation. To properly transmit signals to different places, roads and facilities need to be built. The metal trace in SiP substrate is like roads in a city, responsible for transmitting all kinds of electromagnetic signals. In addition, we also need to consider interconnection of thermal and interconnection of force, transfer heat from chip to outside through substrate or heat sink channel, and take into account the stress caused by deformation, and make a reasonable stress release. Interconnection is the key to the functionality implementation and performance improvement of SiP, and it is becoming more and more important now. Figure 4 (see Fig. 2.4) intelligence. Currently, Artificial Intelligence is the most interesting aspect of intelligence Intelligence is the third level of insight into SiP. The main focuses are: (1) system function definition, (2) product application scenarios, (3) SiP testing and debugging, (4) software and algorithm. The key words are: System, Function, 5G, HPC, AI, IoT, Mobile phone, Autopilot, Aerospace…, Testing, Debugging, Software, algorithm etc. Intelligence needs to be understood more from the perspective of “function application”. Intelligence is just like human. With people, the construction and the transportation will have meaning, so intelligence can be the core of SiP. Intelligence is the core for SiP to implement function definition and product application. One of the important points is to take software and algorithm into account in the whole SiP system and optimize them together with the whole system.
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Fig. 2.4 Intelligence Fig. 2.5 SiP → Si3 P summary
Figure 5 (see Fig. 2.5), we make a summary. When designing a SiP, we should think and design with the idea of Si3 P, not only from the perspective of integration—Physical Structure, but also from the perspective of interconnection—Energy Transfer and intelligence—Functional Application.
2.2 Integration of Si3 P In this section, we will give a detailed explanation of the integration in Si3 P.
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Fig. 2.6 Three Level of Electronic System Integration
From the perspective of electronic system integration, it can be divided into three levels of integration, see Fig. 2.6. (1) (2) (3)
Integration on Chip, the most representative of which is SoC; Integration in Package, the most representative of which is SiP; Integration on PCB, the most representative of which is SoP (PCB).
2.2.1 Chip Level Integration Chip Level Integration that we can also call Integration on Chip. Integrated Circuit (IC) is the process of fabricating many transistors, resistors, capacitors, and other components on a very small silicon chip, and connecting them to complete electronic circuits with specific functions (Fig. 2.7). Jack Kilby, the inventor of Integrated Circuit, believes that all the devices needed for a circuit can be made from a single silicon material. Circuits consisting of resistors, capacitors, diodes and triodes can be integrated on a single silicon chip, requiring only one semiconductor material to integrate all electronic devices. Today, we call this kind of integration Homogeneous Integration. On September 12, 1958, the first Integrated Circuit, Phase-Shift Oscillator consisting of resistors, capacitors, diodes and triodes, was tested successfully. The finished product is 0.12 × 0.4 inches (3.05 × 10.2 mm). 42 years later, Kilby won the 2000 No\bel Prize in Physics for inventing Integrated Circuit.
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Fig. 2.7 World’s first integrated circuit (1958)
From September 12, 1958 to now, Integrated Circuits have been on the road of integration for more than 63 years. Integration has always been the primary concern of IC. Today, Integrated Circuits have profound impacts on every corner of our society. The Integrated Circuit itself has also undergone dramatic changes, from the initial millimeter scale (mm) to the micrometer scale (µm) to today’s nanometer scale (nm), reducing by millions of times, and the number of transistors integrated in one chip has reached 10 billion levels. For example, Apple A14 processor: integrates 11.8 billion transistors with 5 nm process; Huawei Kirin 9000 processor: integrates 15.3 billion transistors with 5 nm process. IC level integration is mainly reflected in three aspects. 1.
Reduction in Transistor Size and Increase in Number
In 1958, the first Integrated Circuit was developed successfully, consisting of only a few transistors at mm scale. In 1971, 2300 transistors were integrated in Intel 4004, and the process was 10 µm. In 1989, Intel 486 integrated 1.2 million transistors internally, using 1 µm process. In 2000, Intel Pentium 4 integrated 42 million transistors internally, using 0.18 µm process. In 2010, Intel Core i7-980X integrated 1.170 billion transistors with 32 nm process. In 2018, Intel i9-9980 integrates about 10 billion transistors with a 14 nm process. In 2019, Huawei Kirin 990 5G processor integrated 10.3 billion transistors with 7 nm process.
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In 2020, Apple A14 processors integrated 11.8 billion transistors with 5 nm process. After more than 60 years of development, Integration on Chip has developed sufficiently and is almost at the end. Ultimately, the reduction of transistor process size will reach the limit. Currently, the mainstream process has reached 5 nm and is progressing towards 3 nm and 1 nm. The radius of silicon atom is 0.117 nm, the edge length of silicon crystal is 0.54 nm, and the width of 1 nm can only place three silicon atoms. 2.
Expansion of Chip Area
To increase the integration on silicon chip, one way is to reduce the volume of a single transistor, the other is to increase the area of silicon chip. However, for a long time, due to process constraints and cost constraints, the chip area has not changed much, the chip area about 400 square millimeters (20 mm X20 mm) can be called large chip. In 2017, Tesla V100 created a chip size record of 815 square millimeters. On August 20, 2019, the Wafer Scale Engine, a giant chip from Cerebras, a US startup, reached an astonishing 46,225 square millimeters, about 22 cm (8.5 inches) on each side, larger than the iPad (Fig. 2.8). WSE uses the TSMC 16 nm process to make only one chip on a 12 inch wafer. WSE has 1.2 trillion transistors, while other mainstream chips are all in the 10 billion level. WSE consumes 15,000 watts of power, which is about 1,000 times the power consumption of ordinary chips, and its cooling will also be a big problem. In addition, its large area and the number of 1200 billion transistors present a significant challenge to packaging and testing. So we can only classify this product
Fig. 2.8 World’s largest chip WSE (2019)
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as a niche product. In the short term, apart from attracting attention, it is not very practical and should not have a large market in the long-term practical application. It seems that there is also a limit to chip area growth, not the larger the area, the better. 3.
Developing Towards 3D Structure
Let’s look at Fig. 2.9, which shows a comparison of the Planar FET, FinFET and Stacked nano sheet FET structures from left to right. From Fig. 2.9, we can see that the transistor’s micro-structure has changed from planarization to 3D, but transistors are still in a planar layer on the wafer of Integrated Circuit. So, can transistors also be stacked on multiple layers? The answer is yes. A typical example is the 3D NAND Flash shown in Fig. 2.10 below. Now, the 3D NAND Flash stack of 100 + layers is quite mature. Each transistor layer is about 60 nm, and the overall flash stack is only about 6 µm. With the development of IC integration in 3D direction, the main difficulty is that the process is very difficult, and the current range of application is limited to the
Fig. 2.9 Physical structure of three types of transistors
Fig. 2.10 3D NAND Flash structure
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field of 3D NAND. For other types of chips, only planar structure is used, that is, all transistors are in a planar layer. Of course, in the future, technology development will often exceed our imagination.
2.2.2 PCB Level Integration After discussing the integration on IC, let’s take a look at the integration on PCB. PCB, also known as Print Circuit Board, is an important carrier for electrical connection of electronic components. Almost every electronic device, from electronic watches, calculators, mobile phones to computers, from cars, trains, airplanes, ships to satellites, from wearable devices to communication nets and internet systems, all use PCB for electrical interconnection whenever there are electronic components. It can be said that PCB is one of the most important components in modern electronic industry (Fig. 2.11). The history of PCB is 22 years ahead of Integrated Circuits, and it has been more than 80 years since the birth of PCB. In 1936, Dr. Paul Eisner, an Austrian, introduced the concept of “Printed Circuit” in the United Kingdom, who is known as the “father of PCB”. 1.
Increase the Density of PCB Integration
From the birth of PCB technology to today, the integration degree on PCB has also been greatly improved. Fig. 2.11 Electronic system integration on PCB
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The integration on PCB is mainly reflected in two aspects: (1) the improvement of the integration degree on PCB substrate, mainly including the increase of trace density and number of layers; (2) the improvement of device assembly density, which is mainly due to the reduction of device package size and the increase of pin density. At present, the trace width and clearance of PCB substrate can reach 50 µm level or even smaller, the layers of PCB can even reach more than 100 layers. Due to the improvement of packaging technology, the smaller size of device packaging, the larger pin density and the pin arrangement from linear to planar array also greatly promote the improvement of PCB integration. At PCB level, integration has been fully developed, and there is not much room for further improvement, such as continuing to reduce trace width and clearance, or increasing the number of layers. So people are also considering whether they can do 3D integration on PCB level? 2.
3D Integration on PCB
Although most of the integration on PCB is 2D, there are also some attempts at 3D technology. Usually there are two ways, one is to bury devices in PCB substrates, including passive devices and active devices, but due to process difficulties and production costs, it is not widely used, but in package or SiP substrates, this technology has been more widely used. Another way is to stack PCB, such as Apple’s iPhone X (Fig. 2.12). However, currently stacked PCB technology is rare, and the integration on most PCBs is basically on the XY plane. PCB is not suitable for 3D integration for the following 3 reasons. Fig. 2.12 Stacked PCB technology
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(1) PCB is relatively large in size and has much limitations in 3D integration; (2) Components. installed on PCB usually do not support 3D stacking installation; (3) 3D integration on PCB, often need mechanical components to improve the structural strength, which complicates the mechanical design.
2.2.3 Package Level Integration Next, we will focus on Package Level Integration. 1.
History of Integration in Package
First, let’s look at the history of integration in package. The first microelectronic package can date back to 1947, 11 years before Integrated Circuit and 11 years after PCB. In 1947, three scientists from Bell Laboratories, John Bardeen, Walter Brattain and William Shockley, invented the first transistor and also opened the history of microelectronic package. The earliest electronic package was the TO type package with three leads, gradually developed to the dual in-line (DIP) package as the mainstream. From DIP packaging, due to the complexity of the chip itself, the number of leads that need to be led out becomes more and more. The package begins to develop gradually from DIP with dual side pins to LCC, QFP with four side pins, PGA and BGA with plane array pins. The main functions of traditional electronic packaging are: (1) scale amplification, (2) electrical interconnection, (3) chip protection. Because the traditional electronic package usually contains only one IC chip, there is no concept of integration (Fig. 2.13). Until one day, MCM (Multi-chip Module) came into being, which means multiple chips are integrated in it. The development of MCM is closely related to the HIC (Hybrid Integrated Circuit). Hybrid Integrated Circuit includes thick film Hybrid Integrated Circuit and thin film Hybrid Integrated Circuit. Which is corresponding to the IC monolithic Integrated Circuit mentioned earlier in this chapter. With the rapid development of HIC technology, MCM appeared gradually and the integration in package began. MCM appeared in the late 1980s (about 40 years after the development of electronic packaging technology), and began to develop rapidly after the 1990s (Fig. 2.14). MCM is widely used in aviation, aerospace, weapons, ships and other fields. It does not have much intersection with the traditional electronic package, but as a technology of hybrid Integrated Circuit developed to a certain extent. However, MCM itself is the integration within the package, which can be regarded as the pioneer technology of Integration in Package.
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Fig. 2.13 Single chip package (QFP)
Fig. 2.14 A high power control MCM
MCM is mainly based on two-dimensional integration, and the chips are usually distributed in XY plane. In addition, the chip size and function of MCM are relatively small. Therefore, MCM can’t be called a stand-alone system, we call it module. The spring of integration in package did not really come until the emergence of SiP technology. To some extent, we can say that SiP is the most typical representative of integration in package. When did the real SiP technology come into being? The exact time is not easy to trace. It was at the end of last century. Around 2009, SiP technology began to be
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widely used in China. The author is one of the first engineers to participate in SiP R & D. After the emergence of SiP technology, commercial companies rarely make clear whether they adopt SiP technology, so SiP is not known to the public, but discussed and circulated among relevant technical personnel. Until September 2014, Apple launched Apple watch, which was expected by many people, and clearly proposed to adopt SiP technology. SiP began to become hot all of a sudden, many large companies said to enter SiP field. Based on the concept and ideas of SiP, new concepts and technologies emerge one after another, and advanced packaging technologies also emerge. For example FOWLP, InFO, CoWos, HBM, HMC, Wide-IO, AiP, Chiplet, Cavity, Die stack, Heterogeneous etc. Please don’t let these words confuse your eyes. These technologies are all based on different structures, processes and materials to realize the integration in package. Including OSAT (Out Sourced Assembly and Testing), IC Foundry, system manufacturers have. begun to pay attention to SiP technology, and actively carry out SiP R & D and application. 2.
3D Integration in Package
Inside package, 3D integration has advantages naturally, and there are many types of 3D integration. The 3D technology based on chip stacking is still widely used in the field of packaging integration. In this kind of 3D technology, bare chips are stacked together from bottom to top to form a 3D stack, which is connected by bonding wires from chip sides to substrate, and finally presented in the appearance of SiP. The stacking mode can be pyramid stacking, cantilever stacking, side-by-side stacking, etc., as shown in (Fig. 2.15). Another common way is to install a FlipChip on SiP substrate, and another bare chip is bonded on top of it. As shown in (Fig. 2.16), this 3D solution is more commonly used in mobile phones. 3D integration based on passive TSV, a silicon interposer is placed between the package substrate and bare chips. There are Through Silicon Vias (TSV) in the interposer, and the metal layers on the upper and lower surfaces of the silicon interposer
Fig. 2.15 3D integration technology based on chip stacking
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Fig. 2.16 3D integration of bond wire chip and flip chip
Fig. 2.17 2.5D IC based on passive TSV and 3D IC based on active TSV
are connected by TSV. This kind of integration technology is usually called 2.5D IC, because the silicon interposer as the intermediate layer is passive, and the TSVs are not punched in the chip itself. 3D Integration based on active TSV, at least one bare chip is overlapped with another, and the lower bare chip adopts TSV technology. Through TSV, the upper chip communicates with the lower chip and SiP substrate. This kind of 3D integration technology is often referred to as 3D IC. Figure 2.17 shows the 2.5D IC based on passive TSV and 3D IC based on active TSV respectively. All of the above technologies in this section refer to 3D integration by stacking after the chip process is completed. These means are basically carried out in the packaging stage. We can call them 3D integration within package, 3D packaging or 3D SiP technology.
2.2.4 Summary of Integration Finally, we compare the features of integration in IC, PCB and package, and make a summary and related prediction. 1.
Integration on Chip
The micro scale of the transistor on IC is difficult to continue because it is close to the theoretical limit; The increase of IC area leads to the increase of cost, process difficulty, high power consumption and so it is an unsustainable development;
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The 3D integration on IC is very difficult. At present, it is only limited to 3D Nand Flash. There are no corresponding products and good solutions for other type of device. 2.
Integration on PCB
The increase of trace density and layer number on PCB substrate has been developing slowly for many years, basically reaching the practical limit. There is not much room to continue to reduce the trace width and clearance, or to increase the number of layers; The increase of PCB assembly density depends on the reduction of package size and the increase of device pin density; PCB size is relatively large, 3D Integration limitations are relatively large, components installed on PCB usually do not support 3D stack installation. PCB itself to carry out 3D integration in the structural strength is often to rely on mechanical components, which makes the mechanical design more complex, so the practicability is not good. 3.
Integration in Package
The history of integration in package is shorter than that of package itself. Compared with IC and PCB, the development of integration in package is far not enough and has greater development potential. Unlike IC and PCB, which were initially focused on integration, integration in package was the outcome of package technology developing to a certain extent (about 40 years after the emergence of electronic package) and combined with Hybrid Integrated Circuit technology, so it has a relatively short history and thus has greater development potential. In the field of 3D integration, the integration inside package has natural advantages. The upward pins of the bare chip are connected to the substrate through bond wire, which makes it easy to stack. FlipChip and Bond Wire chip can stacked together. With the development of interposer and TSV technology, 3D integration inside package is even more powerful. The package scale is moderate, unlike IC which has reached the limit (a few atoms alignment) at micro level, or PCB which has a larger size at macro level, its integration often needs to be strengthened by mechanical components, so the integration in package is more suitable for the requirements of current technology development. From the above summary, we can see that the integration in package represented by SiP technology will become the fastest and most potential technology in electronic system integration technology at this stage. Finally, it is important to note that integration is the basis for the development of SiP technology, but SiP is not only limited to integration. We will continue to discuss the interconnection and intelligence later, which are also the essence of SiP technology.
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2.3 Interconnection of Si3 P In the previous section, we elaborated on the first “i”—integration in Si3 P. Below, we explained the second “i”—interconnection in Si3 P in detail. Interconnection means: interconnection and the transmission of information or energy through interconnection. For a SiP, interconnection can be divided into three main areas: • Interconnection of EM • Interconnection of Thermo • Interconnection of Force In this section, we will use more analogy to illustrate the problem. Although not necessarily accurate in the strict physical sense, it is more visualized, has a certain sense of picture, is easy for image memory, and is easier for readers to understand. Therefore, readers are required to actively stimulate their brains and give full play to their imagination. Figure 2.18 show the interconnection diagrams that all SiP designers need to consider.
2.3.1 Interconnection of EM Interconnection of EM, the object of study is signal. Signal transmission requires specific paths, which are the conductors belonging to different nets in SiP, including Die pins, bonding wires, Bump of chips, trace in substrate, vias, pins of package, etc. So, how can the interconnection of each net be optimal? 1.
Net Optimization
Fig. 2.18 3 kinds of interconnections need to be considered in all SiP designs
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In SiP design, the first step of Interconnection of EM is to optimize the net of interconnection relationships, which is different from IC and PCB design. Because in SiP design, whether the pins are dozens, hundreds or even thousands, designers are required to define the function of each pin. So how can you best define it? This is what net optimization needs to focus on. The basic principle of net optimization is to minimize crossover and interconnection. Some EDA software has special net optimization tools, and software can also switch pins automatically to optimize the interconnection relationship. If the software auto-optimization is not enough, the optimal net interconnection can be achieved by manually exchanging the SiP packaging pins. See Fig. 2.19 before and after net optimization. After net optimization, the interconnections need to be connected through metal conductors. At this time, we need to use Bond Wire, Trace, Via, Bump, etc., to connect chip pins with the same net to each other and from chip pins to SiP package pins, in which signals are transmitted. Refer to Fig. 2.20 for the signal transmission path from chip to package.
Fig. 2.19 Comparison before and after net optimization
Fig. 2.20 Signal transmission path from chip to package
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Fig. 2.21 Signal rise time and fall time definition
2.
Rise Time
Signal transmission is accompanied by the electromagnetic field generated by the signal, signal is transmitted in the conductor. The electric field and magnetic field generated by the signal are transmitted together with the signal in the surrounding medium. A signal has two "speeds". One is the physical speed at which it is transmitted, the other is the rate at which it changes. The physical speed of signal transmission is very fast, equal to the speed of light (3 × 108 m/s) in vacuum, in the substrate, about half of the speed of light (organic material) or one-third of the speed of light (ceramic material). Signal is transmitted so quickly, that in ceramic material at least two and a half circles around the earth in one second. Furthermore, the physical speed of signal transmission is independent of the frequency of the signal. The rate of signal change is slow or fast and controllable, usually measured in terms of the time from low level to high level, called rise time. See Fig. 2.21 for the definition of signal rise time and fall time. Generally speaking, the rise time of a signal is not the time it takes for the signal to rise from a low level to a high level, but a part of it. There are usually two types of signal rise time: the first is defined as the 10–90 rise time, which is the time the signal takes to rise from 10 to 90% of the high level. Another is the 20–80 rise time, which is the time it takes for the signal to rise from 20 to 80% of the high level. 3.
Characteristic Impedance
Signals travel along conductors, which are often considered transmission lines. When analyzing a transmission line, it is important to consider its return path. A single conductor and its return path together form a transmission line. The characteristic impedance of a transmission line refers to the ratio of instantaneous voltage to current at a point during signal transmission, which is expressed in Z0. In the course of signal transmission, if the characteristic impedance on the
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transmission line changes, the signal will reflect at the point where the impedance is not continuous. The factors that affect the characteristic impedance of transmission line are dielectric constant, dielectric thickness, trace width, copper foil thickness, surface roughness, etc. Generally, the faster the signal changes, the higher the requirement for the continuity of the characteristic impedance. We can compare the rate of signal change to a moving car, transmission line to a highway, and the change of characteristic impedance to the change of road condition, as shown in Fig. 2.22 below. If the characteristic impedance is continuous, the car will move forward smoothly. If there are potholes on the road surface (impedance discontinuity), the vehicle may bump (signal reflection), and if there is a big pit (serious impedance discontinuity), the vehicle may drive out of the road (signal transmission failure). If the speed is fast (high-speed signal), it is necessary to take the highway as smooth as possible (smooth road surface, good impedance continuity), and if the road condition is not good, reduce the speed as far as possible (reduce the rise time of the signal). As people often say, if the road condition is not good, slow down a little and get to the destination safely. The same is true for signal transmission. On the premise of meeting the function, the change rate of signal should be reduced as much as possible. At the same time, to optimize the transmission line, for designers, the signal transmission line is our own design, so we can control more parameters. The impedance of transmission line will be affected by line width, copper thickness, dielectric properties, dielectric thickness and other parameters, so in the process of signal transmission, impedance discontinuity on transmission line is very common. For example, from die pin to bond wire, from bond wire to substrate, traces through vias, switching to other layers, connecting to package pins, from package pins to PCB, and so on, impedance discontinuity will be more or less, but the signal can normally transmit. Just as the road surface is uneven, the vehicle can reach the destination normally. It is important to control the appropriate speed when drive on different roads. For different types of high-speed signals, it is necessary to plan, design and build corresponding “roads”.
Fig. 2.22 Compare signal transmission to a car driving on the highway
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Signal Integrity, Crosstalk, Delay and EMI
In order to study the signal transmission, we need to understand the signal integrity, crosstalk, delay and EMI in addition to the characteristic impedance. SI (signal integrity) means that the receiver can correctly identify the signal and make the correct response. When the receiver can’t respond normally or the signal quality cannot make the system work stably, the signal integrity problem appears. Signal integrity mainly studies overshoot, reflection, timing, oscillation, etc. Figure 2.23 shows the eye diagram of signal integrity. Crosstalk studies the coupling and interference between signal lines, mutual inductance and mutual capacitance between signal lines. We can use a phenomenon to compare crosstalk. When we ride on a high-speed train, we encounter a high-speed train passing by us, and the train body is subject to a huge disturbance. This disturbance is mainly determined by three factors: speed, distance between two trains and train length. This phenomenon can help us understand crosstalk, because crosstalk is also mainly caused by three factors: the rise time of the signal (speed), the spacing between two signal lines (distance), and the length of the signal lines parallel (train length). Delay refers to the time difference between the transmission of a signal from sender to the receiver. Although the rate of signal transmission is very fast, with the increase of frequency, the requirement of delay becomes higher and higher. In the organic substrate, the dielectric constant is close to 4, and the signal transmission speed is about 1/2 of the speed of light; in the ceramic medium, the dielectric constant is close to 9, and the signal transmission speed is about 1/3 of the speed of light. In order to achieve equal delay, a group of signals are usually controlled by serpentine winding, as shown in Fig. 2.24. Although the speed of signal transmission seems very fast, if the time is very short, the distance of signal transmission is also very limited. For example, within 1 picosecond, the transmission distance of signal on organic substrate is 0.15 mm, while that on ceramic substrate is only 0.1 mm. If routing on a ceramic substrate, the length difference is 1 mm and the delay is 10 picoseconds. The same group of high-speed signals needs to keep the same delay as much as possible, so it is necessary to adopt the equal length strategy in routing. For the differential signal, the delay of N and P nets should also be consistent as much as possible. Fig. 2.23 Eye diagram of signal integrity
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Fig. 2.24 Time delay is controlled by serpentine winding
EMI/EMC, Electromagnetic interference (EMI) refers to the electromagnetic wave generated in the working process of electronic equipment, which will cause interference to other parts of the equipment or external equipment. Electromagnetic compatibility refers to the ability that the electromagnetic energy generated by the equipment does not interfere with other equipment and is not interfered by electromagnetic energy of other equipment. Generally, there is a strong correlation between EMI and signal integrity. For signals with good signal integrity, EMI index is usually better, and for signals with poor signal integrity, EMI index is also relatively poor. The research object of EMI/EMC is different from that of signal integrity. The research object of signal integrity is usually at the PCB or SiP substrate level, while the object of EMI/EMC is usually at the system or device level. 5.
Power and Ground
After learning about signal transmission, let’s take a look at Power and Ground. Power and Ground are also a kind of special signals, which usually appear in the form of plane layer and serve as the reference plane of signal. The return path of transmission line is usually the projection of the signal on reference plane. If the reference plane is not complete, the projection of the signal is cut off, and the return path has problems, the signal integrity problem will also occur. Power Integrity (PI) corresponds to Signal Integrity (SI). With the improvement of system complexity, the increase of power rail and the improvement of power requirements, the power plane is usually divided into many small pieces, so the concept of power integrity (PI) appears. PI research usually includes DC (Direct Current) analysis and AC (Alternating Current) analysis. DC analysis mainly studies the voltage drop and current density to ensure that the device can supply power normally. At the same time, the local part of the substrate should not have too much current density. It can be optimized by modifying the plane layer partition shape, adding vias and expand traces in layout. AC analysis mainly studies plane layer impedance, power supply ripple, plane layer noise and so on. It can be optimized by reasonable capacitance distribution, plane layer position and plane layer shape adjustment.
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Next, we summarize the interconnection of EM in SiP. The purpose of interconnection of EM in SiP is to transmit signals, and the key points are as follows: When we use a moving vehicle to compare to signal transmission, we should first plan the driving route (Net Optimization), and then smooth the road (impedance control routing), secondly, we should control the vehicle speed (reduce the signal rise time), and also consider the vehicle distance (to prevent crosstalk). During driving, we should not interfere with other vehicles or be interfered by other vehicles (EMI/EMC). If travel in groups, the distance between them should not be too large (control the delay difference of the same group of nets). In addition, we have to consider other factors, such as full fuel, full charge, weather and other environmental factors (stability of power supply, integrity of reference ground plane), only in such way can we successfully reach our destination (signal transmission is successful).
2.3.2 Interconnection of Thermo Interconnection of EM needs to focus on specific net or routing, while Interconnection of Thermo needs a more general perspective. In SiP design, Interconnection of Thermo is usually realized by selecting appropriate thermal conductive materials. In addition, sometimes it is necessary to design specific heat channels. There are three ways of heat transfer: conduction, convection and radiation. In SiP, the heat transfer mode is mainly conduction. In SiP, Bare Chip is the main heat source, in addition, the large current in the transmission process will also make the conductor heating, which is the secondary heat source. 1.
Heat Transfer Analogy
With regard to the heat transfer mode of SiP, we can imagine a spring flowing through the earth. The spring mouth is the heat source. Water flows from the spring mouth to all directions, and the water flows more easily to the low-lying places (with small thermal resistance). The ground water flowing through includes: cement ground, grassland, sand and etc. (representing different thermal conductivity layers). In some surface water flows fast (with small thermal resistance), some surface flows slow (with high thermal resistance), some can hold more water (with large heat capacity), and some can hold less water (with small heat capacity). Finally, the water will flow into the sea (with infinite heat capacity). See Fig. 2.25. 2.
Thermal Structure Function Curve
We can draw a curve representing heat resistance and heat capacity, called a thermal structure function curve. The transverse axis of the thermal structure function curve represents heat resistance, which is superimposed by the heat resistance of different layers, the vertical
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Fig. 2.25 Comparing heat transfer to spring water flowing through the earth
axis represents the heat capacity, which is added by the heat capacity of different layers. The curve starts from the active region of the bare chip and ends in the outer space. Because the heat resistance and heat capacity of different materials are different, the slope of the thermal structure function curve varies with the material. The inflection point on the curve is the boundary point of different materials. This feature can help us to analyze the defects in SiP or package structure. For example, the thermal structure function curve of a SiP deviates significantly from that of large sample, indicating that there are holes, poor contact or other defects in this layer of the SiP (Fig. 2.26). With thermal structure function curves, we can obtain the thermal resistance of Junction to Case for chips or SiP, and the thermal resistance of Junction to Air by specific test methods (the method of creating separation points of structural function curves manually). Interconnection of Thermo and heat transfer in SiP can be solved by effectively controlling the heat resistance and heat capacity of different material layers during heat transfer. There are usually multiple chips (heat sources) in SiP, so we can imagine Fig. 2.26 Thermal structure function curve
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Fig. 2.27 Dissipate heat through the special cooling channel
multiple springs that gush out together and flow across different types of ground. This is more complicated than heat transfer from a single source, but the theory is the same. 3.
Special Cooling Channel
There is also a case in SiP where the power consumption of individual chips is very large and a dedicated cooling channel is required, which allows a special cooling channel to be designed in the structure, as shown in Fig. 2.27 below. Die1 and Die2 chips consume a lot of power, ordinary cooling channels can’t solve the problem of heat loss, and so special cooling channels need to be designed for them. As shown in the figure, the chip is directly connected to the heat sink through a metal connector, which minimizes heat resistance and smoothly dissipates heat. Other chips can be designed in a conventional way. In the actual project, this design method has achieved good heat dissipation effect. Of course, its structure is complex and high cost. In addition, the airtightness of metal blocks and shells also requires special technology, so it should be used as appropriate. Interconnection of Thermo simply means that the heat emitted from the chip is transmitted to the external space in a timely and effective manner so as to reduce the temperature difference between the inside and outside of SiP and ensure that the chip junctions temperature do not exceed the specified temperature.
2.3.3 Interconnection of Force The interconnection of Force needs to consider both external and internal forces of SiP or package. For SiP design, the main focus of interconnection of Force is on the interface between different. devices or different materials. External forces mainly come from impact, vibration, acceleration and etc. Internal forces mainly come from relative distortion, which is mainly caused by the change of temperature. 1.
External Forces
First let’s look at the impact of External Force.
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When a mobile phone drops from height to the ground, the impact it is subjected to is transferred to the PCB and then to the SiP and its bare chips inside. When a car is on a bumpy road, the vibration received by the on-board electronic equipment is transferred to the PCB and then to the SiP and its internal chips; when a rocket or missile takes off from the launch pad, the acceleration generated is transferred to the PCB and then to the SiP and its internal chips. Due to the influence of the inertia of the object itself, when the impact, vibration and acceleration from outside act on SiP, it will produce distortion, and when the distortion exceeds the material’s bearing capacity, it will cause physical damage. For SiP, the most prone places to deformation are at the joints of different materials, such as bonding points, Bump of Flip Chip, pins of SiP package and etc. In addition, the ceramic or metal package is a cavity structure inside, and the bond wires are suspended in the middle and supported at both ends. It is also prone to deformation under the impact, vibration and acceleration. In order to cope with the impact of external forces on SiP, the following points are generally needed: First of all, the weight of SiP should not exceed the standard, the materials and sizes used for SiP should be strictly controlled. If the weight exceeds the standard, the structural reinforcement measures should be considered. Secondly, glue or welding materials used for fixing SiP internal devices also need to be tested to verify whether their strength can meet the requirements of impact, vibration and acceleration. In addition, the length and bending shape of the bond wire need to be strictly controlled to avoid the phenomenon of wire short due to shock and vibration. Generally, the maximum length of bond wire with different wire diameters is strictly regulated. If the length of the bond wire exceeds the limit, it is easy to be deformed or broken by the flow impact of the plastic gel in the plastic sealing process. In the ceramic or metal packaging, it will cause the collapse of the bond wire or the collision of the wires with each other during severe vibration, which will cause short circuit. Also, the type of SiP pin should take full account of its bearing capacity. The heavier SiP, need the stronger pin to support and fix. For example, for SiP with large weight and size, PGA is usually used to mount on PCB board. Surface mounting such as BGA or CGA needs careful consideration due to the limited bearing capacity of PCB surface. 2.
Internal Force
Internal Force mainly comes from relative deformation. Almost all materials have the characteristics of heat rise and cold shrink, but the degree of different materials is different. CTE (Coefficient of Thermal Expansion) is a parameter used to describe the change of length caused by the change of unit temperature. When different materials of CTE are combined, they will be deformed relative to each other due to the change of temperature. In addition, different parts in SiP will also have different deformations due to different temperatures themselves, resulting in mutual forces. For example, the device
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heats causing expansion, while the mounting substrate does not heat up, resulting in larger relative dimensions of the device, resulting in thermal stress and distortion at the pin. In addition, it should be noted that temperature changes are usually repeated and long-term, even if physical deformation in the short term does not damage the device, and long-term fatigue deformation can cause damage to the device, so enough allowance should be considered in the design. Relative distortion due to heat is common within SiP. Therefore, for the interface between the chip and the substrate, interposer, solder bumps, etc. are important considerations. At the same time, it should be considered that SiP itself and the PCB board installed will also distort the SiP pin due to the difference of CTE, resulting in stress. Chips that are electrically connected by bond wires are usually fixed on SiP substrate by glue or solder. Rigorous thermal shock and thermal cycling tests are required for the fixed glue or solder used. For Flip Chip, Underfill is required at the bottom of the Flip Chip in order to buffer stress concentration. Outside SiP, the distortion of the pin of SiP and the contact point of the PCB is a key consideration. There is a pin type selection problem here, for example, QFN sizes are usually small, LCC sizes can be slightly larger, and QFP can be larger, because the relative distortion sizes that different pin types can withstand are different. Therefore, when choosing the type of SiP package, fully consider the deformability that different types of pins can withstand. Generally speaking, the larger the package size, the stronger the pin will have to withstand the distortion. Figure 2.28 compares the QFN pins with QFP pins. It can be seen that the QFP pins can withstand large deformations, so QFP can be used on larger packages, while QFN pins can only be used on smaller packages because of their limited ability to withstand deformations. The chips in SiP are fixed on substrate by glue (bond wire chip) or Bump (Flip Chip), and the SiP itself is fixed on PCB board by pins. We can imagine Interconnection of Force as if the pins of chips or the pins of SiP were fixed and could not be moved, as if our feet were standing on the sticky ground. If pulled by external forces (such as someone pushing you or pulling you), our legs and body.
Fig. 2.28 QFN and QFP package
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can withstand certain deformations, but if the external forces are too large, our feet may get detached from the shoes (pins separate from the substrate). So, in addition to shoe strength (pin strength), shoelace should be well fastened (weld strength), and there is a certain degree of distortion that our legs and bodies are subject to (the ability of the parts and pins to withstand distortion), too much distortion or force, even sturdy shoes will also fall off (pin shedding).
2.3.4 Summary of Interconnection For a SiP, interconnection can be divided into three main areas: • interconnection of EM • interconnection of Thermo • interconnection of Force Here, each kind of interconnection is very important and a key factor in SiP’s success. Let’s summarize it in visual language. For interconnections in SiP: • Electricity, such as busy traffic in a city, all-round access; • Thermo, like springs overflowing the earth, fast or slow; • Force, ike the feet on sticky mud, stand and don’t move. Finally, it is important to note that: Integration is the foundation of SiP technology development, and interconnection is the hinge of SiP technology. Later, we will continue to discuss the intelligence in Si3 P, which is also the essence of SiP technology.
2.4 Intelligence of Si3 P In this section, we give a detailed interpretation of intelligence in Si3 P. Intelligence is usually regarded as the general term of intellect and ability. The process from sensation to thinking to memory is called intellect, which results in behavior and language, and the process of expression of behavior and language is called ability. Both are called intelligence. The whole process of feeling, thinking, memory, behavior and language is called intelligent process, which is the expression of intellect and ability. Referring to the two pictures below, we can understand the relationship between intelligence (intellect + ability) and “Intelligent System”. Intellect contains sense, thought and memory that correspond to sensor, processor and memorizer of Intelligent System (Fig 2.29).
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Fig. 2.29 Correspondence between intellect and Intelligent system
Fig. 2.30 Correspondence between ability and intelligent systems
Ability contain behavior and language that correspond to the “hardware execution” and “software execution” of Intelligent Systems, for short as hardware and software (Fig. 2.30). Described in computer language: Intellect emphasizes [input + operation + storage], while Ability emphasizes [execution + output]. For SiP, a reasonable structure system, a reliable system and a fully functional system are the purposes of our design. For SiP, structure can focus on integration (2D, 3D), reliability can focus on interconnection (EM, Thermo, Force), and functional is the intelligence we discuss now. Below, we discuss the functional completeness and intelligence of SiP in four aspects:
2.4.1 System Function Definition 1.
Input + Operation + Storage; Execute + Output
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As we have described earlier, for an intelligent system, it needs to include input, operation, storage, execution, and output. SiP can be used as a stand-alone intelligent system or as part of an intelligent system. In many cases, SiP is not designed to be a complete intelligent system itself, but needs to work with other systems to become a complete intelligent system. As a part of intelligent system, with the increasing demand for intelligence, SiP also needs to have intelligent elements, from the perspective of intelligence to consider the development and design of SiP. If a SiP is to become a complete intelligent system, it needs to include input, operation, storage, execution, output and other units. Such SiP needs to be equipped with sensor, CPU, memory, actuator, output interface and software, so as to become a real intelligent system. 2.
Reasonable Tailoring of Functions
If multiple SiPs work together to form a complete intelligent system, such as SiP including various sensors, SiP including CPU + memory, SiP including video and audio output unit, etc., all these SiPs can be combined to form an intelligent system. Today’s smartphones are integrated with multiple SiPs, which work with each other and become intelligent systems with other units. SiP usually does not deal with the end customer directly, so the intelligence of SiP is mainly embodied in being an intelligent unit and becoming an integral part of the intelligent system. When designing a SiP, according to its actual use, we should not only consider the completeness and intelligence of its functions, but also consider the risks brought about by the complexity of the system, so as to cut its functions reasonably. Multiple SiPs constitute a complete intelligent system. 3.
Resolve Compatibility Issues
Compatibility is a key consideration in SiP design. From the selection of processor model to the definition of package pin function, as well as the selection of package type, compatibility should be considered. As a part of intelligent system, SiP needs to work with other units. In addition, SiP with good compatibility will make its users more efficient and it will also be more acceptable to the market.
2.4.2 Product Application Scenario In the research and development of SiP products, the needs of product application scenarios and application environments should be fully considered, and corresponding strategies should be adopted in the design. For example, the SiP used in deep space exploration spacecraft or satellites needs to consider the reliability in space environment. In addition to adopting the chip with good radiation performance, we also need to adopt design methods such as three
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mode redundancy in the design. In addition, due to the long distance of deep space exploration, it is unable to communicate with the earth in time, so the system needs to be strong enough to make decisions independently in case of emergency. If SiP is used as the main control computer, the design needs a strong enough processor to make independent decisions. If a SiP is applied in a smart phone, its design idea will be completely different. In addition to powerful functions to meet the various app requirements of smart phones, low power consumption design should be considered to make the mobile phone have longer stand-by time. If a SiP is used in intelligent car, its requirements will also be different. Therefore, the design ideas also need to be adjusted accordingly.
2.4.3 Testing and Debugging In general, testing is to find potential problems, debugging is to find ways to solve the problems that have been found. The testing and debugging time of a SiP may account for more than half of its development time. There are many kinds of tests, including function test, performance test, mechanical strength test, thermal shock test, sweep vibration test, constant acceleration test, etc., as well as aging test, ESD test, anti-radiation test, etc. the relevant test items are arranged reasonably according to the application scenarios of the products mentioned above. Debugging is to solve or confirm the problems that have been found by simulating the actual working environment, and changing the hardware and software configuration and working state. For the problems that cannot be solved by debugging, we need to redesign. When defining the channel of SiP to external communication. In addition to meeting the functional requirements of normal operation, it also needs to meet the requirements of testing, debugging and problem analysis. In the definition of SiP package pins, it is necessary to reserve channels for testing and debugging, so as to find potential problems and analyze subsequent problems. The function test and performance test of SiP are usually divided into machine test and board level test. Machine test is generally used to test the electrical parameters of SiP under different working conditions, that is, to meet different functional requirements. For example, the current value and voltage value of different nets under different working modes, usually include normal temperature test (25 °C), low temperature test (–40 °C, –55 °C), high temperature test (85 °C, 125 °C). Different low temperature and high temperature are defined according to different use environment.
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Board level test: various functions and performances of SiP are tested by simulating the actual working condition. In order to test fully, we need to write corresponding test cases, and also need to test at room temperature, low temperature and high temperature.
2.4.4 Software and Algorithm Software and hardware are two parts of an electronic system that depend on each other. In SiP system, both are indispensable. The relationship between software and hardware is mainly reflected in the following three aspects. (1)
(2)
(3)
Software and hardware depend on each other. Hardware is the material basis of software work, and the normal work of software is the way for hardware to play a role. There is no strict boundary between hardware and software. In many cases, some functions of the system can be realized either by hardware or by software. Therefore, in a certain sense, there is no absolute strict boundary between software and hardware. Hardware and software develop together. Software develops with the development of hardware technology, and the continuous development and improvement of software promote the update of hardware. Both of them are interwoven and indispensable.
From the relationship between software and hardware, we can see the importance of software for the system. Without software, SiP can’t achieve its normal function, and its intelligence is even a castles in the air. Generally, the software related to SiP R & D process and product application includes the following types of software: 1.
Testing Software
The test excitation and device model are written by Verilog or VHDL language, and then transformed into *. VCD file (waveform file) by simulation tool, and imported into test machine as test vector. Test vector is the data of logic 1 and logic 0 that act on the device pins for test or operation in each clock cycle. Logic 1 and logic 0 are represented by waveforms with timing characteristics and level characteristics, and are related to waveform shape, pulse width, pulse edge or slope, as well as the position of rising edge and falling edge (Fig. 2.31). According to the characteristics and functions of DUT (Device Under Test), test vectors are provided by the machine, including input to the DUT to test excitation and expected response. The output response of DUT is compared with the expected response, so as to judge whether the DUT is qualified.
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Fig. 2.31 Test vector waveform
Figure 2.32 below shows the basic principle of the machine test. The machine simulates the actual working state of DUT, inputs a series of orderly test waveforms, acts on the device under test at the specified speed of the circuit, and then detects whether the output signal is consistent with the expected figure at the circuit output end, so as to judge whether the DUT function is correct. Board level test software: board level test software is related to the actual working state of SiP. It tests various functions and performances of SiP by simulating the actual working condition. In order to test fully, we need to write corresponding test cases, and also need to test various functions at room temperature, low temperature and high temperature. In order to improve the test efficiency, the board level test software needs to be able to measure multiple SiP at the same time, which is different from the actual working state of SiP.
Fig. 2.32 The principle of machine test
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System Software
System software refers to the system that controls and coordinates SiP system and external equipment and supports the development and operation of application software. It can schedule, monitor and maintain the whole SiP system without user intervention. System software is responsible for managing various independent modules in SiP system to make them work in coordination. The system software enables users to treat SiP as a whole without considering how each hardware unit in the underlying layer works. For example, windows operating system on computer, IOS and Android on mobile phone, VX Works operating system in embedded system all belong to system software. 3.
Application Software
Application software is to solve different problems and meet different application requirements. It can expand the application field of SiP system and enlarge the function of hardware. Application software is a collection of application programs written in a variety of programming languages. It is a program designed to solve certain problems. For example, Office software, EDA design software, simulation software, image processing. software, etc., all kinds of APP in mobile phone such as WeChat, maps, music, news, Alipay all these belong to application software. Application software is usually developed according to specific task requirements, such as monitoring the signal transmitted by a certain sensor for analysis, and performing corresponding tasks, such as step number monitoring, heart rate monitoring, etc. The intelligence of the system needs to be realized and interacted with users through a variety of application software. 4.
Algorithm
Algorithm is the soul of software. There are many kinds of algorithms to implement a specific function of software. The quality of software depends on the quality of algorithm. For example, there are different algorithms in the automatic router of EDA tools. Designers can choose different algorithms to get different routing results. A good algorithm of EDA tool can improve the routing rate, improve the routing effect, ensure the quality of signal transmission. For simulation software, the same problem, different software using different algorithms will get different results, the advantages and disadvantages of the algorithm will affect the simulation speed, simulation accuracy and so on. Therefore, a good algorithm will not only affect the running results of the software, but also affect the execution effect of the whole system.
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Fig. 2.33 Related contents of SiP intelligence
2.4.5 Summary of Intelligence In this section, we describe the intelligence of SiP from four aspects: (1) system function definition, (2) product application scenario, (3) testing and debugging, (4) software and algorithm, and each aspect is classified and explained, as shown in Fig. 2.33. Here, the author would like to emphasize that intelligence is the purpose of system realization, so is SiP.
2.5 Summary of Si3 P 2.5.1 History Review of Integration In the year 1936, the first PCB in human history was born. 11 years later (1947), the world’s first electronic package came out, and 11 years later (1958), the first Integrated Circuit appeared on the earth. The purpose of PCB and IC is to integrate more function units together. The integration on PCB is to route in substrate first and then install the components. IC integration is to make components on silicon substrate first, and then route and interconnect. Package, on the other hand, is designed to protect chips, scale-up, and electrical connections. It has no concept of integration at start. With the development of technology, the integration of PCB and IC is higher and higher, the density is more and more, and the function units are more and more. At this
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time, the main functions of package still have not changed, but with the improvement of IC complexity, it has gradually developed from TO, DIP and other types to QFP, LCC and etc. surface mount types, as well as BGA and CGA of pin array. Package pin density is also increasing, which greatly promotes the improvement of PCB integration. To integrate a system on IC is called SoC (System on Chip), and to integrate a system on PCB we can call it SoP (System on PCB). However, there is still no trend of integration in traditional package. In another field of HIC (Hybrid Integrated Circuits) technology, MCM (Multichip Modules) have been gradually developed. HIC includes thick film integration and thin film integration. At this time integration has gradually begun in package, which has been about 40 years passed since the first electronic package came out. MCM is mostly used in analog and radio frequency fields. It is mainly in metal package, which has no intersection with traditional large-scale digital circuit package, while the latter is mostly plastic package and ceramic package. After another 20 years, by 2007, the density of package has gradually increased, the pin array has become larger and larger, and SoC and PCB are also continuing to develop. The integration in package is limited to MCM, and it is mostly used in HIC field. When MCM needs larger scale and more functions, the original concept is no longer applicable, SiP is finally born and with unique skill: 3D integration technology. Figure 2.34 shows the history of electronic technology integration. With the advancement of technology, the integration on IC has gradually reached the limit of physical scale, Moore’s law will come to an end, and the integration on PCB has also developed to a certain extent, and the progress is slow. SiP, which has the advantage of 3D integration, has become a hot topic and a key technology in the post Moore law era.
Fig. 2.34 The integration history of PCB, package and IC
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From system vendors (Apple, Huawei, etc.) to OSAT (Amkor, ASE, etc.) to foundry (TSMC, Intel, etc.), they all begin to pay attention to and actively apply SiP. In SiP, new packaging forms emerge in endlessly, and new integration methods emerge constantly. From 2D to 2.5D to 3D, people focus on integration technology.
2.5.2 Associative Metaphor The author has been engaged in SiP technology for more than 15 years and has participated in more than 40 SiP projects in China, deeply understands that SiP is the system first, then the package. Integration is the foundation of SiP. The foundation is very important of course. Without foundation, everything else is a castle in the air. However, our cognition can’t always stay in the basic stage, we should understand SiP technology from a more comprehensive perspective. Therefore, the author puts forward the concept of Si3 P, in which i3 represents three words, integration, interconnection and intelligence, which are all starting with i. For SiP, integration is the foundation, interconnection is the hinge, and intelligence is the purpose. Here, let me make an associative metaphor. Integration is like building houses, interconnection is like building roads, and intelligence is like persons. For houses, we can build bungalows (2D integration) or high-rise buildings (3D Integration). For roads we can build ordinary roads, high-speed highways, and highspeed railways. The higher the running speed, the higher the requirements for the smoothness of the route (impedance continuity). In addition, we should reasonably consider the terrain, so that water (heat) can be discharged smoothly. Finally, the appearance of human beings endows the system with functions and intelligence. Integration focuses on physical structure; interconnection focuses on energy transfer; intelligence focuses on function application (Fig. 2.35).
2.5.3 Prospect Forecast About 40 years after it came into being, package began to go on the road of integration. Although it does not focus on integration from start, it later mastered the unique skill of 3D Integration and successfully turned from package to SiP system in package. PCB and IC are on the road of integration from the beginning. So far, they have been developed sufficiently. And with the influence of dimension, too small for IC, too big for PCB, the space for further integration development is limited for them. SiP technology has a short time on the road of integration. With the support of new technology such as 2.5D TSV and 3D TSV technology, there is still a lot of room for its development.
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Fig. 2.35 Summary of Si3 P concept
Therefore, SiP will become the most promising and fastest developing technology in electronic system integration. The following picture can help us understand Si3 P (Fig. 2.36). After the emergence of SiP technology, the definition of MicroSystem has changed. SiP is an important carrier for the realization of MicroSystem. The system implemented in SiP can also be called MicroSystem.
Fig. 2.36 Understanding the concept of Si3 P
Chapter 3
SiP and MicroSystem Suny Li
3.1 SiP Technology 3.1.1 Definition of SiP Technology SiP (System in Package) technology takes several active electronic components with different functions, usually bare chips of integrated circuits, and optional passive devices, such as resistors, capacitors, inductors, etc. as well as other devices such as MEMS (Micro Electro Mechanical Systems) or optical devices, into a single standard packaging device to achieve certain functions, forming a system or subsystem, Which is often referred to as a MicroSystem. In terms of system architecture, SiP integrates various functions of bare chip, including processor, memory, I/O interface, FPGA and other chips in one package, so as to realize a basically complete system function. SiP is corresponding to SoC (System on Chip). Both of them can be called MicroSystem, but they are different in implementation mode and scope, as shown in Fig. (3.1). SoC, also known as system-level chip, are integrated circuits that accomplish specific goals independently on a single silicon chip, which contain a complete system and the contents of embedded software. In a narrow sense, SoC is a chip integration of multiple information systems, which integrates the key components of the system on a single silicon chip. Broadly speaking, SoC is a MicroSystem. If the central processing unit (CPU) is the brain, then SoC is a MicroSystem that includes the brain, heart, eyes and hands. SoC is generally defined as a product that integrates a central processor, an analog IP core, a digital IP core, a memory or an off-chip storage control interface on a single silicon chip. S. Li (B) Beijing, China e-mail: [email protected] © Publishing House of Electronics Industry 2022 S. Li (ed.), MicroSystem Based on SiP Technology, https://doi.org/10.1007/978-981-19-0083-9_3
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Fig. 3.1 SiP corresponds to SoC
SoC is a standard product customized by customers for a specific purpose. SoC is also a technology used to implement the whole process from determining the system functions to the division of hardware and software, and to complete the design. It can be said that SiP and SoC are both MicroSystem that can achieve the same or similar functions, but the scope of their implementation is different. SoC implements the functions of the system on a single silicon chip, or in the process of manufacturing on a wafer. SiP is implemented in a single package, or in the process of packaging and testing. In addition, SiP can be integrated in 2D, 2.5D, 3D or even 4D for different bare chips on the package substrates, interconnected through trace and via on the substrates, and finally encapsulated in an package body. SoC, on the same silicon chip, integrates different functional units into the same chip plane in 2D, and interconnects through trace and via on silicon wafer to form highly integrated chip products. On the basis of SiP or SoC technology, MicroSystem can be realized, so they are both carriers of MicroSystem.
3.1.2 SiP and Related Technologies 1.
SiP Has Received Many Attentions
SiP technology is becoming a hotspot in the development of electronic technology. It has received many attentions from traditional packaging designers, traditional MCM designers, traditional PCB designers, and SoC designers. Compared with traditional Package, SiP is a system-level multi-chip package that can perform independent system functions. Package itself has no concept of integration, but in SiP integration can be fulfilled in many ways. Compared with MCM, SiP is a 3D multi-chip package, whose 3D is mainly reflected in the stacking of chips and the cavity of substrate. At the same time, the size of the chip and the function that SiP can accomplish are also greatly improved than MCM.
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For designers of traditional Packages and MCMs, SiP enhances the functionality and performance of the product, making the Package and MCM products more adaptable. Compared with PCB, the advantages of SiP technology are mainly reflected in its miniaturization, low power consumption and high performance. To achieve the same functions as PCB, SiP only needs about 10–20% of the PCB area and 40% of the power consumption, and the performance will also be greatly improved. Compared with PCB, SiP has better high frequency characteristics because of its smaller area and shorter interconnection. At the same time, due to the short interconnection, less energy is consumed in the transmission line, which also saves power consumption to a certain extent and achieves the effect of reducing power consumption, especially in high-speed circuit design. For traditional PCB designers, besides the development of high performance, high speed and multi-function, another important development direction of PCB systems is high density, small size and low power consumption. Compared with SOC, the advantages of SiP technology are mainly reflected in short cycle, low cost and easy success. To achieve the same function, SiP only needs 10–20% of SoC development time, 10–15% of cost, and is more likely to succeed. As a result, SiP is used as a low-cost, short-term alternative to SoC construction by many industry users. SiP can be used as a pioneer to make products quickly and cheaply at the beginning of SoC projects. When SiP has achieved some stage results in the project, it is recognized and supported by many parties, and then the focus is on SoC research and development. In addition, there is no direct conflict and competition between SoC and SiP. SoC product which design development is completed can also be used in SiP projects. SiP is the crystallization of knowledge, technology and methods in IC industry chain, which blends with each other, penetrates into and integrates applications. It maximizes the flexibility of applying various chip resources and the advantages of packaging interconnection. SiP technology can optimize the system performance to the maximum extent, shorten the development cycle, avoid duplicate packaging, reduce costs and improve the integration degree, improve the system function density, master SiP technology is the key to the mainstream packaging field in the future (Fig. 3.2). At present, the output value of packaging and testing in the world is not high. When SiP technology is mastered by packaging enterprises or more, the industrial pattern will start to adjust. There will be a leap-forward development in the packaging industry. There is no doubt that SiP technology will face greater opportunities and challenges, but also gestate a broader development space. SiP technology is the focus of research at home and abroad in recent years, and is an important means of miniaturization of electronic systems. SiP can achieve 3D system-level packaging through traditional micro-assembly technology, which can be achieved by chip stacking, substrate stacking, package stacking, etc. Therefore, a variety of advanced packaging technologies have been derived, which can be referred to in Chaps. 4 and 5 of this book.
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Fig. 3.2 SiP has received many attentions
2.
Hierarchical Relationship Between SiP and Related Technologies
As mentioned earlier, SoC product design can be used in SiP projects after development, so there is no direct conflict between them. SiP will not replace SoC. Similarly, SiP product design can be used in PCB projects after development, so there is no direct conflict between them, and SiP will not replace PCB. From SoC to SiP to PCB is a hierarchical relationship, which can be divided into three levels. The first level is Chip Level and contains many types of Bare Die, such as SoC, FPGA, Chiplet, etc. The second level is Package Level, which contains many types of Packages such as SiP, MCM, PoP, PiP, AiP, etc. The third level is Board Level, which includes PCB, FPC (Flex Print Circuit), Rigid-Flex, and many other types of boards. See Fig. 3.3, the hierarchical relationship between SiP and related technologies. Traditionally, these three levels are typically accomplished in different roles. For the first level of Chip Level, chip manufacturers are generally responsible for the design and production, including chip design Fabless, wafer Foundry, and so on. For the second level of Package Level, there are specialized packaging vendors such as OSAT (Outsourced Semiconductor Assembly and Test) responsible for packaging and testing; For the third level of Board Level, the system manufacturer is responsible for design, production and testing, such as mobile phone and laptop manufacturers. Usually, there is a clear division of labor at three levels, which has changed since the advent of SiP technology. The change brought by the development of SiP technology is that packaging and testing traditionally considered by chip manufacturer or OSAT are gradually transformed into system manufacturer, which proposing packaging requirements, choosing packaging forms, designing and then commissioning OSAT for packaging
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Fig. 3.3 Hierarchical relationship between SiP and related technologies
and testing, or directly bringing requirements to OSAT or Foundry for design and production. In the past, chips manufacturers usually entrusted OSAT to package the chips before delivering them to end users. Figure 3.4 shows the traditional model and the new collaboration model brought about by the development of SiP technology. Now, with the rapid development of SiP technology, based on the design requirements of miniaturization, low power consumption and high performance, more and more system users want to obtain bare chips, and design, package and test the system on the basis of bare chips. As a result, the demand for bare chips on the market will increase dramatically, and more and more system designers are consulting on how to obtain bare chips through various channels. With this growing demand, traditional chip agents will continue to expand their bare chip business to meet the growing demand of the market. In cases where demand does not reach a certain level, bare chips are usually ordered from IC manufacturers, which can lead to some time delay. Therefore, for SiP designers,
Fig. 3.4 Traditional mode and new mode brought by SiP technology
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at the beginning of the design, full consideration should be given to the ordering channel and ordering cycle. When the market demand reaches a certain level and there is a sustained demand, bare chip agents will consider increasing their inventory to meet user needs from time to time. The maturity of bare chip market is driven by the rapid development of SiP technology. In turn, the development of bare chip market will promote the rapid application and popularization of SiP technology. Since the design of SiP will gradually shift from IC chip manufacturer to system user, and system user is most concerned with the system design, the collaboration between package design and system design will become more and more important. Package design itself will also become an important part of system design, and the whole system needs to be implemented under a unified platform.
3.1.3 SiP or SOP? SiP is short for System in Package and SOP is short for System On Package. SiP has become an internationally recognized standard way of writing. In addition, some people call the concept of system-level package SOP. What is the relationship between SOP and SiP? Which name is more accurate? First of all, we analyze the meaning of Package. Our understanding of package is internal and external, not top and bottom. Therefore, it is more precise to combine package with in. In addition, no matter from the earliest TO package, DIP package, to the current mainstream BGA, CSP package, chips are usually wrapped up, located inside the package, SiP is essentially a package category. Therefore, from this point of view, “in” is more reasonable. See Fig. 3.5. Therefore, in this book, we use SiP as the name of system-level package because it more accurately describes the meaning of system-level package. Is SOP useless? No, we can use SOP (SoP) to refer to System on PCB, or System on Board (SoB), which is more accurate because the board level is also a system with a larger concept and scale range than SiP. Fig. 3.5 The meaning of “in” of SiP is more accurate
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In this way, from SoC to SiP to SoP (SoB), they represent three different system levels, namely, Chip Level, Package Level and PCB\Board Level. It is important to note that no matter SiP, SoC or SoP (SoB), the middle letter should be lowercase. This first conforms to English writing habits, prepositions usually appear in lowercase in acronyms. In addition, SIP with middle I in upper case has another meaning. SIP (Session Initiation Protocol) is a multimedia communication protocol developed by IETF (Internet Engineering Task Force). So we shouldn’t confuse the two. In addition, the Standard Writing Method for SiP has System in Package with no hyphens and System-in-Package with hyphens. Both are currently available at home and abroad because they do not cause any ambiguity and we can assume that both are standard.
3.1.4 Application Fields of SiP Technology In the world, SiP technology is widely used in aerospace, military industry, wireless communication, sensors, computers and networks. The application of SiP technology in modern products mainly includes the following four areas. 1.
Application of SiP in Mobile Phone
Mobile phones are the closest companion of modern people, and almost everyone cannot do without smartphones. The most representative application of SiP is in mobile phones. At present, almost all mobile phone manufacturers from Apple to Samsung, Huawei, Xiaomi, OPPO are actively using SiP technology, with no exception. Smartphones have been developing in the direction of lighter body and more powerful function. Besides optimizing the whole structure, it is more necessary to make articles from the core components—chips, especially those with higher integration. SiP packaging has become an inevitable solution. Figure 3.6 shows Apple smartphones with multiple SiP inside. The development trend of mobile phone is to achieve modular design, which first integrates the parts of mobile phone into different functional modules, then gradually integrates the functions of mobile phone. In mobile phones, baseband modules are generally integrated using SiP technology, including baseband processors, SRAM, LPDDR, Flash, and some passive components. Reduce area by stacking chips. Depending on the heat distribution and routing, stack 2–3 chips. This solution can transfer the routing of most systems to the SiP board, reduce OEM manufacturers’ technical requirements for assembly, reduce the complexity of PCB, reduce PCB costs, and minimize the size of mobile phone PCB motherboard. Smartphones are currently SiP largest application market, and not limited to highend mobile phones, because SiP technology itself does not increase costs. Instead, compared to traditional package, SiP technology makes PCB assembly simpler,
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Fig. 3.6 Apple smartphones with multiple SiP inside
significantly reduces the cost spent on chip packaging, thereby reducing the overall BOM cost of mobile phones, whether it is high-end iPhone 12, Huawei Mate series, or Low-end cell phones all use SiP technology. In smartphones, the most common application of SiP is on the integration of CPU processor and DDR memory. For example, Apple A13 processor + Samsung LPDDR memory, Huawei Kirin 950 processor + Micron LPDDR memory, etc. These are all SiP that encapsulate processors and memory together. Others such as touch-control chips, fingerprint recognition chips, RF front-end chips are also starting to use SiP technology. In addition, SiP has special significance for 5Gmm-wave technology. Currently, the biggest challenges faced by 5Gmm-wave technology are power consumption control of the chip and high-speed signal transmission line effect. Millimeter-wave technology requires higher density chip integration to minimize signal path and maintain loss control. SiP has the characteristics of miniaturization, low power consumption and high performance, which can effectively reduce the package volume, help to reduce chip power consumption and reduce transmission line effect, so it will be more widely used in 5G network. Currently, smartphone chips are mainly concentrated in Qualcomm, MTK, Apple, Samsung, HiSilicon, and so on. These chips manufacturers have generally adopted SiP technology. 2.
Application of SiP in Wearable Devices and Sensors
SiP technology brings the advantages of product size reduction, cost reduction and simple assembly. A large proportion of wearable devices are using SiP technology,
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Fig. 3.7 Smart watches and its sensors
coupled with the strong driving force of Apple Watch, SiP has started to popularize wearable products and smart sensors all over the line. General wearable devices include: smart watches, smart wristband, headset monitors, smart glasses, smart clothes, bags, accessories, etc. How to improve the convenience and functionality of wearable devices is the key to determine the future market development of wearable devices. This also raises higher requirements for the development of wearable devices and related technologies, especially in the smart sensor, which is the core component of wearable devices (Fig. 3.7). Smart sensors and wearable devices complement each other. Depending on the product, smart sensors play different roles in wearable devices. Generally speaking, the highly integrated and diverse measurement of sensors can integrate more monitoring functions for wearable devices; the development and application of new materials for sensors, the development of flexible wearable sensors can improve the wearability of wearable devices; and the reduction of power consumption of sensors can also improve the wearable device’s durability. The volume, quality, power consumption, reliability and stability of the sensor have an important impact on the user experience, wearing comfort and power consumption of wearable devices. On the other hand, wearable devices also put forward higher requirements for sensor development. For the convenience of wearable device requirements, it requires higher for signal collection and chip fusion of sensors in the device, especially in performance, power consumption, volume and so on, which are very different from traditional devices. First, highly integrated and diversified measurements. With the increasing functionality of wearable devices, more sensors need to be integrated, but the size of wearable devices is limited. How to increase the sensor while keeping the volume constant? This requires a highly integrated sensor. Secondly, reduce the power consumption of the sensor and increase the endurance. The key technologies to improve product durability and low energy products are to improve battery energy density and environmental energy acquisition. However,
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before new breakthroughs in battery technology are made, wearable devices can only increase their endurance by reducing sensor power consumption, etc. In addition, in order to improve the user experience, there are strict requirements on sensor sensitivity, response time and performance improvement. The three problems above of sensors are well solved by the miniaturization, low power consumption and high performance of SiP technology. In addition, more and more portable electronic products, such as mobile phones, navigators, and digital cameras, are basically integrated with sensors. For example, fingerprint recognition sensors, CMOS imaging sensitive devices, MicroSystem sensors, and so on. The small size, low cost and easy integration of SiP in these applications are critical to the success of the sensor. Currently, better CMOS imaging sensors can reach tens of millions of pixels on a single sensor chip. To reduce the size of the CMOS imaging sensor and the cost, it is necessary to simply insert the camera module directly into the PCB motherboard. SiP technology enables the lens to be integrated into a standard package, enabling precise alignment and installation between the sensor chip and the lens, and simplifying the adjustment of the lens focal length. In addition, the driver IC and other passive components can be mounted on the bottom of the SiP board together, and an additional flexible connector can be easily mounted on the PCB board. 3.
Application of SiP in Computer and Internet
In many applications of computers and the Internet, the integration of microprocessor ASIC and memory is required. These high-speed digital devices are generally integrated using SiP technology. In packet switching applications of Internet routers, there are usually large ASIC devices that need to communicate with up to 8–16 SDRAM devices. According to the traditional design method, ASIC is encapsulated in its own BGA package. Memories are usually encapsulated in standard TSOP package, which are placed on the PCB motherboard together around the ASIC. In addition, about hundreds of passive devices are also installed on the PCB motherboard to form a complete subsystem. This solution takes up a considerable amount of motherboard area. At the same time, the signal integrity of the whole subsystem, the communication time sequence between memory and ASIC, etc. need to be solved in the motherboard design phase. As the complexity of the system increases, the complexity and cost of the motherboard become more and more difficult to control. In this case, the ASIC is mounted on the SiP substrate using Flip Chip method, the memory is encapsulated by FBGA (Fine-Pitch Ball Grid Array) or CSP, and then the memory is placed on the SiP substrate around the ASIC using conventional SMT technology. Decoupling capacitors and other passive devices are also placed on SiP substrate. Since the connection between ASIC and memory is solved on SiP substrate, the complexity of PCB motherboard is significantly reduced, the number of conductive layers is reduced, and the cost of motherboard is significantly reduced.
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In addition, as a single function module, SiP can be conveniently placed in other PCBs or the whole system in a series of products, which improves the reusability of the system. 4.
Application of SiP in Aerospace and Military Industry
Thanks to the miniaturization, low power consumption and high performance of SiP, NASA and ESA have used SiP technology for many years and used SiP technology in high-end products. Currently, leading research institutes in the field of aerospace and related industry are actively applying SiP technology. Aerospace technology has a high requirement for miniaturization, low power consumption and high performance, which also provides a useful place for SiP technology (Fig. 3.8). SiP technology can not only greatly reduce the volume of electronic products, but also greatly improve the performance of products, and reduce the power consumption to a certain extent of electronic products. SiP technology applied in high-speed digital products can improve the performance of the system. With the increase of the switching speed and the decrease of the voltage in the core area of the chip, noise becomes the main limiting factor of the device performance. It is no longer helpful to place passive devices on PCB motherboards to solve signal integrity problems by traditional methods. For SiP packages with standard wire bonding, decoupling capacitors or terminal resistors can be added to the standard BGA packages to improve device performance and reduce ground rebound, thereby reducing the bit error rate. System designers are able to install a complete subsystem, including a set of chips, plus all other passive components in a single SiP. The use of one SiP package instead of all other individual packages reduces the size of the system, saves the total cost of the system, and improves system performance.
Fig. 3.8 The high requirements of aerospace provide a useful place for SiP Technology
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In SiP, advanced interconnection technology enables stacked chips. For example, an electronic subsystem has a chipset consisting of four chips and about ten passive components. This complete subsystem can be completely installed in SiP package with a side length of 35 mm. If multiple chips are stacked together, a further 25 mm edge-length SiP package can be used. This not only reduces the cost, but also reduces the area of the motherboard occupied, reducing the volume of the entire system. 5.
Summary of SiP applications
In summary, as one of the current advanced packaging technologies, SiP benefits a wide range of chip and system manufacturers due to its advantages in miniaturization, low power consumption, high performance and low cost, especially in the design of highly demanding solutions for lightweight design. In the high-tech fields such as smartphones, wearable devices and sensors, computers and the Internet, aerospace and related fields, SiP technology is getting more and more attention. Why is SiP technology getting more and more attention? In contrast, if the chips are encapsulated separately, they will occupy a large amount of PCB installation space. SiP three-dimensional packaging technology can effectively reduce the package area, improve the utilization of the substrate, and effectively improve the function density of the system. In addition, packaging the chips together in a single SiP can also help to improve the transmission quality of high-speed signals between chips. SiP technology itself mostly uses mature packaging technology, so the risk is relatively small. The key is to propose and apply solutions to improve SiP, which requires the cooperation of chip manufacturers, packaging manufacturers and system manufacturers. With the increasing demand for SiP for OASTs, there are three main requirements to win customers: (1) (2)
(3)
The first is to master the latest new SiP packaging technology, which can be learned from the mergers and acquisitions of some OSATs; Second, to coordinate resources, such as a SiP solution designed and produced for Huawei smartphones, which uses the processor of Qualcomm and the memory of Samsung, it need to coordinate resources from Huawei, Qualcomm and Samsung to design and produce the best SiP products. Third, to improve the system integration ability and enhance the design and simulation capabilities of SiP. At present, the proportion of SiP in all products of OSAT is not very large, and the design and simulation capability of SiP in OSAT itself is relatively weak. It needs to keep up with the development of design and simulation technology to obtain more customers.
The technology content of SiP is high or low, which requires a variety of packaging technologies such as Wire Bonding, Flip Chip, PoP, TSV, RDL, Fan-in, Fan-Out, C2W (Chip to Wafer), W2W (Wafer to Wafer), etc. At the same time, it needs design
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and simulation capabilities to support the development and industrialization of highend SiP technology. Therefore, it is an important means to obtain orders to improve the technical level and to have the ability of a variety of technologies. From the current situation, the trend of package enterprise conglomeration is more and more obvious, which has a great impact on the semiconductor industry chain. It is a general trend to concentrate resources to optimize industrial efficiency, and realize technology and customer sharing. Because the merger can give customers more powerful packaging technology support and get a one-stop solution. On the other hand, less packaging vendors increase the costs and risks to their customers in the supply chain, but overall the benefits outweigh the disadvantages. From the global packaging competition pattern, the grouping trend formed by the merger and acquisition integration is becoming more and more obvious. These merger and acquisition integration will ultimately bring real impetus to the technological innovation of the semiconductor industry.
3.1.5 Selection of SiP Process and Materials For a new SiP product, the first thing designers need to know is what processes and materials are used to implement the SiP product, what are the different choices, and how different are the costs and cycles? This is what I found most important when I was discussing projects with users. It is explained in this chapter. SiP products are mainly divided into three types by process or material: plastic SiP, ceramic SiP and metal SiP. Other packaging types can basically be classified into these three categories. 1.
Plastic SiP
Plastic SiP is characterized by the use of organic substrates, so plastic SiP is also known as organic SiP. Plastic SiP is mainly used in commercial products with the advantage of low cost, but it is relatively poor in heat dissipation, stability and airtightness. Its main features are summarized as follows: • The sealing is not good enough to prevent the chip from being corroded by moisture and corrosive gas. • It is not easy to disassemble. After packaging, it can hardly be opened, otherwise the chip will be damaged. • The thermal performance is poor because the heat transfer coefficient of the organic substrate and the sealing glue is low. • The working temperature range is small, the general temperature range is 0 °C ~ +70 °C, and the industrial grade is −40 °C ~ +85 °C. • The production cycle is short, the general production cycle is 2 ~ 3 months. • Low price, low cost, one prototype needs about RMB 100,000 yuan. • Suitable for mass production and widely used in commercial business.
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Fig. 3.9 Basic structure diagram of plastic SiP
Plastic SiP generally uses organic substrates to interconnect and carry chips, and then solidify and seal chips by Molding. The basic structure of Plastic SiP is shown in Fig. 3.9. 2.
Ceramic SiP
The notable feature of ceramic SiP is that it uses a ceramic substrate, and the substrate and the shell of the ceramic SiP are integrated. Ceramic SiP is mostly used in industrial products, military products, aerospace and related fields. It has good heat dissipation, good airtightness and high reliability. At the same time, ceramic SiP have the advantages of disassembly, making it easy to find faults and to “zero” the problem. Its main features are summarized as follows: • Good sealing, can achieve air tightness, block moisture and corrosive gases; • The thermal conductivity of the ceramic substrate and shell is relatively large, which is good for the chip to dissipate heat. • Good resistance to the extreme temperature, the working temperature of ceramic packaging can reach the military requirements of −55 °C ~ +150 °C. • Easy to disassemble, easy to analyze, the internal chips of the ceramic package are in the vacuum exposed state. • Compared to metal package, it is small and suitable for large-scale complex chips. • Compared to plastic package, it is heavy and sometimes needs to be specially reinforced on the PCB board. • Long production cycle, 6–8 months in general. • Price is high, about RMB 400 K to 1 million is needed for one prototype. • Suitable for military and aerospace applications, and is currently widely used in the global military and aerospace fields. Ceramic SiP uses HTCC substrates to interconnect and carry chips. The shell and the substrates are usually integrated into one structure. The structure is mostly cavity structure, sealed with kovar alloy, and vacuum or nitrogen filled in the sealing chamber. For some high-power Flip Chip devices, is usually placed outside the sealing chamber to facilitate heat sink. The basic structure of ceramic SiP is shown in Fig. 3.10. 3.
Metal SiP
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Fig. 3.10 Basic structure of ceramic SiP
Metal SiP is similar to ceramic SiP. It is used in industrial products, military products, aerospace and related fields. It has good air tightness, high reliability and good heat dissipation. Metal SiP can also be disassembled to facilitate troubleshooting and problem “zero”. Its features are summarized as follows: • It is well sealed to achieve air tightness and to block moisture and corrosive gases. • Good heat dissipation and resistance to extreme temperature. • Easy to disassemble, you can directly see the bare chip inside when you open the lid. • Larger size, heavier weight, fewer pins, not suitable for complex chips. • Usually used in MCM field, RF microwave, analog SiP field has more applications. • Long production cycle, 4–6 months in general. • The price is high, and RMB 300–800 K is needed for one prototype. • More suitable for military and aerospace applications. Metal SiP generally uses LTCC, thick-film or thin-film ceramic substrates to interconnect and carry chips. Metal SiP and ceramic SiP have different integrated structure. The base and shell of metal SiP are designed and processed independently. The substrate is fixed to the metal shell by bonding method, Bond Wire and external pin connection are used on the electrical, the metal SiP is air-tight, and the internal vacuum or nitrogen filling is used. The basic structure of the Metal SiP is shown in Fig. 3.11 below. Designers need to consider the actual situation of the project to determine which processes and materials to choose to complete their SiP projects. Each type of SiP product has its own characteristics and advantages, which requires designers to make reasonable choices according to the project purpose, cycle, funding, etc.
Fig. 3.11 Basic structure of metal SiP
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3.2 MicroSystem 3.2.1 Natural and Man-Made System Before we get to know MicroSystem, let’s first get to know system. A system is an organic whole which is composed of interdependent components, has specific functions, and is part of a larger system to which it belongs. System is usually composed of several functional units, which can be large or small, complex or simple. Here, we classify system into two categories: natural system and man-made system. 1.
Natural System
Natural systems are all kinds of self-circulating systems that have been naturally formed in the universe for hundreds of millions of years, such as celestial bodies, the earth, oceans, ecological and ecological systems, meteorology, and various organisms including the human body. The natural system is a high-order and complex self-balancing system, such as the innate movement of the celestial bodies, the recurrence of seasons, the ecological cycle of animals and plants on the earth, the food chain system, and the various systems that sustain life are all natural systems. The natural system includes the ecological balance system, the life organism system, the celestial system, the material micro-structure system, etc. Individuals in the system exist or evolve according to the natural laws, producing or forming a natural phenomenon and characteristics. The natural environment system has no end, has not been abolished, only has the circulation, and develops from one level to another. The natural systems on which all life on the earth depends are huge and complex, and are interlaced by various natural forces. Natural systems can be as small as an atom or as large as the entire universe. 2.
Man-Made System
Man-made system is a system formed by human participation, such as GPS, spaceship, satellite, airplane, automobile, ship, mechanical equipment, etc. There is an interface between man-made system and natural system, and they influence and penetrate each other. With the rapid development of science and technology in recent hundreds of years, man-made systems have more and more influence on natural systems. Here’s a look at the most typical man-made system: GPS. The Global Positioning System (GPS) has been developed in the United States since the 1970s. It took more than 20 years and cost 30 billion US dollars. It was fully built in 1994. The GPS system consists of three parts: the space part—GPS constellation, which is composed of 24 satellites, 21 of which are working satellites and 3 of which are backup satellites; the ground control part—ground monitoring system; and the user equipment Part—GPS signal receiver.
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Twenty-four satellites are evenly distributed in six orbital planes, with an average height of 20,200 km. At least four satellites can be observed anywhere in the world at any time. The ground control part consists of a master station, five global monitoring stations and three ground control stations. GPS user equipment is composed of GPS receiving module, data processing software and its terminal device such as smartphones. Figure 3.12 below show a diagram of how a GPS satellite orbits the earth. With the rapid development of science and technology, man-made systems can benefit human beings, endanger natural systems and even cause disasters. Therefore, people pay more and more attention to the harmonious coexistence of man-made system and natural system. Man-made system and natural system can also be combined to form a composite system. Composite system is a dynamic and complex system. Man-made system is usually part or element of the composite system, while natural system is often the top level of the composite system. The Milky Way is a system, the Solar System is a system, and the Earth is a system. These are all natural systems. GPS is a system, satellite is a system, payload is a system, PCB is a system, SiP is a system, and SoC is a system. These are man-made systems.
Fig. 3.12 Diagram of global positioning system
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3.2.2 Definition and Features of System In this book, we focus on man-made systems, so the systems described in the following descriptions refer to man-made systems. 1.
System Definition
System refers to the structure that can accomplish one or more functions, and refers to the whole formed by orderly arrangement of scattered things. System is a combination of interdependent components, an organic whole with specific functions, and this organic whole is a component of a larger system. 2.
Features of the System
The system mainly includes the following six features, as shown in Fig. 3.13. Below we explain the six main features of the system, and give a brief description of the corresponding to SiP. (1)
(2)
Collectivity, a system consists of at least two or more elements that can be distinguished from each other, and a single element cannot form a system. Corresponding to the SiP, it indicates that the SiP contains at least two bare chips and a varying number of passive devices. Relevance, each feature in the system is interdependent, constrained and interacted to form an interrelated whole, one feature has changed, and other elements have also changed, causing system changes. Corresponding to SiP, the status of one chip changes, and other chips will have corresponding adjustments to meet the functions defined by SiP, one chip will fail, the whole SiP will fail or some functions will be missing. So when designing SiP, it’s as simple as possible while meeting the functional requirements. Use the fewest chips to implement the function of SiP. Otherwise, one of the chips will fail and the other KGD chips will also fail.
Fig. 3.13 Six features of the system
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Purpose, the system has a clear purpose, that is, the specific functions displayed by the system. This purpose must be the overall purpose of the system, not the local purpose that constitutes the elements or subsystems of the system. A system may have multiple purposes. For SiP, the definition of SiP function is involved. If there is a clear application purpose, the function definition of SiP can be easily defined. The ambiguity of function definition should be avoided, which makes the implementation of SiP design more difficult. Hierarchy, a complex system consists of multiple subsystems, which may be divided into smaller subsystems, and the system itself is a component of a larger system, which is hierarchical. The structure and function of a system refer to the structure and function at the corresponding level. For SiP, SiP should be a subsystem of a complex system, and there will be smaller systems in SiP, such as one or more SoC in a SiP. Environment, also known as environmental adaptability, the system has the ability to adjust itself to the changes of external environment to adapt to the new environment. The system must adjust its own functions as the environment changes. A system without environmental adaptability is lifeless. For SiP, the design of SiP should take into account the impact of environmental changes on SiP products, the possible applications of SiP and the life cycle of SiP products. Dynamicity, the system reflected by the life cycle of the system itself is also in the process of gestation, generation, development, decline, annihilation. Corresponding to SiP, there are also processes such as SiP product concept, planning, design, production, testing, promotion, application, update and replacement.
3.2.3 New Definition of MicroSystem 1.
Traditional Definitions of MicroSystem
MicroSystem is usually systems implemented at a very small scale, usually within a chip or within a package. Traditionally, MicroSystem is often associated with Micro-Electro-Mechanical Systems (MEMS). Common applications include sensors, micro-motors, micro-pumps, and so on. MicroSystem technology is developed from integrated circuit technology. Integrated circuit technology can be said to be the starting point of MicroSystem technology. Silicon anisotropic etching technology is used to fabricate three-dimensional structures (bulk silicon structures) on planar silicon substrates, and integrated circuits are used to fabricate MicroSystem technology devices, such as micro-cantilevers, thin films and nozzles; key components of micro-sensors; and inkjet printing technology. Figure 3.14 shows a MicroSystem processed using integrated circuit technology. With the development of technology, the research of MicroSystem technology has entered a stage of rapid development. Optical MicroSystem technology and biological MicroSystem technology have also developed rapidly. From the beginning, MicroSystem technology mainly carries out scattered research on micro-structure, and now it is in full blossom.
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Fig. 3.14 MicroSystem processed using integrated circuit technology
For example, silicon anisotropic etching technology has been developed to process three-dimensional structures on planar silicon substrates, and integrated circuit processing technology has been used to manufacture MicroSystem technology devices, such as cantilever beams, microphones, accelerometers, micromechanical gyroscopes, etc. Micro-mechanical structures processed by surface micro-machineries, such as springs, transmission machines, cranks, integrated inertial sensors, etc. Adaptive optical system, adjustable filter, gas spectrum analyzer processed by optical microsystem technology; Artificial retina, cochlear implants, embedded physiological sensors, and intelligent surgical tools containing sensors are processed using biological MicroSystem technology. 2.
New Definition of Microsystem
With the advent of SoC and SiP technology, the definition of MicroSystem has changed gradually from the original field which was more focused on micromechanical structure to the more general field, and its scale has also been extended to the scale of SiP. We can now define a system encapsulated in a SiP as a MicroSystem, which can include electronic components (bare chips, resistors, capacitors, inductors, etc.), MicroSystem, optical devices, sensors, gyroscopes, etc. At present, most SiP encapsulated systems are pure electronic systems, which we can call electronic MicroSystem. With the development of technology and increasing demand, SiP encapsulated system will gradually change from electronic MicroSystem to hybrid MicroSystem. On the basis of electronic devices, optical devices, sensors, micro-mechanical structures, micro-pumps and so on will be included (Fig. 3.15). Today, we can define that SiP is an important carrier for the implementation of MicroSystem and the best way to achieve MicroSystem at present. On the basis of SiP, it is easier to achieve the features of miniaturization, low power consumption, high performance, flexibility and diversity of MicroSystem. And reduce costs to a certain extent, shorten the R&D cycle.
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Fig. 3.15 SiP is an important carrier for microSystem
Therefore, SiP design needs to start from a MicroSystem perspective, while MicroSystem need to be implemented through SiP technology.
Chapter 4
From 2D to 4D Integration Suny Li
4.1 Development of Integration Technology Integration refers to the process of changing the original dispersed state of isolated elements in a specific way, combining them together, and interacting with each other to form an organic whole. When this organic whole can be called a system, integration is also called system integration. Therefore, integration is a necessary means to build the system.
4.1.1 Scale of Integration For electronic systems, we can classify the integration on scale. From the internal integration of chip to the internal integration of package to PCB board level integration, we can define them according to their common measurement units and the scale of the major elements they contain. • Nano-scale Integration: The integration on IC is mainly measured in nm, and the scale of transistors it contains is nanometer, which we call nanometer scale integration. • Micron-scale Integration: The integration in SiP or advanced package mainly uses um as its measurement unit, and the internal bare chips, bond wires, RDL, TSV are usually in micron scale, which we call micron scale integration. • Milli-scale Integration: The integration in PCB is mainly measured in mm, and the internal components, pins, traces and vias are usually in mm scale, which we call millimeter scale integration. S. Li (B) Beijing, China e-mail: [email protected] © Publishing House of Electronics Industry 2022 S. Li (ed.), MicroSystem Based on SiP Technology, https://doi.org/10.1007/978-981-19-0083-9_4
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Fig. 4.1 Diagram of integration scale
Figure 4.1 is the diagram of integrated scale which shows the main scales distribution areas of IC, SiP and PCB, there are some overlaps between them. With the development of technology, they even tend to merge in some areas. 1.
IC Internal Integration
IC internal integration has been based on 2D planar integration technology since the birth of integrated circuits. And gradually from the initial milli-scale to the micronscale until today’s nano-scale integration. Today’s integrated circuits can integrate more than 100 million transistors over a square millimeter area, horizontally arranged on a silicon interposer. Although the density of integration is increasing, until today, in addition to 3D NAND FLASH, the integration on IC is mainly 2D integration. In recent years, with IC process approaching the physical limit gradually, the integration on IC is also facing the dilemma of increasing the density of integration. 2.
Package Internal Integration
Package internal integration starts with MCM (Multi Chip Module). Initially, the package internal integration is based on 2D integration. All chips and passive devices are mounted horizontally on package substrate. With the increasing demand for MCM functions and performance, as well as the growing size of chips, when more functions and larger scales are needed, the original concept is no longer applicable, SiP technology finally appears with a unique stunt: 3D integration technology. The initial 3D integration was to stack bare chips of different functions from bottom to top, connect by bond wires on both sides, and present them in a system-level package. The stacking can be pyramid, cantilever, side by side, and so on. Subsequently, a 3D integration method based on silicon interposer emerged, routing (RDL) and punching (TSV) on silicon interposer and installing chips on it. At the same time, 3D integration methods for direct punching (TSV) and routing (RDL) on chips are becoming more and more common. For the sake of distinction, the integration based on silicon TSV is called 2.5D IC, and the integration of directly punching TSV on chip is called 3D IC. Although this is reasonable, it also causes some confusion. For example, many people confuse the IC-based 3D NAND FLASH with the chip stacking-based NAND FLASH, the former is a 3D integration inside IC, and the latter is the 3D integration inside package. With the diversity and flexibility of package internal integration requirements, integration technologies based on rigid-flexible combination substrate or substrate folding are also widely used in many fields. How can we distinguish them from other integration methods?
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PCB Board Level Integration
PCB (Printed Circuit Board) is one of the important components in the electronic industry. Almost every electronic device, from smart bracelet, mobile phones to computers, wireless communication devices, military weapons systems, any device, as long as there are integrated circuits and other electronic components, in order to make the electrical interconnection between the components, it is necessary to use PCB for integration. PCB is composed of insulating substrate, connecting wire, via hole and pad for assembling and welding electronic components, which has dual functions of conducting circuit and insulating substrate. Modern PCB has good product consistency and can adopt standardized design, which is conducive to the realization of mechanization and automation in the production process. At present, the variety of PCB has developed from single side to double-sided board, multilayer board, HDI high-density board, flexible board, rigid-flexible combination board, etc. Due to the influence of component packaging scale and the limitation of PCB processing technology, the integrated density on PCB has not changed much over the years. Therefore, in order to improve the integration density of electronic systems, the internal integration of package has the greatest space for development. Due to the flexibility of its integration method, it has received attention from many aspects. From Foundry to OSAT to system manufacturers are actively researching and applying the package internal integration. SiP and advanced packaging technology have also become the hot spots of the development of electronic technology.
4.1.2 One-Step Integration and Two-Step Integration From the previous chapters, we know that integration is the basis of electronic technology and micro-system implementation. In this chapter, according to the classification method in the previous section, we focus on the current mainstream integration technology. Before introducing integration technologies, let’s look at One Step Integration and Two Steps Integration. 1.
One Step Integration
In this book, we define the integration that is accomplished in a set of processes as one-step integration, such as the production of the Integrated Circuit Bare Chip as we know it. A wafer is coated with a photo resistor, and the wafer is illuminated with ultraviolet light through a mask. The specific shape of the light is illuminated on the wafer. The layout of the microcircuit is copied onto the wafer. The circuit pattern is generated by the photolithography process. The conductivity of the silicon in these
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areas is changed by ion implantation, and a transistor circuit is formed by multilayer metal. The interconnection of various transistors completes complex integrated circuit production. The whole process may take more than 2,000 steps to complete, but the whole circuit does not leave the wafer itself from start to finish. Generally, the whole process is completed in one Foundry, so we call it one-step integration. One-step integration is mainly based on 2D integration. At present, in the application of integrated circuit manufacturing, the vast majority of IC manufacturing belongs to 2D one-step integration. At present only 3D Nand Flash belongs to 3D one-step integration. 3D NAND can now reach 128 layers or higher, and its output is exceeding 2D NAND, and the number of layers will expand further, so 3D NAND can continue to maintain Moore’s Law well. With the development of technology, if 3D one-step integration can also be applied to other IC fields, then the real 3D IC era will come. 2.
Two Steps Integration
In this book, we define the integration of the two processes for the substrate production and assembly as two-step integration. SiP, all package with substrate, MCM and PCB are two-step integration. For example, in the production process of SiP, the substrate is manufactured and tested by substrate factory. After the production of the substrate completed, the packaging manufacturer completes the whole process of adhesive, bonding, welding, packaging, testing of SiP. The production of the substrate and packaging are usually completed by different professional manufacturers or by different professional departments, so we call it two-step integration. The package internal integration technologies described below are all defined on the basis of substrate integration, so they fall into the category of two-step integration.
4.1.3 Classified Naming for Package Internal Integration Traditionally, any stacked integration can be referred to as a 3D integration because there is a functional and signal extension on the Z-axis, whether the stack is inside or outside the chip. Due to the diversity of package internal integration and the emergence of new technologies, there is some confusion in the definition of integration. For this reason, the author combs all kinds of integration methods based on his own experience, and combines with the existing definitions, classifies and names the package internal integration technology, in order to give readers a clearer and in-depth understanding of the integration technology. The author classifies the current package internal integration technologies as follows, with reference to (Table 4.1).
2D integration
The chip is mounted horizontally on the substrate
Tiling
Through substrate
Type
Description
Physical structure
Electrical interconnection
Through substrate
Stacking
The chips are stacked on the substrate and connected to the substrate by bond wires
2D+ integration
Above substrate (Assembly)
Position
Silicon interposer
Stacking
Integration through silicon interposer
Direct chip connection
Stacking
The chip is electrically connected directly through TSV
2.5D integration 3D integration
Table 4.1 Classification naming for package internal integration
Through substrate
Substrate folding
Integration through substrate folding
4D integration
Embedded substrate
Planar passive devices are integrated into the substrate through material generation
Through substrate Through substrate
Embedded substrate
By embedding the chip partially or completely into the substrate
Planar integration
Inside Substrate (Fabrication) Cavity integration
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• Integration above substrate: 2D integration, 2D+ integration, 2.5D integration, 3D integration, 4D integration in 5 categories; • Integration inside substrate: cavity integration and planar integration. When classifying integrated technologies, we follow two standards: physical structure and electrical interconnection.
4.2 2D Integration Technology Preconditions: The following definitions are based on the upper surface mounting device of the substrate. For the case where the device is mounted on the lower surface of the substrate, the same definition can be used to judge the case by simply inverting the mirror image of the substrate. The preconditions are used in the definitions of the five categories of 2D integration, 2D+ integration, 2.5D integration, 3D integration and 4D integration described later.
4.2.1 Definition of 2D Integration 2D integration, refers to the integration of all chips and passive devices horizontally mounted on the surface of the substrate (Fig. 4.2). Definition of 2D Integration: The coordinate system is created with the lower left corner of the surface on the substrate as the origin, the surface on the substrate as the XY plane, and the normal line of the substrate as the Z axis. Physical structure: All chips and passive devices are mounted on the substrate plane, the chips and passive devices are directly in contact with the XY plane, and the traces and vias on the substrate are located under the XY plane. Electrical connection: All need to pass through the substrate (except for a few bond pads that are directly connected through the bond wire).
4.2.2 Application of 2D Integration The most common 2D integration technologies are applied to MCM, parts of SiP, and PCB. 1.
MCM (Multi Chip Module)
MCM is a complete module by installing multiple bare chips on the same substrate with high density. In the traditional packaging field, all packaging is device-oriented, serving the chip, playing the role of protecting the chip, scale-up and electrical connection,
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Fig. 4.2 2D integration definition diagram
there is no concept of integration. With the rise of MCM, the concept of integration has emerged in package, so package has changed substantially. MCM changes the concept of package from chip to module, component or system. MCM is generally divided into the following three types: (1)
(2)
(3)
2.
MCM-L(Multi Chip Module-Laminate)is a multi-chip module made of multilayer printed circuit boards. MCM-L is a mature manufacturing process with low cost. Due to the limited installation of the chip and the structure of the substrate, high density routing is difficult. Therefore, the electrical performance is relatively poor, mainly for products below 30 MHz. MCM-C(Multi chip Module-Ceramic)is a kind of MCM made on ceramic substrates by using thick film technology and high density multilayer routing technology. MCM-C is mainly used for high reliability products of 30500 MHz. MCM-D(Multi Chip Module-Deposited Thin Film) uses thin-film technology to deposit metal materials on ceramic or silicon or aluminum substrates, photolithography signal traces, power and ground traces, and then make multilayer substrates. Mainly used in high performance products above 500 MHz, it has the advantages of high assembly density, short signal channel, low parasitic effect and low noise. 2D Integrated SiP
The process of 2D integrated SiP is very similar to that of MCM. The main difference between 2D integrated SiP and MCM is that the size of 2D integrated SiP is larger than that of MCM and can form a separate system. Organic or high density ceramic substrates are fabricated first and then encapsulated and tested (Fig. 4.3).
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Fig. 4.3 SiP of 2D integration
4.3 2D+ Integration Technology 4.3.1 Definition of 2D+ Integration 2D+ integration refers to the traditional chip stack integration connected by bond wires. Perhaps some people think that chip stacking is 3D integration, why should it be defined as 2D+ integration? There are two main reasons for this: (1) At present, 3D integration refers specifically to integration through 3D TSV. To avoid confusion, we define this traditional stacking of chips as 2D+ integration. (2) Although the physical structure of this kind of integration is 3D, all the electrical interconnections need to pass through the substrate, that is, connect to the substrate through the bond wire first, and then conduct the electrical interconnection on the substrate. This is the same as 2D integration, but it improves the stacking structure and saves package space, so it is called 2D+ integration. 2D+ Integrated Definition: Create a coordinate system with the lower left corner of the surface on the substrate as the origin, the plane of the surface on the substrate as the XY plane, and the normal line of the substrate as the Z axis. Physical structure: All chips and passive devices are above the XY plane, some chips do not touch the substrate directly, and the traces and vias on the substrate are below the XY plane. Electrical connection: all need to pass through the substrate (except for a few bond pads directly connected by bond wire). 2D+ integration is the horizontal installation of chips and passive devices on the surface, on which chip stacking can be carried out. There are three main stacking methods: pyramid stacking, cantilever stacking and side-by-side stacking. Pyramid stacked chips stack up from large to small without inserting media in between. Cantilever stacking requires inserting a dielectric Spacer to bolster the upper chips for easy bonding of the lower chips. Side-by-side stacking is the process of stacking several small chips side by side on top of one large chip. The electrical connection of the upper chip needs to be connected to the substrate through Bond Wire, while the lower chip can be Bond Wire or Flip Chip (Fig. 4.4).
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Fig. 4.4 2D+ integration definition diagram
4.3.2 Application of 2D+ Integration 1.
2D+ Integration of Pyramid Chip Stack
Pyramid chip stack refers to stacking in order from large to small, with the bottom chip being either Bond wire Die or Flip Chip Die. See (Fig. 4.5) below. 2.
2D+ Integration of Cantilever Chip Stack
Cantilever chip stack, in chip stacking design, it is often necessary to stack chips of the same size or different shapes. Cantilever stacking is unavoidable at this time. A certain thickness of spacer must be inserted in stack to pad the upper chips and avoid affecting the Bond Wire of the lower chips. Its processing method is from bottom to top, stack one layer and bond one layer, then continue stacking and bonding, and so on, see Fig. 4.6 below. 3.
2D+ integration of stacked chips side by side
In chip stacking design, sometimes several small chips will be stacked on top of a large chip and connected directly with the substrate through bond wires. For small chips stacked side by side above, most chips with single pin can be connected to the substrate directly through bond wires. See Fig. 4.7 below.
Fig. 4.5 2D+ integration of pyramid chip stack
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Fig. 4.6 2D+ integration of cantilever chip stack
Fig. 4.7 2D+ integration of chips stacked side by side
4.4 2.5D Integration Technology 4.4.1 Definition of 2.5D Integration 2.5D, as its name implies, is a dimension between 2D and 3D. It usually refers to a dimension that has both 2D and 3D characteristics. In the real world, there is no such dimension as 2.5D. Definition of 2.5D integration: A coordinate system is created with the lower left corner of the surface on the substrate as the origin, the plane of the surface on the substrate as the XY plane, and the normal line of the substrate as the Z axis. Physical structure: All chips and passive devices are above the XY plane, at least some chips and passive devices are mounted on Interposer. Above the XY plane are the traces and vias of the interposer, and below the XY plane are the traces and vias of the substrate. Electrical connection: An Interposer provides electrical connection to a chip located on the interposer (Fig. 4.8). 2.5D integration inserts an interposer between chips and substrate, there are traces and vias, in interposer, chips and passive devices are installed on interposer. In addition, some chips and passive devices may be mounted directly on substrates.
4.4.2 Application of 2.5D Integration The key to 2.5D integration is interposer. There are several situations in general, (1) Whether the interposer uses silicon interposer (2) Whether the interposer uses TSV
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Fig. 4.8 2.5D integration definition diagram
(3) Whether the interposer uses other types of materials. On silicon interposer, we refer to the via that pass through the interposer as TSV, and on glass interposer, we refer to it as TGV. 1.
2.5D Integration with TSV in Silicon Interposer
The integration of TSV in silicon interposer is the most common 2.5D integration technology. Chips are usually connected with interposer by MicroBumps. Silicon interposer are connected with substrate by Bumps, there are RDLs in silicon interposer, TSV is used as the channel for electrical connection between the upper and lower surfaces of the silicon interposer. This kind of 2.5D integration is suitable for large-scale chips with high pin density. Chips are usually mounted on silicon interposers as Flip Chip. As follows (Fig. 4.9). 2.
2.5D Integration without TSV in Silicon Interposer
The structure of the 2.5D integration without TSV in silicon interposer is generally shown in Fig. 4.10 below. A larger bare chip is directly mounted on the substrate, which can be connected by Bond Wire or Flip Chip. Some smaller bare chips can be mounted on top of large chips due to its large area, but small chips cannot be directly connected to the substrate, so we need to insert an interposer to install multiple bare chips. There are
Fig. 4.9 2.5D integration with TSV in silicon interposer
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Fig. 4.10 2.5D integration without TSV in silicon interposer
RDL routings on the interposer, which connect the signal from the chip to the edge of the interposer, and then connects to the substrate through Bond Wire. This type of interposer usually does not require TSV, only electrical interconnection through the upper surface routings. Using the high density characteristics of the silicon interposers to improve the interconnection density, the surface of the silicon interposers can be multilayer routings (generally no more than three layers), and the silicon interposer is connected by bond wire to substrate. 3.
2.5D Integration with Other Materials as Interposer
In glass interposer, we call the via through the interposer as TGV (through glass via), and on the ceramic interposer, we call the via through the interposer as TCV (through ceramic via). Glass and ceramic materials have no free moving charge, excellent dielectric properties and close thermal expansion coefficient with silicon. The technology of replacing silicon material with glass or ceramic material can avoid the problem of poor insulation of TSV, which is an ideal 2.5D integrated solution. TGV, TCV technology does not need to make special insulation layer, which reduces process complexity and cost. At present, TGV, TCV and related technologies have wide application prospects in the 2.5D integration of optical communication, radio frequency, microwave, microelectromechanical system and micro-fluid devices.
4.5 3D Integration Technology 4.5.1 Definition of 3D Integration The main difference between 3D integration and 2.5D integration is that in 2.5D integration routing and via are performed on interposer, while in 3D integration routing and via are performed directly on chip and electrically connecting the upper and lower layers of the chip (Fig. 4.11). Definition of 3D integration: a coordinate system is created with the lower left corner of the surface on the substrate as the origin, the plane of the surface on the substrate as the XY plane, and the normal line of the substrate as the Z axis. Physical
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Fig. 4.11 3D integration definition diagram
structure: All chips and passive devices are located above the XY plane, chips are stacked together, TSVs pass through the chip are located above the XY plane, and substrate traces and vias are located below the XY plane. Electrical connection: Direct electrical connection of the chip through TSV and RDL. In addition to directly connecting the upper and lower layers of the chip with TSV and RDL, some chips and passive devices may be integrated on substrate in other ways (2D \2D+ \2.5D). 3D integration technology is also known as active TSV based integration technology. In 3D integration, at least one bare chip is overlapped with another bare chip. The lower chip has TSV on its body. Through TSV, the upper chip communicates with the lower chip and connects to the substrate.
4.5.2 Application of 3D Integration 1.
3D Integration of Same Chips
The vast majority of 3D integration applications are in the same kind of chip stacks, where multiple identical chips are stacked vertically and connected via TSV that pass through the stack, as shown in Fig. 4.12 below. Same chip integration is mostly used in memory integration, such as DRAM Stack, FLASH Stack, etc. 2.
3D Integration of Different Chips
In the 3D integration of different chips, two different chips are usually stacked vertically, connected electrically by TSV, and interconnected with the underlying substrate. Sometimes it is necessary to make RDL on the surface of the chip to connect the underlying TSV. As shown in Fig. 4.13 below, the upper chips are interconnected through TSVs on the lower chip and electrically connected to the substrate.
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Fig. 4.12 3D integration of same chips
Fig. 4.13 3D integration of different chips
4.6 4D Integration Technology 4.6.1 Definition of 4D Integration The diversity of package internal integration is an important reason why SiP has become a hotspot in the development of electronic systems. In the previous section, we talked about the integration of 2D, 2D+ , 2.5D, 3D respectively. In addition, are there any other ways to integrate in SiP? If so, how should we name it? People who have seen Inception should be impressed by the upright ground and the buildings and houses that hang high above it. In reality, this can only happen in dreams or in science fiction. On the earth, gravity and other factors make this less likely. However, in future space cities, there will be a high probability of such urban landscapes. At that time, our city functions will change dramatically. In this book, we define the spatial structure shown in Fig. 4.14 as a “4D” space. In this section, we discuss 4D integration in SiP. Fig. 4.14 Structure of “4D” space
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Fig. 4.15 4D integration definition diagram
The existing integration technologies in SiP, including 2D, 2D+, 2.5D, 3D integration, all chips, interposers and substrates, have a vertical Z-axis in the threedimensional coordinate system, that is, all the substrates and chips are mounted in parallel. This will change in 4D integration. In the coordinate system defined above, when the XY plane rotates around either the X axis or the Y axis, the Z axis of the XY plane will be offset, which can be defined as follows. Definition of 4D integration: First of all, there are several substrates in the integration. For each substrate, a coordinate system is created with the lower left corner of the surface on the substrate as the origin, the plane of the surface on the substrate as the XY plane, and the normal line of the substrate as the Z axis. When the XY planes of different substrates are not parallel, that is, the Z-axis direction of different substrates is offset, we can define this kind of integration as 4D integration. Physical structure: Multiple substrates are mounted in a non-parallel way. Components are mounted on each of the substrates and mounted in a variety of ways. Electrical connection: There are flexible circuits or welded connections between the substrates, and the electrical connections of the chips on the substrates are varied (Fig. 4.15). The definition of 4D integration is mainly about the orientation and interconnection of multiple substrates, so the integration of 4D will also include 2D, 2D+, 2.5D, 3D. In practical applications, we usually name the integration of the highest dimension in the product as its integration method. For example, a SiP contains both 2.5D and 3D integration, which we usually call 3D integration, and so on.
4.6.2 Application of 4D Integration 1.
4D Integration with Rigid-Flexible Substrate
The 4D integrated with rigid-flexible substrate is described below. The substrate consists of six rigid substrate, which are connected by five flexible circuits. On six
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Fig. 4.16 The expanded diagram of 4D integration based on rigid-flexible substrate
rigid substrate, chips and other components can be installed. The flexible circuit mainly plays the role of electrical interconnection and physical connection. After the installation of the components, bend the flexible area 90 degrees, stitch the rigid substrate into a box body, and weld the seams of the rigid substrate, then fill and reinforce the inner part of the package, and finally cover and implant the balls to complete the 4D integration. Fig. 4.16 shows the expanded diagram of 4D integrated package based on rigidflexible substrate, in which A, B, C, D, E and F are rigid substrates, with a total of 6 pieces, which are connected by 5 flexible circuits, and the edges not connected by flexible circuits are metallized for later welding. Components can be installed on each rigid substrate. The principle of installing components is to install the components with high height in the center of the substrate as much as possible, and the components with small height should be installed on the outside of the substrate to avoid interference with components on other substrates. The components on each substrate are arranged in pyramid shape. If it is a bare chip, chips can be stacked. After the components are installed, the flexible circuit is bent up 90 degrees to form an open box body, and the adjacent edges of the rigid substrate are welded. Then molding the box, or reinforce the chip in other ways, seal it, and plant a ball at the bottom. Figure 4.17 shows the completion of 4D integrated package based on rigid-flexible substrate. 2.
Air tight 4D integration with ceramic substrate
Air tight 4D integration with ceramic substrate described below, the ceramic substrate is used as the packaging substrate, and the whole package includes 6 ceramic
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Fig. 4.17 Completed diagram of 4D integration based on rigid-flexible substrate
substrates. Chips and other components can be installed on each ceramic substrate, and the electrical connection points are designed. The physical and electrical connections between the substrates are realized by welding (Fig. 4.18). After all components are installed, four of them are vertically installed and welded into a frame structure, and then the other two substrates are welded to the upper and lower surfaces of the frame structure to form a complete package. Because the air tight welding ring is designed at the joint, the hermetic isolation is realized inside and outside the whole package after welding. The air tight 4D integration substrate is divided into six parts. In the design of the substrate, it can be designed as a whole or each substrate can be designed separately. The electrical connection points between each substrate should be considered in
Fig. 4.18 The expanded diagram of air tight 4D integration
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Fig. 4.19 Completed diagram of air tight 4D integration
the design of the substrate, and the metallization treatment should be done at the edge of the substrate for later air tight welding. After the package is completed, all components are located inside the package and isolated from the external space. The complete air tight 4D integration is shown in (Fig. 4.19) below. Finally, the ball is planted at the bottom of a substrate for 4D integrated package and external electrical connection. If there is a demand, the package can be stacked to further increase the space utilization.
4.6.3 The Significance of 4D Integration From the strict physical sense, based on the existing human cognition, all objects are three-dimensional, two-dimensional foil does not exist, and four-dimensional space needs further research. In order to distinguish different integration methods, we divide them into five integration modes: 2D, 2D+, 2.5D, 3D and 4D. At present, parallel stacking (2D+ , 2.5D, 3D) is the main way to increase integration level in SiP, including chip stacking and substrate stacking. Parallel stacking is widely used at present, which improves the integration of package to a great extent, but there are some problems that are difficult to solve. For example, (1) there are strict requirements for chip size and power consumption in chip stack; (2) there are strict requirements for the size of upper and lower substrates and pin alignment in substrate stack; (3) interconnected metal balls or columns occupy a lot of chip installation space; (4) the heat dissipation problem can ‘t be well solved. Therefore, there are great limitations in the actual project application. In addition, this parallel stacking technology usually fails to achieve airtight packaging, which is the basic requirement for specific applications in many fields such as aerospace, military industry and so on. The 4D integration technology can solve the problems that parallel stacking can’t solve, provide more flexible chip installation space, solve the heat dissipation problem of high-power chips, and the most important airtight problems in aerospace, military and other fields.
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4D integration technology improves the flexibility and diversity of integration. Looking forward to the future, 4D integration technology will certainly have a place in the integration mode of SiP, and will become an important integration technology after 2D, 2D+, 2.5D, 3D integration.
4.7 Cavity Integration Technology 4.7.1 Definition of Cavity Integration 1.
What is a Cavity?
A cavity is a slot that opens on a substrate and usually does not pass through all the layers (in special cases, a cavity that passes through all the layers is called Contour). The cavity can be open or closed in the inner space. A cavity can be either a single or a multi-step one. The so-called multi-step cavity is to dig the cavity inside a cavity and reduce it step by step. Like a sinking square in a city, the bottom area is for people’s activity and the steps can be used as a stand. Below is a common cavity structure in ceramic SiP. Chips are installed in the bottom area, bond finger can be placed on the steps of the multi-step cavity (Fig. 4.20). Cavity is one of the most common substrate processes in ceramic package, and has received more and more attention. At present, with the improvement of technology, cavity is also used in many plastic package. For example, the latest Loongson CPU plastic substrate uses cavity structure. Cavity is a 3D structure. In order to simulate the structure of the cavity correctly, design software is needed to support the 3D substrate design.
Fig. 4.20 Cavity structure in SiP design
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Fig. 4.21 Diagram of multi-step cavity
Fig. 4.22 Diagram of embedded cavity
2.
Definition of Cavity
Figure 4.21 shows a diagram of a multi-step cavity with layers 1–3, 3–5, and 5–7. This multi-step cavity is common in ceramic package and bond finger can be placed on the steps. Figure 4.22 show a diagram of an embedded cavity through which a chip or discrete passive device can be embedded.
4.7.2 Application of Cavity Integration After having understood the definition of a cavity, let’s look at its application. 1.
Improving the Stability of Bond Wires Through Cavity Structure
For stacked or complex chips, multi-layer bonding lines are often used. The bonding finger is often arranged in 3–4 rows, so the outer bonding lines will be long and have a large span, which is not conducive to the stability of the bonding lines, while the cavity structure can effectively improve this problem. From the comparison of the two chip stacks in Fig. 4.23 below, it is obvious that the cavity structure can greatly reduce the length of the bond wire, thus effectively improving the stability of the bond wire.
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Fig. 4.23 Cavity structure can shorten bond wires and improve their stability
2.
Enhance Airtightness of Ceramic Package through Cavity
Ceramic substrates with cavity structure, chips and bond wires are all located inside the cavity, SiP is sealed by cover. If there is no cavity structure, a special welded metal frame is needed to raise the position of the cover, so there is an additional welding procedure, and the tightness of the weld seam needs to be strictly checked to meet the tightness requirements (Fig. 4.24). 3.
Install Components on Both Sides through Cavity
At present, the complexity of SiP is very high and many devices need to be installed. It is often impossible to install all devices on one side of the substrate, and it needs to be installed on both sides. At this time, the structure of the cavity is very important. A part of the chip can be mounted on the bottom of the SiP package through the cavity, and a welding ball can be designed and planted on the outside of the bottom of the package. Figures 4.25 below are shown. If there is no cavity structure, it is difficult to install the device on the bottom of the substrate. If the device is only allowed to be mounted on the top of the substrate,
Fig. 4.24 Cavity structure enhances air tightness of ceramic package
Fig. 4.25 Install chips on both sides through cavity
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it is unavoidable to expand the package area, reduce the design flexibility, and run counter to the concept of SiP miniaturization. Of course, everything has two sides, and the cavity will also have adverse effects on design and production, such as the cavity increases the complexity of the substrate, the requirements for design software are relatively high, the design software needs to support the design function of the 3D substrate, and so on.
4.8 Planar Integration Technology 4.8.1 Definition of Planar Integration Planar integration technology, also known as planar embedding technology, are planar passive devices such as resistors, capacitors or inductors made of special materials, and printed on the surface of the substrate or embedded between the layers of the substrate. Passive devices, such as resistors, capacitors, inductors, are designed and processed to be etched or printed on the surface or inside the substrate to replace the passive components welded on the surface of the substrate, thereby improving the layout space and routing freedom of the active chip. The resistor, capacitor and inductor made by this method have no height and will not affect the thickness of the substrate. (1) The planar resistor is usually made of a resistive material, which can be distributed in different layers of the substrate. (2) The planar capacitor can be divided into two categories, one is a flat capacitor made of capacitive material, which can be distributed in different layers of the substrate, the other is a capacitive material as a medium to form the entire capacitive layer. (3) For planar inductor, a special coil pattern is used, which may span multiple layers and is connected through connect via in the middle. Refer to the planar resistor, capacitor and inductor in the substrate of Fig. 4.26.
4.8.2 Application of Planar Integration At present, planar resistor is widely used in SiP, MCM, thick film and thin film circuits in China and abroad. It is generally made on the surface of the substrate, so as to facilitate the subsequent laser adjustment. Planar capacitors mostly use capacitive materials as media to form the entire capacitive layer. The application of discrete planar capacitors is relatively few, mainly due to the complex process. For example, printed capacitors need at least three layers of materials, while mezzanine capacitors are more complex. In addition to multilayer materials, adjacent layers need to be connected through via (Fig. 4.27).
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Fig. 4.26 Planar resistor, capacitor and inductor embedded in substrate
Fig. 4.27 Basic structure of planar resistor, capacitor and inductor
1.
Planar resistor technology
Planar resistor technology usually uses high resistivity materials to make planar resistors of various shapes and values. At present, the main resistive materials provided are DuPont, Ohmega and TICER. The process includes thick film and thin film. Relatively, the planar resistor structure is relatively simple. Thick film process requires the printing of resistance shapes between two metal terminals. At present, the four commonly used shapes are Rectangle, Top hat, Folded and Serpentine. Rectangle structure is simple, most common, Top hat protruding part for laser resistance adjustment, Folded type occupies less space, is more suitable for smaller resistance value, Serpentine type is suitable for larger resistance value (Fig. 4.28). 2.
Planar capacitor Technology
Planar capacitor technology usually uses dielectric materials with large dielectric constants. It has a structure similar to a parallel-plate capacitor, with metal layers on both sides and a dielectric thin layer with high dielectric constant and low dielectric
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Fig. 4.28 Four shapes of planar resistor structures
loss in the middle, thus increasing the capacitance. Optional capacitive materials come from various manufacturers such as 3 M, DuPont, Gould and Huntsman. The planar capacitor structure is relatively complex, generally divided into Interdigitated, Printed and Mezzanine. (1) The interdigitated capacitor, which is shaped like the fingers of two hands crossing each other, is placed in an electrical layer as a complete element and filled with a medium in the middle. (2) A printed capacitor consisting of two metal terminals at the bottom of the capacitor. One of them has a large area, covered with a medium, and then printed with a conductor. One end of the conductor is above the dielectric layer, the other end is overlapped with a small area of metal terminals. Its effective area is the area overlapped by the bottom metal separated by the media and the printed conductor. (3) The Mezzanine capacitor has a complex structure including top metal, medium, bottom metal and a through hole via (Fig. 4.29). Another way to planar capacitor is to add a layer of capacitance to the entire dielectric layer, which is a relatively simple process. See the capacitive material layer in Fig. 4.26. 3.
Planar Inductor Technology
Planar inductor technology usually uses etching of copper foil or plating of copper to form spirals, bends and other shapes, or to form spiral multi-layered structures by interlayer holes. Its properties depend on the base material parameters and the shape and structure of the graphic. At present, the inductor value that can be supported is relatively small, only a few to several dozens of nanohenry, mainly used in high frequency modules.
Fig. 4.29 Three shapes of planar capacitor structures
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4.9 Summary of Integration Technology Below, we summarize the package internal integration technology described in this chapter with reference to a table. Refer to Table 4.2, where 1–5 integration is mainly related to the assembly process and 6–7 to the substrate process. The judgment is based on the physical structure and the electrical connection. The physical structure is the main one. When the physical structure is not easy to distinguish, the auxiliary one is the electrical connection. Table 4.2 Summary of package internal integration technology No
Name
Physical structure
Electrical connection Diagram
1
2D integration
All chips and passive devices are mounted on the substrate, and the chips and passive devices are in direct contact with the substrate
Need to pass through the substrate
2
2D+ integration
With chip stacking, some chips do not touch the substrate directly
Need to pass through the substrate
3
2.5D integration
At least some chips are mounted on interposer
Interposer provides electrical connection
4
3D integration
With chip stacking, some chips do not touch the substrate directly
Direct connection between upper and lower chips via TSV
5
4D integration
The substrate is folded or mounted in a non-parallel combination of multiple substrates
Need to pass through the substrate
6
Cavity integration
There is a cavity in the substrate, including an open cavity and an embedded cavity
Need to pass through the substrate
7
Planar integration
To etch or print resistors, capacitors, inductors, etc. on the surface or inside of the substrate
Need to pass through the substrate
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Fig. 4.30 Location of seven integration technologies in defining coordinate systems
Figures 4.30 below are the locations of the seven integration technologies described in this chapter in the defining coordinate system, which, combined with the previous definitions, can help readers understand. Figures 4.31 below are a summary of the 2D, 2D+, 2.5D, 3D, 4D integration technologies and the cavity and planar integration technologies mentioned in this chapter. Referring to Table 4.2, we can clearly define and distinguish the differences among the various integration technologies, and select the appropriate integration technology based on the requirements of the SiP project. In the second part of this book, “Design and simulation”, there are detailed descriptions of how different integration technologies are designed in EDA software. Examples are as follows: • Chapter 11: Wire Bonding Design in Detail, detailed introduction to design methods of 2D, 2D+ integrated technology. • Chapter 12: Cavity, Chip Stack and TSV design, the design methods of 2D+ , 2.5D, 3D and cavity integration are introduced in detail.
Fig. 4.31 Summary of SiP integration technologies
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• Chapter 15: Embedded Passive Design, the design method of planar integration technology is introduced in detail. • Chapter 17: Rigid-Flex Circuits and 4D SiP Design, the design method of 4D integration is introduced in detail. • Chapter 19: SiP Design Flow Based on Advanced Package (HDAP), the design method of 2.5D, 3D integration is introduced in detail. Readers can combine the corresponding chapters to practice and master the design methods of different integration technologies.
Chapter 5
SiP and Advanced Packaging Technology Suny Li
5.1 SiP Substrate and Package First of all, it needs to be explained that SiP is different from traditional package. As a complex system-level packaging product, because of the complexity of its internal electrical interconnection, most SiP need a substrate. The substrate is an important carrier for SiP electrical interconnection and physical support. Therefore, we first classify and discuss SiP from the perspective of the substrate. The substrate technology has been developed for more than 80 years, from the initial single side board to today’s high density interconnection board, Rigid-flexible combination board, microwave circuit board, embedded device board, HTCC, LTCC, IC carrier board, MCM substrate, SiP substrate and so on. The development of substrate technology has played a tremendous role in promoting the development of electronic technology. The following is a brief description of substrate technology and its related packaging technology.
5.1.1 Organic Substrate 1.
Rigid Organic Substrate
In general, organic substrates refer to rigid organic substrates, which are made of organic resin and glass fibre cloth as the main materials, and conductors are usually copper foil. Organic resins usually include epoxy resins (FR4), BT resins (bismaleimide triazine resins), PPE resins (polyphenyl ether resins), PI resins (polyimide resins), etc. S. Li (B) Beijing, China e-mail: [email protected] © Publishing House of Electronics Industry 2022 S. Li (ed.), MicroSystem Based on SiP Technology, https://doi.org/10.1007/978-981-19-0083-9_5
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The common thickness of copper foil for organic substrates is 17 micron (half ounce), 35 micron (one ounce), 70 micron (two ounces), and so on. Sometimes, various thickness types are formed by electroplating and deposition, for example, 17 micron copper foil forms 28 micron by copper depositing process. The thickness of the copper foil is proportional to the current carrying capacity. If a larger current is required, a thicker copper foil and a wider trace are required. Table 5.1 is a table of the relationships between line width, copper thickness, temperature rise and current for designers to refer to. Organic substrate media can also be divided into many types. For example, FR4, according to the content of resin and glass fiber, can be divided into 106, 1080, 2116, 7628 and other models. The higher the value, the less the resin content, the higher the glass fiber content, the harder the hardness and the higher the dielectric constant. For example the resin content, 106 has 75%, 1080 63%, 2116 53%, 7628 44%. In addition, there is an RCC (Resin Coated Copper) with 100% resin content. The more resin content, the softer the material, and the higher efficiency of laser drilling. Table 5.2 shows the resin content of different types of dielectric materials, as well as the dielectric constant DK and loss factor DF between 100 M and 1.2 GH, for Designers’ reference. Organic substrates are mainly used in plastic encapsulated devices. Because of their cost advantages, they are currently the most widely used SiP substrates. Generally, in order to take into account all aspects of performance, SiP organic substrates use a variety of types of materials, generally with a higher resin content in the surface, such as RCC, 106, 1080, while the inner layer uses a higher hardness, such as 2116, 7628, to enhance the support strength. Organic substrates have their own characteristics and advantages. Compared with ceramic substrates, organic substrates do not require sintering, are less difficult to process, can make large substrates, and have the cost advantage. In addition, organic substrates have low dielectric constants, which are conducive to high-speed signal transmission. Of course, organic substrates also have their own disadvantages, such as poor heat transfer performance, heat transfer coefficient is usually only between 0.2 and 1 W/(m K), alumina ceramic materials can reach around 18 W/(m K), and aluminum nitride can reach around 200 W/(m K). In addition, the thermal expansion coefficient of organic substrates is usually larger than that of chips, generally 8–18 ppm/°C. The main component of a semiconductor chip is silicon, while the thermal expansion coefficient of silicon is only 2.5 ppm/°C. If the thermal expansion coefficient of the semiconductor chip differs too much from that of the substrate, it will be easy to generate greater stress at the IC weld during thermal cycling and lead to electrical connection failure when the temperature changes. Therefore, in order to ensure the accuracy of SiP or encapsulated substrate microcircuits, it is appropriate to use low thermal expansion coefficient substrate materials.
Trace width (mm)
0.25
0.375
0.5
0.625
0.75
1.25
1.875
2.5
15
20
25
30
50
75
100
2.6
2
1.5
1.1
0.9
0.7
0.6
0.5
4.2
3.5
2.6
1.9
1.7
1.3
1.2
1
Maximum current Amps
17 um
10
35 um
1/2 oz.
Copper thickness
Trace width (mil)
1 oz.
10 °C
Temp rise
Trace carrying capacity
6.9
5.7
4
3
2.5
2.1
1.6
1.4
70 um
2 oz.
3.5
2.8
2
1.4
1.2
1
0.8
0.6
17 um
1/2 oz.
20 °C
Table 5.1 Relationship between trace width, copper thickness, temperature rise and current
6
4.5
3.6
2.5
2.2
1.7
1.3
1.2
35 um
1 oz.
9.9
7.8
6
4
3.3
3
2.4
1.6
70 um
2 oz.
4.3
3.5
2.6
1.7
1.5
1.2
1
0.7
17 um
1/2 oz.
30 °C
7.5
6
4.4
3.2
2.8
2.4
1.6
1.5
35 um
1 oz.
12.5
10
7.3
5
4
3.6
3
2.2
70 um
2 oz.
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Table 5.2 Resin content, DK and DF of organic substrate dielectric materials No
Dielectric
Resin content (%)
DK
DF
1
RCC
100
3.60
0.018
2
106
75
3.70
0.018
3
1080
63
3.90
0.017
4
2116
53
4.20
0.017
5
7628
44
4.35
0.016
When choosing organic substrates, SiP designers should consider both cost and reliability, mainly considering thermal expansion coefficient, vitrification temperature and hygroscopic performance, to select the substrates such as FR4 (epoxy resin), BT (bismaleimide triazine resin), PPE (polyphenyl ether resin) PI (polyimide resin). At the same time, it is necessary to set reasonable copper foil thickness and layer stackup, select different types of materials, control dielectric constant (DK) and loss factor (DF), so as to optimize the performance of SiP or package under the premise of cost optimization. 2.
Rigid-Flex Substrate
Rigid-flex substrates refer to boards that combine flexible circuit boards (FPCs) with rigid printed circuit boards (PCBs). Usually, flexible circuits are used as connections of moving parts. One of the features of this kind of board design is that the number of layers of the flexible circuit and the rigid circuit are often inconsistent, for example, six layers of the rigid circuit and only two layers of the flexible circuit. Usually these two layers are bonded with the third and fourth layers of the rigid PCB. If the components are also to be placed on the flexible circuit, slots or chambers are needed to place the devices directly on the third and fourth layers (Surface layer of flexible circuit), the pad can be directly out of layer 3 and 4. Rigid-flex substrate are widely used in flip and slide mobile phones, and also in space equipment. At present, the more popular folding screen mobile phone also uses a rigid-flexible combination substrate. Details about the Rigid-flex substrate. Refer to Chap. 17 of this book: Rigid-Flex Circuits and 4D SiP Design, and Chap. 27: Rigid-Flex SiP Design Case. 3.
Plastic SiP Based on organic substrate
Usually, the package or SiP with organic substrates are also molded by organic materials, which we call plastic package or SiP. From the micro-structure point of view, the plastic sealing materials are less dense and cannot achieve air tightness, so the sealing of plastic SiP is slightly poor. In addition, because it is glue encapsulated, the plastic encapsulation material is not easy to disassemble. It needs strong acid etching to peel off the encapsulation and expose the bare chip inside, which affects the discovery and analysis of the problem to a certain extent. Also, the thermal performance of the plastic encapsulation device
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Fig. 5.1 Apple Watch and its plastic-encapsulated SiP
is poor because the working temperature range of the plastic encapsulation device is small and it is not suitable for use in harsh environment. However, under the same conditions, plastic SiP is small, light and inexpensive, suitable for mass production, so it has been widely used in the commercial field, and is currently the most widely used in various industries. Figure 5.1 below shows Apple Watch and its plastic-encapsulated SiP.
5.1.2 Ceramic Substrate Ceramic substrates usually contain HTCC, LTCC, Aluminum Nitride and other ceramic substrates, which are introduced one by one. 1.
HTCC Ceramic Substrate
HTCC (High Temperature Co-fired Ceramic) substrates, commonly referred to as aluminum oxide (Al2 O3 ) ceramic substrates, are sintered at around 1600°, generally using tungsten (W) or molybdenum (Mo) with higher melting point as conductors. HTCC prints high melting point metals such as tungsten, molybdenum and manganese on 92–96% aluminum oxide tape-casting raw ceramic according to the circuit design requirements, and combines them with 4–8% sintering additives to form a multilayer composite at 1500–1600 °C. It has the advantages of corrosion resistance, high temperature resistance, long life, high efficiency, energy saving, even temperature, good thermal conductivity and fast heat compensation. HTCC substrates have been developed quite well, and have been widely used in ceramic packaging materials, mainly in high-density ceramic packaging circuits and high-power ceramic substrates. HTCC has the advantages of high mechanical strength, high routing density, stable chemical performance, high heat transfer coefficient and low cost of materials. It has
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been widely used in packaging fields with higher thermal stability requirements, higher sealing requirements and higher heat output. With the arrival of SiP era and package internal integration, electronic system has higher requirements for circuit miniaturization, high density, multi-function, high performance, high reliability and high power. HTCC substrates have been widely used in recent years because they can meet many requirements for electronic system. 2.
LTCC Ceramic Substrate
LTCC (Low Temperature Co-fired Ceramic) Substrate is a kind of ceramic tape made of low temperature sintered ceramic powder with precise and compact thickness. The required circuit graphics are made by laser drilling, micro-pore grouting and printing of precise conductor paste on the raw ceramic tape. A variety of passive devices (capacitors, resistors, inductors, couplers, etc.) are embedded in the multilayer ceramic substrates to make a three-dimensional circuit substrates with built-in passive elements, and then sintered at 800–900 °C to form the ceramic substrates. LTCC has the advantages of low melting point, high metal conductivity, low production cost, printing resistor and capacitor. IC and active devices can be mounted on their surfaces to make passive/active integrated functional modules, which can further miniaturize and densify the circuit. The HTCC substrate is usually dark gray, and LTCC measurements are milky white or light blue, as shown in Fig. 5.2. We can also see from Fig. 5.2 that the pins of the HTCC substrate are dense, while the pins of the LTCC substrate are usually sparse. Because of the high strength of HTCC, it can become a separate shell, so HTCC ceramic packaging is also known as ceramic shell, and LTCC is usually used as a substrate and needs to be installed in a metal shell. Compared with HTCC, LTCC is mostly used in microwave radio frequency, analog circuit and other fields, especially for components for high frequency communication. HTCC is mostly used as high-speed ceramic substrates and high-density interconnected substrates. They will complement each other, learn from each other and develop together for a long time.
Fig. 5.2 Comparison of HTCC and LTCC
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LTCC is an important development direction in the field of packaging materials. With the continuous improvement of materials, the improvement of process control and the maturity of technology, the advantages of LTCC will be more prominent. 3.
AlN ceramic substrate
Aluminum nitride (AlN) substrates have excellent thermal conductivity, small thermal expansion coefficient, good thermal shock resistance, good electrical insulation and good dielectric properties. Heat conductivity represents the ability of the substrate material itself to conduct heat directly. The higher the value, the better the cooling capacity. Therefore, the heat conduction performance of the substrates becomes one of the important evaluation items when high power packaging or SiP chooses substrates. AIN is white or grey-white, monocrystal is colorless and transparent, and sublimation decomposition temperature is 2450 °C under normal pressure. It is a high temperature heat resistant material. AIN has a thermal conductivity of 260 W/mK, 5–10 times higher than alumina, good heat shock resistance and extreme heat resistance of 2200 °C. In addition, aluminum nitride is resistant to aluminum and other molten metals and gallium arsenide, particularly molten aluminum. AIN performance indicators are as follows: (1) (2) (3) (4) (5) 4.
The thermal conductivity is high, reaching 260 W/mK, which is more than 5–10 times of Al2 O3 . Thermal expansion coefficient: 4.5 PPM°C, which matches Si (3–5 PPM°C) and GaAs (6 PPM°C); Various electrical properties: dielectric constant, dielectric loss, bulk resistivity, dielectric strength are good; It has good mechanical properties, higher bending strength than Al2 O3 and BeO ceramics, and can be sintered under normal pressure. Good light transmission and non-toxic Ceramic SiP and Metal SiP Based on Ceramic Substrate
SiP packaging is generally divided into three types by process or material: plastic SiP, ceramic SiP and metal SiP. As mentioned above, plastic SiP is mainly based on organic substrates, which are mostly used in commercial products. It is small, light and cheap, and has the advantages of large quantities and low cost, but it has relatively poor heat dissipation, stability and airtightness. Ceramic SiP and metal SiP are mainly based on ceramic substrates. HTCC substrates are generally used for ceramic SiP, while LTCC substrates are mostly used for metal SiP. AlN substrates can be used for high-power products with high heat dissipation requirements. Ceramic SiP features include: good sealing, good heat dissipation, good resistance to extreme temperature, easy disassembly, easy analysis of problems; smaller size than metal SiP, suitable for large-scale complex chips, aerospace and other rigorous
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Fig. 5.3 Ceramic and metal package
environmental applications which require air tightness requirements; expensive, long production cycle, larger weight and volume than similar plastic products. Metal SiP features include: good sealing, good heat dissipation, good resistance to extreme temperature, easy disassembly, high flexibility; but relatively large size, fewer pins, not suitable for complex chips, more expensive, long production cycle, need to assemble metal shell and substrate, complex process, multiple applications in MCM design, more common applications in the aerospace field. Ceramic and metal package or SiP have the characteristics of good heat dissipation, good airtightness and high reliability. In addition, compared with plastic package, ceramic package and metal package are both hollow structures, which have the disassemblable advantage of being easy to find faults and “zero” the problem. Therefore, they are also welcomed by users in aerospace and related fields (Fig. 5.3).
5.1.3 Silicon Substrate In SiP, the silicon substrates usually appear as interposers. Silicon is a very common element, widely found in rock, gravel, and dust. It constitutes 26.4% of the total crust mass, next only to the first oxygen (49.4%). With the development of the semiconductor industry, the purification and application of silicon has brought human beings to the era of silicon and become an important element of civilization in modern human society. With the development and application of advanced packaging, highly mature silicon technology in integrated circuit production is fully used to produce highprecision wiring. At the same time, it can make full use of the high thermal conductivity and small warp of the silicon material to match the CTE of the chip, and combine with the advanced TSV technology to produce silicon substrate, which can effectively reduce the packaging volume, achieve high density advanced packaging, and improve the system function density. With the increasing demand for 3D integrated packaging and Wafer Level Packaging technology, the silicon substrates can quickly adapt to these requirements and have convenient technology portability. The mature production technology of
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large-scale integrated circuits is transplanted to the production of silicon substrates, high-quality circuit structure is formed on the silicon substrates, and resulting silicon substrates have lower manufacturing costs. Because silicon is a semiconductor material, its conductivity increases with temperature. Therefore, it is necessary to add an insulating layer between the silicon substrate and the conductive layer to isolate the conductive layer from the silicon substrate. Silicon dioxide is usually selected as the insulating layer, which has mature technology, good insulation and little influence on the thermal conductivity. Cu is generally selected as the main conductive material for silicon substrate. Below, we compare the properties of the HTCC, LTCC, ALN, organic and silicon substrate materials described earlier. As shown in Table 5.3, the designer can select the appropriate substrates according to the requirements of the actual project. After the introduction of the substrate, the corresponding package will be discussed, for example, organic substrate corresponding to plastic package, HTCC substrate corresponding to ceramic package, LTCC substrate corresponding to metal package. So, what package should the silicon substrate correspond to? The most widely used silicon substrates are the advanced packaging and related technologies that we will discuss below. Table 5.3 Comparing the properties of five substrate materials Properties
HTCC
LTCC
ALN
Organic substrate
Silicon substrate
Dielectric constant (DK)
9.8
4.2–8.0
8.8
3.6–4.7
11.5
Dielectric loss (DF) (×10–4 ) 1 MHz–2 GHz
5–9
5–9
1–170
5–9
5–9
Thermal expansion coefficient (PPM/°C)
6.8
4–6
4.5
14–18
3–5
Thermal conductivity (W/mK)
18–25
3–5
140–260
0.2–0.6
150
Sintering temperature (°C)
1500–1650
800–900
1650–1800
–
–
Bending strength (Mpa)
290
150
400
–
3–8
Dielectric strength (KV/cm)
150
200–400
140–170
–
1–2
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5.2 Advanced Packaging Technology In this section, we introduce four technologies related to advanced packaging, two of which are used to solve the interconnection problem in advanced packaging: TSV and RDL. TSV solves the vertical interconnection problem and RDL solves the planar interconnection problem. The other two are used to solve component problems in advanced packaging: IPD and Chiplet. IPD is to solve the problem of passive devices, while Chiplet is to solve the problem of active devices. Let’s go through them one by one.
5.2.1 TSV Technology TSV (Through Silicon Via) technology is the latest technology to achieve interconnection between chips by making vertical conduction vias between chips and chips, and between wafers and wafers. The diagram and physical photo of TSV are shown in Fig. 5.4. Different from wire bonding chip stacking technology, TSV can maximize the density of chips stacked in three-dimensional direction, minimize the overall size, and greatly improve the chip speed and reduce power consumption. Therefore, TSV has been called the fourth generation packaging technology after wire bonding, TAB and flip chip. 1.
Technical Characteristics of TSV
There is an obvious difference between TSV and conventional packaging technology. The production of TSV can be integrated into different stages of manufacturing process. Generally, there are two schemes, Via-first and Via-last. The comparison of the two schemes is shown in Table 5.4. The TSV generated before the wafer process completion is often referred to as Via-first. At this time, TSV can be made before the metal interconnection at the front end of Fab factory to achieve the Core-to-Core connection. At present, this
Fig. 5.4 TSV diagram and physical photo
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Table 5.4 Comparison of via-first and via-last schemes Via-first
Via-last
Design phase
Before CMOS or BEOL
After BEOL
Intervention time
IC design stage intervention
Start after wafer production complete
Processing location
IDM wafer foundry
OSAT package factory
TSV size
The width of TSV is 5–20 um
The width of the TSV is 20–50 um
Key dimensions
Strict CD control for key dimensions Relative loose CD control for key dimensions
Aspect ratio
Aspect ratio 3:1 to 10:1
Aspect ratio 3:1 to 15:1
Note BEOL (Back End of the Line) IDM (Integrated Design and Manufacture)
scheme has been studied extensively in the field of high-performance devices such as microprocessors, mainly as an alternative to SoC. Via-first can also make TSV in the wafer factory after CMOS is completed, and then finish the back-end packaging. The TSV generated in the packaging production stage often called Via-last. The obvious advantage of Via-last is that the existing integrated circuit production and design processes will not be changed. At present, some manufacturers have started to use Via-last technology in the high-end Flash and DRAM field, which is to create TSV at the edge of chips and stack the chips or wafers. From Table 5.4, it can be seen that the design of the Via-first process needs to be carried out in the IC foundry, and the control of critical dimensions is more stringent than the Via-last process. Through TSV technology, multi chips are stacked and interconnected, reducing the chip area and greatly reducing the length of the overall interconnect. The shortening of the interconnect length can effectively reduce the power consumption required for driving signals. TSV can generally be divided into 3D TSV and 2.5D TSV, which are described below. 2.
Definition and Characteristics of 3D TSV
The 3D TSV refers to the TSV in IC chip body, and connects the chips through 3D TSV. At least one bare chip is overlapped with another bare chip, and the TSV on the chip body enables the upper bare chip to connect and communicate with the bower bare chip and the substrate electrically. The 3D TSV can be divided into two categories based on the spatial relationship between the upper and lower chips connected: the upper and lower chips in the stack are identical, and the upper and lower chips in the stack are different. The upper and lower identical chips can be directly interconnected by TSV. If the upper and lower chips are different, they need to be rerouted by RDL to align the bumps and pads of the upper and lower chips. The design method for 3D TSV can be referred to in Chap. 12 of this book: Cavity, Chip Stack and TSV design, and Chap. 19: SiP Design Flow Based on Advanced Package (HDAP).
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Fig. 5.5 3D TSV and 2.5D TSV diagram
The 3D TSV technology can integrate the Out-of-chip memory devices on the top of the processor chip, to some extent, eliminating the slow bus speed and high power consumption of Out-of-chip memory devices, and can replace them with vertical interconnection structures with high bandwidth and low delay transmission. Products integrated through 3D TSV technology are often referred to as 3D IC, and their key technologies include the following three points: (1) Fabrication of 3D TSV (2) Thinning of chips or wafers to less than 50um (3) Alignment and bonding of chips and wafers. 3.
Definition and Characteristics of 2.5D TSV
Unlike 3D TSV, which create via directly on chips, 2.5D TSV refers to TSV on silicon interposer. A common mode is to place a silicon interposer between the SiP substrate and bare chips, TSV connects the metal layer on the upper and lower surfaces of the silicon interposer. This TSV is called 2.5D TSV. 2.5D TSV is currently widely used in advanced packaging, such as CoWos (Chipon-Wafer-on-Substrate) of TSMC, which uses 2.5D TSV technology. CoWos installs chips on silicon interposer and interconnects them using high density traces on silicon interposer. Through the RDL on silicon interposer, I/O coordination problems for different types of chip stacks can be solved. The design method of 2.5D TSV can be referred to in Chap. 12 of this book: Cavity, Chip Stack and TSV design, Chap. 19: SiP Design Flow Based on Advanced Package (HDAP), and Chap. 24: 2.5D TSV Technology and Design Case (Fig. 5.5).
5.2.2 RDL Technology RDL (Re-Distribution Layer) is the XY plane interconnection which change the pin position of originally designed integrated circuit chip to new locations and together
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Fig. 5.6 Fan-in and fan-out RDL diagrams
with Bump processes to make the integrated circuit suitable for different packaging forms. RDL can be divided into Fan-in and Fan-out depending on the location of the redistribution bumps. Fan-in RDL refers to the presence of RDL Bump on the chip body, and Fan-out RDL refers to the presence of RDL Bump on the Molding outside the chip, as shown in Fig. 5.6. The RDL process is to coat an insulation layer on IC, define new connection patterns by exposure development, and then use electroplating technology to make new metal traces to connect the original Die Pads with the new Bump pins for the purpose of pin redistribution. The metal traces is mainly made of electroplated copper, and nickel-gold or nickel-palladium-gold can also be plated on the copper lines as needed. Advantages of RDL: (1) It can change the original design of Die Pad chip and increase the added value of the original design. (2) Increase the I/O spacing, provide a larger bump area, reduce the stress between the substrate and the components, and increase the reliability of the components. (3) Distribute pins to a surface array to support more pins. (4) Replace part of IC design to speed up IC development time. As chip requirements for more input/output (I/O) increase, traditional Bond Wire packages will not effectively support thousands of I/O chips. I/O pads are reassigned to bump pads by RDL and mounted on PCB board by Flip Chip, which not only reduce chip area, but also support more I/O, greatly reduce inductance, support higher speed signals, and have better thermal conductivity. RDL is often used in Flip Chip design to redistribute chip I/O pads to bump pads without changing the original I/O pad layout of the chip. However, the traditional routing capability may not be enough to handle large-scale designs, because in these designs, the RDL may be very crowded, which may require multiple RDL layers to complete all routing. For the specific design methods of RDL and flip chip in EDA tools, please refer to Chap. 13: RDL and Flip Chip Design of this book.
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5.2.3 IPD Technology IPD is the abbreviation of Integrated Passive Device. It uses the process of wafer on silicon, glass or ceramic substrates to etch different graphics using photolithography technology to form different devices, which enables high-density integration of various passive components such as resistors, capacitors, inductors, Balun and filters. With the improvement of semiconductor manufacturing capability, from submicron to nano-phase, the integration of active electronic components is also greatly improved, and the demand for passive components with active components is also increasing rapidly, and the trend is still increasing. It requires more space to place these passive components in package, which necessarily increases the overall size of the package, and requires a technology to solve the growing problem of passive components. IPD, originally designed to replace traditional passive chip components, has been widely used in high-brightness LED silicon integration, RF devices, digital and hybrid circuits. At present, IPD technology has become a bridge between the front and back processes of semiconductors, and also an important part of wafer packaging and TSV application. IPD chips have better electrical performance, and in advanced packaging integration, they can be stacked with active chips to achieve the shortest interconnection, which improves the electrical performance of the whole system and greatly reduces the size. IPD technology can save PCB space, lower cost, have IP protection and better electrical performance. Figure 5.7 show the comparison of circuits before and after IPD. The 58 passive components are replaced by three IPD chips, which not only makes the material supply easier, but also requires fewer weld points, simplifies the circuit and improves the reliability.
Fig. 5.7 Comparison of circuit before and after using IPD
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5.2.4 Chiplet Technology 1.
What is Chiplet?
Chiplet, as its name implies, is a small chip, and we can think of it as a hightech version of Lego building blocks. First, decompose the complex functions, then develop a variety of “chiplets” with a single specific function that can be modular assembled, such as data storage, computing, signal processing, data flow management, and so on. On this basis, an integrated system of chiplet is built. Chiplet technology is like building blocks that encapsulate some pre-produced chips to form a system-level chip through advanced packaging technology. These basic bare chips are Chiplet. Chiplet can be made with more reliable and cheaper technology. Smaller silicon wafers themselves are not susceptible to manufacturing defects, and Chiplets manufactured in different processes can be combined organically through SiP technology (Fig. 5.8). The concept of Chiplet is now a major concern, from CHIPS project of DARPA to Foveros of Intel, both sees Chiplet as an important fundamental technology for future chips. The concept of Chiplet originated from the DARPA CHIPS (Common Heterogeneous Integration and IP Reuse Strategies) project. Since the most advanced SoCs are not always acceptable for small-scale applications, in order to improve overall system flexibility and reduce product design time, the CHIPS plan seeks to create a new paradigm for IP reuse, which is Chiplet. Chiplet is a new mode of chip design. To achieve Chiplet, a new IP reuse mode, advanced packaging technology is required to encapsulate multiple silicon chips in one package. To achieve Chiplet’s vision of high flexibility, high performance and low cost silicon reuse, advanced packaging technologies such as 3D integration technology must be used.
Fig. 5.8 Chiplet diagram
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What is IP?
IP (Intelligent Property) is the general term for integrated circuits with intellectual property core. It is a repetitively validated macro module with specific functions that can be transplanted into different semiconductor processes. At SoC stage, IP core design has become an important task for ASIC circuit design companies and FPGA providers, as well as a reflection of their strength. For the development software of FPGA, the richer the IP core it provides, the more convenient the design of the user and the higher the market occupancy. At present, the IP core has become the basic unit of SoC system design and has been exchanged, transferred and sold as an independent design result. IP cores correspond to three categories that describe the functional behavior, namely Soft IP Core, Firm IP Core, and Hard IP Core. (1)
(2)
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Soft IP Core refers to the register transfer level (RTL) model before synthesis in EDA design field. Specifically in the design of the FPGA, it refers to the hardware language description of the circuit, including logical description, netlist and help documents. Soft IP Core is only emulated by function and need to be integrated and layout before used. Its advantages are high flexibility, portability, allowing users to configure themselves; its disadvantages are low predictability of modules, the possibility of error in subsequent design, and a certain design risk. Soft IP Core is the most widely used form of IP core. It is usually submitted to users in HDL text form. It is optimized for RTL level design and functional validation, but it does not contain any specific physical information. With the help of EDA synthesis tool, it can integrate with other external logic circuits and devices with different performance according to different semiconductor processes. Firm IP Core refers to a netlist with planned information in the field of EDA design. It can be seen as a soft core with layout planning in the design of FPGA, which is usually provided as a mixture of RTL code and corresponding netlist. The design flexibility of Firm IP Core is slightly less than that of the Soft IP Core, but the reliability of the core is much improved. At present, Firm IP Core is also one of the main forms of IP core. The design degree of Firm IP core is between Soft IP Core and Hard IP Core. Hard IP Core refers to a validated design layout in the field of EDA design, in FPGA design, it refers to a design with fixed layout and process, which has been validated by front-end and back-end, and cannot be modified by designers. There are two reasons why it cannot be modified: first, the system design has strict timing requirements for each module, which does not allow disruption of the existing physical layout; second, the requirement for intellectual property protection, which does not allow designers to make any changes to it. Hard IP core is a physical design based on semiconductor process. It has a fixed topological layout and specific process, and has been verified by the process, and has guaranteed performance. It is provided to users in the form of circuit physical structure mask and a complete set of process files, which are a complete set of technologies that can be used.
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From IP to Chiplet
When a hard IP core is provided as a silicon chip, it becomes a Chiplet. We can understand that the Chiplet in SiP corresponds to the hard IP core in SoC. Chiplet is a new IP reuse mode, which is silicon-level IP reuse. To design a SoC, the previous method was to purchase some IP, Soft IP core, Firm IP core or Hard IP core from different IP vendors, combine with self-developed modules, integrate into a SoC, and then complete the whole process of chip design and production on chip process node. With Chiplet, we don’t need to design and produce some IPs by ourselves, instead, we just need to buy some chiplets and integrate in one package to form a SiP. So Chiplet can be seen as a hard IP core, but it’s provided as a chip. In this sense, Chiplet is a new IP reuse mode, which is silicon chip level IP reuse. Chips integrated in Chiplet mode will be a “super” heterogeneous system, bringing more flexibility and new opportunities. 4.
Advantages of Chiplet
The advantages of Chiplet include the following: (1)
Flexibility of process selection
With Chiplet mode, chips with multiple process nodes can be integrated in one system. This is also an important factor for Chiplet to support rapid development and reduce implementation costs. In chip design, the newest process is not always the most appropriate for different purposes and types of circuits. In the current single-chip SoC system, the system can only be implemented on one process node. For many functions, it is unnecessary and difficult to use the latest high-cost and high-risk processes. If use Chiplet, we have more options. For modules that seek performance, such as high-performance CPUs, the latest technology is available, other functional modules, such as memory, analog interfaces, can select the most mature process technology. (2)
Flexibility in architecture design
The Chiplet system is a “super” heterogeneous system, which adds new dimensions to traditional SoC, including at least spatial dimensions and process selection dimensions. First, advanced integration technology can dramatically increase the size of the chip as it expands in 3D space. Secondly, combined with the process flexibility described above, we may have a more reasonable trade-off between functionality and process in the architecture design. Third, the system architecture design, especially the interconnection between modules, has more room for optimization. Chiplet is the interconnection of silicon chips, with significant improvements in bandwidth, delay and power consumption. (3)
Flexibility of business modes
The Chiplet mode offers a new choice beyond traditional IP and chip providers: Chiplet providers. Chiplet provides a new form of product to increase the potential market. For some Foundry manufacturers with strong silicon implementation
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capabilities, they will gradually evolve into a dedicated Chiplet supplier, which will further benefit the development of SiP and advanced packaging technology. 5. (1)
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Challenges for Chiplet The challenge of integration technology, Chiplet mode is based on advanced packaging technology, which must be able to achieve low cost and high reliability. With the slowdown of the deployment of IC advanced technology, packaging technology has gradually become the focus of attention, as can be seen from the positive shift of TSMC to packaging and development of InFo, CoWos and other advanced packaging technologies. The challenge of quality and good product rate, in current IP reuse methods, there are mature methods for IP testing and verification. But for Chiplet, this is still a question to explore. Although Chiplet is a certified product, however, it still has a yield problem, and if there is a problem with one of the Chiplet silicon chips in the SiP, the whole system will be affected at a high cost. Therefore, Chiplet integrated into SiP ensures 100% fault-free as possible. The challenge of testing coverage, how the integrated SiP is tested. When multiple Chiplets are encapsulated together, each chiplet can be connected to limited pins. Some Chiplets may not be directly accessible from the pin outside the chip, which also presents new challenges for chip testing.
In the post-Moore’s Law era, IP hard cores will be chipped gradually to form Chiplet, and then encapsulated as SiP to form a system, making Moore’s Law continue, which is also a revolution of Moore’s Law.
5.3 Advanced Packaging Technology Advanced Packaging, or High Density Advanced Package (HDAP), has become a very popular topic. So what kind of packaging is called advanced packaging? Here, based on the author’s years of design experience, we give the definition of advanced packaging here. Advanced Packaging Definition: Advanced design ideas and advanced integration technology are used to reconstruct the chip at package level, and effectively improve the function density of the system. We can call it advanced packaging. There are four key words in this definition: ➀ advanced design idea, ➁ advanced integration technology, ➂ package level reconstruction, ➃ improving function density of system. (1)
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The advanced design idea is different from the traditional packaging design method, and can effectively improve the function density of the package, such as: chip stacking, chip embedding, Chiplet and so on. Advanced integration technology refers to the technology that is different from traditional packaging technology and can also improve the function density, such as TSV, RDL, Flip Chip, IPD, etc.
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Package level reconstruction, refers to the reconstruction and optimization of system performance without changing the original functions of the system, the reconstruction of the functions originally implemented at the chip level (SoC) to the package level, and even to improve the original performance. For example, the concept of chiplet is very consistent with the meaning of package level reconstruction, because of TSV and 3D integration technology, the function units which are far away in the original SoC may have shorter space distance in package level reconstruction, so the performance will be improved. Function density refers to the number of function units in a unit volume, which can be directly understood as the number of transistors in a unit volume. For SiP, the more function density in space, the more advanced it will be. For a detailed definition and explanation of function density, please refer to Chap. 1: from Moore’s law to function density law.
Advanced design ideas need advanced integration technology to support, advanced integration technology also needs advanced design ideas to guide, and the two complement each other, inseparable. Package level reconstruction and function density can be used as criteria for judging advanced nature of the package. In recent years, advanced packaging technology is emerging, and the terms are also emerging in an endless stream, which makes people a little dazzled. At present, there are at least dozens of advanced packaging related names that can be listed. For example, TSV, RDL, IPD, and Chiplet mentioned earlier, as well as WLP (Wafer Level Package), FIWLP (Fan-in Wafer Level Package), FOWLP (Fan-Out Wafer Level Package), eWLB (embedded Wafer Level Ball Grid Array), CSP (Chip Scale Package), WLCSP (Wafer Level Chip Scale Package), CoW (Chip on Wafer), WoW (Wafer on Wafer), FOPLP (Fan-Out Panel Level Package), InFO (Integrated Fan-Out), CoWoS (Chip-on-Wafer-on-Substrate), HBM (High-Bandwidth Memory), HMC (Hybrid Memory Cube), Wide-IO (Wide Input Output), EMIB (Embedded Multi-Die Interconect Bridge), Foveros, Co-EMIB, ODI (Omni-Directional Interconnect), 3D IC, SoIC, X-Cube, etc. How do you distinguish and understand these dazzling advanced packaging technologies? For distinguishing, advanced packaging can be divided into two categories: (1) advanced packaging technology based on XY plane extension, mainly through RDL for signal extension and interconnection; (2) advanced packaging technology based on Z axis extension, mainly through TSV for signal extension and interconnection. When it comes to advanced packaging, there are three manufacturers we can’t avoid: TSMC, Intel and SAMSUNG. Perhaps you will find it strange that these manufacturers are well-known manufacturers of integrated circuits. How did they start to develop packaging? Yes, they do. This also reflects a feature of advanced packaging, the integration of chip manufacturing and packaging.
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5.3.1 Advanced Packaging Based on XY Plane Extension First, let’s look at the advanced packaging technology based on XY plane extension, where XY plane refers to XY plane of wafer or chip. The distinct feature of this kind of packaging is that it does not have TSV, and its signal extension is mainly achieved by RDL layer, usually without substrate, so its RDL depends on the silicon of the chip or on additional Molding. Refer to Fig. 5.6. Because the final packaging product usually does not have a substrate, such packaging is relatively thin and is now widely used in the smartphone field. 1.
FOWLP (Fan-out Wafer Level Package)
FOWLP (Fan-out Wafer Level Package) is a kind of WLP (Wafer Level Package), so we need to know WLP first. Prior to the advent of WLP technology, the traditional packaging process mainly proceeded after bare chip dicing, first Dicing the wafer, then packaging into various forms, as shown in Fig. 5.9. WLP was introduced around 2000. There are two types: Fan-in and Fan-Out. The definitions of Fan-in and Fan-Out are shown in Fig. 5.6. WLP wafer-level packaging differs from traditional packaging in that most of the process is performed on the wafer. That is, packaging the wafer as a whole, then cutting the chips after the packaging is completed. The packaging process is shown in Fig. 5.10. Because the encapsulated chips are almost identical in size to the bare chips, they are also known as CSP (Chip Scale Package) or WLCSP (Wafer Level Chip Scale Package). This kind of package conforms to the market trend of light, small, short and thin consumer electronic products. Parasitic capacitance and inductance are relatively small, and it has the advantages of low cost and good heat dissipation.
Fig. 5.9 The diagram of traditional packaging process
Fig. 5.10 The diagram WLP wafer level packaging process
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At beginning, WLP mostly uses Fan-in type, which can be called Fan-in WLP or FIWLP. It is mainly used on chips with smaller area and fewer pins. FIWLP already produces RDL and Bump on bare wafers when the wafer is not cut. The final twodimensional planar size of the packaging device is the same as the size of the chip itself. The device is fully encapsulated and then separated by dicing. FIWLP is a unique packaging and has a distinct feature of true bare chip size, which is usually used for bare chips with fewer pins and smaller sizes. With the improvement of IC technology, the chip area is reduced and there are not enough space for pins in chip area. Therefore, the Fan-Out WLP packaging form, also known as FOWLP, is derived to make full use of RDL to connect beyond the chip area to get more pins. FOWLP, because RDL and Bump are brought out to the periphery of bare chip, it is necessary to split the bare chip wafer first, and then reconstitute the independent bare chip into the wafer process. On this basis, the final package is formed by batch processing and metallized wiring interconnection. The packaging process is shown in Fig. 5.11. FOWLP uses RDL wiring directly on Die Pad without bonding wires or substrates. It is relatively inexpensive, has smaller packaging size and is thin. However, creep fatigue and weld seam problems are evident in large-size packages (e.g., over 30 mm × 30 mm). FOWLP can be divided into Die First and Die Last according to the process. Die First process simply means putting the chip on first, then RDL wiring. Die Last means doing RDL wiring first, testing the qualified unit and then putting the chip on. FOWLP saves nearly 30% of the packaging cost by eliminating the need for substrate materials, makes the packaging thinner and helps to improve product competitiveness. Whether using Fan-in or Fan-out, WLP wafer-level packaging and PCB connections are in the form of Flip Chip, with the active side of the chip facing down to
Fig. 5.11 The diagram of FOWLP process
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Fig. 5.12 The comparation diagram FIWLP, FOWLP and InFO
the PCB to achieve the shortest circuit path, which also guarantees higher speed and less parasitic effects. On the other hand, due to the use of batch packaging, the entire wafer can be fully encapsulated at one time, and cost reduction is another driving force for wafer-level packaging. eWLB is a widely used FOWLP introduced and used by Infineon, NXP and other companies. In addition, there are other names for FOWLP, which are similar in process, although the names are somewhat different. 2.
INFO (Integrated Fan-out)
InFO (Integrated Fan-out) is an advanced FOWLP packaging technology developed by TSMC in 2017. It is an integration on FOWLP process, which can be understood as the integration of multiple chip Fan-Out process, while FOWLP focuses on the Fan-Out packaging process itself. InFO gives space for chip integration and can be used for RF and wireless chip packaging, processor and baseband chip packaging, graphics processor and network chip packaging. Figure 5.12 are comparation diagram of FIWLP, FOWLP, and InFO. Apple’s iPhone processor was manufactured by Samsung in its early years, but since Apple A11, TSMC has taken orders for two generations of iPhone processors. One of the keys is that TSMC new packaging technology InFO, allows direct interconnection between chips, reduces thickness, and frees up valuable space for batteries or other components. Apple has been using InFO packaging for iPhone series and will continue to use it, such iPhone X, iPhone 11, iPhone 12 and other brands of future phones. The join of Apple and TSMC has changed the application of FOWLP technology, which will make FOWLP (InFO) packaging technology gradually accepted and widely used in the market. 3.
FOPLP (Fan-out Panel Level Package)
The FOPLP (Fan-out Panel Level Package) uses FOWLP ideas and technologies, but uses a larger panel, so it can produce packaging products several times than 300 mm silicon wafer.
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Fig. 5.13 Area comparison between FOWLP and FOPLP
FOPLP technology is an extension of FOWLP technology, which makes Fan-Out process on square carriers with a larger area than 300 mm wafers. Therefore, it is called FOPLP packaging technology. The panel can use PCB carriers or glass carriers for LCD panels. Currently, FOPLP uses PCB carriers such as 24 * 18 inch (610 * 457 mm) with an area of approximately 4 times that of 300 mm silicon wafer, which can be simply considered as an advanced packaging product that can produce 4 times as many as 300 mm silicon wafer in one process. Figure 5.13 shows a comparison between FOWLP and FOPLP. Like the FOWLP process, FOPLP technology integrates the pre-packaging and post-packaging processes and treats them as one-time packaging processes, thus greatly reducing production and material costs. FOPLP uses the production technology on PCB to produce RDL. Its line width and line spacing are currently larger than 10 um. SMT devices are used to mount chips and passive devices. Because its panel area is much larger than the area of the wafer, more products can be packaged at one time. FOPLP has a greater cost advantage over FOWLP. At present, all major packaging companies in the world, including Samsung and ASE, are actively engaged in FOPLP process technology. 4.
EMIB (Embedded Multi-die Interconnect Bridge)
EMIB (Embedded Multi-Die Interconnect Bridge) advanced packaging technology was proposed and actively applied by Intel, which is different from the three advanced packaging described above. EMIB is a kind of substrate packaging. It is introduced in this section because EMIB does not have TSV, and it is also an advanced packaging technology based on XY plane extension. EMIB concept is similar to 2.5D packaging based on silicon interposer, with local high density interconnection through silicon bridges. Comparing with traditional 2.5 packaging because EMIB packaging is no TSV, so EMIB technology has the advantages of normal packaging yield, no additional process and simple design. Traditional SoC chips, CPU, GPU, memory controller and IO controller can only be manufactured in one process. With EMIB technology, CPU and GPU require a high level of technology, they can use 10 nm technology, and 14 nm technology for
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Fig. 5.14 EMIB diagram and physical sectional view
IO unit and communication unit, 22 nm technology for memory part, and then use EMIB advanced packaging technology to integrate the three different processes into one processor. EMIB silicon bridge chips are smaller, more flexible and more economical than silicon interposer. EMIB packaging technology can package CPU, IO, GPU or even chip such as FPGA, AI together according to needs. It can package chips with different processes such as 10, 14, 22 nm into a single chip to meet the needs of flexible business. Figure 5.14 are EMIB diagrams and physical sectional view. Through EMIB, the KBL-G platform integrates Intel Core processor with AMD Radeon RX Vega M GPU, it has Intel Processor’s powerful computing power, AMD GPU’s excellent graphics capabilities, and has an excellent heat dissipation experience. This chip has made history and has taken the product experience to a new level.
5.3.2 Advanced Packaging Based on Z-Axis Extension Advanced packaging technology based on Z-axis extension mainly uses TSV for signal extension and interconnection. Previously, we introduced that TSV can be divided into 2.5D TSV and 3D TSV, through which multiple chips can be stacked and interconnected vertically. In 3D TSV technology, the chips are close to each other, so the delay is less. In addition, the shortening of the interconnect length reduces the parasitic effect and makes the device can run at a higher frequency, which translates into performance improvement and greater cost reduction. TSV technology is a key technology for three-dimensional advanced packaging, including IDM, Foundry, OSAT, emerging technology developers, universities and technology alliances, many research institutions have carried out various research and development on the process of TSV. In addition, readers need to note that although advanced packaging technology based on Z-axis extension mainly uses TSV for signal extension and interconnection, RDL is also indispensable. For example, if the TSV of the upper and lower chips cannot be aligned, local interconnection with RDL is required.
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Fig. 5.15 CoWoS structure diagram
1.
CoWoS (Chip-on-Wafer-on-Substrate)
CoWoS (Chip-on-Wafer-on-Substrate) is a 2.5D packaging technology introduced by TSMC. CoWoS install chips on silicon interposer, interconnects it with a high density routing on the silicon interposer, and then installs interposer on substrate, as shown in Fig. 5.15. CoWoS and the InFO mentioned earlier all come from TSMC, CoWoS has a Silicon Interposer, InFO does not. CoWoS is targeted at the high end of the market with a large number of connections and packaging sizes. InFO has a smaller package size and fewer connections for the cost effective market. The process flow of CoWoS is shown in Fig. 5.16. (1) Install the chip on Silicon Interposer Wafer through uBump and fill in the underfill protection chip and the connected structure. (2) Install the Interposer Wafer on the carrier in reverse with the chip. (3) Thin Interposer Wafer and make RDL and Bump. (4) Transfer the Interposer Wafer from the carrier to tape and cut the Wafer. (5) Remove the cut chip from the tape and mount it on the substrate. TSMC started mass production of CoWoS in 2012. Through this technology, multiple chips are packaged together, and through high density interconnection of silicon interposer, it achieves the effect of small package size, high performance and low power consumption. CoWoS technology has a wide range of applications. The Google chip TPU2.0, INVIDIA GP100 both use CoWoS technology. CoWoS also contributes to AI. Currently, CoWoS has been supported by high-end chip manufacturers such as NVIDIA, AMD, Google, XilinX, and etc. 2.
HBM (High-Bandwidth Memory)
HBM (High-Bandwidth Memory) is mainly targeted at the high-end graphics card market. HBM uses 3D TSV and 2.5D TSV technology, to stack multiple memory chips together via 3D TSV, to interconnect stacked memory chips and GPUs via 2.5D TSV of interposer. Figure 5.17 shows the HBM technical diagram and physical profiles. There are currently three versions of HBM, namely HBM, HBM2 and HBM2E, with bandwidth 128 GBps/Stack, 256 GBps/Stack and 307 GBps/Stack, respectively. The latest HBM3 is still under development. AMD, NVIDIA and Hynix introduce HBM standard. AMD first used HBM standard in its flagship graphics card, with a video bandwidth of 512 GBps. NVIDIA
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Fig. 5.16 CoWoS process flow diagram
Fig. 5.17 HBM technical diagram and physical profile
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Fig. 5.18 HMC diagram and physical profile
followed suit, and then implemented the 1TBps memory bandwidth using HBM standard. Compared with DDR5, the performance of HBM is improved more than three times, but the power consumption is reduced by 50%. 3.
HMC (Hybrid Memory Cube)
The standard for HMC (Hybrid Memory Cube) is driven by Micron, which targets the high-end server market, especially for multiprocessor architectures. HMC uses stacked DRAM chips to achieve greater memory bandwidth. In addition, HMC integrates Memory Controller into DRAM stacked packaging through 3D TSV integration technology. Figure 5.18 show the HMC technical diagram and physical profile. Comparing HBM and HMC, we can see that they are very similar, both stack DRAM chips and interconnect through 3D TSV, and there are logical control chips underneath them. The difference between them is that HBM is interconnected through interposer with GPU, while HMC is directly installed on substrate, no interposer and 2.5D TSV. In HMC stack, the diameter of the 3D TSV is about 5–6 um, the number exceeds 2000+, DRAM chips are usually thinned to 50 um, and the chips are connected by 20 um MiroBump. Memory controllers used to be designed in processors, so the design of memory controllers in high-end servers is complex when a large number of memory modules are required. Now the memory controller is integrated into memory module, the design of the memory controller is greatly simplified. In addition, HMC uses SerDes to implement high speed interfaces, which are suitable for situations where processors and memory are far away. 4.
Wide-IO (Wide Input Output)
Wide-IO (Wide Input Output) technology, powered by Samsung, has reached the second generation. It can achieve up to 512 bits of memory interface width, up to 1 GHz of memory interface operation frequency, and 68 GBps of total memory bandwidth, which is twice the bandwidth of DDR4 interface (34 GBps). Wide-IO is achieved by stacking Memory chips on Logic chips, which are connected by 3D TSV with Logic chips and substrate, as shown in Fig. 5.19. Wide-IO has the advantage of vertical stacked packaging with TSV architecture, which helps to create a mobile memory with speed, capacity and power characteristics to meet the needs of mobile devices such as smart phones, Pads, handheld
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Fig. 5.19 Wide-IO diagram and physical profile
game consoles. Its main target market is mobile devices that require low power consumption. JEDEC points out that the inherent vertical stacking architecture allows Wide-IO2 to achieve four times more bandwidth than LPDDR4 at one-fourth I/O speed. 5.
Foveros (Active Interposer)
In addition to EMIB advanced packaging described earlier in this chapter, Intel introduced Foveros active interposer technology. In Intel’s technical introduction, Foveros is called 3D Face to Face Chip Stack for heterogeneous integration. EMIB differs from Foveros in that the former is a 2D integration technology, while the latter is 3D stacked integration technology. Compared with EMIB, Foveros is more suitable for smaller size products or products with higher memory bandwidth requirements. In fact, there is little difference between EMIB and Foveros in the performance and function. They all integrate chips of different specifications and functions to play different roles. However, in terms of volume and power consumption, the advantages of Foveros are apparent. Foveros transmits very low power per bit of data. Foveros technology deals with Bump spacing reduction, density increase, and chip stacking technology. The first Foveros 3D stacked chip, LakeField, integrates a 10 nm Ice Lake processor with a 22 nm core and has full PC functionality, but is only a few cents in size. Although Foveros is a more advanced 3D packaging technology, it is not a substitute for EMIB, which Intel will use in subsequent manufacturing. Figure 5.20 is a Foveros 3D packaging technology diagram and product profile. 6.
Co-EMIB (Foveros + EMIB)
Fig. 5.20 Foveros 3D packaging technology diagram of and product profile
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Fig. 5.21 Co-EMIB technical diagram
Co-EMIB is the combination of EMIB and Foveros. EMIB is mainly responsible for the horizontal connection, which makes chips from different cores stitch together like a jigsaw. Foveros is a vertical stack, just like tall buildings, each floor can have a completely different design, such as gym on one floor, office on the second floor, apartment on the third floor. The packaging technology that combines EMIB and Foveros, called Co-EMIB, is a more flexible way to make chips that can continue to be stitched horizontally while stacked. Therefore, the technology can stitch multiple 3D Foveros chips together via EMIB to produce a larger chip system. Figure 5.21 are a technical diagram of Co-EMIB. The ODI (Omni-Directional Interconnect) is the key to achieve the performance comparable to that of a single chip provided by the Co-EMIB packaging technology. ODI has two different types. In addition to connecting elevator types of different layers, there are overpasses connecting different three-dimensional structures and sandwiches between layers, which make different chip combinations extremely flexible. ODI enables both horizontal and vertical interconnection of chips. ODI provides greater pin density for wiring and connection than traditional TSVs, further reduces chip resistance and latency, and has higher interconnection bandwidth than TSVs. ODI requires a much smaller number of passes in bare chips than traditional TSV, which can minimize the area of the bare chip, accommodate more transistors and further improve performance. Co-EMIB transforms chip design thinking from a planar puzzle to a stack using a new 3D + 2D packaging method. Therefore, in addition to revolutionary new computing architectures such as quantum computing, CO-EMIB is arguably the best way to maintain and continue the existing computing architecture and ecosystem. Figure 5.22 show a comparison of EMIB, Foveros, and CO-EMIB technology diagrams and product profiles shown by Intel. 7.
SoIC (System-on-Integrated-Chips)
SoIC, also known as TSMC-SoIC, is a new technology proposed by TSMC (Systemon-Integrated-Chips), which is expected to be mass produced in recently. What is SoIC exactly? SoIC is an innovative multi-chip stacking technology that enables the integration of processes below 10 nm in a wafer level. The most striking feature of this technology is that it has no-Bump bonding structure, so it has higher integration density and better performance.
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Fig. 5.22 EMIB, Foveros and CO-EMIB technical diagrams and product profile (Intel)
SoIC contains two forms of technology, CoW (Chip-on-wafer) and WoW (Waferon-wafer). From the description of TSMC, SoIC is a direct bonding technology of WoW or CoW, belonging to Front-End 3D technology (FE 3D), while InFO and CoWoS mentioned earlier belong to Back-End 3D technology (BE 3D). TSMC and Siemens EDA have collaborated on SoIC technology and launched related design and verification tools. Figure 5.23 compare SoC (System-on-Chip) integration with SoIC (Systemon-Integrated-Chips) integration. As you can see from the diagram, SoIC technology divides a large SoC into several small SoCs and integrates them through 3D technology. Specifically, the processes of SoIC and 3D IC are somewhat similar. The key of SoIC is to achieve a joining structure without bumps, and its TSV density is higher than that of traditional 3D IC. The interconnection between multi-layer chips is achieved directly through very small TSV. Figure 5.24 show a comparison of TSV density and Bump size between 3D IC and SoIC. It can be seen that the TSV density of SoIC is much higher than that of 3D IC. At the same time, the direct bonding technology of no-Bump is also used for the interconnection between chips. With smaller chip spacing and higher integration density, SoIC products also have higher function density than traditional 3D IC.
Fig. 5.23 Comparison of SoC integration and TSMC-SoIC integration
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Fig. 5.24 Comparison of TSV density and Bump size between 3D IC and SoIC (TSMC)
TSMC’s SOIC technology can support processes below 10 nm, which means that future chips can achieve better performance than conventional 3D ICs in nearly the same volume, so the industry is very interested in this technology. This technology can not only maintain Moore’s law continuously, but also hopefully further break through the performance of a single chip. In fact, it is also a concrete reflection of t function density law. 8.
X-Cube (eXtended-Cube)
X-Cube (eXtended-Cube) is a 3D integration technology announced by Samsung that can accommodate more memory in a smaller space and reduce the signal distance between cells. X-Cube is used in processes that require high performance and bandwidth, such as 5G, AI, wearable or mobile devices, and applications that require high computing power. X-Cube uses TSV technology to stack SRAM on top of the logical unit, allowing more storage in a smaller space. As can be seen from the X-Cube technology illustration in Fig. 5.25, X-Cube 3D packaging allows stacked packaging of multiple chips, making the finished chip structure more compact than previous 2D parallel packaging. TSV technology is used between the chips to reduce power consumption and increase the transmission rate. This technology will be applied to the cutting-edge fields such as 5G, AI, AR, HPC, mobile chips and VR. X-Cube greatly improves performance because it minimizes the signal distance between storage units. More flexibility for engineers. X-Cube technology significantly reduces the signal transmission distance between chips, improves data transmission speed, reduces power consumption, and can also customize memory bandwidth and density to meet customer needs. Now, X-Cube technology can support 7Nm and 5 nm processes, Samsung will continue to work with global semiconductor companies to deploy the technology in a new generation of high-performance chips.
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Fig. 5.25 Samsung X-cube technology display graph (Samsung)
5.3.3 Summary of Advanced Packaging Technology In the previous section, we describe 12 kinds of the most mainstream advanced packaging technologies today. Table 5.5 is a cross-sectional comparison of these mainstream advanced packaging technologies. From the comparison, we can see that the emergence and rapid development of advanced packaging have been in the past 10 years. Its integration technology mainly includes 2D, 2.5D, 3D, 3D + 2D, 3D + 2.5D, low, medium, high and very high function density. The application fields include 5G, AI, wearable devices, mobile devices, high performance servers, high performance computing, high performance graphics cards and so on. Major application manufacturers include TSMC, Intel and SAMSUNG, which also reflect the trend of integration of advanced packaging and chip manufacturing. Finally, we conclude that the purpose of advanced packaging is to improve function density, shorten interconnect length, improve system performance, and reduce overall power consumption.
5.3.4 Elements: RDL, TSV, Bump and Wafer When describing the advanced packaging technology, we found that almost all advanced packaging cannot be separated from the four elements: RDL, TSV, Bump and Wafer. Therefore, we call them the four elements of advanced packaging. Figure 5.26 shows the relationship between four elements of advanced packaging: RDL is mainly responsible for the extension of signal in XY plane, TSV is mainly responsible for the extension of signal in Z axis, Bump is mainly responsible for the
2009
FOWLP
INFO
FOPLP
EMIB
CoWoS
HBM
HMC
Wide-IO
Foveros
Co-EMIB
TSMC-SoIC
X-Cube
1
2
3
4
5
6
7
8
9
10
11
12
2020
2020
2019
2018
2012
2012
2015
2012
2018
2017
2016
Year
Advanced package
3D
High
Very high
High
3D + 2D 3D
Medium
Medium
3D
3D
High
High
3D + 2.5D 3D
Medium
Medium
Medium
Medium
Low
Function density
2.5D
2D
2D
2D
2D
2D/2.5D/3D
Table 5.5 Comparison of the mainstream advanced packaging technologies
5G, AI, wearable or mobile devices
5G, AI, wearable or mobile devices
High end server, high end enterprise, HPC
High end server, high end enterprise, HPC
High end smartphone
High end server, high end enterprise, HPC
Graphics, HPC
High end server, high end enterprise, HPC
Graphics, HPC
Mobile devices, 5G, AI
iPhone, 5G, AI
Smartphones, 5G, AI
Applications
SAMSUNG
TSMC
Intel
Intel
SAMSUNG
Micron/SAMSUNG/IBM/ARM/Microsoft
AMD/NVIDIA/Hynix/intel/SAMSUNG
TSMC
Intel
SAMSUNG
TSMC
Infineon/NXP
Major manufacturers
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Fig. 5.26 4 elements of advanced packaging: RDL, TSV, bump and wafer
connection of signal in chip interface, Wafer is used as carrier of integrated circuit and media and carrier of RDL and TSV. Table 5.6 gives a comparison of the four elements of advanced packaging (HDAP), among which TSV is mainly used in 2.5D and 3D advanced packaging, while the other three are widely used in 2D/2.5D/3D advanced packaging; RDL and TSV will become smaller and denser with the development of technology; Bump will become smaller and smaller; Wafer will become larger and larger, from 6 to 8 inches earlier to now 12 inches and 18 inches for future use. From Table 5.6, we can also see that RDL, TSV and Wafer will exist with the silicon chip for a long time, while Bump will become smaller and disappear for the silicon–silicon interface. Figure 5.27 shows the development trend of Bump. From 100 to 50 um to 30 um to 20 um to 10 um to 5 um, for the silicon–silicon interface, the TSV extensions of the Table 5.6 Comparing the features of 4 elements in advanced packaging HDAP key element
Function
Applications
Changing trend
Duration time
1
RDL
Extend signals in 2D/2.5D/3D XY plane
The density increases, width and clearance decrease
Same with silicon chip
2
TSV
Extend signals in 2.5D/3D Z axis
The size becomes smaller and the density increases
Same with silicon chip
3
Bump
Connect signals on silicon interface
2D/2.5D/3D
Getting smaller and smaller
Will disappear in future for Si interfaces
4
Wafer
IC carrie and carrie for RDL and TSV
2D/2.5D/3D
Getting bigger and Same with bigger silicon chip
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Fig. 5.27 Trends in bump development
chips interface will bond directly, but for the interface between silicon material and the packaging substrate, Bump still plays an important role such as distracting stress concentration and continues to exist, so the four elements of advanced packaging will exist together with silicon Chips. In SoIC technology, the front-end 3D integration technology of TSMC, the connection of silicon–silicon interface is no Bump, but Bump will continue to exist in advanced packaging of chip process backend, and the 4 elements of advanced packaging will also exist for a long time.
5.4 Features and Design Requirements of HDAP 5.4.1 Features of Advanced Packaging (HDAP) 1.
Advanced packaging “emphasizes inside not outside”
The focus of advanced packaging is different from that of traditional packaging. Traditional packaging “emphasizes outside not inside”, and advanced packaging “emphasizes inside not outside”. Traditional packaging focuses more on pin layout and lead-out methods, such as TO, DIP, SOP, SOJ, PLCC, QFP, QFN, PGA, LGA, BGA and so on. These are the external manifestations of packaging. Because there is no concept of integration inside the traditional packaging, so there is no change. Bond wire, TAB and Flip Chip are the three connection modes of chips in traditional packaging, and the modes are relatively fixed. So we can say that traditional packaging “emphasizes outside not inside”. Unlike traditional packaging, advanced packaging basically uses BGA type of package, which lacks external changes and therefore has little attention of outside. Advanced packaging has a variety of internal integration methods, and there are many technologies and problems to be studied. Its main purpose is to improve the function density within the package. So we can say that advanced packaging “emphasizes inside not outside”.
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Fusion of Advanced Packaging and Chip Manufacturing
Traditional packaging and testing is after chip production, so the packaging industry is a relatively independent industry. Advanced packaging improves the integration of packaging production and chip manufacturing. The main manifestations are as follows: 1. Wafers are encapsulated before cutting, such as FIWLP, FOWLPD, etc. 2. Packaging requires more processing techniques on silicon, such as RDL, TSV, etc. 3. Traditional chip manufacturers join the advanced packaging industry chain, such as TSMC, Intel, SAMSUNG, etc. 3.
Interaction between advanced packaging design and chip design
Traditional packaging design is relatively independent, usually after the chip design is completed, the pin position and signal definition of the chip are determined before packaging design. Because there is no concept of integration in traditional packaging, the main task of traditional packaging design is to connect the pin of the chip to the pin of the package, allocate the reasonable pin of the package to the signal, and distribute power and ground to ensure the good quality of the signal. Advanced packaging design phase often overlaps with chip design phase, the pin position and signal definition of the chip are not completely fixed, and the IO port design of the chip can be designed and optimized in collaboration with the packaging design. Therefore, the interaction between advanced packaging design and chip design is intense, and the corresponding requirements for advanced packaging design tools are also put forward. At present, three major EDA suppliers worldwide have introduced toolkits for advanced packaging design. 4.
The most important way to improve system function density
Traditional packaging has no integration function, and the improvement of system function density mainly depends on the improvement of chip integration. Package contributes to the function density of the system by reducing its size. In addition to obtaining minimal packaging size, advanced packaging has flexible and diverse ways of integration, including 2D, 2D + 2.5D, 3D and so on. With the internal integration of chips approaching the limit and Moore’s Law gradually becoming invalid, package internal integration is the main force to improve the function density of system, and has been the focus of attention from chip manufacturers to system manufacturers. Therefore, advanced packaging is the most important way to improve the function density of system.
5.4.2 Relationship Between Advanced Packaging and SiP Advanced packaging technology has two development directions: one is wafer-level packaging (WLP), which can hold more pins under a smaller packaging area; the other is system-level packaging (SiP), which integrates multiple functional chips into one
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Fig. 5.28 Relationship between HDAP and SiP
to compress the module volume and improve the overall functionality, performance and flexibility of system. Generally speaking, SiP is advanced packaging, but their coverage varies. Referring to Fig. 5.28, the relationship between HDAP (High Density Advanced Packaging) and SiP shows that there is a certain overlap between HDAP and SiP, but they have different coverage areas. HDAP covers single-chip packages such as WLCSP, while SiP is all multichip packages. SiP also contains more types of chips and number of chips than advanced packaging, and has higher process flexibility. For example, SiP may contain bond wire, Flip Chip, RDL, TSV hybrid processes. Advanced packaging concepts generally do not include traditional processes such as bond wire. Generally speaking, advanced packaging emphasizes the advancement of process. InFO, CoWoS, HBM, HMC, EMIB, Foveros all adopt advanced technology, which belongs to advanced packaging technology. At least one or two of the four elements RDL, TSV, Bump and Wafer of advanced packaging are available. SiP, on the other hand, puts more emphasis on system implementation. As long as several bare chips are encapsulated in one package and the corresponding system functions are implemented, it can be called SiP, with little emphasis on the advanced technology. Therefore, Advanced Packaging and SiP have common coverage areas, and they have their own characteristics. For HDAP and SiP, from Foundry to OSAT to System user, the entire industry and supply chain of semiconductors are covered, but their concerns vary. Foundry pays attention to the most dense and difficult parts of HDAP, OSAT pays attention to a wide range of areas, from single-chip WLCSP to SiP, and system users pay more attention to SiP. See Fig. 5.28.
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5.4.3 Advanced Packaging and SiP Design Requirements Finally, according to the characteristics of advanced packaging and SiP, we summarize the design requirements of advanced packaging and SiP. (1)
(2) (3) (4)
(5)
(6)
Interconnection planning across design domains (chip design, packaging design, PCB design), visual net optimization, support Die-Interposer-PackagePCB four-level net connection optimization. Support multiple data format inputs to create chips and package libraries, as well as fast parameterized creation of package libraries. Support for a variety of complex processes: 3D TSV, 2.5D TSV and RDL design, Wire Bonding, Flip Chip, Cavity, and Die Stack design. Supports complex layer stackup, blind buried via processes and high density multilayer interconnection for HDI, planar resistor and capacitor synthesis tools for automatic generation of printable passive devices, and design of substrate embedded chips. With excellent 3D design environment, it supports real-time synchronous updating of 3D and 2D environments, 3D component layout operation, 3D measurement, 3D DRC inspection, 3D data input and output, digital prototype simulation and other functions. Advanced simulation and validation platform supports SI, PI, thermal simulation and analysis, and advanced process verification functions.
The above six functional requirements are based on the characteristics of advanced packaging and SiP, and then we give a summary of the design requirements. Whether a specific design tool meets the design needs, or even exceeds expectations in some ways, requires the reader to read the second part of the book: Design and Simulation, which covers Chaps. 6 Through 21. In addition, the third part of this book: Projects and Cases, through actual cases, describes in detail the design, simulation and verification methods of SiP and advanced packaging products, which have worthy reference values.
References and Notes
References 1. Li S (Li Y) (2017) SiP system-in-package design and simulation. WILEY, New Jersey 2. Li Y, Liu Y (2012) SiP system in package design and simulation. PHE, Beijing 3. Li G, Liu F (2018) Packaging and testing technology of microelectronic devices. Tsinghua University Press, Beijing 4. Wang Y et al (2018) Complete book of integrated circuit industry. PHEI, Beijing 5. Tummala S (2014) Introduction to system-on-package: miniaturization of the entire system. Translated by Liu Sheng. Chemical Industry Press, Beijing 6. Wang Z (2015) Microsystem design and fabrication, 2nd edn. Tsinghua University Press, Beijing 7. Jin Y, Wang Z (2006) Introduction to microsystem packaging technology. Science Press, Beijing 8. Garrou P, Lwona T et al (2006) Multichip module technical manual. PHEI, Beijing 9. Gupta TK (2005) Handbook of thick film hybrid microelectronics. PHEI, Beijing 10. Ulrich R, Brown W (2010) Advanced electronic packaging. Machinery Industry Press, Beijing 11. Xie Y, Cong J, Sapatnekar et al (2016) 3D integrated circuit design, EDA, design and microarchitecture. China Machine Press, Beijing 12. Chuan ST (2016) Wafer level 3D ICs process technology. China Aerospace Publishing House, Beijing 13. Zhang R (2014) Nano integrated circuit manufacturing process. Tsinghua University Press, Beijing 14. Yao Y, Zhou W (2019) Chip advanced packaging manufacturing. Jinan University Press, Guangzhou
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References and Notes
15. Rino M (2020) Three dimensional memory chip technology. Tsinghua University Press, Beijing 16. Li S (Li Y) SiP technology, WeChat public account 17. In addition, some data and information come from the internet and will not be listed one by one
Notes For the length unit of micron, the corresponding symbol is “lm”. In EDA design software, it is usually written in “um”. Therefore, in order to keep the picture and text consistent, the unit corresponding to micron is written in “um” in the main body of this book.
Part II
Design and Simulation
Chapter 6
SiP Design and Simulation Platform Suny Li
From this chapter, we will start to discuss the design, simulation and verification flow of SiP and the implementation of related technologies based on EDA tool. SiP designers come from two aspects: ➀ system users, ➁ IC and package users. System users are used to achieving their design purpose with PCB, so they prefer the design flow similar to PCB design flow in which Schematic is the beginning of design. IC and package users mainly include chip design, chip manufacture, package and test users. They are used to using netlist as the design input. In order to meet the needs of different customers, SiP tool is also divided into two different design flows.
6.1 Development of SiP Design Technology Siemens EDA, former known as Mentor or MentorGraphics, is one of the three largest EDA manufacturers in the world, and also the world’s largest software supplier of PCB and IC package design, simulation and verification. It provides advanced solutions for many electronic enterprises and scientific research institutions in the world, and has occupied a leading position in the market for many years. At present, it belongs to Siemens software division. Referring to Fig. 6.1, we can learn about the development of SiP and HDAP technology of Siemens EDA. In 2009, based on EE2007.5, Mentor introduced Expedition Advanced Packaging bundle (Expedition AdvPkg) to support SiP and Advanced Package design. It absorbed the MCM, thick film, thin film, hybrid circuit design functions of Mentor Board Station, as well as Embedded Passives, IC Package, RF and other design functions of DDE super Max purchased by Mentor, and inherited the excellent layout S. Li (B) Beijing, China e-mail: [email protected] © Publishing House of Electronics Industry 2022 S. Li (ed.), MicroSystem Based on SiP Technology, https://doi.org/10.1007/978-981-19-0083-9_6
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Fig. 6.1 Development and current status of SiP and HDAP platform
and routing functions of Expedition PCB, integrated them all into the new products, make Expedition AdvPkg have powerful functions, fully support SiP and related complex design. In 2015, Mentor launched a brand new Xpedition design platform, and Expedition AdvPkg was upgraded to Xpedition Layout301. While the design function was further enhanced, 3D design function was improved qualitatively. In 3D environment the real state of the product can be simulated to guide the design and production. SiP designers are more convenient to use, and can interact with Mechanic software to realize Digital Prototype design. At the same time, to meet the strong demand of Advanced Package, Siemens EDA developed HDAP design Flow for High Density Advanced Package, including XSI (Xpedition Substrate Integrator) and XPD (Xpedition Package Designer). XSI inherits and develops the excellent functions of IOD ASIC, which is a classic net optimization tool, while XPD originates from the function improvement of Expedition AdvPkg. For SiP and HDAP simulation and verification, Siemens EDA provided HyperLynx Advanced Solver, HyperLynx DRC, HyperLynx SI/PI/Thermal and Calibre 3DSTACK. In the field of professional thermal analysis and testing, Siemens EDA has FloTHERM-thermal analysis tool and T3ster-thermal test system, which can ensure that the designed SiP heat dissipation problems are properly solved. From Fig. 1.6, we can see the development history of SiP and HDAP design platform, as well as the existing various functions of the design, simulation and verification platform.
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6.2 Two Sets of SiP Design Flow According to the description in the previous section, we divide the SiP design flow into two sets: ➀ ➁
General SiP design flow; The SiP design flow based on HDAP – HDAP design flow.
Which design flow is more suitable for yourself? After reading the following design flow introduction, readers should be more clear.
6.3 General SiP Design Flow General SiP design flow refers to the SiP design flow driven by schematic. The main modules include schematic design tools, layout design tools, library creation and management tools, etc.
6.3.1 Schematic Design Input The schematic input tool of SiP design is Xpedition Designer (hereinafter referred to as Designer). In addition to the conventional schematic input, Designer supports RFEngineer, and its RF component library is synchronized with Agilent ADS RF component library. Designer can support the component invoking based on DataBook and material information association, and the simulation of Digital/Analog hybrid circuit with HyperLynx AMS. Designer also supports multi-person concurrent schematic design, that is, multiple designers can design a schematic at the same time. Different designers can operate on different pages without dividing the schematic. At one time, based on the principle of first come first served, the edited page is read-only to other designers, but when the page is released by the current editor, other editors will be able to operate on this pages without conflict. This ability of concurrent schematic edit is particularly important for large and complex SiP projects.
6.3.2 Multi-layout Design Collaboration With the improvement of the complexity of SiP design, One SiP design often includes multiple layout designs. For example, the common 2.5D integration technology needs to include Interposer and Package Substrate. At the same time, SiP also needs to be put on PCB in the form of devices, and the joint design between Interposer-SubstratePCB will become closer and closer.
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Fig. 6.2 Multi-layout design collaboration in one project
As shown in Fig. 6.2, three layout designs are managed in one project, Interposer, Package_Substrate and PCB_Board, which correspond to three schematic respectively. Each design can be designed independently, and they are related to each other because Interposer needs to be installed on the Package_Substrate, and Package_Substrate finally needs to be installed on PCB_Board to work together. In this case, it is more scientific and reasonable to manage multiple layouts and schematics in one project than to adopt three separate projects. Considering the relationship and net connections among the three layouts, including the subsequent PCB system design, the pin allocation of SiP design can be optimized in such case.
6.3.3 Functions of SiP Layout Design In the field of PCB and IC packaging design, Siemens EDA occupies more than 50% of the global market share. All the advantages of PCB design tool can be applied in SiP design as easily as possible. For layout, which is the core function of SiP and IC packaging design, Siemens EDA has developed a number of specific design functions for SiP and HDAP based on XpeditionPCB to support users to complete various requirements of SiP and HDAP design, as shown in Fig. 6.3, which are described in detail below. 1.
3D Integration Design
In Chap. 4 of this book, we defined 3D Integration: the chip is directly connected through TSV. The physical structure of 3D integration is in the form of chip stack, and the electrical connection is directly interconnected through TSV inside the chip. Figure 6.4 shows the Screenshot of Xpedition 3D integration design. Chips are stacked and installed on the substrate. The chips are electrically connected through
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Fig. 6.3 9 functions of SiP layout design
Fig. 6.4 Screenshot of Xpedition 3D integration design
TSV and MicroBump, and the bottom chip is electrically connected with the substrate through MicroBump. 2.
2.5D Integration Design
In Chap. 4 of this book, we defined 2.5D integration: the integration through silicon interposer. The physical structure of 2.5D integration is in the form of chips on silicon interposer and interposer on substrate, and the electrical connection of chips is through RDL and TSV on silicon interposer. Figure 6.5 shows a screenshot of the Xpedition 2.5D integration design.
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Fig. 6.5 Screenshot of Xpedition 2.5D integration design
Chips are mounted on silicon interposer and connected to interposer through MicroBump, the electrical connections of chips are realized through the RDL and TSV on silicon interposer. The silicon interposer is electrically connected to substrate through Bump. 3.
RDL Design
The meaning of RDL (ReDistribution Layer) is to reroute on the chip surface to change the position of IO pin of the chip. RDL can be divided into two types: Fan-In and Fan-Out, which are refer to reroute to inside of the chip or outside of the chip respectively. In addition, the routing on silicon interposer is also known as RDL. Figure 6.6 shows the screenshot of RDL design in Xpedition, which is a Fan-In type RDL. Through RDL, the IO pins used for wire bonding at the edge of the chip are redistributed on the chip surface in plane array, and the chip are installed on the substrate in the form of flip chip through bump.
Fig. 6.6 Screenshot of Xpedition RDL design
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Fig. 6.7 Screenshot of Xpedition 2D+ integration design
4.
2D+ Integration Design
In Chap. 4 of this book, we define 2D+ integration: chips are stacked on substrate and connected to substrate through bond wire. 2D+ integration adopts chip stacking in physical structure, the upper chips are connected to substrate through bond wire, and the lowest chip may be connected to substrate through bond wire or installed on the substrate in the form of flip chip. Figure 6.7 shows the screenshot of Xpedition 2D+ design. Chips are stacked on substrate and connected to substrate through bond wire. Xpedition supports no layer limited IC die stack design, and can cooperate with cavity design, which is conducive to the stability of outside bond wire. From Fig. 6.7, we can see that complex multi-layer bonding requires high precision of bond wire model. The bond wire model of Xpedition supports multiple forms of bending, including corner, round and spline, which is more accurate and close to actual bond wire shape, so as to help designers to improve design accuracy effectively and improve product yield, as shown in Fig. 6.8. 5.
4D Integration Design
In Chap. 4 of this book, we define 4D integration: integration through substrate bending and folding, the physical structure of 4D integration adopts the substrate bending and folding, and the electrical connection is connected through substrate. In addition, in 4D integration, there are also 2D, 2D+, 2.5D and 3D integration modes included probably. Figure 6.9 shows the screenshot of Xpedition 4D integration design. Chips are installed on multiple surfaces inside the package, including 3D integrated chips on the bottom side, 2D integrated chips on the left and back sides and 2D+ integrated chips on the right and top sides.
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Fig. 6.8 Xpedition bond wire model
Fig. 6.9 Screenshot of the Xpedition 4D integration design
6.
Cavity Design
In Chap. 4 of this book, we define cavity integration: it refers to that chips and passive devices are partially or completely embedded in the substrate through cavity, so as to improve the integration density. The cavity can be single-step cavity, multi-step cavity, or embedded cavity. Xpedition supports single-step cavity, complex multi-step cavity and embedded cavity design. Figure 6.10 shows the screenshot of Xpedition cavity design, in which chips are stacked in a multi-step cavity and 3 passive components are placed in a single-step cavity.
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Fig. 6.10 Screenshot of Xpedition cavity design
7.
EP (Embedded Passive) Design
In Chap. 4 of this book, we define plane integration: plane integration technology is also called plane embedded technology. It is to make planar passive devices such as resistance, capacitance, inductance and so on through special materials and print them on the surface of the substrate or embed inside the substrate. Figure 6.11 shows the comparison between surface mount resistor/capacitor and planar resistor/capacitor in Xpedition. Xpedition EP (Embedded Passive) function supports embedded passive components. According to selected resistance or capacitance material, it can synthesize required planar resistance or capacitance automatically, and support laser precise adjustment. Designers can place planar resistors and capacitors on any layer of
Fig. 6.11 Screenshot of surface mount R/C and planar R/C
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Fig. 6.12 Screenshot of Xpedition RF circuit design
substrate. Through EP design, the surface mounting space can be saved and the solder joints can be reduced, thus increasing the reliability. 8.
RF (Radio Frequency) Design
Xpedition RF (Radio Frequency) design function can realize RF circuit design, including the same RF component library as ADS/AWR, supporting the mutual transfer of RF parameters between schematic and layout, and can transfer RF circuit to ADS/AWR for simulation. RF design function can also meet the special design requirements of layout, such as gradual line width change, stitching vias, loop inductor and etc. Figure 6.12 shows a screenshot of RF circuit design in Xpedition. 9.
Team Concurrent Design
Real-time team concurrent design function-team layout can carry out multi-person concurrent design for complex SiP layout, without any design segmentation, design data can be updated to each designer in real time, which greatly reduces the design difficulty and designer’s pressure. According to the statistics of actual projects, with team layout the design efficiency can be improved by more than 50%. This is especially important for SiP project users who have complex design and tight schedule. Figure 6.13 shows the sketch map of real-time team layout design.
6.4 SiP Design Flow Based on HDAP Advanced package, also known as HDAP (High Density Advanced Package) in this book, has become a very hot topic currently. In Chap. 5 of this book, we give the definition of advanced package: the package which adopts advanced design ideas and advanced integrated technology to reconstruct chips at package level, and can effectively improve the Function Density of the package. We can call it Advanced Package.
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Fig. 6.13 Sketch map of real-time team layout design
At present, Advanced Packages usually include WLP, PLP, 2.5D integrated package and 3D integrated package. WLP includes FIWLP and FOWLP. 2.5D and 3D integrated packages are also called 2.5D IC and 3D IC. Figure 6.14 shows the classification of common HDAP at present. WLCSP belongs to Fan-In WLP (FIWLP), FOWLP refers to single chip Fan-Out WLP, INFO refers to multi-chip Fan-Out WLP, PLP usually only has Fan-Out type; Intel’s EMIB is a little special, it is a kind of local silicon interconnect bridge embedded in substrate. According to the definition in Chap. 4 of this book, it should be classified as 2D integration. The industry also usually defines EMIB in 2D. However, the function of EMIB is similar to 2.5D integration, and its design idea is also similar to 2.5D. Therefore, it is classified as 2.5D based on functions and design ideas here.
Fig. 6.14 HDAP classification currently
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Cowos is the standard 2.5D integration, while HBM and Co-EMIB contain 2.5D and 3D technologies, Other integrations such as HMC, wide IO, Foveros, SoIC and X-Cube are all 3D integration technologies. For detailed introduction of the above Advanced Packaging technologies, please refer to the relevant contents of Chap. 5: SiP and advanced packaging technology. In addition, with the development of technology, the definition of Advanced Package will also change. New Advanced packaging technologies will continue to emerge, and the original advanced package may gradually become traditional package.
6.4.1 XSI-Design Integration and Net Optimization Tool As a design input tool for HDAP, it mainly includes the following functions: ➀ component library creation, ➁ definition and optimization of net connection; ➂ layout initial creation. The following Fig. 6.15 shows XSI design interface. 1.
Component Library Creation
Each kind of project is composed of different components, so the component library is the first problem to be solved at the beginning of the project. There are three ways to create component library in XSI. (1) (2) (3)
Component can be generated by importing AIF, CSV and DEF\LEF files. Bare die, Flip Chip, BGA, etc. can be created by importing files. Call component data from Central Library, setup the corresponding central library first, and select the required part number and cell name in the library. Custom definition. XSI has JEDEC standard database template, which can easily and accurately create component library. Just set the corresponding parameters, XSI will automatically create cell and part. Figure 6.16 shows the Custom definition template and pin position in XSI.
Fig. 6.15 XSI design interface
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Fig. 6.16 Custom definition template and pin position definition
2.
Definition and Optimization of Net Connection
First of all, net definition is to assign the corresponding net name to component pins when building the component library. Usually, net definition is carried out by file import. The supported files include VDHL/Verilog and CSV files. In addition, when design SiP and HDAP, the best choice is to share the information of die, interposer and substrate in the whole design process and optimize the whole signal path from die to interposer to substrate. XSI provides an integrated design environment, which can be associated with IC design and PCB design when design chip package. XSI design environment provides the possibility of die, interposer, substrate and PCB overall optimization. Figure 6.17 shows the overall net connection optimization of die, interposer and substrate in XSI. 3.
Layout Initial Creation
Layout Initial creation includes: (1) (2) (3)
chip stack creation, layout initialization, layout template selection.
After chip stack is created and set up in XSI, it can be directly transferred to the layout design tool XPD. Figure 6.18 shows how to create and set up chip stack in XSI.
Fig. 6.17 Overall net connection optimization of die, interposer and substrate in XSI
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Fig. 6.18 Create and setup chip stack in XSI
6.4.2 XPD-HDAP Layout Design Tool In the design process of HDAP, in addition to the design integration and net optimization tool such as XSI, we also need a design tool with powerful layout and routing functions, and also a good 3D design environment, which enables designers to understand the whole packaging structure and details accurately, so as to improve the efficiency and accuracy of the design. XPD (Xpedition Package Designer) is exactly such a tool. In the previous section, we learned about the nine functions of SiP layout design. XPD has seven of them. Among them, 4D integration cannot be realized in XPD, because XPD does not support Rigid-flexible design. XPD does not have RF design function also. But in addition, XDP has some specific features. 1.
3D + 2.5D Design
Aim at current development trend of HDAP, 2.5D integration and 3D integration design have become very common. In addition, some Advanced Packages include both 2.5D and 3D, which we can call 3D + 2.5D. XSI + XPD can be said to be the golden combination for this kind of design. Figure 6.19 is a screenshot of HBM-HDAP design created in XSI and completed in XPD. 2.
Specific Features of XPD
XPD is derived from Xpedition Layout, and its functions are similar to Xpedition Layout 301, but there are some differences. XPD is specially created for Advanced Packaging design, so it has certain optimization and enhancement in packaging design function. For example, XPD can import AIF, CSV netlist and ODB++, and export AIF, Color map and PCB library data. Layout 301 has no corresponding function, and External Component Wizard of XPD is also not provided by layout 301. In addition to cooperating with XSI, XPD can also design from nothing by itself. In this way, for simple SiP or package design, XPD can handle independently.
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Fig. 6.19 Screenshot of 2.5D + 3D HBM-HDAP design in XPD
6.5 Which Design Flow is Suitable for Designers? For general SiP and HDAP design, in many places they are the same, but they also have their own characteristics. Siemens EDA provides two sets of design flow, which are also the same. How can designers determine which design flow is more suitable for them? First, determine what kind of users you belong to, ➀ system users, ➁ IC and Package users. In addition, think about your previous design habits to determine which one is better for you. Functionally, refer to Table 6.1. From Table 6.1, we can see that Designer + Layout 301 and XSI + XPD have their own advantages and specific features, and are basically the same in many aspects. For XPD and Layout 301, they are like twin brothers, have similar basic functions, but also have their own characteristics. XPD is designed specifically for Packages, while Layout 301 supports Package, PCB, and Rigid-Flex designs. How do designers choose the right tools? XSI + XPD is recommended for package design only, especially for HDAP design; Designer + Layout 301 is recommended for schematic input, RF, Rigid-Flex design and also package design.
6.6 SiP Simulation and Verification Flow In Chap. 2 of this book, we propose the concept of Si3 P and point out that the second “i” in Si3 P represents the concept of interconnection. The purpose of interconnection is to transfer information or energy.
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Table 6.1 Function comparisons of two design flows Items
General SiP design HDAP design flow Comments flow
Design tools configuration
Designer + layout 301
XSI + XPD
XSI + layout 301 can cooperate also
1. Schematic input
✓
–
Include schematic concurrent design
2. RF circuit design
✓
–
Functions of designer + layout 301
3. Rigid Flex design
✓
–
Function of layout 301
4. Layout variant management
✓
–
Function of layout 301
5. Multi-layout net optimization
–
✓
Specific function of XSI
6. LEF/DEF support
–
✓
Specific function of XSI
7. AIF\CSV\ODB++ import
–
✓
User library and design data
8. JEDEC standard Cell template
–
✓
Specific function of XSI
9. 3D IC integration design
✓
✓
Die to die connected by TSV
10. 2.5D IC integration design
✓
✓
RDL/TSV in silicon interposer
11. EP design
✓
✓
Automatic synthesis of planar resistor and capacitor
12. Cavity design
✓
✓
Open cavity, embedded cavity
13. Die Stack design
✓
✓
Pyramid, cantilever, side by side stacking
14. Bond Wire design
✓
✓
Multi-type bond wire bending
15. 3D model input and output
✓
✓
3D layout design environment
16. ECAD-MCAD collaboration
✓
✓
3D layout design environment
17. Layout multi-person concurrent design
✓
✓
Multi person participate in one layout design real timely
18. No limited design scale
✓
✓
Layers\Pins\Connections no limit
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For SiP, interconnection can be divided into three main areas: interconnection of EM, interconnection of Thermo, and interconnection of Force. Simulations in SiP mainly focus on these three aspects, which are described one by one below.
6.6.1 Electromagnetic Simulation In Chap. 4 of this book, we divide the integration of SiP into 7 modes: 2D, 2D+, 2.5D, 3D, 4D, cavity integration and planar integration. As we know from the previous content of this chapter, these integration modes can be perfectly implemented in design tools Layout301 and XPD. An important function of simulation tool is to identify and import the physical interconnection model built in design tool into simulation tool correctly, which is usually needed at the beginning of the simulation, as described below. 1.
For Planar Design
Here, we do not use 2D design but planar design because they have different categories in definition. 2D integrated design includes two types: 2D Bond Wire and 2D FlipChip. 2D Bond Wire is 2D integration, but it is not 2D for simulation tool because Bond Wire in electrical interconnection is non-2D. FlipChip and Embedded Passive are both located on or inside substrate, so 2D simulation tools can handle them well. Please see the distinction between 2D integration design and planar design shown in Fig. 6.20. For planar design, we can use HyperLynx SI/PI/Thermal tool for simulation. This tool consists of three modules: ➀ signal integrity analysis tool HyperLynx Si, ➁ power integrity analysis tool HyperLynx PI, and ➂ thermal analysis tool HyperLynx thermal. The three modules are located in the same software environment and can be used for collaborative simulation, such as SI-PI co-simulation and electrothermal co-simulation.
Fig. 6.20 The distinction between 2D integration design and planar design
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Fig. 6.21 Simulation flow for planar design
HyperLynx SI supports signal integrity, crosstalk and EMC Simulation, supports oscilloscope display (conventional, eye diagram), spectrum analyzer display mode. In addition, HyperLynx SI has embedded the analysis Wizard of DDRx and SerDes, which is specially designed for the analysis of DDRx and SerDes. HyperLynx PI supports DC drop, AC decoupling and plane noise analysis, and supports 2D and 3D waveform display. HyperLynx Thermal supports thermal analysis and electrothermal co-simulation with HyperLynx PI. Figure 6.21 shows the simulation fow for planar design. The design data can be directly transferred to HyperLynx for SI/PI/Therma analysis. 2.
For Non-Planar Design
Most SiP and HDAP designs are non-lanar designs, including 2D bond wire, 2D+, 2.5D, 3D, 4D and cavity integration designs. These designs require the use of 3D electromagnetic simulation tool HyperLynx Advanced Solver. HyperLynx Advanced Solver includes 3 Solvers: Fast 3D Solver, Full Wave Solver and Hybrid Solver. Full Wave Solver HPC can be regarded as a high-performance version of Full Wave Solver. The functions of each solver are different. Design data is imported into HyperLynx Advanced Solver, and then different solvers are used to obtain RLGC, S-Parameter, Z-Parameter, Current Density, IR drop, EMI/EMC, etc. refer to Fig. 6.22, simulation flow for non-planar design➀.
Fig. 6.22 Simulation flow for non-planar design➀
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Fig. 6.23 Simulation flow for non-planar design➁
If we need to view the time domain waveform or eye diagram of the signal, we can put the S-Parameter model of the nets obtained through Full Wave Solver and the IBIS model of the chip together into HyperLynx SI for SI simulation, and then time-domain simulation waveform or eye diagram can be obtained, as shown in Fig. 6.23.
6.6.2 Thermal Simulation As we have learned above, HyperLynx thermal can do thermal analysis for planar design to diagnose thermal problems at early stage, so as to avoid overheating or thermal failure in SiP products. For non-planar design or complex design, we need a professional thermal analysis tool FloTHERM, which can support various complex designs from planar to nonplanar. The simulation flow of is FloTHERM shown in Fig. 6.24.
Fig. 6.24 FloTHERM simulation flow
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FloTHERM focuses on heat dissipation analysis of electronic devices and equipment. It is the first software for thermal analysis and optimization in the industry. It can solve the three heat transfer modes of heat conduction, convection and radiation. It has rich and powerful experience data accumulation, and can predict the internal air flow, temperature distribution and heat transfer process. FloTHERM covers multi-scale heat analysis in an all-round way, and supports thermal analysis of ➀ package level: IC devices and LEDs; ➁ board and module level: PCB and power module; ➂ system level: crate and cabinet; ➃ environmental level: Machine room and outer space.
6.6.3 Mechanical Simulation In Chap. 2 of this book, we propose the interconnection of Force, which needs to consider the forces from outside and from inside of SiP package. For SiP design, the main concern of interconnection of Force is the contact surface between different devices or different materials. External forces mainly come from impact, vibration, acceleration, etc. Internal forces mainly come from relative distortion, which is mainly caused by the change of temperature. Siemens EDA provides a mechanical simulation tool Xpedition DfR, which provides two types of simulation: vibration simulation and acceleration simulation, mainly focuses on the impact of external forces. Vibration simulation gives reliability and failure prediction caused by vibration, failure frequency, device-level stress, and 6-degree-of-freedom vibration simulation. Acceleration simulation gives safety factor under certain acceleration, Von-Mises stress at pin-level, detailed stress–strain diagram, and 3-degree-of-freedom force vector. However, at present, this tool has some limitations. It can only support planar SiP design and PCB design. Figure 6.25 shows Xpedition DFR mechanical simulation
Fig. 6.25 Xpedition DfR mechanical simulation flow
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Fig. 6.26 HyperLynx DRC electrical verification flow
flow of planar design. If designers have more requirements for mechanical simulation, they need to seek third-party mechanical simulation tools, such as SIEMENS Simcenter or ANSYS corresponding mechanical simulation tools.
6.6.4 Design Verification 1.
Electrical Verification
Electrical verification is different from simulation tools, which checks the design by electrical rules. HyperLynx DRC embeds a total of 82 kinds of electrical rules in 5 categories: Analog (3), EMI (18), PI (10), SI (43), and Safety (8). Figure 6.26 shows the electrical verification flow of HyperLynx DRC. The core of HyperLynx DRC is the advanced electrical rule checker. It is based on the physical and electrical parameters to validate the design and determine the problem. It conduct a comprehensive Analog, EMI, PI, SI, Safety analysis. Powerful APIs can create complex rule checks, including physical and electrical parameter rules that can be changed based on frequency. Validation results can be used to detect problems with SiP layout design tools interactively, locate problems quickly, and quickly modify errors in design data. 2.
Physical Verification
SiP layout design tools Layout301 and XPD have embedded DRC checking model which can help designers check and validate traditional package and SiP design. For 3D and 2.5D integration designs of HDAP, specific verification tools are required. Calibre is the most influential IC layout verification tool in the industry. Due to the integration of IC design and HDAP design, both 3D and 2.5D integration require RDL and TSV on silicon materials. Therefore, Siemens EDA has developed
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Fig. 6.27 Calibre 3DSTACK physical verification flow
Calibre 3DSTACK specifically for 3D and 2.5D integrated design, which contains 6 functional modules, as shown in Fig. 6.27. Calibre 3DSTACK RVE, a powerful graphical debugging and result observation tool, enables interactive detection between schematic and layouts as well as net browsing. In order to ensure the successful flow of circuit design and higher product yield, foundry will set a number of design rules to restrict the layout graphics according to the process level. These design rules must be followed in layout design. Due to human or tool factors, design rules will be violated inevitably. To ensure the quality of design, DRC verification must be carried out in design stage to ensure that the entire design data meets the foundry process level design rules. Calibre 3DSTACK uses a hierarchical optimization algorithm, which not only improves efficiency, but also avoids erroneous duplicate output, ensures that the layout design and the verified circuit diagram connection are consistent, and ensures that the final product meets the expected design parameters.
6.7 Advanced Natures of SiP/HDAP Platform From previous descriptions in this chapter, we have a basic understanding of SiP and advanced packaging design, simulation and verification platform. From the two design flow of SiP and HDAP for different customer needs, to the comprehensive solutions of electromagnetic simulation, thermal simulation, mechanical simulation, and design verification, all reflect the advantages of SiP and HDAP platform. Next, we summarize the advanced natures of SiP/HDAP platform from five aspects.
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Overall Support for Advanced Packaging Technology
High Density Advanced packaging technology can improve system Function Density to the greatest extent, so it has attracted unprecedented attention in the industry. SiP and HDAP design platform provide overall support for advanced packaging technology. From 3D Integration to 2.5D integration to FOWLP, all can be easily realized in design tools. Designers can easily deal with complex SiP and HDAP design in the platform. For details, please refer to the description in Chaps. 12, 13 and 19. 2.
Optimization for Traditional Packaging Technology
Here, traditional package refer to the package implemented by traditional technology, such as Wire Bonding, Chip stacking, Cavity and other processes. SiP and HDAP design platform have comprehensively optimized and improved these technologies, such as the definition of Bond Wire model, Bond Finger sharing, the setting of Wirebond guide line, the setting of complex chip stacks, the support of complex cavity structure and so on, as well as the layout and routing method, all of which have been greatly improved and optimized from the previous version. For details, please refer to the description in Chaps. 11, 12 and 14. 3.
Multiple Technologies Increase the Flexibility of Integration
SiP and HDAP design platform can not only support advanced packaging and traditional packaging technology, but also support embedded passive design, RF design, Rigid-flex circuit design, multi person real-time Concurrent design and other technologies. The addition of these technologies greatly improves the flexibility of SiP integration. For example, embedded passive devices can save surface mounting space, reduce solder joints and improve reliability; RF design can integrate RF circuit into SiP to realize RF SiP design, which is very common in the field of wireless communication; Rigid-flex circuit design improves the flexibility of MicroSystem integration and realizes 4D integrated design; multi person real-time Concurrent design can improve the design efficiency by more than 50%, which has unique advantages for complex design and urgent projects. For details, please refer to the description in Chaps. 15, 16, 17 and 18. 4.
3D Design Environment to Realize Digital Prototype
Due to the powerful 3D design environment, SiP and HDAP design platform are in the leading position of the industry. The advantage of 3D design is not only the visual impression of the designer, but also the accurate description of the objective things. From every bend in each bond wire, the shape and process selection of the start and end points, the value of the height of the bond pad relative to the chip, to every chip stack, every cavity, every resistor and capacitor, every routing, via, bump and ball, all can be accurately generated through 3D models. Through this precise description, our design can completely have a one-to-one comparison with the actual product, and even replace the physical prototype to a great extent, which is what we call the “digital prototype” concept.
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Fig. 6.28 Digital prototype realized through 3D design environment
Today, in the powerful 3D design environment, we can completely realize the digital prototype design. Since SiP tool has no restriction on the design scale, we can show the digital prototype design through 3D environment for simple or extremely complex design. Figure 6.28 shows the realization of digital prototype of a power module through 3D design environment. From the figure we can see the exact model of each component, including bare chips, resistors, capacitors, inductances, as well as bonding wires, routing, via holes and BGA Ball, etc. In addition, substrate and molding can also be displayed accurately. The 3D environment also includes 3D DRC and 3D measurement functions, basically realizing the function of the physical prototype. In addition to accurately simulating all design elements, 3D design environment supports planar cutting, it can cut 3D model from three planes: X, Y and Z, and the cutting plane can move and rotate to display the fine structure of its internal elements, which goes beyond the physical prototype. For physical prototype, even if it can be cut, it will damage the prototype and cannot be cut at any angle on any plane, at this point, the digital prototype is much more flexible than physical one. At the same time, 3D design environment support the collaborative design function with mechanical software, ECAD-MCAD collaboration enables real-time electronic and mechanical concurrent design of one product. In almost every chapter of this book, there are 3D displays, which show the powerful 3D design capabilities of the tool. 3D design environment give the reader an intuitive impression, whether from product details or the overall display. At the same time, it is also specific feature of this book which simulates the original form of the real product through 3D design environment as much as possible. 5.
Simulation and Verification Ensure the Success of Products
If the digital prototype mentioned above only shows the form of the physical product from static state, simulation tool can simulate the product through actual working state.
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Currently, the SiP simulation and validation platform can support comprehensive simulation from the three fields of electromagnetism, heat and force. It can simulate the working state of actual products. Besides the function of mechanical simulation is not perfect at present, and need the help of third-party tools, in electromagnetic and thermal analysis area, SiP design and simulation platform can solve almost all kinds of practical problems. In addition, the unique electrical verification tool HyperLynx DRC and physical verification tool Calibre 3DSTACK guarantee the consistency of design data to physical products from both electrical and physical aspects, thus ensuring the maximum success of product development. Please refer to the description in Chap. 21 of this book for details.
Chapter 7
Central Library Creation and Management Suny Li
7.1 Structure of Central Library In SiP design process, the first problem designers need to solve is to build and manage library data. Because with the library elements, projects can really start to design. First, let’s look at the structure of Central Library. In Xpedition, the design unit corresponding to schematic is called symbol, the design unit corresponding to layout is called cell. Depending on the type of component, cell will refer to different types of padstacks. For surface mounted devices or bare chips, padstack is usually composed of different layers of pad, such as pad layer, solder mask layer, solder paste layer, gold plating layer, etc. For through-hole devices, padstack is usually composed of pad and hole of different layers. Symbol and cell are mapped together with pins to form part. Figure 7.1 shows the structure of Xpedition central library. Central library is independent of any project and can be referenced by multiple projects at the same time. Central library contains associated symbol, cell, part and padstack, simulation model, layout template, etc. There can be multiple Central libraries, but each design can only be associated with one central library. The parts used in a SiP design, as well as their corresponding symbols, cells and padstacks, are extracted from the central library. Firstly, the symbol is placed in the schematic for interconnection, and then package CDB is carried out. Then, the corresponding cells and padstacks are automatically extracted by forward annotation and passed to layout design. Figure 7.2 shows the relationship between schematic, Layout and Central Library. In addition to the central library, there is a local library in each project, which only contains the data such as part, symbol, cell and padstacks used in this project. S. Li (B) Beijing, China e-mail: [email protected] © Publishing House of Electronics Industry 2022 S. Li (ed.), MicroSystem Based on SiP Technology, https://doi.org/10.1007/978-981-19-0083-9_7
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Fig. 7.1 Structure of Xpedition central library
Fig. 7.2 Relationship between schematic, Layout and Central Library
Modify the data of local library will update the schematic or layout of the project automatically, but does not change the central library data. Local library data can be updated by the central library data associated with the project.
7.2 Dashboard Introduction From now on, we start to use Xpedition tool. First, we learn Dashboard. After the under Xpedition, software installation is completed, we can find Dashboard icon click to start Dashboard. The interface window is shown in Fig. 7.3. For the convenience of use, it is recommended to put Dashboard on the desktop so that it can be enabled at any time. Dashboard is an interface of integrated design environment, which contains the launch links of various tools used in SiP design and simulation. All these tools can be launched directly from the Dashboard. On the left side of Dashboard is Shortcuts column. Designers can select and drag common tools to the Shortcuts, such as Designer , Xpedition , Library Manager and etc. displayed in Fig. 7.3. We can start the corresponding tools by clicking the tool icon with one click mouse button in shortcuts. For the tools that have been placed in Shortcuts, we can also remove them from the right-click menu.
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Fig. 7.3 Dashboard interface window
In the Folders column, there are subdirectories such as projects, toolboxes, WDIR, etc. The projects subdirectory contains the projects currently managed under Dashboard. You can add project through the menu command File → Add project. Among them, the bold type indicates the active project. You can activate a project by clicking its name. Only one project can be activated. When schematic tool designer is opened, the active project will be opened automatically, as shown in Fig. 7.4 FLIPCHIP_DESIGN is the active project. Toolboxes contain 8 subdirectories, which contain various types of tools in Xpedition. Toolboxes are distinguished according to the functions of tools and are placed in different subdirectories. You can click on each subdirectory to view the design tools in it, and by selecting a tool icon, drag it to Shortcuts. Figure 7.5 shows some tool icons contained in Toolboxes. Fig. 7.4 Active project is shown in bold type
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Fig. 7.5 Toolboxes and tools
7.3 Schematic Symbol Creation Click the icon in Shortcuts to start Library Manager, you can open the existing Central Library, from which you can view design elements such as symbol, cell, part and padstacks. You can also create a new Central Library. Select File → New, system will pop out Select a New Central Library directory window to set the path of the new central library. Here we create a new folder and name it SiP_lib2020, and then double-click to enter this folder. After entering the folder, Xpedition Designer/Xpedition Layout is selected by default in flow type, as shown in Fig. 7.6. Then, click the OK button, system will automatically copy some basic library elements to the new Central Library folder. After Central Library is created, under symbol, we can see that there are already three partitions, which are automatically generated by system, namely Boards, Fig. 7.6 Create a new Central Library (click to enter the folder)
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builtin, and Globals, which contain elements such as Schematic frame, connector, power and ground symbol, as shown in Fig. 7.7. Next, create a new symbol in Central Library. In order to distinguish symbols easily, we need to create a new partition first. Right click on symbols, select new partition, and enter SiP_SYM in the pop-up window, click the OK button to see SiP_SYM folder appears in the list, Right click on the folder, select Symbol Wizard, enter Sym1 in the pop-up window, as shown in Fig. 7.8. After click OK, Symbol Wizard step 1 shows up. By default, select block type as module, and select Do not fracture symbol in Will you Fracture the symbol into smaller, that is, do not split the symbol; click the next button, Step 2 symbol name and
Fig. 7.7 The new created Central Library
Fig. 7.8 Create new symbol with Symbol Wizard
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library path, remain default; click the next button, Step 3 symbol parameters, such as pin length, spacing, pin number visibility and location, and Text size in symbol, remain default also. Click next button, to set 5 basic properties of symbol in Step 4. ➀ ➁ ➁ ➃ ➄
Part Number, it is unique in Central Library. Ref Designator, for example U? It indicates that the symbol is sorted with U as prefix in Schematic, and you can modify it, such as N? or R? etc. PARTS, indicates how many identical symbols are included in a part. Level, symbol level, usually keep STD. PKG_TYPE, the Cell name in layout corresponding to the symbol.
Here, we change the Property Value of Part Number to Part001, PKG_TYPE Value to Die_ Cell1, others remain unchanged, as shown in Fig. 7.9. Click next button, Step 5 of Symbol Wizard, which is mainly used to set the information of symbol pin. There are 11 items in total. The first four items, Pin Name, Pin Number, Type and Symbol Side are more important. As shown in Fig. 7.10, they need to be filled in according to the relevant information of symbol pin.
Fig. 7.9 5 basic properties of a symbol
Fig. 7.10 Set the information of symbol pin
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Fig. 7.11 Manage component information in Excel
Here, we use a relatively quick and simple method, namely copy and paste method. Before introducing the method, we first introduce how to manage symbol and cell data in Excel. The information of all components in SiP design can be managed by Excel. The component information used in a project is managed in accordance with Fig. 7.11. The cell information area is on the left side and the symbol information area is on the right side. Different components are divided into different sheet, such as Die1, Die2, Die3, Package, etc. In actual design, it is better to name the sheet with component name, which is easier to distinguish. The information of Symbol and Cell comes from IC chip supplier and may be in Excel format or other formats such as PDF. Regardless of the format, we first copy the useful information into Excel and arrange it in Fig. 7.11. It is important to note that the pin name in the symbol cannot be duplicated, so rename is required. To preserve the original pin name, we created two columns, pin name (original) and pin name (de-duplicate), followed by pin number, input/output, and pin position properties. Rename the duplicate pin names. If the chip has many pins named VSS, rename them to VSS1, VSS2, VSS3… And so on. The cell information area on the left side of the excel table contains important information need to create a cell. We can import this information through die wizard to create a cell automatically. See the cell creation later in this chapter for details. When creating a symbol, refer to Fig. 7.11, select the area surrounded by the dotted line in the symbol area, press to copy, then place the mouse to the first row of pin name in symbol wizard window, and press to paste the data into symbol Wizard. At this time, you can also see the preview of symbols in the window on the right of the wizard, as shown in Fig. 7.12. It can be seen that although the other seven columns do not paste data, the system also gives them according to the default value.
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Fig. 7.12 Paste symbol information into symbol wizard
Finally, click the Finish button, the schematic symbols are created successfully, and the software opens Symbol Editor automatically, as shown in Fig. 7.13, where symbols can be adjusted, such as modifying the shape of the frame, adjusting the position of pins, font size, and so on, to make the symbols as concise and beautiful as possible, so as to improve the quality and readability of the schematic design. At this time, in the main window of library manager, we can see that Sym1 has appeared in SiP_SYM partition, the preview of the symbol is also displayed on the right view window, as shown in Fig. 7.14.
Fig. 7.13 Adjust the symbol in Symbol Editor
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Fig. 7.14 The completion of Symbol SYM1 creation
Using the same method, the symbols of other IC chips and SiP packages (BGA, QFP, etc.) can be created. You can also edit the symbol information in Excel and then create it by copying and pasting it into the symbol wizard. Symbols of passive devices such as R, L and C belong to standard devices and can be imported from other libraries or created manually.
7.4 Layout Cell Creation Layout cells are generally divided into bare chip cell, passive device cell, SiP package cell, etc. this section mainly describes the creation of bare chip cell and SiP cell. As for cells of R, L, C and other passive devices, they are mostly standard devices. Like symbol library, they can be imported from other libraries or created manually.
7.4.1 Bare Chip Cell Creation 7.5 Create Bare Chip Padstack Before creating any cell, we must create the cell padstack first. in library manager toolbar to start padstack editor, first switch to pads Click TAB, click to create a new pad and set its size. In the units column, select the unit as um, select the shape as square in the list on the right, and set the size as 62. The software will automatically name it square 62. If manual naming is required, such
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Fig. 7.15 Create a new Pad
as changing the name to square 62um, we need to remove the previous check box and name it manually. If the designer changes its name directly, the check box will be automatically removed. As shown in Fig. 7.15. In pad TAB, we can create various shapes of pads and thermal pads. If we need to create a special shaped pad in the design, we need to switch to the custom Pad & drill symbol TAB, where we can draw a pad of any shape, as shown in Fig. 7.16. to create a new After the creation of pad, switch to Padstacks TAB and click padstack, named Die_Pad1, as shown in Fig. 7.17. Select Pin-Die as the type. First click the position after Pad, then select square 62um in Available pads column and to assign square 62um to the pad, then save and exit padstacks click the left arrow editor.
7.6 Create Bare Chip Cell Return to the main interface of library manager, right-click on the cell, select new partition, and enter the partition name SiP_CELL in the pop-up window, click the OK button to see the SiP_CELL folder appears in the cell list, Right click on SiP_CELL
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Fig. 7.16 Create a special shaped Pad
folder, select new cell, and enter Die_Cell1 in pop-up window, and then click OK to open the Create Package Cell window, as shown in Fig. 7.18, and enter as described below. • Total number of pins, Enter the number of pins of the chip, in this example, enter 62. The number entered here is usually consistent with the number of pins defined in the corresponding symbol, otherwise an error will be reported when mapping part. • Layers while editing cell, usually enter 2. • Package group, select IC-Bare Die from the drop-down list. • Mount type, select Surface from the drop-down list. • Cell Properties, Click the cell properties button and enter the unit and height of the chip in the new pop-up window. First, select um in units, that is, set the unit to micron, and then input the chip height to 200. Note that the chip height should be input according to the actual chip thickness, usually the thickness of the wafer after thinning. This has a certain impact on the height of the starting point and the shape of the bond wire, thus affecting the consistency of design and production, that is, considering the factors of DFM (Design for manufacturing). After setting, return to Create Package Cell window and click next to enter Cell Editor. The system will automatically pop up place pins window, select all pins and delete them (note that all pins should be deleted first, otherwise they will conflict
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Fig. 7.17 Assign Pad to Die_Pad1 Padstack
with the Pins imported through Die Wizard later), as shown in Fig. 7.19, and then click Close. and select the pin definition In the Cell Editor interface, click Die Wizard icon file to import. The file content usually includes information such as X coordinate, Y coordinate and pin number of IC bare chip Cell, which has been edited in Excel (see Fig. 7.11 for details). In Excel, select the content in the dashed box of the Cell information area (left side of Fig. 7.11), first copy the content to a text file and save it as Die_Cell1.txt (easier to import with Die Wizard). Then select this file in Die Wizard, such as E:\Projects\SiP\Die_Cell1.txt in this example. Note that in Die Wizard window, Unit should be consistent with the unit in imported file, such as um; Format should also be consistent with the contents of imported file, such as X, Y, Pin Name in Fig. 7.20. Select the Separator based on the format of the file, such as Tab in this example. Pad Stacks selects User defined and selects the Die_ Pad1created above in the drop-down list. Then click the New button and the Import button to finish Die_ Cell1 data import, see Fig. 7.20. After importing, click OK to see that the pins of the IC bare chip have been placed in Cell Editor workspace and arranged according to the coordinates in the file. Designers can manually add placement outline, assembly outline, etc. as shown in Fig. 7.21.
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Fig. 7.18 Create bare chip cell and its properties window
If no outer frame is added, the Placement Outline will be automatically added when saving the cell. The principle of placement outline adding is to surround all pins with the smallest rectangle. Select File → Save, and then exit Cell Editor. Under SiP_CELL partition of Library Manager, Die_Cell1 already exists with associated padstacks Die_Pad1, there is no part associated at present, and subsequent Part mapping is required. Die_Cell1 is on the right preview window, the Placement Outline has been added automatically, as shown in Fig. 7.22.
7.6.1 SiP Package Cell Creation 1.
Create BGA Padstack
Below, we takes BGA as SiP package in this example. Before Create SiP package cell library, similarly, we need to create BGA padstack first. Start Padstack Editor in library manager. First, set the size of the Pad. In Pad TAB, select the unit as um, select the Round shape on the right, and set the size as 500. The software will automatically name it
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Fig. 7.19 First delete all pins in Place Pins window
as round 500, and then create a Round Pad 450 with diameter of 450um in the same way. Switch to Padstacks TAB and create a new Padstack named BGA_pad_500um, the type set to pin SMD. It requires multiple layer definitions. ➀ ➁
First, press and hold the key to select Top mount, Bottom mount, and then select Round 500 in the right bar. Then click the arrow to the left to assign Round 500 to the pad layers. Then press and hold the key to select Top mount soldermask, Bottom mount soldermask, Top mount solderpaste, Bottom mount solderpaste, and click the arrow to the left to assign Round 450 to the appropriate Pad layers, and exit Padstack Editor after saving. See Fig. 7.23.
In practical design, Padstacks do not always have the same dimensions defined for each layer, depending on the process. Soldermask is usually smaller than Pad in
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Fig. 7.20 Import Die_Cell1 file via Die Wizard
Fig. 7.21 Pin position imported through Die Wizard
BGA Padstacks of package or SiP substrates, whereas in PCB designs, Soldermask is usually larger than Pad in BGA Padstacks, and the ratio of enlargement or reduction is generally controlled at about 10%. For Solderpaste layer, its size and the thickness of the SMT stencil control the actual amount of solder paste. It needs to be set according to the actual process to achieve strong soldering but avoid short circuit due to too much solder paste.
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Fig. 7.22 Die_Cell1 creation complete
Fig. 7.23 Assign Pads for BGA Padstack
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For Plane clearance layer, if it is not defined, it will be set according to the design constraint rules during layout. If its size is defined, when generating negative plane, plane data are avoided according to its size, which has no impact on positive plane. For Plane thermal layer, if it is not defined, it will be set according to the rules defined in Plane Classes and Parameters during layout. If its size is defined and the use thermal definition from padstack option is checked in Plane Classes and Parameters, the Plane thermal defined in padstacks will be preferred, which is very useful for some special padstacks to define different Plane thermal from other padstacks. 2.
Create BGA Cell Manually
to enter Cell Editor window. We can see In Library Manager main window, click to Die_Cell1 created above already exists in the cell list, select the new button create a new cell. Enter BGA_cell in the cell name column of the Create Package Cell window, enter the number of BGA pins (total rows × total columns) in Total number of pins column. In Layer while editing cell column, enter 2, that is, two layers are required for editing this cell. In the package group column, select IC-BGA in the drop-down list, select surface in Mount type column. Click the Cell Property button and enter the unit and height of the chip in Package cell properties window. First, select mm in units, and then input the chip height to 0. Because this BGA cell is a unit for SiP package pin function, it is located at the bottom of the substrate and has no thickness, so its height is set to 0. As shown in Fig. 7.24. After all items setting, click the next button to enter Cell Editor window. In the Place Pins window that pops up automatically, first assign BGA_Pad_500um created earlier as Padstack Name. Holding down the key, select the first pin, and then select the last pin. At this time, all pins are selected; Hold the key and select BGA_Pad_500um from the drop-down list, we can see that all pins are assigned as BGA_Pad_500um, as shown in Fig. 7.25. Then place the pins. There are many placement methods to choose from. Here, select pattern place and BGA pattern type. Other settings are shown in Fig. 7.25. In the pin # column of Fig. 7.26, the default Pin numbers are 1, 2, 3, 4, 5… And need to be renamed. First select pins 1–30, click the renumber pins button, and set prefix to A, starting number to 1 and increment to 1 in the pop-up Auto Generate Numbers window. Then click OK, we can see that the pin number has been changed to A1, A2, A3… A30. In the same way, select 31–60 pins and rename them to B1–B30; Select 61–90 pins and rename to them C1–C30, and so on. There are three points that designer should pay special attention to: ➀ the prefix of BGA pin does not contain some letters, such as I, O, Q, S, X, etc., so these letters should be omitted during arrangement. ➁ Since the pins of BGA is led out from the bottom surface of the substrate, when creating Cell, the side of the BGA pin needs to be set as Opposite, so that when the BGA cell is placed on the top surface of the substrate, its pins is located on the bottom surface of the substrate. ➂ If the side of the BGA pins are set as Mount, the pin number arrangement order needs to be
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Fig. 7.24 Create SiP Cell and setup it properties
Fig. 7.25 Assign Padstack Name and select place pattern
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Fig. 7.26 Rename BGA pin number and set the side to Opposite
mirrored. For example, A1–A31 becomes A31–A1. During layout, BGA cell needs to be placed on the bottom side of the substrate, so it is still A1–A31 from the top view. The pin after placement is 30 × 30, we can manually delete the pins in middle void, select the pins to be deleted, and then press the key, as shown in Fig. 7.27. Finally, add the placement outline and adjust the size and position of Cell characters. Then select File → Save in the menu, and a prompt box as shown in Fig. 7.28 will pop up, indicating that only 504 pins are placed. Do you want to save this Cell with the new pin count? Click Yes. 3.
Create BGA Cell with Die Wizard
Designers can use Die Wizard to create BGA Cell. First, delete all predefined pins in the Place pins window, then close the Place pins window. If we do not delete the predefined pins, there will be a conflict with
Fig. 7.27 Delete the pins in middle void
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Fig. 7.28 Prompt window for pin count update when saving BGA Cell
the pins imported by Die Wizard later. The actual number of pins = (predefined pins + imported pins) is not consistent with the number defined in Cell Total number of pins. Second, edit the pin coordinates and pin numbers of BGA in Excel. It is easier to arrange pins in Excel, as shown on the left side of Fig. 7.29. Then copy and paste the contents of the file from Excel into Note Pad and save it as BGA_CELL.txt, as shown on the right side of Fig. 7.29, it is easy to import with Die Wizard. Then import BGA_CELL.txt with Die Wizard. In Die Wizard, as in the above method, it is important to note that only Die_Pad1 can be selected in Pad Stacks names (because Die Wizard currently only recognizes Die Pin type). After the completion of the import, replace Die_Pad1 with BGA Pad in Cell Editor. Select all Pins in the Place Pins window. Select the first row, press and hold key, then select the last row, hold the key, click on the last row Padstack Name and select the BGA_Pad_500um created above in the drop-down list, complete the replacement, then save and exit.
Fig. 7.29 BGA Pin coordinates and pin numbers definition
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7.7 Part Creation and Application 7.7.1 Mapping Part After creation of Symbol and Cell, we need to map the schematic Symbol and layout design unit Cell through Part, and add related properties to the Part, such as manufacturer, power consumption, cost and simulation model. The creation process of Part is the same as that of symbol and cell. First, create on library manager partitions, such as SiP_ PART. Then click Part Editor button toolbar. After entering, click the new button to create a new Part. Input Die_Part1as Part Number, as shown on the left side of Fig. 7.30. Typically, Part Number serves as a unique identifier for components and cannot be duplicated with other components. Part Name and Part Label can be set by users according to their needs, and their names are relatively flexible, mainly to help users easily identify components. At the same time, according to the design needs, designers can input device power, process, model and other parameters in Component properties. Then, click the Pin Mapping button in the lower right corner of the Part Editor window and the Pin Mapping window pops up, as shown on the right side of Fig. 7.30. In the Assign symbols bar on the left side of the Pin Mapping window, click the to import Symbol; In the Assign package cell bar on the right side import icon to import the Cell. As shown of the Pin Mapping window, click the import icon in Fig. 7.31. Select the symbol in import Symbols window and type 1 in the Mumber of slots in component bar to indicate that this Part contains only one such Symbol. Check the Include Pin Properties and Include pin number mapping as shown in the left window of Fig. 7.31, then click the OK button. Similarly, select the corresponding Cell in import Cells window and click the OK button.
Fig. 7.30 Part Editor window and Pin Mapping window
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Fig. 7.31 Import Symbol window and import Cell window
After importing, we can see that the pin name and pin number have been mapped. Click the Symbol/Cell Preview button in the lower left corner of the Pin Mapping window to see the graphical mapping of Symbols and Cell, and visually check if the correct object corresponds, as shown in Fig. 7.32. If there is a problem with Symbol/Cell mapping, such as pin names does not match pin numbers, a warning window will pops up when saving, indicating the problem. Only when Symbol and Cell mapped correctly, can they be saved properly, which effectively avoids problems when using the library. On the far left side of the signal list bar is defining pin swappability information, for Die_Part1, because pin definitions are fixed, there is no need to define swappability information. Save it in Part Editor, Die_Part1 creation complete. In the same way, create the BGA Part and import BGA Symbol and Cell for mapping, and set the BGA’s pins to be swappability, select multiple pins at the same Set Swappability Pins, as shown on the left side of Fig. 7.33, and time, then click preview the BGA part mapping as shown on the right side of Fig. 7.33. In the Xpedition design flow, all components, including bare chips and SiP packaging, need to be mapped to Parts in design. Since there is no corresponding Cell for power, ground, net connector, border, and so on, no mapping part is required and can be directly added to the schematic from Symbol partition.
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Fig. 7.32 Symbol and Cell mapping complete and preview
Fig. 7.33 BGA Symbol/Cell Pins swappability setting and mapping preview
7.7.2 Create Cell from Part Data When creating BGA Cells manually, it takes a lot of work to rename Pin #. If the Pin Number (Pin #) has already been added when creating Symbol, we can create a Part before creating Cell, import the Pin Number of Symbol to part, then create the Cell, and pass the Pin Number to Cell through Part so that you do not need to rename Pin # in Cell. The Pin # is passed through as shown in Fig. 7.34 below. The detailed operation flow of the software is as follows. (1)
After Symbol is created (Symbols contain pin properties and pin number mapping), create a new part and import Symbol in the Assign symbols area.
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Symbol (Pin #)
Part (Pin #)
Cell (Pin #)
Fig. 7.34 Pin Number (Pin #) passing process
Fig. 7.35 Create Part and import Symbol (input the Cell name)
(2)
Note that Include pin properties and Include pin number mapping should be checked when importing. Enter the name of the cell directly in the Assign Cell area, such as BGA_ Cell416, which is not actually Cell corresponds to Symbol at this time (Fig. 7.35). After Part is created, create a new Cell and select Create cell from Part data, and we can see that the Part Number and Cell Name defined in the previous step are already in the list. After entering the related properties, click the Next button to enter the Cell Editor. In the Place Pins window, we can see that the Pin # area has inherited the Pin Number defined in Symbol and does not need to be renamed, as shown in Fig. 7.36.
7.8 Central Library Maintenance and Management In SiP design process, since Central Library is the starting point of the design, maintaining and managing the central library can not only improve the design efficiency, but also effectively guarantee the product quality.
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Fig. 7.36 Create Cell from Part data
Generally, Central Library needs to be managed by dedicated person, different designers have different rights, and ensure that Central Library is updated in time, as well as correlated with material information system. Below, we describe the common functions of central library maintenance and management.
7.8.1 Common Settings of Central Library 1.
Central Library Parameter Settings
Menu select Setup → Setup parameters, invoke parameters setting window, which mainly sets the default Design units. In the drop-down list, we can select four default units. Depending on the type of library, if it is SiP library, there are many bare chips, Microns is recommended, as shown in Fig. 7.37 below. 2.
Partition Search Paths Management
Fig. 7.37 Default Design units
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Fig. 7.38 Set partition visibility in design environment
Partition Search Paths, primarily sets whether the partition is visible in the design environment Designer or not. If the partition is checked in the Central Library Partition Search Paths, it is visible when placing Parts in design environment, if is not checked, it is invisible in design. As shown in Fig. 7.38. This function facilitates library management, such as the evaluation partition where some new Parts can be evaluated and not visible to designers; after evaluation, place the Parts to the Release partition, which can be available to designers.
7.8.2 Import and Export Central Library Data 1.
Import and Export Data through Library Services
Menu select Tools → Library Services or click on the toolbar icon to open Library Services, to import and export various library elements. Library Services can also move, copy, and delete library elements, such as Parts, Symbols, and Cells between partitions (Fig. 7.39). 2.
Import and Export Data through EDX Format
EDX is short for Enterprise Data eXchange, whcih facilitates the import and export of library data. • Export EDX file Menu Select File → Export EDX, open the window shown on the left side of Fig. 7.40, enter the path and name of the export file in the Output file bar, then select the folder we want to export, click OK, when the export is complete, pop up a
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Fig. 7.39 Import and export library data through Library Services
Fig. 7.40 Export library data through EDX
prompt box, show EDX export successfully, and then click Open file button to open and preview the export file content. The system automatically opens EDX Navigator, and we can see that the selected folders have been exported, as shown in Fig. 7.41. • Import EDX file Create new Central Library EDX_Test_Lib, then select File → Import EDX from the menu, open the window shown on the left side of Fig. 7.42, enter the path and name of the file in the Input file bar, check the Bulk mode, click OK, open the right window of Fig. 7.42, display the data you can import, continue clicking OK to start data import.
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Fig. 7.41 Preview the Export file content
Fig. 7.42 Import EDX file
When the data import is complete, a successful import prompt window appears, close it. At this time in the Library Navigator Tree of EDX_Test_lib, we can see that the EDX library data has been successfully imported, as shown in Fig. 7.43.
Fig. 7.43 EDX data imported successfully
Chapter 8
SiP Schematic Design Input Suny Li
In Chap. 6, we described the design process of SiP, which can be divided into two types: (1) general SiP design process, and (2) SiP design process based on advanced packaging. In this chapter, we will focus on the general design process of SiP, design input based on schematic.
8.1 Netlist Input In the design of SiP, due to the principal connections between multiple chips, as well as the net connections between the chips and the package itself, the connections are complex, so schematic is generally required as the standard input method. However, in single-chip package design, due to its relatively simple connection, only bare chip pins need to be mapped to the packaging shell with certain rules. As a result, many designers have become accustomed to using Netlist as a design input. First, let’s look at Xpedition netlist format. Xpedition can support a variety of netlist formats, here is the most commonly used Keyin Netlist. It is an ASCII code file and is usually saved as *.kyn. Its content is mainly divided into two parts: %net and part%, as shown in Fig. 8.1. The %net section starts with%page = NEWSCHEMATIC1, and the first column is the net name, such as \AD0\, followed by the pin name connecting to this net, such as \C1\-\1\, indicates the first pin of C1, \U1\-11\ indicates the 11th pin of U1. The %Parts are followed by a list of components, the first column is the component Part number, such as/BGA100/, and the second column is the component Reference Designator, such as/U4/.
S. Li (B) Beijing, China e-mail: [email protected] © Publishing House of Electronics Industry 2022 S. Li (ed.), MicroSystem Based on SiP Technology, https://doi.org/10.1007/978-981-19-0083-9_8
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Fig. 8.1 Keyin Netlist format
If it is a single chip package, it is simple to write the netlist. According to the above file format, except for the special allocation of power supply and ground according to the design requirements, the signal pins are basically one-to-one allocation from the chip to the package, and there are only two components, namely, IC bare chip and Package. After editing the netlist in standard format, we can create the project. In Xpedition Layout environment, select File → New to launch Job Manager Wizard, set the path where the project will be stored, enter the project name as shown in Fig. 8.2, and then click the Next button. Select a central library in Project Editor, such as SiP_Lib2020.lmc, and a preedited Keyin netlist file such as netlist.kyn. Note that the netlist type select Keyin Netlist, then click the OK button, the Central Library and netlist are assigned to the new project, as shown in Fig. 8.3. Click OK to enter the next step. Select the design technology. There are three options: PCB, Package and RigidFlex. Here, select package; Layout template select HDI 2 + 4 + 2; For the layout design path, just keep the software default option, and then click Finish to open the summary window, displaying some information of the project, and then click close, as shown in Fig. 8.4. The software automatically enters Xpedition layout, Menu select Setup → Project Integration for Forward Annotation, components and netlist are brought into the layout environment and layout design can be carried out (Fig. 8.5). In addition, Xpedition supports several other formats of netlists, which can also be used as design input. the operations are basically the same as above. due to the space limitation, it will not be repeated here.
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Fig. 8.2 Create new project with Job Manage Wizard
Fig. 8.3 Assign Central Library and Netlist to the new project
8.2 Schematic Design Input 8.2.1 Schematic Tool Introduction In general SiP design process, schematic is usually used as standard input.
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Fig. 8.4 Specify design technology and template to complete project creation
Fig. 8.5 Components and netlist are brought into the layout environment
In the design process of Xpedition platform, Xpedition Designer (hereinafter referred to as Designer) is the standard schematic input tool. Designer can support basic schematic input, component invocation based on DataBook and material information association, RF schematic input, and HyperLynx AMS simulation for digital/analog mixed circuits. These modules require appropriate License support, see Fig. 8.6. to launch Designer. In Shortcuts of Dashboard, click the icon Before we start Designer, if a project in Projects list of Dashboard is set to Active and shown in bold type in Fig. 8.7 below, Designer will automatically open the project
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Fig. 8.6 Extensible license above the basic schematic module
Fig. 8.7 Bold indicates Four_Chips project is an Active Project
after starts, and we can switch other items in the list to Active Project by clicking on them with the mouse. After startup, Designer window contains several sub windows, including Navigator window, schematic workspace, component placement window DataBook, etc. the display is shown in Fig. 8.8. In the Navigation window, we can see that active project has been automatically opened. In addition to the above interfaces, there are many sub windows in designer, which can be opened or closed by buttons. The functions of some key tools are briefly introduced below. 1.
Common Tools Buttons
• Navigator Button Navigator is mainly used to browse and manage various elements in the project. After opened, it usually appears on the left side of the interface. When the licenses of all functional modules are started, the navigator will have three TABs: Project, RF Groups and Simulation. Among them, Project TAB is mainly used for project management. Designer supports the management of multi-board projects. For example, in Fig. 8.9a, one project managed FC_PACKAGE, PCB_Board and RDL three layout designs. Each layout contains its own schematic. Each schematic can be composed of one or more pages.
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Fig. 8.8 Designer starts and auto open Active Project
Fig. 8.9 Project, RF Group and Simulation TAB in Navigator
Generally, each board has only one valid schematic, and other schematics will be placed in the block. We can right-click the create board command to convert the schematic in the block into a board (it is actually the valid schematic of the board, that is, a new board can be created through this schematic). We can also right-click the board and select the delete command to delete the board. The schematic will be automatically converted into the block. The schematic in blocks cannot package and generate the layout, but can be referenced by other schematics. RF Groups TAB is mainly used for the management of RF design functions, including the creation and management of RF groups and the call and management of other RF functions, as shown in Fig. 8.9b.
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Simulation tab is mainly used to manage the functions of the simulation tool HyperLynx AMS, including the generation and management of TestBenches, the import and management of simulation model library, etc., as shown in Fig. 8.9c. • DataBook Button DataBook is primarily used for calling and placing components, including Part View, Symbol View and Reuse Blocks. Common components are selected in the Part View, which usually has a physical cell corresponding to them. Symbol View is mainly used to place symbols such as boxes, power supply, ground and connector. Reuse Block is mainly used to place Reuse Block, including logical (schematic) and physical (schematic + layout) Reuse Block (Fig. 8.10). Select desired components in the list, then click the Place Symbol button on the right or drag the components directly into schematic. We can also enter the filter conditions in the filter box above the list. Only the components that meet the filter conditions will appear in the list, making it easier to find the components. We can check Add Nets and Add Net Names when placing components so that the nets are automatically generated and named, as shown in Fig. 8.11.
Fig. 8.10 DataBook interface (CL View)
Fig. 8.11 Add Nets and Add Net Names options
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Fig. 8.12 Symbol Properties of ICT Viewer
Another powerful feature of DataBook is the Search window. Click the New in the upper left corner of DataBook to launch the Search Search Window button window. A detailed description of the feature is given in Sect. 8.3. • ICT Viewer Button ICT Viewer (Interconnectivity Table Viewer), including 3 TABs: Hierarchy, Net Properties and Symbol Properties. These three are used to view the net connections of components, net properties and component properties respectively, and can be used to quickly filter, classify and search design elements. Figure 8.12 shows Symbol Properties. • Xpedition PCB Viewer Button Xpedition layout viewing tool. With this function, we can view the layout in schematic environment. The premise is the Create eExp View during Back Annotation option checks (see Chap. 9 for options in layout design), and has successfully performed Back Annotation (i.e. update data from layout to schematic). With Xpedition PCB Viewer, when designing schematic, we can easily view the layout design and make interactive selections and checks, without occupying the layout design license. For example, when a project enters the layout design stage, the schematic designer needs to check layout design with this mode. As shown in Fig. 8.13. • Selection Filter Button Selection Filter makes it easy for designers to select different objects in schematic. The top side drop-down list allows designers to quickly select all options, cancel all options, or select according to different types, as shown in Fig. 8.14. • Add properties Button Add properties button makes it easy for designers to add properties to the same class of objects, as shown in Fig. 8.15, adding properties to Component and to Net, respectively.
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Fig. 8.13 Xpedition PCB Viewer in schematic environment
Fig. 8.14 Selection Filter
Fig. 8.15 Add properties interface
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• Color by net Button Color by net button can easily assign different colors to the nets, which is different from changing the net color in properties window. Color by net can be opened or closed immediately. It is very personalized and can effectively improve the readability of schematic browsing. It is more flexible than properties window to change net color. then select a net, and a gray arrow It is convenient to set color by net. Click appears next to the net. Click the arrow with the mouse to set the special color property of the net, as shown in Fig. 8.16. After setting, we can switch whether to display the color by clicking the color by net button. , When pressed down Color by net button, it becomes a wireframe button the Special Color displays, when clicked the button again, it becomes an unchecked display, and the Special Color turns off. The left and right sides of Fig. 8.17 show
Fig. 8.16 Add special color attribute to net
Fig. 8.17 Special color display and color properties change
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the change of net color display status and property bar when Color by net is turned on or off, respectively. If we want to delete the property of Color by net, menu select Setup → Settings → Display → Colored nets, select the appropriate net name, and click the Delete button below. Please also note that the opening and closing of Color by net also affects the display of output files, such as the output PDF document that will be displayed in the same state as Designer at that time. 2.
Display Control and Schematic Layer
in toolbar to open Menu select View → Display Control or click the button Display Control window, which is a function learned from Xpedition Layout to easily control the display of schematic and enhance their readability. Display Control window is divided into two TABs, Objects and Properties, which . can be expanded or collapsed from the top icon Objects TAB is divided into 8 items, which control the Appearance, Text, Border, Navigator, Layer, Net color, Cross Probing, Selection and Highlighting. Each item is divided into several subitems, which can be expanded by the plus sign before it. Properties TAB is divided into 2 items, Properties and model Properties, as shown in Fig. 8.18. Because of the space limitation, we cannot explain all of them. It is helpful to familiarize yourself with the design environment by clicking on each option, check its sub-options, and see the changes shown in the schematic. Enter keywords in the input bar above the window to quickly find the items we want to display, or click the Save button below to save the display scheme setting. It is worth mentioning that there is also layer concept in Designer. We can add user-defined layers and corresponding labels and text information in different userdefined layers. It is very convenient to simply open the corresponding layers when needed and close them when not needed, without affecting the information of the schematic itself. Figure 8.19 shows the addition of three user-defined layers, Layer0, Layer1, Layer2, and the addition of square, circular, and text to the corresponding layer.
Fig. 8.18 2 TABs of Display Control
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Fig. 8.19 Add graphics and text to user-defined layer
In addition, we should pay special attention to that after the concept of layer is established in the schematic, only the data of the current layer can be edited, and the data of non-current layer cannot be edited, which effectively avoids misoperation. If we need to edit the data of a layer, first use the right-click menu set as current layer to edit the data of this layer. The current layer is displayed in bold. For example, schematic on the left side of Fig. 8.19 is current layer. At this time, the data of layer0, layer1 and layer2 are not editable. Therefore, if the data cannot be edited, please check whether the element is located in the current layer. Double click the mouse to open the properties window to view the user layer property. It is also important to note that elements with electrical characteristics, such as components, connections, are placed on Schematic layer and cannot be changed, so they have no User Layer property. 3.
Toolbar Video Help
When starting to learn an EDA software, engineers need to consult the help files, which to some extent affects the efficiency and enthusiasm of learning. Xpedition has original toolbar video help form, more intuitive, visualized, very convenient for engineers to self-study, to a certain extent, improves the learning efficiency. When mouse pauses on the tool icon, a text prompt box appears. If the word (VIDEO) appears at the end of the prompt box, it indicates that this tool icon has video help. If the mouse stays for more than three seconds, the help video plays automatically, which makes it very easy for engineers to understand the function of the tool. Figure 8.20 is video helps screenshot of Multi-net connection and Specal Components, respectively. If the mouse stays on the tool icon, the video will play repeatedly until the engineers fully understands it. 4.
RF Design and Circuit Simulation Toolbar
, this toolbar is mainly used for RF RF Design Toolbar: circuits design and data transfer with RF simulation tools (ADS/AWR). For detailed operation, please refer to Chap. 16 of this book. , Simulation Toolbar: this toolbar is mainly used to support the digital/analog mixed circuit simulation and
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Fig. 8.20 Video helps of Multi-net connection and Specal Components
the view of simulated waveforms. The introduction of simulation tool, please refer to Chap. 21 of this book.
8.2.2 Create Schematic Project In Designer, menu select File → New → Project, the dialog box pop up shown in Fig. 8.21, and select Xpedition → default in the Project Templates on the left. Xpedition → Xpedition AMS can be selected if the schematic of the digital/analog mixed circuit simulation is needed.
Fig. 8.21 Create new project in Designer
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Fig. 8.22 Create new board and schematic then rename them
Click the browse button on the right side of the Location bar to select the path of the project, and then enter Project Name in the Name bar for example: SiP_Project1, the Location bar will automatically add the name after the selected path. The Central Library Path bar is used to select the path to the central library. We can find the path to the central library by clicking the browse button on the right, such as E:\Projects\SiP\SiP_Lib\SiP_Lib.lmc. Enable concurrent design option is designed to support multi-person concurrent schematic design and is usually unchecked. If engineer want to do concurrent schematic design, that is, multiple people design a schematic at the same time, check this option and enter Server name. For detailed description of multi-person concurrent schematic design, please see Chap. 18 of this book. When all items are input, click the OK button and the new project is created successfully. In the new Projects, select File → New → Board from the menu, and the system automatically creates a new Board and the corresponding Schematic. Rename Board to SiP_Board and renamed schematic to SiP_Sch with right-click menu, as shown in Fig. 8.22. The next step is to select the needed components for schematic design. Generally, there are two main types of components in SiP design: ➀ The components in the package include bare chips, passive resistor devices, etc. ➁ BGA and other types of packaging shell. and place components in CL view mode. When Click the databook button looking for components, we can use the filtering function to select components more quickly and accurately. For example, if we enter SiP in the blank column above part, the system will automatically display only components whose names begin with SiP, as shown in Fig. 8.23. The filtering function is effective for all columns, such as partition and symbol columns. After selecting appropriate components from the library and placing them in schematic, we can close the window of databook, so that the working area will be expanded and easier to operate. The next step is to interconnect components. There are many methods of interconnection. If Add Nets and Add Net Names options are checked when placing components, the net and net name will be automatically added to the schematic, the added net names are consistent with the symbol pin name. At this time, nets with the
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Fig. 8.23 Use the filtering function to find and place components
same pin name in schematic will be automatically connected together, which is very convenient for the design of using signal name as pin name.
8.2.3 Schematic Basic Operation The tools used in schematic basic operation are located in Add toolbar. Combined with the corresponding functions of the tools, we describe the basic operation of schematic. , which is Add toolbar mainly used to add, connect, copy, delete and other operations. Let us describe the tools use methods one by one. Select Button (VIDEO) The Select button is used to select elements in schematic and can be used with to select different elements. The tool has video help and stays Selection Filter the mouse on the tool icon for 3 s, the video will play automatically. Rotate 90 Degrees Button (VIDEO) After selecting the component symbol, the icon will be valid. Each time you click the icon, the component symbol will rotate 90 degrees. The tool has video help and stays the mouse on the tool icon for 3 s, the video will play automatically. Block Button (VIDEO)
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Fig. 8.24 Draw a block and push into the inside schematic
The block button is used to draw the function block in schematic, which is used as the top-level module of the hierarchical schematic design. With the push command, engineer can enter the schematic included in the block. When connecting the nets, the pins of the block are automatically added, and its name is automatically consistent with the connected net name. After the block is drawn, use right-click menu and select push to enter the schematic inside block. We can see that the nets connect pins has been automatically placed in the schematic as a hierarchical interface, the engineer only needs to add components at this schematic and connect the nets to realize the hierarchical schematic design, as shown in Fig. 8.24. ADD Part Button The function of the tool is the same as that of databook, and the icons are the same. They are used to place devices. Net Button (VIDEO) The net button is used to add net connections to components in schematic. In the process of adding, the mouse cursor also attaches the symbol of adding net. This tool also has video help. Multi-Net Connection Button (VIDEO) Multi-Net Connection button can connect multiple nets at the same time. The mouse first selects one set of pins, then another set of pins. The software automatically connects according to the selected order, which can effectively improve the design efficiency. During the adding process, the mouse cursor also attaches the symbol of multi-net connection, and the tool also has video help. Bus Button (VIDEO) Bus button is used to add bus connection in schematic. The bus is quite intelligent, after the bus is drawn, as long as the nets or device pins are close to the bus, the system will automatically allocate the bus branch to the nets or device pins. In the process
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of adding, the mouse cursor also attaches the symbol of bus connection, and the tool also has video help. Text Button Text Button is used to add text notes to schematic. Text can be added to userdefined layers for display and editing independently. User-defined layer is a unique feature of designer tool. Array Button (VIDEO) Array Button is used to copy circuits in array mode. first select the circuit to be copied in schematic, and click the array icon to pop up the array window: ➀ Rectangular array, enter the number of rows and columns, and move the mouse to adjust the spacing to obtain the circuit copy results as shown in the upper part of Fig. 8.25; ➁ Diagonal vector, enter the quantity to be copied, and move the mouse to select the appropriate position to obtain the circuit copy result as shown in the lower part of Fig. 8.25. The tool also comes with video help. Special Components Button (VIDEO) It is mainly used to define input/output, cross page connection, power supply, ground and other common pins.
Fig. 8.25 Circuit copy in array mode
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Fig. 8.26 Special Components definition
When using it for the first time, we need to define it through the settings window, select the corresponding symbol from the central library, and use it directly after it is defined. In the special symbol drop-down list, select an undefined symbol, such as button, select BI, and the setting window will pop up automatically. Click new the corresponding symbol in Central Library builtin partition, as shown in Fig. 8.26, and then click OK. Then, we can see that this symbol has been defined in the special components drop-down list. At this time, we can directly select it and place to schematic. The tool has video help, which can be reference. Add Properties Button It is mainly used to batch add attributes to devices, nets and pins, has described in the common tool buttons above. Reassign names Button (VIDEO) It is mainly used to exchange the names of adjacent nets. The tool has video help, which can be reference. Delete Button It is mainly used to delete elements such as components or nets. Disconnect Button (VIDEO) It is mainly used to disconnect the components from the nets, so as to facilitate the replacement or movement of components. The tool has video help, which can be reference.
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Fig. 8.27 The completion of schematic drawing
Cut Net Button (VIDEO) It is mainly used to cut off the net or bus. The tool has video help, which can be reference. Combined with the introduction of the above 15 tools, we also have a certain understanding of the basic functions of schematic and draw a complete schematic diagram. As shown in Fig. 8.27, it contains three pages of schematic diagram, of which the first page contains three devices and a block1. We can enter the inner schematic of Block1through push.
8.2.4 Schematic Design Check After the schematic drawing is completed, first check and verify the schematic design, menu select tools → verify, and select the settings in the pop-up verify window. In the left navigation bar, we can see that a total of 11 sub titles of verify can be set. They are explained as follows. ➀ Settings, basic options of verify, such as the name of board and schematic, the scope of verify including board, schematic, sheet, configuration file, etc., usually keep the default option. ➁ Interconnectivity, (1) Check whether different types of pins can be directly connected. There are 54 items in total. Each item can be set with four different ignore the check, give a report, give a warning and report forms: prompt an error. We can click the check item with the mouse to switch; (2) Check whether different types of pins can be connected through resistor. There are 45 items in total. As shown in Fig. 8.28. The premise of correct report is that when
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Fig. 8.28 Interconnectivity check items in Verify window
building the component library, the pin type is consistent with the actual, as shown in Fig. 8.29. ➂ Migration, check the format and length of the name. There are 9 check items in total, all of which can be selected. ➃ Connectivity, a total of 29 checks, here, we can choose DRC-109, DRC-110, DRC-119, DRC-123, DRC-127, DRC-128 six items to check. ➄ Electrical, check whether the schematic electrical design is compliant with rules, such as OC gate pull-up, power voltage drop check, etc., there are six checks, some options need to set the range, we can choose to check all. ➅ Hierarchy, mainly checks whether the connection relationship between different levels of the hierarchical schematic is correct. There are five checking items, all of which can be selected for checking.
Fig. 8.29 Pin type assignment during library creation
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➆ Integrity, mainly check whether the schematic Symbol properties are integrated, whether the symbol mapping is normal, etc. There are 12 checks, 10 checks can be selected except DRC-403, DRC-404. ➇ Power&Ground, there are 11 checks for power and ground inspection, 9 of which can be selected to check, remove DRC-501 and DRC-404 for inspection. ➈ Device Specific, there are a total of five checks for device specific, each of which contains sub-items, we can choose to check all. ➉ HDL Checks, there are a total of 8 checks, which need to be checked if the design contains code written by VHDL or Verilog. Links, check the links, a total of 4 items, all of which can be selected. The final check items selected are shown in Fig. 8.30 below. The left side of shows the number of checks for each item, and the right side shows the six selected checks for the Connectivity. The above selected items are only an example, different project requirements, including different specifications of the library, check items need to be adjusted accordingly. Designers can also change the Value of related check items as needed and adjust the severity of check report prompts, such as Note, Warning, and Error. We can also keep the default check items if we don’t have a specific inspection requirement. When the setting is complete, click OK and the software begins to check.
Fig. 8.30 DRC check items selection
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Fig. 8.31 Verify results output
After the Verify is complete, we can view the Verify results in the Output DRC report window. Here, 2 Errors and 18 Warning appear in the output window, as shown in Fig. 8.31. The report shows that two errors are caused by inconsistencies with the pin type definition of power/ground symbol and net VCC/GND, 18 Warnings are caused by the existence of one pin net. The pin type definition needs to be modified in central library, and one pin net only needs to be modified in schematic. In Library Manager, change the power/ground pin type to POWER and GROUND, then menu select Tools → Update Libraries in the designer to update the library, and then Tools → Update Symbol to update the symbols, run Verify again, these 2 errors disappear and the problem is resolved. Then modify the one pin net in schematic. It is important to note that sometimes other errors or warnings will occur during the modification process. It is necessary to carefully confirm whether the warning or error will affect the design. Some check items that will not affect the design itself can also be removed until the final design check can pass. As shown in Fig. 8.32. If the check result has no error or warning, or engineer has confirmed the warning or error information, we can proceed to the next step.
Fig. 8.32 Design check pass
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8.2.5 Design Package Menu select Tools → Package, the Packager window pops up, as shown in Fig. 8.30. Note that the Package described here has a completely different meaning from the previous chapters Package, here Package refers to “design package”, in which data such as device information, net connections, rule definitions in schematic are packaged and passed to layout design through Package. Some options for Package are briefly explained below. The Project bar defaults to the current project file and usually does not need to be changed. The control options consist of two parts: Packaging Options and PDB Extraction Options, please see Fig. 8.33. 1.
Packaging Options
(1) Operations sub-option include Package Symbols, Repackage All Symbols, Repackage Unfixed Symbols and Verify Packaging 4 items, as shown in Fig. 8.34. Package Symbols are most commonly used to package devices that do not specify a reference designator Ref and the devices that are not packaged; Repackage ALL Symbols package all devices, including those previously packaged, removes all the packaging properties of the Frozen Package; Repackage Unfixed Symbols, packages all devices except those with the “Frozen Package” property, and packages unpacked Fig. 8.33 Packager window
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Fig. 8.34 Operation sub-option
“Frozen Package” devices as well; Verify Packaging, check the correctness of the package, and if there are Package errors, write them to the Partpkg.log file. If the property Frozen Package = Fix, Package Symbols and Repackage Unfixed Symbols options cannot change the existing reference designator and pin numbers, but the Repackage All Symbols option removes this property and can change the reference designator and pin numbers. (2) The Optimization sub-option contains three options, Board, Block and Page, indicating that the Symbols that can be merged into the same Part within the Board, Block, or Page are merging packaged (in the case of multiple Symbols in one Part), as shown in Fig. 8.35. (3) Scope sub-options set the scope of package, including all designs, schematics, pages, blocks. If left blank, the entire design is packaged. (4) Other options, as shown in Fig. 8.36. ➀ Update PDB Properties on Symbol, Update component properties from the Part database to schematic symbols. ➁ Allow Alpha-Only Reference Designators, allows only alphabetic Reference Designators to exist. ➂ Log CDB Data, Writes packaging information to the log file. ➃ Fill Reference Designator Gaps, when packaging, fill in the numbering breakpoints of the reference designators so that they are numbered consecutively. ➄ Report warnings for single pin nets, report the single pin nets warning information. Fig. 8.35 Optimization sub-option
Fig. 8.36 Other package options
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Fig. 8.37 PDB extraction options
2.
PDB Extraction Options
The library PDB extraction options mainly contain 5 items, as shown in Fig. 8.37. ➀ Only Extract Missing Library Data. Only extract library data that do not exist in the local database. ➁ Extract Missing with Selected Library Data. If the library is updated during the design process but not all the devices are packaged with the latest ones of the library, click on the Select button to select. If all the devices are as new as in the library, the prompt is: There is no out-of-date parts in this design. ➂ Update Local Library Data with newer central library data. To extract new data from the central library to update components that already exist in the local library. ➃ Rebuild Local library data; Preserve locally built data. Rebuild local database, but data imported directly into the local database or built locally is protected. ➄ Delete local data, then rebuild all local library data. Delete all local data and re-extract from the central library. In actual design, when packaging, we can select the options according to the design needs. Usually item➀ is selected for new designs. However, if in the design process, the central library data has been updated, including Symbol, Cell or Part changes, then select the following items: ➁➂➃➄ as needed, to update the local library data from central library. It is important for designers to note that, in addition to selecting options here, the corresponding options need to be selected in the Project Integration window of the layout tool Xpedition, and the two need to be consistent. For example, if PDB Extraction Options in Packager selects Item 2, Library Extraction Options in Xpedition also needs to select Item 2, as shown in Fig. 8.38, to achieve the desired results. Fig. 8.38 Library extraction options in Xpedition
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Fig. 8.39 Packager finished successfully
After the design package, if prompted as Fig. 8.39, the packager finished successfully. We can enter Xpedition for layout design. If the Package is unsuccessful, an error prompt will appear and the Packager window will automatically pop up again. At this point, we need to view the error information and modify the parts in schematic based on the information, until the Package is successful, then we can enter the layout design.
8.2.6 Output Partlist In the main interface of designer, menu select Tool → Part Lister to output the partlist for production or purchase. The partlister window is divided into four options: General, Advanced, Columns and Header. In General options, Output File Name sets the name of the output file, Scope sets the coverage of the Partlist, include Project, Board or Block. If there are multiple Boards or Blocks in the project, we can choose from the drop-down list. Open the generated file option, when checked, the generated Partlist file will open automatically. The Output format in Advanced option is used to set the output format, which includes Text, HTML, and EXCEL, and can be selected from a drop-down list. Columns option is primarily used to set the contents of the Partlist output file. The list on the left shows the list of entries output from the Partlist. We can create new entries or delete entries by using the tool button on the top, and arrange the order between entries. The right side configures the selected entries. Header option is used to configure the header file and configure information that needs to be output, such as design name, output date, creator name, company, and so on. The four option settings are shown in Fig. 8.40. After the setup is completed, click the Run button at the bottom to output the Partlist file. As shown in Fig. 8.41, the design contains seven types of devices, BGA104PACKAGE belongs to the external package. There are 26 die types of components, of which SIP_7 is Two Pins Die, there are 21, reference number from U4-U24.
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Fig. 8.40 Partlister configuration options
Fig. 8.41 Output HTML format partlist
8.2.7 Schematic Chinese Menu and Chinese Input For Chinese designers, English cannot replace their native language. There are two main aspects of Chinese designers’ preference for their native language: (1) they want tools have Chinese menus, (2) they want to input Chinese text as design specifications and explanatory in the process of schematic design. Both are well resolved in Xpedition now. 1.
Chinese Menu
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Fig. 8.42 Menu language setting in Designer
Xpedition Designer currently supports five languages: English, Chinese, Japanese, Portuguese, Russian, the default language of software is the same as the language of operating system (Fig. 8.42). In Setup → Settings → Advanced → Language bar, we can select a language from a drop-down list. Default is consistent with the language of operating system, so in the Chinese operating system environment, we can display the Chinese menu by Default. After the setup is completed, we need to close and reopen Designer to valid the settings. After reopen Designer, we can see that the menu has been switched to Chinese. Besides the menu being displayed in Chinese, the explanatory text of the video help has also become Chinese, which is very convenient for beginners to learn, as shown in Fig. 8.43. 2.
Chinese Input
In addition to the Chinese menu, it is very convenient to input Chinese in Designer. First, configure the Chinese font library, menu select Setup → Settings → Display → Font Styles to map Chinese fonts, such as Fixed in Style, “宋体” in Font, Simplified Chinese in Charset; and select Kanji in Style, “隶书” in Font, and Simplified Chinese in Charset so that we can map Chinese fonts to Western fonts, as shown in Fig. 8.44. In the same way, we can also map other Chinese and Western fonts such as Script to “楷体”. Once the font mapping is complete, click the Apply or OK button, then input Chinese in Designer page.
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Fig. 8.43 Chinese menu and Chinese tips
Fig. 8.44 Chinese Font mapping
Click the Text button , then click the left mouse button in workspace, and enter Chinese directly in the pop-up window. The text defaults to Fix font because it is already mapped to “宋体”, so it appears as “宋体”. If we want to display other fonts, such as"隶书”, we can change the font to Kanji, which is already mapped to “隶 书”. If we want to display “楷体”, we can change the font to Script, which is already mapped to “楷体”. From Fig. 8.45, which shows Chinese words in schematic, we can see that more than one Chinese fonts on the same page of schematic. Text descriptions can be placed in User Layer in project, which makes it easy to manage, turn on or off in layers. Refer to 8.2.1 in this chapter for setting up and using custom layers. In addition to mapping fonts for Chinese, sometimes for tidy and beautiful design, mapping Fonts is also required for Western text. For example, Fixed is a Western style with loose character spacing and thin strokes. When mapped to Song or Arial, its effect will be significantly improved, and the page neatness and display effect will be greatly improved.
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Fig. 8.45 Input Chinese (multiple fonts) in schematic
In the design environment of a computer, fonts only need to be mapped once, and the font mapping is valid no matter whether you open Designer for schematic editing or edit symbols in Symbol Editor of Library Manager. If the software is reinstalled, font mapping needs to be set again.
8.3 Schematic Input Based on DataBook 8.3.1 Introduction to DataBook DataBook provides an efficient component information management and lookup function for design. It enables R&D (including schematic design and layout design), procurement, production and other functional departments to share component information on a unified platform and to ensure that the components used in the design conform to enterprise standards. The latest component information in R&D, procurement and production can be quickly fed back through DataBook, which effectively avoids the delay of development or production due to incomplete product information, and helps to optimize the selection of components. DataBook can also be used for cost accounting during the schematic design phase, based on the price information of components in the material system. DataBook is a bridge between the schematic symbol library and the component property information library, which can save a lot of schematic symbol library time. Users only need to create a symbol for each component, the symbol itself have no properties, all of its properties can be called from DataBook at design time.
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Fig. 8.46 DataBook interface (Search)
DataBook has the function of property verify. It can verify the component information in design according to the standard component information in material system, find out the non-standard components in design and give warning, which provides effective guarantee for the smooth implementation of product preparation, production and other processes. DataBook can connect to component information database of the company (Fig. 8.46). When placing components, we can also put the related information of the components together into schematic, such as the parameters, price, inventory, manufacturer, etc. Using DataBook can effectively reduce the workload of building a library. For example, there are many types of resistors, resistance values, power, accuracy, and so on. Although the parameters are different, the Symbol of resistor in schematic is the same. If we do not use DataBook, we need to map many parts in the library, which is time-consuming and laborious. With DataBook, we can just create one part and then enter a variety of properties information for different components in DataBook data source. DataBook needs to be configured before it can be used properly. Due to the size of the book, it does not describe the detailed configuration of DataBook, but only describe how it is used.
8.3.2 How to Use DataBook Click the Next Search Window button in the upper left corner of DataBook to open a new Search window, right-click in the new window, select Configure →
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Open, open the pre-configured Central_Lib.dbc file in the central library, then click the drop-down arrow on the right side of the Library bar, and a list shown on the left side of Fig. 8.47 appears. Selecting any of these, such as 普通芯片 (common chip), the Select Database window automatically pops up and then selects the CIS.mdb database file configured in the central library, as shown on the right side of Fig. 8.47. After clicking the OK button, a list of components appears as shown in Fig. 8.46. In the list of Fig. 8.46, we can see properties such as 物资代码, 型号, 生产厂家, 所属大类, 所属中类, 所属小类,器件手册, 封装形式, etc. In addition to facilitating component selection by designers, these attributes can also be automatically loaded into the component properties in schematic, as shown in Fig. 8.48. In the process of standardized file archiving after the design is completed, these properties can be automatically extracted by the software to form standardized documents, which does not require the designer to fill manually at all, saves a lot of time, effectively avoids errors that are prone in manual operation, and ensures the consistency of design and documents.
Fig. 8.47 Select database file for Databook
Fig. 8.48 Components and its properties in schematic
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Fig. 8.49 List only all components manufactured by TI
Below each property bar are filters to help designers filter the components. After setting the search criteria, if the manufacturer is TI, click the exclamation mark button , the list will only list the components that the manufacturer is TI, as shown in Fig. 8.49. By clicking the left mouse button on the dynamic link of the device manual bar, we can directly open the device manual or DataSheet related to the component, as shown in Fig. 8.50, which is very convenient to use. If we want to access the components of another partition, simply select another partition in the drop-down list. Figure 8.51 is a partial device screenshot of the transistor partition in DataBook. Figure 8.52 is a partial device screenshot of the connector partition in DataBook.
Fig. 8.50 Open device manual via dynamic link
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Fig. 8.51 Transistor partition devices in DataBook
Fig. 8.52 Connector partition devices in DataBook
8.3.3 Verify and Update Component Properties An important function of DataBook is to verify and update the properties of components. For example, if we have used a component in schematic design and its properties are later updated in Central Library, DataBook can automatically check for inconsistent properties with the Central Library and update the schematic. This process can be simulated experimentally. First, delete or change the values of the class attributes of a component in the schematic diagram, as shown by the red arrows in Fig. 8.53. in the left toolbar of DataClick the New Live Verification Window button Book to open the Verify window. we can see that the status light on the left side of this component is yellow, indicating that there is inconsistency between the properties of the component in schematic and those in DataBook, and that the properties are missing in the Status bar, which is inconsistent with those in Data Book. at the top right of the window to see Click the Update all Unique Match button the list of components on the right side of the window. The values of the classes have been updated. At the same time, the state of the left-end of component has changed from yellow to green, and the status bar shows OK, indicating that the properties of this component have been updated by DataBook. Go back to the schematic to check the component. We can see that the properties have been automatically labeled from DataBook to component, as shown in Fig. 8.54.
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Fig. 8.53 Artificially delete the Value of classes
Fig. 8.54 Component properties values updated
8.4 File Input and Output 8.4.1 Common Input and Output Data interaction with the outside software is often required in schematic design. Xpedition Designer, as a standard schematic input tool, provides a rich data interface to import data in 17 different formats, as shown in Fig. 8.55. It includes the mainstream design tools in industry, including Altium, P-CAD, CADStar, OrCAD, EAGLE, PADS Logic, Concept HDL, Zuken CR and so on. When selecting these formats of data, the software automatically calls the corresponding converter to convert its schematic to Designer’s format, and converts the
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Fig. 8.55 Designer importable data format
corresponding symbols into symbol library of the design, which is very convenient. Figure 8.56 shows the schematic of the OrCAD format imported in Designer. At the same time, Designer also supports the import of DXF format. It can import border and other graphics drawn in AutoCAD, convert them into border symbols, and use them in schematic design. Similarly, in schematic design, design data needs to be exported to other tools for data interaction. Designer can also export data in 17 different formats, as shown in Fig. 8.57. These include various formats of netlists: EDIF Netlist, VHDL Netlist,
Fig. 8.56 OrCAD format schematic imported into Designer
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Fig. 8.57 Designer exportable data format
Verilog Netlist, Analog Netlist, Keyin Netlist, RINF Netlist, etc. with these netlists, different tools can be used for subsequent design. At the same time, Designer also supports the export of DXF format, which can output the schematic drawn by Designer to AutoCAD for file archiving and output. Designer also supports the output of PDF files, which can contain component property information for design auditing and checking. Figure 8.58 is a PDF file output by Designer. Click on the components with the mouse to view the property information.
8.4.2 Output to Simulation Tool In the process of schematic design, sometimes it is necessary to simulate the signal to determine the topology, match resistor, drive capability of components and other parameters. The related nets can be exported from Designer to HyperLynx for simulation. First select the nets we want to simulate, such as AD1 net, and then select HyperLynx LineSim from the right-click menu. Open the following window, which contains two TABs, Options and Schematic Topology, Options TAB used to configure the output information, and Schematic Topology to view the net topology. See Fig. 8.59. If the layout physical parameters are uncertain, we can keep the default settings. Click Export to HyperLynx, HyperLynx will open and import the net information automatically. Simply attach a model to simulate and get the waveform information, as shown in Fig. 8.60.
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Fig. 8.58 PDF file exported by Designer
Fig. 8.59 Output to HyperLynx LineSim interface
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Fig. 8.60 Export net to HyperLynx and simulate
Please Refer to Chap. 21 of this book for instructions on how to use the HyperLynx simulation tool.
Chapter 9
Layout Creation and Setup Suny Li
9.1 Create Layout Template 9.1.1 Layout Template Definition Layout Template is a standard layout defined in central library that can be referenced by layout design. The information contained in layout template mainly includes Layer Stackup, material parameters, substrate shape, mounting holes, fixed position connectors, etc. For Layer Stackups or substrate shapes that are often used, we can define specific layout templates in Central Library beforehand and referenced directly when designing. This saves design time and is conducive to the standardization of layout design. The substrates used in SiP include: organic substrate, ceramic substrate and silicon substrates. Different materials of the substrates have different Layer Stackup and material parameters, which usually require different layout templates to be created. 1.
Organic Substrate
Organic substrates usually use HDI (High Density Interconnection) substrates. At present, the m + N + m type Layer Stackup is commonly used. m refers to the layer occupied by the laser microvia, commonly referred to as the Buildup layer. N refers to the layer occupied by mechanical drilling, commonly referred to as Laminate layer. Figure 9.1 shows a typical 2 + 4 + 2 HDI Layer Stackup. The usual method is to press Laminate layers together, punch mechanical holes, and then make buildup layers. S. Li (B) Beijing, China e-mail: [email protected]
© Publishing House of Electronics Industry 2022 S. Li (ed.), MicroSystem Based on SiP Technology, https://doi.org/10.1007/978-981-19-0083-9_9
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Prepreg
Core
Laminate
Buildup
Fig. 9.1 Organic substrate with 2 + 4 + 2 layer stackup
2.
Ceramic Substrate
Ceramic substrates generally include HTCC, LTCC, Aluminum Nitride and other substrates, because the ceramic substrates are made by punching holes in each layer of the substrates, then metallizing the holes, making metal graphics by printing, then pressing the substrates together for co-fired, and finally forming the ceramic substrates. Since each layer of the substrate will be perforated individually, the layer stackup settings of the ceramic substrates are more flexible. Instead of the m + N + m type layer stackup in organic substrates, the vias need only be set to connect adjacent layers, and these vias can be freely combined to form holes through different layers, such as (1 → 4) holes can be combined through (1 → 2) + (2 → 3) + (3 → 4), and so on. Figure 9.2 is a Layer Stackup of a ceramic substrate. 3.
Silicon Substrate
With the rapid development of advanced packaging technology, the silicon substrate technology has also been widely used. In 2.5D integration, the silicon substrate is used as interposer, which becomes the bridge between the package substrate and bare chip, and also completes the high-density interconnection between bare chips in SiP. 1 3 5 7
Fig. 9.2 Ceramic substrate layer stackup
Metal Ceramic
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Fig. 9.3 Silicon substrate layer stackup
Structurally, the silicon substrate is a bit like an organic substrate, and the TSV in the middle layer needs to be etched on the silicon material, then the RDL layer on the top of silicon substrate and the RDL layer on the bottom can be fabricated using a technique like buildup. Generally, the top side of the silicon substrate can be used as 3 layers of RDL, and the bottom side can be used as 2 layer of RDL to form a 2 + 2 + 1 Layer Stackup as shown in Fig. 9.3, also known as a 3 + 2 structure, that is, 3 layers of metal on the top of the silicon substrate, and 2 layers of metal on the bottom. In Xpedition design process, the Layer Stackup can be set during the layout design process, or a layout template can be defined in Central Library beforehand, and then be referenced in the design. The second method is usually used for more mature and commonly used Layer Stackup settings. Next, we will create layout templates for organic, ceramic and silicon substrates in central library.
9.1.2 Create SiP Layout Template 1.
Create Organic Substrate Template
Open the Central Library of design in Library Manager, such as SiP_lib2020.lmc file, select Tools → Layout Template Editor in the menu, and select the appropriate type. There are currently five types of templates supported by Xpedition, Drawing, Package Design, Panel, PCB Designs, and RigidFlex Design. Here we select Package Design. We can see that the system already has multiple Package Designs templates by default, as shown in Fig. 9.4. to create a new template, In layout template edit window, click the New button enter the name of the source design the template needs to reference in the pop-up window, and enter the name of the template in the Template name. After clicking the OK button, the source design is automatically copied into the New Template. Elements in the source design, including Layer Stackup, substrate shape, mounting holes, etc., are automatically inherited into the new template.
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Fig. 9.4 Launch layout template editor window
In addition, the designer can copy any existing template and edit from it. For example, copy Package Design 8 Layer Template, select the template, click the , and rename to HDI 2 + 4 + 2 Template, as shown in Copy Template button Fig. 9.5. to enter the template editing state. The Then click the Template Edit button Xpedition Layout window will automatically open and enter an empty layout design. Select Setup → Stackup Editor from the menu to enter the Layer Stackup Editor window. As shown in Fig. 9.6, we can see that there is already an existing Layer Fig. 9.5 Copy a template and rename it
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Fig. 9.6 Start Stackup Editor window
Stackup, which is inherited from the copied template. The Stackup setup is important in layout design, whether it is simulated in HyperLynx SI/PI or calculated in Constraint Manager for the impedance of trace. The settings in Stackup Editor of Xpedition can be inherited to Constraint Manager and HyperLynx SI/PI to ensure consistency of layouts, design rules, and simulation. In Stackup Editor, we can setup thickness and parameters of the dielectric and metal layers, and we can change the layer name to suit the design habit of ourselves. Stackup Editor contains six TABs, Basic, Dielectric, Metal, Z0 Planning, Manufacturing, and Customer View, which focus on setting different options. In Stackup Editor, to add a layer, first select one layer, then use right-click menu Insert Above or Insert Below, or use Copy and Paste command to duplicate the layers. If we need to decrease layers, we can use the Delete command, see Fig. 9.7. We can modify layer name, setup plane layer, define layer parameters, etc. in Stackup Editor. The layer Stackup after modification is shown in Fig. 9.8 below. For consistency of production and design, after setting layer stackup parameters, menu selection Edit → Copy Special → Manufacturing Documentation to copy the layer stackup information into production document format and paste to Word document, which is very convenient in preparing standardized production documents, as shown in Fig. 9.9. Next, the setting of via is required. At this point, if no via defined in central library, we need to define via first. Menu select Setup → Libraries → Padstack Editor, enter the padstack creation window. First, two drill hole with a diameter of 75um and 150um are created. Tolerance is set to 2. With the Generate name from property option checked, we can see that the holes are automatically named Rnd75 ± Tol2 and Rnd150 ± Tol2 by the system,
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Fig. 9.7 Add or delete layers in Stackup Editor
Fig. 9.8 Modify substrate parameters in Stackup Editor
and the corresponding Drill symbol is selected for the two holes in the Drill symbols list. Drill symbols represent the type of holes in Drill drawings that are output after the design has completed, which are used for inspection by drillers. There are four optional types of Drill symbols, as shown in Fig. 9.10, which are explained below. ➀ Automatically assign during output, Indicates that the drilling symbol is automatically specified by Xpedition software system when the drilling is output. ➁ None, indicating that no drilling symbol is set for the hole.
9 Layout Creation and Setup
259 Layer Stackup Design: PCB, Designer: SunyLi. StackupTool 10 um, Er = 3.3 28 um, Layer1, Z0 = 72 ohms, width = 100 um 40 um, Er = 3.7 28 um, Layer2, Z0 = 37.8 ohms, width = 100 um 40 um, Er = 3.7 28 um, Layer3_Plane 120 um, Er = 4.2 17 um, Layer4, Z0 = 78.6 ohms, width = 100 um
802 um
180 um, Er = 4.4 17 um, Layer5, Z0 = 78.6 ohms, width = 100 um 120 um, Er = 4.2 28 um, Layer6_Plane 40 um, Er = 3.7 28 um, Layer7, Z0 = 37.8 ohms, width = 100 um 40 um, Er = 3.7 28 um, Layer8, Z0 = 72 ohms, width = 100 um 10 um, Er = 3.3
Fig. 9.9 Copy layer stackup parameters to production documents
➂ Use character as drill symbol, indicating that we can choose from 26 letters, including upper and lower case letters, for a total of 52 optional symbols. ➃ Use drill symbol from list, indicating a selection from 25 Drill symbols on the right side of the window, and blue indicates that this drill symbol has been selected by other holes. To avoid confusion, choose different Drill symbols for different holes when select symbols. The Size of the drill symbol is usually set to the corresponding size of the hole. In this example, select Use drill symbol from list and select in the Drill symbols list, set the size of Drill symbol to 200, choose Drilled as the drilling type, select Round for the hole, and check the option for Plated to indicate that the hole needs to be metallized, as shown in Fig. 9.11. After the hole is created, switch to the Pads TAB to create a 175um and 250um round Pad. And check the Generate name from properties option, the Pad is automatically named Round 175 and Round 250 according to the properties, as shown in Fig. 9.12.
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Fig. 9.10 Four types of Drill symbol
Fig. 9.11 Create drill hole and specify corresponding drill symbol
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Fig. 9.12 Create pads and generate name from properties
Then switch to Padstacks TAB, create a Padstacks Via_175um of Via type, select Round175 in the Pad list, specify Mount side\internal\Opposite side to the Via_175um with the left arrow , and select Rnd75 ± Tol2 in the Hole list. Then create a Padstacks Via_250um of Via type, select Round 250 in the Pad list, specify the Mount side\Internal\Opposite side of Via_250um with the left arrow , and select Rnd150 ± Tol2 in the Hole list, as shown in Fig. 9.13. When the two Vias are created, select File → save, and exit the window. Menu select Setup → Setup Parameters and switch to Via Definitions TAB to define the vias as shown in Fig. 9.14. Among them, 1–2, 2–3 and 6–7, 7–8 select Via_175um, and the process type is Buildup. Layer 3–6 selects Via_250um and process type is Laminate. The Buildup and the laminate are two different processes for substrate fabrication. Due to the size of this chapter, they are not described here detailed and can be referred to the relevant materials. When the setup is complete, click the OK button to exit the Setup Parameters window. on Xpedition toolbar to enter Draw Mode. Click the Draw Mode button Then select View → Toolbars → Dimension from the menu to open Draw Toolbar and create dimension for the substrate. First, click the first
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Fig. 9.13 Create Via_250um Padstack
Dimension Parameters button and the Dimension Parameters window will pop up, as shown in Fig. 9.15, here we can set various parameters for the dimension. Change Text Height to 1000, Pen Width to 200, the set the Units of dimension to mm, and click the OK button. Then create dimension for the substrate, click the Place Dimension Along a Linear Element button , select the position of the border we want to label, click the left mouse button, the labels will be automatically placed outside the boxes, and the dimension labels will be placed on the Assembly Top layer by default. If we need to place it in another layer, such as a user-defined layer, we can define the Layer in advance in Dimension Parameters window. When the labeling is finished, if we change the size of the border, we can see that the dimension label automatically updates with the change of the border size. In this example, the board Outline size of the template is 30 mm × 30 mm, and on this basis, the Route border is reduced by 0.5 mm (500 um) inward. The size of the Route border can be set as follows: ➀ Hold down the key and double-click the left mouse button on the Board Outline, a Draw Object type border is copied. ➁ Change the Draw Object to Route border and type −500 in the Grow/Shrink column and press . ➂View the dimension properties of Route border and check the Route border in layout has been updated. This method is very effective for complex substrate shapes.
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Fig. 9.14 Setup vias of 2 + 4 + 2 layer stackup
Fig. 9.15 Dimension Parameters setting window
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Fig. 9.16 Three key elements of layout template
The template is now created. The three key elements of the layout template are: ➀ Layer Stackup and parameter definition. ➁ Via Definition. ➂ Substrate shape and dimensions. As shown in Fig. 9.16. Click File → Save and exit the template editing environment. 2.
Create Ceramic Substrate Template
The ceramic substrate layout template creation method of is similar to that of organic substrate. First, copy the existing templates, then rename the template, and then edit the template in Xpedition environment, including layer stackup and parameters setting, via definition, and border and dimension creation. Here, we copy the existing LTCC Design 8 Layer Template, then change the name to enter the layout editing to HTCC 8 Layer Template, see Fig. 9.17. Then click environment. The ceramic substrate layer stackup and parameters setting is shown in Fig. 9.18 below, where the dielectric thickness is 100 um, the metal thickness is 18 um, and the dielectric parameter Er is 9.3. The vias of ceramic substrate setting is shown in Fig. 9.19. Since the vias in ceramic substrate are filled holes, there are no special requirements for the via ring width. We can set the via hole to 75 um and the via pad to 100 um and name it Via_100. In the actual project, the relevant process parameters need to be confirmed with the process personnel. After vias setting, switch to via clearances TAB, in which mainly sets the spacing rules of same net via-via between different layers. In the Same Net definition column below, set distance = 0, type = P (pitch), so that the same net vias of different layers can be overlapped during routing, thus the same net vias of different layers can be combined freely to cross the layers. See Fig. 9.20. Finally, the HTCC board outline and route border are drawn and dimensioned, and the layout template of HTCC ceramic substrate creation is finished. It can be called
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Fig. 9.17 Copy the existing template and rename it to HTCC 8 Layer template
Fig. 9.18 Layer stackup of HTCC ceramic substrate
directly when designing a HTCC substrate, and on this basis, adjust the parameters according to the project requirements. 3.
Create Silicon Substrate Template
The layout template creation method of silicon substrate is similar to that of the previous two substrates. First, find a similar existing template, copy and modify the name, and then enter the editing environment to modify layer stackup and parameters, set vias and draw board outline and route border.
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Fig. 9.19 Setup Vias of HTCC ceramic substrate
Fig. 9.20 Setup the same net via-via distance of different layers
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Here, we choose to copy the existing HDI 2 + 4 + 2 template and change the to enter the editing name to Si_ Interposer 2 + 2 + 1 template, and then click environment. See Fig. 9.21. Set the stackup and parameters of silicon substrate as shown in Fig. 9.22, in which the thickness of silicon is 100um, the Er of silicon is 11.5, the thickness of dielectric is 10 um, the Er of dielectric is 3.6, and the metal layer thickness is 5 um. The via setting of silicon substrate as shown in Fig. 9.23. The via hole of TSV can be set to 15 um and the via pad to 20 um, and it can be named TSV_15 um. The via hole of RDL layer is 10 um and the via pad is 15 um, and it is named RDL_Via
Fig. 9.21 Copy an existing template and rename to Si_Interposer 2 + 2 + 1 template
Fig. 9.22 Layer stackup and parameters setting of silicon substrate
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Fig. 9.23 Setup vias of silicon substrate
10 um. In the actual project, the relevant process parameters need to be confirmed with the process personnel. Then, draw the board outline and route border of the silicon substrate, the layout template of silicon substrate creation is finished. It can be called directly when designing the silicon substrate, and on this basis, adjust the corresponding parameters according to the needs of the project.
9.2 Create Layout Project 9.2.1 Create New SiP Project Create a new project in Xpedition Designer, menu select file → new → project, select Xpedition → default in project templates, set the name and path of the project, and select the corresponding central library. In this example, select the Central Library SiP_lib2020.lmc, in which we have created the layout templates earlier, as shown in Fig. 9.24. Then create a new schematic and draw, verify and package it. After packaging, on the toolbar, select package in design technology bar, select click Xpedition HDI 2 + 4 + 2 Template in Template bar, and set the layout path as.. \SiP, as shown in Fig. 9.25.
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Fig. 9.24 Create a new project and select the central library
Fig. 9.25 Template and Design directory setting
After setting, click OK to enter the layout design environment Xpedition.
9.2.2 Enter Layout Design Environment After entering Xpedition, Click Yes in the prompt box to open the project integration window. The system will prompt: forward annotation required. Click the
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Fig. 9.26 Forward Annotation prompt and operation
orange button in front of forward annotation (orange indicates that there is an update required), as shown in Fig. 9.26. A new window pop up to prompt that system synchronization is in progress, which includes package, database load, net load and so on. After synchronization, a message window will prompt that the forward annotation is successful, the schematic and layout databases will be synchronized, and all the status indicators will turn green. If there are problems in forward annotation, it will prompt warning or error, and write the specific information to the corresponding text file. Click the file viewer in the toolbar and open the forwardannotation.txt file in the list to check button the detailed report of warnings or errors, then make corresponding modifications to the problems, and then repackage the design until the problems no longer occur. Some warnings can be ignored if no critical impact on the design process. Enter Xpedition design interface, as shown in Fig. 9.27. We can check the three elements of the layout template: ➀ layer stackup and parameters definition ➁ via
Fig. 9.27 Xpedition design interface
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definition ➂ the shape and size of the substrate, all of which have been inherited into the design.
9.3 Layout Settings and Operations 9.3.1 Layout License Control First, let’s learn about License control for Xpedition. When entering the Xpedition Layout design environment, we will see the License control options as shown in Fig. 9.28, which can be selected by the designer and explained one by one below. ➀ ➁
➂
➃
Xpedition Layout 101, Basic PCB Design Tool. Support basic PCB design, 3D PCB design, 3D library, Electronic-Mechnical collaborative design, schematic browser, sketch routing, back drill and etc. functions. Xpedition Layout 151, High Speed Automatic PCB Design Module. On the basis of Xpedition Layout101, functions such as auto route, blind and buried via auto route, high-speed PCB design (differential, serpentine, delay), parameterized via, automatic test point, etc. were added. Xpedition Layout 201, Advanced Concurrent PCB Design Module. On the basis of Xpedition Layout151, the following functions have been added: multiperson real-time Concurrent design, topology planning and routing, automatic net optimization (exchange pins or devices). Xpedition Layout 301, SiP and Advanced Packaging Design Module. On the basis of Xpedition Layout201, the following design functions have been added: (1) Bond wire, chip stack, cavity, power ring, etc. (2) Embedded resistors and capacitors in substrate. (3) RF circuit design, RF simulation tool link. (4) Production data checking and editing tools, panel design. (5) Variant management tool. (6) Rigid-flex design function.
Fig. 9.28 Xpedition License control options
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In addition, Xpedition Advanced Technologies, Xpedition Fablink, and Xpedition RF are three options. When Layout 301 is selected, these three functions are included by default. If Layout 201, 151, 101 are selected, designers can select the options according to design needs. It should be noted here that Multi-Person Real-Time concurrent Design is a technology that has been developed for many years and is now open to customers. As long as customers have a license above Xpedition Layout201, they will have the concurrent Design function without the need to configure specific license. This has greatly improved than before, bringing convenience and benefits to customers. It is also conducive to the promotion of multi-person real-time concurrent design technology in layout.
9.3.2 Mouse Operation Methods First, let’s learn how to operate the mouse in Xpedition, as shown in Fig. 9.29. • Selection: The left button is used to select objects. • Zoom: The middle wheel is used to zoom and pan the picture. Roll up the wheel to zoom in. Roll down to zoom out.
Fig. 9.29 Functions of mouse in Xpedition
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• Pan: Press the middle wheel, move the mouse to pan the picture. • Stroke: Right-click is used as Stroke by default. If the mouse slides while pressing the right button, the Stroke function starts. • Right-click menu: Right-click is also used as right-button menu. If we press the right button and hold the mouse still, the right-button menu pops up. Stroke is a fast way to operate mouse commands. Press the right mouse button and move it. The stroke path is based on a 3 × 3 matrix. Creating a sliding path of the right mouse button in the matrix generates a sequence of numbers corresponding to an operation command in the system. For example, by pressing the right button, starting at the upper left corner of the matrix, sliding the mouse diagonally to the bottom right corner ends, a 159 sequence is generated that calls the command View Area. Starting at the lower right corner of the matrix, slide the mouse diagonally to the upper left corner ends, generating a 951 sequence that calls the command View All, which is shown in Fig. 9.30. The Stroke command can also be implemented with the middle mouse button. Menu select View → Mouse Mapping → Middle Button Strokes to change the Stroke from the right mouse button to the middle mouse button, as shown in Fig. 9.31. After switching to the middle button Stroke, press the middle wheel to perform the Stroke operation. At this point, the function of the right button and the middle button are exchanged and the right button become the picture pan. Table 9.1 is a description of commonly used Stroke commands. It can be seen that the Stroke commands supported by Xpedition are very rich, and mastery of Stroke commands can effectively improve design efficiency.
9.3.3 Four Common Operating Modes There are four common operating modes in Xpedition, corresponding to four tool : Select Mode, Place Mode, Route Mode, and Draw Mode, which icons represent different functions. to enter the select mode. This mode is the Select mode, click the button most flexible and can be used to select devices, select trace, select drawing, and operate accordingly. Because many objects can be selected, misoperation may occur sometimes. Place Mode, click the button to enter Place Mode. This mode is mainly used for place device operation. Only devices can be selected, the operation include: place, move, switch layer, align and lock of components. to enter the Route Mode. This mode can only Route Mode, click the button select route related elements such as traces, pins, and netlines. Mainly used for route operation, such as manual route, semi-automatic route, auto route, and can also be used to adjust the net lines.
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(a) 159 view area
(b) 951 view all Fig. 9.30 Right-click stroke operation
Fig. 9.31 Switch right button strokes to middle button strokes
9 Layout Creation and Setup Table 9.1 Stroke functions and corresponding operands
275 Stroke
Functional description
Corresponding operand
Display help on strokes
78,952
Undo command
7,412,369
Report selected objects
1,474,123
View area
159
View all
951
Zoom in
357
Zoom out
753
Delete
74,123,698
Copy
3,214,789
Turn on/off net lines
321,478,965
Tentative snap
729
Static snap
927
Route mode
123
ALT key +
Place mode
321
ALT key +
Draw mode
147
Route interactive
852
Route switch end
9,632,147
Display control
1478
Toggle display active layer only
96,541
Editor control
14,569
Auto-finish
258
Unselect all
1,478,963
ALT key +
(continued)
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Table 9.1 (continued)
Stroke
Functional description
Corresponding operand
Move
74,159
Rotate
3,698,741
OK
654
Cancel
456
Draw Mode, click the button to enter Draw Mode. This mode is mainly used to draw graphics, such as board outline, route border, plane shape, and add text, labels and etc. Select the related object according to the operation mode. Select components under Place Mode. Select traces, pins, and netlines In Route Mode. Select draw object under Draw Mode. Even Select Mode supports all types of elements selection, but it has more stringent requirements for the location of the mouse, so we suggest to use other 3 dedicated mode for easy selection. 1.
Select Parts
Select Parts usually takes place in Place Mode. When a component is selected, the color of the component outline is highlighted, which can be used to determine whether the component is selected or not. In Display Control Object TAB, check Place → Place Outlines → Fill on Hover & Selection option, when the mouse moves over the component (Hover) or the component is selected, the component outline will be filled, as shown in Fig. 9.32. ➀
Single Select, the left mouse button clicks any part of the placement outline to select a component. Previously selected components will no longer be selected.
(a) Unselection
(b) Hover
Fig. 9.32 Display effect of three states of components
(c) Selection
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Fig. 9.33 Use find command to find and select components
➁ ➂ ➃ ➄
2.
Press the key to select more components. The key can be used to select consecutive components or deselect one of them. To cancel all selected components, simply click on any blank area with the left mouse button. Group Select, if we want to select a set of components, we can use mouse to draw a box to select, all of the components inside the box will be selected. Select All, in Place Mode, use the menu Edit → Select All to select all the components. Edit → Add to Select Set: Contains options for selecting fixed, non-fixed, and locked components. Edit → Find, in Place Mode, use + key to find components and select, highlight, or fit view when the components are found, as shown in Fig. 9.33. Select Net
Select Net needs to be done in Route Mode. When the net is selected, the color of the net will be shown as a highlighted stripe, which can be used to determine whether the net is selected, as shown in Fig. 9.34. In Route Mode, we can select multiple net lines, pins, or traces at the same time. When selected, some commands are available, such as Fan Out, route, Reroute, Gloss, Length Adjustment and etc. ➀ ➁ ➂
Single Select: A pin can be selected by clicking it with the mouse, and all the net lines connected to the pin will be selected at the same time. Click on a net line to select it. Click on a trace to select the straight segment of the trace. Double Select: Double-click a trace with the mouse to select all trace segments between two pin pairs. Triple Select: Quickly click a pin, trace or netline three times with the mouse to select all pins, traces and netlines of the net.
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Fig. 9.34 Select net or trace
➃
➄ ➅ ➆
3.
Group Select: To select a group of related net objects, we can use the left mouse button to draw a box. The netlines, pins and trace segments that are all or partially inside the box can be selected. The previously selected object is no longer selected if it is outside the box. To select more objects while keeping the currently selected ones, press the < Ctrl > key and then use the mouse to select. Select All: in Route Mode, menu select Edit → Select All to select all traces, pins, and net lines. In the menu of Edit → Add to Select Set, there are commands that allow engineers to select fixed, non-fixed traces and vias, as well as other special objects. Edit → Find command: The + key combination can be used In Route Mode to find a net and select, highlight, or fit view when the net is found, as shown in Fig. 9.35. Select Draw Objects
In Draw Mode, we can select multiple objects of drawing types at the same time. The selected objects can be modified or deleted. Warning: it is important for designers to note that Draw Mode can select trace and perform deletion, so when editing or deleting in Draw Mode, we should take care not to misedit or delete traces. Like in Route Mode, elements selected in Draw Mode are also shown in highlighted stripes that cover the original color of the object, making it easier for users to identify the selected object. In General Options under Place TAB of Edit Control, if Allow Cell Graphics Edits is checked, the outline of component cell can be edited in Draw Mode.
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Fig. 9.35 Use find command to find and select net in route mode
Figure 9.36 shows select and edit plane shape and component outline in Draw Mode. In Draw Mode, there are as many as 32 types of graphics that can be drawn, as shown in Fig. 9.37. The number of graphics that can be drawn varies depending on the License supports. After a graphic is drawn, its type can also be changed, but not all types can be changed from one to another. ➀ ➁
Single Select, click a drawing object to select it. To select more drawing objects, press the key and click each object we want to select. Group Select, to select a group of drawing objects, use the left mouse button to draw a box to select them.
Additionally, adding text to the substrate such as Chinese and English identifiers, annotations and so on, also works in the Draw Mode.
Fig. 9.36 Select and edit plane shape and component outline in draw mode
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Fig. 9.37 Multiple graphics can be drawn in Draw Mode
9.3.4 Display Control Display Control, mainly used to control the graphical display. At the same time, Display Control also has some other unique functions, such as switching layer when routing. During routing process, we can open the Display Control and place it next to the work area. Display Control contains five TABs: Edit, Objects, Graphic, Fab, and 3D. There are 29 + display classes and hundreds of sub display classes, as shown in Fig. 9.38. 1.
Edit TAB
There are three tags under Edit TAB: Favorites, Layer Display and Global View & Interactive Selection, which can be expanded or collapsed by clicking Symbol at the top of the window. (1)
(2)
By default, there is no content under the Favorites tag, on any other items of display control, we can use right-clicking menu Add to Favorites to add preferred display items here. Layer display tag, used to display physical routing layers, each layer has Traces, Pads, Planes options, and can set colors and patterns individually. There are
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Fig. 9.38 5 TABs of display control
(3)
two options at the top: ➀ List only Route Enabled layers, ➁ Display Active Routing Layer Only. The global view & interactive selection tag contains seven sub-options for displaying related content such as Route/Multi Planning, Place, Route, RF, Wire bond, Board, Draw, and under each of the options there are many more. It is important for the reader to note that this tap shares some of the same options as the layer display tag and will not be displayed on the layout if either side is not selected.
There is a small button on the layer display and global view and Interactive Selection tags that can be clicked to quickly set all or unset all, and save the display options for restore. Please see Fig. 9.39. 2.
Objects TAB
There are 10 tags under Objects TAB: Route/Multi Planning, Place, Vias, Pins, Netlines, Planes, Route Obstructs, Route Areas, RF Objects and Wire bond Objects.
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Fig. 9.39 Quick set button
We can expand or collapse them by clicking on the symbol at the top of the window. Here, we will find some items in Objects TAB are duplicating with Global View & Interactive Selection in Edit TAB, which is true, but the software will automatically synchronize the selection of each TAB. The options below the Objects TAB are more detailed. We can understand as: previous is overview option, here is the detailed option, and here also can set the color. (1) (2)
(3) (4)
Route/multi planning tag is used for displaying route planning, multi-person concurrent design planning and etc. Place tag is used to display items related to the layout, with Top on the left and Bottom on the right. Part items are also shown here, such as pin net names on or off (Fig. 9.40). Vias tag, used to display via related items, including Via Span Number and Via Net Names and etc. Pins tag, used to display pin related items, please note that the option to display pin name and net name is not here but in the Place tag above, we can understand that only metal pins are displayed here
Fig. 9.40 Turn on/off pin net names display
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Fig. 9.41 8-Layer chip stack display items
(5) (6) (7) (8) (9) (10)
3.
Netlines tag, which are used to display contents related to the netlines, netline options are used more for component placement and net optimization. Planes tag, used to display contents related to plane data and plane shapes. Route Obstructs tag, which displays content related to route obstructs. Route Areas tag, route area display options, wiring border, Fence and rule areas are all displayed here. RF Objects tag, RF elements display options, such as RF Nodes, Shapes are displayed here. Wire bond Objects tag: display Include Die Pins, Bond Wires, wirebond Guides. Depending on the number of stacked layers, the contents are different. As shown in Fig. 9.41, the display of 8-layer stacked chips can be turned on and off individually, and the color can be assigned to different layers independently. Graphic TAB
There are five tags in Graphic TAB: Graphics Options, Grids, Color By Group, Color by Net or Class, Object Appearance, which can be expanded or collapsed by clicking at the top of the window. on the symbol (1)
Graphics Options tags: used to control graphics display modes, such as highlight, Dim mode, pattern, full screen cursor, background color, net name on traces, mirror view, tuning meter and etc. are displayed here. Figure 9.42 shows the color display of the Dim Mode slider at different positions, making it easy to check the overall structure of the net routing and information about the surrounding elements.
(2) (3)
Grids tag: which control the display of different types of grid. Color by Group tag: select and display the color of group.
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Fig. 9.42 Display effects under different dim modes
(4)
(5) 4.
Color by Net or Class tag: selects and displays the colors of nets and classes, we can set different color for key nets. Here layout will inherits the colors set in is checked. Constraint Manager if the option Object Appearance tag: used to set pattern for traces, pads and plane data. Fab TAB
There are five tags in Fab TAB: Board Objects, Fabrication Objects, Materials, Drill Drawing and User Draft Layers, which can be expanded or collapsed by clicking on at the top of the window. the symbol (1) (2)
(3) (4) (5) 5.
Board objects tag: used to display Board related items, including fiducials, mounting holes, board outline, cavity, origin, and etc. Fabrication objects tag: used to display production related items, including solder mask, solder paste, assembly items, silkscreen items, cell origins, and etc. Materials tag: used to display materials related items, mainly for embedded resistive materials, capacitive materials and conductive materials. Drill drawing tag: used to display drill drawing and drill chart. User draft layers tag: all user-defined layers are displayed here, including DXF, Gerber, and other layers imported from outside software. 3D TAB
The 3D TAB mainly used to display elements of the 3D view. It contains six tags: options, objects, assemblies, components, mechanicals, PCBs, which can be . Figure 9.43 shows the 3D expanded or collapsed by clicking on the symbol view environment. (1) (2) (3)
Options tag, 3D display effect control, including force opaque, perspective, display internal layers, scale factor, discard tiny objects, etc. Objects tag, display of 3D elements, including substrate, bond wires, embedded materials, trace, via pads, holes, planes, netlines, etc. Assemblies tag, display of 3D assembly elements, include 3D elements imported from outside.
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Fig. 9.43 3D view environment in Xpedition
(4) (5) (6) 6.
Components tag, display of 3D components, Appearance control on the left and visibility control on the right. Mechanicals tag, display of 3D mechanical elements, Appearance control on the left and visibility control on the right. PCBs tag, display of 3D PCB elements. Three Important Tips
The settings of display control are described above. There are more than 29 + tags and hundreds of small items. It is difficult to remember the specific display location at first. If we look for them one by one, it will seriously affect the design efficiency. Fortunately, there is a convenient way, which is the first important tip mentioned below. (1)
When the mouse clicks on Display Control window and then taps the keyboard, an input box automatically appears at the top of the Display Control window. The designer only needs to enter some keywords of the items to be found. For example, enter Meter in the window, press Enter key, the software will searches for Tuning Meter, tick the item, we can display the Tuning Meter when adjusting the length of serpentine trace (Fig. 9.44).
(2)
Dynamic changes in menus are also a feature of the new version of Xpedition. Previous tools, if some functions are unavailable, appear gray. In new Xpedition, unavailable functions are automatically hidden and do not appear in menus. If License is enabled, available functions will automatically appear in menus. For example, the 29 + item we described earlier is named because there are more items actually. For example, with Rigid-Flex license enable, the
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Fig. 9.44 Find display items by keyword search
(3)
menu will contain the content of Rigid-Flex design, and our previous description has no relevant content, so it is not displayed. The advantage of menu dynamic change is that menus are always in concise state. We can save commonly used display schemes for subsequent calls easily, click the Save button at the bottom of the display control, and a save dialog box appears. We can save files locally with design, with software system files or user-specified location. After saving, we can directly call the saved display scheme in the list, which is very convenient and fast (Fig. 9.45).
Display control introduction is now finished and requires designers to become familiar with it in order to improve design efficiency.
Fig. 9.45 Save the display scheme and call it in the list
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9.3.5 Editor Control The Editor Control toolbar is divided into Common Settings and three TABs, Place TAB, Route TAB, and Grids TAB. Each is described below. Figure 9.46 is a screenshot of the common settings and place TAB, route TAB, grids TAB in edit control window. 1.
Common Settings
When editor controls switch between several TABs, the Common Settings at the bottom of the window remain unchanged. Common settings include toggle for interactive DRC and the auto save interval setting. (1)
Interacitve DRC setting
By default, interacitve DRC is always on, that is, the tick option in front of Interactive Place/Route DRC is always selected to ensure that no DRC errors occur in layout design. If we need to turn off Interacitve DRC during the design process, uncheck the box in front of Interactive Place/Route DRC. At this time, the system pops up a prompt window, indicating interactive DRC will be turn off. After clicking the Yes button to confirm, the system automatically pops up the DRC close warning window, indicating DRC off at this time, as shown in Fig. 9.47. When DRC is off, designers can operate violating DRC rules, such as overlapping the pad of two devices, which is often used in some RF circuit designs. The designer needs to be reminded that after completing these DRC violation operations, don’t forget to reopen the DRC, just close the DRC prompt window. The system will automatically pop up a window, prompting that the DRC will be opened, and recommending that the designer run the Batch DRC. Typically, click the No button, because Batch DRC checks are done uniformly when the design is complete. (2)
Settings for Autosave Interval
The value input in Interactive bar is the time interval that system autosave when interactive route takes place. The default value is 60 min. The value input in Auto
Fig. 9.46 Place, route, grids TAB in edit control window
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Fig. 9.47 The system prompts DRC off
Route bar is the time interval that system autosave when auto route takes place. The default value is also 60 min. Designers can adjust the time interval for autosave according to the design situation. Next, let’s describe Place TAB, Route TAB, and Grids TAB. Before describing each TAB, let’s learn how it works. See Fig. 9.48. Click the plus sign with the left mouse button to expand all options, and click the minus sign to collapse all options. Click the arrow at the left end of each option to expand or collapse the options individually. When the option is collapsed, the arrow turns to the right, and when the option is expand, the arrow turns down. The up and down arrows on the right side are mainly used to adjust the relative position between options. The up arrows move the options up. Designers can move the commonly used options up for easy selection. 2.
Place TAB
Place TAB mainly contains two tags, general options and jumper. (1)
General Options
The main settings are layout-related settings, such as Online 2D Placement DRC rules when laying out. If set to Warning, the system will shoe warning message with component conflicts in layout. If set to Preventative, component conflicts are
Fig. 9.48 Edit control window action diagram
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Fig. 9.49 Bond wire DRC options and allow cell text and graphics edits options
prohibited. If the Shove Parts option is ticked, the auto push will occur when the components conflict. According to the actual design situation to select the options. For example, if we need to place parts across the substrate outline, choose Warning so that the system allows the part placement with warnings. If set to Preventative, parts can never be placed because of conflicts with outline, which are prohibited by the system settings. The Online 3D Placement DRC rule works similarly. It is important to note that the general Bond Wire DRC rule is set to 3D DRC and allows the same net bond finger overlap. In addition, if we need to edit cell outline and text, we need to check Allow Cell Text Edits and Allow Cell Graphics Edits, which are not checked by default (Fig. 9.49). Other options, such as the display mode of the netline when moving parts, part alignment, the text rotations, and the cell rotations, are not detailed here. (2)
Jumpers
The main purpose is to set up rules about jumpers, which are not explained in detail here. Engineer can refer to Siemens EDA relevant materials. 3.
Route TAB
Route TAB contains six tags: Dialogs, Plow, Edit & Route Controls, Angel, Corners, Via & Fanouts, and Net Rules On/Off. The specific position of each tag can be switched by the up and down arrows on the right. Designers can place the most commonly used options at the top of the window for easy selection. (1) ➀ ➁ ➂ ➃
Dialogs Tag Layer Settings sub-option: Mainly used to set which layers are allowed to route, the default route direction of each layer, and the setting of layer pairs (that is, layers that switch automatically when vias are placed during routing). Tuning sub-option: Mainly used to set tuning rules, including tuning pattern, diff pair balancing, tuning iterations and autotune options. Diff Pairs sub-option: Mainly used to set the adjacent and same layer pairs of diff pairs, and min length to maintain paring. Pad Entry sub-option: Mainly used to set the prefer pad entry orientation and whether allow via under pad. In SiP or Package design, it is often necessary to place via under pad. For example, in a 6-layer SiP substrate design, if we
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Fig. 9.50 Allow via under pad options
➄ (2)
need to place via under a rectangular package pin Pad, select Pad Rectangle 2 × 0.35, then check Allow Via Under Pad, and check Layer Range 5–6, as shown in Fig. 9.50, indicating that vias are allowed under the pad and vias pass from layer 5 to layer 6. Allow off pad origin, indicating that the vias can deviate from the center of the Pad, Align on long axis, vias need to align on long axis of the pad. Expand trace is used to set trace expansion, which can be adjusted automatically depending on the routing area. Plow Tag
Plow Tag is mainly used for routing control. There are four Route Modes in Xpedition currently: Real Trace/Delayed, Real Trace/Dynamic, Hockey Stick/On Click, Segment/On Click. Two mouse operation styles: Mouse up style and Mouse drag style. Mouse up style refers to move the mouse when the left mouse button is not pressed, which supports the above four Route Modes. Mouse drag style refers to move the mouse when the left mouse button is pressed, which supports the first two Route Modes. There are six Route Modes combined, as shown in Fig. 9.51. In addition, Prohibit violations and Double Click to add vias in the Plow tag are typically ticked.
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Fig. 9.51 Mouse up/drag style and Route mode selection
(3)
Edit & Route Controls Tag
This tag is mainly used to set the Gloss mode and the push & shove operation during routing, as shown in Fig. 9.52. ➀
Gloss mode
Gloss mode, including gloss on, gloss local and gloss off, can switch through key Toggle Gloss during routing process. Via move, Pad jump means that during gloss operation, vias are allowed to be moved and traces are allowed to jump the pad. Remove excess meanders indicate that additional windings are removed during gloss operation. Gloss around deleted routes indicate automatically gloss the surrounding traces when trace or via are deleted. ➁
Push & Shove
Trace shove, via shove and bond finger shove options control whether to push and shove these elements or not in routing process. Pad jump, via jump controls whether the traces are allowed to jump the pads or via during push and shove. (4)
Angel, Corners Tag
The options in this tag is mainly used to control the routing angle and corner, including arc routing, 45 degree routing, and we can set the curve radius and min radius, as shown in Fig. 9.53.
Fig. 9.52 Gloss mode and push & shove settings
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Fig. 9.53 Routing angle and corner options
(5)
Via & Fanouts Tag
The options in this tag mainly controls the rule settings for vias and fanouts during routing process, as shown in Fig. 9.54. ➀
➁ ➂ ➃ ➄
Auto trim through vias: Controls whether to automatically trim a through hole via as a blind via or a buried via, depending on the layer in which the trace is placed at both ends of the through via, provided that the design allows the use of blind vias and buried vias. Allow one additional via per SMD pin: set if multiple vias can be placed under one Pad, and some heat sink pads need multiple vias to be placed. Use place outlines as via obstructs: set if vias are allowed to be placed at the bottom of the component, it is usually allowed, so this option is not checked commonly. Enable fanout of single pin nets: Set whether to fan out a single pin net. If not selected, the single pin net will not fan out and route. Max pins per plane fanout via: Defines the maximum number of pins that share the same fan out via, if not defined, no restriction.
Fig. 9.54 Options in via and fanouts tag
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Fig. 9.55 Options in net rules on/off tag
➅
(6)
Max traced length on restricted layers: Defines the maximum trace length allowed in the restricted layers, including the external and internal layers definition. Net Rules On/Off Tag
Stub lengths: check the stub length rule. Layer restrictions: check the Layer restriction Rule. Via restrictions: check the via restriction Rule. *Max delays and lengths: check the maximum delay and length rule, * indicating that this option is also applicable for auto route (Fig. 9.55). 4.
Grid TAB
Grid TAB is mainly used for setting up grid, including part grids, route grids and other grids, as shown in Fig. 9.56.
Fig. 9.56 Part grids, route grid and other grids setting
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Part Grids Tag
Two kinds of part grids can be set, primary grid and secondary Grid, the number of pins can be set as a criteria to determine the part is suitable for primary grid and secondary Grid. In this way, large parts with large number of pins can quickly locate the positioning, while small parts with small number of pins, such as resistors, capacitors, and so on, can be moved in small grid to facilitate the layout around the large device. Offset is usually set to None. Criteria for parts using primary grid is used to determine which grid a device is suitable for, such as devices with pins greater than or equal to 14, use primary grid, and pins less than 14, use secondary grid. (2)
Rout Grids Tag
Route grid and Via grid can be set in this tag. Because Xpedition really supports no grid routers, we can set both Route Grid and Via Grid to be None, which makes it easier to push and shove in route process. If accurate positioning is required, such as BGA area routing, the appropriate grid can be setup so that the routing is positioned at the center of both Pads. Or in ceramic packaging design, we can set up a reasonable via grid for easy via alignment in the stacking of multilayer vias. (3)
Other Grids Tag
This tag main set the drawing, jumper, and test point grids (Fig. 9.56).
9.3.6 Smart Cursor Tips As software intelligence increases, Xpedition also adds many smart features, such as the menu dynamic changes according to the software capabilities enabled. In addition, when designer moves mouse in Xpedition Layout, the mouse cursor displays different icons to indicate the current state of operation, as shown in Fig. 9.57. There are five states and ten styles, which are explained separately below. ➀
, which is the most General state: The cursor is shown as a small cross common style of mouse cursor in Xpedition, usually indicating that the mouse is idle at this time.
General state
Move state
DRC On
DRC Off
Hover
Normal state
Route state
Fig. 9.57 Cursor display styles in different operating states
Edit state
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➄
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Move state: When the cursor is shown as a cross with four small arrows , it indicates that it is now moving. Press the left mouse button to move the selected element. Route state, in select mode or route mode, when the mouse cursor moves over an element that can be routed, such as a pad, there are two situations: (a) when dynamic highlight is checked, the pad is highlighted, and the cursor changes to a small cross with an outer frame , indicating that the route state is entered. At this time, press the left mouse button to route; (b) when dynamic highlight is not checked, the pad is not highlighted, and the cursor is a regular small cross. Press and drag the mouse to enter the route state as well, and the cursor becomes a small cross with an outer frame . In the case of DRC On, the small cross with outer frame is displayed normally, and in the case of DRC Off, the small cross with outer frame is displayed in red. In route mode, if no element selected, the cursor display hover style , At this point, as long as we select the element that can be route, the route starts and the cursor changes to . Normal state: In Draw Mode, the cursor is usually displayed as . In addition, at the setting window mouse is also displayed as this style. When the related element is selected, the cursor switches to another style and enters the corresponding state. Edit state: When the cursor changes to a two-way arrow, specifically including , indicating that it is in the edit state, generthe following four styles ally operating in this state, the shape of the graphic will change accordingly.
The above description of smart cursor tips in Xpedition Layout, familiar with smart cursor tips can avoid misoperation and improve productivity.
9.4 Layout Design Before the layout, the size of the substrate can be adjusted according to the specific conditions of the project, for example, the Board Outline expands from 30 mm × 30 mm to 31.5 mm × 31.5 mm, and move its Board origin position to (15,750 um, 15,750 um) at the center of the SiP substrate.
9.4.1 Component Placement On Xpedition toolbar, click the button to switch to Place Mode, menu select View , click the → Toolbars → Place, open the place toolbar: first button , the Component Explorer window pops up, as shown in Fig. 9.58. Component explorer is a management window for component placement, with navigators on the left, component list on the right, and a series of toolbars on the top.
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Fig. 9.58 Component explorer window
The left navigation bar lists the elements that can be placed, the entire layout at the top, such as SiP_Board in Fig. 9.58, followed by a list of Groups, such as CL1, CL2, CL3, CL4 in the figure. Groups need to be defined in a schematic or layout before they can be displayed. RF stands for RF related elements, Spares stand for devices that do not exist in the schematic but are not removed from layout, mechanical cells for mechanical elements, drawing cells for drawing elements, such as board frame, labels, and so on. On the right side of the part list, bold letters indicate that the part has not yet been placed in layout, and normal fonts are displayed when part placed in the layout, such as P1 in Fig. 9.58. In the top filter bar of the list, we can select keywords to filter the contents. For example, if we select U* above the first column, the window only display the list of parts that start with U. There are 11 icons in the toolbar, which correspond to different functions. Mouse over the icon will prompt the corresponding icon name. For example, the third icon prompt is: Place by schematic, designer can try to hover on each icon, which is not detailed here. 1.
Place by schematic
Xpedition has a variety of layout options. For more complex SiP designs, it is often necessary to guide the layout through schematic. Click Place by schematic icon in Component Explorer window, then select the part we want to place from schematic, the Cell of the selected part will automatically stick to the mouse when the mouse moves over the layout window. The designer just needs to find a suitable location to place the cell. See Fig. 9.59. In schematic, the color can be changed to monitor whether the parts are placed in layout real-timely. If a part is not placed in the layout, it appears light gray. If placed
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Fig. 9.59 Place part by schematic
in the layout, the normal color is displayed. The change of color is the instant when the part is placed on the layout, which is a real-time display. 2.
Place by Group
Xpedition uses an advanced hierarchical grouping layout. Designers can define functional modules by grouping them in schematic, place them by group in layout design, and then refine the layout within each group. The software calculates the layout space needed by the group based on the sum of the dimensions of the parts contained in the group, and then optimizes the layout within the group. Hierarchical grouping layout is a great innovation in layout design, which greatly improves the guiding role of schematic to layout. In schematic tool Designer, parts have attribute Clusters. Parts with the same Cluster attribute values are divided into one group. When data is transferred to the layout tool Xpedition, parts are automatically divided into groups according to the schematic, such as CL1, CL2, CL3, CL4 listed in the navigator of Fig. 9.60. In Xpedition, drag CL1, CL2, CL3, CL4 to layout environment with the mouse. We found that there were only four circles and no components. At the same time, the group icon of the left navigator of Component Explorer became a small circle, as shown in Fig. 9.60. Then select each circle and use right-click menu Arrange → Arrange One level. As shown in Fig. 9.61 below, the small circles in the navigator become to the device icon. Parts in each group are automatically placed inside group outline. Designers can adjust the relative position of the elements inside the group, or select the group outline to move the whole group. If the devices position in group do not need to adjust, we can use right-click Freeze command to freeze the group, then the relative position of the devices inside group cannot be moved, but the whole group can be moved. 3.
General Placement Method
There are some designs that do not have schematic (driven by netlists) or do not have groups defined in the design, we can use general placement method.
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Fig. 9.60 Drag CL1~CL4 groups to layout window
Fig. 9.61 Place intra-group devices with Arrange command
The general placement method is the easiest. Just select the part from the list of Component Explorer and drag it directly to layout environment. The Ref Des of the part placed in the layout changes to a thinner font. The unplaced part is shown in bold font, making it easy to distinguish whether it is placed or not, as shown in Fig. 9.62. We can also select a part in the list and use right-click menu Place, or select multiple parts in the list and use right-click menu Place Parts Sequentially to place (Fig. 9.63). Here, we explain the Auto Arrange Parts and Distribute functions. The former is to place the components tightly together, where the designer chooses to place them and adjusts them according to the design situation. The latter is to automatically spread out the components and place them outside the board outline, and then the designer chooses to drag them into the substrate one by one. Designers have flexible choices to use them based on their design.
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Fig. 9.62 Drag the part directly from the list to layout environment
Fig. 9.63 Use right-click menu for part placement
9.4.2 View Schematic in Layout Xpedition supports direct viewing schematic in layout environment and does not require additional schematic License. This way, layout designers can view schematic or they can interact layout with schematic without occupying the schematic license. To view schematic in layout environment, first check the Create Schematic View during Forward Annotation option in the Additional Options in Forward Annotation process, as shown in Fig. 9.64.
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Fig. 9.64 Check create schematic view during forward annotation
This operation transfers the schematic data to layout in forward annotation process, which allows designer to open and view schematic in layout. Similarly, if we want to view layout data eExp in schematic, we need to check the Create eExp View during Back Annotation option. After successfully back annotate, eExp can be viewed in schematic environment. When the Create Schematic View during Forward Annotation option is checked and the forward annotation is successful, menu select Window → Add Schematic View to open the schematic view window in layout and conduct interactive checks, as shown in Fig. 9.65.
Fig. 9.65 View schematic design in layout environment
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9.5 Package Pin Optimization In the design of SiP, package pin optimization is very important. The data interface of SiP to the outside world is accomplished by package pins. In addition to some fixed signal pin, the pins of package are usually defined by designer, which gives us a lot of flexibility. How to assign the most suitable pins to different nets is the first consideration in the design. After the completion of the parts placement, the pin definition of the package is optimized according to the actual connection relationship. The optimization principle is the shortest connection and the least crossover, generally by exchanging the package pin (IO of BGA), but the fixed pin of the predefined power or ground needs to be retained. Package pin optimization include automatic net optimization and manual switching pins, in practical design they are often combined. For the specific operation method of net optimization, please see the detailed description in Chap. 13. Only the effect diagram of the optimization is listed here. As shown in Fig. 9.66, it can be seen that the software automatically assigns the nearby BGA pins to nets, and reduces the net crossover as much as possible, thereby effectively ensuring the signal quality and reducing the workload of later routing. If we are not satisfied with the effect of automatic net optimization, we can exchange the BGA pins manually to achieve the optimal net connection. After the completion of package pin optimization, the changes of the pins definition can be back annotated to schematic.
Fig. 9.66 Automatic net optimization effect
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9.6 Layout Chinese Input 1.
Manual input of Chinese texts
In the previous chapter of schematic input, we have discribed the configuration and input of Chinese words in Designer, and how to input Chinese texts in Xpedition Layout is described below. First, menu select View→Toolbars→Draw Create to open , toolbar, then click the Add Text button to input the desired text directly in the String bar of the pop-up window. Text can be placed at any layer of the design and supports various fonts of Windows. Designers can define text height, pen width, angle, text origin, and whether to mirror text, as shown in Fig. 9.67. If we need to edit the input text, we should click the text with the mouse first, and then modify it in the property bar. 2.
Import Chinese Texts from DXF File
In addition to manually input Chinese texts, Xpedition also supports importing Chinese texts from external data files such as DXF. Menu selection File → Import → DXF, in the pop-up DXF Import window, select the files that need to be imported, and setup as Fig. 9.68. Then click the OK button, a prompt window pops up after the import, prompts that the import is error-free, and opens the corresponding User Draft Layer to see the imported DXF data. The imported DXF file contains both graphic and text formats, and its text characters remain editable, not in a single graphic format.
Fig. 9.67 Layout Chinese texts input
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Fig. 9.68 Import DXF file
Designers can convert graphic types, such as Board Outline or Cavity and etc., so elements such as substrate outline designed in mechanical software do not need to be redrawn in Xpedition. Designers can change or edit imported text characters. Click on the texts to see the text content has been placed in the string bar of the properties window. We can edit it in the String bar, as shown in Fig. 9.69.
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Fig. 9.69 Chinese texts imported in DXF files are editable
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Chapter 10
Management of Design Rules Suny Li
10.1 Constraint Manager Constraint Manager (CM), is an integrated environment for setup and management of design rules, it is accessible through the schematic tool Xpedition Designer or the layout tool Xpedition Layout, and maintaining data synchronization. New design rules in schematic are automatically updated to the layout when forward annotation is executed. When do design back annotation, the new design rules in layout will also be updated to schematic, thus enabling the two-way transfer and synchronization of the design rules. Figure 10.1 is design rules transfer flowchart. Constraint Manager can be started from both schematic and layout environments. , and click the icon to enter In the schematic or layout toolbar, find the tool icon the constraint manager easily. We can also choose Tools → Constraint Manager to launch the Constraint Manager from the Schematic menu or Setup → Constraint Manager to launch from the Layout menu. The interface of Constraint Manager is shown in Fig. 10.2. Constraint Manager is a spreadsheet-based working environment. The basic operation is similar to Excel. Engineer can easily define and edit various design rules in Constraint Manager. First, let’s look at some of the concepts in Constraint Manager. Constraint, it is a rule, requirement, or attribute. In design, it is usually assigned to related net or part to control the layout and route to meet or enhance design goals. Scheme, a collection of design rules, can be applied to entire design or to a specific area, such as a rule area. S. Li (B) Beijing, China e-mail: [email protected] © Publishing House of Electronics Industry 2022 S. Li (ed.), MicroSystem Based on SiP Technology, https://doi.org/10.1007/978-981-19-0083-9_10
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Xpedition Designer
Xpedition Layout Back Annotation
Back-end Database
Front-end Database
Constraint Manager Fig. 10.1 Design rules transfer flowchart
Fig. 10.2 Constraint manager interface
Net Class, a group of nets with the same Net Rules, usually with the same physical rules, such as trace width, via assignment, differential clearance, and whether or not route in specific layer. Constraint Class, a group of nets with the same Constraint Rules, usually with the same electrical rules, such as maximum/minimum delay, length matching, custom route topology, and so on. Clearance, which sets the physical spacing rules during layout design. For example, trace to trace, trace to via, trace to pad, trace to plane, pad to pad, pad to via, pad to plane, etc. Z-Axis Clearance, which sets rules between different layers for trace to trace, trace to pad, trace to via, trace to plane, etc.
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Part, which sets properties of a component, such as its type, value, model, power consumption, temperature limit, etc. Noise Rules, noise-related constraints, can effectively control crosstalk and noise in layout design, such as the setting of parallel route rules in crosstalk control. Constraint Template, which allows multiple constraint templates to be set in Constraint Manager so that nets with the same constraints can quickly reuse the same Design Rules. For example, when designing a net with the same topology definition, we can first create a constraint template, then quickly apply the constraint template to the related nets. Constraint Editor, which can be understood as a simplified version of Constraint Manager, can operate directly in Xpedition layout environment. Due to the size of the book, it is not described in detail. Readers can refer to Siemens EDA related materials.
10.2 Scheme A scheme is a collection of physical design rules that can be applied to an entire design or to a specific area, where physical design rules mainly include net class rules and clearance rules. There are two default schemes in Constraint Manager, Master and Minimum, and engineers can also create user-defined scheme. Master, a collection of physical rules applied to the entire design. Minimum, a non-editing scheme, is used only to display the minimum trace width or minimum clearance for all the schemes in the design so that engineers can easily check the smallest physical rules in the design. User-defined schemes in which the design rules differ from those defined in master scheme in certain areas of the design, such as BGA area. User-defined schemes automatically inherit all net class, clearance and layer definitions from Master scheme, but the net class and clearance rules can be set differently from the master scheme. Depending on the design needs, engineer can create multiple user-defined schemes.
10.2.1 Create Scheme Right-clicking menu on Schemes, selecting New Scheme, and renaming it according to its functional characteristics. As shown in Fig. 10.3. The newly created scheme automatically inherits the rule definition of master scheme. Engineers can modify the rule definitions in the new scheme and apply them to different areas depending on the design requirements, as shown in Fig. 10.4.
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Fig. 10.3 Create a new scheme
Rules in Master scheme
Rules in My_area scheme
Fig. 10.4 Modify rules in user-defined scheme
10.2.2 Apply Scheme in Layout Design After modifying the rules in the user-defined scheme, turn off Constraint Manager (data is automatically updated to Xpedition). Enter Xpedition design environment, draw a closed graph on the layout, define its type as Rule Area, and select the userdefined scheme name My_area to assign to this Rule Area. In the rule area, the rules in the user-defined scheme are valid, while in other areas, the rules defined by master scheme are valid. Rules in user-defined schemes are usually defined by the layout designer because the rules take effect only when drawing the rule area in layout and specifying the user-defined scheme, as shown in Fig. 10.5. It is important to note that the rule area should be defined before routing. If the rule area is defined after routing, we need to edit or move the trace so as to the rule area can take effect.
10 Management of Design Rules Rule Area
309 Scheme name
Draw Rule Area
Inside the rule area, the rules defined in this scheme are valid
Outside the rule area,the rules defined in master scheme are valid
Fig. 10.5 Apply user-defined scheme in rule area
10.3 Net Class 10.3.1 Create Net Class and Assign Nets to Net Class In the top-left corner of Constraint Manager Navigator, all existing Net Class names are shown. Right-click on an existing Net Class name and select Delete to delete it, or press the Delete key directly on keyboard. It is important to note that the engineer cannot delete the Default Net Class. Right-clicking menu on Net Classes, selecting New Net Class, and naming it according to its functional characteristics, such as High_Speed. As shown in Fig. 10.6. After the net class definition, we need to assign the corresponding net to net class, the nets assigned in this net class will follow the rules defined in this net class. Rightclick on the net class name, select Assign Nets, then select the nets we want to assign to add the selected nets to the in the pop-up window, click the right single arrow target net class, and if we click the double arrow the target net class, as shown in Fig. 10.7.
, all the nets will be added to
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Fig. 10.6 Create a new net class
Fig. 10.7 Assign nets to net class
10.3.2 Define Net Class Rules Once we have created a Net Class and assign related nets to it, we need to define net class rules that will apply to all nets assigned to this net class. As shown in Fig. 10.8, first set the Typical, Minimum, and Expansion trace width of the net class to 100 um, 80 um, and 200 um, respectively. In the Typical Impedance column, the software automatically calculates the typical impedance based on the Typical trace width, and also calculates the typical differential impedance when the differential Spacing is set. It can be seen that under the same trace width, due to the different distances from the plane layer, the single-end impedance and differential impedance of each layer are different. The closer to the plane layer, the smaller the impedance is.
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Fig. 10.8 Define net class rules
Fig. 10.9 Interval distribution of signal and plane layers controls impedance consistency
So if we want to maintain the same impedance in different layers, we should set different trace widths in different layers. Alternatively, we can use the method of setting the interval distribution between plane layers and signal layers so that each signal layer has a neighboring plane layer as the reference plane. As shown in Fig. 10.9, the interval distribution of signal layers and plane layers provides impedance control, improves signal integrity, and suppresses crosstalk. However, this setting increases the number of substrate layers and needs to consider the cost. The Via Assignment column is used to define the Net Class Via. Click the button before Default. In the Net Class Via column of the pop-up window, click the dropdown arrow to select the desired via, as shown in Fig. 10.10. Before the Net Class Via assign, system use Default Via which is defined in Via Definition TAB of Setup Parameters dialog box in Xpedition environment, please see the previous Chap. 9. Referring to Fig. 10.8, the check box in the Route column indicates whether route is allowed in this layer. Normally, if no route is allowed on plane layer, don’t check the option in Route column, as shown in Fig. 10.8, if route is required on plane layer, check this option, as shown in Fig. 10.9. The Differential Spacing column defines the spacing of two differential pair trace, which, together with other factors, affects the differential impedance.
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Fig. 10.10 Assign via for net class
10.4 Clearance 10.4.1 Create and Setup Clearance Rules In the list of Constraint Manager Navigator, below the net classes is clearance. Like Net Classes, right-click Clearances and select New Clearance Rule in the pop-up menu to create a new Clearance rule, as shown in Fig. 10.11. The items that can be set in the clearance rules are very comprehensive, including Trace to Trace, Trace to Pad, Trace to Via, and Pad to Pad, Pad to Via, Pad to Plane, and so on, and can be set individually for each layer, as shown in Fig. 10.12. In clearance rules setting, column adjustments are often required because there are so many columns. The width of each Column in Constraint Manager can be adjusted by engineer. Select the edge of the Column and drag it to left or right. When dragging to the left makes the Column to have a zero width, the Column is automatically hidden. Engineer can also use this method to hide columns that are not frequently viewed or set, as shown in Fig. 10.13. The same method can be used to adjust the height of the Row and hide the Row. If the engineer needs to re-view the hidden Column, this can be done through View → Reset Colum Widths, which is the same for Row as View → Reset Row Heights, as shown in Fig. 10.14.
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Fig. 10.11 Create new clearance rule
Fig. 10.12 Clearance rules setting
Fig. 10.13 Column width adjustment
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Fig. 10.14 Reset column and row display
10.4.2 General Clearance Rule Menu select Edit → Clearances → General Clearance or click the icon in the toolbar to open General Clearance Rules window. The General Clearance Rules defines the common rules for items, including the clearance from cavity inside edge to component, from cavity outside edge to plane, from cavity to cavity, and from component to component, the clearance between test points, and etc. as shown in Fig. 10.15, which can be set according to the requirements of the process.
10.4.3 Net Class to Net Class Clearance Rule Menu select Edit → Clearances → Class to Class Clearance Rule, or click the icon in the toolbar to launch the Class to Class Clearances window, which define the clearance rules between various net classes. In 10.4.1 Create and Setup Clearance rules section, we created a new Clearances Rule and setup the rules, but these rules did not apply to the corresponding Net Class. By default, all nets follow the Default Rule, which applies to nets within the same net class and between different net classes. In many cases, due to design requirements, engineers define special clearance rules and require that different net classes follow different clearance rules. When nets belonging to the same net class are adjacent, one rule needs to be followed.
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Fig. 10.15 General Clearance Rules definition
When nets of different net classes are adjacent, another rule needs to be followed. In this condition, the net class to net class clearance rules should be specifically defined. Under the Class to Class Clearances window, as shown in Fig. 10.16, there are three net classes: Default, High_Speed, and Power, with three clearance rules, Default Rule, Clearance_1, Clearance_2. By default, the clearance rule between all net classes is Default Rule. If it is not set, for example, to remain blank, it is automatically defined by Default Rule. If it is set, it is defined by the set rules, and there is a certain priority relationship. In Fig. 10.16, the Default and Default net classes follow the Clearance_1 rule, the Default and High_Speed net classes follow the Clearance_2 rule, the Default and Power net classes follow the Clearance_1 rules, the High_Speed and High_Speed net classes follow the Clearance_2 rules, the High_Speed and Power net class clearance rules are to be set, and the power and power net class clearance rules are defined according to Default Rule.
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Fig. 10.16 Net Class to Net Class clearance rules definition window
The define principle is that if there are no settings, the common rules will be inherited and if there are settings, the set rules will be followed. It is very convenient to define the clearance rules between net classes and net classes by simply clicking the drop-down arrow and selecting the clearance rules in the list. To define a net of a net class that follows a specific clearance rule, according to the following order. Create a new clearance rule, such as Clearance_1. Define clearance parameters for each item in Clearance_1. Open the Net Class to Net Class Clearance Rules window and first select the Scheme, such as Master, in the upper right corner. Select the related net class in Source Net Class and Target Net Class, and select the Clearance_1 rule in the drop-down list. The Clearance_1 rule applies between Source Net Class and Target Net Class nets, here Source Net Class and Target Net Class can be the same net class.
10.5 Constraint Class The Constraint Class defines the electrical constraints in the design, including net length, delay, topology, crosstalk, overshoot, ringing, and so on.
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Fig. 10.17 Create new constraint class and assign nets
10.5.1 Create Constraint Class and Assign Nets The way to create a new constraint class is the same as net class. Right-click on Constraint Classes, select New Constraint Class, and enter the name of the constraint class. Then right-click the menu on the new constraint class and select Assign Nets to assign related nets to the constraint class, as shown in Fig. 10.17.
10.5.2 Classification of Electrical Constraints Electrical constraints are usually displayed as All in Constraint Manager, which is divided into the following subcategories or groups for the convenience of engineers in viewing and setting. These Groups are: Delays and Lengths, Differential Pair
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Fig. 10.18 Classification of electrical constraints
Property, I/O, Net Properties, Overshoot/Ringback, Power Nets, Simulated Delays, Template, and so on, as shown in Fig. 10.18. If All is selected, all settings will appear in the spreadsheet, making it inconvenient to set up and find. If only the corresponding groups are selected, only the relevant content will be displayed for easy setup and search. The groups are described below one by one. (1)
Delays and Lengths Group
This group is mainly used to set the delay and length of the net, including the maximum/minimum length, a set of nets match and tolerance. At the same time, the complex length or timing relationship between different nets can be set by Formulas. In Delays and Lengths group, we can also import the actual net lengths from layout design and compare them to the length set in Constraint Manager. (2)
Differential Pair Properties Group
This group is mainly used to set rules for differential pair, including allowable length tolerance between differential pairs, parameter settings for convergence and separation of differential pairs, maximum allowable separation distance, differential clearance, differential impedance, and so on. (3)
I/O Group
This group is mainly used to set the I/O standard of the net. Engineers can select the corresponding I/O standard from the drop-down list. (4)
Net properties Group
This group is mainly used to set the parameters of the net. Among them, it includes the topology of the net (including MST, Chained, TShape, HTree, Star, Custom, etc.); The Analog option is checked for analog nets and for nets that do not require Constraint Manager to automatically recognize them as Electrical Nets. In addition, set the Stub Length of the net, the maximum number of vias allowed, etc. (5)
Overshoot/Ringback Group
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This group mainly sets options such as static low level maximum overshoot, static high level maximum overshoot, dynamic low level maximum overshoot, dynamic high level maximum overshoot, high level ringback margin, low level ringback margin and non-monotonic edge. (6)
Power Nets Group
This group mainly sets the power nets. The nets selected in the Power Net bar is recognized as the power net by the system. Under this option, the Supply Voltage, Max Voltage Drop, Max Current Density, and Max Via Current can be set. (7)
Simulated Delays Group
This group mainly sets simulation-related delays, including maximum/minimum delays, maximum allowable range of delays, and delay matching relationships with other nets. (8)
Template Group
This group is mainly used for the selection and application of constraint templates. First, set up for one of the nets (such as topology, delay, overshoot, etc.). Once the setup is complete, use right-click menu to generate the constraint template, and then apply the template to the same type of nets, which can quickly improve the setup efficiency and accuracy. At the same time, in HyperLynx SI, the constraint template can be generated based on the signal integrity simulation results, and then imported and applied to the corresponding nets through File → Import → Constraint Template in Constraint Manager. The simulation results can be directly applied to the design rules to guide the design by simulation.
10.5.3 Edit Constraint Group Edit Constraint Groups can regroup and adjust existing Constraint Groups, and create new constraints groups to manage constraints classes. Start Edit Constraint Groups with the interface shown in Fig. 10.19. In this window, all constraints are on the left and constraints added to the corresponding constraints group on the right. In addition to regrouping and adjusting constraints, New Constraints Group can be created and assigned appropriate constraints to achieve personalized constraints settings and management. Click the New button in Edit Constraint Groups window, enter a new constraint group name in the pops up window, click the OK button, and then select the relevant constraints in All Constraints list and assign to the new constraint group with a right arrow. When choosing Constraints, a description of the Constraints in the below bar. Designers can choose the same type of rule to form a custom constraint group based on the description, as shown in Fig. 10.20.
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Fig. 10.19 Edit constraint groups window
Fig. 10.20 Create a new constraint group and assign constraints
10.6 Constraint Manager and Layout Data Interaction 10.6.1 Update Layout Data In Constraint Manager, menu select Data → Actuals → Update All, the actual net length in layout design can be updated to Constraint Manager and compared with the
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Error Warning Safe Setting range
Actual length
Fig. 10.21 Imports actual net length of layout to check in constraint manager
length set in Constraint Manager. The net in the safe range is gray, and the net beyond the constraints is red, indicating that error occurred. The net near the constraint setting is yellow, indicating warning, as shown in Fig. 10.21.
10.6.2 Interact with Layout Data Menu select Setup → Cross Probing in Constraint Manager, a blank bar appears at the far left of the spreadsheet where you can select the entire row by clicking the mouse. At the same time, if you select Setup → Cross Probe → Connect from the menu in Xpedition Layout, Constraint Manager and Xpedition Layout can interact with data in real time. As shown in Fig. 10.22. At this time, any net or device selected in Constraint Manager will be automatically selected and highlighted in Xpedition Layout. Similarly, any net or device selected in Xpedition Layout will be automatically selected and switched to the corresponding content item in Constraint Manager, which makes it easier to set rules.
10.7 Rule Setting Instances 10.7.1 Equal Length Setting In the design of high-speed substrate of SiP or package, high-speed signal equal length setting is a basic design requirement. There are three common methods of equal length setting in Xpedition: ➀ matching equal length, ➁ pin-pair equal length, and ➂ formula equal length, which are described one by one below. 1.
Match Equal Length
Match Equal Length requires placing a set of signals in a Match group and specifying the length range or allowable length tolerance of the signal. In Constraint Class,
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Fig. 10.22 Setup data interaction between constraint manager and Xpedition
selects Delays and Lengths Group in the drop-down list, lists the settings related to delay and length, as shown in Fig. 10.23 below. The first column is the net name, and the second column is the Type that we select in Length and TOF (Time of Fly). Depending on the selection, subsequent columns will automatically use different units (um) or (ns), Min and Max columns to set the minimum and maximum net length or TOF, by which the absolute length range of a set of nets is set. Match column is used for matching group name setting, the same name in Match column is identified as a group nets of equal-length, such as PCIE in Fig. 10.22, Tol column is used to set the maximum allowed tolerance within the group, such as 100 um in the figure. Actual column lists the actual net length, and Manhattan is the Manhattan length, which is the sum of the horizontal and vertical distances of the net connection points. With the menu Data → Actuals → Update All, the actual net length in Xpedition
Fig. 10.23 Match equal length settings
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Fig. 10.24 Electrical nets and physical nets
layout design can be updated to Constraint Manager, and displayed in Actual and Manhattan. 2.
Pin Pair Equal Length
Before learning Pin Pair, let’s first understand the concept of Electrical Nets. Electrical Nets correspond to Physical Nets. Physical Nets refers to a physically connected net. Electrical Nets refers to a net with resistance, capacitance and inductance in the middle of the net. In Xpedition, the electrical net is shown as: Netnameˆˆˆ, for example, in Fig. 10.24 below, SRIO0_RXM0ˆˆˆ is the electrical net, which contains physical nets $1N4209 and SRIO0_RXM0, similarly SRIO0_RXP0ˆˆˆ is the electrical net, which contains physical nets $1N4208 and SRIO0_RXP0. With the concept of electrical nets, it is possible to set equal lengths for nets connected with resistors or capacitors, for example, in Fig. 10.23 where SRIO0_RXM0ˆˆˆ and SRIO0_RXP0ˆˆˆ are in the same Match group, the maximum tolerance of the group is 100 um. The purpose of Pin Pair Equal Length is that when a net has multiple pins connected, the local part of the net need set for equal length. Pin Pair is not related to electrical nets. They are similar in that they have multiple pins connected to the same net. Please do not confuse. Below we understand the concept of Pin Pair. Referring to Fig. 10.25, there are two nets, Net001 and Net002, each with multiple pins connected. Each two pins can form a pair called a Pin Pair. If engineer need to set A, B, C equal length, first need to create Pin Pairs before set up equal-length between them. Generally, Pin Pair is not displayed in Constraint Manager, so it cannot be set directly. First select the Net Properties group in the drop-down list, then change the net type to Custom in the Type under Topology, then select the net, and select Auto
Fig. 10.25 The concept of Pin Pair
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Fig. 10.26 Auto Pin Pair generation
Fig. 10.27 Formula equal length setting
Pin Pair Generation from the right-click menu to generate Pin Pair, as shown in Fig. 10.26 below. Then we can refer to the Match Equal Length above to setup it. 3.
Formula Equal Length
Formula Equal length is an important method of equal length setting. It is more flexible and can set the length relationship between different nets. All formulas need to start with ‘ = ’, ‘ > ’, ‘ < ’. Formulas may or may not have units. Without units, the setting units in Constraint Manager shall prevail. The common calculation symbols in formulas are ‘+’, ‘−’, and ‘±’ if you need to input ‘±’. After entering ‘=’, ‘>’, ‘Rest indicates the length rules followed by bond wires that are not in the previously defined row. In the case of manual bonding, wire bonding is allowed within the union of the length ranges specified in all columns.
11.4.2 Settings for Die Pins When setting for Die Pins, switch to Pins TAB and setup in a window like Fig. 11.40. ➀
➁
➂
Side, sets the direction of Bond Wire, and if D is selected, the system follows the default direction, usually based on the nearest edge from Die Pad. If either of E (East)/N (North)/W (West)/S (South) is selected, it follow the direction shown in Fig. 11.41. Note that this definition refers to the orientation in the library when the chip cell is built. In the specific design, if the chip is rotated, the orientation will rotate accordingly. X1, Y1, X2, Y2, set the X and Y coordinates of the offset values of the start and end points from the center respectively. If Bond wires from multiple identical nets are bonded to the same Bond Finger, the offset values need to be set. Figure 11.42 shows the X2 and Y2 coordinate offsets, where two Bond wires bonded to the same Bond Finger and offset −150 um and 150 um on the X2 coordinates, with the starting points coming from the pins U1-23 and U4-23 of different chips, respectively. Figure 11.43 show two Bond wires bonded to the same Bond Finger with offsets of −38 um and 38 um on Y2 coordinates, respectively, with the starting points coming from the pins U1-1 and U1-2 respectively. Model, selects Bond Wire model; Padstack, selects Bond Finger.
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Fig. 11.40 Bond wire parameters and rules setup for die pins
Fig. 11.41 Bond wire direction setting
➃
Align, defines whether the Bond Finger direction is consistent with the Bond Wire direction, and Align tol. Defines the allowable errors; Row sets which row the Bond Finger belongs to, and if it’s a single row, it can be ignored.
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Fig. 11.42 X2 coordinate offset when sharing bond finger
Fig. 11.43 Y2 coordinate offset when sharing bond finger
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Fig. 11.44 Add multiple bond wires on one die pin setting
Fig. 11.45 Add multiple bond wires between die pin and bond finger
11.4.3 Add Multiple Bond Wires Between Die Pin and Bond Finger Click the Add wire button to add more than one Bond Wire on a Die Pin, as shown in Fig. 11.44, setup 3 bond wires for one Die Pin. When the setup is complete, click on the rule-set Die Pin and add Bond Wire, 3 Bond Wires will automatically appear and fan out from one Die Pin at the same time. According to the above settings, each Bond Wire start and end point has a corresponding offset value. The designer only needs to specify the location of Bond Finger and place it on substrate. The final result is shown in Fig. 11.45.
11.4.4 Fan Out from Single Die Pin to Multiple Bond Fingers Click the Add Bond Finger button to fan out multiple Bond Wires from a single Die Pin to multiple Bond Fingers, as shown in Fig. 11.46. When setup is complete, click Die Pin with the rules set and add Bond Wire. The system fans out three Bond Wires in turn with their own Bond Finger. The designer
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Fig. 11.46 Fan out from single die pin to multiple bond fingers setting
Fig. 11.47 Fan out multiple bond finger from single die pin
only needs to specify the position of Bond Finger and place it on the board. The result is shown in Fig. 11.47.
11.4.5 Bond Multiple Die Pins to One Bond Finger Another scenario in Wire Bonding design is to two or more bond Die Pins from identical nets to the same Bond Finger. At this point, we first need to set the offset value of the Bond Wire endpoint on each Die Pin, as shown in Figs. 11.42 and 11.43, with the offsets of X and Y, respectively. After setup, bond the first Bond Wire in normal mode and the second Bond Wire in the following steps: First click Die pin and Bond Finger by holding the key, and then execute the Add Bond Wire command to get the effects shown in Fig. 11.48.
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Fig. 11.48 Two die pins on the same net are bonded to the same bond finger
Fig. 11.49 Setup die to die bonding
11.4.6 Die to Die Bonding In addition to bonding from Die Pin to Bond Finger, there is also a case in which Die Pin is bonded directly to Die pin, DieToDie is selected in the Padstack bar, and as shown in Fig. 11.49, one Die pin is set to fan out two Bond Wires, one to Die Pin and the other to Bond Finger. When the setup is complete, to bond the first Bond Wire in normal mode, and the second Bond Wire will pop up automatically. The designer only needs to connect it to the corresponding Die Pin, as shown in Fig. 11.50. For Die to Die bonding, the choice of ball or wedge at the ends of the bond wire is mainly related to the selected Bond Wire model. For example, the Bond Wire model of Ball to Wedge is selected in Fig. 11.50. Figure 11.51 selects the Bond Wire model of Ball to Ball. Figure 11.52 has a Bond Wire model of Ball to Wedge on the left and a Bond Wire model of Wedge to Wedge on the right.
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Fig. 11.50 Die to die connection of ball to wedge
Fig. 11.51 Die to die connection of ball to ball
Fig. 11.52 Die to die connection of ball to wedge and wedge to wedge
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11.5 Wire Model Editor and Wire Instance Editor Wire Model Editor, in the Setup → Library menu, is used to create the Wire model and define its parameters. Wire Instance Editor, located in the Route → Wirebonds menu and toolbar, is a real-time edit and adjust tool for Bond Wire models. The main differences are that the Wire Model Editor creates and defines parameters for the Wirebond model in the local library, and the Wire Instance Editor checks, edits, and adjusts Bond wires that are already used in the design (Fig. 11.53). We can start the Wire Model Editor without selecting any entities. Bond wires in the local library appear in the list for checking, parameter editing, and adjustments. See Fig. 11.54. Before starting the Wire Instance Editor, we need to select Bond Finger or Die Pin connected to a Bond wire to see the Bond Wire and its surrounding 3D graphics in the browsing window, otherwise the window appears blank. The structure of this interface is the same as that of the Wire Model Editor, but the graphics displayed in the 3D window contain 3D graphics of other adjacent design elements in addition to
Fig. 11.53 Wire model editor and wire instance editor
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Fig. 11.54 Wire model editor is used to edit bond wire model of the local library
Bond wire, and only this Bond Wire corresponds to the model in its model list bar, as shown in Fig. 11.55. With a Bond Wire selected (often select Bond Finger or Die Pin connected to . In the open instance Editor this Bond Wire in practice), click the Tools button window, designers can adjust the shape of Bond Wire by dragging the intermediate operating points p1, p2, p3. And we can see the effect of the adjustment in real time through the 3D window. As shown in Fig. 11.56, Z coordinates of p1, P2 and P3 are adjusted accordingly, which affect the longitudinal height and curve of Bond Wire. During the adjustment process, we can view the 3D results in real time and click the Apply button to apply it directly to the layout design. This vertical adjustment is applicable for multiple row bonding as well as bond wire across components. As shown in Fig. 11.57, the Y coordinates of p1, p2, and P3 are adjusted accordingly, which affects the lateral offset and curve of Bond Wire. During the adjustment process, we can view the 3D results in real time and click the Apply button to apply it directly to the layout design. This lateral adjustment is applicable for bond wire interlace and bond wire around components. By adjusting the (X, Y, Z) coordinates of the Bond Wire operating points p1, P2 and p3, a Bond Wire with any complex shape curve can be designed, which is often encountered in practical design. The left figure of Fig. 11.58 shows the complex Bond Wire curve designed in Xpedition, which requires complex curve bending due to the position of the chip and Die Pin.
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Fig. 11.55 Wire instance editor 3D window shows bond wires and other elements
Fig. 11.56 Adjustment of bond wire curve height (Z coordinate)
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Fig. 11.57 Adjustment of bond wire curve offset (Y coordinate)
Fig. 11.58 Complex curve bond wire in Xpedition design and real photo
This complex bend is often encountered in practical design. For example, the physical photograph in the right figure of Fig. 11.58 shows complex bonding curves under a particular layout and Die Pin distribution. Comparing the left and right images shows that it is practical and effective to design complex Bond Wire curves in Xpedition. In practice, when we encounter the previously described complexity of wire bonding and can avoid conflicts by adjusting the (X, Y, Z) coordinates of p1, p2, and P3 points. Accurate simulation in Wire Instance Editor can effectively predict whether there will be problems in the actual production, thus improving the manufacturability of the product and achieving the purpose of Design For Manufacture (DFM).
Chapter 12
Cavity, Chip Stack and TSV Design Suny Li
12.1 Cavity Design Cavity is one of the most common substrate processes in ceramic packaging. Due to its many advantages in 3D structure, it has been paid more and more attention. Cavity is widely used on HTCC and LTCC substrates. At present, with the improvement of technology, it is also used in many organic substrates, such as the latest Loongson CPU plastic substrate. Cavity is a 3D structure on substrate. In order to truly simulate the cavity, EDA software is required to support 3D substrate structure.
12.1.1 Definition of Cavity A cavity is a big blind hole that opens on substrate and usually does not cross all layers (in Xpedition, we call a hole cross all layer a Contour). Cavity is created by removing substrate material to get an open void area in the internal electrical layers. Cavities can start from one of the outer layers or be embedded within the layer stackup. Cavities can be single step or multi-step; the multistep cavity is “cavity in cavity”. Figure 12.1 shows an open multi-step cavity. In Fig. 12.1, Cavity2 is located in Cavity1, and the chip is placed inside Cavity2. Some Bond Wires are bonded from the chip to the surface of the substrate, some Bond Wires are bonded from the chip to the step between Cavity2 and Cavity1, and some Bond Wires are bonded from the chip to the inside of Cavity2. Connect to different layers of traces with their respective Bond Fingers. Several typical cavity structures are described below. S. Li (B) Beijing, China e-mail: [email protected] © Publishing House of Electronics Industry 2022 S. Li (ed.), MicroSystem Based on SiP Technology, https://doi.org/10.1007/978-981-19-0083-9_12
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Fig. 12.1 Open multi-step cavity
Figure 12.2 shows the profile of an 8-layer substrate structure consisting of metal layers and dielectric layers. Figure 12.3 shows the profile of an 8 layers substrate with a 1–3 layer cavity. The starting layer of the cavity is Layer1, the ending layer is Layer3, and Layer3 is at the bottom of the cavity, exposed to external space. Components can be installed on it. Figure 12.4 shows the profile of 8-layer substrate with multi-step cavity, 1–3 layer cavity, 3–5 layer cavity and 5–7 layer cavity respectively, which is common in ceramic packaging. Bond Finger can be placed on the step of the cavity. Figure 12.5 shows the profile of an 8-layer substrate with an embedded cavity, through which discrete components can be embedded in the substrate. 1
Metal Dielectric
3 5 7
Fig. 12.2 The profile of 8-layer substrate
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1
Metal Dielectric
3 5 7
Fig. 12.3 The profile of 8-layer substrate with 1–3 layer cavity 1
Metal Dielectric
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Fig. 12.4 The profile of 8-layer substrate with multi-step cavity
1
Metal Dielectric
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Fig. 12.5 The profile of 8-layer substrate with embedded cavity
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12.1.2 Cavity Creation In Xpedition tool bar, click the Draw button
to switch to Draw Mode. Then click
the Properties button , select Type Cavity in the Type bar, set Start Layer = 1, Allow Metal = No, End Layer = 2, Allow Metal = Yes, as shown in Fig. 12.6. Then draw the cavity graphics, and in the Fab TAB of the Display Control window, check the Cavity display option in the Board Elements under the Board Objects to see the 1–2 layer cavity structure as shown in Fig. 12.7. Subsequently, a multi-step cavity is drawn, from layers 1–2, 2–3, and 3–4, respectively. The cavity that has just been drawn can continue to be added 2–3 layer cavity and 3–4 layer cavity. In addition, a 1–4 layer cavity can be drawn next to the multi-step cavity for reference and comparison. The overall settings are shown in Fig. 12.8. After finishing cavity creation, open the 3D View window to get two types of cavities as shown in Fig. 12.9. Cavity structure is common in ceramic packaging. Generally complex components, especially when multilayer bonding is required, need to be placed in cavity, such as SoC, DSP, and FPGA, which need multi-step cavity support, and Bond Fingers are placed on the steps of the cavity.
Fig. 12.6 Properties settings for cavity
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Fig. 12.7 1–2 Layer cavity structure
Fig. 12.8 Properties setting for different layer cavities
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Fig. 12.9 Multi-step cavity and single step cavity
There are three main advantages for bonding of complex components in cavity: ➀ It can effectively reduce the height of the bonding wire, thereby reducing the thickness of the package; ➁ It can effectively reduce the length of the outermost bonding wire in multilayer bonding; ➂ we can use cavity to install components on the bottom side of the package.
12.1.3 Place Component into Cavity Once the cavity is designed, the components can be placed into cavity. There are usually two steps: (1) moving the component over the cavity; (2) release the mouse button, if there is no rule conflict, the component will drop down into the cavity automatically, as shown in Fig. 12.10. In Xpedition, the most obvious sign that component drop into the cavity in 2D design environment is that the Pad color of the component change, from the color of top layer pad to the color of the layer in which the cavity bottom located. In the process of placing the component into cavity, if there is a rule conflict, the component cannot be placed into cavity normally, and the related rule settings need to be checked. One exception is that the designer intended to place the component cross over the cavity. In this case, the component is usually larger than the cavity. When the rule setting is met, the component does not drop into the cavity but cross over it, as shown in Fig. 12.11. After the completion of the components layout, open the 3D viewer window, we can get the 3D picture as shown in Fig. 12.12.
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Fig. 12.10 Place component into cavity
Fig. 12.11 Place component crossing over the cavity
12.1.4 Bonding in Cavity After the chip layout is finished, the next step is bonding. Rule settings are also required between Bond Wire bonding and cavity. For example, Wire to Cavity clearance rules, please refer to Sect. 11.4 Bond Wire Rule Settings. There are also cavity rules set up in Constraint Manager, refer to Sect. 10.4.2 General clearance Rules.
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Fig. 12.12 3D view of components and cavity
The designer should note that Bond Finger cannot be placed at the edge of the Cavity (which is not allowed in the production process), it can be placed outside or inside the Cavity, as shown in Fig. 12.13. For multi-step cavity, Bond Finger can be placed on the steps of multi-step cavity. If there is no violation of DRC rules, Bond Finger can be placed on any step of a multistep cavity. When the same Bond Wire is bonded to Bond Finger at different steps, its shape also changes adaptively (by Spline curve fitting, which takes into account
Fig. 12.13 Bond Finger cannot be placed across the cavity boundary
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Fig. 12.14 Bond wire profile adjust with bond finger move
Fig. 12.15 Two-sided multi-step cavity and chip bonding profile of a real project
height, length changes and the stress effect). This can be simulated in Xpedition software as shown in Fig. 12.14. Xpedition can support two-sided multi-step cavity, that is, multi-step cavity can be created on both Top and Bottom sides of the substrate, and chips can be placed into multi-step cavities for bonding, as shown in Fig. 12.15 as a profile of real customer project. From Fig. 12.15, we can see that there are multi-step cavities on the top and bottom sides of the substrate. Chips are placed in cavity for bonding. The bonding wires are up to 4 levels, which are bonded to different steps of the multi-step cavity. This kind of design greatly reduces the thickness of the package and effectively reduces the length of the outer-ring bonding wires. In addition, this cavity structure facilitates the sealing of ceramic package or SiP.
12.1.5 Embedding Chip into Substrate with Cavity With the increasing complexity of system design and the increasing function of the system, more and more components are integrated in system to meet different
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functional needs. At the same time, due to the increasing demand for miniaturization design, the area on the surface of the substrate for component installation is also getting smaller and smaller. Installing more components on smaller substrates is a contradiction in itself. To solve this problem, in addition to continuously reducing the size of the components, another generally accepted method is to embed the components into the inner layer of the substrate, thereby saving the limited surface space of substrate. There are two general methods for embedding components into the inner layer of substrate, which are the discrete embedding and the planar embedding. The discrete embedding refers to the direct embedding of discrete components into the inner layer of substrate during the production of the substrate, where the discrete components include bare chips and passive components such as resistors, capacitors, inductors, etc. The discrete embedding is affected by the thickness of the substrate and the size of the discrete components. Generally, only chips and passive components with smaller size and thickness can be embedded. The advantage is that the discrete components have relatively high accuracy, and support large resistor, capacitor and inductor values. Planar embedding technology is used to make passive components such as embedded resistors and capacitors by printing with paste or by press-in dielectric thin film in substrate. Planar embedding has little effect on the thickness of the substrate, but it also has some limitations. For example, for planar capacitor, limited by the dielectric material itself and the area of the capacitor, the capacitor value that can be provided is small. For resistors, size also affects them and they cannot consume much power. At the same time, the accuracy of planar embedded passive components is not as good as that of discrete components, so planar embedded components usually need laser adjustment to assist in controlling the accuracy of passive components. Xpedition supports both types of embedding. Discrete embedding technology is discussed here. Refer to Chap. 15 Embedded Passive Design for planar embedding technology. Next, we will learn how to embed discrete components in the substrate in Xpedition through specific steps. The first step is to determine which layers the chip will be embedded in the substrate. Designer’s attention is needed here because it is the embedding of discrete components, so the height of the chip or passive component and the thickness of each layer of the substrate need to be considered to calculate the space occupied by the embedded components. In this example, a bare chip is planned to be embedded in layers 4–6 of the substrate. The second step, draw an open cavity in the substrate, as shown in Fig. 12.16. Here, draw a 1–6 layer cavity, the size of the cavity is suitable for chip placement, and take into account the Constraint Manager rules setting, the clearance between cavity and chip and the clearance between cavity and metal, leaving the appropriate space, to avoid the DRC conflict causing the chip not to be placed in the cavity.
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Fig. 12.16 Draw an open cavity on substrate
To see the 3D effect of the cavity more visually, we can open the 3D viewer window through the menu Window → Add 3D Viewer. On the right side of Fig. 12.16, we can see the 3D effect of the cavity and chip. The third step, toggle to place mode, moved the chip over the open cavity. If there is no DRC violation, the chip will drop down into the cavity automatically, as shown in Fig. 12.17. In Xpedition, by default, the finished Bond Wire and Bond Finger will move together with the chip and keep the relative position. When the designer want to
Fig. 12.17 Place components into the open cavity
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Fig. 12.18 Change the cavity start layer to 4
move chip only, he can choose “Move Chip Only” from the right-click menu before moving the chip, only the chip can be moved independently. At this time, the bonding finger stays fixed and the bonding wire will automatically adjust its shape to suit the change of the chip position, provided that the DRC rules are met. The fourth step, after placing the components in the cavity, toggle to drawing mode, select the cavity and double-click the left mouse button to open the properties window, and change the Start Layer of the cavity properties to 4, giving an embedded 4–6 layers cavity, as shown in Fig. 12.18. The fifth step, open the 3D Viewer again, we can see that the cavity has closed, the number of layers it occupies is 4–6, the chip is in the inner layer of the substrate, the bottom of the chip is in the sixth layer of the substrate, the bonding finger is also in the sixth layer of the substrate, and the trace from the bonding finger is also in the sixth layer, as shown in Fig. 12.19. Figure 12.19a is translucent display effect, and Fig. 12.19b is opaque display effect. The sixth step, after the chip is embedded in the substrate, we can route around the chip. Because layer 4–6 are occupied by cavity, we can route in layers 1, 2 and 3 over the chip, in layer 6, we can route from the bond finger, in other layers, we can route as for ordinary substrate. Figure 12.20 shows the position relationship between the chip, cavity and trace in each layer. So far, the operation method of embedding discrete components in substrate in Xpedition has been completed.
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Fig. 12.19 Chip embedded in the inner layer of the substrate
Fig. 12.20 The positional of embedded chip and traces in each layer
12.1.6 Embedding Chip by Adding Cavity to Die Cell It is flexible to embedding discrete chips into the substrate through the cavity, which can support all types of components, but it can be troublesome to change the definition of the cavity and reposition the component, if designer want to reposition the component after embedded. The method described below is to draw a cavity directly in cell when Die Cell is created. The cavity attaches to the component cell, wherever the component moves, the cavity will follow, and it is more convenient when the embedded component switch layer. However, this method currently only supports Bare Die type component, and its pin is SMD type pin, which is the pin that at the bottom of the chip.
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Fig. 12.21 Add cavity to bare die type cell in Cell Editor
After a Bare Die type cell is created in Cell Editor, a cavity is drawn on the periphery of the cell, and the distance between the cavity and the Placement Outline of the cell should conform to the corresponding process standards. Note that the cavity Start Layer and End Layer are both 1, Allow Metal yes, and the properties are not editable, as shown in Fig. 12.21, then save and exit. Then, in Xpedition Layout environment, place this component, view the position of the chip through 3D view window. The chip is first placed on the surface of the chip, as shown on the left side of Fig. 12.21. Then move the component. In move mode, right-click menu to select Change Layer, open the window shown on the right side of Fig. 12.21, and set the layers that need to be switched in the After bar, such as layer 5 in the figure (Fig. 12.22). After clicking Apply, the chip will be placed in Layer 5, as shown on the left side of Fig. 12.23, where the selected chip can switch the installation mode in the cavity by Push command, such as at the bottom of the cavity, or at the top of the cavity, and the corresponding installation layer will also switch from Layer 5 to Layer 4. See Fig. 12.23. From the above description, it can be seen that adding cavity to Cell is flexible for post-processing, but it is limited for the Cell type, which can be used if a Bare Die type chip needs to be embedded. For other types of chips, as long as their pins are SMD type, they can also be artificially set as Bare Die, the embedding in this way is also a flexible design method.
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Fig. 12.22 Place component then change layer setting
Fig. 12.23 Switch the installation mode in cavity by Push command
12.2 Chip Stack Design 12.2.1 The Concept of Chip Stack In order to save space and reduce the substrate area in SiP design, chip stack is often used to stack multiple chips together, insert media in the middle or use special technology for electrical isolation. Figure 12.24 is a physical picture of the chip stack in which media is inserted to lift the upper chip to avoid conflicts with the lower bond wires. Figure 12.25 is a 3D screenshot of chip stack and interposer inserted in chip stack in Xpedition design environment. Chip stack is usually divided into the following two types: Pyramid chip stack and Cantilever chip stack, which have different requirements for insertion media. The pyramid chip stack cannot insert media or insert thin media, while the cantilever chip stack must insert media with a certain thickness to raise the upper-level chip to avoid conflict with the lower-level bond wire, as shown in Fig. 12.26.
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Fig. 12.24 Real photo of chip stack
Fig. 12.25 3D screenshot of chip stack, interposer and bond wire
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Fig. 12.26 Pyramid chip stack and cantilever chip stack
12.2.2 Chip Stack Creation Because interposer may be required in a chip stack, interposer creation is the first step in creating a chip stack. Select the menu command Setup → libraries → Cell Editor → Mechanical. For interposer, the important parameters are height (thickness) and size. Height is set in cell properties, as shown in Fig. 12.27.
Fig. 12.27 Interposer creation interface
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Fig. 12.28 Chip stack operations
Interposer size needs to be drawn in Cell Editor. Click the Editor Graphics button to enter the Cell Editor interface, draw the Placement Outline of Interposer according to design need, and then save and exit Cell Editor. in the Wire After interposer creation, click the Part Stack Configuration button bond toolbar to create and setup the chip stack. First, create a new part stack, such as Newstack2. Enter Parts with Die Pins in the Criterion bar. We can see that all the bare chips are listed in the list below. Select one . The chip is placed in of the components and click the single downward arrow the stack. We can also add all the bare chips to the stack by double downward arrow. In the left-most bars of a chip stack, 0, 1, 2, indicate the number of layers the chip is in the stack. Usually 0 represents the lowest layer, 1 represents the layer above or down arrow layer 0, and so on. chip position can be adjusted by an up arrow , as shown in Fig. 12.28. Rotation indicates the rotation angle of the selected chip in the stack. Different components can have different rotation angles in the same stack, as shown in Fig. 12.29.
12.2.3 Stack Chips Side by Side In chip stack design, there is a situation where two or more small chips are arranged side by side on top of a large chip, that is, multiple chips are located on the same layer of the stack, this is known as Stack chips Side-by-Side, as shown in Fig. 12.30. or down arrows to adjust To stack chips side-by-side, simply use the up the chips that need to be stacked side by side on the same layer. As Fig. 12.31 shows, U5 and U7 are both on layer 2 of the stack, so naturally they are arranged side by side. When two chips are on the same layer of chip stack, their Bond Wire Start heights are the same, and if this situation is not accurately described by the design tool, it will have a certain impact on the production and processing of SiP. When two or more chips stacked in the same layer, they are usually placed on a silicon interposer, which has traces and TSVs. Chips can be electrically connected with the silicon interposer in the form of Bond Wire or Flip Chip, and then the silicon
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Fig. 12.29 Chips with different rotation angles in stack
Fig. 12.30 Stack chips side by side (Side View)
Fig. 12.31 Stack chips side by side in the same layer
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interposer can be connected with the lower chip or package substrate in the form of Bond Wire or Bump.
12.2.4 Chip Stack Adjustment and Bonding When a stack is created, it automatically forms a group and freezes together, moving as a whole instead of just one chip. If we need to adjust the relative position of a chip in the stack, we need to first Unfreeze Group. , then select the chip stack, In Xpedition interface, first switch to place mode right-click the Unfreeze command button to unfreeze the group, so that the chips in stack can move independently. After the adjustment is completed, we freeze the group again to avoid misoperation of the relative position of the chip in stack. As shown in Fig. 12.32, the chips in Freeze and Unfreeze states show, Group Outline in Freeze state is thick and solid, Die Pin is hollow, Group Outline in Unfreeze state is thin and dashed, and Die Pin is normal filled. Figure 12.33 is a 3D display of the relative position of the stacked chips side by side. The wire bonding of chip stack is the same as that of ordinary chips, but the height and span of bonding wires need to be considered when bonding. In the Wire Bond/Power Ring Generator window, select the chip stack, such as Newstack1, then setup the appropriate bonding rules, we can use auto-bonding function, as shown in Fig. 12.34. Because the 3D relationships in the stack are complex, automatic bonding in chip stack takes longer time than in single chip. If the results of auto-bonding are unsatisfactory or, in some cases, the spatial DRC relationship is too complex for the software to complete auto-bonding, a manual bonding by the designer is required. The flexibility of manual bonding is that the
Freeze Fig. 12.32 Freeze and Unfreeze states of the chip stack
Unfreeze
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Fig. 12.33 Stack chips side by side (3D View)
Fig. 12.34 Chip stack auto-bonding setup
designer can adjust the height, span and profile of the bond wire flexibly according to the specific factors such as the position and height of the chip, so as to meet the requirements of production and processing.
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12.2.5 Chip and Cavity Combination Design Chip stack effectively reduces the area of the substrate, at the same time it increases the total height of the chips, and the bond wire of the top chip will therefore span too large. In order to effectively reduce the thickness of the package and SiP and reduce the length of the bonding wire of the upper chip, chips are usually stacked in the cavity. In most cases, the cavity the chip stack placed is multi-step cavity, and Bond Finger is located on different steps of the cavity, as shown in Fig. 12.35. Figure 12.36 shows an example of a user-designed multi-step cavity in Xpedition. The cavity has 4 steps, and the chip with two rows die pins is placed at the bottom of the cavity. The out row Die Pins are bonded to step3 and step4 of the cavity, the inner row Die Pins are bonded to step1 and step2 of the cavity, which effectively reduces the height and length of the bonding wire. Figure 12.37 shows a design example of hybrid technology in Xpedition, which includes step cavity, chip stacks (side-by-side stacks), Die to Die bonding (including
Fig. 12.35 Place chip stack in cavity and bonding
Fig. 12.36 Design example of chip bonding in multi-step cavity
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Fig. 12.37 Design example of hybrid technology
both Ball to Wedge and Wedge to Wedge bonding), and RF circuits. It is a hybrid design of many technologies.
12.3 Concept and Design of 2.5D TSV A silicon interposer is placed between the SiP substrate and bare chips. The interposer has many Silicon through vias (TSV), which connects the top metal layers and bottom metal layers of the silicon interposer. This kind of TSV is called 2.5D TSV. The silicon interposer is a passive component, and the 2.5 TSV is not drill on active chips. 2.5D TSV is currently widely used, for example CoWos (Chip-on-Wafer-onSubstrate) of TSMC uses 2.5D TSV, which installs chips on silicon interposer and interconnects them with high-density trace in silicon interposer. Figure 12.38 shows the 2.5D TSV structure of CoWos as an example. 2.5D TSV requires two substrates: a silicon interposer + a package substrate, so two layout designs are required. The template of silicon interposer can be designed using the silicon layout template described in Chap. 9, and the template of package substrate can use the layout template of organic or ceramic substrate described in Chap. 9.
Fig. 12.38 2.5D TSV structure diagram
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For multi-layout design, refer to Chap. 18 of this book: Multi-layout projects and concurrent design, for 2.5D TSV design, refer to Chap. 24 of this book: 2.5D TSV technology and design case.
12.4 Concept and Design of 3D TSV 12.4.1 Concept of 3D TSV 3D TSV refers to the TSV on IC chip body, and conducts electrical interconnection of the chip through the 3D TSV. At least one bare chip is overlapped with another bare chip, and the chip body has TSV. Through 3D TSV, the top bare chip, the bottom bare chip and the interposer or substrate are interconnected and communicated electrically. For example, HBM and HMC use 3D TSV integration technology. 3D TSV can be divided into two categories according to the relationship between the upper and lower chips connected: (1) the upper and lower chips are identical in the stack, and (2) the upper and lower chips are different in the stack. In addition, according to the time of TSV generation, there are two types: one is that TSVs are reserved at the time of chip design. These TSVs cause additional area overhead of the chip, which we call class A. The other is that TSVs are not considered at the time of chip design, but are generated at the periphery of the chip and connected through TSV in later production stage, which we call class B. In this way, there are four types of combinations: ➀ A, ➀ B, ➁ A, ➁ B. We will start with the example that the top and bottom chips in the stack are identical and TSV is generated on the periphery of the chip in later production stage, i.e. type ➀ B. The TSV penetrates the chip and forms metal contact points on the top and bottom surfaces of the chip. We can think of it as the pad on the top and bottom surfaces of the chip, which is connected by the TSV in the middle, as shown in Fig. 12.39. Then, stack the chips together. As long as the upper and lower chips align with each other, the electrical interconnection of the chips in the stack will connect the
Fig. 12.39 3D TSV cell structure diagram
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Fig. 12.40 Chip stack interconnect through 3D TSV structure
entire chip stack. Then we route trace from the bottom surface Pads of the layer0 chip, the whole chip stack will connect to the substrate, as shown in Fig. 12.40. For type ➀ A, the design method is similar to that described above, except that the number of TSVs will be larger and TSVs will be distributed on the surface of the chip as array. For type ➁ A and ➁ B, because there are different types of chips stacked together, the TSVs are usually not fully aligned, so it is necessary to reroute and distribute pins through the RDL layer to align and electrically interconnect the Pad on the lower surface of the upper chip and the Pad on the upper surface of the lower chip, as shown in Fig. 12.41. RDL can be generated either on the lower surface of the upper chip or on the lower chip. Choose a simple and cost-effective process whenever possible.
Fig. 12.41 Redistribute pin positions with RDL and interconnect with 3D TSV
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12.4.2 3D TSV Cell Creation When designing a 3D TSV, the first step is to create a Cell that supports the 3D TSV, which we call TSV Cell. In the process of chip stack and electrical interconnection through TSV, a concept often mentioned is alignment, that is, vertical interconnection after alignment of the upper and lower TSV, and TSV Cell creation is based on this concept. When we create a TSV Cell, we need to place Die Pad on both top and bottom of the chip. Top and bottom Die Pads have the same Pin numbers and are aligned. The software automatically recognize that the two die pads are connected electrically through the TSV, as shown in Fig. 12.42. In Xpedition environment, TSV Cell is created based on the ordinary Bare Die Cell, and the following changes are made: (1) Pin# is the same for both side, and the same Pin# is placed in Top layer and Bottom layer respectively, as shown on the left side of Fig. 12.42. With the same Pin#, the system automatically considers them with the same net, with net lines connecting to them, as shown on the right side of Fig. 12.42. Then, the top and bottom pins are aligned and Xpedition software connects the top and bottom Die Pads electronically through TSV, as shown in Fig. 12.43. In addition, in the TSV chip stack, there are several layers chips, different from other layer chips, the bottom side Pad type of bottom layer chip should be SMD, as shown on the left side of Fig. 12.44, with the Pad of Bottom side replaced with SIP_PAD_160_SMD. With this way, once the chip stack is complete, the entire TSV chip stack can be interconnected to the substrate or interposer like an SMD-type component. When the Pads of the same net of the chip top and bottom sides are aligned, a small diagonal cross symbol appears on the Pad, indicating the electrical connection between the top and bottom side pads, as shown on the right side of Fig. 12.44.
Fig. 12.42 3D TSV cell creation method
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Fig. 12.43 Connect the top and bottom Die Pad of the chip through TSV
Fig. 12.44 The bottom-most chip has a SMD type bottom pad
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Fig. 12.45 Pin alignment principle between chips of stack
12.4.3 Pin Alignment Principle Between Chip Stack Only pin alignment between the top and bottom chips can be used for electrical interconnection. Of course, the best effect is the pins exactly aligned between the top and bottom chips. If pins cannot be aligned completely due to different processes, the below principles need to be followed. Assuming that the upper and lower Pad sizes are not identical, when the center of a small Pad locates within the area of a large Pad, the software recognizes as an electrical connection, as shown in Fig. 12.45a, and when the center of a small Pad locates outside the area of a large Pad, the software does not recognize as an electrical connection, as shown in Fig. 12.45b. If the upper and lower Pad sizes are identical, the software identifies the electrical connection as long as either Pad center locates within the area of another Pad, otherwise it is not connected.
12.4.4 3D TSV Stacking and Interconnection First, we create a project that contains eight bare chips, four of which are a set of TSV chip stack, a total of two sets of chip stacks, in the form of BGA package. Net connections can be input either in schematic or in netlist, referring specifically to SiP schematic design in Chap. 8 of this book. In this example, eight bare chips are U0 ~ U7, of which U0 ~ U3 is StackA group and U4 ~ U7 is StackB group, as shown in Fig. 12.46. It is important to note that the Bottom layer Pad of each bottom chip of the stack should be SMD type. We need to specify a special Cell for bottom chip of each stack that is different from the other three chips or create a different Part for the bottom chip so that it can be distinguished from other chips. After creating the chip stack, we can check the connection between the chips. First, unfreeze the chip stack, then move each chip independently. When the chips are moved, we can see that the electrical connection between pins are connected
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Fig. 12.46 Create chip StackA and StackB
by net lines, indicating that the net is not physically connected yet, as shown in Fig. 12.47. We move the relative position between the two chips, such as the relative positions of U2 and U3, and observe the change of the pin-to-pin connection between them. When the pin contacts or even partially overlaps, the net lines still exist. Only when
Fig. 12.47 Net lines indicate electrical connections between pads
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Fig. 12.48 Software identifies electrical connections when one pad center locates in another pad
Fig. 12.49 The completion of 3D TSV chip stack (3D view)
the overlap is more than half, that is, when one Pad center locates in another Pad, the net lines disappear, as shown in Fig. 12.48. The disappearance of the net line indicates the formation of a physical connection, at which point the software assumes that the net is connected, and we then fully align the Pad. Open the 3D View and we can see the stack of 3D TSV chips as shown in Fig. 12.49.
12.4.5 3D Pin Model Setup From Fig. 12.49, we can see that the chip stacks have spherical Bump connections, Xpedition supports 3D Pin Model. To set up a 3D Pin Model, first add related properties in Cell Editor → Cell Properties → Custom Properties. • • • • •
3D_PinModel: Settable types are Ball, CopperPillar, CappedCopperPillar. 3D_ PinDiameter, set the diameter of the ball or the CopperPillar. 3D_ PinLength, set the length of the CopperPillar. Felt 3D_ PinTopCut, set the cut length at the top of the ball. Felt 3D_ PinBottomCut, set the cut length at the bottom of the ball.
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In this example, we set 3D_ PinModel = Ball, 3D_ PinDiameter = 100 µm, 3D_ PinTopCut = 20 µm, as shown in the figure below, since the bottom and other chips belong to different Cells, they both need to be set, as shown in Fig. 12.50. Then make specific parameters setting in Package Utilities, menu select Package Utilities → Edit → 3D Pin Model. Package Utilities is a plug-in that needs to be installed separately, there are many settings and features related to advanced packaging, so it is recommended that SiP and package designers install it. The 3D Pin Model settings window has three options: Ball, Copper Pillar, and CappedCopper Pillar. Each option has different parameter settings, see Fig. 12.51. This requires the designer’s attention that if the settings in the user properties and the definitions in 3D Pin Model window are inconsistent, the 3D window will be displayed with the definitions in 3D Pin Model. For example, if the user properties are defined as Ball and the 3D Pin Model is defined as CopperPillar, it will be displayed as CopperPillar, but this is not recommended and generally consistency is recommended. In the same way, we can also define a 3D Pin Model for BGA package. Then, place the two sets of TSV chip stacks in a reasonable position, as shown in Fig. 12.52, with 2D view on the left and 3D view on the right.
Fig. 12.50 Setting of 3D Pin Model custom properties
Fig. 12.51 3D Pin Model settings window
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Fig. 12.52 TSV chip stack placement
12.4.6 Net Optimization and Route Menu select Place → Automatic Swap → Swap by Part Number, places the BGA in the right included column, Swap Items choose Pins, checks the Exhaustive swap option, and clicks Apply. During swap process, the software will have a short pause, if the design is more complex, the pause time will be longer, Swap completed, we can see the number of swapped pins and saving space estimates below, if we want to re-optimize, click Apply again until Swap Count and Savings are 0, the entire process is shown in Fig. 12.53. As shown in Fig. 12.54 before and after optimization, it is clear that after optimization, net crossover is less and connection is shorter. Further optimizations can be made by manually swapping pins, which are not detailed here. After optimization, we can use manual route and auto route. Here we select auto route, which can complete the route quickly. In the later stage, we use manual adjustment to improve the route effect. The route result is shown in Fig. 12.55, with 2D view on the left and 3D view on the right.
Fig. 12.53 Optimize net connection through automatic swap
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Fig. 12.54 Comparison before and after net optimization
Fig. 12.55 Auto route completion effect
12.4.7 DRC Check and Complete 3D TSV Design After the design was completed, we do DRC check to make sure the design was correct. In this example, we mainly checked the connectivity of the net, focusing on whether the net connection through 3D TSV can pass the DRC check. By checking, we found three Hazards, all Dangling Via and Jumpers. After clicking on this item, we found that they are all redundant VCC net vias due to auto route, usually remove these vias.
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Fig. 12.56 Unrouted and Partial Nets is 0
The Unrouted and Partial Nets we are concerned about is 0, that is, all nets are properly connected. As shown in Fig. 12.56. At this time, if a chip in the stack is moved artificially, for example, U3 is moved away from the aligned position, as shown in Fig. 12.57, it can be seen that the net lines have been displayed, indicating that the physical connection break. At this point, re-run DRC checks, Hazard + 80, all Unrouted and Partial Nets. Click on this item to see that they are both connection problems between U2 and U3, exactly the same as our artificial manufactured errors, see Fig. 12.58. Put U3 back in the right place, run DRC again, and Unrouted and Partial Nets back to 0 (−80), as shown in Fig. 12.59. Finally, in 3D View, we can see the completed design. Eight chips are divided into two groups, each with four layer chips connected by 3D TSV, and installed on a BGA substrate, as shown in Fig. 12.60.
Fig. 12.57 Net lines indicating physical connection break
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Fig. 12.58 Move U3 to break the TSV connection, Unrouted and Partial Nets +80
Fig. 12.59 Unrouted and Partial Nets goes back to 0 (−80)
Fig. 12.60 Completed 3D TSV chip stack packaging design
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Chapter 13
RDL and Flip Chip Design Suny Li
13.1 Concept and Applications of RDL RDL, an abbreviation for Redistribution Layer, that is, to make one or more layers of metal on the active chip side to redistribute the pins of the chip. The initial pins of most chips are distributed along the edge of the chip, which is more suitable for wire bonding process. Only a few chips have pins in the form of array. When use advanced packaging, RDL is needed to redistribute the pins. RDL can be divided into Fan-In and Fan-Out types according to the location of the RDL Pad. Fan-In means that the RDL Pad is on top of the Chip Body and Fan-Out means that the RDL Pad is on a Molding Area outside the Chip Body. See Fig. 13.1.
13.1.1 Fan-In RDL RDL starts with the Fan-In type, through which the pins of the chip can be rearranged to any reasonable position on the surface of the chip. Using RDL technology, the Die Pad located around the chip that supports traditional Bond Wire can be reassigned to the entire surface of the chip. RDL Pad is also called UBM (Under Bump Metal) from a process perspective, which refers to the metal area under the welding ball. From a design perspective, it is more convenient to call it RDL Pad. RDL deposits metal and dielectric layers on the surface of the wafer and forms corresponding metal route patterns. The IO ports (pins) of the chips are repositioned, distributed to new areas with more loose pitch and space occupation areas, and a planar array is formed.
S. Li (B) Beijing, China e-mail: [email protected] © Publishing House of Electronics Industry 2022 S. Li (ed.), MicroSystem Based on SiP Technology, https://doi.org/10.1007/978-981-19-0083-9_13
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Fig. 13.1 RDL can be divided into Fan-In and Fan-Out two types (top view)
With this redistribution, the position of the pins has changed, and package or SiP designers have more flexibility to consider the layout of the chips for Flip Chip or SiP design. Traditional Fan-In RDL has to place all I/Os within the chip size range, so its routing is from the Die Pad near the edge of the chip inward to the RDL Pad. Generally, the RDL layer scheme chooses single-layer aluminum, single-layer copper, or multilayer copper. For most designs, a single layer design is sufficient, as shown in Fig. 13.2. The RDL process is to coat an insulation layer on IC chip, define a new trace pattern by exposure development, and then use electroplating technology to make a new metal trace to connect the original Die Pad to the new RDL Pad or Bump for the purpose of redistribution. The rerouting of the metal traces is mainly made of electroplated copper, and nickel-gold or nickel-palladium-gold can also be plated
Fig. 13.2 Fan-In RDL diagram (side view)
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RDL Pad Die Pad
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Fig. 13.3 Fan-In RDL physical photo (top view)
on the copper traces as needed. The copper structure has the advantages of low resistance, high heat dissipation and low cost, making it the best choice for high current and high power devices. RDL advantages: can change the original design of I/O, increase the added value of the original design; It can increase I/O spacing, provide larger Pad or Bump contact area, reduce stress between substrate and components, increase reliability of components, replace part of IC trace design, and speed up IC development time. Another advantage of the RDL layer comes from the cost control of the chip. The life cycle of the chip design can be extended by RDL technology without expensive IC chip redesign. Using the RDL layer usually results in minimal cost overhead. As shown in Fig. 13.3, this is a physical photo of the Fan-In type RDL. The small Pad near the edge of the chip is the Die Pad and the large PAD near the center of the chip is the RDL Pad.
13.1.2 Fan-Out RDL Fan-Out technology corresponds to Fan-In technology. When the chip has more I/O, but the size of the chip is not significantly increased or even reduced, how to accommodate more I/O and keep the pitch, Fan-Out technology appears. Traditional Fan-In RDL has to place all I/Os within the chip size range. Fan-Out can place I/Os outside the chip size range. How can it be done? In typical Fan-Out process, a thin carrier wafer is bonded to the tape for scribing, and the KGD dies are placed downwards to form a “reconfigured wafer element”, which are then molded, and then the carrier wafer and tape are removed. The molding function is as follows: (1) Fan-Out bearing area (2) to protect the back of the chip.
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Fig. 13.4 Fan-Out RDL diagram (side view)
The rerouting process can then be performed on the exposed chip surface, the I/O pads can be rearranged, the bumps can be made, and then the individual package can be diced. As shown in Fig. 13.4, the RDL Pad of Fan-Out is in molding region located outside the chip body. It is important to note that in the general Fan-Out concept, RDL Pads are distributed not only in the Molding region but also in the inner region of the chip. This technique is collectively referred to as Fan-Out, whereas the Fan-In concept is rarely mentioned. The concept of Fan-Out package includes RDL Pad redistribution in both directions of Fan-Out and Fan-In. In addition to Fan-In and Fan-Out described earlier, the main applications of RDL include Via last backside routing of 3D TSV, silicon interposer in 2.5D TSV, etc. For the design of 3D TSV, you can refer to Chap. 12 of this book: Cavity, Chip Stack and TSV design. For the design of 2.5D TSV, you can refer to Chap. 24 of this book: 2.5D TSV technology and design cases. In addition, RDL is also an important technology of advanced packaging.
13.2 Concept and Features of Flip Chip Flip Chip, or FC for short, is a new kind of micro-assembly technology, which has become a common packaging form in the field of high-end devices, high-density packaging and SiP in recent years. Today, Flip Chip technology is being used more and more widely, and the requirement of this technology is also increasing. It poses a series of new and severe challenges for design and production. Designers need to face these challenges and solve the related problems to provide reliable support for the whole process of design, packaging and testing for this technology. The traditional packaging technology is to place the chip active side upward and bond the back side of the chip to the substrate, and then interconnect the electronics through Wire Bonding and TAB technology. Flip Chip, on the other hand, face the
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Fig. 13.5 Flip Chip diagram
chip active side to the substrate, interconnects the chip to the substrate through solder bumps arranged in an array on the chip. On the one hand, Flip Chip technology greatly shortens the length of signal interconnection, reduces the delay, and effectively improves the electrical performance, which is very advantageous for high-speed design. On the other hand, because of the array connection, this kind of interconnection can provide higher I/O density. At the same time, Flip Chip occupies a very small area, almost the same size as the chip. Compared to Wire Bonding and TAB, Flip Chip can achieve the smallest and thinnest package. Flip Chip has become the mainstream packaging technology for high I/O number chips such as high performance CPU, GPU, FPGA and Chipset. Because the Flip Chip I/O pads are distributed over the whole chip surface, it has greater advantages in packaging density and signal processing speed. Flip Chip can be processed by means similar to SMT technology, it is the direction of the development of SiP and high density package. Flip Chip has distinct advantages. ➀ Flip Chip pins are short in length and have the smallest parasitic parameters. ➁ Flip Chip uses a planar array connection, which greatly improves the electrical performance and reduces the package area. ➂ Flip Chip can support more pins to meet the growing demand for I/O. Figure 13.5 is a diagram of Flip Chip. As you can see from the diagram, the Flip Chip is connected to the package substrate through Bumps and then reinforced by under fill. Compared with Bond Wire connections, Flip Chip has no dangling leads, has shorter connections, less parasitic effects, and can support higher frequency signals. Of course, Flip Chip also has its limitations. (1) Flip Chip needs to make bump on wafer, which is a relatively complex process. (2) If the chip is not designed specifically for Flip Chip, the RDL layer needs to be designed and processed. (3) Flip Chip is more susceptible to temperature changes. Consideration should be given to the matching of CTE (Coefficient of Thermal Expansion) between chip and SiP substrate, which has higher thermal analysis requirements. In summary, the advantages of Flip Chip offer us greater opportunities for smaller, faster and more powerful packages, while its shortcomings pose greater challenges requiring more complex processes, more matching materials and higher requirements for thermal analysis.
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From the description above, we know that if the chip itself is designed for the Wire Bonding process, and Flip Chip package is required, RDL layers need to be designed and processed, which usually exist in the form of Fan-In, i.e. only on the surface of the chip. For Fan-Out RDL, Bump can also be made larger because of its relative large area. Generally, it does not need to be re-packaged, but can be installed directly on the PCB board. Although there are significant differences between Fan-In and Fan-Out RDL from a process perspective, they are basically the same from a design methodology and design tools perspective. Therefore, we will focus on Fan-In RDL and use it to package the chip in Flip Chip form.
13.3 RDL Design From the point of view of SiP or packaging design, if IC chips are specifically developed for Flip Chip, there is no need to design and process RDL layers. At this point, the designer just needs to design the Flip Chip substrate. If IC chips are not specifically developed for Flip Chip but only support the Wire Bonding process, RDL layers need to be designed and processed. This chapter introduces the design of RDL layer and Flip Chip in Xpedition design environment through a practical design.
13.3.1 Build Bare Die and RDL Library First of all, in Xpedition environment, the Bare Die and RDL layers, as well as the BGA Package, need create corresponding Cells. From the packaging structure, Bare Die Cell and RDL Cell are placed on the top of the substrate, while BGA Cell is placed on the bottom of the substrate, signal pathway from Die Pad → RDL Layer trace → RDL Pad → Packaged Substrate trace → BGA Pad, as shown in Fig. 13.6. A 3D view of the positions of Bare Die Cell, RDL Cell, and BGA Cell on substrate is shown in Fig. 13.7.
Fig. 13.6 Bare die cell, RDL cell and BGA cell positions on substrate (side view)
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Fig. 13.7 Bare die cell, RDL cell, and BGA cell Locations on substrate (3D view)
Once you have identified the cells that need to be created and their locations, you need to determine the shape and size of the RDL Padstack, which is determined by the number of Die Pads, the area of the chip, and the support capabilities of the Flip Chip process. In this example, a 150um square Pad is chosen as the RDL Pad and named DIE150um_FC, Pin type is chosen as Pin-SMD. For IC Die itself, you also need to create a Pin-SMD type Padstack. In this example, DIE62um_FC is created as IC Die Padstack. After creating RDL Padstack and Die Padstack, the next step is to create Bare Die Cell and RDL Cell. One thing to note here is that the Underside space property value of Bare Die Cell is larger than RDL Cell, as shown in Fig. 13.8. In this way, in the component layout, Bare Die Cell and RDL Cell can be placed on the same layer without DRC conflicts.
Fig. 13.8 Bare die cell and RDL cell property settings
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Fig. 13.9 Created bare die cell and RDL cell
After properties set up, Die Cell can be created from data provided by the chip manufacturer. As described in the previous section, you can import the data files through Die Wizard (see Chap. 7, Establishment and Management of Central Library for details). RDL Cell is created similarly to BGA. In this example, the created Bare Die Cell and RDL Cell are shown in Fig. 13.9. After Cell creation, schematic symbols need to be created. If the number of pins of Bare Die Cell and RDL Cell are exactly the same, the same symbols can be used. Symbols are also created with reference to Chap. 7. Once the symbols are created, you can create IC DIE Parts and RDL Parts and map the corresponding Symbols and Cells, and the Mapped Parts can be applied to the RDL design.
13.3.2 RDL Schematic Design RDL schematic design is very simple, just select RDL Parts and IC DIE Parts to place in the schematic. In this example, the number of pins for RDL Part and IC Die Part are identical, so the same schematic symbol is used so that the pin names for both symbols are identical. When designing schematic, you only need to place RDL Part and IC DIE Part in schematic with the Add Nets and Add Net Names options selected. The net names generated by the pin names are identical, automatically connected, and no manual connection is required. The completed schematic is shown in Fig. 13.10. After the schematic design is completed, review the design and run packager, after which we can enter RDL layout design environment.
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Fig. 13.10 Completed RDL schematic design
13.3.3 RDL Layout Design In layout design environment, the first thing need to do is set up the RDL layer stackup, because the RDL design only requires one layer in this case, so the layer stackup can be set as shown in Fig. 13.11. The thickness and parameters of the specific layer can be adjusted according to the actual situation. Setting here will not affect the production and processing, but will affect the calculation of parameters such as transmission line impedance, and will also affect the results of subsequent software simulation. Then, carry on with device layout, both Bare Die Cell and RDL Cell are placed at the top layer of the substrate, because the Underside Space property (30 um) of Bare Die Cell is larger than the Height property (20 um) of RDL Cell, so they can be placed at the same position without conflict even if the Cells overlap, as shown in Fig. 13.12. When the cell placement, open the net line, you can see that because the location information of the pins is not taken into account in the schematic design, the net
Fig. 13.11 RDL layer stackup setting
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Fig. 13.12 Bare die cell and RDL cell placement (local)
connection relationship is very intertwined and cannot be routed at all. As shown in Fig. 13.13, the net connection relationship needs to be optimized. First, in Xpedition design environment, menu select Setup → Part Editor → Pin Mapping to set all pins of the RDL Part swappable. The specific operation method is as follows: First select the pins that need to be swapped, we can select multiple adjacent pins by holding down the key, Fig. 13.13 Net connections before auto-optimization
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or holding down the key to select non-adjacent multiple pins, then click the , the same group of swappable pins shows the same Set pins swappable button shape, as shown in Fig. 13.14. In this example, all pins of an RDL part are set to the same group of swappable pins, then menu select Place → Automatic Swap → Swap by Part Number. Select to place the the part that needs to be pin optimized, use the arrow to the right part to the Included bar on the right side, in Swap items, select Pins and then click the Apply button, the software starts automatic pins optimization. Depending on the size of the chip and the number of pins, the time for automatic pins optimization o will also vary, usually it takes a few minutes to complete. After the completion of net optimization, we can see the percentage in Savings bar and Total Savings bar, which can be understood as the savings of routing space. This example saves 38.27%, as shown in Fig. 13.15.
Fig. 13.14 Set RDL part all pins swappable
Fig. 13.15 Automatical net optimization interface
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Usually, after automatic optimization, the connection relationship of the net is relatively smooth, but it is difficult to achieve a perfect state. The rest of the net needs to be manually optimized by the designer according to the actual design situation. In route mode, click the Swap Pins button to swap pins manually and follow the instructions in the status bar located at the bottom left of the window. First, the to select one of the pins of RDL Cell that status bar prompts needs to be swapped, at this time, all swappable pins will be highlighted, the status , select one of the suitable pins, and bar prompts change to . Simply click the left mouse button the prompt information becomes anywhere in layout to complete the pin swap function, as shown in Fig. 13.16, where the net lines change from crossing to parallel. By comparing the results of Fig. 13.17 automatic optimization with those of manual optimization, we can see that after the completion of automatic optimization, the connection relationship have been greatly improved comparing with initial net connection, but there are still some net crossings. On the basis of automatic
Fig. 13.16 Optimize net connection by manually swap RDL cell pins
Fig. 13.17 Automatically optimized net connection and its manual counterpart
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˄a˅Use back Annotaiton button
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˄b˅Use ECO menu
Fig. 13.18 Two ways for back annotation
optimization, using manual optimization through pin swap function, the optimal net connection can basically be achieved. Net optimization, whether automatic or manual, is essentially to swap the swappable pins. After the completion of Net optimization, the results of the swap need to be back annotated to the schematic to make the synchronization of schematic and layout. There are two ways of back annotation: (1) using the Back Annotation button located in the Setup → Project Integration window. When the project need back annotation, the button turns orange and the text behind the button prompts Back Annotation Required. Click the button for back annotation. (2) Select the menu ECO → Back Annotate, as shown in Fig. 13.18. After the completion of back annotation, a prompt window will appear to confirm the success of back annotation. Comparing the schematic before and after back annotation, we can see that the pin mapping relationships have changed, the pin names remain unchanged and the pin numbers are updated, so as to achieve a reasonable net distribution in layout. This rationality is unpredictable at the schematic design stage, so it is only achievable through physical connection optimizing in layout and then back annotation to the schematic. A comparison of the pin mapping of the schematic before and after back annotation is shown in Fig. 13.19. After the completion of net optimization, set up the route rules in CM (Constraint Manager), which mainly includes the trace width and clearance of RDL layer (the methods refer to Chap. 10 Management of Design Rules). After the rules setting, we can start auto route and manual route, usually, the effect of manual route is better and can get more reasonable results. The 45° route function can be turned on or off either in manual or auto route. In Setup → Editor Control → Route → Plow → Angle for Segment Plow style, we can choose 90°, 45° or Any angle route function. Selecting 90 and 45° gives the following two different route results, as shown in Fig. 13.20. After routing, layout DRC check is required. Detailed methods of DRC check can be found in Chap. 20: Design review and production data output. After the DRC check, the production data for RDL layer processing can be output. The production data supported by Xpedition include GDSII, DXF, Gerber, ODB++, Neutral File and so on.
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Fig. 13.19 The schematic updated after back annotation
˄a˅90 route result
˄b˅45 route result
Fig. 13.20 Comparison of two types of route results
13.4 Flip Chip Design After the completion of RDL design, we can start Flip Chip design. In RDL Design, the pins of Bare Die have been connected to the RDL Cell, in Flip Chip design the pins of the RDL Cell need to be connected to BGA Cell. It is important to note that if the IC chip manufacturer has defined the IC pin as an array suitable for Flip Chip, there is no need to design and process the RDL layer. If this is the case, we can omit the RDL design in Sect. 13.3 and start designing Flip Chip directly from this section.
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The process discussed in this chapter is the complete design flow from IC Die → RDL → Flip Chip.
13.4.1 Flip Chip Schematic Design In the same project as was used for RDL design, menu select File → New board, then right-click Rename, change the name of the Board to FC_PACKAGE, and also rename the schematic to FC_PACKAGE. Then copy RDL Symbol and its connection directly from RDL schematic to FC_PACKAGE schematic, the symbol can be renamed FC for more intuitive purposes. It is important to note that instead of calling RDL Part and Symbol directly from the central library, we copy RDL Symbol from RDL schematic to FC_PACKAGE schematic, mainly because the RDL Symbol must inherit the pin mapping relationship that has been optimized in the previous RDL design. Then, call the corresponding BGA Package Part from Central Library and place it in the schematic with the Add Net and Add Net name options checked. If the net name is the same with FC symbols, its net will connect automatically. If there are newly added nets on BGA Package, such as redefined power supplies and pins, we need to manually add the nets and net names. As shown in Fig. 13.21, there are three designs under the FLIPCHIP_DESIGN project, namely RDL design, FC_PACKAGE design and PCB_Board design, representing three levels from chip (RDL) package (FC_PACKAGE) and PCB (PCB_Board). There are schematic and pages below the design. If we have alternative designs in project, we can put them in block, copy their contents into a schematic
Fig. 13.21 The project include 3 designs and related schematics
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Fig. 13.22 FC_PACKAGE substrate via setup and the completion of placement
if needed, or convert them to a new design by right-clicking the command Create Board. Note that, as with the previous RDL design, only connections from FC to BGA Package are made in the schematic, and their connections need to be optimized in Xpedition as well. After the completion of schematic design and review, Package the schematic, then go into the Xpedition layout design environment.
13.4.2 Flip Chip Layout Design In Xpedition, the first step is to set the substrate layer stackup and via span definition. The BGA substrate is set to 4 layers with 1 + 2 + 1 layer stackup. The via span definition is set as shown on the left side of Fig. 13.22. The middle layer is Laminate process and the surface layer is Buildup process. After the setup, adjust the board outline size to be the same as the BGA Cell size, and set the Board Original to the center of the substrate, then place the parts. Because there are only two parts, it is relatively simple. FC Cell is placed on the top of the substrate, BGA Cell is placed on the bottom of the substrate, and the origin is set to (0, 0). When the placement is finished, the result is shown on the right side of Fig. 13.22. After the completion of placement, enter Constraint Manager to set up related design rules, including physical rules such as trace width, clearance, and electrical rules such as equal length and differential pair, as shown in Fig. 13.23. For specific setup methods, please see Chap. 10. Once the rules are set up, we can enter the route process. Before route, net optimization should also be done, which is the same as the RDL layout design described above in this chapter. First, in Setup → Libraries → Part Editor → Pin Mapping, all pins of the BGA are set to swappable. Note that the Flip Chip pins need to be set to unswappable at this time.
Fig. 13.23 Setup route rules in constraint manager
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Fig. 13.24 Comparison of net connection before and after automatic optimization
Then, start Place → Automatic Swap → Swap by part number, place the BGA Parts that need pin optimization on the right side of the window, set Swap items to Pins, click the Apply button, and the software starts pin optimization. Depending on the number of pins and the strength of the computer performance, the time for net auto-optimization will also vary. After the automatic optimization is completed, the connection relationship of the net is basically smooth, but it is still difficult to reach a perfect state. The remaining part needs to be manually optimized according to the actual situation of the design. Figure 13.24 shows a comparison of net connections before and after automatic optimization. You can see that most of the net intersections are optimized, but there is still room for improvement in some areas. If the result of optimization is not completely satisfactory, manual optimization can be carried out, and the designer can swap the pins of BGA according to the preconditions such as local net connection and manual route strategy. Refer to the RDL design section above in this chapter for specific methods of pin swap. After the completion of net optimization, start the route. We can choose auto route and manual route. Usually manual route will get better and more reasonable results. Whether it is manual or automatic, we can choose 90 or 45° route function, which is the same as the previous RDL design. In this example, an auto route method is used and a 45° route is selected. Menu select Route → Auto Route, the Auto Route window pops up, select the corresponding auto route pass options, click the Route button to start auto route. During the auto route process, the number of open nets, the route percentage, and the number of vias are all updated in real time, as shown in Fig. 13.25.
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Fig. 13.25 Start auto route
When each pass type finishes in auto route, the check item in front of the pass type will be removed automatically. After the completion of auto route, the number of open nets, route percentage and the number of used vias are no longer updated. If auto route is not 100% complete, the net connection needs to be further optimized or completed by manual route. Figure 13.26 shows the end of auto route. In this example, the completion rate of auto route is 99.2%. The remaining four nets are not connected and can be completed by manual route. Figure 13.27 is the layout after auto route, showing 2D view and 3D view, respectively. The left side of Fig. 13.28 shows a 3D view of the Flip Chip area. The elements we can see include FC Pad, surface layer trace, inner layer trace, 1-2Via, 2-3Via, and so on. We can intuitive see how the route passes through the vias to other layers from
Fig. 13.26 Auto route completion status
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Fig. 13.27 2D view and 3D view after route completion
Fig. 13.28 3D view of flip chip area and BGA area
the 3D view, and we can visually check the vias and layer stackup setting. The right side of Fig. 13.28 shows a 3D view of the BGA area, which is rotated to the bottom of the substrate to view the BGA Pad, the Bottom layer trace, the inner layer trace, and the Via in BGA Pad. Now, the Flip Chip design is almost complete. Subsequent DRC check and output of production data are required. Due to the space limitations, only the Flip Chip design process is introduced in this chapter, the plane layer copper generation and the output of production data are not discussed in this chapter. They will be described in the subsequent chapters. Because the final BGA package will be applied to the actual PCB design or placed on the PCB test board for testing. Therefore, in the same project, PCB_Board can be created, the BGA Package and its net connection can be copied to the PCB_Board schematic and the related test circuit can be added to the PCB test board design, as shown in Fig. 13.29. Design resources can be shared among multiple layouts in the same project. Finally, we can get the system structure diagram of the project designed in this chapter, the signal pathway from Die Pad → RDL layer route → RDL Pad → Package substrate route → BGA Pad → PCB board, as shown in Fig. 13.30.
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Fig. 13.29 3 layout designs in the same project
Fig. 13.30 The system structure of the project in this chapter
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Chapter 14
Route and Plane Suny Li
14.1 Route 14.1.1 Route Overview In Xpedition, Route is generally divided into three types: manual Route, semi-auto Route and Auto Route, among which manual Route is also known as interactive Route. ➀ ➁ ➂
Manual Route is a method of Route that involves Plow, placing via, and connecting to the appropriate Pad by hand. Semi-auto Route refers to part of use of Auto Route. The operations mainly include Fanout, Hug Route, Sketch Route, Reroute, Tune, Auto Finish and Gloss. Auto Route refers to the use of the Auto Route dialog box to create an auto route scheme, which is then automatically completed by the software. Auto route can be used for the entire design or part of the design.
In SiP layout design, the best solution is to combine manual Route, semi-auto Route and Auto Route. For example, the most critical Route is done by manual Route, while manual Route can be assisted by some semi-auto Route commands to speed up the Route process, followed by Auto Route to complete the remaining Route. to switch to Route mode. Menu In Xpedition, click the Route mode button select View → Toolbars → Route to open the Route toolbar, and select Toolbars → Edit to open the Edit toolbar, both of which are commonly used in Route and Plane. The toolbar can be located under a menu and can be dragged by mouse or suspended S. Li (B) Beijing, China e-mail: [email protected]
© Publishing House of Electronics Industry 2022 S. Li (ed.), MicroSystem Based on SiP Technology, https://doi.org/10.1007/978-981-19-0083-9_14
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Fig. 14.1 Route toolbar and edit toolbar
anywhere in the working window. Figure 14.1 show the Route toolbar and the Edit toolbar.
14.1.2 Manual Route In Route toolbar, click the Plow or Multi-Plow button to start Manual Route. A single Plow route when a single Pad is selected, and Multi-Plow route when multiple Pads are selected. A Plow or Multi-Plow can start from Bond Fingers, component Pads, or from any location where traces or vias already exist, as shown in Fig. 14.2. When Multi-Plow, the spacing between multiple Route can be adjusted by the and keys on the keyboard or by the soft keys located below the design window. In addition to using the plow button in toolbar to start the Plow command, you can under the design window or the keys on the choose the soft keys keyboard to start the Plow. In addition, mouse hover on elements that can be routed, such as pads, when the mouse cursor becomes a small cross with an outer frame , you can simply drag the mouse to Route.
Fig. 14.2 Single plow and multi-plow modes
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Fig. 14.3 Select route mode under plow in editor control
1.
Route Mode
There are four modes for manual Route: Real Trace/Delayed, Real Trace/Dynamic, Hockey Stick/On Click, Segment/On Click. Two modes of mouse operation: Mouse up style and Mouse drag style. Mouse up style refers to: when the left mouse button is not pressed the mouse moves which supports the above four Route modes. Mouse drag style refers to: when the left mouse button is pressed the mouse moves which supports the first two Route modes, a total of 4 + 2 Route modes combined. Switch between Route modes by selecting the key or the soft key , or by selecting a Route mode from a drop-down list in the Editor Control dialog box Plow (Fig. 14.3). (1)
Real Trace/Delayed
Select RealTrace/Delayed mode, Trace will follow the mouse cursor, although there is a push function, but there will be a delay, such as the mouse has passed through the crowded area, the following Route will start to push, if the Route goes back, the pushed line will automatically restore to its previous state. This mode will try not to push if the Route channel can be found, which can effectively protect the Route already connected. When the target pad is reached, it will connect automatically without clicking the mouse. This is a smarter Route mode. (2)
Real Trace/Dynamic
Select Real Trace/Dynamic mode, Trace will follow the mouse cursor, and real-time push, the push is strong and no delay, the pushed trace is also real-time update, if the Route goes back, the pushed line can also automatically restore its previous state, when reaching the target pad, it will automatically connect, no mouse click is required, belongs to the smarter Route mode. (3)
Hockey Stick/On Click
Select Hockey Stick/On Click mode, the expected traces (hollow display) will be displayed as hockey and follow the mouse cursor. After clicking the mouse, will place the expected traces and push other traces. Each step of Route confirmation requires a mouse click. When reaching the target pad, a mouse click is required to connect.
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Fig. 14.4 Comparison of four route modes
(4)
Segment/On Click
Select Segment/On Click mode, expected traces (hollow display) will be displayed as a straight line and follow the mouse cursor. After clicking the mouse, the Route will place the expected traces and push other traces. Each step of Route confirmation requires a mouse click. When reaching the target pad, a mouse click is required to connect. In addition, any angle Route needs to be done in this mode. For example, Fig. 14.4 is a comparison of the four Route modes, the white dashed circles indicating where holes can be placed. 2.
Gloss Mode
When manually Route, the router dynamically optimizes the route, removes unnecessary bends, and produces smooth traces, which are called Gloss. Gloss has three modes to choose from: Gloss On, Gloss Local, Gloss Off. Each has its own characteristics and can be switched between. During Route, you can switch between three Gloss modes by pressing the key or by pressing the soft under the design window. key (1)
Gloss On
Gloss On, which automatically removes sharp corners and bends during Route, and automatically optimizes the way trace enters the pad to ensure consistency with the Pad Entry parameter set in the Editor Control dialog box. (2)
Gloss Local
Gloss Local, a smarter mode with smoothness guaranteed. In this mode, the software can better understand the designer’s intentions, keep the bends the designer needs. If you feel Gloss On is too flexible, switch to Gloss Local mode for Route. (3)
Gloss Off
In Gloss Off mode, the Route is done exactly as the designer intended and without any push function. In Gloss Off mode, the traces laid out by Hockey Stick and Segment Route modes are semi-fixed, and semi-fixed traces are non-pushable but can be moved and adjusted by the designer (Fig. 14.5).
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Fig. 14.5 Comparison of three Gloss modes
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Fix and Lock
In the Route process, it is sometimes necessary to fix or lock the critical or special traces to avoid being pushed or deleted by the designer in subsequent Route processes. The Fix and Lock toolbox are located in the middle of the editing toolbar. They are Fix, Semi-fix, Unfix, Lock, Unlock. ➀ ➁
➂ ➃ ➄
4.
Fixed traces and vias cannot be pushed or moved, and cannot be deleted, so as to effectively protect the traces and vias. Semi-fixed traces and vias can be moved manually, but will not be pushed by other Route, playing a part role of the fixed. During the Route process, the pushing caused by other Route actions will not work on Semi-fixed traces and vias. The traces for Fix or Semi-fix can be released by the Unfix command. Lock, with the highest protection priority. Fix or Semi-fix traces can be locked, and can only be unlocked through Unlock. Locked traces cannot be Fix or Semi-fix, or Unfix. Fixed traces and vias are shown as point fills, Semi-fixed traces are shown as short line fills, Locked traces and vias are shown as unfilled void. As Fig. 14.6 shows, 1-Fix, 2-Semi-fix, 3-Unfix, 4-Lock, 5-Unlock. Layer Switch
There are several ways to switch layers when routing manually.
Fig. 14.6 Display characteristics of fix, semi-fix, unfix, lock and unlock
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Fig. 14.7 Before and after via placement
(1)
Switch by Layer Pair
During manual Route process, a white dotted circle indicates that a via can be placed here. At this point, double-click the left mouse button in this position to place the via, the Route changes to the corresponding layer, as shown in Fig. 14.7. Double-click left mouse button to place via has two preconditions: ➀ ➁
Checked in Edit Control Layer Pair Setting
Layer Pair refers to the layer that corresponds to the current layer. If the corresponding layer is not set, there will generally be no white circle, and no via can be placed by double-click the mouse command. The current layer, together with its corresponding layer, is called a layer pair. Layer pairs are set in the Editor Control, menu selection Setup → Editor Control → Route → Dialogs → Layer Settings launches the Layer Settings interface, and the layer selected in Layer Pair is the corresponding layer of the first column layer. As shown in Fig. 14.8, 1–4 makes up a layer pair, and 2P-3P makes up a layer pair. Once the layer pairs are set, the display status can be viewed through the layer pairs , located in the lower right corner status bar of the window. For example 1H indicates the current layer is 1, the default Route direction is Horizontal, 4 V indicates its corresponding layer is 4, and the default Route direction is Vertical. (2)
Switch by up and down arrows
Another layer switching method is to switch layers by the up and down arrows on the keyboard. For example, in the first layer, you can switch to the second layer by the Fig. 14.8 Layer pair setting
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Fig. 14.9 Switch layer by clicking on the route layer with the mouse
down arrow, then to the third layer by pressing the down arrow again. Similarly, you can switch from the lower layer to the upper layer by the up arrow, and so on. Please note layers that do not allow Route to be switched up or down are automatically avoided. (3)
Switch to Any Layer
If the designer wants to switch to any layer randomly during the Route process (excluding layers where Route is not allowed), he can open the Display Control dialog box. During the Route process, click on the layer that needs to be switched to with the mouse, the software will automatically place the hole and switch to the layer, and continue Route in the new layer. This switching method is not restricted by the Layer Pair, and has strong ability to push vias and traces, such as Fig. 14.9 shows. 5.
Move Traces and Vias
When move traces and vias, you need to be in Route mode, but not under Route commands, but under selection commands, the status bar in the lower left corner is shown as Select, and the mouse cursor is a small cross without an outer frame Select the trace or via and hold down the left mouse button, then move the mouse, then the trace and via will be moved, except for the Fixed or Locked trace and via. If there is no Semi-fix, Fix or Lock in the surrounding trace or via, it will be pushed away automatically. When moving a trace, you first select the trace. When you click on the trace with the mouse, you can select a straight trace segment that connects with the click position. If the designer wants to select a specific part of the trace, he can first select the position of the starting point by clicking the left mouse button, and then select the position of the ending point by clicking the left mouse button again, then the middle segment of the two points is selected, such as Fig. 14.10 shown. When selected, the trace can be dragged to move. Only the selected part will be moved, while the rest will remain unchanged. During the move, the mouse cursor is a small cross with an arrow .
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Fig. 14.10 Select trace with one and two mouse clicks
14.1.3 Semi-auto Route Some commands or operations between manual Route and Auto Route are called semi-auto Route, such as Fanout, Hug Route, Sketch Route, Reroute, Tune, Auto Finish, Gloss, etc. When using semi-auto Route, select elements such as nets, pins, vias, etc., and then start semi-auto Route through the buttons on toolbar. 1.
Fanout
First select a set of Pads, then click the Fanout button , the software automatically fans out and adds vias if the rules are met, as shown in Fig. 14.11, the left side selects the Fan out Pad, and the right side performs the Fan Out result. 2.
Hug Route and Sketch Route
Both Hug Route and Sketch Route are intelligent semi-auto route modes. Select the nets that needs to route, then click the Hug Route icon to execute Hug Route , select the nets that needs to route, and then click the Sketch Route icon to execute Sketch Route . The results are slightly different, as shown in Fig. 14.12, Hug Route effect on the left, Sketch Route effect on the right. and UnPacked In addition, Sketch Route can use Sketch Route Style Packed to define the routing path, which is more in line with the designer’s intentions. The operation method is as follows:
Fig. 14.11 Effect of Fanout command
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Fig. 14.12 Effect of hug route and sketch route commands
Fig. 14.13 Sketch route style packed path drawing and route effects
First select the net line, then draw the sketch route with , then double-click the mouse or execute the route, Fig. 14.13 draws the path and effect for Packed mode. , then double-click First select the net line, then draw the sketch route with the mouse or execute the route, Fig. 14.14 draws the path and route effect for UnPacked mode. It is also important to note that the default layers for the selection and route is the current layer, whether Hug Route or Sketch Route. If you need to change the Route layer, you need to change the current layer. 3.
Hug Trace and Multi Hug Trace
The Hug Trace and Multi Hug Trace functions are set up for special types of traces, such as the consistency of Route shape and structure shape that is often required in flexible circuit design, where This Route mode can be used. Hug Trace can only generate one Route at a time and Multi Hug Trace can generate multiple Route at a time. The following methods are used: Click the Hug Trace button , select the net, then click on the start point location, the software will identify “✕”, then click on the end point location, the software will again identify “✕”, then click on the mouse on the side of the reference path, Hug Trace will be placed on the side of the mouse clicked and exist in a semi-fixed state, as shown in Fig. 14.15.
Fig. 14.14 Sketch route style unpacked path drawing and route effects
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Fig. 14.15 Hug trace reference path assign and route effect
Fig. 14.16 Nets assign and route effects of multi hug traces
Click the Multi Hug Traces button , the Multi Hug Traces dialog box pops up, check Graphical net name selection, and then select the net with the mouse (usually the selected net should have its pads arranged in a row), click the Apply button, then click on the starting point location, the software will identify “✕” and then click on the ending point location, the software will identify “✕” again, then click on the mouse on the side of the reference path, Multi Hug Traces will be placed on the side of the mouse clicked and exist in a semi-fixed state, as shown in Fig. 14.16. 4.
Teardrops Generation
Teardrops are often used in the design of SiP substrates to enhance the Route strength of the pad and reduce stress concentration. Click the Teardrops button to launch the Teardrops window, which has three TABs. Pad Teardrops TAB controls the teardrop setting of the pad, Route Teardrops TAB controls the teardrop setting of the Route, and Multiple Via Teardrops TAB controls the teardrop setting between multiple vias, as shown in Fig. 14.17. Among Pad Teardrops TAB, Pad to trace is the most common and can be set to the length or scale of the Teardrops, because the speed of Teardrops generation is very fast, you can try many parameters to get the best Teardrops and gradually develop your own design rules. For example, Fig. 14.18 is a comparison of the layouts without teardrops and the two with teardrops. It can be seen from the figure that teardrops enhance the reliability of the connection points and do not require as high drill alignment accuracy as the layouts without teardrops to avoid possible quality problems. Trace Teardrops TAB mainly controls the strengthening of the connection between the bifurcation lines and the smoothing excess between the line widths. As shown
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Fig. 14.17 Three TABs of the Teardrops window
Fig. 14.18 Comparison of no-teardrop pads and teardrop pads
in Fig. 14.19, the left figure shows the lines without teardrops, the middle one is the parameter settings for generating Route teardrops, and the right one is the effect after generating Trace Teardrops.
Fig. 14.19 Comparison of the fork route without teardrops and with teardrops
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14.1.4 Auto Route Xpedition can automatically route the entire design, specific areas, some nets, special nets, etc. Auto Route can be started at any time during the design process. Auto Route can be used independently or interactively with manual Route. The auto route algorithm is basically the same as that in the semi-auto route and manual route commands. When routing automatically, different routing methods can be set up to achieve better results in less time. Menu select Route → AutoRoute, or click the Auto Route Tool button to start the Auto Route window, as shown in Fig. 14.20. The options for each column of the auto Route window are described one by one below. ➀ ➁ ➂
➃ ➄
Pass Selection Box, check to launch this Route type. Pass Types, including Fanout, No Via, Route, Via Min, Tune Delay, Tune Crosstalk, Smooth, and so on, can be selected from a drop-down list, designers can create new Pass Types or delete existing Pass Types. Items to Route allows you to select all elements in your design for Auto Route, or some elements for Auto Route. There are many types to choose from. When the designer chooses Nets as the auto route type in the first Pass, the window shown on the left side of Fig. 14.21 pops up automatically. When the designer chooses Parts as the auto route type in the second Pass, the window shown on the right side of Fig. 14.21 pops up automatically. Nets or Parts that need auto route are placed in the Included bar on the right side of the window, and the auto route is only valid for Included Bar elements. Order, which mainly includes automatic selection, longest priority, shortest priority, or designer-specified. Effort, routing algorithm, the size of the number represents the complexity of the routing algorithm, the larger the number, indicating that the higher the
Fig. 14.20 Auto route window
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Fig. 14.21 Select nets and parts that need auto route
➅ ➆ ➇ ➈
complexity of the algorithm, the higher the routing rate, and the longer the routing time. Start, End, Now represent the beginning, end and current routing algorithm complexity, respectively. Layers, the designer can choose in the pop-up window whether to route automatically in all layers or only in some layers. Via Grid, Rte.Grid indicates the grid used for vias and Route, Default indicates that the same grid is used for manual Route, that is, Grid set in Editor Control, and None indicates grid-free Auto Route. Fix, indicating whether the Route is automatically Fix after the current Route type is completed, and the Fix option can also be used to unfix the traces that are fixed before the current Route type starts. Pause indicating whether to pause after the current Pass Type auto Route is complete.
After the setup is completed, click the Route button, and the system will start the Auto Route. During the Route process, the lower status bar will also show the Route rate, the number of opens, the number of vias, etc. in real time until all Pass is completed. At present, Auto Route cannot achieve satisfactory results, but the effect of different Route strategies can be analyzed by the Route rate and results of Auto Route. It can also be used to evaluate the effect of layout and net optimization. If the Auto Route rate is low, the layout and net optimization are not good enough, and need to continue optimization, or increase the number of layers of Route. Otherwise, even full manual Route will not eventually get through, so the design strategy needs to be adjusted in time to avoid unnecessary manual waste and ensure the progress of the project.
14.1.5 Differential Pair Route Differential Signal is widely used in high-speed circuit design. Differential signal has strong anti-jamming ability, can effectively suppress EMI and accurate sequence
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positioning, and is favored by circuit designers. LVDS (Low Voltage Differential Signaling) technology is currently used in circuit design. Differential signal Route is also common in the design of SiP substrate. A pair of differential signal Route is often called Differential Pair. The following describes how to set up and Route a differential pair in Xpedition. First, let’s learn how to set differential pair in schematic. In the schematic design environment Designer, select a net, such as DIFF1_N, and in the Properties property bar, set the Diff Pair property value to DIFF1_P (you can select the DIFF1_P net in the drop-down list), then, switching to the DIFF1_P net, you can see that the Diff Pair attribute of the DIFF1_P net is automatically added as DIFF1_N. So far, the differential pair setting in the schematic is complete, as shown in Fig. 14.22. Then, let’s learn how to set up differential pair in CM (Constraint Manager). CM supports manual or automatic setup of differential pair. The two setup methods of differential pair are described below. (1)
Set differential pair manually
In CM, select a pair of nets that need to be set to a differential pair, then click the in the toolbar to set the differential pair. If you Selected Nets Diff Pair button want to remove the set differential pair, select the differential pair name, then click in the toolbar, and the system automatically pops the Remove Diff Pair (s) button up a prompt box asking if you want to remove the differential pair. After clicking Yes, the differential pair is removed, as shown in Fig. 14.23. (2)
Set differential pair automatically
If the number of differential pair is large in the design, the method of automatic setting of differential pair can be used. In CM toolbar, click the Auto Assgin Diff Pairs button , enter a differential pair wildcard in the pop-up window, such as
Fig. 14.22 Set up differential pair in schematic
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Fig. 14.23 Manually setting and removing differential pair in Constraint Manager
‘*_N’ and ‘*_P’, and then click the button to automatically select the net that meets the criteria and place it in the list below the window, as shown in Fig. 14.24. After clicking the Apply button, the system automatically completes the differential pair setting, as shown in Fig. 14.25. Once the differential pair is set up, the differential Route can be done in the Xpedition layout design environment. Select any net in the differential pair, and the system automatically selects its corresponding differential net. The two nets are routed together, and their spacing meets the differential spacing rule set in CM. The differential pair net that completes the Route is shown in Fig. 14.26. This book only briefly describes differential pair Route, which can be set up in more detail in Xpedition and CM. Due to the length of the book, the settings for Fig. 14.24 Set up differential pair automatically in CM
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Fig. 14.25 Differential pair auto-set complete
Fig. 14.26 Differential pair route effect
differential pair are no longer detailed. Refer to the help documents of Xpedition and CM.
14.1.6 Length Control Route In SiP layout design, if high-speed circuit design is involved, it is often necessary to make length control Route for high-speed signal net. For example, a set of signal Route needs to be as long as possible, or the Route length of the whole set of signals needs to be limited to a certain length range, such as 30000 um ± 2%. The general practice is as follows. The first step is to set up the length rule in CM. In this example, the minimum length of Min (um) is 29400 (30000–2%) and the maximum length of Max (um) is 30600 (30000 + 2%) for HS01-HS06 high-speed net, as shown in Fig. 14.27. Designers need to be aware that since all nets are limited to the maximum and minimum lengths, there is no need to set the Match property for the matching group
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Fig. 14.27 Set up length rules in CM
of nets. If you only need to set the length of a set of high-speed nets without limiting the length range, you can do this by setting the entire set of nets to the same matching group (the Match column has the same value). The second step, exit CM after setup is complete, and the set rules are automatically updated into Xpedition, then set the high speed route rules in Xpedition environment. In Editor Control, select the menu command Route → Dialogs → Tuning and pop up the Tuning Patterns window to set the tuning rules. The tuning rule options are divided into four main categories: Tuning pattern rules, Diff pair balancing, Tuning iterations, and AutoTune options. Detailed settings can be made for how the traces are tuned, as shown in Fig. 14.28. Fig. 14.28 Tuning rules setting
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Fig. 14.29 Comparison of Arc tuning and non-Arc tuning
Each setting of the tuning rules has a different effect on the result of tuning. For example, when the Use arcs option is selected, arc corners are automatically used when tuning traces; When the Use arcs option is not selected, a 45° corner is automatically used when tuning the trace, as shown in Fig. 14.29. Use arcs is selected in the left image and not in the right image. Different tuning effects can be obtained through different combination of settings. For example, different combinations of tuning spacing, tuning height, chamfer ratio and whether or not arc is used can produce various tuning effects as shown in Fig. 14.30, which includes different tuning spacing, different tuning height, variable height tuning, arc tuning, differential tuning and so on. Designers can set up the appropriate parameters to achieve the desired results. Once the tuning rules are set up, the tuning can be done. There are three methods: automatic tuning, interactive tuning and manual tuning. Automatic tuning starts with Tune Delay Pass Type, and nets that require Route, such as HS01–HS06. When the setup is complete, click the Route button, and the system will begin to Route and tuning automatically. Depending on the tuning settings, there will be different tuning results. Figure 14.31 shows the results of two automatic tuning methods, serpentine and trombone.
Fig. 14.30 Tuning effect under different settings
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Fig. 14.31 Automatic tuning results of serpentine and trombone
Interactive tuning is done by selecting a net that has already been routed (you can select a single or multiple traces at the same time), then clicking the Tune button , the system makes interactive automatic tuning, which is equivalent to automatic on tuning. Manual tuning is done manually by clicking the Manual Tune button a net that has already been routed. See Fig. 14.32. Designers control the tuning position and length manually. When Tuning Meter is opened, the window automatically displays the length range set in CM and the current tuning length for designers to refer to. When the length is within the set range, the tuning ruler displays green, when the length is approach the set range the tuning ruler displays yellow warning, and when the length is greater than the set range the tuning ruler displays red warning. After tuning, in order to compare the actual tuning length with the length set in CM, you can select Data → Actuals → Update All from the menu in CM to import the actual Route length into CM, as shown in Fig. 14.35. The Actual column shows the actual length of the net. If the actual length is close to the set range boundary, the bottom color of the column shows a yellow alert, and if the actual length exceeds
Fig. 14.32 Manual tuning
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Fig. 14.33 Import tuning actual length
the set range, it shows a red alert. In Fig. 14.33, Manhattan Length is the sum of the X-coordinate difference DX and Y-coordinate difference DY between the various connection points of the net. In general, the actual Route length will not exceed the length of Manhattan, whereas for tunings with limited length, the opposite may be true. Refer to Table 14.1 for an explanation of the detailed tuning rules.
14.1.7 Circuit Copy In SiP design, if there is a multi-channel design, or if there are identical or similar circuits in the design, circuit copy is usually used to save time and maintain the consistency of related circuits. The precondition for circuit copy is that there should be corresponding circuit in the schematic design, that is, it is impossible to duplicate the circuit out of void in Xpedition. Elements that can replicate circuits include component layouts, Route, plane, and even cavities. The following is an example of how to operate circuit copy in a SiP containing four circuit designs. First, complete channel 1 design, such as cavity drawing, device layout, bonding, Route and other operations, as shown in Fig. 14.34. Then, in the selection mode , use the left mouse button to select the circuit that needs to be copied, menu select Edit → Copy to Clipboard, and then select Edit →
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Table 14.1 Detailed tuning settings Tuning shape rule settings: mainly used to set tuning shape, such as tuning spacing, height, type, etc. Minimum spacing
(Only valid for serpentine tunings) Defines the minimum spacing along the trace, which can be set to a fixed value or a multiple of the trace width “x”, such as 2x, with a minimum spacing of 20 when the trace width is 10
Preferred minimum height
Define the minimum height of the tuning (only valid for serpentine tunings)
Maximum height
Define the maximum height of a tuning (only valid for serpentine tunings)
Miter ratio
(Only valid for serpentine tunings) Define the proportion of the miter at the corner and enter 0 to indicate that the proportion of the miter is automatically calculated by the software
Serpentine
Define tuning rules for serpentine Regular height, use the same tuning height when checked Irregular height, use variable tuning height when checked Prevent, no serpentine when checked
Trombone
Defines whether Trombone tunings are allowed Allow, allow Trombone tuning Prevent, no Trombone tuning
Non-Serpentine
Defines whether non-serpentine Route is allowed Allow, allow non-serpentine tuning Prevent, no non-serpentine tuning Prefer, Prefer non-serpentine tuning
Use arc
use arc corner instead of 45° corner
Allow vias in any pattern
Allow vias to be added during tuning
Prevent stairsteps
When checked, stairsteps tuning is prohibited
Diff pair balancing: mainly used to set up two traces of differential pair for length compensation Sawtooth tuning
When checked, can be used to adjust matching of length and phase between two traces of differential pair
Uncoupled tuning
When checked, add length near the load of the shorter trace of differential pair
Sawtooth length
Defines the Sawtooth length as a multiple of the trace width, with a recommended value of 3
Maximum sawtooth height
Defines the sawtooth height as a multiple of the trace width the trace width, with a recommended value of 2
Tuning iterations settings: mainly used to set tuning rules for the execution of Tune Delay Pass Type for Auto route Reduce length
Make the longest trace close to the shortest trace by reducing its length Off, prohibit reducing tuning length Low, Medium and High, defines the amount of time the Auto Router takes to reduce its length (continued)
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Table 14.1 (continued) Tuning shape rule settings: mainly used to set tuning shape, such as tuning spacing, height, type, etc. Add length
Make the shortest trace close to the longest trace by increasing its length Off, prohibit increase tuning length Low, Medium and High, defines the amount of time the Auto Router takes to increase its length
Auto tune options: rule options for automatic tuning of nets Effort
Define the scope of application for automatic tuning ReTune Only, Retune only those traces that are tuned and do not meet the rules Tune & ReTune, Tune all traces and push traces and vias
Automatic urgency
Define the correlation between the tuning option in automatic tuning and auto Route Off, Auto-tuning off, need to use Tune Pass in auto route At End of Pass, automatic tuning after Route Pass in autoRoute is completed At End of Effort, perform automatic tuning after the Auto Route completes the target area On Netline Routed, automatic tuning after Auto Route completes a net
Interactive urgency
Define the correlation between interactive tuning and interactive Route Off, interactive tuning off On Idle, start interactive tuning automatically when interactive Route is complete On Netline Routed, auto interactive tuning from the beginning of the Route While Clicking, auto interactive tuning as soon as Route stops On Drag, auto interactive tuning starts when the mouse moves while Route
Fig. 14.34 Completed channel 1 design
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Fig. 14.35 Placement complete, system prompt no corresponding circuit to place
Paste from Clipboard. The circuit that needs to be copied will stick to the mouse cursor, select the appropriate location and place it in turn until the four circuits are placed. The window shown in Fig. 14.35 appears, system prompt no corresponding circuit in the design to place. Click Cancel. The copied circuit, as shown in Fig. 14.36, has a 2D view on the left and a 3D view on the right. It can be seen that elements such as the cavities, device layout, bonding wires, traces, and vias can be copied. In addition, you can use the menu Edit → Layout Circuit Clipboard to copy in a similar way, which is also easier to use and has more options to control, such as adjustments to the reference designators, nets, and physical layers. Readers can try this on their own without further details here.
Fig. 14.36 Finished 4-channel circuits copy
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Fig. 14.37 Positive plane and negative plane
14.2 Plane 14.2.1 Definition of Plane Plane, also known as copper plane, connects the same nets together by filling with copper or other metal, and is often used for Power, Ground and nets with more connections. We can set a layer as plane layer, or draw a plane shape in signal layer. The pads and vias of the same net as plane will be automatically connected to the plane, and the pads and vias of different nets will be automatically isolated. In Xpedition, Plane is divided into positive Plane and negative Plane, as shown in Fig. 14.37. Positive Plane, plane shows the actual copper plated area after producing Gerber file. Positive plane must be used when grid plane is required around traces and bonding pads. Negative Plane, after produces Gerber file, the Plane displays the opposite image of copper plated area, i.e. where there is copper, there is no plane, negative Plane does not support grid Plane.
14.2.2 Plane Setting In Xpedition, there are two main settings for copper Plane, corresponding to the two and Plane Assignments on the right side of buttons Plane Classes Parameters the Route mode toolbar. 1.
Plane Classes Parameters
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Click the button to open the Plane Class and Parameters window, where the designer can create a custom Plane Class and set parameters for each Plane Class, as shown in Fig. 14.38. at the top Create a new Plane class by clicking the New Plane Class button of the window. Once created, parameters in this Plane class can be set, and multiple Plane classes can be created in Xpedition with different parameters. Specify the appropriate Plane Class when drawing the Plane Shape to achieve the diversity of plane. Each Plane class has three TABs, Thermal Definition TAB, Clearances/Discard/Negative TAB, and Hatch Options TAB. (1)
Thermal Definition TAB
Thermal Definition TAB is mainly used for the definition of Thermal connections, including the setting of tie legs, which can be set for via, through hole and SMD pads. When Use thermal definition from padstack is checked, if the thermal connection mode is defined in central library, it will be preferred, and if it is not defined in central library, the definition in the design will be selected. If unchecked, the connections defined here will be applied to all Padstacks connected to the plane belonging to this Plane Class, as shown on the left side of Fig. 14.38. (2)
Clearances/Discard/Negative TAB
Fig. 14.38 Thermal definition and clearances/discard/negative TAB
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Clearances/Discard/Negative TAB is mainly used for setting Plane spacing and plane Island etc. Default clearance sets the spacing between the mounting hole and other elements with plane. If the value is set differently from the spacing defined in Constraint Manager, the higher value of the two should prevail. The setting of discard plane area options is used for the treatment of isolated plane, which can help designers avoid the problems such as the generation of solitary copper, plane connected to only one pad, plane area less than certain limited areas, etc. so as to generate unexpected EMC problems. There are two modes of anti-pad and Donut for the isolation of negative pad, which can be selected according to the actual needs. Negative plane fill distance beyond route border usually requires a larger value than the distance from Route Boarder to Board Outline, as shown in Fig. 14.38b. If Negative plane fill distance beyond route border is set to 0, copper plane data will also be formed between the Route Board and Board Outline. Plane data will be spread all the way to the edge of the board, which is prone to short circuit and should be avoided in design. This does not occur if a reasonable value is set, such as 100th (2500 um) as shown in Fig. 14.39a. (3)
Hatch Options TAB
Hatch Options TAB is mainly used for hatch setting of positive Plane. If the Width of the hatch is the same as Distance, or With > Distance, the copper is solid (Metal = 100%), and when Width < Distance, the plane with meshed copper. Note that meshed copper are only suitable for positive plane and negative plane cannot generate meshed copper. Figure 14.40 shows the definition of Hatch Options TAB. When the three TABs of Plane classes and parameters are set, click the OK or Apply button, then all the settings are applied to the design. 2.
Plane Assignments Plane Assignments, as shown in Fig. 14.41, are explained in detail below.
➀
The Layer\Net column lists all the layers in the design and the plane nets contained in each layer.
Fig. 14.39 Plane data processing results with two different settings
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Fig. 14.41 Plane assignments window
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Layer Usage bar is mainly used to set the type of layer, optional types are Signal and Plane, Signal layer is Route layer, Plane layer need to specify the corresponding plane nets, such as GND or VCC. Plane Types are used to set the type of plane layer and are divided into Positive and Negative types. It is important to note that the type of the Signal layer can only be Positive. Plane Class, used to specify Plane classes, optional Plane classes are classes created in Plane Classes and Parameters, such as Default and PlaneClass_1– PlaneClass_4 classes in Fig. 14.41. Plane Data State, used to set the plane status, has three options for positive, Draft, Dynamic, and Static. It is recommended to choose Dynamic, when Plane is dynamic, it will be updated automatically in real time, no special Plane command is required. to pop up the Nets In the Add/remove nets from plane layer bar, click button window. The Excluded bar on the left side of the window is an unspecified net. The Included bar on the right side lists the nets assigned to the plane layer. The selected net can be assigned to or removed from the plane layer by a left-to-right arrow in the middle. indicates that the correIn the Use route board as plane shape bar, option sponding net is the default net for the plane layer, with the Route Border as its plane border and no additional border drawing is required. In this example, VCC is the default net for Layer 4, while other nets in the same plane layer, such as VDD and VEE, need to draw Plane Shape as their boundaries.
14.2.3 Plane Shape and Plane Data 1.
Draw Plane Shape and Generate Plane Data
Under Drawing Mode , click the Property button choices in the Property window that pops up. 1. 2. 3. 4. 5. 6.
7.
to make the following
Type is chosen as Plane Shape. Layer chooses 4P, and P represents the Plane layer. Net is selected as VDD, where the optional nets are net VCC, VDD, and VEE assigned to that layer in Plane Assignment. Obstruct type is selected as None, and if Trace or Via is selected, no Route or via placement is allowed in the Plane Shape area. The Lock option is usually not selected, and if selected, the Plane Shape is locked. The Isolate Plane option is usually not selected, indicating that this Plane Shape will automatically merge if it overlaps with a Plane shape of same net; If this option is selected, isolation will occur, indicating that this Plane Shape is an isolated Plane shape with the clearance set in Constraint Manager. Prevent Outgassing Voids, if selected, the Plane does not need Outgassing Voids.
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Plane Class, which can be selected from a drop-down list, where Inherited indicates that the Plane Shape inherits the Plane Class defined for the net in Plane Assignment.
When the setup is complete, click the button to draw the graph, and the selected net VDD will be highlighted automatically, then draw the polygon according to the design requirements. Typically, this polygon needs to contain all the VDD net points (and avoid those of other plane net), as shown in Fig. 14.42. After the Plane Shape of the VDD net is drawn, the Plane Shape of VEE net is drawn according to the same rules. Similarly, the Plane Shape of the VEE needs to contain all the VEE net points, as shown in Fig. 14.43. Since the VCC net is set as the default net with Route Border as its boundary, no additional Plane Shape drawing is required. When the plane shape drawing is finished, open Plane Data in Display Control and check the Fill/hatch option to see the actual Plane data. Because the status of Plane Data is set to Dynamic r, it is updated automatically in real time in Xpedition. Dynamic Plane data is updated in real time regardless of moving components, Route or placing vias. Figure 14.44 shows the actual Plane data of the VCC/VDD/VEE net. The VCC net is bounded by Route Boarder, which is a solid Plane. The borders of VDD and VEE are drawn by the designer and the Plane data in meshed copper (based on different Plane Class definitions). 2.
Edit Plane Shape and Update Plane Data
After the Plane Shape is drawn, if you want to modify it, you need to do it in Draw Mode. In Dynamic state, modify Plane Shape, the Plane Data is updated automatically. Fig. 14.42 Draw VDD plane shape
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Fig. 14.43 Draw VEE plane shape
Fig. 14.44 Actual plane data
There are two common ways to modify a Plane Shape: the first is to drag the border or vertex of the Plane Shape; the second method is to draw a Draw object addition and subtraction operation. first, then add or subtract graphics through The specific operation methods are as follows. First select the original Plane or , then select the graphics that need to be merged or Shape, then click subtracted (the graphics need to be drawn beforehand). The system automatically merges or subtracts the graphics and assigns the new graphics the same properties as the original Plane Shape, as shown in Fig. 14.45. In addition, vertex of Plane shape often need to be modified in design. Xpedition supports three types of vertex types: Corner, Round, Chamfer. When the vertex is selected, switch through the drop-down arrow, as shown in Fig. 14.46. For positive plane, the plating status is set to Dynamic, so after editing Plane Shape, the plane data will be updated automatically in real time. Figure 14.47 shows the effect of VDD net plane data before and after editing Plane Shape.
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Fig. 14.45 Modify the plane shape by addition and subtraction
Fig. 14.46 Three types of plane shape vertex
Fig. 14.47 Comparison of VDD net plane data before and after editing plane shape
3.
Generate Negative Plane Data
For negative Plane, since the status of Plane can only be set to Batch, after editing Plane Shape, the Planes → Generate Negative Planes command needs to be run specifically to generate negative Plane.
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Fig. 14.48 Comparison before and after negative plane data generation
After running the Generate Negative Planes command, negative plane data is normally generated without error prompts, such as disconnected errors on some nets. As shown in Fig. 14.48, the effect before and after the generation of negative Plane is compared. The thermal pad shape indicates that the pad and the Plane data are connected, while the solid pad shape indicates that the pad and the Plane data are isolated. 4.
Delete Plane Data
To delete positive plane data, first select the Plane Shape of the related net in the drawing mode and press the key directly. To delete negative plane data, click Plane → Delete Negative Plane Data, and then delete Plane Shape in Drawing Mode.
14.2.4 Generate Outgassing Voids Outgassing Voids are plane exhaust openings created in SiP substrate design, openings are created in Plane shape to allow gas to be discharged during the lamination process, avoiding factors affecting quality such as copper swell due to improper gas discharge. In Xpedition, Outgassing Voids are a special type of Plane Obstruct and can be manually modified or deleted. If designers manually modify the automatically generated Outgassing Voids, they will become regular Plane Obstruct and will no longer be affected by the Outgassing Voids dialog box. In addition, starting this feature requires support from the Xpedition Layout 301 license. Menu Select Plane → Outgassing Voids to start the Plane Outgassing Voids setup window, which is divided into two parts, left for the parameters setting, right for assignments. Figure 14.49 shows. • Outgassing voids Setup
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Fig. 14.49 Outgassing voids setup window
First, you can create a new Scheme in the Active Scheme name bar, such as VSS_Void, and then select the opening shape. There are six optional shapes, Circle, Square, Rectangle, Oblong, Octagon, and Hexagon. Each shape has its own parameters to set. Alternate shape properties mainly sets the properties of the alternate shape, avoiding the alternate Outgassing Voids when the main Outgassing Voids cannot be generated due to space and other reasons. It can be used as an alternative Outgassing Voids. Figure 14.50 shows a comparison of the two effects, with Alternate shape properties not selected on the left and selected and set on the right. Shape to shape properties are used to define the distance and location of the Outgassing Voids on plane shape, such as the horizontal and vertical distances and the horizontal and vertical offsets relative to their origin. Using this option
Fig. 14.50 Comparison of the effect of the main and main + alternate outgassing voids
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in different scenarios can dislocate the Outgassing Voids on adjacent plane layers, thereby avoiding the uneven produced by stacking a multilayer. Heuristic rules define how the software modifies the Outgassing Voids to eliminate DRC violations. Allow rotation, check this option to allow rotated placement of Outgassing Voids to eliminate conflicts. Allow shift, check this option to move the placed Outgassing Voids to eliminate conflicts. Avoid placing outgassing voids that overlap diff pair traces on adjacent layer, check this option to avoid placing Outgassing Voids in areas where overlap the differential pair traces in adjacent layers. Clearances, Plane Edge, which defines the distance between the Outgassing Voids and the edge of the Plane shape. Plane Voids, which defines the distance between Outgassing Voids and other holes of the Plane shape. • Outgassing voids assignments Different Outgassing Voids types can be specified for each plane layer. Depending on the default or named scheme, Outgassing Voids are created on the selected layer or rule area. Inherited, according to the scheme set for the layer, inherit the settings of the layer in the master or minimum, which is applicable to the rule area, and generate Outgassing Voids in the selected rule area of the layer. None, do not generate Outgassing Voids in the selected rule area or layer. If you do not want to place Outgassing Voids in the high-density rule area of the layer, you can select none. Delete outgassing voids for layer before generation option, when selected, each time the new Outgassing Voids is generated, the previously generated Outgassing Voids is deleted.
14.2.5 Verify Plane Data After Plane data is generated, the Plane data can be checked by Batch DRC. Common plane problems and solutions are as follows. ➀ ➁
Plane did not cover all related pins. Solution: Modify Plane Shape to include all necessary pins, or route manually to pins that are not included by Plane Shape. Plane island appears. Solution: Change the Discard plane area options in Plane Classes and Parameters and discard all untied areas.
Additional, for DFM design purposes, Planes that are connected only to a single Pad need to be removed, or Planes with an area less than a certain limit area need to be discarded. Or the shape of the Plane needs to be optimized so that the curve along the edge of the Plane is not too complex. These can be set in Discard plane area options in Plane Classes and Parameters to achieve optimum Plane, as shown in Fig. 14.51.
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Fig. 14.51 Batch DRC plane check items and discard plane area options
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Chapter 15
Embedded Passives Design Suny Li
15.1 Development of Embedded Technology With the development of electronic technology and the rapid increase of highspeed and high-density electronic products, the demand for miniaturization, low power consumption, high-performance and multi-function of electronic products is also growing. High-density advanced packaging and SiP technology show their importance and receive more attention. With the continuous improvement of the function and performance of electronic systems, it is increasingly difficult to lay out a large number of components on printed circuit boards, packaging or SiP substrates. With the improvement of IC chip integration and its I/O number, the number of passive components will continue to increase rapidly. By burying a large number of passive components in printed circuit board or SiP substrate, the length of the connection between components can be shortened, the electrical characteristics can be improved, the package area can be reduced, and a large number of welding points can be reduced so as to improve reliability and reduce production costs effectively.
15.1.1 Discrete Embedded Technology 1.
Embedded Through Cavity
Discrete embedded technology refers to the technology that embeds chips, resistors, capacitors, inductors and other discrete components which are usually installed on the surface of the substrate, into the interior of the substrate, so as to save surface mounting space and achieve shorter connection. S. Li (B) Beijing, China e-mail: [email protected] © Publishing House of Electronics Industry 2022 S. Li (ed.), MicroSystem Based on SiP Technology, https://doi.org/10.1007/978-981-19-0083-9_15
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Fig. 15.1 Discrete embedded through cavity
In Xpedition, discrete embedded technology is mainly achieved through a cavity, as shown in Fig. 15.1 below. Components are embedded inside substrate through a closed cavity, and the internal components are not visible after the substrate is made. This technology can be used to embed specific chips into the substrate and form a substrate or PCB with intellectual property protection. This chapter focuses on the planar embedded technology. The design method of discrete embedded technology through cavity can refer to Chap. 12 Cavity, Chip Stack and TSV design. 2.
Embedded by Parameter Settings
In Xpedition, passive devices and chips can also be embedded inside substrate through parameter settings. First, in the Setup → Setup Parameters window, select Buried Resistors & Rise Time TAB, check Allow Buried Resistors, and then the Layer Stack Center below is activated so that you can see that layers 3–4 turn yellow and can be moved by clicking with mouse. Two adjacent yellow layers represent the mirror layer, and the device is mirrored at its junction, for example, in the leftmost of Fig. 15.2, Mirror layer is 3–4. When the component is switched from Layer 3 to Layer 4 by the Push command, the component is mirrored. In the middle and right of Fig. 15.2, the mirror layers are changed to 1–2 and 5–6. See Fig. 15.2. Menu select Setup → Libraries → Cell Editor, set the Package Group of the device you want to embed to Buried type, and then you can use the Push command to embed the device into substrate. Devices Package Group that does not set to Buried type can only be switched in Top and Bottom layers by Push command. Devices Package Group set to Buried type can switch directly in turn in each layer, such as 1 → 2 → 3 mirror inversion → 4 → 5 → 6. In 2D design environment, the layer in which the device is located can be determined by the relationship between the color of the device pad and the corresponding
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Fig. 15.2 Set allow buried device and mirror layer
layer when Push is performed. In 3D design environment, you can visually see where the devices are located on the board. See Fig. 15.3, where the figure (a) shows that the devices are located on the top layer of the board before the Push command is executed. The figure (b) shows that after the Push command is executed, devices of non-Buried type are moved from top layer to Bottom layer, and devices of Buried type are moved one layer at a time. Each Push, the device moves down one layer, to the mirror layer mirror inversion is made, and then was Pushed to Bottom layer, in turn, to and back again. It is easy, convenient and quick to bury the device through parameter setting. Specific to the actual project, whether the device can be buried in all layers still needs process confirmation. In the design process, full communication with the technicians is required.
(a)
(b)
Before the push command is executed
After the push command is executed
Fig. 15.3 Place devices with buried type in different layers using push command
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15.1.2 Planar Embedded Technology Planar embedded technology refers to the combination of design and process of passive components such as resistor, capacitor, inductor, etc. by etching or printing, the resistor, capacitor and inductor are made on the surface or inner layer of the board, and then embedded into the board by lamination or buildup process to replace the passive components which need to be welded on the surface of the board, thereby improving the layout space of the active chip. (1)
(2)
(3)
Embedded Resistor Technology Embedded resistor technology usually uses high resistivity materials to make planar resistors of various shapes and different resistor values. Resistor materials include nickel-phosphorus alloy, non-metallic materials (such as carbon, graphite, diamond powder, etc.), or composite materials made of metal powder and non-metal fillers (such as silicon powder, glass powder) and resins, dispersants, smoothing agents, etc. Embedded Capacitor Technology Embedded capacitor technology usually uses dielectric film method, there are two processes, thick film or thin film, generally using dielectric materials with large dielectric constant. Embedded Inductor Technology Embedded inductor technology usually uses etched copper foil or copper plated to form spiral or bend shapes, or interlayer holes to form a spiral multilayer structure. Its characteristics depend on the base material parameters and graphical shape structure. Currently, the inductance value that can be supported is relatively small, only tens of nH, mainly used in high frequency modules.
Figure 15.4 shows the planar embedded resistors, capacitors, and inductors that are located in substrate, respectively. In Xpedition, embedded resistors and capacitors are generated by automatic synthesis tools, while embedded inductors are implemented by functions in RF design module. This chapter mainly describes the design methods of embedded resistors and capacitors.
Fig. 15.4 Planar embedded resistors, capacitors and inductors located in substrate
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15.2 Process and Materials for Embedded Passive In Library Manager, select Tools → Material/Process Editor to open the material and process editor, which has two main items: Processes and Materials on the left side of the window. Processes mainly refers to the process of generating embedded resistors and capacitors, Materials mainly refers to the material of embedded resistors and capacitors, as shown in Fig. 15.5. In Processes, supported process flows include the following. ➀ ➁ ➂
Additive Resistors, commonly used for thick-film resistor generation. Subtractive Resistors, commonly used for thin-film resistor generation. Capacitor, mainly include interdigitated, Mezzanine and Printed capacitor.
At the same time, designers can also create new processes and set different process parameters to meet the specific requirements, designers can create a variety of processes to meet different needs. In Materials, supported materials include the following. ➀ ➁ ➂ ➃
Capacitor, used to generate capacitive dielectric in embedded capacitors. Conductor, used to generate metal conductors in embedded capacitors. Insulator, used to generate insulator dielectric, such as FR4, a substrate material. Resistor, used to generate embedded resistors.
Fig. 15.5 Material and process editor in central library
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Under each type of material items, designers can create new materials and add properties related to them, such as user-made resistor materials, so as to flexibly edit and control materials with different properties.
15.2.1 Embedding Processes Under Processes, you can create multiple processes for different production lines or manufacturers, each of which includes Additive resistors, Subtractive resistors, and capacitors as shown in Fig. 15.6. Typically, the rule definitions in these processes require the involvement of processes and production departments, or before the processed are set up, designers need to fully communicate with the relevant technicians to make process specification-compliant settings. Setup rules can be applied to auto synthesis tools. 1.
Additive Resistors
Figure 15.7 shows the parameter definition window for Additive Resistors. (1)
Common TAB ➀
➁ ➂ ➃
Materials: The Material Selection Bar, which by default contains several materials from DuPont, can be customized by the designer. It is important to note that the material that can be added must have been defined in Materials and support the same process as in the current dialog. For example, Material_1 must be defined as resistor materials in materials and support the Additive Resistors in order to be added to the process at this time. Allowed forms, the allowable resistor shapes mainly include the following four shapes: Rectangle, Top hat, Folded, Serpentine, as shown in Fig. 15.8. Overglaze: Protective glaze coating, which mainly defines the size expansion of the protective glaze coating relative to the resistor material. Process parameters: Definition of process parameters which is mainly set to support processes such as laser resistance adjustment.
Fig. 15.6 Xpedition supports multiple processes
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Fig. 15.7 Common parameters definition window for additive resistors
Fig. 15.8 Four resistor shapes supported by Xpedition
• Minimum trim width: Defines the minimum adjustment width, which can be interpreted as the width of the laser beam. • Process tolerance: The process tolerance value, which defines the tolerance of the synthesized resistance and the actual resistance. If the Process tolerance value is defined as 1, the synthesized resistance is exactly the same as the actual resistance value. If it is defined as 0.8, the synthesized resistance is 80% of the actual resistance value and then adjusted to the actual resistance value by laser adjustment (cutting off the excess with a laser). • Component tolerance: Component tolerance value, usually 0% by default, is not considered in the process. If the designer defines a non-zero value, multiply this value by the Process Tolerance value to define the range of laser resistance adjustment. It is recommended that the designer keep the default value.
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• Corner effect: Defines the corner effect, which mainly defines the effect of corner fillets on the resistance value. The default value is 0.5 for additive resistor and 1 for subtractive resistor. • Process direction: The process angle which can be defined from all, 0, 90, 180 or 270 degrees. ➄
Pad/Gap settings: It mainly defines the size of metal Pad, the spacing between Pad and resistor material, and the epitaxy parameters. • Bend gap: Defines the distance between the curved part and the Pad, which is valid for two shapes, the top hat and the serpentine. • Pad overlap: Define the size of the overlapping parts of the resistor material and the Pad. • Pad length: Defines the vertical length of the Pad. • Pad extend: Defines Pad lateral epitaxy parameters (distances beyond the resistor material).
(2)
Shape Specific TAB Parameters are defined for Folded, Rectangle, Serpentine and Top hat respectively. Figure 15.9 shows the window for defining the shape parameters of Additive resistor. ➀ ➁ ➂ ➃
Min aspect ratio: Define the minimum resistor aspect ratio Max aspect ratio: Define the maximum resistor aspect ratio Serpentine gap: Define the internal spacing of Serpentine resistors Top hat Percentage: Defines the proportion of the protruding part of the top hat resistor to the entire shape
Fig. 15.9 Shape specific parameters definition window of additive resistors
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Fig. 15.10 Common parameters definition window for subtractive resistors
2.
Subtractive Resistor
Figure 15.10 shows the parameter definition window for Subtractive Resistor. (1)
Common TAB ➀
➁ ➂ (2)
Materials: Material selection bar, unlike the materials used in Additive Resistors, Subtractive Resistors is mainly used Ohmega and TICER resistance materials. Designers can also customize the addition of materials. The materials that designers can add must have been defined in material and must support the Subtractive process. Allowed forms: The allowable resistor shapes support Rectangle, Top hat, Folded and Serpentine shapes, just like Additive Resistors. Production mask: Defines the lateral size extension of the mask relative to the Pad.
Shape Specific TAB The parameter types are the same as those of the Additive Resistors shape definition, but the values are set independently. Because of the different processes, the parameter definitions and process parameter settings are different, as shown in Fig. 15.11.
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Fig. 15.11 Shape specific parameters definition window of subtractive resistors
3.
Capacitors Parameters Setting
Figure 15.12 shows the Capacitor common Parameter Definition window.
Fig. 15.12 Capacitor common parameters definition window
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Common TAB ➀
➁
Materials: Material selection bar, optional materials are capacitive materials, mainly 3 M, DuPont, Gould, Huntsman and other manufacturers of capacitive materials. Designers can also add custom materials, which must have been defined in capacitor materials. Process Parameters. • Component tolerance, 1% means that the component tolerance is±1%, and the tolerance range is between 99% and 101%. • Min aspect ratio: Define the minimum aspect ratio of capacitor. • Max aspect ratio: Define the maximum aspect ratio of capacitor.
(2)
Interdigitated & Mezzanine TAB Figure 15.13 is the parameter settings window for Interdigitated & Mezzanine capacitors, which defines the parameters for these kinds of capacitors. ➀
Interdigitated, which is shaped like the fingers of two hands crossing each other, is placed as a complete element in an electrical layer with a medium filled in the middle, as shown in Fig. 15.14.
Fig. 15.13 Interdigitated & Mezzanine capacitor parameters setting window
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Fig. 15.14 Interdigitated capacitor physical structure
• • • • • • ➁
External finger width (A), Metal A finger width. Internal finger width (B), Metal B finger width. Slot width(C), Width of gap between metals. Term width (D), Width of the metal at the end of the capacitor. Number of fingers, Number of Metal Fingers. IDC Dielectric Offset, Media offset, which is the magnification of the medium relative to the metal.
Mezzanine has a complex structure consisting of top metal, medium, bottom metal, and a drill hole. Figure 15.15 shows the physical structure of this capacitor in both the top and side views. • Pin diameter, Size of metal pad of drill hole. • Hole size, define the drill hole size. • Dielectric delta, Magnification of the medium relative to the underlying metal. • Top plate delta, Reduction of top metal to bottom metal.
(3)
Printed TAB A printed capacitor consists of two metal pins at the bottom, one of them has a larger area, is covered with a medium, and then a second layer of conductor is printed on it. One end of the conductor is above the dielectric layer, and the other end is joined with a metal pin with a smaller area. Its effective area is the
Fig. 15.15 Mezzanine capacitor structure
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Fig. 15.16 Printed capacitor setup window
area overlapped by the bottom metal and the printed conductor separated by the medium. As Fig. 15.16 shows, it is a printed capacitor setup window. • Plate 1 to dielectric delta(A), Magnification of the medium relative to the underlying metal (a pin of the capacitor). • Top plate to plate 1 delta(B), Reduction of top conductor relative to bottom metal. • Pad spacing(C), The spacing between two metals at the bottom (two pins of the capacitor). • Dielectric to plate 2 spacing(D), Spacing between dielectric and capacitor 2nd Pin. • Top plate to plate 2 overlap(E), The overlap length of top conductor and the second pin of the capacitor. • Plate 2 width(F), Length of the Capacitor second Pin.
15.2.2 Materials There are four main types of materials: Capacitor, Conductor, Insulator, Resistor, as shown in Fig. 15.17. 1.
Capacitor
The parameters to be defined in capacitive materials include material properties and allowed forms. (1)
Material Properties • Manufacture, such as DuPont, etc. • Description, describing the characteristics of the material. • Cost, the price of the material.
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Fig. 15.17 List of embedded material definitions
• Status, indicating whether the material has passed validation, includes two options, Verified and Unverified, which the designer can adjust at different stages of the design. For example, at the beginning of the design, the material type was chosen as Unverified. After the material has been validated, its type can be adjusted to Verified. • Weight, Weight per unit area of material. • Thickness, Material thickness. • Dielectric Constant, Dielectric Constant of material. • Loss Tangent, Loss Tangent of material.
(2)
For planar capacitors, thickness and dielectric constant are the most important two parameters, which together determine the capacitance value per unit area. Allowed Forms Allowed Forms, indicate the allowable capacitor types during synthesis, including the three types described above. Figure 15.18 defines the window for capacitor material parameters.
2.
Conductor
Parameters defined in conductor materials include material properties and validity of capacitor shapes, as shown in Fig. 15.19. (1)
Material Properties • • • • •
Manufacture, such as Partec. Description, describing the characteristics of the material. Cost, the price of the material. Status, material status, indicating whether the material has passed validation. Weight, Weight per unit area of material.
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Fig. 15.18 Capacitor material parameter definition window
Fig. 15.19 Conductor material parameter definition window
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• • • • (2)
3.
Thickness, Material thickness. Resistivity, Material resistivity. TCR, Temperature Coefficient. Type, Material Type, divided into Planar and Wire materials.
Valid for capacitor forms Valid for capacitor forms are mainly used to select which shape planar capacitor is valid. The optional types are Mezzanine and Printed. Insulator
The parameters defined in the insulator material are mainly Material Properties, which are divided into the following categories. • • • • • • • • •
Manufacture, define the manufacture of the material. Description, describing the characteristics of the material. Cost, the price of the material. Status, material status, indicating whether the material has passed validation. Weight, Weight per unit area of material. Thickness, Material thickness. Dielectric Constant, Dielectric constant of materials. Loss tangent, Material loss tangent. Technology, the process technology, is divided into six types: Core, Substrate, Prepreg, Screened, Additive, Subtractive.
The default insulator material in Xpedition software is only one FR4, which can be added by the designer according to the type of material actually used. By clicking the right mouse button and selecting the menu item that pops up , a new material type will be created automatically, and the designer needs to change its name that is easily identifiable. Then various parameters related to it can be defined in the insulator Material Properties, such as Fig. 15.20. 4.
Resistor
The parameters defined in the resistor material are mainly Material Properties, as shown in Fig. 15.21. • • • • • • • • •
Manufacture, a manufacturer such as DuPont or Ohmega. Description, material description, describes the characteristics of the material. Cost, material price. Status, indicates whether the material has passed validation. Weight, weight per unit area of material. Thickness, Material Thickness. Power equation, power consumption per unit area of material. Voltage handle, material resistance to high voltage. Technology, the process Technology applicable to materials, is divided into Additive and Subtractive.
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Fig. 15.20 Insulator material parameter definition window
Fig. 15.21 Resistor material parameter definition window
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15.2.3 Nonlinear Characteristics of Resistance Materials The resistivity of some resistor materials is not constant, and change with the shape of resistor, such as aspect ratio, which presents a non-linear feature. (1)
Nonlinear Resistivity Curve
When the length of the resistor material is unchanged, its resistivity tends to rise with the increase of its width. When the width of the resistor material is unchanged, its resistivity tends to rise with the increase of its length. When the width of the resistor material is fixed and the length increases, the trend of increase is to increase more quickly at the beginning (steeper curve) and then slowly (slower curve), as shown in Fig. 15.22. (2)
Nonlinear Resistance Curve
Because of the non-linearity of the resistivity, the resistor values will change with the ratio of length to width. The resistance graph can be obtained by switching from Resistivity to Resistance on the resistance curve table. With the same width of the resistor material, the resistance value increases with the increase of its length, and the rate of increase is also disproportionate for different width of the resistor material. As the width of the material decreases, it increases at a faster rate, as shown in Fig. 15.23, from the slope trend of the curve at 40th, 30th, 20th (th represents thousandth inch). For this kind of non-linear resistor material, if the area of resistance is to be calculated manually, the workload will be very large in addition to a large error. With the auto-synthesis function of the software, the work will be very easy. The software fully considers the non-linear factors of the material characteristics in the synthesis calculation, so that it can get enough accurate results.
Fig. 15.22 Nonlinear resistivity curve
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Fig. 15.23 Nonlinear resistance curve
15.3 Automatic Synthesis of Passive Devices 15.3.1 Prepare for Automatic Synthesis The process flow and material characteristics defined in central library can be updated to the local library of the design through Forward Annotation during the design of the SiP substrate. Of course, designers can also start Setup → Material/Processes Editor in the Xpedition environment to set Processes and Material in the same way as the central library. However, the settings are only valid for this design, and the settings in the central library can be applied to all designs that use the central library. 1.
Passive Device Parameter Definition
Before synthesizing, confirm the property values of resistors or capacitors that need to be synthesized, such as component type, resistance value, power consumption and other parameters, which can be input into the Part property information when the component library is built, or edited in the Part Editor in this design. Figure 15.24 defines the parameters of resistance in Part Editor, and the parameters to be defined include the following.
Fig. 15.24 Define resistor parameters in part editor
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Type, Component Type, select Resistor in the drop-down list. Power Dissipation, the actual power consumption of the resistor. VALUE (Ohm), Resistor Value. Reference des prefix, such as R, which is commonly used for resistors.
Figure 15.25 is defined as a parameter of the capacitor in Part Editor. The parameters to be defined include the following. ➀ ➁ ➂
Type, select Capacitor in the drop-down list. VALUE (F), capacitor value. VALUE (Ohm), Resistor Value.
2.
Definition of EC-RES and EC-CAP in Design Environment
1.
Check the settings of Processes and Materials before synthesizing to make sure they are set properly and the parameters are correct. Create Cells for EC-RES and EC-CAP, Copy common Cells for any two pins, such as the resistor 0402 and capacitor 0402, and set their Package group property to Buried. Create EC-RES and EC-CAP Parts, set their Types to Embedded Resistor and Embedded Capacitor, respectively, and map the Cells of EC-RES and EC-CAP to the corresponding Parts. The symbols of EC-RES Parts select any resistor Symbol, and the symbols of EC-CAP Parts select any capacitor Symbol. The above EC devices can be created in the central library, then imported into the local library, or created in the design local library, so that there will be no error reports when the schematic and layout are synchronized, and the synthesized devices will not be replaced by others.
2.
3.
4.
3.
Schematic Preparation and Layout
Before synthesis, the schematic is drawn according to the standard design process. The resistor in schematic needs to be given resistor values and power consumption parameters, and the capacitor needs to be given capacitor values. The following diagram is an example schematic, which includes capacitor C1~C4 with values of 18pF, 56pF, 100pF, 360pF; resistor R1~R12, where R1~R3 is 1K, R4~R6 is 3K,
Fig. 15.25 Define capacitor parameters in Part Editor
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R7~R9 is 4.7K, and R10~R12 is 10K. Among the three resistors with the same resistor values, power consumption is defined as follows: 1/8W, 1/4W, and an undefined power consumption. The schematic is shown in Figure 15.26. Package the schematic and forward annotate to the layout, as shown in Fig. 15.27 below, with a 2D view on the left and a 3D view on the right. Once the data is ready, the automatic synthesis of passive devices can start. First, we will do the automatic synthesis of resistors.
Fig. 15.26 Define resistor and capacitor parameters in schematic
Fig. 15.27 2D view and 3D view of layout
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15.3.2 Automatic Synthesis of Resistors Select Setup → Embedded Passives → Embedded Planner, start Planner interface, select Resistor Planner TAB, start resistor automatic synthesis main interface, as shown in Fig. 15.28, the main setup functions are described below. ➀ ➁ ➂ ➃
Graph Display Mode, select the display mode of graphics, count the number of resistors in the design, choose the percentage or R/Q display, in this case choose the R/Q display of resistors. Resistor Materials, a list of optional materials, lists the resistor materials defined in material definition. Resistance Value/Quality, the resistance value (abscissa) - quantity (ordinate) curve, can visually see the number of different resistor in the design. At the lower part of the synthesizer window you can see the resistors that need to be synthesized. In this case, they are 1 K, 3 K, 4.7 K, 10 K, some resistors with
Fig. 15.28 Resistor auto-synthesis planner interface
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the same resistance value but different power consumption: undefined power consumption, 1/8 W (0.13), and 1/4 W (0.25). Click the Optimize button at the bottom to start Optimizer, as shown in Fig. 15.29. Select all four shapes in the Resistor Forms bar, and Optimize Method selects By Area, which is area-based optimization. Then click Layers TAB to set the layers that resistor is allowed to place. Different layers can be set for different materials. The Auto-synthesis tool supports placing resistor or capacitor on any layer of the design. In the actual design, the designer chooses the layer allowed according to the process and production capacity, for example, if some processes only support the surface layer, only the surface layer is selected here, that is, production and process are considered in the design, that is, DFM (Design For Manufacture). In this example, all materials are allowed in the first and second layers, as shown in Fig. 15.30. Then return to Resistor TAB on the Optimizer interface. In the Embedded Resisto create a new optimization scheme. The system tors bar, click the New button opens the Toggle Optimizer window automatically. In this window, place components need synthesize to the right side of the window. Now three 1 K resistors will be placed on the right side, as shown in Fig. 15.31. Click OK button to return to the optimizer interface and select the different materials that are available. First, select the first material, DuPont_ EP242_ 10. The lower
Fig. 15.29 Resistor optimizer interface
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Fig. 15.30 Set the layer where the planar resistor can be placed
Fig. 15.31 Place resistors need synthesize to the right side of the window
part is yellow, failure appears in PWR handling column, and the optimize button is gray, indicating that the material cannot generate 1 K resistance within the limited area (Fig. 15.32). Next, we choose DuPont_EP242_100, which generates a Rectangle and Serpentine type resistor in both layers 1 and 2, and its Pwr Handing value is much higher than the power consumption we set, so the area of the resistor for different power consumption is the same. Here we select the Serpentine type resistance and click the Apply button (Fig. 15.33).
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Fig. 15.32 DuPont_EP242_10 material cannot generate 1 K resistor within a limited area
Fig. 15.33 DuPont_EP242_100 generates two types of 1 K resistors
Next, we choose DuPont_EP242_1000, which generates Rectangle and Folded type resistors in layers 1 and 2 and whose Pwr Handing values are far greater than the power consumption values we set, so the area of the resistors for different power consumption is the same. Here we select the Rectangle type resistance and click the Apply button (Fig. 15.34). We can also select other materials, synthesize them, and select the best one to get many types of planar resistors, as shown in Fig. 15.35.
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Fig. 15.34 DuPont_EP242_1000 generates two types of 1 K resistors
Fig. 15.35 1 K resistor synthesized from different materials
From Fig. 15.35, it can be seen that the shape and size of the resistors synthesized by different materials are different. In addition, some materials have larger Pwr Handing values and different power consumption resistors are the same. Some materials have smaller Pwr Handing values and so for larger power consumption resistors, the area synthesized is relatively large. If all materials are available, you can also select all materials at once, synthesize and select the best ones. Then, we synthesize and select the other resistors, and finally get the planar resistors shown in the figure below, where R10, R11, and R12 are placed in Layer 2 due to their large area. The synthesized planar resistors can also be directly switched from layer to layer by Push command (Fig. 15.36). In practical design, there is a case where the designer needs to return the planar resistor to the state of the discrete resistor after the automatic synthesis is completed. in the lower left corner of the Optimizer window Click the button and select the component that needs to return the discrete resistor in the pop-up window, as shown in Fig. 15.37. Then click the Apply button located below the window and look back at the layout to see that the selected planar resistor returns to its original discrete resistor.
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Fig. 15.36 Resistor synthesis complete
Fig. 15.37 Planar resistor return discrete resistor operating window
15.3.3 Automatic Synthesis of Capacitor Switch to Capacitor Planer TAB and start the main interface for automatic capacitor synthesis, as shown in Fig. 15.38. The main setup functions are described below.
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Fig. 15.38 Capacitor auto-synthesis planner interface
➀ ➁ ➂ ➃
Graph Display Mode, select the display mode of the graphic, optional percentage or C/Q display, in this example, select the C/Q display of the capacitor, and check the linear display option. Capacitor Materials, a list of optional materials, lists the capacitor materials in the material definition. Capacitor Value/Quality, Capacitor Value (abscissa)—Quantity (ordinate) curve, can visually see the number of capacitors with different values in the design. In the lower part of the synthesizer window you can see the capacities that need to be synthesized, in this case there are four: 18P, 56P, 100P, 360P each.
Automatic synthesis of capacitors is similar to resistor, and software can automatically optimize selection based on area or material preference, or manually by the designer. The software supports the three capacitor forms described earlier, while considering the selection of capacitor and conductor materials.
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In the Optimizer window, switch to Capacitor TAB, select all shapes in Capacitor Form, select all conductor materials in Conductor Material (in actual design only available material can be selected), and select By Area optimization method, as shown in Fig. 15.39. to create a new optimization scheme, place the Then click the New button capacitor need synthesize to the right side in the Toggle Optimizer interface, and click the OK button to return to the Optimizer interface (Fig. 15.40). Then select the available material in Capacitor Materials bar. First select 3M_CPly, you can see that a variety of planar capacitors are synthesized, including printed capacitors, interdigital capacitors and mezzanine capacitors. Generally speaking, interdigital capacitors have a large area and mezzanine capacitors have complex structure, so print capacitors are recommended. You can preview each capacitor by clicking the check box in front of it, then clicking the Optimize button and Apply button to use them (Fig. 15.41). Then select DuPont_EP410, and you can also see that a variety of planar capacitors are synthesized, selected through the Optimize button, and applied by clicking the Apply button (Fig. 15.42). For other capacitor materials, we can also select, synthesize and select several types of planar capacitors, as shown in Fig. 15.43. Planar capacitor is the same as planar resistor. After the automatic synthesis is completed, if the designer needs to return from planar capacitor to the state of discrete
Fig. 15.39 Capacitor optimizer interface
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Fig. 15.40 Place capacitors need to synthesize to the right
Fig. 15.41 Capacitors synthesized by material 3M_C-Ply
capacitor, click the button in the lower left corner of the Optimizer window and select the components that needs to return the discrete capacitor in the pop-up window, as shown in Fig. 15.44. Then click the Apply button located below the window and look back at the layout to see that the selected planar capacitor returns to its original discrete capacitor. Finally, let’s look at the overall effect before and after the synthesis of resistor and capacitor. The left side of Fig. 15.45 shows the state of discrete resistor and capacitor, and the right side of Fig. 15.45 shows the state of planar resistor and capacitor. It can be seen that the discrete resistors and capacitors before automatic synthesis
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Fig. 15.42 Capacitors synthesized by material DuPont_EP410
Fig. 15.43 Capacitors synthesized from different materials
occupy a large volume and can only be installed on the surface of the substrate, thus occupying a large number of effective installation area of the substrate. At the same time, discrete resistors and capacitors need to be connected to the substrate by welding, which increases the weld points, thus reducing the reliability of the system. Planar resistors and capacitors can be embedded in any layer of the substrate, thereby saving the effective mounting area of the substrate surface. At the same time, because the embedded resistor and capacitor are manufactured uniformly during the production of the substrate, directly connected to the substrate trace or copper and does not need to be welded, which reduces the solder joints, thus improving the reliability of the system to a certain extent. Therefore, planar resistors and capacitors can be selected reasonably according to the characteristics and requirements of the project to improve the adaptability of the system.
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Fig. 15.44 Planar capacitor return to discrete capacitor operating window
Fig. 15.45 Comparison of discrete and planar resistors and capacitors
15.3.4 Synchronization of Layout and Schematic After the automatic synthesis of planar resistors and capacitors, the Part Number and Cell become EC-RES and EC-CAP. Open Component Explorer to see the changes of the resistors and capacitors in the list, as shown in Fig. 15.46. The name changes of Cell and Part Number for resistor and capacitor can be back annotated to the schematic. Note that when back annotating, select the first item:
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Fig. 15.46 Part number and cell name of planar resistor and capacitor
Only extract missing library data so that the local data is not updated by the central library. When you reopen the schematic, you can see that all the Cell and Part Number of the synthesized resistor become EC-RES, and all the Cell and Part Number of the synthesized capacitor become EC-CAP, as shown in Fig. 15.47.
Fig. 15.47 EC-RES, EC-CAP properties are back annotate to schematic
Chapter 16
RF Circuit Design Suny Li
16.1 RF SiP Technology RF SiP technology, as its name implies, combines RF technology with SiP technology. RF SiP includes not only microstrip, strip line, ring inductor, cross-finger capacitor, filter, mixer and other circuits commonly used in RF circuit design, but also includes Bond Wire, Flip Chip, Stacked Dies, Cavity, embedded passive devices and other technologies commonly used in SiP design. RF SiP technology is widely used in various fields of the electronic information industry. At present, the most distinctive research and application is the physical layer circuit of wireless communication. Commercial RF chips are difficult to be implemented by silicon plane technology, and the RF integration degree achieved by SoC technology is relatively low, so the performance cannot meet the requirements. At the same time, due to the high frequency of physical layer circuits, various matching and filtering nets contain a large number of passive components, and the technical advantages of SiP are highlighted in these areas. SiP takes advantage of shorter chip interconnects for smaller size, lower power consumption, faster speed and more functionality. For example, a full-featured SiP encapsulates RF, Base Band and Flash chips in one module. In this way, when the wireless front-end analog lines need to be changed, can quickly assemble and provide appropriate functional module. RF SiP technology has gradually become the mainstream of wireless design. RF circuit design can be integrated into different design categories, including the integration of RF circuits on silicon, inside SiP, and on PCB. In this book, RF SiP technology refers specifically to the integration of RF circuit design into the inside of SiP.
S. Li (B) Beijing, China e-mail: [email protected] © Publishing House of Electronics Industry 2022 S. Li (ed.), MicroSystem Based on SiP Technology, https://doi.org/10.1007/978-981-19-0083-9_16
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On one hand, RF SiP technology can simplify RF IC chip design, shorten product development cycle and development cost. On the other hand, RF SiP technology can significantly reduce the number of components of RF unit on PCB comparing with previous products, simplify PCB design, reduce the area of PCB, and improve its reliability. For specialized RF engineers, special tools such as ADS, AWR are usually selected for RF circuit design and simulation. For Package or SiP designers, special design tools such as Siemens EDA’s Xpedition or Cadence’s APD or SiP are selected. However, if RF circuits are required in the design of the SiP substrate or Bond Wire and digital, analog and RF hybrid circuits are designed on the same substrate, ADS tools will not meet the requirements, because ADS itself does not support the design of complex SiP or Package very well and is not a specialty for complex digital circuit design. Therefore, for RF SiP design, designers need to find a design environment that combines RF technology with SiP, can design RF, digital and analog hybrid circuit schematics in a unified environment, and support layout tools such as RF, Bond Wire, Cavity, Stacked Die, Flip Chip, 2.5D TSV, 3D TSV, etc. Xpedition is currently the only design platform that can simultaneously support all the above technologies in the same environment.
16.2 RF Design Flow Xpedition is the best choice for RF SiP designers because it supports both SiP, Package and hybrid design of digital, analog and RF circuits. Flexible RF circuit design can be implemented in Xpedition. RF design data can be output to Agilent ADS/AWR for simulation and validation through RF Connect interface. At the same time, data of ADS/AWR and results of simulation can be imported to Xpedition Designer and Xpedition Layout through RF Connect interface to ensure synchronization and integrity of RF design and RF simulation data. Figure 16.1 is the flow of RF circuit design and simulation in Xpedition. RF schematic design is done in Xpedition Designer, RF Layout design is done in Xpedition Layout, RF Connect can connect with RF simulation engine ADS/AWR to transfer design data with each other.
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Xpedition Designer RF
RF Parameters
Xpedition Layout RF
Back Annotation
RF Connect
Central Library
RF Connect
RF Simulator (ADS / AWR)
Fig. 16.1 RF design and simulation flow in Xpedition
16.3 Configuration of RF Component Library 16.3.1 Import RF Symbols into Design Central Library Before RF schematic input, first configure the RF component library to import RF components from the software installation directory into the designer-specified central library. The easiest way to import RF components is through batch commands. First, write a batch file as shown in Fig. 16.2 and save it as RFCL.bat. The function of this file is to copy the parameterized RF component library from Xpedition installation directory to the Central Library currently used by the designer. The parameterized RF component path is as follows: %SDD_HOME%\standard\RF\ShapesLibrary, which is related to the installation path of Xpedition on the designer’s computer. For example, if Xpedition is installed on the D drive, the path should be changed to SDD_HOME directory under D drive. After writing the batch file, save it, and then run RFCL.bat in DOS window, the system will prompt you to copy the content and copy progress. After the copy is completed, reopen the user center library, you will see a large number of RF components under Symbols, which are fully compatible with RF components in ADS. The following is the change in the contents of the SiP_lib central library before and after running the batch command RFCL.bat. We can see that several RF_xxx partitions have been added to the Symbol directory, as shown in Fig. 16.3.
Fig. 16.2 Batch file content for importing RF component library
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Fig. 16.3 Contents change of central library before and after RFCL.bat run
16.3.2 Central Library Partition Search Path Setting After importing RF symbols to the user’s Central Library through batch command, RF symbols may not be visible in the design associated with this central library. We need to check the partition search paths of the central library. Menu select Setup → Partition Search Paths from Library Manager, open the Partition Search Paths window, check under Define Search Order on the right that symbol partitions need to be used in the schematic. Only the selected partitions are visible at schematic and can be added to the schematic design. Unchecked partitions are not visible in schematic, see Fig. 16.4.
16.4 RF Schematic Design 16.4.1 RF Schematic Toolbar After starting schematic tool designer, you need to enable RF license in the setting, select setup → settings → license in the menu, and check RF Engineer, as shown on the left of Fig. 16.5. After enable RF license, the RF tools will automatically appear in the designer design window, as shown on the right of Fig. 16.5. (1)
RF Connect
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Fig. 16.4 Select symbol partitions used in schematic
Fig. 16.5 Enable RF license, RF tools bar shows
RF Connect is used to dynamically connect with ADS, AWR and other RF simulation tools, and transfer RF schematic of Designer to ADS or AWR for simulation. During the simulation process, RF parameter adjustments are usually required to achieve optimal design results, which can also be returned to Designer via RF Connect. Figure 16.6 shows the RF Connect connections window and configuration window. For cases where both Xpedition software and RF emulation tools are installed on the local computer, the configuration can follow the default configuration. It is
Fig. 16.6 RF connect connections and configuration
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important for designers to note that the configured Port 4001 and Port Range5 needs to be consistent with the port settings on the RF emulation tool side. (2)
RF Group
RF Groups are used for the creation and management of RF groups. Designers can create a group of RF symbols with the same or similar functions based on features such as functionality. There can also be Sub-Groups under RF Groups. RF data is transmitted to RF simulation tools such as ADS in the form of RF Groups. RF data is generally generated by the Generate Schematic Data command, and then transmitted by the Send Schematic Data command, RF Group as shown in Fig. 16.7 below. (3)
RF DRC
RF DRC is used to check the RF design rules. The results of the check are displayed in the Output window. By clicking on the prompt text message with the mouse, the corresponding RF component symbols can be found and selected automatically in the schematic, as shown in Fig. 16.8 below. (4)
RF Parameters
Fig. 16.7 RF Group for data transfer between tools
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Fig. 16.8 RF DRC function and find components by prompt text
RF Parameters are used to set and adjust parameters related to RF components, as shown in Fig. 16.9 below. (5)
RF Project Setup
RF Project Setup is used to set various parameters in RF design as well as layers and nets. The units of all parameters can be selected from the drop-down list. Layer settings can import layer stackup parameters from Layout, as shown in Fig. 16.10.
Fig. 16.9 RF parameters setup window
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Fig. 16.10 RF project setup window
Changes in RF parameter unit settings in schematic are synchronously updated to RF layout design. For example, if you change the unit of RF length to µm in schematic, the setting will be passed to the layout design when Forward Annotation, and when RF Meander is drawn in the Xpedition layout, its default unit will also be updated to µm. In RF Project Setup window, if ADS Variable Handing option is selected, the software automatically checks if the relevant RF variables are handled in a way that is compatible with ADS. Frequency Range refers to setting a specific frequency range supported by RF circuit model when simulating in RF emulators such as ADS. The frequency range setting in Designer allows us to set a frequency range in RF design and transfer it to RF emulator. (6)
Substrates
RF substrates setting, in the Setup Substrates window, you can create a new Substrate or edit the properties of the Substrate, as shown in Fig. 16.11. In the Substrates Properties editing window, mouse clicks on each property, and in the status bar below, you can see an explanation of the property, and edit its values and units.
16.4.2 RF Schematic Input Next, we begin to enter RF circuit schematic in Designer. Click the button , start the DxDataBook, select CL View TAB at the bottom of the window, then select Symbol View, and in the RF_Tlines_Microstrip partition, select maclin3, mbend, mlin, mtee_ads, mrind, mrstub, and so on, and place it in the schematic, see Fig. 16.12. Placed RF Symbols in schematic and copy, arrang, net connectd, and then connect to the leftmost chip. The rightmost end is connected with three resistors in series to get the schematic as shown in Fig. 16.13.
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Fig. 16.11 RF substrates setup and edit window
Fig. 16.12 Select RF components in symbol view
Fig. 16.13 Place RF symbols in designer and connect the nets
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From Fig. 16.13, we can see that each RF component has its own parameter on the RF toolbar to open control. Select the RF symbol, then click the button the RF Parameters window to set or adjust the parameters of the RF component. The schematic includes RF parametric components, common IC bare chip, RF and verify symbol and resistor. At this time, we need to check RF DRC the general schematic respectively. After passing the check, proceed to package. to enter the layout design After the package is successful, click xpedition layout environment. After entering Xpedition interface, in setup → project integration window, follow the prompts for forward annotation, waiting for all status lights turn green, indicating that the schematic and layout data are synchronized.
16.5 RF Parameters Transfer In Xpedition, Menu Select View → Toolbars → Place to open the Place toolbar, then to open the Component Explorer window, we can see that the click the button window lists all three resistors, 15 RF elements and a chip that are input in schematic. Then, in display control, Objects TAB → RF Objects opens the RF-related display options, as shown in Fig. 16.14. Use mouse to select the devices to place them into the layout design environment. When the chip, resistor and RF components are placed, they are shown in Fig. 16.15. RF parameters set in schematic symbol can be passed to RF Cell in layout. RF Cells are automatically synthesized by Xpedition and stored in local library with the same name as RF Symbols in schematic. During Package, Forward Annotation process, RF Cells whose size and shape conform to the parameter definition of RF Symbol are automatically synthesized by
Fig. 16.14 Component explorer window and RF objects in display control
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Fig. 16.15 RF cell placed in layout
RF synthesis engine. Parameter values that control the shape and size of RF Cells are derived from the parameters of RF Symbol, as shown in Fig. 16.16. Below we will see how RF parameters are transferred through specific examples. First, check the MRND in the schematic, whose (L1, L2) parameters are (30mils, 20mils), and the RF Cell passed to the layout inherits the parameters from RF Symbol as well as (30mils, 20mils), as shown in Fig. 16.17. Then, the parameters of MRIND (L1, L2, N) are changed to (20mils, 20mils, 4) in schematic. After Forward Annotations, we can see in layout the parameters of RF Cell (L1, L2, N) are also changed to (20mils, 20mils, 4). The cell shape also changes accordingly, as shown in Fig. 16.18.
Fig. 16.16 RF symbol and RF cell can transfer RF parameters to each other
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Fig. 16.17 RF symbol passes RF parameters to RF cell
Fig. 16.18 RF parameters change in schematic are transferred to layout
Next, change the MRIND RF Cell (L1, L2, N) parameter to (20mils, 55mils, 5) in layout, then run back annotation, and check the schematic, we can see that the RF symbol (L1, L2, N) parameter is also updated to (20mils, 25mils, 5). The RF parameters are transfered from layout to schematic, please see Fig. 16.19.
Fig. 16.19 RF parameters changed in layout are transferred back to schematic
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16.6 RF Layout Design 16.6.1 RF Layout Toolbox In Xpedition, Menu select View → Toolbars → RF to open RF toolbox, as shown in Fig. 16.20. In addition, designers can use the RF menu to invoke RF tools, as well as the right-click menu to invoke RF tools. It is important to note that invoking RF tools usually requires Select Mode to be valid, while only some functions are valid in Layout, route, and Draw mode. RF toolbox can be divided into three main parts by function: RF Shape toolbar, RF Node and Segment toolbar, RF General toolbar, which are explained below. (1)
RF Shape toolbar
The RF tools in this toolbar are mainly used for functions such as rotation, X, Yaxis mirror, Meander replication, automatic distribution of RF Shape components. Operational objects include Library Shape (RF components from central library) and Mander (RF trace drawn directly in layout), as detailed in Table 16.1 below. (2)
RF Node and Segment Toolbar
The tools in this toolbar are mainly used to place Node on RF Shape and edit Meander. Operational objects include Library Shape and Mender, as detailed in Tables 16.2. (3)
RF General Toolbar
Fig. 16.20 RF toolbox
Table 16.1 RF shape toolbar function description RF toolkit
Library shape operability Meander operability √ √ Angle shape Rotating RF element Yes Yes √ √ RF element mirror with X Yes Yes axis Mirror about X √ √ RF element mirror with Y Yes Yes axis Mirror about Y √ Meander replication No ✕ Yes function Copy meander √ RF elements auto arranger Yes No ✕ Auto arranger
Function description
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Table 16.2 RF node and segment toolbar function description Rf toolkit Add edge node
Function description
Add floating node
Library shape operability √ Yes √ Yes
Meander operability √ Yes √ Yes
Add bend
No ✕
Yes
Add segment
No ✕
Yes
Add stub
No ✕
Yes
Add edge node
Add floating node Add bend Add segment
√ √ √
Add stub
Table 16.3 RF generic toolbar function description
RF toolkit Add meander
Function description Add RF meander Route RF meander
Route meander Edit RF meander Edit meander Convert RF shape
Convert conduct shape to RF shape Convert trace to RF Meander
Convert trace to meander (continued)
The tools in this toolbar are mainly used to draw and edit RF Meander in layout, as well as RF parameter setting, RF via, RF Connect operation, and so on, as detailed in Table 16.3. In addition to the tools on RF toolbar, at the bottom of the design window, there are functional soft keys, corresponding to F1–F12 on the keyboard. As the RF element is selected, the status of the soft keys changes with the designer’s operation. When designer operates on RF element, the soft keys change into sub-soft keys for further selection by designer to complete the corresponding operation command.
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505 RF toolkit
Function description Convert RF meander to trace
Convert meander to trace RF parameters & properties
RF parameters and RF properties RF clearance rules
Clearance rules RF meander entry rules Entry rules Place parametric vias Place vias RF connect
Connect with RF simulation tools
16.6.2 Three Types of RF Unit In RF layout design, RF units are divided into three types: RF Standard Shape, Meander, User-Defined RF Shape, which are described below. (1)
RF Standard Shape
RF Standard Shape refers to the RF component called from the central library, which is added to schematic in symbol form when schematic is designed, and then transferred from RF schematic to RF layout through operations such as Package, Forward Annotation, etc. The RF Standard Shape cannot be added directly in layout design. Called from the Central Library and added to the schematic, RF Standard Shape parameters can be accurately passed to layout. Adjustments to RF Standard Shape parameters can be made in the schematic and passed to the layout by Forward Annotation, or RF parameters can be adjusted in the layout and passed to the schematic by back Annotation. The transfer of RF parameters is bidirectional. (2)
Meander
Meander refers to RF traces that are drawn directly in layout and are not related to the schematic. The parameters of Meanders are not back Annotation to schematic. Each segment of Meander is a polygonal metal conductor. (3)
User-Defined RF Shape
User-Defined RF Shape refers to an RF Shape defined by designer in layout, usually composed of polygon metals. Usually, designer draws a normal graphic first, then converts it to an RF Shape by command.
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Fig. 16.21 Segment, node, and clearance in RF units
Clearance
Segment
Node
Segment
All three RF units are composed of Node and Segment and Clearance. Node acts like the pins of common components. Segment is a conductor or a metal shape, just like the body of a common component. Clearance is the distance between other conductors. The connection between Segments is achieved by Node, as shown in Fig. 16.21.
16.6.3 Draw and Edit Meander The following describes how to draw and edit RF Meander in layout. (1)
ADD Meander
Mouse click the Add Meander button , Meander Properties window will pop up automatically. The mouse cursor will also be converted to a large cross of full screen, the Meander can be drawn in design window, and the parameters in Meander Properties can be changed at any time during the Meander drawing process. The Meander Properties window is divided into three main items: General, Shapde Specific, and Serpentine Specific, each of which contains multiple attributes, as detailed in Table 16.4. When drawing a Meander, first set the current layer, and then focus on the Group to which the Meander belongs. During the drawing process, you can change the drawing parameters, such as width, corner type, Miter%, and so on, in Meander Properties window to draw many types of Meanders, as shown in Fig. 16.22 below. If you need to switch the layer where Meander is located, you can switch layers by adding a via, which can be switched by the up and down arrows on keyboard, or by the Layer Display in Display Control, which can be switched directly by mouse click, as shown in Fig. 16.23. (2)
Route Meander
If Add Meander can be regarded manual route, then Route Meander can be regarded as semi-automatic route, only the starting and ending points need to be selected. The
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Table 16.4 Meander properties values and meanings Meander properties name
Properties values and meanings
General
Group
The RF group to which the meander belongs to, through drop-down arrow list all RF groups in the design. In addition, inherit indicates that the meander inherits the RF shape group connected to it; Mouse select, meander has the same group as the shape selected by mouse
Mode
Mode selection, available in segment and serpentine
Snap angle
Define an angle that can be offset by an integer multiple of that angle
Strip type
Type selection, microstrip line and stripline options
Meander name
Meander name, designer definable
Use smooth termination
Automatic smoothing to match terminal connections and reduce reflection
Inherit shape specifics
Inherit the properties of the selected shape (including width, layer, and so on)
Tape to target width
Gradually change the width to the target shape
Merge co-linear segments Merge collinear segments Shape specific
Width
Define the width of the meander
Corner type
Define the type of Meander corner: free radius, corner, miter, radius four types
Miter%
Set the scale value for the tangent angle when Corner type is selected as miter
Radius
Set the radius value when corner type is chosen as radius
Change scope
Define scope for shape change (Width, Corner, etc.) Local—Shape changes apply only to portions drawn after meander Global—Shape change applies to all parts of meander
Change width
Available when change scope is selected as local, taper changes gradually, step changes by step
Serpentine specific Length
Length of serpentine meanders
Slope height
Height of serpentine meanders
Gap width
Spacing between serpentine meanders
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Fig. 16.22 Draw meanders in layout
Fig. 16.23 Switch the layer where meander is located through via
system will automatically route RF Meander according to the selected parameters, as shown in Fig. 16.24, which has certain intelligence. (3)
Edit Meander
Designer can use the Editor Meander command button to edit the Meander. When editing, a dashed line prompt appears and you can drag the mouse as needed. Figure 16.25 shows a comparison of the graphics before and after Meander editing.
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Fig. 16.24 Route meander has certain intelligence
Fig. 16.25 Graphic comparison before and after meander editing
16.6.4 Create User-Defined RF Units 1
Draw and Convert RF Shape
In RF circuit design, if you need to create a special RF shape, you can first draw Conductive Shape in draw mode, then select Convert RF Shape button to convert Conductive Shape to RF Shape, such as Fig. 16.26. The converted RF Shape is placed in Active Group by default. If you need to change the group to which RF Shape belongs, you can operate in Component Explorer window. The specific method can refer to the following about RF Group operation. 2
Add Node and Generate Symbol
Fig. 16.26 Create custom RF shape
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Because all RF Shapes are connected by Node, we need to add nodes for the newly converted RF Shape. Here we add four Edge Nodes and one Floating Node for the RF Shape, then select the RF Group Suny2 to which the RF Shape belongs in Component Explorer, select Generate Library Symbol from the right-click menu, and select In Central Library from the pop-up window. There are two preconditions to remind designers: first, create RF folder in the Central Library root directory corresponding to the design to store the parameters of the RF Shape; second, create a symbol partition in the central library corresponding to the design to store user-defined RF Symbols, which are both indispensable. Then under Central Library, keep (the Central Library for this design), Partition select User_RF symbol partition, set Schematic unit, Grid spacing, and pin length in Designer settings, and clicks OK, as shown in Fig. 16.27. 3
Manage and Apply Symbol in Central Library
When RF symbol generation is complete, a prompt window pops up to indicate that the symbol was created successfully. Then, open the central library corresponding to the project and you can see that: the RF folder in the root directory has the file Suny2.library_element, and the User_RF partition of Symbol has the symbol Suny2 under it. It has a figure similar to the layout customization shape and has five Pins, as shown in Fig. 16.28. Then, right-click the menu to select Edit, adjust the symbol’s pins and shape, and save. In the new design, you can use this custom symbol just like regular RF symbols, which is added to the schematic first, and then passed shape parameters to the layout design through Package and Forward Annotation.
Fig. 16.27 Right-click menu to generate RF symbol
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Fig. 16.28 Schematic RF symbol is create automatically
16.6.5 Via Add Function In traditional circuit and RF circuit designs, various types of Vias need to be added to connect different conductor layers, such as stitched vias and vias added to RF Shape. Figure 16.29 shows the function of Vias. In the RF design toolbar, there are tools specifically for adding vias. Click the to invoke the Place Via window, which contains five TABs: Place Vias button Interactive, Stitch Contour, Stitch Shape, Radial, Array. (1)
Interactive
Interactive placement of vias means manual placement of vias. In the window, you can select the type of vias, net name, conductor layer connected to the vias, whether the vias are locked or not, DRC options, etc. Once set, click the Apply button, and then click the left mouse button on the location where vias need to be placed in the layout to place vias.
Fig. 16.29 Connect different conductor layers through Via
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Fig. 16.30 Parameterized via placement of stitch contour
(2)
Stitch Contour
Stitch Contour, that is, automatically place vias along the boundary of a design element. This design element can be an edge of RF Meander, Trace, Plane or Cavity, and placement rules, such as algorithm, distance, number of rows, spacing between vias, etc. Here we select the Interactive start/end algorithm and, when set, select the design element that needs to place stitched vias, such as RF Meander. Click Apply, select the start point, then the end point, and the software automatically places the stitched vias according to the set rules, as shown in Fig. 16.30. (3)
Stitch Shape
Vias can be placed on metal shape. First select a shape, such as Conductive Shape, select a net and via padstack, then set rules for the placement of vias in the Placement Control, and then click Apply. See Fig. 16.31. (4)
Radial
The button is used to select the location of the center point. After select this button, click the center location for vias with the mouse, set the rules in Placement Control, and click Apply. if keep the center unchanged, change the radius and number of vias, and form a concentric circle via array, as shown in Fig. 16.32. (5)
Array
Place vias in array, where button is used to select the location of the first via in the array. After select this button, click the location where the first via needs to be placed with the mouse. The position bar will automatically update to the coordinate value of the mouse click point, and then set the rules for placing vias in the Placement Control. Then, click Apply and the effect of placing vias like Fig. 16.33 shown.
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Fig. 16.31 Place vias on metal shape
Fig. 16.32 Place vias radial
Fig. 16.33 Place vias in array
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16.6.6 Introduction to RF Group RF units of the same or similar function form an RF Group. All RF design units belong to specific RF Group. In the Xpedition environment, RF operation commands are basically based on RF Groups, such as generating RF Netlist, RF Layout data, etc. In Component Explorer, RF Groups are managed and operated through a right-click menu, such as freezing RF Groups with Freeze commands. RF Group cannot be modified after freezing. At this time, any element in the group is selected and the entire group is selected, the designer can move and rotate the entire group. The frozen group cannot change the layer, add or delete elements or change its parameters. As shown in Fig. 16.34. RF Group display icon changes in different states. When a new RF Group contains no elements, its icon display status is shown on Fig. 16.35a, when a new element is
Fig. 16.34 RF group can be operated from the right-click menu
Fig. 16.35 Three display states of RF group
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Fig. 16.36 Auto arrange function
added to the RF Group, its display status becomes shown on Fig. 16.35b, and when the RF Group is frozen, its display status is shown on Fig. 16.35c. Open Group Outline in Display Control and you can see that all RF units belonging to the same RF Group are surrounded by a wireframe representing the RF Group as a whole.
16.6.7 Auto Arrange Function The Auto Arrange function is used to automatically arrange and connect RF units. Designers can select the entire RF Group at one time, and then use the Auto Arrange function to automatically arrange and connect the units within the entire RF Group. Designers can also select RF units that need to be connected, hold down the key, select the RF units that need to be connected in turn with the mouse, then click the Auto Arrange button, and the status bar will prompt: select seed to arrange selected shapes, after clicking on one of the RF units as seed with the mouse, the system will automatically connect the selected RF units centered on this seed unit, as shown in Fig. 16.36.
16.6.8 Connect RF Units with Bond Wire In RF circuit design, Bond Wire is sometimes used to connect RF units to enhance the flexibility of RF design. Here is how Bond Wire is used to connect RF units. 1.
Create rfbondpad
First, you need to create a Bond Finger named rfbondpad. Menu select Setup → Libraries → Padstack Editor. First, create a Pad Round 50 with a diameter of 50 um then specify Round 50 to rfbondpad (Fig. 16.37). 2.
Specify Bond Wire Model and rfbondpad
In the Bond Wire Parameters & Rules window, select All Parts in the Part Filter, then select RF Group, set Wiremodel and Bond finger padstack, and set the appropriate
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Fig. 16.37 Create rfbondpad
rules. It is important to note that the Bond finger padstack must specify Bond finger with rfbondpad name, otherwise there will be an error report when bonding, as shown in Fig. 16.38 below. 3.
Connect RF Units with Bond Wire
Fig. 16.38 Specify bond wire model, rfbondpad and rules
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Fig. 16.39 Connect RF units with bond wire
Once the setup is complete, the RF units can be connected with Bond Wire, which can directly link the nodes of RF units, or connect to vias or RF Meander. Figure 16.39 shows two ways of connecting through Bond Wire.
16.7 Transfer Data with RF Simulation Tools 16.7.1 Connect RF Simulation Tools Through RF Connect, RF schematic data or RF Layout data can be transferred to RF simulation tools. Current Xpedition-supported simulation tools include ADS and AWR. This book takes ADS as an example. 1.
Start ADS via mglaunch.exe
XpeditionVX supports simultaneous startup of multiple versions, such as VX.2.5, VX.2.6, VX.2.7 and other versions of Xpedition software, and can be started at the same time. This brings great convenience to the designer, but also brings new problems, such as the connection between ADS and which version of Xpedition, to solve this problem, we use mglaunch.exe to start ADS. Because different VX versions have their own mglaunch.exe files, starting ADS with mglaunch.exe will determine the connection relationship to the corresponding version. Mglaunch.exe is located in the bin folder under the installation directory. The most convenient way is to write the following batch files, define the installation paths for Xpedition and ADS, and start ADS with mglaunch.exe under the Xpedition installation path, as shown in Fig. 16.40. After writing, run this batch file to start ADS, connect to Xpedition, and transfer data 2.
ADS Configuration and Connection
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Fig. 16.40 Write batch file to start ADS
After ADS starts, first configure MentorDA_lib in ADS, select DesignKits → Manage Favorite Design Kits from the menu in ADS, click Add Library Definition File below in the pop-up window, and in the pcb_connect directory under the ADS installation directory, such as: $HPEEOF_DIR\pcb_connect\MentorDA_wdk, find the lib.defs file and select it, as shown in Fig. 16.41. When the configuration is complete, the Mentor DA menu option appears when you open Workspace in ADS, select Start MentorDA Server to start the dynamic link, click the OK button according to the default option, and when the connection is complete, a MentorDA server started prompt window appears indicating the connection is successful, as shown in Fig. 16.42. After MentorDA Sever started successfully in ADS, RF Connect can be started in both Xpedition Designer and Xpedition Layout environments, click the connect button to connect. After successful connection, “Connecting to [localhost:4001]…ok “ will be displayed in the Log bar, indicating that the connection is OK. As shown in Fig. 16.43, the connection state in schematic environment is on the left, and the connection state in layout environment is on the right.
Fig. 16.41 Configure MentorDA_lib in ADS
Fig. 16.42 Start Mentor DA Server in ADS
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Fig. 16.43 RF connect can be started in both Xpedition designer and layout
16.7.2 Schematic RF Data Transfer In the schematic tool Designer, after successful RF Connect with ADS, RF schematic designs can be passed to ADS via the right-click menu Send Schematic Data in Designer’s RF Group, as shown in Fig. 16.44 below. It is important to note that non-RF data does not currently support to transfer to ADS, so we can see that chip U1 and resistance R1/R2/R3 are not transferred to ADS. In addition, RF Symbol automatically generated by user-defined RF Shape cannot be transferred to ADS at this time. Therefore, we can conclude that current RF transmissions are based on libraries owned by both. If either party does not have a component library, it will not be transferred during the data transfer process, which requires designer’s attention.
Fig. 16.44 Transfer RF design data from schematic to ADS
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Fig. 16.45 RF schematic is transferred from designer to ADS
After the command executes, you can see in the schematic environment of the ADS that the RF design data is completely transferred from the Designer to the ADS, as shown in Fig. 16.45. By comparing Fig. 16.12 in the previous section, you can see that both RF components and their RF parameters in the schematic are accurately and correctly transferred from the Designer to the ADS Schematic.
16.7.3 Layout RF Data Transfer In the layout environment, after RF connect is connected OK, RF layout design data can be transmitted to ADS. In Component Explorer window, right-click the menu on the RF Groups you want to transfer and select Send Layout Data to transfer the RF data to ADS, as shown in Fig. 16.46. Open ADS Layout after data transfer to ADS, you can see that Xpedition RF Layout data has been transferred to ADS Layout, as shown in Fig. 16.47, user-defined RF Shape is also transferred to ADS in addition to RF library elements. Generally, Send Layout Data is used for one-way data transfer, that is, design data is transferred from Xpedition to ADS in the form of metal shape for simulation. If the parameters of design data need to be adjusted in ADS and returned to Xpedition, it is necessary to use Send Tune/Opt Data for data transfer. Due to the size of the chapter, this is no longer detailed here. Designers can refer to Xpedition and ADS-related materials.
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Fig. 16.46 Transfer RF design data from Xpedition Layout to ADS
Fig. 16.47 RF data is transferred from Xpedition to ADS
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Chapter 17
Rigid-Flex Circuits and 4D SiP Design Suny Li
17.1 Introduction to Rigid-Flex Circuits Rigid-Flex Circuits, which includes both Rigid Circuit and Flex Circuit as its name implies, is an organic combination of both and gives full play to their respective advantages. Generally speaking, rigid circuit refers to the ordinary PCB (Printed Circuit Board), which is an important carrier and component for the integration of electronic systems. Almost every electronic device, from smart watches and mobile phones to computers and communication base stations, uses PCB for electrical interconnection as long as there are electronic connections. FPC (Flexible Print Circuit), also known as flexible circuit, has attracted much attention due to its light weight, thin thickness, flexibility and folding. FPC is usually made of polyimide as the base material. It is small in size, light in weight, can bend freely, has good heat dissipation and is easy to install. It replaces the traditional PCB in many places. Figure 17.1 is the FPC used in mobile phones. Rigid-flex circuits are the combination of PCB and FPC, and can give full play to their respective advantages. The FPC is usually used as one or more circuit layers of the PCB, and then milling the bending parts of the PCB, leaving only the flexible parts. Alternatively, PCB and FPC are combined through laminating according to relevant processes. The production equipment of Rigid-Flex circuit should have the functions of both FPC production equipment and PCB production equipment when PCB and FPC are combined by related processes. Rigid-Flex circuits are relatively difficult to produce, have many details and are more expensive than ordinary PCB, so before shipment, a comprehensive quality check should be carried out, such as bending number test and bending radius and strength test. S. Li (B) Beijing, China e-mail: [email protected] © Publishing House of Electronics Industry 2022 S. Li (ed.), MicroSystem Based on SiP Technology, https://doi.org/10.1007/978-981-19-0083-9_17
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Fig. 17.1 Flexible circuits used in mobile phones
The following points should be noted in the design of Rigid-Flex circuits: ➀ ➁ ➂ ➃
The bending radius of the flexible part needs to be considered. If the bending radius is too small, it will be easy to damage. For stress concentration in bending area, circular arc routing should be used as far as possible. The structure of the three-dimensional space after installation needs to be considered. It is best to simulate it with 3D software. The optimal number of routing layers for the flexible part needs to be considered.
17.2 Rigid-Flex Circuits Design 17.2.1 Design Flow of Rigid-Flex Circuits Xpedition has dedicated Rigid-Flex circuits design module that requires the License enabling Layout301 or Layout201+ Advanced Technologies. First, let’s look at the design flow of the Rigid-Flex circuit, as shown in Fig. 17.2. From the design flow of Fig. 17.2, it can be seen that Rigid-Flex has several stackups settings, including Master Stackup and Sub-Stackups, and has the definition and settings of bending area, compared with traditional substrates. In addition, the design process requires the use of the 3D View tool to confirm the bend area, so the Rigid-Flex circuits design requires a better 3D design environment than the common substrate design.
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Design Preparation
Verify Bend areas in 3D View
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Set Technology to Rigid-Flex
Create Master Stackup
Create Bend Area
Generate Route boarder
Place and Route
DRC Check
Manufacture Data Output
Create Board Outline
Define Sub-stackups
Finished
Fig. 17.2 Rigid-Flex circuits design flow
17.2.2 Layer Type Unique to Rigid-Flex Circuits Secondly, we need to understand the specific layer types of Rigid-Flex circuits. In addition to the common layer types of common substrates, rigid-flex bonding circuits also contain layers of cover layers, adhesive layers, stiffener layers, etc. • Cover Layers Cover Layers usually require larger pads and masks to be designed so that the adhesive of Cover Layers can easily leak onto the pads. When creating a PadStack, you can define larger pads specifically for flexible area. When the component is placed in an area containing Cover Layers, the software uses the definition of the flex padstack; otherwise, the software uses the default padstack definition. Designers can also create custom shapes for Cover Layers by drawing graphics on the Customer Pad. Cover Layers can be defined in the Master Stackup or only in the Sub-stackup of flexible regions. • Adhesive Layers When defining Layer Stackup, the adhesive layers can cover the entire design or only the flexible area. By creating a filling shape on the adhesive layer to specify where the adhesive is located, you can either use subtraction to dig out unwanted shapes on the adhesive layer or integrate the adhesive layer with copper or cover layer. • Stiffener Layers Typically, a stiffener is created by drawing a shape on the stiffener layer. You can use subtraction to create an opening in the stiffener shape, and you can define the opening shape of the stiffener in padstack of mounting holes and through holes. • Specific Soldermask Layer For traditional substrate designs, the software allows only the top and bottom Soldermask layers to be defined. For Rigid-Flex designs with multiple layer stackups, you
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can define a specific Soldermask layer inside the Master Stackup with a customizable name that makes it easy to attach Soldermask to different electrical layers.
17.2.3 Rigid-Flex Circuits Design Steps 1.
Layer Stackup Definition for Rigid-Flex Circuits
Layer Stackup of Rigid-Flex circuits contains a Master Stackup and several Substackups. (1) (2) (3)
The Master Stackup contains at least one dielectric layer and one conductive layer. There must be at least one dielectric layer between all conductive layers in Master Stackup and Sub-stackups. All sub-stackups must have a continuous conductive layer. For example, you cannot set Sub-stackups that contain only signal layers 1 and 5, you need to include layer definitions that are 1, 2, 3, 4, and 5 contiguous.
Figure 17.3 is an example of a rigid-flexible circuit Layer stackup. The rigid section contains the definition of all the layers of the flexible section. For the Layer stackup of the Rigid-Flex circuits in this example, the following considerations are required: (1) (2) (3)
2.
Signal 1, Signal 2, and Signal 5, Signal 6 are only used for routing of rigid circuit segments. Signal 3 and Signal 4 are contained in the Layer stackup of the flexible circuit segment as well as between the Rigid-Flex segments. Cover Layers extends through Rigid-Flex parts and is therefore included in both Layer stackups. Master Stackup Definition
Rigid-Flex circuits usually contain multiple circuit board outline, each of which may have specific layers or share layers to manage routing between different outlines or to simplify the manufacturing process. Master Stackup is the combination of all the Layer stackups of the circuit board outlines in the design, which needs to be set in the correct production and manufacturing order. If a designer modifies Master Stackup during layout or routing, the current design data may be deleted or invalidated. For example, deleting a layer may unintentionally delete components already placed in that layer, deleting a layer may delete existing routing, and invalidate existing through hole ranges. Therefore, layer stackup planning needs to be properly arranged in advance, and no changes are made as far as possible during the design process.
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Rigid Solder Mask Signal Layer1 Dielectic Signal Layer2
Flex
Dielectic
Cover Layer
Flex layers are included in the Rigid stackup
Signal Layer3 Dielectic Signal Layer4 Cover Layer
Dielectic Signal Layer5 Dielectic Signal Layer6 Solder Mask
Fig. 17.3 Rigid-Flex circuit layer stackup definition example
Fig. 17.4 Set design technology to RigidFlex
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Master Stackup only exists in Rigid-Flex design. In Xpedion Layout environment, menu selection Setup → Settings, in the window shown in Fig. 17.4, Design Technology can be set to RigidFlex. Master stackup is a collection of all Sub-stackups, so all the layers contained in Sub-stackups are combined to form a Master stackup. Figure 17.5 defines the Sub-stackup of a Rigid-Flex that consists of three rigid circuits connected together by two flexible circuits. Designers should note that in Layer stackup, Flex base layers are the basis for Rigid-Flex circuit connections and should exist in each circuit. From the observation, we can see that the layer stackup of Rigid circuit is basically the same, and no new layer will be added during the merging process, but Rigid and Flex layers are quite different, so when merging, just insert Flex-specific layers into Rigid layer stackups to get Master stackup, as shown in Fig. 17.6. Rigid 2
Rigid 1
Solder Mask Signal 1
Flex 1
Solder Mask Signal 1
Dielectic Signal 2
Cover Layer Adhesive
Dielectic Signal 2
Flex base
Signal 2 Flex base Signal 3
Flex base Signal 3
Signal 3 Dielectic
Adhesive Cover Layer
Dielectic Signal 4 Dielectic
Signal 4 Solder Mask
Rigid 3
Flex 2
Signal 5
Solder Mask Signal 5
Cover Layer Adhesive
Dielectic Signal 6 Flex base Signal 7 Dielectic
Signal 6 Flex base
Dielectic
Adhesive Stiffener
Flex base Signal 7
Signal 6
Signal 8 Solder Mask
Dielectic Signal 8 Solder Mask
Fig. 17.5 Sub-stackup definition of a Rigid-Flex circuit Master Stackup Rigid 1 Solder Mask Signal 1 Dielectic Signal 2 Flex base Signal 3
Dielectic Signal 4 Dielectic Signal 5
Dielectic Signal 6 Flex base Signal 7
Rigid 2
Solder Mask Signal 1
Flex 1
Dielectic Cover Layer Adhesive
Signal 2 Flex base Signal 3 Adhesive Cover Layer
Cover Layer Adhesive
Solder Mask Signal 1 Dielectic Signal 2 Flex base
Signal 2 Flex base Signal 3
Signal 3
Dielectic
Adhesive Cover Layer
Signal 4 Solder Mask
Dielectic Signal 4 Dielectic Signal 5
Signal 6
Dielectic
Flex base
Signal 8 Solder Mask
Adhesive Stiffener
Rigid 3
Flex 2
Dielectic Cover Layer Adhesive
Cover Layer Adhesive
Signal 6 Flex base Adhesive Stiffener
Signal 7
Solder Mask Signal 5 Dielectic Signal 6 Flex base Signal 7
Dielectic
Dielectic
Signal 8 Solder Mask
Signal 8 Solder Mask
Fig. 17.6 Master stackup is formed by merging sub-stackup layers
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Fig. 17.7 Define master stackup in stackup editor
After the Master stackup merge is complete, we can define Master Stackup in Xpedition, menu select Setup → Stackup Editor, define Master Stackup of Fig. 17.6 in Stackup Editor, and we get Fig. 17.7 when the definition is complete. 3.
Drawing Board Outlines and Set Sub-stackups
Because Rigid-Flex circuits contain multiple board outlines and these board outlines may overlap, some rules are required when drawing board outlines. • Rigid circuit board outines do not overlap • Flexible circuit board outlines can overlap, and the overlapping area cannot have the same layer definition • At the Rigid-Flex junction, the Rigid-Flex circuit board outine touch together, but do not overlap. Figure 17.8 illustrates the drawing rules for Rigid-Flex board outlines: Below, let’s start drawing the board outline. After drawing the shape of the board outline, we need to define the Layer stackup of the board outline, double-click the
Flex 1
Rigid
(1-2)
(1-8) Flex 2 (4-6)
a) Right
Rigid
Flex 1 (1-2)
Rigid
Flex 1 (1-2)
(1-8)
(1-8) Flex 2
Flex 2
(2-6)
(4-6)
b) Wrong: Overlap area has common layer
Fig. 17.8 Drawing rules of Rigid-Flex circuit board outline
c) Wrong: outline cross
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board outline, set the Type to Rigid or Flex in typer bar, enter the name of the board outline in Name bar, click Customer in the Stackup bar to pop up the Stackup Layers window, and select the layer it includes. Then click View Stackup to preview the layer stackup definition of this board outline. Figures 17.9, 17.10, 17.11, 17.12 and 7.13 are the layer stackup definitions of Rigid 1, Flex 1, Flex 2, Rigid 2, and Rigid 3 of the board outlines, respectively. 4.
Generate Route Border
When the border outine drawing and the layer stackup definition are complete, we need to generate a routing border, select Draw → Generate Route Borders from the menu, and select the first item: single route border for entire design in the pop-up window, which creates a uniform routing border for all the board outlines, as shown in Fig. 17.14.
Fig. 17.9 Layer stackup definition for board outline Rigid 1
Fig. 17.10 Layer stackup definition for board outline Flex 1
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Fig. 17.11 Layer stackup definition for board outline Flex 2
Fig. 17.12 Layer stackup definition for board outline Rigid 2
Fig. 17.13 Layer stackup definition for board outline Rigid 3
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Fig. 17.14 Generate Route Borders window
As shown in Fig. 17.15 of the board outlines and route borders, the Rigid-Flex circuit board consists of five parts, three rigid circuits + two flex circuits, each part of which has different Layer stackup and uses a uniform route border. 5.
Define Bend Area
A Rigid-Flex circuit is characterized by its flexible part can be bent, but not all the flexible part can be bent, so the bending area needs to be defined. In addition, the radius, angle, direction of bend are need to be defined. Here we define the bend area of the flexible circuit. Menu select Draw → Bend Area. In the area of the flexible circuit, the bend area is drawn across the flexible board outline, the Bend Area in editing state is filled with curves, the border is editable, the parameters is adjustable, the finished Bend Area is displayed hollow, and the area outside the board is automatically hidden, as shown in Fig. 17.16.
Fig. 17.15 Rigid-Flex circuit board outlines, routing border and layer stackups
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Fig. 17.16 Bend area parameters setting and editing
The parameters of Bend Area are explained below: • Board Outline: Define which board outline the bend area belongs to, only the Flex board outline can be defined. • Bend Radius: Define the Bend Radius. • Bend Angle: Defines the bend angle, where positive values represent upward bending and negative values represent downward bending. • Bend Origin: The origin of a bend, which defines whether the bend origin is on the left, center, or right side of the bend area. • Bend Order: define the bend order. • Area Tolerance: define the tolerances for DRC checks. • First Corner: The first bend point, which defines the bend start point of the routing. • Dynamic Bend: Dynamic bending, which defines whether or not to bend dynamically. • Allow Corner: define whether the routing is allowed to bend in the bend area. • Allow Width Changes: define whether routing can change widths within bend areas. • Allow Non-perpendicular: defines whether the routing can traverse bend areas nonvertically. • Allow Vias: defining whether vias can be placed in bend areas. • Allow Solid Fill: define whether solid fill is possible in bend areas. • Allow Parts: define whether devices can be placed in bended areas. • Left Slide Distance: Define Dynamic Zone for 3D DRC. • Right Slide Distance: Define Dynamic Zone for 3D DRC. • Binding Length: defines the stretch length of the bend area.
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Fig. 17.17 3D View of Rigid-Flex circuits bend area
After drawing and setting of the bend area, we can open the 3D View window and check Flex Objects related options under the 3D TAB of Display Control to see the 3D bend area of the rigid-flex and the flexible circuit, as shown in Fig. 17.17. 6.
Define Flex Layer of Padstack
Larger pads and openings are usually defined on cover layer of flexible area to improve the attach strength of the pads in flexible area. Replacement cells can be defined in the central library to place different cells in the Rigid-Flex areas, or pad definitions for the flexible areas can be added to Cell Padstacks, in this case using the latter method. In this example, padstack 80 × 25R is taken as an example. Under the default TAB, it is defined of rectangle 80 × 25 for top mount and bottom mount, and soldermask of rectangle 86 × 31. Under the flex TAB we add definitions of rectangle 82 × 27 for top mount and bottom mount, and cover layer of rectangle 90 × 35, as shown in Fig. 17.18. Then, by comparing the devices placed in the flexible area before and after the definition of Flex TAB pad, such as the devices upper and lower in Fig. 17.19, we
Fig. 17.18 New pads definition under Flex TAB
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Fig. 17.19 The change before and after Flex TAB pad definition
can see that: (1) the upper device pad size is enlarged, (2) there is a window in Cover Layer of the upper device. The lower device is used for comparison, since Flex TAB is undefined, there is no change. 7.
Increase Stiffener for Device Welding Area
Select Draw → Stiffener from the menu to draw the reinforcement area around the flexible circuit welding area. From the layer stackup definition of board outline Flex 2 in Fig. 17.10, we can know that the Stiffener of the flexible circuit is at the bottom layer. Therefore, the Stiffener reinforcement area appears at the bottom of the flexible circuit. We can rotate the 3D view to the bottom of the flexible circuit. It can be seen that after drawing the Stiffener reinforcement area, it appears at the bottom of the flexible circuit, as shown in Fig. 17.20. 8.
Route and Plane for Flexible Areas
The routing in the flexible circuit area is similar to that of the common substrate. It should be noted that parallel lines should be taken as far as possible and less bending should be made. If bending is required, circular arcs should also be used to reduce stress concentration and avoid failure during bending. We can use functions such as Hug trace and Multi Hug trace to distribute the routing parallel to the flexible area. The operation method can refer to Chap. 14 layout route and plane. Figure 17.21 shows the effect of flexible circuit routing. For plane process of flexible circuit areas, it is generally recommended to use grid plane with a 45° angle between the grid orientation and the bending area of flexible circuit, as shown in Fig. 17.22.
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Fig. 17.20 Draw stiffener area, it appears at the bottom of the flexible circuit
Fig. 17.21 Routing effect of flexible circuit
Fig. 17.22 Plane effect of flexible circuit
17.3 Complex Substrate Technology 17.3.1 Definition of Complex Substrate 1.
Definition of Complex Substrate
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Complex Substrate, as opposed to Simple Substrate, refers to a more complex substrate in both design and production processes. Here, we focus on the design process and give the following definitions. Complex substrate: refers to a SiP or advanced packaging project that contains multiple substrates, and the multiple substrates need to be designed in one Layout environment, which we call complex substrate. For example, the Rigid-Flex circuits we described above usually consist of multiple Rigid and Flex substrates and are completed in a Layout design, so they can be called complex substrate. The substrate used in the Rigid-Flex packaging are complex substrate. In addition, PoP (Package on Package), SiP or advanced packaging with silicon interposer, can be called complex substrate if it needs to be designed in one Layout design environment. Of course, if the upper and lower boards in PoP are designed in different Layouts, and the Silicon interposer and Substrate in SiP or advanced packaging are designed in different Layouts, we do not call them complex boards, but multi-layout projects. For multi-layout projects, please refer to Chap. 18 Multi-Layout Project and Concurrent Design. 2.
Complex Substrate Design Environment Requirements
From the above definition, we can see that to design complex substrate, the Layout design environment needs the following functions: • • • • •
Support Multi-Board Outline; Support Multi-Layer stackup; Support Mulit-Board Interconnection; 3D design environment, support Multi-Board Integration; Support Multi-Technics in production data.
From the above complex substrate design environment requirements and combined with the functionality of Xpedition Layout, we can conclude that except for the third item: Mulit-Board Interconnection which is not completely clear at present, for the other four items Xpedition Layouts can support perfectly. Currently, Xpedition Layout official materials only explicitly support multi-substrate connection based on flexible circuit.
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17.3.2 Application of Complex Substrate In the field of SiP and advanced packaging, the application of complex substrate is very common, including the Rigid-Flex combination packaging and POP mentioned earlier, as well as the packaging type of 2.5D silicon interposer + substrate, RDL + FlipChip can also be classified as the type of complex substrate. It can be said that as long as a package contains multiple substrates or multiple routing structures (RDL, Fan-in, Fan-out), its applications can be classified as complex substrate. • Rigid-Flex substrate packaging The technology of Rigid-Flex substrate is a kind of small size Rigid-Flex PCB technology, which is often referred to as Rigid-Flex combination substrate. Due to the limitations of materials and reliability at present, the bending radius of flexible parts can not be very small temporarily. Therefore, the application of Rigid-Flex substrates in small-size chip packaging needs to be developed. However, the application of Rigid-Flex substrate in slightly larger multi-chip modules has begun to be popularized. Details can be found in Chap. 27 of this book. • PoP Packaging PoP (Package on Package) is stacked vertically by two or more layers of packages. Vertical interconnection between different layers of packages through solder balls, copper pillars, etc. it can improve the density of components in electronic products. With the rapid development of consumer portable electronic products, PoP technology has been widely used. In practical applications, the memory package is usually placed on the top of baseband package. Currently, Apple and Qualcomm’s latest processors all use PoP package, which greatly reduces the size of the motherboard as well as the decrease the distance between the processor and memory. Details design of PoP can be found in Chap. 29. 3.
2.5D Silicon Interposer Packaging
2.5D Silicon Interposer enables high density routing and I/O redistribution. Large pitch bump can be used to assemble the silicon interposer on the organic substrate. The application of silicon interposer can reduce the process requirements for microassembly and improve product reliability. The application of silicon interposer can reduce the CTE mismatch between chips and the organic substrate, shorten the interconnect length, improve the electrical performance, and the metal-filled TSV (Through Silicon Via) can also be used as a heat sink channel. Based on the advantages of silicon interposer, this technology has been widely concerned and studied by companies and scientific research institutions around the world. More and more high-end products provide packaging solutions through silicon interposer. Please refer to the design case of Chap. 24 for details.
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17.4 SiP Design Based on 4D Integration 17.4.1 4D SiP Substrate Definition 1.
Structure and Connection of Substrate
Here, we illustrate the design of the complex substrate with a 4D integrated SiP substrate. The 4D integration is achieved through Rigid-Flex circuits, with additional solder balls at the bottom for PCB welding. For the definition of 4D integration, please refer to the first part of this book, Chap. 4, From 2 to 4D Integration. This SiP uses a 4D integrated package, which consists of six rigid substrates connected by five flexible circuits. On six rigid substrates, chips and other components can be installed. Flexible circuits mainly play the role of electrical interconnection and physical connection. After the installation of the components, bend the flexible area 90°, and stitch the rigid substrate into an open-lid box, weld the seams, then reinforce the inner part of the package, finally seal and implant the balls to form a complete 4D integrated SiP. During the process of substrate production, and chip mounting, the whole Rigid-Flex substrate is located in the same plane. After chip mounting, the flexible part is bent 90° to form a 4D SiP package. Figure 17.23 integrates SiP top view and corresponding side view profile for this 4D SiP. A, B, C, D, E, F are rigid substrates, totally 6 pieces, connected by five flexible circuits, identified as 1, 2, 3, 4, 5 respectively. The rigid substrates are metallized on the edges without flexible circuit connection for later welding. In the top view, where a-a and b-b dots line represent the location of the profile, a-a profile is below the Figure, and b-b profile is on the right side of the Figure. b
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Fig. 17.23 The definition of 4D integrated SiP multi-substrate
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Fig. 17.24 4D SiP substrate layer stackup definition
2.
Layer stackup Definition of the Substrates
After defining the overall structure and connection of the substrate, the next step is to define the Layer stackup of each substrate. In this example, we define A substrate as 6 layers, BCDEF as 4 layers, and flexible connection as 2 layers. By overlaying and merging, we get Master Stackup, as shown in Fig. 17.24.
17.4.2 4D SiP Design Flow 1.
Principle and Scheme Design
This step mainly defines the number of chips to be installed, the interconnection between chips, and the planned layout location. In this example, we have planned 19 bare chips, 8 of which are connected by 3D TSV, each of which is 4 in one group, to form two sets of 3D TSV interconnect stacks, which are mounted on A substrates. The other 11 bare chips are mounted on the BCDEF substrates, including tiling (2D) and chip stacking (2D+). Two chips on the B substrates are stacked together, and three chips on the F substrates are stacked together. In addition, the design contains 12 capacitors and 12 resistors, and the design uses BGA as the pin output. 2.
Board Outline Drawing and Layer stackup Setting
Draw the board outline according to Fig. 17.23, and define Master Stackup layer stackup according to Fig. 17.24. Set up a Layer stackup for ABCDEF and the flexible circuit. In this design, A substrate is 6 layers, BCDEF is 4 layers, Flex is 2 layers, and the layer stackup setting is as shown in Fig. 17.25. After the board outline drawing and layer stackup settings are completed, you also need to draw Bend Area for each Flex area and set its bend angle to 90°, then generate the routing border based on board outline, using the method described earlier in this chapter.
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A BCDEF Flex
Fig. 17.25 4D SiP substrate layer stackup setting
3.
Chip Stacking and Layout
Before layout, first set up the chip stack, which in this example contains four chip stacks: 3D TSV-StackA, 3D TSV-StackB, Stack1-2Chips, Stack2-3Chips. The design method of the chip stack can refer to Chap. 12 of this book. After the chip stack setup is completed, layout the chip to different positions of the substrate. In this design, all the chips need to be laid out to the top layer of the substrate. During packaging process, the chips are encapsulated inside the 4D package by the folded substrate. The BGA package needs to place at the bottom of the A substrate for subsequent PCB connection. Chip bonding occurs after the layout is completed. For chip stacking bonding, different chip layers need to set different bond wire models. The bonded chip stacking is shown in Fig. 17.26, and the overall effect of layout completion is shown in Fig. 17.27, with 2D view on the left and 3D view on the right. 4.
Routing and Optimal Adjustment
For a quick example, this design uses automatic routing. Because the routing in flexible area is as vertical as possible to the bend area, 90° routing is used in this example. The result of automatic routing is shown in the Fig. 17.28, reaching 100%
Fig. 17.26 Bonded chip stacks (3D & 2D+)
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Fig. 17.27 4D SiP substrate overall layout
Fig. 17.28 4D SiP routing complete
routing rate. After the automatic routing is completed, it is necessary to carefully check if there is any irregular routing in flexible bend area, make optimum adjustments, and finally complete the routing. As shown in Fig. 17.28, all Flex bend areas avoid corners.
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4D SiP Digital Prototype
Below, all of our previous work can be validated in 3D environment, and a digital prototype of 4D SiP can be obtained in 3D View. Menu Select Window → Add 3D View to open the 3D design window. Check Flex Bend under Flex Objects in 3D TAB list of Display Control window. We can see that the substrate magically folds into a box package, which we call 4D SiP package. By rotating the cube in the lower left corner, we can rotate the 4D package and view it from all angles. The top and bottom 3D views of the 4D SiP digital prototype are shown in 17.29. Because the box is closed and its internal structure cannot be seen, we can imagine cutting the package to see its internal structure. Xpedition software can really satisfy this idea. Menu select 3D → View → X Cut Plane, we can see that the box is cut, we can move and rotate the CutPlane, view the inside of the package from different locations and angles, Fig. 17.30 shows the inside view after cutting, you can see the exact installation location of chips. Finally, let’s compare the chip distribution and net interconnection before and after routing. In Fig. 17.31, we see that the chips are located in different locations in 3D space, and the net connections between them represent the electrical connection. Then we need to route in 3D space to connect them. Unlike the planar-based routing on common substrates, the routing in 4D SiP needs to go through different substrates, and needs to turn at the connection of the substrates, resulting in the routing in 3D space. In Fig. 17.32, we can see that the physical connection of electrical signals between chips is achieved through real 3D routing. So from the routing point of view, the 4D SiP routing is in 3D space, however the electrical connections that we normally use in 2D or 3D SiP are all routed on the 2D plane.
Fig. 17.29 Top and bottom view of 4D SiP digital prototype
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Fig. 17.30 Internal view of 4D SiP digitized prototype
Fig. 17.31 Components and net connections of 4D SiP digital prototype
17.5 Significance of 4D SiP Design In Chap. 4 of this book: From 2 to 4D integration, we define five integration modes from 2D, 2D+, 2.5D, 3D and 4D on substrate, together with a total of seven integration modes, planar integration and cavity integration in substrate. In these integration methods, in addition to 4D integration, the other integrated routing is in one plane, and then through the vias to connect the different layers of routing. The 4D integration is completely different. Within 4D package, the routing
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Fig. 17.32 3D routing connection of 4D SiP digital prototype
Fig. 17.33 4D integration has broad application prospects
is distributed throughout the 3D space, as we can see in Fig. 17.32, on all six sides of the package. Therefore, we can understand that, in addition to 4D integration, other integration methods are mainly based on the physical structure of the distinction, the routing, that is, the electrical interconnection, is completed in the 2D plane. The difference of 4D integration is that in addition to its physical structure of 3D, its electrical interconnection is also 3D, which has one additional dimension than other integration, which is the important reason why we call it 4D integration. As we mentioned earlier, in addition to the physical structure, electrical interconnection is also a key concern in SiP design. Electrical interconnection directly affects the quality of the signal, thereby affecting the performance and reliability of the product.
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4D integration technology has a wide application prospects, such as panoramic camera for omni-directional monitoring, capsule endoscopy for medical field, multidirectional detector for small space, multi-directional sensor, etc. All of them will use 4D integration, and with the development of technology, it will be applied to more and more fields. With the development of science and technology and the increasing demand for miniaturized micro-system structure in all walks of life, 4D integration technology will be applied more and more widely in the fields of electronics, medicine, aerospace and so on, just like 2.5D integration and 3D integration today. Finally, we need to be clear that 4D integration does not necessarily improve the Function Density within the package, but it greatly increases the flexibility of system integration, increases the diversity of package integration, and plays an important role in increasing the function density of the whole system.
Chapter 18
Multi-layout Project and Concurrent Design Suny Li
18.1 Multi-layout Project 18.1.1 Multi-layout Project Design Requirements In recent years, the rapid development of SiP technology has brought a new trend, that is, the traditional chip packaging that is usually considered by chip manufacturers has gradually changed to the design of packaging by system users. Of course, this kind of packaging is basically composed of multiple chips and can form a complete system, that is, SiP system in package. 1.
Co-design between SiP and PCB
In the past, chip manufacturers usually packed the bare chips before selling them to users. Users get the packaged chips and apply them directly in PCB design. Most of the packages designed in this mode are single chip packages. Nowadays, with the development of SiP technology, more and more users want to obtain bare chips for system design and packaging based on bare chips. As a result, the market demand for bare chips will also increase significantly, and some traditional chip agents will gradually expand the business of bare chips to meet the growing market demand for bare chips. At present, with the requirement of system design miniaturization and low power consumption increasing, many system users turn their attention to SiP and advanced packaging. These users include a number of large multinational companies and scientific research institutions in the world, as well as numerous domestic research institutes, among which aerospace, electronics, ships and other fields are particularly prominent. S. Li (B) Beijing, China e-mail: [email protected] © Publishing House of Electronics Industry 2022 S. Li (ed.), MicroSystem Based on SiP Technology, https://doi.org/10.1007/978-981-19-0083-9_18
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Fig. 18.1 Relationship and signaling pathway among Chip, SiP and PCB
Since SiP and advanced packaging design are gradually changing from IC manufacturer to system user, and system user is most concerned with system design, the collaboration and unified management of SiP packaging design and PCB system design are becoming more and more important. SiP itself has become a key part of the whole system design, which needs to be implemented under a unified platform. Here is a specific example to illustrate. Designers want to design a system that contains two SiPs, which will be placed on the same PCB to form a complete system. The system structure and signal pathway in the design are shown in Fig. 18.1. In addition, in 2.5D integration, silicon interposer need to be inserted between substrate and chips, and two or more substrates need to be stacked together in PoP design. These technologies need to manage multiple substrates in one project, so multi-layout project management is particularly important. 2.
SiP with Multiple Substrates
We have describe complex substrates design in previous chapter. The following definitions are given for complex substrates: a SiP or advanced packaging project contains multiple substrates, and the multiple substrates need to be designed in one Layout environment, such multiple substrates can be called complex substrate. If the upper and lower substrate of PoP are designed in different Layouts, if the Silicon interposer and Substrate in advanced packaging are designed in different Layouts, they are not complex substrate, which we call multi-layout projects. Therefore, SiP project with multiple substrates may belong to a complex substrate project or a multi-layout project due to different design methods. It is necessary to see which method is more convenient and more effective for the smooth and accurate completion of the project. Reasonable selection of design process in Xpedition can achieve twice the result with half the effort. Figure 18.2 shows a typical 2.5D TSV project with three layouts, Interposer, Substrate and PCB, which need to be designed in one project.
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Logic
Interposer
2.5D TSV
Substrate
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Fig. 18.2 Typical 2.5D TSV project contains three layout designs
18.1.2 Multi-layout Project Design Flow Below, we describe the design flow of a multi-layout project using the 2.5D TSV project described above as an example. In Xpedition Designer environment, the following projects can be created: Project named ISB_Project, where I stands for Interposer, S stands for Substrate, B stands for Board, that is, the project contains three layouts, Silicon Interposer, package Substrate, and PCB Board. Create three New Boards in a row, with three layouts in the project named Interposer, Substrate, PCB_Board, as shown in Fig. 18.3, manages multiple layout designs in a project. The three layouts have their own schematic, which can be designed separately or shared with data. For example, if the same schematic design module is used in both Interposer and Substrate, we can design it as a Block and then reference it in the Interposer and Substrate schematic for ease of use. In addition, the elements of the three schematic can directly copy and paste to each other, which also brings convenience to the schematic design.
Fig. 18.3 Manage multiple layout designs in a project
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Fig. 18.4 Three schematic designs correspond to three layouts
Figure 18.4 shows three schematic designs correspond to Interposer, Substrate and PCB_Board three layouts. After schematic designs are completed, each schematic is examined by DRC and packaged separately. Then start the layout design tool Xpedition Layout, when you start Xpedition Layout, first selected different Design Technology for different layout, such as Interposer and Substrate both select Package, PCB_Board selects PCB. Then choose proper different Template, such as Si_Interposer 2 + 2 + 1 Template we created in Chap. 9 for Interposer, HDI 2 + 4 + 2 Template for Substrate, PCB_Board chooses 8 Layer Template. Then choose different Design directory for each layout, as shown in Fig. 18.5. After each layout setting is completed, click the OK button to enter respective layout design environment. Designer can design each layout separately without interference. In the actual design, the sequence of three layout designs should be selected according to the project situation. As Fig. 18.6 shows, on the left is the Interposer layout, which contains two FlipChip bare chips and Interposer Fanout Cell. In the middle is the Substrate layout, which contains Interposer fanout Cell and two resistors, two capacitors and BGA Packaged fanout Cell. On the right is PCB_Board layout with two BGA fanout Cells, four other types of IC, and eight resistors and eight capacitors.
Fig. 18.5 The design technology, template and design directory for three layouts
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Fig. 18.6 Layout design of interposer, substrate, and PCB_Board
Managing multiple layouts through a single project makes this design method more convenient from project management perspective because they all belong to one project. At the same time, the schematics of multiple layouts are related to each other and can be shared. For example, Interposer Fanout Cell is an external interface to Interposer. In Substrate design, Interposer Fanout Cell appears as a component, connecting internal (FlipChip) to external (BGA Package). BGA package Fanout Cell is an external interface for Substrate, and for PCB Boards, it appears a component and plays the role of connecting the internal (Interposer Cell) to the external (PCB Board). Three layouts, each designed separately in separate design environment, are then combined in 3D environment to simulate assembly and form a digital prototype. As shown in Fig. 18.7, the top 3D figure of Interposer is output and imported into Substrate’s 3D environment after the design is completed. The middle 3D figure of Interposer + Substrate is obtained. Then its overall 3D model is output and imported into the 3D environment of PCB Boards to get the bottom 3D figure of Interposer + Substrate + PCB Boards. Figure 18.8 shows a digital prototype consisting of Interposer, Substrate, and PCB_Board. Each layout exists as a cell in larger layout environment and is installed in larger layout like a component. There is a hierarchical relationship between the three layouts. Therefore, Hierarchical Layout Environment is also expecting in future. Through concurrent design among multi layout projects, when adjusting the pin allocation of SiP packaging shell, we can consider not only the connection relationship and net optimization within SiP, but also the connection relationship and net optimization in PCB design, so as to give consideration to both inside and outside,
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Fig. 18.7 Assembly interposer, substrate, and PCB_Board together
Interposer
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Fig. 18.8 A digital prototype consisting of interposer, substrate, and PCB_Board
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and more comprehensively consider the optimization of the whole system rather than one-sided adjustment and local optimization, so as to design better and more advanced products.
18.2 Schematic Multi-person Concurrent Design 18.2.1 Schematic Concurrent Design Ideas With the development of technology and the enhancement of system functions, electronic systems become more and more complex, and more people participate in system design. In the design of complex electronic systems, some system circuit schematics contain different functional modules such as digital part, analog part and radio frequency part. Typically, the electrical design of these different functional modules is undertaken by different designers, each designer completes the partly design and then copies their own schematics together to form a system schematic, as shown in Fig. 18.9. This traditional method is still feasible for more mature circuit diagrams. However, if it is a new design project, the design will change frequently, and the problem is that it needs to be copied frequently. Repeated replication can cause many problems. For example, Designer A made two more changes after finalizing, so he copied the total three times to the master schematic. Designer B made three more changes after finalizing, so he copied the total four times to the master schematic. If the final version of designer A and designer B are not copied under the unified master schematic, the design may become inconsistent. At the same time, this repeated replication will result in the coexistence of multiple versions of the schematic, which makes version control very confusing and difficult to control. Concurrent Designs provide a new way to solve problems that cannot be solved by traditional methods and provide specific implementation methods. A complex system schematic is divided into different parts, usually distinguished by different Sheets. Under the unified management of the concurrent design tools,
Digital circuit schematic Analog circuit schematic
Copy together
System schematic
RF circuit schematic Fig. 18.9 The traditional method of separating design and then copying them together
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Digital circuit sheets Analog circuit sheets
System schematic
RF circuit sheets
Fig. 18.10 Schematic concurrent design method based on sheet operation
different designers enter the related schematic Sheets for design operations. When designer A edits a sheet in the schematic, the Sheet is read-only to other designers, effectively avoiding conflicts. At this point, if other designers, such as Designer B, also want to edit this Sheet, he only needs to ask for the consent of Designer A. When Designer A agrees, Stop editing and close this Sheet, the Sheet protection will be automatically removed. As soon as designer B opens and edits this Sheet, it becomes a read-only Sheet for other designers, including designer A. The idea of conflict avoidance in multi-person concurrent design of schematic can be summarized as follows: The designer who first opened and edited the sheet has permission to operate on this sheet. Figure 18.10 shows schematic concurrent design method based on sheet operation.
18.2.2 Operation Method of Schematic Concurrent Design 1.
Hardware Configuration
In the process of schematic multi-person concurrent design, the first step is to configure the hardware environment. One of the computers serves as a file server on which the Projects folder resides and is readable and writable to all designers participating in the project. Of course, a file server can also be a personal computer of a designer who participates in the design by placing the project files in a folder on his or her computer and opening the folder readable and writable permissions to other designers participating in the project. 2.
RSCM Configuration
When the hardware environment is configured, the configuration of RSCM (Remote Server Configuration Manager) is required. Find RSCM in software installation directory and start it, then menu select Management → Install to install RSCM service. Start RSCM after the installation is complete. You can √ see the current version of MGC.SDD.RSCM.EEVX.2.7 with the Config column “ ” and the Status column in green, indicating that the installation and start are normal, as shown in Fig. 18.11.
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Fig. 18.11 RSCM installation and startup
After RSCM installation and startup is complete, you can also see that RSCM is installed and running under Windows services. 3.
Software Startup and Operation
In this example, we build the operating environment shown in Fig. 18.12 for the sake of illustrating how concurrent design works. Two computers are involved in the schematic concurrent design, Suny-PC and Suny-PC2. The Project data is placed in the folder Xtreme on Suny-PC and shared openly. The two computers are connected directly through a network cable. One of the designers involved in concurrent design, such as Suny Li, opens the project in a shared directory, to avoid library pointing problems caused by inconsistent folder paths between the two people. Both open the project via a network path, for example: \\SUNY-PC\Xtreme\TSV_4D_Integration\TSV_Design.prj. When Suny, the second designer, opens the same schematic, it displays at the top of the schematic page: Schematic is in readonly mode (Locked by SunyLi on computer: Suny-PC), as shown in Fig. 18.13.
Suny-PC2
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Project data Network cable direct connection
Suny
Fig. 18.12 Simple architecture for two-person concurrent design
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Fig. 18.13 When the first designer opens a page first, the second designer’s same page is locked
Although the page is locked, any action by the first designer is real-time visible to the second designer. For page 2 in this design, since the first designer has not opened it, the second designer can open and edit it directly. Then, if the first designer opens page 2, it will show: Schematic is in readonly mode (Locked by Suny on computer: Suny-PC2), as shown in Fig. 18.14. At the same time, different designers can only operate on different pages, and the writable access to a page is based on a “first come, first edit” principle. When a designer edits a page, other designers cannot edit it, but they can see the changes on the schematic page in real time. When the designer no longer edits and closes the page, the writable permissions on the page are released to other designers. For example, when the second designer Suny closes Page 2, the prompt bar on Page 2 of the first designer changes. The prompt bar (Locked by Suny on computer: SunyPC2) disappears and the Click to Edit button appears. The designer can now enter the editing state by simply clicking this button, as shown in Fig. 18.15. At this point, the designer who opens the page and first clicks the Click to Edit button has write access to this page. For other designers, the status bar updates to show that the page is locked by the designer who first clicked it. Find iCDB Server Manager in the software installation directory and start it. We can see the design status of the project with two designers, Suny Li and Suny, using Xpedition Designer, as shown in Fig. 18.16.
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Fig. 18.14 When the second designer first opens a page, the first designer’s same page is locked
Fig. 18.15 Page 2 unlock when the second designer close it
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Fig. 18.16 Designer status display in iCDB server manager
Multi-person concurrent design of schematics is based on mutual cooperation and trust, which can greatly improve the design efficiency and effectively maintain the consistency of design data. The concept of concurrent design is recognized by more and more designers. For large and complex projects, concurrent design by multiple people has become an inevitable trend. It can effectively speed up the progress of the project and improve the competitiveness of the product.
18.3 Layout Multi-person Real-Time Concurrent Design Layouts, unlike schematics, do not have sheet or page splits. Layout multi-person real-time concurrent design technology refers to the design of a layout in which multiple designers participate simultaneously without any design splitting. Layout real-time concurrent design has been popular for many years in Xpedition Layout and is a mature technology. Figure 18.17 shows a layout real-time concurrent design diagram. In layout concurrent design, each participating designer can layout and routing globally, while each designer can set up temporary protection areas to avoid the misoperation of other designers during the design process. Designers not only complete their own editing operations, but also need to communicate with each other by language or telephone, or through the built-in information window. Xpedition Layout Concurrent design Tool supports multiple designers to perform a layout design operation simultaneously. In the design process, the real-time and dynamic operation based on network access completely, without human intervention, greatly improves the design efficiency and quality. Layout concurrent design tools have the following characteristics. (1)
(2)
Layout real-time concurrent design, real-time dynamic collaborative routing, real-time operation can also include component layout, rule setup, routing, auto-routing, copper processing, silkscreen adjustment, etc. Real-time concurrent design throughout the entire layout design process. Layout real-time concurrent design sharing technology based on network access is adopted, which eliminates any design splitting and merging during the collaboration process to ensure the consistency of design data.
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Fig. 18.17 Layout multi-person real-time concurrent design diagram
(3)
(4)
Layout real-time concurrent design is supported by multiple users online at the same time. Designers can adjust dynamically according to the progress and difficulty of the project. Design data is shared on a server or a client (any client can be set as a data server) with other collaboratively design clients.
Traditional (old) layout Collaborative design technology requires artificial “splitting” of the layout to allow multiple people to design at the same time. The definition of interface relationships at partitions is cumbersome and can take much longer than a person’s design time due to frequent design changes. After the design is complete, a design “merge” is required. In a real design, design changes are inevitable and may change many times. This split-merge task assignment does not allow to dynamically adjust the designer’s tasks to adjust the progress of the entire project. Since designers can only see the design completion within their assigned modules, if a designer wants to see the status of the entire design, he must download and merge the design data, so the real-time and dynamic data cannot be achieved. Currently, this old Collaborative design technology has been abandoned by Xpedition.
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Xpedition Layout Concurrent design technology is dynamic and real-time, without splitting, defining interfaces, and merging data. Designers can enter and exit the design dynamically, that is, they can now design with two people together, and with another person joining in the next minute, three people design at the same time. The first two people do not need to make any changes and preparations at all. Later, when only one person is needed, the other two people can quit the design without any design merge process. Automatic synchronization technology allows each designer to see the actions of all others in real time. The process server prevents time and edit conflicts in user actions through priority selection and design rule DRC validation. In addition, members of the project can also lock targets when they create protected areas or display protected areas of work area around the cursor. When design changes that affect other users need to be made, all users can be notified to accept or reject them. At present, the real-time concurrent design technology of Xpediton layout has been developed and applied for many years, and the technology is very mature. It has been widely used in layout design of major companies and scientific research institutes at home and abroad, and has achieved great social and economic benefits. According to the internal statistics of the industry, the design efficiency can be improved up to 40–70%, which greatly shortens the project development cycle, improves the competitiveness of products, provides the best solution for shortening the design cycle of sudden design tasks, and gives enterprises and research institutes an advantage in competition. The author began to contact and actively apply layout real-time concurrent design technology in 2005. From the perspective of actual projects, layout real-time concurrent design can save more than 50% of the design time, and can greatly reduce the pressure of designers, thereby improving the quality of layout design.
18.3.1 Configuration of Layout Real-Time Concurrent Software Layout real-time concurrent design technology includes the following design elements, as shown in Table 18.1. Table 18.1 Layout concurrent design technology configuration table RSCM
Remote Server Configuration Manager manages design data, allowing multiple people to access the same design data at the same time
iCDB Server Manager
Integrate the Universal Database Service Manager to manage and monitor the concurrent design environment
Team server
Concurrent design management server to manage edits by multiple users and synchronize data
Team client
Concurrent design client, computer (user) participating in concurrent design
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Client A
Client B Project data
Client C
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Fig. 18.18 Data transfer relationships in layout concurrent design
Layout real-time concurrent design data transfer relationship as shown in Fig. 18.18, under the unified management of the server, each designer’s design data is transferred to the server in real time, after the server integrates everyone’s design data, then real-time transfer to each designer’s client computer. From a designer’s point of view, his own actions are carried out at the same time as those of other designers. There are several modes that can be used in the software/hardware configuration. Here are the two most commonly used modes. The first mode is a stand-alone server, where design data is placed on the server and the RSCM (Remote Server Configuration Manager) is installed on the server to manage the design data. The people involved in the design are all client mode and have write access to the data on the server. This mode is more suitable for companies or research institutes that often collaborate in design. It requires dedicated servers and can be managed through privileges to make each design only accessible to relevant people, inaccessible to people who are not related to other projects, or only accessible in read-only mode. The second mode is client-side folder sharing mode, which uses a designer’s computer as the design data server, where the design data is placed, and the RSCM software is installed to manage the design data. The folder sharing feature makes this folder writable for all design participants. This mode is flexible and suitable for companies or research institutes that occasionally collaborate in design. This mode does not require a dedicated server to be configured, and for some time-critical projects, the primary layout designer can invite other colleagues to help. In the
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application of practical projects, this mode plays a great role in promoting emergent projects.
18.3.2 Apply Layout Real-Time Concurrent Design 1.
Start Server
First check if RSCM is installed and started properly, refer to Fig. 18.11 in the previous section of this chapter. , select the Then start xPCB Team Layout—Server project you need to design after starting, for example: \\SUNYPC\Xtreme\TSV_4D_Integration\TSV_PCB\TSV_4.pcb, click OK, then select Xpedtion Layout 301 in the pop-up window, click OK, and then wait for the user to join in the starting XDS window, as shown in Fig. 18.19. 2.
Start Client
Then, the client participating in the concurrent design starts Xpedition Layout and opens the design pointed to by XDS. As the designer joins, you can see an increase in the list of users in the XDS window, as shown in Fig. 18.20. Once properly started, each designer can see the actions of all others in real time. Designers participating in concurrent design projects can either lock protection targets by creating protected areas or display protected areas around the cursor. Figure 18.21 shows the windows of two different designers, with Suny on the left showing that the two circles represent themselves without a name, other designers with a name, and the size of the circle represents the protected area of the work area. As the operation time in the same location increases, the circle will gradually grow larger. On the right is the window display for Suny Li. The circle around the designer’s mouse belongs to a protected area, in which other designers cannot enter or edit, thus avoiding the occurrence of misoperation. In addition, designers can draw their own protected areas by hand, menu selection Draw → Xtreme Protect Area to draw their own protected areas, as shown
Fig. 18.19 Start Xpedition layout team server
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Fig. 18.20 Update of user list in XDS window
Fig. 18.21 Layout window display for two designers
in Fig. 18.22, each protected area will display the designer’s name, and only this designer can edit the protected areas. In addition, it is important to note that although the reserve can only be drawn by the designer himself, it can be deleted by other designers. Therefore, designers participating in collaborative projects must be cooperative in order to improve design efficiency. Layout and routing in a concurrent design environment are basically the same as in a stand-alone working mode. Display and operation in a 3D View environment can also be used normally. This is not detailed here. Readers can refer to other chapters. 3.
ICDB Status Monitoring
Find iCDB Server Manager in the software installation directory and launch it. We can see the design status of the project. There are two designers participating in the
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Fig. 18.22 Two designers draw their own protected areas
project, Suny Li and Suny. All of the tools they use are Xpedition Layout. The design status is shown in Fig. 18.23. Two Xpedition Layouts were launched under designer Suny Li, one for XDS Server, one for Client, and one under designer Suny, which matches the actual situation. 4.
Data Save
After the concurrent design is completed, or during the concurrent design process, designers participating in the concurrent design can exit the design environment at any time. When you exit, you are prompted to save your design, usually select Yes.
Fig. 18.23 ICDB server manager status monitoring
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Fig. 18.24 Action of the last designer to leave concurrent design
When the last designer exits the design, the system will prompt the designer to quit the concurrent design for the last. According to the window prompt, after clicking End, the system will continue to pop up whether to save the prompt window, click Yes, as shown in Fig. 18.24. After the design is saved, the concurrent design is completed. Saved design data formats are identical to common layout designs, and can be continued by a single designer or concurrent design by multiple people in subsequent design processes.
Chapter 19
SiP Design Flow Based on Advanced Package (HDAP) Suny Li
19.1 Advanced Package Design Flow Introduction Advanced Packaging or Advanced Package, also known as HDAP (High Density Advanced Package), contains a wide range of technologies, such as RDL, Fan-In, Fan-Out, Flip Chip, TSV, 2.5D, 3D, WLP and so on. Emerging technologies such as FOWLP, Silicon Interposer, CoWoS, and WoW all fall into the category of advanced packaging. Advanced packaging emphasizes the advancement of the process, while SiP emphasizes the functionality of the system. In terms of category, most advanced packaging and HDAP belongs to SiP. SiP and HDAP are driving the convergence of traditional IC design and packaging design. The limitations, costs and risks of the expansion of single-chip IC are driving the growth of advanced multi-chip heterogeneous integrated circuit packaging solutions, creating more opportunities throughout the design process. SiP and HDAP design and verification present unique challenges that traditional design tools and methods cannot solve. Partnership and collaboration among design house, OSAT, Foundry, and Fabless can be achieved by combining IC design and package with tools that can operate in the field of IC and packaging design. Figure 19.1 shows a typical structure diagram of a High Density Advanced Packaging (HDAP).
S. Li (B) Beijing, China e-mail: [email protected] © Publishing House of Electronics Industry 2022 S. Li (ed.), MicroSystem Based on SiP Technology, https://doi.org/10.1007/978-981-19-0083-9_19
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Fig. 19.1 Typical structure diagram of HDAP
19.1.1 Technical Indicators for HDAP Design Environment For successful HDAP design and production, we need to focus on the following technical indicators: (1) (2) (3) (4) (5) (6)
(7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18)
Coordinate and manage multiple layout designs in one environment. Supports rapid evaluation of different packaging technologies or solutions. Capture all data accurately and quickly define the interconnection between chip stack and substrate. Requirements for cross-boundary planning and prototype connectivity, with emphasis on high performance interfaces. Ability to implement design intent in detail with other tools. Ability to handle different substrate combinations such as chip, silicon interposer, package substrate, and PCB board connection planning, management, and visualization. IC-Interposer-Package-PCB 4 Levels optimization. Implement design in a fully integrated 3D environment. Generate and manage hierarchical system net lists. Provides design capacity and performance for extremely high pin count, supporting at least 250 K + pins. Advanced region filling algorithm to accurately represent micron and nano geometries. Supports graded exhaust, density, sharp angle and stress relief checking and verification. Always output complex and high quality GDSII. SPG (Signal-Power-Ground) ratios and modes to ensure high-quality signal return paths and adequate power transmission. Route Planning, Layer Allocation and Routing Feasibility Assessment. Pin optimization for package on PCB or pin optimization for chip in package. Setup and Management of High Speed Signal and Differential Pairing Rules. Quick assessment of electrical and thermal performance.
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Simplify cross-regional, cross-departmental collaboration and communication. Various inputs and outputs of production data, rich input and output interfaces.
19.1.2 HDAP Design Flow First, let’s look at two important tools in HDAP design flow, XSI and XPD. 1.
System Construction and Net Optimization Tool XSI
When design SiP and HDAP, it is best to share information among Die, Interposer, Substrate and PCB and optimize the whole signal path in the whole design process. Xpedition Substrate Integrator (XSI) provides an integrated design environment that can be associated with integrated circuit IC and PCB system design when designing chip packages. XSI design environment opens up possibilities for Die, Interposer, Substrate, and overall PCB optimization. 2.
Package layout design tool XPD
In HDAP design, in addition to the overall net optimization tools, it also needs powerful layout design tools. In addition to powerful layout and routing functions, it also needs an excellent 3D design environment, so that designers can have an accurate grasp of the overall packaging structure and details, so as to improve the efficiency and accuracy of the design. Xpedition package designer (XPD) is such a tool. XPD comes from Xpedition layout, and its function is similar to Xpedition layout 301, but it is also different from Xpedition layout 301. XPD is specially designed for advanced packaging design, so it has certain optimization in packaging design function. For example, XPD can import AIF, CSV netlist and ODB++, and export AIF, color map and PCB library data. While Xpedition layout 301 has no corresponding function. XPD has external component wizard, which layout 301 does not have; Of course, there are some functions of layout 301 that XPD does not have. Layout 301 can support the design of package, PCB and Rigid-Flex, while XPD only supports package design. Layout 301 can be driven by schematic diagram and netlist, while XPD only supports netlist. In other ways, the two are basically the same. It can be said that XPD and layout 301 are like twin brothers, with similar basic functions, but each has its own characteristics. How to choose a reasonable tool for design? If you only do package design and have no special preference for schematic, XPD is recommended. If you not only do package design, but also involve PCB and Rigid-Flex design, and are used to using schematic as the input mode of net connection, Xpedition layout 301 is recommended. 3.
HDAP design Flow
The above two tools, XSI and XPD, are used in HDAP design process. The design flow and tool functions are shown in the following Fig. 19.2:
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Fig. 19.2 Design flow of HDAP through XSI + XPD
(1)
(2)
(3)
(4) (5) (6) (7)
Firstly, the component information is generated by importing AIF, CSV and DEF\LEF files, and the component includes two types. ➀ Pin array or part, including bare chip (bar die), flip chip and BGA, can be created in this type. Generally, it is generated by importing AIF and CSV files. ➁ Virtual die model (VDM) contains more information about the inside of the chip, such as the metal layer inside the chip, and the connection relationship between the external pins and the internal I/O buffer. It is optimized and edited. It is usually created by importing the DEF\LEF file. Then, the signal net connection information is generated by importing VHDL/Verilog or CSV file. Different components are electrically connected by the same net name, and different colors can be set for different nets to distinguish. In XSI floorplan, the device layout, including chip stack setting, net optimization, layout template selection, layer stackup setting, and transfer design data to XPD are implemented. Design in XPD 2D environment, including wire bonding, cavity, chip stacking, layout and routing, copper filling, DRC design checking, etc. 3D digital prototype modeling, structure simulation and 3D DRC inspection are carried out in XPD 3D environment. All kinds of simulation data are output through simulation interface for electrical, thermal and mechanical simulation. Output Gerber, drill, GDS, ODB++ format data for production and manufacture.
19.1.3 Design Task: HBM (3D + 2.5D) Next, we use a HBM design with 3D + 2.5D integration technology as an example to describe how to apply XSI and XPD to realize the design flow of HDAP.
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Before design, we first understand what is HBM, HBM (High Bandwidth Memory) is a new advanced package of GPU/CPU and memory chip. After 3D stacking multiple DRAM chips together with a logic chip, we package them with GPU in 2.5D interposer to realize a large capacity and high-level wide bandwith DRAM combination array. As shown in Figs. 19.3 and 19.4, the die in the middle is the GPU. There are four stacks of HBM DRAM particles on the left and right sides. Each stack contains four layers of DRM chips. There is a DRAM logic control chip at the bottom layer to control the DRAM. The chips in the HBM stack are connected by 3D TSV. The GPU and HBM stacks are connected by MicroBump and Interposer, then Interposer is connected to BGA Ball by Bump and Substrate, and finally to PCB by BGA Ball. To sum up, in the XSI + XPD design tool, in order to achieve HBM design, we need to build four sets of HBM Die Stacks, each containing four HBM Dies and one Logic Die, which are connected by 3D TSV. The four groups of HBM DieStack
Fig. 19.3 Top view of HBM advanced package
Fig. 19.4 HBM side view (with 2.5D + 3D integration technologies)
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and GPU Die are integrated through Interposer. The top and bottom surfaces of the Interposer are interconnected by 2.5D TSV, then installed on the packaging substrates by Bump, interconnected by routing of the substrate, and finally connected by BGA with other devices on the PCB board.
19.2 XSI Design Environment 19.2.1 Design Data Preparation In previous SiP design flow (based on Xpedition Designer + Xpedition Layout), the first step is to create the required component library in Library Manager, complete the net connection in the schematic tool Designer, and then transfer the net list to the layout tool for layout design. In the design process of XSI + XPD, component libraries, net connection and net optimization are also needed, which can be accomplished in XSI, then component and net information are transferred to layout tool XPD for layout design. In Chap. 7: Central Library Management, we describe that the property information of all components in SiP design can be managed by spreadsheet of Excel, then creating a Symbol library by copy and paste, or a Cell library by importing to Die Wizard. XSI supports multiple formats of files, making them more convenient and flexible. In XSI, the files supporting component library creation and net connection include the following: (1)
(2)
(3)
(4)
CSV (Comma Separated Value) file, as its name implies, its parameter values are comma-separated, and CSV can be presented in a spreadsheet, which can be easily edited in software such as Excel. CSV is also a text file that can be opened and edited in a text editor. In XSI, CSV files can be used as chip information input and output or net information input and output. AIF file, which is a standard ASCII format file describing chip dies and package BGA information. The chip has been designed and is no longer planned. Therefore, the file only contains information such as chip and package pins. LEF and DEF files can be selected if more detailed information is needed inside the chip. LEF (Library Exchange Format) file, describes the abstraction of the chip unit used for chip layout and routing. It contains information such as the size of the chip unit, the location of the blockage, pin, etc. DEF (Design Exchange Format) file, describes chip design information, such as how many cells, pins, nets, connections are in an IC design. The information imported through LEF and DEF file formats can contain the metal layers inside the chip and make small adjustments to suit the best pin-to-pin design of the chip to the signal path of package and the whole system.
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VHDL (Very-High-Speed Integrated Circuit Hardware Description Language) file, describes the structure and behavior of hardware in a digital system as text. It is mainly used in the design of digital circuit, and in XSI it is mainly used for input and output signal definition and net information. Verilog file, also known as Verilog HDL, is also a hardware description language (HDL), which describes the structure and behavior of digital system hardware in text form. It can represent logical circuit diagrams, logical expressions, logical functions accomplished by digital logic system, etc. It is mainly used for input and output signal definition and net information in XSI.
Although XSI supports files in many formats, not all files are required, depending on the design. If the chip has been designed and the pin is fixed, the design can start with CSV or AIF files. If the chip has not been designed yet and the pin can continue to be optimized, then LEF and DEF files containing the internal circuit information of the chip need to be used to achieve bi-directional optimization of the chip and package. VHDL and Verilog files are mainly used for input and output signal definitions and net information, and CSV files can also be used to define signals and nets. Below, we describe the design flow and application of high density advanced packaging with 2.5D and 3D integration technology, combining specific EDA software application methods.
19.2.2 Introduction to XSI Working Windows XSI design environment also has latest smart style, its windows and menus will change dynamically according to the designer’s choice, which makes the design more efficient and needs to be adapted. XSI has 8–13 sub-windows (depending on the options), each of which has different functions. Here is a brief description of the eight most commonly used sub-windows in XSI. ➀ ➁ ➂ ➃ ➄
The Project window, which is used to add and manage elements in a project. In the Project window, you can add Design, Components, and edit the properties of Components and Designs. The Properties window, used for viewing and editing properties of elements in a project, shows different property types when different elements are selected. Signal\Connectivty window, which displays as Signal when the component is selected, and Connectivty when the design is selected. Pins window, showing the pins and related properties in the component or design. The Device\Floorplan\Die window displays as Device when ordinary components are selected, Floorplan when design is selected, and Die when VDM is selected. It is a graphical window for editing pins, planning device layout, and net optimization.
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System Connectivity window, Used to display connection relationships throughout project. The Display Control window, which controls the display of the Device\Floorplan\Die window in your design. The Console window, which displays whether each step of the operation was performed correctly and the corresponding information report. Figure 19.5 shows the working window of XSI in Device mode. Figure 19.6 shows the working window of XSI in Floorplan mode.
Fig. 19.5 XSI working window-Device mode
Fig. 19.6 XSI working window-Floorplan mode
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19.2.3 Create Projects and Design then Add Components 1.
Create Projects and Designs
Launch XSI tool, select File → New Project from the menu, set the project path in the pop-up window, and enter the project name, such as HBM_HDAP, click OK to create a new project. Then, in the Project window, right-click menu select Add Design → New, enter the design name Interposer in the pop-up window and select the corresponding central library, then click OK to create the design Interposer as shown in Fig. 19.7a. Repeat the steps above to add design Substrate, as shown in Fig. 19.7b.
19.3 Add Bare Chip Device After creating the design, then create the HBM DRAM Die. Select Interposer design, right-click Add to Design → New Pin Array or Part, and type HBM_A in the Component Name bar of the pop-up window, and A1 in Component RefDes. Then, in the Device Properties window that pops up, select the Text file in the Device definition window and Browse the prepared file HBM_die.csv, as shown in Fig. 19.8a. In the spreadsheet definition window, you can see that the file content has been imported, mainly including Pin Number and pin coordinates X Coord and Y Coord, and enter 35 in Pad Size, unit select um, indicate the chip using 35 um MiroBump, as shown in Fig. 19.8b. Then select Spreadsheet in Signal Source window and select the prepared file HBM_Signal_A.csv, in the spreadsheet definition window, you can see that the contents of the Signal file have been imported, mainly containing information about Signal. Here we need to focus on Function Signal in column 1 and ILN (Instance Level Net) in column 7 and enter column number 7 of ILN in Instance Level Net definition. If the file has a header, check Ignore header, as shown in Fig. 19.9.
Fig. 19.7 Add design interposer and substrate in HBM_HDAP project
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Fig. 19.8 Define the pin position and pad size of the device
Fig. 19.9 Import signal-related information
Then, in the Flow Settings window, set the chip height to 120 um, select IC-Bare Die in the Part Type bar, Mount Style select Surface. In the Definition Perspective window, select Live Bug “Pins Down”, as shown in Fig. 19.10. Finally, set appropriate units and grids in the Advanced window, then click OK to add the components. At this point, we can see the added component HBM_A under the Interposer design of the Project window, preview its graphics in Device window, see its signal assignment in signals window, view its pin definition in Pins window, view its pin properties in the Pins Properties window, and open or close or set its display through the Display Control window. As Fig. 19.11 shows. 3.
Set Pin Position of Chip
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Fig. 19.10 Set part type, height and definition perspective information
Fig. 19.11 HBM_A chip created in interposer design
Chips in the HBM stack are connected by 3D TSV, and the definition of 3D TSV can refer to Chap. 12 of this book. Die Pin is located on both the top and bottom surfaces of the chip connected through the 3D TSV. The location of Die Pin is not set when adding components, so it needs to be set here. First filter the pins of the chip in the Pins list, click the filter button to the right of Number, and enter [ˆtop]$ in the Filter Mode window, indicating that you need to list the pin Number without top keyword, as shown in Fig. 19.12. Then, select all pins in the list and change the Side property from PinDie to PinSMD in the Pin Properties window, as shown in Fig. 19.13. Changing the PinDie property to PinSMD means that the designer changes the pins located on the top surface of the chip to the bottom surface of the chip so that the upper and lower chips can be electrically interconnected by the pins on the top and the bottom surfaces. During the subsequent chip stacking process, the bottom chip pin definition is unchanged, and the system automatically changes pin definitions for
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Fig. 19.12 List the pin number without top keyword through the filter
Fig. 19.13 Change pin side property from PinDie to PinSMD
the other layer chips in the stack, PinDie changes to PinDieTop, PinSMD changes to PinDieBottom. 4.
Copy Component
Since each HBM stack contains four HBM DRAM Dies, which have the same functionality and pin definition, they can be created by replication. Select HBM_A, rightclick Add to Design → New Instance, enter HBM_A2 in column Instance Name, A2 in column Instance RefDes, replicate chip HBM_A2, and repeat the above twice to replicate chip HBM_A3 and HBM_A4. Then create the HBM Logic Die following the same process and method as in step 3 above, select Design Interposer, right-click Add to Design → New Pin Array or Part, type Logic_A in the Component Name bar of the pop-up window, type A0 in Component RefDes, create Chip Logic_A. Set the pin position below Logic_A to PinSMD in the same way as in step 3 above. Readers need to note that only identical chips can use copy method, even if the signal definition and pin position are identical, but chips with different processes cannot use the copy method. For example, the lowest stacked chips are connected to the substrate by PinSMD, while the other stacked chips are connected by PinDieBottom and the PinDieTop of the lower stacked chips, so the lowest stacked chips need to be created separately, not by copying other layer chips. Five chips in in HBM stackA are created, as shown in Fig. 19.14.
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Fig. 19.14 Five chips in HBM StackA
5.
Set up Chip Stack
In Project window, double-click Interposer Design, and the XSI window switches to Floorplan mode. Select Setup → Part Stack Configuration from the menu, click the Add button in the pop-up Part Stack Configuration window to add a new stack, named HBM_StackA, then add the chip to the stack, adjust the position of the chip in the stack with the up and down arrows, to create stack HBM_StackA. The stack consists of five chips, A0, A1, A2, A3, A4, from bottom to top, as shown in Fig. 19.15. Designers need to be aware that while pins are set, pins on the top and bottom surfaces of the chip are defined as PinDie and PinSMD, pin definitions of the other layer chips change automatically, PinDie changes to PinDieTop, PinSMD changes to PinDieBottom, except for the bottom layer chips pin definition unchanged. Repeat the previous 3–6 steps to create the HBM_StackB, HBM_StackC and HBM_StackD. The four completed stack of chips are shown in Fig. 19.16. 6.
Add other Devices
In this example, we also need to add GPU and Bump for the Interposer design. If you use the same CSV file input as before, it will operate in the same way. There are
Fig. 19.15 Create HBM_StackA and set the relative positions of five chips
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Fig. 19.16 HBM_StackA, B, C, D creation complete
two things to note: ➀ The type Part Type of the GPU is set to Flip Chip Die, pin size and height are set according to the actual situation. ➁ Bump’s type is set to BGA, Bump’s PinSide needs to be set to Opposite, pin size is set to actual condition, height is set to 0. At the same time, we need to add BGA for the design Substrate, BGA’s PinSide needs to be set to Opposite, pin size also needs to be set to actual situation, height set to 0. Because XSI itself is also powerful in creating chips or package libraries, we use XSI’s built-in library capabilities to create BGA libraries below. Select Substrate design, right-click Add to Design → New Pin Array or Part, enter BGA in the Component Name bar of the pop-up window, P2 in Component RefDes, Custom definition in Device definition, and set it in the Custom definition window. The window has three TABs, in which General sets the number and pitch of pins, the location of the origin, and so on. Pin matrix sets how the pins are arranged, as well as the pin size and name, Pin numbering sets the order and naming of the pins, and whether the JEDEC standard is applied, refer to Fig. 19.17.
Fig. 19.17 Create BGA via custom definition
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Fig. 19.18 Set desired schematic
In addition, the BGA pin net assignment can refer to the previous steps, BGA’s PinSide is set to Opposite and its height set to 0. 7.
Adding Components by Schematic
We can also add devices and net connections by schematics, first by selecting the Substrate design, then by selecting Use existing schematic as connectivity source in the Setting window, and then by selecting the desired schematic in Design path, as shown in Fig. 19.18. Menu select Import → Connectivity, imports schematic data, and then menu select Tools → External Components to view the imported capacitor list C1 to C12 in a pop-up window, all located in (0, 0), as shown in Fig. 19.19. By changing its coordinate position or dragging it in the Floorplan window, the capacitor positions after layout is shown in Fig. 19.20. So far, we have completed the creation and import of all designs and components of the project. The project includes two layout designs, interposer and substrate. The interposer contains 22 components, forming four HBM stacks, GPUs and bumps; The substrate contains BGA and 12 capacitors.
Fig. 19.19 External component information
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Fig. 19.20 Change capacitor coordinate information
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Associate Designs
In addition, we know that the interposer will be installed on the substrate through the bump, which is used as a component on the substrate, and the bump is used as the direct interface between the interposer and the substrate. Therefore, we need to add the bump to the substrate design. Select the bump in the design interposer and drag it to the substrate. Open the floorplan of the interposer and the substrate respectively. We can see that the bump and other components in the interposer are visible in the substrate, as shown in Fig. 19.21. 9.
System Net Connection View
Since this project contains two layout designs and multiple components, we need to see which pin of which device is connected to which net. We can select the net, rightclick Track Net, and view the design, components, pins and coordinate information of the net connection throughout the project in System Connectivity window, as shown in Fig. 19.22.
Fig. 19.21 Associate interposer and substrate through bump
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Fig. 19.22 System net connection from interposer to substrate
19.3.1 Optimize Net Connection Through XSI Net optimization is one of the highlights of XSI. XSI supports multilevel net optimization, which can support multilevel optimization from Die → Interposer → Subtrate → PCB. The essence of net optimization is to optimize connection relationships by exchanging net definitions on exchangeable pins. The principle of net optimization is to minimize crossovers and shorten connections. In this project, the pin definition of the chip is fixed and cannot be exchanged. To avoid misoperation, we can select all pins of the chip and lock them. A lock icon will appear in front of the locked net, as shown in Fig. 19.23. In the Floorplan interface of Interposer, select Bump, right-click menu select Unravel all nets for selected components, slide the bar to the Quality end in Unravel nets window, then click Unravel, the system will automatically remove net crossovers and reassign the net on the Bump pins, as shown in Fig. 19.24. We can see that after Unravel, the net connectivity has improved significantly. In the Floorplan interface of Subtrate, select BGA, use the same method as above, right-click menu select Unravel all nets for selected components, slide the bar to the Quality end in Unravel nets window, click Unravel, and the system will automatically remove net crossovers. The net on the BGA pins are reassigned as shown in Fig. 19.25. One thing that needs to be made clear to designers is that fully automated optimization is unlikely to yield the best results.
Fig. 19.23 Lock chip pins that cannot be used for swapping
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Fig. 19.24 Comparison before and after interposer net optimization
Fig. 19.25 Comparison before and after substrate net optimization
If a good optimization result is needed, the net can be allocated according to the specified area, and the local net can be optimized many times, which often results in good optimization results. Due to the size of the article, this chapter will not be introduced, you can refer to XSI related technical materials. After optimization, we can select Net AHBM_ADDR_col_[0], right-click Track Net, and in the System Connectivity window we can view the layout design, components, pins, and coordinate information of the net connection, as shown in Fig. 19.26. We can see that the pin position on Bump and BGA has changed, which is the result of two optimizations. All nets in the system can be viewed and compared in this way.
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Fig. 19.26 Optimized system net connection
19.3.2 Layout Template Selection After net optimization, the layout has been basically determined, and subsequent work such as routing can be carried out. Prior to this, we could specify the appropriate layout templates for different designs. Layout templates are usually created specially according to different processes and materials and are prepared for design references. For the creation and setup of layout templates, we can refer to Chap. 9 of this book: Creation and setting of layout. First select Interposer, menu select Setup → Stackup Editor, select Yes from the pop-up Query Save window, then select the pre-created PKG_Interposer_Template (Package) template from the drop-down list. After clicking OK, the layer editor appears, as shown in Fig. 19.27. Then select Substrate, menu select Setup → Stackup Editor, select Yes from the pop-up Query Save window, and select the pre-created PKG_HDI_2 + 4 + 2_Template_3 (Package) template from the drop-down list. After clicking OK, the layer editor appears, as shown in Fig. 19.28. Designers are reminded that the choice of layout templates affects the invocation of Layout tools. If you choose a Package-type template, XPD will be launched when you call Layout tools. If you select a PCB-type template, Xpedition Layout will be launched when you call Layout tools.
19.3.3 Design Data Transfer Next, we need to pass the design data from XSI to XPD, and then do the following work in XPD. First select Interposer, menu select Export → Layout, and the software will automatically launch the Xpedition Package Designer (XPD), call the previously specified layout template. In XPD, menu select Setup → Project Intergration, then click the first button in the Project Intergration window. In the pop-up window, select the Import button, as shown in Fig. 19.29.
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Fig. 19.27 Select layout template for interposer
Fig. 19.28 Select layout template for substrate
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Fig. 19.29 Importing XSI data in XPD
After data import, data synchronization is required. Click the third button to update CES changes to Layout, then click the fourth button to update XPD data to XSI, as shown in Fig. 19.30. From XPD interface, we can see that design elements in XSI, including four HBM Stacks, GPU and Bump, have been imported into XPD and inherit the device layout and net connection in XSI, as shown in Fig. 19.31. Then, go back to the XSI interface, select Substrate in the Project window, menu select Export → Layout, and the software will automatically launch the Xpedition Package Designer (XPD), call in the pre-specified substrate layout template, select the same procedure in XPD as above, import and synchronize the data. In XPD, we can see that design elements, including Bump, BGA and 12 capacitors, have been imported into XPD and inherit the device layout and net connection in XSI, as shown in Fig. 19.32.
Fig. 19.30 Synchronize design data in XPD
Fig. 19.31 XPD inherits interposer design data from XSI
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Fig. 19.32 XPD inherits substrate design data from XSI
19.4 XPD Design Environment XPD is a layout and routing tool designed for advanced packaging. It has the same function as Xpedition Layout 301 and its own characteristics. Next we will complete the following work in XPD for HBM_HDAP project.
19.4.1 Interposer Data Synchronization Check First, we check the Interposer data passed by XSI in XPD to see if it meets the design requirements and if the XSI data is passed to XPD accurately and correctly. For example, open the Part Stack Configuration window and check that the four stacks of chips created in the XSI are correct, as shown in Fig. 19.33. Open Cell Editor and check the cell created in XSI is correct, as shown in Fig. 19.34. In addition, layer stackup settings, via definitions, etc. also need to be checked.
19.4.2 Interposer Layout and Routing 1.
Rule Settings
Because the placement has been completed in XSI, the most important work in XPD is routing. First, in CM (Constraint Manager), nets are divided into two classes: Default and Power, and VCC_INT, VCC_IO, VSS net are assigned to Power class and sets the typical trace width of Default class to 5 um and Power class to 10 um, as shown in Fig. 19.35.
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Fig. 19.33 XPD inherits chip stacking data from XSI
Fig. 19.34 All cells of interposer design in XPD are created by XSI
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Fig. 19.35 Set trace width rules in constraint manager
The spacing rule in CM is 5 um. In Editor Control, close the 45-degree routing, use only the 90-degree routing for Interposer, and then in the Pad Entry window, set Allow via under pad, as shown in Fig. 19.36. 2.
Automatic route
In order to quickly see the effect of routing, the automatic route function is used here. For setting up the automatic route, refer to the previous Chap. 14: Layout Route and Plane. During the process of automatic route, the routing status can be viewed in real time. If the routing rate is relatively low, the rule settings need to be checked and the net needs to be re-optimized if necessary to achieve a higher routing rate. Figure 19.37
Fig. 19.36 Allow via under pad in pad entry
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Fig. 19.37 Interposer automatic route effect
shows the result of Interposer’s automatic route, with the overall screenshot on the left and the local screenshot on the right. In addition, the routing result can be imported into XSI for inspection.
19.4.3 Substrate Data Synchronization Check Similarly, we need to check the Substrate data passed by XSI in XPD to see if it meets the design requirements, and whether the XSI data is passed to XPD accurately and correctly. Below, let’s take the Cell check as an example. Open the Cell Editor window and check that the chip Cell created in XSI is correct or not, as shown in Fig. 19.38. In addition, it is also necessary to check whether the setting of layer stackup and the definition of vias of substrate meet the design requirements.
19.4.4 Substrate Layout and Routing Because the device placement of Substrate has been completed in XSI, the main work in XPD is routing. First, in CM (Constraint Manager), nets are divided into two classes: Default and Power, and VCC_INT, VCC_IO, VSS nets are assigned to Power class, and set Default class typical trace width to 30 um, Power class typical trace width to 60 um, and set reasonable minimum trace width and extended trace width. The spacing rule is set to 30 um in CM. In addition, in Editor Control, allow 45° routing, and then in Pad Entry window, set Allow via under pad.
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Fig. 19.38 All cells of substrate in XPD are created or imported from XSI
In Substrate design, copper is usually applied on plane layer. Here we set Layer4, Layer5, Layer6 as plane layer and assign VSS, VCC_IO and VCC_INT to the corresponding plane layer, as shown in Fig. 19.39. In order to quickly see the effect of routing, Substrate also uses the automatic route function. During the process of automatic route, the routing status can be viewed in
Fig. 19.39 Set up plane layer for substrate and assign nets
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Fig. 19.40 Display effects in XPD and XSI after substrate auto route complete
real time. If necessary, the net needs to be re-optimized to achieve a higher routing rate. Because Substrate has a smaller number of nets and Pins than Interposer, the effect of automatic route can be achieved in a shorter time. The left side of Fig. 19.40 shows the result of Substrate’s automatic route in XPD. When the routing is completed, the routing can be imported from XPD to XSI. The right side of Fig. 19.40 shows the effect of routing imported in XSI.
19.5 3D Digital Prototype Simulation 19.5.1 The Concept of Digital Prototype Digital prototype refers to the digital model of an entire system or subsystem of an electronic or mechanical product expressed on a computer. It has a 1:1 scale and a precise dimension representation with real physical products. It is used to validate the structure, function and performance of a physical prototype by using a digital prototype. From the point of view of computer graphics CAD, the narrow understanding of digital prototype holds that digital prototype is to use virtual reality technology to analyze and design various properties of product model, such as design, manufacturing, assembly, use, maintenance and recycling, and to analyze and display all the features of products in a virtual environment to replace or simplify the physical prototype. Generalized digital prototype considers from the point of view of manufacture that digital prototype is a computer-based product description. It is a real-time computer
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simulation of all required functions from product design, manufacturing, service, maintenance to product recycling. Computer technology is used to design, analyze and simulate various properties of products in order to replace or simplify the physical prototype. Digital prototype design, usually refers to all parts through three-dimensional software modeling design, analysis, and assembly into the whole system, through three-dimensional software, to clear the whole system to each part of the dimensions, materials, structure and other details. Before the concept of digital prototype, many 3D structures were conceived with the designer’s mind and presented in a flat form. With the 3D design environment, digital prototype design became possible. At present, many CAD and EDA manufacturers have started to provide 3D digital prototype design solutions. Xpedition is also at the forefront of the industry in 3D design. Its 3D design environment is far superior to that of its competitors.
19.5.2 Introduction to 3D View Environment 1.
Introduction to 3D View
3D view is a 3D design environment embedded in Xpedition Layout or XPD. Although named View, it has certain design functions. For example, component layout can be completed in 3D View. The function of 3D View in Layout is basically the same with in XPD. The following is an example of XPD. Menu select Window → Add 3D View opens the 3D View window. When the 3D view opens, both the main menu and Display Control will present the 3D option. At the same time, the 3D toolbars can be opened from the menu View → Toolbars → 3D General and 3D View for easy operation in the 3D window, as shown in Fig. 19.41. The 3D general toolbar is mainly used for importing, mapping, exporting models and measuring the distance between 3D elements, including Electronic-Mechanic co-design function MCAD Collaborator. 3D View toolbar contains views of 3D designs from all angles, as well as profiles in the three directions of XYZ. Because of the length relationship, they are not introduced one by one. 2.
3D Rotation Operation
Similar to 2D windows, 3D windows can be zoomed in and out by scroll mouse wheel or zoomed in and out by right-click stroke because 2D windows are top view and do not need to be rotated, while 3D View needs to view the design from all angles, which involves a problem of rotation.
Fig. 19.41 3D General + 3D View toolbar
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Fig. 19.42 3D View rotating cube operation
Rotation in 3D View is done using a small cube in the lower right corner of the window, see Fig. 19.42. ➀ Normally, small cubes are shown in state (a), at which point no matter how the mouse operates, the design will not rotate, thus avoiding misoperation. ➁ When the mouse is close to the small cube, it becomes the display state of (b). Six faces, eight corners and 12 edges of the cube can be used as the basis for rotation. When the mouse clicks on the corresponding elements (face, corner, edge), it can rotate to a fixed position. In addition the small house icon and the two-way rotation arrow can be used to rotate, click on the small house, the design is displayed at the default angle, the designer also can rotate by two-way arrow. ➂ If the mouse clicks on the FRONT face, the design faces the designer with FRONT, and at the same time there are four triangle symbols: up, down, left and right. you can clicks on the triangle symbols to rotate them. Each click on the triangle symbols, the design rotates 90 degrees, see Fig. 19.42c ➃ Designers can rotate the cube at any angle, see Fig. 19.42d. 3.
3D measurement operation
To measure the distance between 3D elements, the mouse clicks on the Measure icon , then clicks on the element to be measured in turn, to measure the distance in 3D, as shown in Fig. 19.43.
Fig. 19.43 Measure distance between 3D elements
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Fig. 19.44 Interposer 3D View (front and back)
In addition, you can set up a 3D Clearance and check through 3D DRC whether the distance between elements meets the set rules.
19.5.3 Build HDAP Digital Prototype Model 1.
Build Interposer Model
First, open a 3D view of Interposer design, with four HBM stacks and GPU on the top side and a Bump on the bottom side, as shown in Fig. 19.44. Then, let’s look at the HBM stacks. For example, HBM_StackA, four DRAM chips are stacked on top of Logic chip and connected by 3D TSV, as shown on the left side of Fig. 19.45. Currently, we can’t see the MicroBump connected between chips, and MicroBump connected between Logic chips and substrate. Then open Cell Editor and make the following settings: Select HMB_A, Create Customer properties: MGC_DiePinDelta = 5 um; 15 um. Select Logic_A, Create Customer properties: MGC_DiePinDelta = 15 um; 35 um. The 3D display after the setup is completed is shown on the right side of Fig. 19.45. MicroBumps connected between the chips, as well as MicroBumps connected
Fig. 19.45 Setup MicroBump for HBM chip stacks
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Logic chips and the substrate, have been automatically generated according to the parameters set. Setting up the other three HBM stacks in the same way will achieve the same effect. Then, set MicroBump for the GPU, in Cell Editor, select GPU Cell, set its Underside Space to 60 um in Cell Properties, then select the Cell in the design (2D or 3D environments). Menu select Package Utilities → Edit → 3D Pin Model, select Ball, and enter 3D_Pin Diameter = 65 um. Look at Fig. 19.46, we can see that the MicroBump for GPU is also set. Next, check Interposer Fan Out Bump, in the same way, select Package Utilities → Edit → 3D Pin Model from the menu, select Ball, and enter 3D_Pin Diameter = 120 um, look at Fig. 19.47, we can see that the Interposer fan out Bump is also set. In addition, we can view the 3D view of traces and vias of Interposer in 3D environment, set the substrate to be translucent, or turn off the substrate display, select Include Internal Layers, and rotate the view to see the distribution of trace (RDL) and via (TSV) inside Interposer from different angles, as shown in Fig. 19.48. 2.
Build Substrate Model
Fig. 19.46 Setup MicroBump for GPU chip
Fig. 19.47 3D View of interposer design
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Fig. 19.48 3D view of RDL and TSV inside interposer
Below, we build 3D model for Substrate. In Substrate 3D View, we can see the following 3D pictures, with 12 0402 capacitors and Interposer Bump on the top side and BGA on the bottom side, as shown in Fig. 19.49. First, specify 3D model for capacitors. Currently, the capacitor model is 2.5D model with only size and height information. The 3D model can be derived from many sources, either from the M3DL provided by Xpedition or from external models. The M3DL library provides millions of 3D models for devices, which can be conveniently provided to designers. There are many M3DL options and rich functions. Due to the space relationship, we do not introduce M3DL here. We use the external model import method. Select the capacitor in 3D environment, select 3D → Models → import from the menu, then select the 3D model that was downloaded from the website beforehand. The formats currently supported are also rich, including: Step, asat, iges, igs, prt, sat, xtd, xtda and many other formats, which can be downloaded from the website to import.The comparison before and after import is shown in Fig. 19.50. Since 3D models are manufacturer supplied, their dimensions should be exactly the same as the physical objects, so we can see the effect of capacitor installed intuitively. The 2.5D model is created by designer for occupancy, usually has large size and has different size with physical object. Below we specify 3D Ball for BGA.
Fig. 19.49 Substrate 3D View (front and back)
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Fig. 19.50 Comparison of capacitors before and after 3D models import
Select Substrate Fan Out BGA, menu select Package Utilities → Edit → 3D Pin Model, select Ball, and enter 3D_Pin Diameter = 350 um, look at Fig. 19.51, we can see that the Ball of Substrate Fan Out BGA is also set. 3.
3D Model Assembly
Because the project contains two layout designs, Interposer and Substrate, the net connection between them is coordinated and optimized through XSI, separated in physical design, separated in production and processing, and then assembly together. Next, we simulate the assembly of two layouts in 3D environment. We can import the design data of Interposer into Substrate, and we can also export the design data
Fig. 19.51 Setup 3D model for BGA ball
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from Substrate into Interposer. In practice, it is recommended to import a design with small amount of data into a design with large amount of data, which can save time and improve efficiency. In this project, because of the large number of Interposer chips and details, there is a large amount of data. We will export Substrate data and then import it into Interposer. (1)
(2)
Design data output, in Substrate design environment, select 3D → Export from the menu, make the following choices in the pop-up window, set the export data type to STEP, save in the local output folder, and keep the default name Substrate.step, Model Options and Metal Element Options can also be selected with reference to Fig. 19.52. Design data import. In Interposer design environment, select 3D → Import Mechanic Model from the menu, select Substate.step from the Output folder of Substate, as shown in Fig. 19.53, and then click the Import button to import Substate.step along with its associated files.
Because the imported data contains metal information and holes in each layer of Substrate, it takes a certain amount of time to import the large amount of data. In order to save import time, information such as inner metal and through hole cannot be selected during data export, which has little influence on model assembly. When the data is imported, click on the imported 3D model to set its name, type, rotation angle, and offset, as shown in Fig. 19.54. So far, we have completed the HBM_HDAP advanced packaging design perfectly through XSI + XPD. The design contains two layouts: Interposer + Substrate, 21 bare chips: 1 GPU + 4 HBM Stacks, which are installed on Interposer, and then Interposer and 12 capacitors are installed on Substrate together. The design contains two advanced packaging technologies, 3D TSV and 2.5D TSV, which are relatively complex, as shown in Fig. 19.55.
Fig. 19.52 Output substrate 3D model
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Fig. 19.53 Import 3D substrate model
Fig. 19.54 Setup properties for imported 3D model
Finally, through the 3D Profile Fig. 19.56, we can see that the signals in the HBM stack are connected to MicroBump through 3D TSV, then connected to MicroBump of GPU and the Bump of interposer with the RDL and 2.5D TSV, and then connected to the BGA ball through the routing and via of Substrate. At present, XSI + XPD can complete HMB_HDAP project so perfectly in one design environment.
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Fig. 19.55 HMB_ HDAP project full 3D model
Fig. 19.56 View electrical path through HMB_HDAP project profile
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Chapter 20
Design Check and Production Data Output Suny Li
20.1 Online DRC In in Xpedition Layout or XPD layout design, real-time DRC is turned on by default, and designers can generally ensure that the design is correct without DRC errors while keeping DRC open. Unless DRC is manually turned off due to the special needs. This real-time DRC is often referred to as Online DRC. The option to turn off the Online DRC feature is in Common Settings in the Editor Control bar. By removing the tick option in front of the Interactive Place/Route DRC, you can turn off the Online DRC. A prompt box pops up to indicate that some features such as teardrops, auto Route Gloss, Tuning, etc. will be turned off in DRC OFF and need you to confirm the DRC OFF. When Yes is selected to confirm, the system automatically pops up a reminder box that DRC is closed and always displays in the upper left corner of the workspace until Online DRC is reopened. Figure 20.1 shows turn off Online DRC and the Warning Message Window after Online DRC OFF. With Online DRC off, designers can do anything without the software system checking, which can be used in some special designs. For example, designer needs to place one of the two resistors on top of the other and choose to weld only one of the resistors when the real welding. This method is often used in RF circuit design. Whether or not the Online DRC check is turned off, a complete DRC check, Batch DRC, is usually required for the entire design when it is finished.
S. Li (B) Beijing, China e-mail: [email protected] © Publishing House of Electronics Industry 2022 S. Li (ed.), MicroSystem Based on SiP Technology, https://doi.org/10.1007/978-981-19-0083-9_20
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Fig. 20.1 Turn off Online DRC and the warning message window
20.2 Batch DRC Batch DRC acts as a detailed check to ensure that all elements in the design are within the scope of the rule definition. Batch DRC is available at any stage of the design process and is usually run after the design is complete. Batch DRC has similar check items to Online DRC, but Batch DRC is more comprehensive and can be configured by the designer. Select Analysis → Batch DRC from the menu, start Batch DRC, or click the tool to start Batch DRC. Batch DRC interface is shown in Fig. 20.2 and divided icon into two TABs, which are explained below.
Fig. 20.2 Two TABs for batch DRC main interface
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20.2.1 DRC Settings (1)
Proximity area
First, in the DRC Settings TAB, select Entire design, as shown in Fig. 20.3, which checks the entire design. If you want to check part of the design, you need to draw DRC Windows in design. DRC Windows can be drawn in Draw mode. There is only one DRC Windows in a design. If one already exists, drawing a new DRC Window will automatically replace the existing DRC Window. When DRC Window is selected, Batch DRC only checks within the scope of DRC Window, which saves a lot of time for complex design and is more suitable for checking different design areas during the design process. If there is no DRC Windows in the design, this option is gray and not optional. (2)
Rules to check
If some nets are selected in the design, the Check selected nets only option is selected automatically, followed by the number of selected nets. If no nets are selected, this option is in gray and cannot selected, as shown in Fig. 20.4. If there are no design changes in the design check, and the results are different between the two checks, be aware that the selected nets are different in the two checks, or that no net is selected at one time (check the entire design) and some nets are inadvertently selected at the other time (check only those selected nets). Connectivity and special rules are usually selected by default, as shown in Fig. 20.4. If not select, the Connectivity and special rules TAB is gray and not enabled. In the Proximity options, Net Class clearances and rules, Plane clearances and rules, Bond Wire clearances and rules are all selected by default, and Test Probe clearances and rules are not optional in grey if test points are not placed in the design. If the General and element to element rules option is not selected, the Advanced Element to Element rules button is gray and not optional, as shown in Fig. 20.5.
Fig. 20.3 Check the entire design
Fig. 20.4 Rules to check status comparison
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Fig. 20.5 Select or not select General and element to element rules
After select General and element to element rules, you can click the Advanced Element to Element rules button to bring up the Element to Element rules table, as shown in Fig. 20.6.
Fig. 20.6 Element to element rules table
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Fig. 20.7 Restore default rules setting of Constraint Manager
Fig. 20.8 Pad to pad checks option
By default, the contents of this table are inherited from the spacing rules in CM (Constraint Manager), where users can change the rules or add new ones. The default font color is black, and when the default rule is changed, the font color becomes red, and if the designer adds a new rule definition, the font becomes blue. Normally, if there is no specific design requirement, the rule table is left as default, with the same definition as in Constraint Manager, without rule changes or additions. If the designer wants to restore the settings in Constraint Manager after change the rules, click the Load Default rules button in the lower left corner, and a warning window appears as shown in Fig. 20.7, indicating that the user-defined rules will be discarded. After clicking the Yes button, the system automatically loads the settings in CM and replaces the user-changed settings. Pad to pad checks are primarily used to choose whether to ignore checking Pads to pads spacing within the same component or between the same nets, as shown in Fig. 20.8. If Disable within the same cell is checked, the pad to pad spacing will not be checked inside the component; if Enable for the same net option is checked, DRC will check the pad to pad, pad to via and via to via spacing on the same net.
20.2.2 Connectivity and Special Rules Switch to Connectivity and Special Rules TAB, which check Traces, Nets, Plane islands, Unplaced parts, Holes/Pads/Vias, and more, one by one.
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Trace ➀ ➁ ➂
(2)
Net ➀ ➁
(3)
➁
(5)
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Single point net: Check and report the existence of a single point net in the design Unrouted or partial nets: Check the connectivity of all net in nonplanar layers
Plane ➀
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Hangers: Suspended traces, i.e. unfinished traces, do not have one end connected to any pads or vias. Loops: A loop route, a traverse that self-forms a loop, may be on one layer or across multiple layers. Widths: Width of the traces, check the width of traces to ensure which are consistent with those defined in CM (Constraint Manager).
Plane islands: Check if there are any islands covered with copper. It is a reminder to designers that Shield Area and negative plating are not checked for islands. Unrouted or partial plane nets: Check the connectivity of all plane layer nets and whether there are plane layer nets that are not copper-fill or are only partially connected.
Parts Unplaced parts, Check for components that exist in the layout database but are not yet placed on the layout. Flex Stackup For checking the layer stackup of flexible circuit, Invalid check will report the discontinuity of the layer stackup. For the rigid-flexible design, check is needed, but other designs can be ignored. Holes/Pads/Vias ➀ ➁ ➂ ➃ ➄
Dangling vias/jumpers: Check for vias or jumpers not connected by traces or plane. Unrouted pins: Check if the pins of the components are connected by traces or plane. Connected unplated pins: Check net connection to unmetallized pins. Incomplete Trace Connection: Check if the trace is not connected Minimum annular ring: Check the minimum ring width of the via, and a warning will be generated if the minimum ring width is less than this setting. The allowable size of the minimum ring width is usually related to the production process. Too small ring widths can easily be cut off during drilling, resulting in a disconnection of the net connection.
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(7)
Vias under ➀ ➁ ➂
(8)
SMD pads: Check if there are vias in the SMD type pad, i.e. drilling holes in the pad, which is not usually allowed in the through hole via design but is often used in the blind buried via design. Top place outline: It is usually allowed if there are any holes underneath the top components, so this check is usually ignored. Bottom place outline: It is usually allowed if there are any holes underneath the bottom components, so this check is usually ignored.
Missing Pads ➀ ➁ ➂
(9)
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All pads on all layer: Check all through pins to make sure they have pads in each layer. All pads on cover and connected internal layers: Check that all the top and bottom pins, as well as the inner pins with trace or plane connections, have pads. Only pads on selected layers: Check if there are missing pads on the layer selected by the user. The user can select the layer in the list box below.
Others ➀ ➁ ➂ ➃ ➄
Part Soldermask Option: Check all component pins for Soldermask. Via Soldermask Option: Check all the vias for Soldermask. Solderpaste Option: Check all SMD pins for Solderpaste. Part Cover Layer Option: Check all pins for Cover Layer, mainly for rigid-flex design. Via Cover Layer Option: Check all vias for Cover Layer, mainly for rigidflex design.
20.2.3 Batch DRC Scheme Batch DRC settings can be saved as a scheme and then reused or edited. When saving, you can choose to save locally or with system files, as shown in Fig. 20.9. Once all settings are complete, the Batch DRC check can be run. When the check is complete, a prompt window will pop up to show how many Hazards have occurred in this design that violate the rules. If no Hazard occur, the DRC check will be prompted to succeed. The DRC check results are placed in Drc.txt file and can be viewed through the File Viewer, as shown in Fig. 20.10.
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Fig. 20.9 Save DRC check scheme
Fig. 20.10 Part of Drc.txt file
20.3 Introduction to Hazard Explorer In addition to viewing Drc.txt file reports, Xpedition provides a more convenient and intelligent DRC viewing method, Hazard Explorer. Menu select Analysis → Hazard to open the Hazard Explorer window. On Explorer, or select the toolbar icon the left side of the window, you can see several TABs, Online, Batch, Summary, 3D Batch, as shown in Fig. 20.11. 1.
Online TAB
First switch to Online TAB, click the Update button above the window, and then view the check results. Referring to Fig. 20.11, Online (27) is displayed at the top of the list, indicating that there are 27 Hazards in the Online DRC, 5 Hazards on the Components (5), 14 Hazards on the Pad Entry (14), and 0 in parentheses indicating that there is no Hazard on the item. Click Pad Entry, list the contents of the 14 Hazards on the right, click on an item, and you can see the exact location of the Hazard in the design window on the right, as shown in Fig. 20.12. Generally speaking, Online Hazards are not serious, such as Pad Entry Hazard, which indicates that the direction in which the pad is going out is not in the set direction, and such Hazards are generally acceptable with process permits.
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Fig. 20.11 Hazard Explorer window
Fig. 20.12 Find Online hazard location through Hazard Explorer window
Online Hazards is the result of Online DRC checks, which are automatically updated in real time as design changes occur without running a special DRC checking command. When a designer corrects an Online Hazards, it automatically disappears from the Hazards list, and all Online Hazards should be checked for correction or accepted by the designer. 2.
Batch TAB
Batch Hazards is a violation result of Batch DRC checks, including 18 check items such as Proximity, Hanger, Trace loop, EP Violations, Missing Pad, Wirebonds, etc. Some projects have subitems below them, which you can expand by clicking on the + above. The same with before, Proximity (5) indicates that the item has five Hazards, and zero in parentheses indicates that the item does not have a Hazard. Click Proximity, list all Hazards on the right, click on an item, and you can see the specific location of Hazards in the right design window, as shown in Fig. 20.13. In general, Batch Hazards are more severe than Online Hazards and need to be focused, such as Proximity, which often indicates a conflict between design elements and board outline that requires modification or confirmation. Figures 20.13, for example, show that there is a conflict between the device pad and the board outline.
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Fig. 20.13 Find batch hazard location through Hazard Explorer window
In this type of design, it is unavoidable because the pad needs to exceed the board outline, so there is no need to modify it in this design, just confirm it, click on the Accept Selected Hazards above the window to accept the Hazards, the word for the Hazard will turn green, and the next time you run Batch DRC, the Hazard will not be reported again. Other Batch Hazards also need to be checked and confirmed one by one. If the Hazards are modified and Batch DRC needs to be rerun to confirm that the Hazard has been successfully modified, the checks can only be performed on the net to which the Hazard belongs (Check selected nets only) to save time. Designers can also find and change all Hazards as described above, rerun Batch DRC, check the entire design, and verify that all Hazards have been successfully modified. Some Hazards are artificially created by the designer during the design process because of the special needs of the design. For example, the border of some plug-in components will be placed outside the Board outline, which requires only designer confirmation. When all Hazards have been checked for changes or confirmations, rerun the Batch DRC and review the entire design until the DRC is completely passed or accepted by the designer. 3.
Summary TAB
Summary TAB is used for statistics and summary of design elements and contains four items: ➀ Length Summary ➁ Estimated Delay Summary ➂ Electrical Net Length Summary ➃ Estimated Electrical Net Delay Summary. (1)
(2)
Length Summary, which lists the length, Meander, and meander percentage of all physical nets in the design. In this list, we can see the length of each net, and whether to increase its length by winding it. Click on a net name in the list, and the net is selected and highlighted in the design window, as shown in Fig. 20.14. Estimated Delay Summary, which lists the delays for all nets in the design, including open nets, where the delay is estimated by dividing the length of Manhattan by the propagation speed of the first internal signal layer.
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Fig. 20.14 Length summary list and net highlighted
(3)
(4) 4.
Electrical Net Length Summary, which lists the electrical nets in design and the lengths, Meanders, and Meander percentage of all physical nets that make up each electrical net. Electrical nets differ from physical nets in that they usually do not contain the length of the bond wire, but nets before and after the resistor may be recognized as the same electrical net. Estimated Electrical Net Delay Summary, which lists delays of all electrical nets. 3D Batch TAB
Through the Summary TAB window, you can have a detailed length and delay statistics for the entire nets of your design, which is important for designs with length requirements. In addition, the statistical results can also output text, which is easy to above the window to output write documents. Click the Report all Hazards icon the status of the current window to a text file. The 3D Batch TAB is used to display the inspection results of the 3D DRC, and as before, the number of Hazards is shown in parentheses. It is important for designers to note that 3D DRC requires rules to be set in a 3D environment and DRC checks to be run. Once the results are obtained, they can be viewed in Hazard Explorer, as shown in Fig. 20.15.
Fig. 20.15 3D batch DRC check results list
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Fig. 20.16 3D clearances settings window
Next, we’ll look at how to set up rules and checks in a 3D environment. First, select 3D → Clearances from the menu and open the 3D Clearances settings window. The first item is the default item, which cannot be changed at present. Designers can add settings as shown in Fig. 21.16. Minimum XY and Minimum Z set the minimum XY and Z spacing. Rule violation is reported as error. Optimal XY and Optimal Z set the best XY and Z spacing and rule violation is reported as Warning. After setup, menu selects 3D → Batch DRC → Full Design, runs 3D DRC checks, after checking, click on the list to see the elements violating in 3D window. For example, the two Bond Wires shown in Fig. 20.17a are less than the set distance of 25 µm and are reported as errors. You can see the other elements by clicking the mouse in the 3D window. From Fig. 20.16b, you can see that the two Bond Wires are
Fig. 20.17 3D DRC check results window
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bonded to the same Bond Finger and belong to the same net, so the distance rule can be relaxed and the 3D DRC can be accepted after confirmation with the processing. In the same way, browse and confirm the other report entries until all the issues have been modified or confirmed.
20.4 Design Library Check Select Analysis → Compare Local Library to Center command from the menu to compare the differences in components, pads, vias and holes between the current local library and the project’s central library. Generally, there are the following situations: (1) older than the central library, (2) newer than the central library, (3) database data that exists only in the local library. VerifyLocal2CentralLibrary.txt file opens automatically after checking and reports the results of comparisons between Pad, Padstack, Cell, Part items and the central library. Figure 20.18 shows the contents of the summary section of the file. The main reasons why the local library cannot match the central library completely are as follows: (1) the central library data is updated during the design process; (2) the designer edits the local library data during the design process. If the local library is to be consistent with the central library, use the menu command ECO → Update Cells & Padstacks or the ECO → Replace Cell command to synchronize the local library with the Central Library data. In general, the Update Cells & Padstacks command is mainly used to synchronously update elements such as the position and shape of the component’s pad. The Reset function in the Replace Cell command is mainly used to synchronously update the literal elements such as the outline and reference designator of the component. If you need to preserve attributes such as position and size of text that has been adjusted in the layout, check option Keep text attribute during replace, and the text attributes will be preserved.
Fig. 20.18 The summary section of the report file between local library and central library
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After checking the entire design, you can prepare the output of SiP production data.
20.5 Production Data Classification SiP production data are divided into the following categories. ➀ ➁ ➂ ➃ ➄
Gerber and drilling data for production of SiP substrates. Data such as Drawing files and component coordinates for SiP assembly (adhesive, bonding, welding, etc.). GDS files for production of Interposer or RDL in SiP and advanced packaging. BGA Color Map for SiP design checking and board level debugging. Mechanical design data for the production of plastic Molding, ceramic and metal encapsulated shells.
Since Mechanical design data such as Molding and encapsulated shells are not part of this book’s discussion, this chapter focuses on how to output the first four production data in Xpedition. Some design engineers are accustomed to sending SiP or PCB layout design files directly to factories for inspection and production processing, which has many drawbacks. For example, it seriously affects the protection of intellectual property rights, causes the leakage of design data, and is not conducive to design engineers learning and understanding of production technology. The standard practice is to convert the layout design files into Gerber and drilling data and hand them to the manufacturer. The Gerber file format, which is the intermediate medium for design and manufacturing, was originally developed by Gerber Corporation in the United States and later became an industry standard data format. Gerber is a collection of formats that describe PCB or package substrate layout (trace layer, soldermask layer, silkscreen layer, etc.) and is the standard format for image conversion in the industry. Now owned by Belgian Ucamco Company. There are three versions of Gerber available: • Gerber X2, the latest Gerber format, inserts layer stackup information and attributes of the board • Extended Gerber, or RS-274X, is currently in general use • The standard Gerber, RS-274D, is an older version that has been gradually discarded and replaced by RS-274X Next, we will describe how to output production files in various formats one by one.
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20.6 Gerber and Drill Data Output 20.6.1 Drill Data Output In Xpedition Layout or XPD, select Output → NC Drill from the menu and open the NC Drill Generation window. (1)
Drill Options TAB, shown in Fig. 20.19a. ➀ ➁ ➂
➃ ➄
NC Drill machine format file, there are two file formats to choose: DrillEnglish.dff is British format, DrillMetric.dff is metric format. NC Drill output directory, which defaults to Output\NC Drill subdirectory in layout directory. Drill Generation Option, Sweep axis chooses the direction of the scan axis, which is divided into horizontal and vertical directions; Bandwidth, scan bandwidth, which defaults to 100th in British units or 2500 µm in metric units. Designers can make reasonable adjustments based on the design density of the substrate. If the substrate route density is high, choose a smaller Bandwidth to avoid the impact of drill back and forth movement on drilling efficiency. If the substrate route density is loose, you can choose a larger Bandwidth to improve the scanning speed. Predrill holes larger than, if the hole diameter is large, you can choose to drill a small positioning hole in advance and then drill a precise hole, which is conducive to the accurate positioning of large holes. Drill file header and Drill file notes are annotated by the user, with the text added at the beginning and end of the drill file respectively.
Fig. 20.19 Drill options and drill chart options
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Drill Chart Options, Fig. 20.19b shows the Drill Chart Options TAB. ➀ ➁ ➂
➃ ➄ ➅ ➆ ➇ ➈ ➉ (3)
Columns bar, which is mainly used to set the content items to be displayed in the drill drawing and the arrangement of each text, can be created or deleted by the designer from existing items. Text Setting, mainly sets the parameters such as font name, font size, line spacing, pen width, display precision, default tolerance and so on. Auto assign drill symbols, the system automatically selects how the drill symbol (that is, the user did not specify it) is selected. Character indicates that the automatic selection is displayed as text, and Symbols indicates that the automatic selection is displayed as symbols. All spans on single chart, if checked, indicates that all drill chart are in the same table. If unchecked, the blind or buried holes defined by different layers are displayed separately in different charts. Drill symbols on separate layers, if checked, output drill drawings to different user-defined layers for easy viewing and printing. Include contours, if checked, contains Contours in the drill drawing. Line separators, which add split lines to the drill chart, include Horizontal split lines and Vertical split lines. Text format, the text format in the drill chart. Include Title case or Upper case. Drill chart title, with the title of the drilling chart added, is located at the top of the drill chart and is generally centered. Special notes, located at the bottom of the drill chart, are normally displayed in left alignment.
Drill Symbols TAB
Drill Symbols TAB is mainly used to define the symbols of drill holes at design level. For different holes, corresponding symbols or characters can be defined to represent them. Designers also have the option of automatically specifying or not generating drill symbols by system. Figure 20.20 show Drill Symbol with text A and Drill Symbol with symbol , respectively. The following choices can be made in the Assignment Method drop-down list: ➀ ➁ ➂ ➃
Automatic assign during output: When the drill hole is output, the drill symbol is automatically selected by the system. None: No drill symbols are generated. Use character as drill symbol: Use text as drill symbol, optionally 26 English letters. Use drill symbol from list: Use a graphic as drill symbol and select it from the list below.
Custom Columns TAB and FCF TAB are usually unchanged, leaving the default settings intact. After the setup is completed, click the OK button, the system automatically runs, and generates drill files, which are placed under the Output\NC Drill folder.
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Fig. 20.20 Drill symbols TAB
The number of drill files varies depending on the user’s layer stackup settings. Figure 20.21 shows the definition of layer stackup in layer 1 to layer 6 and the corresponding drill file generated. Open the Drill Drawing related display options in Display Control to get the drill Drawing and drill charts as shown in Fig. 20.22. After the drill data is generated, to avoid errors, the drill data needs to be checked. The designer can import the Drill data through third-party tools such as CAM350 to check. Drill data can also be imported into Xpedition for inspection. To import drill data in Xpedition, first use FabLink License, menu select Setup → License Modules → Acquire Xpedition FabLink, if you use Layout301, because it contains FabLink license, no operation is required.
Fig. 20.21 6 Layers substrate stackup definition and drill files generated
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Fig. 20.22 Drill drawing and drill chart
Fig. 20.23 Import drill data for inspection
Then, select File → import → Drill from the menu, import the drill data, and open the imported drill layer from Fab → User Draft Layers in the display control to view it, as shown in Fig. 20.23.
20.6.2 Gerber Machine Format Before performing Gerber output, the first step is to set Gerber Machine Format. Menu selection Setup → Gerber Machine Format, pop-up window as shown in Fig. 20.24. Normally, you can just leave the default options as shown in Fig. 20.24, which are explained in Table 20.1.
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Fig. 20.24 Gerber Machine Format setup
20.6.3 Gerber Data Output Gerber data for SiP and advanced packaging substrates are different from Gerber data for ordinary PCB boards and usually do not require Silkscreen screen layer. The main reasons include the following two points: first, the size is too small to print; second, comparing to PCB design, the number of SiP components is relatively small, which is easier to distinguish and identify. Therefore, the Silkscreen layer is generally not included in the Gerber data for SiP and advanced packaging substrates. Gerber data of a typical SiP substrate is composed of Signal layer, Plane layer, Soldermask layer, Solderpaste layer, Drill drawing layer, and so on. Designers can also add or delete related data according to the needs of actual projects. For example, Bond Wire layers are often added to the Gerber output of SiP. On Xpedition menu bar, click Output → Gerber to open the window shown in Fig. 20.25. The Gerber Plot Setup file is used to save the user’s settings and the Gerber Output Directory is used to set the output path of Gerber file. (1)
Parameters TAB ➀
➁ ➂ ➃
Output files are mainly used for creating and naming Gerber output files. Users create and give file names with corresponding meanings based on the layers they need to output. Its file name is usually suffixed with.gdo, as shown in Fig. 20.25a. D-Code Mapping File select Automatic. Header text and Trailer text are used to add comment text at the beginning and end of the file. Generate Macros, which generate user-defined apertures with shapes and lines. Offset from origin, which defines the offset of the Gerber data from the origin of the coordinates, is usually set to (0, 0).
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Table 20.1 Interpretation of Gerber Machine Format setup Parameter name
Options
Interpretation of meaning
Data type
274X/274D
The 274X format contains the aperture table information used. The 274D format does not contain aperture information and requires additional aperture tables to support it
Data mode
Modal/Non-modal
Modal, compact mode, where previously occurring data only appears in later descriptions if there is a change. For example, if the X coordinate does not change in the coordinate description, the X coordinate will not appear in the subsequent description and will reappear only if it changes. No-Modal, non-compact mode, all data appears in each description
Step mode
Absolute/Incremental
Absolute: Location information gives absolute coordinates relative to the origin of the substrate Incremental: Location information gives relative coordinates
Data format
0 ~ 5, 0 ~ 5
Set the number of digits before and after the decimal point, which can be set to 0–5. The default is 2 digits before the decimal point and 4 digits after the decimal point
Zero truncation
Leading/Training/None
Leading, eliminates the previous zero; Training, eliminates the latter zero; None, does not operate on zero
Character set
ASCII/EBCDIC
ASCII(American Standard Code for Information Interchange is the most widely used encoding method. Files encoded with ASCII codes are called ASCII files EBCDIC(Extended Binary-Coded Decimal Interchange Code)is an 8-bit character encoding developed by IBM for its mainframe Usually ASCII code is selected
Arc style
Quadrant/Full Circle/None
Quadrant is an arc format that converts all circles into four arcs. Full Circle, generating a complete arc. None, there are no arc segments, all arcs are roughly fitted by straight lines
Delimiter
*/#/@
Set the separator, optional ‘*’, # and ‘@’ separators (continued)
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Table 20.1 (continued) Parameter name
Options
Interpretation of meaning
Comments
On/Off
Choose whether to insert Comments in the output file, either On or Off
Sequence number
On/Off
Whether to add a sequence number to the file, choose On or Off
Unit
Inch/mm
Unit, inch or mm optional
Polygon fill method
Raster/Draw
Polygon fill method, Raster mode and Draw mode are optional. Raster mode is only available when 274X is selected
Fig. 20.25 Gerber output parameters TAB and contents TAB
➄ ➅ ➆ (2)
Copy Options, used to generate multiple copies of files, usually keep default. Space between origins, sets the spacing when you choose to generate multiple copies of the files. Data type, are consistent with the definition in the selected Gerber Machine Format file, and the user only needs to select the defined file.
Contents TAB
The main purpose is to select the output content corresponding to the output file defined by the designer. There are five main options: Conductors, Board items, Userdefined layers, Cell types, Cell items. As shown in Fig. 20.25b. ➀ ➁
Conductors contain content related to metal conductors, usually including elements related to conductive layers in substrate, such as Bond fingers, pads, traces, vias, etc. Design items, the related content of the board, mainly including Board outline, Cavity, Contours, Silkscreen, Soldermask and so on.
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Fig. 20.26 Output bondwire graph (partly)
➂ ➃ ➄
User-defined layers, contain all user-defined layers and content imported from outside. Cell Types, which contain all Cell types in this design, are available for designers to choose from. Cell items, which contain content related to Cell, such as Bond Wire, Die Pin, Placement Outline, Assembly Outline, etc. Select the layer first, then the elements in that layer.
In Xpedition, the content definition of a Gerber file is flexible, allowing users to combine different options to form the desired Gerber file. For example, designers need to output a Bondwire file as a bond graph, and they can choose the combination shown in Fig. 20.25b. The Gerber file for the output bond graph is shown in Fig. 20.26. For the output of Gerber files, designers can configure it with reference to Table 20.2. Not all designs will encounter User-defined layers, so they are not covered in this table. If the design requires, the designer can define the appropriate user-defined layer and add it to the corresponding output file. Once all the required layer configurations are complete, click the OK button to generate the Gerber file. The generated Gerber data files are placed in the Output\Gerber subdirectory under the layout design directory, with each layer being a separate file.
20.6.4 Import and Check Gerber Data After Gerber data generated, to avoid errors, Gerber data needs to be checked and validated. Designers can check Gerber with third-party tools such as CAM350 or import Gerber data into Xpedition. First enable the license of Fablink XE, select setup → license modules → acquire Fablink XE or acquire Fablink XE Pro from the menu. Then, select File → import → Gerber from the menu to import Gerber data.
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Table 20.2 Configure Gerber file output Output file
Conductor layer Conductor items
Board items
Cell types
Cell items
Bondwire.gdo
Signal layer1
Bond fingers
Board outline
IC-Bare Die
Layer1: Bond wires Die-pins
Positive metal layer (positive)
Corresponding metal layer
Select all (except Via Holes)
Board outline
Select all
None
Negative metal layer (negative)
Corresponding metal layer
Plane data
Board outline
Select all
None
Soldermask top
None
None
Board outline Soldermask top
Select all
None
Soldermask bottom
None
None
Board outline Soldermask bottom
Select all
None
Solderpaste top
None
None
Board outline Solderpaste top
Select all
None
Solderpaste bottom
None
None
Board outline Solderpaste bottom
Select all
None
Finally, open the appropriate layer in the display control to view it, as shown in Fig. 20.27.
Fig. 20.27 Import and check Gerber data
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20.7 GDS File and Color Map Output In the substrate production, we need to output NC Drill and Gerber files. For Silicon Interposer and Fan-In, Fan-Out RDL, we often need to output GDS files. In addition, the Color Map of BGA needs to be output in order to inspect the pins quickly and to facilitate the design and debugging of downstream PCB. Next, we’ll look at the output methods for both files.
20.7.1 GDS File Output Here we take XPD output as an example. In Layout 301, the operation method is basically the same. Menu select File → Export → GDSII, GDSII Export window pop-up, as shown in Fig. 20.28, configuration as follows: (1)
File Setup TAB, Fig. 20.28a ➀ ➁ ➂
GDSII Layers to process, select the layer you want to output, and the layer checked in the front box will be output. GDSII Layers, select the maximum number of layers allowed in the GDSII file, 64 or 256. Output Options, Use strokes for text strings, replace text characters with strokes. Use hierarchical structures, output GDSII files in a hierarchical form. Line segments per circle, which defines the number of lines to simulate a circle, defines the precision of the circle in the GDSII file.
Fig. 20.28 GDS file output window
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Units, which define the units of output, are usually the same as those in the design. Path type, which defines the type of line end. GDSII file, which defines the path to save the GDSII output file.
Content TAB, Fig. 20.28a. ➀ ➁ ➂ ➃ ➄ ➅
GDS setup file, which saves the user’s configuration. Output Layer, which can be selected from the drop-down list. Layers bar, select the items the checked layer needs to output, in Items bar you can use Ctrl and Shift keys to assist in selecting multiple items. Design items, select the design items that you want to output to the GDS file. Cells, select the different elements of the Cell types, items, and corresponding layer that you want to output to GDS file. Die Pins, select the Die Pins that need to be output to GDS file.
Once all options are set, click Ok or Apply to output GDS file, which is located in the set path and can be sent to the manufacturer for production or technical communication. In addition, there is an option to output GDS in Package Utilities, limited to the length of the chapter, which is not descripted here and can be tried by the reader.
20.7.2 Color Map Output When output a Color Map, you first need to define the color of the net, so that you can have colors when output. For a net without a color defined, the net in the output Map is colorless. In XPD or Xpedition Layout, you can define the color of the net through Display Control → Graphic → Nets, as shown in Fig. 20.29.
Fig. 20.29 Define the color of nets in XPD or Xpedition layout
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Then, in XPD, select File → Export → Color Map from the menu, set the path of the output file in the pop-up window, the Component that need to be output, and the output units, etc. as shown in Fig. 20.30. Then click the Export button. When the output is complete, use Excel to open the output XML file in the set path, as shown in Fig. 20.31. For Xpedition Layout, since there is no Color Map option in File → Export menu, another way to do this is to select Package Utilities → Export → BallMap (xml) from the menu.
Fig. 20.30 Output color map options
Fig. 20.31 Open the output color map file in Excel
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20.8 Other Production Data Output 20.8.1 Component and Bond Wire Coordinate Output After processing SiP substrate, the next step is to install the bare chip, resistor, capacitor and other components on the substrate through different processes. The coordinate information of the component is required regardless of the process. For wire bonding process, the coordinate information of the Bond Wire also needs to be output. Menu select File → Export → General interface, select Generic AIS in the pop-up window, and click the OK button, as shown in Fig. 20.32. When the file generation is complete, the software will pop up a prompt window indicating that the file has been successfully generated and vb_ais.txt file can be found in the Output subdirectory of the layout design directory. Open this file to view its file format, as shown in Fig. 20.33. The contents of the file are divided into seven columns, each of which is explained below.
Fig. 20.32 Output Generic AIS file
Fig. 20.33 vb_ais.txt file format
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• The first column is the reference designator of components, or the name of Bond Wires. • Column 2 is the Part Number of the component, which is NULL for Bond Wire. • Column 3 is the rotation angle of the component, which is 0 degrees for Bond Wire. • The fourth and fifth columns are the (X, Y) coordinates of the component, and for Bond Wire, the coordinates of the chip to which the Bond Wire is connected. If Bond Wire is a Die to Die connection between chips, it is the coordinate value of the starting chip. • The 6th column lists the position of the component or Bond Wire, the top or bottom of the substrate. • The 7th column lists whether the component or Bond Wire is mirrored, usually NO. Designers can generate accurate coordinate report files for the start and end points of Bond Wire if required for production processing. This file can be obtained by running the WireReport.vbs file which is located in \SDD_HOME\standard\examples\pcb\Automation\Scripts folder under the installation directory, just select it and drag it to the design window. When the file generation is complete, a prompt window automatically pops up, giving the name and path of the generated report file, usually in the Output folder of layout design. Open the Wirebonds.txt file located under the Output folder of layout design, the format shown in Fig. 20.34. The contents of the file are divided into 10 columns, each of which is explained below. • • • • • •
Column 1 is the name of Bond Wire Columns 2, 3, and 4 are the (X, Y, Z) coordinates of the Bond Wire start point Column 5 is the layer at which the starting point is located Columns 6, 7, and 8 are the (X, Y, Z) coordinates of the Bond Wire end point Column 9 is the layer at which the end point is located Column 10 is the model used by the Bond Wire
Fig. 20.34 Bond wire report file format
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Designers can also refer to the format of WireReport.vbs and write their own scripts for non-standard files or data output. Due to the size of the book, it is not detailed. Readers can refer to Xpedition user guide.
20.8.2 DXF File Output DXF file is a file format developed by Autodesk for CAD drawing data exchange between AutoCAD and other software. Since AutoCAD is now the most popular CAD software, DXF has also been widely used as a de facto standard. DXF is an open vector data format, and most CAD software can read or output DXF files. Output DXF file in Xpedition, select File → Export → DXF from the menu, and the system pops up the window shown in Fig. 20.35a. Select the file path and file name you want to output, select the appropriate Units, check the layer you want to output, and click the OK button to output DXF. If the designer has designed chip layout and cavity in tools such as AutoCAD, it can also be imported to Xpedition through DXF file format for reference design. Select File → Import → DXF from the Xpedition menu to import files in DXF format. As shown in Fig. 20.35b.
Fig. 20.35 DXF file export and import window
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Fig. 20.36 Design status file format
20.8.3 Layout Design Status Output For complete understanding of the current layout design status, you can output a design status file by selecting Output → Design Status from the menu. The file contains basic information such as substrate size, layer stackup, via setting, net, components, Bond Wires, etc. The specific content is shown in Fig. 20.36.
20.8.4 BOM Output During the schematic design phase, Partlist can be output as a list of components for production and procurement. Correspondingly, after layout design is completed, the BOM of the component can also be output as the final production basis, because at this time the design status is fixed and the component will not change. Menu selection Output → Bill Of Material, pop-up BOM output window, as shown in Fig. 20.37. First in the Bill of Material file column, set the path of the output file, then in Setting, configure the items of the BOM. ➀ ➁
The tick option after Part Number indicates that Part Number is used as the classification criterion in the BOM. The tick option after Reference Designator indicates that Reference Designator is used as the classification criterion in the BOM.
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Fig. 20.37 BOM output interface
➂ ➃ ➄
The up and down arrows control the order of entries in the BOM. The tick option before each entry indicates whether or not it appears in the BOM, and the Title of the entry is editable, allowing the designer to change the naming style. With option Include user properties checked, you can include user-defined attributes in the BOM and select the entries you want to output in the user-defined attribute area on the right. When option Include mechanical cells is checked, the BOM contains mechanical Cells, such as the interposer used in chip stack.
Once the settings are complete, you can click the Save icon to save the schema scheme of the settings, then click the OK button or the Apply button to output the BOM. Find the BOM file under the set path and open it in a text editor. You can see the BOM format as shown in Fig. 20.38. The first half of the file is sorted using Part Number as the classification criterion, and the second half is sorted using Reference Designator as the classification criterion. In addition to bare chips, resistors, capacitors, and BGA packages, BOM also includes interposer in chip stacking design.
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Fig. 20.38 Output BOM (contains two classification criterion)
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Chapter 21
SiP Simulation and Verification Suny Li
21.1 Overview of SiP Simulation and Verification With the rapid development of SiP and Advanced Packaging technology, the complexity of design is increasing. The main manifestation is that there are more and more layers of the substrate, and more and more chips and passive components are integrated on the substrate. The bare IC chips are becoming more and more complex, the number of pins is increasing, and the working frequency is also improving. At the same time, the density of routing on substrate is also increasing, and the signal frequency transmitted is also enhancing rapidly. In addition, the use of multiple substrates within a package is becoming more common. With the improvement of chip performance and design complexity, the problem of high-speed circuit becomes more and more prominent, which directly affects the performance and reliability of SiP system. Without simulation, directly designed systems usually do not meet the design requirements. For example, the designed SiP can only work at lower clock frequencies than specifications. Strict screening of the chip is required for system to work properly, sometimes even rework the design several times. To solve these problems, advanced SiP design platforms are needed, strict SiP design processes and specifications are formulated, and the experience of engineers is relied on for circuit design and problem investigation. At present, the experience of engineers in SiP and Advanced Packaging design is far from comparable to that in PCB design. Because PCB design technology has been relatively mature for many years, SiP and Advanced Packaging design have only become popular in recent years. The lack of design experience requires designers to learn more from various simulation tools to ensure the success of the design.
S. Li (B) Beijing, China e-mail: [email protected] © Publishing House of Electronics Industry 2022 S. Li (ed.), MicroSystem Based on SiP Technology, https://doi.org/10.1007/978-981-19-0083-9_21
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Fig. 21.1 SiP and advanced packaging simulation and verification tools
Therefore, after a SiP design is completed, simulation is an essential means to ensure that the design version is as successful as possible. The simulation ensures that the product has good signal integrity, power integrity, good heat dissipation, and meets various requirements of electromagnetic compatibility. In Chap. 6 of this book, we have known that the simulation tools provided by Siemens EDA (Mentor) cover three aspects: Electromagnetic, Thermal and Force. Among them, the electromagnetic and thermal aspects are more comprehensive, and the force simulation needs to be further improved. Here we will focus on the electromagnetic and thermal simulation. In addition, Siemens EDA also provides electrical verification and Advanced Packaging physical verification tools, which we will describe accordingly. Figure 21.1 provides the SiP simulation and verification tools. For SiP simulation needs, Siemens EDA offers HyperLynx SI for signal integrity simulation, HyperLynx PI for power integrity simulation, HyperLynx Thermal and FloTHERM for SiP thermal analysis. Because SiP differs from PCB in that it is integrated in a variety of ways (see Chaps. 4 and 6 for more details), there are different requirements for simulation tools. For non-planar integration, a 3D solver is required to analyze the nets and extract the corresponding parameters. Siemens EDA provides advanced 3D solvers, including Full-Wave Solver, Fast 3D Solver, Hybrid Solver, which can solve these problems. In the schematic design phase, Siemens EDA provides Xpedition AMS for digital-analog hybrid circuit simulation, which can be directly emulated in the schematic environment based on Designer. In addition to simulation tools, Siemens EDA also provides validation tools, including HyperLynx DRC, an electrical verification tool, and Calibre 3DSTACK, an Advanced Packaging physical verification tool. Limited to length, some tools are described in more detail, and their simulation methods are illustrated with examples. Some tools are only briefly described their functions.
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21.2 Signal Integrity Simulation Signal integrity refers to the waveform quality of the signal at the receiver, sender and transmission path, which is mainly manifested in such aspects as delay, reflection, crosstalk, time sequence, oscillation, etc. With the increasing frequency of signal, the problem of signal integrity becomes more prominent. The frequency and characteristics of bare chip, the physical parameters of the substrate, the layout of the chip on the substrate, and the routing of high-speed signals all probably cause the signal integrity problems, which lead to the instability of the system operation and ultimately the system design failure. Taking full account of signal integrity factors and taking effective control measures will effectively improve the signal integrity problems in SiP design.
21.2.1 Introduction to HyperLynx SI HyperLynx SI is a widely used simulation tool for signal integrity of high-speed circuits. Including pre-simulation environment (LineSim), post-simulation environment (BoardSim) and multi-layout analysis functions, embedded DDRx and SerDes analysis wizard, can help designers to simulate signal integrity, crosstalk, DDRx and SerDes analysis and validation, eliminate design hazards, and improve the success rate of design. HyperLynx SI is widely compatible with layout design files from many manufacturers, such as Siemens EDA, Cadence, etc. From net topology planning, impedance design, high-speed rule definition and optimization at the beginning of the design, to final layout validation can be completed in HyperLynx SI. Figure 21.2 show the HyperLynx SI simulation screenshot. (1)
Pre-simulation LineSim
Pre-simulation LineSim can analyze the “What-If” hypothesis of the high-speed signal in the schematic diagram before layout and routing, inspect the signal transmission effect under the virtual layer stackup and routing parameters, and help the designer optimize a set of layout layer stackup, routing impedance and high-speed design rules suitable for the current design. LineSim can automatically connect with the schematic design tool Designer and import the topological structure model of the key nets in the schematic diagram. By investigating the overimpulse/underimpulse, delay, crosstalk and other indicators, it can verify whether the assumptions in the process of SiP product design are reasonable. A set of constraints, such as layer stackup, topology and routing parameters, suitable for such critical nets is obtained by simulation debugging. These constraints can be passed back by LineSim to Designer to form routing rules, which can be transferred to the Xpedition layout design environment to implement rule-driven routing.
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Fig. 21.2 HyperLynx SI simulation screenshot
(2)
Post-simulation BoardSim
Post-simulation BoardSim can import Xpedition layout design files, extract layer stackup and physical parameters, calculate transmission line characteristic impedance, and conduct signal integrity, crosstalk and electromagnetic compatibility analysis. BoardSim can perform interactive simulation analysis on a single net to output accurate signal transmission waveforms or signal eye maps. Designers can modify various matching, passive element parameters and other information of the net in BoardSim. BoardSim also has Batch Simulation capabilities to quickly scan all nets in the layout, discover nets with overshoots, delays, crosstalk and EMI radiation that exceed design requirements, and give detailed analysis reports. (3)
Multi-Layout Analysis Function
The multi-layout analysis function can analyze the signal integrity of a system consisting of multiple SiP layouts, as well as provide practical solutions to the more popular Advanced Packaging systems that contain multiple substrates in a single SiP (such as Interposer + Substrate). The multi-layout analysis function is also applicable for the user to place the designed SiP in the PCB system for co-simulation. Through multi-layout analysis, the transmission effect of key nets on multiple layouts is examined to help designers quantify the impact of cross-substrate transmission on signal working status. (4)
DDRx and SerDes simulation capabilities
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The DDRx wizard guides designers through step-by-step analysis of the signal integrity and timing of the entire DDR interface, supporting a variety of DDR, LPDDR, and NV-DDR technologies. Designers can use parameter scan analysis to determine the best ODT settings, support JEDEC standard parameterized modeling of DRAM controllers, and output reports provide simulation results such as design margins, eye maps, and measured waveforms. The SerDes wizard supports over thirty different standard protocols, including Ethernet, OIF-CEI, PCIe, Fiber Channel, USB, and JESD based technologies, a built-in COM/JCOM analysis engine, full support for IBIS-AMI models, integration of dedicated 3D EM solvers, and the creation of parameterized 3D via models and PCB cross-section models of any structure. (5)
Model Output Function
HyperLynx SI supports S-Parameter, SPICE model output function, which outputs the nets on the layout, including vias, transmission lines, IC pins, matching circuits, etc., to S-Parameters or SPICE format simulation models. HyperLynx SI is compatible with simulation models of many formats, such as IBIS, SPICE, S-Parameter, etc. HyperLynx SI provides powerful IBIS model library support for high-speed simulation, including IC models for standard processes such as CMOS/TTL, CPU/DSP, and IBIS models for devices such as FPGA/CPLD.In addition to the powerful model library support, HyperLynx provides a model creation wizard. Designers can create simple MOD simulation models or IBIS models in standard format by simply entering information such as switch time, parasitic parameters, process type of component pins.
21.2.2 Signal Integrity Simulation Example The following is a brief introduction to the HyperLynx SI simulation process with a SiP design example. 1.
Design Data Transfer
Figure 21.3 show a 3D screenshot of a Dual-SoC SiP layout consisting of two SoCs designed in Xpedition. From the Xpedition menu, select Analysis_Export to HyperLynx SI/PI/Thermal, and the system automatically transfers data to the HyperLynx SI/PI/Thermal environment and opens HyperLynx. In HyperLynx SI, Dual-SoC SiP designs can be automatically imported as shown in Fig. 21.4. 2.
SI Simulation of Key Signals
First, the SI simulation of key signals is performed. Click the Select Nets button in the toolbar of the HyperLynx SI simulation window, and in the Select Net by Name window that pops up, select the key signal that needs to be simulated. HyperLynx supports simultaneous simulation of multiple critical signal nets. The software has
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Fig. 21.3 3D screenshot of SiP layout design in Xpedition
Fig. 21.4 SiP design imported into HyperLynx
no limit on the number of simultaneous simulation nets, but choosing too many nets will affect the simulation speed. In this example, we choose HSPEED_IO4 ~ HSPEED_IO7 four nets, as shown in Fig. 21.5. After selecting the net, except HSPEED_IO4~HSPEED_Outside IO7 net, other in the toolbar, click the nets are faded. Then click the Assign Models button Select button in the pop-up model specifying window, and pop-up the Select IC model window to select the model for the chip. Note that before choosing a model,
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Fig. 21.5 Select the critical signal nets to simulate
if you download it from the website yourself, you can add the model path to the Directories list through the Models → Edit Model Library Paths. Select Model SiP_SoC1.ibs for U1, and select the corresponding Signal D3\D4\D5\D6 one by one. Select Model SiP_SoC2.ibs for U2, and select the corresponding Signal DATA3\DATA4\DATA5\DATA6. As shown in Fig. 21.6. In the Buffer Settings bar, set the four pins of U2 as Output, the four pins of U1 as Input, and for P1 (BGA package pins), we don’t set them first, as Fig. 21.7 shows. When the setup is complete, close the model specifying window, then click the menu to select Simulate SI → Run Interactive Simulation, or click the icon button to start the digital oscilloscope and simulate, the settings as shown in Fig. 21.8. After the simulation, the simulated waveforms can be seen in the oscilloscope window. The waveforms of all detection points are shown on Fig. 21.8a, and the waveforms of the receiver side are shown on Fig. 21.8b. It can be seen that the signal
Fig. 21.6 Specify models for SoC1 and SoC2
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Fig. 21.7 Specify input and output types for simulation models
Fig. 21.8 Digital oscilloscope display simulation results
quality of the receiver side is not very good, and there are obvious oscillations and overshoots. To improve the signal quality, several methods can be used, such as changing the signal drive strength, changing the design of layer stackup, rerouting and terminal matching. Here, we try the last method. Select Simulate SI → Optimize Termination from the menu or click the Tool to launch the Terminator Wizard, which automatically analyzes the net button and gives the analysis results. As shown on the left side of Fig. 21.9a, the software recommends selecting series resistance matching and giving a recommended resistance value of 25.4 . As recommended by the software, we set Quick Terminator in Assign Model to R Series of 25.0 (which allows some tolerances), as shown on the Fig. 21.9b. Rerun the simulation to get the results, the waveforms of the receiver shown on Fig. 21.10a. To compare the results of two simulations in the same window, select
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Fig. 21.9 Use terminator wizard to add series resistor
Fig. 21.10 Significant improvement of signal quality after adding matching resistor
the Previous Waveforms check box, as shown on Fig. 21.10b. By comparing the two simulations, we can see that after adding a match series Resistor, the rise and fall edges are reduced, the overshoot and oscillation are suppressed, and the signal quality is improved significantly. 3.
Exploration of Package Pin Model
In above simulation, we have no settings for P1 (BGA package pins) model, how to deal with such problems in the actual project? First, in the above simulation, there are already signal output pins (four pins of U2), so the BGA package pins can only be input type. In HyperLynx SI simulation, the input pins can have no model, which is equivalent to when the SiP is welded to the PCB, these nets are not connected to other devices, as shown in Fig. 21.11a. Another scenario is that when SiP is welded to PCB, the nets are connected to other devices on PCB, as shown in Fig. 21.11b. At this time, the simulation needs to consider the effects of routing and other devices on PCB, as well as the connection
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Fig. 21.11 Two scenarios of nets on SiP connected through BGA
of SiP Substrate and PCB Board using multi-layout simulation. Due to the size of the text, the discussion will not continue in this chapter and the readers can try by themselves. 4.
Transmission Path Model Extraction
For SiP or Package designers, it is important to extract model parameters for signal transmission paths that indicate the impact of SiP or Package substrate routing on the signal. Select Export → Net to → S-parameter model from the menu. In the pop-up Extract S-parameter model window, click the button , and the S-port will automatically correspond to the component pins in the net. As shown in Fig. 21.12a, it can be seen that The three ports of HSPEED_IO4 are mapped as 1, 2 and 3; The three ports of HSPEED_IO4 are mapped to 4, 5 and 6; The three ports of HSPEED_IO6 are mapped as 7, 8 and 9; The three ports of HSPEED_ IO7 are mapped to 10, 11, and 12. Then enter the frequency range in the modeling parameters field, such as 0.1– 10000 MHz. In frequency Sweeping Type, select adaptive, and check the option of in the lower automatically display results. After setting, click the button left corner of the window and enter the name of the model to be created, such as HSPEED_IO4-7.s12p in the pop-up window, and then click Save to generate the S-parameter model. As shown in Fig. 21.12b. The software automatically opens the HyperLynx Touchstone Viewer, where you can view S-Parameters for different channels, as shown in Fig. 21.13, which can be used in subsequent simulations.
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Fig. 21.12 Output S-parameter model setting
Fig. 21.13 View S-parameter in touchstone viewer
In addition, you can choose Export_Net To_Free-Form Schematic from the menu to output the selected net to the pre-simulation tool LineSim, as shown in Fig. 21.14. LineSim can modify and edit various parameters of the nets to facilitate various hypothetical analysis and quickly obtain the best design solution.
21.3 Power Integrity Simulation With the continuous pursuit of system performance, the design complexity is gradually increasing, and the signal frequency is also increasing. In addition to the analysis
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Fig. 21.14 Output selected nets to LineSim
of signal integrity, such as reflection and crosstalk, stable and reliable power supply has become an important research direction for high-speed SiP design. As the number of chips increases, the core voltage decreases, and the type of power supply increases, more and more power sources are needed to share the same plane layer. Power fluctuation often has a serious impact on system, so the concept of Power Integrity, referred to as PI, has been proposed. In fact, PI and SI are closely related, but the previous simulation tools generally assume that the power supply is in a stable state when performing signal integrity analysis. However, as the system design requirements for simulation accuracy continue to increase, this assumption is obviously becoming unacceptable, so the research and analysis of PI arises. In a sense, PI belongs to the scope of SI research, and Signal Integrity simulation must be based on reliable power integrity. Although power integrity mainly discusses the stability of power supply, how to reduce noise on the ground is often discussed as part of power integrity because the ground level and the power plane are always inseparable in practical systems.
21.3.1 Introduction to HyperLynx PI With the increase of IC power supply types, power consumption, less noise margin and increasing frequency, it is very difficult to design power supply system rationally. Power integrity analysis becomes an essential part of electronic design.
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Fig. 21.15 HyperLynx PI simulation screenshot
With the HyperLynx PI, power distribution problems can be identified early in the design, problems that are difficult to locate in laboratory tests can be found early in design stage, and solutions can be detected immediately in an easy-to-use “What-if” environment. After Layout is completed, the design can be validated by post-simulation to ensure that all the requirements of the design are met. Figure 21.15 show the HyperLynx PI simulation screenshot. (1)
Analysis of DC drop and current density
HyperLynx PI identifies potential DC power distribution problems. For example, excessive voltage drop will result in IC not working properly due to insufficient power supply voltage. High-density current or excessive via current may generate excessive heat, which can cause interruption of connection or damage to the entire circuit board. The results of simulation can be viewed graphically or the results of simulation can be generated, which can help to quickly find and locate DC power distribution problems. (2)
PDN impedance optimization
HyperLynx PI can help designers optimize the impedance of power distribution net (PDN), help designers determine the optimal decoupling capacitance distribution, including the number of capacitors, installation location, installation method, and obtain the impedance curve of power plane under different capacitor distribution to determine the optimal capacitor distribution.
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On this basis, HyperLynx PI can also help designers to analyze the effect of planar impedance on the propagation of noise on the power plane, and show the propagation of noise on the planar layer through the 3D waveform. (3)
Model Extraction
In areas above GHz, a reasonable parameterized via is very important for the SerDes bus. In HyperLynx PI, high-precision via models can be generated, including decoupling net of the entire substrate, all capacitor and the effect of the vias and plane-toplane resonance. HyperLynx PI allows extraction of PDN models and can be easily applied in subsequent simulations.
21.3.2 Power Integrity Simulation Example Following is a brief introduction to the HyperLynx PI simulation process using the Dual-SoC SiP layout design example. Since HyperLynx PI and HyperLynx SI are in the same simulation environment, there is no need to re-import the design data. 1.
DC Voltage Drop Simulation
Select Simulate PI → Run DC Drop Simulation from the menu or click on the toolbar icon to pop up the DC Drop Analysis window. The power nets in the design are listed. Click on different power nets to see a preview of power plane shape. Select different metal layers and the selected layers will be highlighted, as shown in Fig. 21.16. Next, we take VCCINT and VDD as examples for analysis, in which VCCINT = 2.5 V, maximum current 8A, VDD = 1.5 V, maximum current 10A.
Fig. 21.16 DC Drop analysis interface
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First, select VCCINT and click the assign button in the DC Drop Analysis window to set VRM model and DC sink model in the pop-up window. As shown in Fig. 21.17. In this example, P1 is the power supply device VRM and U1 is DC sink. Press and hold the shift key, select all pins of U1, click the assign button under DC sink model to pop up the window shown in Fig. 21.18a, input the following parameters, then click the assign button under reference net, select reference net as GND, as shown in Fig. 21.18b, and then click OK. Then click VRM manager under VRM model, click New in the pop-up window to open Add/Edit VRM window, input the following parameters, click in power pins, select browse, select all pins of P1 belonging to VCCINT in the pop-up dialog window, and then click OK to return to add/edit VRM window, set ref net to GND, click OK to return to VRM Manager window, and the whole setting process is shown in Fig. 21.19. After the model is specified, in DC drop analysis window, click simulate button to simulate. According to the complexity of the design, the simulation time will
Fig. 21.17 Assign power integrity models for VCCINT
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Fig. 21.18 Setting DC sink model and reference net
Fig. 21.19 Setting VRM model and reference net
be different. After the simulation is completed, two windows can be obtained: 3D graphics display window and report window. The 3D graphics display window is shown in Fig. 21.20. From 3D graphics window, we can see VCCINT is distributed in many metal layers, and the voltage on each layer has slight changes. The maximum voltage drop of VCCINT is 1.1mv, which meets the design requirements.
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Fig. 21.20 Simulation results of DC drop of VCCINT
The report window lists the voltage and current values of all pins, via and trace, and all coordinate points are dynamically linked with the DC drop analysis window. After clicking the option of pin column in the report window, the mouse will automatically jump to the corresponding coordinate points in the graphics window, as shown in Fig. 21.21. Using the same method to simulate the DC voltage drop of VDD, the following simulation results of DC drop can be obtained. From the 3D graphics window, it can
Fig. 21.21 The report window is associated with the graphics window
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Fig. 21.22 Simulation results of DC drop of VDD
be seen that VDD is distributed in multiple metal layers, and the voltage on each layer changes slightly. The maximum voltage drop of VDD is 3.5mv, which meets the design requirements, as shown in Fig. 21.22. 2.
Current Density Simulation
After setting the parameters, in one simulation, not only the simulation results of DC drop, but also the simulation results of current density and via current can be obtained. From the 3D graphics window, select switch graph type to DC current density to view the current density simulation results. The maximum current density of VCCINT is 44.0 A/mm2 , as shown in Fig. 21.23. Select switch graph type to DC via current from 3D graphics window to view the simulation results of via current. The maximum via current of VCCINT is 0.192a, as shown in Fig. 21.24. For VDD net, use the same method, switch graph type to DC current density to view the current density simulation results, and the maximum current density of VDD is 75.6 A/mm2 , as shown in Fig. 21.25. Switch graph type to DC via current to view the simulation results of via current. The maximum via current of VDD is 0.5A, as shown in Fig. 21.26.
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Fig. 21.23 Simulation results of VCCINT current density
Fig. 21.24 Simulation results of VCCINT via current
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Fig. 21.25 Simulation results of VDD current density
Fig. 21.26 Simulation results of VDD via current
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21.4 Thermal Simulation SiP consumes more power in the same area than ordinary packages or PCBs because of its small size, many chips concentrate in a smaller space. SiP consumes a lot of power in small area, so thermal simulation of SiP becomes very important.
21.4.1 Introduction to HyperLynx Thermal HyperLynx Thermal uses a locally variable step finite differential algorithm, which is faster than the traditional finite element algorithm. It can be used for heat conduction, convection and radiation. It also considers whether heat sinks are installed on the device, whether heat conduction holes and heat conduction tubes are installed on the substrate. HyperLynx Thermal can analyze multilayer and irregularly shaped substrates, hybrid or subcircuit boards. The substrate can be cooled by edges in an enclosed space or by forced convection in an open system. The flow of gas can also be natural or forced convection, or the enclosed system can be cooled by a heat exchanger. HyperLynx Thermal models can take into account the effects of gravity, gas pressure and direction of gas flow, anisotropic trace, and the influence of copper on heat transfer. By determining the temperature and temperature gradient of SiP substrate and the temperature of the chip, the designer can easily identify potential thermal and reliability problems in the design. (1)
Component Library
HyperLynx Thermal provides two component libraries (Working library and Master library), which contain a large amount of component information. The Master library contains more than 2000 defined components and allows users to expand. Devices built in the working library can be conveniently stored in Master library, and the heating simulation design can be reused. (2)
Component temperature
The objective of thermal analysis is to obtain the temperature of IC devices and their junctions. HyperLynx Thermal calculates the average temperature of IC devices, calculates the junction temperature of IC devices, and displays the temperature of IC devices with color cloud maps. It is easy to quickly find components with higher temperatures, and the temperature values can also be output through a numerical table. (3)
Temperature Cloud Map
The temperature cloud map of HyperLynx Thermal reveals heat conduction on the SiP substrate. Because the thermal expansion is proportional to the temperature, the high temperature area in the work may expand and warp, which causes the connection to
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be detached. The hot spots on the circuit board can be quickly identified by simulation during the design phase. (4)
Temperature gradient cloud map
HyperLynx Thermal outputs a temperature gradient cloud map over the entire SiP substrate. Because of thermal expansion, high gradient areas cause high thermal stress, which is often where cracks and warps occur on printed circuit boards. Temperature gradient cloud maps can help designers find potential problems. When the parameters are set correctly, the simulation results of HyperLynx Thermal are compared with the measured results and with the results of infrared scanning. The simulation accuracy is more than 90%.
21.4.2 Thermal Simulation Example Following is a brief introduction to the HyperLynx Thermal simulation process using the Dual-SoC SiP layout design. Since HyperLynx Thermal and HyperLynx SI are in the same simulation environment, there is no need to re-import design data. 1.
Thermal analysis simulation
By selecting Simulate Thermal → Run Thermal Simulation from the menu, the thermal analysis process can be started and the initial simulation results (simulated with the default parameters of the system) can be obtained, as shown in Fig. 21.27. In HyperLynx Thermal, you can switch between different layers by clicking View , or through a drop-down window on the right side of the next side/layer button the toolbar, as shown in Fig. 21.28, where the dark color represents copper or metal trace.
Fig. 21.27 HyperLynx thermal initial simulation results
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Fig. 21.28 View the metal distribution of different layers in HyperLynx thermal
These data are important for the heat transfer of the substrate, because the heat transfer coefficients of the two materials metal and dielectric in the substrate are very different, the precise distribution of the metals in each layer, and the proportion of the metals in the substrate have a great impact on the accuracy of thermal analysis. (1)
Setup of Environment Parameters
Click on the tool icon to set environmental parameters, such as air temperature, air pressure, gravity, humidity ratio, incoming air velocity, and so on. And the Casing related parameters are set, as shown in Fig. 21.29. (2)
Setup of Component Properties
Fig. 21.29 Environment parameters setting
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Fig. 21.30 Component properties setting
After setting the environment parameters, set the component properties, mainly setting the name, location, power scaling factor (ratio of actual work power consumption to maximum power consumption), etc. Double-click the left mouse button on any component and pop up the Component Properties window. The properties in this window are basically inherited from Xpedition. The designer needs to input the power factor in the Input Power Scaling factor according to the ratio of the actual power consumption to the maximum power consumption of the component. Then click the Edit this Part button to set up the components in more detail in the pop-up Edit Part window. In the Edit Part window, pin parameters, air gap between the components and the substrate, gap thermal conductivity, power dissipation of the components can be set. Here, the power dissipation of U1 is modified to 3.5 W, U2 is modified to 2.5 W, and P1 is modified to 0 W. The default power consumption is estimated by the software based on the area of the device. Others remain default, as shown in Fig. 21.30. (3)
Setup of Substrate Parameters
under the After the component properties setting, click Stackup Editor button HyperLynx environment to set the parameters of the substrate, such as the number of substrate layers, thickness and heat conductivity. These parameters are inherited from the Xpedition design. If the correct settings are made in the Xpedition, there is no need to modify, just check them, as shown in Fig. 21.31. to rerun the After setting all the parameters, click the Run Analysis button thermal analysis, the maximum temperature of the substrate is 92.9 °C and the maximum temperature gradient is 35.9 °C/mm, as shown in Fig. 21.32. If the temperature does not meet the design requirements at this time, other auxiliary cooling methods can be used to reduce the temperature of the substrate and components, such as by adding boundary conditions, heat sink, heat pipe or heat
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Fig. 21.31 Substrate parameter setting
Fig. 21.32 Rerun the simulation to get temperature and gradient cloud maps
screw, and verify its feasibility. Due to the size of the text, this is not to be repeated here, and readers can analyze it by practice. 2.
Electrothermal co-simulation
In addition to the device itself, the high current in the traces on the substrate will also heat up. Considering the heat of this part in the simulation will increase the accuracy of thermal simulation, so the electro-thermal co-simulation is required. Menu selection Simulate Thermal → Run PI/Thermal Co-Simulation, in the popup Batch DC Drop Simulation window, select the net to be emulated, and set its maximum limit. For example, the maximum voltage drop is 5%, the maximum current density is 100A/mm2 , and the maximum via current is 1A, as shown in Fig. 21.33. Because the electrothermal co-simulation needs many iterations, the simulation time is relatively long. After the simulation is completed, we can get the following
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Fig. 21.33 Setup interface for electrothermal co-simulation
results. Refer to Fig. 21.34, the maximum temperature and maximum temperature gradient are reduced to some extent. The simulation results here are different from what we expected, perhaps due to the change of algorithm or external conditions,
Fig. 21.34 Simulation results of electrothermal co-simulation
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Fig. 21.35 Report and waveform of electrothermal co-simulation
limited to space. The reason is not discussed here and left for the reader to think about. In addition to graphically displaying the simulation results, we can also get a simulation report, which lists the simulation results of the power net. Click on the link text inside the report to view the detailed report and the simulation waveforms of the power net, as shown in Fig. 21.35.
21.4.3 Introduction to FloTHERM Software From above thermal analysis, we can see that HyperLynx Thermal is easy to use and can quickly get the simulation results, but there are some limitations, such as simple condition settings, not suitable for complex design, etc. Below we introduce a more specialized thermal analysis tool, FloTHERM. FloTHERM is a powerful three-dimensional Computational Fluid Dynamics (CFD) software that accurately predicts air flow and heat transfer, including the combined effects of conduction, convection and radiation, inside and around electronic components. FloTHERM can be used to quantitatively analyze the heat loss, temperature field and internal fluid movement of the system at different levels. FloTHERM uses an advanced finite volume solver to comprehensively analyze the thermal radiation, heat conduction, heat convection, fluid temperature, fluid pressure, fluid velocity and motion vectors of an electronic system in a three-dimensional structure model. FloTHERM has both steady-state and transient analysis capabilities. It can analyze not only the normal working conditions of electronic equipment, but also the thermal reliability of changing working conditions or sudden failures. It can also analyze the thermal analysis of heat sink systems containing a variety of cooling media, such as electronic equipment or cooling plates with both liquid and air cooling (Fig. 21.36).
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Fig. 21.36 Package thermal analysis using FloTHERM
The post-processing module of FloTHERM can visually and conveniently display the calculated temperature field, velocity field, pressure field and other data in the form of plane cloud, isopotential map, surface temperature distribution map, and three-dimensional animation of fluid motion. Flexible multilayer embedded localized grid technology can greatly improve computational efficiency and handle complex structures while ensuring computational accuracy. Perfect thermal analysis model library, intelligent CAD and EDA interface, full compatibility with common CAD and EDA software, and can be imported and exported through STEP, SAT, IGES, STL, IDF and other standard formats. The application scope of FloTHERM software includes: • • • •
Packaging Level and Chips Level thermal analysis PCB board and module level thermal analysis System level thermal analysis Environmental level thermal analysis.
21.4.4 Introduction to T3Ster To get accurate results in thermal simulation, the accuracy of device model is very important. How to obtain an accurate thermal model of the device? Usually requires testing. Let’s take a look at the T3Ster thermal test equipment. T3Ster (Thermal Transient Tester) is advanced thermal characteristics tester used for semiconductor devices, and for testing thermal characteristics of IC, SoC, SiP, radiator, heat sink, etc. T3Ster, which combines static mode and dynamic mode defined by JESD51-1, can collect device transient temperature response curves (including temperature rise and cooling curves) in real time, with sampling rate as high as 1 microsecond, test delay as short as 1 microsecond, and junction temperature resolution as high as 0.01 °C. T3Ster can test both steady-state and transient thermal resistance.
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Fig. 21.37 T3Ster minimum test environment
T3Ster is the developer of JEDEC’s latest test standard for thermal resistance of Junction-case (θjc) (JESD51-14). T3Ster has developed the world’s first international standard JESD51-51 for testing LEDs, as well as the LED photothermal co-test standard JESD51-52. Figure 21.37 are the minimum test environments for T3Ster, including the T3Ster host, thermostat, test computer and test software installed on the computer. The DUT (device under test) are generally placed in the thermostat or in a temperature-controlled environment. T3Ster’s original Structural Function analysis method, which can analyze the thermal performance (thermal resistance and thermal capacity parameters) of each layer structure on the device’s thermal conduction path, and construct the equivalent thermal model of the device, is a powerful tool to support the packaging process, reliability test, material thermal characteristics and contact thermal resistance of the device. Therefore, it is known as “X-ray” in thermal testing equipment. T3Ster can seamlessly link with professional thermal analysis software such as FloTHERM to import the thermal parameters of the device from the actual test into the thermal simulation software for subsequent simulation and optimization (Fig. 21.38). The functions of T3Ster include: • Chip junction temperature testing, without destroying the chip structure, directly test and obtain the chip junction temperature. Chip surface temperature testing which is measured by thermocouple. • Material Thermal Resistance Measurement θjc (Thermal Resistance from junction to case) θja (Thermal Resistance from junction to air). • The chip structure and defect analysis can be done through the structure function
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Fig. 21.38 Data transfer between T3Ster and FloTHERM
Internal structure analysis, process defect analysis, reliability testing, contact thermal resistance evaluation.
21.5 Advanced 3D Solver 21.5.1 Introduction to HyperLynx Full-Wave Solver HyperLynx Full-wave Solver is a powerful 3D full-wave electromagnetic field solver. Using proprietary accelerated boundary element technology to achieve unprecedented solution speed and capacity while maintaining simulation accuracy. Solvers use multi-core and hybrid architecture technology to enable designers to get results faster and solve the most challenging problems quickly. In a unified environment, designers can solve complex problems such as signal integrity, power integrity and EMI, all of which use broadband full-wave electromagnetic field simulation technology. HyperLynx Full-Wave Solver supports three-dimensional full-wave electromagnetic field simulation, boundary element technology, broadband material and loss modeling, accuracy and frequency-dependent loss, inductance, skin effects, radiation effects, etc. Supports current and voltage sources, as well as a variety of planar wave excitation sources. It supports layout editing and creation, automatic EM analysis, automatic generation of net lists, flexible model clipping options, automatic port settings, adaptive fast frequency scanning capabilities and etc. It can output S, Y, Z parameters, near and far field graphs, noise spectrum graphs, current density graphs, etc. it supports a variety of standard EDA file formats (Fig. 21.39). HyperLynx Full-wave Solver contains Hybrid Signal and Power Integrity Analysis to provide accelerated power-aware signal results. Maxwell’s accuracy is guaranteed through a powerful multi-solver hybrid technology. Designers can analyze crosstalk, loss, characteristic impedance in signal integrity from the frequency domain, as well as current density, decoupling design, and AC analysis in power integrity.
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Fig. 21.39 HyperLynx Full-wave Solver simulation screenshot
Designers can not only optimize the design to improve performance, but also reduce design costs from chips, packaging to PCB.
21.5.2 Introduction to HyperLynx Fast 3D Solver HyperLynx Fast 3D Solver enables the creation and processing of SiP models suitable for power integrity, low frequency SSN/SSO, and full system SPICE model generation, taking into account the skin effect on resistors and inductors. Fast 3D Solver has a quasi-static extractor that solves power integrity, signal integrity, and synchronous switch noise. With its powerful 3D capabilities, automatic extraction includes the ability to process power and signal nets. Users can select a variety of extractions, including impedance, resistance, conductance, capacitance, inductance, and a complete SPICE net. Skin effect can be considered. Fast 3D Solver supports SiP, MCM, PoP and other types of design to extract accurate RLGC models (Fig. 21.40).
21.6 Simulation of Digital-Analog Mixed Circuit In schematic design phase, Siemens EDA provides a hybrid circuit emulation tool Xpedition AMS based on Designer, which can simulate and analyze circuit functions to ensure “design is correct” from the beginning of the design.
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Fig. 21.40 Simulation screenshot of HyperLynx fast 3D solver
Xpedition AMS is based on the Designer environment. If the correct model is attached to the components in the schematic diagram designed in Designer, the Xpedition AMS can be directly started for simulation. Xpedition AMS supports mixed simulation of multilingual models, which is embedded in a hybrid simulation engine based on ADMS and can support multiple languages, including industrial standard Eldo/SPICE, Verilog, VHDL, and the latest standard mixed simulation languages Verilog-AMS, VHDL-AMS and C. Xpedition AMS has a unique hybrid emulation function. For analog circuits, it can use SPICE model. For digital circuits, it can also use languages such as VHDL directly without any model conversion, which makes the digital/analog hybrid emulation function easy to implement. Xpedition AMS has a variety of analytical tools, such as AC analysis, DC analysis, Transient analysis, frequency-domain analysis, time-domain analysis, etc. It can be extended to advanced simulation including Parametric Sweep, Temperature Sweep, Monte Carlo analysis, Worst-Case analysis, etc. to ensure design quality and design stability. It can fully take into account the discrete situation of circuit and components, and ensure the reliability of the product. Xpedition AMS supports multi-tool co-simulation, connecting multiple tools in an integrated simulation environment to give full play to their respective advantages. Figure 21.41 are shown. Xpedition AMS and other analysis tools, such as Simulink
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Fig. 21.41 Xpedition AMS supports multi-tool co-simulation
and LabVIEW link and process with languages such as C/C++, java, and SysteemC, are particularly effective for analyzing complex systems by connecting design teams from the beginning to the end of the development process.
21.7 Electrical Rules Verification Electrical rule verification is to check and validate the electrical rules of the whole design after the layout design is completed. It is an effective guarantee for the design quality. Especially for complex electrical rules that are not easy to emulate, such as traveling across planar divisions, vertical reference plane changes, and rule checks for SI, PI, EMI/EMC, to help designers complete the design quickly, efficiently and with high quality.
21.7.1 Introduction to HyperLynx DRC HyperLynx DRC is a powerful and fast electrical design rule checking and verification tool that helps designers perform electrical rule checking through an automated verification process. Unlike the physical rule-based DRCs built into the design tools, HyperLynx DRC is mainly for electrical rules, which contain five categories of 82 rules, and will be
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Fig. 21.42 HyperLynx DRC integrates multiple types of electrical rules
enriched with software upgrades. In addition, HyperLynx DRC allows users to incorporate their own design experience rules and allows designers to conduct electrical design rule checks on SiP substrate designs using different electrical standards. The rules embedded in the current version of HyperLynx DRC include 43 SI rules for signal integrity, 10 PI rules for power integrity, 18 EMI/EMC rules for electromagnetic compatibility, 3 Analog rules for analog circuits, and 8 rules for safety, which cover all possible problems in electronic design. The Developer can write custom rules in JavaScript or VBScript. In addition to its rich and extensible rules, HyperLynx DRC provides designers with a powerful checking method that enables software to not only locate errors in a highlighted way, but also report the causes of problems and solutions that can be referenced. Figure 21.42 show examples of several types of electrical rules integrated in HyperLynx DRC.
21.7.2 Examples of Electrical Verification Here, we use an example of an 8-chip stacked SiP design to briefly introduce the HyperLynx DRC electrical verification process. The design consists of eight chips stacked on a ceramic substrate, which contains a cavity. The chips are stacked in cavity, and the chips are connected to the substrate by bond wires. The substrate has six layers, two of which are ground layer and the
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other four layers are routing layers. The screenshots designed in Xpedition are shown in Fig. 21.43, with 2D view on the left and 3D view on the right. In Xpedition, select Analysis → Export to HyperLynx DRC from the menu, the system automatically passes the data and opens HyperLynx DRC. First enter the Project Setup Wizard, as shown in Fig. 21.44. below the window and proceed step by step as Then click the next button prompted. The entries we need to set and the settings values in this example are listed in Table 21.1. to import design data and related parameters After setting, click Finish button into HyperLynx DRC, including layers, components, electrical nets, physical nets, net classes and other design elements, which can be accurately transferred to HyperLynx DRC. As shown in Fig. 21.45.
Fig. 21.43 Xpedition design screenshot
Fig. 21.44 HyperLynx DRC project setup wizard
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Table 21.1 HyperLynx DRC parameter settings table Reference value
Note
1
Setup entries Set location Set project units
Setup → Options → Units
Metric, micron
Others keep the default value
2
Set default values
Setup → Options → Default values
Stackup(); Component(); Electrical Net(50 M, 2 ns, 100 mA, 3.3 V); Physical Net
It mainly sets electrical net parameters, and other parameters can be kept as default
3
Set project paths
Setup → Options → Paths
Local Model Directory Related path = settings E:\Project\Sim_Models
4
Assign component models
Setup → Options → Models
Assign by part name
Model specific settings
5
Identify connector
/
/
This design does not include
6
Build electric nets
Project Explorer
Frequency (50 M) Voltage (3.3 V)
Mainly set the net frequency and voltage
7
Identify Project Explorer constant nets
VCC, VSS
Constant net
8
Identify series components
/
This design does not include
9
Tune Setup → Options → Transmission Ground search distance Set the transmission line on (100 um), Minimum distance from lines builder TLine length (50 um) normal and minimum transmission line size
/
10 Tune coupling calculations
Setup → Options → Coupling
Coupling distance (150 um)
Others keep the default value
11 Define differential pairs
/
/
This design does not include
12 Set rule parameters
Project explorer
No change
Keep default
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Fig. 21.45 Design is imported to HyperLynx DRC
The current version of HyperLynx DRC contains five categories, a total of 82 rules, which need to be selected according to the characteristics of the design for different complex situations. Because this design is a digital circuit, we can ignore the Analog rule and choose among SI, PI, EMI and Safety. In this case, we select the following 11 items as examples to check, see Table 21.2. Designers can choose appropriate checks based on the actual situation of their own projects. to run rule checking When setup is complete, click the Execute Rules button and validation. When the check is complete, expand the Rules rule and we can see that some of the colors of the Check box change to red and some to green, red indicates that the Rules failed the DRC rule check, and green indicates that the rule passed the DRC rule check. Below, we will elaborate on the checks in Table 21.2. (1)
In the SI category, we select three check items.
The termination check and trace shielding checks passed, and many vias checks failed. There was an error because the number of vias in some nets exceeded the set value. Expand the inspection results in Project Explorer and select the corresponding entries. The selected net will be highlighted. In the spreadsheet below the window, we can view the number of vias of the net, as shown in Fig. 21.46. The solutions to this problem are as follows: ➀ Modify the problem net in Xpedition to reduce the number of vias. ➁ If the net is not a high-speed net, check conditions can be relaxed, such as changing the maximum allowable number of vias in the net to 10, such nets can pass check. Readers can choose based on the actual situation of their own projects.
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Table 21.2 Check item status in this example Check categories
Check items
Pass or not
Problem analysis
Resolvent
SI
Termination check
Pass
/
/
Trace shielding
Pass
/
/
Many vias
Error
The number of holes exceeded the set value
Modify design/change settings
Power/Ground width
Warning
Part of the line width Allowable is less than the set value
Ground layer
Pass
/
/
PDN via count
Pass
/
/
Net crossing gaps
Pass
/
/
Return path
Pass
/
/
Via sub length
Pass
/
/
Multi-layers creepage distance
Setup error
The design is recognized as Rigid Flex and cannot be checked for
Skip check
Same-layer creepage distance
Setup error
The same as above
Skip check
PI
EMI
Safety
Fig. 21.46 Rules violation net highlighting
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Fig. 21.47 Net VCC segment width warning
(2)
In the PI category, we selected three checks.
The Ground Layer and PDN Via Count checks passed, the Power/Ground Width checks failed, and there was a warning because some trace widths of the VCC and VSS were smaller than the set values. Expand the results of the check in Project Explorer and select the appropriate entry, and the selected net will be highlighted. The parts of the VCC net widths below the set values shown in Fig. 21.47 are highlighted. This problem is usually caused by local inconsistencies between rule settings and actual conditions. For example, for power and ground nets, designers want to increase the widths as much as possible, so in rule settings, widths are set as wide as possible, which is acceptable in most areas, but in some areas of higher density, even in some Bond Finger or where the width of the pad itself is less than the set value, the widths need to be reduced manually. Because these areas are usually smaller and such segments are shorter, they do not affect the design and are generally allowed. in the HyperLynx DRC window, By clicking the Enable Crossprobing button HyperLynx DRC can perform design interaction checks with Xpedition. Selecting any net in HyperLynx DRC will also be selected and highlighted in Xpedition, which increases the convenience of interactive checking and facilitates timely modification of the problem net in Xpedition, as shown in Fig. 21.48. (3) (4)
In the EMI category, we selected three checks, Net Crossing Gaps, Return Path, and Via Sub Length, all pass. In the Safety category, we selected two checks, Multi-layers Creepage Distance and Same-layer Creepage Distance, which failed because the design type
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Fig. 21.48 Design interactive check in Xpedition
was not appropriate. Considering that the design voltage is relatively low, the problem of violating the rules will not occur in general, so the Safety category can be ignored in this case. Let’s conclude: (1)
(2)
HyperLynx DRC contains five broad classes and 82 rules, which will be enriched with software upgrades and allow users to customize rules. Because the actual designs vary widely, HyperLynx DRC has a rich set of rules to provide a more comprehensive coverage of all situations. Not all rules are appropriate for a specific project. Designers need to choose the appropriate inspection items, and understand the purpose of the inspection items and set the parameters correctly. Whether all selected checks should pass the checks, this is a specific problem to be analyzed, and the problems that affect the performance and reliability of the product must be modified before re-checking. For some warnings or errors due to setup reasons, we can modify the parameters of the check and re-check until it passes. In addition, some warnings that have little impact on the design can be accepted or ignored, and be noticed in the next design and promoted gradually.
21.8 HDAP Physical Verification Before HDAP physical verification for high density Advanced Packaging, many people will have a question. After the design is completed, we have already done DRC
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checking in the packaging design tool. The rules I set can also meet the requirements of the process. Why do I need to do physical verification specifically? This is actually closely related to the characteristics of HDAP. In layout design tool Layout301and XPD, the embedded DRC checking tools are sufficient to assist designers in checking and validating for traditional package. For the 3D and 2.5D of HDAP, due to the use of silicon technology, its density and complexity are increasing, and its production process and IC process also have a gradual trend of integration. Traditional DRC tools have been difficult to meet their physical verification needs, and special verification tools are needed. These tools are usually derived and reconfigured from IC Verification tools, such as Calibre 3DSTACK provided by Siemens EDA.
21.8.1 Introduction to Calibre 3DSTACK Calibre is the industry’s most influential IC layout verification tool, because of the integration of IC design and HDAP design, and the need for 3D and 2.5D integration on silicon materials for RDL and TSV. Therefore, Calibre 3D STACK has been developed specifically for 3D and 2.5D integrated design. Calibre 3DSTACK extends physical verification at the Calibre chip level to allow full verification of various 2.5D and 3D stacked chips. With Calibre 3DSTACK, designers can perform DRC and LVS checks on a complete multichip system at any process node without disrupting the current tool flow or requiring new data formats, thus greatly reducing the time required for production output. Since 3D STACK uses standard Calibre DRC, Calibre LVS, and Calibre Design Rev features, no new license is required. Although standard Calibre supports wafer factory certified design rule checking (DRC) and comparing the layout of individual chips to the schematic (LVS), Calibre 3DSTACK extends Calibre’s chip-level signature verification capabilities to allow full design verification of stacked chip components. Calibre 3DSTACK can be used to validate stacked chip components such as 3D stacked memory, stacked sensor arrays, 2.5D structure, or WLP wafer-level packaging. Calibre 3DSTACK performs all DRC and LVS checks based on the package information in the rule set (stacking order, x/y position, rotation, direction, etc.) for the interface geometry between chip designs, including bumps, BGA solder balls, TSV, or copper-to-copper bonding, and supports chips with different process flows. Traditional DRC and LVS validation tools assume that layers are coplanar, that is, polygons on the same GDSII layer are on the same vertical plane. The 2.5D and 3D integrated structures contain multiple chips, which may be graphics on the same GDSII layer, but represent completely different geometries at different vertical depths. When validating 2.5D and 3D designs with traditional tools, layer conflicts may occur between multiple chips with the same GDSII layer.
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Fig. 21.49 Calibre 3DSTACK function block diagram
Calibre 3DSTACK uniquely identifies the geometry of each chip placement layer in the component, allowing precise inspection between the chips. By supporting flexible stacking configurations for multiple chips, Calibre 3DSTACK minimizes interference with existing validation processes, while providing maximum flexibility for designers across process nodes and stacking configurations (2.5D and 3D). Calibre 3dstack can distinguish the layers placed on each chip, so that designers can verify the physical properties of each chip (offset, scaling, rotation, etc.), and track the connection between interposer or chip to chip interface. Calibre 3DSTACK provides scalability to integrate new extraction and validation solutions in the future. The function block of Calibre 3DSTACK is shown in Fig. 21.49.
21.8.2 HDAP Physical Verification Example Next, we use HDAP design example to briefly introduce Calibre 3DSTACK physical verification process. First, it is important to note that Calibre 3DSTACK can only run in UNIX or Linux environments at present. In order to work with XSI or XPD, it is better to install XSI and XPD in Linux environment with Calibre 3DSTACK, or install XSI or XPD in Windows environment, and install Calibre 3DSTACK in Linux environment to solve this problem.
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Next, the author introduces the process of HDAP physical verification in RHEL7 virtual machine environment together with windows environment. If windows environment can support we operate in windows, otherwise it can be operated in RHEL7 Linux environment. 1.
Configure Calibre 3DSTACK Wizard
First, we use the HBM-HDAP designed in Chap. 19 of this book as an example to configure Calibre 3DSTACK, which includes two floorplan, interposer and substrate, and the interposer Floorplan is shown in Fig. 21.50. In XSI, select package utilities → Calibre 3DSTACK wizard from the menu, and the window as shown in Fig. 21.51 will pop up. In XSI Calibre 3DSTACK wizard window, select tools → property manager from the menu, and the window as shown in Fig. 21.52 will pop up. Select interposer and select 3DSTACK → design… from the menu in this window. Add the following properties and values to the interposer. Then, in property manager, select substrate and select 3DSTACK → Design → Exclude → Yes from the menu. This function is to exclude substrate from this verification. Select the interposer and choose 3DSTACK → Design → Exclude → No from the menu to include the interposer in this verification. Then, close the property manager and return to the XSI Calibre 3DSTACK wizard window. 2.
Generate Calibre 3DSTACK file
First, we start with assembly connection, including chip assembly file, interposer assembly file and chip TCL file. In 3DSTACK wizard, select assembly connection TAB, select the Die Assembly option, and then click generate to get the file shown in the box on the right side of the figure below, as shown in Fig. 21.53.
Fig. 21.50 Interposer floorplan in XSI
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Fig. 21.51 Startup XSI Calibre 3DSTACK wizard
Fig. 21.52 Add properties and values to interposer
Then, select Interposer Assembly and generate Die Script Options respectively, and then click the generate button to get two files as shown in Fig. 21.54. In the same way, switch to the Assembly Stack TAB and Assembly Checks TAB, and generate the corresponding file through the Generate button, as shown in Fig. 21.55. Then, switch to the 3DSTACK Netlist TAB, generate Calibre 3DSTACK Netlist file, which is saved in the 3DSTACK directory under the design, as shown in Fig. 21.56. Then, switch to main (main.3ds+) TAB, select all 3ds+ files, generate Main.3ds+ File and save it with the Save button, as shown in Fig. 21.57.
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Fig. 21.53 Generate die assembly file
Fig. 21.54 Generate interposer assembly and die script files
Fig. 21.55 Generate assembly stack and assembly checks files
Then, switch to Run Control TAB and generate run.sh, clean.sh, specs.svrf file, and save it by the Save button, as shown in Fig. 21.58. Hereto, all the required files have been generated and saved in the 3DSTACK folder, as shown in Fig. 21.59.
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Fig. 21.56 Generate Calibre 3DSTACK netlist files
Fig. 21.57 Generate Main.3ds+ file
Fig. 21.58 Generate run.sh, clean.sh, specs.svrf file
All the above files are generated manually. After the designer is familiar with the function and process of each file, he can also generate all the files by pressing the “One Click 3DSTACK Deck” button at the bottom left of the window. In addition to the above generated files, GDS files need to be generated in the design for Calibre inspection and verification. For the generation of GDS file, please refer to Chap. 20. After all the required files are generated, the next step is to physically verify the design through Calibre 3DSTACK. 3.
Use Calibre 3DSTACK for Physical Verification
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Fig. 21.59 The generated files are saved in the 3DSTACK folder
Copy the entire design folder to the Linux environment, start terminal and switch to the 3DSTACK folder under the design, and start Calibre 3DSTACK by calling./run.sh the script file. The system automatically checks and validates the design, and Calibre DESIGNrev and RVE (Results Viewing Environment) environments start after verification is complete. View the design in Calibre DESIGNrev, as shown in Fig. 21.60. Look at 3dstack.rdb and 3DSTACK Report in CalibreRVE, and 3dstack.rdb checks pass in this design. As shown in Fig. 21.61a, the 3D STACK Report is correct, as shown in of Fig. 21.61b.
Fig. 21.60 Verify interposer design in Calibre DESIGNrev
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Fig. 21.61 View inspection report in Calibre RVE
In addition to verification for a single layout, we can also validate multiple layouts at the same time. For example, the design includes two layouts, Interposer and Substrate. When generating a 3DSTACK file, both layouts need to be included. In Property Manager, select Interposer and menu select 3DSTACK → Design → Exclude → No, then select Substrate and menu select 3DSTACK → Design → Exclude → No, to include both Substrate and Interposer in verification. Close the Property Manager, return to the XSI Calibre 3DSTACK Wizard window, and generate all files with “One Click 3DSTACK Deck” button, then perform a similar check above. In the 3DSTACK folder, start Calibre 3DSTACK by calling the script file./run.sh. The system automatically checks and validates the design, and the Calibre DESIGNrev and Calibre RVE environments start after the validation is complete. View the design in Calibre DESIGNrev, as shown in Fig. 21.62. Then, look at 3dstack.rdb and 3DSTACK Report in Calibre RVE.
Fig. 21.62 Verify the overall design in Calibre
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Fig. 21.63 Perform pad overlap check in Calibre
In addition to the above checks and verifications, there are many checks that can be performed in Calibre, such as routing sharp angle checks, routing density checks, connectivity checks, Pad center alignment checks, Pad overlap checks, and so on. Due to the size of the chapter, we do not cover each of them. Readers can refer to the user guide of Calibre software. Figure 21.63 show a report screenshot of dislocation of upper and lower pads in a chip stack during Calibre Pad overlap check in a project. By this kind of check, we can find out the upper and lower misalignment caused by library building among the devices in chip stack in 3D design or avoid the misalignment between the pin of the chip and the Interposer pad in 2.5D design. With the complete physical verification function of Calibre 3DSTACK, we can effectively ensure the correctness and reliability of the design output data, thus improving the one-time success rate of product development.
References and Notes
References 1. Li S (2017) SiP system-in-package design and simulation mentor EE flow advanced design guide. Wiley, New Jersey 2. Li Y, Liu Y (2012) SiP system in package design and simulation: mentor expedition enterprise flow advanced design guide. PHEI, Beijing 3. Layout Advanced Packaging Guide, Mentor 2020 4. Xpedition Library Manager User’s Guide, Mentor 2020 5. Xpedition Designer User’s Guide, Mentor 2020 6. Constraint Manager User’s Manual, Mentor 2020 7. Layout Operations and Reference Guide, Mentor 2020 8. Layout 3D Design Guide, Mentor 2020 9. HyperLynx SI/PI User Guide, Mentor 2020 10. HyperLynx DRC User Guide, Mentor 2020 11. Layout RF Guide, Mentor 2020 12. Xpedition Package Designer 3D Design Guide, Mentor 2020 13. Xpedition Package Designer Operations and Reference, Mentor 2020 14. Xpedition Package Designer Quick Start Guide, Mentor 2020 15. Xpedition Substrate Integrator Quick Start Guide, Mentor 2020 16. Xpedition Substrate Integrator Guide, Mentor 2020 17. Xpedition Substrate Integrator User’s and Reference Manual, Mentor 2020 18. HyperLynx Advanced Solvers User Guide, Mentor 2020 19. Concurrent Design Administrator’s Guide, Mentor 2020 20. Xpedition Layout Team User’s Guide, Mentor 2020
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Notes Fan-In is written Fan-in in some literatures, in order to correspond to Fan-Out, the initial letter of in in this book is also capitalized. In addition, the concept of Fanout also exists in the semi-auto route of Xpedition software, which refers to route and place via from pad. It has a different meaning from Fan-Out. Readers should pay attention not to be confused. In addition, some English characters on Xpedition menus are slightly different from Standard English characters. Generally, the characters in Xpedition menu shall prevail when describing in the text of this book.
Part III
Projects and Cases
Chapter 22
Mass Storage Chip Design Case Suny Li and Junshe An
22.1 Application of Mass Storage Chip in Space Data storage is a critical part in both aerospace and other technical fields. For example, the Mass Storage used in China’s manned space “Shenzhou” series of spaceships is responsible for the important task of storing data collected by various devices on the spacecraft. Microgravity Detector, Cirrus Detector, Electrophoresis, Imaging Spectrometer, Space Camera, Earth Radiation Balance Gauge, Solar Ultraviolet Spectrometer, Solar Constant Monitor, Atmospheric Density Detector, Atmospheric Component Detector, Cell Bioreactor, Multitask Space Crystal Growth Furnace, Space Protein Crystallization Device, Solid Track Detector, so many space devices and instruments collect data that is transferred to mass storage via a highspeed bus on a spaceship, and then transmitted to a ground receiving station via a transmitter. When a spaceship is flying around the earth outside the receiving range of a ground station, all the test data needs to be stored in mass storage, which makes the storage capacity of mass storage critical. Because of the limited space and carrying capacity of the spaceship, all the equipment has strict weight and volume requirements, and cannot exceed the size limit or be overweight. How can maximize storage in a limited volume and weight? The engineers and technicians thought a lot of ways, and the ultimate solution was to improve the storage capacity of the mass storage chip. Because of the high requirement of equipment reliability, anti-shock for spacecraft, the large capacity memory on spacecraft usually does not use disks and other media, but uses a flash memory chip based on Nand Flash, so the capacity of the flash memory chip is very important.
S. Li (B) · J. An Beiging, China e-mail: [email protected] © Publishing House of Electronics Industry 2022 S. Li (ed.), MicroSystem Based on SiP Technology, https://doi.org/10.1007/978-981-19-0083-9_22
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Fig. 22.1 High capacity storage chip based on package stacking
Now new technologies such as 3D IC have started to appear and are being used on flash memory chips. For example, currently 3D NAND technologies make it relatively easy to increase storage capacity, but these new technologies have not yet undergone long-term engineering reliability validation and are too early for the application of space devices. In addition, the new 3D NAND cannot meet the longterm high-intensity storage requirements of space equipment data in terms of number of erases. At present, in order to improve the storage capacity, the most common application in spacecraft is to stack the packed memory chips vertically and do secondary packaging. This product is characterized by its relatively simple and direct implementation. First, the packaging chip needs to be screened, then pin straightening, packaging stacking, plastic encapsulation, cutting and grinding, electroplating, interconnected shaping and other processes. At present, the main manufacturers using this technology are 3D Plus, Mitsubishi, etc. Some companies and research institutes in China also actively study this technology to develop products based on it (Fig. 22.1). This technology greatly improves the storage density and solves the problem that the maximum storage capacity needs to be achieved within a limited volume and weight in spacecraft applications. It is currently widely used in space field. However, this type of memory has its own inherent problems, mainly with the following three drawbacks: (1)
(2)
(3)
Due to the use of plastic packaging devices for secondary packaging, it is also a plastic packaging device itself, which cannot solve the airtight problem required in spacecraft applications, but under the restrictions of existing conditions, it is a solution. Due to the use of package stacking, the thickness and weight are generally larger, and the height of the device is basically more than 10 mm, which results in greater inertia and easy has problems in vibration and impact experiments. Due to the limitations of its structure, the electrical interconnection between chips and between chips and package pins is connected by electroplating wires on the surface of the package. This kind of electroplated wire can only be used for simple electrical interconnection, but cannot guarantee the reference plane required for high-speed signal and the parameter requirements of high-speed circuit with equal length. So at present, it can only be used in low speed and low signal quality areas.
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To solve the three problems mentioned above, we must find a new technology to reduce the weight and volume of mass storage, improve the signal transmission quality, solve the airtight problem, and improve the reliability of space products. From the analysis of current technology development, SiP technology has become the preferred technology.
22.2 Feasibility Analysis of SiP Application In order to apply SiP technology to mass storage, we must first solve the three problems faced by the traditional packaging stacking technology described above and the three unavoidable shortcomings of the old product, so as to enhance the product and obtain market approval. First, choose ceramic packaging materials to solve the airtight problem that plastic sealing cannot solve. At present, ceramic SiP technology is gradually mature in China, can support more complex processes, and has been gradually applied in space projects. Secondly, in order to solve the problem of large volume and heavy weight caused by package stacking, the 3D SiP technology of chip stacking is selected. Chip stacking technology has been used in the industry for many years and is now a mature technology. Finally, in order to solve the need of reference plane for high-speed signal and the requirement of equal length of high-speed data bus, the plane layer of GND or Power should be set reasonably as the reference plane in the design of SiP substrate, and the equal length requirement should be considered in routing, packaging pins should be allocated reasonably, and the equal length of high-speed data trace can be achieved by serpentine routing technology. From above analysis, we can see that the use of SiP technology can really solve the problems that existing products cannot solve, thus making the product a huge improvement in quality and performance. So, will SiP technology succeed in mass storage projects? The following three elements are also required. The three elements for the success of a SiP project are: bare chip, design and simulation, manufacture and testing.
22.2.1 Bare Chip Selection 1.
Problem and Solution of Bare Chip
Bare Die (Bare Chip) refers to the product form before semiconductor components are packaged. Bare chips usually exist in the form of Wafer or Die and become part of semiconductor components, integrated circuits, or more complex circuits such as SiP after packaging (Fig. 22.2).
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Fig. 22.2 Bare chip in the form of wafer or single chip
Many foreign chips are difficult to purchase, especially bare chips, due to such reasons as the foreign chip embargo or restrictions on supply. Often, bare chips needed in a SiP project cannot be purchased, making it difficult for the project to continue. Based on past experience, there are four general solutions: (1)
(2)
(3)
(4)
Use domestic chips instead. At present, domestic chips are also being developed all over the country. Generally, the products of well-known international chip manufacturers can find corresponding substitutes in China. Although the performance and capacity of the chips sometimes cannot reach the international standards of similar products, to a large extent, they can meet the needs of SiP project. Use the same kind of chips instead, such as AD, DA, operational amplifier, etc. Many of these bare chips have similar functions, and can be replaced with the same kind of chips that can be purchased under the premise of meeting the design criteria. Reasonable clipping of design scheme. For example, a complete computer system is not necessarily implemented in a single SiP. It can be divided into system master SiP, data processing SiP, interface management SiP, etc. This makes it easier to implement a part of the function of SiP first, or implement the corresponding function through software programming in SiP using FPGA. If bare chips cannot be found but must be used in SiP projects, small packages such as CSP, QFN, etc. can be used instead, which requires communication with the manufacturer about process compatibility issues ahead of time.
The above four methods have been applied in practical projects, and have achieved good results. Users have finally made satisfactory SiP products and achieved their due functions. 2.
Selection of Bare Chip for Mass Storage
The Mass Storage of this project needs to select one that is large enough and compatible with the older products mentioned earlier, so Nand Flash is preferred.
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Table 22.1 Comparison of four types of Nand Flash Abbreviated name
Full name
Each cell storage bit (numeric values can be stored)
Speed
Life
Price
Rewrite cycle
SLC
Single-level cell
1bit (0, 1)
Fast
Long
Expensive
60,000–100,000 times
MLC
Multi-level cell
2bit (00–11)
Middle
Middle
Middle
8000–10,000 times
TLC
Triple-level cell
3bit (000–111)
Slow
Short
Low
1000 times
QLC
Quad-level cell
4bit (0000–1111)
Slow
Short
Low
1000 times
Currently Nand Flash is divided into SLC, MLC, TLC, QLC and other types. SLC = Single-Level Cell, or 1bit/cell, which can store 0 or 1 per cell, is fast, has a long lifetime, is expensive (about three times the price of MLC), and has about 60,000 to 100,000 erase lifetimes. MLC = Multi-Level Cell, or 2bit/cell, which stores four binary numbers per cell. It has an average speed, average price, and approximately 8,000 to 10,000 erase lifetimes. TLC = Trinary-Level Cell, or 3bit/cell, which stores eight binary numbers per cell. There is also a Flash manufacturer called 8LC, which has a slow and short life and is inexpensive with about 1000 erase lifetimes. QLC = Quad-Level Cell, or 4bit/cell, which stores 16 binary numbers per cell. It has a slow and short life, is inexpensive, and has about 1000 erase lifetimes. Table 22.1 is a comparison of four types of Nand Flash. At present, in SSD solid-state hard disk, MLC chip is the mainstream, it has a moderate price, relatively good speed and life, while low-cost SSD commonly uses TLC chip particles, if used normally, the so-called 1000-time life of TLC is fully enough. At present, most smartphone storage mainly uses TLC chip storage, and some use MCL chip particles. A new type of flash memory chip, QLC, has been introduced. Each cell of QLC consists of four layers of cells, which have larger storage capacity and lower cost. SLC is mainly used in some high-end applications. SLC is the preferred choice for high-reliability applications such as space and satellite applications. This project has selected a model of SLC Nand Flash. At present, the maximum storage capacity of single bare SLC chip with mature technology is 16G bit, which is the best choice for this project.
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22.2.2 Selection of Design and Simulation Tools Currently, there are two main supplier of SiP design software, Siemens EDA (Mentor) and Cadence. SiP simulation software includes Siemens EDA, ANSYS, Cadence, ADS, etc. Each software has its own features and advantages. For design software, it is important to consider whether the latest SiP design technologies can be well supported, such as Wire Bonding, Die Stacks, Cavity, Flip Chip, RDL, Fan-in, Fan-out, 2.5D TSV, 3D TSV, Embedded Passives, RF, MultiLayout Project Management, Multiplayer Real-time Collaborative Design, 3D Realtime DRC and etc. For simulation software, it is important to consider whether the design data can be imported conveniently and various design elements can be identified correctly; whether it has the simulation functions of SI, PI, EMI, thermal and electromagnetic; whether the simulation accuracy and speed can meet the project requirements. According to the characteristics of this project, software is required to have strong 3D design ability, in chip stacking, complex bond wire, and cavity structure. On the whole, Siemens EDA tool Xpedition has better 3D design function and better support for cavity and complex bond wire. Therefore, this project chooses Xpedition as SiP design tool, and the simulation tool also chooses the appropriate simulation tool according to the project requirements.
22.2.3 Selection of Manufacturing and Testing Factory After SiP design is completed, a manufacturer with reasonable price and reliable quality must be selected for manufacture and testing to ensure the final success of the project. In general, the production processes of plastic packaging, ceramic packaging and metal packaging are completely different, and the definition of design rules will vary greatly, so different types of manufacturers should be considered in advance according to the project situation. In the process of project design, it is necessary to get in touch with related manufacturers in advance, acquire the technological capabilities and manufacturing requirements, and define design rules based on them, so that the designed products can meet the requirements of production and manufacturing, commonly referred to as DFM (Design for Manufacturing). Sometimes, in order to win more projects, manufacturers often report their limited production capacity to users. At this time, we need to reasonably assess their normal production capacity and limit production capacity, and try to design within their normal production capacity, so as to avoid the problem of low product yield or high product price.
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In addition, it is also necessary to know if the manufacturer has the ability of “substrate + packaging + testing” or only one of the capabilities, and other needs to be completed through external cooperation. At this time, it is necessary to consult with the manufacturer how to ensure product quality and progress, and avoid project delays due to long production cycle. Because the application of this project is aimed at high reliability areas such as space and satellite. Therefore, airtight ceramic package is preferred, and highgrade ceramic is preferred whenever possible to meet the special needs of space applications. Ceramic substrate or shell are usually manufactured by special manufacturers, which should have the national quality certification system and qualifications for aerospace products. When designing, we need to contact the manufacturers to obtain the design rules for the ceramic substrate. If necessary, we should communicate several times to ensure that the product design and manufacturer’s production capacity are consistent. Packaging and testing manufacturers also need to have a national quality certification system, and have the qualifications of aerospace products. After the manufacturers are selected, we need to communicate with manufacturers many times, including assembly, bonding, packaging, testing and etc. for detailed communication.
22.3 Design of Mass Storage Chip From the previous description, we can see that a prerequisite for the success of a SiP project is to obtain the required bare chips. By contacting manufacturers and agents, the Nand Flash bare chips needed for mass storage can finally be ordered and the chip data can be obtained. The design simulation tool has been selected, and the manufacturer and testing have selected and communicated with each other to confirm that the process is feasible and then the mass storage chip can be designed for the project. The design stage mainly includes the scheme design, detailed design, simulation, and production data output and so on.
22.3.1 Scheme Design 1.
Compatibility Thinking
In order to solve the problem of mass storage used on existing spacecraft, compatibility issues, including size compatibility and functional compatibility, should be considered first in the scheme design, that is, the ability to replace existing products in situ. If the compatibility performance is effectively guaranteed, customers only need to replace the existing old chips directly with new mass storage chips, without
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any design changes to the existing PCB board, which is naturally the ideal state for customers. However, because the new product uses airtight ceramic packaging and the old product is plastic packaging, there is a big difference in technology between the two, so it may be hard to realize fully compatible. Currently, in terms of technological capabilities, plastic package is ahead of ceramic counterpart in trace width, clearance, via size and space, and bond finger size and etc. In addition, ceramic package often require special packaging requirements, so if the same product is designed for plastic and ceramic package separately, the size of ceramic package is generally larger than that of plastic package, which presents a challenge for compatibility design. Through repeated communication and design optimization with production personnel and reasonable arrangement of pin welding position, the new product is finally compatible with the size and function of the old product. 2.
Chip Stacking Scheme
In scheme design, because of the using of 3D chip stacking scheme, choosing which stacking method is the key to SiP design. In actual project, we have conceived a variety of schemes, and ultimately selected the simplest and most practical scheme in process implementation, which also guarantees the quality and reliability of subsequent products to a certain extent. Following is a comparison of the two alternatives to discuss ideas for the selection of alternatives. First, the die Pad single-sided arrangement of the Nand Flash chip objectively brings some convenience to the chip stacking design. Stacking can be done by interlacing chips, and there are many options for stacking. Figure 22.3 shows a scheme based on first-step staggered chip stacking, in which eight bare chips are staggered in turn. The first layer of chip is left, the second layer is right, the third layer is left, and so on. The advantage of this stacking method is that it is more balanced, the distance between bonding lines is relatively far, and the bond wire short phenomenon is not easy to occur. However, this scheme is facing a large problem when the process is implemented and requires at least four heat curing cycles. Each chip needs to be heated and cured before bonding. The chip can be bonded only after it is fixed by glue or adhesive film. Because of its structure, the upper chip covers the bonding point of the lower
Fig. 22.3 Design scheme based on first-step staggered chip stacking
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Fig. 22.4 Design scheme based on 4-step staggered chip stacking
chip, so only 1–2 chips can be bonded first, then 3–4 chips can be bonded, and so on. Thermal curing is required before each bonding. Multiple thermal curing may affect the properties of the adhesive film, and may pose a certain risk to the reliability. In addition, repeated thermal curing and bonding may cause complex operation and affect work efficiency. Therefore, from a process perspective, Fig. 22.3 is not a good scheme. Figure 22.4 shows a scheme based on four-step staggered chip stacking, in which eight bare chips are stacked as follows: four bare chips are stacked form left to right, and four bare chips are stacked from right to left. The bare chips 1, 2, 3, 4 are located below, bonded to the left, the bare chips 5, 6, 7, 8 are located above, bonded to the right. In order that the right bonding line is not too long to affect the stability, a cavity structure is designed on the substrate. The cavity depth is equal to the sum of the thickness of four chips. The left chips are bonded at the bottom of the cavity, and the right chips are bonded on the steps of the cavity, so the two sides are balanced bonded and technically easy to control. This scheme only requires two heat curing times when the process is implemented, which greatly reduces the risk and improves the processing efficiency. So the scheme shown in Fig. 22.4 is our final choice.
22.3.2 Detailed Design After the scheme design is completed, it enters the detailed design stage. Detailed design includes schematic design, specific packaging dimensions, pin definitions, pin spacing, substrate layer stackup planning, via definitions, trace width and spacing settings, layout and routing, equal length design, delay calculation, etc. It takes the most time and effort to do. 1.
Schematic Design
The schematic design mainly defines the connection between chips, the functional definition of the pin, and the connection between the pin and the chip. Data Bus DQ0–DQ7 Shared Bus, Command Lock Enable CLE, Address Lock Enable ALE and Write protection #WP connect together and lead out to the package pin for unified operation. Each bare chip can be independently controlled and monitored by #CE, #RE, #WE and #RB. The pin-to-pin function definition refers to the
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Bare Die
Package
Fig. 22.5 Schematic design of mass storage chip
traditional mass storage chip and takes into account the compatibility of the function. Some schematic diagrams are shown in Fig. 22.5. 2.
Layout Design
Considering the compatibility of size and function, we define the package size as 19 mm × 13.6 mm. The height of the package should be given according to the number of substrate layers, chip stack thickness and structure, which can be tentatively defined as 3–4 mm. Depending on the number of nets, the degree of interlacing, and the number of layers that can be routed, the project sets the substrate to six layers. These layers include two plane layers, both assigned to GND net, four routing layers interconnect the bond fingers with the external pins, and the chip pins are interconnected through bond wires to bond fingers, thus realizing the electrical interconnection between the chips and the external pins. In the layout detailed design stage, we use Xpedition Layout 301 as SiP design tool, which is the mainstream tool in SiP design. It has advantages in 3D SiP design, and has better support for cavity, chip stacking and complex bond wires. Figures 22.6 below is a 3D design screenshot of the mass storage in Xpedition, in which (a) the bird’s-eye view and (b) the side-view profile show clearly the structure of the mass storage. The electrical connections between chips and substrate use 25 m gold bond wires, because many pins of the same kind of chip in the stack have the same net. Shared bond finger is used in the design, which can save routing space effectively and improve the flexibility of bonding. The bond wires of the same net only need to be bonded to the corresponding rectangular area, regardless of their order. The bond wires of the same net, even if they are too close to each other, do not affect the electrical
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Fig. 22.6 3D screenshot of mass storage chip layout design
characteristics of the product and reduce the technical difficulties of production. Figures 22.7 show the bonding diagram (top view) of eight-layer chip stack. For independent nets, bond finger needs to be designed separately and kept away from other nets as far as possible to avoid wire short in vibration or impact test, which can cause instantaneous short circuit and affect product quality and reliability. In addition, for the stability of bond wire, the ceramic packaging process requires that the length of bond wire generally not exceed 3 mm. In this design, the longest spacing of bond wire is 2.6 mm, which is lower than the process limit, thus ensuring the stability of bond wire. After the bond wire design is completed, the net needs to be connected to the ceramic package outer pin through the traces on substrate. An important principle of routing design is that the same type of net should be designed as equal length as possible. For this reason, when routing, the project achieves net equal length by serpentine routing. Referring to Fig. 22.8 for the fourth layer routing of the ceramic substrate, it can be seen that in order to compensate for the net length, many nets have serpentine routing, and in other layers, we have done the same. 3.
Delay Calculation
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Fig. 22.7 Mass storage chip stack bonding diagram
Fig. 22.8 Equal length designed by serpentine routing
Even though serpentine routing can minimize the length differences between nets of the same type, due to spatial and structural limitations, some nets cannot achieve equal length. At this point, the delay and its possible impact on the signal need to be determined by calculation or software simulation. Figure 22.9 below show the routing diagram of a set of DQ signals.
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Fig. 22.9 DQ signal routing topology
Because the bare chip pins of DQ signals are on the left or right side, and the package outer pins of DQ signals are all on the right side, the distance from the left DQ signal to the outer pin is larger than that from the right DQ signal to the outer pin, and cannot be fully compensated by effective serpentine routing due to space and structure. For this reason, we have calculated and analyzed the following. First, we find the line with the greatest difference in length and confirm that its length difference L = 15 mm. In this project, the selected HTCC ceramic medium parameter is DK = 9.3, and its delay formula is: TD = L ÷ C ×
√
DK
where C is the velocity of light, the values can be substituted to obtain: T D = (15 × 10−3 ) ÷ (3 × 108 ) × √ = 15 × 10−11 × 9.3 = 15 × 10−11 × 1.016 = 152.4 × 10−12 s
√
9.3
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That is 152.4 ps. Then, determine the possible impact at different operating frequencies, when the mass storage is working at 33 MHz, the signal cycle is 30 ns, the 152.4 ps signal delay accounts for 0.51% of the signal cycle; when the mass storage is working at 50 MHz, the signal cycle is 20 ns, the 152.4 ps delay accounts for 0.76% of the signal cycle. Generally speaking, when the signal delay is less than 3–5% of the signal cycle, there will be no read and write problems due to the delay. The general working frequency of this mass storage chip is 33 MHz, up to 50 MHz, and the delay only accounts for 0.51–0.76% of the signal cycle, so it will not affect the signal quality. After the design is completed, the design can be imported through simulation tools to conduct signal integrity and power integrity analysis. The general solution is to extract the S parameter model of the critical net by using the 3D field extraction tool, then load the device model and S parameter model in the 2D time domain simulation tool, get the time domain waveform and eye diagram through simulation, and interpret the transmission quality of the signal. Because of the length relationship of the chapter, this is not detailed here. Readers can refer to Chap. 21. 4.
Production Data Output
After the design is completed, design checks are needed, invoke the DRC (Design Rules Check) function of the software, check the layout design for DRC errors and make corrections to ensure the correctness of the design. We can also export the design file to HyperLynx DRC for electrical rule checking to ensure that there are no SI, PI or EMI problems in the design. Subsequently, production data output is made, which generally includes files in Gerber, Drill, BOM, DXF, IDF, GDSII, ODB+, etc. In this project, the data sent to the manufacturer are Gerber, Drill, DXF and netlist files, as well as a production and processing requirements file. In addition, in order to provide the manufacturer with the mechanical design of the ceramic shell, a detailed dimension drawing needs to be output. 5.
Mechanical Design
In this project, the detailed dimension can be drawn by using the drawing function of Xpedition. First, create a user-defined layer, such as dimension layer. Then, in drawing mode, draw a left view on the left side of the design drawing, a bottom view on the right side, and a front view below the design drawing. Then, the dimension function of Xpedition is used for dimensioning, as shown in Fig. 22.10. This dimension drawing needs to be output to substrate manufacturer in DXF or PDF format, the manufacturer design detailed mechanical drawings according to the process requirements. The mechanical design includes detailed process control parameters, such as chamfer, fillet, positive and negative tolerance, and mechanical frame. See Fig. 22.11.
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Fig. 22.10 The dimension drawing in Xpedition
Fig. 22.11 Mechanical design of SiP ceramic shell
With the mechanical drawings and Gerber and drill data, the manufacture of ceramic shell can be started. According to the production output and processing requirements documents, the ceramic shell manufacturer draws detailed production and processing drawings, communicates and review with the designer, product demander and packaging manufacturer, and start the processing of ceramic shell after confirming that the technical parameters are correct. According to the process difficulty, it generally takes three to four months to complete the ceramic shell processing, followed by packaging and testing.
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22.4 Packaging and Testing of Mass Storage Chip The manufacture of the large capacity memory is divided into two steps. The first step is the production of ceramic shell, and the second step is the product packaging and testing, both of which are equally important. In the processing cycle of ceramic shell, the product packaging manufacturers need to make preparations before packaging, including the feasibility test of new technology, chip thinning, adhesive film adhesion test, chip stacking and bonding test, etc., and formulate new product packaging process specifications according to the test results, so as to prepare for new product packaging. After the ceramic shell processing is completed, the packaging manufacturer can start the packaging of new products. In general, they will first make several samples, after the sample test is no problem, then start the processing of the mass production. After processing, all samples need to pass a series of tests, which usually include: function test, electrical test, high and low temperature test, aging test, ESD test, anti-irradiation test, etc.
22.4.1 Packaging 1.
Wafer Thinning and Dicing
The first step of packaging is to thin the wafer. The factors that affect the thickness include the following. (1)
(2) (3) (4)
(5)
Number of layers in the stack. Usually, the more chips in the stack, the thinner the chips will need to be, thus avoiding excessive stack thickness, resulting in increased overall packaging thickness and weight. Support for the thinning process, due to the limitation of the process capability of the thinning equipment and the skillfulness of the operator. Packaging manufacturer’s support, due to limitations of the packaging manufacturer’s process capability and operator proficiency. Restrictions of stacking structure, if a cantilever structure appears, it needs to be considered. It is best to determine the safe thickness of the chip through experiments to ensure that the chip will not be damaged due to bonding pressure. The application scenario of the product also needs to be considered. If the chip is working in a severe environment with vibration, impact and acceleration, the thinning thickness will also need to be determined by experimentation.
After the thinning of the wafer, it is dicing. The main considerations for dicing are the following. (1)
The width of the scribing channel on the wafer and whether the scribing device can support it.
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The material of the wafer, different wafer materials have different requirements for the blade head of the scribing device. Chip adhesive materials, if using adhesive film, need to be affixed before scratching, if using glue, can be applied when assembly.
Select the chip when the scribing is finished, because some chips fail test on a complete wafer. The chip manufacturer will present a Mapping chart showing that which chips pass the test, and which fail, and the operator will need to pick out the KGD (Known Good Die) chips under the guidance of the Mapping chart, while those that fail the test can be used for some destructive testing. A Mapping chart of a wafer is shown in Fig. 22.12, where the KGD chip is represented by “1” and “X” identifies the chip that failed the test. 2.
Chip Adhere and Bonding
After selecting the KGD chips, the chips will be adhered and bonded according to the established procedure. It should be noted that heat curing is required before each
Fig. 22.12 Mapping chart of a wafer
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bonding, and the chips will not bond until they are fixed on the substrate. If there are more stacking layers, multiple heat curing is needed, the effect of multiple heat curing on the reliability of the adhesive film needs to be considered. The bonding process is very mature at present, and only needs to follow the normal operation. For more complex multi-layer bond wires, the following principles should be followed. (1) (2)
(3) (4)
From the top view, bond wires should never cross. The horizontal inclination angle of the bond wire should not exceed 45 degrees, because the larger the horizontal inclination angle is, the closer the minimum distance of the bond wire will be. The lowest chip in the stack, whose bond wires are usually connected to the substrate in the innermost ring, and so on. The bond wires of the same net can be positioned flexibly with a shared bond finger.
When design multilayer bonding, it is necessary to communicate with the bonding engineer several times to confirm the optimal position of the bond point and adjust it in time to achieve Design for Manufacture (DFM). Figure 22.13 shows a comparison between the bond wire design and the actual bond wire graph. The top one is the bond wire design, and the bottom one is the actual bond wire graph. It can be seen that the two graphs are basically the same.
Fig. 22.13 Bond wire design and actual bond wire graph
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For some of the same net bond wires that share the bond finger, the actual bonding is handled flexibly. 3.
Welding and Sealing
For ceramic SiP products with air tightness requirements, welding is required. For multilayer ceramic structures, parallel seam welding is used in most cases. Parallel seam welding can heat and vacuum the sealing device, which reduces the humidity and oxygen molecule content in the cavity. After packaging, the chip inside the cavity is not easy to be oxidized and protected from external factors. It can also use protect gases such as nitrogen during the welding process. The internal and external air tightness isolation after the welding is completed which is also helpful to protect the internal components without affecting the normal operation of the chip due to changes in external conditions. This product uses parallel seam welding and nitrogen-filled protection, which effectively ensures the reliability of mass storage under harsh conditions.
22.4.2 Machine Test Machine test generally refers to the use of ATE (Automatic Test Equipment) for chip testing, test the basic functions of the chip and the corresponding electrical parameters. The console of machine test is an integrated circuit test system that provides power supply, waveforms of different periods, and drive level information for the device DUT (Device Under Test) to be tested. 1.
Test Vector
Test vectors are Logic 1 and Logic 0 data that are applied to the pins of the device during each clock cycle for testing or operation. Logic 1 and logic 0 are represented by waveforms with timing and level characteristics and are related to waveform shape, pulse width, pulse edge or slope, and position of rise and fall edges. In ATE language, test vectors contain input incentive and expected response, which are combined to form ATE test graphics. These graphics are represented in ATE by the rise and fall edges of the system clock, the requirement of device pins for setup and hold times, and a certain formatting method. Test vectors can be optimized and converted from EDA tool-based simulation vectors (including input signals and expected outputs) to ATE format test vectors. The device model is built by EDA tool, and a Testbench simulation and verification platform is established to provide test excitation. The simulation results are verified. The input excitation and output response are stored, and ATE vector files are generated according to ATE vector format. Figure 22.14 is the test vector waveform file for this project. It is converted into a file available on the machine according to the specific format, and then imported into the machine for testing.
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Fig. 22.14 Test vector waveform file
2.
Analysis of Problems in Machine Test and Precautions
There are many problems encountered in the process of machine test, especially for the engineer who first contacted the machine test, which are difficult to avoid, such as the vector that the software can run normally in the simulation environment cannot pass when running on the machine. There are many different working modes between the testing machine and the software simulation environment, and there are also many different working modes between chip in testing and in real work environment. The difference will cause a misunderstanding and lead to problems. For example, in practice, the reset action occurs when the chip is first powered on. Since the chip remains powered on all the time, the reset operation is not necessary at each operation and the chip can operate normally. When a vector is running on testing machine, every vector rerun means that the chip is powered on again. In this case, if there is no reset operation in the vector, the chip will not respond properly. From the machine to see, the vector cannot run through. Therefore, in addition to the correct understanding of the chip operation mode and timing parameters, it is necessary to understand the difference between the vector operating mode on the testing machine and the actual operation of the chip in order to correctly analyze the problem and find out the solution.
22.4.3 System Test System testing, also known as board-level system testing, refers to simulating the real working environment to read, write and erase the memory chips to verify whether they are working properly.
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This project uses all the software and hardware equipment of a certain satellite model to test the new products of mass storage chip. The basic function test process and test results are as follows: (1) (2) (3)
(4) (5) (6)
Power on and full erase, telemetry parameter display erase completed. All analog data sources are opened, data is written at 554Mbps, and telemetry parameters show that data storage is successful. Start the data playback, the ground frame unpacking software shows that the frame and package are continuous, and the data in the package are continuous addends, which are completely consistent with the expected results. The first test data amount is 1.2 GB, and the data interpretation is correct. Erase it completely again, rewrite the data, and play back again, the data is correct. Through the function test under the simulation of the actual working environment, it can be judged that the chip function is working perfectly normal.
Figure 22.15 below is the system test board, in which the thinner chips in front are new products of mass storage, and the thicker chips in the back are old products. In addition to the fully normal functions of the new products, the parameters of the new products have also been improved.
Fig. 22.15 Testing the mass storage chip with system test board
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22.4.4 Follow-Up Testing and Cost Ratio In addition to the above tests, a series of tests have been carried out on the mass storage chip, including thermal shock, temperature cycle, mechanical shock, sweep frequency vibration, constant acceleration, bond strength, chip shear strength, steadystate life, sealing, internal moisture content, moisture resistance, and so on. After the diagnostic test confirms that there is no problem, the prototype can be produced according to the existing process, otherwise the process needs to be improved until the diagnostic test is completely passed. All normal products are processed in one production batch. After processing, they need to pass a series of tests, which usually include: functional test, electrical performance test, high and low temperature test, aging test, ESD test, radiation resistance test, consistency appraisal test, etc. At the same time, each mass storage chip needs to pass board-level system test, carry out read, write and erase function tests under normal, high and low temperature conditions respectively, and identify possible bad blocks, and sample some products for performance test to improve the frequency of the product, test the changes of its function, power consumption and other parameters. In order to make the test non-destructive, that is, the customer gets a brand new product, it is necessary to customize the special test socket and design and make a special test board. Figure 22.16 is the test board for the mass storage chip. There are eight test sockets installed on the test board, which can test 8 products at one time. Only if all the above tests pass successfully, a mass storage chip based on SiP technology will be qualified, can be issued a certificate, approved for market, and be available to users. Based on the funds already invested, we have calculated the cost of each mass storage chip, which is calculated according to 500 products. Among them, bare chips
Fig. 22.16 Mass storage chips, sockets and test board
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Fig. 22.17 Cost proportion to each mass storage chip
(wafer) account for 27%, ceramic substrate accounts for 11%, packaging accounts for 24%, and testing accounts for 38%. As shown in Fig. 22.17, testing accounts for the largest proportion, thus showing the importance of high-level product testing. Note that this only includes the minimum cost. SiP design environment and software configuration, board-level test environment and software development are not included.
22.5 Comparison of Technical Parameters Based on SiP technology, the mass storage chip solves three core problems that existing products cannot solve. It improves greatly in product volume, weight, performance and quality level, and also makes size and function compatible. It can gradually replace existing products in the process of product upgrade. The following table compares the parameters of old and new products. From Table 22.2, we can see that the mass storage based on SiP technology are compared with existing older products. (1) (2) (3) (4) (5)
Reduce volume to one-fourth of existing products Reduce weight to 41% of existing products Increase quality level more than twice 1.25 times better performance More scalable storage capacity
3
Mass storage chip based on SiP technology
Thickness (mm)
12
Product picture
Existing mass storage chip
Product name
Table 22.2 Comparison of product technical parameters
2.73
6.65
Weight (g)
Airtight ceramic packaging
Non airtight plastic packaging
Quality level
Performance
Routing rules are Maximum strictly controlled operating frequency 50 MHz
Only electrical Maximum interconnection operating can be completed frequency 40 MHz
Design rules
128G bit
128G bit
Storage capacity
Pin function compatible replace in situ
Pin function compatible
Compatibility
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(6)
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Pins and functions are fully compatible and can be replaced in situ.
In addition, because the heat transfer performance of ceramic materials is much better than that of plastic sealing materials, new products also have a greater advantage in heat dissipation. After the product is successfully listed, because its size, weight, performance and quality level are much higher than those of existing foreign products, it can completely replace the foreign products and create the market value it should have.
Chapter 23
SiP Project Planning and Design Case Tianrui Zhu and Xiaohong Wang
23.1 SiP Project Planning SiP (System in a package) has become one of the most popular words in the field of microelectronics in recent years. Because of its many advantages, SiP is regarded as a magic weapon to continue or surpass Moore’s law by many microelectronics practitioners. At present, the planning and implementation of SiP projects are also in a turbulent wave. The author has experienced the planning of many SiP projects. In this chapter, the author will analyze the characteristics of SiP and clarify what kind of needs or characteristics of electronic systems are more suitable to be realized by SiP. Then, through the typical projects and products around the author, this chapter expounds the necessary factors to SiP. Finally, the actual project participated by the author is put forward.
23.1.1 Characteristics and Applicability of SiP If external factors are excluded and SiP is only regarded as an implementation method of electronic system, what characteristics and problems are suitable for the implementation of SiP? First, we need to clarify several of the most obvious and exclusive advantages of SiP technology.
T. Zhu (B) · X. Wang Beijing, China e-mail: [email protected] © Publishing House of Electronics Industry 2022 S. Li (ed.), MicroSystem Based on SiP Technology, https://doi.org/10.1007/978-981-19-0083-9_23
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Miniaturization
The most basic feature of SiP is miniaturization, which can greatly reduce the size of the electronic system. SiP products can integrate multiple individual chips, wires and passive devices in the electronic system in one package, that is, the devices, packages and motherboard can be reduced to a single system-package. This integration reduces the system size from two-dimensional and three-dimensional aspects. From the two-dimensional perspective, the package area of each individual chip is omitted, and the wide wires on the PCB, various cables and connectors between boards are reduced and integrated into the package; From the three-dimensional perspective, the separate devices on the PCB are stacked in three-dimensional, so that the total area of multiple chips can also be far less than the accumulation of the area of each chip. Generally, the volume of the electronic system realized by SiP is only one tenth or less of the board-level prototype system, and the weight is also greatly reduced. The weight of multiple packages, equipment shells, connectors, cables, PCBs, etc. is removed. SiP locks the weight of electronic equipment at the “gram” level, fully supporting the applications of mobile communication, wearable devices, medical implants, handheld devices and unmanned equipment. It also provides convenience and cost advantages for space applications (Fig. 23.1). 2.
Heterogeneous Integration-Different Materials
The implementation of SiP can be similar to the PCB. The components with various functions produced by various materials and processes are assembled on the substrate to provide an overall system. The high integration of different materials and processes is another major feature of SiP technology, which we call heterogeneous integration. There are many kinds of semiconductor materials. The commonly used semiconductor materials are divided into elemental semiconductors and compound semiconductors. Elemental semiconductors are semiconductor materials made of
Fig. 23.1 SiP integrates electronic systems in a single package
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Table 23.1 Characteristics of some semiconductor materials Materials
Band gap (eV)
Melting point (K)
Main application field
Si
0.7
1687
Ge
1.1
1221
Low voltage, low frequency and medium power transistor, photodetector
2nd generation
GaAs
1.4
1511
Microwave, millimeter wave devices, light emitting devices
3rd generation
SiC
3.05
2826
GaN
3.4
1973
ZnO
3.37
2248
High temperature, high frequency, anti-radiation and high power devices Blue, green or purple led, semiconductor laser
1st generation
a single element. There are mainly silicon, germanium and selenium, among which silicon and germanium are most widely used. Compound semiconductors are divided into binary system, ternary system, multicomponent system and organic compound semiconductors. Binary compound semiconductors include gallium arsenide (GaAs), indium phosphide (INP), cadmium sulfide, etc.; Ternary and multicomponent compound semiconductors include gallium aluminum arsenic solid solution, Gallium Germanium arsenic phosphorus solid solution, etc. Organic compound semiconductors include naphthalene, anthracene, polyacrylonitrile, etc. In terms of the development process of semiconductor materials, it can be divided into the first, the second or the third generations. For example, the first generation semiconductor materials mainly refer to silicon (Si) and germanium (Ge) element semiconductors; The second generation semiconductor materials refer to compound semiconductor materials, such as gallium arsenide and indium phosphide; The third generation are mainly semiconductor materials with wide band gap (band gap width Eg > 2.2 eV) represented by silicon carbide (SiC), gallium nitride (GaN) and zinc oxide (ZnO) (Table 23.1). Different semiconductor materials have different characteristics. For example, the hole mobility of germanium is four times that of silicon and the electron mobility is twice that of silicon; Gallium arsenide can be made into semi-insulating and highresistance materials with a resistivity of more than 3 orders of magnitude higher than that of silicon and germanium, and its electron mobility is 5–6 times higher than that of silicon; The third generation semiconductor materials have the characteristics of wide band gap, high thermal conductivity, high breakdown electric field, high radiation resistance and high electron saturation rate. They are suitable for the manufacture of high temperature, high frequency, anti-radiation and high-power devices. In a whole electronic system, components with multiple characteristics are often required. That means that if devices with different characteristics, materials and processes can be integrated together, the integrity and applicability of the electronic system will be greatly improved. At present, different materials cannot be freely manufactured together on semiconductor chips, so it is impossible to integrate the characteristics of various semiconductor materials in the same system on a single
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chip. According to the production process and characteristics of SiP, the semiconductor devices of different materials are first taped out without packaging, and the SiP design is carried out synchronously. The integration of semiconductor devices of different materials, that is, heterogeneous integration, can be realized in the SiP system. 3.
Heterogeneous Integration-Different Structures
Heterogeneous integration (with different structures), refers to the integration of systems under different architectures in electronic devices. The architecture here contains multi meanings. It can be the architecture of processing cores, such as ARM, SPARC, DSP, etc., or it can be the architecture difference of general MCU and SOC, it can also be the difference between multi-core and single core, the difference of bus logic within the system, the difference of semiconductor process nodes, etc. The integration of heterogeneous systems is not difficult to realize on PCB. But under the trend of miniaturization of electronic systems, the industry has always considered the chip level implementation of heterogeneous systems. Heterogeneous integration on SOC is very difficult. The original process feature sizes of each chip may be different, and multi clock domain on chip will also bring great difficulty to the back-end. In addition, SOC has high trial and error cost and inflexible architecture change. In the contrast, heterogeneous integration on SiP is much easier. Firstly, the preliminary verification is based on the heterogeneous system design at PCB level, and then implemented in SiP. There is no barrier due to the monolithic integration process or design requirements. Since the Pentagon first proposed heterogeneous integration technology in the 1990s to integrate microelectronic devices, optoelectronic devices and MEMS devices and develop chip-level integrated Microsystems, major manufacturers in the industry are now designing and planning heterogeneous integrated SiP. The high-performance SiP scheme launched by ON Semiconductor is used for precision sensing of portable medical equipment, that is, the scheme of ARM + SRAM + Flash + AD + temperature sensor is adopted; The ST and AMS jointly launched NFC design, using ARM + security microcontroller + Flash + AD + RF. Intel cooperated with Altera that year to launch integrated products of SOC + FPGA + DRAM + SRAM + ASIC + processor + analog components for communication, highperformance computing, broadcasting and military fields; After integrating the relevant resources of Altera, Intel is now planning for heterogeneous SiP integration more comprehensively. The new products will use the innovative embedded multi-core interconnect bridging (EMIB) technology, heterogeneous integrated analog devices, memory, CPU, ASIC and single-chip FPGA architecture (Fig. 23.2). 4.
Low-power Consumption
In the SiP, all bare dies are relatively concentrated, especially the auxiliary circuits of key chips can be placed as close to key chips as possible. The interconnections between chips are very short, and the power consumed in interconnection is greatly reduced, which effectively reduces the total power consumption.
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Fig. 23.2 Schematic of heterogeneous integrated products by Intel
In high-performance storage applications, a large number of parallel IOs are usually used to reduce power consumption and realize high-density interconnection. This demand can be well supported in SiP system, especially in silicon interposer. Taking DRAM as an example, when the junction temperature is higher than 80 °C, its refresh frequency increases, resulting in the increase of power consumption and heat. If integrated in the SiP system, the power consumption is relatively reduced, the generated heat is reduced, the temperature is controlled, and the refresh frequency is not increased, so as to enter a virtuous cycle and ensure the low power consumption of the whole system, which is the advantage of SiP. 5.
High-performance
The performance of the system is usually roughly estimated based on the maximum frequency of its processing unit. Under similar conditions, the higher the maximum frequency, the higher the system performance. The length of the signal line has a great impact on the maximum frequency. The closer it is to the processor core, the higher the running speed of the device. In the SiP design, the package body is removed and the wires on the PCB board between packages is removed. Instead, the interconnection between single bare dies is replaced. The routing length will be more than 1–2 orders of magnitude lower than the routing length at the PCB board level, and the transmission line delay will be reduced accordingly, which is bound to reduce the access delay, improve the performance, and significantly improve the communication bandwidth and rate. Compared with PCB, the absolute length of wires in SiP is shorter, and the parasitic effect of interconnect can be effectively controlled to improve the transmission performance, so as to meet the requirements of high-performance system.
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Conducive to Intellectual Property Protection
There’s also a feature of strong confidentiality of SiP. SiP can “package” the data paths of the electronic system in the package, and cannot be directly contacted by the outside world. If you want to obtain, you must encapsulate the physical damage. But the integrity of the system cannot be guaranteed after the damage, so it is less likely to be stolen or copied. From another point of view, SiP encapsulates the core chip and its supporting circuits, such as the program run by CPU and the configure data files for FPGA. They do not need to be read from the periphery. It also avoids the acquisition of software and data, and can protect the key. In this way, the intellectual property protection of electronic system is strengthened from two aspects of both software and hardware.
23.1.2 Factors That Need to Be Identified for SiP Projects Under the new situation, the development of integrated circuit industry is facing both great challenges and rare opportunities. Therefore, the national and local governments continue to issue relevant policies to support the development of integrated circuits. In recent years, led by the outline for promoting the development of the national integrated circuit industry issued and implemented by the State Council and represented by the national integrated circuit industry investment fund Co., Ltd., the state has increased its investment in the integrated circuit industry. Therefore, in the process of SiP development and industrialization, in addition to carrying out corresponding research and development by themselves, each company is also actively participating in the overall national planning and applying for relevant projects to promote the development of SiP technology and support the research and development of typical products. We must be clear that there are many differences between SiP for project R&D and SiP for product production. In this section, the author will discuss the factors and precautions that must be clear when undertaking and developing SiP projects. The author roughly classifies the SiP projects, and finds that there will be two different types: technology research oriented projects and product development oriented projects. If it is a technical project, it is more related to whether the technology studied is more urgently needed and more valuable for application on the whole SiP technology roadmap; If it is a product project, it is more related to whether the R&D product is suitable for implementation with SiP technology and whether it has market prospects. In general, the establishment of SiP project is directly related to the theoretical level and application value of research direction, as well as the investment income of research funds. When applying for SiP projects, the principles of weighing shall be fully considered and the following principles shall be met at least.
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Innovation
Innovation is the most important principle in SiP project planning at this stage. The investment of SiP related projects focuses on the main line of rapid development. The framework of technology and industry should be built first. Most research resources should tend to the development of relevant new technologies. Therefore, innovation is the top priority at present. We should consult a large number of literatures, conduct extensive research, pay attention to the trend of technological frontier at any time, maintain communication with colleagues in the industry at any time, comprehensively analyze the relevant research status, level, development trend and existing problems in the industry, and timely update the direction and focus of project topics in combination with our own projects, so as to ensure the views referenced and quoted in the demonstration process and the data are up-to-date, and the research direction is at the leading level at home and abroad. 2.
Superiority
SiP technology is an implementation method in a narrow sense, but in a broad sense, it involves a long industrial chain, such as design, simulation, packaging, testing, process, material, reliability, etc. We should first consider our professional direction, focus on the counterpart direction of our specialty, and conduct in depth research in this field, which is helpful to the development of the whole SiP technology. SiP technology itself originates from the junction of component level and single board level (PCB) electronic system, so it has the attributes of component level and PCB level. The development of SiP technology defines systematicness as an important feature, so it has the attributes of system level as well. Therefore, comprehensive consideration should be made from different levels. For example, from the component level, consider the process realization, structural design, etc.; From the board level, consider the selection of integration modules and functions, as well as the evaluation and comparison of integration effects; From the system level, it focuses more on the integration and application of multiple types of devices or modules in SiP, as well as the definition of system architecture and bus configuration. Truly match technology, products and market of SiP, and give full play to their advantages. 3.
Feasibility
The SiP project needs to really implement the feasibility analysis. At present, the SiP industry has not formed a unified technical development route as a whole, and there is no more reference for project R&D process management. The upstream and downstream industrial chains of the project have uneven understanding of SiP, and there is no large amount of practice, the project evaluation has not formed a system, the standards are not mature. Even the project experts may do not have formed thoughts on how to evaluate and whether it is feasible yet.
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Therefore, during project planning, the feasibility of SiP project needs to be carefully considered. We should do extensive investigation, comprehensive analysis and grasp the details, so as to put forward a truly feasible SiP project planning scheme.
23.2 Design Rule Import The typical SiP product planning is usually initiated by the miniaturization requirements of the user’s electronic system. Under the premise of continuous improvement of performance and function, continuous expansion of application and continuous unification of multiple application platforms, when the design of PCB has reached the limit and cannot meet the requirements of miniaturization of electronic system, if the system conditions are suitable, SiP integration can be carried out, so as to reduce the area occupied by chips in the system and interconnection on PCB board. When the system architecture is mature, because the risks brought by performance and interconnection mode are controllable, SiP is the best integrated solution to the size-sensitive electronic systems. The SiP designer usually evaluates the needs of users and the currently formed design. During the evaluation, the SiP designer will make a preliminary plan for the system architecture definition, bare die selection, packaging form, process scheme, overall dimension, development cycle and cost of the SiP module in combination with available resources. In addition, there is an early warning for big changes between the design of SiP and prototype PCB, and communicate with the user to confirm the scheme. The following takes a SiP project as an actual case to share the whole process from user intention requirements, gradual decomposition and analysis to the formation of specific SiP design schemes and rules, and provide an example of SiP project import for readers’ reference.
23.2.1 Project Requirements and Scheme Analysis In this example, the user is a task contractor, which undertakes the R&D task of a subsystem in a complete machine. In the research and development of the whole machine, the user intervened relatively early. When the whole machine had a preliminary function division and definition, it began to verify, built a platform, and started software and algorithm design. After that, the overall plan of the whole machine was made, and the size and connection mode of all subsystems were specified. At this time, the user found that the size and localization rate of the built platform could not meet the needs of the whole machine, so he wanted a way of higher integration. Considering the project development time and risk assessment results, it is found
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that SiP is an ideal solution. Therefore, it is expected to start the planning and design of SiP project based on the built verification platform. 1.
Product Status
The system undertaken by the user mainly completes the communication and control tasks, which is divided into five separate small system boards. The five system boards can be used in combination or separately. The functional requirements and overall dimensions of the five boards are as follows. No. 1 PCB for control task, main functions: data receiving and transmitting control of Ethernet interface, keyboard information input, liquid crystal display output, data receiving and transmitting of serial port, signal control of modulation and demodulation unit; The overall dimension is about 200 mm × 80 mm, of which the components layout area is about 190 mm × 65 mm. No. 2 PCB for control task, main functions: data receiving and transmitting control of Ethernet interface, data transmission and reception of serial port and signal control of modulation and demodulation unit; The overall dimension is about 280 mm × 140 mm, of which the components layout area is about 265 mm × 128 mm. No. 3 PCB for control task, main functions: receive the control information of the main monitoring through the Ethernet interface, and control the rotation of the 6-chamber motor, the motor tuning status indicator, the parameters set by the storage filter and the number of motor rotation steps at the same time; The overall dimension is about 120 mm × 70 mm, of which the components layout area is about 110 mm × 55 mm. No. 4 PCB for monitoring task, main functions: collect alarm signals including temperature alarm, reflection alarm, input power alarm, output power alarm, etc., detect the working current of power amplifier, control the speed of chassis fan, detect the speed of chassis fan, report the alarm, working current and other relevant information of the power amplifier unit to the net management, etc.; The overall dimension is about 122 mm × 101 mm, of which the components layout area is about 122 mm × 70 mm. No. 5 PCB for monitoring task, main functions: set the working frequency of the equipment, set the NC attenuator of the transmission channel, monitor the working state of the synthesizer, give an alarm when the lock is lost, have the power on indicator and working indicator, and store the parameters of SFXJ working frequency and attenuation; The overall dimension is about 220 mm × 80 mm, of which the components layout area is about 210 mm × 68 mm. In addition, the environmental adaptability requirements of the five boards are as follows: Operating temperature: −30 to +55 °C; Storage temperature: −45 to +65 °C; Relative humidity: not higher than 95% ± 3%; Vibration: the equipment can withstand the vibration stress of 2000–4000 km highway transportation, and the vibration time per axle is greater than 75 min. 2.
Scheme Analysis
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Next, the author launches the process of joint analysis between SiP designer and user in this case design for readers’ reference. Users expect that the hardware platform of the five PCBs should be as unified as possible in terms of main components and development environment, so as to reduce the difficulty of use, reduce the complexity of design and production, and reduce the risk of production and procurement. Therefore, in SiP design, the core devices on five boards are unified, and a minimum subset is considered in combination with available resources, which can meet the functional and performance requirements of all five boards. In the user’s prototype system, most control functions and interfaces are built and implemented by FPGA. The user platform selects series FPGA from Xilinx, the development environment and process are relatively unified, and they are used as much as possible in SiP design. The application environment of the user’s communication system is the ground environment without too harsh environmental requirements. Considering the cost, time and volume, the SiP designer recommends the user to use the form of HDI substrate and plastic packaging. The whole system has the requirements of localization rate. The selection of core chips in the system must be carried out within the scope of domestic devices. In addition, confidentiality measures need to be added. If the idea of unified SiP design of five boards is adopted, it is necessary to limit the overall dimension of SiP module according to the minimum horizontal and vertical routing size on the board, and then consider the board level DFM design and allowance. According to multi-party calculation, the overall dimension of this SiP is limited to within 35 mm × 35 mm. Sort out the specific functional requirements of the five boards in the previous section. The system has personalized interfaces have various types, uncomplicated logic and low speed. It is considered to integrate an FPGA in SiP to realize various interface logic without too high-end series to reduce power consumption. Among the functions of the five boards, there is an obvious need of control. Therefore, a control CPU can be selected to complete most control functions. To sum up, the SiP design is planned to be implemented with CPU + FPGA as the core architecture. The public demand and control need shall be completed by CPU as much as possible, while the personalized interface and expansion function shall be realized by FPGA. At the same time, some other resources on the board or other requirements of the system can also be transplanted to FPGA to realize the overall planning. There is not much time for the project, so the development cycle of SiP should first be short. The time of design and production should be strictly controlled. Secondly, the success rate of SiP design should be high. It should be formed at one time as far as possible in both design and process. Finally, the application of SiP should be simple. It is best to complete the development of the bottom layer, and users only need to develop on the top layer. Scheme analysis is a relatively divergent process, and everyone may has a different perspective and view. The author believes that it is necessary to solicit more users’ opinions and make full communication.
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23.2.2 Implementation Scheme of SiP With the specific technical scheme, the design can be started. From this step, the technical requirements of users should not be changed greatly. If there are new requirements, they should be changed in a small range or solved at the PCB level. 1.
Core Devices and Architecture
Starting from the architecture design, the composition and use mode of each device in the SiP module should be gradually clarified, and the main interconnection relationship related to function realization should be determined. The SiP design should start from the selection of core devices and architecture design. The SiP module must be defined for a certain function or application scenario, so the part that directly completes the core requirements of this function or application scenario is the core of this SiP module. The core devices selection and architecture are the foundation of SiP project. They will not change after confirmation. The selection and architecture of other devices are to serve them. In this example, because we have the intention of CPU + FPGA as the core architecture, we choose them respectively, taking into account the communication mode between them. First, the CPU. At that time, the author had two items for the CPU that met the target parameters. The comparison of the important factors is as follows (Table 23.2). From the above comparison, it can be seen that the main frequency difference between the two is not much, and both can meet the system requirements; From the perspective of architecture, the application breadth and support resources of ARM are better than SPARC V8; In terms of main resources and interfaces, CPU1 has more serial ports, PWM and GPIO than CPU2, which can better meet the requirements, while CPU2 has rich built-in memory resources and is more convenient for application; In terms of product maturity, CPU1 has been mature applied, while CPU2 can only provide samples with low maturity. User wants the Ethernet, but neither of them is available. The design cycle is urgent, maturity will be a very important consideration, and CPU1 is a better choice. Table 23.2 Comparison of alternative CPUs CPU
Working frequency (MHz)
Architecture
Main resources and interfaces
Localization
Maturity
CPU 1
100
SPARC V8
Serial port*4, I2 C*2, PWM*10, GPIO*64, 32 KB cache, AD*2
Yes
Mature application
CPU 2
80
ARM
Serial port*3, Yes I2 C*2, PWM*1, GPIO*51, 128 KB FLASH, 20 KB SRAM, AD*2
Samples
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In the user’s original prototype system, most control functions and interfaces are built and implemented by FPGA, and the user platform adopts series FPGA from Xilinx. Therefore, we want to select Xilinx series FPGA or FPGA compatible with it. Next, we will sort out the FPGA resources we have mastered. At that time, we could master the FPGA fully compatible with virtex and virtex II series from Xilinx, with the number of gates ranging from 300k to 3 million, and other parameters can also meet the needs of users. Considering the power consumption, chip size and maturity of several FPGA devices, 300k-gates FPGA of virtex series is selected for design. According to its application and characteristics mainly used for low-speed interface expansion, it is connected on the bus as a peripheral of the CPU to save more resources. So far, we have completed the selection of core devices and interconnection architecture design of SiP module, and determined that this SiP is designed using CPU (SPARC V8 Architecture) + FPGA (compatible with 300k-gates FPGA of Xilinx virtex Series). 2.
Peripheral Auxiliary Device
First of all, don’t over design. SiP is limited by the product form. Don’t be large and complete. Not over design can avoid the core device to make insufficient use of peripheral resources and waste cost, area, power and so on; Secondly, we should also pay attention to the design of core indicators with a margin, not just to meet the immediate needs. When the user makes a little modification or needs to expand the application, it can avoid that there is no margin, which makes the peripheral auxiliary devices become the bottleneck of the system; Third, we should learn to make trade-offs. When the user needs cannot be fully realized, we should give up. The author suggests that the measurement of the above principles should focus on the products to be replaced and subsequent applications, that is, the current and future applications of the product should be the main line, and a little margin should be considered in the performance and quantity of peripheral auxiliary devices. The expected application of the SiP in other schemes and fields is supplemented. Before the demand is determined, do not increase too many resources for the application of other schemes, especially different types of peripheral auxiliary devices, so as to avoid over design. In this example, the amount of data is small and the application environment is not extremely bad. But the SiP is a self-contained system. Therefore, the storage array considers providing both nonvolatile storage and volatile storage, but the data and program are not divided separately. Combined with the performance requirements of CPU, SRAM and flash memory are preliminarily selected to be integrated in the system. How to choose the memory capacity? As we all know, when designing the CPU, it generally leaves a great margin for the memory space that can be supported. In this way, more users and applications can be supported, which can better meet some special application methods and has good scalability. For SiP design, the area and power consumption overhead and cost waste caused by too large memory will bring
23 SiP Project Planning and Design Case Table 23.3 Storage space mapping for the alternate CPU
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Address range
Capacity
Mapping
0X0000 0000 ~ 0X1FFF FFFF
512M
PROM
0X2000 0000 ~ 0X3FFF FFFF
256M
I/O
0X4000 0000 ~ 0X7FFF FFFF
1G
SRAM/SDRAM
risks to the whole design. Therefore, select the appropriate storage capacity without over design. The mapping and size of CPU storage space in this design are as follows (Table 23.3). The non-volatile storage space of the CPU reaches 512 MB, while the volatile storage space reaches 1 GB. We investigated the amount of the user’s current program and the amount of other user applications with the same CPU, combed the available memory resources, and preliminarily proposed that the capacity of SRAM is 1 MB and that of flash is 8 MB. In addition, considering the temporary storage requirements of users for images, we expand the memory type. The largest image exceeds 10 MB, which needs to meet the volatile storage of its maximum image size at least. However, the size of SRAM die is generally large, 10 MB is not suitable for SiP integration. But size of SDRAM die with the same capacity is much smaller than SRAM, which can also meet our needs. Finally, we chose 16 MB SDRAM to integrate into the system, which not only meets the needs of users for temporary image storage, but also meets the needs of future users for small operating systems (Fig. 23.3). So far, the overall architecture of the core part of the SiP module has been designed. On this basis, the later design will make small-scale adjustments according to the specific needs of users and the convenience of applications, but the main architecture will not change. 3.
Layout Planning and Design Rules
CPU
Space for PROM Space for IO
FLASH
FPGA
Space for SRAM/SDRAM
SDRAM
Fig. 23.3 Block diagram of the SiP module system architecture
SRAM
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(1)
(2)
(3)
(4)
Layout: pre layout the selected bare dies. When all the dies are tiled, the size of SiP module will not exceed 32 mm × 32 mm, there is still some margin from the 35 mm × 35 mm limitation of the system. Therefore, it is proposed to lay the dies in a flat layout and simplify the process as much as possible to reduce the risk and cost. According to the power consumption of each die, if the CPU and FPGA have large calorific value and large size, they shall be placed diagonally, and the other dies shall be arranged as appropriate according to the interconnection relationship and routing direction; Layers, trace width and line distance: the design is carried out by using HDI organic substrate and plastic packaging, and is designed according to 8-layer (2 + 4 + 2) substrate. The layout design principle is to ensure sufficient power supply and ground space first. In the case of 8-layer substrate, 4 layers of signal and 4 layers of power supply + ground are proposed, so that at least 4 complete planes can be referred to and the routing space is sufficient. It can be realized only with organic substrate, with a minimum trace width of 50 µm and a line spacing of 50 µm. Heat dissipation design: when the SiP works normally, the power consumption is not higher than 2 W, and the limit case is not higher than 2.5 W. Combined with the user’s thermal simulation of the ambient temperature of the SiP, there is no need to increase the heat sink; In order to improve the reliability and expand the application ambient temperature range in the future, the heat dissipation capacity is strengthened by adding heat conduction through holes in the design, without increasing the area or routing difficulty. Packaging process: the selected dies are based on wire-bonding process. There are mature bonding and lead-out designs in the packaging design of single chip, which can provide reference for SiP design. The CPU has two laps of pads with high density. It requires four layers of bond figure. Different layers also need to specify different bond wire models.
So far, we have seen the whole process of a SiP project from the initial background and requirements to the determination of design rules.
23.3 The Design of SiP Products After the project planning and design rules are imported, the specific design of SiP products can be carried out. Generally, before the formal design or in the design process, it is necessary to pass the PCB board level functional verification, which is a good support for the correctness of SiP solution. After the scheme was implemented, the PCB function verification board would be first designed and tested whether the function can meet
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the demands of customers. Through the test, all kinds of problems that may exist in the design can be found modified. Through the board-level function verification, the function and performance of the module can be further understood, which lays a foundation for the subsequent of SiP schematic design and layout design. The design of the functional verification board adopts the encapsulated chip corresponding to the bare chip in SiP, and the functional design is carried out according to the actual requirements. Its advantage is that it can be tested, found shortcomings, modified scheme, and ensure the correctness of the schematic design. The more sufficient the functional verification of the board is, the smaller the problems will be in the subsequent SiP design and application.
23.3.1 Symbol and Cell Library Creation The SiP design adopts Xpedition design process, including several steps such as library creation, schematic design, layout design and simulation, etc., while the design process of other companies are similar with minor differences. The first step of design is to establish the device library, including the schematic library Symbol and the layout library Cell, and map them into the device library Part. The design method of schematic symbol library are basically the same as PCB schematic symbol library. Unlike the PCB symbol, the number and definition of bare chips are different from those used on PCB, so they cannot be reused, and the design needs to be re-designed in accordance with the definition of bare chips. In the design of layout Cell, the overall size and height of die should be taken into consideration. Generally, the size of die includes the dicing track, and the height of die should be designed according to the design requirements and the thinning process capability of the wafer, which can be generally set at 200–300 µm. In addition, we also need to create the corresponding symbol and cell for packaging shell, The schematic symbol of the package shell is created in the same way as the chip symbol, the cell need to be created according to the type of packaging, physical size, pin number and pin spacing, the height of the package cell can generally be set to 0. After schematic symbols and layout cells are designed, they are mapped into Parts, and then SiP schematic design can be carried out.
23.3.2 Schematic Design SiP schematic design mainly refers to the PCB board-level principle verification and board-level test results, calls the schematic symbols of the bare chip, and appropriately cuts and modifies the board-level schematic design to obtain the SiP schematic design drawings.
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SiP schematic design has passed many verifications and tests of the PCB boardlevel verification board. The principle scheme has been fully verified, and the SiP schematic diagram has been obtained, laying a solid foundation for the subsequent SiP design and production. The SiP mainly integrates 5 kinds of chips: CPU, FPGA, SDRAM, SRAM, and FLASH. In addition, designers should pay attention to that, in the design of SiP schematic diagram, in addition to ensuring the correct interconnection between the chips, the connection relationship between all the chips and the package shell should also be reasonably arranged. Therefore, it is necessary to create a schematic symbol of the package shell in library. In order to facilitate the exchange of pins, the schematic symbol is generally not split. Because the schematic diagram of the package shell has more symbol pins, the size is also relatively larger, and it is usually placed on a separate page and connected with chips through net names. Connect the net to the pins of the package shell according to the type and referring to the order of arrangement on the chips, and then optimize the connection relationship through pin exchange in the subsequent layout design software.
23.3.3 Layout Design In order to improve the application range of a SiP product, we evaluate the product during the design process. In this case, we found that the architecture of the product is highly versatile. In addition to customizing the needs of users, it can also meet the core needs of many control electronic products. In order to adapt to different application scenarios, this example expands the ceramic packaging form on the basis of the original plastic sealing form. Therefore, this product adopts two packaging forms, which are plastic packaging and ceramic packaging. Plastic packaging is for conventional commercial applications, while ceramic packaging is mainly for high-reliability applications. In order to maintain the compatibility of the two packaging forms, the shell size of the two packages are designed as 31 mm × 31 mm. PBGA415 packaging form is used for plastic packaging, and CBGA415 packaging form is used for ceramic packaging. Pin definitions are also consistent. This design is convenient for users to choose freely, and flexible choices can be made when the product application environment is expected to change to meet the needs of different applications. 1.
Plastic Package Substrate Design
After the size of the substrate is determined, the layout of bare chip is carried out first. The bare chip is placed in the layout design according to the functional definition and connection relationship, and the spacing is adjusted according to the process requirements provided by the manufacturer. The length of the bond wire and the
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distance of the trace fan out should be reserved to prevent the problem that the lead cannot be fanned out normally in the later stage. After the layout is determined, we then determine the design layer stackup, plan which layers need to be designed as signal layer, which layers need to be designed as Power or Ground layer, and how to divide the plane layer, then adjust them according to the actual design requirements. The plastic package substrate is designed in accordance with 8 layers (2 + 4 + 2) layer stackup, in which 4 layers are allocated as signal layer, 4 layers as power and GND layer, so that there are 4 complete planes for high-speed signal reference, the minimum trace width is set as 50 µm, and clearance is also set as 50 µm. The routing rules of SiP and PCB are basically the same, which are cross routing in adjacent layers, expanding power traces, key signal traces as short as possible or increase anti-crosstalk design, using as few as possible vias. Because SiP is more compact than PCB in size, the routing density is much higher, so we need to pay special attention to the key signal first. All differential signals have been sorted out in the design, and signal crosstalk and interference issues have been considered. Keep key signal connections as short as possible. Thermal design, organize the power consumption of each bare chip and the thermal conductivity of the adhesives, plastic packaging materials, substrate materials and other materials used by the manufacturer for thermal analysis. Modeling in Thermal Analysis Environment FloTHERM, input data such as power consumption and materials for thermal simulation, and check whether the heat distribution of the simulation results is uniform, whether the temperature gradient of the whole plastic substrate is too large, whether the local temperature is too high, and whether the chip junction temperature exceeds the maximum value. According to the simulation results, adjust the layout and heat dissipation scheme of bare chips. The design can meet the design requirements through thermal simulation, and there is no need to modify the scheme. In addition, after the completion of the SiP design, it is better to carry out the simulation of signal integrity, power integrity and EMC. Through the simulation, check whether there are problems in the power supply, signal and EMC. If there are problems, we can adjust the signal trace and power plane, and to completely solve the possible problems in the design stage. Figure 23.4 shows the design screenshot of the plastic package substrate: 2.
Ceramic Package Substrate Design
The ceramic package substrate and shell are an integrated structure, so the ceramic substrate design is also called the ceramic shell design. Compared with plastic package, ceramic substrate design is relatively more complicated. The structure design in CAD software is required firstly. In order to maintain compatibility, the outer dimensions of the ceramic substrate are the same as the plastic packaging substrate. First, make a solder ring on the edge of the ceramic substrate according to the size requirements of the package manufacturer. The width of the solder ring is designed to be 1.5–1.7 mm according to the processing capacity, and then the chips are laid out in the design.
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Fig. 23.4 Plastic package substrate design (front and back)
Due to the ceramic substrate process, the chip layout cannot be as compact as the plastic package substrate. Five chips cannot be placed on the same surface. After the results of various researches on processing capabilities and structure simulation, four bare chips are finally placed on the front side of the SiP substrate, the largest chip is placed on the bottom surface of the substrate, and the chips are sunk into the substrate through cavity structure. The cavity design refers to the content later in this section. The layout of the ceramic substrate is shown in Fig. 23.5. Layer stackup design: after finishing the chips layout, The next step is to consider how to design the specific Layer stackup, which layer needs to be designed as signal layer, which layer needs to be designed as power or ground layer, how to split the plane layer, and so on. The ceramic substrate is set to 22 layers, including 12 routing layers and 10 plane layers. In addition to the GND layer, which can occupy multiple
Fig. 23.5 Ceramic package substrate design (front and back)
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Fig. 23.6 Cavity structure of ceramic substrate
plane layers, each power supply net can be allocated to one plane layer, so there is no need to divide the plane layer. Each layer of routing has a completed plane layer reference, which is also conducive to the improvement of signal integrity. Since ceramic substrates generally need to design cavity, that is, several steps are cut on different layers of substrate. The width and depth of the steps need to be designed according to the manufacturer’s process. The chip is placed at the bottom of the cavity, and the bonding fingers are placed on the steps of the cavity. For bare chips with more die pins, multiple rows need to be bonded, and multi-level cavity need to be designed, as shown in Fig. 23.6, which is the cavity structure of the ceramic substrate and chip layout diagram. Routing design: due to process limitations, the current trace width and clearance of ceramic substrates are larger than plastic packaging substrates, usually the minimum trace width is set to 100 µm, and line spacing is also set to 100 µm. Vias are more flexible than plastic packaging substrates, which can be generated layer by layer. The ceramic substrate routing rules are basically the same as those of the plastic substrate, which includes cross routing of adjacent layer, expand power traces, short high-speed sensitive signal traces or increase crosstalk prevention design, routing as few vias as possible, differential signal and equal length routing, consider signal crosstalk when routing, and the key signal routing should be as short as possible. In addition, there is generally no routing on the surface of the ceramic substrates, and all the traces are routed inside inner layer, which is also convenient for subsequent production and processing.
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Fig. 23.7 Design electroplating wires for ceramic substrate
Electroplating wire design: due to the production and process requirements, the design of ceramic substrate needs to add Electroplating wire. The principle of the Electroplating wire design is that add Electroplating lines to nets where all the exposed metal rings, gold fingers, pad pins and other elements that need to be electroplated, and to pass these nets to the outside of the package edge through metal wires. The metal can be connected outside the board outline of the substrate. Refer to Fig. 23.7 for the Electroplating wires of the ceramic substrate.
23.3.4 Product Packaging and Testing The ultimate goal of SiP design is to be a product that can be mass-produced and used in large quantities in actual projects. After the design is completed, how can we ensure that the function of SiP we design is normal and the performance is reliable. First of all, encapsulate the product. The substrate and the chip are assembled together. The packaging processes of plastic SiP and ceramic SiP are almost completely different, and they are generally packaged in different manufacturers. The plastic packaging process generally includes: substrate inspection, chip inspection, chip sticking, bonding, welding, encapsulation, cleaning, ball planting, laser marking, cutting, packaging and other processes. The ceramic sealing process generally includes: substrate inspection, chip inspection, chip sticking, bonding, welding, capping, air tightness inspection, ball planting, laser marking, packaging and other processes.
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After the packaging is completed, product testing is carried out. There are many test contents. First, the test vector needs to be used on test machine to ensure the normal function of the SiP. Then, it is necessary to test whether the various electrical parameters of the SiP are normal in different temperature environments. Afterwards, aging and thermal cycle tests, as well as structural tests such as shock and vibration, are required. It should be noted here that product testing needs to be considered when designing SiP schematics. First, we need to understand which pins of a single chip must be used for vector testing. The tested pins must be led out to the package pins during the schematic design, otherwise some functions cannot be tested during the functional test, which can lead to the correctness of the SiP module function cannot be guaranteed. After the test is completed, the function and performance of SiP products are well in various environments, they can become products and be sold in market. The following figure is a physical sample after the packaging test is completed. Figure 23.8 is plastic package SiP sample, Fig. 23.9 is ceramic package SiP sample.
Fig. 23.8 Plastic package SiP sample
Fig. 23.9 Ceramic package SiP sample
Chapter 24
2.5D TSV Technology and Design Case Jian Xu
24.1 2.5D Integration Requirement In order to meet the needs of consumers for miniaturization, multi-function and high performance of electronic products, and to integrate more functions without changing the package size, 3D packaging technology came into being. 3D packaging technology can stack multiple chips, which is often used in the packaging of memory devices. The bare memory chips are stacked vertically and connected with the substrate by wire bonding. This technology has low cost and mature process. It is widely used when the I/O number is less than 200. At present, it still occupies an important position in packaging products. Flip chip technology can shorten the interconnection distance and improve the packaging density for high-performance devices with a large number of I/O. at this time, the organic substrate becomes the bottleneck of flip chip technology in highdensity packaging. It is difficult to realize high-density packaging on the organic substrate, and the cost increases rapidly, so it is very difficult in product application. Silicon interposer can realize high-density layout and I/O redistribution. Through I/O redistribution, silicon interposer can be assembled on organic substrate with large pitch solder balls. The application of silicon interposer can reduce the process requirements of micro assembly and improve product reliability. The application of silicon interposer can reduce the CTE mismatch between chip and organic substrate, shorten the interconnection length and improve the electrical performance, and the metal filled TSV (through silicon via) can be used as the heat dissipation channel at the same time. Based on the advantages of silicon interposer, this technology has been widely concerned and focused by major companies and scientific research institutions around
J. Xu (B) Wuxi, China e-mail: [email protected] © Publishing House of Electronics Industry 2022 S. Li (ed.), MicroSystem Based on SiP Technology, https://doi.org/10.1007/978-981-19-0083-9_24
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the world. More and more high-end products provide packaging solutions through silicon interposer. This way of integration through silicon interposer is usually called 2.5D integration in the semiconductor industry.
24.2 Comparison of Traditional Packaging with 2.5D 24.2.1 Flip Chip Process The conventional flip chip packaging process includes two steps: flip chip and underfill, in which the appropriate flux is needed to enhance the wettability of solder, and the chip can be temporarily fixed on tape during the transfer process. The basic assembly process includes: wafer flow → bumping → slicing → picking up → chip placement → reflow → filling, etc. According to the chip situation, the detailed implementation process is divided into three types, as shown in Table 24.1. Flip chip technology has different branches to meet different needs. On the basis of traditional flip chip technology, there are conductive polymer technology (FCT), anisotropic conductive technology (FCT), etc. No matter what kind of flip chip package, the semiconductor chip is directly assembled on the package substrate. Due to the limitation of substrate material and process, the pitch of solder balls used in the assembly is generally more than 120 Table 24.1 Three flip chip assembly processes Type
Advantage
Disadvantage
Bump chip
Process flow
The cleaning step can be omitted; It is easy to control the residual flux; There are few voids in the solder joint
Need to bumping on the chip; Bump requires high coplanarity; Warpage issue on substrate
W/O bump chip
W/O Bump; Chips can also be flip; The process is simple;
It is difficult to eliminate the residual stress of flux; The probability of voids is high; The pitch is limited
High melting bump chip
The cleaning step can be omitted; The residual flux is easy to control; There are few voids in the solder joint
Bump requires high coplanarity; Bumps need to be made on the substrate
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µm, which can only meet the application of low number of I/O. Because this kind of package only needs one assembly, and the pitch of solder ball used in assembly is larger, the technical requirements are lower, the price of equipment is lower, and it is easy to obtain higher yield, so the packaging cost is much cheaper than that of silicon interposer packaging.
24.2.2 Wire Bonding Process Wire bonding is the electrical connection between the two ends of the small metal wires and the chip, the substrate or the package pins. There are three processes: thermocompression bonding, ultrasonic bonding and thermocompression ultrasonic bonding. Thermocompression bonding is that the wire deforms when heated at high temperature (>250 °C) under the pressure of hot indenter, and the bonding is carried out by adjusting the time, temperature and pressure; Ultrasonic bonding is unheated (usually at room temperature). At the same time of applying pressure, ultrasonic frequency vibration is generated between the weldments, which destroys the oxide layer on the interface between the weldments and generates heat, so that the two solid metals are firmly bonded; Thermocompression ultrasonic bonding is a combination of the above two forms. On the basis of ultrasonic bonding, the heating table and cleaver are heated at the same time. The heating temperature is lower (about 150 °C), which enhances the atomic diffusion and the force between atoms at the original interface between metals and realizes high-quality bonding. Thermocompression ultrasonic bonding has become the mainstream because it can reduce the heating temperature, improve the bonding strength and improve the reliability of devices. Figure 24.1 below shows the micrograph of wire bonding. Wire bonding technology directly connects die pads to the substrate through wires. Compared with flip chip bonding, it saves solder ball processing steps. However, due to the common chip pins are distributed at the edge of the chip, the number of I/O can be obtained is relatively low. In addition, using wire bonding, the connecting wire between the chip pin and the substrate is several millimeters long. In contrast, flip chip bonding is only tens of microns, so wire bonding will limit the high-frequency application of the chip.
24.2.3 Advantage and Disadvantage of Traditional Package and 2.5D Compared with the traditional flip chip technology, wire bonding technology and 2.5D integration, the requirements for chip pins are much lower. Under the current technical premise, both in cost and reliability, it still occupies a dominant position in
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Fig. 24.1 An example of 3D package using wire bonding technology
packaging products. However, due to the wafer level fabrication process, the wiring density has been greatly improved. Compared with traditional FC BGA, 2.5D system integration can achieve finer line width, higher density and higher system integration package, which can meet the requirements of high performance and miniaturization of products. The traditional FCBGA package can arrange about 85–120 IO per square millimeter area, while the density of high-density 2.5D TSV interposer can reach 330–625 IO per square millimeter area, which can greatly improve the overall package layout density. The 2.5D integration technology based on Si Interposer represents the development trend of packaging technology. Compared with traditional packaging technology, it not only realizes the traditional meaning of packaging, but also adds certain functions. Table 24.2 makes a simple comparison of the three packaging technologies.
24.3 2.5D TSV Interposer Design 24.3.1 2.5D TSV Interposer Package Structure The typical 2.5D TSV packaging structure is shown in Fig. 24.2. Single or multiple functional chips are installed on the front of TSV interposer by micro bump. The TSV
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Table 24.2 Simple comparison of three kinds of package Items
2.5D TSV PKG
Flip chip PKG
Wire bond PKG
I/O density
High
Med
Low
Equipment configuration price
High
Med
Low
Chip signal loss
Low
Med
High
PKG cost
High
Med
Low
Packaging cycle
Longest
Med
Shortest
Technology maturity
Med
High
High
Current market share
Low
Med
High
Development trend
Rapid growth
Steady development
The proportion gradually decreased
Fig. 24.2 Typical 2.5D TSV package structure
interposer is placed on the organic substrate by micro solder ball on the back in the traditional flip chip method. The organic substrate has through holes and multi-layer trace layers, and the back has BGA Solder ball, forming the whole package. Underfill 1 provides protection for micro bumps. The height of filling gap is less than 30 µm, so underfill material with low viscosity is needed. Underfill 2 provides protection for the micro solder ball of the TSV interposer facing the organic substrate, and uses the underfill material used in common flip chip packaging. The core component of 2.5D package is TSV interposer, which forms the interconnection bridge between function chip and organic substrate. It not only solves the problem of mismatch between I/O density of function chip and pad density of organic substrate, but also provides high-density interconnection between function chips. The typical TSV interposer section structure is shown in Fig. 24.3. TSV provides the interconnection channel through the interposer. The front micro bumps are used for function chip bonding. The front RDL (redistribute layers) provides the connection between TSV and front micro bumps, and provides the interconnection between multiple function chips. The backside micro solder ball provides soldering interconnection for organic substrate, the backside RDL provides interconnection between
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Fig. 24.3 Typical 2.5D TSV interposer stackup structure
TSV and backside micro solder ball, and the dielectric layer on the substrate surface of interposer provides isolation between multi-layer RDLs and RDL passivation protection. TSV provides the interconnection channel through the silicon substrate, which needs to be filled with conductive materials first and then insulated from the silicon substrate. In typical cases, the conductive material is copper, which is usually filled by electroplating. The insulating material is silicon oxide. In order to prevent the diffusion of copper materials into the oxide layer, it also includes a diffusion barrier layer between silicon oxide and copper filled material. At present, Ti, Ta metal or nitride are mainly used. The upper and lower surfaces of the interposer are defined as shown in Table 24.3. Table 24.3 2.5D interposer layer definition Layer name
Mask name
Definition
Solder cap1
UBM1
Solder cap on top surface of interposer
u-Bump (UBM1)
UBM1
Micro bumps or UBM 1 layer on the top surface of interposer
Dielectric 3
PI3
Top surface, the 3rd dielectric layer
RDL2
M2
Top surface, the 2nd metal layer
Dielectric 2
PI2
Top surface, the 2rd dielectric layer
RDL1
M1
Top surface, the 1st metal layer
Dielectric 1
PI1
Top surface, the 1st dielectric layer
Barrier layer
NA
Dielectric barrier layer
TSV
TSV
TSV hole
Dielectric 4
PI4
Bottom surface, the 1st dielectric layer
RDL3
M3
Bottom surface, the 1st metal layer
Dielectric 5
PI5
Bottom surface, the 2nd dielectric layer (continued)
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(continued) Layer name
Mask name
Definition
Bump (UBM2)
UBM2
Micro bumps or UBM 2 layer on the bottom surface of interposer
Solder cap 2
UBM2
Solder cap on bottom surface of interposer
It should be pointed out that the M1 layer on the front of interposer is close to the middle substrate, and then the M2 and M3 layers are outward in turn, and so is the back of the interposer. This naming is mainly based on the sequence of wafer processing technology, which is the same as the naming method of each layer of the chip. The layers of organic substrate (PCB) are named from top to bottom, so designers should pay attention to it.
24.3.2 2.5D Interposer Package Design Since most of the processes involved in 2.5D interposer are wafer processes, most of the 2.5D interposer are made by FAB, and its main design idea is based on the PDK module established by FAB. The PKD module must be built before the design, and can only be completed in the designated wafer foundry. The design idea is relatively fixed. For advanced OSAT, some company also could do 2.5D interposer business, such as JCAP, NCAP, etc. The design idea involved in this chapter is based on the advanced packaging level. The 2.5D interposer is regarded as a substrate in the package for design processing, and the design idea is more flexible. Different from traditional package, a large part of the workload of packaging based on 2.5D package is the design of interposer. The whole design includes a series of work, such as scheme design, package design, signal simulation, layout and DRC inspection, post simulation verification and so on. After the design is completed, the designer will design data tape out. Generally, according to the format requirements, there are two data formats: 1.
2.
Gerber file is an exported file for packaging organic substrate design. This file is mainly used for substrate manufacturing and sent to the corresponding substrate manufacturing company. GDS file is the file exported from 2.5D interposer design, which is sent to the corresponding mask company for mask design and manufacturing. After the mask is completed, the interposer is streamed.
After the substrate, 2.5D interposer and chip are all available, the overall packaging and assembly will be carried out. Figure 24.4 shows the flow chart of 2.5D package design and implementation.
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System Design
Package SoluƟon
Interposer Design
Package Placement
Pre-SimulaƟon Layout&DRC Check
Post-SimulaƟon
Interposer SimulaƟon
Mask Demo
Data Tape out
Substrate Gerber File
Interposer GDS file
Substrate Manufacture
Mask Design
Total Assem bly
Mask Manufacture
Interposer Manufacture
Chips
Fig. 24.4 2.5D Package design and assembly flow chart
24.4 Process Comparison of Interposer and Organic Substrates At present, silicon and glass substrates are mainly used in the manufacture of interposer. This section will introduce these two typical materials and processes and compare them with organic substrates.
24.4.1 Si Interposer As the silicon-based process is relatively mature and the required equipment and materials are relatively complete, the silicon interposer is mainly used into package
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Fig. 24.5 Typical Si Interposer Manufacture Process Flow
at present. The typical manufacturing process flow of silicon- interposer is shown in Fig. 24.5: (a) First, deep hole etching is performed to define the position and size of TSV, (b) then the insulating layer and diffusion barrier / seed layer are deposited, (c) then copper plating is performed to complete TSV filling, followed by CMP planarization to remove the excess copper layer on the surface, (d) then the top RDL is processed, (e) and UBM micro pad for chip assembly, (f) and then protected by temporary bonding, (g) Thin the substrate, expose TSV on the back side of the substrate, (h) RDL on the back, (i) Ball plating on the back side, (j) finally de-bonding, and scribe to obtain the required silicon interposer.
24.4.2 Glass Interposer Glass can provide better RF performance, and is a transparent material, which has better performance in some applications. Glass interposer can use a manufacturing process similar to silicon-based interposer, which corresponds to TSV on silicon substrate. The through hole made on glass is usually called TGV (through glass via), but it is much more difficult to etch deep holes on glass than on silicon. For example, dry etching is adopted, and the etching rate on glass is less than 1 µm per minute, The etching rate on silicon can reach more than 10 µm per minute, so it becomes very expensive to process glass interposer by dry etching. Although there are other etching methods, such as laser ablation, sand blasting, mechanical drilling and so on, these methods can only process holes with an aperture of more than 100 µm, which can not meet the requirements of high density.
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Fig. 24.6 Schott glass interposer embedded with W multi-wire
Schott glass company put forward a new processing idea of glass interposer in 2010, as shown in Fig. 24.6 below. The W multi-wire is embedded in the glass to provide a glass interposer with conductive through holes. The specific processing method has not been fully disclosed. The glass interposer with specific conductive through holes can be purchased from Schott Glass Company as required, and then the wiring layer and bonding bumps are processed on both sides to obtain the glass interposer. With this processing method, the minimum diameter of W multi-wire is currently 50 µm.
24.4.3 Organic Substrate Organic substrates generally use mechanical drilling or laser ablation to process through holes in the organic board core, and then process multilayer trace and pads on both sides. The basic process is shown in Fig. 24.7. After drilling, the surface copper skin is removed by corrosion, and then a thin layer of copper is deposited by electroless plating. Then, the trace layer is made by dry film mask electroplating.
Fig. 24.7 Organic substrate process flow
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Finally, the dry film and electroless plating seed layer are removed to complete the substrate processing. At present, the minimum through hole diameter processed by mechanical method is 80 µm, and the minimum through hole processed by laser method can reach 50 µm. In order to improve the routing density, there is still a kind of coreless substrate, which directly uses multi-layer route processing to realize the manufacturing of interposer. Due to the processing accuracy of organic substrate, the minimum pad pitch on the chip side is about 120 µm, and finer pitch will be difficult to assemble, while the corresponding Si interposer can allow the assembly of bumps with a pitch of less than 50 µm.
24.4.4 Process Capability Comparison Because silicon interposer or glass interposer is usually installed on organic substrate. According to the characteristics of the three materials and processes and the maturity of the corresponding equipment, the process processing capabilities of silicon interposer, glass interposer and organic substrate are very different. For intuitive understanding, the three are briefly compared in Table 24.4.
24.5 Mask Porcess Introduction Mask plate, also known as photomask. Quartz or glass is used as the substrate, and a layer of metal chromium + chromium oxide + photosensitive adhesive is plated on it to become photosensitive material. The designed circuit pattern is exposed on the photosensitive adhesive through electron beam or laser equipment. The exposed area will be developed through development, etching and other processes, and finally a pattern is formed on the metal chromium, Become an optical mask product with the Table 24.4 Capability Comparison for three types of substrates
Items
Si interposer
Glass interposer
Organic substrate
Hole diameter
10~30 µm
30~100 µm
50~150 µm
Trace W/S
5 µm/5 µm
10 µm/10 µm
25 µm/25 µm
Pad pitch
30~50 µm
50~100 µm
80~150 µm
Processing difficulty
Low
High
Low
Process maturity
High
Low
High
Cost
Med
High
Low
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Fig. 24.8 Mask stackup diagram
Import LIC file
Litho
Lithography exposure
Semi finished glass
Chemical process
Development Exposure image development (yellow)
Final Glass Mask
Etching Etch Cr Layer yellow
Mask cutting (optional)
Final Glass Mask
Photoresist remove
Cleaning &inspection
Cleaning
Remove Photoresist Remove chemical liquid yellow yellow
Fig. 24.9 Mask manufacture process flow
same design graphics. The main application industries include IC industry (semiconductor), flat panel industry (FPD), circuit board industry (PCB), micro mechanical fluid (MEMS) and other industries. Chromium plate raw material is a chromium film base plate formed by depositing chromium chromium oxide film on a flat and high finish glass base plate by DC magnetron sputtering (SP), and then coating it with a layer of photoresist or electron beam resist making chromium plate raw material. See Fig. 24.8 for the specific structure. The mask of PCB enterprises is generally processed and manufactured by themselves, but the processing of IC mask plate is completed by special company. At present, for high-precision mask plates, only a few companys in the world can make them, and there is a large gap between domestic company and the world. Figure 24.9 is the manufacturing process flow chart of mask.
24.6 2.5D Interposer Design, Simulation and Manfacture Based on the design and related process flow of 2.5D interposer introduced in the previous sections, this section briefly introduces the whole process of silicon-based interposer, including design, simulation, wafer fab, assembly and reliability analysis.
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The project includes four bare chips with different functions and sizes: die1~die4, which are flip chip dies. The number of IO chips is dense, and the system has highfrequency signal requirements. It is necessary to perform impedance matching on the signal network and extract the S parameters of the key signal network. Because there are many system chips and the process is complex, the simulation analysis of process and structure warpage is needed.
24.6.1 Package Structure Design In this project, due to the large number of I/O chips and small I/O bump pitch. The line width and line space of the traditional organic substrate can not meet its requirements. Therefore, the 2.5D interposer is adopted. Four chips are bonded on the interposer for signal interconnection and fan out, and then the whole structure is connected with the organic substrate below to form an overall packaging structure. Figure 24.10 below is the interposer 2.5D packaging structure. It includes the analysis of chip height, layout, spacing, underfill filling, layout, interconnection mode and other aspects. The final packaging form adopts the structure of FBGA (fine pitch ball grid array). Due to the bump pitch of the chip and the reflow temperature gradient of the solder ball, the four chips are designed to be pasted on the 2.5D interposer by TCB (thermo compression bonding), and the silicon interposer is bonding on the packaging substrate by flip chip. Different from the traditional packaging structure, many factors such as process, assembly, signal and structure need to be considered before the design of 2.5D interposer, such as: ➀ does the size of interposer exceed the size of exposure area of lithography machine? Can post assembly be met? Whether the metal plating opening rate meets the requirements, etc.; ➁ Whether bumping process or NiAu or NiPdAu is adopted for the surface treatment of the upper and lower parts of the interposer, which will directly affect the later assembly process; ➂ The height of the bump above and below the interposer is limited. Due to the temporary bonding process used in the manufacture of the interposer, the height of the bump is limited to a certain extent; ➃ Requirements for depth width ratio of TSV hole, trace width and space, dielectric layer coverage, etc.; ➄ Considering the temperature gradient of chip, interposer and packaging solder ball, improper material selection may lead to the problem of secondary reflow of the structure; ➅ For high-frequency signal processing, RDL layer, dielectric layer thickness and impedance matching need to be considered, such as coplanar waveguide structure or reference ground structure; ➆ Structural warpage. If the interposer has a large area, the overall warpage of the package and underfill dispensing under the interposer need to be considered in the design.
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Fig. 24.10 2.5D Si interposer package structure and chip layout
24.6.2 Package Layout, Signal and Structure Simulation 1.
2.5D Si Interposer Stackup Setup and Layout
According to the above overall packaging structure, the number of chip I/O and the pre simulation calculation results of key signal network, the structure of setting 2.5D interposer is shown in Fig. 24.11a. The top of interposer contains two layers of RDL and the bottom contains one layer of RDL. See Fig. 24.11b for the setting of stackup material and thickness; The silicon interposer of the project can be designed using traditional SIP packaging layout design software, such as mentor xpedion layout. Figure 24.12 shows the wiring design diagram of one layer. Unlike the organic substrate process, the uniformity and current density of the later RDL electroplating process need to be considered in interposer design, and the opening rate and uniformity of copper sheet need to be considered in the design.
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(a) interposer structure
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(b) interposer stackup setup
Fig. 24.11 Si interposer structure and stackup setup
Fig. 24.12 2.5D interposer metal layer layout
2.
Organic Substrate Stackup and Layout
Through the signal interconnection and signal fan out of the 2.5D silicon interposer, the layout pressure of the organic substrate is greatly reduced. This design adopts the 6-layer BT substrate. The packaging design idea is basically consistent with the substrate design idea of ordinary FC BGA. The silicon interposer can be regarded as an ordinary flip chip. Figure 24.13 shows the stackup structure design and material list of the substrate. After the layout is completed, the DRC of the system is checked. Different from the traditional packaging design, the 2.5D silicon interposer needs additional inspection,
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Fig. 24.13 Organic substrate stackup and material list
including: ➀ TSV opening rate and density inspection; ➁ Density inspection of RDL layer of interposer. 3.
Key Net Signal Simulation
After the package layout design is completed, the key signals need to be simulated to verify whether the signal integrity can meet the design requirements. Figure 24.14 shows the return loss S11 extraction result of single ended signal, and Fig. 24.15 shows the insertion loss S21 extraction result of single ended signal. The whole structure includes the bump of the chip, the full link structure of silicon interposer and organic substrate. 4.
Structure Simulation
After the package layout design is completed, the whole structure needs to be simulated to verify whether its warpage meets the design requirements. Due to the large size of the interposer and carrying a variety of chips, the influence of warpage needs to be considered in the overall packaging structure. In this project, the simulation of packaging warpage is carried out for different substrate thickness. Figure 24.16 is the cloud diagram of package warpage, and Fig. 24.17 is the
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SYZ Sweep 1 S Plot 3
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Curve Info db(S(BT_TRX_N_DIE1_IPD4,BT_TRX_N_DIE1_IPD4)) SYZ Sw eep 1
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db(S(CLK_32K_IC1_21,CLK_32K_IC1_21)) SYZ Sw eep 1 db(S(DIP_GPS_OUT_BGA_M16,DIP_GPS_OUT_BGA_M16)) SYZ Sw eep 1 db(S(DIP_GPS_OUT_DIE1_IPD1,DIP_GPS_OUT_DIE1_IPD1)) SYZ Sw eep 1 db(S(FM_LANT_IPD_BGA_M5,FM_LANT_IPD_BGA_M5)) SYZ Sw eep 1
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db(S(FM_LANT_IPD_IC1_RF41,FM_LANT_IPD_IC1_RF41)) SYZ Sw eep 1 db(S(FM_SANT_IPD_BGA_L5,FM_SANT_IPD_BGA_L5)) SYZ Sw eep 1 db(S(FM_SANT_IPD_IC1_RF40,FM_SANT_IPD_IC1_RF40)) SYZ Sw eep 1 db(S(GPS_LNA_EN_BGA_J17,GPS_LNA_EN_BGA_J17)) SYZ Sw eep 1
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db(S(GPS_LNA_EN_DIE_5,GPS_LNA_EN_DIE_5)) SYZ Sw eep 1 db(S(GPS_LNA_OUT_BGA_J18,GPS_LNA_OUT_BGA_J18)) SYZ Sw eep 1 db(S(GPS_LNA_OUT_DIE_6,GPS_LNA_OUT_DIE_6)) SYZ Sw eep 1 db(S(GPS_RX_IN_BGA_H15,GPS_RX_IN_BGA_H15)) SYZ Sw eep 1
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Fig. 24.14 Single port signal network return loss S11
SYZ Sweep 1 S Plot 4
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db(S(DIP_GPS_OUT_BGA_M16,DIP_GPS_OUT_DIE1_IPD1)) SYZ Sw eep 1 db(S(FM_LANT_IPD_BGA_M5,FM_LANT_IPD_IC1_RF41)) SYZ Sw eep 1
S Parameter in db
db(S(FM_SANT_IPD_BGA_L5,FM_SANT_IPD_IC1_RF40)) SYZ Sw eep 1
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db(S(GPS_LNA_EN_BGA_J17,GPS_LNA_EN_DIE_5)) SYZ Sw eep 1
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db(S(G_CLK_32K_BGA_F18,G_CLK_32K_IC2_D1_68)) SYZ Sw eep 1
db(S(GPS_LNA_OUT_BGA_J18,GPS_LNA_OUT_DIE_6)) SYZ Sw eep 1 db(S(GPS_RX_IN_BGA_H15,GPS_RX_IN_IC2_D1_16)) SYZ Sw eep 1
db(S(OSC_26M_BGA_B10,OSC_26M_IC1_RF4)) SYZ Sw eep 1 db(S(RF_ISM_N_BGA_H12,RF_ISM_N_IC1_RF19)) SYZ Sw eep 1 db(S(SD_CLK_BGA_A7,SD_CLK_IC1_58)) SYZ Sw eep 1
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db(S(SD_D0_BGA_A4,SD_D0_IC1_49)) SYZ Sw eep 1 db(S(SD_D1_BGA_B4,SD_D1_IC1_48)) SYZ Sw eep 1 db(S(SD_D2_BGA_B3,SD_D2_IC1_47)) SYZ Sw eep 1
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db(S(SD_D3_BGA_B2,SD_D3_IC1_46)) SYZ Sw eep 1 db(S(SPI_CLK_BGA_B16,SPI_CLK_IC2_D1_63)) SYZ Sw eep 1 db(S(U0RXD_BGA_E2,U0RXD_IC1_34)) SYZ Sw eep 1
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Fig. 24.15 Single port signal network insertion loss S21
warpage analysis of different organic substrate thicknesses corresponding to different temperatures.
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Fig. 24.16 Warpage simulation of organic substrate with thickness of 500 µm
Fig. 24.17 Temperature dependence of warpage of organic substrates with different thickness
As can be seen from Fig. 24.17, the change of substrate thickness has a significant impact on the warpage of the package. The area with the largest warpage change is at the edge of the substrate. With the increase of temperature, the warpage will continue to decrease. The substrate with smaller thickness will improve the package warpage at low temperature.
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24.6.3 Production Data Tape Out and Mask Preparation After the packaging design and simulation are completed, the files required for production need to be exported. Due to the different manufacturers of organic substrate and silicon-based interposer, the corresponding output data are also different. The files exported from the organic substrate are Gerber files and drilling data. The export method is the same as that of the traditional packaging substrate, which will not be repeated here. The silicon-based interposer is made by a process similar to wafer. The documents received by the mask making company and the silicon interposer processing enterprise are GDS documents. This section mainly introduces the corresponding GDS file processing and mask preparation. Mainstream packaging layout design software has GDS export command. After setting the corresponding layer name and data type in the software, it can be exported. Here is only the GDS file of a single interposer exported. In actual production, the following editing processing will be performed before manufacturing the mask: (1) (2) (3) (4) (5)
(6)
In order to improve efficiency, within the allowable range of the lithography machine, the composition will be carried out within an exposure field of view; Add scribe line according to actual capacity; Add alignment marks in the blank area to facilitate the alignment of upper and lower layers; Add CD (standard size structure) measurement structure and signal test structure; According to the actual process requirements in the later stage, define the black-and-white effect drawing of the mask plate of the graphics and scribe line; Add the line compensation value according to the process capacity of the production line.
Figure 24.18 shows the black-and-white rendering of the 6-inch mask. The size and format of the mask are also different according to different lithography machines. The mask of the project has two field of image. Each image can be arranged with a graphic, or the composition MPW (multi project wafer) can be adopted.
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Fig. 24.18 Black and white rendering of mask
24.6.4 Interposer Manufacture and Assembly After the mask is prepared, the manufacturing of silicon interposer can be started. See the flow diagram in Fig. 24.5 in Sect. 4 for the specific process. The project is made of 12 inch wafer, the thickness of the final interposer is 200 µm, and the hole diameter of TSV is 30 µm. The final wafer sample of the interposer is shown in Fig. 24.19a, and the section electron microscope of the interposer is shown in Fig. 24.19b.
(a) Sample 12inch
Fig. 24.19 2.5D Interposer sample and SEM
(b) SEM
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Fig. 24.20 2.5D Si interposer assembly process flow
The assembly process is based on the traditional flip chip process. The interposer is first bond on the organic substrate, and then the bare chips are pasted on the interposer in turn. See Fig. 24.20 for the main process flow diagram.
Chapter 25
Digital T/R Module SiP Design Case Mengjian Bao, Pei Li, and Wenbin Lu
25.1 Introduction to Radar System Radar is a kind of radio detection equipment, which can measure the distance, direction, speed and other state parameters of the target by transmitting electromagnetic wave and receiving the echo generated by electromagnetic wave on the object. Radar echo signal contains a lot of information of the object, we can use the corresponding methods to extract the information. 1.
Distance measurement: Because electromagnetic energy propagates in space at the speed of light C, as long as the time interval between transmitting and receiving electromagnetic waves is known, the distance of the target can be measured (Fig. 25.1). 2R = C · t_r
2.
3.
Angle measurement: Because the antenna is directional, we can determine the direction of the target by the difference in the power of the echo caused by the directional (Fig. 25.2). Speed measurement: When there is a relative velocity between the target and radar, the carrier frequency of the received echo signal has a frequency shift relative to the carrier frequency of the transmitted signal, which is known as Doppler frequency shift.
fd =
2vr λ
M. Bao (B) · P. Li · W. Lu Shanghai, China e-mail: [email protected] © Publishing House of Electronics Industry 2022 S. Li (ed.), MicroSystem Based on SiP Technology, https://doi.org/10.1007/978-981-19-0083-9_25
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Fig. 25.1 Schematic diagram of radar ranging
Fig. 25.2 Schematic diagram of radar angle measurement
fd is the Doppler shift, vr is the radial velocity between the target and the radar, λ is the carrier wavelength. According to different parameters, radar can be divided into many different types, such as: (1) (2) (3)
According to the function: can be divided into warning radar, guidance radar, weather radar, etc.; According to the system: can be divided into digital phased array radar, synthetic aperture radar, pulse compression radar, etc.; according to the coordinate parameters of the target: can be divided into altimeter radar, two coordinate radar, three coordinate radar, etc.;
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The beam scanning of the first generation of radar is realized by the mechanical rotation of radar antenna, which is the original mechanical scanning radar. Because the mechanical scanning is not convenient, on this basis, phased array radar came into being. Phased array radar realizes beam synthesis by means of electrical scanning. Phased array radar has the following advantages: (1) (2) (3)
Flexible beam pointing, fast scanning and high data rate; A radar can form multiple independent beams at the same time, and realize the test function of different parameters respectively; The target capacity is large, and multiple targets can be tracked.
Phased array radar can be divided into active phased array radar and passive phased array radar. The antenna of active phased array radar uses a transmitting and receiving device called T/R module, each T/R module can radiate and receive electromagnetic waves, Because the antenna array is composed of a large number of T/R modules, So the failure rate is low, even if several T/R modules are damaged, the whole radar will not be affected (Fig. 25.3). Passive phased array radar is composed of a unified transmitter and receiver, plus phased array antenna with phase control capability. Because there is no independent T/R module in passive phased array radar, the technical difficulty is much less than that of active phased array radar in terms of power, efficiency, beam control and reliability. Fig. 25.3 Schematic diagram of active phased array radar
Array antenna
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25.2 SiP Technology Adoption With the pursuit of smaller size for wireless devices, SiP technology and SoC technology provide new ideas for product miniaturization, and provide a good solution for the actual project. SoC technology is to integrate the IC with different functions into one chip. Through SoC technology, not only the volume can be reduced, but also the distance between different ICs can be reduced, and the computing speed of the chip can be improved. SiP technology is an advanced packaging technology. It is a single standard packaging that integrates multiple active and passive components with different functions side by side or stacked to achieve certain functions, forming a system or subsystem. The main difference between SoC Technology and SiP technology is that the starting point of the solution to miniaturization is different. SoC takes chip design as the starting point and highly integrates components on one chip, while SiP takes package design as the starting point and arranges different chips in a package. Compared with SoC technology, SiP has the characteristics of high flexibility, low cost and short cycle. Moreover, SiP has good support for Heterojunction integration, and is especially suitable for the miniaturization integration of RF and microwave systems. Therefore, this design uses SiP technology as an integration means to realize the design of digital T/R components. The key elements of SiP technology are encapsulation carrier and assembly process. encapsulation carrier includes printed circuit board (PCB), low temperature co fired ceramic (LTCC) and silicon substrate. Assembly process includes wire bonding, flip chip and surface mount technology (SMT). LTCC is the abbreviation of low temperature cofired ceramic technology. It is a kind of multilayer ceramic circuit board technology. Because of its excellent electronic, mechanical and thermal characteristics, LTCC is widely used in aerospace, computer and other fields with high reliability requirements. The principle of LTCC is to make low-temperature sintered ceramic powder into raw ceramic belt with accurate thickness and density, and then use laser drilling, microporous grouting, slurry printing and other precision processing technology to print conductive, insulating or resistive materials on the raw porcelain, and make the required circuit diagram according to the design requirements. For multi-layer LTCC, the size and pattern of each raw ceramic belt can be checked by microscope before stacking, and the error can be corrected in time without re plate making. In this way, the production cycle can be greatly shortened and the cost can be reduced. LTCC also has the function of layer embedding. It can also embed passive components such as resistors, capacitors, filters and couplers into multilayer ceramic substrates, and then stack them together for sintering. This technology has the advantages of miniaturization of circuit volume and convenience of layout design.
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LTCC sintering temperature is about 850–900 degrees, and low resistance materials such as gold, silver or copper can be used as conductors. LTCC has been widely used in microwave RF circuit design because of its good electrical performance. Due to the characteristics and advantages of SiP and LTCC mentioned above, the design adopts SiP technology and takes LTCC as the packaging substrate of SiP.
25.3 Design of Digital T/R Module 25.3.1 Function Introduction of Digital T/R Module The front end of active phased array radar is a micro system array with relatively independent functions composed of T/R module and corresponding RF antenna. Compared with passive phased array radar with only one transmitter and receiver, active phased array radar has great advantages in waveform generation and control, distributed data processing and equipment reliability. T/R module is the most core device in the front end of active phased array radar. It can be divided into analog and digital according to the way of function realization. The analog T/R module is located at the rear end of the antenna of the active phased array radar, and its main function is to amplify, phase shift and attenuate the radar transceiver signal according to the external control signal. The main feature of digital T/R module is to use digital technology to realize the function of transceiver channel. For example, DDS (direct digital synthesizer) is applied to the generation channel of radar signal, In the transmitting channel, the phase shift and amplitude weighting required on the RF are completed on the digital baseband, while in the receiving channel, the digital beamforming technology is generally used to amplify and convert the radar echo signal, and then the signal is weighted on the digital baseband to form the receiving beam. Refer to Fig. 25.4 below. With the introduction of digital technology, T/R module can achieve better performance. Compared with analog T/R module, digital T/R module have great advantages, which are mainly reflected in the following two aspects.
waveform data
control word
echo signal
RF part
Digital part DDS control module Transceiver control Echo preprocess
DDS DDS
I Q
Quadrature modulation
IF BPF
mixer and filter
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to RF part
AD
switch
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Fig. 25.4 Schematic diagram of digital T/R module
IF BPF
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Structural advantages:
• It reduces the requirements of complex feeder system. Because each digital T/R module directly corresponds to a small unit in the antenna array, the structure of the radar system is simplified and the radar tends to be miniaturized. • The phase shifter can be omitted. In the digital T/R module, the phase shift of the transmitted waveform is realized by digital technology, so the phase shifter in the analog T/R module is omitted, which is very helpful to simplify the structure of the radar. 2.
Performance advantages:
• The internal transceiver channel of the device is realized by digital circuit, which improves the accuracy of the system. • At the transmitter, the signal has more advantages in phase continuity and frequency resolution. DDS technology is used to generate the transmitted signal, which has flexible control of frequency, phase and amplitude parameters, and is easy to realize multiple complex radar waves. Because the generation of radar waveform is realized by digital method, a variety of complex radar waveforms with different frequencies can be generated In chronological order. If these radar waveforms are sent to different spatial directions, it can track multiple targets in different directions and improve the anti-jamming ability of the radar. • At the receiver, the processing flow of quadrature demodulation and filtering of signals in the receiving channel is realized by software, which is convenient for structure modification and flexible in design.
25.3.2 Structure and Principle Design of Digital T/R The digital T/R module is divided into transmitting channel and receiving channel according to function, as shown in Fig. 25.5 below. The transmitting channel is used to control the phase of the transmitting beam, phase the baseband waveform generated by the waveform generation module, and form the transmitting RF signal through up conversion and amplification. The Digital T / R Module
Fig. 25.5 Structure diagram of digital T/R module receive1 transmit1 receive2 transmit2 receive3 transmit3 receive4 transmit4
RF front end RF transceiver channel 1 RF transceiver channel 2 RF transceiver channel 3 RF transceiver channel 4
Digital control part
Digital transceiver channel
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receiving channel amplifies, down converts, filters, IF sampling and digital quadrature processing the signal to form a digital received signal. According to the composition, the digital T/R module is divided into RF transceiver channel and digital transceiver channel, the functions of the two parts are as follows: • The RF transceiver channel is mainly used to amplify and transmit the received/transmitted microwave signal, receive/transmit conversion, and cooperate with the array antenna to monitor and calibrate the receiving/transmitting channel, It is composed of driver amplifier, limiter, low noise amplifier, filter, up and down mixer, etc.; • The functions of digital transceiver channel mainly include LO/clock generation, up/down conversion, switching filtering, gain control, etc. it is composed of DDS, A/D, mixer, frequency synthesizer, power module and optical interface. In this project, the product designed using SiP technology is the RF front end of digital TR module. In terms of architecture, the RF transceiver channel adopts the mode of signal down conversion. The specific composition structure is shown in Fig. 25.6. RF transceiver channel is composed of low noise amplifier, power amplifier, switch, frequency converter, filter and other RF components. The function of the receiving channel is to amplify the signal received by the antenna, then down convert it to the IF and send it to the subsequent IF unit for processing. The function of the transmitting channel is to up convert the signal sent by the IF unit to the RF section, and then amplify it and send it to the antenna for transmission.
[limiter]
[LNA]
RF in [switch]
[Transceiver frequency conversion integrated chip]
[filter]
[switch]
IF out IF in
RF out [PA]
[Drive amplifier]
RF channel part
Power control part Fig. 25.6 Structure diagram of RF transceiver channel
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In the receiving channel, the input end is first connected with a limiter, which is used to prevent the external excessive clutter signal from entering the module and burning the rear low-noise amplifier, so as to protect the receiving channel. However, because it is at the front end of the channel, its own noise figure will have a great impact on the noise figure of the whole chain, Therefore, when selecting devices, devices with small insertion loss should be selected as far as possible. A low noise amplifier is connected behind the limiter to amplify the input weakly signal and control the noise coefficient of the whole receiving link at a low level. After the signal is amplified by the low noise amplifier, it is sent to the frequency conversion chip for down conversion processing. Because the frequency conversion chip contains an image suppression mixer and a controllable gain amplifier, there is no need to add an additional image frequency suppression filter before the frequency conversion chip, which can reduce the size of the circuit board. Due to the existence of the controllable gain amplifier, We can adjust the gain of the chain according to the actual situation to meet the requirements of the index. The signal down converted to IF passes through the SAW filter to filter out the clutter outside the band and output it to the IF unit. In the transmitting channel, the IF signal first passes through the SAW to filter out some possible out of band spurious, and then carries out up conversion processing through the frequency conversion chip. The frequency conversion chip contains a variable gain amplifier, which can adjust the gain of the link through the external control signal, The signal from the frequency conversion chip first amplifies the small RF signal to the input power range required by the power amplifier through the primary drive amplifier, and then amplifies the signal to the output power range required by the final power amplifier. The switching between transceiver and transmitter is realized by two SPDT switches. In order to achieve high power supply efficiency, when the module is in the receiving state, the power supply circuit only supplies power to the low-noise amplifier. When the module is in the transmitting state, the power supply circuit supplies power to the driving amplifier and the last stage power amplifier. The function of this part is realized through the power control part. The drain voltage modulation circuit adopts a more mature MOS drive chip to drive PMOS. Because the output power of the last stage power amplifier and drive amplifier of the transmitting channel is relatively large, their power supply voltage is 8 V, while in the receiving channel, the power supply voltage of the low-noise amplifier is 5 V, so two drain stage voltage modulation circuits are used. The schematic diagram of the circuit is shown in Fig. 25.7. In the 8 V drain voltage modulation circuit, the driving chip adopts the reverse driver MIC4429, the strobe pulse TTR2 is at the high level, and the driver chip outputs the low level. At this time, the VGS of the switching MOS chip is - 8 V, the switching MOS chip is on, and the source voltage is 8 V. The power amplifier chip works in the amplified state and the module works in the transmitting state. When the strobe pulse TTR2 is selected as the low level, the switch MOS chip is cut off and the transmitting state of the module is turned off. When TTR2 is suspended, because the pull-down resistor is connected, TTR2 is low level. At this time, the switching MOS chip is cut off and the transmitting of the module is still off.
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Fig. 25.7 Drain voltage modulation circuit
In the 5 V drain voltage modulation circuit, the driving chip adopts the forward driver MIC4420, the strobe pulse TTR1 is at the low level, and the driver chip outputs the low level. At this time, the VGS of the switching MOS is -5 V, the switching MOS is on, and the source level voltage is 5 V. The low noise amplifier chip works in the amplification state, and the module works in the receiving state. When the on pulse TRR1 is selected as the high level, the switch MOS is cut off and the component receiving state is turned off. When TRR1 is suspended, because the pull-up resistor is connected, TRR1 is high level. At this time, the switch MOS is cut off and the module reception is still off.
25.3.3 Digital T/R Module SiP Layout Design The layout design of the project is completed through the mentor SiP software Xpedition layout 301. Since the circuit can be divided into RF channel and power control in function, we will arrange the two parts separately in different areas during layout to avoid possible interference between the two parts of the circuit. The whole module includes 4 transceiver channels. The specific layout of single channel is shown in Fig. 25.8. When designing, we should first consider the location of RF and IF external interfaces. Because this module is a part of digital T/R module, after considering the overall structure, we place RF input and output ports on the left side of the circuit and IF input and output ports on the right side of the circuit. After the position of the external interface is determined, the RF devices can be arranged. In order to maintain the continuity of the signal in the transmission process, the RF transmission line should keep a straight line as far as possible. According to this goal, we have reasonably arranged the devices to make the devices arranged in a straight line as far as possible. In order to reduce the influence of RF signal radiation on other signals on the board, a large number of grounding vias are punched on both sides of the transmission line. Due to the low efficiency of the final power amplifier, a large amount of heat dissipation will be generated during operation. Due to the compact structure of the layout, how to conduct the heat efficiently is a problem that must be considered. In the layout design, the cavity is excavated in the power amplifier area, so that the bottom
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Fig. 25.8 Circuit layout (single channel)
of the power amplifier is directly welded with the metal surface of the structure, so as to achieve the effect of rapid heat dissipation. Considering the large current of the final power amplifier, the current resistance and the resistance effect, the power supply line of the power amplifier should also be set wider. Since there are many control signal lines and power lines in the module, in order to make reasonable wiring, this circuit is designed as an 8-layer substrate. The RF signal travels on the first layer, and the second layer is paved in a large area to isolate the RF wiring layer from other layers to avoid some unnecessary interference. The control signal line and power line run on the inner layer. The 8th layer is ground copper in a large area to connect the ground of the whole board with the outer shell. The SiP layout is designed according to the above description. The layout of each receiving channel is shown in the left of Fig. 25.9. Each module is composed of
Fig. 25.9 SiP layout design (single channel and 4-channels)
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the above four channels. The structure of the whole four receiving and transmitting channels is shown in the right of Fig. 25.9. In the process of layout design, there are many practical processing problems that need to be considered in advance. If you don’t pay attention to it, it will lead to problems such as damage of LTCC substrate during processing or the process can’t be realized. The following are some matters need attention in the process of this design for readers’ reference. (1)
(2)
(3)
(4)
The ground of adjacent layers shall be laid in different grid shapes. During LTCC processing, sintering will lead to thermal expansion. If copper regions of each layer are solid, cracking and concave convex will occur. Therefore, the ground copper of the inner layer is generally set as a hatched structure. In addition, in order to ensure the overall flatness of the board, the hatched structure of adjacent layers should also be different. The dielectric thickness of the plate layer shall be determined according to the actual situation. If the area of LTCC substrate is relatively large, the thickness of the substrate should not be too thin. If it is too thin, it will lead to fracture during welding. Generally, the thickness of single layer of LTCC substrate is 96 μm. in the design of this product, due to the large size of the substrate, Therefore, we chose 192 μm (96 + 96) as the substrate thickness of the single layer. The devices to be welded shall not be arranged together in a large area as far as possible. When designing the LTCC layout, the welding area shall not be arranged too densely as far as possible, because the material used in the welding area is platinum palladium, which has a large sheet resistance. If the area is larger, the stress in the sintering process will increase, making the local flatness of the substrate worse. In the T/R module, the devices in the welding area are mainly the resistor and capacitor of the power supply part, and they should be spread out as far as possible. During device layout, the requirements of mounting process for device layout shall be considered. Most devices in T/R module are connected through bonding wires. In the processing, the diameter of solder ball is between 80 μm and 125 μm, and the corresponding gold wire diameter is 25 μm (the diameter of solder ball is generally 3–5 times the wire diameter). In order to make the solder ball hit the device smoothly, The ball center shall be more than 0.8 mm away from the chip. Therefore, when arranging the devices, pay attention to reasonably arrange the spacing between the devices to avoid the phenomenon that the process cannot be welded on the designed board.
25.4 Metal Shell and Integrated Packaging Design The power consumption of the SiP project is relatively large, the total power is 120 W, and the output power of the T/R module is 40 W. Since the efficiency of the final power amplifier is only 30%, about 80 W power consumption will be dissipated
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Table 25.1 Characteristic parameters of materials used Structure
Material
Parameters Density (g/cm3 )
Thermal conductivity (w/mk)
Coefficient of thermal expansion (ppm/°C)
16.4
200
7.2
Bottom bottom plate
Tungsten copper (W-Cu)
Side frame
Kovar (4J29)
8.2
17
5.8
Upper surface cover plate
Iron nickel alloy (4J42)
8.1
14.5
7
Substrate
LTCC
3.1
3.3
5.8
in the form of heat. Therefore, heat dissipation must be carefully considered when selecting the shell. Based on this starting point, tungsten copper (W-Cu) material is selected for the bottom plate. The thermal conductivity of tungsten copper is 200 w/mk. the heat dissipation performance is better among common materials, but the weight will be heavier. Because the product is used for ground equipment, the weight problem cannot be considered temporarily. Considering the thermal expansion coefficient, Kovar material is selected for the side frame. Its thermal expansion coefficient and the thermal expansion coefficient of LTCC substrate are both 5.8 ppm/°C, so it will not cause extrusion fracture during welding. Due to the large heat dissipation of the power amplifier, in the design, we choose to excavate the position of the power amplifier, set a metal boss on the shell, and then place the power amplifier directly on the metal boss, which is conducive to high-power heat dissipation (Table 25.1). In the design of this product, the external interface is realized through the guide pin of the side frame. There are three types of external interfaces: RF interface, low-frequency interface and high current interface. Due to different functions, the diameter and spacing of these three types of external interface are different. • Diameter of low frequency guide pin is 0.45 mm, Diameter of glass around the guide pin during fusion sealing with the diaphragm is 1 mm. • Diameter of RF guide pin is 0.3 mm, Diameter of RF solder groove around the guide pin is 0.75 mm. • The guide pin of high current should be slightly thicker, The maximum current of the guide pin with diameter Ø = 1 mm can reach 5A, The maximum current of the guide pin with diameter Ø = 1.5 mm can reach 10A, Considering that the final power amplifier needs to consume large current, we chose the guide pin with diameter Ø = 1.5 mm. The spacing between the guide pins should also be considered in advance when designing the board. According to the requirements of the processing technology, the spacing between the low-frequency guide pin and the low-frequency guide pin
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Fig. 25.10 Schematic diagram of guide pin of the side frame
should be greater than or equal to 1.4 mm, the space between the RF guide pin and the low-frequency guide pin should be greater than or equal to 2.5 mm, and the space between the RF guide pin and the RF guide pine should be greater than or equal to 3.2 mm. See Fig. 25.10. After the shell is processed, the substrate and the shell need to be integrated and packaged, and the connection between the substrate and the shell is completed by welding. The bottom of the final power amplifier needs to be directly connected with the shell. Generally, there are two methods for such connection: Tin welding and conductive adhesive bonding. If the chip adopts conductive adhesive bonding, the protrusion on the shell can be realized with gold. In this way, the bottom of the cavity is easy to be flat. If the chip is welded with tin, the material needs to be the same platinum palladium material as the top welding area. The sheet resistance of the material itself is large, and the larger the area, the greater the stress during sintering, which will make the local flatness of the board worse. Therefore, conductive adhesive connection is adopted in this design. After the device mounting and shell processing are completed, the devices shall be bonded together through gold wire. There are two ways of gold wire bonding: spherical welding and wedge welding. The path of RF signal generally adopts spherical welding, and the bonded gold wire shall be as short as possible. During layout design, attention should be paid to the space between spherical welding devices, because the diameter of the solder ball is generally between 80 μm and 125 μm, and the center of the ball is more than 0.8 mm away from the chip, it is necessary to reasonably design the layout according to these process requirements. Other parts such as control, power supply and grounding use wedge welding. In case of high current, considering the capacity of the overrcurrent of a single gold wire, you can choose more gold wires or choose aluminum wire bonding. After the integrated packaging and shell cover packaging are completed, the process of vacuum baking to remove hydrogen is also required. Because in some products, GaAs devices are found to have hydrogen poisoning (the hydrogen is disabling the chip). Most of the chips used in our products are GaAs devices. In
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Fig. 25.11 Physical drawing of digital T/R module
order to avoid the risk of such products, we carried out the process of removing hydrogen. The overall dimension of the T/R module is 91.9 mm × 43.8 mm, and the weight is about 500 g. The physical drawing of digital T/R module is shown in Fig. 25.11 above.
Chapter 26
MEMS Verification SiP Design Case Boyuan Zhou
26.1 Project Introduction A MEMS (MicroElectro-Mechanical System), is a millimeter-to micron sized system. MEMS could be a micro-device or a system which is integrated of microsensors, microactuators, micromechanical structures, signal processing circuits etc., MEMS is developed based on semiconductor manufacturing technology. Common MEMS products include microphones, micromotors, micropumps, microoscillators, resonators and inertia sensors, such as gyroscopes, accelerometers, etc., as well as products with them integrated in all-together. MEMS sensor is an independent self-controlled system whose internal forcevoltage transfer structure is generally been made in a scale of micron or even nanometer, with Bosch process (Silicon Deep RIE). In recent years, due to MEMS sensors’ advantages of low power consumption, low cost, small volume, and lightweight, they have been applicated throughout industrial production, scientific research, aerospace, robot and so on. With the increasing precision of MEMS gyro, getting close to fiber gyro, more and more applications appeared in aircraft and UAV fields. IMU (Inertial Measurement Unit) is a device to measure the triaxial angular velocity and acceleration of a platform. An IMU usually contains three uni-axial gyroscopes and three uni-axial accelerometers to measure the angular velocity and acceleration, and figure out the posture and position of the platform through matrix computation. The MEMS chip used in this project is fully customed sensor structure and controller ASIC, there is no proper package available. In order to shorten the development cycle, the preliminary test verification and function testing are conducted B. Zhou (B) Xi’an, China e-mail: [email protected] © Publishing House of Electronics Industry 2022 S. Li (ed.), MicroSystem Based on SiP Technology, https://doi.org/10.1007/978-981-19-0083-9_26
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through organic substrate integrated SiP, which cost less money and time consumption than using ceramic package.
26.2 SiP Scheme Design The original board-level system scheme of this project consists of gyroscope, accelerometer and CPU (MCU3). Inside the gyroscope there are force-voltage transfer structure (manufactured by the Bosch process), ASIC 1 (CV transferring and close-loop controlling) with an AD converter built in, and a MCU for initializing and data transportation. And inside the accelerometer there are also a force-voltage transferrer designed with a different structure, ASIC 2 (CV transferring and openloop controlling), and a MCU for initializing, so the accelerometer output is from ASIC 2, which is an analog signal. The analog output of the accelerometer need to be processed in an AD converter first, then be transported to MCU3, and packed with the Gyroscope output, finally transport outside. The MCU2 was used only for the accelerometer initializing. The MCU3 is used for angular velocity and acceleration data frames grouping and upper communication, as shown in Fig. 26.1. By analyzing the system, the MCU1 was found having enough vacant space to write the upper communication program and the accelerometer initializing data, so we simplifying the original system by remove the AD converter, the MCU2 and MCU3, and changed the system as Fig. 26.2 shown.
Fig. 26.1 Original board-level system scheme
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Fig. 26.2 Simplified system scheme
26.3 SiP Circuit Design This project was designed with the Mentor SiP design tool Xpedition. The process is similar on other tool platforms. Mentor Xpedition can precisely modeling the bond wire and planning the complex cavities need to contain the dies, Meanwhile, we can easily review the whole design with a 3D vision through the Xpedition 3D viewer, which is conducive to find problems and increase design efficiency. SiP designing includes stages as follow, component library building, schematic designing, SiP layout plowing, and manufacture document exporting etc. We take this project as a briefly presentation, to introduce main procedures.
26.3.1 Library Build and Schematic Design First, we start the project with creating all the symbols and cells-so called packages or footprints in other platforms. Then we draw the schematic using the symbols we made, just the same as doing a normal PCB project. 1.
Library Building
The Library Manager links Cells built using Cell Editor and Symbols built using Symbol Editor, and combines both into a Part, For a die part, the symbol used in schematic is the same as an ordinary component, but the cell is built with die pads, which has a unique property, that these pads will not exist on the substrate or board actually. A thinned wafer is commonly 200 µm to 400 µm thick, and then be sliced into dies. Since two of the dies be used in this project are vacuum wafer level packaged MEMS sensor, they are with an abnormal thickness (800 µm) both. The two controller ASIC is with a common thickness of 300 µm.
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Fig. 26.3 Symbols and cells built in library manager
The SiP schematic design could get started after finishing the library preparation. The figure presents the symbols and cells of the four chips that been established in this project (Fig. 26.3). 2.
Schematic Design
The design of SiP project was detailed in the schematic according to the plan, which has been verified with a PCB board before the SiP design started. By alternating the device symbols and cells from packaged into bare die, update the new connections, the SiP schematic is ready to export a new net list for the SiP substrate layout plowing. Making sure each connection inside correctly is the most basic, moreover, reasonably pin- mapping as an isolate package, is a key of make the package convenient to use. In this case, we divided the pins into two part, one part on the south edge for SPI pins output and power pins, and the others on the east and west edge for system testing so that the package is capable to be soldered by only the south side, and make it possible to integrate 3 direction inertial sensors on one board without a shell. In the project the package is designed with 36 pins total, and 9 pins each side. We can update the changes from schematic to layout through Forward Annotation in Xpedition Designer, or from layout to schematic through Back Annotation in Xpedition layout. With this method it’s convenient to improve the pin mapping during the project processing. Figure 26.4 presents the schematic of the model project.
26.3.2 SiP Layout Design The project is completely in accord with the microcrystalline alumina ceramic designing rule (Kyocrea CC100), for validate the design with a low cost plan.
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Fig. 26.4 SiP project schematic
1.
Cavity Design
For the different way between the bare die bonding and the SMD devices assembly, the SiP was designed with cavities on it’s both sides. The height of bonding finger stair and each cavity must follow the wire-bonding process capability. The size of cavity is following an expanded outline (+500 µm each side) of the relevant die. In hope of reducing the vertical drop from die pad to the bonding finger, we set a 1000 µm-deep cavity in the up-side cavity to sink the MEMS die in, and moderate the vertical distance between the MEMS structure chip and the bonding finger. As presented in Fig. 26.5. The accelerometer ASIC is placed beside the gyroscope ASIC for shorten the distance from analog output to the AD input which is inside the gyroscope ASIC.
Fig. 26.5 SiP substrate cavity design
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Fig. 26.6 SiP component placement (both side)
MCU with other discrete devices are set on the down-side. The bottom side devices were assembled by reflow soldering, the bottom side cavity could be covered with epoxy if necessary. The component placement is presented in Fig. 26.6. Each die bonding area should be clearly marked. For the ASIC, two “L” shaped metal mark were located at diagonal of bonding area. The MEMS chip were stick on the bottom of the upper cavity area, so no optical alignment mark is needed. According to the MEMS electrical rule the metalized area of the MEMS bonding area was removed. ASIC bonding area and the optical alignment marks were shown in Fig. 26.7. The thickness of every dielectric layer need to be adapted according to the height of each chip. The first stair of the top side cavity was a 1250 µm-deep cavity, which was containable for both the 400 µm-heaght ASIC and the arch rise of the bond wire, the second stair was 1000 µm-deep to be able to fill-in a 1200 µm height MEMS chips. The devices in the bottom side cavity were no higher than 1000 mm, so the cavity was of 1500 µm depth. Substrate stackup and the thickness of each layer setting was shown in Fig. 26.8.
Fig. 26.7 ASIC bonding area and the optical alignment marks
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Fig. 26.8 Substrate stackup setting
2.
Bond Wire Design
In Xpedition, the bond wires are defined following the 5 points modeling as JEDEC JESD59-1997 Bond wire modeling standard described. By reduced the vertical drop with sinking the MEMS chip into cavity, the normal bond wire model and the anchor point setting is good enough to satisfy the design accuracy. For this project, we only need to adjust the spacing between bond wires, and set them to die-to-die mode (Fig. 26.9). After finishing the component placement, and wire bonding, we can review the whole design with the built-in 3D-Viewer. The SiP 3D Image as shown in Fig. 26.10. 3.
Seal Ring Design
In order to seal the upper cavity with a kover lid, we put a rectangle metalized area as seal ring on the top layer, the seal ring width is 1.8 mm, in this way it is more close to the ceramic shell designing. The seal ring was shown in Fig. 26.11. Since the solder temperature is much higher than the adhesive curing temperature, the component in the down side cavity should be soldered first. And we plan to process parallel seam welding to seal the upper cavity, because of the parallel seam welding only emerge high heat in seal ring area, which does less effect on solder. Finally, fill the down side cavity with epoxy, or just leave it be is OK. Figure 26.12 present the images of before and after upper side sealed. 4.
Half-Cut via and Back Drill
The aim package type of the SiP is LCC36, the pins were designed as half cut vias. As the Xpedition doesn’t have any half-cut via design kit, we need to design this type of via beyond the constrain rules as follow steps. Firstly, extend board outline
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Fig. 26.9 Bond wire modeling
Fig. 26.10 Upper-side 3D Image after wire bonding
wider to contain the original outline and all the pins. Then place ordinary vias along the ‘true board outline’, and connect each via to a conductive shape of same net, and cover the whole via and conductive shape with soldermask to finish the Pin building. Finally, shrink the board outline back to its original position.
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Fig. 26.11 Seal ring on top layer
Fig. 26.12 3D image of upper side seal
Avoiding the seal ring on top layer shorted with Pins, process back drill of 1 mm from top layer on each Pin via, remove the upper half of via plating, the process need to be specifically explained to the substrate manufacturer (Fig. 26.13). 5.
Hint to Design Beyond Constrain Rules
The Mentor Graphic Xpedition is a strict tool under the Constrain rules’ supervise. When the Online DRC is active, operations against the rules were forbidden. Route Outline mostly pulled back around 0.3~0.5 mm from Board Outline, this rule benefits the SI and PI of the board. So most of the plowing operations must be done inside the Router Outline. As mentioned above in Half-cut via, before replace the outlines as a last step of all the designing process, better run DRC to confirm the design completed correctly.
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Fig. 26.13 Conductive shape and via as LCC pin
After replace the two outlines back, the DRC will generate Error marks, check every log in case of some Errors, which are not relevant to the outline element, were missing correction. If it’s needed to keep the seal ring over the LCC pins complete, the via of the pins should be buried via. Considering the feature of this project, in hope of reducing the time of laminating, back drill is also an acceptable option. The final product is shown in Fig. 26.14.
Fig. 26.14 Detail of buried via 3D image and photo of final product
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Fig. 26.15 Module substrate (both sides)
26.4 Assembly and Testing Board As it has been planned while the schematic designing, pins were divided into two groups, one group for testing and the other group for application, it’s easy to assemble three modules through orthogonal welding. To improve the solderability of the pins, the half-cut via were of a quite wide diameter, which is about 0.8 mm wide. The back drill process is not needed in ceramic shell manufacturing process, to avoid the short circuit accident. Between the seal ring and pins. The SiP MEMS module is 1yuan coin sized and has a thickness of 4.5 mm, picture of the module was shown in Fig. 26.15. The components in down cavity may be welded with reflow soldering or spliced with conductive epoxy. After the down side assembly, finish the upper side with normal IC bonding process. Since the module is not a standard sized package, testing with a custom socket is costly, so the module testing was conducted by solder the module directly onto a testing board, as shown in Fig. 26.16. In order to conveniently probe the internal pads that was not connected to the pins, the cap was not sealed, and covered with a removable plastic panel instead during testing. Mostly, MEMS sensor is stress sensitive, so the force-voltage transfer structure chip should be assembled carefully, silicon based adhesive is strongly recommended, for its flexibility, reliability and low cost. In this Project a custom-made silicon based adhesive was used. After the module has being tested for a week, the ASIC and MCU ran well. Though the MEMS chips were sealed hermetically, the package itself is not, so the long term hermeticity is still under observing. The formal product will be much better in hermeticity with a ceramic shell.
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Chapter 27
Rigid-Flex SiP Design Case Liqiang Cao, Peng Wu, Fengman Liu, and Huimin He
27.1 Introduction of Rigid-Flex Substrate Substrate technology can be divided into three categories as rigid substrate, flex substrate and rigid-flex substrate according to the folding characteristic. The rigid substrate has high wiring density, high component placement density and high reliability of solder interconnection between the chip and the substrate. However, flexible substrate has high assembly flexibility. The rigid-flex substrate inherits the advantages of the organic substrate and provides the flexibility of forming special structures. Rigid-flex substrate technology is a small form factor rigid-flex printed-circuitboard (PCB). Compared with the other kinds of materials normally used in the package design, such as low temperature co-fired ceramic (LTCC), aluminum, silicon, organic, the rigid-flex substrate offers a combination of features of good electrical performances, high density interconnection, light weight, mass production capability, high reliability and flexibility of forming 3D stacked structures. Many applications, such as the opto-electrical link, antennas, micro-ball endoscopes, have been developed based on the rigid-flex substrate. But the implementation of the rigid-flex substrate is not easy. On one hand, since some applications are very cost-sensitive, appropriate flexible materials should be selected to balance the cost and electrical performances. The cost of the rigid-flex substrate is normally higher than that of the traditional organic substrate. As to microwave applications with requirements of low insertion loss, the costly liquid crystal polymer (LCP) is usually utilized. On the other hand, thermal management is a difficult problem due to poor thermal conductivities of the organic substrate. Thus, some special designs should be conducted to the substrate and the package structure so as to address these problems. L. Cao · P. Wu (B) · F. Liu · H. He Beijing, China e-mail: [email protected] © Publishing House of Electronics Industry 2022 S. Li (ed.), MicroSystem Based on SiP Technology, https://doi.org/10.1007/978-981-19-0083-9_27
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Fig. 27.1 Integration process from 2-D RF system to 3-D Rigid-flex RF SiP
As is depicted in Fig. 27.1, the package based on rigid-flex substrate can be folded and stacked in the vertical direction, so as to furtherly improve the integration degree. This chapter presents a demonstration of integrating RF front-end module of a micro base station into a compact RF system-in-package (SiP) based on rigid-flex substrate, which is utilized to enable three-dimensional (3D) stacking of active RF chips.
27.2 RF Front-End Architecture and RF SiP Scheme A 3D stacked RF SiP based on the rigid-flex substrate is proposed in this section, which provides an integration solution to the RF front-end part in a micro base station system. Firstly, from a system point of view, the system architecture and power dissipation characteristics are demonstrated (Sect. 27.2.1). Secondly, two stacked SiP package structures are introduced (Sec. 27.2.2). Last but not least, the stack-up design of the RF SiP rigid-flex substrate is demonstrated focusing on the electrical performances such as signal integrity and power integrity (Sect. 27.2.3).
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27.2.1 System Architecture of Micro Base Station RF Front-End As to wireless systems with high power consumption, it is not appropriate to integrate the RF system into a small package, for example, a macro base station covering several kilometers of communication territory with hundreds of watts power consumption. But a micro base station is an exception, which is aimed at covering multicasting of critical messages to mobile users even under communication network failure events. The key feature of a micro base station is small enough to be carried around. Thus, the system is much simple with less power consumption compared to a macro base station. These features make RF SiP integration essential and possible. The RF front-end part of a micro base station is a transceiver system including three different links with zero intermediate frequency architectures, the receiver link (RX), the transmitter link (TX) and the feedback link (FB). The system architecture is fundamental to the design of a RF front-end system, which is demonstrated in details in Fig. 27.2. In the RX link, The RF signal received from the antenna side is amplified with two low noise amplifiers (LNA) and a digital signal amplifier (DSA), then the amplified signal is down converted with a demodulator (DEMOD). The low frequency signal is then amplified with the driver chip (DRV) and selected with a passive low pass filter before it is compatible with the analog–digital converter (ADC). At last the base band signal is transmitted to the digital signal processing module such as a field programmable gate array (FPGA). In the TX link, the base band signal is synthesized in the processing module and transmitted to the digital-analog converter (DAC), and then the signal is filtered and up converted to the RF band. The amplified RF signal is output to the external power amplifier (PA) and transmitted to the antenna. In order to calibrate the DC offset and control the gain of the TX link, a feedback link is implemented, in which the received RF signal can be the output signal from the TX
Fig. 27.2 System architecture of micro base station RF front-end
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link, or from the external RF signal from the antenna. The FB link has the same architecture with the RX link, and shares the same local oscillator (LO) source with the TX link. This zero-intermediate frequency architecture is more suitable for system integration than the super heterodyne transceiver because of cancelling the mediate frequency filters. As it is outlined in the solid box (Fig. 27.2), except the processing and antenna module, the whole front-end system comprising of RF and digital parts is integrated in the RF SiP. The power dissipation characteristic is another important factor of the RF frontend system that needs to be considered. This RF system, consisting of RF, digital and power supply components, is divided into four parts. As it is listed in Table 27.1, the four parts of the system have different numbers of chips and various power consumptions. The total power consumption adds up to 20.1 W with 33 pieces of active chips. Since electrical performances of the RF chips are quite sensitive to the variations of junction temperatures, the thermal management of the system must be well concerned while performing RF SiP integration.
27.2.2 RF SiP Package Design Considering the system architecture with RF and digital parts, a stacked systemin-package structure is proposed to integrate the whole RF front-end into a small package, which is depicted in Fig. 27.3 based on a rigid-flex substrate. The planar substrate is bended and transformed to a 3D stacked structure. This RF SiP integrates 33 active chips and more than 600 passive components. The designed package measures 5 cm × 5.25 cm × 0.8 cm, the occupied area of which is almost 95% reduced compared to that of the prototype board mentioned in another article. Compared to the package-on-package (PoP) structure proposed in that article, the rigid-flex substrate provides higher density and more reliable interconnections between two rigid substrates. Moreover, the easy manufacturing and assembly process revealed in the next sections will prove this to be a promising solution of the future RF SiP. Even the package structure and the rigid-flex substrate are simple and mature, some additional features are designed to handle the thermal management problems and to improve electrical performances. From the thermal management aspect, both the structure and the organic substrate are considered. In order to improve the thermal conductivity of the organic substrate, thermal ground vias are designed at the positions of the active chips (Fig. 27.3). Also, the aluminum shield cap originally designed for the electro-magnetic interference (EMI) elimination is connected to the ground plane. Thus, the heat dissipated by the active chips is transported to the metal cap and can be removed by natural convection or forced air cooling methods. The RF SiP based on rigid-flex substrate includes two structure scenarios: face-toface and back-to-face structures (Fig. 27.3). Two package structures are formed with different placement of RF and power management unit (PMU) chips on the rigidflex substrate. As to the Structure 1 depicted in Fig. 27.3a, top side rigid substrate is
TX (~3.3 W/5pcs)
1080 747 1722.6 870 1765 1150 1761.6
8 × 8 × 1.35
8 × 8 × 0.85
8 × 8 × 0.85
10 × 10 × 0.85
7 × 7 × 0.9
5 × 5 × 0.85
6 × 6 × 0.85
RX_ADC
FB_ADC
TX_DAC
CLK
MOD
DSA
LO
Digital (~6.9 W/13pcs)
Power/mW
Size/mm
Symbol
Part
Table 27.1 Power consumptions and sizes of main active chips
FB (~3.8 W/6pcs)
RX (~6.1 W/9pcs)
Part
DRV
DEMOD
LO
DRV
DEMOD
DSA
LNA
Symbol
4 × 4 × 0.85
4 × 4 × 0.85
6 × 6 × 0.85
4 × 4 × 0.85
4 × 4 × 0.85
5 × 5 × 0.85
3 × 3 × 0.85
Size/mm
210
1250
1761.6
210
1250
1150
600
Power/mW
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Fig. 27.3 Two package structure scenarios
attached to the surface of down side aluminum shield cap. The length of connecting flex substrate can be reduced because the distance between two rigid substrates is smaller compare to the Structure 2, which is depicted in Fig. 27.3b. The other part of these two structures are similar except the connection substrate length. The differences of two structures consequence to different features, thus different application scenarios are suited. RF SiP of structure 1 is suitable for cost-sensitive, high electrical performance and minimized area scenarios. Firstly, compared with structure 2, shorter connection substrate of structure 1 leads to lower insertion loss while high speed or high frequency signals are transported through the connection area. Secondly, short connection substrate means smaller extra area are occupied to interconnecting two rigid substrates. Lastly, minimized area means more rigid-flex substrates can be manufactured and low cost of each substrate. RF SiP of structure 2 is suitable for high reliable, high thermal requirement scenarios. On one hand, compared with structure 1, longer connection substrate of structure 2 leads to more reliable mechanical performance because of larger bending radius. On the other hand, structure 2 has better thermal management performance
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if high power chips are placed on the top side rigid substrate. Detailed simulation results are demonstrated in Sect. 27.4.1. In the following sections, structure 1 is analyzed as to the electrical design and simulation (Sect. 27.3) and the assembly flow (Sect. 27.5) while structure 2 is analyzed as to the thermal management design and simulation (Sect. 27.4).
27.2.3 RF SiP Substrate Stack-Up Design The RF SiP integrating a RF front-end module into a compact package based on rigidflex substrate, which is utilized to enable three-dimensional (3D) stacking of active RF chips. Figure 27.4 presents the stack-up of the rigid-flex substrate containing two 8-layer rigid substrates and a 4-layer flexible substrate. The manufacturing process of this kind of rigid-flex substrate is simple and mature, which makes it much cheaper than the same size LCP substrate. Two polyimide cores are stacked and attached by using some polyimide (PI) films and adhesives. The surface polyimide and adhesive layer is etched outside the flexible area. Then the substrate is sandwiched between two dielectric cores with the prepreg used as the filling material. This mature process has undergone many reliability tests. From the electrical performance aspect, in order to ensure the performance of highdensity interconnections on the rigid-flex substrate, a proper layer stack-up design and reasonable functionality assignment of each layer are two effective methods (Fig. 27.4). Since key RF and clock signals are routed on the top and third layer, a kind of core and prepreg material with low dissipation factor (Df) and complete ground planes (layer 2 and layer 4) as the return paths of RF and clock signals are implemented to ensure the signal integrity (SI) of the transmission lines. Other digital and control signals are designed on sixth and seventh layer because of lower signal integrity requirements. In addition, power planes are mainly designed on the fifth layer while others are full ground planes. These power and ground planes are composed to form the power distribution network for the RF SiP. Solder pads are designed on the eighth layer so
Fig. 27.4 Stack-up of the rigid-flex substrate and dielectric constant of each layer
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as to form the Ball grid array (BGA), which is used to connecting the RF SiP and the motherboard. As to the RF SiP with structure 1 and structure 2, the stack-up design and functionality assignment of each layer are generally the same. Only structure 2 has a longer flexible substrate and has RF chips surface-mounted on the same side on two rigid substrates. If the insertion loss is adequate for the RF system, low Dk and Df dielectric material can also be substituted with normal FR-4 material to reduce cost of the rigid-flex substrate.
27.3 Electrical Simulation of the Rigid-Flex Substrate In the design process of the rigid-flex substrate, electrical interconnection is critical essential to the functionality of the RF SiP. Electrical characterization of the rigidflex substrate mainly focuses on the signal integrity of the transmission lines and power integrity of the power distribution network. The first part (Sect. 27.3.1) emphasizes on the signal integrity of RF signals or high-speed digital signals covering rigid and flexible areas of the substrate. They are quite sensitive to the impedance mismatch problems and should be routed carefully and simulated after the design. The post-design simulation results of which will be demonstrated. As to the other RF signals or high-speed digital signals totally routed on the rigid substrate, carefully design following the signal integrity thumb rules is able to reduce risk and ensure the electrical performances. The second part (Sect. 27.3.2) emphasizes on the power integrity of different power distribution networks (PDN) such as DC voltage drop (VD) and current density (CD) distribution characteristics. These two parameters are restricted by the area of the package substrate, thus need to be simulated to ensure power performances.
27.3.1 Design and Simulation of Signal Transmission Since the interconnection of the transmission lines is complex, each individual layer is assigned with a specific function and full ground planes are implemented as the return paths of high speed or high frequency signals. The routing traces of the rigid-flex substrate are all depicted in Fig. 27.5 in details. Among all the transmission lines, some of them are RF or high-speed digital signals covering rigid and flexible areas of the substrate. They are quite sensitive to the impedance mismatch problems and should be routed carefully and simulated after the design. The RF signals and differential clock signals are arranged in Layer 1 and Layer 3 with complete copper layers (Layer 2 and Layer 4) as the return paths of signals, the post-design simulation results of which will be demonstrated in this section. As to the other RF signals or high-speed digital signals totally routed on the
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Fig. 27.5 Routing layers of the rigid-flex substrate and functionality of each layer
rigid substrate, carefully design following the signal integrity thumb rules is able to reduce risk and ensure the electrical performances. The frequency band of this RF SiP is between 700 and 2600 MHz, at which the RF signals have a wavelength of only several centimeters. Since the scale of wavelength is approaching the length of the transmission lines, small impedance mismatch or any discontinuous structures will cause signal integrity problems. The critical RF signals mainly include RX_IN, FB_IN, and TX_OUT (Fig. 27.6). The transmission paths of these signals have discontinuous structures such as solder balls, vias and copper traces. If the same line width is applied to the RF signals in the rigid-flexible transition area, different impedances may exist because of strip transmission line in the rigid substrate while microstrip line in the flexible substrate. Thus, impedances of traces are matched by assigning different widths. Seeing from the simulation models demonstrated in Fig. 27.6, the line width of the microstrip in the flexible area is much larger than that of the strip line in the rigid area. By using an electromagnetic software based on the finite-element-method (FEM), the electrical performances are characterized (Fig. 27.7). The insertion loss of the RX_IN is less than 0.12 dB, which indicates acceptable signal attenuation between the solder balls and the first stage low noise amplifier. Also, due to the longer transmission lines, the attenuation of the TX_OUT and FB_IN is larger than the RX_IN, and reach 0.33 dB and 0.38 dB respectively. The return loss of the RF signals is better than −25 dB. All these characteristics meet the system requirements (S21 < −0.5 dB, S11 > −15 dB).
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Fig. 27.6 Simulation models of the RF signal transmission line on substrate
Fig. 27.7 S parameters of RF signals on substrate
As it is known to all, the clock signal is critical important to the electrical performances of RF systems. However, the digital part and RF part are placed on two different rigid substrates. The clock signal of 122.88 MHz square wave is generated by the clock chip on the bottom substrate and transmitted to the local oscillator chip on the top substrate. Thus, the signal integrity of the clock signals should be evaluated in the frequency and time domain. Used in the different links of the RF SiP, the key digital clock signals include RX_LO, FB_LO and TX_LO. The schematic and layout of the differential clock signal pairs in the RF SiP are revealed in Fig. 27.8a and b respectively. The simulation in the frequency domain is performed with HFSS, a 3D electromagnetic field solver software. The model is demonstrated in Fig. 27.8c. The transient simulation in the time domain is done by using a circuit simulator,
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Fig. 27.8 Simulation models of digital clock signal transmission line on substrate
which has a schematic comprising of ibis models, the S parameter model and circuit elements (Fig. 27.8d). S parameters extracted from HFSS are demonstrated in Fig. 27.9. The insertion loss (S21) and return loss (S11) of the clock signals are displayed. Generally, the attenuation is relevant to the length of the transmission lines. Thus, the long FB_LO signal has the maximum attenuation which reaches 0.71 dB at 3 GHz. The return loss of these clock signals is less than −15 dB, which is acceptable to this RF SiP. To furtherly evaluate the quality of the clock signal, transient simulation is performed and revealed in Fig. 27.10. The eye diagram is displayed with a standard eye mask for low voltage differential signals (LVDS). From the eye diagram (Fig. 27.10a), the longer transmission line results in much larger ripples to the clock signal. But the maximum ripple is acceptable since the clock signals meet the eye
Fig. 27.9 S parameters of digital clock signals on substrate
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Fig. 27.10 Transient simulation results of digital clock signals on substrate
mask requirements. From the time domain wave signals (Fig. 27.10b), the longer transmission line results in larger delay of several hundred of pico-seconds. This time delay is small enough and will not result in synchronization problems between different links.
27.3.2 Design and Simulation of Power Distribution Network The power distribution network of this RF SiP is complex since it has a variety of supplied voltages, such as 5.5 V, 5 V, 3.3 V, 2.8 V, 2.5 V, 1.8 V and so on. Several copper layers in the rigid-flex substrate are applied to form the power distribution network (Fig. 27.11). Due to the larger number of planes cut outs and vias on the power plane, power integrity should be taken into considerations since these non-ideal current paths may seriously affect supplied voltages and reliability of the substrate. The DC voltage drop (VD) and current density (CD) distribution are two important aspects of the post-design power integrity simulations, which will be demonstrated in this section. Before that, as the basis of the simulation, the simulation model of
Fig. 27.11 Power distribution network design of the rigid-flex substrate
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the PDN is firstly revealed. The power distribution network is carefully designed to ensure the normal voltage supply of the active chips. The DC power integrity simulation of the PDN is performed in an electromagnetic software based on the finite-element-method. Because of the complex model, large amount of meshes and heavy computation work, a 2.5D electromagnetic field solver is selected to balance the simulation accuracy and efficiency. The simulation model of the power integrity analysis is revealed in Fig. 27.12. The layout of the substrate is imported along with the lumped models of the passive components (resistors, inductors, and capacitors). In order to determine the DC voltage drop and current density distribution of the RF SiP, many voltage sources and current sinks are added on the substrate. Figure 27.12a demonstrates the simulation model. All the sources and sinks are referenced to the ground signal on the BGA. A small part of the PDN is displayed in details (Fig. 27.12b) and analyzed (Fig. 27.12c). The voltage source is added at the entrance of the PDN, such as the BGA, or the output pins of the VRM, which has a low output resistance. The current sink is added at the exit of the PDN, such as the input pins of the VRM or active chips, and which has a high input resistance. Similarly, other supplied voltages follow the same setting rule and finally the PDN simulation model is constructed. DC voltage drop is one kind of characteristic of power integrity. The voltage supplies are variable to different chips. Normally the ripple of the supplied voltages should be controlled under 5% of the voltage values. The power distribution network
Fig. 27.12 The DC power integrity simulation model of the rigid-flex substrate
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Fig. 27.13 DC voltage drop contour and key values of the rigid-flex substrate (power plane)
needs to cover the supplying area and avoid large resistance. The power plane is a better choice of delivering current and voltage compared to power traces since it has much less resistance. The positions of the power vias are often rearranged to reduce the damage to the power planes. As it is shown in the DC voltage drop contour (Fig. 27.13), the voltages at the entrance and exit of the power planes are presented. The PDN of typical supplied voltages are well designed. The maximum voltage drop appears at the digital voltage supply of the feedback ADC, which is 6 mV and occupies 0.3% of the supplied voltage (1.8 V). Current density distribution is another kind of characteristic of power integrity. The current density of the power plane is related to the DC voltage drop. The position of the highest current density is usually accompanied with the largest resistance and voltage drop. Too high current density will result in high joule heat accumulation and may deteriorate the copper foil of the substrate. The current density problem associated with the reliability is especially important to this high-power RF SiP with severe thermal management problems. The current density distribution and typical current density values of two layers are displayed in Figs. 27.14 and 27.15. Generally, the current-carrying capacity of conductors is constrained by the thickness, width and acceptable temperature rises. The best method to determine the acceptable current density and reliability of the substrate is to perform the multi-physical field simulation comprising of thermal management and electrical simulation based on the actual trace patterning. Here, in order to evaluate the current density distribution quickly, we follow the thumb rules of determining current-carrying capacity of conductors according to the IPC standard. The current-carrying capacities of the external and internal conductors with 20 ºC temperature rise is 12916 A/cm2 and 6458 A/cm2 respectively.
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Fig. 27.14 Current density distribution of the top and bottom layer (chip placement layer)
Fig. 27.15 Current density distribution (power plane layer)
From the simulation current density distribution, the critical current density is 3370 A/cm2 for the external layer (point B in Fig. 27.14), and 3051 A/cm2 for the internal layer (point B in Fig. 27.15). Both of the results meet the IPC standard and the average temperature rise will be less than 20 ºC. Some small areas at the edge of the power plane will be more than 5000 A/cm2 , but it does not matter since the joule heat will spread over the plane quickly and average temperature rise is not very much.
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27.4 Thermal Management Evaluation of RF SiP Thermal management of this RF SiP is critical important since the total power adds up to 20.1 W (Table 27.1) and the system size shrinks as small as 5 cm × 5.25 cm × 0.8 cm (Fig. 27.3). The maximum junction temperatures are usually regulated as 120 ºC for silicon chips and 150 ºC for GaAs chips. In fact, the operating temperature of active chips is often suggested not more than 95 ºC in order to obtain good chip performances. Thus, thermal management evaluation is essential to the application of this RF SiP. What’s more, the ambient temperature of this RF SiP for a micro base station ranges from 0 to 60 ºC. High ambient temperatures furtherly increase the average junction temperatures of all the chips at full load. Thermal management design of the RF SiP includes thermal resistance network analysis and thermal management simulation analysis of the package structure. In this section, firstly thermal resistance network is extracted and a qualitative comparison is made between two RF SiP structures in Sect. 27.4.1. As to the structure 2 with good thermal management performance, detail thermal management is evaluated by using a thermal simulation software based on the finite-volume-method (FVM) in Sect. 27.4.2.
27.4.1 Thermal Resistance Analysis of the Package Structure Thermal management performance of the RF SiP is strongly related with its internal chip power characteristics (Table 27.1). Typical chip characteristics such as chip ID, functionality, and equivalent heat flux density are all demonstrated in Fig. 27.16. In the map, the designators in the braces represent the functionality of each chip. It can be seen from the map that the demodulator chip (U10) has the highest heat flux density since it consumes 1.25-W energy within 2.8 mm × 2.8 mm × 0.5 mm
Fig. 27.16 Chip ID, functionality and equivalent heat flux density
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Fig. 27.17 Heat dissipation path and thermal resistance network
die size. Other RF chips such as digital signal amplifier (DSA), modulator (MOD), digital-analog converter (DAC), local oscillator (LO) all have considerable heat flux densities. All these chips need to be modeled in the thermal management evaluation. This RF SiP is soldered on a motherboard with an aluminum heatsink mounted on the top side. Thermal resistance network of this package can be analyzed as Fig. 27.17. Since two structure scenarios are demonstrated, thermal resistance networks have a little difference in the top rigid substrate area. Junction temperature of each chip can be calculated from this thermal resistance network. However, multiple heat sources and complex structures make this a complicated process. This thermal resistance network is analyzed and give instructions to the thermal management optimization of this package. Then thermal simulation based on FVM is utilized and finally an optimized package solution is obtained. By using the superposition theorem, this multiple source resistance network can be analyzed. The junction temperatures of chips on the top or bottom layer can be calculated in the following form: j i TjTk = Tambient + n=1 Bn Q Tn × Rupper m=1 Am Q T m + i i + n=1 C n Q Tn + m=k Dm Q Tm × RXTk j i E Q + F Q TjBk = Tambient + m=1 m Tm × Rdown n=1 n T n i i + m=1 G m Q Tm + n=k Hn Q Tn × RdieBk
(a)
(b)
Rupper = RairT + Rhsk + RtcaT + RXT
(c)
Rdown = RairB + Rpcb + RrgdB
(d)
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The coefficients (Am , Bn , Cn , Dm , E n , Fm , G m , Hn ) in the formulas are linear combinations of thermal resistances in Fig. 27.17. Take formula (a) as an example, the junction temperature of chip k on the top layer (TjTk ) is relevant to the ambient temperature (Tambient ), thermal resistance of the upper side heat dissipation path (Rupper ), thermal resistance of material up above the chips (RXTk ) and power of all the heat sources (Q T n ). Thermal management of the RF SiP can be optimized from these aspects. Firstly, Rupper and RXTk can be optimized from the package structures. RXT and RXTk are different between two structure scenarios. The face to face scenario provides a better upside heat dissipation path if thermal vias are designed on the rigid-flex substrate. Secondly, heat sources Q Tn is also affecting the overall thermal performances. Comparing formula (c) and (d), it is easy to find out that thermal vias in the organic substrate provide the top layer a lower thermal resistance path compared with the downside. Thus, placing chips with larger power consumptions on the top layer is a wise and effective method. Last but not least, the ambient temperature is of great importance not only affecting the junction temperature, but also the thermal resistance of elements that surrounded with the environment. It is not easy to lower the ambient temperature in most specific occasions, but lower the thermal resistance of the interfaces are feasible by a variable of methods, such as forced air convection cooling and cold plate cooling method.
27.4.2 Thermal Management Simulation of RF SiP As it can be summarized from the package structure and substrate design above, thermal management simulation of this high-power RF SiP is complicated since this package comprises of multi-layer structures, multiple heat sources, many thermal vias and complex copper traces. Thus the thermal simulation model should be simplified under the premise of simulation precision, in order to improve the mesh quality, accelerate the convergence speed, and reduce the computation time. Some reasonable simplifications are assumed as follows: • The models of solder balls are simplified as blocks with the same thermal conductivity. • Active chips are simplified as silicon blocks with uniform heat power on the surface. • The copper trace pattern on the PCB is considered in copper coverage rate settings. • Thermal vias in the substrate are modeled as blocks with equivalent thermal conductivity. • For the simulation boundary, natural air convection condition is assumed. Thermal management of this RF SiP is evaluated by using a thermal simulation software based on the finite-volume-method (FVM). Figure 27.18 demonstrates the thermal simulation model of the RF SiP (structure 2). The size of each component and typical thermal characteristics of the material used are illustrated in Table 27.2.
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Fig. 27.18 Thermal simulation model of the RF SiP
Table 27.2 Size of components and thermal characteristics of materials Component
Material
Size (mm)
Thermal conductivity (W/mK)
TTD
Silicon
–
148
Thermal adhesive
Composite
–
3
Molding
Epoxy resin
–
0.8
BGA
PbSn(63/37)
0.6
51
Shielding cap
Al
50 × 50 × 2
240
Substrate
BT/Cu
50 × 50 × 1
53.5,53.5,0.435
PCB
FR4/Cu
150 × 120 × 1
53.5,53.5,0.435
Heatsink
Al
60 × 60 × 10
240
Based on the simulation model, a worst-case RF SiP without thermal vias designed in the substrate is demonstrated in Fig. 27.19. The RF SiP is placed in the natural convection environment. From the simulation results, the highest junction temperature of the package reaches unbearable 98.4 ºC, which may cause functionality problems to RF chips. Thus, structure and power distribution optimization are needed to decrease junction temperatures. Firstly, thermal management can be optimized from the structure aspects. Structure optimization of the RF SiP includes not only chip mounting structures, but also thermal via design in the substrate. On one hand, the effectiveness of thermal via design is presented. As it is known to all, the vertical thermal conductivity of the organic substrate (0.435 W/mK) is relatively low compared to other substrate materials such as LTCC, silicon, aluminum and so on. However, proper thermal via design helps improve thermal performance of the organic substrate effectively. This can be concluded from simulation results in Figs. 27.20 and 27.21. The structures with and without thermal vias designed beneath chips are compared. From the simulated temperature contour (Fig. 27.20), it is obvious that thermal vias help minimize the junction temperature gap between different chips in the top substrate. The junction temperature gap, decreased from 31.2 to 5.3 ºC, is caused by heat accumulating and restrained beneath the chips. Thermal vias connect different copper layers and spread the heat to the large area. What’s more, thermal vias provides a direct heat dissipation path from chips to the
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(a) lateral view of the structure (b) bottom substrate (c) top substrate
Fig. 27.19 Simulated temperature contour of the original RF SiP structure without thermal vias
(a) without thermal vias
(b) with thermal vias
Fig. 27.20 Simulated junction temperature contour of the top substrate
aluminum heatsink on the top side. Consequently, the average junction temperatures of the top substrate are much lower with thermal vias. The junction temperatures of the bottom substrate do not decrease as obvious as top substrate, which is account to the small amount of solder balls and the lower thermal conductivity of the PCB. These can be summarized in the simulated junction temperature curve with different power consumptions (Fig. 27.21). On the other hand, optimization of the chip mounting structure is demonstrated. As it shows in Fig. 27.3, two different package structures are designed with chips mounted on the different sides of the rigid-flex substrate. Both structures have thermal
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Fig. 27.21 Simulated junction temperature with and without thermal vias (Structure 2)
vias designed in the organic substrate. The same chip power distribution conditions are assumed. From the junction temperature curve with conditions of two structure scenarios (Fig. 27.22), the average junction temperatures of face to face scenario, including top and bottom substrates, are much lower than that of back to face scenario. This can be attribute to the good heat dissipation path direct from chips to the heatsink. Hotspot appears in the bottom layer with an amplitude of 82 ºC, which indicates acceptable thermal management of this RF system in package. Secondly thermal management can be optimized from power characteristic distribution optimization. From the power characteristic distribution in Fig. 27.16, it can be observed that digital part of the RF SiP consumes a small portion of total power (6.9 W) but occupies half of total areas. Thus, heat flux densities of the digital part are less than the summation of the other parts. Due to the aforementioned better upside heat dissipation path than downside, it is reasonable to place the high-power part on the top rigid substrate. In the simulation results depicted in Fig. 27.23, two cases are compared with high power RF part placed on the bottom substrate and digital part placed on the top substrate (before optimization), or position of two parts exchanged (after optimization). Junction temperatures are optimized with the highest temperature decreased from 96.7 to 82.3 ºC after optimization. The hotspot of the RF SiP transited from the RF chips to digital parts. This is important since digital chips are more stable than RF chips in the high temperature environment. Thirdly thermal management can be optimized from ambient temperature optimization. If the thermal performance with natural convection does not meet system requirements, ambient temperature optimization is an additional method to help
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Fig. 27.22 Simulated junction temperatures of two structure scenarios
Fig. 27.23 Junction temperature comparison before and after optimization (Structure 2)
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Fig. 27.24 Junction temperature of natural convection, forced air cooling and cold plate cooling of structure 2
improve the heat dissipation efficiency. Forced air cooling and cold plate cooling are both effective ways. Based on the face to face structure and optimized chip power distribution, three cases such as natural convection, forced air cooling and cold plate cooling are simulated and compared in Figs. 27.24 and 27.25. Compared with natural convection method, forced air cooling and cold plate cooling are able to decrease junction temperature of the hotspot on the top substrate effectively by increasing the heat exchange capabilities of the top substrate. The junction temperature rise of RF part can be minimized less than 30 ºC by the forced air cooling, and less than 4 ºC by the cold plate cooling. This is especially useful to this RF SiP designed for the micro base station applications, since the environment temperature of which may reach 60 ºC in some occasions.
27.5 Assembly Flow of RF SiP The assembly process of this RF SiP is very simple and reliable. The whole packaging and assembly flow are depicted in Fig. 27.26 based on structure 1. First of all, Substrate cleaning is done before the assembly process (Fig. 27.26a). The chips on the bottom substrate are assembled using surface mount technology (SMT), and then thermal conductive adhesive is coated on the surface of the chips
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Fig. 27.25 Junction temperature comparison under different heat dissipation of structure 2
Fig. 27.26 Packaging and assembly flow of the RF SiP
before a shield cap is mounted (Fig. 27.26b). The aluminum cap is connected to the ground so as to provide enough electromagnetic isolation between different links of this system. After that, the solder balls are mounted on the substrate to form the ball grid array (BGA). Meanwhile, RF chips and a shield cap are soldered on the top rigid substrate (Fig. 27.26c). Thermal conductive adhesive is also used to fill the gap
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between the chips and the shield cap in order to minimize the thermal resistance. After the assembly of the bottom and top rigid substrate, the flexible substrate is bended and conductive silver paste is coated and solidified on the interface of the top substrate and the bottom shield cap, and then the 3D stacked package assembly is finished (Fig. 27.26d). The assembly process of the structure 2 has a little difference with structure 1. BGA solder balls are formed firstly and then all the chips are mounted on the same side of the substrate. After that, thermal conductive adhesive is attached and shield caps are mounted, and then the flexible substrate is bend. Consequently, one round reflow process is reduced and reliability of some RF chips is improved. At last, the RF SiP is surfaced mounted on a test board with voltage regulator modules (VRM) and a surface mounting connector, which is compatible with the connector on the mother board. Then the test board can be plugged and used in the micro base station system. This is the standard procedure of finishing the RF SiP packaging and assembly. In fact, as it is revealed in the photos (Fig. 27.26e), the shield caps are usually removed to have the whole system tested in the debug phase.
Chapter 28
RF System Integrated SiP Design Case Liqiang Cao and Gengxin Tian
28.1 RF System Integration Technology 28.1.1 RF System Introduction A complete wireless communication system includes baseband part, RF part and antenna system, as shown in Fig. 28.1. The baseband part usually includes a digital signal processor (DSP) for processing all communication algorithms in the physical layer, including channel coding, encryption, channel equalization, voice coding/decoding, modulation and demodulation, etc. The RF part includes frequency conversion module and RF front-end module. The frequency conversion module is used for conversion of baseband signal and RF signal, and the RF front-end module is used for transmitting and receiving RF signal. The RF part includes one or more receiving links and transmitting links. The receiving link is composed of RF bandpass filter, low noise amplifier, mixer, IF filter and IF amplifier. Its main function is to convert the RF signal received by the antenna into IF signal through down conversion or directly into baseband signal. The transmitting link is composed of IF bandpass filter, mixer, power amplifier and RF filter. Its main function is to up convert the baseband signal encoded and modulated by the baseband module into RF signal. In addition, the RF front-end module also contains a large number of discrete passive components, which are mainly used for power filtering, decoupling, DC bias, tuning and impedance matching. The main indicators of RF link include output power, link gain, linearity, noise figure and isolation between links. The performance of each RF link is determined by the performance of active and passive components, so the indicators of RF link is also closely related to the indicators of RF components. L. Cao · G. Tian (B) Shanghai, China e-mail: [email protected] © Publishing House of Electronics Industry 2022 S. Li (ed.), MicroSystem Based on SiP Technology, https://doi.org/10.1007/978-981-19-0083-9_28
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Fig. 28.1 Wireless communication system architecture
With the development of wireless communication technology, RF system architecture also changes. Firstly, the increase of the number of frequency bands will lead to the increase of devices in RF system; Secondly, the emergence of new communication technologies will complicate the RF system architecture.
28.1.2 Miniaturization Trend for RF System Integration 1.
Development of Wireless Communication Spectrum
Spectrum is a physical quantity existing in nature, which cannot be increased or reduced. According to the definition of the International Telecommunication Union(ITU), the frequency range of electromagnetic waves that human beings can recognize and use is 3kHz~300GHZ. For ease of expression, these frequency bands are divided into 8 parts according to the frequency: VLF (very low frequency), LF (low frequency), MF (mediate frequency), HF (high frequency), VHF (very high frequency), UHF (ultra-high frequency). In order to prevent interference between different communication applications, the generation and use of radio waves are strictly controlled by law and coordinated by the International Telecommunication Union. The radio spectrum is divided into multiple radio bands according to frequency and allocated to different purposes. In general, the higher the frequency, the worse the penetration. The lower the frequency, the smaller the bandwidth can be provided. In a specific frequency band, the transmission rate that can be achieved is limited. It is also restricted by practical physical conditions such as signal-to-noise ratio and channel bandwidth. Shannon’s theorem describes the relationship between channel width (B) and channel maximum data transmission rate (C), as shown in formula (28.1). It shows that the wider the frequency band, the higher the data transmission rate. According to the communication principle, the maximum channel bandwidth of wireless communication is about 5% of the carrier frequency. Therefore, the higher the carrier frequency, the larger the achievable signal bandwidth, and the bandwidth further determines the maximum transmission rate of data. Therefore, in order to achieve higher data transmission rate and better performance, modern wireless communication technology has been developing towards higher frequency band.
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45 40 35 30
11
25
8
20
4G
8
15 10
21
5 0
15
2
2
3
6
10
25
26
2G/3G
14
Fig. 28.2 Number of mobile communication bands
C = B ln(1 + S/N )
(28.1)
The development of mobile communication technology has gone through five generations, and each update will introduce new frequency bands. As shown in Fig. 28.2, according to the standard specification document released by the international mobile communication standard release organization 3GPP (3rd generation partnership project), from 2G GSM communication to 4G LTE communication, the number of mobile communication bands has increased from 2 to 41, and due to the long-term evolution characteristics of 4G communication, the number of 4G communication bands will continue to grow [3]. 5G communication will expand the frequency to millimeter wave band. 2019 is the first year of 5G. 5G communication will become commercial in this year and begin large-scale erection. By 2020, 5G communication will add more than 50 communication bands, and the global 2G/3G/4G/5G will support more than 91 bands. 5G communication includes sub-6GHz band and millimeter wave band. In the sub-6GHz band, in addition to some bands compatible with 4G communication, several bands within 3GHz and three broadband bands between 3GHz and 6GHz (bandwidth larger than 500MHz) n77\n78\n79 are added. In addition, in the millimeter wave band, n257~n261 bands are added, and the bandwidth is larger than 1GHz. The increase of the number of frequency bands and bandwidth not only improves the data transmission rate of wireless communication, but also improves the low delay of data transmission. 2.
The Development of RF System Architecture
Due to the rapid development of mobile communication technology in recent years, the RF system architecture in mobile terminal equipment has changed greatly. As mentioned above, in order to improve the signal transmission rate and spectrum efficiency, each generation of mobile communication technology will add many new frequency bands. Compared with 3G communication, 4G communication has added more than 30 new frequency bands. At present, the communication frequency bands are distributed below 6GHz, while 5G communication introduces higher millimeter
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wave frequency bands. With these newly added communication frequency bands, there is an increase in the number of RF links in mobile terminal equipment and the number of RF devices. Figure 28.3 shows the system architecture of RF front end in 2G, 3G and 4G mobile terminal equipment respectively. It can be seen that 2G communication has only four frequency bands, so the RF front-end system is relatively simple, including only one PA module integrating power amplifier, filter and antenna switch, as well as two filter banks. There are 10 frequency bands in 3G communication, and the corresponding RF front-end system adds two PA modules and four duplexer groups compared with 2G. In 4G communication, RF front-end system not only produces exponential growth in the number of devices, but also greatly improves the design complexity. The RF chips include: a multimode multiband power amplifier (MMPA) with integrated frequency selection switch, 3 PA modules, 3 duplexers/multiplexers, 6 receive/transmit filters, 1 RF switch, 3 antenna switching modules for high frequency, low frequency and diversity circuits, and 1 diversity receive filter bank. By comparing and analyzing the RF frontend system architecture of 2G, 3G and 4G communication, we can get two views: the number of RF front-end devices is increasing; The complexity of RF front-end system is increasing. From these two points of view, we can draw a conclusion that the RF front-end system integration in mobile terminal equipment is facing an urgent miniaturization problem. In addition, the emergence of new communication technologies will complicate the RF system architecture. For example, the large-scale MIMO technology in 5G communication refers to increasing the number of base station antennas in the multiuser MIMO system to 100 or more. Due to the sufficient number of antennas at the transmitting end, the influence of fast fading in the propagation channel can be eliminated. Large scale MIMO technology has brought breakthrough improvement and development to system spectrum efficiency and energy efficiency, so it has rapidly become one of the key technologies of 5G mobile communication. The RF system applied to large-scale MIMO technology will introduce many receiving and transmitting links due to its large number of antennas, which makes the RF system integration face the urgent demand of miniaturization.
28.1.3 RF SiP Versus RF SoC There are two schemes for RF system integration. One is RF SoC scheme, which uses CMOS technology to integrate different functional components in the whole RF system into a single chip; The other is the RF SiP scheme, which integrates the components implemented through different processes into one package. The advantages and disadvantages of RF SiP and RF SoC are discussed from two aspects.
GSM850/900
DCS/PCS
GSM850
LPF/ Match
QUANTUM TX
Power control
LPF/ PA module Match
Antenna Switch
PA module
PA module
QUANTUM TX
LPF/ Match Antenna Switch
Antenna
2G/3G/4G FDD/TDD/ TD-SCDMA Transceiver
B40 B41
B41
B40
RX
B7
LB band 5 8 20
RX
TX
TX
TX
RX
TX
RX
TX
RX
HB band 1234
Diversity receive filter DRX
MMPA
Band Select Switch
Band Select Switch
TX
RX
(3)4G RF front end system
PAM
PA
PAM
PA
PAM B34/39
PA
2G LB
2G HB
LB
HB
Fig. 28.3 System architecture of RF front end in 2G, 3G and 4G mobile terminal equipment
(2)3G RF front end system
GSM/GPRS/ EDGE/WCDMA Transceiver
Power control
LPF/ PA module Match
Rx filters
(1)2G RF front end system
2G/2.5G GSM/GPRS/ EDGE Quad-Band Transceiver
GSM900
DCS
Rx filters
ASM
Diversity antenna
HB ASM
LB ASM
28 RF System Integrated SiP Design Case 815
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1.
L. Cao and G. Tian
Integration Scheme of Passive Components in RF SoC and RF SiP
There are 60–80% passive components in RF system, including inductor, capacitor and resistor. These passive components play the role of impedance matching, filtering, tunning, DC blocking and bias. The electrical performance of passive components directly affects the performance of RF system. Lower Q value will increase the power consumption of the whole system, and lower self-resonance frequency will reduce the applicable frequency range of RF system. Passive components can be integrated in two ways: on-chip integration and off-chip integration. In the RF SoC integration scheme, the passive device adopts the on-chip integration mode, which is in the form of integrated passive device (IPD); In the RF SiP integration scheme, the passive components adopt the off-chip integration mode, which is in the form of IPD or discrete passive components, in which IPD is integrated in the packaging substrate or RDL, and the discrete passive components are attached to the packaging substrate through surface mount technology(SMT) or embedded in the packaging material. 2.
Influence of RF Device Manufacturing Process on RF System Performance
A complete RF system consists of many components with different functions, including baseband IC, transceiver IC and RF front-end module which contains power amplifier, filter, RF switch, low noise amplifier, antenna tuner and so on. Among them, the baseband IC adopts the traditional CMOS process, and the transceiver IC adopts the BiCMOS process. Due to the large number of components and various functions, the implementation processes of components in RF front-end module are also different. Figure 28.4 shows the development trend of semiconductor process adopted by RF chips in RF front-end module. As the core component of RF front-end module, the performance of PA has a great impact on the whole RF system. In order to achieve large gain and power added efficiency, PA generally adopts GaAs process with wide band gap, while for RF systems with high transmission power requirements, such as base station RF system, PA generally adopts GaN process with wider band gap. Power Amplifiers
Si LDMOS
CMOS
SiGe GaAs RF SOI
GaAs
Antenna/ Mode Switches
RF SOI RF MEMS?
Antenna Tuners
RF SOI RF MEMS? SAW BAW
Filters, Duplexers LNA, LNA+Switch
GaAs RF SOI
2010
2012
2014
2016
2018
Fig. 28.4 The development trend of semiconductor process adopted by RF chips
2020
28 RF System Integrated SiP Design Case
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Although the PA based on CMOS process has been developing, its performance still cannot be compared with GaAs PA and GaN PA. At present, GaAs PA still dominates the PA market. In order to achieve higher Q value and better filtering characteristics, the filter is generally based on surface acoustic wave (SAW) or bulk acoustic wave (BAW) technology and manufactured by MEMS process. RF switch and LNA adopted the traditional GaAs process at first. However, RF SOI process with low cost and performance can meet the requirements has been adopted in recent years. In order to achieve the best performance of RF system, each device needs to work in the best performance. Therefore, if RF SoC technology based on CMOS process is used to realize the integration of RF system, a compromise will be made on system performance and process compatibility. 3.
Wireless Communication System Integration Scheme
At present, the integration of wireless communication system generally adopts the method of combining SoC and SiP, as shown in Fig. 28.5. For the digital baseband and RF transceiver, SoC technology can be used to realize single chip integration. For RF front-end modules with various functions and processes, RF SiP technology is a reasonable integrate method in the current environment. Firstly, RF SiP scheme can realize the integration of high-Q passive devices by many methods. At present, the size of passive surface mount devices continues to shrink from the original common 0402 package to the common 01005 package in RF SiP. The reduction of package size reduces the parasitic effect, which can make the device applied to higher frequency band. Secondly, for off-chip IPD, we can obtain IPD with good electrical properties by selecting dielectric materials and conductor materials with good electrical properties. In addition, due to the advantages of heterogeneous integration of RF SiP, the RF chips with the best performance realized by different processes can be used for system integration, so as to achieve the best system performance. In addition, RF SiP is directly integrated with commercial components, which greatly shortens the time of design and tunning. The vigorous development of advanced packaging technology, flexible packaging structure and Fig. 28.5 Wireless communication system integration scheme
SoC
SiP FEM
Baseband IC
RF Tranceiver IC
PAM
818
L. Cao and G. Tian
the realization of three-dimensional integration make RF SiP the best choice for the miniaturization of RF system.
28.2 Design and Simulation of RF SiP The emergence and development of RF SiP effectively alleviate the miniaturization demand of RF system integration. Miniaturization demand puts forward new requirements and challenges to the design of RF SiP. For example, the layout of devices is more compact, the spacing of signal lines becomes shorter, the electromagnetic interference becomes stronger, and the heat flux density in the package becomes larger, which reduces the heat dissipation performance of the package. Therefore, it is necessary to carry out reasonable structural design, electrical design and thermal management for RF SiP. Next, taking a base station RF system integration SiP as an example, the packaging structure design, electrical simulation optimization design, packaging thermal management and optimization design of RF SiP are introduced.
28.2.1 RF SiP Structure Design RF SiP packaging structure design includes substrate lamination design and device layout. RF SiP packaging structure design is actually a collaborative design process. The substrate lamination design needs to consider the manufacturing process and the electrical performance of the system. The device layout will affect the electrical performance of the system and the thermal performance of the package. Figure 28.6 shows the system architecture of a RF system receive module applied to a micro base station. Its input is RF signal and output is IF signal. The receive module is composed of 2 receive links, including 2 active chips and 125 surface mounted passive devices. The mixer is QFN packaged device, the IF amplifier is bare die, and the IF filter is built by discrete passive devices. The RF performance index of this module is shown in Table 28.1. For high-density system integration, in order to improve the thermal performance of the package, it is necessary to evenly distribute the heating active chips, so as to RX1_I RX1_Q RX2_I
IF AMP
RX1_RFIN FILTER
RX2_Q
Fig. 28.6 RF system architecture of RF SiP
RX_LO
MIXER RX2_RFIN
28 RF System Integrated SiP Design Case
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Table 28.1 The RF performance index of the module Index
Test state
Value
RF frequency range
700MHz~2900MHz
IF frequency range
20MHz~500MHz
LO frequency range
700MHz~2900MHz
Link gain
RF attenuation is 0dB
25dB
Link gain flatness
In continuous 80MHz band