G7000A W7000 Schematics

Citation preview

9. BLOCK DIAGRAM

9. BLOCK DIAGRAM 9.1 Main Board The G7000/W7000 is made up of two PCBs. In lower part of the folder, there is a main board. And in the upper part of the folder, there is a FPCB. Below you can see the block diagram of both PCBs.

s ip

h lc

i b

o M

Figure 9-1. Main Block diagram.

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Schematics & manuals on www.mobilchips.com ___Mobilchips__

9. BLOCK DIAGRAM

9.2 FPCB

h lc

s ip

i b

Figure 9-2. FPCB Block diagram.

o M

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9. BLOCK DIAGRAM

9.3 RF

s ip

h lc

o M

i b

Figure 9-3. RF Block diagram

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9. BLOCK DIAGRAM

h lc

i b

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s ip

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10. CIRCUIT DIAGRAM

10. CIRCUIT DIAGRAM 10.1 BB Circuit 1

2

6

5

4

3

HSP103

HSP102

HSP101

1 VCC GND

R100 20K

C103 150p

C100 10u/16V A_case

C101 22n

A

VR2B 4 6

ICTL

Q100 NDC652P

3 1 2 5

R117 0R

VBAT_2 D100 CRS08

5 2

4

A(3)

VR2B

s ip

R118 10K

3

U103 NC7SZ32

i b

SUB_CS VCHG VBAT C P0402FC12C P0402FC12C

C105 47p

VR2B

R101 20K

26 VCHG2 VCHG1

4 5

R103 MNR04 10K

R105 100R

24 23 20 15 14

1 3 5 7

4.7R 4.7R

R110

47R MNR04 1 3 5 7

A3 10

6 O1

B3 9

7 GND

O3 8

R124 0R

A(0)

MIDI_CS

1K

R112

47R MNR04

VBAT

HSP121

HSP122

HSP120

HSP119

HSP118

HSP116

HSP117

HSP115

HSP114

HSP113

HSP112

HSP111

HSP110

HSP109

HSP108

HSP107

HSP106

25

2 4 6 8

VBACKUP

_CS3 L103 L104

MAIN_CS A(1)

D(0) D(1) D(2) D(3) D(4) D(5) D(6) D(7) _WR LCD_RESET

AUX_IN CTS RTS TX TXD

MAIN_BACKLIGHT I_LED1 I_LED2 I_LED3 SUB_BACKLIGHT SUB_CS A(2) MOTOR (REC_N) EARN REC_P SPKN SPKP

RPWRON

1 3 5 7

TDO TMS TCK TDI

L105 L106 L107 L108 L109 L110 L111 L112

BLM15AG121PN1 BLM15AG121PN1 BLM15AG121PN1 BLM15AG121PN1 BLM15AG121PN1 BLM15AG121PN1 BLM15AG121PN1 BLM15AG121PN1

L113 L114

BLM15AG121PN1 BLM15AG121PN1

L190

J102 LG_LCD_CON_30P 1 2 3

BLM15AG121PN1 BLM15AG121PN1

VDD_3.0V MAIN_CS A0 (D/I)

L124

n.m 1 3 5 7

4 5 6 7 8 9 10 11

BLM15AG121PN1 BLM15AG121PN1

L117 L118 L119 L120

BLM15AG121PN1 BLM15AG121PN1 BLM15AG121PN1 BLM15AG121PN1

MNR04

LED_EN VBACKUP I_LED1 I_LED2 I_LED3 EL_EN VBAT

22 23 24 25 26 27 28 29 30

C108

R114

47p

1M

PCM_TX PCM_SYNC PCM_CLK PCM_RX

D

_WR _RES VSS

15 16 17 18 19 20 21

BLM15AG121PN1

L115 L116

D0 D1 D2 D3 D4 D5 D6 D7

12 13 14

R109 220R

BLM15AG121PN1

DCD R113

C

MC74VHC126

RXD RX DTR HANDSFREE

16

1 AUXGND 12 GND2 19 GND1

5 B1

AUXOP AUXON

R111 2 4 6 8

11 9 8 7

HSP105

DCD

6

HSP104

TDO TMS TCK TDI

O2 11

D(0:7)

R107 R108 2 4 6 8

13 RXD 10 RX 3 DSR 2 HANDSFREE POWER_ON

4 A1

R122 10K

BATT_TEMP

R106 47R MNR04 2 4 6 8

18 AUXOP 17 AUXON

E

B2 12

R104 10K 8 6 4 2

21 BATT2 22 BATT1 AUXI CTS RTS TX TXD

A2 13

3 O0

R102 33K

7 5 3 1

27

L102 BLM15AG100PN1

D

o M

V101

V100

2 B0

HSP134 HSP136 HSP135 HSP133 HSP130 HSP131 HSP132 HSP137

L100 BLM15AG100PN1

h lc

R123 0R

HSP513

A(2)

2

VCC_EXT

HSP128

5

1

4

MAIN_CS

VCC 14

C104 10u (2012)

HSP126

GND IN

ON_OFF

1 A0

R121 10K

Q101 RN1307

R119 0R

U102

B

V102 P0402FC12C

R120 0R

RPWRON

HSP512

OUT

FOLDER

VBAT

R116 0.2R(1%) (2012)

HSP129

VR2B

VR2B

B

VR2B

3

HSP127

U101 SN74HC1GU04DCKR

SUB_CS CS2 (A2) VSS1 VBAT1 MOTOR RECREC+ SPKSPK+

E

HSP514

3 2 CLK RST 7 6

IO VPP

J100 LG_AMP_SIM

C109 100n/16V (2012)

VCHG

5

A

HSP100

SIM_CLK SIM_RST SIM_I_O SIM_VDD

8

7

C110 1uF (1608)

C106 C107 47p 47p

F

F R115 0R

J101

Section

LG-IO_CONN_24P

Date

Sign & Name

Designer

02.04.11

D.S.JUNG

Checked

02.04.11

N.S.KIM

Approved

L

LG issue

1

2

3

4

5

- 89 -

6

Notice NO.

Data

Name

7

Electronics Inc

Model

Sheet/Sheets 1/6

Drawing Name

BASEBAND INTERFACE

Drawing No.

8

10. CIRCUIT DIAGRAM

1

2 R231

KEYLIGHT PWT

4

3

5

6

7

8

9

10

12

11

0R VR2B

LCD_RESET JACK_DETECT SUB_BACKLIGHT DTR DCD MELODY_INT FOLDER A

R672

10K A

XO_ENA RF_ENA SUB_LED2 SUB_LED3 SUB_LED1 MELODY_RESET

VDD_RTC

PCM_CLK PCM_SYNC PCM_RX PCM_TX

C233 100p

CTS RXD

ADD00 ADD01 ADD02 ADD03 ADD04 ADD05 ADD06 ADD07 ADD08 ADD09 ADD10 ADD11 ADD12 ADD13 ADD14 ADD15 ADD16 ADD17 ADD18 ADD19 ADD20 ADD21 ADD22

R225 1M D201 1SS388

TESTRESETZ TEST1 TEST2 TEST3 TEST4 TDO TDI TCK TMS

U201 NAUSICA_CS

SPK_EN B2 SDIO3 C4 SCLK3 B3 SRST3

VR2B

VAUX VS2 VS1 SVDD SDIO5 SCLK5 SRST5

VBAT_2 R208 20K

BDLQM BDLQP BDLIM BDLIP BULQM BULQP BULIM BULIP

MICBIAS AUXI AGNDA1 MICIP MICIN EARP EARN AUXOP AUXON BUZZOP

J6 UDX K6 UDR F5 UEN

R209

_WR

GND

TDO

TCK

TDI

TMS

C5 A6 B6 B5 A5 E6 D6 C6 F10 F8 F9 G8

BATT_TEMP RADIO_TEMP HOOK_DETECT

R204 R205 R206 R207

390R 390R 390R 390R

K2 J1 H3 E2 D3 H1 E1 H10 C1 D1

0R

_CS3 _CS2 _CS1 _CS0

SWITCH FDBK RESERVED VR2IN VR2SEL VR1OUT VR2OUT VR3OUT VR1BOUT VR2BOUT

KBR(0) KBR(1) KBR(2) KBR(3) KBR(4)

FDP

KBC(4) KBC(3) KBC(2) KBC(1) KBC(0)

FWE

D202 1SS388

_BLE _BHE

C223 100n

C224 100n

C225 100n

C226 100n

C222 2.2u (2012)

C234 10u (2012)

C227 100n

C219 10u (2012)

E

MICIP MICIN EARP EARN AUXOP AUXON C215 220n

C216

BGTR1 BGTR2 BGTR3 BGTR4 BGTR5 IBIAS VREF

1u

(1608)

C228 100n

VBAT VBACKUP

D200 1SS388

C3 J3 E5 E4 E3

VCHG ICTL

G4 G3 G2 H2 J2 G1 F4

C217

R226 n.m

100n

G

VDD_RTC C218

R219

100n

120K

VBACKUP

U202 1

C229 100n

C231

OUT

IN

GND

NC

2 4 C230 100n

S-817

100n

KBC(0:4)

F

SIM_VDD SIM_I_O SIM_CLK SIM_RST

3

C221 10u (2012)

C220 10u (2012)

REFGND

N.C

F11 VDD_PLL E14 GND_PLL

C11

E11 VDD_ANG E12 GND_ANG

R211 20K

VR2

C213 270p

QN QP IN IP

0R 0R 0R 0R

MICBIAS AUXI

A3 A1 B1 A2 D4 B4 D5

F3

G

VR3

R280 R281 R282 R283

K9 H7 J7 K8 J8 H9 H8 J9 J10 K10

UPR

GRND1 GRND2 GRND3

R229

D13 VDDS_RTC D14 VDD_RTC C14 GND_RTC

GND0 GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 GND11 F1 N8 K1 P2 P4 P10 P13 G14 A10 A7 A2 B1

VDD0 VDD1 VDD2 VDD3 VDD4 VDD5

L14 VDDS_1_1 N5 VDDS_1_2

VDDS_MIF0 VDDS_MIF1 VDDS_MIF2 VDDS_MIF3

VDDS_2

A4 B6 G1 D1

A11

XD1_03_KBR0 XD1_04_KBR1 XD1_05_KBR2 XD1_06_KBR3 XD1_07_KBR4 K6 M6 P6 N6 L6

KBC4_XD1_02 KBC3_XD1_01 KBC2_XD1_00 KBC1_NIRQ KBC0_NFIQ M5 P5 L5 K5 N4

0R 0R

VR1 VR2B V1B

VDD_RTC

33n

C206

UPR UPR VBACKUP VBAT VCHG ICTL

D

AFC PA_LEVEL

E10 E9 E8 E7 D9 D8 C10 C9

1M K3 VCC1 D2 VCC2 G9 VCC3

C

1n

C211 270p

K7 VDR G6 VDX G7 VFS H6 VCK

G13 SIM_IO F13 SIM_CLK G10 SIM_RST G11 SIM_CD_MAS0 F14 SIM_PWCTRL_I_O5

TDO_ARM

VBAT J4 K4

D7 RTC_ALARM F7 INT1 H4 INT2

J5 BFSX K5 BDX G5 BFSR H5 BDR

N7 M7 M8 P8 L8

10K

TP219

LCDSYNC TSCYM TSCXM ADIN1 ADIN2 ADIN3 ADIN4_TSCXP ADIN5_TSCYP DAC AFC APC AUXGND

D10 ON_OFF F6 RESPWRONZ

F2 C8 B8 A9 B9 C7 A7 B7 A8

C205 CK13M

TP206

L11 BFSR K10 BDR P12 BFSX M11 BDX

MCUDI MCUDO MCUEN0 MCUEN1_I_O8 MCUEN2_I_O13

R203

10K _WR

A4

F1 B10 A10

A14 VSSO

C13 OSC32K_IN B13 OSC32K_OUT C12 CLK32K_OUT

K7 L7 PWT_BU PWL_LT

N2 I_O7_NRESET_OUT P11 ARMCLK_BCLKR M2 IDDQ

A13 RFEN_NoPC A12 TCXOEN N1 niBOOT

L10 TXD_MCSI_1_09 M10 RXD_MCSI_1_010 K9 FSYNCH_MCSI_1_012 N10 CLK_MCSI_1_011

B9 E8 D9 A9 C9

N3 I_O0_TPU_WAIT P3 I_001_TPU_IDLE L4 I_O2_IRQ4 M4 I_O3_SIM_RnW H10 TSPDI_I_O4 N11 BCLKX_I_O6

o M

B11 E10 D11 D10 C10 B10 E9

VBACKUP

K1 C2 G10

R227 R228

_WR _RD

TP205

R202

TDI TMS TCK TDO HANDSFREE END_ON_OFF RPWRON 13MHZ MCLK

P14 VDX N13 VDR M13 VFSRX N12 VCLKRX

RnW_ nFOE_X_A3

F3 F2 G5 G4 G2 G3 H1 H3 H2 H4 H5 J1 J2 J3 J4 K3 K2 K4 J5 L1 L2 L3 D2

TP204

UPR

UPR

ON_OFF

s ip

h lc TP218

TP217

i b

NEMU0_ NEMU1_ NBSCAN_ TDI TDO TCK TMS

U200 CALYPSO

B2 E2

TP212

TP211

TP210

TP209

F

A(0) A(1) A(2) A(3) A(4) A(5) A(6) A(7) A(8) A(9) A(10) A(11) A(12) A(13) A(14) A(15) A(16) A(17) A(18) A(19) A(20) A(21) A(22)

DATA00 DATA01 DATA02 DATA03 DATA04 DATA05 DATA06 DATA07 DATA08 DATA09 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15

TP214

A(0:22)

B7 D7 E7 D6 A6 C6 E6 C5 B5 D5 E5 B4 C4 D4 A3 B3

TP213

E

D(0) D(1) D(2) D(3) D(4) D(5) D(6) D(7) D(8) D(9) D(10) D(11) D(12) D(13) D(14) D(15)

B14 INT4n_IT_WAKEUP P1 EXT_FIQ M3 EXT_IRQ

nBLE_I_O15 nBHE_I_O14 nFWE_X_A0 FDP_nIACK

D(0:15)

F10 ON_OFF D12 nRESPWON

E4 F5 E3 F4

TP208

C204 18p

E13 CLKTCXO F12 START_BIT_CLK13M_OUT

TSPACT00 TSPACT01 TSPACT02 TSPACT03 TSPACT04 TSPACT05 TSPACT06 TSPACT07 TSPACT08 TSPACT09 TSPACT10 TSPACT11

nCS3_ nCS2_ nCS1_ nCS0_

PA_ON D

R224 0R

TP216

D3 C1 C3 C2

M12 M14 L12 L13 J10 K11 K13 K12 K14 J11 J12 J13

RESET_RF

2

OSCAS PWON RPWON

H13 TSPEN0 H12 TSPEN1 H14 TSPEN2 G12 nSCS2_TSPEN3

EN

TX_MODEM RTS_MODEM_TOUT DSR_MODEM_LPG RX_MODEM CTS_MODEM_XF

C8 D8 B8 C7 A8 TX_IRDA RX_IRDA CLKOUT_DSP_SD_IRDA X_A4_TXIR_IRDA X_A1RXIR_IRDA

J14 TSPCLKX H11 TSPDO

CLK DATA

3

R201 220K

R220 10K

1

B VBAT

nBSCAN

X200 MC-146

TP222

K8 SDO_INT10n M9 SDI_SDA P9 SCLK_INT1n L9 NSCS0_SCL N9 NSCS1_X_A2

C

R221 n.m

TDR TEN

R223 R222 TP221

C203 20P

4

10K n.m

RX TX

UPR

UPR C202 20P

RPWRON

VR2B

RTS TXD RXIR_IRDA TXIR_IRDA SD_IRDA

A5 B12 N14 P7 M1 E1

B

TP220

C232

KBR(0:4)

33u/6.3V A-CASE H

H

Section

Date

Sign & Name

Designer

02.04.11

D.S.JUNG

Checked

02.04.11

N.S.KIM

Approved

LG issue

1

2

3

4

5

6

7

- 90 -

8

9

10

Notice NO.

Data

Electronics Inc

Name

11

Model

Sheet/Sheets 2/6

Drawing Name

BASEBAND CHIPSET

Drawing No.

12

10. CIRCUIT DIAGRAM

1

2

3

4

7

6

5

8

A

A

VR2

VR2

B

B

D(0:15) A(1:22)

s ip

TP301

U301

U302 TC58FVB641

C

R302 0R

_CS1

G2 F2 E2 C2 D2 F3 E3 C3 D6 C6 E6 F6 D7 C7 E7 F7 G7 D3 E4 F5 F4 E5

A(1) A(2) A(3) A(4) A(5) A(6) A(7) A(8) A(9) A(10) A(11) A(12) A(13) A(14) A(15) A(16) A(17) A(18) A(19) A(20) A(21) A(22)

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21

H2 CE_ J2 OE_ C5 WE_ H7 BYTE_

D

C4 RY_BY_ D4 WP_ D5 RESET_

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15

TH50VSF4683

G3 K3 G4 K4 K5 G5 K6 G6 H3 J3 H4 J4 H5 J6 H6 J7

D(0) D(1) D(2) D(3) D(4) D(5) D(6) D(7) D(8) D(9) D(10) D(11) D(12) D(13) D(14) D(15)

J5

K2 VSS0 K7 VSS1 NC0 NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11 NC12 NC13 NC14

h lc

i b

o M

VDD

J3 G4 K4 H5 H6 K7 G7 J8 K3 H4 J4 K5 J7 H7 K8 H8

D(0) D(1) D(2) D(3) D(4) D(5) D(6) D(7) D(8) D(9) D(10) D(11) D(12) D(13) D(14) D(15)

A1 A2 A7 A8 B1 B7 B8

L1 L2 L7 L8 M1 M2 M7 M8

J5 J6 K6 J9 G3

A1 A10 B1 B10 C1 F1 F10 G1 G10 L1 L10 M1 M10

C300 100n

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15

VCCF VCCS DU_CIOS VSS0 VSS1 NC0 NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11 NC12

R301

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21

G2 F2 E2 D2 F3 E3 D3 C3 C7 E7 F7 C8 D8 E8 F8 D9 G9 F4 E4 D7 E6 E9

A(1) A(2) A(3) A(4) A(5) A(6) A(7) A(8) A(9) A(10) A(11) A(12) A(13) A(14) A(15) A(16) A(17) A(18) A(19) A(20) A(21) A(22)

C

R300

H2 CEF_ H3 OE_ C6 WE_ H9 BYTE_

0R

VR2

D

E5 RY_BY_ C5 WP_ D5 RESET_ LB_ UB_ CE1S_ CE2S_ DU

n.m

C4 D4 J2 D6 G8

_CS0 _RD _WR

FDP R303

0R

_BLE _BHE _CS2

R305 10K C304 33n

C301 100n

E

E

F

F Section

Date

Sign & Name

Designer

02.04.11

D.S.JUNG

Checked

02.04.11

N.S.KIM

Approved

LG issue

1

2

3

4

5

- 91 -

6

Notice NO.

Data

Name

7

Electronics Inc

Sheet/Sheets

Model

3/6 Drawing Name

MEMORY DEVICE

Drawing No.

8

10. CIRCUIT DIAGRAM

1

2

3

4

5

6

7

8

VR3

R400 1K

2 5

MICBIAS A

6 4

C401 10u (2012)

C400 47p

1 3

JACK_DETECT

C402 47p D401 KDS160E

U404 MAX4599

A

R401 2.4K

MICIP

C405 47p

C404 100n

C403 n.m

Microphone

MIC400

HSP401

HSP400

C407 47p

C406 47p

OB-22S40-C33

C408 100n MICIN R402 1.2K

C409 47p

B

B

C410 33p

VR3

VR3

R419 7.5K VR3

R404

R405

18K

1M

U400 MAX9075 5

C

h lc C411 47p

3

+

JACK_DETECT

1 4

2

R407

i b

C413 100n

1M AUXI AUX_IN AUXOP R420 100R

HOOK_DETECT

s ip

EARN

R408 R409 R410

o M

C414 47p

C427 47p

C412 47p

Receiver

EARN REC_P

HSP402 HSP403

C

J400 9001-8905-040

4.7R 4.7R 4.7R

2

HSP404 HSP405 HSP406

V400

4 3 1

V401

Headset jack

C415 47p

VBAT

U401

D

1 2 3 4

SD_ CNIOSE DELAY ERROP_ GND SENSE_ADJ VIN VOUT

VCC_EXT

SI9182

C416 220n

P0402FC05C

P0402FC05C

D

8 7 6 5

C417 2.2u (2012)

VR3 ON_OFF D(0:7) 0R

R421

VIBRATOR

6

5

SPK_EN

390p

C421 18p

Speaker

U403

R422

V402

11 HPOUT-R 10 HPOUT-L

7 8

1 2 3 4 5 6

MCLK SUB_LED1 MELODY_INT MELODY_RESET

F

E

SPKP SPKN

16 SPVSS 15 SPVDD

YMU762

CLK1 LED -IRQ -RST NC PLLC

10K

18 SPOUT2 17 SPOUT1

28 WR_ 29 _CS 30 A0 31 _RD 32 IOVDD

_WR MIDI_CS A(1) _RD

R417

12 EQ1 13 EQ2 14 EQ3

VREF

U402 MAX4624

C420

VDD VSS

1

R416 82K

R450 150K

3

HSP4081

C422 47p

2

V403

HSP407 1

C423 47p

2

VR2B P0402FC05C

P0402FC05C

9

4

D0 D1 D2 D3 D4 D5 D6 D7 MTR

EARP

C419 10n

R415 39K

27 26 25 24 23 22 21 20 19

+

E

R414 33K

D(0) D(1) D(2) D(3) D(4) D(5) D(6) D(7)

C418 22n

2

n.m F

R418 3.3K C426 1n

Date

Sign & Name

Designer

02.04.11

D.S.JUNG

Checked

02.04.11

N.S.KIM

Section

C424 100n

C425 100n

Approved

LG issue

1

2

3

5

4

- 92 -

6

Notice NO.

Data

Name

7

Electronics Inc

Model

Sheet/Sheets 4/6

Drawing Name

AUDIO

Drawing No.

8

10. CIRCUIT DIAGRAM

2

1

3

6

5

4

7

VBAT C603

8

ANT600 ANT_PAD_LGX

C600 C601 C602

R600 18R

H_H_PWR GND2 H_L_PWR L_L_PWR GND1 L_H_PWR

GND4

1K

8 OUTN NC2 OUTP

DCS 2 GSM 4 NC1 GND1 1

GND5

3 8

R605 68R

U602 LDB32942M05D-429

6 5 4 3 2 1

C605 12p

7 6 5

1

R607 100R

C608 47p

R606 100R

PIN_DCS PIN_GSM

U601 PF08122B

47p

12p

6

L635

POUT_DCS 5

C609

POUT_GSM 4

SW600 MHC-173

L600 0R

1n N600 4.7N LDC15D190A0007A 47p

2

A

L601 12n

6 5 4 3

C606 n.m

5 2 3 4

8

4

8 10

7 6 1

C613 C610 1.2p n.m

C611 C612 1.5p n.m

GND2 3

6 2

7 14

R608 51R

VBAT

1

AFC R642 1K C679 12p

E

VCC CTL

R643 1M

R644 1.5K R645

C675 1n

C622

15p

27p C633 100n

C646

100n

C669

C668

C667

R625 1K

C645 7p

L603

L605 18N

100n 100n

C649

AN CAT

3p

R638 2.2K(1%)

C671 12n (3216)

C660

L606 18N

L608 3.3N

C639 n.m

BPF601 SAFSD942MCL0T00R00 L633 3.3p 4 3.3N 2 3.3p 6

D

C640 n.m

L609

C691 1.2n R634 9.76K(1%)

C658

1

C682 4.7p

3.9N R635 C670 1K 1.2n

U607 NC7WZ02

C674 1n (2012)

R641 390R(1%)

R674 680R

R675 4.7k

2

C684 n.m

C685 100n

TXRXSW LBSW HBSW

R648 2.2K R647 3.3N

L612 6.8N

HBSW

1

TXRXSW

2

LB_LP 1 0 1

LB_HP 0 0 1

HB_LP 1

HB_HP 0

1 0

1 0

C683 100n

R646 2.2K

1

C698 100n

3 D602 HVB387BWK

F Section

Date

Sign & Name

Designer

02.04.11

Y.M.CHO

Checked

02.04.11

D.H.KIM

Approved

n.m

LG 3

E

5

LBSW VREG3

0R

2

8 7

6

issue

1

R626 1K

6

1 3 5

C632 4.7p

R620 R621

R623 n.m

SAFSD1G84CB0T00R00 L632 2.7N 3.3N 4 2 2.7N

L602

D601 HVC369B

C681 4.7p

L611 6.8N

F

R676

3

3 4

TH601 22K_NTC R673 270k

RADIO_TEMP

1

BPF600

C678 n.m

TP610

R677

2

C

C662 3p

C673 5.6n (1608)

3

4

C628 1n

R624 620K

U629 SN74HC1GU04DCKR

3

1K

C686 12p

R636 2.7K(1%)

R622 120R

C643 7p

C642

C648 C657

C627 1n

D600 BAT15-099

C680 1n

2

4

13MHZ

OUT GND 2

5

RESET_RF QN QP IN IP

C672 1.2n (1608)

U606 VC-TCXO-208C

4

C637 39p

R617 51R

A1

VR3

C665 10n

4

R640 n.m

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

2

100n

1K

C664 2.2u (2012)

3 -ERR

100n

-SD

A2

XO_ENA

6

o M

TRF6150

CAT

R637

n.m

NR

i b

U604

C666

R633

RF_ENA

R679 n.m

OUT

IN

GND

5

R678 0R

R632 0R

1

h lc VAPC FILT DETD DETR DCSLNAN DCSLNAP VCC3 PCSMIXN PCSMIXP GNDLNAN VCC2 GSMLNAN GSMLNAP MAINVCO VCC1 VCC8

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

U605 ADP3330_2V85 2

100n

C623 100n

100n

C663 C661 2.2u (2012)

s ip

C635 4.7u P-CASE

C630 n.m

1 3 5

100n

C647 VBAT

D

C641

1n

1K 1K 1K

100n

1n

CLK DATA EN VR2B

R629 R630 R631

R619

C634 1K 1K

C638 1n

HB-SW TXRX-SW VCC10 MAINSPUP1 MAINCP VBAT2 VREG2 APC APCEN VR4IN CLK DATA EN AUXCP VCC9 CRF

R609 0R

C629 27P

R649 10R

100n PA_LEVEL PA_ON

R656 R657

R616 n.m

P-CASE

RESETZ QN QP IN IP VCC7 AUXVCOP AUXVCON RXMIXQP RXMIXQN RXMIXIP RXMIXIN TESTVCO DECRXMIX BIASREF BANDGAP

C692

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

C690 0.5p

13 12 11 9 5 3

B C626 4.7u

LB-SW VCC5 VREG3 VBAT3 R3 TXRXCP R2 MAINSPUP2 GNDTXCP VCC6 RXLOP RXLON VCC4 OMIXRF VBAT1 VREG1

C687 2.2u (2012)

C

DCS_TX GND1 EGSM_TX GND2 GND3 GND4 DCS_RX GND5 EGSM_RX GND6

1 7

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

C636 33u/6.3V A-CASE

2.2K 27p 27p

C615 12n (3216)

C625 1n (1608)

33R 1.2K

C624 2.2u (2012)

n.m

C619 1n

B

R615 C620 C621

R610 0R

VBAT

U603 SHS-M090B

VC1 VC2

C614 330p

C604 27p 1

ANT

PWR_SW DCS_SW GSM_SW VCC GND3 VT

10p

R604

VAPC VDD1 VCTL GND1 GND2 VDD2

8 9 10 11 12 13

TXRXSW HBSW LBSW VREG3

R603

470u

7 9 10

U600 ENFVZ4L07

R601 300R

2

A

R602 300R

4

5

- 93 -

6

Notice NO.

Data

Name

7

Electronics Inc

Model

Sheet/Sheets 6/6

Drawing Name

RF MAIN

Drawing No.

8

10. CIRCUIT DIAGRAM

10.2 RF Circuit 1

2

3

6

5

4

7

VBAT C603

8

ANT600 ANT_PAD_LGX

C600 C601 C602

R600 18R

PWR_SW DCS_SW GSM_SW VCC GND3 VT

H_H_PWR GND2 H_L_PWR L_L_PWR GND1 L_H_PWR

GND4

8 2 4

GND5

DCS GSM NC1

OUTN NC2 OUTP

GND1 1

GND2 3

3 8

R605 68R

U602 LDB32942M05D-429

6 5 4 3 2 1

C605 12p

7 6 5

1

R607 100R

R606 100R

C608 47p

PIN_DCS PIN_GSM

U601 PF08122B

47p

12p

6

L635

POUT_DCS 5

C609

POUT_GSM 4

SW600 MHC-173

L600 0R

1n N600 LDC15D190A0007A

4.7N 47p

2

A

L601 12n

6 5 4 3

C606 n.m

5 2 3 4

8

4

8 10

7 6 1

C613 C610 1.2p n.m

C611 C612 1.5p n.m

6 2

7 14

R608 51R

VBAT

U605 ADP3330_2V85

-SD

3 -ERR

R642 1K C679 12p

E

VCC CTL

R643 1M

R644 1.5K R645

C675 1n

C622 27p C633 100n

3

R623 n.m

R625 1K

BPF600 L602 L603

6

L605 18N

100n 100n

C649

AN CAT

3p

D601 HVC369B

R638 2.2K(1%)

C671 12n (3216)

C660

L606 18N

L608 3.3N

C639 n.m

BPF601 SAFSD942MCL0T00R00 L633 3.3p 4 3.3N 2 3.3p 6

D

C640 n.m

L609

C691 1.2n R634 9.76K(1%)

C658

1

3.9N R635 C670 1K 1.2n

U607 NC7WZ02

C674 1n (2012)

R641 390R(1%)

HBSW

1

TXRXSW

2

C681 4.7p

C682 4.7p

2

R647 3.3N R675 4.7k

C684 n.m

F

C685 100n

L612 6.8N

TXRXSW LBSW HBSW

R648 2.2K

TH601 22K_NTC R674 680R

6

LB_LP 1 0 1

LB_HP 0 0 1

HB_LP 1

HB_HP 0

1 0

1 0

C683 100n

R646 2.2K

1

C698 100n

3 D602 HVB387BWK

F Date

Sign & Name

R677

0R

Designer

02.04.11

Y.M.CHO

Checked

02.04.11

D.H.KIM

R676

n.m

Approved

Section

issue

2

3

E

5

LBSW VREG3

LG 1

8 7

3 4

L611 6.8N

R626 1K

SAFSD1G84CB0T00R00 L632 2.7N 3.3N 4 2 2.7N 1 3 5

C632 4.7p

R619

1

C

100n

C678 n.m

2

C643 7p

C662 3p

C673 5.6n (1608)

3

TP610

R673 270k

RADIO_TEMP

R636 2.7K(1%)

4

C628 1n

R624 620K

U629 SN74HC1GU04DCKR

3

1K

C686 12p

C648 C657

C627 1n

C680 1n

2

4

13MHZ

OUT GND 2

5

RESET_RF QN QP IN IP

U606 VC-TCXO-208C

4 1

AFC

C672 1.2n (1608)

4

R640 n.m

VR3

C646

R617 51R

A1

6

R622 120R

C645 7p

C669

1K

C665 10n

C668

n.m

C664 2.2u (2012)

C637 39p

C630 n.m

D600 BAT15-099

15p

2

100n

XO_ENA

R633 R637

NR

100n

RF_ENA

1

C642

OUT

IN

A2

5

R632 0R

R679 n.m

C666

2

R678 0R

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

100n

C663 C661 2.2u (2012)

GND

D

100n

C623 100n

C629 27P

1 3 5

C647 VBAT

o M

TRF6150

CAT

1K 1K 1K

U604

h lc P-CASE

i b C667

R629 R630 R631

C635 4.7u

VAPC FILT DETD DETR DCSLNAN DCSLNAP VCC3 PCSMIXN PCSMIXP GNDLNAN VCC2 GSMLNAN GSMLNAP MAINVCO VCC1 VCC8

1n

CLK DATA EN VR2B

100n

HB-SW TXRX-SW VCC10 MAINSPUP1 MAINCP VBAT2 VREG2 APC APCEN VR4IN CLK DATA EN AUXCP VCC9 CRF

1n

1K 1K

R620 R621

C634 R656 R657

R616 n.m

R649 10R

100n C641 PA_LEVEL PA_ON

100n

1n

s ip

P-CASE

RESETZ QN QP IN IP VCC7 AUXVCOP AUXVCON RXMIXQP RXMIXQN RXMIXIP RXMIXIN TESTVCO DECRXMIX BIASREF BANDGAP

C638 C692

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

C690 0.5p

R609 0R

13 12 11 9 5 3

B

LB-SW VCC5 VREG3 VBAT3 R3 TXRXCP R2 MAINSPUP2 GNDTXCP VCC6 RXLOP RXLON VCC4 OMIXRF VBAT1 VREG1

C687 2.2u (2012)

C

DCS_TX GND1 EGSM_TX GND2 GND3 GND4 DCS_RX GND5 EGSM_RX GND6

1 7

C626 4.7u

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

C636 33u/6.3V A-CASE

2.2K 27p 27p

C615 12n (3216)

C625 1n (1608)

33R 1.2K

C624 2.2u (2012)

n.m

C619 1n

B

R615 C620 C621

R610 0R

VBAT

U603 SHS-M090B

VC1 VC2

C614 330p

C604 27p 1

ANT

TXRXSW HBSW LBSW VREG3

10p 1K

VAPC VDD1 VCTL GND1 GND2 VDD2

8 9 10 11 12 13

R603 R604

470u

7 9 10

U600 ENFVZ4L07

R601 300R

2

A

R602 300R

4

5

- 94 -

6

Notice NO.

Data

Name

7

Electronics Inc

Model

Sheet/Sheets 6/6

Drawing Name

RF MAIN

Drawing No.

8