Alcatel 1660 SM техническое руководство

Citation preview

Technical Handbook

Alcatel 1660SM STM 16 Multiservice Metro Node

1660SM Rel. 4.4

3AL 91668 AAAA Ed.02

3AL 91668 AAAA Ed.02

1AA 00014 0004 (9007) A4 – ALICE 04.10

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

1660SM REL.4.4 TECHNICAL HANDBOOK

TABLE OF CONTENTS LIST OF FIGURES AND TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7

HANDBOOK GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15

1 HANDBOOK STRUCTURE AND CONFIGURATION CHECK . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 General information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Handbook applicability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Product-release handbooks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Handbook Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 Handbook Configuration Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.1 List of the editions and of modified parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.2 Notes on Ed.01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.3 Notes on Ed.02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

17 17 17 18 24 25 25 25 25

2 COMPLIANCE WITH EUROPEAN NORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Electromagnetic Compatibility (EMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

27 27 28

3 SAFETY NORMS AND LABELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 First aid for electric shock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Safety Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1 General Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 Labels Indicating Danger, Forbiddance, Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.3 Dangerous Electrical Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.4 Harmful Optical Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.5 Risks of Explosions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.6 Moving Mechanical Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.7 Heat–radiating Mechanical Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.8 Specific safety rules in this handbook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

29 29 31 31 32 33 34 36 36 37 38

4 OTHER NORMS AND LABELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Electromagnetic Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.1 General Norms – Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.2 General Norms – Turn–up & Commissioning, Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.3 General Norms – Maintenance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Electrostatic Dischargers (ESD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

39 39 39 40 40 41

02

050411

01

041021

ED

DATE

ECR 23080

CHANGE NOTE

J. MIR ITAVE S. MAGGIO – C. FAVERO J. MIR ITAVE S. MAGGIO – C. FAVERO

P. GHELFI ITAVE

APPRAISAL AUTHORITY

ORIGINATOR

P. GHELFI ITAVE

1660SM REL. 4.4 TECHNICAL HANDBOOK

ED

02 3AL 91668 AA AA 636

1 / 636

1AA 00014 0004 (9007) A4 – ALICE 04.10

42 42

5 LIST OF ABBREVIATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

53

6 GENERAL ON ALCATEL CUSTOMER DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 Products, product-releases, versions and Customer Documentation . . . . . . . . . . . . . . 6.2 Handbook supply to Customers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 Aims of standard Customer Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4 Handbook Updating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.1 Changes introduced in the same product-release (same handbook P/N) . . . . . . . . . . . . 6.4.2 Changes due to new product version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 Customer documentation on CD–ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5.1 Contents, creation and production of a CD–ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5.2 Use of the CD–ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5.3 CD–ROM identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5.4 CD–ROM updating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

59 59 59 59 60 60 60 61 61 62 62 62

DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

63

1 GENERAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Introduction to the equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Insertion of the equipment into the network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.2 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.3 SDH / CWDM integration in “ring” network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.4 SDH / CWDM integration in “linear” network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.5 Network protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

65 65 73 73 74 77 81 83

2 PHYSICAL CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Equipment front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.1 1660SM Shelf front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.2 19” Fans subrack front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Part list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1 Equipment Shelf part list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.2 Fans Subrack 19” part list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.3 Explanatory notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Relationship between Port Card and Access Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Units front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.1 Port cards front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.2 Access cards front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.3 FAN subrack cover front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

85 86 86 87 88 89 104 105 110 120 121 145 165

3 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Connections sub–system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 SIGNAL MANAGEMENT SUB–SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1 Signal management referred to ”G.783 1994” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.2 SIGNAL MANAGEMENT referred to ”G. 783” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 ISA (Integrated Service Adapter) introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 ISA – ATM management sub–system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.1 ATM ( Asynchronous Transfer Mode) basic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.2 ATM in1660SM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 ISA – PR_EA (MPLS) sub–system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.1 PR_EA (MPLS) generalities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

167 167 188 190 190 196 213 215 215 219 224 224

ED

02 3AL 91668 AA AA 636

2 / 636

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

4.3 Suggestions, notes and cautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 Labels affixed to the Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

231 235 235 236 253 253 255 262 264 270 270 273 282 289 290 292 293 296 298 304 306 308 310 311 323 325 327 332 336 339 342 351 353 355 358 359 367 370

4 UNIT DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 21 x 2 Mbit/s access card (A21E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 3 X 34 Mbit/s access card (A3E3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 3 X 45 Mbit/s access card (A3T3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 2 x 140/STM–1 O/E adapter (A2S1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 4 x STM–1 electrical access card (A4ES1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6 High Speed protection access card (HPROT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7 Ethernet access card (ETH–ATX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8 Gigabit Ethernet access Card (GETH–AG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.9 Fast Ethernet Access Card (16 FEA–PR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.10 Fast Ethernet Access Card (2 GBA–PR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.11 Optical booster (BST10, BST15, BST17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.12 Optical 2.5 Gbit/s Preamplifier (PR16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.13 Electrical module (ICMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.14 STM–1 optical modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

373 373 375 377 379 381 383 385 387 390 393 396 400 407 409

1AA 00014 0004 (9007) A4 – ALICE 04.10

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

3.6.2 PR_EA (MPLS) service in 1660SM equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7 ISA – PR Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.1 PR Generalities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.2 PR in 1660SM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8 ISA – ETHERNET management sub–system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.1 Generalities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.2 Main features description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.3 Technical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.4 Ethernet boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9 ISA – ES (Ethernet Switch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9.2 ISA–ES series modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10 4 x ANY HOST C subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.11 Coarse WDM sub–system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.11.1 Equipment facilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.11.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.11.3 “Ring” node functional scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.11.4 “Terminal” node functional scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.11.5 Optical span design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.12 Controller sub–system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.12.1 Network management interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.12.2 ATM/IP/MPLS over SDH Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13 Protection sub–system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.1 EPS Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.2 MS linear trail Protection (1+1 linear APS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.3 MS linear trail Protection (1:N linear dual–ended APS) . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.4 SNCP (Sub–Network Connection Protection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.5 Drop & Continue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.6 Collapsed dual node ring interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.7 Collapsed single node ring interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.8 MS–SPRING protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.14 Synchronizing sub–system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.15 Auxiliary and DCC sub–system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.16 Power supply sub–system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.17 Remote inventory Sub–system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.18 Frames Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.18.1 Synchronous 2048 Kb/s frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.18.2 ATM cells mapping into SDH/PDH frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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1AA 00014 0004 (9007) A4 – ALICE 04.10

STM–4 optical modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gigabit Ethernet optical modules (1000B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 x ANY plug–in modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 x 2 Mbit/s port card (P63E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 x 2 Mbit/s / G703 / ISDN–PRA port card (P63E1N–M4) . . . . . . . . . . . . . . . . . . . . . . . . 3 x 34/45 Mbit/s port card (P3E3T3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 x STM–1 electrical/optical port card (P4S1N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 X 140/STM1 switchable O/E port card (P4E4N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 x STM–1 port (P4ES1N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 x OC3 AU3/TU3 CONVERSION port (P4OC3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STM–4 optical ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 x STM–4 optical port (P4S4N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STM–16 optical port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISA – ATM MATRIX 4X4 (ATM4X4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISA – ATM MATRIX 4X4 ENHANCED (ATM4X4D3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISA – ATM MATRIX 4X4 ENHANCED (ATM4X4V2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISA – ATM MATRIX 8X8 (ATM8X8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISA–Packet Ring Edge Aggregator Unit (PREA1GBE, PREA4ETH) . . . . . . . . . . . . . . . ISA – Packet Ring unit (ISA–PR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISA – Ethernet/Fast Ethernet port (ETH–MB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISA –Giga Ethernet Main Board (GETH–MB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISA– Ethernet switch (ES1–8FE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISA– Ethernet switch (ES1–8FX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISA– Ethernet switch (ES4–8FE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISA ES–16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 X ANY HOST C card (4XANYC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COADM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COADM2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COMDX8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2xCH Transponder SFP without optics (COWLA2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EQUICO card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Matrix card (MATRIXN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CONGI card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SERVICE card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FAN UNIT FOR FAN SHELF 19” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

410 411 412 413 416 421 424 429 436 441 449 454 459 465 472 472 478 485 492 496 500 504 508 508 513 518 523 525 527 529 534 537 541 546 552

5 TECHNICAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.1 Optical Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.2 Electrical Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Electrical interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.1 21 X 2 Mbit/s 75 Ohm electrical characteristics (A21E1) . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.2 21 X 2 Mbit/s 120 Ohm electrical characteristics (A21E1) . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.3 21 X 2 Mbit/s 120 Ohm K20 electrical characteristics (A21E1) . . . . . . . . . . . . . . . . . . . . . 5.2.4 3 X 34 Mbit/s electrical characteristics (A3E3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.5 3 X 45 Mbit/s electrical characteristics (A3T3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.6 STM–1 electrical characteristics (A4 ES1 and ICMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.7 140 Mbit/s electrical characteristics (ICMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.8 Engineering Order Wire characteristics (SERVICE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.9 AUX channels characteristics (SERVICE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 ATM interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.1 ATM matrix 4x4 switching capability (ATM4X4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.2 ATM matrix 4x4V2 switching capability (ATM4X4V2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.3 ATM matrix 4x4 D3 switching capability (ATM4X4D3) . . . . . . . . . . . . . . . . . . . . . . . . . . . .

557 557 561 565 566 566 566 566 566 567 567 567 568 568 570 570 571 572

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4.15 4.16 4.17 4.18 4.19 4.20 4.21 4.22 4.23 4.24 4.25 4.26 4.27 4.28 4.29 4.30 4.31 4.32 4.33 4.34 4.35 4.36 4.37 4.38 4.39 4.40 4.41 4.42 4.43 4.44 4.45 4.46 4.47 4.48 4.49

573 574 575 575 575 576 577 577 577 578 579 580 581 582 583 583 584 585 586 587 588 589 590 602 603 603 604 605 606 606 608 608 611 612 612 614 616 618

MAINTENANCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

619

6 MAINTENANCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 General safety rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 General rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 Maintenance Aspects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4 Instruments And Accessories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 Routine Maintenance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5.1 Routine maintenance every three months . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5.2 Routine maintenance every year . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5.3 Routine Maintenance every five year . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6 Corrective Maintenance (Trouble/Shooting) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6.1 Fan unit for fan shelf 19”substitution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7 Set of spare parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7.1 Suggested Spare Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

621 621 622 622 622 623 623 624 625 625 625 626 626

1AA 00014 0004 (9007) A4 – ALICE 04.10

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

5.3.4 ATM matrix 8x8 switching capability (ATM8X8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4 PR_EA characteristics and MPLS data traffic management (PREA4ETH, PREA1GBE) 5.5 PR characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.1 ISA–PR port card interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.2 16FEA–PR access card interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.3 2GBA–PR access card interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6 ETHERNET characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.1 Ethernet 10/100Base–T interface characteristics (ETH–MB + ETH–ATX) . . . . . . . . . . . 5.6.2 Ethernet switch port card characteristics (ES1–8FE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.3 Ethernet switch port card characteristics (ES1–8FX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.4 Ethernet switch port card characteristics (ES4–8FE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.5 Ethernet switch port card characteristics (ISA ES–16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.6 Access Card Gigabit Ethernet interfaces characteristics (GETH–AG) . . . . . . . . . . . . . . 5.6.7 Gigabit Ethernet ports card interfaces (GETH–MB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7 4 x ANY clients characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.1 Gigabit Ethernet LX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.2 Gigabit Ethernet SX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.3 Fiber Channel 100–SM–LL–I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.4 Fiber Channel 100–M5–SL–I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.5 Fast Ethernet (100BASE FX)/FDDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.6 ESCON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.7 Digital Video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8 Optical interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8.1 Example of a link using 1660SM with L–16.2 JE2 Port and 15 dBm Booster . . . . . . . . 5.9 Coarse WDM subsystem units characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.9.1 COADM–1 Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.9.2 COADM–2 Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.9.3 MUX/DEMUX 8 Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.9.4 2 Channels TRANSPONDER SFP without optical modulle . . . . . . . . . . . . . . . . . . . . . . . . 5.9.5 CWDM optical PLUGIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.10 Power Supply characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.11 Alarm Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.12 Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.13 Environmental conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.13.1 Climatic for operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.13.2 Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.13.3 Transportation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.13.4 EMI/EMC condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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626 626 626

HARDWARE SETTING DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

629

UNITS DOCUMENTATION LIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

631

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All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

6.7.2 General rules on spare parts management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7.3 Particular rules on spare parts management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8 Repair Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1AA 00014 0004 (9007) A4 – ALICE 04.10

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

LIST OF FIGURES AND TABLES FIGURES Figure 1. Subrack label . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2. Subrack label . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 3. Subrack label . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 4. Labels on units with standard cover plate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 5. Modules label . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 6. Internal label for Printed Board Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 7. Back panels internal label . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 8. Label specifying item not on catalogue (P/N. and serial number) . . . . . . . . . . . . . . . . . . . . Figure 9. Label specifying item on catalogue (P/N. and serial number) . . . . . . . . . . . . . . . . . . . . . . . Figure 10. Item identification labels – item on catalog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 11. Label identifying the equipment (example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 12. Example of SDH/DATA/CWDM integration in “metro area” . . . . . . . . . . . . . . . . . . . . . . . . Figure 13. Example of ATM Transport management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 14. ISA–PR Deployment Scenario . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 15. Ethernet service application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 16. Terminal multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 17. Add/Drop Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 18. ”HUB” STM–1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 19. Point–to–point links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 20. Linear drop–insert . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 21. Ring structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 22. Meshed topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 23. SDH/CWDM integration in “ring” with COADM units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 24. SDH/CWDM integration in “ring” with COADM unit: detailed view . . . . . . . . . . . . . . . . . . Figure 25. SDH/CWDM integration in “ring” with MUX/DEMUX unit . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 26. SDH/CWDM integration in “ring” with MUX/DEMUX unit: detailed view . . . . . . . . . . . . . . Figure 27. SDH/CWDM integration in “linear” network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 28. SDH/CWDM integration in “linear” network (MUX/DEMUX): detailed view . . . . . . . . . . . Figure 29. SDH/CWDM integration in “linear” network (COADM unit): detailed view . . . . . . . . . . . . Figure 30. 1660SM units positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 31. 19” Fans subrack unit slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 32. PDH, SDH electrical ports front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 33. 4 x STM–1, 4 x OC3 port : front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 34. STM–4 optical port front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 35. 4 x STM–4 port card – front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 36. STM–16 optical front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 37. I–16 PORT SFF (intra–office) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 38. STM–16 SFP port optical front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 39. ATM 4X4, ATM 4X4V2 and ATM4X4D3 cards – front view . . . . . . . . . . . . . . . . . . . . . . . . Figure 40. ATM 8X8 card – front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 41. ISA – Ethernet port front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 42. ISA– Gigabit ETHERNET board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 43. ISA – ES4–8FE port front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 44. ISA – ES1–8FE port front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 45. ISA ES–8FX front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 46. ISA ES–16 front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 47. ISA– PRE_EA Matrix 4x Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 48. ISA– PRE_EA Matrix 1 x GB–ETH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 49. ISA– PR Matrix 4x4STM4 PLUG–IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 50. COWLA2 front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ED

43 44 45 46 47 48 49 50 50 51 51 69 70 71 72 73 73 74 74 75 75 76 77 78 79 80 81 81 82 86 87 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139

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140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 167 168 168 178 179 180 181 182 183 184 185 186 187 189 193 194 195 206 208 210 212 214 215 216 217 218 222 223

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All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

Figure 51. 4xANY Host C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 52. Matrix card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 53. Equipment controller EQUICO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 54. Control and General interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 55. SERVICE interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 56. 21 x 2 Mbit/s 75 ohm access card 1.0/2.3 connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 57. 21 X 2 Mbit/s 120 Ohm access card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 58. 3 X 34 Mbit/s 75 ohm access card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 59. 3 X 45 Mbit/s 75 ohm access card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 60. 4 X STM–1 access card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 61. High Speed protection – front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 62. 2 x 140/STM–1 O/E adapter (access card)– front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 63. ISA – Ethernet access front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 64. ISA – Gigabit Ethernet access card front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 65. ISA PR 2XGBE 1000 access card front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 66. ISA PR16XETH 10/100 access card front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 67. COADM1 front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 68. COADM2 front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 69. COMDX8 front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 70. STM–1/STM–4 optical module front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 71. STM–1 or 140 Mbit/s electrical module front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 72. Relationship between SFP modules and housing boards . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 73. 4XANY plug–in module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 74. Optical Booster card front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 75. PREAMPLIFIER 2.5 GB/S front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 76. 19” Fans subrack cover front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 77. LOI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 78. HOI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 79. TTF and HOA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 80. 1660SM Block diagram – (SDH and PDH boards) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 81. 1660SM Block diagram – (SDH and PDH boards) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 82. 1660SM Block diagram – (SONET and 4xANY HOSTC boards) . . . . . . . . . . . . . . . . . . . Figure 83. 1660SM Block diagram – (CWDM boards) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 84. 1660SM Block diagram – (CWDM boards) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 85. 1660SM Block diagram – ( Common units and ISA boards) . . . . . . . . . . . . . . . . . . . . . . . Figure 86. 1660SM Block diagram – (ISA boards) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 87. 1660SM Block diagram – (ISA – ES boards) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 88. 1660SM Block diagram – (ISA – ETHERNET boards) . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 89. 1660SM Block diagram – (ISA–PR board) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 90. High Order/Low Order connections for 1660SM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 91. SDH signal management block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 92. 2Mbit/s, 34 Mbit/s, 45 Mbit/s signal management block diagram . . . . . . . . . . . . . . . . . . . Figure 93. 140Mbit/s signal management block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 94. 1660SM Block Diagram: signal management (SDH port) . . . . . . . . . . . . . . . . . . . . . . . . . Figure 95. 1660SM Block Diagram: signal management ( 2Mbit/s PDH ports) . . . . . . . . . . . . . . . . Figure 96. 1660SM Block Diagram: signal management ( 34 Mbit/s and 45 Mbit/s PDH ports) . . Figure 97. 1660SM Block Diagram: signal management ( 140 Mbit/s PDH ports) . . . . . . . . . . . . . Figure 98. Example of technology convergency with ISA boards in OMSN . . . . . . . . . . . . . . . . . . . . Figure 99. Relationship between the VC, the VP and the TP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 100. Basic format of an ATM cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 101. ATM network interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 102. UNI and NNI ATM cell header and payload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 103. 1660SM with ATM Matrix architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 104. Leased line service versus Data transport service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1AA 00014 0004 (9007) A4 – ALICE 04.10

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

Figure 105. MPLS subsystem, protocol stacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 106. Framing for MPLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 107. MPLS label format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 108. PPP frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 109. HDLC frame with PPP encapsulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 110. Ethernet MAC 802.3 frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 111. Ethernet “Tagged” MAC 802.3 frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 112. Ethernet frame format for “MPLS over Ethernet” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 113. MPLS Tunnelling Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 114. Generic MPLS aggregation scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 115. MPLS subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 116. ISA–PR Sub–System Architecture (Overlay Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 117. ISA–PR Sub–System Architecture (Independent Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 118. Traffic flow and processing in 1660 SM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 119. ISA–PR Policing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 120. ISA–PR Traffic Management Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 121. Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 122. Bottlenecks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 123. RPR protection mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 124. Packet protection (and QoS assurance) in multiring network : MPLS over RPR . . . . . Figure 125. Customer Edge Dual Homing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 126. Relationship with other ISA Cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 127. Example of an Ethernet stream transport through a SDH network . . . . . . . . . . . . . . . . . Figure 128. LAN to LAN service block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 129. GFP frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 130. GFP encapsulation of the MAC frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 131. Flow control mechanism: input control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 132. Flow control mechanism: output control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 133. Flow control mechanism: External control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 134. Messages dispatching via Virtual Concatenation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 135. Messages dispatching via Packet Concatenation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 136. Board Ethernet 10/100: System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 137. Example of Ethernet service application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 138. Gigabit Ethernet System architecture: Gigabit access with Fast Ethernet board . . . . . Figure 139. Gigabit Ethernet System architecture:Gigabit Ethernet main board . . . . . . . . . . . . . . . . Figure 140. Ethernet Private Line service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 141. Ethernet Virtual Private Line service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 142. Ethernet Virtual LAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 143. Broadband Access service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 144. ISA–ES access port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 145. Traffic flow and processing in ISA–ES series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 146. ISA–ES series ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 147. ISA–ES series traffic parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 148. WRED Congestion avoidance mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 149. ISA–ES series operational modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 150. Ethernet Multiplexing Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 151. Multiple customers on a single NNI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 152. 4xANY HOST–C: Client allocation grid in “enhanced” slot . . . . . . . . . . . . . . . . . . . . . . . . Figure 153. 4xANY HOST–C: module configuration in “enhanced” slot . . . . . . . . . . . . . . . . . . . . . . . Figure 154. Client allocation grid in “HS slots” with GE/FC/FICON . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 155. Client allocation grid in “HS slots” with FE/FDDI/ESCON/DV . . . . . . . . . . . . . . . . . . . . . Figure 156. module configuration in “HS” slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 157. COADM functionality: example of equipment shelf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 158. MUX/DEMUX functionality: example of shelf equipment . . . . . . . . . . . . . . . . . . . . . . . . .

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Figure 159. 1660SM signal flow diagram with WDM application . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 160. 1660SM (WDM application) ’ring’ node functional scheme (1) . . . . . . . . . . . . . . . . . . . . Figure 161. 1660SM (WDM application) ’ring’ node functional scheme (2) . . . . . . . . . . . . . . . . . . . . Figure 162. 1660SM (WDM application) ’ring’ node functional scheme (3) . . . . . . . . . . . . . . . . . . . . Figure 163. 1660SM (WDM application) ’ring’ node functional scheme (4) . . . . . . . . . . . . . . . . . . . . Figure 164. 1660SM (WDM application)’end’ node functional scheme (Mux/Demux) . . . . . . . . . . . Figure 165. 1660SM (WDM application) ’end’ node functional scheme (COADM) . . . . . . . . . . . . . . Figure 166. Passive optical operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 167. COMDX8 insertion loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 168. COADM2 insertion loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 169. COADM1 insertion loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 170. 1660SM Control Sub–system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 171. 1660SM general management architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 172. Connection Mode for TMN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 173. Protocol stack for SDH/ATM management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 174. Example of management of a network with SDH and ATM/IP/MPLS traffic . . . . . . . . . Figure 175. Low Speed Link Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 176. Example of EPS protection schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 177. High Speed connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 178. Examples of ATM MATRIX EPS protection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 179. Messages exchanged between the EC and the ISA–ATM boards in EPS group . . . . . Figure 180. Examples of MPLS (PR_EA..) boards protection scheme . . . . . . . . . . . . . . . . . . . . . . . . Figure 181. Messages exchanged between EC and ISA–PR_EA Matrix... boards in EPS group . Figure 182. Linear 1+1 single ended protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 183. Linear 1+1 dual ended protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 184. MSP Linear 1:N Dual–Ended protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 185. Typical ring network with SNCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 186. Failure examples in SNCP ring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 187. SNCP example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 188. Drop and Continue D/C A INS A (called “Normal” on C.T.) . . . . . . . . . . . . . . . . . . . . . . . Figure 189. Drop and Continue D/C A INS B (called “Inverse” on C.T.) . . . . . . . . . . . . . . . . . . . . . . . Figure 190. Drop and Continue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 191. Drop and Continue – 1st failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 192. Drop and Continue – 2nd failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 193. Collapsed dual node interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 194. Collapsed dual node interconnection – 1st failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 195. Collapsed dual node interconnection – 2nd failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 196. Collapsed single node ring interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 197. Collapsed single node ring interconnection –1st failure . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 198. Collapsed single node ring interconnection –2nd failure . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 199. 2F MS SPRING Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 200. Effect of a BRIDGE “B side” operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 201. Effect of a BRIDGE “A side” operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 202. Effect of SWITCH “B side” operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 203. Effect of SWITCH “A side” operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 204. Line break recovering operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 205. 2F MS–SPRING example of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 206. Squelching on isolated Node connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 207. MS SPRING Drop and Continue, Insert Continues (protected) . . . . . . . . . . . . . . . . . . . Figure 208. Synchronization function : block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 209. AUX and DCC management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 210. 1660SM –Input power stage and distributed power supply . . . . . . . . . . . . . . . . . . . . . . . Figure 211. Remote Inventory sub–system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 212. 1660SM: SDH multiplexing structure and AU–3/TU–3 conversion . . . . . . . . . . . . . . . . .

1AA 00014 0004 (9007) A4 – ALICE 04.10

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

Figure 213. VC–12 Structure (asynchronous mapping of 2048 Kbit/s) . . . . . . . . . . . . . . . . . . . . . . . . Figure 214. TU–12 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 215. VC–3 structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 216. TU–3 structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 217. VC–4 Structure and POH byte contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 218. STM–1 structure and SOH byte contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 219. STM–4 structure and SOH byte contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 220. Structure of STM–16 and SOH bytes contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 221. Synchronous 2048 Kb/s signal: basic frame overhead . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 222. Synchronous 2048 Kb/s signal: CRC–4 multiframe overhead . . . . . . . . . . . . . . . . . . . . . Figure 223. Mapping of ATM cells into VC12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 224. Mapping of ATM cells into VC4/VC3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 225. Mapping of ATM cells into 2048 kb/s frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 226. Mapping of ATM cells into 34368 kb/s frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 227. 21 x 2 access card – Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 228. 3 x 34 access card block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 229. 3 x 45 access card block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 230. 2 x 140/STM–1 O/E adapter (access card) block diagram . . . . . . . . . . . . . . . . . . . . . . . Figure 231. 4 x STM–1 access card block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 232. HPROT access card block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 233. Ethernet Access –Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 234. Gigabit Ethernet Access card –Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 235. 16FEA–PR Card Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 236. 2GBA–PR Card Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 237. BSTxx – optical block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 238. BSTxx – card block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 239. PR16 optical path and control signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 240. PR16 card block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 241. STM–1 Electrical module –block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 242. STM–1 Optical module – block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 243. STM–4 optical module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 244. Gigabit Ethernet optical module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 245. 63 x 2 Mbit/s card – Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 246. 63 x 2 Mbit/s G.703/ISDN–PRA, Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 247. Functional Diagram of the NT ISDN–PRA block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 248. 3x34/45 port card –Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 249. 4 x STM–1 Electrical/Optical port block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 250. 4 x 140/STM–1 Electrical / Optical port block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 251. Mapper /Demapper 140–PDH / 155–STM1 block diagram . . . . . . . . . . . . . . . . . . . . . . . Figure 252. 4 x STM–1 Electrical port block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 253. 4 x OC3 AU3/TU3 conversion port(P40C3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 254. AU3/TU3 conversion block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 255. STM–4 –block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 256. 4xSTM–4 optical port block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 257. STM–16 optical port block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 258. ATM 4X4 card – Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 259. ATM4X4V2 and ATM4X4D3 card – Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 260. ATM 8X8 card – Block diagram part A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 261. ATM 8X8 card – Block diagram part B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 262. MPLS+4FE Unit (PREA4ETH) – Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 263. MPLS+1GbE Unit (PREA1GBE) – Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 264. PR unit functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 265. ETHERNET port (ETH–MB) – Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 266. Gigabit Ethernet Unit – Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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507 512 517 522 524 526 528 533 536 540 545 551 554 555 613 615 627

TABLES Table 1. Handbooks related to the specific product hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 2. Handbooks related to the METRO OMSN specific product SW management and local product control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 3. Handbooks related to ATM specific product SW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 4. Handbooks related to PR_EA specific product SW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 5. Handbooks related to PR specific product SW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 6. Handbooks related to ISA ES specific product SW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 7. Handbooks common to Alcatel Network Elements using 1320CT platform . . . . . . . . . . . . 21 Table 8. Optional handbooks common to 16xxSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 9. Documentation on CD–ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 10. Handbook configuration check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 11. IEC 950 –Table 16: Overtemperature limits, Part 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 12. Label references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 13. List of Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 14. Network application versus configuration modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Table 15. Main part list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Table 16. Accessories list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Table 17. Fans Subrack 19” part list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Table 18. Explanatory notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Table 19. Relationship between P63E1, P63E1N–M4 (63 X 2 Mbit/s unit) port card and A21E1 access card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Table 20. Relationship between P3E3T3 (3X34/45 Mbit/s Switchable unit) port card and A3E3 access card (3X34 Mbit/s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Table 21. Relationship between P3E3T3 (3X34/45 Mbit/s Switchable unit) port card and A3T3 access card (3X45 Mbit/s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Table 22. Relationship between P4S1N, P4E4N, P4OC3 port card and A2S1 access card . . . . 113 Table 23. Relationship between P4ES1N (4xSTM–1 Electrical) port card and A4ES1 access card. 114 Table 24. Relationship between ETH–MB (11x10/100 Mb/s Ethernet) port card and ETH–ATX access card. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Table 25. Relationship between ETH–MB (10/100Mb) port card and GETH–AG (1.25 Gb/s) access card. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Table 26. Relationship between ISA ES–16 port card and and ETH–ATX access card. . . . . . . . . . 117 Table 27. Relationship between ISA ES–16 port card and and GETH–AG access card. . . . . . . . . . 118 Table 28. Relationship between ISA–PR port card and 16FEA–PR or 2GBA–PR access cards. . . 119 Table 29. Interfaces acceding to the MPLS functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

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All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

Figure 267. ISA ES1–8FE block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 268. ISA ES4–8FE block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 269. ISA ES16 unit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 270. 4 x ANY HOST C card block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 271. COADM1 unit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 272. COADM2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 273. MUX/DEMUX8 (COMDX8) block diagram and LOS detection in ’passive’ boards . . . Figure 274. 2xCH Transponder SFP Without optics COWLA2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 275. 1660SM EQUICO Card Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 276. MATRIX card block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 277. CONGI – Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 278. SERVICE block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 279. Fans shelf 19” general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 280. Fans unit for fan shelf 19” block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 281. Climatogram for Class 3.2 : Partly temperature controlled locations . . . . . . . . . . . . . . . Figure 282. Climatogram for Class 1.2: not temperature controlled storage location . . . . . . . . . . . . Figure 283. Repair form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1AA 00014 0004 (9007) A4 – ALICE 04.10

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

Table 30. Sub–systems & involved cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Table 31. High Order/Low Order connections for 1660SM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 Table 32. ATM transport network layered model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Table 33. ATM traffic contracts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 Table 34. MPLS layer stack over SDH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 Table 35. MPLS layer stack over ETHERNET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 Table 36. Interfaces acceding to the MPLS functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 Table 37. Relationship between 4xANY optical modules and client type . . . . . . . . . . . . . . . . . . . . . . 282 Table 38. 4xANY HOST C client type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 Table 39. Modules configuration in “Enhanced HS” slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 Table 40. Modules configuration in “HS” slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 Table 41. CWDM channels grid supported by 1660SM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 Table 42. Boards insertion loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 Table 43. Fiber technical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 Table 44. Optical transceiver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 Table 45. MSP protection schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 Table 46. Example of SNCP protected groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 Table 47. 16FEA–PR card LEDs designation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392 Table 48. 16FEA–PR interface LED designation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392 Table 49. 2GBA–PR card LED designation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 Table 50. 2GBA–PR interface LED designation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 Table 51. PR unit LED designation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494 Table 52. CONGI A and CONGI B interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541 Table 53. Remote alarm provided by the AND/OR block available on CONGI in slot 10 . . . . . . . . . 542 Table 54. Remote alarm provided by the AND/OR block available on CONGI in slot 12 . . . . . . . . . 543 Table 55. Rack lamps signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543 Table 56. L1, L2 LEDs status for selective call . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547 Table 57. L1, L2 LEDs status for omnibus call . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547 Table 58. Hazard level classification of different optical interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561 Table 59. ATM4X4 board: configurable TPs type and max, number . . . . . . . . . . . . . . . . . . . . . . . . . . 570 Table 60. ATM4X4V2 board: configurable TPs type and max, number . . . . . . . . . . . . . . . . . . . . . . . . 571 Table 61. ATM4X4D3 board: configurable TPs type and max, number . . . . . . . . . . . . . . . . . . . . . . . . 572 Table 62. ATM8X8 board: configurable TPs type and max, number . . . . . . . . . . . . . . . . . . . . . . . . . . 573 Table 63. Parameters specified for STM–1 Optical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591 Table 64. Parameters specified for STM–4 Optical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593 Table 65. Parameters specified for SFP STM–4 Optical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594 Table 66. STM–16 Optical interfaces (Single Channel) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595 Table 67. STM–16 Optical interfaces (Multi Channel) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597 Table 68. Parameters specified for 1000B–SX Optical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598 Table 69. Parameters specified for 1000B–LX Optical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599 Table 70. Parameters specified for 1000B–ZX Optical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600 Table 71. Parameters specified for Optical Booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601 Table 72. Relation between Alarm severity terminology displayed on C.T./O.S. and alarm severity terminology used for the EQUICO leds and CONGI remote alarm connector pins. . . . . . . . . . . . . . . 609 Table 73. Transportation climatic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617 Table 74. Example of correspondence between CS and ’suffix + ICS’ . . . . . . . . . . . . . . . . . . . . . . . . 631 Table 75. Hardware presetting documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634

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1AA 00014 0004 (9007) A4 – ALICE 04.10

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1AA 00014 0004 (9007) A4 – ALICE 04.10

HANDBOOK GUIDE

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1AA 00014 0004 (9007) A4 – ALICE 04.10

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All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

1 HANDBOOK STRUCTURE AND CONFIGURATION CHECK 1.1 General information WARNING ALCATEL makes no warranty of any kind with regards to this manual, and specifically disclaims the implied warranties of merchantability and fitness for a particular purpose. ALCATEL will not be liable for errors contained herein or for damages, whether direct, indirect, consequential, incidental, or special, in connection with the furnishing, performance, or use of this material. NOTICE The product specification and/or performance levels contained in this document are for information purposes only and are subject to change without notice. They do not represent any obligation on the part of ALCATEL. COPYRIGHT NOTIFICATION The technical information of this manual is the property of ALCATEL and must not be copied, reproduced or disclosed to a third party without written consent.

1.2 Handbook applicability

1AA 00014 0004 (9007) A4 – ALICE 04.10

This handbook applies to the following product-releases:

ED

PRODUCT

ANV P/N

FACTORY P/N

1660SM

3AL 36301 AAAA

521.203.300

ANV P/N

FACTORY P/N

3AL 81025 ADAA

––.––.––

PRODUCT

RELEASE

1660SM

4.4

VERSION

02 3AL 91668 AA AA 636

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The list of handbooks given here below is valid on the issue date of this Handbook and can be changed without any obligation for ALCATEL to update it in this Handbook. Some of the handbooks listed here below may not be available on the issue date of this Handbook. The standard Customer Documentation in the English language for the equipment whose product-release-version is stated in para.1.2 on page 17 consists of the following handbooks: Table 1. Handbooks related to the specific product hardware

REF

HANDBOOK

1660SM Rel.4.4 Technical Handbook

ANV Part No.

THIS HDBK

3AL 91668 AAAA

[1] Provide information regarding Equipment description, Maintenance , Hardware setting documentation 1660SM Rel.4.4 Installation Handbook

3AL 91668 BAAA

[2] Provide information regarding Equipment Installation, according to A–Installation Engineering Department rules. 1660SM Rel.4.4 Turnup & Commissionig Handbook

3AL 91668 CAAA

[3]

1AA 00014 0004 (9007) A4 – ALICE 04.10

Provide information regarding Equipment Turn–On, Test and Operation, according to A–Installation Engineering Department rules.

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All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

1.3 Product-release handbooks

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

Table 2. Handbooks related to the METRO OMSN specific product SW management and local product control

REF

HANDBOOK

ANV Part No.

Metro OMSN Rel.4.4/5.2 CT Operator’s Handbook

THIS HDBK or note

3AL 91670 AAAA

[4] Provides Metro OMSN (1640FOX, 1650SMC, 1660SM) “SDH” Craft Terminal screens and operational procedures Table 3. Handbooks related to ATM specific product SW

HANDBOOK

REF

ANV Part No.

[5]

ATM Rel.1.2 Operator’s Handbook

3AL 80814 AAAA

[6]

ATM Rel.2.0 Operator’s Handbook

3AL 81826 AAAA

[7]

ATM Rel.2.1 Operator’s Handbook

3AL 89777 AAAA

[8]

ATM Rel.2.2 Operator’s Handbook

3AL 91714 AAAA

THIS HDBK or note

Provides ATM Craft Terminal screens and operational procedures

Table 4. Handbooks related to PR_EA specific product SW

REF

HANDBOOK

ANV Part No.

PR_EA Rel.1.1 Operator’s Handbook

[9]

THIS HDBK or note

3AL 81062 BAAA

1AA 00014 0004 (9007) A4 – ALICE 04.10

Provides PR_EA Terminal screens and operational procedures

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REF

HANDBOOK

ANV Part No.

[10]

PR Rel.1.0 Operator’s Handbook

3AL 81771 AAAA

[11]

PR Rel.1.1 Operator’s Handbook

3AL 91658 AAAA

[12]

PR Rel.1.2 Operator’s Handbook

3AL 91715 AAAA

THIS HDBK or note

Provides PR Craft Terminal screens and operational procedures

Table 6. Handbooks related to ISA ES specific product SW

REF

HANDBOOK

ANV Part No.

[13]

ES1 Rel.1.0 Operator’s Handbook

3AL 89872 AAAA

[14]

ES1/ES4 Rel.1.1 Operator’s Handbook

3AL 89871 AAAA

[15]

ES1/ES4 Rel.1.2 Operator’s Handbook

3AL91804 AAAA

[16]

ES16 Rel.2.0 Operator’s Handbook

3AL 89870 AAAA

[17]

ES16 Rel.2.1 Operator’s Handbook

3AL 91716 AAAA

THIS HDBK or note

1AA 00014 0004 (9007) A4 – ALICE 04.10

Provides ISA–ES Craft Terminal screens and operational procedures

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All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

Table 5. Handbooks related to PR specific product SW

Table 7. Handbooks common to Alcatel Network Elements using 1320CT platform

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

REF

ANV Part No.

FACTORY Part No.

3AL 79551 AAAA

957.140.042 N

HANDBOOK

1320CT 3.x Basic Operator’s Handbook

THIS HDBK

[18] Provides general information and operational procedures common to all 1320CT (Craft terminal) of Alcatel InfoModel Network Elements. 1330AS Rel.6.5 Operator’s Handbook

3AL 88876 AAAA

––––––––

Provides detailed information and operational procedures regarding the alarm Surveillance software embedded in the 1320CT software package. Information about Historical Alarms an Network Element Symbols Management ( Physical Network Management) are not valid for Craft Terminal. They are only used by Network Management.

[19]

ELB Rel.2.x Operator’s Handbook [20]

3AL 88877 AAAA

––––––––

Provide detailed information and operational procedures regarding the Event Log Browser software embedded in the 1320CT software package.

Table 8. Optional handbooks common to 16xxSM REF

HANDBOOK S9–16xxSM System Installation Handbook

ANV Part No.

FACTORY Part No.

3AL 78901 AAAA

955.100.692 N

THIS HDBK

[21] Provides general installation rules necessary to install the Optinex family equipment in the S9 Rack. Optinex RACK–16xxSM System Installation Handbook

3AL 38207 AAAA

955.110.202 L

[22] Provides general installation rules necessary to install the Optinex family equipment in the Optinex Rack.

1AA 00014 0004 (9007) A4 – ALICE 04.10

N.B.

ED

Handbooks REF. [21] and [22] are available only on paper support

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Table 9. Documentation on CD–ROM

REF

CD–ROM TITLE METRO OMSN Rel.4.4/5.2 CD–ROM–DOC EN

[23]

ANV Part No.

FACTORY Part No.

3AL 91671 AAAA

––.––.––

Contains, in electronic format, the following handbooks: REF. [1] to [4] 1320CT 3.x BASIC CD–ROM–DOC EN

3AL 79552 AAAA

417.100.032

[24] Contains, in electronic format, the following handbooks: REF. [18] to [20] ATM 1.2 CD–ROM–DOC EN

3AL 80815 AAAA

––.––.––

[25] Contains, in electronic format, the following handbooks: REF. [5] ATM 2.0 CD–ROM–DOC EN

3AL 81829 AAAA

––.––.––

[26] Contains, in electronic format, the following handbook: REF. [6] ATM 2.1 CD–ROM–DOC EN

3AL 89778 AAAA

––.––.––

[27] Contains, in electronic format, the following handbooks: REF. [7] ATM 2.2 CD–ROM–DOC EN

3AL 91717 AAAA

––.––.––

[28] Contains, in electronic format, the following handbooks: REF. [8] PR_EA 1.1 CD–ROM–DOC EN

3AL 81063 BAAA

––.––.––

[29] Contains, in electronic format, the following handbook: REF. [9] PR 1.0 CD–ROM–DOC EN

3AL 81769 AAAA

––.––.––

[30] Contains, in electronic format, the following handbook: REF. [10] PR 1.1 CD–ROM–DOC EN

3AL 91659 AAAA

––.––.––

[31] Contains, in electronic format, the following handbooks: REF. [11] PR 1.2 CD–ROM–DOC EN

3AL 91718 AAAA

––.––.––

[32] Contains, in electronic format, the following handbooks: REF. [12] ES1 1.0 CD–ROM–DOC EN

3AL 89875 AAAA

––.––.––

1AA 00014 0004 (9007) A4 – ALICE 04.10

[33] Contains, in electronic format, the following handbooks: REF. [13]

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All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

See para. 6.5 on page 61

REF

CD–ROM TITLE

1AA 00014 0004 (9007) A4 – ALICE 04.10

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

ES1/ES4 1.1 CD–ROM–DOC EN

ANV Part No.

FACTORY Part No.

3AL 89874 AAAA

––.––.––

[34] Contains, in electronic format, the following handbooks: REF. [14] ES1/ES4 1.2 CD–ROM–DOC EN

3AL91805 AAAA

––.––.––

[35] Contains, in electronic format, the following handbooks: REF. [15] ES16 2.0 CD–ROM–DOC EN

3AL 89873 AAAA

––.––.––

[36] Contains, in electronic format, the following handbooks: REF. [16] ES16 2.1 CD–ROM–DOC EN

3AL 91719 AAAA

––.––.––

[37] Contains, in electronic format, the following handbooks: REF. [17]

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This handbook has been edited according to the Alcatel standardized “drawing–up guides” complying with such suggestion. This handbook is divided into the following main topics as described in the table of contents: HANDBOOK GUIDE:

It contains general information on safety norms, EMC and type of labels that might be affixed to the equipment. Furthermore, it describes the handbook structure and the customer documentation. The abbreviation list is supplied too.

DESCRIPTION:

It contains all the equipment’s general and detailed system features including its application in the telecommunication network. Furthermore, it supplies the equipment description and specifications (i.e., system, mechanical,electrical and/or optical).

MAINTENANCE:

It contains all the details for periodic checks, fault location and repair procedures and restore to normal operation through the withdrawal of faulty units and their replacement with spares (*)

APPENDICES:

Section envisaged (but not necessarily included) to describe possible alternative unit.

HARDWARE SETTING DOCUMENTATION:

It encloses the documents related to unit hardware setting operations, if envisaged.

ANNEXES:

Section envisaged (but not necessarily included) containing additional documentation or general information on other topics not inherent to the chapters making up the handbook.

1AA 00014 0004 (9007) A4 – ALICE 04.10

(*)

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If the equipment is software integrated and man–machine interfaced (through a PCD, PC, Work Station or other external processing/displaying system) the maintenance carried out with such system is described in the Operator’s Handbook (see para.1.3 on page 18 )

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All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

1.4 Handbook Structure

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

1.5 Handbook Configuration Check 1.5.1 List of the editions and of modified parts The following table indicates the handbook parts new and modified with respect to the previous edition. Legenda n m

= new part = modified part

p =proposal part PR =proposal edition

Table 10. Handbook configuration check EDITION

01

02

DESCRIPTION

n

1. GENERAL

n

2. PHYSICAL CONFIGURATION

n

3. FUNCTIONAL DESCRIPTION

n

4. UNITS DESCRIPTION

n

m

5. TECHNICAL SPECIFICATION

n

m

MAINTENANCE

03

04

05

06

m

n

6. MAINTENANCE

n

APPENDICES Nothing envisaged HARDWARE SETTING DOCUMENTATION

n

Unit documentation list

n

m

ANNEXES Nothing envisaged Note:

the edition of the enclosed documents (sections HARDWARE SETTING DOCUMENTATION and ANNEXES) is not subjected to configuration check.

1.5.2 Notes on Ed.01 Ed.01 created on October 2004 is the first validated and officially released issue of this Handbook. 1.5.3 Notes on Ed.02

1AA 00014 0004 (9007) A4 – ALICE 04.10

Ed.02 created on April 2005 has been edited for: –

New Hardware setting document (MSZZQ) has been added

–

Correction of CWDM units characteristics

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All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

2 COMPLIANCE WITH EUROPEAN NORMS 2.1 Electromagnetic Compatibility (EMC) The CE markings printed on the product denote compliancy with the following Directives: •

89/336/EEC of May 3rd, 1989 (EMC directives), amended: –

by the 92/31/EEC Directive issued on April 28th, 1992

–

by the 93/68/EEC Directive issued on July 22nd, 1993

Compliancy to the above Directives is declared, whenthe equipment is installed as for the manifacturer handbooks, according to the following European Norms: •

EN 300 386 (V1.3.1), environment “Telecommunication Center”

WARNING

1AA 00014 0004 (9007) A4 – ALICE 04.10

This is a class A product EN55022. In domestic, residential and light industry environments, this product may cause radio interference in which case the user may be required to take adequate measures.

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2.2 Safety

1AA 00014 0004 (9007) A4 – ALICE 04.10

ED

•

IEC 60950–1 ed.2001 ,

for electrical safety

•

EN 60950–1 ed.2001 ,

for electrical safety

•

EN 60825–1 ed.1994 + A11 ed.1996+A2 ed.2001

for optical safety

•

IEC 60825–1 ed.1993 + A2 ed. 2001 (1999)

for optical safety

•

EN 60825–2 ed.2000

for optical safety

•

IEC 60825–2 ed.2000

for optical safety

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

Compliancy to Safety Norms is declared in that the equipment satisfies standardized Norms :

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1AA 00014 0004 (9007) A4 – ALICE 04.10

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

3 SAFETY NORMS AND LABELS 3.1 First aid for electric shock Do not touch the patient with bare hands until the circuit has been opened. Open the circuit by switching off the line switches. If that is not possible, protect yourself with dry material and free the patient from the conductor. ARTIFICIAL RESPIRATION It is important to start mouth to mouth resuscitation at once and seek medical help immediately. TREATMENT OF BURNS This treatment should be used after the patient has regained consciousness. It can also be employed while the artificial respiration is being applied (in this case there should be at least two persons present). WARNING:

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•

Do not attempt to remove his clothing from the burnt parts;

•

Apply dry gauze on the burns;

•

Do not apply ointments or other oily substances.

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1

Lay the patient supine with his arms parallel with the body, if the patient is laying on an inclined plane, make sure that his stomach is slightly lower than his chest. Open the patient’s mouth and check that there are no extraneous bodies in his mouth (dentures, chewing–gum etc.),

2

Kneel beside the patient level with his head. Put a hand under the patient’s head and one under his neck (see fig.) Lift the patient’s head and let it recline backwards as far as possible

3

Shift the hand from the patient’s neck to is chin: place your thumb between his chin and his mouth, the index along his jawbone, and keep the other fingers closed together (see fig.). While performing these operations take a good supply of oxygen by taking deep breaths with your mouth open.

4

With your thumb between the patient’s chin and mouth keep his lips together and blow into his nasal cavities (see fig.)

5

1AA 00014 0004 (9007) A4 – ALICE 04.10

6

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All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

Mouth to mouth resuscitation method

While performing these operations observe if the patient’s chest rises (see fig.) If not it is possible that his nose is blocked: in that case open the patient’s mouth as much as possible by pressing on his chin with your hand, place your lips around his mouth and blow into his oral cavity. Observe if the patient’s chest heaves. This second method can be used instead of the first even when the patient’s nose is kept closed by pressing the nostrils together using the hand you were holding his head with. The patient’s head must be kept sloping backwards as much as possible. Start with ten rapid expirations, hence continue at a rate of twelve/fifteen expirations per minute. Go on like this until the patient has regained consciousness, or until a doctor has ascertained his death.

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All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

3.2 Safety Rules 3.2.1 General Rules •

Before carrying out any installation, turn–up & commissioning, operation and maintenance operations carefully read the relevant Handbook and chapters.

•

Observe safety rules –

When equipment is operating nobody is allowed to have access inside on the equipment parts which are protected with Cover Plate Shields removable with tools

–

In case of absolute need to have access inside, on the equipment parts when it is operating this is allowed exclusively to service personnel, where for Service Personnel or Technical assistance is meant : ”personnel which has adequate Technical Knowledge and experience necessary to be aware of the danger that he might find in carrying out an operation and of the necessary measurements to reduce danger to minimum for him and for others”. The Service Personnel can only replace the faulty units with spare parts. The Service Personnel is not allowed to repair: hence the access to the parts no specified is not permitted. The keys and/or the tools used to open doors, hinged covers to remove parts which give access to compartments in which are present high dangerous voltages must belong exclusively to the service personnel.

–

For the eventual cleaning of the external parts of the equipment, absolutely do not use any inflammable substance or substances which in some way may alter the markings, inscriptions ect.

–

It is recommended to use a slightly wet cleaning cloth.

•

The Safety Rules stated in the handbook describe the operations and/or precautions to observe to safeguard service personnel during the working phases and to guarantee equipment safety, i.e., not exposing persons, animals, things to the risk of being injured/damaged.

•

Whenever the safety protection features have been impaired, REMOVE POWER. To cut off power proceed to switch off the power supply units as well as cut off power station upstream (rack or station distribution frame).

•

The safety rules described at the beginning of the handbook are distinguished by the following symbol and statement:

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SAFETY RULES

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3.2.2 Labels Indicating Danger, Forbiddance, Command

The labels are fully compliant with International Norms ISO 3846–1984. The symbols or statements are enclosed in geometric shapes: ISO 3864–1984.

CONTAINS A SYMBOL STATEMENT INDICATES FORBIDDANCE (WHITE BACKGROUND WHIT RED RIM–BLACK SYMBOL OR STATEMENT) IT IS A COMMAND (BLUE BACKGROUND–WHITE SYMBOL OR STATEMENT).

CONTAINS A SYMBOL INDICATES WARNING OR DANGER (YELLOW BACKGROUND–BLACK SYMBOL AND RIM)

CONTAINS A STATEMENT PROVIDING INFORMATION OR INSTRUCTION. (YELLOW BACKGROUND–BLACK STATEMENT AND RIM)

The labels have been affixed to indicate a dangerous condition. They may contain any standard–known symbol or any statement necessary to safeguard users and service personnel against the most common ones, specifically: •

dangerous electrical voltages

•

harmful optical signals

•

risk of explosion

•

moving mechanical parts

•

heat–radiating mechanical parts

1AA 00014 0004 (9007) A4 – ALICE 04.10

Pay attention to the information stated in the following, and proceed as instructed

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All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

It is of utmost importance to follow the instructions printed on the labels affixed to the units and assemblies.

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

The symbols presented in para.3.2.3 through 3.2.7 are all the possible symbols that could be present on Alcatel equipment, but are not all necessarily present on the equipment this handbook refers to.

3.2.3 Dangerous Electrical Voltages 3.2.3.1 Labelling The following warning label is affixed next to dangerous voltages (>42.4 Vp; >60 Vdc).

If it is a Class 1 equipment connected to mains, then the label associated to it will state that the equipment will have to be grounded before connecting it to the power supply voltage, e.g.:

WARNING ! Ground protect the equipment before connecting it to mains Make sure that power has been cut off before disconnecting ground protection.

3.2.3.2 Electrical safety: general rules

DANGER! Possibility of personal injury:

1AA 00014 0004 (9007) A4 – ALICE 04.10

carefully observe the specific procedures for installation / turn–up and commissioning / maintenance of equipment parts where a.c. or d.c. power is present, described in the relevant installation / turn–up and commissioning / maintenance documents and the following general rules: a)

Personal injury can be caused by –48 V dc (or by 220 V ac if envisaged in the equipment). Avoid touching powered terminals with any exposed part of your body.

b)

Short circuiting, low-voltage, low-impedance, dc circuits can cause severe arcing that can result in burns and/or eye damage. Remove rings, watches, and other metal jewelry before working with primary circuits. Exercise caution to avoid shorting power input terminals.

3.2.3.3 Electrical safety: equipment specific data Refer to para.5.1.2 on page 565.

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3.2.4 Harmful Optical Signals

If the assembly or unit is fitted with a LASER, the labels must comply with the IEC 60825–1 and –2 International Norms.

The symbol indicates the presence of a LASER beam. Danger level is stated within a rectangular label:

If the LASER is a Hazard Level 1, 1M product, the label depicting the symbol within a triangle is not compulsory. If the LASER is a Hazard Level 3A product, the label depicting the symbol within a triangle is compulsory. NOTE: the equipment may be provided with labels of a type other than the illustrated one (reason: previous standard). The rectangular shaped label bears all the information needed, i.e.:

1AA 00014 0004 (9007) A4 – ALICE 04.10

• • • • • •

LASER class Power emitted Wave length Ref. Norm Precautionary measures taken depend on LASER class Indications given on openings, panels and safety interlockers

exemple of power and lenght values

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3.2.4.1 Labelling

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3.2.4.2 Optical safety: general rules On handling optical equipments or units or cables always check that laser labels are properly affixed and that the system complies with applicable optical standards.

DANGER! Possibility of eyes damage: invisible infrared radiations emitted by the fiber optic transmitters can cause eyes damages. Carefully observe the specific procedures for installation / turn–up and commissioning / maintenance of units containing laser devices or cables transporting optical signals, described in the relevant installation / turn–up and commissioning / maintenance documents and the following general rules: a)

Laser radiation is not visible by the naked eye or with laser safety glasses. Although it cannot be seen, laser radiation may be present.

b)

Never look directly into an unterminated fiber optic connector or into a broken optical fiber cable, unless it is absolutely known that no laser radiation is present.

c)

Never look at an optical fiber splice, cable or connector, unless it is absolutely known that no laser radiation is present.

d)

All optical connectors, terminating either fibers and transmitters/receivers, are provided with protective covers that must always be used, as soon as possible, when any optical link is disconnected for installation/test/maintenance purposes or whatever operation.

e)

Never look directly into an unterminated fiber optic connector or into a broken optical fiber cable by means of magnifiers/microscopes, unless it is absolutely known that no laser radiation is present. A magnifier/microscope greatly increases the damage hazard to the eyes.

f)

Never point an unterminated optical fiber splice, cable or connector to other persons, unless it is absolutely known that no laser radiation is present.

g)

Always remove electrical power from near and far optical transmitters before disconnecting optical links between the transmitter and the receiver.

h)

Wearing of laser safety goggles or eyes shields is recommended for every person working on optical devices, whenever the above listed rules cannot be followed.

3.2.4.3 Optical safety: equipment specific data

1AA 00014 0004 (9007) A4 – ALICE 04.10

Refer to paragraph 5.1.1 on page 561 .

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3.2.5 Risks of Explosions

This risk is present when batteries are used, and it is signalled by the following label:

Therefore, slits or apertures are made to let air circulate freely and allow dangerous gasses to downflow (battery–emitted hydrogen). A 417–IEC–5641 Norm. compliant label is affixed next to it indicating that the openings must not be covered up.

3.2.6 Moving Mechanical Parts

1AA 00014 0004 (9007) A4 – ALICE 04.10

The following warning label is affixed next to fans or other moving mechanical parts:

Before carrying out any maintenance operation see that all the moving mechanical parts have been stopped.

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3.2.5.1 Labelling and safety instructions

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

3.2.7 Heat–radiating Mechanical Parts The presence of heat–radiating mechanical parts is indicated by the following warning label in compliancy with IEC 417 Norm, Fig.5041:

As stated by IEC 950 Norm., para.1.4.7 mechanical parts which carry the above pictured label and that could inadvertently be touched, have a temperature T established by the following formula:

(T–Tamb)  (DTmax + 25° – Tmra) where:

T

Temperature of the mechanical part measured at ambient temperature Tamb.

Tamb

Ambient temperature during the test

DTmax

Value defined by IEC 60950 Norm, Table 16 part 2a, para.5.1, and specified in the table below.

Tmra

The maximum room ambient temperature permitted by the equipment specification or 25°C, whichever is greater.

Table 11. IEC 950 –Table 16: Overtemperature limits, Part 2

Maximum overtemperature (°C ) Operator–accessible parts Metal

Glass, porcelain

Plastic, rubber

Handle knob, ect., held or touched for short periods

35

45

60

Handles, knobs, ect., regularly held

30

40

50

Outer surface of the equipment that can be touched

45

55

70

Inner surface of the equipment that can be touched

45

55

70

DANGER! Possibility of personal injury:

1AA 00014 0004 (9007) A4 – ALICE 04.10

carefully observe the specific procedures for installation / turn–up and commissioning / maintenance of equipment parts where heat–radiating mechanical parts are present, described in the relevant installation / turn–up and commissioning / maintenance documents and the following general rule: a)

ED

Personal injury can be caused by heat. Avoid touching powered terminals with any exposed part of your body.

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3.2.8 Specific safety rules in this handbook

1AA 00014 0004 (9007) A4 – ALICE 04.10

•

ED

–

Chapter 6 paragraph 6.1 on page 621

–

Chapter 6 paragraph 6.5.2.1 on page 624

–

Chapter 6 paragraph 6.6.1 on page 625

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

The safety rules are specified in the following chapters:

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All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

4 OTHER NORMS AND LABELS 4.1 Electromagnetic Compatibility The equipment’s EMC norms depend on the type of installation being carried out (cable termination, grounding etc.,) and on the operating conditions (equipment, setting options of the electrical/electronic units, presence of dummy covers, etc.). •

Before starting any installation, turn–up & commissioning, operation and maintenance work refer to the relevant Handbook and chapters.

•

The norms set down to guarantee EMC compatibility, are distinguished inside this handbook by the symbol and term:

ATTENTION

EMC NORMS.

1AA 00014 0004 (9007) A4 – ALICE 04.10

4.1.1 General Norms – Installation

ED

•

All connections (towards the external source of the equipment) made with shielded cables use only cables and connectors suggested in this technical handbook or in the relevant Plant Documentation, or those specified in the Customer’s”Installation Norms.” (or similar documents)

•

Shielded cables must be suitably terminated

•

Install filters outside the equipment as required

•

Ground connect the equipment utilizing a conductor with proper dia. and impedance

•

Mount shields (if utilized), previously positioned during the installation phase, but not before having cleaned and degreased it.

•

Before inserting the shielded unit proceed to clean and degrease all peripheral surfaces (contact springs and connection points, etc.)

•

Screw fasten the units to the subrack.

•

To correctly install EMC compatible equipment follow the instructions given.

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•

Preset the electrical units as required to guarantee EMC compatibility

•

Check that the equipment is operating with all the shields properly positioned (dummy covers, ESD connector protections, etc.)

•

To properly use EMC compatible equipment observe the information given

1AA 00014 0004 (9007) A4 – ALICE 04.10

4.1.3 General Norms – Maintenance

ED

•

Before inserting the shielded unit, which will replace the faulty or modified unit, proceed to clean and degrease all peripheral surfaces (contact springs and connection points, etc.)

•

Clean the dummy covers of the spare units as well.

•

Screw fasten the units to the subrack.

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4.1.2 General Norms – Turn–up & Commissioning, Operation

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

4.2 Electrostatic Dischargers (ESD) Before removing the ESD protections from the monitors, connectors etc., observe the precautionary measures stated. Make sure that the ESD protections have been replaced and after having terminated the maintenance and monitoring operations. Most electronic devices are sensitive to electrostatic dischargers, to this concern the following warning labels have been affixed:

Observe the precautionary measures stated when having to touch the electronic parts during the installation/maintenance phases. Workers are supplied with antistatic protection devices consisting of:

ELASTICIZED BAND

1AA 00014 0004 (9007) A4 – ALICE 04.10

COILED CORD

ED

•

an elasticized band worn around the wrist

•

a coiled cord connected to the elasticized band and to the stud on the subrack.

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4.3 Suggestions, notes and cautions

Suggestion or note.... Cautions to avoid possible equipment damage are marked by the following symbol: TITLE... (caution to avoid equipment damage) statement....

4.4 Labels affixed to the Equipment This chapter indicates the positions and the information contained on the identification and serial labels affixed to the equipment. Figure 1. thru’ Figure 7. illustrate the most common positions of the labels on the units, modules and subracks. Figure 8. thru’ Figure 11. illustrate the information (e.g., identification and serial No.) printed on the labels. The table below relates the ref. numbers stated on the figures to the labels used. Labelling depicted hereafter is for indicative purposes and could be changed without any notice. Table 12. Label references

Ref. No.

Name of Label

1

label specifying item not on catalogue (P/N. and serial number)

2

label specifying item on catalogue (P/N. and serial number)

3

item identification label – item on catalog

4

label identifying the equipment

1AA 00014 0004 (9007) A4 – ALICE 04.10

On contract basis, customized labels can be affixed to the equipment. Standard labels can be affixed to any position on the equipment, as required by the Customer. However, for each of the above are applied the rules defined by each individual Customer.

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All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

Suggestions and special notes are marked by the following symbol:

1AA 00014 0004 (9007) A4 – ALICE 04.10



All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.






NOTE : The above reference numbers are detailed on Table 12. on page 42

Figure 1. Subrack label

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1AA 00014 0004 (9007) A4 – ALICE 04.10






NOTE : The above reference numbers are detailed on Table 12. on page 42

Figure 2. Subrack label

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1AA 00014 0004 (9007) A4 – ALICE 04.10



ED 

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.




NB.1 = The label is present on the support side

NOTE : The above reference numbers are detailed on Table 12. on page 42

Figure 3. Subrack label

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1AA 00014 0004 (9007) A4 – ALICE 04.10








NOTE : The above reference numbers are detailed on Table 12. on page 42

Figure 4. Labels on units with standard cover plate

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1AA 00014 0004 (9007) A4 – ALICE 04.10






NOTE : The above reference numbers are detailed on Table 12. on page 42

Figure 5. Modules label

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All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.







NB.1 = The label is present on the p.c.s. component side

1AA 00014 0004 (9007) A4 – ALICE 04.10

NOTE : The above reference numbers are detailed on Table 12. on page 42 Figure 6. Internal label for Printed Board Assembly

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1AA 00014 0004 (9007) A4 – ALICE 04.10

NB. 1 = The label is present on p.c.s. components side or rear side on the empty spaces. NOTE : The above reference numbers are detailed on Table 12. on page 42 Figure 7. Back panels internal label

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FACTORY P/N + CS FACTORY SERIAL NUMBER

SERIAL NUMBER BAR CODE (format 128; Module = 0,166; EN 799; Subset B/C)

Figure 8. Label specifying item not on catalogue (P/N. and serial number)

ANV ITEM PART NUMBER + space + ICS ANV ITEM PART NUMBER + ICS BAR CODE (format ALFA 39 (+ * start, stop); Module = 0,166; Ratio = 2)

ALCATEL FACTORY PART NUMBER + SPACE + CS

ACRONYM

SERIAL NUMBER

SERIAL NUMBER BAR CODE (format ALFA 39 (+ * start, stop); Module = 0,166; Ratio = 2)

1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 9. Label specifying item on catalogue (P/N. and serial number)

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FREQUENCY (Optional)

ACRONYM

ANV ITEM PART NUMBER

Figure 10. Item identification labels – item on catalog

EQUIPMENT NAME

1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 11. Label identifying the equipment (example)

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1AA 00014 0004 (9007) A4 – ALICE 04.10

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5 LIST OF ABBREVIATIONS

1AA 00014 0004 (9007) A4 – ALICE 04.10

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Table 13. List of Abbreviations

MEANING

ABBREVIATION ABIL

Enabling

ABN

Abnormal

ADM

Add/Drop Multiplexer

AIS

Alarm indication Signal

ALS

Automatic Laser Shutdown

APD

Avalanche Photodiode

APS

Automatic Protection Switching

AND

Alarm on both station batteries

ANSI

American National Standards International

ASIC

Application Specific Integrated Circuit

ATM

Asynchronous Transfer Module

ATTD

Attended (alarm storing)

AU

Administrative Unit

AUG

Administrative Unit Group

AUOH

AU Pointer

AUX

Auxiliary

AU4

Administrative unit – level 4

BATT

Battery

BER

Bit Error Rate

BIP

Bit Interleaved Parity

BNC

Bayonet Not Coupling

C

Storing command

CE

European Conformity

CO

Central Office

CPE

Customer premises equipment

CT

Craft Terminal

CMI

Code Mark Inversion

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1AA 00014 0004 (9007) A4 – ALICE 04.10

MEANING

COAX

Coaxial

CPI

Incoming parallel contacts

CPO

Outgoing parallel contacts

CPU

Central Processing Unit (referred to Controller equipment unit or Microprocessor)

C12/C3/C4

1st, 3rd and 4th level container

DC

Direct Current

DCC

Data Communication Channel

DCE

Data Circuit Terminating Equipment

DPLL

Digital Phase Locked Loop

DTE

Data Terminal Equipment

EBU

European Broadcasting Union

EC

Equipment Controller

ECC

Embedded Control Channel

ECT

Equipment Craft Terminal

EMC

Electromagnetic compatibility

EMI

Electromagnetic interference

EOW

Engineering Order Wire

EPS

Equipment Protection Switching

ESD

Electrostatic discharges

ETSI

European Telecommunication Standards Institute

E2PROM

Electrically erasable programmable read only memory

F

Interface F (for Craft Terminal) or Fuse

FEBE

Far End Block Error

FEPROM

Flesh Electrically erasable programmable read only memory

FERF

Far End Receive Failure

FPGA

Field Programmable Gate Array

GA

Gate Array

GND

Ground

HDBK

Handbook

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All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

ABBREVIATION

1AA 00014 0004 (9007) A4 – ALICE 04.10

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

ABBREVIATION

MEANING

HDB3

High Density Bipolar Code

HIGHREFL

High Optical reflections

HOA

High Order Adaptation

HOI

High Order Interface

HPC

High order Path Connection

HPT

Higher Order Path Termination

HPOM

High order Path Overhead Monitoring

HSUT

High order Supervisory Unequipped Termination

HW

Hardware

ICS

Item Change Status

ID

Identification signals

IEC

International Electrotechnical Committee

IEEE

Institute of Electrical and Electronic Engineering

IN

Input

IND

Indicative alarm

INT

Internal Local Alarms

IP

Internet Protocol

ISO

International Organism for standardization

ITU–T (*)

International Telecommunication Union–Telecommunication Sector

JE1

Joint Engineering

LAN

Local Area Network

LDSSHUT

Command for ALS

LED

Light emitting diode

LOF

Loss of alignment

LOI

Low Order Interface

LOM

Loss Of Multiframe

LOP

Loss Of Pointer

LOS

Loss of signal

LPA

Lower order path adaption

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MEANING

LPC

Lower order path connection

LPOM

Lower Order Path Monitoring

LPT

Lower order path termination or Loopback equipment side (local)

LSUT

Lower order Supervisory Unequipped Termination

M

Tagblock or Alarm storing

MCF

Message Communication Function

MLM

Multi Longitudinal mode

MSA

Multiplex section adaptation

MSOH

Multiplex Section Overhead

MSP

Multiplex section protection

MST

Multiplex section termination

NRZ

No return to zero

NURG

Not urgent alarm

OH–BUS

Dedicated housekeeping stream

OMSN

Optinex MultiService Node

OOF

Out Of Frame

OR

Logic sum/Loss of only one station battery

OS

Operating system

OUT

Output

P/S

Parallel/Serial converter

PC

Personal Computer

PDH

Plesiochronous Digital Hierarchy

PFAIL

Power supply failure

PI

Physical interface

PJE

Pointer Justification Event

PPI

Plesiochronous Physical interface

POH

Path Overhead

PMMF

Physical Machine Management Function

PPS

Path Protection Switching

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ABBREVIATION

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All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

ABBREVIATION

MEANING

PRBS

Pseudo Random Binary Signal

PR_EA

Packet Ring Edge Aggregator

PWALM

Power supply alarm

PWANDOR

ANDOR/3 failure

Q2/QB2

TMN Interface with B2 protocol. Interface towards plesiochronous equipment

Q3/QB3

TMN Interface with B3 protocol. Interface towards TMN

R

Reset command /General alarm

RAI

Remote Alarm Indication

RECC

Recommendation

RAM

Random Access Memory

RDI

Remote Defect Indication

REI

Remote Error Indication

RCK

Received clock

REF

Reference

REL

Release

RIBUS

Remote Inventory BUS

RMS

Root Mean Square

RNURG

Not urgent Alarm command. Lights up the relative rack red LED

RSOH

Regenerator Section Overhead

RST

Regenerator Section Termination

RURG

Urgent Alarm command. Lights up the relative rack red LED

Rx

Reception

SC

Shelf Controller

SDH

Synchronous Digital Hierarchy

SETG

Synchronous Equipment Timing Generation function

SLM

Single Longitudinal Mode

SM

Single Mode/Synchronous Mux

SNCP/I (** )

Subnetwork Connection Protection Inherent

SOH

Section Overhead

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MEANING

S/P

Serial/Parallel Converter

SPI

Synchronous Physical Interface

SSF

Server Signal Fail

SQ

Squelch

STM–0/STM–1

Synchronous Transport Module, levels 0 etc.

SW

Software

TANC

Remote alarm due to failure of all power supply units

TD

Layout drawing

TIM

Trace Identifier Mismatch

TMN

Telecommunication Management Network

TOR

Remote alarm indicating loss of one of the station batteries

TORC

Remote alarm due to a faulty/missing power supply unit

TSD

Trail Signal Degrade

TSF

Trail Signal Fail

TTF

Transport Terminal Function

TUG2/3

Tributary unit group, level 2,3

TUOH

Tributary Unit Overhead

TUP/UP

Equipment Controller remote alarm

TU12/TU3

Tributary unit level 12, 3

TX

Transmission

URG

Urgent

VCXO/VCO

Voltage controlled oscillator

VC12/VC3/VC4

Virtual Container, levels 12,3,4

VMMF

Virtual Machine Management Function

WAN

Wide Access Network

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ABBREVIATION

1AA 00014 0004 (9007) A4 – ALICE 04.10

NOTES – (*) Owing to change of name, all documents issued by the two ITU committees (CCIR ND CCITT) in 1992 (and in some cases even before then) are classified as ITU–R and ITU–T, respectively. (**) Substitutes PPS

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6 GENERAL ON ALCATEL CUSTOMER DOCUMENTATION 6.1 Products, product-releases, versions and Customer Documentation A ”product” is defined by the network hierarchical level where it can be inserted and by the whole of performance and services for which it is meant. A ”product” evolves through successive ”product-releases” which are the real products marketed for their delivery at a certain ”product-release” availability date. So, a ”product–release” defines a set of hardware components and a software package which, as a whole, identify the possible network applications and the equipment performance which the specific ”product-release” has been designed, engineered and marketed for. In some cases a ”product-release” has further development steps, named ”versions”, that are born to improve or add some performance (mainly software) with respect to the previous version, or for bug fixing purposes. A ”product-release” has its own standard Customer Documentation, composed by one or more handbooks. A new ”version” of a ”product-release” may or may not produce a change in the status of the Customer Documentation set, as described in para. 6.4 on page 60.

6.2 Handbook supply to Customers Handbooks are not automatically delivered together with the equipment they refer to. The number of handbooks per type to be supplied must be decided at contract level.

6.3 Aims of standard Customer Documentation Standard Customer Documentation, referred to hereafter, must be always meant as plant-independent. Plant-dependent documentation, if envisaged by the contract, is subjected to commercial criteria as far as contents, formats and supply conditions are concerned (plant-dependent documentation is not described here). Standard hardware and software documentation is meant to give the Customer personnel the possibility and the information necessary for installing, commissioning, operating and maintaining the equipment according to Alcatel–Telecom Laboratory design choices. In particular: the contents of the handbooks associated to the software applications focus on the explanation of the man-machine interface and of the operating procedures allowed by it; maintenance is described down to faulty PCB location and replacement.

1AA 00014 0004 (9007) A4 – ALICE 04.10

Consequently, no supply to the Customers of design documentation (like PCB hardware design and production documents and files, software source programs, programming tools, etc.) is envisaged. The handbooks concerning hardware (usually the ”Technical Handbook”) and software (usually the ”Operator’s Handbook”) are kept separate in that any product changes do not necessarily concern their contents. For example, only the Technical Handbook might be revised because of hardware configuration changes (e.g., replacing a unit with one having different P/N but the same function). On the other hand, the Operator’s Handbook is updated because of a new software version but which does not concern the Technical Handbook as long as it does not imply hardware modifications. However, both types of handbooks can be updated to improve contents, correct mistakes, etc..

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6.4 Handbook Updating

Each handbook is identified by: – the name of the ”product-release” (and ”version” when the handbook is applicable to the versions starting from it, but not to the previous ones), – the handbook name, – the handbook P/N, – the handbook edition (usually first edition=01), – the handbook issue date. The date on the handbook does not refer to the date of print but to the date on which the handbook source file has been completed and released for the production. 6.4.1 Changes introduced in the same product-release (same handbook P/N) The edition and date of issue might change on future handbook versions for the following reasons: –

only the date changes (pointed out in the Table of Contents) when modifications are made to the editorial system not changing the technical contents of the handbook.

–

the edition, hence the date, is changed because modifications made concern technical contents. In this case: • •

the chapters modified with respect to the previous edition are listed in Table 10. on page 25.; in affected chapters, revision bars on the left of the page indicate modifications in text and drawings.

Changes concerning the technical contents of the handbook cause the edition number increase (e.g. from Ed.01 to Ed.02). Slight changes (e.g. for corrections) maintain the same edition but with the addition of a version character (e.g. from Ed.02 to Ed.02A). Version character can be used for draft or proposal editions. NOTES FOR HANDBOOKS RELEVANT TO SOFTWARE APPLICATIONS

Handbooks relevant to software applications (typically the Operator’s Handbooks) are not modified unless the new software ”version” distributed to Customers implies man–machine interface changes or in case of slight modifications not affecting the understanding of the explained procedures. Moreover, should the screen prints included in the handbook contain the product-release’s ”version” marking, they are not replaced in the handbooks related to a subsequent version, if the screen contents are unchanged. 6.4.1.1 Supplying updated handbooks to Customers

1AA 00014 0004 (9007) A4 – ALICE 04.10

Supplying updated handbooks to Customers who have already received previous issues is submitted to commercial criteria. By updated handbook delivery it is meant the supply of a complete copy of the handbook new issue (supplying errata–corrige sheets is not envisaged). 6.4.2 Changes due to new product version A new product version changes the handbook P/N and the edition starts from 01. In this case the modified parts of the handbook are not listed.

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The handbooks associated to the ”product–release” are listed in para.1.3 on page 18.

6.5 Customer documentation on CD–ROM

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

In the following by ’CD–ROM’ it is meant ’Customer Documentation on CD–ROM’ 6.5.1 Contents, creation and production of a CD–ROM In most cases, a CD–ROM contains in read–only eletronic format the documentation of one product–release(–version) and for a certain language. In some other cases, the same CD–ROM can contain the documentation of different product–release(–version)s for a certain language. As a general rule: –

–

CD–ROMs for Network Management products do not contain: •

the Installation Guides

•

the documentation of system optional features that Customers could not buy from Alcatel together with the main applicative SW.

CD–ROMs for Network Elements products do not contain: •

the documentation of system optional features (e.g. System Installation Handbooks related to racks that Customers could not buy from Alcatel together with the main equipment).

A CD–ROM is obtained collecting various handbooks and documents in .pdf format. Bookmarks and hyperlinks make the navigation easier. No additional information is added to each handbook, so that the documentation present in the CD–ROMs is exactly the same the Customer would receive on paper. The files processed in this way are added to files/images for managing purpose and a master CD–ROM is recorded. Suitable checks are made in order to have a virus–free product.

1AA 00014 0004 (9007) A4 – ALICE 04.10

After a complete functional check, the CD–ROM image is electronically transferred to the archive of the Production Department, so that the CD–ROM can be produced and delivered to Customers.

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6.5.2 Use of the CD–ROM

The CD–ROM starts automatically with autorun and hyperlinks from the opened “Index” document permit to visualize the .pdf handbooks Other hyperlinks permit to get, from the Technical handbooks, the specific .pdf setting documents. In order to open the .pdf documents Adobe Acrobat Reader Version 4.0 (minimum) must have been installed on the platform. The CD–ROM doesn’t contain the Adobe Acrobat Reader program. The Customer is in charge of getting and installing it. ReadMe info is present on the CD–ROM to this purpose. Then the Customer is allowed to read the handbooks on the PC/WS screen, using the navigation and zooming tools included in the tool, and to print selected parts of the documentation through a local printer. 6.5.3 CD–ROM identification Each CD–ROM is identified: 1)

by the following external identifiers, that are printed on the CD–ROM upper surface: – the name of the ”product–release(s)” (and ”version” if applicable) – a writing indicating the language(s), – the CD–ROM P/N ), – the CD–ROM edition (usually first edition=01)

2)

and, internally, by the list of the source handbooks and documents (P/Ns and editions) by whose collection and processing the CD–ROM itself has been created.

6.5.4 CD–ROM updating

1AA 00014 0004 (9007) A4 – ALICE 04.10

The list of source handbook/document P/Ns–editions indicated in previous para. 6.5.3 point 2 ) , in association with the CD–ROM’s own P/N–edition, is also loaded in the Alcatel–Information–System as a structured list. Whenever a new edition of any of such handbooks/documents is released in the Alcatel archive system, a check in the Alcatel–Information–System is made to identify the list of CD–ROMs that must be updated to include the new editions of these handbooks/documents. This causes the planning and creation of a new edition of the CD–ROM. Updating of CD–ROMs always follows, with a certain delay, the updating of the single handbooks composing the collection.

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The CD–ROM can be used both in PC and Unix WS environments.

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DESCRIPTIONS

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1 GENERAL 1.1 Introduction to the equipment The Alcatel 1660SM is a synchronous Optical Multi Service Node (OMSN); it complies with the Synchronous Digital Hierarchy (SDH) defined in ITU–T Recommendation G.707. The integration of SDH and WDM technology represents the chance to enhance the network capacity with no impact on the starting physical means (i.e. fibers): the presence of a wavelength grid allows the user to multiply the capacity with limited costs, if compared to the cable laying; on the other side the SDH network (specifically configured with OMSN’s equipment) represents the most flexible and reliable way to handle different types of clients, both TDM and data. The availability of Coarse WDM technology in the 1660SM matches a second driver for network integration, i.e. ’cost reduction’. CWDM optical devices represent a cost effective solution, if compared to the Dense WDM technology and fit most of the network scenarios in area ’metro’(refer to Figure 12. on page 69). 1660SM, makes available up to 8 channels for traffic transport according the ITU –T G.694.2 wavelength grid: 1470 – 1490 – 1510 – 1530 – 1550 – 1570 – 1590 – 1610 nm. The 1660SM with CWDM technology fulfits both ’ring’ and ’linear’ applications (refer to paragraph 1.2.3 on page 77 and paragraph 1.2.4 on page 81). Compatible with existing plesiochronous systems as well as with the installed SDH networks, the 1660SM is a transmission equipment operating at 155 (STM–1), 622(STM–4) and 2488(STM–16) Mbit/s bit rates. It can be configured as a Multiple Line Terminal Multiplexers or as a Multiple Add/Drop Multiplexers or mini cross connect for applications in linear links, network rings and meshed networks. A wide range of ports can be added/dropped/connected by the equipment according to the traffic type to be managed: –

2.048 Mbit/s signal (with asynchronous mapping) Processing of unstructured and structured (ISDN–PRA) 2Mb/s signal.

–

34/45 Mbit/s

–

STM–1 Electrical/Optical

–

STM–4 Optical Signal

–

STM–16 Optical Signal

–

OC3 Electrical/Optical

–

A mixing of SDH and Data Services is possible by inserting the 4xANY board in the 1660SM subrack. It allows to multiplex in the time domain up to 4 client signals into one single 2.5Gb/s optical channel (server signal). Server STM–16 signal is connected to SDH matrix through 1660SM backpanel. Multiplexing scheme delivers a fully compliant SDH frame. The signal can hence be directly connected to a SDH ADM/DXC without requiring prior de–concentration.

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The clients signals can be independently handled among the following types: • • • • •

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• •

ISA (Integrated Service Adapter)

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Alcatel’s Integrated Service Adapter (ISA) series of plug–in cards are specially designed to enhance the optical transport network by adding data–aware features that are easy to introduce, allowing carriers to efficiently and cost–effectively aggregate, switch and transport the expanding amount of data services in their metropolitan network. 1660SM equipped with ISA plug–in cards give telecom operators a new generation modular platform for multi–service SDH transport and further strengthen Alcatel’s leading position in the supply of optical multi–technology transmission networks. The ISA system is modular and the plug–ins can be chosen according to the specific application the 1660SM needs to manage; the following ISA boards are available:

ED

•

ISA–ATM (Asynchronous Transfer Module); the ATM cells, mapped into SDH G707 payloads (VC4, VC4–C, VC3, VC12) or PDH G704/G832/G804 frames (E1, E3), can be processed, routed and switched, using the dedicated unit. Such functionalities are particularly useful in urban and local access ring to consolidate data traffic from different users onto the same SDH Virtual Containers, thereby optimizing the utilization of transmission bandwidth (see Figure 13. on page 70).

•

ISA–PR_EA (Packet Ring Edge Aggregator) also called MPLS (Multi Protocol Label Switching); the packets data services of level 3 of the protocol stack, transported over Ethernet, are routed into the SDH network by means of MPLS labels. Topology can be either meshed or ring networks. It is especially made as interface aggregator.

•

ISA–PR (Packet Ring); the packets data services of level 3 of the protocol stack, transported over Ethernet, are routed into the SDH network by means of MPLS labels. PR is for ring network topology, with dedicated data protector scheme. The role of PR functionality is to provide a shared carrier–class Ethernet Packet Ring either embedded physically into the SDH infrastructure, in which case the embedded Packet Ring is provided in a flexible manner over SDH Virtual Containers (VC–4–Xv), or alternatively the PR can be connected directly to independent fibers to create a Packet Ring over single or dual STM4. PR Deployment Scenario is presented on Figure 14. on page 71.

•

ISA–Ethernet: the Ethernet MAC frames are accessed at 10/100BaseT format, and then mapped into SDH G707 payloads (VC4, VC3, VC12); they can be transparently linked, point–to–point, in the SDH network to allow LAN to LAN connections as depicted in the example of Figure 15. on page 72. If the customer has N sites to be interconnected, each Customer Box uses N–1 Point to Point Ethernet interfaces. Ethernet frames are mapped over a SDH VC using Generic Framing Procedure encapsulation. As SDH Network is transparent, the customer Boxes see them as directly connected in a mesh.

•

ISA–Gbit/s Ethernet: the Ethernet signals are accessed at 1.25Gb/s over optical fiber medium, and then mapped into SDH G707 payloads VC4; they can be transparently linked, point–to–point, in the SDH network to allow LAN to LAN connections as depicted in the example of Figure 15. on page 72 If the customer has N sites to be interconnected, each Customer Box uses N–1 Point to Point Ethernet interfaces. Ethernet frames are mapped over a SDH VC using Generic Framing Procedure encapsulation. As SDH Network is transparent, the customer Boxes see them as directly connected in a mesh.

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–

FICON (1.0625Gbps) Gigabit Ethernet (1.25Gbps)

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•

ISA–ES (Ethernet Switching). ISA–ES series modules provide ETH 10/100/1000 interfaces connectivity for LAN based clients premises inside the metro area. Beyond mapping ETH flows onto the SDH metro network by means of standard mechanisms (as specified in ITU G.7071, ITU G.7042 and ITU G.707) the ISA–ES series cards introduce wire speed classifying, policing and scheduling capability empowered by carrier class Ethernet switching engine. Per customer traffic flow management with low bandwidth granularity, segregation and QoS are just few of the value added arguments that these series of modules offer to the carrier operators at a competitive price.

When 1660SM is used as Add/Drop Multiplexer , mixed STM–N ports can be used in the same configuration thus allowing to manage in the same equipment and at the same time STM–1 , STM–4 and STM–16 rings (multiring) . A large variety of STM–1 optical plug–in modules operating at 1300 nm and 1550 nm is available to cover short and long haul systems. Dedicated optical interfaces are also available to inter–work with boosters and optical pre–amplifiers at all STM–N levels. 1660SM also features “colored” STM–16 interfaces for direct interworking with WDM equipment without intermediate wavelength adapters. All the electrical units (traffic ports) and the common units can be optionally EPS protected with different modularity (1+1; 1+N with 1 v N v15 as far as regards the traffic ports ): –

The EPS protection of the High Speed electrical traffic units ( 34 Mbit/s, 45 Mbit/s and155 Mbit/s) is implemented using a dedicated access module.

–

The EPS protection of the ATM/PR_EA units is implemented.

–

The EPS protection of the ISA–ES16 units is implemented.

According to the network topology, network protection mechanisms are provided: –

Single ended and dual ended MSP (Multiplex Section Protection) can be implemented at any STM–N level.

–

MS–SPRing (Multiple Section Shared Protection Ring) on two fibers bidirectional rings can be implemented at STM–16 level.

A centralized matrix implements the cross–connect function allowing allocation of the PDH and VCi signals into every port, providing add/drop and pass–through functionality at all VCi levels. The maximum matrix cross connection capability can be 96 x 96 STM–1 equivalent port at VC–4 level or 64x64 STM–1 equivalent port at VC–12 / VC–3 level + 32x32 equivalent port at VC–4 level.

1AA 00014 0004 (9007) A4 – ALICE 04.10

A wide auxiliary capacity, in accordance with SDH standards, is available for embedded services. An Engineering Order Wire channel, with DTMF signalling, can be accessed by a microtelephone for maintenance facility. The clock reference function, housed in the centralized unit, synchronizes the 1660SM and provides generation and distribution of a synchronism clock. The distributed clock can be locked to an external 2MHz or 2Mbit/s source, to any STM–N or 2Mbit/s signal. The SSM (Synchronization Status Message) and priority algorithms are supported.

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Traffic ports have no on–board processor (except for some ISA boards) and may be reused from one equipment to another or retrieve from stocks with no worries about software version. The system can be managed either by a Personal Computer through the F interface or by a Network Management System through the Q interface. Moreover, the 1660SM can work as a Mediation Device for Alcatel NE accessible through Q2/RQ2 interface. In this way, it can be possible to transport information about alarms and configurations of PDH and/or Access Systems to/from a centralized TMN using the standard SDH DCC network. A DC/DC converter, located on each board, guarantees the powering of the system. The distribution of Power Supplies inherently guarantees protection.

1AA 00014 0004 (9007) A4 – ALICE 04.10

Other functionalities :

ED

•

Bidirectional Transmission For the 1660SM optical interface a bidirectional transmission on single fiber function is implemented, using an external passive optical coupler.

•

Remote Equipment Control This function allows a centralized management system for small SDH networks, similar to that offered by an OS. That means that it is possible to perform management functionalities , from one of the NEs of the network, toward the other NEs (up to 31), like configuration modification and remote control.

•

Dual OS O.S. Spare is foreseen to protect the Main one.

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The Equipment Controller function provides unit configuration and collects unit alarms, statuses and performance monitoring data. A Local software download facility is available in order to update the complete software of the control subsystem.

Metro Access Ring

CWDM

2.5/nx2.5G CWDM VC–4/3/12 network PACKET Metro Core Ring/Mesh CWDM 1–N x STM–16

E3/DS3 10/100/GbE

E1/DS1

2.5/nx2.5G CWDM network

Metro Edge Ring (up to 100–X Km)

Metro OMSN VC–4/3/12 PACKET

Metro G OMSN

CWDM

CWDM

VC–4/3/12 PACKET

Core OMSN

CWDM

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Link: up to 100 Km

VC–4/3/12 PACKET

SDH@STM–16

1–N x STM–16

E1/DS1 E3/DS3 STM–n/10GbE

10/100/GbE

E1/DS1 STM–n/10GbE

E3/DS3

1AA 00014 0004 (9007) A4 – ALICE 04.10

E/FE

Figure 12. Example of SDH/DATA/CWDM integration in “metro area”

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1AA 00014 0004 (9007) A4 – ALICE 04.10

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1640FOX

1640FOX

ÑÑ ÑÑ ÑÑ ÌÌÌÌ ÌÌÌÌ ÌÌÌÌ Consolidated bandwidth

ÓÓ ÓÓÌÌÌ ÑÑÔ ÓÓÌÌÌ ÑÑÔ ÔÌÌÌ ÌÌÌ

ÌÌÌÌ ÌÌÌÌ ÌÌÌÌ Ô Ó ÌÌÌÌ Ô Ó ÔÓ

3AL 91668 AA AA

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1640FOX

ATM Switch

SDH Network

10/100 Base T Full Duplex 1000 BASE –LX 1000 BASE –SX

Ethernet:

1650SMC

1660SM

ÌÌÌÌ ÌÌÌÌ ÌÌÌÌ

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Traffic engineering: MPLS Routing ATM switching

ÌÌÌÌ ÌÌÌÌ ÑÑ Ó ÑÑÌÌÌÌ Ó ÑÑ Ó

Bandwidth control: – ATMM QoS

1650SMC

TDM ATM PR_EA

PDH Interfaces:

TDM ATM PR_EA

SDH Interfaces:

1640FOX

ÌÌÌÌ ÌÌÌÌ ÌÌÌÌ ÌÌÌÌ

Figure 13. Example of ATM Transport management

02

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Legend : 1660SM with ISA –PR –

Ethernet/IP Core

Customer Switch/Router Hand –off of aggregated packet traffic to core network

1640FOX

GbE

Overlay MPLS Packet Ring created over VC –4–Xv Bandwidth

1650

L3 Router

STM16 SDH Ring

Fe or GbE 1640FOX

1AA 00014 0004 (9007) A4 – ALICE 04.10

1640FOX

ISA –PR does not have to be installed in all ring nodes

End –to–end Metro Ethernet Service created with QoS/SLA

Figure 14. ISA–PR Deployment Scenario

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1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 15. Ethernet service application

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1660SM with LAN to LAN board

Customer box: either LAN Switch or Router

Legenda: protection

SDH level

Ethernet frames are mapped in SDH VC–12. VC–3, VC–4

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The LAN to LAN board is present only at each terminating node

SDH RING NETWORK

mapped on a dedicated SDH VC

Site to Site Traffic is

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1.2 Insertion of the equipment into the network The 1660SM equipment belongs to the Alcatel Optinex family product, compliant with the SDH Synchronous Digital Hierarchy defined by the ITU–T Recs. The equipment 1660SM can be utilized in local, regional and metropolitan networks configured for standard plesiochronous or synchronous systems. The product can be suitably employed on linear, ring and hub networks and on protected or unprotected line links. The equipment applications depends on the different types of networks available. 1.2.1 Configuration •

Terminal multiplexer (see Figure 16. ). The NE is provided with an STM–1/STM–4/STM–16 station interface (eventually stand–by too) to be connected to a Digital Electronic Cross–Connect or to a higher hierarchical line system.

SDH PORT PDH PORTS

NE SDH PORT (SPARE)

Figure 16. Terminal multiplexer •

Add/Drop Multiplexer ( see Figure 17. ) The NE can be programmed to drop (insert) signals from (into) the STM1/STM4/STM–16 stream. Part of the signal pass–through between the line sides, defined A and B in Figure 17. on page 73.

Side A

SDH PORT

SDH PORT

NE

Side B

SDH PORT (SPARE)

SDH PORT (SPARE)

SDH, PDH PORTS

1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 17. Add/Drop Multiplexer

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•

SDH PORT

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”HUB” STM–N (see Figure 18. ) The NE permits to drop/insert STM–N tributaries into a multiple stream and then branch them off in HUB structures.

SDH PORT

NE

SDH PORT (SPARE)

SDH PORT (SPARE)

SDH PORT Figure 18. ”HUB” STM–1 •

Mixed Configuration The NE can handle in the same node all the previously configuration thus performing a mixed configuration.

1.2.2 Application For each of the above configurations different network topologies may be used. The most important network topologies are: Point to Point Linear Ring and multiring topology Meshed topology

•

Point–to–point link (see Figure 19. ) In this case the NE can be connected to another multiplexer through the line

SDH PORT PDH PORTS

NE

NE

SDH PORT SPARE

1AA 00014 0004 (9007) A4 – ALICE 04.10

SDH PORT PDH PORTS

SDH PORT SPARE

Figure 19. Point–to–point links

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•

Linear Drop–insert (see Figure 20. ) The NE can be programmed to drop (insert) PDH and SDH ports from (into) the STM–1, STM–4, STM–16 stream or terminate PDH ports SDH PORT

SDH PORT

NE

NE SPARE

SDH PORT

NE

NE

SPARE

SPARE

PDH PORTS

PDH PORTS SDH AND PDH PORTS

SDH AND PDH PORTS

Figure 20. Linear drop–insert •

Ring structure (see Figure 21. ) The drop–insert function permits to realize ring structures. The VC can be automatically rerouted if the optical splice breaks down or one of the equipment nodes fails SDH AND PDH PORTS

STM–4

NE STM–4

RING 1 SDH AND PDH PORTS

NE

SDH AND PDH PORTS

NE

SDH AND PDH PORTS

STM–4

STM–4

NE STM–1

SDH AND PDH PORTS

PDH PORTS

NE

SDH AND PDH PORTS

NE

RING 2 STM–1

1AA 00014 0004 (9007) A4 – ALICE 04.10

STM–1

STM–1

NE SDH AND PDH PORTS Figure 21. Ring structure

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•

The Meshed topology may be used in case of collection of traffic in peripheral nodes or customer premises sites. 1+1 line protection may be used to protect against line failure and, in some cases, node failure could be protected using dual hub topology too. For this type of network topologies the mini digital cross connect system is very useful and SNCP/I is used. PDH PORT

NE STM–N

SDH AND PDH PORTS

STM–N

PDH PORT

STM–1

PDH PORT

NE

RING

NE

NE

STM–N

STM–1

NE

STM–N

PDH PORT NE

STM–N

SDH AND PDH PORTS

STM–N

NE

NE

RING

NE

NE

STM–N

STM–N

STM–N

PDH PORT

NE

STM–N

PDH PORT

SDH AND PDH PORTS STM–N

PDH PORT

1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 22. Meshed topology

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Meshed Topology (see Figure 22. on page 76)

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1.2.3 SDH / CWDM integration in “ring” network NOTE: in this paragraph and in the following 1.2.4 on page 81 , 1660SM equipped with Coarse WDM units will be called 1660OADM. 1660SM equipped with “Coarse WDM units” fulfits ’ring’ application by using two possible items according to the traffic matrix to be considered : •

COADM 1 (2) channel;

•

MUX/DEMUX 8 channels.

The use of COADM unit for interfacing WDM ring, allows the operator to duplicate/triplicate the starting network capacity based on a ’single optical channel’ provided by ’pure’ STM–N interfaces.

1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 23. SDH/CWDM integration in “ring” with COADM units According to the amount of traffic to be handled at a node of the ring, 1(2) channels (λx, λy) out of the 8 specified by ITU–T grid are added/dropped in order to be handled by 1660SM; the remaining channels possibly not terminated, are by–passed, from one side to the opposite one of the node (W to E, E to W) through a specific link (at WDM level) between COADM’s units.

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In Figure 23. the representation of a ’ring’ network using COADM as ring interface is provided; while in Figure 24. the functional parts related to each node of the ring are detailed.

Figure 24. SDH/CWDM integration in “ring” with COADM unit: detailed view In the showed example, ’added/dropped’ wavelengths ( λ1, λ2, ) are terminated by STM16 ’CWDM’ interfaces operating in compliance with the ITU–T grid. Traffic streams terminated are, then, cross–connected at SDH level and made available to the relevant ’client’ interfaces (SDH/PDH/MPLS/Ethernet).

1AA 00014 0004 (9007) A4 – ALICE 04.10

The use of MUX/DEMUX unit for interfacing WDM ring, allows the operator to terminate the whole pool of optical channels available. MUX/DEMUX unit is required when the traffic matrix is larger than the capacity provided by COADM 1(2) channel/s. The application in a ’ring’ network, requires the use of two MUX/DEMUX units respectively for West side interfacing and East side interfacing.

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COADM unit is specifically devoted to application in a ’ring’ network (due to WDM pass–through link) and requires the use of two separate units respectively for West side interfacing and East side interfacing.

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Figure 25. SDH/CWDM integration in “ring” with MUX/DEMUX unit Up to 8 channels may be added/dropped at a node of the ring, according to the amount of traffic to be terminated; while wavelengths not terminated at a node, are by–passed, from one side to the opposite one of the node (W to E, E to W) through a specific link (at channel level) between MUX/DEMUX units. In Figure 25. the representation of a ’ring’ network using MUX/DEMUX as ring interfaces is provided.

1AA 00014 0004 (9007) A4 – ALICE 04.10

In Figure 26. the functional parts related to each node of the ring are detailed.

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Figure 26. SDH/CWDM integration in “ring” with MUX/DEMUX unit: detailed view

1AA 00014 0004 (9007) A4 – ALICE 04.10

In the showed example, 4 wavelengths ( λ1, λ2, λ3, λ4, ) are ’added/dropped’ at a generic node, then terminated by STM16 ’CWDM’ interfaces operating in compliance with the ITU–T grid. As for previous COADM application, traffic streams terminated are cross–connected at SDH level and made available to the relevant ’client’ interfaces (SDH/PDH/MPLS/Ethernet).

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1.2.4 SDH / CWDM integration in “linear” network The use of 16660SM with “Coarse WDM units” in linear network is properly based on MUX/DEMUX unit deployment. As, already seen for ’ring’ application, the use of MUX/DEMUX allows the termination of 8 available channels. Nevertheless, the use of COADMn unit may be considered for those network scenarios whose traffic demand is satisfied by 1 or 2 wavelengths.

Figure 27. SDH/CWDM integration in “linear” network Figure 27. shows a ’linear’ network application for 1660SM. In Figure 28. a detailed vision of a node in this kind of network is also provided; wavelength multi/ demultiplexing is supposed to be performed by MUX/DEMUX unit.

1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 28. SDH/CWDM integration in “linear” network (MUX/DEMUX): detailed view In the showed example, the whole pool of 8 wavelengths is terminated at the end of the link by STM16 ’CWDM’ interfaces operating in compliance with the ITU–T grid: two shelves are considered in order to allow the equipment of ’colored’ interfaces needed.

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In Figure 8, the possible use of an COADM unit for wavelength multi/demultiplexing is considered; for this functionality, COADM ’pass–through’ link is not used.

1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 29. SDH/CWDM integration in “linear” network (COADM unit): detailed view

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1AA 00014 0004 (9007) A4 – ALICE 04.10

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1.2.5 Network protection The relationship between the network application with their own protection and the configuration modes is summed up in Table 14. on page 83. Table 14. Network application versus configuration modes

NE Configuration

Network Protection Scheme

TM

Point to Point

MSP

Ǹ

Linear

MSP

Ǹ

Network application

Ring

Ǹ

SNCP

Hub and Meshed

ED

ADM

MSP & SNCP

Ǹ Ǹ

Ǹ

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2 PHYSICAL CONFIGURATION

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In all this document, three types of cards will be distinguished : •

access card : it is a board containing the signal physical interfaces ( electrical connectors)

•

ports card : it is the board that performs the SDH elaboration of the signal

•

module (electrical or optical) : It is a particular plug–in card ( of small dimensions ) that is inserted on the front panel of some particular boards.

This Chapter illustrates the physical structure, layout and composition, coding and partition of the Equipment and Fans subrack.

EQUIPMENT: The Equipment Shelf front view is illustrated in Figure 30. on page 86. 1660SM is composed of one shelf containing 21 slots in the access area and 20 slots in the basic area. The two areas are located on different “lines” inside the shelf. The main part code and partition are listed in Table 15. on page 89. The accessories codes and partition are listed in Table 16. on page 102. For the relationship between access cards and port cards refer to paragraph 2.3 on page 110. FANS SUBRACKS: The Fans subracks front view is illustrated in Figure 31. on page 87. The main part code and partition are listed in Table 17. on page 104. NOTES: The explanatory notes are reported in Table 18. on page 105. UNITS FRONT VIEW:

1AA 00014 0004 (9007) A4 – ALICE 04.10

For the units front view refer to para 2.4 on page 120.

N.B.

Table 15. on page 89 contains the units of current equipment release. Units belonging to previous equipment releases/versions (e.g. for configuration updating) are not here listed but still supported, if compatible with the current one. (For eventual units belonging to previous equipment releases/versions refer to the relevant Technical Handbook).

N.B.

The Personal Computer (Craft Terminal) utilized for Initial Turn–on and Maintenance operations is not listed as an item of the equipment, but it can be supplied by Alcatel. See Operator’s Handbook for PC hardware configuration.

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1AA 00014 0004 (9007) A4 – ALICE 04.10

A

R

E

ED A

S

I

C

A PORT LS – HS TBUS

W20

W35

29 30 31 32 33 34 35 36 37 38 39

3AL 91668 AA AA

636 40

W20

PORT ENHANCED – HS

W20

B

MATRIX B

PORT ENHANCED – HS

PORT LS – HS

W20

ACCESS LS – HS ACCESS LS – HS ACCESS LS – HS

W30

SERVICE

ACCESS LS

12 13 14 15 16 17 18 19 20 21

W20

W20

W20

W20

W20

W20

W20

W20

W20

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ACCESS LS – HS

ACCESS LS – HS

ACCESS LS – HS

ACCESS LS – HS

ACCESS LS – HS

ACCESS LS – HS

ACCESS LS – HS

ACCESS LS – HS

CONGI B

W20

W20

ACCESS LS – HS CONGI A

11

W20

PORT LS SPARE – HS

W20

ACCESS LS – HS

9 10

PORT LS – HS

PORT HS

W20

25 26 27 28

W20

W20 8

W20

PORT LS – HS

W20

W20

7

PORT ENHANCED – HS

PORT ENHANCED – HS

W20

W20

6

W20

PORT ENHANCED – HS

W20

W20

5

PORT ENHANCED – HS

PORT LS – HS

W20

W20

ACCESS LS – HS 4

W20

PORT ENHANCED – HS

24

W20

23

PORT ENHANCED – HS

22

W20

W20

E ACCESS LS – HS

R 3

PORT LS – HS

A W20

S 2

ACCESS LS – HS

E 1

W20

MATRIX A

C W20

C

ACCESS LS

S

TBUS

EQUICO A

A

W35

W20

2.1 Equipment front view

2.1.1 1660SM Shelf front view

A

41

W = mm width

Figure 30. 1660SM units positioning

02

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1AA 00014 0004 (9007) A4 – ALICE 04.10

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2.1.2 19” Fans subrack front view

Left side

SLOT 0 SLOT 1

ED Right side

SLOT 2

SLOT 4 SLOT 3 SLOT 5

Figure 31. 19” Fans subrack unit slots

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In the tables of the following paragraphs are listed, named and coded the items and units making up the Equipment Shelf (see para. 2.2.1 on page 89) and Fans subrack (see para 2.2.2 on page 104). Furthermore, for any item the position and the maximum quantity that can be allocated inside the subracks are indicated too. Such tables report the following information : •

Item Name

•

The ”Acronym” identifying the units is silk–screen printed on the front cover plate. The same Acronym, not provided with the point (e.g. L–4.1 becomes L–41), is used by the Craft Terminal to distinguish the unit. There is in exception to this rule for the P3E3T3; the unit is identified as P3E3T3 on the front cover plate and as P3E3/T3 on the Craft Terminal.

•

Factory and ANV part numbers (e.g. 411.XXX.XXX ; 3ALXXXXX XXXX)

•

Maximum quantity

•

Position of the unit inside the equipment. Refer to Figure 30. at page 86 for slot numbering.

•

Number of explanatory notes

1AA 00014 0004 (9007) A4 – ALICE 04.10

Table 18. on page 105 (see para 2.2.3 on page 105) reports all the explanatory notes .

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2.2 Part list

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2.2.1 Equipment Shelf part list

Table 15. Main part list NAME

ANV Part Number (Factory Part Number)

Max. Qty

SLOT

3AL 78834 AA–– (593.155.059E)

–

–

SR60M

3AL 79157 AA–– (593.155.073 U)

1

–

1

TBUS

3AL 79088 AC–– (487.166.408 B)

2

23, 40

2

3AL 81728 AA––

1

––

3

ACRONYM

MECHANICAL STRUCTURE 1660SM SHELF Made up of: 1660SM SHELF

TERMINATION BUS/2 SFP EXTRACTOR LOW SPEED PORTS (PDH)

63x2 MBIT/S PORT 1.0/2.3

4

P63E1

63x2 MBIT/S G703/ISDN– P63E1N–M4 PRA–FS PORT

3AL 79092 AA–– (474.166.425 V )

3AL 79092AC–– (474.166.046 C)

7

24, 27, 30, 32, 33, 36, 39

5

7

24, 27, 30, 32, 33, 36, 39

5 6

HIGH SPEED PORTS (PDH) 3x34/45 MBIT/S SWIT. PORT

7 P3E3T3

3AL 78864 AA–– (474.156.339L)

16

24 to 39

HIGH SPEED PORTS : STM–1 (SDH) and 140 Mbit/s (PDH) P4ES1N

3AL 78823 AA–– (474.166.423T)

4 X 140/STM1 SWITCH. O/E PORT/1

P4E4N

3AL 79263 AA–– (474.156.371L)

4x STM–1 PORT/1

P4S1N

3AL 78821 BA–– (474.156.375 Q)

4 x STM–1 ELECTRICAL PORT/1

1AA 00014 0004 (9007) A4 – ALICE 04.10

NOTES

ED

8 9 10

16

24 to 39

11 12 12

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ACRONYM

ANV Part Number (Factory Part Number)

Max. Qty

SLOT

NOTES

3AL 81736 AA–– (474.156.186 U)

16

24 to 39

12

6

25+26 28+29 34+35 37+38 30+31 32+33

13

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

NAME

HIGH SPEED PORTS : OC3 (SONET) 4 x OC3 PORT

AU3/TU3 CONV.

P4OC3

4 x ANY CONCENTRATOR

4 x ANY HOST C

4XANYC

3AL 81635 AA–– (411.102.533 K)

HIGH SPEED PORTS : STM–4 (SDH)

9

S–4.1 PORT/1 FC/PC

S–4.1N

3AL 78856 BA–– (474.156.376 R)

S–4.1 PORT/1 SC/PC

S–4.1N

3AL 78856 BB–– (474.156.377 J)

L–4.1 PORT/1 FC/PC

L–4.1 N

3AL 78856 BC–– (474.156.378 T)

L–4.1 PORT/1 SC/PC

L–4.1 N

3AL 78856 BD–– (474.156.379 U)

L–4.2 PORT/1 FC/PC

L–4.2N

3AL 78856 BE–– (474.156.380 J)

L–4.2 PORT/1 SC/PC

L–4.2N

3AL 78856 BF–– (474.156.381 F)

4 x STM–4 PORT

P4S4N

3AL 79176 AA–– (411.101.062 V)

16

24 to 39

4

25,26, 28,29, 34,35, 37,38

14 15

16

1AA 00014 0004 (9007) A4 – ALICE 04.10

(Table continues)

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NAME

ACRONYM

ANV Part Number (Factory Part Number)

Max. Qty

SLOT

HIGH SPEED PORTS : STM–16 (SDH)

9, 17

S–16.1 PORT FC/PC/16C

S–16.1ND

3AL 78894 CA–– (411.101.308 R)

S–16.1 PORT SC /16C

S–16.1ND

3AL 78895 CA–– (411.101.309 J)

L–16.1 PORT FC/PC/16C

L–16.1ND

3AL 78896 CA–– (411.101.310 E)

L–16.1 PORT SC/16C

L–16.1ND

3AL 78897 CA–– (411.101.311 T)

L–16.2 PORT FC/PC/16C

L–16.2ND

3AL 78898 CA–– (411.101.312 U)

L–16.2 PORT SC/16C

L–16.2ND

3AL 78899 CA–– (411.101.313 V)

L–16.2 JE2 PORT FC/PC/16C

L–16.2ND

3AL 79029 CA–– (411.101.316 Y)

L–16.2 JE2 PORT SC/PC/16C

L–16.2ND

3AL 79029 CB–– (411.101.317 Z)

L–16.2 JE3 PORT FC/PC/16C CH34

L–16.2ND

3AL 79030 DA–– (411.102.549 B)

L–16.2 JE3 PORT SC/PC/16C CH34

L–16.2ND

3AL 79030 DB–– (411.102.550 G)

I–16.1 PORT /SFF (Intra office)

STM 16 PORT SFP

NOTES

I–16.1ND

3AL 80881AA–– (411.102.022 N)

CO–16

3AL 81434 AA–– (411.102.522 Q)

4

25+26 28+29 34+35 37+38

14 15

25+26 28+29 34+35 37+38

14 15 18

4

25+26 28+29 34+35 37+38

14 19

4

25+26 28+29 34+35 37+38

20

4

1AA 00014 0004 (9007) A4 – ALICE 04.10

(Table continues)

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ACRONYM

ANV Part Number (Factory Part Number)

Max. Qty

SLOT

NOTES

25+26 28+29 34+35 37+38

14 21

25+26 28+29 34+35 37+38

14 22

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NAME

HIGH SPEED PORTS : STM–16 COLORED PORT (SDH) STM16 195.7 PORT 6400 SC/PC/16C

L–16.2ND

3AL 79187 BA–– (411.101.320 G)

STM16 195.5 PORT 6400 SC/PC/16C

L–16.2ND

3AL 79187 BB–– (411.101.321 V)

STM16 195.3 PORT 6400 SC/PC/16C

L–16.2ND

3AL 79187 BC–– (411.101.322 W)

STM16 195.1 PORT 6400 SC/PC/16C

L–16.2ND

3AL 79187 BD–– (411.101.323 X)

STM16 194.9 PORT 6400 SC/PC/16C

L–16.2ND

3AL 79187 BE–– (411.101.324 Y)

STM16 194.7 PORT 6400 SC/PC/16C

L–16.2ND

3AL 79187 BF–– (411.101.325 Z)

STM16 194.5 PORT 6400 SC/PC/16C

L–16.2ND

3AL 79187 BG–– (411.101.326 S)

STM16 194.3 PORT 6400 SC/PC/16C

L–16.2ND

3AL 79187 BH–– (411.101.327 T)

STM16 193.7 PORT 6400 SC/PC/16C STM16 193.5 PORT 6400 SC/PC/16C STM16 193.3 PORT 6400 SC/PC/16C STM16 193.1 PORT 6400 SC/PC/16C STM16 192.9 PORT 6400 SC/PC/16C STM16 192.7 PORT 6400 SC/PC/16C STM16 192.5 PORT 6400 SC/PC/16C STM16 192.3 PORT 6400 SC/PC/16C

L–16.2ND L–16.2ND L–16.2ND L–16.2ND L–16.2ND L–16.2ND L–16.2ND L–16.2ND

3AL 79187 BL–– (411.101.328 C) 3AL 79187 BM–– (411.101.329 D) 3AL 79187 BN–– (411.101.330 A) 3AL 79187 BP–– (411.101.331 X) 3AL 79187 BQ–– (411.101.332 Y) 3AL 79187 BR–– (411.101.333 Z) 3AL 79187 BS–– (411.101.334 S) 3AL 79187 BT–– (411.101.335 T)

4

4

1AA 00014 0004 (9007) A4 – ALICE 04.10

(Table continues)

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NAME

ACRONYM

ANV Part Number (Factory Part Number)

Max. Qty

SLOT

NOTES

4

25+26 28+29 34+35 37+38

14 21

4

25+26 28+29 34+35 37+38

14 22

HIGH SPEED PORTS : STM–16 COLORED PORT (SDH) STM16 195.7 PORT 12800 SC/PC/16C STM16 195.5 PORT 12800 SC/PC/16C STM16 195.3 PORT 12800 SC/PC/16C STM16 195.1 PORT 12800 SC/PC/16C STM16 194.9 PORT 12800 SC/PC/16C STM16 194.7 PORT 12800 SC/PC/16C STM16 194.5 PORT 12800 SC/PC/16C STM16 194.3 PORT 12800 SC/PC/16C STM16 193.7 PORT 12800 SC/PC/16C STM16 193.5 PORT 12800 SC/PC/16C STM16 193.3 PORT 12800 SC/PC/16C STM16 193.1 PORT 12800 SC/PC/16C STM16 192.9 PORT 12800 SC/PC/16C STM16 192.7 PORT 12800 SC/PC/16C STM16 192.5 PORT 12800 SC/PC/16C STM16 192.3 PORT 12800 SC/PC/16C

L–16.2ND L–16.2ND L–16.2ND L–16.2ND L–16.2ND L–16.2ND L–16.2ND L–16.2ND L–16.2ND L–16.2ND L–16.2ND L–16.2ND L–16.2ND L–16.2ND L–16.2ND L–16.2ND

3AL 79188 BA–– (411.101.336 U) 3AL 79188 BB–– (411.101.337V) 3AL 79188 BC–– (411.101.338 E) 3AL 79188 BD–– (411.101.339 F) 3AL 79188 BE–– (411.101.340 L) 3AL 79188 BF–– (411.101.341 H) 3AL 79188 BG–– (411.101.342 A) 3AL 79188 BH–– (411.101.343 B) 3AL 79188 BL–– (411.101.344 C) 3AL 79188 BM–– (411.101.345 D) 3AL 79188 BN–– (411.101.346 E) 3AL 79188 BP–– (411.101.347 F) 3AL 79188 BQ–– (411.101.348 Q) 3AL 79188 BR–– (411.101.349 R) 3AL 79188 BS–– (411.101.350N) 3AL 79188 BT–– (411.101.351 B)

1AA 00014 0004 (9007) A4 – ALICE 04.10

(Table continues)

ED

02 3AL 91668 AA AA 636

93 / 636

ANV Part Number (Factory Part Number)

Max. Qty

SLOT

ETH–MB

3AL 80407 AA–– (474.156.038 A)

6

24 to 39

GETH–MB

3AL 80702 AB–– ––.––.––

8

24 to 39

ATM MATRIX 4X4

ATM4X4

3AL 79093 AA–– (411.101.035 J)

ATM MATRIX 4X4 ENHANCED

ATM4X4V2

3AL 81185 AA–– (411.102.475 Z)

ATM4X4D3

3AL 89917 AA–– ––.––.––

ATM8X8

3AL 79094 AA–– (411.101.036 K)

PREA4ETH

3AL 79631 AA–– (411.101.281 W)

PREA1GBE

3AL 81275 AA–– (411.102.505 Y)

ISA–PR

3AL 89677 AA–– ––.––.––

3

25 to 38

ISA–ES1 8FE

ES1–8FE

3AL 98128AA–– ––.––.––

8

24 to 39

ISA–ES1 8FX

ES1–8FX

3AL 98150AA–– ––.––.––

8

24 to 39

ISA–ES4 8FE + 1GE

ES4–8FE

3AL81879 AA–– (474.156.195 V)

ISA–ES16

3AL81915 AA–– ––.––.––

COWLA2

3AL 81427 AA–– (411.102.520 S)

NOTES All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

ACRONYM

NAME ISA – ETHERNET PORT ETHERNET PORT

GIGABIT ETHERNET PORT/2

23

24 25

ISA – ATM PARTS 26 24 to 39

27

4 ATM MATRIX 4X4 D3

ATM MATRIX 8X8

28

24 to 38

29

ISA – PR_EA PARTS PR_EA MATRIX 4X ETHERNET

30 4

PR_EA MATRIX 1XGB–ETH

24 to 39 31

ISA – PR PARTS PR MATRIX 4X STM4 PLUG–IN

32

ISA – ES PARTS

ISA–ES16 BOARD

33

34 8

24 to 39

16

24 to 39

1AA 00014 0004 (9007) A4 – ALICE 04.10

CWDM PORTS 2xCH TRANSPONDER SFP W/O OPTICS

ED

35

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94 / 636

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

NAME

ACRONYM

ANV Part Number (Factory Part Number)

Max. Qty

SLOT

18

1 to 9, 13 to 21

NOTES

LS (LOW SPEED) ACCESS CARDS 21x2 MBIT/S PROT. 75 OHM 1.0/2.3

A21E1

3AL78831AA–– (474.156.323C)

21x2 MBIT/S PROT. 120 OHM

A21E1

3AL78832AA–– (474.156.324D)

21x2 MBIT/S PROT. 120 OHM K20

A21E1

3AL 79163 AA–– (474.156.366 P)

36, 37

38

36

HS (HIGH SPEED) ACCESS CARDS 3x34 MBIT/S 75 OHM

A3E3

3AL78865AB–– (474.156.181 X)

3x45 MBIT/S 75 OHM

A3T3

3AL78866AB–– (474.156.182 Y)

4xSTM–1 ELECTRICAL 75 OHM

A4ES1

3AL78835AA–– (474.156.325E)

HIGH SPEED PROTECTION

HPROT

3AL 78849 AA–– (474.156.127 Y)

8

2 to 9, 13 to 20

41

2x140/STM–1 O/E ADAPTER

A2S1

3AL78818AA–– (474.166.421Z)

16

2 to 9, 13 to 20

42

3AL 80404 AA–– (474.156.039 B)

6

16

2 to 9, 13 to 20

39

40

ISA – ETHERNET ACCESS CARDS ETHERNET ACCESS GIGABIT ETHERNET ACCESS/2

ETH–ATX

GETH–AG

3AL 80411 AB––

8

43 2 to 9, 13 to 20

44

ISA – PR ACCESS CARDS ISA–PR 16XETH 10/100 ACCESS

16FEA–PR

3AL 89678 AA–– ––.––.–– 6

ISA–PR 2XGBE 1000 ACCESS PLUG–IN

2 GBA–PR

3AL 89679AA–– ––.––.––

2 to 8, 13 to 20

45 46

1AA 00014 0004 (9007) A4 – ALICE 04.10

(Table continues)

ED

02 3AL 91668 AA AA 636

95 / 636

ANV Part Number (Factory Part Number)

Max. Qty

SLOT

NOTES

CONGI

3AL78830AD–– ––

2

10, 12

47

SERVICE

3AL78817AA–– (411.100.704R)

1

11

48

ACRONYM

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

NAME

CONTROL AND GENERAL INTERFACE CONTROL AND GENERAL INTERFACE R5 SERVICE SERVICES I/F

BOOSTER AND PREAMPLIFIER OMSN BOOSTER +10dBm FC/PC

BST10

3AL 78962 AA–– (411.100.902 G)

OMSN BOOSTER +10dBm SC/PC

BST10

3AL 78962 BA–– (411.101.245 H)

OMSN BOOSTER +15dBm FC/PC

BST15

3AL 78962 AC–– (411.100.904 A)

OMSN BOOSTER +15dBm SC/PC

BST15

3AL 78962 BC–– (411.101.247 B)

OMSN BOOSTER +17dBm FC/PC

BST17

3AL 78962 AD–– (411.100.905 B)

OMSN BOOSTER +17dBm SC/PC

BST17

3AL 78962 BD–– (411.101.248 L)

PREAMPLIFIER 2.5 GB/S SC/PC CH34

PR16

3AL 78963 AD–– (411. 102.557 T)

PREAMPLIFIER 2.5 GB/S FC/PC CH34

PR16

2 to 8 13 to 19

1AA 00014 0004 (9007) A4 – ALICE 04.10

8

ED

49

2 to 8 13 to 19

3AL 78963 AC–– (411.102.558 C)

02 3AL 91668 AA AA 636

96 / 636

1AA 00014 0004 (9007) A4 – ALICE 04.10

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

NAME

ACRONYM

ANV Part Number (Factory Part Number)

Max. Qty

SLOT

8

1 to 8 13 to 20

NOTES

CWDM CONNECTION MODULES COADM 1 CH (1470)

COADM1

3AL 81344 AA–– (411.102.513P)

COADM 1 CH (1490)

COADM1

3AL 81344 AB–– (411.102.542 U)

COADM 1 CH (1510)

COADM1

3AL 81344 AC–– (411.102.543 V)

COADM 1 CH (1530)

COADM1

3AL 81344 AD–– (411.102.544 W)

COADM 1 CH (1550)

COADM1

3AL 81344 AE–– (411.102.545 X)

COADM 1 CH (1570)

COADM1

3AL 81344 AF–– (411.102.546 Y)

COADM 1 CH (1590)

COADM1

3AL 81344 AG–– (411.102.547 Z)

COADM 1 CH (1610)

COADM1

3AL 81344 AH–– (411.102.548 A)

COADM 2 CH (1470–1490)

COADM2

3AL 81346 AA–– (411.102.541 R)

COADM 2 CH (1510–1530)

COADM2

3AL 81346 AB–– (411.102.539 Z)

COADM 2 CH (1550–1570)

COADM2

3AL 81346 AC–– (411.102.540 E)

COADM 2 CH (1590–1610)

COADM2

3AL 81346 AD–– (411.102.541 T)

MUX – DEMUX 8 CH.

COMDX8

3AL 81348 AA–– (411.102.517 K)

ED

49

8

1 to 8 13 to 20

02 3AL 91668 AA AA 636

97 / 636

ACRONYM

ANV Part Number (Factory Part Number)

S–1.1 OPT. INTERF. FC/PC

IS–1.1

3AL78815AA–– (474.166.420 C)

S–1.1 OPT. INTERF. SC/PC

IS–1.1

3AL 78815 AB–– (474.166.424 U)

L–1.1 OPT. INTERF. FC/PC

IL–1.1

3AL78838AA–– (474.156.326 F)

L–1.1 OPT. INTERF. SC/PC

IL–1.1

3AL 78838 AB–– (474.156.352 R)

L–1.2 OPT. INTERF. FC/PC

IL–1.2

3AL78839AA–– (474.156.327 G)

L–1.2 OPT. INTERF. SC/PC

IL–1.2

3AL 78839 AB–– (474.156.353 J)

L–1.2 JE OPT. INTERF. FC/PC

IL–1.2

3AL78840AA–– (474.156.328 R)

L–1.2 JE OPT. INTERF. SC/PC

IL–1.2

3AL 78840 AB–– (474.156.354 K)

140/155 ELECTRICAL INTERFACE

ICMI

3AL37558AB–– (474.156.346 K)

53

STM–1 MULTIMODE OPT SC/PC

MM1

3AL 80741 AA–– (474.166.035 Z)

50

Max. Qty

SLOT

NOTES All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

NAME STM–1 MODULES

50,51

64

––

50,51,52

STM–4 MODULES S–4.1 OPTICAL INTERF. FC/PC S–4.1 OPTICAL INTERF. SC/PC L–4.1 OPTICAL INTERF. FC/PC L–4.1 OPTICAL INTERF. SC/PC L–4.2 OPTICAL INTERF. FC/PC L–4.2 OPTICAL INTERF. SC/PC

IS–4.1

IL–4.1

IL–4.2

3AL 79340 AA–– 474.156.372 M 3AL 79451 AA–– 474.156.384 A 3AL 79452 AA–– 474.156.385 B 3AL 79452 AB–– 474.156.386 C

8

––

54

3AL 79453 AA–– 474.156.387 D 3AL 79453 AB–– 474.156.388 N

1AA 00014 0004 (9007) A4 – ALICE 04.10

4xANY MODULES 4 X ANY HS PLUG–IN 1310 (OH–I)

OH–I

3AL 81616 AA–– (474.156.178 K)

12

Refer to Figure 51.

55

4 X ANY LS PLUG–IN 1310 (OL–I)

OL–IN

3AL 81617 AA–– (474.156.179 L)

24

Refer to Figure 51.

56

4 X ANY HS PLUG–IN 850

OH–MM

3AL81613 AA–– (474.156.175 G)

12

Refer to Figure 51.

55

4 X ANY LS PLUG–IN 850

OL–MM

3AL81615 AA–– (474.156.177 A)

24

Refer to Figure 51.

56

ED

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All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

NAME

ACRONYM

ANV Part Number (Factory Part Number)

Max. Qty

SLOT

NOTES

64

––

57 58

1AB 194670001

64

––

58

1AB 196360001

8

––

58

ETHERNET “SFP” OPTICAL MODULES OPTO TRX 1.25GBE SFP–LX 1000B–LX OPTO TRX 1.25GBE SFP–SX 1000B–SX

1AB 18728 0001

1000B

OPTO TRX 1.25GBE SFP–ZX 1000B–ZX

1AB 18728 0002

1AB 18728 0028

STM–1 “SFP” OPTICAL MODULES OPTO TRX SFP S–1.1

100B

STM–4 “SFP” OPTICAL MODULES OPTO TRX SFP S–4.1

S S–4.1

STM–16 “SFP” OPTICAL MODULES (Black and white) OPTO TRX SFP S–16.1

SS–161

1AB 19637 0001

OPTO TRX SFP L–16.1

SL–161

1AB 19637 0004

OPTO TRX SFP L–16.2

SL–162

1AB 19637 0003

–– 4

––

58

––

CWDM “SFP” OPTICAL MODULES (colored) CWDM 1470 NM PIN PLUGIN

SS–162C

1AB 19634 0001

CWDM 1490 NM PIN PLUGIN

SS–162C

1AB 19634 0002

CWDM 1510 NM PIN PLUGIN

SS–162C

1AB 19634 0003

CWDM 1530 NM PIN PLUGIN

SS–162C

1AB 19634 0004

1AA 00014 0004 (9007) A4 – ALICE 04.10

16 CWDM 1550 NM PIN PLUGIN

SS–162C

1AB 19634 0005

CWDM 1570 NM PIN PLUGIN

SS–162C

1AB 19634 0006

CWDM 1590 NM PIN PLUGIN

SS–162C

1AB 19634 0007

CWDM 1610 NM PIN PLUGIN

SS–162C

1AB19634 0008

ED

––

58

02 3AL 91668 AA AA 636

99 / 636

ANV Part Number (Factory Part Number)

CWDM 1470 NM APD PLUGIN

SL–162C

1AB19635 0001

CWDM 1490 NM APD PLUGIN

SL–162C

1AB19635 0002

CWDM 1510 NM APD PLUGIN

SL–162C

1AB19635 0003

CWDM 1530 NM APD PLUGIN

SL–162C

1AB19635 0004

1AA 00014 0004 (9007) A4 – ALICE 04.10

CWDM 1550 NM APD PLUGIN

SL–162C

1AB19635 0005

CWDM 1570 NM APD PLUGIN

SL–162C

1AB19635 0006

CWDM 1590 NM APD PLUGIN

SL–162C

1AB19635 0007

CWDM 1610 NM APD PLUGIN

SL–162C

1AB19635 0008

ED

Max. Qty

SLOT

NOTES

16

––

58

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

ACRONYM

NAME

02 3AL 91668 AA AA 636

100 / 636

1AA 00014 0004 (9007) A4 – ALICE 04.10

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

NAME

ACRONYM

ANV Part Number (Factory Part Number)

Max. Qty

SLOT

NOTES

EQUICO

3AL78836AA–– (411.100.708V)

1

22

59

MATRIXN

3AL78848BA–– (411.101.244 G)

2

23,40

60

MEM–DEV

1AB 17634 0002 ––––

1

––

61

CONTROLLER EQUIPMENT CONTROLLER MATRIX MATRIX /1 FLASH CARD FLASH CARD 256 MB –20/85° C

(End of table)

ED

02 3AL 91668 AA AA 636

101 / 636

Table 16. Accessories list ACRONYM

ANV Part Number (Factory Part Number)

Max. Qty

SLOT

DUMMY PLATE W20

––

3AN49397AA–– (299.701.587 J)

32

––

DUMMY PLATE W30

––

3AN49399AA–– (299.701.590 Z)

1

––

DUMMY PLATE W35

––

3AN49400AA–– (299.701.591 N)

1

––

TELEPHONE HANDSET

––

1AF00398AA–– (013.200.016A)

1

––

65

S9 INSTALLATION KIT

––

3AL78913AA– (299.701.333 S)

1

––

66

OPTINEX RACK INST. KIT X OMSN

––

3AL79463AA–– (299.701.747 H)

1

––

67

40A 72V CIRCUIT BREAKER

––

2

––

68

15A 72V CIRCUIT BREAKER

––

1AB016271 0006 (001.791.356 L)

2

––

69

16A CIRCUIT BREAKER

––

1AB024380012 (001.700.121 J)

2

––

70

4A 72Vdc CIRCUIT BREAKER

––

1AB 162710003 (001.791.353 R)

2

––

71

4A CIRCUIT BREAKER

––

1AB 024380010 (001700122K)

2

––

72

19” / 21” ADAPTER KIT

––

3CA 08540 AA–– (299.701.597 L)

1

––

73

CAPS ESD COMMON PART OMSN

––

3AL 79266 AA–– (299.701.877 U)

1

––

CAPS ESD 1.0/2.3 OMSN

––

3AL 79267 AA–– (299.701.878 D)

38

––

CAPS ESD SUB/D OMSN

––

3AL 79268 AA–– (299.701.879 E)

6

––

CASE EMC 1.0/2.3 FOR CABLE 3.6 mm

––

3AL 80915 AA–– (298.701.209 N)

64

––

75

120 OHM KIT FOR CABLE SUPPORT

––

3AN 50125 AA–– (299.701.063 X)

2

––

76

SM JUMPER FC/PC 1,35 MT

––

16

––

77

NOTES All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

NAME

1AA 00014 0004 (9007) A4 – ALICE 04.10

EQUIPMENT ACCESSORIES

SM JUMPER SC/PC 1,35 MT

ED

––

1AB16271 0015

62 63 64

74

1AB 07984 0025 1AB 08001 0065

02 3AL 91668 AA AA 636

102 / 636

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

NAME

ACRONYM

ANV Part Number (Factory Part Number)

Max. Qty

SLOT

NOTES

KIT T_BUS UPGRADE FOR ISA APPLICATION

––

3AL 81202 AA (299.701.228 H)

1

––

78

KIT SM/MM 50 um PATCH CORD

––

3AL 81465 AA–– (299.701.237 S)

64

––

79

KIT SM/MM 62.5 um PATCH CORD

––

3AL 81466 AA–– (299.701.2378B)

64

––

79

KIT–CABLING ETHERNET

––

3AL 81639 AA––

1

––

80

120 OHM NEW CONNECTOR KIT

––

3AL80834 AA–– (299.701.066 S)

54

––

81

1.0/2.3 COAXIAL CONNECTOR (3mm)

––

1AB061220003 (040.144.001N)

764

––

82

1.0/2.3 MALE COAXIAL CONNECTOR 75 OHM (3.6 mm)

––

1AB009720049 ––

128

––

83

1.0/2.3 MALE COAXIAL CONNECTOR BALUN

––

1AB158340001 (040.144.010J)

8

––

84

RJ45 MALE CONNECTORS 8 WIRES IDC CAT. 6

––

1AB074610019 ––

300

––

85

TBUS

3AL 79088 AC–– (487.166.408 B)

1

–

EXTRACTORS KIT

––

3AL 79497 AA–– (299.701.341 A)

1

––

SFP MODULE PLUG–IN TOOL

––

3AL 81728 AA––

1

––

DUST FILTER FOR FAN SHELF 19”

––

3AL 80371 AA–– (299.908.007 Y)

2

––

OFFICE SIDE ACCESSORIES

SPARE PARTS TERMINATION BUS/2

SOFTWARE

86

1AA 00014 0004 (9007) A4 – ALICE 04.10

(End of table)

ED

02 3AL 91668 AA AA 636

103 / 636

2.2.2 Fans Subrack 19” part list

NAME

ACRONYM

ANV Part Number (Factory Part Number)

Max. Qty

SLOT

SRFAN

3AL79773AA–– (593.153.008 A)

1

–

FAN

3AL 79772 AA–– (411.101.423 L)

4

0,1,2,3

––

3AL 80371 AA–– (299.908.007 Y)

2

4,5

––

3AL 81812 AA––

2

4.5

NOTES

MECHANICAL STRUCTURE FANS SHELF 19” ACCESSORIES FAN UNIT FOR FAN SHELF 19” DUST FILTER SHELF 19”

FOR

METALLIC FAN GRID

FAN

87

1AA 00014 0004 (9007) A4 – ALICE 04.10

(End of table)

ED

02 3AL 91668 AA AA 636

104 / 636

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

Table 17. Fans Subrack 19” part list

2.2.3 Explanatory notes

1AA 00014 0004 (9007) A4 – ALICE 04.10

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

Table 18. Explanatory notes Note

ED

Explanation

1

It is the main shelf of the equipment, also with the back panel

2

Mandatory unit. Used to provide voltage logical reference to all Control and Auxiliary bus.

3

Extractors used to remove the SFP module.

4

As Low Speed ports are intended the 2 Mbit/s speed ports

5

To be used with the LS access cards. Three access cards are needed to fully connect the port’s channel. The P63E1, P63E1N–M4 spare port must be inserted in slot 32.

6

The board supports the NT functionality, performance monitoring, Retiminig and Frame Slip functionalities.

7

As High Speed PDH ports are intended the 34 Mbit/s and the 45 Mbit/s ports

8

The same board can be used as 3x34 Mbit/s or 3x45Mbit/s but its corresponding access cards are separated (i.e A3E3 for 3x34 Mbit/s and A3T3 for 3x45 Mbit/s)

9

As High Speed SDH ports are intended STM–1, STM–4, STM–16 ports

10

The port needs an access card with 4 STM–1 electrical interfaces

11

Each port of this board can be configured as 140 Mbit/s or STM–1.

12

The port needs four (electrical or optical) modules to reach the maximum capability of four channels. Two modules have to be inserted on the card front panel and two on the corresponding access card 2 x STM–1 front panel (A2S1). Notice that different kind of access module (electrical and optical, also of different characteristic and connectors) can be inserted in the port card or in the access card

13

The unit is two slot wide and it can house up to 4 optical modules (OH–I, OL–IN, OH–MM, OL– MM). For details about the max. board capabilty refer to paragraph 3.10 on page 282.

14

The ports does not need access card

15

Ports supplied with different connectors types

16

The board is used in conjunction with ISA–PR board and does not support Low Order traffic termination. Two modules have to be inserted on the card front panel. Notice that different kind of STM–4 modules (also of different characteristic and connectors) can be inserted in the port card .

17

STM–16 port is two slot wide

18

Ports to be used with the Booster

19

The board is used to interconnect distances less than approximately 2Km (intra–office application)

20

The unit is two slot wide and must be equipped with removable SFP optical module. Refer to Figure 72. on page 161 for relationship between SFP modules and relevant Housing board.

21

Port used as input for the WDM equipment (blue band)

22

Port used as input for the WDM equipment (red band)

02 3AL 91668 AA AA 636

105 / 636

23

The board has #11 RJ45 interfaces

24

The board can be equipped with up to four 1.25 Gbit/s Modules. Refer to Figure 72. on page 161 for relationship between SFP modules and relevant Housing board. The max. quantity of GETH–MB units that can be equipped depends on the CONGI type present in the subrack as indicated in the folllowing: a) 8 GETH–MB units if CONGI type 3AL 78830 AB–– is equipped in the subrack b) 8 GETH–MB units if CONGI type 3AL 78830 AC–– is equipped in the subrack c) 6 GETH–MB units if CONGI type 3AL 78830 AA–– is equipped in the subrack

1AA 00014 0004 (9007) A4 – ALICE 04.10

25

ED

Explanation

26

The unit provides a STM–1 interface on the front coverplate. It manages up to 16 ports configurable as: SDH VC–4, SDH VC–3, SDH VC–12, PDH 34M, PDH 2M. The max throughput towards backpanel is 622 Mbit/s. The unit supports the PNNI.

27

It manages up to 252 ports configurable as: SDH VC–4, SDH VC–3, SDH VC–12, PDH 45M, PDH 34M, PDH 2M. The max throughput towards backpanel is 622 Mbit/s. The unit supports the IMA.

28

It manages up to 16 ports configurable as: SDH VC–4, SDH VC–3, SDH VC–12, PDH 45M, PDH 34M, PDH 2M. The max throughput towards backpanel is 622 Mbit/s. The unit supports the IMA.

29

The board is two slot wide. It manages up to 16+16 ports configurable as: SDH VC–4, SDH VC4–C, SDH VC–3, SDH VC–12, PDH 45M, PDH 34M, PDH 2M. The max throughput towards backpanel is 1.2 Gbit/s. The unit supports the PNNI.

30

With a max. data throughput of 1Gb/s, it allows the transportation of MPLS packets over SDH, their routing, and the traffic congestion management. It hosts, further, 4x 10/100BaseT interfaces carring MPLS over ethernet.

31

With a max. data throughput of 1.6 Gb/s, it allows the transportation of MPLS packets over SDH, their routing, and the traffic congestion management. The board can be equipped with one 1.25 Gbit/s Modules. Refer to Figure 72. on page 161 for relationship between SFP modules and relevant Housing board.

32

The board is two slot wide. With a max. data throughput of 6.5 Gb/s data throughput, it allows the transportation of ethernet packets over SDH, their routing, and the traffic congestion management. It hosts four STM4 SFP optical modules interfacing physical line (Refer to Figure 72. on page 161 for relationship between SFP modules and relevant Housing board). Two access cards max are used for each PR board. Mixed access cards configuration are allowed.

33

The unit must be equipped with SFP optical module. Refer to Figure 72. on page 161 for relationship between SFP modules and relevant Housing board.

34

The unit can be equipped with one SFP 1.25 Gbit/s Modules. Refer to Figure 72. on page 161 for relationship between SFP modules and relevant Housing board.

02 3AL 91668 AA AA 636

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All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

Note

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

Note

Explanation

35

The board must be equipped with SFP optical module “colored” (1470 – 1610 nm) or “Black and White”. The max. number of SFP module per board is equal to four. Refer to Figure 72. on page 161 for relationship between SFP modules and relevant Housing board.

36

Protected LS access card . Allow the bidirectional connection of up to twenty–one 2 Mbit/s channels. To be used in EPS protected configurations.

37

Compliant with ITU K20 norms

38

HS access card dedicated to the 3x34 port. Allows the bidirectional connection of up to three 34 Mbit/s channels.

39

HS access card dedicated to the 3x45 port. Allows the bidirectional connection of up to three 45 Mbit/s channels.

40

HS access card to be used for the 4 x STM–1 electrical port. Allows the bidirectional connection of up to 4 channels

41

To be used in an EPS protection scheme as access card for the HS electrical spare port. (3x34 Mbit/s, 3x45 Mbit/s and 155 Mbit/s)

42

The access card needs up to 2 optical or electrical modules to be inserted inside

43

The board has #14 RJ45 interfaces.

44

The board can be used in conjunction with the ETH–MB. If used in conjunction with ETH–MB the access card provides up to two Gigabit Ethernet Interface; in this configuration only the two upper interfaces present on the access card can be used for Gbit Ethernet application. For details on slot position refer to Table 25. on page 116.

1AA 00014 0004 (9007) A4 – ALICE 04.10

The access card can be equipped with SFP Optical module. Refer to Figure 72. on page 161 for relationship between SFP modules and relevant Housing board.

ED

45

The board has 16 RJ45 interfaces at 10/100 Mbit/s. It is used in conjunction with the ISA–PR Card for data access.

46

The board has 2 plug–in interfaces at 1 Gbit/s (Refer to Figure 72. on page 161 for relationship between SFP modules and relevant Housing board) It is used in conjunction with the ISA–PR Card for data access.

47

A max of two Control and General interfaces can be used. Delivers two voltage levels to all the cards. Provides external connectors for housekeepings, remote alarms, rack lamps, Q interface, LAN interface. If two CONGI cards are inserted, they provide different interfaces.

48

Provides the connectors for the auxiliary , EOW channels and the synchronization interfaces.

49

The board is two slot wide

50

Up to 2 of these modules are inserted on the following cards : P4E4N, P4S1N and A2S1 to realize optical connections for a maximum of 2 STM–1 channels. Only one of these modules can be inserted in the ATM matrix 4X4. With the MM1 module must be ordered also the specific patch cord in order to reach the multimode characteristics (50um patch cord or 62 um patch cord).

51

Optical modules supplied with different connectors.

52

Optical modules to be used with the Booster

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1AA 00014 0004 (9007) A4 – ALICE 04.10

ED

Explanation

53

Up to 2 of these modules are inserted on the following cards : P4E4N, P4S1N and A2S1 to realize electrical connections for a maximum of 2 STM–1 or 140 Mbit/s channels . Only one of these modules can be inserted in the ATM matrix 4X4.

54

Up of 2 of these modules are inserted on the P4S4N card to realize optical connections for a maximum of 2 STM–4 channels (one for module).Optical modules supplied with different connectors (SC/PC or FC/PC).

55

Used for: Fiber Channel, FICON, Gigabit Ethernet

56

Used for: Fast Ethernet, FDDI, ESCON, Digital Video.

57

Due to access limitation only two of this modules can be equipped when GETH–AG is used in conjunction with ETH–MB.

58

Refer to Figure 72. on page 161 for relationship between SFP modules and relevant Housing board.

59

Equipment Controller card provides the F interface for the Craft Terminal connection

60

Two MATRIX cards can be used in a 1+1 protected EPS configuration. The card performs connection and cross–connection functionalities and moreover synchronization functionalities.

61

It contains the equipment data base . To be used for running “SDH” and “ATM” software

62

It is essential to insert the relevant dummy plates on the spaces left by the port or access modules units not supplied in order to obtain the EMI/EMC performances.

63

Dummy plate for unequipped SERVICES I/F unit

64

Dummy plate for unequipped MATRIX unit

65

Optional telephone handset associated to the SERVICES I/F card.

66

Set needed to install in the S9 rack.

67

It is necessary when Optinex rack is employed

68

To be used with 3AL 78830 AD–– CONTROL AND GENERAL INTERFACE

69

To be used for external subrack protection when OPTINEX rack is used

70

To be used for external subrack protection when S9 rack is used

71

To be used in Optinex rack (TRU) to power the Fan Shelf

72

To be used in S9 rack (TRU) to power the Fan Shelf

73

Mechanical adaptor utilized to insert the subrack in “21” rack.

74

Protection cups to be used to respect the ESD precaution. At the end of the installation phase all the connectors not used for cabling must be covered with the relevant “protection caps”

75

To be used for EMC performance. One for each 140/155 ELECTRICAL INTERFACE (ICMI)

76

To be installed when 120 Ohm connector are used for 2Mbit/s signals.

77

Must be provided with optical boosters in order to perform connection with STM–4 or STM–16 ports.

78

Upgrade for ATM functionality.

79

Must be used in conjunction with “STM–1 MULTIMODE OPT SC/PC” Optical Module

02 3AL 91668 AA AA 636

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Note

1AA 00014 0004 (9007) A4 – ALICE 04.10

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

ED

Note

Explanation

80

Cable duct to be used during the installation phase. It allows the electrical cables separation from the optical cables.

81

Every kit contains #1 connectors for 7x2 Mbit/s interface 120 Ohm

82

To be used for the 2 Mbit/s connections and for the synchronism on SERVICES I/F card.

83

To be used for the 34/45 Mbit/s and STM–1 electrical connections

84

To be used only with SERVICES I/F port card. It allows the 75/120 Ohm conversion.

85

To be used with the relevant cable, in the installation phase for connections to Ethernet port.

86

Details concerning the software P/N are given in the Operator’s Handbook.

87

Can be used as alternative to the “Dust filter for fan shelf 19”; It doesn’t require maintenance.

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Table 19. Relationship between P63E1, P63E1N–M4 (63 X 2 Mbit/s unit) port card and A21E1 access card Port Card acronym

Port Card Slot

24

27

30

P63E1, P63E1N–M4

32 (spare)

33

36

1AA 00014 0004 (9007) A4 – ALICE 04.10

39

ED

Access Card acronym

Access Card Slot

A21E1

1 (CH. 1–21)

A21E1

2 (CH. 22–42)

A21E1

3 (CH. 43–63)

A21E1

4 (CH. 1–21)

A21E1

5 (CH. 22–42)

A21E1

6 (CH. 43–63)

A21E1

7 (CH. 1–21)

A21E1

8 (CH. 22–42)

A21E1

9 (CH. 43–63)

––––––

––––––

A21E1

13 (CH. 1–21)

A21E1

14 (CH. 22–42)

A21E1

15 (CH. 43–63)

A21E1

16 (CH. 1–21)

A21E1

17 (CH. 22–42)

A21E1

18 (CH. 43–63)

A21E1

19 (CH. 1–21)

A21E1

20 (CH. 22–42)

A21E1

21 (CH. 43–63)

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2.3 Relationship between Port Card and Access Card

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

Table 20. Relationship between P3E3T3 (3X34/45 Mbit/s Switchable unit) port card and A3E3 access card (3X34 Mbit/s) Port Card acronym

Port Card Slot

Access Card acronym

Access Card Slot

P3E3T3

24

A3E3

2 (CH. 1–3)

P3E3T3

25

A3E3

3 (CH. 1–3)

P3E3T3

26

A3E3

4 (CH. 1–3)

P3E3T3

27

A3E3

5 (CH. 1–3)

P3E3T3

28

A3E3

6 (CH. 1–3)

P3E3T3

29

A3E3

7 (CH. 1–3)

P3E3T3

30

A3E3

8 (CH. 1–3)

P3E3T3

31

A3E3

9 (CH. 1–3)

P3E3T3

32

A3E3

13 (CH. 1–3)

P3E3T3

33

A3E3

14 (CH. 1–3)

P3E3T3

34

A3E3

15 (CH. 1–3)

P3E3T3

35

A3E3

16 (CH. 1–3)

P3E3T3

36

A3E3

17 (CH. 1–3)

P3E3T3

37

A3E3

18 (CH. 1–3)

P3E3T3

38

A3E3

19 (CH. 1–3)

P3E3T3

39

A3E3

20 (CH. 1–3)

One or more 1+N (N ≤15) EPS revertive protection scheme can be created (for more detail see point [3] of para. 3.13.1 on page 311). In case of EPS configuration the following configuration rules must be respected: –

Insert the protecting port card in a slot at the most left of of the protected port cards group.

–

Insert the special protection access card (HPROT) associated to the protecting port card following the rule reported in Table 20. on page 111 ( for example if the “protecting port card” has been inserted in slot 24, the ” protection access card HPROT” must be inserted in slot 2).

1AA 00014 0004 (9007) A4 – ALICE 04.10

The max. number of EPS groups is 8 i.e. 8 cards each protected 1+1 revertive. For each group a HPROT access card is required therefore the max number of HPROT access cards is 8.

ED

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Table 21. Relationship between P3E3T3 (3X34/45 Mbit/s Switchable unit) port card and A3T3 access card (3X45 Mbit/s) Port Card Slot

Access Card acronym

Access Card Slot

P3E3T3

24

A3T3

2 (CH. 1–3)

P3E3T3

25

A3T3

3 (CH. 1–3)

P3E3T3

26

A3T3

4 (CH. 1–3)

P3E3T3

27

A3T3

5 (CH. 1–3)

P3E3T3

28

A3T3

6 (CH. 1–3)

P3E3T3

29

A3T3

7 (CH. 1–3)

P3E3T3

30

A3T3

8 (CH. 1–3)

P3E3T3

31

A3T3

9 (CH. 1–3)

P3E3T3

32

A3T3

13 (CH. 1–3)

P3E3T3

33

A3T3

14 (CH. 1–3)

P3E3T3

34

A3T3

15 (CH. 1–3)

P3E3T3

35

A3T3

16 (CH. 1–3)

P3E3T3

36

A3T3

17 (CH. 1–3)

P3E3T3

37

A3T3

18 (CH. 1–3)

P3E3T3

38

A3T3

19 (CH. 1–3)

P3E3T3

39

A3T3

20 (CH. 1–3)

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

Port Card acronym

One or more 1+N (N ≤15) EPS revertive protection scheme can be created (for more detail see point [3] of para. 3.13.1 on page 311). In case of EPS configuration the following configuration rules must be respected: –

Insert the protecting port card in a slot at the most left of of the protected port cards group.

–

Insert the special protection access card (HPROT) associated to the protecting port card following the rule reported in Table 20. on page 111 ( for example if the “protecting port card” has been inserted in slot 24, the ” protection access card HPROT” must be inserted in slot 2).

1AA 00014 0004 (9007) A4 – ALICE 04.10

The max. number of EPS groups is 8 i.e. 8 cards each protected 1+1 revertive. For each group a HPROT access card is required therefore the max number of HPROT access cards is 8.

ED

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1AA 00014 0004 (9007) A4 – ALICE 04.10

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

Table 22. Relationship between P4S1N, P4E4N, P4OC3 port card and A2S1 access card

ED

Port Card acronym

Port Card Slot

Access Card acronym

Access Card Slot

P4E4N, P4S1N, P4OC3 (CH. 1–2)

24

A2S1

2 (CH. 3–4)

P4E4N, P4S1N, P4OC3 (CH. 1–2)

25

A2S1

3 (CH. 3–4)

P4E4N, P4S1N, P4OC3 (CH. 1–2)

26

A2S1

4 (CH. 3–4)

P4E4N, P4S1N, P4OC3 (CH. 1–2)

27

A2S1

5 (CH. 3–4)

P4E4N, P4S1N, P4OC3 (CH. 1–2)

28

A2S1

6 (CH. 3–4)

P4E4N, P4S1N, P4OC3 (CH. 1–2)

29

A2S1

7 (CH. 3–4)

P4E4N, P4S1N, P4OC3 (CH. 1–2)

30

A2S1

8 (CH. 3–4)

P4E4N, P4S1N, P4OC3 (CH. 1–2)

31

A2S1

9 (CH. 3–4)

P4E4N, P4S1N, P4OC3 (CH. 1–2)

32

A2S1

13 (CH. 3–4)

P4E4N, P4S1N, P4OC3 (CH. 1–2)

33

A2S1

14 (CH. 3–4)

P4E4N, P4S1N, P4OC3 (CH. 1–2)

34

A2S1

15 (CH. 3–4)

P4E4N, P4S1N, P4OC3 (CH. 1–2)

35

A2S1

16 (CH. 3–4)

P4E4N, P4S1N, P4OC3 (CH. 1–2)

36

A2S1

17 (CH. 3–4)

P4E4N, P4S1N, P4OC3 (CH. 1–2)

37

A2S1

18 (CH. 3–4)

P4E4N, P4S1N, P4OC3 (CH. 1–2)

38

A2S1

19 (CH. 3–4)

P4E4N, P4S1N, P4OC3 (CH. 1–2)

339

A2S1

20 (CH. 3–4)

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Table 23. Relationship between P4ES1N (4xSTM–1 Electrical) port card and A4ES1 access card. Port Card Slot

Access Card acronym

Access Card Slot

P4ES1N

24

A4ES1

2 (CH. 1 to 4)

P4ES1N

25

A4ES1

3 (CH. 1 to 4)

P4ES1N

26

A4ES1

4 (CH. 1 to 4)

P4ES1N

27

A4ES1

5 (CH. 1 to 4)

P4ES1N

28

A4ES1

6 (CH. 1 to 4)

P4ES1N

29

A4ES1

7 (CH. 1 to 4)

P4ES1N

30

A4ES1

8 (CH. 1 to 4)

P4ES1N

31

A4ES1

9 (CH. 1 to 4)

P4ES1N

32

A4ES1

13 (CH. 1 to 4)

P4ES1N

33

A4ES1

14 (CH. 1 to 4)

P4ES1N

34

A4ES1

15 (CH. 1 to 4)

P4ES1N

35

A4ES1

16 (CH. 1 to 4)

P4ES1N

36

A4ES1

17 (CH. 1 to 4)

P4ES1N

37

A4ES1

18 (CH. 1 to 4)

P4ES1N

38

A4ES1

19 (CH. 1 to 4)

P4ES1N

39

A4ES1

20 (CH. 1 to 4)

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

Port Card acronym

One or more 1+N (N ≤15) EPS revertive protection scheme can be created (for more detail see point [3] of para. 3.13.1 on page 311). In case of EPS configuration the following configuration rules must be respected: –

Insert the protecting port card in a slot at the most left of of the protected port cards group.

–

Insert the special protection access card (HPROT) associated to the protecting port card following the rule reported in Table 20. on page 111 ( for example if the “protecting port card” has been inserted in slot 24, the ” protection access card HPROT” must be inserted in slot 2).

The max. number of EPS groups is 8 i.e. 8 cards each protected 1+1 revertive. For each group a HPROT access card is required therefore the max number of HPROT access cards is 8.

1AA 00014 0004 (9007) A4 – ALICE 04.10

The STM–4 and STM–16 high speed port card does not need Access Card because the physical termination of the channel is on the port itself.

ED

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1AA 00014 0004 (9007) A4 – ALICE 04.10

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

Table 24. Relationship between ETH–MB (11x10/100 Mb/s Ethernet) port card and ETH–ATX access card. Port Card acronym

Port Card Slot

Access Card acronym

Access Card Slot

ETH–MB (CH. 1 to 11)

24

ETH–ATX

2 (CH. 12 to 25)

ETH–MB (CH. 1 to 11)

25

ETH–ATX

3 (CH. 12 to 25)

ETH–MB (CH. 1 to 11)

26

ETH–ATX

4 (CH. 12 to 25)

ETH–MB (CH. 1 to 11)

27

ETH–ATX

5 (CH. 12 to 25)

ETH–MB (CH. 1 to 11)

28

ETH–ATX

6 (CH. 12 to 25)

ETH–MB (CH. 1 to 11)

29

ETH–ATX

7 (CH. 12 to 25)

ETH–MB (CH. 1 to 11)

30

ETH–ATX

8 (CH. 12 to 25)

ETH–MB (CH. 1 to 11)

31

ETH–ATX

9 (CH. 12 to 25)

ETH–MB (CH. 1 to 11)

32

ETH–ATX

13 (CH. 12 to 25)

ETH–MB (CH. 1 to 11)

33

ETH–ATX

14 (CH. 12 to 25)

ETH–MB (CH. 1 to 11)

34

ETH–ATX

15 (CH. 12 to 25)

ETH–MB (CH. 1 to 11)

35

ETH–ATX

16 (CH. 12 to 25)

ETH–MB (CH. 1 to 11)

36

ETH–ATX

17 (CH. 12 to 25)

ETH–MB (CH. 1 to 11)

37

ETH–ATX

18 (CH. 12 to 25)

ETH–MB (CH. 1 to 11)

38

ETH–ATX

19 (CH. 12 to 25)

ETH–MB (CH. 1 to 11)

39

ETH–ATX

20 (CH. 12 to 25)

ED

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Port Card acronym

Port Card Slot

Access Card acronym

Access Card Slot (N.B.)

ETH–MB (10/100 Mb CH.1 to 11)

24

GETH–AG

2 (Gigabit CH. 1 and 2)

ETH–MB (10/100 Mb CH.1 to 11)

25

GETH–AG

3 (Gigabit CH. 1 and 2)

ETH–MB (10/100 Mb CH.1 to 11)

26

GETH–AG

4 (Gigabit CH. 1 and 2)

ETH–MB (10/100 Mb CH.1 to 11)

27

GETH–AG

5 (Gigabit CH. 1 and 2)

ETH–MB (10/100 Mb CH.1 to 11)

28

GETH–AG

6 (Gigabit CH. 1 and 2)

ETH–MB (10/100 Mb CH.1 to 11)

29

GETH–AG

7 (Gigabit CH. 1 and 2)

ETH–MB (10/100 Mb CH.1 to 11)

30

GETH–AG

8 (Gigabit CH. 1 and 2)

ETH–MB (10/100 Mb CH.1 to 11)

31

GETH–AG

9 (Gigabit CH. 1 and 2)

ETH–MB (10/100 Mb CH.1 to 11)

32

GETH–AG

13 (Gigabit CH. 1 and 2)

ETH–MB (10/100 Mb CH.1 to 11)

33

GETH–AG

14 (Gigabit CH. 1 and 2)

ETH–MB (10/100 Mb CH.1 to 11)

34

GETH–AG

15 (Gigabit CH. 1 and 2)

ETH–MB (10/100 Mb CH.1 to 11)

35

GETH–AG

16 (Gigabit CH. 1 and 2)

ETH–MB (10/100 Mb CH.1 to 11)

36

GETH–AG

17 (Gigabit CH. 1 and 2)

ETH–MB (10/100 Mb CH.1 to 11)

37

GETH–AG

18 (Gigabit CH. 1 and 2)

ETH–MB (10/100 Mb CH.1 to 11)

38

GETH–AG

19 (Gigabit CH. 1 and 2)

ETH–MB (10/100 Mb CH.1 to 11)

39

GETH–AG

20 (Gigabit CH. 1 and 2)

N.B.

The following channels are made available (max quantity) when GETH–AG is used in conjunction with ETH–MB:

1AA 00014 0004 (9007) A4 – ALICE 04.10

–

–

ED

up to two Gigabit Ethernet interface on the access card GETH–AG;in this configuration only the two upper interfaces present on the access card can be used for Gbit Ethernet application. up to eleven 10/100 Mbit Ethernet interfaces on the ETH–MB.

02 3AL 91668 AA AA 636

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Table 25. Relationship between ETH–MB (10/100Mb) port card and GETH–AG (1.25 Gb/s) access card.

1AA 00014 0004 (9007) A4 – ALICE 04.10

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Table 26. Relationship between ISA ES–16 port card and and ETH–ATX access card.

ED

Port Card acronym

Port Card Slot

Access Card acronym

Access Card Slot

ISA ES–16

24

ETH–ATX

2

ISA ES–16

25

ETH–ATX

3

ISA ES–16

26

ETH–ATX

4

ISA ES–16

27

ETH–ATX

5

ISA ES–16

28

ETH–ATX

6

ISA ES–16

29

ETH–ATX

7

ISA ES–16

30

ETH–ATX

8

ISA ES–16

31

ETH–ATX

9

ISA ES–16

32

ETH–ATX

13

ISA ES–16

33

ETH–ATX

14

ISA ES–16

34

ETH–ATX

15

ISA ES–16

35

ETH–ATX

16

ISA ES–16

36

ETH–ATX

17

ISA ES–16

37

ETH–ATX

18

ISA ES–16

38

ETH–ATX

19

ISA ES–16

39

ETH–ATX

20

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1AA 00014 0004 (9007) A4 – ALICE 04.10

Table 27. Relationship between ISA ES–16 port card and and GETH–AG access card.

ED

Port Card Slot

Access Card acronym

Access Card Slot

ISA ES–16

24

GETH–AG

2

ISA ES–16

25

GETH–AG

3

ISA ES–16

26

GETH–AG

4

ISA ES–16

27

GETH–AG

5

ISA ES–16

28

GETH–AG

6

ISA ES–16

29

GETH–AG

7

ISA ES–16

30

GETH–AG

8

ISA ES–16

31

GETH–AG

9

ISA ES–16

32

GETH–AG

13

ISA ES–16

33

GETH–AG

14

ISA ES–16

34

GETH–AG

15

ISA ES–16

35

GETH–AG

16

ISA ES–16

36

GETH–AG

17

ISA ES–16

37

GETH–AG

18

ISA ES–16

38

GETH–AG

19

ISA ES–16

39

GETH–AG

20

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Port Card acronym

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1AA 00014 0004 (9007) A4 – ALICE 04.10

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Table 28. Relationship between ISA–PR port card and 16FEA–PR or 2GBA–PR access cards.

ED

Port Card acronym

Port Card Slot

Access Card acronym

Access Card Slot

ISA–PR

25–26

16FEA–PR or 2GBA–PR

2 –3 3–4 4–5

left middle right

ISA–PR

26–27

16FEA–PR or 2GBA–PR

3–4 4–5 5–6

left middle right

ISA–PR

27–28

16FEA–PR or 2GBA–PR

4–5 5–6 6–7

left middle right

ISA–PR

28–29

16FEA–PR or 2GBA–PR

5–6 6–7 7–8

left middle right

ISA–PR

29–30

16FEA–PR or 2GBA–PR

6–7 7–8 8–9

left middle right

ISA–PR

30–31

16FEA–PR or 2GBA–PR

7–8 8–9 9 – 10

left middle right

ISA–PR

31–32

16FEA–PR or 2GBA–PR

8–9 9 – 10 13 –14

left middle right

ISA–PR

32–33

16FEA–PR or 2GBA–PR

12 – 13 13 – 14 14 – 15

left middle right

ISA–PR

33–34

16FEA–PR or 2GBA–PR

13 – 14 14 – 15 15 – 16

left middle right

ISA–PR

34–35

16FEA–PR or 2GBA–PR

14 – 15 15 – 16 16 – 17

left middle right

ISA–PR

35–36

16FEA–PR or 2GBA–PR

15 – 16 16 – 17 17 – 18

left middle right

ISA–PR

36–37

16FEA–PR or 2GBA–PR

16 – 17 17 – 18 18 –19

left middle right

ISA–PR

37–38

16FEA–PR or 2GBA–PR

17 – 18 18 – 19 19 – 20

left middle right

ISA–PR

38–39

16FEA–PR or 2GBA–PR

18 – 19 19 – 20 20 – 21

left middle right

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The following paragraph show the access points (LEDs, switches etc.) present on each unit together with legenda and meaning. More in detail: Paragraph 2.4.1 on page 121 shows the Port cards front view Paragraph 2.4.2 on page 145 shows the Access cards front view

1AA 00014 0004 (9007) A4 – ALICE 04.10

Paragraph 2.4.3 on page 165 shows the Fans subrack cover front view

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2.4 Units front view

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2.4.1 Port cards front view

ACRONYM

SLOTS

P63E1

24,27,30,32,33,36,39

P63E1N–M4

24,27,30,32,33,36,39

P3E3T3

24 to 39

P4ES1N

24 to 39

Multicolor LED:

xxxxxx

(1)

1AA 00014 0004 (9007) A4 – ALICE 04.10

Red led – local unit alarm Green led – in service unit Orange led –unit in Stand–by (EPS schema)

3AL XXXXX AA

LEGENDA (1)

Figure 32. PDH, SDH electrical ports front view

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SLOTS

P4S1N

24 to 39

P4E4N

24 to 39

P4OC3

24 to 39

LEGENDA

ÑÑÑ ÑÑÑ ÑÑÑ ÑÑÑ ÑÑÑ ÑÑÑ ÑÑÑ ÑÑÑ ÑÑÑ ÑÑÑ ÑÑÑ ÑÑÑ ÑÑÑ ÑÑÑ ÑÑÑ ÑÑÑ ÑÑÑ ÑÑÑ ÑÑÑ ÑÑÑ ÑÑÑ ÑÑÑ ÑÑÑ

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ACRONYM

(1)

(2)

(1) Channel # 1 (N.B.) (2) Channel # 2 (N.B.)

1AA 00014 0004 (9007) A4 – ALICE 04.10

xxxxxx

Red led – local unit alarm Green led – in service unit

3AL XXXXX AA

(3) Bicolor LED:

(3)

N.B.– The unit can be equipped with electrical or optical modules (see Figure 70. and Figure 71. ) Figure 33. 4 x STM–1, 4 x OC3 port : front view

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FC/PC

ACRONYM

SLOTS

S–4.1N

24 to 39

L–4.1N

24 to 39

L–4.2N

24 to 39

(2)

SC/PC

(2)

INPUT

INPUT

OUTPUT OUTPUT

LEGENDA (1) Laser restart Key

(1)

(1)

(2) Channel #1

1AA 00014 0004 (9007) A4 – ALICE 04.10

xxxxxx

(3)

3AL XXXXX AA

xxxxxx

Red led – Local unit alarm Green led – in service unit

3AL XXXXX AA

(3) Bicolor LED:

(3)

Figure 34. STM–4 optical port front view

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P4S4N

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ACRONYM

SLOTS 25–26 28–29 34–35 37–38

(1)

(2)

LEGENDA: (1) Channel # 1 (see NOTE) (2) Channel # 2 (see NOTE)

1AA 00014 0004 (9007) A4 – ALICE 04.10

Red led – local unit alarm Green led – in service unit

3AL XXXXX AA

(3) Bicolor LED: (3)

NOTE: the unit can be equipped with optical modules (see Figure 70. on page 159). Figure 35. 4 x STM–4 port card – front view

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FC/PC

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ACRONYM

S–16.1ND

SC/PC

SLOTS 25+26 28+29 34+35 37+38 (1)

(1)

L–16.1ND

25+26 28+29 34+35 37+38

L–16.2ND

25+26 28+29 34+35 37+38

INPUT OUTPUT

INPUT OUTPUT

(2)

(2)

LEGENDA

(3) Bicolor LED:

1AA 00014 0004 (9007) A4 – ALICE 04.10

Red led – Local unit alarm Green led – in service unit

(3)

xxxxxx xxxx 3AL XXXXX AA

(2) Channel #1

xxxxxx xxxx 3AL XXXXX AA

(1) Laser restart Key (3)

Figure 36. STM–16 optical front view

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SLOTS

I –16.1ND

25+26 28+29 34+35 37+38

(1)

INPUT

OUTPUT (2)

LEGENDA (1) Laser restart Key (2) Channel #1

1AA 00014 0004 (9007) A4 – ALICE 04.10

Red led – Local unit alarm Green led – in service unit

xxxxxx xxxx 3AL XXXXX AA

(3) Bicolor LED:

(3)

Figure 37. I–16 PORT SFF (intra–office)

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ACRONYM

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ACRONYM

SLOTS

CO–16

25+26 28+29 34+35 37+38

(1)

(2)

OUTPUT

INPUT

Note: the cavities must be equipped with SFP modules (refer to Figure 72. on page 161)

(1) Laser restart Key (2) Channel #1 (3) Bicolor LED:

xxxxxx xxxx 3AL XXXXX AA

LEGENDA

(3)

1AA 00014 0004 (9007) A4 – ALICE 04.10

Red led – Local unit alarm Green led – in service unit

Figure 38. STM–16 SFP port optical front view

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ACRONYM

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ATM4X4V2 ATM4X4D3

ATM4X4

SLOTS

ATM4X4 ATM4X4V2

(1)

24–39

ATM4X4D3

(2)

LEGENDA

1AA 00014 0004 (9007) A4 – ALICE 04.10

(1)

xxxxxx

(10)

3AL XXXXX AA

(9)

xxxxxx

Reset command Key Channel #1 (N.B.) Red LED – Urgent Alarm (Critical or Major) Red LED – Not Urgent alarm (Minor) Yellow LED – Alarm storing (Attended) Yellow LED – Abnormal condition Yellow LED – Indicative Alarm (Warning) Lamp test push–button Factory use only Multicolor LED: Red led – local unit alarm (INT) Green led – in service unit Orange led –unit in Stand–by (EPS schema)

3AL XXXXX AA

(1) (2) (3) (4) (5) (6) (7) (8) (9) (10)

(3) (4) (5) (6) (7) (8)

N.B.– The ATM4X4 unit can be equipped with electrical or optical STM–1 modules (see Figure 70. and Figure 71. ) Figure 39. ATM 4X4, ATM 4X4V2 and ATM4X4D3 cards – front view

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ACRONYM ATM8x8

SLOTS 24 – 38 (1)

LEGENDA (1)

Reset command Key

(2)

Red LED – Urgent Alarm (Critical or Major)

(3)

Red LED – Not Urgent alarm (Minor)

(4)

Yellow LED – Alarm storing (Attended)

(5)

Yellow LED – Abnormal condition

(6)

Yellow LED – Indicative Alarm (Warning)

(7)

Lamp test push–button

(8)

Factory use only

(9)

Multicolor LED: Red led – local unit alarm (INT) Green led – in service unit Orange led –unit in Stand–by (EPS schema)

(2) (3) (4) (5) (6) (7) (8)

(9)

1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 40. ATM 8X8 card – front view

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SLOTS

ETH–MB

24 to 39

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ACRONYM

(1) (2) (3) (4)

(5) (6) (7) (8)

(9) (10) (11) Not used (12)

LEGENDA (1) to (11) Ethernet Channels (13)

(13) Bicolor LED

1AA 00014 0004 (9007) A4 – ALICE 04.10

Red led – Local unit alarm Green led – in service unit

Figure 41. ISA – Ethernet port front view

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ACRONYM

SLOTS

GETH–MB

24 to 39

OUTPUT (1)

(2)

INPUT

(3)

(4) Note: the cavities must be equipped with SFP modules (refer to Figure 72. on page 161)

(6)

LEGENDA (1) to (4) are Gigabit Ethernet channels Note: the cavities must be equipped with Ethernet Optical Modules (refer toFigure 72. on page 161) (5)

(6): Factory use only

1AA 00014 0004 (9007) A4 – ALICE 04.10

(5) Bicolor LED: Red led – Local unit alarm Green led – in service unit

Figure 42. ISA– Gigabit ETHERNET board

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SLOTS

ES4–8FE

24 to 39

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ACRONYM

(11) OUTPUT

(10)

INPUT

(9)

(1) Note: the cavities must be equipped with SFP modules (refer toFigure 72. on page 161)

(2) (3) (4) (5) (6)

LEGENDA

(7)

(1) to (8) 10/100 Ethernet channels

(8)

(9) Gigabit Ethernet channel SFP (12)

(10) Factory use only (11) Microprocessor restart Key (12) Bicolor LED: Red led – Local unit alarm Green led – in service unit

1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 43. ISA – ES4–8FE port front view

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ACRONYM

SLOTS

ES1–8FE

24 to 39

(1) (2) (3) (4)

1 2 3

4

RJ45 connectors (5) (6) (7) (8)

5 6

7

8

12 34 56 78

(9)

LEGENDA (1) to (8) Ethernet channels (9) Channel status indicators: yellow : active channel yellow blinking: channel with traffic

(10) DBG

(11)

(10) Not used (11) Microprocessor restart Key (12)

1AA 00014 0004 (9007) A4 – ALICE 04.10

(12) Bicolor LED: Red led – Local unit alarm Green led – in service unit

Figure 44. ISA – ES1–8FE port front view

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SLOTS

ES1–8FX

24 to 39

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ACRONYM

(1)

(2)

OUTPUT

(3)

(4)

INPUT

(5)

(6)

(7)

(8)

LEGENDA

(9)

(1): Reset button (2 to 9): are cavity for Fast Ethernet optical SFP modules (Refer to Figure 72. on page 161)

(10)

1AA 00014 0004 (9007) A4 – ALICE 04.10

(10) Bicolor LED: Red led – Local unit alarm Green led – in service unit

Figure 45. ISA ES–8FX front view

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ACRONYM

SLOTS

ISA–ES16

24 to 39 (1)

MAJ MIN uP

(2) (3) (4)

(5) ETH (6) LEGENDA (1) Microprocessor reset key (2) Red LED – Urgent Alarm (Major) RS232 (3) Yellow LED – Not Urgent alarm (Minor) not used in current release

(7)

(4) Microprocessor bicolor LED (5) LED indicating the Ethernet port status (factory use only) (6) Ethernet debugger port (factory use only) (7) RS232 port (factory use only)

1AA 00014 0004 (9007) A4 – ALICE 04.10

(8)

Bicolor LED: Red led – Local unit alarm Green led – in service unit

(8)

Figure 46. ISA ES–16 front view

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SLOTS

PREA4ETH

24 to 39

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ACRONYM

(1)

(2) (3)

(4)

EthPort63

(5)

EthPort62

(6)

EthPort61

(7)

EthPort60

RJ45 connectors LEGENDA (1) Factory use only (2) Microprocessor restart Key (3) Not used (4) to (7) Ethernet cahnnels

(8)

(8) Bicolor LED

1AA 00014 0004 (9007) A4 – ALICE 04.10

Red led – Local unit alarm Green led – in service unit

Figure 47. ISA– PRE_EA Matrix 4x Ethernet

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ACRONYM

SLOTS

PREA1GBE

24 to 39

(1)

(2) (3)

(4) LEGENDA

(1) Factoy use only (2) Microprocessor restart Key (3) Not used (5)

(4) The slot can be equipped with a SFP Gigabit Ethernet optical module, see Figure 72. on page 161

1AA 00014 0004 (9007) A4 – ALICE 04.10

(5) Bicolor LED Red led – Local unit alarm Green led – in service unit

Figure 48. ISA– PRE_EA Matrix 1 x GB–ETH

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SLOTS

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ACRONYM

OUTPUT

ISA–PR

25 to 38 INPUT

LEGENDA

(1)

(1) to (4) SFP optical connections for STM4 SDH ring interface. From top to bottom W1, W2 for West ring interface, E1, E2 for East ring interface. Note: the cavities must be equipped with STM4 optical modules (refer to Figure 72. on page 161) In the figure the four modules are included

(2)

(3)

(5) OK led Red led – Major / critical alarm (Major alarm on ISA–PR or slot alarms in access card or Major transmis– sion alarms on access card. Access card slot alarms stand for: Card Mismatch, Card unassigned, Card Failure on POST _ Power On Self Test) Red led blinking 50/50 – during POST failure (Power On Self Test) Red led blinking 20/80 – Card Mismatch

(4)

Yellow led – Minor alarm Yellow led blinking 50/50 – Maintenance in progress (loopbacks..)

(5)

Green led – OK status (no alarms) Green led blinking 50/50 – ISA–PR is in initialization process (following power–on or reset)

(6)

Led OFF – card not powered (7) (6) ETH– Ethernet management interface RJ45 connector For local Craft Terminal or Network Management System connections (8)

(7) RS 232 – RJ45 connector For internal factory use (8) Microprocessor restart key

(9)

1AA 00014 0004 (9007) A4 – ALICE 04.10

(9) Active led Led OFF – card not powered Green led – card is powered

Figure 49. ISA– PR Matrix 4x4STM4 PLUG–IN

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ACRONYM

SLOTS

COWLA2

24 to 39

(1)

1st Channel

(2)

(3)

2nd Channel

(4) LEGENDA (1) Slot for ”Black & White or ”Colored” SFP module (2) Slot for ”Black & White” or ”Colored” SFP module (3) Slot for ”Black & White” or ”Colored” SFP module (4) Slot for ”Black & White” or ”Colored” SFP module Note: the cavities must be equipped with SFP modules (refer toFigure 72. on page 161) (5)

1AA 00014 0004 (9007) A4 – ALICE 04.10

(5) Active led Red led – Local unit alarm Green led – in service unit

Figure 50. COWLA2 front view

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SLOTS

4XANYC

25+26 28+29 34+35 37+38 32+33

(3)

(1)

LEGENDA: (1) Channel #1 (Low speed 4XANY acronym modules: OL–IN, OL–MM)

(4)

(2) Channel #2 (Low speed 4XANY acronym modules: OL–IN, OL–MM) (3) Channel #3 (Low speed 4XANY acronym modules: OL–IN, OL–MM OR High speed 4XANY acronym modules: OH–I, OH–MM)

(2)

(4) Channel #4 (Low speed 4XANY acronym modules: OL–IN, OL–MM OR High speed 4XANY acronym modules: OH–I, OH–MM) (5)

(5) Bicolor LED: Red led – local unit alarm Green led – in service unit

1AA 00014 0004 (9007) A4 – ALICE 04.10

Note: The allowed mixed configuration are reported on paragraph 3.10 on page 282

Figure 51. 4xANY Host C

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ACRONYM

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ACRONYM

SLOTS

MATRIXN

23,40

(1)

(2)

LEGENDA (1) Reset command key for factory use only xxxxxx

(3) Multicolor LED:

1AA 00014 0004 (9007) A4 – ALICE 04.10

Red led – Local unit alarm Green led – in service unit Orange led – unit in Stand–by (EPS schema)

3AL XXXXX AA

(2) RJ45

(3)

Figure 52. Matrix card

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EQUICO

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ACRONYM

SLOTS 22

(1)

(2)

LEGENDA (3) Reset command key Personal Computer Connector (F interface) RJ45 for factory use only Red LED – Urgent Alarm (Critical or Major) Red LED – Not Urgent ( Minor) Yellow LED – Alarm storing (Attended)

(7) (8) (9) (10) (11)

Yellow LED – Abnormal condition Yellow LED – Indicative Alarm (Warning) Lamp test push–button Alarm storing push–botton (Attended) Green LED – When on it means active unit

(4) (5) (6) (7) (8)

(9) (10)

1AA 00014 0004 (9007) A4 – ALICE 04.10

xxxxxx

(12) Bicolor LED: Red led – Local unit alarm Green led – in service unit

3AL XXXXX AA

(1) (2) (3) (4) (5) (6)

(11) (12)

Figure 53. Equipment controller EQUICO

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ACRONYM

SLOTS

CONGI

10, 12

(1)

(2)

(3)

(4) LEGENDA (1) Power (2) Housekeeping and remote alarm (5)

(3) Rack lamps (not used on CONGI in slot 12) (4) QMD (Q2) (not used on CONGI in slot 12) (5) I/O BNC for Q3 10 base 2 (not used on CONGI in slot 12)

(6)

1AA 00014 0004 (9007) A4 – ALICE 04.10

xxxxxx

(7) Bicolor LED: Red led – local unit alarm Green led – in service unit

3AL XXXXX AA

(6) RJ45 for Q3 10 base T (not used on CONGI in slot 12)

(7)

Figure 54. Control and General interface

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SLOTS

SERVICE

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ACRONYM

11

(1)

J1

J5

J2

J6

J3

J7

J4

J8

LEGENDA (1) I/O auxiliary 2 Mbit/s Channels G.703 J1 – 2 Mbit/s Channel Output 1 J2 – 2 Mbit/s Channel Input 1 J5 – 2Mbit/s Channel Output 2 J6 – 2Mbit/s Channel Input 2 I/O 2 MHz Synchronous interfaces J3 – 2 MHz Output 1 (T4A) or 2 Mbit/s Output (T5A) J4 – 2 MHz Input 1 (T3A) or 2 Mbit/s Input (T6A) J7 – 2 MHz Output 2 (T4B) or 2 Mbit/s Output (T5B) J8 – 2 MHz Input 2 (T3B) or 2 Mbit/s Input (T6B) (2) Auxiliary channels: 4 channel RS–232 4 channel V.11 64 Kbit/s 4 channel G.703 64 Kbit/s

(2)

(3)

(4)

(3) Four wire telephone extension point (RJ45) Four wire telephone extension point (RJ11)

(5)

(5) Z1–Z8 EOW zone selection LEDs (N.B.1)

(6)

(4)

L1

L2

(6) L1–L2 LEDS status for selective call (N.B.2)

(7) (8)

(7) Telephone jack

(9)

(8) Line seizure Key (9) EOW zone selection (N.B.1) (10) Reset command Key

1AA 00014 0004 (9007) A4 – ALICE 04.10

xxxxxx

(11) Bicolor LED: Red led – local unit alarm Green led – in service unit

3AL XXXXX AA

(10) (11)

N.B.1 Only one Zone is operative. N.B.2 For details see Table 56. on page 547 and Table 57. on page 547 Figure 55. SERVICE interface

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2.4.2 Access cards front view

ACRONYM

SLOTS

A21E1

1 to 9,13 to21

(1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19)

LEGENDA

(20)

1AA 00014 0004 (9007) A4 – ALICE 04.10

INPUT

xxxxxx

(22) Bicolor LED: Red led – local unit alarm (INT) Green led – in service unit

(21) 3AL XXXXX AA

(1) – (21) 2 Mbit/s data signals

OUTPUT (22)

Figure 56. 21 x 2 Mbit/s 75 ohm access card 1.0/2.3 connectors

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A21E1

SLOTS

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ACRONYM

1 to 9,13 to21

(1)

(2)

LEGENDA

(3)

(1) Channels # 1 to 7 connector (2) Channels # 8 to 14 connector

1AA 00014 0004 (9007) A4 – ALICE 04.10

Red led – local unit alarm (INT) Green led – in service unit

xxxxxx

(4) Bicolor LED:

3AL XXXXX AA

(3) Channels #15 to 21 connector (4)

Figure 57. 21 X 2 Mbit/s 120 Ohm access card

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ACRONYM

SLOTS

A3E3

2 to 9, 13 to 20

INPUT

(1)

OUTPUT

INPUT

(2)

OUTPUT

INPUT

(3)

OUTPUT

LEGENDA (1) Channel #1 (2) Channel #2

xxxxxx

(4) Bicolor LED:

1AA 00014 0004 (9007) A4 – ALICE 04.10

Red led – local unit alarm (INT) Green led – in service unit

3AL XXXXX AA

(3) Channel #3 (4)

Figure 58. 3 X 34 Mbit/s 75 ohm access card

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SLOTS

A3T3

2 to 9, 13 to 20

INPUT

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

ACRONYM

(1)

OUTPUT

INPUT

(2)

OUTPUT

INPUT

(3)

OUTPUT

LEGENDA (1) Channel #1 (2) Channel #2

(4) Bicolor LED:

1AA 00014 0004 (9007) A4 – ALICE 04.10

xxxxxx

Red led – local unit alarm (INT) Green led – in service unit

3AL XXXXX AA

(3) Channel #3

(4)

Figure 59. 3 X 45 Mbit/s 75 ohm access card

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ACRONYM A4ES1

SLOTS 2 to 9, 13 to20

INPUT

(1)

OUTPUT

INPUT

(2)

OUTPUT

INPUT

(3)

OUTPUT

LEGENDA

INPUT (1) Channel #1

(4)

OUTPUT

(2) Channel #2

xxxxxx

(4) Channel #4 (5) Bicolor LED:

1AA 00014 0004 (9007) A4 – ALICE 04.10

Red led – local unit alarm (INT) Green led – in service unit

3AL XXXXX AA

(3) Channel #3 (5)

Figure 60. 4 X STM–1 access card

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1AA 00014 0004 (9007) A4 – ALICE 04.10

ED 2 to 9, 13 to20

(1) All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

HPROT

Red led – local unit alarm Green led – in service unit

xxxxxx

SLOTS

Bicolor LED:

3AL 91668 AA AA

636

3AL XXXXX AA

ACRONYM

LEGENDA

(1)

Figure 61. High Speed protection – front view

02

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ACRONYM

SLOTS

A2S1

2 to 9, 13 to20

(1)

(2)

LEGENDA

(3) Bicolor LED:

1AA 00014 0004 (9007) A4 – ALICE 04.10

Red led – local unit alarm (INT) Green led – in service unit

xxxxxx

(2) Channel #4 (N.B.)

3AL XXXXX AA

(1) Channel #3 (N.B.)

(3)

N.B.– The unit can be equipped with electrical or optical modules (see Figure 70. and Figure 71. ) Figure 62. 2 x 140/STM–1 O/E adapter (access card)– front view

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SLOTS

ETH–ATX

2 to 9, 13 to20

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ACRONYM

(1) (2) (3) (4)

(5) (6) (7) (8)

(9) (10) (11) (12)

(13) (14) LEGENDA (15)

(1) to (14) Ethernet channels

1AA 00014 0004 (9007) A4 – ALICE 04.10

(15) Bicolor LED Red led – Local unit alarm Green led – in service unit

Figure 63. ISA – Ethernet access front view

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ACRONYM

SLOTS

GETH–AG 2 to 9, 13 to20

OUTPUT

INPUT

(1)

(2)

(3)

(4)

LEGENDA (1) to (4) are Gigabit Ethernet channels Note: the cavities must be equipped with Ethernet Optical Modules (refer to Figure 72. on page 161) Only the two upper cavities can be equipped when the GHETH–AG is used in cojunction with ETH–MB

(5)

1AA 00014 0004 (9007) A4 – ALICE 04.10

(5) Bicolor LED Red led – Local unit alarm Green led – in service unit

Figure 64. ISA – Gigabit Ethernet access card front view

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SLOTS

2GBA–PR

2 to 8 13 to 20

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ACRONYM

OUTPUT

INPUT

LEGENDA (1) and (2) are Gigabit ethernet channels Note: the cavities must be equipped with Ethernet Optical Modules (refer toFigure 72. on page 161) In the figure the two modules are included (3) and (4) Link led, one for each ethernet channel Red led – any port related alarm Green led – link up

(1)

(5) OK led Red led – Major / critical alarm Red led blinking 50/50 – during POST (Power On Self Test) failure Red led blinking 20/80 – Card Mismatch

(2)

Yellow led – Minor alarm Yellow led blinking 50/50 – maintenance Green led – OK status (no alarms) Green led blinking 50/50 – during init Green led blinking 20/80 – Card is Unassigned (i.e.not yet approved by NMS)

(3) (4) (5)

Led OFF – card not powered (6) (6) Active led

1AA 00014 0004 (9007) A4 – ALICE 04.10

Led OFF – card not powered Green led – card is powered

Figure 65. ISA PR 2XGBE 1000 access card front view

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(2)

ACRONYM

SLOTS

16FEA–PR

2 to 8 13 to 20

(3)

LEGENDA (1) 16 x 10/100 fast ethernet channels (2) Link led, one for each channel Green led – link up Led off – link down (3) Activity led, one for each ethernet channel Yellow led – Rx/Tx in progress Led off – link silent

(1)

(4) OK led Red led – Major / critical alarm Red led blinking 50/50 – during POST (Power On Self Test) failure Red led blinking 20/80 – Card Mismatch Yellow led – Minor alarm Yellow led blinking 50/50 – maintenance Green led – OK status (no alarms) Green led blinking 50/50 – during init Green led blinking 20/80 – Card is Unassigned (i.e.not yet approved by NMS) Led OFF – card not powered

1AA 00014 0004 (9007) A4 – ALICE 04.10

(5) Active led Led OFF – card not powered Green led – card is powered

(4) (5)

Figure 66. ISA PR16XETH 10/100 access card front view

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SLOTS

COADM1

1 to 8 13 to 20

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ACRONYM

(1)

(2)

LEGENDA (3) (1) Line Side Fiber Connectors (2) Add/Drop Channel Fiber Connectors (4) (3) Pass–through Fiber Connectors

1AA 00014 0004 (9007) A4 – ALICE 04.10

(4) Bicolor LED Red led – Local unit alarm Green led – in service unit

Figure 67. COADM1 front view

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ACRONYM

SLOTS

COADM2

1 to 8 13 to 20

(1)

(3)

(2)

LEGENDA

(4)

(1) Line Side Fiber Connectors (2) Add/Drop Channel #1 Fiber Connectors (3) Add/Drop Channel #2 Fiber Connectors (5)

(4) Pass–through Fiber Connectors

1AA 00014 0004 (9007) A4 – ALICE 04.10

(5) Bicolor LED Red led – Local unit alarm Green led – in service unit

Figure 68. COADM2 front view

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SLOTS

COMDX8

1 to 8 13 to 20

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ACRONYM

(1)

LEGENDA

(2)

(3)

(4)

(5)

(6)

(7)

(8)

(9)

(1) Line Side Fiber Connectors (2) Channel 1470 nm Fiber Connectors (3) Channel 1490 nm Fiber Connectors (4) Channel 1510 nm Fiber Connectors (5) Channel 1530 nm Fiber Connectors (6) Channel 1550 nm Fiber Connectors (7) Channel 1570 nm Fiber Connectors (10)

(8) Channel 1590 nm Fiber Connectors (9) Channel 1610 nm Fiber Connectors

1AA 00014 0004 (9007) A4 – ALICE 04.10

(10) Bicolor LED Red led – Local unit alarm Green led – in service unit

Figure 69. COMDX8 front view

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STM–1 module EQUIPPED acronym on CARDS SC/PC

IS–1.1 IL–1.1 IL–1.2

P4S1N P4E4N ATM4X4 A2S1 P4OC3

INPUT OUTPUT

MM1 STM–4 module EQUIPPED acronym on CARDS

IS–4.1 IL–4.1

P4S4N Laser restart key

IL–4.2

STM–1 module EQUIPPED on CARDS acronym

IS–1.1 IL–1.1 IL–1.2

FC/PC

P4OC3 P4S1N P4E4N ATM4X4 A2S1

INPUT OUTPUT

STM–4 module EQUIPPED on CARDS acronym

IS–4.1 IL–4.1

P4S4N Laser restart key

1AA 00014 0004 (9007) A4 – ALICE 04.10

IL–4.2

Figure 70. STM–1/STM–4 optical module front view

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1AA 00014 0004 (9007) A4 – ALICE 04.10

ACRONYM

ICMI

ED P4OC3 P4S1N P4E4N ATM4X4 A2S1

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EQUIPPED ON PORTS

INPUT

OUTPUT

Figure 71. STM–1 or 140 Mbit/s electrical module front view

02

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SFP MODULE ACRONYM

EQUIPPED ON PORT/ACCESS

1000B

GETH–MB GETH–AG ES4–8FE 2GBA–PR PREA1GBE

100B

ES1–8FX

SS–161 SL–161 SL–162

CO–16 COWLA2

SS–162C SL–162C SS–41

ISA–PR SFP Module

OUTPUT

INPUT

1AA 00014 0004 (9007) A4 – ALICE 04.10

Optical cables

Figure 72. Relationship between SFP modules and housing boards

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1AA 00014 0004 (9007) A4 – ALICE 04.10

OH–I

OL–IN 4XANYC

OH–MM

OL–MM

ED All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

4XANY modules EQUIPPED acronym on CARDS

OUTPUT

INPUT

Figure 73. 4XANY plug–in module

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ACRONYM

SLOTS

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SC/PC

BST10

2 to 8 13 to 19

BST15

2 to 8 13 to 19

BST17

2 to 8 13 to 19

FC/PC INPUT OUTPUT

(2)

(2)

INPUT OUTPUT

(1)

(1)

LEGENDA: (1) Cover remove (2) IN / OUT Main Signal (3) Yellow LED: active Shut Down (4) Bicolor LED:

1AA 00014 0004 (9007) A4 – ALICE 04.10

Red led – Local unit alarm Green led – in service unit

(3)

(3)

(4)

(4)

Figure 74. Optical Booster card front view

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ACRONYM

SLOTS FC/PC All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

SC/PC

2 to 8 13 to 19

PR16

INPUT OUTPUT

INPUT OUTPUT

(1)

(1)

(2) (2)

LEGENDA: (1) Cover remove (2) IN / OUT Main Signal (3) Yellow LED: active Shut Down (4) Bicolor LED:

1AA 00014 0004 (9007) A4 – ALICE 04.10

Red led – Local unit alarm Green led – in service unit

Not used

Not used

(3)

(3)

(4)

(4)

Figure 75. PREAMPLIFIER 2.5 GB/S front view

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2.4.3 FAN subrack cover front view

(1)

(2)

(4)

(5) (6)

(3)

LEGENDA (1)

MULTICOLOR LED:

1AA 00014 0004 (9007) A4 – ALICE 04.10

Red led – local unit alarm Orange led – temperature major than 55 C Green led – in service unit (2)

Battery A connector

(3)

Battery B connector

(4)

Not used

(5)

Alarms connector for 1660SM

(6)

Not used

Figure 76. 19” Fans subrack cover front view

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1AA 00014 0004 (9007) A4 – ALICE 04.10

ED

02

3AL 91668 AA AA

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3 FUNCTIONAL DESCRIPTION 3.1 General description From Figure 80. on page 178 to Figure 88. on page 186 illustrates, in block diagram form, the units employed in the 1660SM and the general operating functions: •

EQUICO unit The unit provides the following functionality:

•

–

Equipment Controller (EC) function

–

F interface for Local Craft Terminal

–

Communication with the Operation System (O.S) through different interface (DCC, QB3 etc.)

MATRIX unit The unit provides the following functionality:

•

–

Matrix that performs HPC, LPC and protection functions

–

Synchronization functions

–

Shelf Controller (SC) function

2 or 34/45 Mbit/s PDH Electrical unit Different PDH Electrical unit are available: –

”2 Mbit/s PDH Electrical unit” provides the interface for the asynchronous mapping G.703 2 Mbit/s signals into SDH VC12s. Each unit supports 63 interface. The unit is the same for 75 Ω and 120 Ω. applications; impedance match is performed at the “access card” level.

–

”34 Mbit/s / 45 Mbit/s unit” provides the interface for the asynchronous mapping of G.703 34 Mbit/s or 45 Mbit/s signals into SDH VC–3s. Each unit supports 3 interface . The selection of the working mode (3 x 34 Mb/s or 3 x 45 Mb/s) is controlled via software. Two different access module are used for the 34 Mb/s and 45 Mb/s applications.

For both units the Lower Order Interface (LOI) block includes PPI (physically on the Access Card), LPA, LPT functionality (see Figure 77. on page 167 and Figure 80. on page 178)

LOI

1AA 00014 0004 (9007) A4 – ALICE 04.10

PPI

LPA

LPT

Figure 77. LOI block diagram

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•

The unit provide four 140 PDH electrical or 155 Mbit/s STM–1 Electrical/Optical interfaces. The selection of the working mode (per port) is controlled via software: – When the 140 Mbit/s mode is selected, the port provides an interface for the asynchronous mapping of G.703 140 Mbit/s signals into SDH VC–4. The functions performed in the High Order Interface (HOI) block are: PPI (Physically on the Access Card), LPA, HPT(see Figure 78. on page 168 and Figure 80. on page 178. Two of the four PPI blocks are present on the board, the other two are on the Access Card. HOI PPI

LPA

HPT

Figure 78. HOI block diagram –

When the 155 Mbit/s STM–1 mode is selected, the VC–4 can either be unstructured or structured into lower order VCs. The functions performed are TTF and HOA (see Figure 79. on page 168). Two of the four SPI blocks are present on the board, the other two are on the Access Card. TTF SPI

RST

MST

MSP

MSA

HOA HPT

HPA

Figure 79. TTF and HOA block diagram •

4 x155 Mbit/s Electrical/Optical unit The unit provides four bidirectional STM–1 electrical or optical interfaces. For each STM–1, the VC–4 can either be unstructured or structured into lower order VCs. The function performed are TTF and HOA ( see Figure 79. on page 168 and Figure 80. on page 178.). Two of the four SPI blocks are present on the board, the other two are on the Access Card. Any combination of electrical or optical (short or long haul) is possible on the same unit.

•

4 x155 Mbit/s Electrical unit

1AA 00014 0004 (9007) A4 – ALICE 04.10

The unit provides four bidirectional STM–1 electrical interfaces. The four SPI blocks are available on Access Card. For each STM–1, the VC–4 can either be unstructured or structured into lower order VCs. The function performed are TTF and HOA ( see Figure 79. on page 168 and Figure 80. on page 178.).

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4 x 140 Electrical or 155 Mbit/s E/O unit

•

1 X STM–4 Optical unit

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The 1 x STM–4 optical unit provide one STM–4 optical interface; the function performed are TTF and HOA. Several short and long haul types are available. •

1 X STM–16 optical unit The 1 x STM–16 optical unit provide one STM–16 optical interface (on front panel); the function performed are TTF and HOA. Several short and long haul types and connectors are available. “Colored” versions are available for direct interworking with WDM equipment without intermediate wavelength adapters.

•

4 X OC3 AU3/TU3 Conversion unit This board can manage up to 4 x OC–3 (SONET) streams. The board hosts up to 2 interfaces into the front panel. The other two interfaces can be hosted in the Access area using the relevant access card that must be equipped in the slot associated to the corresponding traffic unit slot (refer to Table 22. on page 113). Each combination of interfaces (electrical, S.1.1,L.1.1,..) can be equipped in the same board. On OC–3 interface the Sonet mapping is mange so the RS and MS sections are terminated, the 3 AU3 are processed to extract or insert the 3 VC3. This unit performs the AU3/TU3 conversion , which allows the transport in SDH network of Sonet VC3 traffic. The conversion is performed on OC–3 interface: the 3 VC3 are extracted then re–mapped in SDH VC4 container and this container is passed to the matrix where it is managed as a structured VC4. The OH byte of RS and MS section are managed according SDH ITU standard.

•

ISA – ATM4X4, ATM4X4V2, ATM4X4D3 Three boards types are available: –

ATM4X4 with a max. number of 16 TPs configurable among SDH VC4, SDH VC3, SDH VC12, PDH 2M and PDH 34M.

–

ATM4X4V2 with a max number. of 252 TPs configurable among SDH VC4, SDH VC3, SDH VC12, PDH 2M, PDH 34M and PDH 45M.

–

ATM4X4D3 with a max number. of 16 TPs configurable among SDH VC4, SDH VC3, SDH VC12, PDH 2M, PDH 34M and PDH 45M.

They are a one slot wide boards that integrate an ATM switch functionality. Only the ATM4X4 BOARD also includes a STM–1 local access port on the front panel. For both throughput capacity towards backpanel is 622 Mbit/s. ATM traffic control functions, such as “Shaping” and “Policing” (which are needed to avoid network congestion) are supported.

1AA 00014 0004 (9007) A4 – ALICE 04.10

•

ISA – ATM MATRIX 8X8 It is a two slot wide board that integrate an ATM switch functionality. 16+16 TPs are configurable among SDH VC4,SDH VC4–C, SDH VC3, SDH VC12, PDH 2M and PDH 34M. The throughput capacity is 1.2 Gbit/s. ATM traffic control functions, such as “Shaping” and “Policing” (which are needed to avoid network congestion) are supported.

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•

1660SM can host two types of PR_EA matrix (generically ISA PR_EA board): – in the first version, it hosts a 4 x 10/100 BaseT Fast Ethernet module and the total traffic throughput is 1 Gb/s, in which 622Mb/s are contributed by the SDH matrix, and 400 Mb/s contributed by the 4 Fast Ethernet local ports. – in the second version, it hosts a 1 x 1Gigabit Ethernet module and the total traffic throughput is 1.8 Gb/s, in which 622Mb/s are contributed by the SDH matrix, and 1.25 Gb/s contributed by the Gb Ethernet local port. The following table summarizes the interfaces that can accede to the MPLS functions: TYPE OF INTERFACE

CONTAINER

NOTES

SDH

VC–12, VC–3, VC–4

PDH

E1, E3, T3

not available in current rel.

Ethernet (E, FE, GE)

MAC 802.3

also “802.1p/q Tagged”

Table 29. Interfaces acceding to the MPLS functions •

ISA – PR MATRIX 1660SM can host PR matrix (generically ISA–PR board) and relevant access cards: It provides a shared carrier–class Ethernet Packet Ring embedded, in a flexible manner over SDH VCs (with VC–4–nv framing), either physically or logically into the SDH infrastructure. The ISA–PR is a Layer 2 MPLS–based statistical packet switch with Ethernet and GBE interfaces operating a Resilient Packet Ring transported over multiple STM–4 standard interfaces. The ISA–PR port card is a RPR switch with four STM–4 interfaces providing 6.5 Gbps packet throughput with a provisionable trunk capacity of 1.2 Gbps both in East and West directions. On its front plate a RJ45 connector provides the connection toward the Local Craft Terminal or the Operation System. The following table summarizes the interfaces that can accede to the PR functions: TYPE OF INTERFACE SDH Ethernet (E, FE, GE)

CONTAINER

NOTES

VC–4 MAC 802.3

also “802.1p/q Tagged”

Two access card types are availale (also in mixed configuration):

1AA 00014 0004 (9007) A4 – ALICE 04.10

–

16 FEA–PR – Fast ETHERNET access card 10/100 Ethernet Access card supporting sixteen (16) 10/100 Fast Ethernet interfaces. Up to four 16FEA–PR access cards can be equipped.

–

2 GBA–PR – GigaBit Ethernet access card GigaBit Ethernet Access card supporting two (2) GigaBit Ethernet interfaces.

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ISA – PR_EA MATRIX

•

ISA – Fast ETHERNET unit

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The unit is able to provide 25 x 10/100 Mb/s Ethernet interfaces to allow LAN–to–LAN connections. In the main port are provided 11 connectors on the front panel of the unit. The main port can be used in conjunction with the relevant access module (ETH–ATX) which is able to provide 14 additional 10/100 Mb/s Ethernet interfaces. Ethernet frames are mapped over an SDH VC (VC–12, VC–3, VC–4) with a max. throughput of 622 Mbt/s toward the backplane. Each physical interface can independently be mapped into the relevant VC according to the required bit rate. N.B.

•

The Fast Ethernet unit 10/100 Mb/s can be also used in conjunction with the Gigabit Ethernet Access card (GETH–AG); in this configuration the Fast Ethernet unit can handle the following interfaces: –

two Gbit Ethernet interfaces (on the access card GETH–AG); Ethernet frames are mapped over a single SDH VC–4.

–

11 Interfaces 10/100 Mb/s Ethernet interfaces (on the Main board)

ISA – Gigabit ETHERNET unit The unit is able to manage 4 Gigabit Ethernet interfaces on the main board.

•

ISA ES1–8FE, ISA ES1–8FX and ISA ES4–8FE The boards mainly work as a LAN switching, and in particular they provide the service of connecting two LANs as point to point connection between two routers or switches through a SDH network. ISA ES1–8FE and ISA ES4–8FE units have eight 10/100 Mbit/s Ethernet interfaces on the front panel; the Ethernet traffic, opportunely mapped in the SDH transport structures, is then sent toward the SDH matrix via the back plane with a STM–1 equivalent throughput . ES1–8FX board has eight Small Form factor Pluggeable module supporting optical Fast Ethernet Interfaces on the front panel. ES4–8FE board has also one Small Form factor Pluggeable module supporting a Gigabit Ethernet Interface on the front panel. ISA–ES1 and ISA ES4 series module can classify ETH traffic according to a wide set of standard specified criteria in order to provide a feature reach set of capability. Each classified traffic is referred as a classified flow. Classification criteria are the following: – – – –

Port (Physical ETH or ETH over SDH) IEEE 802.1Q (VLAN tagging) IEEE 802.1p (ETH frame priority) IEEE 802.3 Source/Destination MAC address (also according to IEEE 802.1ad)

1AA 00014 0004 (9007) A4 – ALICE 04.10

Hereafter are reported the available trunking capacity: – –

ED

ISA–ES1 ISA–ES4

has 1 VC–4 of bandwidth available has 4 VC–4 of bandwidth available

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•

As for ISA ES1 and ISA ES4 the boards ISA ES16 mainly work as a LAN switching, and in particular they provide the service of connecting two LANs as point to point connection between two routers or switches through a SDH network. ISA–ES16 is a port less card that can use specific access modules: –

14 x FE access module: 14 x Fast Ethernet ports (10/100 Base T)

–

4 x GE access module:

4 x GB Ethernet ports with SFP plugs

ISA ES16 Classification criteria are the following: – – – – – –

Port (Physical ETH or ETH over SDH) IEEE 802.1Q (VLAN tagging) IEEE 802.1p (ETH frame priority) IEEE 802.3 Source/Destination MAC address (also according to IEEE 802.1ad) MPLS label (according to IETF Martini draft ETH over MPLS) IP–TOS/DSCP fields

Hereafter are reported the available trunking capacity: –

•

ISA–ES16 has up to 16 VC–4 of bandwidth available (depending on the subrack slot capacity of the 1660SM equipment)

4 x ANY HOST C unit The 4xANY board is a Time Division Multiplexer concentrator that performs a bidirectional interface between up to 4 clients data and the MATRIX board (via backpanel) through up to 16 VC–4. A mixing of SDH and Data Services is possible. Multiplexing scheme delivers a fully compliant SDH frame. The board is two slot wide and can be plugged in the enhanced slot( 25&26, 28&29, 34&35, 37&38) and not enhanced slot (30&31, 32&33), so the throughput toward MATRIX unit can be from 1.2 Gbit/s to 622 Mbit/s. Up to 4 client signals can be independently handled among the following types (for details and restriction refer to paragraph 3.10 on page 282) :

1AA 00014 0004 (9007) A4 – ALICE 04.10

• • • • • • •

ED

Fast Ethernet FDDI (125Mbps) ESCON (200Mbps) Digital Video (270Mbps) Fiber Channel (1.0625Gbps) FICON (1.0625Gbps) Gigabit Ethernet (1.25Gbps)

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ISA ES16

•

Double channel multirate transponder (COWLA2) unit

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This unit realizes both the ’wavelength assignment’ and the ’wavelength regeneration’ on the 2 separate channels supported, according to the type of optical interface (’colored’ CWDM or B&W) equipped. Pluggable CoarseWDM/B&W SFP optical modules are equipped in order to allow maximum flexibility in channel configuration. 8 possible Coarse WDM modules with SFP transceiver are available with a throughput up to 2.5Gb/s. CWDM transceiver are ITU–T grid compliant (1470–1490–1510– 1530–1550–1570–1590–1610 nm). The configuration of COWLA2 requires the operator to specify for each module the transported client signal and if the module is colored or B&W. The transponder unit supports the ’3R’ functionality for the following signal types: – – – – – – – – – – – – – •

FDDI (125 Mb/s); Fast Ethernet (125 Mb/s); STM1/OC3; Escon (200 Mb/s); Digital Video (270 Mb/s); STM4/OC12; Fiber Channel (1.0625 Gb/s); FICON (1.0625 Gb/s); Gb Ethernet (1.25 Gb/s); 2 Fiber Channel (2.125 Gb/s); STM16/OC48; 2 Gb Ethernet (2.5 Gb/s); STM16 w/ FEC (2.667 Gb/s)

not operative in current release not operative in current release not operative in current release not operative in current release not operative in current release not operative in current release not operative in current release not operative in current release not operative in current release not operative in current release not operative in current release not operative in current release

OADM1 (COADM1) unit COADM1 unit realizes wavelengths multi–demultiplexing allowing to add/drop 1 channel out of the 8 supported according to CWDM grid and the pass–through of remaining WDM channels not terminated. One specific item per ITU–T channel is foreseen: 1470 – 1490 – 1510 – 1530 – 1550 – 1570 – 1590 – 1610 nm. The functionality of the board has to be considered for ring application, and performing ’one side’ channel termination: thus, two separate boards are required at a node of the ring in order to achieve the complete OADM functionality. ’Loss of Signal’ detection on CWDM optical signal received is provided in order to support the standard management of OMSN’s. The CWDM LOS detection allows the operator to realize an efficient and specific maintenance of the network in case of break of ring/linear cables carrying multiplexed signals.

•

OADM2 (COADM2) unit COADM2 board realizes wavelengths multi–demultiplexing allowing to add/drop 2 channels out of the 8 supported according to CWDM grid and the pass–through of remaining WDM channels not terminated.

1AA 00014 0004 (9007) A4 – ALICE 04.10

Four specific items are foreseen, considering to support the termination of two adjacent wavelengths per item: – – – –

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1470 – 1490 nm; 1510 – 1530 nm; 1550 – 1570 nm; 1590 – 1610 nm.

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•

Mux/Demux 8 ch (COMDX8) unit MUX/DEMUX board realizes wavelengths multi–demultiplexing on the whole group of 8 CWDM channels supported. 8 CWDM ITU–T grid compliant filters are equipped on the MUX/DEMUX module: 1470, 1490, 1510, 1530, 1550, 1570, 1590, 1610 nm. The functionality of the board can be considered both for linear and ring application; contrary to COADMn boards, no ’pass–through’ link is provided, then pass–through of wavelengths not terminated must be realized on each single wavelength. In ’ring’ application, the board performs ’one side’ channels termination: thus, two separate boards are required at a node of the ring in order to achieve the complete functionality. ’Loss of Signal’ detection on CWDM optical signal received is provided in order to support the standard management of OMSN’s. The CWDM LOS detection allows the operator to realize an efficient and specific maintenance of the network in case of break of ring/linear cables carrying multiplexed signals.

•

SERVICE unit The unit provides the following functionality:

•

–

Auxiliary channels

–

Engineering Order Wire (EOW)

–

2 MHz Input/Output

CONGI unit The unit provides the following functionality:

•

–

Power Supply

–

QB3 Interface

–

Housekeeping and remote alarm

–

Q2/RQ2 interface

Access Cards They provides the physical interface for the different types of signals

•

Protection Card The unit allows the EPS protection for 34/45Mbit/s and 155 Mbit/s electrical unit.

1AA 00014 0004 (9007) A4 – ALICE 04.10

•

BOOSTER To improve the span length of STM–N interfaces for single channel application, the Optical booster unit can be used. This unit can be plug–in in the access area. Three integrated boosters are available, according to the relevant gain values: 10dbm, 15dBm and 17dBm.

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The functionality of the board has to be considered for ring application, and performing ’one side’ channel termination: thus, two separate boards are required at a node of the ring in order to achieve the complete OADM functionality. ’Loss of Signal’ detection on CWDM optical signal received is provided in order to support the standard management of OMSN’s. The CWDM LOS detection allows the operator to realize an efficient and specific maintenance of the network in case of break of ring/linear cables carrying multiplexed signals.

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

•

OPTICAL PREAMPLIFIER This unit can be plug–in in the access area. It is used in conjunction with the optical booster to improve the span length of STM–16 interfaces for single channel application.

The functions carried out by the unit can be splitted into the following sub–systems: [1]

Connections sub–system (refer to paragraph 3.2 on page 188)

[2]

Signal management sub–system (refer to paragraph 3.3 on page 190)

[3]

ISA (Integrated Service Adapter) sub–system ( refer to paragraph 3.4 on page 213)

[4]

4xANY HOST C subs–system (refer to paragraph 3.10 on page 282)

[5]

Coarse WDM sub–system (refer to paragraph 3.11 on page 289)

[6]

Controller sub–system (refer to paragraph 3.12 on page 304)

[7]

Protection sub–system (refer to paragraph 3.13 on page 310)

[8]

Synchronization sub–system (refer to paragraph 3.14 on page 351)

[9]

Auxiliary sub–system (refer to paragraph 3.15 on page 353)

[10] Power supply sub–system (refer to paragraph 3.16 on page 355) [11] Remote inventory sub–system (refer to paragraph 3.17 on page 358) On the following paragraphs a detailed description of each sub–system is given. Each logical function does not correspond necessarily to a physical card but can be distributed over more than one card. On the other side, one card can house more than one function. For each sub–system the list of the involved cards and a brief abstract of the function detailed on the following paragraphs is reported in Table 30. on page 176.

1AA 00014 0004 (9007) A4 – ALICE 04.10

Notice that the On Board Power Supply (DC/DC converter in Figure 80. on page 178) is present on each card and that the Controller function is centralized ( EC and SC).

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Table 30. Sub–systems & involved cards Card involved

Connections

MATRIX and ports

Short description On the para. is explained how the signal is managed between the port and the MATRIXE

Signal management

all the ports (LS and HS) Access Modules

On the para. it is explained how the PDH, SDH and SONET signals are elaborated on the ports. The description in compliancy with the G.783 ITU–T Rec.

ISA boards management

ISA boards, relevant access modules and SDH MATRIX

On the paragraph are explained the ATM, Ethernet/Fast Ethernet/Gigabit Ethernet, MPLS, PR, connections types supported by the system.

4xANY management

Coarse WDM

Controller

4xANY HOST C and SDH MATRIX

On the paragraph are explained the 4xANY HOST C connections types supported by the system.

COADM1, COADM2, COMDX8, COWLA2 and SFP modules

On the paragraph is explained the integration of WDM tecnology inside the 1660SM in order to enhance the network capacity.

EQUICO and MATRIX

The control system is centralized. The EQUICO performs the Equipment Controller (EC) function and the MATRIX perform the Shelf Controller (SC) function. The following network protection are explained:

Network protections

all the ports (LS and HS)

– – – – – –

linear MSP MS SPRING SNCP/I and SNCP/N (among VC–4 only) Drop & Continue + insertion SNCP Collapsed single–node ring interconnection Collapsed dual–node ring interconnection

The MATRIX card manages all the protections. 63x2 Mbit/s port (N+1) 3x34/45 Mbit/s port (N+1) Protection 155 Mbit/s electrical port (N+1) ISA–ATM MATRIX (1+1) Equipment ISA–PR_EA MATRIX (1+1) protections

The SC on the MATRIX card controls the EPS protections.

ISA–ES 16 (1+1)

1AA 00014 0004 (9007) A4 – ALICE 04.10

CONGI supply)

(only for the power

MATRIXN HPROT

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Sub–system

(Table continues)

1AA 00014 0004 (9007) A4 – ALICE 04.10

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

Sub–system

Short description The MATRIX performs the synchronization function therefore distributing the clock and synchronisms to all the equipment cards.

Synchronization

MATRIX

Auxiliary

HS ports, SERVICE, EQUICO

On the para. is explained how the OH bytes (DCC, EOW and AUX channels) are managed.

Power supply

all the cards, CONGI

The powering is distributed over the all equipment cards. The CONGI cards provides the 48 V and the service 3.3 V to power each card.

Remote Inventory

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Card involved

all the cards, access card and On the para is explained the Remote Inventory modules architecture

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Prot. Link

63 x 2 Mbit/s PDH Electrical unit MAIN T2

Access cards

line clock

T∅

LOI

–Batt/Gnd Control

DC/DC Converter

G.703

Sw

Data

Electrical Interfaces

Vcc W Prot. Vcc W Control

PROT. CARD

TO/FROM MATRIX See Figure 85.

3 x 34/45 Mbit/s PDH Electrical unit

Prot. Link

Prot. Link

OH

Access cards

Electrical Data

T∅ –Batt/Gnd Control

G.703

LOI DC/DC Converter

Interfaces

Vcc X

Vcc X Control

PROT. CARD

4 x 155 Mbit/s electrical unit

Access cards

Control HOA

Data T∅ T1 DCC OH

1AA 00014 0004 (9007) A4 – ALICE 04.10

–Batt/Gnd

SPI

TTF Prot. Link

DC/DC Converter

HOA

Prot. Link

Electrical Interfaces SPI

TTF

Vcc Y

Vcc Y Control

Figure 80. 1660SM Block diagram – (SDH and PDH boards)

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SPARE

–Batt/Gnd Control T∅ T1 DCC OH

DC/DC Converter

HOI

Vcc Z HOA HOA

Data

140 Mbit/s

PPI TTF

STM–1 SPI

TTF

SPI

TTF

SPI

HOA

STM–1

Optical/ Electrical Interfaces STM–1

Booster

Access card Vcc Z

Control

4 x 155 E/O Mbit/s unit TO/FROM MATRIX See Figure 85.

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

4 x 140 Mb/s el.–155 E/O Mbit/s unit

–Batt/Gnd Control T∅ T1 DCC OH

DC/DC Converter

TTF

Booster

SPI

STM–1

HOA Vcc Z HOA

TTF

Optical/ Electrical Interfaces

STM–1 SPI STM–1

HOA

TTF

SPI

HOA

TTF

SPI

STM–1

Data

Access card Vcc Z

Control

1 x STM–4 SDH unit –Batt/Gnd Control T∅ T1 DCC

DC/DC Converter TTF

Data

STM–4

SPI

HOA

OH

Optical Interfaces

Booster

1 x STM–16 SDH unit Control T∅ T1 DCC

Data

1AA 00014 0004 (9007) A4 – ALICE 04.10

OH

DC/DC Converter

Preamplifier TTF HOA

STM–16

SPI

(*)

Optical Interfaces

Booster

(*) – Removable SFP optical modules are available only on CO–16 port

Figure 81. 1660SM Block diagram – (SDH and PDH boards)

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Control T∅

DC/DC Converter Vcc Z

DCC OH

Data

AU3/TU3 conv.

SPI

AU3/TU3 conv.

SPI

OC3 OC3

AU3/TU3 conversion

SPI

AU3/TU3 conversion

SPI

OC3 Optical/ Electrical Interfaces OC3

Access card

TO/FROM MATRIX See Figure 85.

Vcc Z

Control

4 x ANY HOST C unit –Batt/Gnd

DC/DC Converter

Control

ÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ CDR

T∅

RX TX

Low speed signals: Fast Ethernet FDDI ESCON Digital Video FDDI

Opt. module #1

2xAny

CDR

Data

RX TX

Opt. module #2

STM–16 Mapper

CDR

Low speed signals: Fast Ethernet FDDI ESCON Digital Video FDDI

RX TX

Opt. module #3

2xAny

CDR

RX TX

High speed signals: Fiber Channel FICON Gigabit Ethernet

1AA 00014 0004 (9007) A4 – ALICE 04.10

Opt. module #4

Figure 82. 1660SM Block diagram – (SONET and 4xANY HOSTC boards)

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4 x OC3 AU3/TU3 CONV. unit –Batt/Gnd

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DOUBLE MULTIRATE TRANSPONDER unit Multirate CDR

SFP module

B&W TVC

CK Rx1 Data Rx1

Mx

SFP module

Data Recovery

Data Rx3

CWDM TVC

Data Rx2 Data Recovery

Data Rx4 CK Rx 1:4

B&W or CWDM SFP module

Multirate CDR

CWDM TVC

Data Rx 1:4

CK Multirate Rx3 CDR SFP module

Data Recovery

CK Rx2

Data Recovery

B&W or CWDM

CWDM TVC RS monitor #1

RS monitor

CK Rx4

Multirate CDR

#2

Alarm/Control Interface Remote Inventory EEPROM

RIBUS

ISPB bus

SPI bus

OUTPUT CHANNELS (from colored port or Transponder interface)

INPUT CHANNELS (to colored port or Transponder interface)

λ1 λ2 λ3 λ4 λ5 λ6 λ7 λ8 λ1 λ2 λ3 λ4 λ5 λ6 λ7 λ8

1470

output signal

1490

CWDM

1510 1530 1550

MUX

1570 1610 1590

1470 1490

LOS HANDLING

1510

1550

CWDM input signal

1530

DEMUX

1570 1610 1590

LOS DETECTION

MUX/DEMUX8 unit

Remote Inventory EEPROM

RIBUS

1AA 00014 0004 (9007) A4 – ALICE 04.10

SPI bus

Figure 83. 1660SM Block diagram – (CWDM boards)

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To/From colored port or transponder 1xx0

λx

1xx0

output signal

CWDM λgrid – λx OADM CWDM input signal

CWDM λgrid – λx LOS DETECTION LOS HANDLING To/From OADM opposite side Remote Inventory EEPROM

RIBUS

COADM1 unit SPI bus

To/From colored port or transponder

CWDM λgrid – λx–λy

CWDM

λx λy

1xx0

λx λy

1xx0

output signal

1xx0

OADM CWDM λgrid – λx–λy

CWDM input signal

1xx0

LOS DETECTION LOS HANDLING To/From OADM opposite side Remote Inventory EEPROM

RIBUS

COADM2 unit

1AA 00014 0004 (9007) A4 – ALICE 04.10

SPI bus

Figure 84. 1660SM Block diagram – (CWDM boards)

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CWDM

λx

See from Figure 86. on page 184 to Figure 88. on page 186 Data 2

See from Figure 80. to Figure 82.

1

TO/FROM PORT

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ISA boards

Data

Data

TO/FROM PORT See Figure 80. and Figure 81.

SDH matrix (HPC–LPC)

SERVICE unit

T∅ –Batt/Gnd

T1 T2

MATRIX Synchronization

T3/T6 a T3/T6 b

OH ports

T4/T5 a T4/T5 b

Control

OH add/drop

Control

Control

EQUICO

Shelf –Batt/Gnd

DC/DC Converter

DC/DC Converter

Controller

SC/EC Control

DCC add/drop

RS232

Aux RS232

G.703

Aux 2Mbit/s

G.703

Aux 64kbit/s

V.11

Aux 64kbit/s

Digital Party Line

Voice ext. Local phone Aux ext.

T3/T6 a T3/T6 b T4/T5 a T4/T5 b

G.703

T4a/T5a_ext. T4b/T5b_ext.

Control

CONGI unit

b

EQUICO –Batt/Gnd

Remote alarms & Housekeeping

DC/DC Converter

Equipment

F Interface

Controller

–Batt/Gnd Vcc Control

Filter & DC/DC

CONGI unit

Power B a

leds ports

1AA 00014 0004 (9007) A4 – ALICE 04.10

SERVICE

DCC add/drop

T3a/T6a_ext. T3b/T6b_ext.

–Batt/Gnd Vcc

Filter & DC/DC

QB3 Remote alarms & Housekeeping Rack lamps Q2 Power A

Figure 85. 1660SM Block diagram – ( Common units and ISA boards)

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ISA – ATM MATRIX Control

DC/DC Converter Traffic Policing and Shapimg

CELL SWITCHING

T∅

Data

SDH TERMINATION E/O MODULE

STM–1

ISA – PR_EA MATRIX 1GBPS 1 X GB ETHERNET –Batt/Gnd Control

Gigabit Ethernet Optical Interfaces 1000 BASE–SX / LX /ZX

TO/FROM MATRIX See Figure 85.

STM–1 LOCAL PORT (*)

DC/DC Converter

T∅

OPTICAL MODULE #1 Data

MPLS ENGINE

Optical/Electrical Interface

ATM ENGINE

1000 BASE–SX/LX/ZX

Control

DC/DC Converter

T∅

ETHERNET #1

1

ETHERNET #2 ETHERNET #3

Data

MPLS ENGINE

ETHERNET #4

4

Ethernet Interface 10/100 Mbit/s Base T

ISA – PR_EA MATRIX 4X ETHERNET –Batt/Gnd

1AA 00014 0004 (9007) A4 – ALICE 04.10

NOTE: (*) – Available only on ATM MATRIX 4X4

Figure 86. 1660SM Block diagram – (ISA boards)

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–Batt/Gnd

Gigabit Ethernet Optical Interfaces 1000 BASE–SX / LX /ZX

ISA – ES1 Control

GBit ETH.

ISA – ES4

(*)

T∅

Physical Interface

1

ETH. 1 Data

Ethernet frame

SDH

mapping into

framer

Ethernet switcher

SDH VC ETH. 8 –Batt/Gnd

8

Ethernet Interfaces 10/100 Mbit/s Base T or 100 Mbit/s Base FX

See Figure 85. TO/FROM MATRIX

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Physical Interface

DC/DC Converter

ETHERNET #1

1

ETHERNET #14

14

Control T∅

10/100 ETH Access card

Data

SDH framer

Ethernet frame mapping into SDH VC

Ethernet switcher

Gigabit Ethernet Access card OPTICAL MODULE #1

–Batt/Gnd

DC/DC Converter

1

1000 BASE–SX/LX/ZX

OPTICAL MODULE #2 1000 BASE–SX/LX/ZX 1AA 00014 0004 (9007) A4 – ALICE 04.10

Ethernet Interfaces 10/100 Mbit/s Base T

ISA – ES16

4

Gigabit Ethernet Optical Interfaces 1000 BASE–SX / LX / ZX

TO/FROM MATRIX

See Figure 85.

(*) GIGABIT ETHERNET interface is available only on ES4–8FE board;

Figure 87. 1660SM Block diagram – (ISA – ES boards)

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TO/FROM MATRIX

Control

DC/DC Converter

1

ETHERNET #14

14

Access card

ISA – ETHERNET PORT (10/100 Mb/s)

1

ETHERNET #1

T∅

11

ETHERNET #11 Data

Ethernet frame mapping into SDH VC OPTICAL MODULE #1

Gigabit Ethernet Optical Interfaces 1000 BASE–SX /LX /ZX

See Figure 85.

–Batt/Gnd

ETHERNET #1

1

1000 BASE–SX /LX/ZX

OPTICAL MODULE #2

2

1000 BASE–SX /LX/ZX –Batt/Gnd

Control

DC/DC Converter

Gigabit Ethernet Access card

ISA – GBIT ETHERNET PORT

T∅

Data

Ethernet frame mapping into SDH VCxc

OPTICAL MODULE #1

1

1000 BASE–SX /LX/ZX

OPTICAL MODULE #4

4

1000 BASE–SX /LX/ZX

1AA 00014 0004 (9007) A4 – ALICE 04.10

DC/DC Converter

Figure 88. 1660SM Block diagram – (ISA – ETHERNET boards)

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Ethernet frame mapping into SDH VC

Data

Ethernet Interfaces 10/100 Mbit/s Base T

11

ETHERNET #11

Ethernet Interfaces 10/100 Mbit/s Base T

T∅

Ethernet Interfaces

1

ETHERNET #1

10/100 Mbit/s Base T

ISA – ETHERNET PORT (10/100 Mb/s)

Gigabit Ethernet Optical Interfaces 1000 BASE–SX /LX /ZX

Control

1 ETHERNET #1

NETWORK PROCESSOR

16

STM4 1 STM4 2 STM4 3

ETHERNET #16 STM4 FRAME & INTERFACE

MPLS ENGINE TRAFFIC MANAGEMENT

STM4 4

OPTICAL MODULE #1

1

1000 BASE–SX /LX/ZX NETWORK PROCESSOR

–Batt/Gnd from Congi

Ethernet Interfaces 10/100 Mbit/s Base T

ISA – PR MATRIX

OPTICAL MODULE #2

DC/DC Converter

1000 BASE–SX /LX/ZX

Control PR Controller

from/to Matrix

2 GBA–PR Access card

2

Gigabit Ethernet Optical Interfaces 1000 BASE–SX /LX /ZX

TO/FROM STM4 LINE OR PORT CARD

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16FEA–PR Access card

Craft Terminal

RJ45

1AA 00014 0004 (9007) A4 – ALICE 04.10

or NMS

Figure 89. 1660SM Block diagram – (ISA–PR board)

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This sub–system allows connections between any SDH, SONET, PDH or ISA (Integrated Service Adapter) ports (see Figure 90. on page 189). The connections can be realized at VC–12, VC–3, and VC–4 level using a not blocking matrix present on the MATRIX unit. Several types of connections may be established, such as: •

Unidirectional Point to Point

•

Unidirectional Point to Multipoint

•

Bidirectional Point to Point

The maximum matrix cross connection capability can be 96 x 96 STM–1 equivalent port at VC–4 level or 64x64 STM–1 equivalent port at VC–12 / VC–3 level + 32x32 equivalent port at VC–4 level. The following table illustrates the connections for each unit: Table 31. High Order/Low Order connections for 1660SM STM–1, STM–4, STM–16 ports

OC3 ports

140 Mbit/s ports

34 Mbit/s 45 Mbit/s ports

2 Mbit/s ports

PORTS

Structure

AU–4

TU–3

TU–12

AU–3

VC–4

VC–3

VC–12

STM–1,

AU–4

Yes

–

–

–

Yes

–

–

STM–4,

TU–3

–

Yes

–

Yes

–

Yes

–

STM–16

TU–12

–

–

Yes

–

–

–

Yes

OC3

AU–3

–

Yes

–

Yes

–

–

–

140 Mbit/s

VC–4

Yes

–

–

–

Yes

–

–

34Mbit/s 45Mbit/s

VC–3

–

Yes

–

–

–

Yes

–

2Mbit/s

VC–12

–

–

Yes

–

–

–

Yes

The above connections allows the 1660SM to realize Multi Line Terminal configuration, Add/Drop configuration and Mini Cross–Connect configurations in linear links, rings, and mashed network as describe in Chapter 1 on page 65. AU4–4C and AU4–16C concatenated signals can also be cross connected between any STM–4 and STM–16 ports.

1AA 00014 0004 (9007) A4 – ALICE 04.10

Example of connections types are shown in Figure 90. on page 189 : • • • • • • • • •

ED

connections between 2 Mbit/s ports and STM–1 ports connections between 34 Mbit/s ports and STM–1 ports connections between 45 Mbit/s ports and STM–1 ports connections between 140 Mbit/s ports and STM–1 ports VCn connections between STM–1 ports and STM–4 ports VCn connections between STM–1 ports and STM–16 ports VCn connections between STM–4 ports and STM–16 ports VCn connections between ports of the same type etc. 02 3AL 91668 AA AA 636

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3.2 Connections sub–system

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The maximum quantity of interconnections depends on the matrix capacity and shelf composition.

STM–4

STM–16 STM–16

ÁÁÁ ÁÁÁ

ÁÁÁ ÁÁÁ ÁÁ ÁÁ

MATRIX spare

(1)

(2)

(1)

(3) (4) (5)

(6)

4xANY

(1)

(7)

4xOC3

MATRIX main

ÁÁ ÁÁÁ ÁÁ ÁÁÁ

(1)

(1)

ÁÁÁ ÁÁÁ

ÁÁ ÁÁ

(1)

access card

(1)

”Spare”

63x2 Mbit/s ”Main”

access card

34/45 Mbit/s

access card

4X 140 Mbit/s

4X STM–1

access card

access card

ISA units

access card

ÁÁÁ ÁÁÁ (1)

2 Mbit/s to 2 Mbit/s connections, 34Mbit/s to 34 Mbit/s connections, 45 Mbit/s to 45 Mbit/s connections, 140 Mbit/s to 140 Mbit/s, 155 Mbit/s to 155 Mbit/s STM–4 to STM–4, STM–16 to STM–16, 4xANY to 4xANY, OC3 to OC3.

(2)

STM–1 to STM–4/STM–16 connections; ISA to STM–1/STM–4/STM–16

(3)

140 Mbit/s to STM–1/STM–4/STM–16 connections

(4)

34 or 45 Mbit/s to STM–1/STM–4/STM–16 connections

1AA 00014 0004 (9007) A4 – ALICE 04.10

NOTES:

(5)

2 Mbit/s to STM–1/STM–4/STM–16 connections

(6)

4xANY to STM–4/STM–16 connections

(7)

OC3 to STM–1/STM–4/STM–16 connections ISA = ATM Matrix, PR_EA Matrix, ES and Ethernet boards Figure 90. High Order/Low Order connections for 1660SM

ED

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3.3.1 Signal management referred to ”G.783 1994” In the next paragraphs will be explained the SDH and PDH port signal management. The functional blocks in this description are similar to that utilized in the Craft Terminal application. For each port the description is subdivided in two part: –

Signal management from Side B (high bit rate signal) to Side A (low bit rate signal).

–

Signal management from Side A (low bit rate signal) to Side B (high bit rate signal).

1AA 00014 0004 (9007) A4 – ALICE 04.10

Anyway a signal may not transit through all the functional blocks (e.g. from side A to side B) but it comes back to the source side by means of the matrix (LPC, HPC) thus realizing a cross connection.

ED

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3.3 SIGNAL MANAGEMENT SUB–SYSTEM

3.3.1.1 SDH port signal management (For STM–1, STM–4 and STM–16 see Figure 91. on page 193)

1AA 00014 0004 (9007) A4 – ALICE 04.10

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

Side B to Side A description:

ED

•

SPI (Synchronous Physical Interface) It interface the physical transmission medium, regenerates and decodes line signal and detect the LOF alarm.

•

RST (Regenerator Section Termination) It manages the section overhead bytes for the Regeneration Section; it performed frame alignment detection, regenerator section trace recovery and mismatch detection, B1 BIP–8 errored block count.

•

MST (Multiplex Section Termination) It manages the section overhead bytes for the Multiplexing section; performs BIP–24 errored block count, MS–REI recovery, MS–RDI and MS–AIS detection.

•

MSP (Multiplex Section Protection) and MSPC (Multiplex Section Protection Connection) It provides protection for the STM–N signal against failures within a multiplex section, by using a bit oriented protocol for the MSP bytes K1,K2 and P, B1.

•

MSA (Multiplex Section Adaptation) It performs AU4 pointer interpretation, LOP and AIS detection, pointer justification.

•

HPOM (High Order Path Overhead Monitoring) It monitors the higher order VC–n for errors, and recover the trail termination status. it extract the payload independent overhead bytes J1, G1, B3.

•

HPC (High Order Path connection) This function assign higher order VCs of level n at its input port to higher order VCs of level n at its output port.

•

HSUT (Higher Order Supervisory Unequipped Termination) It performs the termination of an unequipped path recovering path trace information, REI and detecting HP–RDI (Path status monitoring),VC4 BIP–8 Errored Block count.

•

HPT (High Order Path Termination) This function recover the trail termination status. It extract the payload independent overhead bytes/bits (J1, G1, B3) from the VCn layer ;

•

HPA (High Order Path Adaptation) This functions provide VC–4 disassembly TU pointer interpretation, LOP and TU–AIS detection;

•

LPOM (Lower Order Path Monitor) It is used for performance monitoring purpose and for lower order SNCP/n.

•

LPC (Low Order Path Connection) It assigns lower order VCs of level m at its input ports to lower order VCs of level m at its output ports. The process does not affect the nature of the characteristic information of the signal.

•

LSUT (Lower Order Supervisory Unequipped Termination) It is used to monitor unequipped path trace, recovering VC–m unequipped signal label, BIP–2 recovery.

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1AA 00014 0004 (9007) A4 – ALICE 04.10

ED

•

LSUT (Lower Order Supervisory Unequipped Termination) It is used to monitor unequipped path trails; it inserts VC–m unequipped signal label, path trace, BIP–2, REI and RDI.

•

LPC (Low Order Path Connection) It assigns lower order VCs of level m at its input ports to lower order VCs of level m at its output ports. The process does not affect the nature of the characteristic information of the signal.

•

LPOM (Lower Order Path Monitor) It is used for performance monitoring purpose and for lower order SNCP/n.

•

HPA (High Order Path Adaptation) This function provides VC–4 assembly, TU pointer generator, TU–AIS.

•

HPT (High Order Path Termination) It performs path trace identification insertion, RDI and REI insertion VC–4 BIP–8 calculation and insertion, signal label insertion.

•

HPOM (High Order Path Overhead Monitoring) It monitors the higher order VC–4 for errors, and recover the trail termination status. it extract the payload independent overhead bytes J1, G1, B3.

•

HPC (High Order Path connection) This function assign higher order VCs of level n at its input port to higher order VCs of level n at its output port.

•

HSUT (Higher Order Supervisory Unequipped Termination) It generates and inserts an unequipped container, trail trace identifier, RDI and REI, VC–4 BIP–8.

•

MSA (Multiplex Section Adaptation) It performs AUG assembly, AU–4 pointer generation, AU–AIS generation

•

MSP (Multiplex Section Protection) and MSPC (Multiplex Section Protection Connection) It provides protection for the STM–N signal against failures within a multiplex section, by using a bit oriented protocol for the MSP bytes K1,K2 and P, B1.

•

MST (Multiplex Section Termination) It performs BIP–24 calculation and insertion, MS–REI, MS–RDI and MS–AIS insertion.

•

RST (Regenerator Section Termination) It performs frame alignment insertion , regenerator section path trace insertion BIP–8 (B1) calculation and insertion.

•

SPI (Synchronous Physical Interface) Signal conditioning for transmission medium

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Side A to Side B description:

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

Side A To point Y1 Figure 92.

From point Y2 Figure 92. X2

X1

LSUT

LSUT

Low Order Path Layer

LPC LPOM

HSUT

LPOM

HPA

HPA

HPT

HPT

To point W1 Figure 93. Z1

From point W2 Figure 93.

HSUT

Z2

High Order Path Layer

HPC HPOM

HPOM

MSA

MSA

MSP

MSPC

Multiplex Section Layer

MSP

MST

MST

RST

RST

SPI

SPI

Regenerator Section Layer

SDH Physical Layer

1AA 00014 0004 (9007) A4 – ALICE 04.10

Side B

Figure 91. SDH signal management block diagram

ED

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Ports managed are: 2Mbit/s (mapped into VC–12), 34Mbit/s (VC–3), 45Mbit/s (VC–3) and 140Mbit/s (VC–4). The following functions are associated with each PDH port. 2Mbit/s, 34 Mbit/s and 45 Mbit/s port management ( See Figure 92. on page 194 ) Side B to Side A description: •

PPI This block provides the interface between the physical transmission medium and the internal unit format. The received line signal is HDB3 coded. A decoder on the physical interface decodes the signal to NRZ (no return–to–zero) format.

•

LPA This block adapts user data for transport in the synchronous domain. For asynchronous user data, lower order path adaptation involves bit justification. The 2.048 Mbit/s is inserted into a VC–12, which is synchronized (stuffing) with the correspondent TU–12. The 34 Mbit/s or 45 Mbit/s is inserted into a VC–3, which is synchronized with the correspondent TU–3.

•

LPT For the 2.048 Mbit/s the LPT function creates a VC–12 by generating and adding POH to a C–12. The POH formats are defined in Recommendations G.708 and G.709. For the 34 Mbit/s and 45 Mbit/s the LPT functions creates a VC–3 by generating and adding POH to a C–3.

Side A to Side B description: •

LPT The LPT function terminates and processes the POH to determine the status of the defined path attributes.

•

LPA It extracts the POH from the VC–12 (2 Mbit/s) or VC–3 (34 Mbit/s and 45 Mbit/s) .

•

PPI This block provides the interface between the internal unit format and the physical transmission medium. It encodes HDB3 the signal to be sent on line. Side B

PPI

PPI

LPA

LPA

LPT

LPT

Y1

Y2

1AA 00014 0004 (9007) A4 – ALICE 04.10

From point X1 Figure 91.

To point X2 Figure 91. Side A

Figure 92. 2Mbit/s, 34 Mbit/s, 45 Mbit/s signal management block diagram

ED

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3.3.1.2 PDH port signal management

140 Mbit/s port management ( See Figure 93. on page 195 ) All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

Side B to Side A description: •

PPI This block provides the interface between the physical transmission medium and the internal unit format. The received line signal is CMI coded. A decoder on the physical interface decodes the signal to NRZ (no return–to–zero) format.

•

LPA The 140 Mbit/s plesiochronous stream is inserted in a C4 container to be adapted so as to be transported into the synchronous network.

•

HPT The Virtual Container (VC–4) is formatted. The VC–4 is structured so that its octets are distributed within a 125 µs. interval and consist of the C4 container and POH.

Side A to Side B description: •

HPT The HPT extract and processes the POH to determine the status of the defined path attributes.

•

LPA It extracts the 140 Mbit/s signal from the container C4 .

•

PPI This block provides the interface between the internal unit format and the physical transmission medium. It encodes CMI the signal to be sent on line.

Side B

PPI

PPI

LPA

LPA

HPT

HPT

w1

w2

From point Z1 Figure 91.

To point Z2 Figure 91. Side A

1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 93. 140Mbit/s signal management block diagram

ED

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3.3.2 SIGNAL MANAGEMENT referred to ”G. 783”

This paragraph has been introduced as an aid to the understanding of the terms used for the Termination Point (T.P.). These TPs can be accessed and managed by the operator for performance monitoring purpose . In the following will be explained the atomic functions naming conventions and the signal processing in the SDH and PDH port . 3.3.2.1 ATOMIC FUNCTION NAMING CONVENTIONS Each characteristic layer of the SDH network is splitted into different atomic functions : –

trail termination function : •

Source (So): additional information is added to the characteristic information to allow trail monitoring.

•

Sink (Sk): the information related to the trail monitoring is extracted

If a signal fail condition of the associated data signal is detected, a TSF signal is generated to inform the next downstream function. TSF is use in the HPOM (Snm) function to drive the SNCP/MSP protection. –

adaptation function : •

Source (So):the characteristic information is adapted from the client to the server layer

•

Sink (Sk): the characteristic information is adapted from the server to the client layer

The processes present in an adaptation function can be : encoding, rate changing, alignment, justification, multiplexing. If a signal fail condition of the associated data signal is detected, a SSF signal is generated to inform the next downstream function. –

connection function : it represents the connection functions inside the network ( link connection, sub–network network connection) and it is performed by the matrix functional block

Each atomic function is represented by a different symbol and named as follow: –

trail termination TT : triangle Source

Sink naming rules: _TT[ _]

–

example: _TT[ _]

adaptation A : trapezium Sink

Source

1AA 00014 0004 (9007) A4 – ALICE 04.10

naming rules: /_A[] –

connection C: circle or ellipse

naming rules: _C

ED

example: /_A[]

example: _C

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The ITU–T G.783 Recommendation describe the SDH characteristic in terms of atomic functions.

3.3.2.2 SDH PORT FUNCTIONAL BLOCKS

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(For STM–1 , STM–4 and STM–16 see Figure 94. on page 206) The received signal is either electrical STM–1 CMI coded (ITU–T G.703 Rec.) or optical STM–N (ITU–T G.957 Rec.). The SDH frame format is compliant with ITU_T G.707 Rec. In this paragraph will be explained the SDH and PDH port signal management referred to atomic function. For each port the description is subdivided in two part: –

Signal management from Side B (high bit rate signal) to Side A (low bit rate signal).

–

Signal management from Side A (low bit rate signal) to Side B (high bit rate signal).

Side B to Side A description: a)

SDH Physical layer (SPI)

It is the interface between the physical transmission medium and the Regeneration Section. The function performed are describe below: •

Optical or Electrical Section layer Trail Termination: OSn_TT_Sk or ESn_TT_Sk •

•

1AA 00014 0004 (9007) A4 – ALICE 04.10

b)

ED

input LOS detection.

Optical or Electrical Section layer Adaptation to Regenerator Section layer: OSn/RSn_A_Sk and ESn/Rsn_A_Sk •

descrambler.

• • •

A1, A2: frame alignment detection. OOF count and LOF detection. AIS or SSF insertion if LOF is detected

Regenerator Section layer (RST) •

Regenerator Section layer Trail Termination: RSn_TT_Sk • J0: regenerator section trace recovery and mismatch detection (TIM) (not managed in this release) • B1: BIP–8 Errored Block count: even bit parity is computed and compared with B1 recovered from the current frame. • AIS insertion if TIM is detected

•

Regenerator Section layer to Multiplex Section layer Adaptation: RSn/MSn_A_Sk • AIS insertion on AIS detection

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Multiplex Section layer : •

Multiplex Section layer Trail Termination (MST): MSn_TT_Sk • • • •

•

Multiplex Section layer MSn/MSnP_A_Sk • •

–

•

the K1–K2 information (APS protocol) is recovered . AIS or SSF insertion

AIS or SSF detection TSF insertion (on SSF detection)

Multiplex Section layer Adaptation to the High Order Path layer (MSA): MSn/Sn_A_Sk • • • • •

AU–4 Pointer interpreter. LOP detection AU–AIS detection AIS or SSF insertion (on LOP and AU–AIS detection) PJE (Pointer Justification Event) count.

High Order Path layer: •

High Order Path Overhead Monitoring Function (HPOM) –

High Order Path Overhead Trail Termination: Snm_TT_Sk • • • • • • •

•

J1: Path Trace information is recovered. G1[1–4]: The REI information is recovered. G1[5]: Path Status monitoring ––> HP–RDI detection. C2: Signal Label Monitoring ––> UNEQ and VC–AIS detection. B3: VC–4 BIP–8 Errored Block Count ––> Ex–BER and Signal Degrade alarm TSF insertion TSD insertion TSF and TSD are used for SNCP switch

High Order Supervisory Unequipped Termination –

1AA 00014 0004 (9007) A4 – ALICE 04.10

to the Multiplex Section Protection Sub–layer Adaptation:

Multiplex Section Protection Sub–layer Trail Termination: MSnP_TT_Sk • •

High Order Supervisory Unequipped Trail Termination (HSUT): Sns_TT_Sk • • • • •

ED

BIP–24N Errored Block count ––>Ex–BER, Signal Degrade alarm MS–REI recovery. MS–RDI detection. MS–AIS detection.

Multiplex Section Sub–layer Protection function (MSP): –

d)

B2: M1: K2[6–8]: K2[6–8]:

J1: G1[1–4]: G1[5]: C2: B3:

Path Trace information is recovered. The REI information is recovered. Path Status monitoring ––>HP–RDI detection. Signal Label Monitoring ––> UNEQ and VC–AIS detection. VC–4 BIP–8 Errored Block Count.

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c)

•

High Order Path Tandem Connection Trail Termination (according to Option 2 TC described in Recc. ITU–T G.707)

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–

High Order Path Tandem Connection Termination (HTCT): SnD_TT_Sk • • • • • •

•

•

N1[1–4]: VC–4 BIP–8 extraction and EDC calculation. N1[8][73]: RDI extraction. N1[5]: REI extraction. N1[7][74]: ODI extraction (Outgoing Defect Indication). N1[6]: OEI extraction (Outgoing Error Indication) N1[7–8]: extraction from the multiframed channel N1[7–8] of: FAS (Frame Alignment Signal) in frames 1 to 8. trace identifier in frames 9 to 72. TC RDI and ODI in frames 73 to 76. B3: BIP–8 compensation.

High Order Path Tandem Connection Adaptation (according to Option 2 TC described in Recc. ITU–T G.707) –

High Order Path Tandem Connection Adaptation (HTCA): SnD/Sn_A_Sk this function will restore the invalid Frame Start condition if that existed at the iput of the tandem connection. AIS insertion.

•

High Order Path Tandem Connection Monitoring (according to Option 2 TC described in Recc. ITU–T G.707) –

High Order Path Tandem Connection Monitoring (HTCM): SnDm_TT_Sk

1AA 00014 0004 (9007) A4 – ALICE 04.10

• • • • • •

ED

N1[1–4]: VC–4 BIP–8 extraction and EDC calculation. N1[8][73]: RDI extraction. N1[5]: REI extraction. N1[7][74]: ODI extraction (Outgoing Defect Indication). N1[6]: OEI extraction (Outgoing Error Indication) N1[7–8]: extraction from the multiframed channel N1[7–8] of: FAS (Frame Alignment Signal) in frames 1 to 8. trace identifier in frames 9 to 72. TC RDI and ODI in frames 73 to 76.

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•

• • • • • •

Low Order Path Overhead Monitoring Function (LPOM) –

Low Order Path Overhead Trail Termination: Smm_TT_Sk • • • • • • •

•

J2: Trace Identifier Monitoring. V5[8]: RDI information is recovered and reported. V5[3]: REI bit is recovered and the derived performance primitives are reported. V5[5–7]: Signal Label Monitoring ––> VC–AIS detection. V5[1,2]: VC–m BIP–2 Errored Block Count ––>Ex–BER, Signal Degrade alarm AIS or SSF detection––>SSF alarm TSF insertion (used for SNCP switch)

Low Order Supervisory Unequipped Termination (LSUT) –

Low Order Supervisory Unequipped Trail Termination: Sms_TT_Sk • • • • •

1AA 00014 0004 (9007) A4 – ALICE 04.10

VC–4 disassembly. TU pointer interpretation. LOP detection. TU–AIS detection. C2: HP–SLM (signal label mismatch) detection. H4: LOM (Loss of Multiframe) detection.

Low Order Path layer: •

ED

Path Trace information is recovered ––> TIM detection. The REI information is recovered. Path Status monitoring ––>HP–RDI detection. UNEQ detection. VC–4 BIP–8 Errored Block Count ––> Ex–BER, Signal Degrade alarm

High Order Path layer Adaptation to Low Order Path layer (HPA): Sn/Sm_A_Sk • • • • • •

e)

J1: G1[1–4]: G1[5]: C2: B3:

V5[5–7]: J2: V5[1,2]: V5[3]: V5[8]:

signal label is recovered from the VC–m. 000 (unequipped) is expected. trail trace identifier is recovered. BIP–2 is recovered. REI bit is recovered and the derived performance primitives is reported. RDI information is recovered and reported.

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High Order Path layer Trail Termination Function (HPT): Sn_TT_Sk

•

Low Order Path Tandem Connection Trail Termination (according to Option 2 TC described in Recc. ITU–T G.707)

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–

Low Order Path Tandem Connection Termination (LTCT): SmD_TT_Sk • • • • • •

• • •

N2[1–2]: VC–12 BIP–2 extraction and EDC calculation. N2[8][73]: RDI extraction. N2[5]: REI extraction. N2[7][74]: ODI extraction (Outgoing Defect Indication). N2[6]: OEI extraction (Outgoing Error Indication) N2[7–8]: extraction from the multiframed channel N2[7–8] of: FAS (Frame Alignment Signal) in frames 1 to 8. trace identifier in frames 9 to 72. TC RDI and ODI in frames 73 to 76. N2[4]: AIS detection V5[1–2]: BIP–2 compensation.

Low Order Path Tandem Connection Adaptation (according to Option 2 TC described in Recc. ITU–T G.707) –

Low Order Path Tandem Connection Adaptation (LTCA): SmD/Sm_A_Sk this function will restore the invalid Frame Start condition if that existed at the iput of the tandem connection. AIS insertion.

•

Low Order Path Tandem Connection Monitoring (according to Option 2 TC described in Recc. ITU–T G.707) –

Low Order Path Tandem Connection Monitoring (LTCM): SnDm_TT_Sk • • • • • •

1AA 00014 0004 (9007) A4 – ALICE 04.10

•

ED

N2[1–2]: VC–12 BIP–2 extraction and EDC calculation. N2[8][73]: RDI extraction. N2[5]: REI extraction. N2[7][74]: ODI extraction (Outgoing Defect Indication). N2[6]: OEI extraction (Outgoing Error Indication) N2[7–8]: extraction from the multiframed channel N2[7–8] of: FAS (Frame Alignment Signal) in frames 1 to 8. trace identifier in frames 9 to 72. TC RDI and ODI in frames 73 to 76. N2[4]: AIS detection

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Side A to Side B description: Low Order Path layer: •

Low Order Supervisory Unequipped Termination (LSUT) –

Low Order Supervisory Unequipped Trail Termination: Sms_TT_So • • • • •

•

V5[5–7]: J2: V5[1,2]: V5[3]: V5[8]:

signal label 000 (unequipped) is inserted in the VC–m. trail trace identifier is generated. BIP–2 is calculated and transmitted. the number of errors is encoded in REI. RDI indication is inserted.

Low Order Path Overhead Monitoring Function (LPOM) –

Low Order Path Overhead Trail Termination: Smm_TT_Sk • • • • •

•

J2: V5[8]: V5[3]: V5[5–7]: V5[1,2]:

Trace Identifier Monitoring. RDI information is recovered and reported. REI bit is recovered and the derived performance primitives are reported. Signal Label Monitoring ––> VC–AIS detection. VC–m BIP–2 Errored Block Count ––> Ex–BER, Signal Degrade alarm

Low Order Path Tandem Connection Adaptation (according to Option 2 TC described in Recc. ITU–T G.707) –

Low Order Path Tandem Connection Adaptation (LTCA): SmD/Sm_A_Sk this function will restore the invalid Frame Start condition if that existed at the iput of the tandem connection. AIS insertion.

•

Low Order Path Tandem Connection Trail Termination (according to Option 2 TC described in Recc. ITU–T G.707) –

Low Order Path Tandem Connection Termination (LTCT): SmD_TT_So • • • • •

1AA 00014 0004 (9007) A4 – ALICE 04.10

• •

ED

N2[8][73]: RDI insertion N2[5]: REI insertion N2[7][74]: ODI insertion (Outgoing Defect Indication) N2[6]: OEI insertion (Outgoing Error Indication) N2[7–8]: insertion in the multiframed channel N1[7 –8] of: FAS (Frame Alignment Signal) in frames 1 to 8 trace identifier in frames 9 to 72 TC RDI and ODI in frames 73 to 76 N2[1–2]: BIP–2 calculation and insertion V5[1–2]: BIP–2 compensation

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a)

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

•

Low Order Path Tandem Connection Monitoring (according to Option 2 TC described in Recc. ITU–T G.707) –

Low Order Path Tandem Connection Monitoring (LTCM): SnDm_TT_Sk • • • • • •

• b)

High Order Path layer: •

Low Order Path layer to High Order Path layer Adaptation (HPA): Sn/Sm_A_So • • • • •

•

•

J1: G1: B3:

path trace identifier is inserted. insertion of RDI[5] and/or REI[1–4] information. VC–4 Bip–8 calculation and insertion.

High Order Path Overhead Monitoring Function –

High Order Path Overhead Trail Termination (HPOM): Snm_TT_Sk • • • • • •

1AA 00014 0004 (9007) A4 – ALICE 04.10

VC–4 assembly. TU pointer generator. TU–AIS generator. C2: Signal label insertion. H4: Multiframe indicator

High Order Path layer Trail Termination Function (HPT): Sn_TT_So • • •

ED

N2[1–2]: VC–12 BIP–2 extraction and EDC calculation. N2[8][73]: RDI extraction. N2[5]: REI extraction. N2[7][74]: ODI extraction (Outgoing Defect Indication). N2[6]: OEI extraction (Outgoing Error Indication) N2[7–8]: extraction from the multiframed channel N2[7–8] of: FAS (Frame Alignment Signal) in frames 1 to 8. trace identifier in frames 9 to 72. TC RDI and ODI in frames 73 to 76. N2[4]: AIS detection

J1: Path Trace information is recovered. G1[1–4]: The REI information is recovered. G1[5]: Path Status monitoring ––> HP–RDI detection. C2: Signal Label Monitoring ––> UNEQ and VC–AIS detection. B3: VC–4 BIP–8 Errored Block Count. AIS or SSF detection ––> SSF alarm

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High Order Supervisory Unequipped Trail Termination (HSUT): Sns_TT_So • • • • •

•

Generation of an unequipped container and frame offset. C2: “unequipped” insertion. J1: trail trace identifier is generated. G1: insertion of RDI and/or REI information. B3: VC–4 Bip–8 calculation and insertion.

High Order Path Tandem Connection Adaptation (according to Option 2 TC described in Recc. ITU–T G.707) –

High Order Path Tandem Connection Adaptation (HTCA): SnD_A_So this function will replace the incoming Frame Start signal by a local generated one if all–ONEs VC is received.

•

High Order Path Tandem Connection Trail Termination (according to Option 2 TC described in Recc. ITU–T G.707) –

High Order Path Tandem Connection Termination (HTCT): SnD_TT_So • • • • •

• •

•

High Order Path Tandem Connection Monitoring (according to Option 2 TC described in Recc. ITU–T G.707) –

High Order Path Tandem Connection Monitoring (HTCM): SnDm_TT_Sk

1AA 00014 0004 (9007) A4 – ALICE 04.10

• • • • • •

ED

N1[8][73]: RDI insertion N1[5]: REI insertion N1[7][74]: ODI insertion (Outgoing Defect Indication) N1[6]: OEI insertion (Outgoing Error Indication) N1[7–8]: insertion in the multiframed channel N1[7 –8] of: FAS (Frame Alignment Signal) in frames 1 to 8 trace identifier in frames 9 to 72 TC RDI and ODI in frames 73 to 76 N1[1–4]: BIP–8 calculation and insertion B3: BIP–8 compensation

N1[1–4]: VC–4 BIP–8 extraction and EDC calculation. N1[8][73]: RDI extraction. N1[5]: REI extraction. N1[7][74]: ODI extraction (Outgoing Defect Indication). N1[6]: OEI extraction (Outgoing Error Indication) N1[7–8]: extraction from the multiframed channel N1[7–8] of: FAS (Frame Alignment Signal) in frames 1 to 8. trace identifier in frames 9 to 72. TC RDI and ODI in frames 73 to 76.

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–

c)

Multiplex Section layer:

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•

Multiplex Section layer Adaptation to the High Order Path layer (MSA): MSn/Sn_A_So • • •

•

Multiplex Section Sub–layer Protection function (MSP) –

Multiplex Section Protection Sub–layer Termination: MSnP_TT_So •

–

•

generation of K1–K2 information (APS protocol).

Multiplex Section layer Trail Termination: MSn_TT_So • • • •

B2: M1: K2[6–8]: K2[6–8]:

BIP–24N calculation and insertion. MS–REI insertion. MS–RDI insertion. MS–AIS insertion.

Regenerator Section layer (RST) •

Multiplex Section layer to Regenerator Section layer Adaptation : RSn/MSn_A_So •

•

RS–AIS insertion.

Regenerator Section layer Trail Termination: RSn_TT_So • • •

e)

no information is inserted.

Multiplex Section layer Adaptation to the Multiplex Section Protection Sub–layer: MSn/MSnP_A_So •

d)

AUG assembly and byte interleaving. AU–4 Pointer generator. AU–AIS generator.

A1, A2: J0: B1:

frame alignment insertion. regenerator section trace insertion (not managed in this release) BIP–8 calculation and insertion.

SDH Physical layer (SPI)

It is the interface between Regeneration Section and the physical transmission medium. The function performed are describe below: •

Optical or Electrical Section layer Adaptation to Regenerator Section layer: OSn/RSn_A_So and ESn/Rsn_A_So: • •

1AA 00014 0004 (9007) A4 – ALICE 04.10

•

ED

scrambler. AIS generator (on LOS or LOF).

Optical or Electrical Section layer Trail Termination: OSn_TT _So or ESn_TT _So • signal conditioning for transmission medium (e.g. electrical/optical conversion etc.)

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Side A

LPOM Smm

LTCM SmDm

LTCT SmD

To point Y1 From point Y2 Figure 95. Figure 95. Figure 96. Figure 96. LSUT

X1

X2

Sms

Low Order Path Layer

LTCA SmD/Sm

LSUT Sms

LTCM SmDm

LTCT SmD

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LTCA SmD/Sm

LPOM Smm

Sm LPC

Sn/Sm

HTCA SnD/Sn

HTCT Snd

HPOM Snm

HSUT Sns

Sn/Sm HPT

HPT

Sn

High Order Path Layer

HPA

HPA

HTCA SnD/Sn

Sn

To point W1 From point W2 Figure 97. Figure 97. Z2 Z1

HSUT Sns

HPOM Snm

HTCT Snd

Sn HPC

HTCM SnDm

HTCM SnDm

MSA (*)

MSn/Sn

MSn/Sn

MSnP

MSnP

MSP

MSP

MSnPC MSn/MSnP

MST

MSn

MSn

RSn/MSn

RSn/MSn

RSn

RSn

MST

RST

OSn/RSn or ESn/RSn OSn or ESn

Multiplex Section Layer

MSn/MSnP

RST

SPI

MSA (*)

OSn/RSn or ESn/RSn OSn or ESn

SPI

Regeneration Section Layer

SDH Physical Layer

1AA 00014 0004 (9007) A4 – ALICE 04.10

Side B (*) – 1,4,16,64 MSn/Sn are multiplied in STM–n

Figure 94. 1660SM Block Diagram: signal management (SDH port)

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3.3.2.3 PDH PORT FUNCTIONAL BLOCKS

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In LC–NG PDH Low Order ports managed are 2Mbit/s (mapped into VC–12), 34Mbit/s (VC–3), 45Mbit/s (VC–3) and 140Mbit/s (VC–4). The following functions are associated with each PDH port. 2 MBIT/S PORT MANAGEMENT (See Figure 95. on page 208 ) Side B to Side A description: a)

Low Order Path layer: •

Low Order Path layer Trail Termination Function (LPT): S12_TT_Sk • • • • •

•

Low Order Path layer Adaptation to PDH Section layer (LPA): S12/P12x_A_Sk or S12/P12s_A_Sk • •

b)

J2: trail trace identifier is recovered ––> TIM detection. V5[1,2]: BIP–2 is recovered ––> Ex–BER, Signal Degrade alarm V5[3]: REI bit is recovered and the derived performance primitives is reported. V5[8]: RDI information is recovered and reported. AIS or SSF detection ––> SSF alarm

V5[5–7]: Signal label detection in the byte V5[5–7] ––> Signal label Mismatch detection AIS or SSF is applied if Signal label Mismatch is detected

Electrical PDH Physical Section layer (PPI) •

Adaptation to PDH section layer: E12/P12x_A_So or E12/P12s_A_So •

•

It convert the internal signal code to the line code.

Trail Termination: E12_TT_So •

signal conditioning for transmission medium ( e.g. electrical level, etc.)

Side A to Side B description: a)

Electrical PDH Physical Section layer (PPI) •

Trail Termination: E12_TT_Sk • •

•

PDH physical adaptation layer: E12/P12x_A_Sk or E12/P12s_A_Sk • • •

b)

PDH Section layer S12/P12s_A_So •

• 1AA 00014 0004 (9007) A4 – ALICE 04.10

timing is extracted. data are decoded. AIS insertion if LOF or AIS is detected.

Low Order Path layer: •

to Low Order Path layer Adaptation

(LPA): S12/P12x_A_So or

V5[5–7]: Signal label insertion in the byte V5[5–7].

Low Order Path layer Trail Termination function (LPT): S12_TT_So • • • •

ED

input LOS detection. AIS insertion if LOS is detected

J2: V5[1,2]: V5[3]: V5[8]:

trail trace identifier is generated. BIP–2 is calculated and transmitted. the number of errors is encoded in REI. RDI indication is inserted.

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Side A

PPI

PPI E12

E12

E12/P12

E12/P12

LPA

LPA S12/P12

Low Order Path

S12/P12

Layer

LPT

S12

LPT

S12

Y2

Y1

To point X2

From point X1

Figure 94.

Figure 94.

1AA 00014 0004 (9007) A4 – ALICE 04.10

Side B

Figure 95. 1660SM Block Diagram: signal management ( 2Mbit/s PDH ports)

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34 MBIT/S AND 45 MBIT/S PORT MANAGEMENT

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(See Figure 96. on page210 ) Side B to Side A description: a)

Low Order Path layer: •

Low Order Path layer Trail Termination Function (LPT): S3_TT_Sk • • • • • •

•

Low Order Path layer Adaptation to PDH Section layer (LPA): S3/P3x_A_Sk or S3/P3s_A_Sk • •

b)

J1: Path Trace information is recovered ––> TIM detection. G1[1–4]: The REI information is recovered. G1[5]: Path Status monitoring ––>HP–RDI detection. C2: UNEQ detection. B3: VC–3 BIP–8 Errored Block Count ––> Ex–BER, Signal Degrade SSF detection ––> SSF alarm

C2: Signal label detection in the byte C2 –> Signal label Mismatch detection. AIS or SSF is applied if TSF or Signal label Mismatch is detected

Electrical PDH Physical Section layer (PPI) •

Adaptation to PDH section layer: E3/P3x_A_So or E3/P3s_A_So •

•

It convert the internal signal code to the line code (HDB3)

Trail Termination: E3_TT_So •

signal conditioning for transmission medium ( e.g. electrical level, etc.).

Side A to Side B description: a)

Electrical PDH Physical Section layer (PPI) •

Trail Termination: E3_TT_Sk •

•

PDH physical Adaptation layer: E3/P3x_A_Sk or E3/P3s_A_Sk • • • •

b)

PDH Section layer to Low Order Path layer Adaptation (LPA): S3/P3x_A_So or S3/P3s_A_So •

• 1AA 00014 0004 (9007) A4 – ALICE 04.10

timing is extracted. data are decoded. AIS detection and insertion. LOF detection (only in case of E3/P3x_A_Sk)

Low Order Path layer: •

The signal label is inserted in C2

Low Order Path layer Trail Termination Function (LPT): S3_TT_So • • •

ED

Input LOS detection.

J1: G1: B3:

path trace identifier is inserted. insertion of RDI[5] and/or REI[1–4] information. VC–3 Bip–8 calculation and insertion.

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Side A

PPI

PPI E3

E3

E3/P3

E3/P3

LPA

LPA S3/P3

Low Order Path Layer

S3/P3

LPT

LPT S3

S3

Y1

Y2

From point X1 Figure 94.

To point X2 Figure 94.

1AA 00014 0004 (9007) A4 – ALICE 04.10

Side B

Figure 96. 1660SM Block Diagram: signal management ( 34 Mbit/s and 45 Mbit/s PDH ports)

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140 MBIT/S PORT MANAGEMENT

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(See Figure 97. on page 212) Side B to Side A description: a)

High Order Path layer: •

High Order Path layer Trail Termination Function (HPT): S4_TT_Sk • • • • • •

•

Low Order Path layer Adaptation to PDH Section layer (LPA): S4/P4x_A_Sk or S4/P4s_A_Sk • •

b)

J1: Path Trace information is recovered ––> TIM detection. G1[1–4]: The REI information is recovered. G1[5]: Path Status monitoring ––>HP–RDI detection. C2: UNEQ detection. B3: VC–4 BIP–8 Errored Block Count––> Ex–BER, Signal Degrade alarm SSF detection ––> SSF alarm

C2: Signal label detection in the byte C2 –> Signal label Mismatch detection. AIS or SSF is applied if TSF or Signal label Mismatch is detected

Electrical PDH Physical Section layer (PPI) •

Adaptation to PDH section layer:E4/P4x_A_So or E4/P4s_A_So •

•

It convert the internal signal code to the line code (CMI)

Trail Termination: E4_TT_So •

signal conditioning for transmission medium ( e.g. electrical level, etc.).

Side A to Side B description: a)

Electrical PDH Physical Section layer (PPI) •

Trail Termination: E4_TT_Sk •

•

PDH physical Adaptation layer: E4/P4x_A_Sk or E4/P4s_A_Sk • • • •

b)

PDH Section layer to Low Order Path layer Adaptation (LPA): S4/P4x_A_So or S4/P4s_A_So •

• 1AA 00014 0004 (9007) A4 – ALICE 04.10

timing is extracted. data are decoded. AIS detection and insertion. LOF detection (only in case of E4/P4x_A_Sk)

Low Order Path layer: •

The signal label is inserted in C2

High Order Path layer Trail Termination Function (HPT): S4_TT_So • • •

ED

Input LOS detection.

J1: G1: B3:

path trace identifier is inserted. insertion of RDI[5] and/or REI[1–4] information. VC–4 Bip–8 calculation and insertion.

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Side A

PPI

PPI E4

E4

E4/P4

E4/P4

LPA

LPA S4/P4

S4/P4

High Order Path Layer HPT

S4

HPT

W1

S4

W2

From point Z1

To point Z2

Figure 94.

Figure 94.

1AA 00014 0004 (9007) A4 – ALICE 04.10

Side B

Figure 97. 1660SM Block Diagram: signal management ( 140 Mbit/s PDH ports)

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3.4 ISA (Integrated Service Adapter) introduction Today’s metropolitan and regional optical transmission networks need the flexibility to support new and existing services. As new data services overcome traditional voice services in terms of global traffic volume, telecommunication operators face a host of challenges. These include finding the optimal solution with the bandwidth to handle increasing data traffic, keeping infrastructure updating investments to a minimum and protecting their high revenues on traditional voice services. Whereas core networks have to provide traffic with huge bandwidth capacity, metro and regional networks need to focus on better aggregating traffic with refined dimensioning and improved network resource allocation. Integrated ”data–aware” features distributed along the optical transmission nodes of today’s metro networks enable multi–service and multi–technology transmission of data services. They optimize the network infrastructure and bandwidth allocation, giving carriers the twofold benefit of reducing the need for extra investments in dedicated data equipment and safeguarding their high revenues on traditional voice services. Alcatel’s Integrated Service Adapter (ISA) series of plug–in cards are specially designed for the Optical Multi–Service Nodes (OMSN) family (1660SM is part of this family) . They enhance the optical transport network by adding data–aware features that are easy to introduce, allowing carriers to efficiently and cost–effectively aggregate, switch and transport the expanding amount of data services in their metropolitan network. 1660SM equipped with ISA plug–in cards give telecom operators a new generation modular platform for multi–service SDH transport and further strengthen Alcatel’s leading position in the supply of optical multi–technology transmission networks. Whenever and wherever it is needed in the metro network, OMSNs extend their multi–service functionality by integrating ISA plug–in ATM switching and Ethernet/Gigabit Ethernet rate–adaptive transport capabilities into a single optical network element efficiently and cost–effectively. The ISA plug–ins bring metro networks the switching intelligence needed to aggregate and groom mixes of different packet–based data protocols and traditional TDM services (refer to Figure 98. on page 214). ATM and Ethernet ISA cards are able to provide services such as ATM Virtual Private Networks, Broadband Virtual Leased Lines and TLS. The OMSN product family allows operators of SDH transport networks to introduce a wide variety of data managed services including top–level differentiated QoS capabilities, variable service rates and traffic congestion management. Different types of ISA cards can be easily and quickly plugged into 1660SM. The system is modular and the plug–ins can be chosen according to the specific application the optical multi–service equipment needs to manage.

1AA 00014 0004 (9007) A4 – ALICE 04.10

In the following will be explained the different ISA boards type and their application in the network: –

ISA – ATM (Asynchronous Transfer Mode) refer to paragraph 3.5 on page 215.

–

ISA – PR_EA (Packet Ring Edge Aggregator) refer to paragraph 3.6 on page 224

–

ISA – PR (Packet Ring) refer to paragraph 3.7 on page 235

–

ISA – ETHERNET/FAST ETHERNET/GIGABIT ETHERNET refer to paragraph 3.8 on page 253

–

ISA – ES (Ethernet Switch) refer to paragraph 3.9 on page 270

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SAN

UMTS

ISP1 ISP2 RNC

DWDM

ATM

POS Radio

ATM

LMDS

Optical Ring Eth

OMSN

DWDM/OMSN

Enterprise ATM

DWDM

DSL DSL

CORE

GbE

EDGE

1AA 00014 0004 (9007) A4 – ALICE 04.10

ACCESS

Residential

Enterprise

Figure 98. Example of technology convergency with ISA boards in OMSN

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3.5 ISA – ATM management sub–system 3.5.1 ATM ( Asynchronous Transfer Mode) basic Asynchronous Transfer Mode (ATM) is an International Telecommunication Union Telecommunication Standardization Sector (ITU–T) standard for cell relay wherein information for multiple service types, such as voice, video, or data, is conveyed in small, fixed–size cells. ATM networks are connection oriented. This chapter provides summaries of ATM protocols, services, and operation. According to ITU–T Recommendation I.311, an ATM transport network has two layers: the ATM layer and the physical layer as shown in Table 32. . Table 32. ATM transport network layered model Higher layer ATM layer

VC (Virtual Channel) level VP (Virtual Path) level

ATM Transport network Physical Layer

Transmission Path Level Transmission Media Level

The ATM layer is subdivided into two levels: the VP level and the VC level. The relations between the Virtual Channel, the Virtual Path and the Transmission Path are shown in Figure 99. on page 215.

VP

VC VC VC

ÔÔÔÔÔÔÔÔÔÔÔÔÔÔ ÔÔÔÔÔÔÔÔÔÔÔÔÔÔ ÔÔÔÔÔÔÔÔÔÔÔÔÔÔ ÔÔÔÔÔÔÔÔÔÔÔÔÔÔ ÔÔÔÔÔÔÔÔÔÔÔÔÔÔ ÔÔÔÔÔÔÔÔÔÔÔÔÔÔ ÔÔÔÔÔÔÔÔÔÔÔÔÔÔ ÔÔÔÔÔÔÔÔÔÔÔÔÔÔ

VP

VP

VP

Transmission Path

VP

VP

VC VC VC

1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 99. Relationship between the VC, the VP and the TP

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ATM transfers information in fixed –size unit called cells ; each cell consist of 53 octets, or bytes. The first 5 bytes contain cell–header information and the remaining 48 contain the “payload” (user information). Figure 100. on page 216 illustrates the basic format of an ATM cell.

8 Bits

HEADER (5 bytes)

53 Bytes PAYLOAD (48 bytes)

Figure 100. Basic format of an ATM cell An ATM network is made up of an ATM switch and ATM endpoints. An ATM switch is responsible for cell transit through an ATM network. An ATM switch accepts the incoming cell from an ATM endpoint or another ATM switch. It then reads and updates the cell–header information and quickly switches the cell to an output interface toward its destination. An ATM endpoint (or end system) contains an ATM network interface adapter. Examples of ATM endpoints are workstations, routers etc.

1AA 00014 0004 (9007) A4 – ALICE 04.10

An ATM network consists of a set of ATM switches interconnected by point–to–point ATM links or interfaces. ATM switches support two primary types of interfaces: UNI and NNI. The UNI connects ATM end systems (such as hosts and routers) to an ATM switch. The NNI connects two ATM switches. Depending on whether the switch is owned and located at the customers premises or publicly owned and operated by the telephone company, UNI and NNI can be further subdivided into public and private UNIs and NNIs. A private UNI connects an ATM endpoint and a private ATM switch. Its public counterpart connects an ATM endpoint or private switch to a public switch. A private NNI connects two ATM switches within the same private organization. A public one connects two ATM switches within the same public organization (see Figure 101. on page 217).

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1AA 00014 0004 (9007) A4 – ALICE 04.10

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Public ATM Network

Private ATM Network ATM Switch

Public UNI Public NNI

ATM Switch

ED Pivate NNI ATM Switch

ATM Switch UNI UNI

Private UNI UNI

Figure 101. ATM network interface

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8 Bits

HEADER (5 Bytes)

8 Bits VPI

GFC VPI

VPI VCI

VCI PT

PT

CLP

HEC

PAYLOAD (48 Bytes)

53 Bytes

HEC

CLP

ATM UNI cell

ATM NNI cell

GFC (Generic Flow Control) Generic Flow Control field permits multiplexing the transmission of several terminals on the same user interface. It is used for the traffic from the users to the network VPI/VCI (Virtual Path Identifier / Virtual Channel Identifier) The VPI/VCI field contains 24 bits on the UNI interface and 28 bits on the NNI interface. The VPI field is 8 to 12 Bits, allowing 256 to 4096 virtual paths. Each path can consist of 64.000 VCIs. VPI/VCI identifies the next destination of a cell as it passes through a series of ATM switches on the way to its destination. PT (Payload Type) Payload Type field id used to indicate different types of payload for OAM. It also indicates ”end of packet” wich is used with ATM Adaptation Layer 5 CLP (Cell Loss Priority) Cell Loss Priority bit is used for buffer managementin conjunction with congestion control If it is set to 1, then the cell within a buffer could be discarded. When the CLP bit is set to 0, the cell could not be discarded

1AA 00014 0004 (9007) A4 – ALICE 04.10

HEC (Header Error Control) Header Error Control field allows to either correct single bit errors or detect multiple bit errors. If multiple bit errors are detected the cell is dropped.

Figure 102. UNI and NNI ATM cell header and payload

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An ATM cell header can be one of two formats: UNI or the NNI. The UNI header is used for communication between ATM endpoints and ATM switches in private ATM networks. The NNI header is used for communication between ATM switches. Figure 102. on page 218 depicts the basic ATM cell format, the ATM UNI cell–header format, and the ATM NNI cell–header format.

3.5.2 ATM in1660SM

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1660SM can integrate ATM switch functionality through dedicated plug–in board. Three ATM switch boards are available: –

ATM MATRIX 4X4 that provide a 622 Mb/s throughput (4xSTM–1 equivalent capacity); this board includes a local STM–1 access port on the front panel. Up to 16 TPs can be configured among VC–4, VC–3, VC12, E3 and E1.

–

ATM MATRIX 4X4V2 that provide a 622 Mb/s throughput (4xSTM–1 equivalent capacity); Up to 252 TPs can be configured among VC–4, VC4–C, VC–3, VC12, E3, T3 and E1.

–

ATM MATRIX D3 that provide a 622 Mb/s throughput (4xSTM–1 equivalent capacity); Up to 16 TPs can be configured among VC–4, VC4–C, VC–3, VC12, E3, T3 and E1.

–

ATM MATRIX 8X8 that provide a 1.2 Gb/s throughput (8xSTM–1 equivalent capacity) Up to 32 TPs can be configured among VC–4, VC4–C, VC–3, VC12, E3 and E1.

If more capacity is needed more than one ATM board in a single 1660SM can be used. The overall ATM Switch functional model is compliant to ITU–T I.731, I.732, ETSI EN 300 417–1–1/2–1, af–tm–0010.002. The board provide ATM traffic control functions, such as shaping (Input and Output) and policing (UPC, NPC) which are needed to avoid network congestion (SCD, EPD, TPD). The standard PDH and SDH ports of 1660SM can be used to transport ATM traffic streams. The ATM traffic can be mapped on the VC–12, VC–3, VC–4 and VC–4–4c SDH Virtual Containers and on E1, E3 PDH signals, in accordance with relevant ITU–T recommendations (G.804 and G.832 for ATM over PDH and G.707 for ATM over SDH). The following ATM connection types are supported: •

Permanent Virtual Connections (PVCs): Virtual Path Connections (VPCs) and Virtual Channel Connections (VCCs ) provisioned by the TMN.

•

Switched Virtual Connections (SVCs): VPCs or VCCs set–up end–to–end in real–time by signaling procedures. Virtual Channel Connections (VCC) can be transparently tunnelled via a Hard or Soft VP tunnel. (Note: UNI signalling is not supported).

1AA 00014 0004 (9007) A4 – ALICE 04.10

Two instances of Permanent Virtual Connections (PVCs) are defined on network level:

ED

•

Hard PVC: Virtual Path Connections (VPC) and Virtual Channel Connections (VCC); it is a PVC established/released upon a request initiated by a management request procedure (all the nodes involved by the connections need to be configured by the Network Management).

•

Soft PVC: Virtual Path Connections (Soft–VPC) and Virtual Channel Connections (Soft–VCC). The P–NNI signalling and routing is supported according to af–pnni–0055.000, af–pnni–0066.000 and af–pnni–0081.000. In the scope of Soft–PVC the two connecting points contiguous to the connection end–points are defined as calling end–point and called end–point: the former is responsible to start the signaling process in order to establish the Soft–PVC and to restore the connection in case of failures. It is provisioned by the ATM–OS only in the calling and called endpoints and setup by means of a signaling protocol, e.g. the PNNI, in all the other intermediate connecting points as if it is a SVC. The routing of the soft–PVC is done by the calling endpoint by means of the PNNI Routing Algorithm presenting every ATM board together with some network topology knowledge.

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Uni–directional and bi–directional point–to–point ATM connections (VPC and VCC) are supported. Uni–directional (for broadcast or drop&continue usages) point–to–multipoint ATM connections (VPC and VCC) are also supported. The uni–directional point–to–multipoint ATM connection is supported via the Spatial (cell copy to different interfaces) and Logical (cell copy to different flows on the same interface) Multicast feature of the ATM switch. 3.5.2.2 ATM traffic management According to ITU–T I.358 terminology (ATM–Forum TM4.1) the following ATM Transfer Capabilities (ATC) are supported on all connections (see Table 33. on page 220). Table 33. ATM traffic contracts. ATM FORUM

ITU–T

CBR

DBR class 1

PCR0+1, CDVTPCR

CTD, CDV, CLR0+1

––

DBR class 2

PCR0+1, CDVTPCR

CLR0+1

UBR

DBR class U

PCR0+1, CDVTPCR

––

rt–VBR.1

SBR.1 class 1

PCR0+1, CDVTPCR, SCR0+1, CDVTSCR

CTD, CDV, CLR0+1

nrt–VBR.1

SBR.1 class 2

PCR0+1, CDVTPCR, SCR0+1, CDVTSCR

CLR0+1

nrt–VBR.2

SBR.2 class 3

PCR0+1, CDVTPCR, SCR0+1, CDVTSCR

CLR0

nrt–VBR.3

SBR.3 class 3

PCR0+1, CDVTPCR, SCR0+1, CDVTSCR

CLR0

GFR.2

GFR.2

PCR0+1, CDVTPCR, MCR0, MBS, MFL

minimum CLR/FLR for high priority cells/frame

Notes: PCR: CDVT: SCR: MCR: MBS: CLR:

Traffic type parameter

QoS class parameter

Peak Cell Rate Cell Delay Variation Tolerance Sustainable Bit Rate Minimum Cell Rate Maximum Burst Size Cell Loss Ratio

ATC and example of applications CBR (Constant Bit Rate) / DBR (Deterministic Bit Rate): Static amount of bandwidth that has to be reserved. Used for real–time application very sensitive to cell delay variation like circuit emulation, video and voice at constant rate.

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VBR (Variable Bit Rate ) / SBR ( Statical Bit Rate): – Real Time ( rt ): those listed above but at variable rate – Non –real–time ( nrt ) with bursty traffic: Banking transactions, Frame Relay services UBR (Unspecified Bit Rate): Non real–time application, best effort: Banking transactions, World Wide Web (WWW) E–mail, LAN interconnection GFR (Guaranteed Frame Rate) : Non –real–time application with minimum throughput guarantee. Traffic sent beyond this rate ( extra traffic) will receive fair share of resource.

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3.5.2.1 ATM point to point and point to multipoint connections

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The traffic contract is used as input to the Connection Admission Control (CAC) or Global CAC (GCAC) for Soft–PVC in order to accept/reject the ATM connection. Usage Parameter Control (UPC) can be performed at User–Network Interface (UNI) while Network Parameter Control (NPC) can be performed at Network–Network Interface (NNI) or Inter–Carrier Interface (ICI); UPC/NPC can be performed at VP and VC level. Input Shaping can be performed in order to guarantee that incoming traffic is coherent with the resource allocation performed by the CAC. Output Shaping can be performed in order to guarantee that outgoing VPC is coherent with the resource allocation performed by the CAC when several VCC are multiplexed in the outgoing VPC. Congestion control and queues management are performed and alarms are generated accordingly. Traffic and Congestion management is according to ITU–T I.371, ATM Forum af–tm–0056.000. 3.5.2.3 ATM OAM F4 and F5 flows The ATM Switch board support the following OAM functionality at F4 (VP level) and F5 (VC level): •

Fault Management functions supported for all the supported ATM connections are Alarm Indication Signal / Remote Defect Indication (AIS/RDI), Continuity Check (CC) defects and Loop–back. Defects and possible subsequent failures are detected and reported.

•

Performance Management (PM) functions are Forward Monitoring and reporting. The supported ATM cell transfer outcomes are successful cell transfer, tagged cell transfer, errored cells, lost cells, mis–inserted cells and severely errored cell–block. The supported ATM performance parameters are Cell Loss Ratio, Cell mis–insertion Rate, Severely Errored Cell Block Ratio, Cell Transfer Delay, and Cell Delay Variation; moreover, the availability/unavailability status and parameters and the Severely Errored Second are determined.

•

Activation and De–activation of Performance Management (PM) and Continuity Check (CC) are supported.

•

Cell Insertion, extraction, non–intrusive monitoring and loop–back functions and the related processing can be performed at F4 and F5 levels depending on the setting of VPC/VCC end–points and segment end–points before and after the ATM Switching Matrix.

•

OAM is performed according to ITU–T I.610. Performance and Availability according to I.356 and I.357.

3.5.2.4 ATM Virtual Path Group Protection (VPG) The ATM VPG Protection is supported (on Hard–PVC) in order to facilitate fast ATM layer protection switching in cases where the under–laying SDH protection mechanism is not used. The uni–directional and bi–directional 1+1 and 1:1 VPG protection schemes are supported to allow high–priority traffic protection eventually dropping in 1:1 scheme the low–priority traffic. The Signal Fail is used as a switching trigger mechanism. VPG Protection follows ITU–T I.630. 3.5.2.5 ATM switching modules architecture

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The ATM switch is cascaded to the SDH matrix via back–panel connection (see Figure 103. on page 222) In a given node, SDH VCs or PDH flows carrying ATM cells that do not require switching in the ATM layer, at virtual path (VP) / virtual channel (VC) can be cross–connected transparently by the SDH matrix directly, without unnecessarily loading the ATM switch (pass through functionality).

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OMSN Port

Pass–through traffic

RX

TX

TX

RX

STM– STM–4

STM– STM–4

OMSN Port

STM– STM–1

SDH Xconnection

OMSN Port

RX

TX

TX

RX

STM– STM–1 OMSN Port

STM– STM–1

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OMSN Port

Traffic consolidation

OMSN Port

RX

TX

SDH MATRIX

STM– STM–1

TX

RX

OMSN Port

STM– STM–1

–Cell switching

RX TX

SDH termination Traffic policing and shaping

Local Port (*)

ATM ENGINE –

TX RX

STM– STM–1 port

ATM Matrix

NOTES: (*) Available only on ATM MATRIX 4X4

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Figure 103. 1660SM with ATM Matrix architecture

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3.5.2.6 ATM switching modules application The main application of the ATM board is to consolidate ATM traffic collected from different sources onto shared SDH VCs (virtual containers) in STM–n rings and to switch the ATM traffic, as needed at VP and /or VC level, into the network.

Wasted bandwidth

SDH circuits E3

E3 E3

E3

E3

SDH VC–4 [3 X VC–3]

E3

ADM

ADM

Free bandwidth Consolidation E3

Data flows

E3

E3

STM–1 E3

SDH VC–4 [3 X VC–3] E1

1660SM

1660SM ATM board

Figure 104. Leased line service versus Data transport service Typical applications of the atm board concept are ADSL, UMTS and LMDS metropolitan networks.

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In all those scenarios the Provider can take great advantage of the distributed switching functionality for optimizing the transmission resources avoiding wasting capacity not effectively used by the paying traffic. The switch can also be used in FTTB scenarios and as CPE where a mix of TDM and ATM services in the same box results in benefits for both the Provider and the Customers.

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3.6.1 PR_EA (MPLS) generalities The MPLS (Multi Protocol Label Switching) technique is used in Alcatel transport systems in order to distribute and route data packets originated by the network layer (level 3 of the protocol stack) and encapsulated into the Ethernet 802.3 frame; it can be seen as a “server” layer for the Ethernet “client” layer (called “MPLS over SDH”). The data may also be “MPLS–packed” at the network edge, and transported over Ethernet; this transport modality is called “MPLS over Ethernet”. MPLS operates at the level 2 of the protocol stack and uses the SDH as its physical layer to transport and aggregate the various streams of data packets (MPLS over SDH); see Table 34. on page 224. The “MPLS over Ethernet” layering is illustrated in Table 35. page 224. The MPLS technique consists of binding one or more “Labels” to the packets, in this way permitting the forwarding of a packet to the other nodes of the network without inspecting the level 3 header, only the look up of the attached label(s) is needed. The classification of the incoming packets are performed only once, at the edge of the MPLS network; the inner MPLS routers have only to select the “next hop” to which forwarding the incoming packets, by looking the top label. PR_EA (Packet Ring Edge Aggregator) is an Alcatel mark indicating a system that is able to aggregate, at the edge of the MPLS network (ring topology), many mpls packets communications. It is a “path oriented” connection–less service; all the packets belonging to the same stream and assigned to the same class of service are all treated the same way by a router. In other words, when they enter the network, the packets are assigned to a “Forwarding Equivalence Class” (FEC); the subsequent packets with the same destination and the same quality of service are assigned to the same FEC; also other packets belonging to different streams can be assigned to the same FEC, in this way aggregating various packets streams to a common path. This common path is called LSP (Label Switched Path) and can be treated by the intermediate nodes as a tunnel. The intermediate inner nodes have in charge the only forwarding of the packets, and all the incoming packets within the same LSP will be forwarded toward the same direction. For more information about MPLS refer to RFC_3031, RFC_3032, RFC_3209, RFC_3270, ITU–T_ Y1311, etc. 3

NETWORK

2

DATA LINK

any network “packetized” data service ETHERNET MPLS

1

PHYSICAL

SDH

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Table 34. MPLS layer stack over SDH 3

NETWORK

any network “packetized” data service

2

DATA LINK

MPLS

1

PHYSICAL

ETHERNET

Table 35. MPLS layer stack over ETHERNET

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3.6 ISA – PR_EA (MPLS) sub–system

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The Alcatel MPLS system can manage packets data streams transported over “local” Ethernet FE or GE (Fast Ethernet, Gigabit Ethernet) and “remotized” ethernet over GFP/SDH; the packets are identified and classified with a first label (by inspecting the ethernet frame header), marked again by the label switching router with a second label, and then sent into the MPLS network, aggregated and encapsulated into PPP/HDLC/SDH frames. If coming from the MPLS network, the packets can be terminated towards the ethernet ports or routed towards other routers, if possible they are also aggregated into a common FEC; the routing operation is performed by the swapping of the top label. The protocol stacking is illustrated in the figure below (Figure 105. ). The MPLS framing among the various protocols is illustrated in Figure 106. A generic example of MPLS tunnelling is illustrated in Figure 113. page 229. A generic scheme of MPLS classification and aggregation is illustrated in Figure 114. page 230. The label and frames formats are illustrated in Figure 107. , Figure 108. , Figure 109. , Figure 110. ; the GFP frame is reported in the “Ethernet” description, para. 3.8.2.1, page 255.

3

3

any

2

Eth 1 FE or GE local Ethernet

Eth MPLS

2

FE,GE Proc.

3

any 3

2

C&I

Eth MPLS

2

MPLS PPP HDLC

MPLS 1

3

any

3

Eth GFP

2 1

remote Ethernet

2

any

MPLS ROUTING

any Eth MPLS

any

SDH/HDLC Proc.

SDH MPLS over SDH

Eth MPLS

SDH SDH/GFP Proc.

C&I

over SDH

CLASSIFICATION & IDENTIFICATION

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Figure 105. MPLS subsystem, protocol stacking

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PRE FS DA SA DFL

Ethernet Payload

FCS

DA SA DFL

Ethernet Payload

FCS

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Ethernet

Ethernet Packet

GFP

Ethernet Packet

GFP Header

Ethernet Packet

MPLS

Label Label 1 2

Ethernet Packet

Labelled Packet (MPLS)

PPP

HDLC

PPP PAD

MPLS packet

PPP Header

Flag Addr Control

PPP frame

FCS

HDLC frame SDH VC4 or VC3 or VC12 frame

POH

SDH payload

GFP frame

1AA 00014 0004 (9007) A4 – ALICE 04.10

POH

SDH VC4 or VC3 or VC12 frame

SDH payload

Figure 106. Framing for MPLS

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A generic MPLS label is illustrated below (refer to RFC 3032):

0 0 1 2

3 4 5 6

1 7 8 9 0 1 2

3 4 5 6

2 7 8 9 0 1 2

Label

Label:

Label Value (20 bits)

Exp:

Experimental (3 bits)

S:

Bottom of Stack (1 bit)

TTL:

Time To Live (8 bits)

Exp

3 4 5 6

3 7 8 9 0 1

S

TTL

Figure 107. MPLS label format

Protocol 8/16 bits

Information a*

Padding b*

a* + b* 0, EIR = 0, CoS = Medium • voice – CIR > 0, EIR = 0, CoS = High • broadcast TV – CIR > 0, EIR = 0, CoS = Low • residential internet access – CIR > 0, EIR = 0, CoS = Low • VPN for multiple applications – CIR > 0, EIR = 0, CoS = High/Medium/Low (derived from priority indication within the packet) In addition to the standard settind ISA–PR implements a proprietary bunding feature. The use of bunding is optional and does not contradict any of the MEF applications. It improves the performance of the per EVC policing by protecting a higher CoS traffic from undesirable effects of bursts of lower CoS traffic. This allows the customer to better utilise his bandwith by using a single service for all of his VPN applications. Policing attributes the granularity • CIR, EIR – 100 Kbps (or 1% of bandwidth, wichever is larger) • CBS, EBS – 1 Kbyte Policed packets are passed to the Buffer Manager which places them at appropriate queue/s.

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Buffer Management maintains packet memory, structured into multiple queues each queue serving a particular destination and CoS; i.e. three queues per destination. It also maintains various queue fill level thresholds to maintain priorization between CoS, prevent any queue from monopolizing the memory and provide triggers for load balancing. Load balancing packets are issued after a fixed number of yellow bytes is delivered from a channel. Upon reaching the first stress level, indicated by queue depth increasing beyond a threshold, buffer management issues a stress signal to local policers that is increasing in queue depth. Upon reaching a higher threshold it starts discarding the yellow packets. Upon reaching a yet higher threshold, which indicates maximum queue occupancy, it discards all arriving packets. Shaping Shaping controls the rate and the order at which packets are injected into the ring. The total Bandwidth per destination may be determined to either wide NMS as fixed number or dynamically changed by the load balancing mechanism. Selection between the two modes is performed by NMS. The bandwidth per destination is shared between the various queues in decreasing CoS order; i.e. High packets are forwarded first, Medium next and Low last. ADM

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The ADM function maps packets into the synchronous SDH payload. The applicable payloads are VC4–4v, VC4–5v, VC4–6v, VC4–7v, VC4–8v.

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Buffer Management

Ingress summary

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Figure 120. summarises ingress processing.

MEF policer CIR

EIR

Discard Packets output to ring: Packets are output onto the ring into the appropriate Virtual trunk (VT) for the CoS & Destination node/port

Packet analysis(A): Classified by service Based on header and port info

Packet analysis(B): Policing: Packets are put into queues MEF policing with CIR+ based on header priority and EIR SLS. Either per UNI destination port Per EVC Per EVC.CoS Destination A NN proprietary bundling High

SDH out

Queues

Medium

Packet Labeling Martini Labels are stripped, and internal MPLS Labels are added

Low Scheduler

Destination B High Medium Low Aggregate Shapers

Stress

SDH in

Queue filling feedback Similar to R.E.D

Access card NP

Port card Policer

BM

ADM

Figure 120. ISA–PR Traffic Management Overview

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Every packet is assigned an identifier detailing customer, SLA and traffic flow. i.e. where is the packet to be delivered, which priority is the packet given internally. These classified or tagged packets are then managed at wire speed, creating a breakthrough in service agility. Service providers can now market and deliver differentiated services – and importantly, more than one data service per customer interface – to hundreds of customers over a single, shared fibre or wavelength of capacity. ISA–PR functions as a Layer 2 device, so the Ethernet connectivity it provides is transparent to the customer. Therefore any L2 protocol used by the customer, such as spanning tree, can be delivered unaffected, unless explicitly provisioned to filter them out. Sophisticated traffic–engineering algorithms ensure that, on a per–flow, per–node and per–ring basis, all SLAs configured on all network elements are met.

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Egress processing is much simpler than Ingress processing. It involves no extensive classification and no policing. ADM The ADM function selectively drops packets into the node, based on their MPLS labels and identifiers their EVC and CoS. Per packet decision by ADM may result in either: – drop – drop and forward – forward – discard. Buffer Management Buffer management maintains packet memory, structured into queues, each queue serving a 1Gbps interface between Port and Access card and CoS; i.e. three queues per every one of the 4 interfaces. It also maintains various queue fill level thresholds to maintain prioritisation between CoS, prevent any queue from monopolizing the memory and provide triggers for load balancing. Upon reaching the load balancing threshold buffer management issues a flow control packet. Upon reaching a higher threshold it starts discarding the yellow packets. Upon reaching a yet higher threshold, which indicates maximum queue occupancy it discards all arriving packets. Buffer Management forwards packets to the Access cards as long as the interface between the cards is free to do so; i.e. without any shaping. Editing Egress Editing may be provisioned to append an MPLS header, if any of the Ethernet ports on that Access card is configured as a Martini interface. Editing is applied by the Network Processor. L2 Switching Egress L2 Switching comprises MAC based filtering and MAC learning. L2 Switching is applied by the Network Processor. Egress Buffering

1AA 00014 0004 (9007) A4 – ALICE 04.10

Egress Buffer Management maintains packet memory, structured into queues, each queue serving an Ethernet port and CoS; i.e. three queues per every one of the 16 Fast Ethernet in ISA–16FEA card or 2 Gigabit Ethernet in ISA–2GBA card. Egress Buffer Management forwards packets across the Ethernet ports as long as the interface between the ports are available; no failure and no flow control applied by the connected device. Egress Buffering is applied by the Network Processor.

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3.7.2.2 Egress processing

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Load Balancing In order to prevent congestion in the ring each ISA–PR monitors the traffic, identifies congestion conditions, communicates its status to other ISA–PR and responds to congestion reports by other ISA–PR. This set of functions is collectively referred to as ”Load Balancing”. Both ADM and Buffer Manager participate in Load Balancing. Communicating the congestion status is done using OAM–like packets, called LB–OAM. Each ISA–PR generates LB–OAM packets that traverse all the paths, originating at that ISA–PR. While traversing the ring LB–OAM packets are stamped with the congestion levels of the bottlenecks encountered in the path. At the end of the path the packets are sent back to their source ISA–PR. In response to the congestion in the path, the originating ISA–PR adjusts the channel BW in order to reduce the load of traffic in congested bottlenecks. Adjusting the channel BW takes into account the relative SLA satisfaction of the affected services and hence achieves fairness. Channels Channels are virtual pipes that aggregate traffic in the ring. Each channel aggregates traffic that originates from a single ISA–PR and goes to one or more destinations. The total BW of the services in a channel is limited by the channel BW. The originating ISA–PR controls the BW of each channel. Traffic management uses channels to adjust ring traffic so the total forwarded traffic does not exceed the available resources in any point in the ring. In case of congestion the BW of channels that contribute to the congestion will be reduced and the congestion will be relieved. Reducing the bandwidth of a channel will cause the originating network element to forward less traffic through the services of that channel. The reduction in bandwidth will take into consideration the SLA of services in the channel and maintain fairness between customers. Traffic in the physical network is divided into channels.

Each channel carries traffic of multiple services.

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Figure 121. Channels

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Each ISA–PR monitors the traffic traversing it on a number of ”bottlenecks”. Bottlenecks are convergence points in the ring that might be congested when traffic load increases. There are both Ingress and Egress bottlenecks.

Figure 122. Bottlenecks Congestion Indications Whenever a bottleneck is congested the node will notify the other nodes in the ring of the congestion by sending a ”congestion indication”. The congestion indication reports the location of the congestion. In reaction, each node reduces the allocated bandwidth to the channels that send traffic toward the congested bottleneck, thereby relieving the congestion. In case of severe congestion, the congested network element will send repeating congestion indications causing larger bandwidth reduction in the relevant channels. Fairness

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Even in times of congestion on the ring, the ISA–PR assures that – CIR is not affected – EIR is affected in a fair manner Reduction will be relative to the amount of BW the customer bought. Maintaining fairness will be done by balancing the level of ”satisfaction” of channels in the network. The level of satisfaction of a channel represents the difference between the amount of forwarded EIR traffic and the amount of conforming EIR traffic, submitted by the customers. ”Non–conforming” traffic; i.e. traffic exceeding SLA BW, is marked Red by the Policer and not taken into consideration for ”satisfaction” purposes. The load balancing mechanism increases the BW of channels, which are more affected by the traffic load while reducing BW of other channels, which are more ”satisfied”. The bandwidth of each channel will be reduced whenever it gets a congestion indication. If a congestion indication is not received during a period of time the channel bandwidth will be increased.

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Bottlenecks

3.7.2.3 Protection sub–system

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The following protection mechanisms are provided: –

native packet ring protection, refer to point [1] on page 249

–

Dual Attach, refer to point [2] on page 250.

–

Customer Edge (CE) Dual Homing, refer to point [3] on page 251.

[1]

Packet ring protection

The packet protection is provided by the MPLS–based Resilient Packet Ring (RPR) technology, via “Wrapping” mechanism (see Figure 123. on page 249). RPR is currently being standardized by the IEEE 802.17 Working Group and specifies a technology for packet–based transport in ring topologies defining special functions that offer fast fault location and trigger fast switchover at packet level. RPR is used to optimize and manage the portion of bandwidth dedicated to packet traffic in SDH networks. An RPR topology consists of two counter rotating fiber rings (or portion of SDH fiber rings bandwidth) in which multiple nodes share the whole bandwidth (see Figure 123. on page 249) Negotiation for bandwidth occurs among the nodes through specific fairness mechanism that guarantees fair bandwidth allocation for customer traffic per each node. Nodes can send packets to other nodes either by utilizing unicast (point–to–point) or multicast (multipoint) destinations, which enables multipoint Ethernet VPN and Ethernet aggregation services be implemented over RPR. When sending a packet, the node determines which ring direction to use, so the spans in the opposite direction remains free for other customer traffic sent by other nodes. A packet traveling on the ring is stripped by the destination node. This means that the packet does not use all the ring bandwidth but only the span that it requires to go from source to destination. This features is called “spatial reuse” as the bandwidth of the other span of the ring can be used by other paying traffic. RPR protection protocol provides sub–50msec resilience for traffic in case of fiber or node failure. Specific control packets are exchanged among the nodes to keep the ring constantly monitored. “Wrapping” mechanisms is provided for packet protection switch accomplished by merging the frames destined at the failed segment, into payload destined at the opposite direction by node adjacent to the failed segment. Additionally, RPR provides ring–wide QoS assurance mechanisms and three different CoS.

1AA 00014 0004 (9007) A4 – ALICE 04.10

1660SM

1660SM

Figure 123. RPR protection mechanism

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The Martini MPLS encapsulation is used to provide an end–to–end reliable support to Ethernet networking. It specifies a technique by which Layer 2 Protocol Data Units (PDUs) such as Ethernet may be tunneled through an MPLS enabled network. End–to–end Ethernet connectivity relations are transported over specific MPLS Label Switched Paths (LSPs) that are switched through the network. This allows for the provisioning of multiple, segregated customer networks over the Service Provider infrastructure, creating a Virtual Private Network (VPN) for each customer. 1660SM

1660SM

Figure 124. Packet protection (and QoS assurance) in multiring network : MPLS over RPR [2]

Dual Attach protection

Refer to Figure 124. and Figure 21. on page 75.

1AA 00014 0004 (9007) A4 – ALICE 04.10

The Dual Attach protection is a redundant connection to another ring or hub providing aggregate protection. It offers a mechanism that expands the protection capabilities of RPR to multi–ring architectures enabling network–wide resilience. Two RPR rings are interconnected in two points (nodes) so that networking is resilient to both node and link failures. In addition, dual attach allows for multiple node or link failures across multiple RPR structures. Considering Figure 124. , if either Node A fails or the link between Node A and the other ring fails, Node B can forward packets to the other ring through its attachment keeping QoS and SLA levels unaltered.

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MPLS–based RPR technology. To extend the packet protection (and end–to–end QoS...) to a multiring network, it is necessary to put MPLS as the “upper layer” on top of RPR. MPLS provides the technology to handle traffic in multiring networks thus ensuring end–to–end resilience and QoS for carrier–class Ethernet services across such a network. In Figure 124. each ring is responsible of providing RPR protection while the MPLS upper layer working on top of RPR guarantees end–to–end resilience and networking. This is achieved by using two techniques: – Martini MPLS encapsulation – Dual attach protection (described in the following paragraph [2])

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[3]

Customer Edge (CE) Dual Homing protection

The CE dual homing consists in a CE connection to two nodes in a ring for protection of the access interfaces. This protection is described in the following Figure 125. and in Figure 21. on page 75

1660SM 1660SM

1660SM 1660SM

1660SM 1660SM 1660SM

Figure 125. Customer Edge Dual Homing

1AA 00014 0004 (9007) A4 – ALICE 04.10

Alcatel ISA Card Interworking ISA–PR supports interworking with other OMSN’s portfolio’s ISA card types as for the following Figure 126.

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3.7.2.4 Alcatel ISA Card Interworking

Core MPLS Switch/Router

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Core Router

FX, FE FX, FE GbE

GbE

B ayN etw orks

B ayN etw orks

ISA PR

B ayN etw orks

ISA PR

1660SM SDH Ring

EMX3660 Overlay Packet Ring VC–4–Xv B ayN etw orks

B ayN etw orks

B ayN etw orks

ISA PR

ISA PR

ISA PR

CO

ISA PR

GbE

GbE GbE

FE ISA PR_EA

B ayN etw orks

ISA PR_EA

1650

ISA PR_EABayNetworks

B ayN etw o rks

STM–n

1650 Ring 1640

16x0 B ayN etw o rks

B ayN etw o rks

B ayN etw o rks

FE/GbE B ayN etw o rks

1640 ISA Eth

ISA Eth

FE

FE

ISA Eth

FE

B ayN etw o rks

B ayN etw o rks

B ayN etw orks

ISA GbE

GbE

ISA Eth

ISA Eth

ISA GbE

FE

GbE

CE FE

Figure 126. Relationship with other ISA Cards Inter–working with the following ISA cards is supported: – – –

ISA Eth ISA GbE ISA PR_EA

The ISA–PR is designed to be deployed in conjunction with ISA Eth, ISA GbE and ISA PR_EA cards deployed in OMSN node types. Customer deployment will often involve the use of some or all of these ISA card types in an ”overlay” network, which may consist of point–to–point links, aggregation functions and Packet Rings. The ISA–PR_EA card is used to aggregate different ETH traffic flow, while guaranteeing per flow QoS, coming from ISA–Eth or ISA–Gbe into GBE interface that can be connected to the ISA–PR. Customer segregation and traffic management is provided by MPLS traffic segregation on the link between the two ISA–PR and ISA–PR_EA cards.

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The ISA PR_EA cards attaching to the ISA PR may utilize Dual Attach for protection.

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3.8 ISA – ETHERNET management sub–system 3.8.1 Generalities 3.8.1.1 LAN to LAN transport service OMSNs can be equipped with Ethernet units to allow LAN to LAN service as a point to point connection between two routers or switches through a SDH network, as depicted Figure 137. on page 266. The board acts as a gateway towards the SDH network. In order to guarantee the end to end transparency each Ethernet stream/interface of the board is mapped in a specific SDH VC (by means of “GFP” encapsulation algorithms, according to ITU–T G.7041 Rec.) performing a one to one Ethernet traffic mapping into the SDH network. A transport network based on OMSNs equipment provides flexible link service among remote LANs carrying Ethernet traffic, as shown on Figure 127.

OMSN

STM–N

STM–N

OMSN

STM–N STM–N

OMSN Ethernet LAN A over SDH

OMSN

STM–N

OMSN Ethernet over SDH

STM–N

STM–N

LAN B

STM–N

STM–N

OMSN

STM–N

OMSN

1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 127. Example of an Ethernet stream transport through a SDH network –

Transparency The Ethernet frames are forwarded to the output port with no protocol termination. This cause no impact on service management architecture due to transport network insertion

–

Low latency The transport network provides a very low end–to–end delay; the removal of store&forward need in the intermediate nodes using continuous data flow is another consequence of transparency

–

High availability The LAN–to–LAN service makes use of the same resources and infrastructures of the other transported services (ATM, MPLS, PDH and SDH streams...); so availability is very high

–

High quality All the features of the transport network, like very low BER, synchronization, alarms management, performance monitoring, protection mechanisms, ... are used providing so high quality service.

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The functional block diagram of a LAN to LAN service is shown in Figure 128. The client sink termination function adapts the client interface; all the payload frames received are stored into input buffer queue. The source SDH adaptation function draws the frames from the memory emptying the cluster and making it available again; then maps the frame into SDH Virtual Container applying the GFP encapsulation procedure. SDH paths are considered as traffic pipes carrying a continuous data flow. At the output port the dual operation is performed: the output buffer queue is written with payload frames received from SDH line and then the client source termination draws from memory and forwards these frames to the client according to the interface characteristics. = 80 frames Input buffer size Output buffer size = 80 frames, without concatenation 528 frames, VC–3 concatenation (N x VC–3) 2064 frames, VC–12 concatenation (N x VC–12)

Port A

Client sink

Port B

SDH source input buffer

Client A

Client source

SDH pipe – A to B

SDH sink output buffer

Bidir. SDH pipe (N x path)

SDH sink

SDH pipe – B to A

Client source

SDH source

output buffer

Client B

Client sink input buffer

Figure 128. LAN to LAN service block diagram

1AA 00014 0004 (9007) A4 – ALICE 04.10

Three types of Ethernet interfaces are provided – 10 Mbit/s – Ethernet – 100 Mbit/s – Fast Ethernet – 1000 Mbit/s – Giga Ethernet

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3.8.1.2 LAN to LAN functional description

1AA 00014 0004 (9007) A4 – ALICE 04.10

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Different Ethernet interfaces types can be used at the termination ends: e.g. an Ethernet client interface in one side and a Fast Ethernet one in the other side. A SDH pipe can be configured as – a single SDH path or – a concatenation of paths: • N x VC–12 • N x VC–3 • N x VC–4 Depending on client types and SDH pipe a bandwidth limit can occur. A flow control mechanism is used to adapt the client rate to the transport pipe. 3.8.2 Main features description 3.8.2.1 Encapsulation All the types of client – Ethernet – Fast Ethernet – GigaBit Ethernet are mapped into SDH Virtual Containers using encapsulation algorithms for variable length packets, according to ITU–T G.7041 Recommendation “Generic framing procedure (GFP)”. GFP has been adopted to solve the incompatibility between the Ethernet traffic, based on discontinuous data, and the SDH traffic needing a continuous data stream. GFP is able to map length–variable data. The Ethernet frames are GFP encapsulated, to be then mapped into SDH Virtual Containers. In this application the client signals are Ethernet MAC (PDU oriented) type. The GFP encapsulation is shown on Figure 130. on page 258. For each pipe three different GFP frame formats can be configured, as shown on Figure 129. on page 256: – GFP without FCS – GFP with FCS – Extended GFP.

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PLI

PLI

PLI

PLI

cHEC

cHEC

cHEC

cHEC

cHEC

PTI+PFI+EXI

PTI+PFI+EXI

TYPE

PLI cHEC

UPI

Core Header

UPI

Path Status

tHEC

Circuit Status

tHEC

tHEC

Circuit Status

Ethernet data

Ethernet data

Link Status

Ethernet data

Ethernet data

Link Status

Ethernet data

pcHEC

tHEC

Ethernet data

Payload Header

Client Payload Field

Core Header

Payload Header

pcHEC Ethernet data Ethernet data Ethernet data

Ethernet data

Client Payload Field

Ethernet data pFCS FCS Field

pFCS pFCS Ethernet data

pFCS

1AA 00014 0004 (9007) A4 – ALICE 04.10

GFP without FCS

GFP with FCS

Extended GFP

Figure 129. GFP frame format

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PLI

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According to the type, the GFP frame format consists of a Core Header, a Payload Header, a Client Payload field and FCS field. The Core Header, made up of 4 octets, supports frame delineation procedures and essential data link operations functions independent of the higher layer PDUs (Protocol Data Unit). The GFP Core Header consists of the following fields – PLI: it is the PDU Length Indicator field 16 bits length, containing a binary number representing the number of octets in the GFP Payload Area. Zero length means no payload area, i.e. idle frame; this is intended for use as a filler frame for the adaptation process – cHEC: it is the Core Header Error Control field 16 bits length, containing a CRC–16 generated sequence that protects the integrity of the contents of the Core Header by enabling both single–bit error correction and multi–bit error detection. The Payload Header, is a variable–length area, made up of – 4 octets in GFP without FCS and GFP with FCS frame format – 8 octets in Extended GFP frame format, provides payload information like GFP type; when Extended GFP is used this area provides also information used in Packet Concatenation. According to the frame format, in the following are described the various types of fields: –

GFP without FCS and GFP with FCS frame format • the first two octets constitute the GFP type field of the Payload Header, indicating the content and format of the GFP Payload field. The Type field distinguishes between services in a multi–service environment. This field consists of – PTI, Payload Type Identifier, a 3–bit field • PTI=0 for GFP user frame conveying client data • PTI=1 for GFP user frame conveying far–end Client Signal Fail indications – PFI, Payload FCS Indicator, 1–bit field • PFI=0, Payload FCS is present • PFI=1, Payload FCS is absent – EXI, Extension Header Identifier, 4–bit field – UPI, Used Payload Identifier, 8–bit field • tHEC: the 3rd and 4th octets constitute the Type Header Error Control field containing a CRC–16 generated sequence that protects the integrity of the contents of the Type Field by bit error detection.

–

Extended GFP • the first octet is made up of the TYPE fields that provides format and frame type • from 2nd to 6th octet the information about Path Status, Circuit Status and Link Status are given • in the last two octets, the FCS type information are given, in pcFCS fields.

The Payload Field contains the Ethernet frames; this variable–length area may include from 64 to 1574 bytes. The client user/control PDU is always transferred into the GFP Payload field as an octet–aligned packet stream.

1AA 00014 0004 (9007) A4 – ALICE 04.10

The payload Frame Check Sequence (pFCS) is an optional field, 4–bytes long. If selected, it’s a frame check sequence containing a CRC–32 sequence used to detect any packet corruption inside the transport network.

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Ethernet MAC frame Octets

GFP frame

7

Preamble

1

Start of frame delimiter

6

Destination Address (DA)

6

Source Address (SA)

2

Length/Type MAC client data

4 4 8

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Octets Core Header Payload Header

Client Payload Field

Pad Frame check sequence (FCS)

4

Bit # 1 2 3 4 5 6 7 8

1 2 3 4 5 6 7 8

1AA 00014 0004 (9007) A4 – ALICE 04.10

Ethernet MAC Frame fields: –

Preamble: the preamble is a 7–octet field that is used to allow the PLS (Physical Signaling) circuitry to reach its steady–state synchronization with the received frame’s timing.

–

Start of Frame Delimiter: the SFD field is the sequence 10101011. It immediately follows the preamble pattern and indicates the start of a frame.

–

Destination Address (DA): the Destination Address field specifies the station(s) for which the frame is intended.

–

Source Address (SA): the Source Address field specifies the station sending the frame.

–

Length/Type: this two–octet field takes one of two meanings, depending on its numeric value: – If the value of this field is less than or equal to the value of max Valid Frame, then the Length/Type field indicates the number of MAC client data octets contained in the subsequent data field of the frame (Length interpretation). – If the value of this field is greater than or equal to 1536 decimal (equal to 0600 hexadecimal), then the Length/Type field indicates the nature of the MAC client protocol (Type interpretation). The Length and Type interpretations of this field are mutually exclusive.

–

MAC client data and PAD: The data field contains a sequence of n octets; full data transparency is provided. If the length of the data field is less than the minimum required for proper operation of the protocol, a PAD field (a sequence of octets) will be added at the end of the data field but prior to the FCS field.

–

Frame check sequence (FCS): a cyclic redundancy check (CRC) is used by the transmit and receive algorithms tp generate a CRC value for the FCS field. The frame check sequence (FCS) field contains a 4–octet (32–bit) cyclic redundancy check (CRC) value. This value is computed as a function of the contents of the source address, destination address, length, LLC data and Pad (that are all the fields except the preamble, SFD, FCS and extension). Figure 130. GFP encapsulation of the MAC frames

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3.8.2.2 Flow control

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To avoid buffer saturation problems at the termination end, flow management is very important. When an excessive traffic is received, a control mechanism can be used to slow down the transmitter avoiding a packets loss. Three different control options are used: – input control – output control – external control. In the following the relative actions are described. As you can see from Figure 131. on page 259, the input control is performed at the input port; it is always enabled regardless the GFP type. When the input buffer of Port A crosses a fixed threshold of 48 frames, a pause request is sent back to the transmitter; no input frame is thrown away till 80 frames filling occurrence. The pause request message is defined in IEEE 802.3x; the transmitter is asked to be paused for 32 quanta. The transmitter will be re–qualified (pause request stopped) when the input buffer of Port A crosses the 44 frames threshold.

Port A

Client A Client sink

SDH source

Client source

pause request

input buffer

100 Mbps

+

Port B

SDH sink

3 x VC–12

3 x VC–12

SDH source

output buffer

control+ data flow

Client source output buffer

Bidir. SDH pipe (N x path)

SDH sink

Client B

100 Mbps

Client sink input buffer

1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 131. Flow control mechanism: input control

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If the received client throughput is higher than SDH pipe capacity, idle frames are sent to fill the SDH virtual container.

Port A

SDH source

input buffer

100 Mbps

SDH sink

1 x VC–3

output buffer

Bidir. SDH pipe control+ (N x path) data flow

+ Client source

SDH sink

1 x VC–3

Client B

Client source

SDH source

output buffer

pause request

Client sink

Port B

pause request

Client A

10 Mbps

Client sink

input buffer

Figure 132. Flow control mechanism: output control See Figure 133. on page 261. The external control is performed at the output port. When a pause activity is requested from the external client, the output transmitter is stopped for the relative period. The external control is planned for future releases.

1AA 00014 0004 (9007) A4 – ALICE 04.10

This fact could cause first the queue filling of the output buffer of Port B activating the output control previously described, and then the queue filling of the input buffer of Port A activating the input control.

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As you can see from Figure 132. on page 260, the output control is performed at the output port only when Extended GFP is used. When the output buffer of Port B crosses a fixed threshold of – 272 frames, when VC–3 concatenation is used (N x VC–3) – 1040 frames, when VC–12 concatenation is used (N x VC–12) a flow control action is performed to reduce the traffic received from the SDH network: a pause request is sent back to the SDH source of Port B and then, by means of the SDH pipe, to the SDH source of Port A. This fact could cause the queue filling of the input buffer of the Port A: in this case the input control previously described is applied. The transmitter will be re–qualified (pause request stopped) when the input buffer of Port B crosses the – 240 frames threshold, when VC–3 concatenation is used (N x VC–3) – 1008 frames threshold, when VC–12 concatenation is used (N x VC–12)

Client sink

100 Mbps

Port B

SDH source

Bidir. SDH pipe (N x path)

input buffer

Client source

SDH sink

1 x VC–3

SDH sink

1 x VC–3

Client B

Client source output buffer

SDH source

output buffer

Client sink

10/100 Mbps

Client sink input buffer

Client source output buffer pause request

Port A

pause request

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Client A

Client source

+

Client sink

input buffer

control+ data flow

Figure 133. Flow control mechanism: External control 3.8.2.3 Concatenation Two different VC–n concatenation mechanisms are employed in OMSN Lan to Lan transport service: –

Virtual Concatenation for VC–4 concatenation in Gigabit Ethernet clients

–

Packet Concatenation for VC–12 and VC–3 concatenation in Ethernet/Fast Ethernet clients

In both cases differential delay of the network is compensated at path Termination Sink. When Virtual Concatenation is used each Ethernet frame is sent by dispatching one byte per VC in rotation mode. Thus the message to be transmitted by means of the SDH network is splitted byte per byte among the paths making up the Pipe. The Virtual Concatenation Termination feature is according to ITU–T G.707 and G.783 Recs.

Transmission Network 33 2 11 VC–4

Client A

Client B

33 2 21 VC–4 Message

1AA 00014 0004 (9007) A4 – ALICE 04.10

3

Message 2

Message

Message

Message

Message

1

3

2

1

33 2 21 VC–4 Figure 134. Messages dispatching via Virtual Concatenation

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Transmission Network Message 1 VC–12 or VC–3

Client A

Client B

Message 2 VC–12 or VC–3 Message

Message

3

Message

Message

Message

Message

1

3

2

1

2

Message 3 VC–12 or VC–3 Figure 135. Messages dispatching via Packet Concatenation

3.8.3 Technical specification Latency data [1]

GigaBit Ethernet board latency •

[2]

1 x VC–4

1AA 00014 0004 (9007) A4 – ALICE 04.10

64 bytes

=

205 µs

–

512 bytes

=

201 µs

–

1518 bytes

=

193 µs

Fast Ethernet board latency •

ED

–

1 x VC–4 –

64 bytes

=

101 µs

–

512 bytes

=

125 µs

–

1518 bytes

=

178 µs

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When the Packet Concatenation is used, each Ethernet frame is not shared among different paths (VCs) of a certain pipe as in Virtual Concatenation mode; but each message is dispatched on a single path/VC of a certain pipe. When a failure occurs inside the network, unavailable paths are not used and traffic is kept by using the remaining available paths. The bandwidth can be increased/decreased with no impact on traffic (hitless link adjustment). Obviously the messages can be sent through different ways and have to be realigned in reception to restore the proper sequence.

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•

1 x VC–3

•

–

64 bytes

=

72 µs

–

512 bytes

=

147 µs

–

1518 bytes

=

317 µs

1 x VC–12

•

–

64 bytes

=

517 µs

–

512 bytes

=

2108 µs

–

1518 bytes

=

5841 µs

2 x VC–3

•

–

64 bytes

=

277 µs

–

512 bytes

=

1462 µs

–

1518 bytes

=

3997 µs

8 x VC–12 –

64 bytes

=

657 µs

–

512 bytes

=

3452 µs

–

1518 bytes

=

5824 µs

Herebelow is given an example of the end to end delay; it is the sum of the following values: – physical line delay = 5 µs/Km – delay for each OMSN pass through = 5 10 µs/NE – latency. In a 1000 Km long network (5us/Km) and made up of 100 OMSNs equipment (5 10 µs/NE) using a Fast Ethernet board 8 x VC–12 / 512 bytes mapped, the end to end delay is equal to: (1000 Km x 5 µs) + (100 x 10 µs) + 3452 µs = 9452 µs

Allowed differential delay in case of concatenation

1AA 00014 0004 (9007) A4 – ALICE 04.10

VC–12 concatenation = 35 ms VC–3 concatenation =

3 ms

VC–4 concatenation =

256 ms

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3.8.4 Ethernet boards

–

10/100 Mb/s Ethernet unit (refer to paragraph 3.8.4.1 on page 264)

–

Gbit Ethernet (rate adaptive) unit (refer to paragraph 3.8.4.2 on page 268)

3.8.4.1 10/100 Mbit/s Ethernet unit 1660SM can also be equipped with 10/100 Mb/s Ethernet unit to allow LAN to LAN connections as a point to point connection between two routers or switches through an SDH network, as depicted Figure 137. on page 266. The board acts as a gateway towards the SDH network. If the customer has N sites to be interconnected, each Customer Box uses N–1 Point to Point Ethernet interfaces. The 10 or 100 Mb/s Ethernet traffic flows are mapped into VC12, VC3, or VC4 SDH transport structures, more precisely each Ethernet traffic interface of the board is mapped in a specific VCn (n=12, 3, 4), one to one Ethernet traffic mapping in the SDH network is performed, in order to guarantee the transparency end to end. In fact the Ethernet traffic is transported transparently in the SDH Network and it is terminated in the ADMs nodes where Ethernet traffic is dropped towards switches or routers without terminating the Ethernet frames. Mapping Ethernet flow inside VC–12/3/4 implies a compression of the total available bandwidth of the physical ethernet protocol. The IEEE802.3 is the standard algorithm used to adapt each customer flow inside an independent VC. Main functional aspects: Ethernet frames are mapped over a SDH VC using Generic Framing Procedure (GFP) encapsulation (see Figure 130. on page 258, and Recc. ITU–T G. 7041 for details). All the Ethernet access connectors are on the front panel of the unit. The architecture of the board is represented in Figure 136. on page 265. It is constituted by two cards, an access card that provides 14 Ethernet interfaces 10BaseT or 100BaseT, and a main board that provides 11 Ethernet interfaces 10BaseT or 100BaseT (the physical connector is always the same). The Ethernet traffic, opportunely mapped in the SDH transport structures, is then sent toward the SDH matrix through the back–Plane which has 4 STM–1 equivalent throughput. –

The board allows the mapping provisioning between the Ethernet (10 Mbit) or Fast Ethernet (100 Mbit) interfaces and the SDH VC as follows: •

Ethernet interface to a single: – –

•

Fast Ethernet interfaces to a single: – – –

1AA 00014 0004 (9007) A4 – ALICE 04.10

VC–12 or VC–3;

VC–12 or VC–3 VC–4

The back–Panel can support a maximum throughput of 622 Mb/s divided in 4 STM–1 flows. This constitutes a constraint respect to, for example, a configuration of the board with 25 Fast Ethernet interfaces mapped into 25 VC–4 (not possible because overcome the throughput).

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Two types of ETHERNET boards are foreseen for 1660SM :

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This is a typical problem of resource allocation where in one side there are up to 25 VC–n transport structures on the other side there are 4 tubes of STM–1 capacity, and the Operator has to find the mapping VCn–tube which best fits the available resources (622 Mbit/s). Summarizing, the operator first provisions the board defining the interface types, second he creates the VCx defining in the mapping between the interface and VC, since the relationship between interface and VC is one to one. More complex is the association between the VC–n and STM–1 back–Plane flow in order to best fit the resources. –

One Ethernet Interface is mapped in one SDH VC: no grooming of Ethernet frames in the SDH network

–

No Virtual Concatenation of Lower Order SDH VCs

–

Protection occurs at SDH level

1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 136. Board Ethernet 10/100: System architecture

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1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 137. Example of Ethernet service application

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1660SM with LAN to LAN board

Customer box: either LAN Switch or Router

Legenda: protection

SDH level

Ethernet frames are mapped in SDH VC–12. VC–3, VC–4

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The LAN to LAN board is present only at each terminating node

SDH RING NETWORK

mapped on a dedicated SDH VC

Site to Site Traffic is

1AA 00014 0004 (9007) A4 – ALICE 04.10

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Ethernet MAC Frame and GFP Frame fields: –

Preamble: the preamble is a 7–octet field that is used to allow the PLS (Physical Signaling) circuitry to reach its steady–state synchronization with the received frame’s timing.

–

Start of Frame Delimiter: the SFD field is the sequence 10101011. It immediately follows the preamble pattern and indicates the start of a frame.

–

Destination Address (DA): the Destination Address field specifies the station(s) for which the frame is intended.

–

Source Address (SA): the Source Address field specifies the station sending the frame.

–

Length/Type: this two–octet field takes one of two meanings, depending on its numeric value: – If the value of this field is less than or equal to the value of max Valid Frame, then the Length/Type field indicates the number of MAC client data octets contained in the subsequent data field of the frame (Length interpretation). – If the value of this field is greater than or equal to 1536 decimal (equal to 0600 hexadecimal), then the Length/Type field indicates the nature of the MAC client protocol (Type interpretation). The Length and Type interpretations of this field are mutually exclusive.

–

MAC client data and PAD: The data field contains a sequence of n octets; full data transparency is provided. If the length of the data field is less than the minimum required for proper operation of the protocol, a PAD field (a sequence of octets) will be added at the end of the data field but prior to the FCS field.

–

Frame check Sequence (FCS): a cyclic redundancy check (CRC) is used by the transmit and receive algorithms to generate a CRC value for the FCS field. The frame check sequence (FCS) field contains a 4–octet (32–bit) cyclic redundancy check (CRC) value. This value is computed as a function of the contents of the source address, destination address, length, LLC data and pad (that is, all fields except the preamble, SFD, FCS, and extension).

–

PLI: the two–octet PLI field contains a binary number representing the number of octets in the GFP Payload Area.

–

cHEC: the two–octet Core Header Error Control field contains a CRC–16 generated sequence that protects the integrity of the contents of the Core Header by enabling both single–bit error correction and multi–bit error detection.

–

Type: the GFP Type field is a mandatory 2–octet field of the Payload Header that indicates the content and format of the GFP Payload field

–

tHEC: The two–octet Type Header Error Control field contains a CRC–16 generated sequence that protects the integrity of the contents of the Type Field by enabling both single–bit error correction and multi–bit error detection.

–

GFP Extension Header: a 0–to–60 octets extended field that supports technology specific data link headers such as virtual link identifiers, source/destination addresses, port numbers, Class of Service, extended header error control, etc.

–

GFP Payload: The GFP Payload Area consists of all octets in the GFP frame after the GFP Core Header. This variable length area may include from 4 to 65 535 octets.

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The task of the Gigabit Ethernet functionality inside 1660SM is to carry Gigabit Ethernet packets over SDH Virtual Containers. It can be achieved in two different ways using : [1]

“Gigabit Access card” + “10/100 Mbit Ethernet board”: only two Gigabit interfaces are supported.

[2]

“Gigabit Ethernet rate adaptive board”: up to 4 Gigabit interfaces are supported.

[1] “Gigabit Access card” + “10/100 Mbit Ethernet board” This functionality is achieved using the 10/100 Mbit/s Ethernet board (Fast Ethernet) in conjunction with the Gigabit Ethernet Access Card as depicted in Figure 138. The function performed by the Access card is the interfacing on one side with the 1 Gigabit line and on the other side with the 10/100 Mbit/s Ethernet board ( where the signal is processed) through two 1.2 Gbit/s serial busses. Only two of the four interfaces ( pluggable module alternatively 1000 BASE–LX , 1000 BASE–SX, 1000 BASE–ZX) on the Gigabit Access card can be used . Gigabit interface are mapped through Generic Frame Protocol in one VC–4. with a compression ratio of 1:7; 802.3 Ethernet Flow Control is supported. The Ethernet traffic mapped in the SDH transport structures, is then sent toward the SDH matrix through the back–Plane which has 4 STM–1 equivalent throughput. In the configuration depicted in Figure 138. the 10/100 Mbit Ethernet interfaces present on the ETHERNET board can also be used taking into account the limit of the backplane.

Gigabit Eth

1

Gigabit Eth not used

Gigabit Access Card

not used 4

2 x 1.2 Gibit/s busses (through backplane)

10/100 Mbit Eth 1

10/100 Mbit Eth

10/100 ETHERNET BOARD

SDH

SDH

Matrix

Port

10/100 Mbit Eth 11

1AA 00014 0004 (9007) A4 – ALICE 04.10

Backplane : 622 Mbit/s throughput

Figure 138. Gigabit Ethernet System architecture: Gigabit access with Fast Ethernet board

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3.8.4.2 Gbit Ethernet (rate adaptive) unit

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[2] “Gigabit Ethernet rate adaptive board” The board, named Gb Ethernet with GFP mapping (mnemonic label GETH–MB), supports up to four Gb Ethernet interfaces in the main boards as depicted in the following Figure 139.

Ethernet Modules: 1000 Base LX 1000 Base SX 1000 Base ZX

Gbit ETH Main board

1660SM (Slot not Enhanced) Figure 139. Gigabit Ethernet System architecture:Gigabit Ethernet main board The Gb Ethernet interfaces (pluggable module) plugged in main board, are named Small Formfactor Pluggable (SFP) Transceivers and they can be considered as independent items hardware, in fact they have an own Remote Inventory. At the moment three types of Small Formfactor Pluggable Transceivers are provided: 1. Gb Ethernet Long Haul optical interface 1000BASE–LX 2. Gb Ethernet Short Haul optical interface 1000BASE–SX 3. Gb Ethernetl optical interface 1000BASE–ZX Each Gb Ethernet interface can be mapped through the Generic Frame Protocol (GFP) into 1, 2, 3, 4, 5, 6 or 7 VC4s. The mapping determines the rate of compression of the data throughput that can be respectively from 1:7 to 1:1. As for the Fast Ethernet this compression is allowed thanks to the flow control algorithm and considering the Ethernet traffic profile is typically bursty and the mean throughput is less than the peak rate. If the board is into an enhanced slot of 1660SM the back panel throughput is of 1.2 Gb/s instead of 622Mb/s, this determines that the maximum number of VC–4 mappable to the Gb/s Ethernet Interfaces is 8 instead of 4. This, for example, allows the transparent (without compression) transport of a Gb Ethernet interface into the SDH network.

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In order to provide for the Gb Ethernet a rate compression less than 1/7, more than one VC4 can be used to transport the Ethernet traffic, until a maximum of 7 VC4 where the transparent transport is obtained, in fact 7 times 150Mb/s (VC4 payload rate) is 1050Mb/s. Note, if no compression is configured (i.e. mapping on 7 VC4s), also another Gb/s interface can be mapped on a single VC4 (maximum compression level), in order to use all the backpanel bandwidth (8 VC–4 equivalent). The possibility of configuring more VC–4s, referring to the same client, is obtained by High Order virtual concatenation, where the level, the number of VC4s virtual concatenated, is provisioned by the operator.

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3.9.1 General Today’s evolving telecommunications services environment is highly competitive. There is a growing demand from Enterprise customers for simple, wide–area Broadband Data services which meet their needs for plentiful, competitively priced and flexible connectivity. Historically the success of Ethernet as the predominate technology within the Enterprise infrastructure, has been driven by very low capital and operational costs, the high degree of flexibility offered by the technology and importantly its easy of use – the plug and play model. Thus enterprises are now looking for data services outside of the building (in the WAN), which match the Ethernet technology used internally for LAN based services, without the need for expensive conversion equipment. These new services offered by the public network in the Wide Area are referred to a Metro Ethernet services. Similarly network operators and service providers are looking to new services like Metro Ethernet in order to develop new high–value revenue streams. An example of which is enhancing basic Ethernet connectivity this through the use of value added capabilities such as Layer 2 VPNs and multiple Qualities of Service (QoS) per connection. Deployment of Ethernet as a simplistic point–to–point technology will only result in canalization of existing Leased Line, Frame Relay and ATM based services. Only through the provision of Value–Added Services (VAS) of basic Ethernet connectivity to provide differentiation will Metro Ethernet services deliver incremental revenues and ultimately profitability. The ISA–ES series modules can deliver a full set of Ethernet services that are described in the next points [1] to [4]. [1]

Ethernet Private Line EPLine service connects two ports of a client between each other in a transparent fashion (using transparent mode). Traffic originating from one Customer Port is forwarded to the other one without any filtering and maximum level of security possible (physical segregation through different SDH infrastructure). The service emulates an Ethernet ”wire” which actual bandwidth is determined by the SLA and by network load. EPLine does not require MAC learning or MAC–based forwarding.

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Figure 140. Ethernet Private Line service

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3.9 ISA – ES (Ethernet Switch)

[2]

Ethernet Virtual Private Line

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EVP–Line service connects two ports of a client between each other (using bridging mode). Traffic originating from one Customer Port is classified and forwarded accordingly to the other end. The service emulates an Ethernet ”wire” which actual bandwidth is determined by the SLA and by network load. Thanks to the available Eth Multiplexing Function provided by the ISA–ES series modules, different Virtual Private Line services can be defined on the same UNI belonging to different applications and with different QoS SLA. EVPLine adopts MAC learning and MAC–based forwarding according to the need.

Figure 141. Ethernet Virtual Private Line service [3]

Ethernet Virtual LAN EVP–LAN service connects two or more ports of a client between each other (using bridging mode).

1AA 00014 0004 (9007) A4 – ALICE 04.10

Traffic originating from one Customer Port is classified and forwarded accordingly to the other end. The service emulates an Ethernet LAN which actual bandwidth is determined by the SLA and by network load. EVP–LAN adopts MAC learning and MAC–based forwarding with aging timeout.

Figure 142. Ethernet Virtual LAN

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Broadband access In this service, a number of customers are connected to a common Aggregate Port (e.g. typically connected to an ISP point of presence) Traffic is only delivered from individual Customer Ports to the Aggregate Port. Broadband Access can distinguish between various customers’ traffic at the Aggregate Port using VLAN tags. For each customer that is attached to the BA service it is possible to define a specific QoS SLA.

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Figure 143. Broadband Access service

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[4]

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3.9.2 ISA–ES series modules ISA–ES series modules provide ETH 10/100/1000 interfaces connectivity for LAN based clients premises inside the metro area. Beyond mapping ETH flows onto the SDH metro network by means of standard mechanisms (as specified in ITU G.7071, ITU G.7042 and ITU G.707) the ISA–ES series cards introduce wire speed classifying, policing and scheduling capability empowered by carrier class Ethernet switching engine. Per customer traffic flow management with low bandwidth granularity, segregation and QoS are just few of the value added arguments that these series of modules offer to the carrier operators at a competitive price. ISA–ES series is composed by: –

ISA–ES1 module

–

ISA–ES4 module

–

ISA–ES16 module

The ISA–ES series modules are modules that can be plugged according to the bandwidth and interface count demand inside the OMSN product family. Some of the resources available in the SDH infrastructure can be utilized in order to realize a converged multi service network into which different streams (e.g. TDM, ETH, ATM) can travel together in fat big pipes reducing capital and operational expenses for the operator. The major benefits that can be experienced utilizing an ISA–ES card in the SDH networks are: –

Interfaces cost reduction

–

Bandwidth policing according to clients needs and operator’s policy

The interface cost reduction is achieved thanks to the native ETH interfaces provided from the equipment that allow a cost effective replacement of useless and expensive up–link ports an external devices to connect to the public network (e.g. POS (Packet Over SDH/SONET) or FR uplinks). This leads to an infrastructure’s optimization for the operator and an induced cost reduction for the end–user devices. Furthermore bandwidth can be allocated and consequently controlled by the operator (through CIR, PIR and burstiness specification) to the end users in accordance with the real need, independently from the (physical) interface type used case by case. Operators are, as such, enabled to offer more services with enhanced flexibility and granularity, optimizing the bandwidth through the SDH network and opening new value added services from a common set of equipments being the technology TDM, ATM or ETH. As for the other ISA modules the ISA–ES series modules are connected to the main SDH matrix via specific back–panel wires.

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The capacity available from the card to the back panel gives the overall card trunking capacity that is available for traffic to flow from and to the SDH resources (e.g. SDH ports that carry ETH traffic into SDH VC).

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–

ISA–ES1

has 1 VC–4 of bandwidth available

–

ISA–ES4

has 4 VC–4 of bandwidth available

–

SA–ES16

has up to 16 VC–4 of bandwidth available (depending on the back panel capacity of the OMSN equipment)

Each of the ISA–ES series modules has specific ETH access ports and SDH trunks. –

ETH access ports may reside on the card itself of may be provided through other access cards.

–

SDH trunks are connections (SDH VCs) through the back panel to the SDH matrix and to SDH ports (STM–n).

ETH access ports on the ES series modules are: –

ISA–ES1 8FE

has 8 Ethernet ports (10/100 Base T) on the front of the card

–

ISA–ES1 8FX

has 8 Ethernet ports (100 Base FX) on the front of the card

–

ISA–ES4 8FE+1GE

has 8 Ethernet ports (10/100 Base T) and 1 GB Ethernet port (1000 Base SX/LX/ZX SFP) on the front of the card

–

ISA–ES16

is a port less card that can use specific access modules:

•

14 x FE access module: 14 x Fast Ethernet ports (10/100 Base T)

•

4 x GE access module:

4 x GB Ethernet ports with SFP plugs (Optical SX, LX, ZX)

Different ISA–ES series modules can be equipped in the same equipment. In this case it is also possible to realize back–to–back trunking between them via specific cross connections inside the SDH matrix (without the need of cabling). Traffic can flow between two or more cards and the amount of it can be specified according to the need (refer to Figure 144. on page 274). ISA–ES1

ISA–ES16

Access card

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SDH

Figure 144. ISA–ES access port

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The number to the right of the ISA–ES series card gives that amount in VC–4 equivalents. Hereafter are reported the available trunking capacity for each of the ISA_ES series cards:

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Figure 145. provides an high level overview of the traffic flow and processing in the ISA–ES series modules. The pipeline is composed of five main processing steps that are described in the next paragraphs.

De–mapping

Classifier

Policer

Forwarding

Scheduler

Mapping frame

Encap packet

Ports

PIR

Header De– assembly

=

CIR

Frame/packet

Bridge

mapping

+ reassembly

?

=

Figure 145. Traffic flow and processing in ISA–ES series [1]

Mapping

ISA–ES series modules are a family of Ethernet switching modules that provides native ETH access to an SDH infrastructure. Beyond just providing the physical ETH connectivity this family of modules has a full carrier class set of functionality for optimal and efficient handling of ETH traffic flows with QoS. An ISA–ES module receives and sends ETH traffic through two kinds of ports (refer to Figure 146. ): •

ETH physical interfaces (10/100 Base T , 100 BASE FX or 1000 Base SX/LX/ZX)

•

ETH over SDH (also referred as trunk ports)

These ports are connected to a carrier class Ethernet switching engine that processes each flow and takes care of the frame forwarding.

Eth I/O ETH ports

Eth Switch ETH Over SDH ports

Back Panel N x VC

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Figure 146. ISA–ES series ports

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•

IEEE 802.3 10BASE–T Ethernet (twisted–pair copper)

•

IEEE 802.3u 100BASE–TX Fast Ethernet (twisted–pair copper)

•

IEEE 802.1z (Gigabit Ethernet)

•

ANSI/IEEE 802.3 Auto–negotiation

•

IEEE 802.3x Flow Control

•

Data transfer rate from client equipment is limited in accordance with the specified traffic characteristics by the standard IEEE 802.3x flow control mechanism.

Flow control frames are used to prevent congestion of the network that may cause packet discarding at the egress of the network; the flow control mechanism stops the client source until the bandwidth allocated to the service is able to absorb the extra traffic. The result is that no packets are lost even in case of congestion. Flow control can be disabled according to the operator’s choice. The following standards apply to the ETH over SDH ports: •

ITU–T G.7041 GFP (Generic Framing Procedure)

•

ITU–T G.7042 LCAS (Link Connection Adjustment Scheme)

•

G.707 (SDH VC Virtual Concatenation at Low and High Order VC–12, VC–3 and VC–4 nv)

The Ethernet mapping scheme on the trunk ports adheres to the Generic Framing Procedure (ITU–T G. 7041). The Ethernet traffic, opportunely mapped in the SDH transport structures, is then sent by the trunk ports toward the SDH matrix from the back–plane and than to the corresponding SDH port. A trunk port is realized by a bundle of SDH VCs (VC–12, VC–3, VC–4) grouped together according to ITU–T G.707 (Virtual Conc) and ITU–T G.7042 (LCAS).

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The bandwidth of the trunk port in normal operational mode corresponds to the available bandwidth of the grouped VCs (e.g. 5xVC–12 equals 10 Mbps).

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The following standards apply to ETH physical ports:

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[2]

Traffic classification

ISA–ES series module can classify ETH traffic according to a wide set of standard specified criteria in order to provide a feature reach set of capability. Each classified traffic is referred in the next paragraphs as a classified flow. Classification criteria are the following: •

Port (Physical ETH or ETH over SDH)

•

IEEE 802.1Q (VLAN tagging)

•

IEEE 802.1p (ETH frame priority)

•

IEEE 802.3 Source/Destination MAC address (also according to IEEE 802.1ad)

The ISA–ES16 module expands the classification criteria by means of also supporting:

[3]

•

MPLS label (according to IETF Martini draft ETH over MPLS)

•

IP–TOS/DSCP fields

Policing and metering traffic with QoS

ISA–ES series modules allow service providers and carrier operators to specify per flow traffic QoS. ETH flows quality of service is enforced at the ingress of the network and inside the network by traffic conformance check made by the policing function. Policing is performed by means of a token bucket algorithm (dual rate on the ISA–ES16). Traffic QoS is specified by a set of parameters that control its max, mean rate and the relative burst window size in bytes. Policing parameters are specified per classified flow according to: CIR = committer information rate CBS = burst window size at the CIR PIR = excess information rate PBS = burst window size at the PIR

Burst window size (bytes) PBS Yellow EBS CBS EIR

Green

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Rate (bps) CIR

PIR

Figure 147. ISA–ES series traffic parameters

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a)

Guaranteed SLA Typically serves High priority traffic for mission critical applications that require loss–less delivery and minimal delay. Guaranteed SLA denotes BW (CIR = PIR > 0 in 100Kbps increments), which is always available regardless of any congestion conditions. Traffic delivered using Guaranteed BW, is policed to the CIR value with a burst window equal to the CBS. Guaranteed traffic is always composed of green packets and gets the highest priority in the processing chain.

b)

Regulated SLA Typically serves Medium priority traffic, which relies on transport layer protocol (per OSI stack) to recover from occasional loss and requires moderate delay; e.g. client–server applications. Regulated SLA denotes BW (PIR > CIR >0 in 100Kbps increments), which may be overbooked per network operator’s overbooking policy. The portion of bandwidth between CIR and PIR (aka EIR) may therefore be partially available under congestion conditions. This SLA is available only from the ISA–ES16 card. Regulated traffic is composed of green and yellow (Excess of CIR) packets.

c)

Best–Effort SLA Typically serves Low priority traffic, which relies on transport layer protocol (per OSI stack) to recover from loss and tolerates large delay; e.g. email and file transfer applications. Best Effort denotes BW (PIR > CIR = 0 in 100Kbps increments), which may or may not be available per network operator’s reservation for Best Effort policy. It may therefore be unavailable under congestion conditions. Regulated traffic is composed of yellow packets.

[4]

Congestion avoidance and Scheduling

Congestion avoidance techniques serve to anticipate and avoid network congestion conditions wile maximizing network utilization and good–put of the traffic flows. Congestion avoidance in ISA–ES series modules is based on a combination of Tail Dropping and WRED (Random Early Detection); these techniques are designed to provide preferential treatment for premium (CIR) class traffic under congestion situations while concurrently maximizing network throughput and capacity utilization and minimizing packet loss and delay.

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a)

Tail drop Tail drop treats all traffic equally and does not differentiate between classes of service. Queues fill during periods of congestion. When the output queue is full and tail drop is in effect, packets are dropped until the congestion is eliminated and the queue is no longer full.

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Through the specification of per flow traffic parameters the ISA–ES series modules can support the following SLAs:

b)

WRED

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The packet drop probability is based on the minimum threshold, maximum threshold, and mark probability denominator. When the average queue depth is above the minimum threshold, RED starts dropping packets. The rate of packet drop increases linearly as the average queue size increases until the average queue size reaches the maximum threshold. The mark probability denominator is the fraction of packets dropped when the average queue depth is at the maximum threshold. For example, if the denominator is 512, one out of every 512 packets is dropped when the average queue is at the maximum threshold. When the average queue size is above the maximum threshold, all packets are dropped. WRED is applied to yellow packets (Regulated (traffic beyond CIR) and Best Effort traffic quality). 1

Mark probability

0 Minimum threshold

Maximum threshold

Average queue size Figure 148. WRED Congestion avoidance mechanisms c)

Scheduling Scheduling of packets is performed on egress ports combining HOL (FIFO queue) and DRR (Deficit Round Robin) queues. HOL is used for Guaranteed traffic that gets highest priority.

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DRR is applied to Regulated and Best Effort traffic

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Switching and forwarding

ISA–ES series modules are based onto a carrier class Ethernet switching engine with auto learning bridges according to IEEE 802.1ad. This engine is either wire speed performing (all the functions are performed in hw) and highly flexible and configurable. On a per port basis it can be used in two modes: Transparent mode: the engine forwards all the traffic incoming from one port to another without inspection at the specified rate. Bridging mode with Stacked VLAN capability: a group of configured ports (ETH phy or ETH over SDH) are bridged together with MAC auto learning function according to IEEE 802.1ad. Transparent Mode

Back Panel N x VC–4

Eth I/O Bridge Mode

Figure 149. ISA–ES series operational modes a)

Multiple service per UNI port ISA–ES series modules allow multiple services to be deployed from a single UNI Ethernet port. Thanks to the Ethernet Multiplexing Function capability different traffics can coexist on the same port and be differentiated between them by the classification process thus get the desired QoS per flow. CUSTOMER SITE B

CUSTOMER SITE C ETH UNI

1AA 00014 0004 (9007) A4 – ALICE 04.10

CUSTOMER SITE A

EMF CUSTOMER SITE D

Figure 150. Ethernet Multiplexing Function

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[5]

b)

Multiple customers per NNI port

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The ISA–ES series modules allow a single NNI interface to be used for different customers while guaranteeing high levels of segregation, security and per customer QoS ability. ISA–ES series modules allow ETH frames to be tagged before being sent at the NNI interface. The modules have full VLAN tag agility in the sense that VLAN tags can be pushed, swapped and popped by the cards. The provider is able to add its own tags to the customer flows in order to segregate different customers inside common network resources. This taggagility functionality allow service providers to spread the capital expenditures among different customers and as a consequence to offer highly competitive price levels for the offered services to their customers.

CUSTOMER

CUSTOMER B

A

ETH UNI SVLAN 1 SVLAN 2 SVLAN 3

CUSTOMER C

Figure 151. Multiple customers on a single NNI c)

Customer traffic Isolation All ISA–ES series modules ports and services provide customer traffic isolation, such that traffic belonging to a given customer is isolated from traffic of any other customer using an identical or different service.

d)

Customer Address Space Isolation All ISA–ES series modules ports and services provide isolation customer of customer specific addresses, such that VLAN tags and MAC addresses belonging to a given customer are isolated from VLAN tags and MAC addresses of any other customer using an identical or different service.

e)

VLAN Uniqueness

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VLAN at the access interfaces need not be unique. Same value can be used at different ports of the same node or at different nodes. The guarantee of VLAN uniqueness within a port in the ISA PR EA comes from the encapsulation of the Ethernet frames in MPLS LSP’s that segregate Ethernet traffic.

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The unit is able to perform time division multiplex/demultiplex of client channels. The client streams are mapped in 16 virtually concatenated VC–4s according to a proprietary–mapping algorithm. Provisioning parameters and alarm collection are managed through two control interfaces. The board has a highly modular fabric consisting of a housing card that can accommodate up to 4 modules, one for each aggregated traffic. The client data rates that the module can manage are reported in Table 37. : Table 37. Relationship between 4xANY optical modules and client type Client type

Fast Ethernet FDDI

Bit rate

@125 Mb/sec @125 Mb/sec

ESCON Digital Video Fiber Channel FICON Gigabit Ethernet

@200 Mb/sec @270 Mb/sec @1.0625 Gb/sec @1.0625 Gb/sec @1.25 Gb/sec

Associated module Type

Wavelength

Acronym

Low Speed

1310 nm

OL–IN

850 nm

OL–MM

1310 nm

OL–IN

850 nm

OL–MM

1310 nm

OL–IN

850 nm

OL–MM

1310 nm

OL–IN

850 nm

OL–MM

1310 nm

OH–IN

850 nm

OH–MM

1310 nm

OH–IN

850 nm

OH–MM

1310 nm

OH–IN

850 nm

OH–MM

Low Speed Low Speed Low Speed High Speed High Speed High Speed

The 4xANYC modules configuration requires the operator to specify the client type to be transported on each module.

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The Table 38. below reports the number of VC–4 istantiated to manage a data stream of each client type

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3.10 4 x ANY HOST C subsystem

Table 38. 4xANY HOST C client type

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Client type

Number of istantiated VC4

Fiber Channel

8

FICON

8

Gigabit Ethernet

8

Digital Video

2

ESCON

2

Fast Ethernet

1

FDDI

1

The max throughput made available by the 4xANY HOSTC port is STM16 (2.5 Gb/s). The capability to handle the whole throughput in terms of cross–connectivity depends on the equipment of the port in “Enhanced H.S slots” rather than in “H.S. slots” of 1660SM shelf as explained on points [1] and [2]. Insertion of the board across hybrid slot (“Enhanced H.S slots” + “H.S. slots”) is not allowed.

[1]

4 x ANY inserted in enhanced slot (25&26, 28&29, 34&35, 37&38)

1AA 00014 0004 (9007) A4 – ALICE 04.10

In ’Enhanced H.S.’ slot, the connection port matrix can exploit two NGI links per type (i.e. 2 ’H’ / 2 ’X’ / 2 ’L” links), each one operating at 622 Mb/s (equivalent 4xSTM1’s), with a total connection bandwidth of 1.2 Gb/s per slot; then, the port equipped in two ’Enhanced’ slots, allows the user to use up to 2.5 Gb/s throughput according to the client allocation grid showed in Figure 152.

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Modules configured

Links towards MATRIX

Client allocation inside 4xANY board

#1

#3

#2

#4

AU4 #1 AU4 #2 AU4 #3 AU4 #4 AU4 #5

GE, FE, FDDI

FC, FICON

AU4 #6 AU4 #7 AU4 #8

FE, FDDI

AU4 #9 AU4 #10 AU4 #11

FE, FDDI

AU4 #12 AU4 #13 AU4 #14

ESCON, DV

NGI link #0

NGI link #1

ESCON, DV ESCON, DV

GE,

NGI link #2

FC, FE, FDDI

FICON

ESCON, DV

NGI link #3

AU4 #15 Figure 152. 4xANY HOST–C: Client allocation grid in “enhanced” slot Consequently, module configuration allowed are as reported in the following Figure 153.

#1

FE, FDDI, ESCON, DV

#3

FE, FDDI, ESCON, DV

#4

#1

#2

#3

FE, FDDI, ESCON, DV

#3

FE, FDDI, ESCON, DV

#2

FE, FDDI, ESCON, DV

#4

Not eq.

#1

FE, FDDI, ESCON, DV Not eq.

#3

Not eq.

GE, FC, FICON,

Not eq.

Not eq.

Not eq.

Not eq.

GE, FC, FICON,

GE, FC, FICON,

#4

#2

Not eq.

#4

Not eq.

Not eq. 1AA 00014 0004 (9007) A4 – ALICE 04.10

GE, FC, FICON, Not eq.

Not eq.

Not eq.

FE, FDDI, ESCON, DV

#1

Not eq.

Not eq.

Not eq.

#2

FE, FDDI, ESCON, DV

Figure 153. 4xANY HOST–C: module configuration in “enhanced” slot Same considerations of Figure 153. are showed in Table 39. :

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AU4 #0

Table 39. Modules configuration in “Enhanced HS” slot

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Module number #3

Module type

Client configured by operator

OH–MM, OH–IN

Fiber Channel FICON Gigabit Ethernet

OL–MM, OL–IN

Digital Video ESCON

Configuration Constraints In conjunction with this clients on module#3, the module#1cannot be used

Fast Ethernet FDDI #1

OH–MM, OH–I cannot be configured in module#1 OL–MM, OL–IN

Digital Video ESCON Fast Ethernet FDDI

#4

OH–MM, OH–IN

Fiber Channel FICON Gigabit Ethernet

OL–MM, OL–IN

Digital Video ESCON

In conjunction with this clients on module#4, the module#2 cannot be used

Fast Ethernet FDDI #2

OH–MM, OH–I cannot be configured in module#2 OL–MM, OL–IN

Digital Video ESCON

1AA 00014 0004 (9007) A4 – ALICE 04.10

Fast Ethernet FDDI

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4 x ANY inserted in not enhanced slot (30&31 and 32&33) In ’H.S.’ slot, the same connectivity is based on one NGI link per type (i.e. ’H’ / ’X’ / ’L’); with a total connection bandwidth of 622 Mb/s per slot; then, the equipment of the port in two ’H.S.’ slots, allows the user to use up to 1.2 Gb/s throughput. In Figure 154. , the client allocation, concerning Gb Ethernet, Fiber Channel, FICON and the relationship with NGI links available for connecting Matrix card, are showed.

Client allocation inside 4xANY board AU–4 optimization AU4 #0 Modules AU4 #1 configured AU4 #2 AU4 #3 AU4 #4 AU4 #5 #1 #3 AU4 #6 AU4 #7 AU4 #8 #2 #4

AU4 #0 GE, FE, FDDI

ESCON, DV

FICON FE, FDDI

ESCON,

AU4 #6 AU4 #7 AU4 #8

DV ESCON,

AU4 #9 FE, FDDI AU4 #10 AU4 #11

DV

AU4 #12 FE, FDDI AU4 #13 AU4 #14

ESCON,

AU4 #15

FC,

GE, FC,

DV

AU4 #1 AU4 #2 AU4 #3 AU4 #4 AU4 #5

FICON

AU4 #9 AU4 #10 AU4 #11 AU4 #12 AU4 #13 AU4 #14

GE, FC, FICON AU4’s not available GE, FC, FICON AU4’s not available

Links towards MATRIX

NGI link #0

NGI link #1 not available

NGI link #2

NGI link #3 not available

AU4 #15

Figure 154. Client allocation grid in “HS slots” with GE/FC/FICON

1AA 00014 0004 (9007) A4 – ALICE 04.10

In Figure 155. , the ’optimized’ client allocation, concerning Fast Ethernet, FDDI, ESCON, Digital Video, , and the relationship with NGI links available for connecting Matrix card, are showed.

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[2]

Client allocation inside 4xANY board

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AU–4 optimization AU4 #0 Modules AU4 #1 configured AU4 #2 AU4 #3 AU4 #4 AU4 #5 #1 #3

#2 #4

AU4 #6 AU4 #7 AU4 #8

AU4 #0 GE, ESCON, DV FE, FDDI

AU4 #1 AU4 #2 AU4 #3 AU4 #4 AU4 #5

FC, FICON

FE, FDDI ESCON, DV ESCON,

AU4 #9 FE, FDDI DV AU4 #10 AU4 #11 AU4 #12 FE, FDDI ESCON, AU4 #13 AU4 #14

DV

FE, FDDI

AU4 #9 AU4 #10 AU4 #11

FC,

AU4 #15

NGI link #0

ESCON FE, FDDI

DV

AU4’s not available

NGI link #1 not available

ESCON FE, FDDI FE, FDDI

AU4 #12 AU4 #13 AU4 #14

FICON

ESCON DV

AU4 #6 AU4 #7 AU4 #8 GE,

Links towards MATRIX

DV

NGI link #2

ESCON DV

AU4’s not

NGI link #3 not available

available

AU4 #15

Figure 155. Client allocation grid in “HS slots” with FE/FDDI/ESCON/DV

Consequently, module configuration allowed are as reported in the following Figure 156.

#1

FE, FDDI, ESCON, DV

#3

FE, FDDI, ESCON, DV Not eq.

#1

Not eq.

#3

#4

FE, FDDI, ESCON, DV

GE, FC, FICON, Not eq.

Not eq.

Not eq.

#2

FE, FDDI, ESCON, DV

Not eq.

Not eq.

#2

#4

Not eq.

1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 156. module configuration in “HS” slots

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Same considerations of Figure 156. are showed in Table 40.

Module number #3

Module type

Client configured by operator

OH–MM, OH–I

Fiber Channel FICON Gigabit Ethernet

OL–MM, OL–IN

Digital Video ESCON

Configuration Constraints In conjunction with this clients on module#3, all other 3 modules cannot be used

Fast Ethernet FDDI #1

OH–MM, OH–I cannot be configured in module#1 OL–MM, OL–IN

Digital Video ESCON Fast Ethernet FDDI

#4

OH–MM, OH–I cannot be configured in module#4 OL–MM, OL–IN

Digital Video ESCON Fast Ethernet FDDI

#2

OH–MM, OH–I cannot be configured in module#2 OL–MM, OL–IN

Digital Video ESCON

1AA 00014 0004 (9007) A4 – ALICE 04.10

Fast Ethernet FDDI

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Table 40. Modules configuration in “HS” slot

3.11 Coarse WDM sub–system

1AA 00014 0004 (9007) A4 – ALICE 04.10

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The following items are considered: –

STM16 colored port (2 two slots wide) to be equipped in “Enhanced H.S.” slots and supporting the 8 channels ’CWDM’ ITU–T grid;

–

COADM 1ch unit (2 two slots wide) to be equipped in “Access area”, supporting the 8 channels ’CWDM” ITU–T grid;

–

COADM 2ch unit (2 two slots wide) to be equipped in “Access area”, supporting the 8 channels ’CWDM” ITU–T grid;

–

MUX/DEMUX 8ch unit (2 two slots wide) to be equipped in “Access area”, supporting the 8 channels ’CWDM” ITU–T grid;

–

Double channel ’multirate’ Transponder unit (100 Mb/s B 2.7 Gb/s) (one slot wide) to be equipped in every slot of “Basic area”, supporting both wavelength assignment function (B/W to ’col’) and wavelength regeneration function (’colored’ to ’colored’) and performing the transparent transport of the following ’client’ signals:

ED

•

FDDI, (not operative in current release)

•

Fast Ethernet, (not operative in current release)

•

STM1/OC3, (not operative in current release)

•

ESCON, (not operative in current release)

•

Digital Video, (not operative in current release)

•

STM4/OC12, (not operative in current release)

•

Fiber Channel, (not operative in current release)

•

FICON, (not operative in current release)

•

Gb Ethernet, (not operative in current release)

•

2 Fiber Channel, (not operative in current release)

•

STM16/OC48,

•

2 Gb Ethernet, (not operative in current release)

•

STM16 w/ FEC (not operative in current release)

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3.11.1 Equipment facilities

The example below reported, shows the equipment with COADM 1(2) channels unit, as for NE’s belonging to network with limited traffic demand (supported by 1 or 2 wavelengths). For this kind of use, also the equipment is supposed to be limited to one shelf only.

ÔÔÔÔÔÔÔÔÔÔÔÔÊÊ ÔÔ ÔÔÔÔ ÔÔÔÔÔ ÔÔÔÔÔ ÔÔÔÔÔ ÔÔÔÊÊ ÊÊ ÔÔ ÔÔ ÔÔÔ ÔÔ ÔÔÔ ÊÊ ÔÔÔÔÔÔÔÔÔÔÔÔÊÊ ÔÔ ÔÔ ÔÔÔ ÔÔ ÔÔÔ ÊÊ ÔÔÔÔÔÔÔÔÔÔÔÔÊÊ ÔÔ ÔÔÔÔ ÔÔÔÔÔ ÔÔÔÔÔ ÔÔÔÔÔ ÔÔÔÊÊ ÊÊ ÔÔ ÔÔ ÔÔÔ ÔÔ ÔÔÔ ÊÊ ÔÔÔÔÔÔÔÔÔÔÔÔÊÊ ÔÔÔÔÔÔÔÔÔÔÔÔÊÊ ÔÔÔÔÔÔÔ ÔÔ ÔÔÔÊÊÊ ÔÔ ÔÔÔ ÔÔÔÔÔ Ê ÔÔ ÔÔÔÔÔ ÔÔÔ Ê Ê ÔÔÔÔÔ Ê ÔÔ ÔÔÔ Ê ÔÔÔÔÔ Ê ÔÔ ÔÔÔ Ê ÔÔÔÔÔ Ê ÔÔÔÔÔ Ê ÔÔ ÔÔÔ Ê ÔÔÔÔÔ Ê ÔÔÔÔÔ Ê

MATRIX B (spare)

Port LS–HS

4 X ANY

Port HS

SMT–16 ”col”

CONGI B Access Card LS/HS Access Card LS/HS Access Card LS/HS Access Card LS/HS Access Card LS/HS Access Card LS/HS Access Card LS/HS Access Card LS/HS Access Card LS

SERVICE

TPD Port HS Port LS Spare – HS Port LS–HS

Access Card LS/HS Access Card LS/HS CONGI A STM–16 –B&W

COADM 1/2 ch.

Port HS

Access Card LS/HS

SMT–16 ”col”

COADM 1/2 ch.

Port LS–HS

MATRIX A (main)

Access Card LS Access Card LS/HS

EQUICO

Basic

Area

Access

Area

Equipment example with COADM 1/2 CHANNELS for Ring application

ÁÁÁÁÁÁÖÖ ÖÖÖÖÖ ÁÁ Ö ÁÁÁÁ ÁÁÁÁ ÁÁÖÖ ÖÖÖ ÖÖ ÖÖÖÖ ÖÖ ÁÁ ÁÁ ÁÁ Ö ÖÖ ÖÖ ÖÖ ÁÁÁÁÁÁÖÖ ÖÖÖÖÖ ÁÁ ÁÁ ÁÁ Ö ÖÖ ÖÖ ÖÖ ÁÁÁÁÁÁÖÖ ÖÖÖÖÖ ÁÁ Ö ÁÁÁÁ ÁÁÁÁ ÁÁÖÖ ÖÖÖ ÖÖ ÖÖÖÖ ÖÖ ÁÁ ÁÁ ÁÁ Ö ÖÖ ÖÖ ÖÖ ÁÁÁÁÁÁÖÖ ÖÖÖÖÖ ÁÁÁÁÁÁÖÖ ÖÖÖÖÖ ÁÁÖÖ ÁÁÖÖÖ ÁÁÖÖ ÖÖÖÖÖ ÁÁ ÁÁÁ ÁÁÁÁÁÖÖÖÖÖÖÖ ÁÁ ÁÁÁÁÁ ÁÁÁÖÖ ÖÖÖÖÖ ÖÖÖÖÖ ÖÖ ÁÁÁÁÁÖÖÖÖÖÖÖ ÁÁ ÁÁÁ ÖÖ ÖÖÖ ÖÖ ÁÁÁÁÁÖÖÖÖÖÖÖ ÁÁ ÁÁÁ ÖÖ ÖÖÖ ÖÖ ÁÁÁÁÁÖÖÖÖÖÖÖ ÁÁÁÁÁÖÖÖÖÖÖÖ ÁÁ ÁÁÁ ÖÖ ÖÖÖ ÖÖ ÁÁÁÁÁÖÖÖÖÖÖÖ ÁÁÁÁÁÖÖÖÖÖÖÖ

9 10 11 12 13 14 15 16 17 18 19 20 21

1 2 3 4 5 6 7 8

22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41

1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 157. COADM functionality: example of equipment shelf

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The shelf layout of resulting equipment is showed in the following figure.

MATRIX B (spare)

Port LS–HS

SMT–16 ”col”

Port HS

Equipment example with MUX/DEMUX 8 Channels handling 4 CWDM FOR RING APPLICATON (2 SEPARATE SHELVES REQUIRED)

MATRIX B (spare)

Port LS–HS

SMT–16 ”col”

Port HS

SMT–16 ”col”

CONGI B Access Card LS/HS Access Card LS/HS Access Card LS/HS Access Card LS/HS Access Card LS/HS Access Card LS/HS Access Card LS/HS Access Card LS/HS Access Card LS

SMT–16 ”col”

CONGI B Access Card LS/HS Access Card LS/HS Access Card LS/HS Access Card LS/HS Access Card LS/HS Access Card LS/HS Access Card LS/HS Access Card LS/HS Access Card LS

SERVICE SERVICE

Port LS–HS Port HS Port LS Spare – HS Port LS–HS

SMT–16 ”col”

Port HS

ÁÁ Á ÁÁÁÁ ÁÖÖ ÁÁ ÖÖÖÖ ÖÖÖÖ ÖÖÖÖ ÖÖ ÁÁ Á ÁÁ ÖÖ ÖÖ ÖÖ ÖÖ ÁÁÁÁ ÁÖÖÖÖÖÖÖÖ ÁÁÁÁ ÁÖÖÖÖÖÖÖÖ ÁÁ Á ÁÁ ÖÖ ÖÖ ÖÖ ÖÖ ÁÁÁÁ ÁÖÖÖÖÖÖÖÖ ÁÁÖÖ ÁÁÁÁ ÁÁ ÖÖÖÖÖÖÖÖ ÁÁ ÁÁÁ ÁÁÁÁÁÖÖÁÁÁÖÖ ÁÁ ÁÁÁ ÖÖ ÁÁÁ ÖÖ ÁÁÁÁÁÖÖÁÁÁÖÖ ÁÁ ÁÁÁ ÖÖ ÁÁÁ ÖÖ ÁÁÁÁÁÖÖÁÁÁÖÖ ÁÁÁÁÁÖÖÁÁÁÖÖ ÁÁÁÁÁÖÖÁÁÁÖÖ ÁÁÁÁ ÁÖÖÖÖÖÖÖÖ ÁÁ Á ÁÁ ÖÖ ÖÖ ÖÖ ÖÖ ÁÁÁÁ ÁÖÖÖÖÖÖÖÖ ÁÁÁÁ ÁÖÖÖÖÖÖÖÖ ÁÁ Á ÁÁ ÖÖ ÖÖ ÖÖ ÖÖ ÁÁÁÁ ÁÖÖÖÖÖÖÖÖ ÁÁ Á ÁÁ ÖÖ ÖÖ ÖÖ ÖÖ ÁÁÁÁ ÁÖÖÖÖÖÖÖÖ ÁÁÖÖ ÁÁÁÁ ÁÁ ÖÖÖÖÖÖÖÖ ÁÁ ÁÁÁ ÁÁÁÁÁÖÖÁÁÁÖÖ ÁÁ ÁÁÁ ÖÖ ÁÁÁ ÖÖ ÁÁÁÁÁÖÖÁÁÁÖÖ ÁÁÁÁÁÖÖÁÁÁÖÖ ÁÁ ÁÁÁ ÖÖ ÁÁÁ ÖÖ ÁÁÁÁÁÖÖÁÁÁÖÖ ÁÁÁÁÁÖÖÁÁÁÖÖ

Port LS–HS Port HS Port LS Spare – HS Port LS–HS

Access Card LS/HS Access Card LS/HS CONGI A SMT–16 ”col”

MUX / DEMUX 8 Channels Port HS

MUX / DEMUX 8 Channels

Access Card LS/HS

SMT–16 ”col”

SMT–16 ”col”

MATRIX A (main)

Port LS–HS

Port LS–HS

Access Card LS/HS Access Card LS/HS Access Card LS/HS Access Card LS/HS Access Card LS/HS Access Card LS/HS Access Card LS/HS CONGI A

Access Card LS Access Card LS/HS

EQUICO

Access Card LS Access Card LS/HS

MATRIX A (main)

Basic Area

EQUICO

Basic Area

Access Area

ÔÔ ÔÔÔÔ ÔÔÔÔÔ ÔÔÔÔÔ ÔÔÔÔÔ ÔÔÔÊÊ ÊÊ ÔÔ ÔÔ ÔÔÔ ÔÔ ÔÔÔ ÊÊ ÔÔÔÔÔÔÔÔÔÔÔÔÊÊ ÔÔÔÔÔÔÔÔÔÔÔÔÊÊ ÔÔ ÔÔ ÔÔÔ ÔÔ ÔÔÔ ÊÊ ÔÔÔÔÔÔÔÔÔÔÔÔÊÊ ÔÔÔÔÔÔÔ ÔÔ ÔÔÔÔÔ ÊÊ ÔÔ ÔÔÔ ÔÔÔÔÔÔÔ ÔÔ ÔÔÔ ÔÔ ÔÔÔÔÔÔÔ ÔÔ ÔÔÔ ÔÔ ÔÔÔÔÔÔÔ ÔÔÔÔÔÔÔ ÔÔÔÔÔÔÔ ÔÔÔÔÔÔÔÔÔÔÔÔÔÔÊÊ ÔÔ ÔÔ ÔÔ ÔÔ ÔÔ ÔÔ ÔÔ ÊÊ ÔÔÔÔÔÔÔÔÔÔÔÔÔÔÊÊ ÔÔÔÔÔÔÔÔÔÔÔÔÔÔÊÊ ÔÔ ÔÔ ÔÔ ÔÔ ÔÔ ÔÔ ÔÔ ÊÊ ÔÔÔÔÔÔÔÔÔÔÔÔÔÔÊÊ ÔÔ ÔÔ ÔÔ ÔÔ ÔÔ ÔÔ ÔÔ ÊÊ ÔÔÔÔÔÔÔÔÔÔÔÔÔÔÊÊ ÔÔÔÔÔÔÔÔÔÔ ÔÔÔÔÔÔ ÊÊ ÔÔÔ ÔÔÔÔÔÔÔ ÔÔ ÔÔÔ ÔÔ ÔÔÔÔÔÔÔ ÔÔÔÔÔÔÔ ÔÔ ÔÔÔ ÔÔ ÔÔÔÔÔÔÔ ÔÔÔÔÔÔÔ

Access Area

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A further example, shows the equipment with” MUX/DEMUX 8 channels units”.

Figure 158. MUX/DEMUX functionality: example of shelf equipment

In this case 4 wavelengths are supposed to be terminated by the node in ’ring’ application; two shelves are then required in order to host the needed amount of STM16 ’CWDM’ interfaces.

1AA 00014 0004 (9007) A4 – ALICE 04.10

The capability to host within the single shelf, the items required for ’OADM’ application (STM16 ’colored’ interface, 4xANY, double TPD, etc.) is the same in both equipment facilities.

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1660SM with WDM signal flow is functionally based, both in ’ring’ and ’linear’ application, on three directions:

1660SM interfacing

1660SM function

1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 159. 1660SM signal flow diagram with WDM application [1]

“client” signals groomed by SDH matrix and carried by ’CWDM’ wavelengths;

[2]

“client” signals not groomed by SDH matrix and carried, transparently, by ’CWDM” wavelengths (wavelength assignment on B/W signals);

[3]

“server” signals not groomed by SDH matrix and regenerated on same or different wavelength.

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3.11.2 Functional description

3.11.3 “Ring” node functional scheme

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In the following, different examples of 1660SM (WDM application) configured as a ’ring’ node are showed. In every hypothesis, all the items involved (represented in gray color) are hosted in a 1660SM shelf.

Figure 160. 1660SM (WDM application) ’ring’ node functional scheme (1)

1AA 00014 0004 (9007) A4 – ALICE 04.10

Specifically, the node represented in Figure 160. terminates on each side, two channels on STM 16 ’colored’ interfaces. The wavelengths multi/demultiplexing is supposed to be performed by MUX/DEMUX 8 channels

Figure 161. 1660SM (WDM application) ’ring’ node functional scheme (2)

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Optical multi/demultiplexing is, anyway, performed through MUX/DEMUX card. Channels terminated into STM16 interfaces can be processed and cross–connected by SDH blocks till the LO granularity; while channels terminated into ’Transponder’ are not groomed at any level but either adapted to the transmission technique or recovered from line degradation. Next Figure 162. and Figure 163. , show the functionality of a ’ring’ node using COADM 1 (2) ch. for wavelengths multi/demultiplexing.

1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 162. 1660SM (WDM application) ’ring’ node functional scheme (3)

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In Figure 161. the node realizes the wavelengths termination by using also ’Double channel transponder’ unit.

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Figure 163. 1660SM (WDM application) ’ring’ node functional scheme (4)

1AA 00014 0004 (9007) A4 – ALICE 04.10

It can be noticed that there is no difference with respect the use of MUX/DEMUX device as regards the processing of terminated channels (both in SDH matrix and in ’Transponder’ unit); as a difference, the COADM structure include a specific link for by–passing those channels of the grid not locally terminated.

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As already considered for ’ring’ application, the following figures shows the functionality of 1660SM (WDM application) configured as the end of a ’linear’ network (i.e. point–to–point connection). Both cases of MUX/DEMUX unit (Figure 164. ) and COADM unit (Figure 165. ) used in ’end’ node are depicted.

Figure 164. 1660SM (WDM application)’end’ node functional scheme (Mux/Demux) Also in this application all the physical parts involved (showed in gray color) are hosted in 1660SM shelf.

1AA 00014 0004 (9007) A4 – ALICE 04.10

No difference, with respect termination channels functionality, already depicted for ’ring’ application, exists.

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3.11.4 “Terminal” node functional scheme

1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 165. 1660SM (WDM application) ’end’ node functional scheme (COADM)

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The aim of this paragraph is defining the optical performances of 1660SM based on CWDM technology. The optical performances definition bases on the optical characteristics related to CWDM devices supported by the equipment (Transceivers, Mux/Demux, OADM) and on the fiber cable characteristics supposed. The CWDM technology is characterized by channel spacing wider than Dense WDM and allows to realize cost–effective applications, through a combination of un–cooled lasers (huge λ deviation versus temperature range, e.g. 8 nm), relaxed laser wavelength selection tolerances (e.g. ± 2 nm) and wide pass–band filters (e.g. 14 nm) inside the optical passive functions. The following paragraphs concern: [1]

CWDM channels used

[2]

the optical functions characteristics in terms of structures and insertion losses ( Mux/Demux/OADM optical operations: structures and insertion losses);

[3]

the fiber attenuation coefficient and fiber chromatic dispersion profile

[4]

the transceiver optical characteristics necessary for power budget calculation

[1] CWDM channels table The set of wavelengths used in the 1660SM equipment is a subset of the nominal central wavelengths grid defined in the ITU–T G.694.2 Recommendation for coarse WDM systems. The complete CWDM wavelengths grid range is from 1270 nm to 1610 nm with spacing of 20 nm. This spacing is the trade–off between the coarse technological aspects and the need to maximize the number of channels available. Table 41. CWDM channels grid supported by 1660SM Nominal central wavelengths (nm) used in the CWDM 1660SM 1470 1490 1510 1530 1550 1570 1590

1AA 00014 0004 (9007) A4 – ALICE 04.10

1610

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3.11.5 Optical span design

[2] Mux/Demux/OADM optical operations: structures and insertion losses

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1660SM supports the following WDM functions: –

multiplexing and demultiplexing of 8 CWDM channels without ’channels pass–through’ link through COMDX8;

–

multiplexing and demultiplexing of 2 CWDM channels with ’channels pass–through’ link through COADM2;

–

multiplexing and demultiplexing of 1 CWDM channel with ’channels pass–through’ link through COADM1.

Figure 166. shows a generic application of the optical functions listed above with the definitions used in the following paragraphs. Table 42. shows the maximum insertion losses (dB) between: –

demux ’In’ and generic channel ’Drop’;

–

generic channel ’Add’ and mux ’Out’;

–

demux ’In and mux ’Out’ (’Pass–through’ connection).

Note – Channel loop insertion–loss is given by adding demux ’In’ and generic channel ’Drop’ to generic channel ’Add’ and mux ’Out’.

In

Mux

Fiber

Demux

Pass–through

Loop

Drop

Fiber

Out

Add

West

East

Out

Loop

Add

1AA 00014 0004 (9007) A4 – ALICE 04.10

Board #1

Demux

Fiber

Mux

Pass–through

In

Fiber

Drop Board #2

Figure 166. Passive optical operation

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Note – Contribution of Chromatic Dispersion related to Mux/Demux/OADM optical operations has been considered equals 0 ps/nm (range currently considered in devices specification is ± 30 ps/nm). Table 42. Boards insertion loss Optical function

Add Ch. Out insertion Loss (dB) Channels (um)

Pass.–th I.L. (dB)

1.47 1.49 1.51 1.53 1.55 1.57 1.59 1.61 MUX (COMDX8)

1.05 1.35 1.65 1.95 2.25 2.55 2.85 3.15

COADM2

1.55 1.55 1.55 1.55 1.55 1.55 1.55 1.55 2.5

COADM1

1.25 1.25 1.25 1.25 1.25 1.25 1.25 1.25 2.1

Optical function

In – Drop Ch. Insertion Loss (dB) Channels (um)

Pass.–th I.L. (dB)

1.47 1.49 1.51 1.53 1.55 1.57 1.59 1.61 DEMUX (COMDX8)

1.05 3.15 2.85 2.55 2.25 1.95 1.65 1.35

COADM2

1.55 1.55 1.55 1.55 1.55 1.55 1.55 1.55 2.5

COADM1

1.25 1.25 1.25 1.25 1.25 1.25 1.25 1.25 2.1

Figure 167. , Figure 168. , Figure 169. highlight the ’Insertion loss’ values as regards COMDX8, COADM2, COADM1.

In the 8 ch.s Mux/Demux operation (COMDX8), the specific equalization (to be considered for device implementation) of the channel loop ’Insertion loss’ versus channels, can be noticed: the result is a constant channel loop insertion loss from 1.49 to 1.61 um wavelength, while a minor value occurs at 1.47 um. This solution allows to optimize ’span length’ performance, considering both ’typical’ attenuation profile of the Standard SMF, wavelength and number of intermediate nodes within a referenced span: the benefits are in terms of possible longer distances between the nodes or greater power margins between the optical interfaces.

1AA 00014 0004 (9007) A4 – ALICE 04.10

In 2 ch.s Mux/Demux operation (COADM2) the channel loop insertion loss has the same value for every couple of wavelengths.

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Note – Insertion loss values related to ’In – Drop’ channel and ’Pass–through’ includes an assumed 0.5 dB insertion loss due to ’CWDM LOS detection stage’ equipped in Mux/Demux/OADM boards

2.1

5.5

1.05 1.35 1.65 1.95 2.25 2.55 2.85 3.15

Fiber

Out

Mux

In

Demux

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Fiber

1.05 3.15 2.85 2.55 2.25 1.95 1.65 1.35

West 1.05 2.1 1.35 1.65 1.95 2.25 5.5 2.55 2.85 3.15

1.05 3.15 2.85 2.55 2.25 1.95 1.65 1.35

Board #1

Demux

Out

Mux

Fiber

East

In

Fiber

Board #2

Figure 167. COMDX8 insertion loss

In

2.5

1.25

1.55 3.1 1.55 1.55

Out

Mux

Fiber

Demux

1.25

1.55

West

East 2.5

1.25

Out

Mux

1.55 3.1 1.55

1AA 00014 0004 (9007) A4 – ALICE 04.10

Board #1

1.55

1.55

Demux

1.25

Fiber

Fiber

In

Fiber

Board #2

Figure 168. COADM2 insertion loss

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1.25 2.5

1.25

1.05 2.1

1.05

1.25 2.5

1.25

Out

West Out

Board #1

Demux

East Mux

Fiber

Fiber

In

Fiber

Board #2

Figure 169. COADM1 insertion loss [3] Fiber Technical Data The referenced fiber for span length evaluation is the Standard Single Mode (SSMF) ITU–T G. 652. The parameters in Table 43. and they are based on data coming from ITU–T G.957 Recommendation. The column ’Typical Attenuation Coefficient’ includes losses due to installation splices, repair splices, and the operating temperature range. The column ’Maximum Attenuation Coefficient’ is obtained by considering a maximum attenuation coefficient of about 0.3 dB/Km1. in the 1500 ÷ 580 nm and, in general, assuming a +30% tolerance over the whole wavelength range supported by the equipment.

1AA 00014 0004 (9007) A4 – ALICE 04.10

Table 43. Fiber technical data Lambda (um)

Typical Attenuation Coefficient (dB/Km)

Max. Attenuation Coefficient (dB/Km)

Max. Chromatic Dispersion Coefficient (ps/nm/Km)

1.47

0.28

0.36

13.10

1.49

0.24

0.31

14.50

1.51

0.22

0.29

15.80

1.53

0.21

0.27

17.30

1.55

0.21

0.27

18.50

1.57

0.22

0.28

19.60

1.59

0.22

0.29

20.50

1.61

0.23

0.30

21.50

1. The 0.3 dB/Km value is in compliance with the system calculation purposes indicated in the ITU–T G.957 Recommendation.

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All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

In

1.05

Mux

Demux

Fiber

1.05 2.1

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

[4] Line transceivers and optical interface power budget (Tx–Rx) The optical interfaces considered for power budget, span power budget and span length calculation have the main optical characteristics showed in Table 44. These optical interfaces are realized through ’2R’ transceivers integrated in SFP MSA device. Three specific devices allows to achieve the best ’performance/cost’ ratio, matching specific network characteristics. The two modules are: –

SFP with PIN detection, consistent with span length around 40 Km (called hereafter BRONZE version);

–

’standard’ SFP with APD detection, consistent with span length around 70 Km (called hereafter SILVER version);

Table 44. Optical transceiver characteristics

Transmitter

PARAMETER

Unit

Symbol

Output Optical power (EOL)

dBm

POUT

BRONZE

SILVER

0

0

Max.

5

5

Min.

REFERENCE

Typ.

Receiver

Chromatic dispersion

ps/ nm

D*Km

Min.

1000

1600

Average Rx Sensitivity@OC–48+FEC

dBm

RSENS

Max.

–18

–28

Maximum input power

dBm

PMAX

Min.

–3

–9

Optical Path Penalty

dB

Max.

1

2

1

REFERENCE:

1AA 00014 0004 (9007) A4 – ALICE 04.10

1 – Worst–case extinction ratio (8.2dB). Measured with a PRBS 223–1 test pattern, @2.67Gb/s, BER TIM detection. • V5[1,2]: BIP–2 is recovered ––> Ex–BER, Signal Degrade alarm • V5[3]: REI bit is recovered and the derived performance primitives is reported. • V5[8]: RDI information is recovered and reported. • AIS or SSF detection ––> SSF alarm

•

LPA (S12/P12x_A_Sk): It extracts the VC12–POH and processes the TU12 pointer. • V5[5–7]: Signal label detection in the byte V5[5–7] ––> Signal label Mismatch detection • AIS or SSF is applied if Signal label Mismatch is detected

•

PPI (E12/P12x_A_So and E12_TT_So):This block provides the interface between the internal unit format and the physical transmission medium. It encodes into HDB3 code the signal to be sent on line.

1AA 00014 0004 (9007) A4 – ALICE 04.10

Other functions implemented are :

ED

•

Clock Reference Selection Block (on G.A): provides six 2 MHz clock links towards the MATRIX cards for synchronization purposes. The selection among the 63 flows is made via software.

•

TIMING (on G.A): receives the reference clock (38.88 MHz) and synchronism pulse (500 Hz) from the MATRIX cards and extracts the local clocks used by the G.A. The Tx clock is locked, by means of a PLL to the system clock or, when in free running, to a local oscillator with a +–50ppm drift: (51 MHz OSC) block.

•

RIBUS I/F This block is used to read/write from/to the ”RIBUS” stream, to control the LED on the unit, to release the Management–bus in case of power failure, and to use the remote inventory. It is powered by the + 3.3 Vdc supply by CONGI boards.

•

REMOTE INVENTORY It is the memory containing the board information, for identification purposes (see para. 3.17 on page 358 for details).

•

M–BUS Driver It drives the input–output gates of the Management–bus. These drivers can be disabled (by the Bus–OFF signal) in case of power failure.

•

DC/DC CONVERTER It converts the 48/60 V power supply to the 3.3 V used to supply all the components in the board. The DC/DC converter is synchronized with a synchronization clock at 288 MHz (signal Power–Sync, generated by G.A.) in order to avoid EMI problems.

•

STEP DOWN It uses the 3.3 V power supply from DC/DC Converter block to obtain the 2.5 V used to power the Gate Array (G.A.). 02 3AL 91668 AA AA 636

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•

Input side

2Mb/s #1

PPI sink

LPA source

from Access Card

ckr1

LTCT source

ckrx

STM4 BPF I/F

#63

2Mb/s outputs

Access Card

#1

ckr1

2Mb/s #63

ckr63

ckr63

to

LPT source

ckrx

cktx

6x

Output side

2Mb/s #1

PPI source

Clock Reference Selection

LPA sink

LTCT sink

LPT sink

ckt1

STM4 BPF I/F

EPS

2Mb/s #63

#63

cktx

ckt63

ckt1

ckt63

Local Clocks

Power Sync

2.5 V

CONGI A & B

DC/DC CONV.

Config. & Status

51MHz OSC

CMISS

Bus–OFF F

Management Bus

3.3 V

+ 3.3 Vdc

Remote Inventory

63 x 2 MBIT/S PORT CARD

1AA 00014 0004 (9007) A4 – ALICE 04.10

M–BUS Driver

to/from MATRIX

from

STEP DOWN

ck–system a ck–system b

TIMING

ckrx cktx

G.A.

48/60 V

to MATRIX Main and Spare

#1

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ .. ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ .. .. .. ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ .. .. .. ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ .. ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ .. ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ .. .. .. . ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ .. . ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

from MATRIX Main and Spare

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2Mb/s inputs

RIBUS I/F

RIBUS

ID

Unit Failure

Figure 245. 63 x 2 Mbit/s card – Block Diagram

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4.19 63 x 2 Mbit/s / G703 / ISDN–PRA port card (P63E1N–M4)

The 63 x 2 Mbit/s /G.703/ISDN–PRA port is similar to the basic 63 x 2 Mbit/s port, described in the previous paragraph 4.18 on page 413, with the difference that the present board implements also the NT functionality on ISDN Primary Rate Access (PRA) and the “Retiming function” on the 2 Mbit/s interfaces. The Retiming function applies the Equipment Clock to the outgoing 2Mb/s signal that therefore becomes synchronized with the SDH network synchronization reference . The additional circuit that allows this implementation consists in an elastic buffer that is able to absorb the jitter and wander that is transferred to the PDH signal when SDH pointer justification occurs. This feature is programmable via SW, in order to include or exclude the Retiming for each single port. The same P63E1N unit can mix ports that apply or not the retiming. In this paragraph is reported the description of the NT ISDN–PRA function, all the other blocks functionalities are described in the previous paragraph 4.18 on page 413. The ISDN–PRA (Integrated Services Digital Network – Primary Rate Access) is a facility to carry a number of synchronous digital communication channels to the user over a 2048 kbit/s structured signal; the ISDN–PRA structure is defined in recommendation ETS 300 233. The sample frames are reported in paragraph 3.18.1, page 367 up to para. 3.18.1.2, page 369. The 2048 kbit/s signals can be structured or non–structured: in this latter case, the PRA functionality must be disabled from Craft–Terminal. The selection among structured/non–structured and basic–frame/multiframe options is achieved by means of Craft–Terminal, for individual signals. It performs standard PRA functionality as well as some custom Leased Line functions (settable from C.T.). Figure 247. on page 420 illustrates the NT ISDN–PRA block, that performs the following functions:

1AA 00014 0004 (9007) A4 – ALICE 04.10

UPSTREAM DIRECTION (from user to SDH network: incoming signal SY2Min, outgoing signal UP2Mout) –

Loopback2: by means of command LB2, sent by the controller, or detected in the Sa6 message coming from the SDH network (UP2Min signal); this command sends back to the source the upstream signal.

–

AIS Detection: the AIS alarm (AIS2M) is detected after the reception of 512 bits containing less than 3 zeroes.

–

Frame Alignment (FA): it performs basic–frame and multi–frame alignment according to ITU–T G.706, presettable from the controller (commands BF and MF); the LOF2M alarm is declared in case of non alignment .

–

Failure Condition: the Failure Condition FC2M alarm is the “OR” of LOS2M, LOF2M , AIS2M alarms.

–

REI alarm detection (E): the REI2M alarm is detected if E=0.

–

RAI alarm detection (A): the RAI2M alarm is detected if active for 5 consecutive frames.

–

Data Error detection (CRC–4): errors integrity check on the incoming data, according to CRC–4 procedure (Cyclic Redundancy Check), as defined in G.706. In case of errors, the alarm ERR2M is arised.

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(See Figure 246. on page 419).

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–

E bit insertion (E): the outgoing E bit is set to 0 when • a failure condition (FCU) is detected on signal from SDH network (UP2Min); • errors (ERRU) are detected on data from SDH network (UP2Min); • the E insertion may be inhibited from controller, in this case E=1. • E=1 in other cases.

–

A bit insertion (A): the outgoing A bit is set to • ’0’ when a failure condition (FC2M) is detected on signal from user (SY2Min); • ’1’ when Loopback2 (LB2) is activated; • passed transparently in other cases; • the A bit may be forced from controller. • set to ’1’ (*) when a failure condition (FCU) is detected on signal from SDH network (UP2Min); N.B. (*): this option is enabled only in case of Leased Line applications;

–

Sa5, Sa6 Messages: • the outgoing Sa6 message is inserted in 4 Sa6 bits of 4 consecutive frames, with the following significance (listed in order of their priority/severity): – 1000 ––> power fail – 1111 ––> SSF or AUXPU/AISU on signal from SDH network (UP2Min); – 1110 ––> LOFU on signal from SDH network (UP2Min); – 1100 ––> FC2M on signal from user (SY2Min); – 0000 ––> loopback2 (LB2) activated – 0001 ––> alarm REI2M from user – 0010 ––> CRC–4 errors (ERR2M) from user – 0011 ––> simultaneous occurrence of both previous (REI2M and ERR2M) – 0011 ––> only basic–frame alignment on SY2Min signal, when in automatic search – 0000 ––> normal operations. • the outgoing Sa5 bit is set to: – ’0’ ––> when loopback2 (LB2) is activated – ’1’ ––> in other cases.

–

CRC–4 bits insertion: the CRC–4 on data is performed and the result is inserted on bits C1 to C4, according to G.706.

–

Frame Word insertion (FW): the basic–frame and multi–frame alignment words are inserted on the frame.

–

Substituted Frames insertion: the substituted frames are inserted, in case of occurrence of a failure condition (FC2M) on incoming signal from user. N.B. Substituted frame is a frame with Sa4, Sa5, Sa7, Sa8 as well as all the bits in time slots 1 to 31 set to ’1’, and with A bit set to ’0’.

1AA 00014 0004 (9007) A4 – ALICE 04.10

DOWNSTREAM DIRECTION (from SDH network to user: incoming signal UP2Min, outgoing signal SY2Mout) –

Loopback–RX: by means of command LB–RX, sent by the controller; this command sends back to the source the downstream signal.

–

AIS Detection: the AIS alarm (AISU) is detected after the reception of 512 bits containing less than 3 zeroes.

–

AUXP Detection: the AUXPU alarm is detected after the reception of 512 bits containing the pattern ...010101... with less than 3 deviation from the pattern itself. It can be enabled from the controller.

–

Frame Alignment (FA): it performs basic–frame and multi–frame alignment according to ITU–T G.706, presettable from the controller (commands BF and MF); the LOFU alarm is declared in case of non alignment.

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Failure Condition: the Failure Condition FCU alarm is the “OR” of SSF, LOFU , AISU, AUXPU alarms. N.B. SSF =Server Signal Fail, from upstream.

–

REI alarm detection (E): the REIU alarm is detected if E=0.

–

RAI alarm detection (A): the RAIU alarm is detected if active for 5 consecutive frames.

–

Sa6: the Sa6 bit is read for every 4 consecutive frames, to check the presence of the loopback2 command, when 4XSa6=1010, for 8 consecutive times.

–

Data Error detection (CRC–4): errors integrity check on the incoming data, according to CRC–4 procedure (Cyclic Redundancy Check), as defined in G.706. In case of errors, the alarm ERRU is arised.

–

A* insertion: the A bit is • passed transparently in standard applications • set to ’1’ (*) when a failure condition (FC2M) is detected on signal from user (SY2Min); • set to ’1’ (*) when forced from the controller; N.B. (*): this option is enabled only in case of Leased Line applications.

–

E bit insertion (E): the outgoing E bit is set to 0 when • a failure condition (FC2M) is detected on signal from user (SY2Min); • errors (ERR2M) are detected on data from user (SY2Min); • the E insertion may be inhibited from controller, in this case E=1. • E=1 in other cases. • set to ’0’ (*) when Power Fail alarm (PWF) is active; N.B. (*): this option is enabled only in case of Leased Line applications.

–

Sa4* insertion: the bits Sa4 to Sa8 are passed transparently in standard applications, • Sa4 is set to ’0’ (*) when Power Fail alarm (PWF) is active, passed transparently otherwise. N.B. (*): this option is enabled only in case of Leased Line applications.

–

CRC–4 bits insertion: the CRC–4 on data is performed and the result is inserted on bits C1 to C4, according to G.706.

–

Frame Word insertion (FW): the basic–frame and multi–frame alignment words are inserted on the frame.

–

AIS insertion: a continuous bitstream of all ’ONES’ is inserted, in case of occurrence of • force command from the controller; • a failure condition (FCU) on signal from SDH network (UP2Min); • (*) a failure condition (FC2M) on signal from user (SY2Min). N.B. (*): this option is enabled only in case of Leased Line applications.

ALARMS, STATUS AND COMMANDS CONVEYED FROM/TO CONTROLLER Every alarm, status and errors counting results are reported to the controller, for monitoring purposes: –

LOS, REI, RAI, FC, ERR(CRC–4), SSF detected either in upstream and in downstream signal directions N.B. LOS = Loss of user Signal; SSF= upstream Server Signal Fail.

1AA 00014 0004 (9007) A4 – ALICE 04.10

The controller sends the following commands, in order to enable the relevant functions: –

ED

LB–2, LB–RX, BF, MF, ForceA, InhibitE, etc. N.B. BF= Basic Frame; MF = Multi Frame.

02 3AL 91668 AA AA 636

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–

from Access Card

#1

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ.. ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ . .. ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ .. . .. ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ .. . ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ .. .. . ÎÎÎÎÎÎÎÎÎÎÎÎÎ .. .. ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Input side

2Mb/s #1

PPI sink

2 Mb/s POM

NT ISDN PRA source

LPA source

ckr1

#63

LPT source

LTCT source

STM4 BPF I/F

ckrx

ckr1

2Mb/s #63

Clock Reference Selection

ckr63

ckr63

ckrx

6x

Output side

#1

2Mb/s #1

PPI source

2 Mb/s POM

NT ISDN PRA sink

cktx

LPA sink

LPT sink

LTCT sink

STM4 BPF I/F

ckt1

EPS

2Mb/s #63

cktx

ckt63

ckt1

ckt63

Local Clocks

Power Sync

2.5 V

48/60 V

DC/DC CONV.

Config. & Status

51MHz OSC

M–BUS Driver

3.3 V CMISS

Bus–OFF F

Management Bus

to/from MATRIX

from CONGI A & B

STEP DOWN

ck–system a ck–system b

TIMING

ckrx cktx

G.A.

from MATRIX Main and Spare

Access Card

to

2Mb/s outputs

#63

+ 3.3 Vdc

Remote Inventory

63 x 2 MBIT/S PORT CARD

1AA 00014 0004 (9007) A4 – ALICE 04.10

to MATRIX Main and Spare

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

2Mb/s inputs

RIBUS I/F

RIBUS

ID

Unit Failure

Figure 246. 63 x 2 Mbit/s G.703/ISDN–PRA, Block Diagram

ED

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1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 247. Functional Diagram of the NT ISDN–PRA block

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AIS

FCU (*) FC2M

LB 2

FROM/TO CONTROLLER EQUICO

SY2Mout

PWF

LOS2M

SY2Min

To User (downstream)

FC2M

+

FW

AIS 2M

AIS

REI 2M

+

A

REI U

+

A*

RAIU

ALARMS & STATUS

FC U

+

E

FC 2M (*)

ERR U

FCU

E

+

(*) FCU

LB

CRC–4

ERR U

FC2M

A

+

ERR U

CONVEYED FROM/TO CONTROLLER

RAI2M ERR 2M

+

Sa4*

FC 2M

ERR2M

ERR2M

CRC–4

PWF (*)

RAI2M

(*)

PWF

REI 2M

E

FC 2M

CRC–4

LOF2M

FA

BF MF

Sa6

LB2

BF

Sa5, Sa6 Messages

+

MF

E

REIU

BF MF

FA

LOFu

AUXP

FC2M

AIS

AISu

FC U

SUBST FRAMES

AUXPu

FW

+

LBRX

UP2Min

SSF

UP2Mout

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A

RAIU

CRC–4

+

To SDH Network (upstream)

4.20 3 x 34/45 Mbit/s port card (P3E3T3)

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(See Figure 248. on page 423) The P3E3T3 port card is a bidirectional interface from/to three PDH streams at 34 Mbit/s or at 45 Mbit/s switchable and the STM4–BPF (BPF=backpanel format ). Due to the back panel format, the 3 plesiochronous 34 or 45 Mbit/s signals that can be housed in an STM–1 frame, are dropped/inserted in the AU4#4 of the STM–4 frame. It realizes the functions required by the ITU–T G.783 rec. i.e. : •

maps the payload into a C–3

•

add/extracts the VC3 POH

•

processes the TU3 pointer

•

adapts the VC3 to the VC4

•

assembles/disassembles the STM–1 format

The SDH functions are preformed by four Gate Array, one for each port and one that is common to the three ports: –

34/45 Mbit/s interface

The G.A. performs a fully bidirectional interface for a 34 Mbit/s PDH flow or for a 45 Mbit/s PDH flow in compliance with the ITU–T G.783. A G.A. can manage only one stream, therefore three G.A. are necessary to process the 3 streams on the port card. The PPI functions is performed by the access card ( two separated according to the bit rate) according to the ITU–T G.703 Rec. INPUT side •

LPA (S3/P3_A_So) Asynchronous mapping of 3x34 /45 Mbit/s into the VC–3 C2 insertion

•

LPT ( S3_TT_So) J1 path trace insertion G1 (path status) insertion : REI and RDI insertion B3 calculation and insertion (VC3, BIP8) F2 and F3 bytes insertion (coming from OH bus and DCC bus)

•

LTCA (Low order tandem connection adaptation) Frame start signal generation on VC_AIS detection

•

LTCT (Low order tandem connection termination)

1AA 00014 0004 (9007) A4 – ALICE 04.10

N1processing and insertion (TC–RDI, REI, ODI, OEI ..)

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OUTPUT side •

LPA (S3/P3_A_Sk)

•

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

VC3 demapping and desynchronization C2 monitoring AIS generation LPT ( S3_TT_Sk) LP–TIM detection (J1 monitoring) LP–SLM and UNEQ detection (C2 monitoring) RDI detection REI recovery B3 BIP–8 count and error detection F2 and F3 bytes extraction and sending to AUX* bus and DCC* bus •

LTCA (Low order tandem connection adaptation) Invalid frame start condition restoration

•

LTCT (Low order tandem connection termination) N1 monitoring and processing B3 insertion (VC–3 BIP–8 compensation )

–

STM–4 & timing G.A. The G.A. provides the following functions: •

to connect the three ”34/45 Mbit/s interface” to the backpanel . In fact the frame format leaving the ”34/45 Mbit/s interface” is a 4 wire bus at 38.88 Mbit/s while the backpanel format is STM–4*.

•

Timing: it receives the 622 MHz System clock from the two MATRIX and generates the clock at 38.88 MHz for the ”34/45 MBit/s interface”.

Other functions implemented are : •

RIBUS I/F This block is used to read/write from/to the ”RIBUS” stream, to control the LED on the unit, to release the Management–bus in case of power failure, and to use the remote inventory. It is powered by the + 3.3 Vdc supply by CONGI boards.

•

REMOTE INVENTORY It is the memory containing the board information, for identification purposes (see para. 3.17 on page 358 for details).

•

M–BUS Driver It drives the input–output gates of the Management–bus. These drivers can be disabled (by the Bus–OFF signal) in case of power failure. DC/DC CONVERTER It converts the 48/60 V power supply to the 3.3 V used to supply all the components in the board. The DC/DC converter is synchronized with a synchronization clock at 288 MHz (signal Power–Sync, generated by G.A.) in order to avoid EMI problems. STEP DOWN It uses the 3.3 V power supply from DC/DC Converter block to obtain the 2.5 V used to power the Gate Array (G.A.).

1AA 00014 0004 (9007) A4 – ALICE 04.10

•

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Input side

From/To Access Card

Data IN LOS

LPA

LPT

LTCA

LTCT

AU4 ASSEMBLY

STM4 BPF 622 Mbit/s I/F

4 X 38.88 Mbit/s

Output side

Data OUT

LPA

LPT

LTCA

LTCT

STM–4 & TIMING G.A.

AU4 DISASS.

CK 38.88

TIMING CK syst.

AUX DCC CK 38.88 34/45 Mb/s #2 Input side

Data IN From/To Access Card

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

AUX

34/45 Mb/s #3

To/From MATRIX Main and Spare

DCC

CK 38.88

From MATRIX Main and Spare

AUX DCC

LOS

LPA

LPT

LTCA

LTCT

AU4 ASSEMBLY

Power Sync

Output side LPT

LTCA

LTCT

AUX DCC

Input side LPA

LPT

LTCA

LTCT

AU4 ASSEMBLY

Output side

Data OUT

LPA

LPT

LTCA

LTCT

+ 3.3 Vdc

Configuration and Status

From/To Access Card

Data IN LOS

2.5 V STEP DOWN

CK 38.88

34/45 Mb/s #1

DC/DC 48/60 V CONV.

3.3 V

AU4 DISASS.

AU4 DISASS.

Unit Failure

Management bus

M–BUS Driver

CMISS Bus–off RIBUS

1AA 00014 0004 (9007) A4 – ALICE 04.10

3 x 34/45 MBIT/S PORT CARD

REMOTE INVENTORY

F

RIBUS I/F

from CONGI A & B

LPA

To/From MATRIX Main and Spare

Data OUT

Id + 3.3 Vdc

Figure 248. 3x34/45 port card –Block diagram

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4.21 4 x STM–1 electrical/optical port card (P4S1N)

The 4 x STM–1 port processes up to four STM–1 streams. A max. of two electrical or optical modules can be housed on the card to give physical access to the STM–1 signal. The remaining two physical accesses are on the relevant access card . The SDH functions required to manage STM–1 signal are implemented by the G.A. mounted on the board. It interfaces the two MATRIX card via backpanel. Referring to the ITU–T G.783 Recommendation , the G.A. performs the following functions : –

TTF

–

HOA

–

LPOM /LSUT (the last is not available in this release)

–

HPOM /HSUT (the last is not available in this release)

Cross connection functions (MSP, HPC and LPC) are performed by the two MATRIX boards (working in 1+1 configuration). The TTF block is connected to the MATRIX boards (main and spare) through 1+1 bidirectional links at 622 Mbit/s , STM–4 equivalent capacity. HOA block is connected both to the HPC matrices and to the LPC matrices on the two MATRIX boards through a couple of 1+1 links at 622 MBit/s working in protection, STM–4 equivalent capacity. Backpanel interface supply a system–clock to the G.A. internal circuits. In the following block description, the new naming convention of the G.783 is reported. Refer to para. 3.3.2 on page 196 for details. The G.A. send and receive four STM–1 signals (data + clock) at 155 Mbit/s to/from each SPI. An external LOS is received from each input line interface. Each optical transmitter provides its status by means of two input signals: Laser Degrade and Laser Failure. The ALS algorithm is hardware implemented : the G.A. provides the Laser shut Down command (LASER OFF). In the following will be described the signal processing of only one STM–1 interface; the other three interfaces process the signal in the same way. The PISO & SIPO (Parallel–In Serial–Out; Serial–in Parallel–out) blocks allow the unit to interface with the back panel at of 622 Mbit/s bit rate, mapping the STM–1 signals over a STM–4 internal equivalent frame. TTF BLOCK ( SPI, RST, MST, MSA)

1AA 00014 0004 (9007) A4 – ALICE 04.10

This block performs the Transport Terminal Functions (sink on Input side, source on Output side) for STM–1 signals. TTF block provides the T1 timing references at 2 MHz , derived from the STM–1 input signals.

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(See Figure 249. on page 428 )

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INPUT side : from line to MSP block on MATRIX SPI (OSn/RSn_A_Sk) : it descramblers the incoming signal , counts the OOF and reveals the LOF alarm. RST (RSn_TT_Sk) : performs frame alignment detection (A1, A2) , regenerator section trace recovery (J0) and mismatch detection, BIP–8 Errored Block count. J0 is not managed in this release. MST (MSn_TT_Sk) : performs BIP–24 errored block count, MS–REI recovery, MS–RDI and MS–AIS detection. TSD is applied in case of MS–DEG (signal degrade), TSF is applied if MS–AIS is detected. MSA (MSn/Sn_A_Sk) : performs AU4 pointer interpretation, LOP and AIS detection, pointer justification. Moreover the following functions are performed on the Rx side : SOH BYTE extraction (Rx side): DCC bytes (DCCR D1–D3 and DCCM D4–D12) are dropped and serialized in a DCC frame. Two DCC frames are generated working in 1+1 protection. OUTPUT side : from MATRIX to line MSA (Ms/Sn_A_So) : it performs AUG assembly, AU–4 pointer generation, AU–AIS generation. MST (MSn_TT_So) : it performs BIP–24 calculation and insertion, MS–REI MS–RDI and MS–AIS insertion. RST (RSn_TT_So) : it performs frame alignment insertion, regenerator section path trace insertion, BIP–8 calculation and insertion. SOH BYTE insertion (Tx side): DCC bytes (DCCR D1–D3 and DCCM D4–D12) coming from the DCC frames are inserted into the SOH section. SPI (OSn/RSn_A_So) :it scramblers the outgoing signals and insert AIS in alarm condition. HOA BLOCK (HPT, HPA) From HPC matrix to LPC matrix HPT (Sn_TT_Sk) : path trace information is recovered, REI information is recovered, HP–RDI and UNEQ are detected, VC4 BIP–8 errored count block. TSF is applied if SSF or UNEQ or TIM or AIS is detected. TSD is applied if a condition of signal degrade is detected. Moreover : F2 F3 byte extraction (Rx side) : both F2 and F3 bytes are extracted from the received flow and serialized on a DCC frame . N1 byte extraction (Rx side) : for the network Tandem Connection Termination & Monitoring function (TCT/TCM).

1AA 00014 0004 (9007) A4 – ALICE 04.10

HPA (Sn/Sm_A_Sk) : VC–4 disassembly, TU pointer interpretation, LOP and TU–AIS detection, HP–SLM and LOM detection.

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HPA (Sn/Sm_A_So) : VC4 assembly, TU pointer generation, TU–AIS generation , signal label insertion, HPT (Sn_TT_So) : path trace identification insertion, RDI and REI indications insertion, VC–4 BIP–8 calculation and insertion. Moreover: F2 and F3 byte insertion (Tx side) : F2/F3 bytes are inserted on the DCC frame N1 byte insertion (Tx side) : for the network Tandem Connection Termination & Monitoring function (TCT/TCM). The G.A. provides also the HSUT, HPOM, (alternative) and LSUT, LPOM functions (alternative) both in Rx and Tx side. The main task of HSUT are: RX side (from MSA to HPC matrix): • • • • •

path trace information recovery REI recovery HP–RDI detection (path status monitoring UNEQ and VC–AIS detection (signal label monitoring) VC4 BIP–8 Errored Block count

Tx side: (from HPC matrix to MSA) • • • •

generation of an unequipped container ”unequipped” insertion, trail trace identifier generation RDI and /or REI information generation VC–4 BIP–8 calculation and insertion

The main task of HPOM are: RX and TX side: • • • • • • •

signal termination J1 path recovering REI information recovering HP–RDI detection (path status monitoring UNEQ and VC–AIS detection (signal label monitoring) VC4 BIP–8 Errored Block count TSF is generated in case of SSF , UNEQ, TIM , AIS . TSD is generated in case of SD

The main tasks of LSUT are :

1AA 00014 0004 (9007) A4 – ALICE 04.10

RX side (from HPA to LPC matrix): • • • •

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recovering of VC–m unequipped signal label path trace recovering BIP–2 recovery REI and RDI recovery

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From LPC matrix to HPC matrix

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Tx side (from LPC matrix to HPA ): • • • •

insertion of VC–m unequipped signal label path trace insertion BIP–2 insertion REI and RDI insertion

LSUT is used to monitor unequipped path trails . The main tasks of LPOM are : • • • •

trace identifier monitoring RDI and REI recovering and deriving for performance primitives signal label monitoring VC–m BIP–2 errored block count

LPOM is used for performance monitoring purposes. Other functions implemented are : •

RIBUS I/F This block is used to read/write from/to the ”RIBUS” stream, to control the LED on the unit, to release the Management–bus in case of power failure, and to use the remote inventory. RIBUS I/F is powered by the + 3.3 Vdc supply by CONGI boards.

•

REMOTE INVENTORY It is the memory containing the board information, for identification purposes (see para. 3.17 on page 358 for details).

•

M–BUS Driver It drives the input–output gates of the Management–bus. These drivers can be disabled (by the Bus–OFF signal) in case of power failure. DC/DC CONVERTERS

1AA 00014 0004 (9007) A4 – ALICE 04.10

This block converts the 48/60 V power supply 3.3 V and 2.5 V used to supply all the components in the board. The DC/DC converter is synchronized with a synchronization clock at 300 MHz (signal Power–Sync, generated by G.A.) in order to avoid EMI problems.

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F2, F3 Optical or Electrical Plug–in Module

Optical Input/ Output 1

SPI

HPOM HSUT (*)

TTF

STM–1 RST LOS LASER D. DCCR RSOH LASER F. LASER OFF

T1 (3a) (3b) (3c) (3d)

MSA

MST

(4a)

DCCM MSOH

Optical Input/ Output 3

3 rd INTERFACE

SPI ( )

Optical Input/ Output 4

4 th INTERFACE SPI ( )

AUX

PISO & SIPO

(5b) (5c) (5d)

2nd INTERFACE

DCC

PISO & SIPO

(4b) (4c) (4d) (5a)

F2, F3 Optical Input/ Output 2

to/from HPC matrix (H Link)

PISO & SIPO

(1b) (2b) (3b) (4b) (5b)

T1

(1c) (2c) (3c) (4c) (5c)

T1

(1d) (2d) (3d) (4d) (5d)

T1

Config. & Status

622 MHz OSC

Management Bus

M–BUS Driver

CMISS Bus–OFF Remote Inventory RIBUS I/F

Power Sync Unit Failure 3.3 V 2.5 V ACCESS CARD

RIBUS

FROM/TO SERVICE

LPOM LSUT (*)

to/from LPC matrix (L link)

PISO & SIPO

(2b) (2c) (2d)

MATRIX MAIN AND SPARE

(2a)

HPA

MATRIX MAIN AND SPARE

HPT HOA

to/from HPC matrix (X Link)

PISO & SIPO

(1b) (1c) (1d)

FROM/TO MATRIX MAIN AND SPARE

1st INTERFACE

(1a)

ID F

+3.3 Vdc 48/60 V

DC/DC CONVERTERS

FROM CONGI A & B

G.A.

4 x STM–1 ELECTRICAL/OPTICAL PORT

Notes: (*) –

1AA 00014 0004 (9007) A4 – ALICE 04.10

( )–

HSUT and LSUT are not available in the current release THE ” SPI” ASSOCIATED TO THE 3rd AND 4th INTERFACES ARE PHISICALLY ON THE ACCESS CARD

Figure 249. 4 x STM–1 Electrical/Optical port block diagram

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System–clock a System–clock b

4.22 4 X 140/STM1 switchable O/E port card (P4E4N)

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(See Figure 250. on page 434 and Figure 251. on page 435) The 4 X 140/STM1 switchable O/E port card is a bidirectional unit which interfaces up to four plesiochronous 140 Mbit/s (E4) or Synchronous 155 Mbit/s (STM–1) with STM4–BPF (BPF=backpanel format ). The choice among the two possible different interfaces is flexible and mixed configuration are allowed. For each P4E4N port card there are four electrical (75 Ohm) or optical module( Short and Long Haul) ;two of the four module are hosted directly on the port card , the other two are hosted in the relevant access card (A2S1). The description that follows explains the two operating mode of each interface (140 Mbit/s PDH or 155 Mbit/s SDH) on the port card.

155 Mbit/s STM–1 The SDH functions required to manage STM–1 signal are implemented by the G.A. mounted on the board. It interfaces the two MATRIX cards via backpanel. The “Mapper/Demapper 140–PDH/155–STM–1” block is internally by–passed through the EN 140/155 signal when the interface is programmed as 155 Mbit/s. Referring to the ITU–T G.783 Recommendation , the G.A. performs the following functions : –

TTF

–

HOA

–

LPOM /LSUT (the last is not available in this release)

–

HPOM /HSUT (the last is not available in this release)

Cross connection functions (MSP, HPC and LPC) are performed by the matrices present on the two MATRIX boards (working in 1+1 configuration). The TTF block is connected to the MATRIX boards (main and spare) through 1+1 bidirectional links at 622 Mbit/s , STM–4 equivalent capacity. HOA block is connected both to the HPC matrices and to the LPC matrices on the two MATRIX boards through a couple of 1+1 links at 622 MBit/s working in protection, STM–4 equivalent capacity. Backpanel interface supply a system–clock to the G.A. internal circuits. In the following block description, the new naming convention of the G.783 is reported. Refer to para. 3.3.2 on page 196 for details. The G.A. send and receive four STM–1 signals (data + clock) at 155 Mbit/s to/from each SPI. An external LOS is received from each input line interface. Each optical transmitter provides its status by means of two input signals: Laser Degrade and Laser Failure.

1AA 00014 0004 (9007) A4 – ALICE 04.10

The ALS algorithm is hardware implemented : the G.A. provides the Laser shut Down command (LASER OFF). In the following will be described the signal processing of only one STM–1 interface; the other three interfaces process the signal in the same way.

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TTF BLOCK ( SPI, RST, MST, MSA) This block performs the Transport Terminal Functions (sink on Input side, source on Output side) for STM–1 signals. TTF block provides the T1 timing references at 2 MHz , derived from the STM–1 input signals. INPUT side : from line to MSP block on MATRIX SPI (OSn/RSn_A_Sk) : it descramblers the incoming signal , counts the OOF and reveals the LOF alarm. RST (RSn_TT_Sk) : performs frame alignment detection (A1, A2) , regenerator section trace recovery (J0) and mismatch detection, BIP–8 Errored Block count. J0 is not managed in this release. MST (MSn_TT_Sk) : performs BIP–24 errored block count, MS–REI recovery, MS–RDI and MS–AIS detection. TSD is applied in case of MS–DEG (signal degrade), TSF is applied if MS–AIS is detected. MSA (MSn/Sn_A_Sk) : performs AU4 pointer interpretation, LOP and AIS detection, pointer justification. Moreover the following functions are performed on the Rx side : SOH BYTE extraction (Rx side): DCC bytes (DCCR D1–D3 and DCCM D4–D12) are dropped and serialized in a DCC frame. Two DCC frames are generated working in 1+1 protection. OUTPUT side : from MATRIX to line MSA (Ms/Sn_A_So) : it performs AUG assembly, AU–4 pointer generation, AU–AIS generation. MST (MSn_TT_So) : it performs BIP–24 calculation and insertion, MS–REI MS–RDI and MS–AIS insertion. RST (RSn_TT_So) : it performs frame alignment insertion, regenerator section path trace insertion, BIP–8 calculation and insertion. SOH BYTE insertion (Tx side): DCC bytes (DCCR D1–D3 and DCCM D4–D12) coming from the DCC frames are inserted into the SOH section. SPI (OSn/RSn_A_So) :it scramblers the outgoing signals and insert AIS in alarm condition. HOA BLOCK (HPT, HPA) From HPC matrix to LPC matrix HPT (Sn_TT_Sk) : path trace information is recovered, REI information is recovered, HP–RDI and UNEQ are detected, VC4 BIP–8 errored count block. TSF is applied if SSF or UNEQ or TIM or AIS is detected. TSD is applied if a condition of signal degrade is detected.

1AA 00014 0004 (9007) A4 – ALICE 04.10

Moreover : F2 F3 byte extraction (Rx side) : both F2 and F3 bytes are extracted from the received flow and serialized on a DCC frame .

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The PISO & SIPO (Parallel–In Serial–Out; Serial–in Parallel–out) blocks allow the unit to interface with the back panel at of 622 Mbit/s bit rate, mapping the STM–1 signals over a STM–4 internal equivalent frame.

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N1 byte extraction (Rx side) : for the network Tandem Connection Termination & Monitoring function (TCT/TCM). HPA (Sn/Sm_A_Sk) : VC–4 disassembly, TU pointer interpretation, LOP and TU–AIS detection, HP–SLM and LOM detection. From LPC matrix to HPC matrix HPA (Sn/Sm_A_So) : VC4 assembly, TU pointer generation, TU–AIS generation , signal label insertion, HPT (Sn_TT_So) : path trace identification insertion, RDI and REI indications insertion, VC–4 BIP–8 calculation and insertion. Moreover: F2 and F3 byte insertion (Tx side) : F2/F3 bytes are inserted on the DCC frame N1 byte insertion (Tx side) : for the network Tandem Connection Termination & Monitoring function (TCT/TCM). The G.A. provides also the HSUT, HPOM, (alternative) and LSUT, LPOM functions (alternative) both in Rx and Tx side. The main task of HSUT are: RX side (from MSA to HPC matrix): • • • • •

path trace information recovery REI recovery HP–RDI detection (path status monitoring UNEQ and VC–AIS detection (signal label monitoring) VC4 BIP–8 Errored Block count

Tx side: (from HPC matrix to MSA) • • • •

generation of an unequipped container ”unequipped” insertion, trail trace identifier generation RDI and /or REI information generation VC–4 BIP–8 calculation and insertion

The main task of HPOM are: RX and TX side:

1AA 00014 0004 (9007) A4 – ALICE 04.10

• • • • • • •

signal termination J1 path recovering REI information recovering HP–RDI detection (path status monitoring UNEQ and VC–AIS detection (signal label monitoring) VC4 BIP–8 Errored Block count TSF is generated in case of SSF , UNEQ, TIM , AIS . TSD is generated in case of SD

The main tasks of LSUT are : RX side (from HPA to LPC matrix): •

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• • •

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path trace recovering BIP–2 recovery REI and RDI recovery

Tx side (from LPC matrix to HPA ): • • • •

insertion of VC–m unequipped signal label path trace insertion BIP–2 insertion REI and RDI insertion

LSUT is used to monitor unequipped path trails . The main tasks of LPOM are : • • • •

trace identifier monitoring RDI and REI recovering and deriving for performance primitives signal label monitoring VC–m BIP–2 errored block count

LPOM is used for performance monitoring purposes.

140 Mbit/s PDH The functions required to manage 140 Mbit/s PDH signal are implemented by the “Mapper/Demapper 140–PDH/155–STM–1” block and G.A. mounted on the board. The last interfaces the two matrix on the MATRIX cards via backpanel. INPUT side : from line to MSP block on MATRIX The circuits concerned are: PPI (E4_TT_Sk and E4/P4s_A_Sk) : it interfaces the line extracting the timing, decoding data and AIS detecting. It is also performed the PDH LOS processing. The Data flow is than sent to the LPA block after a serial to parallel conversion (SIPO). LPA (S4/P4s_A_So) The 140 Mbit/s plesiochronous stream is inserted in a C4 container to be adapted so as to be transported into the synchronous network. HPT (S4_TT_So) The Virtual Container (VC4) is formatted. The VC4 is structured so that its octets are distributed within a 125 msec. interval (i.e., one STM–1 period), and consists of the C4 container and POH. The latter containing nine octets equally distributed within the frame. Figure 217. on page 363 depicts the structure of a VC4 and of the POH bytes: J1, B3. C2, G1, F2, H4, Z3–Z5. Bytes F2, Z3–Z5 .

1AA 00014 0004 (9007) A4 – ALICE 04.10

PG ( Pointer Generator) A fixed pointer value is inserted in the AUOH to structure the AU4 signal. MST and RST This two functions are necessary to create a proprietary STM–1 signal in order to interface the “Mapper/Demapper 140–PDH/155–STM–1” block with the G.A. Data are sent to the G.A. in a serial way through the PISO block. In the G.A. the complementary function are made (RST, MST, MSA).

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OUTPUT side : from MATRIX to line

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The circuits concerned are: MSA (inside the G.A.): It performs AUG assembly, AU–4 pointer generation, AU–AIS generation MST and RST (inside the G.A.):this two functions are necessary to create a STM–1 signal in order to interface the G.A with the “Mapper/Demapper 140–PDH/155–STM–1” block . Data are sent from G.A. to Mapper/Demapper 140–PDH/155–STM–1” block in serial way and than converted in parallel through a SIPO. ALIGNER: it searches the frame alignment word and checks the alignment conditions. HPT ( S4_TT_Sk): Extracts the POH bytes from the VC4 structure and manages them accordingly (see Figure 217. on page 363). LPA (S4/P4s_ASk) Restructures the 140 Mbit/s PDH signal by extracting it from Container C4 . The signal is than sent in serial way (through PISO) to the PPI block. PPI (E4/P4s_A_So and E4_TT_So ) : it convert the internal signal code to the line code.

Other functions implemented are : •

RIBUS I/F This block is used to: – – – – – –

read/write from/to the ”RIBUS” stream control the LED on the unit to release the Management–bus in case of power failure read remote inventory data enable 155Mbit/ or 140 Mbit/s operating mode ( EN 140/155) separately send Internal Loop and External Loop commands to each interface separately

RIBUS I/F is powered by the + 3.3 Vdc supply by CONGI boards. •

REMOTE INVENTORY It is the memory containing the board information, for identification purposes (see para. 3.17 on page 358 for details).

•

M–BUS Driver It drives the input–output gates of the Management–bus. These drivers can be disabled (by the Bus–OFF signal) in case of power failure. DC/DC CONVERTERS

1AA 00014 0004 (9007) A4 – ALICE 04.10

This block converts the 48/60 V power supply 5V, 3.3 V, 2.5 V and 1.8 V used to supply all the components in the board. The DC/DC converter is synchronized with a synchronization clock at 300 MHz (signal Power–Sync, generated by G.A.) in order to avoid EMI problems.

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HPT

SPI or PPI

Data

MAPPER/DEMAPPER 140–PDH/155–STM1

LOS

TTF

RST

MST

(3a) (3b) (3c) (3d)

Data DCCR RSOH

LASER D. LASER F. LASER OFF O/E Input/ Output 2

MSA DCCM MSOH

3 rd INTERFACE EN 140/155 4 th INTERFACE

SPI ( ) EN 140/155

622 MHz OSC Power Sync.

Config. & Status

Remote Inventory

DCC

PISO & SIPO

(5b) (5c) (5d)

2nd INTERFACE

O/E Input/ Output 4

PISO & SIPO

(4b) (4c) (4d) (5a)

EN 140/155

SPI ( )

to/from HPC matrix (H Link)

(4a)

F2, F3

O/E Input/ Output 3

PISO & SIPO

AUX

(1b) (2b) (3b) (4b) (5b)

T1

(1c) (2c) (3c) (4c) (5c)

T1

(1d) (2d) (3d) (4d) (5d)

T1

Management Bus

M–BUS Driver

CMISS

Bus–OFF

RIBUS EN 140/155 1–4 Line Loop 1–4 Int. Loop 1–4

1.8 V 5V 3.3 V

DC/DC CONVERTERS

RIBUS I/F

FROM/TO SERVICE

O/E LOS Module

T1

HPOM HSUT(*)

F2, F3

to/from LPC matrix (L link)

MATRIX MAIN AND SPARE

O/E Input/ Output 1

LPOM (*) LSUT EN 140/155

PISO & SIPO

(2b) (2c) (2d)

FROM/TO MATRIX MAIN AND SPARE

Line Loop

(2a)

HPA

Int. Loop

to/from HPC matrix (X Link)

ID F

Unit failure

FROM CONGI

1st INTERFACE

PISO & SIPO

(1b) (1c) (1d)

MATRIX MAIN AND SPARE

(1a)

HOA

+3.3 Vdc 48/60 V

2.5 V ACCESS CARD

4 X 140/STM–1 ELECTRICAL/OPTICAL PORT

1AA 00014 0004 (9007) A4 – ALICE 04.10

Notes: (*) –

HSUT and LSUT are not available in the current release

( )–

THE ” SPI” ASSOCIATED TO THE 3rd AND 4th INTERFACES ARE PHISICALLY ON THE ACCESS CARD

Figure 250. 4 x 140/STM–1 Electrical / Optical port block diagram

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System–clock a System–clock b

G.A.

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EN 140/155

MAPPER/DEMAPPER 140–PDH/155–STM1

EN 140/155 DATA to G.A.

155 Mbit/s PISO Data In

LPA Insert into C4

SIPO

HPT

PDH AIS Detector

Pointer Generation

MST

RST

C3,B3 SDH LOS

LOS

TO G.A.

PDH LOS processing EN 140/155

Data Out

OH MANAGEMENT

LPA 140 Mbit/s Reconstruction

PISO

HPT POH EXTRACTION

ALIGNER

SIPO

DATA from G.A.

155 Mbit/s

1AA 00014 0004 (9007) A4 – ALICE 04.10

EN 140/155

Figure 251. Mapper /Demapper 140–PDH / 155–STM1 block diagram

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4.23 4 x STM–1 port (P4ES1N)

The 4 x STM–1 port processes up to four STM–1 streams. The physical accesses to the four STM–1 signals are available on the relevant access card. The SDH functions required to manage STM–1 signal are implemented by the G.A. mounted on the board. It interfaces the two MATRIX card via backpanel. Referring to the ITU–T G.783 Recommendation , the G.A. performs the following functions : –

TTF

–

HOA

–

LPOM /LSUT (the last is not available in this release)

–

HPOM /HSUT (the last is not available in this release)

Cross connection functions (MSP, HPC and LPC) are performed by the two MATRIX boards (working in 1+1 configuration). The TTF block is connected to the MATRIX boards (main and spare) through 1+1 bidirectional links at 622 Mbit/s , STM–4 equivalent capacity. HOA block is connected both to the HPC matrices and to the LPC matrices on the two MATRIX board through a couple of 1+1 links at 622 MBit/s working in protection, STM–4 equivalent capacity. Backpanel interface supply a system–clock to the G.A. internal circuits. In the following block description, the new naming convention of the G.783 is reported. Refer to para. 3.3.2 on page 196 for details. The G.A. send and receive four STM–1 signals (data + clock) at 155 Mbit/s to/from each SPI. An external LOS is received from each input line interface. In the following will be described the signal processing of only one STM–1 interface; the other three interfaces process the signal in the same way. The PISO & SIPO (Parallel–In Serial–Out; Serial–in Parallel–out) blocks allow the unit to interface with the back panel at of 622 Mbit/s bit rate, mapping the STM–1 signals over a STM–4 internal equivalent frame. TTF BLOCK ( SPI, RST, MST, MSA) This block performs the Transport Terminal Functions (sink on Input side, source on Output side) for STM–1 signals.

1AA 00014 0004 (9007) A4 – ALICE 04.10

TTF block provides the T1 timing references at 2 MHz , derived from the STM–1 input signals.

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(See Figure 252. on page 440 )

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INPUT side : from line to MSP block on MATRIX SPI (OSn/RSn_A_Sk) : it descramblers the incoming signal , counts the OOF and reveals the LOF alarm. RST (RSn_TT_Sk) : performs frame alignment detection (A1, A2) , regenerator section trace recovery (J0) and mismatch detection, BIP–8 Errored Block count. J0 is not managed in this release. MST (MSn_TT_Sk) : performs BIP–24 errored block count, MS–REI recovery, MS–RDI and MS–AIS detection. TSD is applied in case of MS–DEG (signal degrade), TSF is applied if MS–AIS is detected. MSA (MSn/Sn_A_Sk) : performs AU4 pointer interpretation, LOP and AIS detection, pointer justification. Moreover the following functions are performed on the Rx side : SOH BYTE extraction (Rx side): DCC bytes (DCCR D1–D3 and DCCM D4–D12) are dropped and serialized in a DCC frame. Two DCC frames are generated working in 1+1 protection. OUTPUT side : from MATRIX to line MSA (Ms/Sn_A_So) : it performs AUG assembly, AU–4 pointer generation, AU–AIS generation. MST (MSn_TT_So) : it performs BIP–24 calculation and insertion, MS–REI MS–RDI and MS–AIS insertion. RST (RSn_TT_So) : it performs frame alignment insertion, regenerator section path trace insertion, BIP–8 calculation and insertion. SOH BYTE insertion (Tx side): DCC bytes (DCCR D1–D3 and DCCM D4–D12) coming from the DCC frames are inserted into the SOH section. SPI (OSn/RSn_A_So) :it scramblers the outgoing signals and insert AIS in alarm condition.

HOA BLOCK (HPT, HPA) From HPC matrix to LPC matrix HPT (Sn_TT_Sk) : path trace information is recovered, REI information is recovered, HP–RDI and UNEQ are detected, VC4 BIP–8 errored count block. TSF is applied if SSF or UNEQ or TIM or AIS is detected. TSD is applied if a condition of signal degrade is detected. Moreover : F2 F3 byte extraction (Rx side) : both F2 and F3 bytes are extracted from the received flow and serialized on a DCC frame .

1AA 00014 0004 (9007) A4 – ALICE 04.10

N1 byte extraction (Rx side) : for the network Tandem Connection Termination & Monitoring function (TCT/TCM). HPA (Sn/Sm_A_Sk) : VC–4 disassembly, TU pointer interpretation, LOP and TU–AIS detection, HP–SLM and LOM detection.

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HPA (Sn/Sm_A_So) : VC4 assembly, TU pointer generation, TU–AIS generation , signal label insertion, HPT (Sn_TT_So) : path trace identification insertion, RDI and REI indications insertion, VC–4 BIP–8 calculation and insertion. Moreover: F2 and F3 byte insertion (Tx side) : F2/F3 bytes are inserted on the DCC frame N1 byte insertion (Tx side) : for the network Tandem Connection Termination & Monitoring function (TCT/TCM). The G.A. provides also the HSUT, HPOM, (alternative) and LSUT, LPOM functions (alternative) both in Rx and Tx side. The main task of HSUT are: RX side (from MSA to HPC matrix): • • • • •

path trace information recovery REI recovery HP–RDI detection (path status monitoring UNEQ and VC–AIS detection (signal label monitoring) VC4 BIP–8 Errored Block count

Tx side: (from HPC matrix to MSA) • • • •

generation of an unequipped container ”unequipped” insertion, trail trace identifier generation RDI and /or REI information generation VC–4 BIP–8 calculation and insertion

The main task of HPOM are: RX and TX side: • • • • • • •

signal termination J1 path recovering REI information recovering HP–RDI detection (path status monitoring UNEQ and VC–AIS detection (signal label monitoring) VC4 BIP–8 Errored Block count TSF is generated in case of SSF , UNEQ, TIM , AIS . TSD is generated in case of SD

The main tasks of LSUT are :

1AA 00014 0004 (9007) A4 – ALICE 04.10

RX side (from HPA to LPC matrix): • • • •

ED

recovering of VC–m unequipped signal label path trace recovering BIP–2 recovery REI and RDI recovery

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From LPC matrix to HPC matrix

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Tx side (from LPC matrix to HPA ): • • • •

insertion of VC–m unequipped signal label path trace insertion BIP–2 insertion REI and RDI insertion

LSUT is used to monitor unequipped path trails . The main tasks of LPOM are : • • • •

trace identifier monitoring RDI and REI recovering and deriving for performance primitives signal label monitoring VC–m BIP–2 errored block count

LPOM is used for performance monitoring purposes. Other functions implemented are : •

RIBUS I/F This block is used to read/write from/to the ”RIBUS” stream, to control the LED on the unit, to release the Management–bus in case of power failure, and to use the remote inventory. RIBUS I/F is powered by the + 3.3 Vdc supply by CONGI boards.

•

REMOTE INVENTORY It is the memory containing the board information, for identification purposes (see para. 3.17 on page 358 for details).

•

M–BUS Driver It drives the input–output gates of the Management–bus. These drivers can be disabled (by the Bus–OFF signal) in case of power failure. DC/DC CONVERTERS

1AA 00014 0004 (9007) A4 – ALICE 04.10

This block converts the 48/60 V power supply 3.3 V and 2.5 V used to supply all the components in the board. The DC/DC converter is synchronized with a synchronization clock at 300 MHz (signal Power–Sync, generated by G.A.) in order to avoid EMI problems.

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System–clock a (1a) (1b) (1c) (1d)

HPT HOA

(2a)

HPA

RST

MST

(3a) (3b) (3c) (3d)

MSA

PISO & SIPO

to/from HPC matrix (H Link)

LOS (4a)

(5b) (5c) (5d)

F2, F3 2nd INTERFACE

SPI

Optical Input/ Output 3

3 rd INTERFACE

SPI Optical Input/ Output 4

4 th INTERFACE SPI

PISO & SIPO

PISO & SIPO

AUX

(1b) (2b) (3b) (4b) (5b)

T1

(1c) (2c) (3c) (4c) (5c)

T1

(1d) (2d) (3d) (4d) (5d)

T1

Config. & Status

622 MHz OSC

DCC

Management Bus

M–BUS Driver

CMISS Bus–OFF Remote Inventory

ID RIBUS

RIBUS I/F

Power Sync Unit Failure

F

3.3 V

+ 3.3 Vdc 48/60 V

DC/DC 2.5 V CONVERTERS ACCESS CARD

FROM/TO SERVICE

(4b) (4c) (4d) (5a)

MATRIX MAIN AND SPARE

DCCM MSOH

FROM/TO MATRIX MAIN AND SPARE

DCCR RSOH

Optical Input/ Output 2

to/from LPC matrix (L Link)

FROM CONGI A & B

SPI

PISO & SIPO

to/from HPC matrix (X Link)

T1

HPOM HSUT (*)

TTF STM–1

(2b) (2c) (2d)

LPOM LSUT (*)

F2, F3 Optical Input/ Output 1

PISO & SIPO

MATRIX MAIN AND SPARE

G.A. 1st INTERFACE

4 x STM–1 ELECTRICAL PORT

Notes:

1AA 00014 0004 (9007) A4 – ALICE 04.10

(*) –

HSUT and LSUT are not available in the current release

Figure 252. 4 x STM–1 Electrical port block diagram

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System–clock b

4.24 4 x OC3 AU3/TU3 CONVERSION port (P4OC3)

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(Refer to Figure 253. on page 447) This board can manage up to 4 x OC–3 (SONET) streams. The board hosts up to 2 interfaces into the front panel, which can be equipped with Electrical (ICMI) or Optical plug–in modules (IS–1.1, IL–1.1, IL–1.2, MM1). The other two interfaces can be hosted in the Access area using the A2S1 access card. Each combination of electrical/optical modules can be equipped in the same board. On OC–3 interface the Sonet mapping is manage so the RS and MS sections are terminated, the 3 AU3 are processed to extract or insert the 3 VC3. This unit performs the AU3/TU3 conversion , which allows the transport in SDH network of Sonet VC3 traffic. The conversion is performed on OC–3 interface: the 3 VC3 are extracted then re–mapping in SDH VC4 container and this container is passed to the matrix where it is managed as a structured VC4. Figure 212. on page 359 depicts the AU3/TU3 conversion mechanism achieved by 4xOC3 board. The Sonet interface (OC3) have not to be configured as Synchronization source. The OH byte of RS and MS section are managed according SDH ITU standard. The configuration is done by Craft Terminal or Network Management. No EPS is supported by this board. The description of the board has been divided in two parts; the first is the “AU3/TU3 conversion block” thath implement the SONET functionality, the second is the “G.A.” that implement the SDH functionality.

AU3/TU3 conversion block The functions required to manage OC3 signal are implemented by the “AU3/TU3 conversion block that interface the G.A. mounted on the board. The last interfaces the two matrix on the MATRIX cards via backpanel. INPUT side : from plug–in module to G.A. The circuits concerned are: SIPO :this block performs the Serial to Parallel conversion (SIPO) of the SONET STS3/OC3 (155 Mb/s) serial stream coming from the line. ALIGNER (SDH/SONET standard Frame Aligner) The Frame Aligner Word (FAW) extracted by the incoming frame is inserted by the MST/RST* source function into the outgoing frame: in this way G.A. is able to detect a possible OOF (Out Of Frame) condition as well.

1AA 00014 0004 (9007) A4 – ALICE 04.10

RST/MST Sk This block performs: • •

Standard SDH/SONET Descrambler extraction of all SOH bytes of the SONET stream that are inserted in RST/MST* source functions to be processed by G.A. B1 and B2 calculation and checking in order to send error information downstream

•

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AU3–TU3 Rx

• • • •

time–division Pointer Interpreter of the 3 AU3s Pointer buffer Pointer Generator of the 3 TU3 multiplexed inside the AU4 Pointer Generator of the AU4

HPT* So This block performs: • •

calculation and insertion of B3 byte in AU4 POH insertion of C2 byte in AU4 POH

MST/RST* So This block performs: • •

insertion of extracted and stored SOH bytes compensation of B1 and B2 bytes by usage of error information collected by RST/MST sink function

PISO: this block performs the towards G.A.

Parallel to Serial conversion (PISO) of the SDH STM–1 stream

On the Input side the LOS alarm is buffered and sent to the G.A.

OUTPUT side : from G.A. to Plug–in module SIPO :this block performs the Serial to Parallel conversion (SIPO) of the SDH STM–1 stream coming from G.A. ALIGNER* Alignment to SDH STM–1 stream coming from G.A. is performed RST/MST* Sk This block performs: • extraction of all SOH bytes of the SDH stream that are inserted in RST/MST source functions • B1 calculation and checking for internal use. HPT* Sk It implements the “Path Label Mismatch“ algorithm; the C2 byte from the incoming AU4 frame is extracted and its content is written into a register. If the value is different than expected, a “Path Label Mismatch” alarm is raised

1AA 00014 0004 (9007) A4 – ALICE 04.10

AU3–TU3 Tx: • • • • •

ED

Pointer Interpreter of the AU4 time–division Pointer Interpreter of the 3 TU3s Pointer buffer Pointer Generator of the 3 AU3 multiplexed inside the OC3 pointer justifications and buffer overflow alarms are reported Equipment Controller (EC)

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The AU3 to TU3 conversion block contains:

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MST/RST So This block performs: • • •

insertion of extracted and stored SOH bytes calculation and insertion of B1 and B2 bytes standard SONET scrambler

PISO: this block performs the Parallel to Serial conversion (PISO) of the SONET STS3/OC3 stream towards the line.

G.A. (Gate Array) The SDH functions are implemented by the G.A. mounted on the board. It interfaces the two MATRIX cards via backpanel. Referring to the ITU–T G.783 Recommendation , the G.A. performs the following functions : –

TTF

–

HOA

–

LPOM /LSUT (the last is not available in this release)

–

HPOM /HSUT (the last is not available in this release)

Cross connection functions (MSP, HPC and LPC) are performed by the matrices present on the two MATRIX boards (working in 1+1 configuration). The TTF block is connected to the MATRIX boards (main and spare) through 1+1 bidirectional links at 622 Mbit/s , STM–4 equivalent capacity. HOA block is connected both to the HPC matrices and to the LPC matrices on the two MATRIX boards through a couple of 1+1 links at 622 MBit/s working in protection, STM–4 equivalent capacity. Backpanel interface supply a system–clock to the G.A. internal circuits. In the following block description, the new naming convention of the G.783 is reported. Refer to para. 3.3.2 on page 196 for details. The G.A. send and receive four signals (data + clock) to/from the four “AU3/TU3 CONVERSION block” An external LOS is received from each input line interface. Each optical transmitter provides its status by means of two input signals: Laser Degrade and Laser Failure. The ALS algorithm is hardware implemented : the G.A. provides the Laser shut Down command (LASER OFF). In the following will be described the signal processing of only one signal from/to “AU3/TU3 CONVERSION block”; the other three interfaces process the signal in the same way.

1AA 00014 0004 (9007) A4 – ALICE 04.10

The PISO & SIPO (Parallel–In Serial–Out; Serial–in Parallel–out) blocks allow the unit to interface with the back panel at of 622 Mbit/s bit rate, mapping the signals over a STM–4 internal equivalent frame.

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This block performs the Transport Terminal Functions (sink on Input side, source on Output side) for the 155 Mbit/s signals. INPUT side : from line to MSP block on MATRIX SPI* (OSn/RSn_A_Sk) : it descramblers the incoming signal , counts the OOF and reveals the LOF alarm. RST (RSn_TT_Sk) : performs frame alignment detection (A1, A2) , regenerator section trace recovery (J0) and mismatch detection, BIP–8 Errored Block count. J0 is not managed in this release. MST (MSn_TT_Sk) : performs BIP–24 errored block count, MS–REI recovery, MS–RDI and MS–AIS detection. TSD is applied in case of MS–DEG (signal degrade), TSF is applied if MS–AIS is detected. MSA (MSn/Sn_A_Sk) : performs AU4 pointer interpretation, LOP and AIS detection, pointer justification. Moreover the following functions are performed on the Rx side : SOH BYTE extraction (Rx side): DCC bytes (DCCR D1–D3 and DCCM D4–D12) are dropped and serialized in a DCC frame. Two DCC frames are generated working in 1+1 protection. OUTPUT side : from MATRIX to line MSA (Ms/Sn_A_So) : it performs AUG assembly, AU–4 pointer generation, AU–AIS generation. MST (MSn_TT_So) : it performs BIP–24 calculation and insertion, MS–REI MS–RDI and MS–AIS insertion. RST (RSn_TT_So) : it performs frame alignment insertion, regenerator section path trace insertion, BIP–8 calculation and insertion. SOH BYTE insertion (Tx side): DCC bytes (DCCR D1–D3 and DCCM D4–D12) coming from the DCC frames are inserted into the SOH section. SPI* (OSn/RSn_A_So) :it scramblers the outgoing signals and insert AIS in alarm condition. HOA BLOCK (HPT, HPA) From HPC matrix to LPC matrix HPT (Sn_TT_Sk) : path trace information is recovered, REI information is recovered, HP–RDI and UNEQ are detected, VC4 BIP–8 errored count block. TSF is applied if SSF or UNEQ or TIM or AIS is detected. TSD is applied if a condition of signal degrade is detected. Moreover : F2 F3 byte extraction (Rx side) : both F2 and F3 bytes are extracted from the received flow and serialized on a DCC frame .

1AA 00014 0004 (9007) A4 – ALICE 04.10

N1 byte extraction (Rx side) : for the network Tandem Connection Termination & Monitoring function (TCT/TCM). HPA (Sn/Sm_A_Sk) : VC–4 disassembly, TU pointer interpretation, LOP and TU–AIS detection, HP–SLM and LOM detection.

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TTF BLOCK ( SPI*, RST, MST, MSA)

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From LPC matrix to HPC matrix HPA (Sn/Sm_A_So) : VC4 assembly, TU pointer generation, TU–AIS generation , signal label insertion, HPT (Sn_TT_So) : path trace identification insertion, RDI and REI indications insertion, VC–4 BIP–8 calculation and insertion. Moreover: F2 and F3 byte insertion (Tx side) : F2/F3 bytes are inserted on the DCC frame N1 byte insertion (Tx side) : for the network Tandem Connection Termination & Monitoring function (TCT/TCM). The G.A. provides also the HSUT, HPOM, (alternative) and LSUT, LPOM functions (alternative) both in Rx and Tx side. The main task of HSUT are: RX side (from MSA to HPC matrix): • • • • •

path trace information recovery REI recovery HP–RDI detection (path status monitoring UNEQ and VC–AIS detection (signal label monitoring) VC4 BIP–8 Errored Block count

Tx side: (from HPC matrix to MSA) • • • •

generation of an unequipped container ”unequipped” insertion, trail trace identifier generation RDI and /or REI information generation VC–4 BIP–8 calculation and insertion

The main task of HPOM are: RX and TX side: • • • • • • •

signal termination J1 path recovering REI information recovering HP–RDI detection (path status monitoring UNEQ and VC–AIS detection (signal label monitoring) VC4 BIP–8 Errored Block count TSF is generated in case of SSF , UNEQ, TIM , AIS . TSD is generated in case of SD

The main tasks of LSUT are :

1AA 00014 0004 (9007) A4 – ALICE 04.10

RX side (from HPA to LPC matrix): • • • •

ED

recovering of VC–m unequipped signal label path trace recovering BIP–2 recovery REI and RDI recovery

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Tx side (from LPC matrix to HPA ): • • • •

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insertion of VC–m unequipped signal label path trace insertion BIP–2 insertion REI and RDI insertion

LSUT is used to monitor unequipped path trails . The main tasks of LPOM are : • • • •

trace identifier monitoring RDI and REI recovering and deriving for performance primitives signal label monitoring VC–m BIP–2 errored block count

LPOM is used for performance monitoring purposes.

Other functions implemented are : •

RIBUS I/F This block is used to: – – – – –

read/write from/to the ”RIBUS” stream control the LED on the unit to release the Management–bus in case of power failure read remote inventory data send Internal Loop and External Loop commands to each interface separately

RIBUS I/F is powered by the + 3.3 Vdc supply by CONGI boards. •

REMOTE INVENTORY It is the memory containing the board information, for identification purposes (see para. 3.17 on page 358 for details).

•

M–BUS Driver It drives the input–output gates of the Management–bus. These drivers can be disabled (by the Bus–OFF signal) in case of power failure. DC/DC CONVERTERS

1AA 00014 0004 (9007) A4 – ALICE 04.10

This block converts the 48/60 V power supply 5V, 3.3 V, 2.5 V and 1.8 V used to supply all the components in the board. The DC/DC converter is synchronized with a synchronization clock at 300 MHz (signal Power–Sync, generated by G.A.) in order to avoid EMI problems.

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System–clock a System–clock b

1st INTERFACE

HPT

(2a)

HPA

Int. Loop

Data

AUE/TU3

(3a) (3b) (3c) (3d)

TTF

Data

CONVERSION

SPI*

RST

MSA

MST

PISO & SIPO

to/from HPC matrix (H Link)

block

O/E Input/ Output 2

DCCM MSOH

(4a)

(1d) (2d) (3d) (4d) (5d)

4 th INTERFACE

622 MHz OSC Power Sync.

Config. & Status

Remote Inventory

AUX

(1c) (2c) (3c) (4c) (5c)

3 rd INTERFACE

SPI ( )

DCC

(1b) (2b) (3b) (4b) (5b)

2nd INTERFACE

SPI ( )

PISO & SIPO

(5b) (5c) (5d)

F2, F3

O/E Input/ Output 3

PISO & SIPO

(4b) (4c) (4d) (5a)

Management Bus

M–BUS Driver

CMISS

Bus–OFF

RIBUS Line Loop 1–4 Int. Loop 1–4

1.8 V 5V 3.3 V

DC/DC CONVERTERS

FROM/TO SERVICE

DCCR RSOH

LASER D. LASER F. LASER OFF

O/E Input/ Output 4

to/from LPC matrix (L link)

RIBUS I/F

FROM/TO MATRIX MAIN AND SPARE

SPI

LOS

to/from HPC matrix (X Link)

HPOM HSUT(*)

F2, F3 O/E LOS Module

PISO & SIPO

(2b) (2c) (2d)

LPOM (*) LSUT

Line Loop O/E Input/ Output 1

PISO & SIPO

(1b) (1c) (1d)

ID F

Unit failure

FROM CONGI

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(1a)

HOA

MATRIX MAIN AND SPARE

G.A.

+3.3 Vdc 48/60 V

2.5 V ACCESS CARD

4xOC3 AU3/TU3 CONVERSION PORT

1AA 00014 0004 (9007) A4 – ALICE 04.10

Notes: (*) –

HSUT and LSUT are not available in the current release

( )–

THE ” SPI” ASSOCIATED TO THE 3rd AND 4th INTERFACES ARE PHISICALLY ON THE ACCESS CARD

Figure 253. 4 x OC3 AU3/TU3 conversion port(P40C3)

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RSOH bytes SOH BYPASS

MSOH bytes

B1 error for compensation Data from plug–in module

B2 error for compensation

OOF

AU3–TU3 Rx SIPO

Aligner

RST sk

MST sk

PI PB PG TU3 AU3

PG AU4*

HPT* So

MST* So

RST* So

PISO

DATA to G.A.

B3, C2 LOS

LOS

LOS BUFFERING

RSOH bytes SOH BYPASS

Data to plug–in module

TU3–AU3 Tx PISO

RST So

MST So

PG AU3

PI PI PB TU3 AU4

C2 check

1AA 00014 0004 (9007) A4 – ALICE 04.10

MSOH bytes

MST* sk

RST* sk

Aligner *

SIPO

DATA from G.A.

HPT* Sk

Figure 254. AU3/TU3 conversion block

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AU3/TU3 CONVERSION block

4.25 STM–4 optical ports

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(See Figure 255. on page453) The STM–4 port processes an optical STM–4 stream. Different STM–4 optical port are available according to the connector type (FC/PC or SC/PC) and wave length (S–4.1, L–4.1 and L–4.2); in the following a generic description is given. The SDH functions required to manage STM–4 signal are implemented by the G.A. mounted on the board. It interfaces the two MATRIX boards via backpanel. Referring to the ITU–T G.783 recommendation, the G.A. performs the following functions : –

TTF

–

HOA

–

LPOM /LSUT (the last is not available in this release)

–

HPOM /HSUT (the last is not available in this release)

Cross connection functions (MSP, HPC and LPC) are performed by the two MATRIX boards (working in 1+1 configuration). The TTF block is connected to the two MATRIX boards through 1+1 bidirectional links at 622 Mbit/s , STM–4 equivalent capacity. HOA block is connected both to the HPC matrices and to the LPC matrices on the two MATRIX boards through a couple of 1+1 links at 622 MBit/s working in protection, STM–4 equivalent capacity. Backpanel interface supply a system–clock to the G.A. internal circuits. In the following block description, the new naming convention of the G.783 is reported. Refer to para. 3.3.2 on page 196 for details. The G.A. send and receive one STM–4 signal (data + clock) at 622 Mbit/s to/from the SPI The SPI can detect an external LOS from the input line . The optical transmitter provides to the G.A. its status by means of two input signals: Laser Degrade and Laser Failure. The ALS algorithm is hardware implemented and the G.A. provides the Laser shut Down command. On the front panel of the unit a push–button is available for manual laser restart. TTF BLOCK (SPI, RST, MST, MSA) This block performs the Transport Terminal Functions (sink on Input side, source on Output side) for the STM–4 signal. TTF block provides the T1 timing references at 2 MHz , derived from the STM–4 input signals

1AA 00014 0004 (9007) A4 – ALICE 04.10

INPUT side : from line to MSP MATRIX SPI (OSn/RSn_A_Sk) : it descramblers the incoming signal , counts the OOF and reveals the LOF alarm. RST (RSn_TT_Sk) : performs frame alignment detection (A1, A2) , regenerator section trace recovery (J0) and mismatch detection, BIP–8 Errored Block count.

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MSA (MSn/Sn_A_Sk) : performs AU4’s pointer interpretation, LOP and AIS detection, pointer justification. Moreover the following functions are performed on the Rx side : SOH BYTE extraction (Rx side): DCC bytes (DCCR D1–D3 and DCCM D4–D12) are dropped and serialized in a DCC frame. Two DCC frames are generated working in 1+1 protection. TP byte insertion (Rx side) : since the cross connection functions are centralized , for protection purpose TSD (Trail Signal Degrade) and TSF (Trail Signal Failure) are transmitted towards the two MATRIX board. K BYTES insertion and extraction (Rx side) : this block provides the in–band transmission of K1,K2, bytes towards the MATRIX board. For each of the 4 STM–1 streams, the bytes are extracted form the line when a TSF is received and transmitted towards the two MATRIX board. OUTPUT side : from MATRIX to line MSA (Ms/Sn_A_So) : it performs AUG assembly, AU–4 pointer generation, AU–AIS generation. The four AUG structure are byte interleaved in the STM–4 structure with fixed phase relationship vs. the same multiple signal. MST (MSn_TT_So) : it performs BIP–24 calculation and insertion, MS–REI MS–RDI and MS–AIS insertion. RST (RSn_TT_So) : it performs frame alignment insertion, regenerator section path trace insertion, BIP–8 calculation and insertion. SOH BYTE insertion (Tx side): DCC bytes (DCCR D1–D3 and DCCM D4–D12) coming from the DCC frames are inserted into the SOH section. K BYTES insertion and extraction (Tx side) : K1, K2 bytes are extracted from the frame coming from backpanel and re–inserted on the same output line frame . HOA BLOCK (HPT, HPA) From HPC matrix to LPC matrix HPT (Sn_TT_Sk) : path trace information is recovered, REI information is recovered, HP–RDI and UNEQ are detected, VC4 BIP–8 errored count block. TSF is applied if SSF or UNEQ or TIM or AIS is detected. TSD is applied if a condition of signal degrade is detected. Moreover : F2 F3 byte extraction (Rx side) : both F2 and F3 bytes are extracted from the received flow and serialized on a DCC frame .

1AA 00014 0004 (9007) A4 – ALICE 04.10

N1 byte extraction (Rx side) : for the network Tandem Connection Termination & Monitoring function (TCT/TCM). HPA (Sn/Sm_A_Sk) : VC–4 disassembly, TU pointer interpretation, LOP and TU–AIS detection, HP–SLM and LOM detection.

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MST (MSn_TT_Sk) : performs BIP–24 errored block count, MS–REI recovery, MS–RDI and MS–AIS detection. TSD is applied in case of MS–DEG (signal degrade), TSF is applied if MS–AIS is detected.

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From LPC matrix to HPC matrix HPA (Sn/Sm_A_So) : VC4 assembly, TU pointer generation, TU–AIS generation , signal label insertion, HPT (Sn_TT_So) : path trace identification insertion, RDI and REI indications insertion, VC–4 BIP–8 calculation and insertion. Moreover: F2 and F3 byte insertion (Tx side) : F2/F3 bytes are inserted on the DCC frame N1 byte insertion (Tx side) : for the network Tandem Connection Termination & Monitoring function (TCT/TCM). The G.A. provides also the HSUT, HPOM, (alternative) and LSUT, LPOM functions (alternative) both in Rx and Tx side. The main task of HSUT are: RX side (from MSA to HPC matrix): • • • • •

path trace information recovery REI recovery HP–RDI detection (path status monitoring UNEQ and VC–AIS detection (signal label monitoring) VC4 BIP–8 Errored Block count

Tx side: (from HPC matrix to MSA) • • • •

generation of an unequipped container ”unequipped” insertion, trail trace identifier generation RDI and /or REI information generation VC–4 BIP–8 calculation and insertion

The main task of HPOM are: RX and TX side: • • • • • • •

signal termination J1 path recovering REI information recovering HP–RDI detection (path status monitoring UNEQ and VC–AIS detection (signal label monitoring) VC4 BIP–8 Errored Block count TSF is generated in case of SSF , UNEQ, TIM , AIS . TSD is generated in case of SD

The main tasks of LSUT are :

1AA 00014 0004 (9007) A4 – ALICE 04.10

RX side (from HPA to LPC matrix): • • • •

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recovering of VC–m unequipped signal label path trace recovering BIP–2 recovery REI and RDI recovery

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Tx side (from LPC matrix to HPA ): • • • •

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insertion of VC–m unequipped signal label path trace insertion BIP–2 insertion REI and RDI insertion

LSUT is used to monitor unequipped path trails . The main tasks of LPOM are : • • • •

trace identifier monitoring RDI and REI recovering and deriving for performance primitives signal label monitoring VC–m BIP–2 errored block count

LPOM is used for performance monitoring purposes. Other functions implemented are : •

RIBUS I/F This block is used to read/write from/to the ”RIBUS” stream, to control the LED on the unit, to release the Management–bus in case of power failure, and to use the remote inventory. RIBUS I/F is powered by the + 3.3 Vdc supply by CONGI boards.

•

REMOTE INVENTORY It is the memory containing the board information, for identification purposes (see para. 3.17 on page 358 for details).

•

M–BUS Driver It drives the input–output gates of the Management–bus. These drivers can be disabled (by the Bus–OFF signal) in case of power failure.

1AA 00014 0004 (9007) A4 – ALICE 04.10

DC/DC CONVERTERS This block converts the 48/60 V power supply to the following voltages:

ED

•

3.3 V and 2.5 V used to supply all the components in the board.

•

–5.2 V to supply the optical module The DC/DC converter is synchronized with a synchronization clock at 300 MHz (signal Power–Sync, generated by G.A.) in order to avoid EMI problems.

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System–clock a

G.A. HOA

to/from LPC matrix (L Link)

HPA

LPOM LSUT (*)

F2, F3

OPTICAL INTERFACE

OPTICAL INPUT/ OUPUT

TTF K1,K2 Tx side Insertion

STM–4 SPI

HPOM HSUT (*)

LOS LASER D. LASER F. LASER OFF

RST

to/from HPC matrix (H Link)

MST

DCCR RSOH

FROM/TO MATRIX MAIN AND SPARE

to/from HPC matrix (X Link)

HPT

K1,K2,TP Rx side Insertion

MSA

DCCM MSOH

T1

DCC AUX F2, F3

FROM/TO SERVICE

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System–clock b

Config. & Status

CMISS

Bus–OFF Remote Inventory

Power Sync –5.2 V 3.3 V 2.5 V

RIBUS

RIBUS I/F

ID

Unit Failure

+3.3 Vdc

48/60 V

DC/DC CONVERTERS

FROM/TO MATRIX MAIN AND SPARE

Laser Restart

Management Bus

M–BUS Driver

FROM CONGI A & B

622 MHz OSC

STM–4 OPTICAL PORT

Notes:

1AA 00014 0004 (9007) A4 – ALICE 04.10

(*) –

HSUT and LSUT are not available in the current release

Figure 255. STM–4 –block diagram

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4.26 4 x STM–4 optical port (P4S4N)

The 4 x STM–4 port can processes up to four STM–4 streams but only two can be terminated so only two can be used. A maximum of two optical modules can be housed on the card to give physical access to the STM–4 signal. The SDH functions required to manage STM–4 signal are implemented by the GAs mounted on the board. It interfaces the two MATRIX cards via backpanel. For simplicity the following description is related only to one of the four STM–4 interfaces that can be process by the card . Referring to the ITU–T G.783 Rec., the GA performs the following functions: TTF and HPOM / HSUT . Cross connection functions (MSP, HPC) are performed by the two MATRIX boards (working in 1+1 configuration). The TTF block is connected to the two MATRIX boards through 1+1 bidirectional links at 622 Mbit/s, STM–4 equivalent capacity. In the following block description, the new naming convention of the G.783 is reported.

1AA 00014 0004 (9007) A4 – ALICE 04.10

The G.A. send and receive STM–4 signals (data + clock) at 622 Mbit/s to/from the SPI. The SPI can detect an external LOS from the input line. The optical transmitter provides to the G.A. its status by means of two input signals: Laser Degrade and Laser Failure.

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Note: this board does not support Low Order traffic termination

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TTF BLOCK (SPI, RST, MST, MSA) This block performs the Transport Terminal Functions (sink on Rx side, source on Tx side) for the STM–4 signal. TTF block provides the T1 timing references at 2 MHz, derived from the STM–4 input signals. INPUT side : from line to MSP MATRIX SPI (OSn/RSn_A_Sk) : it descramblers the incoming signal, counts the OOF and reveals the LOF alarm. RST (RSn_TT_Sk) : performs frame alignment detection (A1, A2), regenerator section trace recovery (J0) and mismatch detection, BIP–8 Errored Block count. MST (MSn_TT_Sk) : performs BIP–24 errored block count, MS–REI recovery, MS–RDI and MS–AIS detection. TSD is applied in case of MS–DEG (signal degrade), TSF is applied if MS–AIS is detected. MSA (MSn/Sn_A_Sk) : performs AU4’s pointer interpretation, LOP and AIS detection, pointer justification. Moreover the following functions are performed on the Rx side: SOH BYTE extraction (Rx side) : DCC bytes (DCCR D1 BD3 and DCCM D4 BD12) are dropped and serialized in a DCC frame. Two DCC frames are generated working in 1+1 protection. TP byte insertion (Rx side) : since the cross connection functions are centralized, for protection purpose TSD (Trail Signal Degrade) and TSF (Trail Signal Failure) are transmitted towards the two HCMATRIX boards. K BYTES insertion and extraction (Rx side) : this block provides the in–band transmission of K1, K2, bytes towards the MATRIXE board. For each of the 4 STM–1 streams, the bytes are extracted form the line when a TSF is received and they are overwritten into the SOH section. OUTPUT side : from MATRIX to line MSA (Ms/Sn_A_So) : it performs AUG assembly, AU–4 pointer generation, AU–AIS generation. The four AUG structure are byte interleaved in the STM–4 structure with fixed phase relationship vs. the same multiple signal. MST (MSn_TT_So) : it performs BIP–24 calculation and insertion, MS–REI MS–RDI and MS–AIS insertion. RST (RSn_TT_So) : it performs frame alignment insertion, regenerator section path trace insertion, BIP–8 calculation and insertion. SOH BYTE insertion (Tx side) : DCC bytes (DCCR D1BD3 and DCCM D4 BD12) coming from the DCC frames are inserted into the SOH section.

1AA 00014 0004 (9007) A4 – ALICE 04.10

K BYTES insertion and extraction (Tx side) : K1, K2 bytes are extracted from the frame coming from backpanel and re–inserted on the same output line frame.

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HPOM, HSUT block

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The GA provides also the HSUT, HPOM (alternative) both in RX and TX side. The main task of HSUT are: RX side (from MSA to HPC matrix): • • • • •

path trace information recovery REI recovery HP–RDI detection (path status monitoring UNEQ and VC–AIS detection (signal label monitoring) VC4 BIP–8 Errored Block count

TX side (from HPC matrix to MSA): • • • •

generation of an unequipped container ”unequipped” insertion, trail trace identifier generation RDI and /or REI information generation VC–4 BIP–8 calculation and insertion

The main task of HPOM are: RX and TX side:

1AA 00014 0004 (9007) A4 – ALICE 04.10

• • • • • • •

ED

signal termination J1 path recovering REI information recovering HP–RDI detection (path status monitoring UNEQ and VC–AIS detection (signal label monitoring) VC4 BIP–8 Errored Block count TSF is generated in case of SSF, UNEQ, TIM, AIS. TSD is generated in case of SD.

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Other functions

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Other functions implemented are: •

RIBUS I/F This block is used to read/write from/to the ”RIBUS” stream, to control the LED on the unit, to release the Management–bus in case of power failure, and to use the remote inventory.

•

REMOTE INVENTORY It is the memory containing the board information, for identification purposes (see para. 3.17 on page 358 for details).

•

M–BUS Driver It drives the input–output gates of the Management–bus. These drivers can be disabled (by the Bus–OFF signal) in case of power failure.

•

DC/DC CONVERTERS This block converts the –48/–60 V power supply to the following voltages: •

3.3V and 2.5V used to supply all the components in the board

•

–5.2Vto supply the optical module

1AA 00014 0004 (9007) A4 – ALICE 04.10

The DC/DC converter is synchronized with a synchronization clock at 300 MHz (signal Power–Sync, generated by GA) in order to avoid EMI problems.

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System–clock a

OPTICAL INPUT/ OUPUT #1

OPTICAL INTERFACE

TTF #1 K1,K2 Tx side Insertion

STM–4 SPI

LOS LASER D. LASER F.

OPTICAL INPUT/ OUPUT #2

HPOM HSUT

RST

DCCR RSOH

MST

.

MSA

DCCM MSOH

to/from HPC matrix K1,K2,TP Rx side Insertion

TTF #2 TTF #3 (not used)

DCC

from/to SERVICE

TTF #4 (not used)

Config. & Status Laser Restart

from/to MATRIX MAIN AND SPARE

Management Bus

M–BUS Driver

Bus–OFF Remote Inventory

Power Sync –5.2 V 3.3 V 2.5 V

DC/DC CONVERTERS

RIBUS

RIBUS I/F

ID

Unit Failure

48/60 V

from CONGI A & B

622 MHz OSC

1AA 00014 0004 (9007) A4 – ALICE 04.10

4xSTM–4 OPTICAL PORT

Figure 256. 4xSTM–4 optical port block diagram

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G.A.

from/to MATRIX MAIN AND SPARE

System–clock b

4.27 STM–16 optical port

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(See Figure 257. on page 464) The description is applicable to all the STM–16 optical ports of this release; up to four STM–16 optical port can be inserted in 1660SM. The units can be distinguished by letters L, S and I defining their dependance on optical components used for Long distance, Short distance or Intra Office. The Input/output unit optical connectors can be accessed from the unit’s front coverplate. The units which operate in the second window are indicated with 16.1, those operating in the third window with 16.2. The units are identified by the type of connector used: –

SFF

–

SFP plug–in module (”colored” or “Black and White”)

–

FC/PC

–

SC/PC

–

SC/SPC

The units identified by JE (Joint engineering) have better optical characteristics, typically for the dispersion values and sensitivity (see Table 66. on page 595). The STM–16 with ”192.3 to 195.7” indication (also defined ”colored”), are used when interfaced with WDM equipment. That number indicates the central frequency (in Thz) of the carrier optical signal, related to the wavelength. These sixteen units are independently characterized by different wavelength. The WDM equipment must receive up to sixteen different wavelength signals from sixteen different STM–16 optical port. The SDH functions required to manage STM–16 signal are implemented by four G.A. ( G.A#1 to G.A.#4 in Figure 257. on page 464) mounted on the board. They interface the two MATRIX boards via backpanel.

1AA 00014 0004 (9007) A4 – ALICE 04.10

Another G.A. (G.A.#5 in Figure 257. on page 464) is present with MUX/DEMUX and loop functions. This G.A. interface the line side with one stream at 2488 Mbit/s an the equipment side with four stream at 622 Mbit/s.

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• •

Line loop Internal loop

Referring to the ITU–T G.783 recommendation, the four G.A. performs the following functions : –

TTF (only the G.A. #1 )

–

HOA (all G.A. from 1 to 4)

–

LPOM /LSUT (all G.A. from 1 to 4). The last is not available in this release

–

HPOM /HSUT ( only the G.A.#1). The last is not available in this release

Cross connection functions (MSP, HPC and LPC) are performed by the two MATRIX boards (working in 1+1 configuration). The TTF block is connected to the two MATRIX boards through four bidirectional links at 622 Mbit/s in 1+1 configuration (H link). HOA block is connected both to the HPC matrices and to the LPC matrices on the two MATRIX boards through two bidirectional link at 622 MBit/s each in 1+1 configuration (”X link” and “L link” respectively) . Backpanel interface supply a system–clock (SYST CK) to the G.A. internal circuits In the following block description, the new naming convention of the G.783 is reported. Refer to para. 3.3.2 on page 196 for details. The G.A.#1 send and receive four 622 Mbit/s signal (data + clock) to/from the G.A.#5 The SPI can detect an external LOS from the input line . The optical transmitter provides to the G.A. its status by means of two input signals: Laser Degrade and Laser Failure. The ALS algorithm is hardware implemented and the G.A. provides (LASER OFF).

the Laser shut Down command

On the front panel of the unit a push–button is available for manual laser restart. TTF BLOCK (SPI, RST, MST, MSA) This block performs the Transport Terminal Functions (sink on Input side, source on Output side) for the STM–16 signal. TTF block provides the T1 timing references at 2 MHz , derived from the STM–16 input signals INPUT side : from line to MSP MATRIX SPI (OSn/RSn_A_Sk) : it descramblers the incoming signal , counts the OOF and reveals the LOF alarm.

1AA 00014 0004 (9007) A4 – ALICE 04.10

RST (RSn_TT_Sk) : performs frame alignment detection (A1, A2) , regenerator section trace recovery (J0) and mismatch detection, BIP–8 Errored Block count. MST (MSn_TT_Sk) : performs BIP–24 errored block count, MS–REI recovery, MS–RDI and MS–AIS detection. TSD is applied in case of MS–DEG (signal degrade), TSF is applied if MS–AIS is detected.

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Two types of loops are possible inside G.A.#5:

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MSA (MSn/Sn_A_Sk) : performs AU4’s pointer interpretation, LOP and AIS detection, pointer justification. Sixteen MSA blocks are present. Moreover the following functions are performed on the Input side : SOH BYTE extraction (Rx side): DCC bytes (DCCR D1–D3 and DCCM D4–D12) are dropped and serialized in a DCC frame. Two DCC frames are generated working in 1+1 protection. TP byte insertion (Rx side) : since the cross connection functions are centralized , for protection purpose TSD (Trail Signal Degrade) and TSF (Trail Signal Failure) are transmitted towards the two MATRIX board. K BYTES insertion and extraction (Rx side) : this block provides the in–band transmission of K1,K2, bytes towards the MATRIX board. The bytes are extracted from the line when a TSF is received and they are transmitted towards the two MATRIX board. OUTPUT side : from MATRIX to line MSA (Ms/Sn_A_So) : it performs AUG assembly, AU–4 pointer generation, AU–AIS generation. The sixteen AU4 structure are byte interleaved in the STM–16 structure with fixed phase relationship vs. the same multiple signal. MST (MSn_TT_So) : it performs BIP–24 calculation and insertion, MS–REI MS–RDI and MS–AIS insertion. RST (RSn_TT_So) : it performs frame alignment insertion, regenerator section path trace insertion, BIP–8 calculation and insertion. SOH BYTE insertion (Tx side): DCC bytes (DCCR D1–D3 and DCCM D4–D12) coming from the DCC frames are inserted into the SOH section. K BYTES insertion and extraction (Tx side) : K1, K2 bytes are extracted from the frame coming from backpanel and re–inserted on the same output line frame . HOA BLOCK (HPT, HPA) From HPC matrix to LPC matrix HPT (Sn_TT_Sk) : path trace information is recovered, REI information is recovered, HP–RDI and UNEQ are detected, VC4 BIP–8 errored count block. TSF is applied if SSF or UNEQ or TIM or AIS is detected. TSD is applied if a condition of signal degrade is detected. Moreover : F2 F3 byte extraction (Rx side) : both F2 and F3 bytes are extracted from the received flow and serialized on a DCC frame . N1 byte extraction (Rx side) : for the network Tandem Connection Termination & Monitoring function (TCT/TCM).

1AA 00014 0004 (9007) A4 – ALICE 04.10

HPA (Sn/Sm_A_Sk) : VC–4 disassembly, TU pointer interpretation, LOP and TU–AIS detection, HP–SLM and LOM detection.

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HPA (Sn/Sm_A_So) : VC4 assembly, TU pointer generation, TU–AIS generation , signal label insertion, HPT (Sn_TT_So) : path trace identification insertion, RDI and REI indications insertion, VC–4 BIP–8 calculation and insertion. Moreover: F2 and F3 byte insertion (Tx side) : F2/F3 bytes are inserted on the DCC frame N1 byte insertion (Tx side) : for the network Tandem Connection Termination & Monitoring function (TCT/TCM). The G.A. provides also the HSUT, HPOM, (alternative) and LSUT, LPOM functions (alternative) both in Rx and Tx side. The main task of HSUT are: RX side (from MSA to HPC matrix): • • • • •

path trace information recovery REI recovery HP–RDI detection (path status monitoring UNEQ and VC–AIS detection (signal label monitoring) VC4 BIP–8 Errored Block count

Tx side: (from HPC matrix to MSA) • • • •

generation of an unequipped container ”unequipped” insertion, trail trace identifier generation RDI and /or REI information generation VC–4 BIP–8 calculation and insertion

The main task of HPOM are: RX and TX side: • • • • • • •

signal termination J1 path recovering REI information recovering HP–RDI detection (path status monitoring UNEQ and VC–AIS detection (signal label monitoring) VC4 BIP–8 Errored Block count TSF is generated in case of SSF , UNEQ, TIM , AIS . TSD is generated in case of SD

The main tasks of LSUT are :

1AA 00014 0004 (9007) A4 – ALICE 04.10

RX side (from HPA to LPC matrix): • • • •

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recovering of VC–m unequipped signal label path trace recovering BIP–2 recovery REI and RDI recovery

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From LPC matrix to HPC matrix

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Tx side (from LPC matrix to HPA ): • • • •

insertion of VC–m unequipped signal label path trace insertion BIP–2 insertion REI and RDI insertion

LSUT is used to monitor unequipped path trails . The main tasks of LPOM are : • • • •

trace identifier monitoring RDI and REI recovering and deriving for performance primitives signal label monitoring VC–m BIP–2 errored block count

LPOM is used for performance monitoring purposes. Other functions implemented are : •

RIBUS I/F This block is used to: – read/write from/to the ”RIBUS” stream – control the LED on the unit – release the Management–bus in case of power failure – read remote inventory data. RIBUS I/F is powered by the + 3.3 Vdc supply by CONGI boards.

•

TONE MODULATOR MANAGEMENT This block is used by the STM–16 optical port with ”192.3 to 195.7” indication. In this block is present a”WDM tone generator”, which starting from the data written in the remote inventory, fix the appropriate wavelength transmitted to the WDM equipment.

•

REMOTE INVENTORY It is the memory containing the board information, for identification purposes (see para. 3.17 on page 358 for details) and additional data for operation of the board in WDM application.

•

M–BUS Driver It drives the input–output gates of the Management–bus. These drivers can be disabled (by the Bus–OFF signal) in case of power failure.

•

DC/DC CONVERTERS This block converts the 48/60 V power supply to the following voltages:

1AA 00014 0004 (9007) A4 – ALICE 04.10

– – – –

+ 2.5 V + 3.3 V –5V +5V

The DC/DC converter is synchronized with a synchronization clock at 300 MHz (signal Power Sync) , generated by G.A.#1) in order to avoid EMI problems.

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SYST CK A/B

G.A.#1 HPT

CK Power Sync

to/from LPC matrix

HOA HPA

4 x 622 Mbit/s

G.A.#5 MUX / DEMUX

K1,K2 Tx side Insertion

F2, F3

RST

MST

HPOM (*) HSUT K1,K2,TP Rx side Insertion

MSA

DCCR DCCM RSOH MSOH

to/from HPC matrix (H link) to/from HPC matrix (H link)

MSA

Line loop Internal loop

to/from HPC matrix

(H link)

to/from HPC matrix

(H link)

MSA

LOS LASER D. LASER F. LASER OFF

AUX F2, F3 Tone

G.A.#2 HPT HOA CK

HPA

SYST CK A/B to/from HPC matrix ( X link) to/from LPC matrix (L link) LPOM (*) LSUT

F2, F3

G.A.#3 HPT

1AA 00014 0004 (9007) A4 – ALICE 04.10

Notes: (*) – HSUT and LSUT are not operative in current release

CK HOA

HPA

SYST CK A/B to/from HPC matrix ( X link) to/from LPC matrix (L link)

Tone

LPOM (*) LSUT F2, F3

Tone modulator management

G.A.#4

Line loop Internal loop

HOA HPA

AUX

F2, F3

SYST CK A/B to/from HPC matrix ( X link) to/from LPC matrix (L link) LPOM (*) LSUT

Bus–OFF

F2, F3

F2, F3

AUX

from/to SERVICE

from/to SERVICE

from/to SERVICE

ID RIBUS I/F

RIBUS +3.3 Vdc

Unit Failure

HPT

CK M–BUS Driver

Remote Inventory

AUX

F2, F3

from/to MATRIX main and spare

DCC

from/to SERVICE

MSA

from/to MATRIX main and spare

O/E SPI

LPOM (*) LSUT

TTF

from/to MATRIX main and spare

2488 Mbit/s OPTICAL INPUT/ OUPUT

(L link)

STM–16 OPTICAL PORT

2.5 V 3.3 V 5V –5 V

Power Sync DC/DC CONVERTERS

48/60 V +3.3 Vdc

from CONGI

Figure 257. STM–16 optical port block diagram

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Laser Restart

T1 to/from HPC matrix ( X link)

from/to MATRIX main and spare

622 MHz OSC

4.28 ISA – ATM MATRIX 4X4 (ATM4X4)

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(See Figure 258. on page 471) This unit realize an ATM switching matrix with a total bandwidth of 622Mbit/s. The board is able to manage up to 16 LT where LT is a physical or logical channel where is mapped an ATM flow (E1, E3, VC12, VC3, VC4). On the board a local STM–1 access carrying an unstructured VC4 is managed. The card perform the following functions: [1]

SDH signal processing

[2]

ATM signal processing

[3]

MATRIX

[4]

MICROPROCESSOR

[5]

Common part

[1] SDH signal processing One STM–1 interface is available on the card. The stream can be optical or electrical according to the modules available (electrical–STM1 or optical–STM1) inserted into the front cover cavity of the ATM MATRIX 4X4. The proprietary function of ”Bidirectional working on single fiber” is provided, by presetting. This function uses the BMD (bad media dependent) byte. The BMD alarm is considered as an external LOS. The ALS algorithm is provided by hardware implementation (Laser–Shut–Down command). The line–interface (SPI) is performed by the pluggable module (line–module). LOS, Laser–Degrade, Laser–fail alarms and Laser–Shut–Down commands are comprised in the Alarms&Commands group in the figure. The SDH functions required to manage STM–1 signals are: – – –

SPI, RST, MST, MSA HPT, LPT and LPA. SOH bytes

Cross connection functions (MSP, HPC and LPC) are performed by the matrices present on the two MATRIXN board (working in 1+1 configuration). The MSA block is connected to the MATRIXN boards (main and spare) through 1+1 bidirectional links at 622 Mbit/s , STM–4 equivalent capacity. SPI, RST, MST, MSA BLOCK

1AA 00014 0004 (9007) A4 – ALICE 04.10

These blocks performs the Transport Terminal Functions (sink on Rx side, source on Tx side) for STM–1 signals.

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SPI (OSn/RSn_A_Sk) : it descramblers the incoming signal , counts the OOF and reveals the LOF alarm. RST (RSn_TT_Sk) : performs frame alignment detection (A1, A2) , regenerator section trace recovery (J0) and mismatch detection, BIP–8 Errored Block count. J0 is not managed in this release. MST (MSn_TT_Sk) : performs BIP–24 errored block count, MS–REI recovery, MS–RDI and MS–AIS detection. TSD is applied in case of MS–DEG (signal degrade), TSF is applied if MS–AIS is detected. MSA (MSn/Sn_A_Sk) : performs AU4 pointer interpretation, LOP and AIS detection, pointer justification. Moreover the following functions are performed on the Rx side : SOH BYTE extraction (Rx side): DCC bytes (DCCR D1–D3 and DCCM D4–D12) are dropped and serialized in a DCC frame. Two DCC frames are generated working in 1+1 protection. Tx side : from matrix on the MATRIXN to line MSA (Ms/Sn_A_So) : it performs AUG assembly, AU–4 pointer generation, AU–AIS generation. MST (MSn_TT_So) : it performs BIP–24 calculation and insertion, MS–REI MS–RDI and MS–AIS insertion. RST (RSn_TT_So) : it performs frame alignment insertion, regenerator section path trace insertion, BIP–8 calculation and insertion. SOH BYTE insertion (Tx side): DCC bytes (DCCR D1–D3 and DCCM D4–D12) coming from the DCC frames are inserted into the SOH section. SPI (OSn/RSn_A_So) :it scramblers the outgoing signals and insert AIS in alarm condition.

HPT, LPT and LPA blocks Two data stream at frequency of 622 MHz are connected to the block called SWITCH in Figure 258. on page 471, one coming from HPC matrix ( L link) and one from LPC matrix (X link). Rx side: from matrix on MATRIXN to LPA or HPT The task of the SWITCH block is to select one of the two busses coming from the matrices according to the type of signal to be connected ( L if is structured or X if unstructured). If the signal is structured the incoming signal (L Link) is sent through the SWITCH to the LPT and LPA block.

1AA 00014 0004 (9007) A4 – ALICE 04.10

•

ED

LPT (S12_TT_Sk): The LPT function terminates and processes the POH to determine the status of the defined path attributes. • J2: trail trace identifier is recovered ––> TIM detection. • V5[1,2]: BIP–2 is recovered ––> Ex–BER, Signal Degrade alarm • V5[3]: REI bit is recovered and the derived performance primitives is reported. • V5[8]: RDI information is recovered and reported. • AIS or SSF detection ––> SSF alarm

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Rx side : from line to MSP matrix on the MATRIXN board

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•

LPA (S12/P12x_A_Sk): It extracts the VC12–POH and processes the TU12 pointer. • V5[5–7]: Signal label detection in the byte V5[5–7] ––> Signal label Mismatch detection • AIS or SSF is applied if Signal label Mismatch is detected

If the signal is unstructured the incoming signal (L Link) is sent through the SWITCH to the HPT block. HPT (Sn_TT_Sk) : path trace information is recovered, REI information is recovered, HP–RDI and UNEQ are detected, VC4 BIP–8 errored count block. TSF is applied if SSF or UNEQ or TIM or AIS is detected. TSD is applied if a condition of signal degrade is detected. N1 byte extraction (Rx side): for the network Tandem Connection Termination & Monitoring function (TCT/TCM).

Tx side: from LPA or HPT to matrix on MATRIXN The task of the SWITCH block is to sent the signal coming from HPT or LPT block towards the matrices on the MATRIXN. The selection is made according to the type of signal to be connected ( L if is structured or X if unstructured). If the signal is structured the datas coming from ATM MAPPING block are sent through the LPT and LPA blocks towards the SWITCH block. •

LPA (S12/P12x_A_So) : This block adapts user data for transport in the synchronous domain. For asynchronous user data, lower order path adaptation involves bit justification. The 2.048 Mbit/s is inserted into a C–12 container (by means of asynchronous mapping), which is synchronized (stuffing) with the correspondent TU–12. • V5[5–7]: Signal label insertion in the byte V5[5–7].

•

LPT (S12_TT_So) : The LPT function creates a VC–12 by generating and adding POH to a C–12. The POH formats are defined in Recommendations G.708 and G.709. • J2: trail trace identifier is generated. • V5[1,2]: BIP–2 is calculated and transmitted. • V5[3]: the number of errors is encoded in REI. • V5[8]: RDI indication is inserted.

If the signal is unstructured the datas coming from ATM MAPPING block are sent through the HPT block to the SWITCH block. HPT (Sn_TT_So) : path trace identification insertion, RDI and REI indications insertion, VC–4 BIP–8 calculation and insertion, signal label insertion. N1 byte insertion (Tx side): for the network Tandem Connection Termination & Monitoring function (TCT/TCM).

HPOM, HSUT BLOCK (HSUT is not operative in this release) HPOM performs the monitoring of an equipped path while HSUT performs the termination of an unequipped path. 1AA 00014 0004 (9007) A4 – ALICE 04.10

From HPOM and HSUT are recovered : • •

the primitives used for Performance Monitoring (Errored block count, Defect seconds) switching criteria for SNCP/N protection

The two functions are alternative.

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Snm_TT_Sk : signal termination , J1 path recovering , REI information recovering, HP–RDI detection (path status monitoring) , UNEQ and VC–AIS detection (signal label monitoring), VC4 BIP–8 Errored Block count. TSF is generated in case of SSF , UNEQ, TIM , AIS . TSD is generated in case of SD. HSUT (Higher order Supervisory Unequipped termination) Sns_TT_Sk : path trace information recovery, REI recovery, HP–RDI detection (path status monitoring), UNEQ and VC–AIS detection (signal label monitoring), VC4 BIP–8 Errored Block count. Sns_TT_So : generation of an unequipped container , ”unequipped” insertion, trail trace identifier generation, RDI and /or REI information generation, VC–4 BIP–8 calculation and insertion.

[2] ATM signal processing

1AA 00014 0004 (9007) A4 – ALICE 04.10

RX side from SDH to MATRIX: –

ATM DEMAPPING: this block extract the ATM cells from the transmission path payload E1, E3, VC3, VC4, VC4c; ATM DEMAPPING BLOCK receive the E1 and E3 frames contained in VC3 and VC4 payload for the processing performed in the equipment boards.

–

CELL DELINEATION : cell delineation is the process which allow the identification of the cell boundaries. It is performed on the cell stream extracted from the PDH/SDH frames

–

DESCRAMBLER:for SDH and PDH the information field of each cell is descrambled with a self synchronizing scrambler polynomial; descrambler is enable for a number of bit s equal to the length of the information field, and again disabled for the following assumed header.

–

HEC VERIFICATION AND CORRECTION: in this block HEC field in the cell header is checked; HEC is used to achieved cell delineation. The algorithm used can recover a single–bit error or detect headers with single and multi–bit errors.

–

CELLs DECOUPLING: idle cells are extracted from the cell stream. Idle cells has been inserted in the far end adaptation source function to reach the synchronous container capacity.

–

HEADER VERIFICATION: this function verifies that the first four octets of the ATM cell header are recognizable as being a valid header pattern. Cells with unrecognized header patterns are discarded. An indication of invalid header cell discard event is provided to the microprocessor interface where are counted.

–

UPC/NPC:this function (policing) checks that the incoming traffic from a VPC is not violating the agreed traffic contract. UPC (User Parameter Control) and NPC (Network Parameter Control) perform the same function but in different parts of the network (respectively at User Network Interface and Network Node Interface )

–

OAM: operations and maintenance function is done by using dedicated cells. Typically function are cells monitoring, cells reporting, faults localization etc.

–

HEADER TRANSLATION: this block performs on each virtual connection an header translation which consist in a conversion of the external identification number (LTI/VPI/VCI) into an an internal identification number for the user to network direction

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HPOM (Higher order path overhead monitoring)

1AA 00014 0004 (9007) A4 – ALICE 04.10

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

–

CONGESTION MANAGEMENT is the block that in the event of congestion is responsible to assure that cell with loss priority will be discarded before than cell with high priority.

–

TRAFFIC SHAPING:this function enhances the utilization of the buffer and matrix providing better switch performance, especially for burst data.

TX side from MATRIX to SDH: –

RATE REDUCTION: The purpose of this block is to smooth the average 622 Mbits/s traffic entering with bursts up to 1,2 Gb/s. This function uses four waiting queues, called Rate Reduction FIFOs, used to manage four priority levels fixed on a per connection basis. They are written at 1,2 Gbits/s and read at 622 Mbits/s.

–

MULTICAST: it is a replication function of the incoming cell towards n outgoing directions; a new connection identifier is used for each replication.

–

ROUTING:The purpose of this function is to guide the cells towards their target LT

–

CONGESTION MANAGEMENT: is the block that in the event of congestion is responsible to assure that cell with loss priority will be discarded before than cell with high priority.

–

TRAFFIC SHAPING: the traffic shaping function modifies the characteristics of cells stream in a VCP in order to improve network efficiency. It allows for meeting traffic contract at the egress of the equipment. The shaping function can correct the Cell Delay Variation generated by the buffer and the matrix.

–

HEADER TRANSLATION:this block performs on each virtual connection an header translation which consist in a conversion of the internal identification number into the external identification number (LTI/VPI/VCI)for the network to user direction.

–

OAM:operations and maintenance function is done by using dedicated cells.

–

CELLs RATE DECOUPLING: idle cells are inserted into cell stream to match the rate of the container.

–

HEC PROCESSING: the Header Error Control value is calculated on the entire ATM cell header and inserted in the appropriate field.

–

SCRAMBLER: information field of each cell is scrambled in order to improve security and robustness of the HEC cell delineation mechanism. In addition it helps randomizing the data in the information field for possible improvement of the transmission performance.

–

ATM MAPPING: the cell stream is inserted into transmission path payload E1, E3, VC3, VC4, VC4c; the E1 and E3 frames are sent to the output of the board mapped in VC12 and VC3 payload because of the processing that will be done in the equipment boards.

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The matrix is in charged of cross connect the incoming and outgoing cells according to the information received by the microprocessor. In case of Soft Permanent Virtual Connection ( Soft–PVC) the P–NNI signalling is supported. [4] MICROPROCESSOR The microprocessor present on the board performs the following functionality: –

configuration, alarm and status gathering of the ATM devices present on the board

–

handling of the signalling packet receive from the matrix in case of Soft–PVC

–

communication with the EC on the EQUICO (SNMP Link); using this channel performance and management date are encapsulated and sent to the EC and from there to the Craft Terminal or O.S.

All the LEDS (except that for Unit–Failure) are driven by the microprocessor. The meaning of the LEDs and Push–Button is reported in Figure 258. on page 471. [5] Common part •

RIBUS I/F This block is used to read/write from/to the ”RIBUS” stream, to control the LED on the unit, to release the Management–bus in case of power failure, and to use the remote inventory. RIBUS I/F is powered by the + 3.3 Vdc supply by CONGI boards.

•

REMOTE INVENTORY It is the memory containing the board information, for identification purposes (see para. 3.17 on page 358 for details).

•

M–BUS Driver It drives the input–output gates of the Management–bus. These drivers can be disabled (by the Bus–OFF signal) in case of power failure. DC/DC CONVERTERS Starting from the 48/60 V power supply the following voltages are generated:

1AA 00014 0004 (9007) A4 – ALICE 04.10

– –

ED

+ 5 Vdc used by the optical module +1.5 Vdc, –3.3 Vdc, –3.3 Vdc, –3.3 Vdc, +2.5 Vdc used to supply all the components in the board.

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[3] MATRIX

System clock a System clock b

HPOM HSUT(*)

MODULE STM–1 (D+CK)

H

LOS

MST

MSA HPT

622 MHz OSC

DCCR RSOH

ÉÉ ÉÉ ÉÉ

DCCM MSOH from/to

LPT

CELLs RATE DECOUPLING

HEADER VERIFICATION

HEC PROCESSING

OAM

HEADER TRANSLATION

OAM

HEADER TRANSLATION

ÉÉ ÉÉ ÉÉ

Struct/unstruct

ATM MAPPING

HEC VERIFICATION DESCRAMBLER & CORRECTION

CELLs DECOUPLING

UPC/NPC

SCRAMBLER

CELL DELINEATION

CONGESTION MANAGEMENT

TRAFFIC SHAPING

ÉÉÉÉ É ÉÉ

S W I T C H

ATM DEMAPPING

TRAFFIC SHAPING

CONGESTION MANAGEMENT

X

SPATIAL MATRIX

ROUTING

RATE REDUCTION

MULTICAST

SDRAM FLASH EPROM

LEDS(X5)

PNNI Signalling

LED TEST RESET

L

LPA

Struct/unstruct

ÉÉÉÉ ÉÉÉÉ É

MICROPROCESSOR

SNMP

Configuration & Status (ATM)

Management Bus M–BUS Driver

Configuration & Status (SDH)

CMISS Bus–OFF Remote Inventory

– 3.3V 3.3 V

DC/DC

Unit Failure

RIBUS RIBUS I/F

CONVERTERS

F

+3.3 Vdc

48/60 V

2.5 V 1AA 00014 0004 (9007) A4 – ALICE 04.10

ID

FROM CONGI

5V 1.5 V

ATM MATRIX 4X4

MATRIX MAIN AND SPARE

RST

from/to EQUICO

I/O

from/to SERVICE

from/to

E/O

AUX

SOH bytes

RSOH, MSOH, F2, F3

LASER D. LASER F. LASER OFF

MATRIX MAIN AND SPARE

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

L I N E

ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ

Figure 258. ATM 4X4 card – Block diagram

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The functional description of the board is similar to ISA ATM4X4V2 (refer to paragraph 4.30); the only differences between the two boards is the number of TPs managed. As a matter of fact ATM4X4D3 board can manage up to 16 TPs among E1, E3, VC12, VC3, VC4, T3, E1 IMA group.

4.30 ISA – ATM MATRIX 4X4 ENHANCED (ATM4X4V2) (See Figure 259. on page and 477 ) This unit realize an ATM switching matrix with a total bandwidth of 622Mbit/s. The board is able to manage up to 252 LT where LT is a physical or logical channel where is mapped an ATM flow (E1, E3, VC12, VC3, VC4, T3, E1 IMA group) On the board a local STM–1 access carrying an unstructured VC4 is managed. The card perform the following functions: [1]

SDH signal processing

[2]

ATM signal processing

[3]

MATRIX

[4]

MICROPROCESSOR

[5]

Common part

[1] SDH signal processing The SDH functions required are:

–

HPT, LPT and LPA. SOH bytes

Cross connection functions (MSP, HPC and LPC) are performed by the matrices present on the two MATRIXN board (working in 1+1 configuration). The MSA block is connected to the MATRIXN boards (main and spare) through 1+1 bidirectional links at 622 Mbit/s , STM–4 equivalent capacity.

HPT, LPT and LPA blocks Two data stream at frequency of 622 MHz are connected to the block called SWITCH in Figure 258. on page 471, one coming from HPC matrix ( H link) and one from LPC matrix (L link). Rx side: from matrix on MATRIXN to LPA or HPT

1AA 00014 0004 (9007) A4 – ALICE 04.10

The task of the SWITCH block is to select one of the two busses coming from the matrices according to the type of signal to be connected ( L if is structured or H if unstructured). If the signal is structured the incoming signal (L Link) is sent through the SWITCH to the LPT and LPA block.

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4.29 ISA – ATM MATRIX 4X4 ENHANCED (ATM4X4D3)

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•

LPT (S12_TT_Sk): The LPT function terminates and processes the POH to determine the status of the defined path attributes. • J2: trail trace identifier is recovered ––> TIM detection. • V5[1,2]: BIP–2 is recovered ––> Ex–BER, Signal Degrade alarm • V5[3]: REI bit is recovered and the derived performance primitives is reported. • V5[8]: RDI information is recovered and reported. • AIS or SSF detection ––> SSF alarm

•

LPA (S12/P12x_A_Sk): It extracts the VC12–POH and processes the TU12 pointer. • V5[5–7]: Signal label detection in the byte V5[5–7] ––> Signal label Mismatch detection • AIS or SSF is applied if Signal label Mismatch is detected

If the signal is unstructured the incoming signal (H Link) is sent through the SWITCH to the HPT block. HPT (Sn_TT_Sk) : path trace information is recovered, REI information is recovered, HP–RDI and UNEQ are detected, VC4 BIP–8 errored count block. TSF is applied if SSF or UNEQ or TIM or AIS is detected. TSD is applied if a condition of signal degrade is detected. N1 byte extraction (Rx side): for the network Tandem Connection Termination & Monitoring function (TCT/TCM).

Tx side: from LPA or HPT to matrix on MATRIXN The task of the SWITCH block is to sent the signal coming from HPT or LPT block towards the matrices on the MATRIXN. The selection is made according to the type of signal to be connected ( L if is structured or H if unstructured). If the signal is structured the datas coming from ATM MAPPING block are sent through the LPT and LPA blocks towards the SWITCH block. •

LPA (S12/P12x_A_So) : This block adapts user data for transport in the synchronous domain. For asynchronous user data, lower order path adaptation involves bit justification. The 2.048 Mbit/s is inserted into a C–12 container (by means of asynchronous mapping), which is synchronized (stuffing) with the correspondent TU–12. • V5[5–7]: Signal label insertion in the byte V5[5–7].

•

LPT (S12_TT_So) : The LPT function creates a VC–12 by generating and adding POH to a C–12. The POH formats are defined in Recommendations G.708 and G.709. • J2: trail trace identifier is generated. • V5[1,2]: BIP–2 is calculated and transmitted. • V5[3]: the number of errors is encoded in REI. • V5[8]: RDI indication is inserted.

1AA 00014 0004 (9007) A4 – ALICE 04.10

If the signal is unstructured the datas coming from ATM MAPPING block are sent through the HPT block to the SWITCH block. HPT (Sn_TT_So) : path trace identification insertion, RDI and REI indications insertion, VC–4 BIP–8 calculation and insertion, signal label insertion. N1 byte insertion (Tx side): for the network Tandem Connection Termination & Monitoring function (TCT/TCM).

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HPOM performs the monitoring of an equipped path while HSUT performs the termination of an unequipped path. From HPOM and HSUT are recovered : • •

the primitives used for Performance Monitoring (Errored block count, Defect seconds) switching criteria for SNCP/N protection

The two functions are alternative. HPOM (Higher order path overhead monitoring) Snm_TT_Sk : signal termination , J1 path recovering , REI information recovering, HP–RDI detection (path status monitoring) , UNEQ and VC–AIS detection (signal label monitoring), VC4 BIP–8 Errored Block count. TSF is generated in case of SSF , UNEQ, TIM , AIS . TSD is generated in case of SD. HSUT (Higher order Supervisory Unequipped termination) Sns_TT_Sk : path trace information recovery, REI recovery, HP–RDI detection (path status monitoring), UNEQ and VC–AIS detection (signal label monitoring), VC4 BIP–8 Errored Block count. Sns_TT_So : generation of an unequipped container , ”unequipped” insertion, trail trace identifier generation, RDI and /or REI information generation, VC–4 BIP–8 calculation and insertion.

[2] ATM signal processing

1AA 00014 0004 (9007) A4 – ALICE 04.10

RX side from SDH to MATRIX: –

ATM DEMAPPING: this block extract the ATM cells from the transmission path payload E1, E3, T3, VC3, VC4, VC4c; ATM DEMAPPING BLOCK receive the E1 and E3/T3 frames contained in VC3 and VC4 payload for the processing performed in the equipment boards.

–

CELL DELINEATION : cell delineation is the process which allow the identification of the cell boundaries. It is performed on the cell stream extracted from the PDH/SDH frames

–

DESCRAMBLER:for SDH and PDH the information field of each cell is descrambled with a self synchronizing scrambler polynomial; descrambler is enable for a number of bit s equal to the length of the information field, and again disabled for the following assumed header.

–

HEC VERIFICATION AND CORRECTION: in this block HEC field in the cell header is checked; HEC is used to achieved cell delineation. The algorithm used can recover a single–bit error or detect headers with single and multi–bit errors.

–

CELLs DECOUPLING: idle cells are extracted from the cell stream. Idle cells has been inserted in the far end adaptation source function to reach the synchronous container capacity.

–

IMA (Inverse Multiplexing over ATM) RX: NxE1 stream are bundled in a single high speed cell stream; E1 stream are collected in a cyclical fashion among physical links preserving sequence( for details on IMA refer to AF–PHY–0086.001).

–

HEADER VERIFICATION: this function verifies that the first four octets of the ATM cell header are recognizable as being a valid header pattern. Cells with unrecognized header patterns are discarded. An indication of invalid header cell discard event is provided to the microprocessor interface where are counted.

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HPOM, HSUT BLOCK (HSUT is not operative in this release)

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–

UPC/NPC:this function (policing) checks that the incoming traffic from a VPC is not violating the agreed traffic contract. UPC (User Parameter Control) and NPC (Network Parameter Control) perform the same function but in different parts of the network (respectively at User Network Interface and Network Node Interface )

–

OAM: operations and maintenance function is done by using dedicated cells. Typically function are cells monitoring, cells reporting, faults localization etc.

–

HEADER TRANSLATION: this block performs on each virtual connection an header translation which consist in a conversion of the external identification number (LTI/VPI/VCI) into an an internal identification number for the user to network direction

–

CONGESTION MANAGEMENT is the block that in the event of congestion is responsible to assure that cell with loss priority will be discarded before than cell with high priority.

–

TRAFFIC SHAPING:this function enhances the utilization of the buffer and matrix providing better switch performance, especially for burst data.

1AA 00014 0004 (9007) A4 – ALICE 04.10

TX side from MATRIX to SDH: –

RATE REDUCTION: The purpose of this block is to smooth the average 622 Mbits/s traffic entering with bursts up to 1,2 Gb/s. This function uses four waiting queues, called Rate Reduction FIFOs, used to manage four priority levels fixed on a per connection basis. They are written at 1,2 Gbits/s and read at 622 Mbits/s.

–

MULTICAST: it is a replication function of the incoming cell towards n outgoing directions; a new connection identifier is used for each replication (not operative in current release).

–

ROUTING:The purpose of this function is to guide the cells towards their target LT

–

CONGESTION MANAGEMENT: is the block that in the event of congestion is responsible to assure that cell with loss priority will be discarded before than cell with high priority.

–

TRAFFIC SHAPING: the traffic shaping function modifies the characteristics of cells stream in a VCP in order to improve network efficiency. It allows for meeting traffic contract at the egress of the equipment. The shaping function can correct the Cell Delay Variation generated by the buffer and the matrix.

–

HEADER TRANSLATION:this block performs on each virtual connection an header translation which consist in a conversion of the internal identification number into the external identification number (LTI/VPI/VCI)for the network to user direction.

–

OAM:operations and maintenance function is done by using dedicated cells.

–

CELLs RATE DECOUPLING: idle cells are inserted into cell stream to match the rate of the container.

–

IMA (Inverse Multiplexing over ATM) TX: high speed stream of ATM cells is broken up in the multiple E1 links( for details on IMA refer to AF–PHY–0086.001)

–

HEC PROCESSING: the Header Error Control value is calculated on the entire ATM cell header and inserted in the appropriate field.

–

SCRAMBLER: information field of each cell is scrambled in order to improve security and robustness of the HEC cell delineation mechanism. In addition it helps randomizing the data in the information field for possible improvement of the transmission performance.

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ATM MAPPING: the cell stream is inserted into transmission path payload E1, E3, VC3, VC4, VC4c; the E1 and E3 and T3 frames are sent to the output of the board mapped in VC12 and VC3 payload because of the processing that will be done in the equipment boards.

[3] MATRIX The matrix is in charged of cross connect the incoming and outgoing cells according to the information received by the microprocessor. In case of Soft Permanent Virtual Connection ( Soft–PVC) the P–NNI signalling is supported. [4] MICROPROCESSOR The microprocessor present on the board performs the following functionality: –

configuration, alarm and status gathering of the ATM devices present on the board

–

handling of the signalling packet receive from the matrix in case of Soft–PVC

–

communication with the EC on the EQUICO (SNMP Link); using this channel performance and management date are encapsulated and sent to the EC and from there to the Craft Terminal or O.S.

All the LEDS (except that for Unit–Failure) are driven by the microprocessor. The meaning of the LEDs and Push–Button is reported in Figure 258. on page 471. [5] Common part •

RIBUS I/F This block is used to read/write from/to the ”RIBUS” stream, to control the LED on the unit, to release the Management–bus in case of power failure, and to use the remote inventory. RIBUS I/F is powered by the + 3.3 Vdc supply by CONGI boards.

•

REMOTE INVENTORY It is the memory containing the board information, for identification purposes (see para. 3.17 on page 358 for details).

•

M–BUS Driver It drives the input–output gates of the Management–bus. These drivers can be disabled (by the Bus–OFF signal) in case of power failure. DC/DC CONVERTERS Starting from the 48/60 V power supply the following voltages are generated:

1AA 00014 0004 (9007) A4 – ALICE 04.10

–

ED

+1.5 Vdc, +3.3 Vdc, , +2.5 Vdc used to supply all the components in the board.

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–

ICP CELL

CELL STREAM

GENERATION

INSERTION

SPLITTING

IMA TX

HPT

É ÉÉÉ

LPT

CELLs RATE DECOUPLING

HEADER VERIFICATION

HEC PROCESSING

CELLs DECOUPLING

SCRAMBLER

L

LPA

Struct/unstruct

Struct/unstruct

ATM MAPPING

HEC VERIFICATION DESCRAMBLER & CORRECTION

CELL DELINEATION

S W I T C H

ATM DEMAPPING

from/to

IMA FRAME

INSERTION

H

IMA RX

UPC/NPC

OAM

HEADER TRANSLATION

OAM

HEADER TRANSLATION

CONGESTION MANAGEMENT TRAFFIC SHAPING

SPATIAL MATRIX

TRAFFIC SHAPING

CONGESTION MANAGEMENT

MATRIX MAIN AND SPARE

FILLING CELL

622 MHz OSC

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IMA TX

ROUTING

RATE REDUCTION

MULTICAST

IMA RX FILLING CELL

INVALID CELL

ICP CELL

IMA

CELL STREAM

DISCARD

DISCARD

REMOVE

SYNC

RECONSTUCTION

SDRAM FLASH EPROM

LEDS(X5)

Configuration & Status (ATM)

from/to EQUICO

ÉÉÉÉ ÉÉÉÉ É

SNMP

Management Bus from/to

M–BUS Driver

Configuration & Status (SDH)

CMISS Bus–OFF Remote Inventory

– 3.3V

ATM MATRIX 4X4

3.3 V

DC/DC

Unit Failure

RIBUS I/F

CONVERTERS

F

+3.3 Vdc

48/60 V

2.5 V 1AA 00014 0004 (9007) A4 – ALICE 04.10

ID

FROM CONGI

5V 1.5 V

RIBUS

MATRIX MAIN AND SPARE

RESET

PNNI Signalling

MICROPROCESSOR

LED TEST

Figure 259. ATM4X4V2 and ATM4X4D3 card – Block diagram

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4.31 ISA – ATM MATRIX 8X8 (ATM8X8)

This unit realize an ATM switching matrix with a total bandwidth of 1.2 Gbit/s. As a matter of fact the unit is two slot wide and it is connected with the SDH Matrix (MATRIXN) through two link at 622 Mbit/s. The block diagram of the board has been been divided in two part depicted in Figure 260. on page 483 and Figure 261. on page 484; the part A describe the common part (microprocessor, led, DC/DC converter) and the signal processing (ATM and SDH) of the first 622Mbit/s link, the part B describe the signal processing (ATM and SDH) of the second 622Mbit/s link. The board is able to manage up to 32 LT where LT is a physical or logical channel where is mapped an ATM flow (E1, E3, VC12, VC3, VC4 and VC4–4c). The card perform the following function: [1]

SDH signal processing

[2]

ATM signal processing

[3]

MATRIX

[4]

MICROPROCESSOR

[5]

Common part

[1] SDH signal processing The SDH functions are: –

HPT

–

LPT and LPA.

Cross connection functions (MSP, HPC and LPC) are performed by the matrices present on the two MATRIXN board (working in 1+1 configuration). HPT, LPT and LPA blocks Two data stream at frequency of 622 MHz are connected to the block called SWITCH in Figure 260. on page 483 , one coming from HPC matrix ( L link) and one from LPC matrix (X link); the same description can be applied to Figure 261. on page 484 that depict the part B of the board. Rx side: from matrix on MATRIXN to LPA or HPT The task of the SWITCH block is to select one of the two busses coming from the matrices according to the type of signal to be connected ( L if is structured or X if unstructured). If the signal is structured the incoming signal (L Link) is sent through the SWITCH to the LPT and LPA block.

1AA 00014 0004 (9007) A4 – ALICE 04.10

•

ED

LPT (S12_TT_Sk): The LPT function terminates and processes the POH to determine the status of the defined path attributes. • J2: trail trace identifier is recovered ––> TIM detection. • V5[1,2]: BIP–2 is recovered ––> Ex–BER, Signal Degrade alarm • V5[3]: REI bit is recovered and the derived performance primitives is reported. • V5[8]: RDI information is recovered and reported. • AIS or SSF detection ––> SSF alarm 02 3AL 91668 AA AA 636

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(See Figure 260. on page 483 and Figure 261. on page 484)

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•

LPA (S12/P12x_A_Sk): It extracts the VC12–POH and processes the TU12 pointer. • V5[5–7]: Signal label detection in the byte V5[5–7] ––> Signal label Mismatch detection • AIS or SSF is applied if Signal label Mismatch is detected

If the signal is unstructured the incoming signal (L Link) is sent through the SWITCH to the HPT block. HPT (Sn_TT_Sk) : path trace information is recovered, REI information is recovered, HP–RDI and UNEQ are detected, VC4 BIP–8 errored count block. TSF is applied if SSF or UNEQ or TIM or AIS is detected. TSD is applied if a condition of signal degrade is detected. N1 byte extraction (Rx side): for the network Tandem Connection Termination & Monitoring function (TCT/TCM).

Tx side: from LPA or HPT to matrix on MATRIXN The task of the SWITCH block is to sent the signal coming from HPT or LPT block towards the matrices on the MATRIXN. The selection is made according to the type of signal to be connected ( L if is structured or X if unstructured). If the signal is structured the datas coming from ATM MAPPING block are sent through the LPT and LPA blocks towards the SWITCH block. •

LPA (S12/P12x_A_So) : This block adapts user data for transport in the synchronous domain. For asynchronous user data, lower order path adaptation involves bit justification. The 2.048 Mbit/s is inserted into a C–12 container (by means of asynchronous mapping), which is synchronized (stuffing) with the correspondent TU–12. • V5[5–7]: Signal label insertion in the byte V5[5–7].

•

LPT (S12_TT_So) : The LPT function creates a VC–12 by generating and adding POH to a C–12. The POH formats are defined in Recommendations G.708 and G.709. • J2: trail trace identifier is generated. • V5[1,2]: BIP–2 is calculated and transmitted. • V5[3]: the number of errors is encoded in REI. • V5[8]: RDI indication is inserted.

If the signal is unstructured the datas coming from ATM MAPPING block are sent through the HPT block to the SWITCH block.

1AA 00014 0004 (9007) A4 – ALICE 04.10

HPT (Sn_TT_So) : path trace identification insertion, RDI and REI indications insertion, VC–4 BIP–8 calculation and insertion, signal label insertion. N1 byte insertion (Tx side): for the network Tandem Connection Termination & Monitoring function (TCT/TCM).

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N.B.

The description that follows can be applied to both Figure 260. on page 483 and Figure 261. on page 484

1AA 00014 0004 (9007) A4 – ALICE 04.10

RX side from SDH to MATRIX: –

ATM DEMAPPING: this block extract the ATM cells from the transmission path payload E1, E3, VC3, VC4, VC4c; ATM DEMAPPING BLOCK receive the E1 and E3 frames contained in VC3 and VC4 payload for the processing performed in the equipment boards.

–

CELL DELINEATION : cell delineation is the process which allow the identification of the cell boundaries. It is performed on the cell stream extracted from the PDH/SDH frames

–

DESCRAMBLER:for SDH and PDH the information field of each cell is descrambled with a self synchronizing scrambler polynomial; descrambler is enable for a number of bit s equal to the length of the information field, and again disabled for the following assumed header.

–

HEC VERIFICATION AND CORRECTION: in this block HEC field in the cell header is checked; HEC is used to achieved cell delineation. The algorithm used can recover a single–bit error or detect headers with single and multi–bit errors.

–

CELLs DECOUPLING: idle cells are extracted from the cell stream. Idle cells has been inserted in the far end adaptation source function to reach the synchronous container capacity.

–

HEADER VERIFICATION: this function verifies that the first four octets of the ATM cell header are recognizable as being a valid header pattern. Cells with unrecognized header patterns are discarded. An indication of invalid header cell discard event is provided to the microprocessor interface where are counted.

–

UPC/NPC:this function (policing) checks that the incoming traffic from a VPC is not violating the agreed traffic contract. UPC (User Parameter Control) and NPC (Network Parameter Control) perform the same function but in different parts of the network (respectively at User Network Interface and Network Node Interface )

–

OAM: operations and maintenance function is done by using dedicated cells. Typically function are cells monitoring, cells reporting, faults localization etc.

–

HEADER TRANSLATION: this block performs on each virtual connection an header translation which consist in a conversion of the external identification number (LTI/VPI/VCI) into an an internal identification number for the user to network direction

–

CONGESTION MANAGEMENT is the block that in the event of congestion is responsible to assure that cell with loss priority will be discarded before than cell with high priority.

–

TRAFFIC SHAPING:this function enhances the utilization of the buffer and matrix providing better switch performance, especially for burst data.

ED

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[2] ATM signal processing

1AA 00014 0004 (9007) A4 – ALICE 04.10

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TX side from MATRIX to SDH: –

RATE REDUCTION: The purpose of this block is to smooth the average 622 Mbits/s traffic entering with bursts up to 1,2 Gb/s. This function uses four waiting queues, called Rate Reduction FIFOs, used to manage four priority levels fixed on a per connection basis. They are written at 1,2 Gbits/s and read at 622 Mbits/s.

–

MULTICAST: it is a replication function of the incoming cell towards n outgoing directions; a new connection identifier is used for each replication.

–

ROUTING:The purpose of this function is to guide the cells towards their target LT

–

CONGESTION MANAGEMENT: is the block that in the event of congestion is responsible to assure that cell with loss priority will be discarded before than cell with high priority.

–

TRAFFIC SHAPING: the traffic shaping function modifies the characteristics of cells stream in a VCP in order to improve network efficiency. It allows for meeting traffic contract at the egress of the equipment. The shaping function can correct the Cell Delay Variation generated by the buffer and the matrix.

–

HEADER TRANSLATION:this block performs on each virtual connection an header translation which consist in a conversion of the internal identification number into the external identification number (LTI/VPI/VCI)for the network to user direction.

–

OAM:operations and maintenance function is done by using dedicated cells.

–

CELLs RATE DECOUPLING: idle cells are inserted into cell stream to match the rate of the container.

–

HEC PROCESSING: the Header Error Control value is calculated on the entire ATM cell header and inserted in the appropriate field.

–

SCRAMBLER: information field of each cell is scrambled in order to improve security and robustness of the HEC cell delineation mechanism. In addition it helps randomizing the data in the information field for possible improvement of the transmission performance.

–

ATM MAPPING: the cell stream is inserted into transmission path payload E1, E3, VC3, VC4, VC4c; the E1 and E3 frames are sent to the output of the board mapped in VC12 and VC3 payload because of the processing that will be done in the equipment boards.

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The matrix is in charged of cross connect the incoming and outgoing cells according to the information received by the microprocessor. In case of Soft Permanent Virtual Connection ( Soft–PVC) the P–NNI signalling is supported. [4] MICROPROCESSOR The microprocessor present on the board performs the following functionality: –

configuration, alarm and status gathering of the ATM devices present on the board

–

handling of the signalling packet receive from the matrix in case of Soft–PVC

–

communication with the EC on the EQUICO (SNMP Link); using this channel performance and management date are encapsulated and sent to the EC and from there to the Craft Terminal or O.S.

All the LEDS (except that for Unit–Failure) are driven by the microprocessor. The meaning of the LEDs and Push–Button is reported in Figure 258. on page 471. [5] Common part •

RIBUS I/F This block is used to read/write from/to the ”RIBUS” stream, to control the LED on the unit, to release the Management–bus in case of power failure, and to use the remote inventory. RIBUS I/F is powered by the + 3.3 Vdc supply by CONGI boards.

•

REMOTE INVENTORY It is the memory containing the board information, for identification purposes (see para. 3.17 on page 358 for details).

•

M–BUS Driver It drives the input–output gates of the Management–bus. These drivers can be disabled (by the Bus–OFF signal) in case of power failure. DC/DC CONVERTERS Starting from the 48/60 V power supply the following voltages are generated:

1AA 00014 0004 (9007) A4 – ALICE 04.10

– –

ED

+ 5 Vdc used by the optical module +1.5 Vdc, –3.3 Vdc, –3.3 Vdc, –3.3 Vdc, +2.5 Vdc used to supply all the components in the board.

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[3] MATRIX

System clock a

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System clock b

622 MHz OSC

LPT from/to

ÉÉ ÉÉ HEADER VERIFICATION

UPC/NPC

HEC PROCESSING

CELLs DECOUPLING

OAM

SCRAMBLER

HEC VERIFICATION DESCRAMBLER & CORRECTION

HEADER TRANSLATION

CONGESTION MANAGEMENT

HEADER TRANSLATION

ÉÉ ÉÉÉ ÉÉÉÉÉÉÉÉ É ÉÉÉÉÉÉÉÉ É É

OAM

Struct/unstruct

ATM MAPPING

TRAFFIC SHAPING

CELL DELINEATION

MULTICAST

ATM DEMAPPING

TRAFFIC SHAPING

CONGESTION MANAGEMENT

S W I T C H

X

ÏÏ ÏÏ ÏÏ ÏÏ ÏÏ ÏÏ ÏÏ ÏÏ ÏÏ ÏÏ ÏÏ ÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ SPATIAL MATRIX

ROUTING

RATE REDUCTION

SDRAM

PNNI Signalling

ÉÉ

FLASH EPROM

LEDS(X5) LED TEST

ÉÉ ÉÉ ÉÉ É ÉÉÉÉÉ ÉÉ ÉÉ ÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏ

MICROPROCESSOR

RESET

Configuration & Status (ATM)

See Figure 261. on page 484

SNMP

from/to EQUICO

CELLs RATE DECOUPLING

L

LPA

Struct/unstruct

MATRIX MAIN AND SPARE

HPT

Management Bus from/to

M–BUS Driver

Configuration & Status (SDH)

CMISS Bus–OFF Remote Inventory

– 3.3V

1AA 00014 0004 (9007) A4 – ALICE 04.10

ATM MATRIX 8x8 (part A)

3.3 V

DC/DC

Unit Failure

RIBUS I/F

CONVERTERS

ID F

+3.3 Vdc

48/60 V

2.5 V

FROM CONGI

5V 1.5 V

RIBUS

MATRIX MAIN AND SPARE

See Figure 261. on page 484

Figure 260. ATM 8X8 card – Block diagram part A

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622 MHz OSC

LPT from/to

ÉÉ ÉÉ CELLs RATE DECOUPLING

HEADER VERIFICATION

HEC PROCESSING

CELLs DECOUPLING

UPC/NPC

ÉÉ ÉÉÉ ÉÉ

SCRAMBLER

OAM

HEADER TRANSLATION

OAM

HEADER TRANSLATION

Struct/unstruct

ATM MAPPING

HEC VERIFICATION DESCRAMBLER & CORRECTION

CELL DELINEATION

CONGESTION MANAGEMENT

TRAFFIC SHAPING

ÉÉ É ÉÉ ÉÉÉÉ É

L

LPA

Struct/unstruct

ATM DEMAPPING

X

TRAFFIC SHAPING

CONGESTION MANAGEMENT

MULTICAST

S W I T C H

MATRIX MAIN AND SPARE

HPT

ROUTING

RATE REDUCTION

ÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏ ÉÉÉÉ ÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏ to /from

Configuration & Status (ATM)

SPATIAL MATRIX

See Figure 260. on page 483

Configuration & Status (SDH)

1AA 00014 0004 (9007) A4 – ALICE 04.10

ATM MATRIX 8x8 (part B)

Figure 261. ATM 8X8 card – Block diagram part B

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System clock a System clock b

4.32 ISA–Packet Ring Edge Aggregator Unit (PREA1GBE, PREA4ETH)

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(See Figure 263. on page 491.) There are two types of PR_EA: a)

in the first version (PREA4ETH), it hosts a 4 x 10/100 BaseT Fast Ethernet module and the total traffic throughput is 1 Gb/s, in which 622Mb/s are contributed by the SDH matrix, and 400 Mb/s contributed by the 4 Fast Ethernet local ports.

b)

in the second version (PREA1GBE), it hosts a 1 x 1Gigabit Ethernet module and the total traffic throughput is 1.8 Gb/s, in which 622Mb/s are contributed by the SDH matrix, and 1.25 Gb/s contributed by the GbEthernet local port.

The unit allows the management of packets data services over Ethernet and their transportation over the SDH network. The ethernet packets are labelled and then mapped onto SDH frames via PPP/HDLC framing. The ethernet access is possible either local and remote, this latter via GFP/SDH framing; ethernet links can be type E, FE, GE (10Mb/s, 100Mb/s, 1Gb/s). The SDH containers used for data transportation are VC–12, VC–3, VC–4. The MPLS traffic can be connected to 63 logical ports. The functions implemented on the board are the following: 4 x Ethernet Module (case of MPLS+4FE board): –

It implements four Ethernet transceiver interfaces, compliant to IEEE 802.3 standard, Carrier Sense Multiple Access with Collision Detection (CSMA/CD), that can be connected to Local Area Networks (LAN) conveying data packets over Ethernet. The interface type is 10/100Base–T, operating at rates 10 or 100Mb/s, using baseband communication on a twisted pair cable, connected by means of RJ45 connector. Its main functions are: • line isolation • operations auto–negotiation, about the following options: 10Mbps or 100Mbps, full–duplex • receive data and clock recovery, transmit pulse shaping • carrier sensing for collision detection • transmission conflicts management.

1 x GigaEthernet Module (case of MPLS+1GE board):

1AA 00014 0004 (9007) A4 – ALICE 04.10

–

ED

It is a pluggable, small–form factor pluggable module (SFP), implementing the optical to electric conversion, and viceversa, to accomplish a full–duplex Gigabit Ethernet interface at 1.25 Gb/s, as specified in IEEE802.3. For its description refer to para. 4.16, page 411 (”Gbit Eth. i/f Module”).

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–

SWITCH: The task of the SWITCH block is to send the signals coming from HPT or LPT block towards the matrices on the MATRIX unit. The selection is made according to the type of signal to be connected (L if it is structured, X if unstructured). The “L” signals are sent to LPT – LPA blocks, the “X” to the HPT.

–

HPT: this block adds/removes the high order POH bytes to the C–4 unstructured payloads (bulks).

–

LPT: The LPT function terminates a VC–12 or a VC–3 by adding or removing the relevant POH bytes to a C–12 or a C–3.

–

LPA: This block adapts the low order payloads C12 or C3 to the higher order containers used for transportation in the SDH (TU–12 or TU–3). The adaptation includes timing synchronization and frame offset with pointers movements.

–

Struct/Unstr: this selector sends the bulk signals (unstructured) to HPT, while the structured signals are sent to LPA–LPT.

1AA 00014 0004 (9007) A4 – ALICE 04.10

Framing: –

PREAMBLE: it provides to remove (toward MPLS direction) the “preamble” and “start–of–frame–delimiter” fields from the ethernet MAC 802.3 header (Medium Access Control), and to reinsert them toward ethernet direction; then it recalculates the FCS value. ( Moreover it decodes the “Tag” fields of the MAC client header (if present): 802.1p and 802.1q, to read the user priority and the VLAN identifier. The in/out ethernet data are 2–bit paralleled at 50Mb/s in case of E or FE; 8–bit at 125 Mb/s in case of GE.

–

BUF: it is a buffer in which the ethernet data are written by means of a smooth ethernet clock, as they are ready, and are then read by the MPLS mapper (PUSH). In case that the buffer is near to full the mechanism of flow–control is started, in order to slow down the ethernet data source.

–

PUSH: it provides to “push in” the first label to the ethernet packet (the second label is pushed by the MPLS router), after having inspected the ethernet header, identified the destination and the class of service. It classifies the packets according to the 802.1p/q “VLAN–Tag” and “User Priority” fields, if configured. Depending on the type of decoded ethernet SLA (Service Level Agreement) the stream can be associated with one of three types of QoS (Quality of Service): Best Effort bandwidth (BE–BW), or Min–BW with regulated bursts, or Guaranteed constant BW.

–

POP: It provides to “pop out” the label from the packet, returning the bare ethernet frame.

–

GFP: it provides to deassemble (toward MPLS direction) the GFP frames (Generic Framing Procedure), removing the GFP header, and to assemble them toward SDH direction. It supports un–concatenated ethernet frames over unstructured VC4 payloads.

–

HDLC: it provides (refer to rec. RFC 1662 and RFC 2615): • to deassemble (MPLS direction) the HDLC frames (High–Level Data Link Control), removing the HDLC header, and to assemble them in SDH direction; • FCS calculation (Frame Check Sequence); • byte stuffing/destuffing: flag sequence or other header octets are encoded by a 2–octet sequence, in the data field, in order to avoid erroneous simulations of the header; • inter–frame filling, by means of the “flag–sequence” (hex 0x7e) repetition; • X^43 +1 data scrambling/descrambling.

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SDH termination:

1AA 00014 0004 (9007) A4 – ALICE 04.10

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–

PPP: it provides to deassemble (in MPLS direction) the PPP frames (Point–to–Point Protocol), removing the PPP header, and to assemble them in SDH direction. It carries out, optionally, the “Martini encapsulation”, removing the FCS field from the ethernet frame and inserting a checksum value for the MPLS packet.

–

A: this block provides to adapt the serial bus from the back–panel bus format to the intra–board bus format, for SNMP messaging between the microprocessor and the EC (equipment controller), for MPLS network configuration.

–

SMAP: it provides, toward MPLS direction, to “unload” the data packets from the SDH frames, and to “load” them in SDH direction; the packets are then switched toward GFP or HDLC processing, according to the logical ports configurations.

MPLS Router: It performs the routing functions by looking the top MPLS label, it can forward the packets streams to up to 63 SDH or ethernet ports. In the MPLS network, it provides to inspect the top label of the MPLS packet in order to identify the incoming FEC and LSP; if possible, it aggregates the packet to other packets streams on a common path, then it selects the forwarding to a next hop by swapping the top label. At the edge of the MPLS network (originating node), on receiving packets from the local or remote ethernet interfaces, it provides to push the top label reporting information for the routing procedure (LSP and FEC). At the edge of the MPLS network (destination node), on receiving packets from the network, it provides to pop out the top label and drops them to the destination end port. At the beginning of a packets stream introduction, the microcontroller starts the RSVP–TE signalling (Resource Reservation Protocol – Traffic Engineered Tunnel) in order to search and establish a path with a certain band capacity and a given priority, between the destination and the source node; this path can be treated as a tunnel and is called LSP (Label Switched Path); once the LSP has been established, the RSVP signalling finishes and starts the Label Distribution Protocol (LDP) signalling, that informs all the nodes of the network to maintain the label bindings for the relevant established LSP. The RSVP and LDP signalling are in–band communications between the local and remote microcontrollers.

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–

It provides to monitor the load of traffic in the local router, and to take measures for preventing the congestions, supported by the intra–board microcontroller, such as: management of many different queues and relative priorities, packets queuing, packets discarding, packets lifetime management, etc. It implements, mainly, for this function, the following mechanisms: • 256 queues for each “logical” port (the logical ports number is 63) • scheduling, by means of HOL or WC–WFQ or WNC–WFQ methods • congestion avoidance via W–RED method (Weighed–Random Early Discarding): in occurrence of congestion conditions signals, a random packets discarding is started, in order to prevent the traffic worsening. • The priority management is based on the ethernet SLA (Service Level Agreement), by means of CIR and PIR values of the traffic contract. • Three types of QoS (Quality of Service) are available: Best Effort bandwidth (BE–BW), Min–BW with regulated bursts, Guaranteed constant BW. • A “Dual–Rate Leaky–Bucket” police mechanism is used (it can be seen as two cascaded leaky buckets, the first based on PIR value, the second on CIR). • In case of congestion, only the low priority traffic will be cut–off, while the high priority traffic maintains the guaranteed BW. • The Best–Effort traffic deployed in ring topology can be associated to a “Fixed Share” of the total available band, or to a “Variable&Proportional Share”. In case of congestion the BE excess traffic will be cut–off via W–RED. • Packets shorter than the minimum ethernet frame are silently discarded. Packets longer than the maximum frame are silently discarded. The discarded packets are counted by the PM function. • Note: the priority and the BW parameters are marked on the first label, at the “PUSH1” function of the ingress node.

Microprocessor:

1AA 00014 0004 (9007) A4 – ALICE 04.10

–

ED

It is a local microcontroller managing and supporting the MPLS functionalities, such as: The RSVP–TE and LDP communications between the destination and the origination nodes, in order to establish the routing and the LSP tunnelling. Management of communications with the EC and the network Operations System (OS), by means of SNMP (Simple Network Management Protocol) messaging, for MPLS network configuration. Configuration of the MPLS functions implemented by the devices on the board, by means of ICMP (Internet Control Message Protocol) messaging. Collection of alarms and status of the MPLS functions. Management of the Performance Monitoring (PM) function for MPLS. Management of Multicast traffic. Management of OSPF (Open Shortest Path First) routing (not operative). Furthermore it aids the congestion control function, supporting the “Queuing Manager” Communications with the EC, by means of the ISSB–EC bus, for software data transfer. It is provided with relevant SDRAM and Flash EPROM devices, for data and software storage.

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Queuing management:

1AA 00014 0004 (9007) A4 – ALICE 04.10

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Other functions implemented on the board are: •

RIBUS I/F This block is used to read/write from/to the ”RIBUS” serial stream, to control the LED on the unit, to release the Management–bus in case of power failure, and to use the remote inventory. RIBUS I/F is powered by the + 3.3 VS supplied by the rear access panel.

•

REMOTE INVENTORY It is the memory containing the board information, for identification purposes (see para. 3.17 on page 358 for details about Remote Inventory information).

•

M–BUS Driver It drives the input–output gates of the parallel Management–bus. These drivers can be disabled (by the Bus–OFF signal) in case of power failure. DC/DC CONVERTERS This block converts the 48/60 V power supply, to obtain the voltages used to supply all the components in the board. The DC/DC converter is synchronized with a synchronization clock at 300 MHz (signal Power–Sync, generated by the SDH asic) in order to avoid EMI problems.

ED

•

LEDS and Push–buttons The board presents, on its front panel, some LEDS and push–buttons; the meaning of these LEDs and Push–Buttons is reported in Figure 47. page 136 and Figure 48. page 137.

•

Buses The main buses on the board are: SNMP: serial bus to carry SNMP (Simple Network Management Protocol) messages between the EC and the intra board controller, for information about MPLS network configuration. This link is implemented by means of the DCC–EC bus from EC on EQUICO unit. ISSB–EC: Intra–Shelf–Serial–Bus from the EC, to communicate software data (download, etc.). ISSB–SPARE: serial bus to the spare MPLS unit (if any) to communicate EPS information (. SDH–CS: from the EC, after derivation from the parallel “Management–bus” (M–bus), for configuration and status information of SDH components. MPLS–CS: from microprocessor, for configuration and status information of MPLS components, it conveys ICMP packets. RIBUS: serial bus from the SC (shelf controller on MATRIX unit), to communicate inventory and peripheral data. M–BUS: called also ISPB (Intra Shelf Parallel Bus), from the SC (shelf controller on MATRIX unit), to communicate data about asics configuration, SDH alarms collection, etc.

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HPOM HSUT RST

MST

AUX

System clock (T0)

MSA H

HPT DCCR RSOH

from/to MATRIX main and spare

DCCM MSOH LPT

SDH–CS 4 x FE 2@50Mb/s

SDH–CS X

LPA

PREAMBLE SMAP

GFP BUF PPP

HDLC

S W I T C H

HDLC PPP POP

L

A

MPLS–CS

MPLS ROUTER

MPLS–CS

SNMP

SNMP

SDRAM

MPLS–CS

FLASH EPROM

ÀÀÀÀÀÀÀÀÀÀ ÀÀÀÀÀÀÀÀÀÀ (EPS) ISSB–SPARE

Configuration & Status for MPLS (MPLS–CS)

MICROPROCESSOR RESTART

from/to SPARE MPLS UNIT

QUEUING MANAGEMENT

from/to EQUICO

PUSH PUSH

ÀÀÀÀÀÀÀÀÀÀÀ ÀÀÀÀÀÀÀÀÀÀÀ ISSB–EC

Management Bus (ISPB)

Configuration & Status for SDH (SDH–CS)

M–BUS Driver

from/to

POP

SMAP

Struct/unstruct GFP

CMISS Bus–OFF Remote Inventory

1.8 V DC/DC 3.3 V

CONVERTERS

Unit Failure

RIBUS RIBUS I/F

1AA 00014 0004 (9007) A4 – ALICE 04.10

2.5 V

ID F

+3.3 Vdc

48/60 V

FROM CONGI

5V

MATRIX MAIN AND SPARE

10/100 Mb/s FAST ETHERNET

622 MHz OSC

from/to SERVICE

MPLS + 4 x FAST ETHERNET

Figure 262. MPLS+4FE Unit (PREA4ETH) – Block diagram

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SOH bytes

RSOH, MSOH, F2, F3

MST

from/to SERVICE

System clock (T0)

MSA H

HPT DCCR RSOH

DCCM MSOH LPT

SDH–CS 8@125Mb/s

SDH–CS X

LPA

PREAMBLE SMAP

GFP BUF PPP

HDLC

S W I T C H

HDLC PPP POP

SMAP

Struct/unstruct GFP

L

A

MPLS–CS

SNMP SNMP

SDRAM

MPLS–CS

FLASH EPROM (EPS) ISSB–SPARE

from/to SPARE MPLS UNIT

MPLS–CS

MPLS ROUTER

ÀÀÀÀÀÀÀÀÀÀÀ

Configuration & Status for MPLS (MPLS–CS)

MICROPROCESSOR

ÀÀÀÀÀÀÀÀÀÀÀ ÀÀÀÀÀÀÀÀÀÀÀ

RESTART

ISSB–EC

Management Bus (ISPB)

Configuration & Status for SDH (SDH–CS)

M–BUS Driver CMISS Bus–OFF Remote Inventory

5V 1.8 V DC/DC 3.3 V

CONVERTERS

Unit Failure

RIBUS RIBUS I/F

2.5 V

ID F

from/to MATRIX main and spare

QUEUING MANAGEMENT

from/to EQUICO

PUSH PUSH

+3.3 Vdc

48/60 V

FROM CONGI

1 x GBE

POP

1AA 00014 0004 (9007) A4 – ALICE 04.10

from/to MATRIX main and spare

622 MHz OSC 1 GIGABIT ETHERNET I/O

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HPOM HSUT RST

AUX

SOH bytes

RSOH, MSOH, F2, F3

MPLS + 1 x GIGABIT ETHERNET

Figure 263. MPLS+1GbE Unit (PREA1GBE) – Block diagram

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The role of the ISA–PR functionality inside 1660SM is to provide a shared carrier–class Ethernet Packet Ring embedded either physically or logically into the SDH infrastructure, in a flexible manner over SDH Virtual Containers. The ISA–PR Packet Ring transports and aggregates Metro Ethernet traffic within a metro access or metro core SDH access ring/rings, all packet traffic is statistically multiplexed, with multiple Classes of Services and guaranteed QoS support (according to the defined SLA). The ISA–PR port card is used in conjunction with the 16FEA–PR and 2GBA–PR Access cards. These Access cards are described in para. 4.9 at page 390 and 4.10 at page 4.10 respectively. Functional Overview The diagram below shows the main functional blocks of the ISA–PR port card and interconnections to the access cards I2C bus

GigaBit Ethernet Access Card

RI GMII

RI

GMII

RI

RI

MII1

NP

RGGI

RGGI

AC (Access chip)

1GData

1GData

1GHOST

1G(Ser) 1G(Ser)

1G 1G 1G

1G

1G

RI Unit Led

BT–Stratix2

AC

1G(Ser) 1G(Ser)

1G(Ser)

1G(Ser)

Octal SerDes

GMII

Port Card

6G(in) HSI 4G(eg)

BU param SRAM Bu Policer/

CI Map SRAM

Stratix1 Channel Scheduler

RGGI

1GHost

GMII

Octal SerDes

Host

1G

Host

FE Access Card

NP

RGGI

Craft Terminal & NMS

MII16

Policer

BM–Stratix1

Channel Scheduler Table

PM param

Mac I/F

ATI 32 (2.4G) ADM – OC12/OC48 Stratix2 Utopia 32bits 2Phy(4)

EDC Daughter Board

Framer TADM Power

1AA 00014 0004 (9007) A4 – ALICE 04.10

Optical transceiver Modules

– Batt / Ground from Congi

STM4 line signals

Figure 264. PR unit functional block diagram

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4.33 ISA – Packet Ring unit (ISA–PR)

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The main functional blocks of the ISA–PR port card are as follows: •

Optical transceivers – Physical ring interfaces: STM–4.

•

Framer ADM – Provides the SDH framing.

•

ADM (Add Drop Multiplexer) – Extracts traffic to be dropped in this port card, and merges traffic received from the access cards with through traffic on the ring.

•

Bandwidth Management – This block incorporates SLA control & policing and buffer management. It is this block that determines the precedence and delay with which packets are forwarded to/from the ring.

•

Host – System controller responsible for the local management of the ISA–PR port card and access cards. The host communicates with the different elements of the ISA–PR series via dedicated control paths. Loss of a host card through a fault does not affect the delivery of customer traffic. The host card can communicate via one of two interfaces:

•

–

External Ethernet interface presented on the faceplate of the ISA–PR port card.

–

Internal Ethernet interface transported in the payload of the packet ring; used for in band communication between network elements and between network elements and the NMS.

EDC (Extended Differential Delay) – The EDC block is implemented on a daughter board. The block is essential to meet various SDH underlay Route Diversity scenarios (Route Diversity refers to SDH signal delivery across more than one fiber in parallel).

Data Path Access to Port The port card receives classified and edited frames from the Network Processor block on the access card. These incoming frames are presented to the bandwidth management block for processing. The bandwidth management block performs: Frame Policing and Marking (crucial component in providing MEF compliant services). Frame marking refers to the method whereby some frames may be marked for possible discard. Under congestion conditions only these frames will be considered for discard. Buffer Management, i.e. frame storage in memory in the proper order till it is forwarded. Scheduled frame forwarding to the various destinations subject to bandwidth availability, priorities, Load Balancing considerations etc. Note that all destinations are possible, i.e. Ring interfaces at the Trunk card, Ethernet interfaces at a Line card, any combination thereof. Buffer Management may discard frames in course of Policing.

1AA 00014 0004 (9007) A4 – ALICE 04.10

The next stage is the ADM block where through traffic from the ring is merged with traffic generated within this system. Frames are forwarded according to priority criteria to the Framer. The Framer maintains the Ring interfaces and maps the frames onto them.

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The ADM looks up the network tag (MPLS) makes a decision according to the following criteria:– • • • •

Drop Drop & forward Forward Discard decision.

All frames that are due to be forwarded on the ring are merged with locally generated frames. All frames that are dropped from the ring are forwarded to the bandwidth management block. The bandwidth management block buffers the frames till they can be forwarded to the Access cards, subject to bandwidth availability, congestion conditions and frame priorities. Control The ISA–PR port card is managed via the host controller housed on the port card itself. The control bus can be used to read inventory information such as serial number, construction information & date of manufacture. LEDs on the ISA–PR faceplate provide indications as specified in the table below.

1AA 00014 0004 (9007) A4 – ALICE 04.10

Table 51. PR unit LED designation

LED name

State

OK

YELLOW

ED

Alarm / Status ON = Minor Blinking 50/50 = maintenance in progress (loopbacks...)

OK

RED

ON = Major/Critical alarms on ISA–PR or Slot alarms in Access Card or Major transmission alarms on Access Card. Access card slot alarms stand for: Card Mismatch, Card Unassigned Card failure on POST (Power On Self Test) Blinking 50/50 = during the POST (Power On Self Test) failure. On POST completion the LED will change its color according to the card status afterwards Blinking 20/80 = card mismatch

OK

GREEN

ON = OK Status Blinking 50/50 = ISA–PR in initialization process (following power–on or reset)

OK

OFF

Active

GREEN

Active

OFF

the card is not powered ON = the card is powered the card is not powered

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Data Path Port to Access The ISA–PR port card receives ring traffic over the SDH optical interfaces. The framer, which hosts the Ring interfaces, recovers and validates the frames and forwards them to ADM

1AA 00014 0004 (9007) A4 – ALICE 04.10

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Physical Interfaces The faceplate for the ISA–PR port module (shown in Figure 49. on page 138) presents the following connectors: SFP optical connections for SDH ring interfaces. The interfaces are designated W1 and W2 for West ring interface and E1 and E2 for East ring interface RS232 – RJ45 connector, allows for connection of a local console interface for use by a qualified engineer for debug purposes Eth (Ethernet Management interface) – RJ45 connector, enables local connection to the web based craft interface. This interface can also be used to connect to the NMS (Network Management System) via a data communications network (DCN). Power The ISA–PR port module receives 48v DC from the backplane and converts to lower voltages for local use. The power consumption of the ISA–PR port module is 50 Watts.

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4.34 ISA – Ethernet/Fast Ethernet port (ETH–MB)

The ETHERNET–PORT is a new unit able to process twenty–five (10/100 Mbit/s) Ethernet and fast Ethernet streams and to map them towards the SDH world. The Ethernet frames are inserted into a GFP (Generic Framing Procedure) packet which is a universal container for data traffic. The unit is able to execute a RATE ADAPTING action, hence it is able to cross–connect a 10/100Mbit/s ETHERNET stream towards an SDH virtual container of any dimension (VC12, VC3, VC4). The Ethernet unit is able to memorize all the frames composing the incoming 10Mbit/s signal in a pseudo hard disk made up of eight RAM (1Mx18bit) memories to be forwarded to the selected VCx. Should the memories be filled up without emptying them in the Vcx, a flow control intervenes. The latter is able to communicate to the Ethernet transmitter to reduce or interrupt the frame transmission up to recovering the stable condition of the archived frames versus the ones sent over the SDH VC. All the write and read operations occur at the 125 Mhz frequency in order to reduce the risk of memory stuffing. The same operation will also be executed on the Tx side, i.e. the frames contained in the SDH virtual containers will pass in the RAMs before to be forwarded to the outgoing Ethernet stream. The ETH–ATX access port can be utilized in order to supply the highest number of Ethernet ports; it is provided only with a physical Ethernet interface facing with the ETHERNET–PORT (ETH–MB) via backpanel as regards the management and cross–connection functions towards the SDH world. In this manner 11 interfaces are made available on the ETHERNET–PORT and 14 interfaces are made available on the ETHERNET ACCESS for a total amount of 25 10/100Mbit/s streams. The ETH–MB can also be used in conjunction with the Gigabit Access card GETH–AG in order to process two 1.25 Gbit/s Ethernet stream and eleven 10/100 Mbit/s Ethernet stream (refer to paragraph 3.8.4.2 on page 268 for details).

1AA 00014 0004 (9007) A4 – ALICE 04.10

In the following is described the signal processing in the Ethernet line –––> SDH matrix (placed on the MATRIX unit) direction. On the opposite side are performed the complementary functions.

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(See Figure 265. on page 499)

The functions implemented on the board are the following:

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–

Ethernet frames processing: •

SELF RATE ADAPTING and interfacing with the line: The Ethernet streams come into the unit via eleven connectors RJ45 on the front–cover, just after there are the transformers to realize the crossover function. The inner part of the line interface comprises the “Self Rate Adapting” block, which is able to perform the physical processing of the 10/100 Mbit/s signals. At the start–up, this block is automatically able to select the max. rate accepted by the remote station; it is however possible to force all the configurations (full–duplex, half–duplex, 10Mbit/s & 100Mbit/s) by means of the check signal “Rate Adapting forced settings” coming from the Microcontroller on the board. The “Self Rate Adapting” block requires a 125 MHz reference clock (supplied by a VCXO) in order to be able to process the input and output signals. The signals are sent to the “Retiming” block after having been processed.

•

RETIMING: The eleven Tx and Rx serial streams together with the clock and synchronism are retimed with the system clock to absorb phase differences (if any) with the clock recovered from the data.

•

GFP: The function of this block is to prepare the Ethernet frames to be mapped towards the SDH world by means of GFP encapsulation (see para. 3.8 on page 253 for details) thus guaranteeing the possibility to utilize any type of VCx virtual container. The “GFP” block” is connected to 8 SSRAM memory pads to create the pseudo hard disk functionality and to 3 external memories (Management memories) where are stored all the information required to perform the connections towards the VCx.

•

MICROCONTROLLER: The Microcontroller can set all the operation settings of the “Self Rate Adapting” block present on the ETH–MB board and the one on the ETH–ATX access unit. Moreover the Microcontroller can configure the “GFP” block cross–connections. The program executed by the microcontroller to perform the various processes resides in two SRAM memories and in one FLASH memory on the board.

•

SIPO & PISO:

1AA 00014 0004 (9007) A4 – ALICE 04.10

These blocks are used to parallel the 1.25Gbit/s streams received from the access port and then processed like the signals recovered from the 11 line interfaces on the same board. In fact, the 14 streams have been serialized by obtaining two 1.25Gbit/s links in order to connect 14 Ethernet streams on the access board via the backpanel. The 1.25Gbit/s streams are also utilized to connect the Ethernet port (ETH–MB) with the Gigabit Access card (GETH–AG).

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•

On the unit is present a VCXO supplying a 125MHz clock to all the logics processing the Ethernet signal. –

1AA 00014 0004 (9007) A4 – ALICE 04.10

–

ED

SDH termination: •

SWITCH: The task of the SWITCH block is to send the signals coming from HPT or LPT block towards the matrix on the MATRIX board. The selection is made according to the type of signal to be connected (L if it is structured, X if unstructured). The “L” signals are sent to LPT – LPA blocks, the “X” to the HPT.

•

HPT: this block adds/removes the high order POH bytes to the C–4 unstructured payloads (bulks).

•

LPT: The LPT function terminates a VC–12 or a VC–3 by adding or removing the relevant POH bytes to a C–12 or a C–3.

•

LPA: This block adapts the low order payloads C12 or C3 to the higher order containers used for transportation in the SDH (TU–12 or TU–3). The adaptation includes timing synchronization and frame offset with pointers movements.

•

Struct/Unstr: this selector sends the bulk signals (unstructured) to HPT, while the structured signals are sent to LPA–LPT.

Other functions implemented on the board are: •

RIBUS I/F This block is used to read/write from/to the ”RIBUS” serial stream, to control the LED on the unit, to release the Management–bus in case of power failure, and to use the remote inventory. RIBUS I/F is powered by the + 3.3 VS supplied by the CONGI

•

REMOTE INVENTORY It is the memory containing the board information, for identification purposes (see para. 3.17 on page 358 for details about Remote Inventory information).

•

M–BUS Driver It drives the input–output gates of the serial Management–bus. These drivers can be disabled (by the Bus–OFF signal) in case of power failure.

•

DC/DC CONVERTERS This block converts the 48/60 V power supply, to obtain the voltages used to supply all the components in the board. The DC/DC converter is synchronized with a synchronization clock at 300 MHz (signal Power–Sync, generated by the SDH asic) in order to avoid EMI problems.

•

LEDS The board presents on its front panel one LED the meaning of which is reported in Figure 41. on page 130.

•

Buses The main buses on the board are: ISSB–EC: serial bus from the EC, to communicate software data (download, etc.). SDH–CS: from the EC, after derivation from the serial “Management–bus”, for configuration and status information of SDH components. RIBUS: serial bus from the SC (shelf controller on MATRIX unit), to communicate inventory and peripheral data.

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VCXO:

System clock a System clock b

from/to

LPT

SDH–CS X

LPA

Power Sync. VCX0 125MHz

GFP Generic Framing Procedure

Data+Ck RETIMING 8

(not used)

12

1

RAM 1,2 Gb/s DATA SIPO & PISO

ÉÉ ÉÉ ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ ÉÉÉ ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ

Rate adapting forced settings

Configuration

SDRAM

ISSB–EC

MICROPROCESSOR

FLASH EPROM

Management Bus (ISPB)

M–BUS Driver

Configuration & Status for SDH (SDH–CS)

CMISS Power Sync.

Bus–OFF Remote Inventory

3.3 V 2.5 V

RIBUS

ID

1.8V DC/DC CONVERTERS

Unit Failure

RIBUS I/F

F

+3.3 Vdc

48/60 V

ETHERNET PORT

1AA 00014 0004 (9007) A4 – ALICE 04.10

from/to ACCESS CARD

ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎ ÎÎ

Full–duplex Half–duplex 10 Mbit/s 100 Mbit/s

É É É

Configuration

from/to EQUICO

11

Management Memory

System clock

SELF RATE ADAPTING

L

from/to

2

ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ

Struct/unstruct

FROM CONGI

ETHERNET INTERFACE 10 BASE T

1

S W I T C H

MATRIX MAIN AND SPARE

HPT

SDH–CS

MATRIX MAIN AND SPARE

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622 MHz OSC

Figure 265. ETHERNET port (ETH–MB) – Block diagram

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4.35 ISA –Giga Ethernet Main Board (GETH–MB)

This unit allows the management of Giga–bit Ethernet data and their transportation over the SDH network. The connections to the Ethernet network are accomplished by means of 4 full–duplex ethernet optical interfaces, type 1000Base–LX , 1000Base–SX, 1000Base–ZX ; the giga–ethernet links operate at rates up to 1.25Gb/s, with data–rate auto–negotiation option, connected by means of LC–Duplex fiber connectors. The SDH container used for Ethernet data transportation is VC–4. The four Ethernet channels can be connected to 4 SDH logical ports at VC4 rate. The main functions implemented on the board are the following: GbEth i/f SIPO&PISOa SIPO&PISOb ETH–GFP TABLES MEM GFP–SDH ALIGNMENT BUFFER SDH–BP Microprocessor RIBUS i/f & Remote Inventory DC/DC Converters. GbEth I/F: four of these blocks are located on the unit; it is a small–form factor pluggable (SFP) module, implementing the optical to electric conversion, and viceversa, to accomplish a full–duplex Gigabit Ethernet interface at 1.25 Gb/s, as specified in IEEE802.3. For its description refer to para. 4.16, page 411 (”Gbit Eth. i/f Module” 1000B–LX, 1000B–SX, 1000B–ZX).

1AA 00014 0004 (9007) A4 – ALICE 04.10

SIPO&PISO: two of these blocks are located on the unit: SIPO&PISOa serves the four Gigabit data afferent the optical interfaces on the present board, while SIPO&PISOb is not used. The SIPO&PISO block receives four ethernet differential signals at a rate of 1.25Gb/s and parallels each of them on ten wires at 125Mb/s rate; viceversa, in the opposite direction, it receives each gigabit signal on a parallel flow on 10–bits basis and serializes it. It accomplishes the PCS and PMA functions specified by the IEEE802.3: • receive clock recovery • data serialization/deserialization • encoding/decoding of octets data to/from ten–bits code–groups (8b/10b) • managing of the auto–negotiation process. ETH–GFP: this is an integrated circuit that accomplishes the data passage from ethernet frames to GFP (Generic Framing Procedure) frames and viceversa. Every function contained in it is repeated 4 times, in order to process the 4 ethernet signals. The ethernet MAC frame structure is illustrated in Figure 110. page 228 and is detailed in rec. IEEE 802.3. The GFP frame structure is illustrated in para. 3.8, page 253, and is detailed in rec.ITU–T G.7041. Its main functions are: NOTE: the functions are here described only in the direction from Ethernet to GFP, in the opposite direction they are opposite and specular. • ETH: it provides to acknowledge the boundaries of the ethernet frames as specified in rec. IEEE 802.3. The octets relevant to ethernet Preamble and Start–Of–Frame Delimiter are discarded.

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(See Figure 266. on page 503).

•

SIL: it provides to acknowledge the ethernet inter–frames silences and to discard them. In this way the useful data only are transferred to the subsequent data buffer. BUFF: it is a buffer in which the ethernet data are written by means of a smooth ethernet clock, as they are ready, and then are read by the GFP mapper. In case that the buffer is near to full the mechanism of flow–control is started, in order to slow down the remote ethernet data source. GFP: it is the GFP mapper. The data are drawn from the buffer at 155Mb/s rate; possible gaps between ethernet encapsulated frames are filled with Inter–Packet Gaps (IPG).

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•

•

TABLES MEM: this is a memory storing some tables of data relevant to: routing, delays of the queues and delays of the links, destinations of the ethernet signals, etc. GFP–SDH: this is an integrated circuit that accomplishes the data passage from GFP frames to SDH frames and viceversa. Every function contained in it is repeated 4 times, in order to process the 4 afferent signals. Its main functions are: NOTE: the functions are here described only in the direction from GFP to SDH, in the opposite direction they are opposite and specular. • LPA: it provides to map, directly, the GFP data into an SDH higher order unstructured C4 container. • HPT: this block adds the higher order POH bytes to the C–4 payload (bulk); it accomplishes only a reduced HPT, since the complete function is implemented on the SDH–BP macro–block. • XC&VC: it implements the Cross–Connection (routing) and the Virtual Concatenation of the encapsulated ethernet signals. The Virtual Concatenation consists in the distribution of the bytes flow of a single ethernet signal, by bytes de–interleaving, over several, concatenated VC4 signals; the virtual concatenation can be done over 2 or 4 or 7 VC4’s. • MSA, MST, RST: they accomplish only reduced SDH functions for the STM1 signal, since they are used here only for intra–board framing purposes; ALIGNMENT BUFFER: this is a buffer storing the data, needed in the case of virtual concatenation: since different VC4’s can have different delays, they must be memorized to be aligned; the maximum tolerable delay difference is 250msec.

1AA 00014 0004 (9007) A4 – ALICE 04.10

SDH–BP: this is an integrated circuit that accomplishes the data passage from STM1 frames to VC4 frames for the BackPanel format and viceversa. Two of these macro–blocks are located on the board, in order to process the 8 afferent signals, since each of them can process 4 stm1 signals. Every function contained in it is repeated 4 times. Its main functions are: NOTE: the functions are here described only in the direction toward the back panel, in the opposite direction they are opposite and specular. • RST, MST, MSA: these are standard SDH functions for the STM1 signal, their function is reduced since they are used here only for intra–board framing purposes; • HPT: this block adds the higher order POH bytes to the C–4 payload (bulk); • 4:1&1:4 : this is a parallel–to–serial converter, in direction towards the backpanel, and a serial–to–parallel converter, in direction from the backpanel; the backpanel signal format is STM4–like, at 622 Mb/s rate. The backpanel signal is split in two: the first (D1a and D2a) going to the main MATRIX Unit and the second (D1b and D2b) to the spare MATRIX Unit

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622MHz PLL: It is a phase locked loop generating the 622 Mhz reference clock for timing the downstream data toward the ethernet interfaces.

Microprocessor: It is a microcontroller (NIOS type) controlling and supporting the Ethernet functionalities, such as: configuration, alarms and states collections, performances monitoring, communications with the Shelf Controller (SC, on MATRIX unit) and with the OS, etc. It communicates with the SC by means of the configuration bus for SDH functions (SDH–CS), coming from the Management bus ISPB (intra shelf parallel bus). It is provided with relevant devices SDRAM (for data memory) and Flash EPROM (for program memory). The other functions implemented on the board are: •

RIBUS I/F This block is used to read/write from/to the ”RIBUS” serial stream (SPI: serial peripheral inventory), to control the LED on the unit, to release the Management–bus in case of power failure, and to use the remote inventory. RIBUS I/F is powered by the + 3.3 VS supplied by the rear access panel.

•

REMOTE INVENTORY It is the memory containing the board information, for identification purposes (see para. 3.17 on page 358 for details).

•

M–BUS Driver It drives the input–output gates of the Management–bus (ISPB: intra–shelf parallel bus). These drivers can be disabled (by the Bus–OFF signal) in case of power failure.

1AA 00014 0004 (9007) A4 – ALICE 04.10

DC/DC CONVERTERS This block converts the 48/60 V power supply, to obtain the voltages used to supply all the components in the board. The DC/DC converter is synchronized with a synchronization clock at 300 MHz (signal Power–Sync, generated by the SDH asic) in order to avoid EMI problems.

ED

•

LEDS and Push–buttons The board presents, on its front panel, one LED, the use and meaning of the LED and of the frontal connectors is reported in Figure 42. on page 131.

•

Buses The main buses on the board are: SDH–CS: from the SC (shelf controller), after derivation from the “Management–bus” (M–bus), for configuration and status information of SDH components. ETH–CS: from microprocessor, for configuration and status information of the Ethernet functions. RIBUS: also called SPI (serial peripheral bus), from the SC (shelf controller on MATRIX unit), to communicate inventory and peripheral data. M–BUS: called also ISPB (Intra Shelf Parallel Bus), from the SC (shelf controller on MATRIX unit), to communicate data about SDH asics and traffic configuration, SDH alarms collection, performance monitoring, etc.

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VCXO25MHz: It generates a 25 Mhz frequency and, by means of a x5 multiplier, the 125 MHz ethernet transmitter reference clock.

622 MHz PLL

:4 622MHz

System clock (T0a, T0b) 2

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

SDH–CS

2

D1a

2

D1b

4:1

155MHz

2x8

LPA

MSA

HPT

MST

2x4

RST

MST

MSA

HPT

RST

1:4 SDH–BP

1

2x8

XC & VC GFP–SDH

from/to

SDH–CS

2x4 @155Mb/s

SDH–BP

2

D2a

2

D2b

2

@622Mb/s

MATRIX MAIN AND SPARE

155MHz

125MHz

ALIGNMENT BUFFER

PowerSync.

@1.25Gb/s

2x4

ETH–GFP 2x4

GbEth I/F 1

125MHz

155MHz

2x40@125Mb/s

SIPO & PISO a

ETH 2x40@125Mb/s

SIL

BUFF

GFP

2x8@155Mb/s

2 3 4

125MHz

ETH–CS 125MHz

TABLES MEM

125MHz

x5

SIPO & PISO b

2x4 @1.25Gb/s

not used

125MHz

VCX0 25MHz

Configuration for Eth.

SDRAM

MICROPROCESSOR (NIOS)

FLASH EPROM

M–BUS Driver CMISS Bus–OFF

internal voltages

PowerSync.

1.5V

Remote Inventory ID

1.8V 3.3 V

DC/DC CONVERTERS

Unit Failure

RIBUS I/F

2.5 V

RIBUS (SPI)

F

+3.3 Vdc

48/60 V

from CONGI

Configuration & Status for SDH (SDH–CS)

from/to

Management Bus (ISPB)

MATRIX MAIN AND SPARE

ETH–CS

1AA 00014 0004 (9007) A4 – ALICE 04.10

Gigabit Ethernet Unit Figure 266. Gigabit Ethernet Unit – Block diagram

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The board ISA–ES1–8FE mainly works as a LAN switching, and in particular it provides the service of connecting two LANs as a point to point connection between two routers or switches through an SDH network. The connections to the Ethernet network are accomplished by means of eight local 10/100 Base T ethernet interfaces located on the front of the board, and eight ethernet over SDH interfaces through back–panel. The SDH container used for Ethernet data transportation are VC–4, VC–3, VC–12, VC3XV and VC12XV. The main functions implemented on the board are the following: [1]

Ethernet Physical interface

[2]

Ethernet Switch module

[3]

Ethernet Mapper (GFP/LAPS)

[4]

Bus converter

[5]

SDH interfacing to Back Panel (TTF and LVC)

[6]

Microprocessor

[7]

RIBUS interface

[8]

Power supply

[1] Ethernet Physical interface This block supports the eight 10/100 Mbit/s ports. The 10/100 Mbit/s Ethernet MAC block is IEEE 802.3, 802.3x and 802.3ac compliant and supports Full Duplex/Half Duplex for 10/100 Mbit/s Ethernet MAC (MAC implements the IEEE 802.3 MAC Control layer and PAUSE operation for flow control) mode of operation. In addition, 3 LED interface are provided for each port to reflect current status. [2] Ethernet Switch module In ISA ES1–8FE board, 16FE ports are used, in which 8 of them for 100BASE–T line side interface, while other 8 for SDH mapper.

1AA 00014 0004 (9007) A4 – ALICE 04.10

The basic functions supported are following listed: • • • • • • • •

ED

MAC based forwarding and autolearning VLAN based forwarding 802.1Q VLAN add/remove/swap Stacked VLAN (802.1Q format) add/remove/swap Multicast/Broadcast 802.3x flow control 802.1Q Priority bits management for queuing, WFQ scheduling Policing and bandwidth allocation

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4.36 ISA– Ethernet switch (ES1–8FE)

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[3] Ethernet Mapping over SDH (GFP/LAPS) Ethernet packets are encapsulated and mapped into SDH frames for transmission. Ethernet mapper supports 8 independent channels for EOS encapsulation. Each channel can be mapped with multi SDH containers with appropriate bandwidth, such as VC12s/VT1.5, VC3s/STS–1s, or VC4s/STS–3c. Both high order and low order concatenation are supported, moreover, virtual concatenation with LCAS (Link Capacity Adjustment Scheme) providesr customer with powerful dynamic bandwidth adjustment scheme to fit various needs. Basic feature list as follows: •

Multi encapsulation mode supported: –

GFP Generic Framing Procedure (ITU–T G.7041)

–

LAPS Link Access Procedure SDH (ITU–T X.86/X.85)

–

BCP PPP Bridge Control Protocol (RFC 1662/2878)

•

Low order/High order Contiguous and Virtual Concatenation supported

•

Container supported:

•

–

VC12–xv (x = 1 to 63)

–

VC3–xv (x = 1 to 3)

Differential delay compensation = 48 ms

[4] Bus converter The task of the Bus converter is to translate 19 Mb/s A/D bus to 155 Mb/s data stream. [5] SDH interfacing with Back Panel (TTF and LVC) The TTF block is connected to the two central boards (MATRIXN) through 1 +1 links @622 Mbit/s in LVDS. TTF (Transport Terminal Function) block provides SDH termination for Regenerator Section and Multiplex Section. The LVC block is connected both to the HPC matrices and to the LPC matrices on the MATRIXN card through couple of 1+1 links @ 622 MBit/s working in protection, LVDS format, STM–4 equivalent capacity. LVC circuits perform the HOA function (Higher Order Assembler) and the Lower Order functions LTCM or LTCT sink, LPOM or LSUT sink, LSUT source and LTC source up to 4 STM1 equivalent.

1AA 00014 0004 (9007) A4 – ALICE 04.10

[6] Microprocessor It is a microcontroller controlling and supporting the Ethernet functionalities, such as: configuration, alarms and states collections, performances monitoring, communications with the Shelf Controller (SC, on MATRIX unit) and with the OS, etc. It communicates with the SC by means of the configuration bus for SDH functions (SDH–CS), coming from the Management bus ISPB (intra shelf parallel bus). It is provided with relevant devices SDRAM (for data memory) and Flash EPROM (for program memory).

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This block is used to read/write from/to the ”RIBUS” serial stream (SPI: serial peripheral inventory), to control the LED on the unit, to release the Management–bus in case of power failure, and to use the remote inventory. RIBUS I/F is powered by the + 3.3 VS supplied by the rear access panel. The following information/alarms coming from the boards are collected and sent to EQUICO: –

Card type and slot identification

–

Alim alarm : it arises in case of card power failure

–

ISPB control: it disables the card access to the ISPB bus in case of board power failure or incase of generic board failure.

–

LED control: it commands the on/off status of the green/red INT LED present on each card.

Moreover the component permits to read/write the remote inventory. [8] Power supply This block converts the 48/60 V power supply, to obtain the voltages used to supply all the components in the board. Ethernet card internally uses five different power voltages. The following voltages are needed: +3.3V , +2.5V, +1.8V, +1.5V, +3.3VS. The other functions implemented on the board are: •

REMOTE INVENTORY It is the memory containing the board information, for identification purposes (see para. 3.17 on page 358 for details).

•

M–BUS Driver It drives the input–output gates of the Management–bus (ISPB: intra–shelf parallel bus). These drivers can be disabled (by the Bus–OFF signal) in case of power failure. DC/DC CONVERTERS

1AA 00014 0004 (9007) A4 – ALICE 04.10

•

ED

LEDS and Push–buttons The board presents, on its front panel, nine LEDs, the use and meaning of the LED and of the frontal connectors is reported in Figure 42. on page 131.

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[7] RIBUS interface

MATRIX MAIN AND SPARE

Link H

1+1

Link X

1+1

Link L

1+1

BUS

from/to

TTF

CONVERTER LVC

1

8

ÎÎÎ ÎÎÎ

From/to SDRAM

Ethernet Physical Interface

Ethernet Switch

Ethernet Mapper (GFP, LAPS)

Module

ÎÎÎ ÎÎÎ

Configuration & Status

SNMP

RESTART MICROPROCESSOR SDRAM FLASH EPROM M–BUS Driver

CMISS Bus–OFF 1.5V

Remote Inventory ID

1.8V 3.3 V

DC/DC CONVERTERS

Unit Failure

RIBUS I/F

RIBUS (SPI) F

2.5 V

+3.3 Vdc

48/60 V

from CONGI

internal voltages

PowerSync.

from/to

Management Bus (ISPB)

MATRIX MAIN AND SPARE

1

8

from/to EQUICO

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System clock a System clock b

1AA 00014 0004 (9007) A4 – ALICE 04.10

ISA ES1–8FE unit

Figure 267. ISA ES1–8FE block diagram

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The description of the board is similar to the ISA ES1–8FE (refer to paragraph 4.36 on page 504) taking into account that ISA ES1–8FX has eight 100 Base FX Optical SFP module instead of 10/100 Base T.

4.38 ISA– Ethernet switch (ES4–8FE) The board ISA–ES4–8FE mainly works as a LAN switching and as gateway from the Ethernet traffic towards the SDH network. In particular it provides the service of connecting two LANs and can be applied mainly in three scenario: [1]

Point to point application where a point to point connection is set–up between two routers or switches through an SDH network.

[2]

Ring application where local interfaces add/drop Ethernet traffic on a ring of virtual concatenated paths in the SDH network.

[3]

HUB application where several switches or routers convey traffic towards a single machine (for example POP router)

The connections to the Ethernet network are accomplished by means of 8 local 10/100 Base T ethernet interfaces located on the front of the board, and 16 ethernet over SDH interfaces through back–panel which has a 622 Mbit/s equivalent throughput. The front panel hosts also one Small Form factor Pluggable module supporting a Gigabit Ethernet interface, the ninth local interface. The SDH container used for Ethernet data transportation are VC–4, VC4XV (only when Gbit Ethernet interface will be managed) VC–3, VC–12, VC3XV and VC12XV. The main functions implemented on the board are the following: [1]

Ethernet Physical interface

[2]

Ethernet Switch module

[3]

Ethernet Mapper (GFP/LAPS)

[4]

SDH interfacing to Back Panel (TTF and LVC)

[5]

Local Microprocessor

[6]

RIBUS interface

[7]

Power supply

1AA 00014 0004 (9007) A4 – ALICE 04.10

[1] Ethernet Physical interface This block supports the eight 10/100 Mbit/s ports. The 10/100 Mbit/s Ethernet MAC block is IEEE 802.3, 802.3x and 802.3ac compliant and supports Full Duplex only for 10/100 Mbit/s Ethernet MAC (MAC implements the IEEE 802.3 MAC Control layer and PAUSE operation for flow control) mode of operation; autonegotiation is also supported.

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4.37 ISA– Ethernet switch (ES1–8FX)

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[2] Ethernet Switch module In ISA ES4–8FE board, 25 ports are used, in which 8 of them for 100BASE–T line side interface, one for 1000Base SX, LX, ZX while other 16 for SDH mapper. The basic functions supported are following listed: • • • • • • • •

MAC based forwarding and autolearning VLAN based forwarding 802.1Q VLAN add/remove/swap Stacked VLAN (802.1Q format) add/remove/swap Multicast/Broadcast 802.3x flow control 802.1Q Priority bits management for queuing, WFQ scheduling Policing and bandwidth allocation

[3] Ethernet Mapping over SDH (GFP/LAPS) Ethernet packets are encapsulated and mapped into SDH frames for transmission. Ethernet mapper supports 16 independent channels for EOS (Ethernet Over SDH) encapsulation. Each channel can be mapped with multi SDH containers with appropriate bandwidth, such as VC12, VC12XV, VC3, VC3XV, VC4 or VC4XV (with local Gb Ethernet interface) Both high order and low order concatenation are supported, moreover, virtual concatenation with LCAS (Link Capacity Adjustment Scheme) provides customer with powerful dynamic bandwidth adjustment scheme to fit various needs. Basic feature list as follows: •

Multi encapsulation mode supported: –

GFP Generic Framing Procedure (ITU–T G.7041)

–

LAPS Link Access Procedure SDH (ITU–T X.86/X.85)

–

BCP PPP Bridge Control Protocol (RFC 1662/2878)

•

Low order/High order Contiguous and Virtual Concatenation supported

•

XV Container supported: According to the port configuration two different operation mode are available for ISA ES–4–8FE as explained in the table below: XV container supported

1AA 00014 0004 (9007) A4 – ALICE 04.10

XV type

SMII operating mode

GMII operating mode

VC12–xv

(x = 1 to 50)

(x = 1 to 63)

VC3–xv

(x = 1 to 2)

(x = 1 to 12)

VC4–xv

(x = 1 )

(x = 1 to 4 )

The choice between SMII or GMII operation is made via Craft Terminal. •

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[5] SDH interfacing with Back Panel (TTF and LVC)

TTF (Transport Terminal Function) block provides SDH termination for Regenerator Section and Multiplex Section. The LVC block is connected both to the HPC matrices and to the LPC matrices on the MATRIXN card through couple of 1+1 links @ 622 MBit/s working in protection, LVDS format, STM–4 equivalent capacity. LVC circuits perform the HOA function (Higher Order Assembler) and the Lower Order functions LTCM or LTCT sink, LPOM or LSUT sink, LSUT source and LTC source up to 4 STM1 equivalent. [6] Local Microprocessor It controls and supports the Ethernet functionalities (Ethernet Physical Interface, Ethernet Switch Module and Ethernet Mapper): configuration, alarms and states collections, performances monitoring, communications with the OS (SNMP). The microprocessor is provided with relevant devices SDRAM (for data memory), Flash EPROM (for program memory) and Compact Flash. External Shelf Controller (SC) controls SDH related circuits by ISPB bus. [7] RIBUS interface This block is used to read/write from/to the ”RIBUS” serial stream (SPI: serial peripheral inventory), to control the LED on the unit, to release the Management–bus in case of power failure, and to use the remote inventory. RIBUS I/F is powered by the + 3.3 VS supplied by the rear access panel. The following information/alarms coming from the boards are collected and sent to EQUICO: –

Card type and slot identification

–

Alim alarm : it arises in case of card power failure

–

ISPB control: it disables the card access to the ISPB bus in case of board power failure or incase of generic board failure.

–

LED control: it commands the on/off status of the green/red INT LED present on each card.

Moreover the component permits to read/write the remote inventory. [8] Power supply This block converts the 48/60 V power supply, to obtain the voltages used to supply all the components in the board. Ethernet card internally uses five different power voltages.

1AA 00014 0004 (9007) A4 – ALICE 04.10

The following voltages are needed: +3.3V , +2.5V, +1.8V, +1.5V, +3.3VS.

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The TTF block is connected to the two central boards (MATRIXN) through 1 +1 links @622 Mbit/s in LVDS.

1AA 00014 0004 (9007) A4 – ALICE 04.10

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

The other functions implemented on the board are:

ED

•

REMOTE INVENTORY It is the memory containing the board information, for identification purposes (see para. 3.17 on page 358 for details).

•

M–BUS Driver It drives the input–output gates of the Management–bus (ISPB: intra–shelf parallel bus). These drivers can be disabled (by the Bus–OFF signal) in case of power failure.

•

LEDS and Push–buttons The board presents, on its front panel, one LED, the meaning of which is reported in Figure 43. on page 132. A push–button for the microprocessor restart is present on the front of the unit.

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Link X

1+1

Link L

1+1

4XSTM–1

1

8

ÎÎÎ ÎÎÎ

From/to SDRAM

1XSMII

2xSMII

(8 Fast Ethernet) Ethernet

Ethernet Physical Interface

ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ

(16 FE)

Switch

2XGMII

2xGMII

Module

Ethernet Mapper (GFP, LAPS)

(2 GB E)

(1 Gbit Ethernet)

from/to EQUICO

SFP module

ISPB

1

IBM

not used

SNMP

RESTART

MICROPROCESSOR

CONTROL BUS BRIDGE

Management Bus (ISPB)

M–BUS Driver

COMPACT FLASH

CMISS

internal voltages

Bus–OFF Remote Inventory

1.5V

ID

1.8V 3.3 V

DC/DC CONVERTERS

Unit Failure

RIBUS I/F

RIBUS (SPI)

from/to

CPLD

F +3.3 Vdc

2.5 V

48/60 V

from CONGI

FLASH EPROM

MATRIX MAIN AND SPARE

SDRAM

ISA ES4–8FE

1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 268. ISA ES4–8FE block diagram

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1+1

PCI

GIGABIT ETH Interface

ETHERNET INTERFACE 10 /100 BASE T

LVC

Link H

from/to

TTF

MATRIX MAIN AND SPARE

System clock a System clock b

4.39 ISA ES–16

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(Refer to Figure 269. on page 517) ISA ES16 unit has a throughput towards the SDH network of 2.5 Gbit/s and it hasn’t any local Ethernet interfaces on the front pane (stand–alone operation)l. The board is able to manage local Ethernet interfaces, but it has to be equipped together with the access card, which has to be plugged into the Access Area. The Access Card, which can be used in conjunction with ISA ES–16 are: –

14x Fast Ethernet access card for providing 14 FE local interface;

–

Gigabit Ethernet Access Card for providing up to four Gigabit Ethernet Local interfaces with SFP optical plugs, which can be 1000B– SX/LX/ZX.

Note: independently of the configured Ethernet local interfaces, the maximum number of ports towards SDH network (managed by Q3) is 64, while the number of ports of the switch can be increased up to 78 if the Fast Ethernet Access Card is applied or up to 68 if the Gigabit/s Access Card is applied. The management and control of those local interfaces is in charge of SNMP. The board mainly works as a LAN switching and as a gateway from the Ethernet traffic towards the SDH network. In particular the board can be used mainly for providing three services: –

Virtual Private Line: point to point application where a point to point is set–up between two routers or switches through a SDH network: the ISA ES–16 can be directly connected to the customer using the local interface of the Access Cards, or the connection to the customers can be remotized using for istance the Fast Ethernet Boards.

–

Virtual Private LAN service: multipoint to multipoint application, where each port of the customer can be connected to every other ports of its virtual private LAN. The forwarding of the Ethernet flows is based on proper classification process taking into account the SLA and the load of the network local interfaces. The topology exploiting this application could be for example a ring topology where the customer local or remote interface add/drop Ethernet traffic on a ring of (virtual) paths in the SDH network. In this way ISA ES–16 work as switch distributed in the network.

–

Broadband access service (hub application scenario) where several switches or routers convey traffic towards a single machine (for example a POP router).

The Ethernet traffic, opportunely mapped in the SDH transport structures, is then sent towards the SDH Matrix through the back–plane which has STM–16 equivalent throughput. This represents the maximum throughput of the board which depends also by the subrack slot. The Ethernet frames can be mapped in different types of SDH Virtual Containers (according the chooses of the operator) using the Frame based GFP (Generic Frame Procedure) protocol, LAPS (Link Access Procedure– SDH) protocol or PPP (Point to Point protocol) protocol over HDLS (High level Data Link Control).

1AA 00014 0004 (9007) A4 – ALICE 04.10

The board is able to forward frames on port numbering, VLAN tag, priority coding, MAC Destination address, but also on MPLS (Multi Protocol Label Switching) label; It supports the Martini encapsulation for transporting the VLAN tagged Ethernet frames into MPLS network.

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–

4.5 Gbit/s layer 2 switching

–

SDH capabilities:

–

–

•

STM16 Ho/STM4 LO

•

virtual concatenation: up to 64 VCG groups

•

hitless LCAS (Link Capacity Adjustment Scheme)

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Main functionalities:

Protocol support: •

POS (Packet Over SDH)

•

GFP

•

IEEE 802.3 Ethernet (10/100 or GBE)

Switching based on: •

Stacked VLAN

•

MPLS

•

MAC learning

–

HW support for EPS:

–

Ethernet access through FE access module or GBE acc module

ISA ES 16 is a single height module that fits in any port slot 1660SM equipment. The equivalent backplane capacity is 1xSTM4 in normal slot or 2xSTM4 in enhanced slots Local data access are available through access slot equipped with 14xFE access card or 4xGBE access card. When attached to 4xGBE access card the input traffic must be reduced in order not to overflow the fabric: in such a case backplane traffic is not affected, while GBE traffic can be reduced by means of 802.3 flow control protocol (pause frames). ISA ES–16 board supports the EPS protection scheme 1+1 where the main and spare position are assigned by management system in a flexible way (refer to paragraph 3.13.1 on page 311 for details). Data enter ES16 embedded in SDH streams by the matrixes and as Ethernet frames from Access Cards. Data connection with Matrixes is realized with MUX/DEMUX and G.A. block.

1AA 00014 0004 (9007) A4 – ALICE 04.10

MUX/DEMUX is connected to main and enhanced NGI ports supporting data up to 4 equivalent STM1 in normal slot and 8xSTM1 in enhanced slot. MUX/DEMUX is configured to talk to G.A block in 16xSTM1 mode; G.A. block generates a STM16 stream to “VCG management block” that handles up to 64 VCGs (Virtual Concatenation Group) with LCAS protocol; also terminates layer 2.5 on each group (GFP, LAPS and POS)..

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Although “VCG management block” can transport several type of layer 2 or 3 formats, foreseeable applications of ISA ES16 only calls for transport of Ethernet and MPLS frames. Extracted frames are sent for further processing to “ETHERNET Mapper” block the function of which are: –

Serial link alignment

–

frame delineation

–

storing of frames entering from SPI3 and access card and forwarding to AD FPGA

–

reassembling of ethernet frames received from AD FPGA and forwarding to Access card

–

format adaptation of segments coming from AD directed to Calla48

ISA ES16 UNIT is connected to FE or GE “access card” directly by “ETHERNET Mapper” block. “Ethernet Mapper” block interfaces to “Layer 2 processing” block through 2 monodirectional 13 LVDS links bus at 450 Mbps. In Rx direction full packet are transferred across the interface. Each packet is prepended with a control word carrying indications of input port, length and other service information. In Tx direction, segments of up to 128 bytes are transferred across the interface: “Ethernet Mapper” block dispatches data to Ethernet reassembling circuitry or to “VCG management” block. Ethernet packets are processed by “Layer 2 processing” block to: –

decode protocol header, up to eight nested protocols or MPLS labels can be extracted

–

search flow and session to which the packet belong

–

policing the streams according to session parameters

–

monitor the traffic with inflow and outflow counters

–

schedule forwarding of packets

–

encapsulation of outgoing packets

Output port, encapsulation and assigned quality of service of outgoing packets depend on a subset of input port, VLAN tags, MAC address and MPLS labels. “Layer 2 processing” block and the local microprocessor cooperates in dynamically learning and obsoleting MAC addresses. Local Microprocessor

1AA 00014 0004 (9007) A4 – ALICE 04.10

It controls and supports the Ethernet functionalities (Ethernet Physical Interface, Ethernet Switch Module and Ethernet Mapper): configuration, alarms and states collections, performances monitoring, communications with the OS (SNMP). The microprocessor is provided with relevant devices SDRAM (for data memory), Flash EPROM (for program memory) and Compact Flash. External Shelf Controller (SC) controls SDH related circuits by ISPB bus.

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This block is used to read/write from/to the ”RIBUS” serial stream (SPI: serial peripheral inventory), to control the LED on the unit, to release the Management–bus in case of power failure, and to use the remote inventory. RIBUS I/F is powered by the + 3.3 VS supplied by the rear access panel. The following information/alarms coming from the boards are collected and sent to EQUICO: –

Card type and slot identification

–

Alim alarm : it arises in case of card power failure

–

ISPB control: it disables the card access to the ISPB bus in case of board power failure or incase of generic board failure.

–

LED control: it commands the on/off status of the green/red INT LED present on each card.

Moreover the component permits to read/write the remote inventory. The other functions implemented on the board are: •

REMOTE INVENTORY It is the memory containing the board information, for identification purposes (see para. 3.17 on page 358 for details).

•

M–BUS Driver It drives the input–output gates of the Management–bus (ISPB: intra–shelf parallel bus). These drivers can be disabled (by the Bus–OFF signal) in case of power failure. DC/DC CONVERTERS Starting from the 48 dc supplyed by CONGI unit with the aids of internal DC/DC converter, are generated the following voltage: – – – – –

1AA 00014 0004 (9007) A4 – ALICE 04.10

•

ED

3.3 Vdc 2.5 Vdc 1.8 Vdc 1.5 Vdc 1.2 Vdc

LEDS and Push–buttons The board presents, on its front panel, one LED, the meaning of which is reported in Figure 43. on page 132.

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RIBUS interface

from/to ACCESS CARD

1,2 Gb/s DATA

System clock a System clock b

G.A.

Link L

LVC

Link H 1+1

VCG

MUX/ DEMUX

TTF

management

Link X

from/to

Ethernet Mapper

LAYER 2 Processing

1+1

1+1

MATRIX MAIN AND SPARE

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SIPO & PISO

EPS–ISSB from/to EQUICO

RESTART SNMP

PCI

Bus (ISPB)

MICROPROCESSOR

FLASH EPROM

COMPACT FLASH

CONTROL BUS BRIDGE

M–BUS Driver CMISS

internal voltages

Bus–OFF 1.2V

Remote Inventory

1.5V 1.8V 3.3 V

ID

DC/DC CONVERTERS Unit Failure

RIBUS I/F

RIBUS (SPI)

F

2.5 V

+3.3 Vdc

48/60 V

from CONGI

PowerSync.

from/to

Management Bus (ISPB)

MATRIX MAIN AND SPARE

SDRAM

1AA 00014 0004 (9007) A4 – ALICE 04.10

ISA ES16

Figure 269. ISA ES16 unit block diagram

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4.40 4 X ANY HOST C card (4XANYC)

This port realizes the mapping of up to 4 “client” signals, into an equivalent bandwidth up to 16 AU4’s; the client allocation depends on the operative bitrate of client signal to be mapped, so as the availability of 16 AU4’s (rather than 8 AU4’s) is related to the type of slot used for the board equipment (refer to paragraph 3.10 on page 282 for details). AU4’s carrying ’client’ signals mapped can be, then, cross–connected at HO level by MATRIX card. ’Client’ interfacing is performed through specific ’pluggable’ modules. Serial data provided by client modules is then processed by the “primary and secondary 2xANY“ blocks in order to realize a ’bit–per–bit’ mapping of client signals supported, that result, after each block processing, ’virtually concatenated’ into an 8xSTM1 bandwidth. A specific FPGA interfaces the two “primary and secondary 2xANY“ blocks performing ’client mapping’ and then provides the whole SDH chain of functions from HPT to RST; this device allows also the optimization of client allocation into the available 8xSTM1’s, when equipped in ’H.S.’ slots (refer to paragraph 3.10 on page 282 for details). The data signal is, then, exchanged to MATRIX card, through the G.A. block operating as electrical interface: equivalent STM16 is received (transmitted) from FPGA block and provided (received) to MATRIX card with NGI framed format (X, L, H links in Figure 270. ) Note – TTF blocks supported by FPGA and G.A block are used only for interface purpose. An internal oscillator (VCXO 622.08 Mb/s) is hosted in order to handle CRU EPS events (physically on MATRIX unit) with no impact on ’client’ traffic transmitted to line.

TX SIDE –

4 X ANY module blocks: the client receiver interface regenerates the incoming client signal and recovers the relative timing; the interface characteristics are related to client type (refer to paragraph 5.7 on page 583). Line loopback commands for each interface are received by “Alarms and Control” block.

–

Primary and Secondary 2xANY blocks: inside these blocks the HPA function is performed; more in details: • • •

–

client clock adaptation virtual concatenation C2 insertion

HPT block: HPT source is performed for all VC–4 in FPGA block; the following function are performed: •

B3: Bit interleaved parity (BIP–8) is computed over all bits of the previous VC–4 and placed in B3 byte position. G1[1–4]: The number of errors indicated in RI_REI (remote error indication extracted in HPT sk) is encoded in the REI (bits 1 to 4 of the G1 byte) G1[5]: When there is an active RI_RDI (remote defect indication extracted in HPT sk), the RDI indication will be sent in bit 5 of G1 byte. Upon termination of the above conditions, the RDI indication will be removed.

1AA 00014 0004 (9007) A4 – ALICE 04.10

• •

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(Refer to Figure 270. on page 522)

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–

MSA block: it performs 16 POINTER GENERATOR functions in parallel, according to ITU and ETSI, on an AU–4 mapping basis.

–

MST block: it is located in FPGA and performs Multiplex Section Termination Source: •

K2 byte is also processed for RDI insertion. RDI is inserted according to sink function consequent actions; S1: Byte S1 is inserted; B2: The error monitoring byte B2 is allocated in the STM–16 for a multiplex section bit error–monitoring function. This function is a bit interleaved parity (BIP–24) code using even parity as defined in Recommendation G.707. The BIP–24 is computed over all bits (except those in the RSOH bytes) of the previous STM–16 frame and placed in the 3x16 respective B2 byte positions of the current STM–16 frame. M1: The number of errors detected by monitoring B2 in the sink side is passed to the source side via the aREI and is encoded in the MS–REI (byte M1) according to 9.2.2.12/G.707.

• •

•

–

RST block: FPGA block implements the RST source functions listed here below. •

B1: The error monitoring byte B1 is allocated in the STM–16 for a regenerator section bit error monitoring function. This function is a bit interleaved parity 8 (BIP–8) code using even parity as defined in Recommendation G.707. The BIP–8 is computed over all bits of the previous STM–16 frame the RSn_CP after scrambling. The result is placed in byte B1 position of the RSOH before scrambling. A1, A2: Frame alignment bytes A1 and A2 (3 x 16 of each) are generated and inserted in the first row of the RSOH. Scrambling is performed according to Recommendation G.707, which excludes the first row of the STM–16 RSOH (9x16 bytes, including the A1, A2, J0 and bytes reserved for national use or future international standardization) from scrambling.

• •

RX SIDE –

RST block: FPGA block implements the RST sink functions listed here below. • •

The STM–16 frame alignment process is performed according to G.783 Recommendation. After the recovery of the frame phase start the received signal is descramblered using the generator polynomial specified in G.707 Recommendation. B1 check is performed. Even bit parity is computed for each bit ”n” of every byte of the preceding scrambled STM–16 frame and compared with bit ”n” of B1 recovered from the current frame in order to detect errored blocks

•

–

MST block: it is located in FPGA block and the function performed are listed below; •

B2: The 3 x 16 error monitoring B2 bytes are recovered from the MSOH. A BIP–24–16 code is computed for the STM–16 frame. The computed BIP–24–16 value for the current frame is compared with the recovered B2 bytes from the following frame and errors are reported . B2 Errored Block events happened during the last second are reported in an “Alarms and controls” block register. B2 Errored Block is also used to calculate total number of errored blocks. M1: MS–REI information is decoded according to G.707 from byte M1 and reported as a 1 second count MS–REI Errored Block events happened during the last second are reported in an “Alarms and controls” block register. MS–REI indication is also used to calculate total number of remote errored block. K2: MS AIS detection

1AA 00014 0004 (9007) A4 – ALICE 04.10

•

•

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MSA block: pointer detection process. The pointer interpreter can detect two defect conditions: • •

Loss Of Pointer (LOP); AU–AIS.

If either of these defect conditions are detected, then a logical all–ones (AIS) signal is generated –

HPT block: •

B3: The error monitoring byte B3 is recovered. BIP–8 is computed for the VC–4 frame. The computed BIP–8 value for the current frame is compared with the recovered B3 byte from the following frame. The process for detecting excessive errors and signal degrade is described in ITU–T Reccomandation. G.806. B3 Errored Block event happened during the last second of VC–4 #0 are reported in “Alarms and controls” block register. B3 Errored Block of VC–4 #0 are also used to calculate total number of errored block. G1[1–4]: The REI is recovered and the derived performance primitives is reported for processing. G1[5]: The RDI defect is processed as described in ITU–T Reccomandation. G.806. C2: Unequipped defect is detected (refer to G.783)

• • • –

HPA block:

1AA 00014 0004 (9007) A4 – ALICE 04.10

The following function are performed:

ED

•

C2 extraction: Byte C2 is recovered from VC–4 #0. If a dPLM is detected (see ITU–T G.806), then it will be reported in an “Alarms and controls” block register.

•

H4 extraction: Multiframe indicator is derived from the H4 byte. The received H4 value is compared to the next expected value in the multiframe sequence. The H4 value is assumed to be in phase when it is coincident with the expected value. If several H4 values are received consecutively not as expected but correctly in sequence with a different part of the multiframe sequence, then subsequent H4 values will be expected to follow this new alignment. If several H4 values are received consecutively not correctly in sequence with any part of the multiframe sequence, then a loss of multiframe (LOM) event is reported. When several H4 values have been received consecutively correctly in sequence with part of the multiframe sequence, then the event will be ended and subsequent H4 values will be expected to follow the new alignment.

•

extraction of payload from packets and process the header content

•

automatic client based band and latency preset

•

client clock adaptation

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–

1AA 00014 0004 (9007) A4 – ALICE 04.10

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

The other functions implemented on the board are: •

RIBUS I/F This block is used to read/write from/to the ”RIBUS” serial stream (SPI: serial peripheral inventory), to control the LED on the unit, to release the Management–bus in case of power failure, and to use the remote inventory. RIBUS I/F is powered by the + 3.3 VS supplied by the rear access panel.

•

REMOTE INVENTORY It is the memory containing the board information, for identification purposes (see para. 3.17 on page 358 for details).

•

M–BUS Driver It drives the input–output gates of the Management–bus (ISPB: intra–shelf parallel bus). These drivers can be disabled (by the Bus–OFF signal) in case of power failure. DC/DC CONVERTERS This block converts the 48/60 V power supply, to obtain the voltages used to supply all the components in the board.

ED

•

LEDS and Push–buttons The board presents, on its front panel, one LED, the use and meaning of the LED and of the frontal connectors is reported in Figure 42. on page 131.

•

Alarms and Controls This block collect the alarm detected on the board and also sends commands like loopbacks.

•

Buses The main buses on the board are: RIBUS: also called SPI (serial peripheral bus), from the SC (shelf controller on MATRIX unit), to communicate inventory and peripheral data. M–BUS: called also ISPB (Intra Shelf Parallel Bus), from the SC (shelf controller on MATRIX unit), to communicate data about SDH asics and traffic configuration, SDH alarms collection, performance monitoring, etc.

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Client #3

ÏÏ Ï Ï ÏÏ

#3 #3 4xANY module

Client #2

Secondary 2xANY

#2 #2

HPA Vitual Concatenation

ÏÏ Ï Ï ÏÏ

Client #4 #4

FPGA

G.A. X

HPT

FRAMER MST/RST (*)

MSA

TTF

H

ÏÏ Ï Ï ÏÏ

System clock a System clock b

ÏÏ ÏÏÏ Ï ÏÏÏÏÏÏ

CDR

ÏÏ Ï ÏÏ

Internal STM–16 Frame

CMISS

Management Bus (ISPB)

Configuration & Status

CLIENT PHYSICAL INTERFACE

L

(*)

M–BUS Driver Bus–OFF

Remote Inventory

4xANY module #4 details

from/to

4xANY module

RIBUS ID

Unit Failure

#1 #2 #3 #4

RIBUS I/F

F

+3.3 Vdc

ALARMS & CONTROLS

1.8V 3.3 V 2.5 V

DC/DC CONVERTERS

1.5 V

1AA 00014 0004 (9007) A4 – ALICE 04.10

(*)– TTF blocks are used only for interface purpose

Figure 270. 4 x ANY HOST C card block diagram

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HPA Vitual Concatenation

#1

MATRIX MAIN AND SPARE

Client #1

VCXO 622.08

Primary 2XANY

from CONGI

4xANY module #1

4.41 COADM1

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(Refer to Figure 271. on page 524) The COADM1 board is two slots wide and can be plugged in every slot of the Access Area without constraint. COADM 1 channel unit realizes wavelengths multi–demultiplexing allowing to add/drop 1 ch out of the 8 supported according to CWDM grid and the pass–through of remaining WDM channels not terminated. One specific item per ITU–T channel is foreseen: – – – – – – – –

1470 nm. 1490 nm. 1510 nm. 1530 nm. 1550 nm. 1570 nm. 1590 nm. 1610 nm.

The functionality of the board has to be considered for ring application, and performing ’one side’ channel termination: thus, two separate boards are required at a node of the ring in order to achieve the complete OADM functionality. Actual OADM functionality is based on specific devices performing mux/demux functionality as regards the channel to be locally terminated (by specific add/drop port) and supporting both bidirectional WDM ports for ’network connection’ and bidirectional WDM ports for ’pass–through’ connection (to/from opposite OADM board). ’Loss of Signal’ detection on CWDM optical signal received is provided in order to support the standard management of OMSN’s and sent to the Shelf Controller via RIBUS block. The CWDM LOS detection allows the operator to realize an efficient and specific maintenance of the network in case of break of ring/linear cables carrying multiplexed signals. The wavelength, which is added/dropped in COADM1, is specified in one of the additional fields of the board Remote Inventory. The configuration of the COADM1 requires the operator to specify the added/dropped wavelength. The operator has to connect the bundle of pass–through channels between two COADM1 boards (respectively on west and east side of the NE). Note – The bundle of a COADM1 cannot be connected to the bundle of another COADM1 with different added/dropped wavelength.

1AA 00014 0004 (9007) A4 – ALICE 04.10

Remote inventory is handled by a dedicated EEPROM carrying the inventory code associated to the optical device; the communication towards Shelf Controller is performed by ’RIBUS block” through ’SPI’ bus.

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CWDM

λx

1xx0

λx

1xx0

output signal

CWDM λgrid – λx OADM CWDM input signal

CWDM λgrid – λx LOS DETECTION LOS HANDLING To/From OADM opposite side Remote Inventory EEPROM

RIBUS

COADM1 unit

SPI bus

TO / FROM Shelf Controller

1AA 00014 0004 (9007) A4 – ALICE 04.10

on MATRIX board

Figure 271. COADM1 unit block diagram

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To/From colored port or transponder

4.42 COADM2

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(Refer to Figure 272. on page 526) The COADM2 board is two slots wide and can be plugged in every slot of the Access Area without constraint. OADM 2ch board realizes wavelengths multi–demultiplexing allowing to add/drop 2 ch out of the 8 supported according to CWDM grid and the pass–through of remaining WDM channels not terminated. Four specific items are foreseen, considering to support the termination of two adjacent wavelengths per item: –

1470 – 1490 nm;

–

1510 – 1530 nm;

–

1550 – 1570 nm;

–

1590 – 1610 nm.

The functionality of the board has to be considered for ring application, and performing ’one side’ channel termination: thus, two separate boards are required at a node of the ring in order to achieve the complete OADM functionality. Actual OADM functionality is based on specific devices performing mux/demux functionality as regards the two channels to be locally terminated (by specific add/drop port) and supporting both bidirectional WDM ports for ’network connection’ and bidirectional WDM ports for ’pass–through’ connection (to/from opposite OADM board). ’Loss of Signal’ detection on CWDM optical signal received is provided in order to support the standard management of OMSN’s. The CWDM LOS detection allows the operator to realize an efficient and specific maintenance of the network in case of break of ring/linear cables carrying multiplexed signals. The two wavelengths, which are added/dropped in COADM2, are specified by the content of the additional fields of the board Remote Inventory. The configuration of the COADM2 requires the operator to specify the added/dropped wavelengths. The operator has to connect the bundle of pass–through channels between two COADM2 boards (respectively on west and east side of the NE). Note 1 – The bundle of a COADM2 cannot be connected to the bundle of a COADM1. Note 2 – The bundle of a COADM2 cannot be connected to the bundle of another COADM2 with different added/dropped wavelengths.

1AA 00014 0004 (9007) A4 – ALICE 04.10

Remote inventory is handled by a dedicated EEPROM carrying the inventory code associated to the optical device; the communication towards Shelf Controller is performed by ’RIBUS block through ’SPI’ bus.

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CWDM λgrid – λx–λy

CWDM

λx λy

1xx0

λx λy

1xx0

output signal

1xx0

OADM CWDM λgrid – λx–λy

CWDM input signal

1xx0

LOS DETECTION LOS HANDLING To/From OADM opposite side Remote Inventory EEPROM

RIBUS

COADM2 unit

SPI bus

TO / FROM Shelf Controller

1AA 00014 0004 (9007) A4 – ALICE 04.10

on MATRIX board

Figure 272. COADM2 block diagram

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To/From colored port or transponder

4.43 COMDX8

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(Refer to Figure 273. on page 528) MUX/DEMUX 8ch board realizes wavelengths multi–demultiplexing on the whole group of 8 CWDM channels supported. One item is, then, foreseen. The functionality of the board can be considered both for linear and ring application; contrary to OADM board, no ’pass–through’ link is provided, then pass–through of wavelengths not terminated must be realized on each single wavelength. In ’ring’ application, the board performs ’one side’ channels termination: thus, two separate boards are required at a node of the ring in order to achieve the complete OADM functionality. ’Loss of Signal’ detection on CWDM optical signal received has to be provided in order to support the standard management of OMSN’s. The CWDM LOS detection allows the operator to realize an efficient and specific maintenance of the network in case of break of ring/linear cables carrying multiplexed signals. The COMDX8 board is two slots wide and can be plugged in every slot of the Access Area without constraint. Specific devices performs mux/demux functionality as regards the whole group of 8 channels to be locally terminated (by specific add/drop port). Bidirectional WDM ports for ’network connection’ are also supported. Remote inventory is handled by a dedicated EEPROM carrying the inventory code associated to the optical device; the communication towards Shelf Controller is performed by ’RIBUS block“ through ’SPI’ bus. The functionality of ’Loss of signal’ received on CWDM input of ’passive’ boards is handled as showed in the following Figure 273. An optical splitter is used in order to provide a low percentage of CWDM power level received to a detection stage including a large bandwidth photodetector and the specific HW for the generation of a LOS primitive.

1AA 00014 0004 (9007) A4 – ALICE 04.10

LOS alarm is reported through ’RIBUS block’ towards Shelf Controller on MATRIX unit.

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(from colored port or Transponder interface)

INPUT CHANNELS (to colored port or Transponder interface)

λ1 λ2 λ3 λ4 λ5 λ6 λ7 λ8

1470 1490 1510

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OUTPUT CHANNELS

λ1 λ2 λ3 λ4 λ5 λ6 λ7 λ8

CWDM

1530 1550

MUX

1570 1610 1590

1470 1490 1510

LOS HANDLING

1530 1550

DEMUX

CWDM input signal

Optical Splitter

1570 1610 1590

LOS DETECTION

x% of CWDM Rx signal

LOS alarm

MUX/DEMUX8 unit

Remote Inventory EEPROM

RIBUS

SPI bus

TO / FROM Shelf Controller

1AA 00014 0004 (9007) A4 – ALICE 04.10

on MATRIX board

Figure 273. MUX/DEMUX8 (COMDX8) block diagram and LOS detection in ’passive’ boards

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4.44 2xCH Transponder SFP without optics (COWLA2)

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(Refer to Figure 274. on page 533) This board realizes the function of double multi–rate transponder–regenerator in CWDM network. Double because it has two channels, multi–rate because it can handle various kinds of standard signals, transponder–regenerator because it can work both as transponder and as regenerator. Each channel of COWLA2 is constituted of two bi–directional optical interfaces on which is realized ’3R’ functionality (Re–amplification, Reshaping and Retiming). When working as transponder the optical interfaces of the COWLA2 channel are one ’B&W’ and one colored, so wavelength assignment is performed. On the contrary if both optical interfaces of the channel are colored, COWLA2 works as regenerator. Double ’B&W’ optical interface configuration, regenerator ’B&W’, isn’t foreseen because not applicable in the 1660SM (with CWDM unit) network scenarios. Colored interfaces, ’server or WDM domain’, are input–output of others equipment resident boards; these perform Coarse Wavelength Division Multiplexing using optical multiplexer–demultiplexer or Optical Add–Drop Multiplexer passive components. ’B&W’ lines, ’client domain’, are typically connected toward remote generic ’B&W’ clients. COWLA2 unit supports the following signal types: – – – – – – – – – – – – –

FDDI (125 Mb/s); Fast Ethernet (125 Mb/s); STM1/OC3; Escon (200 Mb/s); Digital Video (270 Mb/s); STM4/OC12; Fiber Channel (1.0625 Gb/s); FICON (1.0625 Gb/s); Gb Ethernet (1.25 Gb/s); 2 Fiber Channel (2.125 Gb/s); STM16/OC48; 2 Gb Ethernet (2.5 Gb/s); STM16 w/ FEC (2.667 Gb/s).

not operative in current release not operative in current release not operative in current release not operative in current release not operative in current release not operative in current release not operative in current release not operative in current release not operative in current release not operative in current release not operative in current release not operative in current release

In case of SDH services the board performs the management of Regeneration Section overhead on Rx direction. For all others standard signals only ’3R’ functionality is foreseen without protocol specific handling. For all protocols optical LOS and URU alarms are generated. In case of optical LOS on Rx interface, Automatic Laser Shut down procedure is activated in the correspondent Tx side; at the same time laser shutdown or generic AIS insertion is done in the transponder channel Tx direction. When non–SDH services are configured, COWLA2 performs only ’3R’ functionality; signal is transparently regenerated without protocol specific management.

1AA 00014 0004 (9007) A4 – ALICE 04.10

In case of SDH services, besides ’3R’ regeneration, the following functionalities are realized on received side: –

alignment on received A1, A2 byte and generation of relative LOF alarm

–

received section trace identifier byte J0 extraction and generation of relative TIM alarm. J0 management is configurable as one repeated byte or as 16 byte modality (15 byte + CRC–7)

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received error monitoring byte B1 extraction and manipulation (RS non intrusive monitoring). Performance monitoring computation is done in order to produce DEG and LOWBER alarms. Primitive parameters are passed to Shelf Controller that computes PM handling.

–

RS–AIS (MS–AIS with J0 bit at all ’1’, Alcatel proprietary alarm) detection on the incoming signal and generation of relative RS–AIS alarm.

2xCh transponder SFP is a one slot wide plug–in unit constituted by a front panel and a Printed circuit Board Assembly (PBA). On the front panel are available four connectors for optical lines access and a multi–color LED used as visual indicator for card failure alarm and in–service/standby card operating status. Block diagram of COWLA2 unit is reported in Figure 274. Power supplies for all board components are produced from battery interface through DC/DC converts modules. Optical received signal O Rxm (1 = m = 4) is converted into electrical format, D Rxm, from SFPm photo–detector receiver. This block accomplishes re–amplification and reshaping. Electrical received signal, D Rxm, enters into any–rate deserializer Dxm that realizes signal retiming and 1 to 16 de–serialization. Received de–serialized signals, Dpn Rxm (1 = n = 16, 1 = m = 4) and clock, Ckp Rxm, go into FPGA. FPGA component, basing on configuration provisioning, cross–connect a 16 bit parallel data input, Dpn Rxm, with a 16 bit parallel data output, Dpn Txm. In case of SDH service it’s done received regenerator section overhead bytes management. Parallel signals, Dpn Txm, and clock, Ckp Txm, are sent to the any–rate serializer Mxm that carries out 16 to 1 data multiplexing. Multiplexed signal, D Txm, enters into SFPm laser transmitter that produces the optical output signal O Txm. The bi–directional optical to optical path described above constitutes one transponder channel. FPGA registers are configured from Shelf Controller using ISPB bus. FPGA manages programming and alarms of SFPs and any–rate serializers–deserializers through dedicated serial I2C bus interfaces and parallel input–output. PLLs VCXO loop filter blocks are a constituent part of deserializers’s Clock and Data Recovery circuits and of serializers’s Clock Multiplier Unit. They provide appropriate clock reference for serializer–deserializer components. Configuration device (Config Device) contains the program image that is downloaded into FPGA after power–on.

1AA 00014 0004 (9007) A4 – ALICE 04.10

Board remote inventory information are contained in RI EEPROM, a serial non–volatile memory accessible via SPI bus. RIBUS block basically it reads or writes general input–output for commands activation or alarms acquisition and pilots on–board SPI slave bus. RIBUS is controlled from SC through SPI back–plane bus. In the following various COWLA2 blocks will be described.

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–

SFP OPTICAL MODULE

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SFP optical module is a pluggable fiber optic transceiver that arises from a Multi–Source Agreement. Optical wavelength could be B&W or colored conform to CWDM grid. Line bit–rate could be single speed or multi–rate. On COWLA2 it’s for now foreseen the use of mono–mode, multi–rate B&W or multi–rate 8 wavelength colored SFP, capable of maximum span budget of about 80 Km. Photo detector transceiver and laser transmitter achieve respectively optical to electrical and electrical to optical conversion; In addition there are some configuration and alarm pins: –

Tx fault indicates a laser fault

–

LOS specifies an optical loss of signal

–

Presence reflects the insertion–extraction of the module

–

Tx disable when set shuts down the laser

–

Rate select is an optional command for data rate select for multi–rate transceiver.

These signals are input–output of FPGA and can be read–written using dedicated registers. Tx disable and LOS are used by FPGA for ALS functionality. Tx disable, LOS and Presence are also connected to RIBUS block for testing or future utilization. SFP module includes a 512 bytes serial EEPROM, that contains inventory and vendor specific information. This EEPROM can be read and written via ISPB bus.

SERIALIZER/DESERIALIZER

“Deserializer” main functions are clock recovery, data re–sampling and 1 to 16 de–serialization over a continuous bit–rate from 30 Mb/s up to 3.2 Gb/s.

1AA 00014 0004 (9007) A4 – ALICE 04.10

“Serializer” main functions are data re–timing and 16 to 1 serialization over a continuous bit–rate from 30 Mb/s up to 3.2 Gb/s.

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FPGA

–

flexible any rate data channel cross connection

–

E–SNCP/I (for all services) E–SNCP/N (for SDH services) protection schemes toward client or server domain

–

Automatic Laser Shut down procedure implementation

–

STMn Regenerator Section bytes termination for SDH services

–

laser shut down or generic AIS insertion on Tx transponder channel direction when a LOS is detected on Rx side

–

SFP and serializer/deserializer management by ISPB.

DC/DC CONVERTERS Power supply block produces the required on board supplies starting from 48 V ± 20 % battery input . All components work with 3.3 V voltage except FPGA that requires also 1.5 V.

ISPB BUS By mean of ISPB the Shelf Controller (SC) can load proper configuration setting within FPGA internal register, monitor the current status and alarms, collect data for performance monitoring and so on.

RIBUS block This block is used to read/write from/to the ”RIBUS” serial stream (SPI: serial peripheral inventory), to control the LED on the unit, to release the Management–bus in case of power failure, and to use the remote inventory. RIBUS I/F is powered by the + 3.3 VS supplied by the rear access panel.

REMOTE INVENTORY

1AA 00014 0004 (9007) A4 – ALICE 04.10

It is the memory containing the board information, for identification purposes (see para. 3.17 on page 358 for details).

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Its main functions are:

D Rx 1

O Tx 1

SFP #1 MODULE D Tx 1

FPGA

SERIALIZER DESERIALIZER #1

O Rx 2

D Rx 2

O Tx 2

SFP #2 D Tx 2 MODULE

CROSS–CONNECTION MATRIX STMn RS Sink GENERIC AIS

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O Rx 1

SERIALIZER DESERIALIZER #2

O Rx 3

D Rx 3

O Tx 3

SFP #3 MODULE D Tx 3

SERIALIZER DESERIALIZER #3

O Rx 4

D Rx 4

SFP #4 MODULE

O Tx 4

SERIALIZER

D Tx 4

DESERIALIZER #4 #1 #2 #3 #4

ALARMS &

Ï Ï Ï Ï ÏÏÏ Ï

CONTROLS

Configuration & Status Management Bus (ISPB) M–BUS Driver Bus–OFF RIBUS(SPI) ID

3.3 V

CMISS

Remote Inventory

1.5V

+3.3 Vdc

F

DC/DC CONVERTERS

from CONGI

internal voltages

Unit Failure

RIBUS I/F

1AA 00014 0004 (9007) A4 – ALICE 04.10

2XCH TRANSPONDER SFP W/O OPTICS

Figure 274. 2xCH Transponder SFP Without optics COWLA2

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4.45 EQUICO card

The EQUICO unit through the Equipment Controller (EC) manage: •

local dialog with a personal computer (F interface)

•

dialog with the Operation System for Network Management operation through Q3 and DCC interface

•

dialog with a remote Operation System for Network Management operation through interface QAUX .

•

dialog with the external equipment for Network Management operations through Interface Q2 (Mediation Device Function)

•

remote alarms (RE) , alarms criteria towards the rack lamps (RA), housekeeping alarms (HK) and front cover led

•

ISSB bus

The EC performs as well all the SW functions related to the control and management activities like info–model processing, event reporting and logging, equipment data base management, SW downloading and management, etc. To support its activities the EC function requires a non volatile mass storage device (FLASH CARD), boot memory (FEPROM) and RAM memory. F interface: It is used for connection to a local Craft Terminal; The standard implementation of the physical layer for the F interface consists of an RS–232 UART port accessible from the EQUICO card front panel Q3 interface: It is dedicated to an OS station connection through Local Access Network (LAN); QB3 requires a 10BASE2 or a 10BASET interface that is physical provided by CONGI card DCC interface: It is a TMN related communication interface based on the use of the Embedded Communication Channels available in the SOH portion of the SDH frame. Through the QECC interface the 1660SM can exchange management messages with a remote OS. In the 1660SM up to three full duplex ECC channels can be terminated from each SDH interface: one DCC_M at 576 kbit/s, one DCC_R at 192 Kbit/s and one DCC_P 64 Kbit/s (F2, F3 bytes of VC4 ). QAUX interface:

1AA 00014 0004 (9007) A4 – ALICE 04.10

It is provided as an additional TMN communication interface for message exchange between the NE and a Remote OS station based on the use of a 2 Mbit/s proprietary protocol. It can be physically terminated on a 2 Mbit/s auxiliary channel on the SERVICE card. Q2 interface: A mediation function interface is provided to connect the 1660SM to non–SDH network element The RS–485 interface and the cable connector are provided on the CONGI card.

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(See Figure 275. on page 536 )

RE, RA, HK and leds interface:

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RE consists of parallel I/O signals used for remote alarms that can be accessed on the CONGI card RA is dedicated to send commands toward the rack to light up the relevant lamps.; the physical interface is available on the CONGI card. By pressing a push button is possible to store an alarm; HK consist of parallel I/O signals used to handle housekeeping signals (for example alarms received from Fans Subrack, open door etc.); In this way they can be supervised by Craft Terminal. The physical interface is available on the CONGI card. The Equipment Controller also drive the leds present on the front cover to display alarms or status indication concerning the equipment ; for the meaning of the leds see para 2.4 on page 120. By pressing a push button present on the EQUICO front cover is possible to check the efficiency of the leds. ISSB bus: It is an high performance bus supporting communication among the EC function, the SC function on the MATRIX and Local Microprocessor present on the ATM board. Other functions implemented are : •

RESET PUSH–BUTTON used for EC reset.

•

RIBUS I/F This block control the LED on the unit and is also used by the Shelf Controller on the MATRIX to read the remote inventory data though the ”RIBUS” . RIBUS I/F is powered by the + 3.3 Vdc supply by CONGI boards.

•

REMOTE INVENTORY It is the memory containing the board information, for identification purposes (see para. 3.17 on page 358 for details).

1AA 00014 0004 (9007) A4 – ALICE 04.10

DC/DC CONVERTERS This block converts the 48/60 V power supply to secondary voltages necessary for the circuits on the board: +3.3 V and + 2.5 V used to supply all the components in the board.

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F INTERFACE

DCC

DCC MANAGEMENT

To/from STM–N port

Q2 To/from CONGI

Q3

EC

QAUX

Reset

To/from SERVICE

ISSB

To/from MATRIX main and spare, ATM board

Lamp test Remote alarms RE

FEPROM

Alarm storing

REMOTE ALARMS Rack alarms RACK LAMPS RA HOUSEKEEPING Housekeeping LEDS HK

RAM

MANAGEMENT

FLASH CARD

front cover leds Remote Inventory

RIBUS RIBUS I/F

ID

3.3 V

1AA 00014 0004 (9007) A4 – ALICE 04.10

2.5 V

From/to MATRIX main and spare

+3.3 Vdc

Unit Failure

EQUICO

To/from CONGI

48/60 V

DC/DC CONVERTERS

from CONGI A & B

Figure 275. 1660SM EQUICO Card Block Diagram

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To/From Craft Terminal

4.46 MATRIX card (MATRIXN)

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(See Figure 276. on page 540) The MATRIX card used in the 1660 SM equipment performs different functions : •

connections between ports (ATM matrix included)

•

equipment synchronization functions

•

Shelf Controller functions

•

performance monitoring collection

•

power supply

•

remote inventory

As the MATRIX is in 1+1 redundant configuration, all the functions realized by the unit are redundant as well. CONNECTIONS The connections between MATRIX and ports are realized by means of links at 622 Mbit/s (link X, link L and link H in Figure 276. on page 540)

1AA 00014 0004 (9007) A4 – ALICE 04.10

On the MATRIX are implemented the following SDH functions to realize the connections : •

MSP (Multiplex Section Protection) It performs the Multiplex Section Protection (linear and MS–PRING) according to the MSP algorithm result. Refer to para 3.13.2 on page 323 for details on MSP linear protection. Refer to para 3.13.8 on page 342 for details on MS–SPRING protection.

•

AU4 squelching It is used to avoid mis–connections when the MS–SPRING protection is active. For each incoming and outgoing AU4 , should be possible to insert AIS.

•

SNCP (Sub–Network Connection Protection) It performs the Sub–Network Connection Protections, in case of SNCP–ring network configuration, switching from A to B path signals (A and B are two generic transmission side). SNCP is of types HO–SNCP (for VC4 path signals) and LO–SNCP (for VC3 ,VC12, etc. path signals). It can be SNCP/I and SNCP/N; Refer to para 3.13.4 on page 327 for details on SNCP protection

•

HPC (High order Path Connection) This block acts as connection matrix, supporting cross–connection for a max of 96x96 STM1 equivalent signals at VC–4 level.

•

LPC (Low order Path Connection) This block acts as connection matrix, supporting cross–connection for a max of 64x64 STM1 equivalent signals at VC–12 level. In this condition the HPC matrix has a max capacity of 32x32 STM1 equivalent signals at VC–4 level.

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The equipment synchronization is realized by the SETS function (Synchronous Equipment Timing Source) that distributes to each equipment port the pertaining synchronization signals. A high stability oscillator at 10MHz is present to guarantee an holdover or free running working mode compliant to the ITU–T Recs. The clock reference working modes can be: locked, hold over and free running. When working in locked mode , the SETS block can select its reference signal among (the selection is accomplished by means of the software and craft terminal): • • •

timing reference signals coming from the SDH ports (T1 ) 2 MHz signal coming from the PDH ports (T2 ) 2 MHz clocks (T3) or 2 Mbit/s signals (T6) coming from the SERVICE card The T3/T6 clocks are two (i.e. T3a, T3b or T6a, T6b).

The SETG block (Synchronous Equipment Timing Generation) generates : •

a system clock T0 (at 622.08 MHz) locked to the selected reference (T1, T2, T3/T6) and distributed to the equipment. CK38Mhz : it is derived from the system clock (T0) and is distributed to all the ports. Its frequency is 38.88 MHz. MFSY : it is the multiframe synchronism at 500 Hz, obtained from the ck38MHz. It is distributed to all the ports. a 2 MHz clock T4 or a 2 Mbit/s signal T5 used as synchronization clock towards the external, accessible from the SERVICE board. The T4/T5 clocks are two (T4a, T4b and T5a, T5b).

• • •

For a detailed description of the synchronization subsystem refer to para 3.14 at page 351. SHELF CONTROLLER FUNCTIONS The MATRIX houses the circuitry necessary to realize the Shelf Controller. The SC provide the resources to support the SW functions related to the control and management operation of the boards. To perform its functions, the SC directly interfaces the ASICS on the board implementing the SDH functions for data collection (faults or alarm event detections, performance monitoring data) and configuration provisioning. As the SC is involved in critical activities ( for instance EPS ) , is 1+1 protected.

1AA 00014 0004 (9007) A4 – ALICE 04.10

The internal interfaces supporting SC element for communication tasks are: –

Management –Bus. It is a parallel bus connecting the SC processor to all the transport Asics located on the traffic cards to provide communications among the units and the Controller, for management of the units (management of payload processing functions).

–

ISSB : Intra Shelf Serial Bus is a serial bus for communication among SC, EC (on the EQUICO card) and , if present, other processor in the Shelf.

–

RIBUS . It is a serial bus connecting the SC processor to the serially interfaced devices called RIBUS–I/F, located on each board for simple read or write operations, for communications about Remote Inventory, cards failure, bus releasing. RIBUS I/F is powered by the + 3.3 Vdc supply by CONGI boards.

A push–button is present to reset the SC.

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EQUIPMENT SYNCHRONIZATION

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For a detailed description of the Controller refer to para 3.12 on page 304, where the control subsystem is described. PERFORMANCE MONITORING COLLECTION The “Performance Monitoring Management” block housed on the MATRIX card realizes Performance Monitoring functionalities; it collects and stores the data ( Defect seconds and Errored blocks) coming from all the flows. The Performance monitoring can be made at : • • • • • •

Adaptation and Regeneration section Multiplex section Multiplex section adaptation HSUT and LSUT HPOM and LPOM HPT and LPT

POWER SUPPLY The unit receives via backpanel connectors the –48V coming from CONGI boards. The DC/DC converter present on the board generates the following voltage: • • • •

+ 3.3 V + 2.5 V +1.8 V +1.6 V

The Remote–Inventory and RIBUS–I/F blocks are powered by the 3.3 V power service coming from the CONGI boards . REMOTE INVENTORY It is the memory used to maintain the board history and data.

1AA 00014 0004 (9007) A4 – ALICE 04.10

For more details about the Remote Inventory function refer to para 3.17 on page 358.

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PERFORMANCE MONITORING MANAGEMENT

MATRIX LPC

MSP SNCP

AU4 Squelcing

Link L Link H

from/to all port cards

HPC Link X T2 T1 (port)

Timing & Synchronization (SETS)

T0 10MHz OSC

T3a/T6a T3b/T6b

SETG

T4a/T5a T4b/T5b

Reset

MFSY CK38 T0

T0

Management bus

SC

Remote Inventory

Unit Failure

RIBUS

ID From/to spare MATRIX and EQUICO

ISSB

3.3 V 2.5 V 1.8 V

1AA 00014 0004 (9007) A4 – ALICE 04.10

MATRIX

to ports

From/to spare MATRIX and ports

+3.3 Vdc RIBUS I/F

RIBUS

to/from SERVICE

Management bus

M–BUS Driver Bus OFF

FLASH EPROM (1 Mb)

from ports

48/60 V DC/DC CONVERTERS

+3.3 Vdc

from CONGI A & B

1.6 V

Figure 276. MATRIX card block diagram

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4.47 CONGI card

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(See Figure 277. on page 545) The 1660SM equipment can house two CONGI cards, referred as CONGI A main (slot 10) and CONGI B (slot 12). They are not intended as main and spare : each card provides a set of functions . Both units are necessary to provide the complete set. CONGI A can be used as stand alone but in this case only a subset of interfaces can be used . Table 52. reports the interfaces present on each CONGI card. Table 52. CONGI A and CONGI B interfaces CONGI A (slot 10)

CONGI B (slot 12)

POWER

POWER

Housekeeping & Remote Alarms (a subset)

Housekeeping & Remote Alarms ( a subset)

Rack lamps (R/M)

Not used

QMD (Q2)

Not used

Q3 10 base 2

Not used

Q3 10 base T

Not used

INT led

INT led

1AA 00014 0004 (9007) A4 – ALICE 04.10

The main functions performed by the unit are: [1]

Input power stage

[2]

AND/OR and Remote Alarms

[3]

Housekeeping interface (only on CONGI in slot 10)

[4]

R/M interface (only on CONGI in slot 10)

[5]

QMD interface (only on CONGI in slot 10)

[6]

RIMMEL interface

[7]

Q3/QB3 interface (only on CONGI in slot 10)

[8]

Remote inventory

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This circuit decouples the power station battery . It contains the ”Main Power block” with two fuses, EMI input filters, a ”protection circuit block” , a ”step up converter” to provide –9 V and a DC/DC converter to provide the +3.3 V to the RIBUS I/F block ( see para. 3.17 on page 358 for details ). In case of fuse broken an alarm is generated (FUSE)2. A solder strap is present to provide the main power (48V) in modality “two wires” (if +Vbatt is connected to ground or “three wire” (if + Vbatt is not connected to ground) in order to obtain a DC/I decoupling system. [2] AND/OR and Remote Alarms The circuit generates the remote alarms and lights up the the Rack lamps in case of station battery fault. It is powered from the 3.3Vdc power from the service battery and uses it to control the station battery. In case of loss of 3.3 Vdc a PWANDOR alarm is generated. The AND/OR circuit monitors the station battery and provides an alarm (BAT FAIL) in case the voltage level decreases more than 20 % of the nominal value. If BAT FAIL alarm of the CONGI in slot 10 or the same alarm of the CONGI in slot 12 are present , the ORALIM alarm is generated and set to the EQUICO card. Table 53. on page 542 and Table 54. on page 543 report a brief description of the alarms provided by the AND/OR block respectively on CONGI in slot 10 and CONGI in slot 12 . They are all Electronic Ground contacts (GND = alarm, OPEN = no alarm) sent towards the housekeeping and remote alarms connector. Table 53. Remote alarm provided by the AND/OR block available on CONGI in slot 10 ACRONYM T*TOR

T*INT

Fault or loss of one station battery . It concurs to generate NURG, T*NURG and RNURG (it can be stored) Fault or loss of both batteries stations. It concurs to generate T*URG and RURG (it can be stored). It indicates an internal alarm. It is received from EQUICO

T*URG

It indicates an urgent alarm. It is provided from EQUICO

T*NURG

It indicates a not urgent alarm. It is received from EQUICO

T*AND

N.B.

1AA 00014 0004 (9007) A4 – ALICE 04.10

DESCRIPTION

On the Craft Terminal (C.T.) and on the Operation System (O.S). application the T*URG, and T* NURG remote alarm are named in a different way; the relation between this two terminology is explained in Table 72. on page 609.

2. For the right management of the FUSE alarm refer to MAINTENANCE section of the METRO OMSN C.T Operator’s Handbook. As a matter of fact some setting must be checked when two CONGI with different Factory code / ANV suffix are equipped in the subrack.

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[1] Input power stage

Table 54. Remote alarm provided by the AND/OR block available on CONGI in slot 12

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ACRONYM T*TORC

DESCRIPTION It indicates a loss of +3.3V generated by the on board DC/DC converter of one CONGI card. Indeterminate alarm synthesis. Indicate synthesis of alarms not associated to other severity (not used) It indicates an EQUICO microprocessor fault (it can be stored)

T*IND T*TUP T*TANC

It indicates loss of + 3.3 V generated by the on board DC/DC converters of both CONGI cards (it can be stored). It indicates loss of communication with the Operation System (not used)

LOSQ2

[3] Housekeeping interface Two Housekeeping operating mode are supported for CONGI unit: –

CONGI unit preset 2 wire provide 6 inputs and 2 outputs contacts suitable for customer purpose.

–

CONGI unit preset 3 wire provide 4 inputs and 2 outputs contacts suitable for customer purpose.

[4] R/M interface It is used to connect the rack lamps and incoming call signal. Table 55. Rack lamps signals ACRONYM

FUNCTION

T*RATTD

alarms storing

T*RURG

urgent alarm

T*RNURG

not urgent alarm

T*CH

incoming call

T*TOR

absence of one battery

N.B.

On the Craft Terminal (C.T.) and on the Operation System (O.S). application the T*RURG, and T* RNURG remote alarm sent toward the rack lamp are named in a different way; the relation between this two terminology is explained in Table 72. on page 609.

[5] QMD interface It is a RS–485 interface that allows the dialogue between the NE (EC function) and a non SDH equipment. In this case the NE acts as a mediation device. [6] RIMMEL interface

1AA 00014 0004 (9007) A4 – ALICE 04.10

This block provide a serial communication interface with the FANS Shelf in order to receive information like presence of fans unit, fan alarms, fans unit remote inventory etc. (for details about connection with FANS Shelf refer to Installation Handbook). “Rimmel block” is also connected with the Shelf Controller (housed on the MATRIX) and Equipment Controller (housed on the EQUICO) in order to: –

manage the HOUSEKEEPING contact

–

provisioning remote alarm

–

read the 2/3 wire operating mode

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[7] Q3/QB3 interface

–

2 BNC for 10 Base 2 connection type

–

RJ45 for 10 base T connection type.

The Coaxial Transceiver Interface (CTI) circuit performs the driver/receiver interface between the Q3/QB3 coaxial cable ( BNC) and the universal ethernet adapter (AUI). The purpose of the AUI adapter is to adapt the signal, coming from the Equipment Controller on the EQUICO, to the LAN interface. It is directly connected to the RJ45 connector or through CTI to BNC connector.

[8] Remote inventory

1AA 00014 0004 (9007) A4 – ALICE 04.10

It is the memory used to maintain the board history and communication and routing data relevant to the NE ;Remote Inventory activity is managed by the RIBUS I/F block as described on para. 3.17 on page 358.

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The Q3/QB3 interface on CONGI is used for OS connection. Two connectors are available :

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2/3 wire mode + Batt_A Station battery – Batt_A

Fuse

Input Power Stage MAIN

– Batt

POWER BLOCK

Fuse

EMI FILTER

TO ALL BOARDS

+Batt STEP UP CONVERTER

–9V

PROTECTION CICUIT BLOCK

+3.3Vdc TO ALL BOARDS

DC/DC 3.3 V

to RIBUS I/F Fuse BAT FAIL

48V 20%

PWANDOR

OR ALIM

OR

RACK LAMPS

BAT FAIL

R/M AND/OR

HOUSEKEEPING AND REMOTE ALARM

URG, NURG, LOSQ2, INT, UP

To

EQUICO

To other CONGI To

EQUICO

To EQUICO From other CONGI alarms from EQUICO

REMOTE ALARM 6/4 HOUSKEEPING_IN

HK–IN

2 HOUSKEEPING_OUT

HK–OUT RIMMEL

FANS unit FANS management

to/from EQUICO and MATRIX

Serial Link

NON SDH EQUIPMENT

QMD INTERFACE (Q2)

to/from EQUICO

M U X

TRANSCEIVER

not used

–9V

OPERATION SYSTEM 10BASE2

COAX TRANSCEIVER INTERFACE (CTI)

10BASET

FAIL

Q3 INTERFACE

UNIVERSAL ETHERNET INTERFACE ADAPTER (AUI)

Remote Inventory

M U X

to/from EQUICO not used

+3.3 Vdc

RIBUS I/F

RIBUS

CMISS

to/from MATRIX main and spare

1AA 00014 0004 (9007) A4 – ALICE 04.10

CONGI

Figure 277. CONGI – Block diagram

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4.48 SERVICE card

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(See Figure 278. on page 551) The SERVICE card provides the following functions : [1]

AUX (auxiliary) channels management

[2]

Input/output clock management

[3]

EOW channels management

[4]

POWER SUPPLY for internal board use.

[1] AUX channels management It provides : –

four G.703 64 Kbit/s channels, ITU–T G.703 compliant

–

four V11 channels , every one composed by data input, data output and clock

–

four RS–232 channels

–

two 2 Mbit/s G.703 signals that can be used as auxiliary channels

All the electrical interfaces are managed by the Matrix present on the unit. [2] Input/Output clock management Function performed: –

the unit can receives up to two 2 MHz clock (T3a and T3b) or up to two 2Mbit/s signals (T6a and T6b) that could be used to synchronize the N.E. The unit provide software programmability to switch between the two mode.

–

the unit provides up to two 2 MHz clock (T4a and T4b) or up to two 2Mbit/s signals (T5a and T5b) that can be used by another N.E. for synchronism purpose. The unit provide software programmability to switch between the two mode.

[3] EOW management The EOW channels allows to realize two different connections types: a)

between two stations (selective call)

b)

omnibus call (one station is connected with all the other

To this purpose a telephone jack is present on the unit front panel.

1AA 00014 0004 (9007) A4 – ALICE 04.10

Two extension channels with different connectors (RJ45 and RJ11) are available to establish a connection with an external telephone set. Moreover the channel on RJ11 can be used to establish a connection with an external telephone network (future application). The ”Omnibus call” is identified with ”00”.

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Two LEDs L1 and L2 indicate the line status according to the type of call . Table 56. on page 547 and Table 57. on page 547 show the L1 and L2 LEDs meaning for a selective/multiple call and for the omnibus call. Table 56. L1, L2 LEDs status for selective call STATUS

CALLING PARTY

CALLED PARTY

THIRD PARTY

L1 (green)

L2 (yellow)

L1 (green)

L2 (yellow)

L1 (green)

L2 (yellow)

Line engaged

ON

––

ON

––

ON

––

Selective call

ON

––

F

––

ON

––

Replay to selective call

ON

––

ON

––

ON

––

Third party inclusion

ON

––

ON

––

ON

––

Third party inclusion allowed

ON

ON

ON

––

ON

––

Third party selection ended

ON

ON

ON

––

F

––

Reply to third party

ON

––

ON

––

ON

––

Clear third party

ON

––

ON

––

ON

––

Clear forward

ON

––

ON

––

––

––

Clear back

ON

––

ON

––

––

––

Table 57. L1, L2 LEDs status for omnibus call

1AA 00014 0004 (9007) A4 – ALICE 04.10

STATUS

CALLING PARTY

CALLED PARTY REPLY

NO ANSWER FROM CALLED PARTY

L1 (green)

L2 (yellow)

L1 (green)

L2 (yellow)

L1 (green)

L2 (yellow)

Line engaged

ON

––

ON

––

ON

––

Omnibus call

ON

––

F

F

F

F

T < 60 seconds An answer at least

ON

––

ON

F

F

F

T < 60 seconds Called party inclusion

ON

––

ON

ON

F

F

T > 60 seconds An answer at least

ON

––

ON

F

ON

F

T > 60 seconds Called party inclusion

ON

––

ON

ON

ON

F

Third party exclusion

ON

––

ON

F

ON

F

Clear back

ON

––

ON

F

ON

F

Clear forward

––

––

––

––

––

––

LEGENDA ON : LED on fixed –– : LED off F : LED flashing

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The connection between two stations is made when the operator selects the service area desired and the phone number of the station to call. The logical sequence of the main operations about the connection is the following: 1)

Manual selection of the zone where we want to call, pushing Selection Button. The relative Zone’s Led will show the selection (ORANGE color).

2)

Verify the state of the line in the zone: –

Leds L1 and L2 show the state of the line

–

Free or Engaged Tone are sent to the Phone

3)

If the line is free and the Inclusion Button is pushed, the phone will be linked to the Party Line of the selected zone and the zone becomes engaged. The Green Led L1 will be ON on all stations of the zone.

4)

Selection of the phone number on the keyboard telephone handset

5)

Recognize call on called station The called station recognize the phone number and the consequent action is that the led L1 (Green) will flash and the buzzer will ring.

6)

Start of the conversation When the user hangs on the phone the conversation shall start In this condition the buzzer will be off and the led L1 (green) will be on.

7)

End of the conversation

1AA 00014 0004 (9007) A4 – ALICE 04.10

The connection will finish when the caller or the called user will hang off the phone making free the zone.

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Selective call

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Omnibus call The Omnibus connection between one station and all the others in one zone is made when the operator selects the service area desired and the Omnibus call phone number ’00’. The logical sequence of the main operations about the connection is the following: 1)

Manual selection of the zone where we want to call, pushing Selection Button. The relative Zone’s Led will show the selection (ORANGE color).

2)

Verify the state of the line in the zone: –

Leds L1 and L2 show the state of the line

–

Free or Engaged Tone are sent to the Phone

3)

If the line is free and the Inclusion Button is pushed, the phone will be linked to the Party Line of the selectioned zone that becomes engaged. The Green Led L1 will be ON on all stations of the zone.

4)

Selection of the phone number that is 00 for an Omnibus call.

5)

Recognize call on called station the leds L1 (Green) and L2 (Yellow) will flash and the buzzer will ring.

6)

Start of the conversation When the called users hang on the phone the conversation shall start. In this situation the buzzer will be off, led L1 will be on (green) and led L2 will be flashing (yellow). During the conversation, the caller talks and all the other users listen to, but if any of the other users press the Inclusion Button they shall talk in the Omnibus Call while the button remains pressed.

7)

End of the conversation The connection will finish when the caller will hang off the phone making free the line. In the Omnibus call when the users called want to finish the listening, they hang off the phone.

Matrix

1AA 00014 0004 (9007) A4 – ALICE 04.10

The Matrix: –

receives / transmits data from /to the electrical interfaces (G.703, V11, RS–232, 2 Mbit/s, 2Mhz)

–

receives configurations data from ”Management Bus”

–

receives/transmits a serial signal from/to the digital party line (serial port)

–

receives /transmits data (SOH bytes) from/to the STM–N ports and EQUICO and realize cross connections.

–

receives clock and synchronism from the MATRIX

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Digital party line

–

manages the information coming from the SOH matrix

–

detects DTMF code coming from the different channels

–

party line

–

manages LEDs , buzzer , push buttons and speech extensions present on the card front unit

–

receives configuration information from the ”Management Bus”

AD/DA This block is a voice–band audio processor and perform the transmit encoding (A/D conversion) and receive decoding (D/A conversion) together with transmit and receive filtering for voice–band communication systems. Other functions implemented are : •

RIBUS I/F This block is used to read/write from/to the ”RIBUS” stream, to control the LED on the unit, to release the Management–bus in case of power failure, and to use the remote inventory:

•

REMOTE INVENTORY It is the memory containing the board information, for identification purposes (see para. 3.17 on page 358 for details).

•

M–BUS Driver It drives the input–output gates of the Management–bus. These drivers can be disabled (by the Bus–OFF signal) in case of power failure.

[4] POWER SUPPLY The unit receives via backpanel connectors the –48V coming from CONGI boards. The DC/DC converter present on the board generates the following voltage: • • •

+ 3.3 V + 2.5 V to supply the party line and the SOH Matrix – 9 V to supply the phone

1AA 00014 0004 (9007) A4 – ALICE 04.10

The Remote–Inventory and RIBUS–I/F blocks are powered by the 3.3 V power service coming from the CONGI boards .

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The function performed by the Digital Party Line are:

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2 x 2 Mbit/s

2 x 2MHz input

T3a/T6a T3b/T6b

2 x 2MHz output

T4a/T5a T4b/T5b

4 x 64 Kbit/s

AUX

G.703

QAUX OH MATRIX

DCC

to/from EQUICO

T3 T4

G.703

ck system A ck system A

V.11

4 x V.11

to/from STM–N ports

51 MHz RS–232

4 x RS232

L1 L2 Z1

Z8

Serial Port

2.5 V Config. & Status

Buzzer zone selection line reset line seizure

DIGITAL PARTY LINE

M–BUS Driver

RAM RJ11 External Phone extension

AD/DA

RJ45 External Phone extension

AD/DA

Telephone

AD/DA

to/from MATRIX main and spare

Management Bus

Bus–OFF

Remote Inventory

RIBUS

RIBUS I/F

FAULT

–9V 3.3 Vdc 3.3 V 2.5 V –9 V

48/60 V

from CONGI A& B

DC/DC CONVERTERS

1AA 00014 0004 (9007) A4 – ALICE 04.10

SERVICE

Figure 278. SERVICE block diagram

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4.49 FAN UNIT FOR FAN SHELF 19”

The FANS SHELF 19” is composed by a mechanical structure and a back–plane. The Fan Shelf is used to prevent high temperature inside the 1660SM equipment and must be equipped with four FAN UNIT FOR FAN SHELF 19” and two DUST FILTER FOR FAN SHELF 19”. In the lower part of the shelf are present 5 connectors the meaning of which is explained in Figure 76. on page 165. Each FANS UNIT is composed by four fans and some electronic circuits necessary to: •

fans and alarms management

•

dust filter management

•

remote inventory

•

power supply

FANS ALARM MANAGEMENT The core of the FAN UNIT FOR FAN SHELF is the “Fan Controller” that perform the following functionality: –

FAN power supply:at the start up the control of FANS is distributed in sharing mode, so the max current value is reduced at only one FAN at a time.

–

FAN control: the sensing criteria is integrated in order to have an alarm if almost one fan is out of order. If an alarm is present (FAN AL1, FAN AL2, FAN AL3, FAN AL4) because a fan is temporary out of order, the Fan controller try every 8 sec. to restart the fan.

–

Temperature sensor: an external sensor generate an alarm (TEMP AL) when the temperature exceed 55_ C.

–

Remote inventory: through this interface the fan controller read the information stored in the flash EPROM.

–

LED control: the meaning of the led is reported in Figure 76. on page 165.

–

Serial Alarms Interface: the FAN controller reports the alarm on a serial link toward the CONGI board in order to transfer the information to the Shelf Controller on the MATRIXN.

The Fans controller generate an alarm called ALM_URG B #n if at least one fan is faulty or the 12Vdc is not present.

1AA 00014 0004 (9007) A4 – ALICE 04.10

DUST FILTER Two filters are present at the bottom of the fan shelf in order to prevent dusty problem at cooled circuit. This filter could not be removed permanently because the bottom grid performs the function of anti–fire protection. Two electro–mechanical sensor checks if the filters has been removed from the Shelf. These information (FILTER AL1 and FILTER AL2) are than reported to the fan controller of each FAN UNIT FOR FAN SHELF 19”.

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(See Figure 279. on page 554 and Figure 279. on page 554)

1AA 00014 0004 (9007) A4 – ALICE 04.10

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REMOTE INVENTORY It is a flash EPROM where are stored information about the unit like construction date, code number, maker name, Card–type, etc. POWER SUPPLY The main power supply is coming from two connectors: power supply “A” and power supply “B” coming from station battery. The voltage value for both battery is : 48 Vdc ± 20% 3A max; in case of failure an alarm is generated (AL BAT_A, AL BAT_B) A DC/DC converter on the unit provides the 12V necessary to power the FANs. Another DC/DC converter provides the 3.3V power supply voltage from which through a serial regulator is derived a 2.5 V. If one of the above secondary voltage are not present , is generated an alarm (PSU ALM #n).

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BATTERY A BATTERY B

ÏÏ ÏÏ ÏÏ ÏÏ ÏÏ ÌÌ ÏÏÌÌ ÏÏ ÌÌ ÏÏ ÏÏ ÏÏ ÏÏ

FILTER AL1 FILTER AL2

F I L T E R

S E N S O R

SLOT ID

D U S T

FILTER AL1

BATTERY A BATTERY B FILTER AL1 FILTER AL2

BATTERY A

D U S T F I L T E R 2

S E N S O R

BATTERY B FILTER AL1 FILTER AL2 FILTER AL2 SLOT ID

ÏÏ ÏÏ ÏÏ ÏÏ ÏÏÌÌ ÏÏ ÌÌ ÏÏÌÌ ÏÏ ÏÏ ÏÏ ÏÏ

SLOT ID

1

BATTERY A BATTERY B FILTER AL1 FILTER AL2

FAN UNIT FOR FAN SHELF 19” #0

FAN UNIT FOR FAN SHELF 19” #1

ÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏ FAN UNIT FOR FAN SHELF 19” #2

FAN UNIT FOR FAN SHELF 19” #3

PSU ALM #3 PSU ALM #2

> _ 1

PSU ALM

PSU ALM #1 PSU ALM #0

ALM_URG_B #0 ALM_URG_B #1 ALM_URG_B #2

> _ 1

ALM_URG

ALM_URG_B #3

PSU ALM #1

ALM_URG_B #1

PSU ALM #2

ALM_URG_B #2

PSU ALM #3

ALM_URG_B #3

1AA 00014 0004 (9007) A4 – ALICE 04.10

FAN SHELF 19”

Figure 279. Fans shelf 19” general block diagram

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BATTERY B

ÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏ

to CONGI Housekeeping

SLOT ID

BATTERY A

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ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ AL_12V

ALBAT_A

BATTERY A

DC/DC Converter

BATTERY B

DC/DC Converter

+12 V

+12 V

P O W E R

+3.3 V

+3.3 V

+2.5 V

+2.5 V

SERIAL REGULATOR

A L A R M

PSU ALM

ALBAT_B

FANS1

FANS2

FAN AL1

FANS3

FAN AL2

+ 12 V

FANS4

FAN AL3

+ 12 V

FAN AL4

+ 12 V

+ 12 V

ALBAT_B

ALBAT_A

AL_12V

FAN AL3

FAN AL4

FAN AL2

FAN AL1

FAN control 4

FAN control 3

FAN control 2

FAN control 1

TEMP_AL

TEMPERATURE SENSOR

REMOTE

SLOT ID

INVENTORY

FANS CONTROL

FILTER AL1

FILTER

FILTER AL2

ALARM

FAULTY FANS SENSOR

POWER ALARM

LED

FANS CONTROLLER

ALM_URG_A

AL_12V

AL_FAN

SERIAL ALARM INTERFACE A

SERIAL ALARM INTERFACE B

NOT USED

ALM_URG_B

> _ 1

AL_FAN

NOT USED

NOT USED

FANS MANAGEMENT

to CONGI unit

1AA 00014 0004 (9007) A4 – ALICE 04.10

FAN UNIT FOR FAN SHELF19”

Figure 280. Fans unit for fan shelf 19” block diagram

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1AA 00014 0004 (9007) A4 – ALICE 04.10

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3AL 91668 AA AA

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1AA 00014 0004 (9007) A4 – ALICE 04.10

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5 TECHNICAL SPECIFICATIONS Data indicated in the handbook must be considered as standard values Data indicated in the contract must be considered as guaranteed values

5.1 General characteristics Optical Line bit rate

SDH:

Electrical Line bit rate

SDH: 155.520 Mbit/s (STM–1) SONET:155.520 Mbit/s (OC–3) PDH: 139.264 Mbit/s (PDH)

Type of optical fiber

Single mode according to ITU–TG.652, G.654 and Multimode G.651.

Wave length

See Table 63. on page 591, Table 64. on page 593, Table 66. on page 595 and Table 67. on page 597 .

Span length

Depending on fiber type and and optical power budget reported in Table 63. on page 591, Table 64. on page 593, Table 66. on page 595 and Table 67. on page 597 .

Application types

TM and ADM in protected and unprotected linear links and rings DXC (64 STM–1 equivalent port at VC12 level)

Applied standards

ITU–T G.703 for electrical interfaces TU–T G.707 for SDH frame and multiplexing structure ITU–T G.957 and G.958 for optical interfaces ITU–T G.821 and G.826 for transmission quality ITU–T G813 for synchronization ITU–T G.783 and G.841 for network protection architectures ITU–T G.784 and G.774 for system management functions ITU–T G.662 and G.663 for optical amplification

ED

155.520 Mbit/s (STM–1) 622.080 Mbit/s (STM–4) 2488.320 Mbit/s (STM–16) SONET:155.520 Mbit/s (OC–3) 622.080 Mbit/s (OC12)

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Cross–Connections capacity

(96 x 96) STM1 equivalent ports at VC–4 level or (64 x 64) STM1 equivalent ports at VC12 and VC3 levels + (32 x 32) equivalent ports at VC–4 level.

Cross connect features

1660SM has a symmetrical architecture. All traffic port (PDH SDH) of the same type have the same functionality and behavior and there is no inherent split between tributaries and aggregates. This means that it is possible the allocation of the PDH and VCi signals into every port. Connection of concatenated AU4–4c among STM4 and STM–16 ports is supported 125 µs maximum for any traffic pathway

Transmission delay Protections Network protection

SNCP/I and SNCP/N Drop & Continue Single ended 1+1 MSP Dual ended 1+1 MSP Dual ended 1:N MSP 2 fiber MS–SPRING at STM–16 interfaces Collapsed single–node interconnection Collapsed dual–node interconnection ISA–PR packet level ring protection

Equipment protection

1 + 1 MATRIX and Timing EPS 1+1 ATM MATRIX (4X4 and 8x8) EPS 1+1 PR_EA MATRIX EPS 1+1 ISA ES–16 EPS N +1 63x2 Mbit/s EPS (N= 6 max) N + 1 3 x34 Mbit/s EPS (N= 15 max) N + 1 3 x 45 Mbit/s EPS (N= 15 max) N + 1 4 x STM–1 Electrical EPS (N= 15 max)

1AA 00014 0004 (9007) A4 – ALICE 04.10

Management interface Local:

Craft Interface (Personal Computer)

RS232 PC compatible SUB–D 9 pins at 38 Kbit/s

Remote:

Craft Interface (Personal Computer)

RS232 PC compatible SUB–D 9 pins at 38 Kbit/s; it handles up to 31 NEs via DCC (D4 – D12 and/or D1–D3)

Remote:

Transmission Management Network (TMN) interface

G.773 QB3 10 base 2 and 10 base T

Information Model

According to ITU–T (G.774) and ETSI specification

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Add–Drop and Cross connect features

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Remote:

Management messaging with Alcatel Non–SDH equipments (Alcatel proprietary protocol)

Q2 (synchronous, bit rate = 19.2 kb/s) RQ2 (asynchronous, bit rates = 1.2–2.4–4.8–9.6 kb/s)

Protocol Stack/Information Model messages

According to ITU–T G.774 and ETSI rec. ISO–OSI 7–layers reference model. The ATM/IP functions are organized according to TCP/IP reference model; they are managed by means of SNMP protocol tunneling over OSI layers

Dual addressing to O.S.

It allows O.S. redundancy

Operation processes Configuration and provisioning

Equipment, ports, add–drop, cross–connect,synchronization, protection, MCF (Message Communications Function), SEMF (Synchronous Equipment Management Function) OH connection

Software download

It is made locally as well as remotely on non volatile memories without traffic interruption

Performance monitoring

According to G.784, G.826 and G.821.

Unit and Equipment acknowledgement

Through Remote Inventory (Company id, Unit Type, Unit Part Number, Serial Part Number , Software Part Number etc.) For detail refer to Operator Handbook.

Security

Password, operator profile, back–up for programs and data

Output Housekeeping signals (CPO) and Remote Alarms

By electronic relay contacts to be connected to external negative voltage:

Max. guaranteed current with closed condition 50 mA Voltage drops vs. ground with closed condition

–2 V ÷ 0 V

Max. allowed voltage with open condition

–72 V

Input Housekeeping signals (CPI)

1AA 00014 0004 (9007) A4 – ALICE 04.10

Max. guaranteed current with closed condition 3 mA Voltage drops vs. ground with closed condition

–2 V ÷ 0 V

Max. allowed voltage with open condition

–72 V

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Selectable input clock

2048 KHz from 2 Mbit/s port (T2) 2048 kHz external synch clock (2 input, T3a and T3b) or 2048 Mbit/s external synch (2 input, T6a and T6b) STM–N ports (T1)

No. of selected clock (normal mode)

6 max.

Synchronization output

2048 kHz G.703 (2 output, T4a and T4b) or 2048 Mbit/s (2 output T5a and T5b)

Operational modes

Locked to reference Free–run mode ±4.6 ppm (PLL without reference) Holdover mode drift 0.37 ppm max./day ( PLL with stored frequency for more than half an hour,with no selected input frequency)

Synchronization selection

Priority and SSM algorithm

Protection against lighting surges

TNV1 (Telecommunication Network Voltage) for 21 x 2 Mbit/s K20 access module

Additional features:

1AA 00014 0004 (9007) A4 – ALICE 04.10

VCi Signal Label management Programmable alarms severity VC–4, VC–3 and VC–12 Tandem Connection Termination & Monitoring (TCT/TCM) J0 – Section Trace Management J1/J2 Lower Order Path Trace Management (VC–12 and VC–3)

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Clock characteristics

5.1.1 Optical Safety

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5.1.1.1 Hazard Level classification The HAZARD LEVEL classification of the different optical interfaces is given in Table 58. on page 561. The hazard level can be assigned in accordance with the requirements of: –

IEC 60825–1 (1998), IEC 60825–2 (2000) or

–

IEC 60825–1 (1998) + Am. 2 (2001) and IEC 60825–2 (2000)

Table 58. Hazard level classification of different optical interfaces

OPTICAL INTERFACE

UNIT/PORT/ACRONYM

HAZARD LEVEL

STM–1

S–1.1 (short haul)

1

STM–1

L–1.1 (long haul)

3A ; 1M

STM–1

L–1.2 (long haul)

3A ; 1M

STM–1

L–1.2JE1 (long haul)

3A ; 1M

STM–1

MM1

3A ; 1M

STM–4

S–4.1 (short haul)

1

STM–4

L–4.1 (long haul)

3A ; 1M

STM–4

L–4.2 (long haul)

3A ; 1M

STM–16

S–16.1 (short haul)

3A ; 1M

STM–16

L–16.1 (long haul)

3A ; 1M

STM–16

L–16.2 (long haul)

3A ; 1M

STM–16

L–16.2JE2 (long haul)

3A ; 1M

STM–16

L–16.2JE3 (long haul)

3A ; 1M

STM–16

I–16.1 (Intra Office)

STM–16

L–16.2 colored port 16C 6400/12800

1 1M

BST10

1M

BST15

1M

BST17

1M

PR16

1

OPTO TRX 1.25GBE SFP–LX

1000B–LX

1

OPTO TRX 1.25GBE SFP–SX

1000B–SX

1

S–4.1 (short haul)

1

ISA–PR

1AA 00014 0004 (9007) A4 – ALICE 04.10

5.1.1.2 Location type The equipment shall be installed in “restricted locations” (industrial and commercial premises) or “controlled locations” (optical cable ducts and switching centers).

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Output optical interfaces data: the wavelength and the maximum optical power at the output connector of incorporated laser sources is given in Table 63. on page 591, Table 64. on page 593, Table 66. on page 595 and Table 67. on page on 597 . 5.1.1.4 Labelling The labels reported below are put during factory settings, except those (explanatory) concerning the STM–1 ports. In this case the labels are placed in a plastic bag and provided together with the module. The customer shall affix the label on the fibre protection cover of P4E4N, P4S1N units or A2S1 adapter depending on the particular interface of the module (STM–1 port). In the following description it is specified when the label shall be affixed by the customer. The optical interfaces which have HAZARD LEVEL 1 (see Table 58. on page 561) carry the following explanatory label:

The label is put on the fibre protection cover of the following ports: •

STM–1 PORT with S–1.1 interface (P4E4N, P4S1N units or A2S1 adapter – affixed by the customer) STM–4 PORT with S–4.1 interface STM–16 PORT with S–16.1 interface STM–16 PORT with I–16.1 interface PR–16

• • • •

The optical interfaces which have HAZARD LEVEL 3A (see Table 58. on page 561) carry the hazard symbol label:

1AA 00014 0004 (9007) A4 – ALICE 04.10

The label is affixed near the optical connectors on the front plate of the following interfaces: • • • • • • • • • • • • • • •

ED

L–1.1 (STM–1 PORT) L–1.2 (STM–1 PORT) L–1.2JE1 (STM–1 PORT) L–4.1 (STM–4 PORT) L–4.2 (STM–4 PORT) S–16.1 (STM–16 PORT) L–16.1 (STM–16 PORT) L–16.2 (STM–16 PORT) L–16.2JE2 (STM–16 PORT) L–16.2JE3 (STM–16 PORT) L–16.2 (STM–16 colored PORT 6400/12800) BST10 BST15 BST17 ISA–PR

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5.1.1.3 Incorporated laser sources characteristics

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

The optical interfaces which have HAZARD LEVEL 3A (see Table 58. on page 561) and operate at 2nd window, carry the following explanatory label (a multilanguage label kit is also provided):

CAUTION LASER RADIATION WHEN OPEN DO NOT STARE INTO BEAM OR VIEW DIRECTLY WITH OPTICAL INSTRUMENTS

INVISIBLE LASER RADIATION DO NOT STARE INTO BEAM OR VIEW DIRECTLY WITH OPTICAL INSTRUMENTS

CLASS 3A LASER PRODUCT P.MAX=31mW,

= 1300 nm IEC 825 1993

The label is affixed on the fibre protection cover of the following ports: •

STM–1 PORT with L–1.1 interface (P4E4N, P4S1N units or A2S1 adapter – affixed by the customer) STM–4 PORT with L–4.1 interface STM–16 PORT with L–16.1 interface ISA–PR

• • •

The optical interfaces which have HAZARD LEVEL 3A (see Table 58. on page 561) and operate at 3rd window, carry the following explanatory label (a multilanguage label kit is also provided):

CAUTION LASER RADIATION WHEN OPEN DO NOT STARE INTO BEAM OR VIEW DIRECTLY WITH OPTICAL INSTRUMENTS

INVISIBLE LASER RADIATION DO NOT STARE INTO BEAM OR VIEW DIRECTLY WITH OPTICAL INSTRUMENTS

CLASS 3A LASER PRODUCT P.MAX=50 mW,

= 1550 nm IEC 825 1993

The label is put on the fibre protection cover of the following ports: •

STM–1 PORT with L–1.2 interface (P4E4N, P4S1N units or A2S1 adapter – affixed by the customer) STM–1 PORT with L–1.2JE1 interface (P4E4N, P4S1N units or A2S1 adapter – affixed by the customer) STM–4 PORT with L–4.2 interface STM–16 PORT with L–16.2 interface STM–16 PORT with L–16.2JE2 interface STM–16 PORT with L–16.2JE3 interface STM–16 colored PORT 6400/12800

•

1AA 00014 0004 (9007) A4 – ALICE 04.10

• • • • •

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The label is affixed on the fibre protection cover of the following ports: •

STM–1 PORT with L–1.1 interface (P4E4N, P4S1N units or A2S1 adapter – affixed by the customer) STM–4 PORT with L–4.1 interface STM–16 PORT with L–16.1 interface

• •

The optical interfaces which have HAZARD LEVEL 1M and operate at 3rd window (see Table 58. on page 561), carry the following explanatory label (a multilanguage label kit is also provided):

The label is affixed on the fibre protection cover of the following parts: •

STM–1 PORT with L–1.2 interface (P4E4N, P4S1N units or A2S1 adapter – affixed by the customer) STM–1 PORT with L–1.2JE1 interface (P4E4N, P4S1N units or A2S1 adapter – affixed by the customer) STM–4 PORT with L–4.2 interface STM–16 PORT with L–16.2 interface STM–16 PORT with L–16.2JE2 interface STM–16 PORT with L–16.2JE3 interface STM–16 colored PORT 6400/12800 BST10 BST15 BST17

• • • • • • • • •

The multilanguage label kit, for STM–1 ports, is placed in the same plastic bag provided together with the module where explanatory labels (in English language), above mentioned, are put. For all other ports (STM–4 and STM–16), the multilanguage label kit is inserted in the pre–package. The multilanguage label kit contains a set of label that reproduce the same (explanatory) above depicted in the following languages:

1AA 00014 0004 (9007) A4 – ALICE 04.10

• • • •

Italian Francaise Spanish German

The customer, to its own discretion, may stick the labels with appropriate language upon the pre–existing ones or, in case of STM–1 ports, directly on the fibre protection cover of P4E4N, P4S1N units or A2S1 adapter.

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All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

The optical interfaces which have HAZARD LEVEL 1M (see Table 58. on page 561) and operate at 2nd window, carry the following explanatory label (a multilanguage label kit is also provided):

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

N.B.

As an aid to identify the right label to be affixed to an optical module (HAZARD LEVEL 1, HAZARD LEVEL 3A 2nd window, HAZARD LEVEL 3A 3rd window, HAZARD LEVEL 1M 1st window, HAZARD LEVEL 1M 2nd window, HAZARD LEVEL 1M 3rd window) refer to paragraph 2.2 on page 88 where is reported the relationship between the Part number (ex. 3AL 78815AA––) and the interface type (ex. S–1.1) and then refer to Table 58. on page 561 where is reported the relationship between the interface type (ex. S–1.1) and the Hazard Level.

5.1.1.5 Aperture and fiber connectors The locations of apertures and fibre connectors are reported on topographical drawings of units front view and access cards front view in paragraph 2.4 on page 120.

5.1.1.6 Engineering design features In normal operating conditions, unless intentional manumission, the laser radiation is never accessible. The laser beam is launched in optical fibre through an appropriate connector that totally shuts up the laser radiation. Moreover a plastic cover is fitted upon optical connectors by means of screws. In case of cable fibre break, to minimize exposure times, ALS procedure according to ITU–T G.958 Rec. is implemented either on STM–1 port or on STM–4 and STM–16 ports. ALS timing are not longer than maximum specified in G.958.

5.1.1.7 Safety instruction The safety instructions for proper assembly, maintenance, and safe use including clear warning concerning precautions to avoid possible exposure to hazardous laser radiation, are reported in para. 3.2 on page 31 thru 38 and more specifically in para.3.2.4.2 on page 35. 5.1.2 Electrical Safety Electrical Safety Safety status of the connections with other equipments

TNV2 (Telecommunication Network Voltage) for Remote Alarms, Housekeeping Alarms (CPO, CPI), Rack Lamp (RM) SELV (Safety Extra Low Voltage) for all the other

5.1.2.1 Labelling The labels reproduced in para.3.2.3.1 on page 33 are affixed during factory settings. 5.1.2.2 Safety instructions

1AA 00014 0004 (9007) A4 – ALICE 04.10

The safety instructions for proper assembly, maintenance, and safe use including clear warning concerning precautions to avoid possible exposure to hazardous voltages, are reported in para. 3.2 on pages 31 thru 38 and more specifically in para.3.2.3.2 on page 33.

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5.2 Electrical interface characteristics

Type of interface

Electrical according to ITU–T Rec. G.703

Bit rate

2048 Kbit/s  50 ppm

No. of channels

21

Code

HDB3

Signal amplitude

2.37 Vp on 75 Ohm unbalance

Attenuation

0 to 6 dB at 1024 Khz with law Ǹ f

Return loss

w12 dB 51–102 kHz w18 dB 102–2048 kHz w14 dB 2048–3072 kHz

Pulse shape

See ITU–T Rec. G.703

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

5.2.1 21 X 2 Mbit/s 75 Ohm electrical characteristics (A21E1)

5.2.2 21 X 2 Mbit/s 120 Ohm electrical characteristics (A21E1) The electrical characteristics are the same of para 5.2.1 on page 566 except for: Signal amplitude

3 Vp on 120 Ohm balance

5.2.3 21 X 2 Mbit/s 120 Ohm K20 electrical characteristics (A21E1) The electrical characteristics are the same of para 5.2.2 on page 566 except for: Protection against lighting surges

According to ITU–T Rec. K20

1AA 00014 0004 (9007) A4 – ALICE 04.10

5.2.4 3 X 34 Mbit/s electrical characteristics (A3E3) Type of interface

Electrical, according to ITU–T Rec. G703

Bit Rate

34368 Kbit/s " 20 ppm

No. of tributaries

3

Code

HDB3

Signal amplitude

1Vp/75ohms

Attenuation accepted on the incoming signal

0–12dB at 17.184kHz with law pf

Return loss

w12 dB 860–1720 kHz w18 dB 1720–34368 kHz w14 dB 34368–51550 kHz

Pulse shape

as per Fig.17 of ITU–T Rec. G.703

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All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

5.2.5 3 X 45 Mbit/s electrical characteristics (A3T3) Type of interface

Electrical, according to ITU–T Rec. G703 and to ANSI TS 102 Rec.

Bit rate

44.736 Kbit/s " 20ppm

No. of tributaries

3

Code

B3ZS

Signal amplitude

According to ITU–T Rec. G.703 par.5.8 and ANSI T1 102 Rec, Tab.5

Attenuation accepted on the incoming signal

According to ANSI T1 102, Annex A2.5

Pulse shape

as per Fig.14 of ITU–T Rec. G.703 or per Fig.14 of ANSI T1 102 Rec.

5.2.6 STM–1 electrical characteristics (A4 ES1 and ICMI) Type of interface

ITU–T Rec. G.703 compliant

Bit rate

155 520 Kbit/s  20 ppm

Code

CMI

Attenuation accepted on the incoming signal

0–12.7 dB at 78 Mhz with law Ǹ f

Return loss

w15 dB at 8–240 Mhz

Pulse shape

See ITU–T Rec. G.703

1AA 00014 0004 (9007) A4 – ALICE 04.10

5.2.7 140 Mbit/s electrical characteristics (ICMI) Type of interface

ITU–T Rec. G.703 compliant

Bit rate

139264 Kbit/s  15 ppm

Code

CMI

Attenuation accepted on the incoming signal

0–12 dB at 70 Mhz with law Ǹ f

Return loss

w15 dB at 7–210 Mhz

Pulse shape

See ITU–T Rec. G.703

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Speech Channel Interface

Front–panel telephone jack

Handset Impedance

600 ohms

Bandwidth

300 to 3400 Hz

Handset Operating current

18 mA

Input Tx gain

–4/0/0 dB

Output Rx gain

0/–7/0dB

Signalling

DTMF compliant with ITU–T Rec. Q.23

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

5.2.8 Engineering Order Wire characteristics (SERVICE)

Analog EOW Extension Impedance

600 ohms

Bandwidth

300–3400 Hz

Tx level

0 dBr ±0.5 dB

Rx level

0 dBr ±0.5 dB

5.2.9 AUX channels characteristics (SERVICE) Externally accessible data channel (OH bytes termination is Software programmable)

4 x 64 Kbit/s, G.703 codirectional (Rx synchronized) 4 x 64 Kbit/s V11 4 x 9600 baud RS232 2 x 2 Mbit/s G.703

1AA 00014 0004 (9007) A4 – ALICE 04.10

64 Kbit/s (Rx synchronized) G.703 Bit rate

64 Kbit/s

Timing signals

64 Kbit/s and 8 kHz coding style embedded

Bearer

Two balanced pairs (120 ohms): one per route

Coding style

According to ITU–T Rec. G.703 codirectional

Outgoing pulse shape

See ITU–T Rec. G.703

Output Interface characteristics

See ITU–T Rec. G.703

Incoming Interface characteristics

as per the outgoing interface but modified by the characteristics of the interconnection pair. The input circuit can accept an 0 – 3 dB (128 KHz)

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V11 64Kbit/s contradirectional interface

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Type

electrical, according to ITU–T Rec. V11

Receivers Input impedance

> 6 Kohms

Rx levels

”1” or ”OFF” < –0.3 V ”0” or ”ON” > +0.3 V

Drivers Differential output

2 V (Min.)

Use: intrabuilding connections

RS–232 oversampled interface 9600 Kb/s Bit rate

9600 kb/s

Mode

RS–232 Tx & Rx data only

Electrical levels

24 Vpp

Use : intrabuilding connections

1AA 00014 0004 (9007) A4 – ALICE 04.10

2 Mb/s G.703 /G.704 AUX channel interface Electrical

according to G.703 (75 Ohm or 120 Ohm using a special cable)

Attenuation

0 to 6 dB

Return loss

w12 dB 51–102 kHz w18 dB 102–2048 kHz w14 dB 2048–3072 kHz

Pulse shape

See ITU–T Rec. G.703

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5.3 ATM interface characteristics

Throughput towards backpanel

622 Mbit/s

Switching capability

VC and VP switching

PDH containers

E1, E3

SDH containers

VC–12, VC–3, VC–4

Local port

VC–4

Port number

16 (any combination)

Connections

4000 max (VC or VP) unidirectional

VC/VP connection

Hard and Soft VCC/VPC

Policing

UPC and NPC (VC/VP)

Shaping

Input and Output (VC/VP)

Congestion management

SCD, EPD, TPD

OAM

AIS, RDI, CC

Signalling

PNNI

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5.3.1 ATM matrix 4x4 switching capability (ATM4X4)

1AA 00014 0004 (9007) A4 – ALICE 04.10

Table 59. ATM4X4 board: configurable TPs type and max, number Board acronym

max. TPs number

VC4–4C

VC4

VC3

VC12

E1

E3

T3

E1 IMA

ATM4X4

16

No

Yes

Yes

Yes

Yes

Yes

No

No

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5.3.2 ATM matrix 4x4V2 switching capability (ATM4X4V2) Throughput towards backpanel

622 Mbit/s

Switching capability

VC and VP switching

PDH containers

E1, E3,T3

SDH containers

VC12, VC3, VC4

IMA(**) multiplexing

E1 from 1 to 8 channels

Port number

252 (any combination)

Connections

4000 max (VC or VP) unidirectional

VC/VP connection

Hard and Soft VCC/VPC

Policing

UPC and NPC (VC/VP)

Shaping

Input and Output (VC/VP)

Congestion management

SCD, EPD, TPD

OAM

AIS, RDI, CC

Signalling

PNNI

Table 60. ATM4X4V2 board: configurable TPs type and max, number Board acronym

max. TPs number

VC4–4C

VC4

VC3

VC12

E1

E3

T3

E1 IMA

ATM4X4V2

252

No

Yes

Yes

Yes

Yes

Yes

Yes

Yes

1AA 00014 0004 (9007) A4 – ALICE 04.10

(**) For deatailed information about IMA refer to AF–PHY–0086.001

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Throughput towards backpanel

622 Mbit/s

Switching capability

VC and VP switching

PDH containers

E1, E3,T3

SDH containers

VC12, VC3, VC4

IMA(**) multiplexing

E1 from 1 to 8 channels

Port number

16 (any combination)

Connections

4000 max (VC or VP) unidirectional

VC/VP connection

Hard and Soft VCC/VPC

Policing

UPC and NPC (VC/VP)

Shaping

Input and Output (VC/VP)

Congestion management

SCD, EPD, TPD

OAM

AIS, RDI, CC

Signalling

PNNI

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5.3.3 ATM matrix 4x4 D3 switching capability (ATM4X4D3)

Table 61. ATM4X4D3 board: configurable TPs type and max, number Board acronym

max. TPs number

VC4–4C

VC4

VC3

VC12

E1

E3

T3

E1 IMA

ATM4X4D3

16

No

Yes

Yes

Yes

Yes

Yes

Yes

Yes

1AA 00014 0004 (9007) A4 – ALICE 04.10

(**) For deatailed information about IMA refer to AF–PHY–0086.001

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5.3.4 ATM matrix 8x8 switching capability (ATM8X8) Throughput towards backpanel

1.2 Gbit/s

Switching capability

VC and VP switching

PDH containers

E1, E3

SDH containers

VC–12, VC–3, VC–4, VC4–4c

Local port

No

Port number

32 (any combination)

Connections

8000 max (VC or VP) unidirectional

VC/VP connection

Hard and Soft VCC/VPC

Policing

UPC and NPC (VC/VP)

Shaping

Input and Output (VC/VP)

Congestion management

SCD, EPD, TPD

OAM

AIS, RDI, CC

Signalling

PNNI

1AA 00014 0004 (9007) A4 – ALICE 04.10

Table 62. ATM8X8 board: configurable TPs type and max, number Board acronym

max. TPs number

VC4–4C

VC4

VC3

VC12

E1

E3

T3

E1 IMA

ATM8X8

32

Yes

Yes

Yes

Yes

Yes

Yes

No

No

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1AA 00014 0004 (9007) A4 – ALICE 04.10

Throughput

1000 Mb/s (with 4xFE i/f) 1800 Mb/s (with 1xGbE i/f)

PDH containers (not operative)

E1, E3

Ethernet frames

MAC 802.3, optionally “tagged” with 802.1p/q fields (user priority and VLAN identifier) Martini Encapsulation: optional

SDH containers

VC–12, VC–3, SDH/HDLC/PPP)

Local Ethernet ports

4 x 10/100Base–T 1 x1000Base–LX , 1 x 1000Base–SX, 1 x 1000Base–ZX

Remote Ethernet ports

unstruct. VC–4, un–concatenated ethernet frames over SDH (SDH/GFP framing)

Logical Ports number

63 (any combination)

Managed protocols

SNMP,TMN messaging inside DCN

Congestion management

W–RED (Weighed–Random Early Discard) Cut–off on low priority traffic only

Quality of Service (QoS)

Best Effort bandwidth (BE–BW) Min–BW with regulated bursts Guaranted constant BW

Police mechanism

Dual–Rate Leaky–Bucket, based on PIR and CIR values of the traffic contract

Scheduling

HOL and WC–WFQ methods

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VC–4

(POS

framing,

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5.4 PR_EA characteristics and MPLS data traffic management (PREA4ETH, PREA1GBE)

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

5.5 PR characteristics 5.5.1 ISA–PR port card interface characteristics Type of interface

Plug–in SFP Optical module at 622.080 Mbps (STM–4/OC–12), for up to 40 Km; see Table 64. on page 593 for the optical characteristics

STM–4 / OC–12 ports

4 : 2 east + 2 west

Throughput towards backpanel

6.5 Gbps

Ethernet frames

MAC 802.3, optionally “tagged” with 802.1p/q fields (Ethernet frame priority and VLAN identifier). Martini Encapsulation

SDH containers

SDH VC–4 Virtual Concatenation (VC–4–nv): VC–4–4v, VC–4–6v, VC4–8v, VC–4–4c

Managed Ethernet ports (located on access cards) 32 x 10/100Base–T 4 x1000Base–LX/SX/ZX 2 x1000Base–LX/SX/ZX and 16 x 10/100Base–T Managed protocols

SNMP V2c, NMS messaging in Band

Quality of Service (QoS) SLAs

Best Effort bandwidth Regulated bandwidth Guaranted bandwidth

Cabling

Optical fiber

Connector

LC/PC on SFP (Small Formfactor Pluggable) module

1AA 00014 0004 (9007) A4 – ALICE 04.10

5.5.2 16FEA–PR access card interface characteristics Type of interface

Electrical, compliant to IEEE–802.3 standard, 10/100 Base–Tx

Transmit operations

Auto–negotiation options: 10Mbps, 100Mbps, full–duplex, flow control

Bit rate

Autosensing: 10 Mb/s and 100 Mb/s

Provisioning Granularity

100 Kbit/s

Signal amplitude, coding, attenuation, pulse shape, return loss

According to IEEE–802.3 standard, 10Base–T and 100Base–T

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16 per access card used in conjunction with PR port card

Cabling

Twisted–pair, as per IEEE–802.3 rec.

Connector

RJ45

1AA 00014 0004 (9007) A4 – ALICE 04.10

5.5.3 2GBA–PR access card interface characteristics Type of interface

Plug–in Optical module 1000Base–LX, 1000Base–SX, 1000Base–ZX,

Transmit operations

Full–duplex, FlowControl

Bit rate

1000 Mb/s

Provisioning Granularity

100 Kbit/s

Tx and Rx Optical characteristics

According to IEEE–802.3 standard, 1000Base–LX 1000Base–SX and 1000Base–ZX

Port number

2 per access card used in conjunction with PR port card

Cabling

Optical fiber

Connector

SFP (Small Formfactor Pluggable)

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Port number

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

5.6 ETHERNET characteristics 5.6.1 Ethernet 10/100Base–T interface characteristics (ETH–MB + ETH–ATX) Type of interface

Electrical, full compliant to IEEE–802.3 standard, 10Base–T and 100Base–T

Transmit operations

Auto–negotiation options: 10Mbps, 100Mbps, full–duplex

Bit rate

Autosensing: 10 Mb/s and 100 Mb/s

Signal amplitude, coding, attenuation, pulse shape, return loss

According to IEEE–802.3 standard, 10Base–T and 100Base–T

Throughput towards backpanel (ports card)

622 Mbit/s

SDH containers

VC–12, VC–3, VC–4

Port number

11 on the ports card 14 on the access card

Cabling

Twisted–pair, as per IEEE–802.3 rec.

Connector

RJ45

1AA 00014 0004 (9007) A4 – ALICE 04.10

5.6.2 Ethernet switch port card characteristics (ES1–8FE) Type of interface

10 / 100 Base T

Local Ethernet ports number

8 per each ports card

Ethernet over SDH ports number

8

VC termination max.

VC–12 = 63 VC–3 = 3

Number of VCGs ETH over SDH

VC–12 = 8 VC – 3 = 3

VCs per VCG max.

VC–12 = 21 VC –3 = 3

VC comp. delay

48 ms

Mapping to SDH

GFP–F LAPS

Class forwarding criteria per port

according to 802.1 Q (outer VLAN) according to 802.1 p according to 802.3 MAC DA

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VLAN–ids = 1 K MAC addresses = 8K

Multicast

Ethernet

VLAN capabilities

cVLAN (802.1 D) pVLAN (SVLAN)

CoS

Guaranteed Best Effort

Policer

Metering –> token–bucket Marking –> 3 colors Dropping –> out of profile

Scheduler

Head of line –> 4 piorities Deficit Round Robin

Spanning tree

802.1d 802.1 w 802.1s

Performance ethernet counter

yes

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Look up tables number

1AA 00014 0004 (9007) A4 – ALICE 04.10

5.6.3 Ethernet switch port card characteristics (ES1–8FX) Type of interface

100 Base FX

Local Ethernet ports number

8 per each ports card

Ethernet over SDH ports number

8

VC termination max.

VC–12 = 63 VC–3 = 3

Number of VCGs ETH over SDH

VC–12 = 8 VC – 3 = 3 VC – 4 = 1

VCs per VCG max.

VC–12 = 21 VC –3 = 3 VC –4 = 1

VC comp. delay

48 ms

Mapping to SDH

GFP–F LAPS

Class forwarding criteria per port

according to 802.1 Q (outer VLAN) according to 802.1 p according to 802.3 MAC DA

Look up tables number

VLAN–ids = 1 K MAC addresses = 8K

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Multicast

Ethernet

VLAN capabilities

VLAN (802.1 Q) pVLAN (802.1ad)

CoS

Guaranteed Best Effort

Policer

Metering –> single rate token–bucket Dropping –> tail drop

Scheduler

Queues/port = 3 Queuing = Strict Priority

Spanning tree

802.1d 802.1 w 802.1s

Performance ethernet counter

yes

1AA 00014 0004 (9007) A4 – ALICE 04.10

5.6.4 Ethernet switch port card characteristics (ES4–8FE) Type of interface

10 / 100 Base T 1000 Base SX/LX/ZX SFP

Local Ethernet ports number

eight 10 / 100 Base T and one1000 Base SX/LX/ ZX SFP per each port card.

Ethernet over SDH ports number

16 (SMII mode), 2 (GMII mode)

VC termination max.

VC–12 = 252 VC–3 = 12 VC–4 = 4

Number of VCGs ETH over SDH

VC–12 = 16 (SMII), 2 (GMII) VC – 3 = 12 (SMII), 2 (GMII) VC – 4 = 4 (SMII), 2 GMII)

VCs per VCG max.

VC–12 = 50 (SMII), 63 (GMII) VC –3 = 2 (SMII), 12 (GMII) VC –4 = 1 (SMII), 4 (GMII)

VC comp. delay

48 ms

Mapping to SDH

GFP–F LAPS

Class forwarding criteria per port

according to 802.1 Q (outer VLAN) according to 802.1 p according to 802.3 MAC DA

Look up tables number

VLAN–ids = 1 K MAC addresses = 8K

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Ethernet

VLAN capabilities

cVLAN (802.1 D) pVLAN (SVLAN)

CoS

Guaranteed Best Effort

Policer

Metering –> token–bucket Marking –> 3 colors Dropping –> out of profile

Scheduler

Head of line –> 4 piorities Deficit Round Robin

Spanning tree

802.1d 802.1 w 802.1s

Performance ethernet counter

yes

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Multicast

1AA 00014 0004 (9007) A4 – ALICE 04.10

5.6.5 Ethernet switch port card characteristics (ISA ES–16) Local Ethernet ports

none

Ethernet over SDH ports number

64

VC termination max.

VC–12 = 252 VC–3 = 12 VC–4 = 16

Number of VCGs ETH over SDH

VC–12 = 64 VC – 3 = 12 VC–4 = 16

VCs per VCG max.

VC–12 = 21 VC –3 = 3 VC – 4 = 8

VC comp. delay

64 ms

Mapping to SDH

GFP–F HDLC/PPP LAPS

Class forwarding criteria per port

according to 802.1 Q (outer VLAN) according to 802.1 p according to 802.3 MAC DA MPLS + exp. bits

Look up tables number

VLAN–ids = up to 64 K MAC addresses = up to 64K MPLS labels = up to 64K

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Multicast

Ethernet MPLS

MPLS capability

Martini enc. MPLS

VLAN capabilities

cVLAN (802.1 D) pVLAN (SVLAN) (push, pop, swap)

CoS

Guaranteed Regulated Best Effort

Policer

Metering –> token–bucket dual rate Marking –> 3 colors Dropping –> out of profile

Scheduler

Head of line –> 8 piorities Deficit Round Robin

Congestion Avoidance

RED per queue

Spanning tree

802.1d 802.1 w 802.1s

Performance ethernet counter

yes

MPLS counter

yes

1AA 00014 0004 (9007) A4 – ALICE 04.10

5.6.6 Access Card Gigabit Ethernet interfaces characteristics (GETH–AG) Type of interface

Plug–in Optical module 1000Base–LX or 1000Base–SX or 1000 Base–ZX

Transmit operations

Full–duplex, Flow Control

Bit rate

1.25 Gb/s

Tx and Rx Optical characteristics

According to IEEE–802.3 standard, 1000Base–LX, 1000Base–SX and 1000Base– ZX (refer to Table 68. on page 598 and Table 69. on page 599 for details )

SDH containers

VC–4xV

Ports number

2 on the access card if used in conjunction with ETH–MB

Cabling

Optical fibre

Connector

LC–Duplex SFP (Small Formfactor Pluggable)

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1AA 00014 0004 (9007) A4 – ALICE 04.10

Type of interface

Plug–in Optical module 1000Base–LX or 1000Base–SX or 1000 Base ZX

Transmit operations

Full–duplex, Flow Control

Bit rate

1.25 Gb/s

Throughput towards backpanel (ports card)

2 x 622 Mbit/s

Tx and Rx Optical characteristics

According to IEEE–802.3 standard, 1000Base–LX, 1000Base–SX and 1000 Base ZX (refer to Table 68. on page 598 and Table 69. on page 599 for details )

SDH containers

VC–4xV

Local Gigabit Ethernet ports number

8 per each ports card

Cabling

Optical fibre

Connector

LC–Duplex SFP (Small Formfactor Pluggable)

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5.6.7 Gigabit Ethernet ports card interfaces (GETH–MB)

5.7 4 x ANY clients characteristics

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

The interface characteristics are related to client type according to the following paragraphs 5.7.1 Gigabit Ethernet LX The interface is according to IEEE g.802.3 1000Base–LX (clause 38.4) INPUT SIDE · · · · · · · · · · · · · ·

Bit Rate Bit Rate Tolerance Optical Connector Receive Sensitivity Stressed Receive Sensitivity Max Receive Optical Power Opt. Operating Wavelength Opt. Return Loss of Receiver Opt. Modulation Amplitude Signal detect – Asserted Signal detect – Clearing Hysteresis Signal detect Assert Time Signal detect Clearing Time

1250 Mb/s ±100 ppm LC – 20 dBm max. –14.4 dBm –3 dBm max. 1270 nm min., 1355 nm max 12 dB min. 15 µW min., 1000 µW max. –20 dBm max. , –30 dBm +Hyst. min. –30 dBm min (avg.) 0.5 dB min. < 100 µs (excepted SPI access time) < 100 µs (excepted SPI access time)

N.B.: GE flow control is not implemented.

1AA 00014 0004 (9007) A4 – ALICE 04.10

OUTPUT SIDE · · · · ·

Bit Rate Bit Rate Accuracy Optical Connector Laser Type Launched Optical Power

· ·

Opt. Center Wavelength Operating Range

· · · · · ·

Opt. Spectral Width (∆λRMS) Opt. Extinction ratio Opt. Modulation Amplitude Opt. Rise/Fall time (tr/tf) Relative Intensity Noise Deterministic Jitter

ED

1250 Mb/s ±100 ppm LC Class 1 laser safety –11.0 dBm min., –3 dBm max (avg.) 10 µm SMF –11.5 dBm min., –3 dBm max (avg.) 50 µm MMF –11.5 dBm min., –3 dBm max (avg.) 62.5 µm MMF 1270 nm min., 1355 nm max 2 m B 550 m (MMF 62.5 µm) 2 m B 550 m (MMF 50 µm) 2 m B 5000 m (SMF 9 µm) 4 nm max. 9 dB min 189 µW min. 260 ps max (20% B 80%) –116 dB/Hz max. 0.200 UI max.

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5.7.2 Gigabit Ethernet SX

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The interface is according to IEEE g.802.3 1000Base–SX INPUT SIDE · · · · · · · · · · · · ·

Bit Rate Bit Rate Tolerance Optical Connector Receive Sensitivity Max Receive Optical Power Opt. Operating Wavelength Opt. Return Loss of Receiver Opt. Modulation Amplitude Signal detect – Asserted Signal detect – Clearing Hysteresis Signal detect Assert Time Signal detect Clearing Time

1250 Mb/s ± 100 ppm LC – 17 dBm max. – 0 dBm max. 770 nm min., 860 nm max 12 dB min. 15 µW min., 1000 µW max. –17 dBm max. , –30 dBm +Hyst. min. –30 dBm min (avg.) 1.5 dB min. < 100 µs (excepted SPI access time) < 350µs (excepted SPI access time)

N.B.: GE flow control is not implemented.

1AA 00014 0004 (9007) A4 – ALICE 04.10

OUTPUT SIDE · · · · ·

Bit Rate Bit Rate Accuracy Optical Connector Laser Type Launched Optical Power

· · · · · ·

Opt. Center Wavelength Opt. Extinction ratio Opt. Modulation Amplitude Opt. Rise/Fall time (tr/tf) Relative Intensity Noise Deterministic Jitter

ED

1250 Mb/s ±100 ppm LC Class 1 laser safety –9.5 dBm min., –1.5 dBm max (avg.) 50 µm MMF –9.5 dBm min., –1.5 dBm max (avg.) 62.5 µm MMF 830 nm min., 860 nm max 9 dB min 189 µW min. 260 ps max (20% B 80%) –116 dB/Hz max. 0.200 UI max.

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5.7.3 Fiber Channel 100–SM–LL–I

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The FC I/F is compliant to Ansi x3.230 standard (100–SM–LL–I). INPUT SIDE · · · · · · · · · · · · · ·

Bit Rate Bit Rate Tolerance Optical Connector Receive Sensitivity Stressed Receive Sensitivity Max Receive Optical Power Opt. Operating Wavelength Opt. Return Loss of Receiver Opt. Modulation Amplitude Signal detect – Asserted Signal detect – Clearing Hysteresis Signal detect Assert Time Signal detect Clearing Time

1062.5 Mb/s ±100 ppm LC –20 dBm max. –14.4 dBm –3 dBm max. 1270 nm min., 1355 nm max 12 dB min. 15 µW min., 1000 µW max. –20 dBm max. , –30 dBm +Hyst. min. –30 dBm min (avg.) 0.5 dB min. < 100 µs (excepted SPI access time) < 100 µs (excepted SPI access time)

OUTPUT SIDE

1AA 00014 0004 (9007) A4 – ALICE 04.10

· · · · · · · · · · · · · ·

ED

Bit Rate Bit Rate Accuracy Optical Connector Laser Type Launched Optical Power Operating Range Fiber Core Diameter Opt. Center Wavelength Opt. Spectral Width (∆λRMS) Opt. Extinction ratio Opt. Modulation Amplitude Opt. Rise/Fall time (tr/tf) Relative Intensity Noise Deterministic Jitter

1062.5 Mb/s ±100 ppm LC Class 1 laser safety –12.0 dBm min., –3 dBm max (avg.) 9 µm SMF 2 m B2 Km 9 µm 1270 nm min., 1355 nm max 4 nm max. 9 dB min 189 µW min. 260 ps max (20%B80%) –116 dB/Hz max. 0.200 UI max.

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5.7.4 Fiber Channel 100–M5–SL–I

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The FC I/F is compliant to Ansi x3.230 standard (100–M5–SL–I) except where specified. INPUT SIDE · · · · · · · · · · · · ·

Bit Rate Bit Rate Tolerance Optical Connector Receive Sensitivity Max Received Optical Power Opt. Operating Wavelength Opt. Return Loss of Receiver Opt. Modulation Amplitude Signal detect – Asserted Signal detect – Clearing Hysteresis Signal detect Assert Time Signal detect Clearing Time

1062.5 Mb/s ±100 ppm LC –13 dBm max. –1.5 dBm max. 770 nm min., 860 nm max 12 dB min. 15 µW min., 1000 µW max. –17 dBm max. , –30 dBm +Hyst. min. –30 dBm min (avg.) 1.5 dB min. < 100 µs (excepted SPI access time) < 350 µs (excepted SPI access time)

1AA 00014 0004 (9007) A4 – ALICE 04.10

OUTPUT SIDE · · · · ·

Bit Rate Bit Rate Accuracy Optical Connector Laser Type Launched Optical Power

· · · · · · ·

Opt. Center Wavelength RMS spectral width (max) Opt. Extinction ratio Opt. Modulation Amplitude Opt. Rise/Fall time (tr/tf) Relative Intensity Noise Deterministic Jitter

ED

1062.5 Mb/s ±100 ppm LC Class 1 laser safety –9.5 dBm min., –1.5 dBm max (avg.) 50 µm MMF –9.5 dBm min., –1.5 dBm max (avg.) 62.5 µm MMF 830 nm min., 860 nm max 4 nm max. 9 dB min 189 µW min. 260 ps max (20% " 80%) –116 dB/Hz max. 0.200 UI max.

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5.7.5 Fast Ethernet (100BASE FX)/FDDI

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FDDI and Fast Ethernet I/F is compliant to ANSI x3.184–1993 and IEEE 802.3 except where specified. INPUT SIDE · · · · · · · · · · · ·

Bit Rate Bit Rate Tolerance Optical Connector Receive Sensitivity Max. Receive Optical Power Opt. Operating Wavelength Opt. Return Loss of Receiver Signal detect – Asserted Signal detect – Clearing Hysteresis Signal detect Assert Time Signal detect Clearing Time

125 Mb/s ±100 ppm LC – 28 dBm max. –8 dBm min. (avg.) 1270 nm min., 1360 nm max 12.5 dB min. –31 dBm max., –42 dBm + Hyst. min. ; –42 dBm min (avg.) 1 dB min. B 3 dB max. < 100 µs (excepted SPI access time) < 350 µs (excepted SPI access time)

OUTPUT SIDE · · · · · · · · · ·

Bit Rate Bit Rate Accuracy Optical Connector Laser Type Launched Optical Power Opt. Center Wavelength Opt. Spectral Width (∆λRMS) Opt. Extinction ratio Optical Rise/Fall Time (tr/tf) Relative Intensity Noise (RIN)

125 Mb/s ±100 ppm LC Class 1 laser safety –15 dBm min., –8 dBm max (avg.) 1274 nm min., 1356 nm max 2.5 nm max. 8.2 dB min 1.5 ns max. (20% B 80%) 125 dB/Hz nom., –112 dB/Hz max.

1AA 00014 0004 (9007) A4 – ALICE 04.10

N.B. :The Client Transmit Port provides a different ”Launched Optical Power” level than what required by the FDDI & FE standards: – MMF : –20 dBm B –14 dBm – SMF Cat I : –20 dBm B –14 dBm – SMF Cat II : 4 dBm B 0 dBm

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5.7.6 ESCON

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ESCON I/F is compliant to IBM SA–0394–03 INPUT SIDE · · · · · · · · · · · ·

Bit Rate Bit Rate Tolerance Optical Connector Receive Sensitivity Max. Receive Optical Power Opt. Operating Wavelength Opt. Return Loss of Receiver Signal detect – Asserted Signal detect – Clearing Hysteresis Signal detect Assert Time Signal detect Clearing Time

200 Mb/s ±100 ppm LC – 28 dBm max. –8 dBm min. (avg.) 1270 nm min., 1360 nm max 12.5 dB min. –31 dBm max., –42 dBm + Hyst. min. –42 dBm min (avg.) 1 dB min. B 3 dB max. < 100 µs (excepted SPI access time) < 350 µs (excepted SPI access time)

OUTPUT SIDE · · · · · · · · · ·

Bit Rate Bit Rate Accuracy Optical Connector Laser Type Launched Optical Power Opt. Center Wavelength Opt. Spectral Width (∆λRMS) Opt. Extinction ratio Optical Rise/Fall Time (tr/tf) Relative Intensity Noise (RIN)

200 Mb/s ±100 ppm LC Class 1 laser safety –15 dBm min., –8 dBm max (avg.) 1274 nm min., 1356 nm max 2.5 nm max. 8.2 dB min 1.5 ns max. (20% B 80%) 125 dB/Hz nom., –112 dB/Hz max.

N.B. The Client Transmit Port provides a different ”Launched Optical Power” level than what required by the ESCON standard: –MMPL : –20 dBm B –15 dBm –SMPL : –4 dBm B –0 dBm

1AA 00014 0004 (9007) A4 – ALICE 04.10

The bit rate accuracy required by ESCON standard is ±200 ppm

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5.7.7 Digital Video

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Digital Video I/F is compliant to ITU–R Rec. BT.656–4, BT1363–1 and BT1367. INPUT SIDE · · · · · · · · · · · ·

Bit Rate Bit Rate Tolerance Optical Connector Receive Sensitivity Max. Receive Optical Power Opt. Operating Wavelength Signal detect – Asserted Opt. Return Loss of Receiver Signal detect – Clearing Hysteresis Signal detect Assert Time Signal detect Clearing Time

270 Mb/s "100 ppm LC – 28 dBm max. –8 dBm min. (avg.) 1270 nm min., 1360 nm max –31 dBm max., –42 dBm + Hyst. min. 12.5 dB min. –42 dBm min (avg.) 1 dB min. B 3 dB max. < 100 µs (excepted SPI access time) < 350 µs (excepted SPI access time)

OUTPUT SIDE · · · · · · · · · · ·

Bit Rate Bit Rate Accuracy Optical Connector Laser Type Launched Optical Power Opt. Center Wavelength Opt. Spectral Width (∆λRMS) Opt. Extinction ratio Optical Rise/Fall Time (tr/tf) Relative Intensity Noise (RIN) Output jitter

270 Mb/s " 100 ppm LC Class 1 laser safety –15 dBm min., –8 dBm max (avg.) 1274 nm min., 1356 nm max 2.5 nm max. 8.2 dB min 1.5 ns max. (20% B 80%) 125 dB/Hz nom., –112 dB/Hz max. 0.2 UIpp (10 Hz– 27 MHz)

1AA 00014 0004 (9007) A4 – ALICE 04.10

N.B: The Client Transmit Port provides a different ”Launched Optical Power” level than what required by the DV standards: –MM: –12 dBm B –7.5 dBm –SM: –12 dBm B –7.5 dBm

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5.8 Optical interface characteristics

Types of optical interfaces

S–1.1, L–1.1, L–1.2 or L–1.2JE, MM1 Characteristics are given in Table 63. on page 591.

Optical connectors

SC/PC or FC/PC (alternative units)

Pulse shape

See ITU–T G.957

STM–4 optical characteristics: Types of optical interfaces

S–4.1, L–4.1 , L–4.2 Characteristics are given in Table 64. on page 593

Optical connectors

SC/PC, FC/PC (alternative units) or LC/PC on SFP (Small Formfactor Pluggable) module

Pulse shape

See ITU–T G.957

STM–16 optical characteristics: Types of optical interfaces

I–16.1, S–16.1, L.16–1, L.16–2 , L.16–2 JE2, L.16–2JE3, Characteristics are given in Table 66. at page 595. The ”second generation” optical interface characteristics are given in Table 16 which applies for HM1 Optical Units.

Optical connectors

SC/PC, FC/PC, SFF (alternative units)

Pulse shape

See ITU–T G.957

Booster (Optical Fiber Amplifier) characteristics: Types of Booster

BST10 (+10 dBm), BST15 (+15 dBm) and BST17 (+17 dBm). Characteristics are given in Table 71. on page 601

Optical connectors

SC/PC or FC/PC (alternative units)

1AA 00014 0004 (9007) A4 – ALICE 04.10

Optical Preamplifier (PR16) characteristics: Optical connectors

SC/PC or FC/PC (alternative units)

Wavelength bandwidth (main signal):

1530 to 1565 nm

Input power:

–37 dBm to –18 dBm

Output power:

–15 dBm

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STM–1 optical characteristics:

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Table 63. Parameters specified for STM–1 Optical Interface CHARACTERISTICS

UNIT

VALUES

DIGITAL SIGNAL Nominal bit rate

Kbit/s

STM–1 according to G.707 and G.958 155520 S–1.1

Application code (Table 1/G.957) Operating wavelength range

nm

L–1.1

L–1.2

L–1.2 JE1 nb1

1261–1360 1280–1335 1480–1580 1530–1560

TRANSMITTER AT REFERENCE POINT S Source type

SLM/MLM

SLM/MLM

SLM

SLM

Spectral characteristics 

maximum RMS width

nm

7.7

4

–

–



maximum –20 dB width

nm

–

–

1

1



minimum side mode suppression ratio

dB

–

–

30

30

Mean launched power 

maximum

dBm

–8

0

0

0



minimum

dBm

–15

–5

–5

–4

Minimum extinction ratio

dB

8.2

10

10

10

dB

0–12

10–28

10–28

10–29

ps/nm

100

250

1900

3200

Minimum optical return loss of cable plant at S, including any connectors

dB

NA

NA

20

20

Maximum discrete reflectance between S and R

dB

NA

NA

–25

–25

In Ga As PIN

In Ga As PIN

In Ga As PIN

In Ga As PIN

OPTICAL PATH BETWEEN S AND R Attenuation range Maximum dispersion

RECEIVER AT REFERENCE POINT R Type of detector

1AA 00014 0004 (9007) A4 – ALICE 04.10

Mean received power at BER= 1E–10 •

Minimum (sensitivity)

dBm

–28

–34

–34

–34

•

Maximum (overload)

dBm

–8

–10

–10

–10

Maximum optical path penalty

dB

1

1

1

1

Maximum reflectance of receiver measured at R

dB

–14

–14

–25

–25

nb1: To be used with Optical Boosters up to +15 dBm on G652 and G653 fibre N.A = not applicable table continue

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DIGITAL SIGNAL Nominal bit rate

UNIT

VALUES

Kbit/s

STM–1 according to G.707 and G.958 155520

Application (ALCATEL code) Operating wavelength range

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CHARACTERISTICS

MM–1 nm

TRANSMITTER AT REFERENCE POINT S Source type

1270–1360

SLM

Spectral characteristics 

maximum RMS width

nm

–



maximum –20 dB width

nm

1



minimum side mode suppression ratio

dB

30

Mean launched power 

maximum

dBm

–14



minimum

dBm

–19

Minimum extinction ratio

dB

10

dB

0–10

ps/nm

NA

Minimum optical return loss of cable plant at S, including any connectors

dB

NA

Maximum discrete reflectance between S and R

dB

NA

OPTICAL PATH BETWEEN S AND R Attenuation range Maximum dispersion

RECEIVER AT REFERENCE POINT R Type of detector

In Ga As PIN

Minimum sensitivity (BER 10–10)

dBm

–30

Minimum overload

dBm

–14

Maximum optical path penalty

dB

1 (a)

Maximum reflectance of receiver measured at R

dB

–14

NOTES: a= with max 3 Km of multimode fibre 50/125 um G.651 NA= not applicable

1AA 00014 0004 (9007) A4 – ALICE 04.10

end of table.

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Table 64. Parameters specified for STM–4 Optical Interface CHARACTERISTICS

UNIT

VALUES

DIGITAL SIGNAL Nominal bit rate

Kbit/s

STM–4 according to G.707 and G.958 622.080 S–4.1

Application code (Table 1/G.957) Operating wavelength range

nm

L–4.1 nb3

L–4.2

L–4.2 JE nb1, nb2

1274–1356 1280–1335 1480–1580 1530–1560

TRANSMITTER AT REFERENCE POINT S Source type

MLM

SLM

SLM

SLM

Spectral characteristics 

maximum RMS width

nm

2.5

–

–

–



maximum –20 dB width

nm

–

1

1

0.6



minimum side mode suppression ratio

dB

–

30

30

30

Mean launched power 

maximum

dBm

–8

+2

+2

+2



minimum

dBm

–15

–3

–3

–3

Minimum extinction ratio

dB

8.2

10

10

10

dB

0–12

10–24

10–24

10–27

ps/nm

84

250

1900

3200

Minimum optical return loss of cable plant at S, including any connectors

dB

14

20

24

24

Maximum discrete reflectance between S and R

dB

–20

–25

–27

–27

In Ga As PIN

In Ga As PIN

In Ga As PIN

In Ga As PIN

OPTICAL PATH BETWEEN S AND R Attenuation range Maximum dispersion

RECEIVER AT REFERENCE POINT R Type of detector

1AA 00014 0004 (9007) A4 – ALICE 04.10

Mean received power at BER= 1E–10 •

Minimum (sensitivity)

dBm

–28

–28

–28

–32

•

Maximum (overload)

dBm

–8

–8

–8

–8

Maximum optical path penalty

dB

1

1

1

2

Maximum reflectance of receiver measured at R

dB

–20

–20

–27

–27

nb1: Suitable for interworking with the L–4.2JE of the ADM product family with max dispersion 2400 ps/nm; on this application the attenuation range is 10–28 dB. nb2: For long distance applications and additionally suitable to be used with Optical Boosters up to +15 dBm on G652 and G653 fibre. nb3: Suitable for interworking with L–4.1 of ADM product family. In this application the power budget is 10–24 dBm, 250 ps/nm dispersion.

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CHARACTERISTICS

UNIT

VALUES

DIGITAL SIGNAL Nominal bit rate

Mbps

STM–4 according to G.707 and G.958 622.080

Application code (Table 1/G.957) Operating wavelength range

S–4.1 nm

1274–1356

TRANSMITTER AT REFERENCE POINT S Source type

SLM

Mean launched power 

maximum

dBm

–8



minimum

dBm

–15

Spectral characteristics 

maximum RMS width

nm

2.5



minimum side mode suppression ratio

dB

not applicable

dB

8.2

dBm

50

Maximum chromatic dispersion

ps/nm

+ 100

Minimum chromatic dispersion

ps/nm

– 100

Minimum optical return loss of cable plant at S

dB

14

Maximum discrete reflectance between S and R

dB

–20

Minimum extinction ratio Maximum shutdown optical output power OPTICAL PATH BETWEEN S AND R

RECEIVER AT REFERENCE POINT R Type of detector

In Ga As PIN

Mean received power at BER= 1E–10 •

Minimum (sensitivity)

dBm

–29

•

Maximum (overload)

dBm

–8

dB

–14

1AA 00014 0004 (9007) A4 – ALICE 04.10

Max. optical reflectance of receiver measured at R

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Table 65. Parameters specified for SFP STM–4 Optical Interface

Table 66. STM–16 Optical interfaces (Single Channel)

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CHARACTERISTICS DIGITAL SIGNAL Nominal bit rate

UNIT

VALUES

Kb/s

STM–16 according to G.707 and G.958 2488320 S–16.1

L–16.1

L–16.2

1270–1360

1280–1335

1500–1580

SLM

SLM

SLM

nm nm dB

– 1 30

– 1 30

– 1 30

dBm dBm

0 –5

+2 –2

+2 –2

dB

8.2

8.2

8.2

dB ps/nm

0–12 100

10–24 250

10–24 1600

Minimum optical return loss of cable plant at S, including any connectors

dB

24

24

24

Maximum discrete reflectance between S and R

dB

–27

–27

–27

InGaAs PIN

InGaAs APD

InGaAs APD

–18 0

–27 –8

–28 –8

Application code Operating wavelength range TRANSMITTER AT REFERENCE POINT S Source type Spectral characteristics – maximum RMS width – maximum –20 dB width – minimum side mode suppression ratio Mean launched power – maximum – minimum Minimum extinction ratio OPTICAL PATH BETWEEN S AND R Attenuation range Maximum dispersion

RECEIVER AT REF. R Type of detector Mean received power at BER= 1E10–10 • •

Minimum (sensitivity) Maximum (overload)

dBm dBm

Maximum optical path penalty

dB

1

1

2

Maximum reflectance of receiver measured at R

dB

–27

–27

–27

1AA 00014 0004 (9007) A4 – ALICE 04.10

Table Continue

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DIGITAL SIGNAL Nominal bit rate

UNIT

VALUES

Kb/s

STM–16 according to G.707 and G.958 2488320

Application code Operating wavelength range

L–16.2JE1

L–16.2 JE2

L–16.2 JE3

nb2

nb1

nb3

1530–1560

1550–1560

1550–1560

I–16.1

1266–1360

TRANSMITTER AT REFERENCE POINT S Source type

SLM

SLM–ILM SLM–ILM

MLM

Spectral characteristics nm nm dB

– 0.5 30

– 0.2 30

– 0.2 30

4 – –

dBm dBm

+4 +1

+2 –3

+2 –3

–3 –10

dB

8.2

8.2

8.2

8.2

dB ps/nm

13–28 1900

nb1 3200

nb3 4000

0–7 12

Minimum optical return loss of cable plant at S, including any connectors

dB

24

24

24

27

Maximum discrete reflectance between S and R

dB

–27

–27

–27

–27

InGaAs APD

InGaAs APD

InGaAs APD

InGaAs APD

dBm dBm

–29 –9

–29 –9

nb3 –9

–18 –3

Maximum optical path penalty

dB

2

1

1

1

Maximum reflectance of receiver measured at R

dB

–27

–27

–27

–27

– maximum RMS width – maximum –20 dB width – minimum side mode suppression ratio Mean launched power – maximum – minimum Minimum extinction ratio OPTICAL PATH BETWEEN S AND R Attenuation range Maximum dispersion

RECEIVER AT REF. R Type of detector Mean received power at BER= 1E10–10 • •

Minimum (sensitivity) Maximum (overload)

1AA 00014 0004 (9007) A4 – ALICE 04.10

nb1: to be used with booster amplifier on G.652 fiber; attenuation range according to the specific 1664OA power budget nb2: To be used with booster amplifier up to + 15dBm on G653 fiber; or in stand alone configuration nb3: To be used with booster in conjunction with the 1664OA preamplifier on G.652 and G.653 fiber; attenuation range according to the 1664OA characteristics. Suitable for submarine application too, in conjunction with Alcatel booster/preamplifier: specific reference value of max dispersion at 5400 ps/nm with optical path penalty 27

Power Wavelength Bandwidth

nm

1530÷1565

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ÏÏÏÏÏÏ ÏÏ ÏÏÏÏÏÏ ÏÏ ÏÏÏÏÏÏ ÏÏ

ÏÏÏÏÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏÏ

Booster

STM16 Port

STM16 Port

min –6dBm max 4dBm

R

S

Booster Input

15dBm 17dBm

–29dBm –9dBm

SPECIFICATIONS Maximum chromatic dispersion

3200 (ps/nm)

Optical fiber used

G.652

– fiber attenuation

0.25 dB/km

– chromatic dispersion of the fiber

18 ps/nm/km

– penalty

1 dB

Attenuation range min = +17–(–9) max = +15 –(–29)–1

26 dB 43 dB

Minimum span length (26dB/0.25)

104 Km

Maximum span length (due to the attenuation (sensitivity: 43/0.25

172 Km

Following there are the formulas to calculate the minimum and maximum span length. The maximum length can be limited by the receiver sensitivity or by the maximum chromatic dispersion, whichever is most restrictive; the minimum length is limited by the receiver overload. The optical interface characteristics are deduced from Table 66. on page 595 depending on the type of interface. The optical fiber characteristics are reported in rec. ITU–T G.957. Span attenuation range: Min Atten.= (max Tx Power)–(min. Rx Overload)=+17–(–9)=26dB Max Atten.= (minTx Power)–(min. Rx Sensitivity)–(penalty)=+15–(–29)–21=43 dB

1AA 00014 0004 (9007) A4 – ALICE 04.10

Minimum span length (for overload) = (Min Att.)/(fiber att.)=26/0.25=104 Km Maximum span length (for sensitivity) = (Max Att.)/(fiber att.)=43/0.25=172 Km Maximum span length (for dispersion) = (Max dispers.)/(fiber disp.)=3200/18=177.7 Km Thus the maximum fiber span length is limited for attenuation (sensitivity): 172 Km, while the minimum span to avoid overload problems should be 104 Km.

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5.8.1 Example of a link using 1660SM with L–16.2 JE2 Port and 15 dBm Booster

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

5.9 Coarse WDM subsystem units characteristics 5.9.1 COADM–1 Channel General Characteristics Number of channels that can be add/drop per unit:

One channel among the following λ: 1470 nm, 1490 nm, 1510 nm, 1530 nm, 1550 nm, 1570 nm, 1590 nm, 1610 nm

Connector type

MU horizontal

Pass–through Insertion Loss (dB)

ÂÂ ÂÂ ÂÂ ÂÂ Â ÂÂ

2.1

ÂÂÂ ÂÂÂ ÂÂÂ ÂÂÂ ÂÂ ÂÂÂ

Pass–through

Demux side specification In – Drop Ch.

CWDM line In

ÂÂÂ ÂÂ ÂÂÂ ÂÂ ÂÂÂ ÂÂÂ ÂÂÂ ÂÂ ÂÂÂ

DROP Ch.

In–Drop Ch. Insertion Loss (dB)

Channels (nm)

1.25

1470 nm

1.25

1490 nm

1.25

1510 nm

1.25

1530 nm

1.25

1550 nm

1.25

1570 nm

1.25

1590 nm

1.25

1610 nm

Add Ch.– Out Insertion Loss (dB)

Channels (nm)

1.25

1470 nm

1.25

1490 nm

1.25

1510 nm

1.25

1530 nm

1.25

1550 nm

1.25

1570 nm

1.25

1590 nm

1.25

1610 nm

Mux side specificaton ADD Ch. –Out

1AA 00014 0004 (9007) A4 – ALICE 04.10

ÂÂ Â ÂÂ ÂÂ ÂÂ ÂÂ Â ÂÂ ADD Ch.

ED

CWDM Line OUT

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5.9.2 COADM–2 Channels

Number of channels that can be add/drop per unit:

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

General Characteristics Two channels among the following λ: 1470 – 1490 nm 1510 – 1530 nm 1550 – 1570 nm 1590 – 1610 nm

Connector type

MU horizontal

Pass–through Insertion Loss (dB)

2.5

Pass–through

ÂÂ ÂÂ ÂÂ Â ÂÂ Â

Demux side specification

ÂÂ ÂÂ ÂÂ Â ÂÂ Â

ÂÂ ÂÂ ÂÂ ÂÂ ÂÂ ÂÂ ÂÂ

In – Drop Ch.

CWDM line In

DROP Ch.

In–Drop Ch. Insertion Loss (dB)

Channels (nm)

1.55

1470 nm

1.55

1490 nm

1.55

1510 nm

1.55

1530 nm

1.55

1550 nm

1.55

1570 nm

1.55

1590 nm

1.55

1610 nm

Add Ch.– Out Insertion Loss (dB)

Channels (nm)

1.55

1470 nm

1.55

1490 nm

1.55

1510 nm

1.55

1530 nm

1.55

1550 nm

1.55

1570 nm

1.55

1590 nm

1.55

1610 nm

Mux side specificaton

1AA 00014 0004 (9007) A4 – ALICE 04.10

ADD Ch. –Out

ÂÂ ÂÂ ÂÂ ÂÂ ÂÂ ÂÂ Â ÂÂ

ADD Ch.

ED

CWDM Line OUT

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5.9.3 MUX/DEMUX 8 Channels

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General Characteristics Channels number

8

Channels wavelenght

1470 nm, 1490 nm, 1510 nm, 1530 nm, 1550 nm, 1570 nm, 1590 nm, 1610 nm

Connector type

MU horizontal

Demux side specification In – Drop Ch.

CWDM line In

ÂÂ ÂÂÂ ÂÂ ÂÂÂ ÂÂÂ ÂÂÂ ÂÂ ÂÂÂ

DROP Ch.

In–Drop Ch. Insertion Loss (dB)

Channels (nm)

1.05

1470 nm

3.15

1490 nm

2.85

1510 nm

2.55

1530 nm

2.25

1550 nm

1.95

1570 nm

1.65

1590 nm

1.35

1610 nm

Add Ch.– Out Insertion Loss (dB)

Channels (nm)

1.05

1470 nm

1.35

1490 nm

1.65

1510 nm

1.95

1530 nm

2.25

1550 nm

2.55

1570 nm

2.85

1590 nm

3.15

1610 nm

Mux side specificaton ADD Ch. –Out

ÂÂ Â ÂÂ ÂÂ ÂÂ ÂÂ Â ÂÂ

1AA 00014 0004 (9007) A4 – ALICE 04.10

ADD Ch.

ED

CWDM Line OUT

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5.9.4 2 Channels TRANSPONDER SFP without optical modulle

Optical interface characteristics: Refer to paragraph 5.9.5 on page 606 Optical module type:

SFP (APD or PIN) plug–in module

Bit rate client side

2488.320 Mbps : STM–16 / OC–48 2500 Mbps: 2 Gbit Ethernet (not operative in current release) 2.667 Gbps: STM–16 w/FEC (not operative in current release) 2125.00 Mbps: 2 Fiber Channel (not operative in current release) 1250 Mbps: Gbit Ethernet (not operative in current release) 1062.5 Mbps: FICON (not operative in current release) 1062.5 Mbps: Fiber Channel (not operative in current release) 622.080 Mbps: STM–4/OC12 (not operative in current release) 270 Mbps: Digital Video (not operative in current release) 200 Mbps: Escon (not operative in current release) 155.520 Mbps: STM–1/OC3 (not operative in current release) 125 Mbps: Fast Ethernet (not operative in current release) 125 Mbps: FDDI (not operative in current release)

5.9.5 CWDM optical PLUGIN

SFP module type

CWDM Silver

CWDM Bronze

APD

PIN

Detector type Addressed wavelength (nm)

1470,1490,1510,1530,1550,1570,1590,1610

Min. launched power (dBm)

0

0

Max launched power (dBm)

5

5

125 Mbps to 2.7 Gbps

125 Mbps to 2.7 Gbps

8.2

8.2

Max. –20dB bandwidth (nm)

1

1

Minimum SMSR (dB)

30

30

Allowed bitrates Min. extinction ratio (dB)

1AA 00014 0004 (9007) A4 – ALICE 04.10

Chromatic disp. (ps/nm)

1600 1600 1500 1400 1400 1300 1200 1100

1610 nm (λ) 1590 nm (λ) 1570 nm (λ) 1550 nm (λ) 1530 nm (λ) 1510 nm (λ) 1490 nm (λ) 1470 nm (λ)

1000 900 900 900 800 800 700 700

1610 nm (λ) 1590 nm (λ) 1570 nm (λ) 1550 nm (λ) 1530 nm (λ) 1510 nm (λ) 1490 nm (λ) 1470 nm (λ)

Minimum sensitivity (dBm)

–28

–18

Minimum overload (dBm)

–9

–3

Max optic. path penalty (dB)

2

1

Max receiver reflect. (dB)

–27

–27

Optical connector (Tx/Rx)

LC

LC

ED

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General Characteristics

S–16.1

L–16.1

L–16.2

Addressed wavelength (nm)

1270–1360

1280–1335

1500–1580

Min. launched power (dBm)

–5

–2

–2

Max launched power (dBm)

0

+2

+2

Allowed bitrates (Mbps)

2488320

2488320

2488320

Min. extinction ratio (dB)

8.2

8.2

8.2

Minimum sensitivity (dBm)

–18

–27

–28

Minimum overload (dBm)

–3

not available

not available

Max receiver reflect. (dB)

–27

–27

–27

Optical connector (Tx/Rx)

LC

LC

LC

1AA 00014 0004 (9007) A4 – ALICE 04.10

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SFP module type

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Input Voltage

48/60 Vdc " 20%

Input current

25 A max

Power supply interface

according to ETS 300132–2

5.11 Alarm Characteristics Units Alarms: Each port card or access card of the equipment is provided with a bicolor LED (green/red) on the front coverplate. This LED indicates: – –

when red, internal failure when green, in service unit

ATM MATRIX Alarms: All the alarm detected on the unit are related to the ATM traffic management; on the front are present optical indication (LEDs) with the following meaning: • • • • •

Red LED (3): detection of an MAJOR or CRITICAL (URGENT) alarm Red LED (4): detection of a MINOR (NOT URGENT) alarm Yellow LED (5): alarm condition ATTENDED Yellow LED (6): detection of an ABNORMAL operative condition. Yellow LED (7): detection of an WARNING (INDICATIVE) alarm

Refer to Figure 39. on 128 where the front view of the unit and the led locations are illustrated. Centralized Equipment Alarms: All the alarms detected on the units (except ATM matrix board) are collected by the EQUICO unit which will deliver centralized optical indications (by means of LEDs on its front coverplate). Specifically: • • • •

Red LED (4): detection of an MAJOR (URGENT) alarm Red LED (5): detection of a MINOR (NOT URGENT) alarm Yellow LED (6): alarm condition ATTENDED Yellow LED (7): detection of an ABNORMAL operative condition. Type: active loopbacks, forcing the unit into service, laser forced ON or OFF, try to restore after ALS Yellow LED (8): detection of an WARNING (INDICATIVE) alarm

•

Refer to para. 2.4 , page 120, where the front view of each unit and the LED locations are illustrated.

1AA 00014 0004 (9007) A4 – ALICE 04.10

N.B.

ED

On the Craft Terminal (C.T.) and on the Operation System (O.S). application the URGENT (URG), NOT URGENT (NURG) and INDICATIVE alarm are named in a different way; the relation between this two terminology is explained in Table 72. on page 609.

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5.10 Power Supply characteristics

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Table 72. Relation between Alarm severity terminology displayed on C.T./O.S. and alarm severity terminology used for the EQUICO leds and CONGI remote alarm connector pins. Alarm severity terminology on C.T. and O.S.

Alarm severity terminology used for EQUICO leds and for CONGI remote alarm connector pins

CRITICAL or MAJOR

URG , T*URG, T*RURG,

MINOR

NURG, , T*NURG, T*RNURG

WARNING

INDICATIVE

INDETERMINATE (not used)

––

Rack lamps and Remote Alarms: Some equipment alarms are carried to a connector, for customer applications, such as lighting–up of alarm lamps (rack–lamps) or to drive a custom–alarms interface. Rack alarm and Remote Alarm are physically available on the CONGI board connectors. The available alarms are the following: Rack lamps alarms: • • •

T*RURG: urgent alarm (see Table 72. on page 609 for the C.T. terminology) T*RNURG: not urgent alarm (see Table 72. on page 609 for the C.T. terminology) T*RATTD: alarm storing

Remote alarms: Remote alarms delivered by CONGI in slot 10: •

T*URG: detection of an urgent alarm (from Controller) (see Table 72. on page 609 for the C.T. terminology) T*NURG: detection of a non–urgent alarm (from Controller) (see Table 72. on page 609 for the C.T. terminology) T*INT: detection of an Internal alarm (from Controller) T*AND: loss of both battery station T*OR : fault or loss of one battery station

• • • •

Remote alarms delivered by CONGI in slot 12: • • •

T*TORC: It indicates a loss of +3.3V generated by the on board DC/DC converter of one CONGI card. T*IND: Indeterminate alarm. It indicates synthesis of alarms not associated to the other severity (not used) T*TUP: It indicates aN EQUICO microprocessor fault T*TANC: It indicates loss of + 3.3 V generated by the on board DC/DC converters of both CONGI cards (it can be stored). LOSQ2 : It indicates loss of communication with the Mediation Device (not used).

• •

1AA 00014 0004 (9007) A4 – ALICE 04.10

•

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HouseKeeping Alarms/Commands:

–

2 wires mode Four output (CPO) and 12 input (CPI) contacts for house–keeping alarms or commands are available on the CONGI board connector, for customer applications The available house–keeping contacts are the following: • •

–

HK–OUT 1 to 4: outgoing contacts HK–IN 1 to 12: Incoming contacts

3 wires mode: Four output (CPO) and eight input (CPI) contacts for house–keeping alarms or commands are available on the CONGI board connector, for customer applications The available house–keeping contacts are the following: • •

HK–OUT 1 to 4: outgoing contacts HK–IN 1 to 8: Incoming contacts

Alarm Attending: The detected SDH units alarm condition can be stored through push–button (10) on the EQUICO unit (Attended). This operation will turn OFF the general red LED (4) and will light up the yellow LED (6) on the EQUICO unit (Attended); The attended command is also sent to the rack lamps (if present) through the CONGI board. Trouble–shooting: The 1660SM equipment has been designed to dialog with a Personal Computer (PC) in order to service, activate and trouble–shoot the equipment. Trouble–shoot procedure for the equipment and details of the alarms for each card and relevant indications are described in the Operator’s Handbook. Connection with the PC is achieved through connector (2) available on the EQUICO board. The unit can be connected to an Operations System associated to the Transmission Management Network in order to execute operations similar to those carried out by the PC.

1AA 00014 0004 (9007) A4 – ALICE 04.10

Characteristics of the cited remote alarms and Housekeeping contacts interface (EM type) are inserted in Chapter 5.1 on page 557.

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According to CONGI units settings two operative mode are available:

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5.12 Mechanical characteristics Mechanical compatibility

ETSI ETS/E3, S9

Subrack size

482 W x 250 D x 650 H mm

Board size

213 D x 265 H mm

Subrack weight

35 Kg

Cooling

Fans in additional subrack

Rack cabling

Vertical between rack and subrack front access

Electrical Connectors

IEC 603/DIN 41612 IEC 807 (Sub–D) IEC 169–1 (coax. 1.0/2.3) BNC 50 Ω RJ45 RJ11

1AA 00014 0004 (9007) A4 – ALICE 04.10

Back–to–back installation

ED

Yes

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5.13.1 Climatic for operating conditions The Equipment meets the requirements of ETSI Standard with use of fans housed in an external subrack. The functionality of the 1660SM Equipment, Vs. Temperature, is in compliance with : ETS 300 019–1–3 :1992 , class 3.2. Class 3.2:

Partly temperature–controlled locations. (see climatogram on Figure 281. on page 613)

5.13.1.1 Class 3.2: partly Temperature controlled locations This applies to locations: –

where installed equipment may be exposed to solar radiation and heat radiation. They may also be exposed to movements of the surrounding air due to draughts in buildings, e.g. through open windows. They may be subjected to condensed water and to water from sources other than rain and icing. They are not subjected to precipitation;

–

where mould growth or attacks by animals, except termites, may occur;

–

with normal levels of contaminants experienced in urban areas with industrial activities scattered over the whole area and/or with heavy traffic;

–

In close proximity to sources of sand or dust;

–

with vibration of low significance, e.g. for products fastened to light supporting structures subjected to negligible vibrations.

1AA 00014 0004 (9007) A4 – ALICE 04.10

The conditions of this class may be found in : –

entrances and staircases of buildings;

–

garages;

–

cellars;

–

certain workshops;

–

buildings in factories and industrial process plants;

–

unattended equipment stations;

–

certain telecommunication buildings;

–

ordinary storage rooms for frost resistant products and farm buildings, ect.

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5.13 Environmental conditions

1AA 00014 0004 (9007) A4 – ALICE 04.10

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29

5

ED 95

Figure 281. Climatogram for Class 3.2 : Partly temperature controlled locations

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5.13.2 Storage

ETS 300 019–1–1 : 1992, class 1.2 Class 1.2 : weatherprotected, not temper. controlled storage location. This class applies to weatherprotected storage having neither temperature nor humidity control. The location may have openings directly to the open air, i.e., it may be only partly weatherproofed. The climatogram is shown on Figure 282. on page 615. This class applies to storage locations : –

where equipment may be exposed to solar radiation and temporarily to heat radiation: They may also be exposed to movements of the surrounding air due to draughts, e.g. through doors, windows or other openings. They may be subjected to condensed water, dripping water and to icing. They may also be subjected to limited wind–driven precipitation including snow;

–

where mould growth or attacks by animals, except termites, may occur;

–

with normal levels of contaminants experienced in urban areas with industrial activities scattered over the whole area, ad/or with heavy traffic;

–

in areas with sources of sand or dust, including urban areas;

–

with vibration of low significance and insignificant shock.

1AA 00014 0004 (9007) A4 – ALICE 04.10

The conditions of this class may occur in : –

unattended buildings ;

–

some entrances of buildings ;

–

some garages and shacks.

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The 1660SM equipment meet the following requirements Vs. Storage :

1AA 00014 0004 (9007) A4 – ALICE 04.10

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29

Figure 282. Climatogram for Class 1.2: not temperature controlled storage location

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5.13.3 Transportation

ETS 300 019–1–2 : 1992, class 2.2

Class 2.2 : Careful transportation (see Table 73. on page 617 ). This class applies to transportation where special cars has been taken e.g. with respect to low temperature and handling. Class 2.2 covers the condition of class 2.1. In addition class 2.2 includes transportation in all types of lorries and trailers in areas with well–developed road system. It also includes transportation by ship and by train specially designed, shock–reducing buffers. Manual loading and unloading of to 20 Kg is included. Extension of extreme low temperature during transportation is permitted for the 1660SM equipment in its standard packing : AT –40° C for 72 Hours maximum

1AA 00014 0004 (9007) A4 – ALICE 04.10

without damaging the Optical interfaces.

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The 1660SM equipment meets the following requirements Vs. transportation :

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Table 73. Transportation climatic

Unit

2.1 and 2.2

2.3

°C

– 25

– 40

°C

+ 70

+ 70

°C

+ 40

+ 40

°C

–25 / +30

–40 / +30

°C

+40 / +5

+40 / +5

relative humidity, not combined with rapid temperature changes

% °C

95 +40

95 +45

relative humidity, combined with rapid (G) temperature changes air/air, at high relative humidity (NOTE 3 , 6)

%

95

95

°C

–25 / +30

–40 / +30

absolute humidity, combined with rapid (H) temperature changes : air/air at high water content (NOTE 4)

g/m3

60

60

°C

+70 / +15

+70 / +15

(I)

low air pressure

KPa

70

70

(J)

change of air pressure

KPa/min

no

no

m/s

20

20

mm/min

6 (NOTE 7)

6

(M) radiation, solar

W/m2

1120

1120

(N) radiation, heat

W/m2

600

600

m/s

1 (NOTE 7)

1

Environmental parameter (A) low temperature air (B)

high temperature, air enclosures (NOTE 1)

in

(C)

high temperature, air in ventilated enclosures or outdoor air (NOTE 2)

(D) change of temperature air/air

unventilated

(NOTE 3)

(E) change of temperature air/water (F)

(NOTE 3)

(K) movement of the surrounding medium, air (L)

precipitation rain

(O) water from sources other than rain (NOTE 5) (P) wetness

none

conditions of wet surfaces

1AA 00014 0004 (9007) A4 – ALICE 04.10

Notes on next page.

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NOTE 1 :

The high temperature of the surfaces of a product may be influenced by both the surrounding air temperature, given here, and the solar radiation through a window or another opening.

NOTE 2 :

The high temperature of the surface of a product is influenced by the surrounding air temperature, given here, and the solar radiation defined below.

NOTE 3 :

A direct transfer of the product between the two given temperature is presumed.

NOTE 4 :

The product is assumed to be subjected to a rapid decrease of temperature only (no rapid increase). The figures of water content apply to temperatures down to the dew–point; at lower temperatures the relative humidity is assumed to be approximately 100 %.

NOTE 5 :

The figure indicates the velocity of water and not the height of water accumulated.

NOTE 6 :

Occurrence of condensation.

NOTE 7 :

For short duration only.

5.13.4 EMI/EMC condition

1AA 00014 0004 (9007) A4 – ALICE 04.10

For the EMI/EMC condition see para 4.1 on page 39.

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Notes to Table 73. :

1AA 00014 0004 (9007) A4 – ALICE 04.10

MAINTENANCE

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1AA 00014 0004 (9007) A4 – ALICE 04.10

ED

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6 MAINTENANCE

ATTENTION

EMC NORMS

WHEN CARRYING OUT THE GIVEN OPERATIONS OBSERVE THE NORMS STATED IN PARA. 4.1.3 ON PAGE 40

6.1 General safety rules

SAFETY RULES Carefully observe the front–panel warning labels prior to working on optical connections while the equipment is in–service. Should it be necessary to cut off power during the maintenance phase, proceed to switch off the power supply units as well as cut off power station upstream (rack or station distribution frame)

SAFETY RULES A TNV–2 (battery) voltage could be present on “R/M interface connector” (cable side); do not touch the pins when unplugged . DANGER: Possibility of personal injury. Short circuiting, low-voltage, low-impedance, dc circuits can cause severe arcing that can result in burns and/or eye damage. Remove rings, watches, and other metal jewelry before working with primary circuits. Exercise caution to avoid shorting power input terminals.

SAFETY RULES

1AA 00014 0004 (9007) A4 – ALICE 04.10

DANGER: Possibility of eyes damage: read carefully and strictly observe the rules pointed out in para.3.2.4.2 on page 35.

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•

Check that the equipment is operating with all the shields properly positioned (dummy covers, ESD connector protections, etc)

•

In order to reduce the risk of damage the electrostatic sensitive devices, is mandatory to use the elasticized band (around the wrist) and the coiled cord joined connect with the ground rack during the touching of the equipment

6.3 Maintenance Aspects Maintenance consists of a set of operations which maintain or bring back the assembly to optimum operating conditions in a very short time, with the aim of obtaining maximum operational availability. Maintenance is classified as: •

ROUTINE

•

CORRECTIVE

6.4 Instruments And Accessories There is a local terminal (PC) which permits to display all the alarms and manages the Equipment. The relative processing is described in the operator’s handbook. Where TMN is implemented, an Operation System displays alarms and manages all the connected Equipments of the network. Refer to the relevant handbooks.

1AA 00014 0004 (9007) A4 – ALICE 04.10

The need of special tools and accessories to perform possible routine and corrective maintenance procedures is described inside the procedures themselves.

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6.2 General rules

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6.5 Routine Maintenance Routine maintenance is a periodic set of measurements and checks. This maintenance discovers those devices whose function has deteriorated with time and therefore need adjustment or replacement. Typically, digital equipment requires no routine maintenance. The equipment allows to assess the quality of the connection links for SECTION and PATH o counting the errored events and obtaining performance data. The Performance Monitoring Application, described in the Operator’s Handbook, allows this function.

6.5.1 Routine maintenance every three months According to the filter type It is suggested to carry out the following operations every three months: –

Metallic filter cleaning

–

Dust filter substitution

6.5.1.1 Metallic filter cleaning Metallic Filter cleaning (caution to avoid equipment damage) WARNING: BEFORE INSTALLING OR REMOVING THE METALLIC FILTER , CHECK THAT THE PROTECTIVE ADHESIVE FILM HAS BEEN REMOVED.

SAFETY RULES DANGER: Possibility of personal injury. Personal injury can be caused by rotating fans. •

Replace the “Metallic filter” from the FANS Shelf as follow : – unscrew the screws that ensure the Metallic filter to the fans shelf – extract the Metallic filter – clean the metallic filter removing the dust – Insert and ensure the “Metallic filter” to the “FAN shelf“ using the relevant screw

1AA 00014 0004 (9007) A4 – ALICE 04.10

Note: the period of one three months is only indicative; according to the environmental conditions could be necessary to reduce this period.

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02 3AL 91668 AA AA 636

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6.5.1.2 Dust filter for fan shelf 19” substitution

(caution to avoid equipment damage) WARNING: BEFORE INSTALLING OR REMOVING THE DUST FILTER , CHECK THAT THE PROTECTIVE ADHESIVE FILM HAS BEEN REMOVED.

SAFETY RULES DANGER: Possibility of personal injury. Personal injury can be caused by rotating fans. •

Replace the “Dust filter” from the FANS Shelf as follow : – unscrew the screws that ensure the dust filter to the fans shelf – extract the Dust filter – insert the new Dust filter – ensure the “Dust filter” to the “FAN shelf“ using the relevant screw

Note: It is suggested to replace the filter every 3 months; this period is indicative and must be verified according to the environmental conditions. 6.5.2 Routine maintenance every year It is suggested to carry out the following operations yearly: •

power cables check

6.5.2.1 Power cables check

SAFETY RULES DANGER: Possibility of personal injury. Personal injury can be caused by –48 V dc. DANGER: Possibility of personal injury. Short circuiting, low-voltage, low-impedance, dc circuits can cause severe arcing that can result in burns and/or eye damage. Remove rings, watches, and other metal jewelry before working with primary circuits. Exercise caution to avoid shorting power input terminals.

1AA 00014 0004 (9007) A4 – ALICE 04.10

Make these operations:

ED

•

Check that the power cable is perfectly safety grounded.

•

Make sure that the subrack has been tightly fastened to the rack with screws, to guarantee grounding (the rack is connected to the station ground).

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All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

Dust Filter SUBSTITUTION

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

6.5.3 Routine Maintenance every five year It is suggested the replacement of each FANS UNIT equipped in the Fans Subrack after five years of working. For the substitution refer to the sequences shown in paragraph 6.6.1 on page 625 (Fan unit for fan shelf 19”substitution).

6.6 Corrective Maintenance (Trouble/Shooting) Since the Troubleshooting procedure is carried out with the use of the Craft Terminal , please refer ,for details, to the Maintenance Section of the Operator’s Handbook. FIXING THE UNITS (AND MODULES) INTO THE SUBRACK (caution to avoid equipment damage) The screw tightening torque for fixing the units (and modules, if any and if fixed by screws) into the subrack must be:

2.8 kg x cm (0.28 Newton x m) " 10 % Exceeding this value may result in screw breaking.

6.6.1 Fan unit for fan shelf 19”substitution

SAFETY RULES DANGER: Possibility of personal injury. Personal injury can be caused by –48 V dc. DANGER: Possibility of personal injury. Short circuiting, low-voltage, low-impedance, dc circuits can cause severe arcing that can result in burns and/or eye damage. Remove rings, watches, and other metal jewelry before working with primary circuits. Exercise caution to avoid shorting power input terminals. When an ALM_URG alarm is displayed on C.T or O.S. ( associated to an Housekeeping alarm) it means that at least one fan is broken, so it is necessary to replace the “FAN unit” involved. These alarm indications are also displayed on the Fans Subrack front panel.

1AA 00014 0004 (9007) A4 – ALICE 04.10

To substitute the faulty “ Fan unit “ (red led ON) follows the instruction below : –

unscrew the screws that ensure the Fan unit to the fans shelf

–

extract the Fan unit from the Fan shelf

–

insert the new Fan unit into the Fan shelf

–

ensure the Fan unit to the “FAN shelf“ using the relevant screw

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6.7.1 Suggested Spare Parts The overall number of spares depends on Customer requirements, and should be based on the average amount of transmission circuits available to be accounted for not only during MTBF but also during MTTR; the latter depending on the amount of spare parts available. The set of spare parts is inclusive of a minimum number of spares for each type of replaceable plug–in unit (see unit list in Chapter 2 on page 85). 6.7.2 General rules on spare parts management Before storing the spare units make sure that they are working by inserting them in an operating equipment It is suggested to periodically check those spare units have not been utilized for over a year. If the spare parts and the equipment are stored in the same environment, make sure that the spare parts are placed in cabinets to safeguard them from dust and damp. Moreover, they should also be well grounded to avoid electrostatic discharges. If the spare parts are stored in another room, or have to be moved from another place, building or site, make sure that the following is observed: –

the spare parts must be wrapped in anti–static and padded envelopes;

–

the spare parts must not touch wet surfaces or chemical agents that might damage them , gas);

–

if during transport the temperature is lower than that of the room where they had been kept, make sure that before using them they pass a certain period in a climatic chamber to prevent thermal shocks and/or the possibility of steaming up.

(e.g.

When replacing a unit/sub–unit, make sure that the spare unit/sub–unit is set exactly as the replaced one. For the presettings procedures see section HARDWARE SETTING DOCUMENTATION.

6.7.3 Particular rules on spare parts management Whenever some units with flash-memories are common to different kinds of equipment or to different versions of the same type of equipment, it is possible to maintain one spare part only: this allows spare part stock saving, even though software downloading will be necessary when the software loaded into the unit (program part or data part) is different from that necessary in the equipment where the spare unit must be used. At the end of the commissioning phase or after an equipment data change, it is suggested to save the equipment data, e.g. on floppy disk, and store this floppy disk in the spare part stock pointing out the equipment it refers to.

1AA 00014 0004 (9007) A4 – ALICE 04.10

6.8 Repair Form To facilitate operation, data on the faulty unit must be reported on the form shown in Figure 283. on page 627. The repair form must be filled–in with as much data as possible and returned to ALCATEL together with the faulty unit.

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All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

6.7 Set of spare parts

ALCATE L

REPAIR FORM CUSTOMER NAME

ORDER NUMBER/CONTRACT NUMBER

SITE

BRANCH/UNIT/COUNTRY

SYSTEM/EQUIPMENT

PRODUCT RELEASE

STATION/RACK

TO BE FILLED IN BY THE SENDER

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

Fill in this form and affix it to the faulty unit to be returned to Alcatel

EQUIPMENT SOFTWARE PART NUMBER

SUBRACK

SLOT

MNEMONIC

ALCATEL PART NUMBER

SERIAL NUMBER

FAULTY UNIT SOFTWARE VERSION

FAULT PHASE

REASON FOR REPAIR

PRESUMED CAUSE

INSTALLATION / TURN ON

CLEAR FAULT

DROP IN PERFORMANCE

OPERATION

INTERMITTENT FAULT

UPGRADE/QUALITY ALERT

INTERNAL

LIGHTNING

EXTERNAL

MAINTENANCE

AIR COND.

TEMPERATURE FAULT

OTHER

DATE

NAME OF SENDER

FAULT STILL PRESENT AFTER REPAIR

1AA 00014 0004 (9007) A4 – ALICE 04.10

TO BE FILLED IN BY THE REPAIR OPERATOR

COMMENTS

FAULTS DETECTED

PROCESSING UPGRADE

NO FAULTS FOUND

SOLDERING / WIRING

A STANDARD REPAIRING

I NOT REPAIRABLE (REJECTED)

F–L

MECHANICAL M

B–D

ADJUSTMENT

COMPONENT C PRINTED CIRCUIT BOARD V1

P DIRT

V1

V2

SUBSTITUTED QUALITY ALERT

CORROSION I

OTHER

S–X

V3

NOTE : LETTERS ARE FOR FACTORY USE

COMMENTS

DATE

REPAIRING NUMBER

REPAIRING CENTRE

NAME OF REPAIR OPERATOR

Figure 283. Repair form

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1AA 00014 0004 (9007) A4 – ALICE 04.10

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02

3AL 91668 AA AA

636

628 / 636 All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

1AA 00014 0004 (9007) A4 – ALICE 04.10

HARDWARE SETTING DOCUMENTATION

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1AA 00014 0004 (9007) A4 – ALICE 04.10

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3AL 91668 AA AA

636

630 / 636 All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

UNITS DOCUMENTATION LIST This section contains the documents sheets to refer to for unit/sub–unit hardware setting options. The list of the enclosed documents is given in Table 75. on page 634, according to the ANV part number. TABLE EXPLANATION: –

UNIT IDENTIFICATION P/Ns AND CHANGE STATUS Each unit or sub-unit is distinguished by: •

a dual Part No.: –

Factory P/N (4xx.xxx.xxx x)

–

ANV P/N (xxx.xxxxx xx) (NOTE)

NOTE

•

The last two ANV-P/N letters (in the following stated as ’suffix’) stand for a ”feasible alternative”, they might differentiate two units eventhough still functionally compatible. For this reason the indicated ANV P/N does not include the last two letters. For example : the units having P/Ns ”3AL–34065–AAAA” and ”3AL–34065–AABA” are functionally compatible and, as regards to hardware settings, the MSxxx document (described hereafter) 3AL–34065–AAAA-MSxxx is applicable for both.

and by a pair of design & production series (change status): –

CS, associated to the Factory P/N (4xx.xxx.xxx x)

–

ICS, associated to ANV P/N (xxx.xxxxx xx)

The following table shows an example of correspondence between ”FACTORY P/N + CS” and ”ANV P/N + ICS” Table 74. Example of correspondence between CS and ’suffix + ICS’ N.B.

The P/Ns used in this example have no correspondence with those of the actual equipment part list! FACTORY CODE

ANV CODE

P/N

CS

P/N

ICS

487.156.612

01

3AL 34422 AA AA

01

487.156.612

02

3AL 34422 AA AB

01

487.156.612

03

3AL 34422 AA AC

01

1AA 00014 0004 (9007) A4 – ALICE 04.10

In this example you can see that the production series is identified only by the CS as far as the Factory code is concerned, and by the ’suffix + ICS’ if the ANV code is referred to. Some of the possible positions of the label indicating the unit’s P/Ns and CS–ICS are illustrated in para. 4.4 on page 42.

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CROSS–REFERENCE •

Id.

Unit alphabetical notation. It indicates the unit containing one or more subunits.

•

App.

It reports the unit notation (Id) to which the sub–unit belongs.

The HARDWARE SETTINGS can be executed after having checked all the sub–units belonging to a unit, by considering the above cited cross–reference, and by using the presetting documents indicated in Table 75. page 634 and presented in the following point. –

ENCLOSED DOCUMENTS For each type of unit or sub-unit having customizing setting options, the document ”ANV P/N”–MSxxx is annexed to this handbook (in the case of Documentation on CD-ROM the MSxxx documents may be given in a CD-ROM different from that containing this Technical Handbook). The MSxxx documents are enclosed in numerical order. The Edition of the enclosed MSxxx document is the highest available on the date on which the Technical Handbook is assembled. Use of the document MSxxx: •

MSxxx means ”document for hardware presetting options” (the MSxxx document’s Part No. is as that of the unit or sub-unit and its MS acronym defines type). The xxx part of MSxxx is relevant to ANV internal identification codes.

•

As the Customer may have to manage many units of the same type (same P/N) but with different CS–ICS, the document MSxxx describes with possible different chapters the different setting options, according to all the possible CSs–ICSs. For this purpose, a table at the beginning of document (PREFACE) indicates the chapter to be used according to the CS or the corresponding ’suffix + ICS’, taking into account that: –

–

–

a change of the production series does not necessarily imply a change in the setting options; a change of the ANV P/N suffix does not imply a new MSxxx document; the CS, SUFFIX and ICS must be meant as: • from specified CS, SUFFIX or ICS (included) • to next CS, SUFFIX or ICS (excluded) if listed the sequence of CSs is increasing from alphanumeric to numeric (e.g. CS=A0 is lower than CS=01).

Each chapter contains: – –

one or more tables defining the relationship between the functions achievable and the setting options to make; the unit layout drawing which shows the exact location of all the setting options. N.B.

1AA 00014 0004 (9007) A4 – ALICE 04.10

N.B.

IDENTIFIES PIN 1 OF COMPONENT When necessary to make ”TC” Hardware Settings fitted on the rear side of the board, remove the protective cover plate present on the same rear side and replace it at the end of the operation

The setting options described in the documents MSxxx must be used according to 3AL377470001 (962.000.022 F) MSxxx document, inserted in Table 75. on page 634, which shows the ’ON’ (closed) position of microswitches. Those setting options that on the table are indicated by the caption For factory use only should never be modified.

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All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

–

EXAMPLE The P/Ns used in this example have no correspondence with those of the actual equipment part list!

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

N.B.

Taking into account the same unit of Table 74. on page 631: FACTORY CODE

ANV CODE

P/N

CS

P/N

ICS

487.156.612

01

3AL 34422 AAAA

01

487.156.612

02

3AL 34422 AAAB

01

487.156.612

03

3AL 34422 AAAC

01

and supposing that the setting options valid for CS=01 are equal to those for CS=02, but change for CS=03, the table at the beginning of the document 3AL 34422 AAAA MSZZQ will be:

CHAPTER CAPITOLO

FACTORY P/N CODICE DI FABBRICA

ANV P/N CODICE ANV

FROM CS DA CS

FROM SUFFIX DA SUFFISSO

FROM ICS DA ICS

1

01

––AA

01

2

03

––AC

01

If you have the unit identified by one of this identification data: FACTORY CODE

ANV CODE

P/N

CS

P/N

ICS

487.156.612

01

3AL 34422 AAAA

01

487.156.612

02

3AL 34422 AAAB

01

you will use Chapter 1 of document 3AL 34422 AAAA MSZZQ

If you have the unit identified by one of this identification data:

1AA 00014 0004 (9007) A4 – ALICE 04.10

FACTORY CODE

ANV CODE

P/N

CS

P/N

ICS

487.156.612

03

3AL 34422 AAAC

01

487.156.612

04

3AL 34422 AAAD

01

you will use Chapter 2 of document 3AL 34422 AAAA MSZZQ

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The edition of the documents (listed in this table) that are physically enclosed in the handbook is the highest available when this handbook is assembled. The edition of enclosed documents is not specified in this table.

NAME

Id

3AL 78830 AD––

Document for hardware presetting 3AL 78830 AAAG MSZZQ

Control and general XT

b

Equipment Controller

3AL 78836 AA–– (411.100.708V )

–

c

ATM MATRIX 4x4

3AL 79093 AA–– (411.101.035 J)

–

d

ATM MATRIX D3

3AL89917 AA–– ––.––.––

–

e

ATM MATRIX 4x4 ENHANCED

3AL 81185 AA–– (411.102.475 Z)

–

f

ATM MATRIX 8x8

3AL79094 AA–– (411.101.036 K)

–

g

PR_EA MATRIX 4XETH

3AL 79631 AA–– (411.101.281 W)

–

h

PR_EA MATRIX 1XGB–ETH

3AL 81275 AA–– (411.102.505 Y)

–

i

ISA–ES1 8FE BOARD

3AL 98128 AA––

–

j

ISA–ES1 8FX BOARD (SFP)

3AL98150AA––

–

k

ISA–ES4 8FE + 1GE BOARD

3AL 81879AA––

–

l

ISA–ES16 BOARD

3AL 81915 AA––

–

Microswitches ”ON” position

3AL 37747 0001 (962.000.022 F)

3AL 37747 0001 MSZZQ

f

3AL 79202 AA–– (487.156.804 W)

3AL 79202 AAAA MSZZQ

g, h

3AL 79425 AA–– (483.100.252 )

3AL 79425 AAAA MSZZQ

Equipment Controller

b

3AL 79747 AAAA (487.156.090 Z)

3AL 79747 AAAA MSZZQ

ATM MATRIX 4x4

c

3AL 80481 AA–– (487.156.138 Z)

3AL 80481 AAAA MSZZQ

ATM MATRIX 4x4 ENHANCED

d, e

3AL 81183 AA–– (487.156.274)

3AL 81183 AAAA MSZZQ

L2 ETHERNET PORT BOARD

k

3AL81878AA––

3AL81878AAAA MSZZQ

NETWORK PROCESSOR 2

1AA 00014 0004 (9007) A4 – ALICE 04.10

ANV P/N (Factory P/N)

a

ATM MATRIX 8x8

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All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

Table 75. Hardware presetting documentation

App

ANV P/N (Factory P/N)

Document for hardware presetting

PBA–ISA–PREA V2

l

3AL81916AA––

3AL81916AAAA MSZZQ

PBA–ISA FE V2–155

i

3AL98127AA––

3AL98127AAAA MSZZQ

PBA–ES1–8FX

j

3AL98149AA––

3AL98149AAAA MSZZQ

1AA 00014 0004 (9007) A4 – ALICE 04.10

All rights reserved. Passing on and copying of this document, use and communication of its contents not permitted without written authorization from Alcatel.

Id

ED

NAME

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1AA 00014 0004 (9007) A4 – ALICE 04.10

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END OF DOCUMENT

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LABELS AND ASSEMBLY INSTRUCTIONS TARGHETTE E INFORMAZIONI PER IL CENTRO STAMPA

QUESTA PAGINA NON VA INSERITA NEL MANUALE THIS PAGE MUST NOT BE INCLUDED IN THE HANDBOOK COD.MANUALE HDBK P/N:

3AL 91668 AAAA Ed.02

1660SM Rel.4.4 TECHNICAL HANDBOOK ORIGINALE INTERLEAF: FILE ARCHIVIAZIONE: cod ANV (PD1-PD2) – –

No PAGINE TOTALI PER ARCHIVIAZIONE: 638+4=642 DIMENSIONE BINDER SORGENTE (du –ks): 79.836 kBytes

INFORMAZIONI PER IL CENTRO STAMPA - ASSEMBLY INSTRUCTIONS –

STAMPARE FRONTE/RETRO RECTO-VERSO PRINTING

–

COMPOSIZIONE ED ASSIEMAGGIO DEL MANUALE: HANDBOOK COMPOSITION AND ASSEMBLY: numerate numbered

No pagine (facciate) No pages

da from

a to

2

1/2

2/2

TARGHETTE - LABELS frontespizio front 3AL 91668 AAAA Ed.02

manuale manual

ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ 636

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Vedere lista a pagina: ALLEGATI DI UNITÀ (MSZZQ) See list on page: UNIT PRESETTING DOCUMENTS (MSZZQ) 636 TOTALE PAGINE A4 (FACCIATE) TOTAL A4 PAGES:

638

TOTALE FOGLI A4 TOTAL A4 SHEETS:

319

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No documenti MSZZQ No documents MSZZQ 11

WARNING FOR A-UNITS OTHER THAN A-ITALY

1AA 00014 0004 (9007) A4 – ALICE 04.10

•

The documents MSZZQ cited in section ’HARDWARE SETTING DOCUMENTATION’ are stored in eMATRIX. Labels are done according to A-Italy binder format. Source file ALICE 6.10

• •

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THIS PAGE MUST NOT BE INCLUDED IN THE HANDBOOK

FCG

Originators P. GHELFI

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TECHNICAL HANDBOOK

Domain Division Rubric Type Distribution Codes

: : : :

OND SDH 1660SM 1660SM REL. 4.4 TECHNICAL HANDBOOK Internal : External :

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Name App.

INFORMAZIONI EDITORIALI –

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3AL 91668 AAAA Ed.02 3AL 91668 AAAA Ed.02

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