The Philosophy of Symbolic Forms, Volume 3: Phenomenology of Cognition 1000001111, 9781000001112, 1000001113

Citation preview

GATE 2022 conceptually empowered and error free

S

olutions

to enhance solving skills

Digital Circuits A K Tripathi

Mechasoft Publishers

MD, Mechasoft Publishers Retd. Prof., Department of Electronics IERT Allahabad (INDIA)

MRP : 150.00 Copyright © : 2015,2021 Mechasoft Publishers No part of this publication may be reproduced or distributed in any form or by any means, electronic, mechanical, photocopying, recording or otherwise or stored in a database or retrieval system without the prior written permission of the publisher. Mechasoft Publishers, Allahabad (INDIA)

E-mail : [email protected]

Dedicated to Promotion and Elevation of Engineering Education and Way of Life as Gifted by

ALMIGHTY "of which We are an Integral Part”

Preface The prime objective of the Kindle version of Digital Circuits ,GATE , EC , a sequel to GATE Solutions Series to Enhance Solving Skills' is to meet ever growing demand for awless, error free and succinct but conceptually empowered solutions to all the questions over the period 2003-2021. Step by step solutions together with theoretical explanations mark the strength of the text. Perusing the questions asked over the period of last 20 years , it is envisaged that the concepts are repeated, not the questions. Keeping this in view , the adequate stress has been laid to build concepts while bringing out the solutions. This e-book is designed subject wise and chapter wise to particularly supplement the texts for Electronics, Electrical and Instrumentation engineering . The key idea behind this text is to portray a ‘dialogue between a teacher and taught’ in the form of problems and solutions to unfold the intricacies of ‘Digital Circuits ‘so as to keep the students at natural ease at competitive/Universty examinations with ample condence. We do not sense any decit in believing that this title will, in many aspects, be different from the similar titles within the reach of students. In particular, we wish to thank Shreyansh Mishra who typed the entire manuscript in expert fashion, not once but several times . We would also not forget to thank Mr. Triloki Nath Mishra, sincere personality for his consistent persuasion to complete the task. Finally, We extend our appreciation to the family members, Shalini, Pranjali and Divyansh for their unwavering help and patience. The nal manuscript has been prepared with utmost care. However, following the saying that, there is always room for improvement in anything done we would welcome and greatly appreciate suggestions and corrections for further improvements. A
K
Tripathi

CONTENTS Preface 1.Number Systems, Boolean Algebra

IV

and Karnaugh Map Minimization

Questions Answer Key Solutions

1-10 10 11-22

2.Arithmetic Circuits and Code Converters Multiplexer ,Decoder ,PLA and ROM

Questions Answer Key Solutions

23-31 31 32-42

3.Sequential Circuits flip flops , counters, shift registers and FSM

Questions

Answer Key Solutions

43-56 56 57-72

4. ADCs, DACs, Sample and Hold Questions Answer Key Solutions

73-77 77 78-81

5.CMOS Synthesis Questions Answer Key Solutions

83-87 87 88-93

1

Number Systems, Boolean Algebra and Karnaugh Map Minimization

Chapter

Section1

GATE Questions

Q1. If (1235)x=(3033)y, where x and y indicate the bases of the corresponding numbers , then (a) x=7 and y=5

(b) x=8 and y=6

(c) x=6 and y=4

(d) x=9 and y=7 [GATE 2021/1mark] Q2. The two numbers represented in signed 2's complement form are P = 11101101 and Q = 11100110. If Q is subtracted from P, the value obtained in signed 2's complement is (a) 1000001111

(b) 00000111

( c) 11111001

(d) 111111001 [GATE 2008/2marks]

Q3. X = 01110 and Y = 11001 are two 5-bit binary numbers represented in two's complement format. The sum of X and Y represented in two's complement format using 6 bits is (a) 100111

(b) 001000

(c) 000111

(d) 101001 [GATE 2007/1mark]

Q4. A new Binary Coded Pentary (BCP) number system is proposed in which every digit of a base-5 number is represented by its corresponding 3-bit binary code. For example, the base-5 number 24 will be represented by its BCP code 010100. In this numbering system, the BCP code 100010011001 corresponds to the following number in base-5 system (a) 423

(b) 1324

(c) 2201

(d) 4231 [GATE 2006/2marks]

Q5. Decimal 43 in Hexadecimal and BCD number system is respectively (a) B2, 0100 0011

(b) 2B, 0100 0011

( c) 2B, 0011 0100

(d) B2, 0100 0100 [GATE 2005/1mark]

Q6. The range of signed decimal numbers that can be represented by 6-bits in 1's complement format is (a) −31 to + 31

(b) −63 to + 63

(c) −64 to + 63

(d) −32 to +31 [GATE 2004/1mark] Q7. 11001, 1001 and 111001 correspond to the 2's complement representation of which one of the following

sets?

[GATE 2004/2marks]

(a) 25, 9 and 57 respectively

(b) – 6, – 6 and – 6 respectively

( c) – 7, –7 and – 7 respectively

(d) – 25, – 9 and – 57 respectively

GATE Questions Mechasoft 02 Q8. A function F(A, B, C) defined by three Boolean variables A, B and C when expressed as sum of products is given by F = A × B × C + A × B × C + A × B × C where, A, B, and C are the complements of the respective variables. The product of sums (POS) from of the function F is (a) F = (A + B + C ) × (A + B + C ) × (A + B + C ) (b) F = (A + B + C ) × (A + B + C ) × (A + B + C ) ( c) F = (A + B + C ) × (A + B + C ) × (A + B + C ) × (A + B + C ) × (A + B + C ) [GATE 2018/1mark] (d) F = (A + B + C ) × (A + B + C ) × (A + B + C ) × (A + B + C ) × (A + B + C ) Q9. The logic gates shown in the digital circuit below use X0 strong pull-down nMOS transistors for LOW logic level at the outputs. When the pull-downs are off, high-value resistors set the output logic levels to HIGH (i.e. the pull- X1 ups are weak). Note that some nodes are intentionally X2 shorted to implement “wired logic”. Such shorted nodes Y will be HIGH only if the outputs of all the gates whose X3 outputs are shorted are HIGH. The number of distinct values of X3X2X1X0 (out of the 16 possible values) that give Y = 1 is _______. [GATE 2018/2marks] Q10. Which one of the following gives the simplified sum of products expression for the Boolean function F = m0 + m2 + m3 + m5, where m0, m2, m3 and m5 are minterms corresponding to the inputs A, B and C with A as the MSB and C as the LSB? (a) A B + A B C + A B C

(b)A C + A B + A B C

( c) A C + A B + A B C

(d)A B C + A C + A B C [Set1/GATE 2017/2marks]

Q11. The output of the combinational circuit gien below is A C B Y

(a) A+B+C

(b) A(B+C)

(c) B(C+A)

(d) C(A+B) [Set1/GATE 2016/1mark]

GATE Questions

Mechasoft

03

Q12. The minimum number of 2-input NAND gates required to implement a 2-input XOR gate is (a) 4 (b)5 (c) 6 (d) 7 [Set3/GATE 2016/1mark] Q13. Following is the K-map of a Boolean function of five variables P, Q, R, S and X . The minimum sum-of-product (SOP) expression for function is [Set3/GATE 2016/2marks] PQ PQ 11 10 00 01 RS 11 10 00 01 RS 1 1 0 00 0 0 0 0 00 0 01

1

0

0

1

01

0

0

0

0

11

1

0

0

1

11

0

0

0

0

10

0

0

0

0

10

0

1

1

0

X=0

X=1

(a) P Q S X + P QS X + Q R S X + QR S X

(b)QS X + Q S X

( c) Q S X + Q S X

(d) Q S + Q S

Q14. A 3-input majority gate is defined by the logic function M (a, b, c) = ab + bc + ca. Which one of the following gate is represented by the function M[M(a, b,c), M(a, b,c,),c] ? (a) 3-input NAND gate

(b) 3-input XOR gate

( c) 3-input NOR gate

(d) 3-input XNOR gate [Set1/GATE 2015/2marks]

Q15. All the logic gates shown in the figure have a propagation delay of 20 ns. Let A = C = 0 and B = 1 until time t = 0. At t = 0, all the inputs flip (i.e. A = C = 1 and B = 0) and remain in that state. For t > 0, output Z = 1 for a duration (in ns) of ________________________.

A B

Z

C [Set1/GATE 2015/2marks]

GATE Questions

04

Mechasoft

Q16. The Boolean expression F(X, Y, Z) = XYZ + XYZ + XYZ + XYZ converted into canonical product of sum (POS) form is (a) (X + Y + Z)(X + Y + Z)(X + Y + Z)(X + Y + Z) (b) (X + Y + Z)(X + Y + Z)(X + Y + Z)(X + Y + Z) ( c) (X + Y + Z)(X + Y + Z)(X + Y + Z)(X + Y + Z) (d) (X + Y + Z)(X + Y + Z)(X + Y + Z)(X + Y + Z)

[Set1/ GATE 2015/2marks]

Q17. In the figure shown, the output Y is required to be Y = AB + C D . The gates G1 and G2 must be A G1 B

G2

Y

C D (a) NOR, OR

(b) OR, NAND

( c) NAND, OR

(d) AND, NAND

[Set2/ GATE 2015/1mark]

Q18. A function of Boolean variables, X, Y and Z is expressed in terms of the min-terms as F(X, Y, Z) = S (1, 2, 5, 6, 7) Which one of the product of sums given below is equal to the function F(X, Y, Z)? (a) ( X+ Y + Z)(X + Y + Z)(X + Y+ Z) (b) (X + Y + Z)(X + Y + Z)(X + Y+ Z) (c) (X + Y + Z)(X + Y + Z)(X + Y+ Z)(X + Y + Z)(X + Y + Z) (d) (X + Y + Z)(X + Y + Z)(X + Y+ Z)(X + Y + Z)(X + Y + Z) [Set2/ GATE 2015/2marks]

GATE Questions

Mechasoft

05

Q19. A universal logic gate can implement any Boolean function by connecting sufficient number of them appropriately. Three gates are shown. [Set3/GATE 2015/2marks] F1=X+Y F2=X×Y F3=X+Y X X X Y Y Y Gate 1 Gate 2 Gate 3 Which one of the following statements is TRUE? (a) Gate 1 is a universal gate.

(b) Gate 2 is a universal gate.

(c) Gate 3 is a universal gate.

(d) None of the gates shown is a universal gate.

Q20. The Boolean expression

(a) X

(X + Y)(X + Y )+ (X Y) + X

(b) Y

simplifies to

(c) XY

(d) X+Y [Set1/GATE 2014/1mark]

Q21. The output F in the digital logic circuit shown in the figure is (a) F = XYZ + XYZ XOR X Y (b) F = XYZ + X Y Z AND F ( c) F = X Y Z + XYZ Z (d) F = X Y Z + XYZ

XNOR [Set1/GATE 2014/2marks]

Q22.Consider the Boolean function, F(w, x, y, z) = wy + xy + w x y z + w x y + xz + x y z. Which one of the following is the complete set of essential prime implicants? (a) w, y, xz, xz (b) w, y, xz ( c) y, xyz

(d) y, xz, xz [Set1/GATE 2014/2marks]

GATE Questions

06

Mechasoft

Q23. For an n- variable Boolean function, the maximum number of prime implicants is (a) 2(n - 1) (b) n/2 (c) 2n (d) 2(n-1) [Set2/GATE 2014/1mark] Q24. The number of bytes required to represent the decimal number 1856357 in packed BCD (Binary Coded Decimal) from is_____________________. [Set2/GATE 2014/1mark] Q25. In the circuit shown in the figure, if C = 0, the expression for Y is (a) Y = AB+AB C (b) Y = A + B A ( c) Y = A+B B Y (d) Y = A B A B

[Set4/GATE 2014/1mark]

Q26. A bulb in a staircase has two switches, one switch being at the ground floor and the other one at the first floor. The bulb can be turned ON and can be turned OFF by any one of the switches irrespective of the state of the other switch. The logic of switching of the bulb resembles (a) an AND gate (b) an OR gate ( c) an XOR gate (d) a NAND gate [GATE 2013/1mark] Q27. The output Y of a 2-bit comparator is logic 1 whenever the 2-bit input A is greater than the 2-bit input B. The number of combinations for which the output is logic 1, is (a) 4 (b) 6 (c) 8 (d) 10 [GATE 2012/1mark] Q28. In the sum of products function f (X, Y, Z) = S (2, 3, 4, 5), the prime implicants are (a) X Y, X Y (b) X Y, X Y Z, X Y Z ( c) X Y Z, X Y Z, X Y

(d) X Y Z , X Y Z, X Y Z, X Y Z [GATE 2012/1mark]

Q29.The output Y in the circuit below is always “ 1 ” when P (a) two or more of the inputs P, Q, R are “0” (b) two or more of the inputs P, Q, R are “1” Q (c) any odd number of the inputs P, Q, R are “0” R (d) any odd number of the inputs P, Q, R are “1”

Y [GATE 2011/1mark]

GATE Questions

Mechasoft Q 30.

07

Match the logic gates in Column A with their equivalents in Column B. Column A

Column B

P.

1.

Q.

2.

R.

3.

S.

4.

(a) P-2, Q-4, R-1, S-3 (c) P-2, Q-4, R-3, S-1

(b) P-4, Q-2, R-1, S-3 (d) P-4, Q-2, R-3, S-1 [GATE 2010/1mark]

Q 31. For the output F to be 1 in the logic circuit shown, the input combination should be (a) A = 1, B = 1, C = 0 A B (b) A = 1, B = 0, C = 0 (c) A = 0, B = 1, C = 0 F [GATE 2010/1mark] (d) A = 0, B = 0, C = 1 C

{ (

)}{

}

Q32. If X = 1 in the logic equation é X+Z Y+ Z+XY ù X+Z (X+Y) =1 , then ë û (a) Y = Z (b) Y = Z (c) Z = 1 (d) Z = 0 [GATE 2009/2marks] Statement for Linked Answer Question Q33 & Q34. Two products are sold from a vending machine which has two push buttons P1 and P2. When a button is pressed, the price of the corresponding product is displayed in a 7-segment display. If no buttons are pressed, '0' is displayed, signifying 'Rs.0'.If only P1 is pressed, '2' is displayed, signifying 'Rs.2'.If only P2 is pressed, '5' is displayed, signifying 'Rs.5'. If both P1 and P2 is pressed, 'E' is displayed, signifying 'Error'. [GATE 2009/2marks]

GATE Questions

08

Mechasoft

The names of the segments in the 7-segment display, and the glow of the display for '0', '2', '5', 0 2 5 E a and 'E', are shown below. f e

g b c

d Consider (i)push button pressed/not pressed is equivalent to logic 1/0 respectively. (ii)a segment glowing/not glowing in the display is equivalent to logic 1/0 respectively. Q33. If segments a to g are considered as functions of P1 and P2, then which of the following is correct? (a) g = P1 + P2 , d = c + e (b) g = P1 + P2 ,d = c + e

( c) g = P1 + P2 ,e = b + c (d) g = P1 + P2 , e = b + c Q34. What are the minimum number of NOT gates and 2-input OR gates required to design the logic of the driver for this 7-segment display? (a) 3 NOT and 4 OR (b) 2 NOT and 4 OR ( c) 1 NOT and 3 OR (d) 2 NOT and 3 OR Q35. Which of the following Boolean expressions correctly represents the relation between P, Q, R and M1? [GATE 2008/2marks] P Q X (a) M1 = (P OR Q) XOR R Z M1 (b) M1 = (P AND Q) XOR R Y ( c) M1 = (P NOR Q) XOR R R (d) M1 = (P XOR Q) XOR R Q36. The Boolean function Y = AB + CD is to be realized using only 2-input NAND gates. The minimum number of gates required is (a) 2 (b) 3 (c) 4 (d) 5 [GATE 2007/1mark] Q37. The Boolean expression Y = A B CD + A B CD + AB CD + ABC D can be minimized to (a) Y = A BCD + ABC + ACD (b) Y = A B CD + BCD + AB CD ( c)Y = ABCD + B CD + A B C D

(d) Y = ABCD + B CD + ABC D [GATE 2007/2marks]

GATE Questions

Mechasoft

09

Q38. The number of product terms in the minimized sum-of-product expression obtained through the following K-map is (where, “d” denotes don't care states) (a) 2

(b) 3

(c) 4

(d) 5

1

0

0

1

0

d

0

0

0

0

d

1

1

0

0

1

[GATE 2007/2marks]

Q39. The point P in the following figure is stuck at 1. The output f will be

B

P

A f [GATE 2007/2marks]

C (a) ABC

(b) A

( c) ABC

(d) A

Q40.What is the Boolean expression for the truth table shown below? C A f B (a) B(A + C)(A + C) 0 0 0 0 (b) B(A + C)(A + C) 0 0 1 0 ( c) B(A + C)(A + C) 0 0 0 1 0 1 1 1 (d) B(A + C)(A + C) 0 0 1 0 0 1 1 0 0 1 1 1 0 1 1 1

[GATE 2006/2marks]

[GATE 2005/2marks] Q41.The figure shows the internal schematic of a TTL AND-OR-Invert (AOI) gate. For the inputs shown in the figure, the output Y is A B Y Floating Inputs

(a) 0

(b) 1

(c) AB

(d) AB [GATE 2004/1marks]

GATE Questions

10

Mechasoft

Q42. The Boolean expressionAC + BC is equivalent to (a) AC + BC + AC (b) BC + AC + BC + ACB ( c) AC + BC + BC + ABC

(d) ABC + ABC + ABC + ABC [GATE 2004/2marks]

Q43.A Boolean function f of two variables x and y is defined as follows f(0, 0) = f (0, 1) = f (1, 1) = 1; f (1, 0) = 0. Assuming complements of x and y are not available, a minimum cost solution for realizing f using only 2-input NOR gates and 2-input OR gates (each having unit cost) would have a total cost of (a) 1 unit (b) 4 units (c) 3 units (d) 2 units [GATE 2004/2marks] Q44. The number of distinct Boolean expressions of 4 variables is (a)16 (b) 256 (c) 1023

(d) 65536 [GATE 2003/1mark]

Q45.If the functions W, X, Y and Z are as follows W=R+PQ+RS X=PQRS+PQRS+PQRS Y=RS+PR+PQ+PQ then

Z =R+S+PQ+PQR+PQS

(a) W = Z, X = Z (c) W = Y

(b) W = Z, X = Y (d) W = Y = Z

[GATE 2003/2marks]

Answer Key Q1 Q8 Q15

(b) (c) (40)

Q2 Q9 Q16

(b) Q3 (8) Q10 (a) Q17

Q5 (d) (c) Q4 Q12 (b) Q11 (c) Mechasoft Q19 (b) (a) Q18

(b) (a) (c)

Q6 Q13 Q20

(a) (b) (a)

Q7 Q14 Q21

(c) (b,d) (a)

Q22 Q29 Q36

(d) (b) (b)

Q23 Q30 Q37

(d) Q24 (d) Q31 (d) Q38

Q26 (a) (4) Q25 Q33 (d) (d) Q32 Mechasoft Q40 (d) (a) Q39

(c) (b) (a)

Q27 Q34 Q41

(b) (d) (a)

Q28 Q35 Q42

(a) (d) (d)

Q43

(d)

Q44

(d) Q45

(a)

GATE Solutions

Section2 Q1(b) (1235)x = (3033)y Þ x3 + 2x2 + 3x + 5x0 = 3y3 + 3y + 3y0 or

x3 + 2x2 + 3x + 5 = 3y3 + 3y + 3

and this equation is satisfied for x = 8 and y = 6 Note that (1235)8 = 1 ´ 83 + 2 ´ 82 + 3 ´ 81 + 5 ´ 80 = (669)10 and (3033)6 = 3 ´ 63 + 0 ´ 62 + 3 ´ 61 + 3 ´ 60 = (669)10

Minuend ,

P =

111011 01

2's complement of subtrahend,

Q =

00011010

Q2(b)

Sum

= 1 00000111

EAC ignored Result = 00000111 Q3( c) X and Y in 2's complement 5 -bit format can be represented in 6 -bit format by adding 0 to the left of positive number X and 1 to the left of negative number Y without changing their values, as demonstrated below. X=

001110

Y=

111001

Sum = 1

000111

Þ

Sum = 0 0 0 1 1 1

EAC (ignored)

Q4(d) BCP Code

Number in base 5 system

10 0

010

0 11

0 01

4

2

3

1

Q5(b) 43d = 2B16 and 43d = 0100 0011 in BCD

Q6(a) The range of signed decimal numbers that can be represented by k bits in 1's complement format with one bit reserved for sign is from −(2k−1−1) to + (2k−1−1). For k = 6, the range of signed decimal numbers will be from − 31 to + 31.

Q7(c) 2's complement of 11001,1001and 111001are 00111,0111 and 000111 respectively. Note that all the three 00111, 0111 and 000111 represent decimal 7. So, all three numbers 11001, 1001 and 111001 represent decimal - 7.

GATE Solutions

12

Mechasoft F

Q8( c) F(A, B, C) = ABC+ ABC+ ABC = å m (0, 2, 4) and

å

m

(0, 2, 4) = PM(1,3,5,6,7)

= (A + B+ C)(A + B+ C)(A + B+ C)(A + B+ C)(A + B+ C)

BC

BC

BC

BC

A

1

0

0

1

A

1

0

0

0

Q9. Y2 = (X1 Å X 2 )X 3 Y1 = (X 0 Y2 ).X 0 = 0 and Y = X 3 + Y1 = X 3

For Y1 to be '1', the input X0 to the inverter and X 0 (output of inverter) both must be '1' which is never possible. Thus Y = 1 only if X3 = 1, that is, Y = X3 and the number of distinct values of X3X2X1X0 that gives Y = 1 is 8. Q10(b) Boolean function, F(A,B,C) = m0 + m2 + m3 + m5 = A B C + A B C + A B C + A B C F BC BC A A

BC

BC

BC

1

1

1

Þ F = AC + AB + ABC

1

A

Q11( c) The output, Y=B(C+A) as demonstrated below. AB

A

ABC

Y = ABC Å AB Å BC

C B

BC

AB Å BC

Since, X-OR function is distributive Y = [AB(C Å 1)] Å BC = ABC Å BC = B(AC Å C) = B(ACC + ACC) = B[(A + C) C+ AC] = B(AC+ C+ A C) = B[C(A + 1) + A C] = B(C+ A C) = B(C + A)

GATE Solutions

Mechasoft

13

Q12(a) A 2 -input XOR gate can be implemented using 4NAND gates as demonstrated below. X.XY = X + XY = X + Y

X

F = (X + Y)(X + Y) = (X + Y) + (X + Y) = XY + XY = X Å Y

Y

XY Y = XY + Y = X + Y

X=1

Q13(b) X=0

PQ

PQ

PQ

RS

0

1

1

0

1

RS

0

0

0

0

0

1

RS

0

0

0

0

0

0

RS

0

1

1

0

PQ

PQ

PQ

RS

0

0

0

0

RS

1

0

0

RS

1

0

RS

0

0

PQ

XSQ

PQ

XSQ

Sum of product exp ression is QSX + QSX

Q14 (b) The logic function M(a, b, c) = ab + bc + ca =Σ (3,5, 6, 7) and let x1 = M(a, b, c) = å (0,1, 2, 4) = a b c + a b c + a b c + a b c as demonstrated below. M

bc

bc

bc 1

a a

1

5

1

M

bc 3

7

1

6

Let x 2 = M(a, b, c) = ab + bc + ac = å (2, 4, 6, 7)

bc

a

1

a

1

x2

bc 0

bc 1

1

bc

bc

bc 1

a a

1

2

4

bc

= a bc + a bc + a bc + a bc

1

bc

4

1

7

1

2

6

GATE Solutions

14

Mechasoft

M é(M (a, b,c) , M(a, b,c),c) ù = M (x1 , x 2 ,c ) = x1x 2 + x 2c + x1c ë û x1x 2 = éå ë (0,1, 2, 4)ùû éå ë (2, 4,6,7)ùû = å (2, 4) = a b c + a b c ; intersection x 2c = (a b c + a b c + a b c + abc)c = abc = å (7) x1c = (a b c + a b c + a b c + a b c)c = a b c = å (1) M éë(M(a, b,c), M(a, b,c),c) ùû = å (2, 4) + å (7) + å (1) ; union = å (1, 2, 4,7) = a b c + a b c + a b c + abc = a(b c + bc) + a(b c + bc) = a(b Å c) + a(b Å c) = a Å b Å c represents 3 - input XOR gate Note that an XOR expression is equal to an XNOR expression when both have the same odd number of variables. However, they form the complements of each other when the number of variables is even. For example, A Å B Å C = A e B e C, (A Å B Å C) = A Å B e C,

(A e B e C) = A e B Å C but (A Å B Å C Å D) = A e B e C e D In this sense , option (d) is also correct. Q15. At t = 0, when all the inputs flip from A = C =1 and B = 0 to A = C =0 and B = 1 , the output Z = 1 for a duration of 40 ns for t > 0 as demonstrated below with the help of waveforms.

A B

X

Z

A

1 0

B

1 0

B

1 0

C

1 0

X = AB

1 0

Z = XÅC

1 0

C

0

20

40 60 80 Z=1 for 40ns

t(ns)

GATE Solutions

Mechasoft Q16(a) The K map for

15

F(X, Y, Z) = X Y Z + X Y Z + X Y Z + X Y Z

is constructed below. F

YZ

YZ

YZ

YZ

X

0

0

0

1

X

1

0

1

1

Collect the sum terms (corresponding to '0' entries in the map) to get F (X, Y, Z) in canonical POS form as F(X, Y, Z) = (X + Y + Z)(X + Y + Z) (X + Y + Z) (X + Y + Z)

Q17 (a) The output of NOR gate is X1 = C + D = C D . The term C D appears in plus form at output Y. The gate G2 must be OR gate. Another input to G2 (OR gate) must be AB. The gate G1 must be NOR gate to produce output equal to AB for inputs A and B. G1

Note that A + B = AB.

G2

A B

A + B = AB Y = AB + C D

C D

X1 = C + D = C D

Q18(b) The K map for F(X, Y, Z) = X Y Z + X Y Z + X Y Z + X Y Z is constructed below.

F

YZ

YZ

YZ

YZ

X

0

0

0

1

X

1

0

1

1

Collect the sum terms (corresponding to '0' entries in the map) to get F (X, Y, Z) in canonical POS form as F(X, Y, Z) = (X + Y + Z)(X + Y + Z) (X + Y + Z) (X + Y + Z)

GATE Solutions

16

Mechasoft

Q19( c) Gate3 is a universal gate in the sense that all the three basic operations AND, OR and NOT are implement-able using only gate 3 as demonstrated below. X (I) NOT :

X

F

≡

X (ii) AND :

F

≡

F=X+0=X Y=0

Y

X

F = X + Y = XY

Y X X

X

F

(iii) OR :

X

≡

Y

F=X+Y=X+Y

Y

Q20(a) (X + Y)(X + Y) + (XY) + X = X.X + XY + XY + YY + (XY)X = X + XY + XY + (X + Y)X = X éë1+ Y + Y ùû + XX + XY = X + XY = X(1+ Y) = X

Q21 (a) F1 = XY + XY = X Å Y and F1 = X Y + X Y F2 = F1 Z + F1Z = (X Å Y) Z + (X Å Y)Z = (X Y + XY)Z + (XY + XY)Z = X Y Z + XYZ + XYZ + XYZ F = F1.F2 = (X Y + X Y)(X Y Z + XYZ + XYZ + XYZ) = X YX Y Z + X Y X Y Z + X YX Y Z + X Y X Y Z + X Y X Y Z + X Y X YZ + XY X Y Z + X Y X Y Z = X YZ + X Y Z

F1

X Y

F = F1F2 Z F2

GATE Solutions

Mechasoft

17

Q22(d) Complete set of essential prime implicants, can be determined by constructing K map as demonstrated below. Entry of '1' is made in the blocks labeled by product terms wy , xy, w xyz, w x y, x z and x y z F yz yz yz yz wx

1

1

1

wx

1

1

1

wx

1

1

1

1

1

F = y + xz + x z

and essential prime implicants are y, xz and x z.

wx

1

Q23 (d) For n variable Boolean function, the maximum number of prime implicants =

2n = 2n –1. 2

As demonstrated below using K map for n = 2, 3 and 4, it is apparent that the number of prime implicants will be maximum when adjacent 0 and 1 appear in the map. 1

0

1

0

0

1

0

1

0

1

1

0

1

0

1

0

1

0

1

0

0

1

0

1

0

1

0

1

Map for n = 2 Maximum number = 2 2 +1 = 2 of prime implicants

3

4

2 3 +1 = 4

2 4 +1 = 8

Q24. Each decimal number requires four binary digits to be represented in BCD form. (1856357)decimal = ( 0001 1000 0101 0110 0011 0101 0111)BCD The numbers of bytes required to represent 28 bits = 4 Q25 (a) If C = 0, Y = AB + AB as demonstrated below. C=0 Y A B

A+B

A +B = A B

1

0

Y = 1.(AB + A B) = 0 + (AB + A B) = (A + B)(A + B) = AB + AB

A B

AB AB + A B

GATE Solutions

18 Q26( c)

on / off (1 / 0) on / off (1 / 0)

Mechasoft

first floor switch (s1) R

LED on / off ≡ 1 / 0 ground floor switch (s2)

Let s1 be in 1 (on) state. LED will turn on for s2 = 0(off) and will turn off for s2 =1(on). Let s1 be in 0 (off) state. LED will turn on for s2 = 1(on) and will turn off for s2 = 0(off). Switching of this particular nature resembles an XOR logic. Q27(b) Input A A1 A0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1

Input B B1 B0 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1

Output Y 0 0 0 0 1 * (1) 0 0 0 1*(2) 1*(3) 0 0 1*(4) 1*(5) 1*(6) 0

Number of combinations for which output(Y) is logic 1, is equal to 6.

GATE Solutions

Mechasoft

19

f

Q28 (a)

YZ

YZ

X X

1

YZ

YZ

1

1

1

f (X, Y, Z) = X Y + X Y and prime implicants are X Y , X Y.

Q29.

PQ

P

PQ . QR

PQ . QR

Q QR

Y = PQ . QR . PR = PQ + QR + PR

R PR

Y= PQ + QR + PR is a majority function which is also carry output of Full Adder. Y = 1 when two or more of inputs P, Q, R are '1'. Q30 (d) (1)

a b

y = a b + a (b) = a b + ab

≡

a

S.

y

b

(2)

a b

y = a +b = a b

≡

a Q. b

(3)

a b

y = (a) b + a b = ab + a b = a b + a b

≡

R. b

y

y = a .b = a + b

≡

P.

a b

y

a

(4) b

a

Q31 (d) The Boolean variable C must be 1while A and B can assume any value (0/1). F = C Å (A Å B) Å (A Å B) = C Å 1 = C = C Note X Å X = 1

y

GATE Solutions

20

Mechasoft

Q32 (d) For X = 1 éX + Z ë

{Y + (Z + X Y )}ùû {X + Z ( X + Y )}= [1 ] {0 + Z (1+ Y)} = Z

and therefore , Z = 0 will satisfy the logic equation. Q33(b) P1 P2 a b c d e f 0 0 1 1 1 1 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 1 0 0 1 1 1 Simplify the truth table to get a = 1 ; b = P2 ; c = P1 ; d = 1 ; e = P1 + P2 ; f = P1 + P2 and g = P1 + P2

g 0 1 1 1

Also c + e = P1 + P1 + P2 = 1+ P2 = 1 Þ d = c + e

Q34 (d) The hardware design requires minimum number of two NOT gates and three 2- input OR gates as demonstrated below. P1

1

P2 P1 P2

a b c d e f g

Q35 (d) M1 = R Å Z = R Å XY = R Å

{ PQ (P + Q} = R Å éë(P + Q)(P + Q)ùû

= R Å (P Q + P Q )= R Å (P Å Q) = (P XOR Q) XOR R

GATE Solutions

Mechasoft Q36 (b)

21

A B

Y = A B + C D = AB CD

Y C D

Q37 (d) Z

CD

CD

CD

CD

1

AB

1

AB

Y = BC D + A BC D + A BC D 1

AB

1

AB

Q38(a)

1

1 d d

There are two loops (one pair and one quad) in the map and therefore there are two product terms.

1 1

Q39(d) The output f = A as demonstrated below. Note that any low input to NAND gate, forces its output to go high. A P =1

f =A 0

A 1

GATE Solutions

22

Q40(a) For given truth table, K map is constructed below.

Mechasoft f

BC 0 A

f = A C+B+AC f = B (A + C) (A + C)

A

0

BC

BC

BC

0

1

0

0

0

1

Q41 (a) Y = A B +1 = 1 = 0. The floating inputs in TTL family are treated as logic 1(high). However, in practice no input is kept floating due to risk of noise pick up. Unused inputs are advised to be connected to VCC to avoid such a risk. Q42(d) AC + BC = AC(B + B) + BC(A + A) = A BC + A BC + A BC + A BC Q43 (d) Collect all min terms to get

x

x

f(x, y) = x y + x y + xy

y

f

= x(y + y) + xy = x + xy = x + y

2 units Q44 (d)With four variables as inputs, the truth table has 16 rows. Corresponding to each row, the output variables may be assigned a value 0/1. So, 216 distinct truth tables may beconstructed. In n general, number of distinct functions with n variables = 2(2 ) . For n = 4, Number of distinct 4 functions will be 2(2 ) = 216 = 65536. Q45(a) W = R + R S + P Q = R + S + P Q X = P Q R S + P Q R S + P Q R S = R S[P Q + P Q + P Q] = R S[PQ + Q (P + P)] = R S(P + Q) Y = RS + P R + PQ + P Q = R S + P R + Q = RS + (P + R) Q = R S + PQ + Q R Z = R +S+ PQ + P Q R + P Q S = R +S+ PQ P Q R P Q S = R + S +[(P + Q)(P + Q + R)(P + Q + S)] = R + S + éë(P Q + P R + P Q + Q R) (P + Q + S) ùû = R + S +[P Q + P Q S + P R + P Q R + P R S + P Q S + P Q R + Q R S] = R + S + [P Q(1+ S) + P R(1+ Q + S + Q) + P Q S + Q R S] = R +S+ P Q + P R + P Q S+Q R S = R[1+ P + Q S] + S [1+ P Q] + P Q = R + S + P Q

Correlate expressions for W, X, Y and Z to get W = Z and X = Z

2

Chapter

Arithmetic Circuits and Code Converters Multiplexer ,Decoder ,PLA and ROM

Section1

GATE Questions

Q1. Addressing of a 32k ×16 memory is realized using a single decoder .The minimum number of AND gates required for the decoder is (a) 28

(b) 232

(c) 215

(d) 219

[GATE 2021/1mark] Q2.The propagation delays of the XOR gate , AND gate and multiplexer (MUX) in the circuit shown in the figure are 4ns, 2ns and 1ns respectively. P

0

Q R S T

MUX

0 MUX 1 S0

1

Y

S0

If all the inputs P,Q,R,S and T are applied simultaneously and held constant , the maximum propagation delay of the circuit is (a) 3ns

(b) 5ns

(c ) 6ns

(d) 7ns

[GATE 2021/2marks]

GATE Questions

24

Mechasoft

Q3. The figure below, shows a multiplexer where S1 and S0 are the select lines , I0 to I3 are the input data lines , EN is the enable line , and F (P,Q,R) is the output . F is (a) PQ + QR

(b) P + QR

( c) PQR + P Q

(d) Q + PR

EN I0 I1 I2 I3 S1 S0

0 R 0 R 1

F

P Q

[GATE 2020/1mark] Q4. A four -variable Boolean function is realized using 4×1 multiplexers as shown in the figure. The minimized expression for F(U,V,W,X) is F(U,V,W,X) I0 I0 (a) (UV + U V ) W 4×1 4×1 (b) (U V

VCC

+ U V )(W X + W X )

( c) (UV + U V ) W (d) (U V

+ U V )(W X + W X )

I1 MUX

I1 MUX

I2 I3 S1 S0

I2 I3 S1 S0

U V

W X

Q5. A 2 × 2 ROM array is built with the help of diodes as shown in the circuit below. Here W0 and W1 are signals that select the word lines and B0 and B1 are signals that are output of the sense amps based on the stored data corresponding to the bit lines during the read operation. B0 B1 W0 é D 00 W1 êë D10

D 01 ù D11 úû

[GATE 2018/2marks] B0 B1 Sense amps W0

W1 VDD

Bits stored in the ROM Array During the read operation, the selected word line goes high and the other word line is in a high impedance state. As per the implementation shown in the circuit diagram above, what are the bits corresponding to Dij (where i = 0 or 1 and j = 0 or 1) stored in the ROM? é1 0 ù

(a) ê ú ë0 1 û

é0 1 ù

(b) ê ú ë1 0 û

( c)

é1 0 ù ê1 0 ú ë û

(d)

é1 1 ù ê0 0 ú ë û

[GATE 2018/2marks]

GATE Questions

Mechasoft

25

Y Q6. Consider the circuit shown in the figure. The Boolean expression F implemented by the circuit is (a) X Y Z + X Y + Y Z (b) X Y Z + X Z + Y Z ( c) X Y Z + X Y + Y Z (d) X Y Z + X Z + Y Z

0 0 MUX

MUX

1

0

F

1 X

Q7. A programmable logic array (PLA) is shown in the figure. The Boolean function F implemented is P P Q Q (a) P Q R + P Q R + P Q R × × (b)(P + Q + R) (P + Q + R) (P + Q + R) × × ( c) P Q R + P Q R + P Q R × × (d)(P + Q + R) (P + Q + R) (P + Q + R)

Z [Set1/GATE 2017/1mark]

R R × F

× ×

P Q [Set2/GATE 2017/2marks]

R Q8. The functionality implemented by the circuit below is (a) 2-to-1 multiplexer (b) 4-to-1 multiplexer (c) 7-to-1 multiplexer (d) 6-to-1 multiplexer

Q P R S C1 C0

is a tristable buffer

3:8 Decoder

Y

O0 O1 O2 O3

Enable=1

[Set1/GATE 2016/2marks] Q9. A 4:1 multiplexer is to be used for generating the output carry of a full adder. A and B are the bits to be added while Cin is the input carry and Cout is the output carry. A and B are to be used as the selected bits with A being the more significant select bit.

I0 I1 I2 I3

4:1 MUX

Which one of the following statements correctly describes the choice of signals to be connected to the inputs I0 , I1 , I2 and I3, so that the output is Cout?

A B

S1 S0

Cout

GATE Questions

26 (a) I0= 0 , I1=Cin , I2= Cin and I3=1 ( c) I0= Cin , I1=0 , I2=1 and I3= Cin

Mechasoft

(b) I0=1 , I1= Cin , I2 = Cin and I3=1 (d) I0= 0 , I1= Cin , I2=1 and I3= Cin

[Set2/GATE 2016/1mark] Q10. For the circuit shown below in the figure , the delays of NOR gates, multiplexers and inverters are 2 ns, 1.5ns and 1ns ,respectively .If all the inputs P, Q, R, S and T are applied at the same time instant , the maximum propagation delay (in ns) of the circuit is ________________.

P Q R S

0

0

MUX 1

MUX 1 S

S0

Y

0

T [Set3/GATE 2016/2marks] Q11. A 1-to-8 demultiplexer with data input Din, address inputs S0, S1, S2 (with S0 as the LSB) and Y0 to Y7 as the eight multiplexed outputs, is to be designed using two 2-to-4 decoders (with enable input E and address inputs A0 and A1) as shown in the figure. Din, S0, S1 and S2 are to be connected to P, Q, R and S, but not necessarily in this order. The respective input connections to P, Q, R and S terminals should be

P

1E

Q (a) S2, Din, S0, S1

2 to 4 decoder

1A0

R S

(b) S1, Din, S0, S2

1A1

1Y0 1Y1 1Y2 1Y3

Y0

2Y0 2Y1 2Y2 2Y3

Y4

Y1 Y2 Y3

( c) Din, S0, S1, S2 2E

(d) Din, S2, S0, S

2 to 4 decoder

2A0 2A1

Y5 Y6 Y7

[Set2/GATE 2015/2marks] Q12. The outputs of the two flip-flops Q1, Q2 in the figure shown are initialized to 0, 0. The sequence generated at Q1 upon application of clock signal is (a) 01110… (b) 01010… ( c) 00110… (d) 01100…

Q1 J1

Q1

K1 Q1 CLK

J2

Q2

K 2 Q2

[Set2/GATE 2014/2marks]

GATE Questions

Mechasoft

27

Q13. Consider the multiplexer based logic circuit shown in the figure. W

0 MUX

0

1

MUX

F

1 S1 S2

Which one of the following Boolean functions is realized by the circuit? (a) F = WS1 S2 (b) F = WS1 + WS2 + S1 S2 ( c) F = W + S1 + S2 (d) F = W Å S1 Å S2 [Set3/GATE 2014/1mark] Q14. In the circuit shown, W and Y are MSBs of the control inputs. The output F is given by 4 : 1 MUX 4 : 1 MUX I0 I0 (a) F = W X + W X + Y Z I1 I1 (b) F = W X + W X + Y Z F Q Q VCC I2 I2 ( c) F = W X Y + W X Y I3 I3 (d) F = W + X Y Z

(

)

W

Y Z [Set3/GATE 2014/2marks] Q15. If X and Y are inputs and the Difference (D = X – Y) and the Borrow (B) are the outputs, which one of the following diagrams implements a half-subtractor? (a)

Y

X Y

I0 2 : 1 I1 Mux S S I0 2 : 1 I1 Mux

( c)

Y

X Y

I0 2 : 1 I1 Mux S S I0 2 : 1 I1 Mux

D

(b) X

Y X B

B

I0 2 : 1 I1 Mux S S I0 2 : 1 I1 Mux

(d)

X

Y X D

X

I0 2 : 1 I1 Mux S S I0 2 : 1 I1 Mux

D

B

B

D

[Set3/GATE 2014/2marks]

GATE Questions

28

Mechasoft

Q16. An 8 to 1 multiplexer is used to implement a logical function Y as shown in the figure. The output Y is given by I0 0 I1 D I2 0 8´1 (a) Y = ABC + AC D I3 D MUX Y I4 0 I5 0 (b) Y = ABC + ABD I6 1 I7 S2 S1 S0 0 ( c) Y = ABC + ACD A B C (d) Y = ABD + ABC [Set4/GATE 2014/2marks] Q17. The logic function implemented by the circuit below is (ground implies a logic “0”) 4 ´ 1 MUX I0 (a) F = AND (P, Q) I1 (b) F = OR (P, Q) Y F I2 ( c)F = XNOR (P, Q) I3 S S 1 0 (d) F = XOR (P, Q) [GATE 2011/1mark] P Q Q18. The Boolean function realized by the logic circuit shown is (a) F = Σm(0, 1, 3, 5, 9, 10, 14) (b) F = Σm(2, 3, 5, 7, 8, 12, 13) (c) F = Σm(1, 2, 4, 5, 11, 14, 15) (d) F = Σm(2, 3, 5, 7, 8, 9, 12)

C D

I0 I1 4 ´ 1 I2 MUX Y I3

F(A, B, C, D)

S1 S0 AB

[ GATE 2010/2marks] Q19.What are the minimum number of 2-to-1 multiplexers required to generate a 2-input AND gate and a 2-input Ex-OR gate ? (a) 1 and 2 (b) 1 and 3 (c) 1 and 1 (d) 2 and 2 [ GATE 2009/2marks]

GATE Questions

Mechasoft

29

Q20. In the circuit shown, I0 - I3 are inputs to the 4 : 1 multiplexer. R(MSB) and S are control bits. The output Z can be represented by I3 P (a) PQ + P Q S + Q R S

P Q

I2 P

(b) PQ + P Q R + P Q S P Q

( c) P Q R + P Q R + P Q R S + Q R S (d) P Q R + P Q R S + P Q R S + Q R S

4:1 MUX

I1 I0 S 1

S0

R

S

Z

[GATE 2008/2 marks] Q21.In the following circuit, X is given by (a) X = A B C + A B C + A B C + A B C (b) X = A B C + A B C + A B C (c) X = AB+BC+AC

0 1

I0

1

I2

0

I3 S

4 to1 MUX Y

I1

1

S0

A

B

0 1

I0

1

I2

0

I3 S

4 to 1 I 1 MUX

1

Y

X

S0 C

(d) X = A B + B C + A C [GATE 2007/2marks] Q22. The Boolean function f implemented in figure using two input multiplexers is (a) ABC + ABC

C

0

0

1

A

0 f

(b) ABC + AB C ( c) ABC + ABC

C

B

1 E

[GATE 2005/1mark] (d) ABC + ABC Q23.The minimum number of 2 to 1 multiplexers required to realize a 4 to 1 multiplexer is (a) 1 (b) 2 (c) 3 (d) 4 [GATE 2004/2marks]

GATE Questions

30

Mechasoft

Q24.Without any additional circuitry, an 8 : 1 MUX can be used to obtain (a) some but not all Boolean functions of 3 variables. (b) all functions of 3 variables but none of 4 variables. (c) all functions of 3 variables and some but not all of 4 variables. (d) all functions of 4 variables. [GATE 2003/1mark] Q25. Figure I shows a 4-bits ripple carry adder realized using full adders and Figure II shows the circuit of a full-adder (FA). The propagation delay of the XOR, AND and OR gates in Figure II are 20 ns, 15 ns and 10 ns respectively. Assume all the inputs to the 4-bit adder are initially reset to 0. Xn Y3 X3

Y2 X2

Y1 X1

Y0 X0

Sn

Yn Z4

FA

Z3

Z2

FA

S3

S2

Z1

FA

S1

FA

Z0

Zn – 1

S0

Zn

At t = 0, the inputs to the 4-bit adder are changed to X3X2X1X0 = 1100, Y3Y2Y1Y0 = 0100 and Z0 = 1. The output of the ripple carry adder will be stable at t (in ns) = ___________ [Set2/GATE 2017/2marks] Q26. Identify the circuit below.

X1

(c) Gray to Binary converter X0 (d) XS 3 to Binary converter

O P0 O P1 O P2 O P3 O P4 O P5 O P6 O P7

I P0 I P1 I P2 I P3 I P4 I P5 I P6 I P7

Y2 8:3 Encoder

(b) Binary to Xs3 converter

3:8 Decoder

(a) Binary to gray code converter X2

Y1 Y0

[Set1/GATE 2016/2marks] Q27. A 16-bit ripple carry adder is realized using 16 identical full adders (FA) as shown in the figure. The carry-propagation delay of each FA is 12 ns and the sum-propagation delay of each FA is 15 ns. The worst case delay (in ns) of this 16-bit adder will be ____________. A0

B0

FA0 S0

A1 C0

B1

FA1 S1

A14 B14 C1

FA14 S14

C14

A15 B15 FA15 S15

C15

[Set4/GATE 2014/2mark]

GATE Questions

Mechasoft

31

Q28. A digital system is required to amplify a binary-encoded audio signal. The user should be able to control the gain of the amplifier from a minimum to a maximum in 100 increments. The minimum number of bits required to encode, in straight binary, is (a) 8 (b) 6 (c) 5 (d) 7 [GATE 2004/1mark] Q29.The circuit shown in figure has 4 boxes each described by inputs P, Q, R and outputs Y, Z withY = P Å Q Å R and Z = RQ + PR + QP Q

P P Q R Z Y

P Q R Z Y

P Q Z Y R

P Q R Z Y

Output

The circuit acts as a (a) 4 bit adder giving P + Q (c) 4 bit substracter giving Q – P

(b) 4 bit substracter giving P − Q (d) 4 bit adder giving P + Q + R

Q30.The circuit shown in figure converts (a) BCD to binary code (b) Binary to excess - 3 code (c) Excess - 3 to Gray code (d) Gray to Binary code

[GATE 2003/2marks]

INPUTS

MSB

+

+

+

MSB OUTPUTS

[GATE 2003/2marks]

Answer Key

Q1 Q8 Q15

( c) (b) (a)

Q2 Q9 Q16

( c) (a) (c)

Q3 Q10 Q17

Q22

(a)

Q23

(c)

Q24

Q29

(b)

Q30

(d)

Q5 (c) (a) Q4 Q12 (6) Q11 (d) Mechasoft Q19 (d) Q18 (d)

(a) (d) (a)

Q6   (b) Q13 (d) Q20 (a)

Q7 Q14 Q21

(c) (c) (a)

Q26

(a)

Q27 (195)

Q28

(d)

(c) Q25

(50)

Mechasoft

“Engineering education of the student is incomplete if he never had an opportunity to solve a problem invented by himself .”

GATE Solutions

Section2

Q1( c) The memory of size 32k×16, has 32k =25×210=215 locations and 16-bit word can be stored at each location. This will require 15 address lines. In order to realize the memory with 15 address lines using a single decoder, the minimum number of AND gates required for decoder will be 215. P Q2( c) For T=0 , the signal flow path as demonstrated below , gives the propagation delay =2+1=3ns.

signal flow path for T=0 0

2ns

1ns

Q

Y

0 1

R

S0

1 S0

S T

signal flow path T=1

P

0

Q For T=1 , the signal flow path as demonstrated below , gives the propagation delay =2+1+2+1=6ns. The maximum propagation delay = 6ns

1ns

0 R S T

1ns 2ns

1 S0

2ns

1

S0

Y

GATE Solutions

Mechasoft

33

Q3(a) F = S1 S0 .I0 + S1 S0 .I1 + S1 S0 .I2 + S1S0 I3 = P Q R + P Q.0 + P Q R + PQ.1

(

)

= P Q R + PQ R + PQ = P + P Q R + PQ = QR + PQ

Q4( c) 0

F1

I0

4×1 I1 MUX #1 I2 I3 S1 S0

1 1 0

I0

4×1 F(U,V,W,X) I1 MUX #2 I2 I3 S1 S0

0 0

U V W X MUX#1: F1 = S1S0 I0 + S1S0 I1 + S 1S0 I 2 + S 1S0 I3 = UV.0 + UV.1 + UV.1 + UV.0 = U V + UV MUX# 2 : F(U, V, W, X) = S1S0 I0 + S1S0 I1 + S1S0 I 2 + S1S0 I3 = WX.F1 + WX.F1 + WX.0 + WX.0 = W F1 (X + X) = W F1 = W(UV + UV)

Q5(a) For W0 = 1, B0B1 =10 and for W1 = 1, B0B1 =01

B0 W0 é D00 W1 êë D10

B1 D01 ù é1 0 ù = D11 úû êë0 1 úû

Bit lines B0 B1 Sense amps W0

10 word lines

W1

01

VDD

Q6(b) Y

0

0

1

XY 2×1 Mux X

0 1

2×1 Mux

F = Z(X Y) + Z(X Y) = ZXY + Z(X + Y)

Z

= XYΖ + XΖ + YΖ

diode → bit '1' No diode → bit '0'

GATE Solutions

34 Q7.

P P Q Q

Mechasoft

R R

× ×× ×× × × ××

F = PQR + PQR + PQR

P

Q

R Q8(b) The functionality implemented by the circuit is 4 to 1 multiplexer as demonstrated below . Decoder outputs inputs C1 C0 O0 O1 O2 0 0 1 1

0 1 0 1

1 0 0 0

0 1 0 0

0 0 1 0

O3

circuit output Y

0 0 0 1

P Þ

P Q R S

Q

I0 4×1 I MUX

R S

I2 I3 S1 S0

1

Y

C0 C1

Q9(a) The truth table of a full adder and the program table for multiplexer to design full adder is demonstrated below. Decimal A d 0 1 2 3 4 5 6 7

0 0 0 0 1 1 1 1

inputs B Cin

outputs S Cout

0 0 1 1 0 0 1 1

0 1 1 0 1 0 0 1

0 1 0 1 0 1 0 1

0 0 0 1 0 1 1 1

Cout = å (3,5,6,7)

GATE Solutions

Mechasoft

35

Cout = å (3,5,6,7) = ABCin + ABCin + ABCin + ABCin

0

= ABCin + ABCin + AB.1 Compare the expression for Cout with that of general expression for 4 ´ 1 MUX, Y = S1S0 I0 + S1S0 I1 + S1S0 I2 + S1S0 I3 = A BI0 + A BI1 + ABI2 + ABI3

Cin

I0 4×1 I MUX

Cin 1

I2 I3 S1 S0

1

to get I0 = 0,I1 = 12 = Cin and I3 = 1

Y

A B

Q10. For T =0, the input Q and R flow through NOR gate , MUX1 and MUX2. Propagation delay =2+1.5+1.5=5ns 2ns Q R

MUX1 1.5ns 0

MUX2 1.5ns 0

1

1

NOR

Y S0

S0 T=0

For T = 1, the inputs P and S flow through inverter, MUX1 ,NOR gate and MUX2.Propagation delay =1+1.5+2+1.5= 6ns . MUX2 MUX1 Thus, the maximum propagation 2ns 1.5ns 1.5ns delay of the circuit is 6ns . P 0 0

1ns

NOR

1

S

Y

1 S0

S0 T=1

Q11 (d) A 3 line to 8 line decoder can be programmed for use as 1 line to 8 line de-multiplexer with binary inputs to decoder serving as SELECT inputs of de-multiplexer and ENABLE input to decoder serving as DATA input (Din) of de-multiplexer as demonstrated below. P Q

Y0 Y0

1E

R

1A0

S

1A1

2 to 4 decoder

1´8 DE MUX

Y1

Y2

Y2 Y3

Y1

P

Y3

Din

Y4

2A0 2A1

Y5

Y4

2E 2 to 4 decoder

Y6

Y5 Y6

S2 S1

S0

Q

R

Y7 S

Y7

GATE Solutions

36

Mechasoft

Function table of decoder P Q S R 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0

0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0

0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0

Active low output Y0 Y1 Y2 Y3

upper decoder is enabled and lower decoder is disabled

Y4 Y5 Y6 Y7

lower decoder is enabled and upper decoder is disabled

For P = 0 and Q = 0 , upper 2 ´ 4 decoder is selected. For P=0 and Q = 1, lower 2 ´ 4 decoder is selected.

For P = 1, both decoders both decoders are disabled. All outputs are disabled regardless of whether Q=0 or Q=1. will be in inactive HIGH state.

The decoder operation as discussed above, the input P acts as ENABLE and Q, S, R act as inputs to decoder with Q as MSB and R as LSB. The input connections to P,Q,R and S terminals should be Din, S2, S0, S1of demultiplexer respectively. Q12 (d) State transition table PS ≡ Pr esent State

PS Q1

NS ≡ Next State FF

Q 2 J1 = Q2

Inputs

NS +

K1 = Q2 J 2 = Q1 K 2 = Q1 Q1

Q+2

0

0

1

0

0

1

1

0

1

0

1

0

1

0

1

1

1

1

0

1

1

0

0

1

0

1

0

1

0

1

0

0

GATE Solutions

Mechasoft State Diagram

00

37

10 Q1 Q2

01

11

It is apparent from state table and state diagram that the sequence generated at Q1 upon application of clock signal, will be 01100…. Q13 (d) F1 W 0 F1 = S1 W + S1 W = W Å S1 MUX 0 F 1 MUX F2 = S2 F1 + S2 F1 1 = S2 (W Å S1 ) + S2 (W Å S1 ) = W Å S1 Å S2 S1 S2 Q14 ( c)

VCC

4 to 1 MUX

4 to1 MUX

I0

I0 I1

I1 Q I2 I3 S1 S0 W X

F

I2 I3 S1 S0 Y Z

Q = S1 S0 I0 + S1 S0 I1 + S1 S0 I 2 + S1 S0 I3 = W X.0 + W X.1+ W X.1+ W X.0 = W X + W X F = S1 S0 I0 + S1 S0 I1 + S1 S0 I 2 + S1 S0 I3 = Y ZQ + Y ZQ + Y Z.0 + Y Z.0 = Y Q (Z + Z) = Y Q = Y(W X + W X) = W X Y + W X Y

Q15(a) The two outputs of a half subtractor, the difference D = X – Y and the borrow B, are described by Boolean functions D = X Å Y = X Y + X Y and B = X Y . The implementation of these Boolean functions using 2 ´ 1 MUX is demonstrated below. 2 ×1 MUX I0 I1

F S

F = S I0 +SI1

GATE Solutions

38

Mechasoft

Connecting input X of half subtractor to select line S of 2 ´ 1 MUX and comparing F with D, it is observed that I0 = Y and I1 = Y. Again, preserving the connection of input X of half subtractor to select line S of 2 ´ 1 MUX and comparing F with Borrow B, it is observed that I0 = Y and I1 = 0. With these observations, the complete circuit is shown below. Using the steps demonstrated just above, a half subtractor may also be implemented by connecting input Y of half subtractor to select line S of MUX as shown below. 2 ´ 1 MUX

2 ´ 1 MUX Y

I0

I0

X F

D

I1 S

F

B

Y

S I0

D

S

X Y

F I1

F

B

I0 S

I1 2 ´ 1 MUX

I1 2 ´ 1 MUX

Q16 ( c)

Y = S2 S1 S0 I0 + S2 S1 S0 I1 + S2 S1 S0 I 2 + S2 S1S0 I3 + S2 S1 S0 I 4 + S2 S1 S0 I5 + S2S1S0 I6 + S2S1S0 I7

= A BC.0 + A BC D + A BC.0 + A BC D + ABC.0 + A B C.0 + A BC.1+ ABC.0 = A B CD + A BCD + ABC = A C D (B + B) + ABC = A C D + ABC

Q17 (d)

I0 = 0 = 0, I1 = I 2 = 0 = 1 and I3 = 0 F = Y = S1 S0 I0 + S1 S0 I1 + S1 S0 I 2 + S1S0 I3 = P Q.0 + P Q.1+ P Q.1+ PQ.0 = P Q + P Q = XOR(P,Q)

Q18(d)I0=C,I2=D,I2= C and I3 = C D F(A, B,C, D) = S1 S0 I0 + S1 S0 I1 + S1S0 I 2 + S1S0 I3 = A BC + A BD + ABC + A BC D = A BC D + A BC D + A BC D + A BC D + ABC D + A B C D + A BC D = Σ (2, 3, 5, 7, 8, 9, 12)

GATE Solutions

Mechasoft Q19 (a)

0 b

f1 = S0 I0 + S0 I1 = ab + a.0 = ab

2 to1 I0 MUX I1

39

2 to 1 MUX

I0 f = S0 I0 + S0 I1

0

I1

= a.0 + ab = ab

S0

a

a

I0 I1

S0

2 to 1 MUX

f1

f2 = S0 I0 + S0 I1 = ba + ba b

a

2-input AND

= b a + b f1

S0

= ab + ab = a Å b

b

2-input X-OR

Q20 (a) Z = S1 S0 I0 + S1 S0 I1 + S1 S0 I 2 + S1 S0 I3 = R S (P + Q) + R SP + R S P Q + R SP = P R S + Q R S + P R S + P Q R S + PRS = P Q R S + P Q R S + P Q R S + P Q R S +PQRS+ P QRS+ PQR S + PQRS+ PQRS Repeated term has been ignored and output Z is simplified as follows. Z

Z = PQ + QRS + PQS

RS

PQ

RS

RS

RS

1

1

(loops are selected as per given option) PQ

Q21 (a) 0 1 1 0

4 to 1 MUX

0 1 1 0

Y S1

S0

A

B

PQ

1

1

1

PQ

1

1

1

4 to 1 MUX Y S1

X

S0 C

X1

X1 = S1S0 .0 + S1S0 .1+ S1S0 .1+ S1S0 .0 = A B + AB

X = S1S0 .0 + S1S0 .1+ S1S0 .1+ S1S0 .0 = X1C + X1C = (A B + AB) C + (A B + A B) C = A BC + A BC + (A B + A B) C = A BC + A BC + A BC + A BC

GATE Solutions

40

Mechasoft

Q22 (a) The output E of first (left) 2 ´ 1 MUX, is E = B C + B C and the output of second (right) 2 ´ 1 MUX, is f = E. 0 + E A = (B C + B C) A = A BC + A BC Q23 (c) Implementation of 4 to 1 M UX using 2 to 1 MUX 4 to1 MUX

I0

I0

I1

I1

2 to1 MUX

S0 I0

I1

S0 S1

2 to1 MUX S0

S0

I2

I0

I3

2 to1 I1 MUX

4 to1

MUX

Note : If multiplexers have enable facility additionally, the minimum number of 2 to 1 multiplexers could be 2 to realize 4 to 1 multiplexer but the configuration will require one OR gate as demonstrated below.

S1

I0

I0 2 to1

I1

I1 E

I2

I0

I3

I1 2 to1 E MUX

MUX S0

S0 S0

Q24( c) All functions of three variables can be implemented using 8×1 MUX by connecting three variables to three Select/Control lines and 8 Input lines to either VCC or ground depending on min/max terms of the function. Some but not all functions of four variables can be implemented by connecting three out of four variables to Select/Control lines and 8 Input lines to either VCC or ground or fourth variable (normal/complemented). Note that implementation of some functions of four variables might also need additional circuitry.

GATE Solutions

Mechasoft

41

Q25. As demonstrated below, The half adder outputs pn and gn ; n = 0, 1, 2, 3 (also referred to as carry propagate and carry generate ), are generated simultaneously after 20ns equal to delay of an XOR gate. The carry from previous stage, propagation through two gates an AND and an OR for HA 15 + 10 = 25ns. Z0=1 Xn Z3=1 Z2=0 Z1=0 pn 20 Augend →X3X2X1X0 1 0 0 1 ns Yn Sn Augend →Y3Y2Y1Y0 0 1 0 0 Sum 1 1 0 0 0 Zn+1 15 15 ns 10 ns S2 S0 S1 Z4 S3 gn ns Zn The output of ripple carry adder will be stable after 15 + 10 (at LSB) +15 +10(at MSB) = 50ns Note that the sum bit S0 will be stable after 15 + 10 =25ns equal to time taken by Z0 to propagate through an AND and an OR gate. S1 and S2 will be stable simultaneously. S3 will take additional 15 + 10 = 25ns for propagation of carry Z3 through an AND and an OR gate. Q26(a)

decimal

Binary

Gray

decimal

d

X2 X1 X0

Y2 Y1 Y0

d

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0 0 0 0 1 1 1 1

0 0 1 1 1 1 0 0

0 1 1 0 0 1 1 0

0 1 3 2 6 7 5 4

X1 X0

O P0 O P1 O P2 O P3 O P4 O P5 O P6 O P7

I P0 I P1 I P2 I P3 I P4 I P5 I P6 I P7

Y2 8:3 Encoder

0 0 0 0 1 1 1 1

3:8 Decoder

0 1 2 3 4 5 6 7

X2

Y1 Y0

As demonstrated just above ,the interconnection of decoder and encoder implements Binary to Gray code converter. Q27. The worst case delay of 16 bit ripple carry adder = 15 ´ carry propagation delay + 1 ´ sum propagation delay = 15 ´ 12 + 1 ´ 15 = 195 ns In general, the total propagation delay in an n bit parallel (ripple carry) adder = one Half Adder delay + (n ´ delay of one AND gate) + (n ´ delay of one OR gate) = delay of one XOR gate + n ´ delay of one AND gate + n ´ delay of one OR gate = 1 ´ sum propagation delay of Full Adder + ( n – 1) ´ carry propagation delay

42

GATE Solutions

Mechasoft

Q28 (d) 2n ³ 100; n is the smallest integers. n = 7 satisfies this. Q29 (b) Each block corresponds to a full subtractor with P as minuend, Q as subtrahend and R as borrow from previous stage. The outputs Y and Z are difference and borrow respectively with Y = P − Q. Q30 (d)Let input nibble be g3 g2 g1 g0 with g3 as MSB and output nibble be b3 b2 b1 b0 with b3 as MSB. Then b3 = g 3 , b 2 = g 3 Å g 2 b1 = g1 Å [(g 2 Å g 3 ) (g 2 + g 3 )]

= g1 Å [(g 2 g3 + g 2 g 3 ) (g 2 + g 3 )]

= g1 Å (g 2 g3 + g 2 g 3 ) = g1 Å g 2 Å g 3 Similarly, b 0 = g 0 Å g1 Å g 2 Å g 3 These expression for b3, b2, b1 and b0 in terms of g3, g2, g1 and g0, clearly indicate that the circuit coverts Gray code into corresponding Binary code.

3

Chapter Section1

Sequential Circuits (flip flops , counters, shift registers and FSM) GATE Questions

Q1. The propagation delay of the exclusive -OR (XOR) gate in the circuit shown below , is 3ns . The propagation delay of all the flip-flpos is assumed to be zero. The clock (clk) frequency provided to the circuit is 500MHz. Q2 D2

D2

Q0

Q1 D2

Clk Starting from the initial value of the flip-flop outputs Q2 Q1 Q0=111 with D2 =1 , the minimum number of triggering clock edges after which the flip-flop outputs Q2 Q1 Q0 becomes 100(in integer ) is ________________. [GATE 2021/2marks] Q2. For the components in the sequential circuit shown below , tpd is the propagation delay , tsetup is the setup time , and thold is the hold time. the maximum clock frequency (rounded off to the nearest integer ), at which the given circuit can operate reliably , is _____________MHz.

Flip Flop 1 Clk

tpd=2ns

tpd=2ns

tpd=3ns tsetup=5ns thold=1ns

Flip Flop 2

IN

tpd = 8ns tsetup=4ns thold= 3ns

[GATE 2020/2marks] Q3. The state diagram of a sequence detector is shown below . State S0 is the initial state of the sequence detector. If the output is 1 , then 0/0 1/0 0/0 (a) the sequence 01010 is detected . (b) the sequence 01011 is detected .

s0

0/0

s1

1/0

s2

0/0

s3

(c) the sequence 01110 is detected . 1/0 (d) the sequence 01001 is detected.

s4 1/0

1/0

0/1 [GATE 2020/2marks]

GATE Questions

44

Mechasoft

Q4. In the 8085 microprocessor , the number of address lines required to access a 16K byte memory bank is ______________ [GATE 2020/1mark] Q5. In the circuit shown, the clock frequency, i.e., the frequency of the clk signal, is 12 kHz. The frequency of the signal at Q2is ____ _____kHz.

D1 Q1

D2 Q2

clk Q̅ 1

clk Q̅ 2

12 kHz

[GATE 2019/2marks] Q6. The state transition diagram for the circuit shown is

D

Q

1

Q̅

0

CLK

A A=0

A=1 Q=1

Q=0

(a) A=0

A=1

A=0

A=1

Q=0

(b) A=0

A=1

A=0 ( c)

A=1

Q=0 A=1

Q=1

A=0 Q=0

(d)

Q=1 A=0

A=1

A=1

Q=1 A=0

[GATE 2019/2marks]

GATE Questions

Mechasoft

45

Q7. A traffic signal cycles from GREEN to YELLOW, YELLOW to RED and RED to GREEN. In each cycle, GREEN is turned on for 70 seconds, YELLOW is turned on for 5 seconds and the RED is turned on for 75 seconds. This traffic light has to be implemented using a finite state machine (FSM). The only input to this FSM is a clock of 5 second period. The minimum number of flip-flops required to implement this FSM is ____.[GATE 2018/1mark] Q8. In the circuit shown below, a positive edgetriggered D Flip-Flop is used for sampling input data Din using clock CK. The XOR gate outputs 3.3 volts Din for logic HIGH and 0 volts for logic LOW levels. The data bit and clock periods are equal and the value of ∆T/TCK = 0.15, where the parameters ∆T and TCK CK are shown in the figure. Assume that the Flip-Flop and the XOR gate are ideal.

X Q

D

D Flip-Flop CLK ∆

If the probability of input data bit (Din) transition in each clock period is 0.3, the average value (in volts, accurate to two decimal places) of the voltage at node X, is_______________. TCK CK Din ∆T

∆T

[GATE 2018/2marks]

∆T

Q9. In the latch circuit shown, the NAND gates have non-zero, but unequal propagation delays. The present input condition is: P = Q = ‘0’. If the input condition is changed simultaneously to P = Q = ‘1’, the outputs X and Y are P X (a) X = ‘1’, Y = ‘1’ (b) either X = ‘1’, Y = ‘0’ or X = ‘0’, Y = ‘1’ (c) either X = ‘1’, Y = ‘1’ or X = ‘0’, Y = ‘0’ Y (d) X = ‘0’, Y = ‘0’ Q [Set1/GATE 2017/1mark] Q10. Consider the D-Latch shown in the figure, which is transparent when its clock input CK is high and has zero propagation delay. In the figure, the clock signal CLK1 has a 50% duty cycle and CLK2 is a one-fifth period delayed version of CLK1. The duty cycle at the output latch in percentage is ___________. CLK1 CLK1

TCLK

CLK2

CLK2

Q D D-Latch CK

Output

TCLK/5

[Set1/GATE 2017/1mark]

GATE Questions

46

Mechasoft

Q11. A 4-bit shift register circuit configured for rightshift operation, i.e, Din → A, A→ B, B →C, C → D, is shown. If the present state of the shift register is ABCD = 1101, the number of clock cycles required to reach the state ABCD = 1111 is _________.

Din

A B

C

D

Clock

[Set1/GATE 2017/2marks] Q12. A finite state machine (FSM) is implemented using the D flip-flops A and B, and logic gates, as shown in the figure below. The four possible states of the FSM are QAQB= 00,01,10 and 11. Assume that XIN is held at a constant logic level throughout the operation of the FSM. When the FSM is initialized to the state QAQB = 00 and clocked, after a few clock cycles, it starts cycling QA through Q Q D D QB (a) all of the four possible states if XIN = 1 A B XIN (b) three of the four possible states if XIN = 0 CK Q CK Q (c) only two of the four possible states if XIN = 1 (d) only two of the four possible states if XIN = 0 CLK

Q13.The state diagram of a finite state machine (FSM) designed to detect an overlapping sequence of three bits is shown in the figure. The FSM has an input ‘In’ and an output ‘Out’. The initial state of the FSM is S0. If the input sequence is 10101101001101, starting with the left-most bit, then the number times ‘Out’ will be 1 is __________.

In = 0 out = 0

00 S0

In = 0 out = 0

In = 1 out = 0

01 In = 1 out = 0 S1 In = 0 out = 0

In = 1 out = 0

10 S2 In = 1 out = 1

In = 0 out = 0

11 S3

[Set1/GATE 2017/2marks] Q14. Assume that all the digital gates in the circuits shown below in the figure are ideal , the resistor R=10kΩ and the supply voltage is 5V. The D flip-flop D1,D2,D3,D4 and D5 are initialized with logic values 0,1,0,1 and 0, respectively . The clock has a 30% duty cycle The average power dissipated (in mW) in the resistor R is______

D1

Q1

D2

Q2

D3

Q3

D4

Q4

D5

Q5

R=10kΩ

clock [Set2/GATE 2016/1mark]

GATE Questions

Mechasoft

Q15. The state transition diagram for a finite state machine with states A ,B and C , and binary inputs X, Y, and Z, is shown in the figure .

47 Y=1 X=0,Y=0,Z=0

A

X=0,Z=1

Which one of the following statements is correct ? (a) Transitions from state A are ambiguously defined. (b) Transitions fro state B are ambiguously defined. (c) Transitions from state C are ambiguously defined . (d) All of the state transitions are defined unambiguously.

B

Y=1

Y=0,Z=0 X=1, Y=1, Z=1 Z=1 Y=0,Z=1

X=1,Y=0

C Z=0

[Set2/GATE 2016/2marks] Q16.For the circuit shown in the figure , the delay of the bubbled NAND gate is 2ns and that of the counter is assumed to be zero . If the clock (Clk) frequency is 1 GHz, then the counter behaves as a (a) mod-5 counter Clk

(b) mod-6 counter

Q0 (LSB) 3-bit synchronous counter Q1 Q2 (MSB)

( c) mode-7counter

RESET

(d) mod-8 counter [Set3/GATE 2016/2marks] Q17. A mod-n counter using a synchronous binary up-counter with synchronous clear input is shown in the figure. The value of n is ________________.

Clock

QA QB QC CLEAR QD

4-Bit Binary Counter

QA QB QC QD [Set2/GATE 2015/1mark]

GATE Questions

48

Mechasoft

Q18.The figure shows a binary counter with synchronous clear input. With the decoding logic shown the counter works as a

Binary Counter

(a) mod-2 counter

Q3 Q2

(b) mod-4 counter

Clock

Q1

( c)mod-5 counter

Q0

(d) mod-6 counter

CLR

[Set2/GATE 2015/2marks] Q19. The circuit shown consists of J-K flip-flops, each with an active low asynchronous reset (Rd input) .

1 Clock 1

J

Q

Q0

K Rd

1

J

1

K Rd

Q

Q1

1

J

1

K Rd

Q

Q2

The counter corresponding to this circuit is (a) a modulo-5 binary up counter

(b) a modulo-6 binary down counter

( c) a modulo-5 binary down counter

(d) a modulo-6 binary up counter [Set3/GATE 2015/1mark]

Q20. A three bit pseudo random number generator is shown. Initially the value of output Y = Y2 Y1 Y0 is set to 111. The value of output Y after three clock cycles is Y2 D2

Q2

Y1 D1

Q1

Y0 D0

[Set3/GATE 2015/2marks]

Q0

CLK

(a) 000

(b) 001

(c) 010

(d) 100

GATE Questions

Mechasoft

49

Q21. An SR latch is implemented using TTL gates as shown in the figure. The set and reset pulse inputs are provided using the push-button switches. It is observed that the circuit fails to work as desired. The SR latch can be made functional by changing (a) NOR gates to NAND gates

Q

Set

(b) inverters to buffers ( c)NOR gates to NAND gates

5V

and inverters to buffers

Q

(d) 5 V to ground

Reset [Set3/GATE 2015/2marks]

Q22. Five JK flip-flops are cascaded to form the circuit shown in Figure. Clock pulses at a frequency of 1MHz are applied as shown. The frequency (in kHz) of the waveform at Q3 is _______________. 1 J4 Q4 Clk 1 K4

1 J3 Q3 Clk 1 K3

1 J2 Q2 Clk K2 1

J1 Q1 Clk 1 K1

1

1 J0 Q0 Clk K0 1

Clock [Set1/GATE 2014/1mark] Q23. The digital logic shown in the figure satisfies the given state diagram when Q1 is connected S =0 [Set1/GATE 2014/2marks] to input A of the XOR gate. D1 Q1

A

00

D2 Q2

S=1

CLK Q1

S

Q2

10

S=1 S =0 S =0 S=1

01 S=1 11 S =0

Suppose the XOR gate is replaced by an XNOR gate. Which one of the following options preserves the state diagram? (a) Input A is connected to Q2 ( c) Input A is connected to Q1 and S is complemented

(b) Input A is connected to Q2 (d) Input A is connected to Q1

GATE Questions

50

Mechasoft

Q24. In the circuit shown, choose the correct timing diagram of the output (y) from the given waveforms W1, W2, W3 and W4. X1 D Q FF1

CIK Clk

X1

Q output(y)

X2 W1

X2

W2 W3

D

Q FF2 Q

W4

(a) W1

(b) W2

(c) W3

(d) W4 [Set2/GATE 2014/2marks]

Q25. The circuit shown in the figure is a (a) Toggle Flip Flop D (b) JK Flip Flop ( c) SR Latch Clk (d) Master-Slave D Flip flop

Q D Latch Q En

Q D Latch Q En

[Set3/GATE 2014/1mark] Q26. In the given circuit, the race around (a) does not occur (b) occurs when CLK=0 (c) occurs when CLK = 1 and A =B = 1 (d) occurs when CLK=1 and A =B = 0

A CLK B [GATE 2012/1mark]

Q27. The state transition diagram for the logic circuit shown is A=1

Q=0

A=0

A=0

Q=0

Q=1 A=1

A=1

A=1

A=1

Q=1

(d)

Q=0

A=1

A=0

Q

X1

CLK Q

X0 select A

A=0 Q=1

2-1 MUX D

Y

(b)

A=0

( c) Q=0

A=0 A=1

A=1

(a)

A=0

A=0

Q=1

GATE Questions

Mechasoft

51

Q28. When the output Y in the circuit below is “1”, it implies that data has (a) changed from “0” to “1” Data D Q D Q (b) changed from “1” to “0” ( c) changed in either direction (d) not changed

Clock

Q

Y

Q [GATE 2011/1mark]

Q29. Two D flip-flops are connected as a synchronous counter that goes through the following QB QA sequence 00 → 11 → 01 → 10 → 00 → ….. [GATE 2011/2marks] The connections to the inputs DA and DB are (a) DA = QB, DB = QA (b) DA = QA ,DB = QB ( c) DA = (QA QB + QAQB ),DB = QA (d) DA = (QAQB + QA QB ), DB = QB

Q30. Assuming that the flip-flops are in reset condition initially, the count sequence observed at QA, in the circuit shown is Output (a) 0010111……. (b) 0001011…….

DA

( c)0101111…….

QA

DB

QA

QB

DC

QC

QB

QC

Clock (d) 0110100……

[GATE 2010/2marks]

Q31. What are the counting states (Q1, Q2) for the counter shown in the figure below ? (a) 11, 10, 00, 11, 10, ….. Q1 (b) 01, 10, 11, 00, 01, …. J1 Q1 J2 Q2 ( c)00, 11, 01, 10, 00, …. (d) 01, 10, 00, 01, 10, ….

JK Flip Flop

Clock K1

Q1

Q2

JK Flip Flop

1

K2

Q2

[GATE 2009/2marks]

GATE Questions

52

Mechasoft

Q32. Refer to NAND and NOR latches shown in the figure. The inputs (P1, P2) for both the latches are first made (0, 1) and then, after a few seconds, made (1, 1). The corresponding stable outputs (Q1, Q2) are P P1 1 Q1 Q1

Q2

P2

Q2

P2

(a) NAND : first (0, 1) then (0, 1) NOR : first (1, 0) then (0, 0) (b) NAND : first (1, 0) then (1, 0) NOR : first (1, 0) then (1, 0) (c) NAND : first (1, 0) then (1, 0) NOR : first (1, 0) then (0, 0) (d) NAND : first (1, 0) then (1, 1) NOR : first (0, 1) then (0, 1)

[GATE 2009/2marks]

Q33. For the circuit shown in the figure, D has a transition from 0 to 1 after CLK changes from 1 to 0. 1 CLK 0 D 1 Q 0

Q Which of the following statements is true? (a) Q goes to 1 at the CLK transition and stays at 1. (b) Q goes to 0 at the CLK transition and stays at 0. (c) Q goes to 1 at the CLK transition and goes to 0 when D goes to 1. (d) Q goes to 0 at the CLK transition and goes to 1 when D goes to 1. [GATE 2008/2marks] Q34. For each of the positive edge-triggered J-K flip flop used in the following figure, the propagation delay is ΔT. CLK 1

1

J0

1

K0

CLK

0 T t1

t

Q0

1

J1

1

K1

Q1

GATE Questions

Mechasoft

53

Which of the following waveforms correctly represents the output at Q1? 1

(a)

0 2T t1 +

ΔT

1

(b)

0 4T t 1 + 2 ΔT

1

( c)

0 2T t 1 + 2 ΔT

1

(d)

0 4T t1 +

[GATE 2008/2marks]

ΔT

Q35. The following binary values were applied to the X and Y inputs of NAND latch shown in the figure in the sequence indicated below. X P X = 0, Y = 1; X = 0, Y = 0; X = 1, Y = 1 The corresponding stable P, Q outputs will be. (a) P = 1,Q = 0; P = 1, Q = 0; P = 1, Q = 0 or P = 0, Q = 1 (b) P = 1,Q = 0; P = 0, Q = 1 or P = 1, Q = 0; P = 0, Q = 1 (c) P = 1,Q = 0; P = 1, Q = 1; P = 1, Q = 0 or P = 0, Q = 1 (d) P = 1,Q = 0; P = 1, Q = 1; P = 1, Q = 1

Y

Q

[GATE 2007/2marks]

GATE Questions

54

Mechasoft

Q36.For the circuit shown, the counter state (Q1 Q0) follows the sequence (a) 00, 01, 10, 11, 00…… (b) 00, 01, 10, 00, 01…… (c) 00, 01, 11, 00, 01….. D0 Q0 D1 Q1 (d) 00, 10, 11, 00, 10.... CLK CLK [GATE 2007/2marks] Q37. For the circuit shown in figure below, two 4-bit parallel-in serial-out shift registers loaded with the data shown are used to feed the data to a full adder. Initially, all the flip-flops are in clear state. After applying two clock pulses, the output of the full-adder should be (a) S = 0, C0 = 0 (b) S = 0, C0 = 1 ( c)S = 1, C0 = 0 (d) S = 1, C0 = 1

Full Adder

Shift Register 1

0

1

D

A

Q

S

LSB

MSB 0

1

0

1

1

D

B

Q

Shift Register

C1 Q

C0 D

CLK

[GATE 2006/2marks] Q38.Two D-flip-flops, as shown below, are to D0 Q0 be connected as a synchronous counter that goes through the following Q1 Q0 sequence. CK Q0 Clock 00 ® 01 ® 11 ® 10 ® 00 ® ….. The inputs D0 and D1 respectively should be connected as (a) Q1 and Q0

(b) Q1 and Q1

LSB

( c) Q1Q0 and Q1Q0

D1 CK

Q1

MSB

Q1

(d) Q1 Q0 and Q1Q0 [GATE 2006/2marks]

Q39. The present output Qn of an edge triggered JK flip-flop is logic 0. If J = 1, then Qn+1 (a) cannot be determined (b) will be logic 0 ( c) will be logic 1 (d) will race around [GATE 2005/2marks] Q40. Figure shows a ripple counter using positive edge triggered flip-flops. If the present state of the counter is Q2 Q1 Q0 = 011, then its next state (Q2 Q1 Q0) will be (a) 010 1 T2 1 Q2 1 T1 T0 Q1 Q0 (b) 100 CLK ( c) 111 Q2 Q0 Q1 (d) 101 [GATE 2005/2marks]

GATE Questions

Mechasoft

55

Q41.A master-slave flip-flop has the characteristic that (a) change in the input is immediately reflected in the output. (b) change in the output occurs when the state of the master is affected. (c) change in the output occurs when the state of the slave is affected. (d) both the master and the slave states are affected at the same time [GATE 2004/1mark]

Q42.Choose the correct one from among the alternatives A,B,C,D after matching an item from Group I with most appropriate item in Group II. Group-I Group-II P. Shift register 1. Frequency division Q. Counter 2. Addressing in memory chips R. Decoder 3. Serial to parallel data conversion (a) P − 3, Q − 2, R − 1 (b) P − 3, Q − 1, R − 2 (c) P − 2, Q − 1, R − 3 (d) P − 1, Q − 2, R − 2 [GATE 2004/1mark] Q43.In the modulo-6 ripple counter shown in figure the output of the 2-input gate is used to clear the J-K flip-flops.The 2-input gate is 1 C

B

J

C clr K

J

B clr K

A

J

clock input

A clr K

2 – input gate

(a) a NAND gate (c) an OR gate

(b) a NOR gate (d) an AND gate

[GATE 2004/2marks]

GATE Questions

56

Mechasoft

Q44.A mod 6 synchronous counter consists of three JK flip flops and a combination circuit of two input gate (s). The combination circuit consists of (a) one AND gate (b) one OR gate ( c) one AND gate and one OR gate (d) two AND gates [GATE 2003/1mark] Q45.A 4 bit ripple counter and a 4 bit synchronous counter are made using flip flops having a propagation delay of 10ns each. If the worst case delay in the ripple counter and the synchronous counter be R and S respectively, then (a) R = 10 ns, S = 40 ns (b) R = 40 ns, S = 10 ns ( c) R = 10 ns, S = 30 ns (d) R = 30 ns, S = 10 ns [GATE 2003/2marks]

Answer Key Q1 (5) Q8 (0.84) Q15 (c)

Q2 Q9 Q16

(77) Q3 (b) Q10 (d) Q17

Q5 (14) (a) Q4 Q12 (30) Q11 (10) Mechasoft Q19 (c) (7) Q18

(4) (d) (a)

Q6 Q13 Q20

(c) (4) (d)

Q7 Q14 Q21

(5) (1.5) (d)

Q22 (62.5) Q29 (d) Q36 (b) Q43 ( c)

Q23 Q30 Q37 Q44

(d) (d) (d) (d)

Q26 (d) (c) Q25 Q33 Q32 (c) (a) Mechasoft Q40 (c) (a) Q39 (b)

(a) (c) (b)

Q27 Q34 Q41

(d) (b) (c)

Q28 Q35 Q42

(a) (c) (b)

Q24 Q31 Q38 Q45

How you do spells ability . Why you do spells motivation. How well you do spells attitude.

GATE Solutions

Section2

Q1. The clock frequency , fclk = 500MHz and the clock period Tclk =2ns. As demonstrated below, starting from initial state Q2 Q1 Q0=111 with D2=1 , the flip-flop outputs Q2Q1Q0 becomes 100 after 5 clock edges.

State tabel Clk edge number

Time,t D = Q Å Q 2 0 (in ns) 2

1 Q2

Q1

Q0

1

0

1

1

1

1

2

2

1

1

1

1

3

0

2

3

5

4

D2 Q2

3

4

0

1

1

4

6

0

0

1

Q1 Q0

7 5

8

1

0 1

0

0

111

1

2 111

3

4 011

5

6 001

7

8 100

t(ns)

GATE Solutions

58

Mechasoft

Q2 .When the signal flows from FF2 to FF1 , the next clock should not arrive before tpd, FF2 + tsetup,FF1=8ns+5ns =13ns for reliable operation. Similarly , when the signal flows from FF1 to FF2 , the next clock should not arrive before tpd,FF1,+tpd,X-Nor + tpd,NAND + tsetup, FF2= 3ns +2ns +2ns +4ns =11ns for reliable operation. 9 Thus , the reliable circuit operation demands that TCLK ≥ 13ns and fCLK ≤ 10 /13 Hz, that is , fCLK , max =76.92 @ 77MHz Q3(a). As demonstration below , the sequence detected is 01010.

s0

s1

*

* s2 0/0 s3

*

1/0

0/0

*

*

1/0

0/1

s4 4

10

14

n

Q4. Let n be the number of address lines. 16 k byte = 2 ×2 ×8= 2 ×8 ≡ 2 ×8. In order to access a 16 k byte memory bank, 14 address lines will be required . Q5.PS ≡Present state ; NS ≡ Next state FF

PS

Inputs

NS

Q1 Q2 D1 = Q1 Q 2 D 2 = Q1

Q1+ Q 2 +

0 1 0

1 0 0

0 0 1

1 0 0

0 1 0

10

00

0 1 0

01

The circuit has 3 distinct states (mod- 3 counter) .The frequency of signal at Q2 is (12/3) = 4kHz

Q6( c)

FF Input

PS Input Q

A

0 0 1 1

0 1 0 1

D = AQ 1 1 1 0

NS Q+

1 1 1 0

Q Q

0

out

F

1 S 0 A F = AQ + AQ D = Q.(A Q + AQ)

A=0,1 Q=0

Q=1 A=1

A=0

= AQ

D

GATE Solutions

Mechasoft

59

Q7. Green 70s

Yellow 5s

Red 75s

One cycle takes 70 + 5 + 75 = 150s

Clock period =5s and number CPS required in one cycle = 150 / 5 = 30. Thus, FSM will have 30 4 5 distinct states and minimum 5FFS will be required to implement it (2 ≤ 30 ≤ 2 ) Q8. Note that D Flip Flop has characteristic equation, Q(t + 1) = Din. When positive edge of clock occurs, Q output of FF and Din to FF, will be same ,either Q = Din = 0 or Q = Din = 1 and this will force X - OR gate to generate output X = 0. The output X will change from 0 to 1 only if Din undergoes transition ,either from 1 to 0 or 0 to 1 before the next positive edge of clock occurs. In case of no transition, the output X continues to remain 0. CK Din transition probability = 0.3 No transition probability = 0.7

3.3V X 0V

TCK 0.85TCK

∆T=0.15 TCK

X=0 0.85T

CK In case of Din transition, duty cycle , D = = 0.85 T CK Average voltage at node X is VX,av = duty cycle × Peak value × transition probability + 0 × no transition probability = 0.3 × 0.85 × 3.3+ 0 × 0.7 = 0.84V.

Q9(b) Any low input to NAND gate, forces its output to go high. For inputs P = Q = 0, the outputs X = Y = 1. On changing input conditions toP = Q = 1, the possible outputs will be either X = 1, Y = 0 or X = 0, Y = 1 depending on which gate is faster. Such a condition is referred to as race. Truth table NAND Logic P X=1 0/1 0 1 Inputs Output 0 0 1 1 0 1 1 1 0 Y=1 1/0 Q 0 1 1 0 1

GATE Solutions

60 Q10. CLK1=D

T 2

Mechasoft

CLK1

Output

D Q CK

CLK2 Output Q

T 5

CLK2 T T 2 5

Output = D.CLK2 = CLK1.CLK2 T

(T/ 2) - (T/ 5) 5-2 ´100 = ´100 = 30% T 10 Q11. Din = A Å D The right shift Din ® A, A ® B, B ® C and C ® D on arrival of each clock, is demonstrated below. Bear in mind that the present state is ABCD = 1101. Din = A Å D ® A D CLK No. B C 1 0 1 0 1 1 0 1 1 0 Din = 0 2 1 1 0 AÅD 3 0 0 1 1 A B C D 4 0 0 0 1 Clock 0 5 0 1 0 6 0 0 0 1 0 0 7 1 0 8 0 1 0 1 10 clock pulses are required to reach 9 0 1 1 1 the state ABCD = 1111 1 10 1 1 1

The output Q has duty cycle %D =

Q12(d) State table for XIN = 0 Present state

A 0 0 1

XIN

FF Inputs DA = A Å B

Next state + + A B 1 0 1 1 1 0

B 0 0 1 0 1 1 0 1 1 0 1 0 State table for XIN = 1 FF Inputs Present state Next state XIN D = A Å B D = A.X IN A+ A A B+ B B 0 0 1 1 0 0 1 1 1 0 1 1 1 1 1 1 1 0 0 0 0 D B = A.X IN

Note that D flip flop has next state equation: Q(t + 1) = D

00

0

01

0 11 AB

0 FSM cycles through two of four possible states. 00

1

01 AB

1

11

1 FSM cycles through three of four possible states.

GATE Solutions

Mechasoft

61

Q13.The state transition for input sequence, In = 1010 1101 0011 01 is demonstrated below. #1 #2 Present Next 0/0 1/1 1/1 1/0 0/0 IN Out S2 state S3 state S3 S2 S1 S0 1/0 S1 S0 1 0 S1

0

S2

0

S2

1

S3

S3

0

S2

1 #1 0

S2

1

S3

1 #2

S3

1

S1

S1

0

S2

0 0

S2

1

S3

1 #3

0/0 S2

S3

0

S2

0

1/1

S1 0/0

In/Out

S2 1/1 #3 S1

1/0

S1

1/0

S0

0/0

S2

0/0

S3

#4 S3

S2

0

S0

0

S0

1

S1

S1

1

S1

0 0

S1

0

S2

0

S2

1

S3

1 #4

It is easy to observe that ‘Out’ will be 1, 4 times.

Q14. Note the characteristic equation of D flip flop ,Q(t+1) =D, that is ,Q output of D flip flop simply follows the D input .The state table of the circuit is demonstrated below .

Flip Flop outputs

Clock number Q Q Q Q Q 1 5 4 2 3 0 1 2 3 4 5 6 7 8 9 10

0 0 1 0 1 0 0 1 0 1 0

1 0 0 1 0 1 0 0 1 0 1

0 1 0 0 1 0 1 0 0 1 0

1 0 1 0 0 1 0 1 0 0 1

0 1 0 1 0 0 1 0 1 0 0

Circuits outputs Y= Q3+Q5 0 1 0 1 1 0 1 0 1 1 0

Þ

The output y follows the sequence 01011 01011 01011....

GATE Solutions

62 1

2

3

4

5

6

7

Mechasoft 8

10

9

5V 0

0

1

1

1

0

T (sequence repetition period)

1

0

1

1

0

0V

T

During each repetition period T, the sequence remains at +5V for three clock periods and at 0V for two clock periods .The duty cycle =(3/5),peak power =(5×5)/10k=2.5mW and average power =peak power × duty cycle =2.5× (3/5)=1.5mW Q15( c)The transitions from State C are ambiguously defined in the sense that , for X =Y=Z =1 and present state C, there are two possible transitions from C to B and from C to A. It is not well defined whether the finite state machine will transit to B or A from C when binary inputs X=Y=Z=1.Note that the transitions from state A and state B are well defined. Q16(d) Note that the NAND gate (reset logic) generates output after 2ns which is equal to two clock periods . The clock frequency is 1GHz and clock period is 1ns . Let the initial condition be Q2Q1Q0 =000 (decimal 0). The counter is allowed to count further up to Q2 Q1 Q0=110 (decimal 6) where NAND gate is activated to generated output 0 but it does so after 2ns equivalent to 2 clock periods during which counter advances to 111(decimal 7) and back to 000(decimal 0). By the time counter further advances to 001 (decimal 1) ,the NAND output again transits to 1 to allow the counter to repeat the cycle. There will be 8 distinct states and the circuit will behave as a mod 8 counter. States Clock number Q Q Q 2 1 0 0 1 2 3 4 5 6 7

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

NAND gate is activated but will generate output ‘0‘ after two clock periods that is , 2ns. By this time the counter goes back to initial state ‘000‘ and cycle repeats.

Q17. The synchronous binary up counter begins to count from QA QBQCQD = 0000 and continues sequentially up to QAQBQCQD = 0101 (decimal 5) and the output of NAND gate remains '1' till QAQBQCQD = 0101. When on arrival of next clock QAQBQCQD = 0110 , the input requirement for NAND gate to generate output ‘0' is met but it does so only on arrival of still next clock due to synchronous clear input. Thereby, '0110' becomes a valid state .

GATE Solutions

Mechasoft

63

After valid state QAQBQCQD = 0110 ,the NAND gate generates output '0' and the counter resets to all 0's ,that is, QAQBQCQD = 0000 again . Once flip flops have been cleared, the NAND output goes back ‘1' and the cycle repeats as demonstrated below. QA

QB

QC

QD

0

0

0

0

0

0

0

1

0

0

1

0

0

0

1

1

0

1

0

0

0

1

0

1

0

1

1

0

QB QC

Clear

The counter essentially counts from 0000 to 0110 through 7 distinct states. Thus, it is a mod 7 counter, n = 7. Q18(b)The binary up counter begins to count from Q3Q2Q1Q0 = 0000 and continues sequentially up to Q3Q2Q1Q0 = 0011 (decimal 3) and the output of NAND gate remains '1' till Q3Q2Q1Q0 = 0011. When on arrival of next clock Q3Q2Q1Q0 = 0100 , the input requirementfor NAND gate to generate output ‘0' is met but it does so only on arrival of still next clock due to synchronous clear input. Thereby, '0100' becomes a valid state . After valid state Q3Q2Q1Q0= 0100 ,the NAND gate generates output '0' and the counter resets to all 0's ,that is, Q3Q2Q1Q0 = 0000 again . Once flip flops have been cleared, the NAND output goes back ‘1' and the cycle repeats as demonstrated below. Q3

Q2

Q1

Q0

0

0

0

0

0

0

0

1

Q3

0

0

1

0

Q2

0

0

1

1

0

1

0

0

CLR

The counter essentially counts from 0000 to 0100 through 5 distinct states. Thus, it is a mod 5 counter, n =5.

GATE Solutions

64

Mechasoft

Q19 (a) The circuit consisting of J K flip flops (each flip flop has J = K= 1) is three bit truncated ripple (asynchronous) counter. The basic clock is applied to LSB flip flop with output Q0(LSB) and the output of each flip is being used as clock to subsequent flip flops. This is binary up counter, the explanation for which follows little later. The counter begins to count from Q2 Q1 Q0 = 000 up to Q2 Q1 Q0 = 100, the NAND gate output remains '1' . When the counter reaches the temporary state Q2 Q1Q0 = 101, the NAND gate generates output '0' to activate an active low asynchronous reset (Rd) and reset the counter to all 0's that is, Q2Q1Q0 = 000. Then , the NAND gate output again returns to 1 to deactivate Rd input. The cycle repeats as demonstrated below. Q2

Q1

Q0

0

0

0

0

0

1

0

1

0

0

1

1

1

0

0

1

0

1

(temporary state to clear the counter)

The counter has 5 distinct states. This is a module-5 binary up counter. Note that up/down counting sequence of a ripple counter depends on the following three aspects. (i)Whether the flip flops in ripple counter are positive edge triggered or negative edge triggered. Let Pn =1 for negative edge triggering and Pn = 0 for positive edge triggering. (ii)Whether the internal clocks are Q outputs of previous flip flops or Q outputs of previous flip flops. Let QCLK = 1 for Q outputs being used as internal clocks and QCLK = 0 for Q outputs being used as internal clocks. (iii) Whether normal (Q) outputs of flip flops are counter outputs or complementary (Q) outputs of flip flops are counter outputs. Let QOUT = 1 for Q outputs of flip flops being counter outputs and QOUT = 0 for Q output of flip flops being counter outputs.

GATE Questions

Mechasoft

65

Form an expression UP = Pn Å QCLK Å Qout .If UP = 1 the counter will be in up counting sequence and if UP = 0, the counter will be in down counting sequence. In the present problem Pn = 1, QCLK = 1and Qout = 1. Since UP = 1, the circuit is up counter.

Q20(d)The three bit pseudo random generator having initial value Y = Y2 Y1 Y0 = 111, will have output Y = Y2 Y1 Y0 = 100 after three clock cycles as demonstrated below. Present state Flip-Flop Inputs Next state Clock + Sl.No. Y2=Q2 Y1=Q1 Y0=Q0 D2=Q1ÅQ0 D1=Q2 D0=Q1 Y2=Q 2 Y1=Q1+ Y0=Q+0 initial

0

1

1

1

0

1

1

0

1

1

after clk 1

1

0

1

1

0

0

1

0

0

1

after clk 2

2

0

0

1

1

0

0

1

0

0

after clk 3

3

1

0

0

0

1

0

0

1

0

Q21(d) Any input terminal kept floating in TTL gates, is as good as applying logic '1' at that input. In the given circuit, the set and Reset inputs are always '1' whether the push button switches are ON/OFF. When ON, the corresponding input is '1' and when OFF, the corresponding floating input is again as good as '1'. By changing 5V to ground the circuit functions as SR Latch as demonstrated below. Inputs

Outputs

Action

set

reset

Q

Q

0

0

0

0

Forbidden

0

1

0

1

Reset

1

0

1

0

Set

1

1

Q

Q

No change

Note : (i) Any high input to NOR gate, forces its output to go low. (ii) Push button pressed º logic 0 and Push button depressed º logic 1

GATE Solutions

66

Mechasoft

Q22. Five J K flip flops are cascaded to from 5 bit ripple counter. The frequency of waveform at Q3 will be 1000/16 or 62.5 kHz. Note that the wave form at Q0 has frequency =

1000 = 500kHz, 2

at Q1 ,frequency = 1000 = 250kHz, 4 at Q2 ,frequency = 1000 = 125kHz, 8 1000 = 62.5kHz, 16 1000 = 31.25kHz. and at Q4 ,frequency = 32

at Q3 ,frequency =

Q23 (d)Use digital circuit to write state equations as Q 2 (t +1) = D 2 = A Å S and Q1 (t +1) = D1 = Q 2 If input A is connected to Q1 , then Q 2 (t +1) = A Å S = Q1 Å S and if input A is connected to Q1 , then Q 2 (t +1) = A Å S = Q1 Å S = Q1 Å S Thus ,in order to replace XOR by XNOR, the input A should be connected to Q1 to preserve the state equation and state diagram. Note that the input S need not be complemented. Q24( c) The timing diagram of output (y) together with other relevant timing diagrams, is shown below to demonstrate that output (y) matches with wave form W3. Note that D flip-flop tracks the input available just before the clock edge. Timing Diagram Circuit Diagram X1

Clk X1

Q1

D FF1

clk

Q1 y

X2 Q1 Q2 W3 = y = Q1Q2

X2

D

Q2 FF2 Q2

GATE Solutions

Mechasoft

67

Master

Slave

D

Q D Latch 1 Q EN

Q25 (d)

D

Q D Latch 2 Q EN

Clk This is master slave D flip flop. When clock goes positive Q output of master changes according to input at D and when clock goes negative, the slave follows the master. Q26(a) The race around does not occur. When CLK = 1 and A = B = 1, both outputs are forced to be high (1) and there is no race around. But it should also be noted that when A and B return to zero, the outputs will be unpredictable and depend on whether A and B both return to zero simultaneously or A returns to zero before B or B returns to zero before A. The output (Q) will lock at either 1 or 0 depending on propagation time relation between gates(a race condition). Q27 (d) PS = Present State (Qn) ; NS = Next state (Qn +1) ; External (Ext.) input = A and Flip Flop input D = Y where Y = A X 0 + AX1 = A Q + AQ PS

Ext. Input

FF Input D = A Q + AQ

NS +

Q A Q =D 0 0 1 1 0 1 0 0 1 0 0 0 1 1 1 1 This state table translated into state diagram, gives answer (d). Q28 (a) data clk

D1

Q1

Q1

D2

Q2

Y

Q2

Y= Q1 Q2 implies Q1 and Q2 both must be 1 for Y=1. Initially let D1= 0 so that Q1 = 0 and Q2 = 1. Now if data D1 changes to 1, Q1 = 1 and Q1 = 0 but Q2 remains 1.Infact Q2 will change from 1 to 0 when next clock edge hits. The data when changed from 0 to 1, forces Q1 = Q2 = 1 and Y = 1.

GATE Solutions

68

Mechasoft

Excitation Table

Q29 (d) decimal d 0 3 1 2

QB

QA

0 1 0 1

DB

0 1 1 0

1 0 1 0

DA 1 1 0 0

DB

QA

QA

QB

1

1

DA Q A QB

1

QB

QB DB = Q B

QA

1

D A = Q A Q B + QAQB

Q30 (d) Present State QA QB QC 0 0 0 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 0 0 1

000

100

Flip Flop Inputs D A = Q B Å QC DB = QA 1 0 1 1 0 1 1 0 0 1 0 0 0 0 110

011

DC = QB 0 0 1 1 0 1 0

010

101

Next State Q A+ 1 1 0 1 0 0 0

001 Ü

QAQBQC

Q C+ 0 0 1 1 0 1 0

QA = 0 1 1 0 1 0 0.... initial condition

Q31(a) Present State Flip Flop Inputs Q1 Q2 J1 = Q 2 K = Q 1 2 0 0 1 1 1 1 0 0 1 0 1 1

Q B+ 0 1 1 0 1 0 0

state diagram

Next State J 2 = Q1 K 2 = 1 1 1

0 0

1 1

Q+1 Q2+ 1 1 1 0 0 0

00

11 10

GATE Solutions

Mechasoft * Q32 (c) p 0,1 1

Q 1 = 1, 1

* p 2 1, 1

69

* p1 0,1

*

Q 2 = 0, 0*

p2

Q 1 = 1, 0 *

Q 2 = 0, 0* 1, 1*

Note any low input to NAND, forces its output to go high and any high input to NOR, forces its output to go low. Q33 (c) For CLK=0 and D = 0 at CLK transition, Q = 1 as demonstrated below. CLK 0 1 D 0 Q =0 0 0

Q =1

0 1 After CLK transition from 1 to 0, for CLK = 0 , D = 1 and Q = 0 as demonstrated below. CLK

1

D 1

0 Q=1

0 0

Q=0

1

0 Q34(b) CLK 1 0

t

1 Q0 0

t

1 Q1

0 4T t1 t 1 +2 ΔT

t

GATE Solutions

70

Mechasoft

Q35( c) X Y P Q 0 1 1 0 0 0 1 1 1 1 1/0 0/1 Any low input to NAND gate forces its output to go high. For X = Y = 0, P = Q = 1. But when X and Y return to 1, the outputs P and Q will be unpredictable depending on whether X and Y both return to 1 simultaneously or X returns to 1 before Y or Y returns to 1 before X. The outputs P and Q will lock at either 1, 0 respectively or 0, 1 respectively depending on propagation time relation between gates. Q36 (b)

Q37 (d)

Present state Q1 Q0 0 0 0 1 1 0

Flip Flop Inputs D1 = Q0 D0 = Q1 + Q0 0 1 1 0 0 0

Clock pulse 1 2

A 1 1

B 1 1

Ci 0 1

Next state Q 1+ Q 0+ 0 1 1 0 0 0 S 0 1

Q38 (a) The state excitation table is constructed below. decimal FF Outputs FF Inputs d Q1 Q0 D1 D0 0 0 0 0 1 1 0 1 1 1 3 1 1 1 0 2 1 0 0 0 Q39( c) If present output Qn = 0 and input J = 1, then the next state Qn+1 = 1 regardless of input K.

00

01 10

state diagram

C0 1 1

D1 = Q1 Q0 + Q1 Q0 = Q0 D0 = Q1 Q0 + Q1 Q0 = Q1

GATE Solutions

Mechasoft

71

Q40 (b)Normal outputs Q2, Q1 and Q0 , positive edge triggering together with Q0 , Q1 as internal clocks, force the ripple counter to be in up counting sequence. The present state being Q2Q1Q0 = 011 (deceimal 3), the next state will be Q2Q1Q0 = 100 (decimal 4). Q41 (c) Slave follows the master and output of slave is final output of master-slave flip flop. Q42(b)Shift register does serial in parallel out (SIPO) operation, counter does frequency division and decoder is used in memory addressing. Q43( c) The output C is MSB and A is LSB. Flip flops have active low clear. The mod 6 up counter has the counting sequence 000 ® 001 ® 010 ® 011 ® 100 ® 101 ® 000 and so on. The illegal counts are 110 and 111. The output Y of reset logic (two input gate) must be low at illegal counts 110 and 111. The output Y as a function of C, B and A is simplified as follows: Y BA

BA

BA

BA

C

1

1

1

1

C

1

1

0

0

Y=CB Y = C + B (OR gate)

Q44 (d) A mod 6 counter has the state diagram as shown below. 0

1

2

5

4

3

The state table is constructed below. Decimal Flip Flop Outputs d A B C 0 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1

Flip Flop Inputs JA KA JB KB 0 × 0 × 0 × 1 × 0 × × 0 1 × × 1 × 0 0 × × 1 0 ×

JC 1 × 1 × 1 ×

KC × 1 × 1 × 1

GATE Solutions

72

Mechasoft

Symbol (×) denotes don't care condition. Note that JC and KC are never 0. So, JC = KC =1 JA

KA

BC A

0

A

×

BC

BC

0

BC

1

×

×

BC

0

×

BC

BC

A

×

×

×

×

A

0

1

×

×

KA = C

JA = BC

JB

BC

KB BC

BC

BC

BC

A

0

1

×

×

A

0

0

×

×

BC

BC

A

×

×

1

0

A

×

×

×

×

J B = AC

BC

BC

KB = C

Using the expressions for JA , KA , JB , KB , JC and KC derived just above circuit diagram is Combinational circuit sketched below.

JA

A

JB

B

1

JC

C

KA

A

KB

B

1

KC

C

Clk

The combination circuit consists of two AND gates. Q45(b)Worst case delay in n- bit ripple counter is n tp and that in synchronous counter is tp irrespective of number of flip flops being used therein. For n = 4, worst case delay in ripple counter, R = 4 ´ 10 = 40 ns and that in synchronous counter, S = 10 ns.

4

Chapter

ADCs, DACs, Sample and Hold Section1

GATE Questions

Q1. An 8-bit unipolar (all analog output values are positive) digital -to-analog converter (DAC) has a full -scale voltage range from 0V to 7.68V. If the digital input code is 10010110 (the leftmost bit is MSB), then the analog output voltage of the DAC (rounded off to one decimal place ) is ______________V. [GATE 2021/1mark] Q2. A 10-bit D/A converter is calibrated over the full range from 0 to 10V .If the input to the D/A converter is 13A(in hex ), the output (rounded of to three decimal places) is ___________V. [GATE 2020/1mark] Q3. In an N bit flash ADC, the analog voltage is fed simultaneously to 2N – 1 comparators. The output of the comparators in then encoded to a binary format using digital circuits . Assume that the analog voltage source Vin ( whose output is being converted to digital format ) has a source resistance of 75 Ω as shown in the circuit diagram below and the input capacitance of each comparator is 8 pF. The input must settle to an accuracy of 1/2 LSB even for a full scale change for proper conversion .Assume that the time taken by the thermometer to binary encoder is negligible. – Vref255

+

Vref2

– +

Thermometer code to binary converter Digital Output

– Vin + -

Vref1

+

If the flash ADC has 8 bit resolution ,which one of the following alternative is closest to the [ Set2/GATE 2016/2marks]

maximum sampling rate in mega sample per second? (a) 1

(b) 6

( c) 64

(d)256

Q4. Consider a four bit D to A converter. The analog value corresponding to a digital signals of value 0000 and 0001 are 0 V and 0.0625 V respectively. The analog value (in volts) corresponding to the digital signal 1111 is______. [ Set1/GATE 2015/1mark]

GATE Questions

74

Mechasoft

Q 5. An analog voltage in the range 0 to 8 V is divided in 16 equal intervals for conversion to 4-bit digital output. The maximum quantization error (in V) is ___________________. [ Set3/GATE 2014/1mark] Q 6. For a given sample-and-hold circuit, if the value of the hold capacitor is increased, then (a) droop rate decreases and acquisition time decreases. (b) droop rate decreases and acquisition time increases. (c) droop rate increases and acquisition time decreases. (d) droop rate increases and acquisition time increases. [ Set4/GATE 2014/1mark] Q7. The output of a 3-stage Johnson(twisted-ring) counter is fed to a digital-to-analog(D/A) converter as shown in the figure below. Assume all states of the counter to be unset initially. The waveform which represents the D/A converter output V0 is D/A Converter D2 D1 D0

Vref

Clock V0

V0

Q2 Q1 Q0 Johnson Counter V0

(a)

(b)

t

t

V0

V0

( c)

(d)

t

t

[GATE 2011/2marks]

GATE Questions

Mechasoft

75

Statements for Q8 & Q9 In the following circuit, the comparator output is logic “1” if VDAC < Vin and is logic “0” otherwise. The D/A conversion is done as per the relation 3

VDAC = å 2n-1 b n volts, where b3 (MSB), b2, b1 and b0 (LSB) are the counter outputs. n=0

The counter starts from the clear state. V DAC

4 -bit D A converter

–

Clr

4-bit up counter

+ Vin = 62 . V

2 Digit

Binary to BCD

+ 5V

Clk

LED Display

[GATE 2008/2marks]

Clock

Q8.The stable reading of the LED displays, is (a) 06 (b) 13 (c) 12

(d) 07

Q9.The magnitude of the error between VDAC and Vin at steady state (in volts) is (a) 0.2 (b) 0.3 (c) 0.5 (d) 1.0 Statement for Linked Answer Questions Q10 & Q11 In the Digital-to-Analog converter circuit shown in the figure below, VR = 10V and R = 10 KW. R

R

R

i

2R

VR 2R

2R

2R

2R R – +

V0

[GATE 2007/2marks]

GATE Questions

76 Q10.The current i is (a) 31.25 mA

(b) 62.5 mA

Q11.The voltage V0 is (a) − 0.781 V (b) −1.562 V

Mechasoft

(c) 125 mA

(d) 250 mA

(c) −3.125 V

(d) −6.250 V

Q12. A 4 bit D/A converter is connected to a free running 3 bit UP counter, as shown in the following figure. In the figure shown below, the ground has been shown by the symbol Ñ.

Clock

Q2

D3

Q1 Q0

D2 D1 D0 D /A converter

3 + bit counter

1 KΩ – v0

+ 1KΩ

Which of the following waveforms will be observed at v0?

(a)

(b)

( c)

(d)

[GATE 2007/2marks] Q13.The minimum number of comparators required to build an 8-bits flash ADC is (a) 8 (b) 63 (c) 255 (d) 256

[GATE 2003/1mark]

GATE Questions

Mechasoft

Q14.The circuit shown in the figure is a 4 bit DAC. The input bits 0 and 1 are represented by 0 and 5 V respectively. The OP AMP is ideal, but all the resistance and the 5V inputs have a tolerance of ±10%. The specification (rounded to nearest multiple of 5%) for the tolerance of the DAC is

(a) ±35%

(b) ±20%

77

R

b3 b2

R

2R –

4R

b1 b0

Vout

+ 8R

R

(c) ±10%

(d) ±5% [GATE 2003/2marks]

Answer Key Q1 Q8

(4.5) (b)

Q2 Q9

(3.07) Q3 (b) Q10

(a) (b)

Q4   (0.9375) Q5 Q11 (c) Q12

Mechasoft

(0.25) Q6 (b) Q13

(b) (c)

Q7 Q14

(a) (a)

GATE Solutions

Section2 Q1. Step size , S =

VFS 7.68 7.68 = = and (10010110)2 = (150)10 2n –1 28 –1 255

The output of DAC is v0,DAC = 5 ´ (decimal equivalent of digital input) = 150 ´ Q2. A 10-bit DAC has step size , S =

VFS 10

2 –1

(

=

10 1023

13A hex = 0001 0011 10102 = 1 ´ 16 + 3 ´ 16 + 10 ´ 160 Output = 314 ´ S =

7.68 = 4.5V 255

2

)

10

= 314 10

314 ´ 10

= 3.07V 1023 Q3. For full scale input change, that is, Vin =Vref , all comparators will generate high output and there will be 255 capacitors each of value 8pF, in parallel resulting in effective input capacitance C=255× 8pF. The effective time constant ꞇ=Rs C=75×255×8×10–12sec. 1 1 V V It is required that input must settle to an accuracy of ´ LSB = ´ ref = ref for even full scale change within 8 2 2 2 512 such sampling period ,t8 . V æ 1 ö – t /t Thus , Vref – Vref [1 – e s ] £ ref Þ –ts £ t In ç è 512 ÷ø 512 –ts £ 75 ´ 255 ´ 8 ´ 10–12 In(512)–1 Þ –ts £ – 0.954463 ´ 10–6 ts ³ 0.954463 ´ 10–6 and sampling rate fs £ 1.048 ´ 106 The maximum sampling rate is close to1 mega samples per second.

Q4. Let the four word b3b2b1b0 the input to DAC and the reference voltage be V8.The analog output voltage, V0 =

VR n

[b3 23 + b2 22 + b1 21 + b0 20 ] ; n = 4

2 For b3 b2 b1 b0 = 0001 , V0 = 0.0625V gives

0.0625 =

VR 24

[0 ´ 23 + 0 ´ 22 + 0 ´ 21 + 1 ´ 20 ] Þ VR = 1V

1 [1 ´ 24 + 1 ´ 22 + 1 ´ 21 + 1 ´ 20 ] = 0.9375V 24 Alernatively , V0 µ decimal equivalent of binary word . For b3 b2 b1 b0 = 1111 , V0 =

Form the ratio

V 01 V02

=

decimal equivalent of binary word 0001 decimal equivalent of binary word 1111

=

1 15

to get V02 = 15V01 = 15 ´ 0.0625 = 0.9375V.

Q5. Number of quantization levels, Q = 16 and step size, S =

Maximum quantization error, q e max =

S 2

=

0.5 2

= 0.25V

8 16

= 0.5V

GATE Solutions

Mechasoft Q6( b)

79

sample and hold circuit – OA1 +

Va

– OA 2 +

t C

control signal

When the switch closes for small duration ꞇ under the influence of control signal, the capacitor charges to input voltage Va and when the switch is open, the capacitor holds the input voltage. OA1 used as input buffer (unity gain amplifier) providing very low output impedance R0, allows the capacitor to charge rapidly to input voltage with small time constant R0C. OA2 used again as buffer providing large input impedance R i, disallows the capacitor to discharge appreciably, the discharge time constant being R iC. The amount of time taken by capacitor to charge to input voltage is called acquisition time. The pulse width (ꞇ) of control signal should not be smaller than acquisition time. The rate at which capacitor discharges during hold time, is called droop rate. Increasing value of capacitor, the charging and discharging both time constants increase whereby the capacitor takes larger time to charge and also to discharge. So, increased value of capacitor, decreases droop rate and increases acquisition time. Q7 (a) The state diagram of a 3 - bit Johnson counter is depicted below. 000

100

110

111 V0

001

011 Ü

0

4

6

1

7

DAC output waveform

7 6 5 4 3 2 1 0

t

3 3

Q8 (b) VDAC = å 2n-1 b n = 22 b3 + 21 b 2 + 20 b1 + 2 –1 b 0 = 4b3 + 2b 2 + b1 + n=0

DAC step size =

1 = 0.5V 2

b0 2

GATE Solutions

80

Mechasoft

As long as VDAC < Vin, the counter counts from 0(0000) to 15(1111).When VDAC > Vin , clock is disabled and counter stops counting. The count at which 4- bit counter stops is 1101 as demonstrated below. At binary count 1101, the DAC output VDAC = decimal equivalent ´ step size = 13 ´ 0.5 = 6.5V 1 1 0 1 ← digital output DAC output = 6.5V > Vin ← counter stops LED display = 13 (on applying binary 1101 to BCD converter). Q9 (b) Steady state error = DAC output − Vin = 6.5 − 6.2 = 0.3 V i1

Q10 (b)VR

i3 i2

Req= R = 10kU

R

i5 i4

2R

i1 =

R

R

R

i

2R

i8

2R

2R

R

i7 i6

2R

R

R i9 0

– +

i9 V0

VG

VR 10V = = 1mA R eq 10kΩ

i1 = 0.5mA = 500μA 2 i i 4 = i5 = 3 = 250μA 2 i i 6 = i 7 = 5 = 125μA 2 i i = i8 = 7 = 62.5μA 2 i 2 = i3 =

Q11 (c) i9 = i 4 + i8 = (250 + 62.5)μA = 312.5μA and

i9 =

0 – V0 Þ V0 = –i9 × R = 312.5×10 –6 ×10×103 = –3.125V R

GATE Solutions

81 Q 12(b) Excutation table for 8 clocks Clock Q2 Q1 Q0 D3 D2 D1 D0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 2 0 1 0 0 0 1 0 3 0 1 1 0 0 1 1 4 1 0 0 1 0 0 0 5 1 0 1 1 0 0 1 6 1 1 0 1 0 1 0 7 1 1 1 1 0 1 1 8 0 0 0 0 0 0 0

decimal 0 1 2 3 8 9 10 11 0

Mechasoft 11 10 9 8 7 6 5 4 3 2 1 0

t n

Q13 (c) Minimum number of comparators to build n -bit flash ADC = 2 −1. For n = 8 ; 28 −1 = 255. R R R R ù Q14(a) Vout = –VR éê b3 + b2 + b1 + b 0 ;VR = 5V 2R 4R 8R úû ëR é 1 1 1ù Nominal Vout for b3 b 2 b1 b 0 = 1111 is calculated as Vout = –5 ê1+ + + ú = 9.375V ë 2 4 8û

In the worst case maximum value of Vout can be estimated by increasing VR and R appearing in numerator by 10% together with decreasing R appearing in denominator by 10% as 110 é 1 1 1 ù 1 + + + = 12.6 V 90 êë 2 4 8 úû 12.6 - 9.375 % tolerance of DAC = ± ´ 100 = ± 34.4% @ 35% 9.375 Vout = -5.5 ´

5

Chapter

CMOS Synthesis Section1

GATE Questions

Q1. A standard CMOS inverter is designed with equal rise and fall times βn=βp . If the width of the pMOS transistor in the inverter is increased, what would be the effect on the LOW noise margin (N ML) and the HIGH noise margin N MH ? [GATE 2019/1mark] (a)NML, increases and NMH decreases. (b)NML decreases and NMH increases. (c)Both NMLand NMH increase. (d) No change in the noise margins Q2. In the circuit shown, what are the values of F for EN = 0 and EN = 1, respectively? Vdd

(a) 0 and D (b) Hi-Z and D

EN

(c) 0 and 1

F

(d) Hi-Z and D̅ [GATE 2019/1mark]

D

Q3. In the circuit shown, A and B are the inputs and F is the output. What is the functionality of

the circuit?

Vdd

(a) Latch (b) XNOR ( c) SRAM Cell

F

(d) XOR A

B

[GATE 2019/1mark]

GATE Questions

84

Mechasoft

Q4. The logic function f(X, Y) realized by the given circuit is (a) NOR

VDD

X

X

Y

Y

(b) AND

f(X, Y)

( c) NAND (d) XOR

[GATE 2018/1mark]

Q5. What is the voltage V out in the following circuit? VDD

(a) 0V (b) (|VTof PMOS | +VT of NMOS)/2

Vout

10kΩ

( c) Switching threshold (d) VDD

[Set1/GATE 2016/1mark] Q6. Transistor geometries in a CMOS inverter have been adjusted to meet the requirement for worst case charge and discharge times for driving a load capacitor C. This design is to be converted to that of a NOR circuits in the same technology , so that its worst case charge and discharge times while driving the same capacitor are similar . The channel lengths of all transistors are to be kept unchanged. Which one of the following statements is correct? VDD

VDD

In

In2

out

In1 C

Out C

(a)Widths of PMOS transistors should be doubled , while widths of NMOS transistors should be halved. (b) Widths of PMOS transistors should be doubled , while widths of NMOS transistors should not be changed . (c) Widths of PMOS transistors should be halved, while widths of NMOS transistors should not be changed. (d)Widths of PMOS transistors should be unchanged, while widths of NMOS transistors should be halved. [Set2/GATE 2016/1mark]

GATE Questions Mechasoft Q7. The logic functionality realized by the circuit shown in figure is (a) OR

(b)XOR

( c) NAND

(d) AND

85 B

B

A Y

[Set3/GATE 2016/1mark] Q8. In the following circuit employing pass transistor logic, all NMOS transistors are identical with a threshold voltage of 1V. Ignoring the body-effect, the output voltages at P, Q and R are, (a) 4V, 3V, 2V 5V 5V 5V (b) 5V, 5V, 5V 5V P

(c) 4V, 4V, 4V

Q

R

(d) 5V, 4V, 3V [Set1/GATE 2014/1mark] Q9. The output (Y) of the circuit shown in the figure is +VDD

(a) A + B + C A

B

C

(b) A + B C + A C A

Output (Y)

( c) A + B + C B

(d) A B C C

[Set4/GATE 2014/1mark]

GATE Questions

86 Q10.In the circuit shown

Mechasoft

5 Volts A

(a) Y = AB + C (b) Y = (A + B)C ( c) Y= (A+B) C (d) Y= AB + C

C B Y C A

[GATE 2012 /1mark]

B

Q11.The full forms of the abbreviations TTL and CMOS in reference to logic families are (a) Triple Transistor Logic and Chip Metal Oxide Semiconductor. (b) Tristate Transistor logic and Chip Metal Oxide Semiconductor. ( c) Transistor Transistor Logic and Complementary Metal Oxide Semiconductor. (d) Tristate Transistor Logic and Complementary Metal Oxide Silicon. [GATE 2009 /1mark] Q12.The logic function implemented by the following circuit at the terminal Out is +VDD (a) P (b) P (c) P (d) P

NOR Q NAND Q OR Q AND Q

Out

S P

Q [GATE 2008 /2marks] VCC = 5V

Q13. The circuit diagram of a standard TTL NOT gate is shown in the figure. Vi = 2.5 V, the modes of operation of the transistors will be

4kW

1.4kW

100kW Q4

+

Q2

Q1

D + Q3

Vi 1kW –

–

[GATE 2007 /2marks]

GATE Questions

Mechasoft

87

(a) Q1: reverse active; Q2: normal active; Q3 : saturation; Q4 : cut-off (b) Q1: reverse active; Q2: saturation; Q3: saturation; Q4: cut-off ( c) Q1: normal active ; Q2: cut-off ; Q3: cut-off ; Q4: saturation (d) Q1: saturation; Q2:saturation; Q3: saturation ; Q4: normal active Q14.The transistors used in a portion of + 5V the TTL gate shown in the figure have b= 100. The base emitter voltage is 0.7 V 4k Ω for a transistor in active region and 0.75 V for a transistor in saturation. If the sink current I = 1mA and the output is at logic 0, then the current IR will be equal to 1k Ω (a) 0.65 mA

1.4 k Ω

I V0

IR

(b) 0.70 mA

[GATE 2005/1mark] ( c)0.75 mA (d) 1.00 mA Q15.The output of the 74 series of TTL gates is taken from a BJT in (a) totem pole and common collector configuration. (b) either totem pole or open collector configuration. (c) common base configuration. (d) common collector configuration. [GATE 2003/1mark] Q16.The DTL, TTL, ECL and CMOS families of digital ICs are compared in the following 4 columns. (P) (Q) (R) (S) Fan out is minimum

DTL

DTL

TTL

CMOS

Power consumption is minimum

TTL

CMOS

ECL

DTL

CMOS

ECL

TTL

TTL

Propagation delay is minimum The correct column is (a) P

(b) Q

(c) R

(d) S [GATE 2002/1mark]

Answer Key Q1 Q8 Q15

(a) (c) (b)

Q2 Q9 Q16

(b) Q3 (a) Q10 (b)

(b) (a)

Q4 Q11

(d) Q5 (c) Q12

Mechasoft

(c) (a)

Q6 Q13

(b) Q7 (b) Q14

(d) (c)

GATE Solutions

Section2 Q1(a) NML = VIL–V0L and NMH = V0H–VIH

V0 V VOH DD

æ Wö æ Wö çè ÷ø = çè ÷ø L p L n

æ Wö æ Wö çè ÷ø > çè ÷ø L p L n

VOL 0

VIH VIL VIL* VIH* VDD/2

Vi

switching threshold

A CMOS inverter designed with equal rise and fall time ( b n = b p ) has switching threshold VTH =0.5 VDD , that is , at mid point of logic swing. If the width of PMOS, is increased ( Wp >Wn ) the PMOS has larger current driving capability and switching threshold shifts towards input voltage Vi > 0.5VDD.This shift causes both VILand VIH to increase , that is, V*IL>VIL and V*IH >VIH Thus, NML increases and NMH decreases as demonstrated above. Q2(b) Note that X = D.EN and Y = D + EN = D.EN For EN=0 , X=1 and Y =0 M1and M2 both transistors will be off and output F will be in high impedance (Hi-Z) state. When EN=1 ,X= Y=D Then , F =1 when M1 turns on for X=0 or D = 1while F=0 when M2 turns on for Y=1 or D = 0. Thus , F=D for EN=1. Vdd X M1

EN

F

D

M2 Y

GATE Solutions

Mechasoft Q3 (b)

89

Vdd Vdd

B

MP1

F

F Mn1

0 0 1 1

B

Mn2

A

A

Output

B

MP1 MP2 Mn1 Mn2

F

0 1 0 1

on off on off

off off on on

A B

1 0 0 1

F = AeB

Q4(d) PUN ≡ Pull UP Network, PDN ≡ Pull Down Network X 0 0 1 1

Y 0 1 0 1

f 0 1 1 0

QP1 QP2 off on off off on on on off

QP3 QP4 Qn1 Qn2 on off on on on on on off off off off on off on off off

Mn2

B

A

State of Transistors

off on off on

A

Mn1

B

on on off off

MP2

A

MP2

Input

MP1

VDD

PUN, all PMOS

X

QP1

QP3

X

Y

QP2

QP4

Y

Qn3 Qn4 off off on on

off on

f(X, Y)

off on

Qn1

Qn3

Qn2

Qn4

PDN, all NMOS Vdd

Q5( c) VGD=0 for both PMOS and NMOS VT of NMOS> 0 and VT of PMOS < 0 NMOS is in saturation ,VGD