Silicon Semiconductor Technology: Processing and Integration of Microelectronic Devices 365841040X, 9783658410407

Citation preview

Ulrich Hilleringmann

Silicon Semiconductor Technology Processing and Integration of Microelectronic Devices

Silicon Semiconductor Technology

Ulrich Hilleringmann

Silicon Semiconductor Technology Processing and Integration of Microelectronic Devices

Ulrich Hilleringmann Fakultät für Elektrotechnik, Informatik und Mathematik Universität Paderborn Paderborn, Germany

ISBN 978-3-658-41040-7 ISBN 978-3-658-41041-4  (eBook) https://doi.org/10.1007/978-3-658-41041-4 © Springer Fachmedien Wiesbaden GmbH, part of Springer Nature 2023 This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. The publisher, the authors, and the editors are safe to assume that the advice and information in this book are believed to be true and accurate at the date of publication. Neither the publisher nor the authors or the editors give a warranty, expressed or implied, with respect to the material contained herein or for any errors or omissions that may have been made. The publisher remains neutral with regard to jurisdictional claims in published maps and institutional affiliations. This Springer Vieweg imprint is published by the registered company Springer Fachmedien Wiesbaden GmbH, part of Springer Nature. The registered company address is: Abraham-Lincoln-Str. 46, 65189 Wiesbaden, Germany

Preface

This book has been used as a study script at German Universities and Universities for Applied Sciences for almost 30 years. It was initially written in German for students in their 3rd year. Still, it was also quickly used to educate apprentices for microtechnologies and qualifying employers in industrial integrated circuit facilities. Due to its success in Germany, Austria, and Switzerland, the translation into the English language will now enable a larger international audience. The book’s content starts from basic knowledge of individual process steps in silicon technology and extends to modern integration techniques for CMOS circuits. Own experiences of the author give detailed information on the physical processes and chemical reactions occurring during the processing of the silicon semiconductor. Besides the theoretical models, the processing equipment used is discussed in detail. It enables self-studies with some included exercises to provide a feeling of the complexity of semiconductor technology. The author thanks all persons who contributed to the success of this book, starting from the study script in 1992 until the 7. edition in 2018. There were more than 100 diploma-, bachelor- and master thesis, and about 20 PhD students involved in assembling smaller or larger parts around silicon processing. Thank you all for your contributions. October 2022

Ulrich Hilleringmann

V

Contents

1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1 4

2

Silicon Wafer Production. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Silicon as Basic Material. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Production and Purification of the Raw Material. . . . . . . . . . . . . . . . . . . 2.2.1 Production of Technical Silicon. . . . . . . . . . . . . . . . . . . . . . . . . 2.2.2 Chemical Purification of the Technical Grade Silicon. . . . . . . . 2.2.3 Zone Purification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Production of Single Crystals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.1 The Crystal Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.2 Crystal Pulling Method According to Czochralski . . . . . . . . . . 2.3.3 Crucible-Free Zone Pulling. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.4 Crystal Defects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Crystal Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.1 Dicing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.2 Surface Treatment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 Tasks for Slice Production. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5 5 7 7 8 9 10 10 12 14 15 16 16 17 19 20

3

Oxidation of Silicon. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Thermal Oxidation of Silicon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.1 Dry Oxidation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.2 Wet Oxidation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.3 H2O2 Combustion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Modelling of the Oxidation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 The SiO2/Silicon Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Segregation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

21 22 23 23 24 25 27 28

VII

VIII

Contents

3.5

Deposition Processes for Silicon Dioxide. . . . . . . . . . . . . . . . . . . . . . . . 3.5.1 Silane Pyrolysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.2 TEOS Oxide Deposition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 Tasks for the Oxidation of Silicon. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

30 30 31 31 32

4 Lithography. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Mask Technique. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.1 Pattern Generator and Step-And-Repeat Exposure. . . . . . . . . . 4.1.2 Direct Writing of the Mask with the Electron Beam. . . . . . . . . 4.1.3 Mask Techniques for Highest Resolutions. . . . . . . . . . . . . . . . . 4.2 Resist Coating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.1 Structure of the Photoresists . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.2 Deposition of the Photoresist Layer. . . . . . . . . . . . . . . . . . . . . . 4.3 Exposure Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.1 Optical Lithography (Photolithography). . . . . . . . . . . . . . . . . . 4.3.2 Electron Beam Lithography. . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.3 X-ray Lithography. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.4 Further Procedures for Structuring . . . . . . . . . . . . . . . . . . . . . . 4.4 Resist Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.1 Developing and Curing the Photoresist. . . . . . . . . . . . . . . . . . . 4.4.2 Line Width Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.3 Removing the Resist Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 Lithography Tasks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

33 34 35 35 36 37 37 38 40 40 47 50 51 54 54 55 56 58 58

5

59 60 61 61 61 64 65 67 73 73 75 76 76 77 77 78 78

Etching Technology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 Wet Chemical Etching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.1 Dip Etching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.2 Spray Etching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.3 Etching Solutions for Wet-Chemical Structuring . . . . . . . . . . . 5.2 Dry Etching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.1 Plasma Etching (PE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.2 Reactive Ion Etching (RIE). . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.3 Ion Beam Etching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.4 Dry Etching Process for High Etch Rates. . . . . . . . . . . . . . . . . 5.2.5 Atomic Layer Etching (ALE) . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 Endpoint Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.1 Visual Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.2 Ellipsometry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.3 Optical Spectroscopy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.4 Interferometry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.5 Mass Spectrometry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents

5.4 Etching Tasks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IX

78 79

6

Doping Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.1 Alloying. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.2 Diffusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.2.1 Fick’s Laws . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.2.2 Diffusion Process. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.2.3 Implementation of the Diffusion Process. . . . . . . . . . . . . . . . . . 90 6.2.4 Limitations of the Diffusion Technique. . . . . . . . . . . . . . . . . . . 91 6.3 Ion Implantation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.3.1 Range of Implanted Ions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.3.2 Channeling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 6.3.3 Activation of the Dopants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 6.3.4 Technical Design of an Ion Implanter. . . . . . . . . . . . . . . . . . . . 97 6.3.5 Characteristics of Implantation . . . . . . . . . . . . . . . . . . . . . . . . . 100 6.4 Tasks for the Doping Techniques. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

7

Deposition Process. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 Chemical Deposition Processes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.1 The Silicon Gas-Phase Epitaxy. . . . . . . . . . . . . . . . . . . . . . . . . 7.1.2 The CVD Process for Layer Deposition . . . . . . . . . . . . . . . . . . 7.1.3 Atomic Layer Deposition (ALD). . . . . . . . . . . . . . . . . . . . . . . . 7.2 Physical Deposition Processes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.1 Molecular Beam Epitaxy (MBE). . . . . . . . . . . . . . . . . . . . . . . . 7.2.2 Evaporation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.3 Sputtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3 Tasks for the Separation Techniques. . . . . . . . . . . . . . . . . . . . . . . . . . . . References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

103 103 103 106 112 114 114 115 117 120 121

8

Metallization and Contacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1 The Metal–Semiconductor Contact. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2 Multi-Layer Wiring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.1 Planarisation Techniques. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.2 Filling Contact Openings and Vias . . . . . . . . . . . . . . . . . . . . . . 8.3 Reliability of Aluminium Metallization. . . . . . . . . . . . . . . . . . . . . . . . . . 8.4 Copper Metallization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.5 Metallization Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

123 124 127 128 132 133 134 137 138

X

9

Contents

Wafer Cleaning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1 Impurities and Their Effects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.1 Microscopic Impurities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.2 Molecular Impurities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.3 Alkaline and Atomic Impurities. . . . . . . . . . . . . . . . . . . . . . . . . 9.2 Cleaning Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3 Etching Solutions for Substrate Cleaning . . . . . . . . . . . . . . . . . . . . . . . . 9.4 Example of a Cleaning Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.5 Tasks for Substrate Cleaning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

139 140 141 141 142 143 144 145 146 147

10 MOS Technologies for Circuit Integration. . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1 Single-Channel MOS Techniques. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.1 The PMOS Aluminium Gate Process . . . . . . . . . . . . . . . . . . . . 10.1.2 The n-Channel Aluminium Gate MOS Technique. . . . . . . . . . . 10.1.3 The n-Channel Silicon Gate MOS Technology. . . . . . . . . . . . . 10.2 The n-Well Silicon Gate CMOS Process. . . . . . . . . . . . . . . . . . . . . . . . . 10.2.1 Circuit Elements of the CMOS Technology . . . . . . . . . . . . . . . 10.2.2 Latchup Effect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3 Test and Parameter Acquisition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4 Tasks for the MOS Technique. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

149 150 150 152 155 158 164 168 171 172 174

11 Developments for High-Density Integrated Circuits. . . . . . . . . . . . . . . . . . . 11.1 Local Oxidation of Silicon (LOCOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.1 The Simple Local Oxidation of Silicon. . . . . . . . . . . . . . . . . . . 11.1.2 SPOT Technique for Local Oxidation. . . . . . . . . . . . . . . . . . . . 11.1.3 The SILO Technique. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.4 Poly-Buffered LOCOS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.5 The SWAMI LOCOS Technique. . . . . . . . . . . . . . . . . . . . . . . . 11.1.6 Trench Isolation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 Advanced MOS Transistors for High-Density Integrated Circuits . . . . . 11.2.1 Breakdown Mechanisms in MOS Transistors. . . . . . . . . . . . . . 11.2.2 The Spacer Technique for Doping Optimisation. . . . . . . . . . . . 11.2.3 Self-Aligned Contacts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3 SOI Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3.1 SOI Substrates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3.2 Process Control in SOI Technology. . . . . . . . . . . . . . . . . . . . . .

175 175 176 178 179 180 181 184 185 187 189 195 197 197 204

Contents

XI

11.4 Transistors with Nanometer Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . 11.4.1 Requirements for Further Scaling. . . . . . . . . . . . . . . . . . . . . . . 11.4.2 Analysis of Nanometer-Scale n-type Field-Effect Transistors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4.3 The FINFET in SOI Technology. . . . . . . . . . . . . . . . . . . . . . . . 11.4.4 FINFET in the Standard Silicon Substrate. . . . . . . . . . . . . . . . . 11.5 Tasks for High-Density Integrated Circuits. . . . . . . . . . . . . . . . . . . . . . . References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

205 205

12 Bipolar Technology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1 The Standard Buried Collector Technique. . . . . . . . . . . . . . . . . . . . . . . . 12.2 Advanced SBC Technique. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3 Bipolar Process with Self-Aligned Emitter. . . . . . . . . . . . . . . . . . . . . . . 12.4 BiCMOS Techniques. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5 Bipolar Technology Tasks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

215 216 218 219 222 224 224

13 Packaging of Integrated Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.1 Preparing the Wafers for Packaging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.1.1 Reducing the Wafer Thickness. . . . . . . . . . . . . . . . . . . . . . . . . . 13.1.2 Reverse Side Metallization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.1.3 Separation of the Chips. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2 Assembly. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2.1 Substrates/System Carriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2.2 Die Bonding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3 Electrical Contacts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3.1 Single Wire Bonding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3.2 Simultaneous Contacting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4 Finishing the Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.5 Chip Assembly Tasks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

225 226 226 227 227 229 229 231 233 233 238 243 244 244

208 209 210 211 212

Annexes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

1

Introduction

The development in microelectronics impressively demonstrates the continuously increasing performance of semiconductor technology. It started with the development of the first transistor in 1948, followed by the first integrated circuit with only four transistors in 1962, up to memory components with a capacity of several Gbit per chip today. Minimum feature sizes below 10 nm, considered unattainable just a few years ago, are currently used in production. Although often proposed, an end of miniaturisation is not yet in sight.1 The elemental semiconductor silicon almost exclusively serves as the base material for integrated circuits and transistor components. Silicon is a cheap material with excellent electrical and mechanical performance. Especially its specific oxide, which depicts high breakdown voltages, can be easily created in nearly perfect quality. Germanium as another elementary semiconductor, and the III/V or II/VI compound semiconductors GaAs, InP, GaP, CdS, CdSe, etc., play a minor—but not insignificant— role in microelectronics. They are preferred for optoelectronic applications or used at the highest switching speeds, but not in the field of low-power, high-density integrated circuits. Besides cost aspects, their inadequate crystal quality and mechanical properties, such as the limited mechanical stability during processing, negatively affect them. High-density integrated circuits are made almost exclusively from silicon due to the favourable material properties in combination with sophisticated processing technology. Mainly, it includes the comparatively simple conversion of the silicon surface into a high-quality, extremely durable insulator by thermal oxidation. There are three sub-areas to be worked on to produce an integrated circuit:

1 INTERNATIONAL

ROADMAP FOR DEVICES AND SYSTEMS™, 2020 UPDATE, MORE MOORE, IEEE 2021, https://irds.ieee.org/images/files/pdf/2020/2020IRDS_MM.pdf, Upload on 11.05.2022. © Springer Fachmedien Wiesbaden GmbH, part of Springer Nature 2023 U. Hilleringmann, Silicon Semiconductor Technology, https://doi.org/10.1007/978-3-658-41041-4_1

1

2

1 Introduction

• Production of the uniformly doped silicon wafer (wafer or disc production); • Integration of electrical functions using planar technology (so-called “front end”); • Assembly of the microelectronic circuits in housings (“back end” or “packaging”). Planar technology is the basis for realising the electrical functions of an integrated circuit. It contains a sequence of individual processes that act simultaneously on the entire surface of the wafer. Planar technology enables local changes in the semiconductor material or on top of the wafer surface via suitable masking layers like photoresists. To demonstrate the meaning and the interaction of the different individual processes, which are explained in more detail in chap. 3–9, a chronological sequence of the planar technique is given below. The starting point is a uniformly doped wafer, which is affected by the following processing steps (Fig. 1.1): • Creation of a metal or oxide layer on the silicon wafer surface; • Application of a light-sensitive resin called photoresist; • Exposing the photoresist through a mask with the structure of a design plane of the integrated circuit; • Development, which means removing the exposed photoresist areas; • Etching the metal or oxide with the photoresist as a masking layer; • Removal of the remaining photoresist in an etching step; • Diffusion for local doping of the silicon wafer with oxide as a masking layer. This processing sequence is repeated several times during the device integration. It enables local changes in the wafer’s doping level in a targeted manner or to structure different functional layers on the wafer surface. After all doping atoms have been introduced

Fig. 1.1   Planar technique for generating local structures or doping at the surface of a homogeneous silicon wafer

1 Introduction

3

into the crystal, the planar technique ends with the wiring for making the electrical connections: • Deposition of aluminium on the wafer surface creates conductor tracks and contact areas; • Structuring the metal level by applying an etching process masked with a photoresist. The planar technology thus enables the production of identical structures continuously repeated on the entire wafer surface. It facilitates local doping variations by adding doping atoms to increase the substrate doping or to do a counter doping, as it is necessary to integrate individual semiconductors and microelectronic circuits. At the final stage, wafers with some hundred or thousand circuits are ready to be electrically tested according to their analogue or logical operation. The application of the individual integrated device demands a well-defined electrical contact structure and protection of the integrated circuits against ambient influences. According to this request, the silicon wafer is separated into single dies, followed by assembling the integrated circuits into a normalised package. The package establishes standardised electrical connections for further applications. In this study script, all necessary individual processes of microelectronic integration technology are briefly described. A comparison with alternative approaches in the integration course is discussed in detail. The merging of the various techniques follows to form overall processes for MOS (“Metal-Oxide-Semiconductor”) and bipolar transistor integration. The more complex procedures of modern semiconductor technology are explained with the local oxidation processes, the spacer technology, the self-aligned contacts, and the SOI (“Silicon on Insulator”) substrates. In addition, the book gives additional insights into the current developments in semiconductor process technology. For example, CMP (“Chemical-Mechanical Polishing”) is required for surface planarisation in the space-saving STI (“Shallow Trench Isolation”) technology and multi-layer wiring. At the same time, this process step enables copper metallisation using Damascene technology. ALD (“Atomic layer deposition”) is used today for the precisely controlled deposition of ultra-thin insulator layers. This process is also suitable for producing thin conductive metal nitrides in copper metallisation. Further developments aim in the direction of three-dimensional integration. One example is the FINFET transistor, which is now manufactured using substrate and SOI technology. Alternatively, 3D structures can be produced using thinly bevelled silicon dies with advanced assembly and connection technology. These are stacked on one another and electrically connected via TSV (“Through Silicon Vias”).

4

1 Introduction

1.1 Exercises Task 1.1 Starting with 2-inch wafers in the early days of semiconductor technology, the diameter of silicon wafers has grown to up to 300 mm (12 inches) today (Fig. 1.2). Calculate the increase in the area based on 3-inch wafers over 100 mm, 150 mm, 200 mm up to 300 mm! How many complete chips with a size of 10 × 10 mm2 can each be integrated into these silicon wafers? Task 1.2 How does the number of complete dies per wafer change for the wafer diameters mentioned above using a chip size of 30 × 30 mm2? Fig. 1.2   Silicon wafers with different cross-sections: 2”, 3”, 100 mm, 200 mm, and 300 mm. (Photo: A. Rutenburges)

2

Silicon Wafer Production

2.1 Silicon as Basic Material The element silicon has gained the most significant importance as the starting material for individual semiconductor components and integrated circuits. Microprocessors, memory chips, logic circuits, and application-specific circuits (ASIC) are almost exclusively manufactured in the silicon substrate. Power semiconductors such as thyristors, IGBT (Insulated Gate Bipolar Transistor), and many individual transistors or diodes also use this element as the primary semiconducting material. The following section explains why silicon became the most important material of microelectronics, especially for integrating the MOS devices controlled by an electric field. As far as only high switching speeds are concerned, i.e. the mobility (Table 2.1) of the free charge carriers, other materials such as germanium and especially gallium arsenide offer much higher charge carrier mobilities. In contrast to germanium and gallium, silicon is available in almost unlimited quantities. It is the second most abundant elemental component of the earth’s crust after oxygen, accounting for 27.72 wt%. Accordingly, it is an inexpensive starting material whose price is only determined by purification and processing into single-crystal rods or wafers. Silicon already reacts with oxygen at room temperature to form SiO2, the silicon dioxide. SiO2 is a high-quality, mechanically and electrically stable insulator that can be selectively and reproducibly applied to the semiconductor employing temperature treatments. This “species-specific” oxide is particularly advantageous for electrical insulation and local masking of the wafer surface during the manufacture of integrated circuits. In contrast, producing a high-quality insulator with good dielectric properties on the semiconductor materials mentioned above is complicated and cost-intensive. Inherent oxides are either of low quality or technically not reproducible to grow, so silicon dioxide is used here too. © Springer Fachmedien Wiesbaden GmbH, part of Springer Nature 2023 U. Hilleringmann, Silicon Semiconductor Technology, https://doi.org/10.1007/978-3-658-41041-4_2

5

2  Silicon Wafer Production

6 Table 2.1  Charge carrier mobilities in cm2/Vs

Charge carrier

Silicon

Germanium

Gallium Arsenide

Electrons

1350

3900

8500

Holes

450

1900

400

Silicon is a semiconductor with an electrical resistance between a poor conductor and an insulator in its pure state. The resistance or conductivity of silicon can be influenced over several orders of magnitude by adding specific impurities (doping). Instead of silicon atoms (4 valence electrons), so-called doping atoms with three or five valence electrons are introduced into the crystal. Atoms with five valence electrons are called donors (Fig. 2.1). They donate one electron, which does not contribute to the covalent bonds in the lattice, into the conduction band of the semiconductor. In this case, the silicon acquires an n-type character with free electrons as mobile charge carriers. Typical dopants are the donor elements phosphorus (P), arsenic (As) and—less frequently encountered because of its lower solid-state solubility—antimony (Sb). Alternatively, elements with three valence electrons, so-called acceptors, can be added to the crystal structure of the silicon. In this case, one electron per foreign atom is missing to form the complete covalent bond in the lattice. Here an electron out of the semiconductor’s valence band fills the state of the missing binding electron. In total, an unoccupied state remains in the valance band (Fig. 2.2), which leads to defect-electron or hole conduction, and the silicon exhibits p-type conductivity. Descriptively, electrons of neighbouring atoms fill up these bonding defects but leave behind defect electrons themselves. In the case of an electric field, this hopping motion

Fig. 2.1   Two-dimensional representation for incorporating a pentavalent donor atom into the silicon crystal

2.2  Production and Purification of the Raw Material

7

Fig. 2.2   Two-dimensional representation for incorporating a 3-valent acceptor atom into the silicon crystal

of the holes gets a preferred direction. It can be understood as a charge transport through the crystal opposite to the electron motion. The element boron is suitable as a dopant in this case. The other elements of the 3rd main group of the periodic table, aluminium, indium and gallium, also cause p-type doping in silicon, but their use has considerable disadvantages. Aluminium exhibits only moderate solubility in silicon and tends to form agglomerations; the dopant indium is only electrically active to a small extent at room temperature due to the low acceptor level. Gallium atoms already show pronounced diffusion in silicon and silicon dioxide at relatively low temperatures. Various circuit elements such as resistors, diodes, bipolar and MOS transistors can be manufactured by a selective and locally limited silicon doping with donors and acceptors. However, a prerequisite for integrating these semiconductor components and the integrated circuits is a semiconductor material of the highest purity as a perfect single crystal. Impurities, grain boundaries and lattice defects lead to undesired current paths and increased diode leakage currents.

2.2 Production and Purification of the Raw Material 2.2.1 Production of Technical Silicon Elemental silicon is obtained from reducing silicon dioxide (SiO2) in the crystal structure of quartz with carbon as the reaction partner. This process occurs in electric arc furnaces filled with coarse-grained quartz sand and charcoal. It operates above the melting point of silicon (1413 °C) at approximately 1650 °C. In this process, the oxygen bound in the silicon dioxide splits off and reacts with carbon to form carbon monoxide according to the reaction Eq. (2.1): 1650 ◦ C

SiO2 + C −→ Si + 2 CO

(2.1)

Due to its higher density, the liquid silicon is deposited at the bottom of the arc furnace, allowing it to be easily separated from the undissolved silicon dioxide and the gaseous carbon monoxide.

2  Silicon Wafer Production

8

This raw silicon is called technical silicon or “metallurgical grade silicon” (MGS). It is naturally highly contaminated and still contains approximately 2–4% impurities [2], mainly carbon, iron, aluminium, boron and phosphorus. Therefore, it is not yet suitable for electronic devices and circuit integration. Therefore, other chemical processes must follow to produce the required high-purity material.

2.2.2 Chemical Purification of the Technical Grade Silicon The trichlorosilane process is a widely used method to obtain pure silicon, starting from technical silicon as the base material. The raw technical grade silicon is milled to a fine powder and then converted into the chlorine-hydrogen compound trichlorosilane (SiHCl3) at approx. 280–380 °C in HCl-ambient. 300 ◦ C

(2.2)

Si + 3HCl3 −→ SiHCl3 + 2H2

This compound is liquid at temperatures below 31.8 °C. In contrast to SiHCl3, the chlorine compounds of most impurities condense at higher or lower temperatures (Table 2.2). Due to the different condensation temperatures, they can be easily separated from SiHCl3 by fractional distillation. For this purpose, the trichlorosilane is first heated to about 30 °C in the so-called “low boiler” to remove all chemical compounds with a lower boiling temperature by evaporation. Raising the temperature to 32 °C in the “high boiler” leads to evaporation of the trichlorosilane, while all compounds with a higher boiling temperature remain as liquid. Condensation of the trichlorosilane vapour finally yields the high-purity SiHCl3. The condensation temperatures of the chemical compounds PCl3, BCl3 and carbon in the form of pentane are relatively close to that of SiHCl3. Concordant, the main impurities in the distilled SiHCl3 are the dopants phosphorus and boron and the element carbon. By reversing the trichlorosilane process, the silicon can be recovered from the purified SiHCl3. For this purpose, a quartz bell with a heated silicon rod is filled with a gas mixture of trichlorosilane and hydrogen (Fig. 2.3). The resistance-heated, thin silicon rod (approx. 1500 mm in length, 2–5 mm in diameter), a so-called silicon soul, is heated to approximately 1100 °C. At this temperature, the trichlorosilane decomposes and, when hydrogen is added in the ratio SiHCl3:H2 = 1:10, into silicon and hydrogen chloride. The reaction, according to Eq. (2.2), now proceeds in the reverse direction (Eq. 2.3): 1100 ◦ C

(2.3)

SiHCl3 + H2 −→ Si + 3 HCl

Table 2.2  Boiling temperature of some impurities in silicon Substance

BCl3

SiHCl3

CCl4

PCl3

GeCl4

AsCl3

AlCl3

SbCl3

TBP [°C]

12

31.8

76

76

83

132

188

283

2.2  Production and Purification of the Raw Material

9

Fig. 2.3   Reactor for producing polycrystalline silicon rods by thermal decomposition of trichlorosilane

At the same time, hydrogen is released by the dissociation process taking place in parallel according to Eq. (2.4): 1100 ◦ C

4SiHCl3 + H2 −→ Si + 3SiCl4 + 2H2

(2.4)

The elemental silicon is deposited on the silicon core in a polycrystalline form. The soul can grow to a diameter of more than 150 mm. The resulting material has a total purity of 10–9, a boron content of less than 5 × 1012/cm3 and a phosphorus doping of less than 1 × 1013/cm3. This material can already be used as starting material for the Czochralski single crystal growth process (Sect. 2.3.2). However, this degree of purity is only conditionally sufficient for producing, for example, memory and high-voltage components.

2.2.3 Zone Purification In zone purification of silicon, a moving coil fed with a radio-frequency (“RF”) alternating current is placed around the silicon rod. The eddy currents thus induced inside the material heat it locally to the melting point. A liquid zone is created at the location of the RF coil, which can be guided from one end of the rod to the other by moving the coil (Fig. 2.4; [1]). The material outside the plane of the coil remains solid. The melted silicon cannot flow out because of surface tension holding it in place. This process takes place in a high vacuum ambient to avoid impurities from the surrounding atmosphere and molecules or atoms evaporating from the vessel walls (a quartz vessel, for example, leads to enrichment of the material with oxygen). Due to silicon’s high melting temperature, numerous impurities evaporate during this process, leading to

10

2  Silicon Wafer Production

Fig. 2.4   Crucible-free zone cleaning of silicon by exploiting the high solubility of the impurities in the melt

further purification. In addition, a spatial redistribution of impurities also starts in the polycrystalline rod. The solubility of many metals as well as of the dopants boron and phosphorus is higher in the melt than in the crystalline material. During the movement of the coil, these substances stay in the liquid phase area. Finally, the impurities are shifted to the end of the rod [2]. Repeating zone cleaning several times can reduce the total concentration of impurities in the material below the intrinsic conductivity concentration in silicon of about 1.5 × 1010/cm3.

2.3 Production of Single Crystals The current processes in the semiconductor industry are carried out over the entire surface of a thin single-crystalline silicon wafer (also called “disc”, “plate”, or “slice”). It is called the planar technique. Today, wafers with a diameter of 100 mm in research facilities and currently up to a maximum of 300 mm in the industry are 0.45 mm to about 1 mm thick. They are sawn from single silicon crystals with appropriate diameters and polished on the surface for further processing. According to the American Semiconductor Industry Association, future processes will probably be based on wafers with a diameter of 450 mm [3]. Still, the processing facilities have not yet been designed to fulfil all requirements in uniformity at this cross-section.

2.3.1 The Crystal Structure The material used as a substrate in semiconductor technology must be in single-crystal form, i.e. it needs a regular arrangement of atoms. The smallest repeating unit of a crystal is called the “base”, which may consist of several atoms. In the crystal structure, each base represents a lattice point. The atom’s arrangement in the crystal results from the superposition of the lattice points with its base. The lattice of the elementary semiconductors silicon and germanium is a face-centred cubic (fcc) with a base of two identical atoms at positions (0,0,0) and (1/4,1/4,1/4)

2.3  Production of Single Crystals

11

Fig. 2.5   The fcc lattice (left) and the crystal structure of silicon (diamond lattice, right) (after [4])

Fig. 2.6   Crystal planes and Miller’s indices (after [4])

(Fig. 2.5). The crystal structure thus exists as two fcc lattices shifted against each other by 1/4 of the space diagonal of the cubic crystal; this corresponds to the diamond structure. The arrangement of the atoms in a silicon wafer is given by the orientation of the cubic lattice concerning the wafer surface (Fig. 2.6). It is described by the Miller indices, which are determined as follows: • Determination of the intersection points of the plane or surface with the axes of the crystal, e.g. 3,2,2; • Reciprocating (1/3,1/2,1/2) and finding the smallest integer ratio (2,3,3) leads to Miller’s indices (233) for this plane. Thus, a surface orientation can be unambiguously assigned to each silicon wafer. Knowing the Miller indices of the surface means the alignment of the fcc lattice in the wafer is known. It significantly influences the parameters of the integrated devices, e.g., the density of the surface charges and the charge carrier mobility at the crystal surface. The pure silicon obtained in the trichlorosilane process consists of a polycrystalline rod. Nevertheless, microelectronic circuit integration needs monocrystalline silicon wafers. So the rod must be converted into a single crystal first. This conversion is possi-

12

2  Silicon Wafer Production

ble with the Czochralski process or by crucible-free zone pulling for higher crystal quality with lower impurity concentration.

2.3.2 Crystal Pulling Method According to Czochralski In a slowly rotating quartz crucible, the polycrystalline silicon is first melted by radiofrequency heating and further heated up to approx. 1440 °C in order to reliably destroy possible crystallization nuclei in the liquid phase. The temperature is then lowered a little bit and kept constant only slightly above the melting point of silicon at approximately 1425 °C. The crystal pulling starts with a seed crystal for specifying the crystal orientation. It is fixed on a rotatably mounted rod above the melt. The seed crystal is brought up to the surface of the liquid silicon melt from the top. Since the crucible temperature is only slightly above the material’s melting point, the melt is supercooled at the moment of wetting at the location of the immersing seed so that crystallization begins. The nucleus starts to grow, with the accumulating silicon taking over the crystal orientation of the seed crystal (Fig. 2.7). The continuously rotating pull rod moves the growing nucleus slowly upwards without interrupting the contact with the melt (Fig. 2.7). Thus, a rod-shaped single crystal (“ingot”) is formed, the diameter of which is essentially determined by the pulling speed. The ingot grows at a rate of 3–20 cm/h. Its cross-section gets smaller the faster the rod moves up. In order to obtain large and defect-free crystals, precisely controlled temperature stabilization of the melt is required. Thus, a temperature as constant as possible is main-

Fig. 2.7   Principle of single-crystal pulling according to Czochralski (after [5])

2.3  Production of Single Crystals

13

tained within the growth zone. Even minor temperature differences lead to internal stresses during solidification and lattice defects in the growing crystal. Uniform temperature distribution at the melt surface is achieved by rotating the crystal around its longitudinal axis during the pulling process while the crucible rotates in the opposite direction. It is recommended to raise the crucible at the same rate as the melt is consumed (Fig. 2.8). In this way, the location of the growth zone remains unchanged, and the same temperature conditions always prevail. The entire process takes place in an inert gas atmosphere or under high vacuum conditions to prevent oxidation of the molten material. However, oxygen, carbon and boron can dissolve from the crucible walls, leading to contamination or doping of the silicon. For this reason, the process is not used to produce extremely high-purity silicon. Typically transistor and circuit integration use n-type or p-type silicon wafers. The dopants boron or phosphorus define the desired electrical properties of the crystal. The corresponding doping material is already dissolved in the melt, so the doping atoms are incorporated into the lattice during crystal growth. Typical resistivity values for Czochralski silicon (Cz-Si) range from below 50 Ω cm to heavy dopant concentrations with 0.01 Ω cm. The high-resistance material grown in the Czochralski technique is already very well suited for producing silicon wafers for integrating microelectronic circuits.

Fig. 2.8   Schematic of a system for crystal pulling according to Czochralski (according to [1])

14

2  Silicon Wafer Production

2.3.3 Crucible-Free Zone Pulling For the production of high-purity silicon a crucible-free zone pulling in vacuum or inert gas atmosphere is suitable (Fig. 2.9). As in the case of zone cleaning, instead of the entire material, only a part—a zone stabilized by the surface tension of the liquid silicon—is melted along the rod with a targeted locally applied radio-frequency power during crystal production. Valuable single crystals can be produced even with a simple zone cleaning apparatus. However, for higher demands, a seed for presetting the crystal orientation cannot be dispensed with. The high-purity polycrystalline silicon rod is fixed vertically so that its upper end almost touches the seed crystal. As the polysilicon is melted with a radiofrequency coil, the liquid surface bulges slightly and wets the seed, which begins to grow as the heating coil moves slowly downward (about 10–20 cm/h). As in crucible pulling, the polycrystalline supply rod and the nascent crystal rotate in opposite directions about their longitudinal axis (speed 25–75 rpm) to guarantee uniform temperature distribution in the growth zone.

Fig. 2.9   Crucible-free zone pulling for the production of high-purity silicon (after [6])

2.3  Production of Single Crystals

15

The length of the melted zone is only a few millimetres, depending on the thickness of the silicon rods. The process starts at the top of the single-crystal seed. After fusion with the liquid phase, the fused zone is slowly pulled along the stock rod. The result is a single crystal with excellent perfection in the crystal lattice. If weak crystal doping is desired, the doping material is added to the shielding gas as a gaseous compound. Phosphine (PH3) can be used for doping with phosphorus and diborane (B2H6) for boron doping. In the area of the melted zone, the doping gas decomposes into phosphorus, respective boron, and hydrogen. As a result of the high temperature, the dopants penetrate the melt and are incorporated into the growing ingot. Alternatively, the dopants can already be present in the source rod material. Comparable to zone purification, the remaining impurities preferentially remain in the molten zone; consequently, only a tiny percentage of them are incorporated into the resulting crystal. Contaminants only accumulate in greater concentration at the crystal end. This process can produce extremely pure silicon (>1000 Ω cm), which contains considerably less oxygen, carbon, boron, and phosphorus than Czochralsky silicon.

2.3.4 Crystal Defects In case of insufficient temperature control, too high or uneven pulling speed respective other disturbances during crystal pulling, structural defects can occur in the crystal. The essential defects are the point defects with atomic dimensions and the dislocation as a line-shaped defect. The point defect can consist of a simple lattice vacancy, i.e. a single lattice site is not occupied. An interstitial atom is also a point defect; in this case, an additional atom has accumulated between the lattice sites. Thermal excitation can also produce these effects, so point defects are always present in the crystal, even at room temperature. A dislocation can be illustrated as an additional plane inserted into the crystal (Fig. 2.10). They are caused by shear forces in the crystal, which can occur during rapid temperature changes in the material. In microelectronic devices, dislocations act as sinks for dopants generating parasitic current paths in the crystal.

Fig. 2.10   Two-dimensional view of a dislocation in a crystal

16

2  Silicon Wafer Production

A surface defect is present when adjacent crystal regions have different orientations. The contact planes between the crystallites are called grain boundaries; they are characterized by strong disturbances of the bonds of neighbouring atoms. In this case, there is no single crystal.

2.4 Crystal Processing Crystal processing comprises all further processing steps required to obtain ready-to-use crystal wafers with a defined surface orientation from the drawn single-crystal rod, as needed in planar technology. These include the sawing, lapping, etching and polishing steps explained below. First, the cylindrical single-crystal (“ingot”) is turned or milled to the desired diameter (“grinding”) and provided with two flats of different sizes (“primary” or orientation flat, “secondary” or identification flat) according to its crystal orientation and conductance type. The larger orientation flat is usually located along a highly symmetric crystal plane (100 or 110). In comparison, the location of the smaller secondary flat is used to identify the disk type according to Fig. 2.11. Both flats are milled into the crystal with a diamond cutter. From 125 mm diameter, the silicon wafers often have only a notch for identification instead of flats.

2.4.1 Dicing The single crystal is then cut into individual slices by sawing or dicing. For this purpose, the single crystal is precisely aligned according to the desired surface orientation of the wafers and glued or waxed onto ceramic carrier plates. In order to obtain the lowest possible unevenness, warping or thickness variations during the cut, an inner hole saw is used (Fig. 2.12). The inner hole metal saw blades are made of bronze, nickel or steel, with diamond particles on the cutting edge.

Fig. 2.11   Position of the flats for marking the disk material according to the doping and the surface orientation (according to [5])

2.4  Crystal Processing

17

Fig. 2.12   Inner hole saw (left) (after [5]) and wire saw (right) for cutting the single crystal into individual slices (after [6])

In addition to the inner hole circular saws, wire saws are used almost exclusively for large wafer diameters. They allow parallelization of the cutting process. At the same time, the damage to the surface of the crystal is lower compared to the inner hole saw cut. The cutting width is about 100 μm for both methods. Consequently, a significant part of the single crystal is lost when cutting the ingot.

2.4.2 Surface Treatment The cut wafers have a rough surface; in addition, lattice damage has occurred in the crystal due to the mechanical stress during sawing. During the subsequent surface treatment, the destroyed surface layer of the silicon wafer is removed down to the undisturbed crystal lattice, and the semiconductor material is etched back to the specified thickness. The last step is polishing the crystal surface. Various mechanical and chemical methods are applied to achieve a plane wafer surface without any lattice damage.

2.4.2.1 Lapping Using a mixture of glycerine and aluminium oxide or silicon carbide, about 50 μm of the silicon surface is mechanically abraded on a rotating steel disk to produce plane-parallel surfaces. The aluminium oxide serves as an abrasive in this process. The particle size is gradually reduced to allow the fastest possible processing while making a surface as smooth as possible. Abraded material and polishing agent residues flow along grooves in the polishing wheel. The goal is to achieve a surface flatness of approximately two μm across a wafer. Since lapping is a mechanical process, near-surface crystal lattice damage occurs again. These structural failures are removed in the subsequent steps. The devices for lapping are suitable for parallel processing of—depending on the diameter—3 to 12 wafers in one runner, whereby several runners can rotate on one lapping wheel (Fig. 2.13).

18

2  Silicon Wafer Production

Fig. 2.13   equipment for lapping the silicon wafers (after [6]).

2.4.2.2 Rounding off the Edge of the Slice The angular edges of the wafers resulting from crystal sawing can negatively affect the subsequent processes. Layer spalling in the edge area may occur by impacts during wafer processing. It leads to disruptive, mechanically solid and sharp-edged silicon particles, which may lay down on the wafer surfaces and inside the equipment. Furthermore, lattice defects penetrating the wafer can arise starting from the edge of the disc, extending far into the crystal. Another adverse effect concerns resist spinning. The photoresist builds up into a bulge at the edge of the wafer during spin coating due to its surface tension, which impedes close contact with the mask. Both effects can be avoided by rounding off the wafer edges. For this purpose, the wafer edge is moved along a fast rotating diamond cutter (Fig. 2.14), which produces a defined rounding by grinding. 2.4.2.3 Etching In order to remove all the contamination and lattice defects generated on the wafer surface in the lapping step, another 50 μm of silicon is removed by wet chemical etching.

Fig. 2.14   Device for rounding off the wafer edges with a rotating diamond milling cutter (after [5])

2.5  Tasks for Slice Production

19

Table 2.3  Typical data of silicon wafers with tolerance Wafer type [mm]

100

125

150

200

300

Diameter [mm]

100 ± 0.5

125 ± 0.5

150 ± 0.3

200 ± 0.2

300 ± 0.2

Thickness [μm]

525 ± 25

625 ± 25

675 ± 25

725 ± 25

775 ± 25

Misorientation [°]

 ±2

 ±2

 ±2

 ±2

 ±1

Flat/Notch [mm]

30–35

40–45/2

0/2

0/1

0/1

Deflection [μm]

15

20

25

30

50

Thickness var. [μm]

5

5

5

5

4

It is done by immersing the wafers in an etching solution consisting of nitric and hydrofluoric acid diluted with water or acetic acid. At the same time, this solution has a polishing effect, as peaks protruding from the wafer surface are preferentially removed.

2.4.2.4 Polishing A mixture of sodium hydroxide (NaOH), water and SiO2 grains having a diameter of approximately 10 nm, is suitable for polishing the wafer surface. The wafer is pressed against a rotating polishing cloth so that additional 5 μm of silicon is chemically/ mechanically removed from the crystal. Under pressure, the silicon oxidizes due to the resulting frictional heat in the NaOH solution, and the oxide is removed mechanically by polishing. Finally, the processing traces caused by the polishing agent are removed by polishing with pure NaOH solution without any abrasive additive. The resulting surface has a maximum roughness of less than 3 nm at the end of polishing. After this step, singlecrystalline silicon wafers with exact defined geometric dimensions, perfect polished surface and a known dopant concentration and crystal orientation are available. Table 2.3 shows typical wafer parameters.

2.5 Tasks for Slice Production Task 2.1 A silicon crystal doped with phosphorus is checked for its specifications after production. The requirements for the resistivity σ are between 15 and 20 Ω cm. For this purpose, a four-point measurement is performed in which a current is impressed across the outer tips, and the resulting voltage drop is measured at the inner tips (Fig. 2.15). The distance s between the probe tips here is s = 1 mm. The measurement results in a voltage of 25 mV with an impressed current I of 1 mA. Does this crystal meet the resistivity specifications? What is the doping level ND of the crystal?

20

2  Silicon Wafer Production

Fig. 2.15   Arrangement of the tips for measuring the specific resistance of the doped crystal

Help: From the solution of Laplace’s equation in spherical coordinates, it follows for the potential ϕ at the surface at distance r from the current injection ϕ(r) = I/2πσr. Task 2.2 During crystal production Msi = 500 kg high-purity silicon is fused with MB = 20  mg boron. Determine the atomic dopant concentration NBor for the idealized case of complete and lossless incorporation of the boron atoms into the pulled crystal!

References 1. Wilkes, J.G.: Silicon Processing. In: Jackson, K.A. (Hrsg.) Material Science and Technology Vol. 16, VCH, Weinheim (1996) 2. Maurits, J.E.A.: Silicon Production, Treatise on Process Metallurgy, Volume 3: Industrial Processes, pp. 919–948. Elsevier (2014) 3. Semiconductor Industry Association: The National Technology Roadmap for Semiconductors, San Jose (1997) 4. Kittel, C.: Introduction to Solid State Physics. Wiley, New York (2018) 5. Sze, S.M.: Physics of Semiconductor Devices. Wiley, New York (1981) 6. Madou, M.J.: Fundamentals of Microfabrication and Nanotechnology Vol. I, pp 226 ff. CRC Press, Boca Raton (2012)

3

Oxidation of Silicon

In semiconductor technology, silicon dioxide (SiO2) layers are required as insulating layers for the electrical function of the components. However, the oxide is also used as an auxiliary layer for masking during integrating MOS or bipolar circuits. Depending on the individual requirement, various processes have been developed for applying oxides to the silicon wafer surface, which differ in terms of the temperature, growth rate and quality of the resulting layers. In the manufacturing process, silicon dioxide layers are applied as masking oxides to cover the silicon substrate locally and to mask it before a subsequent process step. Another task of the oxide is to prevent the diffusion of dopants from the crystal into the surrounding atmosphere to maintain the existing substrate doping unchanged during the following temperature treatment. Finally, the alignment marks—the structures for aligning the individual photomasks—can be etched into the oxide to anchor orientation points into the wafer surface. For the tasks of the oxides in the production process, the electrical stability of the oxides is irrelevant. In this case, it is essential to have a high growth rate at the lowest possible process temperature. Oxide layers for the electrical function of the circuits are the gate oxide, the field oxide, the intermetal oxide and the capacitor oxide. These different oxides are subject to various electrical tasks and are also differentiated in their way of production according to the transistor requirements. Another application of oxide layers is the passivation of the wafer surface as protection against mechanical damage, corrosion protection for the metallization level, and a diffusion barrier for alkali ions to improve the long-term stability of the circuits. The oxide layers required in planar technology are predominantly produced by thermal oxidation or deposited from the gas phase. Alternatively, the oxides can also be

© Springer Fachmedien Wiesbaden GmbH, part of Springer Nature 2023 U. Hilleringmann, Silicon Semiconductor Technology, https://doi.org/10.1007/978-3-658-41041-4_3

21

22

3  Oxidation of Silicon

deposited by cathode sputtering or thermal evaporation; however, these processes are not widely used in semiconductor technology due to their low oxide quality.

3.1 Thermal Oxidation of Silicon Thermal oxidation occurs when oxygen, as the reaction gas, gets in contact with the hot silicon surface. The oxygen chemically reacts with the silicon of the substrate to form SiO2, resulting in an amorphous, glass-like layer on the surface of the silicon wafer. The thermal oxidation process can be divided into dry oxidation and wet oxidation. Wet oxidation again splits up either into water vapour-based oxidation or H2O2 combustion. Thermal oxidation occurs at a process temperature of around 1000 °C in a quartz tube heated via resistance heaters (Fig. 3.1). The temperature in the quartz tube is kept constant with slight fluctuations of ± 0.5 °C in the area of the silicon wafers. Typically the temperature is measured using thermocouples. There are 3 or 5 separately controllable heating coils along the quartz tube in the oxidation furnace to compensate for any temperature gradient inside the tube caused by disturbances from the gas flow. The independently heated coils allow a constant temperature to be set over a length of approximately 1 m so that 50–200 silicon wafers can be oxidized simultaneously under identical conditions. For wafer diameters of approximately 200 mm and more, the heat convection inside the tube is no longer negligible. The turbulence in the gas flow leads to nonuniform oxide growth on the wafer surface. For this reason, vertical furnaces with quartz tubes arranged perpendicular to the ground floor are increasingly used in modern technologies. For thermal oxidation, the silicon wafers are located in a holder made of quartz glass called a “carrier”. They slowly move into the oxidation tube at approximately 400– 700 °C using an inert atmosphere like nitrogen. The furnace then slowly heats the quartz tube with the wafers to the process temperature, limiting the heating rate to a maximum of approximately 10 °C/min to avoid wafer distortion. After the processing temperature

Fig. 3.1   Design of an oxidation furnace for the optional dry or wet oxidation of silicon

3.1  Thermal Oxidation of Silicon

23

has been reached, the atmosphere inside the tube switches from nitrogen to oxygen (or water vapour) and the corresponding oxidation takes place.

3.1.1 Dry Oxidation The dry oxidation of silicon takes place in a pure oxygen atmosphere according to the chemical reaction

Si + O2 → SiO2

(3.1)

This reaction typically occurs at a process temperature of 1000–1200 °C to achieve a sufficiently high growth rate. Lower temperatures around 800 °C are used to generate electrically highly loaded, extremely thin oxides, e.g. the tunnel oxides of non-volatile memory transistors. However, dry oxidation only leads to a low oxidation rate, i.e. only thin oxide films can be produced in a reasonable time. The resulting oxide films have a high density and a high breakdown voltage. Consequently, dry oxidation is used for oxides subject to high electrical stress, e.g. for the gate oxide of MOS transistors. Gate oxides are increasingly grown in N2O atmospheres to incorporate a small amount of nitrogen into the resulting oxide in addition to the preferential reaction of the silicon with oxygen. Nitrogen has a positive effect on electrical stability [1], and additionally, it reduces boron diffusion through thin oxides. For gate oxide thicknesses below 3 nm, oxidation is often carried out in an RTO process (“Rapid Thermal Oxidation”, Sect. 6.3.3) [2].

3.1.2 Wet Oxidation In wet oxidation, the oxygen flows through a wash bottle (“bubbler” vessel) with water heated to 90–95 °C before the gas is admitted into the oxidation tube. At the semiconductor surface, the water molecules absorbed by the carrier gas react with the substrate to form silicon dioxide. The chemical reaction according to Eq. (3.2) describes the wet oxidation:

Si + 2H2 O → SiO2 + 2 H2

(3.2)

This reaction usually occurs in a temperature range of 900–1100 °C. The growth rate of silicon dioxide is already relatively high at low temperatures, so wet oxidation is suitable for creating thick oxide layers (Table 3.1). The pronounced growth rate results from the reaction of the OH groups with the already grown SiO2. The OH molecules generate a high point defect density in the existing SiO2 structure by attaching to the surface. These point defects accelerate the oxygen or OH diffusion to the silicon/SiO2 interface.

3  Oxidation of Silicon

24

Table 3.1  Growth rates during thermal oxidation of monocrystalline silicon (according to [3]) Temperature (°C)

Dry oxidation (nm/h)

Wet oxidation (nm/h)

T = 900

19

100

T = 1000

50

400

T = 1150

130

650

However, the wet-grown oxide layers do not achieve the high quality of a dry-grown oxide at moderate oxidation temperatures up to 1100 °C. Its breakdown voltage and material density are lower (Table 3.2). Although this changes at higher temperatures in favour of wet oxidation, this effect cannot be used to produce gate oxides in MOS circuits due to the extreme thermal load on the wafers. Wet oxidation is particularly suitable for producing thick masking and field oxides due to its high growth rate at relatively low temperatures (Fig. 3.2). To take advantage of the reduced process temperature and to avoid dopant diffusion, this process is also occasionally used to produce electrically highly stressed oxides after local doping of the silicon wafers. A typical application is the capacitor oxide for a capacitor consisting of a strongly n-type silicon electrode, thermally wet-grown oxide thereon as a dielectric layer and an aluminium counter electrode.

3.1.3 H2O2 Combustion In wet oxidation of silicon by H2O2 combustion, high-purity hydrogen and high-purity oxygen are simultaneously fed into the quartz tube via separate supply lines. It is essential to have a temperature of approximately 600 °C at the gas inlet to ensure direct ignition of the gases at the inlet opening. Furthermore, it is crucial to choose an appropriate mixing ratio of H2:O2 to avoid an explosion of the resulting oxyhydrogen gas. The H2O2 combustion process has the advantage of a high oxide layer growth rate with only a few oxide impurities. In contrast to the limited stability of the bubbler temperature, the amount of OH molecules introduced into the quartz tube is uniform even in long oxidation processes. The process is used to grow thick films as well as to produce thin oxides at low temperatures. One example is the production of the capacitor dielec-

Table 3.2  Properties of thermally oxidized SiO2 layers (after [3]) Density [g/cm3] 1000 °C

1200 °C

Breakdown field strength [V/μm] 1000 °C

1200 °C

O2, dry

2.27

2.15

550

515

O2, wet

2.18

2.21

525

535

Oxidation method

3.2  Modelling of the Oxidation

25

Fig. 3.2   Oxide layer thickness grown on (100)-silicon as a function of oxidation time (after [4])

tric, which can only be oxidized at a maximum of 900 °C due to the diffusion of already introduced dopants. All thermal oxidation processes show a higher oxidation rate for (111) silicon surfaces compared to (100) planes. The oxidation rate also increases significantly on heavily doped n- or p-type silicon. The dopants have an oxidation-supporting effect which is even more pronounced for n-type material. Their concentration must be in the range above 1 · 1018 cm−3 so that the semiconductor material has electrically degenerated. The oxygen diffusion rate in the already grown oxide depends on the concentration gradient from the surrounding atmosphere to the SiO2-Si interface; consequently, the oxidation rate increases with increasing pressure. A special high-pressure oxidation process has been developed in a wet atmosphere for exceptionally high oxide thicknesses, which runs at 10–25 bar. With this process, oxide thicknesses of several micrometres can be produced in a reasonable time.

3.2 Modelling of the Oxidation In all processes described above, the oxide growth rate is not limited by the chemical reaction of the oxygen with the silicon. The limitation is the oxygen diffusion from the surrounding atmosphere through the already existing oxide to the reaction partner sili-

3  Oxidation of Silicon

26

con from the substrate. Since the amount of oxygen available at the oxide/silicon interface decreases with increasing oxide thickness dox, the film growth rate decreases with increasing oxidation time. A thickness increase proportional to the square root of time can be assumed as a rough approximation. A more accurate model takes into account a linear and a parabolic part of layer growth during thermal oxidation: 2 dox + αdox = β(t + t0 )

(3.3)

with α and ß as temperature-dependent quantities and t0 to account for the natural, primarily negligible surface oxide. ß is the parabolic growth constant, while ß/α describes the linear oxide growth. The linear oxide growth prevails at low (or no) oxide thickness since the process proceeds in a reaction-limited manner. In this case, the speed of the chemical reaction determines the growth rate. Consequently, the approximation commonly used for small oxide thicknesses is:

dox =

β t α

(3.4)

with ß/α as the linear growth constant. The linear component is negligible for large oxide thicknesses or long oxidation times. In this case, the diffusion of the oxygen through the oxide already present determines the growth rate, i.e.: √ dox = βt (3.5) The temperature dependence of ß and ß/α is given by: −EP

(3.6)

β = CP e kB T

−EL β = CL e kB T α

(3.7)

EP and EL are the activation energies of the oxidation process, CL and CP are prefactors (see Table 3.3), kB is the Boltzmann constant. Table 3.3  Activation energies and prefactors for the thermal oxidation of silicon [3] Oxidation type

EL [eV]

EP [eV]

Dry, T  1000  °C

2.25

1.14

Wet, T > 900  °C

2.01

0.76

CL [nm/min] 7.35 ·

106

9.92 ·

108

7.35 · 108

CP [nm2/min] 1.70 · 1011 5.79 · 106 5.12 · 106

3.3  The SiO2/Silicon Interface

27

3.3 The SiO2/Silicon Interface In contrast to crystalline silicon, the growing silicon dioxide is amorphous, i.e. there is no regular arrangement of atoms in the layer. Consequently, not all silicon bonds can be saturated at the silicon interface to the oxide, so free bonds are present. They can act directly as a charged state or can be charged subsequently by trapping charge carriers during the electrical operation of the device. These chargeable states are called “traps”; their charge state varies in time. In addition, fixed charges exist near the interface resulting from imperfect oxidation of the silicon [2]. Here, incompletely formed covalent bonds between the silicon and oxygen atoms act as a fixed positive interfacial charge. Further positive charges occur through contamination of the oxide with alkali ions. Alkali ions are not stationary due to their high diffusion coefficient but move towards the negatively charged electrodes when a voltage is applied. This effect can already be detected at 150 °C within a few hours. In addition, there are fixed charges deep in the oxide, which are caused by charged states in the bandgap of the silicon dioxide. The oxide charges mentioned above can be divided into fixed interfacial, stationary and mobile charged states. Chargeable traps exist at the silicon interface and in the oxide itself. The sum of all charges at the transition from the oxide to the silicon substrate always is positive. As these charges directly influence the surface potential of the silicon and thus the threshold voltage of MOS transistors, their density must be kept as low as possible. The density of the stationary and the interfacial charges decreases with increasing oxidation temperature. As hydrogen atoms saturate open bonds, wet oxidation also ensures a lower charge density. For the long-term stability of the circuits, the density of the chargeable states and the mobile oxide charges due to impurities with alkali ions (Na+ , K+ ) is significant since the charge carriers or charges trapped here prevent a temporal constancy of the threshold voltage. Sodium and potassium already drift in the oxide at the operating temperature of integrated circuits. If an electric field is applied—e.g. a gate voltage— positive charges assemble at the negative electrode, thus leading to a local transistor threshold voltage variation over time. Other device parameters show deviations, too. Consequently, these charges must be avoided as far as possible during the production of the oxides. The addition of chlorine during the thermal oxidation process serves as a countermeasure to improve the long-term stability of integrated circuits. It is added to the gas flow as hydrogen chloride (HCl vapour) or trichloroethane (TCA). The chlorine binds the mobile ions during thermal oxidation, so the oxide charge density decreases significantly (cf. Fig. 3.3).

28

3  Oxidation of Silicon

Fig. 3.3   Reduction of the interfacial charges and change of the grown oxide thickness by chlorine addition during the thermal oxidation of silicon (after [5])

3.4 Segregation During the thermal oxidation, the surface of the silicon substrate gets transformed into SiO2. This means the thermal oxidation process consumes silicon from the doped substrate. The ratio of the grown oxide thickness to the amount of consumed silicon is 2.27:1. The oxide rises about 56% above the original silicon surface, and about 44% of the grown oxide thickness is used from the crystalline silicon wafer (Fig. 3.4) shifting the original surface to the depth. The doping atoms out of this zone of consumed silicon can either remain in the silicon crystal or be incorporated into the grown oxide. The solubility of the correspond-

Fig. 3.4   Displacement of the oxide-silicon interface by thermal growth of silicon dioxide

3.4 Segregation

29

ing element in the respective material is decisive for the proportional distribution of the dopants. The segregation coefficient k describes this behaviour:

k=

solubility of the element in silicon solubility of the element in silicon dioxide

(3.8)

If the segregation coefficient k is greater than 1, there is an enrichment of dopant atoms at the silicon surface (“pile-up” effect); the oxidation front drives the dopants ahead of it. For k  UDS

(10.1)

and

ID =

β [UGS − Ut ]2 2

UGS − Ut ≤ UDS

(10.2)

with

β=

µn,p ε0 εr W tox L

(10.3)

10.4  Tasks for the MOS Technique

173

Calculate the cross current through a MOS inverter with a resistive load of 10 kΩ and an n- (p-) channel transistor with W/L = 10 μm/2 μm and tox = 40 nm at 5 V operating and input voltage.

µ0n = 600 cm2 /(Vs), µ0p = 400 cm2 /(Vs), εox = 3, 9, Ut = +(−)1 V Task 10.3 From the topographical layout (Fig. 10.19) of a circuit, its electrical behaviour is to be determined. Draw the technology cross-section from A to A′. What manufacturing process is the layout based on? Draw the circuit diagram and determine the size of the resistor and the design sizes of the transistor from the layout! Calculate the maximum cross-current through the circuit (quasi-static operation). What is the residual voltage UA? Calculate the oxide thickness of the capacitance and the gate oxide thickness of the transistor! Which size of the circuit limits the switching time at the given capacitance?

Rndiff = 40Ω/ ⃣; Utn = 1V ; β = 50µA/V 2 ; CL = 1pF, µn = 600cm2 /(Vs) Task 10.4 Determine the threshold voltages and the surface mobilities of the respective charge carriers from the characteristics of the n- and p-channel MOS transistors, shown in Figs. 10.11 and 10.12, using the equations from Task 10.2 and εox = 3.9. Task 10.5 Label the individual layers of the transistor structure shown in Fig. 10.20

Fig. 10.19   layout for a MOS integrated circuit

174

10  MOS Technologies for Circuit Integration

Fig. 10.20   Photo of a MOS transistor with 3 μm channel length

References 1. Höfflinger, W.B.: Großintegration. Oldenbourg, Munich (1978) 2. Zimmer, G.: CMOS-Technologie. Oldenbourg, Munich (1982) 3. Chen, W.-K.: The VLSI Handbook. CRC Press LLC, Florida (2000)

Developments for High-Density Integrated Circuits

11

The integration technique for CMOS circuits, as discussed in chap. 10, is suitable for minimal transistor channel lengths of approximately 1.5 μm. Further miniaturisation using the presented process flow is limited due to: • • • •

the insufficient resolution of simple optical photolithography, the restricted dielectric strength of the MOS devices, increasing electrical field strength in the transistor’s channel, and growing resistance in the polysilicon tracks.

For this reason, extensive changes in the process flow are required to fabricate circuits with higher integration densities and increased operation frequencies by using more refined structures. Some basic techniques are discussed below.

11.1 Local Oxidation of Silicon (LOCOS) In the planar technique, as treated so far, the field oxide grows over the entire surface of the silicon. Subsequently, the areas where diffusions or implantations occur are exposed to wet chemical etching for oxide removal. The resulting steps between the surface of the field oxide and the open silicon substrate lead to resist accumulation during photoresist deposition and thus limit the resolution of the photolithography technique. In addition, lateral under-etching of the resist mask due to the isotropic etch characteristics of the etch solution for field oxide patterning limits the minimum achievable pattern size because it requires a mask adaptation to compensate for the etch error.

© Springer Fachmedien Wiesbaden GmbH, part of Springer Nature 2023 U. Hilleringmann, Silicon Semiconductor Technology, https://doi.org/10.1007/978-3-658-41041-4_11

175

176

11  Developments for High-Density Integrated Circuits

Furthermore, the metallisation at the field oxide steps has limited conformity, so local necking of crossing traces occurs at the edges. Thus, premature wiring ageing due to electro migration occurs due to the increased local current density. Consequently, for integrating microelectronic circuits with high device density or the smallest structure dimensions, the steps and unevenness on the wafer surface must be significantly reduced or entirely suppressed. One approvement is a specialised process for field oxidation called Local Oxidation of Silicon (LOCOS).

11.1.1 The Simple Local Oxidation of Silicon

Fig. 11.1   Comparison of grown oxide thicknesses on silicon (upper curves) and silicon nitride as a function of the Oxidation time (after [1])

Thickness [µm]

The LOCOS technique uses the different oxidation rates of silicon and silicon nitride for local masking of the wafer surface during thermal field oxidation (Fig. 11.1). Only LPCVD nitride is suitable for masks because PECVD nitrides are usually permeable to oxygen and oxidise at a high rate. In the LOCOS technique, a silicon nitride layer deposited on the wafer surface and patterned via the photolithography and dry etching technique serves as a local diffusion barrier for oxygen, thus acting as an oxidation barrier for the silicon underlying the nitride. A field oxide can consequently only grow on the exposed silicon surface. Since the mechanically very hard silicon nitride has a higher thermal expansion coefficient than silicon, direct contact between the materials causes mechanical stress due to

10

Silicon

1

0,1 Nitride

0,01 0

2

4

6

8

10 12 14 16 Oxidation time [h]

11.1  Local Oxidation of Silicon (LOCOS)

177

Silicon nitride p-Silicon

Silicon nitride

Padoxide

p-Silicon

SiO2

Fig. 11.2   Masking and shape of the grown oxide in the simple LOCOS technique with pad oxide and nitride mask

the high-temperature load during deposition and oxidation. This stress leads to lattice or crystal defects in the silicon substrate. It is necessary to avoid the strain by using a thin silicon dioxide film as a buffer layer, called pad oxide, between the nitride mask and the silicon substrate. It compensates for these temperature-induced mechanical forces by its elasticity. However, the pad oxide causes an undesired lateral oxygen diffusion during thermal oxidation under the nitride mask. It leads to a slight oxide growth in the edge region below the masking. The resulting oxide extends under the nitride mask, thus reducing the active area size; according to its shape, it is called “bird’s beak” (cf. Fig. 11.2). Its length depends on the pad oxide and nitride thickness as well as on the oxidation parameters: the thinner the pad oxide or, the thicker the masking nitride and the higher the oxidation temperature, the weaker the bird’s beak is formed [2]. This bird’s beak reduces—depending on the field oxide thickness—the size of the active areas by up to 1 μm per edge so that a compensating mask preset is required. When wet oxidation, which is considered the standard for generating the field oxide, is used, the “white ribbon” or “Kooi” effect also occurs [3]. In the area of the tip of the bird’s beak, a thin nitride layer forms between the pad oxide and the silicon surface on the active regions during oxidation (Fig. 11.3). Due to the diffusion of OH− groups under the mask edge, slight thermal oxidation of the masking nitride occurs. In this process, ammonia (NH3) forms in conjunction with the hydrogen present during wet oxidation. The ammonia diffuses to the surface of the silicon and leads to thermal silicon nitride in the active areas.

Fig. 11.3   White ribbon effect: Formation of thermal nitride on the silicon surface caused by ammonia generation at the interface between the nitride mask and the pad oxide

OH ¯ Silicon nitride Si3N4 + 6OH → 3SiO2 + 2NH3 + N2 SiO2

NH3 Si3N4 Silicon

178

11  Developments for High-Density Integrated Circuits

This effect is only critical at the tip of the bird’s beak since the diffusion velocity of the NH3 is higher than that of the oxygen. Thus the oxidation rate of the silicon is low at this point. The unwanted nitride stripe must be removed before gate oxidation because no stable gate oxide can grow in this area due to the masking effect of the silicon nitride. Despite the parasitic effects, as mentioned before, simple local oxidation is a suitable technique for advanced circuit integration. The advantages over the planar process are considerable. The transition from the active area to the field area is not abrupt but smooth, with a moderate slope. Neither photoresist thickness fluctuations in edges nor conductor track breaks can occur here. The steps from the silicon to the oxide surface after field oxidation shrink from 100% of the oxide thickness to approximately 55%, and structures with minimum active area widths of approx. 1 μm can also be produced. This small active area width cannot be achieved by wet chemical etching of the field oxide since a mask preset is necessary to compensate for the under-etching in the oxide. After field oxidation, the nitride is removed in hot phosphoric acid (156 °C) or a dry etching process with CHF3/O2. Further surface levelling can now be achieved by targeted wet chemical etching the entire oxide surface by 100–200 nm (“Fully recessed LOCOS”). Although a part of the grown field oxide is lost, the extension of the bird’s beak into the active area decreases. At the same time, the step between the oxide surface and the active silicon reduces according to the difference between the etched layer thickness and the pad oxide thickness.

11.1.2 SPOT Technique for Local Oxidation In addition to the simple LOCOS technique, some more methods, varying in complexity, have been developed to increase surface planarity and suppress parasitic effects such as bird’s beak and white ribbon effect. The local oxidation technique with double field oxidation and nitride deposition (SPOT technique = Super Planar Oxidation Technology, Fig. 11.4) provides an excellent planar surface [4]. As a disadvantage, the structural precision is poor when the mask is transferred into the silicon. Also, parasitic effects such as bird’s beak and white ribbon still occur. Furthermore, this technique requires additional, time-consuming processing steps to produce the field oxide. After thermal field oxidation using the simple LOCOS technique, isotropic wet chemical etching removes the just-grown thermal oxide. The nitride mask remains unchanged on the wafer surface as it is still needed for further processing. Another conformal nitride deposition follows after the second short pad oxidation. This nitride is used to seal the bird’s beak region below the nitride mask to prevent thermal oxidation in this area. With the aid of anisotropic reactive ion etching, e.g. in CHF3/O2 plasma, precisely the last deposited nitride thickness must be removed. So the second masking layer remains

11.1  Local Oxidation of Silicon (LOCOS)

179

Nitride I

a)

Padoxide I SiO p-Silicon SiO2 2

NitrideI I Nitrid Padoxide I b)

Nitride II Padoxide II

p-Silicon Nitride II Nitride Nitrid I I

c)

Field oxide

p - Si p-Silicon

Fig. 11.4   SPOT technique of local oxidation with double field oxidation and nitride deposition to optimise surface planarity. a Cross-section after first field oxidation, b wet chemical oxide back etching, second pad oxidation, conformal nitride deposition and anisotropic nitride etching, and c cross-section after second field oxidation

only below the first nitride and at the vertical edges of the coating. A further wet thermal oxidation yields the desired field oxide layer thickness, with the bird’s beak growing under the second nitride. It leads to a smooth transition from the field region to the active silicon. This SPOT process now provides an almost perfectly planar wafer surface. Significant deviations between the structural dimension of the mask template and that of the active regions in the silicon occur, which are unavoidable. The mask template required to compensate for this difference and the complex process control, in conjunction with the considerable time required for repeated field oxidation, prevent the use of this local oxidation process in modern CMOS technology. The SPOT technique is used in microsystem technology, e.g., to integrate optical waveguides on silicon substrates.

11.1.3 The SILO Technique As an alternative to the processes presented so far, the SILO technique (SILO = Sealed Interface Local Oxidation) is characterised by targeted suppression of the bird’s beak and the white ribbon effect [5]. In this case, the surface of the silicon wafer is first thermally

180

11  Developments for High-Density Integrated Circuits

nitrided at approximately 1200 °C in an NH3 atmosphere—comparable to thermal oxidation. 1200 ◦ C

(11.1)

3Si + 4NH3 −→ Si3 N4 + 6H2

During thermal nitridation, a thin layer of about 4 nm up to 10 nm Si3N4 grows on top of the silicon. Due to its limited thickness, it cannot induce significant lattice stresses in the silicon substrate. This contrasts the techniques mentioned above, where the Si3N4 requests a pad oxide for separation from the crystal. This thin nitride mask would completely oxidise during thermal field oxidation. Therefore another nitride layer must be deposited on top, separated by a thin oxide film. Both layers apply LPCVD for deposition (cf. Fig. 11.5). A photoresist mask protects the active areas of these sandwich-like films during reactive ion etching of all layers for patterning. In the SILO technique, the thermal nitride layer only seals the silicon surface against oxygen diffusion below the structure edges. It effectively suppresses the formation of the bird’s beak around the active regions and the white ribbon effect because oxygen cannot penetrate between the thermal nitride and the silicon substrate. An LPCVD nitride cannot replace the thermal nitride layer because there is inevitably a natural pad oxide between the silicon surface and the nitride. Applying the SILO technique for circuit integration is quite complex because additional process steps—a thermal nitriding as a high-temperature step and a CVD oxide deposition—are required besides nitride deposition. However, it gives good results in suppressing the parasitic effects of the simple LOCOS technique. The surface planarity corresponds to the results of the simple LOCOS technique, i.e. a step of about 55% of the field oxide thickness remains at the active area boundaries after the nitride masking is removed.

11.1.4 Poly-Buffered LOCOS Another alternative to reduce the above-mentioned parasitic effects is the LOCOS technique using a buffer of polycrystalline silicon (“Poly-buffered” LOCOS). Here, a polysil-

Si3N4

SiO2

Thermal Si3N4 p-Silicon

Si3N4 Thermal Si3N4

SiO2

p-Silicon

Fig. 11.5   Structure of masking and oxide growth when using the SILO technique for localised oxidation of silicon

11.1  Local Oxidation of Silicon (LOCOS)

181

Polysilicon Silicon nitride Padoxide p-Silicon

Silicon nitride p-Silicon

SiO2

Fig. 11.6   Masking layer sequence and oxide growth in the poly-buffered LOCOS technique

icon film of 20–50 nm thickness is inserted between the pad oxide and the nitride mask, limiting the expansion of the bird’s beak below the mask edge and effectively suppressing the occurrence of the white ribbon effect on the silicon substrate (Fig. 11.6). The oxygen diffusing under the nitride mask during oxidation oxidises mainly the polysilicon, less the silicon of the substrate; thus, the buffer layer has a positive effect on the structural fidelity. Local nitriding of the silicon surface under the pad oxide does not occur since the required NH3 molecules are not formed due to the lack of backside oxidation of the nitride. After peeling off the masking layers, the step at the field oxide edge to the active area is still about 55% of the oxide thickness. However, since the bird’s beak as oxide runout under the mask is not entirely suppressed, absolute structural fidelity is not given. Due to this minimal extension—only the polysilicon deposition complements the standard LOCOS process—this advanced technology has become a standard in the industry. The poly-buffered LOCOS technique can be optimised by a back-etching step for silicon dioxide after the process sequence of thermal field oxidation and removal of the nitride and polysilicon layers. Besides the pad oxide, the etching process also removes some birds’ beaks and field oxide, consequently reducing the step from field oxide to the active region. This type of field oxidation is widely used under the name “Fully recessed poly-buffered LOCOS”.

11.1.5 The SWAMI LOCOS Technique The previously explained LOCOS techniques show that the step height at the wafer surface after local field oxidation is still 55% of the generated oxide thickness. Structural fidelity is improved but not perfect. The silicon substrate must be etched back by about 55% of the desired oxide thickness in the areas of oxide growth before thermal oxidation to achieve an entirely planar surface. During thermal oxidation, the growing silicon dioxide volume is larger than that of the silicon consumed. Accordingly, the step between oxide and silicon surfaces shrinks in the oxidation course. Etching the substrate in the simple LOCOS technique, SILO, or poly-buffered LOCOS technique, the surfaces of the field and active areas are at the same level after thermal oxidation. However, lateral oxidation of the silicon below the edge of the nitride mask creates an elevation around the active regions. Its height corresponds to the grown

182

11  Developments for High-Density Integrated Circuits

Fig. 11.7   SEM image of a bird’s head using the simple LOCOS technique with the structuring of the substrate (scale = 1  μm)

oxide thickness (Fig. 11.7). Due to its shape, the elevation is called “bird’s head” in reference to the previously explained bird’s beak. The SWAMI-LOCOS technique (SWAMI-LOCOS = Side WAll Mask Isolated LOCal Oxidation of Silicon) aims to obtain a completely flat substrate surface in conjunction with an exact structure size of the active areas. The method applies the etching of the silicon in the field area to compensate for the oxidation-induced volume expansion [6]. Like the simple LOCOS technique, the pad oxide is first thermally oxidised on the silicon. The surface is coated with nitride, and the photoresist mask is applied to cover the active areas. The nitride film and the pad oxide are removed in CHF3/O2 and CHF3/ Ar atmosphere, respectively, using the RIE process. Another anisotropic etching step follows removing the silicon substrate to a thickness of about 55% of the later desired oxide thickness; it is carried out in a reactive ion etching process. BCl3, SiCl4, SF6 or CBrF3 serve as reaction gases. The etch depth corresponds to the volume increase of the silicon by oxidation to the silicon dioxide. Before field oxidation, passivation of the vertical active region flanks against the oxygen atmosphere is necessary. For this purpose, another pad oxide is thermally generated at 900 °C and covered by a second conformal nitride deposition. This second nitride layer can be etched back directly in an anisotropic dry etching process. Only the layers deposited on the vertical flanks and the first nitride remain on the silicon (Fig. 11.8). Consequently, the entire active region is masked during thermal oxidation with silicon nitride at the surface and the active region flanks. During the subsequent thermal oxidation, the field oxide grows outside the active regions until a planar surface is achieved at the end of this process step. Only directly at the interface of the SiO2 to the active areas a narrow constriction is formed, which results partly from the masking-induced depletion of silicon to be oxidised, partly also released by the removed second masking nitride (Fig. 11.9). A significant advantage of the technique mentioned above is that no mask size corrections are required to apply the field oxide, i.e. a planar wafer surface is created in conjunction with a structurally accurate transfer of the mask dimension into the silicon

11.1  Local Oxidation of Silicon (LOCOS)

183 Nitride I Pad oxide I

a)

p-Silicon Nitride II Pad oxide II

b)

p-Silicon Nitride II Field oxide p-Silicon

c) Fig. 11.8   Masking and process sequence in the SWAMI-LOCOS technique to produce a planar wafer surface. a masking and structuring of the substrate, b passivation of the vertical island flanks, and c structure and surface after thermal field oxidation

Fig. 11.9   Surface planarity in the area of the transition from the field oxide to the active area when using the SWAMILOCOS technique

11  Developments for High-Density Integrated Circuits

184

substrate. Furthermore, the bird’s beak, the white ribbon effect and the possible bird’s head occurring in the simple LOCOS technique are effectively suppressed. On the other hand, the constriction around the active area is harmful; parasitic current paths can form in the silicon on these vertical flanks. A conformal oxide deposition with subsequent etching back of the deposited layer to fill the recess may be applied for optimisation.

11.1.6 Trench Isolation In high-density integrated circuits, the distances between the active areas are less than 0.5 μm. Limited field oxide growth will occur in these gaps due to the lateral depletion of available silicon for oxidation by applying any LOCOS technique. Therefore, trench isolation (Shallow Trench Isolation, STI, partly called box isolation) has been developed, which provides sufficient isolation even for dimensions below 50 nm. The process starts with standard LOCOS pad oxide and silicon nitride layer deposition. Instead of thermal field oxidation, narrow trenches with the desired field oxide thickness as their depth are anisotropically etched into the substrate between the active regions. A boron ion implantation suppresses parasitic channels at the trench walls in p-type substrates as inversion may occur due to existing oxide charges. The doping can be done immediately after etching, with the photoresist etch mask also serving to mask the ion implantation (Fig. 11.10). However, the trenches in the n-type regions must be protected against this doping by a photoresist mask. A short oxide etching step removes the pad oxide surrounding the trench opening by about 20 nm to prevent bird’s head formation during the following thin thermal oxidation. Thermal oxidation is needed to avoid high oxide charge density at the interface to

B+ Photoresist Padoxide

a)

Silicon Padoxide

c)

e)

Silicon

Padoxide

b) Si3N4

Silicon Padoxide

Photoresist

Si3N4

Silicon Padoxide

d) Si3N4

Si3N4

Silicon Padoxide

f)

Si3N4

Si3N4

Silicon

Fig. 11.10   Shallow trench isolation a LOCOS starting structure, b trench etching and boron doping, c padoxide pre-etch, d ligner oxidation, e oxide refill by CVD, and f STI after CMP

11.2  Advanced MOS Transistors for High-Density Integrated Circuits

185

the silicon walls. Afterwards, a conformal oxide deposition fills the trenches until the whole openings are closed. The STI process ends with the oxide removal from the surface by chemical mechanical polishing. CMP stops at the silicon nitride film, which is finally removed in phosphorous acid or by reactive ion etching. The integrated transistors are laterally insulated from each other by an oxide that is entirely inside the silicon substrate. The trench depth for transistor isolation is about 250 nm in memory or microprocessor circuits; for high-voltage devices, it can be as deep as 2–5 µm. The STI process is suitable for producing field oxides in the finest interstices with less than 50 nm width. However, it is unsuitable for coarse dimensions in the micrometre range, so a combination of STI and LOCOS technology must be used in circuit integration.

11.2 Advanced MOS Transistors for High-Density Integrated Circuits The reductions of the transistor geometries, especially the channel lengths and the gate oxide thicknesses, improve the conductivities of the n- and p-type transistors. As a result of the higher channel conductivities, the switching speeds of the integrated devices also grow despite the increased gate/substrate capacitances, while the parasitic drain/substrate and source/substrate capacitances and the required circuit area still decrease as side effects. A simple consideration of the MOS transistor as a two-port for calculating the transit frequency is carried out according to the equivalent circuit in Fig. 11.11. In general, at the transit frequency fT for the shorted output, it can be applied: | | | ia | |H21 | = || || = 1 (11.2) ie From this follows for operation in saturation neglecting the gate/drain capacity (CGD = 0):

la+ia

Cgd

ie Va=const.

Ve+ve

le+ie

ve

Cgs

Cgb

ia

gmve

gds

Fig. 11.11   Two-port circuit and simple small-signal equivalent circuit for determining the transit frequency of a MOS transistor

186

11  Developments for High-Density Integrated Circuits

gm 2π (CGS + CGB )

(11.3)

W ∂IDS = µCox (UGS − Ut ) Leff ∂UGS

(11.4)

CGS + CGB = Coc WLeff

(11.5)

fT = Inserting the input conductance gm

gm = and

for the transit frequency fT follows

fT =

µ(UGS − Ut ) 2 2π Leff

(11.6)

Fig. 11.12   Transition frequency of MOS transistors as a function of the square of the inverse effective channel length

Transition frequency [GHz]

i.e. the cutoff frequency of a MOS transistor is directly co-determined by the square of the effective channel length. Although the experimental results in Fig. 11.12 differ significantly from the theoretical values based on these simple model equations, the reciprocal quadratic dependence between fT and Leff is confirmed. Thus, one development goal is to minimise the transistor channel length to increase the cutoff frequencies of integrated MOS circuits. Stateof-the-art (2022) are MOS transistors with channel lengths ranging from 10 to 8 nm effective electrical channel length, with minimum geometries as small as 5 nm predicted for the near future [7]. Integrating these transistors with geometric or electrical channel lengths being a fraction of visible light wavelength, an exact structure definition and transfer are necessary because deviations of only a few nanometers in the channel length mean errors of more than 20% in the geometries of these sub micrometer transistors. Variations will

Theory Experimental

15

10

5

0

0

0,5

1

1,5 1 / L2 [µm-2]

11.2  Advanced MOS Transistors for High-Density Integrated Circuits

187

have a correspondingly strong effect on the transistor parameters and are intolerable in the series production of microelectronic circuits. The simple CMOS process described in chap. 10 is unsuitable for these structural dimensions even after introducing a local oxidation technique. In addition to suppressing electrical breakdown mechanisms due to excessive field strengths and extensions of space charge regions, reducing the resistances in the polysilicon and the contacts is necessary.

11.2.1 Breakdown Mechanisms in MOS Transistors The miniaturisation of MOS transistors down to some nanometres demands precise processing. Failures of less than 5% in line width are needed, especially in the case of structure transfer by photolithography and etching. Even if all technological obstacles are solved, electrical limitations in short channel transistors occur. With decreasing transistor channel length and gate oxide thickness, the field strengths in the MOS transistors increase strongly. Charge carrier generation by impact ionisation (avalanche breakdown), the expansions of the space charge zones and the tunnelling effect in thin gate oxides limit the minimum electrically permissible device dimensions. However, these physical scaling limitations can be shifted to smaller structural dimensions by appropriate process control, e.g., choosing modified dopings in the channel and drain regions in conjunction with the spacer technique.

11.2.1.1 Channel Length Modulation For transistors with a few micrometres in channel length, the voltage-dependent extension of the drain-side space charge zone is negligible compared to the total channel length. In contrast, the influence of channel length modulation increases for short-channel transistors. The output conductance of a transistor increases sharply, i.e. the drain current of the transistor grows with increasing drain voltage in saturation mode. The cause is the drain-side space charge region. Due to the channel/drain doping ratio, the space charge region mainly expands into the channel with increasing drain voltage, thus shortening the electrically effective channel length of the transistors with increasing drain voltage. Consequently, the output conductance of the transistor increases. As compensation for this short-channel effect, higher doping of the channel region or weaker drain doping is required to reduce the width of the space charge region overall or shift its expansion to a large extent out of the channel into the drain region. It is also effective to have the shallowest possible drain/source doping to reduce the influence of the drain field on the transistor’s channel as much as possible. However, a weaker and very flat drain/source doping undesirably increases the terminal resistance of the transistor.

188

11  Developments for High-Density Integrated Circuits

11.2.1.2 Punch-Through Effect With low substrate doping, the space charge region of the drain expands into the substrate with increasing voltage. For transistors with a small channel length, this space charge region can reach the source of the transistor even before the maximum operating voltage is applied. In this case, a high drain current already flows below the threshold voltage of the transistor. The gate electrode can only weakly control the drain current, i.e. the transistor does not switch off at high operating voltage. This penetration of the space charge region from drain to source is called punch-through. It can be suppressed by an increased dopant concentration between the drain and the source of the transistor. Since the surface doping in the n-type transistor increases by the threshold voltage implantation, the space charge region from the drain essentially propagates below the channel. Consequently, to suppress the effect, doping enhancement is necessary between the drain and source terminals in the depth of the pn-junctions drain/substrate and source/substrate, respectively. In the PMOS transistor, on the other hand, the effective surface doping is very low due to threshold voltage adjustment by counter-doping with boron, but it increases with increasing depth. Consequently, the punch-through occurs directly at the interface well to oxide. Due to the low net doping of the n-well surface, the electric field emanating from the drain acts strongly on the transistor channel. The increasing extension of the space charge region into the channel also causes a decrease in the threshold voltage with increasing drain voltage (DIBL = “Drain Induced Barrier Lowering”) for components with a short channel length, irrespective of the conductivity type of the transistor. If the space charge region extends into the vicinity of the source, the channel is depleted of majority charge carriers. Compared to long channel transistors, an inversion already occurs at a lower absolute gate voltage, i.e. the threshold voltage is a function of the channel length for a given drain voltage. 11.2.1.3 Drain-Substrate Breakthrough (Snap-Back Effect) Drain, source and substrate form a parasitic lateral npn bipolar transistor whose base width corresponds to the channel length (Fig. 11.13). If impact ionisation starts due to the applied operating voltages, part of the generated holes in the n-channel transistor flow to the substrate, and the other part to the source. The holes reaching the source are comparable to an externally injected base current, switching the transistor into the on-state.

Fig. 11.13   Drain-substrate breakdown due to carrier generation in the channel (snap-back)

11.2  Advanced MOS Transistors for High-Density Integrated Circuits

189

This hole current lowers the potential barrier and leads to increased electron injection from the source area, which is sucked off by the drain as a collector. The accelerated electrons, in turn, support impact ionisation and thus further increase the hole current. The parasitic bipolar transistor can enter the conductive state already below the breakdown voltage of the drain/substrate diode.

11.2.1.4 Transistor Degradation by Hot Electrons Due to the high field strength in the drain region of the n-type transistors, electrons are accelerated very strongly. They gain enough energy to trigger impact ionisation or overcome the potential gate oxide barrier. On the one hand, this leads to a substrate current and thus to possible latch-up in integrated circuits; on the other hand, a gate current is also generated. Both effects increase the power requirement of an integrated circuit. However, a particular problem is damage to the gate oxide due to the collisions of the high-energetic electrons with the oxide’s atomic structure. Electrons can accumulate at imperfections in the oxide and, as charged bindings, reduce the maximum transistor conductance by charge carrier scattering. In addition, the gate oxide degrades because the breakdown voltage of the oxide decreases after substantial stress by injected electrons. To avoid the hot charge carriers, reducing the maximum field strength in the transistor is necessary by suppressing field strength peaks at the drain-side channel end using weak doping gradients. Alternatively, the operating voltage can be reduced. In principle, the “hot electron” effect also occurs in p-type transistors at high voltages. Still, the field strength required to generate hot holes usually only occurs well above the typical operating voltage due to their lower mobility. Thus, p-channel MOS transistors are mainly resistant to this degradation effect.

11.2.2 The Spacer Technique for Doping Optimisation 11.2.2.1 LDD n-channel MOS Transistors To reduce the field strength at the drain-side channel end—necessary to suppress the “hot electron” effect and the avalanche breakdown—a weakening of the doping gradient at the pn-junction of the drain to the channel is required. A lightly doped drain (LDD) doping profile is suitable for this purpose, which is usually fabricated using spacers in the form of side-wall spacer structures. LDD dopants have an additional positive effect on the undesirable threshold voltage drop occurring at decreasing channel length or increasing drain voltage. Additionally, the LDD profiles decrease output conductance in shortchannel transistors by reducing channel length modulation. Integrating the LDD structures into the process flow requires additional fabrication steps, which are inserted directly after the patterning of the polysilicon gate electrodes. It is based on shallow implantation to form low-doped drain/source regions, conformal oxide deposition in conjunction with subsequent anisotropic back-etching, and standard

11  Developments for High-Density Integrated Circuits

190

drain/source doping. The low dose antimony or arsenic LDD implantation creates a weak near-surface doped n-type region as the drain and source of the transistors. It exhibits only moderate conductivity and does not enable low-resistance contacting but reduces the doping gradient to the channel. The dopant concentration should be in the same order as in the transistor’s channel to keep the field strength at the pn-junction at a minimum. It is necessary to introduce further implantation in a self-adjusting manner, which increases the doping in the drain and source areas to a higher level at a defined distance from the gate. This doping is not allowed to change the weak LDD dopant concentration in the vicinity of the gate; therefore, a deposition- and back-etching technique is required. First, an oxide layer, e.g., LPCVD TEOS oxide, is conformally deposited over the entire surface at a temperature below the onset of dopant diffusion (approx. 750 °C), directly followed by a back-etching step (Fig. 11.14). In this process, the just deposited oxide is anisotropically removed in the reactive ion etching process according to the deposited thickness. At the vertical edges of the gate, the thickness of the oxide layer perpendicular to the wafer surface is higher than at the lateral surfaces. Consequently, an oxide spacer remains here on each electrode side after etching. It serves as a spacer and, in combination with the gate electrode, as a mask for high-dose arsenic implantation to produce the low-resistance, easily contactable drain and source regions. The spacer width and LDD doping parameters must be optimised to reduce the field strength in the transistor as much as possible while keeping the internal resistance of this circuit element low. Figure 11.15 shows the calculated maximum field strength in the NMOS LDD transistor, normalised to the value of a standard n-type device, versus the spacer width for different implantation doses.

a)

b)

c)

d)

e) Fig. 11.14   Spacer technique to generate LDD doping profiles. a Initial structure, b LDD doping, c conformal oxide deposition, d anisotropic etching of the oxide layer to form spacers, e crosssection of the overall structure after high dose drain/source doping

Field reduction factor

11.2  Advanced MOS Transistors for High-Density Integrated Circuits

1

191

Dose [cm-2] 1E12 5E12 1E13

0,9 0,8 0,7 0,6 0,5

0

100

200

300

400

Spacer width [nm] Fig. 11.15   Simulation of the field strength in the LDD-n-channel transistor, normalised to the value of the standard transistor, as a function of the spacer width with the LDD implantation dose as a parameter

In the process described here, an optimum field-reduction exists for LDD doping with the phosphorus ion dose of 5 × 1012 cm−2 at an energy of 80 keV and a spacer width of about 250 nm. Further widening of the spacers does not significantly reduce the field strength but only leads to an undesirable increase in the transistor’s internal resistance. To limit the expansion of the space charge region of the drain, i.e. to suppress the punch-through, a doping increase between the drain and source regions below the channel is necessary. Due to the threshold voltage implantation, the channel already exhibits a significantly increased doping compared to the substrate. Consequently, the space charge region can only extend towards the source in depth below the channel. Boron ions with about 200 keV particle energy can be implanted here before the gate electrode deposition; they locally raise the dopant concentration in this region. Their penetration depth reaches below the drain region, but the transistor threshold voltage is hardly influenced. Figure 11.16 shows the output characteristic of an LDD n-type transistor (W/L = 80 μm/0.6 μm) with 25 nm gate oxide thickness and a spacer width of 250 nm. At a drain voltage of 7 V the avalanche breakdown begins; the punch-through due to the space charge region of the drain does not yet occur even at this voltage.

11.2.2.2 P-type Offset Transistors In the simple CMOS process, n- and p-type transistors are integrated using the same phosphorus-doped gate electrodes. However, due to the work function difference between n+-doped polysilicon gate and n-silicon of the well, a buried channel forms in

11  Developments for High-Density Integrated Circuits

IDS [mA]

192

20

VGS [V]: 4

15 3 10

2

5

0

1 0 0 0,5 1

1,5 2

2,5 3 3,5 4

4,5 5

5,5 6 6,5 7 VDS [V]

Fig. 11.16   Output characteristic of an n-channel MOS transistor with 250 nm spacer width and an effective channel length of 0.6 μm (W   = 80 μm), with a phosphor LDD implantation dose of 5 × 1012 cm−2 at 80 keV

the PMOS transistor. Inversion occurs not on the silicon surface but some nanometres below after reaching the threshold voltage. In the NMOS transistor, the avalanche effect determines the maximum allowable operating voltage of the device. In the p-type MOS transistor, the punch-through is the limiting factor due to the lowering of the net doping at the wafer surface by the threshold voltage implantation. Avalanche breakdown cannot occur because of the lower charge carrier mobility. Simulations show punch-through onset in the region below the channel starting from the drain side. At the same time, the field strength is still far below the onset point of avalanche charge carrier multiplication. Additional doping in conjunction with the side-wall spacer technique can also prevent this effect. The wide propagation of the drain-side space charge region is suppressed by a local increase in the n-well doping below the channel. It forces the drain-side channel to the silicon surface directly below the gate dielectric. In the integration process, selfaligned arsenic implantation with a dose of about 3 × 1012 cm−2 at the relatively high irradiation energy of 320 keV is performed before spacer deposition for local doping increase. It penetrates sufficiently deep into the crystal in the area of the active regions, with the polysilicon gate electrode serving as a mask. The deep arsenic doping is followed by spacer fabrication in the width specified by the NMOS transistor. Drain/source implantation is done with boron. In this doping, the spacers again serve as distance holders to the gate to compensate for boron diffusion during the subsequent activation annealing. The arsenic doping is located beside the gate and below the junction of the channel to the PMOS transistor’s drain (Fig. 11.17).

11.2  Advanced MOS Transistors for High-Density Integrated Circuits

193

Fig. 11.17   Simulation of the doping profile in the PMOS short channel transistor with additional arsenic implantation in the spacer region to suppress the punch-through effect (section from the centre of the channel to the drain)

However, unlike the NMOS transistor, no LDD profile has been established here. The local doping increase in the n-well restricts the space charge extension into the channel region close to the drain. A further extension to the source causing a parasitic current path is prevented. Additional measures to improve the short-channel behaviour are unnecessary for the p-type MOS transistor; the breakdown strength is sufficient for the typical operating voltage of 5 V for these channel lengths. The subsequent temperature steps for dopant activation cause a diffusion of the implanted boron laterally under the spacers. In the optimised process, the time of this annealing is chosen such that the boron atoms reach precisely the edge of the gate electrode. Consequently, the spacers of the PMOS transistors cause a reduction in the parasitic gate/drain and gate/source capacitances, with the effective channel length of the transistor corresponding very closely to the patterned gate length as a result of the lack of under-diffusion. The additional arsenic implantation prevents punch-through due to a localised near-surface doping increase and mitigates the threshold voltage drop with decreasing transistor channel length. Figure 11.18 compares the leakage current behaviour of the “offset transistor” with arsenic implantation described above versus a comparable standard p-type transistor as a function of the effective channel length. Due to the offset implantation, the leakage current decreases by more than two orders of magnitude (Fig. 11.19). In conclusion, applying the spacer technique enables a reproducible integration of pand n-type MOS transistors with sub-µm channel length. The minimum channel length is about 0.5 μm, limited by the operating voltage of 5 V and the existing photolithography technique. However, only applying LOCOS technology enables the transfer of these fine structures into a resist mask using optical lithography. It prevents photoresist thickness

11  Developments for High-Density Integrated Circuits

Drain current [µA]

194 103

Offset - Impl. Standard

102 101

VDS = -5V VGS = 0V W = 100µm

100 10-1 10-2 10-3

0

1

2

3

4 5 6 7 8 9 10 Effective transistor length [µm]

Fig. 11.18   Measurement of leakage current as a function of transistor channel length for the standard FET integration and the offset transistors with additional arsenic implantation

Fig. 11.19   Output characteristic of a p-channel offset transistor with additional deep arsenic implantation to suppress space charge zone penetration and mitigate short channel effects (W/L = 100  μm/0.6 μm)

variations at steps on the wafer surface. Further improvements can be achieved through the STI isolation technique giving complete planarisation, reduced pn-junction’s depths and gate oxide thickness so that today’s integrated circuits allow MOS structures with 12 nm channel length or less.

11.2  Advanced MOS Transistors for High-Density Integrated Circuits

195

11.2.3 Self-Aligned Contacts Self-aligned contacts are fabricated in the CMOS process after spacer patterning or ion implantations for doping the drain/source regions. The process enables a self-aligning, low-impedance contacting of the drain and source electrodes in combination with a drastic reduction of the parasitic wire resistances of the gate electrodes and conductive tracks made of polysilicon. Additionally, the space required for device integration shrinks as the previously required safety distances from the contact opening to the diffusion edges are eliminated; the contact area drain/source to the metallisation can also be reduced. The integration of self-aligned contacts typically uses metals as contact material, sputtered onto the wafer’s entire surface. During thermal treatment, the metal forms a highly conductive silicide at all contact points with the silicon. However, the silicide reaction occurs only selectively on the silicon, not on silicon dioxide. Consequently, the metal silicides are formed only on the exposed drain and source surfaces, the polysilicon gate electrodes and conductor tracks. The common materials used for silicides are titanium, cobalt, palladium, platinum and nickel, with titanium, nickel and cobalt being the most widely used. Before sputtering the metal, an etching step is required to remove the residual oxide on the drain/source areas and polysilicon tracks to guarantee direct contact of the sputtered layer with the silicon. Some metals like titanium or nickel can reduce a thin oxide layer, but uniform silicide formation will not occur without this oxide etch step. Contacting with titanium requires a two-step silicide process to create self-aligning contacts (Fig. 11.20). After the metal deposition on the whole wafer surface, the first step is annealing at approximately 650 °C to form a TiSi2 layer (C49 phase) at the metal/silicon interface. Oxide surfaces do not yet react with the titanium film at this temperature, so a pure metal film continues to be present on the field oxide and spacers. This excess

a)

b)

c)

d)

Fig. 11.20   Integration of self-aligned contacts with titanium. a transistor structure with spacer, b oxide etching of diffusion regions and polysilicon, c titanium coating and silicide creation by annealing, d selective etching of the pure metal and TiSi2 formation

11  Developments for High-Density Integrated Circuits

196

material is removed selectively from the silicide by wet etching in NH4OH/H2O2/H2O solution. A further temperature step at approximately 750 °C follows. The higher temperature treatment converts the TiSi2 into a highly conductive TiSi2 layer (C54 phase) both in the contact area and on the polysilicon. Thus, the entire area above the drain and source regions is contacted via the highly conductive TiSi2 film so that the contact hole location no longer dictates the current path. The temperature steps for silicide formation are carried out as short vacuum annealings in an RTA process to avoid influences of the surrounding atmosphere. Direct creation of TiSi2 in the C54 phase by applying a single temperature step is not possible because a reaction of the titanium with the field oxide or spacers already starts at 750 °C. It prevents the removal of the excess titanium and thus forms shorts between the gate and drain/source electrodes via silicides on the oxides (Table 11.1). Furthermore, in the case of titanium, too long annealing times lead to silicon diffusion from the substrate into the metal layer on the spacers. A silicide also forms on the oxide edges close to silicon surfaces. The reacted titanium in these areas can no longer be selectively removed, and a short circuit occurs due to bridging (“bridge effect”) between the drain or source and the gate. In contrast, the metal diffuses into the silicon in the case of cobalt and nickel. So bridging does not occur even after long annealing times. The required temperature for the silicide process depends on the type of dopant used and the dopant concentration in silicon. While boron doping only weakly affects the silicide reaction, metal silicide formation on silicon with a high phosphorus or arsenic concentration above 1 × 1018 cm−3 requires a considerably higher process temperature. The natural surface oxide also has a disturbing effect. Cobalt requires a completely oxide-free silicon surface to form a highly conductive silicide. With titanium and nickel, at least the required reaction temperature increases in case of oxide residues on the surface, and in addition, the resulting silicide layer thicknesses are uneven.

Table 11.1  Silicides for self-aligning contacts in semiconductor technology with their properties [8] Silizide

Titanium TiSi2 C49

TiSi2 C54

Cobalt CoSi

CoSi2

Nickel NiSi

NiSi2

Temperature [°C]

550

750

400

550

350

750

Specific resistance [µΩcm]

65

13–16

80

10–18

20

40

Selective etchant

NH4OH/H2O2

HNO3

H2SO4/H2O2

Oxide reduction

Yes

No

Yes

Segregation

Strong

Weak

Weak

11.3  SOI Techniques

197

Unlike other metal silicides (Pt-, Co-silicides), titanium silicides are not resistant to hydrofluoric acid. Consequently, contact openings in an oxide on top may only be produced by dry etching, e.g. with CHF3/Ar as the reaction gas. Since the self-aligned contact process consumes silicon from the wafer, silicide contacting of shallow pn-junctions can lead to shorts with the substrate. For each nanometer of metal deposited, 2.27 nm of silicon is converted for TiSi2, and 3.52 nm for CoSi2. If the silicide reaches the pn-junction depth, the device is destroyed. Silicide formation of titanium on polysilicon tracks below 0.35 μm width tends to have agglomeration effects. No continuous high-conductivity silicide film is formed, but instead, continuously interrupted highconductivity sections are created in the polysilicon wire. This effect occurs neither with nickel nor cobalt since here, in contrast to titanium, the metal diffuses during the silicide process, but not the silicon. The segregation effect also occurs during silicide formation. Depending on the metal used, the dopants dissolve more strongly in the metal silicide, so the highly doped drain and source regions are depleted of dopant atoms. The effect depends on the temperature and duration of the thermal treatment and the dopant type. The silicide reaction gives low-resistance metal-semiconductor junctions and highly conductive polysilicon tracks if the process is carefully done. It enables the integration of self-aligned contacts, which are required, on the one hand, for the highest switching speeds and, on the other hand, for reducing the contact hole dimensions and, thus, the chip area.

11.3 SOI Techniques A central problem of conventional integrated circuits is the inevitable degradation of the electrical properties of MOS transistors with decreasing structure size due to the threshold voltage fall-off, the punch-through and the latch-up effect. Additionally, the parasitic capacitances between the drain/source regions and the substrate increase. The capacitances grow disproportionately concerning the reduced transistor size. Silicon on insulator (SOI) technology solves this problem by fabricating each transistor device in a thin, fully isolated silicon island. As a result of the lack of inter-island connections, no latchup effect can occur. Since the active function of the transistor is confined to the thin silicon film, short-channel effects are mitigated. Another advantage is the low leakage currents of the pn-junctions source/substrate and drain/substrate. Due to the comparatively small area of the pn-junctions, higher reverse currents are permissible, enabling applications of CMOS switches at elevated operating temperatures of up to at least 250 °C.

11.3.1 SOI Substrates SOI techniques can be divided into crystal-based methods and recrystallisation techniques. The crystal-based SOI techniques use the single-crystalline silicon wafer as a

11  Developments for High-Density Integrated Circuits

198

film material by creating a buried insulator below the wafer surface. In contrast, recrystallisation processes generally use oxide layers as insulators with an amorphous or polycrystalline silicon layer on top. The layer is deposited, melted by applying energy and converted into crystalline films.

11.3.1.1 FIPOS—Full Isolation by Porous Oxidized Silicon The FIPOS technology uses the high oxidation rate of porous silicon layers to generate single-crystal silicon islands in an oxide insulator. Since only p-type silicon can be sufficiently etched porous, a weakly boron-doped substrate must be available as the substrate material. The wafers are coated with silicon nitride, and the nitride patterning is carried out using a photo technique in a dry etching process as the starting point to generate the SOI structure. In this process, the later silicon islands remain covered with nitride, and the photoresist is also not removed after etching. Beyond these masked areas, deep boron implantation with a high dose strongly raises the surface doping in the field area next to the nitride covers (Fig. 11.21).

a)

b)

c) Fig. 11.21   Process sequence of the FIPOS technique to generate SOI layers from single crystal wafers. a photoresist masking for island definition and p+ implantation, b full-area proton implantation for local doping inversion, c thermal oxidation of the porously etched silicon for dielectric isolation of the islands

11.3  SOI Techniques

199

The weakly p-type silicon below the nitride layer must be protected from electrochemical etching to convert the single-crystal material into porous silicon. It is converted into an n-type state by low-dose hydrogen ion or proton implantation. No doping reversal should occur in the p + regions due to the inserted limited amount of hydrogen. In the following anodic etching step in diluted hydrofluoric acid, the p-type silicon—independent of the dopant concentration level—transforms into a porous material a few micrometres deep; n-type silicon, on the other hand, does not change. The etching process also leads to porous silicon below the n-type islands so that the n-conducting regions are entirely separated from the substrate [9]. Due to the high pore density, the porous material can be thermally oxidised quickly; it forms an electrical insulator of silicon dioxide in which the silicon islands are embedded. Parallel to oxidation, the implanted hydrogen diffuses out of the islands due to the high process temperature. The islands return to the p-type state and are then available as SOI material for circuit integration. The disadvantage of this technique is the occurring wafer distortion caused by the different thermal expansion coefficients of the resulting thick oxide layer and the silicon as the substrate. In addition, the silicon island size is limited by the lateral undercutting of the islands caused by oxidation. The achievable integration density is extremely low as a result of the lateral oxidation of the islands.

11.3.1.2 SIMOX—Silicon Implanted Oxide A successful method for fabricating high-quality single crystalline SOI films relies on high-dose ion implantation of oxygen into weakly doped n- or p-type silicon wafers to create a buried, electrically insulating layer of SiO2 below the wafer surface. The average penetration depth of the ions must be about 150 nm to produce a sufficiently thick silicon top layer on an electrically stable insulator. The required Si:O stoichiometric ratio needs an oxygen ion dose of 1.5 × 1018 cm−2 (atomic oxygen) at particle energies between 150 and 200 keV. In this case, the energy transfer of the ions to the crystal leads to extreme thermal stresses on the silicon wafer during implantation; in addition, considerable

a)

b)

Fig. 11.22   Generation of an SOI substrate by implantation of oxygen ions. a as implanted and b after annealing

200

11  Developments for High-Density Integrated Circuits

radiation damage to the crystal occurs up to near-surface amorphisation of the substrate (Fig. 11.22). The wafer must be heated to at least 400 °C during implantation to avoid radiation damage or amorphisation caused by ion bombardment. The created lattice defects heal instantaneously, and the crystalline state of the silicon film above the insulating layer maintains. However, the single-crystalline capping layer exhibits a high dislocation density because the high-dose implantation damages the crystal lattice despite substrate heating. Furthermore, the oxygen atoms remaining in the crystalline capping layer act as binding defects. Together with the other defects, they reduce the charge carrier mobility in the substrate. Below the silicon top layer, the implanted ions are initially not distributed stoichiometrically to the silicon, resulting in an atomic oxygen distribution with a concentration maximum at a depth of the projected range of the ions. Thus, a homogeneous, electrically stable insulating layer cannot form immediately inside the silicon wafer. An increase in the quality of the SOI structure can be achieved by annealing at a high temperature in an inert gas atmosphere. At 1300 °C, a large part of the crystal defects heals. Furthermore, the buried oxide layer is compacted with the incorporation of oxygen atoms from the silicon top layer to form an electrically resilient, homogeneous insulator that meets semiconductor technology requirements. The complex manufacturing process due to the high-dose ion implantation is a significant disadvantage of the SIMOX technique. Even a modern high-current implantation facility requires more than an hour of irradiation time to implant a 150 mm diameter wafer. Also, the silicon film and the buried insulator uniformity are limited due to limited homogeneities in the ion distribution during the implantation. Nevertheless, the industry uses these SOI substrates for special applications, e.g. to dielectrically separate thermally stressed or high-voltage parts of an integrated circuit from the standard components on the same chip.

11.3.1.3 Wafer Bonding The wafer bonding process starts with two thermally oxidised polished silicon wafers. The surfaces are coated with OH-groups, attached by treatment in H2SO4/H2O2 solution. Both wafers form a bond by placing the wafers next to each other and applying slight pressure. The adhesive bonding can be converted into a mechanically strong bond in a pure temperature step or by anodic bonding. Subsequent etching of one of the two wafers to a few micrometres thickness delivers a crystalline silicon layer on a SiO2 insulator. The connection of the wafers can be carried out with field support by applying a voltage (approx. 500 V) to the wafers at a relatively low temperature of approximately 500 °C via anodic bonding. Still, it is also carried out by thermal oxidation in a pure oxygen atmosphere at 1000 °C [10]. The two wafers must be linked over their entire surface

11.3  SOI Techniques

201

without any interruptions because local distortions may lead to local split-offs of the SOI layer. After the two silicon wafers are joined, one wafer serves as the substrate, while the other is etched back electrochemically or purely by wet chemical etching. Fluctuations in wafer thickness have a negative effect because a uniform silicon film must remain on the oxide. Uniformity can be achieved by creating a pn-junction in the wafer to be etched before the bonding process so that the ablation can be carried out selectively. The depth of the junction defines an etch stop at the position of the space charge region (Fig. 11.23). Alternatively, the implantation of a dose of 1 × 1016 cm−2 hydrogen ions into one of the two wafers to be bonded is an option. Subsequently, the bonding process is carried out by thermal oxidation. During a subsequent temperature step, the implanted wafer bursts off in the region of the range of the hydrogen ions due to internal stresses. A thin homogeneous silicon film remains on the oxide of the carrier wafer, which is available as an SOI layer after surface polishing. This relatively new process is known as “Smart Cut”. SOI substrates with 300 mm diameter, produced by wafer bonding, are commercially available and, comparable to SIMOX substrates, are used in industrial processes. One example is SOI-CMOS circuits for operating temperatures up to 250 °C. However, microprocessors with high clock rates now also use SOI materials.

11.3.1.4 ELO—Epitaxial Lateral Overgrowth A thermally grown oxide film is patterned on the silicon wafer to form islands in the epitaxial lateral overgrowth technique. These oxide islands are covered by lateral crys-

a)

b)

c)

Fig. 11.23   Generation of an SOI film by wafer bonding. a oxidised wafers, b bonded wafers and c SOI substrate after etching back a silicon wafer

202

11  Developments for High-Density Integrated Circuits

tal growth in a subsequent selective epitaxy process starting from the silicon substrate. In gas-phase epitaxy, crystalline silicon can only grow on the uncovered silicon. In the oxide areas, multiple nucleations occur, leading to polycrystalline growth. Polysilicon, however, can be etched back much faster than single crystalline material. Consequently, selective epitaxial growth leads to crystalline silicon starting from the oxide openings. The lateral overgrowth begins at the edges of the oxide islands leading to an SOI film extending on the oxide. SOI structures of more than 10 μm width are entirely overgrown, either in selective epitaxy or in a sequence of deposition and etching back processes (Fig. 11.24). The resulting surface must be ablated by polishing for planarisation to achieve a constant semiconductor thickness on the oxide islands. The limited overgrowth of the oxide severely limits the SOI area, but it exhibits good layer quality. However, the enormous fabrication effort has prevented industrial use of the technique.

11.3.1.5 The SOS Technique The silicon-on-sapphire (SOS) technique is a heteroepitaxial growth process. By using silicon gas phase epitaxy, a single-crystal silicon layer is grown on crystalline insulators such as sapphire (Al2O2) or spinel (MgAl2O4). Sapphire and spinel exhibit an atomic arrangement comparable to silicon at specific crystal cuts on the surface. Single-crystalline films of about 1–2 μm thickness can then be deposited on these insulators in gasphase epitaxy. In the dry etching process, these films are patterned into individual silicon islands suitable for device integration. Because silicon and sapphire or spinel lattice constants are not precisely the same, mechanical stresses occur at the insulator/semiconductor material interface. They cause disturbances in the growing crystal, and in addition, the density of the unsaturated bonds increases, which has the effect of interfacial charges in the device. Despite intensive research over many years, these problems could not be eliminated entirely until today. SOS technology is only used in a few special applications, such as a magnetic field-sensitive diode. 11.3.1.6 SOI Layers by Recrystallisation Processes An SOI layer can also be created by depositing high-purity silicon on an insulating substrate, followed by a high-performance recrystallisation process. The insulating layer, mostly SiO2, should be as thick as possible to avoid capacitances to the substrate; a thick

Fig. 11.24   Local SOI areas produced by lateral epitaxial overgrowth of oxide (ELO process)

11.3  SOI Techniques

203

layer also reduces heat conduction from the surface film structure towards the substrate during recrystallisation. Thermally oxidised single-crystalline silicon wafers are almost always used as the substrate material in order to avoid mechanical stresses due to the different expansion coefficients of the materials. Depending on the deposition technology applied, the active silicon layer is deposited on the oxide in a polycrystalline or amorphous state. The pyrolytic deposition with SiH4 in the LPCVD process, which is widely used in silicon gate CMOS technology, and the plasma-assisted deposition are suitable. The LPCVD process produces polycrystalline silicon films at temperatures above 580 °C; an amorphous layer is formed at lower temperatures. However, the deposition rate is only sufficiently high, above approximately 600 °C, to deposit sufficiently thick films in a reasonable time. Consequently, only PEVCD deposition at about 300 °C is applicable for amorphous silicon films. The recrystallisation of the deposited films is achieved by scanning the wafer surface with high-energy radiation. Suitable heat sources are laser beams, the focused light of a tungsten lamp or a graphite heat emitter, or irradiation with a high-energy electron beam. In these processes, the silicon wafer is preheated from the rear side to approximately 500 °C up to 1250 °C to support the recrystallisation process; the remaining energy required for melting is supplied by the radiation source (Fig. 11.25). Laser and electron beam recrystallisation scans the focused beam over the surface (heated to about 500 °C from the rear side) line by line or in a meandering pattern. Lamp recrystallisation and the graphite heat emitter require only a single scan to treat the entire surface. However, since their energy transfer is very low, the sheet must first be heated to approximately 1250 °C from the rear side. In the recrystallisation processes, the “seeding technique” can determine a specific crystal orientation. At the starting point of the annealing treatment, the silicon film is in direct contact with the substrate, at whose surface epitaxial recrystallisation begins. While maintaining the crystal orientation, this process continues in a lateral direction across the isolation oxide for several millimetres on the wafer.

Fig. 11.25   Laser recrystallisation of a deposited amorphous or polycrystalline silicon film

11  Developments for High-Density Integrated Circuits

204

All the recrystallisation processes mentioned above provide only SOI layers of limited quality since the size of the single-crystalline regions is, at most, a few square centimetres. Nevertheless, transistors and circuits with good quality have been produced in these substrates. In particular, laser and electron beam recrystallisation enable 3D-integration because the substrate temperature during recrystallisation is very low. Consequently, structures already realised in buried layers cannot diffuse out and preserve their function.

11.3.2 Process Control in SOI Technology SOI substrates enable a simplified integration technique for CMOS circuits because the transistors are fabricated in fully isolated thin silicon islands. This eliminates the need for post-diffusion to create a well or field oxidation. A simple schematic of an SOI CMOS process is shown in Fig. 11.26. Starting from the full-surface SOI film, nitride deposition and—with photoresist as a mask—island structuring is carried out first. Two process variants are available:

a)

b)

d)

e) Fig. 11.26   Process control of the SOI integration technique. a encapsulated polysilicon film as initial structure, b islands after recrystallisation, patterning and doping, c oxidation of the edge oxide, removal of the nitride mask and gate oxidation, d cross-section after patterning of the gate electrodes and dopants for the drain/source regions, and e section through the SOI structure after metallisation

11.3  SOI Techniques

205

• in the dry etching process, the silicon can be removed entirely between the islands, or • approximately 55% of the film thickness of the silicon is removed by the dry etching process, while the residual layer between the islands is subsequently converted into an oxide by the LOCOS process. The islands are then doped with boron or phosphorus according to the transistors to be accommodated. Dopants are implanted selectively close to the surface, centrally or at the bottom of the silicon film, controlled by the ion energy. The nitride is removed directly after oxidation and implantations when the LOCOS process is used. In contrast, an enhanced flank oxide first grows up in a humid atmosphere in the first process variant. This oxide prevents parasitic current paths on the vertical walls of the silicon islands. The nitride stripping is followed by thermal gate oxidation, polysilicon deposition, and patterning in the RIE dry etching process. Drain/source implantation is performed with boron and arsenic, respectively, before intermediate oxide deposition, contact hole opening, metallisation and metal patterning complete the SOI process. As a result, MOS transistors integrated into individual semiconductor islands and entirely electrically isolated from the buried silicon crystal are available so that neither the latch-up effect nor punch-through effect across the substrate can occur. Also, shortchannel effects are significantly mitigated due to the altered field distribution in the tightly confined silicon layer. As a result of the missing substrate contact, however, a changed behaviour can be observed in the output characteristic of the transistors. At a drain voltage of a few volts, an offset in the current–voltage characteristic occurs in the saturation region, which is largely independent of the gate voltage (“kink effect”). In the n-channel transistor, charge carrier generation in the channel leads to an additional hole current. The generated holes cannot flow towards the substrate contact but move towards the source. Consequently, the potential below the gate electrode decreases and the effective gate voltage increases. Especially for analogue circuits, a fourth terminal must be provided in the channel area to contact the silicon substrate. After years of development work, SOI technology was initially only able to establish itself in niche areas such as high-temperature electronics. Today, however, microprocessors are manufactured as mass products using this technology because of the very high switching speeds achieved. As a result of the low junction and stray capacitances to the substrate, particularly low-loss high-frequency circuits can be realised here.

11.4 Transistors with Nanometer Dimensions 11.4.1 Requirements for Further Scaling To further miniaturise circuit elements for channel lengths down to 12 nm and below, as predicted by the Semiconductor Industry Association [7], the following steps are imperative:

206

• • • •

11  Developments for High-Density Integrated Circuits

a further reduction of the gate oxide thickness; an increase in channel doping; the reduction of the doping depths; a reduction in lateral dopant diffusion during activation annealing.

Fig. 11.27   Dielectric constant of various metal oxides and bandgap in eV as an overview for the selection of future dielectrics [12]

Band gap ( eV)

Depending on the intended operating voltage, reducing the gate oxide thickness to a minimum of 2.5–3 nm SiO2 is possible until the tunnel effect causes a gate current. Thinner oxides increase the power dissipation in integrated circuits due to the increasing tunnel current. However, publications show that even gate oxide layers as thin as 1.5 nm are suitable for integrating transistors with small gate areas [11]. Nitrided oxides, grown in N2O or O2/NH3 atmosphere, show higher electrical stability than pure SiO2 layers, thereby significantly reducing the tunnelling current. However, these currents increase strongly below 2 nm oxide thickness, so no significant reduction of the gate oxide layer is possible (Fig. 11.27). Further scaling of the gate oxide thickness, as required by transistors with less than 30 nm gate length, is thus only possible by transitioning to layers with significantly higher dielectric constants. Promising materials for future gate dielectrics are oxides of aluminium, zirconium or hafnium deposited in combination with silicon or nitrogen, e.g., HfSiON in the ALD process [13, 14]. Especially HfO2, with a dielectric constant of 18, is already used in microprocessors. An extremely thin oxide layer of less than 0.5 nm can still be present under the metal oxide to achieve a low interfacial charge density at the transition to the semiconductor. It is partly formed by natural oxidation during metal oxide deposition. A further dielectric constant increase is possible by transitioning to TaO5 or TiO2. Ferroelectric materials with ε ~ 500 at layer thicknesses of approx. 50 nm is also under development to achieve oxide-equivalent thicknesses of less than one nanometer. A drastic increase in channel doping is necessary at these low gate oxide thicknesses to adjust the threshold voltage. At the same time, strong channel doping restricts the extension of the space charge region of the drain into the channel; channel length modulation and the drain voltage-induced threshold voltage drop are mitigated. However, the

Dielectric constant

11.4  Transistors with Nanometer Dimensions

207

transistor trans conductance decreases due to reduced carrier mobility resulting from more frequent scattering of electrons by dopant atoms in the crystal lattice. The doping below the channel must also be raised to suppress the punch-through effect in the n-channel transistor. It requires boron implantation with increased energy, which prevents the space charge region from propagating from the drain to the source. Parallel to channel doping, the LDD doping of the NMOS transistors must be raised to ensure reliable lateral contacting of the channel. The LDD doping must extend only a few nanometers deep into the crystal; otherwise, parasitic effects such as the threshold voltage drop induced by the drain voltage or the punch-through susceptibility of the transistors increase. The simultaneous growth of the channel and the LDD doping concentrations leads to high drain-side field strength, favouring avalanche breakdown. Consequently, the allowable operating voltage of these nanometer-scale devices must decrease. Because the power dissipation of a circuit depends on the square of the operating voltage, the power consumption of the integrated components also decreases. Since lateral scattering of the dopant ions under the gate electrode occurs during implantation of the LDD regions due to the collisions with the lattice atoms, the irradiation energy must be kept very low. A heavy element such as antimony exhibits a low penetration depth combined with extremely low lateral scattering. Consequently, this element should be used for LDD implantation. In contrast, arsenic is still required for the high drain/source dopants; the solubility of antimony in silicon is insufficient to produce a concentration suitable for low-resistance contact with the metal. The temperature load for dopant activation must be very low to avoid diffusion effects. Diffusion of only 10 nm is no longer tolerable for geometric channel lengths of 30 nm. For NMOS transistors with arsenic dopants, thermal loads of 900 °C for 10 min are permissible; in the PMOS transistor, this treatment already leads to a short circuit between the drain and source. Here, a maximum load of 800 °C for 2 min is permitted (Fig. 11.28).

Fig. 11.28   Scanning electron micrograph of the gate electrode and output characteristic field of an NMOS transistor with 60 nm channel length and 4.5 nm gate oxide thickness

208

11  Developments for High-Density Integrated Circuits

11.4.2 Analysis of Nanometer-Scale n-type Field-Effect Transistors Due to the inclination of the wafer by 7° to the ion beam to suppress the channelling effect during ion implantation, shadowing by the gate electrode occurs during irradiation. The low diffusion width during activation of the dopants causes a non-controllable region between the shaded side of the channel and the LDD region. On the one hand, the transistor only conducts at an increased drain or gate voltage; on the other hand, an asymmetry of the transistors occurs concerning the swapping of drain and source. This effect can be avoided by perpendicular irradiation of the wafer or by rotating the wafer during ion implantation. The number N of dopant atoms in the channel region of these transistors with 0.05 μm2 gate area is only about 1000. Since the implantation causes a statistical distribution of ions, this number is subject to an error of magnitude N1/2. This statistical deviation causes a variation of the threshold voltage σUt:

1 σ Ut ∼ √ WL

(11.7)

i.e. the deviation of the threshold voltage from the mean value increases with decreasing gate electrode area. Measurements can demonstrate the effect on closely adjacent arrays of identical transistors. The respective transistor arrays differ in widths and lengths with otherwise identical process parameters. Figure 11.29 shows the increase in threshold voltage deviation with decreasing gate electrode area. While the scatter is still low for the transistors with 10 μm2 gate electrode area, the value for 0.14 μm2 electrode area already grows to 22 mV. For transistors with W = L = 50 nm, this value rises to more than 100 mV; the safe operation of circuits can no longer be guaranteed with this strong scattering of Ut. Although all transistors were integrated on one chip, in Fig. 11.29 the transistors with 1 μm channel length show a higher threshold voltage than those with 70 nm length. The reason is the threshold voltage drop with decreasing transistor channel length due to the increasing influence of the drain on the channel area. A reduction of the transistor width leads to increased threshold voltage due to the growing influence of the field area on the channel. Since other transistor parameters like transconductance or subthreshold slope have corresponding distributions depending on the channel area, the characteristics of these extremely small circuit elements with a few 10 nm2 gate electrode areas can no longer be specified precisely but only with probabilities. Consequently, the integrated circuits to be developed in the future must be tolerant to these uncorrelated variations of the transistor parameters.

11.4  Transistors with Nanometer Dimensions

209

Fig. 11.29   Gate area dependence of the transistor threshold voltage and the threshold voltage variation

11.4.3 The FINFET in SOI Technology A special design of modern field-effect transistors is the FINFET structure. Besides the surface channel, the device uses two controllable channels in the vertical direction. For this purpose, the silicon film of an SOI substrate is patterned into approximately 10–20 nm wide fins. The surface of the fins is subsequently coated with a gate dielectric by ALD deposition. The gate electrode covers the lateral fin surface, and additionally, it controls a channel on each of the vertical flanks of the fin. The channel width extends into the depth; the conductivity of the transistor increases while the area required remains the same. Figure 11.30 shows the fabrication and schematic structure of such a transistor. The advantage of the SOI substrate in this transistor is the low gate capacitance due to the oxide film under the gate electrode, combined with minor junction capacitances of the drain and source electrodes. The transistor’s channel width consists of the fin’s width at the surface plus twice the fin height. As a result of the SOI substrate, the fin height and thus the channel width can be produced very uniformly and reproducibly since the buried insulator acts as an etch stop. Due to the small width of the fin, the semiconductor material is entirely free of mobile charge carriers. There are almost no dopant atoms or thermally generated charge carriers in the small volume. The mobile charges forming the channel below the control electrode are injected from the drain and source regions.

210

11  Developments for High-Density Integrated Circuits

Fig. 11.30   Fabrication of a FINFET on SOI substrate

11.4.4 FINFET in the Standard Silicon Substrate SOI substrates are comparatively expensive, which significantly impacts the price of SOI integrated circuits. The integration of FINFETs on substrate silicon wafers is more costeffective, but the process described above cannot be transferred directly. A disturbing factor is the high gate capacitance, which acts outside the fin to the substrate without suitable countermeasures. Therefore a thicker oxide film must be introduced for capacitance reduction next to the fin between the substrate and the gate electrode. In the process, the fin is first etched from the single-crystalline silicon substrate, with the etch depth being composed of the desired fin height plus the oxide thickness. The entire wafer surface is covered with CVD oxide and planarised using chemical mechanical polishing. After planarisation, selective wet etching of the oxide according to the desired fin height follows. The gate dielectric and gate electrode are deposited afterwards. Figure 11.31 Shows a schematic cross-section of the substrate FINFET.

11.5  Tasks for High-Density Integrated Circuits

211

Photoresist

Si fin

Silicon

Silicon

SiO2 Silicon

Silicon S D

G

Silicon

Fig. 11.31   FINFET in the substrate: resist mask, patterning of the fin, oxide deposition and CMP, gate oxidation and polysilicon deposition

11.5 Tasks for High-Density Integrated Circuits Task 11.1 A field oxide of 1 μm thickness is to be applied by local oxidation. For this purpose, wet oxidation is carried out at 1100 °C. What is the minimum thickness of the nitride mask required to ensure that the silicon in the active area is not oxidised? If a nitride mask with a maximum thickness of 20 nm is used, the underlying pad oxide can be dispensed because the risk of lattice disturbances due to mechanical stresses is low with such a thin nitride mask. Calculate the maximum field oxide width achievable with this nitride mask by wet thermal oxidation at 1100 °C? Task 11.2 The parasitic series resistance of an NMOS LDD transistor with and without self-aligned contacts through titanium silicide will be calculated and compared. The transistor has a W/L ratio of 10 μm/2 μm. The LDD regions have a depth of 50 nm and a doping con-

212

11  Developments for High-Density Integrated Circuits

Fig. 11.32   Input characteristics for transistors of different channel lengths

centration of 1018 cm−3. The drain/source regions have a depth of 100 nm at a concentration of 1020 cm−3. The spacer width is 200 nm, and the contact holes are located at a distance of 2 μm from the gate. The gate controls the LDD region, so its resistance is not included in the parasitic series resistance. Calculate the parasitic series resistance of the transistor for the case of standard contacting and for the case when self-aligning contacts are formed with titanium. Task 11.3 Figure 11.32 shows the input characteristics of four transistors with a uniform gate oxide thickness at a constant channel width of 100 μm each. The curves were recorded at a drain-source voltage of 0.1 V. The design dimension LDesign of each transistor is written next to the curves. Since all transistors are on the same wafer, the deviation ΔL from the design length is constant. Determine ΔL by comparing the slopes of the transistors!

References 1. Ruge, I.: Halbleiter-Technologie, Series Halbleiter-Elektronik, vol. 4. Springer, Berlin (1984) 2. Isomae, S., Yamamoto, S., Aoki, S., Yajma, A.: Oxidation-induced stress in a LOCOS structure. IEEE Electron Device Lett. 7, 368–370 (1986) 3. Kooi, E., van Lierop, J.G., Appels, J.A.: Formation of silicon nitride at a Si-SiO2 interface during local oxidation of silicon and during heat-treatment of oxidised silicon in NH3 gas. J. Electrochem. Soc. 123, 1117–1123 (1976) 4. Sakuma, K., Arita, Y., Doken, M.: A new self-aligned planar oxidation technology. J. Electrochem. Soc. 134, 1503–1507 (1987)

References

213

5. Hui, J.C., Chiu, T., Wong, S.S., Oldham, W.G.: Sealed interface local oxidation technology. IEEE Trans. Electron Devices. 29, 554–561 (1982) 6. Chiu, K.Y., Moll, J.L., Manoliu, J.: A bird’s beak free local oxidation technology feasible for VLSI circuits fabrication. IEEE J. Solid State Circuits. 17, 166–170 (1982) 7. ITRS:  https://www.semiconductors.org/clientuploads/Research_Technology/ITRS/2015/ 0_2015%20ITRS%202.0%20Executive%20Report%20(1).pdf (2015). Zugegriffen: 1. Juli 2018 8. Jackson, K.A.: Processing of semiconductors. In: Cahn, R.W., Haasen, P., Kramer, E.J. (Hrsg.) Materials Science and Technology, Vol. 16. VCH-Verlag, Weinheim (1996) 9. Imai, K., Unno, H.: FIPOS (Full Isolation by Porous Oxidized Silicon) technology and its application to LSI’s. IEEE Trans. Electron Devices. 31, 297–302 (1984) 10. Tong, Q.-T., Gösele, U.: Semiconductor Wafer Bonding. Wiley, New York (1999) 11. Momose, H.S., Ono, M., Yoshitomi, T., Ohguro, T., Makamura, S., Saito, M., Iwai, H.: 1.5 nm direct-tunneling gate oxide Si MOSFET’s. IEEE Trans. Electron Devices. 43, 1233–1242 (1996) 12. Robertson, J.: High Dielectric Constant Oxides. EDP Sciences, Cambridge (2004) 13. Doering, R., Nishi, Y.: Semiconductor Manufacturing Technology. CRC Press LLC, Boca Raton (2008) 14. Engström, O., Raeissi, B., Hall, S., Buiu, O., Lemme, M.C., Gottlob, H.D.B., Hurley, P.K., Cherkaoui, K.: Navigation aids in the search for future high-k dielectrics: physical and electrical trends. Solid State Electron. 51, 622–626 (2007)

Bipolar Technology

12

Compared to MOS devices, bipolar transistors have high switching speeds well into the 100 GHz range in conjunction with large transconductances and, thus, excellent driver characteristics. However, the area requirement of these circuit elements is very high compared to the MOS structures due to the required insulations—at least in the SBC (“standard buried collector”) techniques. This disadvantage can be eliminated mainly in advanced bipolar technology with selfaligned emitter and base contact diffusions applying trench isolation. It enables good driver characteristics and reduced switching times in conjunction with a relatively high packing density. In addition, there are severe disadvantages of high process complexity due to the critical epitaxy technique for generating a buried subcollector or the thin base layer. Compared to MOS technology, bipolar technology is characterized by the following typical process features: • • • • • •

buried highly conductive layer as a subcollector; use of weakly doped epitaxial layers; oxide-masked diffusions instead of ion implantations for local doping; polysilicon is not required in the primary process; no self-isolation due to blocking pn-junctions; relatively low packing densities since area-intensive insulation diffusions or oxidations are necessary; • load resistors consist of the base or emitter diffusion regions; • capacitances are created using junction capacitances.

© Springer Fachmedien Wiesbaden GmbH, part of Springer Nature 2023 U. Hilleringmann, Silicon Semiconductor Technology, https://doi.org/10.1007/978-3-658-41041-4_12

215

216

12  Bipolar Technology

12.1 The Standard Buried Collector Technique Bipolar transistors, unlike MOS structures, are not self-insulating, i.e. the individual transistors each require an all-sided junction or oxide isolation for complete electrical separation from adjacent devices. The SBC technique uses deep diffusions to insulate the transistor in the lateral direction. A pn-junction acts between the substrate and the oppositely doped epitaxial layer in the vertical direction towards the substrate. As a result of the isolation diffusion surrounding the individual transistor, the area required in this simple bipolar technology is extensive: the typical dimensions of a transistor are about 50 × 100  μm2. The depth of the isolation diffusion primarily determines the size since its minimum width is about twice the penetration depth of the dopants. Weakly p-type silicon wafers with a (111) surface orientation serve as substrate material for integrating npn transistors. Since the process initially involves only diffusion and deposition but no etching steps, alignment marks must be anchored in the wafer surface to align the photomasks. Consequently, the first photolithographically patterned resist layer serves as an etch mask for creating reference points in the form of steps in the silicon crystal. The masking oxide required for local doping by diffusion grows thermally in a humid atmosphere. The structuring of the oxide mask for subcollector doping is carried out by wet-chemical etching using a photoresist as a mask. Because the subsequent epitaxy process requires exceptionally high temperatures, the element with the smallest diffusion coefficient in silicon—arsenic—must be used as the dopant to avoid strong diffusion of the subcollector. At about 1100 °C, the arsenic diffuses into the crystal and forms a highly conductive layer. It is followed by completely removing the oxide mask in a buffered hydrofluoric acid solution. A weakly doped crystalline layer with a thickness of several micrometres grows over the entire surface utilizing gas-phase epitaxy; it is used to produce the n-type collectors of the npn transistors. Phosphorus, as well as arsenic or antimony, are suitable dopants. For mutual isolation of the collectors of different bipolar transistors of an integrated circuit, a local deep boron diffusion occurs, again masked by an oxide. Consequently, another oxide must be thermally wet-grown and patterned by wet chemical etching using a photolithography technique. During the next high-temperature diffusion step, boron diffusion penetrates the entire epitaxial layer; it must extend at least to the p-type substrate to ensure complete insulation of the individual n-conducting transistor areas. The following structured oxide mask is used to produce the relatively weakly doped base. Here, the element boron diffuses into the crystal again, whereby the depth of diffusion and the doping level significantly influence the width of the active base and, thus, the gain of the transistor. In another thermally wet-grown oxide, the opening for emitter diffusion is exposed above the base. At the same time, oxide etching occurs for the collector contact at the side of the transistor’s base. The emitter diffusion penetrates about 1 μm into the crystal.

12.1  The Standard Buried Collector Technique

217

During this diffusion, strong n-doping also occurs in the collector contact region to better contact the previously weakly n-conducting collector epitaxial layer. The width of the transistor base can be determined by the difference in the penetration depths of the base and emitter diffusions. For low-resistance contacting of the highly doped subcollector, the depth of the emitter diffusion as collector connection is not sufficient. Therefore, in power transistors, an additional, correspondingly deeper diffusion penetrating down to the subcollector is used for improved contacting; it is carried out before the emitter diffusion. This extra process step can be dispensed in simple circuits without a significant driver function. The final integration steps are used for contacting and wiring the individual circuit elements. First, another oxide is thermally grown over the entire surface, into which the contact openings are etched wet-chemically using a photolithography technique. In contrast to the MOS technique, since the pn-junctions protrude deeply into the crystal, direct contact with aluminium without using a barrier layer is possible. By vapour deposition or sputter coating, the metal is applied and patterned with the aid of another photoresist mask in an aluminium etching solution. To alloy the contacts, annealing in N2/H2 atmosphere (forming gas, 75% N2, 25% H2) follows. The process concludes with the deposition of surface passivation and the opening of the terminal pads. A schematic representation of the process is given in Fig. 12.1. This simple bipolar process allows the integration of vertical npn transistors, high and low-impedance resistors from the doped layers and capacitors in the form of pn-junctions operating in the blocked state. The high-resistive resistors can be fabricated from either p-type regions co-generated with the base doping or the weakly n-type collec-

a)

b)

c)

d)

e) Fig. 12.1   SBC technique: a oxide masking and subcollector diffusion, b n-epitaxy and isolation diffusion regions, c base diffusion region generation, d emitter diffusion and collector contact insertion, e contact hole patterning and wiring of npn transistor

218

12  Bipolar Technology

tor epitaxial layer. For low resistance values, the emitter diffusion regions are suitable. The junction capacitances of the base-collector or the base-emitter diode are suitable as capacitors. The latter has a large capacitance per unit area and a low voltage dependence, but the breakdown voltage is relatively low due to the high doping concentrations. Complementary pnp transistors can also be integrated with the npn structures. The vertical design uses the p-type base diffusion of the npn transistor as the emitter, the weakly doped epitaxial layer as the base and the substrate as the collector. Consequently, this pnp transistor is not free in its connections because all collectors are connected through the substrate. Also, the high path resistances and the relatively large base area’s capacitance significantly limit this transistor’s switching speed. Alternatively, a lateral pnp transistor design with the base diffusions of the npn transistor as emitter and collector is an option, applying the n- epitaxial layer as the base. This pnp transistor is free to be connected, but its characteristics strongly depend on the width of the lateral diffusion of the base doping. Because of the relatively weak doping of the emitter of these pnp transistors, the yield and the gain—especially in the high current range—are low. In addition, the relatively high collector doping compared to the base has a negative effect in the form of a very low early voltage. Thus, SBC technology enables the joint integration of npn and pnp transistors with resistors and capacitors. However, its large area requirement is a disadvantage: the necessary distances of the base and collector contacts from the insulation diffusions as well as the width of these diffusions, drastically limit the density of integrated circuit elements.

12.2 Advanced SBC Technique It is reasonable to use dielectric isolation in the lateral direction between the bipolar transistors instead of the circumferential isolation diffusion [1] to achieve a higher degree of integration. The isolation width is reduced, but the alignment overlaps and distances between the collector and base contacts and the previously required isolation diffusion are also completely eliminated. The area requirement of an npn bipolar transistor thus drops to about 15 μm × 25  μm in advanced SBC technology. After doping the subcollector and applying the epitaxial layer, pad oxide is oxidized and covered with nitride to produce dielectric insulation. A photoresist layer masks the etching process to remove the nitride in the insulation region. During the subsequent thermal local oxidation, oxide insulation laterally enclosing the active region is formed. It extends through the entire epitaxial layer. Thus, the n-type collector is isolated vertically from the adjacent circuit elements via a pn-junction to the substrate and, laterally, by the surrounding silicon dioxide layer. The LOCOS insulation is followed by base and emitter fabrication; both areas are doped by diffusion, comparable to the simple SBC technique. The process ends with the contacting and wiring of the elements. Figure 12.2 shows a schematic cross-section of the different steps of the integration process.

12.3  Bipolar Process with Self-Aligned Emitter

219

a)

b)

c)

d)

e) Fig. 12.2   Process steps of advanced SBC technique: a oxide masking and subcollector diffusion, b n-epitaxy, local oxidation to produce insulation, c base generation by diffusion, d diffusion regions of emitter and collector contact, e contact opening and wiring

The base and collector contacts are allowed to terminate within the oxide insulation; as in the simple SBC technique, a short circuit by the insulation ring does not occur here. At the same time, the thickness of the epitaxial layer has been reduced to keep the required depth of the oxide isolation low. Its smaller size also reduces the base and emitter diffusion regions’ depths, so their parasitic junction capacities decrease considerably. Due to the oxide isolation, the collector capacitance is reduced simultaneously. Consequently, a significantly higher switching speed is achieved in total.

12.3 Bipolar Process with Self-Aligned Emitter The bipolar technology with self-aligned emitter and base contact diffusion regions enables transit frequencies in the range above 60 GHz for pure silicon transistors and up to approximately 300 GHz for silicon-germanium switching elements. Fabrication uses doped epitaxial layers as collector and base regions instead of diffusions; only the emitter is diffused into the crystal from a polysilicon layer. The base contacts and the emitter diffuse into the crystal in a self-aligned manner [2]. As the transistor’s subcollector, an n+ layer is epitaxially deposited on the weakly p-doped substrate. A photoresist-masked trench-etch is performed for space-saving lateral insulation, protruding through the strongly n-conducting layer into the p-substrate. These very narrow trenches are filled with oxide in a conformal CVD deposition, and

220

12  Bipolar Technology

Fig. 12.3   Trench isolation in the epitaxial layer after filling the trenches with SiO2 using the CVD process

Fig. 12.4   Cross-section of the self-aligning bipolar process after selective epitaxy

parallel, the oxide deposits over the entire surface as field oxide. In the process, the unevenness in the trench isolation area smoothes out almost completely (Fig. 12.3). A photolithography technique defines the active transistor areas where the field oxide must be removed again to apply further epitaxial layers down to the surface of the subcollector. In order to damage the crystal as little as possible while at the same time achieving high structural accuracy, the field oxide is first removed down to a residual layer in the RIE process, followed by wet-chemical etching down to the silicon surface. Next, the deposition of the relatively weakly doped collector and the thin base in the form of n- and p-doped selective epitaxial steps follow, i.e. the crystalline layers grow only in the oxide opening. The thermal load must be very low (approximately 700 °C) to exclude dopant diffusion in these layers, which are only a few 100 nm thick (Fig. 12.4). Alternatively, an n-doped epitaxial layer can be deposited over the entire surface and removed again by chemical-mechanical polishing down to the oxide surface to fill the opening with n-conducting silicon. In this case, the p-doped base is produced by nearsurface boron implantation. To contact the weakly doped base, a deposition of heavily p-doped polysilicon follows; this layer is directly covered with another oxide and provided with the photoresist mask for the base connections (Fig. 12.5). The dry etching process follows for the oxide structuring and the polysilicon’s geometry definition. In this case, exact control of the etching process is necessary to minimize damage to the base area because the selectivity of the etching process for polysilicon to crystalline silicon is very low.

12.3  Bipolar Process with Self-Aligned Emitter

221

Fig. 12.5   Base connector with oxide spacer for self-aligned emitter production

Alternatively, the selective epitaxy mentioned above can be performed exclusively as an n- layer to mitigate this critical etching process. Then, after the p+ polysilicon patterning, boron implantation is necessary to generate the transistor base. The advantage of this process sequence is the more precise control of the base width since the implantation of boron ions sets its doping depth only after the critical etching process. A conformal oxide deposition followed by a back-etch step provides the base terminal with a circumferential oxide spacer to electrically isolate the lateral polysilicon edges from the other layers. This etching step, which may only be performed dry, must also be performed extremely selectively so as not to change the base width. The crystal surface in the emitter area is now exposed; all other areas are masked with oxide. Another polysilicon layer, heavily doped with phosphorus, is deposited over the entire surface and patterned with the mask for the emitter. Phosphor or boron-phosphor glass is deposited on the whole surface to enable planarization in the reflow process. A full-surface oxide deposition follows at low temperature in the PECVD process to avoid diffusion effects (Fig. 12.6). During the PSG-reflow at more than 900 °C, diffusion processes occur. Boron diffuses from the p+-polysilicon into the base, and phosphorus diffuses from the n+-polysili-

Fig. 12.6   Cross-section of an npn transistor after deposition of the n+ polysilicon for self-aligned emitter diffusion and the intermediate oxide

222

12  Bipolar Technology

Fig. 12.7   Cross-section of a bipolar transistor with self-aligned base and emitter terminals

con into the base as well. The highly conductive base contacts are thus self-aligning, and the emitter is also perfectly aligned with the base connections. Alignment presets causing parasitic resistances and capacitances do not occur. Next, by applying the contact hole mask, the oxide can be removed over the connection areas down to the polysilicon of the base and the emitter and down to the highly doped collector epitaxy in the dry etching process. The process concludes with aluminium metallization and patterning of the wiring plane. A cross-section of the resulting npn bipolar transistor is shown in Fig. 12.7. This bipolar process with self-aligned emitter and base contact diffusion regions is characterized by high cut-off frequencies (>40 GHz) of the circuit elements combined with a relatively high packing density. The typical area of the emitter is only about 0.4 × 1  μm. A further increase in the cut-off frequency is possible with a base consisting of a crystalline silicon-germanium epitaxial layer hetero-epitaxially grown on the silicon substrate. Molecular beam epitaxy or gas phase epitaxy are applicable to achieve a germanium content of around 20% of the atomic composition. On the one hand, the mobility of the charge carriers increases due to mechanical tensions. On the other hand, germanium doping causes a change in the band structure, limiting hole injection into the emitter, and it enables a heavily doped narrow base. SiGe bipolar transistors manufactured in this way achieve cut-off frequencies well above 250 GHz.

12.4 BiCMOS Techniques Many applications of microelectronic circuits cannot be realized with MOS transistors alone because of the required high switching speed. At the same time, integration in bipolar technology is ruled out because of the limited packing density. For these special require-

12.4  BiCMOS Techniques

223

ments, a combination of both technologies has been developed called BiCMOS technology. Circuit parts for high-frequency applications or output driver stages are built with bipolar transistors, while the memory and logic area consists mainly of MOS structures. The CMOS process offers a straightforward npn transistor integration by introducing one complementary implantation. This boron doping generates the p-type base inside the n-well. The n-well of the CMOS process serves as the collector, and the n-type transistor’s drain-source doping as the emitter, as shown in Fig. 12.8. The dose and energy of the additional boron base implantation determine the width of the base and, thus, the gain of the bipolar transistor. The supplement mask and doping steps can be added to the CMOS process after field oxidation and opening of the active regions, with the MOS regions covered with photoresist. However, due to the low well doping concentration, the collector path resistance of the transistors is very high at about 1 kΩ, so these bipolar transistors compatible with MOS technology are of low quality. For bipolar transistors with higher performance, at least a buried sub-collector is necessary to reduce the path resistance. The sub-collector can be integrated using the epitaxy technique, which increases the manufacturing effort considerably. Alternatively, “retrograde-well” doping profiles—doping distributions with a high donor concentration at depth with a weak surface concentration—can be generated by high-energy ion implantation with phosphorus (4–10 meV) for n-well doping. A buried highly conductive n+ layer is created in conjunction with surface doping suitable for the MOS transistors. This concentration profile reduces the collector path resistance of the bipolar transistors to approximately 50 Ω. At the same time, the latch-up of the CMOS components is wholly suppressed due to the low n-well resistance [3]. If the circuit integration requires high-quality bipolar transistors, MOS transistors must be added to the SBC process as the starting technology (Fig. 12.9). The p-type MOS transistors can be integrated directly in the weakly doped n-type epitaxial layer. In contrast, the base doping is too high as a substrate for the NMOS transistors. Here, a process adaptation is necessary. It is impossible to lower the base surface doping for an acceptable threshold voltage of the n-type transistors. The NMOS transistor gets a p-type well in the epitaxial layer, fabricated by boron ion implantation with subsequent diffusion. BiCMOS technology thus enables the integration of high-frequency circuits with high packing density. However, the number of masking and doping steps increases signifi-

Fig. 12.8   Cross-section through a BiCMOS structure fabricated with a CMOS process as the starting point

224

12  Bipolar Technology

Fig. 12.9   Cross-section of the BiCMOS technology starting from SBC process

cantly due to the joint integration of the bipolar and MOS transistors on one substrate. The complex processing leads to reduced yield in functional devices since the probability of a defect in a circuit increases with the number of mask levels.

12.5 Bipolar Technology Tasks Task 12.1 In the SBC process, pnp transistors can also be integrated. Draw the technology crosssection of each possible design and name their special properties! Task 12.2 In the SBC process, the p-type base is diffused after a surface allocation of 1 × 1016 cm−2 for 6 h at 1100 °C (substrate doping ND = 2 × 1014 cm−3). This process is followed by phosphorus diffusion after allocating 1 × 1017 cm−2 for 20 min at 1020 °C. Calculate the effective base width of the bipolar transistor under the simplifying assumption that phosphorus diffusion does not affect the boron profile. What distorting effect does this approximation have? Task 12.3 Calculate the dimensions of a 150 Ω resistor fabricated from the n-type epitaxial layer of the bipolar process (dEpi = 2  μm, ND, Epi = 1 × 1016 cm−3). Can this element be manufactured reproducibly?

References 1. Ruge, I., Mader, H.: Halbleiter-Technologie, pp. 232 ff. Springer, Berlin (1991) 2. Sze, S.M.: VLSI Technology, pp. 499–502. McGraw-Hill, New York (1991) 3. Harms, T., Goser, K., Hilleringmann, U., Fahrner, W.R., Oppermann, K.: Semiconductor Device Fabrication with High Energy Ion Implantation, ESSDERC’89, In: Heuberger, A., Ryssel, H., Lange, P. (Editos) pp. 33–36. Springer Heidelberg (1989)

Packaging of Integrated Circuits

13

After finishing the integration process of the MOS or bipolar devices, the individual chips are available for testing the analogue and digital operations of the circuits on the wafer level. In the case of positive results, encapsulating the chips in a package protecting against external influences is also necessary for their application. At the same time, the standardized package design must provide the user with a macroscopically accessible electrical connection grid. These requirements are met with the aid of assembly technology, which performs the following functions and tasks: • provide a mechanically defined package design that is well-suited for automatic board assembly; • widen the fine electrical connection grid on the chip to a connection grid accessible to the user; • establish the electrical connection between the pads of the semiconductor circuit and the internal terminals of the housing; • dissipating and distributing the heat generated by power loss of the semiconductor devices; • protection against environmental influences and mechanical damage. The importance of assembly technology can be illustrated by the steadily growing worldwide consumption of integrated circuits [1]: from 26 billion units in 1985, consumption rose to about 450 billion units in 1992 and about 2 trillion chips in 2021. An average number of 28 pins per package resulted in a total of over 12 trillion connections between packages and boards in 1992.

© Springer Fachmedien Wiesbaden GmbH, part of Springer Nature 2023 U. Hilleringmann, Silicon Semiconductor Technology, https://doi.org/10.1007/978-3-658-41041-4_13

225

226

13  Packaging of Integrated Circuits

13.1 Preparing the Wafers for Packaging After the wafer leaves the realm of pure semiconductor process technology called the “front-end”, the circuit side of the wafer has a passivated surface with exposed aluminium pads for contacting. In contrast, the reverse side is still electrically and mechanically undefined due to the deposition and etching processes. Before assembly, further chemical or mechanical processing steps are necessary to guarantee a defined status.

13.1.1 Reducing the Wafer Thickness The reverse side of the wafer must be electrically contactable so that charge carriers can be transported via substrate contact. An excellent thermal connection of the chip’s reverse side to the package is required to dissipate the power loss. Although the thermal conductivity of silicon is relatively high, a thinner wafer offers lower thermal resistance. Consequently, reducing the wafer thickness before cutting the discs into individual chips makes sense. At the same time, this removes interfering pn-junctions and oxide layers from the back of the wafer; it also reduces the effort required in the dicing process for chip separation. The lapping technique, wet chemical etching and grinding of the reverse side of the wafer are suitable for reducing the thickness. In lapping, the circuit side of the wafers is bonded to the holder of a lapping machine using wax. So its reverse side slides on the lapping wheel. Silicon carbide (SiC) or aluminium oxide (Al2O3) powder mixed with resin is used as the lapping agent. The equipment design corresponds to the equipment for wafer production (see Sect. 2.4.2.1). The lapping technique enables the reduction of the wafer thickness to approximately 250 μm. Alternatively, removing the reverse side of the wafer is possible by wet chemical etching solutions with varnish or wax masking the surface structures. Diluted mixtures of hydrofluoric and nitric acid allow etching rates of 1–2 μm/min. This etching process also removes crystal defects following the above lapping process. A widely used process is grinding to reduce the thickness of silicon wafers. Rotating grinding wheels coated with diamond powder remove interfering dielectric layers as well as the single-crystalline material from the back of the wafer at a high rate in a rough grinding step. In a subsequent smooth grinding step, a surface with a roughness of less than 100 nm is produced, depicting a thickness tolerance of the surface of ± 3 μm. The depth of crystal damage after fine grinding is only a few micrometres. The wafer thickness can be reduced to about 50 μm using this method. The grinding technique provides a sufficiently thin silicon wafer with a defined reverse side surface for further processing.

13.1  Preparing the Wafers for Packaging

227

13.1.2 Reverse Side Metallization The reverse side metallization must ensure an electrically low-resistance, thermally highly conductive and mechanically stable contact with the package. It requires good adhesion of the used metal to the silicon and must also form a strong bond with the adhesives or solder for chip attachment. One metal alone cannot meet all the requirements; for example, the electrical contact of the wafer’s rear side requires a metal with an appropriate work function for a low ohmic contact resistance—comparable to the electric contacts within the microelectronic circuits. Consequently, the reverse side metallizations of p- and n-type silicon wafers differ to avoid pn-junctions with Schottky characteristics. Multilayer systems consisting of adhesive, intermediate and top layers are suitable. In addition to mechanical strength, the adhesive layer ensures the lowest possible electrical contact resistance between the semiconductor and the metal. The intermediate layer prevents the formation of an alloy between the adhesive layer and the top layer. So alloying does not result in an intermetallic compound that can negatively influence electrical conductivity or mechanical strength. The top layer provides the connection to the environment and must therefore be adapted to the intended mounting process using glue, solder or alloys. An example of reverse side metallization with a multilayer structure is the aluminium/ titanium/silver system for p-type silicon wafers. These layers are each deposited or sputtered in a thickness of approx. 0.5 μm. For n-type wafers, on the other hand, a multilayer structure is not used but only one layer of an antimony/gold alloy.

13.1.3 Separation of the Chips The individual chips of a wafer are separated by a circumferential scribing frame of 50–100 μm width. There are no circuit components inside the scribing frame since this area is destroyed for dismantling the wafers. In order to save circuit space but also to prevent the user from accessing the parameters of the individual integrated circuit elements of the chips, the test structures for parameter acquisition are often located in these areas. During the separation of the circuits by scribing, dicing or laser cutting, the test structures are irrevocably destroyed so that any further access to these elements is safely prevented.

13.1.3.1 Scribing During scribing, a diamond tip guided along the centre of the scribe frame applying slight pressure creates a scratch in the form of an indentation of a few micrometres in the wafer surface. Due to the mechanical damage to the crystal, lattice stresses are created so that the crystal breaks along the scribe line even at low mechanical forces.

228

13  Packaging of Integrated Circuits

The silicon surface in the scribing frame must be exposed to use this separation process because oxide thicknesses of less than 100 nm already lead to the destruction of the diamond tip. However, sufficient lattice strain can only be achieved if the scribing parameters are selected appropriately: the angle of attack, the diamond pressure and the scribing speed must be adapted. The defect zones created during mechanical scribing can be used as authoritative lines to separate the individual chips during subsequent breaking completely. In this process, the wafer adhering to a self-adhesive film is pulled over an edge or pressed with slight pressure against a curved convex surface so that the disc breaks into individual chips. Today, scribing the wafers is no longer common due to the larger wafer diameters. The wafer thickness has increased, making targeted cracking more difficult. In addition, the silicon crystal preferentially breaks along the - planes. In case of a slight misalignment of the wafer orientation, the cracking line can deviate from the scribe line and run through the circuits. In the case of large-area circuits, there is also the risk of damaging the chips by pressing them against the curved surface. These negative aspects led to the scribing technique being used only up to a wafer thickness of approximately 375 μm (corresponding to 3” wafer diameter).

13.1.3.2 Laser Cutting The laser separation process uses an intense, highly focused laser beam with a wavelength of about 1 μm. It locally heats the semiconductor material within the scribing frame. Since silicon only weakly absorbs IR light at this wavelength, the beam penetrates about 100–200 μm into the crystal and briefly melts the material. The absorption creates a large temperature gradient to the surrounding silicon inside the scribing frame; it leads to polycrystalline silicon crystallization during solidification. The process causes significant mechanical stress in the scribing frame between the chips, which can be used to separate the circuits, like in the case of scribing the wafers. The final disassembly of the wafer by breaking is also performed by pressing the lasertreated wafer against a curved surface. Due to the high penetration depth of the infrared light, the laser cutting process can also be used for thicker substrates than the scribing technique. Still, it delivers only limited fracture edge quality. Here, too, deviations between the cut and breaking lines can occur—resulting from an erroneous alignment of the chips or laser scan direction to the crystal orientation—so that damage to the integrated circuits is possible. The scanning speed of the laser cutting process is high compared to the scribing technique. 13.1.3.3 Dicing The cutting process used almost exclusively today for chip separation is sawing or dicing [2]. The tool used is a diamond-coated grinding wheel of approximately 25 μm thickness. It operates at a high rotation speed (30,000 rpm) and is guided along with the scribe frame on an aligned positioning table. As a result of the centrifugal force, the high rota-

13.2 Assembly

229

tion speed causes the stabilization of the fragile dicing saw blade. It thus leads to clean cutting lines running precisely parallel to the chip edges. The wafer sticks to a self-adhesive film (“blue tape”) of defined thickness for the dicing process. Thus, the chips’ orientation and position on the wafer will not get lost after separation. The dicing is done either partially down to a residual thickness or across the whole wafer. In the latter case, a few micrometres are sawn into the blue tape to ensure the entire wafer is safely cut through. In contrast to scribing and laser cutting, the dicing process works independently of the crystal orientation. Water flows continuously over the wafer surface to cool the grinding wheel, and simultaneously it removes the sawdust from the surface. The cutting wheel may also be coated with oxide or nitride grains instead of diamond powder. The edge quality of the cut chips depends on whether the wafer is sawn only to a residual thickness or cut through completely. In the first case, the wafer can still be handled carefully. Still, this procedure produces disturbed, rough fracture edges in the area of the residual silicon when it is later broken into individual chips. Starting from the scribe frame, the crystal defects resulting from the cut extend up to 100 μm into the chip. Therefore, the edge area should be kept free of active elements.

13.2 Assembly After the silicon wafer has been cut into individual dies, the chips are well ordered and of a defined size on the self-adhesive foil, with the positions of the elements that failed the functional test known or marked by a colour dot. The flawless chips must now be removed from the foil, attached to a substrate (in assembly technology, the substrate is the carrier used to attach the chip) and contacted with conductive wires. Substrates can be metallic system carriers, prefabricated packages, layered ceramic carriers or printed circuit boards.

13.2.1 Substrates/System Carriers The system carriers for microelectronic circuits must have high thermal conductivity to dissipate the integrated components’ power loss. Further demands are mechanic stability and a thermal expansion coefficient matching the crystalline silicon. The price must not be neglected either, given approximately 2 kg of metal consumption for 1000 packages. Due to their high thermal conductivity, copper and copper alloys are particularly suitable for circuits with high power dissipation. However, the thermal expansion coefficients do not match those of silicon chips. Primarily adapted are the expensive iron alloys with nickel and cobalt, which are thermally weaker conductors by a factor of 10 to 20. Consequently, an iron alloy is used for large-area circuits with moderate power dissipation, while a system carrier made of copper is selected for power devices.

230

13  Packaging of Integrated Circuits

The system carriers are manufactured by stamping from a metal sheet in roll form. Its typical structure for a dual in-line package (DIL) is shown in Fig. 13.1. In the centre of the system carrier is the island accommodating the silicon chip (a), which is often deep-stamped to compensate for the height difference between the chip surface and the carrier’s contact terminals. The contact ends of the connection fingers (b) are arranged around the island. The ridges between the fingers (c) ensure the stability of the metallic structure; they are cut away while finishing the package after being pressed around with plastic. The reduction in cross-section at the fingers’ ends (d) is intended to allow the pins to be inserted securely into the holes of the printed circuit board—especially during automatic assembly. All lead frame pins are connected at their tips by a stable metal stripe, enabling a roll-up format for tape-automated bonding. It protects against mechanical bending and damage caused by electrostatic discharge effects by forming a short of all contacts. Commonly, the system carriers’ surfaces are gold-plated to achieve good solderability and bondability. Additionally, gold is not susceptible to ambient air leading to corrosion. A possible alloy formation between the gold plating and a copper system carrier at the processing temperatures of 300–400 °C occurring in assembly technology can be prevented by a thin intermediate layer of cobalt or nickel. Premanufactured packages for chip mounting are available as an alternative to the metallic system carriers. Apart from the cover lids, these ceramic or plastic substrates contain a structure comparable to the metallic system carrier to accommodate the chip and the connecting electrical terminals. The expensive ceramic bases enable hermetically sealed encapsulation of the chips with a non-porous connection between the individual planes of the multilayer package and the metal pins. By fusing the metal structure with glass solders, the different components of the ceramic substrates are laminated together to ensure a gas-tight housing.

Fig. 13.1   Design of a stamped system carrier for a 16-terminal DIL package

13.2 Assembly

231

Ceramic substrates are implemented in communications technology, military, and satellite applications. Typical designs are flat packages, dual-in-line (DIL) and pin packages, or multilayer chip carriers with connections on all four sides of the housing. For many applications sensitive in terms of sales price, plastic substrates are sufficient as housings. They offer a considerable price advantage because they can be manufactured inexpensively using injection moulding technology. However, the plastic does not enclose the metallic system carrier without pores, so these housings cannot be used in humid or even corrosive environments. As a result of the poor thermal conductivity of the plastics, these packages are unsuitable for circuits with high power dissipation. Nacked chip assembly applies unpackaged passivated chips directly after the test of operation or wafer dicing. The dies are fixed on a carrier by glue or solder. This technique reduces costs, lowers space requirements, and improves the dynamic characteristics of a circuit by reducing the interconnect length. It is used, for example, in watch circuits and hybrid technology. The chips are mounted on thick-film or thin-film circuits and directly on printed circuit boards. Typical thick-film carriers consist of 96% Al2O3 ceramic as substrate. A screen printing process with subsequent thermal treatment at 800–950 °C is used to produce conductor tracks, resistor networks, connection pads for wire contacting and—in the case of multilayer thick-film boards—insulation layers. Thin-film circuits as carriers for integrated circuits consist of higher-grade ceramics or glass. The respective layers for resistors, dielectrics and conductors are deposited in a vacuum technique and structured photolithographically. Integrated capacitors can also be produced in this process. In both types of ceramic carriers, the conductors lead directly to the bonding surfaces next to the metallized space for mounting the unencapsulated chip. Increasingly, the chips are also mounted directly on simple printed circuit boards. Due to its high space savings, this technology enables cost-effective board production. Still, the mounting techniques have limitations due to the board material’s limited temperature resistance. A serious disadvantage of nacked chip assembly—regardless of the substrate used—is the unknown quality of the chips fixed to the board. Although the integrated circuits can be tested via pin cards before the wafers are cut, it is not always possible to record all the necessary parameters, e.g., high-frequency characteristics. The failures caused by sawing the wafers are not considered, so defective circuits may be installed sometimes.

13.2.2 Die Bonding According to the individual requirements, the chips are attached to the substrates by glueing, soldering or alloying in automatic placement systems (“die bonders”). In this process, a needle presses against the cut-out chip adhering to the self-adhesive film from the rear to be picked up with a vacuum tweezer, wetted with adhesive, positioned on the

232

13  Packaging of Integrated Circuits

system carrier and pressed on. The die bonder is fed with the position data of the flawless chips, determined by the automatic function test on the wafer-level, so that only circuits recognized as good are sent for further processing.

13.2.2.1 Adhesive Bonding Alkaline ion-free epoxy resins in the form of one- or two-component adhesives that cure in the temperature range from room temperature up to 150 °C are used to bond the integrated circuits into the housings. The adhesive components are heavily loaded with silver to achieve a high electrical conductivity of the original insulating material. The silver addition also improves the thermal conductivity to dissipate the power loss. Still, the thermal conductance is low compared to the other fastening methods despite the high silver concentration of up to 80% by weight. Both surfaces to be bonded must be free of impurities; a special metallization is not required for epoxy resin bonding. Curing occurs at elevated temperatures between 80 and 130 °C in a convection furnace or continuous oven. A firm but by no means a rigid bond is formed, which prevents possible mechanical stresses between the chip and the system carrier, even with large circuit areas. The epoxy resin will compensate for any mechanical stress. Epoxy bonding is the most common method for attaching dies with low to moderate power dissipation, although the addition of silver results in high material costs. However, the process provides robust and fast attachment of chips. Due to the limited thermal stability of the epoxy resin, the maximum temperature after bonding the dies is limited to 220 °C. A thermal load of up to 300 °C may be allowed for a short time. 13.2.2.2 Soldering A cost-effective mounting technique is soldering the chips to the system carriers using low-melting solder made of lead-silver-tin or lead-free Cu-Ag-Zn alloys. Soldering provides a mechanically stable connection with good electrical and thermal conductivity, which—depending on the type and thickness of the solder layer—can also compensate for mechanical stresses between the chip and the system carrier to a limited extent. Solder thicknesses of over 50 μm are required for die bonding. The reverse wafer side and the housing must have solderable surfaces in this process. Aluminium backside metallization is consequently unsuitable. Here, additional layers of nickel and silver are applied to the aluminium contact layers. Gold-antimony alloys, commonly used for n-type silicon dies, are directly solderable. The solderable substrate has a nickel-plated or gold-plated surface. Depending on the solder composition, the melting temperatures are in the range of 180–300 °C; this temperature must not be exceeded during the manufacture of the electrical connections and injection moulding for encapsulation. The solder is available as a small plate in an automatic assembly of the system carriers. It is placed between the chip and the system carrier and melted under slight pressure in an inert gas atmosphere.

13.3  Electrical Contacts

233

13.2.2.3 Alloying Instead of a soldering step, alloying allows a mechanically very rigid, electrically and thermally extremely highly conductive connection between the chip and the system carrier. Alloying the chips onto the gold-plated substrates requires a high temperature of about 420 °C for the reaction; this is the thermal limit for the already metallized circuits. The element gold is particularly suitable for alloy formation; it exhibits a eutectic alloy at 370 °C in the phase diagram with silicon. The chip is rubbed onto the gold-plated system carrier under slight pressure at a temperature above the eutectic point to create a strong bond with the silicon. During this process, the gold-silicon alloy forms until all the gold is used up. On cooling, a mechanically solid but relatively brittle compound is formed. The alloying process leads to high thermal stress on the integrated circuit during die attachment. It also restricts the choice of package bases and system carrier materials. Copper alloys have already become brittle at 400 °C, so the requirements for the bending strength of the pins can no longer be met. Plastic bases are completely unsuitable in this temperature range; only ceramic housing bases and system supports made of ferrous alloys meet the requirements. In addition to the high process temperature, the rigid connection between the chip and the package is a disadvantage: mechanical stresses due to different expansion coefficients can lead to the cracking of the silicon chip and, thus, the circuit’s destruction. For this reason, alloying as a connection technique between chip and system carrier is only used for extremely high power dissipation in conjunction with small silicon areas.

13.3 Electrical Contacts The techniques for making the electrical connections between the pads of a chip and the package contacts can be divided into single-wiring and simultaneous contacting processes. Although the last one has significant advantages, single-wire techniques are still widely used in 2022. However, as the number of contacts continuously increases year by year, simultaneous contacting methods are steadily gaining importance due to a reduction in wiring time.

13.3.1 Single Wire Bonding The single-wire processes use gold or aluminium wires of 25–200 μm diameter as electrical connections from the aluminium pad on the chip to the gold-plated package connector. Wire connections are being made in a serial process called “bonding”. The bonding processes can be applied to numerous substrate materials like aluminium, gold, copper or nickel; the interconnections are extremely reliable while being highly automatable and consequently still economical even with many contacts per circuit.

234

13  Packaging of Integrated Circuits

The thermocompression process, ultrasonic or wedge bonding and the thermosonic process are available for single-wire contacting, differing essentially only in the type of energy input used to make the metal-to-metal connections. They use either gold or aluminium as wire materials; however, the thermal stress on the microelectronic circuits during wiring differs strongly.

13.3.1.1 Thermocompression Method The thermocompression process, also known as ball bonding, uses thermal energy and pressure to form a bond between the gold bonding wire and the aluminium pad of the circuit or the system carrier contact. Atomic bonding forces are created at the wire/bond pad interface by intermetallic diffusion, resulting in the welding of the materials with no liquid phase in the course. The wire connection consists of a first bond on the pad of the chip (“ball”) and a second bond on the package contact (“stitch” or “wedge”). In order to melt the wire protruding from the radially symmetrical bond capillary into a sphere at the end, a capacitor discharge takes place towards the end of the wire. The energy supplied by the spark melts the gold wire; due to the surface tension, the melt contracts into a ball. A hydrogen flame can also serve as a heat source, swivelled under the bonding tool and melts the wire end. The bonding tool, heated to approx. 350 °C, presses the ball onto the pad of the chip in the second step. In a period of approximately 60 ms, a force of about 0.5–2 N acts on the contact point. The gold wire bonds with the aluminium pad; the ball deforms into a nail head during bonding due to the pressure. Raising the bond capillary completes the chip-side contact (Fig. 13.2). In order not to kink the wire directly above the nail head, the bonding tool is guided in an arc (“loop”) to the second connection on the system carrier and pressed on there again. The edge of the bonding capillary deforms the wire into a “stitch” or “wedge”, and pressure and temperature create a welded joint again. At the same time, a constriction forms in the wire below the bonding capillary as a predetermined breaking point. At

Fig. 13.2   SEM image of a thermocompression joint with nailhead and stitch (wedge)

13.3  Electrical Contacts

235

a)

d)

b)

e)

c)

f)

Fig. 13.3   Contacting by the thermocompression method: a + b ball generation, c bond with nailhead, d + e loop, f stitch connection with squeezing off the bonding wire

this induced weak point, the bonding wire breaks when the bond tool is lifted off, and a new bonding cycle begins. The entire bonding process is shown schematically in Fig. 13.3. Since the bonding tool shows radial symmetry, the needle, including the wire, can be moved in any direction after the first bond. Consequently, there is no need to position the chip relative to the bonding tool, as is necessary for the ultrasonic process. The thermocompression process uses gold wire exclusively because sphere formation is not reproducible with other materials. Aluminium wire oxidizes at the required temperature and becomes brittle. Other materials have too low surface tension or require higher temperatures during bonding. These are not permissible due to the limited thermal stability of the metallization layer on the chip (Table 13.1).

Table 13.1  Data of the thermocompression process

Temperature:

About 350 °C

Wire cross-section:

About 15–50 µm

Contact time:

About 60 ms

Loop length:

0,8–2 mm

Bond wire:

Au

Bond partner material:

Al-, Au-, Cu-Pads

Pad size:

100 µm · 100 µm

Distance pad to pad:

100–200 µm

236

13  Packaging of Integrated Circuits

A precise temperature setting for the bonding tool is essential for long-term stable bondings with the thermocompression process to prevent the formation of the brittle gold/aluminium alloy Al2Au, called the purple plague, because of its colour. It causes the wire to break even at low mechanical stress.

13.3.1.2 Ultrasonic Bonding Ultrasonic bonding, also known as wedge bonding, is a friction welding process without additional external heat supply, i.e. there is no thermal load on the chip or bond pad during bonding. The vibrating bonding needle operates at a frequency in the ultrasonic range. The wire below the bonding needle’s nose moves parallel to the pad surface with an amplitude of around 2 μm. The wire is pressed against the pad metal during the tool vibrations, rubbing its surface. Frictional heat and pressure create the desired microwelds in the contact area. This method is used for gold/gold, gold/aluminium and aluminium/aluminium joints. The aluminium wire is doped with gold, copper or silver to allow higher electrical loads while improving elasticity and flexural strength. Ultrasonic bonding uses a special needle equipped with a nose and a wire guide capillary as a tool. The nose presses the wire onto the contact pad of the circuit for the first bond. Due to the bonding needle’s ultrasonic vibrations, the aluminium’s surface oxide on the pad and wire cracks. In parallel, the generated heat forms a micro-weld as a contact. While the tool is lifted off and continues moving in the direction of the wire, the bonding wire runs freely through the guide capillary so that only a minimum tensile load occurs at the connection (Fig. 13.4). The bonding tool presses the wire against the substrate contact for the second connection. Again, a micro-weld joint arises by ultrasonic friction and mechanical force. However, the wire is not released when the tool is lifted off. Consequently, it breaks off directly behind the bond joint at a predetermined breaking point. The bonding process concludes with a wire feed under the active surface of the tool (Fig. 13.5). Ultrasonic bonding does not require any additional heating of the chip or the tool; consequently, no brittle Au/Al alloy can form on the circuit pad, even when a gold wire is used. Due to the smaller bonding tool, the required minimum pad area for producing a wire connection is smaller than in the thermocompression process. Additionally, the distance between the individual contacts on the chip can be reduced (Table 13.2). However, the direction of tool movement and respective orientation of the second bond is predetermined by the alignment of the first bond. So positioning and rotation of the system carrier relative to the bonding tool are required for all-sided chip contacting; this adjustment time considerably increases the time needed to produce a complete bond. It reduces the throughput of ultrasonic bonding compared to the thermocompression process. Manufacturers increasingly use copper bond wires for high currents in power electronics components due to their lower resistance and degradation sensibility. These can be ultrasonically bonded with a wire thickness of up to 500 μm at increased power input and pressure. The disadvantage here is the considerably higher wear on the bonding needle.

237

13.3  Electrical Contacts

a)

c)

b)

e)

d)

Fig. 13.4   Contacting with the ultrasonic method: a Adjustment of the tool, b First bond by friction welding, c Loop with free-running wire, d Second bond, e Tearing off the wire with subsequent feed of the wire end under the tool

Fig. 13.5   SEM image of an ultrasonic bond, left 1st bond as the beginning of the loop, right 2nd bond at the end of the loop

Table 13.2  Data of the ultrasonic method

Oscillation amplitude:

1–2 µm

Wire cross-section:

About 15–500 µm

Contacting time:

30–90 ms

Loop length:

0.5–4 mm

Bond wire:

Al, Au, Cu

Bond partner material:

Al, Au, Cu

Pad size:

70 µm × 50  µm

Distance pad to pad:

30 µm–150 µm

238

13  Packaging of Integrated Circuits

13.3.1.3 Thermosonic Method The thermosonic bonding process is also called ball wedge bonding. It is very similar to the thermocompression process, but it combines the two previously mentioned techniques. As a result of the radially symmetrical bonding tool, it allows direction-independent fast contacting of the chips with low thermal stress on the substrate. The welding energy required to make the electrical connections is introduced by external heat supply via the substrate holder and the bonding tool, and ultrasonic oscillations of the needle. Due to the low substrate temperature of 100–200 °C, the process is suitable for chip contacting on temperature-sensitive substrates such as printed circuit boards; bonded chips can also be wired very well using the thermosonic method. The required area and the shape of the bond contacts correspond to the values of the thermocompression process. The bonding wire used here is Au wire, applied to the substrate connections made of Au, Ag, Al, Ni or Cu.

13.3.2 Simultaneous Contacting In contrast to the serial and thus time-consuming single-wire processes, all connections between the package and the chip are made in just two bonding steps or even in just one temperature step in the case of simultaneous bonding. The techniques require special connection structures instead of bonding wires; their individual design depends on the respective process.

13.3.2.1 Spider Contacting In the spider contact process, all chip pads are simultaneously connected to a prefabricated metallic fine structure (“spider”) in a bonding or soldering process. The shape of the spider must correspond to the pad arrangement on the circuit surface. Due to the given positions of the spider’s connector fingers only electrical contacts to one circuit design are possible (Fig. 13.6). Spider contacting requires particular bond

Fig. 13.6   Principle of spider contacting with solder connection

13.3  Electrical Contacts

239

bumps—either on the circuit pads or on the prefabricated spider structure—to bridge the height difference between the aluminium surface and the connection fingers (Fig. 13.7). For solder bonding, these can be of low melting point solders (PbSn) on the chip, or copper with a gold top layer in case of thermocompression technology. Intermediate layers of titanium or chromium are used as diffusion barriers to ensure good adhesion on the aluminium pad; they are covered with copper or palladium. The spider is made of copper, coated with solder or gold on the bonding surfaces. The designs differ into single-layer or multilayer spiders. The single-layer spider is an all-metal structure etched from a copper strip about 35 μm thick. A photoresist is applied to both sides of the metal strip and exposed with the wire structure; it serves as masking. The spider structures are created in a wet chemical etching step, with the metal getting gold-plated or coated with solder after photoresist stripping. The multilayer spider uses plastic tape to carry the fine metallic structure. First, the tape is coated with a thin metal film to create an electrically conductive layer for electroplating. Next, the deposition of the photoresist follows. It is exposed with the negative of the spider structure. So the metal layer is open in the areas of the contact fingers, and the unmasked spaces are galvanically filled with copper. After removing the resist, the starting layer can be etched by wet chemical etching, and the plastic carrier layer can be structured using a dry etching process. The surface finish with gold is again applied by electroplating. The spiders are chained together on a reel in strip form regardless of the production technique. These are fed to the bonding machines for internal and external contact formation. As a result, this process is also called TAB (“Tape Automated Bonding”). To make the electrical contacts from the chip to the housing, the internal contacts, the spider is first connected internally to the pads of the circuit via the connection bumps. For this purpose, a heated stamp simultaneously presses all connection fingers of the spider onto the pads. For a thermocompression connection, the punch temperature is approx. 550 °C, for a solder connection approx. 300 °C. These quite high temperatures are tolerable because only a small amount of heat transfer occurs due to the shortness of the bonding process of 300 ms or 1 s. The bumps’ uniformity significantly influences the bond quality because different heights cause local variations in pressure loads on the chip and can lead to crystal damage or even breakage.

Fig. 13.7   Schematic structure of a chip-side solder bump for spider contacting

240

13  Packaging of Integrated Circuits

After internal bonding, the chip and the spider built a unit, with the spider still in tape form. The outer contact to the package, the layered circuit, or the board is made in a second bonding process. Here, a hollow punch is used as the tool. It first punches the spider with the chip out of the metal strip and then presses the spider’s external connections onto the substrate’s bonding surfaces. The electrical joint is again made by thermocompression or by soldering. A fully contacted circuit is then available. The spider process is a replacement for the time-consuming individual wiring technique. It mainly enables flat contacting, e.g. for check cards, computers, telephone cards, or watch circuits. Because of the circuit-specific spider geometries, the process is only suitable for production in large quantities in conjunction with many contacts per chip.

13.3.2.2 Flip-Chip Contacting Flip-chip contacting is one of the most advanced contacting techniques. It requires a prefabricated connection grid on the system carrier or layered circuit mirrored to the chip’s pad arrangement. For contacting, the integrated circuit has previously been provided with solder bumps. The chip is soldered with the circuit side onto the prefabricated contacts of the substrate. Accordingly, this process is also referred to as “face-down bonding”. In contrast to the contacting methods mentioned so far, only one solder connection is created per contact between the chip and the electrical connections of the system carrier; additional wires or copper structures are not required. The area needed is minimal; it corresponds to the circuit size since all electrical connections are located directly below the chip. The process requires significantly higher bumps than spider contacting, so direct electroplating of the pads is ruled out. To generate the bumps at the height of 30–80 μm, the “remelted solder bumps” technique is used even before the wafers are separated into chips. The remelting process leads to uniformly high structures by exploiting the surface tension of a molten solder layer for agglomeration (Fig. 13.8). All the contact pads are coated with the PbSn, CuAgZnSn or InPb solder on the wafer level. The deposition area significantly overlaps the surface passivation made of glass [3]. Heating the wafer to about 300 °C melts the solder. However, it cannot form a bond with the glass surface, so it withdraws from the glass due to its surface tension and forms

Fig. 13.8   Remelting of a solder bump by agglomeration of a coating applied over a large area around the pad to form a bond ball

13.3  Electrical Contacts

241

a sphere. In this remelt process, the required bumps are formed at a height that is significantly above the deposited solder layer thickness. Their size is defined by the coated area, the coating thickness, and the released metal surface in the passivation oxide window. For contacting, the chip coated with solder bumps is wetted with flux and placed with the circuit side on the substrate’s contact pads, arranged in the circuit’s connection grid. During a thermal treatment at about 335 °C, a solder joint is formed between the substrate, the bumps and the chip. There is a glass dam on the metal to limit the soldering area and to prevent the solder from running over the entire terminal fingers. Typically the process runs in a continuous furnace under a nitrogen atmosphere (Fig. 13.9). The bumps melt and wet the metal surface of the substrate. Melting creates a surface tension that positions the chip floating on the solder exactly to the connection grid of the substrate. The chip is thus self-aligning with the substrate. The size of the contact areas is at least approximately 50 µm by 50 μm. In contrast to the wiring techniques discussed so far, the circuit pads need not only be located at the edge of the chip but can also be located in the middle of the circuit. The solder mainly absorbs mechanical stresses so that cracks cannot form. Flip-chip assembly is the shortest connection between the chip terminals and the substrate. It uses only one solder connection per terminal and requires the smallest area. A serious disadvantage of the flip-chip assembly technique is the low thermal coupling for heat dissipation. The power dissipation of the circuit must be wholly transferred to the substrate via the solder bumps since the chip’s reverse side has no connection to any cooling surfaces. It is possible to glue on an additional heat sink; however, this increases space requirements, so an advantage of the flip-chip mounting technique is eliminated. Alternatively, capillary forces can be used to introduce a thermally conductive solvent-containing liquid (“underfiller”) between the chip and the substrate. After solidification, it reduces the mechanical stresses between the components after curing and acts as a thermal bridge to the system carrier.

13.3.2.3 Beam-Lead Contacting The beam-lead contacting process simultaneously prepares all the chips on a silicon wafer for packaging, i.e. most of the assembly occurs at the wafer level. Like spider technology, the method uses tiny structures as electrical connections to the substrate, but in this case, they are generated directly on the wafer. It eliminates the need for internal

Fig. 13.9   Schematic of a flip-chip connection

242

13  Packaging of Integrated Circuits

contacts; only an external connection between the ends of the beam-leads and the package contacts is required. In the chip’s manufacturing process, full-surface layers of the metals titanium and gold are applied in addition to the wiring layer of the circuit: titanium for improved adhesion is sputtered on and gold for the beam-lead electrodeposited with a structured photoresist layer as a mask. The resulting ridges protrude beyond the edge of the individual circuits by about 200 μm (Fig. 13.10). Instead of the usual die separation by dicing, wet chemical trenching with KOH as an etching solution is used for beam-lead contacting. The process requires circuit surface protection against the aggressive alkaline solution, and the chips must be fixed in their position on the wafer during and after separation. A suitable method is to glue a glass pane to the wafer surface; local backside masking is carried out with a nitride mask structured via lithography. The mask defines the position of the separation trenches during etching; it is aligned with the structure on the circuit side. The silicon underneath the beams is wholly etched away, and the beams protrude beyond the chip edge in a length of 120–200 μm. After the separation etch, comparable conditions exist to the spider technique after internal contacting. The size of the beamleads is about 50–120 μm in width with a thickness of 15 μm. They are susceptible to mechanical damage. The chips can be removed with vacuum tweezers and inserted into the substrates by dissolving the adhesive between the chips and the glass pane. All outer beam-lead contacts are created simultaneously in a thermocompression bonding process. Although the beam-lead technique requires neither a sawing step for separation nor spider production, including internal contacting, its prevalence is extremely low. The large area requirement and the sensitivity of beam-lead ridges negatively affect. For small chip areas, the loss of silicon area is extreme, whereas for large-area circuits with numerous connections, the yield loss due to damaged ridges has an impact.

Fig. 13.10   Principle of beamlead contacting

13.4  Finishing the Packages

243

13.4 Finishing the Packages Integrated circuits need an encapsulation that prevents mechanical damage and, on the other, keeps moisture and corrosive gases from the environment away from the chip surface. In particular applications, e.g., dynamic memory devices, additional protection against α-radiation is necessary. Depending on the system carrier or substrate type, the materials and processes for encapsulation differ. The metallic system carriers are enclosed with plastic after chip attachment and wiring. In the temperature range of around 175 °C, the epoxy resins, duro- or thermoplastics, show very low viscosity; they fill the finest gaps during the injection moulds at high pressure of around 70 bar without damaging the bonding wires. Duroplastics based on epoxy or silicone and various thermoplastics are suitable materials for mould encapsulation. They are filled with quartz powder to match the thermal expansion coefficients to the chip or system carrier. The plastics also contain a black carbon additive for blackening to protect the circuitry from light. All plastics must be free of sodium and chloride ions to prevent harmful effects on the circuit’s lifetime. Due to the high pressure during injection moulding, parts of the plastic compounds get into the seams of the encasing. It leads to the undesirable “flash” at the edge of the housing. After the material has cured, it is removed by dissolving. Next, punching out the metallic bridges, which increases the mechanical strength of the pins, for separation follows. The pins are then tin-plated for better solderability. The housing marking is done by screen printing or stamping; laser marking is also standard. The assembly technique ends with bending the pins and cutting them free at the ends. The prefabricated ceramic packages are sealed using a ceramic plate coated with glass solder at a temperature of 450 °C fixed onto the housing. Alternatively, metal lids can be attached with low-melting-point lead-silver-tin alloys as solder already at approximately 200 °C. Because of these temperature loads, the chip mounting—especially when using the glass solder—must be designed to be temperature-resistant. In contrast to the plastic housings, the ceramic packages are hermetically sealed, thus especially suitable for harsh environmental conditions. The cavity with the chip is closed in an inert gas atmosphere to prevent moisture penetration and to optimally protect the chip against corrosion. Prefabricated plastic packages are characterized by a metallic system carrier overmoulded with a plastic frame—with or without a base—according to the wiring technique. Such enclosures are closed by pressing in prefabricated lids after filling with a gel protecting against moisture. Only bending and cutting operations are required for completion. This type of assembly permits a high degree of automation, but corrosion protection is limited due to the restricted protection against moisture. The chips are freely accessible on the board’s surface after wiring in bare chip assembly. Often there is no special protection for the chips since the entire board is housed in a protective package.

244

13  Packaging of Integrated Circuits

The nacked chips are often covered with carbon black-filled silicone compound or blackened epoxy resin adhesives on printed circuit boards. These covers prevent environmental influences such as ambient humidity or light and impede mechanical damage to the connections during further processing of the boards. For bare chip assembly, this protection is sufficient since the boards themselves are encapsulated. So the chips are rarely exposed to environmental influences. Finally, the assembly technique is followed by a function and parameter test of the circuits, including a “burn-in” step. The chips are operated under an increased temperature load for a fixed period in this process. The encapsulated integrated components are now available to the user for analogue and digital applications such as CMOS or bipolar circuits.

13.5 Chip Assembly Tasks Task 13.1 Calculate the energy required to remelt a gold wire with a diameter of 25 μm into a sphere with a diameter of 60 μm (Tliquid,Gold = 1064 °C, cp,Gold = 0.128 Jg−1 K−1, ρAu = 19.82 g/cm3). Which capacitance must be selected for a spark discharge with 60 V voltage to apply this energy? Task 13.2 A chip of area 1 cm2 is to be packaged in a package made of epoxy resin (thermal conductance k = 0.007 Wcm−1 K−1) or in a package made of Al2O3 ceramic (k = 0.17 Wcm−1 K−1). The housing has a thickness of 2 mm. Which is the maximum power dissipation in each case if the junction temperature Tj is 125 °C or less? The air temperature is 20 °C, and the thermal coupling coefficient between the housing surface and ambient air with free circulation is Θca = 2 °C/W. Total thermal resistance: Θja = Θjc + Θca = (Tj—Ta)/P, with Ta as the ambient temperature, Tj as the junction temperature, and Θjc as the package thermal resistance.

References 1. Hacke, H.-J.: Montage Integrierter Schaltungen In: Engl, W., Friedrich, H., Weinerth, H. (Editors). Series Mikroelektronik. Springer, Berlin (1987) 2. Murray, C.: Die Separation: Changing to Meet Industry Needs, Semiconductor int., pp. 48–49 (1986) 3. Hsu, T.-R.: MEMS Packaging, p. 187. Inspec, London (2004)

Annexes

Appendix A: Solutions to the Tasks Task 1.1 From the disc diameter D and the diagonal d = 14.14 mm of the chip, a square area with n × n chips can first be calculated. The chips fitting the remaining space can be calculated by considering the height and width of the remaining area elements (Table A.1). Task 1.2 Analogous to task 1.1, a square chip with an edge length of 30 mm has a diagonal d = 42.43 mm. For a regular arrangement of the chips around the centre of the wafer, it follows (Table A.2): For a nonsymmetrical arrangement, 1 more chip can be arranged on the 200 mm wafer and 4 more chips on the 300 mm wafer, but these wafers can no longer be disassembled by dicing as the scratch line is locally shifted. Task 2.1 Assuming a spherical potential distribution in the crystal and the approximation “s is very small compared to the sample thickness”, the electric potential V

V=

1 1 1 + V0 ( − 3s − r) 2πσ r

(A.1)

Table A.1  Number of chips per wafer Chips in the square: Edge chips: Number of chips:

3”

100 mm

150 mm

200 mm

300 mm

25

49

100

196

441

4 × 1

4 × 4

4 × (8 + 4)

4 × (12 + 8)

4 × (19 + 15 + 13 + 7)

29

65

148

276

657

© Springer Fachmedien Wiesbaden GmbH, part of Springer Nature 2023 U. Hilleringmann, Silicon Semiconductor Technology, https://doi.org/10.1007/978-3-658-41041-4

245

246

Annexes

Table A.2  Number of chips per wafer in case of 30 mm edge length 3”

100 mm

150 mm

200 mm

300 mm

Chips im Block:

0

4

9

16

49

Randchips: Summe der Chips:

2

0

0

4 × 2

4 × 3

2

4

9

24

61

with V0 as the potential at infinite distance (here = 0). With r = s for tip 2 and r = 2 s for tip 3 the potential difference is given by

∆V = V2 − V3 =

1 2πσ s

(A.2)

Thus it follows for the specific conductance

σ =

1 2π ∆Vs

(A.3)

A specific resistance of 15.7 Ωcm can be calculated from the given numerical values, i.e. the crystal fulfils the specification. Since the resistivity is provided by the equation

ρ=

1 1 ) = ( σ q µn n + µp p

(A.4)

a doping concentration of 3 × 1014 cm−3 follows in case of complete electrical activation of the dopants for n = ND, n >  > p with a charge carrier mobility µn of 1350 cm2/Vs. Task 2.2 From the given masses MSi = 500 kg and MB = 20 mg, the molar masses for silicon mmSi = 28.09 g/mol and boron mmB = 10.81 g/mol, using the atomic density of silicon NSi = 5 × 1022 cm−3:

NBor =

MB mmSi = 5.2 · 1015 cm−3 MSi mmB

(A.5)

Task 3.1 Using the data from Table A.3 the proportion of silicon MSi per cubic centimetre of SiO2 is calculated as:

MSi = ρSiOs

g mSi = 1.0611 3 mSiO2 cm

(A.6)

Thus, the thickness of the consumed silicon layer follows by:

dSi =

MSi · d0 = 0.46 · d0 MSiO2

i.e. 46% of the oxide thickness is consumed in silicon.

(A.7)

Annexes

247

Table A.3  Material data for silicon and silicon dioxide

Material: Silicon SiO2

Density ρ

Molecular weight m

2.33 g/cm3

28.0855 g/mol

2.27 g/cm3

60.0843 g/mol

Task 3.2 Due to the high oxide thickness of 2 μm, the natural oxide thickness t0 in Eq. (3.3) can be neglected. With the data from Table 3.3, the oxidation times tox given in Table A.4 can be calculated. For high temperatures, the approximation according to Eq. (3.5) applies. Dry oxidation is not applicable for 2 μm oxide thickness because of the highly long oxidation times. Task 3.3 About 45% of the oxide thickness is consumed as silicon from the wafer during oxidation. Consequently, 4.5 × 1011 phosphorus atoms are released from the volume of converted silicon. With a segregation coefficient of k = 10, 4.09 × 1011 atoms are deposited in the silicon; the rest are incorporated in the oxide. Converted to 100 nm crystal depth, this means additional doping of approx. 4.1 × 1016 cm−3. Thus, a surface doping of the silicon of 5.1 × 1016 cm−3 phosphorus is present. Task 4.1 The resolution of ± 200 nm at the chip level is obtained after a 5:1 reducing projection, i.e. an accuracy of ± 1  μm is required at the reticle level. In contrast, the chromium etching error of ± 0.05  μm is negligible. The optical reduction factor of 10 further reduces the position error of the apertures in the pattern generator so that an accuracy of ± 10  μm = ± 0.01 mm is required in the aperture positioning. Task 4.2 For λ = 365 nm, at an intensity of P = 10 mW/cm2 and a transmission T = 0.9 of the mask, it follows for the exposure time in seconds

t=

E = 11.1s PT

(A.8)

Table A.4  Comparison of oxidation rates Wet oxidation 920 °C ß [µm2/s]:

5.29 . 10–5

tox after Eq. 3.5 [h]: α [µm/s]: tox after Eq. 3.3 [h]:

1200 °C

Dry oxidation 920 °C

1200 °C

2.15 . 10–4

1.47 . 10–6

1.22 . 10–5

21.0

5.16

756.8

90.8

0.974

0.0968

0.321

0.0491

31.2

5.41

878.5

93.1

248

Annexes

For λ = 320 nm the intensity of the lamp decreases to P = 4.5 mW/cm2, also the transmission of the mask decreases to T = 0.75. Thus it follows that the exposure time t increases to 29.6 s. Task 4.3 Relevant to the calculation is the difference in the expansion coefficients. Assuming an optimal adjustment in the centre of the wafer, the following equation applies for the expansion to the edge of the wafer: ( ) 3.7 × 10−6 K−1 − 2.5 × 10−6 K−1 · ΔT · 50 mm = 200 · 10−6 mm So the maximum temperature variation allowed from the first to the last photolithography step is ΔT = 3.3 °C.

Task 5.1 With r = 75 nm/min, an etching time of 4 min is required to etch the 300 nm thick polysilicon layer. Due to the anisotropy of the etching process, a residue with the height of the field oxide thickness remains at the field oxide edge. This residue of 780 nm height requires an etching time of 10.4 min. During this time, the gate oxide is exposed to the plasma. The etch rate for oxide is 3,125 nm/min with the stated selectivity of 24:1, i.e. 32.5 nm of oxide is removed during the etching of the edges. Consequently, a minimum oxide thickness of 32.5 nm is required. Due to layer thickness fluctuations, an approx. 10% higher layer thickness should be selected for safety. Task 5.2 The processing time for splitting the surface oxide is 1 min so that at a selectivity of 4:1 both 40 nm aluminium and 10 nm photoresist are removed. Step 2 is the “working process” for rapid removal of the metallization. At S = 1.25:1, 100 nm of aluminium and 80 nm of photoresist are removed per minute. The aluminium residues to be etched from the surface are removed in approx. 2 min in step 3. At a selectivity of 6.25:1, only 14.4 nm of photoresist are lost. Consequently, a total of 975.6 nm of photoresist is available for step 2, i.e. this process may take a maximum of 12.2 min. Here, too, a safety margin of 10% should be considered, i.e. the etching time should not exceed 11.0 min. Thus, with a resist thickness of 1 μm, the aluminium layer may be 1.23 μm thick. Task 5.3 The intensity oscillations result from interference of the radiation reflected at the surface of the layer with the backscattered one at the substrate interface. The etch rate is determined by the wavelength of the light, the layer's refractive index and the distance between the minima (maxima) of the oscillations.

Annexes

249

Destructive interference occurs in the case of perpendicular incidence of radiation at (λ /4 + i · λ/2)· nSiO2, i.e. the time between the extreme values corresponds to a layer thickness reduction of 216.5 nm. The etch rate can then be calculated as 134 nm/min. The etching process starts at 40 s and ends at approx. 460 s on the time scale, i.e. the etching time is 420 s. The layer was thus 938 nm thick. Task 5.4 Up to a depth of 20 μm, the etching process proceeds linearly with time. After 20 min, the 5% reduction of the etching rate begins with increasing trench depth. At the desired depth of 50 μm, 30 μm still has to be removed.

30µm = t · 1 µm/ min (1−5%)30

which equals t = 55 min. Add to this 20 min of linear etching, i.e. the total etching time is 75 min. With 10 nm of photoresist removed per minute, a total of at least 750 nm of resist is required for the mask. Task 6.1 Solve Eq. (6.10) for Q using C(x = 0) = 1021 cm−3 and insert into Eq. (6.9). The diffusion length L can be calculated with C(xj = 1 μm) = 1018 cm−3 and Eq. (6.8); it gives L = 0.38 μm. Then the surface occupancy of the crystal can be determined from Eq. (6.10) to be 3.36 × 1016 cm−2. Task 6.2 At the position of the pn-junction in the silicon crystal, NA = ND = 2 × 1014 cm−3. So the concentration is C(xj,t = 50,400 s) = 2 × 1014 cm−3. The near-surface implantation is comparable to a surface coating with dopants, consequently diffusion from an finite source can be applied. According to Eq. (6.11), with EA, boron = 3.7 eV and D0, boron = 14 cm2/s for the diffusion coefficient at 1000 °C, D = 3.24–10–14 cm2/s follows. For xj according to Eq. (6.9), the following applies

xj =

√

( )√ C xj , t πDt ) −4Dtln( Qt

(A.9)

Under the given conditions, the pn-junction depth is xj = 2.7 μm. For the surface concentration after diffusion follows accordingly C(0, 50,400 s) = 1.4 · 1018 cm−3. Task 6.3 This is a diffusion from an finite source with the dopant quantity Q = 5 × 1012 cm−2. The diffusion coefficient at 1170 °C follows according to Eq. (6.11) with EA, phosphorus = 3.66 eV and D0,phosphorus = 3.85 cm2/s to be D = 6.41 · 10–13 cm2/s. Eq. (6.9) can only be solved numerically for the diffusion time determination. This results in t = 50,400 s or 14 h for the diffusion time. The surface concentration is C(0,t) = 1.56 · 1016 cm−2.

250

Annexes

Task 6.4 The elements arsenic and phosphorus are suitable for doping. Antimony also acts as an n-type dopant in silicon, but not all of the introduced Sb atoms can be electrically activated at this high irradiation dose. The implantation time timp is calculated according to the equation

timp =

eDF I

(A.10)

with F as the area to be irradiated, e = elementary charge, D = ion dose and I = ion current. With F = 78.54 cm2 follows timp = 21.0 min. The number of integrator pulses N per charge quantity Q can be calculated according to

N=

eDF Q

(A.11)

N=

I ·t Q

(A.12)

or

As a result, 419 pulses for single charged ions are necessary to implant the required dose into the crystal. Double charged ions only cause a doubling of the current and thus of the number of charges introduced into the wafer, but not of the amount of dopant. It means that 200 pulses of double-charged ions correspond to 100 pulses of single charged particles, and thus it corresponds to a dose of 2.39 · 1014 cm−2. The energy does not influence the total doping implanted into the crystal, but only on the range and range distribution of the ions. Task 7.1 The deposition process for filling the trenches of width b must be carried out with the best possible conformity, i.e. at high temperature. LPCVD depositions with TEOS according to the reaction Eq. (7.8) or dichlorosilane and N2O according to (7.9) are suitable for this purpose. With conformity of k = 0.9 of the deposition process, a thickness d:

d=

b k = 445 nm 2

(A.13)

is required to fill the trench. Task 7.2 The layer thickness dv deposited on vertical walls follows from the surface layer thickness dh multiplied by the conformity factor K to give

Annexes

251

dv = d h K

(A.14)

With a minimum layer thickness of 0.5 μm on the vertical walls, the surface layer thickness follows to 5 μm for the vapour deposition technique and 0.83 μm for the sputtering process. Since the coating of the lateral surface completely fills the oxide opening after only 0.8 μm of vapour-deposited layer thickness, the total layer thickness required for vapour deposition is only 0.8 μm + 0.42 μm = 1.22 μm. Thus, the thickness of the coating needed is also ensured directly at the oxide edge. Task 7.3 The molecule SiC4H12 weighs 88 atomic units or 1.46 · 10–22 g. 10 g diethylsilane consists of about 6.85 · 1022 molecules, all having one Si atom included. 10% of the silicon atoms react with oxygen, forming SiO2 with a molecular weight of 60 atomic units, giving 0.68 g SiO2. Assuming a density of 2.27 g/cm3 for the oxide and an area of 2 times 78.54 cm2 of the wafer front and reverse sides, diethylsilane enables the deposition of 16.3 µm of SiO2. Task 8.1 Aluminium leads to a Schottky diode on weakly n-doped areas due to the band bending at the metal/semiconductor interface. A strong n+-doping in the contact area can improve the contact resistance as the potential barrier formed by the band bending can be overcome due to thermal emission or the tunnelling effect. Alternatively, a contact metal can be used as an intermediate layer. In this case, the metal must have a low work function difference to the n-type silicon to ensure a low-resistance contact. Silicon with p-type conductivity can be contacted directly with aluminium since aluminium as an acceptor leads directly to increased doping in the contact area. Preventing spiking is essential for a leakage current-free contact. For this purpose, silicon is added to the aluminium, deep implantation is carried out in the contact area, or a barrier metal is introduced to separate the aluminium/silicon alloy system. Task 8.2 a. The Kelvin structure allows direct measurement of contact resistance by injecting a current between a metal and a diffusion terminal. The voltage drop arising at the contact hole can be tapped at the other metal and diffusion terminals which are not loaded by the current flow. For the contact resistance, RK follows directly:

RK =

U I

(A.15)

b. The tape-bare structure consists of a diffusion path of width W with square resistance RD. The bare is divided into two parts of length L1 and L2 by three connections. Thus the equations

2RK +

U1 W RD = L1 I1

(A.16)

252

Annexes

2RK +

U2 W RD = I2 L2

(A.17)

can be set up. By injecting a current and measuring the voltage drop, the contact resistance can be calculated independently of the diffusion resistance:

RK =

L2 U2 I1 − 21 L1 U1 I2 2I1 I2 (L2 − L1 )

(A.18)

c. The resistance of a contact hole chain consists of the diffusion and wire resistances as well as the contact resistances. The total resistance can be calculated with a current/voltage measurement. By determining the diffusion resistance at a resistor structure, a value for the contact resistance can be calculated from the number of contacts and the diffusion resistance areas. However, due to increased current densities in the contact hole area (“current crowding”), the externally determined diffusion resistance is overestimated. So only negative values can be calculated for the contact resistance at this measuring structure. Therefore, this structure is suitable for checking the reliability of the contacts but not for the exact measurement of the contact resistance. Task 8.3 Data for the aluminium conductor track with oxide dielectric:

ρAl = 2.7 µΩcm, εox = 3.9, tox = 700 nm, dL = 500 nm, A = F = 100 µm2

Calculation of capacitances neglecting the fringe fields: Capacitance to substrate:

Cbulk =

ε0 εox F = 4.9 fF tox

(A.19)

Cmet =

ε0 εox A = 6.9 fF dL

(A.20)

Capacitance to the wire:

Total capacitance: Cges, Al = Cbulk + Cmet = 11.8 fF. Resistance of Al wire:

RAl =

ρAl l = 2.7 Ω A

Delay time of the aluminium wire with oxide dielectric:

τAl = RAl · Cges = 31.9fs

(A.21)

Annexes

253

Data for the copper tracwire with xerogel dielectric:

ρCu = 1.7 µΩcm, εXe = 2.2 Capacitance to substrate:

Cbulk =

ε0 εXe F = 2.8 fF tXe

(A.22)

Cmet =

ε0 εXe A = 3.9 fF dL

(A.23)

Capacitance to the wire:

Total capacitance: Cges, Cu = Cbulk + Cmet = 6.7 fF. Resistance of the copper wire:

RCu =

ρCu l = 1.7 A

(A.24)

Delay time of the copper wire with xerogel dielectric:

τCu = RCu · Cges,Cu = 11.4fs The delay time of the wiring level can be reduced by a factor of approx. 2.8 by changing from aluminium to copper while replacing the silicon dioxide with xerogel. Task 9.1 Using the data from Task 6.2, the diffusion coefficient for boron at 960 °C follows to be 3.82 × 10–15 cm2/s. The total number of boron atoms is 9.7 × 108 particles, so the surface dopant density is Qs = 4.86 × 1016/cm2. Thus it follows for the surface concentration in the crystal C(x = 0, t = 1 h) = 2.95 × 1021 cm−3 and for the pn-junction depth below the crystal surface xj = 0.3 μm. Task 9.2 The yield of functional chips YC can be calculated from the element yield YE for n elements according to

YC = YEn

(A.25)

With a high device yield, i.e. a small average defect number per chip x, the following applies

YE = 1 −

x n

(A.26)

For the limit value follows

x lim (1 − )n = e−x n

n→∞

(A.27)

254

Annexes

Instead of the mean defect number per chip, the defect density D and the chip area AC can be used so that for x applies:

x = D · AC

(A.28)

YC = e−DAC

(A.29)

YC = e−10DAC

(A.30)

From this, the chip yield results in

With 10 masks the yield is given by

or for the sought defect density D per mask level:

D=

−ln(YC ) = 0.12 cm−2 10AC

(A.31)

There are 0.12 defects/cm2 per mask plane. Task 10.1 Doping step

Dopant

Method

Tub dopingn

Phosphorous

Implantation/Diffusion

Threshold voltage

Boro

Implantation

Polysilicon

Phosphorous

Coating/Diffusion

Drain-Source PMOS

Boron

Implantation

Drain-Source NMOS

Arsenic

Implantation

Reflow BPSG

Boron, Phosphorous

Coating/Diffusion

Task 10.2 UDS = UB—RID applies to the drain voltage of the MOS transistor. Thus, when the input of the device is fully open, UGS—Ut > UDS applies to the transistor. With the information from the task, it follows:

ßn = 2.59 · 10−4 A/V2 ßp = 1.73 · 10−4 A/V2 From the transistor equation for UGS—Ut > UDS, a maximum current of 453.5 μA for an NMOS transistor and 431.8 μA for a PMOS transistor results when the input is fully modulated. Task 10.3 It is a polysilicon gate NMOS process with an aluminium wiring plane. The resistor consists of 115 squares, so it has a value of 4600 Ω. The design sizes of the transistor are

Annexes

255

W = 40 μm and L = 10 μm. Analogous to task 10.2, the maximum transverse current can be calculated as 385 μA. The residual voltage is 3.23 V at the output. The capacitance oxide thickness is calculated from the electrode area and the given capacitance is 86.3 nm. The gate oxide thickness can be calculated from ß to 165.7 nm. The switching time is limited by the charging of the capacitance; the time is determined by the RC-constant. This results in a time constant of 4.6 ns. The technology cross-section and the circuit diagram are shown in Fig. A.1. Task 10.4 The required values can be calculated from the input characteristics as well as from the output characteristics. However, the surface mobility of the charge carriers changes with increasing field strength in the channel area of the transistor so that an exact determination is only possible at low applied voltages. For this reason, the transfer characteristic is considered. The following applies: ] [ 1 2 ID = β (UGS − Ut )UDS − UDS (A.32) 2 From this equation it follows by differentiation for the maximum slope gm:

gm =

µε0 εr W ∂Id UDS = ∂Ugs tox L

(A.33)

gm tox L ε0 εr WUGS

(A.34)

or for the charge carrier mobility μ:

µ=

For the threshold voltage Ut it follows from the drain current at the point of maximum slope

Ut = UGS −

ID UDS − 2 βUDS

Fig. A.1   Technology cross-section for the layout in task 10.3

(A.35)

256

Annexes

From Fig. 10.11 it follows with gm = 520 μS for the mobility of the electrons μn = 565 cm2/(Vs). At the point of maximum slope, the drain current is ID(UGS = 1.4 V) = 0.2 mA. Thus, the threshold voltage of the NMOS transistor can be calculated as Ut = 0.97 V. Correspondingly, a charge carrier mobility of 167 cm2/Vs and a threshold voltage of Ut = −0.92 V follow from Fig. 10.12 for the PMOS transistor. Task 10.5 In the figure, the recognizable details are labelled (Fig. A.2). Task 11.1 From Fig. 11.1, an oxidation time of approx. 2.5 h can be determined for wet oxidation of 1 μm thickness at 1100 °C. The required nitride layer thickness is then at least 50 nm, whereby the uniformity of the deposition and a safety factor of at least 10% must also be taken into account. A layer thickness of about 60 nm is required for reliable masking. With 20 nm nitride, the silicon surface can only be masked for about 40 min during thermal oxidation. During this time, approx. 250 nm of oxide will grow at 1100 °C. Task 11.2 From the given data, the specific conductivity σ of the drain/source areas can be calculated using ( ) σ = q µn n + µp p ≈ qµn ND (A.36) The square resistance of the drain/source areas is thus 4.24 Ω/◽. Neglecting the resistance of the LDD areas, the parasitic drain/source resistance is as follows.

Rges = 2R

1.8 µm = 1.66 Ω 10 µm

Fig. A.2   Photo of a transistor with the labelling of the individual areas

(A.37)

Annexes

257

For the self-aligned silicide contacts, a value of Rges = 0.288 Ω follows, which is lower by a factor of 5. Task 11.3 The slope gm is given by the change in drain current with a gate voltage change for a constant drain/source voltage. Assuming for all transistors a constant carrier mobility, identical gate oxide thicknesses and transistor widths, there is a linear relationship between the channel length L of the transistors and the reciprocal of the slope.

gm =

µε0 εr W ∂Id UDS = ∂Ugs tox L

(A.38)

From the input characteristic, the slopes can be determined by applying a tangent at the point of the maximum slope of the curve (Fig. A.3 and Table A.5). From the graph of channel length L plotted against UDS/gm, the deviation of the design length from the effective electrical channel length can be determined: Since the intersection of the straight line with the design length axis is at approx. 0.3 μm, the effective electrical transistor channel length is 0.3 μm less than the design length for all transistors. The cause may be the under-etching of the resist mask for gate

Fig. A.3   Graph for determining the effective electrical channel length of MOS transistors

Table A.5  Data for determining the effective electrical channel length

L [µm]

gm,max [µS]

UDS/gm,max [V2/A]

1.0

111.1

900

2.0

48.0

2083

3.5 10.0

26.4

3788

8.65

11,561

258

Annexes

definition. Also, a strong dopant diffusion below the gate during the activation annealing of the implanted ions causes this deviation of about 0.15 μm per gate edge. Task 12.1 see Fig. A.4 Task 12.2 Using the data from Task 6.2, the diffusion coefficient for boron at 1100 °C is D = 3.78 × 10–13 cm2/s. With a substrate doping of 2 × 1014 cm−3, the pn-junction of the base to the collector is at a depth of 6.4 μm. For phosphorus, the diffusion coefficient at 1024 °C is 2.15 × 10–14 cm2/s. The position of the pn-junction emitter/base is determined by the concentration equality of the boron profile and the phosphorus distribution, i.e. CB(xj,tB) = CP(xj,tP). It results in a pn-junction depth of 232 nm, so that the base width of this bipolar transistor is about 6.17 μm. The phosphorus diffusion supports the boron diffusion so that the base diffuses more profound into the crystal in the region of the emitter. Consequently, the base width of the transistor is increased, but the gain is lower than expected. Task 12.3 The specific conductance of the epitaxial layer is given by σ = qμnND = 2.16 (Ωcm)−1. Thus, for the dimensioning of the length l and width b of a resistor for a given layer thickness d, it follows that

l = σ dR = 0.065 b

(A.39)

A resistor of 10 μm width may only be 0.65 μm long. Since this length cannot be manufactured reproducibly, emitter diffusion or base diffusion should be used for such a low-resistance resistor. Larger widths for the transistor are not practical due to the area required.

Fig. A.4   Cross-section of a vertical and a lateral pnp transistor

Annexes

259

Task 13.1 The volume of the gold sphere is 1.13 × 10–7 cm3 with a mass of 2.24 × 10–6 g. For melting, a temperature difference of 1044 K has to be overcome at room temperature, i.e., neglecting heat conduction, energy of

E = cp · mAu · ΔT = 2.9 · 10−4

(A.40)

must be supplied. The electrical energy is calculated from

E = U · I · t = 1/2 · U 2 · C

(A.41)

C = 2E/U 2 = 160 nF

(A.42)

i.e. for the capacitance at 60 V follows:

Task 13.2 The specific thermal conductance k can be converted into the thermal resistance according to

θ=

d Ak

(A.43)

For epoxy packages it follows Θepoxy = 14,286 °C/W for heat dissipation from both chip sides, for Al2O3 packages the value is ΘAl2O3 = 0.588 °C/W. With a contact resistance from the package to the air of Θca = 2 °C/W, for the power follows

P=

Tj − T a θca + θjc

(A.44)

For epoxy packages the power loss is 6.4 W, for Al2O3 ceramics 40.6 W.

Appendix B: Colour Table Oxide Thicknesses Colour table for determining the film thickness of thermal oxides on silicon (viewing direction: perpendicular to the surface) /18/. The film thickness x of other transparent films can be determined from the ratio of the refractive indices: tx = tox · nox/nx. Thickness (μm)

Colour

0–0.04

Colourless

0.050

Slightly brownish

0.075

Brown

0.100

Dark to reddish violet

0.125

Royal blue

0.150

Light blue to metallic blue

260

Annexes

Thickness (μm)

Colour

0.175

Metallic, slightly yellowish

0.200

Yellow to golden

0.225

Golden with light yellow-orange

0.250

Orange to melon

0.275

Red-violet

0.300

Blue to violet

0.310

Blue

0.325

Blue to blue-green

0.345

Light green

0.365

Yellow-green

0.390

Yellow

0.412

Light orange

0.426

Pale red to pink

0.443

Violet-red

0.443

Violet-red

0.476

Violet

0.480

Blue-violet

0.493

Blue

0.502

Blue-green

0.520

Green

0.540

Yellow-green

0.574

Yellow

0.585

Light orange

0.60

Pale red to pink

0.63

Violet-red

0.68

Bluish

0.72

Blue-green

0.80

Very light orange

0.85

Matt light red–purple

0.86

Violet

0.87

Blue-violet

0.89

Blue

0.92

Blue-green

0.95

Matt yellow

0.97

Yellowish

Annexes

261

Thickness (μm)

Colour

0.99

Orange

1.00

Pale red to pink

1.02

Violet-red

1.06

Violet

1.07

Blue-violet

1.10

Green

1.18

Red-violet

1.25

Orange

Appendix C: Chemical Compounds and Abbreviations Acetone

C3H6O

Cleaning, paint stripping

Aluminium

Al

Dopant, p-doping

Ammonia

NH3

CVD

Antimony

Sb

Dopant, n-doping

Argon

Ar

Noble gas, plasma etching, sputtering

Arsenic

As

Dopant, n-doping

Arsine

AsH3

Dopant source

Boron

B

Dopant, p-doping

Boron trichloride

BCl3

Dry etching

Boron trifluoride

BF3

Dopant gas for implantation

Chlorine

Cl2

Dry etching

DES(Dieethylsilane)

SiC4H12

CVD, liquid source for silicon

Dichlorosilane

SiH2Cl2

CVD/gas phase epitaxy

Diborane

B2H6

Dopant source

Nitrous oxide (laughing gas)

N2O

PECVD/LPCVD

DTBS (ditertiarbutylsilane)

SiH2C8H18

CVD, liquid source for silicon

Fluoromethane

CH3F

Selective nitride etching

Hydrofluoric acid

HF

Etches SiO2, highly hazardous

Gallium

Ga

Dopant, p-doping

HMDS (hexamethyldisilazane)

Si2C6H18

Bonding agent—lithography

Indium

In

Dopant, p-doping

262

Annexes

Acetone

C3H6O

Cleaning, paint stripping

Potassium hydroxide

KOH

Anisotropic etchant for Si

Lithium hydroxide

LiOH

Anisotropic etchant for Si

Sodium hydroxide

NaOH

Developer, anis. etching solution

Phosphine

PH3

Dopant source

Phosphorus

P

Dopant, n-doping

Phosphoric acid

H3PO4

Etches silicon nitride

Nitric acid

HNO3

Part of Al etching solution

Hydrochloric acid

HCl

Cleaning

Oxygen

O2

Oxidation, RIE

Sulphur hexaflouride

SF6

Dry etching gas

Sulphuric acid

H2SO4

Cleaning

Silane

SiH4

Silane pyrolysis

Silicon nitride

Si3N4

Masking, possible insulating material

Silicon oxide

SiO2

Good insulating material

Silicon oxynitride

SiON

Possible insulating material

Silicon tetrachloride

SiCl4

Gas phase epitaxy

Nitrogen

N2

Carrier gas, flooding of equipment

TEOS (tetraetyhlorthosilicate)

SiO4C8H20

Fast growing SiO2

Titanium silicide

TiSi

Self-aligning contacts

TMAH (tetramethyl ammonium hydroxide)

C4H13NO

Developer, ani. etching solution

TMB(trimethyl borate)

BC3H9

Dopant source for B

TMP(trimethyl phosphate)

PC3H9

Dopant source for P

TOMCATS(tetramethyl-cylotetrasiloxane)

SiO4C4H16

Liquid source silicon oxide CVD

Trichlorosilane

SiHCl3

Purification of silicon

Trifluoromethane

CHF3

Dry etch gas

Hydrogen

H2

Oxidation, annealing

Hydrogen peroxide

H2O2

Cleaning/etching solution

Tungsten hexafluoride

WF6

Tungsten deposition

ALD

Atomic layer deposition

APCVD

Atmospheric pressure chemical vapour deposition

ASIC

Application specific integrated circuit

BPSG

Boron-phosphorus-silicate glass

BSG

Boron-silicate glass

CAIBE

Chemically assisted ion beam etching

CARL

Chemically amplified resist lithography

Annexes

263

CMOS

Complementary metal oxide semiconductor

CMP

Chemical mechanical polishing

CVD

Chemical vapour deposition

DC

Direct current

DES

Diethylsilane

DIBL

Drain induced barrier lowering

DTBS

Ditertiary butylsilane

DUV

Deep ultra violet

ECR

Electron cyclotron resonance

EUV

Extreme ultra violet

FET

Field effect transistor

FIB

Focused ion beam

FIPOS

Full isolation by porous oxidized silicon

GSI

Giant scale integration

HF

High frequency

HMDS

Hexamethyldisilazane

HTO

High temperature oxide

IBE

Ion beam etching

ICP

Inductive coupled plasma

IGBT

Insulated gate bipolar transistor

IMD

Inter metal dielectric

LDD

Lightly doped drain

LOCOS

Local oxidation of silicon

LPCVD

Low pressure chemical vapour deposition

LPD

Liquid phase deposition

LSI

Large scale integration

LTO

Low temperature oxide

MERIE

Magnetically enhanced reactive ion etching

MGS

Metallurgical grade silcon

MOS

Metal oxide semiconductor

NA

Numerical aperture

NMOS

N-channel metal oxide semiconductor

PE

Plasma etching

PECVD

Plasma enhanced chemical vapour deposition

PMOS

P-channel metal oxide semiconductor

SEM

Scanning electron microscope

RF

Radio frequency

264

Annexes

RIE

Reactive ion etching

SBC

Standard buried collector

SCALPEL

Scattering with angular limitation projection electronbeam lithography

SEM

Scanning electron microscope

SILO

Sealed interface local oxidation

SiMOX

Silicon implanted oxide

SOG

Spin-on glass

SOI

Silicon on insulator

SPOT

Super planar oxidation technology

STI

Shallow trench isolation

SWAMI

Side wall masked isolation

TAB

Tape automated bonding

TEOS

Tetraetyhlorthosilicate

TMAH

Tetramethylammonium hydroxide

TMB

Trimethyl borate

TMP

Trimethyl phosphate

TOMCATS

Tetramethylcylotetrasiloxane

TSV

Through silicon vias

US

Ultra sonic

VLSI

Very large scale integration