Lecture Notes in Analog Electronics: Low Voltage Electronic Components 9811998671, 9789811998676

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Lecture Notes in Electrical Engineering 1002

Vančo Litovski

Lecture Notes in Analog Electronics Low Voltage Electronic Components

Lecture Notes in Electrical Engineering Volume 1002

Series Editors Leopoldo Angrisani, Department of Electrical and Information Technologies Engineering, University of Napoli Federico II, Napoli, Italy Marco Arteaga, Departament de Control y Robótica, Universidad Nacional Autónoma de México, Coyoacán, Mexico Bijaya Ketan Panigrahi, Department of Electrical Engineering, Indian Institute of Technology Delhi, New Delhi, Delhi, India Samarjit Chakraborty, Fakultät für Elektrotechnik und Informationstechnik, TU München, München, Germany Jiming Chen, Zhejiang University, Hangzhou, Zhejiang, China Shanben Chen, School of Materials Science and Engineering, Shanghai Jiao Tong University, Shanghai, China Tan Kay Chen, Department of Electrical and Computer Engineering, National University of Singapore, Singapore, Singapore Rüdiger Dillmann, University of Karlsruhe (TH) IAIM, Karlsruhe, Baden-Württemberg, Germany Haibin Duan, Beijing University of Aeronautics and Astronautics, Beijing, China Gianluigi Ferrari, Dipartimento di Ingegneria dell’Informazione, Sede Scientifica Università degli Studi di Parma, Parma, Italy Manuel Ferre, Centre for Automation and Robotics CAR (UPM-CSIC), Universidad Politécnica de Madrid, Madrid, Spain Sandra Hirche, Department of Electrical Engineering and Information Science, Technische Universität München, München, Germany Faryar Jabbari, Department of Mechanical and Aerospace Engineering, University of California, Irvine, CA, USA Limin Jia, State Key Laboratory of Rail Traffic Control and Safety, Beijing Jiaotong University, Beijing, China Janusz Kacprzyk, Intelligent Systems Laboratory, Systems Research Institute, Polish Academy of Sciences, Warsaw, Poland Alaa Khamis, Department of Mechatronics Engineering, German University in Egypt El Tagamoa El Khames, New Cairo City, Egypt Torsten Kroeger, Intrinsic Innovation, Mountain View, CA, USA Yong Li, College of Electrical and Information Engineering, Hunan University, Changsha, Hunan, China Qilian Liang, Department of Electrical Engineering, University of Texas at Arlington, Arlington, TX, USA Ferran Martín, Departament d’Enginyeria Electrònica, Universitat Autònoma de Barcelona, Bellaterra, Barcelona, Spain Tan Cher Ming, College of Engineering, Nanyang Technological University, Singapore, Singapore Wolfgang Minker, Institute of Information Technology, University of Ulm, Ulm, Germany Pradeep Misra, Department of Electrical Engineering, Wright State University, Dayton, OH, USA Sebastian Möller, Quality and Usability Lab, TU Berlin, Berlin, Germany Subhas Mukhopadhyay, School of Engineering, Macquarie University, NSW, Australia Cun-Zheng Ning, Department of Electrical Engineering, Arizona State University, Tempe, AZ, USA Toyoaki Nishida, Department of Intelligence Science and Technology, Kyoto University, Kyoto, Japan Luca Oneto, Department of Informatics, Bioengineering, Robotics and Systems Engineering, University of Genova, Genova, Genova, Italy Federica Pascucci, Department di Ingegneria, Università degli Studi Roma Tre, Roma, Italy Yong Qin, State Key Laboratory of Rail Traffic Control and Safety, Beijing Jiaotong University, Beijing, China Gan Woon Seng, School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore, Singapore Joachim Speidel, Institute of Telecommunications, University of Stuttgart, Stuttgart, Germany Germano Veiga, FEUP Campus, INESC Porto, Porto, Portugal Haitao Wu, Academy of Opto-electronics, Chinese Academy of Sciences, Haidian District Beijing, China Walter Zamboni, Department of Computer Engineering, Electrical Engineering and Applied Mathematics, DIEM—Università degli studi di Salerno, Fisciano, Salerno, Italy Junjie James Zhang, Charlotte, NC, USA

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Vanˇco Litovski

Lecture Notes in Analog Electronics Low Voltage Electronic Components Including Diodes, Transistors, Optoelectronic and Magnetoelectronic Devices, and Semiconductor Technology

Vanˇco Litovski Elektronski Fakultet Niš, Serbia

ISSN 1876-1100 ISSN 1876-1119 (electronic) Lecture Notes in Electrical Engineering ISBN 978-981-19-9867-6 ISBN 978-981-19-9868-3 (eBook) https://doi.org/10.1007/978-981-19-9868-3 © The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 This work is subject to copyright. All rights are solely and exclusively licensed by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. The publisher, the authors, and the editors are safe to assume that the advice and information in this book are believed to be true and accurate at the date of publication. Neither the publisher nor the authors or the editors give a warranty, expressed or implied, with respect to the material contained herein or for any errors or omissions that may have been made. The publisher remains neutral with regard to jurisdictional claims in published maps and institutional affiliations. This Springer imprint is published by the registered company Springer Nature Singapore Pte Ltd. The registered company address is: 152 Beach Road, #21-01/04 Gateway East, Singapore 189721, Singapore

Preface

This is the first book of the series Lecture Notes in Analogue Electronics. It is devoted to electronic components and partly to the technology implemented in their production. It was said by the ancient Latins: “Initia omnium rerum difficillia sunt” (beginnings of all things are difficult). You are about to enter a new world where hundreds of new terms will be introduced describing quantities, physical phenomena and lows, chemical processes, components, and technologies. Of course, it must be so since you are entering a trade that did change and is still furiously changing the world. “Per aspera ad astra” (Through difficulties to the stars) was also said by the Latins. We believe, however, your effort will lead to a success and you will become a part of the thriving electronic engineering community. Here we will start from the very beginning which is the structure of the atom. Based on this, we will present the most important materials used in today’s electronic components: semiconductors. Among them, silicon is the most valued since by far the largest number of modern electronic components are based on it. The p–n junction is part of any electronic component. Even the very resistor if it is embedded in an electronic circuit must contain a p–n junction enabling its functionality. We will go deep into the formation, properties, characteristics, and modeling of this structure since that will facilitate the understanding of the functionality of any other electronic component. Wen implemented as the main functional part of a component the p–n junction serves as a diode. The diode is in fact the first component taken under scrutiny here. The technological procedure to make it, its structure, properties (static and dynamic), its characteristic, limitations, and modeling will be seriously studied. Variants of the diode being convenient for many specific applications will be listed and described in most detail. The diode as part of the integrated circuit will be described too.

v

vi

Preface

The first active component which will be studied is the bipolar junction transistor (BJT). Again, the technological procedure to make it, its structure, properties (static and dynamic), its characteristic, limitations, and modeling will be seriously studied. Variants of the BJT will also be studied including their parameters and the properties of these parameters. The same is done for the junction field effect transistor (JFET), the metal oxide semiconductor field effect transistor (MOSFET), and the metal-semiconductor field effect transistor (MESFET). Special attention is devoted to the component whose behavior is based on the interaction of light and semiconductor. Two main categories of such components are discussed. The ones which are based on changing the properties of the illuminated semiconductor are referred to as photo-devices. Here we have a family of components including diodes, transistors, and others. Special attention will be devoted to the solar cells which are the ones that fully bridged the gap between electronics (low-current electricity) and electrical engineering (high-current electricity). On the other end, one has the semiconductor Devices Emitting Light. Among them a set of LEDs and the laser will be discussed. Finally, a combination of LED and photo-device named opto-coupler will be introduced. Finally, magnetoelectronic devises will be considered being fundamentally based on the physical force of the magnetic field on a moving electron (in a semiconductor). Hall-effect devices as well as a variety of magneto-devices will be studied. The text is accompanied with four appendices which we expect will help the reader to complete the picture. To finish, the author wishes to the reader many pleasant hours reading the book. Niš, Serbia

Vanˇco Litovski

Introduction to the Lecture Notes of Analogue Electronics (LNAE) SERIES

The electron is a phenomenon exhibiting divine properties. We all know it exists but none can see it. Obviously, we consider Electronics inherits his divinity.

Electronics is, nowadays, ubiquitous. There is no aspect of human life being not supported by electronics. None would deny this claim. Even so, when comes to studying electronics, and especially analog electronics, it is mostly avoided by many talented students since it is considered difficult to study. Thus, it is our intention to produce a series of books that will be student oriented and, probably not understandable at first glance, electronics oriented. In that way, we expect to help attracting more young and talented people to study electronics and to further contribute to the human society. In this pamphlet, we will consider two issues. We will first try to answer the question as to why electronics is difficult to study, and then we will give the rationale for preparing a series of books related to analog electronics only. Let’s start with the difficulty. Ever since Nikola Tesla introduced the alternating current (AC) circuits, the primary circuit elements became the coil, the transformer, the AC motor, and the transmission line. All these were described by voltage equations which originate from the discovery of the Russian physicist Heinrich Lenz of the directional relationships between induced magnetic fields, voltage, and current when a conductor is passed within the lines of force of a magnetic field. Lenz’s law states: An induced electromotive force generates a current that induces a counter magnetic field that opposes the magnetic field generating the current. As a consequence, voltage equations were introduced everywhere including the exclusive use of Kirchhoff’s voltage law. That we call the electrical engineering approach to the circuit. The things went so far that even Ohm’s law which should read i = G·v (currents are on both sides) was transformed into his voltage version v = R·i. In that, two serious problems were introduced which concern the modern student of electronics. First, in v = R·i the independent variable is on the left-hand side of the equation while the function (the consequence) is on the right. So, one is supposed first to reorder the equation to come to the solution. That means that, for evaluation of the current, vii

viii

Introduction to the Lecture Notes of Analogue Electronics (LNAE) …

division is supposed to be performed as opposed to the much more natural arithmetic action of multiplication. Of course, to make things still more difficult, instead of the natural quantity which is conductance, resistance was introduced. For example, if a voltage source v is connected to a resistor whose conductance is G = 25 S one would immediately pronounce the value of the current to be i = 25 A. The same resistor has a resistance of R = 40 mΩ, and to come to the current becomes a serious computational task. The transition was so merciless that no schematic symbol for the conductance exists. The conflict becomes still more sever when comes to electronic circuits. Namely, all (no exception) electronic components are modeled by current equation (voltagecontrolled current sources) and, for electronic circuit analysis, Kirchhoff’s current low is the most natural means for equation formulation which is known as nodal equations. A student which is trained to think of voltage equations however is immediately frustrated since he/she does not know what to do with the resistor now. Even a well-trained former student, as is the author of this text, is forced to use reciprocals of the resistances all the time and, at the end of the analysis, is again forced to rearrange the obtained expressions to make them tractable. Of course, modern electronic circuit simulation programs are based on nodal analysis (or the so-called Modified Nodal Analysis) which we would call an electronic approach to the circuits. Nevertheless, due to the voltage background, understanding their functionality is not easy, obstructing their efficient use and, again, is frustrating to many. Next, the students trying to enter into the subject of electronics are facing the duality in electronics which, as we see it, is twofold. To start with, we will mention the synergy (or the conflict) between the DC and AC signals in electronic circuits. In some analyses, these are independent and in others mutually coupled. The fact that the DC supply is a source of energy that is transferred to the useful signal is part of the explanation of what is going on in the circuit. One should understand, however, why even small AC signals (bearing almost no power) are depending on the value of the voltage of the power supply which, in most cases of analysis of incremental circuits, is absent from the schematic. On the other side, one is supposed to understand that, in some electronic circuits, voltages larger than the power supply voltage are produced and limit the applicability of some devices. The other aspect of duality is related to the mutual synergy and antagonism of the time and frequency domain. There is no linear electronic component. That means that the component’s current is a nonlinear function of single or several voltages or currents. So, it is normal, when starting from basic electrotechnics, for nonlinear differential equations to be created to enable the analysis of an electronic circuit. Solving nonlinear differential equation, however, is a task that extremely rarely may be performed in closed form. Practically, there is no time domain electronic circuit analysis without a computer. That is especially true since one has no complete information about the boundary conditions necessary for solving the nonlinear differential equations. That imposes a need for the development of incremental models of electronic devices to allow analysis for small signals. The problem is that, usually, the two versions of the same circuit (the large signal nonlinear and the incremental linear)

Introduction to the Lecture Notes of Analogue Electronics (LNAE) …

ix

are not taught to students as a single complete. To learn the analysis of incremental circuits the students are kept in the so-called “frequency domain” where all of a sudden complex arithmetic is necessary. In that, a complex variable is introduced so that the real frequency of the signal is represented as the imaginary part of the complex frequency. Even the interpretation of the last sentence is confusing if not read several times. This is not the end, however. The students are not rarely facing textbooks written by teachers that want to promote themselves as the ones having strong practical experience. In that, a slang is used as if they are talking to some repair person. Avoiding universal professional terminology and especially verbs representing phenomena within the circuit, invalidates the knowledge delivered and makes the further progress of the student difficult. Having all these in mind it becomes understandable why not only the student but even the teachers face wild wind mills as if they were the Spanish fiction hero Don Quixote. Now, what we want to do with this series of books. We are not in a position to change the unchangeable. The resistors will stay in the schematics as are everywhere and the imaginary part of the complex frequency will still represent the real frequency of the signal. What we can do is to cover the analog electronics as a whole using the same vocabulary which we consider universal. Also, we would like to enable a start from the very beginning in the sense that only very basic knowledge of the student to be necessary to follow the texts. Finally, we want to give a complete knowledge starting with fundamental physics and ending with simulation and optimization, and, especially, with the sustainability aspects of electronic engineering. The series will contain the following issues with the probability for some of them to become merged or splitted in two, according to the running inspiration of the author: Book 1. Semiconductor Components Book 2. Low Voltage Amplifiers and Linear Oscillators Book 3. Semiconductor Technology and Specific Electronic Components Book 4. Discrete and Integrated Large Signal Amplifiers Book 5. Noise in Electronic Circuits and Low Noise Amplifiers Book 6. Power Electronic Circuits Book 7. Analog Electronic Testing Book 8. Analog Electronic Simulation and Optimization Book 9. Artificial Intelligence in Electronic Modeling and Design Book 10. Sustainable Electronic Design. The titles listed here are subject to refinements, too. We really hope that these contents will fit in the contemporary views on the subject and will inspire authors to build on or to make improvements in a way they find better than what we did.

Contents

1.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1

1.2

Electric Current in Semiconductors . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.1 Electronic Structure of the Isolated Atom . . . . . . . . . . . . . . . . . 1.2.2 Electronic Structure of the System of Atoms . . . . . . . . . . . . . . 1.2.3 Electric Current in Semiconductors . . . . . . . . . . . . . . . . . . . . . . 1.2.3.1 P- and N-Type Semiconductors . . . . . . . . . . . . . . . . 1.2.3.2 Concentration of Free Carriers . . . . . . . . . . . . . . . . . 1.2.3.3 The Fermi Level in a Semiconductor . . . . . . . . . . . . 1.2.3.4 The Drift Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.3.5 The Diffusion Current . . . . . . . . . . . . . . . . . . . . . . . . 1.2.3.6 The Continuity Equation . . . . . . . . . . . . . . . . . . . . . .

5 5 9 15 22 26 32 37 41 44

1.3

The p-n Junction and the Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.1 The p-n Junction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.2 Semiconductor Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.2.1 Characteristic of the Diode . . . . . . . . . . . . . . . . . . . . 1.3.2.2 Parameters of the Diode . . . . . . . . . . . . . . . . . . . . . . 1.3.2.3 Temperature Dependence of the Diode Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.2.4 Limitations in the Use of the Diode . . . . . . . . . . . . . 1.3.2.5 Capacitances of the Diode . . . . . . . . . . . . . . . . . . . . . 1.3.2.6 Summary of the Diode Ratings . . . . . . . . . . . . . . . . 1.3.2.7 Varicap Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.2.8 Tunnel Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.2.9 Zener Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.2.10 Metal–Semiconductor Contact and Schottky Diode . . . . . . . . . . . . . . . . . . . . . . . . . .

53 53 57 59 67

1.4

68 71 80 86 88 89 94 97

Bipolar Transistor—BJT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 1.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 1.4.2 Transistor Effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

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Contents

1.4.3 1.4.4 1.4.5 1.4.6 1.4.7 1.4.8

BJT Currents and Their Components . . . . . . . . . . . . . . . . . . . . . Model of the BJT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Characteristics of BJT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Current Gain Coefficient . . . . . . . . . . . . . . . . . . . . . . . . . . . Properties of the BJT at High Frequencies . . . . . . . . . . . . . . . . Characteristics of BJT in Common–Emitter Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.9 Safe Operating Area of the BJT . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.9.1 Maximum Dissipated Power . . . . . . . . . . . . . . . . . . . 1.4.9.2 Current Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.9.3 Minimum Voltage Between Collector and Emitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.9.4 Maximum Collector Voltage . . . . . . . . . . . . . . . . . . . 1.4.9.5 Secondary Breakdown . . . . . . . . . . . . . . . . . . . . . . . . 1.4.9.6 The Complete Active Working Area . . . . . . . . . . . . 1.4.10 Drift Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

109 112 118 120 123

1.5

Junction Field Effect Transistor—JFET . . . . . . . . . . . . . . . . . . . . . . . 1.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.2 Characteristics of a JFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.2.1 Model of the JFET . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.3 Parameters of the JFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.4 Active Operating Area of the JFET . . . . . . . . . . . . . . . . . . . . . . 1.5.5 JFET at High Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.6 JFET as a Voltage-Controlled Resistor . . . . . . . . . . . . . . . . . . . 1.5.7 Constant Current Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

143 143 146 147 155 159 161 162 163

1.6

Insulated Gate Field-Effect Transistors—IGFET . . . . . . . . . . . . . . . 1.6.1 MOS Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6.1.1 MOS Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6.1.2 Threshold Voltage of the MOS Structure . . . . . . . . 1.6.2 MOS Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6.3 Modeling the MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6.3.1 Models of Short-Channel MOS Transistors . . . . . . 1.6.3.2 MOSFET Model in the Subthreshold Region . . . . . 1.6.4 Parameters of the MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6.5 Active Operation Area of the MOSFET . . . . . . . . . . . . . . . . . . 1.6.6 Capacitances of the MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6.7 Dual-Gate MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

165 165 169 171 175 180 187 191 192 194 196 198

1.7

MESFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7.1 The Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7.2 MESFET Model for Large Signals . . . . . . . . . . . . . . . . . . . . . . . 1.7.3 Characteristics of the MESFET . . . . . . . . . . . . . . . . . . . . . . . . . 1.7.4 Parameters of the MESFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7.5 Dynamic Properties of the MESFET . . . . . . . . . . . . . . . . . . . . .

201 201 205 207 208 210

126 132 133 135 135 136 138 138 140

Contents

1.7.6 1.7.7

xiii

Active Operation Area of the MESFET . . . . . . . . . . . . . . . . . . . 212 Development of a MESFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

1.8

Optoelectronic Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8.1 Photodetectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8.1.1 Photoresistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8.2.1 Photodiode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8.1.3 Solar Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8.1.4 Other Photodetectors . . . . . . . . . . . . . . . . . . . . . . . . . 1.8.2 Light Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8.2.1 LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8.2.2 Semiconductor LASER Diode . . . . . . . . . . . . . . . . . 1.8.3 Optocouplers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

215 215 217 220 226 240 243 244 251 256

1.9

Magnetoelectronic Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.9.2 Hall Generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.9.3 Magnetoresistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.9.4 Magnetodiode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.9.5 Magnetotransistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

261 261 265 270 271 272

1.10 Basics of Semiconductor Technology . . . . . . . . . . . . . . . . . . . . . . . . . . 1.10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.10.2 Processes in the IC Production Technology . . . . . . . . . . . . . . . 1.10.2.1 Obtaining Silicon Crystals . . . . . . . . . . . . . . . . . . . . 1.10.2.2 Formation of p–n Junctions . . . . . . . . . . . . . . . . . . . . 1.10.2.3 Semiconductor Surface Protection . . . . . . . . . . . . . . 1.10.2.4 Lithography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.10.3 Bipolar Integrated Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.10.3.1 JFET in Bipolar Integrated Circuits . . . . . . . . . . . . . 1.10.4 MOS Integrated Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.10.5 Hybrid Integrated Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.10.5.1 Thick-Film Integrated Circuits . . . . . . . . . . . . . . . . . 1.10.5.2 Thin-Film Hybrid Integrated Circuits . . . . . . . . . . .

277 277 280 280 283 290 291 294 305 306 320 320 328

1.11 Solved Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 1.12 Examples with SPICE Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 1.13 Part Numbering Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413 1.13.1 The Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413 1.13.2 Pro-electron or EECA Numbering Coding System . . . . . . . . . 413 Literature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419

About the Author

Prof. Vanˇco Litovski was born in 1947 in Rakita, South Macedonia, Greece. He graduated from the Faculty of Electronic Engineering in Niš in 1970, and obtained his M.Sc. in 1974, and his Ph.D. in 1977. He was appointed as a teaching assistant at the Faculty of Electronic Engineering in 1970 and became a Full Professor at the same faculty in 1987. He was elected as Visiting Professor (honoris causa) at the University of Southampton in 1999. From 1987 until 1990, he was a consultant to the CEO of Ei, and was Head of the Chair of Electronics at the Faculty of Electronic Engineering in Niš for 12 years. From 2015 to 2017, he was a researcher at the University of Bath. He has taught courses related to analog electronics, electronic circuit design, and artificial intelligence at the electro-technical faculties in Priština, Skopje, Sarajevo, Banja Luka, and Novi Sad. He received several awards including from the Faculty of Electronic Engineering (Charter in 1980, Charter in 1985, and a Special Recognition in 1995) and the University of Niš (Plaque 1985). Prof. Litovski has published 6 monographs, over 400 articles in international and national journals and at conferences, 25 textbooks, and more than 40 professional reports and studies. His research interests include electronic and electrical design and design for sustainability, and he led the design of the first custom commercial digital and research-oriented analog CMOS circuit in Serbia. He has also headed 8 strategic projects financed by the Serbian and Yugoslav governments and the JNA and has participated in several European projects funded by the governments of Germany, Austria, UK, and Spain, and the EC as well as the Black See Organization of Economic Cooperation (BSEC).

xv

1.1 Introduction

When one holds his mobile phone or is looking at the television set one sees an electronic device. If one opens the device, however, one will see a number of square shaped chips resembling centipede insects properly ordered on a board. What cannot be seen is the internal structure of the chips. So, here we are. It is our intention in this book to open to the reader the magic miniature world of electronics. We will show here what small means in terms of electronics. We will also show what clean means in terms of modern electronics. Consequently, the reader will understand why the most advanced civilization of the ancient world—the Egyptians—were not capable to do electronics. And not only them. The nineteenth century which is frequently referred to as the scientific one, and especially its second part including the beginning of the next one, was the period of human achievements in physics that fundamentally changed the understanding of nature. Giants such as Maxwell, Tesla, Rutherford, Einstein, and many others opened the secrets of physics to an extent that transformed the human society into one which became technology based. It took some time since the effects of their genius thoughts became transformed into devices and equipment changing our everyday life. That was probably because of the turbulent historical events in the first half of the twentieth century. Nevertheless, an explosion started after the WWII which is shaking the human society and bringing continuous progress ever since. The very revolution and bringing electronics into fore of the industrial development started with the discovery of the bipolar junction transistor (BJT) in 1948. That may be considered the first semiconductor electronic component. Namely, at the time diodes were in use but their function was passive meaning that, by their use, one can only rectify (transform into a direct current—DC) an alternating current (AC) signal. The transistor (which comes from trans-resistor) is an active component. Its property is to amplify a signal (being it DC or AC). In that, the BJT became an active component that in fact activated electronics. The development of electronics as a scientific discipline and as the industrial branch is the fastest in human history. We will demonstrate that in this book. © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 V. Litovski, Lecture Notes in Analog Electronics, Lecture Notes in Electrical Engineering 1002, https://doi.org/10.1007/978-981-19-9868-3_1

1

2

1.1 Introduction

Soon after the BJT the Junction Field Effect Transistor (JFET) was introduced. While, structurally, it is built of the same substructures as the BJT its functionality is fundamentally different. That was followed by the Metal Oxide Semiconductor (MOS) structure which first brought the MOS transistor named MOSFET and soon after, the Complementary MOS (CMOS) pair which is the ultimate achievement in signal processing and computer electronics nowadays. CMOS is one of the greatest discoveries human in history that influenced the life of everyone, literally. By the introduction of CMOS chips with billions of MOSFETs started to be produced. The research and development ran after many targets which we will try to shortly systematize in the sequel. Let us start with the materials. Modern electronics is a semiconductor one. Things started with germanium. Soon, however, silicon took over. The reason for that is its properties such as ease to mine, ease to extract from the ore, ease to build large crystals, excellent mechanical and thermal properties, high but not too high melting temperature, low conductivity when the pure, dramatic rise of the conductivity when impurity added, and what is specific “convenient value” of its energy gap. Of course, as we will see, there are many other candidates to replace it (attempts were done). Some compounds such a GaAs found their niches but generally speaking silicon is by far dominant. That does not mean that one may do electronic components using solely silicon. A large list of elements being around the silicon in Mendeleev’s table of elements found their use both as dopant (impurities) to the silicon and as compounds serving as an alternative to it. That means many rare elements are needed to produce electronic components which introduce technologies separating (extracting) them from the tailings left behind by the ore-processing of some materials (for example, copper). In addition, to make an electronic component, already on the silicon chip, one needs wiring which uses metals such as coper, aluminum, silver, or gold. Since coper is susceptible to corrosion and silver and gold are expensive, aluminum is dominant (not exclusive) for this purpose. To finalize, iron–nickel alloy (or copper) is needed to make the leads of the chip which are soldered to the printed circuit board. Also, the chip gets incapsulated which means plastic or ceramic housing is used. Altogether, one may conclude that from this point of view and, as we will see later, from general making components of view, the electronic industry is a chemical one. Here, however, comes the authors dilemma related to the ordering of the separate subjects in the book. Namely, the book is devoted to components and one is to discuss them first. That was done. The drawback of that is the reader’s lack of knowledge related to the technology which deeply influences the characteristics, the properties, and the parameters of the components. On the other side, if technology were to be discussed first, one would never understand the purpose, the influence, and the importance of so many of the operations included in the component making. So we think we chose the less damaging approach. The basic structure of any electronic component is the p-n junction. Starting with basic physics, we end with a full characterization of it. The mathematical expression relating the current (as a dependent variable) and the voltage (as the controlling

1.1 Introduction

3

variable) is developed and physical meaning to the parameters is given. That is referred to as a model of the p-n junction. Special attention is paid to the dynamic behavior of the p-n junction by thorough modeling of his capacitances. Based on that the semiconductor diode is introduced. Properties from an implementation point of view are discussed and practical values of the parameters including limitations of the implementation are given. Special attention is paid to the thermal and power dissipation aspects of the implementation. A wide family of diodes being specific by some of their property is described. One may say that the same for the diode is done for the BJT, the JFET the MOSFET, and the metal–semiconductor field effect transistor (MESFET). What is additional to the diode in the case of the transistors, their frequency domain behavior is discussed too. Two additional chapters make this book specific. First, the subject of optoelectronics is discussed leading to a series of optoelectronic components such as the photodiode, the solar cell, the light emitting diode (LED), the laser diode, and the opto-coupler (or optoisolator). All these are structurally and functionally described. Second, the subject of magnetoelectronics is visited so that the semiconductorbased magnetoelectronic components are also described structurally and functionally. That includes magnetoresistor, magnetodiode, magneto-BJT, magneto-MOS, and, of course, Hall sensor. Based on the content related to the components and using the literature added at the end of the book, we expect the reader to freely continue to dip him/herself into any specific subject of interest. To go back to the technology, the reader is advised to reread the part related to the components after reading the Appendix D where the technologies are studied. Hundreds (or even thousands) of technological operations are performed starting with raw silicon ore and ending with tested electronic components ready to be delivered to the market. To go deep into every one of them would be counterproductive at this level of study. So, here only the main actions and the results are discussed. Processes such as obtaining the pure crystal of silicon, transforming it into a Por N-type semiconductor, making p-n junctions, depositing thin layers over the semiconductor, implanting impurities, creating a connection between parts of the components and components themselves, protecting the semiconductor surface are described. The rationale for making integrated circuits are discussed and making components in so-called bipolar and MOS integrated circuit is described. Properties of such components are given. A separate attention is devoted to the so-called hybrid integrated circuits both thick-film and thin-film by partly describing the technology, component making and properties of the component discussing. There are three more appendices. In Appendix A, a set of solved problems is given. The intention is for the reader to revise his knowledge both by finding the right content of the theoretical part which is related to the problem at hand and to correctly implement the theory. The reader is urged to pay much attention to both the numerical values of the data in the problem and the numerical values of the results.

4

1.1 Introduction

Do try to solve a problem before looking to the solution given. Recapitulation at the end of studying a problem is strongly recommended. Problems related to most of the materials and components are given with special emphasis on diode circuits since DC analysis of circuits with transistors will be given in LNAE_Book 2. Chapter 1.12 is related to SPICE simulation examples. It is used here to demonstrate some analysis types and simulation results which are not readily possible by hand. Some new knowledge is extracted and offered to the reader here. Chatper 1.13 is related to component numbering in the marketing environment. Namely, every single component coming to the market has a tag explaining its properties. These tags are decoded here. That will help the reader to find his way through the infinite maze of offers and descriptions in the producer’s datasheets. To finish, we want to welcome the reader again and deliver the message that one never gets enough details. So, go for them.

1.2 Electric Current in Semiconductors

A pure material in a microelectronic sense of the word is the one in which the number of the impurity atoms is at least 1018 times smaller than the number of the atoms of the prime material.

1.2.1 Electronic Structure of the Isolated Atom The planetary model of the atom proposed by Rutherford in 1911, based on the classical principles of Newton’s mechanics, assumes that an atom consists of a nucleus containing protons and neutrons, and electrons orbiting the nucleus. Electrons are carriers of negative charge while the nucleus is positive (whatever that means). The charge of an electron is q = 1.062·10–19 C, and its mass mn = 9.107·10–31 kg. A proton is a carrier of the same charge as an electron, only of opposite sign (positive). The mass of a proton is 1845 times larger than the mass of an electron (mpr = 1.6726219·10–27 kg). The third particle is a neutron that is electrically neutral. The attractive force between the electron and the nucleus is balanced with the centrifugal force of electron rotation. The energy of an electron and the distance from the nucleus depend on its speed. Electron energy is often measured in electronvolts (eV). One electronvolt corresponds to an energy of 1.602·10–19 J. It is the energy that an electron obtains by crossing the path between two points with a potential difference of one volt. The term energy state of an electron, or abbreviated, state of an electron, refers to the energy of an electron. The set of all states of electrons in an atom is called the state of the atom. Not all phenomena in the matter can be explained by the planetary model of the atom. For example, if an electron moves around a nucleus in a circular path with frequency f , then it must emit energy in the form of electromagnetic waves of the same frequency. This means that it would lose energy, which would lead to its falling to the core. However, this is not happening. This and many other phenomena cannot be explained by the planetary model, which led to the modification of the model.

© The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 V. Litovski, Lecture Notes in Analog Electronics, Lecture Notes in Electrical Engineering 1002, https://doi.org/10.1007/978-981-19-9868-3_2

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6

1.2 Electric Current in Semiconductors

In 1913, Bohr laid down the basic laws that changed the notion of the atomic model. First of all, according to this theory, an electron cannot possess an arbitrary value of energy, as was the case in classical theory, but only certain, discrete energy states. When it is in a state (possessing energy) that corresponds to one of these discrete levels, the electron does not emit energy. This state is called stationary. Electron energy values corresponding to steady states (energy levels) vary from material to material but are all characterized by the fact that the angular momentum of the electron must be an integer multiple of h/(2π) where h is the Planck constant (h = 6.62·10–34 Js). In other words, if mn is the mass of the electron, v is its velocity, and r is the radius of the orbit, the angular momentum of the electron moving in the orbit is 2m n · v · r = n · h/(2π) n = 1, 2, 3, . . .

(1.2.1.1)

During the transition from a higher to a lower steady state, the electron emits energy in the form of radiation whose wavelength is λ = c · h/(E 2 − E 1 ),

(1.2.1.2)

where E 2 —original energy, E 1 —energy corresponding to the new state, and c— speed of light in vacuum (c = 2.998·108 m/s). This is illustrated in Fig. 1.2.1.1a. Theoretically, it is possible to calculate the energy state of the electrons of an atom of a certain element. This state can also be determined by the spectroscopic method, i.e., by measuring the radiation frequencies of the excited atom. Figure 1.2.1.1b shows the possible energy levels of electrons in a mercury vapor atom starting from the level corresponding to the normal energy of the unexcited atom to the energy corresponding to ionization. Some of the possible wavelengths of radiation are also given in m·10–10 . The zero-energy level is the one corresponding to the unexcited atom. This level is called the normal level. Other stationary states are called excited or critical levels. In order to possess these states, the electron needs to increase its energy. The change in energy levels is a consequence of the excitation of atoms. If one electron within an atom increases its energy, it moves away from the nucleus at the same time. When this energy becomes enough for him to move away so far that the nucleus no longer affects him, he becomes a free electron. This phenomenon is called ionization, and the energy required for this process is called ionization energy. For the electron of the mercury atom, it is 10.39 eV. For other elements, this energy spans from approximately 4 to 25 eV. The upper limit corresponds to inert gases, and the lower to alkali metals. A certain ionization electric potential (E/q) corresponds to the ionization energy. Excitation of an atom may be performed in several ways. One possible way is excitation by colliding with an external electron moving towards the atom. The collision can be inelastic and elastic. An elastic collision occurs when the kinetic energy of an electron is not sufficient to raise any of the atom’s electrons to a higher energy level. Such an electron cannot transfer energy to an atom. The consequence

1.2.1 Electronic Structure of the Isolated Atom

7

Fig. 1.2.1.1 a Emission of a photon after transition from higher to lower orbit and b Possible energy levels of the mercury atom electrons

of an elastic collision is a change in the direction of travel of the outer electron while its velocity remains the same. An inelastic collision occurs when the electron that excites the atom has sufficient kinetic energy. This energy should be so large that, when it collides with an electron from an atom, it can transfer that electron to a higher energy state. In this case, the atom absorbs part of the energy of the outer electron. After an inelastic collision, the outer electron changes the direction of its path and its velocity is reduced. Another possible way of excitation of atoms is the collision of atoms and photons. The term photon means the amount of radiation energy that is equal to the product of the Planck constant, h, and the frequency of radiation. In the collision of an atom and a photon, the energy of the photon will be absorbed only if the energy possessed by the photon is equal to the energy difference between the two possible states of the electron. The photon can either be totally absorbed or not absorbed at all. Other ways of excitation will be discussed later. From Fig. 1.2.1.1b it can be seen what energies are needed to bring the electron of a mercury atom to a higher state. In the new, excited state, the electron remains

8

1.2 Electric Current in Semiconductors

very shortly. This time is called the lifetime and spans from 10–7 to 10–10 s. Then the electron returns to its original energy state while emitting electromagnetic energy (in the form of a photon) equal to the energy difference between these two levels. There are energy levels in which the lifetime is much higher and spans from 10–2 to 10–4 s. They are called metastable levels. For mercury vapor electrons, the metastable states are 4.66 and 5.46 eV. Metastable states play a significant role in the ionization process. The relatively long lifetime of electrons in these states allows ionization to take place by means of two collisions of atoms with external electrons or photons. Thus, in the case of mercury vapor, it can happen that the electron, during the first excitation, passes to a metastable level, for example, of 5.46 eV, and there it waits for the second excitation, which adds an energy of 4.93 eV. Now the total energy increase is 10.39 eV, that is, ionization energy is brought to the electron in the atom. The electron is free, and ionization is performed in two steps, via a metastable state. Multi-step ionization is also possible for other energy levels but is much more probable for metastable levels. Quantum mechanics assumes a more complicated atomic structure than Bohr’s model of the atom. This was necessary to explain the details of the emitted spectrum of the excited atom. Thus, for example, in quantum mechanics, the state of an electron is described by the four quantum numbers n, l, me , and ms . The principal quantum number n characterizes the orbit of the electron, i.e., the possible energy of the electron in the corresponding orbit. Its values can be 1, 2, 3, … The quantum number of the angular orbital momentum (Azimuthal quantum number) l characterizes the shape and position of the orbit. Its value is limited by the basic quantum number and can be l = 0, 1, 2, …, n − 1. It is said that the azimuthal quantum number defines the sub-orbit. The magnetic quantum number describes the orientation of the orbit relative to the applied magnetic field. Its possible values are me = 0, ±1, ±2, … ±l. The spin quantum number ms characterizes the orientation of the spin axis of the electron relative to the magnetic field. Its possible values are ms = ±0.5. According to Pauli’s principle of exclusivity, in a system, there are no two electrons with the same set of quantum numbers. The set of quantum numbers means the set of all four quantum numbers that define the quantum state. In other words, this means that there are no two electrons with the same quantum state in one system. The structure of atoms can also be determined using quantum numbers. The principal quantum number determines the position of the orbit of the electron or the electron shell. It is possible that several electrons have the same principal quantum number, i.e., they belong to the same shell. The shells are denoted by the letters K, L, M, N, O, P, Q which correspond to the principal quantum numbers n = 1, 2, 3, 4, 5, 6, and 7. For example, the shell K can be occupied by two electrons. According to the previous explanation these electrons will have l = 0 and me = 0. One of them will have ms = 0.5 and the other ms = −0.5. There can be 8 electrons in the L shell. Because, if n = 2, then l will be 0 or 1. For l = 0 there must be me = 0, and ms = ± 0.5. For l = 1, me can be 0 and ± 1 and ms = ± 0.5. Taking all possible combinations, one may conclude that there are

1.2.2 Electronic Structure of the System of Atoms Table 1.2.1.1 Electronic configuration of atoms of some elements

9

Element

Configuration

C

1s2 2s2 2p2

Si

1s2 2s2 2p6 3s2 3p2

Ge

1s2 2s2 2p6 3s2 3p6 3d 10 4s2 4p2

eight of them. In a similar way, we may conclude that in the shell M there can be 18 electrons, and in the shell N, 32, etc. If all the states in one shell are occupied that shell is filled. The azimuthal quantum number is often marked with letters, too. Thus l = 0, 1, 2, 3, 4, 5 and 6 correspond to the letters s, p, d, f , g, h, and i, respectively. In order to denote the state of the excited atom, the basic quantum number n and the azimuthal quantum number l are used, so an abbreviated notation is formed. Thus, for example, an atom with one shell and two electrons in it is denoted by 1s2 . For an atom whose second shell is also filled, we write 1s2 2s2 2p6 , which means that there are 2s electrons in the first shell, 2s and 6p electrons in the second. Table 1.2.1.1 contains the electronic configurations (electronic structures) of carbon, silicon, and germanium.

1.2.2 Electronic Structure of the System of Atoms An atomic system is a set of atoms that act on each other. Most often, this set is arranged in such a way that the atoms are spatially arranged in the vertices of regular geometric bodies. Bodies with this arrangement of atoms are called crystals. Atoms in a crystal are located at distances of several angstroms so that they affect each other, which results in a modification of the energy structure of atoms. If two atoms are far enough apart they do not affect each other and form two independent systems. Electrons with the same quantum numbers can exist in these two systems. As these two atoms get closer, they affect each other. The distance at which the interaction occurs is an order of magnitude larger than the dimensions of the atoms in the crystal lattice. Two atoms acting on each other are no longer independent systems. Now they form a single system. According to Pauli’s principle of exclusivity, electrons with the same quantum state can no longer exist. It has been experimentally and theoretically proven that in this system there is a shift in the energy levels of electrons. Thus, instead of one energy level, which was the same for both electrons when they belonged to two systems, now there are two energy levels that are very close to each other. This phenomenon is called splitting of energy levels. If a third atom is included in the system, each energy level will split into three new levels. In a solid body, the density of atoms can be of the order of 1029 atoms per cubic meter. This means that each energy level has broken down into “countless” new energy levels. The system now consists of sets of energy levels grouped around

10

1.2 Electric Current in Semiconductors

one energy level corresponding to a lone atom. In each set of levels, the individual energy levels are very close to each other. This phenomenon can be more easily interpreted with the assumption that the set of energy levels is a continuous energy band (a large number of individual levels that are slightly apart from each other) of possible energies. This band is in the vicinity of one energy level of an isolated atom. There are as many of these bands as there were original individual energy levels in isolated atoms. The electrons of the atomic system can possess energy within these bands. The bands are separated by energy gaps. The states corresponding to the energy gap cannot be possessed by any electron. That is why energy gaps are often called forbidden bands or zones. To clarify this phenomenon, let us look at an example of the silicon crystal. Silicon has 14 electrons, and its atom is characterized by the configuration 1s2 2s2 2p6 3s2 3p2 . Of particular interest is the outer shell because the electrons belonging to it participate in the process of conducting electricity. In the third shell it is possible to have two s electrons, six p electrons, and ten d electrons. However, in the case of silicon atoms, there are no d electrons. The subshell s is filled, and the subshell p has only two electrons, which means that four are missing. These are four vacancies that can be filled. In N isolated silicon atoms, there will be a total of N·2 s electrons and N·2 p electrons in the outer shell. Let these N atoms of silicon now come together to form a system—a single crystal of silicon. The process is illustrated in Fig. 1.2.2.1 where the s and p energy states of electrons in the outer shell of silicon atoms are shown, as well as the splitting of these states into bands. Up to some mutual distance here denoted as d 3 the atoms form independent systems with two energy states of electrons in the outer shell s and p. These two states are separated by an energy gap. This means that if an electron were to move from state s to state p, it would need to increase its energy by an amount equal to the energy gap. Sufficient approaching of the electrons leads to their interaction. The states s and p split into new states, which are all the more numerous if there are more atoms entering the system. However, this leads to a reduction in the energy gap. At some Fig. 1.2.2.1 Splitting of energy states in the lattice of a silicon crystal

1.2.2 Electronic Structure of the System of Atoms

11

atom distance (d 2 ) the energy gap disappears. From that distance, the s and p bands were lost and merged into one band. There are no longer s and p electrons of an isolated atom, but electrons in the outer shell of the system. They can change cores by moving from one core to another. We say that all the electrons in the outer shell are free. With further approach of the atoms, after some distance d 1 , the unique energy band splits again into two new bands, but on a different way. There are no more s and p electrons. Each of these two bands has 4·N possible states. In a silicon crystal at the temperature of absolute zero (T = 0 K) all 4·N electrons will be in the lower band called the valence band. The upper, conductive band is empty. The new situation persists with the further approach of the atom. The distance d 0 in Fig. 1.2.2.1 corresponds to the actual distance in the crystal, at that distance the valence and conduction bands are separated by an energy gap of size E g . If the temperature of the crystal increases, electrons can be excited. Thus, it is possible for an electron to move from the valence band to the conduction band. The energy gap E g determines the average number of electrons that can pass from the valence to the conduction band at a given temperature. The size of the energy gap is different for different materials and it determines the conductive properties of the material. In Fig. 1.2.2.2 three typical structures of energy bands in crystals are shown. In the former the distance between the atoms in the crystal lattice is small (Fig. 1.2.2.2a), in the next it is large (Fig. 1.2.2.2b), and in the latter it is between these two (Fig. 1.2.2.2c). It should be mentioned here that the abscissa does not make physical sense; the diagram is two-dimensional only for the sake of clarity. In Fig. 1.2.2.2a the energy gap Eg is significant and amounts to more than 3 eV. For example, for a diamond it is 6 eV. This means that a lot of energy is needed to transfer an electron from the valence band to the conductive one. Even at high temperatures, near the melting point, these materials have very few electrons in the conduction band. These materials are called insulators. In Fig. 1.2.2.2b there is no energy gap. The valence and conduction bands overlap. Most metals are characterized by this structure of energy bands. All electrons from the outer shell can participate in the mechanism of conducting electric current. These materials are called conductors.

Fig. 1.2.2.2 Structure of energy bands of a insulators, b conductors, and c semiconductors

12

1.2 Electric Current in Semiconductors

Materials with a small energy gap (less than 3 eV) are called semiconductors. They are of the greatest interest in modern electronics and will be given special attention. Since the energy required for the excitation of atoms is relatively small, at room temperature, there are electrons in the conduction band, so they are available to conduct electricity. Their number is relatively small (compared to the number of free electrons in conductors) and therefore these materials are called semiconductors. Their energy band structure corresponds to Fig. 1.2.2.2c. Semiconductors can be pure elements such as germanium (Ge) or the most widely used element in electronics today—silicon (Si), however, the properties of a semiconductor have a number of compounds. These are III–V compounds, which means that only elements of the third and fifth groups of the periodic table (GaAs, GaN, GaSb, GaP, InSb, InAs) are used, and II–VI compounds where only elements of the second and sixth groups of the periodic table (CdTe, CdS, CdSe, PbS, PbTe, PbSe, ZnS, and ZnSe) are in use. Note, an IV–IV compound is frequently and successfully in use nowadays. It is SiC. Recently, more complex compounds such as Alx Ga1-x As, Hg1-x Cdx Te, or Cdx Zn1-x S have been used. In the last formulas 0 < x < 1 denotes which part (percentage multiplied by 100) belongs to a given material. By changing the value of x, the properties of the material are controlled, and above all, the energy gap. To help you find your way around, Table 1.2.2.1 provides an excerpt from the Periodic table of the elements that is relevant. Table 1.2.2.2 gives the most important properties (from the point of view of electronics) of some of the most commonly used materials. Some of these features will be discussed in the following text. It can happen that the size of the energy gap spans from 0.18 eV for InSb, over 0.67 eV for Ge and 1.1 eV for Si, to 1.4 eV for GaAs and 3.5 eV for GaN. The stated values of the energy gap apply to room temperature. Namely, the size of the energy gap is a function of temperature. The reason for this is the dilatation of the material, which in fact means that with the increase in temperature, the constant of the crystal lattice (i.e., the distance between atoms) increases. The greater the distance between the atoms, as can be concluded from Fig. 1.2.2.1 (looking from d 0 to the right) means a smaller width of the energy gap. Table 1.2.2.1 Excerpt from Mendeleev’s periodic table of the elements Group III

Group IV

Group V

5B Boron

6C Carbon

7N Nitrogen

13 Al Aluminum

14 Si Silicon

15 P Phosphorus

16 S Sulfur

30 Zn Zink

31 Ga Gallium

32 Ge Germanium

33 As Arsenic

34 Se Selene

48 Cd Cadmium

49 In Indium

50 Sn Tin

51 Sb Antimony

52 Te Tellurium

Group II

Group VI

1.2.2 Electronic Structure of the System of Atoms

13

Table 1.2.2.2 Properties of some semiconductor materials (T = 300 K) Property

Si

Ge

GaAs

InAs

GaP

Atomic (molecular) mass

28.09

72.6

140.6

236.6

100.7

Atom density (molecules/1022 ·cm3 )

5

4.4

2.21

2.9

4.49

4.37

0.566

0.565

0.648

0.545

0.32

Crystal lattice constant 0.543 (nm)

GaN

4H-SiC 40.1

0.31

Density (g/cm3 )

2.33

5.32

5.32

5.79

4.13

6.1

3.21

Melting point (°C)

1415

937

1238

525

1470

1600

2800

Energy gap (eV)

1.11

0.67

1.4

0.18

2.26

3.5

3.26

Dir.

Gap type

Indir.

Indir.

Dir.

Dir.

Indir.

N c (1019 ·cm−3 )

2.8

1.04

4.7

–

1.7

Nv (1019 ·cm−3 )

1.04

6.0

0.7

–

2.25

1.5·1010

2.5·1013

9.0·106

1016

11.8

16

12.5

15.9

ni

(cm−3 )

Relative dielectric constanta

Indir. 1.8 2.1

8

10–10

10–4

10.2

9.5

10

μn (cm2 /Vs)

1350

3900

8500

80 000

300

2000

900

μp (cm2 /Vs)

600

1900

400

1250

150

850

115

K c (kV/cm)

300

100

400

2·103

2.2·103

T max (°C)

200

100

0 (W/(cm·K))

1.5

0.58

0.52

vsat (107 ·cm/s)

1

3.1

1

a

1.1

400–900

900

1.3

4.9

2.5

2

ε = εr ·ε0 , where ε0 = 8.85·10–14 F/cm

The following approximate formula applies to silicon: E g (T ) = 1.21 − 3.6 · 10−4 · T (eV)

(1.2.2.1a)

which means that for T = 0 the value of E g for silicon is equal to 1.21 eV. For the materials with higher energy gap (e.g., GaAs, GaN, and 4H-SiC) we use E g (eV) = E g (0) −

γ · T2 , T +β

(1.2.2.1b)

which for GaAs (according to Table 1.2.2.3) becomes E g (T ) = 1.519 − 5.405 · 10−4 · T 2 /(T + 204).

(1.2.2.1c)

At first glance, the change in the value of the energy gap (for silicon, from 1.21 eV for T = 0 K, to 1.1 eV for T = 300 K) is not significant (less than 10%). This change, however, significantly affects the change in the electrical properties of the material.

14 Table 1.2.2.3 Parameters in the temperature dependence model of E g

1.2 Electric Current in Semiconductors Material

E g (0) (eV)

γ

β (K) 772

GaN

3.396

9.39·10–4

4H-SiC

3.285

3.5·10–4

1100

GaAs

1.519

5.405·10−4

204

Therefore, there are significant differences in the electrical properties of materials with different energy gaps. The overall picture of the changes in the energy structure of the material as compared to the lone atom is not complete by generating the diagram of Fig. 1.2.2.1. We will now consider some other aspects of the grouping of atoms. First, the potential distribution in the atom, i.e., in the material, will be considered. Figure 1.2.2.3 shows the potential distribution in a lone atom (left). The ionization level was taken as the level of zero potential. Horizontal lines symbolically represent the corresponding energy levels related to the main quantum numbers. The abscissa is not usually shown here, but it should be borne in mind that the diagram represents the dependence of the potential on the distance from the atoms core. The example refers to silicon having three electron shells, according to Table 1.2.1.2. Figure 1.2.2.3 (right) shows a simplified picture of the distribution of potentials in a material whose thickness is only four atoms. It should be noted that the level corresponding to the outer shell (n = 3) is splitted into four levels (other dimensions of the material are neglected) since it has four atoms. The interaction of atoms is not pronounced for the lower shells. Similar changes occur in the potential distribution. Up to the levels corresponding to n = 3, the potential distribution does not change, and for higher levels there is a change according to the figure. The potential distribution of an atom overlaps with the one of the neighboring one. Electrons located at the potential corresponding to levels up to n = 3 are in a non-uniform electric field which, for a perfect crystal has periodic nature in space. Two important results can be drawn from this diagram. First, there is a large potential gradient on the outside edge of the material, which means a corresponding

Fig. 1.2.2.3 Simplified picture of potential distribution in material for the lone atom (on the left) and for a system of atoms (on the right)

1.2.3 Electric Current in Semiconductors

15

electric field. Therefore, free electrons cannot leave the material without exceptional excitation. Second, if a constant external electric field is brought into the material, the excited electrons, being unrelated to specific atoms, will be triggered. Since they move through a non-uniform electric field, however, their movement will not be uniformly accelerated, but the speed will vary according to the actions of the external field and the internal distribution of potential. The influence of the material itself on the motion of the electron is usually considered by introducing the effective mass (m*e ) instead of the mass of the free electron (m0 ) in vacuum. The effective mass is larger than the free electron mass. In this way, the interior of the material is reduced to a vacuum and the movement of electrons under the influence of a constant electric field is considered to be uniformly accelerated. As is known from quantum mechanics, for the complete characterization of an electron it is necessary to know its momentum (p = m·v). When representing the properties of a material, this quantity is usually expressed in relation to the energy of the electron. This is how the dependence of energy on the impulse, for a given crystallographic plane, arises. Usually, of course, not the dependence of any energy is given, but the characteristic ones, which are the energies of the lower limit of the conduction band E c and the energy of the upper limit of the valence band E v . These diagrams, for the three most widely used materials, are shown in Fig. 1.2.2.4 for room temperature, in simplified form. A quasi-momentum (k) is plotted on the abscissa, which is related to the electron momentum as p = h·k/(2π). k has the dimension of the reciprocal value of the length. It should be noted that k for the crystallographic plane [100] is applied to the positive half-axis while to the negative half-axis it is applied to the crystallographic plane [111]. Based on these images, it can be seen that in the case of germanium and silicon, the smallest minimum of the conduction band and the maximum of the valence band do not occur at the zero value of the impulse, which means that ionization changes not only the energy of the electron, but also its impulse. Such energy gaps are called indirect. In the case of gallium arsenide, the places of the maximum of the upper limit of the valence band and the minimum of the lower limit of the conduction band coincide. This is a direct energy gap. The existence of a second minimum, which is not much higher than the lowest, as we will see later, also affects the properties of GaAs. Finally, we mention that the crystal lattice constant “a” in Fig. 1.2.2.4 is of the order of nm so that the values of the impulses corresponding to the electron velocities are plotted on the abscissa.

1.2.3 Electric Current in Semiconductors Typical semiconductor materials, such as silicon and germanium, form a crystal lattice shaped as in Fig. 1.2.3.1.

16

1.2 Electric Current in Semiconductors

Fig. 1.2.2.4 Energy bands in the moment-space for a Ge, b Si, and c GaAs. “a” is the constant of the crystal lattice

Fig. 1.2.3.1 Semiconductor (diamond) crystal structure

This is the so-called “diamond” structure that can be described as two mutually coupled cubes. Each of them has one atom on each vertex and one atom in the middle of each side surface. If the first cube has a vertex with coordinates (0,0,0), then the corresponding vertex of the second cube will have coordinates (a/4, a/4, a/4). In Fig. 1.2.3.1 only a part of the second cube is shown (see Table 1.2.3.1). As a result, each silicon atom is located in the center of the tetrahedron surrounded by four silicon atoms. Most III–V compounds crystallize in the form of so-called “zinc blend” structures. This structure is very similar to diamond. In fact, it is a diamond structure, with one of the mentioned cubes being atoms of an element from group III (for example Ga) and the other atoms of an element from group V (for example, As).

0.1

2,500

0.67

Ge

3,300

m

( MV )

10–10

Kc

3.5

GaN

(1010 · 300

K

3,500

ni |T=300 cm−3 )

1.45

(eV)

10–4

1.12

3.26

4H-SiC

|T=300 K

Si

Eg

Material

Table 1.2.3.1 Basic properties of selected semiconductor materials

937

400–900

600

200

T max (°C)

( W cm·K

0.64

1.3

4.9

1.5

0

)

(

cm2 V ·s

3,900

2,000

900

1,450

μn

)

0.8

2.5

2

1

vsat (107 ·m/s)

1.2.3 Electric Current in Semiconductors 17

18

1.2 Electric Current in Semiconductors

Table 1.2.3.2 Part (repeated) of the periodic table of elements 5 B

6 C

7 N

13 Al

14 Si

15 P

16 S

39 Zn

31 Ga

32 Ge

33 As

34 Se

48 Cd

49 In

50 Sn

51 SB

52 Te

In this way, each atom of group III is located in the center of the tetrahedron whose vertices are the elements of group V, and each atom of group V is located in the center of the tetrahedron whose vertices are atoms of group III. A special feature of this structure is that elements from the corresponding group can be mixed separately in each cube (cell). Thus, for example, if Al and Ga are mixed in a cube with trivalent elements, Alx Ga1-x As can be formed. A combination of Inx Ga1-x Asy P1-y is also possible, where in the first cube (III) In and Ga are mixed, while in the second (V) As and P. Of course, 0 < y < 1. To facilitate the reading we repeat the part of the Periodic table in Table 1.2.3.2. A pure semiconductor (Si) without chemical impurities and with a perfect crystal structure will be considered first. This means that the material is absolutely clean, that all places in the crystal lattice are filled and that all distances are according to the stated rules. The conclusions to be drawn apply mainly to all semiconductor materials. Any deviations will be indicated separately. As mentioned earlier, the upper shell of the silicon atom has some possible states, of which only four are filled with electrons. At the temperature of absolute zero, all electrons are in the valence band. The conduction band is empty. Each silicon atom is connected to four adjacent atoms in the crystal lattice via its four electrons in the outer shell. In this way, every two adjacent atoms have two common electrons. This connection is called covalent and is shown in Fig. 1.2.3.2 for a silicon crystal. This is the usual way of representing the three-dimensional structure of crystals in two-dimensional form. Each atom of silicon now has eight electrons in its outer shell. There was no need to shift the charge in the crystal. In complex semiconductors, such as GaAs, however, the internal bond in the crystal is partially ionic, since the As atom is more electronegative than the Ga atom, so the electron cloud moves towards it. There is now more negative charge in the vicinity of the As atom, while the environment of the Ga atom is more positive. As a result of the transfer of charge, when an outside electric field is connected, this semiconductor becomes polarized, which is important when high-energy charge carriers move through the material. Let us now consider the possibility that there are free charge carriers in a semiconductor. At very low temperatures, such material should be expected to function as an insulator, since there are no sources that would communicate the energy required for ionization to the electrons in the outer shell of the silicon atom. This energy can be transmitted, as already mentioned, by a photon coming from outside if there is a

1.2.3 Electric Current in Semiconductors

19

Fig. 1.2.3.2 Two-dimensional representation of silicon crystals

light beam falling on a semiconductor or thermal vibrations of atoms in the crystal lattice around their own positions, i.e., mechanical vibrations. The quantum of energy obtained by vibrating the crystal lattice by analogy with electromagnetic waves is called a phonon and is a measure of the temperature. The mean value of thermal energy that can be communicated to the electron is relatively small—of the order of kT, where k is the Boltzmann constant (k = 1.38·10–23 J/K or k = 8.61·10–5 eV/K). At room temperatures (T = 300 K) this energy is only 0.026 eV, which is significantly less than the energy gap of Si. However, this does not mean that all the electrons in the outer shell have the mentioned energy. The energy distribution of an electron is a statistical quantity, so there is a small probability that an electron will accumulate energy greater than the energy gap. Although the probability is small, given the number of electrons in the valence band (about 1023 cm−3 ), we can conclude that the number of such electrons will not be negligibly small even at room temperature and can be expected to increase with increasing temperature. The process of formation of free electrons in a semiconductor is called generation. The rate of generation g (cm−3 s−1 ) is expressed by the number of new electrons per unit volume per unit time. The number of free electrons in a unit of volume is called the concentration and is denoted by n (cm−3 ). Therefore, the rate of generation is in fact the rate of change of concentration due to generation. It is important to note that the rate of generation, when there are no external causes, is a function of temperature only and not of concentration.

20

1.2 Electric Current in Semiconductors

Fig. 1.2.3.3 Movement of electrons and holes through the crystal

When an electron breaks a covalent bond and leaves an atom, one unfilled covalent bond remains in the atom. It can move through the crystal in the following way. An unfilled covalent bond is filled by taking one of the (free) valence electrons of neighboring atoms. Now, in a new place in the crystal, an unfilled covalent bond is being formed. The process continues and is equivalent to the movement of incomplete covalent bonds through the crystal. Such an unfilled covalent bond is called a hole. The movement of the hole is, in essence, the movement of more electrons. However, as the atom in which the covalent bond is broken has remained positively charged, the whole process can be represented as the movement of a positive charge through the crystal. This process is illustrated in Fig. 1.2.3.3. Therefore, the hole is also a free carrier of electricity and participates in the process of current conduction under the influence of an external electric field. The charge of the hole is positive and, in absolute value, equal to the charge of the electron. A certain mass that is close to the mass of the electron but different (larger) from it, is also attributed to the hole. The process of creating new electrons is accompanied by the process of creating holes. This is shown in Fig. 1.2.3.4 on the energy diagram of a semiconductor. In the diagram, E c indicates the lower limit of the conduction band, and E v denotes the upper limit of the valence band. In a pure semiconductor, the number of free electrons is equal to the number of holes (the holes are always free) because each electron, breaking the covalent bond and becoming free, leaves a hole behind. If the number of free electrons in a unit of volume (concentration of electrons) is denoted by n, and the number (concentration) of holes by p then it will be valid n i = pi , Fig. 1.2.3.4 Electrons in the conduction band and holes in the valence band

(1.2.3.1)

1.2.3 Electric Current in Semiconductors

21

where the index i (i = intrinsic = own) is used to denote the concentration of free carriers in a pure semiconductor. The breaking of a covalent bond is accompanied by the opposite process—their creation. Free electrons “meet” holes on the way through the crystal, lose energy and move from the conduction band to the valence band. This phenomenon is called recombination. The recombination rate represents the number of newly formed covalent bonds (number of recombined electrons) per unit volume in a unit of time and is denoted by r. The time between generation and recombination is called the lifetime (of electrons or holes). At a certain temperature, an equilibrium is established between the number of broken and newly formed covalent bonds due to thermal excitation. This means that the rate of generation is equal to the rate of recombination. These two quantities can be different, however. An example of such a situation is when we illuminate a semiconductor and establish equilibrium (r = g), and then abruptly turn off the light. The rate of generation drops sharply to the value determined by thermal excitation, and the rate of recombination decreases slowly since, when it was light, we had a much higher concentration which should now fall to the value determined by thermal excitation. Therefore, the rate of generation is only a function of external excitation (temperature, lighting, etc.), and the rate of recombination depends also on the concentration of free carriers. The recombination process itself, however, is not so simple and an attempt will be made here to present it in an acceptably simple form. To do this, let us first consider the notion of a defect of the crystal lattice. So far, a semiconductor has been observed under the assumption that it is a perfect crystal structure. This is not the actual case and, as has been said, there may be a vacancy in the lattice, an atom may be displaced, or a foreign atom (undesirable material) may be found in the location where Si is supposed to be. This phenomenon is called a crystal lattice defect. The defect of the crystal lattice creates a new energy level in the energy gap that affects the recombination process by increasing the probability of recombination and is therefore called the recombination center. It is not difficult to conclude that the presence of such centers on the surface of the crystal is more probable. Figure 1.2.3.5 shows the energy gap of silicon and indicates the values of distances (in eV) from the limits of the energy gap to the level that was generated by an impurity. For example, from this picture we can see that the gold atom generates an energy level that is 0.29 eV away from E v . The letter D, in Fig. 1.2.3.5, denotes atoms that generate a level above the Fermi level (to be introduced soon), and the letter A denotes atoms that generate a level below the Fermi level. Let us now consider the E-k dependence of Fig. 1.2.2.4a, b. We notice that the minimum of the conduction band, in k-space, is far from the maximum of the valence band. This means that in Ge and Si the electron also has a large momentum (velocity) which must be maintained during recombination (law of conservation of momentum). Therefore, for the recombination to happen, the electron is first “caught” in the recombination center and only then it can be recombined, gradually transferring the excess energy and momentum to the phonons, i.e., heating the crystal. This is an essential feature of recombination in these materials. Materials with this property are called materials with an indirect energy gap. In this case, the lifetime of free

22

1.2 Electric Current in Semiconductors

Fig. 1.2.3.5 The energy gap and the impurity levels

carriers depends on the concentration of “traps”. Its value can be several ms for Ge while for Si it can reach 100 μs and more. The E-k dependence for GaAs (Fig. 1.2.2.4c) suggests that here the minimum of the conduction band and the maximum of the valence band coincide so that the moment of the carrier is equal to zero. So, the recombination is performed in one step at which emits a photon whose frequency sometimes belongs to the visible spectrum. Such materials are called materials with a direct energy gap. The lifetime of free carriers is much shorter here and is of the order of ns or less. Sometimes, due to the specific shape of the E-k diagram, recombination can be achieved by simultaneously emitting both photons and phonons, which corresponds to GaP, which has an indirect energy gap. In this case, the emitted phonon accepts the momentum, and the emitted photon emits the energy which belongs to the visible, red, part of the light spectrum. These specifics of the recombination affects the application of a semiconductor material: low-frequency or high-frequency components, light sources, detectors, etc.

1.2.3.1 P- and N-Type Semiconductors As we have seen so far, the number of available carriers in a semiconductor is determined by the temperature. Such material is not suitable for use in electronic components. It is desirable that the number of carriers to be determined by the needs of the user and to be independent of temperature. In a semiconductor that (mostly) satisfies these requirements, one type of free charge carrier is significantly more numerous than another. It is produced by controlled addition of other elements to the semiconductor. The process of adding other elements is called doping, and the element that is added is called dopant. The element which is added is also said to be an impurity, and a semiconductor that has impurities is also called an impurity semiconductor (not pure). The amount of dopant is very small compared to the basic semiconductor. The typical ratio of the number of Si atoms to the number of impurities is 106 :1 which

1.2.3 Electric Current in Semiconductors

23

means that the impurity concentration will be about 1016 cm−3 . Usually, the impurity atoms are of similar dimensions as the atoms of the basic semiconductor in order to preserve order in the crystal lattice. If we start from that, the volume of dopant (before dissolving in a semiconductor) is 106 times smaller than the semiconductor itself: to 1 dm3 (i.e., one liter) of silicon it goes 1 mm3 of dopant. Due to this relationship, it is understandable that each impurity atom is surrounded by a very large number of silicon atoms, so it is very distant from other atoms of the same type. Chemical impurities added to Si and Ge are characterized by belonging to either group III or V of the periodic table. In the case of complex III–V materials, dopants are from groups II and VI, for example (Cd and Te). Let us now consider what happens to a semiconductor when chemical impurities are added in a controlled manner. Let the silicon crystal contain pentavalent atoms of chemical impurities, such as phosphorus. Phosphorus has five valence electrons in the outer shell. Four electrons bind covalently to silicon atoms. The fifth electron has no atom to connect with. With very little thermal excitation, this electron becomes free. However, no hole was formed during this process. It is true that the phosphorus atom is positively charged, but since it is covalently bound to four electrons in the crystal lattice, it is an immobile positive ion and cannot participate in the process of conducting current. Figure 1.2.3.6 illustrates a silicon crystal with a pentavalent phosphorus atom in the lattice which resulted in the formation of a free electron and a positive ion. Chemical impurities with five valence electrons are called donors because they hand over one free electron to the semiconductor. Figure 1.2.3.7 shows the energy diagram of a semiconductor with pentavalent chemical impurity. Donor atoms bring

Fig. 1.2.3.6 Pentavalent phosphorus atom in the crystal lattice of silicon

24

1.2 Electric Current in Semiconductors

Fig. 1.2.3.7 Conduction and valence bands with the energy level of the donor atom

in one extra energy level. More precisely, this should, according to previous presentations, be a band. However, due to the low concentration, the donor atoms are at large distances and there is little mutual influence between them. Therefore, it can be said with sufficient accuracy that this is an additional level (not band). The energy level introduced by the donor atom is quite close to the conduction band (about 0.03– 0.07 eV, as shown in Fig. 1.2.3.5). Therefore, already at temperatures higher than T min = 100 K, almost all electrons from this level pass into the conduction band and become free. Below T min , the semiconductor practically behaves as pure (intrinsic). Here is an explanation of this phenomenon. In essence, the lone phosphorus atom acts as a hydrogen nucleus relative to the fifth electron. The fifth electron revolves around its nucleus in the potential field of silicon (therefore, the effective mass greater than the mass of the free electron should be considered), where the relative dielectric constant is εr = 12 and so many times is smaller the mutual electrostatic attraction. Therefore, the radius of the path of such an electron is incomparably larger than the radius of the atom of a hydrogen atom, and the ionization energy is incomparably smaller (of the order of kT ). Thus, now the number of free carriers is increased in relation to the state in pure semiconductor. The increase is significant because all the donor atoms gave one free electron, which, as we will see later, is much more than ni . As the number of free electrons increases, the probability of their recombination increases. Due to the more intensive recombination, the number of holes is smaller compared to the state that would be present in a pure semiconductor. This, true, also reduces the number of free electrons, but the relative reduction of the number of electrons is far less than the relative reduction in the number of holes due to the far higher concentration of free electrons. A semiconductor in which the number of free electrons is far larger than the number of holes is called an N-type semiconductor. In N-type semiconductors, electrons are the majority (main) carriers of electricity, and holes are the minority (secondary). If n and p denote the concentrations of free electrons and holes, respectively, for N-type semiconductors is n > pi

(1.2.3.2)

where ni and pi are the intrinsic concentrations of electrons and holes, respectively.

1.2.3 Electric Current in Semiconductors

25

The opposite process will take place if trivalent chemical impurities, such as boron, are added to the semiconductor. Figure 1.2.3.8 shows a crystal lattice of a semiconductor with a trivalent boron atom embedded in it. Boron has three electrons in its outer shell. These three electrons are built into covalent bonds. One covalent bond, due to the lack of electrons, cannot be realized and a hole remains in that place. This covalent bond is filled by an electron of another atom of silicon which represents the motion of the hole. After that, an immobile negative ion remains in the place of the trivalent boron atom. The number of holes becomes far larger than the number of electrons. Similar to previous explanations, due to increased recombination, the number of electrons is now smaller than it would be in a pure semiconductor. Chemical impurities that increase the number of holes are called acceptors. Figure 1.2.3.9 shows the energy diagram of a semiconductor with trivalent chemical impurities.

Fig. 1.2.3.8 A trivalent boron atom in the crystal lattice of a semiconductor

Fig. 1.2.3.9 Conduction and valence bands with the energy level of the acceptor atom

26

1.2 Electric Current in Semiconductors

The energy level introduced by the acceptor atoms is close to the valence band at a distance of about 0.03–0.16 eV. Therefore, at temperatures higher than T min = 100 K, this level is filled with electrons that have crossed the valence band. It is understood that this refers to the energy level of the acceptor atoms, and not to the band, because it is considered that the mutual distances of the acceptor atoms are large and there is no splitting of the levels to a band. A semiconductor in which the number of holes is significantly larger than the number of electrons is called a P-type semiconductor. In P-type semiconductors, holes are the majority (main) carriers of electricity, and electrons are the minority (secondary). For P-type semiconductors it is: n >> n i p E f . The maximum energy that an electron can have at this temperature is equal to the Fermi level. The probability that an electron has less energy is equal to one, which means that all states are possessed, and the probability that an electron has more energy is equal to zero, which means there are no such electrons. For T = 0 K, it is valid: f (E f ) = 1/2.

(1.2.3.5)

1.2.3 Electric Current in Semiconductors

27

Fig. 1.2.3.10 Fermi–Dirac distribution function

In most cases, the energy levels corresponding to the Fermi level are located in the middle of the energy gap between the valence and conduction bands. Since we have determined the probability that an electron at temperature T has energy E, we can proceed to find the number of free electrons whose energy belongs to an arbitrarily chosen range of energies between E 1 and E 2 . In order to determine this, the number of possible states of electrons in a unit of volume per unit of energy, i.e., the function of the density of the states d s (E), must be known. In the literature, through a more detailed analysis, it is shown that the density of states function is given by ) ( electrons 4π 3 1/2 , ds (E) = 3 (2m n ) 2 E h eV · m3

(1.2.3.6)

where E is energy in eV, and mn the mass of the electron. This relation can be written in the form ds (E) = γE1/2 ,

(1.2.3.7)

γ = 4π · (2m n )3/2 · h −3 .

(1.2.3.8)

where γ is a constant given by

In order to determine the number of free electrons whose energy is between E 1 and E 2 , we must first multiply the function of the probability that the states are possessed (Eq. (1.2.3.4)) and the function of the density of the states. Thus, the electron energy distribution function ρ (E) is obtained, which gives the number of electrons in a unit of volume (m3 ) per unit of energy. ρ(E) =

γE 1/2 dn = . dE 1 + e(E−Ef )/(kT )

(1.2.3.9)

Thus, finally, the mean value of the number of electrons having energy between E 1 and E 2 is obtained as

28

1.2 Electric Current in Semiconductors

{E2 n E1 ,E2 = E1

) ( γE 1/2 electrons . · dE 1 + e(E−Ef )/(kT ) m3

(1.2.3.10)

For example, the total number of free electrons per unit volume at absolute zero temperature (T = 0 K) will be determined now. It is {E f n=

γE 1/2 dE =

2 3/2 γE . 3 f

(1.2.3.11)

0

In order to determine the density of free electricity carriers in the case of semiconductors, it is necessary to know the density of permissible energy states in the conduction band. For the case of metals, the density of permissible energy states is given by (1.2.3.6). In order for this equation to apply to semiconductors as well, the fact must be considered that the density of states in semiconductors becomes equal to zero at the lower limit of the conduction band. This did not apply to metals because the conduction and valence bands overlapped and there was no limit for E. Therefore, in the case of a semiconductor, when calculating the number of free electrons, in Eq. (1.2.3.6), E − E c should be placed instead of E, where E c is the lowest energy in the conduction band: dsc (E) =

4π (2m n )3/2 (E − E c )1/2 . h3

(1.2.3.12)

The product of (1.2.3.12) and the Fermi–Dirac distribution Eq. (1.2.3.4) gives the function of the energy distribution of electrons in a semiconductor: ρec (E) =

1/2 4π 3/2 (E − E c ) (2m ) . n h3 1 + e(E−Ef )/(kT )

(1.2.3.13)

In the last expression, the effective mass of the electron is denoted by mn . This function is shown in Fig. 1.2.3.11a in the fourth column by the line marked with n. Namely Fig. 1.2.3.11 contains a total of twelve drawings arranged in three rows. Note the rotation of the axis. The independent variable is here, as usual, put on the y-axis while the functions are displayed on the x-axis. The row denoted (a) refers to a pure semiconductor, the row denoted (b) refers to an N-type semiconductor, and the row denoted (c) refers to a P-type semiconductor. In each row, first the dimensions are given in the first column, then the density of states function is given for both electrons and holes in a single drawing, then, in the third column, the Fermi–Dirac distribution is given and finally, the energy distributions of electrons and holes are given. The electron concentration in the conduction band is obtained by integrating (1.2.3.13) from the limit of the conduction band (E c ) to infinity:

1.2.3 Electric Current in Semiconductors

29

Fig. 1.2.3.11 Energy distribution of electrons and holes concentration a pure (intrinsic) semiconductor, b N-type semiconductor, and c P-type semiconductor

4π n = 3 (2m n )3/2 h

{∞ Ec

(E − E c )1/2 dE. 1 + e(E−Ef )/(kT )

(1.2.3.14)

In the range of room temperatures, the value of kT is very small and can be taken that 1 + e(E−Ef )/kT ≈ e(E−Ef )/kT . Using this approximation, (1.2.3.14) reduces to n = 2(2πm n kT / h 2 )3/2 e−(Ec −Ef )/kT .

(1.2.3.15)

30

1.2 Electric Current in Semiconductors

Equation (1.2.3.15) is often represented in the form n = Nc e−(Ec −Ef )/kT ,

(1.2.3.16)

Nc = 2(2πm n kT / h 2 )3/2

(1.2.3.17)

where

is the effective density of states in the conduction band. The concentration of holes may be determined in the same way. The differences in the calculations, in relation to the concentration of electrons, are as follows. First, in (1.2.3.13), instead of the Fermi–Dirac distribution, the following function should be introduced: \ | f ' (E) = 1 − f (E) = 1 − 1/ 1 + e(E−Ef )/(kT ) .

(1.2.3.18a)

This is because, for holes, one should look for the probability that they do not have (do not occupy) some energy in the valence band. That is because a hole is in fact defined as an unfilled covalent bond. Since the Fermi–Dirac function represents the probability of possessing some energy at the temperature of absolute zero, the probability of not possessing some energy is complementary to unity. Similar considerations apply to the generation of the hole density function for holes. Namely, in (1.2.3.7) instead of E we should now put E v − E. This considers the fact that the holes correspond to the energies below E v . The density of energy states in the valence band is shown in Fig. 1.2.3.11 in the second column and is marked with p. The analytical expression for this function would be ρsv =

4π (2m p )3/2 (E v − E)1/2 . h3

(1.2.3.18b)

With a new distribution function, the new density of states, and a change in the integral limit (from −∞ to the highest energy in the valence band, E v ), applying exactly the same procedure as for electrons, with the same approximations, for the concentration of holes one gets p = Nv · e(Ef −Ev )/(kT ) ,

(1.2.3.19)

Nv = 2(2πm p kT / h 2 )3/2

(1.2.3.20)

where

is the effective density of the states in the valence band (Table 1.2.2.1), and mp the effective mass of the hole. Equations (1.2.3.16) and (1.2.3.19) show that the concentrations are functions of temperature and the Fermi level. For a given temperature, the concentration depends

1.2.3 Electric Current in Semiconductors

31

only on the Fermi level E f . This further leads to an important conclusion in the case of semiconductors with chemical impurities where the concentrations differ significantly from those of pure semiconductors. As a consequence of the change of concentration of free carriers by adding impurities, the Fermi level must change. Therefore, the effect of the addition of chemical impurities is reflected in a change in the Fermi level of the semiconductor. Multiplying (1.2.3.16) and (1.2.3.19) and assuming that the energy band width is E g = E c − E v , we obtain that the product of the concentration of holes and free electrons in the semiconductor is n · p = Nc Nv e−Eg /(kT ) .

(1.2.3.21)

The product of concentrations of electrons and holes depends only on the temperature and the width of the energy gap. It does not depend on the value of Fermi level. This means that it does not depend on the concentration and type of chemical impurities. Equation (1.2.3.21) confirms the conclusion that the increase in the concentration of one type of free carriers is accompanied by a decrease, in the same ratio, in the concentration of the other type of free carriers since the product of both types of carriers for a given semiconductor and temperature is constant. For intrinsic semiconductors (without chemical impurities), n = ni = pi = p, so from (1.2.3.2) we get n · p = n 2i = pi2 .

(1.2.3.22)

Numerical values for different semiconductors can be found in Table 1.2.2.2. As can be concluded by comparing ni and the density of atoms, at room temperature, an extremely small number of atoms are ionized. For silicon, it is considered that one atom is ionized for every 3·1012 atoms that remain non-ionized. This comparison is useful to get an idea of what the term pure semiconductor means. If each atom of “unintentional impurities” releases one electron, in the case of a “pure” semiconductor, the number of such electrons should be at least two orders of magnitude smaller than ni so that “unintentional impurities” will not determine the electrical properties of the silicon. This means that the number of “unintentional impurities” atoms (read: dirt) should be 3·1014 times less than the number of silicon atoms. If we imagine that the mass of the “unintentional impurity” atom is equal to the mass of the silicon atom in “pure” silicon per kilogram must not be more than 2·10–15 kg of dirt (2 thousandths of a billionth of a milligram). This tells us what strict constraints semiconductor technology must meet. It is easy to see that for GaAs this number is even lower. At the same time, this number indicates the concentration of “intentional impurities” (controlled impurities) in order for them to determine the electrical properties of the semiconductor. Namely, in order for the concentration of electrons formed by ionization of impurity atoms to be dominant in relation to ni , it is usually assumed that the concentration of donors (acceptors) is

32

1.2 Electric Current in Semiconductors

Fig. 1.2.3.12 Temperature dependence of ni . (left) for Ge, Si, and Gas, and (right) for 4H-SiC and GaN

106 times larger than ni . Thus, the typical values of N D and N A in silicon are of the order of 1016 cm−3 . The temperature dependence of ni is usually given as n 2i = A · T 3 · e−Eg /(kT ) .

(1.2.3.23)

If we consider the temperature dependence of E g given by (1.2.2.1), the quantity − E g /(kT ) increases with increasing temperature and with decreasing E g so that, in total seen, ni increases with temperature. The constant A for silicon is 1.5·1032 cm−6 K−3 . The dependence expressed in (1.2.3.23) is shown in Fig. 1.2.3.12 for five materials: Ge, Si, GaAs, 4H-SiC, and GaN. In the case of silicon, it is approximately true that ni doubles as the temperature rises by 11 K. This temperature dependence, as we shall see later, determines the maximum temperature to which the semiconductor is usable.

1.2.3.3 The Fermi Level in a Semiconductor In intrinsic semiconductors, the Fermi level is in the middle of the energy gap, equally distant from the valence and conduction bands. In order to show this, it is necessary to equate the expressions for the concentrations of free carriers of electrons (1.2.3.16) and holes (1.2.3.19) which are here, for convenience, rewritten: n i = Nc e−(Ec −Efi )/(kT )

(1.2.3.24)

pi = Nv e−(Efi −Ev )/(kT ) ,

(1.2.3.25)

1.2.3 Electric Current in Semiconductors

33

where E fi is denoting the Fermi level in an intrinsic semiconductor. It was previously shown that, in an intrinsic semiconductor, the concentrations of electrons and holes are equal. Equating (1.2.3.24) and (1.2.3.25) after solving for E fi one gets E fi =

Nv 1 1 (E v + E c ) + kT · ln , 2 2 Nc

(1.2.3.26)

and by substitution of (1.2.3.17) and (1.2.3.20) it becomes E fi =

mp 1 3 (E v + E c ) + kT · ln . 2 4 mn

(1.2.3.27)

The effective masses of electrons and holes are close, and the value of kT is very small, so that the second term in (1.2.3.27) can be neglected: E fi ≈ (E v + E c )/2.

(1.2.3.28)

Thus, the Fermi level, in an intrinsic semiconductor, is in the middle of the energy gap. It was previously concluded that the influence of chemical impurities is reflected into the change in the Fermi level in relation to the position of intrinsic semiconductors. In N-type semiconductors, the concentration of donor atoms is N D (atoms/m3 ). At room temperature, these donor atoms are ionized and give N D free electrons. The total number of free electrons should be n n = ND + n i ,

(1.2.3.29)

where ni is the concentration of free electrons created in an intrinsic semiconductor. In the temperature range in which semiconductors are usually located, it is valid ND N c or for N A > N v the Fermi level passes into the conduction or the valence band, respectively. This is the most important feature of degenerated semiconductors. Now, for N-type semiconductors, as with metals, there are electrons whose energy is lower than the Fermi level, but they are still available for conduction. Similarly, for P-type semiconductors, there are holes whose energy is higher than the energy of the Fermi level, but which are still in the valence band and are available for conduction. When generating quantitative conclusions, however, it should be borne in mind that at very high concentrations, the approximation made in deriving (1.2.3.15) from (1.2.3.14) cannot be accepted since E f is now close to E c (similar is valid for the P-type). In this case, therefore, the integral in (1.2.3.14) must be calculated numerically. In the case of a degenerated semiconductor, the impurity atoms interact. Now they are relatively close, so the paths of the “fifth electron”, since they have a large radius, affect each other, and in the energy gap we cannot talk about the donor level, but about the donor levels. This effect is illustrated in Fig. 1.2.3.13c, e. The degradation of the properties of the semiconductor can also occur due to the increase in temperature. Namely, at room temperatures, N D is usually at least five orders of magnitude larger than ni , so that ni is negligible. At elevated temperatures, however, N D remains unchanged while ni increases according to (1.2.3.23). There is a value of temperature when ni ceases to be negligible as compared to N D , so that in the case of N-type semiconductors (1.2.3.38) must be used for the calculation of the concentrations. Of course, at even higher temperatures ni becomes dominant, so the semiconductor behaves as intrinsic. If we assume that the limit of use of the semiconductor is ni = N D , then we have the following expression for the maximum temperature at which the semiconductor can be used Tmax =

Eg 1 . √ 2k ln{ Nc Nv /ND }

(1.2.3.39)

If we take as an example silicon with N D = 5·1014 cm−3 we get T max = 277 °C. For germanium with the same concentration, it would be T max = 100 °C. T max is much higher if the impurity concentration is higher since ni needs to reach N D . In

1.2.3 Electric Current in Semiconductors

37

the practical case, the usability limit of the semiconductor is defined for significantly lower values of ni than N D is, so it is usually assumed that the maximum temperature for silicon is about 200 °C, and for germanium about 90 °C (For some other materials see Table 1.2.2.2). These numbers may vary according to the properties of the component we use. The general conclusion is that components with a large energy gap can be used at higher temperatures. SiC, for example, may be used even above 600 °C.

1.2.3.4 The Drift Current When a constant voltage is applied to the sides of a piece of semiconductor (chip), an electric field K is established inside the semiconductor. This field acts on the free charge carriers and causes them to move in the direction of the electrostatic force acting on them. This movement of free carriers through a semiconductor will be called drift, and the current made by carriers—drift current. Since, by introducing the effective mass of the carriers, we have considered the periodic potential field that prevails in the material independently of the external field, we can assume that the carrier will behave as if it were in a homogeneous electric field. This means that it would move uniformly accelerated with a velocity: v = q·K·t/mn . This is not the case, however. At a given external electric field, the carriers move at a constant speed. The reason for this is a phenomenon we call scattering. There are several scattering mechanisms, of which only two will be described here. Scattering on the crystal lattice occurs due to the collision of free carriers with disturbances in the periodicity of the internal potential distribution in the crystal. These disturbances are the result of vibrations (movements) of atoms around a fixed place in the crystal lattice due to their thermal energy. At one point, the electron enters the area where the atoms are more densely packed, and then it can be found in the area where the atoms are less densely packed. As we have already said, the quantum of vibration energy of the crystal lattice is called the phonon. It can, of course, exist only inside the lattice, and like the photon, it has a corpuscular nature. Now the collision of an electron with a disturbance of the potential distribution in the crystal can be identified as a collision of a free carrier and a phonon. In this collision, energy and momentum are maintained, but there is a change in the direction and speed of the carriers, which means that (if we had a homogeneous beam of carriers) the carriers are scattered. The carrier loses the kinetic energy that it has accumulated during acceleration due to the external field, from the moment of the last scattering. It is then accelerated again until it is scattered again. It is natural that the scattering will be more intense if the temperature is higher. Scattering on impurities is caused by the presence of ionized impurity atoms in different places of the crystal lattice. Since they are in fact ions, they act with an electrostatic force on the electrons that pass by them, changing the direction of their movement. It is easy to see that if the speed of the carriers is higher, the change of direction will be smaller, so this type of scattering will be less pronounced.

38

1.2 Electric Current in Semiconductors

The mean value of the carrier velocity in a semiconductor in the presence of scattering, vd , is given by vdn = −μn K

(1.2.3.40a)

vdp = μp K ,

(1.2.3.40b)

where the index “n” refers to electrons and the index “p” to holes. The proportionality constants μn and μp are called the mobility of electrons and holes, respectively. The values of electron and hole mobilities for selected semiconductor materials at room temperature at small electric fields and for typical impurity concentrations are given in Table 1.2.2.2. It can be seen that the mobility of electrons is several times larger than the mobility of holes, which would be intuitively self-evident when one considers that the movement of a hole is in fact the movement of more electrons. This property of mobility significantly influences the choice of semiconductor type when choosing electronic components. It turns out that μ=

qis , m

(1.2.3.41)

where τs is the transit time (time between two scatterings). For smaller τs the mobility is smaller. It also turns out that 1/μ = 1/μr + 1/μa ,

(1.2.3.42)

where μr denotes mobility that they would have if there was scattering only on the crystal lattice and μa denotes the mobility they would have if there was scattering on impurity atoms only. The carrier mobility is not a constant quantity. It is a function of the carrier concentration, temperature, and the magnitude of the electric field in the material. The influence of concentration on mobility is understandable by itself, since the number of impurity atoms directly determines the scattering. The higher the concentration, the lower the μa . As can be seen from (1.2.3.42) when μa < μr , μa determines the overall mobility. Thus, above some value of concentration, mobility begins to decline. The diagram of the dependence of the mobility of electrons and holes (main carriers) on the concentration in silicon is shown in Fig. 1.2.3.15. The dependence of mobility on temperature is also a complex function. By the nature of things, the mobility associated with scattering on the crystal lattice must decrease with temperature. This dependence is usually given as μr = μr0 (T0 /T )3/2 ,

(1.2.3.43)

1.2.3 Electric Current in Semiconductors

39

Fig. 1.2.3.15 Mobility and diffusion constant for the majority carriers in silicon as a function of concentration

where T 0 is the reference temperature and μr0 is the corresponding value of the mobility for that temperature. On the other hand, due to the increase in the thermal velocity of free carriers at increased temperature, the mobility μa also increases, since scattering due to impurity atoms decreases. So, the following is used μa = μa0 (T /T0 )3/2 ,

(1.2.3.44)

where μa0 is now the value of μa at T 0 . The total dependence of mobility on temperature can be obtained when (1.2.3.43) and (1.2.3.44) are replaced in (1.2.3.42). It should not be forgotten that μa0 depends on the concentration (Fig. 1.2.3.15), so that depending on the concentration, the temperature curve has a different shape. In addition, it should be borne in mind that the degree 3/2 in (1.2.3.43) and (1.2.3.44) is derived from a defect-free crystal. Depending on the number of defects, other (higher) exponent values are used. This is especially true when the currents that are established on the surface (where the density of defects is higher) of the semiconductor are important. There, the presence of the third type of scattering—on the defects of the crystal lattice—has to be considered. Finally, with increased electric fields, the dependence of the velocity of free carriers on the electric field is not linear but follows the law of the square root up to a drift velocity of the order of 103 m/s. Usually, instead of changing the expression for velocity (1.2.3.40), in this area, it is assumed that the mobility is inversely proportional to the square root of the electric field. Above these field values, the velocity gradually reaches its maximum value, which is determined by the thermal velocity of the carriers (for silicon about 105 m/s) and no longer depends on the magnitude of the electric field. We say that the velocity is saturated. When the velocity of carriers is saturated, in order for (1.2.3.40) to remain valid, the mobility must be inversely proportional to the electric field.

40

1.2 Electric Current in Semiconductors

At the end of these considerations on mobility, it should be noted that the mobility of minority carriers in a semiconductor is somewhat lower due to the shorter lifetime of the minority carriers (the percentage of recombined minority carriers is higher than the percentage of recombined majority carriers). Let us now consider the electric current generated in a semiconductor subjected to an electric field. Let the electric field acts in the direction of the x-axis and let the concentration of free electrons and holes in the semiconductor be n and p, respectively. The charge of the electron is −q, and of the hole is q. Then the electron current density will be Jnx = −

1 q · n · dV q · n · dx 1 dQ = = = qnvdn = qnμn K x , S dt S dt dt

(1.2.3.45)

where S is the cross-sectional area, V is the volume, and K x is the electric field in the x-axis direction. The current density of holes is obtained in a similar way: Jpx = qpvdp = qpμp K x .

(1.2.3.46)

The total current density is obtained by adding the current densities of electrons and holes: ) ( Jx = Jnx + Jpx = q nμn + pμp · K x .

(1.2.3.47)

Equation (1.2.3.47) can be written in the form Jx = σK ,

(1.2.3.48)

σ = q · (nμn + pμp )

(1.2.3.49)

where

is the specific conductivity of the semiconductor material. In an N-type semiconductor n >> p, and in a P-type semiconductor p >> n. That is why one can write σn = qnμn

(1.2.3.50)

σp = qpμp

(1.2.3.51)

and

for N- and P-type semiconductors, respectively. The direct relation between the specific conductivity and the concentration of free carriers makes it possible to determine the concentration of free carriers by knowing the specific conductivity of a material (for example, by measurement).

1.2.3 Electric Current in Semiconductors

41

Fig. 1.2.3.16 Generalized temperature dependence of the specific conductivity for the moderate concentration of the majority carriers

Specific conductivity depends on the temperature for two main reasons. One of them is the dependence of the concentration on the temperature, which, in the case of a doped semiconductor, is pronounced at very low temperatures (when all the atoms of impurities are not ionized) or at very high temperatures (when the speed of thermal generation of free carriers becomes very high). The second reason is the temperature dependence of mobility, which has already been discussed and which will have a dominant effect on moderate temperatures which are the ones that are of the greatest interest. In Fig. 1.2.3.16 the general form of temperature dependence of specific conductivity on temperature for a doped semiconductor with moderate impurity concentration is given. It should be noted that the abscissa has a reciprocal value of temperature so that the origin of the diagram corresponds to infinite temperature. Room temperature belongs to the area where μ ≈ T −3/2 . When a semiconductor is degenerated, at moderate temperatures, the conductivity is practically independent of temperature. At room temperature, intrinsic materials have the following specific resistances (ρ = 1/σ): ρSi = 230 kucm, ρGe = 47 ucm and ρGaAs = 10 Mucm. By adding impurities, the specific resistance is reduced. Thus N-type silicon with N D = 5· 1015 cm−3 has ρSi = 1 ucm.

1.2.3.5 The Diffusion Current The previous considerations referred to the semiconductor in which free carriers are generated due to thermal excitation. Except for exceptional situations (very large semiconductor wafers where the ends may be at different temperatures) the distribution of carrier concentrations is uniform given that the temperature is the same everywhere. However, there is a possibility of causing unevenness in the concentration of carriers in the pellet. This may be achieved by illuminating one part of the plate or by injecting free carriers into the semiconductor in an appropriate manner. Irrespective of the way in which irregularities in concentration occur, a concentration gradient is formed in the semiconductor, which results in the movement of carriers

42

1.2 Electric Current in Semiconductors

Fig. 1.2.3.17 Movement of holes by diffusion

or the formation of current. The movement of carriers (or in nature, in general, particles) due to the non-uniformity of concentrations with the tendency to equalize the concentration is called diffusion. Let a higher concentration of holes is created at one end of the semiconductor (for example, by injection of carriers) than in the rest of the semiconductor. In Fig. 1.2.3.17 the change in the concentration of holes p(x) along the length of the semiconductor x is presented. The holes move chaotically through the semiconductor. Thus, through a cross section whose abscissa is x, they pass in both directions. But, since the concentration of holes to the left of the section is higher than in the right part, more holes will move from left to right than from right to left. The result of this process is the directed movement of holes, by diffusion, along the x-axis, which makes an electric current. According to the phenomenon that forms it, this current is called diffusion current. The density of the diffusion current of the holes will be proportional to the change in the concentration of the holes along the x-axis. If the change in concentration is larger (the curve p(x) has a larger slope), the diffusion current is also larger. Therefore, it can be written

Jpx = −q Dp

dp . dx

(1.2.3.52)

The negative sign in this equation arises due to the fact that the hole concentration gradient is negative. In the same way, we express the electron diffusion current density as Jnx = −q Dn

dn . dx

(1.2.3.53)

The proportionality constants Dp in (1.2.3.52) and Dn in (1.2.3.53) are called diffusion constants of holes and electrons, respectively. The diffusion constant is shown to be given as D = kT · is /m

(1.2.3.54)

1.2.3 Electric Current in Semiconductors Table 1.2.3.1 Diffusion constant

43

cm2 /s

Si

Ge

GaAs

Dn

34

98

217

Dp

13

46

11.5

so that the Einstein relation is applicable: Dp Dn kT = VT . = = μn μp q

(1.2.3.55)

The ratio of diffusion constant and mobility is determined by the temperature. The value of V T is often called the voltage equivalent of temperature. Numerical values of diffusion constants of electrons and holes for room temperature, at concentrations of 1015 cm−3 and at small fields are given in Table 1.2.3.1. As with mobility, it can be observed here that the diffusion constant of the electron is larger than the diffusion constant of the holes. In equilibrium condition, when there is a concentration gradient of one type of carriers in a semiconductor, there is also a concentration gradient of the other type. If the concentration of holes decreases with increasing distance, the electron concentration increases so that the condition n·p = ni 2 is always fulfilled. The total diffusion current density in these conditions is ) ( ∂p ∂n − Dp Jdx = q Dn ∂x ∂x

(1.2.3.56)

and since the derivatives are of the opposite signs, the terms are added together in absolute value. If we apply voltage to such a semiconductor, the total current density will be ) ∂p ∂n , Jx = q(nμn + pμp )K x + q Dn − Dp ∂x ∂x (

(1.2.3.57)

where the electron current density is ) ( ∂n Jnx = q nμn K x + Dn ∂x

(1.2.3.58)

and the holes current density is ) ∂p . = q pμp K x − Dp ∂x (

Jpx

(1.2.3.59)

The results presented here can be used to explain the phenomenon that occurs in a semiconductor that is not uniformly doped. So, in one place we have a higher concentration of impurities, and in another lower. In the steady state, without an

44

1.2 Electric Current in Semiconductors

Fig. 1.2.3.18 Electric field and potential difference orientations within a non-uniformly doped n-type semiconductor slab. n(x 1 ) < n(x 2 )

external electric field and without injection of external carriers, J nx = 0 and J px = 0. By inserting these conditions in (1.2.3.58) and (1.2.3.59) we get K = VT

1 dn 1 dp = −VT . p dx n dx

(1.2.3.60)

This equation shows that an electric field is established at the place where there is a built-in change of the carrier concentration. The size of the field is a function of distance and is determined by the gradient of the change in the built-in concentration. This phenomenon is explained by the diffusion of (majority) carriers in the area with lower concentration. Of course, after the establishment of balance, there is no more movement of the carriers. This means that the established field prevents further movement. This situation is depicted in Fig. 1.2.3.18 for the case when electrons are the majority carriers. Equation (1.2.3.60) is, of course, still applicable.

1.2.3.6 The Continuity Equation From the previous statements it can be concluded that if we want to determine the current flowing through a semiconductor, we must determine the concentration gradient. To find this quantity, we use the continuity equation. It describes the rate of change of the concentration of free carriers (electrons and holes) in a given volume. The derivation of this equation will be simplified here, but the final result is undoubtedly correct. Let us first consider the situation in a semiconductor through which current flows under the condition that the generation and recombination are abstracted. For this purpose, we will use the cube of Fig. 1.2.3.19. Here /\x is the length of the edge of the cube. The current I enters the cube in the x-axis direction while the current I + /\I leaves the cube. Causes of current changes can be, for example, changes in carrier speed, carrier divergence, etc. If the current is made up of electrons, then in

1.2.3 Electric Current in Semiconductors

45

Fig. 1.2.3.19 Semiconductor cube with the input and output current shown

the time interval /\t the cube will leave /\N more electrons than entered (N) so that the current increment is /\I = q(/\N //\t)

(1.2.3.61)

(The current is obtained as I = q(N//\t)). The change in the electron concentration in the time interval /\t, due to the change /\N, is equal to the quotient /\N and the cube’s volume: /\n = /\N /V

(1.2.3.62a)

or /\n =

/\I · /\t . q(/\x)3

(1.2.3.62b)

The last expression is in fact approximative because the finite time interval and the finite volume of the cube are taken. If we switch to differentially small increments, we get dI · dt . q(dx)3

(1.2.3.63)

dI dn = . dt q(dx)3

(1.2.3.64)

dn = which leads to

Bearing in mind that the increment of the current density along the x-axis is d Jnx = d[I /(dx)2 ] for (1.2.3.64) one can write

(1.2.3.65)

46

1.2 Electric Current in Semiconductors

1 d Jnx dn = . dt q dx

(1.2.3.66)

This equation shows the change in the concentration of free electrons over time, as a function of the change in the current density looking longitudinally (in other words, the rate of change in the concentration is proportional to the current density gradient). The increase in current that affects the cube is not the only cause of changes in the concentration of free electrons. In the observed volume, free electrons are generated at a certain temperature, and they also recombine with holes. Let gn electrons be generated per unit volume per second and let r n electron be recombined per unit volume per second. gn is the rate of generation, and r n is the rate of recombination of free electrons. The rate of change of concentration can now be corrected if generation and recombination are considered: dn 1 d Jnx = gn − rn + . dt q dx

(1.2.3.67)

This is one of the possible forms of the continuity equation for electrons. The continuity equation for holes will be dp 1 d Jpx = gp − rp − . dt q dx

(1.2.3.68)

The minus sign of the last term comes from the opposite sign of the charge of the holes as opposed to the electrons. Substituting (1.2.3.58) and (1.2.3.59) into (1.2.3.67) and (1.2.3.68), respectively, yields ∂n ∂n ∂ 2n ∂ Kx = gn − rn + μn K x + μn n + Dn 2 ∂t ∂x ∂x ∂x

(1.2.3.69)

∂p ∂p ∂2 p ∂ Kx = gp − rp − μp K x − μp p + Dp 2 ∂t ∂x ∂x ∂x

(1.2.3.70)

The rate of recombination of free electrons depends on their concentration, since the higher the concentration, the higher the probability of recombination. So: rn = kn n,

(1.2.3.71)

where k n is the proportionality constant. There is a concentration of free electrons n0 when the process of generation and the process of recombination are in equilibrium, i.e., gn = gn |n=n 0 = kn n 0 .

(1.2.3.72)

1.2.3 Electric Current in Semiconductors

47

For a given temperature, the rate of generation of free electrons is constant, so the combination of (1.2.3.71) and (1.2.3.72) yields gn − rn = kn (n 0 − n).

(1.2.3.73)

In this case, let the change in the current density J nx due to fluctuations in the carrier velocity be equal to zero. Then (1.2.3.67) can be written in the form dn/dt = kn (n 0 − n).

(1.2.3.74)

On the other hand, it can be shown that dn 1 =− , dt |n−n 0 =1 τn

(1.2.3.75)

where τn is the average lifetime of electrons. Indeed, in (1.2.3.72), if the change in the concentration of electrons (dn) is equal to one electron, then the corresponding change in time is τn , because this is the time during which the electron exists as free. Thus: kn = 1/τn .

(1.2.3.76)

Substituting (1.2.3.72) into (1.2.3.70) gives gn − rn = −(n − n 0 )/τn .

(1.2.3.77)

By a similar consideration, for holes they would get gp − rp = −( p − p0 )/τp .

(1.2.3.78)

Substituting (1.2.3.77) and (1.2.3.78) into (1.2.3.69) and (1.2.3.70), respectively, brings the very frequently used expressions for the continuity equation. n − n0 ∂n ∂ 2n ∂n ∂ Kx =− + μn n + Dn 2 + μn K x ∂t τn ∂x ∂x ∂x

(1.2.3.79)

p − p0 ∂p ∂2 p ∂p ∂ Kx =− − μp p + Dp 2 . − μp K x ∂t τp ∂x ∂x ∂x

(1.2.3.80)

The continuity equation for electrons and holes is derived for the majority of carriers of electricity. The same equations will apply to minority carriers. Thus, in an N-type semiconductor, the continuity equation for minority carriers will be pn − pn0 ∂ pn ∂ Kx ∂ 2 pn ∂ pn =− − μp pn + Dp − μp K x , ∂t τpn ∂x ∂x ∂x2

(1.2.3.81)

48

1.2 Electric Current in Semiconductors

Fig. 1.2.3.20 Free electrons injected in a semiconductor slab

where the index n is used to denote the N-type of the semiconductor. Similarly, for a P-type semiconductor, the continuity equation for electrons, which are the minority carriers here, will be n p − n p0 ∂n p ∂ 2np ∂n p ∂ Kx =− + μn n p + Dn 2 . + μn K x ∂t τnp ∂x ∂x ∂x

(1.2.3.82)

If the changes along all three coordinate axes are considered, the continuity equation, for the example of electrons in an N-type semiconductor, takes the form ( ) ∂n ∂n ∂n 0 K + = − n−n + μ + K + K n x y z τn ∂z )∂ x ( ∂ y2 ) ( 2 ∂ Ky ∂ Kz ∂ Kx ∂ n ∂2n +μn n · ∂ x + ∂ y + ∂ z + Dn ∂ x 2 + ∂ y 2 + ∂∂ zn2 . ∂n ∂t

(1.2.3.83)

This equation is obtained by summing the corresponding changes along the coordinate axes. A similar expression can be derived for holes in a P-type semiconductor, etc. The following example can serve as a good illustration of the application of the continuity equation. Let free electrons be generated at one end of the semiconductor crystal, for example, by photon excitation or simply by inserting free electrons as shown in Fig. 1.2.3.20. For x = 0 the electron concentration is higher than the equilibrium value n0 . The value of the excess concentration is n(0) − n0 . Electrons move by diffusion from left to right along the length of the semiconductor. Along the way, they recombine with holes, so the concentration of electrons decreases along the x-axis. Let the semiconductor shown in Fig. 1.2.3.20 be long enough so that at its right end the concentration is n0 . If the electrons at the left end of the semiconductor are inserted or generated at a constant speed, the change in the electron concentration along the semiconductor will not depend on time and will be (dn/dt) = 0 for each x. Let no electric field acts on the semiconductor (K = 0). The continuity equation, under these conditions, will have a form 0=−

d2 (n − n 0 ) n − n0 + Dn . τn dx 2

(1.2.3.84)

1.2.3 Electric Current in Semiconductors

49

The solution to this equation is n − n 0 = A1 e−x/L n + A2 e x/L n ,

(1.2.3.85)

where Ln =

/

Dn τn .

(1.2.3.86)

The values of the integration constants (A1 and A2 ) are determined from the boundary conditions. For x = 0, it is n = n(0) (known concentration determined by external excitation). For x → ∞ it is n = n0 so that A2 = 0. Thus (1.2.3.85) is reduced to n − n 0 = [n(0) − n 0 ]e−x/L n .

(1.2.3.87)

The quantity L n is called a diffusion length of the electron. According to (1.2.3.87), this is the distance at which the concentration decreases e = 2.72 times in comparison to the initial concentration. The diffusion length of holes (L p ) is defined in a similar way. It can be shown that for one electron (or hole) the diffusion length represents the mean length of the path exercised between generation and recombination. From (1.2.3.87) we see that when x (depth in a semiconductor) is about five times larger than L n , the concentration n is practically equal to n0 , which means that 5·L n is the approximate depth to which injected carriers penetrate. The value of L n depends on the values of the diffusion constant and the lifetime. For silicon, for example, if we take τn = 20 μs and Dn = 34 m2 /s we get L n (Si) = 0.24 mm. For GaAs at τn = l0−9 s, we have L n (GaAs) = 4.6 μm, for GaN at N D = 1017 cm−3 we have L n (GaN) = 1.7 μm, and for 4H-SiC at τn = l0−9 s we have L n (GaAs) = 1.5 μm. The significance of the obtained result (1.2.3.83) comes to the fore when the secondary carriers are considered. Namely, the injection of main carriers is practically irrelevant since n0 is a large number in the N-type semiconductor, so we can practically not influence the behavior of the semiconductor. Having in mind, however, the small values of n0 when the P-type semiconductor is in question, it is easy to practically realize values of n(0) that are significantly above n0 and thus to create a large concentration gradient and a corresponding current. Injected carriers, however, are of one type (in this case, electrons) so that they represent an excess charge of one type in the semiconductor and disrupt electrical neutrality. It is also interesting to establish the dependence of the concentration of excess minority carriers on the time when the injection stops. For this purpose, we use the continuity Eq. (1.2.3.82) with ∂np /∂x = 0 (since there is no built-in concentration gradient) and K = 0. Now recombination is what determines the concentration of injected secondary carriers, so we have n p (t) − n p0 = [n p (0) − n p0 ] · e−t/τn .

(1.2.3.88)

50

1.2 Electric Current in Semiconductors

Here, np (0) is the value of the concentration of excess minority carriers for t = 0, and np0 is the equilibrium concentration of minority carriers (electrons in a P-type semiconductor). Based on this relation, we conclude that τn determines the rate of recombination (disappearance) of the injected excess charge of free carriers. If τn is small, this process is very fast so that in the components where the injected charge should be transported through the semiconductor (we will see later that this is the case with the bipolar transistor) we cannot use such a material (GaAs for example). The continuity equation can also be solved if the concentration of injected carriers changes with time. As an example, we will consider the case when n(0) changes periodically: n(x, t)|x=0 = n(0) · sin(ωt)

(1.2.3.89)

n(x, t)|x=0 = n(0)ejωt .

(1.2.3.90)

or in a complex form

Therefore, at a distance x, the concentration will depend on the time according to the law n(x, t) − n(0) = N (x) · ejωt ,

(1.2.3.91)

where N(x) represents the dependence of concentration on the distance which, as shown earlier, has an exponential form. Substituting (1.2.3.91) into (1.2.3.79), for K x = 0, one gets jωN (x) · ejωt = −

d2 N (x) N (x) · ejωt + Dn ejωt τn dx 2

(1.2.3.92)

which can be written in the form 0 = −N (x)

d2 N (x) 1 + jωτn + . L 2n dx 2

(1.2.3.93)

If the concentration did not depend on time, which was the case in (1.2.3.84), N(x) = n − n0 would hold, so (1.2.3.93) would have the form 0=−

N (x) d2 N (x) + . L 2n dx 2

(1.2.3.94)

By comparing the last two equations, we conclude that the solution of the continuity equation derived for steady state (concentration does not change over time) will also be valid for the case when the concentration √ changes in time if the diffusion length is replaced by the expression: L ∗n = L n / 1 + jωτn . It is understood that the

1.2.3 Electric Current in Semiconductors

51

same conclusion applies to holes, with the proviso that in the solution of the continuity equation / for the steady state, the diffusion length of the holes L p is replaced by L ∗p = L p / 1 + jωτp if the concentration changes with time. The last results will be of precious value when characterizing the frequency response of bipolar transistors which comes in the fourth chapter of this book.

1.3 The p-n Junction and the Diode

1.3.1 The p-n Junction If in a semiconductor material we have chemical impurities of the acceptor type (Ptype semiconductor) at one end and chemical impurities of the donor type (N-type semiconductor) at the other end, then this semiconductor is a combination of two different types of semiconductor or it is a p-n junction. This junction is shown in Fig. 1.3.1.1a. To the left of the junction is a higher concentration of holes because it is a Ptype semiconductor, and to the right of the junction in an N-type semiconductor is a higher electron concentration. Therefore, there will be diffusion of holes from the P-type semiconductors into the N-type semiconductors and diffusion of electrons in the opposite direction. Since the holes, from the area close to the junction’s boundary, have passed into the N-type semiconductor, the P-type semiconductor layer along the boundary itself will no longer be electrically neutral but, in that part, the negative charge (due to negative acceptor ions) will be in excess. In a similar way, due to the diffusion of electrons, in an area close to the boundary on the side of the N-type semiconductor, there is an excess of positive charge. This situation is schematically shown in Fig. 1.3.1.1a, and the dependence of the space charge density on the distance in Fig. 1.3.1.1b. In the semiconductor, at the junction, the electrical neutrality is disturbed, with a negative space charge in the P-region and a positive one in the N-region. As a result of the action of two opposite charges on the junction, an electric field K x will appear, directed from the layer with positive space charge to the layer with negative. This electric field is schematically shown in Fig. 1.3.1.1a, and c shows the change in intensity of the same as a function of distance. The electric field K x has such a direction that it does not allow further movement of holes from the P-region into the N-region and electrons from the N-region into the P-region. Electrons and holes no longer pass through the junction because the

© The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 V. Litovski, Lecture Notes in Analog Electronics, Lecture Notes in Electrical Engineering 1002, https://doi.org/10.1007/978-981-19-9868-3_3

53

54

1.3 The p-n Junction and the Diode

Fig. 1.3.1.1 a Schematic representation of the p-n junction, b space charge density for (left) abrupt change of the concentration of the impurities and (rigth) lienar change of the concentration of impurities, and c the intensity of the electric filed at the junction

component of the force originating from the electric field and the component of the force generated by the concentration gradient are in equilibrium. A stationary state has been established at the p-n junction which is characterized by the existence of a transitional area in the vicinity of the junction boundary. In the transition region, there is an excess negative charge in the P-region and a positive charge in the N-region. That is why the transition area is also called the area of space charge. In the transitional area, there are no free carriers of electricity, so it is also called a depleted region. The width of the depleted region depends on the concentration of free carriers or impurities in the P- and N-region. If these concentrations are not equal to each other, the transition region is asymmetric with respect to the limit of the p-n junction. The larger width is in the area where the concentration of impurities is lower. In general, the width of the transition area is small and is of the order of 10–6 m or 1 micron. The electric field acting in the transition region creates a potential barrier between the P- and N-regions, which does not allow further movement of the charge. Therefore, it is said that the transition area contains a potential barrier or contact potential. The magnitude of the potential barrier can be calculated as a function of the concentrations of donor and acceptor atoms in N- and P-type semiconductors. The starting

1.3.1 The p-n Junction

55

Fig. 1.3.1.2 Energy levels at the p-n junction

point for the calculation is the fact that the p-n junction is a unique system and that in this system the Fermi level must be constant. In Sect. 1.2.3.3, the Fermi level for P- and N-type semiconductors is determined, and its position is shown in Fig. 1.2.3.13. Since in the p-n junction the Fermi level is constant, it is necessary for the energy levels of the valence and conduction bands to shift in relation to it, as shown in Fig. 1.3.1.2. Namely, in the P-domain the Fermi level is closer to the valence band while in the N-domain it is closer to the conduction band. It is not difficult to understand the phenomenon of bending of energy bands if we consider the dependence of the Fermi level on the concentration. Namely, at the boundary of the p-n junction there is a sudden change in the concentration of carriers, and thus the value of the Fermi level. If, however, the insistence on a constant Fermi level remains nothing but to move the boundaries of the valence and conduction bands. The notations in Fig. 1.3.1.2 are as follows. E f denotes the Fermi level, E cp and E cn the energy of the lower limits of the conduction band in P- and N-semiconductors, and E vp and E vn the energy of the upper limits of the valence band in P- and Nsemiconductors, with E g energy of the energy gap, and with E 0 energy of the barrier. The difference between the energies of the lower limits of the conduction bands of the P- and N-domains (or the upper limits of the valence bands) represents the energy barrier that free electrons from the N-domain must overcome in order to pass into the P-domain or holes from the P-domain they need to master in order to move to the N-domain: E 0 = E cp − E cn = E vp − E vn .

(1.3.1.1)

From (1.2.3.33) and (1.2.3.36) one gets E cn = E f + kT · ln(NC /ND )

(1.3.1.2)

56

1.3 The p-n Junction and the Diode

and E cp = E g + E vp = E g + E f − kT · ln(NV /NA ),

(1.3.1.3)

while from (1.2.3.21) we find the width of the energy gap as: E g = kT · ln

NC NV . n·p

(1.3.1.4)

Bearing in mind (1.2.3.22) one gets E g = kT · ln(NC NV /n 2i ).

(1.3.1.5)

By combining (1.3.1.5), (1.3.1.3), (1.3.1.2) and (1.3.1.1) one gets E 0 = kT · ln(NA ND /n 2i ).

(1.3.1.6)

If we introduce: nn —electron concentration in the N-region (nn ≈ N D ), np —electron concentration in the P-region, pn —hole concentration in the N-region and pp —hole concentration in the P-region (pp ≈ N A ), (1.3.1.6) becomes (

pp E 0 = kT · ln pn

)

(

) mn = kT · ln , mp

(1.3.1.7)

where the relation n n pn = n p pp = n 2i was used. Numerical values of the potential barrier in silicon ranging up to 1 eV can be obtained for practical values of the concentration of electrons and holes in the P- and N-regions, respectively. Example E.1.3.1 Determine the height of the potential barrier at the silicon p-n junction on which it is N D = 1015 cm−3 and N A = 1018 cm−3 . Consider the ambient temperature T = 300 K. Solution: By substitution in (1.3.1.6) one gets E 0 = 0.635 eV which represents the energy barrier at the junction. The potential barrier is V 0 = E 0 /q = 0.635 V. The temperature dependence of the size of the energy barrier at the p-n junction is predominantly determined by the dependence of the intrinsic concentration ni . Since ni is growing very fast with the increase in temperature, it is to be expected that E 0 will decrease accordingly. These reasonings will be supported by one example. Example E.1.3.2 Determine the height of the energy barrier at the p-n junction from Example E.1.3.1 for three temperature values: T = 270 K, T = 300 K, T = 330 K.

1.3.2 Semiconductor Diodes

57

Solution: By substituting in (1.3.1.6) the following numbers are obtained: E 0 (270 K) = 0.83 eV, E 0 (300 K) = 0.78 eV, and E 0 (330 K) = 0.73 eV.

1.3.2 Semiconductor Diodes A diode is an electronic component that has the property of conducting current in only one direction. This direction is called the conductive or direct and, in ideal conditions, the resistance of the diode in that direction is zero. In the other, nonconductive or inverse direction, the diode does not conduct current and, ideally, the resistance of the diode in that direction is infinite. It is easy to understand the need for such an electronic component. When an alternating signal is applied to the diode, current will flow through the diode only in one half-cycle of the signal (only positive or only negative), which means that the alternating signal will be rectified. In addition to this there are many other applications of the diode. The described ideal characteristic of the diode can be approximately realized by means of a p-n junction. This means that the p-n junction can be used as a diode. Due to the way in which the p-n junction is obtained, such a diode is called a diode with a surface junction or simply a junction diode. The structure of one diode is shown in Fig. 1.3.2.1a. It consists of a P-type semiconductor body, a p-n junction, an N-type semiconductor body, and two contacts: a P-type metal–semiconductor and an N-type metal–semiconductor. The forward biasing of the diode is shown (when a larger current flows through the junction). Figure 1.3.2.1b shows an electric circuit using the schematic symbol of the diode. The external power supply (battery), which is connected to the p-n junction, acts in opposition to the electric field K, which represents a potential barrier (V 0 = E 0 /q). If the effects related to the contact between the metal and the semiconductor and the semiconductor body itself, which will be discussed later, are ignored, a barrier equal to V 0 -V now acts at the junction. In order for an electron to pass from the conduction Fig. 1.3.2.1 a Forward biased p-n junction and b schematic representation

58

1.3 The p-n Junction and the Diode

band in the N-region to the conduction band in the P-region, it needs to be supplied, at least the energy q(V 0 – V ), which is less if the external polarization voltage V is larger. Thus, with forward biasing, the potential barrier decreases and thus increases the probability that a thermally activated electron has enough energy to overcome the barrier and move into the P-region. The same goes for holes. In conclusion, we can say that when the junction is forward (directly) biased, carriers are injected into the area of the opposite type of conductivity. The number of injected carriers in a given p-n junction depends on the connected direct polarization voltage and temperature. Figure 1.3.2.2a shows the energy diagram of a forward-biased diode. The current through the diode during forward biasing is made up of the majority of charge carriers. The inverse (backward) biasing of the p-n junction is shown in Fig. 1.3.2.3. The electric field, caused by an external voltage source V, acts in the same direction as the electric field K x at the junction. As a result, the overall potential barrier is higher, and the width of the depleted area has increased. This situation is shown in Fig. 1.3.2.2b. Holes from the P-region cannot pass into the N-region and vice versa: electrons from the N-region cannot pass into the P-region. In the first approximation, current does not flow through the junction. More precisely, a current indeed flows. It is made up of minority carriers. Namely, the electric field at the junction is such that under its influence electrons from the P-region (np ) move to the N-region and holes from the N-region (pn ) to the P-region. The current in the forward direction is several orders of magnitude higher than the current in the backward direction because for the same ratio the concentration of majority carriers is higher than the concentration of minority carriers. Fig. 1.3.2.2 Energy levels at a a forward biased p-n junction and b a backward biased p-n junction

1.3.2 Semiconductor Diodes

59

Fig. 1.3.2.3 a Backward biased p-n junction and b schematic representation

1.3.2.1 Characteristic of the Diode The characteristic of a semiconductor junction diode is in fact the dependence of the current through the diode on the voltage at the terminals of the diode. It can be determined experimentally or theoretically. For the experimental determination of the diode characteristics, the circuit of Fig. 1.3.2.4 is usually applied. Note, the voltmeter here is placed far from the diode so that its leakage current does not disturb the measurement. When high (forward) currents are measured, however, the voltmeter should be placed in parallel with the diode so that the voltage drop on the ampermeter is avoided. Typically measured dependences of the current through a semiconductor diode on the voltage at its terminals are given in Fig. 1.3.2.5 for germanium (Ge) and silicon (Si) diodes. In Fig. 1.3.2.5 the scale for the current in forward (first quadrant) and backward (inverse) (third quadrant) directions are not the same. The same goes for the voltage scale. With forward biasing, the current, in the beginning, practically does not grow, but then, for still small voltages of the order of several hundred millivolts, it begins to increase very quickly. In inverse polarization, the inverse current increases to a biasing voltage of about −0.1 V, and then becomes approximately constant, of the order of nA for silicon and μA for germanium diodes. Only at high inverse voltages (of the order of one hundred volts) does the inverse current begin to rise sharply. This part, in Fig. 1.3.2.5, is called the breakdown area and, as a rule, does not represent the working area of the diode because the rectifying properties are lost there. In order to theoretically determine the current through a diode, it is first necessary to see which components are present in forward and inverse biasing. Figure 1.3.2.6 shows a forward-biased p-n junction and the components of the current flowing through it. Fig. 1.3.2.4 A circuit to ensure the diode characteristic

60

1.3 The p-n Junction and the Diode

Fig. 1.3.2.5 Characteristic of the semiconductor junction diode made of germanium (Ge) and silicon (Si) Fig. 1.3.2.6 Components of the currents at the p-n junction

1.3.2 Semiconductor Diodes

61

Under the influence of an electric field, holes move from the P-region to the N-region and form the hole-current in the P-region which is here represented by its density J pp . As we approach the junction, the intensity of this current decreases because the holes recombine with the electrons along the way. After the junction, the holes pass into the N-region and form a hole-current in the N-region (J pn ). Due to further recombination, the magnitude of this current decreases to zero at the end of the N-region. Namely, it can be assumed that the length of the N-region is large enough to recombine all the injected holes. Under the action of an electric field, electrons move in the N-region towards the junction and form an electron current in the N-region (J nn ). Along the way, they recombine with the holes so that the electron current decreases. As they pass through the junction, they form an electron current in the P-region (J np ). The length of the P-region is large enough so that all electrons injected from the N-region recombine before the end of the P-region. Based on these considerations, we can easily conclude that both types of carriers participate in the formation of diode current: electrons and holes. That is why such components are called bipolar. Thus, a diode is a bipolar component. The total current is obtained by adding the current of holes and electrons. It is constant and independent of distance from the junction. In the cross-section, x = 0, the total current density can be determined as | | | | |J | = | Jpn (0)| + | Jnp (0)|.

(1.3.2.1)

In this consideration, it is assumed that the width of the depleted area is small and that the currents do not change when passing through it. Therefore, in Fig. 1.3.2.6, the transition area is not even indicated. In addition, as can be seen from the same figure, the sizes of J nn and J pp differ because the concentrations of impurities (main carriers) in the N- and P-regions are considered to be different. Figure 1.3.2.7 represents the dependence of the free carrier concentrations in the N- and P-domains on the distance x. Since the holes pass from the P- to the N-region, their concentration at the junction [pn (0)] is much higher than the own concentration of holes in the N-region (pn0 ) that exists when no voltage is connected to the diode: pn (0) >> pn0 .

(1.3.2.2)

Due to recombination, the concentration of holes in the N-region decreases with increasing value of x according to the indicated law pn (x) and at the end of the semiconductor is pn0 . With respect to (1.3.2.2), the change in the concentration of holes with the change in distance is significant. This means that in the N-region the hole current will have a diffusion character. If pn (x) is known, the current density of the holes J pn (0) at the junction can be determined based on (1.2.3.52) as: Jpn (0) = −q Dp

d pn (x) . dx |x=0

(1.3.2.3)

62

1.3 The p-n Junction and the Diode

Fig. 1.3.2.7 Concentration distributions for forward biasing

Similarly, according to (1.2.3.53), the electron current density at the junction is Jnp (0) = q Dn

dn p (x) , dx |x=0

(1.3.2.4)

where np (x) is the dependence of the electron concentration in the P-region on the distance from the junction. The electron concentration at the junction np (0) is significantly higher than the intrinsic electron concentration in the P-region np0 : n p (0) >> n p0 ,

(1.3.2.5)

but at the end of the P-region it becomes equal to the intrinsic concentration of electrons due to recombination (it is still assumed that the length of the P-region is sufficiently large). The variation of the concentration of holes in the N-region and electrons in the P-region can be obtained as a solution of the continuity equation. As the concentration does not depend on time, assuming that the current has only a diffusion character, (1.2.3.81) can be written in the form 0=−

d2 pn (x) pn (x) − pn0 + Dp . τpn dx 2

(1.3.2.6a)

The general form of the solution of this differential equation is pn (x) − pn0 = A1 e−x/L p + A2 ex/L p .

(1.3.2.6b)

1.3.2 Semiconductor Diodes

63

Integration constants (A1 and A2 ) are determined from boundary conditions which are expressed as follows. When it is x → ∞ then pn (x) → pn0 .

(1.3.2.7a)

Therefore, the constant A2 must be equal to zero. For x → 0 it is pn (x) = pn (0)

(1.3.2.7b)

which allows for the constant A1 to be determined. Now we get pn (x) − pn0 = [ pn (0) − pn0 ] · e−x/L p .

(1.3.2.8)

The value of pn (0) is determined from (1.3.1.7) which can be written in the form pn = pp e−E0 /(kT ) .

(1.3.2.9)

At the junction itself, for x = 0, when no external voltage is applied, the concentrations of the majority and minority carriers are the same as in the whole P-region, so (1.3.2.9) can be rewritten in the form pn0 = pp0 · e−E0 /(kT ) .

(1.3.2.10)

When the external voltage V is applied, however, the concentration at the junction, at x = 0, changes since the external voltage reduces the energy of the barrier E 0 by the value q·V. That is why the following is valid pn (0) = pp (0) · e−(E0 −q V )/(kT ) .

(1.3.2.11)

With small changes in the concentration at the junction (with small “injections”) it can be assumed that the concentrations of the main charge carriers do not change: pp (0) = pp0 .

(1.3.2.12)

The last statement can be demonstrated by the following example. The usual concentrations of majority carriers are of the order of pp0 = 1016 cm−3 while for the minority carriers we have np0 = 104 cm−3 . Let the electrons from the N-region pass into the P-region and let the concentration of electrons at the junction increase to np (0) = 1014 cm−3 . Electrons in the P-region are minority carriers and their concentration has increased by 1010 times. Due to the electrical neutrality, however, the same positive charge is attracted from the depth of the P-type semiconductor so that pp (0) = pp0 + np (0) = 1016 + 1014 ≈ 1016 cm−3 . It is this result that is stated in (1.3.2.12). By substituting (1.3.2.12) into (1.3.2.11) one gets

64

1.3 The p-n Junction and the Diode

pn (0) = pp0 · e−E0 /kT · e V / VT .

(1.3.2.13)

By eliminating E 0 from this equation (using (1.3.2.10)), the following expression is obtained pn (0) = pn0 · e V /VT .

(1.3.2.14)

The last expression gives the dependence of the concentration of minority carriers, in the N-region on the boundary of the p-n junction, as a function of the voltage connected externally and the concentration of minority carriers when this voltage is switched off. Equation (1.3.2.14) is often referred to as the law of the p-n junction. Example E.1.3.3 For a silicon p-n junction it is known: N D = 1015 cm−3 , N A = 1018 cm−3 . Determine the concentration of the minority carriers in the P-region before and after the application of a voltage V = 0.65·V 0 . Solution: Substitution in (1.2.3.32) gives: pn0 = ni 2 /N D = 2·105 cm−3 , while substitution in (1.3.2.14): pn (0) = 3.2·1013 cm−3 . Two comparisons are needed to evaluate the result we obtained. First, the value of the connected voltage is significantly less than the size of the barrier. Then, the magnitude of the concentration increased by more than 108 times. Therefore, under the action of the forward voltage, a significant injection occurs even at relatively low voltages, and the number of available carriers for conducting current becomes enormous. The dependence on the concentration of minority carriers in the N-region can now be completely determined. By substituting (1.3.2.14) into (1.3.2.8) one gets pn (x) − pn0 = pn0 (eV / VT − 1) · e−x/L p .

(1.3.2.15)

Using a similar procedure, we determine the dependence of the concentration of minority carriers in the P-region. n p (x) − n p0 = n p0 (eV /VT − 1) · e−x/L n .

(1.3.2.16)

By substituting the last two expressions in (1.3.2.3) and (1.3.2.4) we get ( Jnp (0) = ( Jpn (0) =

q Dp pn0 Lp q Dn n p0 Ln

) ( ) V · e VT − 1 ,

(1.3.2.17)

) ( ) V · e VT − 1 .

(1.3.2.18)

With respect to (1.3.2.1) the current density through a forward-biased semiconductor diode is

1.3.2 Semiconductor Diodes

65

( J=

q Dn n p0 q Dp pn0 + Lp Ln

) ( ) V · e VT − 1 .

(1.3.2.19)

The value 1/V T at room temperature (T = 300 K) is 1/V T ≈ 39 V−1 . This means that with increasing the polarization voltage V, for forward biasing, the current through the diode increases very rapidly according to the law e39·V ≈ 1016.8·V . If the surface of the p-n junction is S, the current through the diode is expressed as I = IS · (e V /VT − 1),

(1.3.2.20)

where (

Dn n p0 Dp pn0 + IS = q S Lp Ln

)

( =

q Sn 2i

) Dp Dn . + ND L p NA L n

(1.3.2.21a)

The resulting expression for the diode characteristic is usually called the diode model. It tells us what equation we will use to describe the diode when we write Kirchoff’s equations for the electrical circuit in which the diode is located. In inverse polarization, the current through the diode will be made up of minority carriers from the P-region—electrons, which will pass into the N-region, and holes from the N-region, which will pass into the P-region. When deriving the expression for the current, the whole procedure would be repeated and for inverse current the same expression (1.3.2.20) would be obtained with the difference that the voltage V is now negative. As, at room temperatures, 1/V T is a large number, even at low inverse voltages the inverse current is saturated (its value becomes constant). Thus, for example, for V = −0.1 V from (1.3.2.20) we get I = −0.98·I S . Therefore, for inverse voltages higher than 0.1 V, the inverse current can be expressed as Iinv = IS .

(1.3.2.22)

This current is called the inverse saturation current. Example E.1.3.4 Calculate the value of the inverse saturation current of the p-n junction (using (1.3.2.21)) if S = 1000 (μm)2 , q = 1.6·10–19 C, Dn = 20 cm2 /s, Dp = 10 cm2 /s, L n = 10 μm, L p = 5 μm, nn = N D = 5·1015 cm−3 , pp = N A = 1017 cm−3 and ni = 1.4·1010 cm−3 . Solution: After substitution in (1.3.2.21) one gets I S = 1.317·10−15 A. The theoretically derived characteristic of a semiconductor diode given in (1.3.2.20) deviates, although not much, from the experimentally obtained characteristic. The causes of this deviation lie mainly in two facts. First, in derivation (1.3.2.20) the effects of generating and recombination of free carriers in the depleted (transient) region of the junction were neglected, and then the voltage drop on the

66

1.3 The p-n Junction and the Diode

semiconductor body from the junction to the ohmic contact and on the ohmic contact itself was neglected, too. As for the correction of the model to simulate the breakdown one may say that the approximation of the breakdown characteristics is usually done by dividing I S by the function: f (V ) = (1 + V / VB )m ,

(1.3.3.21b)

where V B is the breakdown voltage, and m is the coefficient that represents a measure of the rate of increase of the collector current and is usually an even number, which in computer applications ensures that the current does not change sign after the breakdown. Otherwise, in manual calculations, the inverse voltage can never exceed the breakdown voltage since the current would exceed an infinite value. The breakdown voltage in (1.3.3.21b) is a positive number. In addition to significant deviations that occur in the breakdown region, for inverse biasing, the following can be observed. For the p-n junction, as shown in Example E.1.3.3, I S = 1.317· 10−15 A is obtained. This value is several thousand times less than the value that can be measured at an inverse voltage of 10 V. In addition, it can be experimentally determined that the inverse current increases linearly with increasing the inverse voltage which is not expressed in (1.3.2.20), so it can be concluded that in parallel with the junction there is a resistance through which a current flows that is much higher than the inverse saturation current. It is said that the current is leaking through the junction, i.e., that in parallel to the diode is connected a leaking resistance of the order of 1010 to 1012 u. The cause of this current is the generation and recombination of carriers in the depleted area (generation-recombination current). Since these are extremely small currents, the generation, and recombination due to defects of the crystal lattice (especially on the crystal surface) and due to contamination, come now to the fore (they become significant). Appropriate energy levels that appear in the energy gap facilitate both generation and recombination. In the case of forward biasing, deviations occur at low and at very high currents. In the case of germanium diodes, the current begins to increase noticeably only when the biasing voltage exceeds 0.2 V. This phenomenon is also noticeable in silicon diodes where this voltage is about 0.6 V. This voltage is directly related to the junction potential barrier and is larger for diodes made of materials with a wider band gap. The voltage when the diode begins to conduct significantly is called the cut-in voltage or the conduction threshold and is denoted by V γ . Deviations in small direct currents are a consequence of recombination in the transition region. It is understandable that the effect of recombination in small currents is much more pronounced than in large ones. In addition, since the inverse saturation current of a silicon diode is about a thousand times smaller than that of a germaniumyum diode, the effect of recombination in the transition region of a silicon diode is much more pronounced. In order to include this effect in the diode model, it is usual to modify the exponential term in (1.3.2.20) by replacing eqV/(kT ) with eqV /(ηkT ) , where is η = 1 for

1.3.2 Semiconductor Diodes

67

germanium diode and silicon diode at significant currents, and η = 2 for silicon diode at low currents. Finally, at very high currents, the voltage drop across the semiconductor body and the ohmic contact reduces the voltage drop at the junction itself. Thus, for a given voltage, the diode current is less than that which would be obtained from (1.3.2.20). This issue will be discussed in more detail later on.

1.3.2.2 Parameters of the Diode Here we will talk about electrical quantities that characterize the behavior of a semiconductor diode. The basic parameter of a diode is its inverse saturation current. The numerical value of the inverse current ranges from 10–8 to 10–2 mA for the germanium diode and from 10–12 to 10–6 mA for the silicon diode. Another parameter that is of great importance for the characterization of a diode is its resistance. We distinguish between static and dynamic resistance of the diode. Static resistance has no special technical significance and is defined as the quotient of the voltage on the diode and the current flowing through it as Rs =

V , I |V =VQ

(1.3.2.23a)

as depicted in Fig. 1.3.2.8a. The dependence of this resistance on the applied voltage (or on the diode current) is nonlinear. The dynamic or internal resistance of a semiconductor diode is defined for a given point on the characteristics (V Q , I Q ) in the following way rD = 1/

dI . dV |V =VQ

(1.3.2.23b)

This is also depicted in Fig. 1.3.2.8a. After substitution of (1.3.2.20) into (1.3.2.23) one gets rD =

VT kT = . q(I + IS ) I + IS

(1.3.2.24)

The dynamic resistance is a function of the diode current. For I >> I S (forward biasing) and room temperature, it can be expressed in numerical terms as rD =

1 VT = (u). I 39 · I

(1.3.2.25)

68

1.3 The p-n Junction and the Diode

Fig. 1.3.2.8 a Diode characteristic with a selected (working) point, its coordinates and its tangent and b Dependence of the dynamic resistance of a real diode (r D ) on the diode current

Thus, the internal resistance in direct biasing is a nonlinear function, i.e., it is inversely proportional to the current through the diode. In (1.3.2.25) the current is given in amperes, so it can be easily concluded that the internal resistance is of the order of ohms. So, for I = 26 mA it is r D = 1 u. In the case of a real diode, due to the deviation from (1.3.2.20), the dependence of the dynamic resistance on current (or voltage) is slightly changed. At very low currents (1.3.2.25) gives a very high resistance value so that the practical dynamic resistance is determined by the leakage resistance. At high currents (1.3.2.25) produces a resistance value almost equal to zero so that the dynamic resistance of the diode is determined by the resistance of the ohmic contacts and the body of the semiconductor from the junction to contact. A typical measured dependence of the dynamic diode resistance on current is shown in Fig. 1.3.2.8b.

1.3.2.3 Temperature Dependence of the Diode Characteristic Equation (1.3.2.20) shows that the characteristic of the diode also depends on the junction temperature. In order to find the explicit dependence, combining (1.2.3.22), (1.2.3.31), and (1.2.3.34), respectively, one gets

1.3.2 Semiconductor Diodes

69

pn0 = n 2i /ND ,

(1.3.2.26)

n p0 = n 2i /NA .

(1.3.2.27)

and

Substituting these expressions in (1.3.2.20) gives ( I =

q Sn 2i

Dp Dn + L p ND L n NA

)

· (e V / VT − 1).

(1.3.2.28)

The temperature dependence of ni 2 is obtained from (1.2.3.21). Using it (1.3.2.28) becomes ( I = qS

Dp Dn + L p ND L n NA

)

( ·4

2πmkT h2

)3

·e−Eg /(kT ) · (e V / VT − 1).

(1.3.2.29)

where for simplicity one uses mn mp = m2 . Having in mind the temperature dependence of the mobility, Einstein’s relation, and the expression for the diffusion length, it is assumed that the quotient of the diffusion constant and the diffusion length is inversely proportional to the temperature, so the characteristic is rewritten as I = A · T 2 e−Eg /(kT ) (e V / VT − 1).

(1.3.2.30)

The constant A no longer depends on the temperature. By analyzing this relation, we conclude that, at a constant voltage, the first two factors that make it up, contribute to the increase of current with increasing temperature, and the third contributes to the decrease of current with increasing temperature. First of all, the current increases with the square of the temperature. This factor is multiplied by the second that contributes to the exponential growth of the current. In this part, the exponent is negative, and its absolute value decreases with increasing temperature both due to the decrease in the size of the energy gap and because we have the temperature in the denominator of the exponent. Finally, as for the third contributor, the exponent in eV / VT decreases with increasing temperature because V T = (kT/q) increases with increasing temperature. However, the first two factors (contributors) have a dominant influence, so the overall effect is that the diode current increases with increasing temperature. This is quantitatively shown in Fig. 1.3.2.9 (generated by SPICE simulation). The temperature coefficient of the diode current is said to be positive. Otherwise, this is a property of all bipolar components. The positive temperature coefficient of the diode current is quantitatively expressed indirectly through the temperature dependence of the inverse saturation current and through the temperature dependence of the voltage on the diode at constant current.

70

1.3 The p-n Junction and the Diode

Fig. 1.3.2.9 Temperature dependence of the diode characteristic. (a) current as a function of voltage for two temperatures (generated by SPICE) and (b) inverse saturation current as a function of temperature

For inverse polarization, very soon it becomes |V| >> V T so it is −I = IS = A · T 2 e−Eg /(kT ) .

(1.3.2.31)

For the practical values of the constant A, it is obtained that the inverse saturation current is doubled when the temperature changes by /\T = 10 K. The dependence of the I S on the temperature for one diode, in a logarithmic scale, is shown in Fig. 1.3.2.9b. Example E.1.3.5 Using the approximation that the inverse saturation current of the p-n junction doubles with increasing temperature by 10 K, approximately determine the value of the inverse current of the p-n junction at T = 77 °C, if at T = 27 °C it was I S (27 °C) = 0.2 pA. Then approximately determine the increment of the diode current if the diode voltage is constant V = 0.65 V. Assume that (kT/q)|T=27 °C = 0.026 V.

1.3.2 Semiconductor Diodes

71

Solution: Since /\T = 50 K, the inverse saturation current increases by 250/10 = 25 times and becomes I S (77 °C) = 25 ·0.2 = 6.4 pA. By substituting into (1.3.2.20) one gets I(27 °C) = 14.4 mA and I(77 °C) = 16.4 mA which gives /\I = 2 mA. Let us now consider forward biasing. From (1.3.2.30), if it is assumed that the current is constant, and if the voltage is differentiated with respect to the temperature, the sensitivity of the forward biasing voltage to changes in temperature is obtained as dV ≈ −2.5 mV/K. dT |I =C te

(1.3.2.32)

The negative sign on the right-hand side of the last expression indicates the fact that when the diode current is kept constant, the voltage decreases with increasing temperature. Numerical values for the rates of change of the inverse saturation current and voltage on the diode with temperature change, which are given here, represent the average values for germanium and silicon diodes and are calculated for room temperature (T = 300 K). The general conclusion is that due to the increase in temperature, the current through the diode increases. The temperature coefficient of the diode current is said to be positive.

1.3.2.4 Limitations in the Use of the Diode When working with a diode, a certain power is dissipated (consumed). It is equal to the product of the voltage and current of the diode: pd = v · i.

(1.3.2.33)

The diode through which the current flows acts as a heat source. This means that, due to the release of heat on the diode, the temperature of the diode rises. An increase in temperature leads to an increase in current and, at constant voltage, to an increase in dissipation. Therefore, the process of self-heating of the diode is possible due to the positive temperature coefficient of the current. This process will stop at a temperature at which the heat given off to the environment becomes equal to the newly generated heat. If we denote the ambient temperature by T 0 , and the temperature of the junction by T J , we can write TJ − T0 = Rth Pd ,

(1.3.2.34)

where Pd is the mean value of the power, and Rth is the coefficient of proportionality called thermal resistance. Rth is a measure of the increase in junction temperature

72

1.3 The p-n Junction and the Diode

relative to the ambient temperature for a given dissipation and is expressed in K/W. This expression is graphically illustrated in Fig. E.1.3.6a. For a given ambient temperature (for example, the equipment in which the diode will be located operates at a temperature of T 0 = 350 K) at a given thermal resistance, there is a maximum value of dissipation at which maximum junction temperature is reached: TJ

max

− T0 = Rth Pd max ,

(1.3.2.35)

The maximum junction temperature was determined in terms of previous considerations of the temperature dependence of ni , i.e., based on (1.2.3.39). From (1.3.2.35) we conclude that the higher the ambient temperature (where the diode will be installed), the lower the maximum power that can be dissipated on the diode will be. Therefore, in situations where high power is required, special cooling measures are applied, which reduces Rth . Example E.1.3.6 Based on (1.3.2.35) determine the maximum dissipation of the diode for the values of ambient temperature and thermal resistances given in the first two columns of Table T.E.1.3.6. The maximum temperature of the component is T j max = 160 °C. Solution: Figure E.1.3.6b depicts the relation (1.3.2.35), which is rewritten as Pd max = (T J max -T 0 )/Rth , for two values of Rth . For a selected ambient temperature T 0 a two values of Pd max are found defined by two values of Rth . When this procedure is repeated for each temperature from Table T.E.1.3.6, the values given in the last column of Table T.E.1.3.6 are obtained. We notice that depending on the environment in which the component will work and the method of cooling, the value of the maximum dissipation of the same component can vary in a very wide range. The next limitation of the diode is the maximum current. This restriction mainly refers to the current that can be withstood by the electrical conductors (bonds) that Fig. E.1.3.6 a Dependence of junction temperature on dissipation and b graphical determination of maximum dissipation for selected ambient temperature (T0 a ) and for two values of thermal resistance (Rth 1 and Rth 2 )

1.3.2 Semiconductor Diodes Table T.E.1.3.6 Xxx

73 T 0 (o C)

Rth (K/W)

Pd max (W)

−30

10

19

0

10

16

30

10

13

60

10

10

90

10

7

−30

1000

0.19

0

1000

0.16

30

1000

0.13

60

1000

0.10

90

1000

0.7

connect the metal contact to the external conductors (wires). Namely, bonds act as fuses so that when a proper current is exceeded, the diode is permanently damaged (bonds are interrupted-melted). Another limitation in the operation of the diode is the maximum inverse voltage, which is the subject of further discussion in this section. At high inverse voltages there is a sharp increase in inverse current as shown in Fig. 1.3.2.5 in the characteristic of a real diode. This area is characterized by large changes in current with very small changes in diode voltage. In other words, the voltage across the diode is approximately constant with respect to changes in the diode current. This area of the characteristic is called the breakdown area. The breakdown occurs because the carriers, which make up the inverse current, get a large amount of energy in the transition region due to the fact that the electric field at the transition is large. For example, for a junction width of one micron and a total inverse voltage of only 1 V, the electric field is 106 V/m. When the inverse voltage on the diode reaches a certain value the primary electrons, in collisions with the atom of the crystal lattice, generate new ones. There is a so-called impact ionization. The increased number of free carriers further accelerates and collides with the atoms in the crystal lattice causing a new increase in the number of charge carriers. The process is repeated and there is a sudden multiplication of the carriers or a sudden increase in current, which, in fact, is a breakdown. This phenomenon is referred to as avalanche breakdown. The multiplication of free carriers is facilitated by the fact that a large voltage acts on the transition region so that as the current increases, the total energy consumed to heat the junction (dissipation at the junction) increases. This results in an increase in the junction temperature, which in turn results in the breaking of covalent bonds and generation of free carriers in the transition region, and thus an increase in the electric current through the junction. Higher inverse current also means higher dissipation at the junction, i.e., higher junction temperature. This phenomenon is referred to as thermal breakdown. The avalanche and thermal effects work in synergy, resulting in a sudden increase in current. It is clear, however, that the breakdown in the initial

74

1.3 The p-n Junction and the Diode

part has an avalanche character because, in the beginning, the current is too small to cause a thermal breakdown. It should be noted that the breakdown is cumulative. When it starts with an increase in the number of free carriers in the transition area, that increase results in a new increase in free carriers, and so on. This explains the fact that when the breakdown starts, it is not necessary to further increase the inverse voltage on the diode in order to increase the current so that this voltage remains practically constant. If the diode current is not limited by, for example, external resistance, the cumulative increase in current will result in too high a junction temperature so that the component will break down i.e., become permanently destroyed. In the following text, a simplified theory of determining the breakdown voltage of a p-n junction will be given. It will be considered that the p-n junction is made in the form of a junction of two plates of unlimited area, which means that there will be no talk of edge effects. This analysis will be also used to draw some other conclusions that are important for understanding the operation of diodes and other electronic components. The maximum electric field that can exist at the p-n junction K B , i.e., the field at which an avalanche breakdown occurs, is related to the energy of the energy gap by the relation q K Bl = E g ,

(1.3.2.36)

where l is the mean length of the path between two collisions. This equation shows the equality of the electron energy between two collisions and the energy of the energy gap. If the width of the depleted region is w, and V B is the maximum inverse voltage (voltage at which the breakdown begins) at the junction, then it will be VB = K B w.

(1.3.2.37)

By combining the last two equations, we get VB = wE g /ql.

(1.3.2.38)

The last equation shows that the breakdown voltage is proportional to the width of the energy gap. Therefore, silicon diodes, since their energy gap is larger, will have a higher maximum breakdown voltage than the corresponding germanium ones. To accurately determine the value of the breakdown voltage, it is necessary to determine the width of the transition region w which is equal to the sum of the widths of the parts of the transition region in the P- and N-region: w = wp + wn . To this end, for the transition region, the Poisson equation

(1.3.2.39)

1.3.2 Semiconductor Diodes

75

d2 0 Q =− dx 2 ε

(1.3.2.40)

needs to be solved. It relates the electrical potential and the density of space charge. In (1.3.2.40) 0 stands for the potential, Q for the density of space charge, and ε is the dielectric constant of the semiconductor. For a p-n junction with an abrupt concentration change (left-hand side of Fig. 1.3.1.1b) (1.3.2.40) can be rewritten in the form d2 0 q NA for x ≤ 0 (P-region), = 2 dx ε

(1.3.2.41)

d2 0 q ND for x ≥ 0 (N-region). =− 2 dx ε

(1.3.2.42)

and

In the first step of integration of these equations, we have in mind the boundary condition that the electric field (d0/dx) for x = −wp and x = wn is equal to zero as depicted in Fig. 1.3.1.1c. After the first integration, the electric field in the transition region is obtained as −K =

) q NA ( d0 = x + wp for x ≤ 0, dx ε

(1.3.2.43)

−K =

q ND d0 = (x − wn ) for x ≥ 0. dx ε

(1.3.2.44)

and

Equating the last two equations and putting x = 0 gives an important relation wp ND = , wn NA

(1.3.2.45)

which shows that the widths of the parts of the transition region in the P- and N-region are inversely proportional to the concentrations of the corresponding impurities in the N- and P-region. Where the concentration of the majority carriers is higher, the part of the width of the depleted area is smaller. This result is quite natural since, due to the electrical balance, it is necessary that the space charge on both sides of the junction is equal. The relation (1.3.2.45) is illustrated in Fig. 1.3.2.10a. In this picture N A > N D so it is wp < wn . In the special case when N A >> N D (or vice versa) then wp | | > || || . | dx | dx |t=t2 dx |t=t3 |t=t1

(1.3.2.59)

With this in mind, the substitution in (1.3.2.3) gives: Jpn |t=t1 > Jpn |t=t2 > Jpn |t=t3 .

(1.3.2.60)

The time dependence of the diode current is shown in Fig. 1.3.2.12d. Observing this dependence, one can notice the similarity of the waveform with one of the Fig. 1.3.2.12 Diffusion capacitance. a barrier at the junction, b circuit diagram with diode and switch, c concentration of minority carriers as a function of distance and time d current as a function of time, e RC branch that exhibits equal waveform, and f recovery time

D

i(t)

v(t) E0/q

Rg

V a

Vg

t0

b pn(0)

pn(x,t)

t1< t2< t3 pn0

c

i(t)

R

x

i(t)

Rg I t0

C

Vg d

e

t i(t) I

Ir

trr t0

f t

84

1.3 The p-n Junction and the Diode

current of a parallel RC circuit to which the same excitation was applied (depicted in Fig. 1.3.2.12e). This leads to the conclusion that a capacitor acts in parallel with the diode. The capacitance of this capacitor is called diffusion capacitance, which is quite natural considering the causes that underlie the phenomenon it represents. The numerical value of this capacitance can be determined on the basis of the dependence of the injected charge of minority carriers Qp in the N-region: Cdp =

d Qp . dV

(1.3.2.61)

The dependence Qp (V ) is obtained in the following way. When the voltage is applied to the junction, a new dependence on the concentration of the minority carriers is established. The magnitude of the injected charge is proportional to the area (in Fig. 1.3.2.12c) between the old and the new concentration (the old concentration is pn0 ). This area, i.e., injected concentration, is calculated from the expression {∞ Q p = S {q · [ pn (x) − pn0 ]} · d x.

(1.3.2.62)

0

Having in mind that the subintegral function is given by (1.3.2.15) the last expression is easily integrated: Q p = q Spn0 L p (e V / VT − 1).

(1.3.2.63)

Now for the diffusion capacitance of the holes in the N-region we have Cdp =

q 2 S · pn0 L p V / VT e . kT

(1.3.2.64)

The diffusion capacitance of electrons in the P-region is obtained by an identical procedure to be: Cdn =

q 2 S · n p0 L n V / VT e . kT

(1.3.2.65)

The total diffusion capacitance is obtained by summing these two components, so we have Cd = Cdp + Cdn =

) qS ( pn0 L p + n p0 L n eV /VT = Cd0 eV / VT . VT

(1.3.2.66)

Considering (1.3.2.20) the diffusion capacitance can also be expressed through the current of the p-n junction as:

1.3.2 Semiconductor Diodes

Cd =

85

) qS ( n p0 L n + pn0 L p · (1 + I /IS ) VT = Cd0 (1 + I /IS ) ≈ Cd0 (I /IS ).

(1.3.2.67)

Based on (1.3.2.66) and (1.3.2.67), we conclude that the diffusion capacitance is an exponential function of the voltage at the junction, i.e., that it is linearly dependent on the junction’s current. Example E.1.3.10 For a junction with N A = 1017 cm−3 , N D = 1015 cm−3 , τn = 103 μs, and τp = 40 μs find C d0 /S (diffusion capacitance at zero voltage per unit area), then find C d0 if S = (50 μm)·(50 μm) and, finally, find C d (0.65 V). Solution: One gets C d0 /S = 0.23 pF/cm2 = 0.23·10–8 F/m2 = 0.23·10–8 pF/(μm)2 . When this number is multiplied by the surface, we get C d0 = 5.75·10–8 pF. Extremely low capacitance! This means that the value of diffusion capacitance comes to the fore only at relatively high forward voltages. So, C d (0.65 V) = 6120 pF. It should be borne in mind, of course, that then the very small dynamic resistance of the junction acts in parallel with it so that this capacitance is bridged (almost short-circuited). To end, do compare C d (0.65) from this and C t (0.65) from the previous example. The difference is immense. If we suppose that V >> V T using (1.3.2.21) and (1.2.3.86) under the condition τn = τp = τ (the lifetime of electrons and holes as minority carriers is not equal, but here this condition helps us to come to the appropriate general conclusion), (1.3.2.67) becomes transformed into Cd =

τ I. VT

(1.3.2.68)

This expression indicates that materials with a short lifetime exhibit very low diffusion capacitance. In diodes where the body of the semiconductor is short (shorter than the corresponding diffusion length so that the concentration of the minority carriers does not fall to their equilibrium concentrations), the limit of the integral in (1.3.2.62) does not go to infinity, so in (1.3.2.68) instead of the lifetime, the transit time of the minority carriers from the junction boundary to the ohmic contact should be put. The following approximate expression turns out to be valid: τd = τ · [ch(w/L) − 1],

(1.3.2.69)

where τd is the transit time and L is the diffusion length of the minority carriers on the diode side where the majority carrier concentration is lower. The importance of the diffusion capacitance is most often expressed through a quantity called the diode recovery time and denoted by t rr (from: reverse recovery). Namely, during forward biasing, there is a large mobile charge of minority carriers in the body of the semiconductor on both sides of the junction. If we now wanted to

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1.3 The p-n Junction and the Diode

change the polarization of the diode from forward to backward, ideally, we would expect the diode to be immediately transferred from conducting state into a nonconducting state. In order to neutralize the large mobile charge, however, the diode current will have to be large and negative for some time. The magnitude of the current will depend on the external circuit, and the diode itself will act as a short circuit. When the mobile charge is neutralized, this current will disappear. The process is equivalent to the discharge of diffusion capacitance and is illustrated in Fig. 1.3.2.12f. It can be seen that the phenomenon is even more complex than we have described. Finally, let us recall once again that the capacitance values of the p-n junction depend on the values of the voltage at the junction and the current through the junction. Such capacitances are called nonlinear capacitances. Since the reader encounters such elements for the first time, we will recall the analogy of these elements with nonlinear resistive two-terminal elements (p-n junction in stationary mode) and nonlinear inductances (inductors with an iron core where the magnetization curve is not linear). As we will see later, when analyzing circuits with such capacitances, for small alternating signals, the numerical value of the capacitance is taken which is determined by the DC (steady) component of the signal.

1.3.2.6 Summary of the Diode Ratings For the implementation of a diode in some circuits one should select among so many available on the market. The choice is impossible if no criteria are established. To that end a set of diode parameters and ratings are usually reported by the producers and often cited in books. Use of the internet, however, is preferable as a source of information on component specifications because all the data obtained from manufacturer websites are (most probably) up-to-date. We will list below some typical diode parameters listed in a datasheet. Abbreviations will be given as usually found in datasheets. Maximum repetitive inverse voltage (V RRM ) is the maximum amplitude of the voltage pulse train the diode can withstand when backward biased. Maximum DC inverse voltage (V R or V B ) is the maximum amount of voltage the diode can withstand before breakdown. Maximum forward voltage (V F ) is usually specified according to the diode’s rated forward current. Maximum (average) forward current (I F AV ) is the maximum average value of the diode current when forward-biased. Maximum (peak or surge) forward current (I FSM or I F(surge) ), the maximum peak value of the diode current when forward biased.

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Maximum total dissipation (PD max ) is the maximum power allowable to be dissipated at the diode. Maximum junction temperature (T J max ) is the maximum allowable temperature for the diode’s p-n junction. Maximum/minimum storage temperature (T STG ) is the range of allowable temperatures for storing a diode. For example, during storage and especially transportation (delivery) the component faces different ambient (storage) temperatures which may range down to −55 °C (in a container loaded at a flying plane) or up to 120 °C (in a container loaded at a truck running through a desert). Since, however, there is no internal dissipation the maximum storage temperature will usually be larger than the maximum operating temperature. Here the reader should be aware that a semiconductor component is a complex structure built in layers of different materials (such as silicon, silicon oxide, nitrogen oxide, aluminium, etc.) These layers have different dilatation coefficients and, even if there is no current, at very low and very high temperatures one may expect large strain between the layers and potential damage to the component. Thermal resistance (Rth ) is a measure of the rise of the junction temperature as compared with the ambient temperature for a given dissipation. It is expressed in o C/W. Ideally, this figure would be zero, meaning that the diode package was a perfect thermal conductor and radiator, able to transfer all heat energy from the junction to the outside air (or to the leads) with no difference in temperature across the thickness of the diode package. A large value of Rth will lead to the rise of the junction temperature despite the investments done for cooling. In other words, to protect the diode the undertaken cooling may be not enough. Maximum reverse current (I R max ) is the inverse current of a diode under the maximum rated inverse voltage (V DC max). Sometimes it is referred to as leakage current. Its value should be as small as possible so enabling the blocking behavior of the diode at backward biasing. Generally, it is much smaller than the forward current and is in the range of nA. Junction capacitance (C t ) is the value of the junction capacitance at moderate inverse voltages (mostly given for zero bias). Its value varies largely depending on the type (application) of the diode. A germanium switching diode may have a capacitance less than pF while the solar cell may go up to several nF. Inverse recovery time (t rr ) is the time needed for a forward-biased diode to switch off at a sudden change of the biasing voltage from forward to backward. It is related to the diode’s diffusion capacitance and, similarly to the case of C t , fast switching diodes may have as a small t rr as in the range of ns, while rectifying diodes will need μs to recover. Since almost all of these parameters are temperature dependent a single number is not enough to completely describe the rating under consideration. That is why manufacturers (in their datasheets) usually provide for diagrams expressing these ratings as a function of temperature (and other variables). In that way, as we can see,

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1.3 The p-n Junction and the Diode

establishing the right rating for a component is a task involving a serious study of the design under consideration.

1.3.2.7 Varicap Diode The property of nonlinear capacitances to change their value as a function of the applied voltage was used for the construction of a special component called a varicap diode (varactor, voltacap). A schematic symbol of the varicap diode is given in Fig. 1.3.2.13. In order to ensure that this component, by its nature, is as close as possible to the pure capacitance, it is necessary to keep the resistance of the diode as high as possible. Therefore, the normal mode of operation of this diode is backward biasing. In this case, the value of the resistance of the component is of the order of 1 Mu and more. For small alternating components (increments) of the signal that are superimposed on the DC bias, the diode behaves as pure capacitance since the reactance of the capacitor is much lower than the resistance of the junction. If we keep in mind what has been said above, we can easily conclude that the junction capacitance is of primary importance in this diode. A typically measured dependence of the capacitance of this kind of a diode as a function of the inverse voltage is shown in Fig. 1.3.2.14 and it qualitatively fits the expression (1.3.2.58). Fig. 1.3.2.13 Varicap diode, schematic symbol

Fig. 1.3.2.14 Example dependence of the capacitance of a varicap diode as a function of the inverse voltage

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Fig. 1.3.2.15 Resonant circuit whose resonant frequency is controlled by the voltage V. C serves as a DC isolation for L 0 and L isolates the AC signal from the DC source V. RF stands for radio frequency

The varicap diode can be used in all circuits where a change in capacitance as a function of external voltage is required and especially in circuits where the resonant frequency of the resonant circuit of which the varicap diode is a part can be changed. One such circuit is shown in Fig. 1.3.2.15. This is a resonant circuit with a variable resonant frequency controlled by an external DC voltage. Namely, since the capacitance C is infinite, for the alternating component of the signal coming from the right-hand side, the diode is connected in parallel with the capacitor (C 0 ) of the resonant √ circuit so that the resonant frequency of the circuit is given by f 0 = 1/[2π L 0 (C0 + Ct )]. In this case, C t is a function of the DC voltage V supplied through the coil L of infinite inductance. This coil represents infinite impedance for the alternating signal and thus separates it from the battery (Otherwise the RF signal would be short-circuited by the battery). By changing V, the resonant frequency of the circuit also changes. More on the application of varicap diodes will be in LNAE_Book 3 which is related to linear oscillators.

1.3.2.8 Tunnel Diode When discussing the breakdown voltage we have shown that with increasing concentration of main carriers on both sides of the p-n junction, the maximum inverse voltage (the breakdown voltage) decreases. It is possible that at a very high impurity content (103 :1) the maximum inverse voltage to become zero, i.e., that for inverse voltages, practically, the diode is a short circuit. This phenomenon is explained by the use of the laws of quantum mechanics and the mechanism of tunneling, so diodes that have such characteristics are called tunnel diodes. The characteristic of a germanium tunnel diode is shown in Fig. 1.3.2.16. On the characteristic, in part A-B, the dynamic resistance of the tunnel diode is negative. Due to the negative dynamic resistance, the tunnel diode is used in pulse circuits for fast switches, for oscillators at high frequencies, and the like. Example E.1.3.11 The diode whose characteristic is depicted in Fig. 1.3.2.16 is built into the circuit of Fig. E.1.3.11a. It is known that ig = 0.6 mA and R = 1.5 ku.

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1.3 The p-n Junction and the Diode

Fig. 1.3.2.16 Characteristic of a tunnel diode

Using graphic analysis find the possible values of the voltage and the current of the diode. Solution: We first write down the node equation: v + i = ig . R

(E.1.3.11.1)

This line is drawn together with the diode characteristic in Fig. E.1.3.11b. There are three intersection points (marked by Q) which represent three possible solutions for diode voltage and current. Which of these three solutions will occur in the circuit will depend on the value of the voltage on the diode at the time of switching on. Since in this example the circuit is purely resistive, at the moment of switching on all voltages are equal to zero, the solution will be the point with the smallest abscissa: (v ≈ 0.045 V, i ≈ 0.55 mA). In the following text, an attempt will be made to explain the mechanisms underlying the characteristics of this type of diode. Due to the high content of impurities, the Fermi level in the P-type of the semiconductor is significantly shifted in relation to the Fermi level in the N-type. Since in the p-n junction this level should be constant, there are significant shifts in the boundaries of the conduction and valence bands in the P- and N-regions. It can happen that the lower limit of the conduction band in the P-domain has less energy than the upper limit of the valence band in the N-region. Now charge carriers from one band can pass through the junction into the energy levels of the other band, freely, without exchanging energy. The passage of free charge carriers through a potential

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v

ig

i

I [mA] 1

D

R

a

Q

A

C

0.8 0.6 0.4

b

-0.2 -0.1

B

0.1 0.2 0.3 0.4 0.5 0.6 V [V] -0.4 -0.6 Fig. E.1.3.11 a Simple circuit with tunnel diode and b graphic analysis

barrier without exchanging energy is called tunneling. Figure 1.3.2.17 illustrates this phenomenon using the energy bands for a tunnel diode without externally connected voltage (a) and in the case of backward biasing (b).

Fig. 1.3.2.17 a Energy band diagram of an unbiased p-n junction and b Energy band diagram of a backward biased p-n junction (with degenerated semiconductors on both sides in both cases). The green arrow shows the movement of electrons

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1.3 The p-n Junction and the Diode

In Fig. 1.3.2.17a the Fermi level is in the valence band in P-type semiconductors and in the conduction band in N-type. No voltage is connected from the outside. In backward biasing when the voltage is negative on the P-region, the Fermi level of the P-region is shifted relative to the Fermi level of the N-region as shown in Fig. 1.3.2.17b. Now electrons (minority carriers) from the P-region can tunnel into the N-region through a potential barrier without exchanging energy. The current through the tunnel diode, in these conditions, is large and is limited by the external circuit. In the case of forward biasing of a p-n junction making a tunnel diode, with an increase in the biasing voltage, the energy levels change successively in the manner shown in Fig. 1.3.2.18. At low bias voltages (Fig. 1.3.2.18a) there will be small changes in energy levels that are opposite to those for inverse voltages. Now electrons from the N-region pass through the barrier in the P-region without exchanging energy. The total current of the p-n junction is equal to the sum of the tunneling current and the normal diffusion current through the p-n junction corresponding to forward biasing.

Fig. 1.3.2.18 Variation of energy levels of the tunnel diode depending on the biasing voltage

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In the initial part of the characteristic (branch 0-A-B of Fig. 1.3.2.17) the tunnel current prevails because for small voltages the diffusion current is small. One can see from Figs. 1.3.2.18 and 1.3.2.16 that in the region of voltages at which the internal resistance of the tunnel diode is negative, the diffusion current of the p-n junction is practically equal to zero. So the current of the tunnel diode reaches its maximum (point A on the characteristic) when the distribution of energy levels corresponds to that in Fig. 1.3.2.18b. Then, most of the free electrons can tunnel through the barrier. With further increase of the forward biasing voltage, the current of the p-n junction begins to decrease because, according to Fig. 1.3.2.18c, the energy bands between which tunneling occurs are reduced. Part A-B on the characteristic of a diode with negative resistance corresponds to this phenomenon. Finally, according to Fig. 1.3.2.18d, the occurrence of tunneling ceases because the energies of the upper limit of the valence band of the P-region and the lower limit of the conduction band of the N-region no longer overlap. However, the diode current continues to grow in the region B-C and, in that region, the characteristics of the tunnel diode from Fig. 1.3.2.16 coincides with the characteristic of the ordinary diode with p-n junction. This is because the current of the tunnel diode, in this case, is made up only of the diffusion component. A schematic symbol of the tunnel diode is given in Fig. 1.3.2.19. Germanium, silicon, or gallium-arsenide are most commonly used as semiconductor materials for the production of tunnel diodes, although other materials are not excluded. Let us now consider in a little more detail the most important feature of a tunnel diode: the property of exhibiting negative resistance. First, to understand the meaning of negative resistance, we will consider the following example. Example E.1.3.12 The current i in the circuit of Fig. E.1.3.12 is negative. In other words, the resistance that loads the battery is negative. What is inside the black box that loads the battery? Solution: In order for the current to be negative, it is necessary to have a battery in the black box whose voltage is higher than V g . Therefore, if the quotient v/i is negative, we are talking about an energy source. Of course, the same goes for the negative dynamic resistance dv/di. The negative resistance is an energy source and vice versa. According to this conclusion, if the operating point (Q) of the tunnel diode is brought to the part of the characteristic where the slope is negative, it will act as a source. It is said that the circuit will have regenerative properties. These negative Fig. 1.3.2.19 Schematic symbol for tunnel diode

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1.3 The p-n Junction and the Diode

v

Fig. E.1.3.12 Illustration of negative resistance

i Vg

Black box

resistance properties are used in signal-generating circuits. In them, DC voltage or current (ig in the circuit with Fig. E.1.3.11a) is used to generate time-varying signals that have a periodic character.

1.3.2.9 Zener Diode The normal mode of operation of a Zener diode is the inverse polarization in the breakdown region. The dynamic resistance of the diode in this area is very low. This means that for small increments in the diode voltage, large alternating currents are obtained, i.e., the voltage on the diode remains practically constant even with significant changes in the diode current. Therefore, this diode is used to stabilize a voltage and obtaining reference DC voltages. With the change of impurity concentrations, the maximum inverse voltage can be changed in a wide range from a few volts to a few hundred volts. However, Zener diodes are most often produced for voltages from −2 to −12 V because the characteristics of diodes with these values of the breakdown voltages are the steepest, i.e., these diodes have the lowest dynamic resistance. This feature is shown in Fig. 1.3.2.20 for eight different diodes. The characteristics in the forward biasing practically coincides for all these diodes. The horizontal dashed line in Fig. 1.3.2.20 states that the question of when the breakdown occurred is open. Namely, it is considered here that the breakdown occurred when the diode current exceeded 5 mA. It is a matter of the diode user and the properties of the diode itself. Therefore, as we will see later, for the same diode another value can be adopted as the breakdown voltage, although not very different. The same figure shows the schematic symbol for the Zener diode. The breakdown of the Zener diode is controlled by a mechanism that has not been discussed so far, so the necessary attention will be paid to that phenomenon first. Namely, since the concentration of impurities is very high at low backward voltages, along with the avalanche breakdown, the so-called Zener’s breakdown occurs. It is formed under the influence of a very strong electric field in the transition region, which can be up to 108 V/m at high concentrations. Electrons in valence bonds, subjected to such a strong field, break valence bonds and generate a pair of electron and hole. Roughly speaking, the electric field in which atoms of the space charge

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95

Fig. 1.3.2.20 a Characteristics of a set of Zener diodes and b schematic symbol

region are located strips electrons from atoms. This phenomenon is expressed in diodes that have a very high concentration of majority carriers on both sides of the junction and the corresponding breakdown voltages are below 6 V. In such diodes, the avalanche effect is predominantly determined by the Zener effect. Diodes with a slightly lower concentration of majority carriers are dominated by avalanche breakdown based on impact ionization (which is higher than 6 V). Given the purpose of these diodes, it is important to know the temperature dependence of the breakdown (reference) voltage of the diode. This dependence can be roughly represented by a linear law: Vz (T ) = Vz (T0 ) + αz (T − T0 ),

(1.3.2.70)

where αz = ∂V z /∂T is the temperature coefficient [V/K]. The temperature coefficient is different for different diodes, i.e., it depends on the value of the breakdown voltage of the diode. This dependence is given in Fig. 1.3.2.21 where the current through the Zener diode, for which the temperature coefficient is determined, is constant. The figure shows the value of the relative temperature coefficient α ' z (in percentage per Kelvin). This is its definition: '

αz =

% αz · 100 . Vz K

(1.3.2.71)

It can be easily noticed that, for Zener diodes whose breakdown voltage is around 6 V, the temperature coefficient is almost equal to zero. For higher voltages it is positive and for lower voltages it is negative. Here is the explanation. At lower breakdown voltages, the Zener breakdown dominates. As the temperature increases, the energy of valence electrons also increases, so it is easier to break valence bonds under the influence of an electric field. In other

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1.3 The p-n Junction and the Diode

Fig. 1.3.2.21 Dependence of the relative temperature coefficient on the value of breakdown voltage (every point on the x-axis represents a separate diode)

words, for a given value of the current, at higher temperatures, the smaller electric field is needed, i.e., lower inverse voltage. Therefore, for voltages less than 6 V, the temperature coefficient is negative and the breakdown voltage decreases with increasing temperature. At inverse voltages higher than 6 V, avalanche breakdown predominates. As the temperature rises, so do the thermal vibrations of the lattice (vibrations of the atoms in the lattice). Therefore, the mean path length between two collisions l decreases since the scattering on the crystal lattice is more intensive. This, according to (1.3.2.38), leads to an increase in breakdown voltage. It is theoretically possible to make a Zener diode with a temperature coefficient equal to zero. Practically, the so-called reference Zener diodes used in reference voltage sources may have temperature coefficients of α ' z ≈0.001% / K in a very wide temperature range, and with a dynamic internal resistance of r D ≈ 1 u. It should be noted that the voltage stability on these diodes is comparable to the stability of a standard battery. Example E.1.3.13 For a Zener diode whose breakdown voltage is V z = 10 V, determine the breakdown voltage increment if the diode temperature changes by /\T = 20 K. Solution: We read from the diagram of Fig. 1.3.2.21 (at the current of 1 mA) the value of the relative temperature coefficient to be α’z = 0.05%/K. After substitution of αz = /\V z //\T into (1.3.2.71) and solving for /\V z , one gets /\Vz =

α ' z · /\T · Vz = 100 mV. 100

The question remains whether the value obtained is a small or large increment. When considering the answer to this question, we should first compare the obtained increment with the voltage V z . The increment is 100 times less than the value of the voltage and from that point of view it can be considered small. A comparison

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97

with the magnitude of the signals processed in electronic circuits such as the signal generated in the microphone or other converters, however, does not lead to such an optimistic conclusion. Namely, the amplitudes of these signals are of the order of several millivolts while the increment /\V z = 100 mV is much larger and therefore it is usually unacceptable. According to this logic, in order to obtain better temperature stability, it is sometimes better to connect in series two Zener diodes whose breakdown voltages are half of the targeted.

1.3.2.10 Metal–Semiconductor Contact and Schottky Diode Each practical component contains a metal–semiconductor contact so that it plays a significant role in the functionality of all of them. Even the simplest component—the diode—has two contacts, and only one p-n junction, which speaks of the number of contacts in electronics. Making contact with the desired characteristics is not a simple problem as contact is a special type of junction that has specific conductive properties. Contact properties can be clarified by considering energy bands at the boundary. The basis for these considerations is the fact that the Fermi levels on both sides of the junction are equal. The Fermi level in conductors is within the conduction band. Having in mind the energy distribution of electrons (1.2.3.4), we conclude that at room temperature relatively few electrons have an energy higher than E f . Therefore, it can be considered that E f is the energy of the electron with the highest energy in the metal. In order for such an electron to leave the metal, an energy E M = q·ϕM (where ϕM is the corresponding potential) must be added to it. This energy is referred to as the work function of the metal. In semiconductors, the Fermi level is in the energy gap, so the work function for silicon is E Si = q·ϕSi . Since, however, there are no free electrons in the energy gap (between the Fermi level and the bottom of the conduction band) of interest is the energy that will transfer the electron out of the conduction band (E c ). This energy is called the affinity of the semiconductor χ = q·ϕx . E M , E Si, and χ are the minimum energies required for the emission of electrons from the material so that the electron released after emission has a velocity equal to zero. When a metal and a semiconductor are brought together, the Fermi levels become equalized by creating a short-term transfer of electrons from the material with a lower work function to the material with a higher one (as is the case with the p-n junction), Fermi levels become equal when a potential difference occurs at the junction such that it is equal to ϕMS = ϕM – ϕSi . The situation before and after the junction is formed is shown in Fig. 1.3.2.22a. Here the electrons pass from the semiconductor to the metal. The metal becomes negatively charged, and on the other hand, a depleted area with a positive space charge is created in the semiconductor. The depth of the depleted area depends on the concentration of impurities. This concentration is significantly lower than N c (for the N-type semiconductor of Fig. 1.3.2.22b) as well as than the concentration of electrons in the metal (in the metal each atom is ionized). Therefore, the change in concentrations on the semiconductor surface is relatively large, and insignificant on the metal side. Thus, the

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1.3 The p-n Junction and the Diode

Fig. 1.3.2.22 Energy diagram of a metal semiconductor junction a before the junction and b after

surface of a semiconductor accepts the entire change in the Fermi level, and thus the potential difference. The situation corresponds to a p-n junction with an abrupt change in concentration when one side is much more doped than the other. The barrier created in this way behaves in two ways towards electrons from different sides. Namely, free electrons from semiconductor need to overcome the barrier ϕMS in order to pass into metal, and electrons from the metal, of which there are many more, need to overcome a larger barrier ϕB= ϕMS- χ. Statistically speaking, however, it turns out that the probable number of electrons that can pass from one side to the other and vice versa is the same. So, in the absence of an external field, we have balance. Having in mind the positive space charge on the surface of the semiconductor, it is easy to conclude that there is a barrier at the metal–semiconductor junction for holes that would penetrate from the metal into the semiconductor. For holes, minority carriers, from the semiconductor, however, not only is there no barrier but there is an electric field that helps them pass into the metal. Therefore, when inverse voltage is connected (semiconductor at higher potential), the energy bands are further bent and the potential barrier for electrons from the semiconductor is increased. Since the surface of the semiconductor accepts the total potential increase, in this case the potential of the metal boundary remains unchanged so that the barrier for electrons from the metal (to pass into the semiconductor) remains the same: ϕB . As a result of inverse biasing, a small current of minority carriers flows through the junction. The overall situation corresponds to a backward-biased diode. In forward biasing (semiconductor at lower potential), the barrier on the semiconductor side is reduced so that significantly more electrons from the N-region can

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99

pass into the metal while the barrier on the metal side remains ϕB and still prevents electrons from the metal from passing into the semiconductor. A large current may flow now.

1.3.2.9.1 Schottky Diode Based on the presentations so far, we can conclude that the metal–semiconductor contact is, if no special measures are taken, a rectifying junction. A component based on such a junction is called a Schottky barrier diode or simply a Schottky diode. A similar diode can be obtained at the junction of P-type semiconductors and metal when E M < E Si . The behavior of the practical Schottky diode differs from the conclusions drawn due to the high density of surface states that are always found at the crystal boundary (surface states = energy states of defects + energy states of unwanted impurities). These are energy states whose energy falls within the energy gap. Measurements show that the surface states are particularly dense in the middle of the energy gap. Due to the presence of these states, the energy bands on the surface bend, even in the absence of metal. When metal is applied, there is a definite bending of energy bands, which is less than in the case of a perfect surface. Obviously, surface states reduce the influence of metal work function on the bending of energy bands. Since surface states are always present, the diode will always exhibit a smaller barrier than can be expected based on ϕMS . The characteristic of the Schottky diode and the schematic symbol are shown in Fig. 1.3.2.23. For the sake of comparison Fig. 1.3.2.23a also shows the characteristics of a silicon junction diode. A logarithmic scale for the y-axis was used, which is convenient considering the exponential dependence of the currents. By comparing the Schottky diode and the ordinary junction diode, we conclude that the barrier is smaller and that conduction will occur sooner. On the other hand, in backward biasing, the current is mostly made up of electrons from the metal that has enough energy to overcome the barrier ϕB . It is important to note that, at room

Fig. 1.3.2.23 a Characteristics of Schottky diode and diode with p-n junction and b Symbol for Schottky diode

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1.3 The p-n Junction and the Diode

temperature, the number of these carriers is practically constant, so that the inverse current depends very little on the temperature, unlike the inverse current of the p-n junction. The property that only carriers from the semiconductor side are injected into the metal (and not holes into the semiconductor) during forward biasing, has significant consequences for the behavior of the Schottky diode. First of all, there are practically no excess minority carriers in the semiconductor (no diffusion), i.e., the injected charge is very small, so the diffusion capacitance is negligible. If we keep in mind that it determines the speed of operation of the diode in reversing forward into backward biasing, we may conclude that the Schottky diode is suitable for use in high-speed switching circuits. Then, since holes do not pass through the depleted region during forward biasing, we have very small recombination in the depleted region, so the characteristic is very close to exponential even at small currents. Finally, electrons injected from the semiconductor into the metal have significantly higher energy than other electrons in a metal whose energy is determined by thermal equilibrium. These electrons are called hot electrons, and the component-diode with hot electrons. Being convenient for implementation in power electronic circuits the Schottky diode will be revisited in LNAE_Book 4.

1.3.2.9.2 Ohmic Contact When connecting components to external circuits, the rectifying property of the metal–semiconductor contact is not suitable and should be avoided. This is achieved in two ways. It would be most convenient to choose a metal with lower (for a metal-N-type semiconductor contact) or with higher (for a metal-P-semiconductor contact) work function. For the metal-P-type semiconductor contact ϕMS ≤ 0, and the Fermi level in the semiconductor is above the Fermi level in the metal so there is no obstacle for the holes from the semiconductor to pass into the metal regardless of the polarization. The appropriate metal is aluminium. For metal-N-type semiconductor contact, the contact problem is more difficult due to the already-mentioned surface states. Therefore, another approach is used to solve this problem. Namely, on the surface, at the point of contact, the concentration of impurities in the semiconductor has risen to the level of degeneration. In this case, regardless of the surface states, the Fermi level is in the conduction band. The potential barrier is now so narrow that the carriers can tunnel in both directions with very little resistance. This kind of contact is called ohmic contact. The energy band diagram for a metal—N-type semiconductor ohmic contact is depicted in Fig. 1.3.2.24. The value of its resistance is in the order of milliohms and less. Note, for low-power devices when the forward current is in the range of milliampers, this value leads to voltage drops on the contact of the order of microvolts. When high-power devices are

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101

Fig. 1.3.2.24 Energy band diagram for the case of metal—N-type semiconductor Ohmic contact

considered, however, tenths of millivolts may be obtained if such a resistance were to be encountered. That, usually, is not the case since larger junction and contact surface areas are used in such devices thus the resistances of the contacts are smaller.

1.4 Bipolar Transistor—BJT

1.4.1 Introduction It is the most widely used discrete active semiconductor component. It consists of two p-n junctions. These two junctions form areas with the same type of conductivity separated from each other by an area of the opposite type of conductivity so making a sandwich. To denote this component in texts, the designation BJT from bipolar junction transistor is usually used which means bipolar transistor with p-n junctions. Two possible combinations exist when forming the sandwich. A PNP-type transistor is shown in Fig. 1.4.1 together with the schematic symbol, and an NPN-type transistor is shown in Fig. 1.4.2. The same figures show the power sources that polarize the p-n junctions. The conduction process of these components is based on both types of charge carriers. Therefore, they are called bipolar transistors. Germanium or silicon can be used as a semiconductor material for BJTs. It should be noted that modern transistors are mostly made of silicon. The biasing of the junctions shown in Figs. 1.4.1 and 1.4.2 is called normal polarization of the transistor as opposed to the inverse polarization when the terminals of both batteries are swapped. A junction that is forward biased during normal polarization of a transistor is called emitter junction. The other junction is backward biased. This junction is called collector junction. The area from the emitter junction to the external terminal is called the emitter (or emitter body) and denoted by E while the area from the collector junction to the corresponding terminal is called collector (or collector body) and denoted with C. The emitter and collector, which are semiconductors of the same type, are separated by an area of the opposite type called the base and denoted with B. In PNP transistors, the emitter is connected to a higher potential than the base while the collector is more negative than the base. In NPN transistors, the biasing is opposite: the emitter is negative to the base and the collector is more positive. This provides forward biasing of the emitter and backward biasing of the collector junction.

© The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 V. Litovski, Lecture Notes in Analog Electronics, Lecture Notes in Electrical Engineering 1002, https://doi.org/10.1007/978-981-19-9868-3_4

103

104

1.4 Bipolar Transistor—BJT

Fig. 1.4.1 a PNP transistor and b schematic symbol for a PNP transistor

Fig. 1.4.2 a NPN transistor and b schematic symbol for an NPN transistor

When inversely polarized, the roles of the emitter and collector are swapped. Now the collector junction is forward biased and the emitter is backward biased. Since the emitter and collector are not identical structures (by concentration and area, for example), the characteristics of the “new” transistor having swapped electrodes will be different from the normally polarized one. In Figs. 1.4.1 and 1.4.2, I E , I B , and I C denote the emitter, base, and collector currents, respectively. It can be seen that the direction from the external circuit towards the transistor has been chosen for all currents. It is said that the technical direction of currents was used, which starts from the fact that the transistor is a node into which all three currents converge. Their sum, of course, should be equal to zero. In the roughest approximation, the operation of the BJT can be studied on the model of two p-n junctions or two semiconductor diodes, which is shown in Fig. 1.4.3 for the PNP case. This notion, however, is far from being able to accurately describe the phenomena in a transistor. The transistor was obtained from a single piece of crystal, which will be explained later. The width of the base area is extremely small, less than 10–5 m.

1.4.1 Introduction

105

Fig. 1.4.3 Representation of PNP transistors using two diodes

Therefore, the values of the currents through the p-n junctions will be changed in relation to those that would correspond to the lone diodes of Fig. 1.4.3. Namely, for each p-n junction individually, it cannot be considered that the width of the semiconductor material from any junction further into the base is large enough to allow the application of the theory of diode model generation expressed by the boundary condition (1.3.2.7a). In other words, the boundary conditions set when determining the p-n junction current will not apply here. For the analysis, we will first use the model given in Fig. 1.4.4 which represents the potential distribution through the PNP transistor. When analyzing this image, it should be borne in mind, Fig. 1.3.2.10b. In Fig. 1.4.4, the potential of the emitter body was chosen as the reference potential. The dashed vertical lines in this figure represent the so-called metallurgical junctions. In fact, these are the boundaries between the P- and N-regions where the concentration of the majority carriers changes sign. At the emitter and collector junctions, as with the diode, depleted regions are formed which are hatched in the figure. The transition region at the emitter junction, due to forward biasing, is narrower than the transition region at the backward biased collector junction. The actual width of the base area is less than the distance between the metallurgical boundaries of the two junctions due to the existence of transition (depleted) regions. In Fig. 1.4.4, w denotes the so-called effective width of the base area. Similar to a semiconductor diode, the space charge or diffusion capacitances act in parallel with the emitter and collector junction. Although in the case of transistors Fig. 1.4.4 PNP transistor model with potential distribution through it

106

1.4 Bipolar Transistor—BJT

the total capacitance of the emitter junction, due to the narrower transition area, is higher than in the collector junction, the capacitance of the collector junction has a greater impact on the operation of the transistor. The reason for this is that, with the normal polarization of the transistor, the resistance of the collector diode is very high, so the capacitance at this junction is more pronounced. In contrast, since the emitter junction is forward biased, the resistance of the emitter diode is low and it bridges the capacitor at the emitter junction. In Fig. 1.4.4, the potential distribution through the transistor is also given. E indicates the size of the energy barrier. The dashed line shows the distribution of potentials when external polarization sources are not connected. It can be noticed that, practically, the whole voltage change is concentrated on the transition areas because their resistance is by far larger than the resistance of other areas. The difference in the levels on the emitter and collector side indicates the fact that the concentrations of the majority carriers in the emitter and collector are not equal. This difference will be “covered” by differences in potential barriers at the metal–semiconductor contacts on the emitter side and the collector side. With the use of external power sources (polarization), the potential distribution changes. The emitter junction is forward biased (conducting), so the voltage V EB is subtracted from the potential barrier. Therefore, now, in the transition region of the emitter junction, the change in potential is smaller. In contrast, the collector junction is backward biased, the voltage of the potential barrier and the external negative voltage are added so that a much larger voltage drop is concentrated on the collector junction. The transition regions separating the N- and P-regions are the same in character and influence as in the case of a semiconductor diode. They contain uncompensated donor or acceptor charges that make up the space charge. Considerations about the width of the transition areas, which are derived for the semiconductor diode, are valid here as well. The width of the transition regions depends on the magnitude of the biasing voltages V EB and V CB . Under normal polarization, the width of the depleted region at the emitter junction is far smaller than that at the collector junction. By changing the polarization voltage, the widths of the transition regions of the junctions also change. This means that the effective width of the base is not constant and it changes when the biasing voltages change. At the same time, since the collector inverse voltage is significantly higher its influence on the effective base width will be greater.

1.4.2 Transistor Effect The basic effect, the so-called transistor effect, is achieved by the migration of the majority carriers (holes through a PNP transistor or electrons through an NPN transistor). In PNP transistors, the holes move from the emitter, where they are majority carriers, to the emitter junction under the influence of an electric field (i.e., drift).

1.4.2 Transistor Effect

107

When they reach the emitter junction, they are injected into the base. The concentration of injected holes in the base on the emitter side increases. With the earlier assumption that carrier concentrations do not change during transport through the depleted region, the concentration of holes at the emitter junction in the base area is far higher than the intrinsic concentration of holes in the base since the holes, in the base, are minority carriers. However, this is not the case at the collector end of the base where the concentration of injected secondary carriers is significantly lower. This forms a significant concentration gradient of the minority carriers in the base. That is why within the base the holes mostly move by diffusion towards the collector junction. At the collector junction, we have the following situation. The collector junction is backward biased and supports the movement of minority carriers from the base, through the potential barrier, to the collector. The holes, which are minority carriers in the base, pass into the collector and form the collector current. The same reasoning applies to the movement of electrons in NPN transistors. If the other components of the transistor currents, which will be discussed later, are ignored, the emitter and collector currents are equal because all the carriers that left the emitter arrived at the collector junction. As the resistance of the collector junction is very high, since this junction is backward biased, as seen from the external collector terminal, the transistor acts as a constant current source. In other words, the value of the collector current, as long as the transistor is normally polarized, does not depend on the magnitude of the voltage at the collector junction, so the transistor can be considered a constant current source. The magnitude of the collector current is determined by the voltage between the emitter and the base. On the collector side, the transistor therefore acts as a voltage-controlled current source (VCCS). This feature of the transistor allows signal gain to be realized in the manner illustrated in Fig. 1.4.5. An excitation AC source vg whose amplitude V m is significantly smaller than E BE is connected in series with the biasing battery of the emitter–base junction. The instantaneous value of the voltage at the emitter junction is now given by vBE (t) = E BE + vg (t) = E BE + Vm cos(ωt).

Fig. 1.4.5 Illustration of the operation of the transistor as an amplifier

(1.4.1a)

108

1.4 Bipolar Transistor—BJT

Therefore, the emitter and collector currents also contain alternating components (in addition to constant DC), which, according to the previous reasoning, are approximately equal to each other. Based on the assumption that vg 0 for the P-channel JFET. The natural direction of the drain current of a JFET is determined by polarization, which has already been mentioned. Thus, for an N-channel JFET, the natural and technical directions coincide, and for a P-channel JFET these directions are opposite. In the case of a P-channel JFET, the holes form a drain current from the source to the drain, and the technical direction is always from the external terminal (drain) to the component. Here we will briefly interrupt the discussion and make a few comments on the theory of electronic component modeling. Namely, when deriving the model of electronic components, so far, we started from the description of physical phenomena in them (continuity equations, for example) and generated models by solving differential equations describing phenomena in components. Such an approach to modeling is called physical. However, it has been shown that the physical approach is not always simple enough to apply (junction’s leakage effects, for example) or does not provide expressions that are suitable for handling during circuit analysis. That is why, sometimes, the model created by the physical approach is supplemented or replaced by a more suitable one. Thus, the diode and BJT model was expanded with leakage resistances, semiconductor body resistances, and capacitances, and the JFET model

1.5.2 Characteristics of a JFET

153

was completely replaced by the approximate expression. An approach to component modeling that starts from an expression and tries to determine the constants (parameters) in it by approximating the characteristics of a component is called the black-box approach. Equation (1.5.18b) is a black-box model of a JFET. Here, for example, the constant I DSS was introduced, which is measured as the drain current at V DS = 0. I DSS is determined by the channel dimensions and specific conductivity and represents an approximation of drain current when V GS = 0. Analytically, it is easiest to find its value if V GS = 0 is set in (1.5.20c). The saturation current will be obtained when the channel width decreases to zero, i.e., when the biasing voltage of the p-n junction reaches the critical voltage: VGS − VDS = Vp .

(1.5.20a)

The solution of this equation by V DS gives the saturation voltage: VDSsat = VGS − VP .

(1.5.20b)

So, for V GS = 0, one gets V DS sat = −V p (according to the above example it would be V DS sat = 2.82 V). At voltages V GS which are higher in absolute value, the value of the saturation voltage will decrease. For example, for V GS = 0.95·V p , one gets V DS sat = −0.05·V p which means that if V p = −2.82 V one gets V DS sat = 0.141 V. If the V GS voltage, based on (1.5.20b), is eliminated from (1.5.18b), the following will apply at the boundary between the ohmic and saturation areas: IDsat = IDSS · [VDSsat /(−Vp )]2 .

(1.5.20c)

Here I Dsat is the saturation current. This tells us that the two areas of operation of the JFET (ohmic and saturation) are, in the field of output characteristics, separated by a parabolic line shown in Fig. 1.5.8. By substituting (1.5.20a) into (1.5.18a) the drain current in saturation conditions is obtained as: | | 3 2 (V0 − Vp ) 2 − (V0 − VGS ) 23 ID = G 0 VGS − Vp + . (1.5.20d) 3 (V0 − Vp )1/2

Fig. 1.5.8 The boundary between the ohmic and saturation regions in the field of output characteristics of a JFET

154

1.5 Junction Field Effect Transistor—JFET

Thus, we generated analytical expressions for the characteristics of JFET in all three areas. First, expression (1.5.10) gives the output characteristics in the linear domain. We will talk more about these characteristics later, and now let us just mention that the current is a linear function of V DS . The slope of this line, which passes through the origin, depends on the value of V GS . Thus, the transistor acts as a controlled (linear) resistor. Then, the expression (1.5.18) represents the output characteristics in the Ohmic area. Here, the dependence of the current on the voltage V DS is no longer linear, although it also contains a significant linear term. As V DS increases, the slope tends to zero. The current reaches extremum (the slope becomes equal to zero) when the condition (1.5.20a) is satisfied. Finally, for V DS higher than those given by (1.5.20b), voltage saturation occurs. The current I DS no longer depends on V DS —it is saturated. The value of the saturation current depends on the value of the V GS . Therefore (1.5.20c), in fact, represents a transfer characteristic of the JFET. Of the greatest importance is the expression that determines the area of saturation (or the pinch-off area). Since (1.5.20d) is a relatively complex expression, it is usually approximated by: { IDS =

IDSS (1 − 0

VGS 2 ) Vp

| | za |VGS | < |Vp | | |, za |VGS | > |Vp |

(1.5.21a)

which was created by substituting (1.5.20a) into (1.5.18b). When using this expression for N-channel JFET it is valid that V p < 0 and, at normal biasing, V GS < 0. While, for P-channel JFET V p > 0 and, at normal polarization, V GS > 0. It remains to point out some more facts related to JFET’s saturation behavior. Namely, there are two theories about the formation of the drain current at saturation. According to one, a real interruption of the channel never occurs, and thus the drain current is not completely saturated. To show this, consider the expression (1.5.16). For the drain current density at a distance x from the source we have: JD =

dV ID =σ = q ND μn K . W · d(x) dx

(1.5.22)

At small electrical fields μn does not depend on the field, so the current density increases with increasing the field. This means that the ratio I D /d increases and d decreases. The channel is getting narrower. At moderately large electric fields, √ the mobility of the carriers becomes proportional to 1/ K so that the increase in current density is slower, which means that the channel narrows more slowly. Finally, at very large electric fields (before the breakdown occurs) the mobility decreases proportionally to 1/K so that the current density becomes approximately constant and independent of the field, d becomes constant (small) so that the interruption of the channel cannot occur. After all, if the channel were interrupted, the current density would become infinite, which is physically impossible. According to another

1.5.3 Parameters of the JFET

155

theory, the depleted regions overlap and the electrons fly through the newly formed depleted region on the way from the source to the drain. Here, too, however, the increase in drain voltage is reflected in the further expansion of the depleted areas, that is, in the shortening of the rest of the channel that remained un-depleted. The analysis of the dependence of the current density on the value of the electric field, and thus on the voltage V DS , which was performed here, indicates the continuity of the process of voltage saturation of the JFET. This results in a constant increase in drain current, although slower if V DS is higher. This increase in the drain current is included in the expression for the output characteristic of the JFET in the region of voltage saturation by multiplying the current by a factor that is linearly dependent on the V DS . That is expressed as { IDS =

| | IDSS (1 − VGS /Vp )2 (1 + λVDS ) for |VGS | < ||Vp || . 0 for |VGS | > |Vp |

(1.5.21b)

The number λ has a dimension of 1/V and corresponds to the reciprocal of the Early voltage previously introduced for similar purposes in the modeling of the BJT. For a JFET, whose reciprocal of the slope of the output characteristics is of the order of 1 Mu, λ of the order of 10–3 V−1 can be expected. λ will be higher if the slope of the output characteristics is higher.

1.5.3 Parameters of the JFET We distinguish between static and dynamic JFET parameters. By static we mean those that are related to the DC mode of operation of the JFET, and by dynamic we mean those that are related to the derivatives of the characteristics, i.e., to the dynamic (incremental) mode of operation. The current I DSS is the most important static parameter of JFET. This is the drain current for V GS = 0. Based on the transfer characteristics depicted in Fig. 1.5.5 it can be concluded that, to some extent, I DSS depends on V DS . Therefore, often, when stating this parameter, the value of V DS should be given. Only for relatively high voltages V DS is not relevant. Based on the same figure, for the transistor shown, we have I DSS = 10 mA. The pinch-off voltage V p determines when the JFET will be brought to cut-off (by increasing V GS ) or when it will be brought to saturation (by increasing V DS ). Since it can be identified as a voltage corresponding to the cessation of drain current flow, a current corresponding to “zero current” must be specified to define it. If, for example, it is chosen that the zero current is 1 μA, then from Fig. 1.5.5 we have V p = 4.4 V. Finally, the last static parameter is the inverse saturation current of the gate-channel junction, I GSS . It is determined under the condition that the drain is short-circuited to the source (so, the transistor is seen from the gate as a diode). This current is important

156

1.5 Junction Field Effect Transistor—JFET

because it determines the input resistance of the JFET. Like any inverse current, it is temperature dependent and its temperature dependence corresponds to the inverse saturation current of the diode. For example, for an increase in temperature of 50 K, it can be expected that the I GSS will increase tenfold: one decade by 50 K. Otherwise, at room temperature, its value is about 10 nA. The input resistance is therefore over 108 u. The dynamic parameters of JFET are the voltage gain coefficient, the transconductance, and dynamic (internal or output) resistance. The voltage gain coefficient is defined as a partial derivative of the constant current characteristic as: μ=−

dVDS ∂ ID ∂ ID / =− . ∂ VGS ∂ VDS dVGS |ID =C te

(1.5.23)

The transconductance is defined as a partial derivative of the transfer characteristic as: gm =

dID . dVGS |VDS =C te

(1.5.24)

Typical values of the JFET’s transconductance are in the range of several mA/V. The internal resistance is defined as a partial derivative of the output characteristic as rD =

dVDS . dID |VGS =C te

(1.5.25)

Typical values of the internal resistance are between 105 and 106 u. For a given operating point or for given coordinates in the field of transistor’s characteristics, the values of the dynamic parameters can be determined graphically, from the characteristics, taking finite (instead of infinitesimal) increments of voltages and currents around the quiescent operating point. If we use DC values in (1.5.1a) it becomes: ID = ID (VGS , VDS ).

(1.5.26)

Its total differential is dID =

∂ ID ∂ ID dVGS + dVDS, ∂ VGS ∂ VDS

(1.5.27)

which leads to dID = gm dVGS +

1 dVDS . rD

(1.5.28)

1.5.3 Parameters of the JFET

157

For I D = Cte (i.e., dI D = 0) a relation connecting the dynamic parameters is obtained as:

gm · rD = −

dVDS , dVGS

(1.5.29)

or gm · rD = μ.

(1.5.30)

According to this result, the numerical values of the voltage gain coefficient of the JFET are of the order of several hundreds. As can be seen from (1.5.10), (1.5.18), (1.5.20) the dynamic parameters of the JFET are nonlinear functions of the terminal voltages. For example, by differentiating (1.5.21) with respect to V GS we get | ( ) / IDSS / 2IDSS VGS gm = ID = C te ID , −1 =2· 2 Vp Vp Vp

(1.5.31a)

which means that the transconductance is proportional to the root of the drain current. It should be noted here that the application of the first part of this formula for a Pchannel transistor at normal biasing (V p > 0 and V GS > 0) will give a negative sign in the differentiation, which is natural given that the fact that the current is negative was neglected. This sign is ignored. The dependence of r D and μ can be considered in a similar way. If r D were calculated from (1.5.25) and (1.5.21a), infinite resistance would be obtained. Its first approximation, however, can be obtained by differentiating (1.5.21b) with respect to V DS and taking a reciprocal value. If so, one gets ) ( 1 + λ · VDS 1 ∂ ID = ≈ . rD = 1/ ∂ VDS λ · ID λ · ID

(1.5.31b)

The obtained result can be interpreted in the following way. The approximation (1.5.21b) generates output characteristics whose slope depends on V GS or I D . The higher the current, the higher the slope of the output characteristic at the same V DS value. Hence the reciprocal dependence of the output resistance on the drain current. When considering the dependence of the transconductance and the internal resistance on I D , the starting point was the parabolic approximation [(1.5.21a) and (1.5.21b), respectively], of the dependence of the current on the gate voltage. The error made when approximating the function given by (1.5.20) by the function given by (1.5.21) is, generally, acceptable when the difference in the values of the function (current) is in question. The situation with the derivative with respect to V GS can

158

1.5 Junction Field Effect Transistor—JFET

be concluded if we keep in mind that the derivative of (1.5.20) with respect to V GS gives the dependence of the transconductance in the form of root of the V GS , and the derivative of (1.5.21) in the form of a linear function of V GS . Even if the values of the transconductance obtained in these two ways do not differ at low V GS , these considerations point to the important conclusion that the transconductance of the component cannot be significantly increased by increasing the current. A more precise expression than (1.5.31a) says that the transconductance grows proportionally to the root of V GS , i.e., approximately with the third root of the current. Since the JFET is a semiconductor component, its current also depends on temperature. There are two main reasons for the temperature dependence of the JFET’s current. First of all, due to the increase in temperature, the mobility of the carriers in the channel decreases, and thus the resistance of the channel increases. Due to that, the drain current decreases. The second effect refers to the change in channel width due to temperature. Namely, the widths of the depleted areas decrease with increasing temperature (due to the decrease of the barrier E 0 ), which means that the channel expands and that the resistance of the channel decreases. Due to that, the current increases. At large channel widths (V GS ≈ 0), the changes in the width of the depleted areas due to temperature as compared to the total width of the channel are small, so the increase in resistance due to the decrease in mobility dominates. At low (in absolute value) voltages V GS the drain current decreases with increasing temperature! When the channel is narrow (V GS ≈ V p ), the changes in the width of the depleted areas are significant as compared to the width of the channel, so that the expansion of the channel dominates with increasing temperature, and the current increases with temperature. There is a value of V GS for which the current is practically independent of temperature. Unfortunately, at this voltage, the current is relatively small, so this effect cannot be used practically. For the most part, the characteristic is dominated by a decrease of the current with increasing temperature, which means that the drain current of the JFET has a negative temperature coefficient (unlike bipolar, where the temperature coefficient is positive). According to the drain current, the dynamic parameters depend on the temperature. These changes are not linear, but it can be assumed that with an increase in temperature of 1 K, the transconductance decreases by about 0.4%, and the internal resistance increases by about 0.4% in the range around room temperature and for V GS = 0 V. The measured dependence of the transconductance on V GS at constant V DS for different temperatures can be seen in Fig. 1.5.9. It is necessary to notice the logarithmic scale for the y-axis and the fact that the point where the transconductance does not change with temperature—the zero temperature-coefficient point—is in the area of very small transconductances.

1.5.4 Active Operating Area of the JFET

159

SI. 1.5.9 Dependence of the transconductance of a JFET on V GS for three temperatures

1.5.4 Active Operating Area of the JFET As with the BJT, the main limitation in the operation is the maximum dissipation on the drain. It depends on the temperature in the same way. The difference is that JFET is not usually used in high-power amplifiers, so other limitations come to the fore. Of course, it should be borne in mind that the temperature coefficient of the drain current is negative, so the process of self-heating is eliminated. Finally, JFET does not exhibit a secondary breakdown. The maximum current is limited by the maximum current of the conductors that connect the contacts to the external pins or by local overheating of the source due to uneven current distribution. In order to increase the maximum current, the source and drain usually have an interdigital structure (they enter each other like straightened fingers of one hand into the fingers of the other hand). The minimum drain current is zero. JFET can be switched off only if |V GS | > |V p | at normal biasing. At low voltages between the drain and the source, we are in the ohmic or linear region. This region corresponds to the areas of current saturation in a BJT. From the characteristics and based on (1.5.20) we see, however, that the minimum voltage on the drain—the voltage at which we leave the saturation region and move to the ohmic region—is much higher than in a BJT. For a transistor whose characteristics are shown in Figs. 1.5.4 and 1.5.5 for V GS = 0 V, the minimum voltage (at the saturation limit) is V DS = V p = 4.4 V. Usually, however, the minimum voltage is related to the current, so for V GS = 0 and I D = 6 mA, from (1.5.20c) we get V DSmin ≈ 3.4 V. This area is often described by the value of internal resistance RDSon . This is by definition the reciprocal value of the slope of the output characteristic in the linear region. Its value is significantly lower than r D in the region of (voltage) saturation, it is several hundred ohms and, of course, depends on V GS and I D . For the characteristics of Fig. 1.5.4, RDSon ≈ 610 u was obtained. Considering that with the change of gate voltage (input values), we get small or no changes in the output current in the ohmic region (Fig. 1.5.4), we can easily conclude that the ohmic region is outside the active area of the JFET. Increasing the drain voltage increases the backward biasing of the gate-to-channel junction in the part near the drain and, at too high voltages, a breakdown can occur. Figure 1.5.10 illustrates how the gate-to-channel p-n junction is biased starting from

160

1.5 Junction Field Effect Transistor—JFET

SI. 1.5.10 JFET as a distributed resistor

the drain and ending at the source. Here, the p-n junction is shown through a series of diodes that have a cathode in the channel while the channel is represented as a series connection of a set of resistors. The channel is said to be shown as a distributed resistor. It is now easy to see that the first diode from above has the highest inverse voltage (V GD = −15 V) and that, as the drain voltage increases, a breakdown will occur on it first. When measuring the breakdown voltage, the drain is usually grounded (as is the source) so that there is no potential distribution inside the transistor. In that way, the breakdown will occur at the diode which has the lowest breakdown voltage (due to the non-uniformity of the gate and the channel, the local breakdown voltages are not equal). This voltage is usually denoted by V GSS0 . It should be borne in mind that it represents the voltage between the gate and the drain and that V DS-max is less than V GSS0 by the magnitude of the voltage at the gate (by |VGS |). V GSS0 is of the order of a few tens of volts. For illustration, the following set of parameters characterizes a JFET: IDSS = 14 mA for VDS = 5 V and VGS = 0 for VDS = 15 V and ID = 1 μA Vp = 3.7 V for VGS = −15 V and VDS = 0 IGSS = 10 nA for VDS = 15 V and VGS = 0 rD = 5 M u for VDS = 15 V and VGS = 0 gm = 5.5 mS for VGS = 0 and ID = 0 RDSon = 125 u and IG = 10 μA VGSSO = −25 V min for VDS = 0 All parameters were measured at room temperature.

1.5.5 JFET at High Frequencies

161

1.5.5 JFET at High Frequencies Since it has a p-n junction, the JFET also has its capacitances. In fact, we may speak of a single capacitor located between the gate and the channel, which, when we look at the component from the outside, manifests itself as two: one between the source and the gate, and the other between the gate and the drain. When it comes to the normal biasing of the transistor, these are the space charge capacitances of the p-n junction and their values are of the order of several pF. If parasitic capacitances such as capacitances towards the housing or capacitances between the introductory conductors are added to these capacitances, we get a complete picture as in Fig. 1.5.11a. By C GS the total capacitance between the gate and the source (mostly space charge) is denoted. Similarly, C GD is the capacitance between the drain and the gate while with C DS the capacitance between the drain and the source (practically only parasitic capacitance). The dependence of the first two on the gate voltage is depicted in Fig. 1.5.11b. Typical values are C GS = 9 pF (for V DS = 15 V, V GS = 0), C GD = 3 pF (for V DS = 15 V, V GS = 0) and C DS = 0.05 pF. Although C GS is the largest capacitance, the most important is the capacitance of C GD , since it allows for the so-called Miller’s effect, which means a return signal path is created through it from the output (drain) to the input (gate).

SI. 1.5.11 JFET capacitances. a Symbolic representation b example dependences of the capacitances on V GS and c large-signal model of the N-channel JFET

162

1.5 Junction Field Effect Transistor—JFET

Given these capacitance values, the input impedance of the JFET at higher frequencies (of the order of tens of MHz) is not so large, so in this respect JFET does not have a significant advantage over the bipolar transistor. However, one significant advantage remains regarding nonlinear distortions (more on these in LNAE_Book 2). Namely, since JFET has an approximately square transfer characteristic, when excited by a simple periodic signal, the output current will have three components: DC, simple-periodic with the same frequency as the excitation signal, and another simple periodic with twice the original frequency. This is not the case with the bipolar transistor whose I C (V BE ) transfer characteristic is exponential and generates many new signals that are difficult to filter. To complete the modeling issue, in Fig. 1.5.11c, we represent the complete nonlinear model of the JFET applicable for large signals and at high frequencies. As compared with Fig. 1.5.11a here the transistor is substituted by a nonlinear current source and two diodes representing the gate to channel junction (in two parts).

1.5.6 JFET as a Voltage-Controlled Resistor We have previously shown that in the linear region, i.e., at low voltages on the drain, the JFET behaves as a linear resistor whose resistance can be controlled by the voltage at the gate. In Fig. 1.5.11 the output characteristics of JFET at low drain voltages (up to +60 mV) are given. It can be seen that the characteristic is linear and bilateral (V DS can also be negative). The slope of these I D versus V DS lines represents the conductance between the drain and the source. A change in V GS has the effect of rotating the line around the origin. It can be seen that the possibility of controlling the resistance is limited. In the case of Fig. 1.5.12 the resistance varies from 133 u (for V GS = 0) to 800 u for V GS = 3 V. At higher voltages (in absolute values) at the gate r D can be higher. Fig. 1.5.12 JFET as a variable linear resistor

1.5.7 Constant Current Diode

163

Fig. 1.5.13 a Schematic symbol of the constant current diode and b its characteristic

1.5.7 Constant Current Diode If the JFET’s gate is permanently connected to the source, a two-terminal device (diode) is created whose characteristic is determined by the characteristic for V GS = 0. In a wide range of voltages on the diode from the pinch-off voltage to the breakdown, the current through the diode is constant and does not depend on the connected voltage. For voltages lower than the pinch-off voltage, the current decreases and this is not the operating region of this component. Due to the mentioned properties, this diode is called a constant current diode. Its symbol is shown in Fig. 1.5.13 where the anode corresponds to the drain and the cathode to the source. The arrow indicates the direction of the current flow. This component exhibits a dual characteristic with the Zener diode. Namely, while the voltage of the Zener diode was constant and independent of the current, now the current is constant and does not depend on the voltage. This component is used in circuits when the current of a branch needs to be kept constant regardless of the connected voltages. This is possible because it will accept all voltage increments.

1.6 Insulated Gate Field-Effect Transistors—IGFET

1.6.1 MOS Structure MOS transistors, unlike bipolar and JFET, are made on the surface of a silicon crystal and its operation depends on the presence of a boundary between the semiconductor and the insulator. Therefore, in this section, the electrical properties of the semiconductor surface will be considered first. This will enable the acquisition of basic knowledge for understanding the functionality and to generate models of the MOSFET. For a P-channel MOSFET, the semiconductor material of the substrate is N-type silicon and the insulator on the surface is silicon dioxide (SiO2 ). This structure is shown in Fig. 1.6.1a. In doing so, it is considered that the N-type substrate is related to the reference potential (it is usually said: the lowest potential in the circuit). Therefore, for now, all voltages are measured with respect to the potential of the substrate. Deep in the substrate (frequently referred to as bulk) free charge carriers are electrons. The electrical conditions of silicon (semiconductor) near the surface are described by the terms: accumulation, depletion, and inversion, depending on whether the density of space charge on the surface (on the semiconductor side) is higher, lower or of opposite sign from the bulk, respectively. Figure 1.6.1 illustrates these conditions by showing the energy bands (b), and the charge distribution (c). Let us now consider the conditions on the surface of a semiconductor individually. In the case of accumulation, the concentration in the N-type silicon, in a narrow area near the surface, is of the same sign as deep in the substrate, but it is increased. A mobile space charge was formed, the value of which per unit area is denoted by Q , I (C/cm2 ). This means that the specific conductivity of the surface will be increased in relation to the specific conductivity of the substrate. According to the need for the Fermi level to be constant, the energy bands on the surface are bent downwards, which is equivalent to moving the Fermi level to higher value as a result of increasing the concentration of the majority carriers. The consequence is an electric field that is (for

© The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 V. Litovski, Lecture Notes in Analog Electronics, Lecture Notes in Electrical Engineering 1002, https://doi.org/10.1007/978-981-19-9868-3_6

165

166

1.6 Insulated Gate Field-Effect Transistors—IGFET

Fig. 1.6.1 Conditions on the surface of the semiconductor (1) accumulation, (2) depletion, and (3) inversion

the N-substrate) directed towards the surface. The shallow area in which this charge occurs is called the accumulation area. This condition is illustrated in Fig. 1.6.1(1). The accumulated charge on the surface of the semiconductor can be formed if an external electric field is brought in a suitable way, which will (for the N-substrate) attract electrons to the surface. In other words, it is necessary to bring the gate to a positive potential with respect to the substrate. The surface of the semiconductor, under these conditions, is still of the same type of conductivity as the substrate, and its conductivity is higher. Depletion occurs when (for the N-substrate) the gate is brought to a negative potential (or electric field) relative to the substrate. This results in removal of the main carriers from the surface, i.e., to depletion of the surface. Under depletion conditions, which are shown in Fig. 1.6.1(2), the energy bands bend moderately upwards. Therefore, the concentration of electrons (majority carriers) on the surface is lower than in the substrate. This is why an immobile positive charge of donor ions occurs. The later charge will be denoted as Q , B (C/cm2 ).

1.6.1 MOS Structure

167

The properties of the depletion condition are usually analyzed using the “depletion approximation”, where it is assumed that the depleted region along the surface of the semiconductor is completely depleted, i.e., does not contain free carriers. It is also assumed that the physical boundary between this area and the substrate is sharp and clear. Under the conditions of approximation, the depletion distribution Q , B is rectangular as shown in Fig. 1.6.1c(2). It is easy to determine that under these conditions the electric field on the surface is a linear function of the distance from the surface. The electrostatic potential is a parabolic function of the distance. The total stationary surface charge Q , B located in the depleted region up to depth X d is Q ,B = q ND X d

(1.6.1)

The electric field K s on the surface (on the inside) of the semiconductor is obtained from Gauss’s law as K s = −Q ,B εs

(1.6.2)

where it is assumed that the field deep in the substrate is zero. εs is the absolute dielectric constant of silicon (semiconductor). The minus sign comes from the fact that the surface vector (oriented outwards) coincides with the negative x-axis. In inversion, the conductivity type of the surface layer is opposite to the conductivity type of the substrate. This condition enables the manifestation of the basic functionality of the MOSFET and is therefore of the greatest interest. If the field on the surface of the depleted crystal increases, a point at which the energy state E fi is equal to the Fermi level E f on the surface is soon reached. The surface now behaves like a pure semiconductor. If the energy bands continue to bend upwards, E fi becomes larger than E f near the surface, so the concentration of holes becomes higher than one of the electrons [Fig. 1.6.1(3)]. We say that the surface is inverted. The concentrations of electrons and holes on the surface are now determined by the following relations: n = n i e(Ef −Efi )/kT

(1.6.3)

p = n i e−(Ef −Efi )/kT

(1.6.4)

and

We get (1.6.3) by combining (1.2.3.24) and (1.2.3.33) using n = N D and E f = E fn , while (1.6.4) is obtained by combining (1.2.3.25) and (1.2.3.36) using p = N A and E f = E fp . Although the surface is inverted at the moment when E fi becomes larger than E f , the concentration of holes remains small until E fi grows significantly above E f . Only when the exponent in (1.6.4) becomes large enough will a significant number of holes be available. Therefore, “inversion approximation” is used, where it is assumed that

168

1.6 Insulated Gate Field-Effect Transistors—IGFET

a strongly inverted surface is formed only when E fi is significantly above E f (as much as, deep in the substrate, E f is above E fi ). From (1.6.3) and (1.6.4), it can be seen that the surface is strongly inverted when the concentration of holes on the surface becomes equal to the concentration of electrons deep in the substrate, i.e., when the surface is inverted in relation to the substrate. As before, for the electric field from the inner side, we can write   K s = − Q ,B + Q ,I /εs ,

(1.6.5)

where Q , I (C/cm2 ) is the mobile charge per unit area in the inverted layer, while Q’B is the fixed charge of ionized impurity atoms. The electrostatic potential Φ in a semiconductor is determined by the potential energy of charged particles. The relationship between the electrostatic potential and the energy of the electron is, as before, E = −qΦ. For convenience, the Fermi level can be chosen as the reference energy level. The potential corresponding to energy E would be Φ = −(E − E f )/q

(1.6.6)

Further, if the selected reference level is E fi , deep in the semiconductor it will be ⎧ ⎨ VT · log(ND /n i ) for N-substrate E fi − E f Φf = − = ⎩ q |x>X d VT · log(NA /n i ) for P-substrate.

(1.6.7)

Thus, Φf is positive in an N-type semiconductor and negative in a P-type semiconductor. Under the condition of strong inversion, the total bending of the energy bands corresponds to a potential barrier (ΦB ) which is equal to twice the Fermi potential and has the opposite sign: ΦB = −2 · Φf

(1.6.8)

This bending of the energy bands on the surface of the semiconductor under the influence of the external field corresponds to the complete displacement of the energy bands at the usual p–n junction, as discussed in Chap. 1.2. The difference is that the junction is now formed as an induced junction under the action of K s . The value of ΦB is negative for the inverted P-type layer on the N-substrate, and positive for the inverted N-type layer on the P-substrate. When the condition of strong inversion is reached, the energy bands no longer bend significantly with the increase of the “intensity” of the inversion. This can be seen if we keep in mind that the exponential term in (1.6.4) now has a rather high value, so a small increase in the argument allows a significant increase in the

1.6.1 MOS Structure

169

concentration of free carriers. Therefore, as K s increases, Q ,1 increases, and Q ,B and X d remain practically constant. It is interesting to note that the inverted layer located on the surface of silicon below the oxide and the semiconductor substrate now form a p–n junction. A depleted area is formed between the inverted layer and the substrate so that, if properly biased, the inverted layer is isolated from the substrate. Thus, we have briefly described the conditions prevailing on the surface of semiconductors and characterized the electrical nature of the surface from the inside. Let us now consider the conditions related to the outer side of the semiconductor surface in the MOS structure.

1.6.1.1 MOS Capacitances In the production of MOS transistors, the surface of the semiconductor is covered with a thin (usually 5·10–8 to 10–7 m) layer of dielectric. This layer is usually silicon dioxide (SiO2 ). This insulating layer is usually called “oxide”. Above the oxide is a gate that is usually made of aluminium. The whole “sandwich” (metal-oxide-silicon) forms an MOS capacitor which is shown in Fig. 1.6.2a. The electrical properties of the oxide are determined by the thickness (t ox ), dielectric constant (εox ), and charge (Qox ) that can be found inside the oxide. This charge has a significant impact on the characteristics of MOS transistors. It can occur in several ways: it can be ions of impurities embedded in the silicon (before oxidation took place); charges near the silicon-oxide boundary resulting from the in-completion of the regular crystal lattice of silicon; or, as is mostly the case, ionized silicon atoms in the oxide. It has been shown that by suitable surface preparation, regardless of the origin, this charge becomes immobile and it is concentrated close to the silicon

Fig. 1.6.2 a MOS structure and b dependence of the MOS capacitance on the voltage between the gate and N-substrate

170

1.6 Insulated Gate Field-Effect Transistors—IGFET

surface (on the insulator side). Therefore, it is convenient to assume that this charge also has a surface nature and is expressed by Q , ox (C/cm2 ). The Qox charge is shown in Fig. 1.6.1c (by a blue stripe). Based on the above, it can be concluded that Q , ox modifies the electric field in both the oxide and the silicon. Note also that Q , ox does not depend on the type of conductivity of the substrate and is usually positive. If the capacitance between the metal gate and the silicon substrate is measured as a function of the voltage connected between the gate and the substrate, the dependence corresponding to Fig. 1.6.2b is obtained. The three areas on this curve correspond to three conditions on the surface of the semiconductor. When considering the N-type substrate, when the gate is at a positive potential with respect to the substrate (V G > 0), the surface is under the condition of accumulation and acts as a conductor, which has the consequence that the capacitance corresponds to the capacitance between two conductive plates separated by the oxide. The capacitance per unit area, in this case, is C , = C ,ox = εox /tox

(1.6.9)

Since εox = 3.45 · 10–5 pF/μm, and typically t ox ≈ 0.1 μm, for C ,ox we approximately get C ,ox = 34.5 · 10–5 pF/(μm)2 . So, a component with a gate area of 30·50 (μm)2 exhibits a capacitance of 0.52 pF. When the voltage at the gate is negative enough to form a depleted region in silicon, the effect is equivalent to increasing the thickness of the oxide. Namely, another insulating layer is now added to the insulation layer (oxide)—the depleted area. Therefore, the total capacitance decreases. However, in order to show the depletion effect and the inversion effect together, the total capacitance is expressed as a series connection between the oxide capacitance and the capacitance of the depleted region: 1/C = 1/Cox + 1/Cd

(1.6.10)

When the depleted area expands, C d decreases, so the overall capacitance decreases. Finally, at high negative voltages, an inverted layer is formed along the surface so that a real series connection of two capacitors is formed. The plates of the former consist of the metal and the accumulated charge (which acts as a conductor), separated by the oxide as the dielectric while the plates of the latter constitute of the accumulated charge and the charge of the majority carriers in the substrate with the depleted region between the inverted layer and the substrate as a dielectric. Soon the width of the depleted area reaches a maximum, so the overall capacitance no longer decreases.

1.6.1 MOS Structure

171

1.6.1.2 Threshold Voltage of the MOS Structure Before we finally start determining the analytical dependence of the transistor characteristics, let us consider other factors that influence the determination of the boundary lines between the three conditions prevailing on the surface of the semiconductor. The transition between accumulation and depletion occurs when the energy bands in silicon remain horizontal all the way to the surface. This is illustrated in Fig. 1.6.3a and is called the “flat zone” condition. In this case, there is no electric field in the silicon, and the density of excess charge is equal to zero. The mobile electrons in the N-substrate neutralize the positive charge of donor atoms. In the absence of charge in the oxide (Q ,ox = 0), the electric field outside the silicon is equal to zero and the energy bands in the oxide are also horizontal. However, as shown in Fig. 1.6.3b, this condition does not occur when the voltage at the gate is zero. This is a consequence of the difference between the work functions (ionization energy) of silicon and metal, which enables the formation of a potential barrier between metal and silicon (ΦMS ). Here we have a situation reminiscent of a Schottky diode, except that, here, the semiconductor and the metal are separated by an oxide so that no charge is transferred. The work function of a material is defined as the energy required to transfer one electron from the Fermi level in the material to vacuum. In the case of the MOS structure, the energies we mentioned above represent modified work functions: from the Fermi level in the gate metal to some conductive band in the oxide. They are shown in Fig. 1.6.3a using the equivalent potential barriers ΦM and ΦSi . The figure shows the condition in flat zones and without Qox . Therefore, the voltage at the gate required to obtain flat zones is simply equal to the difference of potential barriers and is expressed as VG = ΦMS = ΦM − ΦSi

(1.6.11)

where ΦMS is frequently referred to as the metal-to-silicon work function. For typical impurity concentrations, we have ΦMS ≈ −0.3 V for N-type silicon. Due to the presence of Qox , the value of the voltage required to produce flat zones differs from that given in (1.6.11). This is illustrated in Fig. 1.6.4. When flat zones are established, there is no field in the silicon side. In order to achieve this having in mind the positive Qox , the voltage at the gate must be negative enough so that the same but negative charge (−Qox ) appears on the metal. Now , VG = Q ,ox /Cox

(1.6.12)

When both Q , ox and ΦMS are considered for the voltage that will cause flat zones in silicon, we have , VFB = ΦMS − Q ,ox /Cox

(1.6.13)

172

1.6 Insulated Gate Field-Effect Transistors—IGFET

Fig. 1.6.3 Energy diagram showing the metal-to-silicon work function. a Case of flat zones, b gate grounded, and c charges when gate grounded

When the voltage at the gate is more negative than V FB , the surface of the silicon becomes depleted and the zone curves upwards. When E fi just touches E f , the semiconductor is intrinsic (on the surface). With a further increase in E fi , an inverted P-type layer is formed. This defines the boundary between depletion and inversion. However, under inversion, we have adopted only a strong inversion that will occur if it is   (E fi − E f ) at the surface = E f − E fi inside the substrate

(1.6.14)

1.6.1 MOS Structure

173

Fig. 1.6.4 Influence of the oxide charge on the change of the work function a flat zone case and b grounded gate

174

1.6 Insulated Gate Field-Effect Transistors—IGFET

Therefore, for the total potential barrier (ΦB ) which is a consequence of the bending of the zones on the surface, we have ΦB = −2 · Φf

(1.6.15)

The negative sign indicates that the energy zones bend in the opposite direction to Φf . In our example, E fi is basically below E f , so the zones curve upwards. In the component with a P-channel ΦB is a negative number. We obtain at the value of the width of the depleted region by analogy with the width of the depleted region on one side of the p–n junction, which we previously stated to be / 2ε(E 0 − q · V ) wn = 2 q ND (1 + ND /NA ) If it is considered that the concentration N A corresponds to the concentration of carriers in the metal then N A >> N D . If now, we consider that the potential difference between the surface and the substrate (V ) is equal to zero and if we identify the potential barrier at the junction (E 0 /q) with −ΦB , we obtain Xd =

√ 2εs (−ΦB )/(q ND )

(1.6.16)

and, based on (1.6.1) for the space charge, we have Q,B =

√

2εs q ND (−ΦB )

(1.6.17)

The gate voltage that is needed to cause a strong inversion is called the threshold voltage (V T ). We get the value of this voltage as a sum of – the voltage required to cause flat zones (V FB ); – the voltage that will cause bending of energy zones to cause strong inversion; and – voltage required for the formation of an electric field that maintains the charge QB in the depleted area. The charge QB requires a charge −QB in the metal or a gate voltage of −QB /Cox . Accordingly, for the threshold voltage, we have , VT = VFB + ΦB − Q ,B /Cox

(1.6.18)

and using (1.6.13) we obtain , , VT = ΦMS + ΦB − Q ,ox /Cox − Q ,B /Cox

(1.6.19a)

1.6.2 MOS Transistor

175

Example 1.6.1 Find the threshold voltage of the structure if an N-type silicon substrate is used with N D = 1015 cm−3 . It is given: ΦMS = −0.3 V, Q , ox = 1.5·1011 · (1.6·10–19 ) C/cm2 , t ox = 10–7 m, εs = 1 pF/cm i εox = 0.346 pF/cm. Solution: We calculate first: C ,ox = εox /t ox = 3.46· 10–8 F/cm2 . Then we determine: ΦB = −2Φf = √ −2·ln(N D /ni ) ≈ −0.6 V. It remains to be determined: Q , B = 2εs q ND (−ΦB ) = 1.4·10−8 C/cm2 , which gives VT = ΦMS + ΦB − Q , ox /C , ox − Q , B /C , ox = −0.3−0.6−0.7−0.41 = −2.01 V. In the last expression, Q , B is calculated from (1.6.17). It was considered that there was no voltage drop between the inverted layer (channel) and the substrate. If this voltage exists Q , B should be calculated from Q ,B (V ) =

√

2εs q ND (−V − ΦB )

(1.6.20)

where V is the voltage at the junction between the P-channel and the N-substrate reduced by the value of Φf . For the specific example (N-substrate), the quantities V and ΦB are negative. In this case, the threshold voltage expression is modified into VT = VT0 + B ·

√

|V − 2Φf | −

√ 2|Φf |

(1.6.19b)

where Φf is given by (1.6.7), B=

√

,

2qεs ND /Cox ,

VT0 = ΦMS − 2Φf −

(1.6.19c) ,

Q ox + Q B0 , Cox

(1.6.19d)

and Q ,B0 = Q ,B (0)

(1.6.19e)

To make these expressions easier to handle, Table 1.6.1 contains the signs of the quantities that enter the above expressions.

1.6.2 MOS Transistor Basically, a transistor with an insulated gate is a resistor whose resistance is controlled by an external voltage (similar to the JFET) and thus achieves a transistor effect. The simplest component of this type is shown in Fig. 1.6.5. It is called an enhancementtype N-channel MOSFET.

176 Table 1.6.1 Signs of the quantities participating in the expression of the threshold voltage

1.6 Insulated Gate Field-Effect Transistors—IGFET Parameter

P-substrate

N-substrate

Metal

−

−

N+

ΦMS for a gate made of Si

−

−

P+ Si

+

+

Φf

−

+

QB

−

+

Qox

+

+

V

+

−

B

+

−

Fig. 1.6.5 Enhancement-type N-channel MOSFET. a Top view and dimensions, b cross section and biasing

The substrate here is a P-type semiconductor in which two N-regions with a high concentration of impurities (N+ ) are diffused. One of them is the source and the other is the drain. The P-type substrate has low impurity concentration. A SiO2 insulator was placed over the P- and N-regions, through which aluminium contacts for the source and drain were applied by vacuum evaporation. In the middle between the source and the drain, over the insulator, a metal representing the gate is applied. The gate is, therefore, isolated from the substrate. To understand the functionality of this component, it should first be borne in mind that both the source and the drain with the substrate form p-n junctions whose depleted regions are practically entirely in the substrate. Therefore, when we look at the structure: source-substrate-drain, we recognize two diodes connected in opposition similarly to a bipolar transistor (emitter–base–collector). The essential difference in comparison with the bipolar transistor is that the substrate is not used as a base. Instead, its surface, in the part between the source and the drain, becomes inverted

1.6.2 MOS Transistor

177

(a channel is formed) so that a resistor of the same type of conductivity as the source and the drain is formed on the surface of the semiconductor. Via this resistor current between the source and the drain may be established. By modulating its resistance with the help of the gate potential, a transistor effect is achieved. For this purpose, the polarization of the transistor is realized in the following way. For an N-channel transistor, the drain is at a more positive potential than the source (V DS > 0), and the gate is at a potential that is at least for the threshold voltage higher than the substrate potential. The following applies to the P-channel transistor: the drain is at a negative potential as compared to the source (V DS < 0), and the gate is at a potential that is more negative by the threshold voltage than the substrate. For the special case when the substrate is connected to the source, when V BS = 0, the gate voltage is measured with respect to the potential of the source. Therefore, V GS > V T is required to establish a channel in an N-channel transistor, and V GS < V T is required to establish a channel in a P-channel transistor. For the N-channel transistor of Fig. 1.6.5, it is assumed that the substrate is connected to the most negative potential in the circuit (−V SS ) or to the source. When V GS < V T , the surface under the gate is a P-type semiconductor, the channel is not formed and no current flows between the source and the drain. When a positive voltage is applied, the gate induces electrons in the surface and inverts the type of conductivity. When the voltage at the gate reaches the threshold voltage (so that for the P-substrate V GS > V T ) the area between the source and drain becomes an N-type semiconductor and acts as a channel. Hence, the name N-channel MOSFET with induced (enhancement) type channel. Roughly speaking, in these conditions, the source and drain are short circuited by the channel. The current between the source and the drain depends on the voltages V DS and V GS . Understandably, the influence of voltage between the gate and the source is dominant. If this voltage increases in absolute value, the number of induced electrons is higher, so the drain current is higher. The reason for this is the fact that this voltage determines the total number of electrons that will be available to form the current. For a given voltage V GS , with the increase of the voltage between the source and the drain, the drain current first increases and then turns into saturation. In saturation (voltage), the drain current does not depend on the V DS but only on the V GS . The phenomena in the channel going on when the drain voltage changes will be discussed later. Figure 1.6.6 shows the output characteristics of an enhancement mode N-channel MOSFET. It should be noted that for V GS = 0 and V DS > 0 the drain current is equal to zero or I D = 0. The characteristics of the MOSFET at negative drain voltages are especially interesting. The course of this characteristic is shown in Fig. 1.6.6 in the third quadrant. Namely, since the MOSFET is a symmetric component, it would be expected that the characteristics behave as odd functions. Why isn’t that so? In fact, it is. The problem with Fig. 1.6.6, when negative V DS , is that when it is negative, the source and the drain swap roles while we still measure V GS from the gate to the source (which is now drain). If we measured V GS from the gate to the drain, we would get a symmetrical characteristic to the one from the first quadrant. Thus, now we get a

178

1.6 Insulated Gate Field-Effect Transistors—IGFET

Fig. 1.6.6 Output characteristics of an N-channel enhancement-type MOSFET

parabolic characteristic because if the potential of the gate is kept fixed, the potential difference between the gate and the new source is constantly increasing so that these are not characteristics for a constant input voltage. The MOSFET is often produced with an N-semiconductor between the source and the drain as shown in Fig. 1.6.7. Modification with respect to the MOSFET of Fig. 1.6.5 is that an N-channel with a lower donor concentration (N) is formed between the source and the drain by implantation. That is why this structure is called MOSFET with built-in (depletion mode) channel. With this type of MOSFET, there are free electrons in the channel as majority carriers even in the absence of positive voltage at the gate. The induced electrons are added to them when the gate is positively biased. With the change of V GS , the total number of free electrons in the channel changes, and thus the conductivity of the channel, which results in a change in the current between the drain and the source. The main effect that is achieved by building in a channel is to program the value of the transistor’s threshold voltage. Namely, depending on the concentration of implanted ions in the area between the source and the drain, the threshold voltage value can decrease and even become negative. Thus, the existence of free carriers in the channel (existence of the channel) even without a special polarization voltage allows V GS to change the sign, i.e., the gate to be at a more negative potential than the source, and still current to flow. Fig. 1.6.7 Depletion-type N-channel MOSFET

1.6.2 MOS Transistor

179

Fig. 1.6.8 Output characteristics of a depletion-type N-channel MOSFET. a the whole field and b in the vicinity of the origin

At positive gate voltages, the depletion-type MOSFET behaves the same as when the channel is induced, because the positive voltage at the gate induces new electrons in the channel, attracting them from the base. When the gate is at a negative potential with respect to the substrate, the number of free carriers in the channel (electrons) decreases by pushing them into the substrate. The holes that are now attracted to the gate electrode do not participate in the conduction of current since the drain-tosubstrate junction is backward biased, so it is conductive only for minority carriers (in the P-substrate, these are electrons). In the case of a depletion mode N-channel MOSFET, therefore, the threshold voltage is negative, so that at V GS = 0 and V DS > 0, I D > 0. The drain current can be reduced to zero if the gate voltage becomes negative and lower (more negative) than the threshold voltage. Typical characteristics of this type of transistors are shown in Fig. 1.6.8a. Figure 1.6.8b shows that this component can also be used as a voltagecontrolled linear resistor. Several MOSFET schematic symbols are in use. They are shown in Fig. 1.6.9. In addition to the source (S), gate (G), and drain (D), the MOSFET can also have a substrate (B of bulk) terminal. This terminal, however, in transistors intended to be put on the market as discrete components, is most often connected to the source as shown in the second line of Fig. 1.6.9. If this is not the case, the value of the potential of the substrate with respect to the potential of the source can have a significant impact on the operation of the transistor even for normal polarization of the substrate, i.e., for backward biasing of the source-to-substrate and drain-to-substrate junctions. If one of these two junctions if forward biased, the operation of the component is practically disabled. It can be seen that the gate is also symbolically separated from the channel. The horizontal line of the gate terminal is shifted to indicate which of the two symmetrical electrodes is considered to be the source. Given the complexity of the complete symbols shown in the first line, Fig. 1.6.9, simplified symbols are also in use. A series of such symbols is shown in the second row of the same image. Let us first consider the first line or complete symbols. The

180

1.6 Insulated Gate Field-Effect Transistors—IGFET

D B

G S D G

D

D B

G S

a

D G

S

S

D B

G S

b

G

S

S

B

G S

c G

D

d

S

Fig. 1.6.9 Symbols for MOSFET, a and b enhancement type, c and d depletion-type channel, a and c N-channel, b and d P-channel

vertical line parallel to the gate refers to the channel. The enhancement mode channel is shown by a dashed line, and in depletion mode MOSFETs that line is solid. The substrate is making two p-n junctions one with the drain and the other with source. Both are normally backward biased. The arrow in the symbol indicates the direction of the diode between the drain and the substrate (or between the source and the substrate). In the second row of symbols, it is assumed that the source is short circuited to the substrate. In addition, instead of using a dashed line for the enhancement-type channel, here the depletion-type channel is denoted by a thicker line. The arrow, now, indicates the natural direction of the source current, which is equivalent to a bipolar transistor. It should be noted that in some documents and books one can find a symbol for an MOS transistor that does not have any arrow which means that the channel type is not specified. In such cases, it is an electronic circuit that is exclusively composed of transistors of the same type of a channel, so it is known in advance what kind of transistors they are. It should also be borne in mind that, most often, the MOS transistor is a symmetrical component. Starting from that, for the bottom row of symbols in Fig. 1.6.5, one can say that the source was determined by the fact that the substrate is attached to it. If the symbol from the first row is used but the horizontal line of the gate terminal is in the middle, in order to conclude which is the drain and the source, one should look to the biasing (direction of drain current determined by the battery) and apply the principle that the source is the electrode where from the carriers start (electrons in N-channel and holes in the P-channel transistor).

1.6.3 Modeling the MOSFET The knowledge gathered so far enables the generation of an analytical expression for the MOSFET characteristic. Figure 1.6.10 illustrates the structure of a P-channel MOSFET. The figure shows a coordinate system and the significant dimensions that will be used later.

1.6.3 Modeling the MOSFET

181

Fig. 1.6.10 Enhancement-type P-channel MOSFET

In the analysis that follows, only the movement of the carriers in one direction (along the y-axis) will be considered, which means that, as with the BJT, the analysis will be one dimensional. It will also be assumed that the electric field component along the x-axis (i.e., the depth of the component) does not affect the movement of the charge along the channel. Consider a small section of the cannel. When the voltage at the gate is equal to the threshold voltage, the channel is just beginning to form. An increase in the voltage above the threshold voltage ΔV G = V G −V T results in an increase in the surface charge for ΔQ , = C , ox ·ΔV G at the gate electrode, and thus the charge of the opposite sign (−C ox ·ΔV G ) on the second plate of the capacitor formed by the oxide. This represents the increment of the corresponding mobile charge in the channel. In the general case, if the voltage drop across the channel is V (from the source to the point with coordinate y), the voltage at the C ox capacitance at that point is V G −V and the mobile charge Q , I in the inverted layer is , Q ,I = −Cox (VG − VT − V )

(1.6.21)

Equivalent to the conductivity of a semiconductor which has been shown to be equal to the product of the mobility and the amount of charge per unit volume [Eq. (1.2.3.51)], a surface conductivity (σs ) is defined here using the surface charge (charge per unit area, C/cm2 ) and the average mobility of the carriers (μp ): , σs = μp Q ,I = −μp Cox (VG − VT − V ) (1/Ω)

(1.6.22)

Based on Ohm’s law, we have J s = σs K y for the surface current density. The quantity K y is a function of the voltage gradient along the y-axis only, K y = dV /dy. If we keep in mind that the surface current density is obtained as the quotient of the current I D and the width of the channel W, we can write ID dV = Js = σs K y = −σs W dy or

(1.6.23)

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1.6 Insulated Gate Field-Effect Transistors—IGFET

ID dy = −σs W · dV

(1.6.24)

After substitution of (1.6.22), one gets , ID dy = W · μp Cox (VG − VT − V )dV

(1.6.25)

Let the voltages of the source and drain with respect to the substrate be denoted V S and V D , respectively. By integration (1.6.25) from y = 0 (source) to y = L (drain), one gets   1 I D = 2 · β (VG − VT0 ) · (VD − VS ) − VD2 − VS2 2

 2 3 3 − B · (−VD − ΦB ) 2 − (−ΦB ) 2 3

(1.6.26a)

where V T was substituted using (1.6.19) and (1.6.20), β=

μp , W C · 2 ox L

(1.6.26b)

and B is given by (1.6.19c). The expression (1.6.26a) is considered the model of the MOSFET. About its versions and limitations there will be discussion later. Often, in electronic circuits, the source of the MOSFET is attached to the substrate. In this case, in (1.6.26), we put V S = 0, so for the current, we get   ID = 2 · β VGS − VT0 − 21 VDS · VDS −

 3

3

− 23 · B (−VDS − ΦB ) 2 − (−ΦB ) 2

.

(1.6.27)

The reader can independently develop appropriate expression for the case when the substrate is connected to the drain. The direction of the current in (1.6.26) was chosen to coincide with the direction of the positive y-axis. The relation (1.6.26) can be simplified if we assume that QB is constant along the channel and given by expression (1.6.17). In that case, instead of (1.6.26), we get ID = 2 · β · [(VG − VT0 )(VD − VS )−

  1 2 VD − VS2 2

(1.6.28a)

and for the case when the source is connected to the substrate, i.e., when V S = 0, instead of (1.6.27), one gets   1 2 ID = 2 · β · (VGS − VT0 )VDS − VDS 2

(1.6.28b)

1.6.3 Modeling the MOSFET

183

where V T0 is given by (1.6.19d). It is possible to create additional simplifications of the expression (1.6.26) or (1.6.27). Let us now mention that (1.6.26) was developed under the condition that the channel exists in the entire length from the source to the drain. Under some conditions, however, this is not the case. Therefore, the characteristics described in (1.6.26) should be recognized as a part of the whole. This part is called the linear or ohmic region of the MOSFET characteristics. Under certain conditions, current can flow even when the channel is not formed in a small part of the surface below the gate. This situation is called saturation (voltage) of the channel (drain) current and represents operating conditions that are different from those prevailing in the ohmic region. Below we will give more details on this operating mode of the MOS transistor. Consider a P-channel transistor with a grounded source (V S = 0) and a fixed voltage at the gate where V G < V T (i.e., |V G | > |V T |). The channel is formed by the fact that the charge in the insulated gate maintains the charge in the channel. This situation at low drain voltages (V DS ≈ 0) is illustrated in Fig. 1.6.11a. The channel acts as a linear resistor and that is why we say that it is a linear region of transistor characteristics. Such characteristics are shown in Fig. 1.6.8b. Fig. 1.6.11 The MOS transistor’s channel. a Linear region (VDS ≈ 0), b ohmic region (VDS < VGS −VT ), c transition (channel interruption) between ohmic region and saturation (VDS = VGS −VT ), and d saturation region with channel shortening (VDS > VGS −VT )

184

1.6 Insulated Gate Field-Effect Transistors—IGFET

Now, let the drain voltage increase in absolute value (the drain voltage is negative). At the beginning, there is a channel of constant resistance between the source and the drain, so I D increases linearly with V D . As V D becomes more negative, the potential (V ), at the end of the channel on the drain side, V DS , also becomes more negative and tends to deplete the drain-to-substrate p–n junction, thus reducing part of the electric field (coming from the gate voltage) which is available for the maintenance of the charge in the channel. So, we have two influences: the effective gate voltage V GS −V T tends to invert the surface and thus form a channel, and the drain potential V DS which tends to deplete the surface and break the channel. This situation is illustrated in Fig. 1.6.11b. Thus, for higher drain voltages, when V DS < V GS −V T is still valid, the value of Q , I close to the drain decreases, the conductivity of the channel becomes lower, so the characteristics are curved and tend to become horizontal. When the condition V DS = V GS −V T is met, the channel is interrupted. Namely, the voltage on the drain is sufficient to neutralize the effect of the effective gate voltage. This situation is illustrated in Fig. 1.6.11c. The drain voltage can increase so much that the electric field in the oxide near the drain becomes insufficient to maintain even the smallest charge in the inverted region. Now the end of the channel on the drain side will belong to the depleted drain-to-substrate junction area. The channel is said to be pinched off as illustrated in Fig. 1.6.11d. Now, between the source and the drain, we have a series connection of the channel whose resistance is relatively small and the depleted area whose resistance is very high. From the moment when pinch off occurs, the entire increment of V DS is taken by the high resistance of the depleted area and therefore the drain current practically does not increase. Voltage saturation occurs. The drain voltage that leads to (voltage) saturation is denoted as V DS sat . When saturation occurs, the current through the transistor is determined by the part of the channel from the source to the interruption. Therefore, assuming that the length of the channel remains the same, the current does not depend on the drain voltage, so it remains constant—it is saturated. Free carriers in the channel (holes) drift under the influence of the electric field that forms the drain voltage. When they get transferred from the channel into the depleted area nearby the drain, they are abruptly attracted to the drain due to the large electric field in this area. Based on these considerations, we can determine the MOSFET model for the saturation region. At the saturation limit, the mobile charge in the inverted area is equal to zero: , Q ,I = −Cox (VG − VT − V ) = 0

(1.6.29)

In this case, V = V DS = V DS sat so that VDS sat = VGS − VT

(1.6.30a)

When considering this expression, it should be borne in mind that V T (given by (1.6.19)) is a function of the voltage V which, in this case, is equal to the potential

1.6.3 Modeling the MOSFET

185

difference between the substrate and the channel (which is connected to the source) V BS . If, for simplicity, it is assumed that V T is constant [as in the execution (1.6.28)] and the voltage V DS sat from (1.6.30a) is substituted by (1.6.28), one gets the value of the saturation currents as IDS sat = A · (VGS − VT )2 = IDSS (1 − VGS /VT )2

(1.6.31a)

where A = 2·β and I DSS = A·(V T )2 . Based on this analysis, we obtained an approximation of the transfer characteristics of the MOSFET in saturation in the same form as in the case of the JFET. However, it should be borne in mind that in a MOS transistor the gate voltage should be (in absolute value) higher than the threshold voltage for a current to flow, so it cannot be said that there is a simple analogy between V T and V p. I DSS does not have the same meaning. To make it easier to understand the meaning of what is said, Fig. 1.6.12a shows the output; Fig. 1.6.12b, the transfer characteristic of an enhancement-type N-channel MOSFET transistor calculated according to (1.6.28) and (1.6.31a); and Fig. 1.6.12c, the transfer characteristic of a depletion-type N-channel MOSFET calculated according to (1.6.31a). Figure 1.6.12d, however, depicts the transfer characteristics of the same transistor when the potential difference substrate-to-source on the threshold voltage is considered. As could be expected, since the threshold voltage increases with the increase in V BS , the transfer characteristic shifts translationally towards higher (in absolute value) voltages at the gate. This change in the threshold voltage has a significant impact on the overall characteristics of the transistor so that it is directly related to the switching off of the transistor (I D = 0). A higher threshold voltage means that a higher voltage is required at the gate for the transistor to start conducting (to switch on). If (1.6.31a) is solved for V GS , one gets VGS = VT ±

√

ID / A

(1.6.31b)

where the upper sign is taken for the N-channel transistor, and the lower for the P-channel. (The reader is warned to pay maximum attention to the explanation of the signs.) This expression indicates that the voltage at the gate can be considered as having two components. One (V T ) would form a channel, and the other would overcome the voltage on the drain that opposes the formation of the channel. Thus, after comparison with (1.6.30a), we identify √ VDSsat = ± ID /A

(1.6.30b)

Note that, as with BJT, the output characteristics at voltage saturation of the actual MOSFET are not horizontal. The reason for this should be sought in the following. The width of the depleted area at the drain-to-substrate junction, which is in fact the depleted area from the pinch off to the drain, is not constant. It depends on the value of the drain voltage. Namely, since the concentration in the drain is much higher

186

1.6 Insulated Gate Field-Effect Transistors—IGFET

Fig. 1.6.12 Computed characteristics of N-channel MOSFET. a Output, b transfer for the enhancement type, c transfer for the depletion type, and d transfer for the enhancement type for different values of potential difference between the source and substrate

than the concentration in the substrate, practically, the change in the width of the p–n junction takes place at the expense of the depleted area in the substrate (for the BJT it was narrowing the base) or on account of the length of the channel. If the length of the channel decreases and the voltage on it remains V DS sat , the electric field on it becomes higher and the carriers accelerate more, which results in an increase in the drain current. Thus, the internal (output) resistance of a MOSFET is not infinite and amounts to several tens of kilohms. Therefore, an expression similar to the one valid for the JFET can be written for the MOSFET characteristic in saturation: ID = A · (VGS − VT )2 · (1 + λ · VDS )

(1.6.31c)

1.6.3 Modeling the MOSFET

187

A typical value is λ ≈ 10–2 V−1 , which means that its reciprocal value (the voltage corresponding to the Early voltage of the BJT) is 1/λ ≈ 100 V. The development of MOSFET model for a depletion mode channel runs similarly to the development given in this section. In that case, the mobile charge Q , I in the channel should be increased by a constant determined by the surface concentration of the built-in (implanted) free charge. Example 1.6.2 For an N-channel MOSFET we know: W /L = (6 μm)/(1 μm), V T0 = 0.7 V, k , = μn C ox /2 = 55 μA/V2 , and λ = 0.04. Find the drain current if V B = V S = 0 V, V D = 3 V, and V G = 2 V. Solution: First, we conclude that the substrate does not affect the value of the threshold voltage and that V T = V T0 , so we determine the mode of operation of the transistor. Since V DSsat = V G −V T = 2−0.7 = 1.3 V, which is smaller than V D , we conclude that the transistor operates in saturation. Thus from (1.6.31c) we calculate ID = A(VGS − VT )2 (1 + λ · VDS ) = 55 · 10−6 ·

6 · 10−6 (2 − 0.7)2 (1 + 0.04 · 3). 1 · 10−6

= 0.62 mA.

1.6.3.1 Models of Short-Channel MOS Transistors The development of integrated circuit technology was aimed at reducing the dimensions of components for several reasons. First of all, smaller dimensions mean an increase in the number of components per unit area, which increases the packing density or reduces the cost of silicon per transistor. Then, the reduction of dimensions leads to a reduction of all capacitances, which increases the upper cut-off frequency of transistor application. Finally, when using MOS transistors, transistor dimension control (W or L) can also control transistor characteristics. Thus, by shortening the channel, higher drain currents can be obtained for the same biasing voltages or, which is the same, the same current can be obtained with lower voltages. Lower voltage, for the same current, means lower dissipation per transistor which further increases the packaging density. Short-channel MOS transistors, because the channel is short, can be considered as components in which the source-substrate-drain structure can be viewed as a bipolar transistor whose base is connected to a fixed potential. The collector current of this BJT is small since it is cut-off. In addition to this, or, in parallel with this, a channel carrying the main component of the current is completely or partially formed between the source and the drain. With this in mind, we conclude that short-channel transistors have some specific properties, so they are given special attention here. Let us first consider the influence of the channel shortening on the threshold voltage of the MOS transistor. As mentioned earlier, the value of the threshold voltage

188

1.6 Insulated Gate Field-Effect Transistors—IGFET

Fig. 1.6.13 Influence of depleted area on depletion of part of the channel before inversion

is also determined by the stationary space charge Q ,B in the channel. The influence of the source and drain depleted regions is such that they already form a part of this charge and when the channel is short that part is no longer negligible as compared to Q ,B , so the required gate voltage is reduced, that is, the threshold voltage for its formation is smaller. It can now be considered that the channel (seen longitudinally) does not have a rectangular but a trapezoidal shape as shown in Fig. 1.6.13. By further increasing the drain voltage, before saturation, the depleted drain region has larger impact, so the threshold voltage is further reduced. It should be noted here that the positive charge in the oxide reduces the threshold voltage of N-channel transistors, so that in order to have a reasonable reproductive value of the threshold voltage, the concentration on the substrate’s surface should be around 1015 cm−3 . This is achieved by local implantation of boron atoms in the shallow surface layer of the substrate. In the case of short-channel transistors, at high drain voltages, saturation of the electron velocity occurs near the drain, where the accelerating field is largest. This results in a change in the shape of the transfer characteristics of the transistor. Namely, if the mobility (in order to keep the speed constant) is inversely proportional to the electric field prevailing in the channel [K = (V DS −V GS + V T )/L], then it can be considered that, in the saturation region, the transfer characteristic is approximately linear: ID =

εox W (VG − VT ) 2 · tox

(1.6.32)

More precise expressions will be given later. Electrons located in a large electric field (K > 104 V/cm) receive more energy than they lose during the scattering process. Therefore, they can be considered to have a higher temperature than the temperature of the crystal: they become hot. Such electrons can have an energy higher than the energy of the upper limit of the conduction band, that is, they can overcome the barrier on the surface of the semiconductor and leave it. In the case of the MOS structure, such electrons can

1.6.3 Modeling the MOSFET

189

penetrate the oxide where they are trapped by the positive charge of the oxide and thus form the gate current, affect the instability of the threshold voltage, and reduce the transconductance of the transistor. In order to reduce this effect, it is necessary to reduce the number of traps (positive charges) in the oxide in a suitable way, which is achieved by case-hardening the oxide at about 400 °C. In the presence of drain voltage, short-channel transistors manifest a number of effects that significantly affect the overall properties of the component. If the channel is short and if the resistance of the substrate is high (concentration of impurities low), it can happen that the depleted areas of the source and drain overlap, even at V D = 0. In this situation, two mechanisms of current conduction are possible: due to the presence of a channel and due to the presence of a N+ -P− -N+ BJT. Of course, only the later component of the current is of interest here. By combining J = −σn K = qnμn K

(1.6.33)

dK /dy = qn/ε

(1.6.34)

and the Poisson equation

after integration, we easily get −dV /dy = K =

√ 2y J/(εμ)

(1.6.35)

After second integration with V = 0 at y = 0 and V = V D at y = L, and by solving for J, one gets   J = (9με)VD2 / 8L 3

(1.6.36)

We can conclude that the additional component of the current formed on the N+ P -N+ diode is parabolic and is similar to the characteristic of the vacuum triode. This means that in the case of overlapping of the depleted areas of the source and the drain, we have a completely new form of the current component. It also flows in the absence of a channel, so special measures must be taken to switch off the transistor. This means that the body of the transistor should be backward biased enough relative to the source to prevent injection of carriers from the source into the substrate. Flow of drain current (I DST ) occurs in absence of a channel even when the depleted areas on the drain and the source are not overlapped. This is the current of the majority carriers of the substrate. For an N-channel transistor, it is a hole current. Since it is a p–n junction current, the dependence of I DST on the voltage (V DS ) is exponential. During the formation of the channel, there is a sharp increase in the surface of the diode, which has the substrate as the P anode and the active part of the transistor (source-channel-drain) as the N cathode. As a result, I DST is growing rapidly. Of course, normally it is smaller than the drain current. Its importance becomes apparent when the transistor needs to be switched off (in order to remain negligibly small, −

190

1.6 Insulated Gate Field-Effect Transistors—IGFET

it is necessary that the voltage at the gate is at least 0.5 V lower than the threshold voltage) or when the drain current is small (in this case I DST must be considered). Having in mind all the effects related to the short-channel transistor mentioned here, we can conclude that such an MOS transistor is a very specific component. It is difficult to believe that the characteristics of such a component can be presented in a closed form. Therefore, analytical expressions are used that originate from those we developed earlier, but also contain modifications related to the corresponding effects. Empirical constants are introduced to weigh each effect. An example of such a model of an MOS transistor will be given below. The previously presented model of MOS transistors (Eq. (1.6.26)) which did not consider the shortening of the channels and the occurrences in short channels, can again be expressed as   2 ID = β · 2(VGS − VT ) · VDS − VDS

(1.6.37)

for the ohmic region and ID sat = β · (VGS − VT )2

(1.6.38)

for saturation, where β= A=

, W μCox W = k, · 2 L L

, k , = μCox /2

VT = VT0 + B ·

√

VSB + 2Φf −

(1.6.39a) (1.6.39b)

√ 2Φf

kT · ln(NA /n i ) q √ , B = 2qεNA /Cox

Φf =

(1.6.40) (1.6.41) (1.6.42)

and , VT0 = ΦMS + ΦB + Q ,ox /Cox

(1.6.43)

ΦMS is given by (1.6.11), ΦB by (1.6.8), and V SB is the potential difference between source and substrate. When working with a short-channel transistor, a modified model for the ohmic region would be ID =

  2 α, · A · 2(VGS − VT )VDS − α, · VDS for VDS ≤ (VGS − VT )/α, (1.6.44a) 1 + θ · (VGS − VT )

1.6.3 Modeling the MOSFET

191

and for saturation ID sat =

  , A · (VGS − VT )2 [1 + λ α/α, )2 VDS 1 + θ · (VGS − VT )

for VDS > (VGS − VT )/α, (1.6.44b)

where VD sat = (VGS − VT )/α,

(1.6.45a)

, VDS = VDS − VD sat

(1.6.45b)

α, = α + γ · (VGS − VT )

(1.6.46)

and VT = VT0 + B ·

√

VSB + 2Φf −

√

√ 2Φf − D VDS

(1.6.47)

New empirical constants α, γ, λ, θ, and D, called short-channel transistor parameters, have been introduced here.

1.6.3.2 MOSFET Model in the Subthreshold Region Before concluding the considerations on modeling of MOS transistors, one more fact should be considered. Namely, when considering the threshold voltage, it was stated that the formation of the channel will occur if the surface is inverted. An important condition is set that the surface is considered to be inverted only if it is strongly inverted. The question arises as to whether drain current also flows for gate voltages whose value is less than the threshold voltage, i.e., for which the surface is inverted but not strongly. The answer is: yes! The mode of operation of the transistor in this case is subthreshold. The drain current in these operating conditions is modeled by an exponential function as   VGS W · exp (1.6.48) ID = ID0 · L n · kT /q where two empirical parameters n and I D0 are introduced, which are usually, for a given technology, determined by measurement. The value of n ranges between 1 and 3.

192

1.6 Insulated Gate Field-Effect Transistors—IGFET

When applying this expression, it should be borne in mind that between the area of weak inversion modeled with (1.6.48) and the area of strong inversion modeled with (1.6.31) or (1.6.38), there is a transition area whose modeling is not that simple. By the way, the operation of the MOSFET under low inversion conditions is of great importance from the point of view of minimizing consumption in amplifier electronic circuits. In some cases, circuits are designed purposely to work in the subthreshold region to minimize dissipation.

1.6.4 Parameters of the MOSFET The most important static parameter of the MOS transistor is the threshold voltage. Although it depends on the applied voltages, the threshold voltage can be considered a parameter because the source is usually connected to the substrate so that V T is practically constant. The following quantity β = A/2 =

μ , W C 2 ox L

(1.6.49)

is often considered as a parameter in the literature. For a given V T , it may be considered as a measure of the drain current. Namely, as we saw earlier with the given technology (gate material, oxide thickness, substrate concentration, oxide charges, oxide dielectric constant), only the dimensions of the transistor remain available to the transistor designer to define its properties. By changing the W/L ratio, the current at the same gate voltage can be increased or decreased. Increasing L also increases the resistance of the channel, so at the same drain voltage we get smaller current and vice versa. Increasing W reduces the resistance of the channel and increases the current. It should be borne in mind that increasing the product W ·L increases the total capacitance of the gate, so to minimize the capacitance and maximize the current, appropriate optimum should be sought. As we will see later (LNAE_Book 5), increasing the surface area of the gate leads to a reduction in the noise of the MOS transistor, so that other optimums can be sought too. The dynamic parameters of the MOSFET are defined in the same way as for the JFET. The essential difference with respect to JFET refers to the need to express the influence of the substrate potential on the drain current. Namely, in the expression for drain current given in (1.6.26), all voltages are expressed with respect to the substrate potential. This also means that V S is in fact V SB , the voltage between the substrate and the source. If the substrate and the source are not short circuited, a change in this potential difference will result in a change in I D . The measure of the ratio of these changes is the transconductance defined with respect to the substrate gmB = ∂ ID /∂ VBS

(1.6.50a)

1.6.4 Parameters of the MOSFET

193

Similarly, to the JFET, for the MOSFET transconductance, we can derive gm =

, √ √ W ∂ ID μCox = (VG − VT ) = 2β(VG − VT ) = 2 β · ID ∂ VGS L

(1.6.50b)

which is obtained by differentiating (1.6.31a) with respect to V G . Here again, for a Pchannel transistor, we get a negative sign for the transconductance since we omitted the negative sign of the current. In (1.6.50a), the absolute value should be taken. Similarly, for the internal resistance, we have   1 + λVDS ∂ ID 1 ∂ VDS = = 1/ ≈ rD = ∂ ID ∂ VDS λID λID

(1.6.50c)

The value of the transconductance gm = ∂I D /∂V GS is of the same order as for JFET, and the internal resistance is much lower and is of the order of tens of kilohms. The input resistance, however, due to the insulated gate is very high and reaches 1010 –1012 Ω. As with all semiconductor components, the current of the MOSFET depends on the temperature. Here, too, with the increase of temperature two tendencies are experienced. First, with increasing temperature, the mobility of the carriers in the channel decreases, which results in a decrease in current. On the other hand, with increasing temperature, the threshold voltage decreases (about 40 mV/K), which results in an increase in current. The threshold voltage decreases mainly due to the increased concentration of minority carriers in the substrate at increased temperature. In normal biasing, when the voltage at the gate is not too close to the threshold voltage, the mobility is of dominant influence, so it can be said that the drain current of the MOS transistor has a negative temperature coefficient. To display the temperature properties of the MOSFET, the following quantity is usually used: k, =

μ , C 2 ox

(1.6.54)

This quantity is called the conductivity factor. Figure 1.6.14a shows the normalized dependence of k , on temperature, where T = 25 °C is taken as the nominal temperature. The change in temperature is mainly due to the decrease in the mobility of free carriers in the channel with the rise of temperature. The dependence of the threshold voltage increment on temperature is shown in Fig. 1.6.14b. Bearing in mind that ΔV T is significantly smaller than V G in (1.6.50b), i.e., ∂(V GS + ΔV T ) ≈ ∂V GS , we conclude that the change in V T practically does not affect the change in the transconductance, so that the temperature dependence of the transconductance is determined only by the temperature dependence k’ and that Fig. 1.6.14a gives the dependence of the transconductance on temperature at the same time.

194

1.6 Insulated Gate Field-Effect Transistors—IGFET

Fig. 1.6.14 Temperature properties of MOS transistors. a Dependence of the conductivity factor and b dependence of the threshold voltage

1.6.5 Active Operation Area of the MOSFET As with other types of semiconductor components, the most important limitation in the operation of a MOSFET is the maximum power dissipated on the drain PDmax . This line is depicted in Fig. 1.6.15 in brown. Exceeding this power leads to exceeding the maximum temperature, which can catastrophically affect the characteristics of the transistor. Unless special measures are taken due to the relatively small crosssectional area of the channel, the current of the MOSFET is small so that the MOSFET is a low-power component and usually this limitation is not critical (more material related to power MOSFETs will be given in LNAE_Book 4). The phenomenon of secondary breakdown does not manifest itself in MOSFETs. The minimum current is equal to zero and occurs when the voltage at the gate is less than the threshold voltage. Here it should be borne in mind that the channel is Fig. 1.6.15 Active (and safe) operation area of a MOSFET

1.6.5 Active Operation Area of the MOSFET

195

established, i.e., that the surface is inverted, gradually so that even at voltages that are slightly lower than the threshold voltage, the drain current is already flowing, albeit very small. In addition, the MOS transistor in conditions when the channel is not formed can be considered as a PNP or NPN structure whose base is the substrate, and the source and drain are the emitter and collector, respectively. During the normal biasing of the MOS transistor, I CE0 flows between the source and the drain, which is small since the base width is relatively large. The maximum current is limited similar to JFET which is depicted in Fig. 1.6.15 by a dashed green line. The maximum voltage on the drain is determined by the breakdown of the p– n junction between the drain and the substrate. It is an avalanche breakdown of an inversely biased p–n junction. The value of the breakdown voltage (BV DB = Breakdown Voltage between the Drain and the Bulk, as denoted in Fig. 1.6.15) depends on the concentration on both sides of the junction and is measured in tens of volts. Here we will point out an additional effect related to BV DB that adds to the ones discussed above and is related to short-channel MOSFETs. In the case of an N-channel MOS transistor with a short channel, after a breakdown on the drain, there is a sharp decrease in voltage and an increase in current, similar to a BJT. The amount at which the voltage on the drain V DS0 is stabilized depends on the voltage at the gate and decreases with increasing V G . This phenomenon is related to the existence of a parasitic N+ -P− -N+ structure parallel to the MOS transistor so that the body of the component (P-type) plays the role of the base of the bipolar transistor. During the breakdown, part of the drain current passes into the substrate and creates a voltage drop on the resistance of the substrate’s body, which biases forward the source-to-substrate junction, which completely corresponds to the situation with the BJT where the body resistance of the base played the same role. The minimum voltage on the drain V Dsmin is determined by transition to the ohmic region, which can be seen in Fig. 1.6.15. When the voltage between the drain and the source drops below the value V DS = V GS −V T (for N-channel transistor), a dashed line shown in red in Fig. 1.6.15, then for the same increments of V GS , we get smaller current increments (the transconductance decreases) and therefore this area does not belong to the active area of the transistor. As can be seen from Fig. 1.6.6, the minimum voltages reach values of several volts. The above definition of the minimum voltage is often considered too restrictive, i.e., the minimum voltage so defined is too large. Instead, especially when the transistor is operating as a switch, one first goes for the value of the RDSon . This is the reciprocal to the slope of the tangent to the output characteristics in the origin as depicted in Fig. 1.6.15 in blue. When built in a circuit (e.g., amplifier) the voltages and currents of the MOSFET obey the so-called load line (which will be discussed in LNAE_Book 2). In such cases, the abscissa of the interception of the load line and the RDSon line defines the V DSmin . The value of RDSon is of order of ohms for low-power transistors and milliohms for high-power transistors. This practically describes the complete active area of operation of the MOSFET, which has the same shape as the active area of operation of the BJT depicted in

196

1.6 Insulated Gate Field-Effect Transistors—IGFET

Fig. 1.4.19. Similar as the one depicted in Fig. 1.4.23, with proper changes of the numbers, is the safe operating area of the MOSFET. It will be discussed in more detail in LNAE_Book 4. This transistor, however, has another limitation that needs to be considered. Namely, due to the small thickness of the oxide, even at relatively low voltages at the gate, very large electric fields can be created in the oxide and electrostatic breakdown can occur. For example, for t ox = 10–7 m and V = 100 V, we get a fantastic value of 109 V/m (one gigavolt per meter) which, of course, causes a breakdown. In this case, the component is permanently damaged. In fact, usually, a tiny tunnel is created between the gate and the substrate which is from inside covered by melted metal and consequently is conductive. That creates gate current which influences the response at the input of the transistor and may have a total failure as a consequence. It is interesting that at these voltages there is a relatively small charge on the gate, due to the low capacitance of the oxide, and that this charge can be created when handling the transistor if the gate is not grounded. Therefore, when the MOS transistor is manufactured as a discrete component, the operator and the tools must be earthed for the entire time of operation. In cases when it is not the most important to preserve a very high input resistance of the MOSFET, when designing a discrete transistor, a Zener diode is bult in parallel between the gate and the source, which is backward biased during normal operation of the MOSFET. The breakdown voltage of the diode is chosen so that the diode breaks down rather than the gate. Since the diode breakdown process is reversible, the gate is protected. In turn, the inverse current of the diode now flows between the gate and the source before the breakdown, during normal operation, which means that the input resistance of the transistor is reduced. With MOS digital integrated circuits, we find slightly modified protection against electrostatic breakdown. We will finish with the warning: the drain-too-substrate junction must always be backward biased to prevent the transistor to behave like a conducting diode.

1.6.6 Capacitances of the MOSFET MOSFET is a complex component so that more capacitances are formed in it having different nature. An illustration of these capacitances is given in Fig. 1.6.16. The capacitance C ox is the capacitance of the oxide. As we saw earlier, it is nonlinear, i.e., it abruptly changes its value during the formation of the channel, which is shown in Fig. 1.6.2. In linear circuits, when there is a constant biasing of the gate, and the variable component of the signal is small in comparison to the biasing, this capacitance can be considered constant. In digital and pulse circuits, when the transistor is led from the cut-off to the ohmic region through the active region (saturation), the capacitance changes its value. Figure 1.6.16 shows the situation when the transistor is saturated, so it can be seen that most of this capacitance is connected to the source via a conductive channel.

1.6.6 Capacitances of the MOSFET

197

Fig. 1.6.16 MOSFET capacitances in saturation mode

In addition, between the gate and the source and between the gate and the drain, there are two capacitances named overlap capacitances. Namely, in order to be sure that the metal of the gate will cover the entire channel, it is usually expanded on both sides so that it partially covers the source and drain. In this way, two very small capacitances are formed, which are indexed here with the letter “o”. The MOS transistor has two p-n junctions and two corresponding capacitances. Since these p-n junctions are always backward biased, these are space charge capacitances of the source-substrate (C tSB ) and the drain-substrate (C tDB ) junction. These capacitances are of course nonlinear and when there is an alternating component of the voltage on the drain (or source) they change their value according to the change of the signal. Finally, when the channel is formed, depleted area between the channel and the substrate is formed, and thus the space charge capacitance C tCB . Figure 1.6.17a shows a MOSFET viewed as a component with its capacitances. These capacities include those of Fig. 5.1.16. C GS consists mostly of C ox but contains also C oGS . C GD mostly consists of C oGD , and when the transistor is biased in the ohmic region, when the channel is not interrupted, it also contains a part of C ox . C DB is in fact C tDB (when the transistor is biased in the ohmic region so that the channel is not interrupted, it also contains part of C tCB ). Finally, C SB contains C tSB and C tCB . Fig. 1.6.17 a Equivalent MOSFET capacitances, b P-channel MOSFET model for large signals

198

1.6 Insulated Gate Field-Effect Transistors—IGFET

It is not difficult to conclude that C SB is in fact the largest capacitance in the transistor because it includes both the source-to-substrate and the channel-to-substrate junctions. This is the most important reason the source is usually short circuited to the substrate. When the source is connected to the bulk, this capacitance disappears, and C DB becomes C DS . Unlike the JFET, here we have an inevitable and relatively large capacitance between the drain and the source. Integrated MOS transistors have low capacitances. The reason for this is the small areas of the transistors which are determined by the length (L) and the width of the channel (W ), and the “lengths” of the source (L S ) and drain (L D ) as depicted in Fig. 1.6.5. Thus, the following numbers can be considered realistic and typical: C GS = 5 fF, C GD = 10 fF, C DB = 30 fF, and C SB = 50 fF. In discrete transistors, the capacitances of MOSFETs are of the order of picofarads, with C DS being the largest and C GD the lowest. Due to the relatively large capacitances, especially in transistors with a large channel width when the surface area of the source and drain increases, the upper cut-off frequency of MOS transistors as discrete components is lower than in bipolar ones. Having in mind the capacitances, it is possible to construct the electrical schematic of the MOS transistor model for large signals. For a P-channel transistor, such a schematic is shown in Fig. 1.6.17b. As can be seen, with respect to Fig. 1.6.17a, the symbol of the transistor is replaced by the resistive part of the MOSFET model consisting of a current source I D (natural current direction) from the source to the drain and two diodes DBS and DBD representing the junctions of the substrate with the source and the drain, respectively. This schematic is equivalent to the circuit diagram of the Ebers–Moll model in Fig. 1.3.8. It can be extended by the resistances of the drain and source bodies in the manner shown in Fig. 1.3.9 for a bipolar transistor.

1.6.7 Dual-Gate MOSFET As mentioned earlier, the capacitance between the output (D) and input (G) terminal of the transistor is of great influence on the behavior of the component at high frequencies. The reason for this is the fact that this capacitance creates a return path of the signal from the output to the input. Reduction of this capacitance increases the upper cut-off frequency of application of a given component. In the case of MOS transistors, this is achieved by moving the drain away from the gate. In order to create the conditions for the current to continue to flow, however, a conductive path is provided between the channel and the drain by introducing a continuation of the channel. The formation of this second channel is controlled by a new additional metallization—the second gate. This is how the dual-gate MOSFET shown in Fig. 1.6.18a is created. The first and second channels are connected by one N+ area. Gate 2 is usually at a fixed potential, and in addition to the biasing, the signal which will be processed is brought to Gate 1. In this way, Gate 1 and Drain are separated so that C G1D becomes very small, about 0.005 to 0.02 pF. The schematic symbol of the

1.6.7 Dual-Gate MOSFET

199

Fig. 1.6.18 a Dual-gate MOSFET, b symbol, c output characteristics, and d transfer characteristics

dual-gate MOSFET is shown in Fig. 1.6.18b. It is an enhancement-type transistor. Finally, Fig. 1.6.18c and d show the characteristics of one dual-gate MOSFET. As can be seen, the output characteristics are measured for a fixed (most suitable) value of the potential of the second gate, which is denoted here V G2S . The transfer characteristics are measured for a fixed value of the drain potential, as for all FETs, but differ for different values of the potential of the second gate. With this in mind, the drain currents can be considered a function of the potential of both gates.

1.7 MESFET

1.7.1 The Device MESFET is a component that is similar to MOSFET in its construction while in its mode of operation it is closer to JFET. The main difference with respect to the MOSFET relates to the way the gate is attached. Namely, the oxide is omitted so that the metal gate is applied directly to the semiconductor (hence the name MEtal Semiconductor FET) and forms a Schottky diode. Thus, in a MESFET the gate is not isolated which makes it different from the MOSFET and at the same time no p–n junction is used which makes it different from the JFET. In addition to the mentioned differences, since it is not necessary to form a p–n junction, GaAs is easily used in this component (mobility of holes in GaAs is so small that the production of the bipolar component becomes irrational) as a substrate material (channel) applied to the highly resistive wafer (unlike MOS structures). At reasonably small fields, GaAs has significantly higher electron mobility, which enables obtaining components with a higher transconductance and higher cut-off frequency (shorter propagation time from source to drain). On the other hand, the high-resistance wafer makes the parasitic effects less pronounced compared to the substrates that are significant in MOS transistors. In this way, components are obtained (in modern times also integrated circuits) whose upper cut-off frequency is of the order of tenths of GHz. To understand the operation of the MESFET, we will first consider the characteristics of a silicon component to point out the differences between silicon and GaAs, especially in the case of a short channel. Figure 1.7.1a shows the current–voltage dependence of a thin layer of N-type silicon grown on an insulating wafer. Ohmic contacts of the source and drain are applied to the surface of the conductive layer. Applying positive V DS (between the outer terminals) results in current generation. For low voltages, the thin film acts as a linear resistor, but for larger fields the electron drift velocity does not rise as fast as the electric field. Therefore, the current–voltage characteristic starts bending downwards (below a straight line). When V DS continues to rise, the critical value © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 V. Litovski, Lecture Notes in Analog Electronics, Lecture Notes in Electrical Engineering 1002, https://doi.org/10.1007/978-981-19-9868-3_7

201

202

1.7 MESFET

of the field at which the electron reaches the saturation velocity is soon reached, as shown in Fig. 1.7.2. Due to this, the drain current becomes saturated. Figure 1.7.1b shows the situation that occurs when a metal gate is applied to the surface of a semiconductor so that a Schottky diode is formed. Refer to Fig. 1.3.2.23 for the energy diagram of a metal–semiconductor junction which should help in understanding Fig. 1.7.1b. A depleted area is formed below the gate the depth of

Fig. 1.7.1 Dependence of current on voltage for N-type semiconductor layer. a Characteristics of N-type layer, b N-type layer with V GS = 0, c N-type layer with V GS = 0 and V DS = V DSsat , d N-type layer with V GS = 0 and V DS > V DSsat and e N-type layer with V GS < 0

1.7.1 The Device

203

Fig. 1.7.1 (continued)

Fig. 1.7.2 Equilibrium drift velocity in Si and GaAs

which depends on the height of the barrier (work function difference) at the metal– semiconductor junction. This depleted area has the same effect as the insulating wafer, i.e., restricts the flow of current through the N-substrate. If a voltage is applied to the gate, the height of the barrier can be controlled, and thus the lateral (source

204

1.7 MESFET

to drain) current through the component, thus achieving a transistor effect. Note, since no interventions were made related to the local concentration of the majority carriers at the metal–semiconductor surface, the depleted region is formed automatically. Hence, this is an enhancement-type transistor. The rest of the discussion in this chapter will be devoted to this type of component. Its main property from the application point of view is that it conducts for V GS = 0. Speaking in the terminology of switching, it is normally ON. As we will see in more detail soon, its functionality is very similar to the JFET. Alternatively, one may obstruct the current for V GS = 0 by reducing the concentration in the substrate (bringing E fSi down to E fi in Fig. 1.3.2.23a) so that the depleted region goes deep into the wafer. Of course, small D is needed, too. In that case one would need a large positive gate voltage to attract electrons from the deep of the substrate and to reduce the depth of the depleted region so allowing the current to flow. That would be a depletion-type MESFET. When the gate is connected to the source, as in Fig. 1.7.1b, we have a similar situation as in Fig. 1.7.1a with the fact that the channel is now thinner. If we introduce the labels W –for the channel width, d(x) for the channel thickness, and v(x) for the drift velocity we may write: ID = qW · n(x) · d(x) · v(x)

(1.7.1)

where x is the distance from the source towards the drain. For field values that are less than the critical (K C ) the electron concentration in the channel is n = N D . Since the drain is at a higher potential than the source (so far V GS = 0), the depleted area is wider on the drain side. Bearing in mind that the same current flows through all parts of the channel, where the channel is thinner, the current density is higher, so it is necessary for the field to be larger. This means that the velocity of the carriers increases in this part of the channel. A further increase of the drain voltage causes the electrons to reach their maximum speed vs below the end of the gate that is closer to the drain. This situation is shown in Fig. 1.7.1c. In this case, the channel reaches a thickness of d 0 , and the drain voltage reaches its saturation value V DSsat . Thus, the characteristic enters the area of voltage saturation. As the drain voltage increases, the depleted region expands so that the point (x l ), at which the velocity saturation occurs for the first time, moves towards the source as in Fig. 1.7.1d. As x moves towards the source, the potential of point x l decreases and the channel expands, which means that the resistance of that part of the channel decreases, so more current will be injected into the area of the channel where the speed is saturated. Thus, the I DS curve has a positive slope with finite dynamic resistance from the drain to the source even after saturation. To the right of x 1 , the potential of the channel increases as it widens the depleted area and thins out the channel. In order for the current to remain constant since the speed is saturated, the concentration of carriers in this part of the channel changes. Thus, we conclude from (1.7.1) that between x 1 and x 2 , where d < d 1 , a space charge of electrons should occur in order for the increase in concentration to neutralize the decrease in the channel thickness. At x 2 , d = d 1 and in order to maintain a constant current the space charge changes

1.7.2 MESFET Model for Large Signals

205

sign. Due to the additional field created by the negative space charge in the region between x 2 and x 3 , the electron velocity is still saturated. Let us now consider the situation when a negative voltage is applied to the gate. In this case, the depleted area expands (Fig. 1.7.1e). For small V DS values, again, the channel acts as a linear resistor which is now larger than in the case when there was no gate or when the gate was at the source potential. Therefore, the critical field is reached at a lower drain current than for V GS = 0. Now we may conclude that for the gate to have effective control of the channel current, the gate length L must be larger than the channel depth, D, or L/D > 1. This requires a channel depth on the order of 0.05–0.3 μm for most GaAs MESFETs. The small channel depth requires that the carrier concentration in the channel be as high as possible to maintain a high current. If we wanted to repeat this analysis for the case with GaAs as the basic material, we would have a more complex situation, mostly because the equilibrium velocity of the electron as a function of the electric field reaches a maximum value for a field of 3 kV/cm, and then decreases to the level of saturation rate corresponding to the saturation rate of electrons in silicon. This diagram is shown in Fig. 1.7.2. Some effects are also important, which are expressed only at very short gate lengths ( 1.9

a The 2014 Nobel Prize in Physics was awarded to Isamu Akasaki, Hiroshi Amano, and Shuji Nakamura for the invention and development of efficient GaInN blue LEDs

Let us now consider the electrical characteristics of LEDs. Figure 1.8.30a shows the dependence of the current on the applied voltage. This line does not differ in shape from the characteristic of a silicon junction diode, but, considering that a material with a larger energy gap is used, it is shifted towards higher forward biasing voltages. For a GaAs diode (whose characteristics are shown in this figure), the forward (normal) biasing voltage is about 1.2 V. For diodes radiating in the visible range, it is about 2 V. Figure 1.8.30b represents the dependence of output (light) power as a function of current at constant forward voltage for room temperature. It is easy to see that

1.8.2 Light Sources

247

Fig. 1.8.30 a GaAs LED characteristic, b Output power as a function of current, and c normalized output power as a function of junction temperature. The user is advised to pay attention to the scales (logarithmic or linear) in these diagrams

in a very wide range of currents there is a (almost) linear dependence between the emitted power and the diode current. During recombination, as already mentioned, we do not always get a photon, but sometimes the recombination is done gradually by the emission of phonons. If the temperature is higher, this phenomenon is more frequent so that with the increase in temperature, the emission of light power decreases according to the hyperbolic law. This dependence is shown in Fig. 1.8.30c. It can be said that the power output has a negative temperature coefficient (if the current is kept constant). However, this should not be confused with the positive temperature coefficient of the current at constant voltage. Other optical characteristics of LEDs refer to the spatial angle of radiation, which depends on the method of production, and is typically around 30 spatial degrees, as well as to the width of the radiation spectrum (Fig. 1.8.29), which in the case of GaAs is around 40 nm. As with all other components the LED’s area of operation is limited. The maximum inverse voltage is small and amounts to about 5 V (in order for recombination to be intense, a high concentration is required, so the breakdown voltage is small), the maximum current is less than 100 mA at a voltage of 1.2 V, which is related for heating the diode and reducing the radiation power. Due to the small width of the depleted area, the space charge capacitance is large so that during pulse operation it affects the upper cut-off frequency of the signal that excites the LED. The efficiency of LEDs is low. Starting from Fig. 1.8.30 for a current of 50 mA, the dissipation power is Pd = v·i = 12·50·10–3 = 60 mW. The emitted power is, however, P = 550 μW. So, for the efficiency we get η = (P/Pd )·100 = 0.92%. Due to the increased dissipation power, however, the diode is heated according to (1.3.2.34). If Rth = 500 K/W for the dissipation power just calculated at ambient temperature T = 25 °C, we get T J = 61 °C. Now we can correct the value of the

248

1.8 Optoelectronic Components

Fig. 1.8.31 Polarization of an LED that illuminates a photodiode

radiated power and the efficiency. For T J = 61 °C, we get P = 0.7·550 μW = 385 μW and η = (385·10 6/60·10 3)·100 = 0.62%. In cases where the ambient temperature is increased or when it is necessary to obtain a higher light output, measures must be taken to reduce Rth . It is of interest the effect that can be achieved by the power of the light generated by an LED. For this purpose, let us consider the circuit of Fig. 1.8.31 where the LED is biased by a V = 10 V battery and illuminates the photodiode. We will determine how much power per unit area can be obtained if the photodiode is located at a distance d from the LED. Let us first consider the value of the resistor used for biasing. If the voltage on the diode should be V d = 1.2 V and if the current through the diode is I d = 50 mA, we get R=

8.8 V − Vd · 103 = 176 U. = Id 50

(1.8.18)

As we said, the total radiation angle of this diode is θ = 30 spatial degrees or π/6 sterad. At the distance d, a circular surface of S 0 = 1 cm2 would represent a spatial angle: / ( ) θ0 = 2 · arctg S0 / π · d 2 = 2 · arctg(0.56/d), where d is given in centimeters. Since it is θ0 /θ = P0 /P we easily get P0 = P0 =

2P · arctg(0.56/d). θ

(1.8.19) θ0 θ

· P or

(1.8.20)

Of course, this relation is only valid as long as θ0 < θ. For d = 2 cm, one gets P0 =

2 · 385 · 10−6 · 0.27 = 397 μW. π/6

(1.8.21)

Now, based on Fig. 1.8.6b, we can make conclusions on the effect that can be realized when the current of the photodiode that is illuminated is considered. Since H = P0 /S 0 = 397/1 (W/cm2 ), a current of I p = 86 μA is obtained for this photodiode.

1.8.2 Light Sources

249

Fig. 1.8.32 Circuit for temperature stabilization of LED radiated power

LED polarization as shown in Fig. 1.8.31 is common and most frequent. However, if it is desired to ensure temperature stability of the radiated power, it is necessary to increase the current through the diode when the temperature rises in order to compensate for the drop in radiation power (here, naturally, the LED’s dissipation power increases and if this is not tolerable, the diode should be cooled so reducing Rth ). A simple circuit that performs this function is shown in Fig. 1.8.32. Here, the positive temperature coefficient of the collector current of the BJT is exploited. With a suitable choice of Rth , the change in collector current with temperature can be made to be approximately reciprocal to the drop in the radiated power of the LED. LED, as already mentioned, is also used as an indicator. In this case, the indicator that contains seven diodes arranged in such a way that all ten digits can be generated by selecting two (to display the digit 1), three (7), four (4), five (2, 3, 5, 6, 7), six (0), and seven (8) LEDs that will light up. This combination is called a seven-segment display. To display a number with more digits, as many seven-segment displays as there are digits are needed. Thus, a six-digit number requires six displays with seven diodes each. All LEDs will light up if the number 8 is displayed. So, for the number 888888, 42 LEDs will light up. For I d = 50 mA, this indicator will require P = (50·10−3 A)·(1.2 V)·(42 diodes) = 2.52 W, which is of course a large power and therefore such indicators are not used in battery-powered equipment [for a 10 V battery the total battery dissipation due to additional power consumption on the biasing resistors would be 42·(10)·(50·10–3 ) = 21 W] but only in stationary devices connected to the grid.

1.8.2.1.1 White LED Light Sources LEDs discussed so far emit monochromatic light. White LEDs, by definition, emit polychromatic light. Therefore, these are referred to as “solid-state lighting” and are used in place of applications which are traditionally using conventional white light sources (incandescent and fluorescent lamps). Speaking from the advance of science point of view, one should appreciate this discovery having in mind the eternal human aspiration to impersonate the Sun (e.g., The Sun King).

250

1.8 Optoelectronic Components

Fig. 1.8.33 Three diodes (LEDs) producing white light

Note, white light has a spectrum which covers the range of blue, via the green up to the red color. These three light intensities are added equally to generate the white light. Generally, there are three approaches to produce white light. The first one is illustrated in Fig. 1.8.33. Here, three chips of red, green, and blue color LEDs are mounted on a single wafer preserving very small dimensions and distances. Every diode has its own voltage supply like any LED while the cathodes are connected together. Since the distance is very small and so are the sizes of the chips the resulting light seen from outside of the component is white. Apart from the occupied area, the need for three supply voltages makes this technology difficult to implement and serious research was made in order to produce a new, compact component using single supply. To simplify, that was achieved using an electroluminescent component which emits a near-ultraviolet light and a fluorescent material which absorbs the ultraviolet light and emits a fluorescence in a visible light range from blue to red. One may say that conversion of a single-color light into broadband white light is performed. The functionality of this second method is illustrated in Fig. 1.8.34a. Here an LED-generating ultraviolet, violet, or blue light (see Table 1.8.4) is used to illuminate a slab (in fact, the LED is immersed into the slab) of phosphor which emits a fluorescence in a visible light range from blue to red. It is said that the phosphor is performing downconversion (of frequency) when producing the green and red components. Having in mind that the red light has a much larger wavelength than the violet (or even the blue) one may say that large frequency shift (large Stokes shift) is needed to produce white light in this way. That is, the efficiency of conversing blue into white light is not perfect, on the contrary.

Fig. 1.8.34 Phosphor-based white light production. a Full conversion and b partial conversion

1.8.2 Light Sources

251

The most successful way is to use a blue LED chip exciting phosphor which emits green and red light. Its blue light is partially absorbed by the phosphor, and the other part of the blue light passes through the phosphor. Use of blue-emitting GaN chips in combination with luminescence downconverting inorganic YAG:Ce phosphor was reported. YAG stands for yttrium aluminium garnet. The structure is depicted in Fig. 1.8.34b. It performs partial conversion. As a result, the blue light (from the LED chip), green light (from the phosphor), and red light (from the phosphor) together form white light. Nowadays, LEDs remain the fastest growing and developing lighting technology. Large arrays of LEDs emitting white light are put together (in series and parallel) to form a lamp competing the existing incandescent ones. The ability to produce light directly from electrical energy without intermediate steps (e.g., heating) leads to important improvements in efficiency. Since these structures are solid-state devices, another advantage of LEDs is their long lifetime. It was estimated that the largescale introduction of solid-state lighting enables decrease of the electrical power consumed by lighting by more than 50%, amounting to global annual electrical energy savings exceeding 1 000 TWhr. Accordingly, the luminous flux per package in the last 50 years was risen 105 times, while the price expressed in USD/lumen fell almost 107 times (note, 1 lux = 1 lm/m2 ). One is not to forget that LED lighting is based on DC supply. That is usually not a problem when used in portable devices albeit even there some accommodation of the supply voltage is necessary (some kind of DC-to-DC converter). When applied for home and industrial lighting, however, one needs first (as any electronic equipment does) an AC-to-DC converter (regulated rectifier) in order for the lighting to function. Usually, the latter conversion circuit is embedded inside the housing of the new “valve” so that in real life we have as many AC-to-DC converters as the number of devices is. Hence, the price of the converter, which, by the way, limits the lifetime of the whole, must be low. If, however, not special attention is paid to the quality of the converter from distortion point of view, it (there are so many of them, maybe billions at the moment of writing of this text) may seriously pollute the grid by impregnating higher harmonics and so interfering (with negative consequences) with everyone connected to the grid.

1.8.2.2 Semiconductor LASER Diode LASER is one of the light sources that has an increasing importance. The development of LASERs has an increasing influence on industrial and scientific technological development. It can be implemented in several ways, but only the so-called semiconductor injection LASER, the principle of operation of which is close to other optoelectronic components, will be considered here. It is considered that the injection LASER is one of the most significant discoveries of the second halve of the last century.

252

1.8 Optoelectronic Components

LED, as the only source that is discussed in detail here, as well as other sources that are available to us every day, are characterized by spontaneous or incoherent radiation of light. This means that the emitted light contains several spectral components, and the phase positions of the electromagnetic waves that make up the ray are mutually independent. LASER radiation, on the other hand, is almost pure monochromatic radiation. The width of the spectrum in semiconductor lasers, where electrons move between energy bands, is a few tenths of a nm, and in gas lasers, where electrons “fly” between levels, the spectrum width is measured in tens of pm. The phase of the electromagnetic wave is dependent on the phase from the previous or next moment. This kind of radiation is called coherent, and the component that generates it is called a LASER, which comes from light amplification by stimulated emission of radiation. The possibility of LASER radiation arises from the quantum mechanical principle which states that during the interaction of electrons and photons there is an equal probability: (a) that the photon will be absorbed and the electron will remain excited or (b) if the electron is already excited, another photon will be emitted, but one that has the same wavelength, phase, polarization, and direction of propagation as the first one. So, the original photon is amplified. The electron naturally falls from its excited state to a lower energy state. Both of these situations are shown symbolically in Fig. 1.8.35. We immediately conclude that materials with an indirect energy gap cannot be used as a LASER material. Whether the original photon will be absorbed or amplified depends on whether most of the electrons are in an excited or unexcited state (in the case of semiconductor LASER, whether they are in the valence band). If most of the electrons are in an excited state, we have a situation called population inversion. It cannot occur if special measures are not taken to communicate sufficient energy to the electrons before the LASER radiation occurs. Population inversion in the vicinity of the p–n junction can be achieved at high impurity concentrations by means of a high direct current (hence the injection LASER). The current at which the LASER emission starts is referred to as the threshold current (I th ). Further rise of this current will bring more intensive emission so that it is then called drive current. In fact, a large number of injected carriers create an area close to the junction in which there is a very large number of electrons in

Fig. 1.8.35 Interaction of photons and electrons. a there is no population inversion, the photon is absorbed and generation occurs and b there is population inversion, so the original photon stimulates the emission of another

1.8.2 Light Sources

253

the conduction band, and at the same time, there is a very large number of holes in the valence band due to impurities. The recombination is intensive and photons are produced. The former, instead of being absorbed or emitted, stimulate the emission of new photons. In this way, the initial radiation is created. In order to get a LASER component, it is necessary to have so-called feedback, i.e., it should be ensured that the photons obtained in this way become coherent with each other. This is achieved by forming an optical resonator. Namely, the photons created in this way spread through the crystal, reach the wall of the resonator, and are reflected from the inside by the surface of the crystal, which acts as a mirror. Now they again pass through the region where the population is inverted and stimulates the emission of new photons (amplify) that are coherent with them. They reach the other wall and are partially reflected so that a stronger and stronger emission of coherent light is created. As already mentioned in order for LASER radiation to occur, it is necessary to reach a certain value of direct current. This value is called the threshold current. The threshold current (I th ) density for a GaAs diode, for example, is about 50 kA/cm2 at room temperature or 5 kA/cm2 at 77 K. Therefore, this laser cannot practically work at room temperature, but at the temperature of liquid nitrogen and even then, with special measures and working conditions. When viewed as components, the best InGaAsP lasers, at a wavelength of 1.3 μm, have a threshold current of 10 mA at a temperature of 106 K. The optical power, when the current exceeds the threshold current, becomes a linear function of the current with a typical slope of 0.5 W/A. This issue will be discussed in more detail later. We will here interrupt the discussion on the very functionality and efficiency of the LASER diode in order to shortly explain how the optical resonator is created within the component. The light refraction is governed by Snell’s law which states that, for a given pair of media having refractive indices n1 and n2 , the ratio of the sines of the angle of incidence φ1 and angle of refraction φ2 is equal to the ratio of the refractive indices, i.e., sinφ1 n2 = . sinφ2 n1

(1.8.22)

Figure 12.8.36 illustrates the three situations that happen when a light ray is falling onto a boundary surface of two materials. First, as shown in Fig. 1.8.36a, the incident ray falling to the boundary under the angle φ1 is partly reflected under the same angle and partly refracted under the angle φ2 . The angle φ2 is calculated as ( φ2 = arcsin

) n1 sinφ1 . n2

(1.8.23)

Obviously the angle of refraction cannot exceed 90°. If we put φ2 = 90° and denote the critical incident angle as φ1 = φc from (1.8.22), we get

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1.8 Optoelectronic Components

Fig. 1.8.36 Explanation of reflection, refraction, and total internal reflection

( ) n2 . φc = arcsin n1

(1.8.24)

This situation is depicted in Fig. 1.8.36b. The arcsin function producing φc is defined only if n2 ≤ n1 . Hence, for isotropic media (the ones where n1 and n2 do not change within the proper material), total internal reflection (as in Fig. 1.8.36c) can occur if the second medium has a higher refractive index than the first. We will relate now this knowledge to the semiconductor properties. Namely, it was proven in the literature that the refractive index of a material is related to the energy gap of the semiconductor. Specifically, for II-V compounds, the following (among several others) was proposed: n=

/ 4

1 + 40.8/E g2 ,

(1.8.25)

where E g is substituted in eV. This is an important relation explaining how one can construct a boundary between two semiconductor materials that enables total reflection which, as we already mentioned, is crucial for creation of a semiconductor injection LASER. It says that materials with a larger bandgap will have a smaller index of refraction for the same wavelength of light. In the next, we will consider an example LASER diode whose structure and dimensions are depicted in Fig. 1.8.37. The energy gap of In1-x Gax Asy P1-y used as the active region of the LASER is given by E g (x, y) = 1.35 + 0.642x − 1.01y + 0.758x 2 + 0.101y 2 − 0.159x y − 0.28x 2 y + 0.109x y 2 eV.

(1.8.26)

Table 1.8.5 contains limiting values of E g and n of II-V compounds participating in In1-x Gax Asy P1-y obtained for xe(0,1) and ye(0,1). We will add to Table 1.8.5: n(0.48,0.24) = 3.4555 which was taken from the literature since (1.8.25) is not valid for In1-x Gax Asy P1-y . If so, at the In0.52 Ga0.48 As0.24 P0.76 (n1 ) and InP (n2 ) interface, the critical incident angle would be φc = 39.62°.

1.8.2 Light Sources

255

Fig. 1.8.37 Laser diode: a working principle and definition of the surfaces and b heterojunction and InGaAsP diode

Table 1.8.5 The energy gap and refraction index of II-V compounds participating in In1-x Gax Asy P1-y

The energy gap (in eV) and refraction index of In1-x Gax Asy P1-y x=0

x=1

y=0

E g (InP) = 1.344 n = 2.20378

E g (GaP) = 2.75 n = 1.5902

y=1

E g (InAs) = 0.441 n = 3.810325

E g (GaAs) = 1.511 n = 2.0842

Let us go back now to the functionality. Light losses occur due to radiation to the outside and due to reabsorption of photons inside the semiconductor body far from the outside where there is no population inversion. If these losses become smaller than the light amplification by means of stimulated emission, the number of photons and the intensity of the light will increase very quickly while the high current of the diode will continuously renew the inversion of the population. Since the losses increase with the increase in light intensity, this process will stabilize at the value at which there is a balance of losses and amplification. The way of making a semiconductor LASER diode (or semiconductor injection laser), in principle, will be shown on the example of an InP laser from Fig. 1.8.28a. The surfaces marked with A are very well polished and completely parallel to each other. The latter is achieved by a suitable choice of crystallographic planes. When the light reaches these walls from the inside, about 30% is returned due to the change in the refractive index, and that is enough to exceed the losses. The rest is emitted as coherent light. Wall B is deliberately roughened to prevent the formation of a second resonator. The properties of the LASER diode are most frequently expressed via the socalled L/I curve. It relates the drive current versus the light output. One set of such characteristics measured for four different temperatures is depicted in Fig. 1.8.38. This figure also illustrates the value of I th (being about 20 mA for T = 25 °C) and its temperature dependence which is serious. Of course, the ordinary I/V characteristic is also of interest. It is depicted in Fig. 1.8.39. Note the large threshold due to the large energy gap of the material used. It is a custom when depicting this characteristic in literature to swap current and

256

1.8 Optoelectronic Components

Fig. 1.8.38 Optical power versus driver current for different temperatures of a laser diode

Fig. 1.8.39 Characteristic of a laser diode

voltage since the driver current is considered independent variable when describing the LASER diode. We find that unnatural since, still, the voltage is the cause of any current. The laser efficiency is typically expressed as η = 0.3 mW/mA at room temperature and decreases by about 0.01 for each 10 °C. Typical figures for wavelength variations with respect to voltage may be around 0.1 to 0.5 nm/°C, but this is mostly dependent upon the device, its frequency, and a number of other considerations.

1.8.3 Optocouplers The combination of a light source and a photodetector in the same housing has led to a very useful family of components commonly called optocouplers. The name comes from the fact that light is used for signal-coupling two electronic systems. Since, however, the light source (transmitter) circuit and the photodetector (receiver) circuit are electrically isolated one can use the term optoisolators too. Some components from this family are shown in Fig. 1.8.40. It can be seen that virtually any combination of source and detector is possible. The main purpose of these components is the isolation of two electronic circuits, which enables separation of the grounding of

1.8.3 Optocouplers

257

Fig. 1.8.40 Elements with light coupling: a LED/photoresistor, b LED/photodiode, c LED/photoBJT, d LED/photo-Darlington, e LED/photo-SCR, and f LED/photodiode and a BJT as an amplifier

the transmitting and receiving parts. The coupling is realized via photons instead of charged particles and therefore significant advantages of these components arise: – Due to the fact that photons are not subject to the influence of magnetic and electric fields, the isolation is significantly better than using transformers or inductive coupling. – Signal transmission is unilateral, which means that a change in operating conditions in the load circuit does not affect the input (exciting) circuit. – The operating speed of these circuits (upper cut-off frequency) is significantly higher than the speed of other types of couplings. The basic parameters of the optoisolator are current gain (or current transfer ratio—CRT), isolation voltage, upper cut-off frequency, the input current, and the maximum allowable output voltage. The current gain (CTR) is the quotient of the output current and the input current and is usually given as a percentage. The value of the current gain ranges from 0.2% for the LED/photodiode given in Fig. 1.8.31b, over 100% for the LED/photo-BJT of Fig. 1.8.31c, to 600% for the LED/photo-Darlington of Fig. 1.8.31d. The isolation voltage is the voltage at which an electrostatic breakdown occurs between the transmitter and the receiver. These are in fact coupled via the coupling capacitance and the leakage resistance. Most optoisolators are designed so that the transmitter and receiver are very close, separated only by a transparent layer of SiO2 with a coupling capacitance of 0.01 pF and a typical isolation voltage of about 1 kV. Optoisolators designed for higher voltages use optical fibers to reduce the coupling capacitance. In such cases, an insulation voltage of 50 kV is reached. The bandwidth (or the upper cut-off frequency) must be known to understand the maximum data rates that can be used with an optocoupler. The slowest (the ones with smallest bandwidth) are the LED/photoresistor-based components depicted in Fig. 1.8.40a. Their cut-off frequency is only a few tens of Hz. The ones that use photo-BJT (depicted in Fig. 1.8.40c) may have a bandwidth of 250 kHz, while those that use photo-Darlingtons (depicted in Fig. 1.8.40d) may only have a tenth of that.

258

1.8 Optoelectronic Components

The fastest is the LED/photodiode (depicted in Fig. 1.8.40b) which reaches several tenths of MHz. Generally speaking, the lower the CTR, the faster the rise and fall times. The input current importance comes from the fact that it defines the value of the biasing resistance for a given supply voltage of the input circuitry. The maximum allowable output voltage is defined by the type of the output component. In high-voltage applications, usually, the optocoupler is separated from the high-voltage circuit by a high-voltage amplifier. The most important characteristic of the optoisolator is the transfer characteristic (CTR), which represents the dependence of the output on the input current at a fixed output voltage. This characteristic for three different temperatures for the LED/photoBJT is shown in Fig. 1.8.41 together with the structure of the component itself. It can be seen that the temperature coefficient of the CTR (for the temperatures cited in the figure) is negative, which means that at higher temperatures for the same transmitter current we have a lower receiver current. In fact, in some components, the temperature dependence of the efficiencies of the transmitter and the receiver compete with each other so that at temperatures below zero CTR rises with temperature. This should be especially considered in applications where it is important for the functionality of the device that the output current exceeds a certain threshold. Note that the signal transmission from the input to the output for the LED/photoresistor coupling is characterized by the quotient of the increment of the resistance of the photoresistor and the increment of the current of the LED. This coefficient is of the order of 10 kU/A. On the other hand, for the LED/photo-thyristor from Fig. 1.8.40e of interest is the minimum input current that enables the firing of the thyristor. Finally, let us say that it is possible to integrate the photodiode and the amplifier together and thus retain the advantages of the LED/photodiode coupling in terms of speed, and correct the shortcomings in terms of current amplification. The simplest case of such a solution is shown in Fig. 1.8.40f. Here, the current gain

Fig. 1.8.41 a Example structure of an optoisolator using LED/photo-BJT and b transfer characteristics (current transfer ratio) of the optoisolator

1.8.3 Optocouplers

259

Fig. 1.8.42 Optoisolator in the electrical (transmitting part) and electronic (receiving part) circuit

is around 20%, the cut-off frequency is around 1 MHz, and the isolation voltage is around 2.5 kV. Since there will be no other opportunity within the LNAE series, we will here try to exemplify the implementation of the optocouplers by two examples. The method of applying this component in the electronic circuit, which serves to indicate the presence of grid voltage, is shown in Fig. 1.8.42. The circuit is excited by the mains voltage so that R is determined similarly to the circuit in Fig. 1.8.31, R = (1.41·220–1.2)/I p . In the negative half-cycle, the LED is backward biased, and since the maximum inverse voltage is small, an ordinary junction diode must be connected, which will become forward biased and thus protect the LED. In the output circuit, the emitter current of the transistor from the optoisolator excites the amplifier which converts the current into a voltage signal. The circuit that follows reacts at the moment of the excitation or at switching on the mains. The second example is related to a circuit which is most frequently encountered in modern renewable energy electrical power sources. Namely, as is the case with solar systems, other convertors of energy available in nature are producing DC voltage at the output. That voltage, preferably with a changed value, is used as DC supply while in most cases is inverted into AC voltage and (expectedly) connected to the grid. The electronic circuits performing DC-to-DC transformation are named converters while the ones that perform DC-to-AC transformation are named inverters. Part of such a system is depicted in Fig. 1.8.43. In any case, the system consists of the following stages. The DC voltage, here V DD , is brought to a pair of power MOS transistors (N-channel) connected in series. These transistors are alternatively switched on and off supplying or sinking current from the next stage which is built of an LC filter which is further loaded by proper load. The amplitude of the voltage at the output may vary and gets measured and compared with a given reference to produce an error signal which is used as a seed for creation of a controlling signal fed back to the pair of transistors. The error is, in fact, impregnated into the width of the rectangular pulses of a sequence by a pulse width modulator. Hence, PWM signal. P W M is its complement. That signal is now convenient to control the switching of the MOS transistors.

260

1.8 Optoelectronic Components

Fig. 1.8.43 MOSFET gate drive circuit of a DC-to-DC converter

The problem is, however, that the PWM signal is produced in a low-voltage (including digital) environment which is not compatible with the controlled highvoltage and high-power system. The solution to bringing the PWM signal to the gates of the MOS transistors is use of optocouplers as depicted in Fig. 1.8.43. Do note the need for separate supply voltage (V CC ) for the optocouplers. The part of the circuit left of the MOS transistors is frequently referred to as a gate drive. What we discussed here is a very simple example of a gate drive.

1.9 Magnetoelectronic Components

1.9.1 Introduction The flow of electric current through semiconductor elements by itself indicates that, if the component is in a magnetic field, there will be effects related to the Lorentz force. Namely, an electron with velocity v, which moves in a magnetic field of induction B, is acted upon by a force: F = q · (v × B)

(1.9.1)

and if the angle between the direction of the current (or the velocity of the carriers) and the magnetic induction is not equal to zero, the electrons will be deflected (hence the need of vector notation in (1.9.1)). This phenomenon forms the basis of the operation of all electronic components that are used to measure or recognize the magnetic field. There are more and more such components in professional and consumer devices. Depending on the application, the source of the magnetic field can be a permanent magnet where the induction can range from 10–5 T (for thin magnetic layers) to several Tesla in some motors, or a variable magnet, i.e., the magnetic field of an electric current where, for example, a conductor through which 1 A flows has an induction of 10–4 T on its surface. Based on this, we can make conclusions about the sensitivity of the components that should serve for measuring the magnetic field. Before considering different types of components from this area, a basic theory will be given about the influence of the magnetic field on the semiconductor through which the current flows (if the diffusion component of the current is excluded, the conclusions would, in general, also apply to conductors). For the sake of simplicity, a three-dimensional geometry will be considered in which the magnetic induction has the direction of the z-axis, and the voltage on the semiconductor is connected at its ends along the x-axis so that in the absence of a magnetic field the current flows only in the x-axis direction. Therefore, the external electric and magnetic fields form a right angle independent of the direction of the field and current. The situation is illustrated in Fig. 1.9.1. If the magnetic field is considered, the expression for the © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 V. Litovski, Lecture Notes in Analog Electronics, Lecture Notes in Electrical Engineering 1002, https://doi.org/10.1007/978-981-19-9868-3_9

261

262

1.9 Magnetoelectronic Components

Fig. 1.9.1 A semi-conducting plate in a magnetic field

current density through the semiconductor changes and instead of (1.2.3.58) for the electron current density, the following applies: Jn (B) = Jn (0) − μ∗n [Jn (B) × B]

(1.9.2)

where Jn (0) is given by (1.2.3.58), B is the magnetic induction (or the magnetic flux density), while μ∗n is the Hall mobility which is proportional to μn in the following way: μ∗n = rn μn .

(1.9.3)

The quantity r n is the scattering factor and represents the quotient of the statistical mean squared and the squared statistical mean value of the electron flight (between two collisions) time. r n is slightly higher than unity (for silicon at room temperature r n ≈ 1.15) and depends on the temperature. For r p , however, approximately 0.7 was obtained. An equation similar to (1.9.2) can also be written for holes. It represents the so-called galvanomagnetic effect and simultaneously contains the influence of the magnetic field on both the drift current and the diffusion current. When (1.9.2) is solved for Jn (B) one gets: Jn (B) = σnB [K − μ∗n (B × K )]

(1.9.4)

where σnB = σn /[1 + (μn * B)2 ]. Here it should be kept in mind that due to the removal (shifting) of electrons from the main direction (x-axis), additional components of the electric field and current in the x–y plane appear. Therefore, we have | ( )| Jnx = σnB K x − μ∗n B · K y

(1.9.5a)

| | Jny = σnB K y − μ∗n (B · K x ) .

(1.9.5b)

Based on these relations, it is possible to identify most of the secondary phenomena that occur in a semiconductor due to the magnetic field. Let us first consider the case when the flow in the y-axis direction is disabled (J ny = 0). From (1.9.5b), we get that between the sides of the semiconductor wafer, along the y-axis, an electric field called the Hall field is obtained:

1.9.1 Introduction

263

K y = −μ∗n B · K x = RH Jnx B

(1.9.6)

and the very phenomenon of the Hall effect. In (1.9.6) one should put: RH = −μ∗n /σn = −rn /(q · n)

(1.9.7)

where RH is the Hall coefficient. The minus sign in (1.9.6) and (1.9.7) indicates the fact that the rear part of the tile (Fig. 1.9.1) is at a higher potential than the front (along the y-axis). To the electric field, K y corresponds a potential difference called the Hall voltage. By substituting I = J nx ·W ·d from (1.9.6) we get: VH = K y W =

rn RH ·B·I = · B · I, d q ·n·d

(1.9.8)

where I is the current that (from outside) enters the plate (and flows out of the plate) along the x-axis. The existence of an electric field along the x- and y-axes results in bending of the equipotential and current lines in the crystal. The amount of bending of these lines is given by: tg(θH ) = K y /K x = −μ∗n B = σn RH B

(1.9.9)

tg(θH ) = K ny /K nx = −μ∗n B = σn RH B.

(1.9.10)

or

Figure 1.9.2 illustrates the deformation of the lines. It is easy to conclude that if the sample is narrow (L >> W ), the deformation of the current lines is insignificant compared to the deformation of the field lines. The Hall effect is dominant. So, under the condition L >> W, the Hall voltage is proportional to the magnetic induction. In the opposite case, when W >> L, it can be said that the sample is very short and that the Hall voltage is practically short-circuited by the external electrodes. Therefore, if L > L) is a parabolic function of the magnetic induction. This effect will be identified as magnetoresistive.

264

1.9 Magnetoelectronic Components

Fig. 1.9.2 Illustration of the influence of the magnetic field on electric field lines (vertical) and current lines (horizontal)

The previous considerations were related to the doped semiconductor in which the concentration of one type of carrier dominates. If this is not the case, i.e., if the semiconductor is weakly doped, for the Hall coefficient we have: RH = −

rn (μn /μp )2 n − rp p ) ( q · [ μn /μp · n + p]2

(1.9.11b)

Let us now imagine a situation where the magnetic field acts in the direction of the y-axis. The carriers are now deflected in the z-axis direction. Two cases are of interest. First, when the concentration of one type of carrier is dominant, the possibility that on one side (upper or lower) carriers can leave the wafer is of interest. In this way, the bending of the current lines leads to a direct effect on the number of carriers that will reach the contact plate on the x-axis at the end of the tile. This also affects the current at the other end. The current at the output of the plate depends on the magnetic field. We say that the bending effect dominates. The second case refers to a very weakly doped semiconductor where the upper and lower surfaces are treated differently so that the recombination speed on one (upper or lower) is higher than on the other. During the effect of the magnetic field on the carriers, there will be a change in the concentration of carriers towards the surface due to different recombination. If the magnetic field acts in the direction of the y-axis, Fig. 1.9.3 illustrates two characteristic cases of concentration dependence along the z-axis, where the lower side of the tile (z = 0) has a higher recombination rate. This phenomenon is called magnetic concentration. The existence of a concentration gradient in the direction transverse to the movement of the carriers results in a change in the current through the tile. In this way, another way of coupling the magnetic field and the semiconductor current is realized. In addition to the four phenomena listed here: the Hall effect, the magnetoresistive effect, the effect of bending, and magnetoconcentration, some other phenomena can be identified which, however, are of very specific interest and will not be discussed here. It is important to say that the electronic components in which these effects are manifested are usually complex enough to manifest several effects simultaneously. At the same time, with commercially available components, one effect

1.9.2 Hall Generators

265

Fig. 1.9.3 Illustration of magnetic concentration: a Bx < 0 and b By > 0

dominates. Therefore, in further considerations, four types of components that identify the presence of a magnetic field and which we will call magnetoelectronic or magnetogalvanic components will be considered.

1.9.2 Hall Generators By installing contacts on the sides (with coordinates (L/2, 0, d/2) and (L/2, W, d/2)) to the tile from Fig. 1.9.1, it is possible to measure and use for other purposes the Hall’s voltage. Such a component is called a Hall generator. It is important that the length of the contacts be significantly smaller than L (which we said is also significantly larger than W ) so that the contacts do not short-circuit the longitudinal plate and thus effectively reduce its length. Based on (1.9.8), we conclude that when making this kind of generator, one should choose as thin a plate as possible. In addition, in order for the Hall voltage to be as high as possible, one should choose a plate with a very low concentration of the majority carriers. Finally, if we go back to (1.9.6), we can easily conclude that the Hall voltage will be higher if the carrier mobility is higher. This tells us that we should choose materials with high mobility such as InSb, InAs, and InAsP. Given that the real component cannot fully fulfill the condition L >> W and given that the contacts are not infinitely short, instead of (1.9.8) we use: VH =

RH · G · I · B, d

(1.9.12)

where G is a geometry-dependent correction factor which, for example, for (L/W ) > 3, G → 1. There are a number of practical implementations of the Hall generator. Let us first consider a plate that generates a Hall voltage for itself. Figure 1.9.4a shows one of the possible ways of making a tile. It is characteristic of this configuration that the pairs of contacts can swap functions. Figure 1.9.4b shows the dependence of the Hall voltage (normalized with the device current) as a function of the magnetic induction (V H /I = RH G·N/d) for different values of the load resistance connected between the

266

1.9 Magnetoelectronic Components

Hall’s contacts. It is not difficult to calculate that the internal resistance of the Hall generator is about 2 y. A measure of the sensitivity of the Hall generator can be seen from the dependence shown in Fig. 1.9.4c. The temperature dependence of the Hall coefficient for three materials is shown here. One can see the unsuitability of InSb due to its pronounced temperature dependence, although at room temperature it exhibits a very high RH . Recently, of great interest are components that can be made using standard technological procedures used in the production of integrated circuits and components that can work together with an integrated circuit so that the obtained signal may be amplified or processed on the same chip. Hall generators made of silicon or gallium arsenide are of interest from that point of view. One solution using a silicon wafer and a standard bipolar process is shown in Fig. 1.9.5. Figure 1.9.5a represents a cross-section of the component. The role of the wafer is played by the epitaxial layer of the collector (of standard bipolar technology as described in Chap. 1.10), in which four emitter diffusions are embedded in pairs perpendicular to each other: two long ones for the current contacts and two shorter

Fig. 1.9.4 Hall plate. a appearance, b normalized dependence of Hall voltage on induction and c dependence of Hall coefficient on temperature

1.9.2 Hall Generators

267

for the Hall voltage contacts. The current contacts are parallel to the plane of the drawing and are not visible in this picture. In this way, Hall tiles are obtained whose approximate dimensions are W = 200 μm, L = 400 μm and 5 < d < 10 μm. For the sensitivity of the Hall generator, it is important to achieve n·d = 1013 cm−2 . It is also important to keep in mind that the thickness (d) of the plate depends on the width of the depleted area of the p–n junction established between the substrate (P) and the collector diffusion (N). This is another cause of component temperature instability. Figure 1.9.5b depicts a simplified representation of a system which is using a Hall generator. There are three parts in it. First, one needs a voltage source (e.g., battery)

Fig. 1.9.5 Hall generator in a bipolar integrated circuit. a cross-section, b principle diagram of the coupling of the Hall generator and amplifier and c the output voltage as a function of the magnetic induction

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1.9 Magnetoelectronic Components

which is supplying the necessary current in a strongly controlled manner. Then comes the very Hall component which is, finally, followed by a voltage amplifier. The latter has to have two important properties. First, it has to have a very large input resistance so as not to disturb the functionality of the Hall generator and, it has to amplify the voltage difference between the input terminals. The last property is expressed by the plus and minus signs near its input terminals. Figure 1.9.5c depicts the transfer characteristic of a circuit built as in Fig. 1.9.5b. As one can see, thanks to the amplifier used, the output voltage in absence of magnetic induction is large enough to allow connection to the circuitry that performs further processing. From this figure, we may read that S H = ∂V out /∂B ≈ 15 V/T. Of course, one is not to miss the fine linearity of this transducer (at least for the given measurement conditions). When measuring the magnetic field that is parallel to the semiconductor surface, a vertical Hall generator should be used as shown in Fig. 1.9.6. The component is relatively complex, but the functionality itself is simple. In an N-plate (a CMOS integrated circuit easily accepts such a component) the component area is defined by a relatively deep P-diffusion (p-well) that forms a backward biased p–n junction. Within this area, five N bands are diffused so that the central one forms one layer, and the two outermost layers form the second layer of the Hall tile. The shape of the current lines is shown in the picture. Hall plate contacts are placed laterally in relation to the current flow. Of course, part of the carriers is also collected by the Hall contacts so that there is a potential difference between them even in the absence of a magnetic field. The value of the contact current is usually determined externally so that the voltage drop between the contacts and the potential of the contacts in the absence of a magnetic field are exactly determined. For an external current of 0.5 mA, the measured slope of the dependence of V H on B was about 300 mV/T. The MOS structure is very suitable for making a Hall generator in an integrated form. It is only necessary to expand the MOS transistor by two contacts laterally in relation to the source-drain line. An example of a component using an N-channel transistor is shown in Fig. 1.9.7. For this component, the channel width (W ' ) is usually chosen to be close to the channel length L, so (W ' /L) = 1.2 applies. It is important to note that it is not desirable for the transistor to operate in the region of voltage Fig. 1.9.6 The structure of a vertical Hall generator

1.9.2 Hall Generators

269

Fig. 1.9.7 MOS Hall generator. a cross-section and b top view

saturation in order not to pinch-off the channel. Thus, part of the area between source and drain would be lost to the Hall effect. On the other hand, considering that the Hall voltage is proportional to the current, it is not desirable to work in the linear region, since the sensitivity would be reduced. A compromise is achieved by choosing V DS = V GS . In this case, the components with the induced channel (enhancement mode) work in saturation (but at the limit), and the components with the built-in channel (depletion mode) in the ohmic region (also at the limit, but on the other side). In both cases, the depth of the channel, which here represents the depth of the Hall plate, is not uniform on the way from the source to the drain i.e., the tile along this line is not symmetrical. This leads to the conclusion that the contacts should be moved towards the drain area (l/L > 0.5). For example, for a component with L = W ' and l/L = 0.8, V H /B·I = G·RH /d = 103 V/(AT) was obtained, where G is still the shape factor. When the drain voltage is used instead of the current to characterize the component, the following expression for the Hall voltage is used: VH = G ·

W' · μ∗ · VDS B. L

(1.9.13)

Here, it should be considered that μ* is in fact the surface Hall mobility, which is about two times smaller than the mobility in the body of the semiconductor. In addition, μ* is a function of the electric field i.e., gate voltage. The measured characteristic of the MOS Hall generator is shown in Fig. 1.9.8. The resulting voltage is about 10% lower than the one calculated from (1.9.13).

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Fig. 1.9.8 Characteristic of the MOS Hall generator

1.9.3 Magnetoresistors As shown earlier, for a very short tile (W >> L) the dominant effect is magnetoresistive. The approximate dependence of the specific resistance on magnetic induction is given by (1.9.11). Components that are intended for the conversion of magnetic induction into a change in resistance are called magnetoresistors. Discrete magnetoresistors are made in a form of a series connection of a set of parallel strips of indium on a plate of InSb. It is also possible to make a narrow plate of InSb that has inside (parallel to the main axis) needles of NiSb, which has significantly higher specific conductivity. The dimensions of the needles are 1 × 50 μm. The number of inserted needles controls the resistance in the absence of a magnetic field. Figure 1.9.9a shows the appearance of a magnetoresistor consisting of six parallel-arranged, series connected strips, and Fig. 1.9.9b the corresponding characteristic. R(0) is the resistance of the sample in the absence of a magnetic field and reaches several ky. The schematic symbol for a magnetoresistor is depicted in Fig. 1.9.9c. The slanted line signifies a variable resistor in general, while the x denotes that it is magnetoresistor.

Fig. 1.9.9 Discrete magnetoresistor a appearance, b normalized characteristic, and c schematic symbol

1.9.4 Magnetodiode

271

The temperature coefficient of such resistors depends very little on the induction and is of the order of –0.2 (%/K). Magnetoresistors are also made on silicon as a substrate in the form of a thin film, and in this case, ferromagnetic materials are usually used. Such is, for example, NiFe which contains 80% Ni and 20% Fe or NiCo with 76% Ni and 24% Co. It is significant for these components that they reach high sensitivity even at low fields (B ≈ 10–2 T) with a temperature coefficient of 0.3%/K. Given that they are made of silicon, they can be connected to an amplifier circuit like the previously mentioned Hall components. In this case, four magnetoresistors connected in a bridge are usually used. In one diagonal of the bridge, a power supply is connected while in the other a voltage proportional to the induction is obtained. In order for the bridge to become asymmetric when a magnetic field appears, the resistors are not arranged in parallel on the plate but have a suitable arrangement. Very recently giant magnetoresistance (GMR) based components were introduced. GMR is manifested in multi-layered structures in which ferromagnetic and non-magnetic conductive layers are alternately stacked. Important changes (almost 80%) in the resistance as a function of the magnetic induction were reported. These components are out of the scope of this book.

1.9.4 Magnetodiode In the case of a magnetodiode, of dominant influence is the effect of magnetoconcentration, which is illustrated in Fig. 1.9.3. This effect is best expressed in the structure shown in Fig. 1.9.10. It is a P+ N– N+ diode with double injection. Namely, when the voltage is applied, holes (P+ ) and electrons (N+ ) are injected into N− . In addition, the top and bottom surfaces of the diode have a significantly different recombination rates. This can be achieved either through the difference in the mechanical fineness of the surface (scratching one surface and polishing the other) or through increased recombination on the surface of the diode where it rests on the substrate.

Fig. 1.9.10 Diode with double injection

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The following approximate relation is obtained for the magnetodiode current: I =

9 V2 W · L · q · μn μp τeff (n 0 − p0 ). 8 L3

(1.9.14)

In this relation, n0 and p0 are the equilibrium concentrations of electrons and holes in the N region, and τeff is the effective lifetime of the carriers. This quantity is highly dependent on the magnetic field, that is, the very principle of the influence of the magnetic induction on the diode current is expressed through the dependence of the effective lifetime. Two examples of how to make a magnetodiode in integrated circuits are given in Fig. 1.9.11. Figure 1.9.11a shows a magnetodiode made in standard CMOS technology, and in Fig. 1.9.11b shows a section of a silicon magnetodiode on sapphire (SOS stands for silicon-on-sapphire). Dependence of τeff on magnetic induction for a given ratio of recombination speed on surfaces S1 and S2 is shown in Fig. 1.9.11c, and d presents the characteristics of the diode depicted in Fig. 1.9.11b. In the case of the magnetodiode from Fig. 1.9.11a, the Si/SiO2 surface on the upper side forms a surface with low recombination, and the junction of the substrate and the P-well form a surface with a high recombination rate. In the latter case, the electrons that overcome the barrier at the p–n junction are collected at the terminal C, which is equivalent to their recombination. The magnetodiode from Fig. 1.9.11b has a Si/Al2 O3 surface that actually represents a surface with a high recombination rate.

1.9.5 Magnetotransistors The complexity of the structure and mode of operation of transistors, especially BJTs, allows them to produce all the secondary effects caused by the magnetic field once they are exposed to it. By magnetotransistors, however, here we will mean the components where the carrier lines bending effect is by far the most dominant. Such components can be made both as lateral structures (in that case they have a double collector (drain)) and as vertical structures (bipolar only). Figure 1.9.12a shows a MOS transistor with two drains, and Fig. 1.9.12b BJT one with two collectors. In both cases, the magnetic field acts perpendicular to the surface of the semiconductor so that bends the lateral component of the current according to its intensity and direction. The dual-drain MOSFET shown here is often called a MAGFET. The essence of the mode of operation is that in the absence of a magnetic field, drain 1 and drain 2, due to symmetry, have equal currents, and when a magnetic field is applied, due to the action of the Lorentz force on the carriers in the channel, increase of one at the expense of the other happens. If the drains are connected to the same potential through equal resistors due to the difference in the drain currents, a potential difference will appear between them. An effect is obtained which is characteristic of the so-called differential amplifier.

1.9.5 Magnetotransistors

273

Fig. 1.9.11 Magnetodiodes. a cross-section of a magnetodiode in CMOS technology, b crosssection of a magnetodiode in SOS technology, c dependence of the effective lifetime on magnetic induction for a given value of the ratio of recombination speed on the lower and upper surface, and d characteristics of magnetodiodes made on sapphire (n0 = 1015 cm−3 )

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Fig. 1.9.12 Magnetotransistors with lateral current flow. a MOSFET with two drains (split drain MOSFET) and b BJT with two collectors (split collector BJT)

Bipolar transistors with two collectors as in Fig. 1.9.12b work on a principle that is practically identical to that of a MAGFET. However, there are some specifics that need to be clarified. In the case of an ordinary BJT, the base area is narrow in order to obtain the most important parameters of the transistor: the current gain coefficient and the cut-off frequency. Such a component cannot serve as a magnetotransistor because the magnetic field is not given space to act on the carriers. Therefore, in the case of magneto-BJTs, it is necessary to increase the width of the base. In order to prevent all minority carriers from recombining in the area of the base and thus losing the transistor effect, two contacts are installed in the base (denoted B1 and B2 ) to which voltage is supplied so that inside the base, in the space between the emitter and the collector, we have a built-in electric field. It makes the minority carriers to drift. It is significant that the collector N-epitaxial layer can be used as the base area in standard bipolar technology, so that this component is easily integrated. A bipolar magnetotransistor with two collectors can also be realized in a vertical configuration. Here, however, a structure that has only one collector will be considered. A simplified version of the vertical magnetotransistor is shown in Fig. 1.9.13a, while Fig. 1.9.13b represents its more complicated version. Figure 1.9.13c depicts an electronic circuit that models the latter structure. The component is designed to be produced in a CMOS integrated circuit. In the N− plate which has N+ diffusion for the contact (S), a P-well is made by diffusion. The two P+ diffusions (B1 and B2 ) form the terminals of the two bases, which have the same role as in the lateral component with two collectors. The source of the MOS transistor is the emitter (E)

1.9.5 Magnetotransistors

275

of the bipolar one, and the drain is the collector (C). The auxiliary terminal of the gate (G) brings the surface between the emitter and the collector in a depleted state so that there is no surface current, which drastically reduces the so-called 1/f noise. This is the only role of the gate. The magnetic field acts perpendicular to the plane of the drawing. As can be seen from Fig. 1.9.13c this component essentially has two collectors though. The first is N+ diffusion in the P-well and is marked with C, and the second is the N− substrate with N+ contact which is marked with S. It is also easy to conclude that a large part of the injected carriers from the emitter will be accepted on the second collector (S) due to the fact that the surface of the base (P-well)-collector (base) junction is large. The accelerating field between the bases helps to improve the current distribution in favor of the C terminal current (I C ). Under the influence of the magnetic field, the carriers are displaced upwards (I C increases) or downwards (I S increases). The characteristics IC (IE )|IB =C te for two values of the magnetic induction are shown in Fig. 1.9.14.

Fig. 1.9.13 Lateral magneto-BJT. a cross-section of a simplified version b cross-section of the full version c equivalent circuit

276 Fig. 1.9.14 Characteristics of the magnetotransistor from Fig. 1.9.13

1.9 Magnetoelectronic Components

1.10 Basics of Semiconductor Technology

1.10.1 Introduction The simplified introductions about the structure of semiconductor components and the method of their production, which have been discussed so far, can serve to understand the fundamental mechanisms in them. In order to get a true idea of the determinants of the quantitative performance of components and electronic circuits, as well as to get an idea of the parasitic effects accompanying the components, one must enter the domain of methods for manufacturing semiconductor components. Based on the knowledge about how they were made and what materials were used, we can draw conclusions about the price and about the limitations related to their application. The development of technology for the production of semiconductor components, starting in 1948, when the first bipolar transistor was made, recorded fantastic results. New, more advanced procedures are registered almost every day. New components are created or existing ones are improved. Therefore, the development of methods for the production of semiconductor components will not be discussed in detail in further presentations, nor will we attempt to describe all the important procedures for their production. Attention will be paid to the most important methods and procedures. Semiconductor components can be made on a silicon (or other) plate so that they are individual and intended for independent inclusion in the operation of the device, and then we call them discrete components. All previous considerations pointed to this way of application of the components. There is, however, the possibility to simultaneously manufacture and connect several transistors and passive components in the same chip so that they perform a complex electronic function. Then we say that the components are integrated on one wafer and that the resulting circuit is integrated. The basic procedures for making discrete components and integrated circuits are essentially the same. To make a discrete diode, for example, you need to realize a p–n junction on silicon, mount the silicon on the wafer, connect the P- and Nregions with leads (wires) and place it in a casing. For the production of an integrated circuit, in addition to the production of one p–n junction, a number of operations are © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 V. Litovski, Lecture Notes in Analog Electronics, Lecture Notes in Electrical Engineering 1002, https://doi.org/10.1007/978-981-19-9868-3_10

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performed in order to realize all components individually. Other activities (assembly, etc.) remain as common. Therefore, in further presentations, there will be no mention of special procedures for making discrete components. By making integrated circuits instead of mounting and connecting discrete components on a printed circuit board, a number of advantages are obtained. The first and most important advantage is the drastic reduction of the surface area (and volume) of the electronic circuit. The number of components per unit volume is usually called packing density. Often, however, due to the surface mounting of the components, whether on a printed, ceramic, or silicon plate, the packing density is understood as the number of components per unit area. Today, packing densities of the order of 171.3 million transistors per square millimeter have been reached. Of course, this is not a typical packing density. A density of 106 /mm2 can be considered typical. Depending on the number of integrated components (making up a single electronic function), we distinguish different degrees (scales) of integration. Low-level integration (SSI = Small Scale Integration, 2 to 100 transistors) represents the case when up to a hundred components are integrated. If up to five hundred components are integrated, we say that it is a medium degree of integration (MSI = Medium SI, 100–500 transistors). For circuits where up to twenty thousand components are integrated, we say that it is a high degree of integration (LSI = Large SI, 500 to 20,000 transistors). Integrated circuits with up to a million components have a very high degree of integration (VLSI = Very LSI, 20,000 to 106 transistors) and, finally, if the number of components is larger, it is said to be an ultra-high degree of integration (ULSI, more than 106 transistors). To illustrate the pace of development of integrated circuit technology in the last decades Fig. 1.10.1.1 depicts the number of transistors per chip as a function of time for the last fifty years. Note the logarithmic scale at the y-axis. Such a rise in the number of transistors per chip was enabled by the reduction of the dimensions of the transistors i.e., their features. Figure 1.10.1.2 depicts the fall of the size of the gate length in time for the last 60 years. Here again, the y-axis is in Fig. 1.10.1.1 Number of transistors per integrated circuit (product) in years

1.10.1 Introduction

279

Fig. 1.10.1.2 Minimum gate length in μm as a function of time

logarithmic scale. That means an exponential fall in the size of the gate. It is usual to characterize these developments in the semiconductor technology by the so-called Moor’s law which says that the numbers are doubling (or halving) in a given fixed period of time (say three years). Among the advantages of integrated circuits, in addition to those mentioned, we should mention significantly increased reliability of the electronic circuit; significantly lower price per transistor when working with high-volume production; reduced parasitic effects of internal connections; reduced dissipation, etc. Although it is not the subject of discussion here, in order for the reader to get an idea of the advantages of integrated circuits over classical ones, we will briefly clarify the concept of reliability. The circuit for which the most likely time interval between two failures is very long, is considered reliable. The interval between two failures will be shortened if any component or connection fails. Roughly speaking, an integrated circuit represents one, albeit more complex, component for which the probability of failure is higher than that of one discrete component, but significantly lower than that of n discrete components that it replaces. Therefore, the lifetime of devices containing integrated circuits is extended. When talking about the price, one should first of all consider the savings on the silicon surface, which is better used in integrated circuits. In addition, however, one should keep in mind the countless complex operations that turn a small silicon wafer into a component that can be mounted on a PCB. For discrete components, this is done n times, and for integrated components, once. Finally, the assembly of n components must be significantly more expensive and less reliable than the assembly of one integrated circuit if the number of soldering points is considered. There are mainly two ways of making integrated circuits. When an integrated circuit is formed on the surface of a semiconductor crystal, partially penetrating in it, we say that it is a monolithic integrated circuit. Namely, the crystal (most often silicon) has a very regular structure and hence the name (mono = single, lit = stone). The second procedure includes the application of layers on an insulating surface with the assembly (gluing) of the already formed components and the connection of all

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that. Therefore, the second method uses mixed components and consequently this type of integrated circuit is called hybrid. In hybrid integrated circuits, a monolithic integrated circuit or a discrete transistor is most often used as an active part. There are so-called thin-film and thick-film hybrid integrated circuits. The presentations in this section will be divided into the following parts. First, the procedures for making monolithic integrated circuits will be described, then bipolar and MOS monolithic circuits will be described. A separate section in this Chapter will be devoted to the description and manufacturing procedures of hybrid integrated circuits. The reason for this is the specific materials and technologies that are in use.

1.10.2 Processes in the IC Production Technology 1.10.2.1 Obtaining Silicon Crystals In earlier presentations on the properties of semiconductors, some properties of silicon crystals were mentioned which can be of great importance for the behavior of individual components but also for the integrated circuits. Among them, we mention defects in the crystal lattice (atoms of the crystal are not in their places—which can mean that they are missing or have been displaced) and unwanted impurities that generate energy levels within the energy gap. Therefore, silicon with a concentration of defects and unwanted impurities (all together) can be considered pure if its concentration is much smaller than ni . For example, for silicon, an acceptable concentration of unwanted impurities would be 107 cm−3 . This means that one impurity atom per 1015 silicon atoms is allowed. From the point of view of the reproducibility of the characteristics of the components, an important feature of the crystal is the uniformity of the concentration of carriers with which the crystal is doped. Let us also mention the anisotropic mechanical properties of crystals, which indicates the obligation to strictly consider the position of the crystallographic axes in relation to the axis of the crystal body. The geometric figures that usually appear in integrated circuits are rectangular and placed so that their edges coincide with the crystallographic axes. In the following text, the methods for obtaining silicon that meet such strict requirements will be briefly mentioned. Silicon is the second most abundant element and makes up 25% of the earth’s crust. Its production usually starts from a mixture of quartz sand (SiO2 ) and carbon. This mixture is placed in an electric arc furnace where reduction takes place. Namely, if there is an excess of SiO2 , the following reaction occurs: SiO2 + 3C = SiC + CO 2SiC + SiO2 = 3Si + 2CO.

1.10.2 Processes in the IC Production Technology

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Of course, the resulting silicon is far from pure because neither the quartz sand nor the carbon was particularly pure. The first stage of cleaning is based on the property that impurities are grouped mostly on the surfaces of Si grains. They are removed using an acid that does not react with Si, but dissolves impurities. After this cleaning process, about 0.2% of foreign matter remains in the silicon. The next stage is chlorination Si + 2Cl2 = SiCl4 whereby silicon tetrachloride is separated by a distillation process. During this process, some of the impurities are eliminated, and especially boron is effectively eliminated, which would be difficult to separate in later processes. After distillation, SiCl4 is reduced with Zinc: SiCl4 + 2Zn = Si + ZnCl2 , or hydrogen: SiCl4 + 2H2 = Si + 4HCl. In a short diversion, we are drawing here the attention of the reader that semiconductor industry is in fact a chemical one. The purity achieved by the chemical process is still insufficient for the production of electronic components. The final purity is achieved by the process of zone refining. The process consists of the following. The silicon rod is placed vertically. A wire coil is placed around it through which an alternating current of radio frequency is passed. Due to the effect of the electromagnetic field of the coil, the part of the silicon rod that is covered by the coil heats up and melts. At the same time, the rod rotates slowly, and the coil moves from the bottom to the top (and vice versa). This procedure is illustrated in Fig. 1.10.2.1a. The trick is that impurities whose melting point is lower than that of silicon remain in the molten part and are transported to the ends of the rod. This procedure is repeated several times. The process of zonal refining ends by cutting off the ends of the rod, leaving the middle part with extremely pure silicon. The pure silicon obtained in this way is still not usable for the production of semiconductor components. First, components are usually manufactured by starting from a silicon wafer with a given type of conductivity and a given specific resistance. In addition, as has been said several times, it is necessary to have monocrystalline silicon. For this purpose, the obtained pure silicon is melted, and the desired impurities are added to it. A crystal grows from this melt. The most commonly used method of crystal growth is the Czochlarski method. In this process, the seed (pure crystal without defects), crystallographically oriented in a suitable way, is first brought into contact with the surface of molten silicon which is doped with the appropriate dopant. Then the germ (crystal) is gradually pulled out at a constant speed with slow rotation around its own axis, while the temperature of the contact surface of the crystal and the melt is strictly controlled. In this way,

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Fig. 1.10.2.1 a Zone refining, b the Czochlarski process: a symbolic representation of the apparatus and the process, and c an extracted single crystal (ingot) of silicon together with one cut plate (wafer)

crystals whose diameters range from 5 to 30 cm in steps of 2.54 cm (corresponding to diameters from 2 to 12 inches) are extracted. A simplified representation of this process is given in Fig. 1.10.2.1b. The heating is done by a coil that covers the entire container and through which an alternating current of radio frequency (RF) flows. The crystal obtained in this way is further prepared for the production of electronic components. Figure 1.10.2.1c shows a photograph of a silicon rod (ingot) obtained by this method together with a silicon plate that is created by cutting (slicing) this crystal.

1.10.2 Processes in the IC Production Technology

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Greater uniformity of impurity concentration in the crystal, in recent times, is obtained by the process of doping by neutron transmutation. This complex process is based on the partial transmutation of silicon into phosphorus, whereby silicon is exposed to hot neutrons and transmuted into phosphorus, releasing beta particles. Now one starts cutting the crystal into tiles (wafers), which in fact form the base for making the component. In order to ensure adequate mechanical strength, the thickness of the tile increases with the increase of its diameter and ranges from 0.2 to 0.8 mm. Cutting must be done along one crystallographic plane so that the surface has uniform properties. Cutting is done with a diamond saw (a circular plate on the edge of which diamond grains are applied, which rotates and gradually penetrates the crystal) so that the final surface of the plate is quite rough. Bearing in mind that electronic components are made planarly (which means in one plane) on the surface of the wafer, it is first necessary to level (polish) the surface of the tile to the quality of the finest mirror. Components that are made from one side of the wafer are planar (or horizontal), and if the function of the component includes the entire wafer and there are contacts on both sides, we are talking about a vertical component. Several components (several discrete or several integrated) are simultaneously realized on a single wafer. These form islands separated by areas of unused silicon. These areas will be used to cut the wafer into individual components and thus chips are created. Cutting is usually done by a diamond spike, which in fact only makes deep trenches on the surface so that the chips break off easily (and automatically by a vacuum powered nozzle).

1.10.2.2 Formation of p–n Junctions There are several ways to form a p–n junction on a substrate of a given conductivity type. The most commonly used process is diffusion. For this process, impurity atoms should be applied to the surface of the crystal and then the substrate should be heated. Due to the rough vibrations of the atoms in the crystal lattice, the atoms of the basic crystal release places to be occupied by the impurity atoms, gradually diffusing into the depth of the pellet. The process is analogous to the dissolution of materials (impurities) in silicon. If the impurity atoms are of approximately equal dimensions and valence, they easily replace the atoms of the crystal lattice. This process is called substitutional diffusion. Impurity atoms move randomly in all directions, but if we have a higher concentration of impurity in one area, then fewer atoms will diffuse towards it, and more towards the area with a lower concentration. The speed of penetration will depend on the creation of vacancies in the lattice. It is possible for an impurity atom to occupy a place in the crystal without replacing an atom of the basic material. In fact, in the lattice, there are locations between atoms that are suitable for occupation and are called interstitial sites. At elevated temperatures, impurity atoms can jump from one interstitial site to another and thus diffuse. This type of diffusion is interstitial diffusion.

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One or the other diffusion is possible in the crystal. In silicon, for example, iron, gold, copper, and lithium diffuse interstitially. However, at the end of diffusion, gold atoms end up at substitution sites, although due to their size, they create discontinuities in the lattice, and thus the effects are caused by the defect (diode with gold dot). The most important dopants diffuse substitutionally. The diffusion process is controlled by a law that is equivalent to the part of the continuity equation that relates to diffusion (diffusion current): ∂2 N ∂N =D 2, ∂t ∂x

(1.10.2.1)

where N is the concentration of impurities at the depth x in the wafer at the moment t from the start of diffusion. This expression is called Fick’s second law and states that the rate of change of concentration is proportional to the second derivative of concentration by distance. The constant D is called the diffusion coefficient. It expresses the temperature dependence of the diffusion process and is usually given as: ln D = a/T + b,

(1.10.2.2)

where a and b are constants that depend on the type of crystal and on the dopant. For example, for boron and phosphorus in silicon we have: a ≈ −2.88· 10–8 and b ≈ 2.178· 10–11 , where D is obtained in cm2 /s, and temperature is given in K. Due to the high-temperature dependence of the diffusion coefficient, this process is carried out under strictly controlled temperature (for the mentioned example, about 1400 K). Depending on the amount of dopant available on the surface of the crystal, the solution (1.10.2.1) has the form of exponential (unlimited amount of dopant) and Gaussian (limited amount of dopant) function. At the same time, each of these curves is limited by the diffusion time but also by the maximum solubility of the dopant. The latter means that an infinite number of atoms cannot be introduced into the crystal for a given temperature. By choosing the amount of deposited material before diffusion (dopant application is called predeposition), and by choosing the temperature and time of diffusion, the impurity profile in the semiconductor is controlled. Impurity profile refers to the dependence of concentration on distance after diffusion. In Fig. 1.10.2.2, the impurity profiles created by diffusion are given depending on the method of performing diffusion and in dependence on the duration of diffusion, all for a single temperature. N x is the nominal concentration in the substrate. It can be seen that the curve (a) produces a higher concentration with a lower depth and vice versa, the Gaussian curve (b) can provide a higher depth with a lower concentration. In any case, the maximum concentration of impurities is on the surface. Diffusion of carriers causes changes in the properties of the surface as compared to the substrate. The most suitable indicator of the electrical properties of the surface is its resistance. It is usually expressed through the layer resistance, which represents the quotient of the mean value of the specific resistance of the surface (When viewed from the surface itself towards the plate, the concentration changes and so does the

1.10.2 Processes in the IC Production Technology

285

Fig. 1.10.2.2 Diffusion of impurities. Dependence of the concentration on the depth of diffusion for a unlimited source of predeposited dopants and b limited source of predeposited dopants

specific resistance.) and the thickness of the layer we are observing. If we denote the layer resistance as Rs , the thickness of the layer as x, the length of the diffused area as L, and the width as W, for the resistance we have R=

L ρ L = Rs . xW W

(1.10.2.3a)

Layer resistance is given in ohms per square (Ω/⎕). Namely, regardless of its dimensions, diffusion whose layer resistance is Rs , if it is square shaped, will always have the same resistance R = Rs because L = W. Therefore, when determining the resistance of the diffused layer, first, depending on the place of the connection (contact), one defines what will be considered the length and what will be the width, and then count the squares whose side is W (width) and multiply that number by Rs . The value of the layer resistance is measured by the four-point probe depicted in Fig. 1.10.2.3. As shown in the picture, current I flows through spikes 1 and 4 and through the plate while voltage V is measured between spikes 2 and 3. If the depth of diffusion is significantly smaller than the distance between the spikes, the following relation is derived: Rs = 4.5

V (Ω/m). I

(1.10.2.3b)

Although we talked about p–n junctions when we first mentioned diffusion, we have not considered them until now. But here they are. Let the silicon wafer be doped with a concentration of one type (N x ), and let N be the concentration of the opposite type. At the intersection of the curves N(x,t) and N x (Fig. 1.10.2.2) there is a change in the type of concentration of the majority carriers, which means that it is the place of a p–n junction. If the curve N(x,t) is steep, we have an abrupt p–n junction, while a gentle curve gives an approximately linear change in the effective concentration. Namely, the presence of impurities of one type (N x ) in the area of the opposite conductivity type N leads to the neutralization of part of the impurities so that the effective concentration is considered to be the difference N–N x . The same applies to the opposite side of the junction.

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Fig. 1.10.2.3 Measuring the layer resistance by a four-point probe

Finally, when considering diffusion, we mention that it is an isotropic process, which means that it spreads in all directions when looking at the wafer. If the impurities spread to the depth of the semiconductor, we have vertical diffusion, and if they spread laterally (horizontally), we speak of lateral diffusion. Figure 1.10.2.4 shows a wafer with predeposited material that diffuses isotopically. The depth of diffusion is the same everywhere. Although this property of diffusion is often effectively used, lateral diffusion is usually undesirable because it increases the overall dimensions of the p–n junction, thereby reducing the packing density of monolithic circuits. Diffusion provides control of the concentration of impurity atoms up to a depth of 25 μm. When precise control of the surface concentration in layers thinner than 1 μm is desired, ion implantation of impurities is used. This process involves ionization of impurity atoms and their subsequent acceleration in an electric field. Then, they hit the base material (silicon) and penetrate to a depth of a few fractions of a micron. Before we take a closer look at the implantation process, let us see some of its advantages and disadvantages compared to diffusion. First, the impurity profile can be precisely controlled. The reason for this is the fact that it mostly depends on the implantation system and not on the properties of the substrate. The number of implanted atoms does not depend on the maximum solubility so that the properties of thin semiconductor layers can be precisely controlled. Fig. 1.10.2.4 Vertical and lateral diffusion

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Then, the implanted atoms are directed towards the depth of the semiconductor, which means that there is no lateral movement of impurities, which enables reduction of the dimensions of the components. Finally, implantation is a low-temperature process, which means that the danger of disrupting the properties of existing p–n junctions that were previously performed on the wafer by the diffusion method is reduced. Among the disadvantages of implantation, we should highlight the fact that only shallow impurity profiles can be obtained. Then, when penetrating through the crystal, impurity atoms (ions) on their way destroy the crystal. In order to regenerate the crystal lattice and bring impurity atoms to the appropriate places in it, an additional temperature process is required (lower temperatures than during diffusion). This process is usually called tempering. The general composition of the ion implantation system is shown in Fig. 1.10.2.5. The system consists of an ion source, a magnetic mass filter that separates unwanted ions, a gun for accelerating ions, a beam focusing lens, and a deflecting plate. The target is usually a metal disc containing 50–60 Si wafers arranged in a circle. To clarify the function, we assume that Boron should be implanted. For this purpose, BF3 or BCl3 is used. Ions are usually formed by the decomposition of these compounds during bombardment with electrons produced by an arc discharge or from a cold cathode. In this way, several types of ions are formed which are separated by an ion separator using a magnetic field. Acceleration of the filtered ions is done using an accelerating potential of 10–300 kV. At the target, the diameter of the beam is about 1 cm2 . The beam current is from 10 μA to 2 mA. The ion dose refers to the number of implanted ions per unit area and ranges between 1011 and 1016 atoms/cm2 . Collisions between atoms of impurities and atoms of the basic material are by nature a random phenomenon. Therefore, Gaussians can be taken as the final distribution of implanted ions. This distribution is usually characterized by a mean value called the range and a standard deviation or dispersion. Unlike diffusion, where the amount of concentration and distribution are tied to one another, in the case of implantation we can more easily control the amount of concentration and the profile of impurities. The dose defines the value of the concentration, and the voltage with which the ions are accelerated, the profile of the impurity. Fig. 1.10.2.5 General view of ion implantation system

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Fig. 1.10.2.6 Distribution of the implanted boron into silicon

Figure 1.10.2.6 shows the impurity profile of boron ions in silicon at different accelerating fields and at a constant dose. It can be seen that with the increase of the accelerating field, the range (depth) and scattering (width of the layer) also increase. Increasing the dose would only increase the ordinate axis in this figure. It is characteristic that the scattering depends on the ratio of the mass of ions and the mass of silicon so that with heavier ions the scattering is less. One of the most important techniques in the production of electronic components (and p–n junctions) is the production of epitaxial films. The introduction of the growth process of a uniformly doped epitaxial film (layer) over a uniformly doped silicon substrate leads to a tenfold reduction in scrap during the manufacture of semiconductor components compared to the manufacture of transistors with triple diffusion. The name “epitaxial” should be read as “made from the top”. During epitaxial growth from the gas phase, gas containing silicon compounds passes over the wafer. The atmosphere is kept at an elevated temperature and the reactions that occur lead to the deposition of silicon atoms. They jump into the corresponding places on the surface of the crystal lattice so that as a result we have a completely regular continuation of the crystal lattice. By adding appropriate doping gases, impurities such as B, P or As can be distributed in the epi-layer. The concentration of these impurities is uniform, which means that it does not depend on the distance (depth). The process is usually carried out in an epitaxial reactor. The thickness of the layers ranges from a few microns to tens of microns. Two basic processes are used for silicon deposition: reduction of SiCl4 (silicon tetrachloride) and pyrolytic decomposition of SiH4 (silane). Here we will briefly describe only the first one. In this process, hydrogen is added to SiCl4 and the temperature in the reactor is kept at around 1000 °C. The following reaction takes place 2SiCl4 + 2H2 → Si + SiCl4 + 4HCl i.e., silicon is deposited on the surface, hydrochloric acid evaporates, and SiCl4 participates in the reaction again. It is characteristic that if the molar ratio of SiCl4

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and H2 is greater than 0.28, instead of deposition, silicon is eroded (etched) from the surface. To make the epi-layer on a P- or N-type semiconductor, diborane (B2 H6 ), phosphine (PH3 ), or arsine (AsH3 ) are added to the atmosphere. In most cases, when making N-type epitaxial layers, As is used as an impurity. The diffusion coefficient of arsenic is small, so that during subsequent temperature processes of wafer processing, there is no change in the impurity profile in the epi-layer. Based on the previous presentations on epitaxial growth, it can be concluded that it is possible to realize an absolutely sudden change in concentration at the border of the substrate and the epi-layer. Without going into details, we will mention here that the concentration change at the boundary of the epi-layers is not abrupt but obeys the exponential law. When the type of impurity changes at the junction, a p–n junction is formed by epitaxial growth. Due to the continuity of the change in concentration, the junction boundary moves towards the epitaxial region. The position of this limit would be final if additional high-temperature processes were not performed. Since this is not the case, she moves. A typical example is the diffusion process. Namely, during the production of semiconductor components, additional p–n junctions are often formed in the epitaxial layer by diffusion. On that occasion, diffusion occurs at the boundary of the epi-layer and the substrate and consequently the boundary of the p–n junction moves towards the area with a lower concentration of impurities. The epitaxial growth technique is also used in the production of p–n junctions with very sharp boundaries as well as heterojunctions on complex semiconductor materials such as GaAs. Heterojunction represents the connection of two different semi-conducting materials so that there is no deformation of the crystal lattice at the boundary. In these situations, chemical epitaxy is not used, but molecular beam epitaxy (MBE = molecular beam epitaxy). This process is low-temperature and the junction boundary is extremely precisely determined. Molecule beam epitaxy is performed in a very complex device, a simplified representation of which is given in Fig. 1.10.2.7. This device can be used to grow GaAs and Alx Ga(1-x) As. The basic parts of this system are the heated molecule sources, the source caps, and the heated substrate on which the epitaxial layer will grow. Epitaxial layers of a pure semiconductor can be formed by means of a source of Al, Ga, and As molecules. The other two sources contain silicon and beryllium, which are most often used as impurities for GaAs and Alx Ga(1-x) As. Silicon replaces Ga or Al atoms from group III so that one more electron is produced, i.e., silicon acts as a donor. Beryllium also replaces Ga or Al atoms, but has one less electron, which means that it acts as an acceptor. The rate of evaporation of the basic material as well as the flux of atoms (or molecules) depends on the temperature in the sources so that it is very strictly controlled. It is chosen so that the layer grows at a speed of 10–6 m/h, which corresponds to one layer of GaAs molecules per second. Since each source of molecules is equipped with a cover that can be closed in a time that is significantly shorter than a second, it is possible to control the composite semiconductor (x in Alx Ga(1-x) As) or impurities in the layer whose thickness is comparable to the scale of an atom. Since

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Fig. 1.10.2.7 Simplified representation of the molecular beam epitaxy (caps of Ga and As are open)

the entire component is formed in this way without high-temperature processes, the resulting p–n junctions have very sharp boundaries. It should not be emphasized that the equipment for molecular beam epitaxy must be very complicated and very expensive, so this technique is used for the production of very specific components.

1.10.2.3 Semiconductor Surface Protection The surface of the semiconductor plays an important role in the operation of the electronic component and it must be protected from atmospheric influences (diffusion of impurities, application of grease and moisture, etc.). The process of surface protection is called passivation and is usually done by forming a thin layer of SiO2 or Si3 N4 . Silicon dioxide is used more often as a passivating agent due to the simplicity of its formation, but also due to the possibility of masking semiconductors, which will be discussed later. SiO2 , when formed at temperatures of about 1000 °C and lower, is an amorphous glass. It is characteristic that the structural formula is given by SiO4 4− , which means that this molecule is tetravalent electronegative. The silicon atom, which is tetravalent, is located in the middle of a regular tetrahedron whose corners contain oxygen atoms. Each Si atom shares an electron with the four neighboring oxygen atoms. Each oxygen atom has one unpaired electron left. The tetrahedrons are connected so that two silicon atoms share one oxygen atom. If there are no defects in the arrangement of Si atoms and in the absence of impurities, all oxygen atoms have filled bonds and SiO2 is a very good insulator. The diffusion of impurities in SiO2 and the existence of defects deteriorate the electrical properties of SiO2 (resistance and critical field). It is characteristic that, due to the low valence, oxygen atoms can migrate through the oxide so that in their place there remains an excess of positive charge that is characteristic of the oxide and particularly important for the operation of MOS transistors.

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The oxide can be applied to the surface in the form of a thin layer, which will be described when considering hybrid integrated circuits. Here we will consider another procedure for forming the oxide layer, i.e., oxide growth on a silicon substrate at elevated temperature. In this case, the silicon on the surface oxidizes so that an oxide is formed. At the same time, oxygen from the reactor’s atmosphere diffuses through the oxide that has already been formed and reaches the silicon atoms. Therefore, part of the silicon is consumed so that about 44% of the oxide is actually spent silicon. In order to protect the oxide from the penetration of heavy atoms (Na) and other diffusants from the atmosphere, Si3 N4 (silicon nitride) is often used in the production of semiconductor compounds. It is deposited from a mixture of SiCl4 and NH3 at about 850 °C.

1.10.2.4 Lithography Literally speaking, the term lithography should be understood as writing (painting) on the crystal surface. The purpose of writing the pattern will be easily seen if one looks at Fig. 1.10.2.4 where it is shown that on the surface of the wafer, an area over which the predeposition and later diffusion will be carried out should be precisely determined. Therefore, the components must be “drawn” on the surface of the wafer. The procedure usually proceeds as follows. First, the surface is covered with oxide, which will serve as a masking material during diffusion. In order for predeposition or diffusion to take place, holes should be made in the SiO2 on the silicon surface. For this purpose, the oxide is covered with a photosensitive layer—resist. Now, one illuminates the resist, most often with ultraviolet light, through a glass plate on which an opaque layer has been partially applied. This glass plate is called a mask. In places where the resist is illuminated, its chemical properties change so that the illuminated (in some cases unilluminated) layer is easily removed, leaving patterns on the surface of the resist where SiO2 is visible. By etching SiO2 with an agent that does not corrode the resist or Si, we get openings in SiO2 on the surface of Si through which predeposition can be carried out after the rest of the resist is removed from the surface SiO2 . A very similar procedure is used for the formation of the Al–Si contacts, with the fact that Al application (corresponding to predeposition) will be discussed later. The process described above in brief is visualized in Fig. 1.10.2.8. Now we will consider individual actions in more detail. First of all, it should be noted that lithography is usually done with ultraviolet light, but if one wants more precise (smaller) shapes on the surface, then X-rays, or electron beam lithography (EBL = electron beam lithography) are used. The need to use as hard rays as possible arises due to unwanted phenomena that occur at the border (contact) of the mask and the resist, and which can mostly be expressed through the refraction and diffraction of the incident light beam, which makes the edges of the pattern imprecise.

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Fig. 1.10.2.8 Photolithographic procedure. a Silicon wafer, b oxide deposited, c resist deposited, d a mask set above the photoresist and ultraviolet light activated, e the not-illuminated resist removed (washed), f etched oxide, and g the rest of the photoresist removed

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When an electron beam is used to expose the resist, it is possible to use it directly on the plate (without a mask), which gives an extremely high-quality edge between the illuminated and non-illuminated part, although the process is much slower. Depending on the type of exposure (light, X-rays, electron beam) one needs corresponding resists: photoresist, X-ray resist, and electron beam resist. It is important to note that this emulsion (photoresist) behaves like photographic film, but the resolution is much better. Strips with a minimum width of 2 μm can be formed with photoresist. Narrower strips do not have reliable dimensions. Regardless of the wavelength of the exposure beam, resists can be positive or negative. The negative photoresist polymerizes when illuminated so that those areas remain insoluble. Figure 1.10.2.8 shows the use of such a resist. In the case of positive photoresists, the energy of the rays destroys the molecules so that the illuminated part is easily soluble. One important component of the lithographic system are devices for setting (positioning) the masks—aligners. The essence of the problem solved by this device will be clear if it is considered that several consecutive photolithographic cycles are performed at the same spot on the crystal surface in order to form several p–n junctions and made contacts. Since we are working with very small dimensions, the next mask must be very precisely adjusted over the area (diffusion, for example) that was formed earlier. The production of some integrated circuits requires a series of (in some special cases up to) 30 masks, so the adjustment of the masks is extremely important. In these devices, the exposure of the resist is also performed. Today, aligners are used in which the mask and the plate come into intimate contact (as in Fig. 1.10.2.8d, where on the plate and on each mask, patterns are made in advance that serve for adjustment) and aligners without contact where the mask and plate are separated (tenths of a micron) so that the mask is protected from wear. One should bear in mind the high-volume production, where one mask will serve to expose a large number of wafers. When the illuminated (negative) photoresist has been removed, it is necessary to start etching the oxide. There are two most important etching processes in use: wet and dry etching. In wet oxide etching, the wafer is immersed in a hydrofluoric acid solution that etches (dissolves) SiO2 where it is available but does not dissolve Si or the resist. The result of etching is shown in Fig. 1.10.2.8f. This wafer is first dipped in a solution that removes the photo resist, and then washed to remove dirt. A significant shortcoming of this process, which limits its application to the production of components of relatively large dimensions, is isotropy. Namely, the etching spreads in all directions towards the wafer and goes laterally under the resist. In this way, the opening through which the diffusion will be carried out later is enlarged, and the precision is also reduced. This disadvantage of wet etching is significantly alleviated in the (more complex) dry etching process. One variant of dry etching is plasma etching. In this case, the wafer is placed in a low pressure system that is heated by an RF coil so that gas ionization occurs in the chamber—plasma is created. CF4 is usually found in the gas, which is ionized into CF3 and F. These radicals react with SiO2 so that SiF4 and SiO2 are formed, which leave the system in the form of a gas, taking atoms of Si and O, being parts of the oxide, with them.

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Now let us consider the mask itself. As already said, it represents a glass plate on which a very thin layer of opaque material with high wear resistance (chromium, for example) is applied. The edge of the layer must be very sharp to avoid diffraction. Like the integrated circuits themselves, the masks can be made using a light beam or an electron beam. In the first case, mask making includes several stages. First of all, the so-called reticle is made in the computer-controlled system. It is also a glass plate on which there is a pattern that refers to one lithographic cycle (one chip), but the dimensions are 5–10 times larger than the final one. Usually, this plate is used to make a master-mask. On it, the pattern on the reticle is reduced to the right size and repeated multiple times in order to produce more integrated circuits (chips) on the same wafer. This process is usually called step and repeat. The master-mask is not used in the aligner, but its copy. It is possible to use the reticle directly in an advanced aligner that performs reduction, and step and repeat using its optical system. Another process for making masks uses an electron beam. In this case, the mastermask is produced directly. The glass plate is first covered with metal (chromium), and then with a resist that is sensitive to electrons. The electron beam moves along the surface of the resist and is active where it is needed while turned off where it is not. After the exposure, the mask is immersed in a developer and rinsed, which removes the unwanted (polymerized) part of the resist, and then etched, which removes the unwanted metal layer. Finally, the rest of the resist is removed and we get a mastermask.

1.10.3 Bipolar Integrated Circuits The production of a BJT as a discrete component can be done by two diffusions into a plate of a given type of conductivity that will serve as a collector. For example, in an N-type wafer (Fig. 1.10.3.1a), boron diffusion is first performed, which forms the collector junction (Fig. 1.10.3.1b), and then phosphorus diffusion (Fig. 1.10.3.1c) in order to form an emitter junction. When some activities related to second-order phenomena are omitted, this picture would include the process of making a discrete transistor. The production of an integrated circuit is in many ways similar to this series of activities, but there are a number of problems that must be solved during its formation. The most important problem is the mutual isolation of the components on the chip. It consists of the following. If in the same wafer as in Fig. 1.10.3.1, one wants to install another transistor, they will have a common collector area and if the voltage drop on the collector body is abstracted, the transistor collectors would be short-circuited. This problem is present in the production of all components in integrated circuits. There are several ways to overcome this problem. The isolation of components by additional diffusion is most often used, and that process will be described here first. It starts from a P-type substrate on which the epitaxial layer will later grow. Due to the relatively small specific conductivity of the epitaxial layer before it is applied

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Fig. 1.10.3.1 Stages in making a discrete transistor. a N-type silicon, b Boron diffusion, c Phosphorus diffusion, and d formed holes for applying metal contacts

to the surface of the substrate, an area of high conductivity (N+ ) called the buried layer is formed under the place where the transistor will be created. The first mask will serve to define the buried layer. The substrate with a buried layer coated with oxide is shown in Fig. 1.10.3.1a. The thickness of the buried layer is about 5 μm, and the layer resistance is between 10 and 30 Ω/⎕. The next step is the application of an epitaxial layer that will serve as a collector. The thickness of this layer can reach up to 25 μm, with a specific resistance of the order of 0.1 to 0.5 Ωcm. Arsenic is most frequently used as an impurity because it has a low diffusion coefficient, so that during the following diffusions, there is no movement of the boundaries of the junctions. Since the doping is uniform, we can talk about specific resistance here. The structure obtained after epitaxy is shown in Fig. 1.10.3.2b. Now it can be seen that the buried layer is connected parallel to the collector area so that it reduces the total resistance of the collector. The wafer is covered with oxide.

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Fig. 1.10.3.2 Phases in the fabrication of an integrated BJT. a formation of the buried layer, b epitaxial layer of the collector, c diffusion of the isolation, and d the transistor without contacts

The critical step that separates integrated from discrete circuits is insulation diffusion. Namely, diffusion takes place around the perimeter of the component (transistor) so that a P-type semiconductor is formed. This diffusion is deep enough to reach the P-substrate and in this way islands of N-type semiconductors (collectors) are formed in the P-type wafer. We say island because the collector is surrounded from below and on all sides by a P-type semiconductor. If the substrate (here wafer) is brought to the lowest potential in the circuit, the substrate-to-collector junction will always be backward biased. When we install two transistors on the same wafer, there will be a P-region between their collectors so that two diodes connected in opposition are formed (they have a common anode formed by the P-region, and cathodes on each collector). Regardless of the potential difference between the N-regions, at least one of the diodes will always be backward biased so that the collectors are isolated. The only coupling between the transistor and the substrate is the junction capacitance, which limits

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this isolation technique to relatively low frequencies. Namely, if the signals are high-frequency, the impedance of the capacitor becomes low so that the insulation disappears. Diffusion of insulation is made by Boron. Figure 1.10.3.2c shows the situation corresponding to the crystal after diffusion of insulation. Another mask is used to realize this diffusion. The next step is to create a base diffusion. Boron is used again. During this high-temperature process, the re-diffusion of the insulation occurs so that it partly expands. The layer resistance of the base is about 200 Ω/⎕. A third mask is used for this diffusion. Emitter diffusion is the last step in making the transistor itself before applying the contacts. Phosphorus is used for this diffusion, which has a stabilizing effect on the oxide layer by reacting with heavy Na atoms. There are two specificities related to this process. First, the difference in the Fermi level of Al, which is used as a metallic bond on the surface between the components of the semiconductor, and the Fermi level of the P-semiconductor is insignificant so that such a connection forms an ohmic contact. In order to form an ohmic contact at the N-semiconductor-Al junction, however, it is necessary for the semiconductor to be degenerated (N+ ). Two consequences follow from this. First, on this occasion, diffusion should be done in the collector in order to form the ohmic contact of the collector, and then, the diffusion should occur from an unlimited source, which means that the impurity profile in the emitter will be an exponential function. Another specific feature of emitter manufacturing is related to the fact that the time and temperature of the diffusion of the emitter (since the concentration on the surface is fixed) determine the width of the base as well as the current gain coefficient of the transistor in an integrated circuit. The layer resistance of the emitter is very low. The cross-section of the part of the transistor with the emitter and base regions is shown in Fig. 1.10.3.3d. A fourth mask is used for this diffusion. In order to make the contacts of the corresponding areas and to connect those areas to other parts of the circuit, windows should be opened in the oxide (fifth mask). Then the wafer is covered with a thin layer of aluminum (metallization), which is subsequently removed from the entire surface except for the contacts and the connections (metal strips running on the surface connecting the devices) with a new photolithography process (mask number 6). The electrical and mechanical properties of the connection are improved by using more complex materials. The thickness of the aluminum metallization is about 1 μm. In this way, an integrated circuit is created that is additionally protected by a layer of glass. It is formed by a low-temperature process—pyrolytic decomposition, which occurs during the decomposition of various silicon compounds at an elevated temperature. An example of such a reaction is: SiH4 + 2O2 → SiO2 + 2H2 O Heat is needed as a catalytic effect.

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Fig. 1.10.3.3 NPN BJT in an integrated circuit using diffusion as isolation. a top view and b cross-section

In order for the integrated circuit to be connected to other circuits using metallization, extensions of the input and output terminals are made along the edge of the silicon wafer (chip). These extensions are called pads and have a relatively large surface area in order to fit the connecting wires (having in mind the tolerances of the wiring due to vibrations). After applying the pyrolytic glass, the pads are inaccessible, so one last photolithographic process is needed to remove the glass from them (mask number 7). Figure 1.10.3.3 shows the top view and the cross-section of a transistor produced by this series of activities. The dimensions of individual areas are also indicated. Distances between individual boundaries should be noted, which indicate limitations due to lateral diffusions. The transistor obtained in this way has approximately the following parameters: β≈150, I c0 ≈ 100 nA, f T = 1 GHz, V EB0 = 5 V, and V CE0 ≈ 40 V. In the mentioned process, when very shallow transistors need to be developed, implantation can also be included, for example for emitter or base predepositions. Before considering other components in bipolar integrated circuits, we should mention that every NPN transistor is accompanied by parasitic structures including the substrate. We have already mentioned the junction capacitance between the collector and the substrate. More interesting, however, is the vertical base–collectorsubstrate structure, which in fact represents a parasitic PNP BJT that is blocked in normal operating mode, since both the base-to-collector junction and the base-toemitter junctions are backward biased. When the NPN BJT is in current saturation, however, the collector-to-base junction is forward biased, so the base of the NPN BJT takes over the role of the emitter of the parasitic PNP BJT, which now works in

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Fig. 1.10.3.4 Substrate PNP BJT

the active region and draws current towards the substrate. This violates the isolation condition of the NPN BJT. Due to the width of the collector area, the current gain coefficient of the parasitic BJT is small, but it still limits the operation of the NPN BJT and the further reduction of dimensions. Although not often, in bipolar integrated circuits it happens that it is necessary to integrate a PNP BJT as well. Considering the P-substrate, this component is more difficult to manufacture and, when manufactured, has significantly lower performance than NPN BJT. If the collector of the PNP BJT is connected to a fixed negative potential (in such cases, the transistor works as a common collector amplifier—to be discussed in LNAE_Book 2), it is possible to use a vertical PNP structure as a transistor. This type of transistor is known as substrate BJT. The cross-section of this transistor is shown in Fig. 1.10.3.4. It can be seen that there is no buried layer and that the role of the base is taken over by the epitaxial N-layer. A P-diffusion serves as an emitter. Such a transistor has a β of order 25, a very high collector junction capacitance and a very high resistance of the body of the base, which significantly degrades its frequency characteristics. Another variant of making a PNP BJT is the so-called lateral transistor. The corresponding structure is shown in Fig. 1.10.3.5. Now the standard base diffusion of the NPN BJT is used to make both the emitter and the collector of the lateral PNP BJT. The collector completely surrounds the emitter in order to collect as many injected carriers in the base as possible. An N-type epi-layer serves as the base. The operation of the component depends on the holes that are injected from the emitter diffusion. They diffuse laterally and are accepted by the collector. This is the reason for the ring shape of the collector. The width of the base depends on the lateral distance between the borders of the emitter and the collector. This distance can be controlled within the limits allowed by lithography and lateral diffusion. In practice, the width of the base of the lateral transistor is large compared to the width of the base of the NPN BJT, which results in lower gain and a lower cut-off frequency. When making the lateral transistor, there are two vertical PNP structures that load the main one. The emitter–base-substrate structure is of greater importance because the emitter junction is forward biased so that the parasitic PNP BJT is also in the active area of operation mode. Due to this, a part of the minority carriers injected into the base is dragged towards the substrate and thus the current gain coefficient is additionally degraded.

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Fig. 1.10.3.5 Lateral transistor. Arrows indicate the paths of movement of the minority carriers in the base

The lateral transistor is characterized by a smaller concentration of the majority carriers in the emitter than in a normal NPN transistor, which means that the breakdown voltage at the emitter junction is significantly higher. Other performances of the lateral transistor are worse (5 < β < 100, f T ≈ 10 MHz). In addition to BJTs, diodes, resistors, and capacitors are found in bipolar integrated circuits. Coils (speaking generally) cannot be realized in a simple and effective way and, if they are necessary, terminals of the IC (pads) are created for them and they are tied later. It is possible to integrate specific complex integrated circuits, so-called impedance converters which, when loaded with capacitance, give an inductive input impedance. In this way, it is possible to simulate inductance. This issue will be discussed in LNAE_Book 4. The diode in a bipolar integrated circuit is not produced as a specific component but is obtained by connecting the transistor terminals in one of the possible combinations shown in Fig. 1.10.3.6. Which combination will be used depends on the desired special properties of the diode. If a diode with a high breakdown voltage and a high resistance in the forward direction is desired, a collector connection will be used as in Fig. 1.10.3.6c. This type of diode has a breakdown voltage higher than 25 V, and its inverse current is about 100 nA. The diode of Fig. 1.10.3.6e would be used as a high current and low dynamic resistance device. Similar considerations can be made for each type of coupling. In some of the cases, by short-circuiting two areas, the parasitic vertical transistor is removed, which can also be of great importance. Resistors in bipolar integrated circuits can be realized in several ways. When diffusion is used as a resistive layer, we distinguish emitter, base, and collector resistors. If implantation is used in the N-epitaxial layer, an implanted resistor is created, and finally, if a special epitaxial layer is used on the wafer surface, one gets an epitaxial resistor. The general feature of all techniques is that the tolerances of such resistors are bad (the accuracy with which a resistor can be made is ±20%, which means that if we make a resistor R of 1 kΩ we can expect 0.8 < R (kΩ) < 1.2. In addition to this, the resistance value of such resistors is very temperature dependent so that, together with

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Fig. 1.10.3.6 Diode in a bipolar integrated circuit. a and b the emitter junction used as a diode, c, d the collector junction used as a diode, and e parallel connection of the emitter and collector junction

the tolerance, in a wider temperature range, the resistor value range usually is 50% wider than its nominal value. With implanted resistors, the situation is somewhat better, so that the tolerances are around ±6% with better temperature properties. In a special case, however, when a voltage divider is used, bearing in mind that the resistances and their tolerances appear in both the numerator and the denominator of the transfer coefficient of such a branch, a relatively precise value of the output voltage can be obtained. Which area of the diffused BJT will be used as a resistor depends on the value of the resistance. The emitter area has a layer resistance between 2 and 5 Ω/⎕ and can be used for making small resistances. Such a situation is depicted in Fig. 1.10.3.7a. The collector has higher specific resistance and can be used as an area for making larger resistances (Fig. 1.10.3.7b). The base has the highest layer resistance (about 200 Ω/⎕) and it can be used for even higher resistances (Fig. 1.10.3.7c). It can be seen that even in this case, for the production of higher resistances, many squares are needed. For example, even with a minimum diffusion width of 10 μm (Fig. 1.10.3.3 can serve as a measure of lateral diffusion), 20 squares are needed to make a 4 kΩ resistor, which means that the resistor should be 200 μm = 0.2 mm long. Such resistors, if they must be realized, are made in the form of meanders as in Fig. 1.10.3.7d, whereby the square at the contact point and at the turning point is calculated as half the resistance of an ordinary square. In this picture, it should be noted that the base area is narrower than the emitter area, so that the resistor is actually a P-tunnel under the N-diffusion of the emitter. Even larger resistors can be made at the cost of introducing another photolithographic process and ion implantation. In this way, a layer resistance of up to 10 kΩ/⎕ is obtained. As already stated the value of this resistor can be controlled much more precisely. In order to form the contacts, two diffused P-type areas are needed, which are realized at the same time as the bases of the other transistors (before implantation). The cross-section of the implanted resistor is given in Fig. 1.10.3.7e. It should be noted that the integrated resistor, like the transistors, has its own parasitic vertical structure. By suitable bonding of the appropriate areas (connection to a fixed potential, short circuit, etc.) as in Fig. 1.10.3.7a (the left-hand side metallization

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Fig. 1.10.3.7 Resistors in a bipolar integrated circuit. a emitter resistor, b collector resistor, c base resistor, d base resistor of 20 m—top view, and e implanted resistor

short-circuiting the P and P+ regions connected to a negative potential) the influence of some parasitic effects may be reduced. With the base resistor, there remains a vertical PNP BJT, which couples the resistor to the substrate via its depletion capacitance. Whenever possible, the collector area of the base resistor is connected to the highest positive potential. When implantation (which as an additional process makes the integrated circuit more expensive) is excluded, serious problems remain in the manufacture of resistors,

1.10.3 Bipolar Integrated Circuits

303

Fig. 1.10.3.8 Collector junction as an integrated capacitor (left cross-section, right equivalent circuit)

especially of high resistances. Therefore, in order to reduce the area of the integrated circuit, whenever possible, transistors are used as dynamic resistors. This use of transistors will be discussed later in LNAE_Book 4. A capacitor in bipolar integrated circuits can be realized in two ways: as the space charge capacitance of a backward biased p–n junction and as a MOS capacitor. The latter will be discussed together with MOS integrated circuits. If the parasitic capacitance of the collector-to-substrate p–n junction is excluded, there are two space charge capacitances available. When handling higher voltages, the capacitance of the collector junction should be used. Such a capacitor together with the equivalent circuit indicating the parasitic elements is shown in Fig. 1.10.3.8. The basic properties of this capacitor are the capacitance is from ten to a hundred μF/m2 (or up to 0.1 fF/μm2 ), the series resistance is of the order of several tens of ohms (resistance of the body of the collector), the breakdown voltage is equal to the breakdown voltage of the transistor and amounts to several tens of volts and its temperature coefficient is about 0.1%/K. In addition, the value of the capacitance is a function of the applied voltage, which was already explained earlier. Finally, the biasing of the junction must be ensured so that the collector is always at a more positive potential than the base. Bearing all this in mind, we conclude that this capacitor cannot serve effectively, especially considering that it requires a large surface area. Let us note that in the circuit of Fig. 1.10.3.8 there is a capacitance of the collector junction of the vertical transistor, which is not significantly lower than the basic one and thus degrades its effect. If lower voltages (up to 9 V) are used, the emitter junction of the transistor can be used, which for backward biasing gives a capacitance of up to 1000 μF/m2 . With this capacitor, if the collector area is connected to a fixed positive potential, the parasitic effect is less pronounced. All other properties of the previous structures remained the same. There are a number of variations in the basic process for making bipolar integrated circuits. There are especially many of them when digital integrated circuits need to be developed. Considering the great variety and the newer solutions, variants of the basic process will not be considered here, except for one that indicates the way to increase the cut-off frequency. It is an isoplanar process. Here, instead of diffusion, oxide is used to isolate the components. In this way, the surface area of Si is reduced (consumption of material but also the capacitance of the transistor) by more than two times compared to the basic procedure. The reduction occurs because the diffusion

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Fig. 1.10.3.9 Isoplanar transistor

of the base can end at the oxide. The transistor made by the isoplanar process is shown in Fig. 1.10.3.9. It can be seen that the transistor is now surrounded by oxide. The collector diffusion, N+ , now makes direct contact with the buried layer. Since the diffusion of the base ends at the border of the oxide (on the right-hand side), the mask of the base also ends at the oxide so that the lateral diffusion is cut off—the transistor is shortened. Looking sideways, the emitter ends on oxide on both sides, too. This also means that less precision is required for the definition of the area of the base and the emitter so that the component can be even smaller. The absence of lateral p–n junctions reduces both the capacitance of the collector junction and the capacitance towards the substrate. In this way, components with f T = 5 GHz but with a breakdown voltage (V CE0 ) of about 5 V only were obtained. It remains to mention one problem that is not characteristic solely of bipolar integrated circuits. It is about crossing connections. When the connections cannot be made in a single plane, it is necessary to set the conductors to pass over each other without touching. This can be done with an N area that would transmit the signal under the aluminum connection at the crossing. An oxide layer would be applied between them. This situation is shown in Fig. 1.10.3.10. It is normal that the N+ diffusion (used for crossing) is located (isolated by P-diffusion) in the N-epitaxial layer where all the resistors are located. The N-area is attached to the highest positive potential, and the P-area usually does not float but is attached to the lowest (negative) potential. In this way, the effect of the parasitic NPN structure, which is inevitable, is disabled. To protect the oxide from breakdown, the metallization containing the crossover is never led directly to the pads.

Fig. 1.10.3.10 Crossing two connections. a cross section and b top view

1.10.3 Bipolar Integrated Circuits

305

When crossing two lines, it is on the integrated circuit designer to decide which one will be implemented by diffusion and which by metallization. It is usually chosen that the connection through which a smaller current flow goes through the N region in order to have a smaller voltage drop on the resistance of that connection. The voltage drop on the aluminum connection can be considered negligible. Finally, one should not forget that no additional procedures are needed for the implementation of crossing in this way. The connection is realized like any transistor. If, however, the number of crossings is very high, the total resistance of the connections can increase drastically. This increases the time constants: (a) which is made by the resistance of the connection and the input capacitance of the transistor to which it leads and (b) which is made by the resistance of the connection and the parasitic capacitance to the substrate. Due to this, there is a decrease in the cut-off frequency of the circuit, i.e., the speed of operation of the integrated circuit. In such situations, several layers are used to connect above the surface. They can be made of aluminum or polysilicon, and they are separated from each other by lowtemperature glass (will be shown later on with the CMOS technology). A standard lithographic procedure is used for interlayer bonding.

1.10.3.1 JFET in Bipolar Integrated Circuits JFET is often used to improve the performance of bipolar integrated circuits (when it comes to increasing the input impedance of the amplifier, reduction of noise, etc.). Since the bipolar technology is adapted to the corresponding BJTs, the production of JFET represents a special requirement and significantly increases the price of the integrated circuit. The cross-section of the JFET isolated by diffusion is shown in Fig. 1.10.3.11. The N-area that served as the collector (no buried layer) now serves as the channel. The source is placed symmetrically so that it practically encompasses the component while the drain is in the middle. The carriers move from the periphery to the center. On their path, again symmetrically, there is a gate so that the potential of the gate determines the width of the passage (channel) vertically. To make a P-channel transistor, it is necessary to first form a P-region in the N-diffusion that will serve as a channel. Fig. 1.10.3.11 JFET in a bipolar integrated circuit

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1.10.4 MOS Integrated Circuit The production of MOS transistors with a metal gate in integrated technology is not burdened with such complex problems as is the case with BJTs. Namely, the MOS transistor has the property of self-isolation, which means that it is not necessary to take special measures to isolate transistors with the same channel type. This conclusion is easily reached if one considers that all three areas of MOS transistors (source, drain, and channel) form a depleted area with respect to the substrate, so that between two transistors there are always two diodes connected in opposition. When the N-channel transistor is in question, the common anode of the diodes is the substrate, and the cathodes lie on the corresponding N-regions of one and the other transistor. Due to this, the overall dimensions of MOS integrated circuits (especially digital) can be smaller than the bipolar ones, which made this family very attractive for mass production. There are, however, some parasitic effects that somewhat complicate the picture of the mutual isolation of transistors in MOS integrated circuits. The basic problem is the positive charge in the oxide that is on the surface of the silicon wafer and serves to protect it. In between the transistors, the oxide induces charge under the surface boundary (in the case of P-channel transistors, it brings the substrate into accumulation while in the case of N-channel transistors into inversion i.e., it forms a parasitic channel). This charge changes the conductivity of the surface, which may conflict with the requirement for insulation. This problem is overcome by applying the source and drain electrode over a thicker oxide not only above the drain and source but also above the substrate (this technique will be discussed later in LNAE_Book 4). At the same time, a shallow layer of acceptors is diffused (or implanted) in order to prevent the formation of Nregions on the surface. In accordance with these considerations, an integrated circuit with N-channel transistors (NMOS integrated circuit) was realized, which is shown in Fig. 1.10.4.1. In order to minimize the charge in the oxide and thereby reduce the threshold voltage, the [111] orientation of the crystal is used, where Q’ox = 1.4 · 10–8 C/cm2 . To adjust accurately the threshold voltage one uses ion implantation of impurities. Without it, due to charge in the oxide, an inverted N-type layer would form on the surface, i.e., a channel so that the transistor would work as a component with built-in channels (depletion mode). Fig. 1.10.4.1 NMOS transistors in an integrated environment. a cross section and b top view

1.10.4 MOS Integrated Circuit

307

Unfortunately, increasing the surface concentration reduces the mobility in the channel and increases the capacitance between the channel and the substrate. If these factors are critical, implantation can be omitted with the fact that the threshold voltage would be adjusted by the potential of the substrate in relation to the source (additional battery). Finally, to ensure that the channel is formed along the entire length between the source and the drain (between the ends of the lateral diffusions of the source and the drain), due to the inaccuracy in setting the gate mask (in relation to the ends of the lateral diffusions) in the aligner, it is necessary to have a certain overlapping of the gate metallization with both the source and drain diffusions. In this way, overlapping capacitances are created. Nowadays the CMOS process is dominant for both analogue and digital circuits. To make it easier to understand the purposes of all actions undertaken in this complex process, however, we will first discuss the NMOS process which in fact supplanted the earlier PMOS process. The process of making an NMOS integrated circuit would take place as follows. It starts with a P-type substrate of orientation [100] with N A = 1015 cm−3 . A thick layer of oxide is formed over the wafer by oxidation, which will serve as a mask. The first mask defines the N-type source and drain areas. After the appropriate lithographic process, predeposition, diffusion (N = 1019 cm−3 ), and oxide growth over the diffusion take place. The second mask defines the protective ring. Now the implantation (or predeposition followed by diffusion), hardening, and growth of the oxide are performed, so that a protective ring with N = 1017 cm−3 is obtained. The third mask serves to define the area of the gate that will be covered by a thin layer of oxide (t ox = 0.1 μm). After the growth of the gate oxide, boron is implanted through the oxide so that the threshold voltage is defined (fourth mask). This is followed by tempering in order to regenerate the crystal lattice and activate the boron atoms. The next (fifth) mask is used to form an opening in the oxide for contacts. After applying the metal, it is necessary to define the area from which the metal will be removed, so a new lithographic procedure and a sixth mask are needed. Now, pyrolytic glass is applied over the component using a low-temperature process, and holes for the pads are created in it with the last lithographic process (seventh mask). There is a suitable sequence by which P-channel integrated circuits can be developed. Due to the positive charge in the oxide acting on the N-substrate, it is easier to control the threshold voltage and isolation here. The disadvantage of these components, however, is the lower mobility of the carriers, so the upper cut-off frequency up to which they can be used is also lower. For these reasons, PMOS technology is almost completely abandoned. The cut-off frequency (or operating speed) of the MOS component depends on the concentration in the channel (mobility), channel length (signal propagation time), and capacitances (time required for charging and discharging). In order to maximize the speed, a lower concentration of impurities in the channel should be taken, the length of the channel should be minimized and the capacitance should be minimized. In general, reducing the dimensions of the transistor increases the packing density

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Fig. 1.10.4.2 CMOS—pair a schematic and b simplified cross-section

and the speed of operation simultaneously. In the process that uses an aluminum gate, the length of the channel is defined by a mask. This means that the minimum length is determined by the lithographic process. In addition, the metallization must overlap with the source and drain. This overlap creates capacitances that limit the speed. The production of a complementary transistor (P-channel) in the field of N-channel ones, sets new requirements. This problem is solved by introducing additional diffusion (or implantation) and by changing the type of conductivity of the wafer. Namely, the wafer is now of P-type and N-channel transistors are normally implemented in it. To make a P-channel transistor, first, a deep area (N-well) is formed by diffusion in the P-substrate, which now serves as a substrate for making a P-channel transistor. When a pair composed of P-channel and N-channel transistors are connected according to Fig. 1.10.4.2a a pair of complementary MOS transistors known as a CMOS pair is created. This configuration is widely used (especially in digital electronic circuits) due to low dissipation, although it does not provide such a high degree of integration as NMOS (digital) circuits. For the sake of simplicity, to begin with, the case using a metal gate will be considered here. The cross-section of this structure is shown in Fig. 1.10.4.2b. The concentration in the P substrate is about N A = 3· 1016 cm−3 , and in the N-well it is N D = 1015 cm−3 . With these concentrations, both transistors will work as if they have an induced channel (enhancement mode). As long as the biasing voltages are less than 5 V, the surface under the thick oxide will have the same type of conductivity as the substrate, so that the transistors will be isolated. In other words, the P-region is heavily doped so that it is not depleted under the effect of the positive charge in the oxide. In order to make a faster and smaller MOS component, a method called the self-aligned silicon gate process was developed. In this process, adjusting the length of the channel under the gate does not depend on the mask. The process is shown in a simplified form in Fig. 1.10.4.3 where the complete CMOS sequence was considered. First (Fig. 1.10.4.3a) the preparation for making the P-channel transistor in the P− -wafer is performed. For this purpose, an opening is formed in the photoresist on the surface of the wafer, where the so-called N-well will be created. It is an N-island (in the P-type semiconductor) in which the P-channel transistor will be embedded. After removal of the photoresist, a repeated process of oxidation and heating of the wafer is performed, enabling the diffusion of the implanted atoms deeper into the silicon. Another cycle of removing the oxide and forming a thin oxide allows

1.10.4 MOS Integrated Circuit

309

Fig. 1.10.4.3 CMOS process with self-aligned polysilicon gate

the deposition of silicon nitride, which has a different temperature coefficient than silicon. Thus, a nitride layer is applied over the entire wafer as shown in Fig. 1.10.4.3b. In order to define the areas where the active components (N-channel and P-channel transistors) will be placed, the entire cycle of photolithography is performed with the application of photoresist, illumination, development, and removal of unnecessary material from the surface. Thus, a second implantation was made possible over the

310 Fig. 1.10.4.3 (continued)

1.10 Basics of Semiconductor Technology

1.10.4 MOS Integrated Circuit

311

Fig. 1.10.4.3 (continued)

metal 1 BSPG

CVD oxide

FOx

FOx

-

P substrate m

N-well

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entire surface of the chip, except for the area where the transistors will be formed (Fig. 1.10.4.3c). This implantation prevents the formation of unwanted channels on the surface of the wafer. In the next step (Fig. 1.10.4.3d), one more cycle is performed, which enables P-type implantation, which covers the entire plate except for the Nwell and makes it impossible to form (on the surface of the wafer) parasitic N-channel transistors whose gates would be connections that would later pass over the surface. Now, in order to achieve good insulation between the active areas, a thick oxide grows over the entire wafer, except where there is nitride. This insulation procedure is known as LOCOS insulation. The disadvantage of this procedure is that the oxide is drawn under the nitride and thus reduces the active areas. Figure 1.10.4.3e shows the result that occurs after the formation of a thick oxide. This is followed by the removal of nitride and the formation of a thin oxide that will serve as a gate. Polysilicon is now applied over the entire wafer, which is shown in Fig. 1.10.4.3f. It should be kept in mind that the thin oxide here is practically imperceptible due to its small size. In the next cycle, the polysilicon is shaped so that it forms the gates of the transistors and their connections. Until this moment, the drain and source areas have not been diffused. Modern procedures use LDD diffusion (from: lightly doped drain or source), which minimizes the influence of the impact ionization during implantation. In order for LDD diffusion to be realized, first an oxide layer is formed around the polysilicon, which serves as a spacer, which is shown in Fig. 1.10.4.3g. In the next step, first, the areas that will serve as P-channel transistors are covered (with photoresist) and then N+ is implanted to form the source and drain of the N-channel transistor. These areas are also formed where metal will be connected to the N-regions in order to make ohmic contacts. The situation is shown in Fig. 1.10.4.3h. In this process, the photoresist, polysilicon, and spacers (oxide) act as obstacles for implantation so that the edges of the source and drain are precisely determined by the spacers, which makes it impossible to overlap the gate (polysilicon) and the drain/source. When the spacers are removed (by etching), a lighter drain/source implant is installed, which is shown in Fig. 1.10.4.3i. In this way, an area is formed at the border of the gate with the drain (source) that has a slightly higher resistance than the bulk of the drain (source) and which is precisely adjusted with the polysilicon gate. The length of the channel is therefore determined by this implantation. Considering the lower concentration in the drain (source) on the gate side, later thermal processes that expand the implanted area will have a smaller effect and thus the overlap of the drain and the gate will remain very small. At the same time, due to the lower concentration on the drain side, with normal biasing, the depleted area will partially expand towards the drain, which increases the operating voltages. The entire process of drain/source formation is repeated for the P-channel transistor as shown in Fig. 1.10.4.3j. Now, as seen from Fig. 1.10.4.3k, the transistors are formed and it remains to do the connections and protection of the wafer surface. In order to prepare the contacting of the metal and the drain/source area, a new thick oxide is applied which is shown in Fig. 1.10.4.3l marked with BPSG (from borophospho-silicate glass). The following photolithographic procedure defines the areas where the BPSG will be removed in order to deposit the contact metal. After

1.10.4 MOS Integrated Circuit

313

the application of the metal, a new photo-lithographic process takes place, which will determine the areas from which the metal will be removed and the areas where the metal will remain. This is the so-called Metal 1 layer that connects the transistors with the environment. After etching the metal, the surface is again covered with a new layer of glass (SiO2 ), which is shown in Fig. 1.10.4.3m marked with CVD oxide (CVD = chemical vapor deposition = application from the gas phase). Now, after an additional photolithographic process, the contacts to the metal are opened and a new layer of metal is applied, which serves as an additional degree of freedom for connection. The situation is shown in Fig. 1.10.4.3n. Note that the two levels of metal may be connected by vertical bonds as seen in the figure. After etching and forming connections in Metal 2, the surface of the wafer is passivated (protected from contamination) by means of a new layer of glass, usually SiO2 , but nitride is also possible. At that time, a CMOS integrated circuit was formed. Let us now consider how the silicon gate affects the threshold voltage of the component. The threshold voltage, according to previous presentations, depends on four quantities. By introducing a polysilicon gate, only one is affected: the contact potential difference between the gate and the substrate. Since it is the same material (silicon substrate and silicon gate), a reduction of the threshold voltage can be expected. In fact, the contact potential difference is determined by the difference in Fermi levels due to the difference in carrier concentration in the substrate (P-type) and the gate (N-type). In this way, by controlling the concentration on both sides of the semiconductor, the threshold voltage of the polysilicon gate transistor can be controlled. For example, with a concentration on the surface of silicon of 2 · 1016 cm−3 , the contact potential difference for the aluminum electrode is ϕMS = 0.97 V. When the gate is made of polysilicon with a concentration in it of 1019 cm−3 (same as in the source and the drain) a contact difference of –0.9 V is obtained. When the biasing voltages are higher than +5 V, protective rings must be installed that will prevent the formation of low-resistance paths between adjacent transistors (regardless of the channel type). A sketch of this situation is given in Fig. 1.10.4.4. An N-type ring was used to isolate the P-channel component, and a P-type ring was used to isolate the N-channel component. Through the N-type ring, the substrate is connected to the highest negative potential, and through the P-type P ring, it is connected to the lowest negative potential (or to the ground). In this way, inverse polarization of the P-Well-substrate diode is also ensured. Due to the high concentration in the drain and the protective ring, they should be separated by a region of higher resistance in order to prevent Zener breakdown between them. It can be seen that in Fig. 1.10.4.4 the P-channel transistor has twice the width of the N-channel. This is done in cases where it is important that the P-channel transistor has as close the characteristics of the N-channel one (transconductance, cut-off frequency) as possible. Increasing the channel width compensates for the lower mobility of the holes in the P-channel transistor. In the usual implementations of digital integrated circuits, however, the dimensions of the transistors are the same. Two significant parasitic structures are associated with the CMOS pair. The first one refers to vertical bipolar transistors made up of the N-channel transistor. These are the NPN structures Source-P-well—Substrate and Drain-P-well—Substrate. Since

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Fig. 1.10.4.4 A schematic view (in principle) of the CMOS structure and the guard rings

the source is usually short-circuited to the ground as in Fig. 1.10.4.2 of importance is the vertical NPN transistor on the drain. The base of this transistor is made up of the P-well and if a special terminal (pad) is made for it, a bipolar transistor is created in a MOS circuit that can be used as a common collector amplifier since the collector (N-substrate) is connected to a fixed potential. The input terminal of this amplifier would be the base (P-well), and the output would be the emitter (N+ -drain). The four-layer structure that occurs between the source of the P-channel and the drain of the N-channel transistor is also important. Between these two areas is the N-area of the substrate and the P-well, so that a PNPN structure is formed, which has an external terminal to the P-region. Thus, a thyristor appears (thyristors will be discussed later in LNAE_Book 4) whose anode is the source of the P-channel transistor, its cathode is the drain of an N-channel transistor, and its gate is the Pwell. This structure limits the maximum voltage between the anode and the cathode, and if it is exceeded, it goes into conduction with practically unlimited current. A short circuit occurs. In order to avoid this, a Zener diode whose breakdown voltage is lower than the maximum is usually connected in parallel to the (+) terminal of the integrated circuit. Sometimes, due to the favorable characteristics of MOS transistors from the point of view of input impedance and noise, MOS components in bipolar integrated technology are used in analogue electronic circuits. The input component consists of (a pair of) MOS transistors, and the other amplifier components are bipolar. The method of realization of MOS transistors in standard bipolar integrated circuits with diffusion as insulation is shown in Fig. 1.10.4.5. Figure 1.10.4.5a shows the realization of an enhancement mode P-channel MOS transistor. The N-area of the collector serves as a channel, and the source and drain are formed by base diffusion. In this embodiment, the substrate (collector epitaxy) is connected to the source potential via the N+ contacting area. The depletion mode P-channel transistor (the one with a built-in channel) requires an additional process— implantation of the P-channel in the N-substrate (collector epitaxy). Figure 1.10.4.5b shows a somewhat more complex situation that arises during the realization of an Nchannel MOS transistor in a bipolar integrated circuit. In order to form a transistor, additional P-type diffusion is necessary. The reason for this is that the usual base diffusion has a high concentration of the majority carriers in the channel so that the

1.10.4 MOS Integrated Circuit

315

Fig. 1.10.4.5 MOS transistor in a bipolar integrated circuit a P-channel and b N-channel

threshold voltage of this transistor would be unacceptably high. By choosing the concentration during additional P-diffusion, it is possible to set the channel to be built-in (very small N A ) or induced (relatively higher N A ). It has already been mentioned several times that protection in MOS integrated circuits is also performed using Zener diodes. They can, in addition, be used as sources of reference voltages, so it will be shown here how these components are made in CMOS integrated circuits. Figure 1.10.4.6 illustrates two diodes in a CMOS circuit. The overlapping of the N+ and P+ diffusions is characteristic of this structure. It (the overlapping) forms the depleted region of the diode. One terminal is connected to the power supply so the other can be used as a reference. The MOS structure can be used to make an integrated capacitor more efficiently than the P–N junction. The main advantage of MOS capacitance is the different nature of the dependence of the capacitance on the voltage on it. As we have shown before, the MOS capacitance changes its value only when the surface state changes from accumulation to inversion and vice versa. As long as the surface is inverted (or in a state of accumulation) the capacitance is constant. A simplified representation of MOS capacitance in bipolar integrated circuits is given in Figure 1.10.4.7a, and in the MOS circuit with N-substrate in Fig. 1.10.4.7b. One electrode consists of a metal surface, and the other a semiconductor with high concentration so that it Fig. 1.10.4.6 Two Zener diodes in a CMOS integrated circuit

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Fig. 1.10.4.7 MOS capacitor a in a bipolar integrated circuit and b in a CMOS integrated circuit

can be considered that the surface does not change its state, and that C = Cte . Of course, in order to achieve this condition in MOS integrated circuits, an additional implant is needed, intended only for the production of capacitors (that is not shown in Fig. 1.10.4.7b). The value of the capacitance depends on the thickness of the oxide and on the area. For an oxide thickness of 0.5 μm and considering that εox = 3.45 · 10–5 pF/μm, capacitances of the order of 500 μF/m2 or 0.5 fF/(μm)2 are obtained. In order to get an idea of this size, we will determine the capacitance of a capacitor whose surface is (50 · 50)(μm)2 , which roughly corresponds to the surface of one transistor. By multiplying the surface area (S = 2500 · 10–12 m2 ) by 500 μF/m2 (or 2500 · 0.5), we get a capacitance of only 1.25 pF. At the same time, the breakdown voltage is about 30 V. If one wants a capacitor with a higher breakdown voltage, one should use a thicker oxide, which will reduce the capacitance per unit area. Figure 1.10.4.7 shows the equivalent circuits of MOS capacitors, from which it can be seen that they have series resistance (R < 10 Ω) as well as a parasitic p–n junction to the substrate that degrades their properties. Since the substrate is weakly doped, the width of the depleted area is large, so its parasitic capacitance is small, but if one works with capacitors whose capacitances are in the order of pF, usually, it cannot be neglected. In MOS technology, it is possible to make a resistor in several ways, of which we mention diffused, polysilicon, implanted, and p-well resistors. The diffused resistor is created using source or drain diffusion and is shown in Fig. 1.10.4.8a. The layer resistance of such a resistor is usually in the range of 10 to 100 Ω/⎕. Resistors with small resistances having relatively high voltage and temperature coefficient (due to the dependence of the mobility on the electric field and temperature) and with pronounced parasitic capacitance to the substrate can be obtained with this procedure.

1.10.4 MOS Integrated Circuit

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Fig. 1.10.4.8 Resistor in a CMOS integrated circuit. a source or drain diffusion in a P-well, b polysilicon resistor, and c P-well as a resistor

The polysilicon resistor is shown in Fig. 1.10.4.8b. This resistor is surrounded by thick oxide and has a layer resistance of 30 to 200 Ω/⎕. It is characteristic that it has a very low voltage coefficient and slightly pronounced parasitic effects. If one additional masking step is allowed, a resistor can be obtained as a layer of implanted ions. The properties of this resistor are similar to that of the diffused one, with the fact that a significantly higher layer resistance can be obtained (from 500 to 2000 Ω/⎕). Finally, the P-well resistor shown in Fig. 1.10.4.8c consists of a P-well strip (diffusion) completed with additional P+ source and drain diffusions at the contact points. With this procedure, resistors with a layer resistance of 1 to 10 kΩ/⎕ can be obtained. Their properties in terms of accuracy and stability to changes in the electrical and non-electrical environment are poor, so they can be used as protective resistors and the like. Based on all of this, a conclusion is imposed that was also valid for bipolar integrated circuits. Namely, even when the resistor has stable properties and an exact value (which is difficult to achieve), it will have a small layer resistance. This means that the resistor significantly reduces the packing density of the integrated circuit, and that is why when designing analogue integrated circuit, one tends to replace them by the so-called dynamic resistors or transistors. More will be said about this technique later (LNAE_Book 4). For integrated circuits that are intended for operation at radio frequencies or even for microwave integrated circuits, it is necessary to have the possibility of making an integrated coil. The biggest problem related to integrated or so-called monolithic coils is that they lack a magnetic core that should contain the magnetic flux. As a result, the integrated inductances occupy a large area on the chip, and at the same time there is considerable coupling (interference) with the components in their vicinity.

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The integrated inductance is designed in the form of a spiral, as will be shown in more detail later. Here we will show part of a CMOS integrated circuit that contains such inductances. Figure 1.10.2.9 shows a circuit in which, as can be seen, the inductances occupy an incomparably larger area than the rest of the circuit (shown as darkened areas at the bottom of the figure). The total area of this chip is (0.93 × 0.93) mm2 . The most important parameters of an integrated coil are its inductance, Q-factor, parasitic capacitance to the substrate (and corresponding resonant frequency), as well as the area it occupies on the wafer. In order to achieve parameter values that are closer to the optimum, and especially to reduce the parasitic capacitance, the conductors that make up the spiral are often twisted so that the component according to Fig. 1.10.2.10 arises. Here is shown a five-winding component that has a center tap. The purpose of the middle terminal is to enable the application of this coil in symmetrical circuits, i.e., circuits that handle differential signals. This creates a series connection of two coils that have an external terminal at the point of connection. In order to get an idea of the properties of the obtained component Fig. 1.10.2.11 shows the dependence of the real (R) and imaginary (X) part of the impedance of this coil, which is designed to have an inductance of 6 nH. Figure 1.10.2.12 shows the equivalent circuit of half of the coil viewed between one of the ends and the middle terminal. Numerical values of the model parameter are L = 6 nH, Rs = 9.3 Ω, C s = 220 fF, and Gs = 0.2 mS. The value of the Q-factor is Q = 8.33 at f = 2.43 GHz. When the coil is used without a center tap, the following values are obtained: L = 12 nH, Rs = 18.6 Ω, Q = 7.2 at f = 2.43 GHz. At the end of this overview of the elements of MOS integrated circuits, let us mention that the largest capacitance in the MOS structure is at the junction with the substrate. This backward biased junction has a large surface, so it has a decisive Fig. 1.10.4.9 CMOS monolithic integrated circuit with integrated coils

1.10.4 MOS Integrated Circuit

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Fig. 1.10.4.10 Top view of the coil having a tap in the middle

Fig. 1.10.4.11 The real (R) and imaginary (X) parts of the impedance of half of the coil from Fig. 1.10.4.10

Fig. 1.10.4.12 Equivalent circuit of half the coil between one of the terminals and the tap

influence on the speed of operation of integrated circuits built of MOS transistors. Techniques have appeared that exclude Si as a substrate and use an insulator so that this junction is avoided. That is how the components that got the name SOI (from Silicon On Insulator) are created. The basic principle of these techniques is that epitaxial silicon grows on the insulating substrate, which is later reduced to a solitary island by etching. On that, now a piece of silicon, the source and drain regions are formed by diffusion to produce a transistor. One example of this technique is SOS MOS. Here, the insulating substrate is single-crystal aluminum oxide-sapphire, hence the name (SOS = Silicon On Sapphire). Since sapphire is an extremely good insulator, parasitic capacitances towards the substrate and between components are practically completely eliminated. A section of this structure is shown in Fig. 1.10.4.13.

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Fig. 1.10.4.13 SOS CMOS pair

1.10.5 Hybrid Integrated Circuits In addition to monolithic integrated circuits, microelectronic technology also offers the so-called hybrid integrated circuits. The very name “hybrid”, which means mixed, speaks of the fact that several different technologies are used in the production of such circuits. A hybrid circuit consists of an insulating plate on which passive components, usually in the form of layers (films), and active components are applied (in contrast to monolithic circuits where they were inserted into the crystal) as monolithic chips (of course without encapsulation). With a special procedure, all these components are connected and thus a hybrid integrated circuit is created. There are small exceptions to the above-described procedure for creating a hybrid circuit. Namely, in some situations (with so-called thin-film hybrid circuits) it is possible to make a transistor without installing a silicon chip. Also, it is possible to install a finished passive component (most often the so-called chip capacitor) instead of applying layers. Hybrid integrated circuits are used in special situations when, for example, there is high dissipation or when working at high frequencies. In some situations, when deciding for a circuit to be implemented in hybrid technology, the ability to manufacture passive components with strict tolerances and controlled temperature coefficients plays a decisive role. Although the layers that are applied to the substrate are very thin, due to the nature of current conduction and the method of applying the layers, hybrid integrated circuits are divided into thin-layer and thick-layer ones. The thickness of the resistive, conductive, insulating, and dielectric layers in the thin-film technique ranges from 0.01 to 0.1 μm. In the case of thick-film circuits, we find layers with a thickness of 12–25 μm. Due to the mentioned difference in operations in the technology of hybrid integrated circuits, in the following text thick-film and thin-film circuits will be considered separately.

1.10.5.1 Thick-Film Integrated Circuits For the sake of easier understanding of the manufacturing method and the characteristics of hybrid integrated circuits, we will use Fig. 1.10.5.1, which describes the process of manufacturing a thick-film circuit. First, as with all other circuits, one needs to find an electrical schematic that performs the desired function. Here, of

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course, we also mean numerical values of the circuit parameters both of active and passive components. After the selection of the chips (Integrated circuits, discrete transistors, diodes, and chip passive components) that will be mounted (this is important at this moment because of the dimensions), it becomes possible to solve the problem of designing the passive components and connections which are realized as films. Namely, passive components and connections are applied in the form of layers, so for the given characteristics of the layer, the shape of the surface occupied by that layer should be determined. Rectangular shapes are usually used. Of course, the problem of placing and routing passive and active components on the surface of the substrate should also be solved. When these problems are solved, one can start making masks. For each applied layer it is necessary to design one mask. The material, which will become a layer on the substrate after processing, before use has the form of a paste (named ink) and is usually applied to the substrate by screen printing. This procedure, in turn, implies the existence of a screen whose holes are partially open so that the ink is applied to the substrate under pressure through the open part and forms a pattern according to the designed component or connection. This gives the layer its shape, but not its final electrical properties. In the next phase, the layer is dried in order to remove the solvents that gave the necessary fluidness, and then it is baked (sintered) in order to obtain the final electrical characteristics. Fig. 1.10.5.1 The flow of designing and manufacturing a thick-film integrated circuit

Synthesis of the circuit’s schematic

Testing Packaging Testing

Design of the masks

Functional trimming the resistors

Production of the masks

Preparation of the screen

Repetition as many times as necessary

Mounting the components (chips)

Trimming the resistors

Printing Drying

Firing

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Applying a layer by screen printing, drying, and firing is repeated for each layer. Sometimes it is possible to apply several layers (usually such layers do not overlap) and drying and firing are done at the same time. A special property of thick-film integrated circuits is the possibility of adjusting (by trimming) the values of the passive elements. This is achieved by subsequent refinement of the shape of the layer by abrasion or by a laser beam. With special care, components can be made with tolerances tighter than 0.1%. In order to make this possible, when connecting the elements, some of them remain unconnected so that their value can be set before the final connection. After adjustment, the element is included in the circuit by additional soldering. After mounting the chips and soldering, one gets a complete circuit whose characteristics may deviate from the desired one due to wider tolerances of non-adjustable elements (especially monolithic chips). Therefore, by adjusting the values of some passive elements created as film, it is possible to fit the characteristics of the real circuit into the given requirements. This means that by deviating the values of the parameters of the elements that we adjust, we compensate for the deviations of the parameters of the elements that cannot be adjusted. This setting is functional. Note that, here, analogue circuits are under consideration. The quantity to be adjusted may be the nominal gain or the cut-off frequency (or something else) of the thick-film integrated circuit. Of course, to perform this phase one needs constant and repetitive measurement. This is followed by testing before encapsulation, bonding (connecting the terminals from the substrate to the pins of the components), and encapsulation. The finished component is also tested. The described sequence roughly describes the process of making thick-film hybrid integrated circuits. In the following text, some more details will be given about the individual aspects of the production of thick-film circuits. Let us first consider the materials used in this technology. The substrate on which the layers are applied should have the following properties: high mechanical strength, high electrical resistance, high breakdown voltage, low dielectric losses, high thermal conductivity, low-temperature expansion coefficient, and smooth surface. These properties are mainly satisfied by two materials. The most commonly used sintered wafer (therefore has a granular internal structure) made of Al2 O3 (96%) containing 4% MgO and SiO2 . The disadvantages of this material include the need for surface polishing and relatively low thermal conductivity (0.25 J/(cm °Cs)). When the thermal properties of the wafer are of decisive importance, BeO (99.5%) is used. The thermal conductivity of this material is 2.4 J/(cm °Cs). Its disadvantage, however, is the toxicity of its surface, so great care must be taken when handling these wafers. For the production of passive components, as already mentioned, inks are used. The ink usually consists of several components that should provide: the basic property of the component (resistance, conductivity, dielectric or insulating properties), adhesion of the ink to the substrate, and mechanical properties related to screen printing. Therefore, the ink contains particles of metals, alloys, metal oxides, and glass, as well as solvents, agent which wets, etc.

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When talking about making conductors that will connect components on a hybrid integrated circuit, conductive inks are used. The basic properties that should be provided by these inks are: good adhesion to the substrate, providing as narrow a conductive strip as possible, good solderability, good adhesion to the ends of the thick-film resistor to which they are attached as well as a small layer resistance. The best results are obtained by inks that contain mixtures of platinum or palladium with silver or gold as a conductive material. With an ink based on Pd and Au, it is possible to reliably produce a conductive strip as narrow as 20 μm. However, due to the lower price, inks based on Pd and Ag are most often used. With the aforementioned pastes, a layer resistance of 0.003 to 0.2 Ω/⎕ can be achieved. Obtaining as little layer resistance as possible is extremely important in order to reduce the resistance of long and narrow strips (which have a large number of squares) and thus reduce the voltage drop on them. It should be kept in mind that in a hybrid circuit, the connection (strips) can be longer than 1 cm. For the production of thick-film resistors, an ink similar to that used for conductors is used except that instead of conductive metals, ruthenium dioxide, bismuth ruthenate, iridium dioxide, etc. are used. For application at high temperatures, the so-called cermets (ceramic + metal) based on molybdenum and manganese are preferred. In order to obtain the appropriate resistance, the ratio of the amount of metal (or oxide) and glass in the paste usually varies in favor of one or the other. With these inks, the layer resistance can be controlled from a few Ω/⎕ to 10 MΩ/⎕. This does not mean that with every material it is possible to obtain inks with such a wide range of layer resistance, but with a given material, by changing the content ratio of conductors and glass, it is easy to control the layer resistance in a range of four order of magnitude. At least two materials will be needed to create a circuit with a larger resistance range. During the creation of the hybrid circuit itself, for a given resistance of the resistor, we can choose the length, width (number of squares), and layer resistance (type of ink). If only one ink is used to make all the resistors, there is a risk of creating disproportionately large (by area) resistors. For example, if we use ink having 1 KΩ/⎕, to make a resistor of 1 MΩ, it takes a thousand squares. On the other hand, resistors whose dimensions are less than 1/3 ⎕ are not recommended due to parasitic effects. Therefore, when making one hybrid circuit, we usually must use several inks, for example, three, where RS1 = 1 Ω/⎕, RS2 = 10 Ω/⎕, and RS3 = 100 Ω/⎕. They can be made of the same material but with a different ratio of the amount of oxide and glass. Since for the application of each ink, a separate mask must be made (and often the drying and baking process must be done independently), increasing the number of inks significantly increases the cost of making a hybrid circuit. This means that when synthesizing the circuit, care should be taken to minimize the dispersion of the resistance value in the circuit, thus reducing the required number of masks. The temperature coefficient of the thick-film resistor is between −10–4 and +10–4 Ω/ΩK. Insulating inks can be used for the production of thick-film capacitors or for covering conductors at the intersection of conductive strips. In the first case, ceramics (BaTiO3 ) is most often used, with which capacitances of up to 40 nF/cm2 or 400

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μF/m2 can be achieved. When a very large Q-factor is desired, crystal glass is used. To separate conductors that cross, inks are used that are usually based on amorphous glass. Let us now consider in more detail the technique of making thick-film circuits. The key step in this process is screen printing, so we will first consider the production of the screen. Among several variants, we will take a screen consisting of steel wires with a diameter of about 50 μm arranged at distances of about 70 μm. In order to prepare it for use in screen printing, a photosensitive material is applied to the screen, which is then illuminated through a mask with ultraviolet light. The mask is removed, and the screen is rinsed and blown in order to remove the unwanted part of the emulsion from the grate and allow the paste to pass through here later. The screen printing process itself takes place by placing a screen on top of the substrate (on which the hybrid circuit is formed) onto which the ink is applied. Then a squeegee is moved over the surface of the screen so that the paste is forced to pass through the holes on the screen and thus applied to the substrate. The entire process is shown in Fig. 1.10.5.2. The thickness of the layer, and thus to a large extent its properties, depends on the pressing force and the speed of the squeegee. The substrate obtained in this way is first dried in order to evaporate the solvents. This is usually done at a high temperature, but in such a way that it does not cause chemical processes in the ink. Then the firing is started. Usually, firing lasts 45 min, with the wafer constantly moving through the oven in which there is a temperature profile according to Fig. 1.10.5.3a. First, by gradually raising the temperature, the remaining organic materials are burned, then, in the interval when the maximum temperature is reached, the sintering Fig. 1.10.5.2 Screen printing. a view of the screen and squeegee before lowering the squeegee (The arrows indicate the direction of movement of the presser) and b a sketch of the set where the straining of the screen under pressure at the point of contact can be seen

Squeegee Ink

Frame Pattern letting of the ink through screen the screen

a Frame

Squeegee

Ceramic pad

screen

b

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Fig. 1.10.5.3 a Temperature profile for firing the ink, b ink after firing, and c appearance of the screen

a

Galss

Voids

Metal chips

b

Substrate

c

of the grains of the basic material and the glass, as well as the grains of the glass with the substrate, takes place and, finally, in the interval of cooling-down the aim is to minimize glass breakage. It should be noted that the value of the maximum temperature has a decisive effect on the result of sintering, and thus on the electrical properties of the layer. In conductive inks, the fusion of conductive grains dominates, as shown in Fig. 1.10.3.5b, and thus the resistance is reduced. The required temperature is around 900 ◦ C at most. In resistive ink, the metal grains are usually surrounded by glass grains and sintering takes place at lower temperatures. In Fig. 1.10.3.5c we used the space to display part of the screen. Another process used in thick-film technology may be of interest. It is the assembly of monolithic and other chips. For this purpose, we have already prepared connections on the ceramic substrate, realized with conductive ink. Chips, however, are prepared in a special way. At the points of contact (pads), metal parts are applied that are significantly above the silicon surface. Now the chip is turned down and the metal extensions are soldered to the contact point as in Fig. 1.10.5.4. Let us now consider the passive components themselves, made in thick-film technology. The thick-film capacitor is a three-layer structure. The lower electrode is made of conductive material and it is fired before applying the dielectric ink. The

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Fig. 1.10.5.4 Assembly of chip components for hybrid technology

dielectric is applied in two layers so that the first layer dries and only then is the second layer applied and dried. After firing the dielectric, which completely covers the lower conductive coating, the upper conductive coating is printed, dried, and fired. The structure of the thick-film capacitor is shown in Fig. 1.10.5.5. It can be seen that the surface of the capacitor is determined by the upper conductive electrode, which is significant from the point of view of later finishing—adjusting the capacitance. Capacitors made in this way have a temperature coefficient of the order of ≈10–4 F/FK, and tolerances up to ≈20%. With subsequent adjustment, tolerances of 3% can be achieved. If a large capacitance is realized, a large area of the substrate may be occupied. In such a case, the use of miniature capacitors (chip capacitors) is often resorted to, which are applied to the substrate in the same way as active components (Fig. 1.10.5.4). A thick-film resistor is the most important component of a thick-film integrated circuit. It is usually made in the form of a rectangle and is recommended to be Fig. 1.10.5.5 Thick-film capacitor. a top view and b section A-A‘

Fig. 1.10.5.6 Thick film resistor. a top view and b section

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327

distributed parallel to the edges of the substrate. The structure of the resistor is shown symbolically in Fig. 1.10.5.6. It is not recommended to design resistors with dimensions less than 1/3 ⎕ or larger than 5 ⎕. Adjusting the value of the resistor is achieved by reducing the cross-section of the resistor by cutting the resistive layer. The cutting methods are shown in Fig. 1.10.5.7. It can be seen that first a cut is made perpendicular to the longitudinal axis of the resistor and if such a cut is not enough, it is extended along the resistor. There are some additional tricks in performing the cutting in order to reduce current congestion around them. The adjustment procedure itself is performed with the help of an automatic machine that cuts and simultaneously measures the resistance value. Cutting stops automatically when the desired resistance is reached. Cutting can be achieved by the abrasive effect of a jet of fine grains (which must then be vacuumed out to keep the surface clean) or by a laser beam. Although this second procedure seems naturally more convenient, there are problems regarding the reflection of the laser beam from the surface of some materials that would be processed. It is easy to see that trimming can only increase the resistance value of the resistor (with capacitors, the capacitance only decreases). Therefore, the resistors that will be adjusted are designed so that they surely have a lower resistance than required. When designing resistors, special attention should be paid to heat removal. Namely, for a given dissipated power and thermal resistance between the layer and the substrate, we can find the minimum area of the resistor that provides the desired cooling. From these considerations, we mainly determine the dimensions of the square. Inductors are not made in the form of thick layers, and as already said, if one insists on thick-layer technology, the problem of inductors and large capacitances is not solved. That is why miniature passive components, so-called chip components that are mounted as discrete active components or monolithic integrated circuits. An example of a chip coil with a magnetic core is shown in Fig. 1.10.5.8. Based on everything presented, we can conclude that thick-film hybrid integrated circuits represent an alternative to monolithic circuits in cases where the dissipated power is relatively large since they can withstand higher working temperatures (up to 300 °C). They behave better in presence of moisture in the surrounding atmosphere. In presence of radiation (space applications) hybrid circuits behave better than the monolithic ones. Then, they are preferable in cases when the number of passive components (especially resistors) is relatively large. The ability to adjust circuit parameters can also be decisive when choosing this technology. Finally, a thick-film circuit can replace a printed circuit board on which components with completely different purposes are applied (opto-components, bipolar analogue and digital, MOS digital, sensors, etc.).

Fig. 1.10.5.7 Adjusting (trimming) the value of the thick-film resistor a transverse notching, b a combination of transverse and longitudinal notching

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Fig. 1.10.5.8 a Chip coil (photo) and b Chip coil (drawing)

1.10.5.2 Thin-Film Hybrid Integrated Circuits The essential difference between thin-film and thick-film hybrid circuits is in the method of application and the chemical composition of the applied layers. In the thinfilm technique, mainly two application techniques are used: the vacuum evaporation technique and the sputtering technique. In doing so, it is possible to apply thin layers through the mask (the mask in this case has the shape of a screen and through it pass the particles that are applied to the substrate) or cover the entire substrate with a thin layer which is then by a photolithographic process and subsequent etching shaped as desired. Vacuum evaporation is achieved by transferring material from a heated steam source (sublimation, in fact) to a substrate, which here represents the condensation surface. All this is done in a high vacuum. At such low pressures, the mean free path of vaporized molecules or atoms exceeds the dimensions of the space in which the evaporation takes place, so it can be said that the molecules travel in a straight line without collision and settle on the substrate. The heating of the carrier, from which the corresponding material evaporates, is usually performed by an electron beam that starts from a thermionic cathode. Therefore, the carrier should be placed in a closed electric circuit (well grounded). The substrate on which the molecules are deposited is relatively close, so it must be cooled. Cathode sputtering is relatively more complex. It takes place in a vessel filled with inert gas under low pressure (Fig. 1.10.5.9). When a high voltage is applied to the tube, an arc discharge occurs so that the inert gas atoms are ionized and hit the cathode. A material that will serve as a thin-film is already applied to it. Under the impact of inert gas ions, it evaporates and diffuses through the tube until it meets the substrate where it will settle. By properly placing the anode, on which the substrate of the hybrid circuit is located, most of the steam will settle on the substrate. To form thin layers of insulators or semiconductors between the anode and the cathode, an alternating voltage of radio frequency acts. There are a number of variants of the sputtering procedure (Fig. 1.10.5.10). Of course, it should be kept in mind that these two techniques are also used when making thin layers in monolithic circuits (metal, polysilicon, oxide, etc.).

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Fig. 1.10.5.9 Cathode sputtering

Fig. 1.10.5.10 A 48 square thin-film resistor (strip width is 25 μm)

Let us now consider the materials for thin-film circuits. The substrate that will be used in this case must be very smooth. BeO, Al2 O3, or crystalline Al2 O3 (sapphire) glass or ceramics are used. In this case, Al2 O3 in non-crystalline form is processed so that it has an unevenness of less than 1 μm without polishing. Nichrome is most often used for thin-film resistors. It is a nickel–chromium alloy with 20% chromium that has a specific resistance of 110·10–6 Ωcm. With this alloy, layer resistances of the order of 500 Ω/⎕ are easily obtained. Cermets (composite materials composed of ceramic and metal) are usually used to obtain very high resistances. Aluminum, gold, and palladium are most often used for conductive strips in thinfilm technology, as well as in monolithic circuits. In this case, the choice of material represents a compromise between conductivity and adhesion of the conductor to the substrate. The following oxides are used as the dielectric layer of a thin-film capacitor or as an insulator when crossing connections: SiO, SiO2 , Al2 O3, and Ta2 O5 . Tantalum pentoxide, whose relative dielectric constant is larger than 20, is of interest for making capacitors. This material reaches a capacitance of about 200 nF/cm2 . Before considering the components realized in the thin-film technique, the conductive properties of the thin layers will be considered. Namely, if the thickness of the layer is very small, i.e., of the same order of magnitude or smaller than the length

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of the electron’s mean free path, scattering on the surface becomes significant. This scattering is more pronounced if the layer is thinner and as a global consequence has a decrease in mobility, i.e., an increase in layer resistance. This means that the layer resistance of a thin-film depends on the material used, but also on the thickness of the layer. Thus, a layer of tantalum with a thickness of 0.015 μm has a layer resistance of 11.25 Ω/⎕, while a thicker layer of 0.15 (ten times) has only 0.9 Ω/⎕ (about one hundred times lower). The shape of the thin-film resistor is basically similar to the shape of the thick-film resistor, with the difference that here we have a smaller layer resistance, so a larger number of squares is often needed. This means that the thin-film resistor is shaped like a diffused resistor in monolithic circuits (Fig. 1.10.3.7d). Different materials used exhibit different temperature coefficients of the resistance of the thin-film. If two-layer resistors are used (as a parallel connection and so that the layers have temperature coefficients of different signs), the total temperature coefficient can be significantly reduced. The thin-film capacitor is a three-layer structure. The lower plate is usually tantalum, the dielectric is tantalum pentoxide, and the upper plate is gold as a continuation of the conductive layer (Fig. 1.10.3.11). The typical loss of this type of capacitor is tg(δ) = 3·10–3 . Now it is easy to see that thin-film circuits are extremely suitable for making RC networks. It is possible to make coils using thin-film technology, but with limited inductance values. They are usually made in the form of a spiral, with the inner end of the spiral having a contact and connection under the insulator. Such a structure seen from above is shown in Fig. 1.10.3.12. The dimensions of the coil are about (1.5 × 1.5) mm2 , and L = 40 nH and Q = 30 at 500 MHz were obtained. As was said at the very beginning, the specificity of the thin-film integrated circuit is that it is possible to make a thin-film transistor. The properties of this transistor are similar to the properties of a MOSFET, and the mode of operation itself is reminiscent of the operation of a MOSFET, too. The structure of the thin-film transistor is shown Fig. 1.10.3.11 Cross section of a thin film capacitor

Fig. 1.10.3.12 A coil in a thin-film integrated circuit

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Fig. 1.10.3.13 Thin film transistor

in Fig. 1.10.3.13. First, source and drain metallization is applied to the substrate. Then a thin layer of semiconductor, in this case, CdS, is sputtered. This semiconductor makes an Ohmic contact with the metal strips so that p–n junctions are not needed as with MOSFETs. An insulator is applied over the semiconductor, and then a strip of metal that will serve as a gate. Such a transistor is equivalent to an N-channel MOSFET. The very operation of the transistor can be explained by considering the semiconductor as a high resistance material (the energy gap of CdS is about 2.4 eV) so that in the absence of the gate field, very small current flows in the circuit (between the source and the drain). By applying a voltage to the gate, the semiconductor can be brought to a state of accumulation and the current flow increases. Thus, modulation of the resistance of the semiconductor, and consequently current flow through the transistor, is enabled. The characteristics of these transistors are modeled in the same way as the characteristics of depletion mode (built-in channel) MOS transistors, but with a very small (per absolute value) threshold voltage. All this suggests that the most important applications of thin-film integrated circuits will be in the area of very high frequencies. A variant of this technology is the so-called microstrip technology used in microwave circuits, which uses piezoelectric substrates.

1.11 Solved Problems

Problem 1.11.1 Determine the concentration of free electrons (n) and holes (p) in a silicon sample at a temperature of 300 K. The donor and acceptor impurity concentrations are: (a) N D = 2 · 1011 cm−3 and N A = 3 · 1011 cm−3 , (b) N A = N D = 1015 cm−3 , (c) N D = 1015 cm−3 and N A = 1011 cm−3 . Note: The number of free carriers and their mobilities can be read from Table 1.2.2.2. Solution to Problem 1.11.1 For the product of the concentrations of free charge carriers in a semiconductor, the following applies: n · p = n 2i .

(1.11.1.1)

On the other hand, to preserve electrical neutrality, the sum of the negative charges in the semiconductor must be equal to the sum of the positive charges so that: n + NA = p + ND ,

(1.11.1.2)

where the total negative charge consists of free electrons and immobile ionized acceptor atoms while the total positive charge consists of holes and immobile ionized donor atoms. Solving the system of Eqs. (1.11.1.1) and (1.11.1.2) yields expressions for the concentrations of free electrons and holes as: | | / n = (ND − NA ) ± (ND − NA )2 + 4n 2i /2

© The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 V. Litovski, Lecture Notes in Analog Electronics, Lecture Notes in Electrical Engineering 1002, https://doi.org/10.1007/978-981-19-9868-3_11

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and p = −(ND − NA ) ±

/ (ND − NA )2 + 4n 2i /2

As the charge concentrations are positive numbers, only positive solutions should be considered, i.e., | | / 2 2 (1.11.1.3) n = (ND − NA ) + (ND − NA ) + 4n i /2 and p = −(ND − NA ) +

/

(ND − NA )2 + 4n 2i /2.

(1.11.1.4)

(a) Based on (1.11.1.4), while one uses ni = nSi = 1.5 · 1010 cm−3 , the concentration of holes is: p = 1.022 · 1011 cm−3 . The concentration of free electrons can be calculated using (1.11.1.1) from which it follows that: n = n 2i / p = 0.022 · 1011 cm−3 . Based on the obtained values of the concentration of free charge carriers (i.e., p > n), it can be concluded that this sample behaves as a P-type semiconductor. (b) From (1.11.1.2) it follows that the concentrations of holes and free electrons are equal and based on (1.11.1.1) it is obtained that n = p = n Si . So, if a semiconductor sample is doped with the same concentrations of acceptor and donor impurities, it behaves as an intrinsic semiconductor. (c) Based on numerical data from this part of the problem, it can be considered that N D >> N A , and from (1.11.1.2) it is obtained that n >> p, which means that based on (1.11.1.2) one can write: n ∼ = ND = 1015 cm−3 . From (1.11.1.1) one can get that: p = n 2Si /n = 2.25 · 104 cm−3 . Since in this case n > p, this sample is an N-type semiconductor. Note: For easier calculations, approximate numerical values for the intrinsic concentrations of charge carriers in the semiconductor are used here, and not those given in Table 1.2.2.2. (for Ge: nGe = 2.5·1013 cm−3 , for Si: nSi = 1.5·1010 cm−3 ). These numerical values will also be used in the following problems unless the problem requires the use of more correct ones. Problem 1.11.2 (a) Determine the specific resistance of pure silicon at temperature T 0 = 300 K. (b) Determine the specific resistance of the given sample in the event that donortype impurities were added so that the ratio of the number of silicon atoms and impurity atoms is equal to 108 .

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335

Note: The number of free carriers and their mobility can be read from Table 1.2.2.2. Solution to Problem 1.11.2 (a) The following expression applies to the specific conductance of a semiconductor: ) ( σ = q · n · μ n + p · μp ,

(1.11.2.1)

where n and p are the concentrations of free electrons and holes, respectively, and μn and μp are their mobilities. For an intrinsic semiconductor we have: n = p = n Si = 1.45 · 1010 cm−3 . (So, from) (1.11.2.1) the specific conductivity of this sample is σ = q · n Si μn + μp = 4.24 · 10−6 (ocm)−1 , and the corresponding specific resistivity is: ρ = 1/σ = 2.3 · 105 ocm. (b) The concentration of donor impurities can be calculated from the given ratio: NSi /ND = 108 , which leads to: ND = NSi /108 = 5 · 1014 cm−3 . Since there are no acceptor impurities in the semiconductor sample, based on (1.11.1.2) it follows: n ∼ = ND = 5 · 1014 cm−3 , so that the concentration of holes amounts 2 to: p = n Si /n = 0.42 · 106 cm−3 . Now it is easy to find the specific conductance of the sample: σ = q · (n · μn + p · μp ) = 0.108 (ocm)−1 , so that the specific resistance is: ρ = 1/σ = 9.62 ocm. Now, by comparing the result obtained under a and b one may draw conclusions on the immense influence of the impurities on the specific resistance of the semiconductor sample despite the fact that their concentration is still (much) much smaller than the number of silicon atoms per cubic centimeter. Problem 1.11.3 (a) Determine the concentration of holes and free electrons in a P-type germanium sample that is at temperature T 0 = 300 K and has a specific resistance ρ = 1 ocm. (b) Repeat the procedure from the previous part of the problem for an N-type silicon sample that has a specific resistance ρ = 100 ocm. Solution to Problem 1.11.3 (a) Since it is P-type germanium, it is p >> n, so based on (1.11.2.1) we get: ρ = 1/σ = 1/(q · p · μp ). Wherefrom the concentration of holes becomes: p = 1/(ρ · q · μp ) = 3.47 · 1015 cm−3 . The electron concentration is then: n = n 2Ge / p = 1.8 · 1011 cm−3 . (b) Similar reasoning shows that the concentrations of free electrons and holes in the silicon sample are n = 4.6 · 1013 cm−3 and p = 4.9 · 106 cm−3 , respectively.

336

1.11 Solved Problems

Here we want to draw the reader’s attention to the important difference in the properties of Ge and Si. Namely, the resistivity of Ge is 100 times smaller than the one of Si despite the fact that the concentration of the majority carriers in Si is 100 times larger (even though one can object since we are comparing P-type Ge and N-type Si samples). Note: The specific resistance of a pure germanium sample is 47 ocm, and of a pure silicon sample 2.3 · 105 ocm. By adding impurities of any type, these resistances are reduced. As the mobilities of the carriers in the semiconductor sample are functions of the impurity concentration (see Fig. 1.2.3.15) which, up to concentrations of the order of 1015 cm−3 , can be considered constant, this problem can be solved in the described way if the specific resistance of the sample is larger than 1 ocm for germanium or 10 ocm for silicon. Otherwise, the problem becomes non-linear and is solved using a graph like the one in Fig. 1.2.3.15. Problem 1.11.4 Calculate the percentage change in the specific conductivity of silicon for the case when the temperature changes from T 0 = 300 K by /\T = 1 K. The energy gap width is given by: E g (T ) = E g (0) − α · T 2 /(T + β)

[eV],

(1.11.4.1)

where E g (0) = 1.165 eV, α = 7.02 · 10–4 eV/K and β = 1108 K. Neglect the temperature dependence of the mobility of free carriers. Solution to Problem 1.11.4 Based on (1.11.2.1) the specific conductivity of the pure semiconductor is given by: ) ( σ(T ) = q · n Si (T ) · μn + μp .

(1.11.4.2)

The change in this conductivity due to the change in temperature is a consequence of the change in the intrinsic concentration of charge carriers ni . The dependence of the intrinsic concentration of the carriers on the temperature is given by the expression: n Si (T ) = A · T 3/2 e−Eg (T )/(2·kT ) .

(1.11.4.3a)

Taking the logarithm of both sides leads to: ln[n Si (T )] = ln( A) + 1.5 · ln(T ) − E g (T )/(2 · kT )

(1.11.4.3b)

and after differentiation of both sides, we get: | | E g (T ) dT 3 α T +2·β dn Si (T ) 2 · = + + · . · T 2 n Si (T ) 2 2 · kT 2 · kT (T + β) T

(1.11.4.4)

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337

Based on (1.11.4.1) the size of the energy gap of Si at T 0 = 300 K is: E g (300) = 1.12 eV, so that from (1.11.4.4), at T 0 = 300 K and /\T = dT = 1 K one gets: dn Si (T )/n Si (T ) = 0.08235.

(1.11.4.5)

After logarithming (1.11.4.2) and taking the derivative one gets: dn Si (T ) ds(T ) = ⇒ 8.235%. σ(T ) n Si (T )

(1.11.4.6)

It is noticeable that the relative change of the conductivity of the intrinsic silicon is large even for a small temperature change of only /\T = 1 K. Problem 1.11.5 At what temperature will the concentration of minority carriers reach 1% of the concentration of the majority carriers in a sample of silicon doped with 5 · 1013 boron atoms per cm3 ? Assume that energy gap does not change with temperature. Solution to Problem 1.11.5 At T 0 = 300 K the concentrations of holes and electrons in a doped silicon are, respectively: p(T0 ) ∼ = NA = 5 · 1013 cm−3 and n(T0 ) = n 2Si (T0 )/ p(T0 ) = 0.45 · 107 cm−3 . As the temperature increases, new electron–hole pairs will be generated, and at a certain temperature T the carrier concentration will be: p(T ) = p(T0 ) + /\p and n(T ) = n(T0 ) + /\n, where /\p = /\n. As, in this case, it is a P-type semiconductor, it is p(T 0 ) >> n(T 0 ), which means that the increment of the concentration of holes, /\p, is much smaller than the very concentration of holes, p, at T 0 , i.e., p(T0 )>>/\p. Accordingly, at the temperature T for the concentration of holes, one has p(T ) ∼ = p(T0 ). In order for the concentration of minority carriers to reach 1% of the concentration of majority carriers, it is necessary to reach the value:n(T ) = p(T )/100 = 5 · 1011 cm−3 . This means that at the required (unknown) temperature, T, the product of the concentration of electrons and holes is: n 2Si (T ) = n(T ) · p(T ) = 25 · 1024 cm−6 or n Si (T ) = 5 · 1012 cm−3 . It follows from (1.11.4.3a) and (1.11.4.3b) that the ratio of the intrinsic concentration at temperature T and the intrinsic concentration at temperature T 0 is:

338

1.11 Solved Problems E n Si (T ) − g ·(T /T −1) . = (T /T0 )3/2 · e 2·kT0 0 n Si (T0 )

(1.11.5.1)

After taking the logarithm of both sides one gets (

T ln[n Si (T )/n Si (T0 )] = 1.5 · ln T0

)

Eg · − 2 · kT0

(

) T0 −1 . T

(1.11.5.2)

This expression may be simplified if one supposes that the change of temperature is not large (i.e., T /T 0 ≈ 1) and considering that E g /(2kT ) >> 1.5. If so, it may be rewritten in the form: ( ) Eg T0 · −1 . (1.11.5.3) ln[n Si (T )/n Si (T0 )] ≈ − 2 · kT0 T Solving this equation for T yields the required temperature as: T =

T0 1−

2·kT0 Eg

(T ) · ln nnSiSi(T 0)

= 410K .

(1.11.5.3)

If it is assumed that the room temperature is T 0 ≈ 25 °C, the obtained result means that T ≈ 135 °C. Problem 1.11.6 Determine the position of the Fermi level in relation to the level of the upper limit of the valence zone of the silicon wafer which is doped with acceptor impurities of concentration N A = 5 · 1014 cm−3 . The plate is at a temperature of 300 K. Solution to Problem 1.11.6 The concentration of holes is approximately equal to the concentration of acceptor impurity atoms: p∼ = N A.

(1.11.6.1)

On the other side according to (1.2.3.25) it is: p = Nv · e−(Ef −Ev )/(kT ) .

(1.11.6.2)

Combining the last two expressions one gets: E f − E v = kT · ln(Nv /NA ), or: E f − E v = 0.258 eV.

(1.11.6.3)

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339

Fig. 1.11.7.1 Energy diagram

Problem 1.11.7 Calculate the value of the potential difference in silicon having an uneven distribution of donor impurities from ND+ = 1017 cm−3 to N D = 1014 cm−3 . Set T 0 = 300 K. Solution to Problem 1.11.7 When no electric current flows through the semiconductor, the Fermi level is constant along the entire sample so that individual energy levels occupy positions as shown in Fig. 1.11.7.1. For the concentration of electrons in the heavily doped part of the semiconductor, the following applies: − n+ ∼ = ND+ = Nc e

E c+ −E f (kT )

,

(1.11.7.1)

while in the less doped part of the sample is: n∼ = ND = Nc e−(Ec −Ef )/(kT ) .

(1.11.7.2)

Based on (1.11.7.1) and (1.11.7.2) one may produce: N+ n+ + = D = e−(Ec −Ec )/(kT0 ) . n ND

(1.11.7.3)

From Fig. 1.11.7.1 it can be seen that an energy barrier has been created as: E 0 = E c − E c+ ,

(1.11.7.4)

and based on (1.11.7.3) and (1.11.7.4) for E 0 we get: ( E 0 = (kT0 ) · ln and the required potential difference is:

) ND+ , ND

(1.11.7.5)

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1.11 Solved Problems

( +) ND kT0 E0 = · ln = 0.18 V. V0 = q q ND

(1.11.7.6)

Problem 1.11.8 A silicon diode is doped on the N side with N D = 1016 cm−3 , and on the P side with N A = 4 · 1018 cm−3 (This is considered a diode with abrupt junction). Calculate the contact potential, the width of the transition region, and the maximum value of the electric field under the condition that the diode is not biased and the temperature is T 0 = 300 K. Solution to Problem 1.11.8 It is known, Eqs. (1.3.2.51a) and (1.3.2.51b), that the width of the transition region of the abrupt p-n junction is given by: / w0 = wn0 + wp0 =

2 · e · V0 · q

(

) 1 1 , + ND NA

(1.11.8.1)

where, based on (1.3.1.6), the expression for the contact potential is: V0 =

kT0 NA ND = 0.83 · ln q n 2i

V.

(1.11.8.2)

The expression (1.11.8.1) can be simplified if it is considered that N A >> N D . In that case, the transition region extends to a greater amount in the N area, so that: / (1.11.8.3) w0 ≈ wn0 ≈ (2 · ε · V0 )/(q · ND ) = 3.28 · 10−5 cm. Finally, the peak value of the electric field in the transition region is given by the expression (1.3.2.44) for x = 0: K max = −q · ND wn /ε = −5 · 104

V , cm

(1.11.8.4)

or K max = –50 kV/cm. The result obtained is a hint to the events going on in semiconductor components when fields are considered. Namely, due to small dimensions even small voltage differences lead to very high fields. To illustrate, the grid line bearing 10 kV running as high as 10 m, is producing a field between the wire and the ground of 0.01 kV/cm only. Such high fields between layers in a semiconductor produce stress to the material and are one of the important reasons of aging of the components. Problem 1.11.9 If it is known that the space charge capacitance of a backward biased diode with an abrupt p-n junction is C t1 = 20 pF at the biasing voltage V 1 = –5 V and C t2 = 18.5 pF at biasing V 2 = –6 V, determine the value of the capacitance of the diode at V 3 = –8 V.

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341

Solution to Problem 1.11.9 The width of the transition region of the biased abrupt p-n junction is given by the expression (1.3.2.51): / w = w0 ·

1−

V , V0

(1.11.9.1)

where w0 is given by (1.11.8.1) while V is the biasing voltage. The space charge capacitance is given by the expressions (1.3.2.56), so based on the data given in the problem, it is possible to write the following system of two nonlinear equations with two unknowns, V 0 and C 0 : / Ct1 = C0 / 1 − V1 /V0

(1.11.9.2)

/ Ct2 = C0 / 1 − V2 /V0 .

(1.11.9.3)

After solution one gets: V 0 = 0.926 V and C 0 = 50.6 pF. Now, the expression for the space charge capacitance can be written in the following form: / Ct = 50.6 [pF]/ 1 − {V [V ]}/{0.926 [V ]}.

(1.11.9.4)

By substitution V = V 3 , one gets the required space charge capacitance to be: C t3 = 16.3 pF. Problem 1.11.10 In the case of a silicon p-n junction, obtained by diffusion, the distribution of impurity concentration in the vicinity of the metallurgical boundary of the junction can be approximated by a straight line whose slope is a. Determine the distribution of the electric field and potential along the transition region, and the space charge capacitance of this type of p-n junction. Solution to Problem 1.11.10 An approximation of the charge distribution in the depleted area is depicted in Fig. 1.11.10.1 and can be represented by the expression: ρ(x) = q · a · x.

(1.11.10.1)

To find the distribution of the electric field and potential at the junction the Poisson’s equation will be used: d2 V (x) ρ(x) . =− 2 dx ε

(1.11.10.2)

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1.11 Solved Problems

Fig. 1.11.10.1 Charge distribution in the depleted area

After substitution of (1.11.10.1) into (1.11.10.2), the following differential equation is obtained: d2 V (x) q ·a·x =− , 2 dx ε

(1.11.10.3)

Which, after (first) integration, becomes: q ·a 2 dV (x) =− · x + c1 . dx 2·ε

(1.11.10.4)

Since: K (x) = −

dV (x) , dx

(1.11.10.5)

based on (1.11.10.4) it will be: K (x) =

q ·a 2 · x − c1 . 2·ε

(1.11.10.6)

The constant c1 will be determined using the condition that at x = –wp0 the electric field is zero i.e., K (x)|x=−wp0 = 0.

(1.11.10.7)

q ·a 2 · wp0 . 2·ε

(1.11.10.8)

Its value is: c1 =

Based on (1.11.10.6) and (1.11.10.8), the distribution of the electric field in the transition region is given by the expression K (x) =

) q · a( 2 2 x − wp0 . 2·ε

(1.11.10.9)

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343

Fig. 1.11.10.2 Field distribution in the depleted area

This function is graphically depicted in Fig. 1.11.10.2. The peak value of the electric field is obtained for x = 0 and is: K max = −

q ·a 2 · wp0 . 2·ε

(1.11.10.10)

In order to determine the potential distribution along the transition region, it is necessary to integrate the Eq. (1.11.10.4) which, after substituting the expression for the constant c1 , becomes: ) q ·a ( 2 dV (x) 2 =− · x − wp0 . dx 2·ε

(1.11.10.11)

After integration one gets: V (x) = −

) q ·a ( 3 2 · x + c2 . · x /3 − wp0 2·ε

(1.11.10.12)

If as a reference the potential at x = –wp0 is chosen i.e., V (x)|x=−wp0 = 0,

(1.11.10.13)

For the integration constant c2 , from (1.11.10.2), one gets: c2 =

q ·a 3 · wp0 , 2·ε

(1.11.10.14)

so, the final expression for the potential distribution is: V (x) = −

q ·a · 2·ε

(

) x3 2 3 2 − wp0 . x − wp0 3 3

(1.11.10.15)

The potential difference at the points for x = –wp0 and x = wn0 represents the contact potential: V0 = V (x)|x=−wp0 − V (x)|x=wn0 ,

(1.11.10.16)

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1.11 Solved Problems

Fig. 1.11.10.3 Potential distribution in the depleted area

which based on (1.11.10.15) is: q ·a · V0 = − 2·ε

(

) 3 3 wp0 wn0 2 − wp0 wn0 − 2 . 3 3

(1.11.10.17)

The potential distribution along the transition area is shown in Fig. 1.11.10.3. On the other hand, based on the conditions of electroneutrality of the transition region of the p-n junction one may write: {wn0 {wp0 S · q · a · x · dx = S · q · a · x · dx, 0

(1.11.10.18)

0

or 2 2 S · q · a · wn0 /2 = S · q · a · wp0 /2.

(1.11.10.19)

This leads to: wn0 = wp0 .

(1.11.10.20)

The total width of the transition area is: w0 = wn0 + wp0 = 2 · wn0 = 2 · wp0 .

(1.11.10.21)

Based on (1.11.10.21), the contact potential can also be written in the form: V0 = so, the width of the transition area is:

q ·a · w03 , 12 · ε

(1.11.10.22)

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345

/ w0 =

3

12 · ε · V0 , q ·a

(1.11.10.23)

and the space charge capacitance: / S C0 = ε · =S· w0

3

ε2 q · a . 12 · V0

(1.11.10.24)

Problem 1.11.11 For a silicon diode with an abrupt junction, the impurity distribution around the junction can be approximated by a linear function. Calculate the value of the contact potential if the following is known: the space charge capacitance at zero voltage on the p-n junction C 0 = 8.85 pF, the area of the p-n junction S = 10–4 cm2 , and the peak value of the electric field within the transition region |K max | = 12 · 104 V/cm. Solution to Problem 1.11.11 Based on the results of Problem 1.11.10, the space charge capacitance of this type of p-n junction is: C0 = S ·

/ 3

ε2 · q · a/(12 · V0 ),

(1.11.11.1)

and the peak value of the electric field is: K max = −

q ·a · wp2 . 2·ε

(1.11.11.2)

The contact potential at the junction is given by the expression: V0 =

2 q ·a · · wp3 . 3 ε

(1.11.11.3)

By combining (1.11.11.1) and (1.11.11.3) one gets: C0 = ε · S/(2 · wp ),

(1.11.11.4)

wp = 0.5 · (ε · S)/2 · C0 .

(1.11.11.5)

where from:

By substitution of (1.11.11.5) into (1.11.11.2) one gets:

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1.11 Solved Problems

q ·a |K max | = · 8·ε

(

εS C0

)2 ,

(1.11.11.6)

based on which it is possible to write that it is: q·

a = 8 · |K max |[C0 /(ε · S)]2 . ε

(1.11.11.7)

Now, by substitution into (1.11.11.3) one gets the contact potential: V0 = 2 · |K max | · ε ·

S = 0.96V. 3C0

Problem 1.11.12 A silicon p-n junction is characterized by: N D = 1016 cm−3 , N A = 5 · 1018 cm−3 , τp = τn = 1 μs, S = 0.01 cm2 , μnp = 1100 cm2 /Vs, and μpn = 120 cm2 /Vs. Considering that the lengths of both sides of the junction are much larger than the corresponding diffusion lengths of the minority carriers, determine the voltage on the p-n junction if, at room temperature, the current through the junction is I D = 1 mA. Solution to Problem 1.11.12 Based on the Einstein’s relation one gets: ) kT cm2 · μpn = 3.1 , q s ( ) kT · μnp = 28.6 cm2 /s, = q (

Dpn = Dnp

(1.11.12.1) (1.11.12.2)

and from there: /

Dpn τp = 1.8 · 10−3 cm,

(1.11.12.3)

Dnp τn = 5.3 · 10−3 cm,

(1.11.12.4)

pn0 = n 2Si /ND = 2.25 · 104 cm−3 ,

(1.11.12.5)

n p0 = n 2Si /NA = 45 cm−3 .

(1.11.12.6)

L pn = L np =

/

while

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347

This allows for the calculation of the inverse saturation current of this p-n junction: IS = q · S · (Dpn pn0 /L pn + Dnp n p0 /L np ) = 6.3 · 10−14 A.

(1.11.12.7)

On the other hand, the current and voltage at the p-n junction are related by the well-known relation ( VD ) ID = IS e VT − 1 . (1.11.12.8) Solving (1.11.12.8) in terms of V D , we obtain an expression for the voltage at the junction as: VD = VT · ln(1 + ID /IS ) = (kT /q) · ln(1 + ID /IS ) = 0.61 V.

(1.11.12.9)

Problem 1.11.13 It is known that the Zener breakdown in germanium occurs when the electric field reaches the value K max = 2 · 107 V/m. For a germanium diode with an abrupt p-n junction, determine the voltage V z at which Zener breakdown occurs. The following is known: ρp = 0.2 ocm, ρn N A , E 0 = q · V 0 , and supposing that V B >> V 0 , one gets KB =

/

2 · q · (−VB ) · NA /ε.

(1.11.13.2)

By solving for the breakdown voltage, one gets: −VB =

ε · K B2 , 2 · q · NA

Hence, the Zener voltage is: V z = –V B = 6.32 V.

(1.11.13.3)

348

1.11 Solved Problems

Fig. 1.11.14.1 Two diode (isolating) circuit

- VD1 + + VD2 ID1 V

+

ID2 I

Problem 1.11.14 For the diode circuit of Fig. 1.11.14.1 determine the current in the circuit and the voltages on the diodes if the breakdown voltages of both diodes are: (a) V B < –6 V and (b) V B = –5.9 V. The inverse saturation currents of the diodes are I S1 = I S2 = I S = 5 μA, and the voltage of the power source is V = 6 V. Solution to Problem 1.11.14 (a) If we denote by V D1 and V D2 the voltages between the anode and cathode of diodes D1 and D2 , respectively, and by I D1 and I D2 the currents through them, based on Fig. 1.11.14.1, where these quantities are indicated, one may write the Kirchhoff’s equations as:

I = ID1 = −ID2 ,

(1.11.14.1)

V = VD1 − VD2 .

(1.11.14.2)

On the other hand, the voltages and currents of the diodes are related by the current–voltage characteristic, which, when applied to each of the diodes, gives: ( VD1 ) ID1 = IS1 e VT − 1 ,

(1.11.14.3)

( VD2 ) ID2 = IS2 e VT − 1 .

(1.11.14.4)

Considering the fact that the inverse saturation currents of the diodes are equal, based on (1.11.14.1), (1.11.14.3) and (1.11.14.4) it follows that e VD1 / VT − 1 = −e

VD2 VT

+ 1.

(1.11.14.5)

By combining (1.11.14.2) and (1.11.14.5) the circuit analysis problem from Fig. 1.11.14.1 is reduced to solving a system of non-linear equations which, in this case, will be solved approximately. Namely, the biasing of the circuit is performed in such a way that diode D1 is forward biased while D2 is backward biased. This means that the solution of the aforementioned system of non-linear equations will certainly satisfy the following

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349

VD1 > 0, VD2 < 0,

(1.11.14.6)

|VD1 | ≤ V and |VD2 | ≤ V.

(1.11.14.7)

and it is also obvious that it is:

Based on these inequalities and the fact that the breakdown voltage of the diode is |V B | > V, one can conclude that none of the diodes will operate in the breakdown region. As the diode is characterized by high resistance when backward biased and low resistance when forward biased, one can also conclude that the largest part of the voltage of the battery V will develop on the backward biased diode D2 , i.e., |VD2 | >> |VD1 |.

(1.11.14.8)

If we also consider the fact that the voltage equivalent of temperature, at room temperature is VT =

kT0 = 26 mV, q

(1.11.14.9)

Based on (1.11.14.2), (1.11.14.8) and (1.11.14.9) one can claim that: |VD2 | >> VT .

(1.11.14.10)

Since V D2 is negative from (1.11.14.10) one has: eVD2 / VT > V m . The source Rg = 100 o, and the load RL = 9.7 ko resistances are known. Determine the waveform of the voltage at the load (vout ).

358

1.11 Solved Problems

Fig. 1.11.19.2 Equivalent circuit for the case the diode is conducting

Fig. 1.11.19.3 Equivalent circuit for the case the diode is not conducting

Solution to Problem 1.11.19 According to the description of the characteristics of the diode, it can be concluded that in this case the approximation shown in Fig. 1.11.18.4b is applicable. Here the breakdown voltage of the diode is V B 0 it goes into breakdown. Therefore, for vin > 0 the following applies: V A = vin ,

(1.11.21.3)

VC = vin = 2.5 V.

(1.11.21.4)

This region of operation of the diode will remain until vin increases enough so that V D2 > V γ . Having in mind that: VD2 = VA − VC = vin − 2.5 V, D2 will start conducting when: Vγ = vin − 2.5 V, or vin = Vγ + 2.5 V = 3.1 V .

(1.11.21.5)

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365

Fig. 1.11.21.4 Equivalent circuit when D1 is not conducting and D2 is conducting

Fig. 1.11.21.5 Equivalent circuit when both D1 and D2 are conducting

Thus, the area of operation of the circuit is created in which diode D1 is blocked and D2 conducts, which is shown in Fig. 1.11.21.4. The following applies to the output node of this circuit: (vout − V2 )/R2 + (vout + Vγ − vin )/rD = 0,

(1.11.21.6)

from where we get the output voltage: vout =

R2 R2 R1 · vin − · Vγ + · V2 . R1 + R2 R1 + R2 R1 + R2

(1.11.21.7)

With a further increase in the input voltage, the potential V A increases, and when V A = V 1 + V γ , D1 starts conducting. From the circuit of Fig. 1.11.21.4 we have: VA =

) ( R1 R2 · vin + · Vγ + V2 , R1 + R2 R1 + R2

(1.11.21.8)

so that the value of the voltage needed for D1 to start conducting is: vin = (R1 /R2 ) · (V1 − V2 ) + V1 + Vγ = 14.35 V. Above this value both diodes conduct, so the circuit of Fig. 1.11.21.5 is valid. After analysis of this circuit one gets: vout = −VD0 + Vγ + V1 = V1 = 10 V.

(1.11.21.9)

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Fig. 1.11.21.6 The transfer characteristic of the circuit of Fig. 1.11.21.1

D1 C D2 A

Fig. 1.11.22.1 Example two diode circuit for low-frequency time domain analysis

R1

R2

V1

V2

vin

vout

Based on everything previously said, the expression for the transfer characteristic of the circuit from Fig. 1.11.21.1 can be written in the following form:

vout =

⎧ ⎪ ⎨ V2 ,

R2 R1 +R2

⎪ ⎩V , 1

( ) vin − Vγ +

R1 V, R1 +R2 2

for − 15 V ≤ vin ≤ 3.1 V for 3.1 V ≤ vin ≤ 14.35 V (1.11.21.10) for 14.35 V ≤ vin ≤ 15 V

which after substituting the numerical values gives:

vout

⎧ for − 15 V ≤ vin ≤ 3.1 V ⎨ 2.5 V, = 2 · vin /3 + 0.43 V, for 3.1 V ≤ vin ≤ 14.35 V ⎩ 10 V, for 14.35 V ≤ vin ≤ 15 V

(1.11.21.11)

The expression (1.11.21.11) is graphically presented in Fig. 1.11.21.6. Problem 1.11.22 Sketch the waveform of the output voltage if the circuit from Fig. 1.11.22.1 is excited by a (low-frequency) sinusoidal voltage of amplitude 15 V. The diodes are identical with V D0 = 0.6 V, r D = 0, r z = 0, V z = 10 V. It is known: R1 = 10 ko, R2 = 20 ko, V 1 = 3.4 V and V 2 = 10 V.

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Fig. 1.11.22.2 Equivalent circuit when D1 is in breakthrough and D2 is conducting

Solution to Problem 1.11.22 The procedure for solving this Problem will partially coincide with the procedure from the previous ones. Namely, first of all, the transfer characteristic of the circuit, vout = f (vin ), should be determined, and then the waveform of the output voltage is obtained by substituting vin (t). We will start the analysis of this circuit for vin = –15 V. Let us start from the assumption that both diodes are blocked. In this case it is: VA = vout = V2 = 10 V , and VC = V1 = 3.4 V . The diode voltages now are V D1 = vin -V C = –18.4 V and V D2 = vout -V C = 6.6 V. From here it is obvious that the initial assumption is not correct, and that according to these voltages, D1 is in breakdown, while D2 is conducting. The circuit corresponding to this situation is shown in Fig. 1.11.22.2. Based on this circuit, it is possible to write that the output voltage as: vout = vin + Vz + Vγ .

(1.11.22.1)

By increasing vin , the potential V C increases, and with that, the current through D1 decreases: −ID1 =

VC + Vγ − V2 VC − V1 + . R1 R2

(1.11.22.2)

It becomes equal to zero at: VC =

R1 · R1 + R2

(

R2 · V1 + V2 − Vγ R1

) = 5.4 V.

(1.11.22.3)

From this it is concluded that D1 will pass from breakdown into cut-off when the input voltage reaches the value: vin = −Vz + VC = −4.6 V. Therefore, for vin > –4.6 V, D1 is blocked, and D2 is conducting. The corresponding circuit is shown in Fig. 1.11.22.3. It is now possible to write: (vout − V2 )/R2 + (vout − V1 − Vγ )/R1 = 0,

(1.11.22.4)

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Fig. 1.11.22.3 Equivalent circuit when D1 is not conducting and D2 is conducting

Fig. 1.11.22.4 Equivalent circuit when both diodes are conducting

Fig. 1.11.22.5 Equivalent circuit when D2 is not conducting and D1 is conducting

2 2 ·(V1 + Vγ )+ R1R+R · V2 = 6 V and VC = vout − VD0 = 5.4 V . So that: vout = R1R+R 2 2 Since for vin > –4.6 V, D1 is blocked, the assumption was correct. Further increasing the input voltage leads to a situation where both D1 and D2 conduct. This will be met when the input voltage is larger than V C by V γ , i.e., vin = VC + Vγ = 6 V. The equivalent circuit for this case is shown in Fig. 1.11.22.4. The output voltage in this case can be calculated as:

vout = vin − VD0 + Vγ = vin .

(1.11.22.5)

With a further increase of the input voltage, V C will also increase, because: V C = vin –V γ , and therefore the current through resistor R2 will decrease, I R2 = (V 2 –V γ V K )/R2 , and when this current becomes equal to zero D2 will stop conducting. This is fulfilled for V 2 – V γ –V C = 0, i.e., D2 will stop conducting when the input voltage becomes vin = V2 − VD0 + Vγ = V2 = 10 V. The equivalent circuit when D1 conducts and D2 is blocked is shown in Fig. 1.11.22.5. The output voltage in this case is:

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Fig. 1.11.22.6 The transfer characteristic of the circuit of Fig. 1.11.22.1

vout = V2 = 10 V .

(1.11.22.6)

The voltage transfer characteristic of the circuit from Fig. 1.11.22.1 can now be written in the following form: ⎧ vin + Vz + Vγ , ⎪ ⎪ ⎨ R2 · (V + V ) + 1 γ vi = R1 +R2 ⎪ v , ⎪ in ⎩ V2 ,

R1 R1 +R2

for − 15 V ≤ vin ≤ −4.6 V · V2 , for − 4.6 V ≤ vin ≤ 6V for 6 V ≤ vin ≤ 10 V for 10 V ≤ vin ≤ 15 V

which after substitution of the numerical values becomes: ⎧ vin + 10.6 V , for − 15 V ≤ vin ≤ −4.6 V ⎪ ⎪ ⎨ 6 V, for − 4.6 V ≤ vin ≤ 6V vout = ⎪ for 6 V ≤ vin ≤ 10 V vin , ⎪ ⎩ 10 V, for 10 V ≤ vin ≤ 15 V

(1.11.22.7)

(1.11.22.8)

The graphic representation of (1.11.22.8) is given in Fig. 1.11.22.6. Considering (1.11.22.8) it can be said that if the input voltage satisfies −15 V ≤ vin ≤ −4.6 V, the output voltage is: vout = vin + 10.6 V.

(1.11.22.9)

Given that the excitation signal is sinusoidal, the expression (1.11.22.9) represents a sinusoid with an added DC component of 10.6 V. Furthermore, if −4.6 V ≤ vin ≤ 6 V, at the output, is a constant voltage, it does not depend on the input and its value is vout = 6 V. For 6 V ≤ vin ≤ 10 V, the output voltage is equal to the input voltage, so in the time interval in which this condition is met, the output waveform and excitation voltage are equal. Finally, while 10 V ≤ vin ≤ 15, the output voltage will be constant, vout = 10 V, and will not depend on the input.

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Fig. 1.11.22.7 The time domain response (for low frequencies) of the circuit of Fig. 1.11.22.1

Fig. 1.11.23.1 A simple linear regulator circuit

I V

IL

R VL

Iz Dz

RL VL

Taking everything into account Fig. 1.11.22.7 shows the waveforms of the input (blue line) and output voltage (red line). Problem 1.11.23 The Zener diode in the circuit of Fig. 1.11.23.1 is defined by V z = –V B = 50 V when the diode current is in the range I zmin ≤ I z ≤ I zmax , with I zmin = 5 mA and I zmax = 40 mA. The voltage of the power source is V = 200 V. (a) Determine the value of the resistance R that ensures a linear change in load current in the regulation range from I Lmin =0 to I Lmax . What is the value of I Lmax ? (b) If the value calculated in the previous part of the Problem is adopted for R and if the current of the load is I L = 25 mA, within what limits can the voltage of the power source vary while the circuit remains within the regulation range? Solution to Problem 1.11.23 The circuit of Fig. 1.11.23.1 represents one of the simplest voltage regulators circuits. Its task is to ensure a constant voltage on the load, regardless of the changes in the load current, I L , the resistance, RL , and the voltage, V, of the power supply battery. For this purpose, the property of the backward biased diode, which works in the breakdown region, was used. In that case for a large range of current changes, the voltage on the diode is approximately constant. This means a Zener diode is implemented due to its small dynamic resistance in the breakdown region. As the diode is backward biased in the breakdown region, in order to avoid unnecessary work with negative values, the voltage on the Zener diode, V inv = –V D , will be defined as the voltage between the cathode and the anode, and for a positive current direction, we will adopt the direction from the cathode to the anode. Note that the voltage and current directions adopted in this way are opposite of those used when describing ordinary diodes.

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Fig. 1.11.23.2 The diode characteristic used in this case

It is important to note that if the Zener diode’s current, I z , satisfies the inequality: Izmin ≤ Iz ≤ Izmax ,

(1.11.23.1)

then the voltage across the diode is: Vinv = Vz .

(1.11.23.2)

In order for (1.11.23.2) to be valid, i.e., to avoid non-linearity at low currents, the current through the Zener diode must be larger than I zmin (see Fig. 1.11.23.2). The maximum current I zmax is defined by the maximum allowed dissipation on the diode. If (1.11.23.2) is fulfilled, it is said that the circuit is in the range of regulation, that is correct and safe operation of the circuit is ensured. (a) For the circuit of Fig. 1.11.23.1 one can write: I = Iz + IL .

(1.11.23.3)

Considering (1.11.23.2), the current I can also be expressed as: I =

V − Vz . R

(1.11.23.4)

As all quantities on the right-hand side of (1.11.23.4) are constant, provided that the circuit is within the regulation range, the current I is also constant. Based on (1.11.23.3), the sum of the currents I z and I L is also constant. So, an increase in the load current will cause a decrease in the current through the Zener diode, and vice versa. In other words, when the maximum current, I Lmax , flows through the load, the minimum allowed current I zmin must flow through the Zener diode, and if the minimum current, I Lmin , flows through the load, the current through the Zener diode should not exceed I zmax . By providing the previous conditions, the operation of the circuit is ensured within the regulation range. Considering the expression (1.11.23.3), it can be said that:

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I = Iz + IL = Izmin + ILmax = Izmax + ILmin = C te

(1.11.23.5)

Since I Lmin = 0 and I zmax = 40 mA, based on (1.11.23.5) one can find I: I = Izmax + ILmin = 40 mA.

(1.11.23.6)

Based on (1.11.23.4), for the resistance R one gets: R=

V − Vz = 3.75 ko. I

(1.11.23.7)

The maximum current through the load can be determined from (1.11.23.5) as: ILmax = I − Izmin = 35 mA.

(1.11.23.8)

(b) If R = 3.75 ko and I L = 25 mA, the battery voltage V can vary, but in order for the circuit not to go out of the regulation range, the current I must not fall below the minimum, I min , or be larger than the maximum, I max . These two values are defined by the following expressions: Imin = IL + Izmin = 30 mA

(1.11.23.9)

Imax = IL + Izmax = 65 mA.

(1.11.23.10)

and

Based on the previous two expressions, it is not difficult to conclude that the limits in which the battery voltage can vary without disturbing the correct operation of the circuit are given by: Vmin = R · Imin + Vz = 162.5V

(1.11.23.11)

Vmax = R · Imax + Vz = 293.5V.

(1.11.23.12)

and

Problem 1.11.24 Determine the voltage and current of the Zener diode in the circuit shown in Fig. 1.11.24.1, if in the area of backward biasing it can be approximated by the characteristic shown in Fig. 1.11.24.2. Here V z = 9 V and I zmin = 2 μA. The inverse saturation currents of diodes D1 and D2 are I s1 = 1 μA and I s2 = 3 μA. It is known that R = 400 ko and V = 10 V. The breakdown voltages of diodes D1 and D2 are |V B1 | >> V and |V B2 | >> V.

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373

Fig. 1.11.24.1 A Zener diode in a diode circuit

R

D1 V

Dz

D2

Fig. 1.11.24.2 The Zener diode characteristic used in this case

Solution to Problem 1.11.24 For the circuit of Fig. 1.11.24.1 it is obvious that diodes D1 and D2 are backward biased. Considering that: |VB1 | >> V and |VB2 | >> V ,

(1.11.24.1)

there is no possibility of bringing them into breakdown. To represent them the model shown in Fig. 1.11.18.3c is used, where for diode D1 : Is1 = 1 μA,

(1.11.24.2)

Is2 = 2 μA.

(1.11.24.3)

and for D2 :

The area of operation of the diode Dz is unknown, so we will assume that it operates in breakdown. Considering the characteristic from Fig. 1.11.24.2, for its representation we will use the model from Fig. 1.11.18.3b, where: Izmin = 2 μA,

(1.11.24.4)

Vz = 9 V, rz = 0.

(1.11.24.5)

Based on the above and under the assumption that the diode Dz is in breakthrough, the circuit from Fig. 1.11.24.1 can be represented by equivalent one as depicted in

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Fig. 1.11.24.3 Equivalent circuit for the two states of conduction of the Zener diode

Fig. 1.11.24.3, where the switch is in position (1). The voltage on the Zener diode is, depending on the position, (1) V inv = V z , or (2) V inv < V z . The current through the resistor R in the circuit of Fig. 1.11.24.3 amounts:

I =

V − Vz = 2.5 μA. R

(1.11.24.6)

Apart from this, the condition for node (1) must be fulfilled: I + Is1 − Iz − Is2 = 0.

(1.11.24.7)

It follows that the current through the Zener diode is: Iz = I + Is1 − Is2 = 0.5 μA.

(1.11.24.8)

Bearing in mind the characteristic from Fig. 1.11.24.2, it is impossible for the current I z to be less than I zmin , while the voltage on the diode is V inv = V z . This leads to the conclusion that the assumption that the working point is located in the area of breakthrough is incorrect. So, Dz is also backward biased, and for its representation, the model from Fig. 1.11.18.3c with the current I z defined by (1.11.24.4) will be used. The switch from Fig. 1.11.24.3 is now in position (2). Similarly to (1.11.24.7), in this case, the following must be valid: I + Is1 − Is2 − Iz = 0.

(1.11.24.9)

Iz = 2 μA,

(1.11.24.10)

I = Iz + Is2 − Is1 = 4 μA.

(1.11.24.11)

Since:

one has:

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375

R

Fig. 1.11.25.1 A circuit to study the temperature dependence of the diode characteristic

D V

RL

vout

Dz

Fig. 1.11.25.2 Equivalent circuit when D conducts and Dz is in breakdown

Now the voltage across the Zener diode can be calculated as follows: Vinv = V − R · I = 8.4 V.

(1.11.24.12)

Problem 1.11.25 The Zener diode in the circuit of Fig. 1.11.25.1 is defined by V z = –V B = 6.2 V at the temperature T 0 = 300 K. The relative temperature coefficient of V z is:

αz =

1 dVz · 100 = 0.02 %/K. · Vz dT

(1.11.25.1)

The silicon diode D is described with V D0 = 0.7 V and dV γ /dT = dV D0 /dT = – 2 mV/K. Determine approximately the value of the output voltage and its temperature sensitivity at temperature T 0 . Calculate the value vout at T = 350 K. It is known V = 12 V, R = 14 o, and RL = 10 ko. Solution to Problem 1.11.25 It is not difficult to check that the diode D will conduct, and Dz will be in breakdown, so that the circuit from Fig. 1.11.25.1 can be represented by an equivalent circuit given in Fig. 1.11.25.2. As the output voltage of the circuit of Fig. 1.11.25.2 is: vout = Vγ + Vz ,

(1.11.25.2)

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and as is known that at T 0 : Vγ (T0 ) = 0.7 V,

(1.11.25.3)

Vz (T0 ) = 6.2 V,

(1.11.25.4)

Vout (T0 ) = Vγ (T0 ) + Vz (T0 ) = 6.9 V.

(1.11.25.5)

and

One gets:

By differentiating both sides of the expression (1.11.25.2) with respect to T, one gets: dVγ dVz dvout = + . dT dT dT

(1.11.25.6)

Bearing in mind that based on (1.11.25.1) one gets: mV dVz αz · Vz (T0 ) = 1.24 , = dT |T =T0 100 K

(1.11.25.7)

and, in addition, that: dVγ mV , = −2 dT |T =T0 K

(1.11.25.8)

based on (1.11.25.6), the temperature sensitivity of the output voltage at temperature T 0 , is: dVγ dvout dVz mV , = + = −0.76 dT |T =T0 dT |T =T0 dT |T =T0 K

(1.11.25.9)

The output voltage at temperature T = 350 K can be approximately calculated based on the expression: dvout dT |T =350

K

=

vout (T ) − vout (T0 ) , /\T

(1.11.25.10)

where from: vout (T ) = vout (T0 ) +

dvout · /\T . dT |T =T0

(1.11.25.11)

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Fig. 1.11.26.1 A two Zener diodes voltage regulator under low-frequency sinusoidal excitation

Fig. 1.11.26.2 Equivalent circuit when both diodes are in breakthrough

Since: /\T = T − T0 = 50 K,

(1.11.25.12)

it is obtained that the output voltage at T = 350 K is vout (T ) = 6.862 V . Problem 1.11.26 Determine the direct and alternating components of the voltage at the output of the circuit shown in Fig. 1.11.26.1. It is given that V = 15 V, vin = V m ·sin(ωt), V m = 1.5 V, R1 = 30 o, R2 = 18 o, and R3 = 14 o. The Zener diodes in the breakdown region are modled with V z = 10 V i r z = 5 o. Solution to Problem 1.11.26 Bearing in mind that V is sufficiently larger than V z , and that V m > ρC , for the impurity concentrations it is valid

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