*248*
*64*
*9MB*

*English*
*Pages 160
[161]*
*Year 2023*

Table of contents :

Contents

List of Figures

1 Introduction

[DELETE]

1.1 Overview

1.1.1 Chapter Organization

1.2 A Quick Overview of Some ADC Basics

1.2.1 ADC Sampling

1.2.2 ADC Quantization

2 Overview of Pipelined ADCs

[DELETE]

2.1 Searching for the Analog Estimate

2.2 Elements of a Pipelined ADC

2.2.1 The Sub-ADC

2.2.2 The DAC

2.2.3 The Summation Node

2.2.4 The Gain Element

2.3 Cascading Multiple Stages

2.3.1 Combining the Sub-ADC Outputs

2.3.2 Impact of Gain on Input-Referred Noise

2.3.3 Impact of Gain on Power

2.4 Pipelined ADC Architectural Artifacts

2.4.1 Impact of Non-ideal Sub-ADCs

2.4.2 Impact of Non-ideal DACs

2.4.3 Impact of Non-ideal Gain Elements

2.5 Impact on ADC INL

2.5.1 Extracting Nonlinearity Plots

2.5.2 Example Nonlinearity Plots

3 Pipelined ADC Topologies

[DELETE]

3.1 Switched-Capacitor Topologies

3.1.1 Impact of Capacitor Mismatch

3.1.2 MDAC Switch Configurations

3.1.3 Timing Configuration

3.2 Alternative Switched-Capacitor Topologies

3.2.1 Flip-Around Topology

3.2.2 Separate DAC Capacitors

4 Frontend Sampling Networks

[DELETE]

4.1 Frontend Input Buffer

4.1.1 Design Factors

4.2 Input Buffer Implementations

4.2.1 The Emitter Follower

4.2.2 The Source Follower

4.2.3 Alternative Input Buffer Implementations

4.3 Sampling Switches

4.3.1 Track Phase Distortion

4.4 Sub-ADC Sampling Network

4.4.1 Without a Frontend Track-and-Hold

4.4.2 Impact of Bandwidth Mismatch

4.5 A Buffer-Less Frontend

4.5.1 Introducing a Reset Phase

5 Comparator Design

[DELETE]

5.1 Comparator Metastability

5.1.1 Metastability Rate

5.1.2 First-Order Comparator Model

5.2 Calculating the ADC Error Rate

5.2.1 Impact of Noise on Code Error Rate

5.2.2 ADC Error Rate Analysis

5.2.3 Simulating and Measuring Error Rates

5.3 Impact of Impulse Sensitivity Function

5.3.1 Comparator Impulse Sensitivity Function

5.3.2 Simulating the Impulse Sensitivity Function

5.3.3 Mapping the ISF to ADC Performance

6 Reference Generation

[DELETE]

6.1 Reference Amplifier Options

6.1.1 Reference Error Modeling

6.2 Signal-Dependent Response

6.2.1 Examples of Signal-Dependent Charge

6.2.2 Generalized Charge Analysis

6.2.3 Mitigation Techniques

6.3 Impact of Reference Noise

6.3.1 Examples of Signal-Dependent Noise

6.3.2 Generalized Noise Analysis

7 Correcting Pipelined ADC Errors

7.1 Error Correction

7.1.1 DAC Error Correction

7.1.2 Gain Error Correction

7.2 Error Estimation

7.2.1 Intuition Behind Error Estimation

7.2.2 Estimation Example

7.2.3 Matrix-Based Estimation

Contents

List of Figures

1 Introduction

[DELETE]

1.1 Overview

1.1.1 Chapter Organization

1.2 A Quick Overview of Some ADC Basics

1.2.1 ADC Sampling

1.2.2 ADC Quantization

2 Overview of Pipelined ADCs

[DELETE]

2.1 Searching for the Analog Estimate

2.2 Elements of a Pipelined ADC

2.2.1 The Sub-ADC

2.2.2 The DAC

2.2.3 The Summation Node

2.2.4 The Gain Element

2.3 Cascading Multiple Stages

2.3.1 Combining the Sub-ADC Outputs

2.3.2 Impact of Gain on Input-Referred Noise

2.3.3 Impact of Gain on Power

2.4 Pipelined ADC Architectural Artifacts

2.4.1 Impact of Non-ideal Sub-ADCs

2.4.2 Impact of Non-ideal DACs

2.4.3 Impact of Non-ideal Gain Elements

2.5 Impact on ADC INL

2.5.1 Extracting Nonlinearity Plots

2.5.2 Example Nonlinearity Plots

3 Pipelined ADC Topologies

[DELETE]

3.1 Switched-Capacitor Topologies

3.1.1 Impact of Capacitor Mismatch

3.1.2 MDAC Switch Configurations

3.1.3 Timing Configuration

3.2 Alternative Switched-Capacitor Topologies

3.2.1 Flip-Around Topology

3.2.2 Separate DAC Capacitors

4 Frontend Sampling Networks

[DELETE]

4.1 Frontend Input Buffer

4.1.1 Design Factors

4.2 Input Buffer Implementations

4.2.1 The Emitter Follower

4.2.2 The Source Follower

4.2.3 Alternative Input Buffer Implementations

4.3 Sampling Switches

4.3.1 Track Phase Distortion

4.4 Sub-ADC Sampling Network

4.4.1 Without a Frontend Track-and-Hold

4.4.2 Impact of Bandwidth Mismatch

4.5 A Buffer-Less Frontend

4.5.1 Introducing a Reset Phase

5 Comparator Design

[DELETE]

5.1 Comparator Metastability

5.1.1 Metastability Rate

5.1.2 First-Order Comparator Model

5.2 Calculating the ADC Error Rate

5.2.1 Impact of Noise on Code Error Rate

5.2.2 ADC Error Rate Analysis

5.2.3 Simulating and Measuring Error Rates

5.3 Impact of Impulse Sensitivity Function

5.3.1 Comparator Impulse Sensitivity Function

5.3.2 Simulating the Impulse Sensitivity Function

5.3.3 Mapping the ISF to ADC Performance

6 Reference Generation

[DELETE]

6.1 Reference Amplifier Options

6.1.1 Reference Error Modeling

6.2 Signal-Dependent Response

6.2.1 Examples of Signal-Dependent Charge

6.2.2 Generalized Charge Analysis

6.2.3 Mitigation Techniques

6.3 Impact of Reference Noise

6.3.1 Examples of Signal-Dependent Noise

6.3.2 Generalized Noise Analysis

7 Correcting Pipelined ADC Errors

7.1 Error Correction

7.1.1 DAC Error Correction

7.1.2 Gain Error Correction

7.2 Error Estimation

7.2.1 Intuition Behind Error Estimation

7.2.2 Estimation Example

7.2.3 Matrix-Based Estimation

- Author / Uploaded
- Manar El-Chammas

- Similar Topics
- Technique

Synthesis Lectures on Engineering, Science, and Technology

Manar El-Chammas

High-Performance and High-Speed Pipelined ADCs

Synthesis Lectures on Engineering, Science, and Technology

The focus of this series is general topics, and applications about, and for, engineers and scientists on a wide array of applications, methods and advances. Most titles cover subjects such as professional development, education, and study skills, as well as basic introductory undergraduate material and other topics appropriate for a broader and less technical audience.

Manar El-Chammas

High-Performance and High-Speed Pipelined ADCs

Manar El-Chammas Austin, TX, USA

ISSN 2690-0300 ISSN 2690-0327 (electronic) Synthesis Lectures on Engineering, Science, and Technology ISBN 978-3-031-29699-4 ISBN 978-3-031-29700-7 (eBook) https://doi.org/10.1007/978-3-031-29700-7 © The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature Switzerland AG 2023 This work is subject to copyright. All rights are solely and exclusively licensed by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. The publisher, the authors, and the editors are safe to assume that the advice and information in this book are believed to be true and accurate at the date of publication. Neither the publisher nor the authors or the editors give a warranty, expressed or implied, with respect to the material contained herein or for any errors or omissions that may have been made. The publisher remains neutral with regard to jurisdictional claims in published maps and institutional affiliations. This Springer imprint is published by the registered company Springer Nature Switzerland AG The registered company address is: Gewerbestrasse 11, 6330 Cham, Switzerland

To my family, and its newest addition, Nadine.

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.1 Chapter Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 A Quick Overview of Some ADC Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.1 ADC Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.2 ADC Quantization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1 1 2 3 4 6 8

2 Overview of Pipelined ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Searching for the Analog Estimate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Elements of a Pipelined ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1 The Sub-ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.2 The DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.3 The Summation Node . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.4 The Gain Element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Cascading Multiple Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.1 Combining the Sub-ADC Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.2 Impact of Gain on Input-Referred Noise . . . . . . . . . . . . . . . . . . . . . . 2.3.3 Impact of Gain on Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Pipelined ADC Architectural Artifacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.1 Impact of Non-ideal Sub-ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.2 Impact of Non-ideal DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.3 Impact of Non-ideal Gain Elements . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 Impact on ADC INL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.1 Extracting Nonlinearity Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.2 Example Nonlinearity Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11 12 14 15 15 17 17 18 19 23 23 26 27 30 31 34 34 36 37

3 Pipelined ADC Topologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Switched-Capacitor Topologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.1 Impact of Capacitor Mismatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

39 39 43 vii

viii

Contents

3.1.2 MDAC Switch Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.3 Timing Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Alternative Switched-Capacitor Topologies . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1 Flip-Around Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 Separate DAC Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

48 49 51 52 53 54

4 Frontend Sampling Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Frontend Input Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.1 Design Factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Input Buffer Implementations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.1 The Emitter Follower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.2 The Source Follower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.3 Alternative Input Buffer Implementations . . . . . . . . . . . . . . . . . . . . . 4.3 Sampling Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.1 Track Phase Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 Sub-ADC Sampling Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.1 Without a Frontend Track-and-Hold . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.2 Impact of Bandwidth Mismatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 A Buffer-Less Frontend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.1 Introducing a Reset Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

57 57 58 67 68 73 76 77 77 79 81 83 85 88 89

5 Comparator Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 Comparator Metastability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.1 Metastability Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.2 First-Order Comparator Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Calculating the ADC Error Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.1 Impact of Noise on Code Error Rate . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.2 ADC Error Rate Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.3 Simulating and Measuring Error Rates . . . . . . . . . . . . . . . . . . . . . . . 5.3 Impact of Impulse Sensitivity Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.1 Comparator Impulse Sensitivity Function . . . . . . . . . . . . . . . . . . . . . 5.3.2 Simulating the Impulse Sensitivity Function . . . . . . . . . . . . . . . . . . . 5.3.3 Mapping the ISF to ADC Performance . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

91 92 92 93 95 97 100 106 111 112 113 116 119

6 Reference Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 Reference Amplifier Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.1 Reference Error Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 Signal-Dependent Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.1 Examples of Signal-Dependent Charge . . . . . . . . . . . . . . . . . . . . . . . 6.2.2 Generalized Charge Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

123 124 124 127 129 130

Contents

ix

6.2.3 Mitigation Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 Impact of Reference Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.1 Examples of Signal-Dependent Noise . . . . . . . . . . . . . . . . . . . . . . . . 6.3.2 Generalized Noise Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

131 135 135 135 136

7 Correcting Pipelined ADC Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 Error Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.1 DAC Error Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.2 Gain Error Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 Error Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.1 Intuition Behind Error Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.2 Estimation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.3 Matrix-Based Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

139 139 140 141 144 144 146 148 150

List of Figures

Fig. Fig. Fig. Fig. Fig.

1.1 1.2 1.3 1.4 1.5

Fig. Fig. Fig. Fig. Fig.

1.6 2.1 2.2 2.3 2.4

Fig. Fig. Fig. Fig.

2.5 2.6 2.7 2.8

Fig. 2.9 Fig. 2.10 Fig. 2.11 Fig. 2.12 Fig. 2.13 Fig. 2.14 Fig. 2.15

Target speed-SNR design space for pipelined ADCs . . . . . . . . . . . . . . . Sampling and quantization operations within an ADC . . . . . . . . . . . . . Input signal with a uniform sampling and b quantization . . . . . . . . . . . Nyquist zones across input frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . Quantization error plotted a versus time and b versus the input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Probability distribution of quantization error . . . . . . . . . . . . . . . . . . . . . Pipelined ADC search analogy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Systolic array representation of pipelined ADCs . . . . . . . . . . . . . . . . . . Primary building blocks of a pipelined ADC stage . . . . . . . . . . . . . . . . a Sub-ADC quantization example and b DAC output as a function of sub-ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer function for sub-ADC with nine levels . . . . . . . . . . . . . . . . . . . DAC transfer function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal at a summation node and b output of gain element . . . . . . . . . . Backend ADC that a directly quantizes the summation node output or b the amplified output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cascaded stages in pipelined ADC, with digital outputs . . . . . . . . . . . . Two methods to generate the ADC output by combining the digital outputs of the stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sub-ADC digital output combination with 1-bit overlap between stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power as a function of inter-stage gain . . . . . . . . . . . . . . . . . . . . . . . . . . Optimal scaling factors as a function of inter-stage gain with a no bound on scaling and b a bound of 16 . . . . . . . . . . . . . . . . . . . . . . Sub-ADC transfer function with a ideal thresholds and b threshold mismatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stage residue as a function of sub-ADC a ideal thresholds, b threshold mismatch, and c random thresholds . . . . . . . . . . . . . . . . . . .

2 3 4 5 7 7 12 13 14 16 16 17 18 19 19 22 22 25 26 27 28

xi

xii

List of Figures

Fig. 2.16 Fig. 2.17 Fig. 2.18 Fig. 2.19 Fig. 2.20 Fig. 2.21 Fig. 2.22 Fig. 2.23 Fig. 3.1 Fig. 3.2 Fig. 3.3 Fig. 3.4 Fig. 3.5 Fig. 3.6 Fig. 3.7

Fig. 3.8 Fig. 3.9

Fig. Fig. Fig. Fig. Fig. Fig.

3.10 3.11 3.12 4.1 4.2 4.3

Fig. 4.4 Fig. 4.5 Fig. 4.6

Stage residue as a function of sub-ADC thresholds (both ideal and non-ideal), with redundancy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DAC error plot with a non-linear errors and b linear gain error . . . . . Stage residue as a function of DAC with a non-linear errors and b a linear gain error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stage residue as a function of gain errors. a With linear gain mismatch and b with third order nonlinearity . . . . . . . . . . . . . . . . . . . . . Example pipelined ADC for nonlinearity analysis . . . . . . . . . . . . . . . . . FFT of a an ideal ADC b an ADC with gain errors and c an ADC with DAC errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a Error plot for ideal ADC and b error plot for an ADC with DAC nonlinearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NL error plot for an ADC with a a linear DAC gain error and b a stage output gain error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switched-capacitor MDAC topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switched-capacitor topology in a track phase and b redistribution phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Residue plot with G = 4 and N = 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . Impact of gain error on a SNDR and b SFDR . . . . . . . . . . . . . . . . . . . . Mismatch-related impact of capacitor and stage gain on a 14b ADC. a Gain error and b estimated SNDR with 3σ gain error . . . . . . MDAC sampling switch on-resistance during track phase . . . . . . . . . . . Resetting the feedback capacitors during track phase through a the amplifier and b explicit voltages. (Ron represents the sampling switch during the track phase) . . . . . . . . . . . . . . . . . . . . . . Alternating track and redistribution phases in cascaded stages . . . . . . . a Timing relationship of digital outputs of each stage, as a function of the ADC input signal and b alignment of stage outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MDAC with flip-around configuration. Phases not illustrated . . . . . . . . Residue plot for flip-around topology . . . . . . . . . . . . . . . . . . . . . . . . . . . MDAC with separate DAC capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . Simplified frontend sampling network . . . . . . . . . . . . . . . . . . . . . . . . . . . Input buffer impedance during track mode . . . . . . . . . . . . . . . . . . . . . . . a Buffer transfer function and b Best-fit mean square error (normalized to the signal power) for an input signal spanning 1 GHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sampling network a track phase and b hold phase . . . . . . . . . . . . . . . . Required current per unit pF sampling capacitor for target slew rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Capacitance between input and output of input buffer . . . . . . . . . . . . . .

29 31 32 33 34 35 36 37 40 41 42 45 47 49

50 50

51 52 53 54 58 59

60 61 62 62

List of Figures

Fig. 4.7 Fig. 4.8 Fig. 4.9 Fig. 4.10

Fig. 4.11 Fig. 4.12 Fig. 4.13

Fig. 4.14

Fig. 4.15 Fig. 4.16 Fig. 4.17 Fig. 4.18 Fig. 4.19 Fig. 4.20 Fig. 4.21 Fig. 4.22

Fig. 4.23 Fig. 4.24 Fig. 4.25 Fig. 4.26 Fig. 4.27 Fig. 4.28

Transition from hold phase to track phase. a Input and output waveforms and b change in output voltage . . . . . . . . . . . . . . . . . . . . . . . a Source impedance impulse response and b impact on input waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MDAC configuration during a track phase and b hold phase . . . . . . . . Impact of kickback on SFDR with conventional MDAC configuration, as a function of increasing track time. a Eye diagram of kickback response and b SFDR as a function of track time. In this example, a 64-point sine wave was used . . . . . . . . . . . . . . Attenuated kickback with a one input buffer and b two input buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Emitter follower input buffer with ideal bias current, driving a capacitor load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Emitter follower with different current mirrors. a Resistor degenerated NPN current mirror b NMOS current mirror cascoded with an NPN transistor or c with an NMOS transistor . . . . . Impact of frequency on emitter follower due to current through a 1pF sampling capacitor and an FSR = 2, for different bias currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using a replica capacitor to reduce signal-dependent current . . . . . . . . Source follower input buffer with ideal bias current . . . . . . . . . . . . . . . Addressing body bias modulation with a direction connection of body to source and b using a replica buffer to drive the body . . . . . Options to reduce VDS modulation in source followers . . . . . . . . . . . . . Abo’s bootstrap circuit for highly linear sampling switches . . . . . . . . . a Precharging the bootstrap capacitor during hold phase and b tracking the input via the bootstrap capacitor during track phase . . . Mitigating VT modulation by bootstrapping VS B . . . . . . . . . . . . . . . . . . Impact of matching on first stage performance as a function of (a), (b) a track-and-hold and (c), (d) no track-and-hold, for different input frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Impact of timing error as a function of frequency for a a low input frequency and b a higher input frequency . . . . . . . . . . . . . . . . . . . Maximum voltage error due to phase error and input frequency with a 3-bit sub-ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Impact of voltage error on a the output residue and b the available margin for static offset . . . . . . . . . . . . . . . . . . . . . . . . . . Replica sub-ADC path with delay trim for phase error . . . . . . . . . . . . . Impact of bandwidth mismatch on sub-ADC voltage error, with f 3d B = 4 GHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Off-chip network driving sampling circuit without input buffer . . . . . .

xiii

63 64 65

66 67 68

70

72 73 74 75 76 78 78 79

80 81 82 83 84 85 86

xiv

List of Figures

Fig. 4.29 Fig. 4.30

Fig. 4.31 Fig. 5.1

Fig. Fig. Fig. Fig.

5.2 5.3 5.4 5.5

Fig. 5.6 Fig. 5.7 Fig. 5.8 Fig. 5.9 Fig. 5.10 Fig. 5.11 Fig. 5.12 Fig. 5.13 Fig. 5.14

Fig. Fig. Fig. Fig. Fig. Fig.

5.15 5.16 5.17 5.18 5.19 5.20

Fig. 5.21

Simplified kickback model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Kickback decay with CS = 500fF and RS = 50, for different bandwidths. Dashed vertical lines mark track times corresponding to 2.5 and 1.25 GSPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset switch added to sampling network, with timing diagram . . . . . . Timing relationship resulting in potential metastability with a a simple metastability test structure and b a corresponding timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Linearized cross-coupled comparator model . . . . . . . . . . . . . . . . . . . . . . Impact of increasing TR on comparator metastability rate . . . . . . . . . . Digital and analog paths in pipelined ADC stage . . . . . . . . . . . . . . . . . . Impact of comparator regeneration on residue amplifier output, where half of the sampling period Ts is available for residue generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC output with noise. a Full ADC output and b zoomed in output with best-fit line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a Code error histogram and b cumulative probability that absolute value of code error ≥ CE . . . . . . . . . . . . . . . . . . . . . . . . . . ADC error probability due to noise with estimated sigma . . . . . . . . . . Comparator thresholds and metastable regions . . . . . . . . . . . . . . . . . . . . Example ADC code error rate versus sampling period for different τ A and τC values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Impact of noise and metastability on error rate . . . . . . . . . . . . . . . . . . . Clocking the sub-ADC of later stages earlier to improve metastability rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Simulating comparator time constant by sweeping the input voltage for a no systematic offset and b some systematic offset . . . . . Simulating comparator time constant (with τC = 4ps) using the output derivative. a Example output b Output normalized with derivative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Improving error rate with an additional analog delay . . . . . . . . . . . . . . Clocking the comparators before sampling has finished . . . . . . . . . . . . Input impulse much a earlier or b later than the clock rising edge . . . Impact of varying pulse amplitude on comparator output delay . . . . . . Simulation setup for comparator impulse sensitivity function . . . . . . . . a Comparator ISF with different clock risetimes and b comparator ISF with different transistor sizes . . . . . . . . . . . . . . . . . . . Comparator ISF a with limited frontend bandwidth and b with a comparator preamplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

86

87 88

93 94 95 96

97 98 99 99 102 103 105 106 108

109 110 111 112 113 114 115 116

List of Figures

Fig. 5.22

Fig. 5.23

Fig. 6.1 Fig. 6.2 Fig. 6.3 Fig. 6.4

Fig. 6.5 Fig. 6.6 Fig. 6.7 Fig. 6.8 Fig. 6.9 Fig. 6.10 Fig. 7.1 Fig. 7.2 Fig. 7.3

Fig. 7.4

Fig. 7.5 Fig. 7.6

a ISF of sub-ADC path and MDAC sampling path, where both operate with the same clock and b impact of ISF on output residue with same clock for sub-ADC and sampling path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Impact of ISF on output residue with a tunable clock delay, with a the ISFs of Fig. 5.22, b with bandwidth mismatch, and c with a preamplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Simplified reference amplifier configuration with battery and sampling capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Relationship between time constants and size of battery capacitor, for a slow reference amplifier topology . . . . . . . . . . . . . . . . . Relationship between output impedance and size of battery capacitor size, for a fast reference amplifier . . . . . . . . . . . . . . . . . . . . . . a Capacitor configuration during track phase. b Capacitor configuration during redistribution phase, for a given sub-ADC output. Feedback capacitors not shown . . . . . . . . . . . . . . . . . . . . . . . . . . Signal-dependent charge provided by a reference voltage in an MDAC with N = 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reference routing to all stages with inductive characteristics . . . . . . . . Charge equalization with replica input sampling. Single-ended representation. a Track phase and b Redistribution phase . . . . . . . . . . . Charge equalization with dummy capacitors . . . . . . . . . . . . . . . . . . . . . . Splitting reference routing between stages using a replica reference amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Impact of reference noise for different values of N . . . . . . . . . . . . . . . . Digital correction of first stage DAC errors . . . . . . . . . . . . . . . . . . . . . . Digital correction of gain errors. a Combination of backend outputs. b Scaling backend output. c Scaling first stage output . . . . . . a ADC output with gain error. b ADC output with gain correction. Correction 1 multiplies the backend output with a correction factor as in Fig.7.2b and Correction 2 multiplies the first stage output with a correction factor as in Fig. 7.2c . . . . . . . . . . . . . . . . . . . . a DAC correction example, with segments corresponding to different sub-ADC outputs. Arrows indicate direction of correction, and segment mean illustrated with the dot. b Nonlinearity plot after DAC error correction . . . . . . . . . . . . . . . . . . . . a Sub-ADC raw bits b Full ADC output with one-to-one mapping of LSBs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nonlinearity plot with DAC errors in the first two stages. a ADC error plot and b Backend ADC error plot . . . . . . . . . . . . . . . . . . . . . . . .

xv

117

118 124 126 127

128 131 131 133 134 134 136 141 142

143

145 146 147

xvi

Fig. 7.7

Fig. 7.8 Fig. 7.9

List of Figures

Nonlinearity plot with corrected DAC errors in the first two stages. a Correction only in the first stage and b in both the first and second stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Estimating gain error with signal-dependent offsets . . . . . . . . . . . . . . . . a Error plot with DAC and gain errors and b error plot after correction with matrix model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

148 149 150

1

Introduction

Analog-to-digital converters (ADCs) are instrumental components in electronic systems. They serve as one of the interfaces between the analog world and the digital signal processing (DSP) algorithms that interpret the world. Almost every system we interact with requires such an interface. Used in applications ranging from communication systems to ultrasound machines, from security cameras to internet-of-things sensors, ADCs play a critical role in the complete signal chain, and are a ubiquitous element in our lives. The choice of ADC architecture depends on the target application and its specifications, and this book discusses one of those architectures—that of the pipelined ADC.

1.1

Overview

This book focuses solely on the pipelined ADC, an elegant architecture that addresses a large number of application needs. It is written for both the experienced engineer who would like to learn more about certain subtleties of pipelined ADCs, and for new engineers who would like to have a more in-depth perspective of what a pipelined ADC design entails. This book does not cover all aspects of pipelined ADCs. There is rich research history on various topics in pipelined ADC design (such as on amplifier topologies, calibration algorithms, and noise analysis). As a result, I decided to not include some of these topics in this book (references are provided when these are mentioned). Even though these are all crucial elements of pipelined ADC design, there are other aspects that are much less frequently discussed and that also impact performance. These “second-order” considerations are the primary focus of this book. © The Author(s), under exclusive license to Springer Nature Switzerland AG 2023 M. El-Chammas, High-Performance and High-Speed Pipelined ADCs, Synthesis Lectures on Engineering, Science, and Technology, https://doi.org/10.1007/978-3-031-29700-7_1

1

2

1 Introduction

Fig. 1.1 Target speed-SNR design space for pipelined ADCs

I also assume certain knowledge on your behalf. For example, I assume you are familiar with kT /C noise and its analysis, are comfortable with fast Fourier transforms (FFT), understand circuit bandwidth and time constants, and know how to calculate distortion metrics, to name just a few of my assumptions. There are numerous resources online that can aid with these topics. Pipelined ADCs have been designed for a large range of sample rates and resolutions, and different design considerations apply to different regions of operation. In this book, I primarily focus on high-performance and high-speed pipelined ADCs [1]. The exact definition of these two does depend on the process node being used, but with a large brush, it covers the space outlined in Fig. 1.1. Specifically, this book focuses on sample rates from a few hundred MSPS (Megasamples per second) to several GSPS (Gigasamples per second), and an SNR of between 55–70 dB. Although time-interleaved ADCs [2, 3] are a powerful (and sometimes necessary) technique to extend the sampling rate and achieve a more optimal PPA (power, performance, area) metric, this book focuses on a single-channel ADC. There is an elegance to pipelined ADCs that is sometimes lost in the day-to-day design effort. Their intrinsic regular structures, as discussed in Chap. 2, impacts both systemlevel and circuit-level aspects. Architecture and circuit level decisions must be made in tandem, requiring both an analytic and intuitive understanding of the different moving parts in pipelined ADCs. My hope is that this book helps present and analyze some of this elegance.

1.1.1

Chapter Organization

The rest of this chapter covers some initial basics of ADCs, to set the stage for the rest of the book. Chapter 2 presents an overview of the pipelined ADC, followed by more specific topologies in Chap. 3. The flow in the rest of the book follows the signal flow in pipelined ADCs. The frontend sampling networks of pipelined ADCs are covered in Chap. 4. In Chap. 5, the comparator and its impact on high-speed performance is analyzed, and the

1.2

A Quick Overview of Some ADC Basics

3

reference amplifier is discussed in Chap. 6. Finally, although calibration is not specifically discussed in this book, Chap. 7 touches on mismatch correction and estimation with trimming algorithms that can be implemented during production test.

1.2

A Quick Overview of Some ADC Basics

ADCs combine sampling and quantization operations in order to convert a continuous-time analog input signal into a discrete-time digital output signal, as in Fig. 1.2. Conceptually, these operations are commutative, in that the final result is the same regardless of whether sampling or quantization comes first. However, practical constraints typically lead to sampling being the initial operation, as in Fig. 1.2. Several assumptions are often made in the analysis of both the sampling and quantization operations. For example, sampling is assumed to be a periodic operation with a uniform sampling period TS (as in Fig. 1.3a) and sampling rate FS = 1/TS , and thus deviations from this uniform sampling period are not desired (such as those resulting from random variations due to jitter [4] or more systematic variations due to clock modulation [3]). This assumption, however, is not necessarily true. Non-periodic sampling systems exist [5], and can still convert the appropriate analog information into a digital data stream. Likewise, signal quantization is also assumed to be uniformly distributed (as in Fig. 1.3b), which is also not a necessary assumption. Quantization introduces a signal-dependent error into the signal chain, and the optimal quantization function minimizes the statistical energy of this error based on the input signal statistics [6, 7]. Since this information is not necessarily known a priori, it is easier to impose uniform quantization (some notable exceptions to this are logarithmic ADCs [8]). These simplifications are not only driven by circuit implementations, but also by digital signal processing (DSP) requirements. Most DSP algorithms operate under the assumptions of periodic sampling and uniform quantization. Instead of transforming non-uniform quantization and non-uniform sampling into a synchronous DSP-friendly signal stream, it is simpler for all to assume both are uniform (even if it is less optimal in specific applications).

Fig. 1.2 Sampling and quantization operations within an ADC

4

1 Introduction

Fig. 1.3 Input signal with a uniform sampling and b quantization

Diverging from these norms requires a system level design of both the analog frontend and the algorithms of the digital backend [9, 10]. The rest of this chapter touches on both the sampling and quantization operations in more detail.

1.2.1

ADC Sampling

The ADC input signal is represented by x(t), as in Fig. 1.2. With a sampling period of TS , the sampled analog signal is xs [n] = x(nTS ). An artifact of this is aliasing, which results in a non-injective mapping. Unless the signal information is limited to the Nyquist bandwidth FBW < F2S [11–13], it is impossible to invert the sampling operation after the fact, unless certain additional conditions are met [14]. This bandwidth constraint can be generalized into “Nyquist zones”, as in Fig. 1.4, if the signal of interest is not in [0, F2S ). If a signal is in the mth Nyquist zone, then its frequency content is in [(m − 1) F2S , m F2S ), where m is an integer. Even though this does alias post-

1.2

A Quick Overview of Some ADC Basics

5

Fig. 1.4 Nyquist zones across input frequency

sampling, the sampling operation can be inverted [12], a property that sub-sampling relies on. Aliasing is often explained with the example of a sinusoidal function. For example, if x(t) = sin(ω0 t), then the sampled output is xs [n] = sin(ω0 nTS ). The sampled output is identical if ω0 = ω1 or if ω0 = ω1 + 2π TS (these are two examples from an infinite space). Although aliasing can be discussed in the time-domain, as with this sinusoidal example, it is more interesting in the frequency domain. A sampling operation can be modeled using the Dirac comb function [15], with δ(t − nTS ) = x(nTS )δ(t − nTS ) (1.1) xs (t) = x(t) n

n

such that xs [n] = xs (nTs ) = x(nTs )

(1.2)

Since the Fourier transform of a Dirac comb is also a Dirac comb [15], and since time-domain multiplication is equivalent to frequency domain convolution, the frequency response of the sampled signal in Eq. 1.1 is X s ( f ) = F {xs (t)} = X ( f − n FS ) (1.3) n

where FS = 1/TS and X ( f ) = F {x(t)} (the Fourier transform of x(t)). In Eq. 1.3, replicas of the original signal are shifted along the frequency axis with periodicity of FS . The discrete-time Fourier transform equivalent of Eq. 1.3 is X s () = X ( − n FS ) (1.4) n

where ∈ [−FS /2, FS /2]. Thus, if the original signal crosses multiple Nyquist zones, it will fold into the baseband.

6

1 Introduction

The impact of aliasing must be managed as part of the specification process. For example, if the signal content is wideband and spans up to 1 GHz, then the ADC sample rate will be larger than 2GSPS (the exact number can depend on other factors such as the anti-aliasing filter). The signal can also have a smaller bandwidth (for example, 100 MHz), but its signal images due to harmonics (such as the second and third harmonic) can alias into the signal band if the sampling rate is not chosen correctly.1 As systems evolve to require more signal information, the increasing signal bandwidth results in increasing sampling rates.

1.2.2

ADC Quantization

With an input signal of x(t), the quantized output is y(t) = f (x(t)), where f () is the quantization operator. This is a deterministic function, and can be written as y(t) = f (x(t)) = x(t) + eq (x(t))

(1.5)

where eq (x) is the signal-dependent quantization error. Quantization is a deterministic error (not a random one2 ), although it is commonly analyzed via statistical analysis [16]. The quantization operation reduces the accuracy of the output signal (compared to the original input) by rounding (or, mapping) the input signal x(t) to the nearest quantization level. This effectively estimates the input signal with a coarse value, as in Fig. 1.3b. The quantization error of the signal in Fig. 1.3 is plotted in Fig. 1.5 (note the normalized y-axis in units of the LSB, or least-significant bit) in two different ways. Figure 1.5a plots the error versus time, where a deterministic signature is evident. However, this is not a qualitatively useful way of plotting quantization error. Figure 1.5b plots the error versus the input signal. Here, a clear pattern is also evident. Each segment corresponds to a quantized value, and the number of segments correspond to the number of quantization levels. Plotting the error versus input signal is extremely useful in the design, analysis, and debug of ADCs, and will be visited in later chapters in the context of pipelined ADCs. As in Fig. 1.5, the error of an ideal uniform quantization function is bounded to [−0.5, 0.5) LSB. If the input signal surpasses the ADC full-scale range range, the quantization error becomes unbounded. The impact of quantization error on the overall ADC performance can be quantified with the first-order probability density of eq , if x(t) is assumed to be randomly distributed [16]. With a step of between each quantization level, the quantization error of an ideal uniform quantizer is bounded to [−/2, /2), as in Fig. 1.6. With p(eq ) as in Fig. 1.6, the mean-square error (MSE) of eq (with μ = 0) is

1 Frequency planning is used to ensure that this does not happen. 2 Although commonly referred to as quantization “noise”, this is a misnomer. In ADC analysis, it

is important to differentiate between random and deterministic artifacts since they have different implications. In this book, I will be exclusively referring to this as quantization error.

1.2

A Quick Overview of Some ADC Basics

7

Fig. 1.5 Quantization error plotted a versus time and b versus the input signal Fig. 1.6 Probability distribution of quantization error

qmse = E (eq − μ)

2

=

/2

−/2

eq2 p(eq )deq =

2 12

(1.6)

Equation 1.6 relates to the ADC resolution. For example, an ADC with B bits and a full-scale range of F S R has 2 B levels and an LSB size of = F2SBR . The MSE is qmse =

F S R2 12 · 22B

(1.7)

1 Introduction

8

As the ADC resolution increases, the quantization error decreases. The signal-to-quantization ratio (SQR), assuming an input sinusoidal signal with amplitude F 2S R is

SQR =

PS = qmse

FSR 2

2

2 F S R2 12·22B

= 22B ·

3 2

(1.8)

In addition to quantization error, other errors can also get lumped into the denominator (including other distortion elements and random errors such as noise), resulting in the signalto-noise-and-distortion ratio (SNDR). Be f f , the ADC’s effective number of bits (ENOB), can be obtained from the SNDR with 2Be f f 2 ·3 (1.9) ≈ 6.02Be f f + 1.76 S N D Rd B = 10 log10 2 This metric forms a useful basis for comparison between different ADCs, even though it does not provide the same design insight that the quantization error plot (Fig. 1.5b) does. The target ENOB impacts the choice of ADC resolution. Typically, the quantization error is sized to be much less than the noise power, so that the noise power dominates the S N D R (and can enable a more power optimal configuration). This results in an ADC resolution of at least one to two bits higher than its target SNDR. Although these two operations are seemingly simple, implementing and analyzing them are not, and have lead to a rich history of innovation in both circuits and DSP. This book discusses both sampling and quantization in the context of pipelined ADCs, including various artifacts that degrade ADC performance.

References 1. El-Chammas M (2017) Design techniques for multi-GS/s and high performance pipelined ADCs. ISSCC F6: Pushing the performance limit in data converters 2. El-Chammas M (2010) Background calibration of timing skew in time-interleaved A/D converters. PhD thesis, Stanford University 3. El-Chammas M, Li X, Kimura S, Maclean K, Hu J, Weaver M, Gindlesperger M, Kaylor S, Payne R, Sestok CK, Bright W (2014) A 12 bit 1.6 GS/s BiCMOS 2 × 2 hierarchical time-interleaved pipeline ADC. IEEE J Solid-State Circuits 49(9):1876–1885 4. Da Dalt N, Harteneck M, Sandner C, Wiesbauer A (2002) On the jitter requirements of the sampling clock for analog-to-digital converters. IEEE Trans Circuits Syst I: Fundam Theory Appl 49(9):1354–1360 5. Tsividis Y (2010) Event-driven data acquisition and digital signal processing-a tutorial. IEEE Trans Circuits Syst II Express Briefs 57(8):577–581 6. Max J (1960) Quantizing for minimum distortion. IRE Trans Inf Theory 6(1):7–12 7. Lloyd S (1982) Least squares quantization in PCM. IEEE Trans Inf Theory 28(2):129–137 8. Cantarano S, Pallottino GV (1973) Logarithmic analog-to-digital converters: a survey. IEEE Trans Instrum Meas 22(3):201–213

References

9

9. Tsividis Y (2004) Digital signal processing in continuous time: a possibility for avoiding aliasing and reducing quantization error. In: 2004 IEEE international conference on acoustics, speech, and signal processing, vol 2, pp ii–589 10. Li Y, Shepard K, Tsividis Y (2005) Continuous-time digital signal processors. In: 11th IEEE international symposium on asynchronous circuits and systems, pp 138–143 11. Nyquist H (1928) Certain topics in telegraph transmission theory. Trans Am Inst Electr Eng 47(2):617–644 12. Shannon C (1949) Communication in the presence of noise. Proc IRE 37(1):10–21 13. Whittaker ET (1915) XVIII.–on the functions which are represented by the expansions of the interpolation-theory 14. Donoho D (2006) Compressed sensing. IEEE Trans Inf Theory 52(4):1289–1306 15. Bracewell R (1978) The Fourier transform and its applications, 2nd edn. McGraw-Hill Kogakusha, Ltd., Tokyo 16. Widrow B (1956) A study of rough amplitude quantization by means of Nyquist sampling theory. IRE Trans Circuit Theory 3(4):266–276

2

Overview of Pipelined ADCs

Pipelined ADCs get their name from their intrinsic pipelining operation [1]. The final output is derived from several cascaded stages, where the intermediate analog and digital data are both pipelined over multiple clock cycles. Pipelining allows these stages to operate concurrently, improving the ADC throughput, and also allows the construction of a higher resolution ADC using lower resolution building blocks. If the ith stage of a pipelined ADC with M stages has a resolution of Ni (where 1 ≤ i ≤ M), then the ADC resolution B is function of the stage resolutions, such that B = f (N1 , N2 , . . . , N M ). Pipelined ADCs have an interesting history. Variations of ADCs built with cascaded stages (that do not necessarily operate concurrently) have existed for over half a century [2, 3]. Redundancy, an important part of pipelined ADCs (see Sect. 2.4.1), has been an instrumental element of such ADCs [4]. For more details on some of these earlier variants, [5] outlines a journey from circulation ADCs, to cascaded ADCs (with 1 bit per stage and a gain of 2), to partially cascaded ADCs (with multiple bits per stage). Pipelined ADCs also have structural similarities to algorithmic ADCs [6] and sub-ranging ADCs. For example, [7] proposes a pipelined structure from an algorithmic structure, before being more formalized in [8].1 Reference [1] is possibly the first pipelined ADC implemented in a CMOS technology, and helped set the stage for the continued evolution of this architecture. Since then, the pipelined ADC has become a powerful architecture. This chapter discusses the conceptual aspects of a pipelined ADC. It starts by framing the ADC as a search function, before focusing on the core elements of a pipelined ADC.

1 If you are familiar with even earlier implementations of pipelined ADCs, whether in patents or

literature, please reach out. © The Author(s), under exclusive license to Springer Nature Switzerland AG 2023 M. El-Chammas, High-Performance and High-Speed Pipelined ADCs, Synthesis Lectures on Engineering, Science, and Technology, https://doi.org/10.1007/978-3-031-29700-7_2

11

12

2.1

2 Overview of Pipelined ADCs

Searching for the Analog Estimate

ADCs estimate the analog input with a digital word (with a residual quantization error, as discussed in Chap. 1). An analogy of how pipelined ADCs implement this estimation is useful, as illustrated in [9]. Figure 2.1 shows a simplified version of this, where you are tasked with finding a house in a neighborhood using a map. Instead of finding it by looking at each house individually, you can find it with a series of coarse searches. First, figure out which street you should look into, as in Fig. 2.1a. Second, focus on that street, center it on your screen (Fig. 2.1b), and then zoom in (Fig. 2.1c). Third, figure out which block the house is in. Fourth, center the block (Fig. 2.1d), and zoom in again ((Fig. 2.1e). Finally, you would have zoomed in enough to figure out which house you are looking for.

Fig. 2.1 Pipelined ADC search analogy

2.1

Searching for the Analog Estimate

13

The quantization operation of a pipelined ADC estimates the analog input with a similar search function. It first finds the coarse section (of the full-scale range) the input signal is in, before zooming into that section. It can again find a coarse sub-section, and zoom into that, and so on. This iterative operation allows the quantization level closest to the analog input to be found. In fact, all ADCs are search functions, with different complexities. A flash ADC can be modeled as a parallel linear search, where every quantization level is checked simultaneously for the input signal. A SAR ADC is analogous to a binary search function (assuming a binary operation), where the search range is sequentially divided into two. The pipelined ADC is a hybrid search function, with a repeated combination of a parallel linear search and a multiway search (this is similar to a binary search, but with higher segmentation that relates to the stage resolution). For example, if each stage is a 1 bit quantizer, then the pipelined ADC is also a binary search function. In addition to its hybrid search function, the pipelined ADC allows for consecutive input signals to be operated on in parallel. By pipelining the intermediate search results in a systolic array [10], the ADC can operate on new inputs before completing that of the previous inputs, as illustrated in Fig. 2.2. Here, the ADC consists of multiple stages, and the results from one

Fig. 2.2 Systolic array representation of pipelined ADCs

14

2 Overview of Pipelined ADCs

stage are passed to the next in each time period. Thus, the search for the analog estimate is “pipelined”, and the end result of these pipelined operations is a quantized representation of the input.

2.2

Elements of a Pipelined ADC

To implement this search function, a pipelined ADC consists of cascaded stages, and each stage (except for the last) include several key elements [11], as in Fig. 2.3. These elements are the • Sub-ADC: this is a coarse ADC that spans at least the full-scale range of the stage input (analogous to the coarse search function discussed above). • DAC: this is a coarse digital-to-analog converter (DAC) that generates the signal used to shift the input signal into the appropriate range for the next cycle (analogous to part of centering function discussed above) • Summation node: this is a summation element that calculates the difference between the input and the DAC output, in order to center the segment of the input signal for the next stage (analogous to part of the centering function discussed above) • Gain: this is a gain element that amplifies the centered signal into a signal large enough for the next stage (analogous to the zoom function discussed above)

Fig. 2.3 Primary building blocks of a pipelined ADC stage

2.2

Elements of a Pipelined ADC

15

Practically, additional blocks are also needed, such as a track-and-hold (to capture the output of the stage and store it for the next stage, and discussed in Chap. 4), a clock generator (to generate the clocks required for the different blocks), and reference amplifiers (discussed in Chap. 6). However, the four elements in Fig. 2.3 constitute the core of the pipelined ADC. By cascading multiple such stages, the ADC can take an input waveform and generate a quantized output that estimates this input. The pipelined ADC does this by recursively searching for a coarse segment that contains the input, and zooming into this segment so that the next stage can continue the search. The remainder of this chapter discusses these elements in more detail, and how they come together to create the final output word. It ends by also presenting the impact of potential errors these elements may introduce.

2.2.1

The Sub-ADC

Although the sub-ADC in a stage can consist of any ADC architecture, it typically is a flash ADC. The ith stage has an Ni level ADC with a resolution of Bi = log2 (Ni ). The size of the sub-ADC least significant bit (LSB) is a function of both the full-scale range (FSR) and Ni , such that the quantized output is yi [n] = f (x[n]) = x[n] + eqi (x[n])

(2.1)

Qualitatively, the sub-ADC selects the coarse segment that contains the input signal, as in Fig. 2.4a, with a typical transfer function as in Fig. 2.5 (where F S R = 1V ). In the example of Fig. 2.5, the sub-ADC has nine levels (if the sub-ADC is a flash ADC, this is implemented with eight comparators). As in Fig. 2.3, the sub-ADC output drives the DAC to help center the relevant segment.

2.2.2

The DAC

The DAC generates an analog representation xd of the sub-ADC output. Theoretically, the DAC in a stage can be any DAC architecture that generates an appropriate analog signal. However, the two more common options are a switched-current DAC [12] or a switchedcapacitor DAC (as discussed in Chap. 3). It generates Ni levels such that it can either be driven directly by the sub-ADC output or by a mapping of the sub-ADC output (such as with dynamic-element matching [13]). The output of the DAC in the ith stage is xdi [n] = h(yi [n])

(2.2)

where yi [n] is the sub-ADC output (Eq. 2.1), and h() is the digital-to-analog transfer function.

16

2 Overview of Pipelined ADCs

Fig. 2.4 a Sub-ADC quantization example and b DAC output as a function of sub-ADC

Fig. 2.5 Transfer function for sub-ADC with nine levels

Qualitatively, the DAC generates an analog signal that represents the center of segment corresponding to the sub-ADC output, as in Fig. 2.4b, such that the transfer function of the DAC (as a function of the sub-ADC output) is as in Fig. 2.6. On its own, the DAC does not seem to do much besides converting the sub-ADC output into an analog signal. However, the quality of this conversion is an integral part of the overall ADC, as will be discussed later in this chapter and in Chap. 3. The DAC is often integrated with both the summation and the gain elements as in the topologies discussed in Chap. 3, but this not necessary [12].

2.2

Elements of a Pipelined ADC

17

Fig. 2.6 DAC transfer function

2.2.3

The Summation Node

The summation node of Fig. 2.3 subtracts the DAC output xd from the input signal x. This generates an analog signal xs [n] such that xs [n] = x[n] − xd [n] = x[n] − h(yi [n]) = −eq [n]

(2.3)

where eq [n] is the quantization error of the sub-ADC, as in Eq. 2.1. Figure 2.7a depicts this as a function of the input signal, and as expected, it has the same form as the quantization error discussed in Sect. 1.2.2. With an ideal sub-ADC, this is bounded between ± L S2 B . Qualitatively, this summation node generates the quantization error of the sub-ADC, by centering the relevant section. Although conceptually simple, it also has accuracy requirements similar to the DAC. Note that, as in Fig. 2.8a, the output of the summation node can be directly quantized with a backend ADC. Combining D1 and D B results in a higher resolution ADC. However, as in Fig. 2.7a, the output of the summation node has a reduced full-scale (± L S2 B ), which imposes significant constraints on the next stage. Instead, the signal is amplified (or, zoomed into) using a gain element. This relaxes the constraints of the next stage.

2.2.4

The Gain Element

The last element of a stage is the gain element, as in Fig. 2.3. This amplifies the output of the summation node, converting the quantization error of Fig. 2.7a into the signal of Fig. 2.7b, which has a larger magnitude. This signal is commonly called the residue, such that xo [n] = Gxs [n] = −Geq [n]

(2.4)

18

2 Overview of Pipelined ADCs

Fig. 2.7 Signal at a summation node and b output of gain element

where G is the gain. Due to this amplification, the full-scale of the residue is larger than that of the quantization error. In Fig. 2.7b, for example, the gain is set to Ni . Thus, the residue is bounded to ± F 2S R , and can be quantized by a backend ADC, as in Fig. 2.8b. Since the full-scale after the gain element is larger than its inputs, the constraints on the backend ADC are relaxed, as discussed in the next section. In a practical implementation, the gain G is set so that the residue (without additional artifacts, as discussed in Sect. 2.4.1) is limited to ± F 4S R . This allows for redundancy in the sub-ADCs, for reasons elaborated on in Sect. 2.4.1.

2.3

Cascading Multiple Stages

Section 2.2 discussed the core building blocks in a single stage. A pipelined ADC consists of multiple cascaded stages, where the output of one stage feeds into the next, as in Fig. 2.9. The structure of the last stage is simplified and consists primarily of the sub-ADC, since it does not need to generate an output residue signal.

2.3

Cascading Multiple Stages

19

Fig. 2.8 Backend ADC that a directly quantizes the summation node output or b the amplified output

Fig. 2.9 Cascaded stages in pipelined ADC, with digital outputs

There are two data paths in Fig. 2.9. The first is the analog path. Each stage (except for the last one) takes its analog input signal and passes an analog output residue signal to the next stage. The second is the digital path, where the outputs Di of the each sub-ADC are combined together to map to a single digital output word Dout .

2.3.1

Combining the Sub-ADC Outputs

The digital output Dout of a B-bit pipelined ADC is a function of all the sub-ADCs outputs, such that (2.5) Dout = f (D1 , D2 , . . . , D N ) = xin + eq (xin )

20

2 Overview of Pipelined ADCs

The mapping f is selected such that the ADC quantization error eq is equivalent to that of a 2 B-bit ADC, where L S B = F2SBR and σq2 = L S12B . This can be derived by representing Dout as a linear combination of the sub-ADC outputs, such that Dout =

N

Hi Di

(2.6)

i=1

for a set of scaling factors Hi . Since the digital output of the ith stage is if i = 1 xin + eq,1 Di = xi + eq,i = −G i−1 eq,i−1 + eq,i otherwise

(2.7)

where eq,i is the quantization error of the ith stage, Eq. 2.6 becomes Dout =

N

Hi (xi + eq,i ) = H1 (xin + eq,1 ) +

i=1

N

Hi (−G i−1 eq,i−1 + eq,i )

i=2

= H1 xin + H N eq,N

(2.8)

N + (Hi−1 − Hi G i−1 )eq,i−1 i=2

There are three components in Eq. 2.8. First, the input signal, with H1 xin , is clearly evident. Second, a scaled version of the quantization error of the final stage, with H N eq,N , is also present. Third, the quantization errors of all the intermediate stages are available as a function of the linear scale factors Hi and the stage gain G i . By pipelining the stages, the quantization error of the intermediate stages are quantized by the next stage. These intermediate quantization errors do not appear in the output of Eq. 2.7 if 1 if i = 1 1 if i = 1 Hi = Hi−1 = i−1 1 (2.9) otherwise j=1 G j G i−1 otherwise With this, the ADC output reduces to Dout = xin + H N eq,N = xin + eq,N

N −1 j=1

1 Gj

(2.10)

The quantization error of the last stage is attenuated by the gain values of the preceding stages, and those of the intermediate stages are canceled. Therefore, the mean-square error of the quantization is L S B N2 1 (2.11) σq2 = · N −1 2 12 j=1 G j

2.3

Cascading Multiple Stages

21

where L S B N is the LSB of the Nth stage. With B N bits and a full-scale range of F S R N in the last stage, L S B N = F S R N /2 B N , and Eq. 2.11 becomes σq2 =

F S R 2N 1 1 · 2 = 12 · N −1 12 2 B N + j=1 log2 (G j )

F S RN 2 BT

2 (2.12)

The total ADC resolution BT is a function of the resolution of the last stage and the sum of the logarithms of the inter-stage gains,2 such that BT = B N +

N −1

log2 G j

(2.13)

j=1

Thus, after combining the stage outputs, the mean-square error of the pipelined ADC quantization error is equivalent to that of a BT -bit ADC. In other words, a pipelined ADC cascades low resolution stages to create a high resolution ADC.

2.3.1.1 Combining the Digital Outputs The pipelined ADC output is generated by adding up scaled sub-ADC outputs, as in Eq. 2.6, where the scaling factors are as in Eq. 2.9. These factors can be fixed coefficients, based on the pipelined architecture, or adjustable coefficients if calibration is implemented [14]. Two equivalent implementations of this are illustrated in Fig. 2.10, where the difference between outputs of Fig. 2.10a and b is a linear gain factor. Figure 2.10b is the more standard implementation approach, in part because the earlier stages generate their digital outputs earlier in the conversion cycle. With this, the output is generated with a series of multiplyaccumulate operations. Qualitatively, the outputs of the sub-ADCs are realigned based on the values of Hi , as in Fig. 2.11. Often, the values of G i (and therefore, of Hi ) are powers of two, which allows for a trivial implementation in the digital domain (with a series of bit shifts). This simplifies the output combination to only a series of accumulate operations (with shifted sub-ADC outputs). In Fig. 2.11, for example, there is a one-bit overlap between digital outputs, as a function of pipelined ADC redundancy, which is discussed in Sect. 2.4.1.

2.3.1.2 Relationship Between Inter-Stage Gain and Stage FSR In most implementations of pipelined ADCs, the full-scale range is constant across stages. However, it is possible to have different full-scale ranges for each stage. In such designs, the effective inter-stage gain, which defines the stage resolution, is not equal to the gain G i of the gain element [15]. For example, assume the gain of the first stage is G 1 . If the full-scale 2 The total ADC resolution is not directly a function of the resolution of the intermediate sub-ADCs,

which provides valuable degrees of freedom in the design of pipelined ADCs.

22

2 Overview of Pipelined ADCs

Fig. 2.10 Two methods to generate the ADC output by combining the digital outputs of the stages

Fig. 2.11 Sub-ADC digital output combination with 1-bit overlap between stages

range of the second stage is reduced to half that of the first, such that F S R2 = F S2R1 , then intuitively, G 1 would reduce by half in order to maintain the same relative input signal range for the second stage. In general, the effective inter-stage gain is G i,e f f = G i

F S Ri F S Ri+1

(2.14)

In case the full-scale range is not constant across stages, the previous derivations for Eqs. 2.9 and 2.13 can be modified to use the effective inter-stage gain. Furthermore, even though the effective inter-stage gain may be designed to be a power of two (providing

2.3

Cascading Multiple Stages

23

one bit of sub-ADC redundancy), the gain G i does not need to be. In [15], for example, the effective inter-stage gain was eight, whereas the gain was six. This relaxes amplifier linearity constraints due to the reduced output swing.

2.3.2

Impact of Gain on Input-Referred Noise

Although this book does not focus on noise, it is important to discuss this in the context of inter-stage gain, as it affects architectural decisions. Assuming uncorrelated noise sources, the variance of the total input-referred noise of a properly configured pipelined ADC is 2 = σn,T

N 2 σn,i i=1

Hi2

2 = σn,1 +

N i=2

2 σn,i i−1 2 j=1 G j

(2.15)

where σn,i is the standard deviation of the input-referred noise of each stage. The noise of later stages is attenuated by the cumulative inter-stage gain of the preceding stages. Consider a simple example, where G i = G and σn,i = σn ∀i. Thus, 2 1 − G 2N σn2 σn2 σn2 2 2 G + + · · · + = σ ≈ σ n n (G)2 (G 2 )2 (G N −1 )2 G2 − 1 1 − 12 1

2 σn,T = σn2 +

(2.16)

G

where the last approximation assumes G 2N 1. From an input-referred noise perspective, increasing the gain decreases the total input-referred noise (with diminishing returns), and converges to the noise of the first stage for large G. Even without the assumption that all the stage gains are equal to G, the noise of the later stages are significantly attenuated and marginally impact the total ADC noise. This cumulative attenuation for later stages means that it is power sub-optimal to have the noise in each stage equal to that of the first stage.

2.3.3

Impact of Gain on Power

Later stages have a diminishing impact on the total input-referred noise due to the cumulative gain of the preceding stages, as in Eq. 2.15. Since halving the noise power of a given circuit topology will double the circuit power,3 it is more power optimal to increase the inputreferred noise of later stages. This design optimization can significantly reduce the overall power dissipation [16–18]. The total power of a stage is a complex model of various parameters. This section analyzes a simplified power model, to illustrate architectural optimization, and the model can be expanded to include various relevant design parameters. For the purpose of this analysis, 3 This excludes potential design and topology optimization. Reducing the power but maintaining the

circuit bandwidth results in a reduced capacitance and decreased gm .

24

2 Overview of Pipelined ADCs

the total power Pi of the ith stage is broken into three components. The first is a resolution dependent component (that is independent of noise, such as for the sub-ADC) Pc,i = Pc,0 2 Bi , where Pc,0 and Bi are the nominal power value and the sub-ADC resolution, respectively. The second is a noise dependent component (that is a function of noise, such as in the σ2

amplifier) Ps,i = Ps,0 σn,0 2 where Ps,0 and σn,0 are the nominal power and noise sigma, and n,i

σn,i is the stage noise sigma. The third is simply a constant power value Pk (for example, due to biasing circuits). Therefore, the total power Pi of the ith stage is Pi = Pk + Pc,0 2 Bi + Ps,0

2 σn,0

(2.17)

2 σn,i

and the total ADC power is PT =

N

Pi =

i=1

N

Pk + Pc,0 2

Bi

+ Ps,0

i=1

2 σn,0 2 σn,i

(2.18)

Note that this is clearly a simplistic model. For example, the last stage does not have a DAC or gain element. The power of elements such as the amplifier and DAC are a function of multiple parameters besides noise targets (such as inter-stage gain, resolution, and settling requirements), and the factors Pc,0 and Ps,0 can be stage dependent. Thus, what follows is illustrative, but not prescriptive, and a thorough analysis to capture a more complete and realistic power model is a powerful tool in pipelined ADC design.4 With this, the total power can be optimized by bounding the total input referred noise to σn , such that min

σn,i ∀i

PT (2.19)

s.t. σn,T < σn where σn,T and PT are as in Eqs. 2.15 and 2.18, respectively.

2.3.3.1 Optimization Example To illustrate the analysis with a simple example, assume a B-bit ADC and that each stage has a gain of G. The resolution of each stage is equal to B S , where B S = log2 (G), and thus the total number of stages is N = BBS . Let B = 12, Pk = 2, Pc,0 = 1, and Ps,0 = 10. How should the stages be sized?

4 Keeping track of current consumption and power of the different blocks in a system, and capturing

their relationship with important metrics such as noise, is recommended throughout the design process. As the design progresses, this view helps shed light on any potential architectural and circuit-level weaknesses, and gives insight into optimization knobs.

2.3

Cascading Multiple Stages

25

Fig. 2.12 Power as a function of inter-stage gain

First, assume this ADC is naively designed, such that the stages are not scaled (thus having the same noise sigma). With σn,T = σn (the target standard deviation), the total power without stage scaling is plotted as a function of the gain per stage in Fig. 2.12. Here, it is clearly inefficient to use a low gain value since many stages are required, and as the gain increases, the resolution-dependent power begins to eventually dominate. Now, assume a less naively designed ADC. It is clear that since the last several stages have negligible effect on the input-referred noise, it is not power optimal (or area optimal) for these stages to have the same input-referred noise as the first stage. The optimal scaling factors can be obtaining by solving Eq. 2.19 using tools such as [19]. The power with optimal scaling as a function of gain is also plotted in Fig. 2.12, and is lower than that without scaling. These scaling factors are plotted in Fig. 2.13a for different stage gains. Later stages are significantly smaller than the first stage, since their noise contribution quickly diminishes. This saves power. However, unbounded scaling is not practical from a technical perspective or a business one. For example, if the sampling capacitor of the first stage is 1pF, the scaling factors in Fig. 2.13a suggest a capacitor less than 1fF in the last stage. In addition, since optimizing each stage takes time (and introduces additional risk), it is also sub-optimal from a time-to-market and engineering effort perspective. To illustrate, assume the scaling factor is limited to 16. The optimization framework of Eq. 2.19 can be modified to include this as a constraint. The resulting optimal power with limited scaling is plotted in Fig. 2.12, and the relevant scaling factors are in Fig. 2.13b. There is just a minimal increase in power compared to optimal scaling. Note that the optimal power in Fig. 2.12 has a shallow minimum [17]. It is in the designer’s interest to accurately account for as many power sources in the design as possible (as mentioned, the example used here is simplistic), but to also keep in mind that other design related factors should also factor into this optimization framework (such as DAC mismatch,

26

2 Overview of Pipelined ADCs

Fig. 2.13 Optimal scaling factors as a function of inter-stage gain with a no bound on scaling and b a bound of 16

amplifier bandwidth, etc., which have not been considered here). These factors can all be included into a core optimization framework that allow for a robust analysis of overall power and complexity, and is a worthwhile effort in the task of optimizing the pipelined ADC topology.

2.4

Pipelined ADC Architectural Artifacts

This overview of pipelined ADCs ends with a discussion on several impairments that impact the accuracy of the conversion. Pipelined ADCs operate by coarsely quantizing the input signal, and then passing on the amplified quantization error to the next stage. What happens to the integrity of the final digital output if the stage elements are non-ideal?

2.4

Pipelined ADC Architectural Artifacts

2.4.1

27

Impact of Non-ideal Sub-ADCs

The previous discussions assumed the sub-ADC to be an ideal quantizer (as evident in the plot of Fig. 2.7, where each level has the same size). However, ADCs have mismatch and noise, which impact the ADC thresholds in a systematic and a random fashion, respectively. Both the ideal transfer function and an example real transfer function (with non-uniform step sizes as a function of threshold mismatches) of an example ADC (with N = 8 thresholds) are illustrated in Fig. 2.14a and b, respectively. This degrades the sub-ADC linearity. How does this affect the pipelined ADC? The stage residue plot (as in Fig. 2.7b) is a useful way of capturing these sources of error. The sub-ADC transfer functions of Fig. 2.14 result in the residue plots of Fig. 2.15. In this scenario, G = 8 (matching the number of thresholds), and the horizontal lines denote the full-scale range of the subsequent stage. In Fig. 2.15a, the residue is fully within the input range of the next stage. However, in Fig. 2.15b, the residue is larger than | L S2 B | and surpasses the full-scale range due to the sub-ADC threshold mismatch. Unless the next stage can handle such excursions, this can lead to gross errors in the pipelined ADC transfer function.

Fig. 2.14 Sub-ADC transfer function with a ideal thresholds and b threshold mismatch

28

2 Overview of Pipelined ADCs

Fig. 2.15 Stage residue as a function of sub-ADC a ideal thresholds, b threshold mismatch, and c random thresholds

Random threshold values, such as those due to noise, also impact the stage output. For example, the residue plot in Fig. 2.15c is not deterministic, and can also lead to excursions from the input full-scale range of the next stage.

2.4

Pipelined ADC Architectural Artifacts

29

Reducing the mismatch and noise of the sub-ADC has a direct cost in terms of power and area. For example, if the sub-ADC is a standard flash ADC, then reducing the mismatch by 2X increases the area by 4X (assuming a fixed topology) [20, 21], or would require additional offset correction [22]. Reducing the input-referred noise of the comparator has a similar tradeoff, and the pipelined ADC would not be a workable architecture if it were this sensitive to noise and mismatch in the sub-ADC. Luckily, this sensitivity is significantly reduced due to redundancy.

2.4.1.1 Value of Redundancy In the previous analysis, G = N . Given the sensitivity of the residue to sub-ADC artifacts, one option is to reduce G i so that there is sufficient margin between the residue and the full-scale range of the next stage. For example, if G = N /2, the effective resolution of the stage is one bit less than the resolution of the sub-ADC, resulting in sub-ADC redundancy (often referred to as error correction). The output residue is plotted in Fig. 2.16 (with and without mismatch). Even though this example has the exact same sub-ADC mismatch as that of Fig. 2.15b, the residue plot does not exceed the full-scale range. It may appear that residue plot in Fig. 2.16 still introduces errors into the pipelined ADC transfer function, since the ENOB of the sub-ADC will be lower with threshold mismatch than without. For a given input value, the residue with threshold mismatch is xr ,i = −G i · eq,i

(2.20)

where eq,i is the quantization error of the imperfect sub-ADC. Since the residue is quantized by the next stage, the combination of the digital outputs is

Fig. 2.16 Stage residue as a function of sub-ADC thresholds (both ideal and non-ideal), with redundancy

30

2 Overview of Pipelined ADCs

Di +

−G i · eq,i + eq,i+1 eq,i+1 Di+1 = xi + eq,i + = xi + Gi Gi Gi

(2.21)

which holds as long as the residue is within the full-scale range of the subsequent stage. Thus, even with threshold mismatch, the sub-ADC quantization error of the intermediate stages is removed from the pipelined ADC output once the stage outputs are digitally combined. This results in a significant resiliency in pipelined ADCs. The use of redundancy introduces a clear benefit since it relaxes the design constraints of the sub-ADC. The cost is the increased number of stages. For example, if N = 8 in each stage, then a 12-bit ADC would have log12(8) = 4 stages if there were no redundancy and 2

= 6 stages if there were redundancy. To clearly demarcate the effective resolution from the sub-ADC resolution, it is common to explicitly define the stage resolution as Bi = Be f f ective + Br edundant . For example, a 4 bit stage with a gain of 8 (an effective resolution of 3 bits) is defined as a 3 + 1 bit stage. A common example of redundancy that is taught in academia and is used by some industry solutions is the 1.5 b/stage pipelined ADC [23–25], which has some architectural benefits. This is implemented with two comparators in the sub-ADC and an inter-stage gain of 2, such that the stage has an effective resolution of log2 (G i ) = 1 bit. The sub-ADC has log2 (3) ≈ 1.5 bits (hence the name). Thus, there is only a half-bit of redundancy, and this implementation is a 1 + 0.5 bit stage. 12 log2 (8/2)

2.4.2

Impact of Non-ideal DACs

The DAC will also be non-ideal and will also have an impact on the residue plot. Unlike the sub-ADC, however, the DAC output directly changes the residue value in a way that does not cancel out when the stage outputs are digitally combined. For example, if the DAC transfer function is xd = D1 + e1 (D1 ), then the output Dout is G 1 (xin − xd ) + eq,2 D2 = D1 + G1 G1 eq,2 = D1 + (xin − (D1 + e1 (D1 ))) + G1 eq,2 = xin − e1 (D1 ) + G1

Dout = D1 +

(2.22)

This has a new component e1 (D1 ), which is the DAC error as a function of D1 , the sub-ADC output. Thus, the DAC error appears as part of the stage input (and if this is the first stage, it directly appears with the ADC input), affecting ADC linearity. The DAC error can include both random and systematic errors, each of which has a different impact on ADC performance. For example, DAC noise directly impacts the noise power of the stage. Examples of DAC code-dependent errors e1 (D1 ) and a linear gain error G D are plotted in plotted in Fig. 2.17a and b, respectively. The impact of these transfer

2.4

Pipelined ADC Architectural Artifacts

31

Fig. 2.17 DAC error plot with a non-linear errors and b linear gain error

functions on the stage residue is illustrated in Fig. 2.18, where segments in the residue plot have a code-dependent offset when compared to the residue with an ideal DAC. This directly distorts the final ADC output, as in Eq. 2.22. Since DAC errors directly appear with the stage input signal, it requires precision commensurate with the stage specifications. In the first stage, the DAC would need to be as linear as the target ADC linearity. For resolutions larger than 8–10 bits, this an expensive DAC (in terms of area and power). Fortunately, both of these DAC errors can be corrected, as discussed in Chap. 7.

2.4.3

Impact of Non-ideal Gain Elements

The residue is generated by amplifying the sub-ADC quantization error, such that Dout = D1 + H1 G 1 (xin − D1 ) + H1 eq,2 = xin +

eq,2 G1

(2.23)

32

2 Overview of Pipelined ADCs

Fig. 2.18 Stage residue as a function of DAC with a non-linear errors and b a linear gain error

where G 1 is the gain of the first stage, H1 = G11 is the digital gain used to combine the backend output, and eq,2 is the quantization error of the backend ADC. Errors in the gain element also directly appear in the signal path and can have both random and systematic errors, as is the case with DAC errors. For example, the first stage gain element’s inputreferred noise directly appears with the stage input signal, degrading the SNR. The gain element can introduce errors such as a linear gain error g, with a gain G = G 1 (1 + g), or a signal dependent error (such as a second or third order expansion [14]), with an amplifier output of Gx + f a (x), where f a (x) is the amplifier nonlinearity. The pipelined ADC output becomes −G 1 (1 + g)eq,1 − f a (eq,1 ) + eq,2 eq,2 − f a (eq,1 ) = xin − geq,1 + G1 G1 (2.24) When H1 does not cancel the inter-stage gain due to a gain error, the sub-ADC quantization error eq,1 “leaks” into the output. The impact of a linear and nonlinear gain error on the stage residue plots are plotted in Fig. 2.19a and b, respectively. Dout = D1 +

2.4

Pipelined ADC Architectural Artifacts

33

Fig. 2.19 Stage residue as a function of gain errors. a With linear gain mismatch and b with third order nonlinearity

Note that the error in Fig. 2.19a, due to a linear gain error, is primarily an issue because it results in a mismatch with the digital gain H1 , since that is no longer equal to the inverse of the gain value. If, however, H1 is adjusted such that H1 (G 1 + g) = 1, then the sub-ADC quantization error is removed. As a result, linear gain mismatch can typically be corrected without too much effort (see Chap. 7 for more details). Nonlinear gain errors can also be corrected for, but do require more complicated algorithms [14].

2.4.3.1 Relationship to DAC Error The linear gain error in a DAC creates a response similar to that of an inter-stage gain error. Intuitively, this results in a scaled quantization error due to the increased DAC L S B, which meshes with the gain, resulting in an inter-stage gain error. Analytically, Eq. 2.22 can be rewritten as Dout = D1 +

G 1 (xin − (1 + g)D1 ) + eq,2 eq,2 = (1 − g)xin − geq,1 + G1 G1

(2.25)

34

2 Overview of Pipelined ADCs

Similarly to gain errors, a DAC linear gain error results in quantization “leakage” as a function of the error, impacting ADC linearity. In addition, a global gain error is introduced. As discussed in Chap. 7, it is possible to correct for both gain and DAC errors with similar mechanisms.

2.5

Impact on ADC INL

This chapter wraps up by summarizing the impacts of the mismatches in Sect. 2.4 on the ADC nonlinearity (such as the integral nonlinearity, commonly known as INL). Although FFTs capture many useful metrics, the ADC INL captures mismatch-related signatures that provide useful insight. To illustrate, this section uses a simple ADC model, as in Fig. 2.20. This ADC has a (2 + 1) bit first stage, and a 10 bit backend ADC, resulting in a 12-bit ADC. The mismatch errors of Sect. 2.4 directly impact the ADC linearity, and can be captured by both dynamic metrics (SFDR, SNDR, etc.) and static metrics (INL and DNL). For example, in an FFT analysis, the resulting quantization errors are correlated to the input signal,5 which appear as higher order harmonics [27], as illustrated in Fig. 2.21. However, relating those harmonics to specific errors is challenging. In INL plots, however, these errors create different and mismatch-specific signatures (in fact, Chap. 7 uses this type of analysis to estimate the relevant mismatches).

2.5.1

Extracting Nonlinearity Plots

Standard INL plots (such as those obtained with the histogram method [28]) require a large number of data points, which is impractical to use in simulations. Furthermore, in high-speed

Fig. 2.20 Example pipelined ADC for nonlinearity analysis 5 These errors also impact small-signal linearity, as the input signal amplitude decreases. In some

applications, this is not acceptable. Although correcting these errors helps (see Chap. 7), any residual errors will result in dips in the SFDR plots as the input signal crosses various stage transitions. Dither, not discussed in this book, is one technique that helps randomize these residual errors, as discussed in [26].

2.5

Impact on ADC INL

35

Fig. 2.21 FFT of a an ideal ADC b an ADC with gain errors and c an ADC with DAC errors

ADC design and measurements, sine-wave testing is the standard choice. It is possible to extract an INL-like plot from this data, which captures the nonlinearity (NL) of the ADC, and allows for the same data to be used to generate both an FFT and an NL plot. To generate the NL plot, a best-fit sine wave (Db f ) is extracted from the captured data Dout , such that the error is (2.26) e N L = Dout − Db f Here, Db f = A sin(2π f in + φ) for some A and φ that minimizes the mean-square error of e N L . Fortunately, this best-fit signal can be directly derived from the FFT of the output data without any additional analysis. The error e N L captures both random errors and systematic ones. It can be plotted versus the ADC code, capturing signal-dependent signatures. The NL error can also be generated for the backend ADC, in order to capture the behavior of each stage (as illustrated in Chap. 7).

36

2.5.2

2 Overview of Pipelined ADCs

Example Nonlinearity Plots

For an ideal (and noiseless) ADC, the NL plot is as in Fig. 2.22a. Due to quantization, e N L includes the quantization error of ± L S2 B , as is evident in Fig. 2.22a. Here, the error plot is color-coded as a function of the first stage sub-ADC output. The signature of these nonlinearity plots depends on the error source. For example, a codedependent DAC error does not correctly shift the coarse segment. This is directly reflected in the ADC NL plot, as in Fig. 2.22b, which is color-coded for different sub-ADC output codes. The error transfer function is different than that of Fig. 2.22a, since the error has a code-dependent offset that exceeds the expected quantization bounds. Gain errors create a different signature. As discussed, gain error is either due to an error in the DAC gain, or an error in the gain element. Both of these are depicted in the error plots of Fig. 2.23a and b, respectively. The signatures of both are similar, and the error curve now has a non-zero slope in each segment that corresponds to a sub-ADC code. These signatures are not random. Although the deterministic nature of these errors is evident in the spectrums of Fig. 2.21b and c, their source is unclear. Fortunately, the NL

Fig. 2.22 a Error plot for ideal ADC and b error plot for an ADC with DAC nonlinearity

References

37

Fig. 2.23 NL error plot for an ADC with a a linear DAC gain error and b a stage output gain error

error plots, which can be extracted from the same data used to generate FFT plots, provide deep insight. They are an instrumental tool in both the pre-silicon and the post-silicon phase, and will be useful when correction is discussed in Chap. 7.

References 1. Lewis S, Gray P (1987) A pipelined 5-Msample/s 9-bit analog-to-digital converter. IEEE J SolidState Circuits 22(6):954–961 2. Smith B.D. (1956) An unusual electronic analog-digital conversion method. IRE Trans Instrum, vol. PGI-5, pp 155–160 3. Savitt D (1959) A high-speed analog to digital converter. IRE Trans Electron Comput, EC8(1):31–35 4. Verster TC (1964) A method to increase the accuracy of fast-serial-parallel analog-to-digital converters. IEEE Trans Electron Comput EC-13(4):471–473 5. Schmid H (1970) Electronic analog/digital conversions. Van Nostrand Reinhold Company 6. Li P, Chin M, Gray P, Castello R (1984) A ratio-independent algorithmic analog-to-digital conversion technique. IEEE J Solid-State Circuits 19(6):828–836

38

2 Overview of Pipelined ADCs

7. Kinniment DJ, Aspinall D, Edwards DB (1966) High-speed analogue–digital convertor. In: Proceedings of the institution of electrical engineers, vol 113, pp 2061–2069(8) 8. Severin J (1971) Technique for high speed analog-to-digital conversion 10. US Patent App. 3599204 9. Buchwald A (2008) Pipelined A/D converters: The basics. ISSCC T2 10. Kung H, Leiserson C (1978) Systolic Arrays for (VLSI). CMU-CS, Carnegie-Mellon University, Department of Computer Science 11. Pelgrom MJM (2010) Analog-to-Digital Conversion, 1st edn. Springer Publishing Company, Incorporated 12. El-Chammas M, Li X, Kimura S, Maclean K, Hu J, Weaver M, Gindlesperger M, Kaylor S, Payne R, Sestok CK, Bright W (2014) A 12 bit 1.6 GS/s bicmos 22 hierarchical time-interleaved pipeline ADC. IEEE J Solid-State Circuits 49(9):1876–1885 13. Galton I (2000) Digital cancellation of D/A converter noise in pipelined A/D converters. IEEE Trans Circuits Syst II: Analog Digit Signal Process 47(3):185–196 14. Murmann B, Boser B (2003) A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification. IEEE J Solid-State Circuits 38(12):2040–2050 15. Payne R, Corsi M, Smith D, Kaylor S, Hsieh T (2010) A 16-Bit 100 to 160 MS/s SiGe BiCMOS pipelined ADC With 100 dBFS SFDR. IEEE J Solid-State Circuits 45:2613–2622 16. Kwok P, Luong H (1999) Power optimization for pipeline analog-to-digital converters. IEEE Trans Circuits Syst II: Analog Digit Signal Process 46(5):549–553 17. Chiu Y, Gray P, Nikolic B (2004) A 14-b 12-MS/s CMOS pipeline ADC with over 100-SD SFDR. IEEE J Solid-State Circuits 39(12):2139–2151 18. Cline D, Gray P (1996) A power optimized 13-b 5 Msamples/s pipelined analog-to-digital converter in 1.2 /spl mu/m CMOS. IEEE J Solid-State Circuits 31(3):294–303 19. Diamond S, Boyd S (2016) CVXPY: a Python-embedded modeling language for convex optimization. J Mach Learn Res 17(83):1–5 20. Pelgrom M, Duinmaijer A, Welbers A (1989) Matching properties of MOS transistors. IEEE J Solid-State Circuits 24:1433–1439 21. Flynn M, Donovan C, Sattler L (2003) Digital calibration incorporating redundancy of flash ADCs. IEEE transactions on circuits and systems ii: analog and digital signal processing 50(5):205–213 22. El-Chammas M (2010) Background calibration of timing skew in time-interleaved A/D Converters. PhD thesis, Stanford University. 23. Abo A, Gray P (1999) A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter. IEEE J Solid-State Circuits 34:599–606 24. Lewis S, Fetterman H, Gross G, Ramachandran R, Viswanathan T (1992) A 10-b 20-Msample/s analog-to-digital converter. IEEE J Solid-State Circuits 27(3):351–358 25. Cho T, Gray P (1995) A 10 b, 20 Msample/s, 35 mw pipeline a/d converter. IEEE J Solid-State Circuits 30(3):166–172 26. El-Chammas M, Li X, Kimura S, Coulon J, Hu J, Smith D, Landman P, Weaver M (2015) 15.8 90dB-SFDR 14b 500 MS/s MICMOD switched-current pipelined ADC. In: 2015 IEEE International Solid-State Circuits Conference—(ISSCC) Digest of Technical Papers, pp 1–3 27. Pan H, Abidi A (2004) Spectral spurs due to quantization in Nyquist ADCs. IEEE Trans Circuits Syst I Regul Pap 51(8):1422–1439 28. IEEE standard for terminology and test methods for analog-to-digital converters. IEEE Std 12412010 (Revision of IEEE Std 1241-2000), pp 1–139, 2011

3

Pipelined ADC Topologies

Pipelined ADCs can be implemented in various technologies with different topologies. The most common framework in CMOS technology is that of switched-capacitors [1], which is the focus of this chapter. However, in certain cases, alternative structures, such as switched-current pipelined ADCs, are a viable and more applicable option, and several implementations of these topologies are discussed in [2–7].

3.1

Switched-Capacitor Topologies

A pipelined ADC has a configuration as in Fig. 2.9, where all stages except for the last have a structure as in Fig. 2.3 (the last stage consists of a sub-ADC). With switched-capacitors, it is possible to combine the DAC, summation, and gain elements into a multiplying digitalto-analog converter (MDAC), as in Fig. 3.1. Figure 3.1 contains a sub-ADC, various switches, sampling and feedback capacitors, reference voltages, and an amplifier, in a differential configuration. Although this is visually different from Fig. 2.3, it has the same function. The sub-ADC coarsely quantizes the input signal, and the DAC is integrated within the amplification structure via the sampling capacitors Cs and reference signals vr e f p/n , such that the output of the amplifier is the residue G(xin − xd ). The signal flow can be captured by dividing the functionality of Fig. 3.1 into two phases and analyzing the distribution of charge.1 1 The analysis in this chapter assumes linear capacitors, which, if implemented with devices such

as MOM capacitors, is a reasonable assumption. However, if nonlinear capacitors are used (such as MOS capacitors), the voltage dependent capacitor values [8] should be considered in the charge analysis. © The Author(s), under exclusive license to Springer Nature Switzerland AG 2023 M. El-Chammas, High-Performance and High-Speed Pipelined ADCs, Synthesis Lectures on Engineering, Science, and Technology, https://doi.org/10.1007/978-3-031-29700-7_3

39

40

3 Pipelined ADC Topologies

Fig. 3.1 Switched-capacitor MDAC topology

Figure 3.2 illustrates the two phases of the switched-capacitor topology of Fig. 3.1. The first phase, as in Fig. 3.2a, is the track phase, where the sampling capacitors Cs are connected to the input signal, and the feedback capacitors C f are reset. At the end of the first phase, bottom-plate sampling holds the tracked input signal on the capacitors,2 such that the total charge on both Cs and C f in each half-circuit is Q p1 = (vinp − vcmi )N Cs + (vcmo − vcmi )C f Q n1 = (vinn − vcmi )N Cs + (vcmo − vcmi )C f

(3.1)

where vcmi and vcmo are the input and output common-modes, respectively. There are two components to this charge. The first is the signal-dependent charge stored on C S , the sampling capacitors. The second is the signal-independent charge on C f , the feedback capacitors, which are reset to a constant voltage. The total differential charge is Q 1 = Q p1 − Q n1 = (vinp − vinn )N Cs = vid N Cs

(3.2)

where vid = vinp − vinn is the differential input voltage. The second phase, as in Fig. 3.2b, is the redistribution phase (which generates the output residue3 ). The sub-ADC output D (which ranges from 0 to N ) drives the reference switches that connect Vr e f p/n to the N sampling capacitors, and the amplifier outputs drive

2 Bottom-plate sampling still suffers from charge injection. However, this is, to a first-order, signal-

independent, and cancels out in a differential configuration. 3 In different topologies, such as those of switched-current pipelined ADCs [2], this phase can be

referred to as the residue generation phase. Charge redistribution is primarily used in switchedcapacitor topologies.

3.1

Switched-Capacitor Topologies

41

Fig. 3.2 Switched-capacitor topology in a track phase and b redistribution phase

the feedback capacitors. The reference switches are configured differentially, such that in each half-circuit of Fig. 3.2b, D capacitors are connected to either vr e f p or vr e f n , and N − D caps are connected to vr e f n or vr e f p . The charge at the end of the second phase4 is Q p2 = Dvr e f p + (N − D)vr e f n − vx Cs + (vop − vx )C f Q n2 = Dvr e f n + (N − D)vr e f p − vx Cs + (von − vx )C f

(3.3)

where vx is the virtual ground voltage at the input of the amplifier. The differential charge in the second phase is 4 Note that, in this analysis, the amplifier’s settling error is assumed to be zero, with infinite open-loop

gain and bandwidth. Practically, the open-loop gain and bandwidth should be selected to make the settling error “small” enough. If it is not, than the virtual ground condition on the amplifier input is not maintained, which impacts the charge transfer. Various work over past years has focused on relaxing this constraint [9, 10].

42

3 Pipelined ADC Topologies

Fig. 3.3 Residue plot with G = 4 and N = 8

Q 2 = Q p2 − Q n2 = (2D − N ) V R Cs + vod C f

(3.4)

where V R = vr e f p − vr e f n is the differential reference voltage, and vod = vop − von the differential output voltage. Since the total charge is conserved, the differential output voltage is derived by setting Q 1 = Q 2 , such that N Cs 2D − N = G (vid − v D AC ) vid − V R (3.5) vod = Cf N where the gain and the DAC transfer function are, respectively, G=

2D − N N Cs and VD AC = V R Cf N

(3.6)

Equation 3.5 has the same form as Eq. 2.4, and V R is a function of the ADC FSR. By configuring the reference switches as a function of the sub-ADC output D, the differential output is an amplified version of the sub-ADC quantization error. For example, if N = 8 and G = 4 (this provides a extra bit of redundancy5 ), then the residue transfer function with 2V R = F S R is plotted in Fig. 3.3.

5 The sub-ADC output has nine levels, as seen in Fig. 3.3, which is log (9) ≈ 3.1 bits, and the 2 stage resolution is log2 (4) = 2 bits. With nine levels, the sub-ADC output word needs four bits, and assigning the right value to each level can simplify the digital combination to ensure that an input of vin = −0.5F S R results in an output of zero and an input of vin = 0.5F S R results in an output of 2 B − 1.

3.1

Switched-Capacitor Topologies

3.1.1

43

Impact of Capacitor Mismatch

Capacitors are an integral part of the switched-capacitor MDAC operation, impacting both the stage gain and the residue generation, as in Eq. 3.5. The charge analysis of Eqs. 3.1 and 3.3 assumed all the MDAC capacitors were equal to their ideal value. Removing this assumption, such that Csp,i and Csn,i are the ith sampling capacitors for the positive and negative half circuit (and similarly for the feedback capacitors), the charge equations in the two phases are Q p/n1 = (vinp/n − vcmi )

N

Csp/n,i + (vcmo − vcmi )C f p/n

i=1 D N = vr e f p/n − vx Csp/n,i + vr e f n/ p − vx Csp/n,i

Q p/n2

i=1

(3.7)

i=D+1

+ vop/n − vx C f p/n

Each capacitor can be expressed in terms of the ideal capacitors Cs and C f and its error, such that Csp/n,i = Cs (1 + Cep/n,i ) and C f p/n = C f (1 + Cep/n, f ). Furthermore, the errors can be combined into 2Ce,i/ f = Cep,i/ f + Cen,i/ f , such that the differential charge in each phase is Q 1 = vid Cs

N

(1 + Ce,i ) + (vic − vcmi )Cs

i=1

N

(Cep,i − Cen,i )

i=1

+ (vcmo − vcmi )C f (Cen, f − Cep, f ) Q 2 = VR Cs

Do

(1 + Ce,i ) − V R Cs

N

(1 + Ce,i ) + (vr c − vx )

i=Do +1

i=1

N

(Cep,i − Cen,i )

i=1

+ vod C f (1 + Ce, f ) − (voc − vx )(Cep, f − Cen, f ) (3.8) where vid is the differential input signal, vic is the input common-mode, V R is the differential reference voltage, vr c is the reference common-mode, vod is the differential output voltage, and voc is the output common-mode. In each of these two equations, there is a signaldependent component and a signal-independent component that are both a function of the capacitor errors. The differential output voltage is vod

Cs = vid Cf − VR

N

i=1 (1 + C e,i )

(1 + Ce, f ) N Do (1 + Ce,i ) − i=D (1 + Ce,i ) Cs i=1 o +1 Cf

(1 + Ce, f )

+ f (vic , voc , vcmo , vcmi , vr c , vx , vcmi , Ce )

(3.9)

44

3 Pipelined ADC Topologies

where the last term is signal-independent and is a function of the different common-mode voltages and the capacitor errors. This constant appears as an offset, and although this will not be discussed further, it must be noted that this offset should be controlled (for example, the output common-mode feedback circuit should be properly implemented [11]), since it can impact later stages.

3.1.1.1 Impact of Capacitor Mismatch on Gain Error The stage gain G is a function of the ideal gain G ideal and the gain error eG , such that G = G ideal (1 + eG ). When (for example) the first stage eG = 0, the quantization error eq1 of the first stage “leaks” into the ADC output. The residual error power can be written in terms of this quantization error and the gain error, such that 2 2 σe2G = eq1 eG

(3.10)

Thus, the ADC SNDR (ignoring noise) becomes S N D R = 10 log10

PS PN

≈ 10 log10

PS σq2 + σe2G

(3.11)

where σq2 is the quantization error variance of an ideal ADC. This relates the ADC performance to the acceptable gain error in each stage. When the additional error due to gain mismatch is comparable to the quantization error of the backend ADC (i.e. σq = σG ), the SNDR drops by 3dB. The gain error eG that results in this 3dB drop is LSB 1 L S Bbackend eG = = · (3.12) L S B ST 1 G ideal L S B ST 1 where L S B, L S B ST 1 , L S Bbackend are the LSBs of the ADC, the first stage, and the backend ADC, respectively. This can be rewritten as a function of N and the ADC resolution B, such that N (3.13) eG = B 2 As the resolution of the sub-ADC and the stage inter-stage gain increase, the bound on gain error relaxes, proportionally to N . For example, Fig. 3.4a plots the impact of gain error on the SNDR of a 12b ADC (with an ideal first stage gain of G = 4 and G = 8). The theoretical calculations match the modeled behavior, and can be used to bound the gain error as a function of acceptable degradation and stage resolution. Gain error also impacts the SFDR, as in Fig. 3.4b, since it results in higher order harmonics. Depending on system specifications, this impact may impose more stringent constraints6 on gain error than that of SNDR.

6 And this may necessitate additional techniques such as dither [5].

3.1

Switched-Capacitor Topologies

45

Fig. 3.4 Impact of gain error on a SNDR and b SFDR

As seen in Eq. 3.9, capacitor mismatch results in a non-ideal gain of G=

Cs Cf

N

i=1 (1 + C e,i )

(1 + Ce, f )

= G ideal (1 + eG )

(3.14)

where G ideal = N CCsf . Assuming the errors are independently and identically distributed random variables with a zero-mean distribution and are 1, the error variance can be approximated as

σG2

= Var =

G G ideal

2 σ2 σcs cf

N

+ σc2f

1

Cs ≈ 2 Var Cf G ideal

N i=1

(1 + Ce,i )

1 − Ce, f

(3.15)

σcs 2 + N

where σcs and σc f are the normalized standard deviations of the sampling and feedback capacitor errors, respectively.

46

3 Pipelined ADC Topologies

If gain mismatch is primarily due to capacitor mismatch (as opposed to amplifier loop gain [9]), then Eq. 3.15 can be analyzed with Eq. 3.12. For example, with 1-bit redundancy, the sampling and feedback capacitors are set to C f = 2Cu and Cs = Cu , where the unit capacitor Cu has a normalized error standard deviation of σce . Thus, the normalized variances for C f and Cs are

2 σce 2

2 , respectively, resulting in a gain variance of and σce

σG2 =

4 σ2 0.5σce σce 2 N +2 2 2 + ≈ + 0.5σce σce −−−−→ ce N →∞ N N 2N 2

(3.16)

In addition, Cu = CNT , where the total sampling capacitance C T is set achieve a certain kT /C 2 = N σ 2 , where σ noise. Thus, the unit capacitor’s normalized error variance σce cT is the cT error of the total capacitance (and is constant if C T is fixed). For every doubling of N , the normalized capacitor error variance increases by 2X, and the sub-ADC quantization power decreases by 4X, such that the error power due to gain error is 2 2 eG ∝ σe2G = σq1

σ2 1 N +2 2 −−−−→ cT · N σ · cT 2 N →∞ N N N

(3.17)

This decreases with N , and the SNDR due to gain error improves by 3dB when the stage resolution increases by 1 bit, which relaxes the constraints on capacitor matching. There are other factors that can drive the choice of N (and the sub-ADC resolution) besides just gain error. Given a fixed topology, the impact of capacitor mismatch can be mitigated by several means. One approach is to sufficiently size the capacitors to reduce mismatch.7 For example, with a 1%/fF capacitor mismatch standard deviation (a ballpark estimate based on current technologies), the impact of capacitor sizing on the standard deviation of gain error can be calculated for different inter-stage gains, as in Fig. 3.5a. As expected, the standard deviation increases with G. The SNDR (due to gain mismatch8 ) can also be estimated. Figure 3.5b estimates the SNDR with a gain error of 3σG , for a 14b ADC. Here, the SNDR improves by 3dB for a given C T when G doubles, as expected from Eq. 3.17. Note that this only captures the impact of random mismatch. If systematic errors exist, such as those due to layout gradients or asymmetric coupling, the performance will further degrade. Additional approaches to mismatch mitigation include calibration [14] and trim during production test (see Chap. 7), which corrects for capacitor errors, such that the capacitors do

7 To a first order, if a capacitor C has a standard deviation of σ , then a parallel combination of u ce √ N Cu will have a standard deviation of N σce (assuming uncorrelated variations). Even though the

error has increased, √ the normalized standard deviation, which is the ratio of error to capacitor size, has decreased by N [12, 13]. This is analogous to Pelgrom’s coefficient [12] which directly ties in the mismatch to the device area (since N capacitors will have N times the area). 8 Capacitor mismatch also results in DAC linearity errors, which is not included in this plot.

3.1

Switched-Capacitor Topologies

47

Fig. 3.5 Mismatch-related impact of capacitor and stage gain on a 14b ADC. a Gain error and b estimated SNDR with 3σ gain error

not need to be sized for mismatch. Dither [5] is also a powerful technique to further randomize the systematic signatures of residual gain errors, which can reduce the magnitudes of higher order harmonics.

3.1.1.2 Impact of Capacitor Mismatch on DAC Error Equation 3.9 also captures the impact of capacitor mismatch on DAC errors. These mismatches result in additive and code-dependent errors, and the reader can explore their impact in a similar fashion as done here for gain error. The capacitor mismatch requirements are also relaxed as the stage resolution increases [15]. Calibration, trimming, dithering [5], and other techniques [16] can be used to mitigate the impact of these errors.

48

3.1.2

3 Pipelined ADC Topologies

MDAC Switch Configurations

The MDAC is configured for each phase with different sets of switches, as in Fig. 3.2. The tracking switch and overall sampling network will be discussed at length in Chap. 4. Here, other switches that are included in the MDAC are covered.

3.1.2.1 Sampling Switch During the track phase, bottom-plate sampling is implemented with a sampling switch at the amplifier inputs, as in Fig. 3.6. Due to its differential operation, there is minimal current that feeds into the Vcmi generator. The switch on-resistance, as in Fig. 3.6, creates a non-zero voltage drop across the switch due to the signal-dependent current through the sampling capacitors. This can impact signal fidelity. Increasing the switch size decreases the resistance, increases the parasitic capacitance, and increases the leakage current when this switch is off (during the redistribution phase9 ). If a transistor directly connects each amplifier input terminal to Vcmi , as Rs2 does in Fig. 3.6, the total on-resistance is Ru (3.18) RT 1 = 2Rs = 2 Ws where Ru and Ws are the resistance of a unit width transistor and the width of the transistors, respectively. To minimize capacitance and leakage for a given transistor length, the width should be kept as minimum as possible. For high input frequencies, the current through these switches, during the track phase, can be non-negligible. If the resistance is not low enough, a signal-dependent voltage will appear across the sampling switch. This resistance can be decreased with the introduction of a third switch directly between the two terminals, as in Fig. 3.6. Rs1 shorts the two terminals, and the two Rs2 switches connect the terminals to Vcmi , resulting in an on-resistance of RT 2 =

2Rs2 Rs1 2Ru = 2Rs2 + Rs1 2W1 + W2

(3.19)

where W1 and W2 are the widths of the transistors, and the total width of transistors attached to a terminal is W1 + W2 . With this configuration, the resistance reduces by Ws RT 2 = RT 1 2W1 + W2

(3.20)

Intuitively, the transistors for Rs2 can be small (to connect Vcmi to the capacitors), and the transistor for Rs1 can be the dominant transistor. This would reduce on-resistance by almost half for equivalent parasitic capacitance and leakage, which would proportionally reduce the voltage delta between the two amplifier input terminals. Alternatively, if the two 9 Charge redistribution relies on a high impedance summing junction. A leakage current provides

another path for charge, degrading charge redistribution fidelity.

3.1

Switched-Capacitor Topologies

49

Fig. 3.6 MDAC sampling switch on-resistance during track phase

configuration options have the same resistance, then the widths of the two switches can be set to W1 ≈ W2s and W2 W1 , which would result in almost half the leakage due to the reduced transistor size.

3.1.2.2 Feedback Capacitor Reset Switch During the track phase, a second set of switches in the MDAC is connected to Vcmo , as in Fig. 3.2a. In this phase, the feedback capacitors must be reset to a signal-independent charge. It is possible to reset these capacitors by simply having the amplifier output absorb the charge, as in Fig. 3.7a. However, this may result in insufficient reset. Due to the finite on-resistance of the sampling switch, the residual signal-dependent voltage drop across amplifier input terminals will impact the amplifier output, resulting in frequency-dependent reset behavior. This can impact ADC performance. Resetting the feedback capacitors via a direct connection to a Vcmo generator decouples the amplifier operation from the reset operation, as in Fig. 3.1. It is also possible to configure the switches as in Fig. 3.7b, where the feedback capacitors are also disconnected from both the amplifier input and output and are instead forced to Vcmi and Vcmo . This further improves the feedback capacitor reset. However, these additional switches do introduce a zero in the feedback path, and should be considered during the design phase.

3.1.3

Timing Configuration

Since each stage operates with two primary phases, the phases of consecutive stages can be alternated as in Fig. 3.8 (which illustrates the timing for the first three stages). For example, if stage i is in the redistribution phase, stage i + 1 is in the track phase and tracks the output of stage i. This results in a latency of N2 (before the digital output of the last stage is available). The sub-ADC outputs are generated as in Fig. 3.9a. The sub-ADC of each stage typically

50

3 Pipelined ADC Topologies

Fig. 3.7 Resetting the feedback capacitors during track phase through a the amplifier and b explicit voltages. (Ron represents the sampling switch during the track phase)

Fig. 3.8 Alternating track and redistribution phases in cascaded stages

begins its timing at the end of the track phase, with its encoder output generated at the end of the redistribution phase,10 and each stage output is consecutively offset (in time) by a half clock cycle. The output of the each sub-ADC encoder will need to be aligned with the correct outputs of the rest of the stages when they are combined, as in Fig. 3.9b. In addition, the internal timing of each stage can impact performance. In switchedcapacitor circuits, non-overlapping clocks ensures that charge is conserved and charge redistribution functions as intended. 10 Depending on speed requirements, process technology, and sub-ADC resolution, the encoder logic

may need to be pipelined, which would add additional latency.

3.2

Alternative Switched-Capacitor Topologies

51

Fig. 3.9 a Timing relationship of digital outputs of each stage, as a function of the ADC input signal and b alignment of stage outputs

Conventionally, the clock period is split almost evenly between the track and the redistribution phases (with a small portion dedicated to non-overlapping), but this is not necessary. The overall design power and performance can be improved by allocating more time for one phase versus the other [5]. Since the amplifier settling performance typically limits the overall speed, it is possible to explore increasing the redistribution time at the expense of track time. This can improve other metrics, such as metastability and code error rate (as discussed in Chap. 5). It is up to the designer to understand where the critical bottlenecks are in their design, and to veer from convention in order to improve the target metrics.

3.2

Alternative Switched-Capacitor Topologies

The topology discussed in the majority of this chapter is a classical switched-capacitor topology, where the sampling capacitors and feedback capacitors are separate. Alternative configurations are possible, and may be preferred for various reasons. For example, the feedback factor of the amplifier in the configuration of Fig. 3.1 is β=

Cf 2 < N Cs + C f + C par N +2

(3.21)

where C par is the parasitic capacitor at the amplifier input, and C f = 2Cs . The feedback factor β impacts the closed-loop bandwidth and gain, affecting both the achievable sample rate and the gain error (due to the finite amplifier gain). Thus, it is beneficial to maximize β when possible. Additionally, in this configuration, the same capacitors are used for both sampling the input and for the residue generation (via the reference voltages). As discussed in Chaps. 4 and 6, this can result in performance degradation. These can be addressed by different topologies, as discussed below.

52

3.2.1

3 Pipelined ADC Topologies

Flip-Around Topology

A flip-around topology [15] can achieve a similar residue generation functionality as the topology of Fig. 3.1. This operates by “flipping around” some of the sampling capacitors, such that they become feedback capacitors. Figure 3.10 is an example implementation, where there are only N unit capacitors on each differential side. During the track phase, all of these N capacitors sample the stage input, and there are no explicit feedback capacitors that are reset during this phase. During the redistribution phase, some of the sampling capacitors (Cs < 1 : 0 > in Fig. 3.10) switch into feedback capacitors (and are connected between the input and output of the amplifiers). If two of the N sampling capacitors flip into feedback capacitors, the differential output voltage is N 2D − (N − 2) vid − V R (3.22) vod = 2 N Thus, the gain is N /2, with N − 2 transitions. With G = 4 (and N = 8), the residue is as in Fig. 3.11. In addition to potential area savings due to the reduced number of capacitors, the primary benefit is the improved feedback factor, which changes to β=

2 2Cs < N Cs + C par N

Fig. 3.10 MDAC with flip-around configuration. Phases not illustrated

(3.23)

3.2

Alternative Switched-Capacitor Topologies

53

Fig. 3.11 Residue plot for flip-around topology

This has almost an NN+2 improvement compared to Eq. 3.21, and can have measurable impact on performance, especially when N is small.

3.2.2

Separate DAC Capacitors

For reasons that will be elaborated on in Chaps. 4 and 6, it is not always preferable to have the sampling capacitors also operate as the DAC capacitors. Separating these is possible [17], as in Fig. 3.12. During the track phase, the sampling capacitors, Cs , connect to the input signal. The DAC capacitors, Cr , are reset to a common-mode voltage. During redistribution phase, the sampling capacitors are connected to a common-mode voltage, and the DAC capacitors are then connected to the respective reference voltage as a function of the sub-ADC output. This results in the required charge redistribution, such that the differential output is 2D − N N vod = vid − V R (3.24) 2 N C

where Cs = Cr = 2f . This has an identical transfer function to the first topology we analyzed. Although this topology has benefits, a significant drawback is the reduced feedback factor, where Cf 2 < (3.25) β= 2N Cs + C f + C par 2N + 2 which can have a substantial impact on amplifier performance and power. These are two examples of different MDAC topologies. Depending on the design requirements and design challenges of each stage in an ADC, it is possible to use one topology for one stage and another for the next. It is worth the reader’s time to investigate these with

54

3 Pipelined ADC Topologies

Fig. 3.12 MDAC with separate DAC capacitors

analysis and simulations, in order to gain a deeper understanding of the various tradeoffs and their impact on pipelined ADCs.

References 1. Temes GC, Moon U-K, Allstot D (2021) Switched-capacitor circuits [education]. IEEE Circuits Syst Mag 21(4):40–42 2. El-Chammas M, Li X, Kimura S, Maclean K, Hu J, Weaver M, Gindlesperger M, Kaylor S, Payne R, Sestok CK, Bright W (2014) A 12 bit 1.6 GS/s BICMOS 2×2 hierarchical time-interleaved pipeline ADC. IEEE J Solid-State Circuits 49(9):1876–1885 3. Payne R, Corsi M, Smith D, Kaylor S, Hsieh T (2010) A 16-Bit 100–160 MS/s SiGe BiCMOS Pipelined ADC With 100 dBFS SFDR. IEEE J Solid-State Circuits 45:2613–2622 4. Payne R, Sestok C, Bright W, El-Chammas M, Corsi M, Smith D, Tal N (2011) A 12b 1GS/s SiGe BiCMOS two-way time-interleaved pipeline ADC. In: 2011 IEEE international solid-state circuits conference digest of technical papers (ISSCC), pp 182–184 5. El-Chammas M, Li X, Kimura S, Coulon J, Hu J, Smith D, Landman P, Weaver M (2015) 15.8 90dB-SFDR 14b 500MS/S BICMOS switched-current pipelined ADC. In: 2015 IEEE international solid-state circuits conference—(ISSCC) digest of technical papers, pp 1–3 6. Poulton K, Neff R, Muto A, Liu W, Burstein A, Heshami M (2002) A 4 Gsample/s 8b ADC in 0.35/spl μ/m CMOS. In: 2002 IEEE international solid-state circuits conference. Digest of technical papers (Cat. No. 02CH37315), vol 1, pp 166–457 7. Poulton K, Neff R, Setterberg B, Wuppermann B, Kopley T, Jewett R, Pernillo J, Tan C, Montijo A (2003) A 20 GS/s 8 b ADC with a 1 MB Memory in 0.18 μm CMOS. In: 2003 IEEE international solid-state circuits conference digest of technical papers (ISSCC), vol 1, pp 318–496 8. McCreary J (1981) Matching properties, and voltage and temperature dependence of MOS capacitors. IEEE J Solid-State Circuits 16(6):608–616 9. Murmann B, Boser B (2003) A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification. IEEE J Solid-State Circuits 38(12):2040–2050

References

55

10. Iroaga E, Murmann B (2007) A 12-bit 75-MS/s pipelined ADC using incomplete settling. IEEE J Solid-State Circuits 42(4):748–756 11. Choksi O, Carley L (2003) Analysis of switched-capacitor common-mode feedback circuit. IEEE Trans Circuits Syst II: Analog Digit Signal Process 50(12):906–917 12. Pelgrom M, Duinmaijer A, Welbers A (1989) Matching properties of MOS transistors. IEEE J Solid-State Circuits 24:1433–1439 13. Omran H, Alahmadi H, Salama KN (2016) Matching properties of femtofarad and sub-femtofarad mom capacitors. IEEE Trans Circuits Syst I Regul Pap 63(6):763–772 14. Karanicolas A, Lee H, Bacrania K (1993) A 15 b 1 MS/s digitally self-calibrated pipeline ADC. In: 1993 IEEE international solid-state circuits conference digest of technical papers, pp 60–61 15. Yang W, Kelly D, Mehr L, Sayuk M, Singer L (2001) A 3–V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist input. IEEE J Solid-State Circuits 36(12):1931–1936 16. Galton I (2000) Digital cancellation of D/A converter noise in pipelined A/D converters. IEEE Trans Circuits Syst II: Analog Digit Signal Process 47(3):185–196 17. Devarajan S, Singer L, Kelly D, Pan T, Silva J, Brunsilius J, Rey-Losada D, Murden F, Speir C, Bray J, Otte E, Rakuljic N, Brown P, Weigandt T, Yu Q, Paterson D, Petersen C, Gealow J, Manganaro G (2017) A 12-b 10-GS/s interleaved pipeline ADC in 28-nm CMOS technology. IEEE J Solid-State Circuits 52(12):3204–3218

4

Frontend Sampling Networks

High-speed and high-performance ADCs require high-linearity frontends that interface with the input analog signal and convert it into a signal that the rest of the ADC signal chain can use. The exact topology of the frontend depends on the pipelined ADC architecture and on overall target specifications, such as SFDR, SNR, bandwidth, and power. However, there are several common components, as illustrated in Fig. 4.1, such as the input termination, input buffer, and sampling switch and capacitor. Myriad variations of Fig. 4.1 are possible. For example, bottom-plate and top-plate sampling switches [1] are both potential options. The input termination can include various bandwidth-enhancing circuit elements. The frontend sampling structure can be implemented as standalone (similar to Fig. 4.1) [1, 2], integrated as part of the pipeline MDAC [3] (as discussed in Chap. 3), or even as part of a separate switched-capacitor amplifier [4]. It can include a separate sampling network for the sub-ADC, or have the sub-ADC connected to the output of the track-and-hold [1, 5]. These decisions are made as part of the architectural analysis based on the target specifications and the resulting ADC design space.

4.1

Frontend Input Buffer

The frontend input buffer is an important component of the signal chain (although not always a necessary one, as discussed later in this chapter). From an application perspective, it simplifies integration as it provides a more constant input impedance,1 which eases constraints 1 There is still periodic behavior at the input due to the sampling circuit following the buffer. Though

the input buffer attenuates this effect, the residual energy may still cause issues. One example of this (input kickback) is discussed later in this chapter. © The Author(s), under exclusive license to Springer Nature Switzerland AG 2023 M. El-Chammas, High-Performance and High-Speed Pipelined ADCs, Synthesis Lectures on Engineering, Science, and Technology, https://doi.org/10.1007/978-3-031-29700-7_4

57

58

4 Frontend Sampling Networks

Fig. 4.1 Simplified frontend sampling network

on the driving circuit. If the input buffer is not included, the system engineer must ensure that the driving circuit has sufficient drive strength for the time-varying behavior of the frontend track-and-hold. An input buffer helps reduce dependency on the behavior of the driving circuits, and is typically included in most high-speed and high-performance ADCs. The input buffer in Fig. 4.1 drives a sampling circuit. Regardless of the actual implementation of the sampling circuit, the input buffer must still charge and discharge the capacitors as a function of the input signal, and it directly impacts ADC performance. It sees a continuoustime large swing input signal, and must be designed to achieve the required specifications with both large and small signal swings. The rest of this section discusses the input buffer in more detail.

4.1.1

Design Factors

This section details several factors affecting the input buffer design [6] that can directly impact ADC performance.

4.1.1.1 Sizing the Sampling Capacitor With a sampling capacitor of Cs (as in Fig. 4.1), the variance of the integrated noise [7] (excluding the buffer2 ) is kT vn2 = (4.1) Cs In a differential implementation, the total sampled noise is 2vn2 . With a differential input signal peak-to-peak voltage of V pp , the SNR with a full-scale sine wave is S N R = 10 log10

PS PN

⎛ ⎜ = 10 log10 ⎝

1 2

⎞

V pp 2 2 ⎟ ⎠ 2kT Cs

= 10 log10

2 Cs V pp

16kT

2 If the input buffer is included in the analysis, the total integrated noise will increase.

(4.2)

4.1

Frontend Input Buffer

59

Fig. 4.2 Input buffer impedance during track mode

Every 2X increase in sampling capacitance halves the noise variance and improves the SNR by 3dB. This requires an increased drive strength of the buffer (and thus, increases the power3 ).

4.1.1.2 Output Bandwidth The input buffer must effectively drive the sampling capacitor in both a continuous-time and a discrete-time fashion. The sampling switch on-resistance and the buffer output impedance are as in Fig. 4.2. When the sampling switch is on, a first-order transfer function is 1 VOU T = VI N 1 + sτ

(4.3)

The time constant in Eq. 4.3 is τ = Cs (R B + R SW ), where R B and R SW are the buffer output impedance and the switch on-resistance, respectively. The larger the capacitor (sized for thermal noise reasons), the smaller the input buffer output impedance and switch resistance need to be in order to achieve a target bandwidth. Bandwidth specifications are driven by system level requirements on signal fidelity, and are especially important for wideband signals. For example, communication systems require certain error vector magnitude (EVM) targets, which can degrade with frequency dependent gain and phase variations. The impact of a finite bandwidth on a wideband signal as compared to an infinite bandwidth can be captured with a mean-square error calculation [8]. For example, assume a 1 GHz bandwidth signal with a constant spectral density from 0 to 1 GHz. Figure 4.3a plots the resulting power spectral density across this frequency range, for different frontend bandwidths. Since finite bandwidth results in a frequency-dependent error in the output signal when compared to the input, the minimum mean-square error can be extracted with a best-fit signal. Figure 4.3b plots the residual frequency dependent mean-square error, and depicts the resulting signal-to-distortion ratio (SDR) over the full input frequency range. These frequency-dependent variations can impact application specific metrics, and must be managed either by design or compensated for with some form of correction. 3 The input buffer must be able to charge the increased capacitance at the same speed, and must also be able to drive the equivalent resistance of the sampling capacitor, which is C 1F . s S

60

4 Frontend Sampling Networks

Fig. 4.3 a Buffer transfer function and b Best-fit mean square error (normalized to the signal power) for an input signal spanning 1 GHz

Thus, the input buffer, given the load capacitance it drives, must be designed to achieve the target bandwidth, which will have implications on topology and power.

4.1.1.3 Signal-Dependent Current During Track Phase Since the buffer directly drives a capacitor, an additional continuous-time factor that must be considered is the signal-dependent current the buffer must tolerate. Assuming a sine wave input with frequency f in and amplitude A, the current Ic through the capacitor Cs is Ic = C s

dV = 2π f in Cs A cos(2π f in t) dt

(4.4)

For a given signal amplitude and capacitor load, the current increases with input frequency. This introduces frequency dependent distortion in the input buffer during the track phase, and the buffer must be designed accordingly.

4.1

Frontend Input Buffer

61

4.1.1.4 Slewing Limitations of Input Buffer Although the input buffer sees a continuous-time signal, the sampling network has alternating periodic states. As a result, the impedance the buffer drives is time-varying, as a direct function of each of the track and hold phases, as in Fig. 4.4. During the track phase (Fig. 4.4a), the buffer drives the network including the sampling capacitor, whereas when the switch is open in the hold phase (Fig. 4.4b), it only drives the parasitic capacitance C P . This time-varying load can be reflected into the input of the buffer via impedance transformations, and thus the design stage should consider this either via analysis or simulations. Additionally, as the sampling network transitions from hold to the track phase, the input buffer must simultaneously absorb the capacitor charge already stored in the hold phase, and charge the capacitor to its current input voltage. Since the input buffer has a finite bias current, it may enter the slewing region before it transitions to the linear region. When slewing, the current required to generate the voltage difference V in time t, assuming static voltages, is V I = Cs (4.5) t Figure 4.5 illustrates the tradeoff between these parameters by normalizing the current to the sampling capacitor. For example, with 1pF capacitance, a 0.4V voltage step, and a 1GHz sampling clock (such that the track time is 500ps), the buffer must be able to provide at least 1mA of current. The time required to slew sets a lower bound on the input buffer current. However, the target is tighter than this. The input buffer tracks a dynamic signal, and if it were completely slew limited, it would introduce significant distortion. Even if it were not slew limited, the available time for linear settling is now signal dependent, and the buffer needs to quickly transition from the slewing region to the linear region to reduce this dependency. Reducing the slew time requires an increase in the input buffer current, as plotted in Fig. 4.5.

Fig. 4.4 Sampling network a track phase and b hold phase

62

4 Frontend Sampling Networks

Fig. 4.5 Required current per unit pF sampling capacitor for target slew rate

4.1.1.5 Input Buffer Kickback Since the source impedance is non-zero, the time-dependent behavior of the input buffer can disturb the input signal. One cause of this is the input-output coupling capacitor Cc , as illustrated in Fig. 4.6. If the bandwidth is not high enough, then the output voltage changes at a different rate than the input voltage. The resulting current through the coupling capacitor results in a voltage differential across the source impedance Rs , disrupting the input. However, if the bandwidth of the input buffer is large enough, such that Vout ( f ) ≈ Vin ( f ), then this parasitic capacitor is almost bootstrapped away during the track phase (even without exact equality, the Miller capacitance is much smaller than the actual capacitor). The primary disturbance, however, is due to kickback, with the transition from the hold phase to the track phase. For simplicity, assume slewing has been designed to be small enough such that the buffer output almost immediately reaches the correct voltage level once the frontend transitions from hold to track, as in Fig. 4.7a. During the rest of the track phase, the output perfectly follows the input. This transition results in large voltage steps, as illustrated in Fig. 4.7b, which injects a current into the input, and creates a response due to the finite source impedance. Since most impedances have an RLC component at the input of ADC (due to elements such as routing

Fig. 4.6 Capacitance between input and output of input buffer

4.1

Frontend Input Buffer

63

Fig. 4.7 Transition from hold phase to track phase. a Input and output waveforms and b change in output voltage

parasitics, bondwires, board routing, etc.), a typical impulse response of the input source impedance is as in Fig. 4.8a, and the resulting buffer output voltage is illustrated in Fig. 4.8b. The signal seen by the input buffer now has an additional element to it, as a direct impact of kickback, such that vin,bu f f er (t) = vin,ideal (t) + h k (t) ∗ vo (t)

(4.6)

The second component is a function of the impulse response h k (t) and of output voltage step vo . This kickback decays during the track phase, and the residual kickback is a function of the voltage step, the source impedance related impulse response, and the sampling period [1]. For a fixed sample rate, there are limited options available to reduce kickback. The impulse response h k (t) can be changed by either reducing the time constant of the source impedance (thus, narrowing the impulse response), or reducing the kickback magnitude. This must be factored into either the input buffer design or the frontend architecture, and may even necessitate additional calibration algorithms [9].

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4 Frontend Sampling Networks

Fig. 4.8 a Source impedance impulse response and b impact on input waveform

One may argue that the residual kickback is not an issue, since in this example, the output of the buffer is still a sum of two sine waves (which is still a sine wave). Thus, kickback does not introduce distortion. However, there are several factors to consider. First, having a memory of past samples in your current sample leads directly to inter-symbol interference (which can be problematic in multiple systems and applications, such as in communication systems). Second, real input buffers may enter a slewing region, which will introduce a distortion factor into the kickback current (and thus, into the input signal). Finally, in the example used above, the held voltage is a linear function of the sampled signal. In MDACs (discussed in Chap. 3), this is not the case. To illustrate this, a simplified MDAC structure is shown in Fig. 4.9. During track phase, as in Fig. 4.9a, the charge on the sampling capacitor is a function of the input. During the hold phase, the charge on the capacitor is a function of the sub-ADC output D1 , as in Fig. 4.9b. f (D1 ) is a quantized version of the input signal, where the quantization error is dependent on the resolution of the sub-ADC, as discussed in Chap. 2. When the MDAC then transitions from hold to track, the voltage step is now a function of the input signal and of f (D1 ). Equation 4.6 contains a heavily quantized component (i.e.

4.1

Frontend Input Buffer

65

Fig. 4.9 MDAC configuration during a track phase and b hold phase

a nonlinear function) of the previous sample, and with insufficient kickback decay, the ADC performance will be impacted due to the residual nonlinearity. This can be demonstrated with an ideal pipelined ADC (with a 3-bit sub-ADC in the first stage) and a sine wave input signal. The residual error is a function of the kickback impulse response, and thus the tracking linearity is a function of time. Figure 4.10a plots the eye diagram of the residual kickback as a function of time (normalized to a fraction of the impulse response time constant). Since the voltage step in this model is instantaneous (i.e. no slewing and infinite bandwidth) and the impulse response is due to an ideal RLC model, the kickback crosses zero at the same instant4 multiple times in the eye diagram of Fig. 4.10a. The residual error at these time points is zero, resulting in a high SFDR value. In between these points, the SFDR drops as a function of the residual error, as in Fig. 4.10b. This illustrates the sample rate dependent behavior of kickback.5 4 In reality, the zero-crossing point will be different as a function of the input signal, but it does follow

a similar pattern with peaks and troughs, as a function of the ADC track time and sample rate. 5 Kickback should be considered early in the design phase, to ensure that it will not limit performance.

Its impact can influence the choice of topology and may require various solutions [5, 9, 10].

66

4 Frontend Sampling Networks

Fig. 4.10 Impact of kickback on SFDR with conventional MDAC configuration, as a function of increasing track time. a Eye diagram of kickback response and b SFDR as a function of track time. In this example, a 64-point sine wave was used

Input buffers are useful in attenuating the impact of kickback, but may still be insufficient, and two cascaded buffers may be required. Figure 4.11 illustrates these two scenarios. The initial kickback magnitude at the input node is reduced as a function of the number of buffers, which mitigates its impact. Kickback is revisited at the end of this chapter, in Sect. 4.5, for ADCs that do not include an input buffer in their frontend network.

4.2

Input Buffer Implementations

67

Fig. 4.11 Attenuated kickback with a one input buffer and b two input buffers

4.2

Input Buffer Implementations

The discussion in the previous section apply to input buffers in general and can influence the choice of topology. There are various approaches to ADC input buffers, depending the performance requirements. However, in almost all high-performance and high-speed pipelined ADCs, there are a limited number of options that are typically used. This section focuses on the voltage follower (both emitter and source followers), and some variations thereof. The efficiency, simplicity, and robustness of the voltage follower makes this circuit a leading contender for most ADCs. Though this book touches little on transistor-level noise considerations due to the abundance of literature on the topic, the input buffer is directly in the signal path, and thus its noise contributions (and implications on performance) must be considered by the ADC designer. In this section, the emitter follower is the discussed first. Although high performance bipolar technology is currently less common than a primarily CMOS technology, it is still a technology that has recently been used in high-linearity ADC design [2]. In addition, bipolar technology provides an analytic elegance that is sometimes difficult to replicate with CMOS technologies, allowing for deeper foundational and intuitive understandings. The section will then transition into source followers and its derivatives, which are the more common choices in modern pipelined ADCs.

68

4.2.1

4 Frontend Sampling Networks

The Emitter Follower

Figure 4.12 depicts an emitter follower configured with an NPN transistor and an ideal current source I B . During the track phase, the input buffer drives a capacitor load through a sampling switch, such that Vout = GVin − VB E , where VB E is the base-emitter voltage, and G is the emitter follower gain. Several small signal properties such as output impedance, bandwidth, and gain can be approximately derived. The output impedance of the emitter follower is Rout ≈

1 VT ≈ gm IB

(4.7)

where VT = kT /q, and where gm is the transconductance of the NPN in Fig. 4.12. The bandwidth of the emitter follower (ignoring the on-resistance of the sampling switch) is ω3d B =

1 Rout C T

≈

gm CS + C P

(4.8)

where C S is the sampling capacitor, C P is some parasitic capacitance (not shown in Fig. 4.12), and C T = C S + C P . The gain of the emitter follower is Av ≈

gm r o gm r o + 1

(4.9)

where the output impedance of the NPN transistor, ro , is a function of the early voltage. In practical high performance NPNs, Av ≈ 1 [1].

Fig. 4.12 Emitter follower input buffer with ideal bias current, driving a capacitor load

4.2

Input Buffer Implementations

69

These simplified derivations provide sufficient initial design guidance and insight into design tradeoffs. More rigorous small-signal analysis [11–13] on the emitter follower can be performed.6

4.2.1.1 Large Signal Impact on Linearity These small-signal properties are useful in quickly analyzing the impact of the input buffer on various ADC related specifications, but are not sufficient to properly design the emitter follower. Since this circuit sees large signal swings, additional constraints are required. For example, as previously discussed in Sect. 4.1.1.4, slewing can impact distortion. Depending on the required slew time, a minimum bias current is required. More practically, the emitter follower biasing can be optimized for the combination of slewing and linear settling. Large signal swings also result in both static and dynamic nonlinearities. A finite early voltage V A [16] in the NPN transistor can impact nonlinearity [17], since the current VB E VC E I E = α Is e VT 1 + (4.10) VA is a function of the voltage drop across the base-emitter junction (VB E ) and the collectoremitter junction (VC E ). With the collector connected to the supply, as in Fig. 4.12, VC E is signal-dependent, which modulates VB E since the bias current is constant. Therefore, the output of the emitter follower, which should directly follow the input, actually includes a nonlinear component with Vout = VE ≈ Vin − VB E (Vin )

(4.11)

In a pseudo-differential input buffer, these harmonics are dominated by the third harmonic. Fortunately, in high performance bipolar technologies, the early voltage is large enough such that it is possible to achieve over 90dB SFDR with an emitter follower [2, 18]. This is not often the case with a CMOS source follower, as discussed in Sect. 4.2.2. A more pressing issue in emitter followers is that the bias current is non-ideal. The finite output impedance of the current source in an emitter follower introduces a signal-dependent bias current, which also modulates the VB E of the NPN transistor. For most applications, high linearity requirements dictate a cascoded current source, which shields the current mirror from the large signal swing and increases its effective output impedance. Several flavors of this are illustrated in Fig. 4.13.

6 For example, an inductive component appears at the input of the emitter follower. Depending on

what is driving the emitter follower, ringing may be possible as a function of the various parameters of the emitter follower (such as gm , the base resistance rb , etc.) [14, 15], and should be optimized.

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4 Frontend Sampling Networks

Fig. 4.13 Emitter follower with different current mirrors. a Resistor degenerated NPN current mirror b NMOS current mirror cascoded with an NPN transistor or c with an NMOS transistor

The exact choice of the current mirror will depend on various design requirements, and the reader will be able to deduce the best options for their scenario.7 Various tradeoffs between the different options exist, such as impact on mismatch [19], noise, and signal headroom.

4.2.1.2 Frequency Dependent Linearity Dynamic nonlinearities introduce a frequency dependent distortion component. Several contributors to this include slewing, input kickback, and nonlinear transistor capacitances, some of which have been discussed earlier. An additional source of dynamic nonlinearity is due to the sampling capacitor, even if the capacitor itself is an ideal component, as is discussed here. Emitter followers are typically biased with a constant current, I B , as in Fig. 4.12. However, the emitter follower drives a capacitor. This introduces a signal-dependent current (as in Eq. 4.4) that superimposes on the constant bias current due to Kirchhoff’s Current Law (KCL), such that the emitter current is I E = I B + IC . Thus, the base-emitter voltage (ignoring the early voltage and the finite current mirror output impedance) becomes I B + IC (4.12) VB E ≈ VT ln Is 7 For example, a three-transistor NMOS stack was used in [2] for the required signal swing and

linearity targets.

4.2

Input Buffer Implementations

71

The current through the capacitor, IC = Cd V /dt, is signal-dependent (and increases with frequency), and the expression for VB E can simplified with a Taylor series expansion into IB IC + ln 1 + VB E ≈ VT ln IS IB 2 (4.13) IB IC 1 IC 1 IC 3 + − + ≈ VT ln IS IB 2 IB 3 IB where IC /I B < 1. With a differential input signal, the differential emitter follower output is IC 1 IC 3 (4.14) + Vo = Vop − Von ≈ Vin − 2VT IB 3 IB This introduces third order distortion due to the signal harmonic. An alternate approach to viewing this distortion is discussed in [20], where the distortion is derived through the small-signal parameter gm , which now becomes signal-dependent due to IC . This modulates the input buffer gain. If Vin is a sinusoidal signal with frequency f in and amplitude A, then Eq. 4.14 can be used to estimate the resulting SFDR, such that

I B3 (4.15) S F D Rd B ≈ 20 log10 2 VT (2π f in Cs )3 A2 As a result of this dynamic current, the SFDR deteriorates with larger sampling capacitors, larger amplitudes, and larger input frequencies, as reflected in Eq. 4.15. Figure 4.14 plots the SFDR as a function of input frequency, for this dynamic nonlinearity (other static nonlinearities are not included), both using the large signal model for an NPN transistor, and using the SFDR estimate of Eq. 4.15. In Fig. 4.14, the bias current I B doubles with each curve. The estimate of Eq. 4.15 starts to diverge for low SFDR values, since some of the approximations are less valid as IC /I B increases (especially as IC /I B → 1). Without additional topology changes, the primary option to improve SFDR at higher input frequencies is to increase the bias current I B , which decreases the current ratio IC /I B .

4.2.1.3 Design Techniques for Improved Performance In a well-designed emitter follower, dynamic nonlinearities dominate at higher input frequencies. Design techniques for static nonlinearities8 will be revisited later with the source follower. This section focuses on the dynamic nonlinearity due to the capacitor current IC .

8 Some artifacts may pose problems as a function of the architecture and system-level specifications,

and do need to be addressed. For example, in [1], temperature-dependent emitter follower gain was addressed to ensure calibration-free linearity targets were met.

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Fig. 4.14 Impact of frequency on emitter follower due to current through a 1pF sampling capacitor and an FSR = 2, for different bias currents

The ratio of IC /I B increases with input frequency, adversely impacting the input buffer linearity, as in Eq. 4.14. Simply increasing the bias current (to reduce the IC /I B ratio) can address this, but leads to excessive power consumption, as plotted in Fig. 4.14. Digital calibration of this frequency dependent nonlinearity is also possible, but nontrivial to implement [21]. This signal and frequency dependent distortion can be compensated for with an elegant solution [17, 20]. A replica current IC R can be introduced such that the current through the emitter is (4.16) I E = I B + IC − IC R The distortion is canceled when IC R = IC , and Fig. 4.15 illustrates an implementation of the replica current IC R . The node VC in the cascoded current mirror is ideally held to an almost DC voltage (cascoding attenuates the impact of the signal VOU T on the node VC ). A capacitor connects from the input to VC , such that it sees a swing of VI N − VC . Since VC is almost a DC voltage, the current through the replica capacitor C R is IC R ≈ C R

d VI N dt

(4.17)

such that the current through the NPN is IE ≈ IB + CS

d VOU T d VI N d VI N − CR ≈ I B + (C S − C R ) dt dt dt

(4.18)

Theoretically, the emitter current can be made almost signal-independent if C S = C R . Therefore, VB E modulation can be reduced by generating a current through a replica capacitor, as a function of the input voltage, and then injecting this current back into the emitter follower.

4.2

Input Buffer Implementations

73

Fig. 4.15 Using a replica capacitor to reduce signal-dependent current

For various reasons, perfect cancellation cannot be achieved, and these residual imperfections impact performance as the input frequency increases. For example, VOU T = VI N due to a frequency dependent relationship. In addition, the signal-dependent current goes through the current mirror’s cascode transistor, modulating VC (this in turn changes the current through C R and the bias current I B as a function of VC and the output impedance). The parasitic capacitance at VC , a function of the capacitor C R in addition to the transistors and routing at VC , also impacts the efficiency of this solution. These imperfections and their impact can be analyzed as part of the design process. Some of these issues can be addressed with better cascoded structures (such as a 3stack structure [2], for example). Some can be optimized by design, but will still limit the correction at higher frequencies. Finally, two important drawbacks of this approach are that 1) the introduction of C R reduces the input bandwidth and 2) the introduction of larger parasitic capacitors at the VC node can increase the noise contributions of the cascode transistor at higher frequencies (thus impacting SNR). These are some of the tradeoffs the designer will need to optimize for. Additional modifications are also possible, such as introducing a replica buffer [17] that can directly drive C R , instead of driving it with the input signal, adding resistors to the replica path to potentially balance phase differences, or using a gain-boosting amplifier to reduce the VC modulation. However, these can result in additional design complexities.

4.2.2

The Source Follower

The emitter follower has superior gm efficiency when compared to source followers. Furthermore, in specialized processes, the transit frequency of bipolar transistors can be extremely high. However, these processes are not commonly available, and therefore most ADCs

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Fig. 4.16 Source follower input buffer with ideal bias current

are currently designed in a CMOS process, with some exceptions in a BiCMOS process [1, 2, 18, 22]. An example of an NMOS source follower is illustrated in Fig. 4.16. Some of the issues discussed with the emitter follower are applicable to source followers. For example, the drain-source voltage VDS modulation impacts static nonlinearity due to the finite output impedance of the input NMOS and leads to significant performance degradation with large signal swings [23]. In addition, the dynamic nonlinearity due to the current through the sampling capacitor also modulates VG S , and a similar solution, as discussed in Sect. 4.2.1.3, can be used. There are also additional factors that degrade the performance of a source follower, such as the signal-dependency of the threshold voltage VT due to a non-constant VS B (if the body is connected to ground), which further modulates VG S .

4.2.2.1 Design Techniques for Improved Source Follower Performance The finite (and nonlinear) output impedance, and the body effect of the source follower input transistor, can limit its performance to less than 70 dB SFDR, depending on magnitude of the input swing. Although careful design can improve this, it is extremely challenging to achieve high linearity for typical signal swings across corners. Design techniques to improve the output impedance and reduce the effect of body bias (and thus, increasing linearity) are usually required. If the process includes a deep n-well, then the signal-dependent behavior of VS B is addressed by either shorting the body to the source (i.e. the output), as in Fig. 4.17a, or by using a replica buffer to drive the body, as in Fig. 4.17b. Connecting the body to the source is the simpler option, and this typically will address the issue. However, there may be situations where the extra capacitance on the output due to this connection will introduce unwanted design constraints. In such situations, a replica buffer as in Fig. 4.17b can be used, since the main buffer and the replica buffer can be individually optimized for their respective roles,

4.2

Input Buffer Implementations

75

Fig. 4.17 Addressing body bias modulation with a direction connection of body to source and b using a replica buffer to drive the body

but will also introduce other artifacts (e.g. the phase difference between the two buffers) that can impact performance. VDS modulation also impacts linearity. This can be mitigated by controlling the drain voltage to reduce the signal component of VDS . This is typically implemented by replicating the input voltage onto the drain voltage, effectively “bootstrapping” the transistor’s VG D (and equivalently, VDS , since this is a source follower with a gain close to 1). Several implementations are illustrated in Fig. 4.18. In Fig. 4.18a, M2 drives the drain of M1 and is biased with I B . Although this improves linearity without an increase in current, it does require M2 to have a smaller VG S than M1 (so that M1 remains in saturation). Thus, M2 must have a larger width and/or smaller length (or can designed with lower threshold device), and will likely reduce bandwidth due to the larger input capacitance. Additionally, it may require a higher supply voltage (which would then impact power) so that M2 also has sufficient headroom. The increased size of M2 can be addressed by introducing some level shifting to its input [24], as in Fig. 4.18b. This approach introduces a high-pass filter response between the input and the gate of M2. At DC, M2 does not see the input signal, and thus the VDS of M1 is still signal dependent. However, for large enough frequencies (as a function of the 3dB bandwidth of the high-pass filter), the gate of M2 is a level-shifted version of the input. For many high-frequency data converters, where low input frequencies are not important, this is sufficient. As with Fig. 4.18a, an increased supply may be required. This level-shifting can also be implemented with a switched-capacitor network [9].

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Fig. 4.18 Options to reduce V DS modulation in source followers

Figure 4.18c illustrates another level-shifting approach, with the use of a PMOS source follower. This requires an extra bias current and may also require additional supply headroom. However, it can decouple the size of M2 from the input, and be modified such that the PMOS source follower buffers the source (VOU T ) of M1 instead of VI N (as long as M1 stays in saturation), such that the input is not loaded by this additional buffer. Finally, Fig. 4.18d illustrates yet another approach. The PMOS transistor directly drives the drain of M1, and an additional bias current is required to both absorb I B and to bias the PMOS transistor. Supply headroom is an issue in this configuration. Furthermore, since the drain of M1 is directly biased, the slewing behavior of the source follower is further impacted, which can impact performance and power dissipation. A slight reconfiguration of Fig. 4.18d leads to a super-source follower topology, which the reader can also explore. Other topologies that reduce the VDS modulation are possible. It is recommended the reader explore these configurations, with various target specifications and frequency ranges, in order to gain a more intuitive understanding of the different tradeoffs and complexities.

4.2.3

Alternative Input Buffer Implementations

Both the emitter follower and the source follower are common input buffer implementations for high-performance ADCs. They have relatively simple structures (even though the actual design requires diligence), and they typically can achieve high bandwidth and linearity if designed well. However, depending on various architecture needs and technology parameters, alternate options may bring additional benefits. For example, push-pull architectures can improve the output impedance (by almost doubling the effective gm with little overhead in power). These options will not be discussed in more detail in this book, but have appeared in various designs [3, 25, 26].

4.3

Sampling Switches

4.3

77

Sampling Switches

As depicted in Fig. 4.1, the input buffer drives the sampling network. The sampling switch sees a large and high frequency signal, and impacts ADC performance. Some of the artifacts it introduces are the voltage-dependent switch resistance that affects tracking linearity [27], nonlinearities during transitions between the track and hold phases (such as due to input kickback and charge injection [28]), and any feedthrough or leakage during the hold phase [2]. This section focuses on distortion during the track phase.

4.3.1

Track Phase Distortion

Since the sampling switch is directly in the signal path, it introduces distortion during the track phase. A significant contributor of this is the on-resistance of the sampling switch [27, 28]. The signal-dependent bandwidth of the switch (which impacts its amplitude and phase response) generates distortion that affects the ADC performance, and its on-resistance must either be sized such that the resulting RC time constant is significantly smaller than the track time or be sufficiently linearized. Both approaches limit the signal-dependent bandwidth modulation (as a fraction of the sampling network bandwidth), as also illustrated by a Volterra series analysis [27]. In high-speed ADCs designed for a high input signal frequency, simply increasing the switch size is unrealistic. Although the on-resistance does reduce proportionally to the switch width, its capacitance increases, which introduces a lower-bound to the achievable time-constant. In addition, the switch capacitances include nonlinear components due to the transistor junctions, which adversely affect signal quality during the track phase. In a topplate sampling topology, signal-dependent charge injection also increases, further distorting the signal when the switch transitions from track to hold.9 Instead, high-performance and high-speed ADCs typically linearize the on-resistance in order to achieve the required linearity specifications. The standard solution to this is bootstrapping [29, 30], which allows the switch to be reasonably sized. Bootstrapping also reduces the signal-dependency of both charge injection and the track-to-hold transition. Though there have been multiple implementations of a bootstrap circuit, a common one is the Abo bootstrap (illustrated in Fig. 4.19), which has been included in numerous designs. In Fig. 4.19, the primary sampling switch is denoted with the dashed circle. The sampling switch on-resistance is a strong function of the gate-source voltage, and bootstrapping the sampling switch addresses this by setting the gate-source voltage to a constant voltage. A precharged capacitor C B can be used to add a DC voltage to the input

9 This is one of the benefits of bottom-plate sampling, where the charge injection is primarily constant.

In certain architectures, top-plate sampling provides significant value [1], but will impact performance if not managed properly.

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4 Frontend Sampling Networks

Fig. 4.19 Abo’s bootstrap circuit for highly linear sampling switches

Fig. 4.20 a Precharging the bootstrap capacitor during hold phase and b tracking the input via the bootstrap capacitor during track phase

signal (and to drive VG ). This capacitor is charged to a signal-independent voltage during the hold phase [29], as in Fig. 4.20a. During the track phase, as illustrated in Fig. 4.20b, the bottom terminal of the bootstrap capacitor is driven by the input signal VI N , such that the top terminal of the capacitor is a level-shifted version of VI N . The capacitor is connected to VG , the gate of the sampling switch, ideally resulting in a signal-independent VG S . Practically, VG S still contains signal components due to issues such as parasitic capacitances in the bootstrapped path. Bandwidth mismatches between the bootstrapped path and the sampling switch also introduce additional signal components at increasing frequencies. These artifacts must be managed through diligent design.

4.4

Sub-ADC Sampling Network

79

Fig. 4.21 Mitigating VT modulation by bootstrapping VS B

The signal modulation of the threshold voltage VT (due to a signal-dependent VS B ) also adversely impacts the on-resistance linearity. If the process technology includes a deep n-well, this issue can be addressed as in Fig. 4.21. The dashed circle is the tracking switch, matching Fig. 4.19. The transistors in the dashed box are used to reduce the signal-dependency of VS B . In Fig. 4.21, the body of the sampling switch is shorted to the input during track phase. Thus, VS B = 0. During the hold phase, the body is shorted to ground (to ensure a reverse biased VD B junction). Note that the optimal sizing for the transistor that connects VS to VB is one that balances the difference between VS B and VD B , due to the symmetric behavior of a triode transistor. As performance requirements increase, other impairments will also begin to impact linearity. For example, switching the body to ground during the track to hold transition, as in Fig. 4.21, changes the bias condition of the reverse-biased junction diode between the drain and the body. In a top-plate sampling topology, this will in turn inject nonlinear and signaldependent charge into the sampling capacitor, which will limit performance at much higher input frequencies due to the increased switch size [31]. As the diligent designer targets higher and higher performance specifications, subtleties like this become more apparent, and hopefully additional solutions will arise.

4.4

Sub-ADC Sampling Network

The input signal of each stage of a pipelined ADC goes to both the MDAC sampling capacitors and the sub-ADC, as discussed in Chap. 2. The operation of pipelined ADCs assumes the signals both components see are effectively the same, such that the digital combination of different stage outputs represent a high-fidelity quantized version of the ADC input. If the signal paths modify the input signal differently, the overall ADC performance may be

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Fig. 4.22 Impact of matching on first stage performance as a function of (a), (b) a track-and-hold and (c), (d) no track-and-hold, for different input frequencies

impacted depending on the ADC architecture. This is especially problematic in the first stage, if the ADC does not have a frontend track-and-hold. Figure 4.22 illustrates four scenarios. Figure 4.22a, b contain a frontend track-and-hold with different input frequencies. The MDAC sampling capacitors and sub-ADC track a held signal (outlined with the dashed oval in Fig. 4.22) such that they do not actively see a continuous-time signal, which desensitizes the response to phase mismatch and frequency related variations. Although gain mismatch between the two paths impacts the stage residue (as discussed in Chap. 2), this is not frequency dependent, and input frequency behavior is primarily a function of the frontend track-and-hold. Figure 4.22c, d do not include a frontend track-and-hold, and thus, the MDAC and subADC do not see a held signal. The impact of not having this is discussed next.

4.4

Sub-ADC Sampling Network

4.4.1

81

Without a Frontend Track-and-Hold

Figure 4.22c, d illustrate an ADC architecture without a frontend track-and-hold, with different input frequencies. Due to bandwidth and timing mismatches in the two paths, the frequency-dependent gain and phase response for each of the MDAC sampling network and the sub-ADC are different. Although bandwidth mismatch degrades overall performance, it is typically the phase mismatch component that is most problematic, with its impact increasing with frequency. As a result, the MDAC and sub-ADC each sample different voltages. Figure 4.23 illustrates an example with timing mismatch of t and the corresponding voltage difference V , which is a function of the input signal gradient. Thus, for higher input frequencies, as in Fig. 4.23b, the resulting voltage error is larger than with lower frequencies, as in Fig. 4.23a. Since this voltage error is signal-dependent, it this appears as a signal-dependent offset in the sub-ADC (when compared to the MDAC path). With a sine wave input signal and a phase mismatch of τ , the maximum voltage error can be shown to be equal to Ve,max =

FSR FSR sin (2π f in τ ) ≈ (2π f in τ ) 2 2

(4.19)

Fig. 4.23 Impact of timing error as a function of frequency for a a low input frequency and b a higher input frequency

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Fig. 4.24 Maximum voltage error due to phase error and input frequency with a 3-bit sub-ADC

where F S R is the input full-scale and f in the input signal frequency, and where the approximation is valid for small values of 2π f in τ [32]. For an N-bit first stage, the sub-ADC LSB is FSR (4.20) L S B ST 1 = N 2 Assuming 1-bit redundancy in the pipelined ADC architecture, the tolerable comparator offset is L S B ST 1 /2. Thus, the maximum allowable phase mismatch is τ ≈

1 2 N · 2π f in

(4.21)

and is inversely proportional to the input frequency. Figure 4.24 plots the maximum voltage error as a function of frequency, for different values of τ . As the input frequency increases, the voltage error quickly becomes comparable to the stage LSB. However, the margin for this error is much less than the stage LSB. With 1-bit redundancy,10 for example, half the LSB is already occupied by the signal (excluding any comparator offset). Figure 4.25a plots the impact of this error on the output residue of this stage, which eventually exceeds the full-scale range of the stage. With this error, the available static offset margin, is plotted in Fig. 4.25b. As the frequency increases, the available margin approaches zero, and a phase error of several picoseconds will limit the input frequency to a few GHz, unless alternate techniques are used [32, 33]. In silicon, the phase error can easily be several picoseconds, if not more [34], as a function of the signal and clock routing (and transistor mismatches). Thus, without a front-end trackand-hold, as in Fig. 4.22a, either diligent care is needed in the design, layout, and extracted simulations of these paths, or some trim capability [33] is required. An example of this is in 10 Of course, a higher level of redundancy can be used, which would provide more margin for this

frequency-dependent error.

4.4

Sub-ADC Sampling Network

83

Fig. 4.25 Impact of voltage error on a the output residue and b the available margin for static offset

Fig. 4.26, which illustrates simplified MDAC and sub-ADC sampling paths. The sub-ADC bandwidth response is roughly matched to that of the MDAC path by using a scaled sampling network replica. A programmable delay is inserted into one of the clocking paths (this is usually in the sub-ADC path due to its reduced jitter sensitivity), and provides a knob to correct the phase error. Trim can be implemented during characterization (if the mismatch is primarily dominated by systematic error), during production test if there is a part-to-part variation, or with a calibration algorithm if the mismatch is time-varying [32, 33].

4.4.2

Impact of Bandwidth Mismatch

More generally, mismatches between the impulse responses of the two paths result in signaldependent voltage errors. Although an impulse response11 captures both bandwidth and timing properties, this section, for simplicity, focuses only on bandwidth mismatch (timing 11 A more rigorous discussion of impulse responses of the sub-ADC path (by modeling the compara-

tor) is discussed in Chap. 5, where the comparator impulse sensitivity function (ISF) is analyzed.

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Fig. 4.26 Replica sub-ADC path with delay trim for phase error

mismatch was previously discussed). The interested reader can explore a more general analysis based on the complete impulse response [8]. Bandwidth mismatch can be modeled in the frequency domain with Ye ( f ) = [HM ( f ) − H A ( f )] X ( f )

(4.22)

where HM ( f ) and H A ( f ) are the frequency responses of the MDAC and sub-ADC paths, respectively, X ( f ) is the input signal, and Ye ( f ) is the resulting error. The signal-dependent voltage error in the time-domain is a function of the integrated error in the frequency domain. Since this is heavily dependent on the transfer functions and the input signal spectral density, a general derivation will not be provided here. However, it is possible to look at specific examples. For example, assume that the MDAC has a first-order bandwidth response, such that HM ( f ) =

1 1+ j

f f 3d B

(4.23)

where f 3d B is the bandwidth, and that the sub-ADC has a bandwidth that is slightly lower than f 3d B due to mismatch. Figure 4.27 plots the voltage error due to Eq. 4.22 across frequency, for a narrowband signal and for different mismatch percentages. This peaks close to f 3d B ,

4.5

A Buffer-Less Frontend

85

Fig. 4.27 Impact of bandwidth mismatch on sub-ADC voltage error, with f 3d B = 4 GHz

before decreasing (due to decreasing gain). Since the gain decreases with frequency, the resulting error with mismatch eventually decreases. With wideband signals, the resulting voltage error error will differ, since the total integrated error will factor in. Regardless of the exact bandwidth and input signal, Fig. 4.27 makes it clear that bandwidth mismatch will reduce the available margin in the stage residue, which makes the residue even more sensitive to timing mismatch between the two paths and to comparator offset.

4.5

A Buffer-Less Frontend

Input buffers are an almost ubiquitous interface between the ADC driving circuit and its internal sampling network. However, they come with a cost in terms of power, complexity, and impact on dynamic metrics, as discussed in Sect. 4.1. Without an input buffer, the driving circuit needs to have sufficient drive strength to charge and discharge the sampling capacitor, and must be designed to tolerate the resulting time-varying impedance. If the driving circuit already has the required drive strength, then removing the input buffer from the signal chain is an option that can help optimize the overall PPA of the ADC. Unfortunately, input kickback, discussed in Sect. 4.1.1.5, becomes even more problematic. This section revisits kickback, and discusses additional potential mitigation strategies. Figure 4.28 illustrates a high-level representation of a buffer-less sampling circuit. The off-chip signals, via PCB and package traces, directly drive the on-chip termination resistors and sampling capacitors. As described in Sect. 4.1.1.5, the charge stored on the sampling capacitors from the previous cycle “kicks back” onto the input, and in an MDAC, this charge is a heavily quantized version of the input signal. In a buffer-less ADC, kickback is unattenuated, and directly couples into the off-chip network. This can be modeled with a

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4 Frontend Sampling Networks

Fig. 4.28 Off-chip network driving sampling circuit without input buffer Fig. 4.29 Simplified kickback model

simple RC network,12 as in Fig. 4.29, where the capacitor is driven with a pulsed voltage to emulate the voltage step that occurs when the sampling network transitions from hold to track. This allows for simple evaluation of kickback (and its decay) in both analysis and simulations. With kickback modeled as in Fig. 4.29, the initial magnitude of kickback on the input node Vin is proportional to Cs /(Cs + C p ). This voltage decays at a rate set by the RC time constant at node Vin , such that the kickback response Vk (t) at node Vin is t

Vk (t) = Vk (0)e τk

(4.24)

where Vk (0) and τk are the voltage step and the decay time constant, respectively. For a given resistance (which may be set as a function of the source impedance), there is a clear tradeoff in terms of the initial magnitude Vk (0) and the time constant τk . For example, this magnitude can be decreased by increasing C p (which also reduces the input bandwidth). However, this results in a direct increase of the decay time constant. Two scenarios are plotted in Fig. 4.30. The higher bandwidth scenario (3GHz) has a larger initial condition, but decays much faster 12 This is a simplistic model to illustrate the kickback decay, discussed in Sect. 4.1.1.5. In an actual

design evaluation, the input bondwire and PCB and package transmission line model should be included.

4.5

A Buffer-Less Frontend

87

Fig.4.30 Kickback decay with CS = 500fF and RS = 50, for different bandwidths. Dashed vertical lines mark track times corresponding to 2.5 and 1.25 GSPS

than the lower bandwidth. Although a 3 GHz bandwidth decays sufficiently for a 1.25 GSPS ADC (assuming a track time of 2F1 S ), it does not for a 2.5GSPS ADC. Furthermore, as illustrated in Fig. 4.10, inductive behavior leads to ringing in the kickback decay response, which makes kickback even more problematic. In order to address this issue in the absence of an input buffer, the designer has several options. For example, it is clear from Eq. 4.24 and Fig. 4.30 that increasing the bandwidth significantly improves the decay response by reducing τk . It is also possible to increase the resolution of the first stage. This decreases the quantization steps, which reduces the magnitude of the nonlinearity that is injected at the input (thus, reducing Vk (0)). This nonlinearity can also be addressed by separating the sampling and DAC capacitors, as discussed in Chap. 3. The MDAC can be configured as described in Sect. 3.2.2, such that the sampling capacitors are charged to a signal-independent common-mode voltage during the redistribution phase. When the MDAC transitions from hold to track again, the resulting kickback is signal-independent. Separating the DAC capacitors ensures that the quantization charge does not discharge through the input network (at the expense of other properties such as a decreased feedback factor). Calibration is also possible [9]. Here, the signal-dependent kickback is subtracted digitally from the ADC digital output, with Dˆ out [n] = Dout [n] − α1 Dout [n − 1]

(4.25)

where α1 represents the magnitude of the inter-symbol interference that arises from kickback, and can be extracted through background estimation techniques [9]. In addition, the impact of kickback can be significantly reduced with the introduction of a reset phase, as discussed below.

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4 Frontend Sampling Networks

Fig. 4.31 Reset switch added to sampling network, with timing diagram

4.5.1

Introducing a Reset Phase

Kickback arises from the signal-dependent charge stored on the sampling capacitors. With enough track time, the residual charge can decay, as in Fig. 4.30. In addition to techniques already discussed, the charge on the sampling capacitors can also be made signalindependent with the introduction of a reset phase, as in Fig. 4.31 [5, 35, 36]. During the hold-phase, the charge on the two differential sampling capacitors contains a quantized signal component, but the total charge on the two capacitors is signal-independent. Shorting the capacitors redistributes and equalizes the charge on both differential halves. Thus, as the sampling network transitions from the hold phase to the track phase, if the capacitors were shorted together before the track phase begins, then the charge injected into the input network is signal-independent, removing the inter-symbol interference due to kickback. It is also possible to short the capacitors directly to an internally generated voltage, although this is not necessary. Fortunately, the reset phase can be generated as part of the clock generator. The pulse used for this reset switch should not overlap with either P1 or P2, as in Fig. 4.31, and thus comes at the expense of either the track or amplification time (or both). However, 20–40 picoseconds of reset time is sufficient, and can be achieved with proper layout and low routing resistance [5], and is on the order of the non-overlapping time between P1 and P2. With this modification to the sampling network, it is possible to equalize the charge on the sampling capacitors, which will improve ADC performance.

References

89

References 1. El-Chammas M, Li X, Kimura S, Maclean K, Hu J, Weaver M, Gindlesperger M, Kaylor S, Payne R, Sestok CK, Bright W (2014) A 12 bit 1.6 gs/s bicmos 2–2 hierarchical time-interleaved pipeline ADC. IEEE JSolid-State Circ 49(9):1876–1885 2. El-Chammas M, Li X, Kimura S, Coulon J, Hu J, Smith D, Landman P, Weaver M (2015) 15.8 90db-sfdr 14b 500 ms/s bicmos switched-current pipelined ADC. In: 2015 IEEE international solid-state circuits conference—(ISSCC) digest of technical papers, pp 1–3 3. Devarajan S, Singer L, Kelly D, Pan T, Silva J, Brunsilius J, Rey-Losada D, Murden F, Speir C, Bray J, Otte E, Rakuljic N, Brown P, Weigandt T, Yu Q, Paterson D, Petersen C, Gealow J, Manganaro G (2017) A 12-b 10-gs/s interleaved pipeline ADV in 28-nm cmos technology. IEEE J Solid-State Circ 52(12):3204–3218 4. Yoshizawa H, Temes GC (2007) Switched-capacitor track-and-hold amplifiers with low sensitivity to op-amp imperfections. IEEE Trans Circ Syst I: Regul Pap 54(1):193–199 5. El-Chammas M (2017) Design techniques for multi-gs/s and high performance pipelined ADCS. ISSCC F6: Pushing the performance limit in data converters, Feb 2017 6. Das D (1997) Techniques for low distortion buffering of high speed switched capacitor ADCs. PhD thesis, Massachusetts Institute of Technology 7. van der Ziel A (1981) Equipartition laws of thermal noise. IEEE J Quantum Electron 17(8):1324– 1325 8. El-Chammas M, Murmann B (2009) General analysis on the impact of phase-skew in timeinterleaved ADCs. IEEE Trans Circ Syst I: Regul Pap 56:902–910 9. Ali AMA, Dinc H, Bhoraskar P, Dillon C, Puckett S, Gray B, Speir C, Lanford J, Brunsilius J, Derounian PR, Jeffries B, Mehta U, McShea M, Stop R (2014) A 14 bit 1 gs/s rf sampling pipelined ADC with background calibration. IEEE J Solid-State Circ 49(12):2857–2867 10. Varzaghani A, Yang C-KK (2009) A 4.8 gs/s 5-bit ADC-based receiver with embedded DFE for signal equalization. IEEE J Solid-State Circ 44(3):901–915 11. Razavi B (2013) Fundamentals of microelectronics. Wiley, Fundamentals of Microelectronics 12. Gray PR (2009) Analysis and design of analog integrated circuits, 5th ed. Wiley Publishing 13. Der Ziel AV (1958) Noise in junction transistors. Proc IRE 46(6):1019–1038 14. Rein H-M, Moller M (1996) Design considerations for very-high-speed si-bipolar ic’s operating up to 50 gb/s. IEEE J Solid-State Circ 31(8):1076–1090 15. Choma J (1989) Simplified design guidelines for dominant pole amplifiers peaked actively by emitter or source followers. IEEE Trans Circ Syst 36(7):1005–1010 16. Malone F (1977) The early voltage of a bipolar transistor. IEEE Trans Electron Dev 24(2):167– 168 17. Aksin D, Maloberti F (2022) Very high-speed bjt buffer for track-and-hold amplifiers with enhanced linearity. In 2002 IEEE international symposium on circuits and systems. Proceedings (Cat No02CH37353), vol 5, pp V–V 18. Payne R, Corsi M, Smith D, Kaylor S, Hsieh T (2010) A 16-Bit 100 to 160 MS/s SiGe BiCMOS Pipelined ADC With 100 dBFS SFDR. IEEE Jf Solid-State Circ 45:2613–2622 19. Vadipour M (1994) Optimum degeneration for minimum mismatch in bipolar current sources. IEEE J Solid-State Circ 29(10):1297–1300 20. Ali AMA, Morgan A, Dillon C, Patterson G, Puckett S, Bhoraskar P, Dinc H, Hensley M, Stop R, Bardsley S, Lattimore D, Bray J, Speir C, Sneed R (2010) A 16-bit 250-ms/s if sampling pipelined ADC with background calibration. IEEE J Solid-State Circ 45(12):2602–2612

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21. Setterberg B, Poulton K, Ray S, Huber DJ, Abramzon V, Steinbach G, Keane JP, Wuppermann B, Clayson M, Martin M, Pasha R, Peeters E, Jacobs A, Demarsin F, Al-Adnani A, Brandt P (2013) A 14b 2.5gs/s 8-way-interleaved pipelined ADC with background calibration and digital dynamic linearity correction. In: 2013 IEEE international solid-state circuits conference digest of technical papers, pp 466–467 (2013) 22. Payne R, Sestok C, Bright W, El-Chammas M, Corsi M, Smith D, Tal N (2011) A 12b 1GS/s SiGe BiCMOS two-way time-interleaved pipeline ADC. In: 2011 IEEE international solid-state circuits conference digest of technical papers (ISSCC), pp 182–184 23. Tsividis Y, Fraser D (1981) Harmonic distortion in single-channel MOS integrated circuits. IEEE J Solid-State Circ 16(6):694–702 24. Straayer M, Bales J, Birdsall D, Daly D, Elliott P, Foley B, Mason R, Singh V, Wang X (2016) 27.5 a 4gs/s time-interleaved rf ADC in 65 nm CMOS with 4 ghz input bandwidth. In: 2016 IEEE international solid-state circuits conference (ISSCC), pp 464–465 25. Ali AMA, Dinc H, Bhoraskar P, Bardsley S, Dillon C, McShea M, Periathambi JP, Puckett S (2020) A 12-b 18-gs/s rf sampling ADC with an integrated wideband track-and-hold amplifier and background calibration. IEEE J Solid-State Circ 55(12):3210–3224 26. Hershberg B, Dermit D, van Liempd B, Martens E, Markuli´c N, Lagos J, Craninckx J (2021) A 4-gs/s 10-enob 75-mw ringamp ADC in 16-nm CMOS with background monitoring of distortion. IEEE J Solid-State Circ 56(8):2360–2374 27. Yu W, Sen S, Leung B (1999) Distortion analysis of MOS track-and-hold sampling mixers using time-varying volterra series. IEEE Trans Circ Syst II: Analog Digit Signal Processing 46:101–113 28. Iizuka T, Ito T, Abidi AA (2018) Comprehensive analysis of distortion in the passive fet sampleand-hold circuit. IEEE Trans Circ Syst I: Regul Pap 65(4):1157–1173 29. Abo A, Gray P (1999) A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter. IEEE J Solid-State Circ 34:599–606 30. Razavi B (2015) The bootstrapped switch [a circuit for all seasons]. IEEE Solid-State Circ Mag 7(3):12–15 31. Aggrawal H, El-Chammas M (2018) Track and hold with active charge cancellation, Jul 31 2018. US Patent App. 10037814B2 32. Huang P, Hsien S, Lu V, Wan P, Lee S-C, Liu W, Chen B-W, Lee Y-P, Chen W-T, Yang T-Y, Ma G-K, Chiu Y (2011) Sha-less pipelined ADC with in situ background clock-skew calibration. IEEE J Solid-State Circ 46(8):1893–1903 33. Brandolini M, Shin YJ, Raviprakash K, Wang T, Wu R, Geddada HM, Ko Y-J, Ding Y, Huang C-S, Shih W-T, Hsieh M-H, Chou AW-T, Li T, Shrivastava A, Chen DY-C, Hung BJ-J, Cusmai G, Wu J, Zhang MM, Yao Y, Unruh G, Venes A, Huang HS, Chen C-Y (2015) A 5 gs/s 150 mw 10 b sha-less pipelined/sar hybrid ADC for direct-sampling systems in 28 nm CMOS. IEEE J Solid-State Circ 50(12):2922–2934 34. El-Chammas M (2010) Background calibration of timing skew in time-interleaved A/D converters. PhD thesis, Stanford University 35. Poulton K, Neff R, Setterberg B, Wuppermann B, Kopley T, Jewett R, Pernillo J, Tan C, Montijo A (2003) A 20 GS/s 8 b ADC with a 1 MB Memory in 0.18 μm CMOS. In: 2003 IEEE international solid-state circuits conference digest of technical papers (ISSCC), vol 1, 318–496, Feb 2003 36. Devarajan S, Singer L, Kelly D, Decker S, Kamath A, Wilkins P (2009) A 16-bit, 125 ms/s, 385 mw, 78.7 db snr CMOS pipeline ADC. IEEE J Solid-State Circ 44(12):3305–3313

5

Comparator Design

In each pipelined ADC stage, the sub-ADC coarsely quantizes the stage input signal (see Chapter 2). With a robust pipelined ADC architecture and choice of redundancy, the design requirements of the sub-ADC are relaxed. For example, the sensitivity of ADC performance to artifacts such as comparator offset and noise is significantly reduced with redundancy, and thus the comparator1 is not typically viewed as a critical component. However, for highspeed pipelined ADCs, the comparator can impact certain performance metrics, especially at higher sample rates and input frequencies. This chapter focuses on the impact of comparator metastability on the ADC code error rate, and on the impact of the comparator’s impulse sensitivity function on ADC performance [2]. The comparator (and sub-ADC) also offers several knobs to the designer that allow for improved overall ADC performance. For example, dither can be embedded within the comparator to randomize the residue thresholds, which in turn reduces the magnitude of higher order harmonics [3, 4]. In addition, some closed loop calibration algorithms that optimize other parameters of ADC performance use elements of the sub-ADC [5–7]. These will not be discussed in this chapter, but are interesting topics the reader can further explore. For simplicity, the discussion in this chapter assumes the sub-ADC is a flash ADC and that the comparators are regenerative [1] (i.e. have a positive feedback topology). Although there are exceptions [7], a flash ADC is typically the architecture of choice in higher speed pipelined ADCs due to its fast conversion time.

1 The metrics that should be tracked in a comparator design [1] depend on the ADC architecture

and specifications, and may include comparator power, input-referred offset, input-referred noise, clock-to-Q delay, input kickback, regeneration time constant, and impulse sensitivity function. This chapter focuses on the latter two. © The Author(s), under exclusive license to Springer Nature Switzerland AG 2023 M. El-Chammas, High-Performance and High-Speed Pipelined ADCs, Synthesis Lectures on Engineering, Science, and Technology, https://doi.org/10.1007/978-3-031-29700-7_5

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5.1

5 Comparator Design

Comparator Metastability

A clocked comparator converts an input signal vin (t) (at time t = nT ) into a binary output Dcomp [n], such that 1, if vin (nT ) > 0 (5.1) Dcomp [n] = 0, otherwise where T is the clock period. In a real transistor level circuit, this output is not generated instantaneously, since the comparator needs to sufficiently regenerate from its initial conditions. If this does not occur within the clock period, then the comparator is metastable and its output is considered undefined. Classically analyzed in flip-flops [8], metastability has also played a role in the design space of different ADC architectures [9, 10]. Comparator metastability may cause glitches to appear in the ADC output, resulting in significant word errors, and becomes more problematic at higher clock frequencies, since the metastability rate (the frequency of these metastable events) increases. The rest of this section dives into comparator metastability in more detail, and is followed by an analysis of the relationship between comparator metastability rates and pipelined ADC error rates.

5.1.1

Metastability Rate

Figure 5.1 illustrates a simple example of metastability. In Fig. 5.1a, a device under test (DUT) is followed by a D flip-flop (DFF), where both circuits operate on the rising edge of their clock. When D1 is generated, there is a period of time where the value of D1 is uncertain, as in Fig. 5.1b. If the DFF is clocked (with C L K 2 ) during this period, its output may be incorrect. With sufficient time between the rising edges of C L K 1 and C L K 2 , D1 enters a stable (or deterministic) region, such that the DFF output is correct, as in Fig. 5.1b. The structure in Fig. 5.1 is applicable to various DUTs. For example, in digital systems, the DUT may consist of some DFFs and combination logic. The output of the DUT must satisfy certain setup times for the following DFF. If setup violations do exist, one solution is to simply reduce the clock frequency (or increase the supply). More relevant to this book, the DUT may also be a comparator. The receiving circuit can correctly interpret the DUT output if the output signal passes some threshold before the circuit is clocked. Otherwise, the DUT is considered metastable [8]. The metastability rate (MR) is defined as the probability that the signal is less than the threshold, as in (5.2) M R = P(|Y | < ym ) Here, Y is the signal being analyzed, and ym is the threshold at which the next block can accurately decode the signal. In the example of Fig. 5.1a, the signal can be Y = D1 − Vmid pt , for some midpoint voltage (if D1 is a differential output, Vmid pt is typically zero). Thus, if the absolute value of Y is less that ym , then the DUT is considered to be metastable. The signal Y is a function of time, and is less likely to be metastable as more time passes. The

5.1

Comparator Metastability

93

Fig. 5.1 Timing relationship resulting in potential metastability with a a simple metastability test structure and b a corresponding timing diagram

metastability rate of Eq. 5.2 is typically defined at a given clock period, and can be derived for a comparator using the following first-order model.

5.1.2

First-Order Comparator Model

Positive-feedback comparators consists of cross-coupled circuits (often, but not always, implemented with cross-coupled inverters), that can be linearized [11] as in Fig. 5.2. The linearized configuration in Fig. 5.2 is a dynamic system that depends on the initial conditions (without loss of generality, at time t = 0) of the capacitor voltages Vop and Von (where the differential output at t = 0 is Vod (0) = Vop (0) − Von (0)). The transfer function of the differential output can be derived [11] as a function of time to be t

Vod (t) = Vod (0)e τC

for t ≥ 0

(5.3)

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5 Comparator Design

where τC is the comparator regeneration time constant. Thus, the comparator exponentially amplifies (or, regenerates) its initial condition , where the magnitude of regeneration is a function of time. Additionally, the differential capacitor voltage Vod (0) can be expressed as Vod (0) = AC Vin , where Vin is the differential input signal at t = 0 and AC is a linear comparator gain. From Fig. 5.2, the regeneration time constant τC is derived [11] as τC =

CL CE + CI = gm gm

(5.4)

where C L is the load capacitance and gm is the transconductance of the cross-coupled inverter. C L consists of both the comparator extrinsic and intrinsic capacitances, C E and C I , respectively, such that C L = C E + C I . If C E = 0, the comparator time-constant τC is lower-bounded by the transistor transit frequency f T , which is a function of the process technology. Although Eq. 5.3 is unbounded, the comparator does eventually transition from its linear regime (where it regenerates exponentially) to a slew-based regime that is eventually limited by either ground or supply. The transition point is a function of the comparator topology, and has minimal impact on metastability analysis except for an additional delay component. When the DUT in Fig. 5.1 is a positive-feedback comparator, Eq. 5.3 can be combined with Eq. 5.2. Since the receiving cell needs an input larger than ym , the comparator is considered metastable for a given regeneration time t = TR if the input is small enough such that |Vin | < Vin,m =

ym − Tτ R e C AC

(5.5)

where Vin,m is the minimum voltage needed for the output to regenerate to ym . The metastability rate (as in Eq. 5.2), assuming a uniform input signal distribution, is M R = P(|Vod | < ym ) = 2

Fig. 5.2 Linearized cross-coupled comparator model

T Vin,m ym − R e τC =2 FSR F S R · AC

(5.6)

5.2

Calculating the ADC Error Rate

95

Fig. 5.3 Impact of increasing TR on comparator metastability rate

where F S R is the input signal full-scale range. Both the regeneration time TR and time constant τC have an exponential impact on the metastability rate, and are typically the key optimization parameters. An example of the relationship between the metastability rate and regeneration time is plotted in Fig. 5.3. For example, increasing TR by approximately ten time constants can reduce the metastability rate by more than four orders of magnitude. In leading edge technology nodes, the comparator time constant τC can be as low as a few picoseconds, which illustrates the impact of increasing TR by only a few tens of picoseconds. Although other variables in Eq. 5.6 also impact the metastability rate, their impact is linear and are not a dominant optimization parameter. The comparator metastability rate plays a direct role in the ADC error rate. In a pipelined ADC, the regeneration time constant τC is primarily a function of the comparator design for a given technology node. However, the regeneration time has various dependencies on the pipelined ADC topology. For example, the amplifier and DAC settling time, the comparator propagation delay, and the intrinsic phase delay of the comparator all reduce the available regeneration time. This is discussed in more detail in the following section.

5.2

Calculating the ADC Error Rate

Comparator metastability can ripple into the ADC output [12], resulting in gross errors in the ADC output word. Although these output errors (also known as sparkle codes) are commonly referred to as a bit error (and the associated BER, or bit error rate), a better phrase is the code error rate or word error rate [13], which ties together the error frequency and magnitude. Comparator metastability in each stage of a pipelined ADC can result in code errors. However, the magnitude of these errors is different per stage, due to the inter-stage gain.

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5 Comparator Design

As a result, design efforts on improving the error rate typically focus on the first stage. The following analysis assumes both the comparator and sub-ADC are properly designed, such that at most one comparator has a metastability event. This output uncertainty impacts two paths in the pipelined ADC stage, as in Fig. 5.4. The first is the digital path (through the subADC encoder), and the second is the analog path (through the DAC, amplifier, and sampling circuit of the next stage). These two paths have different impacts on the error magnitude. The pipelined ADC stage should be architected such that impact of metastability on the digital path is much smaller than that on the analog path. If the sub-ADC encoder is incorrect, it can generate a code error of at least one stage LSB (which can be many LSBs with respect to the full ADC). This is a significant error, and can be easily mitigated by choosing a robust encoder design that ensure the encoder error is limited to 1 bit (for example, a Mangelsdorf Encoder [14] or a Wallace Encoder [11, 15, 16] can be used). Furthermore, since the encoder output is not used until all the stage outputs are combined, standard pipelining techniques can be used that improve the error rates in the digital path [9]. This ensures that the dominant source of metastability induced code errors in a pipelined ADC is the analog path. The longer a comparator takes to regenerate, the shorter the available time for other analog blocks to sufficiently settle. As illustrated in Fig. 5.5, delays in the comparator output directly translate to a delayed amplifier output. In this analog path, code errors occur if the amplifier output has not sufficiently settled before the end of the residue generation phase, and thus the error rate is a function of both the comparator and of the subsequent blocks. The rest of this section focus on this analog path, since it ties in the analog settling times of various blocks, the amplifier gain, and the comparator time constant to allow rough estimates of the ADC error rate. Although this chapter focuses on metastability, code errors also result from random noise. In fact, for small error magnitudes, Gaussian noise can dominate the error rate, whereas for larger errors, comparator metastability can. The next section quickly touches on error rate

Fig. 5.4 Digital and analog paths in pipelined ADC stage

5.2

Calculating the ADC Error Rate

97

Fig. 5.5 Impact of comparator regeneration on residue amplifier output, where half of the sampling period Ts is available for residue generation

analysis using Gaussian input noise. Due to its simplicity, this analysis helps set the stage for a more interesting analysis of errors due to metastability.

5.2.1

Impact of Noise on Code Error Rate

Consider a 12b ADC with additive Gaussian noise of σ = 1 LSB (resulting in an SNR of approximately 63 dB). Figure 5.6a plots the ADC output with a sine wave input, and Fig. 5.6b zooms into a section of this output to illustrate the impact of noise. The code error is the deviation of the ADC output compared to its ideal value (or the best-fit value, as in Fig. 5.6b), and its histogram is plotted in Fig. 5.7a. The code error rate (CER) is calculated for a target code error magnitude [13], C E, such that the CER is C E R = P(|err or | ≥ C E)

(5.7)

This is plotted in Fig. 5.7b, for different values of CE.2 If the code errors are due to Gaussian noise, then the error rate can be extrapolated based on Gaussian statistics. The cumulative distribution in Eq. 5.7 can be expressed with the complementary error function (taking into consideration both halves of the probability distribution and assuming zero-mean) as in ∞ 2 1 −x CE R = 2√ e 2σ2 d x (5.8) 2πσ 2 C E 2 The noise used in this example has a Gaussian distribution (and thus, is unbounded). However, the

plots in Fig. 5.7 used a finite number of samples, which limits the ability to calculate the CER for larger values of CE. To do this, much more data is required. For example, if error rates of less than 10−5 are to be measured, over 1 million samples will need to be captured in order to obtain a reasonable estimation. If error rates of less than 10−15 are to be measured, then even with a 10GSPS ADC, measurements will need to run for over a week. This is not a practical lab or simulation measurement (especially for low error rates), and thus necessitates extrapolation [17].

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5 Comparator Design

Fig. 5.6 ADC output with noise. a Full ADC output and b zoomed in output with best-fit line

Extrapolation to large sample counts is possible if enough data is captured to accurately extract key parameters (such as the noise standard deviation σ), as plotted in Fig. 5.8. For example, if the noise σ = 1 LSB, a code error magnitude of 10 LSBs results in an extrapolated error rate of less than 10−20 . If, however, insufficient samples are taken, the estimation variance of these parameters can result in erroneous results. Figure 5.8 plots an example with a 10% mismatch in σ, which results in almost a 3X order of magnitude difference in the error rate. It is evident that although Gaussian noise results in an error distribution, its impact on anything larger than a few sigma of noise is negligible. This is not the case when the source of code errors is comparator metastability.

5.2

Calculating the ADC Error Rate

99

Fig. 5.7 a Code error histogram and b cumulative probability that absolute value of code error ≥ CE

Fig. 5.8 ADC error probability due to noise with estimated sigma

100

5.2.2

5 Comparator Design

ADC Error Rate Analysis

As depicted in Fig. 5.5, delays in the comparator output result in a delayed amplifier response. With a large enough delay, the stage output does not sufficiently settle to the required backend accuracy, resulting in an incorrect ADC output code (i.e. code errors). It is possible that the comparator remains metastable until the end of the redistribution phase [18], which will result in a gross code error. However, smaller code errors will still occur when the comparator has regenerated well before the end of the redistribution phase [2, 17, 19], which is the case analyzed here. This section focuses on the analog path of Fig. 5.4, which includes the flash sub-ADC, the residue amplifier, and the DAC. For simplicity, the below analysis details the case when the amplifier response is dominant (when compared to the DAC), to allow for key tradeoffs to be easily extracted. This is revisited in later in this section, where the DAC settling behavior is also considered.

5.2.2.1 Qualitative Analysis Before deriving quantitative relationships between different pipelined ADC parameters and the ADC error rate, it is instructive to qualitatively analyze [20] the impact of the key parameters with a few examples. This provides some intuition as to tradeoffs, so that the equations that are derived later in this section do not come as a surprise. For example, as the comparator time constant τC increases, the comparator needs more time to regenerate. This decreases the available redistribution time for the amplifier, resulting in a larger error rate. Likewise, as the amplifier settling time constant increases, the amplifier requires more time to sufficiently settle. This also results in a larger error rate, since for the same amplification time, the residual dynamic error increases. It is possible to improve this by decreasing the comparator time constant, since the comparator regenerates in a shorter time, thus increasing the available amplifier redistribution time. As previously discussed, the code error rate is a function of the error magnitude, and larger error magnitudes occur with larger amplifier settling error, which occurs when the comparator regeneration time increases. Thus, the error rate will decrease as the error magnitude increases, since the increased regeneration time is due to a smaller input signal. Since the comparator response is exponential, this decrease follows an exponential relationship. This also applies for the amplifier settling time constant, since the amplifier redistribution time and the comparator regeneration time affect each other. Finally, the error rate is also a function of the resolution of the backend ADC, since these code errors occur when the stage output has not sufficiently settled to the accuracy of the backend ADC. If, for example, the first stage resolution is constant, then as the resolution of the backend ADC decreases, the error rate for a given error magnitude decreases, since more settling error is acceptable. However, if the ADC resolution is constant, then a reduced backend ADC resolution means an increased first stage resolution. The increased number of comparators increase the number of regions in the input signal where metastability can

5.2

Calculating the ADC Error Rate

101

occur. The end impact in this scenario on error rate depends on the relative magnitudes of the comparator and amplifier time constants.

5.2.2.2 Quantitative Analysis The comparators in the flash sub-ADC have a regeneration response as analyzed in Sect. 5.1.2. To quickly recap, a comparator is no longer considered metastable if its output reaches a certain threshold, ym . Thus, the time the comparator needs to regenerate to ym is ym + tD (5.9) tC = τC ln Vin,c AC where τC is the comparator time constant, Vin,c is the comparator (differential) input voltage, AC is the linear comparator gain, and t D is a delay parameter (due to factors such as comparator slewing, clock buffers, switch logic, etc.). For most input signal levels, all subADC comparators regenerate quickly, and an amplifier designed with a small enough settling time constant will sufficiently settle. However, input signal levels near comparator thresholds (illustrated by the vertical gray lines in Fig. 5.9) fall into a metastable region, and will extend that comparator’s regeneration time. In a properly designed sub-ADC, at most one comparator may have a long regeneration time since the input signal is close to its threshold. The other comparators that did regenerate quickly (since the input signal was not close to their thresholds) will appropriately drive the corresponding DAC elements such that the amplifier output settles in response to those comparators within the redistribution phase. This is not the case for the lone metastable comparator. Once this final comparator completes its regeneration, after a time tC (as in Eq. 5.9), it drives the remaining DAC element. The amplifier then must settle in response to this change in its input in a time TR − tC , where TR is the total stage redistribution time. The residue amplifier of Fig. 5.4 has finite bandwidth and thus, an associated settling time. For simplicity, assume the amplifier has a dominant pole, such that its settling behavior is similar to that of a single pole system with a closed-loop gain of G A and a settling time constant3 of τ A . Although this assumption is not necessary , it does simplify the analysis and clarifies tradeoffs between various parameters. For a given amplifier (differential) input voltage Vin,a , the residual output-referred settling error (ignoring amplifier slewing) after a time of TR − tC is V A,err or = G A Vin,a e

−

T R −tC τA

(5.10)

Thus, the shorter the available amplifier settling time (TR − tC ), the larger the residual error. V or The input-referred settling error is simply Verr or = A,err GA .

3 The time constant is the inverse of the amplifier bandwidth, and should be small enough so that the

amplifier sufficiently settles during the redistribution phase without comparator metastability.

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5 Comparator Design

Fig. 5.9 Comparator thresholds and metastable regions

The remaining DAC element corresponding to this lagging comparator will results in approximately a ± F 2S R step4 at the amplifier output (and ± F2GS RA at its input) once the comparator has completed its regeneration. Thus, at the regions of metastability of Fig. 5.9, the amplifier input-referred settling error is Verr or =

V A,err or FSR − =± e GA 2G A

T R −tC τA

=±

FSR − e N

T R −tC τA

(5.11)

where N is the number of comparators and G A = N /2. A code error with a magnitude of L LSBs (in a B-bit ADC) can be related to the above amplifier input-referred settling error with Verr or = ±L

FSR 2B

(5.12)

Thus,

2 − TRτ−tC L A = B (5.13) e N 2 where the factor of 2 is a result of combining ±L. Combining this with Eq. 5.9 results in

Vin,c AC ym

=e

−

T R −t D τC

N

L 2 B+1

− τ A τC

(5.14)

which relates the comparator input voltage to an estimated code error of L LSBs. For comparator input voltages less than Vin,c , the resulting code error is larger than L since the comparator needs more time to regenerate. Therefore, assuming a uniform input distribution, the probability for one comparator to result in an ADC code error of at least L is 4 This is an approximation of the actual response, which has some dependency on the stage architec-

ture. However, the introduced error with this approximation is negligible and has minimal impact on the error rate order of magnitude.

5.2

Calculating the ADC Error Rate

103

Fig. 5.10 Example ADC code error rate versus sampling period for different τ A and τC values

PL = p(C E ≥ L) = p(Vin ≤ Vin,c ) =

Vin,c FSR

(5.15)

With N comparators in the sub-ADC, the probability of error for the ADC across all comparators is T −t Vin,c N ym − R D e τC Pe = N PL = N = FSR F S R · AC

N

L

− τ A τC

2 B+1

(5.16)

This relates the probability of a code error larger than L LSBs to the comparator time constant τC , the amplifier time constant τ A , and the redistribution time TR . Equation 5.16 can be expressed as Pe = A0 e

−

T R −t D −t0 τ A τC

(5.17)

where A0 =

N ym F S R · AC

and t0 = (B + 1) ln(2) − ln(L) − ln(N )

(5.18)

Eq. 5.17 captures the design and architecture tradeoffs in a succinct expression. A0 is a design and architecture dependent factor, and t0 is dependent on the ADC resolution and the target code error magnitude. This illustrates several tradeoffs with the ADC design, as qualitatively covered in Sect. 5.2.2.1. First, a smaller comparator time constant τC exponentially reduces the error rate, and also sharpens the slope of the error rate with respect to the redistribution time TR . Second, a smaller amplifier time constant reduces the impact of t0 , thus also resulting in a lower error rate since the comparator has more time to regenerate. Finally, the impact of N , the number of levels in the first stage depends on the ratio of τ A and τC . If τ A /τC > 1, then increasing N improves the error rate since the backend ADC resolution decreases.

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The impact of some of these parameters are plotted in Fig. 5.10 for an error magnitude of L = 32, across sampling period. As expected, a larger sampling period decreases the resulting error rate. Decreasing τC sharpens the slope (since it is in the denominator of Eq. 5.17), whereas decreasing τ A shifts the curve (since it is in the numerator). Although not plotted, minimizing t D (introduced by signal path elements such as clock buffers, comparator buffers, reference switching logic, to name some examples) shifts the curves in Fig. 5.10 to the left.

5.2.2.3 Impact of Amplifier Gain-Bandwidth In the previous discussion, the number of levels in the first stage marginally impacts the error rate. However, this assumes that the amplifier time constant τ A is independent of N . With a constant amplifier gain-bandwidth product, increasing the gain will decrease the bandwidth (increasing the time constant), with τ A = G A τU G B =

N τU G B 2

(5.19)

where τU G B is the unity gain-bandwidth time constant. Thus, Eq. 5.17 becomes Pe = A0 e

−

T R −t D −t0 N 2 τU G B τC

(5.20)

Although t0 decreases as N increases, t0 N still increases. Thus, if error rate is an important specification, it will limit the design space of the pipelined ADC architecture.

5.2.2.4 Impact of DAC Settling In the above analysis, the focus was on the comparator regeneration time constant and the amplifier settling time constant, and assumes the DAC output has settled instantly. This simplification allows the above tradeoffs to be extracted in a concise expression, but it is also possible to include the impact of DAC settling [19]. With switched-capacitor pipelined ADCs, the settling behavior of the DAC is a function of the reference generator (discussed in Chap. 6) and of the reference switches. In a firstorder model, this has a time constant of τ D . Thus, the settling response of the amplifier output is FSR − t − t Vo,a (t) = ± (5.21) 1 − e τ A 1 − e τD 2 and the input-referred error (as in Eq. 5.11) becomes F S R − τt − t − t − t e A + e τD − e τ A e τD N t F S R − τt − t e A 1 + e τ A τD ≈± N

Verr or (t) = ±

(5.22)

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where t = TR − tC as before. Now, the DAC time constant plays a role [19] by introducing t

−

t

an additional factor 1 + e τ A τ D . If τ D τ A , which is typically the case in pipelined ADCs, then this expression simplifies into the previous analysis. How much of an impact the DAC will have on error rate is dependent on the relative values of τ D and τ A , which is something the designer will need to consider.

5.2.2.5 Error Rate as a Function of Code Error Magnitude In Fig. 5.10, the error rate was plotted across sample period, for a given code error value. If the code error target is small, the error rate will be dominated by Gaussian noise, as discussed in Sect. 5.2.1. However, the impact of noise drops off very quickly for larger error magnitudes, and is dominated by metastability errors. The error probability relates to the power of the code error magnitude L, with Pe ∝ L

τ C

− τA

(5.23)

which drops off slower than a Gaussian distribution. An example error rate versus error magnitude is plotted in Fig. 5.11, where errors due to both Gaussian noise and metastability are illustrated. Though the values change depending on all the design parameters, there will typically exist a point where the error rate due to metastability is larger than that due to noise.

5.2.2.6 Impact of Later Stages Pipelined ADC error rates are dominated by metastability in the first stage, as assumed in the above analysis, since the first stage has the most stringent settling accuracy requirements. For example, an L LSB code error due to the second stage means that the second stage

Fig. 5.11 Impact of noise and metastability on error rate

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Fig. 5.12 Clocking the sub-ADC of later stages earlier to improve metastability rate

input-referred error is LG A (where G A is the inter-stage gain), which gives it significant margin when compared to errors in the first stage. However, later stages can also impact the error rate, if not designed properly. If two stages have similar design parameters (such as τC and τ A ), then it is much more likely that the first stage results in a code error larger than L than it is for the second stage to results in a code error of L. Additionally, later stages can have improved timing. Although the residue amplifier still needs to settle sufficiently in order to not impact the ADC linearity, the sub-ADC input does not need an accurate input voltage. By nature of the ADC redundancy, unsettled stage 1 amplifier outputs can be absorbed by the stage 2 sub-ADC. Thus, the subADC can be clocked earlier, as with φ ADC,2 in Fig. 5.12, where the rising edge of φ ADC,2 occurs a time td before the second stage redistribution phase begins, and before the first stage redistribution ends. This results in a multiple time constant increase in regeneration time, which, as in Fig. 5.3, significantly reduces the comparator metastability rate. Since this has substantial impact on the error rate of the second stage, it is possible to ignore the impact of later stages in a high-level code error analysis. However, it is important that the later stages do not have significantly larger time constants than the first stage. Otherwise, the benefits of the inter-stage gain and additional regeneration time evaporate. The impact of the second stage, for example, can be calculated using a variant of Eq. 5.16, by replacing L with LG A . This can be used to ensure the later stages do not meaningfully degrade the ADC error rate.

5.2.3

Simulating and Measuring Error Rates

For small error rates, it is not possible to simulate millions of points to obtain sufficient samples at the target sample rate in a reasonable time frame, which is why the previous analysis serves as an analytic guide without requiring simulations. However, it is important to be able to extract sufficient data from simulations to predict what the error rate would be. In addition, the code error rate must also be validated in silicon. In this section, the simulation

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of comparator time constants, an integral part of Eq. 5.17, is discussed. In addition, both stage simulation and ADC measurement strategies are detailed, in order to extract code error estimates in a reasonable amount of time.

5.2.3.1 Simulating the Comparator Time Constant The comparator time constant τC has a significant impact on error rate, as illustrated in Fig. 5.10, and it is important to accurately extract it in simulations. Theoretically, it is possible to sweep the comparator input voltage to capture the range of inputs that result in comparator metastability for a given regeneration time. Practically,5 however, this approach does not always work for a variety of reasons, and other approaches are required. With a correct testbench setup, it is possible to simulate accurate values of τC . As discussed in Sect. 5.1.2, the comparator output regenerates with Vo (t) = Vin AC et/τC

(5.24)

for a given input voltage Vin , as long as the comparator is in its linear region. Increasing the input voltage by e results in Vo = (eVin ) AC et/τC = Vin AC e(t+τC )/τC

(5.25)

which shifts the comparator output curve to the left by τC , as in Fig. 5.13a. The time shift between the two curves can be quickly extracted in simulations, and directly maps to the comparator time constant [21]. The input voltage (and its multiples) should be small enough to ensure the comparator is in its linear region (where it grows exponentially as in Eq. 5.24), but not too small where it is impacted by other comparator behaviors such as offset. Figure 5.13 illustrates an example of this, where Vin is 1mV, and both eVin and e−1 Vin are simulated, for a comparator with τC = 4ps. The arrows demonstrate the time shift between the different curves. The comparator response with these inputs is plotted in Fig. 5.13a, where the extracted time constant is estimated to be 4ps (as expected), and is independent of any delays introduced by clocking or buffers. Figure 5.13b plots the comparator response with offset. The time difference between curves changes depending on which curves are used to estimate τC , as a result of this voltage offset. To address this, the designer can simulate across more input voltage magnitudes (for both positive and negative inputs), and calculate a best-fit to reduce the impact of this systematic offset. This is especially important with extracted simulations, where offsets due to parasitics [22] will impact the analysis. Of course, the offset can be calibrated out in simulations, to place the comparator in a more centered state.

5 A quote to always keep in mind when working with circuits is: “In theory, theory and practice are

the same. In practice, they are not”.

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Fig. 5.13 Simulating comparator time constant by sweeping the input voltage for a no systematic offset and b some systematic offset

An alternative simulation methodology can be used to extract τC without worrying about offset, but does require slightly more data analysis. The derivative of Eq. 5.24 is d Vo (t) 1 Vin AC et/τC = dt τC

(5.26)

Taking the ratio of Eq. 5.24 to its derivative in Eq. 5.26 results in Vo (t) d Vo (t) dt

= τC

(5.27)

This method is insensitive to the input signal, as long as the comparator is in its linear region, and systematic offset does not impact the result. Although analytically straightforward, this method is more complicated to visually inspect. The comparator response is not as clean

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Fig. 5.14 Simulating comparator time constant (with τC = 4ps) using the output derivative. a Example output b Output normalized with derivative

as represented by Eq. 5.24, and for a period of time before and after the linear region, the comparator behavior is not meaningful for this analysis [21]. For example, a standard strong-arm latch may give a response as in Fig. 5.14 a, where the outputs first need to settle to some voltage level before they start regenerating in the linear region. Figure 5.14b plots the ratio of an example comparator output to its derivative. In Fig. 5.14, a rectangle outlines the appropriate region, where the ratio is equal to the comparator time constant of 4ps. The regions before and after the rectangle do not represent the regeneration time constant, and this makes it slightly harder to extract the time constant.

5.2.3.2 Measuring ADC Code Error Rates For applications that require specific error rates, post-silicon measurements are critical. However, extremely small error rates can not be measured in a reasonable amount of time. For example, a 10 GSPS ADC with a target error rate of 10−15 at a specific code magnitude requires multiple days of data collection to minimize estimation variance.

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Instead of running measurements for extended periods of time, error rates can be extrapolated [13, 17, 23]. Since lower code error magnitudes occur more frequently, enough data can be collected to reduce the estimation variance of their code error rates. The error probability reduces with increased error magnitude, as in Eg. 5.23, and thus, a best fit-line can be used to extrapolate to larger code error magnitudes. Additionally, it is also possible to extrapolate error rates by running the ADC with a higher sample rate. The reduced clock period exponentially increases the error rate for a target error magnitude, allowing for much more data collection in a more reasonable amount of time ([17] has an example of this with a switched-current pipelined ADC). It is also a strategy that can be used in simulations, in order to verify the theoretical error rate estimates with an acceptable simulation time.

5.2.3.3 Improving the ADC Error Rate If the ADC’s error rate is too high, there are several approaches that can help mitigate the issue. The first and obvious ones are to decrease both the comparator and amplifier time constants. However, these are lower bounded by the transit frequency f T of the process node, since the intrinsic transistor capacitance will limit speed. Achieving these bounds can cost significantly in terms of power, with diminishing returns. If further time constant reduction is not feasible, architectural modifications can also be implemented, that primarily aim to increase the comparator regeneration time. For example, an additional track-and-hold stage [17, 24] can be implemented that provides an analog delay, as in Fig. 5.15. In this, the sub-ADC can begin to operate a half clock cycle early, providing significant improvement in regeneration time and ADC error rate. Since the analog delay element is in the analog signal path, it impacts both noise and linearity, and results in a power and area penalty. For extremely low error rate targets, it is also possible to cascade two track-and-holds (to further increase the comparator regeneration time). Alternatively, clocking modifications can be implemented to reduce the track time of the first stage [3]. This results in more time for both the regeneration and redistribution phase.

Fig. 5.15 Improving error rate with an additional analog delay

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Impact of Impulse Sensitivity Function

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Correction schemes that help reduce the error magnitude [25] are also possible. Although time-interleaved ADCs are not discussed here, that is also an architectural decision that can help with error rate reduction [11, 26]. Finally, the sub-ADC can simply be clocked as early as possible, in order to minimize the td component of Eq. 5.17 [2], and can directly operate on the dynamic input signal. This introduces additional design constraints on matching, as discussed in the next section.

5.3

Impact of Impulse Sensitivity Function

Section 4.4.1 discussed ADCs without a frontend track-and-hold in order to improve the ADC’s overall PPA. This also has the added benefit of potentially improving the ADC error rate. Since the stage 1 sub-ADC is clocked as early as possible, the time delay (td ) of Eq. 5.17 is reduced. It is also possible for the sub-ADC comparators to directly operate on the continuous-time input signal instead of a held signal, as in Fig. 5.16, using the sampling clock P0 , which samples the signal before P1 goes low. This minimizes td without requiring a frontend track-and-hold. However, the comparator now shapes the dynamic input signal, and its bandwidth can impact the mismatch between the two paths. As discussed in Section 4.4.1, matching between the sampling path and the sub-ADC path is critical for high frequency input signals. As a result, the comparator sees the input signal vin,c (t) = (h c ∗ vin )(t)

Fig. 5.16 Clocking the comparators before sampling has finished

(5.28)

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where h c (t) is its impulse response, such that comparator output of Eq. 5.1 becomes 1, if(h c ∗ vin )(nT ) > 0 (5.29) Dcomp [n] = 0, otherwise In a continuous-time (and linear time-invariant) circuit, it is possible to directly extract the impulse function and its corresponding frequency domain transfer function using common simulation techniques. With a time-varying circuit, such as a clocked comparator, this can be extracted with a series of transient simulations [2, 27, 28], that result in an impulse sensitivity function. This is discussed next.

5.3.1

Comparator Impulse Sensitivity Function

Consider an impulse as an input to the comparator, such that vin (t) = δ(t − t0 ). Also consider that the comparator is clocked at t = t1 , such that the comparator begins to regenerate at t1 . The output of the comparator depends on the relationship between t0 and t1 . For example, if t0 t1 or t0 t1 , as in Fig. 5.17, the comparator will not react much to the input, because it would either be in the reset phase, as in Fig. 5.17a, or would already have completed regeneration, as in Fig. 5.17b. This is captured by the unchanged delay of the comparator output relative to its input clock, which can be interpreted as the comparator being “insensitive” to the input signal. However, as t0 approaches t1 , the comparator output response does change, such that it is “sensitive” to the input signal. In this “region of sensitivity”, the comparator output behavior changes, and this change is captured by quantifying the delay of the comparator output with respect to its input clock. For example, for a given t0 in this region, different amplitude pulses will result in different output delays (by impacting the regeneration time), as in Fig. 5.18. This delay increases as the input amplitude decreases, and the amplitude A I S F that results in a target delay of t I S F [27] can be extracted. The comparator impulse sensitivity function is then defined with

Fig. 5.17 Input impulse much a earlier or b later than the clock rising edge

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Impact of Impulse Sensitivity Function

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Fig. 5.18 Impact of varying pulse amplitude on comparator output delay

S I S F (t) =

K A I S F (t)

(5.30)

where t = t1 − t0 , K is a normalization factor [27], and A I S F (t) is the amplitude that results in the target output delay. For example, if t is large enough that an impulse has no impact on the output delay, then increasing the amplitude of the pulse will also not have an impact, and S I S F = 1/A I S F = 0. However, if t is a value at which the comparator does react to the input, increasing the amplitude will decrease the output delay (and vice versa). The ISF function of S I S F (t) is the comparator impulse function of Eq. 5.28, and convolves with the input such that the comparator output is 1, if (S I S F ∗ vin )(nT ) > 0 Dcomp [n] = (5.31) 0, otherwise Since the sampling path in the MDAC will not have the same response, mismatches between the two signal paths exist, and will degrade the ADC’s high frequency response.

5.3.2

Simulating the Impulse Sensitivity Function

A closed-form expression for the ISF of a given comparator topology is nontrivial to derive.6 This is further complicated by other circuit properties, such as the clock rise/fall time, input impedance, routing and transistor parasitics, etc. For this reason, simulations are used to accurately extract the ISF. Figure 5.19 describes the testbench [2, 27, 29] that can be used for these simulations. Alternate simulation methods are also possible [30]. The verilog-A module in Fig. 5.19 adjusts the amplitude of V pulse in order to achieve a specific output delay.7 This can be implemented with various search algorithms, such as

6 To my knowledge, one does not exist yet. 7 Although the value of the target delay impacts the amplitude, this simulation does not require a

specific delay value. Since the ISF is normalized by the area [27], the transfer function is not sensitive to the chosen delay target, as long as it is in a reasonable range for both the circuit and the simulator.

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Fig. 5.19 Simulation setup for comparator impulse sensitivity function

a binary search [27]. A I S F (t) is simulated for different values of t, and the impulse sensitivity function8 S I S F (t) is then derived with Eq. 5.30. This section presents a few examples of ISF responses using this simulation methodology, with a strong-arm latch.9 Although the ISF of Eq. 5.30 should be normalized to the area [27], the plots in this section scale the ISF to a constant peak, such that they are more visually comparable.

5.3.2.1 Impact of Clock Rise Times Figure 5.20a plots the ISF for a strong-arm latch with different clock risetimes. Even with an extremely sharp risetime of 1ps, the peak of the ISF occurs when t = t1 − t0 ≈ −3ps < 0. This means that the comparator is most sensitive to an input signal that arrives shortly after the clock goes high. The width of the ISF at the 3dB limit is approximately 4ps, which implies the comparator has a very high bandwidth, and the ISF quickly drops to below 10% of its peak, with a width of less than 10ps. With more realistic clock risetimes (the mid-point of the clock edge is used as the time reference), the peak of the ISF shifts further to the left, and has a wider response as the clock risetime increases, as also plotted in Fig. 5.20a.

5.3.2.2 Impact of Transistor Sizes Figure 5.20b illustrates several ISFs for a different input and clock transistors sizes. For example, if the input pair of a strong-arm latch is too small, then the comparator continues to be sensitive to signals after the clock edge since the drains of the input transistors have not been sufficiently pulled down (which allows more time for the input signal to impact regeneration). On the other hand, if the clock transistor size increases, the comparator has a narrower ISF. Additional sizing tradeoffs can be explored, and the ISF can be added as a design specification, since it can lead to a slightly different optimal transistor sizing.

8 The Fourier Transform can then be used to translate this to the frequency domain, to illustrate the

effective comparator bandwidth. 9 This methodology can be applied to different comparator configurations. It can also be used with

other time-varying circuits, such as the MDAC sampling path.

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Impact of Impulse Sensitivity Function

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Fig. 5.20 a Comparator ISF with different clock risetimes and b comparator ISF with different transistor sizes

5.3.2.3 Impact of Limited Frontend Bandwidth The comparator input comes from a replica tracking path, as in Fig. 5.16, that models the bandwidth of the MDAC sampling path. Figure 5.21a plots the ISF for several different tracking bandwidths. The left part of the ISF is limited by the comparator performance. However, the right side is limited by the input bandwidth, and has an expected first-order response.

5.3.2.4 Impact of Comparator Preamplifier Although a strong-arm latch has excellent transient performance in terms of speed, time constant, and impulse sensitivity function, the design sometimes requires a preamplifier. Figure 5.21b plots the ISF for a comparator with several different preamplifier biasing conditions (where the bandwidth ∝ Ibias ). As the bandwidth decreases, the ISF becomes wider. Such responses can lead to significant bandwidth mismatch with the sampling path.

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Fig. 5.21 Comparator ISF a with limited frontend bandwidth and b with a comparator preamplifier

5.3.3

Mapping the ISF to ADC Performance

As discussed in Sect. 4.4.1, mismatch between the sampling and sub-ADC paths results in the stage output residue growing beyond the full-scale range of the next stage, as a function of input frequency. If the sub-ADC comparators directly operate on the continuous-time input signal, then the comparator bandwidth becomes a factor. The behavior of the stage residue can be obtained with full stage simulations in the pipelined ADC, but these can take hours (and sometimes days, with extracted simulations). In addition, if the residue does grow in an unexpected manner, then the stage simulations do not always offer actionable insight into the root cause. Since ISF simulations can be run in a matter of minutes, the pipelined ADC behavior across input frequency can be evaluated using the ISFs of both the sampling and the subADC path without requiring a complete stage simulation. This mapping of the ISF to the

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Impact of Impulse Sensitivity Function

117

pipelined ADC performance can be done much earlier in the design phase, allowing for the impact of the comparator ISF to be quantified, as discussed in this section. The ISF of both the sub-ADC path (including the comparator) and the MDAC sampling path should first be extracted. Figure 5.22a plots example ISFs for a configuration similar to Fig. 5.16. With the replica tracking circuit, the bandwidth of the two paths almost perfectly match, as illustrated in the right half of Fig. 5.22a. However, the sampling path is less sensitive to signals after the sampling instant than the sub-ADC (as illustrated in the left half of Fig. 5.22a). The ISF of each path directly convolves with the input signal, and the signals the sub-ADC and the MDAC see are vin,M D AC (t) = S M D AC,I S F (t) ∗ vin (t) vin,C O M P (t) = SC O M P,I S F (t) ∗ vin (t)

(5.32)

where S M D AC,I S F and SC O M P,I S F are the ISFs for the sampling path and comparator, respectively. A high-level model of the pipelined ADC can use the simulated ISFs of each

Fig. 5.22 a ISF of sub-ADC path and MDAC sampling path, where both operate with the same clock and b impact of ISF on output residue with same clock for sub-ADC and sampling path

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Fig. 5.23 Impact of ISF on output residue with a tunable clock delay, with a the ISFs of Fig. 5.22, b with bandwidth mismatch, and c with a preamplifier

path with the expressions in Eq. 5.32. With vin (t) as a sinusoidal signal, the input frequency can be swept, and the output residue of the stage can be calculated with this model. This captures the impact of any mismatch between the two paths as a function of frequency, similar to what was done in Section 4.4.1.

References

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Figure 5.22b plots an example of this, using the ISFs of Fig. 5.22a. Due to mismatch between the two responses, the residue overshoots the bound after several GHz input frequency. With some margin allocated for comparator offset, this bound is exceeded with an even lower input frequency. This type of analysis allows the exploration of various design knobs that may improve the output residue (and the ADC performance) across frequency. For example, the comparator clock can be skewed compared to the sampling path clock, in order to compensate for phase error [2, 31]. The impact of this knob is illustrated in Fig. 5.23a, where the clock is delayed in discrete steps. Here, a trim of approximately 4ps helps to significantly extend the performance. The impact of additional bandwidth mismatch between the two paths can also be captured, once the ISF for each path is extracted. This is illustrated in Fig. 5.23b. Comparator clock skew trim is included, demonstrating the complex interplay between phase delay and bandwidth mismatch. Finally, the impact of a comparator preamplifier, with an ISF as plotted in Fig. 5.20, is illustrated in Fig. 5.23c. In both of these plots, clock skew trim is insufficient to compensate for the bandwidth mismatch, even when comparator offset is not included. The use of ISFs, and the subsequent mapping to the pipelined ADC performance [2], can offer early insights into architectural decisions, by illustrating the benefits or drawbacks of various potential circuits. The examples in this section used sine wave inputs to demonstrate the frequency-dependent impact, but this analysis is extendable to wideband signals that more realistically capture the application’s signal statistics, and is a topic the interested reader can further explore.

References 1. Pelgrom MJM (2010) Analog-to-Digital conversion, 1st edn. Springer Publishing Company, Incorporated 2. El-Chammas M (2017) Design techniques for multi-gs/s and high performance pipelined ADCS. ISSCC F6: Pushing the performance limit in data converters, Feb 2017 3. El-Chammas M, Li X, Kimura S, Coulon J, Hu J, Smith D, Landman P, Weaver M (2015) 15.8 90db-sfdr 14b 500 ms/s bicmos switched-current pipelined ADC. In: 2015 IEEE international solid-state circuits conference—(ISSCC) Digest of Technical Papers, pp 1–3 4. Devarajan S, Singer L, Kelly D, Decker S, Kamath A, Wilkins P (2009) A 16-bit, 125 ms/s, 385 mw, 78.7 db snr CMOS pipeline ADC. IEEE J Solid-State Circ 44(12):3305–3313 5. Shi L, Zhao W, Wu J, Chen C (2012) Digital background calibration techniques for pipelined ADC based on comparator dithering. IEEE Transn Circ Syst II: Express Briefs 59(4):239–243 6. Li J, Moon U-K (2003) Background calibration techniques for multistage pipelined ADCS with digital redundancy. IEEE Trans Circ Syst II: Analog Digit Signal Processing 50(9):531–538 7. Lagos J, Markuli´c N, Hershberg B, Dermit D, Shrivas M, Martens E, Craninckx J (2022) A 10.1enob, 6.2-fj/conv.-step, 500-ms/s, ringamp-based pipelined-sar ADC with background calibration and dynamic reference regulation in 16-nm CMOS. IEEE J Solid-State Circu 57(4):1112– 1124 (2022)

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8. Veendrick H (1980) The behaviour of flip-flops used as synchronizers and prediction of their failure rate. IEEE J Solid-State Circ 15:169–176 9. Portmann C, Meng T (1996) Power-Efficient metastability error reduction in CMOS Flash A/D converters. IEEE J Solid-State Circ 31:1132–1140 10. Chan C-H, Zhu Y, Sin S-W, Murmann B, Seng-Pan U, Martins RP (2017) Metastablility in sar ADCS. IEEE Trans Circ Syst II: Express Briefs 64(2):111–115 11. El-Chammas M (2010) Background calibration of timing skew in time-interleaved A/D converters. PhD thesis, Stanford University 12. Kester W (2010) Find those elusive ADC sparkle codes and metastable states. Analog Dev 13. Ye B, Chan K (2016) Verified design pipeline ADC code error rate analysis and measurement. Texas Instruments 14. Mangelsdorf C (1990) A 400-mhz input flash converter with error correction. IEEE J Solid-State Circ 25(1):184–191 15. Wallace CS (1964) A suggestion for a fast multiplier. IEEE Trans Electron Comput EC-13:14–17 16. Sail E, Vesterbacka M (2007) Thermometer-to-Binary decoders for flash analog-to-digital converters. In: Proceedings of European conference on circuit theory and design, pp 240–243, Aug 2007 17. El-Chammas M, Li X, Kimura S, Maclean K, Hu J, Weaver M, Gindlesperger M, Kaylor S, Payne R, Sestok CK, Bright W (2014) A 12 bit 1.6 gs/s bicmos 2-2 hierarchical time-interleaved pipeline ADC. IEEE J Solid-State Circ 49(9):1876–1885 18. Guhados S, Hurst PJ, Lewis SH (2012) A pipelined ADC with metastability error rate − ln τR CS where the last equality is derived with C B = (2 K − 1)C S for some value of K ≥ 0.

6.1.1.1 Slow Reference Amplifier In a B-bit ADC, if K > B, then < 21B = 1 LSB, even at t = 0. With a 12-bit ADC, this can result is a huge capacitor, and is a slow reference solution. It is easy to interpret this as implying that the amplifier time constant can be large, since the error introduced in this cycle is less than an LSB. However, if this error is not corrected within a reasonable time, then it accumulates and will modulate the reference voltage. To prevent this, the time constant can be set to M sampling periods (the value of M can be either less than or greater than 1, and is a function of the design requirements and the acceptable residual error), which bounds the amplifier output impedance ro to ro (C B + C S ) < M TS → ro