Green Nanotechnology 1774073366, 9781774073360

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GREEN NANOTECHNOLOGY

GREEN NANOTECHNOLOGY

Edited by:

Mulmudi Hemant Kumar

ARCLER

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e

s

s

www.arclerpress.com

Green Nanotechnology Mulmudi Hemant Kumar

Arcler Press 2010 Winston Park Drive, 2nd Floor Oakville, ON L6H 5R7 Canada www.arclerpress.com Tel: 001-289-291-7705 001-905-616-2116 Fax: 001-289-291-7601 Email: [email protected] e-book Edition 2020 ISBN: 978-1-77407-410-7 (e-book)

This book contains information obtained from highly regarded resources. Reprinted material sources are indicated. Copyright for individual articles remains with the authors as indicated and published under Creative Commons License. A Wide variety of references are listed. Reasonable efforts have been made to publish reliable data and views articulated in the chapters are those of the individual contributors, and not necessarily those of the editors or publishers. Editors or publishers are not responsible for the accuracy of the information in the published chapters or consequences of their use. The publisher assumes no responsibility for any damage or grievance to the persons or property arising out of the use of any materials, instructions, methods or thoughts in the book. The editors and the publisher have attempted to trace the copyright holders of all material reproduced in this publication and apologize to copyright holders if permission has not been obtained. If any copyright holder has not been acknowledged, please write to us so we may rectify. Notice: Registered trademark of products or corporate names are used only for explanation and identification without intent of infringement.

© 2020 Arcler Press ISBN: 978-1-77407-336-0 (Hardcover)

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DECLARATION Some content or chapters in this book are open access copyright free published research work, which is published under Creative Commons License and are indicated with the citation. We are thankful to the publishers and authors of the content and chapters as without them this book wouldn’t have been possible.

ABOUT THE EDITOR

Hemant obtained his PhD from Nanyang Technological University, Singapore in 2014. His interests span from material synthesis via solution processed methods to it application in energy harvesting devices such as photovoltaics and water splitting. He is currently working as a research fellow at the Australian national university on silicon/perovskite solar cells.

TABLE OF CONTENTS

List of Contributors .......................................................................................xv List of Abbreviations ................................................................................. xxvii Preface...................................................................................................... xxxi Chapter 1

Vertical Silicon Nanowire Platform for Low Power Electronics and Clean Energy Applications................................................ 1 Abstract ..................................................................................................... 1 Introduction ............................................................................................... 2 Low Power Electronics ............................................................................... 4 Clean Energy ........................................................................................... 21 Challenges and Opportunities.................................................................. 30 Summary ................................................................................................. 32 Acknowledgment ..................................................................................... 32 References ............................................................................................... 33

Chapter 2

The Challenges of Green Nanotechnology .............................................. 41 Sumarry ................................................................................................... 41

Chapter 3

Green Synthesis of Silver Nanoparticles by Escherichia Coli: Analysis of Antibacterial Activity ............................................................ 45 Abstract ................................................................................................... 45 Introduction ............................................................................................. 46 Materials and Methods ............................................................................ 47 Results and Discussions ........................................................................... 50 Conclusion .............................................................................................. 60 Acknowlwedgment .................................................................................. 60 References ............................................................................................... 61

Chapter 4

Green Synthesis, Characterization and Catalytic Activity of Natural Bentonite-Supported Copper Nanoparticles for the Solvent-Free Synthesis of 1-Substituted 1H-1,2,3,4-Tetrazoles And Reduction of 4-Nitrophenol ............................................................. 67 Abstract ................................................................................................... 68 Introduction ............................................................................................. 68 Experimental............................................................................................ 69 Results and Discussion ............................................................................ 71 Conclusion .............................................................................................. 81 Acknowledgments ................................................................................... 82 References ............................................................................................... 83

Chapter 5

Honey Mediated Green Synthesis of Nanoparticles: New Era of Safe Nanotechnology ............................................................ 87 Abstract ................................................................................................... 87 Introduction ............................................................................................. 88 Green Synthesis ....................................................................................... 90 Natural Honey ......................................................................................... 93 Physical Characteristics of Honey ............................................................ 93 Chemical Composition of Honey ............................................................. 94 Honey Mediated Green Synthesis of Nanoparticles ................................. 95 Gold Nanoparticles ................................................................................. 96 Silver Nanoparticles................................................................................. 97 Palladium Nanoparticles .......................................................................... 97 Carbon Nanoparticles .............................................................................. 98 Platinum Nanoparticles ........................................................................... 98 Challenges ............................................................................................... 99 Conclusion ............................................................................................ 100 Acknowledgments ................................................................................. 100 References ............................................................................................. 101

Chapter 6

Laser Irradiation In Water For The Novel, Scalable Synthesis of Black Tiox Photocatalyst For Environmental Remediation .................... 111 Abstract ................................................................................................. 111 Introduction ........................................................................................... 112 Experimental.......................................................................................... 114 Results and Discussion .......................................................................... 116

x

Conclusion ............................................................................................ 121 Acknowledgements ............................................................................... 121 References ............................................................................................. 122 Chapter 7

Henna (Lawsonia inermis L.) Dye-Sensitized Nanocrystalline Titania Solar Cell ................................................................................... 125 Abstract ................................................................................................. 125 Introduction ........................................................................................... 126 Structure and Operation of Dye-Sensitized Solar Cells ........................... 127 Experimental.......................................................................................... 129 Results and Discussion .......................................................................... 130 Conclusion ............................................................................................ 134 Acknowledgments ................................................................................. 135 References ............................................................................................. 136

Chapter 8

Stem Cell Tracking Using Iron Oxide Nanoparticles ............................. 139 Abstract ................................................................................................. 139 Introduction ........................................................................................... 140 What is a Superparamagnetic Iron Oxide Nanoparticle? ........................ 141 Using Spions in Magnetic Resonance Imaging (MRI).............................. 142 Stem Cell Tracking ................................................................................. 144 Synthesis and Labeling of Magnetic Iron Oxide Particles ........................ 146 A Comparison of Different Coats For Spions .......................................... 148 In Vivo Animal Studies ........................................................................... 150 Human Studies ...................................................................................... 152 The Limitations of MRI and The Use of Spions ....................................... 154 Conclusion ............................................................................................ 156 References ............................................................................................. 157

Chapter 9

Enhancing Photocatalytic Degradation of Methyl Blue Using PVP-Capped and Uncapped CdSe Nanoparticles .................................. 165 Abstract ................................................................................................. 165 Introduction ........................................................................................... 166 Methodology ......................................................................................... 167 Results and Discussion .......................................................................... 168 Conclusion ............................................................................................ 175

xi

Acknowledgments ................................................................................. 175 References ............................................................................................. 176 Chapter 10 Green Preparation and Spectroscopic Characterization of Plasmonic Silver Nanoparticles Using Fruits As Reducing Agents ......... 179 Abstract ................................................................................................. 179 Introduction ........................................................................................... 180 Results and Discussion .......................................................................... 181 Conclusion ............................................................................................ 187 Experimental.......................................................................................... 187 Acknowledgements ............................................................................... 188 References ............................................................................................. 189 Chapter 11 Epigallocatechin Gallate Nanodelivery Systems for Cancer Therapy ..................................................................................... 191 Abstract ................................................................................................. 191 Introduction ........................................................................................... 192 EGCG .................................................................................................... 194 Nanotechnology and Nanochemoprevention......................................... 202 Conclusions ........................................................................................... 214 Acknowledgments ................................................................................. 215 Author Contributions ............................................................................. 215 References ............................................................................................. 216 Chapter 12 Fluorogenic RNA Aptamers: A Nano-platform for Fabrication of Simple and Combinatorial Logic Gates ............................................. 231 Abstract ................................................................................................. 231 Introduction ........................................................................................... 232 Results and Discussion .......................................................................... 235 Materials and Methods .......................................................................... 243 Conclusions ........................................................................................... 246 Author Contributions ............................................................................. 246 Acknowledgments ................................................................................. 247 References ............................................................................................. 248

xii

Chapter 13 CTHRSSVVC Peptide as a Possible Early Molecular Imaging Target for Atherosclerosis ........................................................ 255 Abstract ................................................................................................. 256 Introduction ........................................................................................... 257 Results ................................................................................................... 258 Discussion ............................................................................................. 271 Materials and Methods .......................................................................... 274 Conclusions ........................................................................................... 280 Acknowledgments ................................................................................. 280 Author Contributions ............................................................................. 281 References ............................................................................................. 282 Chapter 14 The Current Trends In The Green Syntheses of Titanium Oxide Nanoparticles And Their Applications ........................................ 287 Abstract ................................................................................................. 288 Introduction ........................................................................................... 288 Green Synthesis of TiO2 Nanoparticles From Different Sources .............. 290 Applications of Green TiO2 NPs ............................................................. 308 Conclusion ............................................................................................ 317 References ............................................................................................. 319 Chapter 15 CoFe2O4/Carbon Nanotube Aerogels As High Performance Anodes For Lithium Ion Batteries .......................................................... 329 Abstract ................................................................................................. 330 Introduction ........................................................................................... 330 Experimental.......................................................................................... 332 Results and Discussion .......................................................................... 333 Conclusions ........................................................................................... 342 Acknowledgement ................................................................................. 342 References ............................................................................................. 343 Chapter 16 Nanoparticles Biosynthesized by Fungi and Yeast: A Review of Their Preparation, Properties, and Medical Applications .................. 347 Abstract ................................................................................................. 347 Introduction ........................................................................................... 348 Biological Synthesis of Nanoparticles .................................................... 349 Biosynthesis of Nanoparticles by Microorganisms .................................. 351 xiii

Biosynthesis of Nanoparticles by Fungi .................................................. 351 Production of Nanoparticles by Using Yeast ........................................... 358 Biomedical Applications of Green Synthesis Nanoparticles.................... 360 Conclusions ........................................................................................... 368 Acknowledgments ................................................................................. 368 Author Contributions ............................................................................. 368 References ............................................................................................. 369 Index ..................................................................................................... 383

xiv

LIST OF CONTRIBUTORS D.-L. Kwong Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research), 11 Science Park Road, Singapore 117685 X. Li Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research), 11 Science Park Road, Singapore 117685 Electrical and Electronics Engineering Department, Nanyang Technological University, Singapore 639798 Y. Sun Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research), 11 Science Park Road, Singapore 117685 Electrical and Electronics Engineering Department, Nanyang Technological University, Singapore 639798 G. Ramanathan Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research), 11 Science Park Road, Singapore 117685 Electrical and Electronics Engineering Department, Nanyang Technological University, Singapore 639798 Z. X. Chen Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research), 11 Science Park Road, Singapore 117685 S. M. Wong Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research), 11 Science Park Road, Singapore 117685 Electrical and Electronics Engineering Department, Nanyang Technological University, Singapore 639798

xv

Y. Li Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research), 11 Science Park Road, Singapore 117685 Electrical and Computer Engineering Department, National University of Singapore, Singapore 117576 N. S. Shen Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research), 11 Science Park Road, Singapore 117685 K. Buddharaju Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research), 11 Science Park Road, Singapore 117685 Y. H. Yu Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research), 11 Science Park Road, Singapore 117685 Electrical and Electronics Engineering Department, Nanyang Technological University, Singapore 639798 S. J. Lee Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research), 11 Science Park Road, Singapore 117685 Electrical and Computer Engineering Department, National University of Singapore, Singapore 117576 N. Singh Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research), 11 Science Park Road, Singapore 117685 G. Q. Lo Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research), 11 Science Park Road, Singapore 117685 Miguel de la Guardia Department of Analytical Chemistry, University of Valencia, Spain Koilparambil Divya School of Biosciences, Mahatma Gandhi University, Kottayam, Kerala, India

xvi

Liya C. Kurian School of Biosciences, Mahatma Gandhi University, Kottayam, Kerala, India Smitha Vijayan School of Biosciences, Mahatma Gandhi University, Kottayam, Kerala, India Jisha Manakulam Shaikmoideen School of Biosciences, Mahatma Gandhi University, Kottayam, Kerala, India Akbar Rostami-Vartooni Department of Chemistry, Faculty of Science, University of Qom, Qom, Iran Mohammad Alizadeh Department of Chemistry, Faculty of Science, University of Qom, Qom, Iran Mojtaba Bagherzadeh Material Research School, NSTRI, 81465-1589, Isfahan, Iran Eranga Roshan Balasooriya Department of Zoology & Environment Sciences, Faculty of Science, University of Colombo, Colombo, Sri Lanka Department of Chemistry, Faculty of Science, University of Colombo, Colombo, Sri Lanka Chanika Dilumi Jayasinghe Department of Zoology & Environment Sciences, Faculty of Science, University of Colombo, Colombo, Sri Lanka Department of Zoology, Faculty of Natural Sciences, The Open University of Sri Lanka, Nugegoda, Sri Lanka Uthpala ApekshaniJayawardena Department of Zoology & Environment Sciences, Faculty of Science, University of Colombo, Colombo, Sri Lanka Department of Zoology, Faculty of Natural Sciences, The Open University of Sri Lanka, Nugegoda, Sri Lanka Ranasinghe Weerakkodige Dulashani Ruwanthika Department of Chemistry, Faculty of Science, University of Colombo, Colombo, Sri Lanka

xvii

RohiniMendis de Silva Department of Chemistry, Faculty of Science, University of Colombo, Colombo, Sri Lanka Preethi Vidya Udagama Department of Zoology & Environment Sciences, Faculty of Science, University of Colombo, Colombo, Sri Lanka Massimo Zimbone CNR-IMM, via S. Sofia 64, 95123 Catania, Italy Giuseppe Cacciato CNR-IMM, via S. Sofia 64, 95123 Catania, Italy Mohamed Boutinguiza Grupo de Aplicaciones Industriales de los Láseres, Departamento de Física Aplicada, E.T.S. Ingenieros Industriales de Vigo, Rúa Maxwell, s/n, Campus Universitario, 36310 Vigo, Spain Vittorio Privitera CNR-IMM, via S. Sofia 64, 95123 Catania, Italy Maria Grazia Grimaldi CNR-IMM, via S. Sofia 64, 95123 Catania, Italy Dipartimento di Fisica e Astronomia, Università di Catania, via S. Sofia 64, 95123 Catania, Italy Khalil Ebrahim Jasim Department of Physics, College of Science, University of Bahrain, Bahrain Shawqi Al-Dallal College of Graduate Studies and Research, Ahlia University, Bahrain Awatif M. Hassan Department of Chemistry, University of Bahrain, Bahrain Elizabeth Bull UCL Centre for Nanotechnology and Regenerative Medicine, Division of Surgery and Interventional Science, University College London, London

xviii

Seyed Yazdan Madani UCL Centre for Nanotechnology and Regenerative Medicine, Division of Surgery and Interventional Science, University College London, London Roosey Sheth UCL Centre for Nanotechnology and Regenerative Medicine, Division of Surgery and Interventional Science, University College London, London Amelia Seifalian UCL Centre for Nanotechnology and Regenerative Medicine, Division of Surgery and Interventional Science, University College London, London Mark Green Department of Physics, King’s College London, Strand Campus, London, UK Alexander M Seifalian UCL Centre for Nanotechnology and Regenerative Medicine, Division of Surgery and Interventional Science, University College London, London Royal Free London National Health Service Foundation Trust Hospital, London, UK Kgobudi Frans Chepape Department of Chemistry, Vaal University of Technology, Vanderbijlpark 1900, South Africa Thapelo Prince Mofokeng Department of Chemistry, Vaal University of Technology, Vanderbijlpark 1900, South Africa Pardon Nyamukamba Department of Chemistry, Vaal University of Technology, Vanderbijlpark 1900, South Africa Kalenga Pierre Mubiayi Department of Chemistry, Vaal University of Technology, Vanderbijlpark 1900, South Africa Makwena Justice Moloto Department of Chemistry, Vaal University of Technology, Vanderbijlpark 1900, South Africa xix

Jes Ærøe Hyllested Danmarks Tekniske Universitet DTU, Department of Physics and Department of Micro- and Nanotechnology, 2800 Kgs. Lyngby, Denmark Marta Espina Palanco Danmarks Tekniske Universitet DTU, Department of Physics and Department of Micro- and Nanotechnology, 2800 Kgs. Lyngby, Denmark Nicolai Hagen Danmarks Tekniske Universitet DTU, Department of Physics and Department of Micro- and Nanotechnology, 2800 Kgs. Lyngby, Denmark Klaus Bo Mogensen Danmarks Tekniske Universitet DTU, Department of Physics and Department of Micro- and Nanotechnology, 2800 Kgs. Lyngby, Denmark Katrin Kneipp Danmarks Tekniske Universitet DTU, Department of Physics and Department of Micro- and Nanotechnology, 2800 Kgs. Lyngby, Denmark Andreia Granja UCIBIO/REQUIMTE, Department of Chemical Sciences, Faculty of Pharmacy, University of Porto, Rua de Jorge Viterbo Ferreira, 228, 4050-313 Porto, Portugal Marina Pinheiro UCIBIO/REQUIMTE, Department of Chemical Sciences, Faculty of Pharmacy, University of Porto, Rua de Jorge Viterbo Ferreira, 228, 4050-313 Porto, Portugal Salette Reis UCIBIO/REQUIMTE, Department of Chemical Sciences, Faculty of Pharmacy, University of Porto, Rua de Jorge Viterbo Ferreira, 228, 4050-313 Porto, Portugal Victoria Goldsworthy Department of Chemistry, Ball State University, Muncie, IN 47304, USA

xx

Geneva LaForce Department of Chemistry, Ball State University, Muncie, IN 47304, USA Seth Abels Department of Chemistry, Ball State University, Muncie, IN 47304, USA Emil F. Khisamutdinov Department of Chemistry, Ball State University, Muncie, IN 47304, USA Rosemeire A. Silva Laboratory of Immunology, Heart Institute (InCor), Hospital das Clínicas da Faculdade de Medicina da Universidade de São Paulo, São Paulo 05403-000, Brazil Ricardo J. Giordano Chemistry Institute, Biochemistry Department, University of Sao Paulo, Sao Paulo 05508-000, Brazil Paulo S. Gutierrez Laboratory of Pathology, Heart Institute (InCor), Hospital das Clínicas da Faculdade de Medicina da Universidade de São Paulo, São Paulo 05403-000, Brazil Viviane Z. Rocha Clinical Division, Heart Institute (InCor), Hospital das Clínicas da Faculdade de Medicina da Universidade de São Paulo, São Paulo 05403-000, Brazil Martina Rudnicki Department of Clinical and Toxicological Analyses, Faculty of Pharmaceutical Sciences University of São Paulo, São Paulo 05508-000, Brazil Patrick Kee Division of Cardiology, Department of Internal Medicine, The University of Texas Health Science Center at Houston, Houston, TX 77054, USA Dulcinéia S. P. Abdalla Department of Clinical and Toxicological Analyses, Faculty of Pharmaceutical Sciences University of São Paulo, São Paulo 05508-000, Brazil

xxi

Pedro Puech-Leão Division of Vascular and Endovascular Surgery, University of São Paulo Medical School, São Paulo 05403-000, Brazil Bruno Caramelli Clinical Division, Heart Institute (InCor), Hospital das Clínicas da Faculdade de Medicina da Universidade de São Paulo, São Paulo 05403-000, Brazil Wadih Arap University of New Mexico Comprehensive Cancer Center, Division of Hematology/Oncology and Division of Molecular Medicine, Department of Internal Medicine, University of New Mexico School of Medicine Albuquerque, NM 87131, USA Renata Pasqualini University of New Mexico Comprehensive Cancer Center, Division of Hematology/Oncology and Division of Molecular Medicine, Department of Internal Medicine, University of New Mexico School of Medicine Albuquerque, NM 87131, USA José C. Meneghetti Medicine Nuclear Service and Molecular Image, Heart Institute (InCor), Hospital das Clínicas da Faculdade de Medicina da Universidade de São Paulo, São Paulo 05403-000, Brazil Fabio L. N. Marques Departamento de Radiologia e Oncologia, Faculdade de Medicina da Universidade de São Paulo (LIM43), São Paulo 05403-911, Brazil Menka Khoobchandani Institute of Green Nanotechnology, Department of Radiology and Chemistry, University of Missouri, Columbia, MO 65211, USA Kattesh V. Katti Institute of Green Nanotechnology, Department of Radiology and Chemistry, University of Missouri, Columbia, MO 65211, USA Ademar B. Lugão Nuclear and Energy Research Institute—IPEN/CNEN/São Paulo 05508-000, Brazil xxii

Jorge Kalil Laboratory of Immunology, Heart Institute (InCor), Hospital das Clínicas da Faculdade de Medicina da Universidade de São Paulo, São Paulo 05403-000, Brazil Muhammad Nadeem Department of Biotechnology, Quaid-i-Azam University, Islamabad, Pakistan Institute of Integrative Biosciences, CECOS University, Hayatabad, Peshawar, KP, Pakistan Duangjai Tungmunnithum Laboratoire de Biologie des Ligneux et des Grandes Cultures (LBLGC EA1207), Université d’Orléans, Pôle Universitaire d’Eure et Loir, Chartres, France Department of Pharmaceutical Botany, Faculty of Pharmacy, Mahidol University, Bangkok, Thailand Christophe Hano Laboratoire de Biologie des Ligneux et des Grandes Cultures (LBLGC EA1207), Université d’Orléans, Pôle Universitaire d’Eure et Loir, Chartres, France Bilal Haider Abbasi Department of Biotechnology, Quaid-i-Azam University, Islamabad, Pakistan Laboratoire de Biologie des Ligneux et des Grandes Cultures (LBLGC EA1207), Université d’Orléans, Pôle Universitaire d’Eure et Loir, Chartres, France Syed Salman Hashmi Department of Biotechnology, Quaid-i-Azam University, Islamabad, Pakistan Waqar Ahmad Department of Biotechnology, Quaid-i-Azam University, Islamabad, Pakistan Adnan Zahir Department of Biotechnology, Quaid-i-Azam University, Islamabad, Pakistan Xin Sun School of Environmental Science and Engineering, Collaborative Innovation Center for Marine Biomass Fibers, Materials and Textiles of Shandong Province, College of Automation and Electrical Engineering, Qingdao University, No. 308, Ningxia Road, Qingdao 266071, China xxiii

Xiaoyi Zhu School of Environmental Science and Engineering, Collaborative Innovation Center for Marine Biomass Fibers, Materials and Textiles of Shandong Province, College of Automation and Electrical Engineering, Qingdao University, No. 308, Ningxia Road, Qingdao 266071, China Xianfeng Yang Analytical and Testing Centre, South China University of Technology, Guangzhou 510640, China Jin Sun School of Environmental Science and Engineering, Collaborative Innovation Center for Marine Biomass Fibers, Materials and Textiles of Shandong Province, College of Automation and Electrical Engineering, Qingdao University, No. 308, Ningxia Road, Qingdao 266071, China Yanzhi Xia School of Environmental Science and Engineering, Collaborative Innovation Center for Marine Biomass Fibers, Materials and Textiles of Shandong Province, College of Automation and Electrical Engineering, Qingdao University, No. 308, Ningxia Road, Qingdao 266071, China Dongjiang Yang School of Environmental Science and Engineering, Collaborative Innovation Center for Marine Biomass Fibers, Materials and Textiles of Shandong Province, College of Automation and Electrical Engineering, Qingdao University, No. 308, Ningxia Road, Qingdao 266071, China Queensland Micro- and Nanotechnology Centre (QMNC), Griffith University, Nathan, Brisbane, QLD 4111, Australia Amin Boroumand Moghaddam Department of Bioprocess Technology, Faculty of Biotechnology and Biomolecular Sciences, Universiti Putra Malaysia, Serdang, Selangor 43400 UPM, Malaysia Farideh Namvar Institute of Tropical Forestry and Forest Products (INTROP), Universiti Putra Malaysia, Serdang, Selangor 43400 UPM, Malaysia Research Center for Animal Development Applied Biology & Department of Medicine, Mashhad Branch, Islamic Azad University, Mashhad 91735, Iran xxiv

Mona Moniri Department of Bioprocess Technology, Faculty of Biotechnology and Biomolecular Sciences, Universiti Putra Malaysia, Serdang, Selangor 43400 UPM, Malaysia Paridah Md. Tahir Institute of Tropical Forestry and Forest Products (INTROP), Universiti Putra Malaysia, Serdang, Selangor 43400 UPM, Malaysia Susan Azizi Department of Bioprocess Technology, Faculty of Biotechnology and Biomolecular Sciences, Universiti Putra Malaysia, Serdang, Selangor 43400 UPM, Malaysia Rosfarizan Mohamad Department of Bioprocess Technology, Faculty of Biotechnology and Biomolecular Sciences, Universiti Putra Malaysia, Serdang, Selangor 43400 UPM, Malaysia 2 Institute of Tropical Forestry and Forest Products (INTROP), Universiti Putra Malaysia, Serdang, Selangor 43400 UPM, Malaysia

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LIST OF ABBREVIATIONS AR

Antireflection

AFM

Atomic force microscopy

BAX

BCL-2-associated X protein

BSA

Bovine serum albumin

BET

Brunauer–Emmett–Teller

CMOS

Complementary Metal-Oxide-Semiconductor

DUV

Deep ultraviolet

DNMT

DNA methyltransferase

DIBL

Drain induced barrier lowering

DSSCs

Dye-sensitized solar cells

DLS

Dynamic Light Scattering

EAC

Ehrlich’s Ascites Carcinoma

EE

Encapsulation efficiency

EDS

Energy dispersive X-ray spectroscopy

EPR

Enhanced permeability and retention effect

EGFR

Epidermal growth factor receptor

EGCG

Epigallocatechin-3-gallate

EQE

External quantum efficiency

FBS

Fetal bovine serum

FE-SEM

Field emission scanning electron microscopy

FEM

Finite Element Method

FTIR

Fourier transform infrared spectroscopy

GAA

Gate-All-Around

HE

Hematoxylin–eosin

HCC

Hepatocellular carcinoma cells

HGF

Hepatocyte growth factor

HDP

High density plasma

HOMOs

Highest occupied molecular orbitals

HPLC

High performance liquid chromatography

HCAECs

Human coronary artery endothelialcells

HUVECs

human umbilical vein endothelial cells

IGFIR

Insulin-like growth factor I receptor

KACST

King Abdulaziz City for Science and Technology

LDH

Layered double hydroxide

LHE

Light harvesting efficiency

LC

Loading capacity

LGs

Logic gates

LUMO

Lowest unoccupied molecular orbital

MNP

Magnetic nanoparticle

MRI

Magnetic resonance imaging

MG

Malachite green

MMPs

Matrix metalloproteinases

MSCs

Mesenchymal stem cells

MOSFET

Metal-Oxide-Semiconductor field effect transistor

MB

Methylene blue

MIC

Minimum inhibitory concentration

MAPK

Mitogen-activated protein kinases

NC

Nanocrystals

NP

Nanoparticle

NDSSCs

Natural-dye-sensitized solar cells

NIR

Near infrared

NVM

Nonvolatile memory

NMR

Nuclear magnetic resonance

NAs

Nucleic acids

ONO

Oxide-nitride-oxide

pMBA

para-mercaptobenzoic acid

PTEN

Phosphatase and tensin homolog

PBS

Phosphate buffered saline

PVs

Photovoltaics

xxviii

PlGF

Placental growth factor

PAGE

Polyacrylamide gel electrophoresis

PCL

Polycaprolactone

PEG

Polyethylene glycol

PLA

Polylactic acid

PLL

Poly-L-lysine

PCR

Polymerase chain reaction

PVP

Polyvinylpyrrolidone

PCE

Power conversion efficiency

PSMA

Prostate-specific membrane antigen

QE

Quantum efficiency

QY

Quantum yield

RBS

Rutherford backscattering spectrometry

SEM

Scanning electron microscopy

SRCR

Scavenger receptor cysteine-rich

SAED

Selected area electron diffraction

SLN

Sentinel lymph node

SRH

Shockly-Reed-Hall

SONOS

Silicon-Oxide-Nitride-Oxide-Silicon

SPECT

Single-photon emission computed tomography

SWNT

Single wall nanotubes

SS

Subthreshold slope

SOD

Superoxide dismutase

SPIONs

Superparamagnetic iron oxide nanoparticles

SERS

Surface enhanced Raman scattering

SPR

Surface plasmon resonance

TMAH

Tetramethylammonium Hydroxide

TMS

Tetramethylsilane

TEC/TEG

Thermoelectric cooling/thermoelectric generation

TLC

Thin-layer chromatography

TEM

Transmission electron microscopy

TB

Trap-to-band xxix

TFET

Tunneling field effect transistor

VEGF

Vascular Endothelial Growth Factor

XRD

X-ray diffraction

XRF

X-ray fluorescence

XPS

X-ray photoelectron spectroscopy

xxx

PREFACE

This book comprises a collection of several articles providing insights and introduction to the common practices on the synthesis, characterization and application of nanomaterials in various fields ranging from medicine to electronics. The readers will also get a broad overview of the methods and commonly employed tools to gauge the properties of the nanomaterials. Chapters 1-8 describe the need for nanotechnology in different industrial sectors and laboratories and means of synthesizing these materials in a ecologically safe method. Chapter 1 describes methods to fabricate silicon nanowires from bulk using a top-down method. While Chapter 2 is a commentary justifying preparing sustainable nanomaterials and the related safety aspects concerned with it. Chapters 3-7 describe various methods of synthesizing nanomaterials using green methods and with some articles emphasizing on the characterization techniques such as X-ray diffraction, Scanning (Transmission) electron microscopy, Fourier transmission infrared resonance spectroscopy. Chapters 8-10 also highlight on the characterization techniques which span from detecting stem cells to plasmonic silver nanoparticles and photocatalytic degradation of organic pigments. Chapters 11-16 showcase the vast areas of applications for the nanomaterials synthesis by green nanotechnology which encompass cancer therapy, logic gates, molecular imaging, energy harvesting and storage devices such as batteries.

CHAPTER 1

VERTICAL SILICON NANOWIRE PLATFORM FOR LOW POWER ELECTRONICS AND CLEAN ENERGY APPLICATIONS

D.-L. Kwong1, X. Li1,2 , Y. Sun 1,2, G. Ramanathan1,2, Z. X. Chen1, S. M. Wong1,2, Y. Li1,3, N. S. Shen1, K. Buddharaju1, Y. H. Yu1,2, S. J. Lee1,3, N. Singh1, and G. Q. Lo1 1 Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research), 11 Science Park Road, Singapore 117685

Electrical and Electronics Engineering Department, Nanyang Technological University, Singapore 639798

2

Electrical and Computer Engineering Department, National University of Singapore, Singapore 117576

3

ABSTRACT This paper reviews the progress of the vertical top-down nanowire technology platform developed to explore novel device architectures and integration Copyright: D.-L. Kwong, X. Li, Y. Sun, et al., “Vertical Silicon Nanowire Platform for Low Power Electronics and Clean Energy Applications,” Journal of Nanotechnology, vol. 2012, Article ID 492121, 21 pages, 2012. https://doi.org/10.1155/2012/492121. Copyright: Copyright © 2012 D.-L. Kwong et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

2

Green Nanotechnology

schemes for green electronics and clean energy applications. Under electronics domain, besides having ultimate scaling potential, the vertical wire offers (1) CMOS circuits with much smaller foot print as compared to planar transistor at the same technology node, (2) a natural platform for tunneling FETs, and (3) a route to fabricate stacked nonvolatile memory cells. Under clean energy harvesting area, vertical wires could provide (1) cost reduction in photovoltaic energy conversion through enhanced light trapping and (2) a fully CMOS compatible thermoelectric engine converting waste-heat into electricity. In addition to progress review, we discuss the challenges and future prospects with vertical nanowires platform.

INTRODUCTION Since late 1990s, the nanowire has become a buzz word in nanoscience and nanotechnology domain with many promises, demonstrations and surprises in the technologically important and application-rich areas. For example, nanowire devices, especially in Gate-All-Around (GAA) architecture, have emerged as the front-runner for pushing Complementary Metal-OxideSemiconductor (CMOS) scaling beyond the roadmap. These devices offer unique advantages over their planar counterparts and other contenders, which make them feasible as an option for 15 nm and beyond technology nodes with sub-10 nm channel length devices already demonstrated through simulations [1] and experiments [2]. Indeed, the cylindrical geometry gives inverse logarithmic dependence of the gate capacitance on the channel diameter, and thus the gate length in these devices can be scaled with wire diameter without reducing the gate dielectric thickness aggressively. With the same principle, it also makes the GAA nanowire architecture an excellent candidate for Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) type nonvolatile memory applications where the gate dielectric has to be necessarily thicker. Chemical and biological sensing has been another important area where large surface to volume ratio enhances detection limit and make nanowire sensors as potential candidates [3, 4]. The giant piezo-resistive coefficient and reduced low frequency noise make the nanowires suitable for transducer world [5]. Nanowires have also shown excellent potential in the area of photonics [6], solar energy harvesting [7, 8], and energy storage [9]. Fundamentally, the improved properties of nanowire devices are a result of a combination of shape, density, and strong confinement of photon, phonon and electrons and their relative changes in reference to planar bulk structure.

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The fabrication technology of nanowire can be broadly categorized into two groups: (i) the bottom-up and (ii) the top-down. The bottom-up approaches involving synthesis of nanowires have been extensively reviewed in the literature [10–12] and are not discussed in further detail here. The top-down approach starts with pattern definition, mainly using conventional lithography, followed by pattern transfer and then trimming to reduce the diameter of the wire to nanoscale. Although isotropic wet etch can be used to trim the wire diameter, self-limiting oxidation process is generally used for better process control and has been extensively exploited at our institute [13]. In this paper, we review the progress of our top-down vertical nanowire technology platform from low power electronics and clean energy applications view point. A review of lateral nanowire platform focusing logic, nonvolatile memory, and biosensing applications has been published recently [13] and therefore will not be included here. The vertical platform resolves most of the fabrication-related challenges of lateral nanowires, for example, gate definition under the wire, gate etching on the wire, lithography, free gate length control and provides CMOS circuits with much smaller foot print as compared to any lateral (including planar, Fin, nanowire) MOS transistor at the same technology node. Being vertical, it decouples source/ drain (S/D) implant processes and therefore acts as a natural platform for tunneling FETs—allowing independent tuning of S/D junctions and implant type for achieving low subthreshold slope (SS) and suppressing ambipolar behavior. Nonvolatile memory devices on vertical wires have the potential to be stacked vertically along the wire length in addition to footprint benefit similar to the CMOS. Under the green electronics title, Section 2 discusses the scaling through vertical approach followed by our progress on three electronic devices, namely, Metal-Oxide-Semiconductor field effect transistor (MOSFET), Tunneling field effect transistor (TFET), and SONOS nonvolatile memory (NVM); all fabricated in GAA format. In Section 3, we discuss clean energy harvesting, where results on solar cell showing performance improvement through enhanced light trapping and absorption, and a fully CMOS compatible thermoelectric engine converting waste heat into electricity, are presented. The challenges and future prospects with vertical nanowires are discussed in Section 4. Finally, Section 5 summarizes the paper.

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LOW POWER ELECTRONICS Scaling Through Vertical Approach Vertical nanowire devices, having source, drain, and gate terminals on top of each other, occupy much less area than planar as described in Figure 1. In terms of half-pitch “𝐹”, generally the minimum lithographic printable feature size, a planar transistor occupies 8 𝐹2 while a vertical transistor can be designed in 4 𝐹2 thus reducing the foot print by 50% for a given technology node. When connected together to fabricate circuits, the impact is even more, for example, a CMOS inverter which uses 40 𝐹2 of area with planar devices can be fabricated in 12 𝐹2 using vertical nanowires, resulting in an area saving of about 70%. The area saving directly relates to improvement in speed and saving in power consumption through resistance “𝑅” and capacitances “𝐶”, both of which scale directly with area. The circuit speed being inversely proportional to “𝑅 𝐶”-constant increases by ~6.1 × (e.g., simply Speed ∝ 1 / 𝑅𝐶 ∝ ( Area )− 3/2). The power consumption, being proportional to 𝐶 𝑉2, reduces to 30% of the planar (e.g., Power ∝ 𝐶 𝑉2∝ (Area)). A summary of the area, speed, and power advantages with vertical nanowires devices as compared to planar and lateral nanowire is provided in Table 1. Worth mentioning here that these back-of-the envelop calculations do not take into account any parasitic. Table 1: Benchmarking of lateral and vertical nanowire devices with planar

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Journal of Nanotechnology Gate

Drain

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GND 2F Device area = 2F × 2F = 4F 2 Inverter area = 6F × 2F = 12F 2

Figure 1: Schematic illustration of the footprint of (a) lateral and (b) vertical GAA nanowire MOSFET and corresponding CMOS inverters.

Figure 1: Schematic illustration of the footprint of (a) lateral and (b) vertical GAA nanowire MOSFET and corresponding CMOS inverters.

is generally used for better process control and has been prospects with vertical nanowires are discussed in Section 4. extensively exploited at our institute [13]. scaling potentialFinally, the paper. Despite the same fromSection gate5 summarizes control perspective as In this paper, we review the progress of our top-down for lateral wire, the vertical wireelecdevice2.takes lead over lateral wire in foot vertical nanowire technology platform from low power Low Power Electronics tronics andprint clean energy applications view point. A reviewand of power advantage. Indeed the lateral scaling followed by speed 2.1. Scaling Through Vertical Approach. Vertical nanowire lateral nanowire platform focusing logic, nonvolatile memwire device foot print remains 8𝐹2, thedevices, samehaving as planar device. At terminals circuit on top of source, drain, and gate ory, and biosensing applications has been published recently each other,better occupy much area than planar asas described in [13] and therefore will not be included The vertical level, however, lateral here. nanowire can do little thanless planar device Figure 1. In terms of half-pitch “F”, generally the minimum platform resolves most of the fabrication-related challenges it can allow current matching with stacking of lateral wires, for example, lithographic printable feature size, a planar transistor occuof lateral nanowires, for example, gate definition under the forming twowire, wires out offree a Fin using channel for PMOS but in 4F 2 while as a vertical transistor can be designed 8F 2 both wire, gate etching on the lithography, gate[14] lengthand pies thus reducing the foot print by 50% for a given technology control and provides circuits with much smaller only one CMOS for NMOS. In contrast, the current matching in vertical devices is node. When connected together to fabricate circuits, the foot print as compared to any lateral (including planar, Fin, possible with gate-length scaling without penalty foot Further, impact is evenon more, for print. example, a CMOS the inverter which nanowire) MOS transistor at the same technology node. 2 of area with planar devices can be fabricated in uses 40F Being vertical, it decouples source/drain (S/D) implant pro- design vertical approach is a route to resolve and fabrication issues related to 12F 2 using vertical nanowires, resulting in an area saving of cesses and therefore acts as a natural platform for tunneling lateral nanowires. example, uniform is a challenge astothe about 70%. Thegate area saving directly relates improvement FETs—allowing independent tuningFor of S/D junctionsdefining and in not speed and saving in power through resisimplant type for achieving low subthreshold (SS) may shadowing effects in plasma slope etching allow clearing theconsumption gate material tance “R” and capacitances “C”, both of which scale directly and suppressing ambipolar behavior. Nonvolatile memory the have lateral nongated regions. nanowire transistors are with area.GAA The circuit speed being inversely proportional to devices onbeneath vertical wires the potential to be stacked Vertical × (e.g., issue simply Speed ∝ “RC”-constant increases by ∼6.1 effect vertically along the wire length in addition to footprint benanticipated to be promising candidates as there is no shadowing efit similar to the CMOS. Under the green electronics title, (Area)−3/2 ). The power consumption, being proporand the gate length can be defined by1/RC the∝film deposition and etch back Section 2 discusses the scaling through vertical approach tional to CV 2 , reduces to 30% of the planar (e.g., Power ∝ thanonlithography. followed byrather our progress three electronic devices, namely, CV 2 ∝ (Area)). A summary of the area, speed, and power Metal-Oxide-Semiconductor field effect transistor (MOSadvantages with vertical nanowires devices as compared to FET), Tunneling field effect transistor (TFET), and SONOS planar and lateral nanowire is provided in Table 1. Worth Feasibility nonvolatileIntegration memory (NVM); all fabricated in GAA format. mentioning here that these back-of-the envelop calculations In Section 3, we discuss clean energy harvesting, where do not take into account any parasitic. GAA vertical nanowire CMOS transistors testscaling vehicle to develop results on We solarused cell showing performance improvement Despite the as same potential from gate control through enhanced light trapping and absorption, and a fully perspective as for lateral wire, the vertical wire device takes CMOS compatible thermoelectric engine converting waste lead over lateral wire in foot print scaling followed by speed heat into electricity, are presented. The challenges and future and power advantage. Indeed the lateral wire device foot

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Green Nanotechnology

vertical platform on 8′′ silicon wafers [15]. The fabrication process steps of which are illustrated in Figure 2. Shown in Figure 3 are scanning electron microscopy (SEM) images taken as various fabrication stages. Circular resist dots of different diameters (from 160 nm to 600 nm) were patterned using deep ultraviolet (DUV) lithography followed by 1 μm deep Si etch with SF6 chemistry under resist mask. The etch depth can be tuned depending upon the device design. Si pillars were then oxidized at 1150°C to be converted into nanowires. High temperature was used to decrease the viscosity of grown oxide, ensuring smooth cylindrical Si core at the center of the pillar. The oxidation rate at the bottom of the pillar was low due to increased stress at high curvature [16, 17]. The grown oxide was then stripped in diluted HF (DHF). The SEM images of nanowire thus fabricated are shown in Figures 3(a) and 3(d).

Figure 2: (a) Single silicon nanowire with bottom isolation, (b) after gate stack deposition, (c) after gate extension pad definition and HDP oxide deposition followed by etch back defining gate length, (d) after poly-silicon end cap removal, (e) removal of oxide followed by S/D and gate implant (single implant for all three electrodes), (f) final device after metalization. (Reprinted with permission from [15]. [2008] IEEE.)

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Figure 3: SEM pictures at different stages of device fabrication. (a) Vertical nanowire with diameter ~20 nm; (b) after gate patterning by lithography but before exposing the drain (the tip of the pillar) of the transistor; (c) after the drain (pillar tip) is exposed, ready for taking metal contacts, (d) vertical nanowire arrays with pitch of 500 nm. Nanowires are 1 μm tall with a diameter of ~20 nm. (Reprinted with permission from [15]. [2008] IEEE.).

Vertical nanowire formation was followed by a 250 nm thick layer of high density plasma (HDP) oxide deposition and wet etch-back using DHF (1 : 25). The HDP deposition resulted in thicker oxide on the bottom surface and thinner oxide along the nanowire sidewalls due to the nonconformal deposition. After wet etch-back ~150 nm, thick oxide remained to cover the footing of the vertical standing wire. This technique separates the gate electrode from the source extension pad and thus reduces the gate to source fringing capacitance. Gate oxide of ~5 nm was then thermally grown on the exposed wire surface, followed by deposition of 30 nm poly-Si, which serves as the gate electrode (Figure 3(b)). Gate pad was then patterned and

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Green Nanotechnology

etched under resist mask which covers the nanowire and provide a poly extension for gate contact. After gate pad etching, the process of HDP oxide deposition followed by wet etch back was repeated to access the poly on top of nanowire while protecting the gate pad defined earlier. The exposed polySi was then isotropically etched by low RF power SF6plasma. Alternatively, this cap could be removed in wet Tetramethylammonium Hydroxide (TMAH) solution. The oxide on the wafer was then completely stripped in DHF (Figure 3(c)), and As (1 × 1015 cm−2/10 keV) was implanted four times from four directions, 90 degrees apart, with large tilt angle (45 degree) It was followed by a rapid thermal annealing and standard metallization process. Figure 4 shows typical characteristics from NMOS of channel diameter ~20 nm and PMOS of channel diameter ~40 nm, both having channel length of 150 nm. The device displayed very good performance with steep turnon (SS~75 to 100 mV/dec), strong gate electrostatic control (extremely low Drain induced barrier lowering (DIBL) (10 to 50 mV/V)), and high 𝐼on/ 𝐼off ratio (~107). However, the threshold voltage 𝑉th, with poly-Si gate is much lower than required to integrate these devices into circuits [18–21].

Figure 4: Transfer characteristics of GAA n- and p-FETs showing near ideal subthreshold swing indicating the excellent electrostatic control.

Due to the small channel volume, conventional channel doping proves difficult with nanowires and may result in significant 𝑉th fluctuation due to dopant fluctuations in addition to mobility degradation. A better method of

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𝑉th adjustment is through gate work function tuning. We have implemented NiSi fully silicided (FUSI) and TiN gates, both with undoped nanowire channel. TiN is found to provide better symmetry for N and P devices, however, on the other hand, FUSI gate showed tenability with implant in gate poly-Si. Figure 5 presents SEM image of FUSI gate device and 𝑉th values of both the TiN and FUSI gate devices.

Figure 5: (a) A scanning electron microscope (SEM) image of an FUSI gate device after silicidation (440°C, 30 s) and removal of un-reacted Ni in H2SO4:H2O2:H2O solution. (b) Box plots of the 𝑉th distribution of measured devices for each split. 𝑉th extraction using linear extrapolation was done for over 10 devices in each split.

The 𝑉th-adjusted devices show distinct 𝑉th shifts (Δ 𝑉th) relative to each other as can be seen in Figure 5(b). The TiN PMOS and poly-gate NMOS have the lowest 𝑉t h (~−0.38 V and −0.22 V), followed by the tuned FUSI gate device (~−0.15 V) and the FUSI gate device (~0.07 V), while TiN NMOS has the highest 𝑉th (~0.42 V). The TiN gate shows great potential in adjusting 𝑉th for vertical SiNW MOSFETs to allow them to be integrated into low standby power circuits.

Turning MOSFET into Tunneling FET Scaling of MOSFET to improve device performance and increase device density faces enormous challenges beyond the 22 nm node due to excessive increase in passive power. This arises due to the nonscalability of the SS that limits further reduction in MOSFET threshold voltage, 𝑉th, and hence supply voltage, 𝑉dd. To overcome this problem and to design more energy-efficient

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Green Nanotechnology

devices, alternative transistor designs with low SS are needed. One of such devices is the TFET [22–28]. Unlike the MOSFET, which utilizes thermionic injection of carriers, TFET uses tunneling as the carrier injection mechanism. Therefore, it is possible for TFET to achieve low OFF state current as well as SS below the theoretical limit of 60 mV/decade for MOSFETs at room temperature. TFETs are essentially gated p+ −i −n+ diodes working under reverse bias and can operate as n- or p-TFETs. By controlling the i region with a gate, a tunneling barrier can be created either at the p+ −i (n-TFET, 𝑉𝐺> 0) or n+ −i (p-TFET, 𝑉𝐺< 0) junctions where carriers are able to tunnel through as shown in Figure 6(a) using band structure [27]. The reversebiased p–i–n diode gives the TFET the low OFF-state diffusion current.

Figure 6: (a) Band diagram of TFET showing tunneling junction, (b) 𝐼𝑑- 𝑉𝑔 and characteristics of a vertical SiNW TFET with diameter 70 nm, gate length 200 nm and gate oxide thickness 4.5 nm. (Reprinted with permission from [28]. [2009] IEEE.).

Leveraging on our vertical nanowire platform, tunneling FETs are fabricated similar to MOSFET using the same mask sets but with opposite type of source/drain doping. We used nitride hard mask to protect the wire top while implanting the bottom electrode. Shown in Figure 6(b) is the 𝑛-TFET 𝐼𝑑- 𝑉𝑔 curves obtained from a device with diameter ~70 nm, gate oxide thickness 4.5 nm, and gate length 200 nm. Excellent 𝐼on/ 𝐼o f fratio at 𝑉𝑛+= 1 . 2 V is observed (~107), with an 𝐼off (at 𝑉𝑔= 0 V) of ~7 pA/μm and 𝐼on (at 𝑉𝑔= 1 . 2 V) of ~53 μA/μm (normalised with the wire circumference). The resulting record high 𝐼on and low DIBL (~17 mV/V) for this Si TFET is a result of the excellent gate control of the GAA nanowire structure. However, the obtained SS of 70 mV/dec is beyond the limit of kT/q (≈60 mV/dec), likely due to the tunneling junction (𝑝 + − 𝑖) not being perfectly abrupt. To achieve SS < KT/q limit, we improve the abruptness of tunneling junction through

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a novel silicidation induced dopant segregation process [29] depicted in Figure 7. To demonstrate this experimentally, we used nanowires with height of 400 nm and diameter ranging from 30 to 200 nm. Afterwards, the bottom part of the nanowire was vertically implanted with BF2 for pTFETs and with As for nTFETs to form the drain regions of the TFETs. Isolation and gate stack was formed similar to presented for MOSFET. Then Source was implanted with As for pTFETs and BF2 for nTFETs and thereafter followed by silicidation, which segregated the dopants to form abrupt source/channel junction. Finally, contact metallization was done.

Figure 7: Vertical Silicon nanowire TFET process flow schematic. (a) Vertical pillar etch and As implantation to form the drain region, (b) isolation oxide deposition and gate stack formation, (c) the top amorphous-Si etched to expose source side of TFET, (d) source implanted with BF2, (e) dopant segregated Ni

Green Nanotechnology

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silicidation, (f) contact opening and Al metallization. (Reprinted with permission from [29] [2011] IEEE.).

The transmission electron microscopy (TEM) image showing vertical section of the fabricated p-TFET device is presented in Figure 8.

Figure 8: Cross-sectional TEM of pTFET showing a very narrow uniform wire surrounded with gate and silicide at top. 8

Journal of Nanotechnology 1E − 9

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Figure 9 shows the 𝐼𝑑- 𝑉𝑔 characteristics for both pTFET and nTFET, respectively. SS of 30 mV/decade averaged over a decade of drain current is obtained for both pTFET and nTFET devices. Improvement is due to the sharp doping profile at the source side as a result of dopant segregated silicidation, which causes dopants to pile up at the silicide edge [30, 31]. 8 Journal of Nanotechnology Suppression of ambipolar conduction is also achieved because of natural 1E − 9 1E − 8 asymmetry of the vertical nanowire platform, which facilitates independent tuning 1E − 9 of source and drain. 1E − 10 Id (A)

Id (A)

SS distribution with drain current is presented in Figure 10(a). SS below 1E − 10 − 11 drain current for pTFET and for 60 mV/decade is achieved for 3 decades1Eof 1E − 11 more than 2 decades in the case of nTFET. The difference in SS behavior 1E − 12 of pTFET and nTFET may arise because of the difference in the dopant 1E − 12 segregation betweenSS ∼As and BF2 and wafer to wafer process variations. 30 mV/dec SS ∼30 mV/dec 1E − 13 13 The1E −impact on nanowire diameter on SS is presented in Figure 10(b); SS degrades with the increase of channel diameter. When channel gets wider, 1E − 14 1E − 14 0 0.5 1 2 −1.5 −control 1 −0.5 the gate−2 electrostatic on the 0channel region gets weaker or1.5 behaves V (V) V (V) more like a Vplanar device. Moreover, for larger wires, the encroachment = −0.1 V V = −0.1 V of NiSi into the wire is reduced, therefore, dopant gradient at the source(a) (b) Figure interface 9: (a) Measured I is -V less characteristics of (a)and p-TFEThence and (b) n-TFET = 30 mV/decade averaged over a decade. channel steep, thewith SSSS degrades. g

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Figure 10: (a) SS versus Id for TFETs. p-TFET exhibits sub-60 mV/decade swing for 3 decades of Id , while n-TFET maintained sub60 mV/decade for more than 2 decades of Id (Vds = 0.1 V). (b) SS variations on nanowire diameter of p-TFETs. SS increases as NW diameter gets wider.

Figure 10: (a) SS versus 𝐼d for TFETs. p-TFET exhibits sub-60 mV/decade swing for 3 decades of 𝐼d, while n-TFET maintained sub-60 mV/decade for 2.4. Vertical Nanowire-Based Memory. Market thickness, pTFET2has underlap ofof ∼35𝐼nm more than decades (𝑉while = nTFET 0 . 1has V). (b) SS variations onNonvolatile nanowire diameter d dson drain side of the nonvolatile memory has been booming persistently large underlap of ∼100 nm. Large underlap seems to be one of the reasons suppressingas the NW ON current of due gets to increasing demand of the portable electronic devices. of p-TFETs. SS increases diameter wider. nTFET. Optimum gate-drain underlap is required to further suppress ambipolar conduction as well as to maximize ON current.

It is currently dominated by flash memory having polysilicon floating gate as the charge storage material. The

By using higher permittivity (high-𝜅) dielectric floatinggate gate memory, however, isand facing low-bandgap rigorous challenges materials at tunneling interface, ON current can be further enhanced [32,

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Green Nanotechnology

33]. We also noted the difference in ON current between our pTFET and nTFET devices, that is because of the difference in the gate-drain underlap thickness, pTFET has underlap of ~35 nm while nTFET has large underlap of ~100 nm. Large underlap on drain side seems to be one of the reasons suppressing the ON current of nTFET. Optimum gate-drain underlap is required to further suppress ambipolar conduction as well as to maximize ON current.

Vertical Nanowire-Based Nonvolatile Memory Market of the nonvolatile memory has been booming persistently due to increasing demand of the portable electronic devices. It is currently dominated by flash memory having poly-silicon floating gate as the charge storage material. The floating gate memory, however, is facing rigorous challenges in the course of scaling beyond the 22 nm technology node because of significantly reduced coupling ratio and increased gate interference [34]. To overcome the scaling issues, the discrete charge trapped devices are being investigated widely. These devices use charge trapping materials such as silicon nitride, high-𝜅 dielectric, and metal/silicon nanocrystals in place of conductive poly-Si floating gate and have simple fabrication process, lower programming voltage, and robust tolerances to defects in the thin tunnel oxide [35–40]. However, in discrete charge trap devices the gate dielectric thickness, for example, oxide-nitride-oxide (ONO) in case of silicon nitride as trap layer, is hard to scale due to the data retention concerns, and therefore it is difficult to avoid concomitant problems of severe short channel effects with scaling. From transistor structure view point, the cylindrical architecture relaxes the requirement for ultrathin gate oxide and therefore is promising for SONOS-type nonvolatile memory, where thicker tunnel/block oxide is favored for longer retention time [41]. Apart from the superior gate control and electric field enhancement at tunnel oxide to channel interface, observed from the lateral- nanowire-based GAA SONOS cell [42], memory cell fabricated on vertical nanowires platform has more implication due to its small foot print and potential for 3D multilevel integration [43]. In our recent work, we fabricated a gate-all-around (GAA) SONOS flash memory on a vertical Si nanowire (SiNW) of diameter of 20 nm as the channel and presented excellent program/erase (P/E), retention, and endurance characteristics [44]. The performance was further improved by replacing the charge trap layer with silicon nanocrystals (NC). The fabricated cells were

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an important building-block towards three-dimensional (3D) multilevel integration for ultrahigh density application. Though looks simple, vertical stacking of memory cells could be very challenging in forming junctions on nanowires between the cells. To overcome the junction formation issue, we also designed and fabricated a novel junction-less vertical SiNW-based SONOS cell. Being free of doped junctions, the junction-less (JL) memory device makes vertical SiNW a suitable platform for vertical stacking of memory cells to achieve ultra-high density application. The fabrication steps of our memory cells are sketched in Figure 11 and their detail are available in [45]. Just to highlight here, the JL-SONOS process was started with phosphorus implantation in p-type Si wafer followed by furnace annealing to create a uniform doping profile with different concentrations in the upper portion of the substrates. After that it follows the process flow of conventional junction-based vertical SiNW SONOS to form the wire channel and p-type doped poly-Si gate without S/D implantation, as shown in Figure 11(b). The absence of junctions on wire allows easy stacking of multiple cells on a nanowire. Journal of Nanotechnology As implant

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Figure 11: (a) Process integration flow of vertical SiNW junction-based NC-Flash: (a-1) vertical SiNW formation; (a-2) As is implanted to form the source; (a-3) gate stack deposition (O-N-O or O-NC-O for SONOS and NC-flash, resp.) and gate pad definition; (a-4) tip poly and Figure O-NC-O removal, followed by drainintegration implant; (a-5) metallization; process integration of vertical JL-SONOS: (b-1) bulk 11: (a) Process flow of (b) vertical SiNW flow junction-based NCimplant and annealing; (b-2) vertical SiNW formation; (b-3) gate stack deposition and gate pad definition; (b-4) tip poly and ONO removal; Flash: (a-1) SiNW formation; (a-2) As is during implanted tosteps form source; (b-5) metallization; (c) tiltedvertical top view SEM image of SONOS/JL-SONOS fabrication key process (left the to right): vertical SiNW formation; gate pad definition; tip poly and ONO removal; metallization. (Reprinted with permission from [45]. [2011] IEEE.)

(a-3) gate stack deposition (O-N-O or O-NC-O for SONOS and NC-flash, resp.) and gate pad definition; (a-4) tip poly and O-NC-O removal, followed by drain in the course of scaling beyond the 22 nm technology node integration characteristics [44]. was further improved implant; (a-5) metallization; (b) process flowThe ofperformance vertical JL-SONOS: because of significantly reduced coupling ratio and increased by replacing the charge trap layer with silicon nanocrystals (b-1) bulk implant and annealing; (b-2) vertical SiNW formation; (b-3) gate gate interference [34]. To overcome the scaling issues, the (NC). The fabricated cells were an important buildingdiscrete charge trapped devices are being investigated widely. These devices use charge trapping materials such as silicon nitride, high-κ dielectric, and metal/silicon nanocrystals in place of conductive poly-Si floating gate and have simple fabrication process, lower programming voltage, and robust tolerances to defects in the thin tunnel oxide [35–40]. However, in discrete charge trap devices the gate dielectric thickness, for example, oxide-nitride-oxide (ONO) in case

block towards three-dimensional (3D) multilevel integration for ultrahigh density application. Though looks simple, vertical stacking of memory cells could be very challenging in forming junctions on nanowires between the cells. To overcome the junction formation issue, we also designed and fabricated a novel junction-less vertical SiNW-based SONOS cell. Being free of doped junctions, the junction-less (JL) memory device makes vertical SiNW a suitable platform

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Green Nanotechnology

stack deposition and gate pad definition; (b-4) tip poly and ONO removal; (b-5) metallization; (c) tilted top view SEM image of SONOS/JL-SONOS fabrication during key process steps (left to right): vertical SiNW formation; gate pad definition; tip poly and ONO removal; metallization. (Reprinted with permission from [45]. [2011] IEEE.).

Shown in Figure 12(a) is a cross-sectional TEM image of a vertical SiNW GAA JL-SONOS with wire diameter equals to 20 nm and gate length of ~120 nm. Figure 12(b) shows the cross-sectional TEM image of the gate stack with ONO thickness 5/7/7 nm. An atomic force microscopy (AFM) image over 1 μm × 1 μm area of the nanocrystals deposited on tunnel oxide (in case of NC-flash) is shown in Figure 12(c). It reveals good uniformity and isolation between Si-NCs, although the size is big (~30 ± 10 nm in diameter) and density is low (around 7.5 × 1010/cm−2), indicating lot of room for further improvement. The effect of embedding SiNCs as trapping layer is illustrated in Figure 13(a) by comparing the P/E speed of NC-SOncOS with the control SiN-SONOS cell, both on 50 nm thick wire. The NC-SOncOS shows larger Δ 𝑉th for the same P/E time period, indicating a better charge storage capability. The results indicate that the trapping centers in devices using silicon nanocrystals as charge trapping medium are superior than that of SiN, which enhances the trapping efficiency of the devices. Journal of Nanotechnology

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Figure 12: (a) Cross-sectional TEM image of vertical SiNW GAA JL-SONOS: diameter of wire is 20 nm and gate length 120 nm, (b) Crosssectional TEM image of gate stack showing ONO thickness 5/7/7 nm. (c) AFM image scanned on 1 × 1 μm2 surface area that reveals the formation of Si-NC with a density of 7.5 × 1010 /cm−2 . (Reprinted with permission from [45]. [2011] IEEE.)

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5 nm Power Electronics and .... Vertical Silicon Nanowire Platform for Low (a)

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Figure 12: (a) Cross-sectional TEM image of vertical SiNW GAA JL-SONOS: diameter of wire is 20 nm and gate length 120 nm, (b) Cross2 surface area that reveals the sectional TEM image of gate(a) stack showing ONO thickness 5/7/7 nm. (c) of AFM image scanned on GAA 1 × 1 μm Figure 12: Cross-sectional TEM image vertical SiNW JL-SONOS: formation of Si-NC with a density of 7.5 × 1010 /cm−2 . (Reprinted with permission from [45]. [2011] IEEE.)

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after 10 seconds 85 C retention for which the devices were programmed at 15 V for 100 μs and erased at −18 V for 1 ms. Incorporating SiNCs into the trap layer can significantly Solid: PGM Open: ERS 4 SiNW diameter = 50 nm improve the charge loss by forming isolated energy wells due to conduction band offset [46] between Si and dielectrics. As shown in Figure 13(b), after SiNCs incorporation, the reten3 tion characteristics show great improvement and negligible memory loss was observed after 105 seconds retention at 2 ◦ C. Excellent endurance properties have been obtained for 85 both SiN-SONOS and NC-Flash devices. The characteristics of junction-less cells are presented 1 next. Figure 14 illustrates the P/E characteristics of JLSONOS with channel doping of 1 × 1017 cm−3 and 1.5 V 2.4 V

ΔVth (V)

in Figure 12(c). It reveals good uniformity and isolation between Si-NCs, although the size is big (∼30 ± 10 nm in 5 diameter) and density is low (around 7.5 × 1010 /cm−2 ), SiNW diameter = 50 nm 4 g = 15 V) improvement. The effect indicating lot of roomPGM for(Vfurther 3 of embedding SiNCs as trapping layer is illustrated in 2 Figure 13(a) by comparing the P/E speed of NC-SOncOS with the control SiN-SONOS cell, bothSolid: on SOncOS 50 nm thick wire. 1 Open: SONOS the same P/E time The NC-SOncOS shows larger ΔVth for 0 period, indicating a better charge storage capability. The −1 results indicate that the trapping centers in devices using −2 silicon nanocrystals as charge trapping medium are superior 3 than that of SiN, −which enhances ERS (Vg = −16 V) the trapping efficiency of the devices. −4

Vth (V)

diameter of wire is 20 nm and gate length 120 nm, (b) Cross-sectional TEM image of gate stack showing ONO thickness 5/7/7 nm. (c) AFM image scanned on 1 × over 1 μm1 2μm surface the formation density of 7.5 (AFM) image × 1 μmarea area that of thereveals nanocrystals As canofbeSi-NC seen in with Figure a13(b), a partial window closure 10 −2 projected afterIEEE.). 10 years) is observed for SiN-SONOS deposited on tunnel oxide (in case of NC-flash) is shown from (∼30% /cm . (Reprinted with permission [45]. [2011] × Journal 10 of Nanotechnology 11 5 ◦

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SOncOS (PGM: 15 V 1 ms, ERS: −16 V 10 μs) SONOS (PGM: 15 V 100 μs, ERS: −18 V 10 ms) (a)

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Figure 13: (a) Comparison of P/E speed between vertical SiNW-based NC-SOncOS and SiN-SONOS, with gate length of 150 nm and wire diameter of 50 nm. (b) Retention characteristics at 85◦ C for vertical SiNW-based GAA SONOS and NC-SOncOS. (Reprinted with permission from [45]. [2011] IEEE.)

Figure 13: (a) Comparison of P/E speed between vertical SiNW-based NCSOncOS and SiN-SONOS, with gate length of 150 nm and wire diameter of 50 nm.7 (b)Doping Retention 0 for vertical SiNW-based GAA SOconcentration: characteristics at 85°C 6 Solid = 10 /cm NOS and (Reprinted with permission from [45]. [2011] IEEE.). ONC-SOncOS. pen = 10 /cm 17 19

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As4 can be seen in Figure 13(b), a partial window closure (~30% projected −2 after 10 years) is observed for SiN-SONOS after 105 seconds 85°C retention 3 2

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5 for which the devices were programmed at 15 V for 100 μs and erased at SiNW diameter = 50 nm PGM Open: ERS 4 (V = 15 V) −18 V for 1PGMms. Incorporating SiNCs into 4the Solid: trap layer SiNW diameter = 50 nmcan significantly 3 improve the charge loss by forming isolated energy wells due to conduction 2 band offset [46] between Si and dielectrics. 3As shown in Figure 13(b), after Solid: SOncOS 1 Open: SONOS SiNCs incorporation, the retention characteristics show great improvement 0 2 and negligible memory loss was observed after 105 seconds retention at −1 −2 85°C. Excellent endurance properties have1 been obtained for both SiN−3 V ERS ( = − 16 V) SONOS and NC-Flash devices. 1.5 V 2.4 V

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10 10 10 10 10 10 10 10 10 10 10 The characteristics of junction-less cells are10presented next. Figure 14 10 years Time (s) Pulse time (s) illustrates the P/E characteristics of JL-SONOS with channel doping of 1 × SOncOS 17 −3 19 −3 (PGM: 15 V 1 ms, ERS: −16 V 10 μs) 10 cm and 1 × 10 cm , respectively, for a fixed wire diameter of 20 nm. SONOS For both the doping concentrations, the memory window nearly same, −18 V 10 ms) (PGM: 15 V 100 μs, ERS:is 17 −3 more precisely, 3.2 V for low doped (1 × 10 cm ) and 2.7(b)V for moderately (a) when P/ESiNW-based time NC-SOncOS of 1 msandwas usedwithatgate+15 V/−16 V,wire doped ×Comparison 1019 cmof −3 Figure(1 13: (a) P/E),speed betweena vertical SiN-SONOS, length of 150 nm and diameter of 50 nm. (b) Retention characteristics at 85 C for vertical SiNW-based GAA SONOS and NC-SOncOS. (Reprinted with permission respectively. from [45]. [2011] IEEE.) −8

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Figure 14: (a) Programming and (b) erasing characteristics using FN tunneling of vertical SiNW-based GAA JL-SONOS memory device with channel doping of 1 × 1017 cm−3 and 1 × 1019 cm−3 . (Reprinted with permission from [45]. [2011] IEEE.)

Figure 14: (a) Programming and (b) erasing characteristics using FN tunneling of vertical JL-SONOS device doping 3 , respectively, for GAA 1 × 1019 cmSiNW-based a fixed wire diameter of memory 1019 cm 3 ), when a P/Ewith time ofchannel 1 ms was used at +15 V/ 17 both−3the doping concentrations, −16 V, respectively. memory of 120×nm. 10For cm and 1 × 1019 cm−3.the(Reprinted with permission from [45]. [2011] window is nearly same, more precisely, 3.2 V for low doped Shown in Figure 15 is the feasibility on the multibit IEEE.). (1 × 1017 cm 3 ) and 2.7 V for moderately doped (1 × programming for the JL-SONOS measured on cell with −

−

−

Shown in Figure 15 is the feasibility on the multibit programming for the JL-SONOS measured on cell with doping 1 × 1019 cm−3. As obvious from the figure, the memory cell is able to store 2 bits per cell using four states “00”, “01”, “10”, and “11” with each state defined a different 𝑉th of >1 V.

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Figure 15: Multibit programming characteristics of JL-SONOS memory with a gate biases of 12, 14, and 16 V for 1 ms. Wire diameter = 20 nm, channel doping = 1 × 1019 /cm−3 . (Reprinted with permission from [45]. [2011] IEEE.)

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The high temperature retention characteristic at 85°C for JL-SONOS 5.5 is shown in Figure 16(a). The JL-SONOS with high channel doping (1 × 19 −3 Solid: PGM 10 cm ) exhibits less 𝑉th degradation as compared to lightly doped JLSolid: PGM 5 Open: ERS Open: ERS up SONOS (1 × 1017 cm−3), and its memory window can be well maintained to 105 sec. Under retention conditions, 4.5direct trap-to-band (TB) tunneling from a nitride traps to the channel conduction band is the main discharge 4 mechanism. With increased channel doping, the energy states close to the 3.5 channel conduction band are more likely to be occupied by electrons. This reduces the probability of further electron injection from the trap layer, 0 3 10 101 10 2 103 10 4 105 10 6 10 101 10 2 103 10 4 105 and thus moreTime reliable charge storage can be expected [47]. The endurance (s) Cycle (numbers) ) JL-SONOS: ( 1017/cm characteristic of−3JL-SONOS is shown Figure 16(b), in which all devices can (PGM: 16 V 1 ms, ERS: −15 V 100 μs) JL-SONOS: ( 1017/cm−3) maintain the P/E window after 105 cycles at 85°C. Vth (V)

6.5

Figure 15: Multibit programming characteristics of JL-SONOS memory with a gate biases of 12, 14, and 16 V for 1 ms. Wire diameter = 20 nm, channel doping 6.5 = 1 × 1 019/cm−3. (Reprinted with permission from [45]. [2011] IEEE.).

JL-SONOS: (1019/cm−3 ) (PGM: 15 V 1 ms, ERS: −16 V 1 ms)

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(PGM: 16 V 1 ms, ERS: −15 V 100 μs) JL-SONOS: (1019/cm−3 ) (PGM: 15 V 1 ms, ERS: −16 V 1 ms) (b)

Figure 16: (a) Retention characteristic at 85◦ C for JL-SONOS memory device with channel doping of 1 × 1017 cm−3 .and 1 × 1019 cm−3 . (b) Endurance characteristic at 85◦ C for JL-SONOS memory device with channel doping of 1 × 1017 cm−3 .and 1 × 1019 cm−3 . (Reprinted with permission from [45]. [2011] IEEE.)

doping 1 × 1019 cm−3 . As obvious from the figure, the memory cell is able to store 2 bits per cell using four states “00”, “01”, “10”, and “11” with each state defined a different Vth of >1 V. The high temperature retention characteristic at 85◦ C for JL-SONOS is shown in Figure 16(a). The JL-SONOS

with high channel doping (1 × 1019 cm−3 ) exhibits less Vth degradation as compared to lightly doped JL-SONOS (1 × 1017 cm−3 ), and its memory window can be well maintained up to 105 sec. Under retention conditions, direct trap-toband (TB) tunneling from a nitride traps to the channel conduction band is the main discharge mechanism. With

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Figure 15: Multibit programming characteristics of JL-SONOS memory with a gate biases of 12, 14, and 16 V for 1 ms. Wire diameter = 20 nm, channel doping = 1 × 1019 /cm−3 . (Reprinted with permission from [45]. [2011] IEEE.) 6.5

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JL-SONOS: (1019/cm−3 ) (PGM: 15 V 1 ms, ERS: −16 V 1 ms) (b)

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Figure 16: (a) Retention characteristic at 85◦ C for JL-SONOS memory device with channel doping of 1 × 1017 cm−3 .and 1 × 1019 cm−3 . (b) Endurance characteristic at 85◦ C for JL-SONOS memory device with channel doping of 1 × 1017 cm−3 .and 1 × 1019 cm−3 . (Reprinted with permission from [45]. [2011] IEEE.) 17 −3 19 −3

Figure 16: (a) Retention characteristic at 85°C for JL-SONOS memory device with channel doping of 1 × 10 cm .and 1 × 10 cm . (b) Endurance characteristic 85°C for JL-SONOS device channel ofVth1 19 cm −3 with high channel with doping (1 doping 1 × 10at . As obvious from the figure, memory the × 1019 cm−3doping ) exhibits less 17cell is −3 −3 four states degradation as compared to lightly doped[45]. JL-SONOS (1 × memory able to store 2×bits10 per19cell using × 10 cm .and 1 cm . (Reprinted with permission from [2011] 1017 cm−3 ), and its memory window can be well maintained “00”, “01”, “10”, and “11” with each state defined a different IEEE.). up to 105 sec. Under retention conditions, direct trap-toV th of >1 V.

The high temperature retention characteristic at 85◦ C for JL-SONOS is shown in Figure 16(a). The JL-SONOS

band (TB) tunneling from a nitride traps to the channel conduction band is the main discharge mechanism. With

A possible 3D memory cell circuit design based on vertical SiNW JL-SONOS is illustrated in Figure 17. Without using junction for both selection gate transistors and memory cell, the integration process would be Journal of Nanotechnology significantly simplified. BL

CG

LSG

USG

13

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USG SL CG

LSG

n+ p-Si substrate (a)

SL (b)

Figure 17: Schematic of 3D multilevel stacked NAND using JL-SONOS as building blocks.

Figure 17: Schematic of 3D multilevel stacked NAND using JL-SONOS as building blocks. increased channel doping, the energy states close to the channel conduction band are more likely to be occupied by electrons. This reduces the probability of further electron injection from the trap layer, and thus more reliable charge storage can be expected [47]. The endurance characteristic

incorporate optical properties of the device studied by using 3D Finite Element Method (FEM). The light is assumed to be incident normally to the SiNP array, under − → AM 1.5 G 100 mW cm−2 spectrum. The electric field ( E ) at each coordinate of the 3D simulation grid is calculated

Vertical Silicon Nanowire Platform for Low Power Electronics and ....

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CLEAN ENERGY Vertical Nanowire-Based Solar Cell

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Si thin film solar cell is considered for the next generation of solar cell as it provides a viable pathway towards low material and production cost [48]. Nonetheless, the thickness of Si thin film is much lower than the optical thickness to absorb 90% or more of the above-band-gap-photons [49], limiting the total power conversion efficiency (PCE). One of the possible approaches to enhance the light absorption is the integration of Si nanostructure on thin film. In addition to many other optical phenomenons, diffraction of light plays a key role with nanostructured surface making poorly absorbed red light to enter at higher angle into the film, thus improving the chances of absorption. Although, the exploitation of Si nanowire or nanopillar (SiNP) in solar cell application [49–53] has been widely studied over the past decade due to its excellent optical [53–56] and electrical properties [49, 52], there was not much systematic analysis that could guide design of high efficiency solar cells. Our group did a very through simulation-based study [7] and followed that by experimental verification [8]. We found the optimized pillar diameter (𝐷) is 0.20 μm, at diameter/periodicity (𝐷 / 𝑃) ratio of 0.5 (i.e., periodicity 0.4 μm) and height (𝐻) 1 μm [7, 56], the SEM image of Journal of Nanotechnology which is shown in Figure 18(a). Metal top contact

Diameter

d μm

n-type emitter Wn μm W p μm

p-type base NA = 1016 cm−3

Periodicity

p + back surface field NA = 1020 cm−3 (a)

Metal back contact

(b)

Figure 18: (a) SEM image of a Si nanopillar pattern used for simulating PCE analysis. Pillar parameters are diameter = 200 nm, pitch = 400 nm, and height = 1000 nm; (b) crossectional schematic of axial junction. (Reprinted with permission from [8]. [2010] IEEE.)

Figure 18: (a) SEM image of a Si nanopillar pattern used for simulating PCE analysis. Pillar parameters are diameter = 2000.7nm, pitch = 400 nm, and height = Photogenerated carrier profile ( cm− 3 s− 1 ) 1.41e + 023

28 16

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on )

rrent Jsc (mA cm−2)

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Green Nanotechnology

1000 nm; (b) crossectional schematic of axial junction. (Reprinted with permission from [8]. [2010] IEEE.).

We comprehensively study the electrical characteristics of the optically optimized structure for both the axial and radial 𝑝 - 𝑛 junctions using simulations. Our simulations incorporate optical properties of the device studied by using 3D Finite Element Method (FEM). The light is assumed to be incident normally to the SiNP array, under AM 1.5 G 100 mW cm−2 spectrum. The electric field ( ⃗ 𝐸 ) at each coordinate of the 3D simulation grid is calculated and exported to the Cogenda Genius Simulation Manager [57] for electrical solving the current continuity equation and Poisson’s equation self-consistently. The calculations of the current-voltage (𝐽 - 𝑉) characteristic of the SiNP solar cell follow the description in [58]. Driftdiffusion model is implemented for carrier transport within the device. Shockly-Reed-Hall (SRH) and Auger recombination are also taken into consideration. We discuss only axial junction (device in Figure 18(b)) here. Shown in Figure 19(a) is the effect of minority carrier diffusion length on short circuit current 𝐼sc and open circuit voltage 𝑉oc. Inset shows the PCE comparison with planar reference device. It can be observed that a diffusion length as poor as 0.6 μm is tolerable with our design, showing the possibility of exploitation of low-grade Si in photovoltaic application to lower the production cost [59]. Indeed a PCE of 17.4%, assuming surface recombination velocity “𝑆” = 0 cm-s−1, is predicted with small minority carrier diffusion length for electron (𝐿𝑛≥ 0 . 6 μm). Figure 19(b) shows the photo-generated carrier concentration with a clear concentration effect inside the wire. Designing the junction location inside this highly concentrated area is the key of getting high performance. Further, it is worth mentioning that though bulk recombination is lowered in thin film solar cell, and the Auger and surface recombination may increase due to higher carrier densities near the surface. It would have a negative impact on the short circuit current density (𝐽sc) and open circuit voltage (𝑉oc) [60], especially for nanopillar solar cell due to the increased surface area and absorption near the surface. We found a decrease in PCE from 17.4% to 15.5% with 𝑆 increased from 0 cm-s−1 to 1000 cm-s−1, indicating its detrimental impact [7].

p + back surface field NA = 1020 cm−3 (a)

Metal back contact

(b)

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Figure 18: (a) SEM image of a Si nanopillar pattern used for simulating PCE analysis. Pillar parameters are diameter = 200 nm, pitch = 400 nm, and height = 1000 nm; (b) crossectional schematic of axial junction. (Reprinted with permission from [8]. [2010] IEEE.)

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SiNP textured solar cell Un-textured solar cell (a)

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Figure 19: (a) Short circuit current and open circuit voltage of the SiNP textured solar cell at various Ln . Inset is the efficiency of the SiNP textured and untextured solar cell; (b) photo-generated carrier profile G in a Si nanopillar textured thin film solar cell at Ln = 0.6 μm. (Reprinted with permission from [59]. [2010] IEEE.)

Figure 19: (a) Short circuit current and open circuit voltage of the SiNP textured solar cell at various 𝐿𝑛. Inset is the efficiency of the SiNP textured and untextured solar cell; photo-generated carrierto Jprofile 𝐺 in2 ademonstrated Si nanopillar a short circuit current density (Jsc )(b) of 34.3 mA/cm2 is comparison on the solar sc of 18.1 mA/cm cell without SiNP. realized on axial p-n junction inside SiNP surface textured textured thin film solar cell at 𝐿𝑛= 0 . 6 μm. (Reprinted with permission from solar cell, which is the highest to date among reported Si Shown in Figures 20(a) and 20(b) are the micro[59]. [2010] IEEE.). nanowire (SiNW)/SiNP-based solar cells. This is in distinct scope images of the nanopillar-based and planar solar cells,

Next we present our experimental results of axial junction nanopillar solar cells, the fabrication details of which are available in [8]. Owing to the significantly enhanced light absorption of the optimized SiNP array texturing, a short circuit current density (𝐽sc) of 34.3 mA/cm2 is realized on axial p-n junction inside SiNP surface textured solar cell, which is the highest to date among reported Si nanowire (SiNW)/SiNP-based solar cells. This is in distinct comparison to 𝐽sc of 18.1 mA/cm2 demonstrated on the solar cell without SiNP. Shown in Figures 20(a) and 20(b) are the microscope images of the nanopillar-based and planar solar cells, respectively. It is clearly observed that the textured solar cell appears darker than the untextured one due to its superb antireflection properties. In align with our previous theoretical prediction, the lowest reflection is achieved when the SiNP diameter is 200 nm as shown in Figure 20(c) (e.g., 𝐷 / 𝑃 is 0.5) [7, 56].

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(a)

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Figure 20: Photographs of (a) SiNP textured and (b) untextured solar cell (without top TCO layer). (c) Reflectance spectra with varying parameters. (Reprinted with permission from [8]. [2010] IEEE.)

Figure 20: Photographs of (a) SiNP textured and (b) untextured solar cell (without top TCO layer). (c) Reflectance spectra with varying parameters. (Reprinted with Itpermission fromthat[8]. respectively. is clearly observed the[2010] textured IEEE.). solar photons are more efficiently absorbed. The device textured cell appears darker than the untextured one due to its by the SiNP array with D of 200 nm (or D/P of 0.5) and H of superb antireflection properties. In align with our previous 1000 nm haswas the best EQE (>200%to of the untextured one), The external quantum efficiency (EQE) measured investigate theoretical prediction, the lowest reflection is achieved when implying the excellent light trapping and carrier extraction efficiency ofnmthe lightin absorption carrierforseparation/carrier the SiNP diameter is 200 as shown Figure 20(c) (e.g.,andcapability the sample with optimizedcollection surface texturing. D/P is for 0.5) [7, 56]. The results are also well matched with the aforementioned the device (Figure 21). The doping concentration of the emitter (with The external quantum efficiency (EQE) was measured reflection measurement and simulation result [7]. 20 −3 junction depth oflight 250absorption nm) and 10circuit cmcurrent , and doping level ” measured under AM 1.5 G to investigate efficiency of the andback carriersurface Theis short “Jscthe 100 mW cm−2 illumination for nanopillar devices with variseparation/carrier collection 16 for the −3 device (Figure 21). The of base is 10 cm in the devices. The illuminated condition is AM 1.5G, ous diameter is shown in Figure 22(a) along with simulated doping concentration of the emitter (with junction depth of −3 cm−2 , and the doping level current-voltage in main Figure 22(b). The measured 250 nm) and is, back100 surface is 1020 that mW cm . Figure 21 depicts the EQEgraphs in the energy range Jsc increases with increasing D/P ratio, and the trend is in good of base is 1016 cm−3 in the devices. The illuminated condition −2 as a function of SiNP diameter. The EQE of SiNP array of solar spectrum is AM 1.5G, that is, 100 mW cm . Figure 21 depicts the EQE agreement with the simulation results and EQE data. of SiNP surface textured device is boosted in the main energy range of solar spectrum ashigher a function of thatThe textured devices is much than ofJscuntextured one, indicating that to a maximum of ∼31.4 mA/cm2 with pillar D of 200 nm, SiNP diameter. The EQE of SiNP array textured devices is the photons moreone,efficiently The textured the SiNP ∼1.7 device times larger than that ofby the untextured device which is much higher than that of are untextured indicating thatabsorbed. the

array with 𝐷 of 200 nm (or 𝐷 / 𝑃 of 0.5) and 𝐻 of 1000 nm has the best EQE (>200% of the untextured one), implying the excellent light trapping and

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carrier extraction capability for the sample with optimized surface texturing. The results are also well matched with the aforementioned reflection 16 measurement and simulation result [7].

Jou

temperature, respectively. Commerc electric materials-alloys of Bi, Te, 1 at room temperature [62]. Howe 80 difficult to handle and process like s 70 is widely used in the semiconduc 60 thermoelectric materials have their their bulk form, their low-dimension 50 to outperform expectations [63]. S 40 considered for thermoelectric applic 30 has become a potential contender a 20 show that the thermal conductivity is reduced by 2 orders (to a k o 10 in an improvement in the ZT val 0 material of 0.01. The tremendous red 400 500 600 700 800 900 1000 1100 to the effect of phonon boundary Incident wavelength (nm) [64–69]. This significant discovery chip-level thermoelectric energy ha D = 200 nm D = 50 nm to be integrated into conventional e D = 100 nm No nanopillar Silicon as the TEG material, the use o can be avoided. Figure 21: External quantum efficiency for various pillar diameter Figure 21: External quantum efficiency for various pillar diameter showing best We recently reported a top-do showing best result for 200 nm pillar diameter under AM 1.5 G −2 result for 200 nm pillar illumination. −2 diameter under AM 1.5 G 100 mWcm integration technology for SiNW-ba 100 mWcm illumination. (Reprinted with permission from [8]. IEEE.) matic flow of which along with SE (Reprinted with[2010] permission from [8]. [2010] IEEE.). Figure 23. The P and N SiNW eleme The short circuit current “𝐽sc” measured under AM 1.5 G 100 cm−2 and at the bottom topmW by Aluminum formed by selective silicidation. Th illumination for nanopillar devices with various diameter is shown in Figure (18.1 mA/cm2 ). To the best of our knowledge, the device in highly scalable and appropriate for 22(a) along with simulated current-voltage graphs in Figure 22(b). The due to the ease o nanopillar p-n our work achieved the highest Jsc using the power generation junction. with increasing 𝐷 / 𝑃 ratio, and the trendCMOS measured 𝐽sc increases is inICs.The good microscope image o In brief, nanowiresresults are shown have high potential for is shown in Figure 24(a) with stack agreement the simulation andto EQE data. Journalwith of Nanotechnology 17 improving solar cell performance through improvement in ment in Figure 24(b). It had a total reflection /absorption behaviour. 0With proper design, poor 35 5 mm (60% filled with doped wire D = 200 nm = 1000 nm Height quality silicon is shown to be acceptable and does not deterithermocouples. Periodicity = 400 nm 30 D = 150 nm depthμm. = 250 nm orate performance till diffusion length is as lowJunction as 0.6 −5 The power generation of the dev 25 High short circuit current is demonstrated experimentally heating one side using a copper hea D = 100 nm 10 to planar cell. with an improvement ofNo 1.7× in −comparison 20 SiNP cated on separate wafer and attach The heater die also had temperatur 15 −15 Shown in Figure 25(a) is the open ci 3.2. Vertical Nanowire-Based Thermoelectric Cooling/TherD = 100 nm 10 the TEG with different temperatur moelectric Generation. With the−20 aggravation in the high D = 1bioanalytical 50 nm 5 device “dT”. As expected, an increase heat flux fields like 3D electronics, implantable = 200 nm an increase in dT. A Voc of 1.5 mV devices, and semiconductor lasers, the thermal Dmap of −25 0 0 0.1 0.2 0.3 0.4 0.5 0.6 of Si nanopillarhas become extremely overall applied dT of 70 K across generalDiameter electronics uneven and detVoltage (V) setup (0.12 K across the SiNW). A li rimental to(a)the devices’ performance [61]. Besides a growing (b) all data points is due to S = dV/dT need to cool down the local hot spots generated, there is an Figure 22: (a) Measured J as a function of Si nanopillar diameter under AM 1.5 G 100 mWcm illumination (b) Simulated J-V characteristic ofeven Si nanopillar thin attractive film solar cell (with underlying Si thin film ∼800 nm). (Reprinted with permission [2010] resistance values presented i more opportunity to ofharvest the surplus heat.from [8].thermal IEEE.) Figure 22: (a) However, Measured as harvesting a function nanopillar diameter AMon the largest Voc me dV/(NdT) S =under chip𝐽sclevel hasof notSibeen feasible due to = 70 K), the effective Seebeck coeffi the low thermoelectric conversion efficiency of current bulk be increased. In Figure 25(b), the generated voltage/power smoothing using H2 annealing [71] may help in reducing extracted to be 39 μV/K. The extrac and also duedTtoof a70lack of proper CMOS compatible is plotted as materials a function of current at a total K this variation. Indeed, being controlled from all sides the across the experimental setup. A maximum power output of sensitivity of device parameters to nanowire diameter,reported which SiNW value at comparable material. 1.5 nW is realized under a voltage and current of 0.75 mV and is defined by lithography and generally has ±5% variation, ever, it can be pointed out that each l basicif we principles of dT thermoelectric cooling/thermoeis large. Poor lithographic process window for pillar pattern 2 μA, respectively. InThe our device, could extend the 2 is one the main of critical dimension variation across the wirelectric to 1 K, a power density of 1.2 μW/cm can be are setup has its own interfacial therma generation (TEC/TEG) based oncontribution Peltier or Seebeck harvested. However, the ability to maintain a large dT across across the wafer. However, one of the solutions for this effectsa larger where electric current is isaccompanied heat the SiNW to generate powerall is another important problem the change of patternby polarity using hardlower mask significantly the actual dT ac aspect that needs to be considered and optimized. scheme. Use of variability-specific designs, such as eight tranfirst demonstration, there is a room current and vice versa. A thermoelectric device can alternate 100

Height = 1000 nm Periodicity = 400 nm Junction depth = 250 nm

Current density (mA/cm2 )

Short circuit current density (mA/cm2 )

External quantum efficiency (%)

90

sc

−2

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1.5 G 100 mWcm−2 illumination (b) Simulated J-V characteristic of Si nanopillar thin film solar cell (with underlying Si thin film of ~800 nm). (Reprinted with permission from [8]. [2010] IEEE.).

The 𝐽sc of SiNP surface textured device is boosted to a maximum of ~31.4 mA/cm2 with pillar 𝐷 of 200 nm, which is ~1.7 times larger than that of the untextured device (18.1 mA/cm2). To the best of our knowledge, the device in our work achieved the highest 𝐽sc using the nanopillar p-n junction.

In brief, nanowires are shown to have high potential for improving solar cell performance through improvement in reflection /absorption behaviour. With proper design, poor quality silicon is shown to be acceptable and does not deteriorate performance till diffusion length is as low as 0.6 μm. High short circuit current is demonstrated experimentally with an improvement of 1.7× in comparison to planar cell.

Vertical Nanowire-Based Thermoelectric Cooling/Thermoelectric Generation With the aggravation in the high heat flux fields like 3D electronics, implantable bioanalytical devices, and semiconductor lasers, the thermal map of general electronics has become extremely uneven and detrimental to the devices’ performance [61]. Besides a growing need to cool down the local hot spots generated, there is an even more attractive opportunity to harvest the surplus heat. However, chip level harvesting has not been feasible due to the low thermoelectric conversion efficiency of current bulk materials and also due to a lack of proper CMOS compatible material. The basic principles of thermoelectric cooling/thermoelectric generation (TEC/TEG) are based on Peltier or Seebeck effects where all electric current is accompanied by heat current and vice versa. A thermoelectric device can alternate between being a power generator via heat to electrical current conversion or a cooler via electrical current carrying away the heat [62]. The efficiency of the thermoelectric modules is dictated by the dimensionless figure-of-merit ZT, that is, 𝑆2𝜎 𝑇 / 𝜅, where 𝑆, 𝜎, 𝑘, 𝑇, are Seebeck coefficient, electrical conductivity, thermal conductivity, and absolute temperature, respectively. Commercial state-of-art thermoelectric materials-alloys of Bi, Te, Sb, and Se have ZT ≥ 1 at room temperature [62]. However, these materials are difficult to handle and process like silicon technology, which is widely used in the semiconductor industry. Although thermoelectric materials have their performance limited in their bulk form, their lowdimensional nanostructures seem to outperform expectations [63]. Silicon,

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which was never considered for thermoelectric applications in its bulk form, has become a potential contender at the nanoscale. Studies show that the thermal conductivity of a 50 nm wide SiNW is reduced by 2 orders (to a 𝑘 of 1.6 W/mK) resulting in an improvement in the ZT value to 1 from the bulk material of 0.01. The tremendous reduction of 𝜅 is attributed to the effect of phonon boundary scattering at nanoscale [64–69]. This significant discovery opens up a window for chip-level thermoelectric energy harvesting with potential to be integrated into conventional electronic circuitry. With Silicon as the TEG material, the use of Bi2Te3-based materials can be avoided.

We recently reported a top-down CMOS compatible integration technology for SiNW-based TEG [70], the schematic flow of which along with SEM images is shown in Figure 23. The P and N SiNW elements are connected at the top by Aluminum and at the bottom through metal-silicide formed by selective silicidation. This SiNW-based TEG is highly scalable and appropriate for chip level cooling and power generation due to the ease of integration with other CMOS ICs.The microscope image of the completed device is shown in Figure 24(a) with stack details during measurement in Figure 24(b). It had a total surface area of 5 mm × 5 mm (60% filled with doped wires) and consisted of 162 thermocouples.

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Figure 23: Schematic of fabrication (a) SiNW formation by dry etch, (b) Ion implantation, P/N elements definition, each element consists of hundreds of SiNW, (c) P/N couples formed by dry etch, (d) SiNW top and bottom silicidation while protecting the sidewall, (e) dielectric deposition and etch back to expose only the tip of the SiNW, and Top metallization. (f) SEM images of pillar formation, (g) N & P implants can be seen clearly under microscope with a different shade, (h) SEM image of SiNW after N/P implant, and (i) metallization etch showing individual N/P couples. Inset shows the tips of the SiNW exposing after oxide etch which confirms structure of the TEG. (h) and (i) are images of test structures, the actual design is too large to be shown in SEM image. (Reprinted with permission from [70]. [2011] IEEE.). Journal of Nanotechnology

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T1 Heat sink, 0.0085 K/W 5

6

Silicon substrate, 0.023 K/W (200 μm, (7.6 mm)2 ) Bottom oxide, 0.012 K/W (1 μm, (7.6 mm)2 )

3

SiNW island, 9.2 × 10−5 K/W(0.8 μm, (7.6 mm)2 )

4

Device (effective), 0.01 K/W (1 μm, (7.6 mm)2 ) Top metal (Al), 0.00017 K/W (1 μm, (5 mm)2 ) TIM, 5.72 K/W (100 μm, (5 mm)2 ) 1

2

Silicon test chip, 0.047 K/W (725 μm, (1 cm)2 ) T2 (b)

(a)

Figure 24: (a) Snapshot of the completed TEG (6 pads at the sides of the TEG to allow connections of different areas). Connecting the terminals 1 and 5 establishes an ohmic path between several serpentine P- and N-elements in a 5 mm × 5 mm area. (b) Different layers used 24: (a) Snapshot of the TEG used (6 pads at the sides TEG in theFigure experimental setup. Indicated in the different layerscompleted is the thermal resistance in the calculations. The heatof sinkthe thermal resistance calculation is based on Al with a dimension of 5 cm × 5 cm × 5 mm. (Reprinted with permission from [70]. [2011] IEEE.)

1.4

1.4

1.2

1.2

1.2

1 0.8 0.6 0.4 0.2

1

1

0.8

0.8

0.6

0.6

0.4

0.4

Power (nW)

1.4

Voltage (mV)

Open circuit voltage (mV)

to allow connections of different areas). Connecting the terminals 1 and 5 establishes anTemperature ohmicacross path between several serpentine P- and N-elements in a setup (K) 0 23 area. 35 (b) 46 Different 58 70 layers 81 5 mm ×115 mm used in the experimental setup. Indi1.6 1.6 cated in the different layers is the thermal1.6resistance used in the calculations.

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The heat sink thermal resistance calculation is based on Al with a dimension of 5 cm × 5 cm × 5 mm. (Reprinted with permission from [70]. [2011] IEEE.).

The power generation of the device was characterized by heating one side using a copper heater designed and fabricated on separate wafer and attached to device under test. The heater die also had temperature measurement devices. Shown in Figure 25(a) is the open circuit voltage, 𝑉oc across the TEG with different temperatures generated across the device “dT”. As expected, an increase in 𝑉oc is observed with an increase in dT. A 𝑉oc of 1.5 mV was measured under an overall applied dT of 70 K across the whole experimental setup (0.12 K across the SiNW). A linear relationship across all data points is due to S = dV/dT relationship. With the thermal resistance values presented in Figure 24(b) and using S = dV/(NdT) on the largest 𝑉oc measured across setup (dT = 70 K), the effective Seebeck coefficient of the TEG was extracted to be 39 μV/K. The extracted value is lower than reported SiNW value at comparable doping level [64]. However, it can be pointed out that each layer in the experimental setup has its own interfacial thermal resistances which will lower significantly the actual dT across the TEG. As it is a first demonstration, there is a room to improve interfacial thermal resistances and thus improve the dT across the nanowire. Indeed, the idea of an ultrathin thermoelectric device is envisioned to be directly integrated onto chips for direct energy harvesting. In this way, the interfacial thermal resistance associated with the experimental setup can be eliminated. Hence, the effective dT across the SiNW can be increased. In Figure 25(b), the generated voltage/power is plotted as a function of current at a total dT of 70 K across the experimental setup. A maximum power output of 1.5 nW is realized under a voltage and current of 0.75 mV and 2 μA, respectively. In our device, if we could extend the dT across the wire to 1 K, a power density of 1.2 μW/cm2 can be harvested. However, the ability to maintain a large dT across the SiNW to generate a larger power is another important aspect that needs to be considered and optimized.

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Figure 25: (a) Plot of the TEG’s 𝑉oc versus the different dT (actual/estimated) applied across it. A best fit line is drawn through all the data points. (b) Voltage/ Power versus Current curve when dT (estimated) is 0.12 K with 𝑉oc and 𝐼sc of 1.5 mV and 3.79 μA, respectively. The black line is a linear fit and the red line a polynomial fit of the data points. (Reprinted with permission from [70]. [2011] IEEE.).

In brief, SiNW TEG was fabricated using CMOS compatible topdown processes. Seebeck effect was demonstrated and power generation was measured. With further improvements in top metallization and low thermal conductivity material filling between nanowires, such as polyimide, excellent nanoscale thermoelectric energy harvesters can be realized. Such SiNW TEG can be cost-effective, scalable and possibly easier to be integrated. By potential integration of these TEG beneath (wafer backside) traditional high heat flux circuitry, these nanoscaled generators can provide location specific thermal harvesting and pave way to ultra low powered IC’s and self-powered circuits.

CHALLENGES AND OPPORTUNITIES There has been significant progress in fabrication technology and in understanding of the electrostatics and transport in the GAA nanowire devices; huge challenges remain to be met before this new device architecture reaches the level of manufacturing. The first challenge is large device parameter variability in the threshold voltage and 𝐼on as reported in [10]. This variability is mainly attributed to possible variation of nanowire shape, size/ diameter, roughness and variation in interface quality. Tight control of the starting pillar dimensions with advanced lithography and surface smoothing

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using H2 annealing [71] may help in reducing this variation. Indeed, being controlled from all sides the sensitivity of device parameters to nanowire diameter, which is defined by lithography and generally has ±5% variation, is large. Poor lithographic process window for pillar pattern is one the main contribution of critical dimension variation across the wafer. However, one of the solutions for this problem is the change of pattern polarity using hard mask scheme. Use of variability-specific designs, such as eight transistor SRAM [72] or probabilistic circuit design techniques, such as neuromorphic designs [73], could form part of the solution for successful implementation of GAA nanowire devices into manufacturable circuits. The second challenge pertains to the tuning of the threshold voltage. Due to very limited volume of channel body, the doping of the channel for 𝑉th adjustment is not feasible. Due to cylindrical architecture, the impact of gate oxide thickness on 𝑉th is also expected to be significantly diminished. The feasible solutions lie only with the tuning of the gate electrode work function and the wire diameters. The third challenge, specific to vertical nanowire devices, is inherent asymmetry between source and drain resistance, and also in channel diameter if profile is not controlled well. These asymmetries have to be taken care of in circuit designs and therefore provide an opportunity to designers to come up with novel design solutions. Further, the vertical wire is shown as natural platform for TFET; the challenge with circuit design which could be huge as TFET will not work as pass transistor in both directions. Designing hybrid circuits with MOSFETS and TFETS could be one of the solutions to resolve this issue. The issues which are a challenge in electronics domain have either little or no impact on energy harvesting or could even be favorable. For example, critical dimension variation should not impact on solar efficiency, and thermoelectric power generation is expected to improve with surface roughness as a result of decreased thermal conductivity [64, 65]. Though not reviewed in this paper, the use of nanowires in Li ion batteries as anode is another high potential application where none of the issues described above will have any impact [9]. Nanowires also provide opportunity of cointegrating various types of devices either from functionality or performance perspective or for the both on silicon platform. For example, Si/III-V and Ge wires cointegration can provide high performance electronics with NMOS on Si/III-V and PMOS on Ge wire. Worth mentioning here that such hetero-integration may be limited to bottom up technologies as top down would require wafer

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level selective epitaxial deposition of these materials on silicon which has been a challenge for long due to lattice missmatch.

SUMMARY The status of vertical GAA nanowire technology platform developed using top-down approach has been reviewed. Area, speed, and power advantages of vertical platform for green CMOS based electronics are discussed. In addition to excellent MOSFET scaling potential, the vertical wire is projected as a natural platform for TFET devices demonstrating record low subthreshold slope. Progress on nonvolatile memory cells is reviewed and junction-less wire memory is projected as an excellent platform for 3D stacking. Nanowires seem to have possible novel solutions in low cost solar and thermal energy harvesting. The presented top-down techniques can potentially address the needs of “end-of-the-Silicon technology-roadmap” and beyond CMOS era, possibly can lead to an all nanowire autonomous system where data computation, data storage, energy harvesting, and energy storage could all be possible by using nanowire devices, all integrated on chip either at same level or different, using TSV if not direct. Thus, nanowire technology indicates feasibility of opening up newer application opportunities for Si technology.

ACKNOWLEDGMENT The authors acknowledge the support from Semiconductor Process Technologies Lab of the Institute of Microelectronics/A*STAR, Singapore in samples preparation and analysis.

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