Vertical GaN and SiC Power Devices [1 ed.] 9781630814298, 9781630814274

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Microwave

Details about the effects of photon recycling are explained, presenting readers with a greater understanding of state-of-the-art GaN bipolar devices. This book offers in-depth coverage of bulk crystal growth of GaN, including hydride vapor-phase epitaxial (HVPE) growth, high-pressure nitrogen solution growth, sodium-flux growth, ammonothermal growth, and sublimation growth of SiC. The fabrication process, including epitaxial growth, ion implantation, diffusion, oxidation, metallization, and passivation, is explained. The book provides details about metal-semiconductor contacts, unipolar power diodes, and metal-insulator-semiconductor (MIS) power switching devices. Bipolar power diodes, power switching devices, and edge terminations are also covered in this resource.

Include bar code ISBN 13: 978-1-63081-427-4 ISBN: 1-63081-427-X

Vertical GaN and SiC Power Devices Kazuhiro Mochizuki

Mochizuki

Kazuhiro Mochizuki is affiliated with the National Institute of Advanced Industrial Science and Technology, Japan. Previously he was involved in the research of GaN and SiC power devices at the Central Research Laboratory, Hitachi Ltd., Tokyo, Japan. He is a senior member of the IEEE and a member of the Japan Society of Applied Physics. He is also a lecturer at the University of Electro-Communications, Tokyo, Japan, and Hosei University, Tokyo, Japan. He received his B.S., M.S., and Ph.D. in electronic engineering from the University of Tokyo, Japan.

Vertical GaN and SiC Power Devices

This unique resource provides a thorough introduction to vertical gallium nitride (GaN) and silicon carbide (SiC) power devices using real device data and physical models. Comparing and contrasting these technologies, the book uses clear examples from recent years and presents the design features of various GaN and SiC power devices. Vertical versus lateral power semiconductor devices are also explored based on real commercial device data. The abstract concepts of solid-state physics as they relate to solid-state devices are explained with particular emphasis on power solid-state devices.

ARTECH HOUSE BOSTON I LONDON

www.artechhouse.com

PMS 2965

PMS PROCESS BLUE

Vertical GaN and SiC Power Devices

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For a complete listing of titles in the Artech House Microwave Series turn to the back of this book.

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Vertical GaN and SiC Power Devices Kazuhiro Mochizuki

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Library of Congress Cataloging-in-Publication Data A catalog record for this book is available from the U.S. Library of Congress. British Library Cataloguing in Publication Data A catalogue record for this book is available from the British Library. Cover design by John Gomes ISBN 13: 978-1-63081-427-4 © 2018 ARTECH HOUSE 685 Canton Street Norwood, MA 02062

All rights reserved. Printed and bound in the United States of America. No part of this book may be reproduced or utilized in any form or by any means, electronic or mechanical, including photocopying, recording, or by any information storage and retrieval system, without permission in writing from the publisher. All terms mentioned in this book that are known to be trademarks or service marks have been appropriately capitalized. Artech House cannot attest to the accuracy of this information. Use of a term in this book should not be regarded as affecting the validity of any trademark or service mark. 10 9 8 7 6 5 4 3 2 1

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Contents Preface References

1

2

xi xii

Vertical Versus Lateral Power Semiconductor Devices 1 1.1 1.2 1.3

Introduction Typical Power Device Characteristics Vertical versus Lateral Unipolar Power Devices 1.3.1 Vertical versus Lateral Unipolar Power-Switching Devices 1.3.2 Vertical versus Lateral Unipolar Power Diodes 1.4 Summary References

1 2 4 5 8 10 12

Physical Properties of GaN and SiC

15

2.1 2.2

15 16 17 20 21 24 27 28 29 30 32 33 35 36

2.3 2.4

2.5 2.6 2.7 2.8

Introduction Crystal Structures 2.2.1 Crystal Structures of AlN and GaN 2.2.2 Crystal Structures of SiC 2.2.3 Crystal Defects Energy Bands Impurity Doping 2.4.1 n-Type Doping 2.4.2 p-Type Doping Carrier Mobility Impact Ionization Figure of Merit Summary References

v

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vi

Vertical GaN and SiC Power Devices

3

p-n Junctions

41

3.1 3.2 3.3 3.4

41 42 43 44 44 46 47 48

3.5 3.6

3.7

3.8 3.9

4

5

50 52 52 55 55 57 57 59 61 63 63

Effects of Photon Recycling

65

4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8

65 67 68 71 72 74 78 80 80

Introduction Family Tree of Photon-Recycling Phenomena Intrinsic Photon Recycling Influence of IPR on Forward-Biased GaN p-n Diodes Influence of Self-Heating on Forward-Biased GaN p-n Diodes Influence of EPR on Forward-Biased GaN p-n Diodes Possible Models for EPR Summary References

Bulk Crystal Growth

83

5.1 5.2

83 84 85 86 86 87 87 88 89 89

5.3 5.4 5.5 5.6

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Introduction Diffusion Continuity Equations Carrier Recombination Lifetime 3.4.1 Band-to-Band Recombination Lifetime 3.4.2 SRH Recombination Lifetime 3.4.3 Auger Recombination Lifetime 3.4.4 Overall Expression for Carrier Recombination Lifetime Depletion-Region Width of One-Dimensional p+n Abrupt Junction One-Dimensional Forward-Current/Voltage Characteristics 3.6.1 Low-Level Injection Condition 3.6.2 High-Level Injection Condition 3.6.3 An Example of Measured Current/Voltage Characteristics Multidimensional Forward-Current/Voltage Characteristics 3.7.1 Influence of Surface Recombination on Peripheral Current of p+n Diodes 3.7.2 Influence of Electric-Field Concentration on Non-Self-Aligned Mea-type p+n Diodes Junction Breakdown Summary References

Introduction HVPE Growth of GaN 5.2.1 Mechanism of HVPE Growth of GaN 5.2.2 Doping During HVPE Growth of GaN 5.2.3 Epitaxial Lateral Overgrowth of GaN High-Pressure Nitrogen Solution Growth of GaN Sodium-Flux Growth of GaN Ammonothermal Growth of GaN Sublimation Growth of SiC 5.6.1 Mechanism of Sublimation Growth of SiC

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Contents

5.7 5.8 5.9

6

Introduction MOCVD of GaN Two-Dimensional Nucleation Theory BCF theory CVD of 4H-SiC CVD Trench Filling of 4H-SiC Summary References

Fabrication Processes 7.1 7.2

7.3

7.4

7.5

7.6

7.7 7.8

8

5.6.2 Doping During Sublimation Growth of SiC High-Temperature Chemical Vapor Deposition of SiC Solution Growth of SiC Summary References

Epitaxial Growth 6.1 6.2 6.3 6.4 6.5 6.6 6.7

7

vii

Introduction Etching 7.2.1 ICP Etching 7.2.2 Wet Chemical Etching Ion Implantation 7.3.1 Ion Implantation into GaN 7.3.2 Aluminum-Ion Implantation into 4H-SiC 7.3.3 Nitrogen-Ion and Phosphorus-Ion Implantations into 4H-SiC Diffusion 7.4.1 Historic Background of Boron Diffusion in SiC 7.4.2 Dual-Sublattice Diffusion Modeling 7.4.3 Semi-Atomistic Simulation Oxidation 7.5.1 Thermal Oxidation of GaN 7.5.2 Thermal Oxidation of 4H-SiC Metallization 7.6.1 Ohmic Contacts to GaN 7.6.2 Ohmic Contacts to 4H-SiC Passivation Summary References

97 97 97 100 101 103 109 111 112

117 117 117 118 119 120 121 121 125 125 125 127 129 132 132 132 133 133 133 134 134 134

Metal-Semiconductor Contacts and Unipolar Power Diodes 143 8.1 Introduction 8.2 Schottky-Barrier Lowering 8.3 Forward-Biased Schottky Junction 8.4 Forward-Current/Voltage Characteristics Based on Diffusion Theory

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90 90 90 91 92

143 145 146 149

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viii

Vertical GaN and SiC Power Devices

8.5 8.6 8.7

8.8 8.9 8.10

8.11

9

Forward-Current/Voltage Characteristics Based on TED Theory Reverse-Current/Voltage Characteristics Based on TFE Theory Pure SBDs 8.7.1 Pure GaN SBDs 8.7.2 Pure 4H-SiC SBDs Graded AlGaN SBDs 4H-SiC SBDs with a Thin p+-Type Layer Shielded Planar SBDs 8.10.1 GaN merged p-n Schottky Diodes 8.10.2 4H-SiC JBS Diodes Summary References

Metal-Insulator-Semiconductor Capacitors and Unipolar Power-Switching Devices 9.1 9.2

Introduction MIS Capacitors 9.2.1 Idealized MIS Capacitors 9.2.2 Influence of Insulator and Fixed Charges on MIS Capacitors 9.3 AlGaN/GaN Heterostructures 9.4 Band Lineup for GaN, AlN, 4H-SiC, and Representative Insulators 9.5 GaN HFETs 9.5.1 GaN MIS HFETs 9.5.2 GaN MESFETs 9.5.3 GaN p+-gate HFETs 9.6 4H-SiC JFETs 9.7 MISFETs 9.7.1 Planar MISFETs 9.7.2 Trench MISFETs 9.7.3 SJ MISFETs 9.8 Summary References

10

Bipolar Power Diodes and Power-Switching Devices 10.1 10.2 10.3 10.4

Introduction Optimum Design of a One-Dimensional p-n Diode GaN p-n Diodes with a Nonuniformly Doped Drift Layer 4H-SiC p-i-n Diodes 10.4.1 Reported Results Concerning 4H-SiC p-i-n Diodes 10.4.2 Stored Charge in Forward-Biased 4H-SiC p-i-n Diodes 10.4.3 Reverse Recovery of 4H-SiC p-i-n Diodes 10.5 n-p-n BJTs 10.5.1 Collector-Layer Design 10.5.2 Base-Layer Design 10.5.3 Critical Collector-Current Density for Second Breakdown

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150 151 153 153 155 157 157 159 161 161 163 163

169 169 170 170 173 174 175 176 176 181 181 183 185 187 191 194 196 196

203 203 206 209 211 211 212 213 215 215 216 218

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Contents

10.6

10.7 10.8 10.9

11

11.3 11.4 11.5 11.6

Introduction MFP for GaN Power Devices 11.2.1 MFP Without Guard Rings 11.2.2 Guard-Ring-Assisted MFP SM-JTE for 4H-SiC Power Devices CD-JTE for 4H-SiC Power Devices Hybrid-JTE for 4H-SiC Power Devices Summary References

218 218 219 219 219 220 220 223 224

229 229 232 232 234 234 234 235 237 237

Reliability of Vertical GaN and SiC Power Devices 241 12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8

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10.5.4 GaN BJTs 10.5.5 SiC BJTs Shockley Diodes 10.6.1 Reverse Blocking of Shockley Diodes 10.6.2 Forward Blocking of Shockley Diodes SiC Thyristors SiC IGBTs Summary References

Edge Terminations 11.1 11.2

12

ix

Introduction Tolerance to HTRB Stress Tolerance to HTGB Stress Tolerance to H3TRB Stress Tolerance to TC Stress Tolerance to HTO Stress Tolerance to Terrestrial Cosmic Radiation Summary References

241 241 244 244 245 245 246 247 248

About the Author

251

Index

253

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Preface Compared with silicon, both gallium nitride (GaN) and silicon carbide (SiC) have excellent physical properties; the electric field that results in breakdown is more than 10 times higher, and the thermal conductivity is 33%−330% higher. They are therefore expected to be the ultimate materials for power devices used in highly efficient power-electronics systems. In the case of GaN, recent progress concerning high-quality freestanding substrates has dramatically improved the performance of vertical power devices. However, in the latest book on GaN and SiC power devices, this improved performance is only mentioned briefly in a 10-page-long chapter [1]. In view of that situation, this book is intended to provide a comparative introduction to vertical GaN and SiC power devices for students, researchers, and engineers working in the field of crystal growth, processing, and design for power semiconductor devices. I started writing this book after receiving an offer from Artech House following a talk I was invited to give entitled “Vertical GaN Bipolar Devices: Gaining Competitive Advantage from Photon Recycling” at the International Symposium on Compound Semiconductors in 2016 [2]. The emphasis in this book is therefore partly on photon recycling (Chapter 4), which is important for increasing not only the effective minority-carrier lifetime but also the ionization ratio of deep acceptors. Photon recycling in GaN is attributable to very large peripheral current flowing through non-self-aligned mesa-type p-n junctions (Chapter 3). This phenomenon has not been described in any books, since forward current flowing through p-n junctions has been treated one-dimensionally only.

xi

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xii

Vertical GaN and SiC Power Devices

In addition, to the best of my knowledge, all the books on GaN and SiC power devices inadequately describe Schottky junctions; namely, they describe thermionic emission as a limiting process on current transport even though electron mobility becomes quite low under a high electric field. As described in Chapter 8, diffusion is more important, especially when electron mobility is reduced by ion-implantation-induced damage or phonon scattering at elevated temperatures. Among unipolar power-switching devices, SiC superjunction powerswitching devices are expected to have the lowest specific on-resistance around a breakdown voltage of 6.5 kV. Although trench-filling epitaxy is indispensable for fabricating Si and SiC superjunction devices, the trenchfilling mechanisms in the cases of silicon and SiC are completely different. Chapter 6 is thus dedicated to explaining such epitaxial growth mechanisms. Other topics that have not been covered in previous books on power semiconductor devices include the following: a comparison of vertical and lateral power-semiconductor devices based on reported results (Chapter 1), modeling of aluminum and boron profiles in SiC (Chapter 7), GaN bipolar junction transistors (Chapter 10), and a comparison of junction terminations and reliability of vertical GaN and SiC power devices (Chapters 11 and 12). I wrote this book with the help of valuable supporting discussions with professor Tomoyoshi Mishima of Hosei University on extrinsic photon recycling (Chapter 4); Professor Emeritus Tatau Nishinaga of the University of Tokyo on supersaturation of spiral growth and the Gibbs–Thomson effect (Chapter 6); professor Toshikazu Suzuki of the Japan Advanced Institute of Science and Technology on Schottky junctions (Chapter 8); and anonymous reviewers from Artech House on the whole manuscript. I also thank Dr. Yasuhiro Shimamoto, Dr. Akio Shima, and Dr. Yuki Mori of Hitachi for their support in improving the manuscript.

References [1]

Baliga, B. J., Gallium Nitride and Silicon Carbide Power Devices, Singapore: World Scientific, 2017, pp. 391–400.

[2]

Mochizuki, K., “Vertical GaN Bipolar Devices: Gaining Competitive Advantage from Photon Recycling,” International Symposium on Compound Semiconductors, Toyama, Japan, June 26–30, 2016, paper ThB2-1.

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CHAPTER

1 Contents 1.1 Introduction 1.2 Typical Power Device Characteristics 1.3 Vertical versus Lateral Unipolar Power Devices 1.4 Summary

Vertical versus Lateral Power Semiconductor Devices 1.1

Introduction

Success of silicon-based electron devices triggered rapid progress in microelectronics and nanoelectronics that deal with relatively low power (i.e., less than 10W) (Figure 1.1). Even in power electronics dealing with much higher power, silicon-based devices have played a dominant role in recent decades; however, they are reaching the limit of progress set by fundamental material properties. Wide-bandgap semiconductors have thus attracted great attention as materials for next-generation power devices since they have superior material properties compared to silicon (see Section 2.7). The most advanced wide-bandgap semiconductor is silicon carbide (SiC); note, for example, that its implementation into railcar-traction inverters significantly reduced power loss [1]. Another material for next-generation power

1

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2

Vertical GaN and SiC Power Devices

Max voltage (V)

10 4 10 3

Power electronics 10 2 10 1 Microand nano-

10

0 electronics

10−1

10 0

10 1

10 2

10 3

10 4

10 5

Max current (A)

Figure 1.1 Areas of microelectronics, nanoelectronics, and power electronics as a function of maximum voltage and current.

devices is gallium nitride (GaN). Lateral power-switching devices that use GaN layers on Si substrates have a great impact on the cost-effectiveness of switching-mode power supply as well as consumer electronics [2] (see Section 1.3.1.1). Moreover, vertical GaN power devices have also attracted significant attention for their large current-handling capability [3]. As shown by the upward arrows in Figure 1.2(a, b), both SiC and GaN are expected to increase current rating (by increasing current density in the chip) and operating frequency, as described in Section 2.7. This chapter compares vertical and lateral GaN and SiC power devices in Section 1. 3.

1.2 Typical Power Device Characteristics Power semiconductor devices are used as both switches and diodes [4] in power electronics, where electrical energy is converted from AC to DC (rectifier), DC to DC (DC-to-DC converter), and DC to AC (inverter). A diode is a two-terminal device that allows current to pass in one direction (from anode to cathode) while blocking current in the opposite direction (up to breakdown voltage [BV] shown in Figure 1.3). As shown in Figure 1.4, a typical three-phase voltage-source inverter, which outputs an AC voltage to a three-phase balanced load [5], uses six switches and six diodes. When the loads are inductive (e.g., in the case of motors), the diodes are used as reverse conducting devices (because most semiconductor switches conduct current in a single direction only). While the forward-current and voltage characteristics of a power-semiconductor diode show an offset voltage (Figure 1.3), a power-semiconductor switching device has either zero-offset-voltage characteristics (Figure 1.5[a]) or offset-voltage characteristics (Figure 1.5[b]); in both cases, it exhibits forward voltage drop VF when it carries forward current IF.

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1.2 Typical Power Device Characteristics

3

10 5

Current rating (A)

10 4

10 3

High-voltage DC transmission Application of wide-bandgap power-semicounductor devices

Electric trains

Automobiles

10 2

10 1

10 0

10 −1 10 1

Switching-mode power supply

10 2

10 3

10 4

10 5

Voltage rating (V)

(a) 10 7 Application of wide-bandgap power-semicounductor devices

Operating frequency (Hz)

10 6 Switching-mode power supply 10 5 Automobiles

10 4

Electric trains 10 3

10 2 High-voltage DC transmission 10 1

10 2

10 3

10 4

10 5

Voltage rating (V)

(b) Figure 1.2 Applications of power-semiconductor devices from the viewpoints of (a) current rating and (b) operating frequency.

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Vertical GaN and SiC Power Devices

Current

4

IF

BV Voltage

VF Offset

Figure 1.3 Schematic illustration of current/voltage characteristics of power-semiconductor diodes (IF: forward current; VF: forward-voltage drop; BV: breakdown voltage).

Current direction E 2

Switch

Diode U V

N

W Inductive load E 2

Figure 1.4

Circuit configuring a three-phase voltage-source inverter.

1.3 Vertical versus Lateral Unipolar Power Devices In a semiconductor, current is carried by two types of carriers, namely, negatively charged electrons and positively charged holes. Power-semiconductor devices can thus be classified as unipolar and bipolar devices. In the case of unipolar devices, current is carried via electrons or holes; in bipolar devices, on the other hand, current is carried by both electrons and holes. As classified in Figure 1.6, lateral unipolar power-switching devices and lateral unipolar power diodes with structures comprising GaN layers on Si substrates, GaN layers on SiC substrates, GaN layers on sapphire substrates,

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1.3 Vertical versus Lateral Unipolar Power Devices

On

Current

Current

On

IF

5

IF

Off VF

Voltage (a)

Off BV

VF Offset

Voltage (b)

BV

Figure 1.5 Schematic illustration of (a) zero-offset-voltage and (b) offset-voltage characteristics of power-semiconductor switching devices (IF: forward current; VF: forwardvoltage drop; BV: breakdown voltage).

Lateral power-switching device

Unipolar device

Bipolar device

Lateral power diode

• GaN on Si substrate • GaN on SiC substrate • GaN on GaN substrate • GaN on sapphire substrate • SiC on SiC substrate Not widely used

Not widely used

Figure 1.6 Classification of lateral power-switching devices and diodes as unipolar and bipolar devices.

GaN layers on GaN substrates, or SiC layers on SiC substrates have been reported; however, lateral bipolar power-switching devices and lateral bipolar power diodes have not been widely used. Therefore, this section compares vertical and lateral devices with respect to unipolar power-switching devices and unipolar power diodes. 1.3.1 Vertical versus Lateral Unipolar Power-Switching Devices Figure 1.7 shows lateral and vertical unipolar power-switching devices with an area A of 1 cm2. Unipolar power-switching devices show zero-offsetvoltage characteristics, shown in Figure 1.5(a), where specific on-resistance RonA is defined as VFA/IF. Lateral unipolar power-switching devices gain an advantage over vertical ones in that RonA does not include specific substrate resistance RsubA (Figure 1.7[a]).

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6

Vertical GaN and SiC Power Devices

A = 1 cm2

A = 1 cm2 R on A R on A

Substrate

(a)

R sub A

(b)

Figure 1.7 Schematic illustration of (a) lateral and (b) vertical unipolar power-switching devices with an area A of 1 cm2, where RonA and RsubA, respectively, denote specific onresistance and specific substrate resistance.

1.3.1.1 Vertical versus Lateral GaN Unipolar Power-Switching Devices In Figure 1.8, RonA of lateral GaN unipolar power-switching devices that have been manufactured [2] is plotted as a function of voltage rating. RsubA values of GaN and SiC substrates, which are also shown in Figure 1.8, are calculated as follows. The resistivity and thickness of GaN substrates are, respectively, reported to be 0.018 Ω cm and 600 μm [6], while those of SiC substrates are, respectively, reported to be 0.015–0.02 Ω cm and 350–500 μm [7]. RsubA values of GaN and SiC substrates are thus calculated, respectively,

Specific resistance (mΩcm2)

10

R sub A of GaN substrates

1

R sub A of SiC substrates

R on A of lateral GaN unipolar power-switching devices 0.1 10

100 Voltage rating (V)

1000

Figure 1.8 Voltage-rating dependence of reported room-temperature-specific on-resistance (RonA) of lateral GaN unipolar power-switching devices [2], together with specific substrate resistance (RsubA) of GaN (dashed line) and SiC substrates (dotted lines) [6, 7].

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1.3 Vertical versus Lateral Unipolar Power Devices

7

to be 1.1 (dashed line in Figure 1.8) and 0.53–1.4 mΩcm2 (dotted lines in Figure 1.8). Moreover, RonA of lateral GaN unipolar power-switching devices increases with increasing voltage rating but does not exceed RsubA of GaN and SiC substrates as long as the voltage rating is less than 200V. Furthermore, as stated in Section 1.1, the previously fabricated lateral GaN unipolar switching-devices are formed on Si substrates [2], which are much cheaper and larger than GaN substrates. That means that lateral GaN unipolar power-switching devices are suitable for low-cost and low-voltage applications such as the switching-mode power supply shown in Figure 1.2. With respect to a voltage rating exceeding about 400V, the maximum chip current of lateral GaN-on-Si-substrate unipolar power-switching devices is 70A (A = 0.29 cm2) [8] (Figure 1.9). Because no larger currents have been reported since 2009, this value seems to be a practical limit. Uniform operation of lateral GaN unipolar power-switching devices on a larger GaN-

1000

Unipolar power-switiching devices

[9]

Lateral GaN on GaN [12]

[8]

[11]

Ga N

tic a

on Si

lS iC

10

tic al Ga N

La te ra l

Ve r

Current (A/chip)

100

Ve r

1

0.1 1996

1998

2000

2002

2004

2006

2008

2010

2012

2014

2016

Year Figure 1.9 Reported current per chip of lateral GaN-on-Si substrate (open circles), lateral GaN-on-GaN substrate (open triangle), vertical GaN (solid circles), and vertical SiC (solid squares) unipolar power-switching devices as a function of the year of publication.

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8

Vertical GaN and SiC Power Devices

on-Si chip is probably prevented by the high density of crystalline defects (see Section 2.2.3) and residual stress in GaN layers on nonnative substrates. On the other hand, vertical GaN unipolar power-switching devices are following the same trend as vertical SiC unipolar power-switching devices (up to 350A with A of 1.0 cm2 [9]) but with a 10-year delay. In general, vertical power-switching devices have the advantage of having higher voltage at their bottom so that crossover metallization used in lateral powerswitching devices can be eliminated [10]. A chip current of 23A (A = 0.023 cm2) demonstrated in a vertical GaN unipolar power-switching device [11] is thus considered to increase up to about 350A. It is therefore clear that vertical GaN unipolar power-switching devices are desirable for large-current and high-voltage operation. Note here that the maximum chip current of lateral unipolar power-switching devices may become larger in the future since a newly developed lateral GaN unipolar power-switching device formed on a GaN substrate demonstrated 32A per chip with A of 0.040 cm2 [12]. Note also, however, that the use of GaN substrates for lateral devices sacrifices the low cost expected in the case of lateral devices formed on Si substrates. 1.3.1.2 Vertical versus Lateral SiC Unipolar Power-Switching Devices Figure 1.10 plots reported RonA values of lateral [13−19] and vertical [20−22] SiC unipolar power-switching devices as a function of breakdown voltage. The reported RonA of lateral SiC unipolar power-switching devices is more than 10 times higher than the reported RonA of vertical SiC unipolar power-switching devices. Although an approach to improving the poorer RonA/BV relation was proposed in 2005 [23], its effect has yet to be demonstrated. Therefore, vertical SiC unipolar power-switching devices are considered to be desirable for large-current and high-voltage operation, which is similar to the case of GaN unipolar power-switching devices (described in Section1.3.1.1). 1.3.2

Vertical versus Lateral Unipolar Power Diodes

Since few papers have been published on lateral unipolar SiC power diodes, only unipolar GaN power diodes are considered. Unlike power-switching devices, power diodes do not have control terminals. Therefore, in the case of lateral unipolar power diodes, multiple diodes can be connected in parallel (Figure 1.11); for example, up to eight parallel diodes (consisting of aluminum-gallium-nitride [AlGaN]/GaN heterojunction [24]) have been reported [25]. (Note that AlGaN is an alloy of aluminum nitride [AlN] and GaN.) Among those lateral unipolar power diodes, three parallel AlGaN/GaN diodes on Si

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1.3 Vertical versus Lateral Unipolar Power Devices

9

1000

Specific on-resistance R onA (mΩ cm2)

Unipolar power-switching devices

Lateral SiC 100

10 Vertical SiC 1

0.1

1 Breakdown voltage BV(kV)

10

Figure 1.10 Reported room-temperature-specific on-resistance of lateral (open circles) [13–19] and vertical (solid circles) [20–22] SiC unipolar power-switching devices as a function of breakdown voltage.

AlGaN GaN Anode

AlGaN

Cathode

GaN AlGaN GaN Buffer Substrate

Figure 1.11 Schematic illustration of lateral unipolar power diodes comprising three parallel AlGaN/GaN heterojunction diodes.

substrates with breakdown voltages and chip sizes of, respectively, 600V and 3.4 × 4 mm, and a maximum chip current of 20A were reported [26]. Lateral and vertical unipolar power diodes with A of 1 cm2 are schematically illustrated in Figure 1.12. Unipolar power diodes have offset-voltage characteristics as shown in Figure 1.3, where differential specific on-resistance RonAdiff is defined as dVFA/dIF. Lateral unipolar power diodes should

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10

Vertical GaN and SiC Power Devices

A = 1 cm2

A = 1 cm2

R on A diff R on A diff

(a)

Substrate

R sub A

(b)

Figure 1.12 Schematic illustration of (a) lateral and (b) vertical unipolar power diodes with an area A of 1 cm2, where RonAdiff and RsubA, respectively, denote differential specific on-resistance and specific substrate resistance.

gain an advantage over vertical ones in that RonAdiff does not include RsubA. Unlike lateral unipolar power-switching devices, however, lateral unipolar power diodes with a voltage rating of less than 200V have not been reported. In the case of a voltage rating of about 600V, current-density/voltage characteristics of the above-described three parallel AlGaN/GaN diodes on Si substrates [26] are compared to those of the reported 790-V 50-A vertical GaN unipolar power diodes (with anode area of 3 × 3 mm) [27] (Figure 1.13). Since the chip size of the vertical GaN unipolar power diode is not described in [27], two probable sizes (minimum: 3.4 × 3.4 mm; maximum: 4 × 4 mm) are assumed in the calculation of its current density. Even in the case of assuming the larger chip size, the current density of the vertical GaN unipolar power diode is larger than that of the three parallel AlGaN/GaN diodes (Figure 1.13). While the maximum chip current of lateral GaN unipolar power diodes [26] has not increased since 2011, the maximum chip current of vertical GaN unipolar power diodes is still increasing [27] and following the trend of vertical SiC unipolar power diodes [28], but with a delay of about 10 years (Figure 1.14).

1.4

Summary

This chapter briefly explains the functions of power-semiconductor switching devices and diodes through an example case of a three-phase voltagesource inverter. As materials for next-generation power-switching devices,

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1.4

Summary

11

300

Current density (A/cm2)

Unipolar power diodes Vertical GaN Chip size: 3.4 × 3.4 mm 4.0 × 4.0 mm

200

100 Lateral GaN 0 0.5

0.7

0.9

1.1

1.3

1.5

Voltage (V) Figure 1.13 Current-density/voltage characteristics of large-current (> 20A) lateral GaN (open circles: chip size of 3.4 × 4 mm) [26] and vertical GaN (solid circles: probable minimum chip size of 3.4 × 3.4 mm; solid triangles: probable maximum chip size of 4 × 4 mm) [27] unipolar power diodes.

1000

Unipolar power diodes

[28]

[26]

Ve

N Ga [27] al c i rt

on Si

iC

10

Ve r

Later al Ga N

tic al S

Current (A/chip)

100

1

0.1 1996 1998 2000 2002 2004 2006

2008 2010

2012

2014 2016

Year Figure 1.14 Reported current per chip of lateral GaN-on-Si substrate (open squares), vertical GaN (solid squares), and vertical SiC (solid triangles) unipolar power diodes as a function of the year of publication.

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Vertical GaN and SiC Power Devices

SiC and GaN are introduced as the most promising wide-bandgap semiconductors. With respect to vertical versus lateral device configuration, these materials are compared in the cases of unipolar power-switching devices and diodes. When the voltage rating is less than 200V, lateral unipolar GaN power-switching devices demonstrate their advantage in terms of lower RonA; on the other hand, when the voltage rating exceeds 400V, vertical GaN and SiC power-switching devices and power diodes achieve larger maximum chip current and higher current density compared to lateral GaN ones. In accordance with these findings, the following chapters discuss only vertical power devices.

References [1] Hamada, K., et al., “3.3 kV/1,500A Power Modules for the World’s First All-SiC Traction Inverter,” Japanese Journal of Applied Physics, Vol. 54, 2015, pp. 04DP07-1–04DP07-4. [2] http://epc-co.com/epc/Products/eGaNFETsandICs.aspx. [3] https://arpa-e.energy.gov/?q=slick-sheet-project/vertical-gan-transistors. [4] Shockley, W., “The Theory of p-n Junctions in Semiconductors and p-n Junction Transistors,” Bell System Technical Journal, Vol. 28, No. 3, 1949, pp. 435–489. [5] Blaabjerg, F., and J. K. Pedersen, “Optimized Design of a Complete ThreePhase PWM-VS inverter,” IEEE Transactions on Power Electronics, Vol. 12, No. 3, 1997, pp. 567–577. [6] Yoshida, T., et al., “Preparation of 3-inch Freestanding GaN Substrates by Hydride Vapor Phase Epitaxy with Void-Assisted Separation,” Phyica Status Solidi A, Vol. 205, No. 5, 2008, pp. 1053–1055. [7] https://www.wolfspeed.com/index.php/downloads/dl/file/id/888/product/0/ materials_catalog.pdf. [8] Kambayashi, H., et al., “Enhancement-Mode GaN Hybrid MOS-HFETs on Si Substrates with over 70-A Operation,” International Symposium on Power Semiconductor Devices and ICs, Barcelona, June 14–18, 2009, pp. 21–24. [9] Nakamura, T., et al., “High-Performance SiC Power Devices and Modules with High Temperature Operation,” International Symposium on VLSI, Automation and Test, Hsinchu, April 25–28, 2011, pp. 1–2. [10] Ueda, D., “Renovation of Power Devices by GaN-Based Materials,” International Electron Devices Meeting, Washington, D.C., June 7–9, 2015, pp. 422–425. [11] Oka, T., et al., “Over 10-A Operation with Switching Characteristics of 1.2 kVClass Vertical GaN Trench MOSFETs on a Bulk GaN Substrate,” International Symposium on Power Semiconductor Devices and ICs, Prague, June 12–16, 2016, pp. 459–462.

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1.4

Summary

13

[12] Handa, H., et al., “High-Speed Switching and Current-Collapse-Free Operation by GaN Gate Injection Transistors with Thick GaN buffer on Bulk GaN Substrates,” International Electron Devices Meeting, San Francisco, Dec. 5–7, 2016, pp. 256–259. [13] Okamoto, M., et al., “Lateral RESURF MOSFET Fabricated on 4H-SiC ( 000 1 ) C-Face,” IEEE Electron Device Letters, Vol. 25, No. 6, 2004, pp. 405–407. [14] Fujikawa, K., et al., “800 V 4H-SiC RESURF-Type Lateral JFETs,” IEEE Electron Device Letters, Vol. 25, No. 12, 2004, pp. 790–791. [15] Banerjee, S., et al., “Robust, 1000-V, 130-mΩcm2, Lateral Two-Zone RESURF MOSFETs in 6H-SiC JFETs,” International Symposium on Power Semiconductor Devices and ICs, Santa Fe, June 4–7, 2002, pp. 69–72. [16] Zhang, Y., et al., “1,000-V 9.1-mΩcm2 Normally off 4H-SiC Lateral RESURF JFET for Power Integrated Circuit Applications,” IEEE Electron Device Letters, Vol. 28, No. 5, 2007, pp. 404–407. [17] Kimoto, T., et al., “Design and Fabrication of RESURF MOSFETs on 4HSiC(0001), ( 1120 ), and 6H-SiC(0001),” IEEE Transactions on Electron Devices, Vol. 52, No. 1, 2005, pp. 112–117. [18] Noborio, M., J. Suda, and T. Kimoto, “4H-SiC Lateral Double RESURF MOSFETs with Low on Resistance,” IEEE Transactions on Electron Devices, Vol. 54, No. 5, 2007, pp. 1216–1223. [19] Lee, W.-S., et al., “Design and Fabrication of 4H-SiC Lateral High-Voltage Devices on a Semi-Insulating Substrate,” IEEE Transactions on Electron Devices, Vol. 59, No. 3, 2012, pp. 754–760. [20] Nakamura, T., et al., “High Performance SiC trench Devices with Ultra-Low Ron,” International Electron Devices Meeting, Washington, DC, June 5–7, 2011, pp. 599–601. [21] Harada, S., et al., “3.3-kV-Class 4H-SiC MeV-Implanted UMOSFET with Reduced Gate Oxide Field,” IEEE Electron Device Letters, Vol. 37, No. 3, 2016, pp. 314–316. [22] Kawahara, K., et al., “6.5-kV Schottky-Barrier-Diode-Embedded SiC-MOSFET for Compact Full-Unipolar Module,” International Symposium on Power Semiconductor Devices and ICs, Sapporo, May 28–June 1, 2017, pp. 41–44. [23] Baliga, B. J., Silicon Carbide Power Devices, Singapore: World Scientific, 2005, pp. 471–472. [24] Ishida, H., et al., “Unlimited High Breakdown Voltage by Natural Super Junction of Polarized Semiconductor,” IEEE Electron Device Letters, Vol. 29, No. 10, 2008, pp. 1087–1089. [25] Terano, A., et al., “GaN-Based Multi-Two-Dimensional-Electron-Gas-Channel Diodes on Sapphire Substrates with Breakdown Voltage of over 3 kV,” Japanese Journal of Applied Physics, Vol. 54, 2015, pp. 06650-1–06650-5. [26] Shibata, D., et al., “GaN-Based Multijunction Diode with Low Reverse Leakage Current Using p-Type Barrier Controlling Layer,” International Electron Devices Meeting, San Francisco, Dec. 5–7, 2011, pp. 587–590.

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Vertical GaN and SiC Power Devices

[27] Tanaka, N., et al., “50-A Vertical GaN Schottky Barrier Diode on a Freestanding GaN Substrate with Blocking Voltage of 790V,” Applied Physics Express, Vol. 8, 2015, pp. 071001-1−071001-3. [28] Nakamura, T., et al., “Development of SiC Diodes, Power MOSFETs and Intelligent Power Modules,” Physica Status Solidi A, Vol. 206, No. 10, 2009, pp. 2403–2416.

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CHAPTER

2 Contents 2.1 Introduction

Physical Properties of GaN and SiC

2.2 Crystal Structures 2.3 Energy Bands 2.4 Impurity Doping 2.5 Carrier Mobility 2.6 Impact Ionization 2.7 Figure of Merit 2.8 Summary

2.1

Introduction

As stated in Section 1.1, wide-bandgap semiconductors, such as GaN and SiC, have attracted great attention due to their superior material properties compared to silicon; however, neither GaN nor SiC exist in significant quantities in nature. While GaN was first synthesized in powder form by Maruska and Tietjen in 1969 [1], the first synthesis of SiC (in 1824) was reportedly accidental: the result of attempts by Berzelius to make diamond [2]. In fabrication of power devices based on GaN or SiC, a GaN or SiC layer is grown on a substrate (described in Section 1.3). The unavailability of GaN substrates forced early researchers to use sapphire substrates because the thermal-expansion coefficient of sapphire is relatively close to that of GaN. Since 1986, Akasaki, Amano, and their coworkers have improved the quality of GaN layers by inserting an AlN nucleation layer between the GaN layer and the sapphire substrate [3, 4]. In 1988, they achieved p-type doping, which introduces

15

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16

Vertical GaN and SiC Power Devices

holes (i.e., positively charged carriers [see Section 1.3]), in GaN [5]. The first development of practical GaN optical devices (namely, p-n junction blue-light-emitting diodes fabricated by Nakamura et al. in 1991 [6]) was followed by the first demonstration of a GaN electron device on a sapphire substrate in 1993 [7]. A large lattice misfit of about 13% at growth temperature [8], however, generated a high density of crystalline defects (namely, dislocations, as described in Section 2.2.3) in GaN layers grown on sapphire substrates. In 1999, two-inch freestanding GaN substrates were produced from 250–300-µm thick GaN films grown on sapphire [9]. Since then, vertical GaN power devices have been fabricated [10], and electrical characterization of GaN layers with a low density of defects have been investigated [11]. In contrast to GaN, SiC has been mainly used as a substrate for growing a SiC layer, since a technique for seeded sublimation called the modified Lely method was developed by Tairov and Tsvetkov in 1978 [12]. Sublimation was needed because the solubility of carbon in silicon solution is low (e.g., only 0.1% carbon can be dissolved in silicon at 2,073– 2,273K [13]). In contrast to p-type doping in GaN, p-type doping in SiC has not been difficult. However, growing a SiC layer had been difficult because of the tendency of SiC to crystallize into over 250 modifications (so-called polytypes) [14]. In 1987, Kuroda et al. proposed a technique called stepcontrolled epitaxy [15] to reproduce the same polytype in a SiC layer as that in the substrate it is grown on. Note that the term epitaxy, which means a crystalline overlayer having well-defined orientation with respect to the substrate crystal structure (see Chapter 6), comes from two Greek words: epi meaning upon and taxis meaning arrangement. Owing to the above two techniques, the opportunity to fabricate and apply SiC power devices grew ripe in the early 1990s [16]. In view of the above-described history concerning GaN and SiC, the remainder of this chapter compares crystal structures, including crystal defects, of GaN and SiC and then describes their energy bands, impurity doping, carrier mobility, and impact ionization. Since some vertical GaN power-switching devices utilize AlGaN/GaN heterostructures [17−19], crystal structures and energy bands of AlN are also described. Finally, Section 2.7 introduces a commonly used figure of merit for power devices.

2.2

Crystal Structures

AlN, GaN, and SiC are compound semiconductors that allow a stoichiometry of 50% aluminum, gallium, or silicon and 50% nitrogen or carbon. Note that silicon germanium (Si1-xGex) is not a compound semiconductor but an alloy semiconductor because x can take any value from 0 to 1. The

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2.2

Crystal Structures

17

electronic structures of aluminum, gallium, nitrogen, silicon, and carbon atoms in their ground states are as follows: 13Al: 31Ga: 7N:

(2.1a)

1s2 2s2 2p6 3s2 3p6 3d10 4s2 4p1

(2.1b)

1s2 2s2 2p3

14Si: 6C:

1s2 2s2 2p6 3s2 3p1

1s2 2s2 2p6 3s2 3p2

1s2 2s2 2p2

(2.1c) (2.1d) (2.1e)

where the subscripts and the superscripts, respectively, show atomic number and number of orbital electrons. Both aluminum and gallium have three valence electrons in their outermost shells, while nitrogen has five valence electrons in its outermost shells. AlN and GaN are thus known as III-V compound semiconductors. On the other hand, SiC is called a IV-IV compound semiconductor because both silicon and carbon have four valence electrons in their outermost shells. 2.2.1

Crystal Structures of AlN and GaN

AlN and GaN can take any of the following crystalline structures: rock salt (Figure 2.1), zincblende (Figure 2.2[a]), or wurtzite (Figure 2.2[b]). Rocksalt structures are observed under very high pressures only: 23 GPa for AlN [20] and 52 GPa for GaN [21]. Under ambient conditions, the thermodynamically stable structure for both AlN and GaN is wurtzite. The energy differences for various compound semiconductors (calculated using wave-function and classical-orbital radii [22]) are plotted in Figure 2.3. In

Figure 2.1 Rock-salt crystal structure (solid circles: aluminum and/or gallium atoms; open circles: nitrogen atoms).

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Vertical GaN and SiC Power Devices

(a)

(b)

Wurtzite-zincblende energy difference (meV/atom)

Figure 2.2 (a) Zincblende and (b) wurtzite crystal structures (solid circles: aluminum and/or gallium atoms; open circles: nitrogen atoms).

20 Calculated from wave-function orbital radii Calculated from classical orbital radii

10 Zincblende stabilized

0 Wurtzite stabilized

−10

−20

Figure 2.3

SiC

AlN

GaN

GaP

GaAs

Calculated energy differences for wurtzite-zincblende structures [22].

contrast to zincblende-stabilized III-V compound semiconductors, such as gallium phosphide (GaP) and gallium arsenide (GaAs), both AlN and GaN are wurtzite-stabilized III-V compound semiconductors. Note that it is not clear from Figure 2.3 whether SiC is a zincblende-stabilized or wurtzitestabilized IV-IV compound semiconductor; experimentally, however, as described in Section 2.2.2, zincblende SiC often appears at relatively low temperature Plan and perspective views of the wurtzite structure [Figure 2.2(b)] are shown in Figure 2.4. In such hexagonal-prism crystals, crystal planes can be expressed with Miller-Bravais indices (hkil) [23] such that the relation h+k+i=0

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(2.2)

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2.2

Crystal Structures

19

(a)

c a2

a3 a1 (b)

Figure 2.4 (a) Plan and (b) perspective views of the wurtzite structure shown in Figure 2.2(b) (solid circles: aluminum and/or gallium atoms; open circles: nitrogen atoms).

is always satisfied. The indices are determined by performing the following steps:  Determining the intercepts of the plane with the a1, a2, a3, and c axes;  Forming the reciprocals of the intercepts;  Finding the smallest set of integers that are in the same ratio as the intercepts;  Writing the indices with a bar if they are negative. Typical crystal planes in the wurtzite structure are shown in Figure 2.5. The (0001) plane (which features aluminum and/or gallium polarity (Figure 2.6[a]) shown in Figure 2.5(a) is the most common substratesurface for GaN power devices [9]. The following substrates have also been fabricated: ( 000 1 ) which features nitrogen polarity (Figure 2.6[b]) GaN [24], ( 10 10 ) so-called m-plane GaN [25], ( 1120 ) so-called a-plane GaN [26], (0001) AlN [27], ( 10 10 ) AlN [28], and (0001) AlGaN [29].

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Vertical GaN and SiC Power Devices

(0001) plane (N polarity) (b)

(0001) plane (Al and/or Ga polarity) (a) Figure 2.5 2.4.

(1010) m-plane

(1120) a-plane (d)

(c)

Typical crystal planes in the wurtzite structure shown in Figures 2.2(b) and

Al and/or Ga polarity

N polarity

(a)

(b)

Figure 2.6 Atomic arrangement of (a) (0001) and (b) ( 000 1 ) planes in the wurtzite structure shown in Figure 2.5(a, b) (solid circles: aluminum and/or gallium atoms; open circles: nitrogen atoms).

2.2.2

Crystal Structures of SiC

Polytypes are expressed with the number of Si-C stacking layers in a unit cell and the crystal system (e.g., C for cubic and H for hexagonal). The atomic arrangements of common polytypes (i.e., 3C-, 4H-, and 6H-SiC), together with those of 2H-SiC, are shown in Figure 2.7, where A, B, and C are the occupation sites in a hexagonal close-packed structure (Figure 2.8). 3C-SiC (i.e., zincblende SiC) is a low-temperature stable polytype that is transformed into hexagonal polytypes above 2,300K [30]. 2H-SiC (i.e., wurtzite SiC) is also unstable at high temperatures. As a power semiconductor, 4H-SiC is superior to 6H-SiC because electron transport in 6H-SiC strongly depends on crystallographic orientations (see Section 2.5).

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2.2

Crystal Structures

21

A C B A C B A

C B A B C B A

A B A B A B A

A B C A C B A

3C (zincblende)

4H

6H

2H (wurtzite)

(a)

(b)

(c)

(d)

Figure 2.7 Schematic cross-sections of common polytypes of (a) 3C-SiC, (b) 4H-SiC, (c) 6H-SiC, and (d) 2H-SiC. Large and small circles denote silicon and carbon atoms, respectively.

A

A

A

B A

A

B A

A

A

A

C

C

A

A

A

Figure 2.8 Schematic plan view of occupation sites (A, B, and C) in the hexagonal closepacked structure.

Note that in accordance with the above definition, zincblende and wurtzite GaN (or AlN) can be expressed as 3C- and 2H-GaN (or AlN). For simplicity, however, GaN (or AlN) hereinafter means the most stable wurtzite GaN (or AlN). 2.2.3

Crystal Defects

Some crystal defects are electrically active and are thus of major concern for power devices. In general, they can be categorized as four types: zero-dimensional (i.e., point), one-dimensional (i.e., line), two-dimensional (i.e., areal), and three-dimensional (bulk) defects. Point defects influence carrier lifetime (see Chapter 3) and, consequently, conductivity modulation in bipolar devices (see Section 3.7). Two basic types of native point defects are well-known: vacancies (also known as Schottky defects) (i.e., atoms missing from lattice sites) and interstitials (also known as Frenkel defects) (i.e., additional atoms in between lattice sites) [31]. In thermal equilibrium, the concentrations of vacancies (CV) and interstitials (CI) take equilibrium values (CV* and CI*, respectively) that are determined from the respective free energies of formation, FV and FI, as follows [32, 33]:

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22

Vertical GaN and SiC Power Devices

CV* = CsV exp(−FV/kT)

(2.3a)

CI* = CsI exp(−FI/kT)

(2.3b)

where CsV and CsI are, respectively, the concentrations of the sites that are open to vacancies and interstitials, k is Boltzmann’s constant, and T is absolute temperature. In the case of silicon, CsV = 2.0 × 1023 cm−3, FV = 2.0 eV, CsI = 5.0 × 1022 cm−3, and FI = 2.36 eV have been conventionally used in a commercial process simulator [34]. These values were successfully applied for boron diffusion in 4H-SiC (see Section 7.4), even though the exact values for GaN and 4H-SiC are unknown. Other than general vacancies and interstitials, carrier traps in GaN have been investigated [35] and the reported results on two major point defects (i.e., Z1/2 [36] and EH6/7 [37]) in 4H-SiC have been summarized [38]. Line defects are called dislocations. Edge (Figure 2.9[a]) and screw dislocations (Figure 2.9[b]) are the two primary types of dislocations, while mixed dislocations are intermediate between these dislocations. An edge dislocation is formed when an extra (or missing) half-plane of atoms is introduced. In Figure 2.9(a), the dislocation lying in the basal plane (i.e., [0001]) is called a basal-plane dislocation (BPD); the dislocation lying perpendicular to (0001) is called a threading edge dislocation (TED). The difference between a BPD and a TED is only the direction of the dislocation; thus, a BPD often converts to a TED and vice versa. With respect to screw dislocations, a threading dislocation (solid line in Figure 2.9[b]) becomes an origin of spiral growth (see Sections 6.2, 6.4, and 6.5). Note, however, that in the case of GaN and 4H-SiC, the height of the spiral step differs: one Ga-N bilayer in the case of GaN and four Si-C bilayers in the case of 4H-SiC. Since threading dislocations act as nonradiative recombination centers (see Section 3.4.2) in GaN [39], they directly affect performance of GaN-based light emitters, especially laser diodes (LDs). The use of GaN substrates, instead of sapphire substrates, reduced the density of threading dislocations to the order of 106 cm−2, thereby improving the reliability of GaN LDs. Threading dislocations similarly influence carrier lifetime in GaN and 4H-SiC bipolar power devices locally, but they do not influence carrier lifetime in unipolar power devices [38]. Areal defects that alter the periodic sequence of layers are called stacking faults (Figure 2.10). In GaN, stacking faults are rarely observed because stacking-fault energy is high (1.2 J/m2) [40]. Furthermore, theory suggests that stacking faults in GaN are not electrically active [41]. In 4H-SiC, on the other hand, stacking faults are common defects because stacking-fault energy is low (0.014 J/m2) [42].

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2.2

Crystal Structures

23

(a)

(b)

Figure 2.9 Schematic illustration of (a) edge and (b) screw dislocations. In (a), an extra half-plane is inserted. When the surface in (a) is (0001), the dashed line is a basal plane dislocation and the dotted line is a threading-edge dislocation.

So-called inversion domains are also known as areal defects in GaN. Inversion domains have opposite growth polarity to that of the matrix. In the case of a (0001) surface, V-shape pits are formed in inversion domains because GaN having nitrogen-polarity grows slower than GaN having gallium-polarity [43]. Inversion domains combined with strain change the piezoelectric field [44], and that change possibly affects the characteristics of vertical GaN power-switching devices with AlGaN/GaN heterostructures [17−19].

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24

Vertical GaN and SiC Power Devices

A

A

A B

A

A

A

A

A

A

B

B C

A

A B

C

C A

C

C

C

C

A A B

C

A

A

C

C

C

A

B

B

A

A

C

A

A A

C

C

A

C

C A

B B A

C A

B

C A

C

B A

A

B

A

B

A

B B

B

A B

A

A B

C

B

A

A

A

A

B A

A A

Stacking fault Figure 2.10 Schematic plan view of occupation sites (B) and stacking-fault sites (C) on occupation sites (A).

Bulk defects are associated with a volume including voids, cracks, and/ or nano/micropipes. Nanopipes in GaN and micropipes in 4H-SiC are tunnel-like defects (i.e., open-core screw dislocations) aligned in the growth direction of the crystal, and they penetrate the film. In the case of epitaxial growth of 4H-SiC, micropipes were reported to be dissociated into multiple closed-core screw dislocations, leading to closure of micropipes [45, 46].

2.3

Energy Bands

An electron acted on by the coulombic potential of an atomic nucleus is allowed at certain energy levels only. As more atoms are added to form a crystal, the forces exerted on each electron are altered. Since the Pauli exclusion principle states that each allowed electron energy level has to be different, the original energy level splits into N different allowed levels when N atoms are added. Since the original energy level is in the order of a few electronvolts, and N is in the order of 1022, the separation between the N different energy levels is in the order of 10−22 eV. This energy-level separation is so small (compared to thermal energy in the order of 10-2 eV) that electrons can easily move between the levels. The N different energy levels can therefore be regarded as a continuous band of allowed energies (i.e., an energy band). In semiconductors, the valence electrons in the outermost shell completely fill an allowed energy band (i.e., the valence band), and an energy gap to the next-higher band exists (Figure 2.11). At temperatures above 0K,

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2.3

Energy Bands

25

Energy gap E g

Conduction band

EC ED EF EA

Valence band

EV

Figure 2.11 Energy bands for a semiconductor [bottom edge of the conduction band (EC), donor level (ED), Fermi level (EF), acceptor level (EA), and top edge of the valence band (EV)].

the valence band is not entirely filled because a small number of electrons possess enough thermal energy to be excited across the energy gap into the next allowed band. Since the electrons in the upper band can respond to an applied electric field to produce current, the upper band is called the conduction band. The bottom edge of the conduction band and the top edge of the valence band are usually expressed as EC and EV, respectively. When electrons are excited into the conduction band, empty states are left in the valence band. If an electric field is applied, nearby electrons can move into those empty states and produce current. The motion of charge in the valence band can thus be expressed in terms of the vacant states by treating the states as particles with positive charge. These particles are called holes (described in Section 1.3), whose concept can be understood through the analogy of bubbles in running water. In semiconductors, EC and EV are functions of crystal momentum, and the energy gap Eg is defined as the difference between the minimum EC and the maximum EV (Figure 2.12). In the case of direct-bandgap semiconductors (e.g., AlN and GaN), the momentum at which EC reaches a minimum and the momentum at which EV reaches a maximum are the same (Figure 2.12[a]); however, in the case of indirect-bandgap semiconductors (e.g., silicon and SiC), they are different (Figure 2.12[b]). In (a), an electron can shift from the highest-energy state in the valence band to the lowest-energy state in the conduction band without a change in crystal momentum. In (b), an electron cannot shift from the highest-energy state in the valence band to the lowest-energy state in the conduction band without a change in crystal momentum. Energies denoted by the solid vertical arrow come from photons (i.e., a quantum of electromagnetic radiation), while energy denoted by the dotted horizontal arrow comes from a phonon (i.e., an excited state in the quantum-mechanical quantization of the modes of vibrations).

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Vertical GaN and SiC Power Devices

Energy

Conduction band

Valence band

Momentum (a)

Energy

Conduction band

Phonon-assisted transition Valence band

Momentum (b)

Figure 2.12 Energy versus crystal momentum for semiconductors with (a) direct bandgap and (b) indirect bandgap.

Eg can be obtained by optical absorption spectroscopy [31], in which optical-absorption coefficient α (cm−1) is the most important parameter. The intensity of light, I0, exponentially decreases to I(x) at depth x from the surface as I(x) = I0 exp(−αx)

moch-ch02.indd 26

(2.4)

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2.4

Impurity Doping

27

In direct-bandgap semiconductors, α is empirically known to be proportional to (Ephoton−Eg)0.5, where Ephoton is the energy of a photon. The square root of the reported values of α [47−49] is thus plotted in Figure 2.13 as a function of Ephoton. In the case of AlN and GaN, the onset of absorption is steep, and the threshold of absorption determines Eg. In the case of 4H-SiC, on the other hand, optical absorption slowly increases, even when Ephoton exceeds Eg. Such different optical-absorption behaviors lead to photon recycling playing either a dominant or a negligible role (see Chapter 4).

2.4

Impurity Doping

The most useful means of controlling the number of carriers is incorporating substitutional impurities called dopants, namely, donors that donate electrons to conduction bands or acceptors that accept electrons from (and leave holes) in valence bands. If most of the dopants are donors, the semiconductor is called n-type; on the other hand, if most of the dopants are acceptors, the semiconductor is called p-type. In intrinsic (i.e., nondoped) semiconductors, all carriers result from excitation across Eg. Consequently, electron concentration n and hole concentration p equal intrinsic carrier concentration ni. The mass-action law, namely, np = ni2

(2.5)

400

293−300K GaN

AlN

α0.5(cm−0.5)

300

200

100

4H-SiC 0

3

4

5

6

7

Photon energy Ephoton (eV) Figure 2.13 Square root of reported optical-absorption coefficients of AlN, GaN, and 4HSiC as a function of photon energy [47−49].

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28

Vertical GaN and SiC Power Devices

gives ni as ni = (NCNV)0.5 exp(−Eg/2kT)

(2.6a)

NC = 2 (2πmnkT/h2)1.5

(2.6b)

NV = 2 (2πmpkT/h2)1.5

(2.6c)

where NC and NV are, respectively, effective density of states in conduction bands and valence bands; mn and mp denote, respectively, effective masses of electrons and holes; and h is Planck’s constant. While NC and NV vary in proportion to T1.5, ni is much more temperature-dependent due to the exponential term in (2.6a). For GaN with Eg = 3.44 eV [50] and 4H-SiC with Eg = 3.23 eV [51], ni doubles about every 3-K increase in temperature near room temperature. Dependences of ni on T for GaN and 4H-SiC are expressed as [52, 53]: niGaN = (4.3 × 1014 × T1.5 × 8.9 × 1015 × T1.5)0.5 × exp(−3.44 × 1.6 × 10−19/2/1.38 × 10−23/T) = 2.0 × 1015T1.5 exp(−2.0 × 104/T) (cm−3)

(2.7a)

ni4H-SiC = (3.25 × 1015 × T1.5 × 4.8 × 1015 × T1.5)0.5 × exp (−3.23 × 1.6 × 10−19/2/1.38 × 10−23/T) = 3.9 × 1015T1.5 exp(−1.9 × 104/T) (cm−3)

(2.7b)

and

and they are shown in Figure 2.14 in comparison with the dependence of ni on T for silicon. For example, at 150°C, ni in Si reaches 1013 cm−3, which is the practically minimum doping level. In GaN and 4H-SiC, on the other hand, ni is far below that level even at 250°C. This lower ni is the reason GaN and 4H-SiC power devices can operate at a much higher temperature. 2.4.1

n-Type Doping

As donors, silicon is used for GaN, while nitrogen or phosphorus is used for 4H-SiC. While a large amount of energy (exceeding Eg) is required to excite an electron from the valence band to the conduction band, only a small amount of energy is required to excite an electron from a donor to the conduction band. This requirement corresponds to a donor level ED being located just below EC (Figure 2.11). The reported minimum ionization

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Impurity Doping

Intrinsic carrier concentration (cm−3)

2.4

29

10 15

10 13

10 9 Si

10 3 10 −3 10 −9

4H-SiC

10 −15 10 −21 −50

GaN 0

50

100 150 Temperature (°C)

200

250

Figure 2.14 Temperature dependences of intrinsic carrier concentration in GaN, 4H-SiC, and silicon.

energy for donors (i.e., EC−ED) is 0.02 eV for silicon in GaN [51] and 0.059 eV for nitrogen in 4H-SiC [54]. At room temperature, these ionization energies are comparable to thermal energy (i.e., 0.026 eV), so all the donors (with concentration ND) are considered to be ionized. The charge-neutrality condition in an n-type semiconductor is thus expressed as ND+p = n

(2.8)

Combining (2.5) with (2.8) leads to the following equation: n2+NDn−ni2 = 0

(2.9)

The positive solution of (2.9) under the condition ND >> ni is n = [−ND+(ND 2+4ni2)0.5]/2 ≈ ND

2.4.2

(2.10)

p-Type Doping

As acceptors, magnesium is used for GaN, while aluminum or boron is used for 4H-SiC. Unlike ED, acceptor level EA is relatively far from EV (Figure 2.11). Reported acceptor ionization energy (i.e., EA−EV) is about 0.2 eV for magnesium in GaN [55]; 0.2 eV for aluminum; and 0.3 eV for boron in 4H-SiC [56]. Since these values are much larger than thermal energy at the practically highest temperature (e.g., 0.045 eV at 250°C), not all acceptors are ionized. Concentration of ionized acceptors is given by [57]

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30

Vertical GaN and SiC Power Devices

NA- = NA/{1+4 exp[(EA−EF)/kT]}

(2.11)

where NA is acceptor concentration and EF is the Fermi level (i.e., the energy level of an electron at thermodyanmic equilibrium with 50% probability of being occupied). Since electron and hole concentrations are expressed as [57] n = NC exp[−(EC−EF)/kT]

(2.12a)

p = NV exp[−(EF−EV)/kT]

(2.12b)

and

the charge-neutrality condition in a p-type semiconductor is expressed as NV exp[−(EF − EV)/kT] = NA/{1 + 4 exp[(EA − EF)/kT]} + NC exp[−(EC − EF)/kT] ≈ NA/{1 + 4 exp[(EA − EF)/kT]}

(2.13)

From (2.13), EF can be graphically determined, as shown in the examples for p-type GaN in Figure 2.15. Note that the acceptor ionization ratio rA (i.e., NA−/NA) depends not only on T but also on NA (e.g., at T = 150°C, rA = 8.6% when NA = 1×1019 cm−3, while rA = 58% when NA = 1 × 1017 cm−3, as shown in Figure 2.15[b]).

2.5

Carrier Mobility

Drift velocity vdrift is defined as net carrier velocity in applied electric field E. Electrons are accelerated in the field direction during the time between their collisions with the crystal lattice. When colliding, electrons exchange energy with the lattice. As long as |E| is small, however, the energy exchanged is small and the lattice is not heated appreciably. If the elementary charge (1.6 × 10−19 C) is denoted by q, the force on an electron is −qE and the momentum gained is mnvdrift, so the equation −qEτ = mnvdrift

(2.14)

is satisfied for mean scattering time τ. Therefore, vdrift is given by vdrift = −μnE

(2.15a)

μn = qτ/mn

(2.15b)

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Carrier Mobility

Concentration (cm−3)

2.5

31

1.E+21 21

10

(4.7%) 4.7× 1016 4.6× 1015 (4.6%)

NV

p

NA- (NA = 1× 1017 cm-3)

1.E+15 10 15 1.E+12 10 12

(a)−50 oC, E A−E V = 0.2 eV

10 9 1.E+09

Concentration (cm−3)

00

1.E+21 21

10

(8.6%) 8.6× 1017 5.8× 1016 (58%)

NV

0.1 0.1

p

0.3 0.3

0.4 0.4

NA- (NA = 1× 1019 cm-3) NA- (NA = 1× 1017 cm-3)

1.E+15 10 15

(b) 150oC , E A−E V = 0.2 eV

10 9 1.E+09 00

Concentration (cm−3)

0.2 0.2 E F −E V (eV)

1.E+18 10 18

1.E+12 10 12

1.E+21 21

(16%) 1.6× 1018 8.0× 1016 (80%)

NA- (NA = 1× 1019 cm-3)

1.E+18 10 18

10 N

0.1 0.1

0.2 0.2 E F −E V (eV)

p

0.3 0.3

0.4 0.4

NA- (NA = 1× 1019 cm-3)

V

1.E+18 10 18 1.E+15 10 15

NA- (NA = 1× 1017 cm-3)

1.E+12 10 12

(c) 250oC , E A−E V = 0.2 eV

9

10 1.E+09 00

0.1 0.1

0.2 0.2 E F −E V (eV)

0.3 0.3

0.4 0.4

Figure 2.15 Shockley diagram to determine Fermi level EF and hole concentration p in p-type GaN with acceptor ionization energy of 0.2 eV at (a) −50°C, (b) 150°C, and (c) 250°C. Each diagram shows two values of acceptor concentration, NA.

where μn is called electron mobility. Since analogous arguments apply to holes, total drift current density Jdrift can be written as Jdrift = (−q)n(−μnE) + qpµpE = q(nμn + pμp)E

(2.16)

Room-temperature μn and μp perpendicular to the c-axis are plotted in Figure 2.16 as a function of dopant density in GaN and 4H-SiC. Note that the μn values in the case of GaN and 4H-SiC are much larger than the μp value in the case of GaN and 4H-SiC. For that reason, electrons are chosen as carriers in low-on-resistance unipolar GaN and 4H-SiC power devices (see Chapters 8 and 9).

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32

Vertical GaN and SiC Power Devices

1000

Mobility (cm2/Vs)

Room temperature 800 600 400 200

μn GaN

μp4H-SiC

μn 4H-SiC

μpGaN

0

10

10 17

10 18 |ND − NA|(cm−3)

10 19

10 20

Figure 2.16 Room-temperature electron and hole mobility perpendicular to the c-axis in GaN [55, 58] and 4H-SiC [59, 60].

With respect to the reported μn at ND = 1 × 1016 cm−3, in the case of 6H-SiC, μn parallel to the c-axis was 60 cm2/Vs, and μn perpendicular to the c-axis was 400 cm2/Vs; in contrast, in the case of 4H-SiC, μn parallel to the caxis was 900 cm2/Vs, and μn perpendicular to the c-axis of 800 cm2/Vs [61]. Such relatively isotropic electron transport is the reason 4H-SiC is preferred to 6H-SiC as a material for power devices.

2.6

Impact Ionization

Impact ionization is a process by which electron-hole pairs generated by carriers (mainly holes in the case of GaN [62] and 4H-SiC [63]) gain enough energy from an electric field (Figure 2.17). This process creates the onset of avalanche breakdown and is characterized by the impact-ionization coefficient, which is defined as the number of electron-hole pairs created by a mobile carrier traversing a unit length through the depletion region in the direction of the electric field. Although a lot of impact-ionization coefficients have been experimentally determined [62−68], they differ appreciably. This difference is probably due to the presence of defect, a nonuniform electric field, and the onset of premature breakdown at chip edges [62]. In this book, the largest critical electric field (Ecritical) ever reported (i.e., 3.75 MV/cm [69] for GaN and 2.50 MV/cm for 4H-SiC [68]) is thus used instead of impact-ionization coefficients. Accordingly, avalanche breakdown can be assumed to occur simply when the maximum electric field equals to Ecritical, whose slight dependence on T and ND, for example, in the case of 4H-SiC [68],

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2.7

Figure of Merit

33

EC

EV

Figure 2.17 Multiplication of electrons and holes from impact ionization due to holes.

Ecritical = (2.653 + 2.222 × 10−6 T2 – 1.166 × 10−3T)/[1–0.25 log10(ND/1016)] MV/cm

(2.17)

is ignored hereafter.

2.7

Figure of Merit

As a final section of this chapter on physical properties, Baliga’s figure of merit for power devices (BFOM) [70] and Baliga’s figure of merit for devices operating at high frequencies (BHFFOM) [71] are derived by considering a uniformly doped drift layer for unipolar power devices with a parallel-plane configuration. Poisson’s equation is given as dE(x)/dx = qND/εrεo

(2.18)

where εr is relative permittivity (i.e., 10.4 parallel to the c-axis of GaN [72] and 10.0 parallel to the c-axis of 6H-SiC [73]), and εo is permittivity in vacuum (i.e., 8.85 × 10−14 F/cm). As shown in Figure 2.18, the solution to (2.18) gives a triangular electric-field distribution. At the onset of avalanche breakdown, E(0) can be assumed to be Ecritical. Since the minimum thickness of the drift layer at which E becomes zero is WD, ND is given by

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34

Vertical GaN and SiC Power Devices

E critical

x

O WD

Drift layer

Substrate

Figure 2.18 Uniformly doped drift layer and its electric-field distribution.

ND = (εrεo/qWD)Ecritical

(2.19)

Breakdown voltage BV is equal to the area of the triangle, (i.e., Ecritical WD /2), so WD is given by WD = 2BV/Ecritical

(2.20)

Since in an n-type drift layer, Jdrift can be approximated from (2.16) as Jdrift ≈ qND μn (BV/WD)

(2.21)

specific resistance of the ideal drift layer is obtained from (2.19)−(2.21) as Rideal = 4BV2/BFOM

(2.22)

where BFOM = εrεoμnEcritical3

(2.23)

In the case of metal-insulator-semiconductor field-effect transistors (see Section 9.7) whose gate is biased at VG, input capacitance per unit area CI (see Section 9.2.2) is given as [71] CI = (εrεoqND/2VG)0.5

moch-ch02.indd 34

(2.24)

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2.8

Summary

35

By using (2.19) and (2.20) in (2.24), it can be shown that CI = εrεoEcritical/2(VGBV)0.5

(2.25)

BHFFOM, which has the dimensions of frequency, is defined as [71] BHFFOM = 1/RidealCI

(2.26)

By using (2.22)−(2.24), (2.26) can be derived in terms of material parameters as follows: BHFFOM = μnEcritical2VG0.5/2BV1.5

(2.27)

While εr and μn of GaN and 4H-SiC are comparable to those of silicon (i.e., 11.7 [74] and 1,000 cm2/Vs [75]), Ecritical of GaN and 4H-SiC is about 10 times higher than Ecritical of silicon (i.e., 0.2 MV/cm [75]). As listed in Figure 2.19, calculated BFOM and BHFFOM of GaN and 4H-SiC are, respectively, more than 1,000 times and more than 100 times higher than those of silicon.

2.8

Summary

This chapter introduces the development history and physical properties of GaN and SiC with an emphasis on crystal structures. The chapter’s description of crystal defects, especially stacking faults in 4H-SiC, will be referred to in Section 12.6. The chapter also briefly describes energy bands and impurity doping. To introduce the BFOM and BHFFOM, the chapter compares the relative permittivity, electron mobility, and critical-electric field in the case of GaN and 4H-SiC. On the basis of these described properties, this book compares vertical GaN and 4H-SiC power devices.

Semiconductor

E critical

εr

μn

BFOM

BHFFOM

Si

1

1

1

1

1

GaN

19

0.9

0.9

5300

320

4H-SiC

13

0.9

0.9

1500

140

Figure 2.19 Material properties and calculated BFOM and BHFFOM.

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36

Vertical GaN and SiC Power Devices

References [1] Maruska, H. P., and J. J. Tietjen, “The Preparation and Properties of Vapor-Deposited Single-Crystalline GaN,” Applied Physics Letters, Vol. 15, No. 10, 1969, pp. 327–329. [2] Trew, R. J., J.-B. Yan, and P. M. Mock, “The Potential of Diamond and SiC Electronic Devices for Microwave and Millimeter-Wave Power Applications,” Proceedings of the IEEE, Vol. 79, No. 5, 1991, pp. 598–620. [3] Amano, H., et al., “Metalorganic Vapor Phase Epitaxial Growth of a High Quality GaN Film Using an AlN Buffer Layer,” Applied Physics Letters, Vol. 48, No. 5, 1986, pp. 353–355. [4] Akasaki, I., et al., “Effects of AlN Buffer Layer on Crystallographic Structure and on Electrical and Optical Properties of GaN and Ga1-xAlxN (0 < x ≤ 0.4) Films Grown on Sapphire Substrate by MOVPE,” Journal of Crystal Growth, Vol. 98, 1989, pp. 209–219. [5] Amano, H., et al., “Electron Beam Effects on Blue Luminescence of ZincDoped GaN,” Journal of Luminescence, Vol. 40–41, 1988, pp. 121–122. [6] Nakamura, S., T. Mukai, and M. Senoh, “High-Power GaN p-n Junction BlueLight-Emitting Diodes,” Japanese Journal of Applied Physics, Vol. 30, No. 12A, 1991, pp. L1998–L2001. [7] Khan, M. A., et al., “High Electron Mobility Transistor Based on a GaNAlxGa1-xN Heterojunction,” Applied Physics Letters, Vol. 63, No. 9, 1993, pp. 1214–1215. [8] Pearton, S. J., C. R. Abernathy, and F. Ren, Gallium Nitride Processing for Electronics, Sensors, and Spintronics, London: Springer, 2006, p. 6. [9] Kelly, M. K., et al., “Large Freestanding GaN Substrates by Hydride Vapor Phase Epitaxy and Laser-Induced Liftoff,” Japanese Journal of Applied Physics, Vol. 38, No. 3A, 1999, pp. L217–L219. [10] Johnson, J. W., et al., “Breakdown Voltage and Reverse Recovery Characteristics of Freestanding GaN Schottky Rectifiers,” IEEE Transactions on Electron Devices, Vol. 49, No. 1, 2002, pp. 32–36. [11] Suda, J., and M. Horita, “Characterization of n-Type and p-Type GaN Layers Grown on Freestanding GaN Substrates,” Compound Semiconductor Week, Toyama, Japan, June 26–30, 2016, paper WeB1-1. [12] Tairov, Y. M., and V. F. Tsvetkov, “Investigation of Growth Processes of Ingots of Silicon Carbide Single Crystals,” Journal of Crystal Growth, Vol. 43, 1978, pp. 209–212. [13] Scace, R. I., and G. A. Slack, “Solubility of Carbon in Silicon and Germanium,” Journal of Chemical Physics, Vol. 30, No. 6, 1959, pp. 1551–1555. [14] Wesch, W., “Silicon Carbide: Synthsis and Processing,” Nuclear Instruments and Methods in Physics Research B, Vol. 116, 1996, pp. 305–321. [15] Kuroda, N., et al., “Step-Controlled VPE Growth of SiC Single Crystals at Low Temperatures,” Solid State Devices and Materials, Tokyo, Aug. 25–27, 1987, pp. 227–230.

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Summary

37

[16] Matsunami, H., “Technological Breakthroughs in Growth Control of Silicon Carbide for High Power Electronic Devices,” Japanese Journal of Applied Physics, Vol. 43, No. 10, 2004, pp. 6835–6847. [17] Ben-Yaacov, I., et al., “AlGaN/GaN Current Aperture Vertical Electron Transistors with Regrown Channels,” Journal of Applied Physics, Vol. 95, No. 4, 2004, pp. 2073–2078. [18] Kanechika, M., et al., “A Vertical Insulated Gate AlGaN/GaN Hetrojunction field Effect Transistor,” Japanese Journal of Applied Physics, Vol. 46, No. 21, 2007, pp. L503–L505. [19] Shibata, D., et al., “1.7 kV/1.0 mΩcm2 Normally-Off Vertical GaN Transistor on GaN Substrate with Regrown p-GaN/AlGaN/GaN Semipolar Gate Structure,” International Electron Devices Meeting, San Francisco, Dec. 5–7, 2016, pp. 10.1.1–10.1.4. [20] Ueno, M., et al., “X-Ray Observation of the Structural Phase Transition of Aluminum Nitride Under High Pressure,” Physical Review B, Vol. 45, No. 1, 1992, pp. 10123–10126. [21] Ueno, M., et al., “Stability of the Wurtzite-Type Under High Pressure: GaN and InN,” Physical Review B, Vol. 49, No. 17, 1994, pp. 14–21. [22] Yeh, C.-Y., et al., “Zinc-Blende–Wurtzite Polytypism in Semiconductors,” Physical Review B, Vol. 46, No. 16, 1992, pp. 10086–10097. [23] Frank, F. C., “On Miller-Bravais Indices and Four-Dimensional Vectors,” Acta Crystallographica, Vol. 18, 1965, pp. 862–866. [24] Li, X., et al., “Properties of GaN Layers Grown on N-Face Freestanding GaN Substrates,” Journal of Crystal Growth, Vol. 413, 2015, pp. 81–85. [25] Kojima, K., et al., “Low-Resistivity m-Plane Freestanding GaN Substrate with Very Low Point-Defect Concentrations Grown by Hydride Vapor Phase Epitaxy on a GaN Seed Crystal Synthesized by the Ammonothermal Method,” Applied Physics Express, Vol. 8, 2015, pp. 095501-1–095501-4. [26] Wu, Y.-H., et al., “Freestanding a-Plane GaN Substrates Grown by HVPE,” SPIE Proceedings, Vol. 8262, 2012, pp. 82621Z-1–82621Z-5. [27] Yazdi, G. R., et al., “Freestanding AlN Single Crystals Enabled by Self-Organization of 2H-SiC Pyramids on 4H-SiC Substrates,” Applied Physics Letters, Vol. 94, No. 8, 2009, pp. 082109-1–082109-3. [28] Satoh, I., et al., “Development of Aluminum Nitride Single-Crystal Substrates,” SEI Technical Review, Vol. 71, 2010, pp. 78–82. [29] Novikov, S. V., et al., “Molecular Beam Epitaxy of Freestanding Bulk Wurtzite AlxGa1-xN layers Using a Highly Efficient RF Plasma Source,” Physica Status Solidi C, Vol. 13, No. 5–6, 2016, pp. 217–220. [30] Yoo, W. S., and H. Matsunami, “Solid-State Phase Transformation in Cubic Silicon Carbide,” Japanese Journal of Applied Physics, Vol. 30, No. 3, 1991, pp. 545–553. [31] Kittel, C., Introduction to Solid State Physics (Eighth Edition), New Jersey: John Wiley & Sons, 2005, p.188 and pp. 585–586.

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[32] Bockstedte, M., et al., “Ab Initio Study of the Migration of Intrinsic Defects in 3C-SiC,” Physical Review B, Vol. 68, No. 20, 2003, pp. 205201-1–205201-17. [33] Bracht, H., “Self- and Foreign-Atom Diffusion in Semiconductor Isotope Heterostructures. I. Continuum Theoretical Calculations,” Physical Review B, Vol. 75, No. 3, 2007, pp. 035210-1–035210-3. [34] https://www.silvaco.com/products/tcad/process_simulation/process_simulation.html. [35] Tokuda, Y., et al., “DLTS Study of n-Type GaN Grown by MOCVD on GaN Substrates,” Superlattices and Microstructures, Vol. 40, 2006, pp. 268–273. [36] Dalibor, T., et al., “Deep Defect Centers in Silicon Carbide Monitored with Deep Level Transient Spectroscopy,” Physica Status Solidi A, Vol. 162, No. 1, 1997, pp. 199–225. [37] Hemmingsson, C., et al., “Deep Level Defects in Electron-Irradiated 4H-SiC Epitaxial Layers,” Journal of Applied Physics, Vol. 81, No. 9, 2007, pp. 6155–6159. [38] Kimoto, T., and J. A. Cooper, Fundamentals of Silicon Carbide Technology, Singapore: John Wiley & Sons, 2014, pp. 161–172. [39] Evoy, S., et al., “Scanning Tunneling Microscope-Induced Luminescence of GaN at Threading Dislocations,” Journal of Vacuum Science and Technology B, Vol. 17, No. 1, 1999, pp. 29–32. [40] Northrop, J. E., “Theory of ( 12 10 ) Prismatic Stacking Fault in GaN,” Applied Physics Letters, Vol. 72, No. 18, 1998, pp. 2316–2318. [41] Stampfl, C., and C. G. Van de Walle, “Energetics and Electronic Structure of Stacking Faults in AlN, GaN, and InN,” Physical Review B, Vol. 57, No. 24, 1998, pp. R15052–R15055. [42] Hong, M. H., et al., “Stacking Fault Energy of 6H-SiC and 4H-SiC Single Crystals,” Phylosophical Magazine A, Vol. 80, No. 4, 2000, pp. 919–935. [43] Daudin, B., J. L. Rouviere, and M. Arlery, “Polarity Determination of GaN Films by Ion Channeling and Convergent Beam Electron Diffraction,” Applied Physics Letters, Vol. 69, No. 17, 1996, pp. 2480–2482. [44] Beach, R. A., and T. C. McGill, “Piezoelectric Fields in Nitride Devices,” Journal of Vacuum Science and Technology B, Vol. 17, No. 4, 1999, pp. 1753–1756. [45] Kamata, T., et al., “Structural Transformation of Screw Dislocations via Thick 4H-SiC Epitaxial Growth,” Japanese Journal of Applied Physics, Vol. 39, No. 12A, 2000, pp. 6496–6500. [46] Kamata, T., et al., “Influence of 4H-SiC Growth Conditions on Micropipes Dissociation,” Japanese Journal of Applied Physics, Vol. 41, No. 10B, 2002, pp. L1137–L1139. [47] Perry, P. B., and R. F. Rutz, “The optical Absorption Edge of Single-Crystal AlN Prepared by a Close-Spaced Vapor Process,” Applied Physics Letters, Vol. 33, No. 4, 1978, pp. 319–321. [48] Muth, J. F., et al., “Absorption Coefficient, Energy Gap, Exciton Binding Energy, and Recombination Lifetime of GaN Obtained from Transmission Measurements,” Applied Physics Letters, Vol. 71, No. 18, 1997, pp. 2572–2574.

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2.8

Summary

39

[49] Sridhara, S. G., et al., “Absorption Coefficient of 4H Silicon Carbide from 3900 to 3250 Angstrom,” Journal of Applied Physics, Vol. 84, No. 5, 1998, pp. 2963–2964. [50] Monemar, B., et al., “Recombination of Free and Bound Excitons in GaN,” Physica Status Solidi B, Vol. 245, No. 9, 2008, pp. 1723–1740. [51] Bougrov, V., et al., in Properties of Advanced Semiconductor Materials GaN, AlN, InN, BN, SiC, SiGe (eds. Levinshtein, M. E., Rumyantsev, S. L., and Shur, M. S.), New York: John Wiley & Sons, 2001, pp. 1–30. [52] http://www.ioffe.ru/SVA/NSM/Semicond/GaN/bandstr.html. [53] http://www.ioffe.ru/SVA/NSM/Semicond/SiC/bandstr.html. [54] Choyke, W. J., and G. Pensl, “Physical Properties of SiC,” MRS Bulletin, Vol. 22, No. 3, 1997, pp. 25–29. [55] Horita, M., et al., “Hall-Effect Measurements of Metalorganic Vapor-Phase Epitaxy-Grown p-Type Homoepitaxial GaN Layers with Various Mg Concentrations,” Japanese Journal of Applied Physics, Vol. 56, 2017, pp. 031001-1-031001-4. [56] Heera, V., D. Panknin, and W. Skorupa, “P-Type Doping of SiC by High Dose Al Implantation−Problems and Progress,” Applied Surface Science, Vol. 184, No. 1−4, 2001, pp. 307–316. [57] Sze, S. M., and K. K. Ng, Physics of Semiconductor Devices (Third Edition), New Jersey: John Wiley & Sons, 2007, pp. 17–27. [58] Kyle, E. C. H., et al., “High-Electron-Mobility GaN Grown on Freestanding GaN Templates by Ammonia-Based Molecular Beam Epitaxy,” Journal of Applied Physics, Vol. 115, 2014, pp. 193702-1–193702-12. [59] Kagamihara, S., et al., “Parameters Required to Simulate Electric Characteristics,” Journal of Applied Physics, Vol. 96, No. 10, 2004, pp. 5601–5606. [60] Matsuura, H., et al., “Dependence of Acceptor Levels and Hole Mobility on Acceptor Density and Temperature in Al-Doped p-Type 4H-SiC Epilayers,” Journal of Applied Physics, Vol. 96, No. 5, 2004, pp. 2708–2715. [61] http://www.iue.tuwien.ac.at/phd/ayalew/node21.html. [62] Baliga, B. J., “Gallium Nitride Devices for Power Electric Applications,” Semiconductor Science and Technology, Vol. 28, 2013, pp. 1–8. [63] Konstantinov, A. O., et al., “Ionization Rates and Critical Fields in 4H Silicon Carbide,” Applied Physics Letters, Vol. 71, No. 1, 1997, pp. 90–92. [64] Raghunathan, R., and B. J. Baliga, “Temperature Dependence of Hole Impact Ionization Coefficients in 4H and 6H SiC,” Solid State Electronics, Vol. 43, No. 2, 1999, pp. 199–211. [65] Hatakeyama, T., et al., “Impact Ionization Coefficients of 4H Silicon Carbide,” Applied Physics Letters, Vol. 85, No. 8, 2004, pp. 1380–1382. [66] Loh, W. S., et al., “Impact Ionization Coefficients in 4H-SiC,” IEEE Transactions on Electron Devices, Vol. 55, No. 8, 2008, pp. 1984–1990. [67] Green, J. E., et al., “Impact Ionization Coefficients in 4H-SiC by Ultralow Excess Noise Measurements,” IEEE Transactions on Electron Devices, Vol. 59, No. 4, 2012, pp. 1030–1036.

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[68] Niwa, H., J. Suda, and T. Kimoto, “Impact Ionization Coefficients in 4H-SiC Toward Ultrahigh-Voltage Power Devices,” IEEE Transactions on Electron Devices, Vol. 62, No. 10, 2015, pp. 3326–3333. [69] Ozbek, A. M., and B. J. Baliga, “Planar Nearly Ideal Edge-Termination Technique for GaN Devices,” IEEE Electron Device Letters, Vol. 32, No. 3, 2011, pp. 300–302. [70] Baliga, B. J., “Semiconductors for High-Voltage, Vertical Channel FETs,” Journal of Applied Physics, Vol. 53, No. 3, 1982, pp. 1759–1764. [71] Baliga, B. J., “Power Semiconductor Device Figure of Merit for High-Frequency Applications,” IEEE Electron Device Letters, Vol. 10, No. 10, 1989, pp. 455–457. [72] Barker, Jr., A. S., and M. Ilegems, “Infrared Lattice Vibrations and Free-Electron Dispersion in GaN,” Physical Review B, Vol. 7, No. 2, 1973, pp. 743–750. [73] Patrick, L., and W. J. Choyke, “Static Dielectric Constant of SiC,” Physical Review B, Vol. 2, No. 6, 1970, pp. 2255–2256. [74] http://www.ioffe.ru/SVA/NSM/Semicond/Si/basic.html. [75] Baliga, B. J., Fundamentals of Power Semiconductor Devices, New York: Springer Science, 2008, p. 16.

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CHAPTER

3 Contents

p-n Junctions

3.1 Introduction 3.2 Diffusion 3.3 Continuity Equations 3.4 Carrier Recombination Lifetime 3.5 Depletion-Region Width of OneDimensional p+n Abrupt Junction 3.6 One-Dimensional Forward-Current/Voltage Characteristics 3.7 Multidimensional Forward-Current/Voltage Characteristics 3.8 Junction Breakdown 3.9 Summary

3.1

Introduction

To understand not only bipolar power devices (Chapter 10) but also edge terminations (Chapter 11), p-n junctions are of great importance. This chapter begins by introducing equations for the diffusion current. Subsequently, the chapter derives continuity equations and compares the carrier recombination lifetimes of GaN, 4H-SiC, and silicon. The basic theory of current/voltage characteristics developed by Shockley [1] is then explained. In addition, the chapter discusses the multidimensional effect on current/voltage characteristics of a non-selfaligned mesa-type p-n junction. GaN and 4H-SiC power devices are often made from n-type starting material because their electron mobilities are higher than their hole mobilities (see Section 2.5). Therefore, this chapter mainly considers n-type GaN and 4H-SiC, as well as their junctions with heavily doped p-type (p+) GaN and 4H-SiC.

41

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3.2

Diffusion

When carrier concentration has a gradient, the carriers migrate from the high-concentration region to the low-concentration region by a process called diffusion. One-dimensional diffusion-current densities for electrons and holes are expressed, respectively, by Fick’s law [2] as Jn_diffusion = qDn(∂n/∂x)

(3.1a)

Jp_diffusion = −qDp(∂p/∂x),

(3.1b)

and

where Dn and Dp are diffusivity of electrons and holes, respectively. In an ntype semiconductor that is neither heavily doped (i.e., nondegenerate) nor under an external applied field, drift-current density of electrons (given by [2.16] as qnμnE) balances Jn_diffusion as follows: qnμnE + qDn(∂n/∂x) = 0

(3.2)

Under the thermal equilibrium condition, the Fermi level EF must be constant. Therefore, the partial derivative of electron concentration n = NC exp[−(EC−EF)/kT] (see [2.12a]) with respect to x becomes ∂n/∂x = −(NC/kT) (∂EC/∂x) exp[−(EC−EF)/kT]

(3.3)

Since qE = ∂EC/∂x

(3.4)

(3.3) becomes ∂n/∂x = −qEn/kT

(3.5)

Combining (3.2) and (3.5) gives the following Einstein relation for an n-type semiconductor Dn = (kT/q) μn

(3.6a)

Similarly, for a nondegenerate p-type semiconductor, the Einstein relation becomes Dp = (kT/q) μp

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(3.6b)

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3.3

3.3

Continuity Equations

43

Continuity Equations

An infinitesimal slice of a crystal (thickness: dx; cross-sectional area: A) located at x is treated one-dimensionally (Figure 3.1). The number of electrons flowing into the slice and flowing out of the slice are, respectively, Jn(x)/(−q) and Jn(x+dx)/(−q). When the generation and recombination rates per unit volume for electrons are represented, respectively, by Gn and Rn, the rate of change in the number of electrons in the slice is given by (∂n/∂t)Adx = [Jn(x)/(−q)−Jn(x + dx)/(−q)]A + (Gn− Rn)A dx

(3.7)

Expanding the second term on the right-hand side in a Taylor series gives the following continuity equation: ∂n/∂t = (1/q)(∂Jn(x)/∂x) + (Gn−Rn)

(3.8a)

For holes, the continuity equation (3.8b) is similarly obtained; as suggested the sign of (−q) on the right-hand side of (3.8a) is switched. ∂p/∂t = (−1/q) (∂Jp(x)/∂x) + (Gp−Rp)

(3.8b)

According to (2.16) (namely, Jdrift = q(nµn+pµp)E), electron and hole drift-current densities are given as Jn_drift = qnμnE

(3.9a)

Jp_drift = qpμpE

(3.9b)

and

Gn : generation rate

J n (x) −q

R n : recombination rate

x

J n (x + dx) −q

x + dx

Figure 3.1 Increase in electron concentration in an infinitesimal slice (thickness: dx; cross-sectional area: A) related to net flow of electrons into the slice and excess of generation over recombination.

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Combining (3.9a, b) with (3.1a, b), respectively, gives the following equations of total current densities of electrons and holes: Jn = qnμnE + qDn(∂n/∂x)

(3.10a)

Jp = qpμpE − qDp(∂p/∂x)

(3.10b)

and

Inserting (3.10a, b), respectively, into (3.8a, b) and assuming that mobilities and diffusivities are independent of x gives the final form of continuity equations for electrons and holes, respectively, as ∂n/∂t = μnn(x)(∂E/∂x) + μnE(x)(∂n/∂x) + Dn∂2n/∂x2 + (Gn − Rn) (3.11a) and ∂p/∂t = −μpp(x)(∂E/∂x) −μpE(x)(∂p/∂x) + Dp∂2p/∂x2 + (Gp − Rp). (3.11b)

3.4

Carrier Recombination Lifetime

An external stimulus, such as photonic or thermal energy, creates excess carriers. When the external stimulus is removed, the excess carrier concentration decays to the equilibrium value mainly through (1) bandto-band (Figure 3.2[a]) (2) Shockley-Read-Hall (SRH) (Figure 3.2[b]), and (3) Auger (Figure 3.2[c]) recombination processes. 3.4.1

Band-to-Band Recombination Lifetime

The band-to-band recombination rate Rband-to-band is proportional to electron and hole concentrations, namely Rband-to-band = Bnp,

(3.12)

where B is the band-to-band recombination coefficient (i.e., 1.2 × 10−11 cm3/s for GaN [3], 1.5 × 10−12 cm3/s for 4H-SiC [4], and 4.7 × 10−15 cm3/s for Si [5]). The relatively large B for GaN is attributed to the direct bandgap (see Section 2.3). Note that even among the indirect semiconductors, B for

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3.4

Carrier Recombination Lifetime

45

EC

EC

Photon emission

Photon emission

Photon emission

photon absorption

photon absorption

EV

EV (a)

EC

Et EC

EC

EV

EV

EV (b)

(c)

Figure 3.2 Schematic illustration of (a) band-to-band recombination, (b) Shockley-ReadHall recombination, and (c) Auger recombination. Band-to-band recombination with reabsorption of recombination radiation (i.e., photon recycling) is also shown in (a).

4H-SiC is more than 300 times larger than B for Si. This considerable difference in B is quantitatively discussed in Section 3.4.4. Band-to-band recombination plays an important role in determining carrier lifetimes under high-level injection (i.e., when excess-carrier concentration p [= n, due to charge neutrality] is larger than the majoritycarrier concentration). Electron and hole concentrations in an n-type semiconductor under high-level injection are given, respectively, as nn = ND+ p ≈ p

(3.13a)

pn = pno+ p ≈ p

(3.13b)

and

where pno is hole concentration under thermal equilibrium.

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Rband-to-band in an n-type semiconductor under high-level injection is thus given as Rband-to-band_p = BΔp2 ≡ Δp/τband-to-band_p

(3.14a)

where the band-to-band recombination lifetime under high-level injection is τband-to-band_p = 1/(BΔp)

(3.14b)

As described in Section 2.3, the optical-absorption coefficient of GaN is much larger than that of 4H-SiC. In the case of GaN, radiative recombination is therefore often reabsorbed (i.e., photon recycling) (Figure 3.2[a]), effectively increasing τband-to-band_p, namely, decreasing B. Photon recycling is described in detail in Chapter 4. 3.4.2

SRH Recombination Lifetime

In any semiconductor, localized states in an energy gap (Figure 3.2[b]), due to such factors as point defects (Section 2.2.3) and impurity atoms, are practically present. According to analyses by Shockley and Read [6] and Hall [7], the recombination rate USRH in the steady state via a single deep-level recombination center is given as USRH = σnσpvthNt(np−ni2)/[σn(n + n1) + σp(p + p1)] = (np − ni2)/[(n + n1)/(σpvthNt) + (p + p1)/(σnvthNt)]

(3.15)

where σn and σp are, respectively, capture cross-sections for electrons and holes, vth is thermal velocity, Nt is trap concentration, and n1 and p1 are, respectively, equilibrium electron and hole concentrations when EF coincides with trap level Et. Namely, n1 = ni exp[(Et−Ei)/kT]

(3.16a)

p1 = ni exp[(Ei−Et)/kT],

(3.16b)

and

where Ei is the intrinsic Fermi level (i.e., the mid-gap level). Since the minority-carrier lifetimes in heavily doped p-type and n-type semiconductors are respectively defined as

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3.4

Carrier Recombination Lifetime

47

τp0 = 1/(σpvthNt)

(3.17a)

τn0 = 1/(σnvthNt),

(3.17b)

and

(3.15) can be expressed as USRH = (np−ni2)/[τp0(n+n1)+τn0(p+p1)]

(3.18)

The dependence of USRH on Et in (3.18) can be expressed by assuming σn = σp ≡ σ0 and τn0 = τp0 ≡ τ0 as follows: USRH = (np−ni2)/{n+p+2ni cosh[(Et−Ei)/kT]τ0}

(3.19)

Here, it is considered that an n-type semiconductor with no current flow is disturbed by creation of equal numbers of excess electrons and holes. If low-level injection is considered, Δn and Δp are much less than (n0+p0), where n0 and p0 denote, respectively, thermal-equilibrium electron and hole concentrations. The continuity equation for excess holes (3.11b) becomes ∂Δp/∂t = Gp−Rp = −USRH = [−(n0 + p0)Δp]/{n0 + p0 + 2ni cosh[(Et − Ei)/kT]τ0}

(3.20)

For recombination centers around the mid-gap level, (Et − Ei) becomes negligibly small, so (3.20) can be expressed as ∂Δp/∂t ≡ −Δp/τSRH_p

(3.21a)

τSRH_p = τ0 = τp0 = 1/(σpvthNt)

(3.21b)

and

Equation (3.21b) indicates that the SRH lifetime of holes in an n-type semiconductor (τSRH_p) is independent of majority-carrier concentration ND under low-level injection. 3.4.3

Auger Recombination Lifetime

When excess carriers recombine in a region with a large dopant concentration, the probability of direct recombination between electrons

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Vertical GaN and SiC Power Devices

and holes (Figure 3.2[c]) may not be neglected. In such a recombination process (called Auger recombination), three free carriers interact; namely, either two electrons and a hole or two holes and an electron (Figure 3.2[c]). The Auger recombination rate UA is given as UA = Cnn(np−ni2)+Cpp(np−ni2)

(3.22)

where Cn and Cp are coefficients for interactions in which the remaining carrier is an electron or a hole, respectively. In the case of Auger recombination in an n-type semiconductor, if Cn ≈ Cp, the second term on the righthand side of (3.22) is smaller than the first term on the right-hand side of (3.22). The Auger-recombination lifetime of excess holes Δp is thus given as τA_p = Δp/UA ≈ 1/(CnND2)

(3.23)

Reported Cn values are about the same for GaN (4.5 × 10−31 cm6/s [8]), 4H-SiC (5.0 × 10−31 cm6/s for [9]), and Si (2.8 × 10−31 cm6/s [10]). 3.4.4

Overall Expression for Carrier Recombination Lifetime

If the dependence of τSRH_p on Δp is neglected, an overall expression for the recombination lifetime of holes in an n-type semiconductor is given as τp = 1/[(1/τband-to-band_p)+(1/τSRH_p)+(1/τA_p)]

(3.24)

The values of B and Cn described in Sections 3.4.1 and 3.4.3 are used to calculate τp, which was calculated as a function of Δp when ND = 1 × 1014 cm−3 (Figure 3.3). In the case of silicon, Auger recombination limits τp under high-level injection when τSRH_p exceeds 10 μs (Figure 3.3[a]). In the case of 4H-SiC, on the other hand, band-to-band recombination limits τπ under high-level injection when τSRH_p exceeds 1 μs (Figure 3.3[b]). The latter result is mainly due to the relatively large B for 4H-SiC. In the case of GaN, if the effect of photon recycling is not present, τp reduces to about 10% of τp for 4H-SiC at a fixed excess-carrier concentration. This is because band-to-band recombination limits τp even when τSRH_p is 100 ns (Figure 3.3[c]). However, the dependence of τp on excess-carrier concentration for GaN under the effect of photon recycling is comparable to that for 4H-SiC for the following reason. For example, in the case of AlGaAs/GaAs heterostructures, photon recycling factor Φ (i.e., effective band-to-band recombination lifetime τband-to-bandeff divided by τband-to-band_p) of 4−6 was reported [11]. In Figure 3.3(d), Φ of 8 is assumed simply because τband-to-bandeff for GaN becomes equal to τband-to-band_p for 4H-SiC. Since Cn for

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3.4

Carrier Recombination Lifetime

Carrier lifetime (s)

10 −2 10 −3 10 −4

Carrier lifetime (s)

10 −5 s 10 −6 s

10 −7

10 −7 s

10 −8 10 −9 10 15

10 −8 s 10 16

10 −6

10 −4 s 10 −5 s 10 −6 s

10 −7

10 −7 s

10 −8 10 −9

10 −8 s 10 15

Carrier lifetime (s)

10 −4 10 −5

10 16

(c) GaN without photon recycling

10 −5 s 10 −6 s

10 −7

10 −7 s

10 −8 10 −9

10 −8 s 10 15

Carrier lifetime (s)

10 −3 10 −4 10 −5

10 17

10 18

10 17

10 18

TAuger

Tband-to-band

10 −4 s

10 −6

10 −2

10 18

T band-to-band

10 −5

10 −3

10 17 TAuger

(b) 4H-SiC

−3 10 −4 10 s

10 −2

Tband-to-band

10 −4 s

10 −6

10 −3

TAuger

(a) Si TSRH = 10−3 s

10 −5

10 −2

49

10 16

(d) GaN with photon Tband-to-band recycling 10 −3 s 10 −4 s 10 −5 s

10 −6

10 −6 s

10 −7

10 −7 s

10 −8 10 −9 10 15

10 −8 s 10 16

TAuger

10 17

10 18 3

- ) Excess carrier concentration (cm

Figure 3.3 Calculated recombination lifetime in the case of n-type (a) silicon, (b) 4H-SiC, (c) GaN without photon recycling, and (d) GaN with photon recycling (photon recycling factor: 8) as a function of excess-carrier concentration. Band-to-band and Auger recombination coefficients used are, respectively, 4.7 × 10−15 cm3/s and 2.8 × 10−31 cm6/s for silicon, 1.5 × 10−12 cm3/s and 5.0 × 10−31 cm6/s for 4H-SiC, and 1.2 × 10−11 cm3/s and 4.5 × 10−31 cm6/s for GaN.

GaN is about the same as that for 4H-SiC (see Section 3.4.3), the dependences of τp on excess-carrier concentration are similar in the case of GaN and 4H-SiC.

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3.5 Depletion-Region Width of One-Dimensional p+n Abrupt Junction The following depletion approximation, which assumes box-profile depleted charges with width WDp in the p+region and WDn in the n-region, is used for simple analysis (Figure 3.4[a]). Since the electric field in the neutral regions is almost zero, the following equation must be satisfied: NAWDp = NDWDn

(3.25)

Since the Poisson equation is expressed as ∂E/∂x = −qNA/εrεo for − WDp ≤ x ≤ 0

(3.26a)

∂E/∂x = qND/εrεo for 0 ≤ x ≤ WDn

(3.26b)

and

the electric field is obtained by integrating (3.26a, b) as follows: E(x) = −qNA(x+WDp)/εrεo for − WDp ≤ x ≤ 0

(3.27a)

E(x) = −Emax+qNDx/εrεo = −qND(WDn−x)/εrεo for 0 ≤ x ≤ WDn

(3.27b)

and

where Emax is the maximum electric field (Figure 3.4[b]) expressed as Emax = qNAWDp/εrεo = qNDWDn/εrεo

(3.28)

As shown in Figure 3.4(b, c), the total depletion-region width WD and built-in potential Ψbi can be approximated, respectively, by WDn and Ψn because WDp and Ψp are much smaller than WDn and Ψn in the case of a p+n abrupt junction. Integrating (3.27b) gives Ψbi as Ψbi ≈ qNDWDn2/2εrεo

(3.29)

From (3.29), WD of a one-dimensional p+n abrupt junction is expressed as WD ≈ (2εrεoΨbi/qND)0.5

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(3.30)

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3.5

Depletion-Region Width of One-Dimensional p+n Abrupt Junction

p+region

51

n-region

Neutral region

Depletion region

q ND −WDp + + + + + + + + + + + − O WDn − − − − − − − − − − −q NA

Neutral region

x

(a) E WD

−WDp

WDn

x

O

−E max (b)

−q?ψn

q ψbi

EC EF

q ψp

(c)

EV

Figure 3.4 Abrupt p+n junction under thermal equilibrium: (a) space-charge distribution under depletion approximation, (b) electric-field distribution, and (c) energy-band diagram.

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3.6 One-Dimensional Forward-Current/Voltage Characteristics A one-dimensional p+n junction is considered to be connected to a voltage source with the n-region grounded and the p+region at V volts relative to ground. The junction is assumed to be not illuminated, so carrier concentration is only influenced by V. Furthermore, ohmic drops are assumed to be neglected, so V is sustained entirely at the junction; that is, total junction voltage is Ψbi−V. 3.6.1

Low-Level Injection Condition

Electron concentration at the quasi-neutral boundary in the n-region next to the p+n junction (i.e., x = WDn ≈ WD) can be assumed to be equal to ND regardless of whether the junction is at equilibrium or under bias. Here, WD under bias is given by (3.30) by replacing Ψbi with Ψbi–V to give WD ≈ [2εrεo(Ψbi−V)/qND]0.5

(3.31)

If hole concentration in the p+region under thermal equilibrium is denoted as pp0, p(WD) under low-level injection is approximated by p(WD) ≈ pp0 exp[−q(Ψbi−V)/kT]= (ni2/ND+) exp(qV/ kT)

3.6.1.1

(3.32)

Diffusion Current

The continuity equation (3.11b) for the neutral n-region under steady state is given as 0 = Dp∂2Δp/∂x2−Δp(x)/τSRH_p

(3.33)

Equation (3.33) has the simple exponential solution Δp(x) = A exp[−(x−WD)/(DpτSRH_p)0.5] +B exp[(x−WD)/(Dp τSRH_p)0.5]

(3.34)

where constants A and B are determined by boundary conditions. If neutral n-region width is much larger than diffusion length Lp ≡ (Dp τSRH_p)0.5, Lp represents the average distance traveled in the neutral n-region before a hole injected from the p+region recombines. Since Δp(x) must decrease with increasing x, B in (3.34) must be zero. By combining (3.32) and (3.34), it follows that

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3.6

One-Dimensional Forward-Current/Voltage Characteristics

Δp(x) = (ni2/ND+) [exp(qV/kT)−1] exp[−(x−WD)/Lp]

53

(3.35)

Since hole current flows only by diffusion at x = WD (Figure 3.5[a]), total current density flowing through the p+n junction is given as J total = Jp(x) |x =WD = −qDp ∂Δp / ∂x |x =WD = J SLL [ exp(qV / kT) − 1]

(3.36a)

JSLL = qDpni2/(ND+Lp)

(3.36b)

and

In the case that NA− in the p+region is decreased (Figure 3.5[b]), Jtotal can be expressed as the sum of Jp_diffusion(WDn) and Jn_diffusion(−WDp). By combining (3.35) and (3.36a, b), Jtotal can be expressed as Jtotal = qni2 [Dp/(ND+Lp)+Dn/(NA-Ln)] [exp(qV/kT)−1]

(3.37)

In the case that the thickness of the p-region (Wp) is less than Ln (Figure 3.5[c]), the expression for Jn_diffusion(−WDp) changes to

(

)

(

)

J n_diffusion −WDp = qni2 Dn / N A − Wp ⎡⎣exp (qV / kT ) − 1⎤⎦

(3.38)

Jtotal therefore becomes Jtotal = qni2 [Dp/(ND+Lp)+Dn/(NA − Wp)] [exp(qV/kT)−1]

(3.39)

When the diode current density is proportional to [exp(qV/nkT)–1], n is called the ideality factor. Equations (3.36a), (3.37), and (3.39) show that the ideal diffusion current under low-level injection has an ideality factor of unity. 3.6.1.2

Space-Charge Recombination Current

In addition to Jtotal expressed by (3.36a), (3.37), and (3.39), space-charge recombination current density Jrecombination also exits. Jrecombination is also important because it becomes larger than Jtotal when V is small. From the mass-action law and (3.32), it follows that n p = ni2 exp(qV/kT)

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(3.40)

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Vertical GaN and SiC Power Devices

J n_drift

J p_drift

Total current density

J p_diffusion x

0 WD (a)

J n_drift

J p_drift

J n_diffusion

J p_diffusion

Total current density

x

−WDp0 WDn (b)

J n_drift

J n_diffusion

J p_drift

Total current density

J p_diffusion

−Wp −WDp0 WDn (c)

x

Figure 3.5 Current-density components under low-level injection around (a) thick p+n, (b) thick p-n, and (c) thin p-n abrupt junctions.

Inserting (3.40) into (3.19) gives USRH = ni2 [exp(qV/kT)–1]/{n+p+2ni cosh[(Et−Ei)/kT]τ0} ≈ ni2 exp(qV/kT)/{n+p+2ni cosh[(Et−Ei)/kT]τ0}

(3.41)

Since the denominator of (3.41) reaches a minimum when n = p and Et = Ei, maximum USRH is given as USRHmax ≈ (ni/2τ0) exp(qV/2kT)

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(3.42)

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3.6

One-Dimensional Forward-Current/Voltage Characteristics

55

Under the assumption that most of the depletion layer has USRHmax, maximum Jrecombination can be approximated as

Jrecombinationmax ≈ qUSRHmaxWD = JSR exp(qV/2kT)

(3.43a)

and JSR = qWDni/2τ0

(3.43b)

Equation (3.43a) shows that the space-charge recombination current under low-level injection has an ideality factor of two. 3.6.2

High-Level Injection Condition

Even under high-level injection, charge neutrality can be assumed to hold at every point (i.e., ∂Δp(x) ≈ p(x) is equal to ∂Δn(x) ≈ n(x)). Based on (3.32), in the case of WD being larger than the drift-layer thickness 2d, p(2d) ≈ ni exp(qV/2kT)

(3.44)

is obtained. Jtotal then becomes roughly proportional to exp(qV/2kT), showing that the high-level injection current has an ideality factor of two. Its proportional constant is given by [12] JSHL = {2qDaNC0.5NV0.5 tanh(d/La)/La/[1–0.25tanh4(d/La)]0.5} × exp[–(Eg+qVM)/(2kT)]

(3.45)

where VM is the voltage drop across the drift layer, and Da is ambipolar diffusivity defined as Da = 2DnDp/(Dn+Dp)

(3.46)

and La is the ambipolar diffusion length defined as La = (Da τHL)0.5

(3.47)

where τHL is the high-level injection lifetime. 3.6.3

An Example of Measured Current/Voltage Characteristics

On the basis of the equations described in Sections 3.6.1 and 3.6.2, Jtotal is expressed as

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Vertical GaN and SiC Power Devices

Jtotal = JSRexp(qV/2kT)+JSLLexp(qV/kT)+JSHLexp(qV/2kT)

(3.48)

where the effect of series resistance is neglected. An example of the measured current/voltage characteristics of a circular-mesa GaN p+n diode with a diameter of 60 μm [13], together with the three extracted components on the right-hand side of (3.48) is shown in Figure 3.6. The layered structure of the diode consists of p+GaN (NA = 2 × 1019 cm−3 / 0.5 μm), n-GaN (ND = 2 × 1016 cm−3 / 10 μm), and n+GaN (ND = 2 × 1018 cm−3 / 2 μm) on a GaN (0001) freestanding substrate [13]. In this example, space-charge recombination with n = 2 dominates the forward current when V is less than 2.8V. A current component of low-level injection with n = 1 is added in the V range from 2.8 to 2.9V. From 2.9 to 3.0V, on the other hand, the forward current is dominated by a current component of high-level injection with n = 2. The measurement results plotted in Figure 3.6 deviate from the line representing the current component of high-level injection when V is greater than 3.0V. Such deviation has generally been attributed to a series-resistance 10 −2 60-μm φ 300 K High-injectionlevel current (n = 2)

Forward current (A)

10 −3

10 −4

10 −5

10 −6

Space-charge recombination current (n = 2)

Low-injection-level diffusion current (n = 1)

10 −7

10 −8 2.6

2.7

2.8 2.9 Forward voltage (V)

3.0

3.1

Figure 3.6 Example of measured forward current/voltage characteristics of a GaN p+n diode (open circles [13]), together with the extracted current components: space-charge recombination with ideality factor n of two, low-level injection with n = 1, and high-level injection with n = 2.

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3.7

Multidimensional Forward-Current/Voltage Characteristics

57

effect [14]. In that V range, however, a multidimensional effect (described in Section 3.7) has to be taken into account.

3.7 Multidimensional Forward-Current/Voltage Characteristics This section clarifies the multidimensional effects concerning a forwardbiased p+n junction. In the case of Si p+n diodes, a planar structure, where a p+region is formed by ion implantation and diffusion of acceptors, is usually adopted (Figure 3.7[a]). However, a planar structure is not suitable for either GaN or 4H-SiC p+n diodes for the following reasons. Although magnesium can be implanted into GaN [15−17], the activation ratio of magnesium acceptors is very low, which results in a large ideality-factor (i.e., 2.6) and a low forward-current-density (i.e., 1 A/cm2) of p-n diodes [17]. In the case of 4H-SiC, aluminum implantation has been frequently used; however, conductivity modulation has not been fully achieved with the use of ion implantation [18]. The use of ion implantation for active regions is thus avoided in the cases of GaN and 4H-SiC p+n diodes. The p+region of GaN and 4H-SiC p+n diodes is usually made of a p+ epitaxial layer grown on an n-type epitaxial layer (Figure 3.7[b]). (The epitaxial growth is described in detail in Chapter 6.) To define the area of the active region, a mesa structure (Figure 3.7[c]) must therefore inevitably be formed. (Chapter 7 details device processing, including etching.) Fabrication of mesa-type p+n diodes is finished with the formation of cathode and anode electrodes on the backside and top of the p+n diodes, respectively. In such mesa-type p+n diodes, especially small ones, peripheral current due to surface recombination increases. Furthermore, the anode electrode is usually formed with a non-self-aligned process, especially because annealing is required for activating magnesium acceptors in GaN [19, 20]. In such nonself-aligned mesa-type p+n diodes, peripheral current due to electric-filed concentration also increases. 3.7.1 Influence of Surface Recombination on Peripheral Current of p+n Diodes 3.7.1.1

Surface-Recombination Velocity

Section 3.4.2 discusses SRH recombination centers uniformly distributed in the bulk of a semiconductor material. Similarly, at a semiconductor surface, localized states (Est) are located within the energy gap. Instead of the volume density of bulk centers, the area density of surface centers [Nst (cm−2)] is treated here. When σn = σp ≡ σ, (3.15) and (3.16a, b) reduce to

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Vertical GaN and SiC Power Devices

Anode

p type

n type n + type Cathode (a) p type n type n + type Cathode (b)

n type n + type Cathode (c) Anode

p type

n type n + type Cathode (d)

Figure 3.7 Schematic cross-sections of (a) planar and (d) mesa-type p+n diodes: (b) and (c): show fabrication processes of mesa-type p+n diodes.

Us = σ vth Nst (ns ps − ni2) / (ns + n1s + ps + p1s)

(3.49a)

n1s = ni exp [(Est − Ei) / k T]

(3.49b)

p1s = ni exp [(Ei − Est) / k T]

(3.49c)

where ns and ps are, respectively, electron and hole concentrations near the surface. If product np is assumed to be constant throughout the surface space-charge region in an n-type semiconductor, ns ps = ND+ p’

(3.50)

where p’ is hole concentration at the neutral edge of the space-charge region. When Est ≈ Ei, (3.49a) reduces to

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3.7

Multidimensional Forward-Current/Voltage Characteristics

59

Us = σ vth Nst ND+ [p’ – (ni2 / ND+)] / (ns + ps + 2 ni) = s Δ p’

(3.51a)

s = σ vth Nst ND+ / (ns + ps + 2 ni)

(3.51b)

where s is surface-recombination velocity, and Δp’ is excess-hole concentration at the neutral edge of the space-charge region. If the surface is neutral, ND+/ (ns+ps+2ni) is unity, so s can be expressed as s = σvthNst 3.7.1.2

(3.52)

Simulation of the Influence of Surface Recombination

The current/voltage characteristics of the GaN p+n diodes described in Section 3.6.3 were simulated in a cylindrical coordinate system (Figure 3.8) by using a commercial simulator [21]. The over-etched depth of the n-GaN drift layer was assumed to be 0.5 μm, and the simulation parameters used were the same as those reported in [13] and [22]. To identify the location where the surface recombination dominates the measured forward current, one of the following surface-recombination velocities was used as a parameter: s1 on the side surface of p+GaN; s2 on the side surface of n-GaN; or s3 on the surface of etched n-GaN. As shown in Figure 3.9, the measured mesa-diameter dependence of the forward current at 2.7V is well reproduced with s2 = 1 × 108 cm/s. The slope of unity also confirms that the current simulated with s2 is a peripheral current. On the other hand, the dependences Surface recombination velocity s1 s2 s3

p+ GaN (0.52 μm) r

anode 0.5-μm over-etched

300 x

−

n GaN (10 μm) n+ GaN (412 μm) cathode

y

Figure 3.8 Schematic of a simulated GaN p+n diode, including the following three surface-recombination velocities: s1 on the side surface of p+GaN; s2 on the side surface of n-GaN; and s3 on the surface of etched n-GaN.

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Vertical GaN and SiC Power Devices

Forward current at 2.7 V (A)

60

10 −4 273K 10 −5

s 2 = 1× 10 8 cm/s

10 −6 10 −7 10 −8

s 1 = 1× 10 8 cm/s s 3 = 1× 10 8 cm/s

10 −9 10 −10 10 1

10 2 Mesa diameter ( μm)

10 3

Figure 3.9 Measured (open squares [13]) and simulated 2.7-V forward-biased currents of GaN p+n diodes as a function of mesa diameter.

simulated using s1 and s3 show much lower forward current even with a large value of s1 and s3 (i.e., 1 × 108 cm/s). The slope of the two plots indicates that the currents with s1 and s3 are dominated by bulk diffusion current under low-level injection. This result leads to the conclusion that the forward current of a GaN mesa-type p+n diode is dominated by s2, namely, carrier recombination at the side surface of the etched n-GaN. 3.7.2 Influence of Electric-Field Concentration on Non-Self-Aligned Mea-type p+n Diodes Here we analyze another multidimensional effect concerning a highly forward-biased p+n junction. To exclude the influences of deep acceptors in GaN and 4H-SiC (see Section 2.4.2) and surface recombination, a non-selfaligned mesa-type Si p+n diode with an over-etched depth of zero at 300K was numerically investigated (Figure 3.10) [23]. Potential contours of the diode (anode-electrode radius: 30 μm; mesa radius: 35 μm) were simulated in terms of a cylindrical coordinate system by using the commercial simulator [21]. The epitaxial layers consist of 0.5-μm-thick Si (NA: 5 × 1017 cm−3) and 10-μm-thick Si (ND: 2 × 1016 cm−3). As for the Si substrate, a thickness of 500 μm and ND of 5 × 1018 cm-3 were assumed. For both electrons and holes, the same lifetime (10 μs) was used. Simulated potential contours of the non-self-aligned mesa-type Si p+n diode are shown in Figure 3.11. When V is 0.6V, the potential variation in the n-Si layer is only 22 mV (Figure 3.11[a]). Under this bias condition, the n-Si layer is considered to be quasi-neutral, and minority-carrier diffusion dominates Jtotal. As V increases, conductivity modulation gets stronger, and the potential variation in the n-Si layer increases {i.e., 27 mV at 0.8V (Figure 3.11[b]) and 38 mV at 0.9V (Figure 3.11[c])}. Accordingly,

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3.8

Junction Breakdown

Anode electrode

p+Si 17 −3 (5 x 10 cm / 0.5 μm)

61

35 30 n-Si (2 x 1016 cm−3/10 μm)

300 x (μm)

−3

n Si (5 x 10 cm /500 μm) +

18

Cathode electrode y

Figure 3.10 Schematic of simulated non-self-aligned mesa-type Si p+n diode. The overetched depth of the n-Si layer is assumed to be zero.

the n-Si layer is no longer considered to be quasi-neutral, and the driftcurrent component dominates Jtotal. At 0.8V, the potential contours in the n-Si layer terminate at the p-n junction. However, at 0.9V, the potential contours in the n-Si layer extend into the p+Si layer, and potential crowding is observed in the p+Si layer around the edge of the anode electrode (Figure 3.11[c]). This electric-field concentration around the edge of the anode electrode leads to peak Jtotal exceeding 104 A/cm2 (Figure 3.12). Such a considerable increase in Jtotal is considered to be a feature of a non-self-aligned mesa-type p+n junction, and it plays an important role in photon recycling (described in Chapter 4).

3.8

Junction Breakdown

Under a sufficiently high electric field, one of two breakdown processes can occur. In the first one, called avalanche breakdown, free carriers gain enough energy from the field to break covalent bonds in the lattice (see Section 2.6). In the second breakdown process, called Zener breakdown, an electron makes a transition from a valence band to a conduction band without interactions of any other particles (i.e., band-to-band tunneling). Devices exhibiting Zener breakdown have lower breakdown voltage (BV) than those exhibiting avalanche breakdown. In other words, as understood from (3.30) and (3.31), small WD (i.e., large ND) is necessary for band-toband tunneling to occur. In the case of Si p-n junctions, whether avalanche or Zener breakdown occurs can be determined by temperature (T) dependence of BV; that is, with increasing T, BV increases because the mean-free path of electrons decreases (so avalanche breakdown occurs), while BV decreases because

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Vertical GaN and SiC Power Devices

30 μm

5 μm

p+Si (5 × 10 17 cm−3 / 0.5 μm) anode electrode 0.473 V

n-Si (2× 10 16 cm−3 / 10 μm)

0.451 V (a) 0.6-V forward -biased 0.483 V 0.474 V

0.465 V 0.456 V (b) 0.8-V forward -biased 0.515 V 0.510 V 0.504 V 0.499 V 0.493 V 0.488 V 0.477 V

0.482 V (c) 0.9-V forward -biased

Figure 3.11 Simulated potential contours of non-self-aligned mesa-type Si p-n diode forward-biased at (a) 0.6V, (b) 0.8V, and (c) 0.9V.

Figure 3.12 Simulated iso-current-density contours of non-self-aligned mesa-type Si p-n diode forward-biased at 0.9V.

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3.9

Summary

63

the flux of valence-band electrons available for band-to-band tunneling increases (so Zener breakdown occurs). However, this trend is not necessarily true for p-n junctions made of GaN and 4H-SiC having a relatively large density of crystal defects. For example, in the case of 4H-SiC p-n junctions, the reported dependence of BV on T varied from junction to junction [24].

3.9

Summary

This chapter compares carrier recombination lifetimes and current/voltage characteristics of GaN and 4H-SiC p-n junctions with those of a Si p-n junction. Among the multidimensional effects the chapter introduces, electricfield concentration around the edge of a non-self-aligned mesa-type p-n junction is described—to the author’s knowledge, for the first time in semiconductor textbooks. Such electric-field concentration leads to large local current density, which is considered to be the basis for photon recycling to occur in direct-bandgap semiconductors (see Chapter 4).

References [1] Shockley, W., “The Theory of p-n Junctions in Semiconductors and p-n Junction Transistors,” Bell System Technical Journal, Vol. 28, No. 3, 1949, pp. 435–489. [2] Fick, A., “On Liquid Diffusion,” Journal of Membrane Science, Vol. 100, 1995, pp. 33–38. [3] Schenk, H. P. D., et al., “Band Gap Narrowing and Radiative Efficiency of Silicon-Doped GaN,” Journal of Applied Physics, Vol. 103, 2008, pp. 103502-1–103502-5. [4] Goldberg, Y., M. E. Levinshtein, and S. L. Rumyantsev, in Properties of Advanced Semiconductor Materials GaN, AlN, SiC, BN, SiC, SiGe (eds. Levinshtein, M. E., S. L. Rumyantsev, and M. S. Shur), New York: John Wiley & Sons, 2001, pp. 93–148. [5] Trupke, T., et al., “Temperature Dependence of the Radiative Recombination Coefficient of Intrinsic Silicon,” Journal of Applied Physics, Vol. 94, No. 8, 2003, pp. 4930–4937. [6] Shockley, W., and W. T. Read, “Statistics of the Recombination of Holes and Electrons,” Physical Review, Vol. 87, No. 5, 1952, pp. 835–842. [7] Hall, R. N., “Electron-Hole Recombination in Germanium,” Physical Review, Vol. 87, No. 2, 1952, pp. 387–388. [8] Scheibenzuber, W. G., et al., “Recombination Coefficients of GaN-Based Laser Diodes,” Journal of Applied Physics, Vol. 109, 2011, pp. 093106-1–093106-6. [9] Galeckas, A., et al., “Auger Recombination in 4H-SiC: Unusual Temperature Behavior,” Applied Physics Letters, Vol. 71, No. 22, 1997, pp. 3269–3271.

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[10] Schroder, D. K, et al., Semiconductor Material and Device Characterization (Third Edition), New York: Wiley-IEEE, 2006, pp. 392. [11] Ahrenkiel, R. K., et al., “Ultralong Minority-Carrier Lifetime Epitaxial GaAs by Photon Recycling,” Applied Physics Letters, Vol. 55, No. 11, 1989, pp. 1088–1090. [12] Baliga, B. J, Fundamentals of Power Semiconductor Devices, New York: SpringerVerlag, 2008, Chapter 5. [13] Mochizuki, K., et al., “Influence of Surface Recombination on Forward Current−Voltage Characteristics of Mesa GaN p+n Diodes Formed on GaN Freestanding Substrates,” IEEE Transactions on Electron Devices, Vol. 59, No. 4, 2012, pp. 1091–1098. [14] Sze, S. M., and K. K. Ng, Physics of Semiconductor Devices (Third Edition), John New Jersey: Wiley & Sons, 2007, pp. 96–100. [15] Feigelson, B. N., et al., “Multicycle Rapid Thermal Annealing Technique and Its Application for the Electrical Activation of Mg Implanted in GaN,” Journal of Crystal Growth, Vol. 350, 2012, pp. 21–26. [16] Anderson, T. J, et al., “Activation of Mg Implanted in GaN by Multicycle Rapid Thermal Annealing,” Electronics Letters, Vol. 50, No. 3, 2014, pp. 197–198. [17] Anderson, T. J, et al., “Improvements in the Annealing of Ion Implanted IIINitride Materials and Related Materials,” International Conference on Compound Semiconductor Manufacturing Technology, Miami, 2016, pp. 225–228. [18] Kimoto, T., et al., “Promise and Challenges of High-Voltage SiC Bipolar Power Devices,” Energies, Vol. 9, No. 11, 2016, pp. 908-1–908-15. [19] Amano, H., et al., “Electron Beam Effects on Blue Luminescence of ZincDoped GaN,” Journal of Luminescence, Vol. 40–41, 1988, pp. 121–122. [20] Nakamura, S., T. Mukai, and M. Senoh, “High-Power GaN p-n Junction BlueLight-Emitting Diodes,” Japanese Journal of Applied Physics, Vol. 30, No. 12A, 1991, pp. L1998–L2001. [21] http:// www.silvaco.com/products/device_simulation/atlas.html. [22] Mochizuki, K., et al., “Numerical Analysis of Forward Current-Voltage Characteristics of Vertical GaN Schottky-Barrier Diodes and p-n Diodes on Freestanding Substrates,” IEEE Transactions on Electron Devices, Vol. 58, No. 7, 2011, pp. 1979–1985. [23] Mochizuki, K., “Vertical GaN Bipolar Device: Gaining Competitive Advantage from Photon Recycling,” Physica Status Solidi A, Vol. 214, No. 3, 2017, pp. 160048-1–160048-8. [24] Konstantinov, A. O., et al., “Temperature Dependence of Avalanche Breakdown for Epitaxial Diodes in 4H Silicon Carbide,” Applied Physics Letters, Vol. 73, No. 13, 1998, pp. 1850−1852.

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CHAPTER

4 Contents 4.1 Introduction

Effects of Photon Recycling

4.2 Family Tree of Photon-Recycling Phenomena 4.3 Intrinsic Photon Recycling 4.4 Influence of IPR on Forward-Biased GaN p-n Diodes 4.5 Influence of SelfHeating on ForwardBiased GaN p-n Diodes 4.6 Influence of EPR on Forward-Biased GaN p-n Diodes 4.7 Possible Models for EPR 4.8 Summary

4.1

Introduction

It is often said that GaN is not suitable for bipolar power devices because it is a direct-bandgap semiconductor (see Section 2.3) so that it could have a short carrier recombination lifetime (see Section 3.4). For example, in [1], Baliga wrote, “the interest in GaN power devices is limited to unipolar power devices.” In the same textbook, however, he referred to the reported 3.7-kV GaN p-n diodes [2] and wrote, “The diodes exhibited the expected knee voltage of 3.0 volts and an on-state voltage drop of 3.3 volts at a current density of 100 A/cm2. The low on-state voltage drop was observed despite a very low lifetime of 2 ns measured in the drift region.” [3] Although the reason for the low on-state voltage drop is not described in the textbook, it is attributable to the increased carrier recombination lifetime due to photon recycling. Gaining advantage from photon recycling is indispensable for improving the performance of

65

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21

37.5

18

36.0

15

34.5

Vertical GaN p-n diode

33.0

9

31.5

Two-junction non-concentrator solar cell

2

BV /RonA

diff

12

Efficiency (%)

2

(GW/cm )

GaN p-n diodes (see Section 10.3) and GaN bipolar junction transistors (see Section 10.5.4). As described in Sections 2.3 and 3.4, photon recycling is the reabsorption of recombination radiation in direct-bandgap semiconductors such as GaN, GaAs, and AlxGa1-xAs (x < 0.4) [4, 5]. Its effect in indirect-bandgap semiconductors, such as SiC and silicon, is thus considered to be negligible. With respect to AlGaAs-GaAs heterostructures, the influence of photon recycling on radiative-recombination lifetime [6], diffusion length and internal quantum efficiency [7], and minority-carrier lifetime [8] has been investigated; and photon recycling was first utilized in semiconductor devices for reducing the threshold currents of ridge [9] and surface-emitting laser diodes [10] in 1990 and 1991, respectively. In 2011, photon recycling was also utilized for improving performance of GaAs solar cells and vertical GaN p-n diodes; in particular, a conversion efficiency η of 28.2%, beating the previous record of 26.4% [11], and low differential specific onresistance RonAdiff (Section 1.3.2), independent of temperature [12], were achieved. Since then, photon recycling has been applied to multijunction solar cells and GaN p-n diodes with breakdown voltage BV exceeding 3 kV; for example, in 2013, both η of two-junction nonconcentrator solar cells and figure-of-merit BV2/RonAdiff of GaN p-n diodes rapidly deviated from their respective long-term trends [13−22] (Figure 4.1). However, the detailed mechanisms of photon recycling in the case of these solar cells and p-n diodes are considered to be different. This chapter breaks photon

6

30.0

3

28.5

0 1989

1993

1997

2001

2005

2009

2013

27.0 2017

Year Figure 4.1 Conversion efficiency of two-junction nonconcentrator GaAs solar cells and the ratio of the square of breakdown voltage (BV) to differential on-resistance (RonAdiff) of vertical GaN p-n diodes as a function of the year of publication.

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4.2

Family Tree of Photon-Recycling Phenomena

67

recycling into separate types and models these on the basis of experimental findings.

4.2

Family Tree of Photon-Recycling Phenomena

Photon recycling can be distinguished by the way emitted photons are recycled (Figure 4.2). In the case of external photon recycling, as shown schematically in Figure 4.3(a), parts of the photons (with energy hν1) that are emitted externally from active region 1 are recycled in narrower-bandgap active region 2; that is, the emitted photons are absorbed in active region 2 and create electron-hole pairs; the created electrons and holes rapidly emit phonons (namely, thermalize to the band edge); and recombination of the electrons at the bottom of the conduction band (EC2) and the holes at the top of the valence band (EV2) results in the emission of photons with energy hν2 (which is lower than hν1) (Figure 4.3[b]). Using blue-spectral InGaN in active region 1 and yellow-spectral AlGaInP in active region 2, an externally photon-recycled white light-emitting diode (LED) was first demonstrated in 1999 [23]. The latest achievement concerning external photon recycling include a safe ultraviolet (UV) LED. Since UV light is invisible to the naked eye and may cause irreparable damage to the human skin and eyes, green-light emission was incorporated External photon recycling Photon recycling

Intrinsic photon recycling Internal photon recycling Extrinsic photon recycling

Figure 4.2

Family tree of photon-recycling phenomena.

hv 1

hv 2 recycling

Active region 2

hv 1

E C1 E C2 hv 1

hv 1

hv 2 E V2

Active region 1 n-type

contact p-type contact (a)

E V1 (b)

Figure 4.3 (a) Schematic cross-section of a “semiconductor photon-recycling light-emitting diode” [23] and (b) energy-band diagrams illustrating processes involved in external photon recycling.

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in that UV LED as an indicator and warning sign during operation. Using ultraviolet-spectral In0.01Ga0.99N in active region 1 and green-spectral In0.28Ga0.72N in active region 2, a UV LED with an externally photon-recycled green indicator was demonstrated [24]. Internal photon recycling, in which the emitted photons are recycled within the host crystal, can be categorized as intrinsic photon recycling (IPR) by band-to-band transitions and extrinsic photon recycling (EPR) by transitions involving forbidden-gap energy levels [25]. As shown as an example of a forward-biased p+-n direct-bandgap semiconductor junction in Figure 4.4, intrinsic photon recycling increases minority-carrier lifetime τp; that is, the ratio of the resultant effective minority-carrier lifetime τeff to τp is defined as photon-recycling factor Φ [6] (see Section 3.4.4). Note that Φ should be different for specific device structures; for example, Φ = 4−6 in the case of an AlGaAs/8-μm-thick GaAs/AlGaAs double heterostructure [8]. On the other hand, extrinsic photon recycling involving deep acceptors or deep donors increases the ionization ratio of those dopants. However, the mechanism for extrinsic photon recycling has yet to be established. Section 4.7 presents possible models based on indirect experimental evidence.

4.3

Intrinsic Photon Recycling

The effect of intrinsic photon recycling on vertical GaN p-n diodes was analytically estimated by Velmre and Udal [26]. However, before their work is discussed, the effect of intrinsic photon recycling in GaAs solar cells is examined. By equating the ideal diffusion current (with an ideality factor n of unity—see Section 3.6.1.1) with photocurrent Iph, it is possible to express open-circuit voltage VOC as [27] VOC = (k T/q) ln(Iph/IS)

p+ type

(4.1)

p+ type

n type

n type

EC

EC

EV

EV

Figure 4.4 Schematic band diagrams of a forward-biased p+-n junction where intrinsic photon recycling is taking place.

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Intrinsic Photon Recycling

69

where k is Boltzmann’s constant, T is absolute temperature, q is electronic charge, and IS is saturation current. For p+-n type and n+-p type diodes, IS is, respectively, given as [27] IS = (A q NC NV/ND) (Dp/τpeff)0.5 exp(−Eg/k T)

(4.2a)

IS = (A q NC NV/NA) (Dn/τneff)0.5 exp(−Eg/k T)

(4.2b)

and

where A is active area, NC is effective density of states in conduction band, NV is effective density of states in valence band, ND is donor density, NA is acceptor density, Dp is hole diffusivity, Dn is electron diffusivity, τpeff is effective hole lifetime, τneff is effective electron lifetime, and Eg is energy bandgap. As the influence of intrinsic photon recycling increases, τpeff or τneff increases, thereby decreasing IS and increasing VOC. For example, in 2011, a GaAs single-junction solar cell with record η, consisting of front-metal contacts, an antireflection coating, a back-metal contact, and a flexible handle (Figure 4.5), attained IS/A of 6.0 × 10−21 A/m2 [28]. According to (4.2a) under the simple assumption of Φ = 10, IS/A should be 6.0 × 10−21 × 100.5 = 1.9 × 10−20 (A/m2) when the effect of intrinsic photon recycling is negligible (Figure 4.6[a]). Current/voltage characteristics of the GaAs solar cell under illumination are shown in Figure 4.6(b), where the solid and dashed curves, respectively, denote the characteristics with and without intrinsic photon recycling. Note that intrinsic photon recycling affects VOC, but not short-circuit current ISC. Therefore, the maximum output power with intrinsic photon recycling becomes larger than maximum output power without intrinsic photon recycling (i.e., area Vmw.o.PR Im of the rectangle with hatched dashed lines in Figure 4.6[b] by area (Vm − Vmw.o.PR) Im of the rectangle with hatched solid lines in Figure 4.6[b]). As for the increase in η of a two-junction solar cell reported in 2013 (Figure 4.1), intrinsic photon recycling also played an important role [29]. As shown in Figure 4.7, radiative recombination in the bottom (GaAs) cell Front metal Anti-reflection coating GaAs cell Back contact metal Flexible handle Figure 4.5

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Schematic cross-section of reported GaAs single-junction solar cell [28].

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Vertical GaN and SiC Power Devices

Current density (A/cm2)

1.E -01 −1 10

25 oC

−6 1.E -06 10

−11 1.E 10-11

n=1 1.E-16 −16 10

1.9 × 10−20 −21 1.E-21 10

6.0 × 10−21

0

0.2

0.4

0.6 Voltage (V)

0.8

1

(a) Current Vmw.o.PR VOCw.o.PR

O

0.4

0.8

Vm VOC 1.2

Voltage (V)

Im

−ISC

(b)

Figure 4.6 (a) Dark current-density/voltage characteristics and (b) illuminated current/ voltage characteristics of a GaAs single-junction solar cell shown in Figure 4.5. In (a), open circles denote series-resistance-corrected data [28]; solid and dashed lines, respectively, denote ideal diffusion-current density (whose ideality factor n is unity) with and without intrinsic photon recycling. In (b), solid and dashed curves, respectively, denote characteristics with and without intrinsic photon recycling. Im and Vm correspond to current and voltage for maximum power output (ISC: short-circuit current [i.e., photocurrent Iph]; VOC: open-circuit voltage with effect of photon recycling; VOCw.o.PR: open-circuit voltage without effect of photon recycling).

leads to the emission of photons at approximately the bandgap energy of GaAs (shown by solid arrows). Efficient photon recycling is possible because these photons are not absorbed in the top cell (made of wider-bandgap InGaP). It has to be noted, however, that the photons emitted through radiative recombination in the InGaP cell (shown by dashed arrows) are strongly absorbed in the GaAs cell, and that absorption reduces the potential for intrinsic photon recycling within the InGaP cell. The effect of intrinsic photon recycling on vertical GaN p-n diodes was similarly analyzed by Velmre and Udal [26]. However, their analyses

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Influence of IPR on Forward-Biased GaN p-n Diodes

71

Front metal Anti-reflection coating InGaP cell Tunnel junction GaAs cell Back contact metal Flexible handle Figure 4.7

Schematic cross-section of reported InGaP/GaAs two-junction solar cell [29].

were carried out before forward-current (IF)/voltage (VF) characteristics of vertical GaN p-n diodes were reported. Section 4.4 shows that the measured IF/VF characteristics of vertical GaN p-n diodes cannot be reproduced by simulation including the effect of intrinsic photon recycling only.

4.4

Influence of IPR on Forward-Biased GaN p-n Diodes

The IF/VF characteristics of a non-self-aligned mesa-type GaN p-n diode (anode-electrode radius: 30 μm; mesa radius: 35 μm) (Figure 4.8) were simulated (in terms of the cylindrical coordinate system) by using the commercial device simulator [30]. The epitaxial layers consisted of 0.5-μm-thick GaN (acceptor concentration NA: 5 × 1017 cm−3; acceptor level EA: 0.235 eV [31]) and 10-μm-thick GaN (donor concentration ND: 2 × 1016 cm−3). As for the GaN substrate, a thickness of 500 μm and ND of 5 × 1018 cm−3 were assumed. For lifetime τ of both electrons and holes, the same value was used. Contact resistivities of the anode and cathode electrodes were neglected. As shown in Figure 4.9, IF of GaN p-n diodes increases with increasing τ; however, IF saturates when τ exceeds 0.5 ms, and saturated IF is lower than measured IF (solid circles in Figure 4.9 [18]) when VF exceeds 3.6V. This result shows that the extended τ due to intrinsic photon recycling does not play a dominant role in determining the IF of vertical GaN p-n diodes. In contrast, even with τ of 50 ns, simulated IF monotonically increases with decreasing EA; in other words, the simulation can reproduce measured IF with EA between 0.135 and 0.185 eV (Figure 4.10). This result indicates that forward-current conduction increases the ionization ratio of deep acceptors with an EA of 0.235 eV. Since forward-current conduction generates not only recombination radiation but also heat, Section 4.5 considers the selfheating effect on the measured IF.

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Vertical GaN and SiC Power Devices

Anode electrode

p-GaN (5 × 10 17 cm−3/ 0.5 μm)

300

35 30

x (μm)

n-GaN (2 ×10 16 cm−3/10μm) n-GaN (5 ×10 18 cm−3/500μm) Cathode electrode y

Figure 4.8

Schematic of a simulated non-self-aligned mesa-type GaN p-n diode.

Forward current IF (mA)

60

Anode radius: 30μm E A = 0.235 eV 300 K

40

Measured T > 50 ms

T = 0.5 μs 20 T = 50 ns 0 3.0

3.3

3.6

3.9

Forward voltage VF (V) Figure 4.9 Measured forward-current/voltage characteristics of the GaN p-n diode reported in [18] (circles), together with characteristics simulated with a minority-carrier lifetime τ of 50 ns (solid line), 0.5 μs (dashed line), and 50 ms or longer (dotted line).

4.5 Influence of Self-Heating on Forward-Biased GaN p-n Diodes The self-heating effect on GaN-based high-power transistors was investigated by Turin and Balandin using the method of images [32]. They calculated the heat-spreading radius (b) from a point heat source on the surface of a substrate (thermal conductivity: κ1; thickness: t) with its rear surface contacting a heat sink (thermal conductivity: κ2) (Figure 4.11[a]). When κ2/ κ1 > 10, the amount of normalized heat flow 2b/t does not depend on κ2/κ1 but on the net heat-flow fraction (Σ in Figure 4.11) only; that is, 2b/t = 2.0, 2.3, and 2.8, when Σ = 50, 60, and 70%, respectively [32]. When the heat

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4.5

Influence of Self-Heating on Forward-Biased GaN p-n Diodes

Forward current IF (mA)

60

Anode radius: 30μm T = 50 ns 300 K

40

73

E A = 0.135 eV

Measured

20

E A = 0.185 eV E A = 0.235 eV

0 3.0

3.3

3.6

3.9

Forward voltage VF (V) Figure 4.10 Measured forward-current/voltage characteristics of the GaN p-n diode reported in [18] (circles), together with characteristics simulated with acceptor level EA of 0.235 eV (solid line), 0.185 eV (dashed line), and 0.135 eV (dotted line).

source has a finite area (radius: a), as shown in Figure 4.11(b), thermal resistance (Rth) across a circular cross-section (radius: b) along the vertical axis (z-axis) can be obtained, as long as heat spreads uniformly in the circular truncated cone, as follows [33]:

Rth =

∫

bt /(b − a)

at /(b − a)

(1 − κ1 ) t 2 ⎡⎣ π(b − a)2 ⎤⎦z −2dz = ⎡⎣2 / ( πκ1a )⎤⎦ /(2b / t)

(4.3)

2a

Σ

Σ

2b 2b

2b

(a)

(b)

Figure 4.11 Schematic of net heat-flow fraction Σ from (a) point and (b) circular (radius: a) heat sources on the surface of a semiconductor substrate.

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Vertical GaN and SiC Power Devices

The increase in junction temperature Tj (ΔTj) of GaN p–n diodes can therefore be estimated if a is small. When a is 30 μm, putting measured k1 of 2.0 Wcm−1K−1 [34] into (4.3) gives Rth (W/K) = 106 / (2b/t)

(4.4)

As shown in Figures 4.9 and 4.10, at 300K, power consumed by the diode (P) was 0.192W when the diode was forward-biased at 3.9V. When the ratio of photons externally radiated from the mesa edge is ηe, the net power that increases Tj is (1 − ηe)P; ΔTj is thus expressed as ΔTj = 20 Σ (1 − ηe)/ (2b/t)

(4.5)

Since determining ηe requires integrating sphere measurements, ΔTj was calculated as a function of ηe instead. As shown in Figure 4.12, maximum ΔTj is 5.2 K at ηe = 0 and almost independent of Σ (in the range from 50 to 70%). This ΔTj value is concluded to be too small to increase acceptor ionization at 300K. Therefore, the possible increase of ionization ratio of deep acceptors described in Section 4.4 is attributable to radiative recombination, namely, extrinsic photon recycling.

4.6

Influence of EPR on Forward-Biased GaN p-n Diodes

Junctuion-temperature increase ΔTi(K)

As shown in Section 3.7, peripheral current dominates IF of highly forward-biased non-self-aligned p-n diodes. Therefore, the EA values used to

66

Σ = 50% Σ = 60% Σ = 70%

44

22 a = 30μm 300K 0

O

0.2

0.4

0.6

0.8

1

Externally radiated photon ratio ηe

Figure 4.12 Dependence of estimated increase in junction temperature of the GaN p-n diode shown in Figure 4.8 on an externally radiated photon ratio. Net heat-flow fraction Σ is varied from 50 to 70%.

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4.6

Influence of EPR on Forward-Biased GaN p-n Diodes

75

reproduce measured IF of the GaN p-n diode in Figure 4.10 can only be used as a guide for an effective acceptor level EAeff. To quantitatively evaluate EAeff due to extrinsic photon recycling, rectangular transmission-line-model (TLM) patterns [35] formed with GaN p+–n junction epitaxial layers were employed by Mochizuki et al. [36]. Instead of EA = 0.175 eV [37] used in [36], more recently reported EA of 0.235 eV [31] is used in the following. The mesa structure of the TLM patterns (Figures 4.13 and 4.14), with epitaxial layer structures consisting of p++-GaN (Mg: 2 × 1020 cm−3/20 nm)/ p+-GaN (Mg: 5 × 1017 cm−3/0.5 μm)/n--GaN (Si: 2 × 1016 cm−3/10 μm)/ n+-GaN (Si: 2 × 1018 cm−3/ 2 μm), was fabricated by inductively coupledplasma (ICP) dry etching (see Section 7.2). Titanium/aluminum and palladium/aluminum ohmic electrodes, respectively, were then formed by electron-beam deposition on the bottom surface of an n+-GaN substrate and on the top surface of a p++-GaN layer (see Section 7.6.1). Finally, the exposed portion of the p++-GaN layer was etched by ICP dry etching using the palladium/aluminum electrodes as a mask. Current/voltage characteristics of the fabricated TLM patterns were first measured conventionally (namely, with no bias applied to the p–n junction; see Figure 4.13[b]). Under the

80

I

20

10

3μm

5

100μm

II’

(a)

A V Pd/Al ++ p GaN 70 nm 430 nm

p-GaN

n-GaN +

n GaN + n GaN substrate Ti/Al Stage

(b) Figure 4.13 Schematic (a) plan view of TLM patterns and (b) I-I cross-section of conventional TLM measurement setup.

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Vertical GaN and SiC Power Devices

80

20

3μm

5

10

100μm

II

II

(a)

A

V1 − V2 > 0.5V V2 IV A

V

VA Pd/Al

V1 ++

p GaN

p-GaN

IL

OFF n-GaN +

VK

n GaN + n GaN substrate Ti/Al Metal plate Glass slide Stage

(b) Figure 4.14 Schematic (a) plan view of transmission-line-model (TLM) patterns and (b) II-II cross-section of forward-biased TLM measurement setup.

assumption that the resistance of the pattern with the largest gap (i.e., 20 μm) is dominated by the sheet resistance of the p+-GaN layer, hole mobility μp was determined to be 15 cm2/Vs from the current/voltage characteristics obtained by the commercial device simulator [30] (Figure 4.15). One of the palladium/aluminum electrodes (anode) was then forwardbiased to the bottom electrode (cathode), and the current/voltage characteristics between the electrodes on both sides (Figure 4.14) were measured. As shown in Figure 4.16 as an example of potentials V1 and V2 simulated with anode current of 90 mA in 3-μm-gap/5-μm-gap patterns shown in Figure 4.14, V1 is almost constant, and V2 linearly decreases with increasing |V1 − V2| when V1 − V2 > 0.5V. Under this condition, lateral-current (|IL|)/ lateral-voltage (|V1 − V2|) characteristics of the 5-μm-gap region in the p+GaN layer are obtained. In Figure 4.16, when V1 − V2 < −0.5V, on the other hand, V2 is almost constant, and V1 linearly decreases with increasing |V1 − V2|. Under this condition, |IL|/|V1 − V2| characteristics of the 3-μm-gap region in the p+-GaN layer are obtained.

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4.6

Influence of EPR on Forward-Biased GaN p-n Diodes

77

2 Current (mA)

RT

−2

1

−1

O

1

2

Voltage (V) −1

Measured μp = 17 cm2/Vs 15 cm 2/Vs 13 cm 2/Vs

−2

Figure 4.15 Measured (open circles) and simulated (by using hole mobility μp as a parameter) current/voltage characteristics of a 20-μm-gap transmission-line-model pattern.

3.1

3.0

2.9

Characteristics in 3-μm-gap region −2

−1

Characteristics in 5-μm-gap region

2.8 0

1

2

V1−V2(V)

Figure 4.16 Simulated potentials of V1 and V2 (in Figure 4.14) of 3-μm-gap/5-μm-gap patterns with anode current of 90 mA (i.e., anode-to-cathode voltage [VA – VK in Figure 4.14] of 3.24V), as a function of V1 - V2.

When |V1 − V2| < 0.5V, both V1 and V2 are larger than the built-in potential of the p–n junction, Vbi (about 3V), so the hole current flows not only in the p+-layer but also in the n--GaN layer. Therefore, the experimental results for this condition (|V1 − V2| < 0.5V) were not used because of difficulty in the analysis. Measured and simulated |IL|/|V1 − V2| characteristics of the TLM patterns when the vertical anode current IV was 90 mA are compared in Figure 4.17. When the gap of the TLM patterns is 20 μm (Figure 4.17[a]), measured IL agrees well with IL simulated with an EA of 0.235 eV. However, as the gap decreases from 10 μm, measured IL deviates more from IL simulated with EA of 0.235 eV. (Figure 4.17[b−d]). Since this tendency was also the case for

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Vertical GaN and SiC Power Devices

0.8 0.6

(a) 20-μm gap

measured

0.4 0.2 0

E A = 0.235 eV

0.8 0.6

(b) 10-μm gap

0.4

measured E Aeff = 0.144 eV

IL

(mA)

0.2 E A = 0.235 eV

0 0.8 0.6

(c) 5-μm gap

measured E Aeff = 0.147 eV

0.4

0.2 E A = 0.235 eV

0 0.8 0.6

(d) 3-μm gap

2

0.4

E Aeff = 0.150 eV

0.2

E A = 0.235 eV

0 − 0.2 0.5

measured 1

1.5 V1 – V2 (V)

2

Figure 4.17 Measured (symbols) and simulated lateral-current (|IL|)/lateral-voltage (|V1−V2|) characteristics of transmission-line-model patterns with vertical current of 90 mA.

IV = 10−70 mA, it is concluded that the effect of extrinsic photon recycling rapidly decreases from the edge of the p-type electrode, over a 10-μm range, independently of IV.

4.7

Possible Models for EPR

In a conductivity-modulated GaN p+-n junction (see Section 3.7), photons are considered to be created mainly through the conduction-band/valenceband transition in n-GaN. In [33], the energy of photons was assumed to be used for electron emission from ionized magnesium acceptors to the conduction band (Figure 4.18[a-1]). The resultant neutralized acceptors are then ionized through electron capture from the valence band. The electrons emitted from the ionized magnesium acceptors to the conduction band in p+-GaN are considered to emit phonons and move to the conduction-band minimum (Figure 4.18[a-2]). If the holes are injected into n-GaN (Figure

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4.7

Possible Models for EPR

79

EC

0 - 0 - 0 -

EC

0 - 0 - 0 -

EV

EV

(a-1)

(b-1)

EC

0 - 0 - 0 0

EC

0 - 0 - - -

EV

EV

(a-2)

(b-2)

EC

0 - 0 - 0 -

EC

0 - 0 - - -

EV

EV

(a-3)

(b-3) Supplied from n +-GaN

0 - 0 - 0 -

Supplied from n +-GaN 0 - 0 - - -

EV (a-4)

EV (b-4)

Figure 4.18 Energy-band diagrams illustrating two possible models (i.e., from [a-1] to [a-4] and from [b-1] to [b-4] for extrinsic photon recycling in GaN p-n diodes.

4.18[a-3]), the same number of electrons are injected into n-GaN from n+GaN to maintain charge neutrality in n-GaN (Figure 4.18[a-4]). However, if the electrons recombine with the holes in p+-GaN, the ratio of ionized magnesium acceptors does not increase. If the energy of photons was used by neutral magnesium acceptors to capture electrons from the valence band (Figure 4.18[b-1]), the acceptors are ionized and the high-energy holes in the conduction band in p+-GaN are considered to emit phonons and move to the valence-band maximum (Figure 4.18[b-2]). In this case, the ratio of ionized magnesium acceptors increases. And if the holes are injected into n-GaN (Figure 4.18[b-3]), to

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Vertical GaN and SiC Power Devices

maintain charge neutrality in n-GaN, the same number of electrons are injected into n-GaN from n+-GaN (Figure 4.18[b-4]). Note that in both cases shown in Figure 4.18(a-1−a-4, b-1−b-4), conservation of momentum is not violated; since acceptors and donors are highly localized, they have a wide range in momentum space (according to the uncertainty principle). To reveal the mechanism of extrinsic photon recycling, however, further experimental investigation is needed.

4.8

Summary

This chapter classifies photon recycling as external photon recycling or internal photon recycling. White and UV LEDs are introduced as examples of the application of external photon recycling. Internal photon recycling, which has recently been utilized to improve the η of multijunction solar cells and BV2/RonAdiff of vertical GaN p-n diodes, was further classified as intrinsic photon recycling by band-to-band transitions and extrinsic photon recycling by transitions involving forbidden-gap energy levels. While intrinsic photon recycling is responsible for improving η, intrinsic photon recycling alone cannot explain the improved BV2/RonAdiff. Extrinsic photon recycling by transitions involving deep acceptors is thus considered to play an important role in increasing the ionization ratio of deep acceptors in p+-GaN. To reveal the mechanism of extrinsic photon recycling, however, further experimental investigation is needed.

References [1] Baliga, B. J., Gallium Nitride and Silicon Carbide Power Devices, Singapore: World Scientific, 2017, p. 52. [2] Kizilyalli, I. C., et al., “Vertical Power p-n Diodes Based on Bulk GaN,” IEEE Transactions on Electron Devices, Vol. 62, No. 2, 2015, pp. 414–422. [3] Baliga, B. J., Gallium Nitride and Silicon Carbide Power Devices, Singapore: World Scientific, 2017, p. 215. [4] Dumke, W. P., “Spontaneous Radiative Recombination in Semiconductors,” Physical Review, Vol. 105, No. 1, 1957, pp. 139–144. [5] Stern, F., and J. M. Woodall, “Photon Recycling in Semiconductor Lasers,” Journal of Applied Physics, Vol. 45, No. 9, 1974, pp. 3904–3906. [6] Asbeck, P., “Self-Absorption Effects on the Radiative Lifetime in GaAsGaAlAs Double Heterostructures,” Journal of Applied Physics, Vol. 48, No. 2, 1977, pp. 820–822. [7] Kuriyama, T., T. Kamiya, and H. Yanai, “Effect of Photon Recycling on Diffusion Length and Internal Quantum Efficiency in AlxGa1-xAs-GaAs

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Summary

81

Heterostructures,” Japanese Journal of Applied Physics, Vol. 16, No. 3, 1977, pp. 465–477. [8] Ahrenkiel, R. K., et al., “Ultralong Minority-Carrier Lifetime Epitaxial GaAs by Photon Recycling,” Applied Physics Letters, Vol. 55, No. 11, 1989, pp. 1088–1090. [9] Gigase, Y. B., et al., “Threshold Reduction Through Photon Recycling in Semiconductor Lasers,” Applied Physics Letters, Vol. 57, No. 13, 1990, pp. 1310–1312. [10] Numai, T., et al., “Current Versus Light-Output Characteristics with No Definite Threshold in pnpn Vertical to Surface Transmission Electrophotonic Devices with a Vertical Cavity,” Japanese Journal of Applied Physics, Vol. 30, No. 4A, 1991, pp. L602–L604. [11] Savage, N., “Photon Recycling Breaks Solar Power Record,” IEEE Spectrum, Vol. 48, No. 8, 2011, p. 16. [12] Mochizuki, K., et al., “Photon-Recycling GaN p-n Diodes Demonstrating Temperature-Independent, Extremely Low On-Resistance,” International Electron Devices Meeting, Washington, DC, Dec. 5–7, 2015, pp. 591–594. [13] http://www.nrel.gov/ncpv/images/efficiency_chart.jpg. [14] Irokawa, Y., et al., “Current–Voltage and Reverse Recovery Characteristics of Bulk GaN p-i-n Rectifier,” Applied Physics Letters, Vol. 83, No. 11, 2003, pp. 2271–2273. [15] Cao, X. A., et al., “Growth and Characterization of GaN PiN Rectifiers on Freestanding GaN,” Applied Physics Letters, Vol. 87, 2005, pp. 053503-1–053503-3. [16] Yoshizumi, Y., et al., “High-Breakdown-Voltage pn-Junction Diodes on GaN Substrates,” Journal of Crystal Growth, Vol. 298, 2007, pp. 875–878. [17] Nomoto, K., et al., “Over 1.0 kV GaN p-n Junction Diodes on Freestanding GaN Substrates,” Physica Status Solidi A, Vol. 208, No. 7, 2011, pp. 1535–1537. [18] Hatakeyama, Y, et al., “Over 3.0 GW/cm2 Figure-of-Merit GaN p-n Junction Diodes on Freestanding GaN Substrates,” IEEE Electron Device Letters, Vol. 32, No. 12, 2011, pp. 1674–1676. [19] Hatakeyama, Y, et al., “High-Breakdown-Voltage and Low-Specific-on-Resistance GaN p-n Junction Diodes on Freestanding GaN Substrates Fabricated Through Low-Damage Field-Plate Process,” Japanese Journal of Applied Physics, Vol. 52, 2013, pp. 028007-1–028007-3. [20] Ohta, H., et al., “Vertical GaN p-n Junction Diodes with High Breakdown Voltage over 4 kV,” IEEE Electron Device Letters, Vol. 36, No. 11, 2015, pp. 1180–1182. [21] Nomoto, K., et al., “GaN-on-GaN p-n Power Diodes with 3.48 kV and 0.95 mΩcm2: A Record High Figure-of-Merit of 12.8 GW/cm2,” International Electron Devices Meeting, Washington, D.C., Dec. 7–9, 2015, pp. 237–240. [22] Ohta, H., et al., “5.0 kV Breakdown-Voltage Vertical GaN p-n Junction Diodes,” Extended Abstracts of International Solid State Devices and Materials, Sendai, Sep. 19–22, 20017, pp. 671–672. [23] Guo, X., J. Grafi, and E. F. Schubert, “Photon Recycling Semiconductor Light Emitting Diode,” International Electron Devices Meeting, Washington, D.C., Dec. 5–8, 1999, pp. 600–603.

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[24] Chen, F. B., et al., “GaN-Based UV Light-Emitting Diodes with a Green Indicator Through Selective-Area Photon Recycling,” IEEE Transactions on Electron Devices, Vol. 63, No. 3, 2016, pp. 1122–1127. [25] Mochizuki, K., et al., “Influence of Surface Recombination on Forward Current–Voltage Characteristics of Mesa GaN p+n Diodes Formed on GaN Freestanding Substrates,” IEEE Transactions on Electron Devices, Vol. 59, No. 4, 2012, pp. 1091–1098. [26] Velmre, E., and A. Udal, “Comparison of Photon Recycling Effect in GaAs and GaN Structures,” Estonian Academy of Sciences, Engineering, Vol. 10, No. 3, 2004, pp. 157–172. [27] Sze, S. M., and K. K. Ng, Physics of Semiconductor Devices (Third Edition), Hoboken, NJ: John Wiley & Sons, 2007, p. 723. [28] Kayes, B. M., et al., “27.6% Conversion Efficiency, a New Record for SingleJunction Solar Cells Under 1 Sun Illumination,” 37th IEEE Photovoltaic Specialists Conference (PVSC), Seattle, WA, June 19–27, 2011, pp. 4–8. [29] Kayes, B. M., et al., “Flexible Thin-Film Tandem Solar Cells with >30% Efficiency,” Journal of Photovoltaics, Vol. 4, No. 2, 2014, pp. 729–733. [30] http://www.silvaco.com/products/tcad/device_simulation/atlas/atlas.html. [31] Horita, M., et al., “Hall-Effect Measurements of Metalorganic VaporPhase Epitaxy-Grown p-Type Homoepitaxial GaN Layers with Various Mg Concentrations,” Japanese Journal of Applied Physics, Vol. 55, 2016, pp. 05FH03-1–05FH03-4. [32] Turin, V., and A. A. Balandin, “Electrothermal Simulation of the Self-heating Effects in GaN-Based Field-Effect Transistors,” Journal of Applied Physics, Vol. 100, 2006, pp. 054501-1–054501-8. [33] Mochizuki, K., et al., “Optical-Thermo-Transition Model of Reduction in On-Resistance of Small GaN p-n Diodes,” Japanese Journal of Applied Physics, Vol. 52, 2013, pp. 08JN10-1–08JN10-4. [34] Ohshima, Y., et al., “Thermal and Electrical Properties of High-Quality Freestanding GaN Wafers with High Carrier Concentration,” Physica Status Solidi C, Vol. 4, No. 7, 2007, pp. 2215–2218. [35] Berger, H. H., “Models for Contacts to Planar Devices,” Solid-State Electronics, Vol. 15, No. 2-A, 1972, pp. 145–158. [36] Mochizuki, K., et al., “Determination of Lateral Extension of Extrinsic Photon Recycling in p-GaN by Using Transmission-Line-Model Patterns Formed with GaN p–n Junction Epitaxial Layers,” Japanese Journal of Applied Physics, Vol. 52, 2013, pp. 08JN22-1–08JN22-4. [37] Pearton, S. J., C. R. Abernathy, and F. Ren, Gallium Nitride Processing for Electronics, Sensors, and Spintronics, London: Springer, 2006, p. 184.

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CHAPTER

5 Contents

Bulk Crystal Growth

5.1 Introduction 5.2 HVPE Growth of GaN 5.3 High-Pressure Nitrogen Solution Growth of GaN 5.4 Sodium-Flux Growth of GaN 5.5 Ammonothermal Growth of GaN 5.6 Sublimation Growth of SiC 5.7 High-Temperature Chemical Vapor Deposition of SiC 5.8 Solution Growth of SiC 5.9 Summary

5.1

Introduction

Growing bulk crystals is indispensable for producing single-crystal wafers. It is well-known that silicon wafers are produced from a polycrystalline silicon melt. Even in the case of GaAs, which has a considerable vapor pressure due to arsenic, melt growth with a liquid encapsulant (i.e., boron oxide, B2O3) has been widely used for producing single-crystal wafers [1]. However, no such encapsulant for either GaN or SiC has been found. As shown in the phase diagrams of the GaN and SiC binary systems in Figure 5.1, a stoichiometric liquid phase does not exist in GaN or SiC under atmospheric pressure [2, 3]. For liquidphase bulk growth from a stoichiometric melt, temperature and pressure exceeding, respectively, 2,700K and 92,000 atm for GaN (Figure 5.2 [2]) and 3,573K and 98,000 atm for SiC [3] are theoretically needed. Therefore, the most common techniques for growing bulk GaN and SiC at present is vapor-phase growth—namely,

83

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gas (1 atm)

Temperature (K)

2500

2000 liquid + gas 1500 1117 1000 liquid +GaN 500

GaN + gas

303 Ga + GaN 0

20 40 60 80 100 Atomic percent of nitrogen (%) (a)

4000 gas (< 1 atm) Temperature (K)

3500 3113 ± 40 3000 liquid +SiC

2500

SiC + C

2000 1687 Si + SiC

1500 0

20 40 60 80 100 Atomic percent of carbon (%) (b)

Figure 5.1 Phase diagrams of (a) GaN and (b) SiC binary systems under atmospheric pressure [2, 3].

hydride vapor-phase epitaxy (HVPE) for growing GaN and sublimation for growing SiC. This chapter also introduces other techniques for bulk-crystal growth, as they are now being intensively investigated as ways to improve crystal quality and productivity.

5.2

HVPE Growth of GaN

Since GaN seed crystal is not readily available (see Section 2.1), thick GaN films are grown by HVPE on foreign substrates, such as GaAs and sapphire. The biggest advantage of HVPE growth is its high growth rate (typically, several hundred micrometers per hour).

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5.2

HVPE Growth of GaN

85

3000 liquid

Temperature (K)

2500

2700 (92 katm) 49 katm

liquid +GaN

2000

GaN + liquid

10 katm 1500

1000

500

303 0

20

40

60

80

100

Atomic percent of nitrogen (%) Figure 5.2

5.2.1

Calculated condensed phase diagram of the GaN system [2].

Mechanism of HVPE Growth of GaN

An HVPE reactor generally consists of source and epitaxy zones (Figure 5.3). In the source zone, gallium is kept at a certain temperature (about 1,100K) and reacts with HCl gas as follows: 2Ga(l)+2HCl(g) ↔ 2GaCl(g)+H2(g)

(5.1a)

Ga(l)+HCl(g) ↔ GaCl2(g)+H2(g),

(5.1b)

2Ga(l)+6HCl(g) ↔ 2GaCl3(g)+3H2(g)

(5.1c)

2GaCl3(g) ↔ (GaCl3)2(g)

(5.1d)

Source zone

Epitaxy zone

NH 3 HCl Carrier gas

Ga

Substrate

Figure 5.3 Schematic illustration of hydride vapor-phase epitaxial growth reactor consisting of source and epitaxy zones.

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where “l” and “g” in parentheses denote, respectively, liquid and gas. The gaseous species formed in the source zone according to the above reactions and NH3 are separately transported to the epitaxy zone by a carrier gas such as hydrogen, nitrogen, helium, and argon. In the epitaxy zone, the source species are mixed according to the following reactions: GaCl(g)+NH3(g) ↔ GaN(s)+HCl(g)+H2(g)

(5.2a)

2GaCl(g)+2HCl(g) ↔ 2GaCl2(g)+H2(g)

(5.2b)

GaCl(g)+2HCl(g) ↔ GaCl3(g)+H2(g)

(5.2c)

2GaCl3(g) ↔ (GaCl3)2(g)

(5.2d)

where “s” in parentheses denotes solid. According to a reported thermodynamic calculation [4], the partial pressures of GaCl2 and (GaCl3)2 are very small. Moreover, the partial pressure of GaCl3 is much lower than that of GaCl [5], so (5.2a) is considered the most dominant reaction. Supersaturation in the case of HVPE growth of GaN is expressed as σ = (P0GaCl−PeGaCl)/PeGaCl = (P0GaCl/PeGaCl)−1

(5.3)

where P0GaCl and PeGaCl are, respectively, input and equilibrium partial pressures of GaCl. 5.2.2

Doping During HVPE Growth of GaN

Dichlorosilane (SiH2Cl2) is commonly used for HVPE growth of silicondoped GaN due to its high thermal stability [6]. Note that silane (SiH4) is unsuitable for silicon doping in HVPE because it decomposes into silicon and hydrogen before it is transported to the epitaxy zone. With respect to p-type doping, on the other hand, metallic magnesium has been used to fabricate freestanding GaN by HVPE [7]. 5.2.3

Epitaxial Lateral Overgrowth of GaN

Epitaxial lateral overgrowth (ELO) is generally known to be effective for bending dislocations (extending from substrates) and thereby reducing dislocation density [8]. In the case of GaN, conventional ELO was improved by two processes: dislocation elimination using epitaxial growth with inversepyramidal pits (DEEP) [9, 10] and void-assisted separation (VAS) with a thin TiN film [11, 12].

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5.3

High-Pressure Nitrogen Solution Growth of GaN

87

As for DEEP [10], a SiO2 layer having round openings was formed directly on a GaAs surface. First, a GaN buffer layer was grown on the GaAs surface at a low temperature. The substrate temperature was then raised to the growth temperature of GaN in an NH3 ambient, and a thick GaN layer was grown. After the GaN layer was grown to a thickness of over 500 µm, the GaAs starting substrate was mechanically removed. When a GaN crystal grows with numerous large pits, dislocations are concentrated at the center of each pit. Dislocation density therefore decreases with increasing distance from the center of the pits. Up to 150-mm freestanding GaN substrates have been grown by using 150-mm GaAs wafers [13]. In contrast, dislocation density (about 3 × 106 cm−2) in GaN substrates fabricated by VAS using a sapphire substrate is relatively uniform [12]. A TiN nano-mask formed during VAS is used to easily separate GaN from sapphire [11]. However, enlarging wafer diameter is difficult due to orientation deviation. Recently, 175-mm freestanding GaN substrates were fabricated by a tiling technique that merges small multiple wafers with a thick GaN layer grown by HVPE [14].

5.3

High-Pressure Nitrogen Solution Growth of GaN

In high-pressure nitrogen solution (HPNS) growth [15], the solubility of nitrogen in a gallium melt becomes relatively high, because nitrogen molecules dissociate on the gallium surface and dissolve in the gallium melt. The dissolved nitrogen atoms are then transported from hot regions to cool regions in the gallium solution, where GaN crystallizes. The growth rate is low due to the very low solubility of nitrogen (< 0.5%), and the size of the grown GaN crystals has been limited to several millimeters. However, it was reported that HPNS growth produces very low dislocation-density (< 2 × 102 cm−2) [15].

5.4

Sodium-Flux Growth of GaN

The solubility of nitrogen in a gallium melt is increased by adding sodium to the melt. This so-called sodium-flux method can thus decrease the growthtemperature range (800−1,200K) and pressure (< 50 atm) [16]. Nitrogen molecules are first ionized by sodium at the gas/liquid interface, and the ionized nitrogen is dissolved in the Ga-Na melt. The nitrogen atoms then combine with gallium atoms, thereby nucleating GaN crystal [16]. Most of the nitrogen atoms contribute to the growth of GaN-seed crystal at the bottom of a crucible. However, when the nitrogen concentration exceeds a critical value, liquid-phase epitaxy (LPE) occurs [17−23]. Four-inch GaN

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bulk crystal [22] with low dislocation density (< 103 cm−2) has reportedly been grown by this method [23].

5.5

Ammonothermal Growth of GaN

Ammonothermal growth of GaN involves creating a temperature gradient between a source material zone and GaN seeds. An autoclave, which is a pressure chamber used at elevated temperature, is filled with ammonia and heated to 800–900K, generating pressure in the range of 2,000–4,000 atm, which makes the ammonia a supercritical fluid (Figure 5.4). Supercritical ammonia enables transport of GaN from the source zone to the seeds, which can thereby grow [24]. To increase the solubility of GaN in supercritical ammonia, basic mineralizers (e.g., NaNH2, LiNH2, and KNH2) or acidic mineralizers (e.g., NH4Cl, NH4Br, and NH4I) are commonly used [25]. In 1995, a fine crystalline GaN was obtained from gallium, ammonia, and LiNH2 (or KNH2) by Dwilinski et al. [26] Moreover, GaN crystal grown with such basic mineralizers was reported to have dislocation density below 104 cm−2 [27]. With respect to acidic mineralizers, on the other hand, the first experimentally grown GaN crystal was reported in 2008, and its dislocation density was relatively high (106 cm−2) due to the use of HVPE seeds [28]. Although the rate of ammonothermal growth of GaN improved to 344 μm/day for c-plane growth and 46 μm/day for m-plane growth [29], reducing the impurity level is still challenging; for example, concentrations of transition metal and oxygen in the GaN crystal were reported, respectively, to be less than 1017 cm−3 and in the order of 1019 cm−3 [5].

Pressure (atm)

Supercritical fluid 2000 −4000

Solid

Critical point

Liquid Gas

Triple point

800–900 Temperature (K)

Figure 5.4

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Schematic pressure versus temperature relation of ammonia.

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5.6

Sublimation Growth of SiC

5.6

89

Sublimation Growth of SiC

The first sublimation growth of SiC, in which many platelets nucleated randomly in a crucible, was carried out by Lely in 1955 [30]. After that, seeded sublimation growth of SiC, in which the seed crystal was placed at a 100-K cooler point in a crucible, was achieved by Tairov and Tsvetkov in 1978 [31]. In the case of this so-called modified Lely method, the SiC seed crystal is placed near the lid of the crucible, while SiC powder is placed at the bottom of the crucible (Figure 5.5). Radio-frequency induction or resistive heating heats the crucible, under the flow of argon or helium to about 2,600K. Progressive increases in the diameter of sublimation-grown 4H-SiC bulk crystal has resulted in the commercial availability of 150-mm diameter wafers, as well as the recent announcement of 200-mm diameter wafers [32]. 5.6.1

Mechanism of Sublimation Growth of SiC

The main reactions during sublimation growth of SiC are given as follows [33]: Si2C(g)+SiC2(g) ↔ 3SiC(s)

(5.4a)

SiC2(g)+3Si(g) ↔ 2Si2C(g)

(5.4b)

Si2C(g) ↔ 2Si(g)+C(s)

(5.4c)

Si(g) ↔ Si(l)

(5.4d)

Seed

rf coil

Grown boule

Low temperature

Vapor-phase to solid-phase

Solid-phase to vapor-phase

Source

High temperature

Graphite crucible

Figure 5.5

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Schematic illustration of a crucible for seeded sublimation growth of SiC.

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Due to the low stacking-fault energy of SiC (see Section 2.2.3), polytype mixing often occurs [34]. In the case of sublimation growth of heavilynitrogen-doped n-type 4H-SiC ( 000 1 ) under optimized conditions, however, no polytype mixing occurs [35]. 5.6.2

Doping During Sublimation Growth of SiC

SiC is doped with nitrogen by introducing nitrogen gas into the growth ambient. The incorporation of nitrogen in SiC crystal is determined by the equilibrium between nitrogen in the gas phase and nitrogen adsorbed on the growing surface [36]. Although nitrogen concentration NN can be increased to 1020 cm−3, NN in commercial n-type 4H-SiC wafers is kept to less than 2 × 1019 cm−3 to suppress stacking-fault formation [37, 38]. P-type doping, on the other hand, is achieved by adding an aluminumcontaining compound to the SiC source. The incorporation of aluminum into SiC crystal is almost proportional to the vapor pressure of aluminum in the crucible. However, heavy aluminum doping is still a challenge because it leads to preferential growth of 6H-SiC [35].

5.7

High-Temperature Chemical Vapor Deposition of SiC

High-temperature chemical vapor deposition (HT-CVD) has been developed to overcome the limitation of sublimation growth of SiC [39−41]. A SiC boule is grown at 2,400−2,700K and 0.2−0.7 atm in a vertical graphite crucible (Figure 5.6). Highly supersaturated vapor forms silicon and SiC clusters via homogeneous nucleation. Precursor gases (e.g., SiH4 and C3H8 diluted in herium or H2 carrier gas) are fed through a heating zone to a seed-crystal holder placed at the top of the reactor. The typical growth rate is 0.3−0.7 mm/h. Compared to sublimation growth, HT-CVD has the advantage that the supply of source material is maintained without depletion, thereby enabling growth of long SiC boules.

5.8

Solution Growth of SiC

As noted in Section 2.1, the solubility of carbon in silicon solution is very low. It, however, can be increased under high pressure. For instance, argon pressure of 98 atm was used for solution growth of SiC [42]; however, the SiC growth rate was below 0.5 mm/h around 2,500K. The solubility of carbon in a silicon solution can also be increased by adding chromium, scandium, or titanium to a SiC solvent [43−49]. For instance, the maximum growth rate was reported to be 2 mm/h at 2,300K [49]; however, metallic contamination (in the order of 1017 cm−3 [50]) in the grown SiC could be a problem. With respect to doping, both p-type

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5.9

Summary

91

Seed-crystal holder Seed Grown boule

Heating zone

Graphite crucible

Precursors

Figure 5.6

Schematic illustration of a reactor for HT-CVD of SiC.

10 1

Growth rate (mm/h)

< 4-inch solution growth SiC 10 0

4-inch HTCVD SiC 150-mm seeded 175-mm HVP GaN sublimation SiC

10 −1

10 −2

150-mm HVP GaN 4-inch < 4-inch ammonotherma Na flux GaN GaN

Platelets HPNS GaN 10−3 1 10 10 2 10 3 10 4 10 5 Dislocation density (cm−2 )

10 6

10 7

Figure 5.7 Comparison of reported growth rate and dislocation density of bulk GaN and 4H-SiC. The diameter of the circles schematically represents the reported maximum diameter of wafers.

and n-type 4H-SiC were successfully grown under Al-N codoping conditions [51].

5.9

Summary

Figure 5.7 compares the growth rate, dislocation density, and maximum wafer diameter of bulk GaN and 4H-SiC described in this chapter. A tiling

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technique that merges multiple wafers grown by sodium-flux with a thick GaN layer by HVPE [14] is a candidate for fabricating large-area small-dislocation-density GaN wafers. As for 4H-SiC, seeded sublimation growth is possibly the most mature; however, solution growth is a candidate for highquality 4H-SiC wafers.

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[14] Yoshida, T., et al., “Development of GaN Substrate with a Large Diameter and Small Orientation Deviation,” Physica Status Solidi B, Vol. 254, No. 8, 2017, pp. 1600671-1–1600671-4. [15] Bockowski, M., “Bulk Growth of Gallium Nitride: Challenges and Difficulties,” Crystal Research and Technology, Vol. 42, No. 12, 2007, pp. 1162–1175. [16] Yamane, H., et al., “Preparation of GaN Single Crystals Using a Na Flux,” Chemistry of Materials, Vol. 9, No. 2, 1997, pp. 413–416. [17] Mori, Y., et al., “Growth of GaN Crystals by Na Flux LPE Method,” Physica Status Solidi A, Vol. 207, No. 6, 2010, pp. 1283–1286. [18] Kawamura, F., et al., “Growth of a Large GaN Single Crystal Using the Liquid Phase Epitaxy (LPE) Technique,” Japanese Journal of Applied Physics, Vol. 42, No. 1A, 2003, pp. L4–L6. [19] Kawamura, F., et al., “Novel Liquid Phase Epitaxy (LPE) Growth Method for Growing Large GaN Single Crystals: Introduction of the Flux Film CoatedLiquid Phase Epitaxy (FFC-LPE) Method,” Japanese Journal of Applied Physics, Vol. 42, No. 8A, 2003, pp. L879–L881. [20] Kawamura, F., et al., “The Effects of Na and Some Additives on Nitrogen Dissolution in the Ga-N System: A Growth Mechanism of GaN in the Na Flux Method,” Journal of Materials Science: Materials in Electronics, Vol. 16, No. 1, 2005, pp. 29–34. [21] Kawamura, F., et al., “Effect of Carbon Additive on Increases in the Growth Rate of 2 in GaN Single Crystals in the Na Flux Method,” Journal of Crystal Growth, Vol. 310, No. 17, 2008, pp. 3946–3949. [22] Mori, Y., et al., “Growth of GaN Crystals by Na Flux Method,” ECS Journal of Solid State Science and Technology, Vol. 2, No. 8, 2013, pp. N3068–N3071. [23] Imade, M., et al., “Growth of Bulk GaN Crystals By the Na-Flux Seed Technique,” Japanese Journal of Applied Physics, Vol. 53, No. 5S1, 2014, pp. 05FA06-1–05FA06-5. [24] Dwilinski, R., et al., “Properties of Truly Bulk GaN Monocrystals Grown by Ammonothermal Method,” Physica Status Solidi C, Vol. 6, No. 12, 2009, pp. 2661–2664. [25] Fukuda, T., and D. Ehrentraut, “Prospects for the Ammonothermal Growth of Large GaN Crystal,” Journal of Crystal Growth, Vol. 305, No. 2, 2007, pp. 304–310. [26] Dwilinski, R., et al., “GaN Synthesis by Ammonothermal Method,” Acta Physica Polonia A, Vol. 88, No. 5, 1995, pp. 833–836. [27] Dwilinski, R., et al., “Excellent Crystallinity of Truly Bulk Ammonothermal GaN,” Journal of Crystal Growth, Vol. 310, No. 17, 2008, pp. 3911–3916. [28] Ehrentraut, D., et al., “Reviewing Recent Developments in the Acid Ammonothermal Crystal Growth of Gallium Nitride,” Journal of Crystal Growth, Vol. 310, No. 17, 2008, pp. 3902–3906. [29] Pimpukar, S., et al., “Improved Growth Rates and Purity of Basic Ammonothermal GaN,” Journal of Crystal Growth, Vol. 403, 2014, pp. 7–17.

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[30] Lely, J. A., “Darstellung von Einkristallen von Silicium Carbid und Beherrschung von Art und Menge der eingebauten Verunreinigungen,” Berichte der Deutschen Keramischen Gesellschaft, Vol. 32, 1955, pp. 229–236. [31] Tairov, Y. M., and V. F. Tsvetkov, “Investigation of Growth Processes of Ingots of Silicon Carbide Single Crystals,” Journal of Crystal Growth, Vol. 43, 1978, pp. 209–212. [32] https://globenewswire.com/news-release/2015/07/16/752880/10142036/ en/II-VI-Advanced-Materials-Demonstrates-World-s-First-200mm-DiameterSiC-Wafer.html. [33] Kaprov, S. Y., Y. N. Makarov, and M. S. Ramm, “Simulation of Sublimation Growth of SiC Single Crystals,” Physica Status Solidi B, Vol. 202, No. 1, 1997, pp. 201–220. [34] Knippenberg, W. F., “Growth Phenomena in Silicon Carbide,” Philips Research Reports, Vol. 18, 1963, pp. 161–274. [35] Kimoto, T., and J. A. Cooper, Fundamentals of Silicon Carbide Technology, Singapore: John Wiley & Sons, 2014, p. 49. [36] Ohtani, N., et al., “Impurity Incorporation Kinetics During Modified-Lely Growth of SiC,” Journal of Applied Physics, Vol. 83, No. 8, 1998, pp. 4487–4490. [37] Chung, H. J., et al., “Stacking Fault Formation in Highly Doped 4H-SiC Epilayers During Annealing,” Materials Science Forum, Vol. 433–436, 2003, pp. 253–256. [38] Rost, H. J., et al., “Influence of Nitrogen Doping on the Properties of 4H-SiC Single Crystals Grown by Physical Vapor Transport,” Journal of Crystal Growth, Vol. 257, No. 1–2, 2003, pp. 75–83. [39] Kordina, O., et al., “High Temperature Chemical Vapor Deposition of SiC,” Applied Physics Letters, Vol. 69, No. 10, 1996, pp. 1456–1458. [40] Ellison, A., et al., “High Temperature CVD Growth of SiC,” Materials Science and Engineering B, Vol. 61−62, 1999, pp. 113–120. [41] Ellison, A., et al., “SiC Crystal Growth by HTCVD,” Materials Science Forum, Vol. 457−460, 2004, pp. 9–12. [42] Hofmann, D. H., and M. H. Muller, “Prospects of the Use of Liquid Phase Techniques for the Growth of Bulk Silicon Carbide Crystals,” Materials Science and Engineering B, Vol. 61−62, 1999, pp. 29–39. [43] Syväyärvi, M., et al., “Liquid Phase Epitaxial Growth of SiC,” Journal of Crystal Growth, Vol. 197, 1999, pp. 147–154. [44] Kusunoki, K., et al., “Solution Growth of Self-Standing 6H-SiC Single Crystal Using Metal Solvent,” Materials Science Forum, Vol. 457–460, 2004, pp. 123–126. [45] Ujihara, T., et al., “Crystal Quality Evaluation of 6H-SiC Layers Grown by Liquid Phase Epitaxy Around Micropipes Using Micro-Raman Scattering Spectroscopy,” Materials Science Forum, Vol. 457–460, 2004, pp. 633–636. [46] Kamei, K., et al., “Solution Growth of Single Crystalline 6H, 4H-SiC Using Si–Ti–C Melt,” Journal of Crystal Growth, Vol. 311, 2009, pp. 855–858.

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Summary

95

[47] Danno, K., et al., “High-Speed Growth of High-Quality 4H-SiC Bulk by Solution Growth Using Si−Ti−C Melt,” Materials Science Forum, Vol. 645–648, 2010, pp. 13–16. [48] Daikoku, H., et al., “Top-Seeded Solution Growth of 4H-SiC Bulk Crystal Using Si-Cr Based Melt,” Materials Science Forum, Vol. 717–720, 2012, pp. 61–64. [49] Kado, M., et al., “High-Speed Growth of 4H-SiC Single Crystal Using Si-Cr Based Melt,” Materials Science Forum, Vol. 740–742, 2013, pp. 73–76. [50] Danno, K., et al., “Diffusion of Transition Metals in 4H-SiC and Trials of Impurity Gettering,” Applied Physics Express, Vol. 5, No. 3, 2012, pp. 031301-1–031301-3. [51] Mitani, T., et al., “4H-SiC Growth from Si–Cr–C Solution Under Al and N Co-doping Conditions,” Materials Science Forum, Vol. 821–823, 2015, pp. 9–13.

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CHAPTER

6 Contents

Epitaxial Growth

6.1 Introduction 6.2 MOCVD of GaN 6.3 Two-Dimensional Nucleation Theory 6.4 BCF Theory 6.5 CVD of 4H-SiC 6.6 CVD Trench Filling of 4H-SiC 6.7 Summary

6.1

Introduction

Epitaxial growth is indispensable for fabricating designed layer structures in both GaN and 4H-SiC power devices (see Section 3.7). This chapter introduces the fundamentals of metalorganic chemical-vapor deposition (MOCVD) of GaN and chemical-vapor deposition (CVD) of 4H-SiC. In addition, the chapter introduces trench-filling epitaxial growth of 4H-SiC as an advanced technology for high-voltage 4H-SiC superjunction (SJ) power devices (see Chapters 8 and 9).

6.2

MOCVD of GaN

MOCVD (synonymously called metalorganic vapor-phase epitaxy [MOVPE], organometallic chemical-vapor deposition [OMCVD], or organometallic vapor-phase epitaxy [OMVPE]) has been the most dominant technique for epitaxial growth of III-V compound semiconductors [1]. The group III precursors used in the case of GaN-based materials are the same as

97

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those used in the case of GaAs- and InP-based materials; namely, trimethylgallium (TMG), triethylgallium (TEG), trimethylaluminum (TMA), and trimethylindium (TMI). MOCVD of GaN-based materials differs from that of GaAs- and InP-based materials in terms of growth temperature due to the difference in the bond energies of group-V precursors; that is, a larger bond energy (about 400 kJ/mol) of ammonia (NH3) compared to the bond energies (about 300 kJ/mol) of arsine (AsH3) and phosphine (PH3) [2, 3] requires a higher growth temperature (about 1,400K) for GaN-based materials compared that (about 1,200K) for GaAs- and InP-based materials. An example of MOCVD system for epitaxial growth of GaN is schematically illustrated in Figure 6.1. Instead of TMG, TEG can be the metalorganic source. In the case of epitaxial growth of AlGaN and InGaN, TMA and TMI sources are also used. For n- and p-type doping, supply lines of n- and ptype dopant gases (e.g., silane [SiH4] and biscyclopentadienyl magnesium [CP2Mg]) are added, respectively, to the MOCVD system. Accurate control of the flow rates of these gases makes it possible to grow epitaxial layers of sophisticated devices. MOCVD of GaN is usually carried out under a nitrogen-rich atmosphere. According to first-principles calculations and thermodynamic analysis, gallium is incorporated as gas-phase gallium atoms on the GaN growth surface, and the migration of these atoms is the rate-limiting process [4]. Experimentally, selective-area GaN MOCVD was used to separate areas with screw dislocations from those without screw dislocations [5]. Interstep distance λ0 of a growth spiral (Figure 6.2) originating from a screw dislocation is given as [6]. λ0 = 19γVm/mΔμ

(6.1)

Mass flow controller H2 NH 3 H2 H2

GaN substrate

rf coil

(CH3)3Ga Exhaust

Figure 6.1

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Schematic illustration of a GaN MOCVD system.

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6.2

MOCVD of GaN

99

Growth direction

λ0

Direction of atomic steps propagating on growth surface Side-surface free energy: γ

h

Screw dislocation

Figure 6.2 Schematic perspective view of a growth spiral originating from a screw dislocation. Narrow arrows show the direction of steps propagating on the growth surface (h: spiral-step height; γ: free energy of side surface of the spiral step).

where γ is the free energy of the side surface of the spiral step, Vm is the molar volume of the growing species, m is the number of spirals at the center (e.g., m =1 in Figure 6.3[a, b]; m = 2 in Figure 6.3[c]), and Δμ is the difference in the chemical potentials of the growth atmosphere and the crystal, given as [7]. Δμ = RT lnα

(6.2)

where R is the ideal gas constant, T is the growth temperature, and α is the supersaturation ratio, defined as

(a)

(b)

(c)

Figure 6.3 Schematic plan views of growth spirals originating from (a, b) one, and (c) two screw dislocations.

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α=σ+1

(6.3)

where σ is the supersaturation as defined in Section 5.2.1. As shown by the symbols in Figure 6.4, spiral- and nucleus-growth rates in areas, respectively, with and without screw dislocations during GaN MOCVD were plotted as a function of α (calculated from [6.1] and [6.2]) by Akasaka et al. [5] Their experimental results are reproduced by the dotted line calculated on the basis of the Burton−Cabrera−Frank (BCF) theory [8], which is described in Section 6.4. On the other hand, the growth rate in the case without screw dislocations is very low. This result means that α was lower than the critical supersaturation ratio αcritical for two-dimensional nucleation, which is explained in Section 6.3.

6.3 Two-Dimensional Nucleation Theory Nucleation becomes dominant when α exceeds αcritical. This section introduces the expression for αcritical based on two-dimensional nucleation theory. The critical nucleation rate is expressed as [9] Jnuc = Zωnucnnuc

(6.3)

where Z is the Zeldovich nonequilibrium factor to account for depletion of the critical nuclei population due to their growth or decomposition, ωnuc is

10

Nucleus growth

Growth rate ( μm/h)

8

Spiral growth BCF theory

6 4 2 0 1

1.05

1.1 1.15 1.2 Supersaturation ratio

1.25

Figure 6.4 Experimental spiral-growth rate as a function of supersaturation ratio obtained by Akasaka et al. [5] (open symbols: experiments; dotted line: theoretical growth rate calculated on the basis of BCF theory) [8].

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6.4

BCF theory

101

the frequency with which a nucleus grows to become supercritical, and nnuc is the critical-nuclei concentration. Equation (6.3) can be rearranged as [9] Jnuc = (2πrnucaνnsn0) (Enuc /4πkTnnuc)0.5 exp(−Ediff/kT) exp(−Enuc/kT) ≈ exp(65) exp(−Enuc/kT) (6.4) where Enuc is the free energy of nucleus formation, nnuc and rnuc are, respectively, the concentration and radius of atoms for a critical nucleus, a is the interatomic distance, ν is the atomic-vibration frequency, ns is the sheet concentration of adatoms, n0 is the sheet concentration of adatom sites, and Ediff is the activation energy for surface diffusion. In the case of a diskshaped nucleus, Enuc is expressed as [9] Enuc = πh1γ2Ω/(kTlnα)

(6.5)

where h1 is height of one Ga−N or Si−C bilayer (Figure 6.5), and is volume of an atom. Combining Equations (6.4) and (6.5) gives the well-known equation for αcritical: αcritical = exp{πh1γ2Ω/[(65−lnJnuc)k2T2]}

6.4

(6.6)

BCF theory

BCF theory assumes that growth is conducted by steps provided from screw dislocations and that surface diffusion is the rate-limiting process [8]. It

h1

Side-surface free energy: γ

Figure 6.5 Schematic illustration of a two-dimensional nucleus with a height of one GaN or SiC bilayer and a side-surface free energy of γ. Arrows show the direction of steps propagating on the growth surface.

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has been applied to vapor phase epitaxy of silicon [10, 11], GaAs under an arsenic-rich atmosphere [12], GaAs under a gallium-rich atmosphere [13], GaAsSb and InGaAs [14], 6H-SiC under a carbon-rich atmosphere [15], and 4H-SiC under a silicon-rich atmosphere [16]. In this section, a simple one-dimensional surface diffusion model based on BCF theory [8] is considered (Figure 6.6). During the diffusion of adatoms toward steps, some of the adatoms reach steps and are incorporated into the crystal, while others re-evaporate into the vapor. When nucleation on terraces does not occur (i.e., α < αcritical—see Section 6.2), the net incoming flux onto the surface should be equal to the diffusion flux toward steps; namely, −Ds(d2ns/dx2) = J−ns/τs

(6.7)

where Ds and ns(x) are, respectively, the surface diffusivity and sheet concentration of adatoms, J is the incoming flux, and τs is the mean residence time of adatoms. If steps are assumed to be perfect sinks for adatoms (i.e., capture probability of adatoms at steps is unity), the boundary condition is expressed as ns(±λ0/2) = ns0

(6.8)

where ns0 is the equilibrium sheet-concentration of adatoms. The solution to (6.7) then becomes

J

ns τs

−D s

d 2n s dx2

h

λ0 2

0

λ0 2

x

Figure 6.6 Schematic illustration of a spiral step treated one-dimensionally. Steps with height h are separated by equal distance λ0.

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6.5

CVD of 4H-SiC

103

ns(x) = Jτs+(ns0−Jτs)[cosh(x/λs)/cosh(λ0/2λs)]

(6.9)

where λs is the surface diffusion length of adatoms, given as [8] λs(x) = (Dsτs)0.5 = a exp[(Edes− Ediff)/kT]

(6.10)

where Edes is the activation energy for desorption. Growth rate Rg is proportional to (σ2/σ1)tanh(σ1/σ) [8], where σ1 = 9.5γa/(mkTλs)

(6.11)

Namely, Rg is proportional to σ2 (i.e., [α − 1]2) when σ > σ1. When λs >> λ0, ns(x) (6.9) becomes a parabola (Figure 6.7). When the flux of adatoms toward steps (i.e., −Ds[dns/dx]) is so small that maximum α at x = 0 is lower than αcritical, two-dimensional nucleation on terraces does not occur. When −Ds(dns/dx) becomes large enough for maximum α to exceed αcritical, on the other hand, two-dimensional nucleation theory (Section 6.3) needs to be applied.

6.5

CVD of 4H-SiC

Sheet concentration of adatoms n s

Large flux toward step

α

αc

Small flux toward step

ns0

1

λ0 2 Figure 6.7

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Supersaturation ratio

In CVD of SiC, silane (SiH4) and propane (C3H8) are often used as precursors, and hydrogen (H2) as a carrier gas. Growth temperature typically ranges from 1,800 to 1,950K. Since conventional cold-wall CVD reactors with horizontal [17] and vertical [18] configurations could not create a uniform temperature distribution, hot-wall CVD reactors have been developed [19]. In the case of hot-wall CVD reactors (Figures 6.8[a−c]), SiC wafers are placed inside gas-flow channels formed in susceptors, which are efficiently

0

λ0 2

x

Distributions of ns(x) and α(x) when λs >> λ0.

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Gas in Gas in

Thermal insulator

Gas in

(a)

(b)

(c)

Figure 6.8 Schematic illustration of a SiC hot-wall CVD system: (a) horizontal, (b) chimney, and (c) planetary reactors.

heated by rf-induction. Since the wafers are heated by radiation from the front side and by conduction from the back side, temperature uniformity is easily established. In the gas phase of SiC CVD, the major chemical reactions are considered as follows [20]: SiH4 ↔ SiH2+H2

(6.12a)

Si2H6 ↔ SiH2+SiH4

(6.12b)

SiH2 ↔ Si+H2

(6.12c)

2H+H2 ↔ 2H2

(6.12d)

C3H8 ↔ CH3+C2H5

(6.12e)

CH4+H ↔ CH3+H2

(6.12f)

C2H5+H 2CH3

(6.12g)

2CH3 ↔ C2H6

(6.12h)

C2H4+H ↔ C2H5

(6.12i)

C2H4 ↔ C2H2+H2

(6.12j)

H3SiCH3 ↔ SiH2+CH4

(6.12k)

H3SiCH3 ↔ HSiCH3+H2

(6.12l)

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6.5

CVD of 4H-SiC

105

Si2 ↔ 2Si

(6.12m)

Si2+CH4 ↔ Si2C+2H2

(6.12n)

SiH2+Si ↔ Si2+H2

(6.12o)

CH3+Si ↔ SiCH2+H

(6.12p)

SiCH2+SiH2 ↔ Si2C+2H2

(6.12q)

For n- and p-type doping, supply lines of n- and p-type dopant gases (e.g., nitrogen and TMA) are added, respectively. This section describes the fundamentals of 4H-SiC CVD. Section 6.6 introduces an advanced CVD technology for trench filling. As described in Section 2.1, step-controlled epitaxy [21] for reproducing the same polytype of epitaxial layer as that of the substrate was proposed by Kuroda et al. In that study, the polytype of SiC layers on SiC (0001) substrates with various misorientations was investigated, and homoepitaxy of 6H-SiC was achieved. Moreover, homoepitaxial growth of 6H-SiC on misoriented 6H-SiC substrates was reported by Kong et al. [22, 23] In the case of 4H-SiC, homoepitaxial growth was similarly demonstrated [24]. It has been reported that steps appear on the surface of a misoriented substrate. Since these steps resemble spiral steps originating from a screw dislocation (Section 6.2), the two-dimensional nucleation theory (Section 6.3) and BCF theory (Section 6.4) can be similarly applied to deal with surface diffusion on the stepped surface of a misoriented substrate [10−16]. When λs > λ0, on the other hand, adatoms migrate and reach steps (Figure 6.9[b]). The dominant steps of misoriented 4H-SiC (0001) are two or four bilayers high [25], leading to unique determination of incorporation sites A, B, and C at the steps and replication of the substrate polytype in the epitaxial layer. According to a simulation of surface mass fluxes in the SiH4−C3H8−H2 growth system [17, 26], the surface reaction of silicon adatoms with acetylene (C2H2), namely, 2Si+C2H2 ↔ 2SiC+H2

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(6.13)

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B C B A

B C B A

A B C B A

C A B C B A

B C A B C B A

C A B C B A

A B C B A

B C B A

B C B A

B C B A

B C B A

B C B A

B C B A

B C B A

B C B A

C B C B A

B C B A B C B A

B C B A B C B A

B C B A B C B A

A C B C B A

B A C B C B A

A C B C B A

C B C B A

B C B A

B C B A

B C B A B C B A

B C B A B C B A

B C B A B C B A

B C B A B C B A

B C B A

B C B A

(a) λs > λ0/2, Rg becomes independent of λ0 {i.e., (2h/n0) [J−(ns0/ τs)]}. According to [27], Rg depends little on θ when θ = 4°−45°, but it decreases when θ = 1°. λs is thus estimated to be comparable to or less than h/(2 tan1°) (i.e., 14.4 nm for two-bilayer-high steps and 28.9 nm for fourbilayer-high steps). If n0 is assumed to be equal to the concentration of sites of silicon adatoms on the surface (1.21 × 1015 cm−3), J−(ns0/τs) can be calculated from (6.15). Dependences of J−(ns0/τs) on the C/Si ratio calculated from (6.15) for λs of 12−36 nm are shown in Figure 6.10. When λs = 12−18 nm in the case of two-bilayer-high steps and λs = 24−36 nm in the case of four-bilayer-high steps, the least-squares fit of J−(ns0/τs) matches those of

3

(a) h = 0.504 nm

2

2.0× 10 15 r −1.2×10 14 (λs = 12 nm)

J −ns0 /τs (× 10 15 cm−2s−1)

1 1.6 ×10 15 r −1.0 ×10 14 (λs = 18 nm)

0 −1 (b)h = 1.01 nm 0.6

1.0× 10 15 r −0.6 ×10 14 (λ s = 24 nm)

0.4 0.2

0.8 ×10 15 r −0.5 ×10 14 (λs = 36 nm)

0 −0.1 0

0.2

0.4 C/Si ratio r

0.6

0.8

Figure 6.10 Dependences of J−(ns0/τs) on the C/Si ratio calculated from (6.15) for λs of 12−36 nm. Experimental results denoted by error bars are taken from [27]. Lines and corresponding equations show the least-squares fit to the experimental results.

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θ = 1° −45°. This λs range agrees with the above estimated values (i.e., 14.4 and 28.9 nm). The absolute value of the intercept with the vertical axes in Figure 6.10(a, b) give an equilibrium desorption flux of C2H2 molecules, ns0/ τs, of (0.5−1.2) × 1014 cm−2s−1. This value corresponds to the equilibrium vapor pressure of C2H2 molecules ( PC H e ) of (0.4−1.0) × 10−4 Pa, which is 2 2 obtained from Knudsen’s equation [14], namely, ns0/τs = PC H e /(2πmC 2 2

0.5

H kT) 2 2

(6.16)

where mC2 H 2 is the mass of a C2H2 molecule. In two-dimensional nucleation mode, where nucleation on terraces occurs (Section 6.3), under a silicon-rich atmosphere, the equilibrium vapor pressure of silicon adatoms must be similar to the incoming pressure of silicon; namely, the supersaturation ratio for silicon (αSi) equals unity [12]. Since the supersaturation ratio for carbon (αC) reaches a maximum at the center of a terrace (i.e., x = 0) (Figure 6.7), the maximum supersaturation ratio for SiC is obtained from (6.9) as αmax ≡ αSi αC(x = 0)≈ 1+(λ0n0Rg/4hλs)(τs/ns0)tanh(λ0/4λs)

(6.17)

Nucleation on terraces becomes dominant when αmax exceeds αcritical (see Section 6.3). For a disk-shaped nucleation per second on a 10×10-nm2 area, (6.6) becomes αcritical = exp{πh1γ2Ω/[(65−ln1012)k2T2]}

(6.18)

where h1 is height of one Si-C layer (0.252 nm) and Ω is the volume of the Si-C pair (2.07 × 10−23 cm3). The free energy of the side surface of a twodimensional nucleus under a silicon-rich atmosphere is assumed to be 2.22 J/m2, which is the calculated γ for silicon-terminated 3C-SiC (111) [28]. From (6.17) and (6.18), the off-angle dependence of critical growth rate (Rc) for mode transition between step-flow growth and two-dimensional nucleation is calculated at T = 1,773K (Figure 6.11). It is confirmed that the range of Rc, originating from variation in determining λs (Figure 6.10), does not depend on h (h = 0.504 or 1.01 nm). It is also confirmed that the experimental data for step-flow growth in [27] are in the bottom-right region under the curve calculated using ns0/τs and λs values obtained from Figure 6.10. According to (6.17), Rc increases with increasing ns0/τs. According to (6.13) and (6.16), an increase in ns0/τs, namely, an increase in PC2 H 2 e , is achieved by reducing the SiH4 flow rate. To maintain the C/Si ratio at less than unity (i.e., a silicon-rich atmosphere), however, the C3H8 flow rate

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6.6

CVD Trench Filling of 4H-SiC

10 2

Growth rateR g (μm/h)

ns0 /τs =

10 1

109

1.0 × 10 14 cm−2s−1 (λs = 18 nm, h = 0.504 nm) 0.5 × 10 14 cm−2s−1 (λs = 36 nm, h = 1.01 nm)

two-dimensional nucleation ns0 /τ s =

10 0

1.2 × 10 14 cm−2s−1 (λs = 12 nm, h = 0.504 nm) 0.6 × 10 14 cm−2s−1 (λs = 24 nm, h = 1.01 nm)

step flow

10 −1 0

0.2

0.4

0.6

0.8

1

Off-angle from (0001) θ (degree)

Figure 6.11 Off-angle dependence of the critical growth rate for mode transition between step-flow growth (bottom-right region) and two-dimensional nucleation (top-left region) calculated with the equilibrium desorption flux and surface diffusion length of C2H2 molecules obtained from Figure 6.10. Data denoted by an error bar is taken from [27].

must be limited, resulting in a lower Rc. The calculated curves in Figure 6.11 are thus considered to be close to the practical limit at T = 1,773K.

6.6

CVD Trench Filling of 4H-SiC

As shown in Figure 2.18, the breakdown voltage (BV) of a p+n junction with an n-type drift layer is equal to EcriticalWD/2 (Figure 6.12[a] and the dashed line in Figure 6.12[c]). In the case of a p+n junction with alternating n- and p-type regions within a drift layer (a so-called SJ diode) [29], the same BV can be realized with a drift layer with half the thickness (i.e., WD/2) (Figure 6.12[b] and the solid line in Figure 6.12[c]) because ND in (2.2) becomes effectively zero. SJ structures thus improve the trade-off relationship between BV and specific resistance of the ideal drift layer Rideal (Section 2.7). The first 4H-SiC SJ diode with BV = 1.5 kV was fabricated by multiepitaxy [30], by which multiple n-type epitaxial layers are grown over patterned ion implanted p-type regions to create alternating p/n columns. In the case of a silicon SJ structure, the p-type regions merge due to controlled diffusion of p-type dopant (i.e., boron) during epitaxial growth [31]. However, this diffusion is not feasible in a SiC SJ structure due to the very low diffusivity of aluminum or very large diffusivity of boron [30]. Refilling

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E critical

O

n p n p n p

Drift layer

n-type

WD

n-type

Superjunction

2 +

n type

WD +

Substrate

n type

x

(a)

(b)

(c)

Figure 6.12 Drift layers consisting of (a) an n-type semiconductor and (b) a superjunction structure, together with (c) their electric-field distributions.

an epitaxial layer into 4H-SiC trenches is therefore highly practicable for 4H-SiC SJ power devices with BV > 2 kV [32, 33]. In a conventional SiH4:C3H8:H2 CVD system [33–37], the use of a relatively high pressure (up to 38 kPa [38]) reduces the mean free path of growing species comparable to the size of microtrenches, thereby allowing the continuous-fluid approximation to be used [39]. In the case of a large growth rate on a bare wafer (R0), the isoconcentration contours of growing species close to a nonplanar surface are parallel to the surface, as shown by the dotted lines in Figure 6.13(a). Fluxes toward the mesa top and the trench bottom, respectively, become large and small, resulting in morphological instability. When R0 is small (e.g., due to re-evaporation of growing species at a relatively high temperature [1,923K] [33]) and the radius of curvature (r) is small, the shape of the isoconcentration contours changes due to the two-dimensional Gibbs–Thomson effect [40, 41], namely, Ce(r) = Ce(∞) exp[γVm/RTr]

(6.19)

where Ce(r) is the equilibrium gas-phase concentration of the growing species in contact with a curved surface with radius r (Figure 6.13[b]). Note that the sign of r depends on whether the mesa surface is convex upward (r > 0) or convex downward (r < 0). Note also that (6.19) becomes

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6.7

Summary

r

111

Solid

r

Solid

Solid

Solid

(a)

(b)

Figure 6.13 Schematic cross sections of nonplanar growing surfaces when the growth rate and radius of curvature (r) are (a) large and (b) small. Dotted lines and solid arrows, respectively, show isoconcentration contours and direction of fluxes of growing species in the vapor.

Ce(r) = Ce(∞) exp[2γVm/RTr]

(6.20)

under the three-dimensional Gibbs–Thomson effect [42]. To further reduce R0, hydrogen chloride (HCl) gas has been added to the procedure for conventional CVD growth [43−45]. The resultant fluxes toward the mesa top and the trench bottom, respectively, become small and large, resulting in a uniform surface. In the case of shallow (< 5 μm-deep) trenches, dependences of experimentally measured growth rates (both at the mesa top and on the trench bottom) on trench pitch were reproduced with (6.19) [41, 46]. Experimentally, by overcoming the strong impact of slight misalignment of trench-direction from the [ 1120 ] direction, 25-μmdeep n-type 4H-SiC trenches were refilled with p-type 4H-SiC [47].

6.7

Summary

This chapter explains the fundamentals of GaN MOCVD and 4H-SiC CVD on the basis of the two-dimensional nucleation and BCF theories. In addition, the chapter explains the trench-filling epitaxial growth of 4H-SiC as an advanced technology for fabricating SJ structures. To apply this trench filling to 4H-SiC SJ power devices, however, developing techniques for evaluating distribution of p-type dopant is considered indispensable.

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References [1] Dupuis, R. D., “III-V Semiconductor Heterojunction Devices Grown by Metalorganic Chemical Vapor Deposition,” IEEE Journal of Selected Topics in Quantum Electronics, Vol. 6, No. 6, 2000, pp. 1040–1050. [2] Simka, H., et al., “Computational Chemistry Predictions of Reaction Processes in Organometallic Vapor Phase Epitaxy,” Progress in Crystal Growth and Characterization of Materials, Vol. 35, No. 2–4, 1997, pp. 117–149. [3] Davidson, D. F., et al., “A Pyrosis Mechanism for Ammonia,” International Journal of Chemical Kinetics, Vol. 22, No. 5, 1997, pp. 513–535. [4] Sekiguchi, K., et al., “Thermodynamic Considerations of the Vapor Phase Reactions in III-Nitride Metal Organic Vapor Phase Epitaxy,” Japanese Journal of Applied Physics, Vol. 56, 2017, pp. 04CJ04-1–04CJ04-4. [5] Akasaka, T., Y. Kobayashi, and M. Kasu, “Step-Free Hexagons Grown by Selective-Area Metalorganic Vapor Phase Epitaxy,” Applied Physics Express, Vol. 2, No. 9, 2009, pp. 091002-1–091002-3. [6] Cabrera, N., and M. M. Levine, “On the Dislocation Theory of Evaporation of Crystals,” Philosophical Magazine, Vol. 1, No. 5, 1956, pp. 450–458. [7] Nishinaga, T., “Progress in Art and Science of Crystal Growth and Its Impacts on Modern Society,” Japanese Journal of Applied Physics, Vol. 54, 2015, pp. 050101-1–050101-12. [8] Burton, W. K., N. Cabrera, and F. C. Frank, “The Growth of Crystals and the Equilibrium Structure of Their Surfaces,” Proceedings of the Royal Society of London A, Vol. 243, No. 866, 1951, pp. 299–358. [9] Hirth, J. P., and G. M. Pound, Condensation and Evaporation, Nucleation and Growth Kinetics, Oxford: Pergamon, 1963, Chapter D. [10] Abbink, H. C., R. M. Broudy, and G. P. McCathy, “Surface Processes in the Growth of Silicon on (111) Silicon in Ultrahigh Vacuum,” Journal of Applied Physics, Vol. 39, No. 10, 1968, pp. 4673–4681. [11] Kasper, E., “Growth Kinetics of Si-Molecular Beam Epitaxy,” Applied Physics A, Vol. 28, No. 2, 1982, pp. 129–135. [12] Nishinaga, T., and K.-I. Cho, “Theoretical Study of Mode Transition Between 2d-Nucleation and Step Flow in MBE of GaAs,” Japanese Journal of Applied Physics, Vol. 27, No. 1, 1988, pp. L12–L14. [13] Nishinaga, T., and T. Suzuki, “The Role of Step Kinetics in MBE of Compound Semiconductors,” Journal of Crystal Growth, Vol. 115, No. 1–4, 1991, pp. 395–405. [14] Mochizuki, K., and T. Nishinaga, “MBE Growth of GaAs1-xSbx and InyGa1-yAs and Application of BCF Theory to Study the Alloy Composition,” Japanese Journal of Applied Physics, Vol. 27, No. 9, 1988, pp. 1585–1592. [15] Kimoto, T., and H. Matsunami, “Surface Kinetics of Adatoms in Vapor Phase Epitaxial Growth of SiC on 6H-SiC{0001} Vicinal Surfaces,” Journal of Applied Physics, Vol. 75, No. 2, 1994, pp. 850–859.

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[16] Mochizuki, K., “Theoretical Consideration of Step-Flow and Two-Dimensional Nucleation Modes in Homoepitaxial Growth of 4H-SiC on (0001) Vicinal Surfaces Under Silicon-Rich Condition,” Applied Physics Letters, Vol. 93, 2008, pp. 222108-1–222108-3. [17] Burk, A., and L. B. Rowland, “Homoeptaxial VPE Growth of SiC Active Layers,” Physica Status Solidi B, Vol. 202, No. 1, 1997, pp. 263–279. [18] Rupp, R., et al., “Silicon Carbide Epitaxy in a Vertical CVD Reactor: Experimental Results and Numerical Process Simulation,” Physica Status Solidi B, Vol. 202, No. 1, 1997, pp. 281–304. [19] Kordina, O., et al., “Growth of SiC by “Hot-Wall” CVD and HTCVD,” Physica Status Solidi B, Vol. 202, No. 1, 1997, pp. 321–334. [20] Nishizawa, S., and M. Pons, “Growth and Doping Modeling of SiC-CVD in a Horizontal Hot-Wall Reactor,” Chemical Vapor Deposition, Vol. 12, No. 8–9, 2006, pp. 516–522. [21] Kuroda, N., et al., “Step-Controlled VPE Growth of SiC Single Crystals at Low Temperatures,” Solid State Devices and Materials, Tokyo, Aug. 25–27, 1987, pp. 227–230. [22] Kong, H. S., et al., “Growth, Doping, Device Development and Characterization of CVD Beta-SiC Epilayers on Si(100) and alpha-SiC(0001),” MRS Proceedings, Vol. 97, 1987, pp. 233–246. [23] Kong, H. S., J. T. Glass, and R. F. Davis, “Chemical Vapor Deposition and Characterization of 6H-SiC Thin Films on Off-Axis 6H-SiC Substrates,” Journal of Applied Physics, Vol. 64, No. 5, 1988, pp. 2672–2679. [24] Itoh, A., et al., “High-Quality 4H-SiC Homoepitaxial Layers Grown By Step-Controlled Epitaxy,” Applied Physics Letters, Vol. 65, No. 11, 1994, pp. 1400–1402. [25] Kimoto, T., et al., “Step Bunching Mechanism in Chemical Vapor Deposition of 6H- and 4H-SiC{0001},” Journal of Applied Physics, Vol. 81, No. 8, 1997, pp. 3494–3500. [26] Meziere, M., et al., “Modeling and Simulation of SiC CVD in the Horizontal Hot-Wall Reactor Concept,” Journal of Crystal Growth, Vol. 267, No. 3–4, 2004, pp. 436–451. [27] Saito, H., and T. Kimoto, “4H-SiC Epitaxial Growth on SiC Substrates with Various Off-Angles,” Materials Science Forum, Vol. 483–485, 2005, pp. 89–92. [28] Pearson, E., et al., “Computer Modeling of Si and SiC Surfaces and Surface Processes Relevant to Growth from the Vapor,” Journal of Crystal Growth, Vol. 70, No. 1–2, 1984, pp. 33–40. [29] Fujihira, T., “Theory of Semiconductor Superjunction Devices,” Japanese Journal of Applied Physics, Vol. 36, No. 10, 1997, pp. 6254–6262. [30] Kosugi, R., et al., “First Experimental Demonstration of SiC Superjunction (SJ) Structure by Multiepitaxial Method,” International Symposium on Power Semiconductor Devices and ICs, Waikoloa, June 2014, pp. 346–349.

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[31] Lorenz, L., et al., “COOLMOS—A New Milestone in High Voltage Power MOS,” International Symposium on Power Semiconductor Devices and ICs, Toronto, May 1999, pp. 3–10. [32] Kosugi, R., “Development of SiC Superjunction (SJ) Device by Deep TrenchFilling Epitaxial Growth,” Materials Science Forum, Vol. 740–742, 2013, pp. 785–788. [33] Kojima, K., et al., “Filling of Deep Trench by Epitaxial SiC Growth,” Materials Science Forum, Vol. 740–742, 2013, pp. 793–796. [34] Takeuchi, Y., et al., “SiC Migration Enhanced Embedded Epitaxial (ME3) Growth Technology,” Materials Science Forum, Vol. 527–529, 2006, pp. 251–254. [35] Sugiyama, N., et al., “Growth Mechanism and 2d Aluminum Dopant Distribution of Embedded Trench 4H-SiC Region,” Materials Science Forum, Vol. 600– 603, 2009, pp. 171–174. [36] Schöner, A., et al., “In Situ Nitrogen and Aluminum Doping in Migration Enhanced Embedded Epitaxial Growth of 4H-SiC,” Materials Science Forum, Vol. 600–603, 2008, pp. 175–178. [37] Negoro, Y., et al., “Embedded Epitaxial Growth of 4H-SiC on Trenched Substrates and pn Junction Characteristics,” Microelectronics Engineering, Vol. 83, No. 1, 2006, pp. 27–29. [38] Ji, S. Y., et al., “Influence of Growth Pressure on Filling 4H-SiC Trenches by CVD Method,” Japanese Journal of Applied Physics, Vol.55, 2016, pp. 01AC04-1–01AC04-4. [39] Mochizuki, K., et al., “Analysis of Trench-Filling Epitaxial Growth of 4H-SiC Based on Continuous Fluid Approximation Including Gibbs–Thomson Effect,” Materials Science Forum, Vol. 897, 2017, pp. 47–50. [40] Krishnamachari, B., “Gibbs–Thomson Formula for Small Island Sizes: corrections for High Vapor Densities,” Physical Review B, Vol. 54, No. 12, 1996, pp. 8899–8907. [41] Mochizuki, K., et al., “Numerical Analysis of the Gibbs–Thomson Effect on Trench-Filling Epitaxial Growth of 4H-SiC,” Applied Physics Express, Vol. 9, 2016, pp. 03560-1–03560-4. [42] McDonald, J. E., “Homogeneous Nucleation of Supercooled Water Drops,” Journal of Meteorology, Vol. 10, 1953, pp. 416–433. [43] J., S. Y., et al., “Filling 4H-SiC Trench Towards Selective Epitaxial Growth by Adding HCl to CVD Process,” Applied Physics Express, Vol. 8, 2015, pp. 065502-1–065502-4. [44] Yamauchi, S., et al., “200 V Super Junction MOSFET Fabricated by High Aspect Ratio Trench Filling,” International Symposium on Power Semiconductor Devices and ICs, Naples, June 2006, pp. 1–4. [45] Hara, K., et al., “150 mm Silicon Carbide Selective Embedded Epitaxial Growth Technology by CVD,” Materials Science Forum, Vol. 897, 2017, pp. 43–46. [46] Mochizuki, K., et al., “First topography simulation of SiC-chemical-vapordeposition trench filling, demonstrating the essential impact of the Gibbs−

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Thomson effect,” International Electron Devices Meeting, San Francisco, December 4–6, 2017, pp. 788–791. [47] Kosugi, R., et al., “Strong Impact of Slight Trench Direction Misalignment from [1120 ] on Deep Trench Filling Epitaxy for SiC Superjunction Devices,” Japanese Journal of Applied Physics, Vol. 56, 2017, pp. 04CR05-1–04CR05-4.

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CHAPTER

7 Contents

Fabrication Processes

7.1 Introduction 7.2 Etching 7.3 Ion Implantation 7.4 Diffusion 7.5 Oxidation 7.6 Metallization 7.7 Passivation 7.8 Summary

7.1

Introduction

This chapter introduces the basic aspects of the processing steps for fabricating GaN and 4H-SiC power devices, excluding epitaxial growth (already described in Chapter 6). Sections 7.3 and 7.4 describing, respectively, ion implantation and diffusion, cover mainly topics associated with 4H-SiC. Sections 7.2 and 7.5– 7.7, dealing, respectively, with etching, oxidation, metallization, and passivation comparatively describe GaN and 4H-SiC device processing.

7.2

Etching

Since both GaN and 4H-SiC are extremely inert materials in regard to conventional wet chemical etching, they are usually etched with a highdensity plasma, such as magnetron reactive ions, an electron-cyclotron-resonance plasma, or an inductively coupled plasma (ICP). Among these techniques, ICP etching achieves the highest etching rate; for example, the first ICP etching of GaN in a chlorine/hydrogen/argon

117

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.

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plasma resulted in an etching rate of about 0.7 μm/min [1, 2]. ICP plasmas are formed by an inductive coil to which RF (radio frequency) power is applied (Figure 7.1). Ion energy and plasma density can be decoupled, resulting in uniform density and energy distributions, even with low ion and electron energies. Consequently, ICP etching can produce low damage while maintaining a high etching rate. Anisotropic etching is achieved by applying an RF bias to the samples being etched. This section describes ICP etching and wet chemical etching of GaN and 4H-SiC in terms of reported results. 7.2.1

ICP Etching

Halogen- and methane-based ICP plasmas have been used for ICP etching of GaN [3−8]. For halogen-based plasmas, etch rates are limited by the volatility of the group-III halogen etch product. Among halogen-based plasmas, chlorine-based plasmas typically yield high etching rate. For methane-based plasmas, on the other hand, the etching rate is much lower. Although these techniques for ICP etching can minimize plasma damage, their influence on device characteristics cannot be neglected. According to Ohta et al., the damage was removed by thermal treatment at 850°C [9]. For the ICP etching of SiC, fluorine-, chlorine-, and bromine-based plasmas have been used [10−14]. Fabrication of 25-μm-deep 4H-SiC trenches has also been demonstrated [15] for superjunction structures (Chapters 6, 8, and 9). Showerhead gas distribution

RF power supply

Plasma

Powered electrode

13.56 MHz

Figure 7.1

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Schematic illustration of an ICP etcher.

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Etching

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7.2.2 Wet Chemical Etching Wet chemical etching of semiconductors in general involves oxidation of the semiconductor surface and subsequent dissolution of the resulting oxides. Oxidation requires holes that can be supplied either chemically or via an electrochemical circuit [16]. 7.2.2.1

Chemical Eching

With respect to the chemical etching of GaN, gallium- and nitrogen-polar surfaces reportedly showed different etching characteristics; that is, only nitrogen-polar surfaces (of both epitaxial GaN layers [17] and bulk GaN [18]) were etched in aqueous KOH. The mechanism of etching a nitrogenpolar GaN surface was interpreted as [19] 2GaN+3H2O → Ga2O3+2NH3

(7.1)

where KOH works as a catalyst and a solvent for Ga2O3. Unlike a nitrogen-polar surface, a gallium-polar (0001) surface is selectively attacked and shows hexagonal etch pits in hot (470−490K) phosphoric acid [20−24]. With respect to the chemical etching of SiC, on the other hand, etching in phosphoric acid is impractical because of the low etching rate. Instead, molten KOH has been used to oxidize SiC and remove the formed oxide [25]. However, contamination of potassium must be avoided, especially during SiC oxidation [26]. Moreover, care must be taken to create dislocation pits because the KOH-etching rate becomes higher around the intersection points of dislocations with a surface. As for wet etching after trench structures have been fabricated, the use of 25% tetramethylammonium hydride (TMAH) at 358K was reportedly effective for obtaining smooth GaN ( 1 100 ) planes [27]. TMAH is widely used in lithography as a basic solvent in the development of an acidic photoresist and is free from the contamination by alkaline metal. 7.2.2.2

Photoelectrochemical Etching

Photoelectrochemical etching (PEC) is independent of crystal polarity of GaN [28]. The first PEC etching of GaN used a He-Cd laser (with a wavelength of 325 nm) in an aqueous KOH solution (with an etching rate of 400 nm/min) or in an aqueous HCl solution (with an etch rate of 40 nm/min) [29]. PEC etching has also been used in the case of AlGaN/GaN heterostructures. For example, in the case of Al0.2Ga0.8N/GaN heterojunction field-effect transistors, wet gate-recess etching using a 35-mW/cm2 mercury arc lamp and 0.5-mol% KOH was demonstrated. In that demon-

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stration, a DC bias of 2V was applied between the mesa-etched surface of the edge region of a two-inch wafer and the platinum grid (Figure 7.2) [30]. In the case of a SiC p-n junction, p-type SiC can be selectively etched without ultraviolet light illumination because of the lack of holes in n-type SiC [31, 32]. Etching of n-type SiC, on the other hand, is possible under the illumination of ultraviolet light with above-bandgap photons [33−37]. Photogenerated holes are accumulated at the electrolyte (e.g., KOH solution)/ n-type SiC interface, while holes are depleted at the electrolyte/p-type SiC interface.

7.3

Ion Implantation

As described in Sections 3.1 and 3.7, GaN and 4H-SiC power devices are often made from n-type starting material, and the use of p-type dopant implantations for active regions is avoided in the case of p+n diodes. In the case of unipolar power devices, on the other hand, aluminum-ion implantation into 4H-SiC is frequently used; however, magnesium-ion implantation into GaN is not much used because of a very low activation ratio (Section 3.7). Boron-ion implantation into 4H-SiC is not much used either, for the following reason. An energetic ion penetrating through a 4H-SiC (or GaN) crystal generates a collision cascade consisting of silicon vacancies VSi and carbon vacancies VC (or gallium vacancies VGa and nitrogen vacancies VN) as well as silicon interstitials ISi and carbon interstitials IC (or gallium interstitials IGa and nitrogen interstitials IN). Post-implantation annealing is

KOH solution

U lig ltr ht avi o

le t

Platinum grid

Figure 7.2 Schematic illustration of a PEC etching apparatus used for etching an AlGaN/ GaN heterostructure [30].

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121

thus needed, and redistribution of boron in SiC during annealing becomes very large (Sections 6.6 and Section 7.4). During post-implantation annealing, surface degradation occurs. A SiN cap is conveniently used for post-implantation annealing of implanted GaN around about 1,500K [38]. In the case of SiC, on the other hand, a carbon cap is frequently employed for post-implantation annealing around 1,950K [39]. As for n-type dopant implantations, silicon-ion implantation into GaN and nitrogen-ion and phosphorus-ion implantations in 4H-SiC have been frequently used. 7.3.1

Ion Implantation into GaN

Magnesium-ion implantation has been attempted using a high-quality ntype GaN epitaxial layer grown on a freestanding GaN substrate, and p-type conversion was confirmed by the following three experimental results [40]. 1. Low-temperature photoluminescence spectra of the layer showed magnesium-acceptor related emissions. 2. Vertical diodes showed clear rectifying I-V characteristics and emitted ultraviolet and blue-green light when forward-biased. 3. Positive Hall coefficients were also observed. However, increasing the activation ratio of magnesium acceptors is still a challenge. Silicon-ion implantation has been used for fabricating AlGaN/GaN high-electron mobility transistors (HEMTs) [41] to reduce metal/GaN contact resistance and fabricate a lightly doped channel region. It has also been applied to p-type GaN to fabricate normally-off GaN metal-insulatorsemiconductor field-effect transistors (MISFETs) with a threshold voltage of +3.4V [42]. 7.3.2

Aluminum-Ion Implantation into 4H-SiC

In the case of boron-ion implantation into silicon, scatter-in channeling [43] (or so-called paradoxical profile broadening [44]) was observed during high-tilt-angle implantation (e.g., 7° for [100] Si) through a randomized surface layer. In the scatter-in process, some high-energy ions, which move in a random direction after crossing the surface layer, are scattered in channeling directions and penetrate deeper into the undamaged underlying crystal. When the tilt angle is 0°, the depth of the as-implanted profile decreases with the increasing thickness of the surface oxide because a well-collimated ion beam is scattered by the amorphous oxide layer (i.e.,

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amorphization-suppressed channeling). On the other hand, at higher tilt angles and at certain energies, the as-implanted profile becomes deeper with increasing oxide thickness because of scatter-in channeling [45]. In the case of aluminum-ion implantation into 4H-SiC, the substrate is usually misoriented from (0001) by 4°−8° to achieve step-flow epitaxial growth [46]. Thus, scatter-in channeling of aluminum has such a high probability that the effect of a surface oxide on channeling becomes important. Moreover, due to the negligible diffusivity of aluminum in 4H-SiC, multiple-energy aluminum implantations have to be used to form box-like profiles. The sequence of implantations (i.e., increasing or decreasing order of implantation energy) is thus important in determining whether the scatterin channeling or amorphization-suppressed channeling dominates the boxlike profiles. Mochizuki et al. used a 4H-SiC wafer (misoriented by 8° from (0001) toward [ 1120 ]) with and without a 35-nm-thick SiO2 layer for fivefold aluminum implantation at room temperature to achieve 0.3-μm-deep boxlike profiles with a mean plateau concentration of 1 × 1019 cm−3 [47]. Implantation energies (keV) and corresponding doses (×1013 cm−2) were 220/10, 160/5, 110/7, 70/6, and 35/3. The implantation without the SiO2 layer in a decreasing energy order resulted in the least-extended tail in the aluminum-concentration profiles. The tail of the profiles for implantation with the SiO2 layer extends deeper than that for implantation without the SiO2 layer. This difference resulted from the scatter-in channeling. In the case of increasing order of implantation energy, on the other hand, little difference between the tails of the profiles for implantations with and without the SiO2 layer was observed. Thus, the effect of amorphization-suppressed channeling was less than that of scatter-in channeling. To analytically express a wide selection of implanted ion profiles in 4HSiC, Pearson frequency distribution functions [48] have been successfully applied [49]. For heavy ions such as aluminum, however, large channeling tails of distributions deviate from the single-Pearson distribution functions [49–51]. The dual-Pearson distribution, which is a weighted sum of two Pearson distribution functions [48], has thus been used to model the randomly scattered portion and the channeled portion of the profile [52]. The depth profile of aluminum, N(x), is represented by N(x) = D1f1(x)+D2f2(x)

(7.2)

fi(x) = Ki[1+{(x–Rpi)/Ai–ni/ri}2]−mi exp[–ni arctan{(x–Rpi)/Ai–ni/ri}2] (i = 1, 2) (7.3) where f1 and f2 are, respectively, normalized Pearson type IV distribution functions for the randomly scattered and channeled components of the

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123

profile, and D1 and D2 are the doses represented by each Pearson function. For Pearson type IV distribution functions, K1 and K2 are normalized constants. Rp1 and Rp2 are projected ranges, and n1, n2, r1, r2, A1, A2, m1, and m2 are parameters related to the range stragglings ΔRp1 and ΔRp2, skewnesses γ1 and γ2, and kurtoses β1 and β2, as follows: ri = –(2+1/b2i)

(7.4a)

ni = –rib1i/(4b0ib2i–b1i2)0.5

(7.4b)

mi = –1/(2b2i)

(7.4c)

Ai = mirib1i/ni

(7.4d)

b0i = –ΔRpi2(4βi–3γi2)C

(7.4e)

b1i = –γiΔRpi(βi+3)C

(7.4f)

b2i = –(2βi–3γi2–6)C

(7.4g)

C = 1/[2(5βi–6γi2–9)] (i = 1, 2)

(7.4h)

Dose ratio R is defined as R = D1/(D1+D2)

(7.5)

To avoid arbitrariness of Rp2 [53], Rp2 was set equal to Rp1 (Figure 7.3). Comparing the dual-Pearson parameters with the single-Pearson parameters shows that the dependences of Rp in the case of implantation without the SiO2 layer, ΔRp1, and γ1 are almost the same as those stated in two reports [49, 50], but they slightly differ from those stated in another report [51]. Although β values of the reported single-Pearson model are not shown to avoid complexity, the obtained relationship between β1 and r1 in Figure 7.3(e), β1 = 1.19β1o

(7.6a)

β1o = [39γ12+48+6(γ12+4)1.5]/(32–γ12)

(7.6b)

is very similar to the following reported relationship [51]: β = 1.30βo

moch-ch07.indd 123

(7.6c)

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Vertical GaN and SiC Power Devices

Projected range Rp (μm)

124

1

(a)

[47]

[49] [50]

Without SiO2

−1

10

With SiO2

10−2

(b) 0.8

Skewness γ Range straggling Δ Rp (μm) Dose ratio R

Without SiO2 0.6 0.4

With SiO2

0.2 0

(c)

Δ Rp2 10−1

Δ Rp1 −2

10

(d) 4

γ2

2

γ1

0 −2

Kurtosis β

(e)

βjo = [39γ j2 + 48 + 6 (γj2 + 4)1.5]/(32 − γj2)

103

(j = 1, 2) 102

β2 = 2.95 β2o β1 = 1.19 β1o

101 1 30

100

300

Energy (keV)

Figure 7.3 Dual-Pearson parameters as a function of implantation energy. (Projected ranges, range stragglings, and skewnesses from previous reports are also shown for comparison.)

In Figure 7.3(a), Rp for implantations with the SiO2 layer is smaller than that for implantations without the SiO2 layer. This result is due to the existence of the SiO2 layer during implantation. On the other hand, in Figure 7.3(b), compared to R for implantations without the SiO2 layer, R for implantations with the SiO2 layer becomes smaller, (i.e., more aluminum ions channel, owing to the scatter-in channeling). It should be noted that in the case of aluminum implantations with the 35-nm-thick SiO2 layer, R monotonically increases under the following conditions [54]:  Dose of 1 × 1014 cm−2 and energy exceeding 300 keV;  Dose of 1 × 1015 cm−2 or more and energy of 35 keV or more. This result suggests that under either condition, the influence of the amorphization-suppressed channeling [43] might also increase.

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7.4

Diffusion

125

Lateral range straggling can be extracted by expressing the lateral-concentration profiles as a one-dimensional dual-Pearson-distribution function multiplied by another distribution function (e.g., a Gaussian function). Such a two-dimensional model should contribute to efficiently simulating the current-voltage characteristics of 4H-SiC power devices [55, 56]. In addition to the dual-Pearson approach, Monte-Carlo simulation using binarycollision approximation (BCA) [57, 58] has also been used. Asymmetric lateral straggling due to a surface misorientation of a SiC substrate was shown with BCA simulation [59]. 7.3.3

Nitrogen-Ion and Phosphorus-Ion Implantations into 4H-SiC

Concentration profiles of implanted nitrogen and phosphorus ions have been analyzed by taking a single-Pearson approach [49, 60–62]. In Figure 7.4, obtained Rp and ΔRp are shown as a function of implantation energy in nitrogen and phosphorus ion implantation into SiC. Both nitrogen and phosphorus atoms show negligible diffusion during post-implantation annealing [63].

7.4

Diffusion

Negligible diffusion for implanting silicon and magnesium atoms into GaN and annealed at 1,450°C [64] and for aluminum atoms implanted into 4HSiC annealed at 1,700°C [65] has been observed by secondary ion mass spectrometry (SIMS). In contrast, the mechanism of boron diffusion in SiC has been considered to be very complicated. However, its understanding should become more important because the use of boron diffusion for fabricating 4H-SiC metal-insulator-semiconductor field-effect transistors was recently reported to reduce the interface state density near the conduction band edge of 4H-SiC [66]. 7.4.1

Historic Background of Boron Diffusion in SiC

The first analysis of boron diffusion in SiC was based on a boron-vacancy model of 6H-SiC [67]. Detailed analysis of the boron-concentration profiles in nitrogen-doped 4H- and aluminum-doped 6H-SiC, however, indicated that ISi, rather than VSi, controls the diffusion of boron [68]. ISi-mediated boron diffusion was then reconsidered in light of evidence of participation of IC [69]. According to experiments on self-diffusion in isotopically enriched 4H-SiC, diffusivities of ISi and IC are of the same order of magnitude, and it was proposed that under specific experimental conditions, either defect is strongly related to the preferred lattice site of boron. Theoretical calculations of a 3C-SiC crystal structure [70–72] also showed that ISi and

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Nitrogen

1

R p (μm)

Phosphorus

0.1

0.01 0.2 Phosphorus

ΔRp (μm)

0.15

Nitrogen

0.1

0.05

0 10

100

1000

Implantation energy (keV)

Figure 7.4 Projected range Rp and range straggling ∆Rp as a function of implantation energy in nitrogen and phosphorus ion implantation into SiC [49, 60–62].

IC are far more mobile than VSi and VC. Under the assumption that ISi and IC have the same mobility in 4H-SiC, boron diffusion, via ISi and IC, can be simulated from a certain initial distribution of point defects. Boron-related centers in SiC are known to have two key characteristics: a shallow acceptor with ionization energy of about 0.30 eV and a deep level with ionization energy of about 0.65 eV [73]. While the nature of the shallow acceptor defect is accepted as an off-center substitutional boron atom at a silicon site (BSi) [74], that of the deep boron-related level is not clear. A BSi-VC pair [73] was refuted by ab initio calculations that suggest a BSi-SiC complex as a candidate [75]. In addition, candidates such as a substitutional boron atom at a carbon site (BC) and a BC-CSi complex were also put

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7.4

Diffusion

127

forward [76]. The boron-related deep center prevails in boron-doped 4HSiC homoepitaxially grown under a silicon-rich condition [77], while similar experiments under a carbon-rich condition favor the shallow boron acceptor [69]. Since the site-competition effect suggests that boron atoms can occupy both silicon- and carbon-related sites, it is assumed that the deep boron-related level originates from BC [69]. According to the theoretical results on 3C-SiC [70, 71], a mobile boron defect is a boron interstitial (IB) rather than a boron-interstitial pair, which is considered to mediate boron diffusion in silicon [78, 79]. Although it is ideal to simulate diffusion of IB to calculate boron-concentration profiles, the most relevant configuration of IB in 4H-SiC is still not clear. To reproduce the experimentally obtained boron-diffusion profiles for designing 4H-SiC power devices, a boron-interstitial-pair diffusion model in a commercial process simulator [57], which is optimized mainly for use with silicon, is applied. The reported boron-concentration profiles in 4H-SiC [80, 81] are used in Sections 7.4.2 and 7.4.3 because the annealing conditions for high-temperature (500°C)-implanted (200 keV/4 × 1014 cm−2) boron ions are systematically varied. 7.4.2

Dual-Sublattice Diffusion Modeling

It is assumed that ISi and IC diffuse on their own sublattices [82] in accordance with the theoretical calculation on boron diffusion in 3C-SiC [83]. The kick-out reactions forming IB from a boron atom at the silicon site (BSi) and at the carbon site (BC) are then expressed as BSi + ISi ↔ IB(type-I)

(7.7)

BC + IC ↔ IB(type-II)

(7.8)

where the expression for the charge state is omitted. In the case of 3C-SiC, IB(type-I) and IB(type-II) can be a carbon-coordinated tetrahedral site, a hexagonal site, or a split-interstitial at a silicon site or a carbon site [71]. The reactions given by (7.7) and (7.8) correspond to the following reactions in the boron-interstitial pair diffusion model [84]: BSij + ISim ↔ (BSi ISi)u+ (j+m−u) h+

(7.7a)

BCk + ICn ↔ (BC IC)v + (k+n−v) h+

(7.8a)

with charge states j, k, m, n, u, v ∈ {0, ±1, ±2, …} and holes h+. According to a previous calculation [71], ISi in 3C-SiC can be charged from neutral to +4, and IC from –2 to +2. If it is assumed that the variations in the charge

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states of ISi and IC in 4H-SiC are the same as those in 3C-SiC, the ranges of m and n in (7.7a) and (7.8a) are limited to m ∈ {0, 1, 2, 3, and 4} and n ∈ {0, ±1, and ±2}. Boron diffusion in an epitaxially grown 4H-SiC structure with a buried boron-doped layer [85] is modeled as shown in Figure 7.5. In this case, the concentrations of point defects are considered to be in thermodynamic equilibrium. The Fermi model, in which all effects of point defects on dopant diffusion are built into pair diffusivities [86], is thus applied. In the present case, the pair diffusivities are (BSiISi)u and (BCIC)v in (7.7a) and (7.8a). In general, when the doping concentration exceeds the intrinsic carrier concentration ni [87], where ni(T) = 1.70×1016 T1.5 exp(−2.08×104/T) (cm−3)

(7.9)

diffusion becomes concentration-dependent [86]. Diffusivity D of a pair (impurity A and interstitial I) is thus expressed as DAI = DAI0+DAI+(p/ni)+1+DAI++(p/ni)+2+DAI−(p/ni) −1+DAI=(p/ni) −2

(7.10)

where p is hole concentration, and superscripts “++” and “=” traditionally stand for +2 and –2. As described in the Section 7.4.1, boron atoms are incorporated into silicon sites as shallow acceptors (BSi−) when a SiC structure is grown under a carbon-rich condition. Equations (7.7a) and (7.10) thus become

Boron concentration (cm−3)

1020

Symbols: Janson et al. [85]

1019 1018

=

(BSi Isi) − (BSi Isi)

As grown at 1620°C After 1-h anneal at 1700°C

1017

0

(BSi Isi) +

(BSi Isi) ++ and (BSi Isi)

1016 1015

0

0.5

1 Depth (μm)

1.5

2

Figure 7.5 Boron-concentration profiles in an epitaxially grown 4H-SiC structure with a buried boron-doped layer before (open circles) and after one-hour annealing at 1,700°C [85]. The profile simulated using the diffusivity of a double-negatively charged BSiISi pair of 1 × 10−15 cm2/s (solid curve) can precisely reproduce the experimental results (solid circles).

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129

BSi−+ISim ↔ (BSiISi)u+(−1+m−u) h+

(7.11)

D(BSiISi) = D(BSiISi)0+D(BSiISi)+(p/ni)+1+D(BSiISi)++(p/ni)+2 +D(BSiISi)−(p/ni) −+D(BSiISi)=(p/ni)2

(7.12)

with m ∈ {0, 1, 2, 3, and 4} and u ∈ {0, ±1, and ±2}. It is assumed that a single term in the right-hand side of (7.12) dominates the diffusion of (BSiISi) pairs. In Figure 7.5, the profile after one-hour annealing at 1,700°C was fitted by using one of the diffusivities of the following five (BSiISi) pairs: neutral, single-, and double-positively charged, and single- and double-negatively charged. As shown in Figure 7.5, the profile simulated with the diffusivity of a double-negatively-charged (BSiISi) pair of 1 × 10−15 cm2/s can precisely reproduce the experimentally obtained concentration profiles, while the profiles simulated using the other four diffusivities cannot. (BSiISi)= is therefore chosen to simulate the diffusion of BSi−. The diffusion of BC [71] is modeled next. Since BC can be regarded as an acceptor, (7.8a) becomes BC−+ ICn ↔ (BCIC)v+(−1+n−v) h+

(7.13)

with n and v ∈ {0, ±1, and ±2}, and (7.10) becomes D(BCIC) = D(BCIC)0+D(BCIC)+(p/ni)+1+D(BCIC)++(p/ni)+2 +D(BCIC)−(p/ni)−1+D(BCIC)=(p/ni)−2

(7.14)

In the case of p-type 6H-SiC, the diffusivity of in-diffused boron is proportional to p when boron vapor pressure is low [68]. Under the assumption that similar dependence is observable in the case of 4H-SiC, Section 7.4.3 uses the diffusivity of a single-positively charged pair (BCIC)+ to simulate the diffusion of BC−. 7.4.3

Semi-Atomistic Simulation

Diffusion of implanted boron ions is calculated from the initial point-defect distribution determined by Monte-Carlo simulation [82]. In the calculation, the continuity equation ∂/∂t (CI+C(BSiI)=+C(BCI)+) = −div(JI+J(BSiI)=+J(BCI)+)–Kr(CICV–CI*CV*) (7.15)

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is solved with J(BSiI)= = −D(BSiI)= {−grad[CBSi−(CI/CI*)+CBSi−(CI/CI*)(qE/kT)]}

(7.16)

J(BCI)+ = −D(BCI)+ {−grad[CBC− (CI/CI*)+CBC−(CI/CI*)(qE/kT)]}

(7.17)

and

where CI and CV are interstitial and vacancy concentrations, CI* and CV* are equilibrium interstitial and vacancy concentrations, JI is the interstitial flux, Kr is the interstitial-vacancy bulk recombination coefficient, q is the electronic charge, E is the electric field, k is Boltzmann’s constant, and T is the absolute temperature. As expressed by (7.16) and (7.17), both the fluxes of (BSiI)= and (BCI)+ take the effect of electric field into account. The first step of the simulation is to obtain as-implanted boron profiles along with the initial distribution of point defects. Once ISi and IC are created, they are treated as the same I (with an unidentified origin). Similarly, the created VSi and VC are treated as the same V. Equations (7.12) and (7.14) are therefore simplified as D(BSiI) = D(BSiI)=(p/ni)−2

(7.18)

D(BCI) = D(BCI)+(p/ni)+1

(7.19)

In the Monte-Carlo simulation, the surface of 4H-SiC was assumed to be misoriented by 8° from (0001) toward [ 1120 ], and the boron-ion-beam divergence was set to 0.1°. The probabilities of the implanted boron ions occupying a silicon site (rSi) or a carbon site (rC) are specified as follows. For boron-ion implantation of 4×1014 cm−2 at 200 keV and 500°C [81, 82], as-implanted concentration profiles of BSi−, BC−, I, and V are calculated under the tentative assumption that rSi = rC = 0.5. The detailed procedure for determining other temperature-dependent parameters is described in [82]. As shown in Figure 7.6, owing to the introduction of the dual-sublattice modeling (described in Section 7.4.2), the simulated boron-concentration profiles well describe the tail regions of the measured profiles (symbols) with a background doping level (Nb) ranging from n- to p-type under conditions T = 1,900°C and t = 15 min [81]. The tail regions are represented mainly by BSi− (Nb = 1 × 1019 cm−3 [n-type]) and BC− (Nb = 2 × 1015 cm−3 [n-type] and 4 × 1019 cm−3 [p-type]). With respect to time-dependent diffusion, annealing-time (5 to 90 min) dependences of boron concentration

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Diffusion

131

Boron concentration (cm−3)

1020 10

Nb = 4 × 1019 cm−3 (p) 15

−3

19

−3

Nb = 2 × 10 cm (n)

19

Nb = 1 × 10 cm (n)

10

18

10 10 10

17

16

Symbols: Linnarsson et al. [81] 1900°C, 15-min anneal

15

1014

As implanted

1

0

2

3

Depth (μm)

Figure 7.6 Measured (symbols [81]) and simulated boron-concentration profiles in 4HSiC after 15-min annealing at 1900°C.

profiles for Nb = 4 × 1019 cm−3 (p-type) and T = 1400°C [81] are shown in Figure 7.7. The measured time-dependent boron-diffusion profiles (symbols) are precisely reproduced with parameters D(BSiI)= = 3 × 10−18 cm2/s, D(BCI)+ = 6 × 10−12 cm2/s, and Kr = 3 × 10−16 cm3/s. The following remaining issue should also be noted: For applying the developed semi-atomistic simulation to fit other experimentally obtained boron-concentration profiles, rSi/rC must be optimized. Since this optimization is strongly related to experimental conditions [69], rSi/rC needs to be optimized for each experimental condition.

20

Boron concentration (cm−3)

10

90 min 40 min 20 min 10 min 5 min

19

10

1018 17

10

1016 1015 As implanted

1014 0

1

2

3

4

5

Depth (μm)

Figure 7.7 Measured (symbols [81]) and simulated boron-concentration profiles in 4 × 1019-cm-3-doped p-type 4H-SiC after annealing at 1,400°C.

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7.5

Oxidation

In the case of silicon, thermal oxidation represents the most useful method for oxide growth because of a high-quality oxide/semiconductor interface and convenience in terms of device fabrication. However, thermal oxidation of compound semiconductors is much more complex phenomenon than that of silicon. 7.5.1 Thermal Oxidation of GaN He-Cd laser illumination has been used to grow 80-nm-thick α-Ga2O3 by oxidizing GaN in an H3PO4 solution (with pH of 3.5) [88]. This technique has also been applied to fabricating AlGaN/GaN metal-insulator-semiconductor (MIS) high electron mobility transistors [89]. However, among the five phases of Ga2O3, α is a metastable phase; the most stable phase of Ga2O3 is β. Although β-Ga2O3 was obtained by oxidizing GaN at 850 °C for 12 h in an oxygen ambient [90], a very small conduction-band discontinuity, ΔEC, of 0.1 eV (Figure 7.8 [91]) limits its use as a gate dielectric for GaN MIS field-effect transistors (MISFET) (compare ΔEC = 2.3 eV in the case of a deposited SiNx layer on GaN and ΔEC = 2.1 eV in the case of a deposited Al2O3 layer on GaN [92]). 7.5.2 Thermal Oxidation of 4H-SiC Thermal oxidation of SiC is expressed as 2SiC+3O2 → 2SiO2+2CO

(7.20) EC 2.3 eV

0.1 eV

β-Ga2O3 4.9 eV

GaN 3.4 eV

SiN x 5.2 eV

2.1 eV

Al2O3 7.0 eV

EV

Figure 7.8

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Reported energy band alignment at room temperature [91, 92].

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7.6

Metallization

133

where CO molecules ideally diffuse out of the growing oxide. However, some carbon atoms possibly remain near the oxide/SiC interface. Although the measured dependences of oxide thickness on oxidation time have been explained by the so-called Deal−Grove model [93, 94], deviation from this model has been pointed out [95]. Microscopic understanding of thermal oxidation is thus yet to be established. With respect to ΔEC of the thermal oxide/4H-SiC, ΔEC on (0001) (i.e., 2.7−2.8 eV) was reported to be larger than ΔEC on ( 000 1 ) (2.3−2.5 eV) [96]. This difference in ΔEC possibly comes from a dipole at the interfaces of the oxide and 4H-SiC polar (0001) faces. The use of an oxide deposited on 4H-SiC and nitrided in NO or N2O was found to be more reliable compared to oxides formed by N2O oxidation and O2 oxidation [97]. A pileup of nitrogen at the oxide/SiC interface reportedly contributed to the improvement of the interface quality [98].

7.6

Metallization

Since Schottky contacts are described in Chapter 8, n- and p-ohmic contacts are introduced as follows. 7.6.1

Ohmic Contacts to GaN

Titanium/aluminum and titanium/aluminum-based multilevel structures (e.g., gold/nickel/aluminum/titanium) are commonly used as ohmic contacts to n-GaN [99]. A low specific contact resistance ρc of less than 10−5 Ωcm2 was achieved using titanium/aluminum annealed at 900°C for 20 s [100]. With respect to contacts with n+GaN (whose donor density is in the order of 1019 cm−3), tungsten and tungsten silicide (WSix) also led to low ρc (8×10−5 Ωcm2 [101]). As for ohmic contacts to p-GaN, palladium and palladium-based contacts (including gold/palladium, gold/platinum/palladium, and gold/palladium/magnesium/palladium) show ohmic characteristics even before annealing [102]. This finding was explained by a “disorder-induced gap state (DIGS) model” [103] in which Fermi-level pinning occurs due to stress in the epitaxial Pd (111)/p-GaN (0001) interface [104]. A very low ρc of 1×10−6 Ωcm2 was reported in the case of gold/titanium/gold/silver/palladium alloyed at 800°C for 1 min in flowing nitrogen ambient [105]. 7.6.2

Ohmic Contacts to 4H-SiC

A 50−100-nm-thick nickel layer becomes a good n-ohmic contact with 4HSiC (ρc = 1 × 10−6 Ωcm2 at a donor density of 2 × 1019 cm−3) when sintered at around 1,000°C [106, 107]. The carbon atoms that accumulated near the

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metal/semiconductor interface were suggested to lower ρc [108]; however, the detailed mechanism is not fully understood [107]. As for p-ohmic contacts with 4H-SiC, aluminum-based metal (e.g., titanium/aluminum and titanium/nickel/aluminum) are known [109, 110]. To obtain ρc of less than 1 × 10−5 Ωcm2, acceptor concentration exceeding 3 × 1019 cm−3 was needed when sintering was performed at 1,000°C for 2 minutes [111]. To avoid using low-melting-point (about 630°C) aluminum, palladium-based [112], nickel-based [113], and titanium-based p-ohmic contacts [114] have also been investigated.

7.7

Passivation

Since the surface of a semiconductor is sensitive to a high-electric field, the free bonds of the surface atoms must be terminated. As a passivation layer, SiO2 is often used for both GaN and 4H-SiC power devices. Other than SiO2, high-dielectric-constant (high-k) film has been applied for GaN diodes. A high-k film generates a greater expanded depletion region than that generated using a SiO2 film with the same thickness, so higher breakdown voltage devices are expected. A mixed oxide of SiO2 and CeO2 (k = 12.3) was formed on mesa-type GaN p+n diodes using MOCVD [115−117]; the resultant breakdown voltage exceeded 2 kV, while that of diodes passivated with SiO2 (k = 3.9) was 1 kV [118]. With respect to the application of high-k film to 4H-SiC power devices, a field plate (see Chapter 11) using HfO2 was simulated [119]. The simulation results showed that a high-k field plate can significantly relieve electricfield enhancement and increase breakdown voltage.

7.8

Summary

Following Chapter 6 on epitaxial growth, this chapter describes the basic aspects of fabrication processes for GaN and 4H-SiC power devices. Readers should also refer to the latest papers on oxidation of 4H-SiC as related research is still being actively conducted.

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[3] Lee, Y. H., et al., “Etch Characteristics of GaN Using Inductively Coupled Cl2/ Ar and Cl2/BCl3 Plasmas,” Journal of Vaccum Science and Technology A, Vol. 16, No. 3, 1998, pp. 1478–1482. [4] Kim, H. S., et al., “Effects of Inductively Coupled Plasma Conditions on the Etch Properties of GaN and Ohmic Contact Formations,” Materials Science and Engineering B, Vol. 50, No. 1–3, 1997, pp. 82–87. [5] Cho, H., et al., “Low Bias Dry Etching of III-Nitrides in Cl2-Based Inductively Coupled Plasmas,” Journal of Electronics Materials, Vol. 27, No. 4, 1998, pp. 166–170. [6] Cho, H., et al., “Comparison of Inductively Coupled Plasma Cl2 and Cl4/H2 Etching of III-Nitrides,” Journal of Vacuum Science and Technology A, Vol. 16, No. 3, 1998, pp. 1631–1635. [7] Lee, J. W., et al., “Dry Etching of GaN and Related Materials: Comparison of Techniques,” IEEE Journal of Selected Topics of Quantum Electronics, Vol. 4, No. 3, 1998, pp. 557–563. [8] Smith, S. A., et al., “High Rate and Selective Etching of GaN, AlGaN, and AlN Using an Inductively Coupled Plasma,” Applied Physics Letters, Vol. 71, No. 25, 1997, pp. 3631–3633. [9] Ohta, H., et al., “Ion-Irradiation Damage on GaN p-n Junction Diodes by Inductively Coupled Plasma Etching and Its Recovery by Thermal Treatment,” Nuclear Instruments and Methods in Physics Research B, Vol. 409, 2017, pp. 65–68. [10] Cao, L. H., B. H. Li, and J. H. Zhao, “Etching of SiC Using Inductively Coupled Plasma,” Journal of the Electrochemical Society, Vol. 145, No. 10, 1998, pp. 3609–3612. [11] Wang, J. J., et al., “Inductively Coupled Plasma Etching of Bulk 6H-SiC and Thin-Film SiCN in NF3 Chemistries,” Journal of Vacuum Science and Technology A, Vol. 16, No. 4, 1998, pp. 2204–2209. [12] Khan, F. A., and I. Adesida, “High Rate Etching of SiC Using Inductively Coupled Plasma Reactive Ion Etching in SF6-Based Gas Mixtures,” Applied Physics Letters, Vol. 75, No. 15, 1999, pp. 2268–2270. [13] Jiang, L. D., et al., “Inductively Coupled Plasma Etching of SiC in SF6/O2 and Etch-Induced Surface Chemical Bonding Modifications,” Journal of Applied Physics, Vol. 93, No. 3, 2003, pp. 1376–1383. [14] Mikami, H., et al., “Role of Hydrogen in Dry Etching of Silicon Carbide Using Inductively Coupled and Capacitively Coupled Plasma,” Japanese Journal of Applied Physics, Vol. 44, No. 6A, 2005, pp. 3817–3821. [15] Kosugi, R., et al., “Strong Impact of Slight Trench Direction Misalignment from [ 1120 ] on Deep Trench Filling Epitaxy for SiC Super-Junction Devices,” Japanese Journal of Applied Physics, Vol. 56, 2017, pp. 04CR05-1–04CR05-4. [16] Zhuang, D., and J. H. Edgar, “Wet Etching of GaN, AlN, and SiC,” Materials Science and Engineering Reports, Vol. 48, 2005, pp. 1–46. [17] Palacios, T., et al., “Wet Etching of GaN Grown by Molecular Beam Epitaxy on Si(111),” Semiconductor Science and Technology, Vol. 15, No. 10, 2000, pp. 996–1000.

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[18] Rouviere, J. L, et al., “Polarity Determination for GaN Films Grown on (0001) Sapphire and High-Pressure-Grown GaN Single Crystals,” Applied Physics Letters, Vol. 73, No. 6, 1998, pp. 668–670. [19] Li, D., et al., “Selective Etching of GaN Polar Surface in Potassium Hydroxide Solution Studied by X-Ray Photoelectron Spectroscopy,” Journal of Applied Physics, Vol. 90, No. 8, 2001, pp. 4219–4223. [20] Morimoto, Y., “Few Characteristics of Epitaxial GaN–Etching and Thermal Decomposition,” Journal of the Electrochemical Society, Vol. 121, No. 10, 1974, pp. 1383–1384. [21] Shintani, A. and S. Minagawa, “Etching of GaN Using Phosphoric Acid,” Journal of the Electrochemical Society, Vol. 123, No. 5, 1976, pp. 706–713. [22] Kim, B. J., et al., “Wet Etching of (0001) GaN/Al2O3 Grown by MOVPE,” Journal of Electronic Materials, Vol. 27, No. 5, 1998, pp. L32–L34. [23] Hong, S. K., et al., “Evaluation of Nanopipes in MOCVD Grown (0001) GaN/ Al2O3 by Wet Chemical Etching,” Journal of Crystal Growth, Vol. 191, No. 1–2, 1998, pp. 275–278. [24] Mynbaeva, M. G., et al., “Wet Chemical Etching of GaN in H3PO4 with Al ions,” Electrochemical and Solid-State Letters, Vol. 2, No. 8, 1999, pp. 404–406. [25] Katsuno, M., et al., “Mechanism of Molten KOH Etching of SiC Single Crystals: Comparative Study with Thermal Oxidation,” Japanese Journal of Applied Physics, Vol. 38, No. 8, 1999, pp. 4661–4665. [26] Stagg, J. P., “Drift Mobilities of Na+ and K+ Ions in SiO2 Films,” Applied Physics Letters, Vol. 31, No. 8, 1977, pp. 532–534. [27] Kodama, M., “GaN-Based Trench Gate Metal Oxide Semiconductor Field-Effect Transistor Fabricated with Novel Wet Etching,” Applied Physics Express, Vol. 1, 2008, pp. 021104-1–021104-3. [28] Weyher, J. L., et al., “Recent Advances in Defect-Selective Etching of GaN,” Journal of Crystal Growth, Vol. 210, No. 1–3, 2000, pp. 151–156. [29] Minsky, M. S., M. White, and E. L. Hu, “Room-Temperature Photoenhanced Wet Etching of GaN,” Applied Physics Letters, Vol. 68, No. 11, 1996, pp. 1531–1533. [30] Lee, J.-S., et al., “Photoelectrochemical Gate Recess Etching for the Fabrication of AlGaN/GaN Heterostructure Field Effect Transistor,” Japanese Journal of Applied Physics, Vol. 40, No. 3A, 2001, pp. L198–L200. [31] Chang, W. H., “Micromachining of p-Type 6H-SiC by Electrochemical Etching,” Sensors and Actuators A, Vol. 112, No. 1, 2004, pp. 36–43. [32] Ke, Y., et al., “Surface Polishing by Electrochemical Etching of p-Type 4H-SiC,” Journal of Applied Physics, Vol. 106, No. 6, 2009, pp. 064901-1–064901-7. [33] Shor, J. S., et al., “Characterization of Nanocrystallites in Porous p-Type 6HSiC,” Journal of Applied Physics, Vol. 76, No. 7, 1994, pp. 4045–4049. [34] Shor, J. S., R. M. Osgood, and A. D. Kutz, “Photoelectrochemical Conductivity Selective Etch Stops for SiC,” Applied Physics Letters, Vol. 60, No. 8, 1992, pp. 1001–1003.

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[35] Shishkin, Y., W. Choyke, and R. P. Devaty, “Photoelectrochemical Etching of n-Type 4H Silicon Carbide,” Journal of Applied Physics, Vol. 96, No. 4, 2004, pp. 2311–2322. [36] Mikami, H., et al., “Analysis of Photoelectrochemical Processes in α-SiC Substrates with Atomically Flat Surfaces,” Japanese Journal of Applied Physics, Vol. 44, No. 12, 2005, pp. 8329–8332. [37] Ke, Y., R. P. Devaty, and W. J. Choyke, “Comparative Columnar Porous Etching Studies on n-type 6H-SiC Crystalline Faces,” Physica Status Solidi B, Vol. 245, No. 7, 2008, pp. 1396–1403. [38] Kasai, H., et al., “Nitrogen Ion Implantation Isolation Technology for Normally-Off GaN MISFETs on p-GaN Substrate,” Physica Status Solidi C, Vol. 11, No. 3–4, 2014, pp. 914–917. [39] Negoro, Y., et al., “Electronic Behaviors of High-Dose Phosphorus-Ion Implanted 4H-SiC (0001),” Journal of Applied Physics, Vol. 96, No. 1, 2004, pp. 224–228. [40] Nomoto, K., et al., “Ion Implantation into GaN and Implanted GaN Power Transistors,” ECS Transactions, Vol. 69, No. 11, 2015, pp. 105–112. [41] Nomoto, K., et al., “Remarkable Reduction of On-Resistance by Ion Implantation in GaN/AlGaN/GaN HEMTs with Low Gate Leakage Current,” IEEE Electron Device Letters, Vol. 28, No. 11, 2007, pp. 939–941. [42] Taguchi, S., et al., “High Threshold Voltage Normally-Off GaN MISFETs Using Self-Aligned Technique,” Physica Status Solidi C, Vol. 9, No. 3–4, 2012, pp. 858–860. [43] Ottaviani, L., et al., “Aluminum Multiple Implantations in 6H-SiC at 300K,” Solid-State Electronics, Vol. 43, No. 12, 1999, pp. 2215–2223. [44] Park, C., et al., “Paradoxical Boron Profile Broadening Caused by Implantation Through a Screen Oxide Layer,” International Electron Devices Meeting, Washington, D.C., 1991, pp. 67–70. [45] Morris, S. J., et al., “An Accurate and Efficient Model for Boron Implants Through Thin Oxide Layers into Single-Crystal Silicon,” IEEE Transactions on Semiconductor Manufacturing, Vol. 8, No. 4, 1995, pp. 408–413. [46] Kuroda, N., et al., “Step-Controlled VPE Growth of SiC Single Crystals at Low Temperatures,” Solid State Devices and Materials, Tokyo, 1987, pp. 227–230. [47] Mochizuki, K., et al., “Detailed Analysis and Precise Modeling of MultipleEnergy Al Implantations Through SiO2 Layers into 4H-SiC,” IEEE Transactions on Electron Devices, Vol. 55, No. 8, 2008, pp. 1997–2003. [48] Pearson, K., “Contributions to the Mathematical Theory of Evolution, II: Skew Variation in Homogeneous Material,” Philosophical Transactions of the Royal Society of London, A, Vol. 186, 1895, pp. 343–414. [49] Janson, M. S., et al., “Ion Implantation Range Distributions in Silicon Carbide,” Journal of Applied Physics, Vol. 93, No. 11, 2003, pp. 8903–8909. [50] Stief, R., et al., “Range Studies of Aluminum, Boron, and Nitrogen Implants in 4H-SiC,” International Conference on Ion Implantation Technology, Kyoto, June 1998, pp. 760–763.

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[51] Lee, S.-S. and S.-G. Park, “Empirical Depth Profile Model for Ion Implantation in 4H-SiC,” Journal of Korean Physical Society, Vol. 41, No. 5, 2002, pp. L591–L593. [52] Tasch, A. F., et al., “An Improved Approach to Accurately Model Shallow B and BF2 Implants in Silicon,” Journal of the Journal of Electrochemical Society, Vol. 136, No. 3, 1989, pp. 810–814. [53] Suzuki, K., et al., “Comprehensive Analytical Expression for Dose Dependent Ion-Implanted Impurity Concentration Profiles,” Solid-State Electronics, Vol. 42, No. 9, 1998, pp. 1671–1678. [54] Mochizuki, K. and H. Onose, “Dual-Pearson Approach to Model Ion-Implanted Al Concentration Profiles for High-Precision Design of High-Voltage 4H-SiC Power Devices,” Materials Science Forum, Vol. 600–603, 2009, pp. 607–610. [55] Mochizuki, K., and N. Yokoyama, “Two-Dimensional Modeling of AluminumIon Implantation into 4H-SiC,” Materials Science Forum, Vol. 679–680, 2011, pp. 405–408. [56] Mochizuki, K., and N. Yokoyama, “Two-Dimensional Analytical Model for Concentration Profiles of Aluminum Implanted into 4H-SiC (0001),” IEEE Transactions on Electron Devices, Vol. 58, 2011, pp. 455–459. [57] http://www.silvaco.com/products/tcad/process_simulation/process_simulation.html. [58] https://www.synopsys.com/silicon/tcad/process-simulation.html. [59] Mochizuki, K., et al., “A-Commercial-Simulator-Based Numerical-Analysis Methodology for 4H-SiC Power Device Formed on Misoriented (0001) Substrates,” IEEE Journal of the Electron Devices Society, Vol. 3, 2015, pp. 316–322. [60] Ahmed, S., et al., “Empirical Depth Simulator for Ion Implantation in 6H SiC,” Journal of Applied Physics, Vol. 77, No. 12, 1995, pp. 6194–6200. [61] Rao, M. V., et al., “Donor Ion-Implantation Doping into SiC,” Journal of Electronic Materials, Vol. 28, No. 3, 1999, pp. 334–340. [62] Janson, M. S., et al., “Range Distributions of Implanted Ions in Silicon Carbide,” Materials Science Forum, Vol. 389–393, 2002, pp. 779–782. [63] Kimoto, T., and J. A. Cooper, Fundamentals of Silicon Carbide Technology, Singapore: John Wiley & Sons, 2014, pp. 191–193. [64] Wilson, R. G., et al., “Redistribution and Activation of Implanted S, Se, Te, Be, Mg, and C in GaN,” Journal of Vacuum Science and Technology A, Vol. 17, No. 4, 1999, pp. 1226–1229. [65] Kosugi, R., et al., “First Experimental Demonstration of SiC Super-Junction (SJ) Structure by Multiepitaxial Method,” International Symposium on Power Semiconductor Devices and ICs, Waikoloa, June 2014, pp. 346–349. [66] Okamoto, D., et al., “Improved Channel Mobility in 4H-SiC MOSFETs by Boron Passivation,” IEEE Electron Device Letters, Vol. 35, No. 12, 2014, pp. 1176–1178. [67] Mokhov, E. N., E. E. Goncharov, and G. G. Ryabova, “Diffusion of Boron in p-Type Silicon Carbide,” Soviet Physics–Semiconductors, Vol. 18, 1984, pp. 27–30.

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[68] Bracht, H., N. A. Stolwijl, and G. Pensl, “Diffusion of Boron in Silicon Carbide: Evidence for the Kick-Out Mechanism,” Applied Physics Letters, Vol. 77, No. 20, 2000, pp. 3188–3120. [69] Rüschenschmidt, K., et al., “Self-Diffusion in Isotopically Enriched Silicon Carbide and Its Correlation with Dopant Diffusion,” Journal of Applied Physics, Vol. 96, No. 3, 2004, pp. 1458–1463. [70] Rurali, R., et al., “Theoretical Evidence for the Kick-Out Mechanism for B Diffusion in SiC,” Applied Physics Letters, Vol. 81, No. 16, 2002, pp. 2989–2991. [71] Bockstedte, M., A. Mattausch, and O. Pankratov, “Ab Initio Study of the Migration of Intrinsic Defects in 3C-SiC,” Physical Review B, Vol. 68, No. 20, 2003, pp. 205201-1–205201-17. [72] Gao, H., et al., “Atomistic Study of Intrinsic Defect Migration in 3C-SiC,” Physical Review B, Vol. 69, No. 24, 2004, pp. 245205-1–245205-5. [73] Duijin-Arnold, A. V., et al., “Electronic Structure of the Deep Boron Acceptor in Boron-Doped 6H-SiC,” Physical Review B, Vol. 57, No. 3, 1998, pp. 1607–1619. [74] Duijin-Arnold, A. V., et al., “Spatial Distribution of the Electronic Wave Function of the Shallow Boron Acceptor in 4H- and 6H-SiC,” Physical Review B, Vol. 60, No. 23, 1999, pp. 15829–15847. [75] Aradi, B., et al., “Boron Centers in 4H-SiC,” Materials Science Forum, Vol. 353– 356, 2001, pp. 455–458. [76] Bockstedte, M., A. Mattausch, and O. Pankratov, “Boron in SiC: Structure and Kinetics,” Materials Science Forum, Vol. 353–356, 2001, pp. 447–450. [77] Srindhara, S. G., et al., “Photoluminescence and Transport Studies of Boron in 4H-SiC,” Journal of Applied Physics, Vol. 83, No. 12, 1998, pp. 7909–7920. [78] Sadigh, B., et al., “Mechanism of Boron Diffusion in Silicon: An Ab Initio and Kinetic Monte Carlo Study,” Physical Review Letters, Vol. 83, No. 21, 1999, pp. 4341–4344. [79] Windle, W., et al., “First Principles Study of Boron Diffusion in Silicon,” Physical Review Letters, Vol. 83, No. 21, 1999, pp. 4345–4348. [80] Linnarsson, M. K., et al., “Aluminum and Boron Diffusion in 4H-SiC,” Materials Research Society Proceedings, Vol. 742, Warrendale, Dec. 2002, paper K6.1. [81] Linnarsson, M. K., et al., “Boron Diffusion in Intrinsic, n-Type amd p-Type 4H-SiC,” Materials Science Forum, Vol. 457–460, 2004, pp. 917–920. [82] Mochizuki, K., H. Shimizu, and N. Yokoyama, “Dual-Sublattice Modeling and Semi-Atomistic Simulation of Boron Diffusion in 4H-Silicon Carbide,” Japanese Journal of Applied Physics, Vol. 48, 2009, pp. 031205-1–031205-6. [83] Bockstedte, M., A. Mattausch, and O. Pankratov, “Different Roles of Carbon and Silicon Interstitials in the Interstitial-Mediated Boron Diffusion in SiC,” Physical Review B, Vol. 70, No. 11, 2004, pp. 115203-1–115203-13. [84] Bracht, H., “Self- and Foreign-Atom Diffusion in Semiconductor Isotope Heterostructures. I. Continuum Theoretical Calculations,” Physical Review B, Vol. 75, No. 3, 2007, pp. 035210-1–035210-16.

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[85] Janson, M. S., et al., “Transient Enhanced Diffusion of Implanted Boron in 4HSilicon Carbide,” Applied Physics Letters, Vol. 76, No. 11, 2000, pp. 1434–1436. [86] Plummer, G. H., M. D. Deal, and P. B. Griffin, Silicon VLSI Technology, Upper Saddle River, NJ: Prentice Hall, 2000, p. 411. [87] Baliga, B. J., Silicon Carbide Power Devices, Singapore: World Scientific, 2005, pp. 978–981. [88] Lee, C.-T., H.-Y. Lee, and H.-W. Chen, “GaN MOS Device Using SiO2–Ga2O3 Insulator Grown by Photoelectrochemical Oxidation Method,” IEEE Electron Device Letters, Vol. 24, No. 2, 2003, pp. 54–56. [89] Huang, L.-S., et al., “AlGaN/GaN metal-oxide-semiconductor High-Electron Mobility Transistors Using Oxide Insulator Grown by Photoelectrochemical Oxidation Method,” IEEE Electron Device Letters, Vol. 29, No. 4, 2008, pp. 284–286. [90] Kim, H., S.-J. Park, and H. Hwang, “Thermally Oxidized GaN Film for Use as Gate Insulators,” Journal of Vacuum Science and Technology B, Vol. 19, No. 2, 2001, pp. 579–581. [91] Wei, W., et al., “Valence Band Offset of β-Ga2O3/Wurtzite GaN Heterostructure Measured by X-Ray Photoelectron Spectroscopy,” Nanoscale Research Letters, Vol. 7, 2012, pp. 562-1–562-5. [92] Hua, M., et al., “Integration of LPCVD-SiNx Gate Dielectric with RecessedGate E-Mode GaN MIS-FETs: Toward High Performance, High Stability and Long TDDB Lifetime,” International Electron Devices Meeting, San Francisco, Dec. 2016, pp. 260–263. [93] Deal, B. E., and A. S. Grove, “General Relationship for the Thermal Oxidation of Silicon,” Journal of Applied Physics, Vol. 36, No. 12, 1965, pp. 3770–3778. [94] Song, Y., et al., “Modified Deal–Grove Model for the Thermal Oxidation of Silicon Carbide,” Journal of Applied Physics, Vol. 95, No. 9, 2004, pp. 4953–4957. [95] Hijikata, Y., Y. Yaguchi, and S. Yoshida, “A Kinetic Model of Silicon Carbide Oxidation Based on the Interface Silicon and Carbon Emission Phenomenon,” Applied Physics Express, Vol. 2, 2009, pp. 021203-1–021203-3. [96] Watanabe, H., et al., “Energy Band Structure of SiO2/4H-SiC Interfaces and Its Modulation Induced by Intrinsic and Extrinsic Interface Transfer,” Materials Science Forum, Vol. 679–680, 2011, pp. 386–389. [97] Noborio, M, et al., “Reliability of Nitrided Gate Oxide for n- and p-Type 4HSiC(0001) Metal-Oxide-Semiconductor Devices,” Japanese Journal of Applied Physics, Vol. 50, No. 9R, 2011, pp. 090201-1–090201-3. [98] Kimoto, T., et al., “Interface Properties of Metal-Oxide-Semiconductor Structures on 4H-SiC{0001} and ( 1120 ) Formed by N2O Oxidation,” Japanese Journal of Applied Physics, Vol. 44, No. 3, 2005, pp. 1213–1218. [99] Fan, Z., et al., “Very Low Resistance Multilayer Ohmic Contact to n-GaN,” Applied Physics Letters, Vol. 68, No. 12, 1996, pp. 1672–1674. [100] Liu, Q. Z., and S. S. Lau, “A Review of the Metal–GaN Contact Technology,” Solid-State Electronics, Vol. 42, No. 5, 1998, pp. 677–691.

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[101] Cole, M. W, et al., “Post Growth Rapid Thermal Annealing of GaN: The Relationship Between Annealing Temperature, GaN Crystal Quality, and Contact– GaN Interfacial Structure,” Applied Physics Letters, Vol. 71, No. 20, 1997, pp. 3004–3006. [102] Lee, J.-L., et al., “Ohmic Contact Formation Mechanism of Nonalloyed Pd Contacts to p-Type GaN Observed by Positron Annihilation Spectroscopy,” Applied Physics Letters, Vol. 74, No. 16, 1999, pp. 2289–2291. [103] Hasegawa, H., and H. Ohno, “Unified Disorder Induced Gap State Model for Insulator-Semiconductor and Metal-Semiconductor Interfaces,” Journal of Vacuum Science and Technology B, Vol. 4, No. 4, 1986, pp. 1130–1138. [104] Kim, D.-W., et al., “Electrical Properties of Pd-Based Ohmic Contact to p-GaN,” Journal of Vacuum Science and Technology B, Vol. 19, No. 3, 2001, pp. 609–614. [105] Adivarahan, V., et al., “Very-Low-Specific-Resistance Pd/Ag/Au/Ti/Au Alloyed Ohmic Contact to p GaN for High-Current Devices,” Applied Physics Letters, Vol. 78, No. 18, 2001, pp. 2781–2783. [106] Porter, L. M., and R. F. Davis, “A Critical Review of Ohmic and Rectifying Contacts for Silicon Carbide,” Materials Science and Engineering B, Vol. 34, No. 2–3, 1995, pp. 83–105. [107] Kimoto, T., and J. A. Cooper, Fundamentals of Silicon Carbide Technology, Singapore: John Wiley & Sons, 2014, pp. 259–261. [108] Reshanov, S. A., et al., “Effect of an Intermediate Graphite Layer on the Electronic Properties of Metal/SiC Contacts,” Physica Status Solidi B, Vol. 245, No. 7, 2008, pp. 1369–1377. [109] Crofton, J., et al., “Titanium and Aluminum-Titanium Ohmic Contacts to pType SiC,” Solid-State Electronics, Vol. 41, No. 11, 1997, pp. 1725–1729. [110] Vassilevski, K., et al., “Phase Formation at Rapid Thermal Annealing of Al/Ti/ Ni Ohmic Contacts on 4H-SiC,” Materials Science and Engineering B, Vol. 80, No. 1–3, 1997, pp. 370–373. [111] Crofton, J., et al., “Contact Resistance Measurement on p-Type 6H-SiC,” Applied Physics Letters, Vol. 62, No. 4, 1997, pp. 384–386. [112] Kassamokova, L., et al., “Thermostable Ohmic Contacts on p-Type SiC,” Materials Science Forum, Vol. 264–268, 1998, pp. 787–790. [113] Fursin, L. G, J. H. Zhao, and M. Weiner, “Nickel Ohmic Contacts to p- and nType 4H-SiC,” Electronics Letters, Vol. 37, No. 17, 2001, pp. 1092–1093. [114] Lee, S. K., C. M. Zettering, and M. Östling, “Low Resistivity Ohmic Titanium Carbide Contacts to n- and p-Type 4H-Silicon Carbide,” Solid-State Electronics, Vol. 44, No. 7, 2000, pp. 1179–1186. [115] Ohno, H., et al., “Chemical Vapor Deposition of CeO2 Films Using a Liquid Metalorganic Source,” Electrochemical and Solid-State Letters, Vol. 9, No. 3, 2006, pp. G87–G89. [116] Tagui, K., et al., “The Electrical Property of CeO2 Films Deposited by MOCVD on Si (100),” Electrochemical and Solid-State Letters, Vol. 10, No. 7, 2007, pp. D73–D75.

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[117] Matsumura, T., et al., “MOCVD of CeO2 and SiO2 Mixture Films Using Alkoxy Sources,” ECS Solid State Letters, Vol. 4, No. 12, 2015, pp. N17–N19. [118] Yoshino, M., et al., “High-k Dielectric Passivation for GaN Diode with a Field Plate Termination,” Electronics, Vol. 5, No. 2, 2016, pp. 15-1–15-7. [119] Song, Q.-W., et al., “Simulation Study on 4H-SiC Power Devices with High-k Dielectric FP Terminations,” Diamond & Related Materials, Vol. 22, 2012, pp. 42–47.

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CHAPTER

8 Contents 8.1 Introduction 8.2 Schottky-Barrier Lowering 8.3 Forward-Biased Schottky Junction 8.4 Forward-Current/ Voltage Characteristics Based on Diffusion Theory 8.5 Forward-Current/ Voltage Characteristics Based on TED Theory 8.6 Reverse-Current/ Voltage Characteristics Based on TFE Theory 8.7 Pure SBDs 8.8 Graded AlGaN SBDs 8.9 4H-SiC SBDs with a Thin p+-Type Layer 8.10 Shielded Planar SBDs 8.11 Summary

Metal-Semiconductor Contacts and Unipolar Power Diodes 8.1

Introduction

As described in Chapter 1, a power diode, which exhibits forward voltage drop VF at forward current IF (Figure 1.8), is one of the building blocks of power-electronic circuits. In the case of a bipolar diode, qVF takes a value approximately equivalent to the bandgap energy Eg of the semiconductor used, where q is elementary charge (1.6 × 10−19 C). For example, the measured forward-current/voltage characteristics of a GaN p+n diode (Figure 8.1[a]) [1] (which is shown in Figure 3.6) are plotted on a linear scale in Figure 8.1(b). At IF of 5.2 mA (i.e., 180 A/cm2), VF becomes Eg/q of GaN (i.e., 3.44V [2]). To further decrease VF, a unipolar diode must therefore be used. Another advantage of a unipolar diode is absence of minority-carrier injection, leading to a very fast turnoff and low switching energy.

143

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Forward current (mA)

10 −1

60-μm Φ 300 K

10 −2 10 −3 10 −4 10 −5 10 −6 10 −7 2.7

Forward current (mA)

25

2.9

3.1 3.3 3.5 Forward voltage (V) (a)

3.7

3.9

3.7

3.9

60-μm Φ 300 K

20 15 10 5

5.2 3.44

0 2.7

2.9

3.1 3.3 3.5 Forward voltage (V) (b)

Figure 8.1 Room-temperature forward-current/voltage characteristics of a GaN p+n diode plotted on (a) semi-log [1] and (b) linear scales.

A unipolar diode utilizes a metal-semiconductor contact called a Schottky junction [3]. An energy-band diagram of a metal and an n-type semiconductor that are not in contact is shown in Figure 8.2(a). The vacuum or free-electron energy is taken as a reference level that represents the energy that an electron would have if it were free of influence of the metal or the semiconductor. The difference between the vacuum level and Fermi level (see Section 2.3) is called the work function, which is usually denoted as qΦ in eV (or Φ in volts). In the case of semiconductors, the work function becomes a function of dopant concentration. Since electron affinity qΧ (i.e., the difference between the vacuum level and the conduction-band minimum, EC) is constant, the work functions of the metal and the semiconductor are respectively expressed as qΦm and q(Χ + Φn) in Figure 8.2(a), where qΦn is the difference between EC and the Fermi level EF of the semiconductor. Hereafter, the case that Φm > Χ + Φn—namely, the electrons in the semiconductor have a higher total energy (on average) than the electrons in the metal—is considered.

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8.2

Schottky-Barrier Lowering

145

Vacuum qX qΦm

qΦn

qX

EC EF

qΦm EC EF

EV EV (a)

(b)

qΨbi EC EF

q(Φm−X) WD

EV (c) Figure 8.2 Energy-band diagrams of a metal and an n-type semiconductor (a) in separation and connected with (b) finite and (c) no gaps.

When the metal and the semiconductor are almost in contact and separated with a finite gap (Figure 8.2[b]), the Fermi level of the metal, which is equal to qΦm, coincides with the EF of the semiconductor in equilibrium. Note that in Figure 8.2(b) the vacuum level is continuous and the electron affinity is constant. In the case that the gap between the metal and the semiconductor becomes zero (Figure 8.2[c]), an abrupt discontinuity of EC exists at the metal-semiconductor interface. The magnitude of this discontinuity is called the Schottky-barrier height (qΦB), which is expressed as

qΦB = q(Φm − Χ) = q(Ψbi + Φn)

(8.1)

Since qΦB is smaller than Eg (= EC − EV) of the semiconductor, VF of a unipolar diode is less than VF of a bipolar diode as long as the voltage-drop across the drift layer is negligible.

8.2

Schottky-Barrier Lowering

Schottky-barrier lowering is the lowering of qΦB induced by an image force in the presence of electric field. In detail, when an electron is at

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a distance x from a metal surface, a positive charge is induced on the metal surface. The attractive force between the electron and the positive charge is equivalent to the attractive force F between the electron and an equal positive charge located at −x (i.e., the image charge) given as F = −q2/[4πεrεo(2x)2] = −q2/(16πεrεox2)

(8.2)

The work done on the electron in the course of its transfer from the point x to infinity is given as W ( x) =

∫

∞ x

(

Fdx = −q2 / 16πεr εo x 2

)

(8.3)

Equation (8.3) corresponds to the potential energy Ep(x) of an electron placed at distance x from the metal surface. Under electric field E, Ep(x) is lowered from −q|E|x as follows: Ep(x) = −q|E|x−q2/(16πεrεox)

(8.4)

Ep(x) reaches a maximum at xm, which is given as xm = [q/(16πεrεo|E|)]0.5

(8.5)

under the condition dEp/dx = 0. qΦB is thus reduced from the value at x = 0 [(8.1)] by ΔqΦB, which is given by ΔqΦB = (qEmax/4πεrεo)0.5

(8.6)

where Emax is maximum field strength (see Section 3.5).

8.3

Forward-Biased Schottky Junction

Two distinctly different mechanisms exist in forward current across a Schottky junction: thermionic emission of carriers across the Schottky barrier [4] and diffusion of carriers from the semiconductor into the metal [3] (Section 8.4). The thermionic emission theory postulates that only energetic electrons, which have an energy equal to or larger than the conduction band energy at the metal-semiconductor interface, contribute to forward current JTE (8.7). The diffusion theory, on the other hand, assumes that the driving force for forward current JD (8.8) is distributed over the length of the depletion layer.

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8.3

Forward-Biased Schottky Junction

147

JTE = qNC(kT/2πmn)0.5 exp(−qΦB/kT) [exp(qVF/kT)−1]

(8.7)

JD = (q2DnNC/kT){[2q(ΦB−Φn−VF)ND]/εrεo}0.5 × exp(−qΦB/kT) [exp(qVF/kT)−1]

(8.8)

and

where NC is the effective density of states in conduction bands (2.6b), mn is the effective mass of electrons, and Dn is the diffusivity of electrons (Section 3.2). In the case of a silicon Schottky junction, forward current is limited by JTE; however, this is not the case with GaN and 4H-SiC Schottky junctions due to the following reason. The charge and field distributions and band diagrams for a metal-semiconductor junction are similar to those of a p+n junction shown in Figure 3.4. When forward voltage VF is applied to the metal and the semiconductor is grounded, Emax is given by (3.28) and (3.31) as Emax = [2qND(Ψbi−VF)/εrεo]0.5

(8.9)

For example, breakdown voltage BV is about 0.5 kV when ND is 5 × 1014 cm−3 in the case of a silicon Schottky junction, and ND is 1 × 1017 cm−3 in the cases of GaN and 4H-SiC Schottky junctions [5]. When Ψbi − VF is 0.1V, Emax is 4 kV/cm in the case of the silicon Schottky junction and 60 kV/cm in the cases of the GaN and 4H-SiC Schottky junctions. Although the drift velocity of electrons (vn) in the case of the silicon Schottky junction is almost proportional to |E|, vn almost saturates in the cases of the GaN and 4H-SiC Schottky junctions (Figure 8.3) [6−8]. Einstein relation (see [3.6a]) changes a little under high Emax as follows: Dn = (akT/q) μn(E)

(8.10)

where a = 1.5 in the case of n-type GaN under Emax of 60 kV/cm [9]. Equation (8.8) then becomes JD = aqμn(Emax)NCEmax exp(−qΦB/kT) [exp(qVF/kT)−1]

(8.11)

When Emax is 60 kV/cm, μn is 345 and 164 cm2/Vs (Figure 8.3), respectively, for n-type GaN and 4H-SiC. These high-field μn values are much lower than low-field μnGaN of 1,000 cm2/Vs and μn4H-SiC of 1,140 cm2/Vs [10]. This condition means that collisions of electrons with the lattice (i.e.,

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Electron drift velocity (x107cm/s)

148

2.5 300K 2.0 GaN

1.5 1.0

4H-SiC

silicon 0.5 0

00

4

10 10

20 20

30 30

40 40

50 50

60 60

Electric-field strength (kV/cm)

Figure 8.3 Electric-field strength dependences of drift velocities of electrons in n-type GaN, 4H-SiC, and silicon [6−8].

diffusion) significantly contribute to electrons in n-type GaN or 4H-SiC reaching the Schottky junction (Figure 8.4) [11−13]. However, in the literature on GaN and/or SiC power devices, thermionic emission is described as the controlling forward-current-conduction mechanism of a Schottky junction [14−17]. Therefore, forward-current/voltage characteristics based on diffusion [3] and thermionic emission diffusion (TED) [18] are introduced in Sections 8.4 and 8.5. λ

qφ B

λ

λ

λ

λ

λ

λ

λ

λ

λ

Electron

EC x xm

WDn

EV Figure 8.4 Schematic band diagram of a forward-biased GaN or 4H-SiC Schottky junction. λ denotes electron mean free path.

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8.4

Forward-Current/Voltage Characteristics Based on Diffusion Theory

149

8.4 Forward-Current/Voltage Characteristics Based on Diffusion Theory According to the diffusion theory proposed by Schottky [3], WDn is assumed to be sufficiently larger than λ (which is the case with GaN and 4H-SiC Schottky junctions) so using diffusivity and mobility of electrons for analyzing current/voltage characteristics is practical. According to that diffusion theory, the dependence of forward-current density (JD) on forward voltage (VF) in a Schottky junction is obtained by integrating the equation for electron diffusion and drift (see [3.10a]), namely, JD = qnμnE+qDn(∂n/∂x)

(8.12)

across the depletion region near the Schottky junction. If the potential is denoted as Φ, E = −∂Φ/∂x

(8.13)

Using the Einstein relation (see [3.6a]), for an n-type semiconductor, namely, Dn = (kT/q) μn

(8.14)

(8.12) can be written as JD = qDn[−(qn/kT)(∂Φ/∂x)+∂n/∂x]

(8.15)

By multiplying both sides of (8.15) by an integrating factor, exp(−qΦ/ kT), before integration and assuming that JD is not a function of x, (8.15) becomes JD ∫

WDn

0

exp ( −qΦ / kT ) dx = qDn ⎡⎣n exp ( −qΦ / kT )⎤⎦

WDn 0

(8.16)

If Φ(0) is defined as zero, Φ(WDn) becomes ΦB−Φn−VF. Equation (2.12a) is used to express n(WDn) and n(0) as n(WDn) = NC exp(−qΦn/kT)

(8.17a)

n(0) = NC exp(−qΦB/kT)

(8.17b)

and

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Substituting these boundary values into (8.16) gives J D = qDn N C exp ( −qΦ B / kT ) ⎡⎣exp (qVF / kT ) − 1⎤⎦ / ∫

WDn

0

exp ( −qΦ / kT ) dx (8.18)

By integrating (3.27b), it is possible to approximate Φ(x) as Φ(x) = (qND/εrεo)x(WDn−x/2) for 0 < x < WDn

(8.19)

When (8.19) is inserted into (8.18), and integrating the substituted equation, JD is obtained as a function of VF as JD = JDS [exp(qVF/kT)−1]

(8.20a)

and JDS = (q2DnNC/kT){[2q(ΦB−Φn−VF)ND]/εrεo}0.5 exp(−qΦB/kT) (8.20b) In (8.20b), the square-root dependence of JDS on VF is weak; therefore, it is possible to approximate (8.20a) as JD = JDS’ [exp(qVF/nkT)−1]

(8.21)

where JDS’ is independent of VF and n is an ideality factor(Section 3.6.1.1).

8.5 Forward-Current/Voltage Characteristics Based on TED Theory In Section 8.4, the Schottky junction is assumed to be almost at thermal equilibrium even though currents are flowing. In this section, the influence of thermionic emission on current/voltage characteristics is also considered through the boundary condition of thermionic-recombination velocity vR at xm. Here, the case that qΦB is large enough that the charge concentration between the metal surface and x = WDn (Figure 8.4) is that of ionized donors is considered. Under the assumption that the portion of the barrier between x = 0 and xm acts as a sink for electrons, forward-current density based on TED is expressed as JTED = {A*T2/[1+(vR/vD)]}exp(−qΦB/kT)[exp(qV/kT)−1]

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8.6

Reverse-Current/Voltage Characteristics Based on TFE Theory

vR = (A*T2/2q)(2πmnkT/h2)−1.5

151

(8.22b)

v D = ( μn kT / q ) exp (qΦ B / kT ) / ∫

WDn

0

exp [ EC(x)/ kT ]dx

(8.22c)

EC(x) = qΦB−(q2ND/2εrεo)(2WDnx−x2)

(8.22d)

A* = 4πmnk2q/h3,

(8.22e)

and

where EC(x) is the conduction-band-edge energy measured from the Fermi level in the metal, vD is the effective diffusion velocity associated with the transport of electrons from WDn to xm, h is the Planck constant (6.6 × 10−34 Js), and A* is the effective Richardson constant. For free electrons, A* is equal to the Richardson constant A of 120 Acm−2K−2. Since GaN has isotropic effective mass (0.20 × 9.1 × 10−31 kg) in the lowest minimum of the conduction band, A*/A is simply equal to 0.20. In the case of 4H-SiC, on the other hand, A*/A becomes 1.2 because the number of conduction band minima is 6 [19]. In (8.22a), vR/vD determines the relative current-limiting factor of TE versus diffusion. In the case of a GaN Schottky junction, JTED is limited by the diffusion process at elevated temperatures due to reduced μn [12] (see Section 8.7.1). In the case of a shielded 4H-SiC Schottky junction fabricated using ion implantation (see Section 8.10.2), the influence of the diffusion process on current/voltage characteristics is large even at room temperature [13]. Note that numerical analysis is convenient for simultaneously considering TE and diffusion [11].

8.6 Reverse-Current/Voltage Characteristics Based on TFE Theory When negative bias VR is applied to a metal/n-type semiconductor Schottky junction, a voltage is applied across the depletion region formed in the n-type semiconductor. In the cases of GaN and 4H-SiC Schottky junctions, the resulting tunneling current due to large Emax, which is an order of magnitude larger than Emax in the case of a silicon Schottky junction, cannot be ignored. Electron tunneling near the Fermi level is called field emission (FE), while tunneling of thermally excited electrons, which face a thinner barrier than FE, is called thermionic-field emissions (TFE) (Figure 8.5). FE dominates when thermal energy kT is much lower than E00, which is defined as

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qφB

TFE FE

Electron

EC

EV

Figure 8.5 Schematic energy-band diagram showing electron tunneling (i.e., FE and TFE) through a reverse-biased Schottky junction.

E00 = (qh/4π) (ND/mnεrεo) 0.5

(8.23)

As shown in Figure 8.6, kT is lower than E00 when ND > 1015 cm−3 and T < 15K. At room temperature, on the other hand, kT >> E00 when ND < 1016 cm−3, indicating the dominance of TFE over FE. Current/voltage characteristics calculated under the assumption of TFE was reported to agree with the reverse characteristics of 100-µmdiameter nickel/GaN Schottky-barrier diodes (SBDs) [20]; however, it did not agree with the reverse characteristics of large (9-mm2) nickel/GaN SBDs [21]. Moreover, in the case of 4H-SiC SBDs, threading-dislocation density was reported to influence the measured reverse characteristic; for example, maximum reverse current density (2 × 10−1 mA/cm2 at 0.6 kV) of 53 molybdenum/4H-SiC SBDs was four-orders-of-magnitude larger than minimum reverse current density (2 × 10−5 mA/cm2 at 0.6 kV) [22] (Figure 8.7). These findings suggest that describing an equation for JTED under the reverse-biased condition with (8.22a) is not much use. Instead, structures that minimize reverse current (namely, insertion of a wider-bandgap

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Pure SBDs

153

Energy (meV)

100

m n = 0.20× 9.1 × 10 −31 kg εr = 10 kT (T = 500K) E 00

10 kT (T = 300K)

kT (T = 15K)

1 10 15

Figure 8.6 tion.

10 16 Donor concentration ND (cm-3)

10 17

Calculated E00 (8.23) versus thermal energy as a function of donor concentra-

53 molybdenum/4H-SiC SBDs N D = 5 ×10 15 cm−3, RT

2

Reverse current density J R (mA/cm )

10 1

Maximum J R

10 −1

10 −3 Minimum J R 10 −5

10 −7

0

0.4 0.8 Reverse voltage VR (kV)

1.2

Figure 8.7 Maximum and minimum reverse current-density/voltage characteristics of molybdenum/4H-SiC SBDs measured at room temperature [22].

or a thin p+-type semiconductor layer, and/or lower E [Figure 8.8]) are introduced after planar SBDs are introduced.

8.7 8.7.1

Pure SBDs Pure GaN SBDs

In 2001, availability of freestanding GaN substrates made it possible to fabricate the 450-V and 700-V vertical GaN SBDs [23, 24], shown in Figure 8.9(a) (hereinafter called pure GaN SBDs), for the first time. The backside ohmic contacts were titanium/aluminum [23] or titanium/aluminum/

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(a) Insertion of a wider bandgap layer

(b) Insertion of a p+-type layer

(c) lower E

E C’’

E C’

EC

Figure 8.8 Schematic conduction-band diagrams for suppressing electron tunneling through a reverse-biased Schottky junction. In (a) and (b), a wider-bandgap semiconductor layer or a thin p+-type layer is inserted at the Schottky junction, while in (c) the electric field (solid line) is lower than those shown in Figure 8.5.

platinum/gold [24], while the Schottky contact was platinum/gold [23] or platinum/titanium/gold [24]. However, ND was relatively large—namely, > 5 × 1016 cm−3 [23], and in the order of 1017 cm−3 [24]. In 2006, ND of 7 × 1015 cm−3 was used for fabricating 600-V pure GaN SBDs on GaN substrates [25, 26]. The first pure GaN SBDs with a lightly doped epitaxial layer (ND = 1 × 1014 cm−3) grown on n+ GaN substrates were fabricated with edge termination (see Chapter 11) by argon-ion implantation [27, 28]. The reported BV was 1.3 kV. Pure SBDs using high-quality GaN (μn = 930 cm2/Vs) were first fabricated in 2010 by using nickel/gold Schottky contact metal and field-plate edge termination [29] (see Chapter 11). BV was 1.1 kV, and forward current IF exceeded 10A with relatively low VF of 1.46V at JF = 500 A/cm2. In 2015, 9-mm2 pure GaN SBDs with both high IF (50A) and high BV (0.79 kV) were fabricated by using nickel Schottky contact metal and mesa field-plate

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Pure SBDs

155

Anode electrode

Schottky contact Ohmic contact

n- GaN n+ GaN substrate Cathode electrode

Forward-current direction

(a) Anode electrode

Anode electrode

n- gradedAlGaN

p+

Anode electrode

p+ SiC

p+ SiC

n- GaN

n-

n- SiC

n+ GaN substrate Cathode electrode

n+ substrate Cathode electrode

n+ SiC substrate Cathode electrode

(b)

(c)

(d)

Anode electrode p+ GaN

p+ GaN

Anode electrode p+ GaN

Anode electrode

p+ GaN p+ SiC

n- GaN n+ GaN substrate Cathode electrode

(e) VF < 3.4 V

n- GaN n+ GaN substrate Cathode electrode

(f) VF > 3.4 V

p+ SiC

n- SiC n+ SiC substrate Cathode electrode

(g)

Figure 8.9 Cross-sectional schematic illustrations of active regions of SBDs: (a) pure SBD, (b) SBD with a wider-bandgap layer, (c) SBD with a thin p+-type layer, (d) trench SBD with a thin p+-type region, (e, f) GaN merged p-n Schottky (MPS) diode, and (g) 4H-SiC junctionbarrier Schottky (JBS) diode.

edge termination [21] (see Chapter 11). As shown in Figure 8.10(a), VF was 1.30V for a typical limit on power dissipation of a semiconductor package (PP = 300 W/cm2 [30]). With increasing temperature, μn decreases as a result of phonon scattering. Dependence of qΦB on temperature (348–573K) was analyzed by fitting measured IF/VF characteristics of a nickel/n-GaN pure SBD on the basis of the TED model [12]. 8.7.2

Pure 4H-SiC SBDs

The first-reported high-voltage pure SiC SBDs with low VF (1.1 V at JF = 100 A/cm2) were 6H polytype [31]. The Schottky metal was platinum, and BV was 400V. BV was later improved with edge termination using argon-ion implantation [32] (see Chapter 11). With respect to pure 4H-SiC SBDs, BV

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Forward current density JF (A/cm2)

Forward current density JF (A/cm2)

2

Forward current density JF (A/cm )

156

400 300 W/cm2

300 200

100 9-mm2 0.79-kV pure GaN SBD

0 0.5

1.30 1.5 1 Forward voltage VF (V) (a)

2

400 300 W/cm2

300

200

100 8-mm2 1.7-kV pure 4H-SiC SBD

0 0.5

1.401.5 1 Forward voltage VF (V) (b)

2

400 300 W/cm2

300 200

100 0.64-mm2 0.4-kV gradedAlGaN SBD

0 0.5

1.401.5 1 Forward voltage VF (V) (c)

2

Figure 8.10 Forward-current-density/voltage characteristics of (a) 9-mm2 0.79-kV pure GaN SBD [21], (b) 8-mm2 1.7-kV pure 4H-SiC SBD [33], and (c) graded AlGaN SBD [34] measured at room temperature.

ranging from 1.5 to 2.5 kV with VF of 2.4V at JF = 100 A/cm2 [35], BV of 4 kV with VF of 6V at JF = 100 A/cm2 [36], and BV of 4.9 kV with VF of 2.4V at JF = 25 A/cm2 [37] were achieved by using nickel Schottky contact metal. Pure molybdenum/4H-SiC SBDs with BV of 4.15 kV with VF of 1.89V at JF = 100 A/cm2 were also fabricated [38].

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8.8

Graded AlGaN SBDs

157

As an example of pure 4H-SiC SBDs with large IF, JF-VF characteristics of a reported 8-mm2 1.7-kV SBD [32] are shown in Figure 8.10(b). According to Figure 8.10(b), VF is 1.40V for PP of 300 W/cm2.

8.8

Graded AlGaN SBDs

With respect to vertical SBDs with a wider-bandgap layer (Figure 8.9[b]), GaN SBDs with a graded AlGaN layer have been fabricated by using palladium [39] and nickel/gold [33] Schottky contact metals. Due to the existence of oxygen shallow donors (e.g., energy depth of 0.03 eV [40, 41] for Al0.26Ga0.74N) that reduce qΦB (thin-surface-barrier [TSB] model) [42], however, analyzing their JR/VR characteristics tends to be complicated [39]. As shown in Figure 8.10(c), VF of a reported 0.64-mm2 0.4-kV graded AlGaN SBD [32] is 1.40V (for PP of 300 W/cm2), which is 0.1V larger than VF of the pure GaN SBD shown in Figure 8.10(a).

8.9

4H-SiC SBDs with a Thin p+-Type Layer

With respect to a SBD with a p+-type layer (thickness: a) (Figure 8.9[c]), an idealized profile of net donor concentration (ND−NA) is shown in Figure 8.11(a). Distribution of electric field E shown in Figure 8.11(b) is expressed as

E = Emax−qpx/εrεo for 0 < x < a

= −qnx(WDn−x)/εrεo for a < x < WDn

(8.24)

where Emax is given as Emax = q[−pa+n(WDn−x)]/εrεo

(8.25)

Conduction-band minimum (EC) reaches a maximum at x = b, where b = [ap−(WDn−x)n]/p

(8.26)

ΦB is thus increased from ΦB of a SBD without a thin p+-type layer by ΔΦB = Emaxb−qpb2/2εrεo

(8.27)

When p and ap are designed to be much larger than n and WDnn, respectively, ΔΦB approaches ΦB+qpa2/2εrεo; namely, effective ΦB increases (Figure 8.11[c]).

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Vertical GaN and SiC Power Devices

N D−N A

n a

x WDn

p E E max

b a

x WDn

EC qΔφB

qφB

ba

WDn

x

Figure 8.11 Distributions of (a) idealized profile of net donor concentration, (b) electric field, and (c) conduction-band minimum.

An SBD with a thin p+-layer, namely, a 4H-SiC trench SBD in which the trenches extend into the p+-type regions (Figure 9.9[d]), has been demonstrated. As simulated in the case of 0.6-kV class SBDs [43], the region where |E| exceeds 1.5 MV/cm appears below the bottom of the trenches of the trench SBD, while it appears around the Schottky junction of the planar SBD (Figure 8.12). At a reverse bias of 0.6 kV, Emax at the Schottky junction of the trench SBD is 0.68 MV/cm, which is less than half that of the planar SBD (1.65 MV/cm) [43]. In the case of a 5-μm-thick n-type drift layer (ND = 1.0 × 1016 cm−3), metal with large ΦB (e.g., 1.31V) is needed to suppress

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Shielded Planar SBDs

0

159

Anode electrode

0

Anode electrode

Depth ( μm)

Depth ( μm)

> 1.5 MV/cm

2

4

−2 0 2 Lateral dimension ( μm) (a)

2 > 1.5 MV/cm

4

−2 0 2 Lateral dimension ( μm) (b)

Figure 8.12 Simulated distributions of regions where electric-field strength exceeds 1.5 MV/cm in 0.6-kV reverse-biased (a) planar and (b) trench SBDs with a thin p+-type layer [43].

reverse leakage at 0.6 kV. Owing to the combination of a thin p+-region and a trench structure, metal with small ΦB (0.85V) was successfully formed on the drift layer with 1.05-μm-deep trenches; namely, VF was reduced by 0.48V, while comparable reverse leakage was kept at 0.6 kV (i.e., < 1 × 10−6A for a 3.06-mm2 chip) [43]. Reported current/voltage characteristics of a 4H-SiC trench SBD with + a p -type region [43] and a 0.79-kV pure GaN SBD [21] are shown in Figure 8.13. Under the condition of PP = 300 W/cm2, VF of the 4H-SiC trench SBD with a p+-type region (1.03V) is 0.27V lower than that of the pure GaN SBD (Figure 8.13[a]). With respect to reverse characteristics, both SBDs have practically low leakage-current-density (< 1 mA/cm2) (Figure 8.13[b]); however, JR at VR = 0.7 kV of the pure GaN SBD is about six times larger than that of the 4H-SiC trench SBD with a p+-type region. Note that although it is possible to fabricate GaN trench SBDs by using ICP etching and wet etching (Section 7.2), it is difficult to fabricate GaN trench SBDs with a thin p+-type region due to the difficulty of increasing the activation ratio of ion-implanted magnesium acceptors (Section 7.3.1).

8.10

Shielded Planar SBDs

A shielding technique to reduce |E| at the Schottky junction of trench SBDs with a thin p+-type region has also been applied to planar SBDs by alternately forming Schottky and p-n junctions (Figure 8.9[e−g]). The shielded planar SBDs whose anode metal and p-n junctions make ohmic contacts are called merged p-n Schottky (MPS) diodes. On the other hand, the shielded planar SBDs whose anode metal and p-n junctions make Schottky contacts are called JBS diodes. Forward current flows through the Schottky junctions only in the case of MPS diodes and junction barrier Schottky (JBS)

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Vertical GaN and SiC Power Devices

Forward current density JF (A/cm2)

160

600 600

300 W/cm2

9-mm2 pure GaN SBD mm2

3.06 4H-SiC trench SBD

400 400

300 230 200 200

00 0.5

0.5

1 1.03

1

1.30

1.5

2

1.5

2

Forward voltageVF (V)

Reverse current density JR (A/cm2)

(a) 1.E −2 10-02

9-mm2 pure GaN SBD −3 1.E 10-03

× 5.9

−4 1.E 10-04

3.06 mm2 4H-SiC trench SBD

−5 10-05 1.E

500

500

600

600

700

700

800

800

Reverse voltage VR (V) (b)

Figure 8.13 Room-temperature (a) forward and (b) reverse current-density/voltage characteristics of the reported 0.7-kV-class 4H-SiC trench SBD with a thin p+-type layer [43] and pure SBD [21].

diodes when VF < Eg/q (Figure 8.9[e, g], respectively). In contrast, forward current also flows through the p-n junctions of MPS diodes when VF > Eg/q (Figure 8.9[f]). The electron-hole recombination energy is known to be used often for creating defects [44] (see Section 12.6). Since the stacking-fault energy of 4H-SiC (0.014 J/m2 [45]) is much smaller than that of GaN (1.2 J/m2 [46]) (Section 2.2.3), a JBS diode is preferred to an MPS diode in the case of 4H-SiC diodes. With respect to shielded GaN SBDs, on the other hand, MPS diodes, in which p+-type regions exist in the active area, are preferred because using magnesium-ion implantation in the edge-termination area is difficult.

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8.10

Shielded Planar SBDs

8.10.1

161

GaN merged p-n Schottky diodes

GaN MPS diodes (Figure 8.9[e, f]) have been fabricated, and their current/ voltage characteristics were compared with those of pure GaN SBDs and GaN p-n diodes [47]. As shown in Figure 8.14(a), the turn-on voltage of GaN MPS diodes (0.8V) agrees with that of pure GaN SBDs. Although JF of pure GaN SBDs saturates around 4.4 kA/cm2, JF of GaN MPS exponentially increases due to current flow through the p-n junctions. BV of GaN MPS diodes is 1.6 kV, which lies between BV of pure GaN SBDs and BV of GaN p-n diodes (Figure 8.14[b]). 8.10.2

4H-SiC JBS Diodes

2

Reverse current density JR (A/cm )

2

Forward current density JF (kA/cm )

In JBS diodes, regions of p+-n and Schottky junctions are alternated to shield the Schottky junction against a high electric field [48] (Figure 8.9[g]). The

9 p-n diode

MPS diode

6

SBD 3

0

3 6 Forward voltageVF (V) (a)

0.8

9

40 SBD

MPS diode

p-n diode

30

20

10

00

0.6

1.6 1.8 1.2 Reverse voltage VR (V) (b)

2.4

Figure 8.14 Room-temperature (a) forward and (b) reverse current-density/voltage characteristics of reported 0.01-mm2 GaN MPS diode [47].

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Vertical GaN and SiC Power Devices

Forward current density JF (A/cm2)

space between the p+-type regions is chosen so as not to prevent unipolar conduction in the on-state. The first high-voltage SiC JBS diodes were reported in 1998 [49, 50]. BV of 0.7 kV was achieved with a 9-μm-thick drift layer doped at 3 × 1015 cm−3 [50]. BV of 4H-SiC JBS diodes was then improved to 2.8 kV with a 27-μm-thick drift layer doped at 3 × 1015 cm−3 [51], 4.3 kV with a 30-μm-thick drift layer doped at 2 × 1015 cm−3 [52], and 10 kV with a 120-μm-thick drift layer doped at 6 × 1014 cm−3 [53]. 4H-SiC JBS diodes have been implanted with aluminum ion (see Section 7.3.2). JF/VF characteristics of these 4H-SiC JBS diodes were thus analyzed by assuming the ratio of the laterally extended length to the vertical depth of the p+-n junction (r) to be 85% in the case of silicon JBS diodes [54] and 1.5% in the case of 4H-SiC JBS diodes [55]. The much smaller r in the latter case originates from the extremely low diffusivity of aluminum [56]. On the other hand, the vertical concentration profile of implanted aluminum in 4H-SiC results in an extended tail due to channeling (see Section 7.3.2). Furthermore, according to two-dimensional Monte Carlo simulation, implanted aluminum ions and implantation-induced point defects laterally spread from the edge of the implantation mask [57–59]. To take such effects into account is thus important when the spacing between the p+-type regions in 4H-SiC JBS diodes is reduced. For example, 4H-SiC JBS diodes with 2-μm-wide p+ stripe regions separated by 1 μm and nickel/4HSiC SBDs were experimentally and computationally investigated [57]. As for an example of a 22-μm-thick drift layer doped with silicon at 3 × 1015 cm−3, the measured JF/VF characteristics of a 1.8-mm2 nickel/4H-SiC SBD (open circles) are reproduced with a simulation that assumes qΦB of 1.59 eV and a uniform μn of 840 cm2/Vs (dashed line) (Figure 8.15). However,

150

Fitted SBD with uniform mobility

1.8-mm2 4H-SiC diodes 3 × 10 15 cm-3/22 μm drift layer 100 qφB = 1.59 eV room temperature

JBS diode fitted with uniform mobility

JBS diode fitted with degraded mobility in surface region

50 50

0 1

2

3

Forward voltage VF(V)

Figure 8.15 Forward-current-density/voltage characteristics of measured (symbols) and simulated (lines) nickel/4H-SiC SBD and JBS diodes with a 22-μm-thick drift layer doped at 3 × 1015 cm−3. Simulation is carried out by assuming uniform μn of 840 cm2/Vs (dashed and dotted lines) or degraded μn of 450 cm2/Vs in the 0.23-μm-thick surface region (solid line).

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8.11

Summary

163

when measured JF/VF characteristics of 1.8-mm2 4H-SiC JBS diodes were simulated under the same assumption, JF was overestimated (dotted line). A two-layer model taking into account the lateral spreading of implantation-induced point defects was thus proposed [57]. According to the model, since the region with significant lateral spreading of interstitials is shallower than 0.23 µm, μn in the surface region was considered to be degraded. The measured JF/VF characteristics of a 1.8-mm2 4H-SiC JBS diode (solid circles) are successfully reproduced with a simulation that assumes μn of 450 cm2/ Vs in the region shallower than 0.23 μm and 840 cm2/Vs in the region deeper than 0.23 μm (dashed line).

8.11

Summary

The first half of this chapter explains the physics of metal-semiconductor contacts, including Schottky-barrier lowering, as well as the current-transport theories based on diffusion and thermionic-emission diffusion. Compared to conventional pure SBDs, SBDs with structures with a thin p+-type or wider-bandgap layer and/or with a reduced electric field are better approaches from the viewpoint of decreasing reverse leakage. The second half of this chapter introduces graded AlGaN SBDs, 4H-SiC trench SBDs with a thin p+-type region, GaN MPS diodes, and 4H-SiC JBS diodes, in addition to pure GaN and 4H-SiC SBDs.

References [1] Mochizuki, K., et al., “Influence of Surface Recombination on Forward Current−Voltage Characteristics of Mesa GaN p+n Diodes Formed on GaN Freestanding Substrates,” IEEE Transactions on Electron Devices, Vol. 59, No. 4, 2012, pp. 1091–1098. [2] Monemar, B., et al., “Recombination of Free and Bound Excitons in GaN,” Physica Status Solidi B, Vol. 245, No. 9, 2008, pp. 1723–1740. [3] Schottky, W., “Halbleitertheorie der Sperrschicht,” Naturwissenschaften, Vol. 26, No. 52, 1938, pp. 843–843. [4] Bethe, H. A., “Theory of the Boundary Layer of Crystal Rectifiers,” MIT Radiation Laboratory Report, Vol. 185, No. 43, 1943, pp. 12−57. [5] Baliga, B. J., Gallium Nitride and Silicon Carbide Power Devices, Singapore: World Scientific, 2017, p. 79. [6] Jacoboni, C., et al., “A Review of Some Charge Transport Properties of Silicon,” Solid-State Electronics, Vol. 20, No. 2, 1977, pp. 77–89. [7] Bhapkar, U. V., and M. S. Shur, “Monte Carlo Calculation of Velocity-Field Characteristics of Wurtzite GaN,” Journal of Applied Physics, Vol. 82, No. 4, 1997, pp. 1649–1655.

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[8] Khan, I. A, and J. A. Cooper, “Measurement of High Field Electron Transport in Silicon Carbide,” Materials Science Forum, Vol. 264–268, 1998, pp. 509–512. [9] Rodrigues, C. G., Á. R. Vasconcellos, and R. Luzzi, “Nonlinear Charge Transport in III-V Semiconductors: Mobility, Diffusion, and a Generalized Einstein Relation,” Journal of Applied Physics, Vol. 99, 2006, pp. 073701-1–073701-12. [10] Baliga, B. J., Gallium Nitride and Silicon Carbide Power Devices, Singapore: World Scientific, 2017, p. 32. [11] Mochizuki, K., et al., “Numerical Determination of Schottky Barrier Height of Nickel/n-Type Gallium Nitride Diodes Formed on Freestanding Substrate,” Journal of Modern Mathematics Frontier, Vol. 3, No. 2, 2014, pp. 29−33. [12] Maeda, T., et al., “Temperature Dependence of Barrier Height in Ni/nGaN Schottky Barrier Diode,” Applied Physics Express, Vol. 10, 2017, pp. 051002-1−051002-4. [13] Mochizuki, K., et al., “Influence of Lateral Spreading of Implanted Aluminum Ions and Implantation-Induced Defects on Forward Current−Voltage Characteristics of 4H-SiC Junction Barrier Schottky Diodes,” IEEE Transactions on Electron Devices, Vol. 56, No. 5, 2009, pp. 992−997. [14] Pearton,, S. J, C. A. Abernathy, and F. Ren, Gallium Nitride Processing for Electronics, Sensors and Spintronics, London: Springer-Verlag, 2006, p. 44. [15] Baliga, B. J., Gallium Nitride and Silicon Carbide Power Devices, Singapore, World Scientific, 2017, pp. 147−172. [16] Baliga, B. J., Silicon Carbide Power Device, Singapore: World Scientific, 2005, p. 85. [17] Kimoto, T., and J. A. Cooper, Fundamentals of Silicon Carbide Technology, Singapore: John Wiley & Sons, 2014, p. 249 and pp. 282−286. [18] Crowell, C. R., and S. M. Sze, “Current Transport in Metal-Semiconductor Barriers,” Solid-State Electronics, Vol. 9, No. 11−12, 1966, pp. 1035−1048. [19] Itoh, A., T. Kimoto, and H. Matsunami, “High Performance of High Voltage 4H-SiC Schottky Barrier Diodes,” IEEE Electron Device Letters, Vol. 16, No. 6, 1995, pp. 280−282. [20] Suda, J., et al., “Nearly Ideal Current-Voltage Characteristics of Schottky Barrier Diodes Formed on Hydride-Vapor-Phase-Epitaxy-Grown GaN Freestanding Substrates,” Applied Physics Express, Vol. 3, 2010, pp. 101003-1−101003-3. [21] Tanaka, N., et al., “50 A Vertical GaN Schottky Barrier Diode on a Freestanding GaN Substrate with Blocking Voltage of 790V,” Applied Physics Express, vol. 8, 2015, pp. 071001-1−071001-3. [22] Fujiwara, H., et al., “Relationship Between Threading Dislocation and Leakage Current in 4H-SiC Diodes,” Applied Physics Letters, Vol. 100, 2012, pp. 242102-1−242102-4. [23] Johnson, J. W., et al., “Schottky Rectifiers Fabricated on Freestanding GaN Substrates,” Solid-State Electronics, Vol. 45, No. 3, 2001, pp. 405–410. [24] Zhang, A. P., et al, “Vertical and Lateral GaN Rectifiers on Freestanding GaN Substrates,” Applied Physics Letters, Vol. 79, No. 10, 2001, pp. 1555–1557.

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[25] Zhou, Y., et al., “High Breakdown Voltage Schottky Rectifier Fabricated on Bulk n-GaN Substrate,” Solid-State Electronics, Vol. 50, No. 11–12, 2006, pp. 1744–1747. [26] Zhou, Y., et al., “Temperature-Dependent Electrical Characteristics of Bulk n-GaN Schottky Rectifier,” Journal of Applied Physics, Vol. 101, 2007, pp. 024506-1–024506-4. [27] Ozbeck, A. M., and B. J. Baliga, “Planar Nearly Ideal Edge Termination Technique for GaN Devices,” IEEE Electron Device Letters, Vol. 32, No. 3, 2011, pp. 300–302. [28] Ozbeck, A. M., and B. J. Baliga, “Finite-Zone Argon Implant Edge-Termination for High-Voltage GaN Schottky Rectifiers,” IEEE Electron Device Letters, Vol. 32, No. 10, 2011, pp. 1361–1363. [29] Saitoh, Y., et al., “Extremely Low On-Resistance and High Breakdown Voltage Observed in Vertical GaN Schottky Barrier Diodes with High-Mobility Drift Layers on Low-Dislocation-Density GaN Substrates,” Applied Physics Express, Vol. 3, 2010, pp. 081001-1–081001-3. [30] Zhang, Q., et al., “12-kV p-Channel IGBTs with Low On-Resistance in 4HSiC,” IEEE Electron Device Letters, Vol. 29, No. 9, 2008, pp. 1027–1029. [31] Bhatnagar, M, P. K. McLarty, and B. J. Baliga, “Silicon Carbide High Voltage (400 V) Schottky Barrier Diodes,” IEEE Electron Device Letters, Vol. 13, No. 10, 1992, 501–503. [32] Alok, D., B. J. Baliga, and P. K. McLarty, “A Simple Edge Termination for Silicon Carbide with Nearly Ideal Breakdown Voltage,” IEEE Electron Device Letters, Vol. 15, No. 10, 1994, pp. 394–395. [33] Miura, N., et al., “4H-SiC Power Metal–Oxide–Semiconductor Field Effect Transistors and Schottky Barrier Diodes of 1.7 kV Rating,” Japanese Journal of Applied Physics, Vol. 48, 2009, pp. 04C085-1–04C085-4. [34] Hontz, M. R., et al., “Modeling and Characterization of Vertical GaN Schottky Diodes with AlGaN Cap Layers,” IEEE Transactions on Electron Devices, Vol. 64, No. 5, 2017, pp. 2172–2178. [35] Chilukuri, R. K., and B. J. Baliga, “High Voltage Ni/4H-SiC Schottky Rectifiers,” International Symposium on Power Semiconductor Devices and ICs, Toronto, May 26–28, 1999, pp. 161–164. [36] McGlothlin, H. M., et al., “4 kV Silicon Carbide Schottky Diodes for High Frequency Switching Applications,” IEEE Device Research Conference, Santa Barbara, June 28–30, 1999, pp. 42–43. [37] Singh, R., et al., “SiC Power Schottky and PiN Diodes,” IEEE Transactions on Electron Devices, Vol. 49, No. 4, 2002, pp. 665–672. [38] Nakamura, T., et al., “A 4.15 kV 9.07 mΩ-cm2 4H-SiC Schottky Barrier Diode Using Mo Contact Annealed at High Temperature,” IEEE Electron Device Letters, Vol. 26, No. 2, 2005, pp. 99–101. [39] Mochizuki, K., et al., “Analysis of Leakage Current at Pd/AlGaN Schottky Barriers Formed on GaN Freestanding Substrates,” Applied Physics Express, Vol. 4, No. 2, 2011, pp. 024104-1–024104-3.

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[40] Ploog, K. H., and O. Brandt, “Doping of Group III Nitrides,” Journal of Vacuum Science and Technology A, Vol. 16, No. 3, 1997, pp. 1609–1614. [41] Ptak, A. J., et al., “Controlled Oxygen Doping of GaN Using Plasma Assisted Molecular-Beam Epitaxy,” Applied Physics Letters, Vol. 79, No. 17, 2001, pp. 2740–2742. [42] Hasegawa, H., and S. Oyama, “Mechanism of Anomalous Current Transport in n -Type GaN Schottky Contacts,” Journal of Vacuum Science and Technology B, Vol. 20, No. 4, 2002, pp. 1647–1655. [43] Nakamura, T., et al., “High Performance SiC Trench Devices with Ultra-low Ron,” International Electron Devices Meeting, Washington, D.C., Dec. 5–7, 2011, pp. 599–601. [44] Kimmering, L. C., “Recombination Enhanced Defect Reactions,” Solid-State Electronics, Vol. 21, 1978, pp. 1391–1401. [45] Hong, M. H., et al., “Stacking Fault Energy of 6H-SiC and 4H-SiC Single Crystals,” Phylosophical Magazine A, Vol. 80, No. 4, 2000, pp. 919–935. [46] Stampfl, C., and C. G. Van de Walle, “Energetics and Electronic Structure of Stacking Faults in AlN, GaN, and InN,” Physical Review B, Vol. 57, No. 24, 1998, pp. R15052–R15055. [47] Kajitani, R., et al., “A High Current Operation in a 1.6 kV GaN-Based Trenched Junction Barrier Schottky Diode,” Solid State Devices and Materials, Sapporo, Sept. 27–30, 2015, pp. 1056–1057. [48] Baliga, B. J., “The Pinch Rectifier: A Low Forward Drop High Speed Power Diode,” IEEE Electron Device Letters, Vol. 5, No. 6, 1984, pp. 843–843. [49] Held, R., N. Kaminski, and E. Niemann., “SiC Merged p-n/Schottky Rectifiers for High Voltage Applications,” Materials Science Forum, Vol. 264–268, 1998, pp. 1057–1060. [50] Dahlquist, F., et al., “Junction Barrier Schottky Diodes in 4H-SiC and 6H-SiC,” Materials Science Forum, Vol. 264–268, 1998, pp. 1061–1064. [51] Dahlquist, F., et al., “A 2.8 kV JBS Diode with Low Leakage,” Materials Science Forum, Vol. 338–342, 2000, pp. 1179–1182. [52] Wu, J., et al., “4,308 V, 20.09 mΩcm2 4H-SiC MPS Diodes Based on a 30 Micron Drift Layer,” Materials Science Forum, Vol. 457–460, 2004, pp. 1109–1112. [53] Hull, B. A., et al., “Performance and Stability of Large Area 4H-SiC 10-kV Junction Barrier Schottky Rectifiers,” IEEE Transactions on Electron Devices, Vol. 55, No. 8, 2008, pp. 1864–1870. [54] Baliga, B. J., “Analysis of Junction-Barrier-Controlled Schottky (JBS) Rectifier Characteristics,” Solid-State Electronics, Vol. 28, No. 11, 1985, pp. 1089–1093. [55] Zhu, L., and T. P. Chow, “Analytical Modeling of High-Voltage 4H-SiC Junction Barrier Schottky (JBS) Rectifiers,” IEEE Transactions on Electron Devices, Vol. 55, No. 8, 2008, pp. 1857–1863. [56] Negoro, Y., T. Kimoto, and H. Matsunami, “Carrier Concentration Near Tail Region in Aluminum- or Boron-Implanted 4H-SiC (0001),” Journal of Applied Physics, Vol. 98, No. 4, 2005, pp. 043709-1–043709-7.

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[57] Mochizuki, K., et al., “Influence of Lateral Spreading of Implanted Aluminum Ions and Implantation-Induced Defects on Forward Current–Voltage Characteristics of 4H-SiC Junction Barrier Schottky Diodes,” IEEE Transactions on Electron Devices, Vol. 56, No. 5, 2009, pp. 992–997. [58] Mochizuki, K., et al., “A Commercial-Simulator-Based Numerical-Analysis Methodology for 4H-SiC Power Device Formed on Misoriented (0001) Substrates,” IEEE Journal of the Electron Devices Society, Vol. 3, 2015, pp. 316–322. [59] Mochizuki, K., et al., “Uniform Luminescence at Breakdown in 4H-SiC 4Ω-off (0001) p–n Diodes Terminated with an Asymmetrically Spaced Floating-Field Ring,” IEEE Journal of the Electron Devices Society, Vol. 3, 2015, pp. 349–354.

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CHAPTER

9 Contents 9.1 Introduction 9.2 MIS Capacitors 9.3 AlGaN/GaN Heterostructures

Metal-Insulator-Semiconductor Capacitors and Unipolar PowerSwitching Devices

9.4 Band Lineup for GaN, AlN, 4H-SiC, and Representative Insulators 9.5 GaN HFETs 9.6 4H-SiC JFETs 9.7 MISFETS 9.8 Summary

9.1

Introduction

As described in Section 7.5.2, SiC can be thermally oxidized in the same manner as silicon, except for the simultaneous production of CO. On the other hand, a deposited SiNx or Al2O3 layer is frequently used as an insulator on GaN and AlGaN (see Section 7.5.1). Therefore, in this chapter, MIS is used for GaN and SiC and metal-oxide-semiconductor (MOS) is used for silicon only. Unipolar power-switching devices include the MISFET and the static-induction transistor (SIT) [1], which consists of a p-n-junction-gate SIT (also called a junction field-effect transistor [JFET]), a Schottky-junction-gate SIT (also called a metal-semiconductor field-effect transistor [MESFET]), and a p+-gate SIT (also called

169

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a p+-gate FET). With respect to JFETs, 0.6-kV-class 4H-SiC products are commercially available; however, most of them have normally-on characteristics (Figure 9.1[a]), which are an impediment to some circuit applications [2]. Although conventional MESFETs also have normally-on characteristics, V-grooved AlGaN/GaN MESFETs were reported to exhibit normally-off characteristics (Figure 9.1[b]) [3]. Therefore, this chapter focuses on MISFETs, MESFETs, and p+-gate FETs. A brief review of the physics of MIS capacitors is followed by an introduction to GaN heterojunction FETs (HFETs), 4H-SiC JFETs, and GaN and 4H-SiC MISFETs, including those with trenched-gate and SJ structures (see Sections 6.6 and 7.2.1).

9.2

MIS Capacitors

9.2.1

Idealized MIS Capacitors

J D (A/cm2)

J D (A/cm2)

A MIS capacitor is a capacitor formed from metal, insulator, and semiconductor layers. Although the MIS capacitor has been directly applied to, for example, charge-coupled devices for optical imaging and signal processing, it is not only the basic building block of MISFETs but also the most useful tool to study semiconductor surfaces. Section 8.1 considers a metal/n-type semiconductor contact; in contrast, this section studies a metal/insulator (thickness: d)/p-type semiconductor structure. The structure is assumed to have no charges in the insulator and no interface states or fixed charges at the insulator/p-type semiconductor interface. (The influence of insulator and fixed charges on the MIS structure is described in the Section 9.2.2.) As described in Section 8.1, electron affinity [qΧi for the insulator and qΧ for the p-type semiconductor shown in Figure 9.2(a)] is the difference between the vacuum level

VGS = 0

R on A (mΩcm2) VGS < Vth < 0

R on A (mΩcm2) BV VDS (V)

O (a)

VGS > Vth > 0

0 < VGS < Vth O

BV VDS (V)

(b)

Figure 9.1 Schematic drain current-density (JD)/drain-source voltage (VDS) characteristics of (a) normally-on and (b) normally-off power-switching devices. Vth denotes the threshold voltage explained in Section 9.2.1.

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MIS Capacitors

171

qφ ms = qφ m−qX−

Eg −q ψF 2

vacuum level qXi qφ m

qX

qψ F

q φms d

EC

EC

Ei EF EV

Ei EF EV

(a)

(b)

EC qφ ms < 0

Ei EF EV

qψS < 0 EC

qV < 0

qψF

(c)

Ei EF EV

(d)

qV > 0

0 < qψS < qψF EC qψF Ei EF EV

qψS = 2qψF EC qψ F Ei EF EV

qV > 0

WDp (e)

(f)

Figure 9.2 Energy-band diagrams of a metal, insulator, and p-type semiconductor when the metal work function is lower than the semiconductor work function: (a) separated, (b) connected with zero bias, and (c) connected with flat-band bias and the bias conditions of (d) accumulation, (e) depletion, and (f) inversion.

and conduction-band minimum EC. Since the intrinsic Fermi level Ei, which is the Fermi level of an intrinsic semiconductor, lies in the middle of bandgap Eg, the work function of the p-type semiconductor, qΦs, is expressed as

qΦs = qΧ + (Eg/2) + qΨF

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where ΨF is the Fermi potential defined as the difference between Ei/q and EF/q and can be calculated from ionized acceptor concentration NA- and intrinsic carrier concentration ni (see Section 2.4) as [4] ΨF = (kT/q) ln(NA−/ ni)

(9.2)

When the metal work function, qΦm, is lower than qΦs, the energy bands bend downward [Figure 9.2(b)]. Since the difference between the work functions of a metal and a p-type semiconductor, qΦms, is given as qΦms = qΦm−qΧ−(Eg/2) −qΨF

(9.3)

the flat-band condition (Figure 9.2[c]) is realized when flat-band voltage VFB = Φms (< 0) is applied to the metal, and the p-type semiconductor is grounded. If the p-type semiconductor is held at ground and voltage V applied to the metal is kept negative but increased in magnitude above |Φms|, the surface potential ΨS, which is defined as the total band bending from the substrate to the surface, becomes negative [Figure 9.2(d)]. Since no current flows in the MIS structure, EF remains flat, resulting in an accumulation of holes near the surface of the p-type semiconductor (a so-called accumulation case). When V is positive, on the other hand, the bands bend downward. When V is so small that the condition 0 < ΨS < ΨF is satisfied (Figure 9.2[e]), holes are depleted from the surface of the p-type semiconductor (a so-called depletion case). Similar to (3.30), depletion width WDp is given as WDp = [2εrεoΨS/qNA]0.5

(9.4)

Total charge in the depletion region, QD, can be obtained as QD = −qNAWDp = −[2qεrεoNAΨS]0.5

(9.5)

which is balanced by a positive sheet charge on the metal surface. When V is large enough for Ei at the surface of the p-type semiconductor to cross over EF, ΨS becomes 2ΨF (Figure 9.2[f]); namely, electron concentration at the surface of the p-type semiconductor equals hole concentration in the bulk. The voltage at which this state occurs is known as the threshold voltage Vth. The condition V > Vth is called the inversion case. Once the p-type semiconductor is biased into inversion, electron concentration at the surface of the p-type semiconductor becomes an approximate exponential function of ΨS, which thus changes little with increasing V. As

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MIS Capacitors

173

a result, WDp and total potential drop across the depletion region (2 F) are relatively constant. 9.2.2

Influence of Insulator and Fixed Charges on MIS Capacitors

The effect of insulator charge is first treated one-dimensionally [5]. The case that a density of charge QI is located on plane x = xI (0 ≤ xI ≤ d) is considered, as shown in Figure 9.3(a). The charge at xI induces equal and opposite charges that are divided between the p-type semiconductor and the metal. A shift in VFB (ΔVFB) can be obtained by using Gauss’s law as follows. The constant electric field EI between the metal (x = 0) and QI (x = xI) (Figure 9.3[b]) is given as EI = −QI/εIεo

Charge

(9.6)

QI

QI = −Qm−QD d O

WDp QD

xI

x

Qm Metal

Insulator

p-type semiconductor

Electric field

(a)

O

Metal

xI

d

Insulator

WDp

x

p-type semiconductor (b)

Figure 9.3 Schematic illustrations for analyzing the effect of an insulator-charge density QI on MIS structure. (a) Charge configuration at zero bias (QI = −Qm − QD) and (b) electricfield distribution at zero bias.

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where εI is the relative permittivity of the insulator. ΔVFB is thus obtained as ΔVFB = xIEI = −xIQI/εIεo

(9.7)

Since insulator capacitance per unit area (CI) is given as CI = εIεo/d

(9.8)

(9.7) can be expressed as ΔVFB = −xIQI/CId

(9.9)

which reaches a maximum when xI = d. The above equations can be generalized for ΔVFB by an arbitrary distribution of charge ρ(x) by superimposing and integrating the increments that result from charges distributed throughout the insulator as follows: ΔVFB = − (1/ C I ) ∫

xI

0

( x / x I ) ρ(x)dx

(9.10)

In contrast, fixed charge at the insulator/p-type semiconductor interface (Qf) contributes to ΔVFB through −Qf/CI. Therefore, VFB, which includes the effects of Φms, insulator charge, and interface charge, can be written as ΔVFB = Φ ms − (1/ C I ) ∫

xI

0

9.3

( x / x I ) ρ(x)dx − Q f / C I

(9.11)

AlGaN/GaN Heterostructures

Distribution of conduction-band edge EC of a typical AlGaN/GaN heterostructure formed on GaN (0001) is shown in Figure 9.4(a). Both spontaneous and piezoelectric polarizations are known to induce charges in this material system [6]. The wider bandgap of AlGaN creates a conductionband discontinuity, ΔEC, which leads to formation of a two-dimensional electron gas (2DEG). As described in Section 8.8, oxygen-related shallow donors (e.g., with energy depth ESD of 0.03 eV [7, 8] for Al0.26Ga0.74N) exist on the AlGaN surface, so the Fermi level is pinned at ESD. On the AlGaN surface, polarization charge −σAlGaN balances qNSD+, where NSD+ is ionized surface-donor concentration (Figure 9.4[b]). Since at the AlGaN/GaN interface, 2DEG charge −σ2DEG and polarization charge −σGaN balance polarization charge +σAlGaN, σ2DEG is given as

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9.4

Band Lineup for GaN, AlN, 4H-SiC, and Representative Insulators

P SP AlGaN P PE

175

P SP GaN

AlGaN

EC ΔE C

(0001) surface E SD

EF

AlGaN

GaN (a)

+qNSD + +σAlGaN +σGaN

−σGaN −σ2DEG −σAlGaN (b)

Figure 9.4 Distribution of (a) conduction-band edge and (b) interface charges of a typical AlGaN/GaN heterostructure formed on GaN (0001). (PSP: spontaneous polarization; PPE: piezoelectric polarization.)

σ2DEG = σAlGaN−σGaN

(9.12)

Sheet-electron concentration ns and electron mobility μn of a 2DEG formed on GaN (0001) and Si (111) substrates were measured [9]. While nsGaN(0001) was similar to nsSi(111) (5.6−5.7 × 1012 cm−2), μnGaN(0001) (1,900 cm2/Vs) was 30% larger than μnSi(111) (1,450 cm2/Vs) due to improved GaN crystal quality. This 2DEG sheet resistance, ρ2DEGGaN(0001), of 580 Ω/sq is used for estimating specific on-resistance RonA in Section 9.5.1.

9.4 Band Lineup for GaN, AlN, 4H-SiC, and Representative Insulators Figure 9.5, based on [10−14], summarizes a band lineup for GaN, AlN, 4HSiC, and representative insulators. With respect to an insulator for GaN MIS capacitors, SiNx [15], Al2O3 [16, 17], and HfO2 [18] have been adopted. It was reported that high-density mid-gap states existed at the Al2O3/(Al)GaN interface [19] probably due to Ga−O bond formation [20]. To reduce the influence of such Ga−O bond formation, in-situ NH3-plasma treatment [21],

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ΔE C = 1.9 eV

2.1 eV 1.2 eV

2.5 eV

1.1 eV 0.2 eV

GaN 3.4 eV

AlN SiN x

HfO2

Al2O3

SiO 2

4H-SiC 3.2 eV 0.0 eV

ΔE V = 0.3 eV

0.8 eV 1.6 eV

1.6 eV 3.2 eV

Figure 9.5

Band lineup for GaN, AlN, 4H-SiC, and representative insulators [10−14].

in-situ MOCVD-grown thin AlN layers [22, 23] and atomic-layer-deposited AlN layers [24] have been investigated.

9.5

GaN HFETs

A GaN HFET is a GaN FET in which a layer of wider-bandgap material (i.e., AlGaN) is epitaxially grown over a 2DEG channel. It is also known as a GaN HEMT because of the high electron mobility of a 2DEG (see Section 9.3). The wider-bandgap material can be used as a part of multiple insulator layers (i.e., GaN MIS HFETs—see Section 9.5.1) or as a single insulator layer (i.e., GaN MESFETs and GaN p+-gate HFETs—see Sections 9.5.2 and 9.5.3). 9.5.1

GaN MIS HFETs

In GaN MISFETs, an insulator layer is formed on an AlGaN layer to suppress gate leakage current. A schematic cross-sectional view of the first vertical GaN MIS HFET on a freestanding GaN substrate is shown in Figure 9.6 [25]. Electron current flows through the AlGaN/GaN heterojunction and the aperture, spreads into the drift layer at about a 45-degree angle, and finally becomes uniform. During the off-state, the p+-GaN region plays the role of a current-blocking region. According to (3.25), sheet concentration of acceptors in the depleted p+-GaN region is equal to sheet concentration of donors in the depleted n-GaN drift layer. Even when the depleted n-GaN width equals the thickness of n-GaN drift layer (tdrift), the depleted p+-GaN width must be less than the thickness of the p+-GaN region (tp+) to prevent a phenomenon called punch-through. This condition was satisfied in [25] because sheet-acceptor concentration (3 × 1014 cm−2) in the p+-GaN region was much larger than sheet-donor concentration (3 × 1012 cm−2) in the

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9.5

GaN HFETs

Source n+-GaN GaN AlN p+-GaN

177

Gate Insulator AlGaN

Electron current flow

2DEG Source n+-GaN GaN AlN p+-GaN

n-GaN

n+-GaN substrate Drain

Figure 9.6 Schematic cross-sectional view of the first vertical GaN MIS HFET on a freestanding GaN substrate [25].

n-GaN drift layer as long as all the doped magnesium and silicon atoms became, respectively, acceptors and donors. Breakdown voltage BV (Figure 9.1) can then be determined as the voltage at which the maximum electric field at the p+/n GaN junction (Emax in Section 3.5) equals the critical electric field (Ecritical in Section 2.6). However, BV was not reported in [25]. The process flow for forming the aperture in Figure 9.6 is shown in Figure 9.7. A 3-μm-thick n-GaN layer, a 0.1-μm-thick p+-GaN layer, a 10-nm-thick AlN layer, and a 50-nm-thick GaN layer were grown on an n+-GaN (0001) substrate by MOCVD (see Section 6.2) (Figure 9.7[a]). The GaN/AlN/p+-GaN layer was dry-etched by ICP dry etching with Cl2 gas and an SiO2 mask (see Section 7.2.1) (Figure 9.7[b]). After the mask was removed, a 0.3-μm-thick n-GaN layer (Si: 1 × 1016 cm−3) and a 15-nm-thick Al0.25Ga0.75N layer were grown by MOCVD (Figure 9.7[c]). Here, the AlN layer was used to suppress mass transport from the surface to the aperture region [26]. Silicon-ion implantation was used to form n+-GaN source regions (see Section 7.3.1). As a gate insulator and an electrode, a 50-nm-thick hightemperature SiO2 layer and a 250-nm-thick phosphorous-doped polycrystalline silicon film were deposited by low-pressure chemical vapor deposition. Annealing to activate the polycrystalline silicon (at 850°C for 20 min) also activated hydrogenated magnesium [27]. It should be noted here that magnesium in the p+-GaN on which n-GaN is grown is not fully dehydrogenated by activation annealing [28]; therefore, ammonia-molecular beam epitaxy, instead of MOCVD, was recently used to fabricate GaN MIS HFETs without activation annealing [29]. In [25], the source and drain electrodes made of titanium (20 nm)/aluminum (1 μm) were formed by electron-beam evaporation. The GaN MIS

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SiO2 GaN AlN

p+-GaN n-GaN n +-GaN substrate (a) SiO2 GaN AlN

p+-GaN n-GaN n +-GaN substrate (b) AlGaN

n-GaN

GaN AlN

p+-GaN

GaN AlN

p+-GaN n-GaN n +-GaN substrate (c)

Figure 9.7

Process flow for fabricating the aperture shown in Figure 9.6 [25].

HFET had normally-on characteristics with Vth of −16V. At gate-source voltage VGS of 0V, RonA was 2.6 mΩcm2, which can be further reduced by decreasing the width of the JFET region, WJFET (Figure 9.8), as explained next. RonA is ideally determined by the specific resistance of the components in the current path shown in Figure 9.8: RonA = RSA+RchA+RaccumA+RJFETA+RdriftA+RsubA

(9.13)

where RSA is specific source resistance, RchA is specific channel resistance, RaccumA is specific accumulation-region resistance, RJFETA is specific JFETregion resistance, RdriftA is specific drift-region resistance, and RsubA is specific substrate resistance (see Section 1.3.1). In (9.13), RSA can be neglected because source regions are usually heavily doped. RchA is given as RchA = ρ2DEGGaN(0001) Lch (P/2),

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(9.14)

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9.5

GaN HFETs

179

L ch

WJFET

PP/2

Gate Insulator

Source R SA

AlGaN

Source

n +-GaN

R chA

R accmA

GaN AlN

Depletion region

R JFET A

Depletion region

t p++WDn

p+-GaN

45 o

t drift−tW drift Dn

Rdrift A

Rsub A drain

Figure 9.8 Specific resistances in the current flow path of the vertical GaN MIS HFET shown in Figure 9.6.

where Lch is channel length and P is cell pitch (Figure 9.8). RchA can be approximated as RaccumA = 0.6 ρ2DEGGaN(0001) WJFET (P/2)

(9.15)

where the factor 0.6 is typically used for vertical silicon power-switching devices to account for two-dimensional current spreading from the channel into the JFET region [30]. RJFETA, RdriftA, and RsubA are expressed as RJFETA = ρdrift (tp++WDn)(P/2)/(WJFET−WDn)

(9.16)

RdriftA = ρdrift{[(P/2)ln[(P/2)/(WJFET−WDn)] + tdrift−WDn−[(P/2)−WJFET]}

(9.17)

RsubA = ρsub tsub

(9.18)

where ρdrift is resistivity of the drift region, ρsub is resistivity of the substrate, tsub is thickness of the substrate, and depleted n-GaN width WDn is already given as (3.30); namely, WDn ≈ (2εrεoΨbi/qND)0.5

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(9.19)

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Vertical GaN and SiC Power Devices

Note that in (9.13), specific contact resistance is neglected due to its small value (i.e., 8 × 10−5 Ωcm2) [25]. Built-in potential Ψbi is given as [31] Ψbi = (kT/q) ln(NAND/ni2),

(9.20)

where niGaN is already given as (2.7a); namely, niGaN = 2.0×1015T1.5 exp(−2.0×104/T) (cm−3)

(9.21)

In the case P/2 = WJFET + 4 μm, RonA of the vertical GaN MIS HFET at 300K is calculated as a function of WJFET (Figure 9.9). In [25], Lch = 2 μm and WJFET = 1.5 μm. Other parameters used to calculate the curves in Figure 9.9 are listed as follows: ρ2DEGGaN(0001) = 580 Ω/sq (Section 9.3); μn = 850 cm2/Vs (Figure 2.16); εr = 10.4 [32]; ρsub = 0.018 Ωcm and tsub = 600 μm [33]. Calculated RonA reaches a minimum of 1.7 mΩcm2 at WFET = 3.5 μm. RaccumA increases with WJTEF when WJFET < 3.5 μm, while contributions of RdriftA and RJFETA become large when WJFET > 3.5 μm. Since the contribution of RsubA (i.e., 1.1 mΩcm2) is dominant, in the present case of a 3-μmthick 1 × 1016-cm−3 doped n-GaN drift layer, thinning GaN substrates is effective for reducing RonA. Note that in contrast to the above-described epitaxially grown p+-type GaN buried regions [25], magnesium-ion-implanted p+-type GaN buried regions have also been used [34]. Activation annealing was carried out at 1,553K in NH3+N2 ambient, and the resultant BV and RonA were 250V and 2.2 mΩcm2, respectively.

Specific resistance (mΩcm2)

3.0 2.5

Kanechikaet al. [25]

RonA

2.0 1.7 1.5

RsubA

1.0 0.5

0

2

3.5 4

6 JFET width WFET (μm)

8

RaccumA Rdrift A RchA RJFETA 10

Figure 9.9 Specific resistance of a vertical GaN MIS HFET (Figure 9.6) as a function of JFET width calculated from (9.13) to (9.21) in the case P/2 = WJFET + 4 μm.

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GaN HFETs

9.5.2

181

GaN MESFETs

In GaN MESFETs, no insulator layers are formed on an AlGaN layer. As shown in Figure 9.10, the direction of spontaneous polarization is parallel to a GaN (1120 ) surface. Since only piezoelectric polarization induces charges at the AlGaN/GaN interface formed on GaN (1120), ns becomes smaller than that at the AlGaN/GaN interface formed on GaN (0001). If the AlGaN/GaN interface is formed on a face between (0001) and (1120 ), ns takes a value between ns(0001) and ns(1120 ). A 0.2-μm-thick n+GaN layer (Si: 3 × 1018 cm−3), a 1-μm-thick p+-GaN layer (Mg: 5 × 1018 cm−3), and a 5-μm-thick n-GaN layer (Si: 7 × 1015 cm−3) layer were grown on an n+-GaN (0001) substrate by MOCVD [3]. V-grooves in the n+-GaN/ p+-GaN/n-GaN layers (with a slope angle of 16°) were formed by ICP dry etching, and Al0.25Ga0.75N/75-nm-thick GaN layers were regrown (Figure 9.11). By thinning the Al0.25Ga0.75N layer from 35 to 10 nm, Vth shifted from −3.2 to +0.3V. As for the normally-on devices, BV of 672V and RonA of 7.6 mΩcm2 were reported; however, neither BV nor RonA were reported for normally-off devices. 9.5.3

GaN p+-gate HFETs

In GaN p+-gate HFETs, a p+-type GaN layer is formed on an AlGaN layer. With an appropriately designed p+-type GaN layer, the potential of the heterojunction is lifted up only below the gate, which leads to positive Vth (solid line in Figure 9.12). A 15-μm-thick n-type GaN drift layer doped at 1 × 1016 cm−3 was grown on an n+-type GaN substrate (Figure 9.13[a]) and the resultant BV and RonA were, respectively, 1.5 kV and 2.2 mΩcm2; however, Vth was relatively low (namely, 0.5V) [35]. As a function of surface tilt angle from (0001), ns of p+-GaN/AlGaN/ GaN was calculated [36] (Figure 9.14). Reduction of ns increased Vth to 2.5V Spontaneous polarization

[1120]

[0001] [1100]

Figure 9.10 Schematic cross-section of GaN ( 1120 ) showing direction of spontaneous polarization (solid circles: gallium atoms; open circles: nitrogen atoms).

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Vertical GaN and SiC Power Devices

Gate AlGaN GaN/n+-GaN Source

2DEG Source

p +-GaN

n -GaN

n +-GaN substrate Drain Figure 9.11 Schematic cross-sectional view of a vertical GaN MESFET on a freestanding GaN substrate [3].

(0001) surface EC (0001) surface E SD p+-GaN

EF AlGaN

GaN

Figure 9.12 Distributions of conduction-band edge of p+-GaN/AlGaN/GaN (solid line) and AlGaN/GaN (dashed line) heterostructures formed on GaN (0001) at a gate-source bias of 0 V.

when p+-GaN/AlGaN/GaN layers were regrown over V-shaped grooves formed over an n-type GaN drift layer. On the basis of this finding, p+GaN/AlGaN/GaN layers were regrown over the V-grooves at the surface of p+-GaN (Mg: 3 × 1019 cm−3) and 13-μm-thick n-GaN (Si: 1 × 1016 cm−3) drift layers by MOCVD (Figure 9.13[b]). An insulating GaN layer doped with carbon at 5 × 1018 cm−3 was also inserted to block off-state leakage current. After selective etchings of p+-GaN to form the gate and of AlGaN/ GaN/carbon-doped GaN to form the source electrode by ICP dry etching, titanium/aluminum source and palladium/gold gate electrodes were formed on the front side, and a titanium/aluminum/titanium/gold drain electrode was formed on the backside. The resultant BV and RonA were, respectively, 1.7 kV and 1.0 mΩcm2. Stable gate characteristics and successful 400-V/15A fast switching were also demonstrated.

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4H-SiC JFETs

183

Gate

p+-GaN AlGaN

Source

n +-GaN

Source

n +-GaN

2DEG

p+-GaN

p+-GaN n-GaN

n +-GaN substrate Drain

(a)

Gate

Source

p+-GaN AlGaN GaN C-dopedGaN

2DEG AlGaN

Source

p+-GaN n-GaN

n +-GaN substrate Drain

(b)

Figure 9.13 Schematic cross-sectional views of (a) planar [35] and (b) V-grooved [36] GaN p+-gate HFETs on freestanding GaN substrates.

9.6

4H-SiC JFETs

A JFET is a buried-channel FET and is thus free from surface effects. However, the large distance between the gate and the channel makes achieving normally-off characteristics challenging (see Section 9.1). Normally-off 4HSiC JFETs based on a trenched-and-implanted vertical channel structure (Figure 9.15[a]) were demonstrated with RonA of 3.6 mΩcm2 and BV of 1.7 kV [37] and RonA of 130 mΩcm2 and BV of 11 kV [38]. However, narrow channel widths (less than 1.7 μm [37] and 0.55 μm [38]) pose stringent requirements on lithography. By inserting p+ screen grids between the gate and the drain, RonA of 2.4 mΩcm2 and BV of 1.4 kV were achieved, but Vth was as low as +1.0V [39]. A 4H-SiC JFET with buried p+ grids as the controlling gate (Figure 9.15[b]) was also demonstrated with RonA of 1.0 mΩcm2 [40]. However, BV of 700V was measured at VGS = −12V, which is the normally-on feature.

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Vertical GaN and SiC Power Devices

Sheet electron concentration (×10 12 cm−2)

184

10 8 6 4

2

0

30

60

90

Surface tilt-angle from (0001) (deg) Figure 9.14 Calculated sheet electron concentration of a p+-GaN/AlGaN/GaN channel as a function of surface tilt-angle from (0001) [36].

Source

n+

Channel Gate

Gate

n - drift layer n + substrate Drain

(a) Gate

p+ top gate Source

Source

n+

Channel

p+ buried gate

n+ p+ buried gate

n - drift layer n + substrate Drain

(b)

Figure 9.15 Schematic cross-sectional views of 4H-SiC JFETs with (a) trenched-andimplanted channels and (b) p+ buried gates.

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MISFETs

185

When a high-voltage normally-on 4H-SiC JFET was cascoded with a low-voltage normally-off silicon MOSFETs, the JFET-MOSFET pair operate as a normally-off power-switching device from an external perspective (Figure 9.16) [41]. A 3.3-kV normally-on 4H-SiC JFET was recently cascoded with a 80-V normally-off silicon MOSFET, and a blocking voltage higher than 4.0 kV and a low RonA of 14.7 mΩcm2 were realized [42].

9.7

MISFETs

A MISFET is an FET that includes a MIS capacitor, a drift layer, and source and drain regions. The gate structure in the MIS capacitor is divided into planar and trench types, while the drift-layer structure is divided into conventional n- and SJ types. Figure 9.17(a–c) shows schematic cross-sectional views of planar, trench, and SJ MISFETs. Planar Si MOSFETs were the first unipolar power-switching devices to be commercially successful. To reduce fabrication cost, channels in these devices were formed by the so-called double-diffusion process; namely, the difference between lateral diffusivities of p- and n-type dopants defines the channels. In the cases of GaN and

Drain

Normally-on 4H-SiC JFET

Gate

Normally-off silicon MOSFET

Source

Figure 9.16 A high-voltage normally-on 4H-SiC JFET cascoded with a low-voltage normally-off silicon MOSFET.

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Vertical GaN and SiC Power Devices

Gate

Source

Insulator

n+ p-base

Gate

Source

n+

Source

Insulator

n+

n+ p-base

p-base n-drift region

n + substrate Drain

(a) Source

Source

Source

n+

Gate

p-base

n+

n+

gate Gate

p-base

Insulator

n+ p-base

Insulator

n-drift region

n + substrate Drain

(b) P Source

Gate

Insulator

n+ p-base p

Source

n+ n+ p-base

≈tdrift Wn

p (N A) Wp

Gate

Source

Insulator

n+ p-base n-drift region (N D)

p

n + substrate

Drain

(c)

Figure 9.17 Schematic cross-sectional views of (a) planar, (b) trench, and (c) SJ MISFETs.

4H-SiC MISFETs, on the other hand, the double-diffusion process cannot be used due to lack of dopant diffusion (e.g., silicon and magnesium in GaN and aluminum in 4H-SiC) and complicated dopant diffusion (e.g., boron in 4H-SiC) (see Section 7.4). GaN and 4H-SiC planar MISFETs have therefore been fabricated by epitaxial growth and/or ion implantation. Trench MISFETs (also called UMISFETs due to the U-shaped cross section of the gate insulator) (Figure 9.17[b]) can increase channel density because the MIS channel is oriented perpendicular to the surface. Moreover, trench MISFETs can eliminate RJFETA compared to planar MISFETs, resulting in extremely low RonA [43].

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MISFETs

187

The concept of SJ devices [44], in which alternating p- and n-type columns are located in a drift layer, was first applied to a varactor diode [45], and then to commercial production of silicon SJ MOSFETs [46]. Although Figure 9.17(c) shows a planar SJ MISFET, a trench SJ MISFET can also be fabricated. 9.7.1

Planar MISFETs

To the author’s knowledge, no planar GaN MISFETs have been reported. In the case of SiC, a planar 6H-SiC MISFET was fabricated in 1997 [47] using the double-implantation process, in which multiple-energy boron ions are implanted to form 1-μm-deep p-base regions (Figure 9.17[a]). The insulator used in the MIS structure was a thermally grown oxide, and inversion-layer channel mobility μinv was 20 cm2/Vs. The reported BV and RonA were 760V and 130 mΩcm2, respectively. In 2001, a planar 4H-SiC MISFET was fabricated using a deposited oxide [48]. The reported μinv, BV, and RonA were 14 cm2/Vs, 2 kV, and 55 mΩcm2, respectively. With respect to BV and RonA, improved values, such as 2.4 kV and 42 mΩcm2 [49] and 10 kV and 236 mΩcm2 [50], had been reported by 2004. In 2015, an amelioration of RchA of a planar 4H-SiC MISFET was demonstrated, in which trenches were formed in the channel region to increase the channel density per area [51]. On the other hand, μinv has been increasing over time (up to, for example, 130 cm2/Vs [52]) by improving MIS interface quality by using nitrogen [53] (see Section 7.5.2) or phosphorus [54, 55] doping during post-oxidation; strontium- [56], barium- [57], antimony- [58], or lanthanum- [52] passivation of interface-charge traps, and diffusing boron-passivation of dangling bonds in dry oxide [59, 60]. μinv-limiting factors include Coulomb scattering, surface scattering, and phonon scattering [61]; in the case of a SiO2/4H-SiC interface, Noguchi et al. experimentally observed phononlimited μinv and concluded that surface roughness is not the dominant μinv-limiting factor at high voltages [62]. When VGS exceeds Vth, the surfaces of p-base and JFET regions correspond, respectively, to the inversion and accumulation cases (Section 9.2.1). Electron current flows through the inversion-layer channel (created on the surface of the p-base regions) into the accumulation layer (formed on the surface of the JFET region), spreads into the drift layer at about a 45-degree angle, and finally becomes uniform (Figure 9.18[a]). To reduce RJFETA, heavily-doped n-type JFET regions and a current-spreading layer (CSL) (Figure 9.18[b]) have been used [63]. When such a structure is used, RonA of a planar 4H-SiC MISFET is ideally determined by the specific resistance of the components in the current path (shown in Figure 9.18[b]) as

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Vertical GaN and SiC Power Devices

Gate Source

Source

insulator inversion layer

accumulation layer

n+

n+

p-base

p-base

Depletion region

Depletion region

45 o

n-drift region

n + substrate Drain (a) L ch

L access

WJFET

P /2 Gate

Source inversion layer

R SA tCSL

R ch A

accumulation layer

n+

R accmA

p-base depletion region

Source

insulator

p-base R JFET A

depletion region

n + current-spreading layer (CSL)

tdrift

n-drift region

R driftA

n + substrate

R subA Drain (b)

Figure 9.18 (a) Current-flow path of a planar 4H-SiC MISFET without a CSL and (b) specific resistances in the current flow path of a planar 4H-SiC MISFET with a CSL.

RonA = RSA+RchA+RaccumA+RJFETA+RdriftA+RsubA

(9.22)

In (9.22), RSA can be neglected because source regions are usually heavily doped. RchA is given as RchA = Lch (P/2)/[μinvCI(VGS−Vth)]

(9.23)

where CI is specific capacitance of the gate insulator, which is expressed as the ratio of the permittivity to thickness of the gate insulator; namely, CI = εI/tI

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(9.24)

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MISFETs

189

RaccumA is given as

RaccumA = 0.6(WJFET−WDn)(P/2)/[μaccumCI(VGS−Vth)]

(9.25)

where μaccum is electron mobility in the accumulation layer. Here, the factor of 0.6, which already appeared in (9.15), is typically used for vertical silicon power-switching devices to account for two-dimensional current spreading from the channel into the JFET region [30]. And WDn is obtained using (2.7b), ni4H-SiC = 3.9 × 1015T1.5 exp(−1.9×104/T) (cm−3)

(9.26)

and (9.19) and (9.20). RJFETA and RdriftA can be approximated, respectively, as RJFETA = ρCSL tCSL(P/2)/(WJFET−WDn)

(9.27)

RdriftA = ρdrift tdrift

(9.28)

and

where ρCSL and tCSL are resistivity and thickness of the CSL. RsubA is given by (9.18). In the case of the double-self-aligned short-channel 4H-SiC planar 1-kV-class MISFET reported in [64], Lch = 0.5 μm; P/2 = 4 μm; tI = 50 nm; WJFET = 0.5 μm; NCSL = 1.0 × 1017 cm−3; tCSL = 0.9 μm; Ndrift = 8.55 × 1015 cm−3; and tdrift = 8.4 μm, and VGS−Vth = 20V. With the assumption of μaccum = μinv, μCSL = 600 cm2/Vs, μdrift = 850 cm2/Vs (Figure 2.16), ρdrift = 0.02 Ωcm [65], and tdrift = 350 μm [65], RonA at 300K is calculated as a function of μinv (Figure 9.19). RJFETA is negligibly small due to the use of a CSL. Although μinv was not described in [64], the result in Figure 9.19 indicates that in the case of 4H-SiC planar 1-kV-class MISFETs, the measured RonA of 6.7 mΩcm2 [64] should decrease with increasing μch. With respect to higher-voltage 4H-SiC planar MISFETs, typical thickness/donor concentration in drift layers for BV of 1.7, 3.3, and 4.5 kV are, respectively, 15 μm/2 × 1015 cm−3, 34 μm/1.5 × 1015 cm−3, and 40 μm/1 × 1015 cm−3 [66]. Under the assumption of μdrift of 850 cm2/Vs (Figure 2.16) for the three doping levels, RonA’s at 300K are calculated as a function of μinv (Figure 9.20). Since RdriftA dominates RonA in such high-voltage MISFETs, decreasing μinv is not so important in terms of reducing RonA.

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Vertical GaN and SiC Power Devices

10

Rdrift A

Specific resistance (mΩcm2)

Ron A

RsubA Rsub(mu1cm2) A

8 Wang and Cooper [64] 6

Rch A 4

Raccum A

2

RJFET A

0 1

10

100

Inversion-layer channel mobility (cm2/Vs) Figure 9.19 Specific resistance of a 4H-SiC planar 1-kV-class MISFET with a CSL (Figure 9.16[b]) as a function of inversion-layer channel mobility calculated from (9.18) to (9.20) and (9.22) to (9.28).

35 R on A of 4.5-kV-class 4H-SiC planar MISFET

Specific resitance (mΩcm2)

30 25 20

R on A of 3.3-kV-class 4H-SiC planar MISFET

15 10 5

R on A of 1.7-kV-class 4H-SiC planar MISFET R ch A

0 1

10 Inversion layer channel mobility (cm2/ Vs)

100

Figure 9.20 Specific resistance of 4H-SiC planar 1.7−4.5-kV-class MISFETs with a CSL (Figure 9.18[b]) as a function of inversion-layer channel mobility calculated from (9.18) to (9.20) and (9.22) to (9.28).

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MISFETs

191

9.7.2 Trench MISFETs The basic structure of a trench MISFET is shown in Figure 9.17(b). Since the first Si trench MOSFET was reported in 1985 [43], it took 11 and 23 years, respectively, for the first 4H-SiC [67] and GaN [68] trench MISFETs to be reported. 9.7.2.1

GaN Trench MISFETs

Reported values of BV and RonA of GaN trench MISFETs on freestanding GaN substrates are listed in Figure 9.21 [68−76]. With respect to gate layout, the use of a regular hexagonal-trench gate with a cell pitch of 12.6 μm (Figure 9.22) resulted in a ratio of gate width to unit cell area (WG/Scell) of 0.267 μm−1 [71], which was twice as large as WG/Scell of a stripe layout with a cell pitch of 15 μm [70]. The hexagonal layout with a cell pitch of 18 μm for a 1.5 × 1.5-mm2 chip (active area: 1.8 mm2) resulted in large current (23.2A) and fast switching characteristics [72]. However, μinv in an inverted p-GaN channel of conventional trench MISFETs is low. To increase electron mobility in channels, in situ oxide, GaN interlayer-based vertical trench MOSFET (OG-FET) [73, 74] and GaN vertical fin power FET [75, 76] have been reported. While the former was fabricated using regrowth of a GaN interlayer followed by MOCVD dielectric deposition on a trenched structure, the latter uses only n-type GaN layers with submicron fin-shaped channels. 9.7.2.2

4H-SiC Trench MISFETs

Although BV of 4H-SiC MISFETs was increased to 1.1 kV in 1997 [77] and 1.4 kV in 1998 [78] from that of the first 4H-SiC trench MISFET (i.e., 0.26

Authors and ref.

Otake et al. [68]

Kodama et al. [69]

Oka et al. [70]

Oka et al. [71]

Oka et al. [72]

Year

2008

2008

2014

2015

2016

Breakdown voltage (kV)

−

0.18

1.6

1.25

1.6

Specific on-resistance (mΩcm2)

9.3

−

12.1

1.8

2.7

Authors and ref.

Gupta et al. [73]

Gupta et al. [74]

Sun et al. [75]

Zhang et al. [76]

Year

2017

2017

2017

2017

Breakdown voltage (kV)

0.99

1.4

0.8

1.2

Specific on-resistance (mΩcm2)

2.6

2.2

0.36

0.2

Figure 9.21 Reported values of BV and RonA of GaN trench MISFETs on freestanding substrates [68–76].

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Vertical GaN and SiC Power Devices

Gate

Source

10 μm

Figure 9.22 Schematic plan view of a regular hexagonal-trench gate layout [71, 72].

kV [67]), a very strong electric field developed across the gate insulator limited BV of 4H-SiC trench MISFETs. Even in the case of silicon-trench MOSFETs, a strong electric field is developed in the gate oxide at the bottom corner of the silicon trench [79]; however, the electric field in the underlying semiconductor (ES) is weak, 0.3 MV/cm [80]. On the other hand, Es becomes high, namely, 3.75 MV/cm [81] for GaN and 2.50 MV/cm for 4H-SiC [82] (see Section 2.6). According to Gauss’s law, the electric field in a gate insulator (EI) is related to ES as follows: EI = (εr/εI)ES

(9.29)

where εr and εI are respectively relative permittivities of the semiconductor and the insulator. Since εr parallel to the c-axis is 10.4 for GaN [83] and 10.0 for 6H-SiC [84] (see Section 2.7) and εI is 7.5 for Si3N4 and 3.9 for SiO2 [85], EI becomes large, namely, 5.2 MV/cm in the case of Si3N4 on GaN [68], and 6.4 MV/cm in the case of SiO2 on 4H-SiC [67]. These EI values are close to dielectric strength (≈ 10 MV/cm for both Si3N4 and SiO2 [85]), resulting in destruction of gate insulator at the trench bottom during application of high VDS [67]. Shielding such high EI is thus indispensable; however, to the author’s knowledge, no GaN shielded-trench MISFETs have been reported. In contrast, in 2002, p+ shielding regions, which are short-circuited to the source terminal, were first incorporated at the bottom of the trench of 4H-SiC trench MISFETs (Figure 9.23[a]) [86]. BV of such 4H-SiC shielded trench MISFETs increased to 3 kV for a 50-μm-thick drift layer doped at

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MISFETs

193

Source

Source

n+

Gate

p-base

Insulator

Source

n+

n+

p-base

p+ shielding region

n+

gate Gate

p-base

Insulator

n-drift region n + substrate Drain

(a) Source

Source

n+

Gate Insulator

Source

n+

n+

p-

base

p+ shielding region

n+

Gate gate Insulator

n-drift region n + substrate Drain

(b)

Source

Source

n+

Gate

n+

Source

n+

n+

Gate

p-base

p-base

Insulator

Insulator

p+ shielding region

p-base

n-drift region

p+ shielding region

n + substrate Drain

(c) Figure 9.23 Schematic cross-sectional views of p+ shielded (a) single-trench [79], (b) double-trench [88], and (c) V-groove trench MISFETs [90].

8.5 × 1014 cm−3 [86] and 5 kV for a 115-μm-thick drift layer doped at 7.5 × 1014 cm−3 [87]. However, reported RonA values of these 4H-SiC trench MISFETs were relatively large: 18 [67], 180 [77], 311 [78], 120 [86], and 228 mΩcm2 [87]. In 2011, 4H-SiC MISFETs with source and gate trenches (so-called double trenches [Figure 9.23(b)]) were reported with very low RonA: 0.79

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mΩcm2 for BV = 630V (Ndrift = 1.8 × 1016 cm−3; tdrift = 5 μm) and 1.41 mΩcm2 for BV = 1260V (Ndrift = 7.5 × 1015 cm−3; tdrift = 8 μm) [88]. As described in Section 8.8, such a double-trench structure is also effective for reducing the electric field in trench SBDs. It has to be noted that tsub was thinned down to 100 μm in [88]. Measured μinv on the trench sidewalls of the double-trench MISFETs was relatively small (i.e., 11 cm2/Vs) [88]. According to Harada et al. [89], the deep p+ regions create a JFET under the trench with a potential barrier that reduces the electric field at the bottom of the trenches, and EI can be reduced to less than 3 MV/cm if the deep p+ regions are formed 1.2 μm deeper than the bottom of the gate trench. 9.7.2.3

4H-SiC V-groove Trench MISFETs

A V-groove MISFET that utilizes the 4H-SiC ( 0338 ) face for the channel region is shown in Figure 9.23(c) [90]. Its fabrication process starts by growing a 12-μm-thick n-type drift layer doped at 4.5 × 1015 cm−3. The p+ shielding regions are then formed by aluminum-ion implantation, followed by growth of a 3-μm-thick n-type drift layer doped at 7 × 1015 cm−3. To form a 0.6-μm-long channel on the trench sidewalls, p-base and n+ source regions are implanted, respectively, with aluminum and phosphorus. BV and RonA were, respectively, 1,700V and 3.6 mΩcm2, in contrast to 575V and 3.1 mΩcm2 for a V-groove MISFET fabricated without the p+ shielding regions. It was reported that μinv along the trench sidewalls was 80 cm2/Vs [91] and that a design in which the p+ regions occupy 30% of the active area balances BV and RonA [92]. 9.7.3

SJ MISFETs

According to Gauss’s Law, BV for a given SJ drift layer (Figure 9.17[c]) reaches a maximum when the sheet charge in each n-or p-type column Qs is given as Qs = qNDWn = qNAWp = εrεoEcritical

(9.30)

where Wn and Wp are, respectively, widths of n- and p-type columns. RdriftA is expressed as RdriftA = ρdrift tdrift(P/Wn)

(9.31)

where trench depth is approximated by tdrift. From (2.16), ρdrift = 1/(qNDμn)

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(9.32)

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MISFETs

195

putting (9.30) and (9.32) into (9.31) leads to the following expression: RdriftA = tdriftP/(μnQs)

(9.33)

If the electric field along the trench is assumed to be uniform, tdrift = BV/Ecritical_SJ

(9.34)

where Ecritical_SJ is critical electric field of an SJ drift layer. From (9.30), (9.33), and (9.34), it follows that RdriftA = BV P/(εrεoμnEcritical_SJ2)

(9.35)

As derived in (2.22), RdriftA of a conventional n-type drift layer is given as RdriftA = 4BV2/(εrεoμnEcritical_conv3)

(9.36)

where Ecritical_conv is the critical electric field of a conventional n-type drift layer. Comparing (9.35) with (9.36) clarifies the following advantages of an SJ drift layer:  RdriftA increases linearly with BV, which is opposed to the quadratic increase for a conventional n-type drift layer.  RdriftA decreases linearly with P because, according to (9.30), ND and NA must be increased with decreasing P. Larger ND reduces ρdrift (9.32) and hence RdriftA. Note, however, that Ecritical_SJ becomes smaller than Ecritical_conv because a high electric field extends over a larger distance, thereby producing enhanced impact ionization [93]. To the author’s knowledge, no GaN SJ MISFETs have been reported. The only 4H-SiC SJ MISFET reported to date is a V-groove MISFET with a drift layer formed by ion implantation [94]. The epitaxially grown n-type drift layer was 6.0-μm-thick and doped at 3 × 1015 cm−3, and p-type columns with 3-μm-deep 3 × 1016-cm−3 box profiles were formed with highenergy (up to 9 MeV) aluminum ion implantation. A 2-μm-thick epitaxial layer was then grown on the SJ structure, and the V-groove MISFET structure (Figure 9.23[c]) was fabricated. The resultant Vth of 3.4V was the same level as that of a conventional 4H-SiC V-groove MISFET. BV and RonA were, respectively, 820V and 0.97 mΩcm2.

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The impact of the SJ structure should appear more clearly in regard to higher-BV MISFETs. Moreover, fabrication of such SJ MISFETs will require trench-filling epitaxy (as described in Section 6.6).

9.8

Summary

This chapter starts by reviewing the physics of MIS capacitors and AlGaN/ GaN heterostructures to provide an understanding of MISFET and HFET operations. Detailed analysis of RonA is carried out by taking a reported GaN MIS HFET and a 4H-SiC planar MISFET as examples. The chapter also introduces reported device performances of GaN MESFETs, GaN p+-gate HFETs, GaN trench MISFETs, 4H-SiC trench MISFETs, and 4H-SiC V-groove MISFETs. Finally, with respect to SJ MISFETs, the chapter describes the concept of charge balance and introduces the very recently reported device performance of 4H-SiC V-groove SJ MISFETs.

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[89] Harada, S., et al., “Determination of Optimum Structure of 4H-SiC Trench MOSFET,” International Symposium on Power Semiconductor Devices and ICs, Bruges, June 3–7, 2012, pp. 253–256. [90] Wada, K., et al., “Fast Switching 4H-SiC V-Groove Trench MOSFETs with Buried p+ Structure,” International Symposium on Power Semiconductor Devices and ICs, Waikoloa, June 15–19, 2014, pp. 225–228. [91] Mikamura, Y., et al., “Novel Designed SiC Devices for High Power and High Efficiency Systems,” IEEE Transactions on Electron Devices, Vol. 62, No. 2, 2015, pp. 382–389. [92] Uchida, K., et al., “The Optimized Design and Characterization of 1,200 V/2.0 mΩcm2 4H-SiC V-Groove Trench MOSFETs,” International Symposium on Power Semiconductor Devices and ICs, Kowloon, May 10–14, 2015, pp. 85–88. [93] Baliga, B. J., Silicon Carbide Power Devices, Singapore: World Scientific, 2005, p. 369. [94] Masuda, T., R. Kosugi, and T. Hiyoshi, “0.97 mΩcm2/820 V 4H-SiC Super Junction V-Groove Trench MOSFET,” Materials Science Forum, Vol. 897, 2016, pp. 483–488.

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CHAPTER

10 Contents 10.1 Introduction 10.2 Optimum Design of a One-Dimensional p-n Diode 10.3 GaN p-n Diodes with a Nonuniformly Doped Drift Layer 10.4 4H-SiC p-i-n Diodes 10.5 n-p-n BJTs 10.6 Shockley Diodes 10.7 SiC Thyristors 10.8 SiC IGBTs 10.9 Summary

Bipolar Power Diodes and Power-Switching Devices 10.1

Introduction

As stated in Section 8.1, a forward voltagedrop VF (at forward current IF [Figure 1.8]) of a unipolar power diode becomes less than VF of a bipolar power diode as long as the voltage drop across the drift layer is negligible. In other words, VF of a bipolar power diode becomes smaller than VF of a unipolar power diode when the voltage rating is high. With regards to power dissipation of 4H-SiC power diodes, it was theoretically derived that a bipolar power diode is preferred when reverse voltage exceeds 2 kV and operating frequency is below 30 kHz [1]. With respect to GaN bipolar power diodes, on the other hand, that voltage and frequency should decrease on the basis of the measured stored charge of a 1.6-kV GaN bipolar power diode being only 5.6% of that of a Si bipolar power diode [2]. This stored-charge difference

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is due to the shorter carrier lifetime of GaN; however, effective carrier lifetime (under high-level injection) of GaN is increased by photon recycling (see Chapter 4), which led to a demonstration of a GaN bipolar power diode with very high breakdown voltage BV (i.e., 5.0 kV) [3]. Bipolar power diodes include p-n diodes (Figure 10.1[a]) and p-i-n diodes (Figure 10.1[b]). In addition, p-n-p-n diodes, called Shockley diodes, (Figure 10.1[c]) have been developed, although they are functionally two-terminal power-switching devices. All these diodes adopt a non-self-aligned mesa-type configuration, as explained in Section 3.7. With respect to power-switching devices, GaN bipolar ones have not been reported. Although GaN/InGaN heterojunction bipolar transistors

Anode

p+-anode Termination

Termination

n-drift region

n + substrate Cathode

(a) Anode

p+-anode Termination

Termination

i-drift region

n + substrate Cathode

(b) Anode

p+-anode n-base Termination

Termination

p-drift region

n + substrate Cathode

(c)

Figure 10.1 Schematic cross-sectional views of bipolar power diodes: (a) p-n diode, (b) p-i-n diode, and (c) Shockley diode (i.e., p-n-p-n diode). Although “i” stands for intrinsic, a lightly-doped n-type layer is usually used for an i-drift layer in the case of a wide-bandgap semiconductor p-i-n diode.

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10.1

Introduction

205

were fabricated on freestanding GaN substrates [4], the transistors were designed for rf small-signal amplification. However, on the basis of a bipolar junction transistor (BJT) being the first bipolar power-switching device based on silicon, this chapter briefly introduces the possible performance of a n-p-n GaN BJT as a candidate for the first GaN bipolar power-switching device. As essential components of 4H-SiC power-switching devices, BJTs (Figure 10.2[a]), thyristors (Figure 10.2[b]), and insulated-gate bipolar transistors (IGBTs) (Figure 10.2[c]) have been fabricated. 4H-SiC n-p-n BJTs with breakdown voltage up to 1.7 kV are commercially available, and their characteristics have been modeled and simulated [5]. Thyristors are

Emitter Base p+

n +-emitter p-base

Base p+

Termination

Termination

n-drift region

n + substrate Collector

(a) Anode Gate n+

p+-anode n-base

Gate n+

Termination

Termination

p-drift region

n + substrate Cathode

(b) Emitter

n+ p-base

Gate

insulator

Gate

Emitter

n+

insulator

n+

p-base

Emitter

n+ p-base

n-drift region

p+ substrate Collector

(c) Figure 10.2 Schematic cross-sectional views of bipolar power-switching devices: (a) BJT, (b) thyristor, and (c) IGBT.

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Vertical GaN and SiC Power Devices

formed by incorporating gate electrodes in Shockley diodes (Figure 10.1[c]) so that they can be switched on for valuable lengths of time during on-state. A conventional thyristor is usually turned off by lowering the anode current below a holding current, Ih. However, gate-turn-off thyristors (GTOs) and emitter-turn-off thyristors (ETOs) can be turned off, respectively, with negative gate and emitter currents; for example, up to 22-kV 4H-SiC GTOs [6] and 22-kV 4H-SiC ETOs [7] have been demonstrated. In BJTs and thyristors, control electrodes (i.e., base electrodes in the case of BJTs and gate electrodes in the case of thyristors) make ohmic contacts with semiconductor regions. In contrast, an insulated-gate structure is used in IGBTs. The name IGBT is derived from its operation based on the insulated-gate fieldeffect transistor and the bipolar transistor. The structure of an n-channel IGBT (Figure 10.2[c]) is similar to that of an n-channel MISFET (Figure 9.17[a]), except that an n+ substrate in the MISFET is replaced with a p+ substrate in the IGBT. Although the backside electrode of IGBTs is conventionally called a collector electrode, it functions as an emitter electrode of a p-n-p BJT (Figure 10.3). Up to 27-kV 4H-SiC n-channel IGBTs have been reported [8]. This chapter covers only planar types of the above-described bipolar power diodes and power-switching devices. Note, however, that similar to the MISFETs described in Section 9.6, trench and V-groove structures have also been applied to IGBTs [9–11].

10.2

Optimum Design of a One-Dimensional p-n Diode

Section 3.5 considers depletion-region width, WDn, of a reverse-biased onedimensional p+n diode when drift-layer thickness Wn is equal to or larger than WDn, which is given by (3.31), by replacing Ψbi−V with VR

n -channel MISFET

Source and collector contact Gate Insulator

Gate Insulator Source

Collector of BJT Drain of MISFET and base of BJT p-n -p BJT p+ substrate Emitter of BJT

Figure 10.3 Schematic cross-section of an n-channel IGBT viewed as a combination of an n-channel MISFET and a p-n-p BJT.

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10.2

Optimum Design of a One-Dimensional p-n Diode

207

WDn ≈ (2εrεoVR/qND)0.5

(10.1)

where εr is relative permittivity parallel to the c-axis, εo is permittivity in a vacuum, VR is reverse bias, and ND is net donor density in a uniformly doped drift layer. When Wn = WDn at a rated voltage (Figure 10.4) and WDn >> WDp, BV is given as BV ≈ EmaxWn/2

(10.2)

Putting εr of 10.4 for GaN [12] and 10.0 for 4H-SiC [13] (see Section 2.7) and the highest critical electric field (Ecritical) ever reported (i.e., 3.75 MV/cm [14] for GaN and 2.50 MV/cm for 4H-SiC [15]) (see Section 2.6), respectively, into (10.1) and (10.2) leads to an optimum design of a onedimensional p-n diode with a uniformly doped drift layer (as shown in Figure 10.5).

n −region

p+ region neutral region

depletion region

n + region neutral region

q ND +++++++ ++++ −WDp − O Wn = WDn − − − − − − − − − − −q NA

x

(a) E −WDp

Wn = WDn O

x

−E max (b)

Figure 10.4 Reverse-biased abrupt p+/n−/n+ junction in which depletion-region width is equal to drift-layer thickness: (a) space-charge distribution under depletion approximation and (b) electric-field distribution.

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10 18

10 3

One-dimensional GaN (0001) p+n diode

10 2

10 17 16

1.5 × 10

15

10 16

10 1

10 15

10 0

10 14 0.1

1

3

Drift-layer thickness (μm)

Vertical GaN and SiC Power Devices

Net donor density (cm −3 )

208

10 −1 10

100

10 18

One-dimensional 4H-SiC (0001) p+n diode

10 3 640

10 17

10 2

10 16

10 1

10 15

10 0

2.0 × 1014

1014 0.1

1

10

80 100

10 −1

Drift-layer thickness (μm)

Net donor density (cm −3 )

Breakdown voltage (kV) (a)

Breakdown voltage (kV) (b)

Figure 10.5 Optimum design of (a) GaN (0001) and (b) 4H-SiC (0001) abrupt p+/n−/n+ junction in which depletion-region width is equal to drift-layer thickness.

As source gasses for MOCVD of n-type GaN, TMG, ammonia (NH3), and silane (SiH4) are most frequently used (see Section 6.2). Residual carbon background is known to be minimized by performing MOCVD under a large partial pressure of NH3. For instance, it was found that a NH3/ TMG flow-rate ratio exceeding 1,000 decreases concentration of unintended carbon acceptors (i.e., about 5 × 1016 cm−3) in epitaxially grown GaN (0001) to 1 − 2 × 1016 cm−3 [16] (open symbols in Figure 10.6). If minimum controllable ND is assumed to be 1.5 × 1016 cm−3, the highest BV is predicted from Figure 10.5(a) to be about 3 kV when Wn is 15 μm. These values are close to the experimentally measured ones: BV = 3.7 kV in the case of ND = 6 × 1015 cm−3 and Wn = 40 μm [16] and BV = 1.1 kV in the case of ND = 2 × 1016 cm−3 and Wn = 10 μm [17]. To achieve higher BV, a nonuniformly n-type-doped drift layer, which is described in Section 10.3, has been employed [3, 18, 19]. In the case of CVD of 4H-SiC, on the other hand, minimum controllable ND can be greatly decreased by increasing the carbon-to-silicon inputgas ratio (C/Si ratio); for example, it can be decreased from 1 × 1016 cm−3

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10.3

GaN p-n Diodes with a Nonuniformly Doped Drift Layer

209

N 2 flow rate (sccm) 10 −4

10 −3

10 −2

10 −1

10 0

10 1

10 20

- −3 ) Net donor density (cm

GaN (0001) [16] 10 19

Slope = 1

Unoptimized growth Optimized growth

10 18 10 17

Slope = 1

10 16 4H -SiC (0001) [20]

10 15

C/Si =1.2 C/Si = 1.8

10 14

10 −3

10 −2

10 −1

10 0

10 1

10 2

SiH 4 flow rate (sccm, 100 ppm)

Figure 10.6 Reported net donor density in epitaxially grown GaN (0001) and 4H-SiC (0001) as functions of flow rates of SiH4 and N2, respectively [16, 20].

to 2 × 1014 cm−3 by increasing the C/Si ratio from 1.2 to 1.8 [20] (solid symbols in Figure 10.6). From Figures 10.5(b) and 10.6, it is predicted that the highest BV is about 80 kV when drift-layer thickness is 640 μm. Using such a thick drift layer, however, greatly increases RonA. By making Wn smaller than WDn (to form a so-called p-i-n junction as shown in Figure 10.7[a]), the electric-field profile becomes trapezoidal, as shown by the solid lines in Figure 10.7(b). As the doping level in the drift layer (ND1) decreases, the electric-field profile approaches a rectangle, as shown by the dashed lines in Figure 10.7(b). BV thus approaches the maximum, given as BVmax = EmaxWn

(10.3)

To take advantage of the lower and controllable ND, 4H-SiC bipolar diodes often use a p-i-n junction, which is described in Section 10.4. Note that although “i” stands for intrinsic, a lightly-doped n-type layer is usually used as an i-drift layer.

10.3

GaN p-n Diodes with a Nonuniformly Doped Drift Layer

To reduce the peak electric field at the p-n junction, a GaN p-n diode with double drift layers consisting of a 5-μm-thick n-type GaN layer doped at 1 × 1015 cm−3 and a 15-μm-thick n-type GaN layer doped at 1 × 1016 cm−3 was fabricated; the resultant BV was over 3 kV [18]. Triple drift layers were also applied to GaN p-n diodes with the following properties: BV = 3.48 kV

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Vertical GaN and SiC Power Devices

n −region

p+region neutral region

n +region

depletion region

neutral region

q ND2 q ND1 −WDp

++ +++++++ ++ − O Wn WDn − − − − − − − − − − −q NA

x

(a) E −WDp

Wn WDn O

−E max

x

Lower N D1 (b)

Figure 10.7 Reverse-biased abrupt p+/n−/n+ junction: (a) space-charge distribution under depletion approximation and (b) electric-field distribution. Compared to the solid lines in (b), the dashed lines in (b) represent the electric-field distribution in the case of lower ND1.

for a 6-μm-thick GaN layer doped at about 1 × 1015 cm−3, a 11-μm-thick n-type GaN layer doped at 3 × 1015 cm−3, and a 15-μm-thick n-type GaN layer doped at 1.2 × 1016 cm−3 [19] and BV = 5.0 kV for a 5.5-μm-thick undoped GaN with a residual silicon concentration of < 2 × 1015 cm−3, a 22-μm-thick n-type GaN with a silicon concentration of 9 × 1015 cm−3, and a 5.5-μm-thick n-type GaN with a silicon concentration of 1.6 × 1016 cm−3 [3]. Owing to extrinsic photon recycling (EPR)—see Section 4.6—differential specific on-resistance RonAdiff (see Section 1.3.2) of reported GaN p-n diodes [3, 17−19] is comparable to that of 4H-SiC p-i-n diodes [21, 22] (Figure 10.8). Due to a typical limit on power dissipation of a semiconductor package (300 Wcm/2 [23]), however, EPR does not practically work in the case of GaN p-n diodes. As shown as an example in Figure 10.9, the

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10.4

4H-SiC p-i-n Diodes

211

10

[22]

(mΩcm2 )

Differential specific on -resistance

100

[21] [3]

[18]

1

[19] [17]

0.1 102

103

104

105

Breakdown voltage (V)

Figure 10.8 Reported differential specific on-resistance of GaN p-n diodes (solid symbols [3, 17−19]) and 4H-SiC p-i-n diodes (open symbols [21, 22]) versus breakdown voltage.

maximum allowable current density of a GaN 5.0 kV p-n diode [3] is 90 A/ cm2, and its corresponding forward voltage is 3.4V. The latter voltage, however, is comparable to that of a 4H-SiC 3.5-kV junction-barrier Schottky diode (see Section 8.9) (i.e., 3.1V) [24]. In contrast, EPR should work effectively in the case of a zero-offset (see Figure 1.7[a]) GaN n-p-n BJT, which is described in Section 10.5.4.

10.4 10.4.1

4H-SiC p-i-n Diodes Reported Results Concerning 4H-SiC p-i-n Diodes

An epitaxially grown anode was used in a 4H-SiC p-i-n diode to achieve BV of 6.2 kV [25]. In the case of ion-implanted anodes, the forward characteristics were reported to be sensitive to junction depth and activation process [26]. A 4H-SiC p-i-n diode with a 100-μm-thick drift layer doped at 1 − 3 × 1014 cm−3 reportedly demonstrated VF = 7.1V at 100 A/cm2 and BV of 8.6 kV [27]. Co-implantation of aluminum, carbon, and boron was also used to form an anode of a 4H-SiC p-i-n diode with a 40-μm-thick drift layer doped at 1 × 1015 cm−3 [28]; VF at 100 A/cm2 and BV were reported as 4.7V and about 4.5 kV, respectively. These VF values are not sufficient in terms of the limit on the power dissipation of a semiconductor package (as shown in Figure 10.9). Since conductivity modulation (see Section 3.7) has not been fully achieved by using aluminum-ion implantation [29], carrier lifetime has been improved by epitaxial growth [30] and elimination of carbon-vacancy defects

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Vertical GaN and SiC Power Devices

Forward current density (A/cm2)

212

400 5.0-kV GaN p-n diode [23]

300

200

100 100

90

300 W/cm2

3.5-kV 4H-SiC JBS diode [24] 3.4

00 11

22

3.1

33 Forward voltage (V)

44

55

Figure 10.9 Reported current/voltage characteristics of a 5.0-kV GaN p-n diode [3] and a 3.5-kV 4H-SiC junction barrier Schottky diode [24], together with a curve showing the power-dissipation limit of a semiconductor package (i.e., 300 W/cm2) [23].

(i.e., carbon-ion implantation [31] and thermal oxidation [32]). Due to improved crystal growth (i.e., reduced micropipe and defect densities) and epitaxy (i.e., reduced epitaxial defects), carrier lifetime of epitaxial 4H-SiC was improved and a 10-kV p-i-n diode with VF of 3.9V at 100 A/cm2 was demonstrated in 2004 [30]. The i-drift layer used was 100-μm-thick and doped at 2 × 1014 cm−3. By applying carbon-ion implantation or thermal-oxidation, a 4H-SiC p-i-n diode with VF of about 4.0V at 100 A/cm2 was demonstrated in 2012 [33]. Its BV was calculated to be 18.5 kV in the case of a 120-μm-thick i-drift layer doped at 7 × 1013 cm−3. RonAdiff was 3.3 mΩcm2 at BV of 12.9 kV (for a 100-μm-thick drift layer doped at 3 × 1014 cm−3) [21] and 9.72 mΩcm2 at BV of 26.9 kV (for a 268-μm-thick drift layer doped at 1 − 2 × 1014 cm−3) [22], as shown by the open symbols in Figure 10.8. 10.4.2

Stored Charge in Forward-Biased 4H-SiC p-i-n Diodes

Under high-level injection (see Section 3.6.2), forward-current density is given as JF = JSHL exp(qV/2kT)

(10.4a)

JSHL = {2qDaNC0.5NV0.5 tanh(d/La)/La/[1–0.25tanh4(Wn/2La])0.5} × exp[–(Eg+qVM)/(2kT]) (10.4b) where VM is the voltage drop across an i-drift layer, and Da is ambipolar diffusivity defined as

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10.4

4H-SiC p-i-n Diodes

213

Da = 2DnDp/(Dn + Dp)

(10.4c)

where Dn and Dp are, respectively, electron and hole diffusivities, and La is ambipolar diffusion length defined as La = (Da τHL)0.5

(10.4d)

where τHL is high-level injection lifetime. Average carrier density and stored charge in the i-drift layer are thus given as nave = JF τHL/qWn

(10.5)

Qs = qWnnave = JF τHL.

(10.6)

and

According to (10.6), Qs increases with τHL at fixed JF. Therefore, decreasing τHL is necessary for reducing Qs, although large τHL is needed for reducing VF (see Section 10.4.1). To estimate Qs, the reported forward current-density/voltage characteristics of a 26.9-kV 4H-SiC p-i-n diode [22] are taken as an example in the following. When the limit on the power dissipation of a semiconductor package is 300 W/cm2 [23], JF should be less than 70 A/cm2 (Figure 10.10). If τHL in (10.6) is taken as 3 μs [22], maximum Qs is estimated to be 2.1 × 10−4 C/cm2. 10.4.3

Reverse Recovery of 4H-SiC p-i-n Diodes

As described in Section 1.2, a power diode is used as a reverse conducting device in the case of an inductive load (e.g., a motor). When the diode is a p-i-n diode, power dissipation from the on-state to the off-state is larger than that from the off-state to the on-state. This is because the charges in the i-drift layer stored during the on-state are removed first. The phenomenon by which a large reverse current is produced before the p-i-n diode can support high voltage is called “reverse recovery.” As illustrated in Figure 10.11, anode current density decreases from JF at a rate −k until WDn becomes Wn. Just after the current density reaches a minimum (i.e., JR = −k trr), voltage rises rapidly to the supply voltage [34]. The charge removed during reverse recovery is given as Qrr = JRtrr/2

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(10.7)

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Vertical GaN and SiC Power Devices

Forward current density (A/cm2)

214

140 26.9-kV 4H-SiC p-i-n diode 120 100

300 W/cm2

80 80

70 60 60 40 40 20 20

00 3 3.0

3.5 3.5

4 4.0

4.4 4.5 4.5

5 5.0

Forward voltage (V) Figure 10.10 Reported current/voltage characteristics of a 26.9-kV 4H-SiC p-i-n diode [22], together with a curve showing the power dissipation-limit of a semiconductor package (i.e., 300 W/cm2) [23].

Anode current density

JF

slope: −k

trr t

0 Qrr

−J R

Figure 10.11 Schematic anode current-density and voltage waveforms of a p-i-n diode during reverse recovery.

where trr is the reverse-recovery time shown in Figure 10.11. From (10.6) and (10.7), trr and JR are expressed as trr = (2 τ HL JF/k)0.5

(10.8)

JR = (2 k τHL JF)0.5.

(10.9)

and

For example, when τHL = 3 µs [22], JF = 70 A/cm2, and k = 2 × 107 A/cm2/s, trr and JR are calculated to be 4.6 μs and 92 A/cm2, respectively.

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10.5

n-p-n BJTs

10.5

215

n-p-n BJTs

The first SiC BJT, comprising an n-type emitter layer doped at 1020 cm−3, a 0.8-μm-thick p-type base layer doped at 4 × 1017 cm−3, and an n-type collector layer doped at 5 × 1018 cm−3, was reported in 1977 [35]; however, due to heavy collector doping, its open-base collector-to-emitter breakdown voltage BVCEO was quite low (i.e., 50V). In consideration of that drawback, this section first describes the designs of collector and base layers. Subsequently, the section examines the critical collector-current density for “second breakdown,” which is characterized as an abrupt reduction in the voltage drop across a BJT. Next, the section discusses the expected performance of GaN BJTs and the reported performance of 4H-SiC BJTs. 10.5.1

Collector-Layer Design

This section neglects the influence of conductivity modulation. Openemitter collector-to-base breakdown voltage BVCBO is the same as the BV of a p-i-n diode (see Section 10.2), namely, BVCBO = EcriticalWN−qND1WN2/(2εrεo)

(10.10)

Specific drift-region resistance RdriftA is given as RdriftA = WN/(qµnND1)

(10.11)

where μn is electron mobility. Eliminating ND1 from (10.10) and (10.11) gives the following equation: RdriftA = WN3/[2μnεrεo(EcriticalWN−BVCBO)]

(10.12)

Differentiating (10.12) with respect to x (shown in Figure 10.7) gives dRdriftA/dx = WN2(2EcriticalWN−3BVCBO)/ [2μnεrεo(EcriticalWN−BVCBO)2]

(10.13)

RdriftA reaches minimum when dRdriftA/dx = 0, namely,

WN_optimum = (3/2)(BVCBO/Ecritical)

(10.14a)

and

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Vertical GaN and SiC Power Devices

ND1_optimum = (4/9)(εrεoEcritical2/qBVCBO).

(10.14b)

BVCEO is related to BVCBO by

BVCEO = BVCBO(1 + β0)−1/n

(10.15)

where β0 is common-emitter current gain at low current, and n is about 10 for SiC [36]. As shown in Figure 10.12, BVCEO/BVCBO is calculated to be larger than 0.5 as long as β0 is less than 103. Here, BVCBO = 2BVCEO is thus assumed. Equations (10.14a) and (10.14b) are respectively expressed as WN_optimum = 3BVCEO/Ecritical

(10.16a)

ND1_optimum = (2/9)(εrεoEcritical2/qBVCEO)

(10.16b)

and

and shown in Figure 10.13. 10.5.2

Base-Layer Design

Charge density in the optimum collector layer is determined from (10.16a) and (10.16b) as Qcollector = (2/3)(εrεoEcritical/q)

(10.17)

BVCEO/BVCBO

1.01

BV CEO = BV CBO(1+ β0 )−1/10

0.9 0.9

0.8 0.8

0.7 0.7

0.6 0.6

0.5 0.5 1

10

β0

10 2

10 3

Figure 10.12 Ratio of BVCEO to BVCBO calculated using (10.15) as a function of commonemitter current gain at low current. n is assumed to be 10 [36].

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10.5

n-p-n BJTs

217

WN_optimum (… μm)

10 5 4H-SiC

10 4

GaN

10 3 10 2 10 1 10 0 10 0

10 1

10 2

10 3

BV CEO (kV)

(a) 1017 ND1_optimum (cm−3)

1016 1015 1014 10

GaN

13

1012 1011 10 0

4H-SiC

10

1

10

2

10 3

BV CEO (kV)

(b)

Figure 10.13 (a) WN_optimum and (b) ND1_optimum calculated from (10.16a) and (10.16b) as a function of BVCEO in the case BVCEO = 2BVCBO.

which is 1.4 × 1013 cm−2 in the case of GaN and 9.2 × 1012 cm−2 in the case of 4H-SiC. Charge density in a base layer should be larger than Qcollector to prevent emitter-collector punch through. In addition, base-layer thickness WB should be less than electron diffusion length Ln (see Section 3.6.1.1) to achieve high β0. Moreover, a high base-doping level is desirable from the view point of reducing emitter-current crowding, which is caused by base-current-induced voltage drop in the p-type base layer [37]. However, the base-doping level should be low enough to maintain emitter-injection efficiency γE, which is a measure of emitter current produced by electron injection from the emitter into the base, and is expressed as [37] γE = DnBtENDE+/(DnBtENDE++DpEWBNAB−)

(10.18)

where DnB and DpE are, respectively, diffusivities for electrons in the base and holes in the emitter, NDE+ and NAB− are, respectively, concentrations of ion-

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Vertical GaN and SiC Power Devices

ized donors in the emitter and acceptors in the base, and tE is emitter-layer thickness. 10.5.3

Critical Collector-Current Density for Second Breakdown

In the case of silicon BJTs, a phenomenon called second breakdown is known to limit the safe operating area (namely, the voltage and current conditions over which the device can operate) [38]. Critical collectorcurrent density JCSB for second breakdown is expressed as [38] JCSB = εrεovs Ecritical2/(2BVCBO)

(10.19)

where vs is electron saturation velocity (1 × 107 cm/s for Si [39]; 2.5 × 107 cm/s for GaN [40]; 3.3 × 106 cm/s for 4H-SiC [41]). When BVCBO = 1.2 kV (i.e., BVCEO ≈ 0.6 kV), JCSB is calculated to be 0.17 kA/cm2 for silicon BJTs, 120 kA/cm2 for GaN BJTs, and 15 kA/cm2 for 4H-SiC BJTs. In the case of silicon BJTs, JCSB lower than operational current-density is the cause for the second breakdown. In the cases of GaN and 4H-SiC BJTs, on the other hand, JCSB is larger than operational current-density, suggesting that GaN and 4H-SiC BJTs are free from second breakdown. 10.5.4

GaN BJTs

Zero-offset current/voltage characteristics of a GaN n-p-n BJT were demonstrated, although the device had a quasi-vertical configuration formed on a sapphire substrate [42]. In the case of such zero-offset BJTs, EPR is expected to work effectively. As described in Section 4.6, the lateral extension of EPR in p-type GaN was determined to be about 10 μm from the edge of the p-type electrode. Therefore, GaN BJTs with 20-μm-spaced base fingers are considered to be the most areaefficient in terms of RonA. Under the assumption of effective acceptor level EAeff determined in Section 4.6, current/voltage characteristics of 0.6-kV-class GaN BJTs (BVCBO = 1.2 kV) with a non-self-aligned base mesa structure were simulated [43]. RonA of GaN BJTs can be lower that of state-of-the-art 0.6-kV-class 4H-SiC trench MISFETs [44]. However, the BJT structure that minimizes base current density remains to be optimized. 10.5.5

SiC BJTs

The first SiC BJTs (reported in 2001) demonstrated BVCEO of 1.8 kV and β0 of 20 [45]. β0 was then increased to 50 for 2.7-kV BJTs [46], 63 for 21-kV BJTs [47], 73 for 0.6-kV BJTs [48], 110 for 0.27-kV BJTs [49], and 134 for

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10.6

Shockley Diodes

219

0.95-kV BJTs [50]. In 2011, β0 of 257 and 335 were, respectively, attained for BJTs formed on 4H-SiC (0001) and ( 000 1 ) substrates, although BVCEO of these BJTs were not reported [51]. These extremely large β0 values were achieved by utilizing optimized device geometry and continuous epitaxial growth of the emitter-base junction, in combination with a deep-levelreduction process to improve the lifetime in the base layer.

10.6

Shockley Diodes

Since neither GaN nor 4H-SiC Shockley diodes have been reported, basic characteristics of a silicon Shockley diode, which form the basis for understanding thyristor characteristics, are reviewed hereafter. The basic structure of a one-dimensional Shockley diode is schematically shown in Figure 10.14. It consists of three p-n junctions: J1, J2, and J3. The width of the region doped at P2 (WP2) is much larger than the width of the other three regions, and P2 is much lower than the other three doping levels. 10.6.1

Reverse Blocking of Shockley Diodes

In reverse-blocking mode, J1 and J3 are reverse-biased, while J2 is forward-biased. And most of the applied reverse bias is supported by the p2-region. In the case that depletion-region width at breakdown is less than Wp2, avalanche multiplication causes breakdown at BVR (Figure 10.15); in the opposite case, punch-through (namely, J2 being shorted to J3) causes breakdown at BVR. 10.6.2

Forward Blocking of Shockley Diodes

In forward-blocking mode, J1 and J3 are forward-biased, while J2 is reversebiased. Most of the applied anode voltage is thus supported by J2. When the anode voltage reaches BVF (Figure 10.15), electron-hole pairs are generated (see Section 2.6) ([1] in Figure 10.16[a]). The generated electrons and holes are injected into the n1- and p2-neutral regions, respectively ([2] and [2’] Wp2 Anode

p2

n1

p1 J1

J2

n2

Cathode

J3

Figure 10.14 Schematic structure of a one-dimensional Shockley diode. In a typical silicon Shockley diode, net doping levels are p1 ≈ 1020 cm−3, n1 ≈ 1018 cm−3, p2 ≈ 1014 cm−3, and n2 ≈ 1019 cm−3.

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Anode current

220

Forward conduction

Ih BVR O Reverse blocking

Anode voltage Vh

BV F Forward blocking

Figure 10.15 Schematic current/voltage characteristics of a Shockley diode.

in Figure 10.16[a]), resulting in a decrease of n1- and p2-depletion-region widths ([3] and [3’] in Figure 10.16[b]). To maintain charge neutrality, p1and n2-depletion-region widths are also decreased ([4] and [4’] in Figure 10.16[b]), which leads to increased forward bias at J1 and J3 ([5] and [5’] in Figure 10.16[b]). This increased forward bias increases hole injection from the p1-neutral region to the n1-neutral region ([6] in Figure 10.16[b]) and electron injection from the n2-neutral region to the p2-neutral region ([6’] in Figure 10.16[b]), which further increases electron and hole injection into the p1- and n2-neutral regions ([2] and [2’] in Figure 10.16[a]). Such positive feedback reduces anode voltage from BVF to Vh (Figure 10.15) and leads to forward conduction.

10.7

SiC Thyristors

SiC thyristors (Figure 10.2[b]) are formed by connecting gate electrodes to the n1 region of Shockley diodes (Figure 10.17). As shown in Figure 10.18, thyristors can be turned on even when the anode voltage is less than BVF (shown in Figure 10.15) by injecting electrons from the gate electrode. A 22-kV 4H-SiC GTO reported in 2014 used a 160-μm-thick p-type drift layer doped at 2 × 1014 cm−3 and demonstrated VF of 5V at 25 A/cm2 [6]. Due to the success of high-voltage SiC IGBTs described in Section 10.8, however, SiC thyristors are not so actively being developed right now.

10.8

SiC IGBTs

Since a 4H-SiC n-channel IGBT capable of attaining 13-kV blocking voltage was reported in 2007 [52], 10-kV [53], 12.5-kV [54], 16-kV [55], 22-kV

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10.8

SiC IGBTs

221

EC

(2’) Hole injection

EV

(2) Electron injection (1) Electron-hole-pair generation

-- - ++++ - - ++ + -- + J1

- - ++ - - ++ - - ++ - - ++ J2

J3 (a) (6’) Increase in electron injection

(5’) Increase in forward bias EC EV

(5) Increase in forward bias

(6) Increase in hole injection (3’) (4’) Decrease in Decrease in p2-depletion- n2-depletionregion width region width - + -+ - + -+ J3

(3) (4) Decrease in Decrease in p1-depletion- n1-depletionregion width region width - + -+ - ++ J1 J2 (b)

Figure 10.16 Schematic band diagrams illustrating the conditions immediately (a) before and (b) after anode voltage reaching BVF shown in Figure 10.15.

[56], and 27-kV [8] n-channel IGBTs have been demonstrated. Owing to conductivity modulation (see Section 3.7), RdriftA of IGBTs is greatly reduced from that of MISFETs (see Section 9.7). In contrast, the switching loss of

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Gate

Anode

p1

p2

n1

Cathode

n2

Anode current

Figure 10.17 Schematic structure of a one-dimensional thyristor.

Ih IG > 0

BV R O

IG = 0 Anode voltage

Vh

BV F

Figure 10.18 Schematic current/voltage characteristics of thyristor.

IGBTs is much larger than that of MISFETs. The reason for that switchingloss difference is similar to the reverse recovery of p-i-n diodes described in Section 10.4.3. Since the basic operating principles of SiC IGBTs are described in detail in elsewhere [57, 58], this section only provides a brief description of the turn-off characteristics of 4H-SiC IGBTs. To turn IGBTs off, gate bias has to be reduced to zero (Figure 10.19[a]). When gate bias becomes lower than threshold voltage, electron current in the channel ceases. However, in the case of an inductive load, collector current is sustained by holes stored in the n-type drift region, as shown in Figure 10.19(b). Collector bias, on the other hand, begins to increase immediately after gate bias becomes lower than threshold voltage (Figure 10.19[c]). To quench the injection of holes, controlled vanadium doping during 4H-SiC epitaxial growth has been demonstrated; the resultant epilayer doped with nitrogen and vanadium was reported to have a minority-carrier lifetime below 20 ns [59].

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10.9

Summary

223

VG

t (a) IC

t (b) VC

t (c) Figure 10.19 Schematic turn-off waveforms for n-channel IGBTs driving an inductive load: (a) gate bias, (b) collector current, and (c) collector bias.

10.9

Summary

This chapter first describes the optimum design of a one-dimensional structure to provide a clear understanding of GaN p-n diodes. Then, for a clear understanding of 4H-SiC p-i-n diodes, this chapter reviews stored charge and reverse recovery. With respect to power-switching devices, the chapter first discusses n-p-n BJTs from the viewpoints of collector/base design and second breakdown. Subsequently, for a clear understanding of 4H-SiC thyristors, the chapter describes Shockley diodes. Finally, the chapter provides a brief introduction to the reported blocking voltage of 4H-SiC n-channel IGBTs and their typical turn-off waveforms.

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References [1] Morisette, D. T., and J. A. Cooper, Jr., “Theoretical Comparison of SiC PiN and Schottky Diodes Based on Power Dissipation Considerations,” IEEE Transactions on Electron Devices, Vol. 49, No. 9, 2002, pp. 1657–1664. [2] Kajitani, R., et al., “A High Current Operation in a 1.6 kV GaN-Based Trenched Junction Barrier Schottky Diode,” Solid State Devices and Materials, Sapporo, Sept. 27–30, 2015, pp. 1056–1057. [3] Ohta, H., et al., “5.0 kV Breakdown-Voltage Vertical GaN p-n Junction Diodes,” Extended Abstracts of International Solid State Devices and Materials, Sendai, Sep. 19–22, 20017, pp. 671–672. [4] Lochner, Z., et al., “NpN-GaN/InxGa1-xN/GaN Heterojunction Bipolar Transistor on Freestanding GaN Substrate,” Applied Physics Letters, Vol. 99, 2011, pp. 193501-1–193501-3. [5] Brooks, S. E., “Modeling and Simulation of 1700-V 8-A GeneSiC Superjunction Transistor,” Thesis and Dissertation, University of Arkansas, Fayetteville, Aug. 2016. [6] Palmour, J. W., “Silicon Carbide Power Device Development for Industrial Markets,” International Electron Devices Meeting, San Francisco, Dec. 15–17, 2014, pp. 1–8. [7] Song, X., et al., “22 kV SiC Emitter Turnoff (ETO) thyristor and Its Dynamic Performance Including SOA,” International Symposium on Power Semiconductor Devices and ICs, Hong Kong, May 10–14, 2015, pp. 277–280. [8] Brunt, E. V., et al., “27-kV, 20-A 4H-SiC n-IGBTs,” Materials Science Forum, Vol. 821–823, 2015, pp. 847–850. [9] Chang, H. R., and B. J. Baliga, “500-V n-Channel Insulated Gate Bipolar Transistor with a Trench Gate Structure,” IEEE Transactions on Electron Devices, Vol. 36, No. 9, 1989, pp. 1824–1829. [10] Singh, R., et al., “High Temperature SiC Trench Gate p-IGBT,” IEEE Transactions on Electron Devices, Vol. 50, No. 3, 2003, pp. 774–784. [11] Zhang, Q., et al., “10 kV Trench Gate IGBTs on 4H-SiC,” International Symposium on Power Semiconductor Devices and ICs, Santa Barbara, May 23–26, 2005, pp. 159–162. [12] Barker, Jr., A. S., and M. Ilegems, “Infrared Lattice Vibrations and Free-Electron Dispersion in GaN,” Physical Review B, Vol. 7, No. 2, 1973, pp. 743–750. [13] Patrick, L., and W. J. Choyke, “Static Dielectric Constant of SiC,” Physical Review B, Vol. 2, No.6, 1970, pp. 2255–2256. [14] Ozbek, A. M., and B. J. Baliga, “Planar Nearly Ideal Edge-Termination Technique for GaN Devices,” IEEE Electron Device Letters, Vol. 32, No. 3, 2011, pp. 300–302. [15] Niwa, H., J. Suda, and T. Kimoto, “Impact Ionization Coefficients in 4HSiC Toward Ultrahigh-Voltage Power Devices,” IEEE Transactions on Electron Devices, Vol. 62, No. 10, 2015, pp. 3326–3333.

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Summary

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[16] Kizilyalli, I. C., et al., “Vertical Power p-n Diodes Based on Bulk GaN,” IEEE Transactions on Electron Devices, Vol. 62, No. 2, 2015, pp. 414–421. [17] Hatakeyama, Y., et al., “Over 3.0 GW/cm2 Figure-of-Merit GaN p-n Junction Diodes on Freestanding GaN Substrates,” IEEE Electron Device Letters, Vol. 32, No. 12, 2011, pp. 1674–1676. [18] Hatakeyama, Y., et al., “High-Breakdown-Voltage and Low-Specific-on-Resistance GaN p-n Junction Diodes on Freestanding GaN Substrates Fabricated Through Low-Damage Field-Plate Process,” Japanese Journal of Applied Physics, Vol. 52, 2013, pp. 028007-1–028007-3. [19] Nomoto, K., et al., “GaN-on-GaN p-n Power Diodes with 3.48 kV and 0.95 mΩcm2: A Record High Figure-of-Merit of 12.8 GW/cm2,” International Electron Devices Meeting, Washington, D.C., Dec. 7–9, 2015, pp. 237–240. [20] Kimoto, T., and J. A. Cooper, Fundamentals of Silicon Carbide Technology, Singapore: John Wiley & Sons, 2014, p. 92. [21] Sundarsesan, S., et al., “12.9 kV SiC PiN Diodes with Low On-State Drops and High Carrier Lifetimes,” Materials Science Forum, Vol. 717–720, 2012, pp. 949–952. [22] Kimoto, T., et al., “Progress in Ultrahigh-Voltage SiC Devices for Future Power Infrastructure,” International Electron Devices Meeting, San Francisco, Dec. 15–17, 2014, pp. 36–39. [23] Zhang, Q., et al., “12-kV p-Channel IGBTs with Low On-Resistance in 4H-SiC,” IEEE Electron Device Letters, Vol. 29, No. 9, 2008, pp. 1027–1029. [24] Brosselard, P., et al., “High Temperature Behaviour of 3.5 kV 4H-SiC JBS Diodes,” International Symposium on Power Semiconductor Devices and ICs, Jeju, May 27–30, 2007, pp. 285–288. [25] Sugawara, Y., et al., “6.2 kV 4H-SiC Pin Diode with Low Forward Voltage Drop,” Materials Science Forum, Vol. 338–342, 2000, pp. 1371–1374. [26] Chilukuri, R. K., et al., “High Voltage p-n Junction Diodes in Silicon Carbide Using Field Plate Edge Termination,” MRS Symposium Proceedings, Vol. 572, 1999, pp. 81–86. [27] Singh, R., “Silicon Carbide Bipolar Power Devices—Potentials and Limits,” MRS Symposium Proceedings, Vol. 640, 2001, pp. H4.2.1–H4.2.12. [28] Fedison, J. B., et al., “Al/C/B Co-implanted High Voltage 4H-SiC Pin Junction Rectifiers,” Materials Science Forum, Vol. 338–342, 2000, pp. 1367–1370. [29] Kimoto, T., et al., “Promise and Challenges of High-Voltage SiC Bipolar Power Devices,” Energies, Vol. 9, No. 11, 2016, pp. 908-1–908-15. [30] Das, M. K., et al., “High Power, Drift-Free 4H-SiC PiN Diodes,” International Journal of High Speed Electronics and Systems, Vol. 14, No. 3, 2004, pp. 860–864. [31] Storasta, L., and H. Tsuchida, “Reduction of Traps and Improvement of Carrier Lifetime in 4H-SiC Epilayers by Ion Implantation,” Applied Physics Letters, Vol. 90, No. 6, 2007, pp. 062116-1–062116-3. [32] Hiyoshi, T., and T. Kimoto, “Reduction of Deep Levels and Improvement of Carrier Lifetime in n-Type 4H-SiC by Thermal Oxidation,” Applied Physics Express, Vol. 2, No. 4, 2009, pp. 041101-1–041101-3.

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[33] Nakayama, K., et al., “Characteristics of a 4H-SiC Pin Diode with Carbon Implantation/Thermal Oxidation,” IEEE Transactions on Electron Devices, Vol. 59, No. 4, 2012, pp. 895–901. [34] Baliga, B. J., Gallium Nitride and Silicon Carbide Power Devices, Singapore: World Scientific, 2017, pp. 203–212. [35] Von Muench, W., P. Hoeck, and E. Pettenpaul, “Silicon Carbide Field-Effect and Bipolar Transistors,” International Electron Devices Meeting, Washington, D.C., Dec. 5–7, 1977, pp. 337–339. [36] Chow, T. P., “High-Voltage SiC and GaN Power Devices,” Microelectronics Engineering, Vol. 83, No. 1, 2006, pp. 112–122. [37] Baliga, B. J., Gallium Nitride and Silicon Carbide Power Devices, Singapore: World Scientific, 2017, p. 442. [38] Huang, A. Q., and B. Zhang, “The Future of Bipolar Power Transistors,” IEEE Transactions on Electron Devices, Vol. 48, No. 11, 2001, pp. 2535–2543. [39] Jacoboni, C., et al., “A Review of Some Charge Transport Properties of Silicon,” Solid State Electronics, Vol. 20, No. 2, 1977, pp. 77–89. [40] Bhapkar, U. V., and M. S. Shur, “Monte Carlo Calculation of Velocity-Field Characteristics of Wurtzite GaN,” Journal of Applied Physics, Vol. 82, No. 4, 1997, pp. 1649–1655. [41] Sankin, V. I., and A. A. Lepneva, “Electron Saturated Vertical Velocities in Silicon Carbide Polytypes,” Materials Science Forum, Vol. 338–342, 2000, pp. 769–771. [42] Terano, A., T. Tsuchiya, and K. Mochizuki, “Characteristics of GaN-Based Bipolar Transistors on Sapphire Substrates with the n-Type Emitter Region Formed Using Si-ion Implantation,” IEEE Transactions on Electron Devices, Vol. 61, No. 10, 2014, pp. 3411–3416. [43] Mochizuki, K., “Vertical GaN Bipolar Devices: Gaining Competitive Advantage from Photon Recycling,” Physica Status Solidi A, Vol. 214, No. 3, 2017, pp. 1600489-1–1600489-8. [44] Nakamura, T., et al., “High Performance SiC Trench Devices with Ultra-low Ron,” International Electron Devices Meeting, Washington, D.C., June 5–7, 2011, pp. 599–601. [45] Ryu, S.-H., et al., “1800V NPN Bipolar Junction Transistors in 4H-SiC,” IEEE Electron Device Letters, Vol. 22, No. 3, 2001, pp. 124–126. [46] Ghandi, R., et al., “Fabrication of 2700-V 12 mΩ-cm2 Non-ion-implanted 4H-SiC BJTs with Common-Emitter Current Gain of 50,” IEEE Electron Device Letters, Vol. 29, No. 10, 2008, pp. 1135–1137. [47] Miyake, H., et al., “21-kV SiC BJTs with Space-Modulated Junction Termination Extension,” IEEE Electron Device Letters, Vol. 29, No. 11, 2008, pp. 1598–1600. [48] Miyake, H., T. Kimoto, and J. Suda, “Improvement of Current Gain in 4H-SiC BJTs by Surface Passivation with Deposited Oxides Nitrided in N2O or NO,” IEEE Electron Device Letters, Vol. 32, No. 3, 2011, pp. 285–287.

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Summary

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[49] Zhang, Q., et al., “4H-SiC BJTs with Current Gain of 110,” Solid State Electronics, Vol. 52, No. 7, 2008, pp. 1008–1010. [50] Nonaka, N., et al., “A New High Current Gain 4H-SiC Bipolar Junction Transistor with Suppressed Surface Recombination Structure: SSR-BJT,” Materials Science Forum, Vol. 615–617, 2009, pp. 821–824. [51] Miyake, H., T. Kimoto, and J. Suda, “4H-SiC BJTs with Record Current Gains of 257 on (0001) and 335 on ( 000 1 ),” IEEE Electron Device Letters, Vol. 32, No. 7, 2011, pp. 841–843. [52] Das, M. K., et al., “A 13-kV 4H-SiC n-Channel IGBT with Low Rdiff,on and Fast Switching,” Materials Science Forum, Vol. 600–603, 2008, pp. 1183–1186. [53] Zhang, Q., et al., “SiC Power Devices for Microgrids,” IEEE Transactions on Power Electronics, Vol. 25, No. 12, 2010, pp. 2889–2896. [54] Ryu, S., et al., “Ultra High Voltage (> 12 kV), High Performance 4H-SiC IGBTs,” International Symposium on Power Semiconductor Devices and ICs, Bruges, July 3–7, 2012, pp. 257–260. [55] Yonezawa, Y., et al., “Low Vf and Highly Reliable 16 kV Ultrahigh Voltage SiC Flip-Type n-Channel Implantation and Epitaxial IGBT,” International Electron Devices Meeting, Washington, D.C., Dec. 9–11, 2013, pp. 164–167. [56] Brunt, E. V., et al., “22 kV, 1 cm2, 4H-SiC n-IGBTs with Improved Conductivity Modulation,” International Symposium on Power Semiconductor Devices and ICs, Waikoloa, June 15–19, 2014, pp. 358–361. [57] Kimoto, T., and J. A. Cooper, Fundamentals of Silicon Carbide Technology, Singapore: John Wiley & Sons, 2014, pp. 373–392. [58] Baliga, B. J., Gallium Nitride and Silicon Carbide Power Devices, Singapore: World Scientific, 2017, Chapter 17. [59] Miyazawa, T., et al., “Vanadium Doping in 4H-SiC Epitaxial Growth for Carrier Lifetime Control,” Applied Physics Express, Vol. 9, 2016, pp. 11130-1– 11130-4.

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CHAPTER

11 Contents

Edge Terminations

11.1 Introduction 11.2 MFP for GaN Power Devices 11.3 SM-JTE for 4H-SiC Power Devices 11.4 CD-JTE for 4H-SiC Power Devices 11.5 Hybrid-JTE for 4H-SiC Power Devices 11.6 Summary

11.1

Introduction

When a SBD is unterminated, the electric field around it is enhanced at a sharp edge of the Schottky electrode (point A in Figure 11.1[a]). Although amorphization of GaN [1, 2] and SiC [3] surfaces by using argon-ion implantation successfully relieved such electric-field enhancement, suppressing large reverse leakage, which is possibly due to residual crystalline defects, is difficult. A commonly used approach for screening such an enhanced electric field in the case of silicon SBDs is to incorporate a p+ guard ring (Figure 11.1[b]). However, in the case of GaN SBDs, magnesium-ion implantation is not an established technique (see Section 7.3.1). In the case of 4H-SiC SBDs, on the other hand, diffusion of ion-implanted aluminum is negligible (see Section 7.4). As a result, significant crowding of electric field occurs at the outer edge of the guard ring (point B in Figure 11.1[b]). Similarly, when an aluminum-ionimplanted 4H-SiC planar p-n junction is unterminated, the electric field is enhanced at the

229

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outer edge of the p-n junction (point C in Figure 11.1[c]). Consequently, edge termination, other than that formed by amorphization and a p+ guard ring, is indispensable for producing GaN and 4H-SiC power devices with breakdown voltage BV close to the ideal value. As for an edge-termination structure of GaN power devices, a field plate (FP) [4] (Figure 11.2[a]), especially a mesa field plate (MFP) without p+ guard rings [5] (Figure 11.2 [b, c]) or a MFP with a p+ guard ring [6] (Figure 11.3), is frequently used. With respect to edge-termination structures formed by ion implantation, on the other hand, field-limiting rings (FLRs) (Figure 11.4[a]) [7] have the advantage that they can be incorporated with a p+ implantation processing step. At high voltage, however, FLRs are less attractive because the spacing of each ring is limited by the capabilities of the lithography used to form it. A structure called junction termination extension (JTE) (Figure 11.4[b]) [8] is thus more favorable for fabricating high-voltage 4H-SiC power devices [9]. The biggest issue concerning JTE is its high sensitivity to the activation ratio of sheet acceptor concentration to aluminum-ion implantation dose φ. To relieve a sensitivity against variation of φ, variation of lateral doping (VLD) (Figure 11.4[c]) has been applied to silicon power devices [10]. A

Insulating film

Insulating film

Anode electrode

Anode electrode p+

A B n−-GaN

n− -GaN

n +-GaN

n +-GaN

Cathode electrode

Cathode electrode

(a)

(b) Insulating film

Anode electrode p+ C n− -GaN

n +-GaN Cathode electrode (c)

Figure 11.1 Schematic cross-sections of (a) an unterminated SBD, (b) a guard-ring-terminated SBD, and (c) an unterminated ion-implanted p+n planar junction.

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11.1

Introduction

231

Anode electrode p+-GaN

Field plate

Field plate Anode electrode Insulating film

Insulating film

n− -GaN

n−-GaN n +-GaN Cathode electrode

n +-GaN

(b) Cathode electrode (a) Anode electrode Field plate n−-GaN

Insulating film

n +-GaN Cathode electrode (c)

Figure 11.2 Schematic cross-sections of (a) a planar field-plate-terminated GaN SBD, (b) a mesa-field-plate-terminated GaN p-n diode, and (c) a mesa-field-plate-terminated GaN SBD.

VLD structure is fabricated in such a way that p-type dopant ions are implanted through a striped mask whose share of open areas decreases from the p+ anode region to the edge region. The subsequent p+ drive-in diffusion process results in a profile with decreasing doping concentration and decreasing depth toward the edge region. In the case of 4H-SiC power devices, on the other hand, drive-in diffusion is impractical due to negligible diffusivity of aluminum and anomalous diffusion of boron (see Section 7.4). Instead, several advanced types of JTEs—including the following ones that minimize the number of lithography and implantation steps—have been proposed: space-modulated JTE (SM-JTE) (Figure 11.4[d]) [11], counterdoped JTE (CD-JTE) (Figure 11.4[e]) [12], and hybrid-JTE (Figure 11.4[h]) [13], which combines ring-assisted JTE (RA-JTE) (Figure 11.4[f]) and multiple-floating-zone JTE (MFZ-JTE) (Figure 11.4[g]). It should be noted that surface of 4H-SiC is usually passivated with SiO2, and the positive charge at the SiO2/4H-SiC interface (Qf) compensates the negatively ionized acceptors in the JTE region [14−16]. A JTE that has a greater tolerance to φ can thus have a greater tolerance to Qf [12].

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p+guard ring

Polyimide

Field -plate electrode

p+GaN

p+guard ring

Main p-n diode

Anode electrode p+GaN 5.5-μm-thick un -GaN

p+GaN

22 -μm-thick n−GaN (Si: 9 × 10 15 cm−3 ) 5.5-μm-thick n−GaN (Si: 1.6 × 10 16 cm−3 ) 2-μm-thick n+GaN (Si: 2 × 10 18 cm−3 ) n +GaN substrate Cathode electrode

Figure 11.3 Schematic cross-section of a guard-ring-assisted mesa-field-plate-terminated GaN p-n diode [6].

Conventional FP, FLR, and JTE terminations are described in detail in some textbooks [17, 18]. Namely, in the case of FP, the influences of field-insulator thickness and FP length on BV of 4H-SiC Schottky and p-n junctions have been numerically calculated [18]. With respect to BV of a p-n junction terminated with FLR, an analytical expression is given in the case of a single field-limiting ring [18], while numerically calculated results are exemplified in the case of a 4H-SiC p-n junction terminated with multiple field-limiting rings [17]. As for JTE, numerically calculated BV of a 4H-SiC p-n junction is shown as a function of sheet acceptor concentration in single- [18] and two-zone [17] JTE. Therefore, this chapter describes only MFPs for GaN power devices and SM-, CD-, and hybrid-JTE for 4H-SiC power devices.

11.2 11.2.1

MFP for GaN Power Devices MFP Without Guard Rings

In a GaN p-n diode terminated with an MFP without guard rings (Figure 11.2[b]), the field-plate electrode covers the edge of the anode electrode over the insulating layer, which spreads the depletion region in the n−type GaN layer along the mesa surface. After such an MFP was first applied to GaN p-n diodes in 2011 [5], MFP-terminated GaN MISFETs [19] and MFP-terminated GaN SBDs [20] (Figure 11.2[c]) were reported in 2014 and 2015, respectively. The MFP edge terminations used in these devices were

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11.2

MFP for GaN Power Devices

SiO 2

Anode p+

233

SiO 2 n- epitaxial layer n+ substrate Cathode Counter-doped JTE (CD-JTE)

n- epitaxial layer n+ substrate Cathode Field-limiting rings (FLR)

(e)

(a) SiO 2

Anode p+

SiO 2

(f)

(b) Anode p+

SiO 2

n- epitaxial layer n+ substrate Cathode Variation of lateral doping (VLD)

(g) Anode p+

n- epitaxial layer n+ substrate Cathode Space-modulated JTE (SM-JTE)

(d)

Anode p+ n- epitaxial layer n+ substrate Cathode Multiple-floating zone JTE (MFZ-JTE)

(c) SiO 2

Anode p+ n- epitaxial layer n+ substrate Cathode Ring-assisted JTE (RA-JTE)

n- epitaxial layer n+ substrate Cathode Junction termination extension (JTE) SiO 2

Anode p+

n

SiO 2

Anode p+ n- epitaxial layer n+ substrate Cathode Hybrid-JTE

(h)

Figure 11.4 Schematic cross-sections of (a) FLRs, (b) a JTE, (c) a variation of lateral doping (VLD), (d) a space-modulated JTE (SM-JTE), (e) a counter-doped JTE (CD-JTE), (f) a ring-assisted JTE (RA-JTE), (g) a multiple-floating-zone JTE (MFZ-JTE), and (h) a hybrid-JTE.

formed on SiO2/spin-on-glass (SOG) insulating layers [5] or on SiO2/Al2O3 insulating layers [19, 20]. In 2012, 4H-SiC power devices with high-k dielectric FP terminations were studied by simulation [21]. According to the results of that study, a high-k film generates a wider depletion region than that using a SiO2 film with the same thickness. In the simulation, Si3N4 and HfO2 were used as insulating layers in a planar FP (as shown in Figure 11.2[a]). In 2016, a 0.7-μm-thick mixed oxide film consisting of CeO2:SiO2 at a ratio of 2:1 was applied as an MFP for GaN p-n diodes [22]. Although relative permittivity k of CeO2 is 26, k of the mixed oxide was lowered to 12.3 [22], which is much closer to that of GaN (i.e., 10.4 [23]) compared to that of SiO2 (i.e., 3.9). This structure led to more uniform reverse-current flow and avalanche breakdown-immune characteristics. Shown as solid circles in Figure 11.5, GaN p-n diodes terminated with an MFP using the mixed oxide (CeO2:SiO2) showed stable breakdown at 2.2 kV. In contrast, GaN diodes terminated with an MFP using SiO2 suddenly broke at 2.2 kV (open circles in Figure 11.5).

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Reverse current (A)

10 −4 10 −5 Mixed oxide of CeO2 and SiO2

SiO2

10 −6 10 −7 10 −8 0

0.5

1.0

1.5

2.0

2.5

Reverse bias (kV)

Figure 11.5 Reported reverse-current/voltage characteristics of GaN p-n diodes terminated with a MFP using SiO2 (open circles) and mixed oxide of CeO2 and SiO2 (solid circles) [22].

11.2.2

Guard-Ring-Assisted MFP

A cross-section of a GaN p-n diode terminated with a guard-ring-assisted MFP is schematically shown in Figure 11.3 [6]. A p+ guard ring is formed around the main p-n diode, and a polyimide resistor is inserted between the guard ring and the p-n diode. Without such a resistor, a p-n diode could be damaged at the outermost ring when a reverse bias is applied to it. The resistor creates a voltage drop between the p-n diode and the guard ring, thereby increasing BV from 4.8 to 5.0 kV [6].

11.3

SM-JTE for 4H-SiC Power Devices

In the case of SM-JTE, multiple rings with modulated width and spacing are embedded in a uniformly doped JTE region. Simulated breakdown voltage of 600-μm-wide SM-JTE applied to 4H-SiC p-i-n diodes (with 150-μmthick i-layer doped at 1 × 1014 cm−3) is shown in Figure 11.6 [24]. The aluminum doses for the rings and JTE region are respectively 1.8 × 1013 and 4.5 × 1012 cm−2. It is clear from Figure 11.6 that compared to uniformly doped JTE, SM-JTE offers a much wider optimum window of JTE dose to obtain nearly ideal BV.

11.4

CD-JTE for 4H-SiC Power Devices

In the case of CD-JTE, n-type counter-doping is used to create the effect of multiple zones in a uniformly p-type-doped JTE region [12]. As shown by

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11.5

Hybrid-JTE for 4H-SiC Power Devices

235

25

Breakdown voltage (kV)

20

SM-JTE

15

10 Uniformly doped JTE 5

0 0.5

1.0

1.5 2.0 JTE dose ( × 10 13 cm−2)

2.5

Figure 11.6 Reported dependences of simulated breakdown voltage of 4H-SiC p-i-n diodes (with 600-μm-wide JTEs) on JTE dose. Thickness and donor concentration of the i-layer are respectively 150 μm and 1 × 1014 cm−3. As for SM-JTE, an optimum dose window for obtaining nearly ideal breakdown voltage is remarkably enlarged [24]. SM-JTE has been applied to 21-kV 4H-SiC p-i-n diodes [25] and 21-kV 4H-SiC BJTs [26].

the open circles in Figure 11.7, BV of 4H-SiC p-i-n diodes terminated with uniformly doped JTE degrades when Qf is positive. In contrast, BV of p-i-n diodes terminated with CD-JTE degrades little up to Qf = 6 × 1012 cm−2 (solid circles in Figure 11.7), and that lack of BV degradation indicates superior robustness of BV against process variation [12].

11.5

Hybrid-JTE for 4H-SiC Power Devices

While floating rings are inserted in a uniformly doped region in a RAJTE (Figure 11.4[f]) [9, 27], dose is gradually distributed in the manner of VLD in a MFZ-JTE (Figure 11.4[g]) by controlling the width of the discrete implanted regions (i.e., zones) [28]. RA-JTE and MFZ-JTE were first optimized by Sung and Baliga. With respect to 4H-SiC p-i-n diodes with a 40-μm-thick, 2 × 1015-cm−3-doped drift layer, the optimized widths of the former and latter JTE were respectively 120 and 90 μm [29]. Six 3-μm-wide p+ rings, with spacing varied from 3 to 8 μm, were used in the optimized RA-JTE, while the width of i-th zone Wi (i = 2, 3, … 10) was varied as 10 (μm)/(1.07 × [i −1]). A hybrid-JTE was then constructed by narrowing the width of the optimized RA-JTE to 90 μm and placing the narrowed RAJTE near the p+ main junction and the 90-μm-wide MFZ-JTE next to the

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Breakdown voltage (kV)

4

3

CD-JTE

2

Uniformly doped JTE

1

0 −6

−4

−2

0

2

4

6

8

10

SiO 2/SiC interface - charge density Qf (×10 12 cm−2)

Figure 11.7 Reported dependences of simulated breakdown voltage of 4H-SiC p-i-n diodes with a 100-μm-wide CD-JTE (solid circles) and a uniformly doped JTE (open circles) on SiO2/SiC interface-charge density. Thickness and donor concentration of the i-layer are respectively 30 μm and 2 × 1015 cm−3 [12].

6 RA -JTE

Breakdown voltage (kV)

Hybrid-JTE 5 Uniformly doped JTE 4 MFZ -JTE 3

2

1 0.5

1

1.5

JTE dose ( × 10 13 cm−2) Figure 11.8 Reported JTE dose dependence of measured breakdown voltages of 4H-SiC p-i-n diodes with 180-μm-wide hybrid-JTE, 120-μm-wide RA-JTE, 90-μm-wide MFZ-JTE, and 120-μm-wide uniformly doped JTE. Thickness and donor concentration of the i-layer are, respectively, 40 μm and 2 × 1015 cm−3. The JTE doses of 9 × 1012 and 1.25 × 1013 cm−2 are respectively estimated from the implanted doses of 1.3 × 1013 and 1.8 × 1013 cm−2 under the assumption of activation ratio of 70% [29].

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11.6

Summary

237

RA-JTE (Figure 11.3[h]). As shown in Figure 11.8, a high dose in the optimized RA-JTE and uniformly doped JTE drastically reduce BV. This reduction was attributed to a high electric field at the outer edge of the JTEs [29]. Since the dose dependence of BV of the optimized MFZ-JTE is opposite to that of the optimized RA-JTE and that of the uniformly doped JTE, as for the hybrid-JTE, the optimum dose window for obtaining nearly ideal breakdown voltage is enlarged.

11.6

Summary

This chapter introduces mesa-field-plate termination structures for GaN power devices, as well as space-modulated-, counter-doped-, and hybridJTEs for 4H-SiC power devices as advanced termination structures. Readers should also refer to the latest papers on termination structures for vertical GaN and 4H-SiC power devices , since related research is still being actively conducted.

References [1] Ozbeck, A. M., and B. J. Baliga, “Planar Nearly Ideal Edge Termination Technique for GaN Devices,” IEEE Electron Device Letters, Vol. 32, No. 3, 2011, pp. 300–302. [2] Ozbeck, A. M., and B. J. Baliga, “Finite-Zone Argon Implant Edge-Termination For High-Voltage GaN Schottky Rectifiers,” IEEE Electron Device Letters, Vol. 32, No. 10, 2011, pp. 1361–1363. [3] Alok, D., B. J. Baliga, and P. K. McLarty, “A Simple Edge Termination for Silicon Carbide with Nearly Ideal Breakdown Voltage,” IEEE Electron Device Letters, Vol. 15, No. 10, 1994, pp. 394–395. [4] Conti, F., and M. Conti, “Surface Breakdown in Silicon Planar Diodes Equipped with Field Plate,” Solid-State Electronics, Vol. 15, No. 1, 1972, pp. 93–105. [5] Nomoto, K., et al., “Over 1.0 kV GaN p-n Junction Diodes on Freestanding GaN Substrates,” Physica Status Solidi A, Vol. 208, No. 7, 2011, pp. 1535–1537. [6] Ohta, H., et al., “5.0 kV Breakdown-Voltage Vertical GaN p-n Junction Diodes,” Extended Abstracts of International Solid State Devices and Materials, Sendai, Sep. 19–22, 20017, pp. 671–672. [7] Kao, Y. C., and E. D. Wolley, “High-Voltage Planar p-n Junctions,” Proceedings of IEEE, Vol. 55, No. 8, 1967, pp. 1409–1414. [8] Temple, V. A. K., and W. Tantraporn, “Junction Termination Extension for Near-Ideal Breakdown Voltage in p-n Junctions,” IEEE Transactions on Electron Devices, Vol. 33, No. 10, 1986, pp. 1601–1608.

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[9] Perez, R., et al., “Planar Edge Termination Design and Technology Considerations for 1.7-kV 4H-SiC PiN Diodes,” IEEE Transactions on Electron Devices, Vol. 52, No. 10, 2005, pp. 2309-2316. [10] Stengl, R., and U. Gösele, “Variation of Lateral Doping—A New Concept to Avoid High Voltage Breakdown of Planar Junction,” International Electron Devices Meeting, Washington, D.C., Dec. 1–4, 1985, pp. 154–157. [11] Feng, G., J. Suda, and T. Kimoto, “Space-Modulated Junction Termination Extension for Ultrahigh-Voltage p-i-n Diodes in 4H-SiC,” IEEE Transactions on Electron Devices, Vol. 59, No. 2, 2012, pp. 414–418. [12] Huang, C., et al., “Counter-doped JTE, an Edge Termination for HV SiC Devices with Increased Tolerance to the Surface Charge,” IEEE Transactions on Electron Devices, Vol. 62, No. 2, 2015, pp. 354–358. [13] Sung, W., and B. J. Baliga, “A Comparative Study 4500-V Edge Termination Techniques for SiC Devices,” IEEE Transactions on Electron Devices, Vol. 64, No. 4, 2017, pp. 1647-1652. [14] Sheridan, D. C., et al, “Comparison and Optimization of Edge Termination Techniques for SiC Power Devices,” International Symposium on Power Semiconductor Devices and ICs, Osaka, June 4–7, 2001, pp. 191–194. [15] Matsushima, H., et al, “Measuring Depletion-Layer Capacitance to Analyze a Decrease in Breakdown Voltage of 4H-SiC Diodes,” Journal of Applied Physics, Vol. 119, 2016, 154506-1-154506-6. [16] Matsushima, H, et al, “Analyzing Charge Distribution in the Termination Area of 4H-SiC Diodes by Measuring Depletion-Layer Capacitance,” Japanese Journal of Applied Physics, Vol. 55, 2016, 04ER17-1-04ER17-5. [17] Kimoto, T., and J. A. Cooper, Fundamentals of Silicon Carbide Technology, Singapore: John Wiley & Sons, 2014, pp. 427–434. [18] Baliga, B. J., Gallium Nitride and Silicon Carbide Power Devices, Singapore: World Scientific, 2017, pp. 90–115. [19] Oka, T., et al., “Vertical GaN-Based Trench Metal Oxide Semiconductor FieldEffect Transistors on a Freestanding GaN Substrate with Blocking Voltage of 1.6 kV,” Applied Physics Express, Vol. 7, No. 2, 2014, pp. 021022-1–021022-3. [20] Tanaka, N. et al., “50A Vertical GaN Schottky Barrier Diode on a Freestanding GaN Substrate with Blocking Voltage of 790V,” Applied Physics Express, Vol. 8, 2015, pp. 071001-1−071001-3. [21] Song, Q.-W., et al., “Simulation Study on 4H-SiC Power Devices with Highk Dielectric FP Terminations,” Diamond & Related Materials, Vol. 22, 2012, pp. 42−47. [22] Yoshino, M., et al., “High-k Dielectric Passivation for GaN Diode with a Field Plate Termination,” Electronics, Vol. 5, No. 2, 2016, pp. 15-1−15-7. [23] Barker, Jr., A. S., and M. Ilegems, “Infrared Lattice Vibrations and FreeElectron Dispersion in GaN,” Physical Review B, Vol. 7, No. 2, 1973, pp. 743–750.

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Summary

239

[24] Kimoto, T., et al., “Progress in Ultrahigh-Voltage SiC Devices for Future Power Infrastructure,” International Electron Devices Meeting, San Francisco, Dec. 15–17, 2014, pp. 36–39. [25] Niwa, H., J. Suda, and T. Kimoto, “21.7 kV 4H-SiC PiN Diode with a SpaceModulated Junction Termination Extension,” Applied Physics Express, Vo. 5, No. 6, 2012, pp. 1598-1600. [26] Miyake, H., et al., “21 kV SiC BJTs with Space-Modulated Junction Termination Extension,” IEEE Electron Device Letters, Vol. 33, No. 11, 2012, pp. 1598-1600. [27] Kinoshita, K., et al., “Guard Ring Assisted RESURF: A New Termination Structure Providing Stable and High Breakdown Voltage for SiC Power Devices,” International Symposium on Power Semiconductor Devices and ICs, Santa Fe, June 4–7, 2002, pp. 253–256. [28] Sung, W., et al., “A New Edge Termination Technique for High-Voltage Devices in 4H-SiC-Multiple-Floating-Zone Junction Termination Extension,” IEEE Electron Device Letters, Vol. 32, No. 7, 2011, pp. 880–882. [29] Sung, W., and B. J. Baliga, “A Near Ideal Edge Termination Technique for 4500 V 4H-SiC Devices: The Hybrid Junction Termination Extension,” IEEE Electron Device Letters, Vol. 37, No. 12, 2016, pp. 1609–1612.

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CHAPTER

12 Contents 12.1 Introduction 12.2 Tolerance to HTRB Stress

Reliability of Vertical GaN and SiC Power Devices

12.3 Tolerance to HTGB Stress 12.4 Tolerance to H3TRB Stress 12.5 Tolerance to TC Stress 12.6 Tolerance to HTO Stress 12.7 Tolerance to Terrestrial Cosmic Radiation 12.8 Summary

12.1

Introduction

This chapter describes reported reliability tests on vertical GaN and 4H-SiC power devices. They are based on JEDEC [1] and JEITA [2] standards for silicon power devices and cover high-temperature reverse bias (HTRB), hightemperature gate bias (HTGB), high-humidity, high-temperature reverse bias (H3TRB), thermal cycling (TC), and high-temperature operating (HTO), and terrestrial cosmic radiation.

12.2 Tolerance to HTRB Stress HTRB tests verify long-term stability of semiconductor-chip leakage. Semiconductor chips or power modules (Figure 12.1) are stressed with a reverse voltage (e.g., 80% of the rated blocking capability of power devices) at an ambient temperature of their operational limit.

241

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Bond wire

Insulating resin

semiconductor chip

Insulating substrate (Al2 O3 or AlN)

Solder

Base plate (Cu or AlSiC)

Figure 12.1 Schematic cross-section of a typical power module.

Mobile ions, possibly contaminations during assembly or residue of solder flux, can accumulate in high electric-field areas and generate a surface charge. The surface charge can alter the electric field in power devices and generate additional leakage [3]. In the case of vertical GaN power devices, substrate orientation has been reported to play a significant role in tolerance to HTRB stress. While on-axis epitaxial growth of GaN results in large hexagonal hillocks due to spiral growth around a screw dislocation (see Section 6.2), introducing a slight miscut of several tenths of a degree makes step-flow growth (see Section 6.5) overwhelm spiral growth. Use of step-flow growth resulted in 231 (i.e., 77/lot × 3 lots) GaN p-n diodes (rated at 1,200V and 10A) passing 1,000-h HTRB tests at 960V and 150°C. Moreover, threshold voltage Vth, specific on-resistance RonA, and forward drain current of GaN normally-onjunction field-effect transistors did not shift before and after 788-h HTRB tests [4]. With respect to normally-off transistors, over-300-h stability of Vth and off-state leakage IDS (at drain-source bias VDS = 400V) of 1.7-kV GaN p+-gate heterojunction field-effect transistors was reported [5], as described in Section 9.5.3 (Figure 12.2). In the case of MISFETs (see Section 9.7), an HTRB test stresses not only the p-n junction at the drain but also the gate insulator. According to the results of tests on commercial-off-the-shelf 4H-SiC MISFETs (rated at 1,200V and 42A) [6], after 378-h HTRB stress of 960V at 150°C, a drain-source short occurred in one of four 4H-SiC MISFETs. As shown in Figure 12.3, the other three MISFETs showed drain leakage at different levels as stress time increased. Possible mechanisms of such drain-leakage degradation include drain-to-source subthreshold leakage, band-to-band-tunneling-dominated p-n junction leakage, and interface-trap-induced leakage [6].

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12.2 Tolerance to HTRB Stress

243

10 −5

3

VDS = 400V, VGS = 0V 125°C

2

10 −6

IDS @400 V (A)

Vth (V)

Vth

I DS 10 −7 300

1 0

100

200 Time (h)

Figure 12.2 Reported results of HTRB tests on vertical GaN transistors on GaN substrates [5].

10 −2 10 −3 VDS = 960V, VGS = 0V 150°C

IDS @960 V (A)

10 −4 10−5 10 −6 10 −7 10 −8 10 −9 0

200

400

600 Time (h)

800

1000

Figure 12.3 Reported results on HTRB tests of commercial-off-the-shelf 4H-SiC MISFETs [6].

Moreover, in an HTRB test at 152°C and 90% of the rated voltage of commercial 1.2−1.7-kV 4H-SiC MISFET power modules (rated at 120−400A) [7], three out of five modules did not pass the test, showing

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that the tolerance of 4H-SiC MISFET modules to HTRB stress needs to be further improved.

12.3 Tolerance to HTGB Stress In HTGB tests, variation in Vth is monitored after prolonged gate-source bias VGS is applied to MISFETs at high temperature. Commercial-off-the-shelf 4H-SiC MISFETs (rated at 1,200V and 42A) have been tested at 150°C [6]. As shown by solid and open symbols in Figure 12.4, positive and negative VGS stresses respectively cause positive and negative shifts in Vth. This effect is attributable to electrons tunneling into or out of insulator traps in response to the electric field produced by VGS stress [8, 9].

12.4 Tolerance to H3TRB Stress In H3TRB tests, penetration of moisture through an insulating resin (Figure 12.1) is accelerated under high humidity, high temperature, and high reverse bias to verify the reliability of power modules. In the case of silicon IGBT power modules, corrosion has been reported to build up due to the formation of a closed water film linking the chip metallization of the active area being the negative electrode [10]. According to a first report on 6

150°C 5

Vth (V)

4

Vth = +20V 3

Vth = −10V

2

1

0

200

400

600

800

1000

Time (h) Figure 12.4 Reported results of HTGB tests on commercial-off-the-shelf 4H-SiC MISFETs. (Solid symbols: VGS = + 20V and 150°C; open symbols: VGS = −10V and 150°C [6].)

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12.5 Tolerance to TC Stress

245

H3TRB tests (at 85°C, 85% relative humidity, and 80V) of GaN p-n diodes, a few diodes failed after 850 hours due to delamination caused by water ingress from chip edges. After improving the encapsulation dielectric layer, however, no diodes failed in further H3TRB tests [4]. According to the reported results of H3TRB tests on commercial 0.3−0.8kV 4H-SiC MISFET power modules at 90°C, 90% relative humidity, and 65% rated voltage, two out of five modules failed after 690 and 860 hours; the former was due to failure of the diode connected with the MISFET chip, and the latter was due to failure in the gate oxide [7]. It should be noted that even in the case of three modules that passed the H3TRB test, RonA increased, showing that tolerance of 4H-SiC MISFET power modules to H3TRB stress needs to be further improved.

12.5 Tolerance to TC Stress A TC test induces an accelerated thermomechanical stress on power modules that consists of several materials with different thermal-expansion coefficients. In the case of silicon IGBT power modules, the most dominant failure is bond-wire liftoff [11]. It was reported that 385 (i.e., 77/lot × 5 lots) GaN p-n diodes (rated at 1,200V and 10A) passed 1,000-cycle TC tests when temperature was varied from −65°C to 150°C [4]. It was also reported that five TC-tested 4H-SiC MISFET commercial power modules passed 1,186 cycles when temperature varied was from −50°C to 150°C [7].

12.6 Tolerance to HTO Stress When an excited minority carrier recombines with an electronic center associated with a defect, the recombination energy is known to be released nonradiatively to induce local vibrations of the defect, which leads to some rearrangement of the defect itself [12, 13]. Although GaN-based devices have high dislocation density, their lifetimes have been reported to be long due to large shear stress under dislocation motion [14]. An HTO test on 77 GaN p-n diodes under forward current density of 20 kA/cm2 at junction temperature of 275°C actually showed no degradation of the current/voltage characteristics [4]. In contrast, electron-hole recombination at a BPD (see Section 2.2.3) in the drift layer of 4H-SiC bipolar devices induces nucleation and expansion of recombination-enhanced stacking faults, which increases their forward voltage VF [13, 15]. Dislocation motion in 4H-SiC seems to be caused by lowering the energy of the material system (see Section 2.2.3), not by applying shear stress [15]. Such recombination-induced stacking faults also degrade performance of 4H-SiC unipolar devices. For example, it was reported that

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when the body diode of a 4H-SiC MISFET with a 100-μm-thick, 6 × 1014 cm−3-doped drift layer (Figure 12.5[a]) was forward-biased (VGS = −10V) for one hour, VF increased, in a similar manner to that observed in the case of 4H-SiC p-i-n diodes (Figure 12.5[b]) [16]. In another report, 4H-SiC MPS diodes (see Section 8.6.1) with different BPD densities were forward-biased, and it was observed that VF increased as a function of injection time (Figure 12.6) [17]. The latter report shows that reducing BPD density is the most important issue in regard to improving tolerance of 4H-SiC power devices to HTO stress.

12.7 Tolerance to Terrestrial Cosmic Radiation

Gate

Source

p+

Source

n+

n + p+

p

p Body-diode current

100-μm-thick, 6 ×10 14 cm−3-doped n drift layer n + 4H- SiC

substrate

Drain (a)

Drain-source current (A)

The Earth is constantly showered by cosmic radiation with highly energetic particles, mainly protons as well as light and heavy nuclei [18]. These particles collide with air molecules to give rise to cascades of secondary particles reaching the ground. Although this terrestrial cosmic radiation is made up of neutrons, protons, pions, muons, electrons, and electromagnetic waves, neutrons account for 95% of it at sea level [19]. In the case of silicon power devices, neutrons have been shown to cause failures via interactions with lattice atoms. Resultant recoiled atoms or spallation products create charge spikes along their trajectories. Because electrons are attracted to drain or collector electrodes and holes to source or gate electrodes, these attendant electrons and holes can lead to current transients, which can turn on a parasitic bipolar transistor and result in a burn-out failure. Since the hole pile-up under the gate can increase the electric field around the gate insu-

0 −1

1h

−2

0h

−3 −4

VGS = −10V

−5 −12 −10

−8

−6

−4

−2

Drain-source voltage (V) (b)

Figure 12.5 (a) Schematic cross-section and (b) reported current/voltage characteristics of a body diode in a 4H-SiC MISFET [16].

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12.8

Summary

247

Forward- voltage Increase at 25 A/cm2 (V)

30 30°C

High BPD density

20

10

Low BPD density

0

5

10

15

20

Injection time at 75 A/cm2 (min)

Figure 12.6 Reported forward-voltage increase in 4H-SiC MPS diodes as a function of injection time [17].

lator to the point of causing catastrophic failure, a gate rupture failure can also occur [20]. However, neutron-induced failures are not well understood in the cases of GaN and 4H-SiC power devices [20−26]. For example, in one study, GaN p-n diodes were exposed to 1-MeV 3 × 1013-cm−2 neutrons [21]. According to the results of that study, RonA increased from 2−3 mΩcm2 by 3 mΩcm2, while breakdown voltage BV decreased from 1,740V by 80V. Such degradation of RonA and BV indicates that both on- and off-state performances are impacted by radiation-induced defects within the drift region of GaN p-n diodes. On the other hand, when tolerances of commercial silicon and 4HSiC MISFETs to terrestrial neutron radiation were compared [20], it was found that although neutrons give rise to fewer failures in SiC MISFETs compared to silicon MISFETs, the failure modes in SiC MISFETs can differ depending on the vendor. These results show that tolerances of vertical GaN and 4H-SiC power devices to terrestrial cosmic radiation have to be further investigated.

12.8

Summary

This chapter briefly describes reported results of HTRB-, HTGB-, H3TRB-, TC-, HTO-, and terrestrial cosmic radiation tests on vertical GaN and 4H-SiC power devices. Readers should refer also to the latest papers on such reliability tests because related research is still being actively conducted.

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References [1] JEDEC, Solid State Technology Association, Temperature, Bias, and Operating Life, JESD22-A108D, 2005. [2] JEITA, Environmental and Endurance Test Methods for Semiconductor Devices, EIAJ ED-4701/100, Tokyo, Japan, 2001. [3] Lutz, J., et al., Semiconductor Power Devices Physics, Characterization, Reliability, Heidelberg: Springer, 2011, pp. 380−411. [4] Kizilyalli, I. C., et al., “Reliability Studies of Vertical GaN Devices Based on Bulk GaN Substrates,” Microelectronics Reliability, Vol. 55, No. 9−10, 2015, pp. 1654–1661. [5] Shibata, D., et al., “1.7 kV/1.0 mΩcm2 Normally-Off Vertical GaN Transistor on GaN Substrate with Regrown p-GaN/AlGaN/GaN Gate Structure,” International Electron Devices Meeting, San Francisco, Dec. 5–7, 2016, pp. 248–251. [6] Yang, L., and A. Castellazzi, “High Temperature Gate-Bias and ReverseBias Tests on SiC MOSFETs,” Microelectronics Reliability, Vol. 53, 2013, pp. 1771–1773. [7] Ionita, C., and M. Nawaz, “End User Reliability Assessment of 1.2–1.7 kV Commercial SiC MOSFET Power Modules,” International Reliability Physics Symposium, Monterey, April 2–6, 2017, pp. WB-1.1–WB-1.6. [8] Lelis, A., et al., “Time Dependence of Bias-Stress-Induced SiC MOSFET Threshold Voltage Instability Measurements,” IEEE Transactions on Electron Devices, Vol. 55, No. 8, 2008, pp. 1835–1840. [9] Lelis, A., et al., “Temperature-Dependence of SiC MOSFET Threshold-Voltage Instability,” Materials Science Forum, Vol. 600–603, 2009, pp. 807–810. [10] Minzari, D., et al., “Electrochemical Migration on Electronic Chip Resistors in Chloride Environments,” IEEE Transactions on Device Materials Reliability, Vol. 9, No. 3, 2009, pp. 392–402. [11] Wang, H., et al., “Transitioning to Physics-of-Failure as a Reliability Driver in Power Electronics,” IEEE Journal of Emerging and Selected Topics in Power Electronics, Vol. 2, No. 1, 2014, pp. 97–113. [12] Kimmering, L. C., “Recombination Enhanced Defect Reactions,” Solid-State Electronics, Vol. 21, 1978, pp. 1391–1401. [13] Maeda, K., K. Suzuki, and M. Ichihara, “Recombination Enhanced Dislocation Glide in Silicon Carbide Observed In-Situ by Transmission Electron Microscopy,” Microscopy, Microanalysis, Microstructures, Vol. 4, 1993, pp. 211–220. [14] Sugiura, L., “Dislocation Motion in GaN Light-Emitting Devices and Its Effect on Device Lifetime,” Journal of Applied Physics, Vol. 81, No. 4, 1997, pp. 1633–1638. [15] Skowronski, M., and S. Ha, “Degradation of Hexagonal SiliconCarbide-Based Bipolar Devices,” Journal of Applied Physics, Vol. 99, 2006, pp. 011101-1–011101-24. [16] Agarwal, A., “A New Degradation Mechanism in High-Voltage SiC Power MOSFETs,” IEEE Electron Devices Letters, Vol. 28, No. 7, 2007, pp. 587–589.

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[17] Caldwell, J. D., “Recombination-Induced Stacking Fault Degradation of 4HSiC Merged-PiN-Schottky Diodes,” Journal of Applied Physics, Vol. 106, 2009, pp. 044504-1–044504-6. [18] Soelkner, G., “Ensuring the Reliability of Power Electronic Devices with Regard to Terrestrial Cosmic Radiation,” Microelectronics Reliability, Vol. 58, 2016, pp. 39–50. [19] Ziegler, J. F., “Terrestrial Cosmic Ray Intensities,” IBM Journal of Research and Development, Vol. 40, No. 1, 1996, pp. 19–39. [20] Akturk, A., “Single Even Effects in Si and SiC Power MOSFETs due to Terrestrial Neutrons,” IEEE Transactions on Nuclear Science, Vol. 64, No. 1, 2017, pp. 529–535. [21] King, M. P., et al., “Performance and Breakdown Characteristics of Irradiated Vertical GaN P-i-N Diodes,” IEEE Transactions on Nuclear Science, Vol. 62, No. 6, 2015, pp. 2912–2918. [22] Rashed, K., et al., “Terrestrial Neutron Induced Failure In Silicon Carbide Power MOSFETs,” IEEE Radiation Effects Data Workshop, Paris, July 14–18, 2014, pp. 1–4. [23] Akturk, A., R. Wilkins, and J. McGarrity, “Terrestrial Neutron Induced Failures in Commercial SiC Power MOSFETs at 27C and 150C,” IEEE Radiation Effects Data Workshop, Boston, July 13–17, 2015, pp. 115–119. [24] Asai, H., et al., “Tolerance Against Terrestrial Neutron-Induced Single-Event Burnout in SiC MOSFETs,” IEEE Transactions on Nuclear Science, Vol. 61, No. 6, 2014, pp. 3109–3114. [25] Asai, H., et al., “Terrestrial Neutron-Induced Single-Event Burnout in SiC power diodes,” IEEE Transactions on Nuclear Science, Vol. 59, No. 4, 2012, pp. 880–885. [26] Griffoni, A., et al., “Neutron-Induced Failure in Silicon IGBTs, Silicon SuperJunction and SiC MOSFETs,” IEEE Transactions on Nuclear Science, Vol. 59, No. 4, 2012, pp. 866–871.

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About the Author Kazuhiro Mochizuki received a B.S. (1986), M.S. (1988), and Ph.D. (1995) in electronic engineering from the University of Tokyo, Japan. In 1988, he joined the Central Research Laboratory, Hitachi Ltd., Tokyo, where he was involved in the research of GaN and SiC power devices, as well as GaAs microwave power amplifiers. From 1999 to 2000, he was a visiting researcher at the University of California, San Diego. Since 2015, he has been on loan to the National Institute of Advanced Industrial Science and Technology, Japan. His current research interests are related to high-voltage superjunction power devices. He is the author or coauthor of over 100 research papers in international journals and conference proceedings. He is a senior member of the Institute of Electrical and Electronics Engineers and a member of the Japan Society of Applied Physics. He is a part-time lecturer with the University of Electro-Communications, Tokyo, and with Hosei University, Tokyo.

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Index A AlGaN/GaN diodes, 8–9 AlGaN/GaN heterostructures, 174–75 AlN band lineup, 175–76 crystal structures, 17–20 optical-absorption coefficients, 27 Aluminum-ion implantation, 121–25 Ammonothermal growth of GaN, 88 Amorphization-suppressed channeling, 124 Areal defects, 23 Auger recombination defined, 47–48 rate, 48 schematic illustration, 45 See also Recombination lifetime B Baliga’s figure of merit for devices operating at high frequencies (BHFFOM), 33–35 Baliga’s figure of merit for power devices (BFOM), 33–35 Band-to-band recombination in carrier lifetimes, 45–46 coefficient, 44 defined, 44 schematic illustration, 45 Basal-plane dislocation (BPD), 22 Base-layer design, 216–18

Binary-collision approximation (BCA), 125 Bipolar junction transistors (BJTs) control electrodes, 206 defined, 205 GaN, 218 n-p-n, 215–19 schematic cross-section, 205 SiC, 218–19 zero-offset, 218 Bipolar power diodes introduction to, 203–6 schematic cross-section, 204 Bipolar power-switching devices BJTs, 205, 206 introduction to, 204–6 schematic cross-section, 205 summary, 223 Boron-concentration profiles, 128 Boron diffusion in SiC, 125–27 Boron interstitial, 127 Breakdown voltage (BV), 2, 34, 66, 109, 147 Bulk crystal growth ammonothermal growth of GaN, 88 HPNS growth of GaN, 87 HT-CVD of SiC, 90, 91 HVPE growth of GaN, 84–87 introduction to, 83 sodium-flux growth of GaN, 87–88 solution growth of SiC, 90–91

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Bulk crystal growth (continued) sublimation growth of SiC, 89–90 summary, 91–92 Bulk defects, 24 Burton-Cabrera-Frank (BCF) theory, 101–3 calculation based on, 100 defined, 101 C Carrier mobility, 30–32 Charge density base layer, 217 optimum collector layer, 216 Chemical etching, 119 Chemical-vapor deposition (CVD) of 4H-SiC, 97, 103–9 chemical reactions, 104–5 overview, 103–4 step-controlled epitaxy, 105 step velocity calculation, 107 surface mass fluxes, 105 trench filling, 109–11 use of, 103 Collector-layer design, 215–16 Conduction band, 25 Continuity equations, 43–44 Counter-doped JTE (CD-JTE), 231, 234–35 Crystal defects, 21–24 Crystal momentum, 25, 26 Crystal structures, 16–24 AlN, 17–20 GaN, 17–20 overview, 16–17 rock-salt, 17 SiC, 20–21 wurtzite, 18, 19, 20 zincblende, 18 Current/voltage characteristics based on diffusion theory, 149–50 based on TED theory, 150–51 based on TFE theory, 151–53 body diode in 4H-SiC MISFET, 246 example of, 55–57

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4H-SiC p-i-n diodes, 214 high-level injection conditions, 55 low-level injection condition, 52–55 multidimensional, 57–61 one-dimensional, 52–57 Shockley diodes, 220 thyristors, 222 TLM patterns, 78 zero-offset, 218 D Dark current-density/voltage characteristics, 70 Defined, 63 Depletion-region width, 50–51 Diffusion boron, in SiC, 125–27 defined, 42 dual-sublattice modeling, 127–29 overview, 125 semi-atomistic, 129–31 See also Fabrication processes Diffusion current, 52–53 Diffusion length, 66 Diffusion theory, 149–50 Direct-bandgap semiconductors, 26, 27, 66 Dislocations, 22 Drift layers illustrated, 110 nonuniformly doped, 209–11 SJ, 194, 195 triple, 209–10 uniformly doped, 207 Drift region, resistivity of, 179 Drift velocity, 30, 147 Dual-Pearson distribution, 122 Dual-Pearson parameters, 123, 124 Dual-sublattice diffusion modeling, 127–29 E Edge terminations CD-JTE for 4H-SiC power devices, 234–35

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Index

hybrid-JTE for 4H-SiC power devices, 235–37 introduction to, 229–32 MFP for GaN power devices, 232–34 SM-JTE for 4H-SiC power devices, 234 Einstein-field strength dependences, 148 Einstein relation, 42, 147, 149 Electric field, 50 Electron concentration, 43 Electron-hole recombination energy, 160 Electrons current densities of, 44 effective mass of, 147 Electron tunneling, 152, 154 Emitter-turn-off thyristors (ETOs), 206 Energy bands, 24–27 Epitaxial growth BCF theory, 101–3 CVD of 4H-SiC, 103–9 CVD trench filling of 4H-SiC, 109–11 introduction to, 97 with inverse-pyramidal pits, 86 MOCVD of GaN, 97–100 summary, 111 trench-filling, 111 two-dimensional nucleation theory, 100–101 Epitaxial layer, refilling, 109–10 Equilibrium desorption flux, 108 Equilibrium gas-phase concentration, 110 Etching chemical, 119 ICP, 118, 182 overview, 117–20 photoelectrochemical, 119–20 wet chemical, 119–20 See also Fabrication processes Extrinsic photon recycling energy-band diagrams, 79 GaN p-n diodes, 210 models for, 78–80

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255 F Fabrication processes, 117–34 diffusion, 125–31 etching, 117–20 introduction to, 117 ion implantation, 120–25 metallization, 133–34 oxidation, 132–33 passivation, 134 summary, 134 Fermi level, 144, 171 Fermi potential, 172 Fick’s law, 42 Field-limited rings (FLRs) defined, 230 schematic cross-section, 233 Forward-biased Schottky junction, 146–48 Forward blocking, of Shockley diodes, 219–20 Forward-current/voltage characteristics based on diffusion theory, 149–50 based on TED theory, 150–51 graded AlGaN SBD, 156 JBS diodes, 162 one-dimensional, 52–55 4H-SiC aluminum-ion implantation into, 121–25 band lineup, 175–76 boron diffusion in, 128 boron-doped homoepitaxy, 127 etching, 117–20 net donor density, 209 nitrogen-ion implantation into, 125 ohmic contacts to, 133–34 phosphorus-ion implantation into, 125 pure SBDs, 155–57 SBDs with thin p+-type layer, 157 stacking-fault energy, 160 thermal oxidation of, 132–33 trench SBD, 158 See also SiC 4H-SiC diodes

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256

Forward-current/voltage characteristics (continued) fabrication by multiepitaxy, 109 forward-voltage increase in, 247 JBS, 161–63 p+ region of, 57 4H-SiC JFETs, 183–85 controlling gate, 183 defined, 183 high-voltage normally-on, 185 schematic cross-sectional views, 184 4H-SiC p-i-n diodes current/voltage characteristics, 214 defined, 211 dependences of simulated breakdown voltage, 236 forward-biased, stored charge in, 212–13 JTE dose dependences, 236 reported results concerning, 211–14 reverse recovery of, 213–14 4H-SiC power devices CD-JTE for, 234–35 hybrid-JTE for, 235–37 n-type starting material, 41 SM-JTE for, 234 4H-SiC SJ MISFETs, 195 4H-SiC substrates, 106 4H-SiC trench MISFETs, 191–94 breakdown voltage (BV), 191–92 double-trench, 193 single-trench, 193 V-groove, 193, 194 Free energy nucleus formation, 101 Frenkel defects, 21 G GaAs single-junction solar cell, 69 Gallium nitride. See GaN GaN ammonothermal growth of, 88 areal defects, 23 under arsenic-rich atmosphere, 102 band lineup, 175–76 binary systems, 83, 84 carrier mobility, 30–32

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crystal structures, 17–20 effective carrier lifetime, 204 energy bands, 24–27 epitaxially grown, net donor density, 209 etching, 117–20 figure of merit, 33–35 under gallium-rich atmosphere, 102 HPNS growth of, 87 HVPE growth of, 84–87 ICP etching, 118 impact ionization, 32–33 impurity doping, 27–30 introduction to physical properties of, 15–16 mechanism of HVPE growth of, 85–86 MOCVD of, 97–100 ohmic contacts to, 133 optical-absorption coefficients, 27 p-n, schematic simulation, 59 practical optical devices, 16 pure SBDs, 153–55 sodium-flux growth of, 87–88 stacking faults and, 22 thermal oxidation of, 132 GaN BJTs, 218 GaN diodes MPS, 161 p+ region of, 57 GaN HFETs defined, 176 MESFETs, 181 MIS, 176–80 p+-gate, 181–83 GaN MESFETs, 181, 182 GaN MIS HFETs defined, 176 normally-on characteristics, 178 process flow for forming aperture, 177, 178 resistance of, 180 schematic cross-section, 177 GaN p-n diodes differential specific on-resistance of, 211

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Index

extrinsic photon recycling, 210 forward-biased, 71–78 influence of photon recycling on, 74–78 junction temperature, 74 measured forward-current/voltage characteristics of, 73 self-heating effect, 72–74 GaN p-n junctions, 78 GaN power devices n-type starting material, 41 reliability of, 241–47 GaN shielded-trench MISFETs, 192 GaN trench MISFETs, 191 GaN unipolar power-switching devices lateral, current per chip, 7 vertical, 8 vertical versus lateral, 6–8 voltage-rating dependence, 6 Gate-turn-off thyristors (GTOs), 206 Gauss’s Law, 194 Graded AlGaN SBDs, 156, 157 Guard-ring-assisted MFP, 234 H Heat-flow fraction, 73 Heterojunction FETs (HFETs), 170, 176–83 High-electron mobility transistors (HEMTs), 121 High-humidity, high-temperature reverse bias (H3TRB) stress, 241, 244–45 High-level injection conditions, 55 High-pressure nitrogen solution (HPNS) growth, 86 High-temperature chemical vapor deposition (HT-CVD) of SiC, 90, 91 High-temperature gas bias (HTGB) stress, 241, 244 High-temperature operating (HTO) stress, 241, 245–46 High-temperature reverse bias (HTRB) stress, 241–44 Hybrid JTE, 231, 235–37

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Hydride vapor-phase epitaxy (HVPE) growth of GaN doping during, 86 epitaxial lateral overgrowth of, 86–87 epitaxy zone, 86 mechanism of, 85–86 overview of, 84 schematic illustration, 85 Hydrogen chloride (HCl) gas, 111 I ICP etching, 119–20, 182 Idealized MIS capacitors, 170–73 Impact ionization, 32–33 Impurity doping, 27–30 n-type, 28–29 overview, 27–28 p-type, 29–30 Inductively coupled plasma (ICP) dry etching, 75 Insulated-gate bipolar transistors (IGBTs) backside electrode, 206 defined, 205 schematic cross-section, 205 SiC, 220–23 structure, 206 Internal photon recycling, 68 Internal quantum efficiency, 66 Interstitials, 21, 22 Intrinsic photon recycling effect on vertical GaN p-n diodes, 68, 70–71 forward-biased GaN p-n diodes, 71–72 schematic band diagrams, 68 See also Photon recycling Inversion domains, 23 Ion implantation aluminum-ion, 121–25 into 4H-SiC, 121–25 into GaN, 121 nitrogen-ion, 125 for n-type dopant implementations, 121

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Ion implantation (continued) overview, 120–21 phosphorus-ion, 125 silicon-ion, 121 See also Fabrication processes J JBS diodes defined, 161–62 forward-current/voltage characteristics, 162 high-voltage, 162 implantation, 162 Junction breakdown, 61–63 Junction field-effect transistor (JFET) 4H-SiC, 183–85 defined, 169, 183 Junction termination extension (JTE) counter-doped (CD-JTE), 231, 234–35 defined, 230 dose dependences, 236 hybrid, 231, 235–37 multiple-floating-zone (MFZ-JTE), 231 ring-assisted (RA-JTE), 231 schematic cross-section, 233 space-modulated (SM-JTE), 231, 234 terminations, 232 types of, 231 L Lateral GaN, 11 Lateral range straggling, 125 Lateral unipolar power diodes, 9–10 Line defects, 22 Low-level injection condition, 52–55 M Mass-action law, 27 Mesa field plate (MFP) defined, 230 for GaN power devices, 232–34 guard-ring-assisted, 234

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without guard rings, 232–33 Mesa-type p+ diodes non-self-aligned, 60–61, 62, 71 schematic cross-section, 58 Metal-insulator-semiconductor capacitors. See MIS capacitors Metal-insulator-semiconductor fieldeffect transistors (MISFETs), 121, 132 defined, 185 double-diffusion process, 186 planar, 187–90 schematic cross-section, 186 SJ, 194–96 trench, 186, 191–94 Metallization ohmic contacts to 4H-SiC, 133–34 ohmic contacts to GaN, 133 See also Fabrication processes Metal-organic chemical-vapor deposition (MOCVD) of GaN defined, 97 experimental growth-spiral rate, 100 growth spirals, 99 in nitrogen-rich atmosphere, 98 schematic illustration, 98 source gases for, 208 Metalorganic vapor-phase epitaxy (MOVPE), 97 Metal-semiconductor field-effect transistors (MESFETs), 169–70 Metal work function, 171, 172 Minority-carrier lifetime, 66 MIS capacitors idealized, 170–73 insulator and fixed charges and, 173–74 summary, 196 Monte Carlo simulation, 129, 130 Multidimensional forward-current/ voltage characteristics electric-field concentration influence, 60–61 surface recombination influence simulation, 59–60

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Index

surface-recombination velocity, 57–59 Multiple-floating-zone JTE (MFZ-JTE), 231 N Nitrogen-ion implantation, 125 Nonplanar growing surfaces, schematic cross sections of, 111 Non-self-aligned mesa p+n diodes, 60–61, 62, 71 N-p-n BJTs base-layer design, 216–18 collector-layer design, 215–16 critical collector-current density, 218 defined, 215 GaN, 218 SiC, 218–19 See also Bipolar junction transistors (BJTs) N-type doping, 28–29 N-type semiconductors, 27 O Occupation sites, 24 Off-angle dependence, on critical growth rate, 109 Ohmic contacts to 4H-SiC, 133–34 to GaN, 133 One-dimensional forward-current/ voltage characteristics diffusion current, 52–53 example of, 55–57 low-level injection condition, 52–55 space-charge recombination current, 53–55 Optical absorption spectroscopy, 26 Organometallic chemical-vapor deposition (OMCVD), 97 Organometallic vapor-phase epitaxy (OMVPE), 97 Oxidation of 4H-SiC, 132–33 of GaN, 132

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overview, 132 See also Fabrication processes P Paradoxical profile broadening, 121 Passivation, 134 Pearson type IV distribution functions, 123 Permittivity, 207 Permittivity-to-thickness ratio, 188 Phosphorus-ion implantation, 125 Photoelectrochemical (PEC) etching, 119–20 Photon recycling effects of, 65–80 efficient, 70 extrinsic, 78–80 family tree of phenomena, 67–68 first utilization, 66 forward-biased GaN p-n diodes, 74–78 GaN p-n diode performance and, 65–66 internal, 68 intrinsic, 68–72 introduction to, 65–67 light-emitting diode schematic crosssection, 67 overview, 66–67 summary, 80 Planar MISFETs current-flow path, 188 4H-SiC, 187–90 higher-voltage, 189 6H-SiC, 187 specific resistance, 190 See also Metal-insulatorsemiconductor field-effect transistors (MISFETs) P-n diodes GaN, with nonuniformly doped drift layer, 209–11 one-dimensional, optimum design of, 206–9

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260

P-n junctions abrupt, under thermal equilibrium, 51 breakdown, 61–63 carrier recombination lifetime and, 44–49 continuity equations and, 43–44 depletion-region width, 50–51 diffusion and, 42 introduction, 41 one-dimensional forward-current/ voltage characteristics, 52–57 peak electric field, reducing, 209 reverse-biased, 210 summary, 63 Polytypes atomic arrangements of, 20 schematic cross-sections, 21 Power devices applications of, 2, 3 as diodes, 2 reliability of, 241–47 as switches, 2 typical characteristics, 2 vertical versus lateral, 1–12 Power diodes bipolar, 203–23 current-voltage characteristics, 4 unipolar, 134 vertical versus lateral, 8–10 Power module, schematic cross-section, 242 Power-switching devices bipolar, 5 offset-voltage characteristics, 5 unipolar, 5–8 vertical versus lateral, 4, 5–8 zero-offset-voltage, 5 P-type doping, 29–30 P-type semiconductors defined, 27 electron concentration at surface, 172 metal work function, 171 Pure SBDs 4H-SiC, 155–57

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GaN, 153–55 high-voltage, 155 See also Schottky-barrier diodes (SBDs) R Range straggling, 126 Recombination lifetime Auger, 47–48 band-to-band, 44–46 calculated, 49 carrier concentration decays through, 44 overall expression for, 48–49 photon recycling and, 66 schematic illustrations, 45 SRH, 46–47 Relative permittivity, 174 Reliability introduction to, 241 tolerance to H3TRB stress, 244–45 tolerance to HTGB stress, 244 tolerance to HTO stress, 245–46 tolerance to HTRB stress, 241–44 tolerance to TC stress, 245 tolerance to terrestrial cosmic radiation, 246–47 Reverse blocking, of Shockley diodes, 219 Reverse-current/voltage characteristics based on TFE theory, 151–53 4H-SiC SBDs, 153 Reverse recovery anode current-density and voltage waveforms, 214 charge removed during, 213–14 of forward-biased 4H-SiC p-i-n diodes, 213–14 Richardson constant, 151 Ring-assisted JTE (RA-JTE), 231 Room temperature, 31, 32 S Schottky-barrier diodes (SBDs) active regions of, 155

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Index

4H-SiC, with thin p+-type layer, 157–59 graded AlGaN, 156, 157 measured at room temperature, 153 pure 4H-SiC, 155–57 pure GaN, 153–55 reverse characteristics, 152 shielded planar, 159–63 trench, 158–59 unterminated, 229, 230 with wider-bandgap layer, 155 Schottky-barrier height, 145 Schottky-barrier lowering, 145–46, 163 Schottky defects, 21 Schottky junction defined, 144 depletion region near, 149 forward-biased, 146–48 GaN, 151 silicon, 151 Secondary ion mass spectrometry (SIMS), 125 Second breakdown, 218 Self-heating effect, on forward-biased GaN p-n diodes, 72–74 Semi-atomistic diffusion, 129–31 Shielded planar SBDs defined, 159 electron-hole recombination energy, 160 Shockley diodes current/voltage characteristics, 220 defined, 219 forward blocking of, 219–20 reverse blocking of, 219 Shockley-Read-Hall (SRH) recombination defined, 46 mid-gap level, 47 rate, 46 schematic illustration, 45 See also Recombination lifetime SiC binary systems, 83, 84 boron diffusion in, 125–27 carrier mobility, 30–32

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crystal structures, 20–21 energy bands, 24–27 figure of merit, 33–35 HT-CVD of, 90, 91 ICP etching, 118 impact ionization, 32–33 impurity doping, 27–30 introduction to physical properties of, 15–16 optical-absorption coefficients, 27 solution growth of, 90–91 sublimation growth of, 89–90 as substrate for growing a SiC layer, 16 See also 4H-SiC SiC IGBTs defined, 220–22 schematic turn-off waveforms, 223 turn-off characteristics, 222 SiC thyristors, 220 SiC unipolar power-switching devices, 8, 9 Silicon carbide. See SiC Silicon-ion implantation, 121, 177 Silicon-trench MOSFETs, 192 Single-Pearson model, 123 SJ diodes, 109 SJ MISFETs advantage of, 195 4H-SiC, 195 GaN, 195 impact of, 196 overview, 194–95 Sodium-flux growth of GaN, 87–88 Solution growth of SiC, 90–91 Space-modulated JTE (SM-JTE), 231, 234 Stacking-fault energy, 160 Stacking faults, 22 Stacking-fault sites, 24 Static-induction transistor (SIT), 169 Step-controlled epitaxy, 105 Stored charge, in forward-biased 4H-SiC p-i-n diodes, 212–13 Sublimation growth of SiC doping during, 90

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262

Sublimation growth of SiC (continued) mechanism of, 89–90 overview, 89 Surface mass fluxes, 105 Surface recombination influence simulation, 59–60 velocity, 57–59 T TED theory, 150–51 Terrestrial cosmic radiation, 241, 246–47 Thermal cycling (TC) stress, 241, 245 Thermal equilibrium, 21 Thermal oxidation of 4H-SiC, 132–33 of GaN, 132 overview, 132 Thermionic emission theory, 146 Thermionic-field emissions (TFE) defined, 151 reverse-current/voltage characteristics based on, 151–53 Threading edge dislocation (TED), 22 Three-phase voltage-source inverter, 4 Thyristors current/voltage characteristics, 222 ETO, 206 formation of, 205–6 GTO, 206 schematic cross-section, 205 schematic structure, 222 SiC, 220 TLM measurement setup, 75, 76 TLM patterns, 76, 77 current/voltage characteristics, 78 plan view, 75 Tolerance to H3TRB stress, 244–45 to HTGB stress, 244 to HTO stress, 245–46 to HTRB stress, 241–44 to TC stress, 245 to terrestrial cosmic radiation, 246–47 Total drift current density, 31

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Trench MISFETs basic structure of, 191 channel density and, 186 4H-SiC, 191–94 4H-SiC V-groove, 194 GaN, 191 See also Metal-insulatorsemiconductor field-effect transistors (MISFETs) Trench SBD, 158–59 Turn-on voltage, 161 Two-dimensional electron gas (2DEG), 174 Two-dimensional nucleation mode, 108 side surface, 106 silicon-rich atmosphere, 108 Two-dimensional nucleation theory, 100–101 U Unipolar power diodes advantage of, 143 energy-band diagrams, 145 introduction to, 143–45 lateral, schematic illustration, 9 Schottky junction, 144 vertical versus lateral, 8–10 Unipolar power-switching devices AlGaN/GaN heterostructures, 174–75 4H-SiC JFETs, 183–85 GaN, 6–8 GaN HFETs, 176–83 MISFETs, 185–96 schematic illustration, 6 SiC, 8 summary, 196 vertical versus lateral, 5–8 V Vacancies, 21, 22 Vacuum level, 144, 145 Valence band, 24–25 Variation of lateral doping (VLD), 230

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Index

Vertical GaN, 11 Vertical GaN unipolar power diode, 10 Vertical SiC, 11 V-groove trench MISFETs, 194 Void-assisted separation (VAS), 86 W Wet chemical etching chemical, 119 defined, 119 photoelectrochemical, 119–20 See also Etching

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Wide-bandgap semiconductors, 1 Work function, 144, 171, 172 Wurtzite crystal structure, 18, 19, 20 Z Zener breakdown, 61, 63 Zero-offset current/voltage characteristics, 218 Zincblende crystal structure, 19

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Artech House Microwave Library Behavioral Modeling and Linearization of RF Power Amplifiers, John Wood Chipless RFID Reader Architecture, Nemai Chandra Karmakar, Prasanna Kalansuriya, Randika Koswatta, and Rubayet E-Azim Control Components Using Si, GaAs, and GaN Technologies, Inder J. Bahl Design of Linear RF Outphasing Power Amplifiers, Xuejun Zhang, Lawrence E. Larson, and Peter M. Asbeck Design Methodology for RF CMOS Phase Locked Loops, Carlos Quemada, Guillermo Bistué, and Iñigo Adin Design of CMOS Operational Amplifiers, Rasoul Dehghani Design of RF and Microwave Amplifiers and Oscillators, Second Edition, Pieter L. D. Abrie Digital Filter Design Solutions, Jolyon M. De Freitas Discrete Oscillator Design Linear, Nonlinear, Transient, and Noise Domains, Randall W. Rhea Distortion in RF Power Amplifiers, Joel Vuolevi and Timo Rahkonen Distributed Power Amplifiers for RF and Microwave Communications, Narendra Kumar and Andrei Grebennikov Electric Circuits: A Primer, J. C. Olivier Electronics for Microwave Backhaul, Vittorio Camarchia, Roberto Quaglia, and Marco Pirola, editors EMPLAN: Electromagnetic Analysis of Printed Structures in Planarly Layered Media, Software and User’s Manual, Noyan Kinayman and M. I. Aksun

An Engineer’s Guide to Automated Testing of High-Speed Interfaces, Second Edition, José Moreira and Hubert Werkmann Envelope Tracking Power Amplifiers for Wireless Communications, Zhancang Wang Essentials of RF and Microwave Grounding, Eric Holzman Frequency Measurement Technology, Ignacio Llamas-Garro, Marcos Tavares de Melo, and Jung-Mu Kim FAST: Fast Amplifier Synthesis Tool—Software and User’s Guide, Dale D. Henkes Feedforward Linear Power Amplifiers, Nick Pothecary Filter Synthesis Using Genesys S/Filter, Randall W. Rhea Foundations of Oscillator Circuit Design, Guillermo Gonzalez Frequency Synthesizers: Concept to Product, Alexander Chenakin Fundamentals of Nonlinear Behavioral Modeling for RF and Microwave Design, John Wood and David E. Root, editors Generalized Filter Design by Computer Optimization, Djuradj Budimir Handbook of Dielectric and Thermal Properties of Materials at Microwave Frequencies, Vyacheslav V. Komarov Handbook of RF, Microwave, and Millimeter-Wave Components, Leonid A. Belov, Sergey M. Smolskiy, and Victor N. Kochemasov High-Efficiency Load Modulation Power Amplifiers for Wireless Communications, Zhancang Wang High-Linearity RF Amplifier Design, Peter B. Kenington High-Speed Circuit Board Signal Integrity, Second Edition, Stephen C. Thierauf

Integrated Microwave Front-Ends with Avionics Applications, Leo G. Maloratsky Intermodulation Distortion in Microwave and Wireless Circuits, José Carlos Pedro and Nuno Borges Carvalho Introduction to Modeling HBTs, Matthias Rudolph An Introduction to Packet Microwave Systems and Technologies, Paolo Volpato Introduction to RF Design Using EM Simulators, Hiroaki Kogure, Yoshie Kogure, and James C. Rautio Introduction to RF and Microwave Passive Components, Richard Wallace and Krister Andreasson Klystrons, Traveling Wave Tubes, Magnetrons, Crossed-Field Amplifiers, and Gyrotrons, A. S. Gilmour, Jr. Lumped Elements for RF and Microwave Circuits, Inder Bahl Lumped Element Quadrature Hybrids, David Andrews Microstrip Lines and Slotlines, Third Edition, Ramesh Garg, Inder Bahl, and Maurizio Bozzi Microwave Circuit Modeling Using Electromagnetic Field Simulation, Daniel G. Swanson, Jr. and Wolfgang J. R. Hoefer Microwave Component Mechanics, Harri Eskelinen and Pekka Eskelinen Microwave Differential Circuit Design Using Mixed-Mode S-Parameters, William R. Eisenstadt, Robert Stengel, and Bruce M. Thompson Microwave Engineers’ Handbook, Two Volumes, Theodore Saad, editor Microwave Filters, Impedance-Matching Networks, and Coupling Structures, George L. Matthaei, Leo Young, and E. M. T. Jones

Microwave Material Applications: Device Miniaturization and Integration, David B. Cruickshank Microwave Materials and Fabrication Techniques, Second Edition, Thomas S. Laverghetta Microwave Materials for Wireless Applications, David B. Cruickshank Microwave Mixer Technology and Applications, Bert Henderson and Edmar Camargo Microwave Mixers, Second Edition, Stephen A. Maas Microwave Network Design Using the Scattering Matrix, Janusz A. Dobrowolski Microwave Radio Transmission Design Guide, Second Edition, Trevor Manning Microwave and RF Semiconductor Control Device Modeling, Robert H. Caverly Microwave Transmission Line Circuits, William T. Joines, W. Devereux Palmer, and Jennifer T. Bernhard Microwaves and Wireless Simplified, Third Edition, Thomas S. Laverghetta Modern Microwave Circuits, Noyan Kinayman and M. I. Aksun Modern Microwave Measurements and Techniques, Second Edition, Thomas S. Laverghetta Modern RF and Microwave Filter Design, Protap Pramanick and Prakash Bhartia Neural Networks for RF and Microwave Design, Q. J. Zhang and K. C. Gupta Noise in Linear and Nonlinear Circuits, Stephen A. Maas Nonlinear Microwave and RF Circuits, Second Edition, Stephen A. Maas

On-Wafer Microwave Measurements and De-Embedding, Errikos Lourandakis Passive RF Component Technology: Materials, Techniques, and Applications, Guoan Wang and Bo Pan, editors Practical Analog and Digital Filter Design, Les Thede Practical Microstrip Design and Applications, Günter Kompa Practical Microwave Circuits, Stephen Maas Practical RF Circuit Design for Modern Wireless Systems, Volume I: Passive Circuits and Systems, Les Besser and Rowan Gilmore Practical RF Circuit Design for Modern Wireless Systems, Volume II: Active Circuits and Systems, Rowan Gilmore and Les Besser Production Testing of RF and System-on-a-Chip Devices for Wireless Communications, Keith B. Schaub and Joe Kelly Q Factor Measurements Using MATLAB , Darko Kajfez QMATCH: Lumped-Element Impedance Matching, Software and User’s Guide, Pieter L. D. Abrie Radio Frequency Integrated Circuit Design, Second Edition, John W. M. Rogers and Calvin Plett Reflectionless Filters, Matthew A. Morgan RF Bulk Acoustic Wave Filters for Communications, Ken-ya Hashimoto RF Design Guide: Systems, Circuits, and Equations, Peter Vizmuller RF Linear Accelerators for Medical and Industrial Applications, Samy Hanna RF Measurements of Die and Packages, Scott A. Wartenberg The RF and Microwave Circuit Design Handbook, Stephen A. Maas

RF and Microwave Coupled-Line Circuits, Rajesh Mongia, Inder Bahl, and Prakash Bhartia RF and Microwave Oscillator Design, Michal Odyniec, editor RF Power Amplifiers for Wireless Communications, Second Edition, Steve C. Cripps RF Systems, Components, and Circuits Handbook, Ferril A. Losee Scattering Parameters in RF and Microwave Circuit Analysis and Design, Janusz A. Dobrowolski The Six-Port Technique with Microwave and Wireless Applications, Fadhel M. Ghannouchi and Abbas Mohammadi Solid-State Microwave High-Power Amplifiers, Franco Sechi and Marina Bujatti Spin Transfer Torque Based Devices, Circuits, and Memory, Brajesh Kumar Kaushik and Shivam Verma Stability Analysis of Nonlinear Microwave Circuits, Almudena Suárez and Raymond Quéré Substrate Noise Coupling in Analog/RF Circuits, Stephane Bronckers, Geert Van der Plas, Gerd Vandersteen, and Yves Rolain System-in-Package RF Design and Applications, Michael P. Gaynor Technologies for RF Systems, Terry Edwards Terahertz Metrology, Mira Naftaly, editor TRAVIS 2.0: Transmission Line Visualization Software and User's Guide, Version 2.0, Robert G. Kaires and Barton T. Hickman Understanding Microwave Heating Cavities, Tse V. Chow Ting Chan and Howard C. Reader Understanding Quartz Crystals and Oscillators, Ramón M. Cerda Vertical GaN and SiC Power Devices, Kazuhiro Mochizuki

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