Topics in signal processing 9789811395314, 9789811395321

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Suhash Chandra Dutta Roy

Topics in Signal Processing Analog and Digital

Topics in Signal Processing

Suhash Chandra Dutta Roy

Topics in Signal Processing Analog and Digital

123

Suhash Chandra Dutta Roy Indian Institute of Technology Delhi New Delhi, Delhi, India

ISBN 978-981-13-9531-4 ISBN 978-981-13-9532-1 https://doi.org/10.1007/978-981-13-9532-1

(eBook)

© Springer Nature Singapore Pte Ltd. 2020 This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. The publisher, the authors and the editors are safe to assume that the advice and information in this book are believed to be true and accurate at the date of publication. Neither the publisher nor the authors or the editors give a warranty, expressed or implied, with respect to the material contained herein or for any errors or omissions that may have been made. The publisher remains neutral with regard to jurisdictional claims in published maps and institutional affiliations. This Springer imprint is published by the registered company Springer Nature Singapore Pte Ltd. The registered company address is: 152 Beach Road, #21-01/04 Gateway East, Singapore 189721, Singapore

Dedicated to my family, comprising Sudipta, my wife, Sumantra, my elder son, Sroddha, my elder daughter-in-law, Shoubhik, my younger son, Parul, my younger daughter-in-law, Soham, my elder grandson, and Malhar (Tutu), my younger grandson.

Acknowledgements

I owe so much to so many that it is not possible to acknowledge all of them in this limited space. To the ones whose credit I have not been able to mention, I ask for forgiveness. To the President of the IETE, Prof. (Dr.) K. T. V. Reddy, I am indebted for his enthusiasm and support. To the successive Publication Committee Chairpersons and Members of the Governing Council, I would like to say a big thank you for approving the proposal for writing this book. To Shrimati Sandeep Kaur Mangat, I would like to express my deep gratitude for successfully leading this project to a conclusion, with her immense patience and love and passion for work, much beyond her duty and for carrying out all the necessary hard work. To all the workers of the Publications Section and the Secretariat in general, I have no words to convey my heartfelt appreciation for their diligent work. To my students—particularly, the research students, I would like to express my love and best wishes for making me learn many things. In fact, I learnt more from them than they from me. Suhash Chandra Dutta Roy

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About This Book

This book, in common with my first book, is for you—students, teachers and researchers. I hope you would enjoy reading it. Starting from 1962, I have written and published a large number of articles in IETE Journals. At various points of time, starting from 1982, I have been requested by students,as well as teachers and researchers, to publish a book of collected reprints, appropriately edited and sequenced. Of late, this request has intensified, and the demand for reprints of some of the tutorial papers I wrote has increased considerably, not only from India, but also from abroad, because of my five video courses related to Circuits, Systems and Signal Processing (CSSP) successfully uploaded by NPTEL on YouTube. I thought it would be a good idea to venture into such a project at this time. This is the reason for my first book, Circuits, Systems and Signal Processing, published by Springer in 2018. Its performance encouraged me to venture into working on a second book, entitled Topics in Signal Processing, and I am glad that Springer has agreed to publish this book also. As in the first book, this also is a book for you, students, teachers and researchers in the subject Signal Processing. It is a collection of research papers published by me in collaboration with some of my colleagues and students in IETE Journals, duly edited and sequenced by me. As you would notice, I have written this book also in a conversational style to make you feel at ease while reading it. The contents of the book are divided into five parts—Parts I–IV dealing with Analog Signal Processing and Part V dealing with Digital Signal Processing. There are a total of 28 chapters. For details, see Contents.

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About This Book

I hope students and teachers will benefit from the book. It is only then that I shall feel adequately rewarded. For any mistakes/confusions/clarifications, please feel free to contact me via email at [email protected]. I take such mails on top priority, I assure you. Happy learning! New Delhi, India

Suhash Chandra Dutta Roy

Contents

Part I

Analog Signal Processing: Signal Processing by Passive Networks 3 5

1

Finite Zero Butterworth and Chebyshev Filters . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2

Bandwidth Enhancement with the Asymmetrical Bridged T-coil Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Analysis of the General BTC . . . . . . . . . . . . . . . . . . 2.3 Symmetrical BTC . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 BWER of the Asymmetrical BTC . . . . . . . . . . . . . . 2.5 Technology Simulation Results . . . . . . . . . . . . . . . . 2.6 Concluding Discussion . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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7 7 9 12 13 16 16 17

Multiple Frequency Impedance Matching by Frequency Transformation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 The Basic Network . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Impedance Matching at a Single Frequency . . . . . . 3.4 Application of Frequency Transformation . . . . . . . . 3.5 Dual-Frequency Impedance Matching . . . . . . . . . . . 3.6 Triple-Frequency Impedance Matching . . . . . . . . . . 3.7 Impedance Matching at Four Frequencies . . . . . . . . 3.8 Impedance Matching at Five Frequencies . . . . . . . . 3.9 Summary of the Procedure . . . . . . . . . . . . . . . . . . 3.10 Concluding Discussion . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Triple Frequency Impedance Matching by Frequency Transformation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 General Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.1 Basic L-Network for Impedance Matching 4.2.2 Single-Frequency Matching . . . . . . . . . . . 4.2.3 Application of Frequency Transformation . 4.3 Triple Frequency Matching Network . . . . . . . . . . . 4.4 Alternative Circuits for Triple Frequency Matching . 4.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Part II 5

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Analog Signal Processing: Signal Processing by Distributed Networks

Application of Topological Formulas to Distributed Parameter Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Topological Formulas . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 Formulas for Ladder Networks and Extension to Non-uniform Transmission Lines . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6

On Equivalent Representation of Lossy Transmission Lines . 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 Derivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.1 Two-Port Equivalence . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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45 45 46 47 48

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Efficient Approximation of Variable Delay Using Tapped Delay Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 Derivation of Formulas for the Weighting Coefficients 7.2.1 Recursive Formula . . . . . . . . . . . . . . . . . . . 7.2.2 Explicit Formula . . . . . . . . . . . . . . . . . . . . . 7.3 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Part III 8

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Analog Signal Processing: Signal Processing by Active Networks

Second-Order Active RC Filters Using a Single Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2 Basic Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3 Low-Pass Realization . . . . . . . . . . . . . . . . . . . . . . . . . 8.4 Bandpass Filter Realizations . . . . . . . . . . . . . . . . . . . . 8.4.1 First Bandpass Realization . . . . . . . . . . . . . . 8.4.2 Second Bandpass Realization . . . . . . . . . . . . 8.5 High-Pass Realization . . . . . . . . . . . . . . . . . . . . . . . . . 8.6 Band Stop Realization . . . . . . . . . . . . . . . . . . . . . . . . . 8.6.1 Second Band Stop Realization . . . . . . . . . . . . 8.6.2 Third Band Stop Realization . . . . . . . . . . . . . 8.7 Economic Aspect of Filter Realizations . . . . . . . . . . . . 8.8 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Tolerance Minded Design of Active RC Bandpass Filters . 9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2 Butterworth Approximation . . . . . . . . . . . . . . . . . . . 9.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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10 Active RC Filters Using a Single Differential Input Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2 The New Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3 Two Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4 A Comparison of the Two Methods . . . . . . . . . . . . . . . . . . 10.5 An Illustration of the Flexibility of the New Method . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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79 79 80 82 83 84 86

11 Second-Order Active RC Bandpass Filters Using Operational Amplifier in Low-Gain Connection . . . . . . . . . . . . . . . . . . . . . 11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 The Circuit Configuration . . . . . . . . . . . . . . . . . . . . . . . 11.3 Sensitivity Considerations . . . . . . . . . . . . . . . . . . . . . . . 11.4 Design Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4.1 Case A: Unity Gain Configuration . . . . . . . . . . 11.4.2 Case B: General K Configuration . . . . . . . . . .

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11.5

Frequency Limitation . . . . . . . . . . . . . . . . . . . . . . 11.5.1 Case A: OA in Unity Gain Configuration . 11.5.2 Case B: OA in Gain = 2 Configuration . . 11.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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97 97 98 100 101 101 103 103 105 106

12 Some Recent Contributions to Inductor Simulation and Applications to Low-Sensitivity Biquad Design . . . . . . . . 12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2 Gyrator Based Methods . . . . . . . . . . . . . . . . . . . . . . . . . 12.3 General Characteristics of Lossy, Grounded L Simulators 12.4 Simple Circuits for Lossy Grounded Inductance . . . . . . . 12.4.1 Four-Component Circuits . . . . . . . . . . . . . . . . 12.4.2 Five-Component Circuit . . . . . . . . . . . . . . . . . 12.4.3 Circuits Using Six Components . . . . . . . . . . . . 12.4.4 Comments . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5 Lossy Floating Inductance Simulation . . . . . . . . . . . . . . 12.6 Applications of Simulated L in the Design of Insensitive Biquadratic Sections . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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13 Evaluating the Frequency Limitations of Operational Amplifier RC Networks by the Dominant-Pole Technique . 13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2 Dominant-Pole Technique . . . . . . . . . . . . . . . . . . . . . 13.3 Frequency Limitations of Lossy Grounded Inductance Simulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4 Experimental Investigations . . . . . . . . . . . . . . . . . . . . 13.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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14 ‘Shadow’ Filters—A New Family of Electronically Tunable Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2 Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3 Special Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.4 Range of Variation . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5 An Open Problem and a Suggestion . . . . . . . . . . . . . . 14.6 An Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Contents

Part IV

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Analog Signal Processing: Signal Processing by Discrete Time Networks

15 Some 15.1 15.2 15.3 15.4

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Processing Applications of Charge-Coupled Devices . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Physics of Charge-Coupled Devices . . . . . . . . . . . . . . . The Input and Output Schemes . . . . . . . . . . . . . . . . . . 16.3.1 Input Circuit . . . . . . . . . . . . . . . . . . . . . . . . . 16.3.2 Output Circuit . . . . . . . . . . . . . . . . . . . . . . . Characterization, Measurement and Compensation of Charge-Transfer Inefficiency . . . . . . . . . . . . . . . . . . CCD Transversal Filters . . . . . . . . . . . . . . . . . . . . . . . 16.5.1 Limitations of This Technique . . . . . . . . . . . . 16.5.2 CCD Low-Pass Filters . . . . . . . . . . . . . . . . . 16.5.3 Bandpass Filters . . . . . . . . . . . . . . . . . . . . . . 16.5.4 Matched Filtering . . . . . . . . . . . . . . . . . . . . . 16.5.5 Hilbert Transformer . . . . . . . . . . . . . . . . . . . 16.5.6 Adaptive Filtering . . . . . . . . . . . . . . . . . . . . . 16.5.7 Complex Coding . . . . . . . . . . . . . . . . . . . . . 16.5.8 Interference Rejection Filter Using CCDs . . . . 16.5.9 Linear Regression Analysis Using CCDs . . . . 16.5.10 Radar Display System Using CCDs for Time Expansion . . . . . . . . . . . . . . . . . . . . . . . . . .

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Aspects of Digital and CTD Signal Processing . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Our Early Work in Digital Signal Processing . . . . . . . Linear-Phase Recursive Filters . . . . . . . . . . . . . . . . . . Discrete Hilbert Transform and Its Applications in Digital Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . 15.5 Roundoff Noise in Digital Filters . . . . . . . . . . . . . . . . 15.6 Quantized Coefficent Design of Digital Filters . . . . . . 15.7 Variable IIR Digital Filters . . . . . . . . . . . . . . . . . . . . 15.8 Variable FIR Digital Filters . . . . . . . . . . . . . . . . . . . . 15.9 Nested Structures for FIR Filters . . . . . . . . . . . . . . . . 15.10 Fourier Transform at Arbitrary Frequencies . . . . . . . . 15.11 Inefficiency Compensation in CTD Delays and Signal Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.12 CTD Linear Phase Versus Minimum Phase Design . . . 15.13 Coefficient Sensitivity in CTD Filters . . . . . . . . . . . . . 15.14 Spectrum Analysis by CTD . . . . . . . . . . . . . . . . . . . . 15.15 Looking Ahead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

16 Signal 16.1 16.2 16.3

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16.5.11 Waveform Generation Using CCDs . . . . . . . . . . . 16.5.12 Cost and Performance Trade-Offs in Various Approaches to Signal Processing . . . . . . . . . . . . . 16.6 Spectral Analysis Using CCDs . . . . . . . . . . . . . . . . . . . . . . 16.7 MTI Radar and Television Ghost Suppression Applications . 16.7.1 Simple Cancelling Filter . . . . . . . . . . . . . . . . . . . 16.7.2 Application to Practical MTI Filters . . . . . . . . . . . 16.7.3 Processor for Pulse-Doppler Radar . . . . . . . . . . . . 16.7.4 Charge-Transfer Memory for ECM . . . . . . . . . . . 16.7.5 Television Ghost Suppression Using CCD . . . . . . 16.8 Concluding Remarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Linear-Phase Versus Minimum-Phase CCD Transversal Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.2 Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.3 Results of Numerical Computations . . . . . . . . . . . . 17.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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19 Generalized Linear Phase Conditions for Causal FIR Systems Revisited . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.1.1 Basic Concepts . . . . . . . . . . . . . . . . . . . . . . . . . 19.1.2 Conditions for GLP and Proof of Sufficiency . . . 19.1.3 Necessary and Sufficient Conditions . . . . . . . . . . 19.2 Method 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.3 Method 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.4 Method 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.5 Method 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.6 Method 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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201 201 201 202 203 204 205 206 208 210

Part V

Digital Signal Processing

18 A State-of-the-Art Survey on Linear Phase Digital Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 18.2 The Problem of Linear Phase and FIR Design 18.3 Linear Phase IIR Design . . . . . . . . . . . . . . . . 18.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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19.7 Method 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 19.8 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 20 Review of Pseudo-Boolean Methods with Applications to Digital Filter Design . . . . . . . . . . . . . . . . . . . . . . . . 20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.2 Pseudo-Boolean Functions . . . . . . . . . . . . . . . . . 20.3 Linear PB Equations and Inequalities . . . . . . . . . 20.4 Nonlinear PB Equations and Inequalities . . . . . . 20.5 Minimization of PB Functions . . . . . . . . . . . . . . 20.6 Applications to Digital Filters . . . . . . . . . . . . . . 20.7 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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21 Maximally Linear FIR Digital Differentiators: A Review . . . 21.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.2 DDS for Low Frequencies: H1(x) . . . . . . . . . . . . . . . . . 21.2.1 Design for Approximation to H1(x) . . . . . . . . 21.2.2 Performance of H1(x) . . . . . . . . . . . . . . . . . . 21.3 DDS for Mid-band Frequencies with Zero Phase: H2(x) 21.3.1 Design for Approximation to H2(x) . . . . . . . . 21.3.2 Performance of H2(x) . . . . . . . . . . . . . . . . . . 21.4 DDS for Mid-band Frequencies with p/2 Phase: H3(x) . 21.4.1 Design for Approximation to H3(x) . . . . . . . . 21.4.2 Performance of H3(x) . . . . . . . . . . . . . . . . . . 21.5 DDS for High Frequencies: H4(x) . . . . . . . . . . . . . . . . 21.5.1 Design for Approximation to H4(x) . . . . . . . . 21.5.2 Performance of H4(x) . . . . . . . . . . . . . . . . . . 21.6 Variable Frequency DDS: Universal Differentiators . . . . 21.6.1 Design of Universal Digital Differentiators . . . 21.6.2 Performance of Universal Differentiators . . . . 21.7 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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229 229 231 231 234 234 235 236 236 239 241 243 243 244 244 246 248 250 250

....... ....... ....... Filters . . ....... ....... .......

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253 253 254 259 260 261 261

22 Design of Maximally Flat and Monotonic FIR Filters Using the Bernstein Polynomial . . . . . . . . . . . . . . . . . 22.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.2 Review . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.3 The Bernstein Polynomial and Design of Maxflat 22.4 Transformation Matrix . . . . . . . . . . . . . . . . . . . . 22.4.1 Coefficients ai’s . . . . . . . . . . . . . . . . . 22.4.2 Coefficients bi’s . . . . . . . . . . . . . . . . .

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22.5 22.6

Maxflat FIR Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . Monotonic FIR Filters . . . . . . . . . . . . . . . . . . . . . . . . . . 22.6.1 Monotonic Filters with Transition Width 2/N . . 22.6.2 Monotonic Filters with Transition Width 3/N . . 22.6.3 The New Method . . . . . . . . . . . . . . . . . . . . . . 22.6.4 Comparative Study . . . . . . . . . . . . . . . . . . . . . 22.7 Quadrature Mirror Filter . . . . . . . . . . . . . . . . . . . . . . . . 22.7.1 Design of MAXFLAT QMF . . . . . . . . . . . . . . 22.7.2 Monotonic QMF with Zero Reconstruction Error at the End and Mid Points . . . . . . . . . . . 22.7.3 Minimization of the Reconstruction Error at xm 22.8 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

23 On the Design of FIR Notch Filters . . . . 23.1 Introduction . . . . . . . . . . . . . . . . . 23.2 Design . . . . . . . . . . . . . . . . . . . . . 23.3 Design Examples and Performance . 23.3.1 Equiripple Design . . . . . . 23.4 Conclusion . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . .

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24 A Simple Solution for the Analytic Inversion of Van der Monde and Confluent Van der Monde Matrices . . . . 24.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.2 Inversion Formula for Van der Monde Matrix . . . . . 24.3 Inversion Formula for the Confluent Van der Monde Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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287 287 287 291 292 293 293

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25 A New Canonic Lattice Realization of Arbitrary FIR Transfer Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25.2 Derivation of the New Structure . . . . . . . . . . . . . . . . . . . . 25.3 Cases Requiring Modification of the Procedure . . . . . . . . . 25.4 Realization of a Single Transfer Function . . . . . . . . . . . . . 25.5 Limitations of the New Procedures . . . . . . . . . . . . . . . . . . 25.6 Concluding Comments . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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301 301 303 305 306 308 309 309

26 A Note on Canonic Lattice Realization Transfer Functions . . . . . . . . . . . . . . . 26.1 Introduction . . . . . . . . . . . . . . . 26.2 The New Procedure . . . . . . . . . . Reference . . . . . . . . . . . . . . . . . . . . . . .

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27 A New Canonic Lattice Realization of Arbitrary IIR Transfer Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27.2 Derivation of the New Structure . . . . . . . . . . . . . . . . . . . . 27.3 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27.4 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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315 315 316 318 321 321

28 A New Feedback Configuration for Canonical Realization of IIR Filters and Its Application to Lattice Realizations . 28.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.2 The Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.3 Applications to Canonical IIR Lattice Realizations . . 28.4 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Author and Contributors

About the Author Suhash Chandra Dutta Roy was fortunate enough to be educated at the Calcutta University, where great professors and researchers like C V Raman, S N Bose, M N Saha and S Radhakrishnan taught and made a name, globally, not only for them, but also for the university and the country. Immediately after my master's, I had to take up a job in a Government Research Institute. I soon discovered that many things are done at the Institute, but not research. I therefore quit and shifted to the newly established University of Kalyani as a lecturer. There I spent a few years, and after my Ph.D., I left the country to take up an Assistant Professorship at the University of Minnesota. A few years passed by, but I felt increasingly guilty that I was not doing anything for my motherland. I therefore returned to the country and joined IIT Delhi, as an Associate Professor where I served for more than four decades as Professor, Head of the Department and as a Dean. The last two positions were imposed upon me, and I suffered because they cut down on the time available for my research and interactions with my dear students. I formally retired at the age of 60, but continued to teach and carry out research, as an Emeritus Fellow, followed by INSA Senior Scientist and INSA Honorary Scientist. Later, when my term as an Emeritus Fellow was over, I did not take any money from IIT Delhi and served voluntarily, simply for the love of teaching and research. I finally left IIT Delhi

xxi

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Author and Contributors

permanently, 12 years after the retirement. I am now settled at Hauz Khas, New Delhi, where I live happily with my wife, but still continue to do research. We enjoy good health because of Yoga and strict diet. I have been extraordinarily lucky to have had gems of Ph.D. students, 30 of them, who have done exemplary work in research and innovation. Some of them have figured in ‘Contributors’. In fact, I feel myself shining with reflected glory. I have also been lucky to have received high recognition through Fellowship of IEEE, Distinguished Fellowship of IETE and Fellowship of all the relevant national academies. I have been awarded some prestigious national awards, including the Shanti Swarup Bhatnagar Prize. Over and above all the awards and recognitions, however, what I value most is the love and affection of my students. I now spend time giving professional lectures on innovations in teaching and research, in general, and also on how to improve their standards in the country. I have the hobby of listening to Hindustani classical music and researching on its maestros. I also love spending quality time with my grandson, Soham. Reading political history and detective stories are my other hobbies. I also read poetry and compose some poems and short stories, for my own pleasure. –In short, I have lived a complete life, with nothing to complain about.

Contributors1 Prof. Amalendu Bhushan Bhattacharyya did his M.Sc. (Physics) and Ph.D. from BHU, and was the Head of the Centre for Applied Research in Electronics (CARE) at IIT Delhi. I collaborated with him in the Analog Signal Processing Systems (ASPS) project of the Department of Electronics, Government of India. In this project, fabrication and applications of the charge-transfer device (CTD)—both bucket-brigade device (BBD) and charge-coupled device (CCD)—formed a major

I shall now introduce my co-authors in some of the papers on which the book is based. The first four were my colleagues in the Institute. The next eleven were my Ph.D. students, listed in alphabetical order. The last person listed here was my M.Tech. student.

1

Author and Contributors

xxiii

part. After retirement, he joined ITM Gurgaon, as Director. He then transferred to Goa University as Professor and Director, VLSI Design program, and finally to the JP University, Noida, as Emeritus Professor. He lives in Noida. Dr. Alladi Prabhakar was a colleague of mine in the Electrical Engineering Department (EED) of IIT Delhi. An IISc Ph.D. holder specializing in Graph Theory, he later transferred to ITI Bangalore, became its Managing Director, and is now settled at Bangalore after retirement. Prof. Surendra Prasad did his B.Tech. at IIT Kharagpur and M.Tech. and Ph.D. from IIT Delhi. After M.Tech., he joined CARE as a lecturer, and after Ph.D., he became an assistant professor in the EE Department, where he later became a professor. He also became a dean, Deputy Director (Faculty) and finally retired as Director. He is now Emeritus Professor at IITD. Prof. Prem Saran Satsangi was a dear colleague of mine at IITD. He did his bachelor’s degree from BHU, master’s from Michigan State University, East Lansing, USA, and Ph.D. from Waterloo at Canada. On return from Waterloo, he became an associate professor, and later a full professor. He occupied several important positions at IIT Delhi, including Head of the Department, Dean and Managing Director, FITT. Later, he took voluntary retirement to take up Directorship of the Dayalbagh Educational Institute (DEI), Agra, a deemed university. After retirement, he was elected to head the Satsang Community and is now the most respected Guruji Maharaj there. Prof. Juzer Vasi is a B.Tech. graduate from IIT Bombay and a Ph.D. holder from Harvard. He joined CARE at IIT Delhi as an assistant professor and transferred to IIT Bombay for family reasons. He established a state-of-the-art microelectronics facility at IITB. Now retired, he is settled at Mumbai. Monica Agrawal was jointly registered with me and Surendra Prasad for her Ph.D. After graduation, she worked with Hughes Software for a few years and then returned to IITD as an assistant professor in CARE. She is now a full professor there, doing important work in Underwater Signal Processing. Muslim Taj Ahmed was a B.Sc. (Engg) graduate from AMU, who also served as a lecturer there. Later, he came to IIT Delhi for his M.Tech., and seeing his extraordinary performance in course work, he was transferred to Ph.D. Program with me as the guide. After Ph.D., he went back to AMU, became an assistant professor and later a professor there. After a few years, he went to Dubai and Saudi Arabia with teaching assignments. After returning to AMU, he served the Zakir Hussain College of Engineering, as its Principal. Unfortunately, he died prematurely.

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Author and Contributors

Vuppuluri Gurusharan Das a B.Sc. (Engg) graduate from Dayalbagh Engineering College (DEI, then under Agra University) and an M.Tech. graduate from IIT Kanpur, came as a QIP candidate to IITD to work for his Ph.D. under my supervision. He was exceptionally brilliant and completed his research in record time. He worked on the CCD as part of the ASPS project. After completion, he went back to DEI, became a full professor there and finally DEI’s Director. After retirement, he rejoined DEI as Professor Emeritus and remained active in teaching and project supervision there. He passed away recently in May 2018. Shail Bala Jain did B.Sc. (Engg) from the Delhi College of Engineering (DCE) and M.Tech. from IITD. She was a faculty in DCE for many years. During this, she registered for Ph.D. at Delhi University with me as her guide and Prof. A. K. Sinha (DCE) and Balbir Kumar (DIT, now NSIT) as co-guides. She became a full professor at IGIT, GGSIP University, and later joined the Indira Gandhi Delhi Technical University for Women as an academic advisor. She is now leading a retired life. Navin Kapur did his B.Tech. at IIT Delhi and then took up a job in CDIL. After a few years, he came to me for Ph.D. I got him a research associateship in the ASPS project to work on CCDs. He did good work, got his Ph.D. and went back to CDIL. After retirement from there, he worked in a private institution as Professor and later became its Director. On superannuation from there, he settled at Delhi. He also passed away recently. Balbir Kumar did his B.E. from Punjab Engineering College (now a deemed university) and was commissioned in the Indian Navy. He came as a sponsored candidate from the Navy to do his M.Tech. at IITD. He worked for his M.Tech. thesis with me and then rejoined the Navy. After a few years, he took voluntary retirement and joined IITD for his Ph.D. He did excellent work on digital differentiators. After Ph.D., he joined the newly established Delhi Institute of Technology (now Netaji Subhas Institute of Technology [NSIT]) as an assistant professor and was promoted to full professorship after a few years. At NSIT, he also worked as an acting director for some time. After retirement, he worked in a private institution for some years. Unfortunately, like Ahmed and Das, he also died prematurely. Shailey Minocha registered for her Ph.D. with me when she was working on a project in CARE. She only had a bachelor’s degree from DCE, but with some course work, she did excellent research. After her Ph.D., she took up a job with TCS, which was followed by a postdoctoral fellowship at Technical University, Braunschweig, Germany. On completion of her fellowship, she moved to the UK and is now a full professor at UK’s Open University.

Author and Contributors

xxv

Rakesh Kumar Patney came to do his M.Tech. at IIT Delhi, after a B.Tech. from IIT Kanpur. He did his M.Tech. thesis with me and continued for his Ph.D. After graduation, he was inducted to the faculty. He recently retired as full Professor and is continuing at IIT Delhi as Emeritus Fellow. L. R. Rajagopal is a graduate of the National Defence Academy, Khadakwasla, Pune, and the Naval College of Engineering at Lonavala, Pune, and was sponsored by the Indian Navy to do his M.Tech. at IITD. He did his M.Tech. thesis with me and Rakesh. Then, he continued at IIT Delhi for his Ph.D. under my supervision. The use of Bernstein polynomials in DSP was his innovation, and the work is widely cited in the literature, even today. After Ph.D., he went back to the Navy and did commendable work in the WESEE project. After superannuation, he started his own industry at Chennai, named ‘Signals and Systems’, which is now well established and reputed for their high-quality power instruments. L. Shankaranarayanan came to work in the ASPS project after his M.Sc. (Physics) from Anna University. Shankar registered for his Ph.D. with Prof. Bhattacharyya and me. He later went to work with Philips and rose to the position of Research Director. I do not know his whereabouts at the present time. Mahesh Chandra Srivastava came to do his Ph.D. under the supervision of Prof. Satsangi and me. He was sponsored by the MMM Engineering College, Gorakhpur. After his Ph.D., he joined BIT Mesra, Ranchi. After a few years, he changed to KNIT Sultanpur and then served several institutions till he came to Jaypee Institute of Technology, Noida. That is what I last knew about him. Recently, I came to know that Mahesh is no more. Phani Bhushan Tholetti was an M.Tech. student. The paper in which he collaborated and contributed to the work in this book was done by him while taking my course on DSP. He is now working in industry at Bangalore.

Part I

Analog Signal Processing: Signal Processing by Passive Networks

This part contains 4 chapters. Chapter 1 deals with finite zero filters of the Butterworth and Chebyshev types. Chapter 2 contains one of my best works. I show that the bandwidth enhancement capability of the asymmetrical bridged T-coil, used as the inter-stage network, is virtually unlimited. This is something new and may open up new investigations, because it offers a technological challenge. Chapters 3 and 4 deal with multiple frequency impedance matching by using the frequency transformation techniques.

Chapter 1

Finite Zero Butterworth and Chebyshev Filters

Abstract An accurate expression is derived for the minimum order of a finite-zero Butterworth filter (Dutta Roy in IEEE Trans AU-19(1):58–63, 1971) [1], which has a steeper cut-off slope than the corresponding Chebyshev filter (Agarwal and Sedra in IEEE Trans AU-20(2):138–141, 1972) [2]. The inaccuracy occurring in the latter is illustrated by a numerical example. Keywords Finite-zero filters · Butterworth filters · Chebyshev filters · Cutoff slope This chapter is concerned with a comparison of the finite-zero, low-pass, Butterworth filter, defined by the magnitude squared function [1]: |Fmn ( jω)|2 =

1 1 + ω2n [(ω02 − 1)/(ω2 − ω02 )]2m

(1.1)

with the corresponding Chebyshev filter, defined similarly by [2]: |Tmn ( jω)|2 =

1 1 + ε2 Cn2 (ω)[(ω02 − 1)/(ω2 − ω02 )]2m

(1.2)

where, in either case, n denotes the order of the filter, m is the order of zeros at ±jω0 , ω0 > 1 and n ≥ 2 m +1. In Eq. (1.2), C n (ω) denotes the Chebyshev polynomial of the first kind, of order n, and ε2 is a ripple controlling factor. We define the cut-off slope in either case as the negative differential coefficient of the magnitude with respect to ω, evaluated at ω = 1, and denote it by S bmn in the Butterworth and S tmn in the Chebyshev case. Further, for the purpose of comparing the two cut-off slopes, we set ε2 = 1; then it can be shown that [1, 2]. √ Sbmn = [n/(2 2)]{1 + 2m/[n(ω02 − 1)]}

(1.3)

and Source: Suhash C. Dutta Roy, “Comparison of Finite Zero Butterworth and Chebyshev Filters,” JIETE, vol 21, p 350, June 1975. © Springer Nature Singapore Pte Ltd. 2020 S. C. Dutta Roy, Topics in Signal Processing, https://doi.org/10.1007/978-981-13-9532-1_1

3

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1 Finite Zero Filters

√ Stmn = [n 2 /(2 2)]{1 + 2m/[n 2 (ω02 − 1)]}

(1.4)

Let nB denote the minimum order of the modified Butterworth function in Eq. (1.1) with mB pairs of zeros at ±jω0 for which the cut off slope is steeper than that given by Eq. (1.4). Then from Eqs. (1.3) and (1.4), it follows that n B + {2m B /(ω02 − 1)} ≥ n 2 + {2m/(ω02 − 1)}

(1.5)

Note that if mB = m, then nB is simply equal to n2 . To allow the Butterworth function to have the highest possible slope, we set m B = (n B − r )/2

(1.6)

where, since mB is to be an integer,  r=

1, for odd n B 2, for even n B

(1.7a, b)

Substituting Eq. (1.6) into Eq. (1.5), we get n B ≥ (1/ω02 )[2m + r + n 2 (ω02 − 1)]

(1.8)

which, combined with Eq. (1.7a, b), gives  n B = Lower of

odd < (1/ω02 )[2m + 1 + n 2 (ω02 − 1)] > even < (1/ω02 )[2m + 2 + n 2 (ω02 − 1)] >

(1.9)

where the notation means the lowest integer greater than or equal to a. Agarwal et al. [2] have assumed Eq. (1.7a), without regard to the possibility of an even nB , and the resulting equation can be written in our notations as n B =

(1.10)

As an example of the inaccuracy of Eq. (1.10), let n = 5, m = 2 and ω0 = 2.0; then Eq. (1.10) gives nB = 20 and according to Eqs. (1.6) and (1.7a), mB = 9.5. Since mB has to be an integer and mB = 10 is not allowed, the highest possible value of mB is 9. Under these conditions, the left-hand side of inequality (1.5) becomes 26 while the right-hand side becomes 26.33. In the above situation, Eq. (1.9), on the other hand, gives nB = lower of {odd ; even } = 21 and from Eqs. (1.6) and (1.7a), one obtains, mB = 10. With these values, the left-hand side of inequality (1.5) is 27.67 which is greater than 26.33, the value of the right-hand side.

1 Finite Zero Filters

5

As another example of the √ application of Eq. (1.9), let n = 5 and m = 2, as in the previous case, but ω0 = 6. Then Eq. (1.9) gives nB = lower of {odd ; even } = 22 and hence mB = 10. It may now be verified that these satisfy the inequality (1.5).

References 1. S.C. Dutta Roy, On maximally flat sharp cut-off low-pass filters. IEEE Trans. AU-19(1), 58–63 (1971) 2. M.C. Agarwal, A.S. Sedra, On designing sharp cutoff low-pass filters. IEEE Trans. AU-20(2), 138–141 (1972)

Chapter 2

Bandwidth Enhancement with the Asymmetrical Bridged T-coil Network

Abstract This chapter presents the results of a theoretical investigation of the asymmetrical bridged T-coil (BTC) bandwidth enhancement network under the condition of maximally flat magnitude (MFM) response. Conventionally, the BTC is used in the symmetrical configuration and it is well known that, as compared to the commonly used RC load, the√maximum bandwidth enhancement ratio (BWER) under the MFM condition is 2 2. It is shown here that by introducing asymmetry, even under the constraint of MFM response, the maximum achievable BWER is theoretically unlimited, the limit being set only by practical considerations. Unlimited BWER has never been considered possible, even theoretically, with BTC or any other network, and the result reported here is believed to be a breakthrough in the design of wide-band and ultra wide-band amplifiers. Simulations for a few designs indicate that practical realization of the full potential of the asymmetrical BTC may have to wait for improved technologies which facilitate tight coupling between the two parts of the coil and also minimize parasitic effects. Keywords Bandwidth enhancement · Bridged T-coil · Maximally flat magnitude · Wide-band amplifiers

2.1 Introduction Considerable interest has been shown in the analysis, design, and applications of the bridged T-coil (BTC) network during the past three decades [1–30]. While major application of the BTC is in wide-band amplifiers [1–25], several recent papers relate to its application in replacing transmission line sections required in ultra wideband power dividers and bandpass filters, thereby significantly reducing the circuit size without affecting the performance [26–28]. This equivalence was first proposed in [29] for modelling low-temperature co-fired ceramic embedded inductors. Yet another very recent application of the BTC has been reported in [30] in the design of all-pass networks and phase-shifters. Source: Suhash C. Dutta Roy, “A Theoretical Investigation into the limits of Bandwidth Enhancement with the Asymmetrical Bridged T-Coil Network,” IETE Journal of Research, vol 62, pp 379–386, May–June 2016. © Springer Nature Singapore Pte Ltd. 2020 S. C. Dutta Roy, Topics in Signal Processing, https://doi.org/10.1007/978-981-13-9532-1_2

7

8

2 Asymmetrical BTC

This chapter will focus on the application of the BTC in wide-band amplifier design only, a typical stage of which is shown in Fig. 2.1, where the active device is an NMOS transistor. As mentioned in [13] and [16], the BTC has been used for about four decades by Tektronix Inc. in oscilloscope circuitry, but its design remained a trade secret for a long time. A US patent on a bridged T-termination network, which can be considered as a lossy BTC was granted as early as 1964 [31], but the first public disclosure of analysis and design of the BTC appeared in 1982 [1] (not 2004 [13], as mentioned in [16]). Most of the contributions reported so far used the symmetrical form of the BTC, and it has been well established that under the maximally flat magnitude (MFM) condition, the maximum bandwidth √ enhancement ratio (BWER), as compared to the commonly used RC load, is 2 2. Asymmetrical BTC was considered in [6, 7, 9] and [14]. In [6] as well as [9], the maximum BWER achieved was the same as that of the symmetrical BTC under the MFM condition. It was mentioned in [7] that the BWER considerably exceeded the conventional limit but no theoretical analysis or the condition (MFM or otherwise) under which the same was achieved was given. There are indications in [14] of achieving, with an asymmetrical BTC, a BWER greater than 4 with zero-dB ripple; however, zero-dB ripple does not necessarily mean the MFM condition, and no theoretical analysis was provided. If ripples are allowed, [14] shows that the BWER can even exceed 5. It is worth mentioning here that in [32], published as early as 1954, the circuits labelled D are asymmetrical BTCs; again, there was no theoretical analysis, but the plots of gain frequency characteristics given in Fig. 2.2 of that paper indicated a BWER much in √ excess of 2 2. A comprehensive theoretical investigation of the general asymmetrical BTC is carried out in this chapter, and it is shown that even under the MFM constraint, the BWER achievable by this network is theoretically unlimited, the realizable limit being set only by practical considerations. This result is believed to be a breakthrough in the design of wide-band and ultra wide-band amplifiers. Some of the theoretical designs were simulated using models of 130 nm technology, which show that parasitic effects severely limit the bandwidth enhancement, and lead to the conclusion that improved technologies, which allow tight coupling Fig. 2.1 A common source NMOS amplifier stage with a bridged T-coil network in the drain circuit

RT Lb CC

+ V1

M

La

+ CL V o

2.1 Introduction

9

Fig. 2.2 Small-signal equivalent circuit of Fig. 2.1, where L 1 = L a + M, L 2 = L b + M, and L 3 = −M

CC L1

L2 L3

I1 = gmV1

RT +

CL

Vo

between the two parts of the asymmetrical BTC, and also minimize the parasitic effects, will be needed to realize the full potentials of the BTC. The chapter is organized as follows. In the next section, we give the equivalent circuit of Fig. 2.1 and the expression for its transfer impedance, which is of order 4. This transfer function is then reduced to one of order 2 by following [16] and the conditions under which this can be done are stated. Section 2.3 deals with the application of these results to a symmetrical BTC, where a misconception in the existing literature [13] is cleared. Section 2.4 contains the details of derivation needed to find the BWER of the asymmetrical BTC under the MFM constraint, and establishes the fact that in theory, the BWER can be infinitely large. A plot of BWER versus the coefficient of coupling is given and some specific designs are given in the form of a table. Section 2.5 comments on the results of simulation of a few designs while Sect. 2.6 contains the concluding discussions.

2.2 Analysis of the General BTC The small-signal equivalent circuit of Fig. 2.1 is shown in Fig. 2.2, where gm is the transconductance of the NMOS transistor. In [16], this circuit was analysed by using the extra-element theorem [33] whereas in [17], a much simpler analysis was carried out by using classical techniques. In either case, the result obtained is the following: Z T = V0 /Ii = RT N (s)/D(s) N (s) = s 2 Cc (L a + L b + 2M) + s((L b + M)/RT ) + 1 D(s) = s 4 Cc C L (L a L b − M 2 ) + s 3 Cc C L RT (L a + L b + 2M) + s 2 (Cc (L a + L b + 2M) + C L L b ) + sC L RT + 1.

(2.1)

The transfer impedance Z T is of the fourth order, and it is difficult to proceed further analytically. Following [16], we, therefore, convert it to a second-order one by forcing pole-zero cancellation, i.e. we write

10

2 Asymmetrical BTC

D(s) = ( ps 2 + qs + 1)N (s)

(2.2)

and determine the constraints on the element values by equating the coefficients of powers of s on both sides. Carrying out these steps, we get [16] p = C L (L a L b − M 2 )/(L a + L b + 2M),

(2.3)

C L (L a L b − M 2 )(L b + M) , Cc RT (L a + L b + 2M)2

(2.4)

q = C L RT −

q(L b + M) + p = CL Lb, RT

(2.5)

and q = C L RT −

Lb + M . RT

(2.6)

Comparing Eqs. (2.4) and (2.6) gives Cc La Lb − M2 = . CL (L a + L b + 2M)2

(2.7)

Also, by substituting Eqs. (2.3) and (2.6) in Eq. (2.5) and carrying out some algebraic simplifications, we obtain C L RT2 =

(L b + M)(L a + L b + 2M) . La + M

(2.8)

Let L a = L, L b = bL, and M = mL; then the coefficient of coupling between the two inductors in Fig. 2.1 is given by m M =√ 1/2 (L a L b ) b

(2.9)

C L RT2 (1 + m) (b + m)(1 + b + 2m)

(2.10)

k= Also, Eq. (2.8) gives L= and Eq. (2.7) gives

Cc b − m2 = . CL (1 + b + 2m)2

(2.11)

2.2 Analysis of the General BTC

11

When L and C c obey Eqs. (2.10) and (2.11), respectively, Z T /RT becomes a second-order function of the form 1 ZT = 2 , RT ps + qs + 1

(2.12)

where p=

(b + m)L LC L (b − m 2 ) . and q = C L RT − 1 + b + 2m RT

(2.13)

Equation (2.12) can be recast in the standard form Z T /RT = ω02 /(s 2 + 2ς ω0 s + ω02 ).

(2.14)

Comparing Eqs. (2.12) and (2.14) and using Eqs. (2.10), (2.11), and (2.13), we get, after simplification, 1 + b + 2m 1 ω0 = √ = p C L RT



b+m (1 + m)(b − m 2 )

(2.15)

and  q 2ς = = pω0

(b + m)3 . (1 + m)(b − m 2 )

(2.16)

As is well known has MFM response √ [34], the transfer function given by Eq. (2.14) √ when ς = 1/ 2 (critically damped case). For 0 < ς < 1/ 2 (underdamped 2 1/2 case), the magnitude response exhibits a peak √ of value 1/[2ς (1 − ς ) ] at the 2 1/2 frequency ω0 (1 − 2ς ) . When ς = 1/ 2 (overdamped case), the magnitude response decays monotonically. Typical plots of the magnitude of Eq. (2.14) for underdamped, critically damped and overdamped cases are shown in Fig. 2.3. The 3-dB bandwidth of Eq. (2.14) is given by   ω3 = ω0 (1 − 2ς 2 ) + (1 − 2ς 2 )2 + 1

(2.17)

The 3-dB bandwidth of the amplifier with the commonly employed RT C L load is given by 1/(RT C L ). Hence, the BWER with the BTC load is given by η = ω3 RT C L

(2.18)

12

2 Asymmetrical BTC 1.2

Fig. 2.3 Frequency response of (2.14) for ς = 0.5 (underdamped), 0.707 (critically damped), and 1 (overdamped)

1.1 1.0 0.9

z = 0.707 z = 0.5

0.8

|ZT /RT | 0.7

z =1

0.6 0.5 0.4 0.3 0.2 0

0.2 0.4 0.6 0.8

1

1.2 1.4 1.6 1.8

2

(w/w 0)

2.3 Symmetrical BTC For the symmetrical BTC, b = 1, and Eqs. (2.15) and (2.16) simplify to the following: ω3 =

2 C L RT



1+m 1−m

(2.19)

and  2ς =

1+m 1−m

(2.20)

With b = 1, Eq. (2.9) gives k = m, and from Eq. (2.20), we get k=

4ς 2 − 1 4ς 2 + 1

(2.21)

Putting b = 1 in Eqs. (2.10) and (2.11), and using Eq. (2.21), we get L=

  1 C L RT2 1 + 2 and Cc = C L /(16ς 2 ). 4 4ς

(2.22)

These results agree with those derived by many authors earlier. Now combine Eqs. (2.18) with (2.17) and then use Eqs. (2.19)–(2.21), along with the fact that k = m. The result is   η = 4ς (1 − 2ς 2 ) + (1 − 2ς 2 )2 + 1 (2.23) Equation (2.17) shows√that as ς increases from 0 to 1, ω3 decreases monotonically √ √ from ( 2 + 1)1/2 ω0 to ( 2 − 1)1/2 ω0 , passing through the value ω0 at ς = 1/ 2.

2.3 Symmetrical BTC

13

In Eq. (2.23), however, because of the factor ς , the BWER will √ show a maximum at some value of ς , and it is not difficult to show that ς = 1/ 2 is this value. Thus, the condition for MFM response is also the condition for maximum BWER. Except for [25], this fact has not been explicitly √ mentioned in the literature. The maximum η is calculated from Eq. (2.23) as 2 2. Lee [13] mentions that a bandwidth greater than ω0 and a value of η almost equal to 3 are possible to be achieved by using ς = 0.7507. However, the analysis given here does not corroborate √ this assertion. In fact, for ς = 0.7507, 2, as expected, because η is a maximum Eq. (2.23) gives η = 2.8184, less than 2 √ when ς = 1/ 2.

2.4 BWER of the Asymmetrical BTC For a general transfer function of the form of Eq. (2.14), combining Eqs. (2.17) and (2.18) with Eq. (2.15), we get the following expression for the BWER of the asymmetrical BTC:  η = (1 + b + 2m)

b+m × (1 + m)(b − m 2 )

 (1 − 2ς 2 ) +



(1 − 2ς 2 )2 + 1 (2.24)

√ For MFM, ς = 1/ 2 and Eq. (2.24) becomes  η = (1 + b + 2m)

b+m (1 + m)(b − m 2 )

 21

.

(2.25)

√ Further, putting ς = 1/ 2, we get 2=

(b + m)3 . (1 + m)(b + m 2 )

(2.26)

Thus for MFM response, b and m have to satisfy Eq. (2.26) and for any such set, η is given by Eq. (2.25). Combining Eqs. (2.25) with (2.26), the expression for η gets further simplified to the following: η=

√

  1+m 2 1+ b+m

(2.27)

It is difficult to find, analytically, the variation of b with m from Eq. (2.26) or that of η with m from Eq. (2.27). One way is to simplify Eq. (2.26) to get a cubic equation in b and to solve it; however, as is well known [35, 36], an explicit expression for b in terms of m cannot be written and one has to take recourse to numerical computations. An alternative, and a simpler way, is to introduce the variable β = b/m; which converts

14

2 Asymmetrical BTC

Eq. (2.26) to the following quadratic equation in m: ((β + 1)3 + 2)m 2 + 2(1 − β)m − 2β = 0

(2.28)

The solution of Eq. (2.28) is m=

(β − 1) ±

 (β − 1)2 + 2β((β + 1)3 + 2) (β + 1)3 + 2

(2.29)

The sign in Eq. (2.29) is dictated by the fact that b has to be positive. Thus if β is taken as positive, then m has to be positive; hence only the positive sign in Eq. (2.29) is acceptable. A discussion on the possible range of values of m and b is in order at this point. Figures 2.1 and 2.2 show that m has been assumed to be positive, i.e. the coupling between L a and L b is negative. Can m be negative, i.e. is it possible to achieve a BWER > 1 with positive coupling? This question has been answered in the negative in the past, see e.g. [14] and [21]. Note that m = 0 means that there is no coupling between the two coils and the advantages of using the BTC are lost. Also, from Eq. (2.26), m is calculated as 1/3 when b = 1, which corresponds to the symmetrical case. Hence the range of m to be considered is 0 < m < 1/3. The range of b is of course √ 0 < b < 1. What about b > 1? Computation shows that b > 1 leads to BWER < 2 2. These points need to be kept in mind in interpreting Eqs. (2.28) and (2.29). We computed the values of m for about two decades of values √ of β, and also the corresponding values of b, the coupling coefficient k = m/ b, and the BWER η. The results are given in Table 2.1 along with the design values of the normalized inductance L/(C L RT2 ) calculated from Eq. (2.10) and the capacitance ratio C C /C L calculated from Eq. (2.11). The variation of η with k is shown in Fig. 2.4. Table 2.1 Some specific designs for the asymmetrical BTC √ β m β k = m/ b η 0.396 ×

L/(C L RT2 )

C c /C L

72.825

48.544

0.366 × 10–5

0.02

0.198 ×

0.04

0.392 × 10–1

0.157 × 10–2

0.990

37.463

23.585

0.269 × 10–4

0.06

0.581 ×

10–1

0.349 ×

10–2

0.984

25.710

15.367

0.880 × 10–4

0.10

0.946 ×

10–1

0.946 ×

10–2

0.973

16.296

8.776

0.355 × 10–3

0.20

0.177

0.354 × 10–1

0.941

9.251

3.988

0.211 × 10–2

0.40

0.303

0.121

0.871

5.758

1.778

0.985 × 10–2

0.60

0.383

0.230

0.799

4.606

1.131

0.208 × 10–1

1.00

0.447

0.447

0.669

3.702

0.691

0.451 × 10–1

2.00

0.408

0.815

0.451

3.042

0.438

0.937 × 10–1

3.00

0.333

1.000

0.333

2.828

0.375

0.125

10–1

10–3

0.995

2.4 BWER of the Asymmetrical BTC Fig. 2.4 Plot of BWER (η) versus coefficient of coupling (k)

15 102

h 101

100

0.4

0.5

0.6

0.7

0.8

0.9

1

k

The results for η in Table 2.1 and Fig. 2.4 are truly amazing, because they show that the BWER achievable by the asymmetrical BTC is theoretically unlimited, the realizable limit being set only by practical limitations of tight coupling and large inductance and capacitance spreads needed for large η. Parasitics will also play a major negative role, as discussed under Sect. 2.5. The capability of unlimited BWER can also be justified from the expression (2.27), which can be rewritten in terms of β and m as follows: η=

  √ 1 + (1/m) 2 1+ 1+β

(2.30)

This clearly shows that η → ∞ when m → 0. The values of the intermediate variable β are retained in Table 2.1 so as to facilitate the design for any value of η which lies in between two successive entries. Note that the last row in the table corresponds to the symmetrical BTC. In order to display the possibility of achieving large BWERs with the asymmetrical BTC, we have calculated, for typical values of RT and C L , the element values corresponding to the fifth row in Table 2.1, along with those for the commonly used RT C L load and the case of symmetrical BTC corresponding to the last row in Table 2.1. These are given below. Design A with simple RT C L load: RT = 50  and C L = 5 pF. Design B with symmetrical BTC (b = 1): RT = 50 , C L = 5 pF, L a = L b = 4.688 nH, and C C = 0.625 pF. Design C with asymmetrical BTC (b = 0.0354): RT = 50 , C L = 5 pF, L a = 49.85 nH, L b = 1.765 nH, and C c = 0.01055 pf. The corresponding expected values of the −3 dB frequencies are 0.6366, 1.8002, and 5.889 GHz, respectively. These designs were simulated with P Spice and the

16

2 Asymmetrical BTC 750 0.00 Plot C

-750 -15.00 -22.50

Plot A

Plot B

Vo I1 RT

-30.00 0.00G

1G

1G

Frequency(Hz) Fig. 2.5 Frequency response for designs A, B, and C obtained by P Spice simulation

resulting magnitude responses are shown in Fig. 2.5. These results agree with the expected ones, thus validating the theoretical investigations reported in this chapter.

2.5 Technology Simulation Results Using Agilent’s Advanced Design System tools with models of United Microelectronics 130 nm (1P8M) technology, simulation studies were carried out for a few specific designs of Table 2.1 with RT = 50  and C L = 5 pF. The results of simulation are rather disappointing and indicate that parasitics cause appreciable deviations from the ideal characteristics and that the distortions increase with increasing coefficient of coupling. Simulations with only the device parasitics indicate that the BTC parasitics have dominant effect on the deviations from maximal flatness and reduction of the BWER. Realizing the full potential of the theoretical results derived here will therefore have to wait for improved technologies for inductor fabrication in future.

2.6 Concluding Discussion A comprehensive theoretical analysis has been carried out in this chapter of the general asymmetrical BTC network used as the load of a wide-band amplifier, and it has been shown that the BWER achievable is unlimited, the limit being set only by practical considerations of tight coupling, large spreads in inductance and capacitance values, and of course, parasitics. Unlimited bandwidth has never been reported earlier, by either the BTC or any other network, and it is believed that the results of this chapter will set a new trend in the design of wide-band and ultra wide-band amplifiers.

2.6 Concluding Discussion

17

Simulation results indicate that the realization of the full potential of the asymmetrical BTC in wide-band amplifiers will have to wait for substantial improvements in the technology of inductance fabrication. Acknowledgements This work was supported by the Indian National Science Academy through the Honorary Scientist scheme. The author is thankful to Y. V. Joshi, S. K. Koul, R. Bhattacharya, and G. Chowdary for their help in preparing the manuscript.

References 1. P. Staric, An analysis of the tapped coil peaking circuit for wideband/-pulse amplifiers. Elektrotehniski Vestnik. 49, 66–79 (1982) 2. P. Staric, Three and four pole tapped coil circuits for wideband/-pulse amplifiers. Elektrotehniski Vestnik. 50, 129–137 (1983) 3. E.M. Chase, W. Kennan, A power distributed amplifier with constant-R network, in Proceedings of the IEEE GaAs IC Symposium, Genelefe, FL (1986), pp. 13–17 4. C. Hutchinson, W. Kennan, A low noise distributed amplifier with gain control, in Proceedings of the IEEE GaAs IC Symposium, Anaheim, CA (1987), pp. 119–122 5. D.L. Feucht, Handbook of Analog Circuit Design (Academic Press, San Diego, CA, 1990) 6. L. Selmi, D.B. Estreich, B. Ricco, Small-signal MMIC amplifier with bridged T-coil matching networks. IEEE J. Solid State Circuits 7, 1093–1096 (1992) 7. J. Kim, J.-K. Kim, B.-J. Lee, M. S. Huang, H.-R. Lee, S.-H. Lee, N. Kim, D.-K. Jeong, W. Kim, Circuit techniques for a 40 Gb/s transmitter in 0.13 µm CMOS, in Proceedings of the IEEE International Solid-State Circuits Conference, San Francisco, CA (2005), pp. 150–151 8. S. Galal, B. Razavi, Broadband ESD protection circuits in CMOS technology, in Proceedings of the IEEE International Solid-State Circuits Conference, San Francisco, CA (2003), pp. 182–183 9. T. Toifl, M. Kossel, C. Menolfi, T. Morf, M. Schmatz, A 23 GHz differential amplifier with monolithically integrated T-coil in 0.09 µm CMOS technology, in IEEE Microwave Theory and Techniques Society Symposium, Philadelphia, PA (2003), pp. 239–242 10. S. Galal, B. Razavi, 10 Gb/s limiting amplifier and laser modulation driver in 0.18 µm CMOS technology. IEEE J. Solid State Circuits 38, 2334–2339 (2003) 11. S. Galal, B. Razavi, Broadband ESD protection circuits in 0.18 mm CMOS technology. IEEE J. Solid State Circuits 38, 2138–2146 (2003) 12. S. Galal, B. Razavi, 40 Gb/s amplifier and ESD protection circuit in 0.18 mm CMOS technology. IEEE J. Solid State Circuits 39, 2389–2396 (2004) 13. T.H. Lee, Planar Microwave Engineering: A Practical Guide to Theory, Measurement and Circuits (Cambridge University Press, Cambridge, 2004) 14. S. Shekhar, J.S. Walling, D.J. Allstot, Bandwidth extension techniques for CMOS amplifiers. IEEE J. Solid State Circuits 41, 2414–2439 (2005) 15. H. Zheng, S.Z. Lou, H.P. Leung, RF system architectures and circuit techniques for wideband transceiver, in Proceedings of the IEEE International Workshop on Radio Frequency Integration Technology, Singapore (2005), pp. 30–37 16. J. Paramesh, D.J. Allstot, Analysis of the bridged T-coil circuit using the extra-element theorem. IEEE Trans. Circuits Syst. II Express Briefs 53, 1408–1412 (2006) 17. S.C. Dutta Roy, Comments on ‘Analysis of the bridged T-coil circuit using the extra element theorem’. IEEE Trans. Circuits Syst. II Express Briefs 54, 673–674 (2007) 18. M.T. Reiha, J.R. Long, Symmetrical monolithic T-coils for broadband IC design, in IEEE Microwave Theory and Techniques Society Symposium, Honolulu, HI (2007), pp. 1909–1911

18

2 Asymmetrical BTC

19. E. Pillai, J. Wiess, Novel T-coil structures and implementation in a 6.4-Gb/s CMOS receiver to meet return loss specifications, in Proceedings of the IEEE Electronic Components and Technology Conference, Reno, NV (2007), pp. 147–153 20. D. Linton, S. Thijs, J. Borremans, M. Dehan, D. Tremouilles, M. Scholz, M. I. Natarajan, P. Wambacq, G. Groeseneken, T-diodes—a novel plug-and-play wideband RF circuit for ESD protection methodology, in Proceedings of the EOS/ESD Symposium, Anaheim, CA (2007), pp. 4A.1.1–4A.1.8 21. M. Kossel, C. Menolfi, J. Weiss, P. Buchmann, G.V. Bueren, L. Rodoni, T. Morf, T. Toifl, M. Schmatz, A T-coil enhanced 8.5 Gb/s high swing SST transmitter in 65 nm bulk CMOS with RL , can be taken care of by simply interchanging the positions of RS and RL in Fig. 3.1. Eliminating Bp from the two Equations in (3.2), we get X s2 = R S (R L − R S ) = R12 , say Fig. 3.1 The basic L-network

(3.3)

Z1 = jXs

Rs

Y1 = jBP

RL

3.2 The Basic Network

21

Or, X s = ±R1

(3.4)

Combining this with the second Equation in (3.2) gives B p = ±R1 /(R L R S ) = ±G 2 , say

(3.5)

As already stated, the signs in Eqs. (3.4) and (3.5) should be either both positive or both negative.

3.3 Impedance Matching at a Single Frequency For matching RL to RS at a single frequency ω0 , we can choose either an inductance L s for X s and a capacitance C p for Bp , or a capacitance C s for X s and an inductance L p for Bp . In the first case, to be referred to as Design 1 (D1) L s = R1 /ω0 and C p = G 2 /ω0

(3.6)

while for the alternative design, to be called Design 2 (D2), Cs = 1/(R1 ω0 ) and L p = 1/(G 2 ω0 )

(3.7)

We shall mostly use D1 in our further discussions, it is being implied that D2 is equally applicable, giving another set of solutions.

3.4 Application of Frequency Transformation Let ω0 be normalized to 1 rad/s and let S denote the complex frequency variable in the single-frequency matching network. Then the problem of multiple frequency impedance matching reduces to that of transforming S = ±j1 to another set of frequencies s = ±jωi , i = 1 to N, where s denotes the complex frequency variable in the transformed network. It is well known [1, 2] that the functional relationship between S and s is an LC impedance or admittance function of the general form S = (k0 /s) + k∞ s +

 i

  ki s/ s 2 + qi

(3.8)

Using Eq. (3.8) on D2, for example, C s = 1/R1 (recall that ω0 has been normalized to unity) transforms to a parallel connection of a capacitance of value k ∞ /R1 , an inductance of value R1 /k 0 , and a number of series LC circuits, the number being the

22

3 Multiple Frequency Impedance Matching

same as the upper limit in the summation of Eq. (3.8). The ith series LC circuit will have an inductance of value R1 /k i and a capacitance of value k i /(qi R1 ). Similarly, the inductance L p = 1/G2 transforms to a series connection of an inductance of value k ∞ /G2 , a capacitance of value G2 /k 0 and a number of parallel LC circuits, the number being the same as in the case of C s . The ith parallel LC circuit will have an inductance of value k i /(qi G2 ) and a capacitance of value G2 /k i . Similarly, Eq. (3.8) can be used on D1 to derive another circuit which can be used for the same purpose. In addition, note that applied to an inductance, Eq. (3.8) results in a Foster 1 (F1) form of realization, while applied to capacitance, the result is a Foster 2 (F2) form of realization. Each of them can be converted to the other Foster form or Cauer 1 (C1) or Cauer 2 (C2) form. By different combinations of these forms for the two LC networks, a large number of competing circuits can be generated. The set can be further expanded by synthesizing each LC impedance by combining two or more of F1, F2, C1 and C2 forms to generate more circuits having the same impedancematching properties. A further dimension is added to the generation of competing circuits by the flexibility in choosing the transformation function. In general, for odd N, one can choose either of the first two terms in Eq. (3.8) and the summation with i = 1 to (N − 1)/2. For even N, one can choose both of the first two terms in Eq. (3.8) and the summation with i = 1 to (N − 2)/2; alternatively, one can use only the summation with i = 1 to (N/2). The number of circuits that can be generated is, therefore, virtually indefinite. These can be compared, and the best one can be selected according to some appropriate criterion. However, for small values of N, the number of alternative circuits is limited and the designer need not feel uncomfortable in leaving out some a from consideration. For example, for N = 2, we can choose either the first two terms only or a single term in the summation in Eq. (3.8). However, the latter is of the form of reciprocal of the former, and it is easily verified by choosing either of the two options, and using D1 as well as D2 suffice. Also, a single series or parallel LC circuit cannot be converted to any other form, thus giving only two alternative circuits for impedance matching at two frequencies. We shall investigate this case in more details in the next Section. For N = 3, either of the first two terms and a single summation in Eq. (3.8) can be selected and applied to D1 as well as D2, giving four alternative circuits. In addition, each Foster form can be converted to the other, and four combinations, namely, (F1, F1), (F1, F2), (F2, F1) and (F2, F2), are possible for the series and shunt arms of Fig. 3.1. Converting a Foster form of three elements to either of the Cauer forms is not useful here because it gives the other Foster form. It is also not possible to make partial synthesis with one of the Foster or Cauer forms and switching to another form. Thus, a total of eight competing circuits can be found. We shall investigate this case in Sect. 3.6, but shall work out only one design. It can be easily appreciated that the number of alternative circuits grows with increasing N. We shall not discuss this issue further. For finding the element values in any circuit, we require the values of ki s and qi s in terms of ωi s. These can be obtained by the following procedure. Put S = +j1 and s = jω in the chosen transformation equation and simplify. This will give an algebraic

3.4 Application of Frequency Transformation

23

equation in ω of order N, containing the constants ki s and qi s in the coefficients. To find how these constants are related to ωi s, one way is to make a reactance plot of the transformation, i.e. a plot of S/j versus s/j to find out at which values of ω, S/j becomes +1. These frequencies must correspond to ωi s, but not all with positive signs. A simpler way is to use the facts that the reactance (or susceptance) is an odd function of ω and its slope is strictly positive. From these, it is easily shown that if S has a pole at s = 0, i.e. if the first term in Eq. (3.8) is included in the chosen transformation, then the required frequencies are −ω1 , ω2 , –ω3 . On the other hand, if S has a zero at s = 0, then the required frequencies are ω1 , –ω2 , ω3 . Note that the signs alternate, and it is adequate to find the sign of ω1 only. Now equate the previously obtained equation to (ω + ω1 ) (ω − ω2 ) (ω + ω3 )…. = 0, or (ω − ω1 ) (ω + ω2 ) (ω − ω3 )…. = 0, as the case may be. By comparing the coefficients, one can easily find the required ki s and qi s. The procedure will be amply clear from the examples worked out in the following Sections.

3.5 Dual-Frequency Impedance Matching Let the frequencies at which matching is needed be ω1 and ω2 . We use the transformation S = (k0 /s) + k∞ s

(3.9)

As mentioned in the previous section, using this on D1 and D2 suffices to find the only possible competing networks. Note, in passing, that Eq. (3.9) is the well-known low-pass to bandpass transformation. By putting S = +j1 and s = jω in Eq. (3.9) and simplifying, we get the following quadratic equation in ω: ω2 − (1/k∞ )ω − (k0 /k∞ ) = 0

(3.10)

Since S has a pole at s = 0, the roots of this equation are −ω1 and ω2 , so that Eq. (3.10) should be identical to the following: ω2 − (ω2 − ω1 )ω − ω1 ω2 = 0

(3.11)

Comparing coefficients, we get k∞ = 1/(ω2 − ω1 ) and k0 = ω1 ω2 /(ω2 − ω1 )

(3.12)

The networks obtained by using Eq. (3.9) on D1 and D2 are shown in Fig. 3.2a and b, respectively. We shall now compare the two designs with the help of a numerical example. Let ω1 = 0.5 rad/s and ω2 = 0.7 rad/s; these are normalized frequencies and the results can be applied to any situation where ω1 :ω2 = 5:7 by appropriate frequency

24

3 Multiple Frequency Impedance Matching

(a)

1/(k0R1)

(b)

k•R1

k•R1 R1k0

Rs

1/(k0G2)

k•G2

RL

k•G2

RS

RL G2/k0

Fig. 3.2 Circuits obtained by application of Eq. (3.9) to a D1 and b D2

Table 3.1 Comparison of the two circuits of Fig. 3.2

Parameter

(a)

(b)

Total inductance

7.5 H

10.5714 H

Total capacitance

1.7142 F

5.2857 F

Highest inductance

5H

10 H

Highest capacitance

1.1428 F

5F

Inductance spread

2

17.5

Capacitance spread

2

17.5

scaling. Also, let RL = 2 Ohms and RS = 1 Ohms; again, the results can be applied to any situation where RL : RS = 2:1 by impedance scaling. Calculation gives k ∞ = 5, k 0 = 1.75, R1 = 1 Ohms, and G2 = 0.5 mho. The element values, from left to right, are calculated as 5H, 0.5714F, 2.5H and 1.1428F for Fig. 3.2a and 0.5714H, 5F, 10H and 0.2857F for Fig. 3.2b. Table 3.1 shows a comparison of the two circuits for some relevant implementation parameters. Clearly, the circuit of Fig. 3.2a would be a better choice from all considerations. Note that the inductance and capacitance spreads are the same in each circuit; this is expected from the general values given in Fig. 3.2.

3.6 Triple-Frequency Impedance Matching To bring variety into experience, let us use the transformation   S = k∞ s + k1 s/ s 2 + q1

(3.13)

Applied to D1, this gives the circuit shown in Fig. 3.3. By following the procedure given in Sect. 4 and illustrated in the previous Section, the two cubic equations to be compared are obtained as follows: ω3 − (1/k∞ )ω2 − [q1 + (k1 /k∞ )]ω + (q1 /k∞ ) = 0

(3.14)

3.6 Triple-Frequency Impedance Matching

25

Fig. 3.3 Circuit obtained by applying Eq. (3.19) to D1

k•R1

1/(k1R1) k1R1/q1

RS

1/(k1R1)

k•G2

R1

k1G2/q1

And (ω − ω1 )(ω + ω2 )(ω − ω3 ) = ω3 − (ω1 − ω2 + ω3 ) or, ω2 − (ω1 ω2 + ω2 ω3 − ω1 ω3 )ω + ω1 ω2 ω3 = 0

(3.15)

Comparison gives k∞ = ω1 − ω2 + ω3 , q1 = ω1 ω2 ω3 k∞ , and k1 = k∞ (ω1 ω2 + ω2 ω3 − ω1 ω3 − q1 )

(3.16)

The element values of the circuit in Fig. 3.3 can now be calculated.

3.7 Impedance Matching at Four Frequencies In this as well as the next Section, for brevity, we shall skip the routine steps and the circuit diagrams, and shall only give the design equations. We choose the transformation       S = k1 s/ s 2 + q1 + k2 s/ sm2 + q2

(3.17)

The roots of the quartic equation obtained from Eq. (3.17) should be ω1 , −ω2 ω3 and −ω4 . The equations for finding ki s and qi s are k1 + k2 = −ω1 + ω2 − ω3 + ω4 = A, say

(3.18)

q1 + q2 = ω1 ω2 − ω1 ω3 + ω1 ω4 + ω2 ω3 − ω2 ω4 + ω3 ω4 = B, say

(3.19)

k1 q2 + k2 q1 = ω2 ω3 ω4 − ω1 ω3 ω4 + ω1 ω2 ω4 − ω1 ω2 ω3 = C, say

(3.20)

q1 q2 = ω1 ω2 ω3 ω4 = D, say

(3.21)

26

3 Multiple Frequency Impedance Matching

q1 and q2 can be found from Eqs. (3.19) and (3.21) by solving a quadratic equation. This gives two solutions, one being the reciprocal of the other. Either of them can be chosen for q1 ; then the other is q2 . Substituting these values in Eq. (3.20) and combining with Eq. (3.18), one can find k 1 and k 2 . The final results are q1 = (1/2)[B +



B 2 − 4D)], q2 = D/q1 , k1 = (Aq1 − C)/(q1 − q2 ), and k2 = A − k1

(3.22)

It is easily shown that interchanging the values of q1 and q2 has the effect of interchanging the values of k 1 and k 2 , so that the circuit does not change.

3.8 Impedance Matching at Five Frequencies Let the transformation function be       S = (k0 /s) + k1 s/ s 2 + q1 + k2 s/ s 2 + q2

(3.23)

By applying Eq. (3.23) to D1 or D2, the resulting circuit configuration can be easily drawn. For the constants, the equations to be solved are obtained as k0 + k1 + k2 = ω1 − ω2 + ω3 − ω4 + ω5 = A, say q1 + q2 = ω1 ω2 − ω1 ω3 + ω1 ω4 − ω1 ω5 + ω2 ω3 − ω2 ω4 + ω2 ω5 + ω3 ω4 − ω3 ω5 + ω4 ω5 = B, say

(3.24) (3.25)

k1 q2 + k2 q1 + k0 (q1 + q2 ) = ω1 ω2 ω3 − ω1 ω2 ω4 + ω1 ω2 ω5 + ω1 ω3 ω4 − ω1 ω3 ω5 + ω1 ω4 ω5 − ω2 ω3 ω4 + ω2 ω3 ω5 − ω2 ω4 ω5 + ω3 ω4 ω5 = C, say (3.26) q1 q2 = ω1 ω2 ω3 ω4 + ω1 ω2 ω4 ω5 − ω1 ω2 ω3 ω5 − ω1 ω3 ω4 ω5 + ω2 ω3 ω4 ω5 = D, say (3.27) k0 q1 q2 = ω1 ω2 ω3 ω4 ω5 = E, say

(3.28)

As in the case of the previous Section, q1 and q2 can be solved from Eqs. (3.25) and (3.27) by solving a quadratic equation, whose solutions are reciprocals of each other. Also, as in the previous case, interchanging q1 and q2 has the effect of interchanging the values of k 1 and k 2 . Once q1 and q2 are determined, k 0 is found from Eq. (3.28), and k 1 and k 2 are found from Eqs. (3.24) and (3.26). The final results are as follows: q1 = (1/2)[B +



B 2 − 4D], q2 = D/q1 , k0 = E/D,

k1 = {[A − (E/D)]q1 − [C − (B E/D)]}/(q1 − q2 ) and k2 = A − k0 − k1 (3.29)

3.9 Summary of the Procedure

27

3.9 Summary of the Procedure The steps in the design of networks for impedance matching at multiple frequencies can be summarized as follows: Step 1. Design the basic network D1 or D2 or both for the given RL and RS with ω0 = 1 rad/s. Step 2. Choose the transformation function as follows. For N = 2, choose either the first two terms only or a single term in the summation in Eq. (3.8). For odd N ≥ 3, choose either of the first two terms in Eq. (3.8) and the summation with i = 1 to (N − 1)/2. For even N ≥ 4, choose the first two terms in Eq. (3.8) and the summation with i = 1 to (N − 2)/2; alternatively, use only the summation with i = 1 to (N/2). Step 3. Apply the transformation to D1 (or D2 or both) to obtain the circuit configuration (s) and element values in terms of ki s and qi s. Step 4. Put S = j1 and s = jω in the transformation function and simplify to get an Nth order algebraic equation in ω. Step 5. Identify the roots of the equation obtained above as ω1 , −ω2 , ω3 ,… or −ω1 , ω2 , −ω3 ,… depending on whether S has a pole at the origin or not. Write the equation in terms of ωi s and compare its coefficients with those of the equation obtained in Step 4. Step 6. Find the ki s and qi s in terms of ωi s from the results of Step 5, and substitute them in the circuit (s) obtained in Step 3. Step 7. Find some alternative circuits from the results of Step 6 by synthesizing the series and shunt LC impedances by Foster or Cauer techniques or a combination of them. Also, explore other possible transformations, if necessary, and finally, choose the best one according to a predefined criterion.

3.10 Concluding Discussion In this chapter, we have presented the application of frequency transformation technique to impedance matching at multiple frequencies in formal network theoretic terms. This allows a multiplicity of solutions to be found out, from which one can make a selection based on an appropriate criterion. Explicit design equations have been given for N = 2 to 5. While we have confined the discussion to only L-configuration, it should be obvious that the technique can be applied to other basic configurations like T or π . In all cases, however, the solution is far from being canonic. In fact, in the circuits considered in this chapter, we require 2 N number of components for matching at N frequencies. A reduction in component count may be possible by using other configurations of the basic network or by using two-port synthesis techniques. We have considered only resistive source and load impedances and have assumed lossless inductances and capacitances. Some useful discussions on complex load

28

3 Multiple Frequency Impedance Matching

impedances, and component losses have been included in [4], but there is scope for formalizing the procedures in network theoretic terms and evolving design procedures for the general case. In this chapter, we have not considered the bandwidth over which impedance matching takes place with a certain level of tolerance. There is a short discussion on this aspect in [4], but again, there is scope for further research, particularly because of the fact that if the ωi s are not far apart, then the response around any ωi is affected by that around other ωi s close by. The positive aspect of this interaction is that one may be able to design wideband-matching circuits by placing ωi s close together. Acknowledgements This research was supported by the Honorary Scientist scheme of the Indian National Science Academy. The author thanks Shoubhik Dutta Roy for his help in the preparation of this manuscript.

References 1. L. Wienberg, Network Analysis and Synthesis (Wiley, Hoboken, New Jesrsey, 1962) 2. E.A. Guillemin, Synthesis of Passive Networks (Wiley, Hoboken, New Jesrsey, 1964) 3. S.C. Dutta Roy, On the design of multiple pass-band filters by frequency transformation. IETE J. Res. 58, 20–23 (2012) 4. N. Nallam, S. Chatterjee, Multi-band frequency transformations, matching networks and amplifiers. IEEE Trans. Circuits Syst. I. Regular Papers, 60, 1635–1647 (2013)

Chapter 4

Triple Frequency Impedance Matching by Frequency Transformation

Abstract The purpose of this chapter is to bring to the attention of students and teachers of circuit theory, as well as of practising design engineers, a recently reported technique for impedance matching at multiple frequencies. This will be done through a specific example, namely that of design of a lumped network for matching a given load resistance RL to a given source resistance RS at three given frequencies ω1 , ω2 and ω3 . The method is based on the application of the frequency transformation technique, commonly used in analog filter design, to a basic single-frequency matching network. By comparison with the existing approach of assuming a network configuration and solving a set of simultaneous equations, as reported in a recent paper, the new method is shown to have the advantages of design by synthesis, elegance and simplicity. Further, by virtue of the synthesis approach, the method allows a number of alternative networks to be designed, so that the best one can be selected on the basis of a predetermined criterion. Keywords Frequency transformation · Network design · Impedance matching · Multiple frequency matching

4.1 Introduction Modern multi-band mobile communication has created the need for microwave systems which can handle several frequencies by the same hardware, without the necessity for switching. This, in turn, requires networks which can match a given load to a given source at multiple frequencies. Most of the work reported in the literature on this subject has focussed on dual-band matching, using distributed networks [1–5]. Triple frequency matching has also been reported [6] using such networks. Distributed network systems become bulky, particularly when the operating frequencies are not very high, and lumped or hybrid systems have therefore been developed for compact devices [7, 8].

Source: S.C.Dutta Roy, “Triple Frequency Impedance Matching by Frequency Transformation.” IETE Journal of Education, vol 55, pp 47–51, January–June 2014. © Springer Nature Singapore Pte Ltd. 2020 S. C. Dutta Roy, Topics in Signal Processing, https://doi.org/10.1007/978-981-13-9532-1_4

29

30

4 Triple Frequency Impedance Matching

Most of the network topologies used so far have been based on a design by analysis, i.e. by assuming a possible network configuration from heuristic considerations and experience, analysing it, and then solving a set of simultaneous equations to derive the component values. The purpose of this chapter is to bring to the attention of students and teachers of circuit theory as well as of practising design engineers a recently proposed method [9, 10] for the same purpose, which is based on the frequency transformation technique, as commonly used in analog filter design [11]. This will be done through a specific example, namely that of designing a network for matching a load resistance RL to a given source resistance RS at three given frequencies ω1 , ω2 and ω3 . The reason for this specific choice is to compare the method with the existing approach for the same design, as reported in a recent paper [8]. It is shown that the new method is characterized by design by synthesis, elegance and simplicity. The circuit configuration evolves automatically, and by virtue of the synthesis approach, a number of alternative circuits can be easily found, from which the best one can be selected in accordance with a predetermined criterion. First, for ready reference, we give a brief review of the general theory, and then discuss the design of the triple frequency transformer.

4.2 General Theory 4.2.1 Basic L-Network for Impedance Matching We first consider the general L-network shown in Fig. 4.1 (called network D2 in [10]), where X s is a reactance and Bp is a susceptance. For matching, we require the relation   Rs = 1/ j B p + 1/(R L + j X s )

(4.1)

to be satisfied at the frequency or frequencies of interest. Simplifying Eq. (4.1) and equating the real and imaginary parts on both sides give the following equations:   Rs 1 − X s B p = R L

(4.2a)

and Fig. 4.1 The basic L-network for impedance matching

jXs Rs

jBp

RL

4.2 General Theory

31

B p R L Rs =X s

(4.2b)

Equation (4.2b) shows that Bp and X s should be of the same sign. Also, combining Eq. (4.2a, b) to eliminate Bp , we get X s2 = R L (Rs − R L )

(4.3)

Equation (4.3) shows that the configuration is applicable only if Rs > RL . This is no restriction, however, because for the other case, i.e. Rs < RL , the positions of the source and the load are to be interchanged. Equation (4.3) gives  X s = ± [R L (Rs − R L )] = ±R1 , say

(4.4)

B p = ±R1 /(R L R S ) = ±G 2 , say.

(4.5)

and correspondingly,

As mentioned earlier, Bp and X S should both be either positive or negative. As discussed in the comprehensive network theoretic formulation of the technique by Dutta Roy [10], one could have a parallel development with the L-network having the shunt arm Bp across RL and the series arm X S in series with the source (this is called network D1 in [10]). As mentioned later in this chapter, this alternative is important in deriving other alternative equivalent circuits for matching.

4.2.2 Single-Frequency Matching For matching at a single frequency ω0 , one choice is to have an inductor L 1 for X s and a capacitor C 2 for Bp , while the other choice is to have C 1 for X s and L 2 for Bp . Using the first choice, the element values are: L 1 = R1 /ω0 and C 2 = G2 /ω0 .

4.2.3 Application of Frequency Transformation Frequency transformation is a well-known technique in analog filter design [11] by which a normalized lowpass filter with a cut-off at 1 rad/sec can be transformed to any other kind of filter, be it high-pass, bandpass, band-stop or multi-bandpass, with the same tolerances as in the prototype. Basically, it transforms the frequency of 1 rad/sec to the cut-off frequencies of the desired filter. In more general terms, the performance at 1 rad/sec is reproduced in the transformed filter at the desired frequencies. There is no reason why performance cannot be impedance matching, as demonstrated in [9, 10] and this chapter.

32

4 Triple Frequency Impedance Matching

Let S denote the complex frequency variable in the single-frequency matching network and let ω0 be normalized to 1 rad/sec. Then the problem reduces to that of transforming S = ±j1 to the multiple frequencies s = ±jωk , where, in general, k = 1, …, N, s being the complex frequency variable in the transformed network. As is well known [12, 13], the transformation function is an LC immittance (impedance or admittance) function of the form S = k0 /s + k∞ s +



  ki s/ s 2 + qi

(4.6)

where the limits of the summation are determined by the number of frequencies at which matching is required. For example, if N = 2, then the first two terms in Eq. (4.6) suffice. Alternatively, one can use only the first term in the summation, which, in fact, is of the same form as the reciprocal of the first two terms. For N = 3, as is the case in the example to follow, either of the first two terms and one term in the summation serve the purpose. In general, for N odd and ≥3, either of the first two terms is to be taken along with the summation with i ranging from 1 to (N−1)/2. For N even and ≥4, there are two choices, viz. (1) take the first two terms and the summation with i ranging from 1 to (N−2)/2 or (2) take only the summation with i ranging from 1 to (N/2). In addition, as already mentioned, there are two choices for the basic single-frequency matching network. Clearly, with the flexibility in choosing the basic network and the transformation function, one can generate a number of matching networks having the same performance. Some more alternative networks can be generated by synthesizing each of the reactance and susceptance functions by the other Foster or Cauer or mixed canonic forms. From this multiplicity of networks, one can choose the best one using some appropriate criterion like the total inductance or capacitance or the spread in the values of the components.

4.3 Triple Frequency Matching Network We shall now illustrate the simplicity, elegance and flexibility of the frequency transformation technique by designing a triple-frequency matching network. The basic network is shown in Fig. 4.2a, where the fact that ω0 has been normalized to 1 rad/sec has been taken into account. One appropriate transformation for this case is   S = k0 /s + k1 s/ s 2 + q1

(4.7)

The impedance of L 1 (=R1 ) thus transforms into   S L 1 = (k0 R1 )/s + k1 R1 s/ s 2 + q1

(4.8)

4.3 Triple Frequency Matching Network

33

(a)

(b)

Cse

Ls = R1 Cp = G2

Rs

RL

Lp

Rs

Ls Cs RL

Cp

Fig. 4.2 Triple-frequency impedance transformer: a basic single-frequency matching circuit and b triple-frequency matching circuit with element values given in the text

The right-hand side of Eq. (4.8) represents a series connection of a capacitance C se = 1/(k 0 R1 ) and a parallel L s C s circuit with L s = k 1 R1 /q1 and C s = 1/(k 1 R1 ), as shown in Fig. 4.2b. Similarly, the admittance of C 2 (=G2 ) transforms to the circuit shown in the shunt arm of Fig. 4.2b with the following element values: L pe = 1/(k 0 G2 ), C p = k 1 G2 /q1 and L p = 1/(k 1 G2 ). Now the only task that remains to be done is to find the values of k 0 , k 1 and q1 . For this purpose, put S = j1 and s = jω in Eq. (4.8); after simplification, we get the following equation in ω: ω3 + (k0 + k1 )ω2 − q1 ω − k0 q1 = 0

(4.9)

The roots of this equation should give ω1 , ω2 and ω3 , but not all with positive signs. To find which one(s) would be positive, we sketch the reactance function of Eq. (4.8) as shown in Fig. 4.3 and find the frequencies at which S/j = 1. Clearly, the roots of Eq. (4.9) are −ω1 , ω2 and −ω3 . Figure 4.3 also shows that had we taken S/j = −1 in Eq. (4.8), the resulting cubic equation would have the roots ω1 , −ω2 and ω3 . Returning to Eq. (4.9), we see that the left-hand side should be equal to

S/j = W +1

-w 1 -1

Fig. 4.3 Reactance sketch of Eq. (4.8)

w3

w1

-w 2 -w 3

w2

S/j = w

34

4 Triple Frequency Impedance Matching

(ω + ω1 )(ω − ω2 )(ω + ω3 ) = ω3 + (ω1 − ω2 + ω3 )ω2 − (ω1 ω2 + ω2 ω3 − ω3 ω1 )ω − ω1 ω2 ω3

(4.10)

Comparing the right-hand side of Eq. (4.10) with the left-hand side of Eq. (4.9), we get the following three equations: k0 + k1 = ω1 − ω2 + ω3 , q1 = ω1 ω2 + ω2 ω3 − ω3 ω1 , and k0 q1 = ω1 ω2 ω3

(4.11)

Solving these equations, we finally get q1 = ω1 ω2 + ω2 ω3 − ω3 ω1 , k0 = ω1 ω2 ω3 /q1 , and k1 = ω1 − ω2 + ω3 − k0

(4.12)

The circuit of Fig. 4.2b was previously derived by Lin, Chen and Zhao [8] following the conventional approach, i.e. by assuming the circuit, analysing it and then setting up and solving the equations obtained at the three frequencies. As a numerical example, they considered the following specifications: RL = 25 , RS = 50  and {ω1 , ω2 , ω3 } = {0.225, 0.425, 0.625} GHz. Calculations from Eq. (4.12) and the expressions for the element values given under Eq. (4.8) give C se = 23.5 pF, L s = 2.78 nH, C s = 41.31 pF, L pe = 29.38 nH, C p = 2.22 pF and L p = 51.64 nH. These are exactly the same as those obtained in [8]. Simulation and experimental results given in [8] validate the design.

4.4 Alternative Circuits for Triple Frequency Matching As mentioned in the previous section, several alternative circuits for the triple frequency impedance matching can now be obtained. Figure 4.2b network, as it is, has the shunt arm in Foster 2 form (henceforth abbreviated as F2) and the series arm in Foster 1 form (henceforth abbreviated as F1). The shunt arm can also be realized in F1 and the series arm can also be realized as F2. Accordingly, we have four alternative circuits, viz. (F2, F1), (F2, F2), (F1, F2) and (F1, F1). Note that for a three-element network, Cauer forms will reduce to either F1 or F2. Second, using an inductance for Bp and a capacitance for X s in the basic network of Fig. 4.1, and then applying the transformation of Eq. (4.7), one obtains a different circuit which also allows four different circuits to be generated. Third, if the basic network is chosen as D1 of [10], in which there is a shunt arm Bp across RL and a series arm X s in series with RS , then as in the case of D2 discussed so far, another eight networks can be generated, thus making a total of 16 alternative circuits for the same impedance matching purpose. As mentioned in Sect. 2.2, an alternative transformation for triple-frequency impedance matching is

4.5 Conclusions

35

  S = k∞ s + k1 s/ s 2 + q1

(4.13)

The values of the constants have been worked out in [10] along with a possible circuit by transforming the basic network D1, in which the series arm is F1 and the shunt arm is F2. Following the same procedure as in the case of Eq. (4.7), another 16 different circuits can be generated, thus making a grand total of 32 alternative circuits for any specified triple-frequency impedance matching problem. All these circuits can now be compared in terms of total inductance, total capacitance, maximum inductance, maximum capacitance, inductance spread, and capacitance spread, as done in [10] for a dual-frequency impedance matching circuit, and the best one can be chosen in accordance with a predetermined criterion.

4.5 Conclusions As discussed and demonstrated in this chapter, the application of frequency transformation on the basic single-frequency impedance matching network eases the problem of designing multiple frequency matching networks. It gives multiple solutions and facilitates the choice of the most suitable network in a given situation. Acknowledgements This work was supported by the Indian National Science Academy through the Honorary Scientist scheme. The author thanks Shoubhik Dutta Roy and Yashwant V. Joshi for their help in the preparation of this chapter. Thanks are also due to the reviewer for constructive comments.

References 1. C. Monzon, A small dual frequency transformer in two sections. IEEE Trans. Microw. Theory Tech. 51, 1157–61 (2003) 2. Y. Wu, Y. Liu, S. Li, A dual frequency transformer for complex impedances with two unequal sections. IEEE Microw. Wirel. Compon. Lett. 19, 77–79 (2009) 3. X. Liu, Y. Liu, S. Li, F. Wu, Y. Wu, A three section dual band transformer for frequency dependent complex load impedance. IEEE Microw. Wirel. Compon. Lett. 19, 611–613 (2009) 4. F. Paredes, G. Gonzales, J. Bonache, F. Martin, Dual band impedance matching networks based on split-ring resonators for application in RF identification (RFID). IEEE Trans. Microw. Theory Tech. 58, 1159–1166 (2010) 5. M.L. Chuang, Dual band impedance transformer using two section shunt stubs. IEEE Trans. Microw. Theory Tech. 58, 1257–1263 (2010) 6. C.S. Lee, C.-L Yang, A coupling matrix based design of triple band matching network. IEEE Microw. Wirel. Compon. Lett. 23, 391–393 (2013) 7. Y. Liu, Y.J. Hao, Y. Hao, Lumped dual frequency transformer for frequency dependent complex loads. Prog. Electromagn. Res. 126, 121–138 (2012) 8. Y. Liu, Y. Chen, Y.J. Zhao, Lumped triple-frequency impedance transformer. Electron. Lett. 48, 1193–1194 (2012)

36

4 Triple Frequency Impedance Matching

9. N. Nallam, S. Chatterjee, Multi-band frequency transformations, matching networks and amplifiers. IEEE Trans. Circuits Syst.-I: Regular Papers. 60, 1635–1647 (2013) 10. S.C. Dutta Roy, Network design for multiple frequency impedance matching by the frequency transformation technique. IETE J. Res. 59, 698–703 (2013) 11. S.C. Dutta Roy, On the design of a multiple pass-band filter by frequency transformation. IETE J. Res. 58, 20–23 (2012) 12. L. Wienberg, Network Analysis and Synthesis (Wiley, Hoboken, NJ, 1962) 13. E.A. Guillemin, Synthesis of Passive Networks (Wiley, Hoboken, NJ, 1964)

Part II

Analog Signal Processing: Signal Processing by Distributed Networks

This part contain three chapters. In Chap. 5, we show that the familiar topological formulas to representation network can be extended to distributed networks also as a limiting case. Chapter 6 deals with equivalent circuits of lossy transmission lines. It is shown that short circuited lossy transmission lines are equivalent to a lossless line terminated in a resistance and that the equivalence is valid in two port sense also. Finally, in Chap. 7, we deal with the approximating a variable delay using a tapped delay line.

Chapter 5

Application of Topological Formulas to Distributed Parameter Networks

Abstract Topological formulas for lumped electrical networks are extended to distributed parameter networks, and explicit expressions are obtained for the two-port parameters of a non-uniform transmission line. The results agree with those derived earlier by Protonotarios and Wing, following a different procedure. Keywords Topological formulas · Distributed network · Non-uniform transmission line

Nomenclature T2i1 i2 ... j1 j2 Ui1 i2 ..., j1 j2 ...,k1 k2 ...

V (Y ) Wi1 i2 ... j1 j2 ... (Y ) [z]

a two-tree in which the sets of vertices {i1 , i2 , …} and {j1 , j2 , …} are in different connected parts. sum of admittance products of three-trees in each of which the sets of vertices {j1 , j2 , …}, {j1 , j2 , …} and {k 1 , k 2 , …} are in different connected parts. sum of admittance products of trees. sum of admittance products of two-trees T2i1 i1 ..., j1 j2 ... . matrix of open-circuit impedance parameters of a two-port network.

5.1 Introduction Topological formulas have now been well established for lumped electrical networks, both passive and active [1–3]. However, no attempt appears to have been made so far to apply these formulas to distributed parameter networks. In this chapter, topological formulas are used to obtain explicit expressions for the open-circuit Source: A.Prabhakar & S.C. Dutta Roy, “Application of Topological Formulas to Distributed Parameter Networks,” JITE, vol 18, pp 197–199, May 1972. © Springer Nature Singapore Pte Ltd. 2020 S. C. Dutta Roy, Topics in Signal Processing, https://doi.org/10.1007/978-981-13-9532-1_5

39

40

5 Topological Formulas

Fig. 5.1 Passive two port

1

2

1¢

2¢

impedance parameters of one example of a distributed parameter network, viz. a non-uniform transmission line. Although essentially the same results have already been derived by Protonotarios and Wing [4] by a different procedure, it is believed that the approach adopted here is new, and it is hoped that it will stimulate further interest in the application of graph-theoretic techniques to distributed parameter networks.

5.2 Topological Formulas We first recall the well-known topological formulas [1, p. 170] for the open-circuit impedance parameters of a two-port network (Fig. 5.1)   1 W12,1 2 (Y ) − W12 ,1 2 (Y ) W1,1 (Y ) × [z] = W12,1 2 (Y ) − W12 ,1 2 (Y ) W2,2 (Y ) V (Y )

(5.1)

where det[z] = U (Y )/V (Y )

(5.2a)

U (Y ) = U12 ,2,1 + U1,2,1 ,2 + U12,2 ,t + U1,2 ,1 2

(5.2b)

and

5.3 Formulas for Ladder Networks and Extension to Non-uniform Transmission Lines Consider a section of non-uniform transmission line of length l, for which z(x) and y(x) denote the series impedance and shunt admittance, respectively, per unit length of the line, at a distance x from the input port. We approximate the line by an n-section ladder as shown in Fig. 5.2, with x = l/n, Z k = z(kx)x and Yk = y(kx)x In applying Eqs. (5.1) and (5.2a, 5.2b) to Fig. 5.2, we first note that

(5.3)

5.3 Formulas for Ladder Networks and Extension to Non-uniform … Fig. 5.2 Non-uniform line approximated by ladder

Z1

1

41

Z2 Y1

Zn Y1

1¢

2 Yn 2¢

W12,1,2 (Y ) = U12,2,1 = U12,2,1 = U1,2,12 = 0

(5.4)

We may, therefore, rewrite [z] and det[z] in the form  

n ⎤     W W Z (Y ) Z (Y ) 1,1 i 12,1 2 ⎥ ⎢ i=1 i 1 ⎥  

n

i=1n  [z] = n ×⎢ ⎦ ⎣   i=1 Z i V (Y ) Z i W12,1 2 (Y ) Z i W2,2 (Y ) ⎡

n 

i=1

(5.5)

i=1

and  n i=1 Z i U1,2,1 2  det[z] = n i=1 Z i V (Y )

(5.6)

n Z i has been introduced in the numerator and denominator for where the factor i=1 later convenience. Now, every tree of the ladder must contain at least one of the shunt arms. A tree is formed by any non-empty subset of the shunt arms, together with all the series arms preceding the first shunt arm in the subset, all the series arms succeeding the last shunt arm in the subset and all but one of the series arms between any two successive shunt arms  in the subset. Finding out all the trees, multiplying each tree admittance n Z i , and summing, we obtain product by i=1  n 

 Z i V (Y ) =

i=1

n 

Yi1 Z i2 Yi2 Z i3 . . . Z i j  Yi j

(5.7)

j=1

i 1 2Q, G = (1/Q) − 2G 1

(11.12)

Under these conditions, Eq. (11.6) gives SKQ1 = G 2 /(G + 2G 1 ) > 2Q 2

(11.13)

As is well known, when unity gain is obtained with an OA of gain A of the order of 106 , K = A/(1 + A) ≈ 1; so that S AQ = SKQ1 · S AK 1 > 2Q 2 /A. This shows a reduction of the sensitivity by the factor A. If A = 106 , a Q of 500 will give S AQ of the order of 1 ; the gain-sensitivity product (GS) is, however, of the order of 2Q2 . 2  1 ω0   It has already  K = 1, it is evident from  been  shown that Sei ≤ 2 . Also, if Eq. (11.8) that  SeQi  ≤ 1. For practical design values,  SeQi  will be within 21 . As an example, let C = C 1 = l, K 1 = 1, R = R1 = 3Q, R2 = 1/3Q; then the sensitivities are, for medium to high Q. ⎫ ⎪ S ωAo = 0, S AQ = 3Q 2 /A ⎬ ωo ωo ωo ωo ωo 1 S R  S R2  − 2 = S R = SC1 = S R1 ⎪ S RQ ≈ 1/3, S RQ2  − 21 , S RQ1 = SCQ = −SCQ1 = 1/6 ⎭

(11.14)

The UGOA circuit has thus very low passive sensitivities and also presents component reduction. However, because of the high value of gain-sensitivity product (GS), the usefulness is limited to low and medium Q’s only. It has been found that increasing the spread in capacitors does not lead to any marked improvement.

11.4.2 Case B: General K Configuration For a general K 1 , proceeding on similar lines, the following result is obtained for the case of minimum possible SKQ1 : √ √ SKQ min = 2 2.Q − 1, K 1 > 2 − 1/( 3Q)

(11.15)

1

This implies that K 1 = 2 suffices to get any Q; and this can be obtained by using a high gain OA with equal resistors. The value of GS for this case is proportional to Q and the design equations are K 1 = 2, C = C1 = 1, G 2 =

√

√ 2 − 1/(2Q), G 1 = 1/ 2, G = 1/(2Q)

(11.16)

  Sensitivity calculation gives  Seiωo  ≤ 21 as before; however, SCQ , SCQ1 , S RQ1 and S RQ2 become proportional to Q whereas S RQ  3/2. These passive Q sensitivities

92

11 Low Gain Op Amp Active RC Filters

agree with the order given by Mitra [10] for the denominator of the form D(s) = (s + α1 )(s + α2 ) − K 1 s, to which Eq. (11.1) belongs. Thus only for K 1 = 1, there is a very significant reduction in the passive Q-sensitivity.

11.5 Frequency Limitation In this section, frequency limitations are discussed for cases A and B and expression are derived for the highest usable frequency (ω0h ) for a given percentage deviation from nominal ω0 and Q. The analysis and the pole-loci are based on the one-pole roll-off model of the OA. Assuming a finite gain-bandwidth product (GB), an infinite input impedance and {Ra A/(Ra + Rb )}  1, the gain of the non-inverting amplifier is K 1 = G B/{s + (G B/K )}

(11.17)

where A is the open-loop gain of OA and K = 1 + Rb /Ra is the gain corresponding to infinite gain-bandwidth product (GB) and Ra , Rb are the biasing resistances.

11.5.1 Case A: OA in Unity Gain Configuration With K 1 = 1, on substituting Eq. (11.17) in Eq. (11.1), the normalized denominator of the transfer function becomes D(sn ) = (sn2 + sn /Q + 1) +

1 · sn [sn2 + (1/Q + L)sn + 1] G Bn

(11.18)

where sn = s/ωo , G Bn = G B/ωo , and 1

L = {R R1 /[R2 (R + R)]} 2

(11.19)

Using Budak–Peterela method [11], Eq. (11.18) can be put as P1 (sn ) + (1/G Bn )P2 (sn ), with P1 (sn ) = sn2 + (sn /Q) + 1 P2 (sn ) = sn [sn2 + (1/Q + L)sn + 1]

(11.20)

giving 

 d Pn = −P2 (sn )/ddsPn1 (sn )  d(1/G Bn ) sn = pn dβn dαn  − d(1/G + j Bn ) d(1/G Bn )

⎫ ⎬ ⎭

(11.21)

11.5 Frequency Limitation

93

where 1

pn = −αn + jβn = −(1/2Q) + j[1 − 1/4Q 2 ] 2

(11.22)

Following Budak et al. [11], the above equations can be manipulated to give −L dβn dαn = , =− d(1/G Bn ) 2Q d(1/G Bn )

(4Q 2 − 2)L 1

(11.23)

8Q 2 [1 − 1/4Q 2 ] 2

 −L/2

(11.24)

where Eq. (11.24) holds for medium and high Q. Using Budak [11], Eqs. (11.13) and (11.14), and substituting Eq. (11.23) yields ωo L dQ QL dωo =− ; = d(1/G Bn ) 2 d(1/G Bn ) 2

(11.25)

Thus after the first-order correction to the nominal values of ω0 and Q1 , the actual values are ωoa = ωo (1 − ωo L/2G B) Q a = Q(1 + ωo L/2G B)

(11.26)

Equations in (11.26) are the frequency limitation equations of the filter with UGOA. For a prescribed variation in ω0 and Q of x percent from the nominal values, the highest usable frequency is ωo ≤ x · G B/(50L)

(11.27)

11.5.2 Case B: OA in Gain = 2 Configuration Proceeding as in case A it can easily be shown that Eq. (11.18) still represents the pole-defining equation with G Bn (= G Bn /2) replacing G Bn . The differential change in the real and imaginary parts of the complex poles and the actual ω0 and Q can easily be shown to be −L dβn dαn = ; =− d(1/G Bn ) Q d(1/G Bn )

(4Q 2 − 2)L 1

4Q 2 [1 − 1/4Q 2 ] 2

ωo a = ωo (1 − 3ωo L/G B) Q a = Q(1 + 2ωo L/G B)

(11.28)

(11.29)

94

11 Low Gain Op Amp Active RC Filters

(a)

(b)

Fig. 11.3 a Pole-loci for UGOA realization. b Pole-loci for general low-gain (K = 2) realization

Thus the highest usable frequency for x percent allowed variation is ω0 < x · G B/(200L)

(11.30)

11.5 Frequency Limitation

95

The quantity given by Eq. (11.19) is an important design parameter for determining the value of ω0a , Qa and ω0 . In order to compare the frequency limitations of the two cases, we find from the design Eqs. (11.12) and (11.16) developed in Sect. 11.4,   √  max  min  L  K = 1 > 2Q and L  K = 2 < 2

(11.31)

giving ωo |K = 1 < x/100(G B/Q) √ ωo |K = 2 > x/200(G B/ 2)

(11.32)

√ Then for Q > 2 2, OA in K 1 = 2 connection can realize higher ω0 compared with the UGOA case for the same percentage deviation in ωo and Q from nominal values. Equation (11.18) is used for plotting the complex pole-loci as shown in Fig. 11.3a, b for cases A and B, respectively, as a function of Q and GBn for L determined from the design equations. The two sets of curves are similar in nature and show that a decrease in GBn from the nominal value results in a new pole location having lower ω0 (and probably also Q). With increasing Q, the curves of Fig. 11.3a approach the jωn —axis faster than those of Fig. 11.3b. However, the poles are always confined to the left half-plane in both the cases, thus ensuring stable operation.

11.6 Conclusion This chapter discusses canonic bandpass filters using OA in unity gain and low-gain configurations and thus giving a large frequency range of operation. A detailed study is made of the two cases with regard to sensitivity, gain-sensitivity product and the frequency limitations. The UGOA circuit has low passive sensitivity besides giving passive component minimization over similar circuits. By increasing the gain to K l = 2, a marked improvement is shown in the active Q-sensitivity, the gain-sensitivity √ product and the frequency limitations (for Q > 2 2) over the UGOA case. The improvement is however at the cost of passive Q-sensitivity, thus demanding higher tolerances in R’s and C’s. An all-grounded-capacitor equivalent of the filter is given which, coupled with the other advantages already discussed, makes it attractive for IC implementation. The circuit enjoys SKωo1 = 0.

96

11 Low Gain Op Amp Active RC Filters

References 1. M.A. Soderstrand, S.K. Mitra, Extremely low sensitivity active RC filters. Proc. IEEE 57(12), 2175 (1969) 2. P.R. Geffe, A Q-invariant active resonator. Proc. IEEE 57(8), 1442 (1969) 3. T. Deliyannis, A low-pass filter with extremely low sensitivity. Proc. IEEE 58(9), 1366–1367 (1970) 4. R.P. Sallen, E.L. Key, A practical method of designing RC active filters. Trans. IRE. CT 2(1), 74–85 (1955) 5. A.S. Sedra, A class of stable active filters using unity gain voltage followers. IEEE J. SC 7(4), 311–315 (1972) 6. D. Berndt, S.C. Dutta Roy, Inductor simulation using a unity gain amplifier. IEEE J. SC 4(2), 161–162 (1969) 7. H.T. Russel, Single amplifier active filters give stable Q. EDN/EEE. 17(1), 65–66 (1972) 8. F. Anday, Realization of 2nd–order transfer function using a minimum number of elements. Electron. Lett. 8(24), 611–612 (1972) 9. G.S. Moschytz, Gain sensitivity product a figure of merit for hybrid—integrated filters using single operational amplifiers. IEEE J. SC 6(2), 103–110 (1971) 10. S.K. Mitra, Filter design using integrated operational amplifiers (Proc. WESCON, San Francisco, California, 1969) 11. A. Budak, D.M. Petrela, Frequency limitations of active filters using operational amplifiers. IEEE Trans. CT 19(3), 322–328 (1972)

Chapter 12

Some Recent Contributions to Inductor Simulation and Applications to Low-Sensitivity Biquad Design

Abstract Following a brief discussion on the advantages of inductor simulation approach to active filter design, some recent circuits for grounded as well as floating inductors are discussed. The application of simulated inductors to insensitive biquadratic design is illustrated by reference to two recently published techniques. Keywords Inductance simulation · Active RC networks

12.1 Introduction As is well known, active RC filters can be designed either in direct form or in cascade form. In the latter, the prescribed transfer function is realized as a cascade of lower order sections, usually active second order and passive first-order ones. In the direct form, no such decomposition is necessary and the realization is in terms of one structure. Of the various techniques available for this purpose, the more well-known ones are the inductance (L) simulation, the frequency-dependent negative resistance and the generalized impedance converter approaches. It is the first approach that the present chapter is concerned with. In this, a conventional RLC filter is first designed, and then each inductor is replaced by an equivalent active RC one port. There are two advantages of this simple minded procedure. First, the well-established passive synthesis procedures and extensive tables can be used conveniently. Second, as pointed out in [1], this technique often leads to a more stable and a less sensitive realization as compared to other methods. The advantages with regard to sensitivity can be illustrated by considering the doubly terminated lossless network of Fig. 12.1. Let Z i ( jω) = R + j X

(12.1)

The power input Pi (and hence the power delivered to the load, PL ) is given by Source: Suhash C. Dutta Roy, “Some Recent Contributions to Inductor Simulation and Applications to Low Sensitivity Biquad Design,” JIETE, vol 22, pp 419–425, July 1976. An up-dated version of a presentation at the Seminar on ‘Recent Developments in Filter Theory and Design’ held at Hyderabad, December 19–21, 1974. © Springer Nature Singapore Pte Ltd. 2020 S. C. Dutta Roy, Topics in Signal Processing, https://doi.org/10.1007/978-981-13-9532-1_12

97

98

12 Inductor Simulation and Application RS

Fig. 12.1 A doubly terminated LC network Vi

+

LC zi

zo

RL

–

  Pi = PL = |Vi |2 R/ (R + Rs )2 + X 2 .

(12.2)

Let x be a parameter of the LC network. Then the sensitivity of PL to x is S XPL = (x/PL )[(∂ PL /∂ R)(∂ R/∂ x) + (∂ PL /∂ X )(∂ X/∂ x)]

(12.3)

From Eq. (12.2) ∂ PL /∂ R = |Vi |2 (Rs2 − R 2 + X 2 )/[(R + Rs )2 + X 2 ]2

(12.4)

∂ PL /∂ X = −2|Vi |2 R X/[(R + Rs )2 + X 2 ]2 .

(12.5)

and

Normally, doubly terminated LC filters are designed to have maximum power transfer at frequencies of minimum loss in the passband. This implies that at these frequencies, R = Rs and X = 0 which, combined with Eqs. (12.4) and (12.5), lead to the conclusion that PL is insensitive to small variations in the components of the LC network. Similar arguments can be given to show that the output impedance Z 0 should equal RL for zero sensitivity in the passband. The essential task in L simulation approach to active filter design is, obviously, that of designing insensitive active RC one ports having impedances proportional to the complex frequency s. Also, for successful implementation of this technique, the circuits for both grounded and floating inductor simulation are required.

12.2 Gyrator Based Methods Essentially, all active RC circuits for simulating an inductor can be viewed as the realization of gyrators, a gyrator being a nonreciprocal two port, ideally described by the z-matrix

12.2 Gyrator Based Methods

99



0 −r [z] = r 0

 (12.6)

The symbolic representation of a gyrator and its use in simulating a grounded inductor are shown in Fig. 12.2. When two gyrators are cascaded with a capacitor interposed between the two, as shown in Fig. 12.3, one gets a floating inductor. It appears, therefore, that all problems of L simulation are solved if one can realize the z-matrix of Eq. (12.6). A large number of circuits using discrete components and integrated gyrators have been proposed in the literature, of which the Riordan circuit [2] is the most popular; a variation of the Riordan circuit, proposed by Antoniou [3] is shown in Fig. 12.4 and is considered as the best circuit for the purpose. In general, a practical gyrator deviates from the ideal one, described by Eq. (12.6), in that z11 = 0, z22 = 0, and z12 = –z21. The active element phase shifts cause additional complications. These lead to stability and sensitivity problems, but the most important effect is that the realized L becomes frequency dependent and lossy with a finite maximum Q [4]. The problem becomes much more serious in the case of floating-L simulation because, in addition to realizing two ideal gyrators, we also need an exact match between their gyration resistances. Many solutions have so far been proposed, but it Fig. 12.2 Schematic of a gyrator and its use in L simulation

r zin = sCr2

C

Gyrator

Fig. 12.3 Two gyrators used to simulate a floating L

Cr1r2 if r1 = r2

r2

r1 C

Fig. 12.4 Antoniou’s circuit for a gyrator

+ -

zin = sC3G1RL G2G4

G4

G2

C3 +

G1 RL

100

12 Inductor Simulation and Application

has been appreciated that all such gyrator based realizations suffer from the need for accurate matching, in addition to excessive number of active and/or passive elements. It has been amply demonstrated in recent years that what can be achieved by nonideal gyrators can also be obtained by using much simpler and more economic circuits. For example, a lossy grounded inductor circuit may typically consist of one operational amplifier (OA) connected in the unity gain (UG) configuration, two resistors and a capacitor. Similarly, a lossy floating inductor can be made from two UG amplifiers (UGA), three resistors and two capacitors. It is with some of these circuits and their applications that we concern ourselves in the rest of this chapter [5]. As already mentioned, we deal here with some selected contributions only; for other recent contributions, one may refer to the bibliography prepared by the author as referred to in [6], which lists papers published during the period 1971–early 1975. For literature published earlier, reference is made to Beddoes and Morin [7], Mitra [8] and Miller and Newcomb [9].

12.3 General Characteristics of Lossy, Grounded L Simulators All L simulators using a single capacitor realize a bilinear RL impedance of the form Z (s) = H (sτ1 + 1)/(sτ2 + 1), τ1 > τ2

(12.7)

Two canonical passive realizations of Eq. (12.7) are shown in Fig. 12.5. An important special case arises when τ2 = 0, thus giving a series RL impedance; this will be designated as type A. A parallel RL impedance is obtained when H → 0, τ1 → ∞, but H τ1 is finite, this will be called type B. The general case of Fig. 12.5 will be referred to as type C. Setting s = jω in Eq. (12.7), it is easy to show that the realized L and its Q are L = H (τ1 − τ2 )/(1 + ω2 τ22 ) & Q = ω(τ1 − τ2 )/(1 + ω2 τ1 τ2 )

(12.8)

with the Q reaching a maximum value of Q 0 = (1/2)

H(t1 - t2)

H (t1/t2- 1)

   τ1 /τ2 − τ2 /τ1

z(s)

H t1/t2

Fig. 12.5 Canonical representations of a bilinear RL impedance

(12.9)

Ht1 /(t1 - t2) Ht 21 /(t1 - t2)

12.3 General Characteristics of Lossy, Grounded L Simulators

101

at the frequency √ ω0 = 1/ τ1 τ2

(12.10)

At ω = ω0 , the inductance value is L 0 = L dc /(1 + τ2 /τ1 ) ∼ = L dc

(12.11)

where L dc is the dc value of L and the approximation is valid for high Q0 . For types A and B, L and Q are, respectively, given by L = H τ1 and Q = ωτ1

(12.12)

L = H τ1 /(1 + ω2 τ22 ) and Q = 1/(ωτ2 )

(12.13)

and

The sensitivities of L and Q to any parameter can be found by routine calculations. For type C, evaluating the sensitivity at ω = ω0 , it can be shown that S XQ = (1/2)[(τ1 + τ2 )/(τ1 − τ2 )](S Xτ1 − S Xτ2 ).

(12.14)

Since a single capacitor, C, is used, both τ1 and τ2 must be proportional to C; thus SCQ |Type C,ω=ω0 = 0

(12.15)

12.4 Simple Circuits for Lossy Grounded Inductance 12.4.1 Four-Component Circuits Two remarkably simple circuits were forwarded by Prestcott [10] and Berndt and Dutta Roy [11] and are shown in Fig. 12.6a and b, respectively. Note that the only Fig. 12.6 a Prestcott circuit for grounded L simulation. b Berndt–Dutta Roy circuit for the same purpose

R2

(a) +1

R2

(b)

C

R1

k=1

C R1

102

12 Inductor Simulation and Application

Table 12.1 Performance characteristics of Prestcott and Berndt–Dutta Roy circuits

Prestcott

Berndt–Dutta Roy (at ω = ω0 )

Type

A

C

R-spread

May be unity ∼ =2/μ

4Q 20 ∼ =3/μ

1

∼ =1

1 1/2

0 ∼ =1/2

∼ =2Q 2 /μ ∼ 2 =2Q

∼ =2Q 20 /μ ∼ 2 =2Q

SμL (μ = L SC,R 1 R2 Q SC Q S R1 ,R2

OA gain)

SμQ Gain Sensitivity Product (GSP)

0

R2

Fig. 12.7 Ford and Girling scheme for L simulation

R1

C -µ +

difference between them is the position of the CR differentiating network. This, however, leads to quite different characteristics, as given in Table 12.1. A non-zero input admittance (Gi ) and output impedance (R0 ) of the active element can be absorbed in R1 and R2 , respectively in Berndt–Dutta Roy circuit; the effect of either or both in Prestcott circuit is to convert this to a type C circuit. Figure 12.7 shows a circuit proposed by Ford and Girling [12]. With μ = ∞, which is a rather ideal situation, it behaves as type B, with the following characteristics: R-spread may be unity; L ∼ SμL ,Q = 0; SC,R 1 ,R 2 = 1;

SCQ = −1; S RQ1 ,R 2 − 1/2 and GSP = 0.

(12.16)

where GSP = Gain Sensitivity Product. With finite μ, however, we get a type C circuit with deteriorated characteristics, the major effect being that the GSP now becomes 2Q 20 . Further, since the OA is used here without any negative feedback other than that provided by the R1 R2 C network, the performance of the circuit will be severely frequency limited.

12.4 Simple Circuits for Lossy Grounded Inductance

103 R2

Fig. 12.8 Rao–Venkateswaran generalization of Prestcott and Berndt–Dutta Roy circuit

K1 = 1

C K2 = 1 R1

12.4.2 Five-Component Circuit A generalization of Prestcott and Berndt–Dutta Roy circuits was proposed by Rao and Venkateswaran [13] and is shown in Fig. 12.8. This is a type A circuit with the following characteristics: R-spread may be made unity; SμL1 ,μ2 = 1/(μ1,2 + 1); Q L = 1; SμQ1 ,μ2 = (1 + Q 2 )/(μ1,2 + 1); SC,R = 1; SC,R 1 ,R2 1

(12.17)

S RQ = 0; (GSP)1 ∼ = (GSP)2 ∼ = Q 2 ; and L can be adjusted independent of Q.

12.4.3 Circuits Using Six Components The Berndt–Dutta Roy circuit of Fig. 12.6b realizes an impedence Z (s) = R2 (sC R1 + 1)/{sC[R2 + R1 (1 − k)] + 1}

(12.18)

k = 1 + (R2 /R1 )

(12.19)

If we let

in the manner shown in Fig. 12.9, we get a six-component type A circuit. However, this circuit is potentially unstable because, if due to any reason, for example, a change of temperature, k becomes greater than 1 + (R2 /R1 ), i.e. R1 RA becomes greater than R2 RB , a pole is created in the right half-plane. The Caggiano circuit [14] has the same topology as that of Fig. 12.9 but the impedance is now measured across R1 . It suffers from the same stability problem as in the circuit just discussed. With k in the range 1 < k < (1 + R2 /R1 ) in either of these two circuits, one obtains a type C performance with no improvement over the Berndt–Dutta Roy circuit.

104

12 Inductor Simulation and Application R2

Fig. 12.9 Berndt–Dutta Roy circuit operated as type A C

+ m R1

Fig. 12.10 Musiedlak and McPherson circuit

RA = RB R2/R1 RB

R2 RA R1 C

RB

+

-K K = RA/RB

The circuit shown in Fig. 12.10 uses a negative gain amplifier and has been suggested by Musiedlak and McPherson [15]. Note that this circuit can be derived from the low-sensitivity Sallen and Key [16] resonator in Geffe [17], by interchanging the resistors and capacitors and short circuiting the input capacitor.1 This is a type-C circuit with the following features. Minimum gain required, k = 4Q 20 ; R-spread = 16Q 40 ; Q Q SμL ∼ = 1/2; S R1 ,2 ∼ = 1/(8Q 20 ); = 1; SμQ ∼ = −4Q 20 /μ; S RL A,B,C1 ,2 ∼ = 2Q 20 /μ; S R A,B ∼ SCQ = 0 and G S P = 2Q 20

(12.20)

The sensitivities are seen to be low, and the grounded capacitor is a desirable feature for IC implementation; however, the requirement of high gain severely limits the frequency range of application. Another disadvantageous feature is the high Rspread, and the design constraint of R B  1/(ωC) at the frequencies of interest. By changing the position of the R1 C integrating network in Fig. 12.10 to the output, we obtain the circuit of Fig. 12.11, which has the same sensitivity and other performance characteristics as those of the parent circuit, but has the advantage that the finite input impedence RB of the gain block does no longer put a design constraint. If the capacitor in Fig. 12.10 is returned to the output instead of ground, as shown in Fig. 12.12, we get the finite gain version of Ford and Girling circuit. Compared to 1 The

Prestcott and Berndt–Dutta Roy circuits may also be so derived from the Sallen and Key catalog [17].

12.4 Simple Circuits for Lossy Grounded Inductance

105 R2

Fig. 12.11 Circuit derived from Fig. 12.10 by changing the position of the R1 C network

-K

R1

RB

Fig. 12.12 Circuit derived from Fig. 12.10 returning C to amplifier output

C

R2 C

R1

-K

RB

Fig. 12.10, it loses the advantage of a grounded capacitor but has the advantage of L by the factor 1/(4Q 20 ). reducing Sμ,R A, R B

12.4.4 Comments A major conclusion of this presentation of grounded inductance simulators is that while the sensitivity of L and Q to passive elements can be made reasonably small, the sensitivity of Q to the active element and the gain itself cannot be reduced simultaneously. In fact, in all the circuits discussed, the gain sensitivity product is proportional to Q2 . An improvement in this figure is possible only at the expense of an excessive number of elements. In concluding this section, some comments on the effect of finite OA gain and its low-pass frequency response on the realized L and its Q appear to be in order. This study has been conducted by Ahmed and Dutta Roy [18] on the tuned circuits formed by connecting a capacitor across the simulated L. With ideal OA, the zeros of the admittance of the tuned circuit are determined by the equation sCt + (1/H )(sτ2 + 1)/(sτ1 + 1) = 0

(12.21)

where C t is the tuning capacitor. On simplification, Eq. (12.21) yields s 2 + [(τ2 + H Ct )/(H Ct τ1 )]s + 1/(H Ct τ1 ) = 0

(12.22)

from which the quality factor Qt and the resonance frequency ωt are determined to be

106

12 Inductor Simulation and Application

Q t = (H Ct τ1 )1/2 /(τ2 + H Ct )

(12.23)

ωt = (H Ct τ1 )−1/2

(12.24)

and

If each OA is represented by its one-pole roll-off model, viz. μi = μ0i /{1 + (s/ωi )}

(12.25)

then for an n-OA circuit, Eq. (12.22) gets changed to an equation of the form S n+2 + λn+1 s n+1 + · · · + λ1 s + λ0 = 0

(12.26)

where λi ’s are constants. Equation (12.26) must have a dominant complex root pair and can be written as  n 

2 2 s + βn−1 s n−1 + . . . + β0 = 0 s + {sωte /Q te } + ωte where βi ’s are constants and ωte and Qte are, to a good order of approximation, the effective ωt and Qt . A computer algorithm FLAC (Frequency Limitations of Active Circuits) has been written to find Qt0 and ωt0 and hence the percentage deviation, with Qt , ωt , μ0i and ωi as the input data. The results show that the Rao–Venkateswaran circuit has the best performance amongst all such circuits. The negative gain circuits, as expected, have a very low highest usable frequency compared to unity gain circuits.

12.5 Lossy Floating Inductance Simulation A simple, lossy floating inductance simulator circuit is presented in [19]. Consider the Prestcott circuit of Fig. 12.6a with R2 removed from ground, to form the two port of Fig. 12.13. Routine analysis shows that the y-parameters of this circuit are y11 = −y12 = 1/(R1 + R2 + sC R1 R2 ) Fig. 12.13 Prestcott circuit converted to a two port

(12.27) R1

K=1

C

R2

12.5 Lossy Floating Inductance Simulation y11 -y11

1 -y22

y22

2

107 y22 -y22

2 -y11

y11

y11/2 1

1

2

Fig. 12.14 Basic principle of floating immittance simulation R1¢ (= R1)

R1

K=1 1

C

r2 C¢(= C) (= 2R2)

CR1r2 R1+ R¢1+ r2

K¢ = 1 2

K = K¢ = 1 CR1 = C¢R¢1

Fig. 12.15 Dutta Roy’s floating-L simulator

and y22 = −y21 = (sC R1 + 1)(R1 + R2 + sC R1 R2 ).

(12.28)

If two such two ports are cascaded back to back, as in Fig. 12.14, it is easy to show that the result is a floating inductor of impedence Z (s) = R + s L = 2(R1 + R2 ) + 2sC R1 R2 .

(12.29)

The complete circuit is shown in Fig. 12.15, where the values within brackets represent nominal ones. Although the two-component blocks in Fig. 12.14 were assumed identical, it can be shown that this is not essential for obtaining a floating L. For this, one has to analyse Fig. 12.15 with general element values; assuming k ∼ = 1 (with OAs = k ∼  used to realize k and k , this assumption is quite well justified in practice), the only condition required to be satisfied for a floating L turns out to be C R1 = C  R1 .

(12.30)

The resulting floating admittance is Z (s) = R1 + R1 + r2 + sC R1r2 .

(12.31)

where r 2 = R2 + R2 . In practice, Eq. (12.31) can be realized by adjusting a single resistance (R1 or R1 ) so that the voltages at ports 1 and 2 are indistinguishable.

108

12 Inductor Simulation and Application

In order to study the sensitivity characteristics, a general analysis of Fig. 12.15 has been done. The resulting y-parameters are written as Ymn ( jω) = ±1/(Rmn + jωL mn ), where m, n = 1, 2 and the negative sign is used for m = n. The sensitivities of L mn and Q mn = ωL mn /Rmn are evaluated with respect to various parameters and finally, the nominal values of the parameters are substituted. When this is done, it is found that for μ = μ and reasonably high Q’s (> 10), SμL11 ,Q 11 ,L 21 ,Q 21 SμL 22 ,Q 22 ,L 12 ,Q 12 = 0

(12.32)

SμL 11 = SμL22 = (2 + 1/)/μ SμQ 11 = SμQ 22 = (2 + 1/)Q 2 /μ where  = R1 /r 2 . All other sensitivities are found to be less than or equal to unity, some approaching zero as Q increases. With μ = μ ≤ 105 , L mn and Qmn sensitivities to respective μ’s also approach zero provided  is not very small and Q 2 μ/(2 + 1/). In practice,  = 1, i.e. r 2 = R1 is a good choice because then one can fabricate the circuit with equal resistors and equal capacitors. Compared to the earlier known circuits for floating inductor simulation, the circuit just discussed has the following attractive features : low component count; unity spread in resistors, capacitors and active elements; easy adjustment; low sensitivities; absolutely stable configuration; UG connection of OA’s leading to widest possible frequency range of operation; and easy conversion to grounded inductance simulator. Instead of the Prestcott circuit, one could also start from Berndt–Dutta Roy or Rao–Venkateswaran circuit and obtain floating-L simulations. These circuits have been studied by Ahmed [20] together with the frequency limitations of all the three circuits. The Prestcott derived circuit is found to have a superior high-frequency performance as compared to others. However, all three of them are found to be useful up to only a small fraction of the gain bandwidth product of the OA’s. The approach discussed here for floating-L simulation has been independently reported by Wise [21].

12.6 Applications of Simulated L in the Design of Insensitive Biquadratic Sections Leach and Chan [22] proposed a method of insensitive biquadratic design using a perfect simulated L. Dutta Roy and Ahmed [23] showed that one could use a lossy simulated L in this situation with the low-sensitivity feature maintained, and with the added advantage of lower component count. Consider, for example, the circuit of Fig. 12.16, where the (r, L) combination is derived using the Prestcott circuit of Fig. 12.6a. Note that

12.6 Applications of Simulated L in the Design of Insensitive … Fig. 12.16 Insensitive biquad scheme using an L-simulator

A3

V3

+ -1 R

+ Vi -

A2 + -1

V2 C

A1 + -1

V1 r

109

R3

R2

R1

Rf

+

L

+ Vo -

V3 = Vin

    V2 = Vin s 2 + sr/L + 1/(LC) / s 2 + s(r + R)/L + 1/LC ]

   V1 = Vin s 2 + sr/L / s 2 + s(r + R)/L + 1/(LC)

(12.33)

and that V0 = −

3

Vi Ai R f /Ri

(12.34)

i=1

Denoting—Ai Rf /Ri by ai , and substituting for V i /V in from Eq. (12.33), it is easy to show that the transfer function H(s) = V 0 /V in is given by  

 H (s) = s 2 (a1 + a2 + a3 ) + s[r (a1 + a2 + a3 ) + Ra3 ]/L + (a2 + a3 )/(LC) / s 2 + s(r + R)/L + 1/(LC) .

(12.35) Choosing ai ’s, i.e. Ri ’s and Ai ’s appropriately, one obtains all types of second order transfer functions. For example, R2 = ∞, R1 = R2 , A1 = –A2 = ±1 gives low-pass; R2 = R3 = RR1 /r, A1 = A2 = –A3 = ±1 gives high-pass; R1 = ∞, R2 = R3 , A2 = –A3 = ±1 gives bandpass; R1 = ∞, R2 = R3 [1 + R/(r)], A2 = –A3 = ±1 gives bandstop and R1 = ∞, R2 = R3 [1 + R/(2r)], A2 = –A3 = ±1 gives all-pass filters. The Q and ω0 sensitivities can be calculated in the usual manner and it is found that the passive sensitivities are all less than unity, some of them being zero and some 1/2. The multiparameter sensitivities are

110

12 Inductor Simulation and Application R2

Fig. 12.17 Dutta Roy’s insensitive biquad scheme using the circuit of Fig. 12.8 +

C2

K1=1

V1

K2=1

C1

Vi

R1

+ V2 -

z1 = R2 + s C1R1R2

ω0

=

ω S 0 = 2 and < 3. Xi i

Q

(12.36)

A different method of insensitive biquadratic design with a simulated L has been recently proposed by Dutta Roy [24]. The basic structure for this is the Rao–Venkateswaran (loc. cit.) circuit of Fig. 12.8 with an additional capacitor C 2 added at the input, as shown in Fig. 12.17. From the fact that Z i = R2 + sC 1 R1 R2 , it is easy to show that   

 V1;z = Vi s 2 + s/ C1 R1 , s 2 / s 2 + s/(C1 R1 ) + 1/(C1 R1 C2 R2 ) . By appropriate linear combinations of V i,1,2 in another OA, one can again obtain any specified biquadratic transfer function. The advantage with respect to the previous scheme is that no isolating UGA is needed in this case, thus leading to component saving. For example, the basic structure of Fig. 12.16 is a high-pass filter with V 2 , as the output; comparing with the previous high-pass circuit, we get a saving of three OAs and five resistors.

12.7 Conclusion From the account of some recent developments given here, it can be concluded that L simulation approach to active filter design is a fairly developed technique, and can be used for biquadratic or higher order filter designs with the important advantages already mentioned. Designing with lossy, but high Q simulated inductors create no additional problems as compared to the design of doubly terminated LC filters with lossy coils.

References

111

References 1. H.J. Orchard, Inductorless filters. Electron. Lett. 2, 224–225 (1966) 2. R.H.S. Riordan, Simulated inductors using differential amplifiers. Electron. Lett. 3, 50–51 (1967) 3. A. Antoniou, Realization of gyrators using operational amplifiers and their use in RC-active network synthesis. Proc. lEE. 166(11), 1839–1850 (1969) 4. T.N. Rao, P. Gary, R.W. Newcomb, Equivalent inductance and Q of a capacitor loaded gyrator. IEEE J. SC 2(1), 32–33 (1967) 5. S.C. Dutta Roy, On operational amplifier simulation of a grounded inductance. Arch. Elektr. Ubertragung. 29(3), 107–115 (1975) 6. S.C. Dutta Roy, Bibliography of inductance simulation by active RC methods. Microelectron. Reliab. 15, 637–639 (1976) 7. M.P. Beddoes, K.R. Morin, Bibliography on inductance simulation by gyrator methods. IEEE Trans. CT 14(1), 107–111 (1967) 8. S.K. Mitra (ed.), Active Inductorless Filters (IEEE Press Book, New York, 1971), pp. 215–219 9. J.A. Miller, R.W. Newcomb, An annotated bibliography on gyrators in network theory: circuits and uses. Technical Report No. R-72-01 (Elec. Eng. Dept., University of Maryland, USA, 1972) 10. A.J. Prestcott, Loss compensated active gyrator using differential input operational amplifier. Electron. Lett. 2, 283–284 (1966) 11. D. Berndt, S.C. Dutta Roy, lnductor simulation using a single unity gain amplifier. IEEE J. SC 4, 161–162 (1969) 12. R.L. Ford, F.E.J. Girling, Active filters and oscillators using simulated inductance. Electron. Lett. 2, 52 (1966) 13. K.R. Rao, S. Venkateswaran, Synthesis of inductors and gyrators with voltage controlled voltage sources. Electron. Lett. 6, 29–30 (1970) 14. A.C. Caggiano, Operational amplifier simulates inductance. Electron 41, 99 (1968) 15. J. Musiedlak, J. McPherson, Some inductance simulators utilizing a single differential operational amplifier, in Proceedings of the 16th Midwest Symposium on Circuit Theory (1973), pp. IX. 8.1-IX.8.10 16. R.P. Sallen, E.L. Key, A practical method of designing RC active filters. IRE Trans. CT 2, 74–85 (1955) 17. P.R. Geffe, RC amplifier resonators for active filters. IEEE. Trans. CT 15(4), 415–419 (1968) 18. M.T. Ahmed, S.C. Dutta Roy, Evaluating the frequency limitations of operational amplifier RC networks: the dominant pole technique and its application to inductance simulators, in Proceedings of the 18th Midwest Symposium on Circuits and Systems, Paper No. R 19.8 (1975) 19. S.C. Dutta Roy, A circuit for floating inductance simulation. Proc. IEEE 62, 521–523 (1974) 20. M.T. Ahmed, Active RC synthesis of single and multivariable network functions using operational amplifiers, Ph.D. thesis, IIT, New Delhi, 1974 21. B. Wise, Active simulation of floating lossy inductances. Proc. IEEE 121, 85–87 (1974) 22. D.P. Leach, S.P. Chan, A generalized method of active RC synthesis. IEEE. Trans. CT 18, 643–650 (1971) 23. S.C. Dutta Roy, M.T. Ahmed, Synthesis of RC active networks using non-ideal simulated inductance. IEEE Trans. Circuits Syst. 21, 250–257 (1974) 24. S.C. Dutta Roy, A versatile second order active filter. Electron. Eng. 46, 64–68 (1974)

Chapter 13

Evaluating the Frequency Limitations of Operational Amplifier RC Networks by the Dominant-Pole Technique

Abstract A general computer-based technique is given for investigating the highfrequency performance of second-order active RC networks employing an arbitrary number of operational amplifiers. It uses the dominant-pole technique for finding deviations in Q and ω0 from their nominal values as a function of the gain bandwidth product of the operational amplifiers. The technique is applied to active RC circuits simulating a nonideal grounded inductance and curves are given for the highest usable frequency for permissible deviation in Q and ω0 for some typical circuits. Keywords Active RC filters · Dominant-pole technique · Frequency limitations

13.1 Introduction The actual performance of an operational amplifier (OA)–RC network differs considerably from that predicted by conventional design, based on the assumption of ideal OA, due to two major reasons, viz. (i) the sensitivity of the network function to the variations of active and passive components from their nominal values and (ii) frequency limitations introduced by the practical OA. Sensitivity has been a subject of extensive research in the past two decades, and well-established methods are now available for its evaluation and minimization [1]. Frequency limitation due to OA is a relatively recent topic; some of the notable contributions in this direction are due to Budak and Petrela [2, 3], and Faulkner and Grimbleby [4, 5]. These are based on one-pole roll-off model of the OA and are particularly suitable for circuits using one OA. Applied to multiple OA networks, both the methods have some inherent limitations; in the method of Budak and Petrela [6], for example, one may have to sacrifice accuracy by neglecting the fourth and higher order terms in the denominator of the transfer function. In the Faulkner–Grimbleby method [5], the developed procedure is to be repeated as many times as are the number of OA’s in the circuit.

Source: Muslim T. Ahmed & S.C. Dutta Roy, “Evaluating the Frequency Limitations of Operational Amplifier RC Networks by the Dominant-Pole Technique and Its Applications to Inductance Simulation,” JIETE, vol 22, pp 703–708, November 1976. © Springer Nature Singapore Pte Ltd. 2020 S. C. Dutta Roy, Topics in Signal Processing, https://doi.org/10.1007/978-981-13-9532-1_13

113

114

13 Frequency Limitations of Op Amp RC Networks

In the present chapter, a general technique, based on the dominant-pole approximation, is developed for the study of a second-order active RC network using an arbitrary number, n, of OA’s. The technique is applied to low-component count, nonideal, grounded, inductance simulator (IS) circuits reported by Dutta Roy [7]. The effect of finite gain bandwidth product (η) of the OAs has been displayed in the form of curves giving the highest usable frequency (ωh ) for prescribed deviations in Q and ω0 from their nominal values.

13.2 Dominant-Pole Technique Consider an active RC network containing n-OAs which realizes, nominally, the second-order transfer function T (s) =

N (s) N (s) = 2 . D(s) s + a1 s + a0

(13.1)

The degree of N(s) is 0, 1 or 2 depending upon the type of filter desired. The two most important performance criteria characterizing Eq. (13.1) are √ √ Q = ( a0 )/a1 and ω0 = a0 .

(13.2)

Identical OAs are assumed, each having an open-loop gain function A(s) = −

η A0 ωa =− s + ωa s + ωa

(13.3)

where A0 = A(0); ω0 is the 3 dB open-loop bandwidth of the OA and η = A0 ωa stands for the gain bandwidth product. When Eq. (13.3) is substituted for each OA gain in the n-OA circuit being considered, it is obvious that the denominator polynomial of the resulting transfer function will be changed to an (n + 2)th-order polynomial. Denoting this by D (s), D  (s) = Bn+2 s n+2 + Bn+1 s n+1 + · · · + B1 s + B0 = (s 2 + a1 s + a0 )(bn s n + bn−1 s n−1 + · · · + b1 s + b0 )

(13.4a) (13.4b)

where, nominally (i.e. when A0 = ∞, ωa = ∞), a1 = a1 , a0 = 0, bn = bn–1 = … = b1 = 0 and b0 = 1. The quadratic factor in Eq. (13.4b) represents the effect of perturbation of the quadratic D(s) due to finite η of the OA’s and is the dominant complex root pair of D (s) (Ghausi [7]; Millman and Halkias [8]). If this factor can be found out, then the effective Q and ω0 denoted by Qe and ω0e , respectively, can be calculated as

13.2 Dominant-Pole Technique

Qe 

115

   a0 /a1 , ω0e  a0

(13.5)

The percentage deviations in Q and ω0 are, therefore, Q = 100(Q e − Q)/Q, ω0 = 100(ω0e − ω0 )/ω0 .

(13.6)

A computer program FLAC (Frequency Limitations of Active Circuits) has been written to evaluate the dominant quadratic factor of D (s) and hence Q and ω0 for a large number of second-order circuits. The results for grounded inductance simulators will be presented in the next section. A flow diagram for FLAC is given in Fig. 13.1. Fig. 13.1 Flowchart of FLAC

Start

Read Q, hn, n Extract n + 2 roots of D¢( s) = O

Generate effective 2nd order equation from dominant polepair Calculate Qe, woe , D Q and Dwo Print Qe, woe , D Q and Dwo

No

Is data complete ? Yes Stop

116

13 Frequency Limitations of Op Amp RC Networks

13.3 Frequency Limitations of Lossy Grounded Inductance Simulators Figure 13.2 shows the various circuits for simulating a grounded nonideal inductance, as considered by Dutta Roy [6], where each voltage amplifier is realized by an OA, with or without suitable resistances. Each of these circuits, assuming a frequencyindependent OA gain, realizes a bilinear RL-impedance of the form Z (s) = H (sτ1 + 1)/(sτ2 + 1), τ1 ≥ τ2

(13.7)

For evaluating the high-frequency performance, we convert each inductance simulator to a tuned circuit by connecting a capacitance C t across the input terminals. Then, nominally, the quality factor Qt and the resonance frequency ωt of the tuned circuit are given by Q t = (H Ct τ1 )1/2 /(H Ct + τ2 )

(13.8)

ωt = (H Ct τ1 )−1/2

(13.9)

The values of H, τ 1 , τ 2 , Qt , ωt and the design equations and constraints for each circuit have been given by Dutta Roy [6]. Taking the frequency dependence of OA gain into account, the polynomial D (s), which determines effective Qt and ωt becomes of the form of Eq. (13.4a). When this is equated to zero, the resulting equation can be written in the form s n+2 + cn+1 , s n+1 + · · · + c1 s + c0 = 0

(13.10)

where cj = Bj /Bn+2 . The values of the coefficients are given in Table 13.1 for each circuit; these are functions of Qt and the normalized gain bandwidth product ηn = η/ωt both forming the input data to FLAC. The coefficients are used for evaluating the dominant complex root pair of Eq. (13.10) and hence finding Qte and ωte and Qt and ωt for a given range of Qt and ηn . Computations using the dominant-pole technique (DPT) were carried out for a large range of Qt and ηn . High values of Q, in general, lead to large element spread, and hence are not realizable if the circuit is to be fabricated in IC form; nevertheless, Q values up to 200 have been taken to demonstrate the frequency limitations at high Q’s. Some of the results are shown in Table 13.2, which gives the maximum η–1 n corresponding to a given Qt and percentage deviation in either Qt or ωt . If all the three quantities Qt , Qt and ωt are specified, then one has to use the lower of the two values of η–1 n corresponding to (Qt , Qt ) and (Qt , ωt ). The highest usable frequency for a particular OA being used in the circuit can easily be found from ωh = η × ηn−1 .

(13.11)

13.3 Frequency Limitations of Lossy Grounded Inductance Simulators R2

(a)

C

K

C

R2

(e)

R2

(h)

R2

R2

(f)

R1

R1

K2

R1

C

R1

- A +

-K C

R2 C

R1

R1

-K

C

K1

K

R1

K1

(g)

R2

(c)

C R1

(d)

R2

(b)

117

-K

C

R2

(i) K1

R1

R2

(j) -K2

K1

R1

C -K2

C

Fig. 13.2 Nonideal grounded inductors obtained with OA’s in: Positive-gain connection a Prestcott circuit, b Berndt–Dutta Roy circuit, c Rao–Venkateswaran circuit, d Caggiano circuit: Infinite-gain connection, e Ford–Girling circuit; Negative-gain connection—circuits derived from f Sallen–Key’s second-order active filter, g by shifting the RC network, h by returning capacitor to amplifier output; Positive and negative-gain connection—circuits derived from i Geffe’s Q-invariant resonator, j Sanderson’s Q-and ω0 -invariant resonator

118

13 Frequency Limitations of Op Amp RC Networks

Table 13.1 Coefficients of Eq. (13.10) for the various circuits of Fig. 13.2 Circuits referred to in Fig. 13.2 A, B C

D E F, G

Coefficient (ct )   c0 = ηn , c1 = ηn /Q t + 1, c2 = ηn + 1 + 2Q 2t /Q t   c0 = ηn2 , c1 = ηn2 /Q t + 2ηn , c2 = ηn2 + 2ηn 1 + Q 2t /Q t + 1, c2 =   2ηn + 1 + Q 2t /Q t   c0 = ηn /2, c1 = ηn /(2Q t ) + 1, c2 = ηn /2 + 1 + 2Q 2t /(2Q t )   c0 = −ηn , c1 = 1 − ηn /Q t + 2Q t ωan · c2 = 1 + 2Q 2t /Q t − ηn p  1 + 4Q 2t ; c0 = ηn / p   c1 = ηn (2 p − 1)/ 2Q t p 2 + 1/ p c2 = [ηn + (2 p − 1)/(2Q t )]/ p

H

p  1 + 4Q 2t ; c0 = ηn

c1 = p/(2Q t )3 + 2Q t / p ηn + 1, c2 = ηn + p/(2Q t )3 + 2Q t ]

I

p  4Q 2t ; c0 = ηn2 / p, c1 = ηn (4ηn Q t + p + 1)/ p 2 ,   c2 = ηn2 + 1 / p + 4ηn Q t ( p + 1)/ p 2 , c3 = [ηn ( p + 1) + 4Q t ]/ p

J

 p  4Q 2t ; c0 = ηn3 , c1 = ηn2 ηn /(2Q t ) + 2ηn Q t / p + p + 1 + 1/p ,

c2 = ηn 2[ηn + ( p + 2)/(2Q t ) + 2Q t (2 p + 1)/ p] + ηn ( p + 2) c3 = ηn [ηn ( p + 2) + (2 p + 1)/(2Q t ) + 2Q t ( p + 2)] + p, c4 = p[ηn + ( p + 1)/(2Q t )] + ηn ( p + 1)

In this sense, Table 13.2 gives universal values for the calculation of ωh . A close glance at the Table indicates that, basically, the circuits of Fig. 13.2 can be classified into three groups depending upon their operational frequency range. Circuits characterized by medium and high-Q realizations at high frequencies will be called class I. Class II circuits are the ones for low Q (