Silicon-Germanium Alloys for Photovoltaic Applications 0323856306, 9780323856300

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Solar Cell Engineering

SILICONGERMANIUM ALLOYS FOR PHOTOVOLTAIC APPLICATIONS AMMAR NAYFEH Khalifa University, Abu Dhabi, United Arab Emirates

SABINA ABDUL HADI University of Dubai, Dubai, United Arab Emirates

Elsevier Radarweg 29, PO Box 211, 1000 AE Amsterdam, Netherlands The Boulevard, Langford Lane, Kidlington, Oxford OX5 1GB, United Kingdom 50 Hampshire Street, 5th Floor, Cambridge, MA 02139, United States Copyright © 2023 Elsevier Inc. All rights reserved. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying, recording, or any information storage and retrieval system, without permission in writing from the publisher. Details on how to seek permission, further information about the Publisher’s permissions policies and our arrangements with organizations such as the Copyright Clearance Center and the Copyright Licensing Agency, can be found at our website: www.elsevier.com/permissions. This book and the individual contributions contained in it are protected under copyright by the Publisher (other than as may be noted herein). Notices Knowledge and best practice in this field are constantly changing. As new research and experience broaden our understanding, changes in research methods, professional practices, or medical treatment may become necessary. Practitioners and researchers must always rely on their own experience and knowledge in evaluating and using any information, methods, compounds, or experiments described herein. In using such information or methods they should be mindful of their own safety and the safety of others, including parties for whom they have a professional responsibility. To the fullest extent of the law, neither the Publisher nor the authors, contributors, or editors, assume any liability for any injury and/or damage to persons or property as a matter of products liability, negligence or otherwise, or from any use or operation of any methods, products, instructions, or ideas contained in the material herein. ISBN: 978-0-323-85630-0 For information on all Elsevier publications visit our website at https://www.elsevier.com/books-and-journals Publisher: Matthew Deans Acquisitions Editor: Stephen Jones Editorial Project Manager: Fernanda A. Oliveira Production Project Manager: Fizza Fathima Cover Designer: Matthew Limbert Typeset by TNQ Technologies

Preface From authors This book covers two key research and scientific topics. One is the growth of new materials to improve the performance of electrical and optical devices. The other is research into devices for clean and renewable energy. This book combines two specific scientific interests of ours: germanium and solar cell device research. This book was a two-year long project starting in April 2020 (early part of COVID-19 pandemic) and was done jointly by the authors, a professor and his former PhD student. It was a tremendous pleasure to work again together on this project, as this book is largely based on our previous joint research work. During our journey with SiliconeGermanium and solar cells based on it, we found that there is a need for a resource where researchers can find all relevant information at one place, whether they need material properties, SiGe growth methods, simulation methodologies, application, and potential uses. By writing this book, we tried to deliver to the research community and academia such single resource.

From Professor Ammar Nayfeh This book combines two specific scientific passions of mine: germanium and solar cell device research. My passion for germanium started at Stanford during my PhD and evolved to solar device research since joining Khalifa University. Being able to research new materials to improve solar cells that will help the world deploy more clean energy is a very strong motivation of mine. For the research done in this book, I want to acknowledge my former PhD student Dr. Ghada Dushaq, for her thesis work on low temperature Ge on Si growth, and, in addition, my former students Dr. Ayman Rezk and Amro Alkhatib for nanomaterial research conducted. This book was a two-year long project and was done jointly with my first PhD student, Dr. Sabina Abdul Hadi. It was a tremendous pleasure to work again with her on this project as she is a dedicated, hardworking, and motivated researcher that shares the same passions about science, solar, and new materials. Dr. Abdul Hadi’s PhD and MSc thesis was the main inspiration for this book. I would like to thank Khalifa University

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and the government of UAE, for their constant support of research, science, and academia and for giving me the opportunity to pursue my scientific passions. Finally, I want to dedicate this book to my former PhD advisor at Stanford, Professor Krishna Saraswat, and MIT collaborators, Professor Eugene Fitzgerald and Professor Judy Hoyt. Without their guidance and support throughout the years, this book would not be possible. Also, this book would not be possible without the love and support of my family. This includes Abuhantash family (Azzam, Amal, Ahmad, and Osama); my parents Munir and Hutaf Nayfeh; my amazing children Laith, Leia, and Zaid; and finally, and most importantly of all, my always supportive and loving wife Lama. She was very patient with me during the writing of this book, and I am truly thankful and blessed (behind every great man is an even greater woman).

From Dr. Sabina Abdul Hadi As a young researcher, having a good reference, be it a book, professor, or a colleague, is a valuable resource that can put you on the right path for success and make your scientific journey full of joy and excitement. With this book, I hope we will give such a reference, where one can find almost everything they need when working with SiliconeGermanium, especially for solar cell applications. This book would not be possible without my coauthor and former PhD advisor, Professor Ammar Nayfeh. He has been my support and guidance ever since our paths crossed more than a decade ago, for which I can never thank him enough. Professor Nayfeh’s enthusiasm and passion for research are infectious and I am deeply grateful for having the opportunity to work with him, a fellow scientist with keen ear for new ideas and eagerness to make them a reality. I would like to thank Khalifa University and the government of UAE for giving me an opportunity to pursue my research interests during my PhD and MSc studies and to the University of Dubai for their support during writing of this book. Furthermore, I would like to thank Professor Judy L. Hoyt and Professor Eugene Fitzgerald, from MIT, whose knowledge, instrumental insights, and technical support have shaped this research. A lot of research work presented in this book was part of our collaborative efforts with MIT team that included fantastic researchers such as Dr. Pouya Hashemi, Gary Riggott, Dr. Nicole DiLello, Dr. Eva Polyzoeva, and Dr. Timothy Milakovich. Last, but closest to my heart, I want to thank my family for their endless love, patience, and support during writing of this book and my entire

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scientific journey. I specially thank my husband Wissam, whose love always had put everything into perspective. Finally, I dedicate this book to my two favorite ladies, my mother Aida and my daughter Lara. My mother has taught me to be independent and ambitious woman and had always been my loudest supporter. My daughter has taught me patience, perseverance, and pure love, to whom I hope to be a good role model and biggest fan through her life journey.

C H A P T E R

9 Other applications of Si1
xGex 9.1 Introduction Researching new materials for various applications has become the key step in the advancement of future electronic and optoelectronic devices. For most electronic and device applications, Si has dominated the material space. For photonics on the other hand, many other materials are used, such as IIIeV, due to their unique optical properties. Finding simple ways to improve traditional Si is an important and more cost-effective way compared to moving to completely new material systems. Si1
xGex proves to be a valuable alloy since the properties of Si can be tuned based on the Ge %. In terms of applications, Si1
xGex is used in transistors, photodetectors, and nanotechnology and can be used as a template for IIIeV integration. It can be argued that the invention of the transistor is the most important of the modern era, being granted a Nobel Prize in Physics in 1956 [1]. It allowed for the electronic and digital explosion we are currently living in. While the first transistors were Ge based, the first chips and large-scale production of transistor were done on Si wafers. To keep improving the device, the transistor needs to scale in size to fit more per chip and increase the drive current. The scaling of the transistor size to keep up with the performance demand started a period of exponential growth. In 1965, Gordon Moore observed that the number of transistors in an integrated circuit was doubling every 2 years. This observation is known as Moore’s law [2]. Fig. 9.1 plots transistor count versus year since the microchip was first introduced, showing the doubling trend [3]. Eventually due to short channel effects that degrade device performance, simple size scaling became essentially impossible [4,5]. As a result, researchers started to look at new materials with higher mobility to increase the drive current and performance of the device. The search for high mobility semiconductor materials naturally leads researchers to

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© 2023 Elsevier Inc. All rights reserved.

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9. Other applications of Si1–xGex

FIGURE 9.1 Moore’s law: the number of transistors on microchips doubles every 2 years. Reproduced with permission from K. Rupp, Our World in Data: 40 Years of Microprocessor Trend Data. Available: https://ourworldindata.org/grapher/transistors-per-microprocessor.

again investigate Ge use in transistors [6,7]. Ge has higher bulk mobility for both electrons and holes. The lattice electron mobility is mn ¼ 1417 cm2/V-s for Si and 3900 cm2/V-s for Ge. The lattice hole mobility is mp ¼ 471 cm2/V-s for Si and 1900 cm2/V-s for Ge. As a result, there is 2.75 times increase in bulk electron mobility, and 4 times increase in bulk hole mobility in germanium as compared to silicon [8]. Table 9.1 shows the enhancement of the lattice mobility of germanium for both electrons and holes. This increase in bulk mobility should ideally correspond to an increase in surface mobility and an ultimate increase in the transistor performance. In addition to the increase, the electron and hole mobilities of germanium are more symmetric compared to silicon. This leads to smaller area pMOS devices in a CMOS inverter cell, compared to Si-based CMOS.

TABLE 9.1 Lattice mobility enhancement of germanium compared to silicon [8].

Electron mobility, mn (cm /Vs) 2

Hole mobility, mp (cm /Vs) 2

Silicon

Germanium

Mobility enhancement

1417

3900

2.753

471

1900

43

9.1 Introduction

183

Fig. 9.2 shows electron and hole mobilities for various semiconductors, where Ge has the highest hole mobility of any known semiconductor [9]. The effect of Ge % on the mobility of Si1
xGex is also interesting to observe. Fig. 9.3 plots experimental electron and hole mobilities versus Ge % [10]. The initial drop at lower Ge % is due to alloy scattering [10]. In addition to the transistor, Si1
xGex alloys are also a key enabler for on-chip optical communications and infrared detection technologies. Each semiconductor material has its characteristic optical bandgap energy Eg, that determines its capabilities in terms of light absorbing over the electromagnetic spectrum. Table 9.2 summarizes some of semiconductor materials which have been used as photodetectors. The cutoff wavelength, bandgap energy, and the operating bandwidth are the main intrinsic properties that determine the operating regime of an optical detector [11]. As can be seen in Table 9.2, the semiconductor with smaller bandgap has higher cutoff wavelength. Therefore, to detect light in telecom band (1.3e1.5 mm), the maximum allowed bandgap is 0.8 eV. So, materials with bandgaps higher than 0.8 eV will not exhibit any photogenerated current. Germanium is very efficient and suitable material for light detection in the near-infrared. Furthermore, it is compatible with Si standard technology due to the possibility of low temperature integration as discussed earlier in Chapter 4. However, its small bandgap produces higher leakage current and somewhat higher thermally generated noise.

FIGURE 9.2 The mobility for silicon, germanium, and a variety of group IIIeV materials is plotted against the bandgap. Note: Filled symbols indicate electrons, and open symbols indicate holes. Reproduced with permission from R. Pillarisetty, Academic and industry research progress in germanium nanodevices, Nature 479 (2011) 324.

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FIGURE 9.3 Measured electron and hole mobilities versus composition in unstrained Si1
xGex alloys. Reproduced with permission from S. Jain, M. Willander, Chapter 5dBandstructure and related properties, in: Semiconductors and Semimetals, Elsevier, 2003, pp. 91e145. TABLE 9.2 Summary of some of semiconductor material intrinsic properties and optical detection regime. Type

E (eV)

l (nm)

Band

Silicon

1.12

1100

Visible

Gallium arsenide

1.42

875

Visible

Germanium

0.66

1800

Near-infrared

Indium gallium arsenide

0.73e0.47

1700e2600

Near-infrared

Indium arsenide

0.36

3400

Near-infrared

IIIeV compound semiconductor materials are widely used for fabricating photodetectors operating in telecom band due to the direct and narrow bandgap of some of those compounds like InGaAs. However, they are not compatible with Si standard technology and are highly expensive. Therefore, the IR photodetection capability and the compatibility with Si technology make Si1
xGex based photodetectors very promising for monolithic integration in CMOS platform. Moreover, using Si1
xGex as a lattice matched template can help with the integration of IIIeV and Si. Lastly, Si1
xGex has interesting new applications in nanotechnology such as quantum dots (QDs) and nanowires. In addition, QDs can be used to enhance the optical properties of Si1
xGex layers. These nanoscale Si1
xGex materials have interesting new properties compared to bulk or grown layers and can open the door for many new applications.

9.2 Si1
xGex in transistor technology

185

9.2 Si1LxGex in transistor technology For the last 20 years, Si1
xGex alloys have been incorporated into modern-day transistor technologies. For years, the focus of many researchers was to improve the channel mobility of Si transistors and increase the overall output current. This drive led researchers to explore the use of the Si1
xGex by improving the mobility in transistors. One way is to use the lattice mismatch to strain the Si channel which will increase the mobility of Si [12]. Strained-Si can be introduced in both global and local methodologies. Fig. 9.4 shows the various cross sections of strained-Si technologies. Of these, the most effective one is the Si1
xGex embedded in the source/drain of the transistor which can introduce compressive strain into Si p-channel [12]. The use of Si1
xGex to strain the channel enhances the mobility and drive current of MOSFETs as shown in Fig. 9.5A and B [13,14]. The full increase in mobility can be achieved if the channel itself is made from pure germanium or very high Ge %. Over the years there has been a lot of research progress in germanium-based transistors. One such work from Stanford University in 2004 shows growth of Ge on Si by MHAH method, then fabrication of Ge-based PMOS transistor [15]. Fig. 9.6A is a schematic cross section of the final device fabricated. Fig. 9.6B is a high-resolution cross-sectional transmission electron microscopy (XTEM) image showing the high-quality GeOxNy/Ge interface and the Ge single-crystal atomic lattice.

FIGURE 9.4 Schematic cross sections of typical bulk strained-Si MOSFET, strained-Si/ SiGe-on-insulator MOSFETs, and strained-Si MOSFETs with SiGe embedded source/drain. Reproduced with permission from S. Takagi, Siliconegermanium (SiGe)-based field effect transistors (FET) and complementary metal oxide semiconductor (CMOS) technologies, in: Electronic and Optical Materials, SiliconeGermanium (SiGe) Nanostructures, Woodhead, 2011, pp. 499e527.

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FIGURE 9.5 (A) Effective electron mobility versus effective electric field for a strainedsilicon on relaxed SiGe FET fabricated using a conventional CMOS process flow. (B) IeV characteristics of short channel FET comparing the current drive of strained-silicon FET with control unstrained-silicon FET. Reproduced with permission from S.P. Wong, Beyond the conventional transistor, Solid State Electron. 49 (5) (2005) 755e762; K. Rim, S. Koester, M. Hargrove, J. Chu, P.M. Mooney, J. Ott, et al., Strained Si NMOSFETs for high performance CMOS technology, in: 2001 Symposium on VLSI Technology. Digest of Technical Papers, 2001, pp. 59e60.

FIGURE 9.6 (A) Cross section of p-MOSFET fabricated using Si Ge gate electrode and LTO/GeO N gate dielectric. Channel region is high-quality single-crystal Ge. (B) Highresolution cross-sectional transmission electron microscopy of GeOxNy/Ge stack showing the Ge single-crystal lattice and high-quality interface. Reproduced with permission from A. Nayfeh, C.O. Chui, T. Yonehara, K.C. Saraswat, Fabrication of high-quality p-MOSFET in Ge grown heteroepitaxially on Si, IEEE Electron. Device Lett. 26 (5) (2005) 311e313.

9.3 SiGe for infrared photodetection

187

Fig. 9.7A and B presents the IeV characteristics of the p-MOSFETs, while Fig. 9.7C shows the substrate and gate current as a function of drain voltage.

9.3 SiGe for infrared photodetection To realize high-performance and low-cost optical links, it is highly desirable to integrate optical components such as the modulator, waveguide, and the photodetector with the advanced silicon transistor technology. The direct epitaxial growth of Ge on Si contributed to great advances in Ge photodetectors. Ge-based photodetectors with its high absorption coefficient in the NIR region, high electron mobility, fast response times, and low power dissipation have revolutionized both

FIGURE 9.7 Measured (A) Is
Vs characteristics, (B) Id
Vd characteristics, and (C) Isub/ Igate
Vd characteristics; Isub is independent of Vg. Reproduced with permission from A. Nayfeh, C.O. Chui, T. Yonehara, K.C. Saraswat, Fabrication of high-quality p-MOSFET in Ge grown heteroepitaxially on Si, IEEE Electron. Device Lett. 26 (5) (2005) 311e313.

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9. Other applications of Si1–xGex

silicon technology and optical communications. Over the years researchers have successfully demonstrated germanium on silicon photodetectors with high responsivities and low dark current. One such work, Okyay et al. from Stanford University, fabricated a Ge on Si infrared photodetector [11]. Fig. 9.8 shows the cross section of the metalesemiconductoremetal (MSM) device fabricated by the MHAH Ge on Si method (detailed in Chapter 4) [11]. Excellent responsivities and external quantum efficiency with 1 V reverse bias operated at 1.55 mm [11]. In addition, some more recent work by Khalifa University, Dushaq et al. details the fabrication of a Ge photodetector on Si [16]. Fig. 9.9 is a schematic diagram of the fabricated Ge photodetector on Si using a twostep method (details in Chapter 4) [16]. In this work, by using an a-Si-H interlayer good optical response is achieved with 1310 nm laser and incident optical power of 2.4 mW [16].

9.4 IIIeV integration using SiGe template Si1
xGex can also be used as a template for growth of IIIeV materials. This is important for IIIeV integration with Si. Some recent work from Dushaq et al. shows a fabricated GaAs photodetector on Si via PECVD grown Ge [17]. Fig. 9.10A shows an SEM cross-sectional image of the GaAs grown layer on top of Ge film. Fig. 9.10B and C shows a schematic diagram and an SEM image (cross section and top view) of the fabricated photodetector, respectively [17]. The XRD scan of the films stack is shown in Fig. 9.11A [17]. Fig. 9.11B shows Raman scattering spectra of the GaAs layers grown on Ge/Si substrates [17]. Fig. 9.11C shows HRTEM images and selected area diffraction pattern at the Ge/GaAs interface. Fig. 9.12A shows the

FIGURE 9.8 Cross section of metalesemiconductoremetal photodetector fabricated on MHAH Ge layer grown on Si starting substrate. Reproduced with permission from A.K. Okyay, A. Nayfeh, K.C. Saraswat, T. Yonehara, A. Marshall, P.C McIntyre, High-efficiency metale semiconductoremetal photodetectors on heteroepitaxially grown Ge on Si, Opt. Lett. 17 (2006) 2565e2567.

9.4 IIIeV integration using SiGe template

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FIGURE 9.9 Ge metalesemiconductoremetal based photodetector structure by two-step PECVD growth schematic representation. Reproduced with permission from G.H. Dushaq, M.S. Rasras, A.M. Nayfeh, Metal-germanium-metal photodetector grown on silicon using low temperature RF-PECVD, Opt. Express, 25 (25) (2017) 32110e32119.

FIGURE 9.10 (A) SEM cross section of GaAs on Ge/Si with the inset showing EDS of the film constituent; (B) the GaAs MSM based photodetector structure schematic representation; (C) top view of SEM image of the fabricated detector. Reproduced with permission from G.H. Dushaq, A.M. Nayfeh, M.S. Rasras, Complementary metal oxide semiconductor (CMOS) compatible gallium arsenide metalesemiconductoremetal photodetectors (GaAs MSMPDs) on silicon using ultra-thin germanium buffer layer for visible photonic applications, J. Appl. Phys. 126 (2019) 193106.

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FIGURE 9.11 (A) Rocking curves of GaAs films on the Ge/Si wafer with the inset showing multipeak Gaussian fit to determine the peaks’ position; (B) active TO and LO Raman modes of the GaAs layer on the Ge/Si substrate at laser excitations of 488 and 785 nm (the table depicts the TO and LO phonon mode positions); (C) HRTEM image at the GaAs/Ge interface along with their SADPs. Reproduced with permission from G.H. Dushaq, A.M. Nayfeh, M.S. Rasras, Complementary metal oxide semiconductor (CMOS) compatible gallium arsenide metalesemiconductoremetal photodetectors (GaAs MSMPDs) on silicon using ultra-thin germanium buffer layer for visible photonic applications, J. Appl. Phys. 126 (2019) 193106.

electrical connection of the MSM GaAs on Ge detector for IeV measurements. Fig. 9.12B shows the behavior of dark IeV curves of devices fabricated with/without Al2O3 interlayers. The detectors fabricated without the interlayers exhibit w20 times higher leakage current at 1 V compared to the ones with passivation [17]. Thus, this passivation technique significantly enhances the GaAs surface quality and results in a low measured dark current of 82 nA at 1 V for a detector radius of 70 mm. Additionally, the devices show a relatively uniform dark IeV behavior and a good Ion/Ioff ratio [17]. The optical response of the detectors, along with their dark state, is shown in Fig. 9.13. The detectors demonstrate a more than three orders of magnitude difference between the on and off state at 3 V bias.

9.4 IIIeV integration using SiGe template

191

FIGURE 9.12 (A) Top electrical connection of GaAs metalesemiconductoremetal and (B) the rectifying behavior of IeV curves at the MS junction with/without the Al2O3 interlayer. Reproduced with permission from G.H. Dushaq, A.M. Nayfeh, M.S. Rasras, Complementary metal oxide semiconductor (CMOS) compatible gallium arsenide metalesemiconductoremetal photodetectors (GaAs MSMPDs) on silicon using ultra-thin germanium buffer layer for visible photonic applications, J. Appl. Phys. 126 (2019) 193106.

FIGURE 9.13 IeV characteristics of GaAs metalesemiconductoremetal detectors under 850 nm laser illumination along with their dark state. Reproduced with permission from G.H. Dushaq, A.M. Nayfeh, M.S. Rasras, Complementary metal oxide semiconductor (CMOS) compatible gallium arsenide metalesemiconductoremetal photodetectors (GaAs MSMPDs) on silicon using ultra-thin germanium buffer layer for visible photonic applications, J. Appl. Phys. 126 (2019) 193106.

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9. Other applications of Si1–xGex

The results show that GaAs photodetectors can be integrated on Si epitaxially using lattice matched Ge. This idea can be extended to other IIIeV layers to match with Si1
xGex alloys with matched Ge %.

9.5 SiGe in nanotechnology Apart from normal bulk growth technologies, the use of Si1
xGex in nanotechnology is also on the rise. The properties of Si1
xGex germanium QDs are not fully understood yet and that open the door to many exciting breakthroughs. In general, with QDs, the ability to control their location for the specific application is needed. In research by El Khatib et al. a template is made on Si using the nanoindentation and using the unique lattice mismatch and strain between Ge and Si [18]. In this work, ordered 2 nm Ge QDs on Si are achieved [18]. Nucleation site matrices were defined using nanoindentation for the Ge QDs to reside in. Subsequently, a heating treatment was applied to start the Ge self-assembly process. A schematic of the fabrication process described in this work is shown in Fig. 9.14AeC [18].

FIGURE 9.14 Schematic of the quantum dot (QD) assembly process. (A) Nanoindentation phase. (B) Ge nanolayer physical deposition and heat application. (C) QD selfassembly after the deposition and heat treatment. Reproduced with permission from A. Alkhatib, A. Nayfeh, A complete physical germanium-on-silicon quantum dot self-assembly process, Sci. Rep. 3 (2013) 2099.

9.5 SiGe in nanotechnology

193

As shown in Fig. 9.15A and B, two matrices of indentation are used: 10  10 mm and 5  5 mm matrix. The indents on the surface showed trapezoidal pyramidal shapes after the unloading process [18]. Height data of the Si/Ge surface before and after annealing over a part of the 5  5 mm indentation matrix are shown in Fig. 9.16AeC [18]. The Ge QDs formed in the indentation sites only. The resulting structure of indentations with the precise formation of Ge QDs only inside the indentation grooves is shown in a 3D representation restructured from the height imaging using AFM (Fig. 9.16C) [18]. In addition, nanotechnology can be used to improve the properties of SiGe. In recent work, by Rezk et al. 3 nm Si nano is coated on the surface of thin-film PECVD growth Ge to reduce its reflectivity [19]. Fig. 9.17A shows transmission electron microscopic image of individual Si NPs. The Si NPs solution is dominated by bright red-orange luminescence under 365 nm irradiation. The drop casting process on PECVD Ge thin-films is depicted in Fig. 9.17B. Fig. 9.18AeF shows pictures of the PECVD Ge thinfilms under UV with Si NPs. Fig. 9.19 shows XTEM image of PECVD Ge substrate after drop casting the Si NPs [19]. The Si NPs layer with a thickness w30 nm can be observed in Fig. 9.19B using parallel electron energy loss spectrometer [19]. Reflectivity measurements of the coated PECVD Ge sample are studied. Those are depicted in Fig. 9.20 along with the spectra of the uncoated sample. A prominent decrease in R is seen in the PECVD Ge and drop volume increases [19].

FIGURE 9.15 Nanoindentation matrices of different spacing sizes. (A) 50  50 mm indentation matrix of w5 mm spacing and 10 nm depth. (B) 535 mm indentation matrix of w500 nm spacing and w10 nm depth. Reproduced with permission from A. Alkhatib, A. Nayfeh, A complete physical germanium-on-silicon quantum dot self-assembly process, Sci. Rep. 3 (2013) 2099.

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9. Other applications of Si1–xGex

FIGURE 9.16 Formation of quantum dot (QD) structures inside indentation sites. (A) Indentation sites after growth of Ge 1 nm layer prior to annealing. (B) Indentation sites after annealing process with the Ge QDs apparent from the height image. (C) 3D AFM data plot of the matrix QD structure. Reproduced with permission from A. Alkhatib, A. Nayfeh, A complete physical germanium-on-silicon quantum dot self-assembly process, Sci. Rep. 3 (2013) 2099.

FIGURE 9.17 (A) Transmission electron microscopic image of individual Si NPs. Inset shows the Si NPs solution can be seen to be dominated by bright red-orange luminescence under 365 nm irradiation and the self-assembly on a surface of same size (emitting same band) nanoparticles. (B) Graphic depicting the step-by-step casting method of Si NPs on PECVD grown Ge thin-film. Reproduced with permission from A. Rezk, S.A. Hadi, J.M. Ashraf, W.A. Aisha Alhammdi, A. Kumar, G. Dushaq, et al., Strong reduction in Ge film reflectivity by an overlayer of 3 nm Si nanoparticles: implications for photovoltaics, ACS Appl. Nano Mater. 4 (5) (2021) 4602e4614.

9.5 SiGe in nanotechnology

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FIGURE 9.18 Optical microscope images under UV of the (A) uncoated PECVD Ge thinfilms and coated films with Si NPs at a drop volume of (B) 100, (C) 200, (D) 300, (E) 400, and (F) 500 mL. Reproduced with permission from A. Rezk, S.A. Hadi, J.M. Ashraf, W.A. Aisha Alhammdi, A. Kumar, G. Dushaq, et al., Strong reduction in Ge film reflectivity by an overlayer of 3 nm Si nanoparticles: implications for photovoltaics, ACS Appl. Nano Mater. 4 (5) (2021) 4602e4614.

FIGURE 9.19 (A) Cross-sectional transmission electron microscopy (XTEM) image of a Pt coated substrate. Showing the two-step Ge thin films growth and five coats of 100 mL of Si NPs. (B) Electron energy loss spectrometer (EELS) compositional mapping of the stack. Reproduced with permission from A. Rezk, S.A. Hadi, J.M. Ashraf, W.A. Aisha Alhammdi, A. Kumar, G. Dushaq, et al., Strong reduction in Ge film reflectivity by an overlayer of 3 nm Si nanoparticles: implications for photovoltaics, ACS Appl. Nano Mater. 4 (5) (2021) 4602e4614.

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9. Other applications of Si1–xGex

FIGURE 9.20 Reflectance of NIReViseUV spectra for coated PECVD Ge. The samples are coated at drop volumes of 100, 200, 300, 400, and 500 mL. Inset shows reflectance for bulk Ge compared to PECVD grown Ge. Reproduced with permission from A. Rezk, S.A. Hadi, J.M. Ashraf, W.A. Aisha Alhammdi, A. Kumar, G. Dushaq, et al., Strong reduction in Ge film reflectivity by an overlayer of 3 nm Si nanoparticles: implications for photovoltaics, ACS Appl. Nano Mater. 4 (5) (2021) 4602e4614.

9.6 Summary In conclusion Si1
xGex has uses in several important applications apart from photovoltaics. For transistors, they are used to create strain in Si due to the lattice mismatch that increases the mobility and the performance. In addition, the Si channel can be made with Si1
xGex for even a higher increase in mobility. For photonics, Si1
xGex is key for integration of photodetector with advanced Si technology. This will help enable on-chip optical links. Also, Si1
xGex can be used as template for integration of IIIeV with Si, due to the variable lattice constant. This allows for IIIeV photonics and electronics integration with Si. Also, recently Si1
xGex

References

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based QDs and nanomaterials can unlock some new and exciting properties. New innovative methods are reported for a self-assembly process to control the nanomaterial location. In addition, the performance of the Si1
xGex can be altered by adding Si QDs or possibly other materials. Moreover, Si1
xGex alloys are a robust and important material that can be used to improve many electronic, photonic, and nanotechnology-based devices and as a fabrication template to integrate other key materials. Finally, these applications in addition to photovoltaics make Si1
xGex alloys a vital material for the future of many devices allowing for continuation of technological advancements.

References [1] The Nobel Prize. Available: https://www.nobelprize.org/prizes/physics/1956/ summary/. [2] R.R. Schaller, Moore’s law: past, present and future, IEEE Spectr. 34 (6) (1997) 52e59. [3] K. Rupp, Our World in Data: 40 Years of Microprocessor Trend Data, Available: https://ourworldindata.org/grapher/transistors-per-microprocessor. [4] T.N. Nguyen, J.D. Plummer, Physical mechanisms responsible for short channel effects in MOS devices, in: International Electron Devices Meeting, 1981, pp. 596e599. [5] D.J. Frank, R.H. Dennard, E. Nowak, P.M. Solomon, Y. Taur, H.-S.P. Wong, Device scaling limits of Si MOSFETs and their application dependencies, Proc. IEEE 89 (3) (2001) 259e288. [6] K. Saraswat, C.O. Chui, T. Krishnamohan, D. Kim, A. Nayfeh, A. Abhijit Pethe, High performance germanium MOSFETs, Mater. Sci. Eng. B 135 (3) (2006) 242e249. [7] K.C. Saraswat, C.O. Chui, T. Krishnamohan, A. Nayfeh, P. McIntyre, Ge based high performance nanoscale MOSFETs, Microelectron. Eng. 80 (2005) 15e21. [8] B. Streetman, S. Banerjee, Solid State Electronic Devices, Prentice Hall, 1998. [9] R. Pillarisetty, Academic and industry research progress in germanium nanodevices, Nature 479 (2011) 324. [10] S. Jain, M. Willander, Chapter 5dBandstructure and related properties, in: Semiconductors and Semimetals, Elsevier, 2003, pp. 91e145. [11] A.K. Okyay, A. Nayfeh, K.C. Saraswat, T. Yonehara, A. Marshall, P.C. McIntyre, Highefficiency metalesemiconductoremetal photodetectors on heteroepitaxially grown Ge on Si, Opt. Lett. 17 (2006) 2565e2567. [12] S. Takagi, Siliconegermanium (SiGe)-based field effect transistors (FET) and complementary metal oxide semiconductor (CMOS) technologies, in: Electronic and Optical Materials, SiliconeGermanium (SiGe) Nanostructures, Woodhead, 2011, pp. 499e527. [13] S.P. Wong, Beyond the conventional transistor, Solid State Electron. 49 (5) (2005) 755e762. [14] K. Rim, S. Koester, M. Hargrove, J. Chu, P.M. Mooney, J. Ott, et al., Strained Si NMOSFETs for high performance CMOS technology, in: 2001 Symposium on VLSI Technology. Digest of Technical Papers, 2001, pp. 59e60. [15] A. Nayfeh, C.O. Chui, T. Yonehara, K.C. Saraswat, Fabrication of high-quality pMOSFET in Ge grown heteroepitaxially on Si, IEEE Electron. Device Lett. 26 (5) (2005) 311e313. [16] G.H. Dushaq, M.S. Rasras, A.M. Nayfeh, Metal-germanium-metal photodetector grown on silicon using low temperature RF-PECVD, Opt. Express 25 (25) (2017) 32110e32119.

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[17] G.H. Dushaq, A.M. Nayfeh, M.S. Rasras, Complementary metal oxide semiconductor (CMOS) compatible gallium arsenide metalesemiconductoremetal photodetectors (GaAs MSMPDs) on silicon using ultra-thin germanium buffer layer for visible photonic applications, J. Appl. Phys. 126 (2019) 193106. [18] A. Alkhatib, A. Nayfeh, A complete physical germanium-on-silicon quantum dot selfassembly process, Sci. Rep. 3 (2013) 2099. [19] A. Rezk, S.A. Hadi, J.M. Ashraf, W.A. Aisha Alhammdi, A. Kumar, G. Dushaq, et al., Strong reduction in Ge film reflectivity by an overlayer of 3 nm Si nanoparticles: implications for photovoltaics, ACS Appl. Nano Mater. 4 (5) (2021) 4602e4614.

C H A P T E R

8 Cost benefits of Si1
xGex for III-V growth 8.1 Solar PV cost considerations Cost is very important parameter when discussing renewable energy (RE), as it gives an idea of the feasibility of a certain technology. Solar photovoltaic (PV) costs have been steadily declining over the years, with global weighted-average levelized cost of electricity (LCOE) of utilityscale (PV) plants reducing by 85% between 2010 and 2020, from USD 0.381/kWh to USD 0.057/kWh in 2020 [1]. Reducing costs have made solar PV a competitive source of energy, contributing to a steady increase in global capacity of installed PV systems. According to data from IRENA [2,3], global RE capacity increased from 1348 GW in 2010 to w2800 GW in 2020. From this, solar PVs have contributed about 700 GW to global renewable capacity. Fig. 8.1 shows total solar PV capacity in the world over the years [3,4]. The cost of PV solar energy depends on the amount of generated power at the site, which is a function of the PV panel conversion efficiency as well as the solar irradiation and conditions at the installation site. Some of the key drivers for the steady decline in costs of PV module are improved module efficiency, reduced labor costs, and optimization of manufacturing processes. Furthermore, installation and maintenance costs have also been declining over the years, mostly due to increased installers experience and smaller installation area per peak capacity, due to modules improved conversion efficiency. In 2020, balance of system (BoS) costs (installation-related costs but excluding inverters) accounted for about 65% of total system costs [1]. Module prices are often reported in terms of module’s peak capacity, Wp. PV technology learning curve indicates that price of

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© 2023 Elsevier Inc. All rights reserved.

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FIGURE 8.1

World total solar photovoltaic capacity over the years [3,4].

installed module drops by w20% every time global cumulative PV production is doubled [5,6] as shown in Fig. 8.2. However, even though cost of PV generated electricity has been reducing steadily in past years, the price of PV generated electricity is still in the same range as the price of electricity generated by fossil fuels, and

FIGURE 8.2 Solar PV module cost learning curve for crystalline silicon. Data from International Rewneable Energy Agency (IRENA), Solar photovoltaic summary charts. Available: https:// www.irena.org/costs/Charts/Solar-photovoltaic. (Accessed 2022).

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in some parts of the world it may be even higher, as shown in International Energy Agency 2020 cost estimate report [7]. Fig. 8.3 (reproduced from Ref. [7]) compares the estimated electricity generation costs for different technologies. While utility-scale PV median cost is competitive with fossil fuelebased energy, there is large variance in the data, and residential PV costs are still way above the costs of fossil fuels. These results indicate that there is still the need for further reductions in order to make PV financially competitive source of energy on a global scale. One way to lower the price of PV electricity is by improving the efficiency of a solar cell and PV module, thus reducing module area and electric connections related costs as well as the cost of land used, effectively lowering BoS costs, that currently make a large portion of the cost for PV generated electricity. Multi-junction (MJ) solar cells have the highest reported efficiency, but they are still too expensive for commercial, utility, or residential use. Hence there is room for improvement in manufacturing methods and material used in order to lower the costs. Furthermore, lab-reported solar cell efficiencies are usually higher than efficiency in installed PV system. This means there is another avenue for cost reduction due to PV system losses. To know feasibility of the installed

FIGURE 8.3 Estimated levelized cost of electricity (LCOE) by technology. Note: Values at 7% discount rate. Box plots indicate maximum, median, and minimum values. The boxes indicate the central 50% of values, i.e., the second and the third quartile. Reproduced with permission from International Energy Agency & Organisation for Economic Co-operation and Development/Nuclear Energy Agency, Projected costs of generating electricity, 2020 edition, 2020. Available: https://iea.blob.core.windows.net/assets/ae17da3d-e8a5-4163-a3ec-2e6fb0b5677d/ Projected-Costs-of-Generating-Electricity-2020.pdf. (Accessed 2022).

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PV system, average annual electricity generation must be calculated so that overall system cost is amortized over the lifetime of the system and expressed in terms of $/kWh, which is also called LCOE.

8.1.1 Comparative levelized cost of electricity by PV plant Cost of electricity generated by PV power plant can be divided into three main categories [8]: module cost, system cost, and local conditions. PV module costs are mainly due to solar cell production and assembly costs, and they depend on the area of the cell used in a module. The cost of the module and required number of cells within the module decrease with increasing efficiency of the cell. The PV system cost, which is also called BoS cost, includes costs of installation, cabling and connections, substructure, inverters, monitoring, and other engineering and construction related costs [8]. Operation and maintenance costs are also largely covered in BoS costs. Finally, cost of electricity generation also depends on local conditions due to natural and social settings. The weather conditions at installation site can significantly affect the solar cell’s output power and influence how the entire PV system and maintenance are organized. The effect of weather conditions on solar cell’s power is defined by site-specific solar intensity, S (kW/m2). Furthermore, social factors influencing the market price of electricity include government subsidies, that are used in order to encourage development of sustainable energy sources. The LCOE is a net present value of total life cycle costs of the solar PV installed system divided by the amount of energy produced over the system life [9]: LCOE ¼

Total Life Cycle Cost Total Lifetime Energy Production

(8.1)

Taking into consideration the money value depreciation, r (discount rate), and PV system degradation, d, over the N years, the LCOE can be expressed in general terms as [10,11]: N P

Cn ð1 þ rÞn LCOE ¼ n¼1 N P Qn ð1
dÞn

(8.2)

n¼1

where C includes all related costs, such as levelized initial cost (capital investment), maintenance and labor, BoS costs, etc., while Q represents yearly electricity generation. The equation of LCOE can be further modified based on the level of detail needed to be considered in the calculation. Cost can be divided into PV module cost, Cm

8.2 Multi-junction solar cells cost considerations

153

($/m2), area-related BoS including installation costs, Cb ($/m2), inverter cost, Ci ($/kW), and O&M operation costs, while energy production is dependent on PV system efficiency, hsystem, as well as site-specific average annual solar intensity (kWh/(m2 day)) [9e15]. LCOE can also consider money inflation rate, taxes and subsidies, inverter lifetime, etc. The cost analysis considerably changes depending on application, such as installation in PV power plant (utility scale), rooftop stand-alone PV modules, or space applications. For cost analysis presented in this chapter, we use simple form of LCOE to compare processing costs of III-V on Si versus III-V on GaAs technology, without taking into consideration the taxes, interest, or discount rate. Moreover, the cost of III-V/Si MJ solar technology is calculated using the manufacturing cost data available in literature which assumes fabrication taking place in the United States. Thus, manufacturing costs assume tax rate, wages, and depreciation rates characteristic for the United States, while manufacturing scale is assumed to be 500 MW [16]. More details on the assumptions used will be listed later in the specific case study.

8.2 Multi-junction solar cells cost considerations MJ solar cells produced from III-V materials have the highest efficiencies [17], but they are too costly compared to single-junction (SJ) Si solar cells. For comparison, the best reported crystalline Si SJ solar cell has efficiency of w27%, while best SJ solar cell is made of GaAs and has efficiency of 29%. Furthermore, highest efficiency for MJ solar cell is reported for 5- and 6-junction III-V based solar cells (w39% under 1 sun). Most commercially available MJ solar cells are fabricated on Ge or GaAs wafers which serve as substrates or carriers, which is partly the reason for the high production costs of MJ solar cells [18]. Even though MJ solar cells can reach conversion efficiencies as high as 47%, they are still limited to niche applications due to their high cost compared to SJ Si cells. To help MJ solar cell penetrate global PV market, decreasing manufacturing costs ($/W) of MJ solar cells is one of the key factors as it will accentuate the benefits of their high conversion efficiencies. One way to reduce production cost of MJ solar cells is to integrate their production into existing silicon-based manufacturing technology. This would allow large-scale production, such as manufacturing MJ solar cells at 200 mm wafer level, which can reduce $/Wp costs considerably. Besides the lower cost and compatible bandgap, the mechanical strength of silicon is higher compared to GaAs or Ge carrier, which can facilitate the higher yield and larger throughput of manufacturing process.

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MJ solar cells can be grouped into bonded and monolithic cells. For monolithic MJ solar cells, subcells are fabricated on top of each other, often by epitaxial growth of individual layers. Subcells in monolithic MJ solar cells are connected in series, usually via tunnel junction. Due to series connection, current in monolithic cells is limited by the smallest current of one of the subcells, thus current matching is necessary for optimum operation. Furthermore, monolithic based cells are subjected to lattice-matching constraints, which are needed to reduce dislocation defects and maintain high quality material [19,20]. Most commercial monolithic MJ solar cells, such as w31% efficient GaInP/GaAs/Ge triplejunction solar cell by Spectrolab Inc. [21], have the bottom cell placed in the carrier. Depending on how many junctions there are in a cell, substrate carriers are typically Ge or GaAs, which are very costly. In an effort to reduce MJ solar cell costs, researchers are utilizing the growth of III-V inverted metamorphic multi-junction (IMM) solar cells on latticematched substrates (i.e., GaAs or Ge), followed by epitaxial lift-off (ELO) and bonding onto a flexible substrate or another single- or multijunction solar cell. By this method, expensive Ge or GaAs substrate wafers can be reused again for future cell growth, subject to few preparatory fabrication steps. Currently the world record laboratory efficiency for dual-junction (DJ) solar cells is w32.9% for monolithic GaInP/GaAs thin-film cell fabricated by NREL [17,22,23]. As researchers recognized financial impact of using expensive GaAs or Ge substrates for bottom cell, recent years have seen reports of III-V on Si MJ solar cells, fabricated either monolithically or by mechanical stacking/bonding. Some notable DJ cells are monolithic GaAsP/Si with efficiency of w23.4% and mechanically stacked GaAs/Si cells with efficiency of w32.8%, both fabricated by NREL [17]. Even though GaAsP/Si has theoretically bandgap combination close to ideal compared to GaAs/Si cell, the lattice mismatch constraints that the monolithic growth suffers result in lower efficiency. In mechanically bonded MJ solar cells, there is no lattice-matching constraint since all the subcells are fabricated separately and then bonded together, including bonding of monolithic IMM solar cell to another single- or multi-junction cell. However, ELO is essential for the majority of solar cells that utilize mechanical bonding as one of its fabrication steps. The fabrication of both monolithic and bonded MJ solar cells has several challenges. The III-V based bonded MJ cells all involve some form of layer transfer, where layers of active cells are removed from carrier substrate (usually a GaAs or Ge) and are later bonded with another, separately fabricated, cell. There are many techniques to achieve layer transfer, and all come with challenges. Research attempts in layer transfer include chemical ELO, mechanical spalling, laser lift-off, and ion cutting [24].

8.2 Multi-junction solar cells cost considerations

155

In ELO process, a sacrificial layer, that is embedded in the epi-stack, is removed using suitable chemical etchants, allowing the layers on top of the sacrificial layer to be transferred to other substrates. In this process, the growth substrate (usually Ge or GaAs of III-V epi-layers) is preserved and can be reused. In ELO of III-V based solar subcells, hydrofluoric acid (HF)-based chemistry is used for lateral etch of the sacrificial layer that is grown between the substrate and active cell area. The challenge in this process is that ELO step has a slow etch rate of w0.3 mm/h when it is only based on the diffusion [25] and use of HF introduces the roughness on the released layer and the carrier substrate [24]. In order to be able to reuse carrier substrate for further growth, mechanical polishing and surface treatment are then required. Researchers are exploring different sacrificial layers that allow use of chemicals, such as hydrochloric acid, which leave less damage on carrier substrates and released layers [26]. Furthermore, the slow lift-off rate is due to the slow HF diffusion. And even a greater challenge is that the etch process comes to a standstill because of the accumulation of etch by-products AlF3 [25]. Slow release of active layers is not commercially viable, and researchers have investigated different ways to increase the etch rates of sacrificial layer, such as: weight-assisted, surface tension force-assisted, or roller-assisted ELO techniques [24]. For example, the lift-off rate as high as 30 mm/h can be achieved by applying a pulling force on the released layer [25]. Nevertheless, using the kinetic-assisted ELO techniques is still not commercially available and the true costs of such systems are difficult to estimate currently. Since for mass production it is necessary to have fast processing steps, the commercial production of III-V based solar cells using ELO assisted layer transfer involves wafer dicing or patterning into small areas, few millimeters in size. It was proposed that patterned structures can be used to assist with faster lift off [27,28]. For DJ solar cells, silicon has close to an ideal bandgap for a bottom cell, where top cell material should have a bandgap of w1.7 eV [29,30]. Materials with a bandgap that can be utilized for the top cell of Si-based DJ solar cell can be sourced from III-V material alloys. While III-V/Si DJ solar cells are still not readily available in the market, the highest reported efficiency at laboratory level testing is w32.8% for mechanically stacked GaAs on Si solar cells with four terminals [17], where top III-V cell is grown using metal-organic vapor phase deposition (MOCVD) on GaAs substrate [31]. Expensive GaAs or Ge substrates are used in order to maintain high-quality epitaxial layers. However, high-quality III-V layers can also be grown on inexpensive Si substrates by the use of graded buffer layers, such as Si1
xGex [32,33] or GaAs1
yPy [34e36]. Use of those graded buffer layers on Si substrate reduces the effects of lattice mismatch between Si and III-V material [37]. Graded Si1
xGex buffer layers are usually few micrometers thick, thus introduce significant optical losses if used in

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xGex

monolithic DJ solar cell (III-V on Si) [38]. The graded buffer layer composition and thickness will vary depending on the starting substrate and the III-V alloy used for the top cell. Hence, better solution is bonding III-V top and Si bottom cell, where III-V top cell was grown on Si1
xGex/Si or GaAs1
yPy/Si substrates and released from it by an ELO. In this approach, top III-V cell can be fabricated on Ge, GaAs, or Si substrates with lattice-matched graded buffer layers and later reused, increasing cost-effectiveness of the process. In order to address the abovementioned industry challenges and lower costs of fabrication of MJ solar cells using III-V epitaxy on Si, recent years showed increased number of proposed novel techniques for release of III-V layers from its inexpensive Si substrate, such as step-cell structure [39], graphene-assisted layer release/transfer technique [40], or layer-resolved mechanical separation technique [41]. Our research group (formed by collaboration between Khalifa University (formerly Masdar Institute) and MIT) earlier proposed the GaAsP/Si DJ step-cell [39,42] where GaAsP top cell is grown on Si substrates using graded Si1
xGex buffer layer. In the step-cell design, the top cell is patterned in a way that the bottom cell and/or carrier are exposed to etch chemistry, as shown in Fig. 8.4. In this way, the step-cell patterns can assist in faster ELO process, since only few hundreds of micrometers are to be etched, allowing the growth of III-V top cell to be grown on a separate substrate and then bonded with Si bottom cell [28]. Furthermore, step-cell features can be used to optimize performance of the DJ cell [30]. In the cost consideration here, the effect of substrate reuse is analyzed, even when high-quality crystalline Si wafers are used for the growth of Si1
xGex buffer layers. This is needed for the growth of highquality III-V layers on top. For comparison, the cost of commercially available InGaP/GaAs/Ge 3J monolithic solar cells is also estimated. The cost comparison between monolithic cells and cells based on mechanical bonding and substrate reuse has important value for MJ solar cell industry, mainly owing to the price difference between Ge (w$150/ wafer [43]) and Si ($1e2/wafer for bottom Si cell and w$0.1/cm2

FIGURE 8.4 Illustration of two terminal III-V/Si dual-junction step-cell with III-V top cell mechanically stacked onto bottom Si cell, connected via tunnel diode (TD).

8.2 Multi-junction solar cells cost considerations

157

[44, p. 458] for high-quality single crystalline needed Si for III-V growth). Even though high-quality III-V solar cells with low defect density can be grown on Ge or GaAs wafers, resulting in high efficiency devices [45], high costs of those substrates are limiting wide commercial use of III-V. However, recent work on III-V growth on Si1
xGex/Si wafers [46,47] and on GaAsP graded layers grown on Si substrates [48] both have yielded high-quality III-V cells, providing a potential for lowering the costs of MJ solar cells. In cost analysis presented here, we analyze the range of future anticipated conversion efficiencies, where clear trade-off between the material quality and the cost is observed. Finally, a sensitivity cost analysis is carried out while considering midterm and long-term scenarios with different conditions and fabrication steps anticipated.

8.2.1 III-V/Si dual-junction step-cell III-V/Si mechanically bonded DJ step-cell structure shown in Fig. 8.4 is used as basis for cost analysis presented in this chapter. Fig. 8.5 illustrates the details of all layers within the top III-V cell, which are used to estimate the cost of fabrication of III-V/Si DJ cell [28]. Top GaAsP and bottom Si cells are connected in series using a tunnel diode (TD). The top cell consists of a 1.5-mm-thick GaAs0.75P0.25 active layer, 50-nm-thick InGaP window and back surface field (BSF) layers, and 100-nm-thick heavily doped GaAsP contact layer underneath the metal contacts (not shown in Fig. 8.5). As discussed earlier, the top cell in step-cell design can be patterned in the shape of “fingers,” such that the area (Atop) is smaller than the area of the bottom cell (Atotal). These fingers can help facilitate faster lift-off and can be designed narrow enough to allow for a quick chemical lift-off

FIGURE 8.5 Details of bonded GaAsP/Si dual-junction step-cell used for cost analysis [28].

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xGex

process, relying only on HF-based chemistry and without the use of any other additional equipment. In a step-cell, ratio between the total area of the cell (Atotal) and area of the top cell (Atop) can be adjusted such that performance of the III-V/Si DJ cell is optimized. The Atotal/Atop optimum ratio would depend on the top cell bandgap, active layer thickness, or the number of optical losses. Fig. 8.6 shows the detailed balance theoretical upper efficiency limit of Sibased DJ step-cell as a function of Atotal/Atop ratio and the bandgap of the top cell [30]. The results in Fig. 8.6 show that a maximum efficiency of w45% is achievable for DJ solar cell with Atotal/Atop ¼ 1 (conventional solar cell) if the top cell has bandgap of w1.75 eV. However, analysis shows that for top cell materials whose bandgap is between w1.5e1.9 eV, it is possible to achieve efficiencies of w40%e45% for Atotal/Atop ratio larger than 1 is used. This implies that material for the top cell should be carefully selected such that optimum Atotal/Atop ratio is greater than 1 and a step-assisted ELO method can be used to enable high lift-off throughput without sacrificing the optimum device efficiency. For cost reduction, III-V top cell should be grown on high-quality single crystalline (c-Si) carrier. All the layers above bottom Si cell shown

FIGURE 8.6 Detailed balance efficiency upper limit of DJ Si-based step-cell as a function of top cell bandgap and Atotal/Atop ratio under AM 1.5G illumination [30,39]. Figure reproduced with permission from E. Yablonovitch, T. Gmitter, J.P. Harbison, R. Bhat, Extreme selectivity in the lift-off of epitaxial GaAs films, Appl. Phys. Lett. 51 (26) (1987) 2222.

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159

in Fig. 8.5 are grown in inverted order on Si substrate via graded Si1
xGex buffer layer (Fig. 8.7A), so that they can be lifted off and transferred to separately fabricated bottom Si cell. In addition to top-cell layers, a thin layer of aluminum-based III-V alloy has to be deposited as a sacrificial release layer underneath the top cell structure, in order to aid ELO for bonded cells [49]. Furthermore, for comparison, we also analyze the cost of a 3J GaInP/GaAs/Ge monolithic solar cell [21] whose layers are illustrated in Fig. 8.7B. To calculate cost of electricity in $/kWh from certain technology, conversion efficiency of that cell is needed. However, to date, there are no reports on certified experimental efficiency values of bonded twoterminal GaAs0.75P0.25/Si DJ solar cell, where III-V layers are grown on Si1
xGex/Si substrate and layer-transferred onto separately fabricated Si cell. Fortunately, performance of such cells can be estimated either from simulations or by using the internal quantum efficiency of fabricated GaAsP on Si in addition to cost of bottom Si SJ solar cells [39,42,46,47,50]. In some of our earlier work we estimated that achievable efficiency for GaAs0.75P0.25/Si DJ solar cell can range between 25% and 35%, subjected to material quality of each subcell, absorber layer thickness, amount of optical and electrical losses, and design optimization [39,42]. For comparison, there are confirmed experimental efficiencies for GaInP/Si and GaAs/Si DJ solar cells of about 33%, where III-V layers are grown on expensive III-V substrates [17,31]. Thus, for cost analysis carried out in

FIGURE 8.7 Cross section of the growth of (A) inverted GaAsP top cell on c-Si wafer [46] and (B) 3J GaInP/GaAs/Ge solar cell [21]. Adapted with permission from S. Abdul Hadi, E.A. Fitzgerald, S. Griffiths, A. Nayfeh, III-V/Si dual junction solar cell at scale: manufacturing cost estimates for step-cell based technology, J. Renew. Sustain. Energy 10 (1) (2018) 015905.

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this chapter, the focus is on GaAsP/Si DJ cell efficiency range between 25% and 35%.

8.2.2 IIIeV/Si DJ step-cell fabrication process flow used for cost analysis In order to estimate the manufacturing costs of DJ GaAsP/Si step-cell, large-scale manufacturing process flow has to be considered, where all key cost contributing steps are accounted for. The costs of most of the processing steps defined here are mostly based on the III-V/Si DJ cost analysis presented by NREL [16], where process flow is adjusted, and respective costs updated to fit step-cell design and layer thicknesses analyzed in this chapter. Fig. 8.8 illustrates simplified large-scale manufacturing process flow for bonded GaAsP/Si DJ step-cells, where GaAsP cell is grown on Si substrate via graded Si1
xGex buffer. For the growth of high-quality graded Si1
xGex buffer and GaAsP layers, a high-quality single

FIGURE 8.8 Illustration of large-scale manufacturing process flow used for cost estimates for bonded GaAsP/Si dual-junction step-cell, where GaAsP layers are grown on highquality c-Si substrate [39]. Adapted with permission from S. Abdul Hadi, E.A. Fitzgerald, S. Griffiths, A. Nayfeh, III-V/Si dual junction solar cell at scale: manufacturing cost estimates for step-cell based technology, J. Renew. Sustain. Energy 10 (1) (2018) 015905.

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161

crystalline Si substrate that is appropriate for epitaxial growth must be used as a starting substrate. Graded Si1
xGex buffer is grown using chemical vapor deposition (CVD). Further, GaAsP top cell layers, such as GaAsP p/n junction, III-V window, and BSF layers, are grown on latticematched Si1
xGex buffer by using MOCVD. Those layers are deposited in inverted order along with III-V nucleation and sacrificial release layers (as shown in Fig. 8.7A). Once all of the GaAsP top cell layers are deposited, they are patterned in step-cell features such that Al-based sacrificial layer is exposed. Si1
xGex graded buffer and III-V nucleation layer are not etched (Fig. 8.8). Separately, bottom Si cell is fabricated using simple ionimplantation step in order to form n-type emitter. In order to separate GaAsP cell layers from Si1
xGex/Si substrate carrier, an ELO process based on HF chemistry is utilized. Benefit of the step-cell design here is to speed up ELO time by increasing perimeter of etched layer and enabling access of HF chemistry to smaller surface area at one point in time, since chemical-based lift-off process depends on lateral diffusion of etch chemistry. By this way, the manufacturing throughput of III-V cell fabrication and lift-off is increased, and MJ solar cell processing can be shifted to 800 wafer scale or larger. Once the GaAsP cell is removed from Si1
xGex/ Si substrate carrier, the two cells are connected by means of wafer bonding, which can be followed by contact antireflective coating deposition. Employing ELO process permits reuse of high-crystalline carrier substrate after the layer transfer, which in turn lowers overall costs of bonded MJ solar cells. Reuse of the substrate reduces cost of c-Si wafer as well as cost of deposition of graded Si1
xGex buffer. However, when Si1
xGex/Si substrate is exposed to repeated ELO processes and HF chemistry, it suffers surface damage, which then negatively affects material quality of subsequently grown III-V layers. To mitigate this damage, chemical mechanical polishing (CMP) is normally required in order to prepare a substrate for further growth of high-quality III-V cells, that will have low defect density and low surface roughness [28,51]. While the polishing step itself has added costs (w$8e11/polish [16,51]) the true limitation is that CMP removes some of the carrier material so that the carrier substrate cannot be reused indefinitely. To further reduce manufacturing costs, researchers are looking into different ways to reduce the CMP-induced damage to carrier substrate, such as: (1) capping the substrate with another sacrificial layer that can “absorb” ELO-induced defects and can then be chemically etched before next III-V growth [26]; (2) heating up the recycled III-V/Si1
xGex/c-Si substrates prior to the next III-V growth, which will remove natural oxides and recover GaAsP surface. Employing techniques to minimize CMP-induced defects allows increased number of reuses of free III-V/ Si1
xGex/c-Si substrate, while also reducing the number of times CMP process is required between consecutive III-V depositions [52]. Thus, in

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xGex

cost analysis carried out in this chapter, the three cases are considered: the reference; midterm and long-term scenarios; assuming 5, 10, and 20 substrate reuses before the next CMP step, respectively. For the analysis of commercially available monolithic 3J GaInP/GaAs/ Ge cells used here for comparative purpose, the process steps 9e12 in Fig. 8.8 are considered to follow the MOCVD growth of DJ cell on top of the Ge bottom cell [28]. At final stages of the fabrication process, metal contacts and antireflective coating are deposited on the DJ cell. Inspired by the process flow outlined in Ref. [16] and by its low cost, we here assume that front contact deposition (step 9, Fig. 8.8) is done by screen printing. Furthermore, we assume that metal contacts act as a mask for contact layer patterning, thus removing the need to additional lithography step. In a long-term scenario, assuming ohmic contact, the need for highly doped III-V contact layer can be avoided, decreasing manufacturing costs slightly. Finally, one more lithography step that is not shown in Fig. 8.8 is needed to open vias in nonconductive ARC layer.

8.3 Cost analysis We carry out the cost analysis for GaAsP/Si DJ step-cell to enumerate the benefits of using SiGe/Si substrate carriers for the high-quality III-V growth. To better quantify those benefits, costs of SiGe/Si-based III-V DJ cell is compared to industry standard Ge-based MJ solar cells. With this analysis we also establish major cost contributors for bonded III-V/Si DJ step-cells, which can help identify fabrication steps that need improvement or mitigation in the future.

8.3.1 Cost model The cost analysis presented here is mostly based on the data available from NREL study on III-V technology on Si [16] and other relevant resources and assumptions, since actual and commercial costs for III-V technology are not always publicly available and are often company proprietary information. The cost model for manufacturing of bonded GaAsP/Si DJ cell used for analysis presented in this chapter is based on the process flow shown in Fig. 8.8 and data collected primarily from Refs. [16,51,53]. We assume a 500 MW peak capacity utility-scale PV plant (assumption inherited from Ref. [16]). The costs of module assembly are estimated from Ref. [53]. The cost values presented consider taxes, labor wages, equipment depreciation, etc. The assumptions regarding the cleanroom cost/m2, equipment, taxes, maintenance times, labor wages,

8.3 Cost analysis

163

etc., are adapted from Refs. [16,53] and are listed in Table 8.1 [28]. The battery storage costs are not taken into consideration. The cost analysis presented here is divided into three scenarios: (1) reference case for available technology between years 2015 and 20; (2) midterm case where 2015e20 benchmark costs are reduced based on within-the-reach technologies and assumptions; and (3) long-term scenario (beyond year 2025) assuming significant cost reductions for certain fabrication steps in addition to anticipated 20% cost decrease. For GaAsP/Si DJ step-cell, we analyze the efficiency range from 25% to 35%, while the majority of calculations for the reference case assume 30% efficiency. Commercial monolithic 3J GaInP/GaAs/Ge used here for comparison is assumed to have an efficiency range between 30% and 40%. The cost values listed here are all adjusted to 2020 US dollars based on consumer price indices (CPIs) [54]. In the following sections we describe the parts that make up cost of installed PV energy: (A) cell manufacturing costs, (B) installed costs that include module assembly, BoSs (installation), and operation and maintenance costs.

TABLE 8.1 General assumptions used for cost analysis. General assumptions 1

Utility-scale 500 MW PV plant

2

Class 1000 cleanroom cost: $500/m2

3

350 working days/year, 24 h/day

4

0.25 laborers/reactor and 1:0.35 direct: indirect labor ratio

5

$12.05/h unskilled labor rate, $17.56/h skilled labor rate, 55% benefits on wages

6

Electricity price: $0.07/kWh

7

Average effective corporate tax rate: 28%

8

Factory capital equipment costs allocated over: - 30 years for building cost; - 10 years for wafering; - 7 years for cell manufacturing; - 5 years for module manufacturing.

Inherited from National Reneable Energy Labaratory (NREL), A manufacturing cost analysis relevant to singleand dual-junction photovoltaic cells fabricated with III-Vs and III-Vs grown on Czochralski silicon, 2013. Available: http://www.nrel.gov/docs/fy14osti/60126.pdf. (Accessed 2016) and A. Goodrich, P. Hacke, P.Q. Wang, B. Sopori, R. Margolis, T.L. James, M. Woodhouse, A wafer-based monocrystalline silicon photovoltaics road map: utilizing known technology improvement opportunities for further reductions in manufacturing costs, Sol. Energy Mater. Sol. Cells 114 (2013) 110e135. Reprinted with permission from S. Abdul Hadi, E.A. Fitzgerald, S. Griffiths, A. Nayfeh, III-V/Si dual junction solar cell at scale: manufacturing cost estimates for step-cell based technology, J. Renew. Sustain. Energy 10 (1) (2018) 015905.

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8. Cost benefits of Si1
xGex

8.3.1.1 Cell manufacturing costs The solar cell manufacturing costs are mainly reported in $/W, since this metric allows comparison between the costs of PV generated electricity from a wide range of PV technologies. For cost analysis presented here, we extract processing costs per wafer (Cw) from the data available in literature [16,53], by using “reversed” procedure on the manufacturing step costs. For example, Eq. (8.1) is applied to obtain the cost, Cw ($/Wafer), from known values of: PV installed cost, C ($/W); wafer area, A (cm2); cell efficiency, (h); and manufacturing yield, Y. Here the value of 0.1 (W/cm2) is the irradiance for AM 1.5G 1 sun standard.         $ $ W (8.3) ¼C ,0:1 Cw ,h,A cm2 ,Y 2 Wafer W cm For majority of the processing steps analyzed here and outlined in Fig. 8.8 have cost per run, rather than cost per wafer (Cw). The processing steps that are having same cost regardless of wafer size include: ionimplantation, thermal oxidation, wet etch step, PECVD, and contact deposition. For MOCVD step, however, cost/wafer value obtained by Eq. (8.3) needs to be scaled by the number of wafers inside the reactor during the deposition, which means three 800 wafers, eight 600 wafers, and fifteen 400 wafers [16]. Thus, using larger wafers would result in lower total installed PV costs ($/W) since more solar cells will be fabricated at lower costs. Furthermore, for MOCVD cost per run calculation, there is clear distinction in reactor throughput between the 400 , 600 , or 800 wafer-based processing so the wafer sizes are taken into consideration in the analysis presented here. Table 8.2 summarizes some of the assumptions used in cost analysis here, while rest of the assumptions are described in the text that follows. The cost of CVD deposition of 7 mm Si1
xGex on Si substrate (step 2, Fig. 8.8) is assumed to be w$10/wafer for our reference case and largescale manufacturing [28]. However, this value is just an estimate and some vendors on a smaller manufacturing scale have priced similar Si1
xGex deposition as high as $200/wafer [28]. Thus, for sensitivity analysis, we consider both ranges of anticipated SiGe growth costs, $10/ wafer and $200/wafer. Process flow presented in Fig. 8.8, for reference scenario, assumes two lithography steps: one for patterning the top cell step features and the other to open interconnect vias. Today’s lithography costs make up large portion of manufacturing costs for integrated chips (IC) because of the requirements of features of few nanometers in size. However, for step-cell design analyzed here, the minimum feature size is in micrometer range, meaning that proximity lithography (optical mask aligners) can be sufficiently used for DJ step-cell manufacturing. It is estimated that the proximity lithography step cost is five times lower than that of

165

8.3 Cost analysis

TABLE 8.2 Some of the assumptions used for cost analysis. Assumption

Notes/comments

1

III-V nucleation layer is regrown after ELO step with every new III-V growth.

Some of III-V nucleation layers could be removed with CMP step. Also, it can account for substrate capping that may be used to recover SiGe/Si substrate surface quality.

2

Deposition related costs (including material, equipment, and labor) are scaled linearly with the layer thickness.

Exception to this is the costs of GaAsP cell active layers, which are treated differently due to the nature of their deposition.

3

Costs associated with GaAsP cell active layers thickness are scaled linearly with the thickness, while costs related to MOCVD tool general maintenance and operation are kept fixed (per run).

GaAsP deposition involves tool pumping and temperature ramp up and down times and tool maintenance [16], which are not GaAsP thickness dependant; thus these costs are based on a single tool run.

4

In wet etch steps, the material costs are scaled with the area for different wafer sizes, while the remaining costs scale linearly with the thickness.

Wet etch dedicated tools are used for longer times when thicker layers are being etched (assuming linear etch rate).

high-resolution stepper technology used in IC industry [55]. After brief interviews with mask aligner vendors back in 2016, we came to conclusion that the mask aligner for PV requirements and for 200 mm wafers with throughput of 180 wafers per hour [56] would not cost more than US $1M, including taxes and operation and maintenance costs [28]. Inheriting assumptions listed in Table 8.1 we estimate lithography cost per wafer by assuming linear depreciation over 7 years, 350 working days/24 h, and average labor wages of US $14.8/hour (Table 8.1) [28]. With these assumptions, lithography tool cost equals w0.18 US 2015 $/wafer. Adding to that 0.1 $/wafer for consumables and 0.4 $/wafer

166

8. Cost benefits of Si1
xGex

for mask costs (assuming $2000 mask cost/5000 exposures) [57], overall the lithography step is estimated to cost around w$0.68 2015 USD or w$0.75 2020 USD [28]. For midterm case analysis, the lithography cost reduction is assumed due to increased throughput and improved yield. For the long-term, yet achievable, technology, lithography step is replaced with photoresist screen-printing. Improvements in lithography, or avoidance of lithography step by selective growth or screen-printing, are to be expected with expanding market demands. Wafer-bonding costs for large-scale manufacturing are assumed to be w$2.6/wafer in 2020 USD, value adjusted from Ref. [58]. For ELO process, it is assumed that HF chemical bath with etch accelerators such as isopropanol (IPA) and acetone is used, leading to an etch rate of w14 mm/min [59]. Since in step-cell design, the patterned top cell is being lifted off, mesa fingers are assumed to be narrow enough to facilitate 1-h-long bath (i.e., w1700 mm width), suitable for large-scale manufacturing [60]. Cost values breakdown for each process step (in 2020 USD) is listed in Table 8.3, not taking manufacturing yield into account. 8.3.1.2 Installed PV costs In addition to manufacturing cost, installed PV cost also comprises of module assembly cost and on-sight installation related costs (BoS). All of these cost components are expressed in the $/W, where cell’s efficiency and manufacturing yield are taken into account. In the final step of PV module production, manufactured cells are combined into a single module (panel), where individual cells are electrically connected in series and/or parallel connection configurations. Connected cells are encapsulated inside a film that is vacuum laminated onto the array, which is then covered with glass and aluminum frame. The module cost has two components: one that is fixed cost per module and other component where cost varies with the size of the module ($/m2). In the analysis presented here, it is assumed that 100 individual cells are housed in a single module so that wiring-related costs remain constant. Thus, it follows that the module peak power capacity and size vary based on the individual solar cell efficiency, which then results in variable module costs (i.e., size-related costs). The total module area is assumed to have additional 20% of the area allocated for the spacing between the individual cells. The total cost per module ($/module) is converted to $/W based on the module’s peak capacity and from the assumed 100 cells that are housed in it. With increasing global installed PV capacity, prices of module have decreased over the years. In reports carried out in 2013 we have estimated module-related cost (aluminum frame, J-box, stringing and ribbons, etc.) to be w29 $/module (2013 US $) and module sizeerelated cost (glass and

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8.3 Cost analysis

TABLE 8.3 Extracted manufacturing step costs based on Refs. [16,53] for reference case scenario. All costs are in 2020 US $. Step

Starting wafers

800 Si

1

Wafer cost ($)

30.00 [44]

Diameter (cm) Area Wafer lost (%)

600 Ge

400 Ge

25.0a

150.0 [43]

147.4a

20.3

15.2

15.2

10.2

323.7

182.4

182.4

81.1

27

27

133.2

59.2

27

2

Cell area (cm ) Wafer cost ($/cm )

0.127

2

CVD cost ($/wafer)

10.8

3

CMP cost ($/wafer)

8.9

4

MOCVD costs #Wafers per reactor

133.2 0.188 10.8

1.126

2.491

0

0

0

3

III-V 250 nm nucleation layer ($/run) ($/wafer)

4-2

27

236.3 2

4-1

600 Si

8

8

18.8 6.3

15 3.2

2.3

0.4

0.2

Cell growth with BSF, base, emitter, window, contact, and ELO release layers ($/run) ($/wafer)

58.3 19.4

94.4 7.3

11.8

6.3

5

Wafer-to-wafer bonding [61] ($/wafer)

2.6

0

6

Lithography ($/wafer)

1.5

0.75

7

Epitaxial lift-off in HF (chemistry related costs only) ($/wafer)

0.11

0.07

0

0

III-V wet etch ($/wafer)

2.13

1.2

0

0

8

Front contact Ag screen printed ($/run)

0.41

9

Back metalization ($/wafer)

0.41

10

ARC sputtering ($/wafer)

0.05

a

Vendor prices. Adapted with permission from S. Abdul Hadi, E.A. Fitzgerald, S. Griffiths, A. Nayfeh, III-V/Si dual junction solar cell at scale: manufacturing cost estimates for step-cell based technology, J. Renew. Sustain. Energy 10 (1) (2018) 015905 and S. Abdul Hadi, III-V on Si Multi-Junction Step Cell (Ph.D. Dissertation), Abu Dhabi, 2016.

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8. Cost benefits of Si1
xGex

protective sheets) to be w31 $/m2 (2013 US $) [16,53]. However, from current analysis carried out by NREL [61] it is reported that 400 W PERC monocrystalline solar cells have an average module cost of 0.13 $/W, from where it can be extracted that module costs are w52 $/module or w26 $/m2 (2020 USD). It can be also concluded that at least 50% of those costs are still size dependent and will be lower with increasing cell efficiency. Thus, in our analysis here, we allocate fixed 26 $/module and 13 $/m2 which varies with the size of the module, depending on the efficiency of the cells used. As a reminder, in our analysis we assume 100 cells per module and costs are then readjusted into $/W for fair comparison. As mentioned earlier, the BoS costs include all components related to module installation at a PV plant site, such as: structural system (installation, site planning, racks, and related items); electrical system (wiring, installation, inverter); and other costs (permits, labor, profit margins, etc.). BoS costs vary greatly among different countries, ranging from below 0.4 $/W to above 1 $/W [62]. The global capacity weighted-average total installed cost of utility-scale projects was about 0.883 USD/W in 2020 W [62], where on average 65% of it was due to BoS costs. Thus, here we assume BoS costs to be 0.57 USD/W (65% of 0.883 USD). This is partly due to difference in solar cells used and their efficiencies as well as the different levels of economies of scale across countries and knowledge base related to it. In year 2014, average BoS costs were about 0.8 $/W [63], where we can assume that reported BoS cost is mainly for w20% efficient Si solar cells, since more than 85% of globally installed PV capacity was Si-based back then. Based on the BoS cost breakdown reported in Ref. [63, p. 86] we can assume that 30% of BoS costs are fixed regardless of the efficiency of the cell (inverter, permitting, designing, etc.), while 70% of the BoS costs change with the area and the number of modules required for a required capacity. Thus, given above information, in cost analysis presented here we assume that 30% of the BoS costs are fixed, while 70% are varied linearly depending on the efficiency of the cell [28].

8.3.2 Cost analysis results Cost analysis presented here considers three different scenarios: reference, midterm, and long-term. Assumptions outlined in previous section are the basis for the reference scenario (years 2015e20), while midterm and long-term scenarios consider some improved conditions which will be mentioned later. To quantify the number of times that Si1
xGex/Si carrier substrates should be reused for III-V growth, in an economically feasible way, we investigate the carrier wafers with necessary buffer layers’ costs ($/W). Fig. 8.9 shows the costs of Si1
xGex/c-Si substrate as a function of number of reuses. Also shown is the cost of Ge wafer as a reference, assuming that

8.3 Cost analysis

169

FIGURE 8.9 Substrate costs as a function of number of substrate reuses for III-V growth on high-quality 8-inch c-Si wafers for $10 (dashed lines) and $200 (full lines) SiGe CVD growth. Also shown is the cost of Ge wafers used for monolithic 3J solar cells (dotted line, no substrate reuse). Adapted with permission from S. Abdul Hadi, E.A. Fitzgerald, S. Griffiths, A. Nayfeh, III-V/ Si dual junction solar cell at scale: manufacturing cost estimates for step-cell based technology, J. Renew. Sustain. Energy 10 (1) (2018) 015905.

3J solar cell grown on it could have efficiency ranging between 30% and 45%. The cost of Si1
xGex growth varies with manufacturing scale, thus here we consider SiGe CVD growth cost between $10/wafer (dashed lines, Fig. 8.9) and $200/wafer (full lines, Fig. 8.9). The starting 800 single cSi wafer is assumed to be high quality and cost $30 [44] because of the requirements for the epitaxial growth of high-quality Si1
xGex layers. Fig. 8.9 illustrates different options for CMP polishing steps, which could be repeated either prior to each, every second or fifth substrate reuse, labeled here as CMP cycles 1, 2, and 5, respectively. The calculations assume manufacturing yield Y ¼ 0.7 and cell conversion efficiency of 30%. CMP cost per wafer is reduced by the number of substrate reuses and by larger number of cycles before CMP has to be repeated. If the CMP would be necessary after every reuse (CMP cycle ¼ 1), very large number of reuses would be needed for substrate cost to be financially feasible. This means that it is crucial to develop a fabrication process that does not require CMP step very often, and preferably not at all. As shown in Fig. 8.9, the cost of Si1
xGex growth decreases with increasing number of substrate reuses, decreasing from w$46/W without reuse to $2.6/W for 20 reuses and CMP every fifth use for $200/growth Si1
xGex case (Fig. 8.9, red full squares; light gray in print version). For small-scale Si1
xGex growth ($200/growth) and without substrate reuse, using Si1
xGex/c-Si substrate can be as expensive as use of Ge substrate, given that

170

8. Cost benefits of Si1
xGex

Ge-based MJ cells have efficiencies above 35%. This verifies that in order to realize low-cost MJ solar cell production, conversion efficiency, substrate reuse, and large-scale production all play significant role. For rest of the result presented in this cost analysis and under the reference scenario, we assume that Si1
xGex CVD growth cost $10/wafer (equivalent to large-scale production) with five substrate reuses and CMP every second reuse. 8.3.2.1 Reference scenario As mentioned above, for PV fabrication cost calculations for reference scenario, we consider that Si1
xGex/c-Si substrate is reused five times and that CMP step is repeated after every second cycle. Fig. 8.10 shows the breakdown of manufacturing cost ($/cm2) for four different analyzed cases: 8-inch and 6-inch Si-based GaAsP/Si DJ step-cell and 6-inch and 4inch Ge-based monolithic GaInP/GaAs/Ge triple-junction solar cells. It can be concluded from Fig. 8.10 that major cost contributor in fabrication of bonded GaAsP/Si step-cell is MOCVD growth of III-V layers, followed by c-Si substrate and lithography costs. In this case it is assumed that MOCVD reactor can house three of 8-inch wafers and eight 6-inch wafers, which resulted in higher MOCVD related costs for 8-inch wafer-based production. However, the rest of the processing costs are all lower for larger wafer size, leading to lower total manufacturing costs for 8-inch based production wafers. Furthermore, these results suggest that manufacturing monolithic triple-junction solar cells on Ge wafers is

FIGURE 8.10 Estimated manufacturing cost (2020 US $/cm2) by each process step for bonded DJ GaAsP/Si step-cell and monolithic GaInP/GaAs/Ge 3J solar cell for different substrate sizes under reference scenario conditions. Note: Ge wafer costs are outside of the chart’s scale. Adapted with permission from S. Abdul Hadi, E.A. Fitzgerald, S. Griffiths, A. Nayfeh, III-V/Si dual junction solar cell at scale: manufacturing cost estimates for step-cell based technology, J. Renew. Sustain. Energy 10 (1) (2018) 015905.

8.3 Cost analysis

171

considerably costlier, largely due to high substrate costs and thicker III-V layers. Fig. 8.11 shows the total installed PV cost for the reference scenario in all considered cases considering the range for different conversion efficiencies. The efficiencies, h, used for lower and upper range calculations for GaAsP/Si DJ step-cell are set to 25% and 35%, respectively. In Fig. 8.11 the calculations at h ¼ 30% are indicated with a cross sign. For comparison, monolithic 3J GaInP/GaAs/Ge cell is considered to have efficiencies between 30% and 40%, where cross symbol indicates case with h ¼ 35%. Moreover, we also look here into the effect of Si1
xGex cost where total installed costs for $10/wafer (red; gray in print version) and $200/wafer (gray) Si1
xGex growth are calculated. These results show that installed cost of 8-inch GaAsP/Si step-cell ranges between w$8.3/W and w$11.6/W for analyzed efficiency range and for Si1
xGex growth cost of $10/Si1
xGex growth. On the other hand, for $200/Si1
xGex growth the cost varies between $14.9/W and $20.7/W. In contrast, the lowest installed cost of monolithic triple-junction Ge-based cell is w$44/W for 40% efficient cell grown on 6-inch wafer. These results imply that ELO process and substrate reuse could offer a competitive advantage of Si-based DJ solar cells compared to monolithic Ge-based MJ solar cells.

FIGURE 8.11 Estimated range for installed PV costs for analyzed bonded GaAs0.75P0.25/ Si DJ step-cells for efficiency range between h ¼ 25%e35% and utilizing $10 (red; gray in print version) and $200 (gray) SiGe growth. Also shown is the range for the costs of monolithic GaInP/GaAs/Ge solar cells (blue; light gray in print version) for h ¼ 30%e40%. Adapted with permission from S. Abdul Hadi, E.A. Fitzgerald, S. Griffiths, A. Nayfeh, III-V/Si dual junction solar cell at scale: manufacturing cost estimates for step-cell based technology, J. Renew. Sustain. Energy 10 (1) (2018) 015905.

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8. Cost benefits of Si1
xGex

8.3.2.2 Midterm scenario assumption For midterm scenario (within-the-reach for years 2020e25), assumptions about cost reduction of specific processing steps are made based on research developments or based on anticipated 20% reductions whenever global PV capacity is doubled, as per PV learning curves [64]. Under midterm scenario, we assume CVD growth of SiGe layers to cost 8 $/wafer per run. Furthermore, in this scenario, we assume that MOCVD throughput and material consumption efficacy are both improved, assuming total 30% cost reduction for this step. This is based on reports of reactors (such as MOCVD Veeco) that can accommodate 24 6-inch wafers, resulting in approximately 20% cost reduction compared to older system with 8 wafers [65]. Also, AIXTRON reported 40% material-related cost reduction using their top-of-the-line reactors (CRIUS II-XL), partially due to high deposition rates (32 mm/h) and better material utilization [28,66]. For the number of substrate reuses we assume that it is possible to increase it to 10 times where CMP would be needed only after every fifth cycle. Additionally, we assume that average manufacturing yield will be 80% and that GaAsP/Si step-cell efficiency is 32%. The remaining costs are all reduced by 20%, including module and BoS costs, based on PV technology learning curve [28]. Fig. 8.12 shows estimated manufacturing costs for four analyzed cases under midterm scenario assumptions. Total installed cost adds up to be about w4.7 $/W for GaAsP/Si DJ cell with 35% efficiency, which is less than half compared to the costs of reference scenario.

FIGURE 8.12 Estimated manufacturing cost (2020 US $/cm2) by each process step for bonded DJ GaAsP/Si step-cell and monolithic GaInP/GaAs/Ge 3J solar cell for different substrate sizes under midterm scenario conditions. Note: Ge wafer costs are outside of the chart’s scale.

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173

8.3.2.3 Long-term scenario In a long-term scenario that is assumed to be beyond year 2025, emerging or expected technological developments are assumed. One assumption is that Si solar cells will be fabricated on crystalline Si grown by so-called Direct Monocrystalline Silicon Wafer Growth by HighThroughput Epitaxy, developed by NREL and Crystal Solar scientists, where Si cells are grown epitaxially on lattice-matched cheap substrates [67]. This process involves stacking of the wafers vertically into a reactor, which allows up to 500 wafers to be processed per hour, resulting in cell costs of w0.13 $/W [67]. Moreover, MOCVD cost reductions can be expected, since III-V layers are broadly used in light-emitting diode maturing market. Thus, for a long-term scenario it is assumed that MOCVD costs will be further reduced by 30% compared to midterm scenario. Besides, in long-term analysis, growth of the heavily doped III-V contact layer is removed because front ohmic contacts are assumed, also getting rid of the etch step of a contact layer. For the frequency of the CMP step and the number of substrate reuses we assume that it is increased to 50 times [31] where CMP would be needed only after every 10th cycle. This assumption was based on the recent results where researchers were able to grow high-efficiency III-V cells on reused Ge substrates without polishing step at all [68]. Furthermore, bonding costs are assumed to decrease by 50% in longterm scenario, reducing the effect of this major cost contributor. Also, it is assumed that the lithography step can be substituted by screen-printing of photoresist. The rest of the costs are reduced by 20% compared to midterm scenario costs, while manufacturing yield is assumed to improve to 90%. Finally, since today majority of the manufacturing processes are carried out in China, we assume under long-term scenario the 50% reductions in taxes, depreciation rates, labor, utility, and maintenance costs, compared to midterm scenario. In Ref. [16] it was estimated that these costs account for approximately 50% of total manufacturing costs for GaAsP/Si cell. This results in a 25% reduction on overall manufacturing costs compared to midterm scenario costs, which we assume for all manufacturing costs in long-term scenario. Si-based DJ step-cell conversion efficiency is assumed to increase from 32% to 35% [28]. Fig. 8.13 summarizes manufacturing costs in $/cm2 for four analyzed cases under long-term assumptions. Fig. 8.14 compares manufacturing costs for bonded DJ GaAs0.75P0.25/Si step-cell, supposing 8-inch c-Si carrier substrate, for reference, midterm, and long-term scenarios with assumed yield of 70%, 80%, and 90% respectively. Even under very relaxed long-term scenario assumptions, the three major cost contributors are MOCVD growth, wafer carrier, and

174

8. Cost benefits of Si1
xGex

FIGURE 8.13 Estimated manufacturing cost (2020 US $/cm2) by each process step for bonded DJ GaAsP/Si step-cell and monolithic GaInP/GaAs/Ge 3J solar cell for different substrate sizes under long-term scenario conditions. Note: Ge wafer costs are outside of the chart’s scale.

FIGURE 8.14 Bonded DJ GaAsP/Si solar cell manufacturing cost (2020 US $/W) by step for 8-inch Si carrier, comparing reference, midterm, and long-term scenarios. Adapted with permission from S. Abdul Hadi, III-V on Si Multi-Junction Step Cell (Ph.D. Dissertation), Abu Dhabi, 2016 and S. Abdul Hadi, E.A. Fitzgerald, S. Griffiths, A. Nayfeh, III-V/Si dual junction solar cell at scale: manufacturing cost estimates for step-cell based technology, J. Renew. Sustain. Energy 10 (1) (2018) 015905.

wafer bonding. Researchers have identified those cost-driving factors and are actively working on finding alternative and less expensive ways of fabricating MJ solar cells. Currently researchers are exploring MJ cells fabricated via wire-bonding [69] or by using four terminals [70]. The costs related to wire bonding or four-terminal configurations are not

8.4 Conclusion

175

considered in this chapter, but those fabrications steps are much simpler than wafer bonding, hence it can be anticipated that they can drive manufacturing costs of MJ solar cells further down, if successfully used at a large scale. From Fig. 8.14, we see that under midterm scenario assumptions, GaAsP/Si DJ step-cell manufacturing costs drop under $5/W at 500 MW manufacturing scale and assuming 32% efficiency. Furthermore, under the long-term scenario, overall manufacturing costs drop down close to $1.5/W with MOCVD being largest cost contributor. Although in the long-term scenario, the costs of GaAsP/Si DJ step-cell fabricated via SiGe/c-Si substrates are significantly reduced, these costs are still higher than the costs of installed Si SJ solar cell. However, for applications where high power density is essential, such as solar powered vehicles and devices (cars, drones, satellites, etc.), the GaAsP/Si DJ solar cells manufactured on Si1
xGex/c-Si substrates utilizing step-cell design can be a cost-effective solution compared to cells manufactured on Ge or GaAs wafers [28].

8.4 Conclusion In this chapter we presented the bottom-up approach that is used to estimate the manufacturing costs of GaAs0.75P0.25/Si DJ step-cell grown via SiGe graded buffer layer. The process costs are compared to monolithic GaInP/GaAs/Ge triple-junction solar cell as well. We showed how step-cell design can facilitate faster ELO process, making it feasible for large-scale manufacturing, thus lowering the costs related to ELO step. While GaAs0.75P0.25/Si DJ step-cell theoretical efficiencies range between 40% and 45%, in this work we assumed more practical levels with efficiencies of 35% in long-term scenario. For DJ step-cell, top GaAsP cell is assumed to be grown on Si1
xGex/c-Si substrate, lifted-off and bonded to separately fabricate bottom Si cell. Si1
xGex/c-Si substrate is then reused for further GaAsP growth, which reduces the cost of Si1
xGex CVD growth, making III-V/Si-based MJ solar cells economically competitive. Our analysis here also showed that Si1
xGex/c-Si substrate reuse is vital to sustain noteworthy cost advantage compared to Ge-based manufacturing. With sufficiently high number of substrate reuses, costs of CMP step become major cost contributor, rather than CVD growth of Si1
xGex graded buffer. Three scenarios were considered here, with future assumption being based on literature survey and informed assumptions. The results for technology currently available under a reference scenario indicate that major cost contributors in GaAsP/Si DJ step-cell manufacturing are

176

8. Cost benefits of Si1
xGex

MOCVD growth of III-V layers, substrate carrier, lithography, and wafer bonding. Under midterm and long-term scenarios, the number of wafer reuses is increased, while number of cycles without need for CMP is increased. Among other assumptions in those scenarios, we assumed that throughput of most processes is improved, lowering overall costs significantly. Under all scenarios, the cost of MOCVD step needed for the growth of III-V layers remained the largest cost contributor for Si-based cells. On the other hand, for Ge-based growth, the carrier costs are the major contributors under all scenarios. Overall, the analysis presented in this chapter showed that III-V/Si DJ step-cells grown on Si wafer via Si1
xGex buffer layer provide the cost advantage over commercial Ge-based monolithic MJ solar cells. However, costs of III-V/Si DJ step-cell are expected to have higher $/Watt than SJ Si cell, still limiting their use to niche applications such as transportation devices, satellites, light-weight applications, consumer electronics, etc., or in the cases when the site size is of a concern or operation and maintenance costs are high.

References [1] International Renewable Energy Agency, IRENA: renewable power generation costs in 2020, 2020. Available: https://www.irena.org/publications/2021/Jun/Renewable-Power -Costs-in-2020 (Accessed 2022). [2] International Renewable Energy Agency, 5 years of advancing the renewable energy solution. Available: http://resourceirena.irena.org/gateway/dashboard. (Accessed 2016). [3] International Renewable Energy Agency, Renewable Energy Capacity Statistics 2021, IRENA, 2021. [4] BP, Bp statistical review of world energy 2021, 2021. Available: https://www.bp.com/ en/global/corporate/energy-economics/statistical-review-of-world-energy.html (Acc essed 2022). [5] Fraunhofer Institute for Solar Energy Systems, ISE, Photovoltaics report, 2016. Available: https://www.ise.fraunhofer.de/de/downloads/pdf-files/aktuelles/photovoltaics-report -in-englischer-sprache.pdf. [6] International Renewable Energy Agency (IRENA), Solar photovoltaic summary charts. Available: https://www.irena.org/costs/Charts/Solar-photovoltaic. (Accessed 2022). [7] International Energy Agency & Organisation for Economic Co-operation and Development/Nuclear Energy Agency, Projected costs of generating electricity, 2020 edition, 2020. Available: https://iea.blob.core.windows.net/assets/ae17da3d-e8a5-4163-a3ec2e6fb0b5677d/Projected-Costs-of-Generating-Electricity-2020.pdf (Accessed 2022). [8] S. Ringbeck, J. Sutterlueti, BoS costs: status and optimization to reach industrial grid parity, Prog. Photovolt. Res. and Appl. 21 (6) (2012) 1411e1428. [9] L. Fraas, L. Partain, Solar Cells and their Applications, second ed., John Wiley & Sons, Inc., Hoboken, 2010. [10] C. Cameron, A. Goodrich, The levelized cost of energy for distributed PV: a parametric study, in: 35th IEEE Photovoltaic Specialists Conference (PVSC), Honolulu, 2010. [11] M.H. Kang, A. Rohatgi, Development and use of a simple numerical model to quantify the impact of key photovoltaics system parameters on the levelized cost of electricity, in: 38th IEEE Photovoltaic Specialists Conference (PVSC), Austin, TX, 2012.

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C H A P T E R

7 Modeling and simulations of Si1-x Gex based solar cells 7.1 Introduction In this chapter we provide the overview of simulations of different Si1
xGex based solar cells, including single-junction (SJ) Si1
xGex solar cells, as well as III-V/Si dual-junction (DJ) cells that are intended to be fabricated using Si1
xGex graded buffer. Simulations are mostly done using Physics Based Technology Computer Aided Design (TCAD) software package by Synopsys [1], which numerically solves the set of complex equations. Electrical and optical behavior of the cells presented in this chapter is simulated using 2D model in TCAD. TCAD can simulate realistic environment for solar cells, since many physical parameters can be varied and fine-tuned, such as impurity concentration, carrier lifetime, surface recombination, reflective losses, layer thickness, etc. In addition to TCAD simulations, some of the analyses presented here use MATLAB tools, including detailed balance method used to find theoretical efficiency limits of multi-junction (MJ) solar cells and the stepcell configuration. When the data are available, the simulation results are compared to experimental results in order to either validate the simulation model or estimate the dominant loss mechanisms present in the solar cell.

7.2 Overview of synopsys TCAD tools Synopsys combines number of programs in order to complete simulations of process design, process flow, material properties, CMOS technology, device electrical properties, etc., into one software package. Those

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individual tools are grouped under one graphic user interface (GUI) known as Sentaurus Workbench (SWB). Some of the TCAD software tools that can be accessed through Sentaurus Workbench include: Sentaurus Device (Sdevice), Sentaurus Process (Sprocess), Sentaurus Structure Editor (SDE), Inspect, Sentaurus Visual (previously Tecplot), etc. Users can define parameters and variables within the SWB to be able to run broad parametric analysis. The resulting data can be used as graphs, text, or excel files [2]. In order to simulate solar cells in this work we mainly use SDE, SDevice, Tecplot (or Sentaurus Visual), and Inspect from Synopsys. In Sentaurus Structure Editor user can define two-dimensional (2D) or three-dimensional (3D) geometry of a device, along with the materials used for each region, their doping, analytical profiles, and contact definitions. Here, analytic profiles are described by a mesh, which is defined in SDE with command “Mesh.” Meshing profile can be defined separately for different regions, such that interfaces and regions with important generation-recombination events are very dense, whereas rest of the regions will not need a high-density mesh. This is done to optimize calculations capacity but also to ensure realistic simulations of physical events. SDE output file is used as an input to Sentaurus Device, with all material electrical and optical properties already specified. Sdevice is used to specify way the set of complex equations is to be solved, while Sentaurus Visual and Inspect can be used to plot electrical characteristic of simulated device [3]. Sdevice command files have two parts: command file and parameter file. In command file, electrical models that are used to solve set of equations are defined, along with the type of required outputs, such as total current, optical generation or recombination rate, mobility, effective bandgap, etc. On the other hand, in parameter file user specifies the properties of the materials used in SDE defined structure. While default parameters are predefined in Sdevice, user is given an option to manually change those and choose among available models based on used materials. Models, parameters, and assumptions used in most of simulations presented in this chapter are listed below and are grouped into sections as they appear in SDevice file: Physics Section, Optics Section, and Parameter File. Finally, common challenges and types of uncertainties faced in TCAD simulations are discussed.

7.2.1 Physics section The physics section is defined within the Sdevice command file, where user can activate the models required for their simulations. Some of the physics models can be specified globally, to apply to all parts of the device, while some models can be limited to a certain material or interface.

7.2 Overview of synopsys TCAD tools

105

For example, in our simulations, Fermi-Dirac statistics is selected to be used globally, while thermionic emission model is activated for heterojunction (HJ) cells in order to model transport over the barrier at the heterointerface. Moreover, Shockley Read Hall (SRH) Scharfetter recombination model is activated across all device simulation as it simulates the effect of bulk carrier lifetime. In this model, we often used the minority carrier lifetime, s, as a variable parameter by modifying smax for holes and electrons [4]. Furthermore, in SDevice we also model surface recombination. At hetero-interface, surface recombination is modeled by activating the surfaceSRH option, which allows for simulation of the effects of surface recombination velocity. In all simulations presented here, surface recombination velocity was simulated without doping dependence.

7.2.2 Optics section Optics section in SDevice interface allows the user to choose between different models in order to simulate light propagation inside a device and perform the relevant optical generation computations. These include: transfer matrix method (TMM), the raytracing method, and finitedifference time domain (FDTD) method. Typically, raytracing method is used for simple structures, while FDTD method can realistically simulate optical generation in complex devices including 3D structures and textured surfaces. In the simulations presented here, TMM model is used for optical generation simulations, as it provides best tradeoff between results accuracy and computational simplicity. With any of the chosen optical solvers, users can pick how to calculate the optical generation from a few different approaches [3], and those include: L Compute the optical generation from a monochromatic optical source. L Compute the optical generation resulting from an illumination spectrum. L Set a constant value for the optical generation. L Read an optical generation profile from file. L Compute the optical generation as a sum of the above contributions. To simulate currentevoltage (IeV) characteristics in daylight conditions for all simulated cells presented in this chapter, we use an option: ComputeFromSpectrum, where spectrum AM 1.5G is taken from Ref. [5]. Normal incidence light is assumed. Spectrum file can be manually updated if one needs to simulate devices under AM 1.5 D spectrum (for PV concentrated simulation) or for AM 0 (for space applications).

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Another important parameter in Optics Section is “Quantum Yield.” In simulations presented here the quantum yield is sometimes set to “1”, assuming that all absorbed photons are converted to generated electronehole pairs, or it is set to be a step-function of effective bandgap such that optical absorption is “cut-off” at a specified bandgap value. In order to simulate optical generation, optical parameters of all materials in solar cell structure must be used. The complex refractive index model in Sentaurus Device allows definition of the refractive index, ns (in TCAD referred to as n), and the extinction coefficient, k, depending on mole fraction, wavelength, temperature, carrier density, and local material gain [3, p. 442]. However, the wavelength model allows user to insert the refractive index and extinction coefficient as tabulated values from perimeter file (TableODB). In case some wavelengths are not listed in the table, ns and k are then linearly interpolated by the solver. In all simulations presented here we use wavelength-dependent complex refractive index. Complex refractive indices for a-Si, Si, and Si1
xGex were utilized from published ns-k data [6,7]. InGaAP optical properties are used in simulations of III-V cells grown on SiGe/Si substrates and are utilized from Ref. [8], while optical properties for GaAs1
yPy are utilized from Refs. [9,10]. In general, device-specific physics model settings will be briefly described for each device discussed in following sections.

7.2.3 Parameter file As mentioned earlier, the parameter file comprises information about electrical and optical properties of materials used in the simulated device. These parameters are needed to simulate models specified in command file of Sdevice. Details on material properties used in simulations presented here will be described for each device separately in following sections.

7.2.4 Challenges and uncertainties All simulations here are carried out by a 2D model using TCAD Synopsys [1], which basically solves a set of equations for a 1D problem whose conditions are taken at one vertical section (“Line”) of the simulated structure. This can lead to one source of discrepancy between simulations and experimental results, as no solar cell will have the same cross section across its surface area (i.e., nonuniformity of films, presence of contact layer, etc.) Another source of inconsistencies between simulated and experimental results can be because of a lack of accurate models and data for material and interface properties. Simulation results completely depend

7.3 Si1
xGex single-junction cells

107

on the model used and data we input. While we always try to be as accurate as possible in our choice of models or data for all cell structures presented in this chapter, some level of uncertainty remains, as the input data we have available are not always optimum, especially when it comes to simulation of III-V layers. Sometimes, TCAD simulations can over- or underestimate solar cell performance parameters under observation, and some reasons for that can be [10]: -

Optical and electrical properties of the material Optical excitation Contact resistivity Surface recombination, carrier lifetime, and mobility Meshing

Meshing is especially an important aspect of a TCAD model which specifies at which points the required set of equations will be solved. Too much or too little mesh can cause inaccurate results, or even can cause the equation solver not to converge or to take very long time to complete. There are some typical practices used in TCAD simulations, where mesh is increased at important interfaces, such as at the top of the cell or at the junction. However, for structures that are not simple and have more important areas where significant generation and recombination take place, one would need to optimize TCAD model and its meshing by comparison to experimental data and results. There will always be some error margin for simulation results, especially when the model is not fine-tuned for the best fit to experimental data. However, the trends observed by TCAD simulations can guide a researcher into what device behavior can be expected from the experiment under study and help steer the research work in the right direction, saving valuable time and resources.

7.3 Si1LxGex single-junction cells The bandgap of Si1
xGex material can be tuned by adjusting the Ge content, x, allowing control of how much current will be photogenerated from the absorbed light. Bandgap of Si1
xGex decreases with increasing germanium content, resulting in increased short circuit current, Jsc, of Si1
xGex cell. However, with decreasing bandgap, open-circuit voltage, Voc, is bound to decrease. One way to offset the decrease of Voc with larger Ge content to benefit from increasing Jsc is to combine Si1
xGex absorber layer with wide bandgap emitter, such as a-Si. In this section we investigate Si1
xGex SJ solar cells with a-Si emitter.

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7. Modeling and simulations of Si1-x Gex based solar cells

FIGURE 7.1 Cross section of simulated Si1
xGex HIT cells, where (A) is the simple heterostructure of a-Si:H/c-Si1
xGex/c-Si cell and (B) is a-Si:H/i a-Si:H/strained c-Si/c-Si1
xGex/ c-Si HIT structure [11] (not to scale).

For the analysis presented here, we investigate two main HJ structures shown in Fig. 7.1. These solar cells are simulated using the Synopsys TCAD tools [1]. A simple a-Si:H/c-Si1
xGex/c-Si structure shown in Fig. 7.1A is simulated to analyze the effect of Ge content on the performance of thinfilm Si1
xGex HJ solar cells. Simulated structure is composed of a heavily doped p-type Si substrate (Na ¼ 1019 cm
3), lightly doped p-type c-Si1
xGex absorber (x ¼ 0e1 and Na ¼ 1016cm
3), and 15 nm heavily doped n-type hydrogenated amorphous silicon (a-Si:H) with donor concentration Nd ¼ 1  1019 cm
3. Different absorber layer thickness values are analyzed, ranging from 2 to 8 mm. A heavily doped p-type Si substrate serves as the back contact and does not contribute to photogenerated carriers. On the other hand, we also simulate the structure shown in Fig. 7.2B in order to analyze the behavior of thin-film a-Si/i a-Si/c-Si1
xGex HIT solar cells, which have been fabricated by our group [11,13,14] and discussed earlier in this Chapter 5. In HIT structure, the 5 nm of intrinsic a-Si:H and 1 nm intrinsic strained Si are placed in between nþ a-Si emitter and p-type Si1
xGex absorber layers, forming heterojunction with intrinsic thin layer (HIT). Those two layers are used to improve the quality of the a-Si:H/ Si1
xGex interface, as this was observed experimentally. When analyzing HIT structure (Fig. 7.1B), we also look in details into a-Si emitter, optical generation inside Si1
xGex graded buffer, the effect of the absorber layer thickness, and the effect of Ge content. These simulated data are used to

7.3 Si1
xGex single-junction cells

FIGURE 7.2

109

Band diagram for a-Si/c-Si0.5Ge0.5/c-Si HJ cell under equilibrium condi-

tions [11,12].

extract effective lifetime of fabricated solar cell by comparing simulation with experimental data [14]. Bandgap of relaxed Si1
xGex layers is utilized from Braunstein et al. [15], and conduction band offset, DEc, of 0.15 eV between a-Si and strained c-Si is used for structure shown in Fig. 7.2B [16]. Different Ge fractions are simulated using Si1
xGex optical parameters for x ¼ 0, 0.2, 0.5, and 0.75 from Ref. [7] and values for x ¼ 0.39 and 1 from Ref. [6]. There is a large increase in the absorption between 39% and 50% Ge, meaning that Si1
xGex absorber layer with 50% Ge or more can be as thin as 1 mm and effectively absorb as much light as thicker Si layer would. To observe effect of Si1
xGex on the performance of the solar cell only due to its smaller bandgap and enhanced optical absorption, we simulate these structures by keeping the other Si1
xGex material properties, such as the electron/hole mobility, equal to that in Si material [11]. Since Si1
xGex grown on Si is susceptible to dislocations due to which minority carrier lifetime decreases, we use simulation to study their effect on the performance of Si1
xGex solar cells. Minority carrier lifetime, s, of Si1
xGex layer is treated as a parameter by modifying smax for holes and electrons in the SRH Scharfetter recombination TCAD model [4]. Minority carrier lifetime values for all layers of simulated structures of Fig. 7.1 are listed in Table 7.1, along with respective impurity doping concentrations. For substrate doping of 1019 cm
3, expected lifetime is approximately 1 ms [17], but we do consider value of 1 ms as well (for HJ structure of Fig. 7.1A) in order to rule out possible contribution of substrate in optically generated current, by comparing performance of the same cell with sSubstrate ¼ 1 ms and sSubstrate ¼ 1 ms. For a-Si:H emitter, lifetime was fixed

110

7. Modeling and simulations of Si1-x Gex based solar cells

TABLE 7.1 Main parameters used for Technology Computer Aided Design (TCAD) simulations [11]. Region

Na or Nda (cmL3)

Eg (eV)a

ca

nþ a-Si emitter

1019

1.7

3.89

10e6

Intrinsic a-Si (HIT)

1010

1.7

3.89

10e6

Strained c-Si (HIT)

1010

0.95

4.05

sA (variable)

4.05

sA (variable)

p-Si1
xGex active layer

16

Eg (x)

16

10

b

s (s)a

p-Si1
xGex grade layer (HIT)

10

Eg (x)

4.05

sA (variable)

pþ-Si substrate

1019

1.12

4.05

HJ

HIT

10

10e6

e3

Na and Nddimpurity concentrations; Egdbandgap; cdelectron affinity; sdcarrier lifetime. Eg(x)dvaries with x [15].

a

b

at 1 ms for both structures, sufficient for very thin layers regardless of the actual material quality. Main parameters used in TCAD simulations for simple Si1
xGex HJ from Fig. 7.1A and HIT solar cell from Fig. 7.1B are summarized in Table 7.1. Moreover, the structures in Fig. 7.1 are also used to study the effect of front surface recombination velocity, SF, at a-Si/c-Si1
xGex interface [11]. Recombination due to interface defects is simulated by introducing surface recombination velocity at relevant interfaces. Table 7.2 summarizes surface recombination values used at different interfaces for both structures shown in Fig. 7.1.

TABLE 7.2 Summary of surface recombination values used for Technology Computer Aided Design (TCAD) simulations. Interface

Variable

Cell type

Value (cm/s)

a-Si/c-Si1LxGex

Front surface recombination velocity, SF

HJ cell (Fig. 7.1A)

Variable: 0e106

i a-Si/strained c-Si

Front surface recombination velocity, SF

HIT cell (Fig. 7.2A)

Variable: 0e106

Si1LxGex buffer/Si substrate

Back surface recombination velocity, SB

HIT cell (Fig. 7.2A)

1000

7.3 Si1
xGex single-junction cells

111

7.3.1 a-Si/c-Si1LxGex heterojunction solar cell An a-Si/c-Si1
xGex/c-Si heterostructure shown in Fig. 7.1A is studied by simulations for the effects of Ge content (x ¼ 0, 0.2, 0.5, 0.75, and 1), Si1
xGex thickness, Si1
xGex lifetime, and a-Si/c-Si1
xGex interface on the performance of the cell. Band diagram of simulated a-Si/c-Si0.5Ge0.5/c-Si HJ cell under equilibrium conditions (V ¼ 0) is shown in Fig. 7.2, with conduction band offset (Ec) of approximately 0.15 eV between a-Si and Si1
xGex [16]. For 50% Ge content, the bandgap of absorber layer reduces to 0.9 eV as compared to 1.12 eV for Si. Fig. 7.3 shows the open-circuit voltage, Voc, as a function of the minority carrier lifetime for different Ge percentages for a 2-mm-thick Si1
xGex layer. These simulation results imply that Voc reduces with increasing Ge fraction, as expected, but it can be improved close to the level of the pure Si (w0.65 V) if a minority carrier lifetime is 1 ms in Si1
xGex layers. Similarly, as bandgap reduces, short-circuit current density, Jsc, increases with increasing Ge content, as shown in Fig. 7.4 for 2- and 8-mm-thick Si1
xGex absorber layer. It can be observed that for Si1
xGex alloys with large Ge content (above 50%) Jsc is almost same for both absorber thicknesses, indicating that for high Ge percentage thinfilm provides sufficient collection of photogenerated carriers. The efficiency of the solar cell can give us further insights into the cell material requirements as it is a strong function of the material quality and the carrier lifetime. The efficiency as a function of minority carrier lifetime for the 8- and 2-mm-thick Si1
xGex layer is shown in Fig. 7.5. Simulation results indicate that for low material quality the efficiency does not depend on the Ge percentage significantly. For 8-mm-thick

FIGURE 7.3 Voc versus Si1
xGex lifetime for an HJ a-Si/c-Si1
xGex/c-Si solar cell for varying Ge content, x [11,12].

112

7. Modeling and simulations of Si1-x Gex based solar cells

FIGURE 7.4 Jsc versus Ge fraction, x, for the a-Si/c-Si1
xGex/c-Si HJ solar cell, shown for 2- and 8-mm-thick Si1
xGex with lifetime s ¼ 1 ms [11,12].

FIGURE 7.5 Efficiency (%) versus Si1
xGex lifetime for a-Si/c-Si1
xGex/c-Si HJ solar cell with (A) 8-mm and (B) 2-mm-thick Si1
xGex layer shown for different Ge fractions, x [11,12].

7.3 Si1
xGex single-junction cells

113

absorber layer, Si has the highest efficiency for lifetime range between 10 ns and 100 ms (Fig. 7.5A). This is because Voc reduces with increasing Ge content and low lifetime (Fig. 7.3), while also 8-mm-thick Si can absorb sufficient amount of light. On the other hand, if the lifetime is high (around s ¼ 0.1e1 ms) c-Si1
xGex can overtake Si in terms of efficiency for Ge percentages 50% and 75%. This is especially evident for thinner absorber layer (2 mm, Fig. 7.5B) because Si does not absorb enough light to maintain high efficiency, even Voc for relaxed c-Si1
xGex at high lifetime is close to that one of the Si. These results imply that the material quality requirement is less strict for thin cells, which highlights the advantage of using Si1
xGex material as an absorber layer in thin-film solar cells. In addition to recombination in absorber layer the a-Si/c-Si1
xGex performance is affected by quality of interfaces. The interface traps will cause a nonzero surface recombination velocity and are likely to be in the mid-gap of a-Si and Si. Here we study the effect of the interface traps by varying the surface recombination velocity at the a-Si/c-Si1
xGex interface. Simulation results show that open-circuit voltage is susceptible to changes in the interface quality, but short-circuit current density (Jsc) is not. This is because the optically generated carriers are significantly larger than the concentration of carriers that are generated/recombined due to the interface defects [12]. Nevertheless, in the absence of optically generated carriers, the dark current is considerably affected by generation and recombination at the interface trap centers, thus affecting the Voc [12]. Voc as a function of front surface recombination velocity, SF, for HJ solar cell with 2-mm-thick c-Si0.5Ge0.5 absorber layer of variable lifetime is plotted in Fig. 7.6. The results show that interface surface recombination velocity only affects Voc for larger minority carrier lifetime (>100 ns)

FIGURE 7.6 Voc versus a-Si/Si1
xGex surface recombination velocity for an HJ a-Si/ c-Si0.5Ge0.5/c-Si solar cell for increasing lifetime of c-Si0.5Ge0.5 layers [11,12].

114

7. Modeling and simulations of Si1-x Gex based solar cells

FIGURE 7.7 Voc versus a-Si/Si1
xGex surface recombination velocity, SF, for an HJ a-Si/cSi1
xGex/c-Si solar cell for increasing x and 0.1 ms carrier lifetime of c-Si1
xGex layers [11].

inside Si0.5Ge0.5, which implies that the interface defects start to contribute to the dark current for better quality materials. Furthermore, the effect of surface recombination velocity at the heterointerface increases with increasing Ge content, as shown in Fig. 7.7. Even for relatively high lifetime (0.1 ms) of c-Si1
xGex, increasing trap centers at the interface can substantially reduce Voc of a solar cell. These results point out that care must be taken to optimize c-Si1
xGex material quality and improve the a-Si/c-Si1
xGex interface to maintain good Voc and benefit from enhanced optical abruption and increased Jsc with increasing Ge fraction.

7.3.2 nD a-Si/i a-Si/i c-Si/p c-Si1LxGex/c-Si HIT cell In this section, we discuss results of various simulations for nþ a-Si/i a-Si/i c-Si/p c-Si1
xGex/c-Si HIT solar cell (Fig. 7.1B). In this structure, the Si1
xGex layer is separated into active Si1
xGex absorber layer and graded buffer layer. As discussed in earlier chapters, Si1
xGex graded buffer is used in practice to grow high-quality active Si1
xGex layer on top of Si by minimizing strain and dislocation density. In order to achieve highquality Si1
xGex in active layer (SiGe cap), Ge content is increased gradually, starting from Si (x ¼ 0) up to desired Ge fraction, such that 10% Ge is added after every 1 mm thickness of graded buffer. In this section, we analyze performance of an HIT cell for Si1
xGex active layer thicknesses of 2 and 4 mm for Ge fractions of x ¼ 0, 0.2, 0.39, 0.5, and 0.75. These Ge fractions then translate to graded Si1
xGex buffer layer thicknesses of 3, 5, and 6 mm thick used for Ge fractions that are smaller than 30%, smaller than 50%, and larger than 50%, respectively. In practice, material quality

7.3 Si1
xGex single-junction cells

115

of graded Si1
xGex layer is low compared to active SiGe absorber layer is but for simplicity we use equal lifetime for both Si1
xGex layers. Moreover, in simulations presented in this section, we set the back surface recombination velocity, SB, at the interface of Si1
xGex buffer layer and heavily doped c-Si substrates to be equal to 1000 cm/s. In this section, we use TCAD simulations to study the effects of TCAD modeled graded layer, a-Si emitter and HJ, Ge percentage, Si1
xGex layer lifetime, and Si1
xGex layer thickness [11]. However, TCAD does not have built-in definition of Si1
xGex alloys and this is mostly due to the fact that its material properties, its bandgap, and optical parameters do not change linearly with increasing Ge fraction. Thus, for every Ge fraction of Si1
xGex graded layer, TCAD requires new material definition, which can be tedious. Thus, here we first investigate simplifying way of simulating graded buffer, where instead of graded Si1
xGex buffer we use either fixed Ge percentage or Si layer, as two extreme Ge percentages in a graded layer. In order see the error margin that this approach can give us, we compare those two structures that are illustrated in Fig. 7.8A and B (Structure A and B) for cell with x ¼ 0.39 (i.e., active layer is Si0.61Ge0.39). Note that Ge content is chosen based on available optical data. Recall that graded buffer thickness depends on Ge content in active Si1
xGex layer, so for x ¼ 0.39 we use 5-mm-thick grade layer. Fig. 7.9 shows simulated Voc (A) and Jsc (B) as a function of Si1
xGex lifetime, s, for structures A and B and with surface recombination velocities, SF, at the a-Si/c-Si interface, and SB at the Si1
xGex graded layer/ Si-substrate interface equal to 1000 cm/s. Simulation results imply that the effect due to bandgap and optical parameters of the graded layer on the overall solar cell results is small [11] and it justifies our use of simple Si1
xGex with fixed Ge fraction instead of graded buffer layer (structure A) for the rest of analysis carried out in this section. We can conclude that error due to this approach in graded buffer modeling, for any given lifetime, is within w10 mV for Voc and w1.5 mA/cm2 for Jsc. Next, we confirm by simulation, the benefits of a-Si emitter and HIT cell design that is needed to maintain higher Voc for Si1
xGex cells with narrow bandgap. For that purpose, we compare simulation results for structure A and structure C of Fig. 7.7 for Si0.61Ge0.39 HIT and homojunction solar cells, respectively. The homo-junction cell (structure C, Fig. 7.7C) uses nþ doped Si0.61Ge0.39 layer as an emitter. Fig. 7.10 compares simulated Voc values as a function of the minority carrier lifetime (sn ¼ sp) for a 4-mm-thick Si0.61Ge0.39 layer of structure A (a-Si emitter) and structure C (Si0.61Ge0.39 emitter). Increasing Ge content reduces the bandgap of Si1
xGex material (w0.93 eV for Si0.61Ge0.39) which in turn increases the generation leakage of the diode, resulting on low Voc. However, using a-Si with wide bandgap (1.7 eV) as the n-type

116

7. Modeling and simulations of Si1-x Gex based solar cells

FIGURE 7.8 Cross section of a-Si:H/c-Si1
xGex/c-Si HIT cells. (A) Structure A: using Si1
xGex instead of a graded buffer, (B) Structure B: using Si as graded buffer, and (C) Structure C: c-Si1
xGex homo-junction cell with Si1
xGex as graded buffer and emitter, all simulated for x > 0.39. Layer thicknesses are not to scale [11,18].

emitter helps create a barrier for those additional thermally generated carriers and prevents them from reaching the contact. As a result, such HJ diode is expected to reduce the reverse leakage thus increasing Voc [12]. This was also confirmed by simulation as shown in Fig. 7.10. We further simulate HIT cell whose structure is shown in Fig. 7.1B for variable absorber layer thickness and for Ge fractions of x ¼ 0, 0.25, 0.39, 0.5, and 0.75. Based on the Ge content, SiGe graded buffer layer thickness

7.3 Si1
xGex single-junction cells

117

FIGURE 7.9 Simulation results for the structures A and B for x ¼ 0.39, 5-mm-thick graded buffer and 4-mm Si0.61Ge0.39 active layer showing (A) Voc and (B) Jsc [11].

is set to be either 3 mm (for x ¼ 0.25), 5 mm (for x ¼ 0.39 and 0.5), or 7 mm (for x ¼ 0.75). Si1
xGex HIT solar cells are simulated for active absorber layer thickness of 1, 2, 4, and 6 mm [11]. Since with increasing Ge content the bandgap of the Si1
xGex material decreases, Voc of the Si1
xGex HIT cell is going to decrease, while Jsc is expected to increase. Simulation results in Fig. 7.11 show Voc values as a function of Ge fraction, x, for 2-mm-thick Si1
xGex absorber layer with different Si1
xGex lifetimes s ¼ 0.01e10 ms. The back and front surface recombination velocities are both fixed to the value of 103 cm/s. In addition to Voc dependence on Ge content, simulation results also indicate that Voc is strongly dependent on the Si1
xGex material quality (i.e., lifetime) [11,14].

118

7. Modeling and simulations of Si1-x Gex based solar cells

FIGURE 7.10 Voc versus Si0.61Ge0.39 lifetime comparing the heterojunction a-Si/cSi0.39Ge0.61 solar cell to a homo-junction Si0.39Ge0.61 solar cell, with Si0.39Ge0.61 as the graded buffer [11,12].

FIGURE 7.11 Voc versus Ge fraction, x, simulated for x ¼ 0, 0.2, 0.39, 0.5, and 0.75 for 2mm Si1
xGex absorber layer with Si1
xGex lifetimes of s ¼ 0.01e10 ms. Relaxed Si1
xGex bandgap from Braunstein [15] shown for comparison [11]. Adapted with permission from S. Abdul Hadi, P. Hashemi, N. DiLello, A. Nayfeh, J.L. Hoyt, Thin film a-Si/c-Si1
xGex/c-Si heterojunction solar cells with Ge content up to 56%, in 2012 38th IEEE Photovoltaic Specialists Conference, 2012.

Furthermore, as thicker films absorb more of incident light and result in higher photogenerated current, we investigate Si1
xGex absorber layer effects on Jsc. Fig. 7.12 shows simulated Jsc as a function of Ge fraction x for structures with 1-, 2-, 4-, and 6-mm-thick Si1
xGex active absorber layer. Simulation results indicate that Jsc dependence on the absorber thickness reduces with increasing Ge fraction, as expected. This is due to the fact that Ge has high absorption coefficient, meaning that thinner layers with

7.3 Si1
xGex single-junction cells

119

Jsc versus Ge fraction, x, simulated for x ¼ 0, 0.2, 0.39, 0.5, and 0.75 for Si1
xGex absorber layer thickness of 1, 2, 4, and 6 mm [11]. Reprinted with permission from S. Abdul Hadi, P. Hashemi, N. DiLello, et al., Effect of c-Si1
xGex thickness grown by LPCVD on the performance of thin-film a-Si/c-Si1
xGex/c-Si heterojunction solar cells, in MRS Online Proceedings Library 1447, 2012.

FIGURE 7.12

high Ge fraction can absorb more light than thicker layers with less Ge content. For example, as shown in Fig. 7.12, Si solar cell with 6-mm-thick absorber layer is expected to generate Jsc w18 mA/cm2, while 1-mm-thick Si1
xGex absorber layer with x ¼ 0.39 can generate Jsc w21 mA/cm2. Simulation results in Fig. 7.12 assume Si1
xGex lifetime, s ¼ 1 ms, and back and front surface recombination velocities, SB and SF, fixed to 103 cm/s. These results confirm the advantage of Si1
xGex in use for thin-film solar cells.

7.3.3 Summary In this section, we present a simulation model and results for simple nþ a-Si/p c-Si1
xGex HJ and nþ a-Si/i a-Si/i c-Si/p c-Si1
xGex HIT cells. Simulation results confirmed important role of a-Si emitter and HIT design for cells with narrow bandgap absorber, such as Si1
xGex. Furthermore, results suggest that with increasing Ge fraction, shortcircuit current increases, while open-circuit voltage decreases, as expected based on the bandgap of Si1
xGex absorber layer. Simulations also suggest strong dependence of solar cell performance on the material quality and lifetime, with estimates that Si1
xGex HIT cells with Ge content higher than 40% can outperform Si solar cells for high material quality (s > 100 ms). However, results also indicate that as Ge fraction increases, dependence on the material quality reduces for thinner absorber layers, since sufficient number of carriers is absorbed close to the junction and so long diffusion length is not required.

120

7. Modeling and simulations of Si1-x Gex based solar cells

Finally, we investigated effects of the Si1
xGex absorber layer thickness on the performance of the HIT nþ a-Si/i a-Si/p c-Si1
xGex cells with 1, 2, 4, and 6 mm absorber layers. Results showed that the Jsc decreases with decreasing absorber layer thickness, but its dependence on the thickness decreased with increasing Ge content.

7.4 GaAs0.76P0.24/Si1LxGex/Si single-junction solar cells In this section we analyze by simulations GaAs0.76P0.24/Si1
xGex/Si SJ solar cell using Sentaurus TCAD by Synopsys, where GaAs0.76P0.24 SJ cell is grown on Si substrate via graded Si1
xGex buffer. The cross section of the analyzed cell is shown in Fig. 7.13, while the same structure is also fabricated, with details and characterization results published in Ref. [20]. Use of Si1
xGex graded buffer allows for the growth of high-quality III-V layers on Si substrates because lattice mismatch between the two can be minimized by reaching a specific Ge content within Si1
xGex graded buffer. The details of growing III-V on Si are explained in Chapter 6 and earlier in this book. Simulation results presented here are compared to measurements of experimentally fabricated cells and simulation model is adjusted accordingly to achieve best match between simulation and experiment. Matching simulation to an experiment gives an insight into material properties and loss mechanisms of fabricated GaAs0.76P0.24/Si1
xGex/Si cells. The loss factors that can be quantified by means of simulations, among others, include an effect of absorber thickness, diffusion length (carrier lifetime), interface and surface recombination, or other optical

FIGURE 7.13 Cross section of simulated SJ GaAs.76P0.24 cell on Si1
xGex/Si substrate, as in Ref. [20], with 8.7% contact shading. Figure not to scale. Reprinted with permission from S. Abdul Hadi, T. Milakovich, E.A. Fitzgerald, A. Nayfeh, Detailed characterization for TCAD simulations of GaAs0.76P0.24/Si1
yGey/Si single junction solar cells, in 2017 IEEE 44th Photovoltaic Specialist Conference (PVSC), Washington, 2017.

7.4 GaAs0.76P0.24/Si1
xGex/Si single-junction solar cells

121

losses. Analyzing currentevoltage characteristics together with quantum efficiency (QE) and reflectance (R) can help distinguish between different types of losses. Experimental characterization of GaAsP cell grown on Si1
xGex/Si substrate showed threading dislocation density, TDD, w2  0.5  106 cm
2 [20], which can be estimated to translate into minority carrier lifetime of w7 ns [22]. Those GaAs0.76P0.24/Si1
xGex/Si cells have exhibited relatively wide range of Voc values, between 1 and 1.23 V, implying that dominant cause for recombination losses can vary from cell-to-cell on a given substrate and should be investigated.

7.4.1 Simulation model For simulations we use physics-based TCAD model, activating major models and parameters, as explained in Section 7.2. Models and options used in these simulations include: TMM, AM 1.5G standard spectra [5], SRH recombination model (effective lifetime, s) and Auger and Radiative recombination model (TCAD default parameters), thermionic emission, hetero-interface carrier transport models, and FermieDirac statistics. Si1
xGex graded buffer layer is modeled as a stack of different 1-mmthick layers with Ge fraction increasing from 10% to 70% (10%/mm) [21]. Material properties of Si1
xGex alloy for each Ge percentage are defined using basic properties of Si which are modified such that optical properties and Eg are updated using data from Refs. [7,15]. Bandgap of GaAs0.76P0.24 material is set to 1.71 eV [20], a value that is extracted from measured internal quantum efficiency (IQE) based on Urbach’s rule [23]. Optical parameters are used from measurements on separately prepared GaAs0.76P0.24/Si1
xGex/Si stacks [10], while InGaP optical properties are used from Ref. [8] with bandgap Eg_InGaP ¼ 2 eV. Band diagram of simulated GaAs0.76P0.24/Si1
xGex/Si cell in equilibrium (under 0 V bias and in the dark) is shown in Fig. 7.14 [21]. It can be observed that simulated space charge region is around 120 nm and that built-in potential is Vbi w1.61 eV, in agreement with experimentally extracted values [21]. Minority carrier lifetime, s, of Si substrate and Si1
xGex layers are fixed at 10
5 and 10
7 s, respectively [24,25], while lifetime of GaAsP base, emitter, and InGaP material as well as surface recombination velocity, S (cm/s), at different interfaces are all treated as variables. Variable parameters are varied and simulation results are compared to the range of experimental values, in order to find combination of those variables that gives the best match between experiment and simulations. Experimental performance parameters of GaAs0.76P0.24/Si1
xGex/Si cell that are used for fine-tuning of the simulation model are chosen for the best and the

122

7. Modeling and simulations of Si1-x Gex based solar cells

FIGURE 7.14 Band diagram of simulated single-junction GaAs0.76P0.24/Si1
xGex/Si cell under equilibrium conditions. Reprinted with permission from S. Abdul Hadi, T. Milakovich, E.A. Fitzgerald, A. Nayfeh, Detailed characterization for TCAD simulations of GaAs0.76P0.24/ Si1
yGey/Si single junction solar cells, in 2017 IEEE 44th Photovoltaic Specialist Conference (PVSC), Washington, 2017.

worst performing cells from given fabrication batch. Those experimental values are listed in Table 7.3 [20,21].

7.4.2 Simulation results The structure shown in Fig. 7.13 is simulated for different values of effective GaAs0.76P0.24 minority carrier lifetime, sGaAsP, where base and emitter lifetime are set to be equal and no interface defects are taken into consideration (S ¼ 0 cm/s at all interfaces). Results in terms of Jsc (left axis) and Voc (right axis) are shown in Fig. 7.15 as a function of sGaAsP. Results in Fig. 7.15 also show values for different InGaP minority carrier lifetime, sInGaP, while dashed lines indicate the range of experimentally observed Jsc and Voc. Simulation results imply that Voc has strong dependence on GaAsP carrier lifetime, and it can be estimated that sGaAsP TABLE 7.3 Experimental performance parameters for GaAs0.76P0.24/Si1
xGex/Si cell [20,21]. Jsc (mA/cm2)

Voc (V)

Fill factor (FF)

Efficiency (%)

Area (cm2)

Shading (%)

Upper limit

11.00

1.22

0.829

11.20

0.01

8.7

Lower limit

11.97

1.04

0.754

9.94

0.16

7.4

Cell

7.4 GaAs0.76P0.24/Si1
xGex/Si single-junction solar cells

123

FIGURE 7.15 Simulated Jsc (left) and Voc (right) versus effective GaAsP minority carrier lifetime, shown for different InGaP lifetime values. Also shown are the ranges for experimental Jsc and Voc values using dashed lines. Reprinted with permission from S. Abdul Hadi, T. Milakovich, E.A. Fitzgerald, A. Nayfeh, Detailed characterization for TCAD simulations of GaAs0.76P0.24/Si1
yGey/Si single junction solar cells, in 2017 IEEE 44th Photovoltaic Specialist Conference (PVSC), Washington, 2017.

ranges from w0.1 to w50 ns. Exact value of GaAs0.76P0.24 minority carrier lifetime depends on other recombination losses, including the effective carrier lifetime in InGaP window layer, as can be seen in Fig. 7.15. On the other hand, results in Fig. 7.15 show that Jsc is quite sensitive to InGaP lifetime, which could be expected. InGaP window layer absorbs some of the incident light so it can either contribute to photogenerated current for high-quality InGaP layer, or it can cause parasitic absorption in case of low carrier lifetime, decreasing the overall photogenerated current. Considering InGaP minority carrier lifetime and Jsc values in addition to Voc results narrows GaAs0.76P0.24 effective lifetime between 0.5 and 10 ns [21]. The effect of InGaP window layer and its lifetime is visualized by simulated external quantum efficiency (EQE) characteristics shown in Fig. 7.16. Results are shown for various InGaP lifetime values, while GaAs0.76P0.24 absorber and emitter lifetimes are set to 1 and 0.5 ns, respectively, and no interface defects are assumed (S ¼ 0 cm/s). Simulation results imply that InGaP window layer can contribute to photogenerated current significantly by absorbing wavelengths between 300 and 400 nm. This shows importance of keeping the window layer quality as high as possible while choosing its optimum thickness. Even though matching simulation results to values listed in Table 7.3, it is also important to look in Quantum Efficiency data while fine-tuning the variable parameters for best match. Further investigation (not shown here) indicates that sGaAsP impacts more strongly the collection at the long

124

7. Modeling and simulations of Si1-x Gex based solar cells

FIGURE 7.16 Simulated EQE for variable sInGaP ¼ 0.1e10 ns, and GaAs0.76P0.24 absorber lifetime ¼ 1 ns, emitter lifetime ¼ 0.5 ns, and all S ¼ 0 cm/s. Reprinted with permission from S. Abdul Hadi, T. Milakovich, E.A. Fitzgerald, A. Nayfeh, Detailed characterization for TCAD simulations of GaAs0.76P0.24/Si1
yGey/Si single junction solar cells, in 2017 IEEE 44th Photovoltaic Specialist Conference (PVSC), Washington, 2017.

wavelengths, while short wavelength response is strongly affected by the quality and thickness of the InGaP window layer, as expected [21]. We further investigate effect of surface recombination velocity, S, at many of the InGaP window interfaces of simulated structure. Fig. 7.17

FIGURE 7.17 Jsc (left axis) and Voc (right axis) versus surface recombination velocity S (cm/s) at the window layer interface, for base sGaAsP ¼ 1e10 ns. Also shown is the range of experimental Jsc and Voc. Reprinted with permission from S. Abdul Hadi, T. Milakovich, E.A. Fitzgerald, A. Nayfeh, Detailed characterization for TCAD simulations of GaAs0.76P0.24/ Si1
yGey/Si single junction solar cells, in 2017 IEEE 44th Photovoltaic Specialist Conference (PVSC), Washington, 2017.

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xGex/Si single-junction solar cells

125

shows simulated values of Jsc and Voc as a function of S at the InGaP window interface. For those results, lifetime of GaAs0.76P0.24 base is varied between sGaAsP ¼ 1e10 ns and window and emitter lifetime are set to 0.5e5 ns. Simulation results in Fig. 7.17 imply that Jsc is more sensitive to surface recombination at window interface, while Voc is more dependent on the material quality of the base layer, sGaAsP. After comparing simulated results in Fig. 7.17 to the experimental values we can estimate that the minority carrier lifetime of GaAsP layer, sGaAsP, is approximately equal to 5 ns, while S at the top interface can be anything between 104 and 106 cm/s [21]. Finally, simulation parameters are updated based on the experimentally observed values where the base doping and layer thicknesses are adjusted based on the device TEM image [20]. Furthermore, the surface recombination, S, values are activated at all the interfaces with III-V materials and are varied, to find the best match with experimental data. Fig. 7.18 shows the best match between experimental [20] and updated simulation results for JV (a) and QE (b) data. Also shown in figures are all fine-tuned simulation parameters. The selected absorber GaAs0.76P0.24 layer minority carrier lifetime, sGaAsP, is 10 ns and this agrees with expected lifetime associated with TDDs value of this III-V growth on SiGe/Si substrate [20,22,26,27]. Moreover, the interface recombination at the emitterebase interface is set to Sbase ¼ 105 cm/s, based on the experimental extraction of Voc at 0 K [21], while surface recombination at the interface between emitter and window is modeled as 100 cm/s. The GaAsP emitter and InGaP lifetime are both set to 5 ns. We can observe a better match in JV characteristics compared to some discrepancies in QE data of simulated and experimental results. This is because EQE simulations do not account for shading losses (8.6%), and because of reflectance mismatch possibly due to discrepancies in optical properties of III-V layers.

7.4.3 Summary In this section we analyzed GaAs0.76P0.24/Si1
xGex/Si cell by means of simulations which were fine-tuned by using experimental results obtained for the same cells. Using this approach, we estimated that the lifetime of GaAs0.76P0.24 base layer that is grown on Si1
xGex/Si substrate is approximately 10 ns, as expected based on TDDs for those fabricated cells. Simulations also indicate that InGaP lifetime is around 5 ns and that this window layer can significantly affect to photogenerated current, depending on the carrier lifetime. TCAD model and analysis approach presented here show a good fit for currentevoltage characteristics, but

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FIGURE 7.18 Comparison of updated simulations and experimental results for (A) JV and (B) EQE, IQE, and R data. Also shown are updated simulation parameters. Reproduced from T. Milakovich, R. Shah, S. Abdul Hadi, M. Bulsara, A. Nayfeh, E. Fitzgerald, Growth and characterization of GaAsP top cells for high efficiency IIIeV/Si tandem PV, in 2015 IEEE 42nd Photovoltaic Specialist Conference (PVSC), New Orleans, 2015. Reprinted with permission from S. Abdul Hadi, T. Milakovich, E.A. Fitzgerald, A. Nayfeh, Detailed characterization for TCAD simulations of GaAs0.76P0.24/Si1
yGey/Si single junction solar cells, in 2017 IEEE 44th Photovoltaic Specialist Conference (PVSC), Washington, 2017.

modeling more accurate spectral response requires further and more detailed analysis while using accurate material optical properties.

7.5 Effect of Si1LxGex graded buffer on bottom Si cell As we have described in previous section, GaAsP cell of acceptable quality can be grown on Si1
xGex graded buffer that is grown on an Si substrate. Typically, graded buffer layers are utilized for monolithically

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grown MJ solar cells as they help minimize TDD formed due to lattice mismatch between Si and III-V materials deposited on it. Advantage of using this approach is mainly low cost of Si substrate and mature Si-based processing technology. Moreover, for DJ solar cells, almost optimum bandgap combination is formed by top cell bandgap of w1.7 eV (i.e., GaAsP material) and Si bottom cell (more on this we will discuss in the following sections). However, use of this approach for the fabrication of monolithic DJ solar cell with Si bottom cell is challenging due to narrow bandgap of Si1
xGex. Namely, Si1
xGex energy bandgap is lower than that of an Si, which means that Si1
xGex graded buffer has wider optical response than Si and if thick enough, it can negatively affect optical generation within the bottom Si cell [14,19]. To grow lattice matched and dislocation free GaAsP layer with Eg w1.7 eV, SiGe graded buffer needs to have w60% of Ge content, which means Si1
xGex graded buffer thickness is w5e6 mm [20]. As discussed in earlier sections of this chapter, we know that Si1
xGex films as thin as 2 mm absorb significant amount of light, due to high absorption coefficient of Si1
xGex, especially at high Ge content. For monolithic MJ solar cell with Si bottom cell this means that Si cell will receive very small amount of light, generating very low current and limiting performance of the entire MJ solar cell. To mitigate this problem, in our earlier work we have proposed a step-cell design, where parts of the bottom Si cells are exposed to incident light by etching away III-V/SiGe stack above it [10,28,29]. To study this effect experimentally, our group has also fabricated Si1
xGex buffer on top of the SJ Si cell, and we have then analyzed the effects of step-cell design on bottom Si cell. Details on fabrication method and experimental results can be found in Ref. [28], while here we just focus on simulations of the equivalent structure and verification of our step-cell TCAD model. Simulation results for structure shown in Fig. 7.19 are presented here [10,28,29]. Step-cell design is realized by varying Atotal/Atop ratio, where Atotal represents the total area of the cell area, while Atop represents area of the top cell. In our case discussed here, in the absence of the top cell, Atop represents the area of the part of Si cell that is filtered by Si1
xGex buffer (ASiGe). For simulations, we keep Atotal fixed value, while ASiGe (Atop) is varied such that Atotal/Atop ratio ranges from 1 (no Si cell exposed, conventional cell design) to 2, where half of Si cell is exposed to unfiltered incident light [10,28].

7.5.1 Simulation model As mentioned earlier in this chapter, in 2D TCAD simulations, 1D optical problem is solved by taking a cross section of the device (so-called “Line”) while considering the same optical profile for the user-specified

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FIGURE 7.19 Cross section of fabricated step-cell designed Si cells with SiGe graded buffer layer. The Atotal/Atop ratio was varied from 1.0 to 1.8. (Note: When Atotal/Atop ¼ 1, no Si cell is exposed.) Figure not to scale [10]. Adapted with permission from S. Abdul Hadi et al., Novel GaAs0.71P0.29/Si tandem step-cell design, in 2014 IEEE 40th Photovoltaic Specialist Conference (PVSC), Denver, 2014.

region (called “Window”). Having one “Line” and one “window” assumes uniform cross section across the entire simulated device. However, this is not the case for step-cell structure shown in Fig. 7.19, where we have two distinct optically active cross sections (ignoring “in dark” parts under the contact). To be able to simulate optical generation within the step-cell, we need to define two separate optical profiles, one across Atop area (first illumination window for Si1
xGex/Si stack) and another across Astep area (second illumination window for Si bottom cell) [10]. The effect of the step-cell design is simulated by changing the two cross section “Line” positions and two illumination windows width according to the Atop and Astep variations [10]. The best fit to experimental data is achieved by setting Si minority carrier lifetime equal to 50 ms and 100 ns for Si1
xGex material and distributed contact resistance of 40 mU cm2. Graded Si1
xGex buffer is designed as a stack of 1-mm-thick SiGe layers whose Ge content, x, is increased from 0.1 to 0.6 with Dx ¼ 0.1/1 mm. As was the case in other simulations, electrical properties of Si1
xGex are set to be same as the Si ones, while optical parameters and bandgap are kept fixed for each Ge fraction [7,15,30]. Interface surface recombination velocity, S, is set to 103 cm/s at the interfaces: (1) SiO2/strained Si cap, (2) Si0.8Ge0.2 cap/ Si0.4Ge0.6 layer, and (3) above the n-Si emitter at SiO2/Si and Si1
xGex (x ¼ 0.1)/Si.

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7.5.2 Simulation results Fig. 7.20 shows simulated values for Jsc, efficiency, and Voc as a function of Atotal/Atop ratio [10]. Also shown are experimentally measured median values for fabricated cell as shown in Fig. 7.19 [28]. Simulation and experimental results closely agree with each other, implying that used step-cell TCAD model is valid and can be used for further MJ step-cell simulations. While there are some discrepancies between simulated and experimental results, both types of results have the same trend, a steady rise of Jsc with increasing Atotal/Atop ratio. As can be seen from the simulation results in Fig. 7.20, Si1
xGex graded buffer severely lowers the current in the Si cell underneath it (w5 mA/cm2). This means that III-V/Si1
xGex//Si monolithic MJ cell applications with bottom junction placed in Si are not feasible in conventional tandem cell design where top and bottom cells have equal areas. It is still possible to utilize monolithic III-V/Si cells with Si1
xGex graded buffer if the step-cell design is used and parts of the bottom Si cells are exposed to direct incident light, boosting the photogeneration in bottom cell thus mitigating some of the optical losses in Si1
xGex and yielding a higher bottom cell current. While the step-cell design is discussed here as a way to reduce parasitic optical absorption in Si1
xGex graded buffer in monolithic DJ configuration, it can also be used as additional optimization factor for bonded MJ solar cell (more on this will be discussed in the following sections). Furthermore, step-cell design can aid faster lift-off process where III-V cells grown on SiGe/Si substrate are lifted off and then bonded to another cell. More on the advantages of step-cell design in fabrication of III-V/Si bonded cells will be discussed in Chapter 8.

FIGURE 7.20 Simulated Jsc, efficiency, and Voc values for Si cell with Si1
xGex graded buffer on top (x ¼ 0e0.6) using step-cell design. Also shown is the range of experimental Jsc, h, and Voc values along with the median values and error bars [10,29].

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7.6 Simulation of GaAs0.71P0.29/Si dual-junction step-cell: monolithic and bonded structures In earlier sections we have introduced a step-cell design and discussed how it can help mitigate optical losses in Si1
xGex graded buffer for monolithic MJ solar cells, or how it can speed up the lift-off process of III-V cells needed for bonded MJ solar cells. Here we present TCAD simulation results for GaAs0.71P0.29/Si DJ step-cell. The analysis presented here investigates the effect of Si1
xGex graded buffer on the performance of the monolithic DJ step-cell while comparing it to the simulation results for bonded GaAs0.71P0.29/Si cell. Two simulated structures are shown in Fig. 7.21. Fig. 7.21 shows cross section of monolithic GaAs0.71P0.29/SiGe/Si DJ step-cell with graded Si1
xGex (x ¼ 0e0.6) buffer layer (A) and bonded GaAs0.71P0.29/Si DJ step-cell (B). Variable Atotal represents total area of the DJ cell (and bottom Si cell) and Atop represents the area of the top GaAsP cell. When Atotal/Atop ¼ 1, no Si is exposed to unfiltered light and thus a conventional tandem cell is simulated. When Atop decreases and Atotal is kept fixed, Atotal/Atop ratio increases and DJ step-cell is simulated. TCAD model presented here was optimized for Si1
xGex/Si structures discussed in previous section, but it was not fine-tuned to actual GaAs0.71P0.29/Si experimental data. However, simulation results, even though they may not be closely matched to experimental data, can still provide insights into performance trends we can anticipate for conventional and step-cell for bonded and monolithic GaAs0.71P0.29/Si structures.

FIGURE 7.21 Cross section of GaAs0.71P0.29/Si DJ step-cell for variable Atotal/Atop ratio with (A) monolithic DJ cell with SiGe graded buffer layer (structure A) and (B) bonded DJ cell (structure B) (Note: When Atotal/Atop ¼ 1 conventional tandem cell is simulated) [10,29]. Adapted with permission from S. Abdul Hadi et al., Novel GaAs0.71P0.29/Si tandem step-cell design, in 2014 IEEE 40th Photovoltaic Specialist Conference (PVSC), Denver, 2014.

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7.6.1 Simulation model For analysis presented here, DJ step-cell structures shown in Fig. 7.21 are simulated. Structure in Fig. 7.21A is used to analyze performance trends for GaAs0.71P0.29/Si1
xGex/Si monolithic DJ step cell, while structure in Fig. 7.21B is used to analyze bonded GaAs0.71P0.29/Si cell, where it is assumed that GaAs0.71P0.29 is grown on Si1
xGex/Si substrate, lifted off and then bonded with bottom Si cell. For both types of DJ solar cell simulations the following parameters for bottom Si cell are used: 650-mm-thick p-type absorber with NA ¼ 1016 cm
3 and 1-mm-thick n-type emitter with ND ¼ 5  1018 cm
3 where maximum minority carrier lifetime, smax, is varied between 0.1 and 1 ms [25,31] and is modeled to be doping dependent. The top GaAs0.71P0.29 cell comprises of 100-nm-thick emitter, while absorber layer thickness and absorber effective lifetime are treated as variables (s ¼ 10 ps to 10 ns [27,32]). Interface surface recombination velocity is set to 103 cm/s and is considered in the model at the following interfaces: (1) ARC/GaAs0.71P0.29 emitter, (2) GaAs0.71P0.29 base/ Conductive Layer, and (3) at the interfaces above the Si emitter [10,29]. Note that GaAs0.71P0.29 top cell of the structure shown in Fig. 7.21 does not include InGaP back-surface field or window layer (refer to Fig. 7.13 and discussion in Section 7.4). We have shown earlier that InGaP window layer can significantly affect Voc and Jsc of the top cell, thus not including window layer here can be source of possible overestimates of top cell performance. However, these simulations give us useful information on the behavior of step-cell in monolithic and bonded structures. Cells are simulated with 70-nm-thick Si3N4 as antireflective coating (ARC) and 4% contact shading where shading percentage is calculated from the top cell area, Atop. This means that total shading losses decrease for bottom cell when Atotal/Atop ratio is increased (i.e., when Atop decreases, contact width decreases, resulting in less shading of total area Atotal). Complex refractive indices of GaAs0.71P0.29 are utilized from Ref. [10] while optical properties of other materials (SiGe, Si, Si3N4) are obtained from Refs. [30,33]. For this model, the TCAD default bandgap of GaAs0.71P0.29 is used which is equal to 1.67 eV [10,29]. For Si1
xGex bandgap is utilized from Ref. [15]. Top and bottom cells are connected in series. Practically, tunnel diode is used to connect two subcells in a monolithic structure, but we were unable to implement it due to convergence issues in TCAD equation solver. Instead, two subcells are connected in series by using a thin gold layer [10,34]. To avoid any optical interference and losses between the two subcells, the optical properties of interconnect gold layer are changed in SDevice Parameter file such that absorption is equal to zero while

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refractive index is set to Si to avoid any internal reflectance. Using this model to simulate the connection between two subcells means that optical and resistive losses at the interface between the two subcells are not taken into consideration. Optical absorption is modeled such that there is a “cut-off” at material bandgap value (in SDevice Command file in Physics-Optics section, Quantum Yield is set to be a step-function of effective bandgap). Meshing in the step cell is designed using the same approach as was used for conventional cell, where the number of nodes horizontally used for equation solving is made as a function of total width of a solar cell. However, since step-cell design involves variable horizontal features, cell mesh design changes with changing Atotal/Atop ratio, which can affect error margins of simulated results. While outside the scope of this work, we should mention that interesting research topic would be to study the dependence of simulation results on horizontal number of nodes in a mesh design of step-cell. Although the step-cell design for Si1
xGex filtered SJ Si cell introduced in earlier section fits experimental data fairly good, the model’s sensitivity on the mesh can change when two or more junctions are connected in series [10].

7.6.2 Results: monolithic and bonded GaAs0.71P0.29/Si step-cell Fig. 7.22 shows simulated Jsc (mA/cm2) (A), open-circuit voltage Voc (V) (B), and efficiency, h (%) (C) for monolithic GaAs0.71P0.29/Si1
xGex/Si (structure A) compared to bonded GaAs0.71P0.29//Si (structure B), as a function of Atotal/Atop ratio [29] and for 2-mm-thick GaAs0.71P0.29 absorber layer. The effective minority carrier lifetime for GaAs0.71P0.29 layers is set to 10 ns. For monolithic GaAs0.71P0.29/Si1
xGex/Si cell (structure A) simulation results in 7.22 confirm strong absorption in Si1
xGex layer, resulting in a very low current and efficiency for conventional design (Atotal/Atop ¼ 1). When Atotal/Atop ratio is increased (Atop is decreased and bottom cell is exposed), bottom Si cell photogenerated current increases since more of the unfiltered incident light is absorbed in the bottom cell. Results indicate that as bottom cell current increases overall tandem cell efficiency increases with increasing Atotal/Atop ratio. Maximum efficiency is achieved when current matching between two subcells is achieved. For the case of 2-mm-thick GaAs0.71P0.29 absorber layer illustrated in Fig. 7.22, the maximum efficiency is achieved for Atotal/Atop ¼ 1.3, followed by efficiency decrease for larger Atotal/Atop ratio, as the top cell current becomes the limiting factor [10]. Furthermore, we can see that Voc increases steadily with increasing Atotal/Atop ratio, due to increased optical generation in the bottom cell (Fig. 7.22B).

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Simulated results for (A) Jsc (mA/cm2), (B) Voc (V), and (C) efficiency (%) for monolithic GaAs0.71P0.29/Si1
xGex/Si and bonded GaAs0.71P0.29//Si dual-junction stepcells, as a function of Atotal/Atop ratio [10,29]. Reprinted with permission from S. Abdul Hadi et al., Novel GaAs0.71P0.29/Si tandem step-cell design, in 2014 IEEE 40th Photovoltaic Specialist Conference (PVSC), Denver, 2014.

FIGURE 7.22

For bonded GaAs0.71P0.29//Si structure (black lines), the current density and efficiency are much higher than in the monolithic structure due to absence of optical and recombination losses within SiGe graded buffer layers. This is especially evident for conventional cell when no parts of the bottom Si cell are exposed to unfiltered light. Simulations indicate that for bonded GaAs0.71P0.29//Si with 2-mm-thick GaAs0.71P0.29 absorber cell, bottom Si cell is the one with a lower current and a limiting performance factor. This implies that efficiency of bonded cells can also be improved by increasing Atotal/Atop ratio in cases when top cell thickness or bottom cell material quality is not optimized for current matching condition. Furthermore Fig. 7.23 shows simulated currentevoltage (JeV) characteristics for GaAs0.71P0.29//Si bonded DJ step-cells and monolithic GaAs0.71P0.29/Si1
xGex/Si DJ step-cell for optimum Atotal/Atop ratio for 2 mm GaAs0.71P0.29 absorber layer with a lifetime of s ¼ 10 ns. The structures shown in Fig. 7.21 are further analyzed for different GaAs0.71P0.29 absorber layer thicknesses. Fig. 7.24 shows simulated efficiency (%) for given GaAs0.71P0.29 thickness with optimized Atotal/Atop ratio for bonded and for monolithic structures. Simulations imply that when top GaAs0.71P0.29 cell is thin (below 1 mm), enough light reaches

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FIGURE 7.23 Simulated JeV characteristics for bonded GaAs0.71P0.29//Si and monolithic GaAs0.71P0.29/Si1
xGex/Si DJ step-cells for 2 mm GaAs0.71P0.29 absorber layer with a lifetime of s ¼ 10 ns and optimum Atotal/Atop ratio [29]. Reprinted with permission from S. Abdul Hadi et al., Novel GaAs0.71P0.29/Si tandem step-cell design, in 2014 IEEE 40th Photovoltaic Specialist Conference (PVSC), Denver, 2014.

FIGURE 7.24 Simulated efficiency (%) for given GaAs0.71P0.29 thickness with optimized Atotal/Atop ratio for bonded structures and those with Si1
xGex buffer layers [10,29]. Reprinted with permission from S. Abdul Hadi et al., Novel GaAs0.71P0.29/Si tandem step-cell design, in 2014 IEEE 40th Photovoltaic Specialist Conference (PVSC), Denver, 2014.

bottom Si cell so bonded GaAs0.71P0.29//Si tandem cell is optimized when designed as a conventional tandem cell (Atotal ¼ Atop). However, for monolithic DJ cells, Si1
xGex graded buffer layer absorbs most of the light intended for the bottom cell, the optimum design requires Atotal/Atop >1

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even for very thin GaAs0.71P0.29 layers. As the top cell absorber thickness increases, more of the bottom Si cell needs to be exposed to achieve current matching condition and optimum performance [29]. However, this trend cannot go indefinitely, as the top cell starts to have the limiting current due to its reducing surface area. Simulations imply that the optimum Atotal/Atop ratio is a function of the subcell absorption coefficients, bandgap, thickness, material quality, parasitic optical losses, ARC, etc. This means that Atotal/Atop ratio can be used as added optimization design parameter for MJ solar cells, especially when subcell optical parameters, bandgap, or thickness cannot be optimized for current matching in conventional tandem cell design.

7.7 Other simulations for bonded III-V//Si dual-junction solar cells As mentioned earlier, Si1
xGex/Si stack can be used as a starting substrate for the growth of high-quality III-V layers. Those III-V layers can form a subcell for MJ solar cell. III-V cells grown on Si1
xGex/Si substrate can be removed by epitaxial lift-off and then transferred onto a bottom cell, forming bonded MJ solar cell. In this section we give a brief overview of some of our previous work focusing on optimization problems for bonded III-V//Si DJ solar cells. One aspect of analysis is looking into optimum bandgap combination and an MJ design. For this we give an overview of detailed balance method used to find theoretical upper efficiency limit of DJ solar cell as a function of bandgap of two subcells, with special attention to step-cell design (introduced earlier in this chapter). Part of the optimization is also looking into adjusting ARC to achieve maximum current matching and thus optimum efficiency of DJ solar cell.

7.7.1 Detailed balance efficiency limit for DJ III-V/Si solar cell In this section we present theoretical efficiency limit calculated using a detailed balance method for two-terminal (2T) DJ “step-cell” under AM 1.5G incident spectrum [35,36]. Detailed balance method provides the thermodynamic upper efficiency limit of a solar cell [37e39]. For 2T DJ solar cell, detailed balance theoretical upper efficiency limit was estimated to be in the range between 42% and 45%, when the top cell has energy bandgap of Eg w1.6e1.64 eV while bottom cell bandgap Eg w0.94e0.96 eV [40e42].

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As outlined in our earlier work in Ref. [38, p. 3] the detailed balance method includes assumptions: (1) radiative recombination only; (2) all photons with energy greater than material bandgap are absorbed and those with energy lower than the material bandgap are transmitted; (3) one absorbed photon results in one electron hole pair (quantum efficiency QE ¼ 1); (4) all emitted thermal photons are reflected back to the cell and (5) there are no resistive and reflective losses.

Fig. 7.25 shows schematic representation of a DJ step-cell used in analysis presented here, where total area of the device (Atotal) is composed of an area of the top cell (Atop) and the area of the exposed part of the bottom cell (Astep), with Atotal ¼ Atop þ Astep [35]. Top and bottom cell bandgaps are EgT and EgB, respectively. For this analysis, optical generation in the bottom cell is modeled in two regions: (1) step part whose absorption is limited by the bottom cell bandgap, and (2) conventional part, whose absorption is also additionally limited by the top cell bandgap. In Fig. 7.25 photon energies absorbed in each of the subcells are indicated, based on detailed balance assumptions. For example, the top cell absorbs all the photons with energies above its bandgap (hn > EgT), as well as does step part (hn > EgB). However, the filtered part of the bottom cell absorbs photons that have passed through the top cell without being absorbed but their energies are also greater than the bandgap of the bottom cell bandgap (EgB < hn < EgT). Electrically, top and bottom cells in Fig. 7.25 are connected in series, but the bottom cell has dual optical input: (1) one filtered by top cells and (2) a step part exposed to full incident spectrum. Total tandem cell current, I, is equal to the smallest current of all subcell currents: IB for bottom or IT for top subcell. Due to series connection, the open-circuit voltage across the

FIGURE 7.25 Illustration of the two-terminal DJ step-cell, illustrating photon energy range absorbed in each subcell and the step part. Reprinted with permission from S. Abdul Hadi, E.A. Fitzgerald, A. Nayfeh, Theoretical efficiency limit for a two-terminal multi-junction “step-cell” using detailed balance method, J. Appl. Phys. 119 (2016) 073104.

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tandem cell is the sum of the open-circuit voltages across bottom (VB) and top (VT) subcell and is defined as V ¼ VT þ VB. Resistive losses and load effects when current matching is not achieved are ignored for analysis presented here. All results presented here are obtained by simulations done using MATLAB [10,35]. Input AM 1.5G spectrum is utilized from NREL [5] and it is considered for the range between 280 and 2000 nm, with interpolated 5 nm equal wavelength step. Input optical power is assumed to be 1000 W/m2, a default standard for AM 1.5G spectrum. For analysis presented here, subcells bandgap and Atotal/Atop ratio are considered as variables. Specifics and equations of detailed balance method for step-cell structure are explained in depth in Refs. [10,35,36]. If a reader would like to implement detailed balance method, we advise looking up those references. As mentioned earlier, the optimum performance of a 2T MJ solar cell is achieved when subcell currents are equal (current matching condition). For conventional MJ cell (Atotal ¼ Atop) this means that there is one specific optimum combination of the energy bandgaps, Eg, and absorber thicknesses of subcells at which subcell current will match. Fig. 7.26 shows upper efficiency limit of conventional 2T two-junction (2J) cell under AM 1.5G incident spectra, as a function of bottom and top cell bandgaps, calculated using detailed balance method [10]. For conventionally designed 2J tandem cell under AM 1.5G incident spectra, maximum theoretical efficiency is w46% which is obtained for 1.64 and 0.96 eV top and bottom cell bandgaps, respectively.

FIGURE 7.26 Efficiency of a 2J conventional tandem cell (Atotal/Atop ¼ 1) as a function of top and bottom cell bandgap under AM 1.5G spectra [10].

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Further, step-cell is analyzed for combination of three optimum parameters, top and bottom cell bandgap and Atotal/Atop ratio. With increasing Astep (increasing Atotal/Atop ratio) bottom cell current increases but total area of the device increases, limiting maximum efficiency of a step-cell. Furthermore, thermalization losses in a step part of the bottom cell increase with higher Astep area [10]. Thus, for each subcell bandgap combination in 2J tandem step-cell, there is also an optimum Atotal/Atop ratio which results in the maximum step-cell efficiency. Fig. 7.27 shows the step-cell efficiency under AM 1.5G spectrum as a function of Atotal/Atop ratio (Atotal/Atop ¼ 1e2) where subcells bandgaps are optimized for each ratio. Results imply that maximum efficiency of w46% is theoretically attainable for conventionally designed cell (Atotal/ Atop ¼ 1, Fig. 7.27 dashed line). However, efficiency decreases with increasing Atotal/Atop ratio due to increasing total area and limited top cell current. While conventional tandem cell has the highest theoretical efficiency for optimum subcell bandgap combination, the step-cell design can be used to improve the efficiency of tandem cell with conventionally nonoptimized bandgaps (Fig. 7.27, full lines). The benefits of the step-cell design when subcells bandgaps are not optimized can be illustrated by comparing maximum efficiency for conventional and step-cell design for bandgap values optimized for each Atotal/Atop ratio, as shown in Fig. 7.28 [35]. Horizontal axis shows bottom and top cell bandgaps, EgB and EgT, optimized for each Atotal/Atop ratio. Also shown in Fig. 7.28 is the upper efficiency limit of a conventional

FIGURE 7.27 Efficiency of a two-junction (2J) step-cell as a function of Atotal/Atop ratio for optimized bandgap combinations for each Atotal/Atop ratio (from 1 to 2) under AM 1.5G spectrum. Reprinted with permission from S. Abdul Hadi et al., Theoretical efficiency limits of a 2 terminal dual junction step cell, in 2015 IEEE 42nd Photovoltaic Specialist Conference (PVSC), New Orleans, 2015.

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FIGURE 7.28 Upper efficiency limit for two-junction (2J) step-cell (black circles) and conventional 2J cell (Atotal ¼ Atop, red stars; gray in print version), for bandgap combinations optimized for each Atotal/Atop ¼ 1e2 ratio, under AM 1.5G incident spectrum and T ¼ 300 K. Horizontal axis shows optimum bottom and top cell bandgaps, EgB and EgT, for each Atotal/ Atop value. Reprinted with permission from S. Abdul Hadi, E.A. Fitzgerald, A. Nayfeh, Theoretical efficiency limit for a two-terminal multi-junction “step-cell” using detailed balance method, J. Appl. Phys. 119 (2016) 073104.

tandem cell (Atotal ¼ Atop) calculated for the same subcell bandgap combinations as for optimized step-cell. We further analyze the upper efficiency limit of a silicon-based 2J stepcell. Results are illustrated in Fig. 7.29 and show that maximum efficiency limit of w45% can be obtained for conventional tandem cell with top cell bandgap of EgT w1.74 eV. Fig. 7.29 shows Si-based step-cell efficiency limit as a function of Atotal/Atop ratio (x-axis) and top cell bandgap EgT (y-axis) [36]. Here we can see that using Si-based step-cell we can achieve conversion efficiency range between 40% and 45% even when nonoptimized top cell bandgap values are used, ranging between w1.5 and 1.9 eV and Atotal/Atop ratio varying between 1 and 1.3. With decreasing top cell bandgap, optimum Atotal/Atop ratio increases, as less of the top cell area is required due to an increase light absorption in the narrow-bandgap top cell. These results imply that step-cell approach can provide benefits when top cell bandgap is lower than the ideal bandgap that would provide current matching bandgap (EgT w1.74 eV for Si bottom cell) or when there is any another reason why bottom cell would have the limiting current.

7.7.2 Optimizing antireflective coating for GaAs1LyPy/Si DJ solar cell In this section we briefly look into the role of ARC design in optimization of the DJ bonded GaAsP//Si cells. Fig. 7.30 shows schematics of a

140

7. Modeling and simulations of Si1-x Gex based solar cells

FIGURE 7.29 Theoretical upper efficiency limit of two-junction (2J) Si-based step-cell as a function of top cell bandgap, EgT (eV), and Atotal/Atop ratio under AM 1.5G illumination [10]. Reprinted with permission from S. Abdul Hadi et al., Theoretical efficiency limits of a 2 terminal dual junction step cell, in 2015 IEEE 42nd Photovoltaic Specialist Conference (PVSC), New Orleans, 2015.

FIGURE 7.30 Schematics of the cross section for GaAs1
yPy/Si tandem cell analyzed for ARC optimization. Reprinted with permission from S. Abdul Hadi, T. Milakovich, M. Bulsara, S. Saylan, M.D. Dahlem, E.A. Fitzgerald, A. Nayfeh, Design optimization of single-layer antireflective coating for GaAs1
xPx/Si tandem cells with x ¼ 0, 0.17, 0.29 and 0.37, IEEE J. Photovoltaics 5 (1) (2015).

7.7 Other simulations for bonded III-V//Si dual-junction solar cells

141

cross section of bonded GaAsxP1
x//Si DJ cell used for ARC optimization in the analysis presented here. The simulated structure with dimensions of each layer, impurity concentration, and minority carrier lifetimes of each layer are illustrated in Fig. 7.30 and are simulated using TCAD by Synopsis. GaAs1
xPx layer thickness is treated as a variable to find optimum tandem cell design with matching subcell currents. Minority carrier lifetime, s, of Si is modeled as doping dependent in Physics section of SDevice Synopsys tool and its maximum value is set to 1 ms consistent with high-quality c-Si wafer [25,31]. GaAs1
yPy absorber effective lifetime is analyzed for the range between 10 ps and 1 ms, according to the values reported in literature for GaAs epi growth on Si1
xGex graded buffers [27] and pure GaAs materials [32]. Values for energy bandgap for GaAs1
yPy are utilized from Ref. [44], while for Si and GaAs default values from TCAD are used [43]. The two subcells are connected in series using highly conductive layer (gold) in TCAD whose optical properties are modified to ignore any absorption losses (absorption coefficient is set to zero) and any interface reflection losses (refractive index is set to that of Si) [43]. As an optimization indicator we investigate the efficiency of a tandem cell, identifying the best ARC design based on the highest efficiency value of GaAs1
yPy/Si DJ cell. GaAs1
yPy/Si tandem cells are simulated for number of ARC materials where ARC and GaAs1
yPy thicknesses are varied to find optimum design for a given GaAs1
yPy lifetime. Complex refractive indices for ARC materials, GaAs and Si, are used from Refs. [30,33] while optical parameters of GaAs1
yPy (y ¼ 0.17e0.37) are obtained from Refs. [9,10]. Finally, SiO2/Si3N4 double layer antireflective coating (DLARC) is optimized for the most efficient GaAs1
yPy/Si tandem cell and compared to optimum single layer antireflective coating (SLARC) design. Fig. 7.31A shows simulated maximum efficiency for GaAs1
yPy/Si tandem cell as a function of GaAs1
yPy absorber layer thickness (y ¼ 0, 0.17, 0.29, and 0.37) for optimized Si3N4 ARC thickness and for GaAs1
yPy lifetime s ¼ 10 ns. Corresponding optimized Si3N4 ARC thickness for each of the maximum efficiency values obtained is shown in Fig. 7.31B. We can see that maximum efficiency of GaAs1
yPy/Si DJ cell is achieved for 250 nm, w400 nm, and w1 mm thick GaAs1
yPy absorber layer for y ¼ 0, 0.17, 0.29, and 0.37, respectively. Maximum efficiency achieved for these GaAs1
yPy alloys ranges from w20% to w26% and is obtained for Si3N4 ARC thickness of w70 nm, w65 nm, w72, and w75 nm for y ¼ 0, 0.17, 0.29, and 0.37, respectively (Fig. 7.31B). From the simulation results presented in Fig. 7.31B we can observe that optimum ARC thickness increases with increasing GaAs1
yPy absorber layer thickness. This trend is expected because more light is absorbed in thicker top cell, resulting in less optical generation inside the bottom cell. Thus, ARC thickness is adjusted such that it minimizes

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7. Modeling and simulations of Si1-x Gex based solar cells

FIGURE 7.31 (A) maximum efficiency of GaAs1
yPy/Si tandem cell at (B) corresponding optimum Si3N4 ARC thickness (nm) as a function of GaAs1
yPy absorber layer thickness for y ¼ 0, 0.17, 0.29, and 0.37 and GaAs1
yPy lifetime s ¼ 10 ns [10,43]. Reprinted with permission from S. Abdul Hadi, T. Milakovich, M. Bulsara, S. Saylan, M.D. Dahlem, E.A. Fitzgerald, A. Nayfeh, Design optimization of single-layer antireflective coating for GaAs1
xPx/Si tandem cells with x ¼ 0, 0.17, 0.29 and 0.37, IEEE J. Photovoltaics 5 (1) (2015).

the reflection of longer wavelengths that are mostly absorbed in the bottom cell. Moreover, due to the same reason, thicker ARC trend for cells with lower P fraction (y ¼ 0 and 0.17) can be also observed in Fig. 5.5B. Since the bandgap of the top GaAs1
yPy cell increases from w1.43 eV at y ¼ 0 to w1.88 eV for y ¼ 0.37 [44], the top cell with lower bandgap absorbs more of the solar spectrum. Thus, less light is reaching the bottom cell and the ARC thickness is optimized to boost the current in the bottom cell. We further investigate ARC design optimization for different ARC materials, using GaAs0.71P0.29/Si tandem cell (P fraction is fixed at y ¼ 0.29) with various GaAs0.71P0.29 minority carrier lifetime. Fig. 7.32A shows maximum efficiency of GaAs0.71P0.29/Si tandem cell with optimized GaAs0.71P0.29 absorber layer and ARC thickness, as a function of sGaAsP, and for different ARC materials. We can see that Si3N4, Al2O3, and HfO2 materials result in higher efficiency compared to case when SiO2 or ITO is used for ARC. However, this advantage reduces at a lower material quality. Fig. 7.32B shows corresponding optimum ARC thickness as a function of s for GaAs0.71P0.29/Si tandem cell with optimum top cell absorber thickness [43]. Optimum ARC thickness increases as material quality of the top cell increases, to reduce reflection of long wavelength and boost photogeneration in the bottom cell. Similarly, in case of poor top cell material quality (low lifetime), ARC thickness decreases so that optical generation in top cell is increased. Fig. 7.33 shows currentevoltage characteristics of GaAs1
yPy/Si tandem cells (y ¼ 0, 0.17, 0.29, and 0.37) with optimum combinations of SLARC and GaAs1
xPx absorber layer thicknesses with GaAs1
xPx lifetime equal to 10 ns [43].

7.7 Other simulations for bonded III-V//Si dual-junction solar cells

143

FIGURE 7.32

(A) Maximum efficiency and (B) optimum SLARC thickness as a function of GaAs0.71P0.29 minority carrier lifetime, s, for GaAs0.71P0.29/Si tandem cell with optimum GaAs0.71P0.29 absorber thickness [10,43]. Reprinted with permission from S. Abdul Hadi, T. Milakovich, M. Bulsara, S. Saylan, M.D. Dahlem, E.A. Fitzgerald, A. Nayfeh, Design optimization of single-layer antireflective coating for GaAs1
xPx/Si tandem cells with x ¼ 0, 0.17, 0.29 and 0.37, IEEE J. Photovoltaics 5 (1) (2015).

FIGURE 7.33 JV characteristics of GaAs1
yPy/Si tandem cells (y ¼ 0, 0.17, 0.29, and 0.37) with optimum SLARC and GaAs1
yPy absorber layer thicknesses with GaAs1
yPy lifetime equal to 10 ns [10,43]. Reprinted with permission from S. Abdul Hadi, T. Milakovich, M. Bulsara, S. Saylan, M.D. Dahlem, E.A. Fitzgerald, A. Nayfeh, Design optimization of single-layer antireflective coating for GaAs1
xPx/Si tandem cells with x ¼ 0, 0.17, 0.29 and 0.37, IEEE J. Photovoltaics 5 (1) (2015).

In order to observe additional benefits of using double layer ARC, we analyze best performing tandem cell, with 1 mm thick GaAs0.71P0.29 absorber layer. Simulation results show that best reflection suppression for these cell parameters is achieved for DLARC of 75 nm SiO2/60 nm Si3N4 stack [43]. Fig. 7.34 compares simulated reflectance and EQE of

FIGURE 7.34 EQE (red) and reflectance (blue) curves for 1 mm GaAs0.71P0.29/Si tandem cell with 75 nm Si3N4 SLARC (full line) and 75 nm SiO2/60 nm Si3N4 DLARC (dashed line). GaAs0.71P0.29 lifetime equals to 10 ns [10,43]. Reprinted with permission from S. Abdul Hadi, T. Milakovich, M. Bulsara, S. Saylan, M.D. Dahlem, E.A. Fitzgerald, A. Nayfeh, Design optimization of single-layer antireflective coating for GaAs1
xPx/Si tandem cells with x ¼ 0, 0.17, 0.29 and 0.37, IEEE J. Photovoltaics 5 (1) (2015).

GaAs0.71P0.29/Si tandem cell with 1 mm thick GaAsP absorber for 75 nm Si3N4 SLARC and 75 nm SiO2/60 nm Si3N4 DLARC. Use of SiO2/Si3N4 DLARC overall reflectance is decreased (for l ¼ 300e450 nm and l > 700 nm), resulting in improved spectral response of both subcells, and in higher Jsc and efficiency, as shown in JeV characteristics plotted in Fig. 7.35.

FIGURE 7.35 JV characteristics of GaAs0.71P0.29/Si of top, bottom, and tandem cell for 75 nm Si3N4 SLARC (full lines) and 75 nm SiO2/60 nm Si3N4 DLARC (dashed lines). GaAs0.71P0.29 lifetime equals to 10 ns [10,43]. Reprinted with permission from S. Abdul Hadi, T. Milakovich, M. Bulsara, S. Saylan, M.D. Dahlem, E.A. Fitzgerald, A. Nayfeh, Design optimization of single-layer antireflective coating for GaAs1
xPx/Si tandem cells with x ¼ 0, 0.17, 0.29 and 0.37, IEEE J. Photovoltaics 5 (1) (2015).

7.8 Conclusion

145

7.8 Conclusion In this chapter we have given an overview of the various simulations of Si1
xGex based cells, including Si1
xGex HIT cells, monolithic III-V/ Si1
xGex/Si tandem cells, and bonded III-V/Si cells where it is assumed that III-V layers are fabricated via Si1
xGex/Si graded buffers. We also provided an overview of TCAD simulation tools and models, as most of the results discussed here are obtained using TCAD by Synopsis. Furthermore, step-cell concept is discussed in more depth and its advantages are discussed through means of simulations by TCAD and by looking into theoretical efficiency limit based on detailed balance method. Results presented in this chapter show that Si1
xGex has good potential to be used for thin-film cells because layers as thin as 2 mm can absorb significant amount of light. The problem of low energy bandgap associated with increasing Ge fraction, x, causes low Voc in solar cells and can be mitigated by using wide bandgap a-Si as an emitter in a-Si/Si1
xGex HIT solar cell configuration. Furthermore, we have discussed how graded Si1
xGex buffer layers can also be used to grow lattice matched high-quality III-V layers for the purpose of tandem cells, in particular GaAs1
yPy cells. These tandem cells can be either monolithic GaAs1
yPy/Si1
xGex/Si or bonded GaAs1
yPy//Si where GaAs1
yPy top cell of bonded configuration is also fabricated on Si1
xGex/Si substrate, then lifted off and bonded to separately fabricated bottom Si cell. In this study we have shown how strongly Si1
xGex graded buffer layer absorbs the incident light intended for the bottom cell, lowering significantly current in the bottom Si cell and limiting overall efficiency of a tandem cell when used in monolithic configuration. We then introduced step-cell design to reduce optical losses in Si1
xGex graded buffer layers for monolithic GaAs1
yPy/Si1
xGex/Si DJ solar cells. By means of TCAD simulations we showed that efficiency of the monolithic tandem cell can be improved significantly when parts of bottom Si cells in step-cell design are exposed to unfiltered incident light. Furthermore, we also analyzed the step-cell design for bonded GaAsP/Si cell and showed that when subcell thickness or material quality is not optimized to achieve current matching condition, step-cell can still improve performance of the bonded cells as well. Moreover, we investigated theoretical efficiency limit of a step-cell by detailed balance method, which showed that highest efficiency is still achieved for conventional tandem design (when both, top and bottom cells have same area), but that step-cell can provide significant efficiency improvements for materials and bandgap combinations that are not

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7. Modeling and simulations of Si1-x Gex based solar cells

optimum. This means that by using step-cell design we relax other stringent requirements of high material quality or optimum layer thickness or bandgap, which are often difficult to fine-tune. Finally, we presented TCAD simulations for importance and effects of ARC design for GaAs1
yPy/Si DJ cells. Simulation results showed that ARC depends on subcell layer bandgap, thickness, and material quality. ARC layer thickness is adjusted to boost optical generation in either one of the subcells when there is need. For example, for thick top cell layers, there is not enough light reaching the bottom cell, so optimum single layer ARC thickness is increased so that reflection at longer wavelengths is minimized. Similarly, for very thin top cell layer or poor top cell carrier lifetime, thinner SLARC layers are optimum as they minimize reflection at shorter wavelengths that are absorbed in top cell. Simulations of solar cells provide an important insight into device behavior even when simulated values are not exactly matching the experiment. By using simulations, we can anticipate the behavior and trends in a certain experiment, while saving the time and resources by experimentally implementing only devices that showed promising results in simulations.

References [1] SYNOPSYS. Available at: http://www.synopsys.com/Tools/TCAD/Pages/default. aspx. [2] Synopsis TCAD, “User Manual”. [3] Sentaurus Device User Guide, Version D-2010.03, March 2010. [4] D.S. Lee, J.G. Fossum, A physical model for the dependence of carrier lifetime on doping density in nondegenerate silicon, Solid State Electron. 25 (8) (1982) 741e747. [5] National Renewable Energy Laboratory (NREL), Renewable Resource Data Center. Available at: http://rredc.nrel.gov/solar/spectra/am1.5/. (Accessed 26 February 2012). [6] S. Smilab, n-k Database. Available at: http://www.sopra-sa.com/. [7] E. Kasper, Properties of Strained and Relaxed SiGe, Institution of Electrical Engineers, London, 1995. [8] B. Conrad, et al., Optical characterisation of III-V alloys grown on Si by spectroscopic ellipsometry, Sol. Energy Mater. Sol. Cell. 162 (2017) 7e12. [9] T. Milakovich, et al., Optical Properties of MOCVD Grown GaAs1
xPx Epi Layers on SiGe Graded Buffers, 2015. [10] S. Abdul Hadi, III-V on Si Multi-Junction Step-Cell: PhD Dissertation, Masdar Institute of Science and Technology, Abu Dhabi, 2016. [11] S. Abdul Hadi, MSc Thesis: Si1-xGex Thin Film Heterojunction Solar Cells, Abu Dhabi, 2012. [12] S. Abdul Hadi, P. Hashemi, A. Nayfeh, J.L. Hoyt, a-Si/c-Si1-xGex/c-Si heterojunction solar cells, in: International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2011. [13] S. Abdul Hadi, P. Hashemi, N. DiLello, E. Polyzoeva, A. Nayfeh, J.L. Hoyt, Thin-film Si1-xGex HIT solar cells, Sol. Energy 103 (2014) 154e159.

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[14] S. Abdul Hadi, P. Hashemi, N. DiLello, A. Nayfeh, J.L. Hoyt, Thin film a-Si/c-Si1
xGex/ c-Si heterojunction solar cells with Ge content up to 56%, in: 2012 38th IEEE Photovoltaic Specialists Conference, 2012. [15] R. Braunstein, A.R. Moore, F. Herman, Intrinsic optical absorption of germaniumsilicon alloys, Phys. Rev. 109 (3) (1958) 695e710. [16] J.P. Kleider, A.S. Gudovskikh, P. Cabarrocas, Determination of the conduction band offset between hydrogenated amorphous silicon and crystalline silicon from surface inversion layer conductance measurements, Appl. Phys. Lett. 92 (2008) 162101e162103. [17] J.A. del Alamo, R.M. Swanson, Modeling of minority carrier transport in heavily doped silicon emitters, Solid State Electron. 30 (11) (November 1987) 1127e1136. [18] S. Abdul Hadi, P. Hashemi, A. Nayfeh, J.L. Hoyt, Thin film a-Si/c-Si1-xGex/c-Si heterojunction solar cells: design and material quality requirements, ECS Trans. 41 (4) 3e14. [19] S. Abdul Hadi, P. Hashemi, N. DiLello, et al., Effect of c-Si1-xGex thickness grown by LPCVD on the performance of thin-film a-Si/c-Si1-xGex/c-Si heterojunction solar cells, in: MRS Online Proceedings Library 1447, 2012. [20] T. Milakovich, R. Shah, S. Abdul Hadi, M. Bulsara, A. Nayfeh, E. Fitzgerald, Growth and characterization of GaAsP top cells for high efficiency IIIeV/Si tandem PV, in: 2015 IEEE 42nd Photovoltaic Specialist Conference (PVSC), New Orleans, 2015. [21] S. Abdul Hadi, T. Milakovich, E.A. Fitzgerald, A. Nayfeh, Detailed characterization for TCAD simulations of GaAs0.76P0.24/Si1-yGey/Si single junction solar cells, in: 2017 IEEE 44th Photovoltaic Specialist Conference (PVSC), Washington, 2017. [22] K. Hayashi, T. Soga, H. Nishikawa, T. Jimbo, M. Umeno, MOCVD growth of GaAsP on Si for tandem solar cell applications, in: Proceedings of 1994 IEEE 1st World Conference on Photovoltaic Energy ConversiondWCPEC (A Joint Conference of PVSC, PVSEC and PSE, 1994. [23] H. Helmers, C. Karcher, A.W. Bett, Bandgap determination based on electrical quantum efficiency, Appl. Phys. Lett. 103 (2013). [24] T. Ghani, J.L. Hoyt, D.B. Noble, J.F. Gibbons, J.E. Turner, T.I. Kamins, Effect of oxygen on minority carrier lifetime and recombination currents in Si1-xGex heterostructure devices, Appl. Phys. Lett. 58 (12) (1991) 1317e1319. [25] S. Abdul Hadi, P. Hashemi, N. DiLello, E. Polyzoeva, A. Nayfeh, J.L. Hoyt, Effect of germanium fraction on the effective minority carrier lifetime in thin film amorphousSi/crystalline-Si1-xGex/crystalline-Si heterojunction solar cells, AIP Adv. 3 (5) (2013), 052119-052119-6. [26] M. Yamaguchi, C. Amano, Efficiency calculations of thinfilm GaAs solar cells on Si substrates, J. Appl. Phys. 58 (9) (1985) 3601e3606. [27] C.L. Andre, J.J. Boeckl, D.M. Wilt, A.J. Pitera, M.L. Lee, E.A. Fitzgerald, B.M. Keyes, S.A. Ringel, Impact of dislocations on minority carrier electron and hole lifetimes in GaAs grown on metamorphic SiGe substrates, Appl. Phys. Lett. 84 (18) (2004). [28] E. Polyzoeva, S. Abdul Hadi, A. Nayfeh, J.L. Hoyt, Reducing optical and resistive losses in graded silicon-germanium buffer layers for silicon based tandem cells using step-cell design, AIP Adv. 5 (2015) 057161. [29] S. Abdul Hadi, et al., Novel GaAs0.71P0.29/Si tandem step-cell design, in: 2014 IEEE 40th Photovoltaic Specialist Conference (PVSC), Denver, 2014. [30] Software Spectra Inc., Optical Data from Sopra SA. Available at: http://www.sspectra. com/sopra.html. (Accessed 2016). [31] J.E. Park, D.K. Schroder, S.E. Tan, B.D. Choi, M. Fletcher, A. Buczkowski, F. Kirscht, Silicon epitaxial layer lifetime characterization, J. Electrochem. Soc. 148 (8) (2001) G411eG419. [32] Ioffe Institute, 2014. Available at: http://www.ioffe.ru/SVA/NSM/Semicond/GaAs/ electric.html. [33] Ioffe Institute, n,k Databse. Available at: http://www.ioffe.rssi.ru/SVA/NSM/nk/ index.html. (Accessed 2015).

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[34] Synopsys Inc., 2012. Available at: https://solvnet.synopsys.com. [35] S. Abdul Hadi, E.A. Fitzgerald, A. Nayfeh, Theoretical efficiency limit for a twoterminal multi-junction “step-cell” using detailed balance method, J. Appl. Phys. 119 (2016) 073104. [36] S. Abdul Hadi, et al., Theoretical efficiency limits of a 2 terminal dual junction step cell, in: 2015 IEEE 42nd Photovoltaic Specialist Conference (PVSC), New Orleans, 2015. [37] W. Shockely, H.J. Queisser, Detailed balance limit of efficiency of p-n junction solar cells, J. Appl. Phys. 32 (1961) 510. [38] C. Henry, Limiting efficiencies of ideal single and multiple energy gap terrestrial solar cells, J. Appl. Phys. 51 (1980) 4494. [39] A. Marti, G.L. Arauijo, Limiting efficiencies for photovoltaic energy conversion in multigap systems, Sol. Energy Mater. Sol. Cell. 43 (1996) 203e222. [40] A.S. Brown, M.A. Green, Detailed balance limit for the series constrained two terminal tandem solar cell, Phys. E Low-dimens. Syst. Nanostruct. 14 (1e2) (2002) 96e100. [41] C. Feser, J. Lacombe, K. Maydel, C. Agert, A simulation study towards a new concept for realization of thin film triple junction solar cells based on group IV elements, Prog. Photovoltaics Res. Appl. 20 (2012) 74e81. [42] J.P. Connolly, D. Mencaraglia, C. Renard, D. Bouchier, Designing IIIeV multijunction solar cells on silicon, Prog. Photovoltaics Res. Appl. 22 (2014) 810e820. [43] S. Abdul Hadi, T. Milakovich, M. Bulsara, S. Saylan, M.D. Dahlem, E.A. Fitzgerald, A. Nayfeh, Design optimization of single-layer antireflective coating for GaAs1-xPx/ Si tandem cells with x ¼ 0, 0.17, 0.29 and 0.37, IEEE J. Photovoltaics 5 (1) (2015). [44] G.D. Pitt, C.E.E. Stewart, The electrical properties of GaAs1-xPx alloys from a highpressure experiment, J. Phys. C Solid State Phys. 8 (9) (1975) 1397.

C H A P T E R

6 Lattice matched IIIeV materials on Si via Si1
xGex buffer layer 6.1 Introduction Solar cells based on IIIeV materials are still the ones yielding the highest conversion efficiencies, whether they are single-junction or multijunction (MJ) solar cells [1,2]. However, IIIeV materials are rare and costly, limiting the use of IIIeV solar cells to niche applications and preventing their broad commercial use. For that reason, many researchers are exploring ways to use low-cost IIIeV solar cells and optoelectronic devices, where special attention is given to IIIeV on Si [3e10]. Theoretically, the highest efficiency (w38%) for two-terminal, dualjunction (DJ) solar cell can be reached when the top and bottom bandgaps are 1.7 and 1.1 eV, respectively [11]. This means that Si is a perfect candidate for the bottom cell in DJ solar cells, due to its bandgap, mature processing technology, and mechanical stability, while IIIeV alloys (such as GaAs0.7P0.3) can be utilized for the top cell. However, IIIeV materials and Si have a lattice mismatch and different thermal expansion coefficients, which result in dislocations formation in the IIIeV layers when grown directly on Si substrates [4,12]. Fig. 6.1 illustrates relationship between the energy bandgap and a crystal lattice constant for IIIeV and SiGe alloys, where full lines indicate semiconductors with direct bandgap, while dashed lines show indirect bandgap semiconductors. We can see from Fig. 6.1 that it is possible to achieve lattice match between GaAs1
yPy and Si1
xGex alloys, by carefully selecting proper Ge fraction x and P fraction y (red (gray in print version) and black lines). Similarly, it is possible to lattice match AlInP or GaInP alloys to SiGe. Arrows in Fig. 6.1 illustrate the possible path that can be used to grow

Silicon-Germanium Alloys for Photovoltaic Applications https://doi.org/10.1016/B978-0-323-85630-0.00009-1

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© 2023 Elsevier Inc. All rights reserved.

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6. Lattice matched IIIeV on Si via Si1–xGex buffer layer

FIGURE 6.1 Bandgap versus lattice constant for direct ( full line) and indirect bandgap semiconductor alloys (dashed lines). Gray arrows indicate possible direction for graded buffer growth [3].

lattice matched IIIeV materials on Si. One way is to grow graded Si1
xGex buffer layers [5e7,13] while other way is to start with GaP nucleation on Si followed by graded IIIeV layers, until an alloy with required composition is reached [14]. Recently, a group at the Ohio State University (OSU) has reported improvement in IIIeV/Si monolithic solar cells grown via GaP nucleation and graded GaAsP buffer layer, stating efficiency of 21.8% for cells without ARC layer [15]. More recently team at OSU and their collaborators at University of New South Wales fabricated improved generation of those cells, reporting a monolithic GaAs0.75P0.25/Si tandem cell with efficiency of 23.4% [16]. At about the same time, another group, based at University of Illinois, followed a similar approach and made improvements in the cell design and BSF layer. With these changes, they have achieved efficiency of 25% for GaAsP/Si monolithic two-terminal DJ solar cell grown via GaP nucleation and graded GaAs1
yPy layer [17]. For similar approach, a group at Fraunhofer Institute [18] reported a while back GaInP/GaAs monolithic DJ cell grown on Si substrate using GaP nucleation and GaAsP graded buffer having efficiency of 16.4%, while the equivalent cells grown on lattice matched GaAs substrate had efficiency of 27%. High-quality GaAs or GaAsP solar cells were also fabricated on Si via Si1
xGex graded buffers with virtual Ge or Si1
xGex substrates that are lattice matched to IIIeV layers [5,6,19e21]. Growth of different GaAs1
yPy alloys on Si can be achieved by selecting the appropriate Ge fraction in step-graded Si1
xGex buffer layer, to lattice match the IIIeV layer with the desired P fraction, y. In this section we focus on this type of growth and

6.1 Introduction

87

provide more details on the performance of solar cells grown via Si1
xGex/Si substrates. While IIIeV layers are used for fabrication of single-junction solar cells, the main interest in the research community is to achieve low-cost MJ solar cells, which involves Si-based processing. MJ solar cells could be two-terminal where subcells are connected in series, or can have more terminals, where subcells each have their own probes. Furthermore, MJ can be fabricated by bonding individually fabricated subcells, or by monolithically growing a stack of the subcells on top of each other [22e24]. Fig. 6.2 illustrates a cross section of a typical lattice matched monolithic MJ solar cell grown on Si substrate where the top cell layers are grown monolithically on Si via graded buffer layers [3]. For optimum operation of the two-terminal MJ solar cells, it is important that currents in subcells match. This optimization problem means that bandgap combination of subcells needs to be finely tuned, while the material quality (i.e., minority carrier lifetime and diffusion length) has to be maintained high. Overall, maximizing the efficiency of MJ solar cells involves optimization of the material electrical and optical FIGURE 6.2 Cross section of typical two-junction, two-terminal lattice matched monolithic solar cell with tunnel junction (TJ) in between two subcells [3].

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6. Lattice matched IIIeV on Si via Si1–xGex buffer layer

parameters that all mutually interact and need to be simultaneously considered.

6.2 Lattice mismatch and threading dislocation density Lattice mismatch between Si, Ge, and IIIeV materials (Fig. 6.1) causes strain misfit when these layers are grown epitaxially on each other [13]. When Si1
xGex or GaAs1
yPy layers are grown on the Si substrate, strain misfit increases with increasing Ge or Arsenide (As) fraction because the difference between Si and the grown layer lattice constants increases. Once the strained layer thickness reaches a critical thickness, there is not enough energy that is needed to maintain the strain within SiGe or GaAsP layers, so the lattice in the grown layers begins to relax the strain in the epitaxial film. When lattice in epitaxial film is relaxed it causes defects in the form of misfit dislocations, which degrades optical and thermal properties of grown SiGe or GaAsP layers [27]. These dislocation defects can significantly degrade material carrier lifetime by acting as traps for minority carriers [27]. Decreasing the minority carrier lifetime in epitaxial layers due to threading dislocation defects can substantially reduce conversion efficiency of solar cell devices [25,26]. Solar cells performance is degraded by threading dislocations because these defects act as recombination centers for photogenerated excess carriers, where carriers recombine before they can be collected by the external circuit. Yamaguchi et al. [25] have proposed a theoretical model for effective minority carrier lifetime as a function of threading dislocation density (TDD), as defined in Eqs. (6.1) and (6.2): sTDD ¼

4 p3 ,D,TDD

1 1 1 ¼ þ s smax sTDD

(6.1) (6.2)

where D is diffusivity of the material, TDD is threading dislocation density (cm
2), sTDD is the carrier lifetime due to threading dislocations, and smax is minority carrier lifetime in the absence of TDDs. The dependance of minority carrier lifetime on TDDs is also shown graphically in Fig. 6.3 [3]. Yamaguchi et al. calculated that high threading dislocation density (TDD > 108 cm
2) can considerably reduce efficiency of a solar cell, since open-circuit voltage (Voc) can decrease up to 25% while shortcircuit current density, Jsc, can be reduced by more than 50% [25,28]. Thus, it is very important that threading dislocation density can be minimized in SiGe or GaAsP layers epitaxially grown on Si.

6.2 Lattice mismatch and threading dislocation density

89

FIGURE 6.3 Theoretical dependence of minority carrier lifetime on threading dislocation density, TDD (calculated after [25,26]) [3].

In order to minimize threading dislocation density in GaAs1
yPy layers grown on Si, alloy composition has to be changed gradually, so that lattice constant does not change abruptly, resulting in less strain [29]. One way to grow GaAs1
yPy on Si is to gradually introduce Ge fraction into Si1
xGex graded layers grown on the Si, resulting in a relaxed SiGe layer. Once the desired lattice constant is reached at a certain Ge fraction, IIIeV material nucleation layer followed by IIIeV layer growth can be introduced [21,30]. In this approach, IIIeV layers can also be graded until the IIIeV alloy needed for solar cell is reached. Depositing a SiGe alloy on Si substrate and increasing the Ge fraction by w10% for every 1 mm deposited thickness along with carefully optimized growth conditions have been shown to result in high-quality substrates that are suitable for growth of high-quality IIIeV materials with low threading dislocation density [29]. Using this approach, Milakovich et al. have fabricated GaAs0.76P0.24 solar cells on Si using MOCVD (metal-organic chemical vapor phase deposition) of GaAs0.76P0.24 on Si0.25Ge0.75 graded buffers, which resulted in TDD ¼ 1.9  0.5  106 cm
2, and solar cell efficiency (h) as high as 11.5% [21]. Furthermore, Ringel et al. [19] fabricated GaAs solar cells on Ge/graded SiGe/Si substrates that resulted in high-quality GaAs layers with a TDD lower than 2  106 cm
2. Reducing TDD in IIIeV layers grown on Si for the purpose of MJ solar cells is of great importance because they can substantially reduce minority carrier lifetime and diffusion length, lowering the overall conversion efficiency of the cell. As shown in Fig. 6.3, minority carrier lifetime decreases quickly when TDD exceeds 107 cm
2, thus it is important to keep TDD below this limit for solar cell applications.

90

6. Lattice matched IIIeV on Si via Si1–xGex buffer layer

6.3 Optical and electrical properties of GaAs1LyPy deposited on Si1LxGex Optical data of graded GaAs1
yPy layers are not readily available in literature, especially as there are many different growth methods that affect epitaxial film properties. In Fig. 6.4 we show optical parameters of GaAs1
yPy layers that our collaborators at Massachusetts Institute of Technology (MIT) have grown for different y fractions [3,31]. Fig. 6.4 shows measured absorption coefficient (a) and refractive index (b) of MOCVD grown GaAs1
yPy alloys on Si1
xGex/Si stack. These optical parameters are relevant for GaAsP alloys grown on Si1
xGex graded buffers under specific growth conditions and have been used in simulation works presented in the following chapter. Bandgap values for various GaAs1
yPy alloys are considered to be equal to those reported in Ref. [32], as shown in Fig. 6.5. Those values are also used for simulation work that is detailed later in Chapter 7. However, sometimes experimentally observed bandgap can deviate from the values presented in Fig. 6.5, and it depends on actual growth, as we will see later in this chapter when analysis of fabricated GaAsP cells is described. Some of the electrical properties of bulk silicon, germanium, gallium arsenide, and gallium phosphide materials are summarized in Table 6.1.

FIGURE 6.4 Optical properties of MOCVD grown GaAs1
yPy layers: (A) absorption coefficients and (B) refractive index [3,31].

91

6.4 IIIeV on Si MJ solar cells via Si1
xGex buffer in literature

FIGURE 6.5

Composition dependence of bandgap in GaAs1
yPy (after [32]) [3,33].

TABLE 6.1 Electrical properties of bulk Si, Ge, GaAs, and GaP at 300 K [3]. Si

Ge

GaAs

GaP

Electron mobility, mn (cm2/V-s)

1417

3900

8500

250

Hole mobility, mp (cm2/V-s)

471

1900

400

150

Bandgap (eV)

1.12

0.68

1.42

2.26

Dielectric constant

11.7

16.2

12.9

11.1

Electron affinity (eV)

4.05

4.0 10

Intrinsic carrier concentration, ni (cm
3)

1$10

2.0$10

Lattice constant (A)

5.431

5.658

4.07 13

2.1$10

3.8 6

5.65325

2 5.4505

6.4 IIIeV on Si MJ solar cells via Si1LxGex buffer in literature A number of research groups worldwide have been working on solar cells fabricated on Si substrates via Si1
xGex graded buffer layers. In this section we give an overview of most notable research focusing on these cells, whether cells fabricated were single-junction or MJ solar cells. The work presented here focuses on fabricated devices only and their key findings and improvements over time.

92

6. Lattice matched IIIeV on Si via Si1–xGex buffer layer

6.4.1 InGaP/GaAs grown on Si1LxGex/Si substrates A group from the OSU in collaboration with MIT has a long history of working on IIIeV on Si substrates via Si1
xGex graded buffers, providing early insights into the effect that threading dislocation density in Si1
xGex graded buffers has on material quality of IIIeV layers and solar cell performance [5,6,19,26,29,30,34,35]. One of the first IIIeV cells on Si the group has reported was GaAs single-junction solar cell deposited on Ge/Si1
xGex/Si substrate [19]. Structure of the fabricated cell is shown in Fig. 6.6A and it was reported to have TDD about to 1:5  106 cm
2. Similar structure has been fabricated on Ge substrates for comparison and two cells performances are compared under AM 0 incident spectrum, as shown in Fig. 6.6B. Singlejunction GaAs cells grown in Ge virtual substrates on Si1
xGex/Si carrier were reported to have efficiency of 15.6%, just slightly below the value obtained when same cells are grown on actual Ge wafer [19]. This shows that SiGe graded buffers can be successfully used as a low cost and mechanically stable alternative when Ge wafers may be needed. The same group has fabricated DJ In0.49Ga0.51P/GaAs cells on Si1
xGex/Si substrates (structure shown in Fig. 6.7A). External quantum efficiency (EQE) results show that DJ performance is limited by poor InGaP top cell design that needed further optimization [34]. However,

FIGURE 6.6 (A) Cross section of a single-junction GaAs solar cell structure grown by MOCVD on Ge and Ge/SiGe/Si substrates, and (B) JeV characteristics under AM 0 of GaAs cell fabricated on Ge and Ge/SiGe/Si substrates. Reprinted with permission from S.A. Ringel, et al., Single-junction InGaP/GaAs solar cells grown on Si substrates with SiGe buffer layers, Prog. Photovolt. 10 (2002) 417e426.

6.4 IIIeV on Si MJ solar cells via Si1
xGex buffer in literature

93

FIGURE 6.7 (A) Pþ/n In0.49Ga0.51P/GaAs dual-junction solar cell structure grown on an Si1
xGex/Si substrate and (B) measured external quantum efficiency (EQE) for each subcell. Reproduced with permission from S.A. Ringel, et al., IIIeV multi-junction materials and solar cells on engineered SiGe/Si substrates, Mater. Res. Soc. Proc. 836 (L6.2) (2004).

Ringel et al. showed in Ref. [34] that bottom GaAs cell was of high quality and had same collection properties as equivalent cell fabricated on GaAs substrates. The authors chose the cell polarity with p-type emitter and ntype absorber based on their earlier findings that such configuration was much less prone to TDD-related recombination losses compared to cells with n/p configuration [26]. Similar structure to the one shown in Fig. 6.7 is later fabricated by the same group, but with improved In0.49Ga0.51P top cell material parameters and design, leading to DJ solar cell with efficiency of 16.8%, Voc ¼ 2.18 V, and Jsc ¼ 10.48 mA/cm2, tested under AM 1.5G spectrum [36].

6.4.2 Tandem GaAs0.84P0.16/Si0.18Ge0.82 on Si solar cells Research group at NSW Australia has made significant progress on realizing GaAsP/SiGe tandem cell grown on Si substrates [9,20,37e39]. DJ cells with GaAs0.84P0.16 top cell and Si0.18Ge0.82 bottom cell were fabricated via SiGe graded buffer grown on Si substrate, as shown in Fig. 6.8. The reported efficiency on these tandem cells with ARC layer was 18.9% with Jsc ¼ 18.1 mA/cm2, Voc ¼ 1.45 V, and fill factor (FF) ¼ 0.72 [20]. The peak internal quantum efficiency (IQE) of these cells reaches about 90% for both top and bottom cells, as shown in Fig. 6.9 [20,37]. For

94

6. Lattice matched IIIeV on Si via Si1–xGex buffer layer

FIGURE 6.8 Simplified two-terminal GaAsP/SiGe on Si tandem device structure design. Reproduced with permission from M. Diaz, et al., Tandem GaAsP/SiGe on Si solar cells, Sol. Energy Mater. Sol. Cells 143 (2015) 113e119.

FIGURE 6.9 Quantum efficiency of GaAsP/SiGe top and bottom solar cells with and without ARC measured using light bias. Reproduced with permission from M. Diaz, et al., Tandem GaAsP/SiGe on Si solar cells, Sol. Energy Mater. Sol. Cells 143 (2015) 113e119.

6.4 IIIeV on Si MJ solar cells via Si1
xGex buffer in literature

95

those cells, they report the TDD of 6:2  106 cm
2 that they measured by cathodoluminescence [20], which indicates high-quality GaAsP growth on SiGe graded buffer. The same group has also fabricated GaAs0.79P0.21 cells on SiGe/Si substrate [9] with TDD of 2:8  106 cm
2 and top cell, reporting Jsc ¼ 19.1 mA/cm2, Voc ¼ 1.19V, FF ¼ 0.79, and efficiency of 18.4%, which is an improvement of previously fabricated similar cells with efficiency of w15% [40]. One of the main performance limiting factors in those cells is threading dislocation defects. By lowering the TDD, efficiency improvement was achieved.

6.4.3 GaAs0.76P0.24 single-junction solar cell on Si1LxGex/Si substrate In addition, a research group at MIT recently fabricated a GaAs0.76P0.24 single-junction solar cells on Si1
xGex/Si substrate, reporting cells with relatively low threading dislocation density [21,41]. GaAs1
yPy solar cells are fabricated on Si1
xGex graded buffer/Si substrates following three major steps: (1) metamorphic growth of Si1
xGex graded buffer on c-Si substrate, (2) nucleation of lattice matched GaAs1
yPy, and (3) growth of GaAs1
yPy solar cell layers, window, and BSF layers [21]. More details on deposition of Si1
xGex and GaAs1
yPy can be found in earlier chapters of this book or in work presented by Milakovich et al. [21] and Sharma et al. [41]. For GaAs0.76P0.24 cells discussed in this section, Si1
xGex graded buffer layer is grown on Si substrate, with final Si0.24Ge0.76 composition, to achieve lattice match with GaAs0.76P0.24 top cell layers. Further, epitaxial growth of GaAs0.76P0.24 solar cells with InGaP window and back surface field layers is done inside Aixtron closecoupled showerhead metal-organic chemical vapor deposition (MOCVD) reactor. Fig. 6.10 illustrates the cross section of fabricated GaAs0.76P0.24 solar cell and shows the cross section of TEM image of IIIeV layers (reproduced from Ref. [21]). The threading dislocation density for these samples was measured to be around 3 to 4  106 cm
2, a TDD value that guarantees high-quality IIIeV layer deposition [21]. Those cells were fabricated without any antireflective coating. Fig. 6.11 shows EQE, reflectance, and calculated IQE of one of the fabricated GaAs0.76P0.24 cells [3]. The measured reflectance data presented in Fig. 6.11 are probably lower than the reflectance of the actual cell for which EQE is measured, due to the absence of any metal contacts on sample used for reflectance measurements. This means that IQE presented in Fig. 6.11 is slightly underestimated [3].

96

6. Lattice matched IIIeV on Si via Si1–xGex buffer layer

FIGURE 6.10 Schematic cross section of fabricated GaAs0.76P0.24 SJ. Also shown is BF TEM image of grown IIIeV layers [3]. Reproduced with permission from T. Milakovich, R. Shah, S. Hadi, M. Bulsara, A. Nayfeh, E. Fitzgerald, Growth and characterization of GaAsP top cells for high efficiency IIIeV/Si tandem PV, in: 2015 IEEE 42nd Photovoltaic Specialist Conference (PVSC), 2015.

Fig. 6.12A shows the median values of measured Jsc, efficiency, FF, and Voc values for a batch of fabricated cells, and Fig. 6.12B is an example of JeV characteristics of one of the cells measured under 1 sun for AM 1.5 G standard, with Jsc w12 mA/cm2, Voc w1.1 V, FF w0.8, and efficiency w10.5% [3]. Based on the IQE data (Fig. 6.11) it can be shown that the fabricated GaAs0.76P0.24 cells have a potential of achieving Jsc w18 mA/cm2, given the presence of optimized antireflective coating. The bandgap value of the absorber material can be extracted from the QE curve, given that absorber layer is thick enough to provide clear band edge [42]. For direct bandgap materials, absorption coefficient a and band edge are related as: ðEÞf pffiffiffiffiffiffiffiffiffiffiffiffiffiffi E
Eg , allowing extraction of bandgap from linear fit to E(IQE)2 curve. When absorber layer is thick enough, IQE approaches unity for energy levels above bandgap, Eg (so-called saturation region), while it has exponential behavior at the edge below Eg (QE onset). The bandgap Eg can thus be estimated at a transition between QE onset and saturation regions, on a semilogarithmic plot of the IQE, as shown in Fig. 6.13. It can be

6.4 IIIeV on Si MJ solar cells via Si1
xGex buffer in literature

97

FIGURE 6.11 Measured reflectance and external and internal quantum efficiency (EQE and IQE) of fabricated GaAs0.76P0.24 single-junction solar cell [3].

FIGURE 6.12 Measured (A) median values of Jsc and efficiency (left axis) and Voc and fill factor (right axis) with error bars for the range of measured values and (B) JeV characteristics under 1 sun for GaAs0.76P0.24 SJ solar cells [3].

estimated from Fig. 6.13 that the bandgap for fabricated GaAs0.76P0.24 cell is Eg w1.717 eV, a value close to Eg ¼ 1.71 eV reported in Ref. [21] for a similar sample.

6.4.4 Other approaches for IIIeV on Si tandem cells As mentioned earlier in this chapter, IIIeV layers can be grown on Si substrates via GaP nucleation on Si and by utilizing GaAsP graded layer. Another, more recent, approach is to form GaAsP/SiGe monolithic

98

6. Lattice matched IIIeV on Si via Si1–xGex buffer layer

FIGURE 6.13 Bandgap determination using exponential fit to normalized internal quantum efficiency (IQE) curve at saturation region and QE onset region [3].

two-terminal DJ solar cell by growing Si1
xGex graded buffer in a reversed order, on top of Ge layer that is grown on porous Si, and then reducing the Ge fraction until the desired level is reached [8]. Another approach in realizing IIIeV on Si MJ cells is by using epitaxial lift-off (ELO) and layer transfer followed by bonding of the two subcells. In this approach, a IIIeV top single-junction cell (or MJ cells) is grown on lattice matched substrate (could be GaAs, Ge, or via SiGe/Si substrate), and it is then lifted off and bonded to separately fabricated and optimized Si bottom cell [23,24]. Currently, the highest reported efficiency at laboratory level testing is w32.8% for mechanically stacked GaAs on Si solar cells with four terminals [1], where top IIIeV cell is grown using MOCVD on GaAs substrate [24]. When compared to the performance of monolithic tandem cells that we have discussed earlier in this chapter, we can say that mechanical stacking and bonded structures do yield higher conversion efficiency. This is mainly due to the lack of optical losses associated with graded buffer layer, as well as the lower threading dislocation density if the layers are grown on lattice matched substrates (GaAs) prior to layer transfer. However, ELO has its implementation challenges, since chemical and diffusion-based lift-off procedure takes a long time to complete, making it economically impractical [43]. One of the proposed ways to speed up the ELO process that we discuss in this book is use of step-cell design with

References

99

patterning of the top IIIeV cells [44,45]. Additional discussion about the step-cell and its cost will be provided in Chapters 7 and 8, respectively.

6.5 Conclusion In this chapter we provide an overview of most notable IIIeV on Si solar cells with focus on cells grown via Si1
xGex graded buffers. As IIIeV layers have different lattice constant and thermal expansion coefficient from the one on Si, growing IIIeV materials directly on Si causes strain in IIIeV layers, which then result in dislocation misfits, once this strain is relaxed. Dislocations reduce minority carrier lifetime and act as carrier traps, negatively affecting the performance of solar cells. One way to minimize threading dislocation density (TDD) that we discussed in depth in this chapter is to grow graded Si1
xGex buffer layers on Si, gradually increasing Ge fraction until final SiGe layer with desired Ge content and required lattice constant is reached, allowing deposition of lattice matched IIIeV layers. In this chapter we have provided optical properties of such GaAs1
yPy alloys grown on lattice matched Si1
xGex/Si substrates. A number of research groups have used this method, successfully fabricating GaAs/Si or GaAsP/Si1
xGex monolithic two-terminal DJ solar cell. While those groups have achieved growth of high-quality IIIeV cells with low TDD, research has shown that performance of those monolithic cells is lower compared to their bonded counterparts, where IIIeV cells are lifted off from their lattice matched substrates and mechanically bonded to separately fabricated bottom Si cells. This is mainly due to the fact that in monolithic configuration there are unavoidable optical losses in graded buffer layers, in addition to other recombination losses at different interfaces. However, even for bonded tandem cells, Si1
xGex graded buffers on Si substrates can still be used as a low-cost lattice matched carriers for IIIeV top cell growth, bringing IIIeV based solar cells closer to wider range of consumers.

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xPx alloys from a highpressure experiment, J. Phys. C Solid State Phys. 8 (9) (1975) 1397. Ioffe Institute, GaInAsP: Band Structure and Carrier Concentration. Available: http:// www.ioffe.ru/SVA/NSM/Semicond/GaInAsP/bandstr.html#Band. (Accessed 2016). S.A. Ringel, C.L. Andre, M. Lueck, et al., IIIeV multi-junction materials and solar cells on engineered SiGe/Si substrates, Mater. Res. Soc. Proc. 836 (L6.2) (2004). J.A. Carlin, S.A. Ringel, E.A. Fitzgerald, M. Bulsara, High quality GaAs growth by MBE on Si using GeSi buffers prospects for space photovoltaics, Prog. Photovolt. Res. Appl. 8 (3) (2000) 323e332. M.R. Lueck, C.L. Andre, A.J. Pitera, M.L. Lee, E.A. Fitzgerald, S.A. Ringel, Dual junction GaInP/GaAs solar cells grown on metamorphic SiGe/Si substrates with high open circuit voltage, IEEE Electron. Device Lett. 27 (3) (2006) 142e144. M. Diaz, L. Wang, A. Gerger, A. Lochtefeld, C. Ebert, R. Opila, I. Perez-Wurfl, A. Barnett, Dual-junction GaAsP/SiGe on silicon tandem solar cells, in: 40th IEEE Photovoltaic Specialist Conference (PVSC), Denver, 2014. B. Conrad, et al., Improved GaAsP/SiGe tandem on silicon outdoors and under concentration, in: 2016 IEEE 43rd Photovoltaic Specialists Conference (PVSC), 2016. K.J. Schmieder, et al., GaInP window layers for GaAsP on SiGe/Si single and dualjunction solar cells, in: 2013 IEEE 39th Photovoltaic Specialists Conference (PVSC), 2013. K.J. Schmiedera, et al., GaAsP on SiGe/Si material quality improvements with in-situ stress sensor and resulting tandem device performance, in: Material Sciences in Semiconductor Processing, 2015, pp. 614e620. P. Sharma, T. Milakovich, M. Bulsara, E.A. Fitzgerald, Controlling epitaxial GaAsxP1
x/ Si1
yGey heterovalent interfaces, ECS Trans. 50 (9) (2012) 333e337.

102

6. Lattice matched IIIeV on Si via Si1–xGex buffer layer

[42] H. Helmers, C. Karcher, A.W. Bett, Bandgap determination based on electrical quantum efficiency, Appl. Phys. Lett. 103 (2013). [43] J.J. Schermer, et al., Thin-film GaAs epitaxial lift-off solar cells for space applications, Prog. Photovolt. 13 (2005) 587e596. [44] S. Abdul Hadi, E.A. Fitzgerald, S. Griffiths, A. Nayfeh, IIIeV/Si dual junction solar cell at scale: manufacturing cost estimates for step-cell based technology, J. Renew. Sustain. Energy 10 (1) (2018) 015905. [45] E. Polyzoeva, S.A. Hadi, A. Nayfeh, J.L. Hoyt, Reducing optical and resistive losses in graded silicon-germanium buffer layers for silicon based tandem cells using step-cell design, AIP Adv. 5 (2015) 057161.

C H A P T E R

5 History of c-Si1
xGex solar cells 5.1 Introduction Finding new ways to increase the generation current of thin-film solar cells with new materials and design innovations continues to be one of the main research challenges for photovoltaics over the last 30 years. To harness the energy from the sun, we are limited by the available material properties. More specifically, the bandgap of the semiconductor will determine how much sunlight can be absorbed. So, one way to increase the output current of solar cells is to use material with smaller bandgap that allows more sunlight to be absorbed. Alloying Ge with Si is one way to reduce the bandgap of Si, making Si1
xGex attractive for PV. However, adding Ge increases the defect density and reduces the electrical quality (lifetime), as was discussed in Chapter 4. As a result, over the years, progress has been made to minimize defect density and demonstrate improved solar cell performance. The bandgap reduction with the improved material quality will increase the ability of thin-film solar cells to absorb photons and hence increase the efficiency [1]. However, the reduction in bandgap will undoubtably reduce the open-circuit voltage (Voc). Moreover, it is very possible there exits an optimal bandgap where the drop of the Voc and the increase in current are at a point where the efficiency can still increase compared to a thin-film Si cell. As a result, Si1
xGex is an ideal material since the bandgap is tunable with the percentage of Ge (x). As scientists realized the potential value of a tunable bandgap material, the research of Si1
xGex in solar cells began. In this chapter, a literature review of c-Si1
xGex based solar cell is carried out. The reduction in bandgap and the ability of Si1
xGex to absorb light closer to the surface could help with the main issues associated with thin-film Si-based solar cells. In addition, the use of a lower bandgap bottom cell in a tandem cell design continues to be important for future high efficiency low-cost cells.

Silicon-Germanium Alloys for Photovoltaic Applications https://doi.org/10.1016/B978-0-323-85630-0.00005-4

63

© 2023 Elsevier Inc. All rights reserved.

64

5. History of c-Si1
xGex solar cells

5.2 Research history of c-Si1LxGex based solar cells The following section will cover the history of c-Si1
xGex solar cell research. Fig. 5.1 is the total number of c-Si1
xGex research papers versus time (year scale) based on exhaustive literature search. The plot shows that c-Si1
xGex research began for a short period, from 1996 to 2001 then nothing was published after that. Then from 2012 to 2018 a sharp rise in c-Si1
xGex related publications can be attributed to the new growth techniques that reduce the dislocation density (highlighted in chapter 4) and to the increased motivation of low-cost III-V tandem solar cells that can incorporate Si1
xGex. The use of Si1
xGex in tandem solar cells will be discussed in chapter 7.

5.3 Research history of single crystal c-Si1LxGex In 1992, Healy and Green conducted a simulation study on c-Si1
xGex in solar cells using PC1D [2]. It was the first study at a conceptual level showing the potential of the lower bandgap c-Si1
xGex for solar cells. Fig. 5.2 shows the simulated structure in that work [2]. Fig. 5.3 shows that as the Ge % increases the efficiency increases due to the smaller bandgap, hence more sunlight being absorbed [2]. It also shows that as the thickness decreases the effect of higher Ge % is more pronounced. With 30% Ge, the 10 mm layer can match or even outperform the cell with 75 mm layer since most of the light absorption will occur in the first few microns. In 1997, Gutjahr et al. presented at the IEEE Photovoltaics Specialist Conference (PVSC) the use of liquid phase epitaxy to grow c-Si1
xGex

FIGURE 5.1 Number of Si1
xGex solar papers versus time.

5.3 Research history of single crystal c-Si1
xGex

65

FIGURE 5.2 PC1D simulated SiGe solar cell structure. Reprinted with permission from S.A. Healy, M.A. Green, Efficiency enhancements in crystalline silicon solar cells by alloying with germanium, Sol. Energy Mater. Sol. Cell. 28 (3) (1998) 273e284.

FIGURE 5.3 Efficiency versus Ge % for different thickness of c-Si1
xGex. Reprinted with permission from S.A. Healy, M.A. Green, Efficiency enhancements in crystalline silicon solar cells by alloying with germanium, Sol. Energy Mater. Sol. Cell. 28 (3) (1998) 273e284.

directly on Si for solar cell application [3]. In that work, they grew Si1
xGex on Si (111) with x ¼ 9% and 27%. The dislocation density can be reduced by using a graded buffer layer that slowly increases the Ge % minimizing the effect of the lattice mismatch. Fig. 5.4 shows the transmission electron microscopy (TEM) of the c-Si1
xGex layer highlighting the dislocations [3]. Table 5.1 lists the solar cell results versus thickness of Si1
xGex layer.

66

5. History of c-Si1
xGex solar cells

FIGURE 5.4 Transmission electron microscopy (TEM) of Si0.9Ge0.1 on Si 111 substrate showing misfit dislocation at the interface. Reprinted with permission from A. Gutjahr, I. Silier, N. Rollbuher, M. Konuma, F. Banhart, K. Said, J. Poortmans, SiGe layer structures for solar cell application grown by liquid phase epitaxy, IEEE Photovoltaic Specialists Conference (1997) 759e762. TABLE 5.1 Solar cell results from Si1
xGex solar cells [3]. Thickness (m)

Jsc (mA/cm2)

Voc (V)

Efficiency (%)

8

23.2

0.544

8.8

10

23.4

0.541

8.9

14

24.4

0.540

9.1

Fig. 5.5 is the internal quantum efficiency (IQE) for c-Si1
xGex solar cell fabricated for different thicknesses [3]. In 1999, Said et al. demonstrated the use of c-Si1
xGex as an absorber layer in solar cells [4]. In this work, they fabricated c-Si1
xGex solar cells and studied the effect of an Si cap and the base doping. The thickness of the c-Si1
xGex layer was 15 mm and Ge % was 10%. Fig. 5.6 shows a comparison between IQE of the Si, c-Si1
xGex/Si, and Si/c-Si1
xGex/Si for the same thickness showing the effect of the Si cap [4]. The best results are obtained with using Si cap in addition to a highly doped relaxed buffer layer inserted between the Si substrate and the c-Si1
xGex base layer. Table 5.2 shows the summary of the best result obtained in Ref. [4].

67

5.3 Research history of single crystal c-Si1
xGex

FIGURE 5.5 Internal quantum efficiency (IQE) of c-Si1
xGex solar cell. A. Gutjahr, I. Silier, N. Rollbuher, M. Konuma, F. Banhart, K. Said, J. Poortmans, SiGe layer structures for solar cell application grown by liquid phase epitaxy, IEEE Photovoltaic Specialists Conference (1997) 759e762.

FIGURE 5.6 Internal quantum efficiency (IQE) of SiGe versus Si. Reprinted with permission from K. Said, J. Poortmans, M. Caymax, J.F. Nijs, L. Debarge, E. Christoffel, Design, fabrication, and analysis of crystalline Si-SiGe heterostructure thin-film solar cells, IEEE Trans. Electron. Dev. 46 (10) (1999) 2103e2121.

TABLE 5.2 Solar results for p-Si/p-SiGe/pþ-SiGe/pþþ-Si (substrate) [4]. Jsc (mA/cm2)

Voc (V)

FF (%)

Efficiency (%)

27.3

0.565

73.4

11.3

68

5. History of c-Si1
xGex solar cells

In 2013, Onyegam et al. fabricated a c-Ge solar cell [5]. In the paper, they describe the use of an exfoliation process to make 50-mm-thick Ge layers. They report 5.28% efficiency compared to 1.78% for bulk Ge cell. Fig. 5.7 shows a schematic process flow of the Ge solar cell fabrication. Figs. 5.8 and 5.9 show the exfoliated Ge and the final cell, respectively. Fig. 5.10 shows the JeV of the Ge thin-film cells compared to bulk Ge. Results show that cells with exfoliated Ge have higher Jsc and Voc and better fill factor. Fig. 5.11 shows the IQE and external quantum efficiency (EQE) of the exfoliated Ge compared to bulk Ge and Si [5]. In 2014, Abdul Hadi et al. demonstrated a c-Si1
xGex heterojunction emitter based solar cell with a-Si emitter [6,7]. In this work, c-Si1
xGex was grown epitaxially by low pressure CVD using a graded Si1
xGex buffer layer. The results of the paper will be highlighted in detail in Section 5.3. In 2015, Cariou et al. used low temperature epitaxial growth of c-Si1
xGex absorber for thin-film heterojunction solar cell (Table 5.3) [8]. In that work they fabricate c-Si0.73Ge0.27 solar cells with a thickness of 1.9 mm. Fig. 5.12 shows the fabricated cell and JV/EQE curves [8]. Dashed and dotted lines represent single path absorption for the two compositions and thicknesses.

FIGURE 5.7 Process flow for fabricating exfoliated a-Si:H/c-Ge cell. Reprinted with permission from E. Onyegam, D. Sarkar, M. Hilali, S. Saha, R. Rao, L. Mathew, D. Jawarani, J. Mantey, M. Ainom, R. Garcia, W. James, S. Banerjee, R. Garcia, W. James, S.K. Banerjee, Exfoliated, thin, flexible germanium heterojunction solar cell with record FF¼58.1%, Sol. Energy Mater. Sol. Cell. 111 (2013) 206e211.

5.3 Research history of single crystal c-Si1
xGex

69

FIGURE 5.8 Photograph of an exfoliated Ge foil along with reusable wafer. Reprinted with permission from E. Onyegam, D. Sarkar, M. Hilali, S. Saha, R. Rao, L. Mathew, D. Jawarani, J. Mantey, M. Ainom, R. Garcia, W. James, S. Banerjee, R. Garcia, W. James, S.K. Banerjee, Exfoliated, thin, flexible germanium heterojunction solar cell with record FF¼58.1%, Sol. Energy Mater. Sol. Cell. 111 (2013) 206e211.

FIGURE 5.9 Photograph of the completed 50 mm flexible Ge foil with 1.2 cm2 a-Si:H/cGe HJ cells. Reprinted with permission from E. Onyegam, D. Sarkar, M. Hilali, S. Saha, R. Rao, L.Mathew,D.Jawarani,J.Mantey,M.Ainom,R.Garcia,W.James,S.Banerjee,R.Garcia,W.James,S.K. Banerjee, Exfoliated, thin, flexible germanium heterojunction solar cell with record FF¼58.1%, Sol. Energy Mater. Sol. Cell. 111 (2013) 206e211.

In 2015, Oshima et al. fabricated c-Si1
xGex by MBE with x ¼ 49%, 70%, and 84% Ge [9]. Fig. 5.13 shows the fabricated solar cell structure, while Fig. 5.14 shows QE as function of Ge % for this work [9].

70

5. History of c-Si1
xGex solar cells

FIGURE 5.10 JeV characteristics of 500 mm bulk Ge and exfoliated 50 mm Ge heterojunction solar cells under AM 1.5G illumination. Reprinted with permission from E. Onyegam, D. Sarkar, M. Hilali, S. Saha, R. Rao, L. Mathew, D. Jawarani, J. Mantey, M. Ainom, R. Garcia, W. James, S. Banerjee, R. Garcia, W. James, S.K. Banerjee, Exfoliated, thin, flexible germanium heterojunction solar cell with record FF¼58.1%, Sol. Energy Mater. Sol. Cell. 111 (2013) 206e211.

FIGURE 5.11 External and internal quantum efficiency (EQE and IQE) spectra of exfoliated 50 mm Ge, 500 mm bulk Ge, and 500 mm bulk Si heterojunction solar cells. Reprinted with permission from E. Onyegam, D. Sarkar, M. Hilali, S. Saha, R. Rao, L. Mathew, D. Jawarani, J. Mantey, M. Ainom, R. Garcia, W. James, S. Banerjee, R. Garcia, W. James, S.K. Banerjee, Exfoliated, thin, flexible germanium heterojunction solar cell with record FF¼58.1%, Sol. Energy Mater. Sol. Cell. 111 (2013) 206e211.

71

5.3 Research history of single crystal c-Si1
xGex

TABLE 5.3 Summary of solar cell results. Cell details

Voc (V)

Jsc (mA/cm2)

FF (%)

Efficiency (%)

Si 1.7 mm

0.501

16.1

78.6

6.4

c-Si0.73Ge0.27 1.9 mm

0.416

18.8

77.5

6.1

FIGURE 5.12 Drawing of heterojunction epi-SiGe cell:Al/(pþþ)c-Si/(i)epi-SiGe/(n)a-Si: H/ITO/Al. JeV curves (top-right axis) and EQE (bottom-left axis) of 1.9 mm epi-Si0.73Ge0.27 and 1.7 mm epi-Si cells. Dashed and dotted lines represent single path absorption for the two compositions and thicknesses. Reprinted with permission from R. Cariou, J. Tang, N. Ramay, R. Ruggeri, P. R. I. C. Pages, Low temperature epitaxial growth of SiGe absorber for thin film heterojunction solar cells, Sol. Energy Mater. Sol. Cell. 34 (2015) 15e21.

Table 5.4 shows the solar results, while Fig. 5.15 shows the JeV curve for cells presented in Ref. [9]. In 2016, Li published a paper on the performance of c-Si1
xGex on Si solar cell with graded buffers [10]. Fig. 5.16 illustrates the structure of the three cells, and Fig. 5.17 shows the measured EQE of the cells [10].

72

5. History of c-Si1
xGex solar cells

FIGURE 5.13 Structure of fabricated c-Si1
xGex solar cell. Reprinted with permission from R. Oshima, M. Yamanaka, H. Kawanami, I. Sakata, K. Matsubara, T. Sugaya, Fabrication of hydrogenated amorphous Si/crystalline Si1
xGex (x  0.84) heterojunction solar cells grown by solid source molecular beam epitaxy, Jpn. J. Appl. Phys. 54 (2015) 012301.

Table 5.5 tabulates the solar cell results with and without a compositionally graded c-Si1
xGex base. In 2017, Khadri et al. used MBE to fabricate c-Si1
xGex/Si solar cell and studied the effect of the Front Surface Field (FSF) [11]. Fig. 5.18 shows JeV characteristic for Si0.85Ge0.15/c-Si heterojunction solar cells with and without FSF, while Table 5.6 summarizes the solar cell performance parameters [11]. Also in 2018, Khan et al. used MBE to fabricate c-Si1
xGex solar cells with 10% Ge (Table 5.7) [12]. Fig. 5.19 shows the cross section of that device [12]. Table 5.8 is a summary of the c-Si1
xGex solar cells history highlighting the key solar cell results including deposition method, thickness, Voc, Jsc, fill factor (FF), and efficiency.

5.4 c-Si1LxGex HIT solar cell From the various solar cell structures outlined in Section 5.2, the work on heterojunction emitter based solar cell (HIT) with Si1
xGex will be

73

5.4 c-Si1
xGex HIT solar cell

FIGURE 5.14

External quantum efficiency (EQE) (symbol) and internal quantum efficiency (IQE) (dashed line) spectra for 3-mm-thick Si1
xGex heterojunction solar cells with (A) x ¼ 0, (B) x ¼ 0.49, (C) x ¼ 0.70, and (D) x ¼ 0.84. The inset shows log-scale IQE spectra for each cell. Reprinted with permission from R. Oshima, M. Yamanaka, H. Kawanami, I. Sakata, K. Matsubara, T. Sugaya, Fabrication of hydrogenated amorphous Si/crystalline Si1
xGex (x  0.84) heterojunction solar cells grown by solid source molecular beam epitaxy, Jpn. J. Appl. Phys. 54 (2015) 012301.

TABLE 5.4 Key solar parameters versus Ge % [9]. Ge %

Jsc (mA/cm2)

Voc (V)

FF %

Efficiency %

0

15.2

15.2

65.2

4.3

49

16.7

16.7

48.7

1.8

70

21.4

21.4

49.5

2

84

24

24

49.1

2

highlighted here [6]. In this work a large bandgap a-Si emitter (1.7 eV) is used to help suppress the Voc loss while not affecting the current increase. This way the largest effect of the Si1
xGex lower bandgap can be achieved. The HIT cell design has been studied extensively over the past 10e15 years but not applied to SiGe [14]. In this work, a-Si:H/c-Si1
xGex/c-Si HIT cells with thin epitaxial Si and Si1
xGex (x ¼ 0.25, x ¼ 0.41, and x ¼ 0.56) active layers and an a-Si:H nþ emitter is shown in Fig. 5.20. These growth details are discussed in Chapter 4.

74

5. History of c-Si1
xGex solar cells

FIGURE 5.15 JeV curves under AM 1.5G at 1 sun for 3-mm-thick Si1
xGex heterojunction solar cells with (A) x ¼ 0, (B) x ¼ 0.49, (C) x ¼ 0.70, and (D) x ¼ 0.84. The inset shows a dependence of Ge contents on JSC. Reprinted with permission from R. Oshima, M. Yamanaka, H. Kawanami, I. Sakata, K. Matsubara, T. Sugaya, Fabrication of hydrogenated amorphous Si/crystalline Si1
xGex (x  0.84) heterojunction solar cells grown by solid source molecular beam epitaxy, Jpn. J. Appl. Phys. 54 (2015) 012301.

FIGURE 5.16 Structures of three fabricated devices for the study of using a compositionally graded SiGe base. Reprinted with permission from D. Li, X. Zhao, L. Wang, B. Conrad, A. Soeriyadi, A. Lochtefeld, A. Gerger, I. Perez-Wurfl, A. Barnett, Performance improvement for epitaxially grown SiGe on Si solar cell using a compositionally graded SiGe base, Appl. Phys. Lett. 109 (2016) 243503.

75

5.4 c-Si1
xGex HIT solar cell

FIGURE 5.17 Measured external quantum efficiencies (EQEs) of the three devices shown in Fig. 5.16. Reprinted with permission from D. Li, X. Zhao, L. Wang, B. Conrad, A. Soeriyadi, A. Lochtefeld, A. Gerger, I. Perez-Wurfl, A. Barnett, Performance improvement for epitaxially grown SiGe on Si solar cell using a compositionally graded SiGe base, Appl. Phys. Lett. 109 (2016) 243503. TABLE 5.5 Device results with and without a compositionally graded Si1
xGex base [10]. Solar cell

Voc (V)

Jsc mA/cm2 from EQE (above 750 nm)

No graded Ge

0.297

14.8

66

2.9

Graded 85% Ge

0.291

16.3

66

3.1

Graded 88% Ge

0.261

18.5

61

2.9

FF %

Efficiency (%)

The solar cells are fabricated on chemically cleaned heavily boron doped Si wafers with a doping density of approximately 4  1018 cm
3. For the Si1
xGex cells, a 1-mm (x ¼ 0.41), 2-mm, and 4-mm-thick relaxed Si1
xGex (x ¼ 0.25, 0.41, and 0.56) layer was epitaxially grown by LPCVD using SiH4 at 900 C on a 3- to 6-mm-thick graded, relaxed buffer layer using SiH4 and GeH4 with threading dislocation density of around w106 cm
2 [15]. Also Si-based solar cells are fabricated to compare. The structure after Si1
xGex epitaxial growth of graded and active layer is illustrated in Fig. 5.21. For the growth, the Si1
xGex was in situ doped p-type to a level of approximately 5  1016 cm
3 using B2H6. And an w1 nm strained-Si was

76

5. History of c-Si1
xGex solar cells

FIGURE 5.18 Experimental JeV characteristic for n (Si0.85Ge0.15)/p(c-Si) heterojunction solar cells with and without FSF realized by (a-Si:H 2 nm) thin layer n-doped. Reprinted with permission from M. Kadri, O. Messaoudi, M. Krichen, K. Dhahri, M. Rasheed, E. Dhahri, A. Zouari, K. Khirouni, J. O. A. R. Barille´, Optical and electrical properties of SiGe/Si solar cell heterostructures: ellipsometric study, J. Alloys 721 (2017) 779. TABLE 5.6 Solar cell results extracted from currentevoltage characteristics [11]. Cell

Voc (V)

Jsc (mA/cm2)

FF (%)

Efficiency (%)

With FSF

0.8

3.42

67

3.4

No FSF

0.81

2.12

57

1.2

TABLE 5.7 Current density, fill factor (FF), Voc, and efficiency of SiGe based solar cells [12]. Jsc (mA/cm2)

FF (%)

Voc

Efficiency (%)

16

54

0.418

3.5

grown at w560 C on top of the Si1
xGex layer to improve the interface with a-Si. Next, using plasma-enhanced chemical vapor deposition (PECVD), 5 nm undoped a-Si:H and 10 nm nþ doped a-Si:H are deposited on the layers. Finally, w230 nm of Indium Tin Oxide (ITO) is sputtered for the antireflective (AR) [16]. Fig. 5.21 illustrates cross section of a device through the steps of strained-Si, a-Si, and ITO deposition [6].

77

5.4 c-Si1
xGex HIT solar cell

FIGURE 5.19 Cross section of cSi1
xGex solar cells with 10% Ge. Reprinted with permission from M.A. Khan, R.S.K. Sawano, P. Sichanugrist, A. Lukianov, Y. Ishikawa, Growth and characterization of low composition Ge, x in epi-Si1
xGex (x G 10%) active layer for fabrication of hydrogenated bottom solar cell, J. Phys. D Appl. Phys. 51 (2018) 185107.

TABLE 5.8

Summary of c-SiGe solar cells. Ge (%)

Voc (V)

Jsc (mA/ cm2)

FF (%)

14

27

0.54

24.4

68.6

RP-CVD 750C

15

10

0.559

24.2

76

Onyegam et al. [5]

Exfoliated from Ge bulk

50

100

0.203

44.7

58.1

5.28

Abdul Hadi et al. [13]

RP-CVD 750C

2

56

0.323

21.16

68

4.7

Cariou et al. [8]

PECVD/ 175C

2

27

0.416

18.8

77

6.1

Oshima et al. [9]

Solid source MBE

3

84

0.167

24

49.1

2

Li et al. [10]

RP-CVD

w3

88

0.261

18.5

61

2.9

Khadri et al. [11]

MBE

NA

15

0.64

67

3.4

Khan et al. [12]

MBE

1

10

0.418

54

3.5

Deposition method

Thickness (mm)

Gutjahr et al. [3]

LPE 650-900

Said et al. [4]

Source

2.79 16

Efficiency (%) 9.1 10.3

78

5. History of c-Si1
xGex solar cells

FIGURE 5.20 Cross section of a-Si:H/c-Si1
xGex/c-Si HIT cells as fabricated including ITO and Ag contacts. Reprinted with permission from S.A. Hadi, P. Hashemi, N. DiLello, E. Polyzoeva, A. Nayfeh, J.L. Hoyt, Thin-film Si1
xGex HIT solar cells, Sol. Energy 103 (2014) 154e159; S. Abdul Hadi, MSc Thesis, Si1-xGex Thin Film Heterojunction Solar Cells, Masdar Institute, Abu Dhabi, 2012.

Solar cells with area of 0.25 cm  0.25 cm, 0.5 cm  0.5 cm and 1 cm  1 cm were then fabricated. Fig. 5.22A shows one of the fabricated device samples and (B) is the close up of the top view of the solar cell cluster on a sample. Fig. 5.23 shows the TEM images of fabricated device [17]. As shown, the graded layer has more defects which indicates a lower lifetime than top c-Si1
xGex cap layer. Measured JeV characteristics of the fabricated a-Si:H/c-Si1
xGex/c-Si cells under 1 sun in AM 1.5G for x ¼ 0, 0.25, 0.41, and 0.56, for 2 mm Si1
xGex absorber layers, are shown in Fig. 5.24. The plots show that as x increases Jsc increases and is accompanied by a decrease in Voc due to the lower bandgap. EQE for a-Si:H/c-Si1
xGex/c-Si 1  1 cm solar cells with 2 mm absorber layer for x ¼ 0, 0.25, 0.41, and 0.56 is shown in Fig. 5.25. The EQE result highlights the improved spectral response as the Ge percentage increases. This bodes well for thin-film solar cells with higher Ge percentage. Dark current measurements for cells with 2 mm thick absorber layer using values near the median of the statistical data are shown in Fig. 5.26. The dark current increases with Ge content, from approximately 10 nA at
0.5 V for Si-based cells to close to 0.5 mA for cells with an Si0.44Ge0.56 absorber layer. This increase is the result of a reduction in bandgap and a decrease in the minority carrier lifetime due to an increase in threading dislocation density with increasing Ge content. In Chapter 8, TCAD simulation of thin-film Si1
xGex solar cells is discussed in detail.

5.4 c-Si1
xGex HIT solar cell

79

FIGURE 5.21 Cross section of a device through steps of Si1
xGex epitaxial graded and active absorber layer growth. S.A. Hadi, P. Hashemi, N. DiLello, E. Polyzoeva, A. Nayfeh, J.L. Hoyt, Thin-film Si1
xGex HIT solar cells, Sol. Energy 103 (2014) 154e159; S. Abdul Hadi, MSc Thesis, Si1-xGex Thin Film Heterojunction Solar Cells, Masdar Institute, Abu Dhabi, 2012.

FIGURE 5.22 (A) Sample of a device after completion of processing; (B) top view photograph of the fabricated cells. Reprinted with permission from S.A. Hadi, P. Hashemi, N. DiLello, E. Polyzoeva, A. Nayfeh, J.L. Hoyt, Thin-film Si1
xGex HIT solar cells, Sol. Energy 103 (2014) 154e159; S. Abdul Hadi, MSc Thesis, Si1-xGex Thin Film Heterojunction Solar Cells, Masdar Institute, Abu Dhabi, 2012.

80

5. History of c-Si1
xGex solar cells

FIGURE 5.23 Transmission electron microscope (TEM) images of 2 mm Si0.58Ge0.42 cell (a) graded buffer Si1
xGex layer and active Si0.58Ge0.42 interface with zoom into graded layer dislocations and (b) ITO/a-Si interface with zoom to strained c-Si interface. Reprinted with permission from S.A. Hadi, P. Hashemi, N. DiLello, E. Polyzoeva, A. Nayfeh, J.L. Hoyt, Thinfilm Si1
xGex HIT solar cells, Sol. Energy 103 (2014) 154e159.

FIGURE 5.24 Measured JeV characteristics under 1 sun in AM 1.5G for a-Si:H/c-Si1
xGex/cSi 0.25  0.25 cm solar cells with 2 mm absorber layer for x ¼ 0, 0.25, 0.41, and 0.56. Reprinted with permission from S.A. Healy, M.A. Green, Efficiency enhancements in crystalline silicon solar cells by alloying with germanium, Sol. Energy Mater. Sol. Cell. 28 (3) (1998) 273e284.

5.4 c-Si1
xGex HIT solar cell

81

FIGURE 5.25 Measured external quantum efficiency (EQE) for a-Si:H/c-Si1
xGex/c-Si 1  1 cm solar cells with 2 mm absorber layer for x ¼ 0, 0.25, 0.41, and 0.56. Reprinted with permission from S.A. Hadi, P. Hashemi, N. DiLello, E. Polyzoeva, A. Nayfeh, J.L. Hoyt, Thinfilm Si1
xGex HIT solar cells, Sol. Energy 103 (2014) 154e159.

FIGURE 5.26 Measured dark JeV characteristics for a-Si:H/c-Si1
xGex/c-Si solar cells with 2 mm absorber layer (0.25  0.25 cm) and x ¼ 0, 0.25, 0.41, and 0.56 (values close to mean and median). Reprinted with permission from S.A. Hadi, P. Hashemi, N. DiLello, E. Polyzoeva, A. Nayfeh, J.L. Hoyt, Thin-film Si1
xGex HIT solar cells, Sol. Energy 103 (2014) 154e159.

82

5. History of c-Si1
xGex solar cells

5.5 Summary In this chapter, a comprehensive historical review of c-Si1
xGex solar cells is carried out. The history shows the renaissance period started around 2012 due to advancements in the growth methods that reduced the dislocation density of c-Si1
xGex. As a stand-alone single-junction cell, c-Si1
xGex has the potential to improve on traditional lower efficiency thin-film c-Si solar cells due to the smaller bandgap and more sunlight absorbed. This was especially highlighted in the HIT cell structure. However, it is clear that the main impact of c-Si1
xGex is as bottom cell for high efficiency low-cost tandem cell, which is to be covered in the upcoming chapters.

References [1] G. Beaucarne, F. Duerinckx, I. Kuzma, K.V. Nieuwenhuysen, H.J. Kim, J. Portmans, Epitaxial thin-film Si solar cells, Thin Solid Films 511e512 (July 2006) 533e542. [2] S.A. Healy, M.A. Green, Efficiency enhancements in crystalline silicon solar cells by alloying with germanium, Sol. Energy Mater. Sol. Cell. 28 (3) (1998) 273e284. [3] A. Gutjahr, I. Silier, N. Rollbuher, M. Konuma, F. Banhart, K. Said, J. Poortmans, SiGe layer structures for solar cell application grown by liquid phase epitaxy, IEEE Photovoltaic Specialists Conference (1997) 759e762. [4] K. Said, J. Poortmans, M. Caymax, J.F. Nijs, L. Debarge, E. Christoffel, Design, fabrication, and analysis of crystalline Si-SiGe heterostructure thin-film solar cells, IEEE Trans. Electron. Dev. 46 (10) (1999) 2103e2121. [5] E. Onyegam, D. Sarkar, M. Hilali, S. Saha, R. Rao, L. Mathew, D. Jawarani, J. Mantey, M. Ainom, R. Garcia, W. James, S. Banerjee, R. Garcia, W. James, S.K. Banerjee, Exfoliated, thin, flexible germanium heterojunction solar cell with record FF¼58.1%, Sol. Energy Mater. Sol. Cell. 111 (2013) 206e211. [6] S.A. Hadi, P. Hashemi, N. DiLello, E. Polyzoeva, A. Nayfeh, J.L. Hoyt, Thin-film Si1
xGex HIT solar cells, Sol. Energy 103 (2014) 154e159. [7] S. Abdul Hadi, MSc Thesis. Si1-xGex Thin Film Heterojunction Solar Cells, Masdar Institute, Abu Dhabi, 2012. [8] R. Cariou, J. Tang, N. Ramay, R. Ruggeri, P. R. I. C. Pages, Low temperature epitaxial growth of SiGe absorber for thin film heterojunction solar cells, Sol. Energy Mater. Sol. Cell. 34 (2015) 15e21. [9] R. Oshima, M. Yamanaka, H. Kawanami, I. Sakata, K. Matsubara, T. Sugaya, Fabrication of hydrogenated amorphous Si/crystalline Si1
xGex (x  0.84) heterojunction solar cells grown by solid source molecular beam epitaxy, Jpn. J. Appl. Phys. 54 (2015) 012301. [10] D. Li, X. Zhao, L. Wang, B. Conrad, A. Soeriyadi, A. Lochtefeld, A. Gerger, I. PerezWurfl, A. Barnett, Performance improvement for epitaxially grown SiGe on Si solar cell using a compositionally graded SiGe base, Appl. Phys. Lett. 109 (2016) 243503. [11] M. Kadri, O. Messaoudi, M. Krichen, K. Dhahri, M. Rasheed, E. Dhahri, A. Zouari, K. Khirouni, J.O.A.R. Barille´, Optical and electrical properties of SiGe/Si solar cell heterostructures: ellipsometric study, J. Alloys 721 (2017) 779. [12] M.A. Khan, R.S.K. Sawano, P. Sichanugrist, A. Lukianov, Y. Ishikawa, Growth and characterization of low composition Ge, x in epi-Si1
xGex (x G 10%) active layer for fabrication of hydrogenated bottom solar cell, J. Phys. D Appl. Phys. 51 (2018) 185107.

References

83

[13] S. Abdul Hadi, P. Hashemi, A. Nayfeh, J.L. Hoyt, a-Si/c-Si1-xGex/c-Si heterojunction solar cells, in: SISPAD, 2011. [14] M. Taguchi, et al., HIT cells e high-efficiency crystalline Si cells with novel structures, Prog. Photovoltaics Res. Appl. 8 (October 2000) 503e513. [15] I. Aberg, Ph.D. Thesis, MIT, 2006. [16] ITO/a-Si deposited by MVSystems, Inc. [17] Evans Analytical GroupÒ (EAG)," [Online]. Available: http://www.eaglabs.com/ about-eag.html.

C H A P T E R

4 Si1exGex deposition and properties 4.1 Challenge If lattice constants are the same, high-quality films “without dislocations” can be achieved. For example, epitaxial-Si on an underlying Si substrate will result in very high-quality single crystal Si. However, to grow two different materials with the same high quality, the lattice constant of the grown film must match the lattice constant of the underlying substrate [1]. By nature, there are different materials that have the same lattice constants, such as GaAs/AlAs and Ge/GaAs, and in those cases, high-quality layers can be grown. In addition, in some cases, matching the lattice constants can be achieved by using ternary alloys. Since GaAs and AlAs have the same lattice constant then the ternary alloy AlxGa1
xAs has the same lattice constant over the entire range of x. Thus, one can choose the desired x (with corresponding bandgap), then grow on a matched GaAs substrate [1]. Fig. 4.1 shows the bandgap (at 300 K) versus lattice constant for a range of semiconductor materials and alloys [2,3]. Fig. 4.1 also shows the Si/Ge system and how the lattice constant increases as Ge fraction increases. In addition to the widespread use of lattice matched epitaxial layers, advanced epitaxial growth techniques allow the growth of very thin (w100 A) layers of lattice mismatched crystals. If the mismatch is only a few percent and the layer is thin, the epitaxial layer growth with a lattice constant follows that of the seed crystal. The resulting layer is in compression or tension along the surface plane as its lattice constant adapts to the seed crystal. Such a layer is called pseudomorphic because it is not lattice matched to the substrate without strain. Fig. 4.2 illustrates the lattice of strained versus unstrained epitaxy based on the lattice match.

Silicon-Germanium Alloys for Photovoltaic Applications https://doi.org/10.1016/B978-0-323-85630-0.00003-0

37

© 2023 Elsevier Inc. All rights reserved.

38

4. Si1exGex deposition and properties

FIGURE 4.1 Bandgap versus lattice constant for various alloys including Si1
xGex [2,3].

FIGURE 4.2 Schematic of heteroepitaxy (left) strained layer when the lattice of the epitaxial layer is larger than the substrate and (right) unstrained layer when the grown layer is strained to match the substrate crystal [4].

4.1 Challenge

39

However, if the epitaxial layer exceeds a critical thickness, tc, which depends on the lattice mismatch, the strain energy leads to formation of defects called “misfit dislocations.” Fig. 4.3 shows a high-resolution transmission electron microscope (TEM) based image of dislocations that form during Ge on Si growth [5]. The smaller the Ge percentage the less lattice mismatch to c-Si and the Si1
xGex system will experience less strain. As one starts to grow Ge on Si, the new Ge layer will conform to the lattice spacing of the Si substrate. The Ge layer is compressively strained as the lattice constant is reduced [5]. Below a critical thickness, one can grow defect-free compressively stained Ge on Si. This thickness has been shown to be around 4e10 nm [6]. As one continues to grow thicker layers, it is energetically favorable to relieve the strain by forming dislocations at the Ge/Si interface [6]. Eq. (4.1) describes the relationship between the lattice constant of Si1
xGex and fraction x [7]. aðxÞ ¼ 5:6579
0:2269ð1
xÞ

(4.1)

The amount of strain and threading dislocations is proportional to the amount of lattice mismatch between c-Si1
xGex and c-Si. Fig. 4.4 (left axis) plots the Si1
xGex (%) lattice constant versus x using Eq. (4.1) while right axis plots the lattice mismatch to c-Si versus x. From Fig. 4.4 (left axis), the lattice constant drops linearly with increasing x, from 5.43 for x ¼ 0 to 5.66 for x ¼ 1. On the right axis of Fig. 4.4, the % mismatch to c-Si shows an increase from 0 for c-Si homoepitaxy to nearly 4.2% for Ge on Si. Moreover, islanding can occur as an additional means of reducing the elastic strain energy of the film [6]. This leads to rough surfaces unsuitable for device applications. The following sections will detail the process of islanding and dislocations in c-Si1
xGex on silicon heteroepitaxy.

FIGURE 4.3 Cross-sectional TEM micrograph of Ge growth on Si showing threading dislocations [5].

40

4. Si1exGex deposition and properties

FIGURE 4.4 c-Si1
xGex lattice constant (left axis) and % mismatch of c-Si1
xGex to Si (right axis) versus Ge fraction x.

4.2 Growth methods To understand the growth mechanisms, it important to understand the various growth modes. These are island growth mode or what is called VolmereWeber growth (VW), layer growth mode, or Frank Van der Merwe (FVM), and StranskieKrastanov (SK) growth (a combination of layer and island growth). The following is a brief description of the island growth, and the layer growth mode, while SK growth will be described in greater detail in the next section, as this mode describes the germanium/ silicon system. In the island growth mode, the smallest stable clusters nucleate on the substrate and grow in three dimensions to form islands. This happens when the deposited atoms are more strongly bound to each other than to the substrate. This growth mode is typical of metal on insulators. In this mode the growing layer wants to minimize interface and surface energy, so islanding occurs. In the layer growth mode, the smallest stable clusters grow in two dimensions, resulting in the formation of planar sheets. In this growth mode, the atoms are more strongly bound to the substrate than to each other. An example of this growth mode is single crystal epitaxial growth of semiconductor films. The growing layer reduces the surface energy, and wets the surface completely, resulting in smooth layer on layer growth. If the balance of forces changes during the growth, the first few layers will comprise a continuous smooth film that usually has properties that differ from the bulk. The balance of forces will change during the growth if the materials have a large lattice mismatch and the strain associated. This is due to the influences of the surface, interfaces, and the film

4.2 Growth methods

41

structure, determined by the initial condensation process. The film growth involves the processes of initial nucleation and subsequent deposition [8]. Nucleation refers to the earliest steps of film growth where enough vapor atoms or molecules condense on the substrate. Soon after exposure to the incident flux a uniform distribution of small highly mobile clusters or islands form. In SK growth islanding happens to relieve the misfit strain without an energetic barrier associated with forming dislocations. The clusters grow both in size and density until the islands begin to merge in what is known as the coalescence phenomenon. Coalescence decreases the island density allowing further nucleation to occur. Coalescence continues until a connected network with unfilled channels and voids develops. Finally, the voids are filled and a continuous film results. Fig. 4.5 shows the three growth modes of heteroepitaxy: (a) layerby-layer (FrankeVan der Merwe) growth; (b) island (VolmereWeber) growth; and (c) layer-plus-island (StranskieKrastanov). The StranskieKrastanov (SK) growth mode describes the germanium silicon heteroepitaxial growth system. This growth mode is a combination of the island and layer growth modes. The balance of forces changes during the growth due to the lattice mismatch between Ge and Si. It has been shown that the condition for SK growth is that the mismatch (ε) is between 3% and 7% [9]. In SK growth, there is an initial adsorbate wetting layer of characteristic thickness. After the formation of one or more monolayers, subsequent layer growth becomes unfavorable and island growth begins to relive the misfit strain. Then, there is a sudden transition from 2D to 3D islands, known as the SK-transition [10]. The final layer consists of separated 3D island upon a (reduced) persisting wetting layer. Some examples of heteroepitaxial systems that follow the SK model are Ge/Si, InAs/GaAs, PbSe/PbTe, CdSe/ZnSe, PTCDA/Ag. Finally, the SK growth mechanism can be used to grow self-assembled quantum dots.

FIGURE 4.5 The three growth modes of heteroepitaxy: (A) Layer-by-layer (FrankeVan der Merwe) growth; (B) island (VolmereWeber) growth; and (C) layer-plus-island (StranskieKrastanov). Reprinted with permission from V. L. Tassev and S. R. Vangala, "Thick Hydride Vapor Phase Heteroepitaxy: A Novel Approach to Growth of Nonlinear Optical Material," Crystals , vol. 9, no. 8, p. 393, 2019 [8].

42

4. Si1exGex deposition and properties

The desired properties of them are dislocation free, narrow size distribution, well-defined shape, and spatial ordering [11]. In addition to islanding associated with SK growth, germanium on silicon growth results in misfit dislocations that thread to the surface as threading dislocations. As described in the previous section, as the growth begins there is a thin wetting layer followed by islanding growth. Below the critical thickness, the germanium layer will be dislocation free and take the lattice constant of the underlying silicon layer. The critical thickness has been shown to be between 4 and 10 nm for this system. However, this thickness will vary depending on the growth conditions. So as a result, germanium will be compressively strained by 4.2% below the critical thickness. As the deposited film gets thicker, atoms continue to be forced to a different lattice constant. The total strain energy increases linearly with thickness. As the growth continues, it becomes favorable to create defects in the film that allows the layer to adopt its relaxed lattice constant and relieve the strain. These defects are called misfit dislocations and are formed at the Ge/Si interface. Fig. 4.6 shows the three growth modes of epitaxy from matched (homoepitaxy), to relaxed and strained heteroepitaxy. Fig. 4.7 illustrates the cross section and atomic view of germanium layer after critical thickness and dislocations have formed [5]. There are two predominant dislocations in the Ge on Si system. Misfit dislocations are introduced to relax the lattice mismatch between the layer and the Si substrate and are typically confined to the interface between the layer and the Si substrate. They relax the lattice mismatch between the Ge layers and the Si substrate by introducing extra half plane of atoms. These misfit dislocations are confined to the interface between the Ge layer and the Si substrate and are energetically stable when the Ge thickness is larger than a critical thickness for misfit dislocation formation. Threading dislocations are the by-product of the introduction of misfit dislocations

FIGURE 4.6 Epitaxial film growth modes [12].

4.2 Growth methods

43

FIGURE 4.7 Cross section and atomic view of germanium layer after critical thickness and dislocations have formed [5].

and do not relax lattice mismatch strain. Threading dislocations are left in the layers because dislocations cannot end in a crystal. Dislocations must either form a loop or terminate at a free surface. Since the layer surface is always the nearest free surface to the substrate, these threading dislocations typically thread from the layeresubstrate interface to the layer surface. The fact that devices are usually built close to the layer surface, threading dislocations cannot be easily avoided and are a very important impediment in electrical devices. Threading dislocations can reduce carrier lifetime, carrier mobility, and compromise device reliability [13]. There are two main ways to determine threading dislocation density: plan-view TEM and defect etching. Cross-sectional TEM is an excellent way to study the defects in layer; however, it is difficult to quantify them due to the small viewing area. As a result, defect-etch and plan-view TEM are the most accepted and widely used methods for determining the threading dislocation density. Fig. 4.8 is a cross-sectional transmission electron microscope (X-TEM) bright field image showing the Ge on Si with 6 degrees off-cut substrate. The threading dislocations are confined within the first 700 nm Ge epilayer. Beyond this thickness, minimum number of dislocations are observed which indicates a high-quality Ge film. In plan-view TEM dislocations appear as crystal imperfections in the lattice and can thus be counted also. Threading dislocation density is reported as a density per cm2. Typical values of threading dislocation density for the germanium on silicon system range from 1010 to 2  106 cm2. The large range is due to the numerous methods published on growing germanium on silicon. Fig. 4.9 shows an example of plan view TEM highlighting dislocations. Defect etching method etches dislocations at a higher rate than the layer and thus etch pits appear visible using an optical microscope [5]. These etch pits are the dislocations and can be counted to determine threading dislocation density. Fig. 4.10 is an optical microscope 100 plan view image after defect etch example showing etch pits signifying threading dislocation density.

44

4. Si1exGex deposition and properties

FIGURE 4.8 Cross-sectional transmission electron microscope (X-TEM) bright field image of Ge on Si with 6 degrees off-cut substrate, with the treading dislocations confined within the first 700 nm Ge epilayer. Reprinted with permission from K. H. Lee, S. Bao, B. Wang, C. Wang, S. F. Yoon, J. Michel, E. A. Fitzgerald and C. S. Tan, "Reduction of threading dislocation density in Ge/Si using a heavily As-doped Ge seed layer," AIPAdvances , vol. 6, p. 025028 , 2016 [15]. FIGURE 4.9 Plan view TEM showing misfit dislocations. Reprinted with permission from A. K. Okyay, A. Nayfeh, K. C. Saraswat, T. Yonehara, A. Marshall and Paul C McIntyre, "High-efficiency metal-semiconductor-metal photodetectors on heteroepitaxially grown Ge on S," Optics Letters, vol. 31, no. 17, pp. 2565-2567, 2006 [14].

4.3 Deposition techniques The ability to grow high-quality films on semiconductors substrates is very important for many applications. The method used depends on the materials to be deposited. In semiconductor CMOS processing today some of the more popular materials needed are silicon, low temperature oxide (LTO), various dielectrics, germanium, or siliconegermanium. The method of choice used in all cases is chemical vapor deposition (CVD). In

4.3 Deposition techniques

45

FIGURE 4.10 Optical microscope 100 plan view image after defect etch example of threading dislocation etch pits (EPD) [5].

CVD, the film is produced by chemical reactions that take place on the substrate surface between reactant gases that are introduced into the deposition chamber [16]. On the other hand, physical vapor deposition (PVD), which is based on physical methods such as evaporation or sputtering, is primarily used to deposit metals. In PVD, atoms are produced which pass through a lowpressure gas phase and then condense on the substrate. In CVD growth, the film producing reaction must take place on the surface of the substrate and not in the gas stream. This helps avoid any gas phase reaction that could deteriorate the film quality [16]. Fig. 4.11 shows a common configuration of a cold-wall reactor [16]. The wafers are heated

FIGURE 4.11

Common configuration of cold-wall reactor. Reprinted with permission from J. D. Plummer, M. D. Deal and P. B. Griffin, Silicon VLSI Technology, Prentice Hall, 2000 [16].

46

4. Si1exGex deposition and properties

by using a graphite susceptor, which in turn is heated by RF induction. Since only the wafer and susceptor are heated, deposition on the reactor walls is minimized. On the other hand, to grow high-quality low temperature oxide a “hot-wall” or low-pressure CVD chamber can be used. The growth is done at a low pressure with the wafers stacked upright. The CVD growth process can be described by seven steps highlighted in Fig. 4.12. First, the reactants are transported to the deposition region. Second, there is diffusion of the reactants from the gas stream through the boundary layer to the wafer surface. Third, the reactants are adsorbed on the wafer surface. Fourth, chemical decomposition and reactions take place on the surface accompanied with surface migration to attachment sites. Fifth, by-products are desorbed from the surface. Sixth, the byproducts flow to the main gas stream by diffusion. Finally, a thermal process is used to force away the by-products from the deposition region. To grow relaxed heteroepitaxial germanium layers on silicon, the proper gas is needed that would lead to the chemical reaction on the surface. Epitaxial growth is unique in that the growth conditions are such that grown film takes the crystal lattice of the underlying surface substrate film. Ideally, the grown substrate will be single crystal if the underlying substrate is single crystal. For example, epitaxial silicon is grown by decomposing silane by the following reaction: SiH4 / Si þ 2H2

(4.2)

Similarly, epitaxial germanium is grown by decomposition of germane by the following reaction: GeH4 / Ge þ 2H2

(4.3)

So as a result, heteroepitaxial growth of Ge on single crystal Si should result in single crystal Ge. Growth of single crystal Ge on Si depends strongly on the growth conditions used. One of the major variables in this growth process is temperature. The temperature needs to be high enough to allow for the chemical reaction to take place and to allow for the Ge

FIGURE 4.12

The seven parts of a CVD process (1) transport of reactants by forced covection (2) transport of reactants by diffusion (3) adsorption of reactants (4) surface process (5) desorption of byproducts (6) transport of byproducts by diffusion (7) transport of byprodcuts by forced convection. Reprinted with permission from J. D. Plummer, M. D. Deal and P. B. Griffin, Silicon VLSI Technology, Prentice Hall, 2000 [16].

4.4 Si1
xGex growth solutions

47

atoms to arrange in a single crystal manner. For growing single crystal Ge layers, the typical growth temperatures for the proper reaction to take place on the surface ranges from 400 C to 600 C, with the higher temperature yielding the faster growth rate. Below 400 C temperature, the proper reaction may not take place and growth may result in polycrystalline Ge or even amorphous Ge. Apart from growth temperature the other variables that affect the growth are pressure and germane concentration. To get the best quality films, low pressure growth is needed. The germane concentration can be used to increase the growth rate of the layer. All these conditions may vary from chamber to chamber, so it is important to characterize and optimize the chamber and growth prior to growth. In addition, a very clean surface is needed to get good epitaxial growth. If there is any contaminant or native oxide, epitaxial growth will not occur. One of the most important consequences of the lattice mismatch of Ge on Si is that dislocations form during the heteroepitaxy to relieve the misfit stress. These dislocations form at the Si/Ge interface as misfit dislocations and subsequently thread to the surface as threading dislocations, generally making the layers unsuitable for device applications. It has been calculated that from thermodynamic arguments, that to grow ˚ of c-Si1
xGex film on Si (100) without dislocations, one must limit 100 A the Ge content to less than 50% [6].

4.4 Si1LxGex growth solutions With the above challenges highlighted, many novel ideas and techniques developed through research have been introduced to grow highquality Si1
xGex layers on Si. These layers have resulted in threading dislocation densities as low as 1  106 cm
2 hence making them useable for integration with Si and for optical/electrical devices [5,9,14,17e40]. These methods include using molecular beam epitaxy, solid phase epitaxy, graded buffer layer, chemical vapor deposition, and high temperature annealing. Some of these layers are geared toward electronics while others toward photonics. The following section highlights some of the key results in the Si1
xGex growth on Si over the years. In 1984, Bean et al. demonstrated pseudomorphic growth of Si1
xGex via Molecular Beam Epitaxy (MBE). In this work, they show for the first time a full range of alloy compositions with good crystallinity. In 1991, Fitzgerald et al. used graded buffer layers to grow fully relaxed c-Si1
xGex [18]. They grow compositionally graded c-Si1
xGex on Si at 900 C using both MBE and Rapid Thermal Chemical Vapor Deposition (RTCVD) with x ranging from 0.1 to 0.53. For the higher Ge fraction of 0.53 they get very

48

4. Si1exGex deposition and properties

low threading dislocation around 3  106 cm
2 confirmed by plan view TEM. Also in 1991, Eaglesham et al., use low temperature MBE to grow Ge on Si (x ¼ 1). They show that with the low temperature growth they can suppress islanding. They also study the effect of thickness on the relaxation [19]. In 1992, Malta et al., also grew Ge on Si (x ¼ 1) via MBE at 900 C. They see many defects at the interface but a very low density of 105 cm
2 further away. In 1993, Liu et al. got high-quality Ge on Si by solid phase epitaxy [21]. In 1998, Currie et al. also showed a way to control the threading dislocations in graded buffer layers [22]. This method allows for 100% Ge without the increase in dislocations. They achieved a low threading dislocation density of 2.1  106 cm
2 [22]. In 1999, Luan et al. introduced a two-step growth approach with high temperature cyclic annealing. With this approach they get threading dislocation density 2.3  106 cm
2 [23]. From 2004 to 2006 Nayfeh et al. from Stanford University introduced Multiple Hydrogen Annealing for Heteroepitaxy (MHAH) [5,14,24,25]. The technique involves CVD growth of Ge on Si, followed by in situ hydrogen annealing with subsequent growth and annealing steps. Misfit dislocations are concentrated at the Si/Ge interface rather than threading to the surface as expected in this 4.2% lattice mismatched system. Using this technique Ge layers were grown on Si with dislocation densities as low as 1  107cm
2 and Rrms surface roughness as low as 2.5 nm. This method can be extended to Si1
xGex for any percentage of x. The only added step is the high temperature hydrogen annealing at the end. In addition, a complete experimentally based theoretical model was developed to explain the MHAH method. The model shows that hydrogen annealing removes any native oxide from the surface allowing for high temperature Ge surface diffusion, which is governed by the surface chemical potential, to take place. Because the diffusion takes place from regions of high chemical potential to regions of low chemical potential in the strain relaxed film, the Ge layer flattens out to a smooth layer. Also, during the hydrogen annealing, the model shows that the high temperature leads to dislocation motion and subsequent annihilation. The combination of these two mechanisms and the multiple growth aspects of MHAH leads to a homoepitaxial step resulting in very high-quality Ge layers. Fig. 4.13 shows a topographical AFM image with Rrms value taken from 10  10 mm AFM scan showing 90% reduction in surface roughness. Fig. 4.14A and B is tilted HRSEM cross section of the unannealed sample along with the 825 degrees annealing sample showing the reduction in surface roughness. In Fig. 4.14A the evident is the large Ge islands from the SeK growth, while in Fig. 4.14B the islands have flattened out to a continuous layer. Fig. 4.15 shows a schematic representation of the MHAH method. The initial rough, high dislocation density layer is followed by the first

4.4 Si1
xGex growth solutions

49

FIGURE 4.13 Topographical AFM images with Rrms value from 10 mm  10 mm AFM scan showing 90% reduction in surface roughness [5].

annealing step and regrowth. This growth, annealing/growth can be repeated depending how thick the desired layer is. Also, this can be used for any x fraction in Si1
xGex. Fig. 4.16 is cross-sectional TEM of the MHAH Ge on Si which highlights the threading dislocations being concentrated at the interface. Fig. 4.17 shows plan view TEM showing the reduction in dislocations. The dislocation density drops from 7.3  108/cm2 to 1.5  107/cm2 [41]. The high-quality low density MHAH-Ge was used to fabricate MetaleSemiconductoreMetal (MSM) photodetectors [14]. Fig. 4.18 shows the cross section of fabricated MSM device. Fig. 4.19 shows the responsivity and photocurrent for the MHAH-Ge MSM device on Si operated at 1.55 mm. Responsivities of 0.76A/W are observed under 1V reverse bias, corresponding to 61% external quantum efficiency (h). The highest < of 0.85A/W, corresponding to h w 68%, was observed from a detector with 5 mm electrode width and spacing. Under similar conditions, the theoretical maximum collection efficiency, for a film of 4.5 mm thick, is 88% without accounting for reflections from the surface. In 2014, Abdul Hadi et al. used graded buffer layers to grow on Si1
xGex with x ¼ 0, 0.25, 0.41, and 0.56 [30,31]. The Si1
xGex layers are 2 and 4 mm Si1
xGex layer grown on pþ silicon substrate using a graded buffer layer to reduce the threading dislocation density. Using these solar cells with Si1
xGex (x ¼ 0.25, 0.41, and 0.56) active layers and an a-Si:H nþ emitter is fabricated. For the Si1
xGex cells, relaxed Si1
xGex active layers

50

4. Si1exGex deposition and properties

FIGURE 4.14 Top: Cross-sectional high-resolution SEM image (45 degrees cut): (A) no hydrogen anneal; (B) 825 C; Bottom: topographical AFM image of epi-Ge layer: (C) no hydrogen anneal; (D) 825 C. Reprinted with permission from A. Nayfeh, C. O. Chu, T. Yonehara and K. Saraswat, "Effects of Hydrogen Annealing on Heteroepitaxial-Ge Layers on Si: Surface Roughness and Electrical Quality," Applied Physics Letters (APL) , vol. 85, no. 14, p. 2815 , 2004 [24].

(either 2 or 4 mm thick) were epitaxially grown at 900 C on a 3, 5, and 6 mm thick graded, relaxed buffer layer (for x ¼ 0.25, 0.41, and 0.56, respectively) using SiH4 and GeH4 precursors in Low-Pressure Chemical Vapor Deposition (LPCVD) reactor. The Si1
xGex was doped in situ p-type to a level of approximately 1016 cm3 using B2H6. Fig. 4.20A shows a high-resolution cross-sectional TEM image of the fabricated a-Si:H/c-Si1
xGex/c-Si cells with 2 mm Si1
xGex and x ¼ 0.42. The Si1
xGex graded layer is w4 mm. The image shows a large density of dislocations in the graded layer as expected [30]. Fig. 4.20B shows enlarged images of the Si1
xGex active (absorber) layer (top) and graded layer (bottom). As expected, in the Si1
xGex absorber layer the density of dislocations is greatly reduced to a level that is not observed in crosssectional TEM. Using these layers, solar cells were fabricated, and their performance will be discussed in detail in Chapter 5. From the solar cell results, the effective lifetime versus x is extracted [30].

4.4 Si1
xGex growth solutions

FIGURE 4.15

51

MHAH method to deposit high-quality Ge on Si [5].

FIGURE 4.16 Cross-sectional TEM image of (A) 155-nm heteroepitaxial-Ge layer on Si grown with a single growth and H anneal step and (B) 400-nm heteroepitaxial-Ge layer on Si grown by the MHAH method. Reprinted with permission from A. Nayfeh, C. O. Chu, T. Yonehara and K. Saraswat, "Fabrication of high-quality p-MOSFET in Ge grown heteroepitaxially on Si," Electron Device Letters (EDL), vol. 26, pp. 311-313, 2005 [25].

Fig. 4.21 plots the effective lifetime versus Ge % and shows as expected the effective lifetime drops as Ge fraction increases. The lifetime extracted for Si0.75Ge0.25 is w1 ms, decreasing to w40 ns for Si0.44Ge0.56 [30]. In 2017, Dushaq et al. demonstrated low temperature deposition of germanium films on silicon using radiofrequency plasma-enhanced

52

4. Si1exGex deposition and properties

FIGURE 4.17 Plane view TEM showing reduction in defects from MHAH method. Reprinted with permission from A. Nayfeh, C. O. Chu, T. Yonehara and K. Saraswat, "Fabrication of high-quality p-MOSFET in Ge grown heteroepitaxially on Si," Electron Device Letters (EDL), vol. 26, pp. 311-313, 2005 [41].

FIGURE 4.18

Cross section of MSM photodetector fabricated on MHAH-Ge layer grown on Si starting substrate. Reprinted with permission from A. Nayfeh, C. O. Chu, T. Yonehara and K. Saraswat, "Fabrication of high-quality p-MOSFET in Ge grown heteroepitaxially on Si," Electron Device Letters (EDL), vol. 26, pp. 311-313, 2005 [14,41].

chemical vapor deposition (RF-PECVD) [33]. A two-step temperature technique and different GeH4 flow rates have been employed during the deposition process. Fig. 4.22A and B summarizes the two-step process of the Ge growth. In step one (low temperature (LT), high rate (HR)) the deposition was performed at 350 C with 3 sccm flow of GeH4. This step is followed by an in situ annealing at 350 C using 20 sccm of H2 and 200 sccm of Ar for 10 min. Some samples are grown without in situ annealing for comparison. After this, step two (high temperature (HT), low rate

4.4 Si1
xGex growth solutions

53

(Left) Photodetector responsivity at l ¼ 1.55 mm versus reverse bias for TiGe-Ti MSM-PDs with 5 mm finger width and spacing and 104 mm2 active area. (Right) Photocurrent of the MSM device versus light power at l ¼ 1.55 mm and different applied biases. Reprinted with permission from A. K. Okyay, A. Nayfeh, K. C. Saraswat, T. Yonehara, A. Marshall and Paul C McIntyre, "High-efficiency metal-semiconductor-metal photodetectors on heteroepitaxially grown Ge on S," Optics Letters, vol. 31, no. 17, pp. 2565-2567, 2006 [14,41].

FIGURE 4.19

FIGURE 4.20 (A) Cross-sectional TEM image of the fabricated a-Si:H/crystallineSi1
xGex/c-Si cell with 2 mm Si1
xGex, x ¼ 0.42 and Si1
xGex graded layer of w4 mm; (B) enlarged images of the Si1
xGex active layer (top) and graded layer (bottom). Reprinted with permission from S. A. Hadi, P. Hashemi, D. Nicole, A. Nayfeh and J. Hoyt, "Effect of germanium fraction on the effective minority carrier lifetime in thin film amorphous-Si/crystalline-Si1xGex/ crystalline-Si heterojunction Solar Cells," AIP Advances, vol. 3, no. 5, p. 052119, 2013 [30].

(LR)) of the Ge deposition starts immediately without removing the wafer from the system. The Ge growth carried out at 500 C with 1 sccm of GeH4. With these two steps one cycle of Ge growth is done. Fig. 4.23 shows HRSEM cross-sectional images of the deposited Ge films on Si. Study of the surface morphology of low temperature Ge seed layer revealed that a surface roughness as low as 0.5 nm can be achieved with in situ low temperature annealing in rich H2 chamber. Also, the Fast Fourier Transform pattern taken at the same area imaged by TEM for the seed layer exhibited crystalline nature due to the hydrogen induced

54

4. Si1exGex deposition and properties

FIGURE 4.21 Estimated effective lifetime, s eff versus Ge fraction for fabricated cells with 2 mm thick epi-Si1
xGex layer. Reprinted with permission from S. A. Hadi, P. Hashemi, D. Nicole, A. Nayfeh and J. Hoyt, "Effect of germanium fraction on the effective minority carrier lifetime in thin film amorphous-Si/crystalline-Si1xGex/crystalline-Si heterojunction Solar Cells," AIP Advances, vol. 3, no. 5, p. 052119, 2013 [30].

FIGURE 4.22 Schematic representation of Ge two-step growth. (A) One cycle of deposition, (B) growth of thick films. Reprinted with permission from G. H. Dushaq, M. S. Rasras and Ammar M. Nayfeh, "Low temperature deposition of germanium on silicon using Radio Frequency Plasma Enhanced Chemical Vapor Deposition," Thin Solid Films, pp. 585-592, 2017 [33].

FIGURE 4.23 High-resolution SEM images of the PECVD grown Ge-on-Si using two steps (LT/HR, HT/LR, 1 cycle growth). An EDS analysis of the film is shown in the insert. Reprinted with permission from G. H. Dushaq, M. S. Rasras and Ammar M. Nayfeh, "Low temperature deposition of germanium on silicon using Radio Frequency Plasma Enhanced Chemical Vapor Deposition," Thin Solid Films, pp. 585-592, 2017 [33].

4.4 Si1
xGex growth solutions

55

crystallization. Furthermore, study of the post-annealed Ge layers at different temperatures in H2 and N2 gas ambient revealed an improved electrical and transport properties of the films treated at T < 600 C. Also, samples annealed at 550 C show the lowest threading dislocation density (TDD) of w1  106 cm
2. MSM photodetectors fabricated using low temperature Ge layer grown directly on Si has been studied. Results revealed that w4 order of magnitude reduction of dark current is achieved by inserting w20 nm layer of a-Si:H. Furthermore, the photoresponse of the detector is tested under 1310 nm laser light. A responsivity of 0.9 A/W is achieved at 1 V reverse bias for detector fabricated with 20 nm barrier layer compared to 0.5A/w of the one without barrier layer. The low temperature processing of Ge/Si demonstrates a great potential for p-channel transistors and optical detectors applications in monolithically integrated CMOS platform. A highresolution image of the seed layer along with Si substrate is shown in Fig. 4.24C. In our growth, the high Ge flow rate, low deposition temperature, and the rich hydrogen flow are the main factors that suppress the 2D to 3D transition of SK growth. It is very crucial to have smooth seed layer with RMS roughness of w0.5 nm. The property of underlying layer strongly influences the surface morphology and crystallinity of the Ge films subsequently grown at 500 C. A fast Fourier transform (FFT) image of the film shown in Fig. 4.24C is depicted in Fig. 4.24D. The seed layer shows polycrystalline nature behavior as indicated by sharp dots in the FFT pattern. Hydrogen plays a major role in the transformation process from amorphous to crystalline at low temperature The incorporation of hydrogen helps in etching the week bonds in the GeeGe network, which promotes the generation of a prolong chain of crystalline order. Furthermore, RF-PECVD reactor promotes the nanocrystal growth at low temperature via plasma contribution. Fig. 4.24E shows the contrast appear in the diffraction pattern for the low and the high temperature Ge layer which related to the different GeH4 flow rates in each layer. As the film thickness increases, and far from the interface, a clear improvement in the film quality can be achieved. The threading dislocation density was also extracted on the layers using chemical etching [33]. Fig. 4.25 shows an optical micrograph image of the etch pits for 700 nm Ge epi-layer. Threading dislocation density is obtained by estimating the count of etch pits and then divided by its area and the layer is around 1  106 cm
2. A schematic diagram, Transmission Electron Microscope (TEM) and Scanning Electron Microscope images, and X-ray diffraction pattern of the fabricated photodetector layers are shown in Fig. 4.26. The optical response of the detectors is tested using monochromatic 1310 nm laser with incident optical power of 2.4 mW. The laser is coupled vertically to the sample using a vertically mounted fiber with a far field beam waist diameter of approximately 200 mm. The reflectivity of the PD surface is minimized by optimizing the thickness of the (SiO2) which acts as

56

4. Si1exGex deposition and properties

FIGURE 4.24 TEM cross section of Ge-on-Si growth. (A) and (B) bright field TEM (BFTEM), (C) HRTEM image of LT/HR layer, (D) fast Fourier transform (FFT) of (C), (E) LT/HR and HT/LR interface along with FFT pattern. Reprinted with permission from G. H. Dushaq, M. S. Rasras and Ammar M. Nayfeh, "Low temperature deposition of germanium on silicon using Radio Frequency Plasma Enhanced Chemical Vapor Deposition," Thin Solid Films, pp. 585-592, 2017 [33].

antireflecting coating (ARC). The IV characteristics of the detectors under illumination are measured by reverse biasing the top metal pads. The photoresponse with and without a-Si:H interlayer is shown in Fig. 4.27. The detectors fabricated without a-Si:H barrier interlayer exhibit very low photoresponse which is approximately the same as the dark current values. However, devices fabricated with just w5 nm barrier interlayer demonstrate a considerable difference between the illuminated and dark state. The difference is about two orders of magnitude at 1V.

4.5 Optical properties of Si1LxGex Optical properties of semiconductor materials are of crucial importance for their application in opto-electronics devices. The absorption of the light in a semiconductor is defined by extinction coefficient, k, which

4.5 Optical properties of Si1
xGex

57

FIGURE 4.25 Optical micrograph image of the etch pits for 700 nm Ge epi-layer. Reprinted with permission from G. H. Dushaq, M. S. Rasras and p. Ammar M. Nayfeh, "Low temperature deposition of germanium on silicon using Radio Frequency Plasma Enhanced Chemical Vapor Deposition," Thin Solid Films, pp. 585-592, 2017 [33].

FIGURE 4.26

Ge MSM based photodetector structure: (A) schematic representation; (B) SEM image of Ge-on-Si layer with an inset showing XRD spectra and TEM image of the photodetector layers; (C) SEM top view image of the fabricated detectors showing detector active area of 104 mm2. Reprinted with permission from G. H. Dushaq, M. S. Rasras and Ammar M. Nayfeh, "Low temperature deposition of germanium on silicon using Radio Frequency Plasma Enhanced Chemical Vapor Deposition," Thin Solid Films, pp. 585-592, 2017 [34].

58

4. Si1exGex deposition and properties

FIGURE 4.27 Photoresponse characteristics of Ge MSM detectors with and without a-Si: H interlayer. Reprinted with permission from A. Nayfeh, C. O. Chu, T. Yonehara and K. Saraswat, "Fabrication of high-quality p-MOSFET in Ge grown heteroepitaxially on Si," Electron Device Letters (EDL), vol. 26, pp. 311-313, 2005 [34].

describes how deep light is absorbed in the material by means of absorption coefficient, a, defined as a¼

4pk l

(4.4)

where l is wavelength of incident light. By using absorption coefficient, we can estimate the profile of the light attenuation in a material, defined at any depth, d, as: I ¼ Io e
ad

(4.5)

where Io is incident light intensity and reflection, R ¼ 0. Furthermore, the reflection and propagation of the light through semiconductor material and at different interfaces are determined by its refractive index, ns . Refractive index is defined as the ratio of the velocity of light in vacuum to the velocity of the light in the optical material [42,43]. Extinction coefficient and refractive index are both used to define optical behavior of the material and are combined in one term, called complex refractive index, e n: e n ¼ ns þ ik

(4.6)

Complex refractive indices for Si1
xGex alloys with various Ge fractions are shown in Fig. 4.28. Data shown in Fig. 4.28 are combined from different resources, from Kasper [44] and by Sopra (now part of Semilab Co. Ltd [46], which has since been published online by various other sources [45,47]). Both refractive index and extinction coefficients increase with increasing Ge fraction, resulting in higher optical absorption of Si1
xGex alloys with higher Ge content.

References

59

FIGURE 4.28 Optical properties of Si, Ge, and undoped Si1
xGex alloys: (A) refractive index and (B) extinction coefficients [3,44,45].

4.6 Conclusion In conclusion, Si1
xGex heteroepitaxy on Si has been one of the important research challenges over the last 25 years. The potential for integration of Si1
xGex on Si for photonic applications is important and exciting. The challenge is due to the lattice mismatch between Si and Ge that results in dislocation and poor material quality for devices. The chapter highlights and discusses the reasons for the dislocations and the growth modes/mechanisms. Some of the main innovations and solutions that were obtained over the years include Si1
xGex grading buffer layer, high temperature cyclic annealing, hydrogen annealing, and low temperature PECVD, to name some. The innovations have resulted in layers with density as low as 1  106 suitable for a plethora of devices to including photovoltaics to be discussed in chapter 5.

References [1] S. Banerjee, B. Streetman, Solid State Electronic Devices, Prentice Hall, 1998. [2] A. Bett, F. Dimroth, G. Stollwerck, O. Sulimi, III-V compounds for solar cell applications, Appl. Phys. A 69 (1999) 119e129. [3] S. Abdul Hadi, III-V on Si Multi-Junction Step-Cell: PhD Dissertation, Masdar Institute of Science and Technology, Abu Dhabi, 2016. [4] S. Soresi, InP Based Tandem Solar Cells Integrated onto Si Substrates by Heteroepitaxial MOVPE, Electronics, Universite´ Montpellier, 2018.

60

4. Si1exGex deposition and properties

[5] A. Nayfeh, Heteroepitaxial Growth of Relaxed Germanium on Silicon, Stanford Thesis, 2006. [6] R. People, J. Bean, Alculation of critical layer thickness versus lattice mismatch GexSi1x/Si strained-layer heterostructures, Appl. Phys. Lett. 47 (3) (1985) 322e324. [7] S. Adachi, Silicon-germanium alloy (SixGe1-x), in: Optical Constants of Crystalline and Amorphous Semiconductors, Springer, Boston, 1999. [8] V.L. Tassev, S.R. Vangala, Thick hydride vapor phase heteroepitaxy: a novel approach to growth of nonlinear optical material, Crystals 9 (8) (2019) 393. [9] D.J. Eaglesham, M. Cerullo, Dislocation-free Stranski-Krastanow growth of Ge on Si(100), Phys. Rev. Lett. 64 (16) (1990) 1964. [10] W.H. Brattain, J. Bardeen, Dislocation-free Stranski-Krastanow growth of Ge on Si(100), Phys. Rev. Lett. 64 (1990) 1943e1946. [11] H. Kim, Z.M. Zhao, Y. Xie, Three stage nucleation and growth of Ge self-assembled quantum dots grown on partially relaxed SiGe buffer layers, Phys. Rev. B 68 (2003) 205312. [12] Silicon Based Epitaxial Thin Films, MKS Instruments, 2021. Available, https://www. mksinst.com/n/silicon-epitaxial-thin-films. [13] H.-C. Luan, Ge Photodetectors for Si Microphotonics, MIT Ph. D. Thesis, 2001. [14] A.K. Okyay, A. Nayfeh, K.C. Saraswat, T. Yonehara, A. Marshall, P.C. McIntyre, Highefficiency metal-semiconductor-metal photodetectors on heteroepitaxially grown Ge on S, Opt Lett. 31 (17) (2006) 2565e2567. [15] K.H. Lee, S. Bao, B. Wang, C. Wang, S.F. Yoon, J. Michel, E.A. Fitzgerald, C.S. Tan, Reduction of threading dislocation density in Ge/Si using a heavily As-doped Ge seed layer, AIP Adv. 6 (2016) 025028. [16] J.D. Plummer, M.D. Deal, P.B. Griffin, Silicon VLSI Technology, Prentice Hall, 2000. [17] J.C. Bean, T.T. Sheng, L.C. Feldman, A.T. Fiory, R.T. Lynch, Pseudomorphic growth of GexSi1-x on silicon molecular bean epitaxy, Appl. Phys. Lett. 44 (1984) 102. [18] E.A. Fitzgerald, Y. Xie, M.L. Green, D. Brasen, A.R. Kortan, J. Michel, Y. Mii, B.E. Weir, Totally relaxed GexSi1
x layers with low threading dislocation densities grown on Si substrates, Appl. Phys. Lett. 59 (1991) 811e813. [19] D.J. Eaglesham, M. Cerullo, Low temperature growth of Ge on Si (100), Appl. Phys. Lett. 58 (1991) 2276. [20] D.P. Malta, J.B. Posthill, R.J. Markunas, Low-defect-density germanium on silicon obtained by a novel growth phenomenon, Appl. Phys. Lett. 60 (1992) 844. [21] W. Lui, J.S. Chen, D. Lie, M. Nicolet, Ge epilayer of high quality on a Si substrate by solid-phase epitaxy, Appl. Phys. Lett. 63 (10) (1993) 1405. [22] M. Currie, S. Samavedam, T.A. Ladgdo, C.W. Leitz, E.A. Fitzgerald, Controlling threading dislocation densities in Ge on Si using graded SiGe layers and chemical-mechanical polishing, Appl. Phys. Lett. 72 (14) (1998) 1718. [23] H.-C. Luan, D.R. Lim, K.K. Lee, K.M. Chen, J.G. Sandland, K. Wada, L.C. Kimerling, High-quality Ge epilayers on Si with low threading-dislocation densities, Appl. Phys. Lett. 75 (1999) 2909e2911. [24] A. Nayfeh, C.O. Chu, T. Yonehara, K. Saraswat, Effects of hydrogen annealing on heteroepitaxial-Ge layers on Si: surface roughness and electrical quality, Appl. Phys. Lett. 85 (14) (2004) 2815. [25] A. Nayfeh, C.O. Chu, T. Yonehara, K. Saraswat, Fabrication of high-quality p-MOSFET in Ge grown heteroepitaxially on Si, Electron Device Letters (EDL) 26 (2005) 311e313. [26] Z. Zhou, J. He, R. Wang, Heteroepitaxial growth of Ge films on Si substrates and its applications in optoelectronics Physics 40 (2011) 799e806. [27] S. Kang, Y.-H. Kil, B.G. Park, C.-J. Choi, T.S. Kim, T.S. Jeong, K.-H. Shim, Optical properties of Si1
xGex quantum dots grown using RPCVD, Electron. Mater. Lett. 7 (2011) 121e125.

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[28] B. Yan, L. Zhao, B. Zhao, J. Chen, Hydrogenated amorphous silicon germanium alloy with enhanced photosensitivity prepared by plasma enhanced chemical vapor deposition at high temperature, Vacuum 89 (2013) 43e46. [29] K. Tao, J. Hanna, Epitaxial growth of germanium-rich silicon-germanium films on Si(001) substrate by reactive thermal chemical vapor deposition, Appl. Surf. Sci. 282 (2013) 472e477. [30] S. Abdul Hadi, P. Hashemi, D. Nicole, A. Nayfeh, J. Hoyt, Effect of germanium fraction on the effective minority carrier lifetime in thin film amorphous-Si/crystallineSi1xGex/crystalline-Si heterojunction Solar Cells, AIP Adv. 3 (5) (2013) 052119. [31] S. Abdul Hadi, P. Hashemi, N. DiLello, E. Polyzoeva, A. Nayfeh, J.L. Hoyt, Thin-film Si1
xGex HIT solar cells, Sol. Energy 103 (2014) 154e159. [32] V. Sorianello, G.D. Angelis, A.D. Iacovo, L. Colace, S. Faralli, M. Romagnoli, High responsivity SiGe heterojunction phototransistor on silicon photonics platform, Opt Express 23 (2015) 28163e28169. [33] G.H. Dushaq, M.S. Rasras, A.M. Nayfeh, Low temperature deposition of germanium on silicon using radio frequency plasma enhanced chemical vapor deposition, Thin Solid Films 636 (2017) 585e592. [34] G.H. Dushaq, M.S. Rasras, A.M. Nayfeh, Metal-germanium-metal photodetector grown on silicon using low temperature RF-PECVD, Opt Express 25 (25) (2017) 32110e32119. [35] Y. Yamamoto, P. Zaumseil, M.A. Schubert, A. Hesse, J. Murota, B. Tillack, Abrupt SiGe and Si profile fabrication by introducing carbon delta layer, ECS J. Solid State Sci. Technol 6 (2017) 531. [36] W. Lim, M. Manjappa, Y. Srivastava, L. Cong, A. Kumar, K. MacDonald, R. Singh, Ultrafast all-optical switching of germanium-based flexible metaphotonic devices, Adv. Mater. 30 (2018) 1705331. [37] H. Ru¨cker, B. Heinemann, High-performance SiGe HBTs for next generation BiCMOS technology, Semicond. Sci. Technol. 33 (2018) 114003. [38] C. Kim, H. Kang, W. Park, Epitaxial Ge solar cells directly grown on Si (001) by MOCVD using isobutylgermane, J. Kor. Phys. Soc. 72 (2018) 633e638. [39] L. Becker1, G. Schwalb, T. Schroeder, M. Albrecht, Controlling the relaxation mechanism of low strain Si1
xGex/Si(001) layers and reducing the threading dislocation density by providing a preexisting dislocation source, J. Appl. Phys. 128 (2020) 215305. [40] P. Liu, K. Wu, S. Xiahou, Y. Yang, S. Chen, R. Lei, P. Guo, W. Wang, G. Li, High-quality Ge film grown on Si substrate and its thermodynamic mechanism, Vacuum 186 (2021) 110068. [41] A.K. Okyay, A. Nayfeh, K. Saraswat, T. Yonehara, A. Marshall, K. Saraswat, Strain enhanced high efficiency germanium photodetectors in the near infrared for integration with Si, in: LEOS 2006 - 19th Annual Meeting of the IEEE Lasers and ElectroOptics Society, 2006, pp. 460e461. [42] M. Fox, Optical Properties of Solids, Oxford University Press, 2001, pp. 2e7. [43] B. Saleh, M.C. Teich, Photonic-crystal optics, in: Fundamentals of Photonics, second ed., WILEY, New Jersey, 2007, pp. 246e252. [44] E. Kasper, Properties of Strained and Relaxed SiGe, Institution of Electrical Engineers, London, 1995. [45] Software Spectra Inc., Optical Data from Sopra SA. Available at: http://www.sspectra. com/sopra.html. (Accessed 2016). [46] S. Semilab, News: Semilab acquires assets of SOPRA. Available at: https://www. semilab.hu/category/news/sopra. [47] Ioffe Institute, n,k Databse. Available at: http://www.ioffe.rssi.ru/SVA/NSM/nk/ index.html. (Accessed 2015).

C H A P T E R

3 Basics of solar cells 3.1 The photovoltaic effect Edmund Becquerel discovered the photovoltaic (PV) effect in 1839, when he observed that shining light on a silver-coated platinum electrode immersed in electrolyte generated an electric current [1,2]. Albert Einstein published a paper in 1905 explaining the details of photoelectric effect, although the first PV devices were fabricated three decades earlier, by William Adams and Richard Day in 1876 using selenium [3]. Once technology evolved, silicon p/n junctions were first reported in 1954 by Chapin, Fuller, and Pearson [4]. Initially, for a brief period, PV solar research was moving fast in research and technology circles, but funding for it decreased significantly in early 1980s, only to take off again in early 2000s and onward [5]. The research into PV solar cells and solar energy gained traction in early 2000s mainly due to increasing awareness about effect of fossil fuels on climate change, as well as increasing energy demand. Fig. 3.1 shows world’s primary energy consumption in terawatthours over the years [6], with almost linear trend with increasing time. Furthermore, semiconductor industry for Integrated Chip (IC) fabrication matured over past few decades, which also provided access to lowcost fabrication technology for solar cells, that was not available back in 1980s. Having high-throughput technology and know-how easily available allowed for fabrication of low-cost PV solar cells with $/Watt costs comparable to fossil fuelebased energy. Moreover, PV solar cells efficiency has been increasing ever since, further driving down the cost of generated kWh, making it cheaper than electricity generated from fossil fuels.

Silicon-Germanium Alloys for Photovoltaic Applications https://doi.org/10.1016/B978-0-323-85630-0.00004-2

17

© 2023 Elsevier Inc. All rights reserved.

18

3. Basics of solar cells

FIGURE 3.1 World primary energy consumption (TWh) over the years [6].

3.2 Solar energy Solar energy is an electromagnetic radiation ranging from ultraviolet to infrared spectral range (200ew3000 nm). Solar radiation is filtered through Earth’s atmosphere, and its intensity is reduced by means of ozone absorption, water vapor, and scattering by airborne dust and aerosols [7]. The standard value assumed for the solar radiation intensity in free space, just outside of Earth’s atmosphere, is 1353 W/m2, while at surface of the Earth that value is approximately 1000 W/m2 [4, p. 19]. Those atmospheric effects on solar spectrum are categorized by the air mass factor (AM), which is a measure of the optical path length relative to the minimum path length when the sun is directly overhead. AM 0 standard represents a solar spectrum outside of the Earth’s atmosphere, while AM 1.5 standard is an acceptable energy-weighted average for terrestrial applications [7,8]. AM 1.5 standard at the surface of the Earth can further be classified into AM 1.5G (Global) and AM 1.5D (Direct þ Circumsolar) spectra where AM 1.5G is a standard for global outdoor 1 sun irradiation (diffuse and direct), while AM 1.5D is a standard mostly used to analyze concentrated solar power performance. Fig. 3.2 shows standard spectra for AM 0, AM 1.5G, and AM 1.5D [9]. Solar incident power density, Ps , for AM 1.5G irradiation is approximated to be 1000 Wm2 , while it is w900 Wm2 for AM 1.5D spectrum. The standard incident power density is often used as an input power when the efficiency of solar cell’s under 1 sun is measured and calculated.

3.3 PV solar cells and solar power generation

19

FIGURE 3.2 Extraterrestrial (AM 0) solar spectrum (blue dotted line), standard global terrestrial (AM 1.5G) spectrum (full black line), and direct þ circumsolar (AM 1.5D) spectrum, obtained from NREL [9].

3.3 PV solar cells and solar power generation Solar cells are fundamental elements of a PV solar generation (Fig. 3.3A). The most basic structure of a solar cell is a p/n junction with antireflective coating (ARC) and metal contacts. When exposed to the sun, solar cells provide photovoltage, that can range between 0.5 and 1 V or higher, depending on the material used or the type and structure of the cell. Most stand-alone solar power generation systems are used to charge DC batteries, which require 12 V power supply. In order to achieve required DC voltage, solar cells are connected in series where their individual photovoltages add up, thus forming a solar module (Fig. 3.3B). Typical Si module has 36 cells, with newer models housing more cells by utilizing half-cell technology to minimize resistive or shading losses that amplify in series connections [10]. Furthermore, to supply sufficient amount of solar power, solar modules are then connected in parallel or series, depending on the final voltage and ampere requirements. This makes up a solar array, the final structure that is visible at a PV power plant (Fig. 3.3C).

3.3.1 Solar cell operation and currentevoltage characteristics Solar cells function based on collection of photogenerated free minority carriers by absorption of incident light. The single p/n junction solar cells are the most widely produced cells in the market today, with Si solar cells

20

3. Basics of solar cells

FIGURE 3.3 Illustration of (A) solar cell, (B) solar module combined of solar cells connected in series, and (C) solar array where modules are connected in parallel and series, depending on required voltage and current specifications.

making up majority of the commercial cells. The Si solar cells could have different levels of quality, ranging from monocrystalline (single crystal) high-quality cells, polycrystalline Si cells with average quality but costeffective, and amorphous Si cells that are mostly used for thin-film, low-cost solar cells. The p/n junction can be made by using one

3.3 PV solar cells and solar power generation

21

semiconductor and it is often called a homojunction, or with two different semiconductor materials forming a heterojunction solar cell. Furthermore, depending on the material and structure used, there are p/i/n types of cells where “i” stands for an intrinsic absorber layer, heterojunction solar cells mixing up more than one semiconductor material, heterojunctions with intrinsic layer (HIT) solar cells, organic solar cells, hybrid organicsemiconductor solar cell, etc. Fig. 3.4 shows an illustration of a simple single-junction (SJ) solar cell comprising of basic components: absorber and emitter normally forming a p/n junction, ARC, and back/front contacts that are used for efficient collection of photogenerated current. As illustrated in Fig. 3.4, some of the incident light gets reflected at different interfaces of the cells, while absorbed light results in the generation of electronehole pair (EHP), giving rise to photocurrent. Photogenerated current in a solar cell under illumination is directly dependent on the energy spectrum and the intensity of incident light. Wavelength of the incident photon is related to energy transition, DE, through the relation: l¼

hc 1:24 ¼ ðmmÞ DE DEðeVÞ

(3.1)

where l is the wavelength, h is Planck’s constant, and c is speed of light. Incident photon creates an EHP when it has sufficient energy to excite an electron from a valence band (Ev) to a conduction band (Ec) energy level. For this to happen, photon energy needs to be greater than the bandgap, Eg, of the semiconductor [7]. While the number of generated free carriers depends on the incident illumination and semiconductor material properties such as material bandgap, the collected photocurrent is also a

ARC

Emier

e

-

h+

Absorber Contacts

FIGURE 3.4 Schematics of a simple single-junction solar cell.

22

3. Basics of solar cells

function of how efficiently a solar cell collects those newly generated free carriers. This photogenerated carrier collection efficiency is called quantum efficiency (QE), and it is the probability of collecting an electron for every incident photon [4]. Eq. (3.2) defines the relationship between photogenerated current density, Jph, and incident spectral photon flux density, F (number of photons/unit area/unit time), solar cell’s QE, and semiconductor bandgap [4]. Z N Jph ¼ q FðEÞQEðEÞdE (3.2) Eg

where q is electron charge (q ¼ 1:6  1019 C), and current, J, is defined as current per unit area of the cell (J ¼ I/Area). QE of solar cells is a strong function of overall solar cell design, fabrication process, and material properties. Some of the design aspects that affect QE are the reflection of the incident light and absorber/emitter layer thickness or doping. From material properties aspect, carrier lifetime should be large enough, such that EHPs generated far from the junction and depletion layer can be collected before they reach junction and recombine. Finally, processing technology can introduce various recombination effects at surfaces and interfaces, which again can negatively affect probability of collection of photogenerated free carriers before they recombine. In the dark, a solar cell operates as a normal diode, with thermally generated current J0, also called dark current, and under ideal conditions can be calculated as:   Dp Dn pn þ np J0 ¼ q (3.3) Lp Ln where Dp and Dn are hole and electron diffusivity, respectively; Ln and Lp are electron and hole diffusion lengths, respectively; and np and pn are minority carrier concentrations. Diffusivity is a function of carrier mobility, m, and can be defined using Einstein relation D ¼ m kT q , where k is

Boltzmann’s constant (k ¼ 8:62  105 eV=K), and T is the temperature (in pffiffiffiffiffiffi Kelvin) [7]. Diffusion length can be expressed as L ¼ Ds, where s is the minority carrier lifetime [7]. Solar cell dark current density, Jdark, is a function of thermally generated current density, J0, and many other recombination factors that take place in nonideal conditions. Net dark current with various recombination mechanisms taking place simultaneously can be approximated to:   V q Jdark z J0 m kT  1 (3.4) e where m is ideality factor.

3.3 PV solar cells and solar power generation

23

For an ideal (Shockley) diode, ideal dark current density, Jdark;ideal , can be approximated by using Eq. (3.4) and setting m ¼ 1 [11], where zero recombination in depletion (space charge) region is assumed (JSCR ¼ 0). Zero recombination in the depletion region approximation is usually assumed for indirect bandgap materials, while for direct bandgap materials with strong absorption and for cells with very wide depletion region, space charge region (SCR) recombination may be dominant [4]. Recombination current in SCR can be approximated to Ref. [4]: qni W JSCR ¼ pffiffiffiffiffiffiffiffiffi sn sp

(3.5)

where ni is semiconductor intrinsic carrier concentration, W is SCR width, and sn and sp are minority carrier lifetime of p and n regions, respectively. Current density delivered by an ideal solar cell is a superposition of the photogenerated current density, Jph, and dark current density, J0, and is defined as:   qV (3.6) J ¼ Jph  J0 kT  1 e Additional, nonideal characteristics of practical solar cells are caused by many factors, such as power dissipation due to contact resistance or the leakage due to device perimeter effects. The resistive effects can be approximated to electrically equivalent resistances connected in series, modeled as Rs , and connected in parallel (shunt), modeled as Rsh , as shown in Fig. 3.5. Eq. (3.7) shows nonideal approximation for current density of the solar cell taking into account effects of Rs and Rsh [4], while in ideal conditions, Rs ¼ 0 and Rsh ¼ N. 0 1 qðVþJARs Þ V þ JARs (3.7) J ¼ Jph  J0 @e mkT  1A  Rsh

FIGURE 3.5 Equivalent circuit for nonideal solar cell, including series and shunt resistances. Reproduced with permission from S. Abdul Hadi, III-V on Si Multi-Junction Step-Cell, PhD Dissertation, Masdar Institute of Science and Technology, Abu Dhabi, 2016.

24

3. Basics of solar cells

3.3.1.1 Short circuit current and open circuit voltage With ideal conditions (Rs ¼ 0 and Rsh ¼ N), shorting output terminals of circuit in Fig. 3.4 results in the total current density through circuit approximately equal to photogenerated current density, Jph . Thus, this current density is referred to as short circuit current density, Jsc , and it is the maximum current density generated by a solar cell. Furthermore, maximum voltage difference under illumination at the output terminals of the circuit in Fig. 3.5 is achieved when output terminals are left open (isolated) and it is called an open-circuit voltage, Voc . Open-circuit voltage is limited by the type of semiconductor used in solar cell, particularly by its bandgap, and is defined as [7]:   kT Jsc þ1 (3.8) Voc ¼ ln q J0 Current density versus voltage (J-V) characteristics of a typical solar cell are shown in Fig. 3.6. The effects of series and shunt resistance on the J-V characteristics are shown in red (light gray in print version) and blue (gray in print version) lines, respectively. 3.3.1.2 Fill factor Solar cells deliver power when they operate under forward bias and illumination, where maximum power is given by: Pmax ¼ Jmax $Vmax

(3.9)

FIGURE 3.6 J-V characteristics, with effects of series (Rs ) and shunt (Rsh ) resistance on J-V curve shown in red (light gray in print version) and blue (gray in print version), respectively. Reproduced with permission from S. Abdul Hadi, III-V on Si Multi-Junction Step-Cell, PhD Dissertation, Masdar Institute of Science and Technology, Abu Dhabi, 2016.

3.3 PV solar cells and solar power generation

25

Vmax is always lower than Voc, and it is constrained by the material bandgap, lattice thermalization, and other nonradiative losses in solar cell. When ideally, Vmax and Jmax are equal to the values of Voc and Jsc , respectively, theoretical maximum power deliverable by the solar cell is equal to product of Jsc and Voc. The ratio between the cell’s actual Pmax and theoretical maximum power of JscVoc is measured by a fill factor, FF, defined as: FF ¼

Jmax $Vmax Jsc $Voc

(3.10)

Typical J-V curve and power density for a solar cell are illustrated in Fig. 3.7, where maximum delivered power (Jmax $Vmax ) and maximum theoretically deliverable power (Jsc $Voc ) are shown in terms of area of green (light gray in print version) and blue (gray in print version) rectangles, respectively. The FF is decreased when nonideal aspects are present, such as resistive losses, increased leakage current, and diode ideality factor m larger than 1. For theoretical analysis of solar cells performance, it is convenient to estimate maximum theoretical FF, so that resistive and other losses could be quantified. Expression of a maximum theoretical FF is given by FF ¼

vOC  lnðvOC þ 0:72Þ vOC

(3.11)

q

where vOC ¼ mkTVOC and T is the operating temperature of the solar cell [13].

FIGURE 3.7 Current density (black) and power density (red; dark gray in print version) of a solar cell as a function of voltage. Also shown are rectangles JmaxVmax (green dotted rectangle; light gray in print version) and ideal JscVoc (blue dashed rectangle; gray in print version). Reproduced with permission from S. Abdul Hadi, III-V on Si Multi-Junction Step-Cell, PhD Dissertation, Masdar Institute of Science and Technology, Abu Dhabi, 2016.

26

3. Basics of solar cells

3.3.1.3 Conversion efficiency The solar cell conversion efficiency, h, is defined as a ratio of input light power density, Ps, and maximum output power, Pmax . Standard for input power density under 1 sun is Ps ¼ 1000 Wm2 (AM 1.5G). Maximum output power can be calculated as: Pmax ¼ Jsc Voc FF, so that efficiency, h, is given by: h¼

Jsc $Voc $FF Ps

(3.12)

The nonradiative recombination mechanisms are reflection of material quality, and they can greatly affect the conversion efficiency of solar cells. This effect can be defined through bandgap voltage offset parameter, Woc, given as: Woc ¼

Eg  Voc q

(3.13)

Since Voc is a function of energy bandgap, by using bandgap offset defined in Eq. (3.13), the effect of bandgap on solar cells performance is removed. Thus, using Woc allows comparison between solar cells made from various materials (different bandgap) with different levels of material quality [14]. R.R. King et al. have summarized Woc values for SJ solar cells for a range of different bandgap materials, as shown in Fig. 3.8 (after [15]). Also shown in Fig. 3.8 are theoretical Woc values calculated based on

FIGURE 3.8 Woc of single junction solar cells for a range of different bandgap materials (after [15,16]). Reproduced with permission from S. Abdul Hadi, III-V on Si Multi-Junction StepCell, PhD Dissertation, Masdar Institute of Science and Technology, Abu Dhabi, 2016.

3.3 PV solar cells and solar power generation

27

detailed balance theory (blue dashed; gray in print version) and also taking radiative recombination into account (red dashed; light gray in print version), as well as Woc calculated from data reported by M. Green et al. [16]. From theoretical values, it can be observed that Woc changes very slightly due to material bandgap, which means that Woc allows us to compare the performance, design, and material quality of solar cells made of low and high bandgap materials. Furthermore, difference between experimental Woc and theoretical values shows the effect of nonradiative recombination factors in each of the cells. It is clear that GaAs SJ solar cells have reached their theoretical limits, while cells made of other materials still have room for improvement.

3.3.2 Multi-junction solar cell operation Multi-junction (MJ) solar cells are made of a stack of two or more SJ subcells. The subcells can be electrically connected in series or in parallel and can be monolithic or individual cells bonded together. The advantage of MJ solar cells is that each subcell absorbs the incident photons with energy, E ¼ hn (where h is Planck’s constant and n is the incident light frequency), close to cell’s bandgap, thus optimizing light absorption and reducing the lattice thermalization losses that occur when high energy photons are absorbed. MJ solar cells are optimally designed such that higher bandgap materials, which absorb larger energy photons (shorter wavelengths), are placed on top, while materials with smaller bandgap that absorb the light with lower energy photons (longer wavelengths) are placed under the top subcell. In this manner, less energy is wasted through lattice thermalization from absorbed excess energy. Fig. 3.9 illustrates light absorption in MJ solar cell stack (a), where high energy photons (short wavelengths) are absorbed in high bandgap top subcell and lower energy photons are transmitted into underlying subcell with lower bandgap [12]. In series connection, an MJ cell is a two-terminal (2T) device, whose efficiency is limited by the lowest current generated in one of the subcells, while subcell voltages add up. The performance of a 2T MJ solar cell is optimized when subcell currents are matched. In a traditional 2T MJ cell design, current-matching conditions impose restrictions on the selection of the energy bandgap, Eg, and absorber thicknesses of the subcells. Fig. 3.10 shows an illustration of a simple 2T dual-junction solar cell with ARC, connected in series via tunnel diode (TD) or another conductive layer. Most commonly used material for bottom subcell in commercially available MJ solar cells is Germanium (Ge). Ge has a low bandgap and absorbs wavelengths up to an infrared region, which makes it an ideal candidate for the last (bottom) cell in MJ stack. Subcells made of several

28

3. Basics of solar cells

FIGURE 3.9 Illustration of (A) light absorption in triple-junction solar cell stack and (B) corresponding wavelength in standard AM 1.5 G spectrum. Reproduced with permission from S. Abdul Hadi, III-V on Si Multi-Junction Step-Cell, PhD Dissertation, Masdar Institute of Science and Technology, Abu Dhabi, 2016.

ARC

Top Cell TD / Conductive Layer

Bottom Cell Contacts

FIGURE 3.10 Illustration of a typical two-terminal dual-junction solar cell with antireflective coating (ARC), connected in series using either tunnel diode (TD) or transparent conductive layer.

III-V compounds are normally placed above the Ge bottom cell because of their tunable bandgap and close lattice constant to Ge. Nevertheless, use of Ge substrates adds to the high cost of MJ solar cells and research trends presently focus on finding lower cost solutions. MJ solar cells based on III-V materials have the highest reported experimental and theoretical efficiencies [16e21]. Currently, the highest reported efficiency of 39.2% is reported for 6 junction solar cells made by National Renewable Energy Laboratory (NREL) [16,19]. However, MJ solar cells are mostly limited to niche applications such as use in space or for unmanned aerial vehicles, due to their high costs.

3.3 PV solar cells and solar power generation

29

Recently there have been ongoing efforts to make MJ solar cells more widely commercially available by achieving high conversion efficiency (h) at a lower cost. One of the design approaches to lower costs of MJ solar cells is by using silicon (Si) as a base for MJ solar cells fabrication. Si is an attractive and cost-effective alternative, due to its abundance, low cost, and mature state of the Si solar cell technology. Theoretically, it was shown that for 2T dual-junction solar cell, maximum theoretical efficiency of w38% can be achieved when the bottom cell bandgap, EgB, is 1.1 eV (such as Si), and the top cell bandgap, EgT, is 1.7 eV (such as GaAs0.7P0.3 from the group of III-V materials) [22]. Based on bandgap values and their absorption properties, the most suitable material for top subcell of Sibased MJ solar cells are III-V materials [23,24]. Another way of using Si to lower MJ solar cell production cost is as substrate carrier for growth of high-quality III-V materials, usually via Si1xGex layers [25e28].

3.3.3 Solar cell design considerations In order to optimize performance of SJ and MJ solar cells, a number of design parameters are taken into account. For solar cells in general, most common design optimization factors include: minimizing reflection losses, ensuring long diffusion length (i.e., high minority carrier lifetime), increasing optical path or number of light passes through the absorber layer, improving open-circuit voltage by engineering proper junction interface or junction doping, minimizing resistive and shading losses, etc. In addition to these general design concerns, improving MJ solar cell designs often concentrates on accomplishing the maximum limiting current by optimizing subcell bandgap and absorber thickness in order to achieve the current-matching condition. Areal current matching for tandem cells can also be used, where the top cell has a bandgap larger than the bottom cell and the area of bottom cell is increased such that current matching is achieved [24,29]. In addition to each subcell bandgap and thickness, their individual material properties, such as minority carrier lifetime and diffusion length, considerably affect the design optimization of MJ solar cells. Since diffusion length is an actually effective absorber layer thickness, the subcell design has to take that into account, so that layer thickness of a subcell is approximately close to the diffusion length of the material. This is especially important for top layers, so that incident light is utilized in the most optimum way. For example, for III-V solar cells that are grown on Si substrates, minimizing threading dislocation density in grown III-V layers is very important, since these dislocations can substantially degrade minority carrier lifetime and diffusion length in the grown layers.

30

3. Basics of solar cells

Moreover, ARC is another important design factor in MJ solar cells. ARC thickness and design can be adjusted to a favor specific wavelength range (longer or shorter wavelengths), such that current in a specific subcell can be increased in order to achieve current-matching condition. For example, if the top cell material is thin or it has a short diffusion length due to poor minority carrier lifetime, the ARC can be designed such that reflection in shorter wavelengths is minimized and optical current in top subcell is increased. Overall, MJ design optimization is a symbiosis of material electrical and optical parameters that all mutually interact and need to be taken into consideration simultaneously.

3.4 Light management for PV solar cells Most semiconductor materials have refractive index considerably higher (n w 3) than that of the air (n ¼ 1) or glass (n w 1.4). When two materials have such different refractive indices, the incident light is significantly reflected at the material interface resulting in large reduction of solar cell’s efficiency. For example, uncoated crystalline silicon (c-Si) surface (refractive index n w 3.7) at the interface with air (n w 1) reflects between 30% and 48% of the light incident on the material [30]. In order to improve the performance of solar cells, it is necessary to employ optimized ARC in order to reduce the amount of reflected light. The designs of optimum ARC material, layer thickness, number of ARC layers, as well as surface texturing are all studied with the purpose of optimizing the solar cell performance [30e36]. Ideally, the ARC material should be abundant and inexpensive, transparent to most of the solar spectrum absorbed by the cell and compatible with materials and processes used in solar cell production. Single-layer ARC minimizes the reflection at one specific wavelength, socalled “quarter-wave” ARC layers, while the rest of the wavelengths are often highly reflected. In order to reduce reflection in a wider range of wavelengths, double and multilayer ARCs can be utilized. However, the choice of the ARC materials for double-layer and multilayer ARCs is more restricted because of refractive index constraints [31e33]. Different materials such as SiO2, SiOx, SiNx, Si3N4, TiO2, ZnO, ITO, ZnS, MgF2/ZnS, etc., have good ARC properties [30e36], with their performance depending on the deposition conditions and solar cell application. Another way of reducing the reflectance is by surface texturing, which is of most interest for concentrated solar cells with normal light incidence [31].

3.6 Nanotechnology in PV solar cells

31

With growing development of tandem cell applications for high efficiency, ARC design specifically tuned to optimize MJ cell performance is needed. Since for optimum performance of MJ cells, current generated in all subcells needs to match, the ARC can be designed to maximize optical absorption in the cells with lowest photogenerated current base cell, but without major reduction in the performance of other subcells in the MJ stack.

3.5 Concentrated solar PV Concentrated photovoltaic (CPV) power lowers the cost of energy produced by using inexpensive concentrating optics which effectively reduces solar module area required to generate electricity. Current generated by solar cell under the concentrated light scales linearly with solar concentration factor, X. Since optical current increases linearly the open-circuit voltage, Voc, increases by the term ln(X), resulting in an overall increase in efficiency. However, conversion efficiency cannot increase indefinitely with increasing solar concentration due to few factors. These include a physical limit to open-circuit voltage being the built-in voltage of the cell, and increasing series resistance associated with increasing current. the advantage of CPVs is in the increased power density  Typically,  J$V Area

generated by the cell, rather than slight increase in the efficiency

due to the increase in Voc. The additional costs for concentrating optics or tracking systems are compensated by the lower module area per generated amount of power. Concentration systems between 300 and 1000 normally are based on the III-V materials, while low concentration PV plants (below 100) usually operate based on silicon solar cells [37]. Today’s record efficiency for solar cell under concentration is held by NREL at 47.1% for six-junction III-V based solar cell under 14 suns [16,19].

3.6 Nanotechnology in PV solar cells The prevalence of nanotechnology in PV solar cell applications has been increasing steadily in recent years. Scientists have looked into different modes of nanotechnology and how it can help increase efficiency of solar cells. The nanotechnology fields that are applied in PV solar cells range from nanoparticles use for luminescence purposes, surface texturing via nanoparticles depositions for light trapping in thin films, use of nanofluids to reduce negative thermal effects on solar panels, nanowires to affect optical absorptions, etc.

32

3. Basics of solar cells

Nanotechnology is mostly applied to thin-film solar cells (second generation solar cells compared to first generation bulk Si solar cells), in attempt to increase their conversion efficiency while retaining advantages of thin films, such as low-cost production and flexibility. Thin-film solar cells have a much thinner absorption layer, and this is a major reason of low conversion efficiency. It should be noted that for materials with high absorption coefficients, such as GaAs or Ge solar cells, the thin absorption layer is sufficient to generate the current needed and no significant loss is achieved. This is not the case for the material with lower absorption coefficients such as Si. In this case, nanoparticles can be applied such that they trap and scatter light, thus increasing the optical path. Another way is to use metal nanoparticles that exhibit plasmonic effect, where electrons at the boundary between dielectric and metal are excited by the incident light in a way to preserve and concentrate the light on the semiconductor absorber layer near the metal nanoparticle, thus effectively increasing the optical absorption and resulting conversion efficiency [38]. Furthermore, if nanoparticles are placed at the surface of the solar cells, they can cause light trapping by scattering, increasing optical path of incident light, thus effectively extending the thickness of the absorber layer, and increasing the efficiency [38]. Typically nanoparticles used in PV are gold, silver, and aluminum, due to their effective interaction with sunlight [39]. Due to the plasmonic effects of nanoparticles, the absorption in solar cells can be increased by 30% or even 70%, depending on the type and shape of nanoparticles used [39e41]. Another types of nanoparticles used to enhance efficiency of solar cells are luminescent nanoparticles, which are normally made of semiconductor materials. Such nanoparticles emit light once they are excited by incident photons, exhibiting so-called upshifting (emitting light at higher energy than incident photon) or downshifting (emitting light at lower energy than incident photon). By use of luminescent nanoparticles, solar cells’ absorption range can be shifted beyond its bandgap or absorption length, potentially utilizing more of the incident spectrum and thus increasing the conversion efficiency of the solar cells. Furthermore, in case of downshifting, high energy incident photons are absorbed by nanoparticles and lower energy photons are emitted and then reabsorbed by the absorber layer of solar cell. In downshifting process, thermalization losses typically associated with high energy incident photons are avoided or reduced, which results in a slight increase of solar cells efficiency. Besides thermalization losses associated with absorption of high energy photons, PV panels, especially in building integrated or in concentrated solar power, suffer from thermally induced efficiency reduction due to overheating of the panels. Temperature on the panels can reach as high as 80 C, significantly reducing conversion efficiency of the solar panels and their lifetime. While some materials, such as those from III-V

References

33

group, are more resilient to these thermal effects, they are costlier compared with a-Si based thin-film solar cells. Moreover, nanoparticles have been successfully used along with other methods to reduce thermally induced efficiency losses in building-integrated PV panels [42].

3.7 Summary In this chapter solar energy and physics of solar cell operation are reviewed. Solar power is an abundant energy source sufficient to meet increasing global energy demand. Currently, Si solar cells dominate PV solar market, while MJ solar cells achieve the highest efficiency. However, MJ solar cells are still too expensive to be broadly used and are limited to applications such as space. In order to increase solar cell efficiency, scientists are exploring many different ways, such as managing the light absorption and propagation inside solar cells, using concentrated solar power as well nanoparticles and nanofluids. While Si solar cells are approaching their theoretical efficiency limit, performance of thin-film solar cells can still be improved by novel methods, leading to further reduction of solar power costs.

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[33] K. Abade, F. Fonseca, R. Mansano, P.J. Abade, PECVD single-layer (SiN:H) and doublelayer (SiN:H/SiO2) ARC on mono and multicrystalline silicon solar cells, in: IEEE PVSC, 2000. [34] D.N. Wright, E.S. Marstein, A. Holt, Double layer anti-reflective coatings for silicon solar cells, in: 31st IEEE PVSC, 2005. [35] M. Neander, F. Gromball, D. Neumann, N. Harder, W.A. Nositschka, Anti-reflectivecoating tuned for higher solar module voltage, in: IEEE 4th World Conference on Photovoltaic Energy Conversion, 2006. [36] D. Bouhafsa, A. Moussia, A. Chikouchea, J. Ruizb, Design and simulation of antireflection coating systems for optoelectronic devices: application to silicon solar cells, Sol. Energy Mater. Sol. Cell. 52 (1e2) (March 1998) 79e93. [37] S. Philipps, A.W. Bett, K. Horowitz, S. Kurtz, Current Status of Concentrator Photovoltaics (CPV) Technology, 2016. Available at: www.ise.fraunhofer.de. [38] H.A. Atwater, A. Polman, Plasmonics for improved photovoltaic devices, Nat. Mater. 9 (2010). [39] H.M. Yassin, S.E. Mahran, Y.M. El-Batawy, J-V characteristics of plasmonic photovoltaics with embedded conical and cylindrical metallic nanoparticles, Int. J. Electron. Commun. 124 (2020) 153326. [40] A. Elrashidi, Optical absorption enhancement of a-si:H solar cells using plasmonic nanoparticles and nanoantennas, Mater. Today Proc. 4 (2017) S27eS35. [41] Y. Zhang, B. Cai, B. Jia, Ultraviolet plasmonic aluminium nanoparticles for highly efficient light incoupling on silicon solar cells, Nanomaterials 6 (2016) 6. [42] S.A. Nada, D.H. El-Nagar, H.M.S. Hussein, Improving the thermal regulation and efficiency enhancement of PCMIntegrated PV modules using nano particles, Energy Convers. Manag. 166 (2018) 735e743.

C H A P T E R

2 Motivation 2.1 Introduction The negative effects of climate change and global warming are no longer a futuristic issue to deal with. This is the result of the continued and extensive use of fossil fuels and subsequent greenhouse gas emissions such as CO2. The earth has been warming at an alarmingly fast pace the last 40 years due to greenhouse gas emission and the trapping of heat in the atmosphere. To slow down and eliminate this unnatural warming rate a reduction in greenhouse gas emissions is essential. This is accomplished by an increase in the deployment and use of clean renewable energy. Solar energy continues to play a significant role in the clean energy shift due to the abundance and unlimited supply of energy provided by the sun. The use of solar energy is on an exponential rise, thanks to recent government policies to reduce emissions. For example, Fig. 2.1 plots the solar energy production in the United Arab Emirates (UAE) from 2009 to 2019 showing an exponential rise starting in 2016 reaching almost 3500 GWh of production in 2019 [1]. The UAE is also home to the Mohammed Bin Rashid Al Maktoum solar park, the largest single site solar park in the world. This project will help reduce more than 6.5 million tons of emissions and will have capacity of 5000 MW [2]. Fig. 2.2 plots the solar energy generation in the United Sates showing an exponential rise starting with less than 20,000 GWh in the year 2010 to nearly 120,000 GWh today [3]. History was also made on May 4, 2022, when renewable energy powered California shy of 100% for the first time. More notable is that solar power provided two-thirds of the amount needed [4]. In addition to climate change, the limited reserves of fossil fuels will eventually make them unable to meet the needs of the ever-increasing

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2. Motivation

FIGURE 2.1 Solar energy generation in the United Arab Emirates from 2009 to 2019 [1].

FIGURE 2.2

Solar photovoltaic (PV) generation in the United States from 1990 to 2020 [3].

demand of energy [5]. Fig. 2.3 plots the world’s primary energy consumption as a function of time. Solar energy can be well situated to fill this energy need and gap given that it is easy to deploy, low cost, and has high efficiency. While the motivations are clear for solar cells, unsurprisingly economics plays a strong role in the decision-making. The challenge is the ability to improve photovoltaic device efficiency while maintaining or even reducing its cost. This is difficult as the semiconductor crystal properties used in modernday solar cells limit the amount of light that can be absorbed. Namely

2.2 Climate change and global warming

7

FIGURE 2.3 World primary energy consumption versus years [6].

the bandgap is a major fundamental bottle neck and provides a theoretical limit to efficiency of the solar cell. As a result, the nucleus of current and future solar research is finding new novel materials and designs that can overcome this barrier. SiliconeGermanium (Si1
xGex) alloys are one such material with a tunable bandgap to increase the amount of absorbed sunlight when bandgap is reduced. In addition, the Si1
xGex absorption coefficient increases as more Ge is added and hence the thickness of the solar cell can be reduced which will decrease the cost. One challenge of Si1
xGex is that the reduction of bandgap will also reduce open-circuit voltage (VOC) and efficiency. The physics of these parameters will be discussed in Chapter 3. As a result, there is a limit to the amount of Ge that can be alloyed to reach a peak efficiency for single-junction based solar cells. This is the main reason that Si1
xGex never replaced silicon for single-junction solar cells. This will be discussed further in detail in Chapter 5. As a result, the main use for Si1
xGex is as a bottom cell in a tandem cell since in this design the VOC reduction does not affect the overall efficiency. The Si1
xGex based tandem cells are currently the best performing solar cells in the market. Finally, in terms of fabrication and integration, Si1
xGex can be also used for lattice matching of various III-V materials due to tunable lattice constant.

2.2 Climate change and global warming The negative effects of greenhouse gas emissions are no longer a future effect but rather a current crisis. Increased CO2 emissions in the last 40 years are the main culprit for ongoing climate change [7]. These emissions have resulted in unnatural CO2 in the atmosphere, trapping heat and causing the Earth to warm. Currently the Earth is experiencing a drastic increase in floods, forest fires, hurricanes, and extreme heat waves that are

8

2. Motivation

attributed to warming of the atmosphere and climate change. Fig. 2.4 plots the CO2 in the atmosphere as a function of time [7]. This graph is based on the comparison of atmospheric samples contained in ancient ice cores and more recent direct measurements and provides evidence that atmospheric CO2 has increased dramatically since the Industrial Revolution compared to paleoclimatologic (past climate) measurements over the past 800,000 years. A dramatic increase since 1950 is seen, which correlates to the rapid warming of the atmosphere [7]. Unfortunately, human activities are the primary reason for climate change. Since the mid-20th century this has proceeded at an exponential rate [8]. Scientists have collected data about our planet and climate on a global scale for many years and this confirms the changing climate. In the mid-19th century, the heat-trapping nature of carbon dioxide and other gases was demonstrated and explained. There is no question that increased levels of greenhouse gases must be causing the Earth to warm in response and evidence is very clear. The data show that current warming is occurring roughly 10 times faster than the average, while carbon dioxide from human activity is increasing more than 250 times faster than it did from natural sources [9e13]. As a result, the planet’s average surface temperature has risen about 1.8 C since the late 19th century, a change driven largely by increased carbon dioxide emissions into the atmosphere and other human activities and mostly has occurred in the last 40 years [14]. The evidence of climate change and global warming are plenty. The ocean temperature has increased by more than 0.33 C (0.6 F) since 1969 [13]. The ice sheets in Greenland and Antarctic that have decreased in

FIGURE 2.4 Levels of CO2 in the atmosphere as a function of time [7].

2.2 Climate change and global warming

9

mass to glaciers are retreating almost everywhere around the world, releasing captured CO2, and further exacerbating the greenhouse effect [7]. Fig. 2.5A and B shows examples of climate change effects on ice and snow-caps around the world. In addition, a recent study showed the warming of the oceans has caused about 14% of the coral reefs to be lost since 2009 [15]. The study showed that the loss was mainly attributed to coral bleaching, which happens when corals, under stress from warmer water, expel the colorful algae living in their tissues, making them turn white [15]. Also, the amount of spring snow cover in the Northern Hemisphere has decreased over the past 5 decades and the snow is melting earlier in season. One other key sign is the global sea level. The rate of global sea level rising has increased in the past 2 decades, nearly double that of the last century and accelerating slightly every year. Global average sea level rose about 20 cm (8 in.) in the last century. The number of record high temperature events in the United States has been increasing, while the number of record low temperature events has been decreasing, since 1950. The United Sates has also seen an increasing number of intense rainfall events. Also, the acidity of surface ocean waters has increased by about 30% due to more carbon dioxide being released into the atmosphere and hence more being absorbed into the ocean. On February 28, 2022, the Intergovernmental Panel on Climate Change (IPCC) released its latest report, highlighting the causes, impacts, and possible solutions to climate change. Findings in the report show that climate breakdown is happening faster than expected and that the window to act is closing fast. The report is a call to governments and the private sector to take drastic action against climate change [16]. The UN

FIGURE 2.5 (A) Greenland ice melt. (B) The disappearing snowcap of Mount Kilimanjaro, from space [7].

10

2. Motivation

secretary-general, Anto´nio Guterres, said: “I have seen many scientific reports in my time, but nothing like this. This is code red for humanity. We must combine forces now to avert climate catastrophe” [17]. Despite all the warnings and clear evidence of the need to shift to renewable energy, the world is still not moving fast enough to solve this code red situation. It is worth noting that historically humans are slow in making major energy transitions. This is highlighted perfectly in a book by Dr. Vaclav Simil, Energy Transitions: Global and National Perspectives [18]. Fig. 2.6 shows the energy transition arc from coal, oil, and natural gas to modern renewables [18]. This plot is both worrying and exciting. Worrying about the slow progress and how the negative effects of climate change effects will continue, but exciting to be a researcher currently in the renewable energy field since many potential innovations will inevitably be discovered to meet this demand.

2.3 Solar energy and photovoltaics Sunlight that reaches the surface of the Earth provides unlimited, free, and clean energy to use and to generate power. In a single hour, the amount of power from the sun that hits the Earth is more than the entire world consumes in a year. To put that in numbers, from the US

FIGURE 2.6

Arc of energy history [18].

2.4 Why siliconegermanium in PV?

11

Department of Energy, each hour 430 quintillion Joules of energy from the sun hits the Earth. In comparison, the total amount of energy that all humans use in a year is 410 quintillion Joules. For context, the average American home used 39 billion Joules of electricity in 2013 [19]. As a result, solar energy is a very important clean and renewable energy source to help achieve the 1.5 C warming limit and eventually the net zero goal. However, the process of converting the solar energy to electricity is not 100% efficient due to limitations in the crystal properties of the semiconductor material used to make the solar cells. Solar cells are diodes (p-n junctions) that are designed to be able to separate the generated electronehole pairs. These individual cells are combined to make a full solar module. When light is absorbed in a solar cell, a voltage is induced, and this is called the photovoltaic effect. Researching new materials and structures is key in improving the performance of the solar cells. The research includes novel light trapping, tandem cells, or heterojunction solar cells, where materials with different optical properties are combined to absorb more of the solar spectrum. In addition, other efforts are being directed to make more efficient fabrications steps combined with lower material requirements. For example, thin-film solar cells are an attractive technique to lower the production cost, where less material is being used and they can be deposited on cheap substrates, such as ceramics, glass, flexible plastics, or stainless steel, depending on the application. More detail on the physics and principle of solar cells will be discussed in Chapter 3. The only negative environmental impact of solar cells is mostly during production stage, due to high energy consumption in clean rooms and use of harmful chemicals during processing. However, during an average solar panel lifetime of 25 years, pollution is very minimal, and it is limited to maintaining a clear surface or storing collected energy in batteries. This makes solar cells technology a very attractive way to convert the energy from the sun to the electricity.

2.4 Why siliconegermanium in PV? Finding new materials to improve Si solar cells is key to improving solar cell efficiency. Incorporating a semiconductor with a smaller
bandgap Eg increases the photocurrent since it allows absorption of photons with lower energy. This is an attractive way to increase the output current and efficiency of solar cells, especially in thin layers [20]. One such material with smaller bandgap is Si1
xGex. Ge is found mostly in zinc and lead ores, sometimes in silver and gold ores and in some kinds of coal. Most of the Ge comes as a by-product from other industries or from

12

2. Motivation

recycling of lasers and detectors, which makes it very attractive material in terms of sustainability. However, Si still dominates the semiconductor industry due to the ability to deposit high-quality insulators like SiO2. Even with the shift to higher dielectric permittivity-based gate oxides by Atomic Layer Deposition (ALD), Si continues to dominate due to legacy fabrication infrastructure and the high cost of the major change. Also, the abundance of Si and its excellent electrical and mechanical properties make the ideal material for various semiconductor devices. It is also common to alloy different semiconductor materials together to change the optical properties. For example, alloying Si with Ge can reduce the bandgap of the silicon making it useful for photon detection in the infrared regime. More information on Si1
xGex based photodetectors will be discussed in Chapter 9. Si1
xGex has some unique fabrication advantages compared to Sibased technology. One is the ability to grow Si1
xGex at much lower temperatures reducing the thermal budget and making integration of new materials more feasible. More detail on the growth advances is covered in Chapter 4. In addition the bandgap of Si1
xGex drops as the Ge content increases. Fig. 2.7 shows the bandgap of relax Si1
xGex as a function of x dropping from 1.1 to 0.66 eV. The drop as a function of x can be characterized by two regimes. With x less than 0.85 Si1
xGex behaves more like silicon but above 0.85 Si1
xGex is more Ge like. It should be noted that the bandgap change occurs mostly in the valence band which is important in terms of band alignment with heterojunctions and the conduction band offset. Table 2.1 highlights the key properties of mobility and bandgap of

FIGURE 2.7 Composition dependence of bandgap in GeeSi alloys at room temperature [21].

13

2.4 Why siliconegermanium in PV?

TABLE 2.1 Charge mobility and bandgap for intrinsic Si and relaxed Ge at 300 K. Silicon

Germanium

Electron mobility, mn (cm /v-sec)

1417

3900

Hole mobility, mp (cm /v-sec)

471

1900

Bandgap (eV)

1.12

0.68

2

2

both Si and relaxed Ge. The table clearly shows a higher mobility for Ge but a smaller bandgap as discussed previously. Fig. 2.8 shows the optical absorption coefficient of various materials in terms of infrared (IR) spectrum. As can be seen Ge is useful for IR optics applications [22]. Fig. 2.9 plots the optical absorption coefficients of Si, Ge, and undoped Si1
xGex alloys as function of x. The plot shows that Si and Ge are both optically conducting materials. However, the indirect bandgap of silicon limits its application in optoelectronics. As a result, Si is used almost

FIGURE 2.8

Optical absorption coefficients for various materials [23].

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2. Motivation

FIGURE 2.9 Optical absorption coefficients of Si, Ge, and undoped Si1
xGex alloys [25e27].

exclusively for electrical applications. Also, since the bandgap of silicon is 1.12 eV it absorbs light of shorter wavelengths, and this results in a limited generation of electronehole pairs by optical excitation. So compared to Ge, Si will generate less photocurrent in both photodetectors and solar cells. By combining Si and Ge the optical properties can be enhanced making the absorption more toward the infrared in alloys depending on the Ge fraction [22,24]. In addition to the optical absorption coefficients, Ge has very high refractive index with minimal dispersion, which makes it useful in construction of lenses, photodetectors, IR imaging, or optical fibers [28].

2.5 Summary In summary, the negative effects of climate change due to the exponential increase in CO2 emission to the atmosphere from the burning of fossil fuels is upon us. Extreme, dangerous, and costly weather events are on the exponential rise worldwide. A shift to clean and renewable energy sources will help to reduce these effects, limit warming, and help reach

References

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the future goal of net zero emissions. Solar energy and photovoltaics are a key piece to future renewable energy use and are already on the exponential rise, thanks to a strong shift in global governmental policies. In addition, due to the limited nature of fossil fuels, solar energy can help to bridge the gap. For the use of solar cells to continue to rise, the efficiency must continue to increase without increase in cost. This can be achieved by research into new materials such as Si1
xGex alloys. Si1
xGex is attractive for PV, due its smaller bandgap, higher absorption coefficient, and lattice matching potential in tandem cells.

References [1] I.E. Agency, Renewables Information, July 2021. Available at: https://www.iea.org/ data-and-statistics/data-product/renewables-information. [2] T. National, Road to Net Zero, May 09, 2019. Available at: https://www. thenationalnews.com/business/road-to-net-zero/2022/05/05/how-mohammed-binrashid-solar-park-plays-a-key-role-in-dubais-net-zero-strategy/. [3] I.E. Agency, Renewables Information: Overview, August 2021. Available at: https:// www.iea.org/countries/united-states. [4] J. Wilson, USA Today, May 2, 2022. Available at: https://www.usatoday.com/story/ news/nation/2022/05/02/california-renewable-energy-100/9612901002/. [5] S. Mohr, J. Wang, G. Ellem, J. Ward, D. Giurco, Projection of world fossil fuels by country, Fuel 141 (2015) 120e135. [6] BP, Statistical Review of World Energy, July 2021. Available at: https://www.bp.com/ en/global/corporate/energy-economics/statistical-review-of-world-energy.html. [7] NASA, Global Climate Change Vital Signs of the Planet, February 2022. Available at: https://climate.nasa.gov/evidence/. [8] B. Santer, et al., A search for human influences on the thermal structure of the atmosphere, Nature 382 (1996) 39e46. [9] B. Carey, Stanford Report, August 1, 2013, August 1, 2013. Available at: https://news. stanford.edu/news/2013/august/climate-change-speed-080113.html#:w:text¼Stanford%20climate%20scientists%20warn%20that,the%20past%2065%20million%20years. [10] O. Gaffney, W. Steffen, The Anthropocene equation, Anthr. Rev. 4 (1) (2017) 53e61. [11] I.B. Ocko, T. Sun, D. Shindell, M.O.A.N. Hristov, S.W. Pacala, D.L. Mauzerall, Y. Xu, S.P. Hamburg, Acting rapidly to deploy readily available methane mitigation measures by sector can immediately slow global warming, Environ. Res. Lett. 16 (5) (2021) 054042. [12] R.M. DeConto, D. Pollard, R.B. Alley, I. Velicogna, E. Gasson, N. Gomez, S. Sadai, A. Condron, D.M. Gilford, E.L. Ashe, R.E. Kopp, D. Li, A. Dutton, The Paris Climate Agreement and future sea-level rise from Antarctica, Nature 593 (2021) 83e89. [13] N.S. Diffenbaugh, C.B. Field, Changes in ecologically critical terrestrial climate conditions, Science 341 (6145) (2013) 486e492. [14] D. Herring, R. Lindsey, Global Warming Frequently Asked Questions, Climate.gov, June 3, 2021. Available at: https://www.climate.gov/news-features/understandingclimate/global-warming-frequently-asked-questions. [15] C. Garrison, Climate Change Is Killing the World’s Coral Reefs as Oceans Warm, Study Shows, October 5, 2021. Available at: https://www.reuters.com/business/ environment/climate-change-is-killing-worlds-coral-reefs-oceans-warm-study-202110-05/#:w:text¼The%20study%20by%20the%20Global,of%20Grand%20Canyon% 20National%20Park.

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[16] IPCC, IPCC Sixth Assessment Report, 2022. Available at: https://www.ipcc.ch/report/ ar6/wg2/. [17] A. Gawel, N. Cooper, L. Bester, ThePrint, March 13, 2022. Available at: https://theprint. in/world/code-red-for-humanity-3-3-billion-people-are-vulnerable-uns-climatechange-report-says/867520/. [18] V. Smil, Energy Transitions: Global and National Perspectives, Praeger, 2016. [19] R. Harrington, This Incredible Fact Should Get You Psyched about Solar Power, September 29, 2015. Available at: https://www.businessinsider.com/this-is-thepotential-of-solar-power-2015-9. [20] G. Beaucarne, F. Duerinckx, I. Kuzma, K.V. Nieuwenhuysen, H.J. Kim, J. Portmans, Epitaxial thin-film Si solar cells, Thin Solid Films 511e512 (July 2006) 533e542. [21] R. Braunstein, A.R. Moore, F. Herman, Instrinsic optical absoprtion of germaniumsilicon alloys, Phys. Rev. 109 (3) (1958) 695e710. [22] M. Fox, Optical Properties of Solids, Oxford University Press, 2001, pp. 2e7. [23] S.M. Sze, K.K. Ng, Physics of Semiconductor Devices, third ed., John Wiley & Sons, Inc, 2007. [24] C.K. Maiti, G.A. Armstrong, Applications of SiGe Heterostructure Devices, Institute of Physics Publishing, London, 2001. [25] E. Kasper, Properties of Strained and Relaxed SiGe, Institution of Electrical Engineers, London, 1995. [26] S. Smilab, "n-k Database," Available at: http://www.sopra-sa.com/. [27] S.A. Hadi, P. Hashemi, N. DiLello, E. Polyzoeva, A. Nayfeh, J.L.H.M.2 Pages, Thin-film Si1
xGex HIT solar cells, Sol. Energy 103 (2014) 154e159. [28] M. Bosi, G. Attolini, Germanium: epitaxy and its applications, Prog. Cryst. Growth Char. Mater. 56 (3e4) (2010) 146e174.

C H A P T E R

1 About the book New material systems and discoveries are needed to help improve photovoltaic conversion efficiency and cost-effectiveness. These discoveries will be the key enabler in allowing for aggressive use of photovoltaic technologies beyond 2022 and into the next decades. With a global push to curb the negative effects of climate change in full force, the formation of the Paris climate accords in April of 2016, the recent net zero goal from 2021 United Nations Climate Change Conference (COP26), and with many governments changing to a green centric economy, solar energy is most likely the main solution for clean sustainable renewable energy of the future [1e3]. This makes the research into new materials for solar energy even more critical. More specifically the vital question is how these new novel materials interact with each other, and how their material properties will affect photovoltaic performance. New material research and development has become the nucleus and driving force of the PV challenge to improve efficiency without increasing cost significantly. This book looks comprehensively at the crystalline silicon-germanium alloys (Si1-xGex) in photovoltaics. c-Si1-xGex photovoltaics has been a key material for high-performance transistors and photodetectors but it turns out c-Si1-xGex has a lot to offer for photovoltaics. This book will cover all the potential uses of c-Si1-xGex in photovoltaics. It will cover topics from deposition methods; optical, electrical, and material properties; single junction Si1-xGex solar cells; TCAD simulation and detailed balance modeling; III-V integration; and a detailed cost analysis. It should be noted, a large percentage of research highlighted in this book is conducted by authors, Professor Ammar Nayfeh and Professor Sabina Abdul Hadi while at Khalifa University. Some of the work was done in collaboration with Professor Judy Hoyt and Professor Eugene Fitzgerald of Massachusetts Institute of Technology (MIT). In addition, the earlier work on the Ge on Si growth was guided by Professor Krishna Saraswat of Stanford University in collaboration with Professor Nayfeh. Fig. 1.1 shows a demonstration of III-V on Si step cell that was developed using c-Si1-xGex technology.

Silicon-Germanium Alloys for Photovoltaic Applications https://doi.org/10.1016/B978-0-323-85630-0.00002-9

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© 2023 Elsevier Inc. All rights reserved.

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1. About the book

FIGURE 1.1 “Step cell” developed by authors Abdul Hadi and Nayfeh.

All the research done was funded by Khalifa University and United Arab Emirates (UAE) University government in line with their 2050 vision: In 2017, the UAE launched ‘Energy Strategy 2050’, which is considered the first unified energy strategy in the country that is based on supply and demand. The strategy aims to increase the contribution of clean energy in the total energy mix from 25% to 50% by 2050 and reduce carbon footprint of power generation by 70%, thus saving AED 700 billion by 2050. It also seeks to increase consumption efficiency of individuals and corporates by 40% [4].

The book is geared toward graduate students and researchers (both in academia and industry) working on materials in photovoltaics. It includes a summary of c-Si1-xGex material properties relevant for solar research. Also, different simulation models and analysis of c-Si1-xGex material properties on solar cell performance are discussed. Finally, the cost analysis for III-V/Si solar cells via c-Si1-xGex alloys will be useful for companies and future PV planning. The book can be used as MSc or Ph.D. level class textbook. It should be noted that although the book focus is photovoltaics, there is a plethora of useful information for c-Si1-xGex in electronics and photonics.

1.1 Book overview The book is divided into nine chapters including the current Chapter 1 (about the book). Chapter 2 covers the motivation for solar energy in the context of climate change. It will give a holistic look on the issues associated with

1.1 Book overview

3

climate change and greenhouse gas effect with the role solar energy can be used to solve these issues. The motivation for new material innovations to increase the efficiency without increasing cost is discussed. Finally, the potential applications of c-Si1-xGex in the future of photovoltaics will be introduced. Chapter 3 reviews basics of solar cells physics and provides an overview of solar cell concepts, sufficient to prepare the reader for topics of the following chapters. It covers the basic key parameters of solar cell while introducing some basic physics of operations from an electrical, photonic, and material perspective. Chapter 4 highlights c-Si1-xGex deposition methods over the years, focusing on the optical and material properties. This chapter emphasizes the challenges associated with the growth due to lattice mismatch, while differentiating between various growth modes and deposition tools. A historical look at the key research and growth innovations of c-Si1-xGex deposition over years are discussed. Chapter 5 provides a history of c-Si1-xGex solar cells fabrication and demonstration. An overview of key research results to date with an emphasis on c-Si1-xGex heterojunction with intrinsic thin layer (HIT) solar cells. Chapter 6 discusses work on growth of lattice matched III-V on Si via Si1-xGex buffer. Experimental results of actual III-V cells fabricated via Si1-xGex technology are presented here. Chapter 7 details the modeling and simulations of Si1-xGex bufferbased solar cells, including multi-junction III-V/Si solar cells. Simulation results include theoretical analysis of dual and multi-junction using detailed balance method, with a look into effect of step-cell design on multi-junction performance and optimum bandgap combinations. Furthermore, simulation results using TCAD by Synopsis are presented for different Si1-xGex cells and III-V/Si dual junction cell, including various analyses of those structures, such as effect of antireflective coasting design for III-V/Si cells, effect of Si1-xGex graded buffer on bottom Si cell, or effect of step-cell design, among others. Chapter 8 provides an overview of solar cell cost analysis and goes into the cost benefits of using Si1-xGex graded buffers instead of Ge for III-V based multi-junction solar cells. A process flow using step cell is used for the cost analysis, as one of the proposed cost-effective ways for mass production of III-V layers on Si substrates via Si1-xGex graded buffers. Sensitivity analysis with different scenarios is carried out with comparison to costs of standard III-V growth on Ge substrates. Chapter 9 highlights notable applications of Si1-xGex other than PV. Different applications of Si1-xGex are summarized, including its use in CMOS, optics, III-V integration, or nanotechnology. This chapter does not

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1. About the book

go into depth of mentioned subjects, but it provides great starting point for a reader for further explorations of Si1-xGex applications.

References [1] N. Glanemann, S. Willner, A. Levermann, Paris climate agreement passes the costbenefit test, Nat. Commun. 11 (2020) 110. [2] United Nations in Western Europe, 2021. [Online]. Available: https://unric.org/en/ cop26-a-snapshot-of-the-agreement/. [3] The National Academies of Science Engineering Medicine, 2022. [Online]. Available: https://www.nap.edu/resource/other/dels/net-zero-emissions-by-2050/?gclid¼Cj0KCQiAqbyNBhC2ARIsALDwAsC-Mpm4Vx6dmKZXzzKG9S41YZikhG2glBdJ4luvkLiuzO2 Oy8SolkEaAjPHEALw_wcB#page-top. [4] Efforts towards sustainability. https://u.ae/en/information-and-services/environ ment-and-energy/water-and-energy/efforts-towards-sustainability, 2021.

Index ‘Note: Page numbers followed by “f” indicate figures and “t” indicate tables.’

A Antireflecting coating (ARC), 55e56 Antireflective (AR), 75e76

B Bandgap versus lattice constant, 38f Bonded III-V//Si dual-junction solar cells, 135e144 DJ III-V/Si solar cell, detailed balance efficiency limit for, 135e139, 136fe139f GaAs1-yPy/Si DJ solar cell, optimizing antireflective coating for, 139e144, 140f, 142fe144f Bottom Si cell, Si1-xGex graded buffer, 126e129 simulation model, 127e128, 128f simulation results, 129, 129f

C Chemical vapor deposition (CVD), 44e45 Climate change, 7e10 Complex refractive indices, 58 Compositionally graded SiGe base, 74f ComputeFromSpectrum, 105 Concentrated photovoltaic (CPV) power, 31 Conversion efficiency, 26e27, 26f Cost analysis, cost model, 162e168, 163t cell manufacturing costs, 164e166, 165t cost analysis results, 168e175, 169f installed PV costs, 166e168, 167t long-term scenario, 173e175, 174f midterm scenario assumption, 172, 172f reference scenario, 170e171, 170fe171f c-Si1-xGex solar cells compositionally graded SiGe base, 74f exfoliated Ge foil, 69f external quantum efficiency (EQE), 68, 75f, 78 fill factor (FF), 76t Front Surface Field (FSF), 72

199

heterojunction emitter based solar cell (HIT), 72e78, 73f indium tin oxide (ITO), 75e76 internal quantum efficiency (IQE), 66, 67f Photovoltaics Specialist Conference (PVSC), 64e65 research history of, 64 solar cells, 77t thin-film heterojunction solar cell, 68 transmission electron microscopy (TEM), 66f, 80f Currentevoltage characteristics, 19e27, 20fe21f, 23f

D Deposition techniques, 44e47, 45fe46f Dual-junction (DJ) solar cell, 85

E Electron and hole mobilities, 183 Epitaxial germanium, 46 Exfoliated Ge foil, 69f External quantum efficiencies (EQEs), 68, 75f, 78, 92e95, 123

F Fabricated solar cell structure, 69 Fill factor (FF), 24e25, 72, 76t Finite-difference time domain (FDTD) method, 105 Frank Van der Merwe (FVM), 40 Front Surface Field (FSF), 72

G GaAs0.71P0.29/Si dual-junction step-cell, 130e135 monolithic and bonded GaAs0.71P0.29/Si step-cell, 132e135, 133fe134f monolithic and bonded structures, 130e135 simulation model, 131e132 GaAs0.76P0.24/Si1-xGex/Si single-junction solar cells, 120e126, 120f simulation model, 121e122, 122f

200 GaAs0.76P0.24/Si1-xGex/Si single-junction solar cells (Continued) simulation results, 122e125, 122t, 123fe124f GaAs1-yPy, optical and electrical properties of, 90, 90f Germanium compared to silicon, lattice mobility enhancement of, 182t, 183fe184f Global warming, 7e10 Graphic user interface (GUI), 103e104 Greenhouse effect, 8e9

H Heteroepitaxial germanium layers, 46 Heterojunction emitter based solar cell (HIT), 72e78, 73f High-resolution cross-sectional transmission electron microscopy (XTEM), 185 HRSEM cross-sectional images, 51e53 HRTEM, 188e190 Hydrogen, 53e55

I Indium tin oxide (ITO), 75e76 Infrared photodetection, SiGe for, 187e188, 187f InGaP lifetime, 123 Installed PV costs, 166e168, 167t Integrated Chip (IC), 17 Intergovernmental Panel on Climate Change (IPCC), 9e10 Internal quantum efficiency (IQE), 66, 67f, 121

K Khalifa University, 2

L Lattice matched IIIeV materials bandgap, 91f dual-junction (DJ) solar cell, 85 electrical properties of, 91t GaAs1-yPy, optical and electrical properties of, 90, 90f lattice mismatch and threading dislocation density, 88e89, 89f MOCVD, 90f Ohio State University (OSU), 86 Si MJ solar cells, Si1-xGex buffer in literature, 91e99

Index

GaAs0.76P0.24 single-junction solar cell, 95e97, 96fe97f InGaP/GaAs, 92e93, 92f Si solar cells, GaAs0.84P0.16/Si0.18Ge0.82 on, 93e95, 94f Si tandem cells, III-V on, 97e99, 98f threading dislocation defects (TDD), 95 Lattice mismatch and threading dislocation density, 88e89, 89f Levelized cost of electricity (LCOE), 151f Long-term scenario, 173e175, 174f Low-Pressure Chemical Vapor Deposition (LPCVD) reactor, 49e50 Low temperature oxide (LTO), 44e45

M Massachusetts Institute of Technology (MIT), 90 Meshing, 107 Metal-organic vapor phase epitaxy (MOCVD), 90f, 95, 98 Metalesemiconductoremetal (MSM) device, 188 Metalesemiconductoremetal (MSM) photodetectors, 49 Midterm scenario assumption, 172, 172f Misfit dislocations, 39 Molecular Beam Epitaxy (MBE), 47e48 Motivation climate change, 7e10 global warming, 7e10 greenhouse effect, 8e9 Intergovernmental Panel on Climate Change (IPCC), 9e10 open-circuit voltage (VOC), 6e7 photovoltaics, 10e11 renewable energy, 5 SiliconeGermanium (Si1-xGex) alloys, 6e7, 11e14, 12fe13f, 13t, 14f solar cells, 11 solar energy, 6e7, 10e11 United Arab Emirates (UAE), 5 solar energy generation in, 6f United States solar photovoltaic (PV) generation in, 6f Multi-junction solar cell operation, 27e29, 28f Multi-junction (MJ) solar cells, 85 cost considerations, 153e162, 156f III-V/Si DJ step-cell fabrication process flow, 157f, 160e162, 160f

Index

III-V/Si dual-junction step-cell, 157e160, 157fe159f Multiple hydrogen annealing for heteroepitaxy (MHAH), 48e49

N

n+ a-Si/i a-Si/i c-Si/p c-Si1-xGex/c-Si HIT cell, 114e119, 116fe119f

O Ohio State University (OSU), 86 Open-circuit voltage (VOC), 6e7, 24 Optical absorption, 132 Optical properties, 56e58, 57fe59f

P Photovoltaic (PV) effect, 10e11, 17 siliconegermanium, 11e14, 12fe13f, 13t, 14f Photovoltaics Specialist Conference (PVSC), 64e65 Physical vapor deposition (PVD), 45 Plasma-enhanced chemical vapor deposition (PECVD), 75e76

Q Quantum dots (QDs), 184 Quantum Yield, 106

R Radiofrequency plasma-enhanced chemical vapor deposition (RF-PECVD), 51e53 Reference scenario, 170e171, 170fe171f Refractive index, 58 Renewable energy (RE), 5, 149, 150f

S Scanning Electron Microscope images, 55e56 Sdevice command files, 104e105 Semiconductor material, 183 Sentaurus Structure Editor (SDE), 103e104 Sentaurus Workbench (SWB), 103e104 Shockley Read Hall (SRH) Scharfetter recombination model, 105 Short circuit current, 24 a-Si/c-Si1-xGex heterojunction solar cell, 111e114, 111fe114f III-V/Si DJ step-cell fabrication process flow, 157f, 160e162, 160f

201

III-V/Si dual-junction step-cell, 157e160, 157fe159f SiGe nanotechnology, 192e193, 192fe196f template, IIIeV integration using, 188e192, 188fe191f SiliconeGermanium alloys (Si1-xGex), 1, 6e7 Bandgap versus lattice constant, 38f challenge, 37e39 complex refractive indices, 58 deposition techniques, 44e47, 45fe46f growth methods, 40e43, 41fe44f growth solutions, 47e56, 49fe54f, 56f optical properties, 56e58, 57fe59f transmission electron microscopy (TEM), 39, 39f Si MJ solar cells, Si1-xGex buffer in literature, 91e99 GaAs0.76P0.24 single-junction solar cell, 95e97, 96fe97f InGaP/GaAs, 92e93, 92f Si solar cells, GaAs0.84P0.16/Si0.18Ge0.82 on, 93e95, 94f Si tandem cells, III-V on, 97e99, 98f Si1-xGex applications of germanium compared to silicon, lattice mobility enhancement of, 182t, 183fe184f transistor technology, 185e186, 185fe186f infrared photodetection, SiGe for, 187e188, 187f SiGe nanotechnology, 192e193, 192fe196f template, IIIeV integration using, 188e192, 188fe191f single-junction cells, 107e120 Solar cells, 11, 77t concentrated photovoltaic (CPV) power, 31 design considerations, 29e30 Integrated Chip (IC), 17 operation, 19e27 photovoltaic (PV) effect solar cells, 17, 19e30 light management for, 30e31 nanotechnology in, 31e33 solar energy, 18, 19f solar power generation, 19e30 conversion efficiency, 26e27, 26f

202

Index

Solar cells (Continued) currentevoltage characteristics, 19e27, 20fe21f, 23f fill factor, 24e25 multi-junction solar cell operation, 27e29, 28f open circuit voltage, 24 short circuit current, 24 solar cell design considerations, 29e30 solar cell operation, 19e27 Solar energy, 6e7, 10e11 Solar power generation conversion efficiency, 26e27, 26f currentevoltage characteristics, 19e27, 20fe21f, 23f fill factor, 24e25 multi-junction solar cell operation, 27e29, 28f open circuit voltage, 24 short circuit current, 24 solar cell design considerations, 29e30 solar cell operation, 19e27 Solar PV cost considerations levelized cost of electricity (LCOE), 151f renewable energy (RE), 149, 150f StanskieKrastanov (SK) growth, 40 Step cell, 2f StranskieKrastanov (SK) growth, 41e42 Surface recombination values, 110t

T Tabulated values from perimeter file (TableODB), 106 Technology Computer Aided Design (TCAD) software bonded III-V//Si dual-junction solar cells, 135e144 DJ III-V/Si solar cell, detailed balance efficiency limit for, 135e139, 136fe139f GaAs1-yPy/Si DJ solar cell, optimizing antireflective coating for, 139e144, 140f, 142fe144f bottom Si cell, Si1-xGex graded buffer on, 126e129

simulation model, 127e128, 128f simulation results, 129, 129f challenges, 106e107 GaAs0.71P0.29/Si dual-junction step-cell, 130e135 monolithic and bonded GaAs0.71P0.29/ Si step-cell, 132e135, 133fe134f monolithic and bonded structures, 130e135 simulation model, 131e132 GaAs0.76P0.24/Si1-xGex/Si single-junction solar cells, 120e126, 120f simulation model, 121e122, 122f simulation results, 122e125, 122t, 123fe124f n+ a-Si/i a-Si/i c-Si/p c-Si1-xGex/c-Si HIT cell, 114e119, 116fe119f optics section, 105e106 overview of, 103e107 parameters, 106, 110t physics section, 104e105 a-Si/c-Si1-xGex heterojunction solar cell, 111e114, 111fe114f Si1exGex single-junction cells, 107e120 surface recombination values, 110t uncertainties, 106e107 Thin-film heterojunction solar cell, 68 Threading dislocation density (TDD), 88, 95 Transfer matrix method (TMM), 105 Transmission electron microscopy (TEM), 39, 39f, 55e56, 66f, 80f

U Uncertainties, 106e107 United Arab Emirates (UAE), 2, 5 solar energy generation in, 6f

V VolmereWeber growth (VW), 40

X X-ray diffraction, 55e56, 188e190