Power Trade-offs and Low Power in Analog CMOS ICs [1 ed.] 0792376420, 9780792376422, 9780306481406

Citation preview

POWER TRADE-OFFS AND LOW-POWER IN ANALOG CMOS ICs

THE KLUWER INTERNATIONAL SERIES IN ENGINEERING AND COMPUTER SCIENCE

ANALOG CIRCUITS AND SIGNAL PROCESSING Consulting Editor: Mohammed Ismail. Ohio State University Related Titles: POWER TRADE-OFFS AND LOW POWER IN ANALOG CMOS ICS M. Sanduleanu, van Tuijl ISBN: 0-7923-7643-9 RF CMOS POWER AMPLIFIERS: THEORY, DESIGN AND IMPLEMENTATION M.Hella, M.Ismail ISBN: 0-7923-7628-5 WIRELESS BUILDING BLOCKS J.Janssens, M. Steyaert ISBN: 0-7923-7637-4 CODING APPROACHES TO FAULT TOLERANCE IN COMBINATION AND DYNAMIC SYSTEMS C. Hadjicostis ISBN: 0-7923-7624-2 DATA CONVERTERS FOR WIRELESS STANDARDS C. Shi, M. Ismail ISBN: 0-7923-7623-4 STREAM PROCESSOR ARCHITECTURE S. Rixner ISBN: 0-7923-7545-9 LOGIC SYNTHESIS AND VERIFICATION S. Hassoun, T. Sasao ISBN: 0-7923-7606-4 VERILOG-2001-A GUIDE TO THE NEW FEATURES OF THE VERILOG HARDWARE DESCRIPTION LANGUAGE S. Sutherland ISBN: 0-7923-7568-8 IMAGE COMPRESSION FUNDAMENTALS, STANDARDS AND PRACTICE D. Taubman, M. Marcellin ISBN: 0-7923-7519-X ERROR CODING FOR ENGINEERS A.Houghton ISBN: 0-7923-7522-X MODELING AND SIMULATION ENVIRONMENT FOR SATELLITE AND TERRESTRIAL COMMUNICATION NETWORKS A.Ince ISBN: 0-7923-7547-5 MULT-FRAME MOTION-COMPENSATED PREDICTION FOR VIDEO TRANSMISSION T. Wiegand, B. Girod ISBN: 0-7923-7497- 5 SUPER - RESOLUTION IMAGING S. Chaudhuri ISBN: 0-7923-7471-1 AUTOMATIC CALIBRATION OF MODULATED FREQUENCY SYNTHESIZERS D. McMahill ISBN: 0-7923-7589-0 MODEL ENGINEERING IN MIXED-SIGNAL CIRCUIT DESIGN S. Huss ISBN: 0-7923-7598-X CONTINUOUS-TIME SIGMA-DELTA MODULATION FOR A/D CONVERSION IN RADIO RECEIVERS L. Breems, J.H. Huijsing ISBN: 0-7923-7492-4

POWER TRADE-OFFS AND LOW-POWER IN ANALOG CMOS ICs by

Mihai A.T. Sanduleanu Philips Research, Eindhoven, The Netherlands and

Ed A.J.M. van Tuijl Philips Research, Eindhoven, The Netherlands

KLUWER ACADEMIC PUBLISHERS NEW YORK, BOSTON, DORDRECHT, LONDON, MOSCOW

eBook ISBN: Print ISBN:

0-306-48140-5 0-7923-7642-0

©2003 Kluwer Academic Publishers New York, Boston, Dordrecht, London, Moscow Print ©2002 Kluwer Academic Publishers Dordrecht All rights reserved

No part of this eBook may be reproduced or transmitted in any form or by any means, electronic mechanical, recording, or otherwise, without written consent from the Publisher

Created in the United States of America

Visit Kluwer Online at: and Kluwer's eBookstore at:

http://kluweronline.com http://ebooks.kluweronline.com

v

Contents List of figures

ix

List of tables

xiii

Selected Symbols and Abbreviations

xv

Foreword

xvii

Acknowledgements

xix

1. Introduction

1

1.1 Motivation

1

1.2 Problem definition

2

1.3 Scope and outline

3

References

8

2. Power considerations in sub-micron digital CMOS

9

2.1 Introduction

9

2.2 Fundamental limits

10

2.3 From fundamental limits to practical limits of power. An architecture level approach

12

2.4 S/N ratio and power in fixed point applications

18

2.5 Adders and computational power

19

2.6 Ways to low-power in digital

23

2.7 Example of a digital video filter

25

2.8 Conclusions

28

References

29

3. Power considerations in sub-micron analog CMOS

31

3.1 Introduction

31

3.2 Process tuning towards digital needs. Consequences on analog 32

vi 3.3 Fundamental limits

36

3.4 From fundamental limits to practical limits of power. Noise related power

38

3.5 From fundamental limits to practical limits of power. Mismatch related power

56

3.6 Power estimations in continuous time filters

60

3.7 Conclusions

66

References

67

4. Gm-C integrators for low-power and low voltage applications. A

gaussian polyphase filter for mobile transceivers in 0.35

CMOS 69

4.1 Introduction

69

4.2 Large swing and high linearity transconductor

69

4.3 Low voltage current Gm-C integrator with high power efficiency 78

4.4 Low-power luminance video filter. Noise driven power

83

4.5 Low-power, gaussian, polyphase filter for mobile transceivers. Matching driven power

87

4.6 Conclusions

97

References

99

5. Chopping: a technique for noise and offset reduction

101

5.1 Introduction

101

5.2 Ways to reduce offset and 1/f noise

102

5.3 Chopping seen as a modulation technique

105

5.4 Noise modulation

106

5.5 Chopped amplifiers and offset reduction

108

5.6 Low-power low-voltage chopped transconductance amplifier for noise and offset reduction. Chopping at high frequency

109

5.7 A low-power bandgap voltage reference

119

vii 5.8 Conclusions

124

References

125

6. Low-noise, low residual offset, chopped amplifiers for high-end

applications

127

6.1 Introduction

127

6.2 Low-pass filtering in a digital audio system. Application specific constraints

128

6.3 The gain stage

130

6.4 A low noise, low residual offset, chopped amplifier in 0.8mm CMOS

132

6.5 A low noise, low residual offset, chopped amplifier in 0.5mm CMOS

142

6.6 Conclusions

150

References

152

7. A 16-bit D/A interface with Sinc approximated semidigital

reconstruction filter

153

7.1 Introduction

153

7.2 Bitstream D/A conversion system with time-discrete filtering 154 7.3 S-D modulators and noise shaping

155

7.4. Semidigital FIR filter principles

158

7.5. Semidigital FIR filter design

160

7.6 Noise properties of the D/A interface

168

7.7 Realisation

176

7.8 Experimental results

180

7.9 Interpolative D/A converter with Sinc approximation in the time domain

181

7.10. Conclusions

184

References

186

viii 8. Conclusions

187

8.1 Summary

187

8.2 Conclusions

189

8.3 Original contributions

192

8.4 Recommendations for further research

193

APPENDIX 1

195

APPENDIX 2

199

APPENDIX 3

203

INDEX

207

ix

List of Figures

2.1: 2.2: 2.3: 2.4: 2.5: 2.6: 2.7: 2.8: 2.9: 2.10: 2.11: 2.12: 2.13: 2.14: 2.15: 3.1: 3.2: 3.3: 3.4: 3.5: 3.6: 3.7: 3.8: 3.9: 3.10: 3.11: 3.12: 3.13: 3.14: 3.15: 3.16: 3.17: 3.18: 4.1: 4.2: 4.3: 4.4: 4.5: 4.6: 4.7: 4.8: 4.9: 4.10: 4.11:

The levels of abstraction for power considerations Thermodynamic limit Fundamental limits of power in digital Energy as a function of S/N for a generic DSP FIR digital filter IIR digital filter (direct form 1) IIR digital filter (direct form 2) Circuit diagram of a full adder FA RCA m bits adder Cascade RCA for adding m words of B bits Chain (a) vs. tree (b) implementation of adders The delay of a simple inverter The LP prototype after scaling Multiplication by hardwiring Example of a FIR digital video filter Output resistance and the drain current in processes Matching in for processes Analog processor Fundamental power limits as a function of S/N Power spectral densities of the thermal noise Voltage amplifier with feedback Voltage amplifier with differential stage and feedback OTA with active load Feedback amplifier with OTA Current amplifier Frequency transfer of the current amplifier Charge summing amplifier with S/H Switched capacitor amplifier Circuit for settling time computation SI memory cell SI non-inverting amplifier (damped integrator) State space representation of a filter Transconductors with degeneration resistors Gm core diagram Gm fine tuning Gm coarse tuning for different aspect ratios of MN12(13) THD for Gm_TUNE=0 THD for Gm_TUNE=3V Frequency response of the integrator The noise excess factor of the transconductor Circuit diagram of the transconductor Continuous time, current, Gm-C integrator Frequency transfer of the integrator Linearized integrator

9 11 12 15 15 16 17 19 20 21 22 25 26 26 27 33 34 36 37 38 41 43 44 45 46 47 49 50 52 53 54 60 63 70 72 72 73 74 75 75 77 78 79 82

x 4.12: 4.13: 4.14: 4.15: 4.16: 4.17: 4.18: 4.19: 4.20: 4.21: 4.22: 4.23: 4.24: 4.25: 4.26: 4.27: 5.1: 5.2: 5.3: 5.4: 5.5: 5.6: 5.7: 5.8: 5.9: 5.10: 5.11: 5.12: 5.13: 5.14: 5.15: 5.16: 5.17: 5.18: 5.19: 6.1: 6.2: 6.3: 6.4: 6.5: 6.6: 6.7: 6.8: 6.9: 6.10: 6.11: 6.12: 6.13: 6.14: 6.15:

The frequency transfer of the video filter The Norton transformation The SFG of the filter Realization with current Gm-C integrators Realization with OTA-C integrators Low IF receiver topology Low IF downconversion Polyphase lowpass to bandpass transformation The SFG of the polyphase filter Block diagram of the polyphase filter Gain and phase mismatch in polyphase signals Tunable polyphase transfer Negative frequency crosstalk Polyphase differential integrator with source degeneration Negative frequency crosstalk (source degeneration) The noise power of the filter for different scaling factors The autozero technique Noise sampling in autozero amplifiers Noise transfer functions Chopper modulation PSD of 1/f noise after chopper modulation The chopper technique The baseband spectrum Conventional choppers The basic principle Circuit diagram DR and offset as a function of bias current Static and residual offset SINAD at 93KHz chopper frequency Chip photomicrograph Charge injection at the output Charge injection in the input modulator Basic bandgap reference Bandgap voltage reference with chopped amplifier The open loop gain of the opamp The output filters of a bitstream D/A converter The output spectrum of the FIR filter (LPD) Chopped amplifer for low-pass filtering The gain stage of the opamp Differential to single ended converters The output stage with class AB control The class AB control circuit The class AB currents in the output transistors The circuit principle The frequency transfer of the opamp The circuit diagram Noise measurement setup The output spectrum of the opamp Static and residual offset measurement setup Residual offset vs. chopper frequency

84 85 85 86 87 88 89 90 91 91 92 94 94 95 96 97 102 103 104 105 107 108 109 110 111 112 114 115 115 117 118 119 120 122 123 128 129 130 130 131 132 133 134 135 135 136 137 138 138 139

xi 6.16: 6.17: 6.18: 6.19: 6.20: 6.21: 6.22: 6.23: 6.24: 6.25: 6.26: 6.26: 6.27: 7.1: 7.2: 7.3: 7.4: 7.5: 7.6: 7.7: 7.8: 7.9: 7.10: 7.11: 7.12: 7.13: 7.14: 7.15: 7.16: 7.17: 7.18: 7.19: 7.20: 7.21: 7.22: 7.23: 7.24: 7.25: 7.26: 7.27: 7.28: 7.29: 7.30: A1.1: A2.1: A.3.1: A.3.2: A.3.3: A.3.4:

Static and residual offset measurement setup Distortion measurement setup THD vs. output amplitude THD vs. output frequency Chip photomicrograph Class AB output stage The simulated class AB currents in the output transistors The circuit diagram The simulated frequency transfer Transient response Spectral density of the input noise THD vs. amplitude THD vs. frequency Bitstream D/A conversion system Noise model for the one bit quantizer Noise density modulator Noise transfer of the modulator Basic principles Basic principles Sinc approximation method (N=29) Sinc approximation method (N=89) Sinc approximation method (N=27) Noise transfer for N=25 Signal transfer in the audio-band for N=27 Windowing techniques Matching of coefficients Noise transfer Noise generated at the output NRZ coding RZ coding and jitter Circuit diagram The floating current source The opamp used for LPA filtering The open loop gain of the opamp Class A chopped opamp The open loop gain of the class A chopped opamp Low-power D flip-flop for shift registers Chip photomicrograph S/N+THD measurement at 1KHz FS Signal reconstruction Sine approximation Interpolative D/A converter FIR DSP with noise sources The LP prototype after scaling Ideal gaussian transfer and the group delay Attenuation performance of gaussian approximations Gaussian, gaussian-to-6dB and gaussian-to-12dB transfer Group delay and step response of gaussian-to-6(12) dB

139 140 140 141 142 143 144 146 147 148 148 149 149 154 156 156 156 158 158 159 161 162 163 163 164 164 166 168 169 173 174 176 177 177 178 178 179 179 180 181 182 183 183 195 201 204 204 205 205

This page intentionally left blank

xiii

List of Tables

2.1: 2.2: 2.3: 2.4: 3.1: 3.2: 3.3: 4.1: 4.2: 4.3: 4.4: 4.5: 4.6: 5.1: 6.1: 6.2: 7.1: 7.2: A2.1:

Operations per cycle for different multipliers Video filter specifications Coefficients in real format and CSD format Energy per transition of a full adder in CMOS SIA roadmap trajectory for modern processes Thermal noise conductance of a MOST Noise vs. accuracy Video filter spec’s The dimensions of integrator sections Power consumption of the current Gm-C realization Dimensions and power estimations for the OTA-C approach Receiver specifications for different standards The dimensions of the polyphase sections Performance summary Summary of performance Summary of performance Coefficients of the FIR filter Summary of performance Video filter specifications

14 25 26 27 32 39 59 84 85 86 86 89 93 116 141 150 162 181 199

This page intentionally left blank

xv

Selected Symbols and Abbreviations Symbol DVD GPS PCS PDA DR

S/N DECT OTA D/A Sinc BER DSP ECL CML FIR IIR RCA CS CLA

CSA CSD S/H

BW

G GBW WI SI

NEF

Meaning Digital Video Disk Global Positioning System Personal Communication System Personal Digital Assistant Dynamic Range Signal to Noise Ratio Digital Enhanced Cordless Telecommunications standard Operational Transconductance Amplifier Digital to Analog Converter sin(x)/x function Bit Error Rate Digital Signal Processing Emitter Coupled Logic Current Mode Logic Energy per TRansition Finite Impulse Response Filter Infinite Impulse Response Filter Ripple Carry Adders Carry Select adders Carry Look-Ahead adders Conditional Sum Adders Carry Signed Digit Sample and Hold Gate-oxide breakdown field Proportional to ... Transconductance of a MOS/Bipolar transistor Incremental output resistance of a transistor The gate-oxide capacitance The variance of the random variable X (the second central moment The current gain factor of a MOS The thermal noise resistance of a transistor The power spectral density of the noise voltage Bandwidth Gain Gain-Bandwidth product Weak-Inversion Strong Inversion Noise Excess Factor

xvi The saturation limits from negative supply rail (n) and positive supply rail (p) The power efficiency of an input stage The current modulation index The relative accuracy The effective gate-source voltage

xvii

Foreword The enormous rise of digital applications in the last two decades arouses the suggestion that analog techniques will lose their importance. However in applications that work with digital signals analog techniques are still very important for a number of reasons. First the signal that must be processed or stored may be analog at the input and output of the system. Second when digital circuits must operate at high speed the analog behavior becomes important again. And third when only limited bandwidth and signal to noise ratio is available the theoretical maximum data rate is determined by Shannon’s law. This theoretical limit can only be approximated in practice when complex modulation schemes are used, and after this modulation process the signal is analog again. Of course this does effect the tremendous advantage of digital signals compared to analog signals. Where analog signals deteriorate every time they are processed or stored, digital signals can be recovered perfectly when they are tailored to the properties of the system they are used for. The accuracy of digital signal processing is only limited by practical constraints and many digital signals can be compressed very effective so that after compression they use less bandwidth then their analog counterparts. In any aplication there will thus be analog and digital parts and often the choice has to be made if an analog or a digital solution is preferred for a certain function. It is often very difficult to give a founded opinion to this because there are many factors that play a role in this decision. This book tries to bring up methods and information that can help you in making the right choices. Things like the fundamental and practical limits of power dissipation for a specified accuracy and signal to noise ratio are discussed. Other factors like the process choice and related with that the chip area, the maximum supply voltage and the number of pins and external component also play an important role in the choice between analog and digital. Of course if a chip is mainly digital it becomes more difficult to integrate high quality analog circuit first because the digital cross-talk will interfere with the analog signal, second because the process choice will be based on the digital properties. Where many different processes are needed for different state of the art analog applications, CMOS processes that are optimized for digital applications have a tendency to go through comparable technical and lithographical improvements in different companies. Because the economy of these processes is much more determined by feature size than in analog processes, the huge drive for improvement. As smaller feature sizes in digital circuits also means lower energy dissipation per function more and more circuits that are still analog now will become digital in the future. Every new process generation the digital function gets smaller chip area and lower energy dissipation while the analog counterpart may even become worse because of a lower supply voltage, more noise and less linearity. The only analog parameter that still improves with every new CMOS generation is speed. This book starts with the theoretical foundation of the power considerations in sub-micron digital and analog circuits. Next, as there are many circuit solutions that can fulfil a certain specification, classes of circuits are discussed in order to help the reader in making the right initial choices. Then a number of circuits that are realized by the author are discussed in detail and the measurement results are presented. I think that this book can help the mixed signal designer to make the right choices on architectural and circuit level. ED A.J.M. VAN TUIJL

This page intentionally left blank

xix

Acknowledgements

The authors wish to acknowledge the financial support of this work by Philips Research Eindhoven namely the IC Design Sector and the logistic help of Philips Semiconductors Nijmegen during processing of the chips and measurements

This page intentionally left blank

CHAPTER 1 Introduction 1.1. Motivation From a historical point of view, VLSI designers have used the speed as a performance figure in comparing different designs [1], [2]. In terms of area and performance, a lot has been gained from scaling down the CMOS process towards smaller feature sizes [3], [4], [5]. The main concern in the late eighties was to find the best trade-off between performance and area where power consumption was not a design criterion but a subsidiary item. A significant change in the attitude of the designers is the desire to have remote access to computation capabilities without the need to be connected to the wired power supply. Here, the major concern is the weight and size of batteries which depends on the amount of power dissipated by the circuits. The largest majority of portable electronics use rechargeable batteries where the improvement in energy density will be only 40% at the end of this century. Given the slow improvement in the energy capacity, low-power design techniques are essential for portable devices. Subsequently, the efforts of researchers were directed towards power estimation and power reduction techniques [6], [7], [8]. In non-portable applications power consumption it is of concern since the cheap plastic packages for large volume market can withstand only 1W power dissipation. The trend is to increase the integration on chip of digital and analog functionality in more complex systems. In the past, large packages and/or cooling fans were capable of dissipating the heat generated on chip. As the density of integrated systems on chip increases, the cooling method will limit the complexity of those systems. A simple example is the increase of the clock rate of microprocessors (up to 600MHz) in order to increase the amount of computations per time unit. In those applications a figure of merit is the amount of processing per unit of power dissipation (e.g. MIPS/Watt). The power of microprocessors has increased up to some 30W in the last years which generate the situation where personal computers in US use some 10% of the commercial electricity consumption which accounts for the indirect production of from 5 million cars. That is why environmental incentives have required green chips [9].

2

The traditional low-power, low-throughput applications were pocket calculators, wristwatches, hearing aids and pacemakers. However there are a large number of new applications requiring low-power but high throughput [10]. Emerging portable applications are smart cards, DVD players, GPS navigators, digital cameras and camcorders. The advent of portable communications systems like digital cellular telephony networks which employs complex speech algorithms and radio modems, demand lower and lower power. In personal communication systems (PCS) voice, data and full-motion digital video will be transmitted wireless or wire-bound by using portable multimedia access [11]. Obviously, largely increased capabilities must be incorporated in the portable environment capable to support multimedia capabilities. The portable phones are dominating the future applications by far. Low power is the key issue in all those applications and has become the major concern. The mobile communications equipment market is the fastest growing market today. Cellular phones, cordless phones, paging receivers and mobile IT devices (PDA, Palm Top Computers) are becoming high tech due to ever increasing digital services. The analogue trend in those applications is towards low cost while new digital technologies are emerging. The trend is to increase the frequency and the amount of processing per unit of power dissipation (MIPS/power) at higher integration of functionality. In traditional applications and new emerging applications as well, CMOS will dominate by far while the tendency is to go to higher frequency, lower supply voltages and to higher integration of functionality with better computation power [12]. In conclusion, power is becoming a major concern in portable but also in wired power supply applications.

1.2. Problem definition The performance required points out towards higher integration and processing capability at lower and lower power consumption. Digital signal processing has become the major solution in all applications due to versatility, processing capabilities and last but not least lower power consumption. That is why the design effort in the last years has been directed towards low-power in digital. For this reasons, the CMOS process is tuned towards digital performance with negative consequences on analog functionality. What is then the situation in analog? Although digital dominates in size, analog dominates the interfaces and the high speed side. A/D and D/A conversion, filters, amplifiers, voltage references, power-up and power-down converters are possible analog applications. Analog remains the bottleneck in the design trajectory due to the efforts to cope with digital requests. If we are considering the analog part up to few years ago, the evolution has been going on at a slower pace. In the 90’s new technologies are evolved that are merging the high performance needed for analog with the density of CMOS. The design philosophy has to change: you have not to design the best analog circuit per se but the one that fits the best when used together with the DSP section [13]. As often it is told, DSP is the new name of analog: in this situation analog is not an art by itself but has to be in contact with DSP architectural definition. Many technologies are possible from CMOS analog-enhanced to BiCMOS,

3

GaAs etc. CMOS can quite often make the job and guarantee a single chip solution. That is why it should be the first choice whenever possible. In spite of these concerns related to performance degradation of analog circuits, there has not been a major focus on a design methodology of analog circuits which addresses power. When power is on the discussion floor, all aspects of the circuit, important from specifications point of view, are contributing to it. The approach which is presented here takes another viewpoint, in which possible aspects of a system design are investigated with the goal of reducing power consumption from the analog side. We state that low power in analog means to fit the design within the specifications with the minimum possible power consumption by using the most efficient architecture. Claims of low power should be doubled by specifications and the proof that the choice of the architecture is the best. The large variability of analog circuits makes almost impossible a thorough analysis. Only the inventiveness of the analog designer which is, most of the time, experience based or heuristic can generate new solutions. Mixed-signal design should make the best use of different signal representations like: sampled-data, time-discrete or time-continuous to find the best partitioning of the system in terms of performance and power. The ultimate goal is to shift from one domain to another e.g. digital or analog, sampled-data or continuous time and to find the best architecture to fit within the requirements.

1.3. Scope and outline The main part of this work focuses on power, noise and accuracy of analog circuits. However, the working environment for the analog circuits treated here is a mixed level environment. To get the best performance, knowing the limits of power in digital and clearly defining the environment where analog should work is a must. In sub-micron digital CMOS, to optimize power dissipation, a low-power methodology applied at different levels of abstraction is necessary. Power in analog is related to noise and accuracy. A further investigation to quantify their inter-relationship is required. When accuracy is important, new solutions of increasing accuracy in modern CMOS have to be found. We are looking for solutions insensitive to second order effects like mobility reduction and velocity saturation capable of working at low voltage with high linearity, dynamic range and accuracy, with low-power consumption. The outline followed in this book is described below.

Chapter 2: Power considerations in sub-micron digital CMOS Here, we consider first fundamental/physical limits and discuss afterwards the practical limits of power in digital, mostly at the architecture level. The fundamental limits are asymptotic limits and they cannot provide realistic comparisons between possible solutions. At architecture level, it is possible to find relations between power and signal to noise which provide a comparison basis to analog solutions. A new method is presented which takes into account different sources of quantization noise

4

in fixed point representations. Because the computational power of an algorithm implemented in one chip solution dominates, we have considered the computational power. A simple example of a digital filter shows how power can be saved at the architecture level. The same filter has been realized in an analog way in Chapter 4 where comparisons to the digital approach are presented. Ways to low-power in digital are being discussed also. They will provide some input for the analog part of this thesis.

Chapter 3: Power considerations in sub-micron analog CMOS In this chapter it is shown that low power analog circuits have to sacrifice dynamic range, linearity or accuracy. For analog functions, the reduction of supply voltages has a negative influence on dynamic range and power. In this chapter it is shown that low voltage is incompatible with low power when analog signal processing circuits are being considered. In plus, second order effects are becoming first order effects and analog solutions for higher supply voltages cannot be used anymore in scaled down processes. The main analog-related problems in scaled down processes are pointed out. In the beginning we are discussing fundamental limits of power in analog. They are combining in one simple equation power, S/N ratios and speed. There are no restrictions regarding topology, voltage swings, circuit topology, noise generated by active circuits, the process constants and linearity. Practical circuits show that power dissipation is dominated by the current needed to bias the active elements and has values few orders of magnitude larger than fundamental limits. The next section will consider practical limits of power in analog used for comparing different solutions. In analog functions, power is needed for biasing and to have sufficient accuracy and dynamic range. A designer wants a certain dynamic range and speed with a given accuracy, gain and linearity. Power consumption can be noise related or accuracy related. As far as white noise is concerned, it is proven that product is limited by power, topology and supply voltage, regardless of the type of circuits: continuous time or sampled data, current-mode or voltage mode. This is a general method and can be applied to simple analog building blocks or to more complicated analog systems like filters in order to find noise related power. Compared to noise related power, accuracy related power makes use of to find minimal power. The same conclusions like in noise driven power can be drawn for power supply scaled down processes.

Chapter 4: Gm-C integrators for low-power and low-voltage applications: A gaussian polyphase filter for mobile transceivers in 0.35 CMOS This chapter goes in circuits details showing how the theory described in Chapter 3 can be used for power comparisons. At low supply voltage, the key problem of analog signal processing functions is dynamic range reduction. Transconductors are basic functions in analog design used for amplifiers and filters. We are looking for power efficient architectures which can work at low supply voltages with high linearity and low noise. The new technologies are optimized towards digital applications and modern MOST’s suffer from velocity saturation and mobility reduction. New transconductor concepts which do not rely upon the ideal square law of a MOST, are needed. Another issue is to achieve large tunability without

5

conflicting with the large swing requirement. We have presented two power efficient Gm-C integrators capable of working at low supply voltage with high linearity. The first integrator is an OTA-C integrator based on a new idea which features a constant window at the input for different tuning conditions. It allows 2V input swing from a 3.3V power supply voltage with high linearity. It is shown that large swings can be beneficial to achieve large DR/P ratios. Positive feedback is a promising technique for enhancing gain in sub-micron CMOS because current matching in modern technologies improves. It avoids cascoding for having large gains and can be used for low-voltage applications. The second type of integrator considered in this chapter is a Gm-C integrator with local positive feedback for enhancing the gain. The reason for using this integrator consists in the low-voltage, high linearity and very high frequency of operation with a high power efficiency. It is compatible with standard digital technology has a high quality factor Q and can work down to 1.5V power supply voltage. Possible linearity improvements are shown. By using the product concept from Chapter 3 it is explained why the Gm-C approach has better power figures for the same working conditions when compared to OTA-C approach. The two integrators have been used to implement in an analog way the video filter used in Chapter 2. Matching in this type of filters is not important. Therefore we are dealing with noise driven power consumption. The required S/N of about 50dB shows that digital implementations have become more power efficient with possible improvement in the future, while analog solutions will have an increase in power due to power supply down scaling. There are filter applications where matching requirements and noise requirements have the same importance, with constraints on power consumption and linearity. Channel selectivity in receivers has been realized until recently using SAW filters. Those components are external components and therefore integration on chip of selectivity has become a major concern in receivers. A polyphase filter is an example of a selective filter without the need of high Q bandpass sections which are power inefficient according to Chapter 3. Here selectivity is rather obtained by using polyphase signals where matching driven power consumption comes as a variable. Polyphase filters can discriminate between positive and negative frequencies and therefore, using this property, selectivity can be achieved. By using a low power integrator, we have shown how to realize a polyphase filter needed for image rejection in a mobile transceiver. It fits the specifications with much less power consumption than opamp based approaches.

Chapter 5: Chopping: a technique for noise and offset reduction The flicker noise or 1/f noise has become of a major concern in analog circuits in deep sub-micron. In this chapter different methods to reduce 1/f noise and offset are being discussed. Chopping is a technique for noise and offset reduction employed to boost at the same time the accuracy and the dynamic range of analog circuits without extra penalty in power. As a modulation technique, chopping modulates in a different way white noise and 1/f noise of amplifiers. Therefore the difference between 1/f noise modulation and white noise modulation is being introduced with a comparison to sampling methods. Chopping is the only method which reduces 1/f noise and offset without modifying the baseband white noise like in the sampling case.

6

The trend in the new emerging applications is the increase of frequency range and data-rates. Chopping is a low frequency technique but there are applications where bandwidths of the signals are in the MHz range. At this frequency only the residual offsets generated from charge injection will limit the chopping frequency. A new method of using chopper modulation at high frequencies is introduced and a lowvoltage, low-power, chopped transconductance amplifier for mixed analogue digital applications is presented. The principle can be used for a large class of analog circuits for mixed-signal designs. Further it is shown that by using chopping techniques and the chopped OTA presented in the beginning, the accuracy of a bandgap voltage reference can be improved about ten times with the benefit of reducing the 1/f noise of the reference. The two examples show that the term low power has to be related to the specific application and its own specs. The same building block namely an chopped OTA can need about 90 times more power when high-end specs are required.

Chapter 6: Low-noise, low residual offset, chopped amplifiers for highend applications In this chapter we investigate the possibility of reducing the charge injection residual offset and the increase of chopper frequency up to 10MHz. A chopper stabilized opamp can be used wherever offset and noise specifications are important. The chopped amplifiers presented in this chapter are primarily meant as amplifiers capable of driving headphones in portable digital audio with high power efficiency thanks to a class AB stage. The new idea and the key towards low residual offsets is chopping of a part of the bias current which is shared by the output stage and the OTA. We are considering also gain enhancement techniques to boost the gain and to improve the accuracy. In portable digital audio we need high dynamic ranges and high accuracy with minimum power. Two designs are introduced: a CMOS version and a CMOS version. The CMOS version can work at lower power supply voltages with larger gain, based on a new class AB stage. Measurements on the CMOS version shows a DR of 111 d B and offsets lower than up to 7MHz chopper frequency.

Chapter 7: A 16-bit D/A interface with Sinc approximated semidigital reconstruction filter This chapter shows that low-power techniques at the highest level of abstraction as architectural level can lead to power savings which cannot be obtained unless the complete system is taken into study. This chapter presents a 16-bit D/A interface as an example of a system where accuracy and noise give constraints on the power consumption. An important issue to be discussed here is the optimization of the number of coefficients. An FIR filter with a large number of coefficients needs a large number of additional digital circuitry increasing the area, power consumption and complicating more the clock distribution. A large number of coefficients, requires more shift registers. Power in the digital domain will increase. The accuracy of the coefficients is subject to process tolerance caused by rounding of the small coefficients and quantization to the process grid span. A large number of coefficients

7

implies also big differences between coefficients and the accuracy of the smaller coefficients is impaired with consequences on the stop-band rejection. By using a new method called Sine approximation in the frequency domain and an iterative procedure, one can reduce the number of coefficients taking into account process tolerances such that the out of band rejection of noise requirement is met. Compared to the standard solutions we have reduced about four times the number of the coefficients for the same requirements. A differential solution is proposed to reduce the digital crosstalk and to increase the output signal swing. An analysis of the matching, noise and clock jitter is provided. The D/A interface has been realized on chip in a 0.8 CMOS, 5V technology and the measurement results are presented. Another approach: Sine approximation method in the time domain shows that power can be shifted from the digital domain into analog domain which allows the best partitioning of the system in terms of power. The principle of the method is discussed and generalized. Using a combination of the two methods, it is shown that with the same filter complexity like in nowadays approaches a reduction of power with a factor four in the digital domain is possible. Chopping can be used again for high-end applications.

8

REFERENCES [1] N. Weste, K. Eshragian, “ Principles of CMOS VLSI design”, Reading MA, Addison Wesley, 1985. [2] J.S. Ward et al., “Figures of merit for VLSI implementations of digital signal processing algorithms”, Proc. Inst. Elec. Eng., vol. 131, part F, pp.64-70, Feb. 1984. [3] M. Kahumu, M. Kinugawa, “Power-supply voltage impact on circuit performance for half and lower submicrometer CMOS LSI”, IEEE Trans. Electron Devices, vol.37, n0.8, pp. 1902-1908, Aug. 1990. [4] M. Nagata, “Limitations, innovations and challenges of circuits and devices into half-micron and beyond”, Proc. Symp. VLSI circuits, pp.39-42, 1991. [5] J. Borel, “LP/LV circuits in the deep submicron era” in the Proceedings of the 2nd IEEE-CAS Region 8 Workshop on Analog an Mixed IC Design, Baveno, Italy, 1997. [6] M.A. Cirit, “ Estimating dynamic power consumption of CMOS circuits”, Proc. IEEE Int. Conf. Computer Aided Design, pp.534-537, Nov. 1987. [7] S.R. Powell and P. Chan, “Estimating power dissipation of VLSI signal processing chips: The PFA technique”, VLSI Signal Processing IV, New-York: IEEE Press, 1990, Chapter 24. [8] H.J.M. Veendrick, “Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits”, vol. Sc-19, pp. 468-473, Aug. 1984. [9] B. Nadel, “The Green Machine”, PC Magazine, vol.12, no.10, pp.110, May, 1993. [10] J. Borel, “ESSCIRC ’97 low-power, low-voltage workshop”, Southampton, UK, Sept. 1997. [11] J. Rapeli, “Requirements and opportunities for integrated circuit technologies for mobile communications” invited paper at the IEEE International Conference on Electronics Circuits and Systems ICECS ’98”. [12] J. Borel, “LP/LV circuits in the deep submicron era” in the Proceedings of the 2nd IEEE-CAS Region 8 Workshop on Analog an Mixed IC Design, Baveno, Italy, 1997. [13] E. Vittoz, “Future of analog in the VLSI environment”, Proc. ISCAS’ 90, pp. 1372-1375, 1990.

CHAPTER 2 Power considerations in sub-micron digital CMOS 2.1. Introduction To optimize the power dissipation of mixed level systems a low-power methodology should be applied throughout the design process from system-level to process-level while keeping the same performance of the system. Low-power design methodologies can be considered at several abstraction levels as system, algorithmic ,architectural, logical and physical (device/process) as illustrated in fig.2.1. The process technology is under the control of process and device engineers. The other levels can be controlled by the design engineer.

10

Low-power techniques at the highest level of abstraction as algorithmic and architectural can lead to power savings of several orders of magnitude. At this level of abstraction, power analysis allows an early prediction and optimization of the power of a system. Starting from fundamental/physical limits we are discussing afterwards the practical limits of power in digital, mostly at the architecture level. The fundamental limits are asymptotic limits and they cannot provide realistic comparisons between possible solutions. At architecture level, it is possible to find relations between power and signal to noise which provide a comparison basis with analog solutions. Because the computational power of an algorithm implemented in one chip solution dominates, we have made some considerations regarding the computational power. A simple example of a digital filter shows how power can be saved at the architecture level. Last but not least, ways to low-power in digital are being discussed. They will provide some input for the analog part of this thesis.

2.2. Fundamental limits Fundamental limits for power can be derived from the basic principles of electromagnetics, thermodynamics and quantum mechanics [1], [2], [3]. They are asymptotic limits and give the minimum possible power.

2.2.1. Thermodynamic limit The thermodynamic limit can be derived from the following model. The resistor R with a mean square noise voltage given in fig.2.2 has been applied to a digital circuit modeled with an equivalent resistance R. The available noise power is (see reference [4]) where k is Boltzmann’s constant, T is absolute temperature and is the noise bandwidth. Since we want to transfer energy to the circuit in a digital form, the average signal power transferred, should be greater than the available noise power by a factor Therefore, the switching energy transferred to the digital circuit should be:

Although, the constant factor is larger than one we do not know yet how large has to be, in order to be able to have the probability of error in data transmission sufficiently small. For comparison sake, the necessary energy to move a single electron through a potential difference of about 0.1V it is in the order of 4kT=0. 1eV at room temperature. The probability of errors due to the thermal noise can be found by using Poisson distribution and it is proportional to:

11

The bit error rate in a modern digital transmission BER should be better than As a conclusion, in order to get reliable results, we have to use switching energies with a factor larger than the above mentioned value.

2.2.2. Quantum mechanics limit The uncertainty principle derived by Heisenberg provides the second fundamental limit [5]. An energy change associated with a switching transition must satisfy the following condition to give a measurable outcome:

where is the switching time and h is Plank’s constant. During a switching transition of a single electron wave packet, the required average power P can be deducted from (2.3) as:

The point where the thermodynamic limit reaches the same value as the quantum limit represents the boundary between the region where the electron can be treated as a classical particle and the region where it must be treated as a wave packet. Hence, the switching time can be computed as a function of absolute temperature:

12

Fig.2.3 illustrates the fundamental limits of power in digital signal processing from thermodynamics and quantum mechanics considerations in the power P-delay plane. The value of is taken 4 for the sake of comparison. Switching transitions at the left of their loci are forbidden. The zone for low power lies to the right of those limits. The physical limits shown above are not the only limits where power can be addressed. Material limits, circuit limits and system limitations can bring also clues about power. The fundamental limits are asymptotic limits and show how far one can go in the direction of power reduction. For realistic comparisons between different possible implementations of the same digital function we have to address the practical limits as explained in the following section.

2.3. From fundamental limits to practical limits of power. An architecture level approach. Fundamental limits cannot be a basis for relative comparisons between different digital realizations. In practice we need power not only to have a reasonable probability of error but also to switch parasitic capacitances, and a certain amount of

13

static power as a result of nonidealities of the CMOS transistors. To find practical limits of power, rules of thumb based on transistor counts were frequently used to estimate the energy consumption of a proposed digital implementation of an algorithm on chip. Unfortunately there has not been a useful relation between the energy consumption of an algorithm realized in CMOS and either its transistor count or its arithmetic complexity. The cause is the multivariable problem of power which depends on process and digital library too. In this section power at architectural level is being discussed. Without the claim of being exhaustive we try to point out the main problems. There are four sources of power dissipation in digital CMOS circuits [11] which are summarized in the following equation:

represents the switching component of power. is due to the directpath short circuit current which arises when both the NMOS and PMOS transistors are simultaneously active. is due to the leakage current which can arise from reverse bias diode currents and sub-threshold currents. The static power arises in circuits that have a static biasing current between the power supplies present, for example, in class A type of logic (ECL, CML etc.). The previous equation can be rewritten in the following form:

In the switching part of power, represents the activity factor showing how many transitions per clock cycle we have. is the load capacitance and is the clock frequency. The switching power arises when energy is drawn from the power supply to charge and discharge parasitic capacitors. A designer tries to minimize the last three terms of power when compared to the switching power. The problem can be solved by using management solutions which adjusts the threshold voltage of the process in order to minimize the subthreshold currents when switching activity is low. In the following paragraphs we are considering only the switching power. Digital algorithms can be implemented using memory elements, adders and multipliers. In DSP the switching power is a function of the number of bits B, clock frequency and another variable that depends on the type of process and multiplier:

represents the energy per transition and the proportionality constant multiplied by the number of bits gives the number of operations per cycle. In [6] and [7] E. Vittoz has found relationships between power and S/N by taking a general type of multiplier and the general expression for S/N of a signal with discrete amplitude levels:

14

In this case, the number of operations per clock cycle was taken 50 and the power needed for multiplication is:

If the number of bits are replaced in the power relation, one can find:

The signal frequency and the clock frequency are related. Let’s assume that In this particular case, the power per pole depends on S/N as:

Therefore, the relationship between switching energy and signal to noise ratio S/N is logarithmic. This equation has been plotted for different in fig.2.4. To be mentioned the decrease in the for modern processes and therefore, this power limit is pushed down as the road-map trajectory in the modern processes shows [8]. Different multipliers have different number of operations per cycle and therefore the factor 50 in eq.(2.10) is actually dependent on the type of multiplier. Typical figures can be found in the literature [11], [12] and some of those are shown in table 1.1. Therefore, eq.(2.10) cannot be used in a general case being dependent on the type of implementation. The general equation for S/N is valid when one source of quantization errors is present. However, in a filter there are other sources of quantization errors which are introduced in the next paragraph.

15

2.3.1. Power in FIR filters. An example of a DSP algorithm is a digital filter. For the beginning consider a FIR filter with m coefficients in a one chip solution [13] as shown in fig.2.5. Here, the filter structure is composed from basic cells called processing elements PE. A processing element contains memory elements, multipliers and adders. The processing element can be distinguished within the dotted box. Given the number of states S in the filter which have to be memorized, the number of bits per word B and the number of multipliers per processing element X, we can compute the total power per DSP FIR unit

The total power is a sum of power needed for memory the computational power needed for adders and multipliers and the power needed for input/output ports The power needed for computation, can be determined from the power per processing element PE.

16

is a proportionality constant dependent on the technology and lay-out. In this particular case X=1 but it is possible to use one multiplier running times faster and X=1/m with no consequences on eq. (2.14). The number of states and the number of multipliers per PE give the power needed for memory when X=S=1:

In a single chip solution, the power needed for I/O operations depends on the number of bits per word B and the sampling frequency:

If the number of bits B is comparable to the number of processing elements m the power needed for memory access cannot be neglected. Moreover, for a large number of filter coefficients, the memory power will dominate over the computational power. Therefore the total power needed for FIR DSP is:

2.3.2. Power in IIR Filters This form contains a recursive part and a non-recursive part without sharing delay elements (direct form 1) [13]. The number of processing elements PE is n+m as shown in fig.2.6. Again we have assumed memory elements as shift registers. Therefore the internal states of the filter are copied in the memory. In terms of power needed for computation there is no difference between an IIR filter and a FIR filter.

17

The total power will be the sum of power consumed by the recursive part and the power needed by the nonrecursive part.

Given the number of processing elements m+n one can find the power needed by an direct form 1 IIR filter (IIR1) using the same considerations as in the case of a FIR filter.

When the memory elements are shared, the computational power remains the same. The memory access overhead decreases by sharing some delay elements as depicted in fig.2.7 for an IIR filter direct form 2 (IIR2):

In conclusion, power needed for IIR2 DSP is smaller than the power needed for IIR1 DSP. In dedicated applications, shift registers are used as memory elements. In most applications the memory access power can be neglected when compared to computational power. Since the interconnect capacitance dominates in a shift register, the power consumed inside the registers can be neglected. Given the total capacitance at the input and at the output and the activity factor equal for the input and for the output of the register, the power can be approximated with:

The power for input/output operations is the power needed by the input/output registers which are clocked at the rate needed to communicate with the outside world. In a single chip solution, the dominant term, in most of the cases, remains the computational power. From now on we are referring only to this term.

18

2.4. S/N ratio and power in fixed point applications In section 2.3 the relationship between power consumption and S/N has been discussed. The assumption in eq. (2.12) is that quantization noise comes from only one noise source. In practical situations this is however not true. When processing with a fixed number of bits quantization will occur to prevent the increase of number of bits after multiplication. The limitation of the word lengths of intermediate results has one of the most complicated consequences on digital filters. An intermediate result appears as an outcome of a multiplication and/or addition. We shall assume here that we want a B bit system in which the quantities are represented as B-bits words in a fixed-point representation with one sign bit before the decimal point. A product requires 2B-1 bits while an addition requires only B+1 bits. The addition increases the number of bits before the decimal point and the multiplication needs an increased number of bits after the decimal point. Addition introduces overflow problems and multiplication quantization problems. The problem of overflow can be solved by scaling the signal before the filter. Because every multiplication produces an increased number of bits, we have to use quantization after every multiplication in applications with fix number of bits and, therefore, we are introducing noise again. The number of bits used strongly affects all key parameters of a design, including speed, area and power. That is why it is desirable to minimize the number of bits. To find a relation between power, signal to noise ratio S/N and the type of the architecture, we have to compute the S/N in the case of FIR and IIR architectures. Given the quantization step q, the noise power of the quantization noise and the gain factor k for avoiding overflow, we can consider that the signal power at the input provided by the A/D converter is [13]:

The power of the signal in the output can be computed for every possible architecture by knowing the transfer function and the input signal power. As explained, after multiplication quantization occurs and the noise power at the output increases. The method to find the relationship between computational power and S/N is presented in Appendix 1 where, the case of FIR and IIR2 structures has been considered. Given the number of operations per clock cycle, the energy per transition, the desired transfer function and the number of coefficients, one can find the relationship between power and S/N taking into account the noise sources in a FIR or IIR2 structure. In eq.(2.16) the number of operations per clock cycle and the energy per transition are included in the constant while the desired transfer function is included in term

The same type of logarithmic relationship holds for an IIR2 structure between the computational power and signal to noise ratio S/N.

19

2.5. Adders and computational power Parallel multipliers are well known building blocks used in digital signal processors as well as in data processors and graphic accelerators. However, every multiplication can be replaced by shift and add operations. That is why, the adders are the most important building blocks used in DSP’s and microprocessors. The constraints they have to fulfill are area, power and speed. The adder cell is an elementary unit in multipliers and dividers. The aim of this section is to provide a method to find the computational power by starting from the type of adder. There are many types of adders but generally they can be divided in four main classes: Ripple carry adders (RCA); Carry select adders (CS); Carry look-ahead adders (CLA); Conditional sum adders (CSA). The starting point for any type of adder is a full-adder FA. An example of a full adder in CMOS is shown in fig.2.8. The discussion for this adder can be generalized for every type of adders. The outputs SUM and CARRY depend on the inputs a, b and c as:

In a multiplier we are using parallel-series connections of full-adders to make a B bits adder with m inputs. In the following paragraph we make the assumption that every full-adder is loaded with another full-adder. Another assumption will be that the adder

20

has been optimized from the lay-out point of view to give minimal energies per transition when an input has been changed.

2.5.1. Ripple carry adders (RCA) The reason to choose for ripple carry adders consists in their power efficiency [15] when compared to the other types of adders. Making an n bit ripple carry adder from 1 bit adders yields a propagation of the CARRY signal through the adder. Because the CARRY ripples through the stages, the SUM of the last bit is performed only when the CARRY of the previous section has been evaluated. Rippling will give extra power overhead and speed reduction but still, the RCA adders are the best in terms of power consumption. In [15] a method to find the power dissipated by a B bits wide carry-ripple adder has been introduced. Denote the mean value of the energy needed by the adder when the input a is constant and the other two inputs b and c are changed. This energy has been averaged after considering the transition diagram with all possible transitions of the variables. and are being defined in a similar way. Denote the mean value of the energy needed by the full-adder when the two inputs a and b are kept constant and the input c is changing. By analogy we can define and The energy terms and respectively depend on technology and the layout of the full-adder. Composing a m bits adder from a full-adder can be done in an iterative way as shown in fig.2.9. At a given moment, the inputs A[k] and B[k] are stable. After this moment every SUM output is being computed by taking into account the ripple through CARRY. The probability to get a transition on the CARRY output after the first full adder FA is ½. After the second FA the conditional probability to have a transition is ¼ and so on.

21

By using the same reasoning, the probability at the CARRY[m] is The inputs A[k] and B[k] are stable and we have to take into consideration only the energy For the first full-adder, when the inputs A[1] and B[1] are applied, the CARRY output is changing. The first adder contributes with to the total energy. The bit k contributes with energy E[k] given by:

The total energy dissipated by the m bits carry-ripple adder can be found by summing all contributions of the bits k. Hence, we get the total energy as a function of mean values of the basic energies of a full-adder FA:

For large values of m eq.(2.20) can be approximated with the first term. This result can be used to compose cascade adders.

2.5.2. Cascade adders To add m words of B bits length we can cascade adders of the type shown in fig.2.9. The result is illustrated in fig.2.10. We can assume statistical independence between the SUM and CARRY propagation in the following calculation. The SUM propagates in the direction and the CARRY propagates in the direction

22

The energy needed for the SUM propagation is and for the CARRY propagation Supplying the operands at the input b, the energy consumed at the bit (k,1) can be obtained from eq. (2.19):

The total energy of the cascade adder is a sum of the energies needed by the individual bits and can be found by summing E(k,1) over and as shown in eq.(2.22).

When the number of bits B equals the number of words m eq.(2.22) shows the dependence of power on the number of bits squared as explained earlier in the computational power. This shows how the total energy of the cascade adder can be related to the energy consumption of the basic building element, the full-adder FA. Now composing functions at higher level multiplication-like is possible.

2.5.3. Chain versus tree implementations of adders In ripple through carry type of adders, a node can have multiple unwanted transitions in a single clock cycle before settling to its final value. Glitches increase the power consumption. For power-effective designs they have to be eliminated or, when this is not possible, at least limited in number. One of the most effective way of minimizing the number of glitches consists of balancing all signal paths in the circuit and reducing the logic depth. Fig.2.11 shows the tree and the chain implementation of an adder. For the chain circuit shown in fig.2.11 (a) we have the following behavior. While adder 1 computes adder 2 computes with the old value of After the new value of has been propagated through adder 1, adder2 recomputes the correct sum Hence, a glitch originates at the output of adder 2 if there is a change in the value of At the output of adder 3 a worse situation may occur.

23

Generalizing for an N stage adder, it is easy to show that in the worst-case, the output will have N extra transitions and the total number of extra transitions for all N stages increases to N(N+1)/2. In reality, the transition activity due to glitching transitions will be less since the worst input pattern will occur infrequently. In the tree adder case shown in fig.2.11 (b), paths are balanced; therefore the number of glitches is reduced. In conclusion, by increasing the logic depth, the number of spurious transitions due to glitching increases. Decreasing the logic depth, the amount of glitches will be reduced, making possible to speed up the circuit and enabling some voltage downscaling while the throughput is fixed. On the other hand, decreasing the logic depth, increases the number of registers required by the design, adding some extra power consumption due to registers. The choice of augmenting or reducing the logic depth of an architecture is based on a trade-off between the minimization of glitching power and the increase of power due to registers.

2.6. Ways to low-power in digital We have discussed so far power issues related to the architecture level. For every level of abstraction from fig.2.1 there are ways to reduce power which have an influence on analog functionality integrated on the same chip. In this section, we are going to point out which are the most important ways to reduce power at different levels and the consequences on analog functions [11], [12] and [16].

2.6.1. Process technology The most effective way to reduce power at device level is to reduce the power supply voltage. This has consequences on the delay as power supply voltage approaches the threshold voltage. The problems we want to improve are: Increasing current drive capabilities of the devices; Availability of variable and multiple threshold devices for better stand-by characteristics and better matching to the analog or digital design; Reduced parasitic capacitances at small geometries; Improved interconnect technology such that interconnect scales down at the same rate as the devices; Analog will benefit also from this except for supply voltage reduction.

2.6.2. Logic and circuit level There are many techniques available for minimizing power at this level like: Clever circuit techniques to minimize device count and switching activity; Clever transistor sizing and down scaling in the non-critical paths of the system where throughput can be reduced; Reducing the switching activity by logic optimization. Less switching activity will reduce the digital crosstalk; Choose for multi- logic circuits for better optimization of stand-by and dynamic power. Low transistors will give the best analog performance in terms of speed.

24

2.6.3. Power reduction at architecture level At the architectural level of abstraction there are possible certain techniques for power reduction like: Architectures based on parallelism, pipelining and a combination of the two; Power management techniques by shutting down parts of the circuits on stand-by mode; The partition of memory for better power activities; Reduced number of busses.

2.6.4. The algorithmic level To reduce power at the algorithm level one should be able to optimally use an algorithm such that: The number of operations are minimized with consequences on hardware reduction; Better coding for minimum switching activity by taking into account the statistics of the input signal.

2.6.5. Power at system level At this level of abstraction a good partitioning of the system in terms of digital or analog solutions is important. Examples of methods for power reduction are: Integration of analog peripherals and off-chip memories on the same chip; Clock distribution such that system clock is a low frequency clock and internal clock generated at higher frequencies with phase locked loops. Since the average energy dissipation per cycle is proportional to where C is the load capacitance and V is the voltage swing, the obvious path to minimum power is to reduce C by scaling down minimum feature-size and especially to reduce V (see also [17]). Voltage scaling represents an efficient way to reduce power in digital. The minimum allowable value of supply voltage for a static CMOS inverter was derived by R. Swanson [18] as:

The condition arises from the requirement to have voltage gains larger than one. However, reducing the supply voltage down to that value has other consequences. The well known power-delay product or energy per transition, is proportional to For a simple inverter, when is down-scaled close to there is a speed penalty to be paid. The simple inverter shown in fig.2.12 has a delay given by:

25

The lower the supply voltage the higher the delay. Therefore, we have to operate the circuit at the slowest possible speed. In order to maintain the throughput it is necessary to compensate for the increase of the delay by sizing-up W/L ratios of the transistors. When sizing-up the W/L of the transistors, the drain and source diffusion increases and the parasitic capacitances are increasing giving the possibility for an optimum in terms of scaling for keeping the delay constant.

2.7. Example of a digital video filter The following section introduces an example of a low-pass digital FIR filter for video applications, showing how power savings can be made by replacing multiplications with shift and add operations. This is possible by using a special format for the filter coefficients as powers of 2 or differences of powers of two. For digital realizations adders from section 2.5 have been used. The same filter will be realized in Chapter 4 as an analog filter where comparisons between analog and digital realizations will be given. The filter has a pass-band up to 5.5MHz, a transition band from 5.5MHz up to 15MHz and a stopband rejection better than -40dB. The specifications of the video filter are summarized in table 2.2. For a luminance video filter it is important to have a very low pass-band ripple. That is why the possible solutions are Butterworth and inverse-Chebyshev filters with a maximally flat amplitude in the pass-band. It is known that inverseChebyshev filters provide a smaller group-delay when compared to Butterworth counterparts. That is why, an inverse-Chebyshev filter has been chosen. The synthesis procedure of the filter is given in Appendix 2 and the outcome of the synthesis is the filter from fig.2.13. The group delay of the filter varies from 46ns and 59ns, thus within specifications.

26

The chosen sampling frequency of the filter is As long as the coefficients are fixed, multiplications can be transformed in shift and add operations. The computed coefficients are given in table 2.3. Here T stands for sign inversion and L represents the exponent. The first column shows the coefficients in real format and in the second column, the coefficients are given in CSD (Carry sign digit) format.

In this format (CSD), the coefficients are realized from powers of two or differences of powers of two. Multiplication with a power of two means shifting. Consider the second coefficient of the filter 2.343750L-02 which can be written as The multiplication with this value is illustrated in fig.2.14.

27

The input is shifted 5 times and added to the inverted value of the input shifted 7 times. The adder has one bit in plus compared to the word-length and the input CARRY set to one such that overflow will not occur. Fig.2.15 shows the transfer function of the video filter realized with coefficients from table 2.3. It is important to mention that CSD format is an approximation of the filter coefficients. That is why a computer routine is necessary to find the best approximation to fit the filter within the specifications. This method can be used whenever coefficients are fixed, like in dedicated applications. According to table 2.3, the filter can be implemented with 11 adders for multiplications and 9 adders for final summation. The power consumption of the filter can be found by using the results of section 2.5. In the Table 2.4 the energy consumption of the full adder FA from fig.2.8 are given. The technology is a CMOS digital technology. The power consumption of the FIR video filter taking into account only the computational power is 2mW which gives about per pole (0.16pJ/pole). To be mentioned that FIR filters are all zero filters but for the sake of comparisons with analog approaches we have considered the power per analog pole. In conclusion, this example shows that for applications with fixed coefficients a multiplier is not always necessary and power savings can be achieved by using only shift and add operations.

28

2.8. Conclusions Low-power design methods can be considered at several abstraction levels as system, algorithmic, architectural, logical and physical. Low-power techniques at the highest level of abstraction as algorithmic and architectural can lead to power savings of several orders of magnitude. At this level of abstraction, power analysis allows an early prediction and optimization of the power of a system. Starting from fundamental/physical limits we are discussing afterwards the practical limits of power in digital, mostly at the architecture level. The fundamental limits are asymptotic limits and they cannot provide realistic comparisons between possible solutions. At architecture level, it is possible to find relations between power and signal to noise which provide a comparison basis with analog solutions. In section 2.3 the relationship between power consumption and S/N has been discussed. The assumption made is that quantization noise comes from only one noise source. In practical situations this is however not true. When processing with a fixed number of bits, quantization will occur to prevent the increase of number of bits after multiplication. A more accurate approach is presented in section 2.4. Because the computational power of an algorithm implemented in a one chip solution dominates over other sources of power consumption, we have considered only the computational power. Every multiplication can be replaced by shift and add operations. That is why, the adders are the most important building blocks used in DSP’s and microprocessors. The adder cell is an elementary unit in multipliers and dividers. The aim of section 2.5 is to provide a methodology to find the computational power by starting from the type of adder. Composing other functions at a higher level, multiplier-like, is possible by using the results of this section. Although the main part of this thesis focuses more on power related to analog circuits, the working environment for analog circuits treated here is a mixed level environment. Therefore, ways to low-power in digital and their influence on analog functionality are being discussed. They will provide some input for the analog part of this thesis. In the last section a simple example of a digital filter shows how power can be saved at the architecture level by using CSD formats for filter coefficients. Multiplication here will be replaced with shift and add operation eliminating thus an expensive and power consumptive building block. The same filter will be realized in an analog in Chapter 4 and the results compared to digital implementation.

29

REFERENCES [1] R.W. Keyes, “Physical limits in digital electronics”, Proceedings of the IEEE, vol.63, no.5, pp.740-766. [2] J.D. Meindl, “Theoretical, practical and analogical limits in ULSI“, IEEE IEDM, Technical Digest, pp. 8-13, 1983. [3] J.D. Meindl, “ The evolution of Solid State Circuits: 1958-1992-20??”, 1993, IEEE ISSCC Commemorative Supplement, pp.23-26, Feb. 1993. [4] F.W. Sears, “Thermodynamics”, Addison Wesley, Reading, Mass. 1953 [5] H. Haken and H.C. Wulf, Atomic and Quantum Physics, Springer Verlag, pp.8385, 1984 [6] E.A.Vittoz, “Low-power design: ways to approach the limits”, in IEEE International Solid-State Circuits Conference, Dig. Paper, 1994, pp.14-18 [7] E.A.Vittoz, “Future of analog in the VLSI environment”, in Proc. IEEE ISCAS, pp.1372-1375, 1990 [8] Semiconductor Industry Association, “The National Technology Roadmap for Semiconductors” 1997, pp. 46-47. [9] J.A.J. Leijten, J.L. Meerbergen and J. Van Jess, “Analysis and reduction of glitches in synchronous networks”, Proceedings ED&TC, pp.398-403, 1995 [10] T. Sakuta, W. Lee and P. Balsara, “Delay Ballanced multipliers for low power, low voltage DSP core”, 1995 Symp. on low power electronics, Dig. Tech. Papers, pp. 36-37, 1995 [11] A.R. Chandrakasan and R.W. Brodersen, “ Low power digital CMOS design”, Kluwer Academic Publishers, Norwell MA, 02061 USA and Dordrecht, The Netherlands, ISBN 0-7923-9576-X. [12] A. Bellaouar and M.I. Elmasry, “Low power digital VLSI design: Circuits and systems”, Kluwer Academic Publishers, Norwell MA, 02061 USA and Doordrecht, The Netherlands, ISBN 0-7923-9587-5. [13] A.W.M. van den Enden, N.A.M. Verhoeckx, Discrete-time signal processing: An introduction, pp. 173-177, Prentice Hall, 1989, ISBN 0-13-216755-7. [14] D.J. Kinniment, J.D. Garside and B. Gao, “ A comparison of power consumption in some CMOS adder circuits”, Proceedings of PATMOS, Eds. C. Piguet, W. Nebel, pp. 119-132, ISBN 3-8142-0526-X. [15] J. Smit, “On the energy complexity of algorithms realized in CMOS”, in Proceedings of the ProRISC/IEEE Workshop on Circuits, Systems and Signal Processing, Mierlo, The Netherlands, Nov. 1996, pp.331-341. [16] Enrico Macii, “Low power design in deep submicron electronics”, ISBN 0-79234569-X, pp.363-364 [17] H.J.M. Veendrick, “Short circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits”, IEEE Journal of Solid-State Circuits, vol. SC-19, pp.468-473, Aug. 1984. [18] R.M. Swanson and J.D. Meindl, “Ion-implanted complementary MOS transistors in low-voltage circuits”, IEEE Journal of Solid-State Circuits, vol.SC-7, no.2, pp. 146152, April 1972.

This page intentionally left blank

CHAPTER 3 Power considerations in sub-micron analog CMOS 3.1. Introduction Reliability and power considerations in scaled down processes for digital applications point towards lower and lower supply voltages [1] as explained in the previous chapter. The context in which analog functionality has to be integrated is a sub-micron, digital process. This process is optimized for digital solutions regardless the need of integration on chip of analog functionality. For analog functions, the reduction of supply voltages has a negative influence on dynamic range and power dissipation [2], [3], [4]. In this chapter it is shown that low voltage is incompatible with low power when analog signal processing circuits are being considered. Analog designers have to cope with second order effects generated by the incompatibility of the process with analog performance. This makes the process of designing circuits a difficult task since most of the solutions valid for large supply voltages are not anymore useful due to the low voltage limitations. In many cases this yields an increase in power consumption to cope with those requirements. Although performance-critical analog circuits require a higher supply voltage it is important to design low-voltage amplifiers, data converters, filters and understand the ultimate limits for power, dynamic range and linearity [5], [6], [7], [8]. Very low power circuits have to sacrifice dynamic range, linearity or accuracy. We will focus on analog functions with high demands on accuracy, dynamic range and linearity where low-power design means to fit exactly the design within specifications with minimum power. A designer wants a certain dynamic range and speed with a given accuracy, gain and linearity. Low voltage and low power are imposed by the application and the mixed level context. The fundamental limits for low-power in analog are asymptotic limits [2], [3]. They are combining in one simple equation power, S/N ratios and speed. There are no restrictions regarding topology, voltage swings, circuit topology, noise generated by active circuits, the process constants and linearity. By using a

32

simple scaling rule, it is possible to travel along the asymptotic line without knowing whether the circuit is power optimal or not (similar discussions in [9]). Practical circuits show that power dissipation is dominated by the current needed to bias the active elements and has values few orders of magnitude larger than fundamental limits. That is why it is important to know practical limits of circuits and to use them in comparing different possible solutions. Starting from general considerations and simple circuits, it is possible to prove that DR*Speed product is limited by power, topology and supply voltage regardless of the type of circuits: continuous time or sampled data, current-mode or voltage mode. Only white noise is taken into considerations. Substrate noise and 1/f noise are discussed in the next chapters. In some applications matching imposes restrictions on the obtainable accuracy [10]. Accuracy driven power gives stronger limits for power consumption. That is why, some considerations about matching driven power are mandatory. Further details concerning matching will be discussed in the next chapters.

3.2. Process tuning towards digital needs. Consequences on analog Tuning the CMOS technology for mixed signal ICs towards digital performance and low power has numerous consequences on analog functionality. From an analog point of view the most important characteristics of a transistor are: the transconductance, the output conductance, the gate and difussion capacitances, accuracy, speed, noise and signal swing. As we will see, tuning the process towards digital performance impacts the analog functionality and the way designers would have to tackle different analog building blocks.

Table 1 shows the roadmap trajectory predicted by Silicon Industries Association [11]. The most important factor is the gate oxide breakdown field The values for are given from reliability consideration. For analog, the maximum supply can be derived from maximum field strength and oxide thickness. The power supply for analog functions will remain in the order of 1.5 to 2V even for technologies below one tenth of a micron and can be derived from one penlite battery with step-up converters and power management blocks. Even at this voltages designing high performance analog functions is a problem. Also it is assumed that a new replacement for will be found and therefore the maximum field strength will increase. As far as on-chip ROM memory is becoming a fact, devices which can withstand higher voltages are available and difficult analog functions can be integrated on the same die.

33

3.2.1. Transconductance The transconductance of a transistor is limited at the upper side by velocity saturation. In velocity saturation region, the transcoductance becomes constant, independent of gate length or bias:

For an effective width of the saturated transconductance has a value of about for a process. In many analog circuits tuning for process spreads by increasing the current is not effective once the velocity saturation region is trespassed. In some applications, weak inversion region can be used in order to deliver the maximum transconductance for a given current.

3.2.2. Output conductance The output resistance is influenced by channel length modulation, static feedback and weak-avalanche effect as explained in fig.3.1. The output resistance for a given width and a given gate voltage decreases quickly at lower gate lengths. Therefore, the speed increase in deep submicron processes will be paid by a lower output resistance. It is possible for a CMOS process to have a unity intrinsic gain Therefore, the device cannot be used anymore for amplification purposes. The increase of current above the velocity saturation region does not help once the transistor is velocity saturated. Enhancing the output resistance of the transistor by cascoding conflicts with low voltage requirement. Besides, the product appears again in the expression of the output resistance after cascoding. Hence, other solutions have to be found. Techniques employing positive feedback can be considered as long as matching becomes better.

34

3.2.3. Difussion and gate capacitances In modern technologies the gate oxide becomes thinner and subsequently Cox increases. The gate-source and gate-drain capacitances scales down as the process feature size shrinks. However, the difussion capacitance goes up and because the interconnect parasitic capacitances are becoming dominant we can conclude that the load capacitance of a transistor increases.

3.2.4. Accuracy Two identical devices show a random mismatch in the parameters due to the stochastic nature of physical processes. Mismatch can be defined as the process that causes time-independent random variations in physical quantities of identically designed devices [12]. Consider the mismatch of two identical transistors which depends on the random variation of the current factor the threshold voltage and the body factor The classical theory [12], [13] applied for devices with a minimal feature size larger than makes use of the following model:

The variance of the three parameters depends on the process dependent constants A and S. W and L are the gate-width and the gate length respectively and D represents the distance between the devices. The distance dependent terms can be neglected in most cases. Considering only the mismatch in shown in fig.3.2., this will improve

35

for deep submicron technologies due to the dependence of

on the oxide thickness

The above mentioned model is not accurate for deep submicron MOST due to narrow and short channel effects. In references [14] and [15] two other terms which account for narrow and short channels are considered in the mismatch:

The second term models short channel effects and the last term models narrow channel effects. It predicts a better accuracy for devices with small gate widths and large channel lengths than the linear model. The dependence of mismatch on the oxide thickness indicates improvement of matching when scaling down the technology towards deep submicron. The mismatch in the current gain factors becomes dominant in deep submicron and scaling down further does not bring benefits. More about matching is discussed in the following chapters.

3.2.5. Speed The cut-off frequency of a MOST depends on capacitance

and the gate-source

This is valid in saturation and forward biasing of the transistor. Hence, modern processes have higher cut-off frequencies due to the inverse proportionality of with However this increase is being offset by the increase of difussion capacitances and the fact that interconnect cease to scale down when feature size shrinks.

3.3.6. Substrate noise In mixed level applications another source of noise arises. It is the substrate noise or the substrate interference [16] which perturbs analog circuits due to switching in digital. Modern sub-micron technologies have low ohmic substrates and that is why substrate interferences from digital are mostly present. The effect of this source of noise is the bounce of the line which can have values up to few hundreds of mV. As a consequence, the substrate bounce will reduce the dynamic range of analog circuits.

36

3.2.7. Signal swing In modern processes the signal swing reduces with lowering of the power supply. Different options and scenarios are possible. The most trivial solution is multichip module (MCM) technology in which analog functions are implemented on a separate chip. Low devices are important for analog functions when voltage swing is reduced. A natural unimplanted device has a low and can be used for analog blocks. For digital functions, low devices would give an increase in the subthreshold currents. management solutions can be used in a twin-well process to adapt for the best performance. Probably the good news for analog designers is the possibility to have ROM devices which can withstand higher voltages. Therefore separate supply voltages for analog and digital is becoming a fact. The effects of signal swing on dynamic range will be extensively discussed in the next chapter.

3.3. Fundamental limits Fundamental limits for analog processing can be found from fig.3.3 where an analog processor is shown [2], [3]. This analog processor can be an amplifier, a filter, an oscillator etc. On the capacitor C there is a voltage with a peak-peak value From the power supply is drawn a current with a mean value of Denote the charge drawn from the power supply and f the frequency of the signal. Then, the total power P is:

Power has a minimum when the peak-peak voltage on the capacitor has a value close to the power supply voltage. The capacitor C is charged and discharged from the

37

power supply from a resistive path. The thermal noise generated by the resistive path will create noise on the capacitor but the band limiting action of the RC combination gives a finite contribution of noise on the capacitor, independent on the value of the resistor. The noise power on the capacitor is kT/C where k is the Boltzmann’s constant. The S/N ratio defined as the power of the signal over the power of the noise can be found from:

Therefore, we can relate the power P to the S/N ratio in the following manner:

This absolute minimum of power predicts a ten fold increase of power for every 10 dB increase in signal to noise. In fig. 3.4 we have plotted on the same picture the power per frequency for a digital processor (see Chapter 2) and the power per frequency of an analog processor as a function of S/N ratio. Comparisons between power consumption in analog versus digital, based on this figure will predict advantages of digital processors for large S/N ratios and advantages of analog processors for low S/N ratios respectively [2], [3]. Given the fact that energy per transitions in digital decreases with the decrease of the feature size (see SIA roadmap from [11]), in future, digital processors are supposed to become more power efficient even for lower S/N ratios.

38

3.4. From fundamental limits to practical limits of power. Noise related power The fundamental limits for low-power in analog are asymptotic limits without restrictions regarding topology, voltage swings, circuit topology, noise generated by active circuits, the process constants and linearity. Practical analog circuits show power dissipations of few orders of magnitude larger than fundamental limits. That is why it is important to know practical limits of circuits and to use them for comparing different possible solutions in order to make the right choice.

3.4.1. Noise prerequisites. Channel thermal noise To make noise estimations we need the power spectral density of the drain current noise, valid for all possible working conditions of a transistor. The power spectral density of the current noise of a MOS transistor is proportional to the total charge stored in the channel, in the inversion layer [17]. This proportionality holds true for all working regions.

denotes the thermal noise conductance of the transistor. The thermal noise in most of the situations can be modeled either with a current source with a PSD of or with a voltage source with a PSD of as shown in fig.3.5.

The value of can be found from resistance of the transistor

as a function of the thermal noise

The value of the thermal noise conductance depends on the working region of the MOS transistor [17]. Table 3.2 gives the values of the thermal noise resistance as a function of the slope factor n of a MOST and the working region of the MOST. Saturation denotes actually forward saturation in this case. Hence, a MOS transistor biased in triode region (strong inversion or weak inversion) will have a larger noise when compared to saturation noise. For a modern CMOS process the value of the slopefactor n approachesunityand therefore, most of the noisemodels, agree that the

39

power spectral density of the noise current of a MOST in strong inversion and saturation can be approximated with:

3.4.2. Flicker noise Besides white noise we have additional low-frequency noise due to fluctuations of the density of charge carriers caused by trapping of the carriers in the oxide and in the neighborhood of interface. There are different theories but all agree over the dependency of the power spectral density of the noise on frequency and gate area as:

where is a process dependent constant. Although 1/f noise is a low frequency random process, it appears also in RF CMOS circuits e.g. as phase noise in oscillators due to the nonlinear mechanisms which convert the low frequency noise in the sidebands of an oscillator, generating jitter. In older processes, the difference between the noise of a PMOST and an NMOST can be as high as 100 in the favor of PMOST’s. Modern processes without burried transistors show a smaller difference between the noise of a PMOST and a NMOST and an increase of 1/f noise spectral density. The advantage of using PMOS transistors for low noise properties is fading away as the process feature size shrinks. The problem of 1/f noise reduction techniques has been addressed in Chapter 5 and Chapter 6.

3.4.3. Noise optimization through W- scaling of MOS transistor circuits. Taking into account practical limitations it turns out that to preserve the dynamic range of analog circuits, the power dissipation has to increase when voltage supply is down-scaled. At low supply voltage it is important to have an optimization procedure for power [9]. Consider the following set of parameters important for a MOS transistor biased in saturation and strong inversion.

40

First design a circuit to satisfy the DC and AC constraints and afterwards, for noise and offset considerations, scale up the widths of the transistors with a factor n, the lengths L are kept unchanged, the capacitances are scaled up a factor n, the resistors are scaled down with a factor n and the supply voltage is left unchanged. The time constants of the circuit are also not changed. As a consequence, the current in the devices will increase n times, the voltage drops on transistors and resistors remains the same but power, noise, offset and area will change. The power and the area are increasing with a factor n. The noise power spectral densities for the white and 1/f noise decreases a factor n and the offset decreases with a factor n and Therefore, improving the circuit for noise, there is an improvement in matching as well. For current processing circuits, noise currents are more important and one has to refer to PSD of current noise and current matching of two transistors having the same drive voltage:

Consequently, by W up-scaling, matching gets better but noise properties are getting worse. However, the DR for current processing increases with the same scaling factor n as long as the power of the signal increases with a factor n2 and the power of the noise with a factor n. The W scaling is a method to travel along the analog limit for different S/N ratios. However it gives no clue whether the design is close to fundamental limits or not. For this, one should know how far away from the fundamental limits the actual design is. For optimal design, practical limits have to be considered for several alternative circuits. The strategy is to use the architecture which is closer to the fundamental limits. Once the best circuit is known, scaling the design according to W scaling allows to find the best trade-off between power, speed and dynamic range to fit the specifications of the design.

3.4.4. Noise driven power consumption for elementary stages Power estimations based on the simple model described above are far away from the actual power consumption of analog circuits. The forthcoming section presents a general theory for power consumption of elementary stages based on noise and accuracy. Optimal design from power point of view is being discussed which provides the background for implications of noise and mismatch on the performance of analog systems.

41

3.4.5. Voltage processing circuits One of the basic voltage processing stages is the inverting amplifier shown in fig.3.6. The closed loop gain of the circuit is determined by ratios of resistors well controlled over process variations. The frequency response of the amplifier is given below:

Considering the transconductance of the transistor larger than and the low frequency loop gain is defined only by the ratio In this case, the power spectral density of the output noise can be found from the input power spectral density and the gain The noise generated by PMOS transistors can be neglected for large gains G.

Here, we can assume a negligible contribution of the white noise generated by the resistors compared to the noise generated by the transistor e.g. choosing large values for G and small values for R1. Denote BW the bandwidth of the amplifier The noise power at the output can be determined by using the noise bandwidth approach:

42

The voltage swing is limited by the saturation voltages and of the PMOS and NMOS transistors to The dynamic range at the output is found by dividing the power of the signal to the noise power:

In conclusion, the DR of the stage decreases for low power supply voltages and for large gains. When the term in parenthesis can be approximated with one. At low supply voltage it is a second order effect decreasing further the DR. By multiplication of DR with G*GBW and using we get:

In eq.(3.22) P is the power needed to bias the gain stage The total performance of the amplifier is only dependent on the chosen bias point of the stage, some technology constants and is independent of transistor sizes. In a voltage processing stage, and can be chosen independently as long as the supply limits are not trespassed. The total performance of the amplifier can be maximized by lowering This corresponds also with the requirements to get low offsets as it will be explained in section 3.5. The minimal value of in the saturation region is the saturation onset, such that where represents the thermal voltage (see [18]). Accordingly, (3.22) becomes:

This ratio can be considered as a figure of merit for this stage where all important design parameters are present. The required power consumption will be fixed for a given dynamic range, gain and gain-bandwidth. Therefore, the minimal power consumption of this stage biased in strong inversion when is:

When biasing the stage in weak-inversion the transconductance remains the same and the minimum power consumption for the same requirements is:

43

In both situations decreasing the power supply voltage, power will increase while keeping the same DR*G*GBW product. Fig.3.7 shows a voltage amplifier with differential stage and feedback. To make the gain at low frequencies dependent only of the ratio of the two resistors, the transconductance of the transistors M1 and M2 should be made larger than and Due to the single ended output and doubling of the input noise spectral density, the trade-off between DR and G*GBW is found to be

Consequently, the minimal power consumption of this stage biased in strong inversion will be:

The power consumption compared to the single transistor voltage amplifier has been increased four times. The efficiency of this stage is worsened due to the single ended output and differential input. This adds extra noise without the possibility of having large swings like in a differential output case. Minimal power in weak-inversion will be the same:

44

Fig.3.8 shows an operational transconductance amplifier (OTA) with differential stage and active load. This OTA is commonly used in many designs involving operational amplifiers. It also appears in some of the designs from the next chapters. Assume that OTA has been configured as a follower and the load capacitance at the output is The GBW product of the stage depends on the transconductance of the input stage and the load capacitance For accuracy reasons the input stage has been biased in weak-inversion. The GBW of the OTA is:

The power spectral density of the input voltage noise can be found from:

where NEF represents the noise excess factor. For low noise, the transconductance of the input pair has to be larger than the transconductance of the active load. The noise excess factor NEF is close to unity in this situation. The DR at the output in a follower configuration is:

The product DR*GBW does not depend in this case on due to the weak inversion biasing of the input transistors. As a minimum limit of power for the OTA in a follower configuration (G=1) we have:

45

The same result holds true for strong inversion. A robust design of the OTA requires phase margins larger than 45°. The second pole of the OTA can be found from:

The phase margin condition requires a value for of about and that is why we can still use the equivalent bandwidth approach. When comparing the OTA case with G=1 and the case in fig.3.7 it seems that minimum power consumption in both cases is the same. However, in the OTA case configured as a follower the distortion is higher due to the lack of a rail to rail input. The voltage swing will be lower for the same harmonic distortion. That is why, the power efficiency of the OTA configured as a follower is worse when compared to inverting amplifier from fig.3.7 with G=-1. Fig.3.9 shows a feedback amplifier with an OTA. If G denotes the low frequency gain of the amplifier, the gain-bandwidth product of the amplifier can be found from the input transconductance and the output load capacitance The input stage is biased in weak inversion with a current source Denote the current efficiency of the input stage and the total current needed to bias the opamp. The gain-bandwidth product GBW is:

Following the same pattern like in the previous case, the minimum power needed to bias this amplifier is found to be:

46

The higher the power efficiency of the input stage, the lower the power coonsumption. When G=1 and this circuit degenerates in the previous case.

3.4.6. Current processing circuits Consider the basic current amplifier from fig.3.10. The input current is amplified with a factor G by the output transistor M2. The gain G is set by aspect ratios without the need for large output resistance transistors. The transfer of the current amplifier shows the presence of a zero at high frequencies due to feed-forward capacitor and a pole:

The pole of the amplifier is determined by the capacitance by neglecting other capacitances present at the input node. Fig.3.11 shows the frequency transfer of the current amplifier. The gain G at low frequency depends only on aspect ratios. Tuning the current IB, the dominant pole and the zero shifts along the frequency axis keeping the same relation between the first pole, GBW and the zero. Therefore, it is possible to change the GBW of the amplifier without changing the gain. The product G*GBW is not constant like in the case of voltage amplifiers [18]. In the case of a large gain G, the noise at the input is determined only by the transistor M1 and the PMOS current source. Assuming that the mobility factor of the carriers of a NMOS is 3 times larger than the mobility factor of the carriers in a PMOS, the power spectral density of the noise related to the input is:

47

Within the assumption that white noise is dominant and the zero positioned at high frequency, the output power spectral density and output noise can be determined from:

The noise power can be found from the noise power spectral density SIout by integration over the positive frequencies or by using the noise bandwidth approach:

Hence, one can find the dynamic range at the output of the current amplifier, defined as the ratio between the power of the signal current and the power of the noise current. The transistors and are biased in strong inversion. If a current modulation index mi is considered such that distortions are sufficiently low, then the DR is:

For any type of current processing circuits the power supply voltage and the gate drive voltage cannot be chosen independently. Increasing the input current, the gate voltage of M1 is pulled up and at maximum will reach the voltage where is

48

the saturation limit of the PMOS current source transistor. Now, we can relate the quiescent gate drive voltage to the maximum value limited by the supply:

The extra constraint from (3.41) shows that and cannot be chosen independently for this case. The dynamic range can be rewritten as a function of the supply voltage:

Therefore, the lower the supply voltage, the lower the DR of the amplifier. The DR can be increased by increasing the capacitance and/or the modulation index The term containing at denominator can be regarded as a second order effect meant to decrease the DR for low supply voltages. For large gain factors G, the bias power can be approximated with and the factor of merit for this amplifier will be:

As a second order effect, at low supply voltages the efficiency of the current amplifier decreases and we need to use more power in order to keep the same DR*GBW product as explained below:

The different performance specifications of a current amplifier like DR, GBW and power are linked and depend on technological and physical constants. This simply shows that in current or voltage mode circuits one cannot get high DR at high speed without paying in additional power. The designer cannot choose the different performance specifications independently. A special case is the W scaling. By W scaling the circuit, the DR increases at the expense of power but keeping the GBW of the amplifier constant. The same methodology can be applied for other current-mode circuits [33], [34], [35], [36], [37].

49

3.4.7. Sampled data applications The results obtained in the previous section can be generalized to sampled data circuits. Sampled data analog circuits like switched-capacitors and switched-currents are subject to the same trade-off found in continuous time circuits.

3.4.7.1. Switched-capacitors charge summing amplifier One of the most general configurations in switched-capacitors circuits is the charge summing amplifier with sample and hold amplifier at the output illustrated in fig.3.12. The results obtained for this amplifier can be used for switched-capacitor integrators. The amplifier is actually a differential OTA with common-mode control. A simple analysis shows the low-pass character of the amplifier and the S/H circuit. Denote the input charge, the sampling frequency and the output differential voltage of the first amplifier. For two clock cycles 1 and 2, the output of the first amplifier represents an amplified version of the input charge with a low-pass character:

The second amplifier is a S/H amplifier with a low-pass effect on the output of the first amplifier. If denotes the differential voltage at the output of the S/H, then:

50

To simplify our discussion, consider only the charge amplifier with input capacitances and the simplified switching approach as shown in fig.3.13. The reference voltage has a value of The main sources of noise are discussed in the following section.

a. Switch noise Every switch in the configuration has a finite on resistance which generates white noise. This wide-band noise is being sampled on the corresponding capacitor which limits also the noise bandwidth. The two-sided power spectral density of the voltage noise sampled on the capacitor is [19], [20]:

After low pass filtering in a bandwidth sampled switch noise has a value of:

This noise sampled on

the baseband, the noise power of the

is amplified at the output of the amplifier:

51

b. Noise of the OTA At the output of the first OTA we have two noise components due to the equivalent noise voltage “seen” at the input of the OTA. There is a direct noise component at the output transferred by the low frequency gain (1+G). Another noise component comes from the thermal noise of the OTA folded back into the baseband due to undersampling of the input capacitor

Direct noise If the thermal noise is band limited at the output to the thermal noise generated by the OTA has a power of:

the direct component of

Undersampled noise The thermal noise component of the OTA is bandlimited by the OTA. The sample frequency is lower than the GBW frequency of the OTA for settling considerations. For fast settling we need undersampling factors of about 10. Therefore, the extra white noise bands are increasing the baseband noise with a factor 10 by folding back the thermal noise.

This is the largest noise component existent at the output of the OTA. Compare now the folded back noise to the switch noise. Given the values of the capacitor in range and the value of the input transconductance of the OTA in order of few hundreds of it is the folded noise which dominates over the switch noise from (3.51). The noise and power analysis from reference [21], considered as a reference for switched-capacitor circuits has ignored the folded back component of the noise. Compared to the continuous time case, the extra undersampling factor increases noise. The settling requirement makes the noise properties of the switched capacitor worse when compared to the continuous time approach. The S/H amplifier has an output noise which can be found from (3.51) when Hence, the theoretical transfer function of the S/H becomes unity and the same procedure can be applied for it.

c. Settling time As an intermediate step towards power computation, the settling time of the switched-capacitor amplifier is being determined from fig.3.14. The settling time can be found from the feedback factor of the amplifier and the unity gain frequency. From fig.3.14 the feedback factor of the amplifier is found:

52

Given the transconductance of the input stage

the unity gain frequency is:

Denote the current efficiency of the input stage. From (3.52) and (3.53) we can find the theoretical settling time constant as:

The input stage of the OTA has been biased in weak inversion. In sampled data circuits the power trade-off involves instead of GBW. Considering only the undersampled noise from (3.51) the trade-off is:

At limit which is valid also for switched capacitors filters based on bilinear transformation. The minimum power of the SC amplifier is found from (3.55):

53

It is not surprising to discover the resemblance between (3.56) and (3.35) which makes the connection between sampled data circuits and continuous time circuits.

3.4.7.2. Switched-currents applications The memory cell from fig.3.15 is the basic element in switched currents amplifiers, delay elements and integrators [22], [23]. For simplicity, assume a first order behavior of the memory cell. The theoretical settling time constant is where represents the transconductance of the memory transistor. For settling reasons, the time constant should be about ten times larger than the Nyquist sampling period. At the end of phase 1, the voltage across the capacitor C is stored together with a noise voltage and a voltage error due to the charge injection from the switch. The noise on the capacitor C is due to the intrinsic noise of M1 and the noise generated by the switch ON resistance. The noise variance on the capacitor generated by the noise current source of M1 is 2kT/3C given the noise bandwidth approximation. This noise on the gate of M1 gives an output current noise with variance:

This noise is sampled again on the gate of M2 and gives a noise voltage on the transistor M2 with a variance of 2kT/3C. The total voltage noise variance on the gate of M2 will be 4kT/3C which generates at the output of M2, a current noise with a power of:

Given the undersampling effects on the capacitor C the noise will be increased with a factor and therefore the dominant noise component it is not the direct noise of the transistors but the undersampled noise. Settling reasons impose an undersampling factor of about 10 and the folded noise in the baseband is:

54

Given the modulation index using again eq.(3.41) we get:

the saturation limit

of the current source

and

The minimum power consumption of the memory cell can be found by neglecting the last term from (3.60):

The power efficiency of the SI memory cell is low when compared to continuous time current amplifier. The band-limiting action for the noise is performed here only by memory capacitor C. That is why the noise is integrated in a large bandwidth which gives a large amount of noise. The SI memory cell can be used to generate a large class of switched current circuits like amplifiers, integrators and delay cells [24], [25], [26]. Fig.3.16 shows a possible application of the memory cell, a SI amplifier (lossy integrator). Although this integrator suffers from charge injection it can be used as an example to illustrate our theory. The damped integrator contains an extra feedback stage M3 weighted with a factor 1/G where G represents the low frequency gain of the amplifier/damped integrator. To understand the behavior of the circuit we have to consider the currents through the transistors M1 and M2 in the clock cycles and

55

During the phase

the relationship between the output current and

is:

Hence, the transfer function of the circuit is found from the Z-transform of (3.62), (3.63) and (3.64):

By multiplying the denominator and the numerator of H(z) with under the low frequency approximation the transfer function and the cuttof frequency of the amplifier are:

If the ratio between the transconductances of the NMOS transistors and their PMOS biasing counterparts is and the transconductance of the transistors M1 and M2 is the current noise PSD related to the input is found to be:

The noise bandwidth is larger than and the power of the noise at the output due to fold-over effects is found from (3.67) the transfer function and the undersampling ratio. The quiescent value of cannot be chosen independently of supply. Given the settling time the current efficiency of the amplifier and using (3.41) we have:

The minimal power consumption of the switched-currents amplifier is found when

56

3.4.8. Power consumption and power supply voltage down scaling From previous section appears that scaling down the supply voltage, power has to increase in order to keep the same performances. The question is if there are circuits less sensitive to down scaling. In order to answer this question consider the power consumption for a voltage or current-mode circuit either continuous time or sampled data.

Scaling down in order to keep the same DR*GBW product, power has to increase faster in voltage-mode circuits to compensate for power supply down scaling. The explanation for this result comes from the nonlinear relationship between voltages and currents in a current mode circuit whereas in voltage-mode circuits the relationship is linear [see eq.(3.41)]. Similar conclusions will be found in the next paragraph.

3.5. From fundamental limits to practical limits. Mismatch related power Another requirement for some of the analog signal processing circuits is related to the amount of offset they generate. Mismatch causes time independent random variations in the properties of two identically designed devices [12]. The errors produced by mismatch can be divided into systematic and random. If necessary, the systematic errors can be corrected in the design phase. To overcome the random errors, we have to use more power and intuitively it should be a connection between the two. Noise and mismatch can be treated in the same way by considering the mismatch as noise at very low frequencies. In reference [10] it is shown that Speed*Accuracy/Power ratio is fixed by technological constants meant to express the matching figures of a technology. For some applications, the impact of matching on the power required for a given speed and accuracy is even higher than the impact of noise on the power required for a given speed and dynamic range. This is simply because the variance of the noise is about two orders of magnitude lower than the variance of the offset voltages and currents. This is the case of parallel signal processing when the mismatch between the signal processing branches can influence the accuracy of the system [27], as it is the case of A/D and D/A converters [see Chapter7] and some filter applications [see Chapter 4].

3.5.1. Matching in weak inversion and strong inversion A transistor can be biased in different ways by choosing the dependent variable as current or voltage. For voltage biasing, the gate-source voltage of the devices is the same and current is the dependent variable. For current biasing, the current in the

57

devices is the same but the voltage is the dependent variable. We can find the spread of the dependent variable from individual offset contributions. It is possible to show [10] that mismatch is dominant for nowadays sub-micron technologies:

For deep sub-micron technologies mismatch will improve (fig.3.2) and it is expected that mismatch will become dominant for (see ref. [10]). If the dependent variable is current, the accuracy will increase at higher gate drive voltages. This explains why current-mode circuits should be biased deep in saturation for best accuracy. This is in contrast with voltage-mode circuits where the best accuracy is obtained in weak-inversion.

3.5.2. The Accuracy*Speed trade-off The effect of mismatch on power consumption can be discussed from the Accuracy*Speed trade-off. The relative accuracy of a voltage or a current processing circuit is determined by the maximal input signal RMS value and the value of the offset voltage or current respectively [10]:

Take for example the current amplifier from fig.3.10. The offset current related to the input can be found from:

For a modulation index of the stage

the input RMS current is

The power consumption of the stage is

is:

and the relative accuracy

and the Accuracy*Speed trade-off

58

In conclusion, the total performance of the amplifier is dependent on technology constants, the bias point of the stage and it is independent of scaling. We want to have large gains at high speed and high accuracy at low power consumption. That is why we want to maximize the right hand side term. The extra constraint from (3.41) shows that and cannot be chosen independently in this case. From (3.41) and (3.75) we get:

Eq. (3.76) shows how we can trade one specification for another. The figure of merit of the amplifier depends on physical constants and some technology dependent terms. The supply voltage and the topology of the amplifier are also involved in the trade-off. As a second order effect, by reducing the supply voltage, we have to increase the power consumption to have the same product. The minimal power consumption of this stage derived from accuracy reasons is found for the ideal case when

An important conclusion can be drawn. For a given speed, gain and accuracy, matching requirements give extra boundaries on the minimal power. This limitation is stronger than the physical limitation imposed by the effect of the thermal noise, given the levels of noise and offsets. Some of the examples considered in section 3.4. have been analyzed in reference[10] with regard to accuracy. Strong inversion or weakinversion behavior can be treated in the same way. In Table 3 we have presented the comparison between power consumption from dynamic range considerations versus power consumption derived from accuracy considerations. In both cases, power in voltage-mode circuits will increase faster than power for current-mode circuits when scaling down the power supply and keeping the same circuit performance. The strong inversion voltage-mode circuits from Table 3 will be biased at for the best performance. The same analysis can be carried out for weak-inversion operation. In the sampled data case, accuracy will be limited by charge injection. That is why results are not provided.

59

60

3.6. Power estimations in continuous time filters In the context of high frequency applications continuous time filters have an advantage over sampled data filters when power consumption is the important issue [30], [31], [32]. Apart from power overhead from clock circuitry, we need expensive amplifiers with large GBW compared to the sampling frequency for good settling behavior. There are many ways to realize a filter. In the video frequency range and above, the most employed methods are the cascades of biquads and first order sections, gyrator based filters and leapfrog simulation of ladders. Power estimations in gyrator based filters have been addressed in [28] and [29]. DR and power estimations for integrator based designs have been addressed in [7] where only the power of the output stage of the active part has been considered. In this section power estimations in cascade approach and leapfrog simulation of ladders approach are presented. The power involved in this estimations is the power needed for biasing of the complete active part. High end applications require class A operation for low distortion figures. In the following estimations, we will confine the analysis to this requirement. The estimation of power is based on DR optimization presented in [7]. Therefore, the starting point is an already DR optimized structure following the procedure from the same reference. In the state-space representation a n order filter consists of n integrators [38] and the state equations of the filter seen as a state space system are:

In (3.78), A,B,C,D are matrices, D is a scalar, and are the input and output variables. Fig.3.17 shows the state-space representation of the filter without considering the scalar D. The transfer function of the filter is computed from:

The eigenvalues of the matrix A are the poles of the filter. Besides, the elements of the state matrix A are related to important parameters of the filter like the input power spectral densities of the noise at the input of every integrator.

61

3.6.1. Power estimations for a high-Q biquad A first order filter section can be treated in a simple way by following the methodology of section 3.4. Therefore we are discussing only second order sections for the cascade approach. A biquad is a filter with a second-order transfer function H(s):

where Q and are the quality factor and the central frequency of the biquad. In the case of bandpass filters realized with biquads, the coefficient is zero. Once the state matrix of the biquad is known, Q and are computed from:

The assumption is a high quality factor Q of the biquad. To estimate the necessary power to bias the biquad we have to optimize first the DR. The optimization procedure has been addressed in [7]. Under the assumption of equal capacitance design, the maximum DR can be found to be:

Optimal DR depends on the maximum effective voltage which can be defined in relation to -3dB compression point of the filter, the noise excess factor of the transconductor NEF, the quality factor of the biquad Q and the integration capacitance of the integrators C. When is multiplied by the central frequency of the biquad we get:

By using the geometric and arithmetic mean inequalities we get the following inequality involving the trade-off:

In the case of Gm-C filters

and therefore for equal capacitance design:

62

The transconductors used in the biquad can be realized in various ways. We are limiting the discussion to some examples, based on the fact that in submicron technologies only few architectures can be used to get high performance.

a. Operation in strong inversion and are physical transconductances. For strong inversion operation and and are the bias currents of the two transconductors. From the power supply, a fraction of the total current is being drawn by the biquad. Once we know the time constants associated with the biquad, the relationship between and is known. Assume and a safety margin of from the negative rail and from the positive rail at the output of the transconductor necessary to have full linearity. Due to the relationship between and :

By substituting in (3.74) and using the values of the transconductances the product is:

and

For comparison sake with the previous results an equivalent effective gate voltage has been used:

is an equivalent effective gate voltage and is a function of the effective voltages of the transconductors. If equal effective voltages are assumed and saturation onset operation, then From (3.88) we find the trade-off between optimal dynamic range of the biquad and its central frequency for a given supply voltage and a given power needed to bias the biquad.

The power consumption of a biquad increases linearly with the quality factor of the biquad Q. That is why, high Q biquads need large biasing power when large Q and large products are involved.

63

b. Operation in weak inversion The case of a weak inversion transconductor or bipolar transconductor is treated in a similar manner. Now, the transconductances are:

for weak inversion transconductor which degenerates in bipolar case for n=1. Following the same procedure a similar relationship with strong inversion case is found. The equivalent effective voltages of the input transistors of the transconductor are replaced now with thermal voltages

c. Transconductors with degeneration resistors Degenerated transconductors (fig.3.18) can be used to increase the linearity of the input stage. Another positive effect is the increase of the input window of the transconductor. The version (fig.3.18.a) has larger noise when compared to the T version. The T version (fig.3.18.b) has only one current source. Its noise is a common mode noise and therefore rejected in the differential output. This is paid by a lower efficiency in terms of power due to the voltage drops on the degeneration resistors and the effect of lowering the effective transconductance of the stage. For a degeneration resistor the equivalent transconductance of the stage becomes smaller due to series feedback. If we denote the voltage drop on the series resistance the transconductance of the stage and the bias current, then:

64

Hence, in the trade-off the denominator of (3.93) will appear and the effect will be a decrease in the power efficiency. For simplicity assume equal effective gate voltages at saturation onset The minimal power in this case can be found from (3.92) and (3.93):

3.6.2. Power estimations for a bandpass filter The power estimation for a biquad can be extended now to the case of a bandpass filter. A bandpass filter with central frequency and the -3dB bandwidth is obtained from a low-pass equivalent filter with bandwidth by using the biquadratic transformation:

The bandpass filter can be constructed by replacing every integrator in the lowpass filter by an adequate biquad. Given the order of the lowpass prototype n, the order of the bandpass filter is 2n and the number of active elements is 2n. The lowpass filter can be derived from a normalized lowpass filter using the frequency transformation For computing the power, firstly we need to optimize the DR of the filter. According to reference [7], in a bandpass filter derived from a normalized lowpass equivalent filter (in the case of equal capacitance design) the optimal dynamic range follows the inequality:

Optimal DR depends on the maximum effective voltage of the transconductor. The frequency comes from the normalized lowpass filter which has a noise bandwidth:

65

In the case of high Q filters, the noise bandwidth can be approximated with optimal dynamic range becomes:

and

The central frequency of the filter can be considered as the ratio between an equivalent transconductance and the capacitance C. It can be regarded as a linear combination of individual time constants involved in the filter

If the transconductors have input stages biased in strong inversion from a current source then, for a given current efficiency we can relate the transconductance to the total current of the filter

Hence, the central frequency of the filter becomes:

The trade-off

as a function of power is found from (3.98) and (3.101):

When all transconductors are biased at the bandpass filter is found from:

the minimum power needed to bias

The same discussion can be extrapolated to weak-inversion operation and degenerated transconductors. In conclusion, we have shown how to find the minimal power in the case of a biquad and a bandpass filter. The power involved in this section is the bias power, considering only class A of operation. The minimal power consumption depends on the product, the supply voltage, the quality factor of the filter,

66

the noise excess factor of the transconductors, and their current efficiency. It is important to have transconductors with low noise excess factors and high power efficiency capable of large voltage swings with high linearity. The same analysis can be extended to low-pass filter. The difficulty in this case comes from the impossibility to approximate the noise bandwidth from (3.97).

3.7. Conclusions This chapter deals with power considerations in submicron analog CMOS. The context in which analog functionality has to be integrated is a submicron, digital process optimized for digital applications. The consequences on analog requirements have been discussed. The roadmap for scaled down processes for digital applications point to lower and lower supply voltages. For analog functions, the reduction of supply voltages has a negative influence on dynamic range and power dissipation. It is shown that low voltage is incompatible with low power when analog signal processing circuits are being considered. The fundamental limits for low-power in analog are asymptotic limits. They are combining in one simple equation power, S/N ratios and speed. There are no restrictions regarding voltage swings, circuit topology, noise generated by active circuits, the process constants and linearity. That is why relative comparisons between different designs are difficult to be made based only on the fundamental limits. A designer wants a certain dynamic range and speed with a given accuracy, gain and linearity. Low voltage and low power are imposed by the application and the mixed level context. It would be useful to know practical limits of power in order to make choices between different possible solutions considering the active power, voltage supply, circuit topology, noise and linearity. Starting from general considerations and simple circuits, it is possible to prove that DR*Speed product is limited by power, topology and supply voltage regardless if the circuits are continuous time or sampled data, current-mode or voltage mode. Most of those circuits are extensively used in the designs presented in Chapter 4, Chapter 5, Chapter 6 and Chapter 7. Only white noise is taken into considerations. We have shown that scaling down and keeping the same DR*GBW product, power has to increase faster in voltage-mode circuits to compensate for power supply down-scaling. The accuracy requirements give extra boundaries on the minimal power consumption for a given speed, gain and accuracy. This limitation is stronger than the physical limitation imposed by the effect of the thermal noise given the levels of the noise and the levels of the offsets. That is why matching driven power consumption has been considered. By scaling down and keeping the same product, power has to increase faster in voltage-mode circuits to compensate for power supply down-scaling. The same result has been obtained from the noise driven power consumption analysis.

67

REFERENCES [1] A. P. Chandrakasan, S. S. Sheng and R. Brodersen, “Low-power CMOS digital design”, IEEE J. Solid-State Circuits, vol. 27, pp. 473-484, Apr. 1992. [2] E. A. Vittoz, “Low-power design: Ways to approach the limits”, ISSCC 94, pp. 1418. [3] E. A. Vittoz , “Low-power limitations and prospects in analog design”, Advances In Analog Circuit Design Workshop, Eindhoven, Mar. 1994. [4] R. Hogevorst, J. H. Huijsing, K. J. de Langen and R.G.H. Eschauzier, “Lowvoltage low-power amplifiers”, Advances In Analog Circuit Design Workshop, Eindhoven, Mar. 1994. [5] R. Castello, F. Montecchi, F. Rezzi and A. Baschirotto, “Low voltage analog filters”, IEEE Trans. Circuits Syst -I., vol.42, Nov. 1995 . [6] G. Groenewold, “Optimal dynamic range integrators”, IEEE Trans. Circuits SystI, vol.39, No.8, Aug. 1992. [7] G. Groenewold, “Optimal dynamic range integrated continuous time filters”, Delft University Press, ISBN 90-6275-755-3 / CIP , pp. 140-143, 1992. [8] M. Yotsuyanagi, H. Hasegawa, M. Yamaguchi, M. Ishida and K. Sone, “A 2V, 10b, 20Msamples/s, mixed-mode subranging CMOS A/D converter”, IEEE J. SolidState Circuits, vol. 30., No. 12, Dec. 1995. [9] B. Nauta, “Analog CMOS low-power design considerations”, Low power-low voltage workshop at ESSCIRC’96, Neuchatel-Switzerland, Sept. 1996. [10] P. Kinget and M. Steyaert, “Analog VLSI integration of massive parallel signal processing systems”, pp.21-45, Kluwer Academic Publishers, ISBN 0-7923-9823-8, 1997. [11] Semiconductor Industry Association, “The National Technology Roadmap for Semiconductors” 1997, pp. 46-47. [12] M. Pelgrom, A. Duinmajer and A. Welbers, “Matching properties of MOS transistors”, IEEE J. Solid-State Circuits, vol. 24., No. 5,pp. 1433-1439, 1989. [13] A. Pavasovic, A.G. Andreou and C.R. Westgate, “Characterization of subthreshold MOS mismatch in transistors for VLSI systems”, Analog Integrated Circuits and Signal Processing, no.6, pp.75-85, 1994. [14] J. Bastos, M. Steyaert, R.Roovers, P. Kinget, W. Sansen, B. Graindourze, N. Pergoot and E. Janssens, “Mismatch characterisation of small size MOS transistors”, in Proceedings of the IEEE International Conference on Microelectronic Test Structures, pp. 271-276, March 1995. [15] J. Bastos, “ Matching characterization for precision analog design”, PhD thesis Katholieke Universiteit Leuven, Leuven, Belgium, 1996. [16] B. Nauta and G.Hoogzaad, “How to deal with substrate noise in analog CMOS circuits”, European Conference on Circuit Theory and Design, Budapest, September 1997. [17] C. Enz, “Device modeling for low-voltage and low-current circuits” ,Advance engineering course on low-power/low-voltage IC design, pp.52-53, Lausanne, Switzerland, July, 1994. [18] R.F. Wassenaar, “Analysis of analog CMOS circuits”, PhD thesis, University of Twente, Enschede, 1996, ISBN 90-9009960-3. [19] K.R. Laker and W.M.C. Sansen, “Design of analog integrated circuits and systems”, McGraw-Hill, Inc., 1994, pp.692-695, ISBN 0-07-036060-X

68

[20] C.A. Gobet‚ “Spectral distribution of a sampled lowpass filtered white noise”‚ Electron. Lett.‚ vol.45‚ no.1‚ pp.307-316‚ 1974. [21] R. Castello‚ P.R. Gray‚ “Performance limitations in switched-Capacitor filters”‚ IEEE Transactions on Circuits and Systems‚ Vol. CAS-32‚ no.9‚ Sept. 1985. [22] C. Toumazou‚ J.B. Hughes and N.C. Battersby‚ “Switched-currents: an analogue technique for digital technology”‚ IEE Peter Peregrinus Ltd.‚1993‚ ISBN 0 863412947 [23] J.B. Hughes‚ I.C. Macbeth and D.M. Pattullo‚ “Switched-current filters”‚ Proc. IEE‚ Pt. G‚ vol.137‚ pp. 156-162‚ April 1990. [24] J.B. Hughes‚ I.C. Macbeth and D.M. Pattullo‚ “Second generation switchedcurrent circuits”‚ in Proc. IEEE International Symposium on Circuits and Systems‚ pp. 2805-2808‚ 1990. [25] J.B. Hughes‚ I.C. Macbeth and D.M. Pattullo‚ “Switched-current system cells”‚ in Proc. IEEE International Symposium on Circuits and Systems‚ pp. 303-306‚ 1990. [26] J.B. Hughes‚ I.C. Macbeth and D.M. Pattullo‚ “New switched-current integrator”‚ Electronics Letters‚ vol.26‚ pp.694-695‚May‚ 1990. [27] M. Pelgrom‚ “Low-power high-speed AD and DA conversion”‚ in Low-power‚ low-voltage workshop (ESSCIRC’94)‚ Sept. 1994. [28] J. O. Voorman‚ Continuous Time Analog Integrated Filters in Y.P. Tsividis and J.O. Voorman‚ Integrated Continuous Time Filters. New York: IEEE press‚ 1993. [29] B. Nauta‚ “A CMOS transconductance-C filter technique for very high frequencies”‚ IEEE J. Solid-State Circuits‚ vol. 27‚ pp. 142-153‚ Feb. 1992. [30] R. Castello‚ “Low-voltage SC and CT filters”‚ Electronic Laboratories Advanced Engineering Course On Low-Power/Low-Voltage IC Design‚ Lausanne‚ June 1995. [31] M. Steyaert‚ J. Crols‚ S. Gogaert‚ and W. Sansen‚ “Low-voltage analog CMOS filter design”‚ IEEE Int. Symp. Circuits Syst. 1993‚ vol.2‚ pp.1447-1450‚ May 1993. [32] Y. P. Tsividis‚ “ Integrated continuous-time filter design-an overview”‚ IEEE J. Solid-State Circuits‚ vol. 29‚ pp. 166-176‚ Mar. 1994. [33] K.C. Smith and A. Sedra‚ “The current conveyor: A new circuit building block”‚ Proc. IEEE‚ vol. 56‚ pp. 1368-1369‚ 1968. [34] A. Sedra and K.C. Smith‚ “ A second generation current conveyor and its applications”‚ IEEE Trans. CT-17‚ pp. 132-134‚ 1970. [35] R. H. Zele‚ D. J. Allstot and T. S. Fiez‚ “Fully balanced CMOS current-mode circuits”‚ IEEE J. Solid-State Circuits‚ vol. 28‚ pp. 569-575‚ May 1993. [36] S. L. Smith and E. Sanchez-Sinencio‚ “Low voltage integrators for highfrequency CMOS filters using current mode techniques”‚ IEEE Trans. Circuits Syst-II‚ vol.43‚ No.l‚ pp. 39-48‚ Jan.1996. [37] S. L. Smith and E. Sanchez-Sinencio‚ “3V high-frequency current-mode filters”‚ Proc. Int. Symp. Circuits Syst.‚ May‚ 1993‚ Chicago‚ IL. pp. 1459-1462. [38] H.H. Rosenbrock‚ “State-Space and Multivariable Theory”. Thomas Nelson and Sons LTD‚ London‚ 1970.

CHAPTER 4 Gm-C integrators for low-power and low voltage applications. A gaussian polyphase filter for mobile transceivers in CMOS. 4.1. Introduction At low supply voltage, the key problem of analog signal processing functions is dynamic range reduction [1], [2]. This is especially severe in mixed mode systems due to the cross-talk produced by adjacent digital functions. For this reason, a key target is to keep the largest possible voltage swing. Bipolar based transconductors can be widely tuned with negligible variation in the voltage [3]. At low supply voltage, this does not impose restrictions on tunability of the transconductors. On the contrary, in CMOS transconductors, large tunability needed to correct for temperature and process variations gives a significant reduction in voltage swing at low supply voltages [3]. The new technologies are optimized towards digital applications and therefore, modern MOST’s, suffer from second order effects like velocity saturation and mobility reduction. New transconductor concepts which do not rely upon the ideal square law of a MOST are needed. Another issue is to achieve large tunability without conflicting with the large swing requirement.

4.2. Large swing and high linearity transconductor The purpose of this section is to investigate the realization of a low voltage, large swing transconductor, in a digital CMOS technology with a constant input window and a large dynamic range over power ratio. The transconductor can be used as a Gm-C integrator for filter applications or, automatic gain control circuits (AGC). Other applications where noise and linearity are important, can be found in converters. This section presents a low voltage large swing transconductor in a 3.3V CMOS digital technology (see [4] [5]) which preserves a constant input window independent of tuning. The transconductance can be digitally adjusted, in coarse steps, and continuously, in fine steps. When used as a Gm-C integrator with high Q

70

requirements, the quality factor of the integrator can be electronically tuned. Total harmonic distortion is better than -50dB for signal amplitudes of 1.8Vpp and power consumption is 1.48mW from a 3.3V power supply.

4.2.1. Gm core principle The Gm core consists of a PMOS input differential pair MP2, MP3 with degeneration resistors R1 and R2 for V to I conversion as shown in fig.4.1. The input transistors are in weak inversion for two reasons: maximal transconductance for a given current and low and voltages needed for large swing. MP2 (MP3) is biased under a constant current given by MN4 (MN5). The feedback loop MN6 (MN7), MN10 (MN11) and MN8 (MN9) forces a constant current in the input transistors. If the loop gain is high, the differential input voltage will be transferred to the conversion resistors R1 and R2. Any variation at the input will be sensed at the gate of MN6 (MN7) and the current of MN6 is divided between MN8 (MN9) and MN10 (MN11). The current which flows in the conversion resistors is a fraction of the current which flows in the transistor MN6. MN10 works in triode region and the value of the output conductance gives the division ratio between MN10 and MN8. In the output transistors of the transconductor, MN12 and MN13, there is a mirrored replica of the converted signal. It is to be noticed that signal currents in MN6 (MN7) are larger in comparison to the signal current which flows in the conversion resistors R1 and R2. In the conventional methods for V to I conversion [6] current is thrown away to obtain tunability.

71

4.2.2. Transconductance tuning Denote and the small signal transconductance of transistors MP2, MN6, MN8 and the output resistance of MN4. If represents the small signal channel resistance of MN10 in the triode region, the loop gain of the feedback loop MN6 (MN7), MN10 (MN11) and MN8 (MN9) is:

Hence, the larger the output resistance of MN4 (MN5), the larger the loop gain and the higher the accuracy of the conversion. Under the assumption that is infinite, we can derive by simple inspection the small signal transconductance of the converter:

For a given the first term in depends only on aspect ratio’s of MN12 and MN6. The second term comes from source degeneration and the nullor effect of the feedback loop. The last term originates from current division performed by MN8 and MN10. The transconductance can be tuned by varying the small signal output conductance of MN10 and/or by changing the aspect ratio of MN12. Tuning R1 was excluded because of as wing-tunability conflict.

a. Fine tuning Fine tuning can be achieved by adjusting the output conductance of MN10 which depends on the effective gate-source voltage and the drain source voltage of MN10:

When Gm_TUNE changes, the loop keeps a constant gate source voltage for MN8 and MN9. The drain of MN10 (MN11) is pulled in the same direction as Gm_TUNE and the output conductance of MN10 will change. Now, one can see the advantage of the method: the voltage drop on the conversion resistors remains the same when Gm_TUNE varies. Therefore, for a constant of MP2 and MP3 the input swing does not change with tuning. When Gm_TUNE varies from 1.8 to 3V the transconductance of the converter can be changed with about (10%) in a continuous way. This is shown in fig.4.2. The transconductance remains the same for an input window of 2Vpp.

b. Coarse Tuning Process spreads require a tuning factor of about 2÷3 for a modern process. This cannot be achieved only from fine tuning the output conductance of MN10. Therefore, a coarse and a fine tuning are required. This can be achieved by switching transistors

72

with different aspect ratios at the output, for a coarse interval, and fine tuning to get transconductances within the coarse interval as shown in fig.4.9. In this way, the transconductance can be tuned between and in ten coarse steps, with a grid of for fine tuning. The smallest transistor has an aspect ratio of 12/1 and the largest transistor has an aspect ratio of 35/1. Accordingly, the transconductance varies in coarse steps from to as illustrated in fig.4.3.

4.2.3. Common-mode circuit The common-mode circuit consists of transistors MP20, MP21, MN22, MN23 and MP24 (fig.4.9). The common-mode output voltage is sensed by MP20 and MP21 and their output signals are added up in the drain of MN22. A current mirror with active load provides common-mode feedback to the gates of MP18 and MP19. The common-mode DC voltage is thus In our case, the common-mode at the output is 1.5V. For input-output compatibility, the input common mode voltage has

73

been set to 1.5V. The differential output swing is limited by the input range of MP20 and MP21. This is about 1.9Vpp for current values of and The GBW of the common-mode amplifier is larger than the GBW of the differential amplifier in order to ensure stability for all frequencies of interest up to the GBW of differential amplifier. This condition is satisfied if is chosen larger than of the voltage to current converter taking into account the same load capacitance for the two amplifiers.

4.2.4. Linearity of conversion In the voltage to current conversion the main sources of non-linearity are the current division and channel length modulation of the output transistors. The input transistor is biased with a constant current and will not give an important contribution on distortion. The THD has been simulated for different tuning conditions. In fig.4.4 the amplitude of the input signal changes from 1Vpp to 2Vpp when Gm_TUNE is zero. Under coarse tuning, at maximum Gm, in the worst case, the THD of the converter is -47dB and below -50dB for amplitudes lower than 1.86Vpp. The harmonic distortion is dominated by odd harmonics due to differential approach.

When Gm_TUNE becomes 3V, at maximum tuning, the non-linearity due to current division increases and at maximum tuning and maximum signal amplitudes THD approaches -46dB as shown in fig.4.5. This can be explained in a simple way by using the current triangle method [7]. For Gm_TUNE=0, the current division is inherently linear, independent of the working region of MN8 (MN10) and MN9 (MN11). When Gm_TUNE is larger than zero, the voltage difference between the gates of MN8 and MN10 gives extra distortion terms in the current division.

4.2.5. AC response and Q-tuning If the transconductor is used as a Gm-C integrator, the frequency response and the phase response are important for determining the quality factor of the integrator. It is expected that using negative feedback, we get extra poles and extra phase shift at

74

GBW frequency caused by them. A simple analysis reveals the existence of a low frequency pole at and a zero at:

and two high frequency poles. In (4.4) Cgs8 denotes the gate-source capacitance of MN8. The condition to have two real poles can be formulated in terms of output resistance of the current source MN4.

There is a trade-off between a high output resistance needed for large loop gain and a relative low output resistance to avoid peaking of the loop. An optimal value for to provide sufficient loop gain is in the order of a few The Gm-C integrator has a GBW of 1MHz. In fig.4.6, simulations show an open loop gain of 70dB. This is sufficient for most applications. In order to make the phase close to 90° for all possible situations given by process spreads, in high Q applications Q tuning is required. However, this is a disadvantage we have to pay for linearity. The quality factor of the integrator can be tuned by using the non-linear capacitance from the gate to the substrate of a MOS transistor. In fig.4.8 Q_TUNE controls the gate-substrate capacitances of transistors MN25 and MN26. This adjustment does not interfere with Gm tuning.

4.2.6. Noise properties The noise contributions of the common-mode circuit are negligible for a differential output. The noise of MN8 (MN9) and MN10 (MN11) can be made sufficiently small.

75

The main noise contributors are MN6 (MN7), MN12 (MN13), MP18 (MP19) and the conversion resistor R1. This has been confirmed with simulations. At the input of the integrator we have an equivalent voltage noise source with a single sided power spectral density [2]:

In (4.6), represents the small signal transconductance of the integrator and NEF the noise excess factor. For this particular case NEF can be approximated with:

In fig.4.7, NEF has been represented as a function of aspect ratios of transistors MN12 and MN6 at different coarse tuning conditions.

76

At maximum transconductance, the noise excess factor is closed to 6. The noise of the transconductor has been optimized by using W scaling. After scaling, simulations show a total in-band noise of Vrms.

4.2.7. Dynamic range and power Consider the unity feedback configuration and the procedure from section 3.4.5 for G=1. Denote the power efficiency of the transconductor related to the transconductance of the input stage and NEF its noise excess factor. The minimal power consumption for a unity feedback configuration when, the power supply is larger than the saturation limits of the PMOS and NMOS cascoded outputs is:

For comparisons with other low-voltage transconductors we need a factor of merit in which dynamic range, THD power and tuning are taken into account. In [8] a factor of merit for transconductors has been defined:

In the factor of merit FOM, represents the maximum rms value of the input voltage and P the total power needed to bias the complete circuit. The figure of merit was defined under the conditions of maximum tuning and total harmonic distortion of about -50dB in worst-case condition for noise excess factor NEF. Given the dynamic range of the transconductor :

the factor of merit FOM equals DR/4KT·P ratio for a noise bandwidth NB of 1Hz. The figure of merit is determined under the following conditions: The transconductance is NEF=6; The rms input voltage for THD=-50dB is 1.41 Vrms P=1.48mW at This results in a figure of merit of about FOM is ten times better than FOM of the transconductor from references [9] and [10] which has a value of and has been implemented in the same technology. The difference comes from the larger input swing allowed in this design and its linearity. In conclusion large voltage swings at low supply voltage is proven beneficial to achieve high dynamic range and large DR/P ratios.

77

78

4.3. Low voltage current Gm-C integrator with high power efficiency The starting point for this section is the integrator shown in fig.4.9 (see also [11], [12]) which is a modified version of the integrator from reference [13]. The reason for using this integrator consists in the low-voltage, high linearity and very high frequency of operation with a high power efficiency. It is compatible with standard digital technology has a high quality factor Q and can work down to 1.5V power supply voltage. For an ideal integrator, the input differential current should flow entirely in the integration capacitance Without any compensation technique, there is always a current flowing in transistors and damping the integrator. Transistors and provide positive feedback compensation for the signal currents flowing in and enhancing the input resistance of the integrator. Theoretically, if matching is assumed, the gain can become infinity when compensation is achieved. The same circuit provides common-mode rejection in an efficient way. Positive feedback is a promising technique for enhancing gain in sub-micron CMOS because current matching in modern technologies improves. Denote the transconductance of the output transistor. The differential gain of this integrator is:

79

When a and b are equal, the differential gain becomes infinity. However, the gain is limited to some 50-60dB due to second order effects. Obviously, there are no parasitic poles in the structure and only one zero due to gate drain overlap capacitance of the NMOST transistors. The structure can be tuned by changing the value of the bias current The quality factor of the integrator depends on the position of parasitic poles and zeros and also on the differential gain at DC. In our situation there are no parasitic poles and the position of the zero is at much higher frequencies compared to GBW as illustrated in fig.4.10. The quality factor of the integrator depends on the low frequency gain of the integrator and the position of the zero:

Accordingly, the quality factor of this integrator can be as high as 100 for normal values of gain. For high-frequency and/or high Q filters it is very important to have large quality factor integrators. In a ladder filter every integrator simulates a reactive element. Then, finite gain means a lossy inductor or a lossy capacitor. For a reactance two-port with a uniform distribution of quality factors in all reactances the losses can be approximated by:

80

For narrow-bands, where can have values as large as 100 or more, the passband deviation is high when the Q factor of the reactances is low. The Q tuning is difficult to achieve for high Q filters. It is important to have by design a high Q integrator in order to simplify the tuning circuit or to eliminate it if possible.

4.3.1. Dynamic range and power Assume a ratio of in transconductance between the NMOS and PMOS transistors and denote the transconductance of a transistor biased at a current level having the same drive voltage as the chain M1...M3. The power spectral density of the current noise at the input is:

Consider a unity feedback configuration of this integrator. After integration we get the total output noise which can be obtained using the effective noise bandwidth approximation:

Now, we can compute the DR knowing the class A operation of the integrator and the necessity to have a modulation index of the current signal less than 1 in order to reduce distortions.

DR can be increased when using large capacitors at the expense of a larger passive area. From another point of view, DR is limited by the supply and modulation index At low voltages we have to scale up capacitors with in order to keep the same DR. In order to keep the same time constants in the filter and the same speed the currents have to scale up and power has to increase to keep the same DR. The DR*GBW of the integrator is found to be:

Hence, the minimal power needed to bias this integrator in a unity gain configuration is found at limit when is larger than

81

The current efficiency of the OTA is lower than the efficiency of the current Gm-C integrator due to the need for biasing the common-mode circuit and the extra current needed to bias the output branch. Now, we can compare the minimal power of the current-mode Gm-C integrator with the minimal power of the OTA-C integrator when the DR*GBW for the two approaches is the same.

Given the values of the modulation index the values and the noise excess factor NEF=6 this yields a factor 3 in power in the favor of current Gm-C integrator.

4.3.2. The linearity of the integrator. Linearity improvement. Consider the mobility reduction in the current term without taking into account the term dependent on The drain current of a MOS transistor can be approximated as:

In fig.4.11, a linearized integrator is being shown. Without linearization transistors M13 and M14 and the voltage dividers the integration principle can be explained in the following way. The input differential current is being converted into a voltage at the gates of the transistors and At the input the impedance level is low but because of the positive feedback ensured by the transistors and the impedance level increases. The input differential current is being forced in the integration capacitors and the output resistance of the input current sources. Theoretically, if a=b, the gain of the integrator is infinity and the current to voltage conversion undistorted. The only possible distortion term comes from the voltage to current conversion performed at the output by the transistors and The large signal voltages on the integration capacitors are and respectively. Denote the output differential current. Without compensation we have a third order distortion term and no second order terms due to the differential symmetry:

By dividing the gate source voltages by and amplifying the current in the compensation transistors by one can find a condition for undistorted transfer in

82

terms of and The voltage division by is performed by the polysilicon resistor dividers R1, R2 and R3, R4. The current amplification by is performed at the output by the transistors and Now we can write the output currents as a function of the effective gate-source voltages:

At the output, the differential current can be written as a function of the individual output currents:

83

By substituting (4.22) in (4.23) and under the extra condition differential current becomes:

the output

As a conclusion, by choosing and such that we have a linear relationship between the output current and the input differential voltage However, in practical situations mismatches between the two differential branches will give extra even distortion terms. The advantage of the method consists in the possibility of choosing different values for and and the dependence of and on ratios. Given the fact that is close to one, than will be larger than one. Another advantage would be that all voltages of the transistors will be about the same and therefore, one can show that any additional term dependent on in eq. (4.24) will cancel out.

4.4. Low-power luminance video filter. Noise driven power The fundamental limits have shown the difference between an analog filter and a digital one when signal to noise ratio and power/pole are taken as variables in the comparison. However, it is not clear for which S/N ratio the transition between an efficient analog filter and a digital filter takes place. According to the previous conclusions, this transition could be somewhere in between 50dB and 60dB which makes difficult to decide whether or not a digital filter is power efficient when compared to an analog filter. The two integrators presented above are used to realize the video filter from Chapter2 in an analog way and to make a comparison in power with the digital approach. The case of study is a luminance input filter and the reason to take such an example relies on the fact that an 8-bit solution will provide a theoretical S/N of about 50dB. This value is sufficient for video purposes. Moreover, it is important to consider the same technology for all realizations to allow a meaningful comparison. Matching in this type of filters is not important. Therefore we are dealing with noise driven power consumption. The analog filter can be realized in different ways: Gm-C, Mosfet-C, Switched-Current, Switched-Capacitors. As we shall see there are extra problems due to the impossibility to open the switches for SC and SI techniques as long as some other techniques like switched-opamp are not employed [14]. Usually, there is a need for a DC-DC up transformer. The extra noise added from undersampling of high frequency white noise into the baseband and the power needed for clocking, makes sampled data filters not adequate for low-power video processing. That is why only Gm-C filters have been considered in this comparison.

84

4.4.1. Specifications and synthesis In order to start the comparison, we need to specify the analog prototype. The requirements are presented in Table 4.1. For a luminance video filter it is important to have a very low pass-band ripple. For this reason, the possible solutions are Butterworth and inverse-Chebyshev filters with a maximally flat amplitude in the pass-band.

It is known that inverse-Chebyshev filters provide a smaller group-delay when compared to Butterworth counterpart. That is why, an inverse-Chebyshev filter has been chosen. The synthesis procedure is given in Appendix 2 and the outcome is the low-pass prototype illustrated in fig.2.13 from Chapter 2. The frequency transfer from fig.4.12 shows a notch at 16MHz and a stop-band rejection of -30dB. The group-delay of the filter lies somewhere between 46ns and 59ns, thus within the specifications.

4.4.2. The study approach The leapfrog simulation of ladders is a systematic approach which can be used in the realization of analog filters. The reason for using this method consists in the low sensitivity property of the transfer with respect to the limitations of gain, quality

85

factors and bandwidth in the active elements. In the lowpass prototype we have transmission zeros difficult to simulate actively. That is why a Norton transformation is needed as depicted in fig.4.13. The signal flow graph follows according to the prototype from fig.4.13 is shown in fig.4.14.

4.4.3. The current Gm-C approach In this approach, we are using current Gm-C integrators from fig.4.9. The integrators have equal unity transconductances and different capacitors. The realization of the filter is shown in fig.4.15. In the signal flow graph the summing nodes are current summing nodes while the state variables and are voltages. The state variables in this approach are all currents. That is why, the state variable equations have been rewritten in a form compatible with currents. The filter is differential and the negative and positive integrators are differentially coupled. The

86

square boxes represent extra output branches, needed to scale the output current of every integrator. Table 4.2 shows the dimensions of the integrator sections. The filter has been simulated and power estimations after simulations are shown in Table 4.3.

The current and the dimensions of the integrators have been scaled according to W scaling such that the dynamic range (THD of -52 dB) of the filter is 50dB.

4.4.4. The OTA-C approach The realization with OTA-C integrators in a balanced approach is shown in fig.4.16. The complexity of this approach comes from the need to realize actively the tank circuit L2, C2. The dimensions of the integrators and power estimations after simulations are presented in Table 4.4. This shows that current Gm-C filter has a better power efficiency in comparison to the OTA-C approach which is already expected from eq.(4.19).

87

When compared to the digital filter described in Chapter 2, the power per pole in the best analog implementation is while in the digital implementation, the power consumption per pole is showing that digital has been taking over the analog implementation in terms of power consumption for the same dynamic range. Extra power can be expected from the tuning circuitry in the analog implementation and from clock circuitry, shift registers in the digital implementation respectivelly.

4.5. Low-power, gaussian, polyphase filter for mobile transceivers. Matching driven power. We have discussed so far applications where noise driven power consumption is dominant. There are filter applications where matching requirements and noise requirements have the same importance, with constraints on power consumption and linearity. Channel selectivity in receivers has been realized until recently, using SAW filters. Those components are external components and therefore integration on chip of selectivity has become a major concern in receivers. From Chapter 3 we already know that selectivity increases the noise power and requires extra power consumption to achieve it. A polyphase filter is an example of a selective filter without the need of using high Q bandpass sections. Here selectivity is rather ensured by using polyphase signals and two low-pass filter sections where matching driven power consumption comes as a variable. Polyphase filters can discriminate between positive and negative frequencies and therefore, using this property, selectivity can be achieved [15]. By using a low power integrator, we are going to show how to realize a polyphase filter needed for image rejection in a mobile transceiver.

4.5.1. The low IF receiver topology and polyphase filters As mentioned before, we want to discriminate between positive and negative frequencies in order to realize on chip selectivity. This is not possible with real signals but with two dimensional signals or complex signals. We can imagine positive and negative frequencies as being phasors rotating in the complex plan in opposite direction [16.]. The complex signals used in a receiver are called polyphase signals which consist of a number of real signals with different phases. A quadrature signal consists of two real signals with phase shift:

88

Based on complex notation it is possible to define operations like multiplication, and convolution for complex signals with multipliers, filters and amplifiers for complex signals. For more details on polyphase signals references [17], [18], [19] and [20] can be consulted. In order to show the connection of complex signals with polyphase filters and low IF receivers, consider fig.4.17 where the low IF concept is shown. A broadband HF filter is used to prevent overloading of the mixers with strong out of band signals. The low noise amplifier (LNA), amplifies the weak signal from antenna to come to a sufficient signal-to-noise ratio. The mixers are downconverting the signal to a low intermediate frequency IF by multiplication with two quadrature signals which can be seen as a single positive frequency The polyphase bandpass filter ensures the rejection of the mirror frequency and provides the antialiasing necessary in the digital signal processor (DSP) which does the final downconversion to baseband and demodulation of the signal. The downconversion spectra are shown in fig.4.18. The wanted signal is multiplied with a single positive frequency at The mirror signal will be mixed down from to and the wanted signal at With a polyphase filter it is possible to discriminate between the negative and positive frequencies and therefore, the mirror frequency will be filtered out. The advantage of this topology consists in the high level of integration and the lack of DC offsets as in the case of zero IF receiver. The second IF is at low frequency and digital signal processing is possible. Different receivers have different specifications and that is why we want to find the specifications for the polyphase filter from the receiver specifications.

89

4.5.2. Specifications The most common standards in use nowadays are DECT, GSM and DCS1800. The specifications in terms of frequency range, selectivity and channel spacing are given in Table 4.5. For further details reference [20] can be used.

The focus of this section is the design of a polyphase filter for a low-IF DECT receiver. In this standard, the channel spacing is 1.7MHz and the signal bandwidth is about 800KHz. The central frequency is chosen at 1MHz whereas the rejection of the filter at 2.3MHz should be at least -16dB.The image rejection should be -16dB and the image is located 2MHz away from the central frequency. In order to achieve the image rejection spec’s also for GSM standards we are requiring an image rejection of better than -40dB.

4.5.3. Filter synthesis In data communications, the group delay specifications and the step response of the filter are very important. The gaussian transfer offers a flat group delay characteristic and virtually no overshoot in the step response. Gaussian filters are presented in Appendix 2. When gaussian approximation is used, a seventh order filter is necessary. That is why the gaussian-to-6dB approximation will be used and

90

therefore a fifth order filter will suffice. The price paid is a deterioration of the group delay and little overshoot which can be tolerated. The transfer function to be synthesized [21] is:

The low pass prototype is shown in fig.4.19. The transformation from a low-pass into a polyphase bandpass characteristic is achieved by using complex network elements as illustrated in the same picture. Every capacitor is replaced with a parallel connection of a capacitor and a frequency dependent negative element. A coil will be replaced by a parallel connection of a coil and a frequency dependent negative element. The result is shown in fig.4.20 with chosen state variables. The signal flow graph SFG or the leapfrog simulation of ladders method is a direct way to convert the prototype into a filter realization. The result is a filter with low sensitivity to mismatch and realizable with transconductors and grounded capacitors. The state variables and represent the separation between a complex network element and a real network element. The imaginary part or the complex network element is generated by copying currents from the quadrature signal path with a copying factor dependent on the value of the element and the center frequency of the bandpass filter. This is shown explicitly in fig.4.20 where the source and the load transformation for a current input has been already performed. The filter consists actually from two coupled low-pass sections for the I signal and for the Q signal respectively.

91

It is to be mentioned the quadrature inputs/ outputs and the quadrature state variables and (k=1,3,5) in the signal flow graph. The block diagram of the complete filter realized with current Gm-C integrators is illustrated in fig.4.21. The reason for choosing current Gm-C integrators, for realization, is their power efficiency. Other reasons will be discussed later on. The copying factors are realized as aspect ratios in the basic integrator from fig.4.9 where the core transconductance element is the same for all integrators the only difference being only the capacitance values and different coupling factors for every section. The advantage of using equal transconductances consists in better matching between integrators.

92

4.5.4. The effect of mismatch on polyphase signals Mismatch in amplitude and/or phase will impair the polyphase signals which consist of two real signals with a constant phase difference. The mismatch in amplitude and phase generates frequency crosstalk between negative and positive frequencies. In fig.4.22, the RF signal which consists of two quadrature signals is mixed with the local oscillator quadrature signals. The phase mismatch can be added to the two oscillator signals whereas the amplitude mismatch is added in the polyphase filter. The gain mismatch and the amplitude mismatch generate two signals and at intermediate frequency affected by errors:

Since the errors are small, we can approximate the signals as shown in fig.4.22. In the complex plane, the ideal signals are represented as empty circles and the black circles are signals with errors. Magnitude errors will generate crosstalk between the positive and negative frequency components while phase errors in the quadrature outputs of the oscillator generates crosstalk between the I and Q signals. For simplicity, consider only the gain mismatch and I=Q=1. The complex signal at the output can be found from:

93

Besides the wanted positive component, there is a negative frequency component proportional to the amplitude mismatch. A mismatch of 2% gives a crosstalk of about -40dB. Another cause of error is the phase mismatch in the polyphase bandpass section. Given the quadrature signals I and Q impaired only by phase errors:

then, the complex signal at the output with errors will be:

For a phase difference of 1° we get a frequency crosstalk of -35dB. This explains why the requirements on phase and amplitude mismatch in the polyphase filter are very strong in order to achieve the required spec’s. To be mentioned the need to match only the two real integrators in the polyphase integrator. If this condition is fulfilled, the quadrature nature of the two outputs is preserved. A limited quality factor of the integrators gives amplitude errors as explained in eq.(4.13). By using an OTA the nondominant poles and zeros degrade the quality factor giving amplitude errors. The most difficult constraint will be to match two OTA’s while the number of components is large (common mode circuit plus differential stage). The power consumption, area and the supply voltage are also limiting factors in using OTA’s or Opamps to realize the filter.

4.5.5. Filter realization and simulation results The filter has been realized with integrators from section 4.3. The central frequency of the filter can be easily tuned by changing all the bias currents of the integrators simultaneously. The simulated polyphase transfer for different bias currents is shown in fig.4.23. The dimensions of the transistors and the scaling factors of every integrator are given in table4.6. The input transistors are scaled in the same way as the polyphase coupling stages with a factor The I and the Q outputs of the integrator have the dimensions given in the first two columns from table 4.6. In order to study the negative frequency crosstalk, Monte Carlo simulations have been performed.

94

For simulations, we have considered matching between the transistors connected at the same gate potential and also matching between the transistors occupying the same position in the differential polyphase integrator. In this approach, due to the simplicity of the integrator and the small dimensions used for the transistors it is very easy to ensure matching as explained above. This is another reason to chose for the integrators from section 4.3. The power supply voltage was set to and the bias current is . The results of the simulation are shown in fig. 4.24. The image frequency will be at -1MHz and the image rejection here is about -40dB. Due to the large quality factor of the integrators, the magnitude errors are below 0.5dB in the passband. The power consumption of the filter, in this case is 5mW.

95

The image rejection can be increased further by using source degeneration polysilicon resistors as shown in fig.4.25. Matching between transistors can be improved at the expense of voltage swing and the area penalty for using resistors. Another effect will be the reduction of the transconductance of the transistors with a factor given by series feedback loop gain. The mismatch between transistors is desensitized

96

with the same factor. The minimum supply voltage can be as low as with

a nominal supply voltage of 2.5V. The results of the simulation are illustrated in fig. 4.26. The power consumption in this case is 15mW for the filter. The image rejection is -52dB at the expense of higher power consumption and less swing. The value of the resistors is about scaled according to the current levels. The value of the integration capacitors varies between for the first section and for the last section scaled according to the factors (k=1...5). The passband amplitude ripple is increased to 1dB. This can be explained from the decrease in the output resistance of the current sources at higher current levels and the decrease of the integrator gain. The result is the decrease in the quality factor of the integrator. In references [22], [23] a polyphase filter based on opamps has been presented. The filter is tuned from switched capacitor banks. Here matching is achieved using polysilicon resistors and due to the use of opamps the dynamic range is high. Although the mirror signal suppression is better than -60dB, the power consumption is 90mW and the large dynamic range is obtained by using automatic gain control. To be mentioned the power supply voltage of The total area is showing the main disadvantage of that approach, namely power consumption and area.

4.5.6. Noise properties of the filter The filter has been terminated with a load resistor and the total voltage noise power on the load resistor has been simulated. The noise has been integrated in the bandwidth of the filter 500KHz...1.5MHz as illustrated in fig.4.27. The scaling factors represent the W/L scaling factors from Chapter 3. The aspect ratios of the transistors and capacitors are going up s times, the resistors are going down s times and the current level increases s times without changing the voltage levels in the filter.

97

The dynamic range for s=1 is 69dB. A factor two increase in scaling factor s gives a factor two improvement in the noise power and 3dB improvement in the dynamic

range as expected. The matching will be also improved by scaling the filter. In conclusion this approach is attractive for low voltage supply in terms of power, area, complexity and time domain properties when comparing to opamp approach.

4.6. Conclusions In CMOS transconductors, large tunability needed to correct for temperature and process variations gives a significant reduction in voltage swings at low supply voltages and consequently dynamic range reduction. The new technologies optimized for digital applications are impaired by second order effects like velocity saturation and mobility reduction. Most of the concepts used in the past cannot be used anymore. New transconductor concepts which do not rely upon the ideal square law of a MOST, are needed. Another issue is to achieve large tunability without conflicting with the large swing requirement. In the beginning of this chapter a low voltage, large swing, tunable transconductor has been presented. It features a constant input window for all tuning conditions. This structure overcomes the problems related to non-idealities of the modern MOS transistor in terms of tunability range. The transconductance can be digitally tuned, in ten coarse steps, and continuously, between coarse steps, in the range If required, the quality factor can be adjusted such that Gm tuning and Q tuning are independent. Total harmonic distortion stays below -50dB for input amplitudes of in all tuning conditions and well below -60dB for amplitudes lower than Large swing property yields a large dynamic range over power ratio. In worst case the noise excess factor is close to 6 and power dissipation is 1.48mW from 3.3V supply. The transconductor can be used as a Gm-C integrator for filter applications.

98

Positive feedback is a promising technique for enhancing gain in sub-micron CMOS because current matching in modern technologies improves. It avoids cascoding for having large gains and can be used for low-voltage applications. The second type of integrator considered in this chapter is a current Gm-C integrator with local positive feedback for enhancing the gain. The reason for using this integrator consists in the low-voltage, high linearity and very high frequency of operation with a high power efficiency. It is compatible with standard digital technology has a high quality factor Q and can work down to 1.5V power supply voltage. By using the DR*GBW product concept from Chapter 3 it is shown that the current Gm-C approach has better power figures for the same working conditions as Gm-C approach. The fundamental limits have shown the difference between an analog filter and a digital one when signal to noise ratio and power/pole are taken as variables in the comparison. However, it is not clear for which S/N ratio the transition between an efficient analog filter and a digital filter takes place. According to the previous conclusions, this transition could be somewhere in between 50dB and 60dB which makes difficult to decide whether or not a digital filter is power efficient when compared to an analog filter. The two integrators presented above are used to realize the video filter from Chapter2 in an analog way and to make a comparison in power to the digital approach. Matching in this type of filters is not important. Therefore we are dealing with noise driven power consumption. It turns out that digital approach has less power consumption per pole than the analog counterparts for a CMOS process. This explains why, in the future, digital filters will be used even for low DR applications. There are filter applications where matching requirements and noise requirements have the same importance, with constraints on power consumption and linearity. Channel selectivity in receivers has been realized until recently using SAW filters. Those components are external components and therefore integration on chip of selectivity has become a major concern in receivers. From Chapter 3 we already know that selectivity increases the noise power and requires extra power consumption to achieve it. A polyphase filter is an example of a selective filter without the need of high Q bandpass sections. Here selectivity is rather ensured by using polyphase signals where matching driven power consumption comes as a variable. Polyphase filters can discriminate between positive and negative frequencies and therefore, using this property, selectivity can be achieved. By using a low power integrator, we have shown how to realize a polyphase filter needed for image rejection in a mobile transceiver. The filter has a central frequency of 1MHz, a gaussian to -6dB transfer and a pass-band from 500KHz up to 1.5MHz. The filter has been simulated in a CMOS technology with a supply voltage of 2.5V. The image rejection can be made better than -52dB with a power consumption of 15mW with a dynamic range of 69dB. When compared to active-RC realizations with opamps it shows power figures better with a factor six.

99

REFERENCES [1] E.A.Vittoz, “Low-Power Design: Ways to approach the limits”, IEEE International Solid-State Circuits Conference, pp. 14-18, 1994. [2] G. Groenewold, “Optimal dynamic range integrators” , IEEE Transactions on Circuits and Systems-I: Fundamental theory and Applications, Vol.39, no. 8, pp. 614627, August, 1992. [3] R. Castello, “Low-voltage continuous-time filters”, Proceedings of the Workshop on Advances in Analog Circuit Design, Lausanne, Switzerland, 1996. [4] M.A.T. Sanduleanu, A.J.M. van Tuijl and R.F.Wassenaar, “Large swing, high linearity transconductor in CMOS technology”, Electronics Letters, vol.34, no.9, pp. 878-880, April 1998. [5] M.A.T. Sanduleanu, A.J.M. van Tuijl, E. Klumperink, R.F.Wassenaar, “Lowvoltage large swing transconductor”, Proceedings of the 1997 European Conference on Circuit Theory and Design- ECCTD ’97, Budapest, pp.1412-1417, Sept., 1997. [6] C.H.J. Mensink, B. Nauta, “CMOS tuneable linear current divider”, Electronics Letters, vol. 32, no.10, pp. 889-890, May 1996. [7] H. Wallinga and K. Bult, “Design and analysis of CMOS analog signal processing circuit by means of a graphical MOST model”, IEEE J. Solid-State Circuits, vol. SC22, pp. 672-680, June 1989. [8] B. Nauta, “Analog CMOS low-power design considerations”, Low Power-Low Voltage Workshop at ESSCIRC’ 96, Neuchatel-Switzerland, September 1996. [9] C.H.J. Mensink, B. Nauta, H.Wallinga, “A 5.5MHz CMOS low-pass filter using a ‘soft-switched’ transconductor”, Proceedings of the ESSCIRC ’96, pp. 84-87, Neuchatel, September 1996. [10] C.H.J. Mensink, “Analogue transconductors for sub-micron CMOS technology”, PhD Dissertation, ISBN: 90-9009612-4, pp. 30-31, University of Twente, September 1996. [11] S.L. Smith and E. Sanchez-Sinencio, “Low voltage integrators for high frequency CMOS filters using current mode techniques”, IEEE Trans. Circuits Syst-II, vol.43, no.1, pp.39-48, Jan.1996. [12] S.L. Smith and E. Sanchez-Sinencio, “3V high-frequency current-mode filters”, Proc. Int. Symp. Circuits Syst. , May, 1993, Chicago, IL., pp. 1459-1462. [13] B. Nauta, “A CMOS transconductance-C filter for very high frequencies” IEEE J. Solid-State Circuits, vol.27.,pp. 142-153, Feb. 1992. [14] M.Steyaert, J.Crols, S. Gogaert and W.Sansen, “Low-voltage analog CMOS filter design” IEEE Int. Symp. Circuits Syst. 1993, vol2, pp. 1447-1450, May 1993. [15] M.J. Gingel, “Single sideband modulation using sequence asymetric polyphase networks”, Electrical Communication, vol.30, pp.21-25, 1973. [16] N. Boutin, “Complex signals” IEEE journal of Solid States Circuits, vol.12, pp.27-33,1989 [17] S.Darlington, “Realization of constant phase difference”, BSTJ volXXXIX, Jan.l950,pp.94-104. [18] H.J.Orchard, “Synthesis of wideband two-phase networks”, Wireless Engineering, March 1950, pp.81-82.

100

[19] D.K.Weaver, “Design of RC Wide-Band 90-Degree Phase Difference Network”, Proc. Of the IRE, vol.38, July 1950, pp.754-770. [20] W.Saraga, “The design of wide-band phase splitting networks”, Proc. Of the IRE, Vol.38, July 1950, pp.754-770. [20] J.C. Rudell, J.A. Weldon, P. Gray, “An integrated GSM/DECT Receiver Design Specifications”, UCB Research Laboratory Memorandum, Memo#: UCB/ERL M97/82 [21] A.I.Zverev “Handbook of Filter Synthesis” John Wiley & Sons, Inc., 1967 [22] J. Crols and M. Steyaert, “ CMOS wireless transceiver design”, Kluwer Academic Publishers, 1997, ISBN 0-7923-9960-9 [23] J. Crols and M. Steyaert, “ An Analog Integrated Polyphase Filter for a High Performance Low-IF Receiver”, Proc. VLSI Circuits Symposium, Kyoto, pp.87-88, June 1995.

CHAPTER 5 Chopping: a technique for noise and offset reduction 5.1 Introduction In Chapter 3 we came to the conclusion that high accuracy and large dynamic range will cost power. We have considered there only white noise. The 1/f noise or flicker noise decreases further the dynamic range of analog circuits. In the following chapter different methods to reduce 1/f noise and offset are being discussed. Chopping is a technique for noise and offset reduction employed to boost at the same time the accuracy and the dynamic range of analog circuits without extra penalty in power. In the introductory part we are considering different ways of reducing offset and 1/f noise with their advantages and disadvantages. As a modulation technique, chopping modulates in a different way white noise and 1/f noise of amplifiers. Therefore the difference between 1/f noise modulation and white noise modulation is being introduced with a comparison to sampling methods. As we will see, chopping is the only method which reduces 1/f noise and offset without modifying the baseband white noise like in the sampling case [1]. Although, chopping is a low frequency technique, there are applications where bandwidths of the signals are in the MHz range. At this frequency only the residual offsets generated from charge injection and slewing of the input stages will limit at the upper part the chopping frequency. A method to use chopper modulation at high frequencies is introduced and a lowvoltage, low-power, chopped transconductance amplifier for mixed analogue digital applications will be presented. This OTA is meant for high-end audio applications. Chopping and dynamic element matching allow low noise and low residual offsets up to 1MHz. The sensitivity to substrate noise is tackled in the design. In mixed level applications accurate voltage references are difficult to realize due to the lack of reproducible lateral pnp’s and the large offsets inherent to CMOS opamps. Another problem tackled in this chapter is related to the realization of a low power and accurate bandgap voltage reference in CMOS. It is shown that by using chopping techniques and a chopped OTA, the accuracy of a bandgap voltage reference

102

can be improved about ten times without laser trimming and with the benefit of reducing the 1/f noise of the reference. The same chopped OTA for high-end audio applications has a power consumption of while in the bandgap example the power consumption is The two examples show that the term low power has to be related to the specific application and its own specs.

5.2. Ways to reduce offset and 1/f noise Offset and 1/f noise are setting constraints on the obtainable accuracy and dynamic range in the case of CMOS amplifiers. There are several ways to reduce offset and low frequency noise based on sampling or modulation. The autozero technique and correlated double sampling techniques are methods of reducing 1/f noise and offset based on sampling. Due to white noise undersampling, the decrease of 1/f noise and offset is paid by the increase of baseband white noise. In this section the two methods are considered and their advantages and disadvantages are discussed.

5.2.1. The autozero technique The autozero technique [2], [3], [4] reduces the offset and low frequency noise based on sampling methods. This method has been extensively used in the past for offset reduction in comparators and amplifiers [4]. Most of the nowadays A/D converters with offset cancellation make use of auto-zeroed comparators. Fig.5.1 illustrates the principle of an autozero amplifier. In the phase 1 of the clock, the sampling phase, the offset and the flicker noise of the amplifier configured as a buffer is sampled on the capacitor C.

103

The output y(t) is actually the offset voltage amplifier is large:

as long as the open loop gain of the

In the second phase of the clock, the amplification phase, the input signal x(t) is sampled and amplified. The offset and 1/f noise is removed from the output by subtracting the value sampled on the capacitor from its actual output:

The equivalent input offset is reduced by a factor equal to the amplifier open loop gain. The reduction of 1/f noise is based on the high correlation between the 1/f noise samples. The charge injected from the switch produces residual offset which is not cancelled by the autozero mechanism. To show the autozero effect consider a stationary random process n(t) which can be white noise or flicker noise generated by the amplifier A from fig.5.1. For simplicity the amplifier is assumed to have an infinite bandwidth, unity gain A=1 and the input signal is x(t)=0. The equivalent circuit for the noise sampling is shown in fig.5.2. Assuming the switch ideal, the voltage on the capacitor C is an ideal sample and hold signal. If are sampling time instants, h(t) the hold function, the voltage on the capacitor C is:

At the output of the amplifier we have a signal y(t):

104

Given the sample and hold of the noise and/or offset on the capacitor C the output spectrum is found to be:

The output noise spectrum is a sequence of spectra shifted at multiples of sampling frequency The transfer function for every harmonic has a value of:

The transfer function for k=0 has a zero at the origin and acts like a differentiator. Therefore, any DC component of the random process n(t) is cancelled out. That is why this technique is called autozero. Fig.5.3 shows the transfer functions for k=0 and The power spectral density of the output noise is found from (5.5):

If the random process n(t) is white noise the second term from (5.7) introduces foldover components in the baseband. The first term takes care for 1/f noise and offset reduction. The simple switched current memory cell from Chapter 3 has also autozero properties and therefore flicker noise is reduced. In conclusion, autozero amplifiers will reduce the offset and 1/f noise by using sampling techniques at the expense of increasing the white noise in the baseband.

5.2.2. Correlated double sampling Correlated double sampling (CDS) is another technique for offset and noise reduction [5], [6], [7], [8]. This method has been used in charge coupled devices CCD. The main difference between autozeroing and CDS consists in the way the signal is

105

delivered to the output. In CDS methods, there are two sampling times. A sampling time for noise only and a second sampling time for noise and signal with opposite sign. In the CDS case the output is a sampled and hold signal whereas for autozeroing, the output is a continuous time output. CDS relies upon the same correlation between 1/f adjacent samples. This method has also the disadvantage of aliasing white noise in the baseband.

5.3. Chopping seen as a modulation technique Another method for noise and offset reduction is the chopping technique. Chopping is a modulation technique which shifts the spectra of low frequency stationary processes at multiples of chopper frequency out of the band of interest. To understand this, consider a stationary random process x(t) of autocorrelation function and power spectral density which is applied to a band limited amplifier A(f) as illustrated in fig.5.4. The modulation signal (chopper signal) m(t) is periodic with a period T and can be expanded in Fourier series:

The Fourier transform of this signal is a sequence of Dirac pulses decaying with the order of the harmonic and having contributions only at odd multiples of the chopping frequency 1/T.

The power spectral density of the output process y(t)=[A×(t)]m(t) can be found from the following convolution:

106

This gives contributions only at the odd multiples of the chopping frequency 1/T:

Therefore, the output power spectral density is a repeated replica of the input power spectral density at the odd multiples of the chopper frequency rapidly decreasing with the order of the harmonic. That is why foldover effects are not present in the case of chopping. This is the main difference between chopping and sampling methods.

5.4. Noise modulation From the previous paragraph we have seen the modulation effects of chopping on a input process x(t). It is important to notice the difference between a narrow-band process and a broadband process after chopper modulation. The input stationary random process x(t) can be white noise or 1/f noise applied to the amplifier A(f) which has a band limiting effect on the noise.

5.4.1. White noise modulation For the beginning, assume that x(t) is a broadband random process white noise like with a power spectral density In order to simplify the analysis, the gain of the amplifier is taken to be 0dB and the frequency transfer has a first order behavior:

The power spectral density of the noise at the output can be found from (5.11) with assumption that

The series from (5.13) can be computed by using Poisson summation rule [9]. For large values of we get:

107

In conclusion, the chopper modulator has a small influence on the white noise when the bandwidth of the amplifier is larger than the chopping frequency. This is not the case for sampling where undersampling phenomena actually increases the noise in the baseband [1]. The power spectral density of the white noise will be unchanged as long as the bandwidth of the amplifier is larger than the chopping frequency. Chopping at frequencies higher than will reduce the power spectral density of the white noise as explained in reference [4]. Although white noise is a fundamental limitation it can be reduced by chopping. Oversampling in D/A and A/D converters has about the same effect on the baseband white noise.

5.4.2. 1/f noise modulation When narrow band random processes are applied at the input of the chopper modulator the situation will change. The input power spectral density of 1/f noise is:

In the constant c we have included the 1/f noise constant process dependent and the geometry factor, dependent on the dimensions of the transistors. After chopping the PSD of the modulated 1/f noise becomes:

Fig.5.5 shows the normalized PSD of the flicker noise after chopping when The effect of chopper modulation on the flicker noise will be the reduction of the PSD of the output noise at low frequencies. At odd multiples of the chopper frequency the

108

PSD of the flicker noise increases. Thus, under the same condition the PSD of the white noise after chopping remains the same and the PSD of the flicker noise at low frequencies will be reduced.

5.5. Chopped amplifiers and offset reduction We have analyzed so far the effect of chopper modulation on white noise and 1/f noise. In order to be able to process signals without changing the baseband information, we have to modulate signals and noise differently. The principle of chopper amplifiers is illustrated in fig.5.6. For simplicity the 1/f noise has been represented on a logarithmic scale. The input signal is multiplied with a rectangular signal m(t) with unity amplitude and 50% duty-cycle. As a result, the signal is once modulated at odd harmonics of the chopper frequency. The signal will be amplified and/or filtered, modulated back, leaving spectral contributions at even harmonics of the chopper frequency. The amplitude of the modulation signal decreases with 1/n where n is the harmonic number. Offset and 1/f noise are modulated at odd harmonics leaving the baseband free of 1/f noise. In the ideal chopping case, the bandwidth of the amplifier should be infinity. As long as this is true, multiplying the signal twice with m(t) will reconstruct the input signal ideally. If the bandwidth of the amplifier is limited, the result is a high frequency residue centered around the even harmonics and the signal in the baseband is attenuated. To recover the signal, the output has to be low-pass filtered as shown in fig.5.7. Given the corner frequency of the 1/f noise and the cutoff frequency of the low-pass filter at the output, the necessary condition to have complete reduction of the flicker noise in the baseband is found from:

109

To analyze the effect of chopping on the offset of the amplifier, the offset has been represented in fig.5.6 at the input of the amplifier A. As long as the frequency response of the amplifier is flat, the output voltage is found from the following convolution:

This sequence of Dirac pulses has no DC component and the offset at the output has a theoretical value of 0V. Obviously, any temperature drift of the offset voltage is also cancelled out after chopper modulation.

5.6. Low-power low-voltage chopped transconductance amplifier for noise and offset reduction. Chopping at high frequency. In this section the chopping technique will be exploited in order to find a new chopper architecture capable of chopping at high frequencies [10]. Chopping is a method employed for noise and offset reduction in low frequency applications. However, there are applications where the bandwidths of signals can reach MHz range and offset and noise reduction is required. The question is if one can use the chopper technique to process signals with a large bandwidth. In this case we have to be able to increase the chopper frequency without increasing excessively the residual offset generated by second order effects. It is worth to mention that chopper architecture presented in the following sections can be used for low frequency applications also. High-end audio applications will require dynamic ranges of more than 90dB with strong requirements on linearity. When driving headphones, excessive offset decrease the efficiency of the headphone by heating up the coil and even destroying it. In some portable audio applications, power consumption is also a matter of concern. The aim is to boost the dynamic range and the accuracy of the system without power penalty. The low-power chopped transconductance amplifier presented in the

110

following sections is designed for portable audio applications and the principle can be used in a large variety of circuits.

5.6.1. Conventional choppers In conventional choppers [11], [12], [13] the signal is being transposed at the input of the differential pair, amplified and demodulated back at the output nodes as shown in fig.5.8. Switching at high impedance nodes [14], [15], [16] would be disadvantageous due to limited bandwidth of the amplifier. From section 5.4 was clear that we need large amplifier bandwidths in comparison to the chopping frequency. Only in this situation we have reduction of 1/f noise. A band-limited amplifier gives also second order effects like attenuation of the signal in the base-band and high frequency residues around even multiples of the chopping frequency. That is why, in this approach, high frequency chopping is not possible and this method is limited to few tens of KHz. Besides, the switching noise is directly coupled to the output. Because we have switches in the middle of the supply voltage, for low voltage applications charge pumps are needed. This is to ensure that all switches are firmly open and/or closed. We need a low pass filter at the output to recover the base-band free of noise. For low frequency applications the required time constants for filtering cannot be integrated on-chip. Another approach would be to use a bandpass filter centered around to recover the signal [17], [18]. In this situation, very low offsets are reported but the method is applicable for low frequencies. Besides the bandpass section would require extra power [see Chapter 3]. In reference [13] a sample and hold circuit has been used for low-pass filtering by exploiting the low-pass character of the sin(x)/x function. Again this method has been applied for low frequency applications. Theoretically, we need to chop in the signal path where there is no bandwidth limitation and if possible to eliminate the required low-pass filter.

111

5.6.2. The proposed method The proposed method presented in reference [10] is shown in fig.5.9. It comprises an input modulator, a PMOS differential pair, current sources and a low voltage, high bandwidth cascoded mirror, to perform a differential to single ended conversion. The second chopper transposes again the signal at low impedance nodes and demodulates back the signal, canceling out the offset of the bottom transistors. The offset and noise from the current sources will be canceled out by the third chopper which matches dynamically [19] the two transistors on top. There are no consequences on the signal due to the third chopper. The benefit of chopping at low impedance nodes comes from the large bandwidth of the basic amplifier. Therefore, we can chop at much higher frequencies where the only limitation would be the charge injection residual offset and the slewing behavior of the input stage. In plus, the cascode transistors provide low-pass filtering for the high frequency spectral contributions coming from chopping. In this approach charge pumps are not needed if the common mode voltage is well chosen and switching is close to the supply rails. The output node used for Miller compensation filters out the undesired high frequency spectral components from switching, delivering to the output stage an offset/noise free voltage. Another advantage is using the dominant pole of the amplifier as a low-pass filter. In the conventional approach an extra filter after the last chopper is required.

5.6.3. Circuit principle Fig.5.10 illustrates the circuit diagram. The input chopper M10, M11, M13 and M15 transposes the differential input signal applied to the terminals IN+ and INto the alternate output nodes. The second chopper M19, M20, M21 and M22 demodulates the signal and modulates 1/f noise and offset at odd harmonics.

112

The cascoded mirror M24, M25, M12 and M14 performs the required broadband differential to single ended conversion at the output. The need for large bandwidths implies small transistor lengths for M12 and M14 and therefore extra offset and 1/f noise. For this reason a third chopper is being introduced in the signal path: M27, M28, M29 and M30. The transistors M12 and M14 are dynamically matched [19] without consequences on signal. The unswitched cascode transistors provide further improvement in switching noise and residual offset by low pass filtering some of the HF noise components generated from chopping and keeping low voltage swings at their sources. Another source of concern in mixed level applications is the substrate bounce coming from the digital circuitry. Modern processes have a low ohmic substrate and that is why digital circuits pollute the substrate, generating noise in the analog circuits. In a CMOS technology for mixed level signal processing, the substrate bounce can reach 300mV in amplitude with spectral contributions in GHz range, further reducing the voltage swing [20]. In order to minimize substrate interferences, only PMOS transistors and NMOS switches with small dimensions are being used in the signal path [10]. The oxide capacitance of M34 decouples the BIAS line to VSS. Substrate interferences present in the sources of cascode transistors M23 and M26 will be also present at their gates such that gate source voltages of the same transistors can be considered constant for HF substrate noise [20]. For the same reason, the current sources M6 and M7 have their gates decoupled to VSS via a large capacitance [M35].

113

5.6.4. Noise and offset The input transistors have the largest noise contributions because they are providing the largest gain in the circuit. Noise contributions are coming from transistors M6, M7, M12 and M14. Neglecting the noise introduced by cascode transistors and switches, the power spectral density of the white and 1/f noise referred to the input is:

In the above equation and are process dependent constants. Large transconductances of the differential input pair give low white noise. 1/f noise can be minimized by increasing the area of the input pair and increasing the transconductance of the input transistors in comparison to the transconductances of M6, M7 and M12, M14. The input pair is biased in weak inversion for accuracy reasons [see Chapter 3] and white noise considerations. Large phase margins can be obtained when M12 and M14 have small lengths. This increases their contribution to the offset and noise. The dominant terms in the offset voltage are due to threshold mismatch of the input pair and the threshold mismatch of M12 and M14. If denotes the threshold mismatch, the relative gain factor mismatch, the effective gate voltage n the slope factor and the thermal voltage, the offset voltage referred to the input can be approximated as:

In order to reduce the influence of the threshold mismatch of M12 and M14 we have used dynamic element matching to reduce this effect. Fig.5.11 shows the simulated dynamic range (static) of the OTA and the static offset as a function of the bias current JBIAS. The 1/f noise contribution has been subtracted from the total noise. The OTA has been configured as a follower with 10MHz gain bandwidth product (GBW). By scaling down the current according to W scaling and keeping the same power supply voltage and GBW, a factor 10 reduction in power gives a 10dB reduction in DR. This can be seen also from the product of the OTA already discussed in Chapter 3, section 3.4.5. If denotes the total power, the saturation limits at the output node, n the slope factor, the current efficiency and NEF the noise excess factor then:

114

Given the efficiency the noise excess factor NEF=2.2 the GBW=10MHz , to reach a dynamic range of about 92dB we need a minimal power consumption of according to (5.21). From fig.5.9 the bias current for this dynamic range is and the power consumption is From accuracy point of view by increasing the current, the offset voltage decreases. The same factor 10 increase in power consumption will generate only a factor two improvement in accuracy. This explains again that accuracy driven power gives stronger constraints than noise driven power.

5.6.5. Experimental results The chopped transconductance amplifier has been realized in a CMOS technology with two polysilicon layers and three metal layers. For measurements purposes the OTA has been configured as a follower with a bias current of

a. Offset measurements Fig.5.12 shows the static offset and the residual offset for 6 arbitrarily chosen circuit samples after low pass filtering the output. Without chopping (fchop=0), static offsets of less than can occur. Chopping will reduce the offset for relatively low chopper frequencies but increasing the chopping frequency the residual offset will increase. The residual offset is generated by charge injection and mismatch between the transistors of the chopper modulator. Charge injection is a phenomenon which occurs in the switching instants due to the clock feedthrough and charge shot in the channel. At low frequencies the errors per switching period caused by charge injection are negligibly small. The residual offset at 100KHz chopping frequency is less than At high frequencies the errors generated by charge injection cannot be neglected anymore and the residual offset increases. Up to 1MHz the residual offset is lower than in all six cases. At low chopping frequencies, a minimum

115

in the residual offset occurs. Second order effects like charge injection and residual offsets

will be extensively discussed in section 5.6.6.

b. Noise measurements For digital audio applications there are strong requirements for linearity and signal to noise ratios. The measurements for linearity and signal to noise are merged in one measurement called SINAD, an acronym for signal to noise plus distortion. This figure is more restrictive than signal to noise because it includes also the distortion components. Fig.5.13 illustrates the signal to noise plus distortion figure (SINAD) for 93KHz chopping and 1KHz input.

116

The input signal at 0dB reaches 2.8Vpp where distortion is high and dominates SINAD. At this level of signals the output transistors are pulled out of saturation and the distortion is high. For low signal amplitudes the noise level is higher than the distortion level. The measured signal to noise ratio in audio band (0..20KHz) after chopping is -95dB and harmonic distortion (THD) is -89dB at -15dB signal level. Chopping increases the signal to noise plus distortion ratio with about 6dB. The power consumption is from a 3.3V power supply. The 3.3V power supply voltage comes from digital requirements. However, the OTA can work down to 1V with decreased dynamic range. The 1/f noise decreases the dynamic range of the amplifier. The same noise performances can be achieved without chopping but increasing the power consumption 4 times (2.4mW) as estimated by eq.[5.21]. The power needed for chopping is negligible small in comparison to the bias power. In mixed level applications there is always a clock generation circuit for the digital circuits. That is why the clock circuitry for digital functions can be shared with chopped amplifiers without the need for an extra clock. At 1MHz chopping the estimated power consumption of the chopper modulators is about In Table 5.1, a summary of performance is presented. Special measures have been taken in order to improve matching when the layout of the circuit has been made. To reduce charge injection, the switches of the chopper modulator should be well matched. In fig.5.12 the chip photomicrograph is illustrated. The area of the OTA is about Some possible applications of the chopped transconductance amplifier include low noise and low offset applications like: low offset integrators for battery management where the battery current is monitored; high precision and low noise band-gap references in CMOS; headphone drivers in a D/A configuration for portable applications; filters where matching requires too much area and power consumption; sensors with high requirements on precision and temperature drifts;

117

5.6.6. Second order effects: Charge injection and residual offset In the input modulator charge injection and parasitic coupling will cause spikes to appear. Although spikes are common mode signals, the common mode rejection of the amplifier is limited at high frequencies. Therefore, after amplification and demodulation, these spikes generate residual offsets. Only the odd harmonics of the chopper frequency will contribute to the residual offset. In fig.5.15 the output of the chopped OTA is shown. The OTA has been configured as a buffer which modulates its own offset. The spikes presented at the output have a time constant and an amplitude The bandwidth of the spikes is about larger than the chopping frequency. When the charge injection time constant is small, the energy of the spikes will be located at high frequencies. If the bandwidth of the amplifier is well chosen to have sufficient gain for the modulated signal and to reject the spectral components of the spikes, the amount of residual offset generated will be reduced. The Fourier transform of the spike signal is:

This spectrum is applied to the amplifier with a frequency transfer A(f). The residual offset is found from the following convolution:

118

The first term in (5.23) represents the Fourier transform of the spikes filtered by the amplifier transfer function A(f). The second term is the Fourier representation of the chopper signal m(t). In a follower configuration, chopping is an internal operation thus, the transfer function A(f) is the gain of the input stage loaded with transistors M23 and M26. Hence, from (5.23) the residual offset can be found from the following series:

In eq.(5.24) T is the chopping period and the gate-source capacitance of M23 and M26. By using Poisson summation rule for series and considering larger than (condition found in section 5.4), we get:

This shows an increase of the residual offset with chopping frequency and the energy of the spikes, already seen in the measurements from fig.5.12. The explanation of the large spikes in the first modulator can be found from fig.5.16. The input stage has been replaced with a capacitive load and the output stage has an output resistance As long as the rise and fall times of the clock are small, the charge will be equally distributed at the output of OTA and at the input stage regardless the impedance levels of the two nodes. When the output impedance of the OTA is larger than the ON

119

resistance of the switch, the dominant time constant for charge will be and the offset will be proportional to as (5.25) shows. The amplitude of the spike is The larger the output resistance of the OTA, the larger the residual offset

will be. In conclusion, to obtain low residual offset voltages, the output stage of the amplifier should be low ohmic. This problem will be tackled in the next chapter where an output stage will be added in order to improve residual offsets.

5.7. A low-power bandgap voltage reference In the previous section an OTA for high end audio applications has been presented. The need for high dynamic range and large GBW requires few hundreds of of power. A bandgap reference is an example of a low frequency application where accuracy and area give constraints on the total power consumption. In mixed level applications accurate voltage references are difficult to realize due to the lack of reproducible lateral pnp transistors and the large offsets inherent to CMOS opamps. If low power is a must, the accuracy is mainly impaired by the increased offset of the opamps. It is shown that by using chopping techniques the accuracy of a bandgap voltage reference can be improved about ten times without laser trimming and with the benefit of reducing the 1/f noise of the amplifier. This example shows that the principle of the chopped OTA meant for chopping at high frequencies, can be used also in low frequency applications.

5.7.1 The principle of the bandgap The voltage of a bandgap reference is based on the bandgap voltage of a semiconductor: a well defined physical value. In submicron CMOS digital processes, the lack of reproducible lateral pnp’s can be seen as a disadvantage. Without these components one has to rely upon the well known solution for a bandgap reference shown in fig.5.17a, which requires the use of an opamp. In bipolar technologies,

120

simple solutions for voltage references have been considered [21], [22]. For CMOS processes the large offset of the opamp will reduce the accuracy of the output voltage In order to achieve better accuracy, laser trimming is a well known solution but an expensive one. At low bias currents of the opamp, the offset increases and the challenge would be the realization of a low power and accurate bandgap voltage reference in CMOS without laser trimming of resistors. Furthermore, the available area is limited. Obtaining better resistor matching by increasing the area is not an option. When a stable reference voltage is not required at all times (as in the case of an A/D) switched-currents techniques with autozero amplifiers can provide the needed precision [23], [24]. The resulting bandgap reference voltage is not continuous time and has the disadvantage of increasing the white noise by sampling. Besides, the power consumption of the sampled data bandgap is higher than a few hundred In fig.5.17b, the output voltage as [25]:

can be related to the absolute temperature

denotes the extrapolated bandgap voltage of a semiconductor, is the mobility temperature exponent of the charge carriers in a bipolar transistor and the reference temperature. This condition holds true for a well chosen resistance ratio If n is the ratio between the emitter areas of and the thermal voltage kT/q and a process constant then the ratio of resistors has to satisfy the following condition:

In fig.5.17b, a plot of eq.(5.26) centered around

is shown. The accuracy of

121

the output voltage, at the reference temperature depends on the process spread, the offset voltage of the opamp and matching of the resistors.

5.7.2 The accuracy of the bandgap Consider the basic bandgap from fig. 5.17.a. and the deviation of the output voltage from the nominal voltage due to the deviation of the resistances and the offset of the opamp The transistor is made from n identical transistors as shown in fig.5.17a. Denote nominal values, R the actual values of the resistors and the thermal voltage. The absolute error of the reference voltage is given by:

The first term is generated by the process spread of The second term comes from the mismatches of the resistors and The last term is generated by the offset of the opamp. Now we can find the spread of the output voltage as a function of the individual terms

where:

122

Comparing in (5.30) the dominant term is by far For a resistor ratio of about 7 and n=24, the opamp offset voltage spread is amplified about 70 times. The simulated spread in the offset voltage of the opamp is According to (5.30.d) this gives a spread in of about 32mV. Hence, in order to get a better accuracy, one should be able to decrease the offset of the opamp.

5.7.3. Accuracy improvement In fig.5.18 we have a version of the bandgap reference based on the principle

shown in fig.5.17.a with a chopped operational amplifier [26]. The source follower M31 provides the output voltage Vo, bandgap referenced. Simulations shows that the spread of the opamp offset without chopping is

123

Chopping at 10KHz, the offset will be reduced to The current consumption of the opamp is from a 2.5V power supply voltage. Fig.5.19 shows the open loop gain of the opamp. The low frequency gain is 120dB, the gainbandwidth product of the opamp is 300kHz and the phase margin 74°. The resistors and are polysilicon resistors with a low temperature coefficient and their values are given in fig.5.17.b. In order to decrease the spread, parallel-series configurations of equal sized resistors have been used. The area of the circuit is about being dominated by the area of the resistors. Without chopping, the cumulated effect of the spread contributions gives spread at the output. By chopping, the total spread reduces to The accuracy of can be increased, in principle, by increasing the area of the resistors. Simulations show that increasing the area 16 times, the spread of the reference voltage is The bias current can be derived from the bandgap referenced output in order to have a temperature independent biasing. To prevent the zero solution of the output voltage, we need to add a start-up circuit. The total power consumption of the circuit is

5.7.4. Noise properties: Due to the low current levels, the transconductance of the input stage of the opamp is low and the noise properties of the bandgap are dominated by the opamp white noise. The 1/f noise is being reduced by the chopping mechanism and therefore the power spectral density of the noise at the output depends on the noise properties of the opamp. Denote NEF the noise excess factor of the opamp and the incremental resistance of the diode connected transistor The power spectral density of the output noise can be approximated with:

124

The closed loop bandwidth is 30kHz and the rms value of the integrated voltage noise in this frequency band has a value of about for an opamp noise excess factor NEF of 2.2.

5.8. Conclusions From Chapter 3 we came to the conclusion that high accuracy and large dynamic range will cost power. In the following chapter different methods to reduce 1/f noise and offset are being discussed. These methods are based on sampling and modulation and their advantages and disadvantages are reviewed. Chopping is the only method which reduces 1/f noise and offset without modifying or at least without increasing the baseband white noise. Although, chopping is a low frequency technique, there are applications where bandwidths of the signals are in the MHz range. Here,. the residual offsets generated from charge injection will limit the chopping frequency. A method to use chopper modulation at high frequencies is introduced and a low-voltage, low-power, chopped transconductance amplifier for mixed analogue digital applications has been presented. This OTA is designed for high-end applications. Chopping and dynamic element matching allow low noise and low residual offsets up to 1MHz. The sensitivity to substrate noise is tackled in the design. Experimental results show residual offsets of less than up to 1MHz chopping frequency. Second order effects like charge injection and residual offsets are discussed. By chopping, the S/N is improved with about 6dB which brings a factor 4 reduction in power. In mixed level applications accurate voltage references are difficult to realize due to the lack of well characterized lateral pnp’s and the large offsets inherent to CMOS opamps. Another problem tackled in this chapter is related to the realization of an accurate bandgap voltage reference in CMOS. It is shown that by using chopping techniques and a chopped OTA, the accuracy of a bandgap voltage reference can be improved about ten times without laser trimming and with the benefit of reducing the 1/f noise of the amplifier. This example shows that low power is a relative term which has to be adapted to the application.

125

REFERENCES [1] C.A. Gobet, “Spectral distribution of a sampled lowpass filtered white noise”, Electron. Lett., vol.45, no.1, pp.307-316, 1974. [2] C. Enz, “Analysis of the low-frequency noise reduction by autozero technique”, Electron. Lett., vol.20, pp. 959-960, Nov. 1984 [3] C. Enz, E. Vittoz, F.Krummenacher,” A CMOS chopper amplifier”, IEEE J. SolidState Circuits, vol.SC-22, pp. 335-342, June 1987. [4] C.Enz, “High precision CMOS micropower amplifiers”, These no.802 (1989), Ecole Polytechnique Federale de Lausanne EPFL. [5] K.H. White, D.R. Lampe, F.C. Blaha and I.A. Mack, “Characterization of surface channel CCD image arrays at low light levels”, IEEE J. Solid-State Circuits, vol. SC9, pp. 1-14, Feb. 1974. [6] R.W. Brodersen and S.P. Emmons, “Noise in burried channel charge-coupled devices”, IEEE J. Solid-State Circuits, vol. SC-11, pp. 147-156, Feb. 1976. [7] R.J.Kansy, “Response of a correlated double sampling circuit to 1/f noise”, IEEE J. Solid-State Circuits, vol.SC-15, pp. 373-375, June 1980. [8] H.M. Wey and W. Guggenbuhl, “Noise transfer characteristics of a correlated double sampling circuit”, IEEE Trans. Circuits Syst., vol. CAS-33, pp.1028-1030, October 1986. [9] A. Papoulis, “The Fourier integral and its applications”, Mc Graw-Hill,1962 [10] M.A.T. Sanduleanu, B.Nauta and H.Wallinga, “Low-power low-voltage chopped transconductance amplifier for noise and offset reduction”, Proceedings of the European Solid-State Circuits Conference, pp.204-207, October 1997. [11] K.C. Hsieh et al., “A low-noise chopper-stabilized differential switched-capacitor filtering technique,” IEEE J. Solid-State Circuits, vol. SC-18, pp. 708-715, Dec. 1981. [12] C. Enz, E. Vittoz, F.Krummenacher,” A CMOS chopper amplifier”, IEEE J. Solid-State Circuits, vol.SC-23, pp. 750-758, June 1988. [13] A. Bakker and J.H. Huijsing, “A CMOS chopper opamp with integrated low-pass filter”, Proc. ESSCIRC’97, Southampton, UK, Sept.1997, pp. 200-203.

126

[14] Analog devices, Inc., Datasheet, OP-07, Ultra-low offset voltage operational amplifier. [15] Harris Semiconductor, Inc., Datasheet, ICL-7650S, 2MHz, Supper ChopperStabilized Operational Amplifier, 1996. [16] Linear Technology, Inc., Datasheet, LTC 1050, Precision chopper stabilized operational amplifier with internal capacitors. [17] C. Menolfi and Q. Huang, “A CMOS instrumentation amplifier with 600nV Offset, noise and 150dB CMRR”, “ IEEE Custom Integrated Circuits Conference, CICC ’98”, Santa Clara, May 1998. [18] C. Menolfi and Q. Huang, “A low-noise CMOS instrumentation amplifier for thermoelectric infrared detectors”, IEEE J. Solid-State Circuits, vol.SC-32, no.7, pp. 968-976, July 1997. [19] R.J. van de Plassche, “Dynamic element matching for high accuracy monolithic D/A converters”, IEEE J. Solid-State Circuits, vol.SC-11, no.7, pp.795-800, Dec. 1976. [20] B. Nauta and G.Hoogzaad, “How to deal with substrate noise in analog CMOS circuits”, European Conference on Circuit Theory and Design, Budapest, September 1997. [21] A. van Staveren, J. van Velzen, C.J.M. Verhoeven and A.H.M. van Roermund, “An integratable second-order compensated bandgap reference for IV supply”, Analog Integrated Circuits and Signal Processing, no.8, pp.69-81, 1995. [22] M.Gunawan, “A curvature-corrected low-voltage bandgap reference”, IEEE Journal of Solid-State Circuits, no.28, pp667-670, June 1993. [23] B. Gilbert, S.F.Shu, “Switching Bandgap Voltage Reference”, U.S. Patent 5,563,504, Oct. 1996 [24] M.Tuthill, “A switched current, switched capacitor temperature sensor in CMOS”, Proceedings of the European Solid-State Circuits Conference, pp.228231, Southampton, October 1997. [25] P.Gray and R.G. Meyer, “Analysis and Design of Analog Integrated Circuits”, John Wiley & Sons, Inc., ISBN 0-471-59984-0. [26] M.A.T. Sanduleanu, A.J.M. van Tuijl and R.F. Wassenaar, “Accurate low power bandgap voltage reference in CMOS technology”, Electronic Letters, vol.34., no.10, pp.1025-1026, May 1998.

CHAPTER 6 Low-noise, low residual offset, chopped amplifiers for high-end applications 6.1. Introduction In the previous chapter a chopped transconductance amplifier has been presented. This amplifier is capable of reducing 1/f noise and offset by chopping up to 1MHz but the residual offset can be as high as As explained in section 5.6.6. from Chapter 5, charge injection and parasitic coupling in the input modulator will cause spikes which after amplification and demodulation generate residual offset. In order to minimize the effect, a low output impedance voltage signal source is required. The large output impedance of the OTA, in a follower configuration, driving the input stage, generates spikes at the output which are responsible for the large residual offsets at frequencies higher than 1MHz. In this chapter we are investigated further the possibility of reducing the charge injection residual offset and the increase of chopper frequency up to 10MHz. In some applications, an amplifier has to drive a low-ohmic load with high efficiency. Therefore, a class AB output stage is needed. The output stage introduces its own offset which is added to the total offset. If low offset is a desired constraint, the contribution of the output stage to the total offset should be minimized. For lowvoltage applications large swing is a requirement (Chapter 3). This chapter focuses on the design and the realization of low voltage amplifiers with rail to rail class AB output stages capable of chopping up to 10MHZ, with low noise, high linearity and low residual offset. The generality of the method makes them suited for a large class of designs. A chopper stabilized opamp can be used wherever offset and noise specifications are important. The chopped amplifiers presented in this chapter are primarily meant as amplifiers capable of driving headphones in portable digital audio. In those applications, extra offsets give extra dissipation in the load. Different headphones have different impedance. The impedance of headphones varies between

128

few tens of up to few In a class AB output stage with rail-to-rail output, the low frequency gain of the amplifier depends on the load. The linearity and offset are also variables dependent on the low frequency gain. It is desired to have high linearity and low noise for all possible loads. Accuracy requires high gain which might be difficult to be accomplished in a low voltage design. We are considering also gain enhancement techniques to boost the gain and to improve the accuracy. In portable digital audio we need high dynamic ranges and high accuracy with minimum power. By adding a class AB output stage with strong requirements on linearity, the power consumption will increase. Again the application specific constraints dictate the amount of power needed to fit the design within specifications. In conventional chopper stabilized opamps [1], [2], [3] for 1/f noise and offset reduction, differential amplifiers are being used and bandwidth is limited to few tens of kHz. Switching at the differential output will introduce most of the switching noise and residual offset. Other solutions for offset reduction like ping-pong techniques have the disadvantage of high power consumption and linearity problems [4]. Rail to rail input stages have offset and linearity problems [5]. This chapter presents two chopped amplifiers which circumvent the above mentioned drawbacks. They are designed in sub-micron technologies and are capable of reducing the 1/f noise up to 10MHz without excessively increase of the switching offset. They can drive low ohmic loads with high linearity in high-end audio applications.

6.2. Low pass filtering in a digital audio system. Application specific constraints Fig.6.1 illustrates the output filters of a bitstream D/A converter used in a digital audio interface [6]. System level aspects related to this will be presented in Chapter 7. The 1 bit input of the shift registers is delivered by a digital noise shaper. A

129

sampled data low-pass FIR filter (LPD) attenuates the out of band quantization noise to -55dB. The filter has been realized with weighted current sources controlled by switches. The outputs of the shift register decide if a current source is switched to ground or to the input of the continuous-time analog low-pass filter (LPA). The output of the FIR filter has to be again filtered in order to eliminate the unwanted repetitions of the spectra due to the sampling process. The analog filter has to do the reconstruction of the analog signal without increasing the in-band noise and with high linearity. The extra current source biases the output of the opamp to have maximum possible swing at the load and the right common mode level at the input. The load of the opamp is a headphone. The input signal of the opamp used for low-pass filtering consists of a baseband spectrum and the attenuated aliases centered around multiples of the sampling frequency as illustrated in fig.6.2. The spectra around multiples of sampling frequency are caused by the filtering effect of the hold function performed at the output of the FIR filter. The attenuation of the quantization noise in the first band is close to -55dB, attenuation ensured by the FIR filter. In this particular case, 64 times oversampling is used such that the effective sample frequency is 2.8MHz (see Chapter 7). The continuous time low-pass filter attenuates further the out of band noise delivering to the headphone the baseband audio signal and some extra out of band noise sufficiently attenuated. There are strong requirements in terms of linearity, noise and offset for the operational amplifier. For example, 16 bit D/A interface requires a signal to noise ratio of 98dB. The headphone can withstand offsets up to 12mV without damages but the acoustic efficiency will decrease. A chopper stabilized opamp can be an useful solution for the reduction of noise and offset. In this case, chopping at multiples of sampling frequency is an advantage because of sin(x)/x dips in the spectrum (see fig.6.2) and advantageous for clock generation circuits. Fig.6.3 shows the chopped amplifier with a gain stage and an output stage for low-pass filtering. The two chopper modulators are shown explicitly. Chopping can be considered an internal operation inside the feedback loop. The input of the class AB stage provides the filtering needed to recover the baseband spectrum after chopper modulation whereas the RC combination outside amplifier provides the filtering needed to attenuate the unwanted repetitions of the sampling spectra.

130

6.3. The gain stage One of the requirements of the amplifier is that a low-ohmic load has to be connected to the output of the opamp. Therefore, large output transistors are needed to supply the large output currents. The output stage does not have a large gain. The amplifier is divided in two sections: a high gain section and an output section containing an output stage with a high current drive capability. In fig.6.3 the position of the output stage is after the second chopper. Therefore, the noise and the offset of the output stage can become dominant in the total noise/offset term. As long as the gain of the input stage is sufficiently high, the offset/noise contribution of the output stage can be made negligible small. Another reason to have large gain comes from the attenuation of signal in the class AB output stage which can be as high as 30dB. Fig.6.4 illustrates the input stage of the opamp. The reason to chose a PMOS input stage comes from the necessity to reduce the influence of the substrate noise.

131

The two transistors are in a N-well and the well is connected to the supply voltage such that any substrate interference coupled via the parasitic capacitance to substrate is decoupled to line. The opamp has a single-ended output. The chopper modulators need a differential signal but the required single-ended output imposes the use of a differential to single-ended conversion. This is discussed in the next paragraphs. In fig.6.5 different possible solutions for differential to single ended conversion are depicted. The circuit from fig.6.5.a has been already presented in the previous chapter. The input differential signal current x is injected at the source of M3 and M4. The mirror in top will perform the differential to single ended conversion while M1 and M2 are in saturation and providing the necessary biasing. Chopping at low impedance nodes as shown in the case of the OTA from previous chapter means chopping three times in the signal path. Charge injection in the third modulator is a common mode interference as long as the current mirror has infinite bandwidth. However, the limited bandwidth of the mirror decreases the common mode rejection properties of the circuit. The circuit from fig.6.5.b performs the conversion without the need of a PMOS mirror. M1 and M2 are working in the linear region and the signal conversion is performed at the drain of M2. The cross-quad M3...M6 keeps the drains of the transistors M1 and M2 in steady state at the same voltage, minimizing the systematic offset of the opamp. Besides, it provides a high output impedance needed for large gains. The disadvantage is the large voltage needed at the output node to keep M3...M6 in saturation. In order to drive the output transistors from the class AB stage close to cutoff, we need large swings at the output node of the gain stage. The two current sources from the top are dynamically matched.

132

Fig.6.6.c shows the differential to single ended converter employed in the design of the gain stage. By using this stage, there is no need for a PMOS current mirror in the signal path. We are chopping only twice in the signal path and the accuracy of the current sources Io can be improved by using dynamic element matching. Compared to the previous solution we can have larger swings at the output 2x while chopping only twice in the signal path. The choice of the output stage has to be made in conformity to the low voltage requirements. The source follower configuration from fig.6.6.a gives always a voltage drop of about one to the supply rails and therefore the maximum possible output swing could never be reached. The rail-to-rail configuration from fig.6.6.b has a close to rails swing. The disadvantage is that the gain depends strongly on the load and the transconductance of the output transistors.

6.4. A low noise, low residual offset, chopped amplifier in CMOS As already mentioned, the opamp consists of a gain stage and an class AB output stage. Driving a low ohmic load of with a rail to rail output, the opamp has to deliver some 160mA to the load. To reduce power consumption, a class AB output stage is therefore needed. This section presents a low noise, low residual offset, chopped amplifier with a class AB output stage [7] in CMOS technology.

6.4.1. The class AB control circuit There are many different ways to construct a class AB control circuit. The circuit shown in fig.6.7 combines simplicity and good stability properties [8]. The principle of operation is based on two MOS translinear loops M14, M16, M18, M19 and M15, M17, M20, M21 respectively. The quiescent current in the output transistors is controlled by the two loops. In steady state, with no signal at the input, the currents In and Ip are equal and they are equally divided between M14 and M16. The bias current Ibias ensures a constant voltage at the gates of M14 and M16. Therefore a

133

constant bias current flows through M16 and M17. The presence of the signal in the current In determines an imbalance between the currents In and Ip and the currents flowing through M14 and M15 are not equally divided. This gives a change in the currents flowing in M16 and M17 generating a current flowing into the load. There is always a minimum current flowing in the output stage and the output transistors are never turned off. The minimum current is determined by Ibias and some aspect ratios. Denote Iq the quiescent current in the output transistors and assume In=Ip=2Ibias in steady state. Consider the two MOS translinear loops M14, M16, M18, M19 and M15, M17, M20, M21 respectively under the conditions Then, the relationship between the quiescent current and the bias current is found from:

If denotes the minimum current allowed in the output transistors, then the relationship between and the minimum current is:

134

The factor r depends on the aspect ratios of the transistors in the translinear loop and holds for NMOS as well for the PMOS counterparts M15, M20, M21 and M14, M18, M19 respectively:

Fig. 6.8 shows the simulation of the class AB currents in the output transistors as a function of the voltage across the load The quiescent current has been taken

6.4.2. The circuit principle The principle of the opamp is based on the circuit shown in fig.6.9. It is explicitly shown that the output stage and the OTA share the same current which can be chopped according to the principle illustrated in fig.6.5.c. The In current delivered by the OTA is chopped while the current Ip delivered in top will be dynamically matched to eliminate its offset. By sharing the same bias some of the offset generated by the class AB output stage is eliminated. The remaining offset is generated by the currents Ibias. In fig.6.11, the complete circuit diagram of the opamp is shown. The input chopper M30, M31, M32 and M33 transposes the differential input signal applied to the Plus and Min terminals to the alternate output nodes of the modulator. As a result, the input signal is modulated at odd harmonics of the chopper frequency. The second chopper M34, M35, M36 and M37 demodulates back the signal and modulates 1/f noise and offset at odd harmonics. In order to cancel out the noise and offset of M8 and M9, the-third chopper M38, M39, M40 and M41 matches dynamically the two branches. A low voltage cascoded mirror M3, M4, M5 and M6 performs a differential

135

to single ended conversion for the signal which is applied to the output stage. The class AB output stage uses two MOS translinear loops to control the current in the output transistors. The offset of the output stage is mainly caused by mismatch between the currents of M22 and M26. In fig.6.10 the simulated transfer of the opamp loaded with is presented. The open loop gain is 74dB and the phase margin is 81° for a GBW of 3.2MHz. The quiescent current of the output stage has been chosen for linearity reasons. The output transistors have large dimensions and can deliver 160mA short circuit current in a rail to rail configuration without latching.

136

137

6.4.3. Measurements The chopped amplifier has been realized in a CMOS digital technology with one polysilicon layer and two metal layers. Special layout techniques have been used to reduce the mismatch and charge injection of the switches. Ten arbitrarily chosen samples, have been measured. The two complementary chopper signals are generated by a pulse generator with complementary outputs and adjustable rise and fall times. The connections to the testing board are made with BNC-SMD coax cable terminated to reduce reflections. A bias current of is used to bias the amplifier.

a. Noise measurements In order to verify the reduction of 1/f noise in the baseband, a spectrum analyzer measures the spectrum of the amplifier configured as an amplifier with 40dB gain as depicted in fig.6.12. The reason was the noise floor of the analyzer, higher than the noise of the opamp. The two resistors give negligible contributions to the total noise. At the output, the spectrum analyzer measures the noise of the amplifier amplified with 40dB in a bandwidth of about 100KHz which is exactly the bandwidth of the low pass filter in the D/A interface.

A HP-VEE program has been used to make possible time averaging of measurements. The measurements have been done with different chopping frequencies and different rise and fall times. In fig.6.13, the output noise spectrum is shown. The chopping frequency is 1MHz, situation showing the reduction of 1/f noise. At input, the residual noise is the white noise of the amplifier, attenuated with about 3dB compared to the unchopped case. The rise and fall times of the chopper modulator have an important effect on the reduction of 1/f noise. The larger the transition times, the more important becomes the 1/f noise from the switches which have small dimensions and inherently large noise. In fig.6.13 the rise and fall times of the chopper signals are 5ns. Chopping at 10MHz, the influence of the transition times on the chopper signals becomes important and the 1/f noise is not reduced completely with transition times in the interval tr=10ns...20ns. However, chopping at 10MHz with the 1/f noise can be

138

completely removed. The residual thermal noise at the output of the opamp is about and the input noise of the opamp 40dB less. When the load resistance is the maximum output voltage is The dynamic range of the amplifier configured as a follower in audioband is 111dB when chopping at 1MHz. The S/N+THD figure (SINAD) is about 10dB lower due to distortion reasons.

b. Offset measurements The amplifier has been configured as a follower for offset measurements. The static offset can be measured directly at the output. For dynamic measurements the output is low pass filtered and a digital measures the output offset as illustrated in fig.6.14. Ideally only the offset of the output stage should remain but, second order effects like mismatch of the switches and non-ideal behavior of the

139

chopper signals are the cause of the residual offset when the chopper frequency increases. The measured static offset has a mean value of 1.7mV with a standard deviation For the measurement, ten arbitrarily chosen samples have been considered. When choppers are activated, the measured residual offset can be plotted as a function of chopper frequency. This is shown in fig.6.15. The two graphs correspond to different transition times generated from two different pulse generators. The upper curve corresponds to a 6ns transition time and the lower curve corresponds to 15ns transition time. Up to 8MHz, the residual offset is lower than This is mainly generated by the output stage. In this frequency range, the transition time of the chopper signal is not important. The residual offset is virtually independent of a change in rise or fall time. This shows again that offset can be treated just as low frequency noise. At higher frequencies, the larger the transition time, the higher the offset. Fig.6.16 shows the offset of the ten samples at different chopping frequencies.

140

c. Linearity measurements The linearity measurement setup is presented in fig.6.17. The THD of the opamp was measured as a function of amplitude and frequency. The input sine-wave has been supplied by a low distortion oscillator. THD of the input signal is -90dB which determines the lower limit of the measurable distortion. The THD is independent of the chopper frequency and that is why all linearity measurements have been done with 1MHz chopper frequency. To use the full swing at the output the amplifier has been configured as an inverting amplifier with 0dB gain. The linearity measurement versus amplitude at 1KHz is illustrated in fig.6.18. When the load is clipping occurs at 1.35V output amplitude. With load, clipping occurs close to the supply voltage at 1.65V output amplitude. The lowest input signal handled by the the distortion analyzer is 60mV an that is why the THD is not measured at lower amplitudes. For high ohmic loads, the THD is better than -91dB for 1.5V voltage swing. For low ohmic loads, the THD is better than -83dB. The linearity at low amplitudes is impaired by cross-over distortion.

141

With high ohmic loads, the linearity of the amplifier is better because the output stage has a higher gain and does not have to deliver large currents to the load. The linearity depends on the quiescent current flowing in the output transistors. The current consumption of the opamp is mostly determined by the quiescent current in the output stage. For the measurements has a value of The THD as a function of frequency is illustrated in fig.6.17. It was measured in the audio band with two different loads. The output signal amplitude is 0.8V. The linearity with a load at 1KHz is better than -88dB and -80dB for a load. At high frequencies, the loop gain falls and the effect of the feedback becomes less effective. The complete summary of performance is shown in Table 6.1.

142

The area of the chip is about and a chip photomicrograph is shown in fig.6.20. The power consumption is 1.8mW from a 3.3V power supply. It can work down to 1.8V with reduced swing and DR being able to deliver 160mA with a rail-torail output in a load without latch-up. The class AB control circuit of the output stage is limiting the lowest value of the supply voltage at about In order to work at lower supply voltages another class AB control circuit has to be considered.

6.5. A low noise, low residual offset, chopped amplifier in CMOS This section presents a low noise, low residual offset, chopped amplifier in CMOS technology. It consists of a chopped transconductance stage and a new class AB stage capable of working at 1.3V supply voltage. By using gain boosting and low voltage techniques, the gain of the amplifier is boosted at 91dB for a load.

6.5.1. The class AB control circuit The chopped amplifier is divided in two parts: the gain stage and the output stage capable of driving low-ohmic loads. To be able to go to lower supply voltages, a new class AB control circuit is introduced. The output stage is shown in fig.6.21 and consists of an input common-mode current source of the pair M14 and M15, with active load, and the class AB control circuit. The output transistors M35, M36 are driven in phase from high impedance nodes. To control the output currents, a

143

feedback control has been chosen. A scaled copy of the current in the output devices flows through M33 and M37. The two copies are forced in the transistors M34 and M32. The feedback loop around the differential amplifier M14 and M15 will enforce the condition:

The transistors M34 and M35 can work in weak inversion or strong inversion. In both situations the class AB control is effective.

a. Weak inversion behavior If the transistors M34 and M32 are well matched and at the same temperature in weak inversion, forward saturated then the condition (6.4) can be rewritten as:

where n is the slope factor, is the thermal voltage, represents the gain factor, m the scaling factor and is a dimensionless constant. This condition holds true as long as The constant depends on technology and some physics constants.

144

In eq. (6.6) represents the surface potential and the Fermi level potential. In most cases, the constant can be approximated with:

The transistors M32 and M34 are considered matched and at the same temperature. The body effect has been neglected. One can see that for a given temperature, the product of the left hand side terms from (6.5) is constant. The class AB behavior has been simulated and shown in fig.6.22. If only the product rule would have been implemented, the residual current is not limited. Hence, if one of the transistors would conduct a lot of current the other one works at very low currents and the gate-source voltage associated with it becomes low. The circuit that drives the gates of the output transistors should have some 500÷600mV voltage room to keep all of its transistors in saturation. That is why, in this approach we need a well defined residual current in the output transistors. The two extra current sources IMIN subtract a small current from the copied output currents coming from M33 and M37. This causes in all situations a shift upwards for the current flowing in the output transistors providing the required minimum current.

b. Strong inversion behavior If the transistors M34 and M32 are working in strong inversion the class AB control of the output transistors is also valid. This time the condition (6.4) can be rewritten as:

This equation is valid if only

145

6.5.2. Circuit principle The final version of the circuit is illustrated in fig.6.21. The weak inversion variant of the class AB control has been chosen for implementation. The large bandwidth mirror M7, M8, M13, M14 and M15 used for differential to single ended conversion, is being chopped at low impedance nodes. The single ended signal current generated at the output of the mirror acts as a common-mode current of the differential pair M14 and M15 being divided afterwards in two branches. Due to the equal splitting, the output transistors M36 and M35 are driven in phase. The only sources of offset and 1/f noise remains the output stage and mismatches between the two signal branches. There are few reasons to desire a high gain for the transconductance stage. For low ohmic loads, the output stage attenuates the signal up to -12dB. Hence, the open loop gain of the amplifier drops down. If the transconductance stage has large gain, the offset and 1/f noise generated in the output stage can be neglected. In modern processes, the output resistance of the transistors is very low. Simple cascoding does not offer a solution in this case because of the large voltage headroom needed. Besides, we want large swings at the output nodes of the transconductance stage in order to ensure that output transistors are driven out of saturation for large swings. A gain boosting circuit M16, M17, M22 and M23 has been added to the cascode transistors M18, M19, M20 and M21. Its current consumption is limited to few nanoamperes and the noise and offset of the gain boosting transistors is negligible. At the output node, we can go as low as Because the gain boosting transistor works at low current, in weak inversion, the gate-source voltage of M16 is close to and therefore we can go as low as 600mV from the ground rail. The same applies to the PMOS counterparts. The gate of the transistor M14 is connected to a constant voltage and the differential amplifier will enforce a constant voltage at the gate of M16. The gain boosting circuit limits the minimum supply voltage at about 1.4V :

146

147

6.5.3. Simulation results The circuit has been simulated by using a CMOS process. A worst case situation with a low ohmic load of has been considered in all cases. The opamp is compensated with two Miller capacitors of 5pF and 2.5pF, respectively, to account for the area differences of the two output transistors M35 and M36.

a. Open loop gain and stability The open loop gain of the circuit is presented in fig.6.24 under the condition of a heavy load of 300pF load capacitance, respectively. The opamp has a gain bandwidth product of 1.8MHz, 91dB low frequency gain and the phase margin is 87 degree and 83 degree respectively. By steering the output transistors in triode region, to have a close to rail output, instability could occur. This is caused by the decrease of the gain and the shift of the second pole of the amplifier. In order to prove that the circuit is stable in all possible situations, a transient analysis has been performed for different amplitudes at the output as shown in fig.6.25 This simulation has been done with different possible amplitudes of the signal in a follower configuration and shows no ringing or overshoot at the output. For a load, the maximum output voltage is close to the rails within 360 millivolts.

b. Noise and offset properties Fig.6.26 illustrates the spectral density of the input referred voltage noise for the two opamps. In the case of the opamp implemented in a CMOS process, the 1/f noise properties are worse in comparison to the opamp implemented in CMOS, although the dimensions of the input transistors are the same and the input

148

stage is biased at the same current level. We have mentioned in Chapter 3 that in deep sub-micron technologies, the transistor effect takes place more at the surface and therefore the 1/f noise will increase. The spectral density of the white noise in both cases is Offset simulations show a static offset of 1.67mV. Chopping at 10MHz, the simulated residual offset is but at 1KHz chopping, the simulated residual offset is about Given the fact that 1/f noise is reduced by chopper modulators and the white noise has the same spectral density at low frequencies we can conclude that after chopping, the two designs have the same noise power in the audio band. For the same supply voltage, the signal power is higher in this case due to large voltage swings allowed at the output.

149

c. Linearity simulations The linearity of the opamp depends on the load and frequency. In fig.6.26 the THD as a function of the output amplitude is shown. This simulation was done at 1KHz input frequency and load resistance. THD is better than -85dB for signal amplitudes close to At low signal amplitudes the cross-over distortion takes over and the linearity gets worse. At high amplitudes clipping occurs and again the harmonic distortion increases. In fig.6.27 the THD versus frequency has been considered. The amplitude of the signal is close to and the load resistance is As expected, the harmonic distortion increases at higher frequencies due to the reduction of the loop gain. The power consumption of the opamp is 1.5mW from a 3.3V power supply voltage being dominated by the power consumption of the class AB output stage.

150

The opamp can work down to 1.4V with reduced swing and dynamic range. A summary of the simulated performance is shown in Table 6.2.

6.6. Conclusions This chapter dealt with low-noise, low residual offset, chopped amplifiers for high-end applications. In the previous chapter a chopped transconductance amplifier has been presented. This amplifier is capable of reducing 1/f noise and offset by chopping up to 1MHz but the residual offset can be as high as Here we have investigated further the possibility of reducing the charge injection residual offset and the increase of the chopper frequency up to 10MHz. In some applications, an amplifier has to drive a low-ohmic load with high power efficiency. Driving a low ohmic load of with a rail to rail output, the opamp has to deliver some 160mA to the load. To reduce power consumption, a class AB output stage is therefore needed. The output stage introduces its own offset which is added to the total offset. If low offset is a desired constraint, the contribution of the output stage to the total offset should be minimized. This chapter focuses on the design and the realization of low voltage amplifiers with rail to rail class AB output stages capable of chopping up to 10MHZ, with low noise, high linearity and low residual offset. The generality of the method makes them suited for a large class of designs. The chopped amplifiers presented in this chapter are primarily meant as amplifiers capable of driving headphones in portable digital audio. In those applications, extra offsets give extra dissipation in the load. It is also desired to have high linearity and low noise for all possible loads. The first amplifier has been realized in a CMOS. Measurements show a dynamic range of 111dB for the amplifier

151

configured as a follower when chopping at 1MHz. For high ohmic loads, the linearity is better than -91dB for 1.5V voltage swing. For low ohmic loads, the THD is better than -83dB. The power consumption is 1.8mW from a 3.3V power supply. The class AB control circuit of the output stage is limiting the lowest value of the supply voltage at about 1.8V. The second amplifier designed in CMOS technology has a new class AB output stage which can work at lower supply voltages. The open loop gain of this amplifier has been increased to 92dB by using gain boosting techniques. Offset simulations show a static offset of 1.67mV. Chopping at 10MHz, the simulated residual offset is but at 1KHz chopping, the simulated residual offset is , . The linearity of the opamp is better than -85dB for signal amplitudes close to The power consumption of the opamp is 1.5mW from a 3.3V power supply voltage being dominated by the power consumption of the class AB output stage. It can work down to 1.4V with reduced swing and dynamic range.

152

REFERENCES [1] A. Bakker and J.H. Huijsing, “A CMOS chopper opamp with integrated low-pass filter”, Proc. ESSCIRC’97, Southampton, UK, Sept. 1997, pp. 200-203. [2] K.C. Hsieh, P.R.Gray, D.Senderowicz, D.G. Messerschmitt, “A low-noise chopper stabilized differential switched capacitor filtering technique”, IEEE J.Solid-State Circuits. vol. SC-16, no.6, Dec.1981, pp.708-714. [3] C. Menolfi and Q. Huang, “A low-noise CMOS instrumentation amplifier for thermoelectric infrared detectors” IEEE J.Solid-State Circuits. vol. 32, no.7, July 1997, pp.968-976. [4] I.E. Opris and G.T.A. Kovacs, “A rail to rail ping-pong opamp”, IEEE J.SolidState Circuits, vol. 31, no.9, Sept. 1996, pp. 1320-1324. [5] W.C. Wu, W.J. Helms, J.A. Kuhn and B.E. Byrkett, “Digital-compatible highperformance operational amplifier with rail to rail input and output ranges”, IEEE J.Solid-State Circuits. vol. 29,n0.1, Jan.1994, pp.63-66. [6] D. K. Su, B. A. Wooley, “A CMOS Oversampling D/A Converter with a CurrentMode Semidigital Reconstruction Filter”, IEEE J.Solid-State Circuits. vol.28, no.12, Dec. 1993, pp.1224-1223. [7] M.A.T. Sanduleanu, A.J.M. van Tuijl, R.F. Wassenaar, M.C. Lammers and H. Wallinga “A low noise , low residual offset chopped amplifier for mixed level applications”, Proceedings of the 5th International Conference on Electronics, circuits and Systems ICECS’ 98, Lisbon, Portugal, Sept. 1998, pp.233-236. [8] D.M. Monticelli, “A quad CMOS single-supply opamp with rail-to-rail output swing”, IEEE J. Solid-State Circuits, vol.SC-21, no.6, pp.1026-1034, Dec.1986. [9] M.A.T. Sanduleanu, A.J.M. van Tuijl, R.F. Wassenaar, M.C. Lammers and H. Wallinga “Low-Power Low-Voltage Chopped Amplifier with a New Class AB Output Stage for Mixed Level Applications”, Proceedings of the 9th annual IEEE Workshop on Circuits, Systems and Signal Processing ProRISC’ 97,Mierlo, The Netherlands, Nov.1997, pp.519-525.

CHAPTER 7 A 16-bit D/A interface with Sinc approximated semidigital reconstruction filter 7.1. Introduction Low-power techniques at the highest level of abstraction as architectural level and algorithmic level can lead to power savings which cannot be obtained unless the complete system is taken into study. This chapter presents a 16-bit D/A interface with Sinc approximated semidigital reconstruction filter as an example of a system where accuracy and noise give constraints on the power consumption of the system [1], [2]. As we will see, reducing power in the analog domain the power in the digital domain is also reduced. Practical D/A interfaces suffer from circuit nonidealities such as component noise, mismatches, device nonlinearities, substrate bounce and clock jitter which can impair the resolution of the complete system [3], [4], [5], [6], [7]. Because of those imperfections, the analog reconstruction is the most difficult analog building block in a DSP system. In a switched capacitor D/A the exponential charge transfer is inherently nonlinear generating too much distortion [8], [9], [10]. Besides we need two opamps for charge summing and low-pass filtering. In this respect, a current driven D/A it is a better choice [11]. This chapter presents a differential, currentdriven 16-bit D/A interface with Sinc approximated semidigital reconstruction filter. An important problem to be discussed in the chapter is the optimization of the number of coefficients. An FIR filter with a large number of coefficients needs a large number of additional digital circuitry increasing the area, power consumption and complicating more the clock distribution. A large number of coefficients, requires more shift registers and therefore, the power in digital domain will increase. Moreover, the accuracy of the coefficients is subject to process tolerance caused by rounding of the small coefficients and quantization to the process grid span [11]. A large number of coefficients implies big differences between coefficients. The

154

accuracy of the smaller coefficients is impaired with consequences on the stop-band rejection. By using Sinc approximation in the frequency domain and an iterative procedure one can reduce the number of coefficients taking into account process tolerances such that the out of band rejection of noise requirement is met. Compared to the standard solutions we have reduced about four times the number of the coefficients for the same requirements. With only 25 coefficients we get more than 50dB stopband rejection of out of band noise. A differential solution is proposed to reduce the digital crosstalk and to increase the output signal swing. An analysis of the matching, noise and clock jitter is provided. The D/A interface has been realized on chip in a 0.8mm CMOS 5V technology and the measurement results are presented. Another approach is the Sinc approximation method in the time domain. By using this method, power can be shifted from the digital domain into analog domain and the best partitioning of the system in terms of power can be found. The price paid is an increase of the filter complexity with the benefit of keeping the same power consumption in the analog part. The principle of the method is discussed and an example is given.

7.2. Bitstream D/A conversion system with time discrete filtering Fig.7.1 illustrates the block diagram of a bitstream D/A conversion system[12]. This system consists of a digital filter, a noise shaper and a reconstruction

155

filter. Eventually, the power amplifier can be integrated on the same chip. In the digital filter the data rate of the input digital word is increased by interpolative upsampling 64 times. The filter interpolates the input signal and calculates intermediate points. The low-pass filter limits sharply the audio-band at 20KHz. In order to reduce the quantization noise in the baseband two techniques are used: oversampling and noise shaping. By oversampling in the digital filter, the quantization is performed at higher clock rates and the resulting quantization noise power is spread over a larger bandwidth. This yields lower noise in the baseband. Noise shaping is a technique used to reduce the quantization noise in the audioband, by shaping the quantization noise out of the baseband. In combination with oversampling this method gives sufficient reduction of the quantization noise to realize high accuracy systems. In the 1-bit D/A converter, the digital sequence present at the output of the noise-shaper (1,0,0,1,0...) it is translated into an accurate two-level analog signal (A,-A,-A,A,-A,...) with high linearity. In the same block, a sampled data FIR filter (LPD) will suppress the out-ofband noise. To reduce harmonic distortion and intermodulation products in the output power amplifier, the level of the high frequency quantization noise has to be lower than -50dB. A first order, continuous-time analog low pass filter (LPA) will reconstruct the signal by attenuating the spectral repetitions at multiples of sampling frequency. In fig.7.1 the signal and the noise spectra of the D/A system are shown. For simplicity, the oversampling frequency is not drawn at the right scale (4 times instead of 64 times). Fig.a shows that a sampled signal consists of an infinite sequence of the original spectra shifted by multiples of Therefore also the noise power is shown up to Oversampling (see fig.b) spreads the noise over a larger frequency band and places the signal spectra further from each other. The noise shaper shapes the noise out of the baseband to higher frequencies (see fig.c). In fig.d+e, the signal at the output of the FIR filter (doted) and the signal at the output of the LPA filter (thick lines). The noise at high frequencies is filtered by the time discrete filter. The final operation, i.e. the low-pass continuous-time filtering, removes the undesired spectral repetitions from the signal.

7.3.

modulators and noise shaping

The specifications of the reconstruction filter are related to the properties of the noise-shaper. In this section the performance of the noise shaper with respect to the in-band noise is discussed.

7.3.1. Noise model The quantizing error which is introduced into the signal is modeled by the addition of white noise as illustrated in fig.7.2. The one bit quantizer maps any non-negative input value onto A and any negative input onto -A. So the amplitude of the output signal is fixed and not dependent on the input signal level. In the noise model for the one bit quantizer the signal dependent gain of the quantizer is

156

represented by the gain constant As the quantization step q is equal to 2A the quantization noise power of the one bit quantizer is given by:

Within the noise model the noise is not correlated with the signal and the noise PSD of the noise introduced by the quantizer is uniform distributed in the fundamental interval as shown in fig.7.3 and given by:

7.3.2. Sigma-delta modulator A one bit code can be generated by means of a sigma-delta modulator . In a sigma-delta modulator the loop filter G is placed in the path of the input signal (see fig.7.4). If G(z) is the transfer function of the loop filter G we have:

157

Eq. (7.3) shows that the signal transfer of the sigma-delta modulator is:

which approximates 1 in the signal band where The noise PSD at the output is inversely proportional to and the noise contribution of the modulator vanishes at those frequencies for which In the implementation of the modulator, an integrating loop filter is applied which results in minimal noise density at DC. The output noise density is shaped by means of feedback and the noise transfer is:

The overall gain of the signal that results from quantization is equal to one. The value of the gain constant can be obtained from the calculation of the power at the output of the quantizer, which is based on the integration of the power spectrum of the output noise. The total noise power at the output of the noise shaper is obtained from the integration of the power spectral density:

7.3.3. Noise transfer There is no difference between a noise shaper and a sigma-delta modulator. However, in the realization, the place of the loop filter is the only distinction. For this D/A converter a sigma-delta modulator has been used since the loop filter function of a properly working device was available. The design of the modulator will not be discussed here since it is a separate topic. For the following sections it is important to know only the transfer function of the loop filter The order of the modulator is a trade-off between accuracy and stability. Large order modulators give more attenuation for the noise in the baseband but stability becomes worse. A third order modulator will be the choice for this design. The loop filter has a transfer (see reference [12]) given by:

158

For the constants of eq. (7.7), the following values have been used: k = 1.5, r = 0.763 and t = 0.0303. The gain constant has been numerically computed and its value is 0.95. Now, we have the transfer function of the noise as:

The noise transfer plotted in the fundamental interval is illustrated in fig.7.5 and it will be used in sizing the coefficients of the FIR filter. More about noise shapers can be found in reference [13].

7.4. Semidigital FIR filter principles Consider fig.7.6 where the basic principle of the current driven D/A interface is shown [11]. As explained in section 6.2, it consists of a FIR semidigital filter with 1

159

bit digital delay units and analog tap weights followed by an analog post-filter [14]. The input of the D/A interface is a bitstream signal already noise-shaped. The current source needed to prescribe the common mode level at the input introduces noise. Integrating on the same chip analog and digital circuits, the substrate noise can become a problem in the single ended approach. That is why we have introduced the differential D/A from fig.7.7. The 1-bit output of the noise-shaper with a sample frequency of 2.8MHz will pass through the 1-bit digital delay units implemented with shift-registers. The outputs of the shift registers are controlling the switches of the current taps directing the current to the negative or positive input of the opamp. The noise-shaper and the upsampling filter are not integrated on the same chip. The FIR filter has unity transfer for the baseband signal, with minimum ripple and attenuates the out-of-band quantization noise. Due to oversampling, the analog post-filter can be simply reduced to a first order filter thus simplifying the integration on-chip of the digital and analog functions. The coefficients of the filter implemented with weighted current sources, have the property that The filter is symmetrical with respect to the middle coefficient. Due to the differential approach if a current is flowing towards the positive input of the opamp, a negative current is flowing towards the negative input of the opamp. Therefore, the current is not being dumped to ground as will be in the case of single-ended solutions [see fig.7.6]. The differential approach has been used to make larger voltage swings at the output. The effect of digital crosstalk and the glitches in the output current will be minimized. Given the data x[n] at the input of the shift registers, the currents at the input of the opamp are:

160

The filter coefficients are implemented by using current sources with different weights The output of the shift-registers is time continuous due to the holding property. During sampling interval, the current is delivered continuously to the output of the FIR and therefore zero-order hold effect is being encountered. The analog continuoustime first order RC filter attenuates further the ripple present in the output of the FIR filter. Given the pole of the low-pass filter and the sampling frequency the total transfer function of the FIR and continuous time analog filter including the zero-order hold effect will be:

The total transfer is considered when the coefficients of the filter are being calculated. The cutoff frequency of the low-pass filter should be chosen such that the pass-band response is not impaired.

7.5. Semidigital FIR filter design To design the time-discrete filter, the effect of the noise-shaper and the lowpass continuous time analog filter have to be considered. The noise shaper and the oversampling ratio are specified and all the requirements and conditions are known. The next step is the calculation of the coefficients. But how many coefficients are necessary? To answer this question some boundary conditions will be introduced. The area that is available limits the number of coefficients to about 100 irrespective to the implementation which is chosen. Since the coefficients are implemented by weighted currents this imposes a limitation also. The ratio between the largest and the smallest coefficient is limited by accuracy. A large number of coefficients implies big differences between coefficients. The accuracy of the smaller coefficients is impaired with consequences on the stop-band rejection. There are also a few conditions for the signal transfer function of the filter. First of all, the ripple in the audio-band has to be very small (< 0.1 dB). A small droop (0.5 dB) is allowed since the digital filter can correct for this non-ideal behavior. In the design of a discrete time filter suitable for audio signals, phase is an important parameter too. In a digital lowpass filter design, a linear phase can be obtained by a symmetric impulse response. Odd or even numbers of coefficients can be used. The main requirement is to achieve a stop-band rejection for the noise of more than 50dB.

7.5.1 Calculation of coefficients In the literature, a number of standard algorithms for digital filter design are extensively discussed [15]. The methods are based on Fourier series, the frequency sampling method, the Remez exchange method and equiripple designs. All these methods cannot be used since the design of this filter is not a standard design but the product of a time discrete filter and the transfer function of the noise shaper. Such

161

methods generate a large number of coefficients and over-specifications. In order to take into account that the noise transfer will be influenced by the noise-shaper, the semidigital filter and the low-pass analog filter, we have developed an iterative method to design the filter based on Sinc approximation of the impulse response as shown in fig.7.8. Here, we have represented the transfer of the noise shaper NS, the transfer of the semidigital filter LPD and the analog low-pass LPA. The noise transfer is denoted NS*LPA*LPD. The simulations were performed with a routine written in MatLab. This allows to optimize the number of the coefficients and to take into account the effects of matching on the response. First, the time domain is divided into N equal steps and the symmetric coefficients are calculated by using the division of sin(x)/x. The Sinc function has been windowed with a rectangular window. The computer is used to perform this calculation by employing the Z-transform. For the noise shaper the transfer function is also calculated by using a Z-transform routine. Since the continuous time low-pass filter may not influence the characteristic at the audio-band, its cutoff frequency is set to 140 kHz. In this way it is possible to filter the spectral images at multiples of the sample frequency sufficiently. Further, these three functions are plotted on a logarithmic scale and therefore they can be easily added. The Sinc function has been truncated to the first five lobes but the -50dB requirement for the out of band noise is not met. By taking more coefficients, the stop-band rejection becomes better than -55dB, as shown in fig.7.9.

162

Simulations have been carried out to determine which part of the Sinc function is important and how many coefficients are necessary in the optimum case. The number of lobes from which the Sinc is approximated changes the transfer characteristic of the filter. It is also important to ensure that at zero crossings of the Sinc function the approximation has also a zero. At that moment the next sample reaches its maximum value. Using more coefficients to approximate the same part of the Sinc means decreasing the time step. This is equivalent with increasing the sample frequency in the case of a digital filter. The results is a smaller pass band of the LPD filter characteristic without changing its shape. It turns out that just the main lobe of the Sinc function is the most important part to approach the desired filter characteristic. With no more than 25 coefficients this main lobe can be approximated such that the required attenuation of more than 50dB is reached. Actually there are 27 coefficients but two of them are zero. The calculated coefficients are given in Table 7.1.

163

To be noticed the small ratio between the largest and the smallest coefficient which is about 12. The approximation of the main lobe is shown in fig.7.10. The first and the last coefficient are zero. The transfer characteristics for the noise and signal are illustrated in fig.7.11. The rejection of the out of band noise of the noise characteristic (NS*LPA*LPD) is better than -53dB up to the higher end of the fundamental interval A sensitivity analysis will show that in the worst case the required -50dB is fulfilled. For the signal transfer a smooth roll off dB in the audio-band) can be seen. The zoomed characteristic of the signal in the audio-band is shown in fig.7.12.

164

The sharp digital filter will correct the droop of the characteristic along with the sin(x)/x distortion at the end of the pass-band. The gain error can be corrected by multiplying the coefficients with a constant factor.

7.5.2

Windowing

In the design of a FIR filter windowing functions are used to reduce the infinite length of the impulse response. By applying a rectangular window on the impulse response, i.e. just deleting a number of the coefficients, there will be oscillations in the frequency response due to Gibbs phenomenon. In order to reduce the oscillations different window functions can be applied. Widely used window functions for example are Bartlett, Hamming, Hanning and Kaiser (see fig.7.13).

165

By multiplying the calculated Sinc coefficients with a window, the transfer becomes slightly better. After this operation the ratio between the smallest and the largest coefficient increases tremendously. For a digital filter this is not a problem because the coefficients are represented by a number of bits. In this application this means a large ratio between components. Moreover, due to windowing, the transfer function becomes more sensitive to rounding. That is why no windowing technique is used for the calculation of the coefficients.

7.5.3 Filter response and the coefficient quantization The coefficients of the filter are subject for mismatch, rounding and quantization to the incremental grid span of the process. This will affect the stop-band attenuation of the filter with some influence on the pass-band also. We would like to obtain specifications for the coefficients of the filter such that we get sufficient suppression of the quantized noise out of audio band without affecting the pass-band. Coefficient non-idealities generate an erroneous transfer function:

The deviation of the filter transfer depends on the random coefficient errors

When the random coefficient errors are Gaussian distributed the deviation of the filter transfer is Rayleigh distributed [16] with a mean value and a standard deviation given by.

In eq.(7.14) N is the filter length and represents the standard deviation of the coefficients due to process mismatch. The deviation of the filter transfer has three main causes: rounding of small coefficients, quantization of the coefficients to the finite incremental grid span and mismatch. Those effects are treated separately.

7.5.4 Rounding small coefficients For FIR filters with a lot of coefficients we have to deal with large ratios between the largest and the smallest coefficient. It is necessary to round small coefficients to fit to the smallest feature size of a transistor. Rounding of small coefficients will introduce quantization errors with consequences on stopband rejection. The response of the filter in the pass-band it is influenced only by large coefficients and the rounding procedure has no influence on the pass-band. In order to

166

estimate the stopband rejection we have to consider the size of the minimum coefficient As a rule of thumb, the maximum achievable stop-band rejection is:

To have a stopband rejection of about -50dB the rounded coefficients have to be smaller than In our case, the smallest coefficient is 0.0054 and rounding is not a necessity. In the design procedure we try to keep the number of the coefficients as low as possible in order to avoid big differences between the largest and the smallest coefficient.

7.5.5

Matching of coefficients

In contrast to a digital filter, where the only important error is caused by truncation or rounding due to the finite word length, in the time discrete filter the mismatch of the coefficients will impair the frequency characteristic. In practice the analog coefficients are realized by using current sources and their values will deviate from their nominal value. The condition for the stop band noise has to be met under mismatch conditions. Only Monte-Carlo analysis can reveal the effect of mismatches on the transfer characteristic. In fig.7.14 the realization of the coefficient is shown. A floating current source improves the matching between the PMOS and NMOS branches. The current related to the same coefficient The mismatch of the coefficient is a consequence of mismatch and mismatch. Consider a multi-parameter function From multi-parameter sensitivity analysis we have:

167

Regarding the current as the multi-parameter function, the mismatch of the coefficient is found as a function of individual mismatch terms of transistors Mo and Mk neglecting the contributions of the cascode transistors. For a single ended current mirror, the inaccuracy of the coefficient is found from:

The lengths of the transistors Mk are taken equal and therefore we get:

The maximum value of the width of the transistor MO is limited from area requirements. Consider now the current mirror with PMOS and NMOS outputs. The transistors Mkn and Mkp have the same dimensions. Denote and the mismatch of the PMOS and NMOS branch respectively. Hence, the mismatch of the coefficient in the differential approach is given by:

Denote the mismatch term:

Then the mismatch of the coefficient

in the differential approach becomes:

This result in conjunction with eq.(7.14) can be used to have a first estimation of the errors in terms of and of the transfer H. The Monte Carlo optimization procedure described later in section 7.5.7 is based on

7.5.6 Quantization to the incremental grid span The IC processes have a finite incremental grid span. For example in a 0.8mm CMOS process, the finite incremental grid span is in the order of The dimensions of the devices (width and length) have to be quantized to the grid span.

168

Rounding introduces a length uncertainty of and the error can be considered uniformly distributed in this interval. Compared to the errors introduced by mismatch, quantization to grid has a negligible influence on the filter response. Again eq. (7.14) can be used to show this effect.

7.5.7 Simulations Equation (7.21) shows that each coefficient has a standard deviation which depends on W and L. Generating filter characteristics with errors for coefficients, we cover about 99.75% of the possible cases. In MatLab, there are no standard routines to perform a Monte Carlo analysis. However, it is simply to generate normal distributed random numbers with mean 0.0 and variance 1.0. Therefore it is possible to combine this random number generator with the previous derived equation, to calculate what the effects are on the filter characteristic. The random number determines also if the coefficient is rounded up or down respectively.

In fig.7.15 the simulation results for the optimal widths and lengths of the transistors are shown. The inaccuracy of the noise transfer increases at the end of the fundamental interval. In this region, the effect of the noise shaper on the noise transfer is less effective and attenuation of the noise is ensured by the FIR filter. In the worst case we have -61dB rejection for the noise. The signal transfer is slightly affected by the matching properties.

7.6. Noise properties of the D/A interface The semidigital FIR filter and the low pass analog filter will increase the amount of noise at the output. Another source of noise is the clock jitter. We are considering here only the noise of the current sources and the clock jitter. The opamp noise can be easily quantified. As long as the effect of the noise generated in the analog part of the D/A converter is larger than the quantization noise, the resolution of the converter will be impaired. One should be able to quantify those effects and to design a low noise analog interface.

169

In fig.7.16 the realization of the coefficient has been considered. Due to the differential approach, the current sources are both present when the coefficient is active and gives a contribution to the output. The white and 1/f noise from the cascode transistors can be neglected. The noise sources which give a significant contribution at the output are shown explicitly.

7.6.1 White noise considerations The effect of this noise at the output can be considered when the input PDM signal represents a pure sinusoidal waveform represented with ones and zeros with a density p and 1-p respectively. During the period Ts, the coefficient is active and the current Ii+noise flows in the parallel connection R and C. Because the signal is periodic, the switch will be on and off periodically. The noise transfer to the output, differs for pMOS and nMOS current sources as:

In the noise transfer appears the transconductance of the transistor configured as a current source and the pole determined by the RC combination in the low pass filter. The power of the output white noise due to the current Ii during the interval Ts can be determined from the noise bandwidth of the circuit and the power spectral density of the voltage noise and respectively:

Denote the audioband from 0 to 20KHz. From fig.7.16 we can find the relationship between the oversampling ratio in the converter and the interval

170

During this interval, the current Ii can be dumped to the ground or can be used to make larger swing in the differential approach. The noise and the current Ii are available only a fraction from the total Tsig. The noise has to be considered in the audioband. Therefore, the power of the noise available at the output in the interval Tsig will be:

The pulse shown in fig.7.16 is not a singular pulse and will appear in the interval Tsig according to the density of ones in the representation of the sinusoidal signal in this interval. Given the fact that the density of ones and zeros is p and 1-p respectively and the number of total samples is Q, the total noise generated by the pMOST and nMOST current sources due to the coefficient in the Tsig becomes:

The total noise can be found by adding all the individual noise contributions of the coefficients in the interval Tsig:

The current Ii is a fraction of the total current needed to bias the FIR filter Now, the transconductances and can be replaced by:

where are the effective gate-source voltages for the pMOS and nMOS branches. The voltages are all equal in the case of pMOS and nMOS current sources respectively. In the FIR semidigital filter, the sum of the coefficients is one. Hence, we can find a relationship between the total current ,the density of ones and zeros in the representation of the signal, the oversampling ratio, the effective gate-source voltages and the total power spectral density of the noise voltage at the output.

171

As a conclusion, in order to minimize the white noise present at the output of the converter one has to increase the oversampling ratio and to decrease the total current in the semidigital filter. Decreasing the value of the resistor R will give a negligible influence of the resistor noise at the output. On the other hand, the output stage of the opamp is rail to rail to ensure large swings of the signal. If the common mode voltage at the input of the opamp is then in order to use the full swing at the output. In the particular case p=1/2 the density of ones and zeros in the signal representation are equal. Under this assumption and by denoting:

then the power spectral density at the output becomes:

7.6.2 1/f noise considerations In the following paragraph we are considering the effects of the 1/f noise on the power spectral density of the output noise voltage. The noise transfer to the output has the same behaviour as the white noise transfer from (7.31) and (7.32). Given the power spectral density of the 1/f noise present at the gates of the pMOS and nMOS current sources of the coefficient

one can find the output noise power up to the corner frequency of the 1/f noise can be approximated as follows:

It

This noise is present at the output only during the period Ts and should be weighted with the density of ones and/or zeros. By following the same pattern as in the case of the white noise, we can find the total noise power at the output as a function of oversampling ratio, signal statistics and the FIR filter structure:

The transconductances of the PMOS and NMOS transistors depend on the coefficient and the total current needed to bias the semidigital filter as:

172

All the transistors of the current sources have the same length and respectively and different widths according to the filter coefficients. By using the property of the filter coefficients it is possible to rewrite (7.35) in the following form:

The total noise coming only from the semidigital FIR filter can be found by adding the contributions of the white noise and the 1/f noise. Besides, we have to take into account the noise of the opamp and the noise generated by the feedback resistor R.

7.6.3 Noise generated by the clock jitter Another contribution upon the total noise generated by the D/A interface would be the noise generated by the clock jitter. As long as the FIR semidigital filter is being implemented with a lot of coefficients, the area would be large and the clock distribution would be a problem. Going to high oversampling ratios OR, to be able to increase the accuracy of the converter we encounter the clock jitter and its consequences. The clock jitter can be reduced by using a crystal referenced clock. In order to consider those effects we have to take into account two possible realizations of the PDM codes, non return to zero (NRZ) and return to zero (RZ) coding.

a. NRZ coding Let’s assume an uncertainty in the sampling moments of the clock. In the case of NRZ coding, the actual values of the output depend on the previous values generating inter-symbol interference. In fig. 7.17.a, the currents flowing in the resistor R are shown. The uncertainty in the sampling moments kT will generate an uncertainty in the low-pass filtered voltage at the output of the D/A. The output voltage in the period [kT,(k+1)T] according to fig.7.17. b) and the time constant of the low-pass filter is:

From (7.38) it is obvious that NRZ coding generates inter-symbol interference because of the correlation between samples. If the period of the signal PDM represented is , the period of the top samples T, and the number of samples Q, then the average of the output voltage can be approximated as:

173

The assumption would be that the low-pass filter has a larger time constant RC compared to the period of the top samples T. In order to find the effect of jitter on the output noise, consider (7.38) for t=(k+l)T under the assumption

The consequence of jitter will be the spread of the mean value of the voltage variation considered in (7.40). The mean value of this variation in the interval is:

and its spread as a function of the clock jitter :

This value represents actually the rms noise in a bandwidth

b. RZ coding Fig.7.18 illustrates the return to zero current top pulses and the output voltage exaggeratedly small for understanding purposes. In the case of return to zero, the top current pulses will go periodically to zero and the inter-symbol interference will be reduced. This has consequences on signal dependent distortion too. However, we have to face another problem inherent to return to zero coding. Because current steps are larger now in comparison to NRZ coding, the errors made in the area of the top pulses by clock jitter are also larger, generating larger noise at the output.

174

The period of the output signal is denoted The effect of the jitter on the output voltage has to be considered in a bandwidth given by following the same pattern as in the case of noise calculation at the output. The average of the current top pulse in the period T is:

The mean of the output voltage

in the interval [kT,(k+1)T] depends on the current

Clock jitter generates the spread of the denoted which gives the spread of the output voltage denoted The relationship between and is given by:

This represents the power of the noise related to the bandwidth 1/T which has to be related now to the bandwidth The power of the noise in this bandwidth will be:

The interval in which the pulse is ON denoted is related to T as By using the oversampling ratio the duty cycle and (7.46), the power of the noise in band width is found to be:

175

The signal to noise ratio in the bandwidth consideration can be determined from:

when only the clock jitter is taken in

The area of the top pulse will be larger when increases and the noise generated by jitter will have less influence on the total S/N. As a conclusion, the larger the ON time of the pulse, the better the S/N and larger clock jitter can be tolerated. When return to zero coding is being used the inter-symbol interference will become less dominant as in the case of non return to zero coding. Breaking the correlation between the current top pulses, the signal dependent distortion will be improved. As a final example, consider 1/T=2.8MHz, OR=64 and A clock jitter of gives a S/N ratio of about 91dB corresponding to 15 bits resolution. In order to have a higher resolution than 15 bits a clock jitter of about 50ps or less will be required. This gives a design condition for the clock generation part of the interface.

176

7.7. Realization The circuit diagram is illustrated in fig.7.19. The bitstream output of the noise shaper is applied to the DATA input terminal and shifted in the registers R1...R25. The outputs of the shift registers are applied to the AND gates A return to zero signal RTZ derived from the clock CK is present at the other inputs of the AND gates and reduces the inter-symbol interference between the top flat current pulses. Therefore the signal dependent distortion is reduced. The coefficients of the filter are implemented as aspect ratios of the current sources connected transistors. The switches are realized with differential pairs driven by the outputs of the AND gates and the outputs of the inverters The output buffers of the AND gates and the inverters are chosen such that during transitions the switches are driven very fast in order to minimize the effects of the charge injection.

7.7.1 Floating current source To minimize the mismatch between the pMOS and nMOS current sources, a floating mirror MN1 and MP1 delivers the same current Io to the pMOS and nMOS branches. The bias needed for cascoding is generated in the biasing section at nodes BIAS_N and BIAS_P. The floating current source is illustrated in fig.7.20. A replica of the bias current J_BIAS is forced in the transistor MN2. The same current is flowing in the transistor MP2. The MOS translinear loop around the transistors MN2, MP2 and MN1, MP1 generates a copy of the same current in the output transistors. An increase of the input current generates an increase of the voltage at the gates of MN2 and MN3. The feedback loop MN3, MN5 adjusts the current in the transistor MN5 to be equal with the current in the input branch. MN4 ensures a constant bias

177

current in the transistor MN3. The outputs of the current source are floating and can withstand a minimum supply voltage of about 0.4V.

7.7.2 The opamp used for LPA filtering The output of the D/A interface has to drive a high efficiency power amplifier with high linearity and low noise. Besides it has to deliver 1mA in a 10k differential load. The opamp of the RC-active low-pass filter is shown in Figure 7.21. It is a two stage Miller compensated opamp with a class A differential output. The first stage is a folded cascode amplifier with a large gain. The rail to rail output stage can deliver 1mA to the differential output load. Since a differential configuration is used, a common mode control circuit is required. The common mode at the output is sensed by resistors R1 and R2 and then applied at the inverting input of the differential pair MN16 and MN17 where it is compared to the reference voltage E_COMMON. The

178

bias current of the first stage is adjusted in order to equalize the two voltages at the input of the sense amplifier. In fig.7.22, the frequency transfer of the amplifier is shown. The DC open loop gain of the amplifier is 90dB and the unity gain frequency 40MHz. The opamp is compensated with a Miller capacitor of 12pF in series with a resistor of to correct for the phase shift introduced by the zero. This yields a phase margin of 75°. The noise behavior of the opamp is dominated by the noise of the first stage at low frequencies. The dynamic range of the amplifier is 103dB for a supply voltage of 5V. The power consumption of the opamp is dominated by the output stage power and has a value of 10mW from a 5V power supply voltage. In order to increase the dynamic range of the opamp for higher resolutions D/A interfaces, a class A chopped opamp can be used. Fig.7.23 shows a class A chopped amplifier based on the opamp from fig.7.21.

179

By introducing choppers and in the signal path (dotted lines) the stability of the opamp will be impaired. The chopper matches dynamically the controlled current sources MP3 and MP4 outside the signal path. To improve stability, a larger compensation capacitor is required. The simulated frequency response of the opamp is shown in fig.7.24. The unity gain frequency is 17MHz, the phase margin has a value of 75° and the open loop gain is 90dB. For stability, a 14pF capacitor has been used in series with

7.7.3 Low-power D flip-flop for shift registers The current sources of the FIR filter are controlled by switches driven from the outputs of a delay line as explained in section 7.4. The shift registers in the delay line are low-power D flip-flops realized with a minimum number of components as illustrated in fig.7.25. A master-slave action is required in order to isolate the output from the input. The D flip-flop consists of two inverters, two transmission gates and feedback to improve the switching behavior. When CK_NEG is active, the data D is loaded at the output of the first inverter and will be transferred to the output when CK

180

is active. By using simple transistors as transmission gates, the level “1” of the data D is degraded to This slows down the low transition of the inverter. To correct this problem, a feedback path is added which restores the correct levels at the output. The main advantage of this approach is the reduction in the number of the clock lines and simplicity.

7.8. Experimental results The D/A interface has been realized in a CMOS 5V technology with two metal layers and one polysilicon layer. Fig.7.26 illustrates the chip photomicrograph. The active area of the circuit is being dominated by capacitances needed for low-pass filtering and compensation. Extreme care has been taken for matching the current sources in the lay-out. During the measurements, the RTZ signal was set to VDD. For measurement purposes, a bitstream signal has been used as a DATA input. Fig.7.27 shows the signal to noise and distortion measurement (S/N+THD) for a sine input at 1KHz. Here, the noise floor is around -115dB...-120dB and the distortion peaks are lower than -87dB. The total harmonic distortion is -86dB at 1KHz input and the even order distortion components give the largest contribution at the output.

181

The setup for the spectrum measurements had a single ended input. This explains the unexpected increase in the even order harmonics. Table 7.2 shows the performance summary of the D/A interface.

7.9. Interpolative D/A converter with Sinc approximation in the time domain The signal reconstruction can be improved by using another approach based on Sinc approximation in the time domain. In this approach a reduction of power in the digital domain by a factor two can be achieved. The price paid is an increase of the filter complexity by doubling the number of current sources and shift registers with the benefit of keeping the same power consumption in the analog part. To understand

182

the principle of the interpolative D/A converter consider first the signal reconstruction from its samples.

7.9.1 Signal reconstruction Assume y(t) to be an ideal sampled signal. This signal can be obtained by multiplying a continuous signal x(t) with a periodic train of Dirac pulses.

In conformity with sampling theorem ( WKS theorem) [15] if the signal is ideally low-pass filtered, the signal can be recovered from its samples. Denote the sample frequency and 1(t) the impulse response of an ideal low pass filter. The original function can be obtained by adding together an infinite number of Sinc pulses weighted with the sample value:

In fig.7.28 the reconstruction process is graphically shown. The dotted line is the sum of the Sinc functions. As long as we can generate the complete sequence of Sinc functions, the reconstruction process is ideal. In our case, the reconstruction process starts with a D/A converter which is followed by a sample-and-hold circuit and finally an analog filter. This means that the analog value coming from the D/A converter is hold until the next sample arrives. Therefore, the reconstruction of the signal is done by summing the top-flat pulses as a coarse approximation of the Sinc functions. A better approximation of the Sinc function is shown in fig.7.29.

183

The sampling period is halved and a new pulse is present at -T/2 with a duration of T. Theoretically, dividing further the sampling interval in equal time slots and introducing new top flat pulses, the precision of this approximation can be improved. However, the complexity required to realize the filter limits the number of top-flat pulses used for this approximation. Fig.7.30 illustrates the implementation of the Sinc approximation in time domain of fig.7.29. The number of the shift registers has been doubled and the number of the coefficients is doubled. Every coefficient is halved and repeated twice in the FIR filter. In this method, a third interpolating sample is present between two adjacent samples, equal to the arithmetic mean of the two initial samples. By doubling the number of coefficients and shift registers at the input of the analog low-pass continuous time filter, the equivalent sample frequency is doubled. Consequently, the sampling frequency of the digital filter can be reduced with a factor two without changing the sample frequency at the output of the FIR filter. The consequence is that the digital filter and the noise shaper can have a sampling frequency with a factor to lower and therefore, the power in the digital side is reduced a factor two. By halving the coefficients and repeating them twice, the complexity in the analog part increases but, the power consumption remains the same. Only the slew behavior of the opamp will limit the method. The digital part consisting of digital filters, noise shaper, clock generation circuitry can work at half of the initial clock frequency.

184

This gives a reduction in power with a factor two. If we increase the complexity of the FIR filter with another factor two, we end up with 100 coefficients, complexity comparable with standard methods like Remez exchange algorithm. The benefit will be the reduction of power with a factor 4 in the digital domain.

7.10. Conclusions This chapter dealt with system level aspects where a D/A interface with Sinc approximated semidigital reconstruction filter as an example of a system where accuracy and noise give constraints on the total power consumption. It shows that low-power techniques at the highest level of abstraction can lead to power savings which cannot be obtained unless the complete system is taken into study. The method used in this chapter is based on a new approach, the Sinc approximation approach, either in frequency domain or in time domain. A differential, current-driven 16-bit D/A interface with Sinc approximated semidigital reconstruction filter has been presented. The benefit of the differential approach is the reduction of substrate interferences and the increase in voltage swing necessary to have large dynamic range. The chapter focusses on the optimization of the number of coefficients of the FIR filter. An FIR filter with a large number of coefficients needs a large number of additional digital circuitry increasing the area, power consumption and complicating more the clock distribution. A large number of coefficients, requires more shift registers and therefore, the power in digital domain will increase. The overhead in power due to clock distribution has to be added. The accuracy of the coefficients is subject to process tolerance caused by rounding of the small coefficients and quantization to the process grid span. A large number of coefficients implies big differences between coefficients. The accuracy of the smaller coefficients is impaired with consequences on the stop-band rejection of the filter. By using Sinc approximation in the frequency domain and an iterative procedure one can reduce the number of coefficients taking into account process tolerances such that the out of band rejection of noise requirement is met. Compared to the standard solutions we have reduced about four times the number of the coefficients for the same requirements. With only 25 coefficients we get more than 50dB stopband rejection of the out of band noise. The resolution of the system is impaired by circuit nonidealities such as component noise, mismatches, device nonlinearities, substrate bounce and clock jitter. Some of those issues have been treated here and an analysis of the matching, noise and clock jitter is provided. To increase the matching in the differential FIR filter, a floating mirror has been used. The differential opamp with common-mode control can be chopped or unchopped depending on the resolution required. The D/A interface has been realized on chip in a 0.8µm CMOS, 5V technology and the measurement results have been presented.

185

Another approach is the Sinc approximation method in the time domain. By using this method the best partitioning of the system in terms of power can be found. Accordingly, power consumption in the digital domain can be reduced. The price paid is an increase of the filter complexity with the benefit of keeping the same power consumption in the analog part. The principle of the method is discussed and an example is given.

186

REFERENCES [1] M.A.T. Sanduleanu, A.J.M. van Tuijl, R.F. Wassenaar and H.Wallinga, “A 16-bit D/A interface with Sinc approximated semidigital reconstruction filter and reduced number of coefficients”, Proceedings of the European Solid-State Circuits Conference, The Hague, The Netherlands, pp.176-179, Sept. 1998. [2] M.A.T. Sanduleanu, A.J.M. van Tuijl, R.F. Wassenaar and H.Wallinga, “A 16-bit D/A interface with Sinc approximated semidigital reconstruction filter and reduced number of coefficients”, Proceedings of the 10th annual IEEE Workshop on Circuits, Systems and Signal Processing ProRISC’ 98, Mierlo, The Netherlands, Nov. 1998 [3] B. Kup, E. K. Dijkmans et al., “A bit-stream digital-to-analog converter with 18-b resolution”, IEEE J. Solid-State Circuits, vol. 26, no.12, pp.1757-1763, Dec. 1991. [4] A. Baschiroto et al., “A 16 bit Digital-to-Analog Converter for Audio Codec Applications”, Proceedings of ECCTD, vol.3, Sept. 1997, pp. 11.1-11.6. [5] Y. Matsuya, K. Uchimura, A. Iwata and T. Kaneko, “A 17-bit Oversampling D-toA conversion technology using multistage noise shaping”, IEEE J. Of Solid-State Circuits, vol.24, n0.24, pp. 969-975, Aug. 1989. [6] P.J. Naus, E.K. Dijkmans et al., “A CMOS Stereo 16-bit D/A Converter for digital audio”, IEEE J. Solid-State Circuits, vol. SC-22 , pp.390-395, June 1987 [7] H. J. Schouwenaars, D.W.J. Groeneveld et al., “An oversampled multibit CMOS D/A converter for digital audio with 15-dB dynamic range”, IEEE J. Solid-State Circuits, vol. 26, no.12, pp.1775-1780, Dec. 1991. [8] H. Qiuting and G.S. Moschytz, “ Analog FIR filters with an oversampled modulator”, IEEE Trans. Circuits and Syst.-II: Analog and digital signal processing, vol.39, no.9, pp.658-663, Sept. 1992. [9] P.J. Hurst and J.C. Brown, “Finite impulse response switched-capacitor filters for the delta-sigma modulator D/A interface”, IEEE Trans. Circuits and Syst. vol.38, no. 11, pp. 1391-1397, Nov. 1991. [10] W.M.C. Sansen, H. Qiuting and K.A.I. Halonen, “Transient analysis of aharge aransfer in SC filters-gain error and distortion, IEEE J. Solid-State Circuits, vol. SC 22, no.2, April. 1987. [11] D.K.Su and B.A. Wooley, “ A CMOS Oversampling D/A Converter with a Current-Mode Semi-digital Reconstruction Filter”, IEEE J. Of Solid-State Circuits, vol.28, n0.12, Dec. 1993, pp. 1224-1233. [12] E.F. Stikvoort, “Some subjects in digital audio, noise shaping, sample-rate conversion, dynamic range compression and testing, Ph.D dissertation, Eindhoven University of Technology, May. 1992. [13] L. R. Carley, “A noise-shaping coder topology for 15+ bit converters”, IEEE J. Of Solid-State Circuits, vol.24, n0.2, pp. 267-273, April. 1989. [14] S.M. Kershaw, S. Summerfield, M.B. Sandler and M. Anderson, “Realisation and implementation of a sigma-delta bitstream FIR filter”, IEE Proc.-Circuits Devices Syst., vol.143, no.5, pp. 267-273, Oct. 1996. [15] A.W.M van den Enden and N.A.M. Verhoeckx, “Discrete-time signal processing, Prentice Hall, 1989. [16] A. Petraglia and S. Mitra, “Effects of coefficient inaccuracy in switched-capacitor transversal filters”, IEEE Trans. Circuits Syst., vol.38,n0.9, Sept. 1991, pp. 977-983.

CHAPTER 8 Conclusions This chapter surveys the content of the book. In section 8.1 a summary of the contents is given, while section 8.2 presents the main conclusions. Original contributions of this work are discussed in section 8.3 and recommendations for further research will follow in section 8.4.

8.1. Summary The work presented in this book concerns power, noise and accuracy in mixed-signal applications. Along the material presented it is shown that power, noise and accuracy should be treated in an unitary way, the three terms being well interrelated. It is divided in a theoretical part which covers sub-micron digital and submicron analog and an applicative part where accuracy related power and noise related power is encountered. The main part of the book deals with analog circuits working in a digital environment where the process has been optimized for digital applications. To get the best performance, knowing the limits of power in digital and clearly defining the environment where analog should work is a must. Starting from fundamental/physical limits we are discussing afterwards the practical limits of power in digital, mostly at the architecture level. The fundamental limits are asymptotic limits and they cannot provide realistic comparisons between possible solutions. At architecture level, it is possible to find relations between power and signal to noise which provide a comparison basis with analog solutions. A simple example of a digital filter shows how power can be saved at the architecture level. The possible ways to low-power in digital are being discussed which provide some input for the analog part of this thesis. The general trend, in digital, to scale down the power supply makes the process of designing analog circuits a difficult task since most of the solutions valid for large supply voltages are not anymore useful due to the low voltage limitations. In all cases this yields an increase in power consumption. Besides, analog designers have to cope with second order effects generated by the incompatibility of the process with analog performance. Starting from general considerations and simple circuits, we have

188

proven that DR*Speed product is limited by power, topology and supply voltage regardless of the type of circuits: continuous time or sampled data, current-mode or voltage mode. Matching imposes also restrictions on the obtainable accuracy and that is why, accuracy related power consumption has been discussed. The theoretical background from Chapter 2 and Chapter 3 has be used in the applications part. Several examples have been chosen where accuracy driven power and noise driven power applies. At low supply voltage, the key problem of analog signal processing functions is dynamic range reduction. For this reason, a key target is to keep the largest possible voltage swing. The first example is an OTA-C integrator with a high DR/P ratio. This is possible by keeping large swing for all tuning conditions. The second example is a current Gm-C integrator with high quality factor for low voltages. The power efficiency of the two designs has been discussed according to the theoretical background from Chapter 3. The two integrators presented above are used to realize the video filter from Chapter2 in an analog way and to make a comparison in power to the digital approach. The next example is a polyphase filter. Here selectivity is ensured by using polyphase signals instead of high-Q bandpass filters. Matching driven power consumption comes as a variable. By using the current Gm-C integrator, we have shown how to make a low power polyphase filter needed for image rejection in a mobile transceiver. The next chapter considers the 1/f noise and offset in mixed-signal design where chopping can provide a solution to boost the dynamic range and accuracy. A method to use chopper modulation at high frequencies is introduced and a lowvoltage, low-power, chopped transconductance amplifier for mixed analogue digital applications has been presented. This OTA is meant for high-end audio applications. Chopping and dynamic element matching allow low noise and low residual offsets up to 1MHz. We show next that by using chopping techniques and a chopped OTA, the accuracy of a bandgap voltage reference can be improved about ten times without laser trimming and with the benefit of reducing the 1/f noise of the reference. The same chopped OTA for high-end audio applications has a power consumption of 600µW while in the bandgap example the power consumption is 7.5 µW. This example explains why the term “low power” has to be related to the specific application and its own specs. The next chapter focuses on the design and the realization of low voltage chopped amplifiers with rail to rail class AB output stages capable of chopping up to 10MHZ, with low noise, high linearity and low residual offset. This amplifiers can be used for high-end audio applications in driving low-ohmic loads for portable applications. Low-power techniques at the highest level of abstraction as architectural level and algorithmic level can lead to power savings which cannot be obtained unless the complete system is taken into study. Chapter 7 presents a 16-bit D/A interface with Sinc approximation in the timedomain or frequency domain reconstruction filter as an example of a system where accuracy and noise give constraints on the power consumption of the system. Here, reducing power in the analog domain the power in the digital domain is also reduced while the best partitioning of the system in terms of power can be found. Compared to

189

the standard solutions we have reduced about four times the number of coefficients of the FIR filter for the same requirements. With only 25 coefficients we get more than 50dB stopband rejection of out of band noise. A differential solution was proposed to reduce the digital crosstalk and to increase the output signal swing. An analysis of the matching, noise and clock jitter has been attached.

8.2. Conclusions The fundamental limits for low-power in digital are asymptotic limits and cannot be used in power estimations. Power consumption of digital signal processors is a logarithmic function of signal to noise and depends on technology and the architecture. With better and better energies per transition they will compete in the future with analog processors even for low signal to noise ratios. Power analysis at highest level of abstractions can provide solutions for low power. The trend in digital is towards smaller and smaller feature sizes and smaller power supply voltages. This impacts in a negative way analog designs in terms of dynamic range, power, tunability and gain. Only accuracy will benefit from downscaled processes up to a certain point. The fundamental limits for low-power in analog are asymptotic limits. They are combining in one simple equation power, S/N ratios and speed. There are no restrictions regarding voltage swings, circuit topology, noise generated by active circuits, the process constants and linearity. That is why relative comparisons between different designs are difficult to be made based only on the fundamental limits. A designer wants a certain dynamic range and speed with a given accuracy, gain and linearity. Low voltage and low power are imposed by the application and the mixed level context. Starting from general considerations and simple circuits, it is possible to prove that DR*Speed product is limited by power, topology and supply voltage regardless if the circuits are continuous time or sampled data, current-mode or voltage mode. This concept can be generalized for a large class of analog circuits like amplifiers and filters. Scaling down and keeping the same DR GBW product, power has to increase faster in voltage-mode circuits to compensate for power supply down scaling. The accuracy requirements give extra boundaries on the minimal power consumption for a given speed, gain and accuracy. This limitation is stronger than the physical limitation imposed by the effect of the thermal noise given the levels of the noise and the levels of the offsets. That is why, in some applications, matching driven power consumption has to be considered. In CMOS transconductors, large tunability needed to correct for temperature and process variations gives a significant reduction in voltage swings at low supply voltages and consequently dynamic range reduction. The new technologies optimized for digital applications are impaired by second order effects like velocity saturation and mobility reduction. Most of the concepts used in the past cannot be used anymore. New transconductor concepts which do not rely upon the

190

ideal square law of a MOST, are needed. Another issue is achieving large tunability without conflicting with the large swing requirement. The transconductor from Chapter 4 features a constant input window for all tuning conditions which allows large swings for all tuning situations. This structure overcomes the problems related to non-idealities of the modern MOS transistor in terms of tunability range. The transconductance can be digitally tuned, in ten coarse steps, and continuously, between coarse steps, in the range If required, the quality factor can be adjusted such that Gm tuning and Q tuning are independent. Total harmonic distortion stays below -50dB for input amplitudes of 1.8 Vpp in all tuning conditions and well below -60dB for amplitudes lower than 1Vpp. Large swing property yields a large dynamic range over power ratio. In worst case the noise excess factor is close to 6 and power dissipation is 1.48mW from 3.3V supply. The transconductor can be used as a Gm-C integrator for filter applications. Positive feedback is a promising technique for enhancing gain in sub-micron CMOS because current matching in modern technologies improves. It avoids cascoding for having large gains and can be used for low-voltage applications. The second type of integrator considered in this chapter is a current Gm-C integrator with local positive feedback for enhancing the gain. The reason for using this integrator consists in the low-voltage, high linearity and very high frequency of operation with a high power efficiency. It is compatible with standard digital technology has a high quality factor Q and can work down to 1.5V power supply voltage. By using the DR*Speed concept from Chapter 3 it is shown that the current Gm-C approach has better power figures for the same working conditions than OTA-C approach. The two integrators from Chapter 4 are used to realize the video filter from Chapter2 in an analog way and to make a comparison in power to the digital approach. It turns out that digital approach has less power consumption per pole than the analog counterparts for a CMOS process. This explains why, in the future, digital filters will be used even for low DR applications. There are filter applications where matching requirements and noise requirements have the same importance, with constraints on power consumption and linearity. Channel selectivity in receivers has been realized until recently using SAW filters. Those components are external components and therefore integration on chip of selectivity has become a major concern in receivers. From Chapter 3 we already know that selectivity increases the noise power and requires extra power consumption to achieve it. In a polyphase filter, selectivity is ensured by using polyphase signals without the need of bandpass sections. They can discriminate between positive and negative frequencies and therefore, using this property, selectivity can be achieved. By using a low power integrator, we have shown how to realize a polyphase filter needed for image rejection in a mobile transceiver. The filter has a central frequency of 1 MHz, a gaussian to -6dB transfer and a passband from 500KHz up to 1.5MHz. The filter has been simulated in a CMOS technology with a supply voltage of 2.5V. The image rejection can be

191

made better than -52dB with a power consumption of 15mW with a dynamic range of 69dB. When compared to active-RC realizations with opamps it shows power figures better with a factor six. The gaussian transfer allows good time response as required in data transmission. Chopping is the only method which reduces 1/f noise and offset without modifying the baseband white noise. As a modulation method, it boosts the dynamic range and accuracy of analog circuits without power penalty. Although, chopping is a low frequency technique, there are applications where bandwidths of the signals are in the MHz range. We have introduced a new method to use chopper modulation at high frequencies and a low-voltage, low-power, chopped transconductance amplifier for mixed analogue digital applications was presented. This OTA is meant for high-end applications. Chopping and dynamic element matching allow low noise and low residual offsets up to 1MHz. The sensitivity to substrate noise is tackled in the design. Experimental results show residual offsets of less than up to 1MHz chopping frequency. Second order effects like charge injection and residual offsets are discussed. By chopping, the S/N is improved with about 6dB which brings a factor 4 reduction in power. In mixed level applications accurate voltage references are difficult to realize due to the lack of well characterized lateral pnp’s and the large offsets inherent to CMOS opamps. Another problem tackled is related to the realization of an accurate bandgap voltage reference in CMOS. It is shown that by using chopping techniques and a chopped OTA, the accuracy of a bandgap voltage reference can be improved about ten times without laser trimming and with the benefit of reducing the 1/f noise of the amplifier. The bandgap referenced voltage has a spread of 3.2mV after chopping and power consumption. The chopped amplifiers presented further are primarily meant as amplifiers capable of driving headphones in portable digital audio. The generality of the method makes them suited for a large class of designs. In audio applications, extra offsets give extra dissipation in the headphone. It is also desired to have high linearity and low noise for all possible loads. That is why chopping can be used to improve the accuracy and the dynamic range. The first amplifier has been realized in a CMOS. Measurements show a dynamic range of 111dB for the amplifier configured as a follower when chopping at 1MHz. For high ohmic loads, the linearity is better than -91dB for 1.5V voltage swing. For low ohmic loads, the THD is better than -83dB. The power consumption is 1.8mW from a 3.3V power supply. The class AB control circuit of the output stage is limiting the lowest value of the supply voltage at about 1.8V. The second amplifier designed in CMOS technology has a new class AB output stage which can work at lower supply voltages. The open loop gain of this amplifier has been increased to 92dB by using gain boosting techniques. Offset simulations show a static offset of 1.67mV. Chopping at 10MHz, the simulated residual offset is but at 1KHz chopping, the simulated residual offset is The linearity of the opamp is better than -85dB for signal amplitudes close to The power consumption of the opamp is 1.5mW from a 3.3V power

192

supply voltage being dominated by the power consumption of the class AB output stage. It can work down to 1.4V with reduced swing and dynamic range. The last example is a D/A interface with Sinc approximated semidigital reconstruction filter. It shows that low-power techniques at the highest level of abstraction can lead to power savings which cannot be obtained unless the complete system is taken into study. By using Sinc approximation in the frequency domain and an iterative procedure one can reduce the number of coefficients taking into account process tolerances such that the out of band rejection of noise requirement is met. Compared to the standard solutions we have reduced about four times the number of the coefficients for the same requirements. With only 25 coefficients we get more than 50dB stopband rejection of the out of band noise. The resolution of the system is impaired by circuit nonidealities such as component noise, mismatches, device nonlinearities, substrate bounce and clock jitter. To increase the matching in the differential FIR filter, a floating mirror has been used. The differential opamp with common-mode control can be chopped or unchopped depending on the resolution required. The D/A interface has been realized on chip in a CMOS, 5V technology. Measurements shows a THD of -86dB and a noise floor at the output close to -120dB. The Sinc approximation in the time domain provides a solution to decrease power in the digital part of the D/A interface without increasing power consumption in analog. By using this method the best partitioning of the system in terms of power can be found. Accordingly, power consumption in the digital domain can be reduced. By using a combination of the two methods namely Sinc approximation in time domain or Sinc approximation in digital domain, it is shown that keeping the same complexity of the FIR filter as in standard approach, a reduction in power in the digital section, with a factor four is possible.

8.3. Original Contributions The following original contributions can be found in this book and related publications: The S/N and power analysis in fixed point digital filters presented in Chapter 2 and APPENDIX 1 with the architectural approach of power. The DR*Speed concept and its use in finding minimum power consumption in analog circuits continuous time or sampled data. The analysis of analog filters is also an example where the same concept can be used in the analysis of an analog system. The same concept has been used further in the book in some other applications. It was also used to see the effects of power supply voltage downscaling in modern processes ant its impact on voltage or current processing circuits. The transconductor presented in Chapter 4 is a new concept capable to cope with second order effects in modern MOS transistors. The large swing property and the

193

constant window, independent of tuning, are also used in making a design for mixed level applications. The linearity improvement of the current Gm-C integrator and the use of resistor degeneration to improve matching. The gaussian polyphase filter based on current Gm-C integrator is a new concept which shows an improvement with a factor 6 in power when compared to opamp based designs. At the same time is the first material showing how a gaussian filter can be used to achieve selectivity in receivers. The chopper principle from Chapter 3 destinated for high frequency chopping up to 1MHz. This chopped transconductance amplifier can be used for low frequency applications as well as high frequency applications. The principle of accuracy improvement of a bandgap reference voltage circuit by using chopped amplifiers without the need of external filter. The chopped amplifers with class AB output stages where chopping the OTA and a part of the bias current shared in common by the OTA and the class AB output stage will improve the accuracy of the complete amplifier. The class AB stage of the chopped amplifier in 0.5µm CMOS is also a new circuit. The Sinc approximation method in time or frequency domain and its use in D/A converters. The differential approach and the floating mirror used to improve accuracy combined with the reduction of the number of coefficients in the filtering part are also new items. The noise and jitter analysis for the performance of the D/A interface.

8.4. Recommendations for further research Application of the theory illustrated in Chapter 2 for power comparisons and analysis of power in A/D converters. Most of the effort should be done in the comparator sizing according to accuracy requirements for every bit. This is crucial in the next generation A/D for high frequency applications like RF fully digitized radio receivers. A thorough investigation of power in oscillators, low-noise amplifiers where noise optimization is important for improving phase noise and noise factors respectively. The use of chopper technique to improve matching in polyphase filters reducing further the power consumption and the realization of a polyphase filter capable of working below 1V (one penlite requires 0.9V when discharged). The application of the chopper technique in low offset integrators used for battery management in monitoring the battery current. The combination of the two Sinc approximation techniques in a single design for power reduction in the digital domain and the investigation of the possibility to

194

use CDS format in having powers of two as coefficients. This will improve tremendously the matching in the current sources. The implementation of a D/A converter with a class A chopped amplifier for increasing the dynamic range for high resolution applications (>20 bit).

APPENDIX 1 S/N and power in fixed point digital filters The power of the signal at the output computed by knowing the transfer function

for every possible architecture can be and the input signal power

S/N and power for FIR DSP Given the need for rounding after multiplication, the equivalent structure with quantization noise sources is presented in fig.A1.1. Assume that the noise sources e[n] are mutually uncorelated and uncorelated with the signal. Another assumption would be that the input signal is random. The noise power at the output, for the m coefficient structure from fig.A1 is Now the signal to noise ratio S/N can be found:

A FIR filter has m-fold pole in origin. Denote the integral term from (A 1.2) as The integral term can be computed from the theorem of Cauchy by taking into account the residues in z=0:

196

A typical value for the overflow factor k is 0.25. From (A1.2) and (A1.3) one can be able to find a relation between the number of bits B and the S/N.

Considering only the computation power and neglecting the overhead from memory and I/O, the power needed for FIR DSP unit can be found by replacing the number of bits B from (A1.4) in the computational power:

S/N and power for IIR DSP For an IIR DSP unit, the noise power at the output is found by adding the noise sources after every multiplier. The IIR2 is more efficient from power point of view. That is why consider only the case of fig.2.7. If represents the denominator in the filter transfer function, the noise power at the output will be:

In the case of IIR filters the difficulty comes from the integral term which cannot be evaluated easily without knowing the structure of the filter. From (A1.2) and (A1.6) we get:

By following the same pattern as in the case of the FIR filters we are able to calculate the computational power as a function of S/N:

Given the structure of the multiplier the structure of the filter and the desired S/N one can be able to find the computational power. Sometimes it is more important to make relative comparisons between FIR and IIR DSP instead of computing absolute values. The comparison between the IIR and FIR structures can be

197

done under equal S/N condition. Though, the structure of the filters is different, they have the same transfer function. From (A1.2) and (A1.7) we find:

In (A1 .9) rounds the result to the closest largest integer. For accurate comparisons, a correction factor should be added in order to take into account the difference between the approximation of the transfer in FIR and IIR situations.

This page intentionally left blank

APPENDIX 2

The synthesis of the video filter The filter specifications represent the input of the synthesis procedure. First we have to compute the transfer function of the filter and after that to realise this transfer as a LC-ladder. The synthesis procedure is based on Darlington synthesis procedure for partial and total removal of the poles from and simultaneous realisation of the zeros for z21 and the poles for z11 and z21 from the [Z] matrix of the filter. The specifications are given in the table below.

The ripple of the filter is found from the value of

Hence we can compute the order of the filter as:

200

Therefore the chosen order is n=3. The zeros of the transmission can be determined from the order of the transmission:

The roots of the numerator in the transfer are the zeros of the transmission. Now we can compute the numerator of the transfer from (A2.3).

The poles of the transfer

are given by reciprocals of

where:

Finally, the normalized transfer of the filter is:

After frequency scaling to get the passband edge, the new transfer becomes:

For H(s) we have to find the LC-ladder with coefficient at the input is found from:

termination. The reflection

The poles of are the poles of H(s) and the zeros can be chosen arbitrary with extra condition that zeros are complex conjugates. The input impedance in the LC ladder when termination is is a function of

201

We can define four functions related to the even and odd parts of numerator and denominator:

Accordingly we have now the elements of the Z matrix associated to the ladder:

The Darlington synthesis procedure is based on the total and partial removal of the poles from and simultaneous realisation of the zeros for z21 and the poles for z11 and z21. Fig.A2.1 shows the final result of the synthesis.

This page intentionally left blank

APPENDIX 3 Filters with gaussian magnitude approximation In pulse communication systems there is a demand for filters whose impulse responses have the following properties: No ringing and overshoot; Symmetry about the time for which the response is a maximum. A filter that satisfies the above conditions is called a Gaussian filter. The three most common filter types with widely available design tables and curves which approach the ideal Gaussian filter are: 1. The gaussian magnitude filter; 2. The maximally flat group delay filter; 3. The equiriple group-delay filters. Although, the delay performance of a gaussian filter is worse than the Bessel approximation, a gaussian filter has a better step response. By definition, a gaussian function has the form:

where T is the mean value and the standard deviation. If the impulse response of a filter is of this form, then the filter will be said to be gaussian. This impulse response has no overshoot. If we denote , then the ideal gaussian magnitude shape derived from the Fourier transform of g(t) can be written as:

The frequency

is a normalizing frequency and it can be related to the -3dB point as:

The magnitude of the gaussian transfer and the group-delay response are shown below.

204

When the value of the magnitude is e=2.71828 and the relative attenuation is 1Np or 8.68dB. It can be shown that a gaussian magnitude shape is unrealizable but approximations of this transfer can be obtained by using the following series expansion:

An nth-order approximation consists of the first 2n powers in the series. The attenuation of the gaussian function approximated up to n=6 is shown in fig. A.3.2.

The approximation of the Gaussian function with a finite number of network elements can be made better by increasing the number of network elements. However, it is possible to approximate the gaussian function up to a certain level. Gaussian-to-6dB and gaussian-to-12 dB approximations will approximate the transfer up to -6dB point and -12dB point respectively. To show the difference between those approximations,

205

the frequency transfer of a 5th order gaussian, gaussian-to-6dB and gaussian-to-12dB transfer is depicted in fig. A.3.3. With these gaussian approximations it is possible to achieve a higher stopband attenuation with the same number of network elements at the expenses of a small decrease of performance in the time domain response and group delay.

The corresponding group-delay and step response of the approximations shown above are illustrated in fig.A.3.4. This explains the degradation of the group delay and correspondingly, the degradation of the step response when approximating the gaussian transfer.

About authors

Mihai A.T. Sanduleanu received his MSc Diploma from the Faculty of Electronics and Telecommunications, Iasi, Romania, in the field of Radioelectronics and Analog IC Design. In 1991 he joined the Faculty of Electronics and Telecommunications from Iasi, Romania working in analog IC design and CAD. Between January 1993 and May 1994 he accomplished a Master of Electronic Engineering program at Eindhoven University of Technology, with a fellowship from Philips Eindhoven. Between October 1994 and October 1998 he was engaged in analog CMOS circuit research as a PhD student at the MESA Research Institute and University of Twente, Enschede, The Netherlands. The PhD dissertation was entitled “Power, noise and accuracy aspects in CMOS mixed-signal design”. In november 1998 he joined Philips Semiconductors Nijmegen, The Netherlands, working in the field of Fiber Optic Communication Interface IC’s as Senior RF designer. Since April 2000 he is Senior Research Scientist with Philips Research Eindhoven, The Netherlands, working in the Integrated Transceivers group. The topics of his actual research includes Data and Clock Recovery Circuits, Crossbar Switches, Transimpedance Amplifiers, PLL’s and Laser Drivers. He has published 15 papers and holds 18 patents in RF and broadband IC Design.

Ed A.J.M. van Tuijl has more than 20 years experience in the design of Analog and Mixed Signal IC circuits for many different application. In 1992 he joined the University of Twente as a part-time professor in Analog Electronics. After many years at Philips Semiconductors he joined Philips Research Eindhoven, the Netherlands in 1998 as a Principal Research Scientist. He is (co-)author of many papers and holds many patents in the field of Analog Electronics and Data Conversion. His present interests involve hardware design and sound quality of the Super Audio CD standard and Analog Front End design and Data Conversion for Wired Data Communication.

INDEX A/D converter 2,18,56,107,120 absolute abstraction level 9, 152 AC response 73 accuracy 3,4,6,31,32,40,44,5658,66,71,100,114,119-122,128,153-155,166 accuracy driven power 59,114 Accuracy*Speed 57 acoustic efficiency 129 active load 72 activity factor 13,17 adders 13,15,18,20,23,27 addition 18 algorithm 3,9,10,13,15 algorithmic level 24,28,153 amplifiers 2,36,54,55,88‚102 analog circuits 32,35,36,38,40,100 CMOS 4,31 error 121 filter 25,69,83,84,98,168,182,199 functionality 2,23,31,32,66 peripheral 24 post-filter 159 processor 36,56,69 prototype 84 reconstruction 153 systems 4 temperature 10,11 AND gate 176 antenna 88 architecture level 3,6,9,10,12,18,23,24,28,153 area 18,19,116,119,122,160,167 arithmetic complexity 13 mean 61 array 14 aspect ratios 46,72,91,96,133 asymptotic limits 3,10,31,32,38 autozero technique 102,104 amplifiers 103,120 autocorelation function Rxx 105 available noise power 10 average energy 24 signal power 10

bandgap voltage reference 6,102,119‚121-123 bandpass filter 64,87,90,98,110 bandwidth BW 41 Bartlett 164 baseband 88 baseband noise 51‚108 baseband spectrum 109 batteries 1 BER 10 BiCMOS 2 bilinear transformation 52 bipolar 62,69,119 biquad 60-62,64 bit per word B 15 bitstream D/A Converter 128,154,176 body effect 144 body factor 34 Boltzmann’s constant 10 broadband random process 106 building blocks 19 buss 24 Butterworth filter 25, 117,118,123,127,131 118,123,127,142,148 camcorder 2 capacitance 17,23,48 capacitance scaling 40 carry 19-22,27 look-ahead adders (CLA) 19 select adders (CSA) 19 sign-digit format 26-28 cascade adders 21,22 approach 60,61 RCA 21 cascoded mirror 11,134,167 Cauchy theorem 196 cells 15 chain adders 22 channel charge 38 length modulation 33,73 selectivity 5,87,98 spacing 89 thermal noise 38 charge amplifier 50

208

carriers 39 coupled devices 104 injection 6,53,58‚103 111,114, pumps 110 summing amplifier 49 chopped amplifier 6‚108,110,116,122, transconductance amplifier 6,109,114 chopper modulation 6,101‚105,106109,116,123,129,131,134 stabilized 6,128,129 chopping 5-7,101,106,107,114,116, circuit level 23 limits 11 class A 177 A filter 65,80 AB 127-130, 143 AB control 132,133,142,144 AB currents 144 clock cycle 13,14,18,22,54 distribution 24 feedthrough 114 frequency 13‚14 jitter 6,172,174 rate 1 CML 13 CMOS 1,2,4,6,9,12,13,24,25,27,32, 32,38,69,97,119,142,147 coarse interval 72 step 69 tuning 71,73,75 coding 23 coefficients 6‚160-163 coil 90complex plane 92 common-mode amplifier 73 control 49,72 feedback 72,78,159,177 noise 63 comparator 102 complex network elements 90 notation 88 signals 87,92,93 compression point –3dB 61 computational power 3,4,10,15,16,17,18,27,28,196,197 conditional sum adders (CSA) 19 conductance 32 continuous time circuits 53,54

filters 60,78,129,155 conventional choppers 110 conversion linearity 73 resistor 70,75 correlated double sampling 104‚105 cross-over distortion 140,149 crosstalk 92,159 current amplifier 46,47,48,54,57 division 73 drive 23 efficiency 45,52,55,65,81 gain factor 3 Gm-C integrator 78,85,86,91,98 matching 40 mode 4,48,56-58,81 noise 53 processing 40,46,47 scaling 40 triangle method 73 cutoff frequency 35,108 47,61,66,114,119,138 D/A 2,6,56,107,137,155‚168 interface 153,159, 168,177,180 Darlington synthesis 201 data converters 31 rates 6 transmission 10 DC-DC up converter 83 DCS 1800 89 DECT 5,89 deep submicron 35,37 degeneration resistor 63,70 delay 24,25,158,179 balanced 14 elements 16,53 design methodology 3 trajectory 2 device 9 differential gain 79 pair 70 differentiator 104 diffusion capacitance 32-35 digital algorithms 13 audio 115,128 camera 2 filter 4,15,83,87,154,164 function 12 noise shaper 128 processor 37 signal processing 2,18,88 video 2

209

video filter 25 Dirac pulse 105 direct form 2 16 discrete amplitude 13 time filter 160 distortion 81,116,140 dividers 19 DR*GBW 5,45,113 DR*Speed 4,32 drain diffusion 25 droop 160 DSP 2,13,15,17,19,195-197 DVD players 2 dynamic element matching 100,111,113,131-133 power 23 range 3-6,31,35,36, 39,40,42,44, 47,48,56,60,62, 64,65,69,76,80,87,96,98,100 ,109,114,123,141,178 ECL 13 effective noise bandwidth 80 effective voltage 64 eigen values 60 electromagnetics 10 electron 10 energy 10,15,20,21 energy change 11 energy consumption 13 energy density 1 energy per transition ETR 1315,18,20,24,27 equiripple design 160 even distortion 83 experimental results 114 exponent 26 extrapolated bandgap voltage 120 feedback 41,43,45,54 feedback factor 51 feedback loop 71,130,143 Fermi level 144 field strength 32 figure of merit 42,58,76 filter coefficients 16 filter synthesis 89 filters 2,4,5,7,27,31,36,60,61,88,93 fine-step 69 FIR filter 6,15,18,25,27,129,130,153155,158,160,162,164,168,170,179, fixed point digital filter 195 fixed point representation 3‚18 nicker noise 5‚39,102,108 flip-flop D 179 floating curent source 177 folded back noise 53 foldover 104‚106 forward saturation 38

Fourier transform 105,118,160 frequency crosstalk 92-95 frequency dependent negative element 90 frequency sampling method 160 frequency scaling 200 frequency transfer 47,75,79,135 full adder 19-22,27 motion digital video 2 fundamental interval 156,168 limits 4‚1012,28,40,56,83,98 physical limits 3,10,36-38 GaAs 3 gain 4146,54,58 gain boosting 145 gain factor 48 gain stage 130 gain-bandwidth GBW 42,44,45,52,73,74,79,114,116,119,13 5,147 gate capacitace 32,33 drain overlap capacitance 79 drive voltage 47,48 oxide 34 oxide breakdown32 gaussian approximation 89,203-205 distribution 165 polyphase filter 4,69,87,89 to –12dB 205 to –6dB 89,205 transfer 89,203 geometric mean 62 Gibbs phenomenon 164 glitch 22,23,159 Gm coarse tuning 72 fine tuning 72 tuning 74 Gm-C integrators 4,5,70,69,85,97 GPS navigator 2 graphic accelerators 19 green chips 1 grid span 165 group-delay 25,84,89,90,204,205 GSM 89 gyrator filters 60 Hamming 164 Hanning 164 hardware 24 hardwiring 26 harmonic distortion 45,70,73 headphones 6,109,127,129 hearing aids 2

210

Heisenberg 11 heuristic 2 high linearity 3,69,78 end 60‚127 end audio 101,109 Q filters 79,80 Q integrators 80 hold function 103,129,130 I/O operations 15 IIR filter 16-18,196 IIR2 18,196 image rejection 5,89,94,95 in-band noise 76‚129 input swing 71 window 69 /output ports 15 integrated circuits 32 integrator 53,54,60,61,74,78,93 interconnect 35 capacitance 17,23,34 intermodulation products 155 internal states 16 interpolation 155 interpolative D/A converter 181,183 intersymbol interference 172 intrinsic gain 32 inverse-Chebyshev filter 25,84 inversion layer 38 inverter 24,25 inverting amplifier 41 jitter 39,154,168,173,174 Kaiser window 164 large swing transconductor 69,70 laser trimming 119 LC ladder 199,200 leapfrog simulation of ladders 60, length scaling 40 linear integrator 82 phase 160 linearity 4,31,38,62,63,66,74, 81,115,128,135,140,141,149 LNA 88 load capacitance 34 local oscillator 92 loci 11 logarithmic 14 logic circuit 9 depth 22,23 optimization 23 loop gain 41,71,73,103,141 lossy capacitor 79 inductor 79 Low IF DECT receiver 89

downconversion 89 topology 87-89 low noise 6‚127,132,142,168 low-pass 49‚168 filter 250,64,128,129 prototype 26,64,84,90 -bandpass transformation 90 low-power 2,4,6,9‚23,28,31,32,38 66,69,83,87,100‚109,119 methodology 3 supply voltages 42 low-throughput 2 low-voltage 4,6,31,66,68,69, 76,78,97,100,109‚127 luminance video filter 83,84 magnitude 27 management, 36 master-slave 179 matching 4,7,23,32,33,40, 87,94,97,121,166,168 material limits 11 Matlab 161,168 memories 24 memory access power 17 capacitor 54 cell 54 elements 13,15-17 methodology 9 microprocessors 19,28 Miller compensation 111,147, 177,178 MIPS/Watt 1,2 mismatch 34,41,56,92,114,138,165 167,176 amplitude 92‚93 gain 92 57 mixed analog digital 6 signal 3 mixer 88 mobile transceiver 4,5‚69,87 mobility reduction 3,4,81 temperature exponent 120 modulation index 48,54,57,80,81 signal 105 techniques 100,105 modulator 119,134 modulators 155,156,158 Monte-Carlo simulation 93,166-168 MOS 38 Mosfet-C filter 83 MOST 4,38,69 multi chip module (MCM) 36 multimedia 2

211 multi-parameter sensitivity 166 multiple threshold device 23 multiplication 18,22,26 multiplier 13-16,19,89,197 multivariable 13 non-portable 1 narrow channel effects 35 band 80 band process 106 negative feedback 73 frequency 87,88 neuron 12 NMOS 13 NMOST 39,55,80 noise 1/f 5,6,32,39,101,103,106108,110-113,119,123,137,145,147 noise 3,31,38,40,46,50,56,66,74,75, 96,101,104,113,123,129,147 ,154 attenuation 168 bandwidth 10,47,55,65,169 currents 40 density 156 driven power 59,83 excess factor NEF 44,61,75, figure 89 floor 137 measurement setup 137 model 155,156 modulation 106 power 37,42,50,97,171,195 power spectral density 38,40, sampling 103 shaper 154,155,157161,168,176 source 18 spectrum 104 transfer 157,158,163, 168,169 non-recursive 17 non-return to zero (NRZ) 172,173 normalized low-pass filter 64 power spectral density 107 transfer 200 Norton transform 84 number of bits B 13,14 of states 15,16 odd harmonics 134 off-chip memory 24 offset 5,6,40,56,57,88,101,102,104,108,112114,121,122,127-130, 133,138,141,145 cancellation 102 current 57 static 139

one chip solution 3,10 opamp 177 open loop gain 74,122,135,141,147,178,179 operation per cycle 14 oscillators 36,39‚140 OTA 6,44,45,49,51,52,81,93,101, 114,116,118,119,131,134 OTA-C 4,86,87 outline 3 output conductance 32 resistance 33,46,73‚118 stage 132 swing 73 overflow 18,196 overhead 20,60 oversampling 107,129,155,169 overshoot 89,90 oxide thickness 35,32,37,38,40,42, 45,46,48,76,80 pacemaker 2 Palm Top Computers 2 parallel multipliers 18 parallelism 23 parasitic capacitances 12 passband 25,165 edge 200 ripple 96 PCS 2 PDA 2 peaking 74 phase errors 93 locked loops 24 margin 45,113,135,141,147,178 noise 39 shift 73 physical constants 45,58 limits 11,28 ping-pong stage 128 pipelining 23 Pleak 13 PMOS 13,41,111 PMOST 39,46,48,54,80,130 Poisson distribution 10 summation rule 106,118 polyphase bandpass 90 filter 5,87-92,96,98 integrator 94,95 signal 92 transfer 93,94 polysilicon resistor 82,96,122 portable digital audio 6,109,127,128 electronics 1 phones 2 positive

212

feedback 5,32,78,81,97,98 frequency 87,88 power 3,4,6,9,11,13-16,19,23,31, analysis 9 consumption 56,57,87,93 dissipation 3,4,27,38,39,59,114 efficiency 46,54,76,78 estimation 1,61,64,86,113 limit 14 management 23,32 per pole 14,27,87 reduction 12 spectral density 39,44,47,75,80,105107,123,169 trade-off 52 delay product 24 down 2 supply voltage 23,43,47,56,78,94 up 2 practical limits 12,32,38,40,66 probability of error 10,12 process 9,13,14 constants 4,38 grid span 6,153 spreads 32,71,120 technology 23 tolerance 6,153,154 tuning 32 processing elements PE 15 Pshort-circuit 13 Pstatic 13 Pswitching 13-15 Q tuning 73,97 quadrature signal 87,88,90,93 quadrature state variables 91 quality factor Q 61,62,65,70,73,7880,84,93,94,96,97 quantization coefficients 165 errors 14,18,165 noise 3,18,28,129, 155,157,168,195 noise power 155 grid span 167 quantizer, one bit 156 quiescent current 133,135,141 quantum limit 11 mechanics 10,11 radio modems 2 rail to rail stage 127,128,132,135,142,171,177 random errors 56‚165 numbers 168 process, narrow band 107 Rayleigh distribution 165 reactances 79 real format 26 receiver 87,89 reconstruction filter 6, 129,153,154

recursive part 17 registers 23 rejection, out of band 163 relative accuracy 57 Remez exchange algorithm 160 residual offset 101,103‚112,114, 117,118,127,138,139 resistor scaling 40 return to zero (RZ) 172-174 RF signal 92 RF-CMOS 39 ripple 199 carry adders (RCA) 19,20,22 RMS 57,123,173 roadmap 14,32,66 ROM 32,36 rounding 6,165,166 rule of thumb 13 S/N ratio 4,5‚10,13-15,18,28,31,37,83,88, 98,116,175,181,194,196 sample and hold 49,51,103,104,110,182 frequency 51,60,129,159 data 3,49,52,53,58,60,120 sampling 6,27‚102,104 frequency 26 period 53 saturation 39,54 voltages 42,62 SAW 5 scaled down process 4 scaling 26,32 factor 40,93 W 39,40,48,76,86 scope 3 second order effects 31,48,71,117 selectivity 5,87,89 semidigital 6 filter 153,158,160,171,172 settling 51,60 time 51,52,55 time constant 52,53 SFG 85,90,91 shift and add 26 shift registers 6,17,129,159,160,176 short channel effects 34 SIA roadmap 32,37 side-bands 39 sign bit 18 inversion 26 signal frequency 14 path 22 reconstruction 182 swing 36‚112 Silicon Industry Association (SIA) 32 sin(x)/x 110,129,161,164,181 SINAD 115,116,139

213

Sinc approximation 6,7,153,154,161,162 interface 39 slew-rate 141 slope factor 38 smart cards 2 source difussion 25 spectral density 148 spectrum 104,129,137,138 speed 4‚18,20,24,31,32,35,40,56,58 Speed*Accuracy 4 spikes 117,118,127 spread 57‚121,122 spurious transitions 23 square law 4 standard deviation 165 standby power 23 state equations 60 space representation 60 static CMOS inverter 24 feedback 33 offset 138,139 power 13 statistics 24 step-up converters 32 stop-band rejection 7,25,84,160,166 strong inversion 39,42,45,56,58,62,144 sub micron 3-5,9,31,35,57,62,67,119,128,148 substrate bounce 35‚112,130 interference 35 noise 32,35‚100 sub-threshold currents 13,35 SUM 19-22 supply voltage 24,25,31,32,48,93 surface potential 144 swing 43,71 switch noise 50,53 switched capacitors 49,51,52,83,96,153 currents 49,53,54,55,83,104,120 switching activity 23,24 energy 10,11,14 power 13 transition 11,12 synthesis 84 procedure 25‚199 synthesizer 137 system 9 technological constants 48 technology 20,25 thermal noise 51,138 noise, conductance 38 noise, power density 38 noise, resistance 38

voltage 63‚120 thermodynamic limit 10,11 threshold mismatch 113 voltage 13,23,34 throughput 23,25 time constant 53,65 continuous 3 discrete 3 discrete filter 154,160,161,166 top-flat pulse 176,182 topology 32,38,58 total harmonic distortion (THD) 73,74,76, 86,97,116,140,141,149,181 trade-off 52,57,58,65,74 transconductance 32,41,52,53,61, 80,113,132,145 amplifier 6,123,127 tuning 69,71 transconductor 4,62,97 degenerated 62 transfer function 104,156 transistor 13 transition band 25 diagram 20 transitions 23 translinear loop 132,133,135 tree adder 22 triode region 70‚147 truncation 161‚166 tunability 69,70,97 twin-well process 36 uncertainty principle 11 undersampled noise 51,52 undersampling 51,53,83,107 unity feedback 76,80 unity gain frequency 52‚179 up-sampling 155 variable threshold 23 velocity saturation 3,4,32,97 video filter 25,27,199 video frequency 60 VLSI 1 voltage amplifier 41,43 voltage division 82 voltage mode 48,56-58 voltage noise source 75 voltage references 2 voltage scaling 23 voltage supply down scaling 39 voltage swing 31,35,38,42,45,69,95,97,112 management 13 voltage to current converter 73 W/L ratio 25 Walace tree 14 wave packet 11

214

weak avalanche 32 inversion 42,43,45,52‚56,57,63,70, 113,143,145 weighted current sources 129 white noise 39,41,47,50,51,83,100, 104,106,107,120,169 modulation 5‚106 wide-band noise 50 wire-bound 2 wireless 2 word length27 wristwatches 2 zero IF receiver 88 zero order hold 160 Z-matrix 201 Z-transform 55‚161