Power-Aware Computer Systems: Third International Workshop, PACS 2003, San Diego, CA, USA, December 1, 2003 Revised Papers [1 ed.] 3540240314, 9783540240310, 9783540286417
Welcome to the proceedings of the 3rd Power-Aware Computer Systems (PACS 2003) Workshop held in conjunction with the 36t
264 102 2MB
English Pages 215 [229] Year 2005
Table of contents :
Front Matter....Pages -
Runtime Biased Pointer Reuse Analysis and Its Application to Energy Efficiency....Pages 1-12
Inter-program Compilation for Disk Energy Reduction....Pages 13-25
Energy Consumption in Mobile Devices: Why Future Systems Need Requirements–Aware Energy Scale-Down....Pages 26-40
Efficient Scratchpad Allocation Algorithms for Energy Constrained Embedded Systems....Pages 41-56
Online Prediction of Battery Lifetime for Embedded and Mobile Devices....Pages 57-72
Synchroscalar: Initial Lessons in Power-Aware Design of a Tile-Based Embedded Architecture....Pages 73-85
Heterogeneous Wireless Network Management....Pages 86-100
“Look It Up” or “Do the Math”: An Energy, Area, and Timing Analysis of Instruction Reuse and Memoization....Pages 101-116
CPU Packing for Multiprocessor Power Reduction....Pages 117-131
Exploring the Potential of Architecture-Level Power Optimizations....Pages 132-147
Coupled Power and Thermal Simulation with Active Cooling....Pages 148-163
The Synergy Between Power-Aware Memory Systems and Processor Voltage Scaling....Pages 164-179
Hot-and-Cold: Using Criticality in the Design of Energy-Efficient Caches....Pages 180-195
PARROT: Power Awareness Through Selective Dynamically Optimized Traces....Pages 196-214
Back Matter....Pages -
Front Matter....Pages -
Runtime Biased Pointer Reuse Analysis and Its Application to Energy Efficiency....Pages 1-12
Inter-program Compilation for Disk Energy Reduction....Pages 13-25
Energy Consumption in Mobile Devices: Why Future Systems Need Requirements–Aware Energy Scale-Down....Pages 26-40
Efficient Scratchpad Allocation Algorithms for Energy Constrained Embedded Systems....Pages 41-56
Online Prediction of Battery Lifetime for Embedded and Mobile Devices....Pages 57-72
Synchroscalar: Initial Lessons in Power-Aware Design of a Tile-Based Embedded Architecture....Pages 73-85
Heterogeneous Wireless Network Management....Pages 86-100
“Look It Up” or “Do the Math”: An Energy, Area, and Timing Analysis of Instruction Reuse and Memoization....Pages 101-116
CPU Packing for Multiprocessor Power Reduction....Pages 117-131
Exploring the Potential of Architecture-Level Power Optimizations....Pages 132-147
Coupled Power and Thermal Simulation with Active Cooling....Pages 148-163
The Synergy Between Power-Aware Memory Systems and Processor Voltage Scaling....Pages 164-179
Hot-and-Cold: Using Criticality in the Design of Energy-Efficient Caches....Pages 180-195
PARROT: Power Awareness Through Selective Dynamically Optimized Traces....Pages 196-214
Back Matter....Pages -
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- Author / Uploaded
- Yao Guo
- Saurabh Chheda
- Csaba Andras Moritz (auth.)
- Babak Falsafi
- T. N. VijayKumar (eds.)
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