Passive and Active Circuits by Example 3031449657, 9783031449659

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Erkan Yuce Shahram Minaei

Passive and Active Circuits by Example

Passive and Active Circuits by Example

Erkan Yuce • Shahram Minaei

Passive and Active Circuits by Example

Erkan Yuce Department of Electrical and Electronics Engineering Pamukkale University Denizli, Türkiye

Shahram Minaei Department of Electrical and Electronics Engineering Dogus University Istanbul, Türkiye

ISBN 978-3-031-44965-9 ISBN 978-3-031-44966-6 https://doi.org/10.1007/978-3-031-44966-6

(eBook)

© The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature Switzerland AG 2024, Corrected Publication 2024 This work is subject to copyright. All rights are solely and exclusively licensed by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. The publisher, the authors, and the editors are safe to assume that the advice and information in this book are believed to be true and accurate at the date of publication. Neither the publisher nor the authors or the editors give a warranty, expressed or implied, with respect to the material contained herein or for any errors or omissions that may have been made. The publisher remains neutral with regard to jurisdictional claims in published maps and institutional affiliations. This Springer imprint is published by the registered company Springer Nature Switzerland AG The registered company address is: Gewerbestrasse 11, 6330 Cham, Switzerland Paper in this product is recyclable.

Preface

In the past three decades, research and development of active building blocks have been rapidly increased. While operational amplifier-based circuits still find nice applications, new active elements derived from concept of current conveyors have emerged as alternatives for designing active filters, simulated inductors, etc. This book deals with analysis and design of different types of active filters, simulated inductors, etc. through giving more than 200 examples. The text comprises nine chapters that are chosen to provide a complete source for the researchers, undergraduate students, and graduate students who are working on the applications and designs of active filters, simulated inductors, oscillators, rectifiers, etc. with new active elements. Chapter 1 introduces basic concepts such as symbols, units, and prefixes. Several fundamental functions such as constant, sine wave, full-wave rectified, positive halfwave rectified, square wave, triangular wave, sawtooth wave, exponential, delta, unit step, and unit ramp functions versus time are given, where 1 MHz frequency is taken for all the periodical signals. Sensitivity analysis with three examples are treated in which an arbitrary function, an RLC circuit, and two bipolar junction transistor (BJT)-based structures are used. Chapter 2 treats analog signals and systems. The concepts involving linearity, non-linearity, time-invariant, time-variant, linear time-invariant, and causality are briefly explained. Total harmonic distortion is defined, which is explained with an NMOS transistor-based simple amplifier. Definitions of Laplace and Fourier transforms are given. Ideal, second-order ideal, and first-order ideal transfer functions are discussed in detail. Chapter 3 investigates the basic passive elements, resistor, capacitor, and inductor. Current and voltage relations of these passive elements in the time domain, s domain, and frequency domain are also given. Phase and magnitude of any impedance are explained by means of many practices. Fundamental RC and RL circuits and their operating frequency ranges are given. Parallel and/or series RLC circuits are analyzed with some examples. Time domain, s domain, and frequency domain analyses for the series and parallel RC, RL, and RLC circuits are given with v

vi

Preface

some examples. Quality factors of the series and parallel RC, RL, and RLC circuits are explained. Numerous SPICE simulation results are also included to explain the given circuits in which ideal elements are used. Chapter 4 describes passive component-based voltage, current, transimpedance and transadmittance-mode first-order, second-order, and high-order filter transfer functions in detail. In the filter realizations, resistors, capacitors, and inductors are used. Combinations of resistors, capacitors, and inductors implement all the filter transfer functions. Chapter 5 deals with operational amplifiers and their applications. Some fundamental circuits based on ideal operational amplifiers are given. Several restrictions of the operational amplifier-based circuits are exhibited. Many circuits such as simulated grounded inductors, rectifiers, oscillators, and filters employing operational amplifier(s) are given. Slew rate limitations with numerous examples are given. Fullpower bandwidth is defined. Chapter 6 introduces unity gain cells, i.e., current followers and voltage followers. Current and voltage follower-based many analog circuits, for example, amplifier/attenuator, integrator, differentiator, voltage-mode filters, adder, all-pass filters, instrumentation amplifiers, etc., are given. Chapter 7 describes unity gain inverting amplifiers and negative impedance converters. A number of circuits for realizing different transfer functions, firstorder voltage-mode all-pass filters, and one first-order current-mode universal filter based on a single unity gain amplifier are given. Afterward, many circuits based on negative impedance converter(s) are investigated. Chapter 8 deals with current-mode active devices, current conveyors (CCs). These CCs are called first-generation CC (CCI), second-generation CC (CCII), and third-generation CC, and subtractor-connected CCI, current-controlled CCII (CCCII), inverting CCII, differential CC, dual X CCII, differential voltage CC, differential difference CC, fully differential CCII, current differencing CC, and extra X CCCII. A number of circuits for instance simulated inductors, oscillators, rectifiers, filters, etc. are investigated. Chapter 9 introduces other important active components, namely current feedback operational amplifier, operational transresistance amplifier, four-terminal floating nullor, operational transconductance amplifier, voltage differencing inverting buffered amplifier, voltage differencing buffer amplifier, current differencing buffered amplifier, current amplifier, current follower transconductance amplifier, current differencing transconductance amplifier, differential voltage current conveyor transconductance amplifier, and current operational amplifier. Simulated inductors are generally given as application examples for these active devices. Denizli, Türkiye Istanbul, Türkiye August 2023

Erkan Yuce Shahram Minaei

Acknowledgments

The authors would like to thank Prof. Dr. Aydin Kizilkaya, Prof. Dr. Sezai Tokat, Associate Prof. Dr. Firat Yucel, Assistant Prof. Dr. Tolga Yucehan, and Assistant Mehmet Dogan for their helpful suggestions. The author Erkan Yuce would like to dedicate the book to his wife Yildiz Yuce, his daughters Rana Nur Yuce, Gulsu Nur Yuce and his parents. The author Shahram Minaei would like to dedicate the book to his wife Elham Minayi, his daughter Aylin Minayi and his parents.

vii

Contents

1

Basic Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Symbols, Units, and Prefixes . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Some Fundamental Functions . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .

1 1 1 6 10

2

Signals, Systems, and Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Fundamentals of the Signals and Systems . . . . . . . . . . . . . . . . . . 2.2 Laplace and Fourier Transforms . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Ideal Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Ideal Second-Order Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 Ideal First-Order Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11 11 15 17 19 29 34

3

Passive Circuit Elements and Their Analysis . . . . . . . . . . . . . . . . . . . 3.1 Passive Circuit Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Passive Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 RC and RL Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 RLC Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

35 35 35 46 61 72

4

Main Transfer Functions of the Circuits . . . . . . . . . . . . . . . . . . . . . . 4.1 Definition of the Filter Transfer Function . . . . . . . . . . . . . . . . . . 4.1.1 VM FTF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.2 CM FTF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.3 TIM FTF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.4 TAM FTF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 First-Order VM FTFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.1 VM LPF TFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.2 VM HPF TFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.3 VM APF TFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

73 73 73 74 74 75 75 75 77 78 ix

x

Contents

4.3 First-Order CM FTFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 Second-Order VM FTFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 Second-Order CM FTFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6 High-Order VM BPF TF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .

79 81 84 86 87

5

Operational Amplifiers and Their Applications . . . . . . . . . . . . . . . . . 5.1 Practical Operational Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Ideal OAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 OA-Based Basic Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4 Some More Examples Based on the OA . . . . . . . . . . . . . . . . . . . 5.5 Finite Open Loop Gain of the OA . . . . . . . . . . . . . . . . . . . . . . . 5.6 Practical Open Loop Gain OA . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7 Expression of the Open Loop Gain in the Frequency Domain . . . 5.8 Gain Bandwidth Product . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.9 DC Supply Voltage Restrictions . . . . . . . . . . . . . . . . . . . . . . . . 5.10 Simulated Grounded Inductors . . . . . . . . . . . . . . . . . . . . . . . . . . 5.10.1 Lossy SGIs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.10.2 Lossless SGIs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.11 Rectifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.12 Wien Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.13 Analog Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.14 Large Signal Operation in the OA . . . . . . . . . . . . . . . . . . . . . . . 5.15 SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.16 Full-Power Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

89 89 90 92 106 108 110 116 118 121 123 123 128 132 135 138 144 145 149 150

6

Unity Gain Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 Unity Gain Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 CFs and Their Practices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 VFs and Their Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4 CF and VF-Based Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

151 151 151 166 168 174

7

Unity Gain Inverting Amplifiers and Negative Impedance Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 UGIAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3 NICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

175 175 175 179 188

Current Conveyors and Their Applications . . . . . . . . . . . . . . . . . . 8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2 CCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3 CCII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

189 189 189 193

8

. . . .

Contents

xi

8.3.1

Realizations of the Other Active Devices Based on the CCII . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.2 Realizations of the Instrumentation Amplifier Based on the CCII . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.3 Realizations of the Simulated Inductors Based on the CCII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.4 Realizations of the QOs Based on the CCII . . . . . . . . . . 8.3.5 Realizations of the CCII- Based on the CCII+s . . . . . . . 8.4 CCIII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.5 CCCII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.6 ICCII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.7 DCCII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.8 DXCCII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.9 DVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.10 DDCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.11 FDCCII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.12 CDCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.13 EX-CCCII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

194 195 195 199 200 201 203 204 206 208 209 213 216 218 221 223

Other Active Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2 CFOA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3 OTRA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4 FTFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.5 OTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.6 VDIBA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.7 VDBA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.8 CDBA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.9 CA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.10 CFTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.11 CDTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.12 DVCCTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.13 COA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

225 225 225 232 234 238 240 242 243 245 246 247 248 250 251

Correction to: Unity Gain Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C1

9

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253

About the Authors

Erkan Yuce was born in 1969 in Nigde, Turkey. He received the B.Sc. degree from Middle East Technical University, the M.Sc. degree from Pamukkale University, and the Ph.D. degree from Bogazici University, all in Electrical and Electronics Engineering in 1994, 1998, and 2006, respectively. He is currently a Professor at the Electrical and Electronics Engineering Department of Pamukkale University. His current research interests include analog circuits, active filters, synthetic inductors, and MOS transistor-based circuits. He is the author or co-author of about 190 papers published in scientific journals or conference proceedings. He is an assistant editor-in-chief of the International Journal of Electronics and Communications (AEU).

Shahram Minaei received the B.Sc. degree in Electrical and Electronics Engineering from Iran University of Science and Technology, Tehran, Iran, in 1993, and the M. Sc. and Ph.D. degrees in Electronics and Communication Engineering from Istanbul Technical University, Istanbul, Turkey, in 1997 and 2001, respectively. He is currently a Professor at the Department of Electrical and Electronics Engineering, Dogus University, Istanbul, Turkey. He has more than 190 publications in scientific journals or conference proceedings. His current field of research concerns current-mode circuits and analog signal processing. Dr. Minaei is editor of the Journal of Circuits, Systems and Computers (JCSC), International Journal of Circuit Theory and Applications (IJCTA), Elektronika ir Elektrotechnika, and editor-in-chief of the AEU – International Journal of Electronics and Communications. xiii

Chapter 1

Basic Concepts

1.1

Symbols, Units, and Prefixes

Symbols, units, and prefixes are very important issues especially in electrical and electronics engineering (EEE). The international system of units (SI) is exhibited in Table 1.1. Numerous units derived from the SI are demonstrated in Table 1.2. Furthermore, unit prefixes are given in Table 1.3 [1]. Example 1.1 Find value of 5 F/m2 in terms of fF/(μm)2 Solution 1.1 5 F/m2 = 5 × 1015 fF/(106 μm)2 = 5 × 1015 fF/1012 (μm)2 = 5 × 103 fF/ (μm)2

1.2

Some Fundamental Functions

It is a well-known fact that functions are very essential issue for science and engineering notably in EEE. Some of the fundamental functions, namely, constant, sine wave, full-wave rectified, positive half-wave rectified, square wave, triangular wave, sawtooth wave, exponential, delta, unit step, and unit ramp functions are introduced in this chapter. A constant function, namely, x1(t), is depicted in Fig. 1.1, where A is a real number and t is time variable. Therefore, the function has a constant value of A for all the times. A sine wave function is called as x2(t) = Bsin(2πft + ψ), where f > 0 is the frequency, |B| is the peak value, and -180° ≤ ψ ≤ 180° is the phase angle. Furthermore, f and B are real numbers, while ω = 2πf is angular frequency, and T = 1/f is the period. The function x2(t) is depicted in Fig. 1.2 in which B = 500 mV, f = 1 MHz, and ψ = 60° are chosen as a practice. A full-wave rectified function at 1 MHz is depicted in Fig. 1.3, while a positive half-wave © The Author(s), under exclusive license to Springer Nature Switzerland AG 2024 E. Yuce, S. Minaei, Passive and Active Circuits by Example, https://doi.org/10.1007/978-3-031-44966-6_1

1

2 Table 1.1 International system of units (SI)

1 Fundamental physical quantity Length Mass Time Electric current Thermodynamic temperature Amount of substance Luminous intensity

Basic Concepts

SI Meter Kilogram Second Ampere Kelvin Mole Candela

SI symbol m kg s A K mol cd

Table 1.2 A number of units derived from the SI Unit(s) Force, weight Frequency Energy, work, heat Electric charge Electric potential (voltage) Magnetic flux Inductance Capacitance Resistance, impedance, reactance Electrical conductance Magnetic flux density Power, radiant flux Angle

SI Newton Hertz Joule Coulomb Volt Weber Henry Farad Ohm

SI symbol N Hz J C V Wb H F Ω

Expressed in SI-based unit kgms-2 s-1 kg.m2.s-2 A.s kg.m2.s-3.A-1 kg.m2.s-2.A-1 kg.m2.s-2.A-2 kg-1.m-2.s4.A2 kg.m2.s-3.A-2

Expressed in other SI unit – – Nm – J/C Vs Wb/A C/V V/A

Siemens Tesla Watt Radian

S T W rad

kg-1.m-2.s3.A2 kg.s-2.A-1 kg.m2.s-3 m.m-1

A/V Wb/m2 J/s –

rectified function at 1 MHz is depicted in Fig. 1.4. In Figs. 1.3 and 1.4, sinusoidal signals with peak 500 mV at 500 kHz and 1 MHz are applied, respectively. In addition, a full-wave rectifier output is obtained from any function by taking absolute value of this function. A square wave function at 1 MHz is demonstrated in Fig. 1.5, while a triangular wave function at 1 MHz is shown in Fig. 1.6. A sawtooth wave function is plotted in Fig. 1.7 at 1 MHz, while an exponential one is given in Fig. 1.8. Further, this exponential function is defined as x3(t) = 0.5exp(-t/10-6) for t ≥ 0. δΔ(t) function is shown in Fig. 1.9 [2]. Delta function, namely, δ(t), is defined as δðt Þ = lim δΔ ðt Þ Δ→0

ð1:1Þ

uΔ(t) function is exhibited in Fig. 1.10. Unit step function, namely, u(t), is given below.

1.2

Some Fundamental Functions

Table 1.3 Unit prefixes

3

Name Yocto Zepto Atto Femto Pico Angstrom Nano Micro Mili Santi Desi Kilo Mega Giga Tera Peta Exa Zetta Yotta

Symbol y z a f p Ao n μ m c d k M G T P E Z Y

Prefix multiplier ×10-24 ×10-21 ×10-18 ×10-15 ×10-12 ×10-10 ×10-9 ×10-6 ×10-3 ×10-2 ×10-1 ×103 ×106 ×109 ×1012 ×1015 ×1018 ×1021 ×1024 x1(t)

Fig. 1.1 A constant function

A

t

uðt Þ = lim uΔ ðt Þ Δ→0

ð1:2Þ

u(t) function is depicted in Fig. 1.11, and unit ramp function demonstrated in Fig. 1.12 is computed as follows: t

uðτÞdτ = tuðt Þ

r ðt Þ =

ð1:3Þ

-1

Some relations among δ(t), u(t), and r(t) functions are given below. uð t Þ =

dr ðt Þ dt

ð1:4aÞ

4

1

Basic Concepts

Fig. 1.2 A sine wave function at 1 MHz

Fig. 1.3 A full-wave rectifier function at 1 MHz

δðt Þ =

duðt Þ d2 rðt Þ = dt dt 2

ð1:4bÞ

1.2

Some Fundamental Functions

5

Fig. 1.4 A half-wave rectifier function at 1 MHz

Fig. 1.5 A square wave function at 1 MHz t

uð t Þ =

δðτÞdτ -1

ð1:4cÞ

6

1

Basic Concepts

Fig. 1.6 A triangular wave function at 1 MHz

Fig. 1.7 A sawtooth wave function at 1 MHz

1.3

Sensitivity

The sensitivity, namely, the robustness of the outcomes of any models, deals with the effect of independent parameters on the dependent ones. Sensitivity of any function y(x, z, w) to x is defined in Eq. (1.5).

1.3

Sensitivity

7

Fig. 1.8 An exponential function G'(t)

Fig. 1.9 Representation of δΔ(t) function

1/'

-'/2 '/2

t

u'(t)

Fig. 1.10 Representation of uΔ(t) function

1 1/2

'

-'

Fig. 1.11 Representation of u(t) function

t

u(t) 1

t

8

1

Basic Concepts

r(t)

Fig. 1.12 Representation of r(t) function

1 t

∂yðx, z, wÞ x yðx, z, wÞ ∂x

Syxðx,z,wÞ =

ð1:5Þ

Note It is desired that sensitivities of any functions should be small in magnitude [3–8]. Example 1.2 Find the sensitivity of function F(x) to x shown below in which B is a real number. F ðxÞ =

x x-B

ð1:6Þ

Solution 1.2 The sensitivity of the function F(x) given above with respect to x is evaluated as in the following: SFx ðxÞ =

x x x-B

d x B = dx x - B B-x

ð1:7Þ

Note It is observed from Eq. (1.7) that if x approaches to B, sensitivity goes to infinity in magnitude. As a result, the function given in (1.6) is an undesired function due to sensitivity point of view. Example 1.3 A parallel/series RLC circuit has the angular resonance frequency (ω0) as given in Eq. (1.8). Thus, find the sensitivities of ω0 to both passive elements. 1 ω0 = p LC

ð1:8Þ

Solution 1.3 The sensitivities of ω0 to both passive elements are found as SωL 0 =

L dω0 1 =ω0 dL 2

ð1:9aÞ

SωC0 =

1 C dω0 =2 ω0 dC

ð1:9bÞ

1.3

Sensitivity

9 VCC

Fig. 1.13 A simple BJT-based circuit VBB

RB

IC1

VCC

Fig. 1.14 A BJT-based circuit with a resistor in emitter VBB

RB

IC2

RE

In order to express sensitivity more, bipolar junction transistor (BJT)-based simple circuits operated in the forward active region are given in Figs. 1.13 and 1.14 as examples. It is assumed that both BJTs are identical. Thus, collector currents of the topologies given in Figs. 1.13 and 1.14 are, respectively, computed as [9] βF ðV BB - V BE Þ RB

ð1:10aÞ

βF ðV BB - V BE Þ RB þ ðβF þ 1ÞRE

ð1:10bÞ

I C1 = I C2 =

Sensitivities of the collector currents demonstrated in Figs. 1.13 and 1.14 to the current gain (βF = IC/IB) can be, respectively, given below. βF dI C1 =1 I C1 dβF

ð1:11aÞ

βF dI C2 RB þ RE = I C2 dβF RB þ ðβF þ 1ÞRE

ð1:11bÞ

= SIβC1 F = SIβC2 F

One observes from the equations denoted in (1.11a) and (1.11b) that the circuit in Fig. 1.14 is less sensitive than one exhibited in Fig. 1.13 due to the resistor RE. In Eqs. (1.11a) and (1.11b), dIC1/dβF and dIC2/dβF are, respectively, evaluated by dI C1 V BB - V BE = dβF RB

ð1:12aÞ

10

1

Basic Concepts

dI C2 ðV BB - V BE ÞðRB þ ðβF þ 1ÞRE Þ - βF ðV BB - V BE ÞRE = dβF ðRB þ ðβF þ 1ÞRE Þ2 ðV BB - V BE ÞðRB þ RE Þ = ðRB þ ðβF þ 1ÞRE Þ2

ð1:12bÞ

It is understood from above that sensitivity gives a measure for performances of the circuit with respect to their elements or parameters. In other words, it provides selection of the adequate element tolerances [10].

References 1. J.W. Nilsson, S.A. Riedel, Electric Circuits, 10th edn. (Pearson, 2015) 2. A.V. Oppenheim, A.S. Willsky, S.H. Nawab, Signals and Systems, Pearson New International Edition (Pearson Education Limited, Harlow, 2013) 3. A.B. Williams, Analog Filter and Circuit Design Handbook (McGraw Hill Professional, 2013) 4. R. Schaumann, M.E.V. Valkenburg, Design of Analog Filters (Oxford University Press, 2001) 5. A.F. Anday, Aktif devre sentezi (Istanbul Technical University, 1992) 6. A. Anand, M. Agrawal, N. Bhatt, M. Ram, Advances in System Reliability Engineering (Elsevier, Academic, 2019), pp. 267–279 7. E.A. Ustinov, Sensitivity Analysis in Remote Sensing (Springer Briefs in Earth Sciences, 2015) 8. https://www.embedded.com/analyzing-circuit-sensitivity-for-analog-circuit-design/ 9. A.S. Sedra, K.C. Smith, T.C. Carusone, V. Gaudet, Microelectronic Circuits, 8th edn. (Oxford University Press, New York, 2020) 10. N.B. Hamida, B. Kaminska, Multiple fault analog circuit testing by selectivity analysis. Analog Integr. Circ. Sig. Process 4(3), 231–243 (1993)

Chapter 2

Signals, Systems, and Filters

2.1

Fundamentals of the Signals and Systems

Signals can be mainly divided into two subcategories, voltage and current ones. Furthermore, they can be separated into two subgroups, analog and digital ones [1]. In this book, we concentrate on the analog voltage and current signals. Linearity and time-invariance are other important issues. However, full-wave rectifier configurations are nonlinear, while rheostat is a variable resistor. It is assumed that active and passive circuits given in Figs. 2.1 and 2.2 are linear time-invariant (LTI). The circuits exhibited in Figs. 2.1 and 2.2 are examples for the circuit analysis and circuit synthesis, respectively. In Fig. 2.1, vin(t) and the circuit are known, where the output is required. Additionally, in Fig. 2.2, vin(t) and vout(t) are known in which the circuit is required. In Fig. 2.1, the circuit has only a single output voltage, while the topology in Fig. 2.2 can be implemented in several methods [2]. If the circuit in Fig. 2.1 is an active structure, its output voltage with respect to the input voltage can be defined as follows [3]: vout ðt Þ = f ðvin ðt ÞÞ =

1 k=0

ak ðt Þvink ðt Þ

= a0 ðt Þ þ a1 ðt Þvin ðt Þ þ

ð2:1Þ a2 ðt Þv2in ðt Þ

þ ...

where v0in(t) = 1, ak(t) (k = 0, 1, 2, . . .) is a complex number and k of vkin(t) represents kth exponent. The circuit is nonlinear and time-varying for a0(t) ≠ 0, even if it is as in the following form:

© The Author(s), under exclusive license to Springer Nature Switzerland AG 2024 E. Yuce, S. Minaei, Passive and Active Circuits by Example, https://doi.org/10.1007/978-3-031-44966-6_2

11

12

2

Fig. 2.1 A circuit used in the analysis

+ vin(t) _

Fig. 2.2 A circuit utilized in the synthesis

Signals, Systems, and Filters

Given circuit

+ vin(t) _

+ Calculated output

_

Required circuit

+ vout(t) _

1

vout ðt Þ = k=0

ak ðt Þvkin ðt Þ = a0 ðt Þ þ a1 ðt Þvin ðt Þ

ð2:2Þ

The circuit in Fig. 2.1 is linear if its output voltage is as in the following: vout ðt Þ = a1 ðt Þvin ðt Þ

ð2:3Þ

However, equation in (2.3) is time-varying. Apart from this, if the circuit in Fig. 2.1 is time-invariant, it has generally the following equation: vout ðt Þ =

1

ak vkin ðt Þ

ð2:4Þ

k=0

If the configuration in Fig. 2.1 is LTI, it can be defined below. vout ðt Þ = a1 vin ðt Þ

ð2:5Þ

An LTI circuit can be generally shown as n

bk k=0

dk vout ðt Þ = dt k

m

ai i=0

di vin ðt Þ dt i

ð2:6Þ

where a0(d0v(t)/dt0) = a0v(t), bk (k = 0, 1, 2, . . . , n), and ai (i = 0, 1, 2, . . ., m) are time-invariant complex numbers. Also, n ≥ m is required for causality [3]. Input voltage signal and corresponding output voltage signal can be, respectively, demonstrated by vin ðt Þ = A sinðωt Þ

ð2:7aÞ

2.1

Fundamentals of the Signals and Systems

13 VDD

Fig. 2.3 An NMOS transistor-based simple amplifier circuit [4]

RD

iD(t) vout(t)

M

vin(t)

VA

vout ðtÞ =

1

ð2:7bÞ

Bk cosðkωtÞ k=0

From Eq. (2.7b), the total harmonic distortion (THD) is defined as

THD = 100 ×

1 k=2

Bk B1

2

ð2:8Þ

One observes from equation given in (2.8) that DC term of the output signal is not utilized in calculation of the THD. Furthermore, the first nine harmonics including fundamental harmonic are taken in the SPICE simulation program. Example 2.1 Find the THD value of the NMOS transistor-based simple amplifier in Fig. 2.3. Solution 2.1 It is assumed that the transistor operates in the saturation region. If the channel-length modulation effect is ignored, drain current of the circuit in Fig. 2.3 is computed as iD ðt Þ = I D þ id ðt Þ þ io ðt Þ 1 = k n ðvin ðt Þ - V A - V TN Þ2 2 1 1 = k n ð - V A - V TN Þ2 þ kn ð - V A - V TN Þvin ðt Þ þ kn v2in ðt Þ 2 2

ð2:9Þ

Here, VTN is the threshold voltage of the NMOS transistor, while kn is transconductance parameter. In addition, VA is sufficiently less than -VTN. Thus, constant current (ID), desired current (id(t)), and other current (io(t)) signals are, respectively, calculated as ID =

1 k ð- V A - V TN Þ2 2 n

ð2:10aÞ

14

2

Signals, Systems, and Filters

id ðt Þ = kn ð- V A - V TN Þvin ðt Þ io ðt Þ =

1 2 k v ðt Þ 2 n in

ð2:10bÞ ð2:10cÞ

Note cos(2ω0t) = 2cos2(ω0t) - 1. If vin(t) = Acos(ω0t) is chosen, id(t) and io(t) are, respectively, computed by id ðt Þ = k n ð- V A - V TN ÞA cosðω0 t Þ 1 1 1 þ cos ð2ω0 t Þ io ðt Þ = kn ðA cos ðω0 t ÞÞ2 = kn A2 2 2 2 1 2 1 2 = kn A þ kn A cos ð2ω0 t Þ 4 4 = I DC þ iu ðt Þ

ð2:11aÞ

ð2:11bÞ

From (2.11b), IDC and undesired current (iu(t)) are, respectively, written as 1 k A2 4 n

ð2:12aÞ

1 k A2 cosð2ω0 t Þ 4 n

ð2:12bÞ

I DC = i u ðt Þ =

vout(t) of the circuit exhibited in Fig. 2.3 is found as in the following: vout ðt Þ = V DD - RD × iD ðt Þ = V DD - RD × ðI D þ id ðt Þ þ io ðt ÞÞ = V DD - RD × ðI D þ I DC þ id ðt Þ þ iu ðt ÞÞ

ð2:13Þ

If constant currents in vout(t) of equation in (2.13) are ignored, AC part of the output voltage (vout/(t)) is obtained as =

vout ðt Þ = RD × ðid ðt Þ þ iu ðt ÞÞ 1 = RD × k n ð - V A - V TN ÞA cos ðω0 t Þ þ k n A2 cos ð2ω0 t Þ 4 = B1 cos ðω0 t Þ þ B2 cos ð2ω0 t Þ

ð2:14Þ

Here, B1 = RD × kn(-VA-VTN)A and B2 = RD × knA2/4. Finally, THD of the circuit in Fig. 2.3 is evaluated as

2.2

Laplace and Fourier Transforms

THD = 100 ×

1 k=2

Bk B1

15

2

2

Bk B1

= 100 × k=2

2

1 RD × kn A2 A 4 = 25 × = 100 × RD × k n ð - V A - V TN ÞA - V A - V TN

2.2

ð2:15Þ

Laplace and Fourier Transforms

By taking all the initial conditions zero, Laplace transforms of vin(t) and vout(t) in Fig. 2.2 are, respectively, found as follows: V in ðsÞ =

1 -1

vin ðtÞe - st dt

ð2:16aÞ

1

vout ðt Þe - st dt

V out ðsÞ =

ð2:16bÞ

-1

By using equations given in (2.6), (2.16a), and (2.16b), a transfer function (TF) can be defined as m

V ðsÞ H ðsÞ = out = V in ðsÞ

i=0 n j=0

ai si ð2:17Þ bj sj

In Eq. (2.17), real parts of all the poles must be negative for the stability. The following condition, m ≤ n (m ≥ 0 and n ≥ 1) is required for the causality. If m ≥ 1 and n ≥ 1, the equation in (2.17) can be expressed as follows: m

H ðsÞ = K

j=1 n i=1

s þ zj ð s þ pi Þ

ð2:18Þ

Here, K = am/bn. Also, -pi (i = 1, 2, 3,. . ., n) and -zj ( j = 1, 2, 3,. . ., m) are poles and zeroes, respectively. pi given in Eq. (2.18) can be written as

16

2

pi = σ i þ jωi

Signals, Systems, and Filters

ð2:19Þ

If real part of pi = σ i > 0, it is stable. If σ i = 0 and ωi ≠ ωk (k = 1, 2, 3, . . ., n and i ≠ k), it is marginally stable. Otherwise, it is unstable. By taking all the initial conditions zero, Fourier transform of vin(t) in Fig. 2.2 is found as Vin(ω). Likewise, Fourier transform of vout(t) is computed as Vout(ω). Vin(ω) and Vout(ω) are, respectively, given by 1

V in ðωÞ =

vin ðt Þe - jωt dt

ð2:20aÞ

vout ðt Þe - jωt dt

ð2:20bÞ

-1 1

V out ðωÞ = -1

By using equations in (2.20a) and (2.20b), TF of the circuit can be defined as H ð ωÞ =

V out ðωÞ V in ðωÞ

ð2:21Þ

Equation given in (2.21) can be expressed by HðωÞ = jHðωÞjej∠HðωÞ

ð2:22Þ

where ∠H(ω) is phase and |H(ω)| is gain. Thus, the relationship between input and output of the circuit in the time domain and frequency domain are, respectively, given as vout ðt Þ = hðt Þ  vin ðt Þ

ð2:23aÞ

V out ðωÞ = H ðωÞV in ðωÞ

ð2:23bÞ

Here, h(t) is impulse response of the LTI topology, while H(ω) is its Fourier transform. In addition, * is the convolution operator. Note Gain of the passive circuit is between zero and one, while gain of the active configuration can be any positive or negative real numbers. In other words, gain of the active circuit can be more or less than unity in magnitude [1].

2.3

2.3

Ideal Filters

17

Ideal Filters

Ideal low-pass filter (LPF), band-pass filter (BPF), notch filter (NF), and high-pass filter (HPF) have noncausal TFs, but they can be tried to realize with some approximations such as Butterworth, Chebyshev, etc. TFs of the LPF, BPF, NF and HPF are, respectively, demonstrated in Figs. 2.4, 2.5, 2.6, and 2.7, while ideal all-pass filter (APF) TF that is causal is exhibited in Fig. 2.8. ωC in Figs. 2.4 and 2.7 is angular cutoff frequency. Additionally, ω1 and ω2 in Figs. 2.5 and 2.6 are angular cutoff frequencies. LPF has a bandwidth (BW) of ωC, while HPF and APF possess

Fig. 2.4 Characteristics of the ideal LPF

H LP ( )

1

0 Fig. 2.5 Characteristics of the ideal BPF

C

H BP ( )

1

0 Fig. 2.6 Characteristics of the ideal NF

1

2

1

2

H NF ( )

1

0

18

2

Signals, Systems, and Filters

H HP ( )

Fig. 2.7 Characteristics of the ideal HPF

1

0

C

H AP ( )

Fig. 2.8 Characteristics of the ideal APF

1

0 infinity BW. BPF and NF have the following equations for ωC, BW, and quality factor (Q) [5, 6]: ω2C = ω1 × ω2

ð2:24aÞ

BW = ω2 - ω1 ω Q= C BW

ð2:24bÞ ð2:24cÞ

ωC of BPF and NF in Figs. 2.5 and 2.6 is angular resonance frequency or center frequency. Ideal filters demonstrated in Figs. 2.4, 2.5, 2.6, 2.7, and 2.8 can be, respectively, expressed as jH LP ðωÞj = jH BP ðωÞj = jH NF ðωÞj =

1

1 ω ≤ ωC 0 ω > ωC ω 1 ≤ ω ≤ ω2

0 ω < ω1 and ω > ω2 1 0

ω ≤ ω1 and ω ≥ ω2 ω1 < ω < ω 2

ð2:25aÞ ð2:25bÞ ð2:25cÞ

2.4

Ideal Second-Order Filters

19

jH HP ðωÞj =

1 0

ω ≥ ωC ω < ωC

jH AP ðωÞj = 1 ω ≥ 0

ð2:25dÞ ð2:25eÞ

Note For the characteristics given in Figs. 2.4, 2.5, 2.6, 2.7, and 2.8, the negative frequency responses are ignored.

2.4

Ideal Second-Order Filters

A second-order universal filter can realize all the LPF, BPF, NF, HPF, and APF responses [7]. Non-inverting second-order unity gain LPF, BPF, NF, HPF, and APF phase and gain responses for different Q values are, respectively, depicted in Figs. 2.9, 2.10, 2.11, 2.12, and 2.13, which are obtained by using one resistor, one capacitor, and one inductor. Resonance frequency of these filter circuits is taken as f0 ffi 1.59 MHz. Non-inverting second-order unity gain LPF, BPF, NF, HPF, and APF in Figs. 2.9, 2.10, 2.11, 2.12, and 2.13 are, respectively, given below. H LP ðsÞ =

ω20 DðsÞ

ð2:26aÞ

Fig. 2.9 Non-inverting second-order unity gain LPF phase and gain responses for different quality factors against frequency

20

2

Signals, Systems, and Filters

Fig. 2.10 Non-inverting second-order unity gain BPF phase and gain responses for different quality factors versus frequency

Fig. 2.11 Non-inverting second-order unity gain NF phase and gain responses for different quality factors with respect to frequency

H BP ðsÞ =

ω0 Q

s DðsÞ

ð2:26bÞ

2.4

Ideal Second-Order Filters

21

Fig. 2.12 Non-inverting second-order unity gain HPF phase and gain responses for different quality factors versus frequency

Fig. 2.13 Non-inverting second-order unity gain APF phase and gain responses for different quality factors against frequency

H NF ðsÞ =

s2 þ ω20 D ðs Þ

ð2:26cÞ

22

2

s2 DðsÞ

H HP ðsÞ = H AP ðsÞ =

Signals, Systems, and Filters

s2 -

ð2:26dÞ

ω0 Q

s þ ω20 DðsÞ

ð2:26eÞ

The denominator, D(s), in Eq. (2.26) is in the form of DðsÞ = s2 þ

ω0 s þ ω20 Q

ð2:27Þ

Here, ω0 is angular resonance frequency, while Q is quality factor. Apart from this, bandwidth (BW) is evaluated by BW =

ω0 Q

ð2:28Þ

An ideal non-inverting second-order unity gain LPF in the frequency domain has, respectively, the following phase and gain responses: ∠H LP ðωÞ = - Arctan

ω0 ω Q ω20 - ω2

ð2:29aÞ

ω20

jH LP ðωÞj = ω20

2 - ω2

þ

ω0 ω Q

2

ð2:29bÞ

It is seen from Fig. 2.9 and equation indicated in (2.29a) that phase responses of the non-inverting second-order LPF will vary from 0° to -180° if the frequency changes from 0° to infinity. Phase of the LPF is equal to -90° at the resonance frequency. In addition, if f >> f0, gain of the LPF decreases with -40 dB/decade. On the other hand, an ideal non-inverting second-order unity gain BPF in frequency domain has, respectively, the following phase and gain responses: ∠H BP ðωÞ = 90 ° - Arctan

ω0 ω Q ω20 - ω2

ð2:30aÞ

ω0 ω Q

jH BP ðωÞj = ω20

2 - ω2

þ

ω0 ω Q

2

ð2:30bÞ

An ideal non-inverting second-order unity gain NF in the frequency domain has, respectively, the following phase and gain responses:

2.4

Ideal Second-Order Filters

23

ω0 ω Q - Arctan ω20 - ω2 ∠H NF ðωÞ =

if ω < ω0

if ω = ω0 ω0 ω Q if ω > ω0 180 ° - Arctan 2 ω0 - ω2 0

ω20 - ω2

jH NF ðωÞj =

ω20 - ω2

2

þ

ω0 ω Q

2

ð2:31aÞ

ð2:31bÞ

Likewise, an ideal non-inverting second-order unity gain HPF in the frequency domain has, respectively, the following phase and gain responses: ∠H HP ðωÞ = 180 ° - Arctan

ω0 ω Q ω20 - ω2

ω2

jH HP ðωÞj = ω20

2 - ω2

þ

ω0 ω Q

2

ð2:32aÞ ð2:32bÞ

Phase of the HPF is equal to 90° at the resonance frequency. In addition, if f ω0 360 ° - Arctan ω20 - ω2

ð2:37Þ

Likewise, an ideal inverting second-order unity gain HPF in the frequency domain has the following phase response: ∠H HP ðωÞ = - Arctan

ω0 ω Q ω20 - ω2

ð2:38Þ

Finally, an ideal inverting second-order unity gain APF in the frequency domain has the following phase response: ∠H AP ðωÞ = 180 ° - 2Arctan

ω0 ω Q 2 ω 0 - ω2

ð2:39Þ

One observes from Eq. (2.39) that phase response varies from 180° to -180° as the frequency goes from zero to infinity. Note For the non-inverting and inverting second-order universal filter responses, magnitudes of the gains can be more or less than unity if active devices are used in the implementation of the filter structures. Example 2.2 Find the frequency of the second-order LPF for Q > 1/√2, where the gain is maximum. Solution 2.2 Derivative of the gain of the second-order LPF defined in Eq. (2.29b) is taken as

28

2 2 2 d jH LP ðωÞj 2 × ω × ω0 ω0 1 = dω 2 ω20 - ω2 þ

Signals, Systems, and Filters

1 2Q2

- ω2

ω0 ω Q

2

ð2:40Þ

3 2

If equation given in (2.40) is taken as zero, maximum frequency value is found. Therefore, the following more simpler equation is obtained as: 1 1 = 0 ) ω2 = ω20 1 2Q2 2Q2

ω2 - ω20 1 -

ð2:41Þ

Therefore, ωmax is evaluated as 1-

ωmax = ± ω0

1 2Q2

ð2:42Þ

However, ωmax > 0; thus, it is found by ωmax = ω0

1-

1 2Q2

ð2:43Þ

Note ωmax = 0 for Q ≤ 1/√2. Example 2.3 Find the ωC of the second-order LPF with respect to ω0 and Q. Solution 2.3 Firstly, |HLP(ω)| = 1/√2 is taken. Afterward, the following equation is obtained: ω20 ω20

2 - ω2

þ

ω0 ω Q

1 =p 2

2

ð2:44Þ

ω = ωC

From equation given in (2.44), the following equation is obtained: ω40 ω20

2 - ω2C

þ

ω0 ωC Q

2

=

1 ) ω20 - ω2C 2

2

þ

ω 0 ωC Q

2

= 2ω40

ð2:45Þ

If the equation given in (2.45) is expanded, the following equation is obtained: Q2 ω4C þ ω20 ω2C - 2Q2 ω20 ω2C - Q2 ω40 = 0 The above equation simplifies as

ð2:46Þ

2.5

Ideal First-Order Filters

29

ω4C - ω2C 2 -

1 ω2 - ω40 = 0 Q2 0

ð2:47Þ

Solution of the equation exhibited in (2.47), the following ωC is found: ωC = ±

ω0 p Q 2

2Q2 - 1 þ

8Q4 - 4Q2 þ 1

ð2:48Þ

Nevertheless, ωC must be greater than zero. The equation in (2.48) turns into ωC =

ω0 p Q 2

2Q2 - 1 þ

8Q4 - 4Q2 þ 1

ð2:49Þ

If Q = 1/√2 is taken, ωC = ω0 is obtained. Example 2.4 Find gains of the ideal second-order LPF, BPF, and HPF. Solution 2.4 Gains of the ideal second-order LPF, BPF, and HPF are, respectively, found as follows: GLP = lim jH LP ðωÞj

ð2:50aÞ

GBP = jH BP ðωÞjω = ω0

ð2:50bÞ

GHP = ωlim j H ð ωÞ j → 1 HP

ð2:50cÞ

ω→0

2.5

Ideal First-Order Filters

It is a well-known fact that a first-order universal filter can realize all the LPF, HPF, and APF responses. Non-inverting and inverting first-order unity gain LPF, HPF, and APF phase and gain responses are, respectively, exhibited in Figs. 2.19, 2.20, and 2.21, which are obtained by using resistors and capacitors. Pole frequency of the filter circuits in these figures is chosen as f0 ffi 1.59 MHz. Non-inverting and inverting first-order unity gain LPF, HPF, and APF shown in Figs. 2.19, 2.20, and 2.21 are, respectively, given as follows: H LP ðsÞ = ±

ω0 DðsÞ

ð2:51aÞ

30

2

Signals, Systems, and Filters

Fig. 2.19 Non-inverting and inverting first-order unity gain LPF phase and gain responses against frequency

Fig. 2.20 Non-inverting and inverting first-order unity gain HPF phase and gain responses versus frequency

2.5

Ideal First-Order Filters

31

Fig. 2.21 Non-inverting and inverting first-order unity gain APF phase and gain responses with respect to frequency

s DðsÞ ω0 - s H AP ðsÞ = ± DðsÞ H HP ðsÞ = ±

ð2:51bÞ ð2:51cÞ

Here, + sign corresponds to the non-inverting filters, while - sign is related to the inverting filters. Further, the denominator, D(s) is given as DðsÞ = s þ ω0

ð2:52Þ

where ω0 is the angular pole frequency. TFs of Eq. (2.51) in the frequency domain convert to H LP ðωÞ = ±

ω0 DðωÞ

ð2:53aÞ

H HP ðωÞ = ±

jω DðωÞ

ð2:53bÞ

ω0 - jω DðωÞ

ð2:53cÞ

H AP ðωÞ = ± Here, the denominator, D(ω) is given by

32

2

DðωÞ = ω0 þ jω

Signals, Systems, and Filters

ð2:54Þ

If the TFs in Eq. (2.53) are non-inverting, they have, respectively, the following phase responses: ∠H LP ðωÞ = - Arctan

ω ω0 ω ω0

∠H HP ðωÞ = 90 ° - Arctan ∠H AP ðωÞ = - 2Arctan

ð2:55aÞ

ω ω0

ð2:55bÞ ð2:55cÞ

One observes from equation in (2.55c) that phase response varies from 0° to -180° as the frequency goes from zero to infinity. Apart from this, if the TFs in Eq. (2.53) are inverting, they have, respectively, the following phase responses: ∠H LP ðωÞ = 180 ° - Arctan

ω ω0

ð2:56aÞ

∠H HP ðωÞ = - 90 ° - Arctan

ω ω0

ð2:56bÞ

∠H AP ðωÞ = 180 ° - 2Arctan

ω ω0

ð2:56cÞ

One sees from equation in (2.56c) that phase response varies from 180° to 0° as the frequency goes from zero to infinity. On the other hand, gains of the TFs of equations in (2.53) can be given below. jH LP ðωÞj = jH HP ðωÞj =

jH AP ðωÞj =

ω0 ω20 þ ω2

ð2:57aÞ

ω þ ω2

ð2:57bÞ

ω20

ω20 þ ð- ωÞ2 ω20 þ ω2

=1

ð2:57cÞ

It is observed from equations in (2.57a) and (2.57b) that gain of the first-order LPF decreases -20 dB/decade if ω >> ω0, while gain of the first-order HPF increases 20 dB/decade if ω > f0, gain of the fourth-order Butterworth LPF decreases as -80 dB/decade.

34

2

Signals, Systems, and Filters

Fig. 2.23 Phase and gain responses of the fourth-order Butterworth LPF versus frequency

References 1. A.S. Sedra, K.C. Smith, T.C. Carusone, V. Gaudet, Microelectronic Circuits, 8th edn. (Oxford University Press, New York, 2020) 2. A.F. Anday, Devre ve sistem analizi çözümlü problemler (Birsen, 2004) 3. A.V. Oppenheim, A.S. Willsky, S.H. Nawab, Signals and Systems, Pearson New International Edition. (Pearson Education Limited, Harlow, 2013) 4. B. Razavi, Fundamentals of Microelectronics: With Robotics and Bioengineering Applications, 3rd edn. (Wiley, 2021) 5. A.B. Williams, Analog Filter and Circuit Design Handbook (McGraw Hill Professional, 2013) 6. R. Schaumann, M.E.V. Valkenburg, Design of Analog Filters (Oxford University Press, 2001) 7. E. Yuce, A single-input multiple-output voltage-mode second-order universal filter using only grounded passive components. Indian J. Eng. Mater. Sci. 24(2), 97–106 (2017) 8. E. Yuce, S. Minaei, H. Alpaslan, Single voltage controlled CMOS grounded resistors and their application to video filter. Indian J. Eng. Mater. Sci. 21(5), 501–509 (2014)

Chapter 3

Passive Circuit Elements and Their Analysis

3.1

Passive Circuit Elements

Electrical symbols of the fundamental passive elements, resistor, capacitor, and inductor are depicted in Fig. 3.1. Capacitor and inductor are called as energy storage elements and possess memory. However, resistor is memoryless and dissipates power. As state variables, the capacitor has a voltage across its terminals, while the inductor has a current in it. These voltage and current are stated as initial conditions for the capacitor and inductor, respectively. In addition, their current and voltage relationships in the time domain, s domain (complex frequency domain), and frequency domain are given in Table 3.1. It is seen from Table 3.1 that the voltage across the capacitor terminals and the current passing through the inductor are continuous.

3.2

Passive Circuits

Passive elements can be divided into two subcategories: grounded and floating passive elements. Two identical grounded passive circuits are demonstrated in Figs. 3.2 and 3.3. A voltage source is applied to the topology given in Fig. 3.2, while a current source is applied to the same configuration in Fig. 3.3 [1, 2]. Input impedance and admittance of the circuit given in Fig. 3.2 are, respectively, computed as follows: Z=

V test I circuit

© The Author(s), under exclusive license to Springer Nature Switzerland AG 2024 E. Yuce, S. Minaei, Passive and Active Circuits by Example, https://doi.org/10.1007/978-3-031-44966-6_3

ð3:1aÞ

35

36

3

Fig. 3.1 Fundamental passive circuit components (a) resistor, (b) capacitor, and (c) inductor

Passive Circuit Elements and Their Analysis

+

IR

+

VR _

R

VC _

(a)

IC C

+

IL

VL _

L

(b)

(c)

Table 3.1 Current and voltage relationships of the fundamental passive circuit components Passive elements Resistor Capacitor Inductor

Domain Time vR(t) = RiR(t) C ðt Þ iC ðt Þ = C dvdt L ðt Þ vL ðt Þ = L didt

s VR(s) = RIR(s) IC(s) = sCVC(s)

Frequency VR(ω) = RIR(ω) IC(ω) = jωCVC(ω)

VL(s) = sLIL(s)

VL(ω) = jωLIL(ω)

Icircuit

Fig. 3.2 A voltage source applied to the grounded passive circuit

Vtest + _

Fig. 3.3 A current source applied to the grounded passive circuit

Itest

Y=

I circuit V test

+ Vcircuit _

Passive circuit

Passive circuit

ð3:1bÞ

Input impedance and admittance of the circuit shown in Fig. 3.3 are, respectively, calculated below. Z=

V circuit I test

ð3:2aÞ

Y=

I test V circuit

ð3:2bÞ

The circuit of Fig. 3.3 has the same input impedance and admittance as the topology in Fig. 3.2 possesses. Example 3.1 Find phase and magnitude of the input impedance of the ideal resistor shown in Fig. 3.4.

3.2

Passive Circuits

37

Vin

Fig. 3.4 An ideal grounded resistor

Iin R

ZR Vin

Fig. 3.5 An ideal grounded capacitor

Iin C

ZC Solution 3.1 The input impedance of the resistor in the frequency domain is evaluated as Z R ð ωÞ =

V in ðωÞ =R I in ðωÞ

ð3:3Þ

Input impedance of the resistor given in Eq. (3.3) can be expressed as Z R ðωÞ = jZ R ðωÞjej∠Z R ðωÞ

ð3:4Þ

Here, ∠ZR(ω) is defined as phase, and |ZR(ω)| is defined as magnitude of the input impedance of the resistor. In addition, they are, respectively, computed as ∠Z R ðωÞ = 0o

ð3:5aÞ

j Z R ð ωÞ j = R

ð3:5bÞ

Example 3.2 Find phase and magnitude of the input impedance of the ideal capacitor depicted in Fig. 3.5. Solution 3.2 The input impedance of the capacitor in the frequency domain is calculated as Z C ðωÞ =

V in ðωÞ 1 1 = = -j jωC ωC I in ðωÞ

Input impedance of the capacitor given in Eq. (3.6) can be expressed as

ð3:6Þ

38

3

Passive Circuit Elements and Their Analysis

Vin

Fig. 3.6 An ideal grounded inductor

Iin L

ZL Z C ðωÞ = jZ C ðωÞjej∠Z C ðωÞ

ð3:7Þ

where ∠ZC(ω) is defined as phase and |ZC(ω)| is defined as magnitude of the input impedance of the capacitor. Further, they are, respectively, computed as ∠Z C ðωÞ = - 90o j Z C ð ωÞ j =

1 ωC

ð3:8aÞ ð3:8bÞ

Example 3.3 Find phase and magnitude of the input impedance of the ideal inductor exhibited in Fig. 3.6. Solution 3.3 The input impedance of the inductor in the frequency domain is found as Z L ð ωÞ =

V in ðωÞ = jωL I in ðωÞ

ð3:9Þ

Similarly, input impedance of the inductor given in Eq. (3.9) can be expressed as Z L ðωÞ = jZ L ðωÞjej∠Z L ðωÞ

ð3:10Þ

where ∠ZL(ω) is defined as phase and |ZL(ω)| is defined as magnitude of the input impedance of the inductor. Moreover, they are, respectively, evaluated below. ∠Z L ðωÞ = 90o

ð3:11aÞ

jZ L ðωÞj = ωL

ð3:11bÞ

Phases and magnitudes of impedances of the ideal grounded resistor in Fig. 3.4, the ideal grounded capacitor in Fig. 3.5, and the ideal grounded inductor in Fig. 3.6 are simulated through the SPICE program. In all the simulations, R = 1 kΩ, C = 10 pF, and L = 100 μH are chosen. Additionally, the frequency in all the AC simulations is taken from 1 kHz to 1 GHz. Their AC simulation results are, respectively, shown in Figs. 3.7, 3.8, and 3.9 for the ideal grounded resistor in Fig. 3.4, the ideal grounded capacitor in Fig. 3.5, and the ideal grounded inductor in

3.2

Passive Circuits

39

Fig. 3.7 Phase and magnitude of the impedance of the resistor exhibited in Fig. 3.4

Fig. 3.8 Phase and magnitude of the impedance of the capacitor depicted in Fig. 3.5

Fig. 3.6, respectively. Time domain simulation results are, respectively, given in Figs. 3.10, 3.11, and 3.12 in which a sinusoidal peak input current signal with peak 50 μA at 1 MHz is separately applied to each of the ideal grounded resistor in Fig. 3.4, the ideal grounded capacitor in Fig. 3.5, and the ideal grounded inductor in Fig. 3.6.

40

3

Passive Circuit Elements and Their Analysis

Fig. 3.9 Phase and magnitude of the impedance of the inductor shown in Fig. 3.6

Fig. 3.10 Input current of the resistor in Fig. 3.4 and the corresponding output voltage

The ideal floating resistor, the ideal floating capacitor, and the ideal floating inductor are demonstrated in Figs. 3.13, 3.14, and 3.15, respectively. The ideal floating resistor, the ideal floating capacitor, and the ideal floating inductor in s domain are, respectively, expressed with the following matrix equations:

3.2

Passive Circuits

41

Fig. 3.11 Input current of the capacitor in Fig. 3.5 and the corresponding output voltage

Fig. 3.12 Input current of the inductor in Fig. 3.6 and the corresponding output voltage Fig. 3.13 An ideal floating resistor

I1 +

V_ 1

R

I2 +

V_ 2

42

3

Passive Circuit Elements and Their Analysis

Fig. 3.14 An ideal floating capacitor

I1

C

I2

+

+

V_ 2

V_1

Fig. 3.15 An ideal floating inductor

I1

L

I2

+

+

V1

V_ 2

_

1 -1

-1 1

V1 V2

ð3:12aÞ

I1 1 = sC I2 -1

-1 1

V1 V2

ð3:12bÞ

1 -1

-1 1

V1 V2

ð3:12cÞ

I1 1 = R I2

I1 1 = sL I2

Example 3.4 Find equivalent impedance (Zeq) of n impedances all in series. Solution 3.4 Zeq can be evaluated as n

Z eq =

ð3:13Þ

Zi i=1

Example 3.5 Find Zeq of m impedances all in parallel. Solution 3.5 Zeq can be computed by 1 = Z eq

m i=1

1 ) Z eq = Zi

1 m i=1

ð3:14Þ 1 Zi

Example 3.6 Find equivalent admittance (Yeq) of k admittances all in parallel. Solution 3.6 Yeq can be calculated as k

Y eq =

Yi i=1

ð3:15Þ

3.2

Passive Circuits

43

Example 3.7 Find Yeq of n admittances all in series. Solution 3.7 Yeq can be calculated below. 1 = Y eq

n

1 ) Y eq = Yi

i=1

1 n i=1

ð3:16Þ 1 Yi

In general, any impedances in the frequency domain can be defined as in the following: m

V ðωÞ ZðωÞ = in = I in ðωÞ

k=0 n i=0

ak ðjωÞk bi ðjωÞi

=

AR ðωÞ þ jAI ðωÞ BR ðωÞ þ jBI ðωÞ

ð3:17Þ

= jZðωÞjej∠ZðωÞ Here, AR(ω), AI(ω), BR(ω), and BI(ω) are function of real numbers. 180° ≤ ∠Z(ω) ≤ 180° is phase and |Z(ω)| is magnitude. They are, respectively, evaluated below. ∠Z ðωÞ = tan - 1

A I ð ωÞ B ð ωÞ - tan - 1 I AR ðωÞ B R ð ωÞ A2R ðωÞ þ A2I ðωÞ B2R ðωÞ þ B2I ðωÞ

jZ ðωÞj =

ð3:18aÞ ð3:18bÞ

From equation given in (3.17), the corresponding admittance can be expressed as Y ðω Þ =

I in ðωÞ 1 = V in ðωÞ Z ðωÞ

ð3:19Þ

Impedance and admittance selection suitable for integrated circuit (IC) fabrications is given in Table 3.2 in which only resistor and capacitor are considered. Table 3.2 Impedance and admittance selection suitable for IC processes

Z R 1/(sC) R/(1 + sCR) 1/(sC) + R 1 0

Y 1/R sC sC + 1/R sC/(1 + sCR) 0 1

Condition Resistor Capacitor Parallel resistor and capacitor Series resistor and capacitor Open circuit Short circuit

44

3

Passive Circuit Elements and Their Analysis

Any impedances and the corresponding admittances in s domain can be generally expressed below. m

V ðsÞ Z ðsÞ = in = I in ðsÞ

ai s i

i=0 n

bj s j

j=0

n

I ðsÞ 1 Y ðsÞ = = in = Z ðsÞ V in ðsÞ

j=0 m i=0

m

a = m bn

i=1 n j=1

bj sj ai si

ðs - zi Þ

n

b = n am

ð3:20aÞ

s - pj

j=1 m i=1

=

s - zj

=

s - pi

ð3:20bÞ

where ai (i = 1, 2, . . ., m) and bj ( j = 1, 2, . . ., n) are real numbers. zi and z/j refer to zeroes, and pj and p/i are poles. Also, they have the following relations: =

ð3:21aÞ

=

ð3:21bÞ

zj = pj ðj = 1, 2, 3, . . . , nÞ pi = zi ði = 1, 2, 3, . . . , mÞ

Note Real parts of all the poles and zeroes in Eq. (3.20) must be in the left half s plane for the stability [3]. Example 3.8 Find phase and magnitude of the impedance given below, where a, b, c, and d are all real numbers. Z in ðωÞ =

V in ðωÞ a þ jb = c þ jd I in ðωÞ

ð3:22Þ

Solution 3.8 Phase and magnitude of the impedance given in Eq. (3.22) are, respectively, found as follows: ∠Z in ðωÞ = Arc tan jZ in ðωÞj =

b d - Arc tan a c

V in ðωÞ = I in ðωÞ

a2 þ b 2 c2 þ d 2

ð3:23aÞ ð3:23bÞ

Example 3.9 Find phase and magnitude of the impedance of the RLC circuit in the frequency domain, which is demonstrated in Fig. 3.16. Solution 3.9 Impedance of the structure in Fig. 3.16 in the frequency domain can be computed as

3.2

Passive Circuits

45

Vin

Fig. 3.16 An RLC circuit

Iin L

Zin R

Z in ðωÞ = jωL þ R==

C

1 jωC

R 1 þ jωCR Rð1 - jωCRÞ = jωL þ 1 þ ω2 C 2 R2 R CR2 = þ jωðL Þ 1 þ ω2 C2 R2 1 þ ω2 C 2 R2 = jZ in ðωÞjej∠Z in ðωÞ

= jωL þ

ð3:24Þ

From equation given in (3.24), ∠Zin(ω) and |Zin(ω)| are, respectively, calculated below.

∠Z in ðωÞ = Arctan

jZ in ðωÞj =

R 1 þ ω2 C2 R2

CR2 1þω2 C 2 R2 R 1þω2 C 2 R2

ω L-

2

þ ω2 L -

CR2 1 þ ω2 C 2 R2

ð3:25aÞ 2

ð3:25bÞ

Example 3.10 Find the input impedance of the circuit in s domain, which is depicted in Fig. 3.17. Solution 3.10 Input impedance of the structure exhibited in Fig. 3.17 is evaluated below. Z in ðsÞ = R1 þ

1 1 þ sL1 þ 1 1 sC 1 þ sC 2 þ sL2 R2

ð3:26Þ

46

3

Passive Circuit Elements and Their Analysis

Vin

Fig. 3.17 A passive configuration

Iin R1 C1

Zin

L1

R2

3.3

C2

L2

RC and RL Circuits

RC circuit consisting of only one capacitor, resistor(s), and independent source (s) with no inductor is called as first-order topology. Also, RL circuit composed of only one inductor, resistor(s), and independent source(s) with no capacitor is called as first-order structure. As state variables, the capacitors possess voltages across their terminals, while the inductors have currents in them. These voltages and currents are considered as initial conditions for the capacitors and inductors, respectively. On the other hand, voltages/currents of the resistors can change abruptly. First-order RC and RL circuits for t ≥ 0 can be defined by τ

df ðt Þ þ f ðt Þ = K × input dt

ð3:27Þ

where K and the input are constants. f(t) can be capacitor current/voltage, inductor current/voltage, and resistor current/voltage. Also, τ is time constant and can be, respectively, defined for the capacitor and inductor as RC and L/R. From equation denoted in (3.27), f(t) is found as f ðt Þ = A þ Be - τ t

ð3:28Þ

where A and B are real numbers. From equation given in (3.28), A and B are, respectively, computed as follows: f ð 0Þ = A þ B ) B = f ð 0Þ - A

ð3:29aÞ

f ð 1Þ = A

ð3:29bÞ

Hence, from equations in (3.28) and (3.29), f(t) for t ≥ 0 can be rewritten as given below.

3.3 RC and RL Circuits

47

+ vR(t) - iC(t)

Fig. 3.18 A simple circuit containing one capacitor, one resistor, and one independent voltage source

R

Viu(t) +-

C

+ vC(t)

-

R

Fig. 3.19 Calculation of Req

Req=R

f ðt Þ = f ð1Þ þ ðf ð0Þ - f ð1ÞÞe - τ t

ð3:30Þ

Example 3.11 Find vC(t), vR(t), and iC(t) in the simple topology of Fig. 3.18, where Vi is constant positive voltage value and vC(0-) = 0 V. Solution 3.11 For the structure in Fig. 3.18, at time t = 0+, the capacitor is short circuit and the current passing through the capacitor is Vi/R. At time t = 1, the capacitor is open circuit and vC(1) = Vi. vC(t), vR(t), and iC(t) for t ≥ 0 are, respectively, evaluated below. vC ðt Þ = vC ð1Þ þ ðvC ð0Þ - vC ð1ÞÞe - τ = V i 1 - e - τ t

t

ð3:31aÞ

vR ð t Þ = V i - vC ð t Þ = V i - V i 1 - e - τ = V i e - τ t

i C ðt Þ = C

t dvC ðt Þ V = i e-τ Req dt

t

ð3:31bÞ ð3:31cÞ

Here, τ = ReqC. Req is calculated as follows: Independent voltage source is shortcircuited. Capacitor is taken, and it is looked at from the taken capacitor as seen from Fig. 3.19. The seen resistor is Req. In Example 3.11, Req = R. In Fig. 3.20, time domain simulation results for the circuit in Fig. 3.18 is demonstrated in which R = 1 kΩ, C = 50 pF, and Vi = 1 V are chosen. Also, τ is found as 50 ns. Example 3.12 For the topology of Fig. 3.21, find the current passing through the capacitor, iC(t) in which vC(0-) = 0 V, Vi is constant voltage value, and Ii is constant current value. Solution 3.12 Req is found such that the independent input voltage source is shortcircuited, while the independent input current source is open-circuited. Capacitor is taken, and it is looked at from the taken capacitor as seen from Fig. 3.22. Therefore,

48

3 Passive Circuit Elements and Their Analysis

Fig. 3.20 Time domain capacitor current, capacitor voltage, and applied input voltage Fig. 3.21 A structure including one capacitor, two resistors, one independent voltage source, and one independent current source

Fig. 3.22 Evaluation of Req

R1 R2

Viu(t) +-

Iiu(t)

iC(t) C

R1 R2 Req=R1//R2

the seen resistor is Req = R1//R2. In the circuit of Fig. 3.21, iC(0) = Ii + Vi/R1 and iC(1) = 0. Therefore, iC(t) is computed as iC ðt Þ = iC ð1Þ þ ðiC ð0Þ - iC ð1ÞÞe - τ t V = Ii þ i e - τ R1 t

ð3:32Þ

3.3 RC and RL Circuits

49

Fig. 3.23 Time domain capacitor current, applied input current, and applied input voltage of the circuit given in Fig. 3.21 Fig. 3.24 A circuit using one voltage source, two resistors, and one capacitor

R1

vin(t) +-

+ vC(t) C

R2

+ vo(t)

-

Here, τ = ReqC. In Fig. 3.23, the time domain simulation results for the circuit in Fig. 3.21 are given, where R1 = 2 kΩ, R2 = 3 kΩ, C = 10 pF, Vi = 2 V, and Ii = 100 μA are taken. Therefore, Req = 1.2 kΩ and τ = 12 ns are found. Example 3.13 Find vC(t) and vo(t) of the circuit in Fig. 3.24 in which C = 50 pF, R1 = 1 kΩ, and R2 = 2 kΩ are chosen. Also, vC(0-) = 2 V is taken and applied piecewise constant input voltage, and vin(t) is exhibited in Fig. 3.25. Solution 3.13 For the circuit in Fig. 3.24, Req = R1 + R2 = 3 kΩ yielding τ = ReqC = 150 ns. There are two conditions for the circuit in Fig. 3.24. (i) The first condition, 0 ≤ t < 300 ns resulting in vC(0) = 2 V and vC(1) = 5 V. Hence, vC(t) is found below.

50

3

Passive Circuit Elements and Their Analysis

vin(t), V

Fig. 3.25 Applied piecewise input voltage

5 300

t, ns

-5

vC ðt Þ = vC ð1Þ þ ðvC ð0Þ - vC ð1ÞÞe - τ t = 5 - 3e - τ t

ð3:33Þ

From equation given in (3.33), vC(300- ns) is evaluated as vC ð300 - nsÞ = 5 - 3e - 2 ffi 4:594 V

ð3:34Þ

(ii) The second condition, t ≥ 300 ns resulting in vC(300 ns) ffi 4.954 V and vC(1) = -5 V. Thus, vC(t) is evaluated as follows: vC ðt Þ = vC ð1Þ þ ðvC ð300 nsÞ - vC ð1ÞÞe ffi - 5 þ 9:954e -

t - 300 ns τ

t - 300 ns 150 ns

ð3:35Þ

(i) The first condition, 0 ≤ t < 300 ns yielding vo(0) = (5 - 2) × 2/3 = 2 V and vo(1) = 0 V. In this case, vo(t) is calculated as in the following: vo ðt Þ = vo ð1Þ þ ðvo ð0Þ - vo ð1ÞÞe - τ t = 2e - 150 ns t

ð3:36Þ

Here, vo(300- ns) is computed as 0.27 V. However, vo(300+ ns) is independent from one in (3.36) and computed as vo ð300þ nsÞ = ð- 5 - 4:594Þ ×

2 ffi - 6:396 V 3

ð3:37Þ

(ii) The second condition, t ≥ 300 ns yielding vo(300+ ns) ffi -6.396 V and vo(1) = 0 V. As a result, vo(t) can be evaluated by vo ðt Þ = vo ð1Þ þ ðvo ð300 nsÞ - vo ð1ÞÞe = - 6:396e -

t - 300 ns 150 ns

t - 300 ns τ

ð3:38Þ

In Fig. 3.26, the time domain analysis results for the circuit of Fig. 3.24 are shown.

3.3 RC and RL Circuits

51

Fig. 3.26 Time domain simulation results for the topology of Fig. 3.24

R1

Fig. 3.27 A circuit employing one voltage source, two resistors, one capacitor, and one switch

+

Viu(t) -

R2 t=t0

+ C

vC(t)

-

Example 3.14 Find the capacitor voltage, vC(t) given in Fig. 3.27, where t0 = 40 ns, C = 10 pF, R1 = 2 kΩ, R2 = 3 kΩ, vC(0-) = 1 V, and Vi = 2.5 V are selected. Solution 3.14 There are two cases for the circuit in Fig. 3.27. (i) The first case, for 0 ≤ t < 40 ns, vC(0) = 1 V, vC(1) = 2.5 V, and Req = R1 = 2 kΩ. Consequently, τ1 = ReqC = 20 ns, and vC(t) is found below. vC ðt Þ = vC ð1Þ þ ðvC ð0Þ - vC ð1ÞÞe - τ t

= 2:5 - 1:5e - 20 ns t

From equation given in (3.39), vC(40- ns) is found as follows:

ð3:39Þ

52

3

Passive Circuit Elements and Their Analysis

Fig. 3.28 Time domain simulation results for the circuit in Fig. 3.27

vC ð40 - nsÞ = vC ð1Þ þ ðvC ð0Þ - vC ð1ÞÞe - τ t

= 2:5 - 1:5e - 2 ffi 2:297 V

ð3:40Þ

(ii) The second case, for t ≥ 40 ns, vC(40+ ns) = vC(40- ns) ffi 2.297 V, vC(1) = 1.5 V, and Req = R1//R2 = 1.2 kΩ. Therefore, τ2 = ReqC = 12 ns is obtained, and vC(t) is calculated by vC ðt Þ = vC ð1Þ þ ðvC ð40þ nsÞ - vC ð1ÞÞe = 1:5 þ ð2:297 - 1:5Þe = 1:5 þ 0:797e

t - 40 ns 12 ns

t - 40 ns 12 ns

ð3:41Þ

- t -1240nsns

The time domain simulation results for the circuit of Fig. 3.27 are depicted in Fig. 3.28. Example 3.15 Find the voltage across the capacitor, vC(t) in terms of the applied input current, iin(t) for the circuit of Fig. 3.29. Solution 3.15 vC(t) via iin(t) is found as dv ðt Þ 1 iC ðt Þ = iin ðt Þ = C C ) vC ðt Þ = dt C Equation (3.42) for t > 0 can be expressed by

t

iin ðτÞdτ -1

ð3:42Þ

3.3 RC and RL Circuits

53

Fig. 3.29 A circuit composed of one current source and one capacitor

iin(t)

C

+ vC(t)

-

Fig. 3.30 The time domain simulation results for the topology in Fig. 3.29

t

1 vC ðt Þ = vC ð0Þ þ C

iin ðτÞdτ

ð3:43Þ

0

The time domain simulation results for the topology in Fig. 3.29 are exhibited in Fig. 3.30 in which C = 25 pF and iin(t) = 100(μA)u(t) are taken. Note In the time domain simulation results for the topology in Fig. 3.29, a very large-valued parallel resistor is connected to the capacitor in the SPICE simulation. Example 3.16 A capacitor has a constant DC voltage across its two terminals, Vi. If its two terminals are short-circuited at t = 0, find its current. Solution 3.16 The voltage across the two terminals of the capacitor is given by vC ðt Þ = V i uð- t Þ Therefore, the current is evaluated as

ð3:44Þ

54

3

Passive Circuit Elements and Their Analysis

iL(t)

Fig. 3.31 A topology made up of an input current source, one resistor, and one inductor

iR(t)

Iiu(t)

Fig. 3.32 Computation of Req for the structure of Fig. 3.31

R

L

R Req=R

duð- t Þ dvC ðt Þ = CV i dt dt = - CV i δð - t Þ = - CV i δðt Þ

i C ðt Þ = C

ð3:45Þ

Example 3.17 Find the currents, iL(t) and iR(t) in Fig. 3.31, where Ii is a constant DC current and iL(0-) = 0 A. Solution 3.17 At time t = 0+, inductor behaves like an open circuit, i.e., iL(0+) = iL(0-) = 0 A. At time t = 1, inductor behaves like a short circuit; thus, iL(1) = Ii is obtained. In RL circuits, it is known that τ = L/Req. Req is evaluated as follows: Inductor is taken, the independent voltage source is short-circuited, and the independent current source is open-circuited. It is looked at from the taken inductor such that equivalent resistor is Req. For the circuit in Fig. 3.31, evaluation of Req is depicted in Fig. 3.32. iL(t) and iR(t) for t ≥ 0 are, respectively, found as iL ðt Þ = iL ð1Þ þ ðiL ð0Þ - iL ð1ÞÞe - τ t

= Ii 1 - e - τ t

i R ðt Þ = I i - i L ðt Þ = Iie - τ t

ð3:46aÞ ð3:46bÞ

The topology given in Fig. 3.31 is simulated through the SPICE program in which Ii = 100 μA, R = 1 kΩ, and L = 100 μH are selected. As a result, τ = 100 ns is found, and the time domain simulation results for the topology in Fig. 3.31 are demonstrated in Fig. 3.33.

3.3 RC and RL Circuits

55

Fig. 3.33 The time domain simulation results for the topology in Fig. 3.31

iL(t)

Fig. 3.34 A circuit with one voltage source and one inductor

vin(t) +-

L

Example 3.18 Find the inductor current, iL(t) in terms of vin(t) in Fig. 3.34. Solution 3.18 The inductor current, iL(t) in terms of vin(t) can be computed as di ðt Þ 1 vL ðt Þ = vin ðt Þ = L L ) iL ðt Þ = dt L

t

vin ðτÞdτ

ð3:47Þ

-1

From equation given in (3.47), iL(t) for t > 0 can be expressed by t

1 iL ðt Þ = iL ð0Þ þ L

vin ðτÞdτ 0

ð3:48Þ

56

3

Passive Circuit Elements and Their Analysis

Fig. 3.35 Time domain simulation results for the circuit given in Fig. 3.34

The simulation results for the topology in Fig. 3.34 are given in Fig. 3.35, where L = 50 μH and vin(t) = u(t) are taken. Note In the time domain simulation results for the topology in Fig. 3.34, a very small-valued series resistor is connected to the inductor in the SPICE simulation. Any RL or RC circuit in general form can be defined as [4, 5] Z = R þ jX

ð3:49Þ

Here, R is real part of the impedance, while X is imaginary part of the impedance. Also, R and X are real numbers. Therefore, quality factor (Q) of this first-order circuit can be expressed as follows: Q=

X R

ð3:50Þ

Example 3.19 Find impedance, phase, Q, and operating frequency of the series RL circuit depicted in Fig. 3.36. Solution 3.19 The impedance of this series RL topology in s domain is given below. Z s = r s þ sLs

ð3:51Þ

From equation denoted in (3.51), the impedance of the series RL circuit in the frequency domain is expressed by

3.3 RC and RL Circuits

57

Fig. 3.36 A series RL topology

Ls rs

Zs Fig. 3.37 A parallel RL topology

Lp

Rp

Zp Z s ðωÞ = r s þ jωLs

ð3:52Þ

where R = rs and X = ωLs. Then, Qs is evaluated below. Qs =

ωLs ωLs = rs rs

ð3:53Þ

If Qs ≥ 10 is chosen, the effect of rs can be ignored. Further, the circuit in Fig. 3.36 behaves like a lossless inductor at sufficiently high frequencies. In this case, operating frequency range can be found as in the following: Qs =

2πfLs ωLs 10 r s ≥ 10 ) ≥ 10 ) f ≥ × rs rs 2π Ls

ð3:54Þ

Phase and magnitude of the structure in Fig. 3.36 are, respectively, evaluated as ωLs rs

ð3:55aÞ

r 2s þ ω2 L2s

ð3:55bÞ

∠Z s ðωÞ = Arctan j Z s ð ωÞ j =

Example 3.20 Find impedance, phase, Q, and operating frequency of the parallel RL circuit given in Fig. 3.37. Solution 3.20 The impedance of this parallel RL circuit in s domain can be computed by

58

3

Passive Circuit Elements and Their Analysis

Z p = Rp == sLp sLp Rp = sLp þ Rp

ð3:56Þ

Equation of (3.56) in the frequency domain can be expressed as follows: jωLp Rp jωLp þ Rp

Z p ð ωÞ = =

ð3:57Þ

ω2 L2p Rp þ jωLp R2p ω2 L2p þ R2p

From equation given in (3.57), R and X are, respectively, found as R= X=

ω2 L2p Rp

ð3:58aÞ

ω2 L2p þ R2p ωLp R2p

ð3:58bÞ

ω2 L2p þ R2p

Hence, Qp is calculated below.

Qp =

X = R

ωLp R2p ω2 L2p þR2p ω2 L2p Rp ω2 L2p þR2p

=

Rp ωLp

ð3:59Þ

If Qp ≥ 10 is taken, the effect of Rp can be ignored. Hence, the parallel RL circuit of Fig. 3.37 can operate like a lossless inductor at sufficiently low frequencies. In this situation, the operating frequency range is calculated as Qp =

Rp Rp Rp 1 ≥ 10 ) ≥ 10 ) f ≤ 0:1 × × 2π Lp ωLp 2πfLp

ð3:60Þ

Phase and magnitude of the impedance of the circuit in Fig. 3.37 are, respectively, found by ∠Z p ðωÞ = Arctan

Z p ð ωÞ =

ω2 L2p Rp

2

Rp ωLp þ ωLp R2p

ω2 L2p þ R2p

ð3:61aÞ 2

ð3:61bÞ

3.3 RC and RL Circuits

59

Fig. 3.38 A series RC circuit

Cs rs

Zs Example 3.21 Find the impedance, phase, Q, and operating frequency of the series RC circuit exhibited in Fig. 3.38. Solution 3.21 The impedance of this circuit in s domain is computed as Zs =

1 þ rs sC s

ð3:62Þ

Equation of (3.62) in the frequency domain can be expressed as Z s ð ωÞ =

1 j þ rs = þ rs jωC s ωC s

ð3:63Þ

where R = rs and X = -1/(ωCs). In this case, Qs is found below. Qs =

1 - ωC 1 s = rs ωC s r s

ð3:64Þ

If Qs ≥ 10 is selected, the effect of rs can be ignored. Thus, this series RC topology works like a lossless capacitor at sufficiently low frequencies. In this situation, operating frequency range of this topology is found below. Qs =

1 1 1 1 ≥ 10 ) ≥ 10 ) f ≤ 0:1 × × ωCs r s 2πfC s r s 2π Cs r s

ð3:65Þ

Phase and magnitude of the series RC structure in Fig. 3.38 are, respectively, computed as ∠Z s ðωÞ = Arctan

1 - ωC s rs

jZ s ðωÞj =

= - Arctan 1 ω2 C 2s

þ r 2s

1 ωCs r s

ð3:66aÞ

ð3:66bÞ

Example 3.22 Find impedance, phase, Q, and operating frequency of the parallel RC circuit given in Fig. 3.39.

60

3

Passive Circuit Elements and Their Analysis

Solution 3.22 The impedance of this circuit in s domain is found as Zp =

Rp 1 ==Rp = sC p Rp þ 1 sCp

ð3:67Þ

The equation of (3.67) in the frequency domain can be expressed as in the following: Z p ð ωÞ = =

Rp jωC p Rp þ 1

ð3:68Þ

Rp - jωC p R2p ω2 C 2p R2p þ 1

From equation given in (3.68), R and X are, respectively, found as R= X=

Rp ω2 C 2p R2p þ 1

ð3:69aÞ

- ωC p R2p

ð3:69bÞ

ω2 C 2p R2p þ 1

Thus, Qp is evaluated by ωC R2

- ω2 C2 pR2 pþ1 X p p Qp = = ωC p Rp = Rp R 2 2 2

ð3:70Þ

ω C p Rp þ1

If Qp ≥ 10 is taken, the effect of Rp can be ignored. As a result, the parallel topology in Fig. 3.39 behaves like a lossless capacitor at sufficiently high frequencies. In this case, operating frequency range is computed below. Qp = ωCp Rp ≥ 10 ) 2πfC p Rp ≥ 10 ) f ≥

10 1 × 2π Cp Rp

ð3:71Þ

Fig. 3.39 A parallel RC circuit

Cp

Zp

Rp

3.4 RLC Circuits

61

Phase and magnitude of the parallel RC structure in Fig. 3.39 can be, respectively, found by

∠Z p ðωÞ = Arctan

Z p ð ωÞ =

3.4

- ωCp R2p ω2 C 2p R2p þ1 Rp ω2 C 2p R2p þ1

R2p þ ωC p R2p ω2 C 2p R2p

þ1

ð3:72aÞ

= - Arctan ωC p Rp

2

=

Rp

ð3:72bÞ

1 þ ω2 C 2p R2p

RLC Circuits

RLC circuits have at least one resistor and two energy storage elements, i.e., one capacitor and one inductor. If this circuit has no resistor, it is called as lossless. Example 3.23 Analyze the parallel RLC circuit in Fig. 3.40. Solution 3.23 Applying KCL, the following equation for the parallel RLC topology depicted in Fig. 3.40 is obtained: iin ðt Þ = iC ðt Þ þ iL ðt Þ þ iR ðt Þ

ð3:73Þ

Here, iin(t), iC(t), iL(t), and iR(t) are applied input current, capacitor current, inductor current, and resistor current, respectively. Also, v(t) in Fig. 3.40 is a capacitor voltage. On the other hand, inductor voltage of the circuit of Fig. 3.40 can be expressed as vð t Þ = L

diL ðt Þ dt

ð3:74Þ

The capacitor current and resistor current in terms of v(t) can be found below.

v(t)

Fig. 3.40 A parallel RLC circuit

iin(t)

C

L

iL(t)

R

62

3

i C ðt Þ = C iR ðt Þ =

Passive Circuit Elements and Their Analysis

dvðt Þ d 2 i ðt Þ = CL L2 dt dt

ð3:75aÞ

vðt Þ L diL ðt Þ = R R dt

ð3:75bÞ

If equations denoted in (3.75) are replaced into Equation (3.73), the following second-order differential equation is obtained: iin ðt Þ = iL ðt Þ þ

d 2 i ðt Þ L diL ðt Þ þ CL L2 R dt dt

ð3:76Þ

Rearranging the equation in (3.76), the following equation is obtained: d2 iL ðtÞ 1 1 1 diL ðtÞ þ iin ðtÞ = þ i ðtÞ CL CL L CR dt dt 2

ð3:77Þ

The equation of (3.77) simplifies as ω20 iin ðt Þ =

d2 iL ðt Þ ω0 diL ðt Þ þ ω20 iL ðt Þ þ Q dt dt 2

ð3:78Þ

where ω0 and Q are, respectively, found by ω0 = Q=R

1 LC

ð3:79aÞ

C L

ð3:79bÞ

The characteristic expression of the differential equation given in (3.78) can be evaluated as below. m2 þ

ω0 m þ ω20 = 0 Q

ð3:80Þ

Thus, homogeneous solution of the second-order differential equation indicated in (3.78) can be calculated by using the roots. m1,2 = -

ω0 ± 2Q

ω20 - ω20 4Q2

ð3:81Þ

One observes from equation in (3.81) that there are three cases that are explained as follows:

3.4 RLC Circuits

63

(i) m1 and m2 are real and distinct.

m1 = -

ω0 2Q

ω20 - ω20 4Q2

ð3:82aÞ

m2 = -

ω0 þ 2Q

ω20 - ω20 4Q2

ð3:82bÞ

In this case, the overdamped condition is met as given below. ω20 1 - ω20 > 0 ) Q < 2 2 4Q

ð3:83Þ

(ii) m1 and m2 are real and equal. m1 = m2 = -

ω0 2Q

ð3:84Þ

In this case, the critically damped condition is met as follows: ω20 1 - ω20 = 0 ) Q = 2 2 4Q

ð3:85Þ

(iii) m1 and m2 are complex conjugate.

m1 = -

ω2 ω0 - j ω20 - 02 2Q 4Q

ð3:86aÞ

m2 = -

ω2 ω0 þ j ω20 - 02 2Q 4Q

ð3:86bÞ

In this case, the underdamped condition is met as in the following: ω20 1 - ω20 < 0 ) Q > 2 4Q2

ð3:87Þ

On the other hand, a particular solution depends on the form of the applied input, iin(t). After specifying form of iin(t) such as δ(t), u(t), r(t), exponential function, sinusoidal function, etc., the particular solution can be obtained. Then, a complete response for the parallel RLC circuit in Fig. 3.40 can be found by adding homogeneous and particular solutions.

64

3

Passive Circuit Elements and Their Analysis

Fig. 3.41 A series RLC circuit

i(t)

R +

vin(t) -

+ vR(t)

_

L +

vL(t)

_

C

+

v_C(t)

Note Initial conditions of the capacitor and inductor are considered in the complete response. Example 3.24 Analyze the series RLC circuit in Fig. 3.41. Solution 3.24 Applying KVL, the following equation for the series RLC structure depicted in Fig. 3.41 is obtained: vin ðt Þ = vR ðt Þ þ vL ðt Þ þ vC ðt Þ

ð3:88Þ

where vin(t), vR(t), vL(t), and vC(t) exhibit applied input voltage, resistor voltage, inductor voltage, and capacitor voltage, respectively. Further, i(t) in Fig. 3.41 is a capacitor current. Apart from these, the capacitor current of the circuit of Fig. 3.41 can be given by i ðt Þ = C

dvC ðt Þ dt

ð3:89Þ

The inductor voltage and resistor voltage in terms of i(t) can be found below. vL ð t Þ = L

diðt Þ d 2 vC ð t Þ = CL dt dt 2

vR ðt Þ = Riðt Þ = CR

dvC ðt Þ dt

ð3:90aÞ ð3:90bÞ

If equations in (3.90) are replaced into Eq. (3.88), the following second-order differential equation is obtained: vin ðt Þ = CR

d 2 vC ð t Þ dvC ðt Þ þ CL þ vC ð t Þ dt dt 2

ð3:91Þ

Rearranging the equation in (3.91), the following equation is obtained: d 2 vC ðt Þ R dvC ðt Þ 1 1 þ þ vin ðt Þ = vC ð t Þ 2 dt L CL CL dt The equation given in (3.92) simplifies as

ð3:92Þ

3.4 RLC Circuits

65

Fig. 3.42 A series LC circuit

Ls Cs

Zs ω20 vin ðt Þ =

d2 vC ðt Þ ω0 dvC ðt Þ þ ω20 vC ðt Þ þ Q dt dt 2

ð3:93Þ

where ω0 and Q are, respectively, found as ω0 = Q=

1 R

1 LC

ð3:94aÞ

L C

ð3:94bÞ

The similar calculations can be performed for the series RLC circuit, which is made for the parallel RLC topology. On the other hand, any second-order series RLC circuit can be defined as given below. Z=

s2 þ s ωQ0 þ ω20 að s Þ

ð3:95Þ

From equation given in (3.95), BW based on ω0 and Q is evaluated as follows: BW =

ω0 Q

ð3:96Þ

Example 3.25 Find phase and impedance of the series LC circuit in Fig. 3.42. Solution 3.25 The series LC circuit demonstrated in Fig. 3.42 has the following impedance:

Z s = sLs þ

s × sLs þ sC1 s 1 = sC s s×1

From equation given in (3.97), Zs simplifies as given below.

ð3:97Þ

66

3

Zs =

Passive Circuit Elements and Their Analysis

s2 Ls þ C1s ÷ Ls

=

s ÷ Ls

s2 þ Ls1Cs s Ls

ð3:98Þ

From equation in (3.98), ω0 and Q are, respectively, found as ω0 =

1 Ls C s

ð3:99aÞ

Q=1

ð3:99bÞ

Impedance of the series LC circuit demonstrated in Fig. 3.42 in the frequency domain can be found as follows: Z s ðωÞ =

- ω2

1 Ls C s

jω Ls

ð3:100Þ

Phase and magnitude of the impedance of the topology in Fig. 3.42 for 1/(√(LsCs)) ≥ ω > 0 are, respectively, evaluated as ∠Z s ðωÞ = - 90 ° jZ s ðωÞj =

1 Ls C s

- ω2 ω Ls

ð3:101aÞ ð3:101bÞ

Phase and magnitude of the impedance of the circuit in Fig. 3.42 for ω > 1/ (√(LsCs)) are, respectively, computed by ∠Z s ðωÞ = 90 ° jZ s ðωÞj =

ω2 ω Ls

1 Ls C s

ð3:102aÞ ð3:102bÞ

Phase and magnitude of the impedance of the circuit given in Fig. 3.42 are exhibited in Fig. 3.43, where Ls = 100 μH and Cs = 100 pF yielding f0 ffi 1.59 MHz are taken. Additionally, simulations are performed through the SPICE program. One observes from Fig. 3.43 that the phase response varies from -90° to 90° as the frequency changes from zero to infinity. Example 3.26 Find phase and impedance of the parallel LC circuit in Fig. 3.44. Solution 3.26 Impedance of the parallel LC circuit demonstrated in Fig. 3.44 is evaluated below.

3.4 RLC Circuits

67

Fig. 3.43 Phase and magnitude of the impedance of the circuit given in Fig. 3.42 Fig. 3.44 A parallel LC topology Cp

Lp

Zp

s × sLp × sC1 p sLp × sC1 p 1 Z p = sLp == = = sCp sLp þ sC1 s × sLp þ sC1 p p

ð3:103Þ

The equation in (3.103) simplifies as

Zp =

sLp Cp

÷ Lp

s2 Lp þ C1p ÷ Lp

=

s Cp

s2 þ Lp1Cp

ð3:104Þ

Similarly, from equation in (3.104), ω0 and Q are, respectively, found as ω0 =

1 Lp C p

Q=1

ð3:105aÞ ð3:105bÞ

68

3

Passive Circuit Elements and Their Analysis

A parallel LC circuit in Fig. 3.44 in the frequency domain has the following impedance: Z p ðωÞ =

jω Cp 1 Lp C p

- ω2

ð3:106Þ

Phase and magnitude of the parallel LC circuit in Fig. 3.44 for 1/(√(LpCp)) ≥ ω > 0, are respectively, computed as ∠Z p ðωÞ = 90 ° Z p ðωÞ =

ω Cp 1 Lp C p

- ω2

ð3:107aÞ ð3:107bÞ

Phase and magnitude of the parallel LC circuit in Fig. 3.44 for ω > 1/(√(LpCp)) are, respectively, calculated by ∠Z p ðωÞ = - 90 ° Z p ðωÞ =

ω Cp

ω2 -

1 Lp C p

ð3:108aÞ ð3:108bÞ

Phase and magnitude of the impedance of the circuit in Fig. 3.44 are exhibited in Fig. 3.45 in which L = 100 μH and C = 100 pF yielding f0 ffi 1.59 MHz are chosen. Moreover, simulations are performed via the SPICE program.

Fig. 3.45 Phase and magnitude of the impedance of the topology in Fig. 3.44

3.4 RLC Circuits

69

Fig. 3.46 A series RLC circuit

Ls rs

Zs

Cs

It is observed from Fig. 3.45 that the phase response varies from 90° to -90° as the frequency changes from zero to infinity. Example 3.27 Find impedance of the series RLC circuit in Fig. 3.46. Solution 3.27 Impedance of the series RLC circuit in Fig. 3.46 is found as follows: 1 s × sLs þ þ rs sC s 1 þ rs = Z s = sLs þ sC s s×1 1 s2 Ls þ sr s þ ÷ Ls s 2 þ s r s þ 1 Cs Ls Ls C s = = s s ÷ Ls Ls

ð3:109Þ

From equation indicated in (3.109), ω0 and ω0/Q are, respectively, computed by 1 Ls C s ω0 r = s Q Ls

ð3:110aÞ

ω0 =

ð3:110bÞ

From equations in (3.110), Q is evaluated as Q=

ω0 Ls 1 = rs rs

Ls Cs

ð3:111Þ

Impedance of the series RLC circuit in Fig. 3.46 in the frequency domain is given by Z s ð ωÞ =

jω Lrss þ Ls1Cs - ω2 jω Ls

ð3:112Þ

Phase and magnitude of the impedance of the series RLC circuit in Fig. 3.46 in the frequency domain are, respectively, calculated below.

70

3

Passive Circuit Elements and Their Analysis

Fig. 3.47 Phase and magnitude of the impedance of the circuit shown in Fig. 3.46

∠Z s ðωÞ = - 90o þ Arctan

jZ s ðωÞj =

1 Ls C s

- ω2

2

ω Lrss 1 Ls C s

- ω2

þ ω Lrss

ð3:113aÞ

2

ω Ls

ð3:113bÞ

Phase and magnitude of the impedance of the circuit in Fig. 3.46 are demonstrated in Fig. 3.47 in which rs = 1 kΩ, Ls = 100 μH, and Cs = 100 pF resulting in f0 ffi 1.59 MHz and Q = 1 are selected. Also, simulations are made via the SPICE program. One sees from Fig. 3.46 that the phase response varies from -90° to 90°as the frequency changes from zero to infinity. Example 3.28 Find impedance of the parallel RLC circuit depicted in Fig. 3.48. Solution 3.28 Impedance of the parallel RLC circuit depicted in Fig. 3.48 can be found as given below. Z p = sLp ==

1 ==Rp sC p

The impedance given in Eq. (3.114) can be easily evaluated as

ð3:114Þ

3.4 RLC Circuits

71

Fig. 3.48 A parallel RLC structure.

Cp

Rp

Lp

Zp

Zp =

1 = Yp

1 1 sLp

þ R1p þ sC p

1×

=

1 sLp

s Cp

þ R1p þ sC p ×

s Cp

ð3:115Þ

The impedance in Eq. (3.115) simplifies as Zp =

s2 þ

s Cp s Rp1Cp

þ Lp1Cp

ð3:116Þ

From the equation in (3.116), ω0 and ω0/Q are, respectively, evaluated as ω0 =

1 Lp C p

ð3:117aÞ

1 ω0 = Q Rp C p

ð3:117bÞ

Similarly, from the equations given in (3.117), Q is found below. Q = ω0 Rp C p = Rp

Cp Lp

ð3:118Þ

Substituting s = jω into (3.116), the following impedance in the frequency domain can be obtained as Z p ð ωÞ =

jω Cp

jω Rp1Cp þ Lp1Cp - ω2

ð3:119Þ

Phase and magnitude of the impedance of the circuit depicted in Fig. 3.48 are, respectively, evaluated as in the following:

72

3

Passive Circuit Elements and Their Analysis

Fig. 3.49 Phase and magnitude of the impedance of the circuit shown in Fig. 3.48

∠Z p ðωÞ = 90 ° - Arctan

ω Rp C p 1 Lp C p

ð3:120aÞ

- ω2

ω Cp

Z p ð ωÞ = 1 Lp C p

- ω2

2

þ

ω Rp C p

2

ð3:120bÞ

Phase and magnitude of the impedance of the circuit in Fig. 3.48 are demonstrated in Fig. 3.49, where Rp = 1 kΩ, Lp = 100 μH, and Cp = 100 pF yielding f0 ffi 1.59 MHz and Q = 1 are taken. Further, simulations are made through the SPICE program. It is seen from Fig. 3.49 that the phase response varies from 90° to -90° as the frequency changes from zero to infinity.

References 1. J.A. Svoboda, R.C. Dorf, Dorf’s Introduction to Electric Circuits, Global edition. (Wiley, 2018) 2. J.W. Nilsson, S. Riedel, Electric Circuits, Global edition, 11th ed. (Pearson, 2018) 3. L.O. Chua, C.A. Desoer, E.S. Kuh, Linear and Nonlinear Circuits (McGraw-Hill, 1987) 4. R.J. Cameron, C.M. Kudsia, Microwave Filters for Communication Systems, 2nd edn. (Wiley, 2018) 5. D.M. Pozar, Microwave Engineering, 3rd edn. (Wiley, 2005)

Chapter 4

Main Transfer Functions of the Circuits

4.1

Definition of the Filter Transfer Function

If the input is x(t) and the corresponding output is y(t) in a LTI system, the filter transfer function (FTF) of this system is defined as [1] m

Y ðsÞ H ðsÞ = = X ð sÞ

i=0 n j=0

ai s i ð4:1Þ bj

sj

Here, ai (i = 0, 1, 2, . . ., m) and bj ( j = 0, 1, 2, . . ., n) are real numbers. Moreover, X(s) and Y(s) represent Laplace transform of x(t) and y(t), respectively. In this section, FTFs can be divided into four categories depending on the applied input and the corresponding output whether they are current and/or voltage. These FTFs called as voltage-mode (VM), current-mode (CM), transimpedance-mode (TIM), and transadmittance-mode (TAM) are, respectively, depicted in Figs. 4.1, 4.2, 4.3, and 4.4. Apart from these, these FTFs are obtained from the various combinations of R, L, and C.

4.1.1

VM FTF

A VM FTF has ideally infinite input impedance and zero output impedance. The VM FTF in Fig. 4.1 is found as [2, 3] H V ðsÞ =

V out ðsÞ V in ðsÞ

© The Author(s), under exclusive license to Springer Nature Switzerland AG 2024 E. Yuce, S. Minaei, Passive and Active Circuits by Example, https://doi.org/10.1007/978-3-031-44966-6_4

ð4:2Þ

73

74

4

Main Transfer Functions of the Circuits

Fig. 4.1 Block diagram of a VM filter

+ V_in

Iout

Fig. 4.2 Block diagram of a CM filter

Iin

Fig. 4.3 Block diagram of a TIM filter

Iin

HI

+ Vout _

HZ

Iout

Fig. 4.4 Block diagram of a TAM filter

4.1.2

+ Vout _

HV

+ Vin _

HY

CM FTF

A CM FTF has ideally zero input impedance and infinite output impedance. The CM FTF in Fig. 4.2 is given by H I ðsÞ =

4.1.3

I out ðsÞ I in ðsÞ

ð4:3Þ

TIM FTF

A TIM FTF possesses ideally zero input and output impedances. The TIM FTF in Fig. 4.3 is expressed as follows: H Z ðsÞ =

V out ðsÞ = Rm I in ðsÞ

ð4:4Þ

4.2

First-Order VM FTFs

4.1.4

75

TAM FTF

A TAM FTF possesses ideally infinite input and output impedances. The TAM FTF in Fig. 4.4 is expressed below. H Y ðsÞ =

4.2

I out ðsÞ = Gm V in ðsÞ

ð4:5Þ

First-Order VM FTFs

Transfer functions (TFs) of the first-order VM filters can be divided into three categories, low-pass filter (LPF), high-pass filter (HPF), and all-pass filter (APF) TFs.

4.2.1

VM LPF TFs

In this subsection, VM LPF TFs based on the various combinations of R, L, and C are investigated. Example 4.1 Draw the circuit, and find the TF of a first-order VM LPF based on RC. Solution 4.1 The first-order VM LPF based on RC is demonstrated in Fig. 4.5 and has the following TF: 1 V out ðsÞ sC = H LP ðsÞ = 1 V in ðsÞ þR sC 1 1 ω0 RC = = = 1 s þ ω0 sCR þ 1 sþ RC

Fig. 4.5 A first-order VM LPF based on RC

ð4:6Þ

R

+ Vin _

+ Vout C _

76

4

Main Transfer Functions of the Circuits

where ω0 = 1/(RC) is called as angular pole frequency. Further, equation of (4.6) in the frequency domain can be written as H LP ðωÞ =

ω0 jω þ ω0

ð4:7Þ

= jH LP ðωÞjej∠H LP ðωÞ Phase and gain of the TF in Eq. (4.7) are, respectively, evaluated as ∠H LP ðωÞ = - tan - 1 jH LP ðωÞj =

ω ω0

ð4:8aÞ

ω0 ω2 þ ω20

ð4:8bÞ

Gain of the TF in Eq. (4.8b) can be written in dB as follows: 20 logjH LP ðωÞj = 20 log

ω0 ω2 þ ω20

= 20 logðω0 Þ - 20 log

ð4:9Þ

ω2 þ ω20

= 20 logðω0 Þ - 10 log ω2 þ ω20 One observes from Eq. (4.9) that if ω > ω0 is selected, the gain of the LPF decreases with slope of -20 dB/decade. Example 4.2 Draw the circuit, and find the TF of a first-order VM LPF based on RL. Solution 4.2 The first-order VM LPF based on RL is exhibited in Fig. 4.6 and has the following TF: V out ðsÞ R = sL þ R V in ðsÞ R ω0 = L = R s þ ω0 sþ L Here, ω0 = R/L is called as angular pole frequency. H LP ðsÞ =

Fig. 4.6 A first-order VM LPF based on RL

ð4:10Þ

L + V_in

+

R

Vout _

4.2

First-Order VM FTFs

77

Fig. 4.7 A first-order VM HPF based on RC

C +

V_in

4.2.2

+

R

V_out

VM HPF TFs

In this subsection, VM HPFs based on various combinations of R, C, and L are investigated. Example 4.3 Draw the circuit, and find the TF of a first-order VM HPF based on RC. Solution 4.3 The first-order VM HPF based on RC is shown in Fig. 4.7 and has the following TF: V out ðsÞ R = 1 V in ðsÞ þR sC sCR s s = = = 1 sCR þ 1 s þ ω0 sþ RC

H HP ðsÞ =

ð4:11Þ

Similarly, ω0 = 1/(RC) is found. TF given in Eq. (4.11) in the frequency domain can be expressed as H HP ðωÞ =

jω jω þ ω0

= jH HP ðωÞjej∠H HP ðωÞ

ð4:12Þ

Phase and gain of the HPF TF are, respectively, calculated as given below. ∠H HP ðωÞ = 90o - tan - 1 jH HP ðωÞj =

ω ω0

ω þ ω20

ð4:13aÞ ð4:13bÞ

ω2

Gain of the TF in Eq. (4.13b) can be written in dB as follows: 20 logjH HP ðωÞj = 20 log

ω ω2 þ ω20

= 20 logðωÞ - 20 log

ω2 þ ω20

= 20 logðωÞ - 10 log ω2 þ ω20

ð4:14Þ

78

4

Main Transfer Functions of the Circuits

Fig. 4.8 A first-order VM HPF based on RL

R +

V_in

+

L

V_out

It is seen from equation given in (4.14) that for ω > ω0, the gain is 0 dB. Example 4.4 Draw the circuit, and find the TF of a first-order VM HPF based on RL. Solution 4.4 The first-order VM HPF based on RL is given in Fig. 4.8 and has the following TF: V out ðsÞ sL = sL þ R V in ðsÞ s s = = R s þ ω0 sþ L

H LP ðsÞ =

ð4:15Þ

Likewise, ω0 = R/L.

4.2.3

VM APF TFs

VM APFs have different realizations. In the following, a floating output realization of the first-order APF is given. Example 4.5 Find the TF of the first-order VM APF given in Fig. 4.9. Solution 4.5 First-order VM APF in Fig. 4.9 for R2 = R1 can provide the following TF: H AP ðsÞ =

V out ðsÞ 1 1 = 2 1 þ sCR V in ðsÞ

s 11 1 - sCR 1 ω0 =- × =- × 2 1 þ sCR 2 1þ s ω0

ð4:16Þ

Here, ω0 = 1/(RC). From Eq. (4.16), TF in the frequency domain can be written as

4.3

First-Order CM FTFs

79

Fig. 4.9 First-order VM APF based on RC

+

V_in R

R1 + Vout

_ C

R2

H AP ðωÞ = jH AP ðωÞjej∠H AP ðωÞ

ð4:17Þ

where ∠HAP(ω) and |HAP(ω)| are, respectively, calculated as ∠H AP ðωÞ = 180o - 2 tan - 1 jω 1 1 1 - ω0 = × jH AP ðωÞj = 2 2 1 þ jω ω0

ω ω0

12 þ 1 þ 2

ð4:18aÞ 2

ω ω0

ω ω0

2

=

1 2

ð4:18bÞ

The circuit in Fig. 4.9 has inverting APF responses. On the other hand, one can change the polarity of the output in Fig. 4.9 to obtain a non-inverting first-order VM all-pass filter. Thus, gain does not change, while the phase becomes below. ∠H AP ðωÞ = - 2 tan - 1

4.3

ω ω0

ð4:19Þ

First-Order CM FTFs

Similarly, first-order CM FTFs can be obtained from various combinations of R, L, and C. Example 4.6 Find the TFs of the RC-based first-order CM filter demonstrated in Fig. 4.10. Solution 4.6 In order to analyze this RC circuit, an arbitrary auxiliary node called as Vtest is used. By applying KCL, the following equation is obtained:

80

4

Main Transfer Functions of the Circuits

Fig. 4.10 A first-order CM filter based on RC

Vtest

Iin

1 þ sC R

I in ðsÞ = V test

R

C

ILP

IHP

ð4:20Þ

Thus, Vtest can be easily evaluated as follows: V test =

R I sCR þ 1 in

ð4:21Þ

From equation in (4.21), a first-order TIM LPF TF is found as H ðsÞ =

V test R = I in sCR þ 1

ð4:22Þ

By using Eq. (4.21), low-pass current (ILP) and high-pass one (IHP) are, respectively, evaluated as I LP =

V test 1 = I R sCR þ 1 in

I HP = sCV test =

sCR I sCR þ 1 in

ð4:23aÞ ð4:23bÞ

From equations given in (4.23), the following LPF and HPF TFs are, respectively, computed by 1 I LP = sCR þ 1 I in

ð4:24aÞ

sCR I HP = I in sCR þ 1

ð4:24bÞ

The angular pole frequency of this filter is calculated as 1/(CR). Example 4.7 Find the output currents of the RL-based first-order CM filter shown in Fig. 4.11. Solution 4.7 In order to analyze this RL circuit, Vtest is used. By applying KCL, the following equation is obtained: I in = V test Therefore, Vtest can be easily evaluated by

1 1 þ R sL

ð4:25Þ

4.4

Second-Order VM FTFs

81

Fig. 4.11 A first-order CM filter based on RL

Vtest

Iin

V test =

sR I in s þ RL

L

R

ILP

IHP

ð4:26Þ

From equation indicated in (4.26), a first-order TIM HPF TF is found as H ðsÞ =

V test ðsÞ sR = I in ðsÞ s þ RL

ð4:27Þ

By using Eq. (4.26), ILP and IHP are, respectively, calculated as I LP =

R V test = L R I in sL sþL

ð4:28aÞ

I HP =

s V test I in = R s þ RL

ð4:28bÞ

The angular pole frequency of the filter is calculated as R/L.

4.4

Second-Order VM FTFs

Example 4.8 Find the output voltage of the second-order three-input single-output universal filter based on RLC depicted in Fig. 4.12. Solution 4.8 This filter is analyzed by using KCL as below. V - V2 V 1 - V out = out þ ðV out - V 3 ÞsC sL R

ð4:29Þ

Organization of the equation in (4.29), output voltage, Vout depending on the applied input voltages is evaluated as V out =

1 1 s2 V 3 þ s RC V 2 þ LC V1 1 1 2 s þ s RC þ LC

From equation given in (4.30), ω0 and Q are, respectively, computed by

ð4:30Þ

82

4

Main Transfer Functions of the Circuits

Fig. 4.12 A second-order three-input single-output universal filter based on RCL

V1 V2 V3

L

R C

1 ω0 = p LC Q=R

Vout

ð4:31aÞ

C = ω0 RC L

ð4:31bÞ

In Eq. (4.30), Vout is obtained as follows: If V2 = V3 = 0 and V1 = Vin are chosen, an LPF response is obtained. If V1 = V3 = 0 and V2 = Vin are chosen, a BPF response is obtained. If V1 = V2 = 0 and V3 = Vin are chosen, an HPF response is obtained. If V1 = V3 = Vin and V2 = -Vin are chosen, an APF response is obtained. The voltage, -Vin can be easily obtained by using a unity gain inverting amplifier. 5. If V1 = V3 = Vin and V2 = 0 are chosen, an NF response is obtained.

1. 2. 3. 4.

Note Gains of the LPF, BPF, HPF, APF, and NF in Fig. 4.12 are unity. Example 4.9 Find the output voltages Vout1 and Vout2 of the circuit shown in Fig. 4.13. Which filter responses are realized? Solution 4.9 Responses of the second-order single-input two-output filter depicted in Fig. 4.13 can be, respectively, evaluated by

V out1 =

=

1 þ sL sC sL þ R þ s2 þ

s2 þ

1 sC

1 LC

sR 1 þ L LC

V in =

V in

1 þ s2 LC V þ sCR þ 1 in

s2 LC

ð4:32aÞ

4.4

Second-Order VM FTFs

83

Fig. 4.13 A second-order single-input two-output filter

C

R

+ Vin _

C

Fig. 4.14 A second-order single-input single-output filter

L

V out2 =

sL sL þ R þ

1 sC

V in =

s2 LC

Vout2 _

L

+

+ Vin _

=

+

+ Vout1 _

R

Vout _

s2 LC V þ sCR þ 1 in ð4:32bÞ

s2 V sR 1 in s2 þ þ L LC

So, NF and HPF responses are obtained from Vout1 and Vout2, respectively. From equations denoted in (4.32), ω0 and Q are, respectively, calculated as 1 ω0 = p LC

ð4:33aÞ

1 R

ð4:33bÞ

Q=

L C

Example 4.10 Find the output voltage Vout of the circuit shown in Fig. 4.14. Which filter response is realized? Solution 4.10 Response of the second-order single-input single-output BPF shown in Fig. 4.14 can be computed as V out =

sR R V in = 2 sRL V in 1 1 sL þ R þ sC s þ L þ LC

ð4:34Þ

From equation given in (4.34), TF of the circuit is calculated as in the following: H ðsÞ =

sR V out ðsÞ = 2 sRL 1 V in ðsÞ s þ L þ LC

So, a BPF response is obtained from the output, Vout.

ð4:35Þ

84

4

Main Transfer Functions of the Circuits L

R

Fig. 4.15 A second-order single-input single-output filter

+

+

Vin _

C

Vout _

Example 4.11 Find the output voltage, Vout of the circuit shown in Fig. 4.15. Which filter response is realized? Solution 4.11 Response of the second-order single-input single-output filter shown in Fig. 4.15 can be computed as

V out =

1 sC sL þ R þ

1 sC

V in =

1 C s2 L þ sR þ

1 C

V in

1 LC = V sR 1 in s2 þ þ L LC

ð4:36Þ

From equation given in (4.36), TF of the filter is calculated as follows: H ðsÞ =

1 V out ðsÞ = 2 LC 1 V in ðsÞ s þ sR L þ LC

ð4:37Þ

So, an LPF response is obtained from the output Vout.

4.5

Second-Order CM FTFs

Example 4.12 Find the output currents of the second-order CM universal filter based on RLC demonstrated in Fig. 4.16. Solution 4.12 Vtest can be easily evaluated by using the following equation: I in = V test

1 1 þ þ sC sL R

ð4:38Þ

From equation given in (4.38), Vtest is found by V test =

s2

s C1 I 1 1 in þ s RC þ LC

ð4:39Þ

4.5

Second-Order CM FTFs

85

Vtest

Fig. 4.16 A second-order single-input three-output CM universal filter

Iin

L

R

C

ILP

IBP

IHP

Vtest

Fig. 4.17 A second-order single-input single-output CM LPF

Iin

R

L

C

Iout

LPF, BPF, and HPF currents by using Vtest are, respectively, calculated as follows: 1

I LP =

V test = LC I in sL DðsÞ

ð4:40aÞ

I BP =

s 1 V test = RC I in R DðsÞ

ð4:40bÞ

s2 I DðsÞ in

ð4:40cÞ

1 1 þ RC LC

ð4:41Þ

I HP = V test sC = Here, D(s) is given as DðsÞ = s2 þ s

By using LPF, BPF, and HPF currents, NF and APF currents can be, respectively, obtained as I NF = I LP þ I HP

ð4:42aÞ

I AP = I LP - I BP þ I HP

ð4:42bÞ

Example 4.13 Find the output current of the second-order CM LPF based on RLC exhibited in Fig. 4.17. Solution 4.13 Vtest can be easily evaluated by using the following equation: I in = V test sC þ

I ðsL þ RÞ 1 I in ) V test = = 2 in 1 sL þ R sC þ sLþR s CL þ sCR þ 1

ð4:43Þ

86

4

Main Transfer Functions of the Circuits

From equation in (4.43), TF of the LPF is computed below. H ðsÞ =

4.6

1

I out V test LC = = 1 I in I in ðsL þ RÞ s2 þ sR L þ LC

ð4:44Þ

High-Order VM BPF TF

A fourth-order single-input single-output VM BPF is demonstrated in Fig. 4.18 [4]. In this filter, Q1 = ω01R1C1, Q2 = ω02R2C2, ω01 = 1/√((L1+L3)C1), and ω02 = 1/ √((L2+L3)C2). If the passive elements are taken as C1 = C2 = 100 pF, L1 = 10.83 μH, L2 = 23.14 μH, L3 = 5 μH, R1 = 2 kΩ, and R2 = 2 kΩ then f01 ffi 4 MHz, f02 ffi 3 MHz, Q1 ffi 5.03, and Q2 ffi 3.77 are found. Simulation results for this filter are plotted in Fig. 4.19. One observes from Fig. 4.19 that phase response varies from 90° to -270° as the frequency changes from zero to infinity.

+ Vin _

L2

L1

R1 C1

L3

R2

C2

+ Vout _

Fig. 4.18 A fourth-order single-input single-output VM BPF

Fig. 4.19 Phase and gain of the fourth-order single-input single-output VM BPF in Fig. 4.18

References

87

References 1. A.V. Oppenheim, A.S. Willsky, S.H. Nawab, Signals and Systems, Pearson New International Edition. (Pearson Education Limited, Harlow, 2013) 2. A.B. Williams, Analog Filter and Circuit Design Handbook (McGraw Hill Professional, 2013) 3. R. Schaumann, M.E.V. Valkenburg, Design of Analog Filters (Oxford University Press, 2001) 4. M. Dogan, E. Yuce, S. Minaei, M. Sagbas, Synthetic transformer design using commercially available active components. Circuits Syst. Sign. Process. 39(8), 3770–3786 (2020)

Chapter 5

Operational Amplifiers and Their Applications

5.1

Practical Operational Amplifiers

Electrical symbol of the operational amplifier (OA) is depicted in Fig. 5.1. OA has three terminals, non-inverting (+ terminal), inverting (- terminal), and output ones. In addition, it has two symmetrical DC supply voltages, VEE and VCC, where VEE = -VCC [1–4]. Output voltage, Vout, of the OA is evaluated as V out = AðV þ - V - Þ

ð5:1Þ

Here, A is open loop gain of the OA. Furthermore, A is frequency-dependent and can be modeled by using a single pole model as follows: A=

A0 1 þ fjf

ð5:2Þ

b

where A0 is DC open loop gain, while fb is -3 dB frequency. A0 takes values between 104 and 106 practically. Due to high values of A0, OA-based circuits are designed by using feedback. Rated voltages are maximum/minimum voltages at the output of the OA. These voltages are always lower than supply voltages of the OA in magnitude. For example, if VCC = -VEE = 12 V are taken, rated voltages are about Vr+ = 9 V and Vr- = -9 V. In other words, Vr+ < VCC and Vr- > VEE. Moreover, Vout and output current Iout are, respectively, expressed as V r - ≤ V out ≤ V rþ

ð5:3aÞ

jI out j ≤ I out, max

ð5:3bÞ

© The Author(s), under exclusive license to Springer Nature Switzerland AG 2024 E. Yuce, S. Minaei, Passive and Active Circuits by Example, https://doi.org/10.1007/978-3-031-44966-6_5

89

90

5

Operational Amplifiers and Their Applications

Fig. 5.1 Representation of the practical OA

VCC V+

I+

+ OA

V-

-

I-

Iout

Vout

VEE Fig. 5.2 V+ - V- versus Vout characteristics

Vout

Vr+ A0

Vr-/A0

Vr+/A0

V+-V-

Vr-

where Iout,max is the maximum current that can be supplied by the OA. In Fig. 5.2, V+ - V- against Vout characteristics is given in which A0 is the slope. Example 5.1 If A = 104, Vr+ = 9 V, Vr- = -9 V, V+ = 5 V, and V- = -2 V are taken, find the value of Vout. Solution 5.1 From Eq. (5.1), Vout = A(V+ – V-), Vout = 104 × (5-(-2)) = 7 × 104 V is found. Vout cannot exceed 9 V; thus, Vout = 9 V. Example 5.2 If A = 104 Vr+ = 9 V, Vr- = -9 V, V+ = 0 V, and V- = 4 V are chosen, find the value of Vout. Solution 5.2 From Eq. (5.1), Vout = A(V+ - V-), Vout = 104 × (0 - 4) = -4 × 104 V is found. Vout cannot be less than -9 V; therefore, Vout = -9 V.

5.2

Ideal OAs

Two models for the OA can be given. These models are, respectively, given in Figs. 5.3 and 5.4. Vi and Vout in Fig. 5.3 are, respectively, calculated by Vi = Vþ - V -

ð5:4aÞ

5.2

Ideal OAs

91

Fig. 5.3 The first model for the OA

Rout

I+

V+

+ Vi

Rin V-

V+

+

-

-

AVi

Vout +

GmV-

Vout

I-

GmV+

V-

Iout

R

+ Vd

-

PVd

-

Fig. 5.4 The second model for the OA

V out = AV i þ I out Rout

ð5:4bÞ

V out = μV d = μGm RðV þ - V - Þ

ð5:5Þ

Vout in Fig. 5.4 is found as

Here, Vd = GmR(V+ - V-). An ideal OA-based model in Fig. 5.3 has the following properties: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15.

I+ = I- = 0. Rin = 1. A = 1. Rout = 0. Infinity bandwidth. No offset current. No offset voltage. Infinity slew rate (SR). Zero THD. Zero noise. Infinity dynamic range. Infinity common-mode rejection ratio. No parasitic resistors and capacitors. -1 ≤ Iout ≤ 1 -1 ≤ V+ ≤ 1, -1 ≤ V- ≤ 1, and -1 ≤ Vout ≤ 1

92

5

16. 17. 18. 19.

No restricted DC supply voltages. Infinity power supply rejection ratio. Infinity signal to noise ratio. No stability problem.

5.3

OA-Based Basic Circuits

Operational Amplifiers and Their Applications

In this section, OAs are considered as ideal (A → 1). Example 5.3 Find Vout/Vin of the inverting amplifier in Fig. 5.5. Solution 5.3 Due to infinite gain of the OA, V- = V+ = 0. Analysis of the circuit in Fig. 5.5 is performed as follows: R V in - V V - V out V = ) out = - 2 R1 R2 V in R1

ð5:6Þ

Thus, this amplifier has 180° phase difference between Vout and input voltage, Vin. Input resistance of the inverting amplifier Rin = R1 in which A → 1. Also, equivalent circuit of Fig. 5.5 is demonstrated in Fig. 5.6. Mechanical analogy of the inverting amplifier is depicted in Fig. 5.7 [5], while Vin - Vout characteristics of the inverting amplifier are depicted in Fig. 5.8. AC and transient responses of the inverting amplifier are, respectively, given in Figs. 5.9 and 5.10, where LM318/NS OA model is utilized. DC supply voltages of the OA are taken as ±12 V, while R1 = 1 kΩ and R2 = 5 kΩ are chosen. As it is seen from Fig. 5.9, -3 dB frequency (cutoff frequency) of the inverting amplifier is approximately 6.42 MHz. A

Vin

R1

R2

OA

Vout

+ Ao f Fig. 5.5 An inverting amplifier Fig. 5.6 Equivalent circuit of the inverting amplifier

Vin

Vout R1

+

-

-R2Vin /R1

5.3

OA-Based Basic Circuits

Fig. 5.7 Mechanical analogy of the inverting amplifier

93

Vin

R1

R2

Vout

Vout

–

R2 R1

Vin

Fig. 5.8 Vin - Vout characteristics of the inverting amplifier

Fig. 5.9 AC analysis result of the inverting amplifier

sinusoidal input voltage with peak 1 V at 100 kHz is applied. Thus, the results are shown in Fig. 5.10. Note As shown in Fig. 5.5, feedback is fed to – terminal of the OA. Otherwise, the inverting amplifier becomes unstable.

94

5

Operational Amplifiers and Their Applications

Fig. 5.10 Transient analysis results of the inverting amplifier Fig. 5.11 A non-inverting amplifier

+

Vin

OA

-

Vout

Ao∞ R2

R1

Example 5.4 Find Vout/Vin of the non-inverting amplifier in Fig. 5.11. Solution 5.4 Analysis of the non-inverting amplifier given in Fig. 5.11 is achieved as in the following: R V out - V in V in V = ) out = 1 þ 2 R2 R1 V in R1

ð5:7Þ

Input resistance of the non-inverting amplifier Rin → 1. In addition, equivalent circuit of Fig. 5.11 is demonstrated in Fig. 5.12. Mechanical analogy of the non-inverting amplifier is depicted in Fig. 5.13 [5], while Vin - Vout characteristics of the non-inverting amplifier are plotted in Fig. 5.14.

5.3

OA-Based Basic Circuits

95

Fig. 5.12 Equivalent representation of the non-inverting amplifier

Vin

Vout +

-

Fig. 5.13 Mechanical analogy of the non-inverting amplifier

(1+R2 /R1)Vin

R2 Vout

R1

Vin

Vout

1+

R2 R1

Vin

Fig. 5.14 Vin - Vout characteristics of the non-inverting amplifier

R2=100 k:

Fig. 5.15 Topology of Example 5.5

Vin

R1=20 k: R3=20 k:

OA + A→f R4=20 k:

Vout R5=1 k:

Example 5.5 Find Vout/Vin and input resistance of the circuit depicted in Fig. 5.15. Solution 5.5 I+ = 0 A; thus, V+ = 0 V (R4 and R5 have no effect). V- = V+; accordingly, R3 has no effect. Therefore, Vout/Vin and Rin are, respectively, found as

96

5

Operational Amplifiers and Their Applications

Fig. 5.16 Circuit of Example 5.6

R2 Iin

R3

OA

R1 +

Fig. 5.17 Simplified circuit of Example 5.6

R1+R2 R1Iin

_ +

Vout

A→f

R3

OA

Vout

+ A→f

R V out 100kΩ =- 2== -5 V in R1 20kΩ

ð5:8aÞ

Rin = R1 = 20kΩ

ð5:8bÞ

Example 5.6 Find Vout/Iin in the structure of Fig. 5.16. Solution 5.6 The circuit of Fig. 5.16 simplifies as given in Fig. 5.17 in which a source transformation technique is used. Hence, Vout/Iin is evaluated as R3 R1 R3 V out V = ) out = R1 I in R1 þ R2 I in R1 þ R2

ð5:9Þ

Example 5.7 If gain of the nominal value of the inverting amplifier is 10 and both resistors have 5% tolerance, find the range of Vout/Vin. Solution 5.7 The range of Vout/Vin is found below. - 10 ×

0:95 V out 1:05 V ≥ - 10 × ≥ ) - 9:05 ≥ out ≥ - 11:05 V in V in 1:05 0:95

ð5:10Þ

5.3

OA-Based Basic Circuits

97

Fig. 5.18 An integrator topology

C

Vin(s)

R

Vout(s)

OA + A→f Fig. 5.19 A differentiator circuit

R

C Vin(s)

OA

Vout(s)

+ A→f

Example 5.8 Analyze the integrator circuit depicted in Fig. 5.18. Solution 5.8 Transfer function (TF) of this structure in s domain is evaluated by V in ðsÞ 1 = - sCV out ðsÞ ) V out ðsÞ = V ðsÞ R sCR in V ðsÞ 1 =) H ðsÞ = out sCR V in ðsÞ

ð5:11Þ

Output voltage of the integrator in the time domain is calculated as t

1 vout ðt Þ = CR

vin ðτÞdτ

ð5:12Þ

-1

Example 5.9 Analyze the differentiator circuit demonstrated in Fig. 5.19. Solution 5.9 TF of this structure in s domain is calculated as follows: V in ðsÞsC = -

V out ðsÞ ) V out ðsÞ = - sCRV in ðsÞ R V ðsÞ ) H ðsÞ = out = - sCR V in ðsÞ

Output voltage of the differentiator in the time domain is found as

ð5:13Þ

98

5

Fig. 5.20 An antilogarithmic amplifier circuit based on a physical diode

Operational Amplifiers and Their Applications

R

Vin

D

OA

Vout

+ A→f Fig. 5.21 An antilogarithmic amplifier circuit based on a pnp-type BJT

R

BJT

Vin

OA

Vout

+ A→f Fig. 5.22 A logarithmic amplifier circuit based on a physical diode

D

Vin

R

OA

Vout

+ A→f

vout ðt Þ = - CR

dvin ðt Þ dt

ð5:14Þ

Example 5.10 Analyze the antilogarithmic amplifier topologies given in Figs. 5.20 and 5.21. A physical diode is used in Fig. 5.20, while a pnp-type BJT is utilized in Fig. 5.21. Solution 5.10 Analysis of these structures is performed as given below. I Se

V in - V VT

=

V in V - - V out ) V out = - RI S e V T R

ð5:15Þ

where IS is the saturation current and VT is the thermal voltage. Also, VT = kT/ q ffi 25 mV at room temperature that is 27 °C = 300 K. For Vin ≥ 5 VT, the circuits given in Figs. 5.20 and 5.21 operate properly. Example 5.11 Analyze the logarithmic amplifier circuits are depicted in Figs. 5.22 and 5.23. A physical diode is used in Fig. 5.22, while an npn type BJT is utilized in Fig. 5.23.

5.3

OA-Based Basic Circuits

99

Fig. 5.23 A logarithmic amplifier topology based on an npn type BJT

BJT

Vin

R

OA

Vout

+ A→f Fig. 5.24 A squarer based on a PMOS transistor, one resistor, and one OA

R

Vin

PMOS

OA

– VTP

Vout

+ A→f

NMOS

Fig. 5.25 A square rooter based on an NMOS transistor, one resistor, and one OA

Vin

R

-

VTN

OA

Vout

+ A→f

Solution 5.11 Analysis of these circuits is performed as given below. ISe

V - - V out VT

=

V in - V V ) V out = - V T ln in R I SR

ð5:16Þ

For Vout ≤ -5 VT, the circuits given in Figs. 5.22 and 5.23 operate properly. Example 5.12 Analyze the squarer circuit based on a PMOS transistor, one resistor, and one OA shown in Fig. 5.24. It is assumed that PMOS transistor works in the saturation region. Solution 5.12 Analysis of this structure is performed as given below. kp kp V - V out ðV - ð - jV TP jÞ - jV TP jÞ2 = ) V out = - R V 2in 2 in R 2

ð5:17Þ

Example 5.13 Analyze the square rooter circuit based on an NMOS transistor, one resistor, and one OA shown in Fig. 5.25. It is assumed that NMOS transistor works in the saturation region.

100

5

Operational Amplifiers and Their Applications

Fig. 5.26 An analog adder structure

R1

V1 V2

V1

R1

OA

Vout

+ A→f

R2

OA (1) + A→f

V2

R2

R3

R3

Vo

R5

OA

Vout

(2) + A→f

R4

Fig. 5.27 A circuit for providing Vout = 3 V1 – 4 V2

Solution 5.13 Analysis of this topology is performed as V -VkN ðV TN - V out - V TN Þ2 = in ) V out = ± 2 R

2V in kN R

ð5:18Þ

where VGS > VTN must be satisfied; therefore, Vout is evaluated as in the following: V out = -

2V in kN R

ð5:19Þ

For the circuits in Figs. 5.24 and 5.25, Vin > 0 must be satisfied. Example 5.14 Analyze the analog adder circuit depicted in Fig. 5.26. Solution 5.14 Analysis of this circuit is performed by V V1 - V - V2 - V V - V out V þ = ) V out = - R3 1 þ 2 R1 R2 R3 R1 R2

ð5:20Þ

Example 5.15 Design a circuit for realizing Vout = 3 V1 – 4 V2. Solution 5.15 The structure for providing Vout = 3 V1 – 4 V2 is given in Fig. 5.27. Vout of the topology in Fig. 5.27 is found below.

5.3

V1

V2

V3 V4

OA-Based Basic Circuits

101

R3

R1

-

R4

OA

R2

(1) + A→f

Vo

R7

OA

Vout

(2) + A→f

R5 R6

Fig. 5.28 A circuit for providing Vout = 5 V1 + 4 V2 - 2.5 V3 – 2 V4

Vo = -

R2 R R R R R V ) V out = - 5 V o - 5 V 2 ) V out = 2 5 V 1 - 5 V 2 R1 1 R3 R4 R1 R3 R4

ð5:21Þ

It is observed from equation in (5.21) that if R1 = R4 = 1 kΩ, R2 = 3 kΩ, and R3 = R5 = 4 kΩ are chosen, Vout = 3 V1 – 4 V2 is easily obtained. Example 5.16 Design a circuit for realizing Vout = 5 V1 + 4 V2 – 2.5 V3 – 2 V4. Solution 5.16 The structure for providing Vout = 5 V1 + 4 V2 - 2.5 V3 – 2 V4 is given in Fig. 5.28. Vout of the circuit in Fig. 5.28 is evaluated as Vo = -

R3 R R R R V - 3 V ) V out = - 7 V o - 7 V 3 - 7 V 4 R1 1 R2 2 R4 R5 R6

ð5:22Þ

From Eq. (5.22), Vout of the circuit in Fig. 5.28 is recomputed as follows: V out =

R3 R7 R R R R V þ 3 7V - 7V - 7V R1 R4 1 R2 R4 2 R5 3 R6 4

ð5:23Þ

It is seen from equation given in (5.23) that if R1 = R3 = R4 = 1 kΩ, R2 = 1.25 kΩ, R5 = 2 kΩ, R6 = 2.5 kΩ, and R7 = 5 kΩ are taken, Vout = 5 V1 + 4 V2 - 2.5 V3 – 2 V4 is easily obtained. Example 5.17 Analyze the first-order low-pass filter (LPF) depicted in Fig. 5.29. Solution 5.17 Analysis of this topology is performed as follows: 1 V in = - V out sC þ R2 R1

) V out = -

R2 1 V R1 1 þ sCR2 in

ð5:24Þ

Example 5.18 Analyze the first-order high-pass filter (HPF) demonstrated in Fig. 5.30.

102

5

Operational Amplifiers and Their Applications

Fig. 5.29 A first-order LPF

C

R2

R1

Vin

OA

Vout

+ A→f Fig. 5.30 A first-order HPF

R2 Vin(s)

C

R1

Vout(s)

OA

+ A→f

C1

C2

Vin(s)

R1

R2

OA

R4

R3

(1)

OA

+ A→f

(2)

Vout(s)

+ A→f Fig. 5.31 A topology for realizing TF given in (5.26)

Solution 5.18 Analysis of this topology is performed as - V out R R V in sCR1 s = ) V out = - 2 V =- 2 V 1 R2 R1 1 þ sCR1 in R1 s þ CR1 in R1 þ sC 1

ð5:25Þ

Example 5.19 Design a circuit for realizing the following TF: H ðsÞ =

100 1 þ 10s 7

2

ð5:26Þ

Solution 5.19 The circuit for providing TF in (5.26) is given in Fig. 5.31. This circuit can be easily obtained by cascading two first-order LPFs given in Fig. 5.29. Hence, TF of (5.26) becomes below.

5.3

OA-Based Basic Circuits

Vin(s)

R1

103

R2

C1

-

R3

OA (1)

C2

R4

OA (2)

+ A→f

Vout(s)

+ A→f

Fig. 5.32 A topology for providing TF given in (5.30)

H ðsÞ =

100 1 þ 10s 7

2

=

- 10 - 10 × 1 þ 10s 7 1 þ 10s 7

ð5:27Þ

From Eq. (5.27), H(s) simplifies as H ðsÞ =

- RR43 - RR21 - 10 - 10 × = × 1 þ 10s 7 1 þ 10s 7 1 þ sC1 R2 1 þ sC2 R4

ð5:28Þ

From Eq. (5.28), the following equations are obtained: R2 R4 = = 10 R1 R3

ð5:29aÞ

C1 R2 = C2 R4 = 10 - 7

ð5:29bÞ

If C1 = C2 = 100 pF are chosen, R2 = R4 = 1 kΩ and R1 = R3 = 100 Ω are found. Example 5.20 Design a topology for realizing the following TF: H ðsÞ =

100s2 s þ 107

2

ð5:30Þ

Solution 5.20 The circuit for providing TF of (5.30) is plotted in Fig. 5.32. This topology can be easily obtained by cascading two first-order HPFs given in Fig. 5.30. Therefore, TF of (5.30) becomes as H ðsÞ =

100s2 s þ 107

2

=

- RR43 s - RR21 s - 10s - 10s × = × s þ 107 s þ 107 s þ C11R1 s þ C21R3

From Eq. (5.31), the following equations are obtained:

ð5:31Þ

104

5

Operational Amplifiers and Their Applications

R2 R1

R6

-

Vin

OA (1)

C1

R4

Vo1

OA (2)

+ A→f

Vout

+ A→f C2 R3

OA (3)

Vo2

R5

+ A→f

Fig. 5.33 A topology for providing a PID controller

R2 R4 = = 10 R1 R3

ð5:32aÞ

C1 R1 = C2 R3 = 10 - 7

ð5:32bÞ

If C1 = C2 = 100 pF are taken, R1 = R3 = 1 kΩ and R2 = R4 = 10 kΩ are found. Example 5.21 Design a circuit for realizing the proportional integral derivative (PID) controller. Further, TF of the PID controller is defined as H ðsÞ = K p þ

1 þ sT d sT i

ð5:33Þ

Here, Kp, Ti, and Td are, respectively, called as proportional, integral, and derivative constants. Solution 5.21 The OA-based PID controller is demonstrated in Fig. 5.33. Analysis of this PID controller is achieved as follows: Firstly, Vo1 and Vo2 in Fig. 5.33 are, respectively, evaluated as sC 1 þ

1 V R V = - o1 ) V o1 = - 2 V in - sC 1 R2 V in R1 in R2 R1

ð5:34aÞ

V in V in = - sC 2 V o2 ) V o2 = R3 sC 2 R3

ð5:34bÞ

From equations in (5.34), Vout through Vo1 and Vo2 is computed as

5.3

OA-Based Basic Circuits

105

V out = -

R6 R V - 6V R4 o1 R5 o2

ð5:35Þ

By replacing Vo1 and Vo2 into Eq. (5.35), Vout is calculated below. V out =

R R6 R2 R6 1 þ þ sC 1 R2 6 V in R4 R1 R5 sC 2 R3 R4

= Kp þ

ð5:36Þ

1 þ sT d V in sT i

The parameters, Kp, Ti, and Td are, respectively, found as follows: R6 R2 R4 R1

ð5:37aÞ

C 2 R3 R5 R6

ð5:37bÞ

R6 R4

ð5:37cÞ

Kp = Ti =

T d = C 1 R2

Fig. 5.34 A voltage divider circuit

RS=100 k: +_

RS=100 k: + _

Vs=10V

Vs=10V

Iout

+ OA

-

Vout

A→f

Iout

Fig. 5.35 An example for the use of the voltage follower

RL=10 k:

Vout RL=10 k:

106

5.4

5

Operational Amplifiers and Their Applications

Some More Examples Based on the OA

Example 5.22 Find Iout and Vout of the topologies depicted in Figs. 5.34 and 5.35. Solution 5.22 Iout and Vout of the circuit in Fig. 5.34 are, respectively, found as 10 ffi 0:0909mA 110k 10 V out = × 10 ffi 0:909V 110 I out =

ð5:38aÞ ð5:38bÞ

Iout and Vout of the circuit given in Fig. 5.35 are, respectively, evaluated below. I out =

10 = 1mA 10k

ð5:39aÞ

V out = 10V

ð5:39bÞ

Example 5.23 Design a circuit to obtain a current from the voltage. Solution 5.23 This circuit is shown in Fig. 5.36. Analysis of this circuit, the following current is obtained. I out =

V in R

ð5:40Þ

Example 5.24 Design a circuit to obtain a voltage from the current. Solution 5.24 This topology is depicted in Fig. 5.37. Analysis of this circuit, the following voltage is obtained: V out = - RI in

Fig. 5.36 The circuit of Example 5.23

ð5:41Þ

Vin

+ OA

-

A→f

Iout

R

5.4

Some More Examples Based on the OA

107

Fig. 5.37 The circuit of Example 5.24

R

-

Iin

OA

Vout

+ A→f Fig. 5.38 The circuit of Example 5.25

R2

Iin

OA

R1 +

Fig. 5.39 The obtained circuit by performing source transformation to Example 5.25

Vout

A→f

RL

R2 R1 R1Iin

OA

+ _

+ A→f

Vout

RL

Example 5.25 Find output voltage of the circuit in Fig. 5.38 in terms of the applied input current. Solution 5.25 No current is passing through resistor R1 resulting in IR2 = Iin. Therefore, output voltage is computed as V out = - R2 I in

ð5:42Þ

The second approach for solution of Example 5.25 is source transformation technique. Therefore, the structure in Fig. 5.38 is obtained as in Fig. 5.39, and the following output voltage is found: V I in R1 = - out ) V out = - R2 I in R1 R2

ð5:43Þ

Example 5.26 Find output voltage of the circuit in Fig. 5.40 in terms of the applied input current.

108

5

Operational Amplifiers and Their Applications

-

Fig. 5.40 The circuit of Example 5.26

OA

Iin R1

+

Vout

A→f

Vtest R3 I //

R2 I /

Solution 5.26 Vtest is firstly calculated as I in =

0 - V test ) V test = - R1 I in R1

ð5:44Þ

The currents I/ and I// are, respectively, computed as follows: I= =

0 - V test R = 1 I in R2 R2

I == = I = þ I in = 1 þ

ð5:45aÞ

R1 I R2 in

ð5:45bÞ

From equations in (5.45), Vout is evaluated as V out = V test - I == R3 = - R1 I in - 1 þ R R = - R1 þ R3 þ 1 3 I in R2

5.5

R1 I R R2 in 3

ð5:46Þ

Finite Open Loop Gain of the OA

In practice, open loop gain A < 1. In other words, A takes values between 104 ≤ A ≤ 106 where value of A is taken as DC. Actually, A is frequency dependent and decreases as the frequency rises. In this subsection, effect of the finite open loop gain of the OA on the output of the inverting amplifier, non-inverting amplifier, and voltage follower (VF) is investigated.

5.5

Finite Open Loop Gain of the OA

Fig. 5.41 An inverting amplifier with a finite gain OA

109

R2

R1

Vin

V-

OA +

Fig. 5.42 A non-inverting amplifier with a finite gain OA

Vout

A 4.8 V (Vout = -9 V), the OA saturates. Example 5.52 Find the range of R2 for the circuit in Fig. 5.52 such that OA operates in linear region in which Vr = ±9 V. Solution 5.52 V+ = V- is calculated by Vþ = V - = - 5 ×

10 = - 2V 25

ð5:104Þ

The range of Vout is computed as - 9 V ≤ V out ≤ 9 V

ð5:105Þ

From KVL, the following equation is obtained: V - V out -5 þ 2 - 2 - V out -5-V= ) = R1 R2 R2 2k

ð5:106Þ

From Eq. (5.106), Vout is calculated as V out = - 2 þ

3 R 2k 2

ð5:107Þ

From Eq. (5.107), the range of R2 is evaluated as follows: -9≤ -2 þ

22 3 kΩ R ≤ 9 ) R2 ≤ 3 2k 2

ð5:108Þ

5.10

Simulated Grounded Inductors

5.10

123

Simulated Grounded Inductors

Simulated inductors (SIs), namely, synthetic inductors, can be mainly categorized into two subgroups, grounded and floating ones. In addition, SIs can be divided into two subsections, lossy and lossless ones. In this subsection, simulated grounded inductors (SGIs) are investigated. SGIs behave like an inductor in a certain frequency range.

5.10.1

Lossy SGIs

Example 5.53 Find the input impedance of the parallel lossy SGI depicted in Fig. 5.53 [6]. Solution 5.53 Analysis of this circuit is accomplished below. I in =

V in - V test V in þ R1 R2

ð5:109aÞ

V V in = - sCV test ) V test = - in R2 sCR2

ð5:109bÞ

If Vtest in Eq. (5.109b) is replaced into Eq. (5.109a), Iin in terms of Vin is computed as I in =

V in V in V in þ þ R2 R1 sCR1 R2

ð5:110Þ

From equation in (5.110), Zin = Vin/Iin is evaluated by

Fig. 5.53 A parallel lossy SGI

R1

C Vtest

Vin

Iin

R2

OA + A→f

Zin

124

5

Operational Amplifiers and Their Applications

Fig. 5.54 An equivalent circuit for the parallel lossy SGI in Fig. 5.53

Vin

Iin Req

Leq

Zin R1

C Vtest

Vin

Iin

+ OA (1)

-

R2

A→f

OA (2) + A→f

Zin Fig. 5.55 Another parallel lossy SGI

Z in =

V in = I in

1 R1

1 = sLeq ==Req þ R12 þ sCR11 R2

ð5:111Þ

Here, Leq = CR1R2 and Req = R1//R2. Equivalent circuit for the parallel lossy SGI is given in Fig. 5.54. Example 5.54 Find the input impedance of another parallel lossy SGI shown in Fig. 5.55 [7]. Solution 5.54 Analysis of this circuit is achieved below. I in =

V in - V test R1

V V in = - V test sC ) V test = - in R2 sCR2

ð5:112aÞ ð5:112bÞ

If Vtest in Eq. (5.112b) is replaced into Eq. (5.112a), Iin in terms of Vin is calculated by I in =

V in V in þ R1 sCR1 R2

From above equation, Zin = Vin/Iin is found as

ð5:113Þ

5.10

Simulated Grounded Inductors

125

Fig. 5.56 A series lossy SGI

OA Vin

+ A→f

Iin

C

R1

Vtest

Zin

R2

Z in =

V in = I in

1 1 R1

þ sCR11 R2

= sLeq ==Req

ð5:114Þ

where Leq = CR1R2 and Req = R1. Example 5.55 Find the input impedance of the series lossy SGI demonstrated in Fig. 5.56 [8]. Solution 5.55 Analysis of this structure is accomplished as follows: I in =

V in - V test R1

ð5:115aÞ

V in - V test V þ ðV in - V test ÞsC = test R1 R2

ð5:115bÞ

Expansion of equation in (5.115b), the following equation is obtained: V in V V þ sCV in = test þ test þ sCV test R1 R1 R2

ð5:116Þ

From equation given in (5.116), Vtest is evaluated as V test =

1 R1 1 R1

þ sC

þ R12 þ sC

V in

If Vtest in Eq. (5.117) is replaced in Eq. (5.115a), Iin is found below.

ð5:117Þ

126

5

Operational Amplifiers and Their Applications

Fig. 5.57 An equivalent circuit for the series lossy SGI

Vin

Iin Req Leq

I in =

V in -

1 R1 þsC 1 1 þ R1 R2 þsC

V in

=

R1

1 1 R1 þR2 þsC 1 1 þ R1 R2 þsC

V in þ

- R1 - sC 1 1 1 R1 þR2 þsC

V in

R1

ð5:118Þ

Simplification of equation in (5.118), the following equation is found:

I in =

1 R2 1 1 R1 þR2 þsC

V in

ð5:119Þ

R1

Further simplification of equation in (5.119), the following equation is obtained: 1 R2

I in =

× R2

1 1 R1 þR2 þsC

× R2

R1 ×

V in ×

1 R1

ð5:120Þ

1 R1

From equation in (5.120), Zin is evaluated as follows: Z in =

V in = R1 þ R2 þ sCR1 R2 = Req þ sLeq I in

ð5:121Þ

Here, Leq = CR1R2 and Req = R1 + R2. Further, an equivalent circuit for the series lossy SGI is depicted in Fig. 5.57. Example 5.56 Find the input impedance of another series lossy SGI shown in Fig. 5.58 [7]. Solution 5.56 Analysis of this topology is carried out as in the following two equations: I in =

V in - V test R1

ðV in - V test ÞsC =

V test R2

Expansion of equation in (5.122b), the following equation is obtained:

ð5:122aÞ ð5:122bÞ

5.10

Simulated Grounded Inductors

127

OA (2) Vin

+ A→f

Iin

C

R1 Vtest

+

Zin

OA (1)

R2

-

A→f

Fig. 5.58 Another series lossy SGI

sCV in =

V test þ sCV test R2

ð5:123Þ

From above equation, Vtest is calculated as V test =

1 R2

sC V in þ sC

ð5:124Þ

If Vtest in Eq. (5.124) is replaced into Eq. (5.122a), the following equation is found:

I in =

V in -

sC

1 R2 þsC

V in

R1

=

1 R2 þsC 1 R2 þsC

V in þ R1

- sC

1 R2 þsC

V in

ð5:125Þ

From equation given in (5.125), Iin is computed as

I in =

1 R2 1 R2 þsC

V in

ð5:126Þ

R1

Simplifying equation in (5.126), Iin is obtained below. 1 R2

I in =

× R2

1 R2 þsC

× R2

R1 ×

From equation in (5.127), Zin is evaluated as

V in × 1 R1

1 R1

ð5:127Þ

128

5

Z in =

Operational Amplifiers and Their Applications

V in = R1 þ sCR1 R2 = Req þ sLeq I in

ð5:128Þ

where Leq = CR1R2 and Req = R1.

5.10.2

Lossless SGIs

In this subsection, negative/positive lossless SGIs by example are treated. Example 5.57 Find the input impedance of the negative lossless SGI depicted in Fig. 5.59. Solution 5.57 Analysis of this structure is achieved by the following two equations: I in =

V in - V test R1

ðV test - V in ÞsC =

ð5:129aÞ V in R2

ð5:129bÞ

Expansion of equation in (5.129b), the following equation is found: V in - V test = -

V in sCR2

ð5:130Þ

If equation in (5.130) is replaced into equation in (5.129a), the following input impedance is evaluated:

Fig. 5.59 A negative lossless SGI

R1

Vin

+

Iin

OA

-

A→f

Zin C R2

Vtest

5.10

Simulated Grounded Inductors

129

(1)

Vin

Iin

R1

R2

R4

OA +

-

A→f

V2

C

V1 + OA (2)

Zin

R3

A→f

Fig. 5.60 A positive lossless SGI

Z in =

V in = - sCR1 R2 = - sLeq I in

ð5:131Þ

Here, Leq = CR1R2. Example 5.58 Find the input impedance of the positive lossless SGI given in Fig. 5.60 [9]. Solution 5.58 Analysis of this circuit is achieved by the following three equations: I in =

V in - V 1 R1

ð5:132aÞ

V 1 - V in V in - V 2 = R4 R2

ð5:132bÞ

V in R3

ð5:132cÞ

ðV 2 - V in ÞsC = From equations in (5.132), Zin is calculated by Z in =

V in sCR1 R2 R3 = = sLeq I in R4

ð5:133Þ

Here, Leq = CR1R2R3/R4. Example 5.59 Find the input impedance of another positive lossless SGI demonstrated in Fig. 5.61 [10].

130

5

Operational Amplifiers and Their Applications

R1 V2 C1

R2 Vin

Iin

+

V1 OA (1)

-

-

V1

A→f

C2

Zin

OA (2) + A→f

R3

Fig. 5.61 Another positive lossless SGI

Solution 5.59 This structure is analyzed by the following three equations: I in =

V in - V 2 R1

ð5:134aÞ

V in - V 1 = ðV 1 - V 2 ÞsC 1 R2 ðV in - V 1 ÞsC 2 =

V1 R3

ð5:134bÞ ð5:134cÞ

From equations given in (5.134), Zin is computed as follows: Z in =

V in sC 1 R1 R2 ð1 þ sC2 R3 Þ = 1 þ sC 1 R2 I in

ð5:135Þ

If the following matching condition is met: C 2 R3 = C 1 R2

ð5:136Þ

Input impedance of this SGI becomes as Z in =

V in = sC 1 R1 R2 = sLeq I in

ð5:137Þ

In above equation, Leq = C1R1R2. Example 5.60 Find the input impedance of the single OA-based positive lossless SGI shown in Fig. 5.62 [11].

5.10

Simulated Grounded Inductors

131

Fig. 5.62 A single OA-based positive lossless SGI.

R6

V2 C

R3

Vin

Iin

V1 R1

R4

-

V1

Zin

V3

R5

OA + A→f

R2

Solution 5.60 This circuit is analyzed by the following four equations: I in =

V in - V 1 V in - V 1 V in - V 3 þ þ R3 R1 R6 V in - V 1 = ðV 1 - V 2 ÞsC R3

ðV 1 - V 2 ÞsC =

V2 - V3 V2 þ R5 R4

V in - V 1 V 1 = R1 R2

ð5:138aÞ ð5:138bÞ ð5:138cÞ ð5:138dÞ

From equations indicated in (5.138), Zin is found below. Z in = =

V in I in

sC ðR1 þ R2 ÞR3 R4 R6 R1 ðR4 þ R5 Þ þ sC ðR1 R3 R4 þ R1 R4 R5 þ R1 R4 R6 þ R3 R4 R6 - R2 R3 R5 Þ ð5:139Þ

In above equation, if the following matching constraint is met, R1 R3 R4 þ R1 R4 R5 þ R1 R4 R6 þ R3 R4 R6 = R2 R3 R5 Zin simplifies as

ð5:140Þ

132

5

Z in =

Operational Amplifiers and Their Applications

V in sC ðR1 þ R2 ÞR3 R4 R6 = = sLeq I in R1 ðR4 þ R5 Þ

ð5:141Þ

Note Mathematical programs should be used in calculation of the input impedances of the SGIs in Figs. 5.60, 5.61, and 5.62.

5.11

Rectifiers

Rectifiers can be divided into two subgroups, half-wave rectifiers (HWRs) and fullwave rectifiers (FWRs). Example 5.61 Find the output voltage of the simple single OA-based HWR given in Fig. 5.63 [4]. Solution 5.61 This HWR is analyzed as follows: If vin ðt Þ ≥ 0 is taken, diode is ON ) vout ðt Þ = vin ðt Þ

ð5:142aÞ

If vin ðt Þ < 0 is taken, diode is OFF ) vout ðt Þ = 0

ð5:142bÞ

A drawback of this circuit is that the OA is in saturation when vin(t) < 0 and OA can be destroyed if the magnitude of the input voltage is larger than a few volts. Vin-Vout characteristics of the HWR of Fig. 5.63 are depicted in Fig. 5.64. Example 5.62 Find the output voltage of another single OA-based HWR shown in Fig. 5.65. Fig. 5.63 A single OA-based HWR

vin(t)

+

D

vout(t)

OA

-

A→f

RL

Fig. 5.64 Vin-Vout characteristics of the HWR in Fig. 5.63

Vout 1

Vin

5.11

Rectifiers

Fig. 5.65 Another single OA-based HWR

133

vin(t)

R2

R1

vout(t) D2

D1

OA

+ A→f Fig. 5.66 Vin-Vout characteristics of the HWR in Fig. 5.65

Vout –

R2 R1

Vin

Solution 5.62 This HWR is analyzed below. If vin ðt Þ ≥ 0 is taken, D1 is ON and D2 is OFF ) vout ðt Þ = 0 If vin ðt Þ < 0 is taken, D1 is OFF and D2 is ON ) vout ðt Þ = -

ð5:143aÞ

R2 v ðt Þ ð5:143bÞ R1 in

Vin-Vout characteristics of the HWR in Fig. 5.65 are demonstrated in Fig. 5.66. Example 5.63 Find the output voltage of the OA-based FWR shown in Fig. 5.67 [4]. Solution 5.63 This circuit for R2 = R1 is analyzed as in the following: If vin ðt Þ ≥ 0 is chosen D1 is ON and D2 is OFF ) vout ðt Þ = vin ðt Þ

ð5:144aÞ

If vin ðt Þ < 0 is chosen D1 is OFF and D2 is ON ) vout ðt Þ = - vin ðt Þ

ð5:144bÞ

From equations denoted in (5.144), vout(t) is evaluated as vout ðt Þ = jvin ðt Þj

ð5:145Þ

Vin-Vout characteristics of the FWR in Fig. 5.67 are shown in Fig. 5.68. Example 5.64 Find the output voltage of another OA-based FWR depicted in Fig. 5.69 [12].

134

5

Operational Amplifiers and Their Applications

OA vin(t)

(1)

D1

+ A→f

vout(t)

R2

R1

OA

(2)

D2

+ A→f Fig. 5.67 An OA-based FWR Fig. 5.68 Vin-Vout characteristics of the FWR in Fig. 5.67

Vout 1

-1

Vin

R

vin(t)

R

R

D2

D1

OA

(1)

+ A→f Fig. 5.69 Another OA-based FWR

aR

R/2

Vo

OA

(2)

+ A→f

vout(t)

5.12

Wien Oscillators

135

Fig. 5.70 Vin-Vout characteristics of the FWR in Fig. 5.69

Vout a

-a

Vin Fig. 5.71 A Wien oscillator

R4

OA

R1

Vout

+ A→f

C1 R3 R2

C2

Solution 5.64 This structure with four resistive matching condition is analyzed as If vin ðtÞ ≥ 0 is taken, D1 is OFF and D2 is ON ) vout ðtÞ = - ðaR=RÞðvin ðtÞÞ - aRðR=2Þð - vin ðtÞÞ = avin ðtÞ If vin ðtÞ < 0 is taken, D1 is ON and D2 is OFF ) vout ðt Þ = - ðaR=RÞðvin ðt ÞÞ - 0 = - avin ðt Þ

ð5:146aÞ ð5:146bÞ

Therefore, vout(t) is calculated as vout ðt Þ = ajvin ðt Þj

ð5:147Þ

Vin-Vout characteristics of the FWR in Fig. 5.69 are depicted in Fig. 5.70.

5.12

Wien Oscillators

Wien oscillators provide only one sinusoidal output. Example 5.65 Find the characteristic eq. (D(s)), oscillation condition (OC), and oscillation frequency (OF) of the Wien oscillator demonstrated in Fig. 5.71 [13].

136

5

Operational Amplifiers and Their Applications

Solution 5.65 Its analysis is carried out by the following three equations: V - = Vþ

ð5:148aÞ

VV out - V = R4 R1 þ sC1 1

ð5:148bÞ

1 V out - V þ = V þ sC 2 þ R2 R3

ð5:148cÞ

By using equations in (5.148a) and (5.148b), Vout in terms of V+ is found as V out =

R4 þ R1 þ sC1 1 R4 V þ V = Vþ þ þ R1 þ sC1 1 R1 þ sC1 1

ð5:149Þ

If both numerator and denominator are multiplied by sC1, Vout becomes as V out =

R1 þ R4 sC 1 þ 1 Vþ sC 1 R1 þ 1

ð5:150Þ

If equation in (5.148c) is rearranged, Vout by means of V+ is found as follows: V out = V þ sC 2 R3 þ

R3 þ1 R2

ð5:151Þ

Equation given in (5.150) equal to equation in (5.151); thus, the following equation is obtained: V out = V þ sC 2 R3 þ

R þ R4 sC 1 þ 1 R3 þ 1 = Vþ 1 R2 sC 1 R1 þ 1

ð5:152Þ

From equation in (5.152), the following equation is obtained: R

sC 2 R3 þ R32 þ 1 R þ R4 sC 1 þ 1 = 1 1 sC1 R1 þ 1

ð5:153Þ

Similarly, from equation in (5.153), the following equation is obtained: sC 2 R3 þ

R3 þ1 R2

sC1 R1 þ 1 = R1 þ R4 sC 1 þ 1

Expansion of equation in (5.154), the following equation is found:

ð5:154Þ

5.12

Wien Oscillators

137

Fig. 5.72 Another Wien oscillator

R1

OA

R2

+ A→f R3 R4

s2 C 1 C 2 R 1 R 3 þ s C 1 R 1

Vout

C1

C2

R3 þ C2 R3 - C1 R4 R2

þ

R3 =0 R2

ð5:155Þ

If both sides of equation in (5.155) are multiplied by R2/R3, the following D(s) is obtained: DðsÞ = s2 C1 C2 R1 R2 þ s C 1 R1 þ C 2 R2 - C 1

R2 R4 R3

þ 1=0

ð5:156Þ

From equation given in (5.156), the following OC and OF are, respectively, obtained as C1

R2 R4 ≥ C1 R1 þ C 2 R2 R3

f0 =

1 2π

1 C 1 C 2 R1 R2

ð5:157aÞ ð5:157bÞ

Example 5.66 Find D(s), OC, and OF of another Wien oscillator shown in Fig. 5.72 [4]. Solution 5.66 Analysis of this topology is achieved by the following two equations: V - = Vþ = V out -

R2 R1 þR2 V out R3 þ sC1 1

=

R2 V R1 þ R2 out

R2 1 V sC 2 þ R4 R1 þ R2 out

From equation in (5.158b), D(s) is evaluated as

ð5:158aÞ ð5:158bÞ

138

5

Operational Amplifiers and Their Applications

C 1 R1 R4 R2

DðsÞ = s2 C1 C2 R3 R4 þ s C 1 R3 þ C 2 R4 -

þ 1=0

ð5:159Þ

From equations given in (5.159), OC and OF are, respectively, computed below. C 1 R1 R4 ≥ C 1 R3 þ C2 R4 R2 f0 =

5.13

1 2π

ð5:160aÞ

1 C 1 C 2 R3 R4

ð5:160bÞ

Analog Filters

Analog filters can be mainly divided into three subcategories, first-order filters, second-order filters, and high-order filters. In this subsection, it is dealt with firstorder and second-order ones. Example 5.67 Find the first-order all-pass filter (APF) depicted in Fig. 5.73 [14]. Solution 5.67 This filter is analyzed as follows: V - = Vþ = V in -

1 1þsCR V in

R1

1 V 1 þ sCR in

=

1 1þsCR V in

ð5:161aÞ

- V out

ð5:161bÞ

R2

From above equations, TF is computed by

Fig. 5.73 A first-order APF

R2 R1

OA

Vin R

+ C

A→f

Vout

5.13

Analog Filters

139 C1

Vin

R1 Vtest

+

-

R2

(1)

OA

+ OA

A→f

C2

-

(2)

Vout

A→f

Fig. 5.74 A second-order LPF

1 - sCR RR21 V out H ðsÞ = = V in 1 þ sCR

ð5:162Þ

If R2 = R1 is taken for equation in (5.162), TF of this filter becomes below. H ðsÞ =

1 - sCR V out = 1 þ sCR V in

ð5:163Þ

Example 5.68 Find the TF of the second-order LPF exhibited in Fig. 5.74 [15]. Solution 5.68 Analysis of this circuit is achieved by the following two equations: V in - V test = ðV test - V out ÞsC1 R1 V test - V out = V out sC 2 ) V test = V out ð1 þ sC 2 R2 Þ R2

ð5:164aÞ ð5:164bÞ

From above equations, TF is evaluated as 1

H ðsÞ =

ω20 V out C 1 C 2 R1 R2 = 2 = 2 1 1 V in s þ s C1 R1 þ C1 C2 R1 R2 s þ s ωQ0 þ ω20

ð5:165Þ

where angular resonance frequency (ω0) and quality factor (Q) are, respectively, found as ω20 =

1 ) ω0 = C 1 C 2 R1 R2 ω0 1 = ) Q= Q C 1 R1

1 C 1 C 2 R1 R2 C1 R1 C2 R2

ð5:166aÞ ð5:166bÞ

Example 5.69 Find the TF of the multiple feedback second-order LPF demonstrated in Fig. 5.75.

140

5

R2

C1 R3

R1

Vin

Operational Amplifiers and Their Applications

Vtest

OA

C2

Vout

+ A→f

Fig. 5.75 A multiple feedback second-order LPF

Solution 5.69 Analysis of this circuit is achieved by the following two equations: V in - V test V - V out V test = test þ þ V test sC 2 R1 R2 R3

ð5:167aÞ

V test = - V out sC 1 ) V test = - V out sC 1 R3 R3

ð5:167bÞ

From equations in (5.167), the following TF is computed: H ðsÞ =

1 V out R =- 2 V in R1 s2 C C R R þ sC R þ R þ R2 R3 þ 1 1 2 2 3 1 2 3 R1

ð5:168Þ

Here, ω0 and Q are, respectively, evaluated as ω20 =

1 ) ω0 = C 1 C 2 R2 R3

1 C 1 C 2 R2 R3

R2 R3 ω0 R2 þ R3 þ R1 1 ) Q= = Q C 2 R2 R3 R2 þ R3 þ RR2 R1 3

C 2 R2 R3 C1

ð5:169aÞ ð5:169bÞ

Example 5.70 Find the TF of the second-order LPF demonstrated in Fig. 5.76 [16]. Solution 5.70 This LPF is analyzed by the following two equations: V - V out V in - V test = ðV test - V out ÞsC 1 þ test R1 R2 V test - V out = V out sC 2 ) V test = V out ð1 þ sC2 R2 Þ R2 From above equations, the following TF is obtained:

ð5:170aÞ ð5:170bÞ

5.13

Analog Filters

141

C1

Vin

R1

R2

+

Vtest

OA C2

-

Vout

A→f

Fig. 5.76 A second-order LPF

R2

Vin

C1

R1

+

Vtest

OA R3

C2

-

Vout

A→f

Fig. 5.77 A Sallen-Key second-order BPF

H ðsÞ =

V out 1 = 2 V in s C 1 C 2 R1 R2 þ sC 2 ðR1 þ R2 Þ þ 1

ð5:171Þ

where ω0 and Q are, respectively, found as follows: ω20 =

1 ) ω0 = C 1 C 2 R1 R2

1 C 1 C 2 R1 R2

ω0 R1 þ R2 1 ) Q= = Q C 1 R1 R2 R1 þ R2

C 1 R1 R2 C2

ð5:172aÞ ð5:172bÞ

Note If RC-CR transformations are performed for the LPFs in Figs. 5.74, 5.75, and 5.76, HPFs are obtained. Example 5.71 Find the TF of the Sallen-Key second-order band-pass filter (BPF) shown in Fig. 5.77.

142

5

C1

R2 C2

R1

Vin

Operational Amplifiers and Their Applications

Vtest

OA

R3

Vout

+ A→f

Fig. 5.78 A multiple feedback second-order BPF

Solution 5.71 Analysis of this topology is carried by the following two equations: V in - V test V - V out = test þ ðV test - V out ÞsC 1 þ V test sC 2 R1 R2 ðV test - V out ÞsC1 =

V out 1 ) V test = V out 1 þ sC1 R3 R3

ð5:173aÞ ð5:173bÞ

From above equations, the following TF is calculated: H ðsÞ =

sC 1 R2 R3 V out = 2 V in s C1 C2 R1 R2 R3 þ sðC 1 R1 R2 þ C2 R1 R2 þ C 1 R2 R3 Þ þ R1 þ R2 ð5:174Þ

From equation in (5.174), ω0 and Q are, respectively, computed as ω20 =

R1 þ R2 ) ω0 = C 1 C 2 R1 R2 R3

R1 þ R2 C 1 C 2 R1 R2 R3

ðR1 þ R2 ÞC1 C 2 R1 R2 R3 ω0 C1 R1 R2 þ C 2 R1 R2 þ C1 R2 R3 = ) Q= C1 R1 R2 þ C 2 R1 R2 þ C1 R2 R3 Q C1 C2 R1 R2 R3

ð5:175aÞ ð5:175bÞ

Example 5.72 Find the TF of the multiple feedback second-order BPF depicted in Fig. 5.78. Solution 5.72 Analysis of this circuit is accomplished by the following two equations: V V in - V test = ðV test - V out ÞsC 1 þ V test sC 2 þ test R1 R3

ð5:176aÞ

5.13

Analog Filters

143

C1 Vin

R2 C2

R1

-

Vtest

OA

Vout

+ A→f Fig. 5.79 Deliyannis second-order BPF

V test sC 2 = -

V out V ) V test = - out R2 sC 2 R2

ð5:176bÞ

From above equations, the following TF is found: H ðsÞ =

sC2 R2 R3 V out =- 2 V in s C 1 C 2 R1 R2 R3 þ sðC1 þ C2 ÞR1 R3 þ R1 þ R3

ð5:177Þ

Here, ω0 and Q are, respectively, found below. ω20 =

R1 þ R3 ) ω0 = C 1 C 2 R1 R2 R3

1 ω0 C 1 þ C 2 ) Q= = Q C1 C2 R2 C1 þ C2

R1 þ R3 C 1 C 2 R1 R2 R3

ð5:178aÞ

ðR1 þ R3 ÞC 1 C 2 R2 R1 R3

ð5:178bÞ

Example 5.73 Find the TF of the Deliyannis second-order BPF demonstrated in Fig. 5.79. Solution 5.73 Analysis of this structure is achieved by the following two equations: V in - V test = ðV test - V out ÞsC1 þ V test sC 2 R1 V test sC 2 = -

V out V ) V test = - out R2 sC 2 R2

ð5:179aÞ ð5:179bÞ

From above equations, the following TF is evaluated: H ðsÞ =

V out sC 2 R2 =- 2 V in s C 1 C 2 R1 R2 þ sðC 1 þ C 2 ÞR1 þ 1

where ω0 and Q are, respectively, found by

ð5:180Þ

144

5

ω20 =

Operational Amplifiers and Their Applications

1 ) ω0 = C 1 C 2 R1 R2

1 C 1 C 2 R1 R2

ω0 C 1 þ C 2 1 ) Q= = Q C 1 C 2 R2 C1 þ C2

5.14

ð5:181aÞ

C 1 C 2 R2 R1

ð5:181bÞ

Large Signal Operation in the OA

If LM318/NS type OA is supplied with ±12 V, output voltage (Vout) of this OA is generally less than 9 V and greater than -9 V. In other words, Vout is restricted with ±9 V. These restricted voltages are called as rated voltages that are defined below. V rþ ffi 9 V < V CC

ð5:182aÞ

V r - ffi - 9 V > V EE

ð5:182bÞ

Output current (Iout) of any OA cannot exceed Iout,max. For example, LM318/NS type OA has Iout,max ffi 21 mA. Iout, for LM318/NS OA is found as jI out j ≤ I out, max ffi 21 mA

ð5:183Þ

Example 5.74 Find vout(t) and iout(t) in Fig. 5.80 if Vr ffi ±9 V and vin(t) = (1 V)sin (ωt) are taken.

Fig. 5.80 A non-inverting amplifier with a load

VCC vin(t)

+ OA

iout(t)

vout(t)

VEE R2=10 k: R1=2 k:

RL=0.5 k:

5.15

SR

145

Solution 5.74 vout(t) and iout(t) are, respectively, computed as vout ðt Þ = 1 þ iout ðtÞ =

10 sinðωt Þ = 6 sinðωt Þ 2

6 6 sin ðωtÞ = 12:5ðmAÞsinðωtÞ þ 12k 0:5k

ð5:184aÞ ð5:184bÞ

Example 5.75 Find vout(t) in Fig. 5.80 if Vr ffi ±9 V and vin(t) = (2 V)sin(ωt) are chosen. Solution 5.75 vout(t) is calculated by vout ðtÞ = 1 þ

10 × 2sin ðωtÞ = 12sin ðωtÞ 2

ð5:185Þ

However, in Eq. (5.185), vout(t) is limited at about ±9 V as shown in Fig. 5.81. iout(t) of Example 5.75 is drawn in Fig. 5.81. In addition, f = 10 kHz is taken, where LM318/NS OA model is used.

5.15

SR

SR is a nonlinear distortion [4]. SR occurs at high frequencies and is defined as follows: SR =

dvout ðtÞ dt

max

ð5:186Þ

Unit of the SR is V/μs. In order to express SR, an input voltage depicted in Fig. 5.82 (a pulse) is applied to the VF in Fig. 5.83, where VI is sufficiently high. SR is found from slope of vout(t) in Fig. 5.82. Example 5.76 Find vout(t), if vin(t) = VIu(t) is applied to the input of the VF shown in Fig. 5.83 and VI is sufficiently small (ωtVI ≤ SR). Solution 5.76 vout(t) is evaluated as follows [3, 4]: From equation given in (5.59), output voltage, vout(t) of the VF of Fig. 5.83 in s domain is found as V out ðsÞ =

A0 1 1 V in ðsÞ ffi s s V in ðsÞ 1 þ 1 þ A0 1 þ ωb ð1þA ωt Þ 0

Input voltage, vin(t) in s domain is calculated by

ð5:187Þ

146

5

Operational Amplifiers and Their Applications

Fig. 5.81 vin(t), vout(t), and iout(t) of Example 5.75

V in ðsÞ =

VI s

ð5:188Þ

From equations denoted in (5.187) and (5.188), vout(t) of the VF of Fig. 5.83 in s domain is found as follows:

5.15

SR

147

vin(t)

Fig. 5.82 Input and output voltages of the VF

vout(t)

VI -SR

SR

t

Fig. 5.83 A VF given to test SR

vin (t)

+ OA

vout (t)

-

V out ðsÞ =

1 V V VI × I = I 1 þ ωst s s s þ ωt

ð5:189Þ

From above equation, vout(t) of the VF of Fig. 5.83 is computed as vout ðt Þ = V I ð1 - e - tωt Þ

ð5:190Þ

Here, ωt = 2πft is calculated in Eq. (5.78). tr, namely, rise time, is defined as the time of vout(t) to reach from 10% to 90%. Furthermore, tr is computed by tr =

1 lnð9Þ ωt

ð5:191Þ

Above equation is obtained as follows: 0:1 × V I = V I ð1 - e - t1 ωt Þ ) t 1 =

1 1 ln ωt 0:9

ð5:192aÞ

1 lnð10Þ ωt

ð5:192bÞ

0:9 × V I = V I ð1 - e - t2 ωt Þ ) t 2 = tr = t2 - t1 =

1 1 lnð10 × 0:9Þ = lnð9Þ ωt ωt

ð5:192cÞ

Otherwise, for ωtVI > SR, tr is calculated as below. tr =

V VI × ð0:9 - 0:1Þ = I × 0:8 SR SR

ð5:193Þ

In Fig. 5.84, input and output voltages of the VF at various frequencies are given in which input voltage is taken as 5 V peak, and the LM318/NS OA model is utilized.

148

5

Operational Amplifiers and Their Applications

Fig. 5.84 Input and output voltages of the VF at various frequencies

Example 5.77 Find tr if the VF has SR = 107 V/s, ft = 10 MHz, and Vin(t) = 100 (mV)u(t). Solution 5.77 Firstly, the following condition is checked. ωt V I = 2π × 107 × 0:1 ffi 6:28 × 106 ≤ SR = 107

ð5:194Þ

From equation in (5.192c), tr is found by tr =

1 1 lnð9Þ = lnð9Þ ffi 35 ns ωt 2π × 107

ð5:195Þ

Example 5.78 Find tr if the VF has SR = 107 V/s, ft = 10 MHz, and VI = Vin(t) = 1 (V)u(t). Solution 5.78 Firstly, the following condition is checked. ωt V I = 2π × 107 × 1 ffi 6:28 × 107 > SR = 107

ð5:196Þ

From equation given in (5.193), tr is found as given below. tr =

1 VI × 0:8 = 7 × 0:8 = 80 ns SR 10

ð5:197Þ

5.16

5.16

Full-Power Bandwidth

149

Full-Power Bandwidth

Full-power bandwidth ( fM) is defined as the maximum frequency, where the OA provides an undesired AC output with the largest amplitude. Hence, fM for the VF can be expressed as in the following [3, 4]: fM =

1 SR 2π V out, max

ð5:198Þ

where Vout,max = min{Vr+, |Vr-|}. Operating frequency of any OA is given as [3, 4]. f ≤fM

V out, max V out

ð5:199Þ

where Vout ≤ Vout,max. Example 5.79 Find fM if the VF has SR = 107 V/s and Vout,max = 9 V, i.e., Vr+ = Vr- = 9 V. Solution 5.79 fM is calculated below. fM =

1 SR 107 = ffi 176:84 kHz 2π V out, max 2π × 9

ð5:200Þ

Example 5.80 Find the operating frequency if the VF has SR = 107 V/s, Vout, max = 9 V, Vout = 2 V, and fM ffi 176.84 kHz, i.e., Vr+ = -Vr- = 9 V. Solution 5.80 The operating frequency of the VF is evaluated as f ≤fM

V out, max 9 ffi 176:84 kHz ) f ≤ 795:77 kHz V out 2

ð5:201Þ

Example 5.81 Find SR and fM if the VF has Vout,max = 9 V, Vout = 5 V, and f ffi 1 MHz. In other words, Vr+ = -Vr- = 9 V. Solution 5.81 SR and fM are, respectively, found by SR = 2πf M V out, max = 2πfV out ) SR = 2π × 106 × 5 ffi 3:14 × 107 V=s fM =

SR π × 107 = ffi 555:56 kHz 2π × 9 2πV out, max

ð5:202aÞ ð5:202bÞ

Example 5.82 Find f3dB and fM if the non-inverting amplifier has Vout,max = 9 V, SR = 107 V/s, ft = 10 MHz, and 1 + R2/R1 = 100, i.e., Vr+ = -Vr- = 9 V.

150

5

Operational Amplifiers and Their Applications

Solution 5.82 f3dB and fM are, respectively, evaluated below. ft 10 MHz = = 100 kHz 100 1 þ RR21

ð5:203aÞ

SR 107 = ffi 176:84 kHz 2πV out, max 2π × 9

ð5:203bÞ

f 3dB = fM =

It is understood from above that if f ≤ fM is taken, Vout ≤ Vout,max. Also, Vin, max = 9 V/100 = 90 mV.

References 1. J.A. Svoboda, R.C. Dorf, Dorf’s Introduction to Electric Circuits, Global edition. (Wiley, 2018) 2. J.W. Nilsson, S. Riedel, Electric Circuits: Global Edition, 11th ed. (Pearson, 2018) 3. S. Franco, Design with Operational Amplifiers and Analog Integrated Circuits, 3rd ed. 4. A.S. Sedra, K.C. Smith, T.C. Carusone, V. Gaudet, Microelectronic Circuits, 8th edn. (Oxford University Press, New York, 2020) 5. K. Ogata, Modern Control Engineering, 5th edn. (Prentice Hall, Boston [etc.], 2010) ISBN-13: 9780136156734 6. R. Ford, F.E.J. Girling, Active filters and oscillators using simulated inductance. Electron. Lett. 2(2), 52 (1966) 7. K.R. Rao, S. Venkateswaran, Synthesis of inductors and gyrators with voltage-controlled voltage sources. Electron. Lett. 6(2), 29–30 (1970) 8. A.J. Prescott, Loss-compensated active gyrator using differential-input operational amplifiers. Electron. Lett. 7(2), 283–284 (1966) 9. http://www.chuacircuits.com/PDFs/AntoniouInductance-Simulation Circuit.pdf 10. B. Maundy, S.J. Gift, Active grounded inductor circuit. Int. J. Electron. 98(5), 555–567 (2011) 11. H.J. Orchard, A.N. Willson, New active-gyrator circuit. Electron. Lett. 13(10), 261–262 (1974) 12. P. Horowitz, W. Hill, The Art of Electronics, 2nd edn. (Cambridge University Press, Cambridge, 1989) ISBN 0-521-37095-7 13. N. Boutin, Two new single op-amp RC bridge-T oscillator circuits. IEE Proc. G (Electron. Circuit Syst.) 130(5), 222–224 (1983) 14. R. Genin, Realization of an all-pass transfer function using operational amplifiers. Proc. IEEE 56, 1746–1747 (1968) 15. R.E. Bach, Selecting RC values for active filters. Electronics 33, 82–85 (1960) 16. R.P. Sallen, E.L. Key, A practical method of designing RC active filters. IRE Trans. Circuit Theory 2(1), 74–85 (1955)

Chapter 6

Unity Gain Cells

6.1

Unity Gain Cells

Unity gain cells (UGCs), namely, current followers (CFs) and voltage followers (VFs), are main analog devices. They have been found wide application areas in the open literature [1–12].

6.2

CFs and Their Practices

CFs can be divided into four categories, plus-type single output CF (CF+), minus-type single output current follower (CF-), dual output CF (DO-CF), and multiple output CF (MO-CF). CF+ and CF- have two terminals, while DO-CF has three terminals. Also, DO-CF has both Z+ and Z- terminals. MO-CF has at least four terminals. Ideal model of the CF+ is given in Fig. 6.1, while the symbols of the CF+ are depicted in Fig. 6.2. The CF+ can be expressed with the following matrix equation: I Zþ VX

=

α 0

½I X ]

ð6:1Þ

Here, α is frequency-dependent nonideal gain and ideally equal to unity. Input and output impedances of the CF+ are ideally equal to zero and infinity, respectively. Therefore, the CF+ is suitable for current-mode (CM) circuits. Similarly, ideal model of the CF- is shown in Fig. 6.3, while the symbols of the CF- are demonstrated in Fig. 6.4. The CF- can be defined by the following matrix equation: The original version of the chapter has been revised. A correction to this chapter can be found at https://doi.org/10.1007/978-3-031-44966-6_10 © The Author(s), under exclusive license to Springer Nature Switzerland AG 2024, Corrected Publication 2024 E. Yuce, S. Minaei, Passive and Active Circuits by Example, https://doi.org/10.1007/978-3-031-44966-6_6

151

152

6

Fig. 6.1 Ideal model of the CF+

Unity Gain Cells

CF+

VX

IX

α IX

Fig. 6.2 The symbols of the CF+

VX

IX

VZ+

IZ+

CF

X

Z+

IZ+

VZ+

(a)

VX

IX

X

CF+

Z

IZ+

VZ+

(b)

Fig. 6.3 Ideal model of the CF-

VX

Fig. 6.4 The symbols of the CF-

CF-

IX

VX

IZ-

γI X

IX

X

CF

Z-

IZ-

VZ-

VZ-

(a)

VX

IX

X

CF-

Z

IZ-

VZ-

(b)

I Zþ VX

=

-γ 0

½I X ]

ð6:2Þ

where γ is frequency-dependent nonideal gain and ideally equal to unity. Note CF- has all the properties of the CF+ except current direction of the Z terminal.

6.2

CFs and Their Practices

Fig. 6.5 A simple VM circuit based on the CF+

153

Vin

X

CF+

Vout

Z

Z1 Z2

Fig. 6.6 A simple VM topology based on the CF-

Vin

X

CF-

Vout

Z

Z1 Z2

Example 6.1 Analyze the simple voltage-mode (VM) circuits in Figs. 6.5 and 6.6. Solution 6.1 The simple structures based on CF+ and CF- are, respectively, exhibited in Figs. 6.5 and 6.6. Analysis of the simple topology based on CF+ is carried out as follows: I Zþ = αI X

ð6:3aÞ

V in = IX Z1

ð6:3bÞ

V out = - I Zþ Z2

ð6:3cÞ

From above equations, the following transfer function (TF) is easily obtained: α

V in V V Z = - out ) H v = out = - α 2 Z1 Z2 V in Z1

ð6:4Þ

Ideally, TF in Eq. (6.4) turns to Hv =

V out Z =- 2 V in Z1

ð6:5Þ

Likewise, analysis of the simple topology based on CF- is achieved as I Z - = - γI X

ð6:6aÞ

154 Fig. 6.7 An inverting VM amplifier/attenuator

Vin

X

R1

CF+

6

Unity Gain Cells

Z

Vout R2

Fig. 6.8 A non-inverting VM amplifier/attenuator

Vin

X

CF-

Vout

Z

R1 R2

V in = IX Z1

ð6:6bÞ

V out = - IZ Z2

ð6:6cÞ

From above equations, the following TF is easily obtained: γ

V in V out V Z = ) H v = out = γ 2 Z1 Z2 V in Z1

ð6:7Þ

From above equation, TF ideally converts to Hv =

V out Z = 2 V in Z1

ð6:8Þ

By appropriate choice of the impedances, Z1 and Z2 given in Figs. 6.5 and 6.6, the following topologies are obtained. (a) In Fig. 6.7, an inverting VM amplifier/attenuator can be easily obtained by taking Z1 = R1 and Z2 = R2 of the circuit in Fig. 6.5. Thus, TF is evaluated as Hv =

V out R =- 2 V in R1

ð6:9Þ

(b) In Fig. 6.8, a non-inverting VM amplifier/attenuator can be easily obtained by taking Z1 = R1 and Z2 = R2 of the circuit in Fig. 6.6. Therefore, TF is evaluated by

6.2

CFs and Their Practices

155

Fig. 6.9 An inverting VM integrator

Vin

X

CF+

Vout

Z

R C

Fig. 6.10 A non-inverting VM integrator

Vin

X

CF-

Vout

Z

R C

Fig. 6.11 An inverting VM differentiator structure

Vin

X

CF+

Vout

Z

C R

Hv =

V out R = 2 V in R1

ð6:10Þ

(c) In Fig. 6.9, an inverting VM integrator can be easily obtained by taking Z1 = R1 and Z2 = 1/(sC) of the structure in Fig. 6.5. Hence, TF is calculated as Hv =

V out 1 =V in sCR

ð6:11Þ

(d) In Fig. 6.10, a non-inverting VM integrator circuit can be easily obtained by taking Z1 = R1 and Z2 = 1/(sC) of the structure in Fig. 6.6. As a result, TF is calculated by Hv =

V out 1 = V in sCR

ð6:12Þ

(e) In Fig. 6.11, an inverting VM differentiator circuit can be easily obtained by taking Z1 = 1/(sC) and Z2 = R of the structure in Fig. 6.5. Hence, TF is computed below.

156 Fig. 6.12 A non-inverting VM differentiator

Vin

X

CF-

6

Unity Gain Cells

Z

Vout

C R

Vin

CF+

X

Vout

Z

R1 R2

C

Fig. 6.13 An inverting first-order VM LPF Fig. 6.14 A non-inverting first-order VM LPF

Vin

X

CF-

Vout

Z

R1 C

Hv =

V out = - sCR V in

R2

ð6:13Þ

(f) In Fig. 6.12, a non-inverting VM differentiator topology can be easily obtained by taking Z1 = 1/(sC) and Z2 = R of the circuit in Fig. 6.6. Consequently, TF is computed by Hv =

V out = sCR V in

ð6:14Þ

(g) In Fig. 6.13, an inverting first-order VM low-pass filter (LPF) can be easily obtained by taking Z1 = R1 and Z2 = R2//(1/(sC)) of the structure in Fig. 6.5. Thus, TF is found below. Hv =

1 V out R =- 2 V in R1 sCR2 þ 1

ð6:15Þ

(h) In Fig. 6.14, a non-inverting first-order VM LPF can be easily obtained by

6.2

CFs and Their Practices

Fig. 6.15 An inverting first-order VM HPF

157

Vin

X

R1

CF+

Vout

Z

C R2

Fig. 6.16 A non-inverting first-order VM HPF

Vin

X

R1

CF-

Vout

Z

C R2

choosing Z1 = R1 and Z2 = R2//(1/(sC)) of the circuit of Fig. 6.6. Hence, TF is found as Hv =

1 V out R = 2 V in R1 sCR2 þ 1

ð6:16Þ

(i) In Fig. 6.15, an inverting first-order VM high-pass filter (HPF) can be easily obtained by taking Z1 = R1 + 1/(sC) and Z2 = R2 of the structure in Fig. 6.5. As a result, TF is computed below. Hv =

sCR1 V out R =- 2 V in R1 sCR1 þ 1

ð6:17Þ

(j) In Fig. 6.16, a non-inverting first-order VM HPF can be easily obtained by choosing the impedances Z1 = R1 + 1/(sC) and Z2 = R2 of the structure of Fig. 6.6. Thus, TF is calculated as Hv =

V out R sCR1 = 2 V in R1 sCR1 þ 1

ð6:18Þ

Example 6.2 Design a VM analog adder circuits based on a single output CF. Solution 6.2 CF+ and CF- based VM analog adders are, respectively, depicted in Figs. 6.17 and 6.18. Outputs of these circuits are, respectively, indicated below.

158 Fig. 6.17 An inverting VM analog adder based on the CF+

V1

X

CF+

6

Unity Gain Cells

Z

Vout

R1 V2

RT

R2 Vn Rn Fig. 6.18 A non-inverting VM analog adder based on the CF-

V1

X

CF-

Vout

Z

R1 V2

RT

R2 Vn Rn Fig. 6.19 An inverting first-order CM APF based on the CF+

C

Vtest

X

CF

Z+

R

Iin

Iout

n

V out = i=1 n

V out = i=1

RT V Ri i

RT V Ri i

ð6:19aÞ ð6:19bÞ

Example 6.3 Find TF of the inverting first-order current-mode (CM) all-pass filter (APF) shown in Fig. 6.19 [1]. Solution 6.3 Analysis of the inverting first-order CM APF based on the CF+ in Fig. 6.19 is performed as follows:

6.2

CFs and Their Practices

159

Fig. 6.20 A non-inverting first-order CM APF based on the CF+

R

X

CF

Z+

C Iin

Iout

Fig. 6.21 An inverting first-order VM APF based on the CF+

C

R1 Vin

X

R2

CF

Z+

1 1 and I out = V test sC R R 1 1 V test sC R × sC I out R R = = Hi = 1 1 I in V test sC þ R × sC þ R R ðsCR - 1Þ × ð- 1Þ × ð- 1Þ 1 - sCR = =1 þ sCR 1 þ sCR

Vout

I in = V test sC þ

ð6:20Þ

Example 6.4 Find TF of the non-inverting first-order CM APF depicted in Fig. 6.20, which is obtained from one given in [1] by RC-CR transformation. Solution 6.4 Analysis of the inverting first-order CM APF based on the CF+ in Fig. 6.20 is found below. H i ðsÞ =

I out 1 - sCR = I in 1 þ sCR

ð6:21Þ

Example 6.5 Find TF of the inverting first-order VM APF demonstrated in Fig. 6.21 [2]. Solution 6.5 TF of this topology is given below. Hv =

V out =V in

R1 R2

- 1 - sCR1 1 þ sCR1

ð6:22Þ

160 Fig. 6.22 An inverting first-order APF based on the CF+

6

Unity Gain Cells

Z+

Vout

C

Vin

CF

X

R1

R2

If R1 = 2R2 is taken, the circuit in Fig. 6.21 behaves like a CF+ based inverting firstorder VM APF. Analysis of the structure in Fig. 6.21 is achieved by using the following steps: V in 1 = ðV in - V out Þ sC þ R2 R1

ð6:23aÞ

R1 V in = ðV in - V out ÞðsCR1 þ 1Þ R2 ðsCR1 þ 1ÞV out = V in ðsCR1 þ 1Þ ðsCR1 þ 1ÞV out = V in sCR1 þ 1 ðsCR1 þ 1ÞV out = - V in V out =V in

R1 R2

R1 V in R2

ð6:23bÞ ð6:23cÞ

R1 × ð- 1Þ × ð- 1Þ R2

ð6:23dÞ

R1 - 1 - sCR1 R2

ð6:23eÞ

- 1 - sCR1 1 þ sCR1

ð6:23fÞ

Example 6.6 Find TF of the inverting first-order VM APF shown in Fig. 6.22 [2]. Solution 6.6 TF of this circuit is evaluated as Hv =

V out 1 - sCR1 = - R1 V in R2 þ sCR1

ð6:24Þ

If R1 = R2 is chosen, the topology in Fig. 6.22 behaves like a CF+ based inverting first-order VM APF. Analysis of the structure in Fig. 6.22 is accomplished by using the following steps:

6.2

CFs and Their Practices

161

Fig. 6.23 An inverting first-order VM APF based on the CF+

C

R2 Vin

X

R1

sCV in -

V out

Vout

ð6:25aÞ

V in V out = þ sCV out R1 R2

ð6:25bÞ

V in V out þ sCV out × R1 × R1 = R1 R2

V in ðsCR1 - 1Þ = V out V out

Z+

V in V out = R1 R2

ðV in - V out ÞsC sCV in -

CF

R1 þ sCR1 R2

R1 þ sCR1 = V in ðsCR1 - 1Þ × ð- 1Þ × ð- 1Þ R2

V 1 - sCR1 R1 þ sCR1 = - V in ð1 - sCR1 Þ ) out = - R1 R2 V in R2 þ sCR1

ð6:25cÞ ð6:25dÞ ð6:25eÞ ð6:25fÞ

Example 6.7 Find TF of the inverting first-order APF depicted in Fig. 6.23 [2]. Solution 6.7 TF of this circuit is computed as follows: Hv =

V out 1 - sCR1 = - 2R1 V in R2 þ sCR1

ð6:26Þ

If R2 = 2R1 is taken, the circuit in Fig. 6.23 behaves like a CF+ based inverting firstorder VM APF. Analysis of the structure in Fig. 6.23 is carried out by using the following steps: V V in V out þ = ðV in - V out ÞsC - out R1 R2 R2

ð6:27aÞ

V in 2V out þ = ðV in - V out ÞsC R1 R2

ð6:27bÞ

V 2V out þ V out sC = sCV in - in R2 R1

ð6:27cÞ

162

6

Unity Gain Cells

R1

Vin

X

R2

CF

Z+

Vout

C

Fig. 6.24 A non-inverting first-order VM APF based on the CF+

R1 ×

2 1 þ sC V out = R1 × sC V R2 R1 in

ð6:27dÞ

2R1 þ sCR1 V out = ðsCR1 - 1ÞV in R2

ð6:27eÞ

2R1 þ sCR1 V out = ð- 1Þ × ð- 1Þ × ðsCR1 - 1ÞV in R2

ð6:27fÞ

V 1 - sCR1 2R1 þ sCR1 V out = - ð1 - sCR1 ÞV in ) out = - 2R1 R2 V in R2 þ sCR1

ð6:27gÞ

Example 6.8 Find TF of the non-inverting first-order APF depicted in Fig. 6.24 [3]. Solution 6.8 TF of this structure is evaluated below. Hv =

1 - sC ðR1 - R2 Þ V out = 1 þ sCR2 V in

ð6:28Þ

If R1 = 2R2 is taken, the topology in Fig. 6.24 behaves like a CF+ based non-inverting first-order VM APF. Analysis of the structure in Fig. 6.24 is accomplished by using the following steps: V in V - V out = in 1 R1 R2 þ sC

ð6:29aÞ

V in sC V - V out V in × sC = = in 1 R1 × sC sCR2 þ 1 R2 þ sC

ð6:29bÞ

V in sC V - V out × R1 × R1 = in R1 sCR2 þ 1

ð6:29cÞ

V in sCR1 = V in - V out sCR2 þ 1

ð6:29dÞ

V in sCR1 sCR2 þ 1

ð6:29eÞ

V out = V in -

6.2

CFs and Their Practices

163

V2

X

CF

Z+

CF

X

(1)

R1

Vout

Z+

(2)

R3

V1

R2 Fig. 6.25 An IA implementation based on the two CF+s

VX

(2)

(1)

IX

X

CF

Z+

X

CF

Z+

IZ-

VZ-

Fig. 6.26 Realization of the CF- by using two CF+s Fig. 6.27 Symbol of the DO-CF

IZ+ Z+

VX

X

IX

VX

V out =

CF Z-

CF

Fig. 6.28 Ideal model of the DO-CF

IX

α IX

VZ+

IZ-

IZ+

γ IX

sCR2 þ 1 sCR1 1 þ sCR2 - sCR1 V V ) V out = V in sCR2 þ 1 sCR2 þ 1 in sCR2 þ 1 in

IZ-

VZ-

VZ+ VZ-

ð6:29fÞ

Example 6.9 Realize an instrumentation amplifier (IA) based on two CF+s. Solution 6.9 Realization of the IA is depicted in Fig. 6.25 [4], where R2 = R1 is taken. Therefore, output voltage of this IA is calculated by V out =

R3 ðV - V 1 Þ R1 2

ð6:30Þ

Example 6.10 Implement a CF- by using CF+s. Solution 6.10 Implementation of the CF- by using two CF+s is shown in Fig. 6.26. The electrical symbol of the DO-CF is demonstrated in Fig. 6.27, while ideal model

164

6

Fig. 6.29 Realization of the floating current source based on the DO-CF

Unity Gain Cells

Iout Z+

Vin

a

CF

X

R

Z-

Fig. 6.30 The symbol of the floating current source

Iout

b

a

Iout b

(1)

X

Iin

Z1

CF+

(2)

Vtest

Z2

X

R

Z1

Iout

CF+ Z2

C

Fig. 6.31 Non-inverting first-order CM APF

of the DO-CF is given in Fig. 6.28. This DO-CF can be defined by the following matrix equation: I Zþ IZ -

=

α - γ ½I X ]

ð6:31Þ

0

VX

Example 6.11 Design a floating current source based on the DO-CF. Solution 6.11 The floating current source can be implemented by using a voltage source, a resistor, and a DO-CF as depicted in Fig. 6.29. The symbol of this floating current source is shown in Fig. 6.30. The current, Iout, in Figs. 6.29 and 6.30 is evaluated as follows: I out =

V in R

ð6:32Þ

6.2

CFs and Their Practices

Vin

165

Zin

Z-

Z-

Iin

(1)

CF Z+

X

R1

(2)

Z-

CF

Vtest R2

X

C

Fig. 6.32 A positive lossless SGI

Example 6.12 Find the TF of the CM topology in Fig. 6.31 [5]. Solution 6.12 The circuit of Fig. 6.31 is analyzed as V test sC þ

1 - I in R = - I in ) V test = sCR þ 1 R

ð6:33Þ

From equation indicated in (6.33), output current, Iout is found by I out = - I in -

2V test 1 - sCR = I R 1 þ sCR in

ð6:34Þ

I out 1 - sCR = I in 1 þ sCR

ð6:35Þ

Hence, the TF is calculated below. H ðsÞ =

Example 6.13 Find the input impedance of the positive lossless simulated grounded inductor (SGI) in Fig. 6.32 [6]. Solution 6.13 The circuit given in Fig. 6.32 is analyzed with the two equations as given below. It is considered that the current flowing into the X terminal of the CF is equal to the current extracted from the Z- terminal of the same CF. I in =

- V test R2

V in V = - V test sC ) V test = - in R1 sCR1

ð6:36aÞ ð6:36bÞ

If Vtest in Eq. (6.36b) is replaced instead of equation denoted in (6.36a), the following input impedance is obtained:

166

6

I in =

6.3

Unity Gain Cells

V in V ) Z in = in = sCR1 R2 sCR1 R2 I in

ð6:37Þ

VFs and Their Applications

The symbol of the voltage follower (VF) is given in Fig. 6.33, while ideal model of the VF is depicted in Fig. 6.34. The VF can be defined by the following matrix equation: IY 0 = VX β

0 0

VY IX

ð6:38Þ

where β is frequency dependent nonideal voltage gain, which is ideally equal to unity. Note In Fig. 6.34, Rin is ideally equal to infinity. Example 6.14 Find the current TF of the VF-based simple circuit in Fig. 6.35. Solution 6.14 The analysis of the circuit in Fig. 6.35 is performed by using the following three equations: VX = VY

ð6:39aÞ

Fig. 6.33 The symbol of the VF

VY

Y

IY

Fig. 6.34 Ideal model of the VF

VF

X

IX

VX

VF VY

IY

Rin

+ V _ Y

IX

VX

6.3

VFs and Their Applications

167

Fig. 6.35 A simple CM topology based on the VF

VF

Y

X

Z2

Z1

Iin

Iout

Fig. 6.36 The VF-based second-order VM multifunction filter

Y

VF

(1)

Vo1

X

C2

R1 C1 X

Vi1

VF

Y

(2)

R2

Vo2 Vi2

I in =

VY Z1

ð6:39bÞ

I out =

VX Z2

ð6:39cÞ

From above equations, the following TF is obtained: I in Z 1 = I out Z 2 ) H i =

I out Z = 1 I in Z2

ð6:40Þ

So, various first-order current TFs based on the selection of Z1 and Z2 are obtained. Example 6.15 Find the voltage responses of the VF-based second-order multifunction filter in Fig. 6.36 [7]. Solution 6.15 The analysis of the circuit in Fig. 6.36 is performed by using the following two equations: ðV i1 - V o1 ÞsC1 =

V o1 - V o2 R1

ð6:41aÞ

ðV o1 - V o2 ÞsC 2 =

V o2 - V i2 R2

ð6:41bÞ

168

6

Unity Gain Cells

From equations denoted in (6.41), if Vi1 = 0 is chosen, the following LPF TF is found as follows: 1 V o1 = V i2 C 1 C 2 R1 R2 s2 þ C1 R1 s þ 1

ð6:42Þ

Similarly, if Vi2 = 0 is taken, the following HPF TF is evaluated by C1 C2 R1 R2 s2 V o2 = V i1 C 1 C 2 R1 R2 s2 þ C1 R1 s þ 1

6.4

ð6:43Þ

CF and VF-Based Circuits

In this section, CF and VF-based structures are treated with several examples. Example 6.16 Find the phase and magnitude of the impedance of the parallel lossy SGI in Fig. 6.37 [8]. Also, find the useful operating frequency range of this SGI. Solution 6.16 The analysis of the topology in Fig. 6.37 is achieved by using the following two equations: I in =

V in - V test V in þ R1 R2

ð6:44aÞ

V in = - sCV test R2

ð6:44bÞ

From equation indicated in (6.44b), Vtest is computed below. V test = -

V in sCR2

ð6:45Þ

If Vtest is replaced in Eq. (6.44a), Iin is calculated as

R1

Iin

Vin

R2

X

CF

Z+

Vtest

(1)

(2)

C

Zin Fig. 6.37 The UGC-based parallel lossy SGI

Y

VF

X

6.4

CF and VF-Based Circuits

I in =

169

V in V in þ sCR V 1 1 1 2 þ in = V in þ þ R1 R2 R1 R2 sCR1 R2

ð6:46Þ

From equation given in (6.46), the admittance of the structure in Fig. 6.37 is found as in the following: Y in =

I in 1 1 1 = þ þ V in R1 R2 sCR1 R2 1 1 = þ Req sLeq

ð6:47Þ

Here, Leq = CR1R2 and Req = R1//R2 = R1R2/(R1 + R2). In other words, the impedance in s domain is evaluated as Z in ðsÞ = ðsCR1 R2 Þ==R1 ==R2

ð6:48Þ

On the other hand, the impedance of the circuit of Fig. 6.37 in the frequency domain is found as Z in ðωÞ = ðjωCR1 R2 Þ==R1 ==R2

ð6:49Þ

The phase and magnitude of the impedance of the parallel lossy SGI in Fig. 6.37 are, respectively, computed by ∠Z in ðωÞ = jZ in ðωÞj =

π - tan - 1 ðωCðR1 þ R2 ÞÞ 2 ωCR1 R2 ðR1 ==R2 Þ ðωCR1 R2 Þ2 þ ðR1 ==R2 Þ2

ð6:50aÞ ð6:50bÞ

It is seen from above equations that if the following condition is met, the circuit in Fig. 6.37 operates as a lossless inductor. 1 R1 R2 > > ωCR1 R2 ) ≥ 10ωC R1 þ R2 R1 þ R2

ð6:51Þ

From equation in (6.51), the operating frequency range is found below. f≤

0:1 1 × 2π C ðR1 þ R2 Þ

ð6:52Þ

Example 6.17 Find the phase and magnitude of the impedance of parallel lossy SGI in Fig. 6.38 [9]. Also, find the useful operating frequency range of this SGI.

170

6

Unity Gain Cells

R1

Iin

Vin

Y

VF

X

X

R2

(1)

CF

Vtest

Z+

(2)

Y

VF

X

(3)

C

Zin Fig. 6.38 The UGC-based another parallel lossy SGI

Solution 6.17 The analysis of the topology in Fig. 6.38 is carried out by using the following two equations: V in - V test R1

ð6:53aÞ

V in = - sCV test R2

ð6:53bÞ

I in =

From equation indicated in (6.53b), Vtest is computed below. V test = -

V in sCR2

ð6:54Þ

If Vtest is replaced in Eq. (6.53a), Iin is computed by I in =

V in V in þ sCR 1 1 2 = V in þ R1 R1 sCR1 R2

ð6:55Þ

From equation given in (6.55), the admittance of the topology of Fig. 6.38 is found as Y in =

I in 1 1 = þ V in R1 sCR1 R2 1 1 = þ Req sLeq

ð6:56Þ

where Leq = CR1R2 and Req = R1. In other words, the impedance in s domain is computed below. Z in ðsÞ = ðsCR1 R2 Þ==R1

ð6:57Þ

On the other hand, the impedance of the circuit of Fig. 6.38 in the frequency domain is found as follows:

6.4

CF and VF-Based Circuits

171

Z-

CF

X

R1

(1)

Iin

Vin

Y

VF

X

X

R2

(2)

CF

Vtest

Z+

Y

(3)

VF

X

(4)

C

Zin Fig. 6.39 The UGC-based positive lossless SGI

Z in ðωÞ = ðjωCR1 R2 Þ==R1

ð6:58Þ

The phase and magnitude of the impedance of the another parallel lossy SGI in Fig. 6.38 are, respectively, calculated as ∠Z in ðωÞ = jZ in ðωÞj =

π - tan - 1 ðωCR2 Þ 2 ωCR21 R2 ðωCR1 R2 Þ2 þ R21

ð6:59aÞ ð6:59bÞ

It is observed from above equations that if the following condition is met, the circuit in Fig. 6.38 operates as a lossless inductor. R1 > > ωCR1 R2 )

1 1 > > ωC ) ≥ 10ωC R2 R2

ð6:60Þ

From equation in (6.60), the operating frequency range is found as follows: f≤

0:1 1 × 2π CR2

ð6:61Þ

Example 6.18 Find the impedance of the positive SGI in Fig. 6.39 [10]. Solution 6.18 The analysis of the topology in Fig. 6.39 is accomplished by using the following two equations: I in = -

V test R1

V in = - sCV test R2 From equation indicated in (6.62b), Vtest is evaluated as

ð6:62aÞ ð6:62bÞ

172

6

Unity Gain Cells

Z1

Iin

Vin

X

Z2

Zin

CF

Z-

Vtest

Y

(1)

VF

X

(2)

Z3

Fig. 6.40 The UGC-based negative lossless SGI

V test = -

V in sCR2

ð6:63Þ

If Vtest is replaced in Eq. (6.62a), Iin is computed as in the following: I in =

V in sCR2

R1

= V in

1 sCR1 R2

ð6:64Þ

From equation in (6.64), the impedance of the topology of Fig. 6.39 is calculated as Z in =

V in = sCR1 R2 = sLeq I in

ð6:65Þ

where Leq = CR1R2. Example 6.19 Find the impedance of the negative lossless SGI in Fig. 6.40 [11]. Solution 6.19 The analysis of the topology in Fig. 6.40 is carried out by using the following two equations: I in =

V in - V test Z1

ð6:66aÞ

V - V test V in = - in Z2 Z3

ð6:66bÞ

From equation indicated in (6.66b), Vin - Vtest is found below. V in - V test = - V in

Z3 Z2

ð6:67Þ

If Vin - Vtest in Eq. (6.67) is replaced in (6.66a), Iin is evaluated as I in =

- V in ZZ 32 Z = - V in 3 Z1 Z1Z2

From above equation, the impedance is computed as follows:

ð6:68Þ

6.4

CF and VF-Based Circuits

173

Z1

Iin

Vin

(2)

X

VF

Z+

Vtest

(3)

Y

VF

X

Z2

(1)

Y

CF

X

Zin

Z3

Fig. 6.41 The UGC-based positive lossless SGI

Z in =

Z1Z2 V in =I in Z3

ð6:69Þ

Here, if Z1 = R1, Z2 = R2, and Z3 = 1/(sC) are chosen, a negative lossless SGI is obtained. Example 6.20 Find the impedance of the positive lossless SGI in Fig. 6.41 [12]. Solution 6.20 The analysis of the topology in Fig. 6.41 is performed by using the following two equations: V in - V test Z1

ð6:70aÞ

V in V in - V test = Z2 Z3

ð6:70bÞ

I in =

From equation indicated in (6.70b), Vin - Vtest is found as follows: V in - V test = V in

Z3 Z2

ð6:71Þ

If Vin - Vtest in Eq. (6.71) is replaced in (6.70a), Iin is calculated by I in =

V in ZZ 32 Z = V in 3 Z1 Z1Z2

ð6:72Þ

From above equation, the impedance is computed below. Z in =

V in Z 1 Z 2 = I in Z3

ð6:73Þ

where if Z1 = R1, Z2 = R2, and Z3 = 1/(sC) are taken, a positive lossless SGI is obtained.

174

6

Unity Gain Cells

References 1. S. Maheshwari, A new current-mode current-controlled all-pass section. J. Circuit. Syst. Comput. 16(2), 181–189 (2007) 2. A. Toker, S. Ozcan, H. Kuntman, O. Cicekoglu, Supplementary all-pass sections with reduced number of passive elements using a single current conveyor. Int. J. Electron. 88(9), 969–976 (2001) 3. O. Cicekoglu, H. Kuntman, S. Berk, All-pass filters using a single current conveyor. Int. J. Electron. 86(8), 947–955 (1999) 4. L. Safari, G. Ferri, S. Minaei, V. Stornelli, Current-Mode Instrumentation Amplifiers (Springer, 2019) 5. L. Safari, S. Minaei, E. Yuce, CMOS first-order current-mode all-pass filter with electronic tuning capability and its applications. J. Circuit. Syst. Comput. (JCSC) 22(3), 17 (2013) 6. E. S. Erdoğan, Active Filter Design with Unity Gain Current Cells (MSc thesis, Bogazici University, 2004) 7. F. Yucel, E. Yuce, A new voltage mode multifunctional filter using only two voltage followers and a minimum number of passive elements. J. Circuit. Syst. Comput. (JCSC) 24(6), 16 (2015) 8. A. Fabre, O. Saaid, F. Wiest, C. Boucheron, Low power current-mode second-order bandpass IF filter. IEEE Trans. Circuit. Syst. II Analog Digital Sign. Process. 44(6), 436–446 (1997) 9. H. Alpaslan, E. Yuce, Current-mode biquadratic universal filter design with two terminal unity gain cells. Radioengineering 21(1), 304–311 (2012) 10. H. Alzaher, N. Tasadduq, CMOS digitally programmable inductance. In 2006 International conference on microelectronics (IEEE, 2006), pp. 138–141 11. A.U. Keskin, A. Toker, A NIC with impedance scaling properties using unity gain cells. Analog Integr. Circ. Sig. Process 41(1), 85–87 (2004) 12. H. Alpaslan, E. Yuce, New grounded inductor simulator using unity gain cells. Indian J. Pure Appl. Phys. 51(09), 651–656 (2013)

Chapter 7

Unity Gain Inverting Amplifiers and Negative Impedance Converters

7.1

Introduction

Unity gain inverting amplifiers (UGIAs) and negative impedance converters (NICs) are main analog devices. They have been found wide application realms in the related open literature [1–9].

7.2

UGIAs

The electrical symbol of the UGIA is depicted in Fig. 7.1, while ideal model of the UGIA is demonstrated in Fig. 7.2. The UGIA with nonideal voltage gain is expressed as follows: IY = VX

0 -β

0 0

VY IX

ð7:1Þ

Here, IX is an arbitrary current depending on the load connected the X terminal of the UGIA. β is frequency dependent nonideal voltage gain, ideally equal to unity. Also, Rin in Fig. 7.2 is ideally equal to infinity. Example 7.1 Design a simple current-mode (CM) circuit for realizing different transfer functions (TFs) based on the UGIA. Solution 7.1 The simple circuit based on the UGIA is shown in Fig. 7.3. Analysis of the simple topology is carried out as below. V X = - βV Y

© The Author(s), under exclusive license to Springer Nature Switzerland AG 2024 E. Yuce, S. Minaei, Passive and Active Circuits by Example, https://doi.org/10.1007/978-3-031-44966-6_7

ð7:2aÞ

175

176

7

Unity Gain Inverting Amplifiers and Negative Impedance Converters

Fig. 7.1 The electrical symbol of the UGIA

VY

-1

Y

IY

X

VX

IX

Fig. 7.2 Ideal model of the UGIA

VY

IY

Rin

Fig. 7.3 The CM simple circuit based on the UGIA Y

_ +

-1

Z1

Iin

IX

VY

VX

X

Z2

Iout

I in =

VY Z1

ð7:2bÞ

I out =

VX Z2

ð7:2cÞ

From above equations, the following CM TF is obtained: I in Z 1 =

- I out Z 2 I βZ ) H i = out = - 1 β I in Z2

ð7:3Þ

By selecting different elements for Z1 and Z2, various types of TFs can be obtained. Example 7.2 Design a VF by using the UGIAs. Solution 7.2 The VF realization by using two UGIAs is demonstrated in Fig. 7.4. Example 7.3 Find the TF of the first-order voltage-mode (VM) APF based on a single UGIA [1], which is given in Fig. 7.5.

7.2

UGIAs

VY

177

IY

Y

-1

Y

X

(1)

-1

X

IX

(2)

VX

Fig. 7.4 The VF implementation with two UGIAs Fig. 7.5 The first-order VM APF using a single UGIA

Vin

Y

-1

R

X

Vout

C

Fig. 7.6 Another first-order VM circuit employing a single UGIA

Vout R1

Vin

R2

Vtest

R

Y

-1

X

C

Solution 7.3 By applying the KVL for the circuit in Fig. 7.5, the following equation is obtained: - V in - V out = ðV out - V in ÞsC R

ð7:4Þ

Rearranging the equation denoted in (7.4), the equation given below is obtained. - V in - V out = ðV out - V in ÞsCR ) - V in þ V in sCR = V out þ V out sCR

ð7:5Þ

From above equation, TF of the VM APF is found as V in ð- 1 þ sCRÞ = V out ð1 þ sCRÞ )

V out - 1 þ sCR 1 - sCR = =V in 1 þ sCR 1 þ sCR

ð7:6Þ

Example 7.4 Find the TF of another first-order VM topology based on a single UGIA [2], which is depicted in Fig. 7.6.

178

7

Unity Gain Inverting Amplifiers and Negative Impedance Converters

Solution 7.4 By applying the KVL for the circuit in Fig. 7.6, the following equation is obtained: V in - V out V þ V test = out R1 R2

ð7:7Þ

Here, Vtest is evaluated as V test =

1 V 1 þ sCR in

ð7:8Þ

If R1 = 2R2 is taken for the equations indicated in (7.7), the following equation is obtained: V þ V test V - V out V in - V out = out ) in = V out þ V test 2R2 R2 2

ð7:9Þ

Rearrangement of the equation in (7.9), the equation given below is obtained. V in - V out V V in V V in = V out þ ) in = out þ V out 2 1 þ sCR 2 1 þ sCR 2

ð7:10Þ

Further arranging the equation in (7.10), the following equation is obtained as 1 2 V in

þ 12 sCRV in - V in 1 1 - sCR 1 3 =V = V out þ 1 = V out 1 þ sCR 2 1 þ sCR in 2 2

ð7:11Þ

Finally, the following first-order VM APF TF is found. 1 1 - sCR V out =V in 3 1 þ sCR

ð7:12Þ

Example 7.5 Find the TFs of the first-order CM topology based on a single UGIA [3], which is shown in Fig. 7.7. Also, R1 = R2 = R and C1 = C2 = C are chosen. Solution 7.5 Analysis of the first-order CM filter is accomplished by the following five equations: I in = V test sC þ

1 I in RI in ) V test = = R sC þ R1 sCR þ 1 I LP1 =

V test R

I HP1 = V test sC

ð7:13aÞ ð7:13bÞ ð7:13cÞ

7.3

NICs

179

Vtest

-1

Y

X

C1 Iin

R1

R2 IHP1

ILP2

ILP1

C2

IAP1

IHP2

IAP2 Fig. 7.7 The first-order CM structure consisting of a single UGIA

I LP2 = -

V test R

I HP2 = - sCV test

ð7:13dÞ ð7:13eÞ

From above equations, the following output currents are obtained: I LP1 =

1 I 1 þ sCR in

ð7:14aÞ

I HP1 =

sCR I 1 þ sCR in

ð7:14bÞ

I LP2 = -

1 I 1 þ sCR in

ð7:14cÞ

I HP2 = -

sCR I 1 þ sCR in

ð7:14dÞ

I AP1 = I HP1 þ I LP2 = I AP2 = I LP1 þ I HP2 =

7.3

1 - sCR I 1 þ sCR in

1 - sCR I 1 þ sCR in

ð7:14eÞ ð7:14fÞ

NICs

The symbol of the NIC is given in Fig. 7.8 [4]. NIC can be divided into two subcategories, current NIC (INIC) and voltage NIC (VNIC). The symbols of the INIC and VNIC are, respectively, shown in Figs. 7.9 and 7.10.

180

7

Unity Gain Inverting Amplifiers and Negative Impedance Converters

Fig. 7.8 The symbol of the NIC

V1

Fig. 7.9 The symbol of the INIC

I1

V1

Fig. 7.10 The symbol of the VNIC

I1

V1

I1

Fig. 7.11 The first-order VM circuit based on the INIC

NIC

2

1

INIC

2

1

VNIC

2

1

I2

I2

I2

V2

V2

V2

C

Vin

1

R1

INIC

Vout

2

R2

INIC and VNIC are, respectively, expressed by the following matrix equations: I2 1 = V1 0 I2 = V1

-1 0

0 1 0 -1

I1 V2

ð7:15aÞ I1 V2

ð7:15bÞ

Example 7.6 Find the TF of the first-order VM topology based on a single INIC [5], which is shown in Fig. 7.11. Solution 7.6 The topology of Fig. 7.11 is analyzed as in the following: ðV in - V out ÞsC V in sC -

V in - V out V = out R1 R2

V in V out V = - out þ V out sC R1 R2 R1

ð7:16aÞ ð7:16bÞ

7.3

NICs

181

Fig. 7.12 The negative grounded impedance based on a single INIC

Vin

Iin

1

INIC

Vin

2

Iin

Z(s)

Zin

R1 × V in sC -

1 1 1 þ sC = R1 × V out R2 R1 R1

V in ðsCR1 - 1Þ = V out ð- 1Þ × ð- 1Þ × V in ðsCR1 - 1Þ = V out

R1 - 1 þ sCR1 R2

ð7:16cÞ ð7:16dÞ

R1 - 1 þ sCR1 = R2 ð7:16eÞ

- V in ð1 - sCR1 Þ Thus, output voltage is found as V out = -

R1 R2

1 - sCR1 V in - 1 þ sCR1

ð7:17Þ

If R1 = 2R2 is taken, TF of the structure in Fig. 7.11 is computed as follows: V out = -

1 - sCR1 V 1 - sCR1 V ) out = 1 þ sCR1 in V in 1 þ sCR1

ð7:18Þ

Example 7.7 Find the input impedance of the circuit depicted in Fig. 7.12. Solution 7.7 After analysis of the topology of Fig. 7.12, the following input impedance is found as Z in =

- I in Z ðsÞ V in = = - Z ðs Þ I in I in

ð7:19Þ

Example 7.8 Find the input impedance of the structure in Fig. 7.13. Solution 7.8 After analysis of the circuit in Fig. 7.13, the following input impedance is found by

182

7

Vin

Iin

Unity Gain Inverting Amplifiers and Negative Impedance Converters

1

Z1

INIC

2

Z2

Zin

Fig. 7.13 A topology based on a single INIC Fig. 7.14 The positive parallel lossy SGI based on a single INIC

Vin

Iin

1

R

INIC

2

C

R

Zin C

Vin

1

Iin

INIC

R

2

R

Zin Fig. 7.15 The negative parallel lossy SGI based on a single INIC

Z in = Z 1 - Z 2

ð7:20Þ

If Z1 = R and Z2 = R//(1/(sC)) in Fig. 7.13 are taken, a positive parallel lossy simulated grounded inductor (SGI) in Fig. 7.14 is obtained. This parallel lossy SGI is expressed as [6] Z in = R== sCR2

ð7:21Þ

If Z1 = R//(1/(sC)) and Z2 = R in Fig. 7.13 are selected, a negative parallel lossy SGI in Fig. 7.15 is obtained. This negative parallel lossy SGI is expressed by [6]

7.3

NICs

Fig. 7.16 Another circuit based on a single INIC

183

Vin

1

Iin

INIC

2

Z2

Z1

Zin

Fig. 7.17 The positive series lossy SGI based on a single INIC

Vin

1

Iin

INIC

2

R R

C

Zin

Fig. 7.18 The negative series lossy SGI based on a single INIC

Vin

1

Iin

INIC

2

R

Zin

R

C

Z in = - R== - sCR2

ð7:22Þ

Example 7.9 Find the input impedance of the structure given in Fig. 7.16. Solution 7.9 After analysis of the circuit in Fig. 7.16, the following input impedance is found as given below. Z in = Z 1 ==ð- Z 2 Þ

ð7:23Þ

If Z1 = R and Z2 = R + 1/(sC) in Fig. 7.16 are chosen, a positive series lossy SGI in Fig. 7.17 is obtained. This series lossy SGI is expressed below [6]. Z in = sCR2 þ R

ð7:24Þ

If Z1 = R + 1/(sC) and Z2 = R in Fig. 7.16 are taken, a negative series lossy SGI in Fig. 7.18 is obtained. This series lossy SGI is expressed as [6]

184

7

Unity Gain Inverting Amplifiers and Negative Impedance Converters C

Vin

1

Iin

INIC

INIC

1

2

(1)

2

(2)

R

R

R

Zin Fig. 7.19 The positive lossless SGI based on two INICs

Vin

Iin

1

INIC

2

1

R

(1)

INIC

2

(2)

R

R

C

Zin

Fig. 7.20 Another positive lossless SGI based on two INICs

Z in = - sCR2 - R

ð7:25Þ

Example 7.10 Find the input impedance of the structure given in Figs. 7.19 and 7.20 [6]. Solution 7.10 Using the results given in the above examples, after analysis of the circuits in Figs. 7.19 and 7.20, the input impedance for both circuits is found below. Z in = sCR2 = sLeq

ð7:26Þ

where Leq = CR2. Example 7.11 Find the input impedance of the circuit given in Fig. 7.21 [7]. Solution 7.11 After analysis of the circuit in Fig. 7.21, the following input impedance is found by Z in ðsÞ =

sCR1 R2 þ R1 - R2 sC ðR2 - R1 Þ þ 4

ð7:27Þ

If R1 = R2 = R is taken, the input impedance of the topology turns to Z in ðsÞ = Here, Leq = CR2/4.

sCR2 = sLeq 4

ð7:28Þ

7.3

NICs

185

Fig. 7.21 A positive lossless SGI based on one INIC and one VNIC

Iin

Vin

Zin

2

INIC

1

R2

R1

1

VNIC 2

C

Vtest

Vtest V1

1

I1

Z1

INIC

I1

2

(1)

Z2

V2

1

I2

INIC

2

(2)

V2

I2

Fig. 7.22 The floating circuit based on two INICs

Example 7.12 Find the admittance matrix equation for the circuit exhibited in Fig. 7.22. Solution 7.12 The following equations can be written for the circuit in Fig. 7.22 to obtain the admittance matrix equation: I1 =

V 1 - V test Z1

ð7:29aÞ

I1 =

V 2 - V test Z2

ð7:29bÞ ð7:29cÞ

I2 = - I1

From above equations, the following admittance matrix equation is found as I1 I2

=

1 Z1 - Z2

1

-1

V1

-1

1

V2

ð7:30Þ

186

7

Unity Gain Inverting Amplifiers and Negative Impedance Converters

Fig. 7.23 Another floating circuit based on two INICs

V1

Ia V1

1

I1

INIC

2

(1)

Ib

Ia Z2

Z1

V2

1

I2

INIC

Fig. 7.24 A Wien oscillator based on one INIC

2

(2)

Ia

1

INIC

R1

V2

Vout

2

C2

R2

C1

Example 7.13 Find the admittance matrix equation for another topology in Fig. 7.23. Solution 7.13 The following equations can be written for the structure in Fig. 7.23 to obtain the admittance matrix equation: I1 = Ia þ Ib

ð7:31aÞ

I 2 = - ðI a þ I b Þ

ð7:31bÞ

Ia =

V2 - V1 Z2

ð7:31cÞ

Ib =

V1 - V2 Z1

ð7:31dÞ

From above equations, the following admittance matrix equation is evaluated as I1 I2

=

1 Z 1 ==ð- Z 2 Þ

1

-1

V1

-1

1

V2

ð7:32Þ

7.3

NICs

187

Fig. 7.25 A second-order VM universal filter based on one INIC and one VF

V1

V2

C1

Vout

Y VF X (2)

R1 R2

C2

2

INIC 1

(1)

Vtest R3

V3

Example 7.14 Find the characteristic equation (D(s)), osillation condition (OC), and osillation frequency (OF) of the Wien oscillator in Fig. 7.24 [8]. Solution 7.14 Analysis of the circuit in Fig. 7.24 is achieved as V out 1 = V out sC 2 þ R2 R1 þ sC1 1

ð7:33Þ

From above equation, D(s) is calculated by DðsÞ = s2 C 1 C 2 R1 R2 þ sðC 1 R1 þ C2 R2 - C 1 R2 Þ þ 1 = 0

ð7:34Þ

Therefore, OC and OF are, respectively, found as follows: C1 R2 ≥ C 1 R1 þ C2 R2 f0 =

1 2π

1 C1 C2 R1 R2

ð7:35aÞ ð7:35bÞ

Note VNIC is sometimes used instead of INIC or vice versa, because INIC changes the direction of current, while VNIC changes the polarity of the voltage. Example 7.15 Find the output voltage (Vout), resonance frequency ( f0), and quality factor (Q) of the universal filter in Fig. 7.25 [9].

188

7

Unity Gain Inverting Amplifiers and Negative Impedance Converters

Solution 7.15 Analysis of the circuit in Fig. 7.25 is carried out as in the following: ðV 1 - V out ÞsC 1 þ

V 2 - V out V - V test = out R1 R2

ð7:36aÞ

V test - V out V - V3 = test R2 R3

ð7:36bÞ

ðV out - V test ÞsC2 þ

From above two equations, if R2 = R3 = R are taken, output response, f0, and Q of the universal filter are, respectively, computed as V out =

s2 C1 C2 R1 R2 V 1 þ sC 2 R2 V 2 þ R1 V 3 s2 C 1 C 2 R1 R2 þ sC 2 R2 þ R1 f0 =

1 1 × p 2π R C 1 C 2

Q=

R1 × R

C1 C2

ð7:37aÞ ð7:37bÞ ð7:37cÞ

One sees from equations given in (7.37) that all the second-order VM filter responses can be easily obtained with appropriate choice of input voltage(s). Furthermore, Q of this filter can be changed by varying R1 without disturbing the resonance frequency f0.

References 1. A. Toker, S. Ozoguz, Tunable all pass filter for low voltage operation. Electron. Lett. 39(2), 175–176 (2003) 2. E. Yuce, S. Minaei, A novel phase shifter using two NMOS transistors and passive elements. Analog Integr. Circuit. Signal Process. (ALOG) 62, 77–81 (2010) 3. E. Yuce, S. Minaei, N. Herencsar, J. Koton, Realization of first-order current-mode filters with low number of MOS transistors. J. Circuit. Syst. Comput. (JCSC) 22(1), 14 (2013) 4. A.S. Sedra, K.C. Smith, A second-generation current conveyor and its applications. IEEE Trans. Circuit Theory 17(1), 132–134 (1970) 5. O. Cicekoglu, H. Kuntman, S. Berk, All-pass filters using a single current conveyor. Int. J. Electron. 86(8), 947–955 (1999) 6. T.S. Rathore, B.M. Singhi, A family of inductance simulation. JIE PT ET-2 61, 58–59 (1980) 7. E. Yuce, H. Alpaslan, S. Minaei, U.E. Ayten, A new simulated grounded inductor based on two NICs, two resistors and a grounded capacitor. Circuit. Syst. Signal Process. (CSSP) 40(12), 5847–5863 (2021) 8. S. Celma, P.A. Martinez, A. Carlosena, Approach to the synthesis of canonic RC-active oscillators using CCII. IEEE Proc. Circuits Devices Syst. 141(6), 493–497 (1994) 9. E. Yuce, S. Tez, A novel voltage-mode universal filter composed of two terminal active devices. Int. J. Electron. Commun. (AEU) 86, 202–209 (2018)

Chapter 8

Current Conveyors and Their Applications

8.1

Introduction

Current conveyors (CCs) have the property of higher linearity, wider bandwidth, larger dynamic range, etc. when compared to operational amplifiers [1–5]. Three generation CCs are available in the literature, first-generation CC (CCI) [6], secondgeneration CC (CCII) [7], and third-generation CC (CCIII) [8]. Other types of CCs such as subtractor connected CCI (S-CCI), current controlled CCII (CCCII), inverting CCII (ICCII), differential CC (DCCII), dual X CCII (DX-CCII), differential voltage CC (DVCC), differential difference CC (DDCC), fully differential CCII (FDCCII), current differencing CC (CDCC), extra X CCCII (EX-CCCII), etc. are also available in the literature.

8.2

CCI

Symbol of the dual-output CCI (DO-CCI) is shown in Fig. 8.1. If one of the Z- or Z + terminal of this DO-CCI is removed, plus-type CCI (CCI+) and minus-type CCI (CCI-) are, respectively, obtained. This DO-CCI is expressed in the matrix equation (8.1). VX IY I Zþ IZ -

=

1 0

0 1

VY

0

1

IX

0

-1

© The Author(s), under exclusive license to Springer Nature Switzerland AG 2024 E. Yuce, S. Minaei, Passive and Active Circuits by Example, https://doi.org/10.1007/978-3-031-44966-6_8

ð8:1Þ

189

190

8

Fig. 8.1 Symbol of the DO-CCI

VY

Current Conveyors and Their Applications

VX

Z+

Y

IY

DO-CCI X

IX

VZ+

IZ+

Z-

VZ-

IZ-

R/2

I1 C

Vin

Iin

R

Vtest

CCI I1

Vtest

Y Z+

X

I1

R

Zin Fig. 8.2 CCI+ based SGI

One of the most important applications of the CCs is found in realization of the simulated inductors (SIs) that can be lossy or lossless. SIs can be divided into two groups, simulated grounded inductor (SGI) and simulated floating inductor (SFI). Example 8.1 Find the input impedance of the SGI in Fig. 8.2 [9]. Solution 8.1 Its analysis is carried out by using the following four equations: I in =

V in - V test þ ðV in - V test ÞsC þ I 1 R V V in - V test = test þ I 1 R R 2V test ðV in - V test ÞsC = þ I1 R V Z in = in I in

ð8:2aÞ ð8:2bÞ ð8:2cÞ ð8:2dÞ

From equations indicated in (8.2), input impedance of the SGI in Fig. 8.2 is evaluated as Z in =

V in 1 = sCR2 3 I in

ð8:3Þ

8.2

CCI

191

R

I1

Vin

Iin

CCI I1

Zin

Vtest

Y

Z-

X

Y

I1

(1)

VF

X

(2)

C

R

Fig. 8.3 CCI- and VF-based SGI

Example 8.2 Find the input impedance of the SGI in Fig. 8.3 [10]. This SGI consists of one CCI and one voltage follower (VF). Solution 8.2 Its analysis is accomplished by using the following four equations: V in - V test þ I1 R V I 1 = - in R

ð8:4bÞ

I 1 = V test sC

ð8:4cÞ

I in =

Z in =

V in I in

ð8:4aÞ

ð8:4dÞ

From equations indicated in (8.4), input impedance of the SGI in Fig. 8.3 is evaluated as Z in =

V in = sCR2 I in

ð8:5Þ

Example 8.3 Find the input impedance of the SGI in Fig. 8.4 [10]. This SGI uses one CCI and one unity gain-inverting amplifier (UGIA). Solution 8.3 Its analysis is accomplished by using the following four equations: I in =

V in - ð- V test Þ þ I1 R V I 1 = - in R

ð8:6aÞ ð8:6bÞ

192

8

Current Conveyors and Their Applications

R

I1

Vin

Iin

Vtest

Y

CCI I1

Zin

X

Z+

Y

I1

(1)

-1

X

(2)

C

R

Fig. 8.4 CCI+ and UGIA-based SGI

R1

I1

Vo1

Vo2

Y

CCI C1

I1

X

Z-

(1)

I1

Y

VF

X

Vo2

(2)

C2

R2

Fig. 8.5 CCI- and VF-based QO

I 1 = - V test sC Z in =

V in I in

ð8:6cÞ ð8:6dÞ

From equations indicated in (8.6), input impedance of the SGI in Fig. 8.4 is calculated as Z in =

V in = sCR2 I in

ð8:7Þ

Example 8.4 Find the characteristic equation (D(s)), oscillation condition (OC), and oscillation frequency (OF) of the quadrature oscillator (QO) demonstrated in Fig. 8.5 [10].

8.3

CCII

193 R1

I1

Vo1

-Vo2

Y

CCI C1

I1

X

(1)

Z+

Y

I1

-1

Vo2

X

(2)

C2

R2

Fig. 8.6 CCI+ and UGIA-based QO

Solution 8.4 Its analysis is carried out by using the following three equations: V o2 - V o1 = V o1 sC 1 þ I 1 R1

ð8:8aÞ

V o1 R2

ð8:8bÞ

I 1 = V o2 sC 2

ð8:8cÞ

I1 = -

From equations indicated in (8.8), D(s) of the QO in Fig. 8.5 is calculated as DðsÞ = s2 C 1 C 2 R1 R2 þ sC 2 ðR2 - R1 Þ þ 1 = 0

ð8:9Þ

From equation denoted in (8.9), OC and OF are, respectively, found as follows: R1 ≥ R2 f0 =

1 1 ×p 2π C1 C2 R1 R2

ð8:10aÞ ð8:10bÞ

If the analysis of the QO in Fig. 8.6 is achieved [10], the same D(s) value evaluated for the circuit in Fig. 8.5 is found.

8.3

CCII

Symbol of the dual-output CCII (DO-CCII) is exhibited in Fig. 8.7. If one of the Zor Z+ terminal of this DO-CCII is removed, plus-type CCII (CCII+) and minus-type CCII (CCII-) are, respectively, obtained. This DO-CCII is defined in the matrix equation (8.11).

194

8

VY

Fig. 8.7 Symbol of the DO-CCII

Y

IY

VX

Fig. 8.8 INIC design based on the CCII

Current Conveyors and Their Applications Z+

DO-CCII Z-

X

IX

IZ-

VZ+ VZ-

Z+

V1

X

I1

CCII

VY

I2

Y

Fig. 8.9 VF design based on the CCII

IY

Y

CCII

X

Z-

Z+

Fig. 8.10 CF design based on the CCII

Z+

VX

VX IY I Zþ IZ -

8.3.1

IZ+

=

IX

1 0

0 0

0 0

1 -1

X

CCII Y

Z-

VY IX

IX

IZ+ IZ-

V2

VX

VZ+ VZ-

ð8:11Þ

Realizations of the Other Active Devices Based on the CCII

Example 8.5 Implement the current negative impedance converter (INIC), VF, and current follower (CF) by utilizing the CCII. Solution 8.5 The INIC, VF, and CF implementations based on the CCII are, respectively, demonstrated in Figs. 8.8, 8.9, and 8.10.

8.3

CCII

8.3.2

195

Realizations of the Instrumentation Amplifier Based on the CCII

Example 8.6 Find the output voltage of the instrumentation amplifier (IA) in Fig. 8.11 [11]. Solution 8.6 Analysis of the IA in Fig. 8.11 is carried out by V out =

R2 ðV - V 1 Þ = A v ðV 2 - V 1 Þ R1 2

ð8:12Þ

Here, Av = R2/R1.

8.3.3

Realizations of the Simulated Inductors Based on the CCII

Example 8.7 Find the input impedance of the SGI designs in Figs. 8.12 [12] and 8.13 [13]. Solution 8.7 Analysis of the SGIs in Fig. 8.12 and 8.13 is achieved by the following two equations: I in =

V test R1

ð8:13aÞ

V in V = V test sC ) V test = in R2 sCR2

ð8:13bÞ

If Vtest in Eq. (8.13b) is replaced into Eq. (8.13a), the following input current is obtained as

Fig. 8.11 IA realization based on the CCII

V2

Y

(1)

CCII

Vout

Z+

X

R2 R1 V1

Y

X

CCII (2)

Z+

196

8

Current Conveyors and Their Applications

Fig. 8.12 The SGI realization based on the CCII

X Z-

(1)

Vin

R1

CCII Y

Vtest

Iin

C

Z+ Y

Zin

Fig. 8.13 Another SGI implementation based on the CCII

CCII (2)

Vin

X

X

Iin

R2

(1)

CCII Y

Z-

Zin

Vtest

Y

(2)

Z+

CCII X

R1

R2 C

V in

I in =

V test V in = sCR2 = R1 R1 sCR1 R2

ð8:14Þ

From above equation, input impedance of the SGIs in Figs. 8.12 and 8.13 is found as Z in =

V in = sCR1 R2 = sLeq I in

ð8:15Þ

where Leq = CR1R2. Example 8.8 Find the admittance matrix equation of the SFI shown in Fig. 8.14 [14]. Solution 8.8 Analysis of the SFI in Fig. 8.14 is accomplished by the following three equations:

8.3

CCII

197 X

V1

I1

Z+

(1)

X

R1

CCII

CCII

Y

Y

Vtest C

CCII (3)

I2

V2

Z+

Z+

Y

Z+

(2)

X

CCII X

R2

Y

(4)

Fig. 8.14 The SFI implementation based on the CCII

I2 = - I1

ð8:16aÞ

V test R1

ð8:16bÞ

I1 = V test sC =

V1 - V2 V - V2 ) V test = 1 R2 sCR2

ð8:16cÞ

If Vtest in Eq. (8.16c) is replaced into equation denoted in (8.16b), the currents I1 and I2 are, respectively, obtained as follows: I1 =

V1 - V2 sCR1 R2

I2 = -

ð8:17aÞ

V1 - V2 sCR1 R2

ð8:17bÞ

Hence, the SFI of Fig. 8.14 is expressed by the following matrix equation: I1 1 = s C R I2 1 R2

1 -1

-1 1

V1 1 = s L V2 eq

1 -1

-1 1

V1 V2

ð8:18Þ

Here, Leq = CR1R2. Example 8.9 Find the admittance matrix equation of the SFI in Fig. 8.15 [15]. Solution 8.9 Analysis of the SFI in Fig. 8.15 is accomplished by the following three equations: I2 = - I1 I1 = -

V test R2

ð8:19aÞ ð8:19bÞ

198

Current Conveyors and Their Applications

8

R2

V1

I1

X

R1

X

Z-

Vtest

CCII (1)

Y

Z+

Z+

CCII Y

(2)

Z-

C

V2

I2

Fig. 8.15 The SFI based on the CCII

R1

Z+

(1)

C1

Y

Vo2

Z-

CCII

Vo1

X

C2

(2)

Z+

CCII Y

Z-

Io1 Io2

X

R2

Fig. 8.16 The QO based on the CCII

V test sC = -

V1 - V2 V - V2 ) V test = - 1 R1 sCR1

ð8:19cÞ

If Vtest in Eq. (8.19c) is replaced into equation denoted in (8.19b), the same currents I1 and I2 are obtained as given for the SFI in Fig. 8.14.

8.3

CCII

8.3.4

199

Realizations of the QOs Based on the CCII

Example 8.10 Find D(s), OC, and OF of the QO in Fig. 8.16 [16]. Solution 8.10 Analysis of the QO in Fig. 8.16 is accomplished by the following two equations: V o1 = - V o2 sC 2 ) V o1 = - V o2 sC 2 R2 R2 V V R V o2 - V o1 = V o1 sC 1 - o1 ) V o2 - V o1 = V o1 sC 1 R1 - o1 1 R1 R2 R2

ð8:20aÞ ð8:20bÞ

If Vo1 in Eq. (8.20a) is replaced into equation denoted in (8.20b), the following equation is obtained by V o2 þ V o2 sC 2 R2 = - V o2 s2 C 1 C 2 R1 R2 þ V o2 sC 2 R1

ð8:21Þ

Rearrangement of equation given in (8.21), the following equation is obtained as V o2 s2 C1 C2 R1 R2 þ sC 2 R2 - sC 2 R1 þ 1 = 0

ð8:22Þ

From above equation, D(s), OC, and OF are, respectively, found as DðsÞ = s2 C 1 C 2 R1 R2 þ sC 2 ðR2 - R1 Þ þ 1 = 0

ð8:23aÞ

R1 ≥ R2

ð8:23bÞ

f0 =

1 1 ×p 2π C1 C2 R1 R2

ð8:23cÞ

The output voltage, Vo1, is expressed in terms of Vo2 as V o1 = - jωC2 R2 V o2

ð8:24Þ

The currents of the QO, Io1 and Io2, are also defined as I o1 = - I o2 =

V o2 - V o1 R1

ð8:25Þ

Example 8.11 Find the D(s), OC, and OF of the QO in Fig. 8.17 [17]. Solution 8.11 Analysis of the QO in Fig. 8.17 is achieved by the following two equations:

200

8

Fig. 8.17 The QO based on the CCII

C1

Current Conveyors and Their Applications

R2

R1

Vo1

X

Y

R3

C2 Z+

CCII (1)

Y

Vo2

X

CCII (2)

Z+

R4 Y

X

CCII Z+

(3)

V o1 = V o2 sC 2 R2

ð8:26aÞ

V V o1 V o2 = V o1 sC 1 þ o1 R4 R3 R1

ð8:26bÞ

From above equations, D(s), OC, and OF are, respectively, found as follows: DðsÞ = s2 C1 C2 R2 R3 þ sC 2 R2 R3

1 1 R1 R4

þ 1=0

R1 ≥ R4 f0 =

8.3.5

1 1 ×p 2π C1 C2 R2 R3

ð8:27aÞ ð8:27bÞ ð8:27cÞ

Realizations of the CCII- Based on the CCII+s

Example 8.12 Implement the CCII- by using the CCII+s. Solution 8.12 Implementation of the CCII- by using two CCII+s is depicted in Fig. 8.18.

8.4

CCIII

VX VY

201

IX

X

IY

(1)

CCII

(2) Z+

CCII

X

Y

Z+

VZ-

IZ-

Y

Fig. 8.18 Realization of the CCII- by utilizing two CCII+s Fig. 8.19 Symbol of the DO-CCIII

VY

Y

IY

VX

Z+

CCIII Z-

X

IX

VZ+

IZ+

VZ-

IZC

Fig. 8.20 Series RL circuit based on the CCIII+ I1

Vin

Iin

Y

CCIII I1

Zin

X

Vtest Z+

I1

R2 R1

8.4

CCIII

Symbol of the dual-output CCIII (DO-CCIII) is demonstrated in Fig. 8.19. If one of the Z- or Z+ terminal of this DO-CCIII is removed, plus-type CCIII (CCIII+) and minus-type CCIII (CCIII-) are, respectively, obtained. This DO-CCIII is defined in the matrix equation (8.28). VX IY I Zþ IZ -

=

1

0

0 0

-1 1

0

-1

VY IX

ð8:28Þ

Example 8.13 Find the input impedance of the series lossy inductor in Fig. 8.20 [18].

202

8

Current Conveyors and Their Applications C

Fig. 8.21 Parallel RL circuit based on the CCIII+ I1

Vin

Iin

Vtest

X

CCIII I1

Y

Zin

Z+

I1

R2 R1

Solution 8.13 The input impedance of the series lossy inductor in Fig. 8.20 is computed with the following four equations: Z in =

V in I in

ð8:29aÞ

I in = - I 1 þ ðV in - V test ÞsC I1 = -

V in V test - V in þ R1 R2

I 1 = ðV in - V test ÞsC þ

V in - V test R2

ð8:29bÞ ð8:29cÞ ð8:29dÞ

From above equations, the input impedance of the series lossy inductor in Fig. 8.20 is evaluated as Z in =

V in = sCR1 R2 þ 2R1 = sLeq þ Req I in

ð8:30Þ

Here, Leq = CR1R2 and Req = 2R1. Example 8.14 Find the input admittance of the parallel lossy inductor in Fig. 8.21 [18]. Solution 8.14 The input admittance of the parallel lossy inductor in Fig. 8.20 is calculated with the following four equations: Y in =

I in V in

I in = I 1 þ ðV in - V test ÞsC

ð8:31aÞ ð8:31bÞ

8.5

CCCII

203

I1 =

V in V in - V test þ R1 R2

I 1 = ðV in - V test ÞsC þ

ð8:31cÞ

V in - V test R2

ð8:31dÞ

From above equations, the input admittance of the parallel lossy inductor in Fig. 8.21 is found below. Y in =

I in 1 2 1 1 = þ = þ V in sCR1 R2 R1 sLeq Req

ð8:32Þ

where Leq = CR1R2 and Req = R1/2.

8.5

CCCII

Symbol of the dual-output CCCII (DO-CCCII) is exhibited in Fig. 8.22. If one of the Z- or Z+ terminal of this DO-CCCII is removed, plus-type CCCII (CCCII+) and minus-type CCCII (CCCII-) are respectively obtained. This DO-CCCII is defined in the matrix equation (8.33), where RX = VT/(2Io) and VT ffi 26 mV at room temperature [19]. VX IY

=

IZ I Zþ

1 0

RX 0

0 -1 0 1

VY

ð8:33Þ

IX

Example 8.15 Find the input impedance of the SGI in Fig. 8.23 [12]. This SGI is obtained by removing both resistors of one in Fig. 8.12 [12]. Solution 8.15 According to the solution given in Example 8.7 (for circuit of Fig. 8.12), the input impedance of the SGI in Fig. 8.23 is evaluated as

Fig. 8.22 Symbol of the DO-CCCII

VY VX

Y

IY RX

IX

Z+

DO-CCCII Z-

X

Io

IZ+ IZ-

VZ+ VZ-

204

8

Current Conveyors and Their Applications

Fig. 8.23 The SGI based on the CCCII

X

CCCII

Z-

(1)

Vin

Y

Io1

Iin

C Z+

CCCII

Y

Zin

(2)

X

Io2

Fig. 8.24 Symbol of the DO-ICCII

VY VX

Z in =

IY IX

Y

Z+

DO-ICCII X

V in = sCRX1 RX2 = sLeq I in

Z-

IZ+

IZ-

VZ+ VZ-

ð8:34Þ

Here, Leq = CRX1RX2.

8.6

ICCII

Symbol of the dual-output ICCII (DO-ICCII) is demonstrated in Fig. 8.24. If one of the Z- or Z+ terminal of this DO-ICCII is removed, plus-type ICCII (ICCII+) and minus-type ICCII (ICCII-) are respectively obtained. This DO-ICCII is defined in the matrix equation (8.35). VX IY I Zþ IZ -

=

-1 0

0 0

0 0

1 -1

VY IX

ð8:35Þ

Example 8.16 Find the transfer functions (TFs) of the first-order current-mode (CM) universal filter in Fig. 8.25 [20].

8.6

ICCII

205

C

Fig. 8.25 The DO-ICCIIbased first-order CM universal filter

Iin

Vtest Z-

Y

ILP

ICCII

R X

Z+

IAP

Solution 8.16 The input current of the universal filter of Fig. 8.25 is expressed as I in =

2V test þ V test × sC R

ð8:36Þ

From above equation, Vtest is found as follows: V test =

RI in 2 þ sCR

ð8:37Þ

The first-order low-pass filter (LPF) response by using the equation denoted in (8.37) is evaluated by I LP =

2V test 2I in = R 2 þ sCR

ð8:38Þ

From above equation, TF of the LPF is computed as I LP 1 = I in 1 þ 0:5sCR

ð8:39Þ

TF of the first-order CM all-pass filter (APF) is calculated as follows: I AP 1 - 0:5sCR =I in 1 þ 0:5sCR

ð8:40Þ

From equations indicated in (8.39) and (8.40), the angular pole frequency is calculated as ω0 = 1/(0.5RC). The phase angle is also evaluated as ∠ðI AP =I in Þ = 180o - 2 tan - 1 ð0:5ωCRÞ

ð8:41Þ

By interconnection of low-pass and all-pass currents in Fig. 8.25, a first-order highpass current is easily obtained. Thus, the TF of the high-pass filter is found as

206

8

Current Conveyors and Their Applications

0:5sCR I HP = 1 þ 0:5sCR I in

8.7

ð8:42Þ

DCCII

Symbol of the dual-output DCCII (DO-DCCII) is demonstrated in Fig. 8.26. If one of the Z- or Z+ terminal of this DO-DCCII is removed, plus-type DCCII (DCCII+) and minus-type DCCII (DCCII-) are respectively obtained. This DO-DCCII is defined in the matrix equation (8.43). V XP

1

0

0

V XN IY

1 = 0

0 0

0 0

VY I XP

I Zþ IZ -

0 0

1 -1

-1 1

I XN

ð8:43Þ

Example 8.17 Find the input impedance of the SGI in Fig. 8.27 [21]. Solution 8.17 The input impedance of the SGI of Fig. 8.27 is evaluated by using the following seven equations: Z in =

VY VXN VXP

IY IXN

IXP

ð8:44aÞ

I Zþ = I XP - I XN

ð8:44bÞ

I Z - = I XN - I XP

ð8:44cÞ

V Y sC = - I Zþ

ð8:44dÞ

Y XN

V in I in

Z+

DO-DCCII

XP

Fig. 8.26 The symbol of the DO-DCCII

Z-

IZ+

IZ-

VZ+

VZ-

8.7

DCCII

207

Fig. 8.27 The DO-DCCIIbased SGI C

Y

IXN R2

XN

IXP

Z+

DO-DCCII Z-

XP

IZ+ IZ-

Iin

Vin

R1

Zin VY VXN

VXP

IY IXN IXP

Y

XN

ZP+

DXCCII ZN-

XP

IZP+

IZN-

VZP+

VZN-

Fig. 8.28 The symbol of the DXCCII

I XN = I in = I Z - þ I XP =

VY R2

V in - V Y R1

V in - V Y R1

ð8:44eÞ ð8:44fÞ ð8:44gÞ

From above equations, input impedance is calculated as Z in =

V in = sCR1 R2 þ R1 - R2 = sLeq þ Req I in

ð8:45Þ

Here, Leq = CR1R2 and Req = R1 - R2. If R1 = R2 in Fig. 8.27 is chosen, a positive lossless SGI is obtained.

208

8.8

8

Current Conveyors and Their Applications

DXCCII

Symbol of the DXCCII is exhibited in Fig. 8.28. This DXCCII is defined in the matrix equation (8.46). V XP

1

0

0

V XN IY

-1 0

0 0

0 0

VY I XP

I ZPþ

0

1

0

I XN

I ZN -

0

0

-1

=

ð8:46Þ

Example 8.18 Find the input admittance of the SGI in Fig. 8.29 [22]. Solution 8.18 The input admittance of the SGI of Fig. 8.29 is evaluated by using the following three equations: Y in =

I in V in

ð8:47aÞ

I in = ðV in - V test ÞsC -

V test R2

ð8:47bÞ

V in = ðV test - V in ÞsC R1

ð8:47cÞ

From above equations, input admittance is computed as follows:

Fig. 8.29 The DXCCIIbased SGI R1

Vin

Iin

XP

XN

DXCCII ZN-

ZP+

Zin

Vtest R2

Y

C

8.9

DVCC

209

Y in =

I in 1 1 1 1 1 = þ = þ V in sCR1 R2 R1 R2 sLeq Req

ð8:48Þ

where Leq = CR1R2 and 1/Req = 1/R1- 1/R2. If R1 = R2 in Fig. 8.27 is chosen, a positive lossless SGI is obtained.

8.9

DVCC

Symbol of the dual-output DVCC (DO-DVCC) is demonstrated in Fig. 8.30. If one of the Z- or Z+ terminal of this DO-DVCC is removed, plus-type DVCC (DVCC+) and minus-type DVCC (DVCC-) are, respectively, obtained. This DO-DVCC is defined in the matrix equation (8.49). 1

-1

0

I Y1

0

0

0

V Y1

I Y2 I Zþ

= 0 0

0 0

0 1

V Y2 IX

IZ -

0

0

-1

VX

Fig. 8.30 The symbol of the DO-DVCC

VY1 VY2

IY1 IY2

ð8:49Þ

Z+

Y1

IZ+

DO-DVCC Y2

X

Z-

IZ-

VZ+ VZ-

IX VX Fig. 8.31 The DVCC+ based IA

V2

Y1

DVCC V1

Y2

Vout

Z+

X

R2

R1

210

8

Current Conveyors and Their Applications X

Z+

Y2

Vin

DVCC (1)

Y1

Vtest

Iin

Y2

C

Z+

Y1

Zin

R1

DVCC (2)

X

R2

Fig. 8.32 The DVCC+ based SGI Fig. 8.33 The DVCC+ based SGI

Vin

X

Iin

(1)

Y2

DVCC Y1

Z+

Zin Vtest

Y2

(2)

Z+

DVCC Y1

X

R1

R2 C

Example 8.19 Find the output voltage of the IA in Fig. 8.31 [23]. Solution 8.19 The output voltage of the IA in Fig. 8.31 is found by V out =

R2 ðV - V 1 Þ R1 2

ð8:50Þ

Example 8.20 Find the input impedances of the SGIs in Fig. 8.32 [24] and Fig. 8.33 [25]. Solution 8.20 The input impedances of the SGIs in Figs. 8.32 and 8.33 are found by using the following three equations:

8.9

DVCC

211

R1

V1

X

Y2

DVCC

(1)

Z+

Z-

Y1

I1

I2

V2

C

Vtest Z-

Y1

Z+

DVCC

(2)

Y2

X

R2

Fig. 8.34 The DVCC-based SFI

Z in = I in = V test sC = -

V in I in

ð8:51aÞ

V test R1

ð8:51bÞ

V in V ) V test = - in R2 sCR2

ð8:51cÞ

From above equations, the input impedance is evaluated as below. Z in =

V in = sCR1 R2 = sLeq I in

ð8:52Þ

Here, Leq = CR1R2. Example 8.21 Find the admittance matrix equation for the SFI in Fig. 8.34 [26]. Solution 8.21 The admittance matrix equation for the SFI in Fig. 8.34 is obtained by using the following three equations: I2 = - I1

ð8:53aÞ

212

8

Fig. 8.35 The DVCCbased non-inverting firstorder VM APF

Current Conveyors and Their Applications

Vin

X

R

Vout

Y2

DVCC Z-

Y1

Vtest C

I1 = V test sC =

V test R2

ð8:53bÞ

V1 - V2 V - V2 ) V test = 1 R1 sCR1

ð8:53cÞ

From above equations, the admittance matrix equation for the SFI in Fig. 8.34 is expressed as I1 I2

=

1 s C R1 R2

1

-1

V1

-1

1

V2

ð8:54Þ

Example 8.22 Find the TF of the APF depicted in Fig. 8.35 [27]. Solution 8.22 The TF of the APF in 8.35 is found by using the following two equations: V in - V out = V test sC R

ð8:55aÞ

V out = V test - V in

ð8:55bÞ

From above equations, the TF of the non-inverting first-order VM APF is computed as 1 - sCR V out = 1 þ sCR V in

ð8:56Þ

Example 8.23 Find the output voltage of the VM full-wave rectifier (FWR) in Fig. 8.36 [28]. Solution 8.23 Analysis of the FWR of Fig. 8.36 is achieved as in the following: If vin(t) ≥ 0 is taken, D1 is ON and D2 is OFF. Thus, the following output voltage is obtained:

8.10

DDCC

213 Y2

vin(t)

Y1

Y1

DVCC Z+ Y2

X

D2

(2)

DVCC X

D1

(1)

vout(t)

Z+

R2

R1

Fig. 8.36 The DVCC-based VM FWR

vout ðt Þ =

R2 - 1 vin ðt Þ R1

ð8:57Þ

If R2 = 2R1 for the equation denoted in (8.57) is chosen, the output voltage simplifies as vout ðt Þ = vin ðt Þ

ð8:58Þ

If vin(t) < 0 is selected, D1 is OFF and D2 is ON. Hence, the output voltage becomes as follows: vout ðt Þ = - vin ðt Þ

ð8:59Þ

From combination of the equations in (8.58) and (8.59), the following output voltage is obtained: vout ðt Þ = jvin ðt Þj

ð8:60Þ

8.10 DDCC Symbol of the dual-output DDCC (DO-DDCC) is given in Fig. 8.37. If one of the Z- or Z+ terminal of this DO-DDCC is removed, plus-type DDCC (DVCC+) and minus-type DDCC (DDCC-) are, respectively, obtained. This DO-DDCC is defined in the matrix equation (8.61).

214

8

Fig. 8.37 The symbol of the DO-DDCC

VY1

Y1

IY1

VY2

Y2

IY2

VY3

Current Conveyors and Their Applications

Z+

DO-DDCC

Y3

IY3

IZ+

X

Z-

IZ-

VZ+

VZ-

IX

VX Y2

Vin

R

Y3

DDCC

Y1

Z+

X

Vout

Vtest C

Fig. 8.38 The DDCC-based first-order VM APF

-1 1 0 0

VX I Y1

1 0

0 0

I Y2 I Y3

0 = 0

0 0

V Y1

0 0

0 0

V Y2 V Y3

I Zþ

0

0

0

1

IX

IZ -

0

0

0

-1

ð8:61Þ

Example 8.24 Find the TF of the APF depicted in Fig. 8.38 [29]. Solution 8.24 The TF of the APF in Fig. 8.38 is found by using the following two equations: V test =

V in 1 þ sCR

V out = 2V test - V in

ð8:62aÞ ð8:62bÞ

From above equations, the TF of the APF in Fig. 8.38 is evaluated as V out 1 - sCR = V in 1 þ sCR

ð8:63Þ

8.10

DDCC

215

(2)

Y2

DDCC Vin

Y1

(1)

DDCC

Y3

Z+

Y1

Y2

Vtest

X

Vout

X

Y3

Z+

C

R

Fig. 8.39 The DDCC-based first-order VM APF

Y1

(2)

DDCC Vin

Y1 Y3

(1)

DDCC

Y2

Z+

Vout

Y3

Vtest

Y2

X

Z+

X

C

R

Fig. 8.40 The DDCC-based first-order VM APF

Example 8.25 Find the TF of the APF shown in Fig. 8.39 [30]. Solution 8.25 The TF of the APF of Fig. 8.39 is computed by using the following two equations: 2V in 1 þ sCR

ð8:64aÞ

V out = V test - V in

ð8:64bÞ

V test =

From above equations, the TF of the APF in Fig. 8.39 is found as follows: 1 - sCR V out = 1 þ sCR V in

ð8:65Þ

216

8

Current Conveyors and Their Applications

Example 8.26 Find the TF of the APF shown in Fig. 8.40 [30]. This circuit is found from the one given in Example 8.25 by interchanging the Y1 and Y2 terminals of the second DDCC. Solution 8.26 The TF of the APF of Fig. 8.40 is calculated by using the following two equations: 2V in 1 þ sCR

ð8:66aÞ

V out = V in - V test

ð8:66bÞ

V test =

From above equations, the TF of the APF in Fig. 8.40 is found as follows: 1 - sCR V out =1 þ sCR V in

8.11

ð8:67Þ

FDCCII

The symbol of the FDCCII is demonstrated in Fig. 8.41, while representation of the FDCCII with matrix equation is given in (8.68).

VY1 VY2 VY3 VY4

IY1 IY2 IY3 IY4

Y1

ZA+

Y2

FDCCII

Y3 Y4

XA

IXA

IXB

VXA Fig. 8.41 The symbol of the FDCCII

XB

VXB

ZA-

ZB+ ZB-

IZA+ IZAIZB+ IZB-

VZA+ VZAVZB+ VZB-

8.11

FDCCII

217

Fig. 8.42 The FDCCIIbased SGI

Y1

Vin

ZB-

Iin

Y2

ZA- ZB+

FDCCII

Y3

Y4 ZA+

XA

XB

Zin R1

V XA

1

-1

1

0

0

0

V XB I Y1

-1 0

1 0

0 0

1 0

0 0

0 0

V Y1

I Y2 I Y3

0 0

0 0

0 0

0 0

0 0

0 0

V Y2 V Y3

0

0

0

0

0

0

V Y4

I ZAþ I ZA -

0 0

0 0

0 0

0 0

1 -1

0 0

I XA I XB

I ZBþ I ZB -

0 0

0 0

0 0

0 0

0 0

1 -1

I Y4

=

C

R2

ð8:68Þ

Example 8.27 Find the input impedance of the SGI shown in Fig. 8.42 [31]. Solution 8.27 The input impedance of the SGI in Fig. 8.42 is found by using the following six equations: V in I in

ð8:69aÞ

V Y3 = V in

ð8:69bÞ

V XA = V Y3

ð8:69cÞ

V XB = V Y4

ð8:69dÞ

V XB R2

ð8:69eÞ

Z in =

I in =

218

8

VY1 VY2 VY3

IY1

IY2 IY3

Y1 Y2

Y3

(1)

Current Conveyors and Their Applications

Z+

DO-DDCC Z-

X

IZA+

IZA-

VZA+

VZA-

IXA

VXA Y1 Y2

VY4

IY4

Y3

(2)

Z+

DO-DDCC Z-

X

IZB+

IZB-

VZB+

VZB-

IXB VXB Fig. 8.43 Realization of the FDCCII by utilizing two DO-DDCCs

V V V XA = V Y4 sC ) in = V Y4 sC = V XB sC ) V XB = in R1 R1 sCR1

ð8:69fÞ

From above equations, input impedance is found below. Z in =

V in = sCR1 R2 = sLeq I in

ð8:70Þ

Here, Leq = CR1R2. Example 8.28 Realize the FDCCII by using the DO-DDCCs. Solution 8.28 Implementation of the FDCCII by using two DO-DDCCs is given in Fig. 8.43.

8.12

CDCC

The symbol of the CDCC is exhibited in Fig. 8.44, while representation of the CDCC with matrix equation is given in (8.71).

8.12

CDCC

219

Fig. 8.44 The symbol of the CDCC

VP

VN

W+

P

IP

CDCC N

IN

Z

W-

X

IZ

VW+

IW+

VW-

IW-

IX VX

VZ Fig. 8.45 The CDCCbased topology

Vin

Iin

W+

P

R1

CDCC N

0 0

IZ VX

=

1 0

X

W-

VZ

Zin

VP VN

Z

C

0 0

0 0

0 0

IP

-1 0 0 1

0 0

IN VZ IX

I Wþ

0

0

0

1

IW -

0

0

0

-1

R2

ð8:71Þ

Example 8.29 Find the input admittance of the circuit in Fig. 8.45 [32]. Solution 8.29 The input admittance of the circuit given in Fig. 8.45 is computed by using the following six equations: Y in =

I in V in

IN = 0 I Z = I P ) - V Z sC =

V in V ) V Z = - in R1 sCR1

ð8:72aÞ ð8:72bÞ ð8:72cÞ

220

8

Vin

Current Conveyors and Their Applications

(1)

Iin

Y

VF

X

R1

P

W+

(2)

CDCC N

Z

X

W-

VZ

Zin

C

R2

Fig. 8.46 The CDCC-based SGI

I Wþ = I X =

- VX V =- Z R2 R2

ð8:72dÞ

V in R1

ð8:72eÞ

I in = I Wþ þ I in =

V in V þ in sCR1 R2 R1

ð8:72fÞ

From above equations, input admittance is evaluated as Y in =

I in 1 1 1 1 = þ = þ V in sCR1 R2 R1 sLeq Req

ð8:73Þ

where Leq = CR1R2 and Req = R1. So, the circuit realizes parallel Req and Leq. Example 8.30 Find the input admittance of the circuit in Fig. 8.46 [33]. Solution 8.30 The input admittance of the SGI in Fig. 8.46 is computed by using the following six equations: Y in =

I in V in

IN = 0 I Z = I P ) - V Z sC = I Wþ = I X =

V in V ) V Z = - in R1 sCR1

- VX V =- Z R2 R2

I in = I Wþ

ð8:74aÞ ð8:74bÞ ð8:74cÞ ð8:74dÞ ð8:74eÞ

8.13

EX-CCCII

221

I in =

V in sCR1 R2

ð8:74fÞ

From above equations, input admittance is computed as follows: Y in =

I in 1 1 = = V in sCR1 R2 sLeq

ð8:75Þ

where Leq = CR1R2. So, the circuit realizes pure (lossless) inductance Leq.

8.13

EX-CCCII

The symbol of the EX-CCCII is exhibited in Fig. 8.47, while presentation of the EX-CCCII with matrix equation is given in (8.76). In this active block, RX is a function of external current Io. IY

0

0

0

V X1 V X2

1 1

RX1 0

0 RX2

VY

I Z1þ

= 0

1

0

I X1

I Z1 I Z2þ

0 0

-1 0

0 1

I X2

I Z2 -

0

0

-1

ð8:76Þ

Io Z1+

VY

IY

Y

EX-CCCII X1

IX1 VX1 Fig. 8.47 The symbol of the EX-CCCII

X2

IX2 VX2

Z1Z2+ Z2-

IZ1+ IZ1IZ2+ IZ2-

VZ1+

VZ1VZ2+ VZ2-

222

8

Current Conveyors and Their Applications

Fig. 8.48 The EX-CCCIIbased SGI

Io I2

Vin

Iin

Z1Y

I1

Zin

EX-CCCII

Z2+ X1

Z2-

X2

C

Z1+

Vtest

Example 8.31 Find the input impedance of the SGI shown in Fig. 8.48 [34]. Solution 8.31 The input impedance of the SGI is calculated by using the following five equations: Z in =

V in I in

I in = I 1 þ I 2 I1 =

V test - V in RX2

I 2 = V test sC I2 =

V in RX1

ð8:77aÞ ð8:77bÞ ð8:77cÞ ð8:77dÞ ð8:77eÞ

From above equations and considering IZ2- = -IX2, the input impedance of the SGI in Fig. 8.48 is found by Z in =

V in sCRX1 RX2 = I in 1 þ sC ðRX2 - RX1 Þ

ð8:78Þ

One observes from the equation denoted in (8.78) that the SGI in Fig. 8.48 needs a single active element matching condition, RX1 = RX2, to provide a positive lossless SGI.

References

223

References 1. G. Ferri, N.C. Guerrini, Low Voltage, Low Power CMOS Current Conveyors (Springer, 2003) 2. B. Wilson, Tutorial review trends in current conveyor and current-mode amplifier design. Int. J. Electron. 73(3), 573–583 (1992) 3. C. Toumazou, F.J. Lidgey, D.G. Haigh, Analog IC Design: The Current-Mode Approach (Peter Peregrinus, London, 1993) ISBN: 978-0863412974 4. B. Wilson, Recent developments in current conveyors and current-mode circuits. IEE Proc. -G Circuit. Devices Syst. 137(2), 63–77 (1990) 5. R. Senani, D.R. Bhaskar, A.K. Singh, Current Conveyors: Variants, Applications and Hardware Implementations (Springer, 2014) 6. A. Sedra, K.C. Smith, The current conveyor: A new circuit building block. Proc. IEEE 56(8), 1368–1369 (1968) 7. A.S. Sedra, K.C. Smith, A second-generation current conveyor and its applications. IEEE Trans. Circuit Theory 17(1), 132–134 (1970) 8. A. Fabre, Third-generation current conveyor: A new helpful active element. Electron. Lett. 31(5), 338–339 (1995) 9. E. Arslan, U. Cam, O. Cicekoglu, Novel lossless grounded inductance simulators employing only a single first generation current conveyor. Frequenz 57(9–10), 204–206 (2003) 10. H. Alpaslan, E. Yuce, S. Minaei, A new active device namely S-CCI and its applications: Simulated floating inductor and quadrature oscillators. IEEE Trans. Circuit. Syst. I Regular Papers 69(9), 3554–3564 (2022) 11. C. Toumazou, F.J. Lidgey, P.Y.K. Cheung, Current-mode analogue signal processing circuits-a review of recent developments. In 1989 IEEE International Symposium on Circuits and Systems (ISCAS) (IEEE, 1989), pp. 1572–1575 12. A. Sedra, K. Smith, A second-generation current conveyor and its applications. IEEE Trans. Circuit Theory 17(1), 132–134 (1970) 13. O. Cicekoglu, New current conveyor based active-gyrator implementation. Microelectron. J. 29(8), 525–528 (1998) 14. W. Kiranon, P. Pawarangkoon, Floating inductance simulation based on current conveyors. Electron. Lett. 33(21), 1748–1749 (1997) 15. P.A. Mohan, Grounded capacitor based grounded and floating inductance simulation using current conveyors. Electron. Lett. 34(11), 1037–1038 (1998) 16. E. Yuce, DO-CCII/DO-DVCC based electronically fine tunable quadrature oscillators. J. Circuit. Syst. Comput. 26(02), 1750025 (2017) 17. P.A. Martinez, J. Sabadell, C. Aldea, S. Celma, Variable frequency sinusoidal oscillators based on CCII+. IEEE Trans. Circuit. Syst. I Fundamental Theory Appl. 46(11), 1386–1390 (1999) 18. H.-Y. Wang, C.-T. Lee, Systematic synthesis of RL and CD immittances using single CCIII. Int. J. Electron. 87(3), 293–301 (2000) 19. A. Fabre, O. Saaid, F. Wiest, C. Boucheron, High frequency applications based on a new current controlled conveyor. IEEE Trans. Circuit. Syst. I Fundamental Theory Appl. 43(2), 82–91 (1996) 20. L. Safari, E. Yuce, S. Minaei, A new ICCII based resistor-less current-mode first-order universal filter with electronic tuning capability. Microelectron. J. 67, 101–110 (2017) 21. B. Metin, Canonical inductor simulators with grounded capacitors using DCCII. Int. J. Electron. 99(7), 1027–1035 (2012) 22. I. Myderrizi, S. Minaei, E. Yuce, DXCCII-based grounded inductance simulators and filter applications. Microelectron. J. 42(9), 1074–1081 (2011) 23. T.M. Hassan, S.A. Mahmoud, New CMOS DVCC realization and applications to instrumentation amplifier and active-RC filters. AEU Int. J. Electron. Commun. 64(1), 47–55 (2010) 24. A.R. Hamad, M.A. Ibrahim, Grounded generalized impedance converter based on differential voltage current conveyor (DVCC) and its applications. ZANCO J. Pure Appl. Sci. 29(3), 118–127 (2017)

224

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Current Conveyors and Their Applications

25. T. Unuk, DVCC+ based grounded simulator suitable for capacitance multiplier and frequency dependent negative resistor. In 33rd International Conference (Radioelektronika, Pardubice, 2023) 26. K. Pal, Modified current conveyors and their applications. Microelectron. J. 20(4), 37–40 (1989) 27. H.-P. Chen, K.-H. Wu, Grounded-capacitor first-order filter using minimum components. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89(12), 3730–3731 (2006) 28. M.A. Ibrahim, E. Yuce, S. Minaei, A new DVCC-based fully cascadable voltage-mode fullwave rectifier. J. Comput. Electron. 15, 1440–1449 (2016) 29. A. Toker, S. Ozoguz, Novel all-pass filter section using differential difference amplifier. AEU Int. J. Electron. Commun. 58(2), 153–155 (2004) 30. M. Kumngern, K. Dejhan, High-input and low-output impedance voltage-mode all-pass networks. In Proceedings of the 2009 12th International Symposium on Integrated Circuits (IEEE, 2009), pp. 381–384 31. F. Kacar, New lossless inductance simulators realization using a minimum active and passive components. Microelectron. J. 41(2–3), 109–113 (2010) 32. F. Kacar, H. Kuntman, A. Kuntman, Grounded inductance simulator topologies realization with single current differencing current conveyor. In 2015 European Conference on Circuit Theory and Design (ECCTD) (IEEE, 2015), pp. 1–4 33. S. Tez, O.M. Tez, E. Yuce, Derivation of Lossless Grounded Inductor Simulators Based on Active Circuit Elements (ICAT, Antalya, 2018) 34. D. Agrawal, S. Maheshwari, Electronically tunable grounded immittance simulators using an EX-CCCII. Int. J. Electron. 107(10), 1625–1648 (2020)

Chapter 9

Other Active Devices

9.1

Introduction

In this chapter, other active elements such as current feedback operational amplifier (CFOA), operational transresistance amplifier (OTRA), four-terminal floating nullor (FTFN), operational transconductance amplifier (OTA), voltage differencing inverting buffered amplifier (VDIBA), voltage differencing buffer amplifier (VDBA), current differencing buffered amplifier (CDBA), current amplifier (CA), current follower transconductance amplifier (CFTA), current differencing transconductance amplifier (CDTA), differential voltage current conveyor transconductance amplifier (DVCCTA), and current operational amplifier (COA) are treated. Moreover, implementation of the OTRA, FTFN, and CDBA by using two CFOAs is given.

9.2

CFOA

CFOA is a commercially available active device. In other words, the CFOA can be easily obtained by using one AD844 [1]. The symbol of the CFOA is shown in Fig. 9.1, while the current-voltage relationships among terminals of the CFOA can be expressed in the matrix equation (9.1). Implementation of the CFOA by using one plus-type second-generation current conveyor (CCII+) and one voltage follower (VF) is given in Fig. 9.2.

© The Author(s), under exclusive license to Springer Nature Switzerland AG 2024 E. Yuce, S. Minaei, Passive and Active Circuits by Example, https://doi.org/10.1007/978-3-031-44966-6_9

225

226

9

Fig. 9.1 The symbol of the CFOA

IY

VY

Y

IW

CFOA W

IX

VX

Other Active Devices

Z

X

VW

IZ VZ

VY VX

IY IX

Y

(1)

CCII

(2)

VF

Y

Z+

X

X

VW

IW

IZ VZ

Fig. 9.2 Realization of the CFOA by using one CCII+ and one VF

R1

Fig. 9.3 The CFOA-based series RL

Vin

Iin

Y

CFOA W Z

X

Vtest

R2

Zin

C

IY

0

0

0 0

IX

IZ VX

1 = 0

0 1

0 0 0 0

VY VZ

VW

0

0

1 0

IW

ð9:1Þ

Example 9.1 Find the input impedance of the series RL in Fig. 9.3 [2]. Solution 9.1 The input impedance of the series RL in Fig. 9.3 is obtained by using the following three equations:

9.2

CFOA

227

V in I in

ð9:2aÞ

V in - V test R1

ð9:2bÞ

Z in = I in =

ðV test - V in ÞsC = -

V test R2

ð9:2cÞ

Rearrangement of the equation in (9.2c), Vtest, is found below. V test =

V in sC sC þ R12

ð9:3Þ

If Vtest in Eq. (9.3) is replaced into (9.2b), the input current is evaluated as follows: 1 V in sC þ R2 V in sC V in sC V in 1 1 1 sC þ sC þ sC þ R2 R2 R2 = I in = R1 R1 1 1 V in V in × R2 R2 R2 1 1 sC þ sC þ × R2 R2 R2 = = R1 R1 1 V in V in × V in sCR2 þ 1 sCR2 þ 1 R1 = = = 1 R1 sCR1 R2 þ R1 R1 × R1

ð9:4Þ

From above equation, the input impedance is computed as Z in =

V in = sCR1 R2 þ R1 = sLeq þ Req I in

ð9:5Þ

Here, Leq = CR1R2 and Req = R1. Example 9.2 Find the input impedance of the simulated grounded inductor (SGI) in Fig. 9.4 [3]. Solution 9.2 The input impedance of the SGI in Fig. 9.4 is obtained by using the following three equations:

228

9

Vin

Y

Iin

X

Zin

R2

CFOA W

R1

(1) Z

X

Other Active Devices

Z

CFOA W (2)

Vtest

Y

C

Fig. 9.4 The CFOA-based SGI

Z in =

V in I in

ð9:6aÞ

I in =

V test R2

ð9:6bÞ

V in V = V test sC ) V test = in R1 sCR1

ð9:6cÞ

If Vtest indicated in (9.6c) is replaced into the equation in (9.6b), the following input current is obtained: I in =

V in sCR1

R2

=

V in sCR1 R2

ð9:7Þ

From above equation, the input impedance is calculated as Z in =

V in = sCR1 R2 = sLeq I in

ð9:8Þ

where Leq = CR1R2. Example 9.3 Find the input impedance of the CFOA-based SGI demonstrated in Fig. 9.5 [4]. Also, this SGI has the feature of improved low-frequency performance. Solution 9.3 The input impedance of the SGI in Fig. 9.5 is obtained by using the following three equations: Z in = I in = -

V in I in

ð9:9aÞ

V test R1

ð9:9bÞ

9.2

CFOA

229

X (1) W CFOA Z Y Y

C

(2) CFOA W Z X Iin

Vtest

R3

R1

R2

Vin

Zin

Fig. 9.5 The CFOA-based SGI with the property of improved low-frequency performance

Y

(1)

R

CFOA W

Vin

Iin

Z

X

Vtest C1

X

(2)

CFOA W Y

Z

C2

Zin Fig. 9.6 The CFOA-based grounded FDNR

- V test V in - V test = - V test sC R2 R3

ð9:9cÞ

From above equations, the input impedance is calculated as Z in =

R V in = sCR1 R2 þ R1 2 - 1 I in R3

ð9:10Þ

In equation denoted in (9.10), if R3 = R2 is taken, a positive lossless SGI is obtained. Example 9.4 Find the input impedance of the CFOA-based grounded frequencydependent negative resistor (FDNR) in Fig. 9.6 [5]. Solution 9.4 The input impedance of the FDNR in Fig. 9.6 is obtained by using the following three equations:

230

9

V1

Z

I1

R1

X

Z

CFOA W

W CFOA (1) Y

Y

X

(2)

Other Active Devices

I2

V2

Y

Vtest

Z

CFOA W

C

(3)

X

R2

Fig. 9.7 The CFOA-based positive lossless SFI

Z in =

V in I in

ð9:11aÞ

I in = - V test sC 1

ð9:11bÞ

V test = - V in sC 2 ) V test = - V in sC 2 R R

ð9:11cÞ

From above equations, the input impedance is found as Z in =

1 V in 1 = 2 = I in s C 1 C 2 R s2 D

ð9:12Þ

Here, D = C1C2R. Example 9.5 Find the admittance matrix equation of the CFOA-based simulated floating inductor (SFI) in Fig. 9.7 [6]. Solution 9.5 The admittance matrix equation of the SFI given in Fig. 9.7 is obtained by using the following three equations: I2 = - I1

ð9:13aÞ

V test R1

ð9:13bÞ

I1 =

V1 - V2 V - V2 = V test sC ) V test = 1 R2 sCR2

ð9:13cÞ

From above equations, the following admittance matrix equation is obtained:

9.2

CFOA

231

X (1) W CFOA Z Y

Vo1

Y C1

R3 R1

(2) CFOA W Z X

Vo2

R2

C2

Fig. 9.8 The CFOA-based QO

I1 1 = s C R I2 1 R2

1 -1

-1 1

V1 1 = s L V2 eq

1 -1

-1 1

V1 V2

ð9:14Þ

where Leq = CR1R2. Example 9.6 Find the characteristic eq. (D(s)), oscillation condition (OC), and oscillation frequency (OF) of the CFOA-based quadrature oscillator (QO) in Fig. 9.8 [7]. Solution 9.6 The D(s), OC, and OF of the CFOA-based QO shown in Fig. 9.8 are obtained by using the following two equations: V o1 = V o2 sC 2 ) V o1 = V o2 sC 2 R1 R1 V V R V o2 - V o1 = - V o1 sC 1 - o1 ) V o2 - V o1 = - V o1 sC 1 R2 - o1 2 R2 R3 R3

ð9:15aÞ ð9:15bÞ

From above equations, the D(s), OC, and OF of the CFOA-based QO in Fig. 9.8 are, respectively, evaluated by DðsÞ = s2 C 1 C 2 R1 R2 þ sC 2 R1

R2 -1 þ 1=0 R3

R3 ≥ R2 f0 =

1 1 p 2π C 1 C 2 R1 R2

This QO can be controlled orthogonally by changing value of R1.

ð9:16aÞ ð9:16bÞ ð9:16cÞ

232

9.3

9

Other Active Devices

OTRA

The symbol of the OTRA is depicted in Fig. 9.9, while the OTRA can be expressed by the following matrix equation: VP =

VN VO

0

0

0

IP

0 Rm

0 - Rm

0 0

IN IO

ð9:17Þ

Here, Rm is ideally infinity. Example 9.7 Find the input impedance of the OTRA-based SGI demonstrated in Fig. 9.10 [8]. Solution 9.7 The input impedance of the SGI in Fig. 9.10 is obtained by using the following five equations: V in I in

ð9:18aÞ

V in V - Vo þ V in s3C þ in R R

ð9:18bÞ

V o = I P Rm - I N Rm

ð9:18cÞ

I P = V in s3C

ð9:18dÞ

Z in = I in =

Fig. 9.9 The symbol of the OTRA

VP

IP

VN

IN

P

OTRA

O

N

IO

R

Fig. 9.10 The OTRAbased SGI

R

Vin

R

Iin

N

OTRA P

3C

Zin

C

O

VO

9.3

OTRA

233

Fig. 9.11 The OTRAbased non-inverting firstorder VM APF

P

OTRA

O

N

R/ R/

C

Vin

R

V in Vo = IN 1 R R þ sC

Vout

ð9:18eÞ

From above equations, input impedance is computed as Z in =

R2 ðsCR þ sCR þ 1Þ V in = 2 2 3 m I in s 3C R þ s5CR2 þ 2R þ Rm

ð9:19Þ

Here, if Rm goes to infinity, the input impedance simplifies as Z in =

V in R2 sCRm = = sCR2 = sLeq I in Rm

ð9:20Þ

where Leq = CR2. Example 9.8 Find the transfer function (TF) of the OTRA-based non-inverting first-order voltage-mode (VM) all-pass filter (APF) in Fig. 9.11 [9]. Solution 9.8 The TF of the OTRA-based non-inverting first-order VM APF in Fig. 9.11 is calculated by using the following four equations: H ðsÞ = IN =

V out V in

V in V o þ R= R=

ð9:21aÞ ð9:21bÞ

I P = 0 ) V o = - I N Rm

ð9:21cÞ

V in - V out = ðV out - V o ÞsC R

ð9:21dÞ

From above equations, and assuming Rm goes to infinity, the TF is found and simplified as follows:

234

9

Fig. 9.12 Implementation of the OTRA by using two CFOAs

Y VP

VN

(1)

CFOA W

IP

Z

X

X

IN

(2)

VX

VY

H ðsÞ =

IO

CFOA W Y

Fig. 9.13 The symbol of the FTFN

Other Active Devices

IX IY

Z

Z

X

FTFN Y

R= þ Rm ð1 - sCRÞ V out = = V in R þ Rm ð1 þ sCRÞ R ð1 - sCRÞ 1 - sCR = m = Rm ð1 þ sCRÞ 1 þ sCR

W

IZ IW

VO

VZ VW

ð9:22Þ

Note The topology in Fig. 9.11 has a single passive resistive matching condition. Also, if R and C are interchanged in Fig. 9.11, an inverting first-order VM APF can be easily obtained. Example 9.9 Realize the OTRA with CFOAs. Solution 9.9 Realization of the OTRA by using two CFOAs is demonstrated in Fig. 9.12.

9.4

FTFN

The symbol of the FTFN is illustrated in Fig. 9.13, while the FTFN can be expressed with the matrix equation in (9.23).

9.4

FTFN

235 C

Fig. 9.14 The NFTFNbased inverting first-order VM APF circuit

Vin

Vout

Z

X

NFTFN W

Y

R

R

IY IX VX IW

=

0

0

0 0

VY

0

0

0 0

IZ

1 0

0 ∓1

0 0 0 0

VZ VW

ð9:23Þ

Here, - and + sign correspond to minus-type FTFN (NFTFN) and plus-type FTFN (PFTFN), respectively. Example 9.10 Find the TF of the NFTFN-based inverting first-order VM APF in Fig. 9.14 [10]. Solution 9.10 The TF of the NFTFN-based inverting first-order VM APF in Fig. 9.14 is computed by using the following two equations: H ðsÞ =

V out V in

ðV in - V out ÞsC =

V in V out þ R R

ð9:24aÞ ð9:24bÞ

From above equations, the following TF is found: H ðsÞ =

1 - sCR V out =1 þ sCR V in

ð9:25Þ

Example 9.11 Find the input admittance of the PFTFN-based SGI depicted in Fig. 9.15 [11]. Solution 9.11 The input admittance of the PFTFN-based SGI in Fig. 9.15 is found by using the following five equations:

236

9

Other Active Devices

R3

Fig. 9.15 The PFTFNbased SGI R4

Vin

W

I1

Iin

PFTFN Z

I1

R2

X

Y

Zin V2

V1

C

R1

Y in = I in = I 1 þ

I in V in

ð9:26aÞ

V in - V 1 V in - V 1 þ R4 R3

V in - V 1 V 1 = R4 R2

ð9:26bÞ ð9:26cÞ

V2 R1

ð9:26dÞ

V in - V 1 = ðV 1 - V 2 ÞsC R3

ð9:26eÞ

ðV 1 - V 2 ÞsC = I 1 þ

From above equations, the input admittance is evaluated as Y in =

I in 1 R R 1 1 1 = 1þ2 4 - 2 = þ ð9:27Þ þ V in sCR R 1 þ R2 R3 R1 R2 þ R4 sLeq Req 1 3 R4

where Leq and Req are, respectively, found by Leq = CR1 R3 1 þ Req =

R2 R4

ð9:28aÞ

1 1 R2 þR4

1 þ 2 RR43 -

R2 R1

ð9:28bÞ

If Req is taken as infinity, a positive lossless SGI is obtained, which is achieved with the following condition:

9.4

FTFN

237 R2

Fig. 9.16 The PFTFNbased parallel RL topology

Vin

I1

Iin

I1

W

X

PFTFN Z

Zin Vtest

Y

C

R1

1þ2

R4 R2 = R3 R1

ð9:29Þ

Example 9.12 Find the input admittance of the PFTFN-based parallel RL circuit in Fig. 9.16 [11]. Solution 9.12 The input admittance of the PFTFN-based parallel RL structure in Fig. 9.16 is found by using the following four equations: Y in =

I in V in

I in = I 1 þ

ð9:30aÞ

V in R2

- V test sC = I 1 þ

ð9:30bÞ V test R1

V in = - V test sC R2

ð9:30cÞ ð9:30dÞ

From above equations, the input admittance is calculated as follows: Y in =

I in 1 2 1 1 = þ = þ V in sCR1 R2 R2 sLeq Req

ð9:31Þ

Here, Leq = CR1R2 and Req = R2/2. Example 9.13 Find the input impedance of the PFTFN and INIC-based parallel SGI in Fig. 9.17 [12]. Solution 9.13 The input impedance of the PFTFN and INIC-based parallel SGI in Fig. 9.17 is found by using the following four equations:

238

9

INIC

1

Vin

R2

2

W

I1

Iin

Other Active Devices

X

PFTFN Z

I1

Y

Zin Vtest

C

R1

Fig. 9.17 The PFTFN and INIC-based positive lossless SGI

Z in =

V in I in

I in = I 1 -

ð9:32aÞ

V in R2

- V test sC = I 1 þ

V test R1

V in = - V test sC R2

ð9:32bÞ ð9:32cÞ ð9:32dÞ

From above equations, the input impedance is calculated by Z in =

V in = sCR1 R2 = sLeq I in

ð9:33Þ

Here, Leq = CR1R2. Example 9.14 Implement the NFTFN and PFTFN by using the CFOAs. Solution 9.14 Implementations of the NFTFN and PFTFN by using two CFOAs are, respectively, shown in Figs. 9.18 and 9.19 [13].

9.5

OTA

The symbol of the dual output OTA (DO-OTA) is given in Fig. 9.20. The DO-OTA can be expressed with the following matrix equation:

9.5

OTA

239

Fig. 9.18 NFTFN implementation based on two CFOAs

IX

VX

Y

IW (1) Z

X

(2)

CFOA W VY

IY

Y

Z

IW X

VX

IX

X

IZ

VZ

VW

(2)

CFOA W Z

Y

(1) Z

IZ

CFOA W VY

VW

CFOA W X

VZ

Y

IY

Fig. 9.19 PFTFN realization based on two CFOAs Fig. 9.20 The symbol of the DO-OTA

V1

V2

I1 I2 I Oþ IO -

=

+

I1

DO-OTA -

I2

0

0

0

0

V1

0 - gm

0 gm

0 0

0 0

V2 V Oþ

gm

- gm

0

0

VO -

O+ O-

IO+ IO-

VO+

VO-

ð9:34Þ

Example 9.15 Find the input impedance of the OTA-based positive lossless SGI in Fig. 9.21 [14]. Solution 9.15 The input impedance of the OTA-based positive lossless SGI in Fig. 9.21 is found by using the following five equations:

240

9

Vin

Iin

+

Other Active Devices

Vtest

(1)

OTA

O+

-

(2)

OTA

+

C

Zin

O+

Fig. 9.21 The OTA-based SGI topology Fig. 9.22 The symbol of the VDIBA

V1

V2

Z in =

I1 I2

+

W

VDIBA -

V in I in

Z

IW IZ

VW VZ

ð9:35aÞ

I O1þ = - V 1þ gm1

ð9:35bÞ

V in = V 1þ

ð9:35cÞ

I O1þ = - V test sC

ð9:35dÞ

I in = V 2 - gm2 = V test gm2

ð9:35eÞ

From above equations, the input impedance is computed as Z in =

V in sC = = sLeq I in gm1 gm2

ð9:36Þ

where Leq = C/(gm1gm2).

9.6

VDIBA

The symbol of the VDIBA is shown in Fig. 9.22. The VDIBA can be defined with the following matrix equation:

9.6

VDIBA

241

Fig. 9.23 The VDIBAbased first-order VM APF structure

+

W

Vo1

Z

Vo2

VDIBA Vin

-

C

0

I1 I2 IZ VW

=

0

0

0

- gm 0

gm 0

0

0

0

0

V2

0 0 -1 0

VZ IW

V1 ð9:37Þ

Example 9.16 Find the TFs of the VDIBA-based first-order VM APF in Fig. 9.23 [15]. This filter simultaneously provides both non-inverting and inverting responses. Solution 9.16 The TFs of the VDIBA-based first-order VM APF in Fig. 9.23 are evaluated by using the following four equations: H 1 ðsÞ =

V o1 V in

ð9:38aÞ

H 2 ðsÞ =

V o2 V in

ð9:38bÞ

V o1 = - V o2

ð9:38cÞ

I Z = ðV in - V o2 ÞsC = gm ðV in - V o1 Þ

ð9:38dÞ

From above equations, the following non-inverting and inverting first-order VM TFs are, respectively, obtained: H 1 ðsÞ =

1 - gsC g - sC V o1 m = m = V in gm þ sC 1 þ sC g

ð9:39aÞ

m

H 2 ðsÞ =

1 - sC g - sC V o2 gm =- m =gm þ sC V in 1 þ sC g m

ð9:39bÞ

242

9.7

9

Other Active Devices

VDBA

The symbol of the VDBA is demonstrated in Fig. 9.24. The VDBA can be expressed with the following matrix equation: IP

0

0

0

IN IZ

0 - gm

0 gm

0 0

VP VN

I ZC -

gm

- gm

0

VZ

VW

0

0

1

=

ð9:40Þ

Example 9.17 Find the input impedance of the VDBA-based positive lossless SGI in Fig. 9.25 [16]. Solution 9.17 The input impedance of the VDBA-based positive lossless SGI in Fig. 9.25 is calculated by using the following three equations:

Fig. 9.24 The symbol of the VDBA

VP

VN

P

IP IN

W

N

ZC-

VW

IW

VDBA Z

VZ

IZ

IZCVZC-

R

Fig. 9.25 The VDBAbased SGI circuit P

W

VDBA Vin

Iin

N

ZC-

Z

Vtest C

Zin

9.8

CDBA

243

V in I in

ð9:41aÞ

V in - V test R

ð9:41bÞ

Z in = I in =

I Z = V in gm = ðV in - V test ÞsC

ð9:41cÞ

From above equations, the input impedance is found below. Z in =

V in sCR = = sLeq I in gm

ð9:42Þ

Here, Leq = CR/gm.

9.8

CDBA

The symbol of the CDBA is depicted in Fig. 9.26. The CDBA can be defined with the following matrix equation: VP VN IZ VW

=

0 0

0 0

0 0

0 0

IP IN

-1 1

0

0

VZ

1

0

IW

0

0

ð9:43Þ

Example 9.18 Find the input impedance of the CDBA-based positive lossless SGI in Fig. 9.27 [17]. Solution 9.18 The input impedance of the CDBA-based positive lossless SGI in Fig. 9.27 is computed by using the following five equations: Z in =

V in I in

I in = I Z1 = I N1 =

Fig. 9.26 The symbol of the CDBA

VP

VN

IP IN

ð9:44aÞ V test R2

ð9:44bÞ

P

W

CDBA N

Z

IW IZ

VW VZ

244

9

Fig. 9.27 The CDBAbased SGI circuit

Vin

Other Active Devices

Z

Iin

(1)

W

Zin

P

CDBA N

R2

R1 P

(2)

W

CDBA

Vtest

Z

N

C

Fig. 9.28 Implementation of the CDBA by using two CFOAs

Y

VP VN

(1)

CFOA W

IP

X

Z

X

IN

CFOA W Y

I Z2 = - I P2 I P2 =

IZ (2) Z

V in R1

I Z2 = - V test sC

IW

VZ VW

ð9:44cÞ ð9:44dÞ ð9:44eÞ

From above equations, the input impedance is computed as Z in =

V in = sCR1 R2 = sLeq I in

ð9:45Þ

where Leq = CR1R2. Example 9.19 Realize the CDBA by using CFOAs. Solution 9.19 Realization of the CDBA by using two CFOAs is depicted in Fig. 9.28.

9.9

9.9

CA

245

CA

The symbol of the CA is given in Fig. 9.29. The CA can be defined with the following matrix equation: I in I outþ I out -

=

gm

0 0

V in

- gm gm

0 0 0 0

V outþ V out -

ð9:46Þ

Example 9.20 Find the input impedance of the CA-based positive lossless SGI in Fig. 9.30 [18]. Solution 9.20 The input impedance of the CA-based positive lossless SGI in Fig. 9.30 is calculated by using the following three equations: Z in =

V in I in

ð9:47aÞ

I in = V test gm2

ð9:47bÞ

gm1 V in = V test sC ) V test =

gm1 V in sC

ð9:47cÞ

From above equations, the input impedance is computed as

Fig. 9.29 The symbol of the CA

OUT+

Vin

Iin

IN

CA

Vout+

Iout+

OUT-

Vout-

Iout-

Fig. 9.30 The CA-based SGI topology (1) OUT+

Vin

Iin

IN

CA

Vtest

OUT+

C

Zin

OUT- (2)

CA OUT+

IN

246

9

Z in =

Other Active Devices

V in sC = = sLeq I in gm1 gm2

ð9:48Þ

where Leq = C/(gm1gm2).

9.10 CFTA The symbol of the CFTA is shown in Fig. 9.31. The CFTA can be defined with the following matrix equation: VF IZ I Xþ IX -

=

0 1

0 0

0 0

0 0

IF VZ

0

gm

0

0

V Xþ

0

- gm

0

0

VX -

ð9:49Þ

Example 9.21 Find the input impedance of the CFTA-based positive lossless SGI in Fig. 9.32 [19]. Solution 9.21 The input impedance of the CFTA-based positive lossless SGI in Fig. 9.32 is evaluated by using the following four equations:

Fig. 9.31 The symbol of the CFTA

VF VZ

Fig. 9.32 The CFTA-based SGI structure

F

IF

X+

X-

Z

IZ

Zin

Iin

Z

VX-

IX(1)

Vin

VX+

IX+

CFTA

X+

CFTA

X-

F

F

(2)

X+

Z

X-

CFTA

C

9.11

CDTA

247

Z in =

V in I in

ð9:50aÞ

I in = I F1 = - I X2þ = - gm2 V Z2

ð9:50bÞ

I F2 = I Z2 = - I X1 - = gm1 V in

ð9:50cÞ

V Z2 = -

I Z2 sC

ð9:50dÞ

From above equations, the input impedance is found as follows: Z in =

V in sC = = sLeq I in gm1 gm2

ð9:51Þ

where Leq = C/(gm1gm2).

9.11 CDTA The symbol of the CDTA is given in Fig. 9.33. The CDTA can be expressed with the following matrix equation: VP

0

0

0

0

0

IP

VN IZ

0 -1

0 1

0 0

0 0

0 0

IN VZ

0 0

0 0

- gm gm

0 0

0 0

V Xþ VX -

I Xþ IX -

=

ð9:52Þ

Example 9.22 Find the input impedance of the CDTA-based SGI in Fig. 9.34 [20]. Solution 9.22 The input impedance of the CDTA-based positive lossless SGI in Fig. 9.34 is found by using the following eight equations:

Fig. 9.33 The symbol of the CDTA

VP VN

IP IN

P

X+

CDTA N

X-

Z

IZ

VZ

IX+ IX-

VX+

VX-

248

9

N

(1)

P

X+

CDTA P

Vin

Z

(2)

X+

Z

X-

Other Active Devices

CDTA X-

N

C

Iin

Zin Fig. 9.34 The CDTA-based SGI circuit

Z in =

V in I in

ð9:53aÞ

I in = I N1 - I P1

ð9:53bÞ

I N1 = gm2 V Z2

ð9:53cÞ

I P1 = - gm2 V Z2

ð9:53dÞ

I Z2 = - sCV Z2

ð9:53eÞ

I Z2 = I N2 - I P2

ð9:53f Þ

I N2 = - gm1 V in

ð9:53gÞ

I P2 = gm1 V in

ð9:53gÞ

From above equations, the input impedance is found below. Z in =

V in sC = = sLeq I in 4gm1 gm2

ð9:54Þ

Here, Leq = C/(4gm1gm2).

9.12

DVCCTA

The symbol of the dual output DVCCTA (DO-DVCCTA) is demonstrated in Fig. 9.35. The DO-DVCCTA can be defined with the following matrix equation:

9.12

DVCCTA

249

Fig. 9.35 The symbol of the DO-DVCCTA

IY1

VY1

Y1

O+

DO-DVCCTA VY2

Y2

IY2

X

VZ

VX

V1

VO-

IO-

IZ

IX

Fig. 9.36 The DODVCCTA-based SFI circuit

O-

Z

VO+

IO+

I1

Y1

O-

DO-DVCCTA V2

Y2

I2

X

R

I Y1 I Y2 VX IZ I Oþ IO -

=

0 0

0 0

0 0

0 0

0 0

0 0

V Y1 V Y2

1

-1

0

0

0

0

IX

0 0

0 0

1 0

0 - gm

0 0

0 0

VZ V Oþ

0

0

0

gm

0

0

VO -

Z

O+

C

ð9:55Þ

Example 9.23 Find the admittance matrix equation of the DO-DVCCTA-based positive lossless SFI in Fig. 9.36 [21]. Solution 9.23 The admittance matrix equation of the DO-DVCCTA-based positive lossless SFI in Fig. 9.36 is calculated by using the following five equations: I2 = - I1

ð9:56aÞ

VX = V1 - V2

ð9:56bÞ

VX = V Z sC R

ð9:56cÞ

250

9

Other Active Devices

I 1 = gm V Z

ð9:56dÞ

I 2 = - gm V Z

ð9:56eÞ

From above equations, the admittance matrix equation is computed by I1 g = m sCR I2

1 -1

-1 1

V1 1 = sLeq V2

1 -1

-1 1

V1 V2

ð9:57Þ

where Leq = CR/gm.

9.13

COA

The symbol of the COA is given in Fig. 9.37. The COA can be expressed by the following four equations: VP = 0

ð9:58aÞ

VN = 0

ð9:58bÞ

I Z = B ðI N - I P Þ

ð9:58cÞ

IW = - IZ

ð9:58dÞ

Here, B is ideally infinity. Example 9.24 Find the TF of the COA-based non-inverting first-order currentmode APF in Fig. 9.38 [22]. Solution 9.24 The TF of the COA-based non-inverting first-order current-mode APF in Fig. 9.38 is computed by using the following six equations:

Fig. 9.37 The symbol of the COA

VP

IP

P

COA VN

N

IN

IZ

Z W

P

Iin

COA

Vtest R

N

VW

IW

C

Fig. 9.38 The COA-based first-order APF circuit

VZ

Z W

Iout

References

251

I in = V test sC þ

1 R

ð9:59aÞ

I out = - I Z

ð9:59bÞ

IW = - IZ

ð9:59cÞ

I Z = B ðI N - I P Þ

ð9:59dÞ

V test - IW R

ð9:59eÞ

IN =

I P = V test sC

ð9:59f Þ

From above equations, the TF is computed as follows: ð1 - sCRÞ I out = I in 1 - B1 ð1 þ sCRÞ

ð9:60Þ

If B is infinity, equation given in (9.60) simplifies as 1 - sCR I out = I in 1 þ sCR

ð9:61Þ

It is observed from equation in (9.61) that a non-inverting first-order APF TF is obtained. If R and C are interchanged, an inverting first-order APF TF is obtained. Note One observes throughout of this chapter that other active devices can be easily obtained from combination of the OTA(s) and CC(s).

References 1. Analog Devices, AD844 SPICE Macro Model Rev. A, 7/91. https://www.analog.com/en/ license/spice-models?mediaPath=media/en/simulation-models/spice-models/ad844.cir& modelType=spice-models. Accessed 20 Dec 2022 2. E. Yuce, Novel lossless and lossy grounded inductor simulators consisting of a canonical number of components. Analog Integr. Circ. Sig. Process 59, 77–82 (2009) 3. A. Fabre, Gyrator implementation from commercially available transimpedance operational amplifiers. Electron. Lett. 28, 263–264 (1992) 4. E. Yuce, S. Minaei, Commercially available active device based grounded inductor simulator and universal filter with improved low frequency performances. J. Circuit. Syst. Comput. 26(4), 1750052 (2017) 5. A. Toker, O. Cicekoglu, H. Kuntman, New active gyrator circuit suitable for frequencydependent negative resistor implementation. Microelectron. J. 30(1), 59–62 (1999) 6. R. Senani, Realization of a class of analog signal processing/signal generation circuits: Novel configurations using current feedback op-amps. Frequenz 52(9–10), 196–206 (1998) 7. P.A. Martinez, J. Sabadell, C. Aldea, Grounded resistor controlled sinusoidal oscillator using CFOAs. Electron. Lett. 33(5), 346–348 (1997)

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Other Active Devices

8. R. Pandey, N. Pandey, S.K. Paul, A. Singh, B. Sriram, K. Trivedi, Novel grounded inductance simulator using single OTRA. Int. J. Circuit Theory Appl. 42(10), 1069–1079 (2014) 9. C. Cakir, U. Cam, O. Cicekoglu, Novel allpass filter configuration employing single OTRA. IEEE Trans. Circuit. Syst. II Express Briefs 52(3), 122–125 (2005) 10. U. Cam, O. Cicekoglu, M. Gulsoy, H. Kuntman, New voltage and current mode first-order all-pass filters using single FTFN. Frequenz 54(7–8), 177–179 (2000) 11. P. Kumar, R. Senani, New grounded simulated inductance circuit using a single PFTFN. Analog Integr. Circ. Sig. Process 62, 105–112 (2010) 12. S. Tez, O.M. Tez, E. Yuce, Derivation of Lossless Grounded Inductor Simulators Based on Active Circuit Elements (ICAT, Antalya, 2018) 13. U. Cam, O. Cicekoglu, H. Kuntman, Universal series and parallel immittance simulators using four terminal floating nullors. Analog Integr. Circ. Sig. Process 25, 59–66 (2000) 14. R.L. Geiger, E. Sanchez-Sinencio, Active filter design using operational transconductance amplifiers: A tutorial. IEEE Circuit. Devices Magaz. 1(2), 20–32 (1985) 15. N. Herencsar, S. Minaei, J. Koton, E. Yuce, K. Vrba, New resistorless and electronically tunable realization of dual-output VM all-pass filter using VDIBA. Analog Integr. Circ. Sig. Process 74(1), 141–154 (2013) 16. A. Yesil, F. Kacar, K. Gurkan, Lossless grounded inductance simulator employing single VDBA and its experimental band-pass filter application. AEU Int. J. Electron. Commun. 68(2), 143–150 (2014) 17. A. Toker, S. Ozoguz, C. Acar, CDBA-based fully-integrated gyrator circuit suitable for electronically tunable inductance simulation. AEU Int. J. Electron. Commun. 54(5), 293–296 (2000) 18. C. Psychalinos, A. Spanidou, Current amplifier based grounded and floating inductance simulators. AEU Int. J. Electron. Commun. 60(2), 168–171 (2006) 19. N. Herencsar, J. Koton, K. Vrbra, CFTA-based active-C grounded positive inductance simulator and its application. Elektrorevue 1(1), 24–27 (2010) 20. D. Prasad, D.R. Bhaskar, A.K. Singh, New grounded and floating simulated inductance circuits using current differencing transconductance amplifiers. Radioengineering 19(1), 194–198 (2010) 21. W. Tangsrirat, Floating simulator with a single DVCCTA. Indian J. Eng. Mater. Sci. 20(2), 79–86 (2013) 22. S. Kilinc, U. Cam, Current-mode first-order allpass filter employing single current operational amplifier. Analog Integr. Circ. Sig. Process 41, 47–53 (2004)

Correction to: Unity Gain Cells

Correction to: Chapter 6 in: E. Yuce, S. Minaei, Passive and Active Circuits by Example, https://doi.org/10.1007/978-3-031-44966-6_6 The value of equation under Solution 6.7 has been corrected retrospectively to prevent any consequential errors.

The updated version of this chapter can be found at https://doi.org/10.1007/978-3-031-44966-6_6 © The Author(s), under exclusive license to Springer Nature Switzerland AG 2024 E. Yuce, S. Minaei, Passive and Active Circuits by Example, https://doi.org/10.1007/978-3-031-44966-6_10

C1

Index

A Admittance, 35, 36, 42–44, 169, 170, 185, 186, 196, 197, 202, 203, 208, 211, 212, 219–221, 230, 235–237, 249, 250 All-pass filter (APF), 17–19, 21, 23, 26, 27, 29, 31, 75, 78–79, 82, 85, 138, 158–162, 164, 176–178, 205, 212, 214–216, 233–235, 241, 250 Amplifiers, 13, 92–96, 98, 99, 108–120, 144, 149, 154, 191 Angular pole frequency, 31, 76, 80, 81, 110, 111, 116, 205 Angular resonance frequency, 8, 18, 22, 139 Attenuator, 154

B Band-pass filter (BPF), 17–20, 22–24, 26, 29, 82, 83, 85, 86, 141–143 Bandwidth (BW), 17, 18, 22, 65, 91, 118–120, 189 Bipolar junction transistor (BJT), 9, 98, 99

C C, 73, 75, 77, 79, 234, 251 Capacitors, 35–43, 46–49, 51–53, 59–61, 64, 91 Causality, 12, 15 Complex frequency domain, 35 Constant function, 1, 3 Current amplifier, 225 Current controlled CCII (CCCII), 189, 203–204 Current conveyors (CCs), 189–222, 251

Current differencing buffered amplifier (CDBA), 225, 243–244 Current differencing transconductance amplifier (CDTA), 225, 247–248 Current feedback operational amplifier (CFOA), 225–231 Current follower (CF), 151–153, 157–163, 165, 194 Current follower transconductance amplifier (CFTA), 225, 246–247 Current-mode (CM), 73, 74, 79–81, 84–86, 151, 158, 159, 164, 165, 167, 175, 176, 178, 179, 204, 205, 250 Current operational amplifier (COA), 225, 250–251

D DCCII, 206–207 Delta function, 2 Differential difference CC (DDCC), 189, 213–216 Differential voltage CC (DVCC), 189, 209–213 Differential voltage current conveyor transconductance amplifier (DVCCTA), 225, 248–250 Dual output DCCII (DO-DCCII), 206 Dual output ICCII (DO-ICCII), 204 Dual X CCII (DX-CCII), 189

E EX-CCCII, 189, 221, 222 Exponential function, 2, 7, 63

© The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature Switzerland AG 2024 E. Yuce, S. Minaei, Passive and Active Circuits by Example, https://doi.org/10.1007/978-3-031-44966-6

253

254 F First-generation CC (CCI), 189–193 First-order, 29–33, 46, 56, 75–81, 101–103, 138, 156–162, 164, 167, 176–180, 204, 205, 212, 214, 215, 233–235, 241, 250, 251 First-order analog filters, 138 First-order transfer function, 75–78, 160–162, 176–178, 180, 204, 212, 233, 235, 241, 250 Floating, 35, 40–42, 78, 123, 164, 185, 186 Fourier transforms, 15–16 Four-terminal floating nullor (FTFN), 225, 234, 235 Frequency dependent negative resistor (FDNR), 229 Frequency domain, 16, 22, 23, 26, 27, 31, 35, 37, 38, 43, 44, 56, 58–60, 66, 68, 69, 71, 76–78, 110, 116–118, 169, 170 Full-power bandwidth, 149–150 Full-wave rectified function, 1 Full-wave rectifier (FWR), 2, 4, 11, 132–135, 212, 213 Fully differential CCII (FDCCII), 189, 216–218

G Grounded, 35–39, 123, 181, 229

H Half-wave rectifiers (HWRs), 132 High-order transfer function, vi, 86 High-pass filter (HPF), 17–19, 21, 23, 25–27, 29, 30, 32, 75, 77–78, 80–83, 85, 101, 102, 157, 168, 205

I ICCII, 189, 204–206 Ideal filters, 17–19 Ideal first-order filter, 29–34 Ideal OAs, 90–92 Ideal second-order filters, 19–29 Impedance, 2, 73, 123, 151, 181, 190, 226 Inductor, 35, 36, 38–42, 46, 54–58, 61, 64, 123, 169, 171, 190, 195–198, 201–203 Instrumentation amplifier (IA), 163, 195, 209, 210

L L, 73, 75, 77, 79 Laplace transform, 15, 73

Index Linear time-invariant (LTI), 11, 12, 16, 73 Linearity, 11, 189 Lossless, 57–61, 123, 128–132, 165, 169, 171–173, 184, 185, 190, 207, 209, 221, 222, 229, 230, 236, 238, 239, 242, 243, 245–247, 249 Lossy, 123–128, 168–171, 182, 183, 190, 201–203 Low-pass filter (LPF), 17, 19, 22–24, 26–30, 32–34, 75–76, 80, 82, 84–86, 101, 102, 139–141, 156, 168, 205

M Magnitude, 8, 16, 27, 36–40, 43, 44, 57–59, 61, 66–72, 89, 110, 116, 132, 168, 169, 171

N Negative impedance converter (NIC), 175, 179–188, 194 Non-linearity, v Notch filter (NF), 17–20, 22, 23, 25–27, 82, 83, 85

O Operating frequency range, 57–60, 168, 169, 171 Operational amplifier (OA), 89–150, 189 Operational transconductance amplifier (OTA), 225, 238–241, 251 Operational transresistance amplifier (OTRA), 225, 232–234

P Parallel, 8, 42, 43, 53, 57–61, 63, 65–68, 70, 71, 123, 124, 168–171, 182, 202, 203, 220, 237 Passive elements, 8, 35, 36, 86 Phase, 1, 16, 19–27, 29–34, 36–40, 43, 44, 56–59, 61, 65–72, 76, 77, 79, 86, 92, 116, 168, 169, 171, 205 Positive half-wave rectified function, 1 Practical OA, 90 Prefixes, 1, 3

Q Quadrature oscillator (QA), 192, 231 Quality factor, 18–22, 24–26, 56, 139

Index R R, 73, 75, 79, 155, 156, 178, 182–184, 188, 234, 251 RC circuit, 46, 56, 59, 60, 79 Resistor, 9, 11, 35–41, 43, 46–49, 51, 53, 54, 56, 61, 64, 91, 96, 99, 107, 120, 164, 203, 229 RL topology, 56, 57, 237 RLC structure, 64, 71

S Sawtooth wave function, 2, 6 s domain, 35, 40, 44, 45, 56, 57, 59, 60, 97, 110, 145, 146, 169, 170 Second-generation CC (CCII), 189, 193–201, 225, 226 Second-order analog filters, 138 Second-order filters, 138 Second-order transfer function, 139–143 Second-order universal filter, 19, 27 Sensitivity, 6–10 Series, 8, 42, 43, 56, 57, 59, 64–66, 69, 125–127, 183, 201, 202, 226 Signal, 2, 11–15, 39, 92, 144–146 Simulated floating inductor (SFI), 190, 196–198, 211, 212, 230, 249 Simulated grounded inductor (SGI), 123–132, 165, 168–173, 182–185, 190–192, 195, 196, 203, 204, 206–210, 217, 220, 222, 227–229, 232, 235–240, 242–248 Sine wave function, 1, 4 Slew rate (SR), 91, 145–149 Some basic circuits, 92–108 Square wave function, 2, 5 Stability, 15, 44, 92 Subtractor connected CCI (S-CCI), 189 Symbols, 1–3, 35, 89, 151, 152, 163, 164, 166, 175, 176, 179, 180, 189, 190, 193, 194, 201, 203, 204, 206–209, 213, 214, 216,

255 218, 219, 221, 225, 226, 232, 234, 238–240, 242, 243, 245–250 Systems, 1, 2, 11–15, 73

T Third-generation CC (CCIII), 189, 201–203 Time domain, 16, 35, 39, 47–56, 97 Time-invariant, 12 Time-variant, v Total harmonic distortion (THD), 13, 14, 91 Transadmittance-mode (TAM), 73–75 Triangular wave function, 2, 6

U Unit ramp functions, 1, 3 Unit step function, 2 Units, 1–3, 145 Unity gain cells (UGCs), 151–173 Unity gain inverting amplifier (UGIA), 82, 175–179, 191

V Voltage differencing buffer amplifier, 225 Voltage differencing inverting buffered amplifier, 225 Voltage follower (VF), 105, 108, 110, 112, 145–149, 151, 166, 167, 176, 177, 187, 191, 194, 225, 226 Voltage-mode (VM), 73–79, 81–84, 86, 153–162, 167, 176–178, 180, 187, 188, 212–215, 233–235, 241

W Wien oscillators, 135–138, 186, 187