Nanometer CMOS ICs: from Basics to ASICs [1 ed.] 1402083327, 9781402083327

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Nanometer CMOS ICs

Nanometer CMOS ICs From basics to ASICs

Harry Veendrick

ｾ

Springer the languag of sci nee

my businessm edia

Nanometer CMOS ICs Author: Dr. Ir. H.J .M.Veendrick NXP Semicond uctors-Research E-m ail: [email protected] Cover design: Bram Veendrick Photographs used in cover: NXP Semiconductors Typesetting and layout: Harold Bent en and Dre van den Elshout Illustrations: Kim Veendrick and Henny Alblas First English edition: 2008 This book is based on variou s previous publi cations. The first original 1990 publication (Delt a Press b.v.) was in t he Dutch language. In 1992 a revised , updated and translat ed English edit ion of that book was jointly published by VCR Verlagsgesellschaft (Weinheim, Germany) and VCR Publishers Inc. (NY, USA). The t hird book , ent it led Deep-Submicron CMOS ICs: from Basics to ASICs , was a joint publication of Ten Ragen en St arn, Devent er, The Netherland s, and Kluwer Acad emic Publishers, Boston, USA) and published in two edit ions (1998 and 2000). Thi s new book covers th e same subjects , but t hen t hey are completely revised and upd at ed with the most recent st ate-of-the-art material. It covers all subjects, related to nanomet er CMOS ICs: physics, technologies, design, t esting, packaging and failure ana lysis. The conte nts have increased by almost one third , leading to a much more detailed and complete description of most of th e subjects. Thi s new book is almost full colour .

ISBN 978-1-4020-8332-7

NUR 950

© 2008 Springer , Heidelberg, New York, Tokyo Mybus inessmedia, Deventer, The Netherlands All right s reserved. No part of this book may be reproduced , stored in a da tabase or retrieval system, or published, in any form or in any way, electronically, mechanically, by print , photo print, microfilm or any other means without prior written permission from the publisher. Information pub lished in t his work, in any form , may be subject to patent rights and is int ended for study purposes and privat e use only. Although this book and its conte nts were produced with great care, neither the author nor the publisher can guar antee th at th e information contained therein is free from err ors. Readers are advised to keep in mind th at st at ements , data, illustrations, pro cedural detai ls or other items may inadvertently cont ain inaccuracies. This book cont ains many sources and references of t ext , photographs and illustrations. Although the author has given a lot of atte nt ion to carefully refer to t he source of related material, he already apologi zes for th e one or few individu al occasions that this has slipp ed his final review.

Foreword CMOS scaling is now entering the deca-nanometer era. This enables the design of systems-on-a-chip containing more than 10 billion transistors. However, nanometer level device physics also causes a plethora of new challenges that percolate all the way up to the system level. Therefore system-on-a-chip design is essentially teamwork requiring a close dialogue between syst em designers, software engineers , chip architects, intellectual property providers, and process and device engineers. This is hardly possibl e without a common understanding of the nanometer CMOS medium, its terminology, its future opportunities and possibl e pitfalls. This is what this book provides . It is a greatly extended and revised version of the previous edition that was addressing deep-submicron CMOS systems. So besides the excellent coverage of all basic aspects of MOS devices, circuits and systems it leads the reader into the novel intricacies resulting from scaling CMOS down to the deca-nanometer level. New in this edition is the attention to the issues of increased leakage power and its mitigation, to strain induced mobility enhancement and to sub45 nm lithographic techniques. Immersion and double patterning litho the use of high index fluids as well as of extreme UV and other altern at ive litho approaches for sub 32 nm are extensively discussed together with their impact on circuit layout. The design section now also extensively covers design techniques for improved robustness, yield and manufacturing in view of increased device variability, soft errors and decreased reliability when reaching atomic dimensions. In the packaging section attention is paid to rapidly emerging 3D integration techniques. Finally the author shares his thoughts on the challenges of further scaling when approaching the end of the CMOS roadmap by 2015. This book is unique in that it covers in a very comprehensive way all aspects of the trajectory from process technology to the design and packaging of robust and testable systems in nanometer scale CMOS . It is the reflection of the author's own research in this domain but also of almost 30 years experience in interactive teaching of CMOS design to NXP and PHILIPS system designers and process engineers alike. It provides context and perspective to both sides . I strongly recommend this book to all engineers involved in the design and manufacturing of future systems-on-silicon as well as to engineering undergraduates who want to understand the basics that make electronics systems work. Leuven, February 2008 Hugo De Man Professor Emeritus K.U . Leuven Senior Fellow IMEC Leuven Belgium v

Preface An integrated circuit (IC) is a piece of semiconductor material, on which a number of electronic components are interconnected. These interconnected 'chip' components implement a specific function. The semiconductor material is usually silicon but alternatives include gallium arsenide. ICs are essential in most modern electronic products. The first IC was created by Jack Kilby in 1959. Photographs of this device and the inventor are shown in figure 3. Figure 1 illustrates the subsequent progress in IC complexity. This figure shows the numbers of components for advanced ICs and the year in which these ICs were first presented. This doubling in complexity every two years was predicted by Moore (Intel 1964), who's law is still valid today for the number of logic transistors on a chip . However, due to reaching the limits of scaling, the complexity doubling of certain memories now happens at a three-year cycle. This is shown by the complexity growth line which is slowly saturating. Figure 2 shows the relative semiconductor revenue per IC category. CMOS ICs take about 75% of the total semiconductor market . Today's digital ICs may contain several hundreds of millions to more than a billion transistors on one single 1 cm 2 chip. They can be subdivided into three categories: logic, microprocessors and memories . About 10% of the CMOS ICs are of an analog nature. Figures 4 to 7 illustrate the evolution in IC technology. Figure 4 shows a discrete BCI07 transistor. The digital filter shown in figure 5 comprises a few thousand transistors while the Digital Audio Broadcasting (DAB) chip in figure 6 contains more than six million transistors. The Intel Pentium4 Xeon dual-core processor in figure 7.25 (section 7.6), contains 1.3 billion transistors. Figure 7 shows an 8 Gb 63 nm multi-level NAND-flash memory chip. Figure 8 illustrates the sizes of various semiconductor components, such as a silicon atom, a single transistor and an integrated circuit, in perspective. The sizes of an individual MaS transistor are approaching the details of a virus.

vi

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Figure 2: Relative semiconductor revenue by IC category (Source: IC Insights)

Vll

This book provides an insight into all aspects associated with CMOS ICs . The topics presented include relevant fundamental physics. Technology, design and implementation aspects are also explained and applications are discussed. CAD tools used for the realisation of ICs are described while current and expected developments also receive attention. The contents of this book are based on the CMOS section of an industry-oriented course entitled 'An introduction to IC techniques'. The course has been given almost three decades, formerly in Philips, currently in NXP Semiconductors. Continuous revision and expansion of the course material ensures that this book is highly relevant to the IC industry. The level of the discussions makes this book a suitable introduction for designers , technologists, CAD developers, test engineers, failure analysis engineers, reliability engineers, technical-commercial personnel and IC applicants. The text is also suitable for both graduates and undergraduates in related engineering courses. Considerable effort has been made to enhance the readability of this book and only essential formulae are included. The large number of diagrams and photographs should reinforce the explanations. The design and application examples are mainly digital. This reflects the fact that more than 90% of all modern CMOS ICs are digital circuits. However, the material presented will also provide the analogue designer with a basic understanding of the physics, manufacture and operation of nanometer CMOS circuits. The chapters are summarised below. For educational purposes the first four chapters each start with a discussion on nMOS physics, nMOS transistor operation, nMOS circuit behaviour, nMOS manufacturing process, etc. Because the pMOS transistor operation is fully complementary to that of the nMOS transistor, it is then easier to understand the operation and fabrication of complementary MOS (CMOS) circuits. The subjects per chapter are chosen in a very organised and logical sequence so as to gradually built the knowledge, from Basics to ASICs. The knowledge gathered from each chapter is required to understand the information presented in the next chapter(s) . Each chapter ends with a reference list and exercises. The exercises summarise the important topics of the chapter and form an important part of the complete learning process. Chapter 1 contains detailed discussions of the basic principles and fundamental physics of the MOS transistor. The derivation of simple current-voltage equations for MOS devices and the explanation of their characteristics illustrates the relationship between process parameters

Vlll

and circuit performance. The cont inuous redu ction of transistor dimensions leads to increased deviation between the performance predicted by the simple MOS formulae and actual transistor behaviour. The effects of temp erature and the impact of the cont inuous scaling of the geometry on this behaviour are explained in chapte r 2. In addition to their influence on transistor and circuit perform ance, t hese effects can also reduce device lifetime and reliability. The various technologies for the manufacture of CMOS ICs are examined in chapte r 3. After a summary on the available different substrat es (wafers) used as starting material, an explanation of the most important associated photolithographic and processing steps is provid ed. This precedes a discussion of an advanced nanom et er CMOS technology for the manufacture of modern VLSI circuits. The design of CMOS circuits is treated in chapter 4. An introduction to the performance aspects of nMOS circuits provides an ext remely useful background for the explanat ion of the CMOS design and layout procedures. MOS technologies and th eir derivatives are used to realise the special devices discussed in chapter 5. Charge-coupled devices (CCDs) , CMOS imagers and MOS power transistors are among t he special devices. Chapter 5 conclude s the presentation of the fund ament al concepts behind BICMOS circuit operation. Stand-alone memories currently repr esent about 25% of the tot al semiconductor market revenue. However , also in logic and microprocessor les embedded memories repr esent close to 80% of th e total transistor count . So, of all transistors produced in the world, tod ay, about 90% end up in either a st and-alone, or in an embedded memory. This share is expected to st ay at thi s level or to increase. The majority of available memory types are t herefore examined in chapter 6. The basic structures and the operating principles of th e various typ es are explained. In addit ion, the relationships between t heir respective prop erties and applicat ion areas is made clear. Development s in IC technology now facilitate the int egration of complet e syst ems on a chip, which contain several hundreds of millions to more than a billion of transistors. The various IC design and realisation t echniqu es used for these VLSI ICs are present ed in chapter 7. The advantages and disadvantages of the techniqu es and the associated CAD tools are examined. Various modern technologies ar e used to realise a

IX

separate class of VLSI ICs, which are specified by applicants rather than manufacturers. These application-specific ICs (ASICs) are examined in this chapter as well. Motives for their use are also discussed. As a result of the continuous increase of power consumption, the maximum level that can be sustained by cheap plastic packages has been reached. Therefore, all CMOS designers must have a 'less-power attitude'. Chapter 8 presents a complete overview of less-power and less-leakage options for CMOS technologies, as well as for the different levels of design hierarchy. Increased VLSI design complexities, combined with higher frequencies create a higher sensitivity to physical effects. These effects dominate the reliability and signal integrity of nanometer CMOS ICs. Chapter 9 discusses these effects and the design measures to be taken to maintain both reliability and signal integrity at a sufficiently high level. Finally, testing, yield , packaging, debug and failure analysis are important factors that contribute to the ultimate costs of an IC. Chapter 10 presents an overview of the state-of-the-art techniques that support testing, debugging and failure analysis. It also includes a rather detailed summary on available packaging technologies and gives an insight into their future trends. Essential factors related to IC production are also examined; these factors include quality and reliability. The continuous reduction of transistor dimensions associated with successive process generations is the subject of the final chapter (chapter 11). This scaling has various consequences for transistor behaviour and IC performance. The resulting increase of physical effects and the associated effects on reliability and signal integrity are important topics of attention. The expected consequences of and road blocks for further miniaturisation are described. This provides an insight into the challenges facing the IC industry in the race towards nanometer devices . Not all data in this book is completely sprout from my mind . A lot of books and papers contributed to make the presented material stateof-the-art. Considerable effort has been made to make the reference list complete and correct. I apologize for possible imperfections. Acknowledgements I wish to express my gratitude to all those who contributed to the realisation of this book; it is impossible to include all their names. I greatly value my professional environment: Philips Research labs, of which the semiconductor research department is now part of NXP Semiconductors.

x

It offered me the opportunity to work with many internationally highly valued colleagues who are all real specialists in their field of semiconductor expertise. Their contributions included fruitful discussions, relevant texts and manuscript reviews. I would like to make an exception, here, for my colleagues Marcel Pelgrom and Maarten Vertregt, who greatly contributed to the discussions held on trends in MOS transistor currents and variability matters throughout this book and Roger Cuppens and Roelof Salters for the discussions on non-volatile and random-access memories , respectively. I would especially like to thank Andries Scholten and Ronald van Langevelde for reviewing chapter 2 and for the discussions on leakage mechanisms in this chapter, Casper Juffermans and Johannes van Wingerden for their inputs to and Ewoud vreugdenhil (ASM Lithography) for his review of the lithography section in chapter 3. I would also like to sincerely thank Robert Lander for his detailed review of the section on CMOS process technologies and future trends in CMOS devices and Gerben Doornbos for the correct sizes and doping levels used in the manufacture of state-of-the-art CMOS devices. I appreciate the many circuit simulations that Octavio Santana has done to create the tapering-factor table in chapter 4. I am grateful for the review of chapter 5 on special circuits and devices based on MOS transistor operation: Albert Theuwissen (Harvest Imaging) for the section on CCD and image sensors , Johan Donkers and Erwin Hijzen for the BICMOS section and Jan Sonsky for the high voltage section. I also appreciate their willingness to supply me with great photographic material. Toby Doorn and Ewoud Vreugdenhil are thanked for their review of the memory chapter (chapter 6). I appreciate Paul Wielage's work on statistical simulations with respect to memory yield loss. I thank Ad Peeters for information on and reviewing the part on asynchronous design in the low-power chapter (chapter 8). Reliability is an important part of chapter 9, which discusses the robustness of ICs. In this respect I want to thank Andrea Scarpa for reviewing the hot-carrier and NBTI subjects, Theo Smedes for the ESD and latch-up subjects and Yuang Li for the part on electromigration. I also greatly value the work of Bram Kruseman , Henk Thoonen and Frank Zachariasse for reviewing the sections on testing, packaging and failure analysis, respectively. I also like to express them my appreciation for supplying me with a lot of figures and photographs, which support and enrich the discussions on these subjects in chapter 10. Finally, I want to thank Chris Wyland and John Janssen,

xi

for their remarks and additions on electrical and thermal asp ects of Ie packages, respectively I am very grateful to all those who attended the course, because their feedback on educational aspects, their corrections and constructive criticism contributed to the quality and completeness of this book. In addition, I want to thank Philips Research and NXP Semiconductors, in general for the co-operation I was afforded. I thank my son Bram for the layout of the cover and the layout diagrams in chapter 4, and Ron Salfrais for the correctness of a large part of the English text . I would especially like to express my gratitude to my daughter Kim and Henny Alblas for the many hours they have spent on the creation of excellent and colourful art work, which contributes a lot to the quality and clarity of this book. Finally, I wish to thank Harold Benten and Dre van den Elshout for their conscientious editing and type-setting work. Their efforts to ensure high quality should not go unnoticed by the reader. However, the most important appreciation and gratitude must go to my family, again, and in particular to my wife, for her years of exceptional tolerance, patience and understanding. The year 2007 was particularly demanding. Lost hours can never be regained , but I hope that I can give her now a lot more free tim e in return. Harry J .M. Veendrick

Eindhoven, February 2008

xii

Fi gure 3: Th e developm ent of the first IC: in 1958 Jack Kilby demonstrated the feasibility of resistors and capacitors, in addition to transistors, based on semi conductor technology. Kil by, an employee of Texas Instrum ents, submitted the patent request entitled 'Miniaturized Electronic Circuits ' in 1959. His request was honoured. Recognition by a number of Japanese companies in 1990 means that Texas Instrum ents is still benefiting from Kilby 's patent (Source: Texas Instrum ents / Koning & Hartm an).

Xlll

Figure 4: A single BC107 bipolar transistor (Source: NXP Semiconductors)

XIV

Figure 5: A digital filter which com prises a few thou sand transistors (Source: NX P Semicondu ctors)

xv

Figure 6: A Digital Audio Broadcasting (DAB) chip, which comprises more th an six million transistors (Source: NXP Semiconductors)

xvi

Figure 7: An 8 Gb 63nm ML C NAND Chip Layou t (Source: Samsung)

xv ii

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Fi gure 8: Various semiconductor com ponent sizes (e.g., atom, transistor, int egrated circuit) in perspective

XV lll

Overview of symbols

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Cg Cgb Cgd Cgs Cgdo

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Cs Cox

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chann el-shor tening factor or clustering factor area aspect ratio activity factor MOS transistor gain factor gain factor for MOS tr ansistor with square channel nMOS transistor gain factor pMOS t ra nsistor gain factor equivalent gain factor for a combination of t ra nsistors breakdown voltage capacitance bitline capacitance depletion layer capacitance dr ain-substrate capacitance gate capacitance gate-substrate capacitance gate-drain capacitance gate-source capacitance voltage-independent gate-drain capacitance voltage-independent gate-source capacitance parasitic capacitance minimum capacitance scaled capacitance oxide capacitance silicon sur face-inte rior capacitance source-substrate (source-bulk) volt age total capacitance crit ical dimension difference between drawn and effective channel length t hreshold volt age variat ion defect density for uniformly distri buted errors (dust particles) xix

tax tr tsi

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Ion

IR i(t)

threshold-voltage channel-length dependence factor threshold-voltage channel-width dependence factor dielectric constant absolute permittivity relative permittivity of oxide relative permittivity relative permittivity of silicon electric field strength conduction band energy level Fermi energy level intrinsic (Fermi) energy level maximum horizontal electric field strength electric field across an oxide layer valence band energy level horizontal electric field strength critical horizontal field strength vertical electric field strength electric potential Fermi potential surface potential of silicon w.r.t. the substrate interior contact potential between gate and substrate feature size (= size of a half pitch used for stand-alone memories)) clock frequency maximum clock frequency factor which expresses relationship between drain-source voltage and threshold-voltage variation transconductance current substrate current drain-source current characteristic sub-threshold current for gate-substrate voltage of 0 V driver transistor drain-source current load transistor drain-source current saturated transistor drain-source current sub-threshold drain-source current maximum current on current current through resistance time-dependent current

xx

j

cur rent densisty Boltzman's constant k K K-factor; expresses relationship between source -subst rate volt age and threshold voltage amplificat ion factor K wavelength of light A effect ive transistor channel length and inductance L channel length reduction due to channel length modulation LCLM effect ive channel length L effect ive channel length of reference transistor Lre yield mod el par am eter !vI substrate carrier mobili ty /10 channel elect ron mobility /1n channel hole mobility /1p subst ra te doping concent rat ion NA numeric aperture N.A. charge density power dissipati on P dynamic power dissipation Pdy n static power dissipation st at volt age scaling factor p charge Q q elementary cha rge of a single elect ron depletion layer charge Qd gate cha rge Qg total mobil e cha rge in t he inversion layer Qrn mobil e cha rge per uni t area in t he channel Qn oxide cha rge total cha rge in t he semiconductor Qs resistan ce R junction-to-air thermal resistance RJA junction-to-case thermal resist an ce RJ C load resistance RL output resist an ce or cha nnel resist an ce Rout R th errn t hermal resist an ce of a package t apering factor r scale factor S Ssubth r sub-t hreshold slope delay time T

a;

xxi

fall time rise time TR dielectric relaxation time T clock period Tmin minimum clock period T emp te mperature T empi; ambient tem perature T empe case te mperature T empJ junction tem perature 1if t ra nsistor lifeti me t time t cond conducto r thickness t« depletion layer t hickness t d ielectric dielectric thickness t ox gate-oxide t hickness ti s isolat or thickness U comput ing power v carrier velocity Vsat car rier saturation velocity V voltage VB breakdown voltage v;. scaled voltage Va deplet ion layer voltage substrate voltage Vbb Vdd supply voltage ｾ voltage at silicon surface Vd s dr ain-source voltage drain-source voltage of saturated t ransistor Vdssat VE Early voltage Vf b flat-band volt age Vg gate voltage Vgg ext ra supply volt age gat e-source volt age Vgs VgsL load t ra nsistor gate-source volt age VH high voltage level Vin input voltage Vj junction voltage VL low voltage level VPT t ra nsistor pu nch-through voltage Tf

Tr

XX ll

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VT pa r Vout V(X) Vx VX L

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source-substrate (back-bias) voltage ground voltage well-source voltage threshold voltage driver transistor threshold voltage depletion transistor threshold voltage enhancement transistor threshold voltage load transistor threshold voltage nMOS transistor threshold voltage pMOS transistor threshold voltage parasitic transistor threshold voltage output voltage potential at position x process-dependent threshold voltage term process-dependent threshold voltage term for load transistor process-dependent threshold voltage term for driver transistor transistor channel width nMOS transistor channel width pMOS transistor channel width reference transistor channel width transistor aspect ratio nMOS transistor aspect ratio pMOS transistor aspect ratio distance w.r.t. specific reference point yield input impedance

xxiii

List of physical constants

EO Eox

Esi

cPr k q

= 8.85 X 10- 12 F j m

= 4 for silicon dioxide = 11.7 = 0.5 V for silicon substrate = 1.4 X 10- 23 JoulejK = 1.6 X 10- 19 Coulomb

xxiv

Contents v

Forewo rd

vi

Preface

xi x

Overview of sym b ols List of physical constants

x xiv

1 B a sic P rinciples 1.1 Introduct ion . . . . . . . . . . . . . . 1.2 The field-effect prin ciple . . . . . . . 1.3 The inversion-layer MaS tra nsisto r . 1.3.1 T he Metal-Oxide-Semiconducto r (MaS) capacitor " 1.3.2 The inversion-layer Ma S t rans istor 1.4 Derivation of simple Ma S formulae. . . . . . . . . . . . . 1.5 The back-bias effect (back-gate effect, body effect) and the effect of forward-bias " 1.6 Factors which characterise t he behaviour of t he MaS transist or. . . . . . . . . . . . . . . . . 1.7 Different typ es of MaS transistors 1.8 Parasitic MaS tr ansistors . . . . 1.9 MaS transistor symbols . . . . . 1.10 Capacitances in MaS structures 1.11 Conclusions 1.12 References . 1.13 Exercises .

1 1 1 4 11 15 23 27 30 32 34 36 38 48 49 50

2 Geometrical- , physi cal- and field-scaling impact on MOS t r a nsist or behaviour 57 2.1 Introduction . .. . . . . . . . . . .. . . . . . . . . . . . . 57 xxv

The zero field mobili ty . . . .. .. Carrier mobili ty reduction. .. 2.3.1 Vertical and lat eral field carrier mobility redu ction 2.3.2 St ress-induced carrier mobility effects 2.4 Channel length modulation 2.5 Short- and narrow-channel effects . 2.5.1 Short-channel effects . 2.5.2 Narrow-cha nnel effect 2.6 Temp erature influence on carrier mobility and threshold voltage . 2.7 MaS transist or leakage mechanisms 2.7.1 Weak-inversion (subthreshold ) behaviour of the MaS transistor . 2.7.2 Gate-oxide tunnelling 2.7.3 Reverse-bias junction leakage 2.7.4 Gate-induced dr ain leakage (GIDL) 2.7.5 Impact Ionisation . 2.7.6 Overall leakage int eractions and considerations 2.8 MaS transistor models . 2.9 Conclusions 2.10 References . 2.11 Exercises 2.2 2.3

3

Manufacture of M OS devices 3.1 Introduct ion. . . . . . . . . . .. .. . . . . . . . 3.2 Different substrates (wafers) as starting material 3.2.1 Wafer sizes . . . . . . . . . . . . . . . . . 3.2.2 Standard CMOS Ep i . . . . . . . . . . . . 3.2.3 Cryst alline orientation of the silicon wafer 3.2.4 Silicon-on-insulator (Sal) 3.3 Lithography in MaS processes . . . . . . . . . . 3.3.1 Lit hography basics . . . . . . . . . . . . . 3.3.2 Lithographic alte rn at ives beyond 40 nm . 3.3.3 Next generation lit hography. . . . . . . . 3.3.4 Mask cost redu ct ion techniques for low-volume produ ction . 3.4 Etching . . . 3.5 Oxidation . . . . 3.6 Deposition . .. . 3.7 Diffusion and ion impl ant ation .

xxv i

58 59 59 63 64 66 66 69 71 74 75 78 80 81 82 83 86 88 89 91 93 93 95 95 95 98 99 105 105 121 124

126 131 134 137 142

3.8 Planarisation . . . . . . . . . . . . . . . . . . . 3.9 Basic MOS technologies . . . . . . . . . . . . . . 3.9.1 The basic silicon-gate nMOS process. 3.9.2 The basic Complementary MOS (CMOS) process. 3.9.3 An advanced nanometer CMOS process . . 3.9.4 CMOS technology options beyond 45nm . . 3.10 Conclusions . 3.11 References . . 3.12 Exercises . .

4 CMOS circuits 4.1 Introduction... . . . . . 4.2 Th e basic nMOS inverter 4.2.1 Introduction . .. 4.2.2 The DC behaviour 4.2.3 Comparison of the different nMOS inverters . 4.2.4 Transforming a logic function into an nMOS transistor circuit 4.3 Electrical design of CMOS circuits 4.3.1 Introduction . . . . 4.3.2 The CMOS inverter 4.4 Digital CMOS circuits . . . 4.4.1 Introduction . . . . 4.4.2 Static CMOS circuits 4.4.3 Clocked static CMOS circuits . 4.4.4 Dynamic CMOS circuits . . . . 4.4.5 Other types of CMOS circuits. 4.4.6 Choosing a CMOS implementation 4.4.7 Clocking strategies . . . . . . . . 4.5 CMOS input and output (I/O) circuits. 4.5.1 CMOS input circuits. . . . . . 4.5.2 CMOS output buffers (drivers) 4.6 The layout process . . . . . 4.6.1 Introduction . . . . 4.6.2 Layout design rules. 4.6.3 Stick diagram . . . . 4.6.4 Example of the layout procedure 4.6.5 Guidelines for layout design 4.7 Conclusions 4.8 References . . . .. .. XXVII

. . . . .

146 153 153 158 160 168 178 179 183

185 185 186 186 188 196

. 197 . 200 . 200 . 201 . 218 . 218 . 219 . 225 . 228 . 234 . 235 . 236 . 237 . 237 . 238 . 240 . 240 . 241 . 245 . 248 . 252 . 254 . 255

4.9

Exercises

.

. 257

5 Special circuits, devices and technologies 5.1 Introduction .. .. . . . . . . . 5.2 CCD and CMOS image sensors 5.2.1 Introduction . . . . . 5.2.2 Basic CCD operation 5.2.3 CMOS image sensors . 5.3 Power MOSFET transistors . 5.3.1 Introduction .. . . . 5.3.2 Technology and operation 5.3.3 Applications .. 5.4 BICMOS digital circuits . . 5.4.1 Introduction .. .. 5.4.2 BICMOS technology 5.4.3 BIGMOS characteristics 5.4.4 BICMOS circuit performance 5.4.5 Future expectations and market trends. 5.5 Conclusions 5.6 References. 5.7 Exercises

261 . 261 . 262 . 262 . 262 . 267 . 270 . 270 . 271 . 274 . 275 . 275 . 276 . 279 . 280 . 283 . 284 . 285 . 287

6 Memories 6.1 Introduction .. . . . . . . . . . . . . . 6.2 Serial memories . . . . . . . . . . . . . 6.3 Content-addressable memories (CAM) 6.4 Random-access memories (RAM) 6.4.1 Introduction 6.4.2 Static RAMs (SRAM) . . 6.4.3 Dynamic RAMs (DRAM) 6.4.4 High-performance DRAMs 6.4.5 Single- and dual port memories 6.4.6 Error sensitivity 6.4.7 Redundancy .. 6.5 Non-volatile memories 6.5.1 Introduction .. 6.5.2 Read-Only Memories (ROM)

. . . . . . . . . . . . . .

289 289 293 294 294 294 294 310 321 327 328 328 329 329 329

6.5.3

Programmable Read-Only Memories

. 334

6.5.4 6.5.5

EEPROMs and flash memories Non-volatile RAM (NVRAM) .

. 337 . 345

xxviii

6.6 6.7 6.8 6.9 6.10

6.5.6 BRAM (battery RAM) 6.5.7 FRAM , MRAM, PRAM (PCM) and RRAM Embedded memories . . . . . . . . . . Classification of the various memories Conclusions References. Exercises .

. . . . . . .

346 346 350 353 355 357 362

365 7 Very Large Scale Integration (VLSI) and ASICs 7.1 Introduction . . . . . . . . . . 365 7.2 Digital ICs . 368 7.3 Abstraction levels for VLSI . 373 7.3.1 Introduction . . . 373 7.3.2 System level . . . . 376 7.3.3 Functional level . . 379 7.3.4 RTL level . . . . . 380 7.3.5 Logic-gate level . . 383 7.3.6 Transistor level . 384 7.3.7 Layout level. . 386 7.3.8 Conclusions. . 386 7.4 Digital VLSI design . 389 7.4.1 Introduction . 389 7.4.2 The design trajectory and flow . 389 7.4.3 Example of synthesis from VHDL description to layout . . . . . . . . . . . . . . . 394 7.5 The use of ASICs . . . . . . . . . . . . . 402 7.6 Silicon realisation of VLSI and ASICs . 403 7.6.1 Introduction . 403 7.6.2 Hand crafted layout implementation . 406 7.6.3 Bit-slice layout implementation . . . . 407 7.6.4 ROM, PAL and PLA layout implementations . 408 7.6.5 Cell-based layout implementation. . . . . . 413 7.6.6 (Mask programmable) gate array layout implementation . . . . . . . . . . . . . . . . . . . . . . . 415 7.6.7 Programmable Logic Devices (PLDs) 420 7.6.8 Embedded Arrays , Structured ASICs and platform ASICs . . . . . . . . . . . . . . . . . . . . 434 7.6.9 Hierarchical design approach . 438 7.6.10 The choice of a layout implementation form . 439 . . . . . . . . . . . . . . 443 7.7 Conclusions. .. . .. XXIX

7.8 7.9

8 Low 8.1 8.2 8.3 8.4

8.5

8.6 8.7 8.8 8.9

References . Exercises .

.444 .445

power, a hot topic in IC design 447 Introduction.............. . 447 Battery technology summary . . . . . 448 Sources of CMOS power consumption . 450 Technology options for low power . . . . 452 8.4.1 Reduction of l1eak by technological measures . 452 8.4.2 Reduction of Pdyn by technology measures . . . 457 8.4.3 Reduction of Pdyn by reduced-voltage processes . 459 Design options for power reduction . . . . . . . . . . . . 462 8.5.1 Reduction of Pshort by design measures . . . . . . 462 8.5.2 Reduction/elimination of P stat by design measures 464 8.5.3 Reduction of P dyn by design measures 465 Computing power versus chip power, a scaling perspective 501 Conclusions . 504 References. . 505 Exercises . . 509

9 Robustness of nanometer CMOS designs: signal integrity, variability and reliability 511 9.1 Introduction 511 9.2 Clock generation, clock distribution and critical timing. . 513 9.2.1 Introduction 513 514 9.2.2 Clock distribution and critical timing issues 9.2.3 Clock generation and synchronisation in different (clock) domains on a chip . . . . . . 523 . 527 9.3 Signal integrity . . . . . . . . . . . . . . . . . . . . 528 9.3.1 Cross-talk and signal propagation . . . . . . 535 9.3.2 Power integrity, supply an ground bounce . 539 9.3.3 Substrate bounce . . 542 9.3.4 EMC . .543 9.3.5 Soft errors . .547 9.3.6 Signal integrity summary and trends .550 9.4 Variability... .. . . . . . . . . . . . . 9.4.1 Spatial vs. time-based variations . 550 . 550 9.4.2 Global vs. local variations .. .. 9.4.3 Transistor matching . . . . . . . .554 9.4.4 From deterministic to probabilistic design .557 xxx

9.4.5 Can the variability problem be solved? . 9.5 Reliability . . .. . . . . 9.5.1 Punch-through.. . .. 9.5.2 Electromigration . . . . 9.5.3 Hot-carrier degradation 9.5.4 Negative bias temperature instability (NBTI) 9.5.5 Latch-up 9.5.6 Electro-Static Discharge (ESD) . . . . . . . . 9.5.7 Charge injection during th e fabrication process 9.5.8 Reliability summary and trends . 9.6 Design organisation. 9.7 Conclusions 9.8 References. 9.9 Exercises .

. . . . . . . . . . . . . .

559 559 560 560 563 568 569 573 578 578 579 581 583 587

10 Testing, yield, packaging, debug and failure analysis 589 10.1 Introduction . . . . . . . 589 10.2 Testing . 591 10.2.1 Basic IC tests. . . . . . 594 10.2.2 Design for testability . . 608 10.3 Yield . . . . . . . . . . . . . . . 610 10.3.1 A simple yield model and yield control. . 614 10.3.2 Design for manufacturability . 620 10.4 Packaging . . . . . . . . . . 623 10.4.1 Introduction . 623 10.4.2 Package categories . . . . 624 . 627 10.4.3 Packaging process flow . 10.4.4 Electrical aspects of packaging . 633 10.4.5 Thermal aspects of packaging . . 635 10.4.6 Reliability aspects of packaging . . 637 10.4.7 Future trends in packaging technology . 639 10.4.8 System-on-a-chip (SoC) versus system-in-a-package (SiP) . . . . . . . . . . . . . . . . . . . . . 641 10.4.9 Quality and reliability of packaged dies . 645 10.4.10 Conclusions . . . . . . . . 647 10.5 Potential first silicon problems . 648 10.5.1 Problems with testing . . . . . . . . . . . 648 10.5.2 Problems caused by marginal or out-of-specification processing . . . . . . . . . . . . . 650 10.5.3 Problems caused by marginal design . . . . . . . . 653 xxxi

10.6 First-silicon debug and failure analysis . 10.6.1 Introduction . 10.6.2 Iddq and Ll1ddq testin g . . . . . . 10.6.3 Traditional debug, diagnosis and failure analysis (FA) t echniques 10.6.4 More recent debug and failure analysis techniques 10.6.5 Observing the failure. . . . . . . . . . . . . . . . . 10.6.6 Circuit edit ing t echniques 10.6.7 Design for Debug and Design for Failure Analysis . 10.7 Conclusions . 10.8 References. . 10.9 Exercises . .

654 654 654 655 664 675 679 682 683 684 686

11 Effects of scaling on MOS Ie design and consequences for the roadmap 687 11.1 Introduction. . . . . . . . . . . 687 . 689 11.2 Transistor scaling effects . . . 11.3 Interconnection scaling effects . 690 11.4 Scaling consequences for overall chip performance and robustn ess . .695 11.5 Potenti al limit ati ons of t he pace of scaling .702 11.6 Conclusions .708 11.7 References . . 709 11.8 Exercises . . 710

XXXll

Chapter 1

Basic Principles 1.1

Introduction

The majority of current VLSI Very Large Scale Integration) circuits are manufactured in CMOS t echnologies. Familiar examples are memories (1 Gb , 4 Gb and 16 Gb) , micropro cessors and signal processors. A good fund ament al treat ment of basic MOS devices is therefore essential for an und erst anding of t he design and manufacture of modern VLSI circuits. This chapter describ es the operation and characte rist ics ofMOS devices. The material requir ement s for their realisation are discussed and equations that predict their behaviour are derived. The acronym MOS repr esents the Met al, Oxide and Semiconductor materials used to realise early versions of the MOS transistor. The fund ament al basis for the operation of MOS transistors is the field-effect prin ciple. This principle is quite old, with relat ed publications first appearing in the ninet een-thirties. These include a patent applicat ion filed by J.E. Lilienfeld in Canada and the USA in 1930 and one filed by O. Heil, independentl y of Lilienfeld, in England in 1935. At t hat t ime, however , insufficient knowledge of mat erial prop erties resulted in devices which were unfit for use. The rapid development of elect ronic valves probably also hind ered th e development of t he MOS tr ansistor by largely fulfilling the tr ansistor's envisaged role.

1.2

The field-effect principle

The field-effect principle is explained with the aid of figur e 1.1. This figure shows a rectangular conductor, called a channel, with length L, 1

width W and t hickness t cond ' The free elect rons present in t he cha nnel are t he mobile charge carriers. There are n electrons per m3 and t he cha rge q per elect ron equals -1.602 x 10- 19 C(coulomb). The applicat ion of a horizontal elect ric field of magnitude E t o the cha nnel causes the elect rons to acquire an average velocity v = - fLn . E . The electron mobility fLn is positive. The direction of v t herefore opposes t he dir ection of E . The resulting current density j is the product of t he average elect ron velocity and the mobile cha rge density p: j

=

.v

= - n . q . fLn . E

(1.1)

t·I

-rtcond

Figur e 1.1: The field-effect principle A gate electrode sit uate d above t he cha nnel is separated from it by an insulator of thickness tis' A cha nge in the gate volt age Vg influences the cha rge density in the chann el. The current density j is therefore determined by Vg . Example: Suppose the insulator is silicon dioxide (Si0 2 ) wit h a thickness of 2 nm (tis = 2 x 1O- 9m). The gate capacitance will then be about 17 mF 1m2 . T he total gate capacitance Cg is therefore expressed as follows:

Cg

= 17 X 10- 3 .

W . L [F]

A cha nge in gate charge b..Qg = - Cg . b.. Vg causes t he following cha nge in channel cha rge:

+ Cg . b.. Vg = 17 X 10- 3 . W . L . b.. Vg = 2

W · L . t cond . b..p

Thus: 17

10- 3 . ｾ V;g

X

C/m3

t cond

and: A Iu n

I = I -ｾｰ I=

10.6

ｾ Vg eectrons 1 / m3

16

X

q

10

.

t cond

If a 0.5 V change in gate voltage is t o cause a hundred times increase in current density i, t hen the following must apply: ｾ

ｪ

J ::::} tcond

=

ｾｰ

ｾ

p

10.6 ｮ

n

X

1016 . 0.5

t cond .

n

100

5.3 x 1014 n

Examination of two materials reveals the implications of this expression for t cond :

Case a The channel material is copper. Thi s has n :=:::! 1028 elect rons/rn'' and hence tcond :=:::! 5.3 X 10- 14 m. The requir ed cha nnel t hickness is thus less tha n the size of one at om ( :=:::! 3 x 10- 10 m) . Thi s is impossible to realise and its excessive numb er of free carriers renders copper unsuitable as channel material. Case b The channel mat erial is 5ncm n-typ e silicon. This has n :=:::! 1021 electrons/rn'' and hence t cond :=:::! 530 nm . The transcondu ctance 9m of a MOS t ra nsist or is t he rat io of a change in channel (dr ain) curre nt to the corres ponding change in gate volt age: ｾｉ

9m =

However

ｾｉ

-

t cond =

ｧ

I

J

I

Therefore If 1= i W·

ｾｖ ｾｪ

9m

ｾｪ

-- .ｾｖ

ｧ

1 mA, ｾ ｪ Ｏ ｪ = 100 and ｾｖ 9m

=

200 mA/V 3

ｧ =

0.5 V t hen:

In this case, a transconductance of 200 mA/V requires a channel thickness of tcond = 530 nm. Modern IC technologies allow the realisation of much thinner channels. From the above example, it is clear that field-effect devices can only be realised with semiconductor materials. Aware of this fact, Lilienfeld used copper sulphide as a semiconductor in 1930. Germanium was used during the early fifties. Until 1960, however, usable MOS transistors could not be manufactured. Unlike the transistor channel , which comprised a manufactured thin layer, the channel in these inversion-layer transistors is a thin conductive layer, which is realised electrically. The breakthrough for the fast development of MOS transistors came with advances in planar silicon technology and the accompanying research into the physical phenomena in the semiconductor surface. Generally, circuits are integrated in silicon because widely-accepted military specifications can be met with this material. These specifications require products to function correctly at a maximum operating temperature of 125°C. The maximum operating temperature of germanium is only 70°C, while that of silicon is 150°C. A comparison of a few other germanium (Ge) and silicon (Si) material constants is presented below:

Material constant Melting point [0C] Breakdown field [V/ f.lm] Relative expansion coeff. [0C]-l Er

Max . operating temp. [0C]

1.3

Germanium 937 8 5.8 x 10- 6 16.8 70

Silicon 1415 30 2.5 X 10- 6 11.7 150

The inversion-layer MOS transistor

A schematic drawing of the inversion-layer nMOS transistor, or simply 'nMOSt' , is shown in figure 1.2, which is used to explain its structure and operation. The two n" areas in the p-type substrate are called the source and drain. The gate electrode is situated above the p area between them. This electrode is either a metal plate, e.g., aluminium or molybdenum, a heavily doped and thus low-ohmic polycrystalline silicon layer, or a combination of both. Normally, the source and drain areas are also heavily doped to minimise series resistance. The resistance R 4

of a 10/-lm long and 2/-lm wide track is 120 • R where R is the sheet resistance of the track material. The sheet resistance of the source and drain areas usually ranges from 3 to 100 njD with doping levels upto 5.10 19 to 2.10 20 atoms per em", The dope concentration in the p-type substrate is approximately 1014 _10 16 atoms per cm'', while the channel dope (by threshold adjustment implantation, etc.) is between 1017 _10 18 atoms per ern". A p-channel transistor differs from the above n-channel type in that it contains a p+ source and drain in an n-type substrate. gate

ourcc

drain

(bu lk) ub trate

Figure 1.2: Cross-section of an inversion-layer nMOS transistor Characteristic parameters of a MOS transistor are indicated in figure 1.2. These include the width Wand length L of the channel and the thickness tax of the insulating oxide which separates the gate and channel. In modern CMOS VLSI circuits, the minimum values of Wand range from 40 nm to 120 nm and tax ｾ 1.2 nm - 2.5 nm . Continuous development will reduce these values in the future . The depth of the source and drain junctions varies from 50 nm to 200 nm. The energy band theory and its application to the MOS transistor are briefly summarised below. An understanding of this summary is a pre-requisite for a detailed discussion of the behaviour of the MOS transistor. The structure of a free silicon atom is shown in figure 1.3. This atom comprises a nucleus , an inner shell and an outer shell. The nucleus contains 14 protons and 14 neutrons while the shells contain 14 electrons. Ten of the electrons are in the inner shell and four are in the outer shell. The positive charge of the protons and the negative charge of the electrons compensate each other to produce an atom with a net neutral charge . 5

nuclcu ,,--- -- ........

,{

••••-. ｾ

,,/

inner hell

>\

I I

(10 electron )

\ \

I

I

:

:

outer hell

:

(4 electron )

\

I

\

,.'

:

\

\"

-

_-_ .-' -4

Figure 1.3: Th e struct ure of a free silicon atom The elect rons in an at om may possess cert ain energy levels. These energy levels are grouped into energy bands, which are separated by energy gaps. An energy gap represents impossible levels of elect ron energy. The energy bands that apply to the electrons in an at om's outer shell are valence and conduction band s. Figure 1.4 shows these bands and the energy gap for a typical solid mat erial. The valence elect rons determine the physical and chemical prop erti es of a materi al. conduction band electron

} forbidden gap

energy

valence band

Figure 1.4: Schematic representation of electron energy bands in a typical solid material

The four elect rons in the outer shell of a silicon at om are in the mat erial 's valence band . Figure 1.5 shows the bonds that t hese electrons form with neighbouring atoms to yield a silicon crystal.

6

Figure 1.5: Silicon crystal The electrons in a conductor can easily go from the valence band to the conduction band. Therefore, the conduction and valence bands in a conductor partly overlap, as shown in figure 1.6a. In an insulator, however, none of the valence electrons can reach the conduction band. Figure 1.6b shows the large band gap generally associated with insulators. A semiconductor lies somewhere between a conductor and an insulator. The associated small band gap is shown in figure 1.6c. Valence electrons may acquire sufficient thermal energy to reach the conduction band and therefore leave an equal number of positively-charged ions, or 'holes', in the valence band. This produces a limited conduction mechanism in semiconductors.

7

(a)

(b)

(c)

;>.

ｾ (l) l::::

•

(l)

l:::: 0

t:to)

(l)

ｾ

•• •• ••

• ••• •• •

•• •• •• •

Figure 1.6: En ergy bands of a conductor, an insulator and an intrin sic sem iconductor Semiconducto r materials are located in group IV of this syst em. The introduction of an element from group III or V in a semiconduct or crystal produces an 'acce ptor' or a 'donor' atom. This semiconductor doping process dr am ati cally cha nges t he crystal properties. The following t abl e shows t he location of semiconductor materials in the periodic syste m of elements .

III (Acceptors) Boron Aluminium Gallium Indium

Group IV Carbon Silicon Germ anium Stannic (tin)

V (Donors) Nitrogen Phosphorous Arsenic Stibnite

The presence of a group III at om in a silicon crystal lattice is considered first . The situation for boron (B) is illustrated in figur e 1.7a. Boron has one elect ron less than silicon and cannot therefore provid e an elect ron required for a bond with one of its four neighbouring silicon atoms. The hole in the resulting p-type semiconductor is a willing 'acceptor' for an elect ron from an alte rnative sour ce. This hole can be removed relatively easily with the ionisation energy of approximate ly 0.045 eV shown in the energy band diagram of figur e 1.7a. 8

Similar reasoning applies when a group V ato m, such as phosph orus (P) , is present in the silicon lattice. This sit uation is illustrat ed in figure 1.7c. The ext ra electron in the phosph orus atom cannot be accommodated in t he regular bondin g st ructure of the silicon lat tice. It is therefore easy to remove t his 'donor' electron in t he resulting n-type semiconductor. The mere 0.037 eV ionisation energy required is much lower t han t he 1.11 eV band gap energy of silicon. Figur e 1.7b shows the energy band diagram of an intrinsic silicon lattice, which contains no donor or acceptor 'impurity' atoms. The energy level indicat ed by Er in figure 1.7 is called t he Fermi level. An elect ron with t his energy has an equal probability of location in the valence band and the conduct ion band. This probability is exact ly 0.5. The Fermi level of an intrinsic semiconduct or is ofte n referr ed to as the intrinsic Fermi level Ej The Fermi level Ef in a p-type semiconductor is sit uated near the valence band E v , while it is close to the conduct ion band E c in an n-type semiconductor . T he ab ove theory concerning t he different ty pes of semiconductors and their respective energy band diagrams will now be used to explain the behaviour of t he MOS tra nsistor. This explanation is preceded by a description of the st ructure and operation of t he MOS capacitor.

9

•

p-typc cmiconductor

intrinsic cmiconductor

/cxtm electron

n-type semiconductor

,

· B 0.045 c

1

EC}

Ef ••••••• E\, E (a)

•

•

•

• (b)

C

p , • • • • • E; 0.037 cV -', - - - - e,

• (c)

Figure 1.7: Energy band diagrams for p-type, intrinsic, and n-type semiconductor materials

10

1.3.1

The Metal-Oxide-Semiconductor (MOS) capacitor

F igure 1.8 shows a cross-sect ion of a basic MOS capac itor. This struc t ure is identic al to a MOS t ransistor exce pt t hat t he source and drain diffusion regions are om itted.

Vg < 0

------- j-------

Vg>O

++++++++++++++ ---=,...---=,....,

lox -+--,..--_ _

__ ｾ

C??

e+

ｾ

e+ e+

J??

depletion layer

(b) Depletion

(a) Accumu lation

e: fixed negati

c charge carriers (acceptor atom.) + : mobile po itivc charge carriers (free hole) - : mobile negative charge carriers (free electron)

Fi gure 1.8: Cross-section of a MOS struct ure witho ut source and drain areas. Th ere is a capacitance between the gate and substrate. T he p-typ e substrate is mad e wit h an acceptor dop e mat erial , e.g., boron. The substrate is assumed to behave as a normal conductor and contains many free holes. The situation which occurs when t he p-typ e substrate is grounded and a negative voltage is applied t o t he gate elect ro de is shown in figure 1.8a . The negativ e cha rge on the gate is compe nsated by an equal but positive charge in t he substrate . This is accomplished by positively charged holes which accumulate at the SiSi0 2 int erface. These holes are the majority charge carriers in the subst rate. This 'acc um ulation' pr ocess continues until t he positive charge at t he subst rate sur face equals the negative cha rge on t he gate electro de . Ex tra holes are supplied t hrough t he ground contact to t he substrate. The resul t ing accumulation ca pac itor ca n be viewed as an ideal par allel plate capacitor. A different sit uation occurs when t he potenti al on t he gate elect rode is made positi ve wit h respect to t he gro unded substrate. This sit uation is shown in t he cross-section of figure 1.8b. T he pos itive charge which 11

is present on the gate must be counter-balanced by a negative charge at the Si-Si0 2 interface in the substrate. Free positively-charged holes are pushed away from the substrate surface to yield a negatively-charged depletion layer. This 'depletion ' process stops when the negative charge of the depletion layer equals the positive charge on the gate electrode. Clearly, the thickness td of the depletion layer in the equilibrium situation is proportional to the gate voltage. It is important to realise that a depletion layer only contains a fixed charge, i.e., ions fixed in the solid state lattice, and no mobile charge carriers. Various energy band diagrams are used to explain the behaviour of the inversion layer MOS transistor. To provide a better understanding of these diagrams, Poisson's law is first applied to the different regions of the MOS capacitor. These regions include the gate, the Si02 insulator, the depletion layer in silicon and the p-type silicon substrate. Poisson's the electric field law is used to investigate the charge distribution E(z) and the electric potential¢(z) in these regions as a function of the distance z from the Si-Si02 interface. In its one dimensional form, Poisson's law is formulated as follows:

(1.2) E

where

¢(z) z E

electrical potential at position z; distance from the Si - Si02 interface; space charge ; dielectric constant.

The situation in which no space charge is present is considered first. This is almost true in the Si02 insulator, in which case = O. Integration of formula (1.2) once gives the electric field: C1 = integration constant.

Integration of formula (1.2) twice gives the electric potential in Si02:

The electric field in the insulator is thus constant and the electric potential is a linear function of the distance z from the Si-Si0 2 interface.

12

Next, the situation in which a constant space charge is present is considered. This is assumed to be true in the depletion layer, whose width is Wo . In this case:

p where q and NA

-q·NA

the charge of an electron the total number of fixed ions in the depletion layer of thickness td.

Integrating formula (1.2) once gives the electric field: q ·NA

E(z) = - - · z + C1 E

Integrating formula (1.2) twice gives the electric potential in the depletion layer:

Therefore, the electric field in a depletion layer with constant space charge is a linear function of z, while the electric potential is a square function of z. The space charge in a depletion layer is only constant when the dope of the substrate has a constant value at all distances z from the Si-Si02 interface. In practice, the space-charge profile is related to the dope profile which exists in the substrate. The gate and the substrate region outside the depletion layer are assumed to behave as ideal conductors. The electric potentials in these regions are therefore constant and their electric fields are zero. The above results of the application of Poisson's law to the MOS capacitor are illustrated in figure 1.9. Discontinuities in the diagrams are caused by differences between the dielectric constant of silicon and silicon dioxide . The electric charge, the electric field and potential are zero in the grounded substrate outside the depletion region. The observation that the electric potential is a square function of z in the depletion layer is particularly important.

13

+Q Vg

-Q

e e e ee e eee e -

0--

II

i02

- lox

0

..

IVD

ｾ

ｺ

(

t

this drop is caused by the

r====:fference in

Es,,, and Es; ｾ

ｺ

¢(

t linear

square

ｾｺ

F ig ure 1.9: The sections of a MOS capacitor and the associated charge distribution Q(z), electric field E(z) and electric potential ¢ (z )

14

1.3.2

The inversion-layer MOS transistor

Figure 1.10 shows a cross-section of an nMOS transistor wit h OV on all of its te rminals. T he figure also cont ains t he associated energy band diag ram. Metal

Oxide

_ emiconductor (p-typc)

Ec

------- ---- ｾＺ Ｎ

ｾ ｾＡ

ｾ

r= Fermi potential

Ev

e :fixed charge (acceptor-atom) + - : mobile charge (hole or electron , re pectively) Figure 1.10: Cross-section of a MOS transistor with Vgs =Vds =V';;b=OV and th e associated energy band diagram It is assumed that t he presence of t he gate does not affect t he dist ribu t ion of holes and electrons in t he semiconduct or. With the exception of t he depletion areas around the n" areas , t he ent ire p-sub strate is assumed to be homogeneous and devoid of an electric field (E = 0). There is no charge on t he gate and no surface charge in t he silicon. Generally,

15

the electron energies at the Fermi levels of the different materials in the structure will differ. Their work functions (i.e., the energy required to remove an electron from the Fermi level to vacuum) will also differ. When the voltage between the gate and source is zero (Vgs = 0) and the metal gate is short circuited to the semiconductor, electrons will flow from the metal to the semiconductor or vice versa until a voltage potential is built up between the two materials. This voltage potential counter-balances the difference in their work functions . The Fermi levels in the metal and the semiconductor are then aligned. Therefore, there will be an electrostatic potential difference between the gate and substrate which will cause the energy bands to bend. The 'flat-band condition' exists when there is no band-bending at the metalsemiconductor interface. The 'flat-band voltage' Vfb is the gate voltage required to produce the flat-band condition. It is the difference between the work functions of the metal (1)M) and the semiconductor (1)5) , i.e., Vfb = 1>MS = 1>M - 1>5· Since equilibrium holds, the Fermi level in the semiconductor remains constant regardless of the value of the gate voltage. A negative charge is induced in the semiconductor surface when a small positive voltage is applied to the gate, while the source, drain and substrate are at OV, see also figure 1.11. The negative charge is caused by holes being pushed away from the insulator interface. The negatively charged acceptor atoms that are left behind form a negative space charge, i.e., a depletion layer. The thickness of this depletion layer is determined by the potential Vc at the silicon surface . The gate voltage Vgs now consists of two parts: a. The voltage across the oxide Vg

-

Vc ;

b. The voltage across the depletion layer ｾＮ

The capacitance between the gate and substrate now consists of the series connection of the oxide capacitance Cox and the depletion-layer capacitance Cd. The term VT in figure 1.11 represents the threshold voltage of the transistor. This is the gate voltage at which the band-bending at the silicon surface is exactly 21>[. At this band bending, the electron concentration at the semiconductor surface becomes equal to the hole concentration in the bulk. This situation is called (strong) inversion, and the layer of free electrons created at the surface is called an inversion

16

layer. For t he pr esent , VT is ass umed to be positi ve for an inversion-l ayer nMOS transisto r. T his ass um ption is confirmed lat er in t he text .

o

(a)

- - - - - - -- z

b

Figur e 1.11: Cross-section of a MOS transistor with O< Vgs< VT and ｖ､ ｳ ］ｾ｢ ］ ｏ V and its corresponding energy band diagram If t he gate volt age is fur ther increase d (Vgs > VT) t hen the band-b ending at t he silicon surface will be lar ger than 2¢f . This sit uation is illustrat ed in figure 1.12. A compa rison of figure 1.12 and figur e 1.7c reveals t ha t t he energy band at t he silicon sur face correspon ds to an n-typ e semiconductor.

17

M

0

ｾＭ

silicon urface

(a)

depletion layer inver ion layer

mobile charge

b

Figur e 1.12: Cross-section of a MOS transistor with Vgs> VT (VT> O) and

ｖ ､ ｳ］

ｾ｢］ｏ

V and its corresponding energy band diagram

Deep in t he subst rate , however , the energy band corresponds to a ptyp e semiconductor. A very narrow n-typ e layer has t herefore been crea te d at the surface of a p-typ e silicon subst rate. In addit ion t o the negative acceptor atoms alrea dy present , t his inversion layer contains elect rons which act as mobile negative cha rge car riers. Conduction in the n-typ e inversion layer is mainly perform ed by these electrons, which are minority carriers in th e p-type substrat e. The inversion layer forms a conduct ing channel between the t ra nsisto r' s source and dr ain . No cur rent flows in t his cha nnel if there is no voltage difference between the dr ain and source terminals, i.e., Ids = 0 A if Vd s = 0 V. The numb er of elect rons in the cha nnel can be cont rolled by t he gate-source volt age

Vgs .

18

Assuming that Vgs > VT, the effects of increasing Vds from 0 V are divided into the following regions: 1. 0 < Vds

< Vgs - VT.

This is called the linear or triode region of the MOS transistor's operating characteristic.

2. Vds = Vgs - VT. At this point , a transition takes place from the linear to the socalled saturation region. 3. Vds > Vgs - VT. This is the saturation region of the MOS transistor's operating characteristic. The three regions are discussed separately on the following pages .

19

The linear region Figure 1.13 shows the situation in the linear region, in which a current Ids (which flows from drain to source) causes a voltage difference in the channel. The surface potential under the gate decreases from Vds in the drain to 0 V in the source. The maximum potential difference between the gate and channel is at the source . Therefore, the strongest inversion and the highest concentration of electrons in the inversion layer occur adjacent to the source. The maximum potential difference between the channel and substrate is at the drain. The depletion layer is therefore thickest here. In the linear region, the drain current Ids increases with increasing Vds for a constant V gs.

in er ion layer 0.5 nm to 5 nm thick

g ｾ Ｎ｟ｾＭ

0/

-e-e e--- -e-ee e-ee e -

----- -----{2

e- e e- " e e-----------..' e+ ----------e+ ",-e -e e -ee e+ e e e+ - e+ ｾ ｾＭ･ e+ e+ e+ p- e e+ e+ e e b Figure 1.13: Cross-section ofa transistor operating in th e linear (triode) region

20

The transition region An increase in Vds, with Vgs constant, decreases the voltage difference between the gate and channel at the drain. The inversion layer disappears at the drain when the voltage difference between the gate and channel equals the threshold voltage VT. The channel end then coincides with the drain-substrate junction. This situation occurs when Vds = Vgs - VT , and is shown in figure 1.14.

IVg . > vT >ol

___.1.£

_

e

e

e

b Figure 1.14: Situation during transition from triode to saturation region, i.e., Vds=Vgs- VT

21

The saturation region

T he cha nnel end no longer coincides with the drain when tha n Vgs - VT. Thi s sit uation is shown in figure 1.15.

8

-0---- - --

Vds

is larger

8

8 8 8 8 8 8 8 8 8 8,,·------__ 8 ------------,,' ----- 8 8 - - 8 8+ + --------: 8 8 8 8 8 + -----___ 8 8 8 p- 8 + 8 +----(;+--8+--b Figure 1.15: Sit uation in the sat uration region, i.e., Vd s > Vgs

-

VT

The volt age Vx at the end point x of t he inversion layer equals Vgs - VT. Therefore, VT is t he voltage difference between the gate and channel at position x . If t his pinch-off point is considered to be t he virt ual drain of t he tra nsistor, then Ids is determin ed by the voltage Vx = Vgs - VT. In ot her words, the dr ain current in the saturation region equals the drain current at the tra nsit ion point between t he linear and sat uration regions. The value of t he sat uration current is clearly proportional to Vgs . Electrons are emitted from t he inversion layer into the deplet ion layer at t he pinch-off point. Th ese electrons will be at t racted and collected by the dr ain because Vds > Vx , which builds a large electric field across t he very narrow pinch-off region. Figure 1.16 shows the Ids = f (Vds) characteristic for various gate volt ages. If Vds = 0 V, t hen Ids = 0 A. If Vds is less than Vgs - VT, then t he t ra nsistor operates in the tri ode region and the current Ids displays an almost linear relationship with Vds ' Curr ent Ids increases to its saturation value when Vds = Vgs - VT. Fur ther increases of Vds above 22

VT no longer cause increases in I ds ' T he transit ion between t he t riode and saturation regions is characte rised by t he cur ve Vds = Vgs - VT. Vgs -

Rout = finite (real transistor)

•

3

saturation region

linear or triode region 1-,"

./ ._.-.-.-.-.-.-.- I •

Ｌｾ

Vgs

IV

....Rout = infinite ...

Ｏｾｖ､ｓ

(ideal current source)

•• ••

=

.'

Vgs -V

o- F - - , . - - - , . - - - , . - - - , . - - - , . - - - - ' o 0.25V O.5V O.75V 1V 1.25V -

Vds[V]

Figure 1.16: T he Ids=! (Vds) characteristic Eor various values oEVgs

1.4

Derivation of simple MOS formulae

The inversion layer nMOS t ransisto r shown in figur e 1.17 has a width W perp endi cular to t he plane of t he page and an oxide capacitance 2 Cox per unit area . A commonly-used unit for Cox is fF/ , where 15 1 fF = 10- F.

23

inver ion layer depIction layer

x =o

x =L

x

Figure 1.17: Charges in a MOS transistor operating in th e linear region Based on the law of charge the following equality must hold at any position x between the source and drain: (1.3) The components in this equation are charges per unit area, specified as follows:

Qg = t he gate charge [C/m 2 ] ; Qox= primarily a small fixed charge which in practice always appears to be present in the thin gate oxide [C/m 2 ] ; Qn = the mobile charge in the inversion layer [C/m 2 ] ; 2 Qd = the fixed charge in the depletion layer [C/m ] . the inversion layer shields the depletion For gate voltages larger than layer from the gate. The charge in the depletion layer can then be considered constant: (1.4) The threshold voltage is assumed to be constant. The potential in the channel at a position x is V( With Qg = Cox[Vgs - V( x)] and substituting (1.4) into (1.3) yields: Qn = -Cox[Vgs - V 24

-

V(x)]

The total mobile charge dQm in a sect ion of the channel with lengt h dx is defined as: dQm = Qn . W . dx =

ｾ

=}

The drain current

W . Cox [Vgs -

dQ m = - W· Cox [Vgs Ids

- V ( )] . dx

- V( )]

(1.5)

(1.6)

is expressed as: _ dQm _ dQm dx ili - d;- . dt

(1.7)

ds -

where ､ｾｸｭ is defined in equat ion (1.6) and ｾ ｾ is the velocity v at which the charge Qm moves from t he source to t he drain region. This is t he velocity of t he electrons in the inversion layer and is expressed as:

v

V( ) dx

= Mn . = - Mn . - -

(1.8)

where is t he electric field st rengt h and Mn repr esents t he electron mobility in t he inversion layer. The mobility repr esents the ease in which charge carriers move within a semiconducto r. In practice, the effective mobility appears to be less t han one third of t he electron mobility in t he subst rate (see section 2.3). Combining equations (1.6), (1.7) and (1.8) yields: Ids =

Mn . Cox ' W · [Vgs -

- V(

.--

(1.9)

Substituting (30 = Mn . Cox yields: Ids '

= (30 ' W . [Vgs - V - V ( )] .

Integrating the left-hand side from 0 to o to Vd s yields:

()

(1.10)

and t he right-hand side from

(1.11) 25

Equation (1.11) has a maximum value when Vds = Vgs - VT. In this case, the current Ids is expressed as:

Ids =

1 W L . (30 . (Vgs 2.

VT)

2

(1.12)

If Vgs = VT then Ids = 0 A. This clearly agrees with the earlier assumption that VT is positive for an inversion-layer nMOS transistor. The term (3 is usually used to represent ｾ . (30. This factor is called the transistor and depends on geometry. The gain term (30 is a process parameter which depends on such things as the oxide thickness tx : (30

EOE

ox = f-Ln . Cox = f-Ln . -t -

(1.13)

x

The unit of measurement for both (3 and (30 is A/y2. However, f-LA/y2 and mA/y2 are the most commonly-used units. For an n-channel MOS transistor, (30 varies from 360 f-LA/y2 to 750 f-LA/y2 for oxide thicknesses of 3.2 nm and 1.6 nm, respectively. Note that these values for (30 resemble the zero-field mobility in the substrate. The effective mobility in the channel, and so the effective gain factor, is much lower due to several second order effects as discussed in chapter 2. According to equation (1.11), Ids would reach a maximum value and then decrease for increasing Vds - In the discussion concerning figures 1.15 and 1.16, however, it was stated that the current remains constant for The transistor has two operatan increasing Vds once Vds > Vgs ing regions which are characterised by corresponding expressions for Ids' These regions and their Ids expressions are defined as follows:

1. The linear or triode region. 0 < Vds < Vgs - VT. (1.14) 2. The saturation region. Vds :?: Vgs - VT. (1.15) According to equation (1.15), Ids is independent of Vds in the saturation region. The output impedance dVds/dIds should then be infinite and the transistor should behave like an ideal current source . In practice,

26

however, MOS transistors show a finite output impedance which is dependent on geomet ry. This is explained in chapte r 2. Figure 1.16 shows both the ideal (theoreti cal) and t he real current-voltage characterist ics of a transistor with a t hreshold voltage VT = 0.25 V. The I ds = !(Vds)IVgs= constant curves in figure 1.16 are joined by the dotted curve Vd s= V gs- VT at the points where equat ion (1.14) yields maximum values for I ds' This curve divides the Ids- V ds plane into two regions: 1. Left of the dot ted curve: t he triode or linear region, which defined by equation (1.14);

IS

2. Right of the dotted curve: t he saturation region, which is defined by equation (1.15).

1.5

The back-bias effect (back-gate effect, body effect) and the effect of forward-bias

The simple MOS formulae derived in section 1.4 appear to be reasonably satisfactory in most cases. The very important back-bias effect is, however , not included in t hese formul ae. Thi s effect accounts for the modul ation of the threshold volt age by t he subst rate bias and the subsequent effects on the drain current . During normal operation (when V gs > VT and Vd s > V gs - V T) a depletion layer is formed , as shown in figure 1.15. However , t he t hickness of the depletion region und er t he channel increases when a negat ive back-bias voltage (l!,;b) is applied to the bulk (b) with respect to the source . This is caused by t he increased reverse-bias voltage across the fictive cha nnel-substra te junction. The increased depletion layer requires additional charge . T he cha nnel charge therefore decreases if V gs is held constant . T he channel conduct ivity can only be maint ained if Vgs is increased. The t hreshold voltage is t herefore relat ed to the back-bias voltage l!,;b. This dependence is expressed as follows:

+ K ｊｾ ｢ + 2(jJf Vx + K J2"1X Vx

The term s in t hese formulae are as follows:

Vx

= pro cess-related constant threshold voltage t erm ; 27

(1.16) (1.17)

VT O = VTIV';,b=OY ; K = process parameter equal to -ri-y'2NAQfOfsi ; vox

also known as the 'body factor' or K-factor; NA = substrate (bulk) dope concentration; V';,b = source-bulk (back-bias) voltage ; 2 1 GHz). Therefore, 41

will now equal C ox und er all norm al opera t ing conditions. In this case, Ct represents the capacitance between t he gat e and source, i.e., C t = C gs = Cox(L + b.L) . W. The dependence of the capacitance C gs on the applied volt age Vgs is summarised as follows: Ct

• When Vgs < V there is no inversion layer . Here, the value of is determined by the channel width W and the gate overlap . W · Cox ' on the source/dra in area : C gs =

C gs

• When Vgs > V there is an inversion layer. Here, C gs is determined + . W . Cox' by the channel length : C gs = The above non-linear behaviour of Cgs = f (Vgs ) is shown in figure 1.28.

ｵｾ

(L + M) . W · Cox

I

ｾ

M· W · Cox 1 - - - - 0 /

o Figure 1.28: Non-linear behaviour of a MOS capacitance Note: There is no inversion layer when Vgs < V how the gate-subst rate capacitance then behaves.

Figure 1.26 shows

Figure 1.29 shows t he lar ge numb er of capacitances in a real MOS t ra nsistor. These capacitances, which are largely non-linear , are defined as follows: C db , Csb

C gdo, C gso : Cgd , C gs

drain-substrat e and source-subst rate capacitances, which are non-linearly dependent on Vdb and ｾ ｢Ｌ respectively. gate-drain and gate-source capacitances, which are voltage-independent . gate-dra in and gate-source capacitances (via t he inversion layer) , which are non-lin early dependent on Vgs , 42

C gb

:

Vgd and Vgb . gate-subst rate capacitance, which is non-linearly dependent on Vgb .

p" ub trate

(a)

g

s

d

(b)

b Figure 1.29: Capacita nces in a MO S transistor

43

The values of the C db and C sb diode capacitances in figur e 1.29 are expressed as follows:

C(V) _ Co - (1 + ｾＩｬ Ｏｭ

(1.33)

J

where:

= capacitance when V =0; Vj = junction voltage (0.6 V to 0.9 V);

Co

m = grading fact or , 2 ::; m ::; 3: m = 2 for an abru pt junction and m = 3 for a linear junction. Term s Cgdo and C gso represent gate overlap capacitances that are det ermined by t he t ransistor width, the length of the overla p on t he drain and source ar eas, and t he t hickness of the gate oxide. These capacitances are clearl y voltage-ind epend ent. The gate-substrate capacitance Cgb is only imp ortant if Vgs« V . Now, C gb is often expressed as C gb::::::: (0.12 to 0.2) . W . L . Cox. The inversion layer shields t he subst rate from t he gate and Cgb= O when ｖ ｧ ｳｾ VT· Term s Cgd and C gs represent gate-drain and gate-source capacitances, respectively, which are present via the inversion layer (figure 1.28). T he values of t hese capacitances depend st rongly on t he bias voltage on the te rmina ls of t he MOS t ra nsisto r. The following cases are distinguished: Case a Vgs< VT ; no inversion layer, thus Cgd=Cgs= O. Case b Vgs> VT and Vds =O. For reasons of symmet ry, ｃｧｳ ］ｃｧ､ ］ ｾ . W . L . Cox' Case c Vgs> VT and Vds > Vd sat (Vdsat = Vgs - VT). T he transist or is in saturat ion and t here is no inversion layer at the dr ain: Cgd = O and C gs = ｾ . W · L . Cox. This expression for Cgs is derived below. Case d Vgs> VT and 0 < Vds< Vd sa t ' In t his case, a linear interpolation between t he values in cases b and c closely corresponds to the actual values, which are shown in figur e 1.30.

44

\.) C gIOI =

1

2/3 CgtOI

W· L·

Ｍ Ｍ Ｍ ｾＭ

Ｍｾ ＺＭ ｾ

Cox

Ｍ ｷＭｾ

1/2 Cg10 l

Figure 1.30: Cgs and Cgd depend ence on Vds for Vgs> V The above expression in case c for the gate-source capacitance Cgs of a saturat ed MOS transistor is explained with t he aid of figure 1.31. This figure shows a cross-sect ion of a MOS tran sistor biased in the saturat ed region . The cha nnel does not reach the drain ar ea , but stops at a point where the channel potential is exac t ly Vgs - VT.

p- sub trate ＭＭ

ｾ

x =o

ｸ

x =L

Figure 1.31: Cross-section of a saturat ed MOS transistor. Cgs = ｾ . W . L . Cox '

C gd

= 0 and

Equation (1.5) leads to the following expression for the charg e dQ in a cha nnel section of length dx at position = Qn '

W · dx = -W . Cox[Vgs - VT - V( 45

. dx

(1.34)

The following expression for dx is derived from equation (1.9):

dx =

j.tn . Cox'

W . [Vgs - VT - V(x)] . dV(x) Ids

(1.35)

Combining equations (1.34) and (1.35) yields the following expression for dQ(x) :

dQ(x) =

j.tn ·

Cox

2 .

W

2 .

[Vgs - VT - V(x)F . dV(x) Ids

(1.36)

Equation (1.15) yields the following expression for the drain current Ids in a saturated MOS transistor:

Ids =

f3 ( "2' Vgs -

)2 VT =

j.tn . Cox

2

.

W L . (Vgs -

VT

)2

(1.37)

Substituting equation (1.37) in equation (1.36) yields:

Integrating equation (1.38) from the source to the imaginary drain gives:

Q =

=?

Q =

rVgS-VT

lv.

2

"3' W

Cox'

[Vgs - VT - V(x)F . dV(x) (Vgs - VT ) 2

W · L·

2 ·

. L . Cox' (Vgs - VT)

(1.39)

The gate-source capacitance Cgs can be found by differentiating Q in equation (1.39) with respect to Vgs:

dQ

C gs

2

= dVgs ="3' W· L · Cox

(1.40)

The Cgs of a saturated MOS transistor is therefore only two thirds of the total value, while the gate-drain capacitance is zero.

46

In summary: Most capacitances in a MOS transistor are non-linearly dependent on the terminal voltages. For each capacitance, these dependencies are as follows : 1. The diode capacitances Cdb and Csb: C(V)

= (1+f')l/m' where Vj ;: ;:; 0.6 . .. 0.9 V and 2 ｾ m ｾ 3. J

2. Figure 1.28 shows the voltage dependence of gate-channel capacitances Cgd and Cgs when the drain and source are short circuited, as is the case in a MOS capacitance. Figure 1.30 shows the voltage dependence of Cgd and Cgs when the drain and source are at different voltages, i.e., during normal transistor operation. 3. The gate-substrate capacitance Cgb is 0 when Vgs> Cgb= 0.2· W· L· Cox if Vgs
f=1 V throughout t hese exercises. 1. What happens to t he depletion layer in figure 1.12 when the subst rate (b) is connected to a negati ve voltage Ｈｾ -1 V) instead of

ground? What effect does this have on t he threshold voltage VT ?

(r

2. Current I ds in a t ra nsistor = 2) is 100/-LA when its gate-source volt age V is 0.8 V . The curre nt is 324/-LA when V = 1.2 V .

WIL = r - l 1.2 V g

: ｩｾＭＧ｢･ I

s

a) Which t ra nsistor operating regions (linear or saturated) do t hese values of V correspond t o? b) Calculate

f30 and

VT for the given tra nsistor.

3. Given:

d

g

I..---f?fb

+

1.2 V

s

a) What typ e is t he t ransistor shown? b) Calculat e I ds when this t ransistor has t he same f3 as t he t ra nsistor in exercise 2 and VT= -1 V.

50

4. Given:

Ｍｾ

d

If this is an n-type enhancement MOS transistor and the current Ids> 0, explain the following: a) This transistor is always in its saturation region. b) This connection is often called a MOS diode. 5. For this exercise , the threshold voltage VT is 0.25 V. There is no thermal generation of electron/hole pairs.

Vg

___1 _ p: ub trate

b

a) The above structure exists when the source and drain areas of an nMOS transistor are excluded. Copy this structure and include the possible depletion and inversion layers for the following values of Vg : -0.6 V, 0.1 V, 0.6 V and 1.2 V. b) An n+ area is now added to the structure in exercise 5a.

51

Vg

r

Vs

p- ub tratc

b

ｾ

Repeat exercise 5a for

= 0 V and for

Vs

= 0.5 V.

c) The sub strate of the st ructure in exercise 5b is connecte d to a negative voltage: Vbb=-l V. What happ ens to the depletion and inversion layers if ｾ = 0 V and Vg = 0.5 V? d) A second n" area is added to the st ructure of exercise 5b to yield the following struct ure.

p- ubs tratc b

Repeat exercise 5a for

ｾ

= 0 V and

Vd

= 0.8 V.

e) In pr acti ce, there are t hermally-generated electron hole pairs in t he silicon subs trat e. The resulting free electrons in t he deplet ion layer move in t he opposite directi on to the applied exte rnal elect ric field. Draw the direction of movement of the t hermally-generated electrons and holes for Vg=1.2 V in t he struct ure of exercise 5a. If this sit uat ion cont inues for a longer period, a new equilibrium is reached and the elect rons and holes accumulate in the structure. Draw thi s sit uat ion.

52

------eF--- Vdd

d

g 6. The following values apply in the figure shown: Vdd=1.2Y , ,6=lmA/V 2 , Vx=-l Y, Vbb = - l Y .

s +

_ _ _--.1._ _

V ss

a) What type is the transistor and why? b) Calculate and draw the graph Ids=!(Vds) for K=Oy 1/ 2 and Vds=O, 0.2, 0.4, 0.6, 0.8, 1.0 and 1.2 Y. c) Repeat b) for K =0.2 y 1/ 2 . d) Assuming K =0 .2 y 1/ 2 , calculate the output impedance of the transistor for Vds=50 mV and for Vds=0.6 Y. (Note: the drain remains at 1.2 Y).

- - - , . - - - - Vdd

w

- = 0.12/0.06

L

7. The following values apply

for the circuit shown: Vd d = 1.2Y, Vbb = -1 Y, V';;s = 0 Y, K =0.2 y 1/ 2 , 2 ,60 = 400 p,A/y , VX L = -1 Y and VX o = 0.2Y.

: --1

load transistor

"----+---0 Vout

Vin

:

W -=4

driver transistor

: L

ｾＭ

Vss

a) Calculate Vout for Vin=1.2Y. b) Determine the transconductance of both MOS transistors for this situation. c) What value does Vout reach when Vin=O.lY? d) The same low output level must be maintained when the load transistor is replaced by an enhancement-type transistor of the 53

same size and with its gate at ｾｪ､Ｇ Does this require a driver transistor with the same and with a smaller or a larger channel width W? Explain your answer.

If

8. The aspect ratio of this transistor is W/ L = 200nm/50nm. Results of measurements on it are summarised in the following table:

d ｉｾ｢

g

I

ｾ｢｛ｖ｝

1

Ids [tt A ]

40

Vgs = IV 360

10

-

Vgs = 0.5V 0 1.25

a) Determine Vx , K and

!3o

8

for this transistor.

b) Calculate and draw the graph VT=ｦＨｾ｢Ｉ values (0 V ＼ｾ｢Ｒ V).

for at least five ｾ｢

9. Define an expression for the transconductance with respect to the substrate voltage ｾ｢ when the transconductance with respect to

the normal gate voltage is defined as gm = Ｚｾ

.

10. Assume that we build a decoupling capacitor between ｾｳ

and using an nMOS transistor with a gate-oxide thickness t ox 1.6nm.

a) Draw how this nMOS transistor is connected between the ｾｳ lines to form this capacitor.

and

b) What would be its capacitance value per unit area? c) Assuming a pMOS transistor operates fully complementary to an nMOSt, how would you connect such a pMOSt as an additional capacitor in the same circuit as in a).

54

11. The following values apply in the figure shown: both nMOS transistors are identical, Vdd = 1 Y, VT = 0.3 Y when k = 0 y 1 / 2.

ｾ

ｾｶ

a) With what type of device could you compare T 1? b) With what type of device could you compare T2? c) What would be the voltage Va when k = 0 y 1/ 2? d) What would be the voltage Va when k = 0.2 yl /2? connections of T 2 would be left open (floating) , e) If one of the ｾｳ what would be the result in terms of operation of the device T 2 and of the operation of the total circuit?

55

Chapter 2

Geometrical-, physical- and field-scaling impact on MOS transistor behaviour 2.1

Introduction

The simple formulae derived in sect ions 1.4 and 1.5 account for the firstord er effects which influence t he behaviour of MOS t ransistors. Unt il t he mid-seventies , formulae (1.18) appeared quite adequate for predicting the performan ce of MOS circuits. However , t hese tr ansistor formulae ignore severa l physical and geomet rical effects which significant ly degrade t he behaviour of MOS transistors. The results are therefore considera bly more optimi sti c tha n the actual performance observed in MOS circuits. T he deviation becomes more significant as MOS tra nsist or sizes decrease in VLSI circuits. This chapter contains a brief overvi ew of t he most import ant effect s, in nanomet er CMOS technologies, which degrade the performance of MOS devices. The cha pte r concludes with a det ailed discussion on transist or leakage mechanisms.

57

2.2

The zero field mobility

As discussed in chapte r 1, th e MOS transist or current is heavily det ermined by t he gain factor f3 of the transistor :

f3 =

w . f30

-

L

w . /-L . Cox

= -

(2.1)

L

where Wand L represent t he transist or channel width and length respectively, Cox represents t he gate oxide capacitance per unit of area and /-L represents the act ual mobility of t he carriers in t he channel. Thi s mobility can be quite different from th e zero-field or subst rate mobility /-Lo, which depends on the doping concent ration in the subst rate . Figure 2.1 shows zero-field elect ron and hole mobilities in silicon at room temp erature as a function of the doping concent rat ion. [cm 2 /Vs]

1500 1250 ｾ

[cm 2 / s)

ｯｮｉｾ

ｾ

35

0 0

cI ctron

l"'l

30 E

'u 25 Eu

ｾ

0

13. 1000

g

0

u

:.E 750

c

20

0

0

' Vi

E

500

15 @

!lpo

ｾ

10

hole '

250

5

10 15

1016

10 17

lOl l!

1019

1020

1021

[atom /cm 3]

Figure 2.1: Zero-field carrier mobility and diffusion coeflicient as a function of doping concent ration in silicon at room tem perat ure

For a channel dopin g concentration of 1017 atoms/crrr' , the mobility of electrons (/-Lno) is about three tim es that of holes (/-Lpo), in t he absence of an elect ric field. This is t he major reason that the Ion current (which is the saturation current when Vgs = Vdd) of an nMOS transistor is abo ut 58

two to four times higher than t he Ion of an equally sized pMOS transistor, depending on the technology node. It also depends on the transistor st ress engineering and crystal orientation. However , severa l other effects dramatic ally reduce the mobility of t he carriers in the channel. These are discussed in section 2.3.

2.3

Carrier mobility reduction

During norm al transisto r operation, electrical fields are applied in both t he lat eral (horizont al) and transversal (vertical) directions, which influence t he mobility of the carri ers in t he channel. Moreover , when the chip temp erature is increased, eit her by an increase of the ambient t emperat ure or by t he chip's own dissipat ion, thi s will have a negative effect on t he carrier mobility and thus on t he (3 of each t ransistor.

2.3.1

Vertical and lateral field carrier mobility reduction

During norm al operat ion, the effect ive mobility /-l of t he carriers in the transistor channel is degraded by t he mechani sms indicat ed in figure 2.2. These include the vertical electric field E z , the lat eral elect ric field Ex and the carrier velocity v .

gate

p- sub trate Figure 2.2: Compo nents which affect carrier m obility in MOS transistors

When the vertical electric field E; is high, t he minority carriers in an n-chann el device are st rongly attracted to the silicon surface, where they 59

rebound. The resulting 'surface scattering' is indicated by the dashed lines in figure 2.2. This causes a reduction of the recombination time and of carrier mobility f-l with increasing E z . In [1], some experimental results are presented with respect to the vertical field carrier mobility degradation. The vertical electric field depends on the gate voltage and on the substrate voltage . The relationship between these voltages and the mobility can be expressed as follows: f-lo

f-l

= 1 + 01 (Vgs - V

)

+ 02( ｢ｾｖ

+ 2 Vgs - VT ) The saturat ion curre nt specified in equation (1.15) must be changed to account for the effect ive channel length. T he modified expression is as

64

shown in equation (2.12). Idssat

=L

w

-

b..L

f30

CLM

. -2 . (Vgs -

2

(2.12)

where b..L is the lengt h of the depletion region at the silicon surface between the inversion layer and the drain. In the above expression, th e total field-dependent mobility degradation, as discussed before, is not included. The voltage Vds - Vdssat across t his 'pinch-off' region modulates b..LCLM. Thi s effect can be modelled by:

b..LZ u vI = a In (1 + Vds ｾ ［ ､ ｳ ｡ ｴ Ｉ

(2.13)

where a and Vp are constants , which may vary with the tra nsisto r geomet ry. The expression clearly shows t he relation between b..LCLM and t he amount of Vds voltage above Vdssat . T he above discussions show t hat t he additional cont ribut ion to t he drain current of a MOS tra nsistor operating in t he saturation region is proportional to Vds - Vdssat . This effect is somet imes approximated by t he following modified current expression: (2.14) Where I dsQ is the tra nsistor current when t he channel length modul ation is ignored, and oX is a semi-empirical channel length modul ation par amete r, whose reciprocal value (1/ oX ) is analogous to t he BJ T Early voltage . The effect of this channel length modul ation on t he I ds = !(Vds) characte rist ics is shown in figur e 2.6, where t he extrapolation of t he curves in t he saturation region would all intersect t he x-axis closely to the point

it».

65

1.5 [V] 2

1.25 1.0 0.75 0.5 ｏｾＭｩＫ

o

0.5

1.5 Vds [V]

Ｍｾ

Figure 2.6: Effect of channel length mo dulation on the MOS transistor characteristic

Channel-lengt h modulation is an undesired effect, which is par ticularly an issue for analog design. Because channel-lengt h modulation is a shortchannel effect which rapidly decreases with longer cha nnels, analog designs ty pically require larger t han minimum t ransist or channel lengths to improve t he performance and operating margins.

2 .5

Short- and narrow-channel effects

T he electrical behaviour of a MOS t ra nsistor is primar ily det ermi ned by its gain fact or {3, its t hreshold voltage VT and its body fact or K. Generally, t he values of these parameters are largely depe ndent on t he width W and length L of a tra nsistor. T he influence of t hese dependencies increases as t ra nsistor dimensions decrease. T hese small-channel effects, which are discussed below, are part icularly significant in deep-subrnicron and nanometer MOS processes.

2.5.1

Short-channel effects

The cross-secti on present ed in figure 2.7 is used to explain short-channel effects.

66

- - - -

- - - -..

Depletion boundary

Figure 2.7: Cross-section of a short-channel transistor, showing several depletion areas that affect each other

Even in the absence of a gate voltage, the regions under the gate close to the source and drain are inherently depleted of majority carriers, i.e., holes and electrons in nMOS and pMOS transistors, respectively. In a short-channel transistor, the distance between these depletion regions is small. The creation of a complete depletion area under the gate therefore requires a relatively small gate voltage . In other words, the threshold voltage is reduced. This is a typical two-dimensional effect, which can be reduced by shallow source and drain diffusions. However, the associated smaller diffusion edge radii cause a higher electric field near the drain edge in the channel when Vds> Vgs>VT. One way to overcome this problem is to reduce the supply voltage. This short-channel effect on the threshold voltage occurs at shorter gate lengths and causes threshold voltage roll-off, see figure 2.8).

67

0.60

/

reverse short-c hanne l effec t

0.50

ｾ

0

00

.s

"0 ;. "0

0040 0.30

"0

..c til

ｾ ..c

0.20

hort-ehannel effect (thre hold voltage roll-on)

f-

0. 10 0.00 0. 1

1.0

10.0 [prn]

Gate Length

Figure 2.8: Short-channel and reverse short-channel effect on the threshold voltage VT of an nMOS transistor

The use of shallow source and drain exte nsions (see figure 3.39), with less doping than the real source and drain implants, in combination with local higher doped cha nnel regions (so-called halo or po cket implants) suppresses the depletion-layer width in the channel and cont ributes to a reduction of the short-channel effect (SeE). The implant is optimised for tra nsist ors with t he smallest chann el lengths in a given pro cess. These transistors will have the nomin al threshold voltage while t ra nsistors with longer channels will have higher threshold voltages. A second effect that depends on t he channel length is the reverse short-channel effect (RS In convent ional CMOS devices, thi s effect, which involves increasing t hreshold voltages V with decreasing gate length, is caused by a lateral non-uniform channel dopin g induced by locally enhanced diffusion. As describ ed before, current devices use so-called halo implants to suppress short -channel effects. Figure 2.9 shows a possible dope profile in a device with halos. In devices with relatively long channels, these halos occupy a smaller region of the channel. When the channel becomes shorte r, these halos get closer to one anot her and will also cause V rollup. In 180 nm CMOS t echnologies and beyond , these halos int entionally cause roll-up and suppress t he onset of roll-off.

68

ource

drain

L

Figure 2.9: Potential doping profile in the channel of a MOS device including the halos

2.5 .2

Narrow-channel effect

Also, t he width of an act ive device influences t he t hreshold volt age. Th e depletion layer extends under t he edges of t he gat e, where t he gate electrode crosses t he field oxide. With a LOCOS ty pe of field isolation, see figure 2.10, t his effect is primarily caused by t he encroachment of the cha nnel stop dopant at th e edge of t he field isolati on.

LO 0

__, Ｍ ｾＭ Ｍ Ｍ Ｍ Ｇ ｴＭｬｾＧ

ｾＭ Ｍ

channel top implant

depletion layer

p" ub tratc

Figure 2.10: Cross-section of a narrow-channel transistor showing the distribution of electric field lines under the gate Th e addit ional depletion region charge has to be compensated by an 69

additional gate voltage. This results in an increase of the threshold voltage at reduced width of the device. The encroachment of channel stop dopant is especially pronounced for a conventional diffused well technology. The channel stop dopants are implanted prior to the hightemperature LOCOS oxidation and cause a large shift in VT. In a retrograde implanted well process, the field oxidation is performed prior to the well implants and less encroachment of dopant atoms occurs under the gate edge. However, the threshold voltage is still increased as a result of the bird's beak and two-dimensional spreading of the field lines at the edge. Figure 2.11 shows this narrow-channel effect, together with the influence of the channel width on the threshold voltage in a Shallow-Trench Isolation (see chapter 3) scheme. In contrast to the conventional narrowwidth effect, the threshold voltage is even decreased at very narrow channel widths of around 0.2 /-lm. This Inverse Narrow- Width Effect (INWE) is attributed to a sharp corner at the top of the shallow-trench isolation. The fringing field at this corner results in an increased electrical field strength and reduces the threshold voltage. Also, the quality of the oxide used to fill the trench is not as good as the thermally grown LOCOS field oxide. A positive fixed oxide charge is present in the oxide and, in nMOS devices, it contributes to the decreased threshold voltage. This contribution of the fixed oxide charge is less severe than the fringing field compound and depends also on the deposition method used to fill the trench.

70

,.......,

LOCOS + Conventional well

100

>

S ......... II)

-'"

01l

'0 > "0

'0 ｾ ｾ

50 LOCOS + Retrograde well

0

'" ｾ Eo-
l 'b - -3

10-9

-1.0

-0.5

0.0

0_5

1.0

Vgs [V]

Figure 2.19: Most dominant contrib utions to the tota l leakage current in an nMO S transistor in a low-leakage 65 nm CMOS technology at 25 0 C and 125 0 C (top), and at different back bias voltages (bottom) The subthreshold current is exponent ially proportional with t he te mperature , while the gate t unnelling current is almost completely independent of it . For an nMOS tra nsisto r in a general-purpose 65 nm CMOS technology, t he cont ribut ions of the gate and subt hreshold currents will

84

dramatically increase, because such a process has a much thinner gate oxide and a smaller VT.

130nm

IOOnm

65nm •

ubthre hold leakage from ource

•

Gate-induced drain leakage (GIDL)

•

Junction rever e-bia leakage Gate-leakage (direct tunneling)

Figure 2.20: Relative contributions of the various leakage mechanisms to the total transistor leakage current [12J Figure 2.20 shows an example of the relative contributions of the various leakage mechnisms to the total transistor leakage current [12], which itself increases exponentially (Figure 2.21; [13]) with further technology scaling. It reflects a process with very thin gate oxide . However, these contributions may vary dramatically between different technology nodes and between low-power and general-purpose processes from different foundries.

85

Intel 20 nm / trans: lor

I. E-04 ｴＭｾＬＮＧＢ］

I. E-06

t--z-__'-""oli,.........z....- - - - - - - - - - - -

I . E-08

f---;------""""':Od Hor oXldo

Figur e 3.41: STI process cross-section after thi ck oxide deposition In dense areas, the oxide level is well above the silicon nitride, while the oxide t hickness equals the deposited oxide t hickness in large open areas. The remainin g topology is planarised using CMP , see section 3.8. The nitride layer is used as chemical etch stop, see figure 3.42.

Figure 3.42: SEM cross-section after eMP 162

Next, the nitride masking layer is removed, using a wet etch and subsequently sacrificial oxide, gate oxide (by ALD) and polysilicon is deposited, etc. Figure 3.43 shows a cross-section through the width of the device. The gate oxide between the polysilicon layer and the monocrystalline silicon substrate can be as thin as 1 nm in very advanced nanometer CMOS ICs.

Figure 3.43: TEM cross-section through the width of the device In this way, device widths far below 100 nm can be well defined. Figure 3.44 shows a comparison between LOCOS and STI field isolation techniques. It is clear that the STI is much more accurately defined and enables the creation of high aspect-ratio field-oxide isolation areas to improve the circuit density in nanometer CMOS ICs.

163

Figure 3.44: Comparison between LOCOS (top) and STI field isolation (bottom) techniques

Retrograde-well formation

A retrograde-well process (figure 3.39) uses both n-wells and p-wells, and is also called a twin-well process . These wells form the substrate for p-type and n-type devices, respectively. High-energy implantation of the wells yields doping profiles with maxima between 250 and 600 nm beneath the wafer surface in active areas. The maximum dope level beneath thick oxide areas (STI areas) is only a short distance below the bottom of these oxides. The implantation therefore acts as a very effective channel stopper for parasitic devices in these areas. Only a limited temperature is required to drive the well implants to appropriate depths, which results in limited lateral diffusion. Conse-

164

quently, the wells can be accurately defined and their separation from source and drain areas of their own type (e.g., n-well to n" source/drain regions and p-well to p+ source/drain regions) can be relatively small. This is the most important reason for applying retrograde-well processing. Each well can be optimised to yield the highest performance for both types of transistors. This can be done by minimising source/drain junction capacitances and body effect or by using an 'anti-punch-through' (APT) implant. Another advantage is the associated feasible symmetrical electrical behaviour. In addition, the two wells are usually each other's complement and can be formed by defining only a single mask during the design , while the other one is defined during the post processing or chip finishing. Also the throughput time for a retrograde well is shorter than that of a diffused-well . Finally, another significant advantage of twin-well CMOS processes is formed by the better scaling properties, which facilitate the rapid transfer of a design from one process generation to another. The consequences of scaling are extensively discussed in chapter 11. Optimizing technologies for high-speed digital designs generally degrades analogue circuit performance of long-channel devices . Careful optimisation of the front-end process (including the wells) is required to improve mixed analogue/digital circuit performance [24] .

Drain extension The hot-carrier effect, which will be discussed in chapter 9, manifests itself more when carriers acquire more kinetic energy than about 3.2 eV. In 1.2 V processes and below, it becomes almost impossible for the charge carriers to penetrate into the gate oxide (energy equals q . V = 1.2 eV in a 1.2 V process) . Carriers can only acquire such energies after a lot of collisions in the pinch-off region. As the pinch-off regions are very narrow for nanometer CMOS technologies, this is becoming very unlikely to happen. The LDD (chapter 9) implants, as used in processes of 0.35 JLm and larger to reduce the probability of occurence of hot carriers, are thus replaced by a more highly doped source/drain extension (figure 3.39). This source and drain extension is produced similar to the LDD. However, the peak doping concentration (::::; 1 . 1020 - 2 . 1020 atoms /cm') , today, is much higher than usually applied in an LDD and almost equals the peak dope in the highly doped source and drain regions. It results 165

in a lower series resistance. Moreover, oxide spacers have been mostly replaced by nitride spacers and a lot more doping-profile engineering has been performed, to create smooth junctions tot reduce junction leakage (band-to-band tunnelling). This is achieved by a combination of three different implants: a very thin off-axis As implant for the source/drain extension, a much deeper As n" implant for the source/drain formation, followed by an even deeper Phosphorous implant with a reduced doping, to create the smooth junction. This source/drain extension implant is much less deep (10-20 nm) than the actual source/drain junctions, which allows a better control of the channel length and reduces the short-channel effects. Actually, such an extension acts as a hard minidrain. In some cases in literature, only one implant is used to create the drain. This is then without extension implant, and called Highly-Doped Drain (HDD). The phosphorous halo with increased dope in the channel around the drain, reduces the depletion layer thickness and suppresses short-channel effects such as threshold roll-off and punch-through.

Silicides, polycides and salicides Silicidation is the process of creating a surface layer of a refractory metal silicide on silicon. Silicides may be formed by the use of TiSi2, WSi 2, CoSi2, NiSi or other metal silicides. When, for example, a titanium film is deposited directly on a silicon surface, after the definition of the polysilicon and the formation of the source/drain junctions, the titanium and the silicon react to form a silicide layer during a subsequent heating step. Titanium (and some other metals) react with exposed polysilicon and source/drain regions to form TiSi2 silicide (or other silicides). A layer of titanium nitride (TiN) is formed simultaneously on the silicon dioxide. This will be selectively etched away. Silicidation yields low-ohmic silicide top layers in polysilicon and source /drain regions to reduce RC delays by five to ten times, and improve circuit performance. Because the silicidation step is maskless, it is also called self-aligned silicide or salicide. In a polycide process only the polysilicon is silicided . Sheet resistance values for silicided and unsilicided source, drain, and polysilicon regions are presented in table 4.2 in chapter 4.

Ti/TiN film Titanium (Ti) is used in the contact holes to remove oxides and to create a better contact with the underlying silicide. A titanium nitride (TiN) 166

film is used in the contacts, as well as on top of the PETEOS (plasmaenhanced tetra-ethyl orthosilicate) oxide , because of its good adhesive properties. When the tungsten is being etched away with a plasma, TiN is used as an etch stop. The TiN is also responsible for an increased resistance of the contact plugs.

Anti-Reflective Coating (ARC) Reflections during exposure of a metal mask may cause local narrowing in the resist pattern and, consequently, in the underlying metal pattern, which is to be defined. A titanium nitride film is often deposited on top of the metal layer and serves as an Anti-Reflective Coating (ARC). Today, organic ARC is used during all lithographic steps in nanometer technologies. This film is highly absorbent at the exposure wavelength. It absorbs most (>::::: 75%) of the radiation that penetrates the resist. It also suppresses scattering from topographical features .

Contact (re)fill In many processes, particularly those which include planarisation steps, oxide thickness may vary significantly. Deep contact holes with high aspect ratios require special techniques to guarantee good filling of such contacts. This contact filling is often done by tungsten, called (tungsten) plugs, pillars or studs. As these aspect ratios become more aggressive with scaling, poor step coverage and voids in the contact plug become apparent. To fill the plugs void-free , very thin Ti and TiN films are used as a low resistance glue layer for better adhesion to the dielectric.

Damascene metal patterning In 0.18 fim CMOS processes and above , metal patterning is done by depositing an aluminum layer , followed by a dry etching step to etch the aluminum away according to a mask pattern. In the damascene process, copper patterns are created by etching trenches in the dielectric, overfilling these trenches with copper and then polishing the overfill away using CMP, until the polishing pad lands on the dielectric. Damascene copper processing is discussed in some detail in section 3.6. Damascene patterning is used , particularly in 120 nm and below, to form copper wires. In a dual-damascene process, plugs (studs, pillars) and wires are deposited simultaneously. This process replaces the deposition of the plug and its etching, thereby reducing processing costs. 167

The damascene process is mainly used to pattern copper, which cannot be etched like aluminium in plasma reactors. The copper will create too many by-products which remain on the surface and cannot be removed. The use of copper instead of aluminium for interconnection results in a reduction of the interconnection resistivity by 25 to 30%. This advantage is mainly exploited by a reduction of the metal height, so that about the same track resistance is achieved , but at a reduced mutual wire capacitance. This serves two goals: power reduction due to the reduced load capacitance of the driving gate and cross-talk reduction due to the smaller mutual wire capacitance to neighbouring wires. In combination with the use of low-E dielectrics, the speed can be improved even more , or the power can be reduced further. Copper can also withstand higher current densities (reduced chance of electromigration, see also chapter 9).

3.9.4

CMOS technology options beyond 45nm

Approaching the end of Moore's law, by reaching the physical limits of scaling planar CMOS devices, has challenged both process and design engineers to create solutions to extend CMOS technology scaling towards 10nm feature sizes. Local circuit speed is dominated by the devices (transistors' driving currents) while the global speed is dominated by a combination of the devices and interconnects (signal propagation) . There are several issues related to the continuous scaling of the devices and interconnects. Devices

The transistor's driving current depends heavily on its threshold voltage and carrier mobility. Scaling introduces several mechanisms that reduce this mobility, directly or indirectly. First of all, the carrier velocity saturation and surface scattering affects, introduced in chapter 2, are responsible for a two to six times mobility reduction. Apart from this, there is an increased depletion of the bottom side of the polysilicon gate (gate depletion; gate inversion), due to the increased levels of halo implants for suppression of short-channel effects. Because mainly this bottom side of the gate is responsible for the drive current of the transistor, this gate depletion will dramatically reduce it. Current R&D focus is on the potentials of fully-silicided (PUSI gate) and metal gates. It has proven very difficult to replace polysilicon gates with an appropriate metal-gate

168

material. This is due to the fact that the metal workfunction (which also determines the VT) is affected by the metal-gate composition, the gate dielectric and heat cycles. Few metal gates have been identified giving a correct VT after integration in a manufacturable CMOS process flow. In a FUSI gate the chemical reaction during silicidation continues until the gate is siliced all the way down to the bottom of the gate. Its operation then resembles that of a metal gate, and does not show bottom depletion. It is expected that FUSI or metal gate may be introduced in the 45 nm or 32 nm CMOS node . The conventional way of increasing the transistor current is to reduce the gate-oxide thickness. But with oxide thickness values (far) below 2 nm the transistor exhibits relatively large gate leakage currents, which increase with a factor of ten for every 0.2 nm further reduction of the oxide thickness. A high-E gate dielectric (hafnium oxide, zirconium oxide and others) is therefore a must to continue device scaling with an affordable leakage budget. The search for the right combination of high-s gate dielectric with the right gate electrode with the right work function and tolerance to high-temperature process steps is very difficult. Intel has developed a so-called gate-last CMOS process, in which the sources and drains are created before the gate electrode, and has developed the Penryn dual-core processor with 410 million transistors in 45 nm CMOS with high-s gate dielectrics and metal gate [25] . Another way of increasing the transistor current is to improve the channel mobility. The use of strained silicon is one of the alternatives to achieve this. To achieve the best mobility improvements, the strain should be compressive for the pMOS transistors and tensile for the nMOS transistors. In unstrained nanometer CMOS processes the average hole mobility in the silicon is about two times lower than the electron mobility. Therefore, in many cases, the improvement of the pMOS transistor mobility has been given more priority. In a strain-relaxed buffer (SRB) technology, a SiGe layer is grown on a silicon substrate. Germanium atoms physically take more space than silicon.

169

atoms. nMOS and pMOS transistors react differently under the influence of strain. As a result , the introduction of tensile strain improves the performance of nMOS devices while it degrades the performance of pMOS devices and vice versa. nMOS and pMOS devices ar e therefore built with built-in t ensile and compressive strain, respectively.

. .

.

.

..

Figure 3.46: Use of process-induced strain to enhance mobility in an nMOS transistor (left) (Source: ST Microelectroni cs) and a strained Si1 - xG ex film in th e source and drain areas of a pMOS transitor (right) (Source: NXP Semiconductors) The carrier mobility in the channel is also related to t heir physical crystal orientation (see also section 3.2). It is known that the mobility of holes in a (110) silicon substrate with a current flow along the < 110> direction is about two times higher than in conventional (100) silicon. A combination of (110) orient ed cryst al lattice for the pMOS transistors with a (100) lattice for nMOS provides a much better balanc e between nMOS and pMOS transistor performance. The (110) orientation for the pMOS could lead to a 45% increase in drive current [29]. Figure 3.47 shows a cross section of a potenti al nMOS and pMOS device architecture built with different cryst al orientations.

171

BOX

( 110) cpi-I a)'cr

(100) i1icon handle wafer

Figure 3.47: Hybrid-substrate architecture with nMOSt on (100) and pMOSt on (110) crystal orientation

Figure 3.48 shows a summary of a potential technology options to boost t he intrisic device speed.

dual work function metal gate

lin i)O.

I

gate

Tensi le com pressive dual , E. L • pa erwidih

- -...ｾＭ

Ｍ

ｾ

.............. ,' MO. : ( IOO) , < 100 I'MO ' :(IIO) , < 110>

- 20nm

dielec tric

TI c. ten sions

Dual orientation

ub irate :

Figure 3.48: Potential technology options for performance boost of MOS devices (Source: NXP Semicondu ctors)

The optimum combination of st ress and device orientations has driven and will st ill further drive the Ion to much higher values t han available in to day's high-volume CMOS processes as discussed in chapte r 2.3.1. Figure 3.49 shows t he relati ve improvement s of t he Ion currents for nMOS and pMOS tra nsistors, respectively, relative to t he year of mass produ ction [30].

172

1400r----------;,.-------,

E::1.

l

-

'-'

co

1200 1000 800 600 400 L . . . - - - J - _ . L . - - - - J - _..........- . . J . . _..........- - - L - - - '

200 2 200 3 2004 2005 2006 2007 2008 2009 20 I0 MP Year (estimated)

9oor-----------..,----., 800

E ::1.

< 2:

pFET

•

700 600 500 400

300 2001-----J1----J.-

--'--

-'--

..L--

..L----J1----1

2002 2003 2004 2005 2006 2007 2008 2009 20 I0 MP Year (estimated)

Figure 3.49: MOSFET performance trend relative to estim ated m ass production year. I off

= 100 nA/f.Lm

and vdd

= 1.0 V . [3D}

However , it is not only t he rea l value of Ion that counts, bu t it is more t he total Ids = f(Vds) characteristic that counts, because during switching t he transistor cycles through the whole cur rent to voltage characteristic. A fourt h alt ernative to increase t he transistor current is to use a doub le-gate or F inFET t ra nsistor. In a double-gate transistor (figure 3.50.a) , the t ra nsistor body is st ill lat eral, but embedded in between two gates, a bot t om gate and a to p gate. Above a certain thickness of t he body, t here are two parallel cha nnels contribut ing to t he total current of t he device , which now behave as two parallel fully-de plete d SOl transistors.

173

(a)

(b)

Figure 3.50: a) Double-gate transistor and b) cross section of a FinFET (Source : NXP Semiconductors)

In a FinFET architecture, a narrow vertical substrate, about 10 to 30 nm thick (figure 3.50.b) , is located on top of a BOX (burried-oxide) layer and then covered with a thin gate-oxide layer. Then a thin metal layer with a poly silicon cap is formed, covering the gate-oxide areas at all sides: left, top and right side. If the fin (or body) is very thin, this device will operate as a fully-depleted SOl transistor with a higher driving current , due to the parallel current channels. The width of the transistor is determined by the height of the thin substrate, meaning that only onesize (width) transistors can be fabricated. In this example device the transistor width is equal to the width of the fin + two times its height, resulting in a transistor width of 130 nm . The double-gate and FinFET devices are also called multi-gate FET or MuGFET. These devices help to control leakage currents and reduce short-channel effects. Because they do not exhibit doping fluctuations, their matching properies are expected to be much better. However still a lot of innovations from both the technologists and the designers are required to economically build complex ICs with them at reasonable yield. Interconnects

There are several reasons why future CMOS ICs still need an increasing number of interconnect layers. Every new technology node offers us more transistors at a two times higher density. This requires more metal resources to support the increasing need for connecting these transistors. Secondly, they require a more dense power distribution network to be able to supply the increasing current needs. Since the introduction of 120 nm CMOS technologies, the aluminium back-end has been

174

replaced by a copper back-end. Due to th e requir ed use of a barrier layer in the copper (sect ion 3.6) formation pro cess, t he effective copper met al t rack resist ance has only reduced by about 25% compared to aluminium. This has been exploited by reducing the metal height , so t hat met al tracks show resistances compara ble to aluminium , but show less mutual capacitance to neighbouring signals, while maint aining t he signal propagation across t hem. However, further reductions of t he metal height s are limit ed by t he increasing curre nt densities and the chance of electromigration. There is also an issue in t he scaling of t he contacts and vias. Since t heir number and aspect ratio (height/width ratio ) increase with scaling, while t heir sizes decrease, t hey are becoming a very important part in the determination of the global chip performance, reliability and yield. Because of the increasing currents, t he contacts and vias show an increasing amount of volt age drop, particularly when the signal line switches many times from one metal layer to anot her. Another result of the increasing current is t he increased possibility of electromigra tion occurrence, thereby t hreate ning t he reliability. Fin ally, due to the high aspect ratios , t here is an increased chance for bad contacts or opens, which will affect the yield. Already today, but certainly in t he future, design for m anufacturabilty (DfM) becomes an integral part of t he design flow to support yield-improving measures (see also chapte r 10). A few examples are: 1) wire spreading, where wires are route d at larger pitches (spreade d) beca use t here is more area available t han needed by minimum pit ch rout ing and 2) via doubling, where more vias are used for t he same connectio n to improve yield. Most of t he further improvements of t he int erconnect network has to come from further reduct ion of t he dielectri c constant (lOW- E dielectri cs) of the inter-level dielectric (ILD) layers between the metal layers and between t he met al lines within one layer. During t he last two decades, t his dielect ric constant has gradually reduced from 4 to 2.5. It is expected that it will reduce to close to 2, but it still needs many innovations to guarantee sufficient reliability. Some research is current ly focused on airgaps, in which the dielectric material between met al lines in the same layer is replaced by air only. This will reduce the dielectri c constant t o even below 2 (t he effective dielectric constant will not be equal t o 1 (of air) , because t here are also mutual electric-field lines from the top and bottom areas of neighbouring met al lines. The reliability of t hese air gaps is an even bigger challenge. The combined move from aluminium to copper wiring and from oxide

175

to low-E dielectrics required a change in the bonding process because the adhesion and stability are different. LOW-E dielectrics are more porous and include more air, so they become less robust and more sensitive to plasma damage during damascene processing and to pressure during test (probing) and bonding. Particularly when bond-over-active techniques are used, where pads are not only located at the chip's periphery but also on top of circuits, these low-E dielectrics must guarantee sufficient reliability. So, changing pad-related design and technology concepts also influences the reliability of the bonding process . Poor bond pad surface contamination may lead to a bond pad metal peel-off which leads to wedge bond or ball bond lifting . Finally, the continuous process scaling also affects the copper resistivity level. Further scaling leads to an increase of the copper resistivity due to side-wall, grain-boundary and impurity scattering effects which reduce the electron mean free path to 40nm. It also drives the need for ultra-thin, high conductivity barriers and the exploration of "barrierless" approaches. Figure 3.51 shows the expected trend according to the 2006 ITRS roadmap [31]. A further discussion on copper resistance and its modelling can be found in [32].

176

1

,.......,

E

ｾ

8

7.5 7

U

6.5

..........

6

Q)

o 5.5 s:: ro .....

.-

r.Il r.Il

Q) I-. Q)

.:::..... U

5

4.5 4

ｾ Vdd

The output high level must be equal to the suppl y voltag e, i.e., Vout = VH = V dd . Therefore, ｾ Vout = Vdd - VL. Assumin g VTA ｾ VTL yields the following expression for a: a

2VTL > ...,-------"--Vdd

-

VL

(4.3)

• If Vin=VH , then Vout= VL and the gate volt age of the load transistor

T L is Vdd - VTA ｾ Vdd - VTL· Load transistor TL t herefore operates in the saturation region when Vout=VL. The aspect ratio of the bootstrapp ed inverter is t herefore identi cal to that given in equation (4.1) for the inverter with a saturated enhancement load transistor. The bootstrapp ed inverter has the following advantages: 1. There is no threshold loss when the bootstrap capacit ance C is

correct ly dimensioned. 2. There is no ext ra supply voltage required, because the voltage VI is pumped to more than a threshold voltage above Vdd.

193

3. This basic bootstrap mechanism is also called a charge-pump , which is used in many E(E)PROMs and flash memories to generate the much higher programming and /or erasing voltages . To achieve such high voltages (2: 10 V), several of these charge pumps are put in series.

The depletion load transistor The manufacture of depletion transistors requires an extra mask (Dr) and additional processing steps. There are , however, considerable advantages associated with the use of a depletion transistor as load element. These include the following: • The output high level equals

Le.,

V

• There is no extra supply voltage required; • Circuit complexity is minimal and bootstrapping is unnecessary; • Noise margins are high. For these reasons, before the move to CMOS, most nMOS processes were 'E/D technologies' and contain both enhancement and depletion transistors. Some manufacturers, today, even include depletion transistors in their CMOS technologies. Figure 4.6 shows an inverter with a depletion load transistor.

load

Figure 4.6: An inverter with a depletion load transistor The DC operation of the inverter with a depletion load transistor is described as follows :

194

• The depletion load transistor has a negative threshold voltage which was usually between -1 V and -3 V. Therefore, Vout=VH=Vdd when Yin=VL

//\pMOSt contribution .' \ -+-'.,/ nMOSt contribution ,---------I

-t Figure 4.28: CMOS transmission gate behaviour and the individual contributions of the nMOS and pMOS transistors to the charge and discharge characteristics

Pass-transistor logic

In static CMOS circuits, transmission gates are used in latches , flipflops, 'pass-transistor logic' and in static random-access memories. Examples of pass-transistor logic are exclusive OR (EXOR) logic gates and multiplexers. Figure 4.29 shows pass-transistor logic implementations of an EXOR gate. The nMOS transmission gate implementation in figure 4.29(a) is disadvantaged by high threshold loss resulting from 223

body effect. The complementary implementation in figure 4.29(b) yields shorter gate delays at the expense of larger chip area. When connecting the outputs of these gates to a latch circuit (e.g., two cross-coupled pMOS loads), a static CMOS logic family is created (figure 8.17). The threshold voltage loss over the nMOS pass gates is compensated by the level restoring capability of the latch.

nMOS

CMOS

li

ii

(b)

(a)

Figure 4.29: Pass-transistor logic implementations of an EXOR logic gate with (a) nMOS pass transistors (b) CMOS pass-transistor gates A general disadvantage of pass-transistor logic as presented in figure 4.29 is the series resistance between the inputs a and a and the output z . The charging and discharging of a load at the output through the pass transistor causes additional delay. Other disadvantages include the need for complementary control signals. The potentials of pass-transistor logic challenge the creativity of the designers . Several alternatives have been published. These are discussed in detail in the low-power chapter 8, together with their advantages and disadvantages. Finally, circuit designs implemented with pass-transistor logic must be simulated to prevent unexpected performance degradation or even erroneous behaviour caused by effects such as charge sharing (section 4.4.4) . With decreasing voltages in current and future processes, the performance of pass-transistor logic tends to drop with respect to standard static CMOS logic. Therefore, the importance and existence of passtransistor logic is expected to decrease in the coming years. The forms of CMOS logic discussed above can be used in both asynchronous circuits and synchronous, or 'clocked' , circuits. The latter type of circuits 224

are the subject of the next section.

4.4.3

Clocked static CMOS circuits

Signals which flow through different paths in a complex logic circuit will ripple through the circuit asynchronously if no measures are taken. It is then impossible to know which signal can be expected at a given node and time. Controlling the data flow inside a circuit therefore requires synchronisation of the signals. Usually, this is done by splitting all the different paths into sub-paths with a uniform delay. The chosen delay is the worst case delay of the longest data ripple. In synchronous static CMOS circuits, the sub-paths are separated by means of 'latches' and /or 'flip-flops' which are controlled by means of periodic clock signals . Dynamic circuits may also use latches and flip-flops. Alternatively, data flow in dynamic circuits may be controlled by including the clock signals in every logic gate.

Static latches and flip-flops Latches and flip-flops are used for temporary storage of signals. Figure 4.30 shows an example of a static CMOS latch and an extra transmission gate. The transmission gate on the left-hand side is an integral part of the latch, which also comprises two cross-coupled inverters. Complementary logic values can be written into this latch via the transmission gates when the clock signal is high , i.e., when

circuits, 489 asynchronous-> design, 489, 491 ATE, 594 atomic layer deposition, 142,315 ATPG , 609 Attenuated Phase Shift Mask , 113 AttPSM ,113 Automatic Test Equipment, 594 AVS, 456, 471 AVT,555

back-bias, 453 rv controlled VT , 453 rv effect, 27, 201, 454 back-end design, 392 back-gate effect, 27 backscattered electrons, 674 ball grid array, 634 basic rv CMOS process , 158 rv Complementary MOS process, 158 rv MOS technologies, 153 rv silicon-gate nMOS process , 153 battery, 448 rv RAM , 346 rv energy, 449 rv memory effect, 450 BCCD, 262 BCCD surface-state immunity, 265 BCD , 272 rv counter, 488 behavioural simulation, 392 best-case corner , 305 BGA , 634 712

BICMOS rv NAND gate, 280 rv characteristics, 279 rv circuit performance, 280 rv digital circuits, 275 rv performance, 282 rv technology, 275 bipolar rv gain factor , 279 rv noise, 279 Bipolar-CMOS-DMOS, 272 bird 's beak, 135 rv suppression, 135 BIST , 604 BISTAR, 605 bit line, 296 rv select, 296 bit-parallel operation, 381 bit-slice layout, 407 block, 414 f3n, 207 BOA, 638 body rv bias, 454 rv effect, 27, 100, 652 rv factor , 28 bond-over-active, 176, 638 bootstrap-capacitance, 192 bootstrapped load , 192 Boundary Scan Test, 607 BOX layer, 101 f3p , 208 BPSG , 138 BRAM , 346 breakdown rv mechanism, 651 rv voltage, 270 bridging faults, 602 BST, 315, 607

charge

bubbles, 117 buffer circuits, 209 Built-in Self Test , 604 built-in self-test and repair, 605 bulk silicon, 95 buried-channel CCD, 262 buried-oxide layer, 101 burn-in test , 316 burst mode , 300 bus latency, 693

bucket , 262 rv characteristic, 207 rv distribution, 12 rv sharing, 224, 232 rv transfer, 264 charge-coupled device, 261, 262 charge-pump, 194 charged-device model , 576 CHEI , 336 Chemical Mechanical Polishing, 147 Chemical Vapour Deposition, 138 chip , vi rv select, 297 chip-scale rv package, 631, 639 rv packaging, 624 choice of logic implementation, 235 circuit rv density, 159 rv simulation, 48, 393 circuit editing techniques , 679 circuit-analysis program, 196 class-one clean room, 611 clean room , 611 rv convent iona l standard, 611 clock rv activity, 495 rv generation, 523 rv jitter, 520, 527 rv signals , 225 rv skew, 227, 231, 236, 518 rv tree synthesis, 519 clock-phase synchronisation, 525 clocked CMOS circuits, 225 clocking strategies, 236 CMOS , 200 rv

cache register, 340 CAD tools , 367 CAM, 290, 294 capacitances, 42 capacitor-under-bitline, 317 carrier mobility reduction, 59 Cascode Voltage Swing Logic, 234 CBRAM, 349 CCD , 261, 262 CCD cell, 263 CCD operating frequency, 265 CCD shift register, 262 CCO ,524 CD , 120, 124 CDU , 124 cell abutment, 481 cell-based IC design , 369 channel rv conductance, 31 rv dope , 5 rv hot electron injection, 336 rv hot-ele ctron injection, 339 rv length, 120 rv length modul ation, 64 rv stopper, 153, 164 rv stopper implant, 35 channel-free gate array, 416 channel-less gate array, 416 characterisat ion tests, 591 713

NAND gate, 280 buffer design, 213 rv buffer optimi sation , 213 rv driver, 238 rv image sensors, 261 rv inverter , 201 rv inverter design, 207 rv inverter dissipation, 209 rv inverter t ra nsfer characteristic, 203 rv latch, 225 rv out put buffer, 238 rv parasitic bipolar device, 645 rv process, 158, 240 rv transmission gate, 222 CMP, 147 column decoder , 296 compiled cell, 369 Complementary Pass-Transistor Logic, 477 complex PLD , 430 compressive st rain, 170 comput ing power , 501 conduct ion band , 6 conduct ive brid ging memory, 349 constant-field scaling, 696 const ant-volt age scaling, 689, 695 cont act filling, 167 CONTACT mask , 154 CONTACT-mask programmed ROM cell, 332 conte nt-addressable memory, 290, 294 cont inuous array, 417 cont rol rv bus, 374 rv path, 379 copper, 692 core, 369, 414 rv rv

714

correct by design, 512 cosmic particles, 328 cost rv of a wafer factory, 706 rv of interconnect , 350 CPL , 477 CP LD, 430 critical rv delay, 522 rv dimension, 124 rv dimension uniformity, 124 rv dimensions, 120 rv modul e, 388 cross-over capacit ance, 233 cross-talk, 233, 529 crystal-oriented particles, 96 CSP, 624, 639 CUB, 317 current density, 2, 142 current-cont rolled oscillator, 524 custo m IC, 369 custo mer returns , 591 custo misation, 366, 415 CVD, 138 CVSL, 234 CVSL logic gate, 234 cycle rv stealing, 522 rv t ime, 293 D-type flip-flop, 226, 263, 418 damascene-« back-end flow , 692 damascene-> patterning, 167 dark current, 264 dat a rv bus, 374 rv inpu t buffer , 296 rv out put buffer , 296 rv path , 379 rv retention time, 290, 338

database set-up, 579 DDR , 322 decision tree, 386 decoupling capacitor, 537 delay fault , 597, 602 delay-locked loop, 527 ｾｉ､ｱ test, 602 depletion rv layer, 12 rv layer thickness , 66 rv process, 12 rv transistor, 33 depletion-> load , 194 deposition, 137, 680 depth of focus, 109 depth-of-focus, 113 design rv documentation, 579 rv efficiency, 688 rv for anything, 622 rv for debug, 664, 682 rv for failure analysis, 682 rv for manufacturabilty, 175 rv for testability, 608 productivity, 350 rv resources , 688 rv rules, 240 rv style, 706 rv verification , 392 Design for Lithography, 118 design-> hierarchy, 579 design-> organisation, 579 design-rule-check program, 406 designing a CMOS inverter, 207 destructive read-out, 311, 347 DfL,118 DfM, 175, 392, 620 DfM-rules, 620 DIT ,608

DfX,622 DIBL, 77 dicing , 628 dielectric relaxation time, 38 Differential Split Level Logic, 235 diffusion, 142 rv coefficient, 143 digital rv CMOS circuits, 218 rv ICs, 368 rv potentiometer, 394 direct slice writing, 368 direct writing techniques, 127 discharge characteristic, 207 dishing, 149 dislocations, 97 disturbances in the production environment, 610 DLL, 527 DMOS transistor, 270 DOF, 109, 113 DOMINO-CMOS, 229 donor, 9 dope profile, 144 Double Data Rate, 322 Double Pass-Transistor Logic, 478 Double Patterning Technology, 121 double-diffused MOS transistor, 270 double-flavoured polysilicon, 137, 158, 203 double-gate transistor, 173 DPL, 478 DPT, 121 drain, 4 rv extension, 154, 165 rv series resistance, 566 Drain-Induced Barrier Lowering effect, 77

r-;»

715

DRAM, 77, 291, 310 DRAMrv architectures , 319 DR AMrv cell, 310 DRC, 406 DRC-rules, 620 drive current , 62 driver tra nsistor , 188 rv characteristic , 188 DRO , 311, 347 DSL, 235 DSW , 368 du al polysilicon, 159 du al-VT concept, 689 du al-damasc ene, 167 du al-dop e polysilicon, 203 du al-edge triggered flip-flops, 496 du al-p ort memory, 327 dummy met al, 150 DVFS , 471 dynamic rv CMOS, 228 rv CMOS circuits , 228 rv CMOS latch, 230 rv CMOS shift register, 230 rv D-typ e flip-flop, 231 rv RAM, 291, 310 rv flip-flop, 230 rv memory, 291 rv power consumpt ion, 450 rv power dissipation, 210 rv shift regist er cell, 230 rv volt age and frequency scaling, 471 rv volt age drop, 536

ECC , 326, 342, 547 EDO , 321 EDO DRAM, 322 eDRAM , 310 EE P LD, 371 effective rv chan nel length, 64 rv tra nsistor channel length, 154 electric rv field, 12 rv pot enti al, 12 electrical endurance test , 646 elect romagnet ic rv compatibility, 542 rv pulse, 542 electromigration, 142, 560 electro n rv mobility, 2 rv valves, 1 electron mobility, 202 electron-beam , 127 Electron-Beam Pattern Generator , 106 elect rostatic rv charge, 614 rv discharge, 573, 645 rv potenti al difference, 16 embedded rv FPGA , 706 rv SRAM , 309 rv arrays, 434 rv logic, 352 rv memory, 290, 351 rv software, 391 EMC, 542 EMP, 542 emulat ion, 389, 392 endurance characterist ic, 338

e-beam, 127 e-sort, 593 E/D technology, 194 early failure rate, 646 EBPG ,106 716

field oxide isolation, 417 Field Programmable Device, 420 field-effect principle, 1 field-programmable device, 371 FIFO , 291, 293 fill factor, 268 filler cells, 436 FinFET, 174 firm cores , 370 first t ime right silicon , 511 first- silicon debu g, 654 flash memory, 339 flat-band rv condition, 16 rv volt age, 16 flip-chip bonding, 631 flip-flop, 225, 226 floating gate, 336 Focused Ion Beam, 680 formal verification, 393 forward-bias effect, 30 FO UP mini enviro nment, 613 four-transistor SRAM cell, 301 Fowler-Nordheim tunnelling , 337 FPGA, 420, 706 FPM, 321 FPM DRAM, 321 FRAM , 346 full adder, 197, 383 full-CMOS SRAM cell, 300 full-custom IC , 369 full-featured EEPROM , 337 fully-regular libr ary, 119 fully-silicided , 137 functional level, 379 FUSI, 137 rv gate, 168

energy band, 6 rv band diagram, 15 rv band theory, 5 rv gap , 6 energy-delay product, 461 enhancement t ransist or, 33 epi layer , 95 epit axial rv film, 137 rv wafer , 95, 572 EPLD , 371 EPROM , 335 equivalence checking, 393 erosion, 150 error-corre ct ion cod e, 326 ESD , 100, 573, 645 eSRAM, 309 etching, 131 EUV, 124 exclusive OR, 223 EXOR gate, 223, 494, 499 Extended Data Out , 321 rv DRAM , 322 exte rn ally-induced voltage alteration, 672 ext reme data rate RDRAM , 326 Extreme-UV lithography, 124 rv

FA, 654 fab-lite, 178, 443 fabless, 178, 443 failure analysis, 654 Fast P age Mod e, 321 rv DRAM , 321 fat zero, 264 FD-SOI, 102 Fermi level, 9 ferroelectric RAM , 346 FIB , 680

gain factor, 58 GALS , 533, 693 717

gate, 4 array, 415 rv delay, 597 rv depletion, 137, 168, 690 rv forest , 416 rv inversion, 168 rv oxidation, 154 rv oxide, 135 rv oxide tunnelling, 690 gate-dra in overlap capacitance, 155 gate-induced drain leakage, 82 gate-isolat ion technique, 417 gate-last CMOS pro cess, 169 gat e-oxide rv leakage, 79 rv leakage current, 457 rv t hickness, 136 gate-source overlap capacitance, 155 gated clock, 497, 521 GDSII , 441 general-purpose rv CMOS processes, 696 rv process, 137 geomet ric layout rv description language, 441 rv represent ation, 441 GIDL , 82 GLDL , 441 glitches, 494 global variations, 551 globally asynchronous and locally synchronous, 693 globally synchronous, locally asynchronous, 533 glue logic, 376 golden device, 602 GP pro cess, 137, 696 gra ded-dra in t ra nsistor, 564 rv

718

Gray code counte r, 488 ground bounce, 536 halo, 68 hand craft ed layout , 406 hand shake circuits , 493 hard cores, 370 hard ware rv accelerator, 392 rv description language, 369, 383 hardware/ software codesign, 389 HCE , 563 HDD, 166 HDGA , 416 HDL, 369, 383 HDP , 133 hemispherical gra in, 314 hetero-epit axy, 138 heterogeneous system, 376 rv on a chip, 523, 687 hierarchical rv design approach, 438 rv layout , 438 high-density gate array, 416 rv layout , 228 High-Density Plasma, 133 high-energy cosmic particles, 543 high-voltage CMOS, 273 Highly-Doped Drain , 166 hillocks, 560 hold-time violation, 519 hole mobility, 202 holes, 7 homo-epit axy, 138 homogeneous sytem, 377 hot carrier, 82 hot electron, 336 hot-carri er effect, 83, 165, 563 hot-electron effect, 339

infant mortality, 646 input protection, 100 integrated circuit, vi Intellectual Property, 369 intellectual property, 391 inter-die variations, 550 inter-level dielectric, 175, 637 interconnect sheet resistance, 692 interlevel metal, 692 interstitial dope atoms, 144 interstitials, 97 intra-die variations, 551 intrinsic rv failure rate, 646 rv silicon, 9 inverse narrow-width effect, 70 inversion layer, 18 inversion-layer transistor, 4 inverter, 186 rv DC behaviour, 188 rv chain, 214 INWE,70 ion rv acceleration, 143 rv implantation, 142 rv implanter, 143 ionisation energy, 8 IP, 369, 391, 523 IR-drop, 518 islands of synchronicity, 533 isotropic, 132 ISP, 420 iterative multiplier, 381 ITRS, 687

HSG, 314 human-body model, 574 humidity rv sensitivity, 646 rv test , 647 HV-CMOS, 273

IC , vi characterisation, 610 rv customisation, 372 rv database, 106 rv design path, 374 rv design rule check, 106 rv early failure rate, 646 rv electrical check, 106 rv engineering, 610 rv floor plan, 388 rv functional check, 106 rv infant mortality, 646 rv intrinsic failure rate, 646 rv layout, 106, 374 rv lifetime , 141 rv package corrosion, 647 rv package robustness, 647 rv quality, 645 rv reliability, 646 rv reliability tests, 646 rv wearout, 646 I ddq testing, 600 ILD , 175, 637, 692 image sensor , 267 immersion lithography, 116 impact ionisation, 82, 563 implantation duration, 144 improved DRAM access time, 319 In-System Programmability, 420 inductance, 533 inert rv gas, 647 rv liquid , 647 rv

joule heating, 563 junction spiking , 146 K-factor, 28, 29, 202 known-good-die, 643 719

LADA, 673 laser '" dicing, 628 '" signal injection microscopy, 669 laser-assisted device alteration, 673 laser-beam, 127 Laser-Beam Pattern Generator, 106 laser-fusing, 328 latch, 225 latch-up, 99, 277, 570, 645, 652 '" sensitivity, 645 rv thyristor, 645 lateral rv diffusion, 154 '" electric field, 60 law for conservation of charge, 24, 40 layout rv description, 526 '" implementation, 439 '" implementation form, 405 rv level, 375, 388 rv process, 240 LBPG , 106 LDD , 564 LDD transistor, 566 LDO, 472 leakage, 83 rv current, 77, 231, 453 rv power, 454 rv power consumption, 451 Lean Integration with Pass- Transistor, 479 LEAP, 479 LER, 124, 551 level shifters, 473 LIFO, 293

720

light-induced voltage alteration, 673 lightly doped drain, 564 line-edge roughness, 124, 551 linear region, 19, 20 litho-friendly design, 118, 252, 551 lithography, 105 LIVA, 673 LL process , 137 load rv elements , 187, 188 rv lines, 188 rv transistor, 189, 190 loadless SRAM cell, 302 Local Oxidation of Silicon, 134 local variations, 551 LOCOS, 153 '" oxide, 158 '" process, 134 logic simulation, 392 logic-gate level, 383 look-up table, 420, 422 LOP, 461 low-dropout regulator, 472 low-end IC market , 366 low-energy cosmic neutrons, 543 low-leakage rv CMOS processes, 696 rv process , 137 low-operating power, 461 low-power rv CMOS, 447 rv library, 476 low-standby power proces , 696 low-standby power process, 137 low-voltage design , 468 LPCVD, 139 LSIM, 669 LSTP, 696

LSTP pro cess, 137 LUT , 420, 422 machine model, 576 macro, 414 rv cell, 369 magnet ic t unnel junct ion, 347 Magneto-resistive RAM, 347 maj ority charge carrier, 11 Manhattan skyline effect, 439 mapping, 391 mask, 94 rv ROM , 329 mask-less lithography, 128 mask-programmable rv ROM , 329, 412 rv gate arrays , 415 masks, 241 master cell, 416 mat ching, 554 rv coeffient , 555 rv of transistors, 690 max imum storage tim e, 264 MCM , 341, 642 meet- in-the-middl e strategy, 439 mega cell, 369 memory rv address, 292 rv array, 290 rv bank, 324 rv banks, 297 rv cell, 290 rv cont roller, 323 rv matrix, 290 rv word, 292 merged memory logic, 352 met al gate, 169 METAL mask , 155 Metal-Oxide-Semicond uctor CMOS) capacitor, 11 721

micro defects, 96 microcode instruction, 412 microcontrol uni t , 379 microprocessor core, 391 milit ary specificat ions, 4 milling, 680 minority carrier, 18 mismatch, 551 MISR, 605, 649 ML2, 128 MLC, 342 MLL, 128 MLR, 127 MML, 352 mobilit y, 32, 58 modul e generator, 438 molybd enum , 4 rv gate, 155 more t han Moore, 644 MaS , 1 rv capacitance, 38, 41 rv formulae, 23 rv t ransistor leakage mechanisms, 74 rv t rans isto r weak inversion operating region, 75 MaS tra nsistor, 5 MPW, 126 MRAM , 347 MT CMOS, 457 MTJ , 347 multi- chip modul e, 642 multi-layer reticle, 127 Multi-Level Cell, 342 multi-level flash memory, 342 multi-p ort memory, 327 multi-p roj ect wafers , 126 Multiple Inpu t Signature Register, 649

multiple threshold CMOS, 456 Murphy's law, 100

rv memory, 290 normally-off transistor, 33 normally-on transistor, 33 NRE costs, 402 NROM, 345 number representation, 484 NVRAM, 345

n-channel MOS transistor, 32 n-tub CMOS process, 158 n-type silicon, 3 n-well CMOS process, 158, 186 NAND logic D-type flip-flop , 228 nano-imprint lithography, 125 narrow-channel effect, 69, 70 NBTI, 568 Negative Bias Temperature Instability, 568 netlist, 366, 383, 399 next-generation lithography, 125 NGL, 125 NIL, 125 nitride ROM, 345 nMOS rv inverter, 186 rv process, 153 rv transistor, 4, 200 rv transistor gain factor, 207 rv transistor threshold voltage, 200 nMOS-mostly, 228 rv circuit , 186 nMOSt , 4 noise rv immunity, 236 rv margin, 187, 218 non-overlapping , 227 non-overlapping clocks, 231 non-rechargeable batteries, 448 non-recurring engineering costs, 402 non-saturated enhancement load, 190 non-volatile rv RAM, 345

OAI, 112 OBIC , 673 OBIRCH , 672 OCV, 558 off-axis illumination, 112 on-chip variation, 558 one-time-programmable rv EPROM, 336 rv memory, 335 ONO,313 rv gate dielectric, 345 OPC , 117 optical proximity correction, 117 optical- beam rv induced current , 673 rv induced resistive change, 672

OR-function, 197 OR-matrix, 411 OTP, 335 rv EPROM, 336 OUM, 348 output rv buffer, 238 rv conductance, 31 rv enable, 297 rv impedance, 26 rv protection, 100 overlay problem , 317 Ovonic Unified Memory, 348 oxidation, 129, 134 oxide spacer , 565 722

oxide-nitride-oxide, 313

PICA, 665 picosecond imaging circuit analysis, 665 pinch-off '"'" point, 22 '"'" region, 65 pinhole , 651 pipelining, 465 PLA, 410, 412 place and route, 438 placement and routing, 414, 438 planar '"'" DRAM cell, 312 '"'" IC technology, 35 '"'" silicon technology, 4 planarisation, 146 plasma, 139 '"'" etching, 132 platform ASIC, 436 PLD , 371, 420 PLL, 523 pMOS transistor, 200 '"'" gain factor, 208 '"'" threshold voltage, 200 pocket implants, 68 point defects , 96 Poisson's law, 12 poly fuse, 328 POLY mask , 154 polycide process, 166 polycrystalline silicon, 94 '"'" layer, 4 polygon pusher, 406 polymide layer, 328 polysilicon, 94 '"'" gate, 154 '"'" interconnect, 154 PoP, 644 positive photoresist, 129

p-channel MOS transistor, 32 p-type substrate, 4 package-on-a-package , 644 packaging, 623 page, 321, 339 PAL, 412 parallel '"'" connection of transistors, 197, 220 '"'" multiplier, 381 parallelism, 465 parametric '"'" fault, 600 '"'" yield loss, 614 parasitic '"'" MOS transistor, 34 '"'" capacitances, 100 '"'" thyristor, 277 partial product, 381 pass transistor, 222 pass-gate logic, 477 pass-transistor logic, 223, 477 passivation layer, 155 path delay, 597 PCM , 348, 619 PD-SOI, 102 PECVD, 139 PEM, 662 penetration depth, 143 periodic system of elements, 8 Perovskite crystals, 347 Phase-Change Memory, 348 phase-locked loop, 523 Phase-Shift Mask, 113 photolithography, 105 photon emission microscopy, 662 photoresist layer, 129 physical design aspects, 687 723

proximity effects , 550 pseudo-nMOS '" circuit, 207, 221 '" logic, 464 pseudo-static RAM , 291 PSM , 113 punch-through, 165, 560 PVT , 72

positively-charged ion, 7 potential first silicon problem, 648 power '" binning, 474 '" dissipation, 209, 235 '" integrity, 539 '" reduction techniques, 452, 457, 462 '" switch, 456 '" transistor, 270 power MOSFET, 261, 270 '" applications, 274 '" transistor, 270 power-delay product , 32, 460 power-down mode , 497 power-grid integrity, 539 ppm, 592 PRAM , 348 pre-deposition, 143 primary battery cells, 448 probe card, 649 probing, 659 process '" control module, 619 '" cross-section, 251 product term, 410 production tests, 591 programmable '" array logic, 412 '" logic array, 410 '" logic device, 371 '" read-only memory, 334 Programmable Logic Devices, 420 PROM , 334 propagation '" delay, 529, 532, 691, 693 '" time, 522 protection circuit, 237 prototyping, 418

R-load SRAM cell, 301 race, 227 radiation hardness, 345 RAM , 290, 294 Rambus DRAM, 321 Rambus TM , 325 random '" access, 292 '" variations, 551 '" yield loss, 614 random-access memory, 290, 294 ratioed logic, 189 ReAT,311 RDRAM , 321, 325 reactive ion etching, 133 Read-Only Memory, 329 read-only memory, 290 recessed source /drain, 170 recessed-channel array transistor, 311 rechargeable batteries, 449 recombination, 39 '" time , 60 reconfigurable computing, 706 reduced voltage swing, 471 redundancy, 328 refresh '" amplifier , 311 '" operation, 311 regist er-transfer language, 380, 391 reliability 724

st ress conditions, 646 rv tests, 592 repeat ers, 693 replicator circuit , 473 resistance, 533 resistive rv RAM , 349 rv load , 195 resistive-interconnect localisation, 673 Resolution Enhancement Techniques, 110 RET, 110 reticle, 106 retrograde profile, 144 retrograde-well, 164 reuse, 372, 391, 418, 523, 688 reverse short-cha nnel effect, 68 reverse-bias junction leakage, 81 RIE,133 RIL , 673 road ma p, 687 ROM, 290, 329 rv layout , 408 rv logic function, 408 rout ing channel, 415 row decoder , 296 row refresh , 311 RRAM , 349 RSCE ,68 RTL , 372, 380, 391 rv description, 380

velocity, 62 scaling rv effects , 687 rv limit ations, 702 rv properties, 165 scan rv chain, 598 rv test , 415, 418, 598 scan-a nd-repeat operation, 108 scannabl e flip-flop, 598 scanning rv electro n-bea m microscopy, 674 rv optical beam , 669 rv opt ical-beam, 654 SCCD, 262 scheduling, 391 scratch-protect ion layer , 155, 647 SDL, 673 SDRAM , 321, 322 sea-of-gates, 416 sea-of-t rans istors , 417 secondary rv battery cells, 449 rv electrons, 674 Seebeck effect imaging (SEI) , 672 SEL, 546 self-aligned rv drain, 94, 154 rv salicide, 166 rv source, 94, 154 rv source/ drain implant ation, 159 self-discharge rate, 450 self-heating, 103 self-indu ctance, 536 self-test, 415 self-timed circuits , 491 SEM, 674

rv

rv

sacrificial pad oxide, 153 SACVD, 139 salicide, 166 saturated enhancement load , 189 saturation rv current , 22 rv region, 19, 22 725

silicon

semi-custom IC, 372 semiconductor rv doping , 8 rv material , vi sense amplifier, 296, 311 separation by implant ation of oxygen, 100 serial rv ROM , 334 rv memory, 290, 293 series connect ion of transistors , 197, 220 set-up time violation, 519 SED , 544 SGRAM, 325 shadow RAM , 334, 345 Shallow-Trench Isolation, 135, 160 sheet resistance, 154, 195 shift regist er , 230 shift-and-add operation, 381 Shmoo plot, 655 short -channel effect, 66 short -circuit rv current , 209, 239 rv free output buffer , 239 rv power consumpt ion, 451 rv power dissipati on, 210 SIA,687 sign-magnit ude not ation, 485 signal rv integrity, 527 rv processor, 374 rv propagation , 691, 693 Signal Integrity Self-Test , 549 signature , 649 SIL, 667 silicidation, 146 silicide, 251 silicides, 166

atom, 5 rv cryst al, 6 rv dioxide, 2 silicon-insulator-silicon, 315 silicon-on-insulator , 99 silicon-on-sapphire, 100 SIMOX, 100 simulat ion, 392 simultaneously switching outputs, 542 single event latch-up , 546 single event upset , 544 single-edge tri ggered, 496 single-phase, 236 rv clocking, 515 single-port memory, 327 Si02, 2 SIP, 642 SiP, 403 SIS, 315 SIST , 549 six-t ransistor SRAM cell, 300 slack bor rowing, 522 sleep mode, 497 SLI, 420 slurry, 148 SMD, 639 SMIF rv environment , 612 rv pod , 612 SNM, 303 SoC, 350, 365,389,403,642,687 rv design platform, 367 soft rv core, 370 rv defect localisation, 673 rv error, 328, 544 SaG, 146 rv

726

"-' "-' static "-' "-' "-'

SOl , 99 SOl-CMOS, 99 solid immersion lens, 667 SOM, 654, 669 SONOS, 344 SoP, 644 SOS-CMOS process, 100 source, 4 "-' series resistance, 566 source-synchronous t iming, 523 source / drain capacitance, 100 spacer, 565 "-' lithography, 122 specification, 579, 653 speed and area, 235 Spin-On-Glass, 146 spurious transitions, 494 sputter et ching, 132 SRAF,117 SRAM , 291, 294 "-' memory cell, 300 SRB, 169 SRP L, 479 SSO, 542 SSTA, 393 STA, 393, 558 stacked capacitance cell, 313 stand-alone memory, 290 standa rd "-' IC , 402 "-' cell, 413 "-' commodit ies, 372 "-' logic IC , 372 "-' product , 372 standa rd-cell, 413 "-' height , 477 "-' layout , 413, 414 "-' library, 413 standby

current , 76, 455 mode, 346, 453

CMOS circuits, 219 CMOS flip-flop, 226 CMOS invert er characterist ic, 206 "-' RAM , 291, 294 "-' RAM cells, 300 "-' column access, 319 "-' memory, 291 "-' noise margin, 303 "-' power consumpt ion, 451 "-' timing ana lysis, 393 "-' I R -drop , 536 St ati c Timing Analysis, 558 st atist ical static timing anal ysis, 393 St atistical Timing Analysis, 558 STC, 313 st eady-state current, 600 ste p coverage, 141 st ep-and-repeat operation, 108 ST I, 135, 160 "-' stress, 550, 555 st ick diagram , 245 sto rage gate, 262, 263 strain-r elaxed buffer , 169 st ra ined silicon, 169 strong inversion, 16 structural "-' faul t , 600 "-' tes t, 597 st ruc tured ASIC, 436 st uck-at fault , 600 subresolution assist feature, 117 subst rate, 95 "-' boun ce, 539 "-' dope, 5

727

subthreshold rv behaviour, 75, 77 rv current, 77, 453 rv leakage current , 76, 452, 689 rv logic, 218 rv region, 76 rv slope , 76, 103, 601 subthreshold logic, 474 super-fluid NA, 121 supply bounce , 536 surface rv scattering, 60 r-;» states, 264 surface-channel CCD , 262 surface-mount device, 639 Swing Restored Pass-Transistor Logic, 479 switching activity, 482, 535 symbolic layout , 440 synchronous rv CMOS circuits, 225 rv DRAMs, 321, 322 Synchronous Graphics RAM, 325 synthesis, 392 rv tools, 390 system rv design aspects, 687 rv in a package, 403 rv level, 374, 376 rv on a chip, 365, 403 rv on chip, 389, 391 rv on silicon, 391 system-in-a-package, 403, 642 system-on-a-chip, 403, 642 system-on-a-package, 644 systematic yield loss, 614 systems on silicon, 420

D-product , 32 temperature rv expansion coefficient, 647 rv sensitivity, 646 rv variation cycle, 647 temperature-cycle test , 647 tensile strain, 170 TEaS, 139 test vectors, 649 thermal rv behaviour, 635 rv energy , 7 rv generation, 39 rv oxide, 134 thermally-induced voltage alteration, 672 thick oxide, 134, 153 three-beam imaging, 109 three-dimensional DRAM cell, 312 threshold rv adjustment implantation, 5 rv loss, 190, 222 threshold voltage, 16, 29, 201, 652 rv adjustment implantation, 153 rv loss, 222 rv roll-off, 67 rv temperature dependence, 72 tie-off cell, 537 tiles , 150 time stealing, 522 Time- Resolved Photo Emission, 654 time-resolved photon-emission microscopy, 665 timing

T

tapering factor, 214 728

ultra-low power appli cation, 474 uncommitted array, 417 under-etch , 132, 610 usabl e gates, 372 user-sp ecific integrated circuit, 366 USIC, 366 Utilisation factor, 372

"" margins, 521 "" problems, 514 "" verification, 610 "" violations, 519 titanium nitride, 166 TIVA, 672 top-down design pro cess, 374 transconductance, 3, 31 transfer "" efficiency, 264 "" gate, 262, 263 transistor "" level, 384 "" lifetime, 136 "" matching , 554, 690 "" scaling effects, 689 transistor gain factor, 26, 199 "" temp erature dependence, 71 transition "" delay fault , 598 "" region, 21 transmission gate, 222, 225 transparency, 227, 231 trench capacit ance cell, 313 tri-s tate buffer , 239 triode region , 19 triple-well "" concept , 689 "" device, 453 "" technology, 453, 541 TTL "" compatible, 237 "" input buffer, 237 TTL-CMOS input buffer , 237 tunnelling, 137 turn-around tim e, 333, 369, 418 two's complement notation, 485 two-beam imaging , 109

valence "" band , 6 "" elect ron, 6 variability-aware design, 700 VCO , 524 VDMOS , 271 velocity saturation, 60 Verilog, 391 "" code, 391 vertical "" doubl e-diffused MOS, 271 "" elect ric field, 59 "" pillar transistors, 316 very low voltag e test , 602 VHDL, 391 "" code, 391 video "" RAM , 293 "" memories, 293 Video RAM , 324 virtual "" component, 369 "" drain, 22, 64 virtually static RAM , 291 VLV t est , 602 voids, 560 volatile memory, 290 voltage "" drop , 536 "" peaks, 238 "" regulator, 470 voltage-controlled oscillator, 524 729

VPT, 316 VRAM , 293, 324

rv rv rv

wafer, 95 rv diam et er , 610 rv map , 618 rv probing, 610 wafer-level packaging, 624 Wallace tree multipli er , 382, 495 waveform measur ements, 610 wearout , 646 well biasing , 456 well-bias , 455 well-proximity, 555 rv effect , 550 wet-et ching method, 132 wire rv bonding, 629 rv self-heat ing, 562 rv spreading, 621 WLP, 624 word line, 296 work funct ion, 16 worst-case rv corne r, 305 rv delay path, 374, 388 write enable, 297

rv

rv

dust particles, 611 electrostatic charge, 614 humid ity, 610 temperature fluctuations, 610 vibrations, 611

Z-RAM, 326 Zero Capacitor DRAM , 326 zero-ternperature-coefficient , 72 ZTC, 72

x-decoder , 296 X-ray lithography, 125 XDR RDRAM , 326 XIVA, 672 XRL , 125 y-decoder, 296 yellow room , 611 yield , 610 yield cont rol, 619 yield degradation rv UV light , 611 rv chemical impurities, 614 730