Nanodevices for Integrated Circuit Design 9781394185788

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Nanodevices for Integrated Circuit Design

Scrivener Publishing 100 Cummings Center, Suite 541J Beverly, MA 01915-6106 Publishers at Scrivener Martin Scrivener ([email protected]) Phillip Carmical ([email protected])

Nanodevices for Integrated Circuit Design

Edited by

Suman Lata Tripathi Abhishek Kumar K. Srinivasa Rao and

Prasantha R. Mudimela

This edition first published 2023 by John Wiley & Sons, Inc., 111 River Street, Hoboken, NJ 07030, USA and Scrivener Publishing LLC, 100 Cummings Center, Suite 541J, Beverly, MA 01915, USA © 2023 Scrivener Publishing LLC For more information about Scrivener publications please visit www.scrivenerpublishing.com. All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, electronic, mechanical, photocopying, recording, or otherwise, except as permitted by law. Advice on how to obtain permission to reuse material from this title is available at http://www.wiley.com/go/permissions. Wiley Global Headquarters 111 River Street, Hoboken, NJ 07030, USA For details of our global editorial offices, customer services, and more information about Wiley products visit us at www.wiley.com. Limit of Liability/Disclaimer of Warranty While the publisher and authors have used their best efforts in preparing this work, they make no rep­ resentations or warranties with respect to the accuracy or completeness of the contents of this work and specifically disclaim all warranties, including without limitation any implied warranties of merchant-­ ability or fitness for a particular purpose. No warranty may be created or extended by sales representa­ tives, written sales materials, or promotional statements for this work. The fact that an organization, website, or product is referred to in this work as a citation and/or potential source of further informa­ tion does not mean that the publisher and authors endorse the information or services the organiza­ tion, website, or product may provide or recommendations it may make. This work is sold with the understanding that the publisher is not engaged in rendering professional services. The advice and strategies contained herein may not be suitable for your situation. You should consult with a specialist where appropriate. Neither the publisher nor authors shall be liable for any loss of profit or any other commercial damages, including but not limited to special, incidental, consequential, or other damages. Further, readers should be aware that websites listed in this work may have changed or disappeared between when this work was written and when it is read. Library of Congress Cataloging-in-Publication Data ISBN 9781394185788 Cover image: Nanotechnology, Yuriy Nedopekin | Dreamstime.com Cover design by Kris Hackerott Set in size of 11pt and Minion Pro by Manila Typesetting Company, Makati, Philippines Printed in the USA 10 9 8 7 6 5 4 3 2 1

Contents List of Contributors

xiii

Preface xvii Acknowledgements xix 1 Growth of Nano-Wire Field Effect Transistor in 21st Century 1 Kunal Sinha 1.1 Introduction 2 1.2 Initial Works on Nanowire Field-Effect-Transistors (NW-FET) 3 1.2(A) Theoretical and Simulation Studies on Nanowire FET (NW-FET) 4 1.2(B) Fabrication of Nanowire Field-Effect-Transistor (NW-FET) 10 1.3 Application of Nanowire Field-Effect-Transistors (NW-FET) 15 1.4 Conclusion 17 References 18 2 Impact of Silicon Nanowire-Based Transistor in IC Design Perspective 23 G. Boopathi Raja 2.1 Introduction 24 2.2 Nanoscale Devices 25 2.2.1 Carbon Nanostructures 25 2.2.2 Nanoelectromechanical Systems 27 2.2.3 Graphene-Based Transistors 28 2.2.4 Silicon Nanowire Based Devices 29 2.3 Nanowire Heterostructures and Silicon Nanowires 29 2.3.1 Characteristics of SiNWs 31 2.3.2 Fabrication 33 2.3.3 Applications of SiNWs 35 2.4 Performance Analysis of Si Nanowire with SOI FET 38 2.5 Conclusion 40 References 40 v

vi  Contents 3 Kink Effect in Field Effect Transistors: Different Models and Techniques 43 Abdelaali Fargi, Sami Ghedira and Adel Kalboussi 3.1 Introduction 44 3.2 Techniques of Kink Effect 45 3.2.1 Current-Voltage Technique 45 3.2.2 Pulsed I-V Technique 46 3.2.3 Capacitance-Voltage Technique 47 3.3 Different Models of Kink Effect 48 3.4 Kink Effect in MOS Capacitors 48 3.4.1 Incomplete Ionization Model 49 3.4.2 Simulation of the Kink Effect in MOS Capacitor 51 3.4.2.1 Effect of the Variation of Activation Energy 53 3.4.2.2 Effect of the Variation of Traps Density 54 3.4.2.3 Effect of the Variation of Capture Cross Section 55 3.4.3 Comparison Between Experimental and Simulation Results 55 3.4.3.1 Hysteresis Effect on the C-V Characteristics 55 3.4.3.2 Proof of the Origin of Kink Effect 57 3.5 Conclusion 58 References 58 4 Next Generation Molybdenum Disulfide FET: Its Properties, Evaluation, and Its Applications Vydha Pradeep Kumar and Deepak Kumar Panda 4.1 Introduction of Two-Dimensional Materials 4.2 Evaluation of 2D-Materials 4.3 Overview of MoS2 4.3.1 Why MoS2 4.3.2 MoS2 Structured Design 4.4 Properties of MoS2 4.4.1 Bulk Characteristics 4.4.2 Electrical and Optical Characteristics 4.4.2.1 BandGap 4.4.2.2 Photoluminescence Spectra 4.4.2.3 Injection of Electrons 4.4.2.4 Transistor 4.4.3 Mechanical Properties 4.4.3.1 Valleytronics

61 62 64 66 66 67 68 68 68 68 69 69 69 69 69

Contents  vii 4.4.3.2 Optical Transitions 4.4.3.3 Spin-Orbit Valence Band 4.5 Fabrication of MoS2 4.5.1 Mechanical Exfoliation 4.5.2 Intercalation 4.5.3 Solvent Exfoliation 4.5.4 Chemical Vapor Deposition (CVD) 4.6 Applications of MoS2 4.6.1 Solid Lubricants 4.6.2 Electronic Applications 4.6.3 Field-Effect Transistor 4.6.4 Switching Transistor 4.6.5 Nano-Structures 4.6.6 Biosensors 4.6.7 FET-Based Biosensors 4.7 Comparison of Other 2D Materials with MoS2 4.8 Conclusion References 5 Impact of Working Temperature on the ION/IOFF Ratio of a Hetero Step-Shaped Gate TFET With Improved Ambipolar Conduction Bijoy Goswami, Savio Jay Sengupta, Ankur Jyoti Sarmah and Nalin Behari Dev Choudhury 5.1 Introduction 5.2 Device Structure 5.3 Results and Discussion 5.4 Conclusion References

70 70 71 71 71 72 72 72 72 72 73 73 73 73 74 75 80 81

83 84 84 86 89 90

6 Analysis of RF with DC and Linearity Parameter and Study of Noise Characteristics of Gate-All-Around Junctionless FET (GAA-JLFET) and Its Applications 93 Pratikhya Raut, Umakanta Nanda and Deepak Kumar Panda 6.1 Introduction 94 6.2 Structure of GAA-JLFET 97 6.3 Results and Discussion 98 6.3.1 DC Analysis 99 6.3.2 RF Analysis 101 6.3.3 Linearity Analysis 103 6.3.4 Noise Analysis 106

viii  Contents 6.3.4.1 Thermal Noise 6.3.4.2 Flicker Noise 6.3.4.3 Gate-Induced Thermal Noise 6.4 Applications 6.5 Conclusion References

107 107 108 112 112 112

7 E-Mode-Operated Advanced III-V Heterostructure Quantum Well Devices for Analog/RF and High-Power Switching Applications 117 A. Mohanbabu, N. Vinodhkumar, S. Maheswari, S. Baskaran, V. Janakiraman, M. Saravanan and P. Murugapandiyan 7.1 Silicon Era and Scaling Limit 118 7.2 III-V GaN-Based Compound Semiconductors 119 7.3 Band-Gap Engineering 119 7.4 Quantum Well 120 7.5 Polarization in GaN Devices and their Specific Properties 121 7.6 Strain and Lattice Mismatch in III-N Semiconductors 123 7.7 High Electron Mobility Transistors (HEMTs) 123 7.8 Two-Dimensional Electron Gas (2DEG) 124 7.9 AlGaN/GaN Heterostructure HEMT 125 7.9.1 Scope of the III-V Heterostructure Quantum Well Device 126 7.9.2 Problem Statement 127 7.9.3 Motivation for the Present III-V Heterostructure Quantum Well Device 127 7.10 Enhancement Mode GaN DH-HEMTs Device With Boron-Doped Gate Cap Layer 129 7.10.1 Device Architecture 130 7.11 High-K Gate Dielectric III-Nitride GaN MIS-HEMT Devices 132 7.11.1 Device Architecture 134 7.11.2 Boost Converter Circuit Application 136 7.12 Conclusion 137 References 138

Contents  ix 8 Design of FinFET as Biosensor 143 Suman Lata Tripathi and Balwinder Raj 8.1 Introduction 143 8.2 Existing FET Based Biosensors 145 8.2.1 TGRC-MOSFET as a Biosensor 145 8.2.2 An N-Type Nanogap Embedded Polarity Biased Based DM- EDTFET Biosensor 146 8.2.3 Cavity on Source Charge Plasma TFET-Based Biosensor 147 8.2.4 Dielectric Modulated Double Gate Junctionless MOSFET Biosensor 148 8.2.5 A Double Gate Dielectric Modulated Junctionless Tunnel Field-Effect Transistor as a Biosensor 148 8.3 Performance Parameters of Biosensors 149 8.4 FinFET Designed as Biosensor Using Visual TCAD 149 8.5 Biosensors in Disease Detection 152 8.6 Conclusion 153 8.7 Acknowledgement 154 References 154 9 Biodegradable and Flexible Electronics: Types and Applications 157 Vrinda Gupta, Sachin Himalyan and Archit Sundriyal 9.1 Introduction 158 9.2 Biodegradable and Flexible Electronics 160 9.3 Types of Materials Used for Biodegradable and Flexible Electronics 164 9.3.1 Materials for Biodegradable Electronics 164 9.3.2 Materials for Flexible Electronics 167 9.4 Applications of Biodegradable and Flexible Electronic Devices 171 9.4.1 Sensing and Diagnosis 172 9.4.2 Energy Storage 173 9.4.3 Smart Textiles 173 9.4.3.1 Chameleonic Textiles 174 9.4.3.2 Intelligent Textile Sutures 174 9.4.3.3 Textile-Based Flexible and Printable Material 174 9.4.4 Wearable Electronics 175 9.5 Conclusion 176 References 177

x  Contents 10 Novel Parameters Extraction Method of High-Speed PIN Diode for Power Integrated Circuit 181 Sami Ghedira and Abdelaali Fargi 10.1 Introduction 182 10.2 Review of the Technology and Physics of Power PIN Diodes 183 10.2.1 Technological Aspect 183 10.2.2 Physical Aspect 184 10.3 State of the Art of PIN Diode Parameters Extraction 186 10.4 Proposed Method 188 10.4.1 Principle 188 10.4.2 Doping Profile Parameters Identification 188 10.4.2.1 Experimental Method 188 10.4.2.2 Model Description 189 10.4.2.3 Parameters Extraction Procedure 198 10.4.3 Ambipolar Lifetime Estimation 201 10.4.3.1 Experimental Method 201 10.4.3.2 Numerical Analysis of OCVD Method 202 10.4.3.3 Parameters Extraction Procedure 205 10.5 Validation 205 10.6 Conclusion 207 References 208 11 Edge AI – A Promising Technology Remya R., Nalesh S. and Kala S. 11.1 Introduction 11.2 Deep Neural Networks 11.2.1 Multi-Layer Perceptrons (MLP) 11.2.2 Convolutional Neural Networks (CNNs) 11.2.3 Recurrent Neural Networks (RNNs) 11.3 Model Compression Techniques for Deep Learning 11.3.1 Pruning 11.3.2 Quantization 11.3.3 Low Rank Factorization 11.3.4 Knowledge Distillation 11.4 Computing Infrastructures 11.4.1 GPU Accelerator 11.4.2 FPGA Accelerator 11.5 Conclusion References

211 211 213 214 214 215 216 216 217 219 221 221 221 222 223 224

Contents  xi 12 Tunable Frequency Oscillator Abhishek Kumar 12.1 Introduction 12.2 Experimental Methods and Materials 12.2.1 Varactor Diode 12.2.2 Active Inductor 12.3 Results and Discussion 12.4 Conclusion References 13 Introduction to Nanomagnetic Materials for Electronic Devices: Fundamental, Synthesis, Classification and Applications Shivani Malhotra, Mansi Chitkara, Lipika Gupta and Monika Parmar 13.1 Introduction – An Explanation of the Process and Approach 13.2 Nanomaterials 13.2.1 Surface to Volume Ratio 13.2.2 Quantum Confinement Effect 13.3 Synthesis and Characterization of Nano Materials 13.4 Characterization Technique for Structural Analysis 13.5 Magnetic Materials 13.6 Classification of Magnetic Materials 13.7 Magnetic Properties 13.8 Ferrites 13.8.1 Classification and Types of Ferrites 13.8.2 Spinel Ferrite 13.8.3 Garnet 13.8.4 Ortho Ferrite Structure 13.8.5 Magnetoplumbite Structure 13.8.6 Hexagonal Ferrites 13.8.7 Classification of Hexaferrite 13.9 Applications of Magnetic Materials 13.10 Conclusion References About the Editors

227 227 230 231 233 235 240 240

243

244 244 245 246 248 251 252 253 256 258 259 261 261 262 263 263 264 265 268 268 273

Index 275

List of Contributors Kunal Sinha Dept. of Electronics, Asutosh College, Kolkata, India G. Boopathi Raja Department of ECE, Velalar College of Engineering and Technology, Erode, India Abdelaali Fargi Laboratory of Microelectronics and Instrumentation, Department of Physics, University of Monastir, Monastir, Tunisia Sami Ghedira Laboratory of Microelectronics and Instrumentation, Department of Physics, University of Monastir, Monastir, Tunisia Adel Kalboussi Laboratory of Microelectronics and Instrumentation, Department of Physics, University of Monastir, Monastir, Tunisia Vydha Pradeep Kumar Dept. of Sense, VIT-AP University, Near Vijayawada, India Deepak Kumar Panda Department of ECE, Amrita School of Engineering Amaravati, Amrita Vishwa Vidyapeetham, Andhra Pradesh, India Bijoy Goswami Dept. of ETE, Assam Eng. College, Assam, India Savio Jay Sengupta Dept. of ETE, Jadavpur University, West-Bengal, India xiii

xiv  List of Contributors Ankur Jyoti Sarmah Dept. of ETE, Assam Eng. College, Assam, India Nalin Behari Dev Choudhury Dept. of EE, National Institute of Tech., Assam, India Pratikhya Raut ECE Department, VR Siddhartha Engineering College, Kanuru, Vijayawada, Andhra Pradesh, India Umakanta Nanda School of Electronics, VIT-AP University, Near Vijayawada, India A. Mohanbabu Department of Electronics and Communication Engineering, SRM Institute of Science and Technology, Ramapuram, Chennai, India N. Vinodhkumar Department of Electronics and Communication Engineering, Vel Tech Rangarajan, Dr. Sagunthala R&D Institute of Science and Technology, Chennai, India S. Maheswari Department of Electronics and Communication Engineering, Panimalar Engineering College, Chennai, India S. Baskaran Department of Electronics and Communication Engineering, SKP Engineering College, Tiruvannamalai, Chennai, India V. Janakiraman Department of Electronics and Communication Engineering, Dhanalakshmi Srinivasan College of Engineering and Technology, Chennai, India M. Saravanan Sri Eshwar College of Engineering, Coimbatore, Tamil Nadu, India P. Murugapandiyan Anil Neerukonda Institute of Technology & Sciences, Visakhapatnam, Andhra Pradesh, India

List of Contributors   xv Suman Lata Tripathi VLSI Design Lab, School of Electronics and Electrical Engineering, Lovely Professional University, Phagwara, India Balwinder Raj Department of Electronics and Communication Engineering, NIT, Jalandhar, India Vrinda Gupta Dept. of Electronics & Communication Engineering, NIT Kurukshetra, Kurukshetra, India Sachin Himalyan School of VLSI Design and Embedded Systems, NIT Kurukshetra, Kurukshetra, India Archit Sundriyal School of VLSI Design and Embedded Systems, NIT Kurukshetra, India Remya R. Department of ECE, Indian Institute of Information Technology Kottayam, Kerala, India Nalesh S. Department of Electronics, Cochin University of Science and Technology, Kerala, India Kala S. Department of ECE, Indian Institute of Information Technology Kottayam, Kerala, India Abhishek Kumar School of Electronics and Electrical Engineering, Lovely Professional University, Phagwara, Punjab, India

Preface Increasing demand for smart and intelligent devices with better sensing and processing is the one of the main challenges for future device and circuit design. The primary requirement of data-driven decision devices is to have smaller sizes and lower power consumption. Research is being carried out to find suitable materials, to replace and build upon silicone. The most promising replacement for lithographic-based integrated circuits appears to be nano-electronics or circuits constructed with components as small as 10 nanometers. In the past two decades, nanotechnology has emerged as an most important and fascinating area in a variety of science and technology disciplines. Device modeling, fabrication and circuit development with emerging nanodevices like NanoWire, Quantum Well, and CarbonNanoTube are discussed in this book. Beginning with semiconductor devices and continuing through VLSI fabrication, modeling of (analog and digital), and upcoming non-silicon/nanodevices, a wide range of applications, such as high-speed and high-power electronics, as well as the necessity for energy conservation today, interest in the field of nitride-based devices, has grown recently. The emphasis on flexible electronic technology research has increased with the increasing demand for wearable and printable electronic technology. This book offers extensive analysis and demonstration of nanomaterials, wearable electronics, and circuit simulation.

xvii

Acknowledgements The authors would like to thank Department of VLSI Design, Lovely Professional University, Phagwara, India, Department of ECE, NIT Jalandhar and DST SERB (TAR/2022/000325) for provizing necessary facilities required for completing this book. The authors would also like to thank the researchers from different organizations like IIT, NIT, India and international universities etc. who are contributing their book chapters in this book.

xix

1 Growth of Nano-Wire Field Effect Transistor in 21st Century Kunal Sinha

*

Dept. of Electronics, Asutosh College, Kolkata, India

Abstract

The Nanowire Field-Effect-Transistor (NW-FET) is one of the leading transistor architectures which are under the observation of the research community for the future technology node, predicted by the International Technology Roadmap for Semiconductors (ITRS). With the gradual reduction of transistor dimensions following Moore’s law, the existing transistors like FinFET, Tri-Gate MOSFET, etc. are already under pressure to maintain the short channel effects (SCEs) of the transistor within control, and also provide improved performance. With 7/10 nm technology node transistors already under production in several applications, researchers are exploring nanowire structures for future technology node architectures. The initial results from theoretical and simulation studies motivated the researchers to fabricate the NW-FET device, and the fabricated device is also showing impressive output thus researchers are also exploring the feasibility of this device for other possible cutting-edge applications. In this chapter, various theoretical, simulation results from published reports are going to be discussed. Later on, the output results from the fabricated NW-FET device and how this structure can be utilized in future applications will be briefed with appropriate references. In short, this chapter will brief how the research work on NW-FET devices has grown in the 21st century. Keywords:  Nanowire (NW), field effect transistor (FET), MOSFET, FinFET, NW-FET, sensor

Email: [email protected]

*

Suman Lata Tripathi, Abhishek Kumar, K. Srinivasa Rao, and Prasantha R. Mudimela (eds.) Nanodevices for Integrated Circuit Design, (1–22) © 2023 Scrivener Publishing LLC

1

2  Nanodevices for Integrated Circuit Design

1.1 Introduction The rapid development in the field of Nanoscience and Nanotechnology in the last few decades led the research community to evolve the transistor device from conventional Metal-Oxide-Semiconductor-FieldEffect-Transistor (MOSFET) structures to various 3-dimensional (3D) devices like Fin-FET, Gate-All-Around FET (GAA), and Nano-wire FET (NW-FET). The reason for such evolution of transistor structure is due to the rapid demand for a smaller dimensional transistor with improved performance. The rate of reduction of transistor size is achieved by following the famous Moore’s Law, where Gordon Moore predicted that “The number of Transistors in an Integrated Circuit (IC) will double every 18 months” [1]. In the last few decades, by continuous downscaling of transistor dimensions and supply voltage, the continuous demand for higher packing density with low cost per function has been achieved. The increase of packing density in an IC also results in higher circuit speed and lower power dissipation. This inspires the researchers to sustain the growth of the semiconductor industry by reducing the transistor dimension and accordingly the supply voltage. However, as the dimensions start approaching the nano-scale domain ( 0 V: n-type conduction

CB

EF source h

EF VB

e EF

CB

EF drain

drain source VB

Figure 1.2  Schematic diagram of ambipolar transport in n-NWFET (a) strong p-type conduction for Vgs < 0V (b) p-type conduction for Vgs = 0V, (c) n-type conduction for Vgs > 0V, as reported in [35].

takes place for Vgs ≤ 0V and n-type conduction is observed for Vgs> 0V. This is an interesting observation of quantum confinement in the channel region of a transistor, which can be reduced by adjusting the input bias voltage. The effect of channel impurity on the performance of an NW-FET is an interesting field of study. Sano et al. studied and modeled the physics associated with the localized impurities and how to treat coulomb potential consistently when using the drift-diffusion model of simulation [36]. The authors further extended their theoretical work for nanostructured devices where the effects of different material interfaces are taken into account. In another work, Lee et al. modeled the inelastic interaction between the carriers in quantized NW-FET to reduce the computational time of these quantized architectures [37]. The conventional NEGF formulation used to take a significant amount of time to simulate 3D quantized semiconductor devices, however, in this article, the authors demonstrated an alternate approach where the Lowest Order Approximation (LOA) is combined with Pade approximation to proficiently model the scattering phenomenon in NW channel of a FET. The model is included in 3D atomistic quantum transport simulation and the effects of phonon–phonon

Growth of NW-FETs in 21st Century  9 and electron-phonon scattering in NW-FET structure is studied carefully. A significant reduction in computational time has been observed with the accurate result, and these observations are reported in detail in [37]. Though there is a shortcoming of this approach, which is determining the scaling factor to investigate the higher order perturbation terms for both scattering mechanisms, however, the model will be very helpful for deep quantum well structures. Also, the authors claim that their model is capable of providing more efficient results in devices where 2D materials are used and a highly expensive ab-initio level of accuracy is required. The approach is capable of simulating the NEGF framework based quantum transport phenomenon, without the help of heavy computational resources. The electro-thermal phenomenon in a Si NW-FET device structure is modeled by Martinez and Barker [38] where the authors coupled some classical and quantum methodologies with NEGF formalism. This blended methodology is used to model the application of a gate-all-around nanowire transistor. To carry out the electro-thermal simulation of an NW-FET, the electron transport phenomenon is modeled with the help of nonequilibrium green function formalism, and electron-phonon scattering is included within the self-consistent Born approximation. The lattice heating is modeled with the help of Fourier law and used as a hot electron to the phonons. The model shows that the on-state drive current is reduced to 30% when only a hot phonon source is considered and the same drive current is reduced to 70% when Joule law is used alone. Another interesting observation is reported by the authors that a slight cooling effect occurred at an intermediate gate bias voltage and this effect depends on the electron-photon scattering and source length. Therefore, by optimizing the gate bias and source length, the model can be used for cooling the device. Figure 1.3 shows the temperature variation profile through the NW channel, as reported. Another interesting observation the researchers reported is that at high gate bias conditions, the electron flow is unperturbed by the phonon absorption as the source-drain barrier height is small. The dissipation of heat energy from high-energy electron occurs near the drain end and as a result the overall temperature of the NW channel region increases. However, as the temperature of the system increases more, the electron-­ phonon scattering phenomenon starts to build up, and the overall drain current starts to degrade. For large devices, the authors considered only Joule’s power as the only source of heat and found that it produces a large generation of lattice heat and as a consequence, a large decrease in drive current is observed. The model presented in this paper is found very

Temperature (K)

10  Nanodevices for Integrated Circuit Design

300 299.5 299 298.5 5

5 50 y(nm)

x(nm)

0 0

0.2

0.2

0.0

0.0

energy (eV)

energy (eV)

Figure 1.3  Temperature profile through the channel of the device under study. It indicates a cooling effect towards the source and the generation of heat is more towards the drain (as reported in [38]).

–0.2 –0.4

–0.2 –0.4

–0.6 0

10

20

30 x (nm)

40

50

–0.6 0

10

20

(a)

30 x (nm)

40

50

(b)

Figure 1.4  LDOS for a Si NW-FET device potential profile: (a) classical methods (b) quantum result (as reported in [38]).

effective in predicting the amount of heat generation in nano-scale devices like NW-FET and the results are validated with the results obtained from more sophisticated and highly computationally intensive methodologies. The following Figure 1.4 is reported by the authors to show that the new method produces a similar result that the classical methods show.

1.2(B) Fabrication of Nanowire FieldEffect-Transistor (NW-FET) With the discoveries of several advantages of NW-FET through various theoretical and simulation studies by several researchers, scientists of leading semiconductor industries and research laboratories are working hard to fabricate the cutting-edge nanowire structure and implement the

Growth of NW-FETs in 21st Century  11 advantages as reported in leading journals and conferences. Scientists at Harvard University fabricated a Si NW-FET device in early 2000 and reported their observation in [39]. The device structure as fabricated by the authors is shown in Figure 1.5. The fabricated device shows significant improvement in device parameters after source/drain contact thermal annealing and surface passivation. The average trans-conductance improvement is recorded from 45 to 800 nS and hole mobility enhanced from 30 to 560 cm2/V-s. Furthermore, a performance matrix comparison between the fabricated Si NW-FET and planner MOSFET shows that NW-FET has superior performance and the potential to be used in leading cutting-edge technologies. Another interesting study was performed by Xiang et al. [40], where a Ge-core-Si-shell NW channel is used in a High-K metal gate MOSFET architecture, and the device performance is compared with carbon nanotube FET (CNT-FET) device output. The comparative study shows that the drive current is more than three to four times, compared to the state-ofthe-art MOSFET drive current. The reason for such improvement is due to the high conductivity of the NW channel. When the channel conductivity is compared with strained channel material, it is found that the NW offers more than twice the hole mobility. The schematic and fabricated device structure of the work is shown in Figure 1.6. The researchers also demonstrated in their work that the NWFET device offers a lower ambipolar current, which is in contrast with contemporary CNTFET architecture. Thus, the device gives superior performance when compared with conventional High-K MOSFET, strain channel FET and CNTFET.

5 nm

Source

Drain Nanowire Oxide Gate

Figure 1.5  Schematic and fabricated device structure of Si NW-FET (as reported in [39]).

12  Nanodevices for Integrated Circuit Design (a)

(c) Nanowire

High-κ film

Contact Au gate

(b)

Si

Ge

Si

CB SiO2

EF VB Quantum well

(e)

(d)

Au

Ge

Si

ZrO2 SiO2

Figure 1.6  Schematic and fabricated device structure of Ge/Si Core/Shell high-K metal gate MOSFET architecture (as reported in [40]).

NWs can be prepared with different materials and can be used in mechanical, electrical, and medical applications. Figure 1.7 shows images of various NWs, fabricated and reported by various researchers [41, 42]. In [42], researchers developed Si and SiGe NW structures, using a vapor-liquid-solid growth technique, with a controlled doping profile. The purpose of the work was to investigate the impact of nano-scale size on controlled NW growth and develop high-performance NW devices. Further, the researchers also studied the feasibility to use NW transistors in solar cell devices, to increase efficiency. For that purpose, the aspect ratio of NW is varied and enhances light absorption. (a) 0.5 µm

4 µm

1 µm

1 µm

Figure 1.7  (i) SEM view of (a) GaN and (b) InP NW [41] (ii) Silicon nanowires synthesized by vapor-liquid-solid growth [42] (iii) Zinc oxide nanowire.

Growth of NW-FETs in 21st Century  13 A recent study compared the performance matrix of a fabricated Si n-type Gate-All-Around NW-FET (GAA NW-FET) and FinFET device structure for a wide range of temperatures (25 – 125 °C) [43]. The fabricated device structures, shown in Figure 1.8, are as reported by the authors. The study shows that the GAA NW-FET shows better performance in terms of better drive current and sub-threshold slope in the given temperature variation. Also, the authors reported that at weak inversion charge Ninv, effective electron mobility is limited by phonon scattering in both the architecture. However, for high Ninv, electron mobility is less affected by surface roughness scattering in GAA NW-FET compared to FinFET architecture. In another recent work, researchers have shown the fabrication of vertical GaN NW-FET architecture for different NW diameters (i.e. 220–640 nm) and different NW numbers (i.e. 1 – 100) [44]. The purpose of the work is to find the feasibility of mass fabrication of vertical NW-FET with different diameters and different numbers of NW. The fabricated device structure, as reported by the authors, is shown in Figure 1.9. Apart from the feasibility study, the work also shows the variation of different electrical parameters for different NW diameters and numbers, to quantify the impact of these variations on the device performance. It has been observed that the fabricated FET offers a threshold voltage of up to (6.6 ± 0.3) V. The drive current was also found to increase with the increase of NW numbers and diameters of each NW. Furthermore, the gate hysteresis effect is found to be almost zero with the help of proper dielectric passivation material deposition. These results are very promising for the massive production of GaN NW-FET with improved performance. In another work of GaN p-type vertical NW-FET, F. Yu et al. have shown that their fabricated device exhibits a very small amount of off-state leakage current that can be practically considered as normally off [45]. To fabricate the device, both plasma dry reactive etching and wet chemical etching (a) GAA NW-FET

(b) FinFET

5 nm Si

8 nm

HfO2

Si

26 nm Si

Figure 1.8  Schematic and fabricated device structure of Si n-type GAA NW-FET and FinFET, as reported in [43].

14  Nanodevices for Integrated Circuit Design

Gate processing 100 µm

1 µm

20 µm

Figure 1.9  Fabricated device structure of GaNvertical NW-FET (as reported in [44]).

were done. In comparison with other NW-FET, the proposed device offers a superior threshold voltage of 2.5V and a high current density of 101 kA/ cm. These results of GaN vertical NW-FET indicate that the device has the potential to be used extensively in future advanced technology. The carrier transport properties and impact of single trap phenomenon in a fabricated Si NW-FET device are studied and reported in [46]. The dynamic behavior of drain current, before and after the application of gamma-ray treatment is studied, and it was observed that the result deviates from the Shockley-Reed-Hall model prediction. The reason for such result is due to the existence of another energy barrier in accumulation region and the exchange of charge between a single trap and nanowire channel depends on gamma radiation treatment heavily. A detailed analysis is reported in the published work. The fabricated device structure and the variation of the behavior of relative amplitude ΔID/ID with drain current are shown in Figure 1.10.

10-1

200nm

Source

Nanowire

Oxide Back Gate

∆ID / ID

Drain

Source

10-2

Drain

Before Irradiation After Irradiation T=220K

T=280K 10-3

1 2 Drain current, ID (µA)

3

Figure 1.10  Fabricated device structure of Si NW-FET and variation of drain current before and after Gamma Ray radiation as reported in [46].

4

Growth of NW-FETs in 21st Century  15 Gate AI2O3 Contact

Contact

B Gate G

A

(a)

B’ SI Sub

D

D

9 nm

Source

Drain NW surrounded by metals

GaAs NW channel

SI Sub

A’

Gate

NW S

A-A’

S

B-B’

300 nm

(b)

(c)

Substrate 200 nm

Final device

AI2O3

G

Gate

GaAs NW channel

SI Sub

(d)

S

10 um

D

(e)

300 nm

Figure 1.11  The (a) schematic and (b - e) fabricated GaAs NW-FET structure as published in [47].

For the use of NW-FET in low-power applications, researchers fabricated an III-V junction-less NW-FET and reported some interesting observations [47]. The authors minimized the resistance in source/drain and thermal budget, by using the Metal-Organic Chemical-Vapor-Deposition (MOCVD) technique instead of the popular Ion Implantation technique. The fabricated device had a gate length of 80nm and an extremely narrow NW width of 9nm. The transistor exhibits excellent trans-conductance (gm) linearity even at the low bias of 300mV and it is found to be almost insensitive to the bias condition. The proposed device is useful for lowpower RF applications. The schematic and fabricated device structure, as presented by the authors, is shown in Figure 1.11.

1.3 Application of Nanowire Field-Effect-Transistors (NW-FET) According to the published reports on NW-FET, the device has the potential to be used in various advanced CMOS applications. Researchers in leading laboratories studied the device as sensor materials. In [48], an n-type poly-silicon NW-FET device is fabricated and its performance as a sensor device is explored. It has been observed that it can adjust the threshold voltage (VTh) for positive pH sensitivity of 100mV/pH and is also able to detect the presence of deoxyribonucleic acid (DNA) (VTh shift >100mV for 10pM) at the normal system operating voltage. The device can also be used as a non-volatile memory application and the CMOS-compatible fabrication process steps, give a possible solution, for the commercial manufacturing of System-On-Chip biosensor applications. The pH sensitivity

16  Nanodevices for Integrated Circuit Design characteristics and fabricated device structure, as presented in [48], are shown in Figure 1.12. The performance of an InAs NW-FET with HfO2-based high-K gate oxide is studied for low-frequency noise analysis in different current levels [49–51]. From the study, it is observed that the transistor shows some noises at low current levels due to the occurrence of trapping and de-­ trapping at the interface of gate-oxide region. Comparing the noise level with other advanced structures, the noise level is found to be in the same order, the Hooge’s parameter value is found to be 4.2×10-3. It indicates that the addition of HfO2 as a high-K dielectric does not degrade the low-­ frequency noise level. In another recent article, researchers have fabricated a Silicon Nanowire BioFET device for the early diagnosis of cancer [52, 53]. The device is fabricated with 45nm width NW, which was further modified with a specific antibody to form a Si NW BioFET. The transistor successfully demonstrated label-free detection of exosomes with a limit of detection of 2159 particles/L. 2.0x10-6 wire width / Lg = 50 nm / 14µm wire width / Lg = 50 nm / 4µm wire width / Lg = 50 nm / 2µm

Ion (Amp)

1.5x10-6

N+S/D

nanowire

9.7 % / PH

1.0x10-6

Lg

10.9 % / PH

5.0x10-7

9.4 % / PH

0.0

PH5

PH7

PH9

PH7

pH Concentration (a)

PH5

(b)

surface coupling induced substrate potential increase

Passivation PECVD Oxide Surface Oxide Poly-Si Nanowire

N+ S/D

Bottom oxide

N+ S/D O/N/O

Bottom gate nitride trap charge induced channel Vth increase (c)

Figure 1.12  The (a) fabricated and (b) schematic poly Si NW-FET structure (c) performance of the device as pH sensor as published in [48].

Growth of NW-FETs in 21st Century  17 (a)

(b)

I

II 29 nm

Au

45 nm Au

Si NWs

Figure 1.13  The (a) fabricated device structure of Si-NW BioFET and (b) SEM image of the Si-NW area, Inset: SEM image of the Si-NW from cross section and top, as published in [50].

In comparison with other BioFET devices based on two-dimensional material, the proposed Si-NW-BioFET is more compatible with the established CMOS fabrication setup, and thus fabrication cost of the device is also low. Also, this new device exhibits great potential in the detection of ultrasensitive biomolecules, proteins, nucleic acids, etc. The device structure, as reported by the authors, is shown in Figure 1.13.

1.4 Conclusion Nanowire Field Effect Transistor i.e. NW-FET is an advanced version of planner MOSFET device, which not only overcame the challenges faced by previous versions of MOSFET like FinFET but also has shown the potential to lead the semiconductor technological growth in the future. The initial works on the NW-FET device started with Group-IV Si material, later on, researchers started exploring other compound semiconductors like GaAs, InAs, ZnO, etc. In this chapter, the author discussed the gradual growth of the NW-FET device, from silicon to compound semiconductors, from theoretical and simulated works to the fabricated device output results, from the analysis of device physics to the application of modern day with several references from leading journals and conferences. Though the discussion is not exhaustive, there are plenty of other publications where the respected authors explained their findings beautifully. However, from the current chapter, it can be understood that the nanowire transistor has got the attention of the research community and various researchers are working hard to overcome the challenges associated with the device. Already several research works have been published in the last couple of decades

18  Nanodevices for Integrated Circuit Design where the physics of operation, challenges, and possible solutions of the device, and advantages over other established transistor architectures are discussed. These publications also opened up various new fields of research in this structure and people are working on this. Also, how this nanowire transistor can be utilized for modern-day applications, is well documented in recent publications and some of them are discussed in the current chapter. The academic research community and industry are extremely hopeful that the NW-FET device will be the leading transistor architecture in future advanced nanotechnology and applications.

References 1. Moore, G.E., Cramming more components onto integrated circuits. Electronics, 38, 114, 1965. 2. Das, S.K., Nanda, U., Biswal, S.M., Pandey, C.K., Giri, L.I., Performance analysis of gate-stack dual-material DG MOSFET using work-function modulation technique for lower technology nodes. Silicon, 14, 2965, 2021. 3. Hisamoto, D., Lee, W.-C., Kedzierski, J., Takeuchi, H., Asano, K., Kuo, C., Anderson, E., King, T.-J., Bokor, J., Hu, C., FinFET-a self-aligned double-gate MOSFET scalable to 20 nm. IEEE Trans. Electron Devices, 47, 12, 2320, 2000. 4. Seabaugh, A.C. and Zhang, Q., Low-voltage tunnel transistors for beyond CMOS logic. Proc. IEEE, 98, 12, 2095, 2010. 5. Wang, J., Device physics and simulation of silicon NW transistors, PhD Thesis, Univ. Perdue, Purdue University ProQuest Dissertations Publishing August 2005. 6. Ghani, T., Armstrong, M., Auth, C., Bost, M., Charvat, P., Glass, G., Hoffmann, T., Johnson, K., Kenyon, C., Klaus, J., McIntyre, B., Mistry, K., Murthy, A., Sandford, J., Silberstein, M., Sivakumar, S., Smith, P., Zawadzki, K., Thompson, S., Bohr, M., IEEE Int. Electron Devices Meeting Tech. Dig., p. 11.6.1, 2003. 7. Sinha, K., Chattopadhyay, S., Gupta, P.S., Rahaman, H., A technique to incorporate both tensile and compressive channel stress in Ge FinFET architecture. J. Comput. Electron., 16, 3, 620, 2017. 8. Maity, C.K., Chattopadhyay, S., Bera, L.K., Strained-Si heterostructure field effect devices, The Taylor & Francis Group, UK, 2007. 9. Yokoyama, M., Yasuda, T., Takagi, H., Yamada, H., Fukuhara, N., Hata, M., Sugiyama, M., Nakano, Y., Takenaka, M., Takagi, S., Symposium on VLSI Technology, pp. 242–243, 2009. 10. Xuan, Y., Shen, T., Xu, M., Wu, Y.Q., Ye, P.D., IEEE International Electron Devices Meeting, San Francisco, 2008.

Growth of NW-FETs in 21st Century  19 11. Kajale, S.N., Yadav, S., Cai, Y., Joy, B., Sarkar, D., 2D material based field effect transistors and nanoelectromechanical systems for sensing applications. iScience, 24, 103513, 2021. 12. Roy, T., Tosun, M., Kang, J.S., Sachid, A.B., Desai, S.B., Hettick, M., Hu, C.C., Javey, A., Field-effect transistors built from all two-dimensional material components. ACS Nano, 8, 6, 6259–6264, 2014. 13. Yakimets, D., Bardon, M.G., Jang, D., Schuddinck, P., Sherazi, Y., Weckx, P., Miyaguchi, K., Parvais, B., Raghavan, P., Spessot, A., Verkest, D., Mocuta, A., IEDM Tech. Dig., Dec. 2017, p. 501. 14. Cai, L., Chen, W., Du, G., Zhang, X., Liu, X., Layout design correlated with self-heating effect in stacked nanosheet transistors. IEEE Trans. Electron Devices, 65, 6, 2647, Jun. 2018. 15. Yao, J., Li, J., Luo, K., Yu, J., Zhang, Q., Hou, Z., Gu, J., Yang, W., Wu, Z., Yin, H., Wang, W., Physical insights on quantum confinement and carrier mobility in Si, Si0.45Ge0.55, Ge gate-all-around NSFET for 5 nm technology node. IEEE J. Electron Devices Soc., 6, 841, 2018. 16. Bangsaruntip, S., Balakrishnan, K., Cheng, S.-L., Chang, J., Brink, M., Lauer, I., Bruce, R.L., Engelmann, S.U., Pyzyna, A., Cohen, G.M., Gignac, L.M., Breslin, C.M., Newbury, J.S., Klaus, D.P., Majumdar, A., Sleight, J.W., Guillorn, M.A., IEDM Tech. Dig., Dec. 2013, p. 526. 17. Feng, P., Song, S.-C., Nallapati, G., Zhu, J., Bao, J., Moroz, V., Choi, M., Lin, X.-W., Lu, Q., Colombeau, B., Breil, N., Chudzik, M., Chidambaram, C., Comparative analysis of semiconductor device architectures for 5-nm node and beyond. IEEE Electron Device Lett., 38, 12, 1657, Dec. 2017. 18. Bufler, F.M., Ritzenthaler, R., Mertens, H., Eneman, G., Mocuta, A., Horiguchi, N., Performance comparison of n–type Si nanowires, nanosheets, and FinFETs by MC device simulation. IEEE Electron Device Lett., 39, 11, 1628, Nov. 2018. 19. Rau, M., Caruso, E., Lizzit, D., Palestri, P., Esseni, D., Schenk, A., Selmi, L., Luisier, M., IEDM Tech. Dig, Dec. 2016, p. 758. 20. Kim, S.-D., Guillorn, M., Lauer, I., Oldiges, P., Hook, T., Na, M.-H., Proc. IEEE SOI-3D-Subthreshold Microelectron. Technol. Unified Conf., Oct. 2015, p. 1. 21. Aldegunde, M., Garcia-Loureiro, A.J., Kalna, K., 3D finite element Monte Carlo simulations of multigate nanoscale transistors. IEEE Trans. Electron Devices, 60, 5, 1561, May 2013. 22. Loubet, N. et al., Proc. Symp. VLSI Technol., Jun. 2017, p. T230. 23. Iijima, S., Helical microtubules of graphitic carbon. Nature, 354, 56–58, 1991. 24. Sharma, A.K., Zaidi, S.H., Lucero, S., Brueck, S.R.J., Islam, N.E., Mobility and transverse electric field effects in channel conduction of wrap-around-gate nanowire MOSFETs. IEE Proc.- Circuits Devices Syst., 151, 5, 422, October 2004. 25. Wang, J., Rahman, A., Klimeck, G., Lundstrom, M., IEDM Tech. Dig., Dec. 2005, p. 4.

20  Nanodevices for Integrated Circuit Design 26. Guo, J. et al., A quantum-mechanical treatment of phonon scattering in carbon nanotube transistors. Appl. Phys. Lett., 86, 193103, 2005. 27. Kotlyar, R. et al., Assessment of room-temperature phonon-limited mobility in gated silicon nanowires. Appl. Phys. Lett., 84, 5270, 2004. 28. Nagy, D., Espiñeira, G., Indalecio, G., García-Loureiro, A.J., Kalna, K., Seoane, N., Benchmarking of FinFET, nanosheet, and nanowire FET architectures for future technology nodes. IEEE Access, 8, 53196, 2020. 29. Sinha, S., Shyam, K., Nishanthini, L., International Conference On Recent Innovations in Engineering and Technology (ICRIEAT) 2016 at Aurora’s Scientific Technological & Research, Hyderabad, 2016, https://www.researchgate.net/publication/341312637_Nanowire-FET_Devices_for_future_ Nanotechnology. 30. Konar, A., Mathew, J., Nayak, K., Bajaj, M., Pandey, R.K., Dhara, S., Murali, K.V.R.M., Deshmukh, M., Carrier transport in high mobility InAs nanowire junctionless transistors. Nano Lett., 15, 3, 1530–6984, 2015. 31. Yoon, J., Huang, F., Shin, K.H., Sohn, J.I., Hong, W.-K., Effects of applied voltages on the charge transport properties in a ZnO nanowire field effect transistor. Materials, 13, 268, 2020. 32. Seoane, N., Nagy, D., Indalecio, G., Espiñeira, G., Kalna, K., García-Loureiro, A multi-method simulation toolbox to study performance and variability of nanowire FETs. Materials, 12, 2391, 2019. 33. Li, Y., Chen, C.-Y., Chuang, M.-H., Chao, P.-J., Characteristic fluctuations of dynamic power delay induced by random nanosized titanium nitride grains and the aspect ratio effect of gate-all-around nanowire CMOS devices and circuits. Materials, 12, 1492, 2019. 34. Pricea, A. and Martinez, A., Investigation on phonon scattering in a GaAs nanowire field effect transistor using the non-equilibrium Green’s function formalism. J. Appl. Phys., 117, 164501, 2015. 35. Chakraverty, M., A compact model of silicon-based nanowire field effect transistor for circuit simulation and design, 2014, https://arxiv.org/ftp/arxiv/ papers/1407/1407.2358.pdf. 36. Sano, N., Yoshida, K., Yao, C.-W., Watanabe, H., Physics of discrete impurities under the framework of device simulations for nanostructure devices. Materials, 11, 2559, 2018. 37. Lee, Y., Logoteta, D., Cavassilas, N., Lannoo, M., Luisier, M., Bescond, M., Quantum treatment of inelastic interactions for the modeling of nanowire field-effect transistors. Materials, 13, 60, 2019. 38. Martinez, A. and Barker, J.R., Quantum transport in a silicon nanowire FET transistor: Hot electrons and local power dissipation. Materials, 13, 3326, 2020. 39. Cui, Y., Zhong, Z., Wang, D., Wang, W.U., Lieber, C.M., High performance silicon nanowire field effect transistors. Nano Lett., 3, 2, 149, 2003.

Growth of NW-FETs in 21st Century  21 40. Xiang, J., Lu, W., Hu, Y., Wu, Y., Yan, H., Lieber, C.M., Ge/Si nanowire heterostructures as high-performance field-effect transistors. Nature, 441, 7092, 489–493, 2006. 41. Demontis, V., Zannier, V., Sorba, L., Rossella, F., Surface nano-patterning for the bottom-up growth of III-V semiconductor nanowire ordered arrays. Nanomaterials (Basel), 2079, 11, 2021. 42. Clark, T.E., Nimmatoori, P., Lew, K.-K., Pan, L., Redwing, J.M., Dickey, E.C., Diameter dependent growth rate and interfacial abruptness in vapor–liquid– solid Si/Si1−xGex heterostructure nanowires. Nano Lett., 8, 4, 1246, 2008. 43. Kim, S., Kim, J., Jang, D., Ritzenthaler, R., Parvais, B., Mitard, J., Mertens, H., Chiarella, T., Horiguchi, N., Lee, J.W., Comparison of temperature dependent carrier transport in FinFET and gate-all-around nanowire FET. Appl. Sci., 10, 8, 2979, 2020. 44. Fatahilah, M.F., Yu, F., Strempel, K. et al., Top-down GaN nanowire transistors with nearly zero gate hysteresis for parallel vertical electronics, Sci. Rep., 9, 10301, 2019. 45. Yu, F. et al., Normally off vertical 3-D GaN nanowire MOSFETs with inverted-GaN channel. IEEE Trans. Electron Devices, 65, 2439–2445, 2018. 46. Zadorozhnyi, I., Li, J., Pud, S., Hlukhova, H., Handziuk, V., Kutovyi, Y., Petrychuk, M., Vitusevich, S., Effect of gamma irradiation on dynamics of charge exchange processes between single trap and nanowire channel. Small, 14, 1702516, 2018. 47. Song, Y., Zhang, C., Dowdy, R., Chabak, K., Mohseni, P.K., Choi, W., Li, X., III-V junctionless gate-all-around nanowire MOSFETs for high linearity low power applications. IEEE Electron Device Letters, 35, 3 324–326, 2014. 48. Chen, M.C., Chen, H.Y., Lin, C.Y., Chien, C.H., Hsieh, T.F., Horng, J.T., Qiu, J.T., Huang, C.C., Ho, C.H., Yang, F.L., A CMOS-compatible Poly-Si nano­ wire device with hybrid sensor/memory characteristics for system-on-chip applications. Sensors (Basel), 12, 4, 3952–63, 2012. 49. Persson, K.-M., Lind, E., Dey, A.W., Thelander, C., Sjöland, H., Wernersson, L.-E., Low-frequency noise in vertical InAs nanowire FETs. IEEE Electron Device Lett., 31, 5, 428–430, May 2010. 50. Tripathi., S.L., Sinha, S.K., Patel, G.S., Low-power efficient p+ Si0.7Ge0.3 pocket junctionless SGTFET with varying operating conditions. J. Electron. Mater., 49, 4291–4299, 2020. 51. Tripathi, S.L., Sinha, S.K., Gupta, P., International Conference on Intelligent Circuits and Systems (ICICS), pp. 42–45, 2018, doi: 10.1109/ICICS.2018.00021. 52. Zhao, W., Hu, J., Liu, J. et al., Si nanowire Bio-FET for electrical and label-free detection of cancer cell-derived exosomes. Microsyst. Nanoeng., 8, 57, 2022. 53. Tripathi, S.L., Patel, R., Agrawal, V.K., Low leakage pocket junction-less DGTFET with biosensing cavity region. Turk. J. Electr. Eng. Comput. Sci., 27, 4, 2466–2474, 2019.

2 Impact of Silicon Nanowire-Based Transistor in IC Design Perspective G. Boopathi Raja

*

Department of ECE, Velalar College of Engineering and Technology, Erode, India

Abstract

While the majority of the electronics industry depends on lithographic transistors that are getting smaller and smaller, this downsizing cannot go on forever. The most potential replacement for lithographic-based integrated circuits appears to be nano-electronics or circuits constructed with components as small as 10 nm. In chemical laboratories, molecular-size devices including bistable switches, diodes, nanowires, and nanotubes have already been made and studied. It has also been shown how to manufacture small-scale prototypes using methods for selfassembling these devices into various topologies. Nanoscale electronics will be possible due to these devices and assembly techniques; however, they have the drawback of being susceptible to errors and short-term issues. The development of nano-electronics will need fault tolerance mechanisms. Silicon nanowires are treated as basic building component for fabricating nanoelectronic devices including Field Effect Transistors because they have produced using single-crystal structures with diameters of a few nanometers and with adjustable holes and electron doping. To investigate potential silicon nanowire transistor limits, we assessed the impact of the source-drain contact annealing procedure and surface passivation on key transistor parameters. The SiNWs as basic components has significant benefits as compared to cutting-edge planar silicon devices based on all these results as well as other important criteria. Keywords:  Graphene-based field effect transistor, nanoscale, NEMS, silicon nanowire

Email: [email protected]

*

Suman Lata Tripathi, Abhishek Kumar, K. Srinivasa Rao, and Prasantha R. Mudimela (eds.) Nanodevices for Integrated Circuit Design, (23–42) © 2023 Scrivener Publishing LLC

23

24  Nanodevices for Integrated Circuit Design

2.1 Introduction Future nanoelectronics are drawn to materials including carbon nanotubes and semiconductor nanowires since they can serve as both bridge wires connecting to larger scale metallization and perform a range of device functions, [1]. By coating the nanomaterial on the substrate’s isolating surface, creating source, and drain connections at the ends of the NT or NW, and then creating either a top or bottom gate electrode, field effect transistors (FETs) have already been realized using NTs and NWs. This fundamental strategy could provide the cornerstone for hybrid electronic systems that combine nanoscale basic components with more intricate planar silicon circuitry in the future, but a number of concerns, such as device performance, repeatability, and integration, will need to be resolved first. Improvements have been made to important device properties including the carrier mobility and transconductance in the case of NT FETs. For instance, recent research has demonstrated that contact thermal annealing may greatly boost the observed carrier mobility. However, the fact that NT samples blend semiconducting and metallic components might be a barrier for upcoming advances in nanoelectronics, [2]. However, the kind and concentration of doping may be changed throughout the production process of silicon nanowires (SiNWs), which are permanently semiconducting. Additionally, SiNW building blocks might well be easier to integrate than NTs into silicon industry manufacturing and processing which might lower obstacles to the development of hybrid structures. The transconductance and carrier mobility of SiNW FETs were first found to be quite poor. Future research into the characteristics of both the SiNW transistor in a crossed NW FET design has shown that the SiNWs’ initial low values for mobility and transconductance were partially caused by completely inadequate connections between the SiNWs and sourcedrain electrodes, failing to produce characteristics of the single-crystal NW basic elements, [3]. In this work, we examine the limitations of SiNW FETs by examining the effects of source-drain contact annealing and surface passivation  on critical transistor parameters. The average transconductance increased from 45 to 800 Ns and the usual mobility increased from 30 to 560 cm2/Vs after thermal annealing as well as chemical passivation of oxide defects, exhibiting maxima at 2000 nS and 1350 cm2/ Vs, accordingly. The SiNWs as building blocks have significant benefits as compared to cutting-edge planar silicon devices based on these results and other important criteria.

Silicon Nanowire-Based Transistor  25

2.2 Nanoscale Devices Nanoscale devices are ones that can operate with things at the atomic or molecular level and are 100–10,000 times smaller than human cells. Figure 2.1 shows the classification of nanomaterials with examples on each category. Nanoscale devices include nanoelectromechanical oscillators, graphenebased transistors, and synthetic molecular motors including rotaxanes [4, 5]. The application areas of nanomaterials are listed in Figure 2.2.

2.2.1 Carbon Nanostructures For the creation of novel devices such as composites, sensors, and nanoscale electrical devices, carbon nanostructures such as ferrocene, CNTs, CNFs, graphene, and a broad range of related forms are appealing nanomaterials, [6]. For many biological applications, polymers with carbon nanostructures have been researched. CNTs can give biological scaffolds the necessary structural support. Due to the mechanical strength of CNTs, adding a little portion of them to a polymer improves the composite’s mechanical strength significantly, making them a good choice for new polymer composites, [7]. Small concentrations of CNTs less than 1% weight can be added to nanocomposites to enhance their physical characteristics and functionality. Figure 2.3 shows different forms of carbon nanostructures based on arrangement of carbon sheets. Because polymers naturally have low solubility and processability, it is difficult to assemble and process them with polymers to transfer the remarkable features of carbon nanostructures from the nanoscale to the microscale. The problem is overcome by lateral carboxylic synthesis

Nanomaterials

Zero Dimension

One Dimension

Two Dimension

Three Dimension

Quantum Dots Rings Atomic Clusters

Carbon Nanotubes Silicon Nanofibres Filaments Spirals and Springs

Nanolayers Nanodiscs

Embedded Clusters Embedded Crystallites

Figure 2.1  Classification of nanomaterials.

26  Nanodevices for Integrated Circuit Design

Nanotechnology

Agriculture & Biotechnology

Energy & Environment

Nanomaterials Nanoparticles Nanowires Nanorods Nanofilms Carbon Nanotubes Graphene Fullerene Nanocomposites Nanolithographic patterned surfaces

Textiles & Clothes

Information Technology

Healthcare

Transportation

Food & Nutrition

Figure 2.2  Application areas of nanomaterials.

process, which also improves the materials’ interoperability with biological fluids and polymer matrix dispersion. Surface functionalization and the mineralization process were both altered by CNTs. The osteoblast matrix deposition, calcification, cellular proliferation, and synthesis of bone-like tissue were all made possible by the nanotubes’ effective nucleation surface, which also fostered the development of a biomimetic apatite covering.

fullerene carbon nano-onion (CNO) carbon nanodot (CND)

carbon nanohorn (CNH)

nanodiamond (ND)

Figure 2.3  Types of carbon nanostructures.

carbon nanotubes (CNTs)

graphene

Silicon Nanowire-Based Transistor  27 The application of CNTs in biomedicine and their interaction with living things have received a lot of attention. Numerous biological applications, along with the strengthening of tissue engineering scaffolds, have been made possible by the unique features of CNTs. The neurotoxicity and bio-compatibility of CNT nanostructured materials, however, require more investigation. The majority of the formation of different types of cells on CNTs or CNT-based composite materials has occurred in vitro. The ability to use nanotubes as substrates for peripheral nervous cell growth and so as probes of synaptic activity at the nanometer scale was demonstrated by the fact that while nerve cells grown on nanotubes encapsulated with bioactive molecules produced elaborate multiple neurites that showcased extensive branching, they did not prolong and over one or two neurites in unmodified nanotubes. CNTs may be able to help with the biochemical and functional reconnection of injured neurons since they can be used as substitutes for nerve cells and have the same size and shape, [4, 8]. In hippocampus neurons grown on nanotubes, the number of transient postsynaptic currents increased by a factor of six, indicating the establishment of functional synapses. These results showed that CNTs could connect and integrate functional neural network models in vitro without causing severe brain damage. Promising scaffolds for tissue regeneration were developed using multiwalled CNT matrices that resembling honeycombs. Mouse fibroblast cells were grown in these nanotube structures, and they created a confluent layer without cytotoxicity.

2.2.2 Nanoelectromechanical Systems NEMS, or nanoelectromechanical systems, are indeed a group of gadgets that integrate mechanical and electrical performance on the nanoscale. The next logical development in the miniaturization of so-called MEMS devices, or microelectromechanical systems, is NEMS. Mechanical, medicinal, and chemical sensors may be built using NEMS, which frequently combines transistor-like nanoelectronics with commercial processes, compressors, or engines. The term derives from the average size of a nanoscale device, which leads in decreased weight, particularly zero point motion, significant potential quantum mechanical effects, high mechanical resonance frequencies, and a high aspect ratio useful for ground sensing methods. Examples of applications include sensors and accelerometers that detect chemical components in the air, [9]. In 2000, IBM researchers unveiled the first Very Large-Scale Integration (VLSI) based  NEMS device. Its basic idea was that a memory device could be created out of an array of AFM tips that could heat or detect a

28  Nanodevices for Integrated Circuit Design malleable substrate. NEMS memory was added as a new entry to the Emerging Research Devices section of the 2007 International Technical Roadmap for Semiconductors (ITRS).

2.2.3 Graphene-Based Transistors A graphene channel sandwiched between two electrodes and a gate contact that modifies the channel’s electrical response makes up a graphene field effect transistor (GFET). To enable channel surface functionalization and receptor molecule binding to the channel surface, graphene is exposed. The clear target of interest’s receptor molecules attach to the GFET channel’s surface, functionalizing it, [10]. Figure 2.4 shows the arrangement of atoms in grapheme sheet. In particular, graphene-based transistors have made rapid advancements and are currently thought of as a replacement for post-silicon electronics. There are still many unsolved problems regarding the relative usefulness of graphene transistors in practical applications. Short-channel effects, which reduce the performance of current devices, probably won’t happen when graphene field-effect transistors are stretched to shorter channel lengths and quicker speeds. This is possible with the development of gadgets with exceedingly thin channels. The fabrication of gigantic graphene transistors that function in the present digital era, opening a wide and well-defined

Figure 2.4  Graphene sheet.

Silicon Nanowire-Based Transistor  29 bandgap, and creating graphene nanoribbons with distinct edges and widths are among the outstanding problems for graphene transistors, [11, 12].

2.2.4 Silicon Nanowire Based Devices A specific type of semiconductor nanowire known as a silicon nanowire, or SiNW, is typically created out of a silicon substrate by catalytic expansion or by solid-state exfoliation from a liquid or vapor phase. SiNWs have remarkable properties that are lacking from bulk 3-dimensional silicon materials. Silicon nanowires have a wide range of uses, including thermoelectrics, nanowire batteries, photovoltaics, and nonvolatile memory. Due to its unique quasi 1-dimensional physical structure and high surface to volume silicon ratio, silicon nanowire-based devices have a number of advantages over their traditional counterparts. The target application has a major influence on the manufacturing technique selection. However, due of their outstanding achievements, new capabilities like device-level configurations and cutting-edge device concepts such as the junctionless transistor may also be implemented. Thus, it is projected that the advancement of silicon nanowire technology would soon be recognized as an incredibly scalable complement to the existing silicon technology [13]. Nanowires are nanostructures with nanometer-scale diameters. Production of conducting (Au, Pt, Ni), semiconducting (GaN, InP), and insulating (TiO2, SiO2) nanowires is feasible and has a variety of practical uses. The fundamental techniques for creating nanowires are bottom-up techniques and top-down techniques like lithography. The bottom-up approach is determined by chemical composition, and it is the best way to create nanowires because it allows for precise control of crucial factors including chemical composition, growth direction, doping amount, length, and radius. However, the use of nanowires in practical applications is still at the experimental stage, [14].

2.3 Nanowire Heterostructures and Silicon Nanowires We examined the most recent developments in the study of chemically produced SiNWs and nanowire heterostructures. Overall, these illustrations highlight a number of significant developments that have the potential to alter nanoscale research and technology in the future. First, SiNWs’

30  Nanodevices for Integrated Circuit Design physical dimensions and electrical characteristics may be rationally controlled using the generic nanocluster stimulated VLSI growth technique. Second, electrical transport studies show that synthetic chemical silicon nanowires (SiNWs) have substantially lower functional and dopant variations than top-down created silicon nanostructures, resulting in outstanding device properties that typically surpass those of planar silicon technology. Third, we have shown that SiNWs have enormous promise for applications ranging from ultra-sensitive nanoscale sensors for chemical and medical detection to high-density, scalable, integrated nanoelectronics, [13]. There are several nanoscale electronic components and circuits that can be built using SiNWs. Finally, unique SiNW heterostructures display extra dimensions of complexity and functions for basic research and nanoelectronics applications, making it challenging to anticipate how far this type of nanosilicon can advance. Figure 2.5 shows the typical view of Silicon Nanowires produced for Chemical Vapor Deposition. According to the most recent research, nanowires can be used as the building blocks for the semiconductors of highly sensitive biosensors of the future. Nanowires have another practical usage in nanoelectromechanical systems (NEMS) based on their high Young’s moduli. Nanowires can help nanorobots produce and conduct the energy they need. Silicon nanowires are a popular sort of nanomaterial because of their exceptional electrical and mechanical characteristics. The conductivity of silicon nanowires may be manipulated by the fieldeffect action. Semiconducting nanowires include those made of silicon.

2 µm*

Figure 2.5  Silicon nanowires utilizing for chemical vapor deposition [19].

Silicon Nanowire-Based Transistor  31 The forthcoming generation of advanced field-effect transistors and sensors may benefit from silicon nanowires due to these features. Silicon nanowires represent one of the potential choices for the upcoming generation of electronics due to their great characteristics and performance that really is comparable to the best planar devices, [14]. In biochemistry and medicine, new cutting-edge sensors will be necessary for finding novel medications and treating illnesses. These sensors are necessary because they call for analysis with high resolution, affordable costs, and quick real-time answers. Because of its special qualities, including as biocompatibility, adjustable optical and electrical properties, and outstanding surface-to-volume ratio, silicon nanowires are a viable choice for detecting nucleic acids, viruses, and metal ions species. In most cases, they constitute field-effect transistor (FET)-based devices. Three electrodes make up silicon nanowires. The source electrode, drain electrode, and gate electrode are those three electrodes. The gate electrode maintains and controls the channel’s conductance while the source and drain link the semiconductor channel. The ability of this sensor to detect is owing to the presence of silicon nanowires in the conducting material between the drain electrode and the source electrode, [15].

2.3.1 Characteristics of SiNWs A. Thermal Characteristics Silicon nanowires have a curved form when used in research or applications, therefore they aren’t straight. The transit of phonons may be affected by their bending. It might potentially alter the way their thermal conductivity fluctuates. The curve of the nanowire acts as an obstacle to phonon transport when they deviate off from the primary heat flow direction and go axially through the nanowire. Thus, the heat conductivity decreases as the radius of the nanowire curvature increases. The curvature has a bigger impact on the thermal impedance when its radius is one order less than the phonon mean free path (MFP). The proper wire shape may be used to control the heat conductivity of silicon nanowires, [15], making this finding fascinating. B. Chemical Characteristics Natural oxidation is a key chemical process, which makes silicon nanowires very useful for transistor and sensor applications. This impact cannot be prevented because it causes oxygen-derived effects on the surface of the pure semiconductor nanowire core. According to experimental studies,

32  Nanodevices for Integrated Circuit Design the SiOx layer’s chemical modification may effectively double the silicon nanowire’s hole motility. C. Optical Characteristics Nanowires can experience mechanical strain effects whenever exposed to light because of their photo elastic qualities, and light’s wavelength is near to their energy bandgap. D. Mechanical Characteristics The mechanical properties of the nanowire are crucial for device manufacturing because interior dislocations can modify the electrical conductivity of the nanowire under external load, induced strain, and temperature changes. Tensile and compressive stresses experienced during VLSI processing might lead to failure due to electro-migration and delamination. According to research, nanowires’ intriguing mechanical properties are caused by the low defect density per unit length as well as high aspect ratio in comparison to bulk materials. Systems with one dimension comprise nanowires. NEMS (nano-electromechanical systems) and sensors are two areas where nanowires are used. Due to their great tensile strength and Young Modulus, they are exceptionally resilient materials that can store elastic energy. Additionally, silicon nanowires having high oscillation frequencies (100 MHz to 1 GHz) are able to construct nanoscale resonators due to their remarkably elastic properties, [15]. E. Electrical Characteristics of SiNWs It is important to comprehend semiconductor nanowire electrical properties because they indicate if SiNWs are acceptable for use in electronics and sensors applications. Each unit cell in the silicon nanowires has four atoms. Three conductance channels will be found if the crystalline is immaculate. As a result, the nanowire’s crystalline structure has an effect on conductivity. Variations in surface conditions, such as carriers’ scattering processes in nanowires, can alter conductivity. There seem to be findings of the scattering phenomenon as the nanowires’ diameters vary. The conductivity of nanowires is particularly susceptible to the activation of the surface via external charges because of their high surface-to-volume ratio. They can use silicon nanowires in the biosensors and can detect single molecules thanks to this important attribute, [15].

Silicon Nanowire-Based Transistor  33

2.3.2 Fabrication There are several ways to make silicon nanowires, and they can all be broadly categorized as either top-down synthesis—which also refers to methodologies that initiate with bulk silicon and discard the materials to yield the nanowires—or bottom-up synthesis—which refers to methods that use a vapor or chemical precursor to build nanowires. The performance of the SiNW biosensor may be influenced by several variables, including carrier densities, surface chemistry, and diameters. The bottom-up strategy takes into account techniques including photolithography, e-beam lithography, vapor-liquid-solid (VLS), and oxideassisted growth (OAG). There have recently been reports on the use of VLS fabrication methods to create silicon nanowires and their use as biosensors, [14]. (i) Bottom-Up Synthesis Technique • Vapor-liquid-solid (VLS) growth – a kind of accelerated CVD where the catalyst is usually gold nanoparticles and silane serves as the substrate for silicon (also known as seed). First reports of the VLS-based production of silicon nanowires using a silicon substrate combined with a liquid gold droplet appeared in 1964. Following the deposition of metal-catalyzed materials (such as Al, Pt, Fe, and Au) on the silicon wafer using VLS, the development of the silicon nanowires is accelerated using the chemical vapor deposition (CVD) method. SiH4 gas will evolve into silicon vapor as the silicon gas’s source, diffuse across a metal catalyst, and then condense as metal-silicon alloy droplets. As silicon diffuses over the metal nanoparticle catalyst, it will leave the metal silicon droplets and create silicon nanowires, creating a supersaturated state. • Precipitation from a solution – A supercritical fluid (organosilane) is used in place of vapor as a Si precursor in the supercritical fluid liquid-solid (SFLS) modification of the VLS process. The fluid would contain a colloid catalyst, including such colloidal gold nanoparticles, and silicon nanowires would spread throughout the mixture. • Molecular beam epitaxy – a PVD’s plasma environment implementation form.

34  Nanodevices for Integrated Circuit Design

Thermal Oxidation Following chemical or physical bottom-up or top-down processing to create the first silicon nanostructures, thermal oxidation processes are frequently used to produce materials with the desired aspect ratio and size. The self-limiting oxidation behavior of the silicon nanowires is advantageous and unusual, yet it effectively ceases owing to diffusion restrictions, as is expected. The aspect ratios and measurements of silicon nanowires may be precisely controlled using these phenomena, and it has been utilized to create silicon nanowires with small diameters and high aspect ratios. The silicon nanowire’s self-limiting oxidation is helpful for the lithiumion battery’s constituent parts. (ii) Top-Down Synthesis Methods Diverse scholars have outlined the modalities for the top-down methods of producing silicon nanowires in studies. The top-down method comprises the production of separate silicon nanowires from the bulk material. This may be accomplished by using nanolithography techniques as electron beam lithography (EBL), nano-imprint lithography, and others. In these procedures, material removal procedures are employed to create nanostructures from a large-scale predecessor. ■■ ■■ ■■ ■■

Thermal evaporation oxide-assisted growth (OAG) Laser beam ablation Ion beam etching Metal-assisted chemical etching (MaCE)

Metal-Assisted Chemical Etching This is the simplest and least expensive way to make SiNMs. The electroless metal (nickel, gold, silver, and platinum) deposition on the silicon wafer and the following chemical etching in a fluoride-ion solution are the two key steps in this process. In this case, the silicon substrate’s silver ion, which resulted from the deposition of silver nanoparticles on its surface, attracts electrons. The silicon has been oxidized behind the silver nanoparticle, and the HF’s action has caused the holes to form. The created holes act as a sinking path for the remaining Ag nanoparticles. It results in the lateral and longitudinal suspension of silicon and beginning the production of the SiNW arrangements.

Silicon Nanowire-Based Transistor  35

2.3.3 Applications of SiNWs Due to their outstanding chemical and physical capabilities, silicon nanowires are a good alternative for a wide range of applications that rely on their extraordinary physicochemical features. They have different characteristics than bulk silicon material. Due to their ability to trap charges, silicon nanowires are useful in applications like photocatalysts and photovoltaics that need the separation of electrons from holes. Silicon nanowires are appealing for use as field-effect transistors, nanoelectronic storage devices, metal-insulator semiconductors, logic devices, chemical sensors, biological sensors, and flash memory due to all of these properties, [15–22]. Silicon nanowires have a unique advantage as those anodes since they can sustain significant lithiation while preserving electrical properties and structural integrity. Due to their combination of low heat conductivity from the narrow cross-section and high electrical conductivity from the bulk properties of the doped Si, they are efficient and effective thermoelectric generators. Experimental uses of silicon nanowire sensors include the detection of DNA, pH, gas sensors, glucose, drug discovery, and proteins. a. Single Virus Finding a single virus particle is a difficult for SiNW biosensing and is crucial for medicine. In an experiment, the surface of the p-type SiNW sensor was seen to be covered by an antibody receptor. b. pH Hydrogen ion concentration is sensed through pH sensing. When a p-type SiNW’s surface is modified with 3-aminopropyltriethoxysilane, hydrogen ions may be detected by it. The surface charge of the SiNW is altered as a result of the catalytic action of the silane and amino groups. c. Glucose There have been reports of glucose being found. The surface oxide layer of a silicon nanowire is altered by the glucose oxidase (GOx) enzyme. There were findings of a modification in the silicon nanowire’s conductance when glucose was close to its surface. d. Proteins To detect the protein streptavidin, the chemical biotin is utilized as a binding substance. Because it is very selective to this protein, biotin is utilized. When protein reaches the silicon nanowire’s surface, its conduction quickly increases to a constant value. The absence of the molecule biotin

36  Nanodevices for Integrated Circuit Design has no effect on the conductance, demonstrating the excellent sensitivity and selectivity of the SiNW sensor. e. DNA When the uncharged peptide nucleic acid (PNA) is used as the bonding substance on the surface of the p-type SiNW, it is feasible to detect the DNA. PNA was made to exclusively bind to DNA that was of the wild type. The negative charge of DNA causes silicon nanowire conductance to rise quickly. f. Drug Discovery Finding novel medications is crucial for the development of pharmaceuticals. The procedure is similar to the previous application examples, but it makes use of a change in silicon nanowire conductance to gauge how well an organic molecule binds to an enzyme or protein (possible receptors). SiNW sensors therefore make it possible to characterize the medications quickly and simply. g. Sensor Arrays The silicon nanowires may be incorporated into arrays that are useful for assessing complex circumstances. Performance of the whole sensor depends on the array’s repeatability of SiNW elements. Silicon nanowires have good repeatability. h. Gas Sensors SiNWs may be used as gas sensors as well. Palladium nanoparticles were employed to cover the surface of the n-type SiNW in order to show it. This sensor only responds when it is exposed to H2 gas molecules; N2O or NH3 gases have no effect on it. Even still, as the hydrogen gas passed over the sensor, the current that would have been passing through it rose. Because of this, SiNW sensors have higher selectivity values when used as biosensors than when used as chemical sensors. i. Fluorescence’s Sensor-Utilized SiNWs Researchers have showed a unique AuNP-SiNW-based molecular beacons (MBs) for high sensitivity multiplex DNA detection. According to studies, the AuNP-SiNW-based MBs showed strong stability in both thermal stability at 15-85°C and wide salt content in the range of 0.010.1 M, [15].

Silicon Nanowire-Based Transistor  37 j. FET Sensor-Utilized SiNWs The silicon nanowire sensors are conventional FET-based components when contrasted to the three electrodes. The shift in charge density causes an alteration in the electric field at the silicon nanowire’s outer surface. Researchers have developed a highly efficient direct time and label-free DNA detection method using a SiNWs-FET sensor using a top-down methodology. Researchers successfully optimized characteristics such the probe concentration, buffer ionic strength, and gate voltage in order to effectively increase the sensitivity of the SiNWs-FET sensor in their study effort. In conclusion, silicon nanowire is the potential nanomaterial for future nanomaterial sensing, [15]. k. SiNW Transistors Ring oscillators, smart cards, lasers, wearable electronics, high-efficiency programming, 3-Dimensional computing, storage systems, displays, etc. are just a few examples of the many practical uses for SiNW transistors. The summaries of a few of them are provided here.

Ring Oscillator Another experimental use for silicon nanowire transistors is as a ring collector. Compared to traditional manufacturing processes, it offers a number of advantages. The primary one is that perfect device integration is achieved during manufacturing because to SiNW’s great repeatability. Furthermore, the SiNW ring oscillator is better than those created using traditional planar devices because to its high performance and superb stability.

Crossed Nanowire Architecture The crossed nanowire design enables a wide range of electronic device components such as logic gates, transistors, and diode, etc. It is able to produce with high integration density due to tiny diameter of the silicon nanowires. Crossed NWFETs can be constructed with the gate present on either or both of the crossed nanowires’ surfaces, and just a thin SiO2 dielectric layer stands between them on the silicon nanowire surface. The NOR gate is the first device to employ crossed nanowire design. As can be seen, the gate’s output only becomes high when its input and expected output are both low.

38  Nanodevices for Integrated Circuit Design

Memory Array This is due to vertically produced silicon nanowires. Based on the tiny cell size and exceptional array structure, high-density memory is supplied with quick accessing or programming capabilities at a cheap cost of manufacture.

2.4 Performance Analysis of Si Nanowire with SOI FET Nano-electronics show improvement as a technology for furthering IC shrinking. Furthermore, whether nano-electronics will serve as a substitute for traditional integrated circuits or a complementary technology remains to be seen. According to early study, while current elements of CAD tools will be beneficial for nano-electronics, certain additions and alterations will be required. The most progress has been achieved in the study of the ingredients that may comprise nano-electronics. We have compared key SiNW FET characteristics to modern planar metal-oxide-semiconductor FETs (MOSFETs) made with SOI in order to explore this analogy quantitatively (Table 2.1). One important factor impacting the raw device speed is mobility, which controls how quickly charge carriers travel in the conducting channel. In order to compare the results of other crucial factors, the SiNW FET findings have previously were resized with SOI FET gate dimension of 50 nm and gate oxide thickness of 1.5 nm. Compared to the most advanced Si FETs, the SiNW FET’s scaled on-state current (Ion) is significantly higher. Additionally, the mean subthreshold slope for the SiNW FET exceeds the theoretical limit and the typical transconductance is around ten times higher. Fast mobility and high-gain devices may significantly benefit from these advancements. SiNW FET devices also have higher leakage currents, which can be mitigated by putting pn-diodes on the drain and source contacts, just like conventional MOSFETs. This result demonstrates that explicitly verifying scaling assumptions and attempting to produce smaller SiNW FETs may have a big impact. Furthermore, scaling SiNW FET transport properties and contrasting them with those for contemporary planar MOSFETs indicates how SiNWs have a considerable performance advantage over typical devices, making them great building blocks for future nanoelectronics [23, 24].

Silicon Nanowire-Based Transistor  39

Table 2.1  Performance analysis of Si nanowire and SOI FET’s major device parameters. Subthreshold slope (mV/ decade)

Transconductance (µS/µm)

Gate length (nm)

Gate oxide thickness (nm)

Planar Si device

70

650

50

1.5

Nanowire raw data

60

2700–7500

50

1.5

Nanowire converted data

174–609

17–100

800–2000

600

Parameter

Mobility (cm2/Vs)

Ioff (nA/ µm)

Ion (µA/ µm)

9

650

230–1350

4–45

2000– 5600

230–1350

2–50

50–200

40  Nanodevices for Integrated Circuit Design

2.5 Conclusion The target application has a major influence on the manufacturing technique selection. From the perspective of applications, downscaling a silicon metal insulator semiconductor transistor naturally leads to electron devices based on silicon nanowires. The distinct characteristics, however, also permit the implementation of novel device ideas, like as the junctionless transistor, and novel functionality, including reconfigurability at the device level. Silicon nanowires may be precisely grown using bottom-up processes. Due to their better qualities when contrasted to other nanomaterials, silicon nanowires may be employed to create the next generation of nanostructures. Nanowires can grow because of their high Young’s moduli and high elasticity. Because of these traits, detection has been reduced to the scale of a single molecule, which is a significant advancement and has the potential to significantly impact illness diagnosis and lead to the discovery of novel medications. The SiNW electrochemical sensors also eliminate the need for time-consuming and expensive chemical labeling detection by offering a direct label-free electrical readout.

References 1. Haselman, M. and Hauck, S., The future of integrated circuits: A survey of nanoelectronics. Proc. IEEE, 98, 1, 11–38, Jan. 2010, DOI.org (Crossref), https://doi.org/10.1109/JPROC.2009.2032356. 2. Raja, B.G., Impact of nanoelectronics in the semiconductor field: Past, present and future, in: Nanotechnology, pp. 75–91, CRC Press, 2022. 3. Mikolajick, T., Heinzig, A., Trommer, J., Pregl, S., Grube, M., Cuniberti, G., Weber, W.M., Silicon nanowires - a versatile technology platform. Phys. Status Solidi (RRL) - Rapid Res. Lett., 7, 10, 793–799, 2013, https://doi.org/10.1002/ pssr.201307247. 4. Nanoscale devices: https://www.nature.com/subjects/nanoscale-devices. 5. Aguilar, Z.P., Nanomedical devices, in: Nanomaterials for Medical Applications, pp. 235–292, 2013, https://doi.org/10.1016/b978-0-12-385089-8.00006-6. 6. Raja, G.B., Performance review of static memory cells based on CMOS, FinFET, CNTFET and GNRFET design, in: Nanoscale Semiconductors, pp. 123–140, 2022, https://doi.org/10.1201/9781003311379-6. 7. Raja, G.B. and Madheswaran, M., Design and analysis of 5-T SRAM cell in 32nm CMOS and CNTFET Technologies. Int. J. Electron. Electr. Eng., 1, 256– 261, 2013, https://doi.org/10.12720/ijeee.1.4.256-261.

Silicon Nanowire-Based Transistor  41 8. BoopathiRaja, G. and Madheswaran, M., Design and performance comparison of 6-T sram cell in 32nm CMOS, FinFET and CNTFET Technologies. Int. J. Comput. Appl., 70, 21, 1–6, 2013, https://doi.org/10.5120/12188-7751. 9. Themed issue on micro/nano-electro-mechanical-systems (MEMS/NEMS). IEEE Electron Device Lett., 33, 9, 1327–1327, 2012, https://doi.org/10.1109/ led.2012.2214551. 10. Graphene nano transistors: https://www.nature.com/articles/nnano.2010.89. 11. Boopathi Raja, G. and Madheswaran, M., Performance comparison of GNRFET based 6T SRAM cell with CMOS, FinFET and CNTFET Technology. Int. J. Innov. Res. Sci. Eng., 2, 5, 197–204, 2016. 12. Abdul Rashid, J.I., Abdullah, J., Yusof, N.A., Hajian, R., The development of silicon nanowire as sensing material and its applications. J. Nanomater., 2013, 1–16, 2013, https://doi.org/10.1155/2013/328093. 13. Chandra, S.T. and Balamurugan, N.B., Performance analysis of silicon nanowire transistors considering effective oxide thickness of high-k gate dielectric. J. Semiconduct., 35, 4, 044001, 2014, https://doi.org/10.1088/ 1674-4926/35/4/044001. 14. Hobbs, R.G., Petkov, N., Holmes, J.D., Cheminform abstract: Semiconductor nanowire fabrication by bottom-up and top-down paradigms. ChemInform, 43, 32, 1975–1991, 2012, https://doi.org/10.1002/chin.201232227. 15. Silicon nano wires- synthesis and application areas: https://nanografi.com/ blog/silicon-nanowires-synthesis-and-application-areas. 16. Tripathi, S.L. and Patel, G.S., Design of low power Si0.7Ge0.3 pocket junctionless tunnel FET using below 5 nm technology. Wirel. Pers. Commun., 111, 2167–2176, 2020, https://doi.org/10.1007/s11277-019-06978-8. 17. Tripathi, S.L., Patel, R., Agrawal, V.K., Low leakage pocket junction-less DGTFET with bio-sensing cavity region. Turk. J. Electr. Eng. Comput. Sci., 27, 4, 2466–2474, 2019, DOI:10.3906/elk-1807-186. ISSN: 1300-0632. 18. Mendiratta, N., Tripathi, S.L., Padmanaban, S., Hossain, E., Design and analysis of heavily doped n+ pocket asymmetrical junction-less double gate MOSFET for biomedical applications. Appl. Sci., 10, 7, 2499, 2020, https:// doi.org/10.3390/app10072499. 19. Raja, G.B. and Madheswaran, M., Logic fault detection and correction in SRAM based memory applications. 2013 International Conference on Communication and Signal Processing, 2013, https://doi.org/10.1109/iccsp.2013.6577046. 20. Boopathi Raja, G. and Madheswaran, M., Design of improved majority logic fault detector/corrector based on efficient LDPC codes. Int. J. Adv. Res. Electr. Electron. Instrum. Eng., 7, 3429–3437, July 2013. 21. Peng, K.-Q., Wang, X., Li, L., Hu, Y., Lee, S.-T., Silicon nanowires for advanced energy conversion and storage. Nano Today, 8, 1, 75–97, 2013, https://doi. org/10.1016/j.nantod.2012.12.009. 22. CVD Equipment Corporation, https://www.cvdequipment.com/portfolioitem/silicon-nanowires-sem-10-k-x/.

42  Nanodevices for Integrated Circuit Design 23. Bassi, M., Tripathi, S.L., Verma, S., Analysis and design of high-K material nanowire transistor for improved performance. IEEE IEMCON, Vancouver, BC Canada, pp. 0613–0618, 2019. 24. Mendiratta, N. and Tripathi, S.L., DG MOSFET for bio-sensing applications: A review. 2021 Devices for Integrated Circuit (DevIC), pp. 112–115, 2021, doi: 10.1109/DevIC50843.2021.9455760.

3 Kink Effect in Field Effect Transistors: Different Models and Techniques Abdelaali Fargi*, Sami Ghedira and Adel Kalboussi Laboratory of Microelectronics and Instrumentation, Department of Physics, University of Monastir, Monastir, Tunisia

Abstract

The kink effect is a very important phenomenon as it impacts the static and dynamic characteristics of components. It is almost present in all FET devices ranging from MESFET, MOSFET, TFT, and HEMT. At the nanoscale, this effect becomes pronounced and even at low temperatures where CMOS technology can still be used for cryogenic applications like space technology and quantum computing. In this work, we present different techniques to describe kink effect in output characteristics of field effect transistors. This chapter reports the origins of kink effect in FET Devices like impact ionization, short channel effects, incomplete ionization of traps, interface states, etc. We demonstrate by experiments the appearance of a “kink” parasitic effect on the Capacitance-voltage (C-V) characteristics in MOS capacitors in flat band regimes at different temperatures. We show that the numerical simulation can be used to analyze the kink effect origins and the impact of its parameters. Our approach is based on a novel procedure that allows the extraction of these parameters. For this type of devices, we prove that this kink effect is due to the trap introduced by heavy dopants. A study of the influence of the three fundamental characteristics of this defect (activation energy, density, and capture cross section) shows that the indium defect level located at 0.16 eV above Valence Band is the direct cause of kink effect. Keywords:  Capacitance-voltage, kink effect, indium trap, incomplete ionization, CV simulation, activation energy, density of traps, MOS capacitor

*Corresponding author: [email protected] Suman Lata Tripathi, Abhishek Kumar, K. Srinivasa Rao, and Prasantha R. Mudimela (eds.) Nanodevices for Integrated Circuit Design, (43–60) © 2023 Scrivener Publishing LLC

43

44  Nanodevices for Integrated Circuit Design

3.1 Introduction Microelectronics has continuously responded to the demands of speed and integration of components while seeking to maintain their reliability and reduce production costs. However, the reduction of dimensions is confronted with limits of physical, technological, and economic orders. In recent years, even though Field Effect Transistor device technology has advanced significantly, there is still considerable uncertainty about a few factors that impact the device’s performance in its normal function. In the MOSFET transistors, the reduction of its dimensions, and in particular when the channel length becomes less than 0.2 μm, several parasitic effects appear. The kink effect, one of these issues, is characterized by a sudden increase in drain current at a certain drain bias. The kink effect must be better understood from the standpoint of device reliability. While SOI MOSFET devices are known for their superior performance, they often suffer from numerous undesirable side effects caused by the buried oxide layer, including self-heating [1] and kink effects [2–4]. The buildup of holes brought on by impact ionization at the channel region’s drain end causes the kink in current. For the cause of the kink effect, some authors proposed the idea which consists on formation of virtual gate up to the drain region of AlGaN/GaN HEMT [5]. At very low cryogenic temperatures, not only CMOS devices at the microscale and high working voltages display the kink effect in the output characteristics. At extremely low voltages, existing Bulk and SOI CMOS technologies like 180-nm [6] and 28-nm CMOS are employed to monitor this phenomenon. The advanced CMOS technology is used at low temperatures called “cryogenic” for applications in space industry where radiation effects have to be avoided for normal operation of the system and in quantum computing when reading signals from qubits [7]. Many different types of semiconductors used in transistors, including Si in MOSFETs [8, 9], GaAs in MESFETs [10, 11], AlGaAs/InGaAs in HEMTs [12], and InAlAs/InGaAs in HEMTs [13], have successfully reported kink effects. The processes behind such kink effects are categorized from three angles and succinctly outlined in reference [14]. The first one is Channel impact-ionization followed by hole accumulation changes the potential at the channel/substrate contact [15–18]. The second is based on capture and (or) emission of electrons (or holes) through traps (deep levels) and interfaces states [19]. The last one is a combination between deep levels and

Field Effect Transistors  45 impact ionization that produces holes (or electrons) and changes the surface’s occupancy state as well as deep levels located in the bulk or beneath the interface of channel/substrate. All of these publications identify charge carrier de-trapping as the primary factor causing the kink effect. One of the solutions is to bury the channel of the FET device that is to use a retrograde doping profile. In the retrograde channel of silicon NMOS, Indium appears to provide the optimum profiles, that is, profiles that are suitably thin and resistant to annealing. In an earlier work by Fargi et al. [20, 21] and Hizem et al. [22], we carried out a study of In-bound defects in N+P junctions, MOS capacitor and indium-doped silicon-based MOSFET transistors and have analyzed their effects on the output characteristics of these transistors. In Section 3.3 of this chapter, we will show by simulation that the kink effect in the C-V characteristics of the MOS capacitors is due to the indium trap at 0.16 eV above the Valence Band.

3.2 Techniques of Kink Effect In this paragraph, we are giving kink effect details in the electrical characteristics of electron devices like in Capacitance-Voltage (C-V) of the MOS capacitors and in Current-Voltage (I-V) characteristics of FET devices.

3.2.1 Current-Voltage Technique One of the most used techniques to characterize an electron device is to use Current-Voltage tools. It exists a lot of equipment types to get output as well as transfer characteristics of Field Effect Transistors. Here, we have a home-made setup of I-V Technique as shown in Figure 3.1. Our setup consists of a Keithley 236 Source Measure Unit (SMU) used for Ids-Vds characteristics with another Voltage Generator from NI-ELVIS Card used for setting up gate voltage to the transistor. First of all, we fix and regulate Temperature, then we start by fixing gate voltage value at which we perform drain voltage sweep to get Ids-Vds characteristics. We repeat this step until the last value of gate voltage and at each Temperature value. A typical characteristic of FET device presenting kink effect is represented in Figure 3.2 below.

46  Nanodevices for Integrated Circuit Design

GPIB

PC running I-V-T LabVIEW Program

RS232

USB Keithley 236 SMU IDS-VDS

Lakeshore 331S Temperature Controller

NI-ELVIS II VGS Heater

BNC High BNC Low

Thermocouple

Janis VPF-800 Cryostat

Vacuum Pump

Figure 3.1  Schematic diagram of current-voltage technique setup with a temperature variation all controlled by computer running LabVIEW program. 0.15

Vgs = 2 V

0.10 Ids (A)

Kink Effect

0.05

Kink Voltage KKink 0.00

0

2

Vds (V)

4

6

Figure 3.2  A typical output characteristics of FET Device showing the kink effect.

3.2.2 Pulsed I-V Technique Once characterized by I-V technique and showed the kink effect on the output characteristics of the FET device, we could determine the dynamics of the kink by using a Pulsed Current-Voltage which gives details about kink evolution with pulse duration and measurement speed. There are many experiments using Pulsed I-V technique and here as shown in Figure 3.3, a typical setup using a Keithley 236 in Pulsed Mode along with a HP8116 Pulse Generator for gate control.

Field Effect Transistors  47

GPIB

PC running Pulsed I-V-T LabVIEW Program

RS232

USB Keithley 236 SMU in Pulse Mode IDS-VDS

HP 8116A Pulse Generator VGS Heater

BNC High BNC Low

Janis VPF-800 Cryostat

Lakeshore 331S Temperature Controller Thermocouple

Vacuum Pump

Figure 3.3  Schematic diagram of pulsed current-voltage setup with a temperature variation and pulse generator all controlled by a LabVIEW program.

A device under test is mounted inside a cryostat and a Lakeshore 331S Temperature controller is used to set and regulate the Temperature. We begin measurements by setting up the Temperature, then we make a pulse on the gate voltage at which we perform a pulsed Ids-Vds sweep and we repeat this step until the last gate voltage value. All measurements are done until last value of Temperature.

3.2.3 Capacitance-Voltage Technique Capacitance-Voltage is powerful technique that it could be used to determine built-in Voltage of a diode or MOS capacitor and Electronic Doping Concentration of the device. It could be used to measure capacitances of FET like Cgs, Cgd, and Cds by using a special circuit. The setup experiment of this technique is relatively simple and a typical one is represented in the Figure 3.4. As shown above, the setup consists of a Capacitance Meter HP4280A with a cryostat chamber, a vacuum pump and Lakeshore 331S Temperature controller. We mount the device under test (DUT) in the cryostat chamber, then we calibrate the C-V meter and we create vacuum around the DUT by pumping air out of the cryostat. After that, we cool down the device by versing liquid nitrogen and we start C-V measurements at each Temperature. As a result of this technique, it could reveal anomalies in the device characteristics like kink effect, Negative Differential Capacitance, etc…

48  Nanodevices for Integrated Circuit Design

HP 4280A SMU 1 MHz C-V Plotter

GPIB

PC running C-V-T LabVIEW Program

Heater

BNC High BNC Low

RS232 Lakeshore 331S Temperature Controller

Thermocouple

Janis VPF-800 Cryostat

Vacuum Pump

Figure 3.4  Schematic diagram of capacitance-voltage technique setup with temperature all controlled by LabVIEW program.

3.3 Different Models of Kink Effect Kink effect can be seen in output characteristics of most FET devices like MOSFET. It originates from different physical mechanisms which can be described by two main models which are: –– Impact Ionization Model –– Traps and Interface States Model Some authors revealed the existence of kink effect and found its origin related to impact ionization like [15–17]. Some other authors studied extensively the role of traps on kink effect like [5, 19, 22].

3.4 Kink Effect in MOS Capacitors The MOS capacitor structure studied is composed of a Si substrate doped with Boron (1017 cm-3) and Indium (5.1017 cm-3), on which deposited a layer of Silicon dioxide (SiO2) of thickness 3.2 nm and with an n-type heavily doped polysilicon grid (≈ 1020 cm-3).

The experimental study by Capacitance-Voltage (C-V) measurements at different temperatures on MOS structures showed a kink effect that appears in the zone of flat-band (Figure 3.5). We can give a small explanation based on the work of Pirovano et al. [23]:

Field Effect Transistors  49 400 350 300

1

C (pF)

250

Kink Effect

200 150

3

100 50 0 -3

T = 300 K T = 227 K T = 166 K T = 109 K

2 -2

-1

V (V)

0

1

2

Figure 3.5  Capacitance-voltage characteristics of the MOS capacitor at various temperatures showing kink effect in the flat band region.

The density of holes grows in the interface of the accumulation zone (1), and the measured capacitance approaches the oxide capacitance. Because the fermi level sits between the acceptor level and the valence band at low temperatures, the impurities in the substrate are significantly non ionized. In the case of flat bands (region (2)), no holes collected near the surface, and the density of the ionized dopants is a relatively small fraction of the total impurity concentration. The debye’s length value is extremely high and the capacitance of flat bands region diminishes. This is because the density of the ionized impurities represents a small fraction of the active dopant concentration. The increase of the gate voltage causes the ionization of additional dopants, which promotes the spreading of the depletion layer by contributing to the capacitive response. As more dopants are ionized at the interface, the overall capacity rises to a maximum (region (3)), where it remains. A C-V curve’s depletion regime for higher voltages exhibits a capacity decline that follows the typical shape of MOS characteristics.

3.4.1 Incomplete Ionization Model To understand the experimental results of the Capacitance-Voltage (C-V), we have developed a new formulation of the total capacitance of the semiconductor by incorporating the phenomenon of incomplete ionization. We have assumed that the substrate is doped with NA atoms of indium/

50  Nanodevices for Integrated Circuit Design cm3 and that the doping is Gaussian. The usual boundary conditions have been chosen for the potential and the electric field at x = 0 and at x = xd. The ionization rate of indium at any depth x is given by:

N A- (x ) =



NA 1 + g A χ exp [ − βϕ (x )]

(3.1)

With gA = 4 (degeneracy factor for the acceptor level) and

E -E  χ = exp  A0 F   kBT 



(3.2)

Is determined by the neutrality condition in the substrate:

NA = p0 − n0 1 + g Aχ



With n0 and p0 are given by:

1 E -E  exp  A0 C 0  χ  kBT 

(3.3)

E -E  p0 = NV χ exp  V 0 A0   kBT 

(3.4)

n0 = N C





With EA0, EC0, EV0, n0, and p0 are the energy levels and carrier concentrations in the neutral region of the substrate. By taking account of equation (3.1) and making a conventional calculation, the charge in the semiconductor is obtained:

QSC(φs) = Y.Z

(3.5)

With Y = −Sign(ϕ s ) 2ε s kBTN A And = Z

βϕs + ln

p 1 + g A χ exp(−βϕs ) n0  + exp(βϕs ) −1 + 0 exp(−βϕs )−1 NA  NA 1+ g Aχ

Field Effect Transistors  51 The capacity of the semiconductor is deduced from the preceding equation and is written as:



Csc (ϕ s ) =

−βY 2Z

g χ exp(− βϕs ) n p   ⋅ 1 − A + 0 exp(βϕs ) − 0 exp(− βϕs ) 1 + g χ exp ( − βϕ ) N N A s A A  

(3.6)

On the other hand, assuming that VFB = 0 V for simplification, we have: QSC (ϕ s ) = −Cox (VG − ϕs ) Where VG and Cox are the gate voltage and the oxide capacitance respectively. The total capacitance of the MOS device is given by:



1 1 1 = + C Cox CSC

(3.7)

3.4.2 Simulation of the Kink Effect in MOS Capacitor Figure 3.6 shows the flowchart of kink effect in MOS Capacitor Simulation Parameters Optimization Algorithm. We started by defining device geometrical (thickness and dimensions) and technological parameters (doping). Then, we called incomplete ionization model and we performed optimization routine for the three main parameters of the trap inside the device which are activation energy, trap density and capture cross section. After that, we compare simulation and experimental results till we found the best parameters that describe well the kink effect. In Figure 3.7 (a), we simulated the capacitance-voltage curves of the MOS capacitor for various temperatures in the absence of interface states. We note that whatever the temperature the C-V curves are quasi-identical and one notes well the absence in this case of the kink effect. Taking into account the interface states in the simulation of the C-V curves, we obtain the curves of Figure 3.7 (b) where it is clearly seen that an increase in the capacitance (i.e., increase in the charge) for a bias voltage around -1 V which is the kink voltage. We also note that this variation in capacity is a function of temperature. We can therefore deduce that this effect is related to a thermally activated phenomenon. Indeed, the curves of Figure 3.7 (b) are obtained by introducing into the calculation of the capacitance, given by equation (3.7), a trap level located at 0.16 eV above of the valence band with a density NA between 1011 and 1012 cm-3 and with an effective cross-section of 7.10-13 cm2. It is therefore

52  Nanodevices for Integrated Circuit Design Start Define device structure and parameters

Import Incomplete Ionization Model

Optimize Activation Energy?

Optimize Trap Density?

Optimize Capture Cross Section?

Plot C-V characteristics of the device showing kink effect

No

Comparison of simulation and experimental data

Does all parameters optimized? Yes End

Figure 3.6  Flowchart of kink effect in MOS capacitor simulation parameters optimization algorithm.

legitimate to associate this kink effect with the interface defects and in particular the trap associated with the Indium. The kink effect is a universal phenomenon for almost all field effect transistors and also in MOS structures. On the basis of the literature, Jie et al. [24] have shown by simulation that the kink effect is present in MOS

Field Effect Transistors  53 400

T = 100 K T = 120 K T = 140 K T = 160 K T = 180 K T = 200 K T = 220 K T = 240 K T = 260 K T = 280 K T = 300 K

(a)

350

C (pF)

300 250 200 150 100 50 0 -3

VFB

-2

-1

400

C (pF)

C (pF)

300

200 150 100 50 0 -3

2

3

4

(b)

350

250

0 1 V (V)

T = 80 K T = 100 K T = 120 K T = 140 K T = 160 K T = 180 K T = 200 K T = 220 K T = 240 K T = 260 K T = 280 K T = 300 K

-2

200

150 -1.2

-1.1

-1.0

-0.9

-0.8

V (V)

-1

0 1 V (V)

2

3

4

Figure 3.7  Simulation of C-V characteristics at different temperatures of MOS capacitor (a) without traps and (b) with traps showing the kink effect.

capacitor’s C-V characteristics by varying the dopant and the concentration of the dopant.

3.4.2.1 Effect of the Variation of Activation Energy We have chosen a single temperature to see the effect of the activation energy value on the appearance of the kink effect in the flat band regime. We have chosen the following parameters in our simulations: The oxide thickness is 3.8 nm, the concentration of the n-type poly-silicon is 1020 cm-3 and the p-type substrate concentration is 5.1017 cm-3 and is retrograde (Gaussian doping). The results of the simulation show a kink effect whose amplitude decreases by increasing the activation energy as shown in Figure 3.8. This can be explained by the fact that the lower the activation energy the closer the level is to the valence band and therefore the carrier exchange

54  Nanodevices for Integrated Circuit Design 400

T = 100 K

350

Ea = 110 meV Ea = 120 meV Ea = 130 meV Ea = 140 meV Ea = 150 meV Ea = 160 meV Ea = 165 meV Ea = 170 meV

C (pF)

300 250 200 150 100 50 -3

-2

-1

0 V (V)

1

2

3

Figure 3.8  Effect of activation energy on the amplitude of kink at T = 100 K.

is greater, which leads to an increase in the charges and therefore in the capacitance.

3.4.2.2 Effect of the Variation of Traps Density Figure 3.9 shows the simulated C-V curves for a temperature of 100 K, a trap activation energy of 0.16 eV, an effective capture cross section of 7.10-13 cm2 for trap concentrations between 1011 and 1013 cm-3. We see in this Figure that for high concentrations (greater than 1012cm-3) the kink effect becomes very large, of large amplitude and moves towards the high voltages in absolute value towards the accumulation region. 400

T = 100 K

350

-3

cm 11

-3

11

-3

12

-3

12

-3

13

-3

4.10 cm

300 C (pF)

11

10

8.10 cm 12 -3 1.10 cm

250

2.10 cm

200

5.10 cm

150

1.10 cm Kink Effect

100 50 -3

-2

-1 0 Vg (V)

1

2

Figure 3.9  Effect of density of traps on the displacement of kink effect at T = 100 K.

Field Effect Transistors  55 For concentrations below 1012cm-3, the amplitude of the kink effect decreases and is centered around the kink voltage equal to -1 V. This may be due to an exchange of holes between the accumulation zone at Oxidesemiconductor interface and the trap level considered.

3.4.2.3 Effect of the Variation of Capture Cross Section In Figure 3.10, we plotted the simulated C-V curves for a temperature of 100 K and taking into account an activation energy of the trap of 0.16 eV, a trap concentration equal to 1012 cm-3, and for capture cross sections ranging from 10-10 to 10-14 cm2. We find that for values of the weak cross section, the kink effect disappears. However, for large values (10-11 cm2) the kink effect saturates which proves that for such values of the capture cross section any carrier will be trapped by the defect. This proves once again that the kink effect is intimately related to the defects in occurrence the level introduced by the Indium. 400

T = 100 K

350

cm2

-11

cm2

σp = 10

300 C (pF)

-10

σp = 10

cm2

-12

σp = 10

250

σp = 8 . 10 cm2

200

σp = 6 . 10 cm2

-13 -13

σp = 4 . 10 cm2 -13

150

σp = 2 . 10 cm2 -13

100

-13

cm2

-14

cm2

σp = 10

50

σp = 10

-3

-2

-1 0 Vg (V)

1

2

Figure 3.10  C-V at T = 100 K showing the effect of the capture cross section of indium trap on the amplitude of kink.

3.4.3 Comparison Between Experimental and Simulation Results 3.4.3.1 Hysteresis Effect on the C-V Characteristics In this section, we will investigate the C-V curves of MOS capacitors as a function of temperature as shown in Figure 3.11. Experimentally we have

56  Nanodevices for Integrated Circuit Design 350 (a)

T = 80 K T = 100 K T = 120 K T = 140 K T = 160 K T = 180 K T = 200 K T = 220 K T = 240 K T = 260 K T = 280 K T = 300 K

300

C (pF)

250 200 150 100 50 0 –2

–1

0

1

2

V (V)

3

4

5

350 (b)

T = 80 K

300

C (pF)

300

C (pF)

250

200

Down 100 (∆S)

200

Up

0 -2

150

Hysteresis Area (∆S)

-1

0

1

2 V (V)

100 50 0 –2

–1

0

1

2

3

3

4

T = 300 K T = 250 K T = 200 K T = 150 K T = 100 K T = 80 K

4

V (V)

Figure 3.11  C-V curves without hysteresis (a) of MOS capacitors as a function of temperature showing kink effect at -1V and with Hysteresis (b).

5

5

Field Effect Transistors  57 shown a hysteresis in the limit region post kink between depletion and inversion regime. A counter-clockwise hysteresis is shown in the above Figure and that co-appears with the kink effect and it decreases when rising temperatures to 300 K.

3.4.3.2 Proof of the Origin of Kink Effect In order to determine the origin of the kink effect in C-V of MOS Capacitor and in I-V output characteristics in MOSFET transistor studied earlier by Fargi et al. [20], we have compared experimental and simulation results of excess capacitance and current in Figure 3.12. It is clearly shown that the variation of capacitance (ΔC) and current (ΔI) have a maximum at temperatures around 100 to 130 K which is the range of appearance of the Indium defect previously detected by several techniques such as admittance spectroscopy and DLTS. In Figure 3.13, we have shown the variation of hysteresis area (ΔS) in the C-V characteristics as a function of temperature. It is clear that we have the same behavior as for ΔC and ΔI as the hysteresis co-appear with kink effect.

C-V Experiment C-V Simulation Vg = 0.7 V Vg = 1 V Vg = 1.2 V Vg = 1.4 V Vg = 1.6 V

∆ C (pF)

30

20

0,45 0,40 0,35 0,30 0,25 0,20

10

∆ I (mA)

40

0,15 0,10

0 50

0,05 100

150

200 T (K)

250

300

Figure 3.12  Measure of ΔC (experimental and simulation) from C-V characteristics of MOS capacitor and ΔI from I-V characteristics of MOSFET transistor as a function of temperature.

58  Nanodevices for Integrated Circuit Design 25

Hysteresis Area

∆ S (a. u)

20

15

10

5

0 50

100

150

200 T (K)

250

300

350

Figure 3.13  Plot of hysteresis area from C-V characteristics (Figure 3.11(b)) as a function of temperature.

3.5 Conclusion In this chapter, we studied the importance of kink effect in FET devices and reported its different models used in literature like impact ionization and traps and interface states. Using incomplete ionization model, we analyzed kink effect in MOS capacitor. We have shown that the kink effect in the C-V characteristics of the MOS Capacitor studied is due to an Indium defect whose activation energy is 0.16 eV and this by optimizing various parameters of the trap such as the activation energy, the trap density and the capture cross section while being based on the incomplete ionization of the dopant. Our simulations thus prove that indium, introduced as a dopant in silicon, plays the role of a defect which causes the kink effect.

References 1. Kumar, V. and Rana, A.K., Investigation of self-heating effects in ultrathin FDSOI MOSFETS. IOP Conf. Ser.: Mater. Sci. Eng., 1225, 1, 012013, 2022, https://doi.org/10.1088/1757-899X/1225/1/012013. 2. Narayanan, M., Al-Nashash, H., Mazhari, B., Pal, D., Chandra, M., Analysis of kink reduction in SOI MOSFET using selective back oxide structure. Act. Passive Electron. Compon., 2012, 565827, 2012, https://doi. org/10.1155/2012/565827.

Field Effect Transistors  59 3. Narayanan, M.R., Al-Nashash, H., Mazhari, B., Pal, D., Kink reduction using selective back oxide structure. 2009 International Conference on Microelectronics - ICM, 2009, 19-22 Dec. 2009. 4. Sarajlic, M. and Ramovic, R., Analytical modeling of the triggering drain voltage at the onset of the kink effect for PD SOI NMOS. 2006 25th International Conference on Microelectronics, 2006. 5. Kaushik, J.K., Balakrishnan, V.R., Panwar, B.S., Muralidharan, R., On the origin of kink effect in current–voltage characteristics of AlGaN/GaN high electron mobility transistors. IEEE Trans. Electron Devices, 60, 10, 3351– 3357, 2013, https://doi.org/10.1109/TED.2013.2279158. 6. Incandela, R.M., Song, L., Homulle, H., Charbon, E., Vladimirescu, A., Sebastiano, F., Characterization and compact modeling of nanometer CMOS transistors at deep-cryogenic temperatures. IEEE J. Electron Devices Soc., 6, 996–1006, 2018, https://doi.org/10.1109/JEDS.2018.2821763. 7. Jazaeri, F., Beckers, A., Tajalli, A., Sallese, J.M., A review on quantum computing: From qubits to front-end electronics and cryogenic MOSFET physics. 2019 MIXDES - 26th International Conference “Mixed Design of Integrated Circuits and Systems, 27-29 June 2019, 2019. 8. Hafez, I.M., Ghibaudo, G., Balestra, F., Reduction of kink effect in short-channel MOS transistors. IEEE Electron Device Lett., 11, 3, 120–122, 1990, https:// doi.org/10.1109/55.46953. 9. Hafez, I.M., Ghibaudo, G., Balestra, F., Analysis of the kink effect in MOS transistors. IEEE Trans. Electron Devices, 37, 3, 818–821, 1990, https://doi. org/10.1109/16.47796. 10. Haruyama, J., Ohno, Y., Katano, H., Nashimoto, Y., Kink effect related to the self-side-gating effect in GaAs MESFET’s. IEEE Trans. Electron Devices, 41, 10, 1873–1875, 1994, https://doi.org/10.1109/16.324603. 11. Horio, K. and Usami, K., Analysis of kink-related backgating effect in GaAs MESFET. IEEE Electron Device Lett., 16, 6, 277–279, 1995, https://doi. org/10.1109/55.790734. 12. Hori, Y. and Kuzuhara, M., Improved model for kink effect in AlGaAs/ InGaAs heterojunction FET’s. IEEE Trans. Electron Devices, 41, 12, 2262– 2267, 1994, https://doi.org/10.1109/16.337437. 13. Georgescu, B., Souifi, A., Guillot, G., Py, M.A., Post, G., Study of the kink effect in AlInAs/GaInAs/InP composite channel HFETs [journal article]. J. Mater. Sci.: Mater. Electron., 10, 5, 419–423, 1999, https://doi. org/10.1023/a:1008966011311. 14. Haruyama, J., Negishi, H., Nishimura, Y., Nashimoto, Y., Substrate-related kink effects with a strong light-sensitivity in AlGaAs/InGaAs PHEMT. IEEE Trans. Electron Devices, 44, 1, 25–33, 1997, https://doi.org/10.1109/16.554787. 15. Somerville, M.H., Alamo, J.A.D., Hoke, W., Direct correlation between impact ionization and the kink effect in InAlAs/InGaAs HEMTs. IEEE Electron Device Lett., 17, 10, 473–475, 1996, https://doi.org/10.1109/55.537079.

60  Nanodevices for Integrated Circuit Design 16. Somerville, M.H., Ernst, A., Alamo, J.A.D., A physical model for the kink effect in InAlAs/InGaAs HEMTs. IEEE Trans. Electron Devices, 47, 5, 922– 930, 2000, https://doi.org/10.1109/16.841222. 17. Lee, Y.T., Woo, D.S., Lee, J.D., Park, B.G., Impact of incomplete ionization on indium doped buried channel pMOSFETs. J. Korean Phys. Soc., 33, S200– S203, 1998. 18. Canali, C., Paccagnella, A., Pisoni, P., Tedesco, C., Telaroli, P., Zanoni, E., Impact ionization phenomena in AlGaAs/GaAs HEMTs. IEEE Trans. Electron Devices, 38, 11, 2571–2573, 1991, https://doi.org/10.1109/16.97428. 19. Zimmer, T., Ouro Bodi, D., Dumas, J.M., Labat, N., Touboul, A., Danto, Y., Kink effect in HEMT structures: A trap-related semi-quantitative model and an empirical approach for spice simulation. SolidState Electron., 35, 10, 1543–1548, 1992, https://doi.org/http://dx.doi. org/10.1016/0038-1101(92)90096-U. 20. Fargi, A., Hizem, N., Kalboussi, A., Investigation of the kink effect in indium–doped silicon for sub 100 nm N channel MOSFET technology. Int. J. Nanotechnol., 10, 5-7, 523–532, 2013, https://doi.org/http://dx.doi. org/10.1504/IJNT.2013.053521. 21. Fargi, A., Hizem, N., Kalboussi, A., Souifi, A., Electrical analysis of indium deep levels effects on kink phenomena of silicon NMOSFETs. World J. Nano Sci. Eng., 4, 1, 7–15, 2014, https://doi.org/http://dx.doi.org/10.4236/ wjnse.2014.41002. 22. Hizem, N., Fargi, A., Kalboussi, A., Souifi, A., Analysis of the relationship between the kink effect and the indium levels in MOS transistors. Mater. Sci. Eng.: B, 178, 20, 1458–1463, 2013. 23. Pirovano, A., Lacaita, A.L., Pacelli, A., Benvenuti, A., Novel low-temperature CV technique for MOS doping profile determination near the Si/SiO 2 interface. IEEE Trans. Electron Devices, 48, 4, 750–757, 2001, https://doi.org/ http://dx.doi.org/10.1109/16.915719. 24. Jie, B. and Sah, C., MOS capacitance-voltage characteristics from electron-trapping at dopant donor impurity. J. Semicond., 32, 4, 041001, 2011, http://stacks.iop.org/1674-4926/32/i=4/a=041001.

4 Next Generation Molybdenum Disulfide FET: Its Properties, Evaluation, and Its Applications Vydha Pradeep Kumar1 and Deepak Kumar Panda2* Dept. of Sense, VIT-AP University, Near Vijayawada, India Department of ECE, Amrita School of Engineering Amaravati, Amrita Vishwa Vidyapeetham, Andhra Pradesh, India 1

2

Abstract

In this Chapter, we describe the fundamental concepts of 2D materials and their Evaluations along with a brief overview of the Molybdenum disulfide material, its properties, and applications. We also presented, in brief, the different fabrication techniques in the evolution of MoS2 material and their types. Molybdenum disulfide is evaluated as an alternative to Graphene and silicon material in the semiconductor industry due to its variable band gaps and high conductivity in nature. Because of its unique properties, it is proven as a promising material in the applications of nano-electronic devices, Opto-electrical bio-sensors applications, chemical bio-sensors, Terahertz areas, and Energy storage applications. In this paper, we designed a MOSFET with MoS2 material as a channel and compared experimentally the drain current variation between Graphene and MoS2 material used in MOSFET transistors and also compared conventional MOSFET characteristics with MoS2FET transistor characteristics. We also presented the Bio-Sensors-based MoS2FET transistor and proved it has high drive current conductivity and high sensitivity in nature, needed for Bio-Sensor applications. Finally, we related the performance of other 2D materials in comparison to MoS2 (molybdenum disulfide) material. Keywords:  Bio-sensor, graphene, molybdenum disulfide, nano-electrical devices, opto-electrical properties, sensitivity, transition metal dichalcogenides (TMDCs) *Corresponding author: [email protected] Suman Lata Tripathi, Abhishek Kumar, K. Srinivasa Rao, and Prasantha R. Mudimela (eds.) Nanodevices for Integrated Circuit Design, (61–82) © 2023 Scrivener Publishing LLC

61

62  Nanodevices for Integrated Circuit Design

4.1 Introduction of Two-Dimensional Materials 2D Materials are having electrons moving freely in two-dimensional planes and are restricted in the third dimension plane, controlled by Quantum mechanics. These materials come under the class of Nano-material defined by the size of the material, and its bulk properties [1, 2]. Nanomaterials are particles that have their size in the 1–100 nm range and are defined by the number of nanoscopic dimensions they possess as shown below in Figure 4.1 [3]. If the Electron moves in two dimensions and is confined in one direction then it is called 2-dimensional material. Example: TMD materials. If the Electron moves in 1-dimension and is restricted in the other two directions then it is called 1Dimensional material. Example: Electrons in Nano-Wire. If all three directions are confined then it is Zero-Dimensional material. Example: Quantum dot. 2D materials are classified into two types: Single Element 2D material (Ex: Graphene, Black Phosphorus (BP), Single layer Germanium, etc.) Compound 2D materials (Ex: Hexagonal Boron Nitride (h-BN), TMDCs, III-V Group elements, compound semiconductors, etc.) Transition metal dichalcogenide  (TMD  or  TMDC) are the semiconductors having a chemical composition of type MX2 (M = Transition metal atom (such as Molybdenum (Mo) or Tungsten (W), etc.) and X = Chalcogen atom (such as Sulfur (S), Selenium (Se) or Tellurium (Te), etc.)), one layer of M atom will place in between double layers of X atoms. TMDC materials are having the finest molecular sensible capability because of their covalent bond between the atom and chalcogenides and their physical and

kx

kx nz

nz (a)

nz

ny

ky

(b)

nx ny (c)

Figure 4.1  (a) Two-dimensional electron; (b) One-dimensional electron; (c) Zerodimensional electron.

Next-Generation Molybdenum Disulfide  63

(a)

(b)

Figure 4.2  (a) Molybdenum disulfide (MoS2); (b) Tungsten telluride (WTe2).

chemical features like high absorption coefficient, semiconducting property, variable band gaps, and high surface-volume ratio [4, 5]. TDMCs can take various crystal structures as 1T, 2H, and 3R belonging to different groups respectively. The first numeral represents the figure of layers, and the alphabet denotes crystallographic structure. The letter ’T’ is trigonal, ’H’ is hexagonal, and ’R’ is rhombohedral layout. 2H-phase is the utmost commonly used polytype that produces equivalent high conducting characteristics such as those retained by MoS2, MoTe2, WSe2, and MoSe2. These semiconductors are having a wide range of bandgaps (The bulk form layer has an Indirect bandgap and the mono-layer has a direct bandgap) because of which it is used in optoelectronics for visible spectrum range. They have Charge mobilities ranging 100-1000 cm2V-1s-1 and promising as the best choice for two-dimensional transistors. The metallic 1T phase is the other stabled polytype of Tungsten telluride (WTe2) as represented in Figure 4.2 [6]. TMD materials are bonded by weak Van Dallas forces between the layers that help in the easy breaking of lattice mismatch between the layers to form vertical heterostructures, which is one of the advantages of TMD materials. Since the lattice constants are very close, they allow for different building blocks in vertical, lateral, and alloy hetero-structured forms. The TMDC hetero-structure layered materials with wide energy band-gaps are used in different applications of photocatalysts, photodetectors, and field-effect transistors [7, 8]. Two-Dimensional Materials have unique characteristics like: (i) (ii) (iii) (iv) (v)

Discrete Energy Level. Forbidden Energy Gap. Enhanced Energy Bad gap. Quasi–Two Dimensional State. Strongly influenced by surface and interface effects.

64  Nanodevices for Integrated Circuit Design (vi) High Mechanical Strength. (vii) Attractive Charge Transport. (viii) High carrier mobility of up to 105 cm2 V−1 s−1 The complete manuscript is arranged in this way. Section 4.2 explains about Evaluation of 2D materials. In section 4.3, the overview of MoS2 material is described. In section 4.4, different Properties of MoS2 materials are presented. In section 4.5, the different fabrication techniques used in the evolution of 2D materials are focused. In Section 4.6, we explained the applications in detail. In Section 4.7, we compared the performance analysis of other 2D materials with MoS2, and finally, in Section 4.8, we conclude with the conclusion of the manuscript subsequent with references.

4.2 Evaluation of 2D-Materials The invention of the first transistor in 1947 at Bell Laboratory was followed by the integrated circuit era. The scaling of MOSFET to improve its performance is been reduced by more than two orders of magnitude according to Moore’s law following the International Technology Roadmap of Semiconductors. But when the channel length decreases equivalent to the widths of depletion layers of source and drain, the mobility degradation occurs in the channel prompting different types of effects in the device, which degrade the device performance and these effects are called short channel effects (SCEs). To overcome SCEs, the gate oxide thickness is decreased but it then reduces the Ion/Ioff current ratio, and the gate leakage current increases. To overwhelm all these effects with high gate control and high Ion/Ioff current ratio, SiO2 in MOSFET is replaced with 2Dmaterials. Initially, Graphene is used as a gate dielectric material which is a highly conductive semi-metal with high tensile strength and an excellent conductor of heat. Despite all these characteristics, Graphene was limited in the use of electronic applications because of Zero-bandgap. This created interest in studying different 2D materials possessing bandgaps and the most studied material is MoS2 with wide bandgaps compared to graphene [9, 10]. Figure 4.3 shows the I-V characteristics of 2D materials Graphene and Molybdenum disulfide. Because Bandgap exists in MoS2 it has a high conductivity ratio in comparison to Graphene due to its Zero-bandgap. Figure 4.4 illustrates the I-V characteristics of conventional MOSFET at different Vd and Vg values. Similarly, Figure 4.5 illustrates the I-V

Next-Generation Molybdenum Disulfide  65 characteristics of MoS2 in comparison to silicon used in conventional MOSFET. It is observed that MoS2 conducts for fewer supply voltage ranges and gives better conductivity for different drain and gate voltages because of its properties and band gap characteristics [11–13]. Drain Current for MoS2 & Graphene

0.0007 0.0006

Drain Current (A)

0.0005 Graphene MoS2

0.0004 0.0003 0.0002 0.0001 0.0000

0.0

0.1

0.2

0.3 0.4 0.5 Drain Voltage (V)

0.6

0.7

0.8

Figure 4.3  Id-Vd characteristics of graphene and MoS2.

Id vs Vd - MOSFET

1.6 Vg(2V) Vg(3V) Vg(4V) Vg(5V)

1.4 1.2

1.4

Id(uA)

Id(uA)

0.8

1.0 0.8

0.6

0.6

0.4

0.4

0.2

0.2 0

1

Vd(1V) Vd(2V) Vd(3V) Vd(4V)

1.2

1.0

0.0

Id vs Vg - MOSFET

1.6

2 Vd(V)

(a)

3

4

0.0

0

1

2

3 Vg(V)

4

5

(b)

Figure 4.4  (a) Id-Vd of MOSFET for different Vg. (b) Id-Vg of MOSFET for different Vd.

66  Nanodevices for Integrated Circuit Design Drain Current for MoS2 and Silicon

Drain Current (A)

0.0010

0.0008

0.0008 0.0009 0.0004

With Respect various Gate Voltages MoS2 for Vg=2V MoS2 for Vg=1V Si for Vg=1V Si for Vg=2V

0.0006 0.0004 0.0002

0.0002 0.0000 0.0

0.0010

MoS2 for Vd=2V MoS2 for Vd=1V Si for Vd=1V Si for Vd=2V

Drain Current (A)

0.0012

0.5

1.0 1.5 2.0 Gate Voltage (V)

2.5

(a)

3.0

0.0000 0.0

0.2

0.4 0.6 Drain Voltage (V)

0.8

1.0

(b)

Figure 4.5  (a) Id-Vg of MoS2 for different Vd. (b) Id-Vd of MoS2 for different Vg.

4.3 Overview of MoS2 Molybdenum disulfide (MoS2), fabrication using the scotch tapping method and chemical vapor deposition (CVD) technique, are used for many decades because of their properties and methods used effectively in optoelectrical applications, nanostructured device applications, and other architectural designs. MoS2 high driving current, low leakage current, low tunneling current, high operating frequency (THz), thermal conductivity at normal temperature as 131 Wm-1 k-1, better on/off current ratio (108), mobility of 200cm2/vs-1, and subthreshold swing as low as 65 mV/dec, all these characteristics determine the ability of MoS2 to use in electronics with high stability compare to silicon transistors. MoS2 in the bulked layer has a bandgap of 1.29eV and mono-layered has a bandgap of 1.9eV. Indirect bandgap having improved optical characteristics is used widely in optoelectronic applications, whereas direct band gap for high mobility applications because of higher generation/recombination rate of electrons and holes in the bandgap. MoS2 having a high refractive index is used in optoelectronics and with a high chemical coating is used in solid lubricants.

4.3.1 Why MoS2 MoS2 materials look like rock crystals with vertically stacked planes having covalently bounded S-Mo-S atoms that are tightly packed in a hexagonal pattern with Vander-Waals interactions holding the adjacent planes closely as shown in Figure 4.6 [14]. Using scotch tapping, mass spectrometry, and

Next-Generation Molybdenum Disulfide  67

Figure 4.6  Layer form of MoS2, Molybdenum blue in color and Sulfur yellow in color.

chemical vapor deposition (CVD), good quality single thin films of MoS2 of 0.65nm thickness may be created. MoS2 is a semiconductor that has a wide variety of bandgaps (direct and indirect), which is an important characteristic for substituting graphene in the field-effect transistor.

4.3.2 MoS2 Structured Design Molybdenum disulfide (MoS2) crystalline structured design has the arrangement of “S” molecules in the hexagonal plane on both sides of “Mo” molecules as shown in Figure 4.7 [15]. The S and Mo atoms are covalently bonded, forming a triple plane stack; however, the layers that are close to each other with weak Vander-Waal force are separated mechanically to form MoS2 2-dimensional sheets.

z

y x

y z

x

Figure 4.7  Crystalline structure of molybdenum disulfide monolayer.

68  Nanodevices for Integrated Circuit Design

4.4 Properties of MoS2 MoS2 material exists as a metal called molybdenite and is one of the best materials with a unique structure, and unique properties. The structural blocks of Molybdenum disulfide are important in improving the productivity and properties of a material [16].

4.4.1 Bulk Characteristics Generally, MoS2 existence will be as a mineral and appears as a shiny dark solid in its bulk form. As MoS2 has weak interlayer interactions, sheets can slide on each other easily which is used in lubricants. The bulk form of MoS2 semiconductor is restricted in the application of the opto-electronics industry due to its less bandgap value (1.29eV).

4.4.2 Electrical and Optical Characteristics MoS2 also exists in a single plane by removing confined electrons and interlayer interactions lead to increased energy in its bandgap to 1.89eV defined as direct bandgap. An increase of 10-25% of photoluminescence incident light with more visible energy is seen in a single-layer structure.

4.4.2.1 BandGap The bandgap of a material can be tuned by adding strain to the structure. By introducing 1% of biaxial compressive strain in trilayer MoS2, a 300meV increased energy bandgap is observed. 2Deminonal semiconductor structured material is changed to a metallic structure by reducing bandgap to zero, using the Vertical electrical field method for bandgap, shown in Figure 4.8 [15]. Monolayer

4

4

2

2

E – Ef (eV)

E – Ef (eV)

Bulk

0

–2

0

–2

–4

–4 Γ

M

K

Γ

Γ

Figure 4.8  Band diagrams of bulk and mono-layer MoS2.

M

K

Γ

Next-Generation Molybdenum Disulfide  69

4.4.2.2 Photoluminescence Spectra MoS2 Monolayer photoluminescence spectra are explained with twoexcitonic peaks, an exciton having ~1.92eV, and B exciton having ~2.08eV. These peaks in the valence band get split, near the K-point because of spinning orbit coupling that empowers two optically active transitions, due to which high binding energy of the excitons with 500 meV is achieved. Therefore, MoS2 materials are more stable at high temperatures.

4.4.2.3 Injection of Electrons By injecting more electrons into MoS2, using the chemical or electrical doping method, the trions can be formed. Trions are charged excitons consisting of 1-hole and 2-electrons occurring in photoluminescence spectra as a peak form at ~40meV. These Trions help in defining the optical characteristics of MoS2 film at room temperature.

4.4.2.4 Transistor MoS2 transistor generally behaves like N-type transistor with 350 cm2 v-1 s-1 of carrier mobilities. For FET transistors, MoS2 exhibits a high Ion/Ioff current ratio (~108) which makes the logic circuits more effective and for high switching characteristics.

4.4.3 Mechanical Properties Molybdenum disulfide in a monolayered structure having a radius of 0.75mm is used in thin-film FET transistors, are more flexible in nature. They have stiffness the same as steel, with more breaking strength equal to polydimethylsiloxane (PDMS) and polyimide (PI), and promising them suitable for electronic applications with thermal conductivity of 35 Wm-1 K-1.

4.4.3.1 Valleytronics Valleytronics in semiconductors means technology similar to electronics but using control over the valley degree of freedom i.e., electronics uses electrons (electric charge) to retain and move data whereas Spintronics uses the spin of electronics. MoS2 electronics band structure has maxima valence-band energy and minima conduction-band at Brillouin zone

70  Nanodevices for Integrated Circuit Design (K and K`), a similar energy gap is owned by these valleys but is discrete in momentum space when comes to position.

4.4.3.2 Optical Transitions MoS2 semiconductor for optical transition with valleytronics needs angular momentum change in both K and K` points. So, excitons with circular polarization are excited into the valley like, K` region is excited by the lefthanded (σ-) and the K region is excited by the right-handed (σ+), shown in Figure 4.9 [14].

4.4.3.3 Spin-Orbit Valence Band

Energy

For every valley, at spin-orbit split valence band, they possess opposite signs of K and K` points. For instance, the A-exciton of K-valley will have a spin-down hole and spin-up electron, while for B-exciton it has a spindown electron and spin-up hole. This is the opposite for A & B exciton with respect to K`-valley, shown in Table 4.1 [14]. Conduction Band

K+ Wave vector

K–

K+ σ–

σ+ σ+

Splitting spin-orbit

σ–

K+

K–

Splitting Spin-orbit

Valence Band

Figure 4.9  Optical selection rules and spin splitting.

Table 4.1  Shows the valleytronics spinorbit orientations. σ+ (K -valley)

σ+ (K’-valley)

EA

e-

h

e-

EB

e-

h

e- h

h

Next-Generation Molybdenum Disulfide  71

4.5 Fabrication of MoS2 Various methods are used in the fabrication of monolayer MoS2 films. Here few commonly used techniques are described.

4.5.1 Mechanical Exfoliation This process is also known as the Scotch-tapping technique. In this method when a gluey tape is applied to a bulk crystalline layer, it can result to a thin layer of crystal once when we peel the sticky tape because of higher mutual adhesion compared to inter-layer adhesion. The process of pasting and cracking will be a repetitive process until high-quality monolayer MoS2 film is formed. Later this single monolayer can be converted to a substrate using PDMS stamp [17].

4.5.2 Intercalation In this method, bulk crystal layers of MoS2 are dipped in a liquid form of lithium ions (n-type material-hexane) to which H2O is added, such that Table 4.2  Comparison of structural level coordinates between different MoS2 structural polytypes. 1T

2H

3R

Structure Coordination

Octahedral

Trigonal Prismatic

Trigonal Prismatic

Lattice parameters

a = 5.60 A, c = 5.99 A

a = 3.15 A, c = 12.30 A

a = 3.17 Å, c = 18.38 A

Property

Paramagnetic and Metallic

Semiconducting

Semiconducting

Electrical conductivity

105 times higher than 2H phase

Low (~0.1 S/m)

Low (~0.1 S/m)

Absorption peaks

No peaks at 604 nm and 667 nm

Showed peaks at 604 nm and 667 nm

Showed peaks at 604 nm and 667 nm

Common applications

Intercalation in Chemistry

Dry lubricants

Dry lubricants and non-linear optical devices

72  Nanodevices for Integrated Circuit Design the lithium ions react with H2O and get converted to hydrogen solution. This solution pushes the layers separately to give a high-yield metallic 1T structure of monolayer mos2. Later, the 2H structure can be obtained from the 1T structure using the thermal annealing method, shown in Table 4.2 [18].

4.5.3 Solvent Exfoliation In an Organic solvent, sonication of bulk crystals is done by breaking them into thin layers in terms of their thickness and sizes. By this, a surfaceactive region is obtained for ending the process of restacking the layers. By this technique, we get a high yield of a thin-film monolayer.

4.5.4 Chemical Vapor Deposition (CVD) Mechanical exfoliation is not a prominent method in the field of optoelectronics, though it has high crystalline monolayers. To produce highquality films of MoS2 for more applications, the Chemical Vapor deposition method is used. To make MoS2 films, molybdenum trioxide is annealed with sulphur at a high temperature (1000°C).

4.6 Applications of MoS2 4.6.1 Solid Lubricants MoS2 in its liquid lubricant form for long storage application is very difficult because under radiation environmental conditions these liquid lubricants get decay and evaporated easily. So, we use MoS2 in solid lubricant form in the application of orbital-moving mechanisms. Antennas, telescopes, solar cells, satellites, etc., are examples of space-moving systems where the system sustain for a longer period with small service [19].

4.6.2 Electronic Applications MoS2 can be used effectively and efficiently in both electronics and logic device applications because of its variable bandgap. Molybdenum disulfide is a semiconductor because of high conduction and is used in Low power electronic devices and FETs because of 2-Dimensioanl structure which has control over materials electrostatic nature.

Next-Generation Molybdenum Disulfide  73

4.6.3 Field-Effect Transistor Field Effect Transistor (FET) in semiconductor technology is the elementary element having benefits like less cost-effect, less power-consumption, and high switching characteristics. In over-coming short channel effects (SCEs) in developing nanosized devices, a thin channel material with thin gate oxide is highly recommended in the device design. For this, monolayer Molybdenum disulfide is a suitable material [20].

4.6.4 Switching Transistor MoS2 monolayer switchable based transistor was first developed by Radisavljevic with 6.5 A˚ of channel thickness having 30nm thick layer of Hfo2 on Sio2 substrate working as Top-gated dielectric layer. It has Ion/Ioff current ratio of 108 at room temperature with subthreshold slope of 74mV/ dec due to which MoS2 is a promising, flexible device used for low standby power integrated circuits applications.

4.6.5 Nano-Structures A 2-Dimensional Molybdenum disulfide Nano-sized sheets, used for biosensor application are prepared using electro-chemical phenomenon and the sheets are used for electrodes as materials in biosensor-based devices. These sheets with direct bandgap are also having high fluorescence in the visible spectrum that makes Molybdenum a suitable and promising material for optical-biosensor applications. Similarly, One-Dimensional Molybdenum disulfide is having best electrical characteristics likes carbon nanotubes (CNTs) that are used highly in electrochemical biosensors applications.

4.6.6 Biosensors Presently in society, many of them are facing different health issues due to various reasons and that is motivated to study the importance of developing new techniques in analyzing the cause of different diseases and their effects. In this process, an evolution of biosensors in identifying the disease-causing factors for different applications is developed. Bio-sensor performance mainly depends on its sensitivity and selectivity and therefore lots of research work is carried out in analyzing and improving the performance of selectivity and sensitivity of biosensor-based devices.

74  Nanodevices for Integrated Circuit Design

4.6.7 FET-Based Biosensors MoS2 has a diversity of applications in the optical and biomedical areas because of its chemical and crystalline structure apart from its optical and electrical properties. Because MoS2 has high bio-compatibility and bioabsorbability characteristics, it is widely used in nano-sized bio-sensorbased transistors. This motivated the researchers to study FET-based biosensors. In a FET transistor, the electrodes are electrically strongly interfaced with each other depending on the material-based channel in a semiconductor. Due to this high interface interaction between electrodes and channels, the current is controlled by the gate terminal, which is recommended heavily for FET-based biosensor applications. Figure 4.10 [14] shows the structural representation of a Monolayer MoS2-based FET transistor. Figure 4.11 represents the MoS2 physically designed structure using a Multiphysics tool with different layers and Table 4.3 shows different parameters and materials with their properties used in designing of monolayer MoS2 device. Figure 4.12 and Figure 4.13, represent the sensitivity variation and Ion/ Ioff current ratio of MoS2-based FET transistor for various dielectric constant values. From both the figures, it is understood that as the dielectric constant value increases its Ion/Ioff current ratio and its Sensitivity also increase due to the unique properties of MoS2 material.

Drain

Top gate

Monolayer MoS2 Source

HfO2 SiO2 Si (substrate)

Figure 4.10  FET-based monolayer MoS2 structure representation.

Next-Generation Molybdenum Disulfide  75

Figure 4.11  Monolayer MoS2 designed structure using Multiphysics tool.

Sensitivity 1.00E+06 1.00E+04 1.00E+02 1.00E+00

K=1 K=1.5 K=2.14 K=3

K=4

K=6

Figure 4.12  Sensitivity of MoS2 FET transistor.

4.7 Comparison of Other 2D Materials with MoS2 Here we briefed about different 2D materials like MoSe2 (Molybdenum diselenide), WS2 (Tungsten disulfide), and MoTe2 (Molybdenum ditelluride) performances with MoS2 (Molybdenum disulfide) material characteristics in two different design models i.e. Ballistic and Non-Ballistic models. Ballistic/Non-Scattering is an unobstructed flow of charge carriers (electrons) for a long distance in a material, whereas, in non-Ballistic electrons get scattered several ways in a conductor due to the electron’s wavelength, direction, phase, and spin directions properties.

76  Nanodevices for Integrated Circuit Design

Table 4.3  Different properties and materials used in designing monolayer MoS2 devices. Si

Al

SiO2

MoS2

Properties

Value

Unit

Value

Unit

Value

Unit

Value

Unit

Relative Permittivity

11.7

1

8.6

1

4.5

1

4.9

1

Electron lifetime, SRH

10(µs)

S

1

S

1

S

0.5

S

Hole lifetime, SRH

10(µs)

S

1

S

1

S

0.5

S

Band Gap

1.12V

V

3.51

V

8.5

V

2.76

V

Electron affinity

4.05V

V

4.25

V

8.75

V

4.7

V

Electron Mobility

14.5

m /(Vs)

0.001

m /(Vs)

0.1

m /(Vs)

3.64

m2/(Vs)

Hole Mobility

5

m2/(Vs)

0.001

m2/(Vs)

0.2

m2/(Vs)

2.76

m2/(Vs)

Thermal Conductivity

131

W/(m*K)

205.1

W/(m*K)

1.4

W/(m*K)

4.20E-06

1/K

2

2

2

Next-Generation Molybdenum Disulfide  77 Ion/Ioff Current 1.00E+05 1.00E+04 1.00E+03 1.00E+02 1.00E+01 1.00E+00

K=1

K=1.5 K=2.14 K=3

K=4

K=6

Figure 4.13  Drive current ratio for MoS2 FET transistor.

The ballistic method is generally used for short-channel semiconductors. Below we show the analysis response of ballistic and non-ballistic methods for a conventional MOSFET in terms of current conductivity ratio and also for different materials. Figure 4.14 and Figure 4.15 shows the drain current to drain voltage of conventional MOSFET for different gate Voltages. It is observed that the scattering method has less current conductivity ratio in comparison to the 50

40

Ids(uA)

30

20 Vg=0.4V Vg=0.45V Vg=0.5V

10

0 0.0

0.1

0.2

0.3 Vds(V)

0.4

0.5

Figure 4.14  Ids-Vds characteristics of MOSFET in the Ballistic method.

78  Nanodevices for Integrated Circuit Design 4 0.4 V 0.45 V 0.5 V

Ids(uA)

3

2

1

0 0.0

0.1

0.2

0.3 Vds(V)

0.4

0.5

Figure 4.15  Ids-Vds characteristics of MOSFET in the Non-Ballistic method.

Table 4.4  Shows the current conductivity ratio of MOSFET. Vgs

Ids-(scattering)

Ids-(non-scattering)

0.4V

0.8 µA

22 µA

0.45V

2 µA

30 µA

0.5V

3.5 µA

38 µA

non-scattering method. Table 4.4 shows the current conductivity ratio for both ballistic and non-ballistic models in support of Figure 4.14 and Figure 4.15. Figure 4.16 and Figure 4.17 shows the drain current to drain voltage characteristics for various 2D materials in both Ballistic and Non-ballistics models and is observed that the current conductivity ratio of the ballistic method is high in comparison to the scattering method. Also, the current conductivity ratio for MX2 type material is higher than the WX2 type materials due to material properties, their high interface interaction of layers, and their variable bandgaps [21, 22] shown in Table 4.5. Figure 4.18 and Figure 4.19 shows the drain current to drain voltage characteristics for various 2D materials and is observed that the current conductivity ratio of the scattering method is high in comparison to the

Next-Generation Molybdenum Disulfide  79 35

MoS2 MoSe2 MoTe2 WS2

30

Id (mA)

25 20 15 10 5 0 -5

0.0

0.1

0.2 0.3 Vd(V)

0.4

0.5

Figure 4.16  Ids-Vds characteristics of different 2D materials in the Ballistic method. 30 25

Id(mA)

20 15 MoS2 MoSe2 MoTe2 WS2

10 5 0 0.0

0.1

0.2

0.3 Vd (V)

0.4

0.5

Figure 4.17  Ids-Vds characteristics of different 2D materials in the Non-Ballistic method.

Table 4.5  Shows different band gaps for different 2D materials, both in Bulklayered and Mono-layered forms. Depending on the application and design structure of the device, the respective band gap is selected for the materials. TMDC

MoS2

MoTe2

WS2

WSe2

WTe2

Band-gap (Bulk-Layer)

1.19 eV

1.09ev

1.35 eV

1.20 eV

0.84 eV

Band-gap (monolayer)

1.89 eV

1.25 eV

1.98 eV

1.68 eV

1.24 eV

80  Nanodevices for Integrated Circuit Design 2000 MoS2 MoSe2 MoTe2 WS2

Id(mA)

1500

1000

500

0 0.0

0.1

0.2

0.3

0.4

0.5

Vg(V)

Figure 4.18  Ids-Vgs characteristics of different 2D materials in the Ballistic method.

Id(uA)

2000

MoS2 MoSe2 MoTe2 WS2 BP

1000

0 0.0

0.1

0.2

Vg(V)

0.3

0.4

0.5

Figure 4.19  Ids-Vgs characteristics of different 2D materials in the Non-Ballistic method.

ballistic method. Also, the current conductivity ratio for the WX2 type material is higher than for the MX2 type materials.

4.8 Conclusion Molybdenum disulfide is having less mobility (30–60 cm2/Vs) with a high variable band-gap (1.9eV) in comparison to Silicon (1000 cm2/Vs and

Next-Generation Molybdenum Disulfide  81 1.1eV) and is therefore used more effectively for different fields of applications due to which the material credibility and productivity is also raised. It is used in biosensing, optoelectronics [22], and other energy applications due to its unique properties and unique structure design in comparison to other 2D materials. Here, we conclude that by using MoS2 materials as a channel in a MOSFET transistor, its current conductivity is increased and can be used more effectively in Bio-Sensor applications with high sensitivity in nature by lowering the leakage current and overwhelming the short channel effects. Also, we concluded that MX2-type materials are having high current conductivity ratio in comparison to WX2-type materials, due to the material type and its properties.

References 1. Panda, D.K., Lenka, T.R., Singh, R., Goyal, V., El Islam Boukortt, N., Nguyen, H.P.T., Analytical modeling of dielectric modulated negative capacitance MoS2 field effect transistor for next-generation label-free biosensor. Int. J. Numer. Modell.: Electron. Netw. Devices Fields, 36, 2, e3060, 2023. 2. Akbari, E., Jahanbin, K., Afroozeh, A., Yupapin, P., Buntat, Z., Brief review of monolayer molybdenum disulfide application in gas sensor. Phys. B: Condens. Matter, 545, 510–518, 2018. 3. Bhimanapati, G.R., Lin, Z., Meunier, V., Jung, Y., Cha, J., Das, S., Xiao, D. et al., Recent advances in two-dimensional materials beyond graphene. ACS Nano, 9, 12, 11509–11539, 2015. 4. Nawz, T., Safdar, A., Hussain, M., Lee, D.S., Siyar, M., Graphene to advanced MoS2: A review of structure, synthesis, and optoelectronic device application. Crystals, 10, 10, 902, 2020. 5. Samy, O., Zeng, S., Birowosuto, M.D., El Moutaouakil, A., A review on MoS2 properties, synthesis, sensing applications and challenges. Crystals, 11, 4, 355, 2021. 6. Kim, J., Kwon, S., Cho, D.H., Kang, B., Kwon, H., Kim, Y., Lee, C., Direct exfoliation and dispersion of two-dimensional materials in pure water via temperature control. Nat. Commun., 6, 1, 8294, 2015. 7. Gupta, D., Chauhan, V., Kumar, R., A comprehensive review on synthesis and applications of molybdenum disulfide (MoS2) material: Past and recent developments. Inorg. Chem. Commun., 121, 108200, 2020. 8. Krishnan, U., Kaur, M., Singh, K., Kumar, M., Kumar, A., A synoptic review of MoS2: Synthesis to applications. Superlattices Microstruct., 128, 274–297, 2019. 9. Li, X. and Zhu, H., Two-dimensional MoS2: Properties, preparation, and applications. J. Materiomics, 1, 1, 33–44, 2015.

82  Nanodevices for Integrated Circuit Design 10. Kumar, V.P. and Panda, D.K., Next generation 2D material molybdenum disulfide (MoS2): Properties, applications and challenges. ECS J. Solid State Sci. Technol., 113, 033012, 2022. 11. Lu, P., Ho, Y.T., Chu, Y.C., Zhang, M., Chien, P.Y., Luong, T.T., Woo, J.C., Electrical properties of compound 2D semiconductor Mo 1–xNbxS2. Proceedings of the 14th IEEE International Conference on Solid-State and Integrated Circuit Technology, IEEE, pp. 1–4, 2018. 12. Yoo, G., Lee, S., Yoo, B., Han, C., Kim, S., Oh, M.S., Electrical contact analysis of multilayer MoS 2 transistor with molybdenum source/drain electrodes. IEEE Electron. Device Lett., 36, 11, 1215–1218, 2015. 13. Pravin, J.C., Reddy, B.R.K., Saikumar, C., Sandeep, H., Drain current simulation of molybdenum disulfide based devices. Proceedings of the International Conference on Smart Systems and Inventive Technology, IEEE, pp. 1132–1135, 2019. 14. Gao, J., Li, B., Tan, J., Chow, P., Lu, T.M., Koratkar, N., Aging of transition metal dichalcogenide monolayers. ACS Nano, 10, 2, 2628–2635, 2016. 15. Rodriguez, A., The methods to unlock molybdenum disulfide. UC Merced Undergraduate Res. J., 12, 2, 2020. 16. Pradhan, D., Bose, G., Ghosh, S.P., Tripathy, N., Kar, J.P., Effect of process temperature on molybdenum disulphide layers grown by chemical vapor deposition technique. Proceeding of the IEEE Electron Devices Kolkata Conference (EDKCON), IEEE, pp. 388–391, 2018. 17. Sha, J., Xu, W., Yuan, Z., Xu, B., Chen, Y., Fabrication of liquid-gated molybdenum disulfide field-effect transistor. Proceeding of the 12th International Conference on Nano/Micro Engineered and Molecular Systems (NEMS), IEEE, pp. 788–791, 2017. 18. Kumar, V.P. and Panda, D.K., Performance analysis of hetero-dielectric-based MoS2FET with respect to different channel lengths and high K-values for dielectric-modulated biosensor application. Braz. J. Phys., 53, 3, 68, 2023. 19. Haque, M.D., Ali, M.H., Rahman, M.F., Islam, A.Z.M.T., Numerical analysis for the efficiency enhancement of MoS2 solar cell: A simulation approach by SCAP-1D. Opt. Mater., 131, 11267, 2018. 20. Kadantsev, E.S. and Hawrylak, P., Electronic structure of a single MoS2 monolayer. Solid State Commun., 152, 10, 909–913, 2012. 21. He, J., Hummer, K., Franchini, C., Stacking effects on the electronic and optical properties of bilayer transition metal dichalcogenides MoS2, MoSe2, WS2, and WSe2. Phys. Rev. B, 89, 7, 075409, 2014. 22. Sharma, G., Ritu, Quraishi, A.M., Kattayat, S., Josey, S., Hashmi, S.Z., Alvi, P.A., Structure optimization and investigation of electrical and optical characteristics of Alq3/TAZ: Ir (ppy) 3-BCP/HMTPD OLED. Opt. Quantum Electron., 54, s5, 284, 2022.

5 Impact of Working Temperature on the ION/IOFF Ratio of a Hetero StepShaped Gate TFET With Improved Ambipolar Conduction Bijoy Goswami1, Savio Jay Sengupta2*, Ankur Jyoti Sarmah1 and Nalin Behari Dev Choudhury3 Dept. of ETE, Assam Eng. College, Assam, India Dept. of ETE, Jadavpur University, West-Bengal, India 3 Dept. of EE, National Institute of Tech., Assam, India 1

2

Abstract

The working temperature impact on the on current (ION), off current (IOFF) and on to off current ratio (ION/IOFF) of a hetero step-shaped gate TFET (HSSTFET) has been analyzed in this research article. The temperature has been varied from -25°C to 125°C while taking the step temperature as 25°C. Silvaco Atlas has been used for simulated results. The stepshaped gate also reduced the ambipolar current by a significant margin. The simulated results revealed that with increase in temperature ION/IOFF ratio decreases. Hence, it can be said that in electronic circuit the TFETs should be used in lowest possible working temperature so that the higher ION/IOFF ratio of the proposed device can be achieved. But one of the interesting facts of this device is that the change in ION with respect to temperature is negligible but there is a significant change in the IOFF. Hence, the proposed device has a near constant static power dissipation for various working temperature. Keywords:  HSSTFET, ION/IOFF, working temperature, static power dissipation, Silvaco Atlas

*Corresponding author: [email protected] Suman Lata Tripathi, Abhishek Kumar, K. Srinivasa Rao, and Prasantha R. Mudimela (eds.) Nanodevices for Integrated Circuit Design, (83–92) © 2023 Scrivener Publishing LLC

83

84  Nanodevices for Integrated Circuit Design

5.1 Introduction Throughout the last few years, TFET has been appraised as the alternative of the MOSFETs in the field of IOTs and mobile electronic equipment [1, 2]. The main disadvantage of MOSFETs is the limitation of their subthreshold swing (SS) which is 60mV/decade due to thermal emission phenomenon obeyed by the carriers. This limitation can be easily overcome by TFETs due to band to band tunneling phenomenon. Hence, TFET has a sharper SS [3] and also has a lower leakage current characteristic. However, TFET also suffers from two disadvantages: a) TFET has a lower on current than the MOSFET [4] and b) band to band phenomenon can also occur at the drain to channel junction which leads to higher ambipolar current in comparison to MOSFET [5]. Many methods were proposed to improve this ambipolar current such as source gate/drain gate overlap [6, 7], low drain doping architecture [8], engineering of gate work function [9] and so on. The proposed HSSTFET shows provides better ambipolar conduction and the simulated results also justify the same. The variation of the working temperature effects the ION/IOFF ratio differently for MOSFET and TFET structures. For MOSFET, there is an indirect relationship between the working temperature and the ON current [16–19] i.e., the on current decreases with increase in working temperature and for TFET, there is a direct relationship between the temperature and on current i.e., on current of TFET increases with increase in working temperature [10]. This research article pays the attention on the effect of the working temperature on the ION, IOFF and the ION/IOFF ratio of the proposed the HSSTFET. The following is the link to the research article: The unit layout is covered in section two. The simulated results and discussion are detailed in section 5.3, and the study article is concluded in section 5.4.

5.2 Device Structure The proposed HSSTFET has been designed and simulated by using Silvaco ATLAS. The parameters that had been incorporated in the device design, has been provided in the Table 5.1. Figure 5.1 depicts the cross-sectional view of the proposed HSSTFET. For simulation purposes, the following models have been used. The effect of carrier recombination was studied using the SRH model. The non-local route tunneling model is used to integrate band to band tunneling. For

Working Temperature on ION/IOFF Ratio  85 Table 5.1  Used device parameters. Parameter

Value

Channel Length (Lch)

40 nm

Source Length (LS)

50 nm

Drain Length (LD)

50 nm

Oxide Thickness (TOX)

2 nm

Oxide Thickness at drain side (TOXD)

5 nm

Darin Overlap Distance(LOV)

10 nm

Darin Underlap Distance(LUN)

20 nm

Silicon Thickness (TSi)

10 nm

Source Doping (P+)

1020 cm-3

Channel Doping(P)

1015 cm-3

Drain Doping(N+)

5 × 1017 cm-3

Gate Work function

4.2 eV

VGS TOXD

HfO2 TOX

HfO2 LUN

TSi

Source (P+) SiGe 1x1020cm-3

LOV

Drain (N+) Si 5x1017cm-3

Si 1x1014cm-3

HfO2 VGS

HfO2

Figure 5.1  Cross-sectional view of the proposed HSSTFET.

86  Nanodevices for Integrated Circuit Design high doped source and drain areas, doping based mobility models, band gap narrowing models, and fermi statistic models are used.

5.3 Results and Discussion

ID(A/µm)

The impact of working temperature on the current characteristics of proposed HSSTFET has been investigated by using the parameters provided in Table 5.1. All the simulations are performed at a drain voltage of 1V. The gate voltage is adjusted between -1.5V and 1.5V. The temperature ranges from -50°C to 125°C, with -25°C as the phase temperature. Silvaco ATLAS is used to run all of the simulations. The transfer characteristics (drain current vs. gate voltage) of the proposed HSSTFET with respect to working temperature is depicted in Figure 5.2 and Figure 5.3. Figure 5.2 represents the ID vs. VGS curve in logarithmic scale and Figure 5.3 represents the transfer characteristics in scalar scale. From the figures, it can be observed that with increase in temperature, both ION and IOFF increases. This is because as the temperature rises, the resistance of silicon decreases, resulting in a higher ID. As a result, as the temperature rises, the ID rises as well. Furthermore, the proposed system has better ambipolar conduction over [11, 12]. Furthermore, the pro­posed system outperforms several TFET structures in terms of ION [11, 12].

1E-3 1E-4 1E-5 1E-6 1E-7 1E-8 1E-9 1E-10 1E-11 1E-12 1E-13 1E-14 1E-15 1E-16 1E-17 1E-18 1E-19 1E-20 1E-21 -1.5

-50deg -25deg 0deg 25deg 50deg 75deg 100deg 125deg -1.0

-0.5

0.0

0.5

1.0

1.5

Gate Voltage (VGS) (Volt)

Figure 5.2  Transfer characteristics of the proposed HSSTFET vs. working temperature (logarithmic scale).

Working Temperature on ION/IOFF Ratio  87 1.4x10-4 1.2x10-4

-50deg -25deg 0deg 25deg 50deg 75deg 100deg 125deg

ID(A)

1.0x10-1 8.0x105 6.0x10-5 4.0x105 2.0x105 0.0 -1.5

-1.0

-0.5 0.0 0.5 Gate Voltage (VGS) (Volt)

1.0

1.5

Figure 5.3  Transfer characteristics of the proposed HSSTFET vs. working temperature (linear scale).

There are few characteristics of a device that heavily depends on the working temperature and hence temperature effects the device’s performance significantly. Hence, electrical parameters such as ION/IOFF ratio, DIBL, VT etc. gets significantly affected by working temperature. Figure 5.4 shows the characteristics of the threshold voltage with respect to the working temperature. As higher temperature leads to reduction in Si resistance which in turn higher drain current, hence with increase in temperature threshold voltage reduces and it is justified by the Figure 5.4.

0.43 VT

0.42

VT (V)

0.41 0.40 0.39 0.38 0.37 0.36 0.35

–40 –20

0

20 40 60 80 100 120 T (Cº)

Figure 5.4  Threshold voltage with respect to varied working temperature.

88  Nanodevices for Integrated Circuit Design 0.000135 0.000134

3.5x10-14

Ion Ioff

3.0x10-14

0.000133

2.5x10-14

0.000131

2.0x10-14

0.000130

1.5x10-14

0.000129

1.0x10-14

0.000128

ID(A)

ID(A)

0.000132

5.0x10-15

0.000127

0.0

0.000126 -40 -20

0

20

40

60

80 100 120

T (Cº)

Figure 5.5  The ON and OFF drain current of the proposed HSSTFET vs. working temperature.

It can be also observed, that there is a linear dependency of threshold voltage (VT) on the working temperature. Figure 5.5 shows the ION and IOFF currents of the proposed HSSTFET as the temperature rises. The ION increases in proportion to the rise in temperature, and there is a linear relationship. The IOFF, on the other hand, increases as temperature rises, but the relationship is nonlinear, i.e., the off current rises exponentially as temperature rises. One of the most intriguing aspects of the proposed structure is that, as seen in Figure 5.5, although there is a rise in ON current, the discrepancy is not substantial. As a result, the proposed structure is robust in terms of static power dissipation as the working temperature rises. One of the most significant parameters of a transistor that enable it to be used in a digital circuit is ION/IOFF ratio which is depicted in Figure 5.6. As per the simulated resulted it can be said that the maximum ION/IOFF ratio has been obtained at – 50°C and it is at the range of 1016 which is itself better than [11, 12]. The use of SiGe at the source side also improves the ambipolar current than other devices [11–16]. As the temperature rises the ION/IOFF ratio tends to reduce linearly as per Figure 5.6. To use a transistor in digital circuit applications such as amplifier or logic gates, the highest on to off current ratio is considered as the best. Hence, the simulated results may lead to that TFET can work at its highest potential in a digital circuit

Working Temperature on ION/IOFF Ratio  89 ION/IOFF

1E16 1E15

ION/IOFF

1E14 1E13

1E12 1E11

1E10 1E9

-50 -25

0

25 50 T(Cº)

75 100 125

Figure 5.6  ION/IOFF ratio of the proposed HSSTFET vs. working temperature.

at the lower working temperature. However, one of the most significant characteristics of the proposed device is that the ION remains almost constant throughout the working temperature variation depicted in Figure 5.5. Therefore, the proposed device has a constant static power dissipation even if the temperature is varied.

5.4 Conclusion The working temperature impact on the proposed device has been explored in this research article by using Silvaco ATLAS software. The working temperature has been varied from -50°C to 125°C while taking 25°C as the step temperature. It can be seen from the simulation results that as the temperature rises, the ION and IOFF rise with it. However, since the shift in ION is not substantial for the proposed structure, it can be used for any working temperature between -25°C and 125°C in view of static power dissipation. Also, the simulated show that the relationship between the ION and the working temperature is linear, while the relationship between the IOFF and the working temperature is exponential. Furthermore, the results demonstrate that, in terms of ION/IOFF ratio, TFETs can be used in digital circuits at lower operating temperatures. However, due to the proposed device’s ON current stability and low static power dissipation, the proposed TFET structure can be used at any working temperature.

90  Nanodevices for Integrated Circuit Design

References 1. Seabaugh, A.C. and Zhang, Q., Low-voltage tunnel transistors for beyond CMOS logic. Proc. IEEE, 98, 12, 2095–2110, 2010, https://doi.org/10.1109/ jproc.2010.2070470. 2. Ionescu, A.M. and Riel, H., Tunnel field-effect transistors as energyefficient electronic switches. Nature, 479, 7373, 329–337, 2011, https://doi. org/10.1038/nature10679. 3. Choi, W.Y., Park, B.-G., Lee, J.D., King Liu., T.-J., Tunneling fieldeffect transistors (tfets) with subthreshold swing (SS) less than 60 MV/dec. IEEE Electron Device Lett., 28, 8, 743–745, 2007, https://doi.org/10.1109/ led.2007.901273. 4. Boucart, K. and Ionescu, A.M., Double-gate tunnel FET with high-$\kappa$ gate dielectric. IEEE Trans. Electron Devices, 54, 7, 1725–1733, 2007, https:// doi.org/10.1109/ted.2007.899389. 5. Krishnamohan, T., Kim, D., Raghunathan, S., Saraswat, K., Double-gate strained-GE heterostructure tunneling fet (TFET) with record high drive currents and ≪60mV/DEC subthreshold slope. 2008 IEEE International Electron Devices Meeting, 2008, https://doi.org/10.1109/iedm.2008.4796839. 6. Vijayvargiya, V. and Vishvakarma, S.K., Effect of drain doping profile on double-gate tunnel field-effect transistor and its influence on device RF performance. IEEE Trans. Nanotechnol., 13, 5, 974–981, 2014, https://doi. org/10.1109/tnano.2014.2336812. 7. Verhulst, A.S., Vandenberghe, W.G., Maex, K., Groeseneken, G., Tunnel field-effect transistor without gate-drain overlap. Appl. Phys. Lett., 91, 5, 053102, 2007, https://doi.org/10.1063/1.2757593. 8. Abdi, D.B. and Jagadesh Kumar, M., Controlling ambipolar current in tunneling fets using overlapping gate-on-drain. IEEE J. Electron Devices Soc., 2, 6, 187–190, 2014, https://doi.org/10.1109/jeds.2014.2327626. 9. Cui, N., Liang, R., Xu, J., Heteromaterial gate tunnel field effect transistor with lateral energy band profile modulation. Appl. Phys. Lett., 98, 14, 142105, 2011, https://doi.org/10.1063/1.3574363. 10. Lin, S.-C. and Banerjee, K., A design-specific and thermally-aware methodology for trading-off power and performance in leakage-dominant CMOS Technologies. IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 16, 11, 1488– 1498, 2008, https://doi.org/10.1109/tvlsi.2008.2001060. 11. Liu, M., Xie, Q., Xia, S., Wang, Z., A novel step-shaped gate tunnel fet with low ambipolar current, ScienceGate, Retrieved December 8, 2022, from https://www.sciencegate.app/document/10.1109/isdcs.2019.8719250. 12. Agha, F.N., Hashim, Y., Shakib, M.N., Temperature impact on the ion/IOFF ratio of gate all around nanowire TFET. 2020 IEEE International Conference on Semiconductor Electronics (ICSE), 2020, https://doi.org/10.1109/ icse49846.2020.9166887.

Working Temperature on ION/IOFF Ratio  91 13. Sengupta, S.J., Goswami, B., Das, P., Sarkar, S.K., A noise immune double suspended gate MOSFET for ultra low-power applications. Silicon. SpringerLink, 14, 5091–5101, 2021, August 5. Retrieved December 8, 2022, from https://link.springer.com/article/10.1007/s12633-021-01283-1. 14. Bhattacharya, S., Tripathi, S.L., Kamboj, V.K., Design of tunnel FET architectures for low power application using improved Chimp optimizer algorithm. Eng. Comput., 39, 1415–1458, 2021, https://doi.org/10.1007/ s00366-021-01530-4. 15. Roy, A., Goswami, B., Dey, U., Gayen, D., Reja, W., Sarkar, S.K., Impact of trapezoidal channel in double-gate tunnel field effect. Retrieved December 8, 2022, from https://ieeexplore.ieee.org/document/9158233/. 16. Dey, A., Kumari, K., Jana, A., Goswami, B., Nandi, P., Sarkar, S.K., Room temperature PT-modified WO3/P–si film gas sensor for detection of methanol, 1970, January 1, SpringerLink, Retrieved December 8, 2022, from https:// link.springer.com/chapter/10.1007/978-981-15-5224-3_19. 17. Goswami, B., Sengupta, S.J., Reja, W., Das, P., Sarkar, S.K., Validation of input/output characteristics of symmetrical double source. 2021, June 21, Retrieved from 10.1109/DevIC50843.2021.9455764. 18. Reddy, I.V. and Tripathi, S.L., Enhanced performance double-gate junction-less tunnel field effect transistor for bio-sensing application. Solid State Electron. Lett., 3, 19–26, 2021, https://doi.org/10.1016/j.ssel.2021.12.005. 19. Mendiratta, N., Tripathi, S.L., Padmanaban, S., Hossain, E., Design and analysis of heavily doped n+ pocket asymmetrical junction-less double gate MOSFET for biomedical applications. Appl. Sci., 10, 7, 2499, 2020, https:// doi.org/10.3390/app10072499.

6 Analysis of RF with DC and Linearity Parameter and Study of Noise Characteristics of Gate-All-Around Junctionless FET (GAA-JLFET) and Its Applications Pratikhya Raut1, Umakanta Nanda2 and Deepak Kumar Panda3* ECE Department, VR Siddhartha Engineering College, Kanuru, Vijayawada, Andhra Pradesh, India 2 School of Electronics, VIT-AP University, Near Vijayawada, India 3 Department of ECE, Amrita School of Engineering Amaravati, Amrita Vishwa Vidyapeetham, Andhra Pradesh, India 1

Abstract

As a fundamental component of the semiconductor industry, MOSFET played a crucial role in its development. The most significant benefit of MOSFET is the device’s scalability. When the device size reaches the submicron regime, negative consequences such as reduced mobility, short channel effects, and a gradual shift in doping concentration at the junctions become evident. The concentration gradient at source and drain junctions makes the fabrication of these devices more difficult. To address this issue, a device known as a junctionless FET or gated resistor was developed. Due to the simple fabrication technique that does not require the production of junctions, the lower leakage current characteristics, the low short channel effects (SCE) features, and the practically optimal switching performances. Moreover, the GAA JLFET architecture improves the device properties by lowering the bulk-leakage current, increasing the degree of integration, and enhancing the gate controllability. The RF and linear parameter enhance the devices performance by reducing the intermodulation distortion, non-linearity and reducing the noise characteristics in the device. This chapter gives the readers a brief idea about the device architecture and its various DC, RF, linear and noise *Corresponding author: [email protected] Suman Lata Tripathi, Abhishek Kumar, K. Srinivasa Rao, and Prasantha R. Mudimela (eds.) Nanodevices for Integrated Circuit Design, (93–116) © 2023 Scrivener Publishing LLC

93

94  Nanodevices for Integrated Circuit Design analysis with respect to gate voltage, drain voltage, work function, and also its application in various fields in this realistic world. Keywords:  Gate-all-around, junctionless, linearity, MOSFET, noise, RFIC, short channel effects

6.1 Introduction A combination of electrical circuits that are contained on a single, compact, and flat piece of semiconductor material (sometimes referred to as a “chip”) is referred to as an integrated circuit (IC) normally silicon. Compared to circuits built from discrete electronic components, MOS (Metal Oxide Semiconductor) [1] transistor integration has produced circuits that are orders of magnitude smaller, quicker, and less expensive. The chip performance rate has been difficult for the semiconductor industry to maintain. As an example, equipment from firms like Intel and AMD only offer a 10–15% performance improvement over those from the previous generation. This familiarizes users with the industry query, Has the Device’s Performance Peaked? Will producers and designers be able to surpass the limitations of current performance? However, the difficulties in shrinking the size of the chips make it difficult for the firms who are producing them. Not everyone, though, is prepared to quit up just yet. Gate-All-Around, or GAA [2], is a key transistor design that Samsung, a market leader in semiconductor design, proposed with the intention of upholding Moore’s Law [3] and possibly advancing transistor-level semiconductor technology. In essence, GAA offers a redesign of the conventional transistor architecture where gate material covers the silicon semiconductor channel on four sides rather than being covered by the gate from three sides (as in FinFET) [4]. Reduced design size and enhanced potential for channel length scaling [5], which contributes to higher transistor density, are the two main advantages of this transistor design. Digital electronic devices and smart devices are an indispensable component of modern life. Without CMOS technology, it is difficult to imagine or create an electronic device. The integrated circuit industry has benefited significantly from CMOS technology. According to CMOS technology, device size can be decreased by increasing the number of transistors on-chip with each successive generation. Manufacturers of electronic devices scale transistors at each node to increase performance while reducing power consumption at a lower device area and cost. This process is known as PPAC (power-performance-area-cost) scaling [6]. However, junctionless FETs [7] have recently garnered a lot of attention as

RF with DC and Linearity Parameter  95 Conventional Mosfet

DoubleGate Mosfet Tri -Gate Mosfet

Finfet

Nanosheet Gate - All Around Mosfet

Figure 6.1  Evolution of Gate-All-Around Mosfet from conventional Mosfet.

a potential method for continuing scaling toward the sub 10 nm domain. The JLFETs has the following benefits over traditional FETs: It removes the source/drain junction-induced thermal budget restriction. Since the pocket implantation of dopants [8], lateral diffusion process [9], and shallow interface are no longer required, the fabrication of device  has been streamlined, resulting in a simpler process. Because the major conducting path goes through the highly doped silicon bulk, the interface that is comprised of the oxide and the semiconductor channel exhibits a high level of immunity to surface scattering. MOSFET dimensions are further reduced, electrostatic control and driving current are constrained. Gate-all-around JLFET’s [10] are about to become the cutting-edge technology in industrial semiconductor production. The evolutionary flow of Gate-All-Around structure from conventional Mosfet has been outlined in Figure 6.1. What is GAA-JL-FET? Moreover, the first GAA-FET, which was a vertical GAA-FET and was known as a Surrounding Gate Transistor, was unveiled by Toshiba in 1988 [11]. The operation of a Gate-All-Around JL-Field Effect Transistor (GAA-JL-FET) is identical to that of a FinFET transistor, except that the gate material completely encircles the channel. In general, GAA-JL-FETs can have two or four gates depending on the architecture. Likewise, there

96  Nanodevices for Integrated Circuit Design are two forms of GAA: n-channel GAA and GAA with n+ type impurities doped in and p-channel GAA with p+ type impurity doping on the channel. Depending on the implementation, the orientation of these structures might be parallel or perpendicular to the substrate. Why GAA-JL-FET? • Device sizes have shrunk as a result of the development of more advanced manufacturing techniques and the demand for effective gadgets. However, when transistors got bigger, short channel effects, leakage from quantum tunneling, and mobility degradation got worse. FinFETs, which introduced a 3-D architecture as opposed to a planar device, gave a mechanism to more effectively regulate the dynamics of the device. Due to the design characteristics, FinFETs were highly scalable, reduced leakage currents, and offered quicker switching times. • In comparison to conventional JLFET’s, gate all around architectures have proven the advantage of efficient channel control via gate. It possesses the best electrical and conductivity properties. • GAAFET transistors enable improved gate control, resulting in highly efficient devices. As a result of the enhanced channel size and arrangement, leakage current is negligible and short-channel effects are insignificant. • The nanosheets’ width and density can be adjusted. As a result, engineers have a deeper understanding of the device’s characteristics. For example, a wide sheet will generate more current but increase the cost as a whole. The driving current can be decreased if the designers choose to minimize the device size. Moreover, GAA technology has assisted in further reducing voltage scaling, which was previously constrained in FinFET due to design limitations. Analog, RF and Linear characteristics of device are crucial for various systems on chip, RF-IC applications including system in package applications. This chapter briefly deals with the device structure and different modeling approach with the analysis of RF, linearity and noise metrics of the device on various electrical parameters with its applications in various semiconductor industries.

RF with DC and Linearity Parameter  97

6.2 Structure of GAA-JLFET The 2D and 3D schematic representation of GAA-JLFET with all layers has been portrayed in below Figures 6.2(a) and 6.2(b). The device is placed on SOI. This structure comprises of a metal gate with followed by an oxide layer of dielectric material HfO2. Instead of SiO2, HfO2 (High-k dielectric material) has been utilized as a gate oxide material to decrease the leakage current flowing due to gate and also to increase the gate controllability across the channel. The gate all around structure reduces to reduce short channel effects [12] like DIBL, gate leakage current, CLM i.e., channel length modulation [13], subthreshold conduction [14] and also hot electron effect [15]. A high-k dielectric [16] is one whose permittivity K is higher than that of SiO2(K = 3.9). SiO2 was the first gate dielectric chosen for MOSFET’s. Lg Gate Oxide Source N+

Channel N+

Drain N+

Oxide Gate

Lg (a) Oxide

Lg

Source N+

Channel N+

Drain N+

Lg

(b)

Figure 6.2  (a) 2D schematic diagram of GAA-JLFET. (b) 3D schematic diagram of GAA-JLFET.

98  Nanodevices for Integrated Circuit Design Table 6.1  Device parameters of gate all around junctionless FET (GAA-JLFET). Device parameter name

Value

Device Channel length (Lch)

30.1 nm

Device Channel Width (Wch)

10.2 nm

Device Channel Height (hch)

12.1 nm

Gate dielectric constant (K)

32

Device Oxide thickness (tox)

2 nm

Doping concentration of source

2.6 * 1019

Doping concentration of channel

2.6 * 1019

Doping concentration of drain

2.6 * 1019

Temperature

300K

It  has good insulating properties and is easy to make, but it has a low dielectric constant, which is a big problem. Using high-k dielectrics to improve transconductance is good for GAA-JLFET for high frequency applications. Currently, in order to boost the stability of HfO2, other elements like silicon or aluminum are used in research on Hf-based dielectrics. Therefore, hafnium oxide has been used as a dielectric material in this device. The channel thickness (tg) and doping concentration (Nd)  values ​are chosen such that the channel is fully depleted in the off state and permits a substantial amount of current flow in the ON state. Various parameters with dimensions of the device used during simulation purpose have been clearly pictured in Table 6.1. Different models are used in simulation process of the device like Field dependent mobility model in short FLDMOB, the Lombardi’s CVT model, the ShockleyReadHall Recombination model and Boltzmann transport model are used to simulate the device’s electrical properties [17]. The simulation is carried out by deploying commercially available TCAD tool. The impact of quantum mechanics has been neglected for the sake of simplicity. Furthermore, AC simulation is utilized out for analyzing various RF and Linear parameters of the device.

6.3 Results and Discussion Here we have spotlighted various DC, RF, Linear analysis of this device [18]. Figure 6.2 represents the transfer characteristics of GAA-JLFET.

RF with DC and Linearity Parameter  99

6.3.1 DC Analysis Different DC characteristics of the device have been summarized in this section. Despite the fact that the channel depletion zone was very narrow under the gate, the GAA structure, along with a very short channel showed excellent gate controllability. The impact of gate voltage on drain current for GAA-JLFET has been illustrated in Figure 6.3. Thinning the gate oxide improves the electrical properties even more. Even though the leakage current flows through the bulk region, the ON/OFF current ratio in a Vgs range of 1 V is greater than 108. The current switching ratio with respect to various gate metal work functions (ωM) has been represented in Figure 6.4. 1.0×10−5

Drain Current (A/µm)

8.0×10−6 6.0×10−6 4.0×10−6 2.0×10−6 VDS=1V 0.0 0.0

0.2

0.4 0.6 Gate Voltage (V)

0.8

Figure 6.3  Variation of drain current w.r.t. Vgs of GAA-JLFET. 2.5×109

ION/IOFF

2.0×109 1.5×109 1.0×109 5.0×108 0.0

4.2eV

4.4eV 4.6eV 4.8eV Work Function of Gate Metal

Figure 6.4  Variation of ION/IOFF w.r.t. work function.

1.0

100  Nanodevices for Integrated Circuit Design A high current switching ratio i.e. Ion/Ioff indicates lower leakage current, which enhances the device performance. This graph demonstrates that the current switching ratio increases as the value of ωM increases to 4.8 eV from 4.2 eV. This is because the reduction in off-current is more pronounced than the current that flows when the device is on. The subthreshold slope [19] is an important characteristic of the current–voltage characteristic of a semiconductor device. The reciprocal of this slope gives the subthreshold swing. Small subthreshold swing signifies superior channel control, e.g., enhanced Ion/Ioff, which often leads to less leakage current. For subthreshold devices, this also contributes to improved performance. The theoretical minimal subthreshold swing for silicon Transistors at normal temperature is around 60mV/decade. The mathematical expression for the SS is: −1

 ∂ log10 ( I D )  SS =   . ∂ V gs  



(6.1)

In order to study the device’s switching features, the Subthreshold Swing (SS) is retrieved for various metal work function and depicted in Figure 6.5. This graph clearly explains that with increase in gate work function the device’s SS is reduced thereby increasing the efficiency of the device.

Subthreshold Swing (mV/dec)

80 70 60 50 40 30 20 10 0

4.2eV

4.4eV 4.6eV 4.8eV Work Function Of Gate Metal

Figure 6.5  Variation of SS w.r.t. work function.

RF with DC and Linearity Parameter  101

6.3.2 RF Analysis The other crucial Figure of Metrics for an analog and RF circuits are transconductance, denoted by the symbol gm, output conductance, denoted by the symbol gd, Early voltage i.e. VEA, Device intrinsic gain (AV), cut-off frequency (fT), transconductance generation factor, denoted by TGF and some new radio frequency parameters have been discussed in this section. Another crucial device parameter that directly fluctuates with device gain is transconductance (gm). It is the ratio of a small variation in gate bias with respect to change in drain current keeping drain voltage constant.

gm =



∂I D ∂Vgs

(6.2)



As seen in graph, a higher ID value causes a larger transconductance (gm) value. The variation in drain current is highest when Vgs=1.1Volt, as seen in Figure 6.4, which depicts the curve of ID versus Vgs as shown in above graph. The transconductance reaches its maximum peak at Vgs = 1.1 V and after reaching peak value the slope decreases due to high electric field due to rise in gate voltage and ultimately it leads to mobility degradation which in turns lowers the gm. The effect of transconductance with for various gates to source voltage has been clearly pictured in Figure 6.6.

gm(S/µm)

4×10−5 3×10−5 2×10−5 1×10−5 VDS=1V 0 0.0

0.2

0.4 0.6 Gate Voltage (V)

Figure 6.6  Variation of gm w.r.t. Vgs of GAA-JLFET.

0.8

1.0

102  Nanodevices for Integrated Circuit Design 4.0×10–5 Conductance (S/µm)

3.5×10–5 3.0×10–5 2.5×10–5 2.0×10–5 1.5×10–5 1.0×10–5

VDS=1V

5.0×10–6 0.0 0.0

0.2

0.4 0.6 Gate Voltage (V)

0.8

1.0

Figure 6.7  Variation of gds w.r.t. Vgs of GAA-JLFET.

As seen in Figure 6.7, the GAA-JLFET has a lower drain to source conductance (gds). This is  mainly  caused by the electric field  discontinuity along the channel where there is a major doping concentration gradient that redistributes the electric field towards the drain edge. As Vds increases in the saturation region, the heavily doped portion of the channel absorbs excess drain voltage above saturation, preventing further penetration of the electric field to the source end. The screening effect is a physical phenomenon that is the primary factor lowering the gds. The transconductance generation factor, usually TGF [20], is given as the ratio of transconductance to drain current. In other words, it is defined as the effectiveness with which the drain current can be controlled to get the appropriate value of gm. TGF must be high in order to develop low power analog circuits. This is one of the most important performance criteria to  consider when developing subthreshold low-power applications devices. The benefit of a high TGF is the ability to design circuits with a low supply voltage. The mathematical expression for TGF is given as:



TGF =

gm I ds

(6.3)

As TGF directly varies with transconductance of the device it behaves same as the transconductance value. The effect of TGF for gate to source voltage for GAA-JLFET has been pictured in Figure 6.8. The cut-off frequency is defined as the lowest frequency at which the current gain reaches unity. It is the major performance parameter that is

RF with DC and Linearity Parameter  103 40 35

TGF (V-1)

30 25 20 15 10 5 0 0.0

VDS=1V 0.2

0.4 0.6 Gate Voltage (V)

0.8

1.0

Figure 6.8  Variation TGF w.r.t. Vgs of GAA-JLFET.

utilized for making comparisons between devices that are used in highspeed digital switching activities. The maximum  oscillation frequency is calculated by the frequency at which the maximum  single-sided power gain is  0 dB  (unity). Assessing devices utilized in tuned RF (radio frequency) amplifiers is essential. Mathematically it is expressed as:



fT =

gm 2Π(C gs + C gd )



(6.4)

As Vgs increases, more free carriers accumulate in the channel region, increasing drain current (ID) and transconductance (gm). Based on equation (6.4) fT directly varies with gm. As the Vgs value increases from the subthreshold region, fT increases as gm increases and gate to gate capacitance decreases as seen in Figure 6.9.

6.3.3 Linearity Analysis One of the key factors contributing to the non-linearity in RFICs is the device’s non-linearity. Higher order harmonics and intermodulation are caused by a device’s nonlinearity in analog and RF circuits. Circuit nonlinearity results in output power loss. Consequently, one of the key goals when designing circuits for RF applications is to minimize these distortions. To comprehend the nonlinear behavior of RFIC, we must first comprehend the various linearity metrics. The most important characteristics

104  Nanodevices for Integrated Circuit Design

Cut-Off Frequency (Hz)

6×1011 5×1011 4×1011 3×1011 2×1011 1×1011 0 0.0

VDS=1V 0.2

0.4 0.6 Gate Voltage (V)

0.8

1.0

Figure 6.9  Variation cut-off frequency w.r.t. Vgs of GAA-JLFET.

are transconductance and its higher order derivatives, in particular gm2 and gm3 for evaluating the linearity and distortion of any FET device. gm2 and gm3 represent the 2nd and 3rd order transconductance, respectively. Mathematically they are expressed as:





g m2 =

∂ 2 I ds ∂V 2 gs

g m3 =

∂3I ds ∂V 3 gs

(6.5)





(6.6)

These two  parameters are  used  to measure the nonlinearity of FET  devices and determine the  distortion limit. For good linearity and minimum distortion, they should be as small as feasible. The variation of gm2w.r.t. Vgs is shown in Figure 6.10. VIP2 and VIP3 [21] are performance metrics for semiconductor device distortion that are determined by the properties of DC devices. The intercept gate voltage (VIP2) is defined as the voltage at which the first and second order harmonics are equivalent. The intercepted gate voltage at which the first and third order harmonics are equivalent is known as VIP3. VIP3 is typically used to measure linearity accurately at high frequencies. Device linearity is higher in the device with higher VIP2 and VIP3 values.

RF with DC and Linearity Parameter  105 3.5×10−5

gm2(A/µmV2)

3.0×10−5 2.5×10−5 2.0×10−5 1.5×10−5 1.0×10−5 5.0×10−6 0.0 0.0

VDS=1V 0.2

0.4 0.6 Gate Voltage (V)

0.8

1.0

Figure 6.10  Variation gm2 w.r.t. Vgs of GAA-JLFET.





VIP 2= 4 ×

VIP = 3

g m1 g m2

(6.7)

g m1 g m3

(6.8)

24 ×



As gm2 and gm3 decrease, the  values  ​of  VIP2 and VIP3  increase. VIP2 achieves its peak value at lower Vgs because higher Vgs results in poor gate controllability on charge carriers, which leads to non-linearity in the device. Figure 6.11 represents the variation of VIP2 with respect to gate to source voltage for GAA-JLFET. IIP3 is one of the most essential parameters for predicting the intermodulation in the device. IIP3 is the intercepted input power point where the first and third orders intersect. Higher IIP3 values are desired for greater linearity. The equation for IIP3 is:



IIP 3=

2 g m1 × 3 g m3 × Rs

(6.9)

Here Rs is the source resistance which is equal to 50Ω. The impact of Vgs on IIP3 of the device is illustrated in Figure 6.12. It has been noted that at increasing Vgs, this device exhibits the greatest peak

106  Nanodevices for Integrated Circuit Design 2.0

VIP2 (V)

1.5

1.0

0.5 VDS=1V 0.0 0.0

0.2

0.4 0.6 0.8 Gate Voltage (V)

1.0

Figure 6.11  Variation VIP2 w.r.t. Vgs of GAA-JLFET. 0 –10

IIP3 (dBm)

–20 –30 –40 –50 –60 –70 VDS=1V

–80 0.0

0.2

0.4 0.6 Gate Voltage (V)

0.8

1.0

Figure 6.12  Variation of IIP3 w.r.t. Vgs of GAA-JLFET.

value of. Because peak shifting to higher Vgs shows inadequate gate control on charge carriers, the peak of IIP3 should appear at lower Vgs so that device will have higher linearity without any distortion in the circuit as well.

6.3.4 Noise Analysis Electrical noise [22] is caused by more or less random undesirable electrical impulses coupling into circuits where they interfere with information carrying signals. Noise exists in both power supply circuits and signal

RF with DC and Linearity Parameter  107 circuits, but it is a problem in signal circuits in general. There are various types of noise generated in the circuits. Some of them are briefly discussed below.

6.3.4.1 Thermal Noise Channel noise in MOS devices operating in the saturation region can be represented by a current source connected between the drain and source terminals. This noise can be expressed as: 2 ind = 4kTg d 0 ∆f



(6.10)

A voltage source connected in series with the gate can represent the thermal noise of the input channel. The spectral density of voltage is:

υn2,d 8 kTg d 0 = ∆f 3 g m2



(6.11)

6.3.4.2 Flicker Noise When charge carriers flow at the interface, random charge trapping by energy states causes flicker noise in the drain current. This noise may vary from process to process depending on the contaminants of the oxide-silicon contact. Modeling flicker noise using a current source across the drain and source and expressing it as



inf2 K g m2 = f f CoxWL ∆f

(6.12)

where Kf = specific constant of the device W = Effective width of the device L = Effective Length of the device. Because flicker noise is the inverse of frequency, it is also known as 1/f noise. Sometimes it is also referred as Pink Noise.

108  Nanodevices for Integrated Circuit Design Flicker noise decreases with increasing frequency, eventually falling even below thermal noise. The flicker noise corner frequency is the frequency where thermal noise equals flicker (fC).

Kf fC =



γ ωT 4kT

(6.13)

Though flicker noise is insignificant at RF frequencies, it has a significant effect in oscillators and mixers and due to non-linearity or time variation in such circuits.

6.3.4.3 Gate-Induced Thermal Noise Because of capacitive coupling, changes in the channel charge in the inversion region cause a noisy current in the gate. This is termed as GateInduced Thermal Noise in the device. Mathematically it is expressed as: 2 ing = 4kTδ g g ∆f



(6.14)

ω 2C 2gs = & δ 4 for device with long channel. 3 5g d0 The coefficient relation between gate and drain noise is given by:

where = gg

c=

* ing . .ind 2 . i 2ng ind

(6.15)



Where c = j*0.395 for the devices having long channel. Now, we will discuss the circuit noise analysis in terms of gate voltage and drain voltage. Since the electric field varies in all dimensions of the simulated device structure, the 3D Poisson equation (PE for short) is solved using the finite volume method. This method assures conservation of flux  during 3-D Laplacian finite difference method. To  address the quantization  effect,  the  timeindependent 2D Schrödinger equation, namely SE, is numerically solved in the xy cross sectional plane by implementing the FEAST eigenvalue solver to obtain the energy levels of the different sub bands and get the wave function.

RF with DC and Linearity Parameter  109 The explicit dependence on kz in the balance equations [23, 24] is removed by projecting the multi sub band 1D Boltzmann transport equation, i.e., BE, over equi energy surfaces and then discretizing it by employing the H transformation approach. To find the property M of the system matrix, we first perform a parity split on the distribution function on a staggered grid in real space, and then we delete the odd equations. The fully coupled equations are solved using the Newton & Raphson [25] iteration method, providing rapid convergence and linearization for use in simulations of small signals and noise. The Schrodinger equation is transformed into Newton & Raphson equation by employing the first-order perturbation theory [26], that helps in explaining the variation in sub-band energy and wave functions in terms of potential variation. When the electrostatic potential correction is less than 10-12 V, convergence is attained. For the device’s common source configuration, the noise and small-­ signal characteristics are estimated. Because the system of equations surrounding the stationary values needs to be linearized for the small-signal analysis, the stationary Jacobian matrix has additional coefficients that are already known, such as the time-derivative in the Boltzmann equation. Additionally, the stationary Jacobian matrix has a close relationship to with the Newton and Raphson equations. This is due to the fact that the small signal analysis requires the linearization of the system of equations. The reciprocity of the small signal parameters at equilibrium is ensured by a consistent formulation of the Boltzmann and Poisson equations in terms of small signals [27]. Only variations under small-signal operation are taken into account for the noise analysis. The energy grid is extremely dependent on the electrostatic potential because the stabilization technique is required for accurate simulations. Because of this, the design of an equation system that accounts for both small signals and ambient noise is difficult to do so. We start by determining the drain excess noise factor [28] in order to address the device noise behavior.

γ=

W dd 4kbTgD 0



(6.16)

Here Wdd-PSD of noise generated by current flowing in the drain region of the device. gd0-PSD of self-admittance of drain region for Vds = 0V.

110  Nanodevices for Integrated Circuit Design

Drain Excess Noise Factor

1.0 0.8 0.6 0.4 Vgs=0.7V 0.2 0.0 0.0

0.2

0.4 0.6 Drain Voltage (V)

0.8

Figure 6.13  Variation of drain excess noise factor w.r.t. Vds of GAA-JLFET.

Figure 6.13 depicts how noise factor affects the voltage between the GAA- JLFET’s source and drain. It is observed that the noise simulation of the device matches up perfectly with the Nyquist theorem, which means that the factor Wdd is equivalent to the Johnson Nyquist noise (which is normally equal to 1). Wdd will increase in proportion to the shortening of the gate length. For Vds > Vds,sat, the drain excess noise approaches to theoretical VanderZiel limit (γ = 2 3 ) in the long-channel [29]. When the gate length of the device is increased, the PSD [30] of the device experiences a continuous and linear increase when the drain bias is increased beyond the saturation regime. However, when the Vds is held constant, the PSD barely changes at all. Now let us look in to the gate excess noise factor [31] of the device i.e.

β=

5W gg g d 0

4kbT (WC gs )

(6.17)

2



The fluctuation of β with regard to gate to source voltage for various channel lengths of GAA-JLFET is represented in Figure 6.14, which can be found below. This indicates that like, gate excess noise of shorter GAAJLFET is not necessarily greater than that of longer device. Another factor i.e. the shot noise suppression factor also termed as Fano factor [32] is being plotted on a graph in Figure 6.15. Mathematically this factor is expressed as:

RF with DC and Linearity Parameter  111

Gate Excess Noise Factor

1.0×101 8.0×100 6.0×100 4.0×100 2.0×100

Vgs=0.7V

0.0 –0.2

–0.1

0.0

0.1

0.2

Drain Voltage (V)

Figure 6.14  Variation of gate excess noise factor w.r.t. Vds of GAA-JLFET. 1.1 1.0

Fano factor

0.9 0.8 0.7 0.6 0.5 0.4 Vgs=0.7V

0.3 0.2 –0.3

–0.2

–0.1 0.0 Drain Voltage (V)

0.1

0.2

Figure 6.15  Variation of Fano factor w.r.t. Vds of GAA-JLFET.



F=

W dd 2qI dc

(6.18)

Because there aren’t many carriers in the subthreshold region of the device [33], this factor is close to 1, but it goes down when Vgs > Vth. Due to less scattering of electrons in the short channel device the non-equilibrium noise component of the device is generally suppressed as compared to long channel devices. This proves that short channel GAAJLFET device is more immune to noise.

112  Nanodevices for Integrated Circuit Design

6.4 Applications GAA-JLFET technology has become more common in a variety of applications, including electronic switches used in power management, automatic light intensity control for public lighting, and high voltage systems powered by MARX generators. They are frequently utilized in low voltage switches as well. They are utilized by firms such as semiconductor or chip design firms. In the field of semiconductor manufacturing, one of the most important applications of GAA technology is the design of integrated circuits (ICs) [34–36]. They are capable of being utilized as electronic switches for power efficiency, low wattage switches which are less than 200 V, and also able to be incorporated into devices designed to save energy such as inverters. Various uses of GAA-JLFETs are employed in smart gadgets to improve the performance of their processors. The increasing demand for electronics products is predicted to provide new opportunities for the semiconductor industry in the next years. Furthermore, they are employed in many biosensing applications for the detection of numerous viruses in real time, such as COVID SARS-2 virus, etc.

6.5 Conclusion This chapter briefly discussed about the importance of GAA-JLFET in semiconductor industry. In summary, gate-all-around transistors are the integrated circuits of the future. These devices will continue to be advantageous due to their flexible architecture, low operational voltage, high driving currents, high computational speed, and outstanding performance in a small footprint. Compared to traditional JLFETs, the GAA structure is less susceptible to noise, resulting in better device performance. Also at the same time, high value of linearity metrics makes the device less prone to intermodulation distortions, which becomes a sole cause to be utilized in various RFIC applications and also in real time biosensing fields.

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RF with DC and Linearity Parameter  113 3. Moore, G.E., Cramming more components onto integrated circuits, Reprinted from Electronics, in volume 38, number 8, pp.114 ff, April 19, 1965. IEEE Solid-State Circuits Soc. Newsl., 11, 3, 33–35, 2006, doi: 10.1109/N-SSC.2006.4785860. 4. Razavieh, A., Zeitzoff, P., Nowak, E.J., Challenges and limitations of CMOS scaling for FinFET and beyond architectures. IEEE Trans. Nanotechnol., 18, 999–1004, 2019. 5. Madadi, D. and Orouji, A.A., Investigation of short channel effects in SOI MOSFET with 20 nm channel length by a β-Ga2O3 layer. ECS J. Solid State Sci. Technol., 9, 4, 045002, 2020. 6. Clark, R., Tapily, K., Yu, K.H., Hakamata, T., Consiglio, S., O’Meara, D., Leusink, G., Perspective: New process technologies required for future devices and scaling. APL Mater., 6, 5, 058203, 2018. 7. Sahay, S. and Kumar, M.J., Junctionless field-effect transistors: Design, modeling, and simulation, John Wiley & Sons, Wiley-IEEE Press, 2019. 8. Bhuiyan, M.H., A review of the fabrication process of the pocket implanted MOSFET structure. SEU J. Sci. Eng., 14, 1, 8–27, 2020. 9. Fan, S.K., Chen, S.L., Lin, P.L., Chen, H.W., Layout strengthening the ESD performance for high-voltage n-channel lateral diffused MOSFETs. Electronics, 9, 5, 718, 2020. 10. Raut, P. and Nanda, U., RF and linearity parameter analysis of junction-less gate all around (JLGAA) MOSFETs and their dependence on gate work function. Silicon, 14, 10, 5427–5435, 2022. 11. Das, S., Chen, A., Marinella, M., Beyond CMOS. IEEE International Roadmap for Devices and Systems Outbriefs, pp. 01–129, 2021. 12. Panda, D.K., Singh, R., Lenka, T.R., Pham, T.T., Velpula, R.T., Jain, B., Nguyen, H.P.T., Single and double-gate based AlGaN/GaN MOS-HEMTs for the design of low-noise amplifiers: A comparative study. IET Circuits, Devices Syst., 14, 7, 1018–1025, 2020. 13. Hiblot, G., DIBL–compensated extraction of the channel length modulation coefficient in MOSFETs. IEEE Trans. Electron Devices, 65, 9, 4015–4018, 2018. 14. Saha, R., Panda, D.K., Goswami, R., Bhowmick, B., Baishya, S., Analysis on effect of lateral straggle on analog, high frequency and DC parameters in Ge-source DMDG TFET. Int. J. RF Microwave Comput.-Aided Eng., 31, 4, e22579, 2021. 15. Mahapatra, S. and Sharma, U., A review of hot carrier degradation in nchannel MOSFETs—Part I: Physical mechanism. IEEE Trans. Electron Devices, 67, 7, 2660–2671, 2020. 16. Mehta, V., Arya, S.K., Sharma, R., An improved performance of gate allaround junctionless FET using core–shell architecture. IETE J. Res., 1–8, 2021.

114  Nanodevices for Integrated Circuit Design 17. Raut, P. and Nanda, U., A charge-based analytical model for gate all around junction-less field effect transistor including interface traps. ECS J. Solid State Sci. Technol., 11, 5, 051006, 2022. 18. Saha, R., Goswami, R., Panda, D.K., Analysis on electrical parameters including temperature and interface trap charges in gate overlap Ge source step shape double gate TFET. Microelectron. J., 105629, 2022. 19. Panda, D.K., Singh, R., Lenka, T.R., Goyal, V., Boukortt, N.E.I., Nguyen, H.P.T., Analytical modelling of dielectric modulated negative capacitance MoS2-FET for next- generation label-free biosensor. IJNM, 2022. 20. Saha, R., Panda, D.K., Goswami, R., Bhowmick, B., Baishya, S., Analysis on effect of lateral straggle on analog, high frequency and DC parameters in Ge-source DMDG TFET. Int. J. RF Microw. Comput.-Aided Eng., 31, 4, e22579, 2021. 21. Raut, P., Nanda, U., Panda, D.K., RF with linearity and non-linearity parameter analysis of gate all around negative capacitance junction less FET (GAANC-JLFET) for different ferroelectric thickness. Phys. Scr., 97, 10, 105809, 2022. 22. Kumar, N., Purwar, V., Awasthi, H., Gupta, R., Singh, K., Dubey, S., Modeling the threshold voltage of core-and-outer gates of ultra-thin nanotube junctionless-double gate-all-around (NJL-DGAA) MOSFETs. Microelectron. J., 113, 105104, 2021. 23. Gnudi, A., Ventura, D., Baccarani, G., Odeh, F., Two-dimensional MOSFET simulation by means of a multidimensional spherical harmonics expansion of the Boltzmann transport equation. Solid-State Electron., 36, 4, 575–581, 1993. 24. Hong, S.-M., Pham, A.T., Jungemann, C., Deterministic solvers for the Boltzmann transport equation, in: Computational Microelectronics, Springer, Wien, New York, 2011. 25. Ypma, T.J., Historical development of the Newton–Raphson method. SIAM Rev., 37, 4, 531–551, 1995. 26. Löwdin, P.O., Studies in perturbation theory: Part I. An elementary iteration-variation procedure for solving the Schrödinger equation by partitioning technique. J. Mol. Spectrosc., 10, 1–6, 12–33, 1963. 27. Ruić, D. and Jungemann, C., Numerical aspects of noise simulation in MOSFETs by a Langevin–Boltzmann solver. J. Comput. Electron., 14, 1, 21–36, 2015. 28. Scholten, A.J., Tiemeijer, L.F., van Langevelde, R., Havens, R.J., Venezia, V.C., van Duijnhoven, A.T.A.Z., Neinhüs, B., Junge-mann, C., Klaassen, D.B.M., Compact modeling of drain and gate current noise for RF CMOS, in: IEEE IEDM Technical Digest, pp. 129–132, 2022. 29. Noei, M. and Jungemann, C., RF analysis and noise characterization of junctionless nanowire FETs by a Boltzmann transport equation solver. J. Comput. Electron., 18, 4, 1347–1353, 2019.

RF with DC and Linearity Parameter  115 30. Assaf, J., Extraction of noise spectral densities (intrinsic and irradiation contributions) of a charge preamplifier based on JFET. Microelectron. Reliab., 53, 5, 712–717, 2013. 31. van der Ziel, A., Noise in solid state devices and circuits, Wiley, New Jersey, 1986. 32. Ohmori, K. and Amakawa, S., Direct white noise characterization of short-channel MOSFETs. IEEE Trans. Electron Devices, 68, 4, 1478–1482, 2021. 33. Vaddi, R., Dasgupta, S., Agarwal, R.P., Device and circuit design challenges in the digital subthreshold region for ultralow-power applications. VLSI Des., 2009, Article ID 283702, 2009. https://doi.org/10.1155/2009/283702 34. Mendiratta, N. and Tripathi, S.L., 18nm n-channel and p-channel Dopingless Asymmetrical Junctionless DG-MOSFET: Low Power CMOS Based Digital and Memory Applications. Silicon, 14, 6435–6446, 2022, https://doi.org/ 10.1007/s12633-021-01417-5. 35. Kumar, T.S. and Tripathi, S.L., Comprehensive analysis of 7T SRAM cell architectures with 18nm FinFET for low power biomedical applications. Silicon, 14, 5213–5224, 2022, https://doi.org/10.1007/s12633-021-01290-2. 36. Tripathi, S.L., Sinha, S.K., Gupta, P., Design of triple material junctionless CG MOSFET. 2018 International Conference on Intelligent Circuits and Systems (ICICS), pp. 42–45, 2018, doi: 10.1109/ICICS.2018.00021.

7 E-Mode-Operated Advanced III-V Heterostructure Quantum Well Devices for Analog/RF and High-Power Switching Applications A. Mohanbabu1*, N. Vinodhkumar2, S. Maheswari3, S. Baskaran4, V. Janakiraman5, M. Saravanan6 and P. Murugapandiyan7 Department of Electronics and Communication Engineering, SRM Institute of Science and Technology, Ramapuram, Chennai, India 2 Department of Electronics and Communication Engineering, Vel Tech Rangarajan, Dr. Sagunthala R&D Institute of Science and Technology, Chennai, India 3 Department of Electronics and Communication Engineering, Panimalar Engineering College, Chennai, India 4 Department of Electronics and Communication Engineering, SKP Engineering College, Tiruvannamalai, Chennai, India 5 Department of Electronics and Communication Engineering, Dhanalakshmi Srinivasan College of Engineering and Technology, Chennai, India 6 Sri Eshwar College of Engineering, Coimbatore, Tamil Nadu, India 7 Anil Neerukonda Institute of Technology & Sciences, Visakhapatnam, Andhra Pradesh, India 1

Abstract

The most significant invention of the 20th century was the transistor. After invented the first transistor, the technology advancement based on transistor arrived very quickly in the market. Since 1960, Silicon (Si) has been the regularly used semiconductor for fabrication of transistors, due to its presence of large quantity on Earth. “Moore’s Law,” an empirical conclusion that the number of transistors on an integrated circuit with the minimum possible component cost doubles every 18 months, was first put forward by the Gordon Moore, a *Corresponding author: [email protected] Suman Lata Tripathi, Abhishek Kumar, K. Srinivasa Rao, and Prasantha R. Mudimela (eds.) Nanodevices for Integrated Circuit Design, (117–142) © 2023 Scrivener Publishing LLC

117

118  Nanodevices for Integrated Circuit Design co-founder of Intel Corporation, in the early 1960s. After 15 years, researchers believe that Moore’s law might have come to a natural end, Si based CMOS, mainstream logic technology has encountered limitations because of the inadequate chip cooling capacity due to static/dynamic power during switching that demands new channel materials with a with a much relatively high carrier transport velocity than Si [1], [2]. Si-based devices are getting close to the point where performance and chip capability can no longer be scaled up. Device scaling to nano-meter dimensions is possible with the adoption of novel semiconductor channel materials that have better transport capabilities than Si. Nowadays, researchers concentrate more on their work mainly how to minimize the transistors count used in an integrated circuit instead of minimizing the transistor size.In the next generation of III-V/Si integrated platforms, novel high electron mobility transistors (HEMTs) based on current III-V materials such as InAlN, AlGaN, AlN, InN, and GaN will be used for mixed-mode circuit design and modelling, which will be covered in this chapter.Because of technological constraints, a broader development of GaN power switching devices was required, specifically the absence of a reliable Enhancement mode (E-mode) transistor with a high positive threshold voltage VT. The E-mode operation can be approached by realizing techniques such as efficient doping in the GaN cap layer, high-κ metal-Insulator-semiconductor (MIS) with graded barrier structure, N-polar InN channel MIS-HEMT for high power, high breakdown, and high-frequency operation with a sufficiently low density of surface donors. Due to the wide range of applications, such as high speed and high-power electronics, as well as the necessity for energy conservation today, interest in the field of nitride-based devices has grown recently. Keywords:  GaN heterostructures, HEMTs, quantum devices, power switching applications, boost converter

7.1 Silicon Era and Scaling Limit The most significant invention of the 20th century was the transistor. After invented the first transistor, the technology advancement based on transistor arrived very quickly in the market. Since 1960, Silicon (Si) has been the regularly used semiconductor for fabrication of transistors, due to its presence of large quantity on Earth. Si-based devices are getting close to the point where performance and chip capability can no longer be scaled up. Device scaling to nanoscale dimensions is made possible by the introduction of novel semiconductor channel materials that have better transport capabilities than Si. Nowadays, researchers concentrate more on their work mainly how to minimize the transistors count used in an integrated circuit instead of minimizing the transistor size.

E-Mode Operated Quantum Well Devices  119 Among innovative new channel materials, GaN based III-V compound semiconductors, has become competitive against silicon in transistor fabrication. We essentially focus on III-V material based GaN HEMTs used in power conversion and switching. GaN based HEMTs have several qualities which are superior to silicon (Si) based transistors such as high strength of electric field and mobility of electron in the channel. First, GaN-based transistors have a lower ON-state resistance, which creates lower conduction losses in the circuit. Secondly, GaN based HEMT’s devices undergo less leakage losses used for power switching operation in Buck/Boost converters, Full-bridge inverters and for other applications. Thirdly, the presence of lower capacitance of GaN devices decreases the charging and discharging switching losses in the device, thus, less power is required from the driver circuit.

7.2 III-V GaN-Based Compound Semiconductors AlGaN, InAlN, InN, GaN, and their solid solutions are the III-V nitrides that are the focus of this chapter’s discussion. These materials all have wide band gaps, electron mobilities, high value of saturation velocities and large breakdown fields, and low thermal impedance when formed over SiC substrates. III-nitride material is more reliable since it also comes from chemical inertness, thermal stabilization, and radiation resistance. The nitride device’s hexagonal (Wurtzite) crystal structure results in special material qualities such as enormous direct energy band gap, excellent thermal stability, and built-in electric field due to spontaneous and piezoelectric polarization, making them perfect for electronic applications [3]. III-N based diodes and FETs are essential due to their low energy conversion loss and efficient power transmission/distribution ability at high temperature operation. The goal is to create electrical switches based on GaN that operate quickly and effectively across a range of power levels. GaN devices have high power handling capacity allows for more efficient power distribution at higher power levels and smaller device sizes, resulting in a significant decrease in chip area, gate width and power loss.

7.3 Band-Gap Engineering To overcome the material limits of Si and to realize the improvement in device performance needed to meet the necessities in the future, wide

6.0

AIN

(Wurtzite)

(Zinc Blende)

200

ZnSe AIAs GaAs

400

5.0 4.0 3.0

GaN AIP GaP

2.0 1.0 0.0 3.0

InN

3.2

3.4

3.6 5.4 5.6 A Lattice constant (Å)

InP

InAs 5.8 6.0

700

Wavelength (nm)

Band gap energy (eV)

120  Nanodevices for Integrated Circuit Design

1500

Figure 7.1  Variation of III-V material Lattice constant (Å) with Bandgap energy Eg(eV) [4, 5].

bandgap (WBG) semiconductor such as GaN have come to the fore front due to their superior physical properties. They offer superior potential advantage over Si-based devices in the areas of power switching and performance during device operation along with high withstanding temperature, and blocking voltages. Figure 7.1 clearly shows the variation of bandgap and lattice constant of the III-V compound semiconductors. The bandgap energy (Eg) of GaN (3.4 eV) can be engineered from 2.0 eV to 6.2 eV by adding indium or aluminium ternary material to GaN [5]. Hence extra degree of freedom is received from researchers to form a material by band gap Engineering.

7.4 Quantum Well Double quantum Well (QW) is a hetero interface layer with narrow band gap sandwiched between wide band gap materials; the size of the narrow band gap material should be less than the de Broglie wavelength of the electrons and holes of that material. The special movement of carrier in the quantum well is restricted to a plane of two-dimensional well, which means electrons and holes are one-dimensionally confined in a quantum well. The researcher has control over the size, depth, and configuration of the quantum mechanical potential wells due to quantum well technology. Therefore, more reliable devices can be formed using QW structures due to its unique properties such a less heat dissipation and higher efficiency.

E-Mode Operated Quantum Well Devices  121

7.5 Polarization in GaN Devices and their Specific Properties Devices with unique characteristics are created by the intense polarization effects in III-N heterostructure. The unique device is, of course, the III-N heterostructure FET, which, without further impurity doping, intrinsically provides a greater carrier concentration ns≥ 1013 cm-2 through the concept of polarization engineering and generates exceptionally high carrier concentrations in the channel [6]. For AlGaN/GaN HEMTs, the presence of Piezoelectric and Spontaneous polarization influences the channel formation and alters the output characteristics of the devices. III-V Spontaneous (Psp) and piezoelectric (Ppz) polarization are the two polarization phenomena that nitride devices can exhibit. The spontaneous nature of the Nitride (N) crystal and the strong electro-negativity of the nitrogen atom are the reason. We are known that the lack of a center of symmetry in the wurtzite crystal structure results in a net internal electric field. The existence of stress and strain effects (i.e., lattice mismatch) in the interfaces of heterostructures, estimated by [7, 8] and shown in Figure 7.2, is often what allows piezoelectric polarization to occur. Without intentional doping, piezoelectric polarization increases the channel’s electron mobility and carrier concentration to up to µ ≥ 2000 cm2/Vs, which results in lower ON-state resistance, lower loss during conduction, and improved conversion efficiency [7]. In a quantum well, the electrons are effectively confined to prevent alloy impurity scattering. GaN device shows increased electron mobility and dielectric constant make it possible to operate at high frequencies as well as to be used in optoelectronic circuits due to its fast-switching characteristics and direct band-gap property. AI N AI N Ga N Ga N

Psp

Ppz

Psp

Figure 7.2  Piezoelectric, spontaneous polarization, and lattice orientation of AlGaN/GaN crystal caused by interface strain.

122  Nanodevices for Integrated Circuit Design Table 7.1  Compares some primary factors that have a significant impact on the basic performance parameters of the devices [7–9]. Material Parameters

Si

GaAs

SiC

GaN

Band Gap Energy (eV)

1.1

1.4

3.2

3.4

Breakdown field (MV/cm)

1.5

0.5

4.9

>3.0

Thermal Conductivity (W/cm*K)

1.5

0.5

4.9

2.3

Mobility (cm2/V*s)

1300

6000

600

~2000*

Saturated Velocity (*107 cm/s)

1.0

1.3

2.0

2.7

The material qualities and their material advantages at the system and the device level were listed in Table 7.1 and Figure 7.3 [7–10]. In this chapter, an effort is made to identify the factor inducing a drop in performance that prevents GaN-based devices from being widely used. E-mode device with high VT, current density, and operating breakdown voltage for highpower switching are needed to improve the performance of III-V material based GaN devices. ADVANTAGEOUS IN POWER-SUPPLY CIRCUITS HIGH OPERATING TEMPERATURE DUE TO LARGE BANDGAP AND HIGH POTENTIAL BARRIER (ºC) 400

ADVANTAGEOUS IN POWER-SUPPLY CIRCUITS

300

GaN

200

HIGH BREAKDOWN STRENGTH DUE TO LARGE BANDGAP

100

200

300

400

0.4

10

0

2.0

0.6

ADVANTAGEOUS IN POWER-SUPPLY CIRCUITS HIGH MAXIMUM CURRENT DUE TO HIGH CARRIER DENSITY AND HIGH ELECTRON MOBILITY

0.8 1.0 1. (A/mm) 2

100

100

(V/µm)

GaAs

ADVANTAGEOUS IN RF CIRCUITS HIGH MAXIMUM OSCILLATION FREQUENCY DUE TO HIGH ELECTRIC FIELD SATURATION SPEED (GHz) AND LOW PARASITIC CAPACITY

Si 1.5 1.0 0.0 0 (dB)

ADVANTAGEOUS IN RF CIRCUITS SUPERIOR NOISE FACTOR DUE TO LOW CARRIER SCATTERING AND LOW RF LOSSES

Figure 7.3  GaN-based devices have an advantage over Si and GaAs-based counterparts currently available [10].

E-Mode Operated Quantum Well Devices  123

7.6 Strain and Lattice Mismatch in III-N Semiconductors Strain and lattice mismatch between an epitaxial layer (GaN) and device substrate are essential for analyzing the quality of material and crystal stability, as it was addressed with the effects of polarization. The lattice constant of substrate atoms (asub) and epitaxial layer lattice constants (aepitaxy) is  determined by equation that is used to calculate the lattice mismatch [11, 12].

∆a

aepitaxy

=

aepitaxy − asubstrate aepitaxy



(7.1)

In order to make nitride devices, silicon carbide (SiC), sapphire (Al2O3), silicon (Si), and aluminium nitride are frequently used substrates (AlN). AlN has the lowest lattice misfit (1%) in the epitaxial growth of GaN among these substrates, but the wafer and cost size restrictions made AlN less attractive to researchers [13]. SiC substrate has a lattice mismatch that is relatively small (3.4%) compared to the 13% mismatch between GaN and Sapphire substrate. Some researchers are exploring silicon (Si) as the substrate material irrespective of the fact that it has a significant lattice mismatch because of its cost and availability. However, because of the large lattice mismatch with the GaN epitaxy, the manufacturing of silicon-based epitaxial growth of GaN requires special consideration. All things considered, sapphire (Al2O3) is the most extensively utilized substrate for the manufacturing of devices due to its relatively low cost, resistance to oxygen erosion, and temperature stability [14].

7.7 High Electron Mobility Transistors (HEMTs) Heterostructure HEMTs, often known as GaN HEMTs, are currently the most popular and commonly utilized electronic nitride devices. They make use of undoped GaN devices shows excellent thermal stabilization, breakdown, and transport capabilities as well as the high band-gap discontinuities at the heterostructures [15, 16]. A heterostructure, as shown in Figure 7.4, is a mixture of two distinct III-V compound semiconductors with various band gaps and lattice constants. Small lattice mismatches are required. At the heterointerface, defects are produced by a large lattice mismatch. Avoiding crystal lattice

124  Nanodevices for Integrated Circuit Design Semiconductor II χSI

Semiconductor I

E

фSII

фSI

χSII

∆EC

ECI EFI EVI

∆EV Semiconductor II 2DEG ∆EC

Eo ECII EFII

EVII

Semiconductor I E

qVBII

qVBI

∆EV

qVB

EO EC EF EV

Figure 7.4  Band energy distribution at the intersection of wide and narrow bandgaps with reference to Fermi level variation [14].

imperfections is necessary since they affect the device’s electrical performance. In Figure 7.4, a huge bandgap discontinuity and a small lattice orientation are produced by the III-V material at AlxGa1-xN/GaN heterojunctions.

7.8 Two-Dimensional Electron Gas (2DEG) As previously indicated, the schematics of an energy bandgap, 2DEG, Fermi level variation of AlGaN/GaN HEMT devices is shown in Figure 7.4. The interface between high (broader) and lower (narrower) band-gap materials, where increased mobility of electron is possible, is the location where 2DEG is developed just below the heterojunction [15–17]. Chris G van defines the equation of electrons carrier conductivity in the two-­ dimensional well [18].



σ = qnsμ

(7.2)

where q denotes the charge of electron, ns sheet carrier concentration, and µ specifies the electron mobility. A heterojunction-based device’s main purpose is to abruptly alter the bandgap in the layer that meets the GaN layer, possibly leading to a broader quantum well. Figure 7.4 demonstrates clearly that even in the absence of gate voltage, a considerable amount of current starts to flow in the 2DEG channel. The magnitude of the current flow can be regulated by the gate after the positive gate voltage is supplied

E-Mode Operated Quantum Well Devices  125 to the drain, which causes a significant flow of current to flow with varying source/drain potential. The ns concentration determines the value of the drain current density (Id,sat). As ns concentration increases, the 2DEG well will consequently provide more electrons from source to drain.

7.9 AlGaN/GaN Heterostructure HEMT By altering the In or Al alloy composition in AlGaN, InAlN, and other III-Nitride ternary compound materials, band gap engineering allows for continuous band gap variation. Mole fraction “x” is typically tuned for values between 0.18 and 0.3 [19].



leadsto toGaN GaN  xx==00leads  �‘x’ x�mole fraction fraction variation variationin inAl Alx xGa Ga1-x1-xNNleads leadstoto  xx==11leads leadsto toAlN AlN 00 1) matching to biomolecules in nanogap cavities. Before immobilization of biomolecules, the nanogap cavity is filled with surrounding air (dielectric constant, air = 1). By defining an oxide layer with a height of Tbio = 9 nm and varying its dielectric constant bio = 2, 3, 4, 5, 7, the presence of biomolecules in the nanogap cavity region can be simulated. The layer’s height/thickness is chosen to correspond to the practical height of the biomolecules.

8.2.5 A Double Gate Dielectric Modulated Junctionless Tunnel Field-Effect Transistor as a Biosensor The symmetrical design of a double gate dielectric modulated junctionless tunnel field-effect transistor (DG-DM-JLTFET)-based structure is presented and explored for the first time in order to inspect labelfree recognition of biological molecules such as uricase, protein, biotin, ­aminopropyl-triethoxysilane, and others [34]. The fluctuation in the drain current, subthreshold slope, and ION/IOFF ratio have been employed as detecting parameters to recognize the sensitivity of the DG-DM-JLTFET

Top Gate

Biomolecules in the cavity

Oxide Source

Channel

Drain

Oxide Bottom Gate Region I

Region II

Region III Region IV

1 nm native SiO2

Figure 8.4  MOSFET (JL-DM-DG-MOSFET) based biosensors.

Design of FinFET as Biosensor  149 50nm 4.5nm

Source Work Function 5.93

WF 3.9 WF 4.5

3nm

0.5nm

10nm

2nm

Silicon 1e19 (cm^(-3)) (a)

2.5 nm

WF 3.9 WF 4.9

7-8nm

D R A I N

Materials SiO2 Silicon variablecode Conductor

42-43nm

Figure 8.5  Tunnel field-effect transistor (DG-DM-JLTFET)-based structure.

for biomolecule identification by employing TCAD simulation at the moment when biological molecules get immobilized in the nanocavity region. The architectures of DG-DM JLTFET and DG-DM-JLTFET biosensors are presented in Figure 8.4 and Figure 8.5 respectively.

8.3 Performance Parameters of Biosensors The variations in dielectric variation, electric field, channel potential variations, drain current are major performance parameters of FET based biosensors. The sensitivity of device is evaluated the by the percentage variation in performance in presence of biomolecules their concentration, charge type and size etc.

8.4 FinFET Designed as Biosensor Using Visual TCAD Visual TCAD software is used to design different types of transistors or MOSFETs based on their applications using 2D and 3D simulators graphically or through the scripting language. The tool provides the library of various material used for dielectric, contacts, and semiconductor regions. Methodology followed for carrying out the work: Fin Field Effect Transistor dimensional features are defined by the width and height of the fin. The gate length derived explains the “critical design dimension” that divides the nodes of the drain and source. A vertical fin is estimated

150  Nanodevices for Integrated Circuit Design over substrates from one side of the fin to the other to allow an interface between the three sides of the channel or fin. This builds the control over the channel electrically, helping to decrease Short Channel Effects (SCE) and leakage currents, thereby achieving higher on-current. The device’s functional channel length is described by adding Wfin and Hfin twice. The device should be structured in TCAD proceeding earlier to the characterization of the device. Device modeling ended in a few steps, first defining the regions and selecting the materials used for the design. In this section a FinFET is designed for detection of biomolecules and its performance is compared with similar nanowire architecture. Figure 8.6 is the structure of 18nm FinFET with SiO2 and HfO2 as oxide layers, Biotin, Keratin, Zein, Gluten and Streptavidin are the biomolecules introduced in the air cavity that acts as bio sensing element, in which the nature of device can be analyzed by evaluating the performance parameters like threshold

Define Meshing. At sourcechannel region dense meshing

Creating a device structure using Visual TCAD

Physical Model Interface (PMI)

DriftDiffusion Model

Band gap narrowing

Analysis of device through the simulations and graphs.

Lombardi’s Mobility Model

Save the mesh file. Correspondingly, .inp file would be generated.

SRH recombination

Define the electrode voltages of gate, source and drain

Figure 8.6  Methodology of device design on TCAD.

Kane’s band to band tunneling model invoked

Design of FinFET as Biosensor  151 0.000

X(um)

0.0575

0.115 0.173 0.230 0.000

Material

0.0271

Elec

Z(um) 0.0542

Al

0.0813

x

SiO2

0.108 0.000 0.0275 0.0550 Y(um) 0.0825 0.110 y

HfO2 Air Si

z

Figure 8.7  Multichannel FinFET as biosensor.

voltage, the ION/IOFF current ratio by varying different cavity lengths for better performance of FinFET. The Table 8.1 shown below gives the typical dimensions of 18nm triple gate FinFET. Figure 8.7 drain current of the suggested biosensor for neutral and charged analytes influencing positioned area respectively. It is noticed from that immobilization of neutral bio-molecules as air that is K = 1 to K > 1 for instance of biotin, the IOFF decreases suddenly from 10-13 A/µm to 10-16 A/µm along including a small alteration in ON current and it is Table 8.1  Physical parameters of 18 nm FinFET as biosensor. Device parameter

Dimension

Channel length [Lch]

18nm

Gate length [LG]

8nm

Drain, Source length [LD , LS]

3.5nm

Effective oxide thickness [Tox]

2.8205nm

Fin thickness [Tfin]

4nm

Channel doping concentration, NCh

1015/cm3

Doping concentration, NSd

1018/cm3

152  Nanodevices for Integrated Circuit Design Table 8.2  Comparison of performance characteristics of 18 nm FinFET with nanowire. Nano wire for circular gate

3-fin triple gate FinFET

Threshold voltage

0.44 V

0.48 V

Sub threshold slope

50.2 mV/decade

48.2 mV/decade

Ion/Ioff ratio

7.86 × 109

9.16 × 1010

Device type

1.00E+00 1.00E-01 1.00E-02 1.00E-03 1.00E-04 1.00E-05 1.00E-06 1.00E-07 1.00E-08 1.00E-09 1.00E-10 1.00E-11 1.00E-12 1.00E-13 1.00E-14 1.00E-15 1.00E-16

Id vs Vgs [k=1] Id vs Vgs [k=3] Id vs Vgs [k=5] Id vs Vgs [k=7] Id vs Vgs [k=10]

Id(A)

K Increases

0

0.2

0.4

0.6 Vgs(V)

0.8

1

1.2

Figure 8.8  Id-Vgs characteristics with different biomolecules of 3-finFinFET biosensor.

the order 10-4 A and OFF current is observed as 4.34 × 10-16 A/um for K = 10, established at Vgs = 1 Volts and IOFF is measured at Vgs = 0 Volts ,Vds = 1 Volts. The distance of cavity is placed at 5 nm. In Figure 8.8, drain current is plotted with respect to gate voltage in presence of biomolecules. Table 8.2 shows a comparative details of nanowire transistor and 18nm FinFET performance in terms of short channel parameter and ON/OFF current ratio.

8.5 Biosensors in Disease Detection Multiple gate FETs or FinFET are useful in detection of Coronavirus 2019, Hepatitis B virus, Alzheimer’s disease (AD), Cancer, Acute myocardial

Design of FinFET as Biosensor  153 graphene

Counter electrode

Source

Probe molecule

Drain

Neurodegenerative disease

R

HO

NH2

HO

Vg target molecule H

H HO

H

H

Cardiovascular disease

Shift in Dirac Point due to doping Shift in resistance due to doping

Gastric cancer

R

Vg

CH2OH O OH OH

Diabetes OH

OH

Figure 8.9  Biosensor application in disease detection [36].

infarction, Malaria, Nucleic acid level etc. [35]. It can help in detection of l-carnitine for identifying the effect of genetic diseases, and cardiomyopathy etc.

8.6 Conclusion The presented explored different FET based biosensors that are available for biosensing application designed and implemented by many authors and scientists. It includes the performance parameters that are affected by the presence of biomolecules along with variation of electrical characteristics under the effect of multiple biomolecules. A discussion is also presented on the use of TCAD software like Synopsis, ATLAS and Visual TCAD, etc. for evaluating the biosensors performance in virtual conditions. Also, the use of different FET based biosensors is discussed for the disease detection and biomarkers.

154  Nanodevices for Integrated Circuit Design

8.7 Acknowledgement We acknowledge TARE SERB DST (TAR/2022/000325) along with Lovely Professional University, Punjab & NITTTR, Chandigarh, India for providing all required support for this work.

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Design of FinFET as Biosensor  155 12. Gupta, N. and Chaujar, R., Optimization of high-k and gate metal workfunction for improved analog and intermodulation performance of Gate Stack (GS)-GEWE-SiNW MOSFET. Superlattices Microstruct., 97, 630–641, 2016. 13. Gupta, N., Kumar, A., Chaujar, R., Impact of channel doping and gate length on small signal behaviour of gate electrode workfunction engineered silicon nanowire MOSFET at THz frequency, pp. 192–196, 2014. 14. Madhavi, K.B. and Tripathi, S.L., Electrical characterization of highly stable 10nm triple-gate FinFET for different contacts and oxide region materials. Silicon, 14, 12281–12291, 2022, https://doi.org/10.1007/s12633-022-01935-w. 15. Tripathi, S.L., Pathak, P., Kumar, A., Saxena, S., Improved drain current with suppressed short channel effect of p + pocket double-gate MOSFET in sub-14 nm technology node. Silicon, 14, 10881–10891, 2022, https://doi. org/10.1007/s12633-022-01816-2. 16. Verma, S. and Tripathi, S.L., Impact & analysis of inverted-T shaped fin on the performance parameters of 14-nm heterojunction FinFET. Silicon, 14, 9441–9451, 2022, https://doi.org/10.1007/s12633-022-01708-5. 17. Verma, S. and Tripathi, S.L., Effect of mole fraction and fin material on performance parameter of 14 nm heterojunction Si1-xGex FinFET and application as an inverter. Silicon, 14, 8793–8804, 2022, https://doi.org/10.1007/ s12633-021-01592-5. 18. Mendiratta, N. and Tripathi, S.L., 18nm n-channel and p-channel dopingless asymmetrical junctionless DG-MOSFET: Low power CMOS based digital and memory applications. Silicon, 14, 6435–6446, 2022, https://doi. org/10.1007/s12633-021-01417-5. 19. Kumar, T.S. and Tripathi, S.L., Comprehensive analysis of 7T SRAM cell architectures with 18nm FinFET for low power biomedical applications. Silicon, 14, 5213–5224, 2022, https://doi.org/10.1007/s12633-021-01290-2. 20. Singh Patel, G., Lata Tripathi, S., Awasthi, S., Performance enhanced unsymmetrical FinFET and its applications. 2018 IEEE Electron Devices Kolkata Conference (EDKCON), pp. 222–227, 2018, doi: 10.1109/ EDKCON.2018.8770411. 21. Kumar, T.S. and Tripathi, S.L., Leakage reduction in 18 nm FinFET based 7T SRAM cell using self controllable voltage level technique. Wireless Pers. Commun., 116, 1837–1847, 2020, https://doi.org/10.1007/ s11277-020-07765-6. 22. Tripathi, S.L., Sinha, S.K., Patel, G.S., Low-power efficient p+ Si0.7Ge0.3 pocket junctionless SGTFET with varying operating conditions. J. Electron. Mater., 49, 4291–4299, 2020, https://doi.org/10.1007/s11664-020-08145-3. 23. Tripathi, S.L. and Patel, G.S., Design of low power Si0.7Ge0.3 pocket junction-less tunnel FET using below 5 nm technology. Wirel. Pers. Commun., 111, 2167–2176, 2020, https://doi.org/10.1007/s11277-019-06978-8. 24. Verma, S., Tripathi, S.L., Bassi, M., Performance analysis of FinFET device using qualitative approach for low-power applications. 2019

156  Nanodevices for Integrated Circuit Design Devices for Integrated Circuit (DevIC), pp. 84–88, 2019, doi: 10.1109/ DEVIC.2019.8783754. 25. Tripathi, S.L. and Saxena, S., Asymmetric gated Ge-Si0.7Ge0.3nHTFET and pHTFET for steep subthreshold characteristics. Int. J. Microstruct. Mater. Prop., 14, 6, 497–509, 2019. 10.1504/IJMMP.2019.10022985. 26. Tripathi, S.L., Patel, R., Agrawal, V.K., Low leakage pocket junction-less DGTFET with bio-sensing cavity region. Turk. J. Electr. Eng. Comput. Sci., 27, 4, 2466–2474, 2019, DOI:10.3906/elk-1807-186. ISSN: 1300-0632. 27. Mendiratta, N., Tripathi, S.L., Padmanaban, S., Hossain, E., Design and analysis of heavily doped n+ pocket asymmetrical junction-less double gate MOSFET for biomedical applications. Appl. Sci., 10, 7, 2499, 2020, ISSN 2076-3417, https://doi.org/10.3390/app10072499. 28. Vardhan Reddy, I.V. and Lata Tripathi, S., Double gate-pocket-junction-less tunnel field effect transistor. 2021 Devices for Integrated Circuit (DevIC), pp. 525–527, 2021, doi: 10.1109/DevIC50843.2021.9455895. 29. Mendiratta, N. and Tripathi, S.L., DG MOSFET for bio-sensing applications: A review. 2021 Devices for Integrated Circuit (DevIC), pp. 112–115, 2021, doi: 10.1109/DevIC50843.2021.9455760. 30. Kumar, A., Tripathi, M.M., Chaujar, R., Sub-30nm In2O5Sn gate electrode recessed channel MOSFET: A biosensor for early stage diagnostics. Vacuum, 164, 46–52, 2019. 31. Sharma, D., Singh, D., Pandey, S., Yadav, S., Kondekar, P.N., Comparative analysis of full-gate and short-gate dielectric modulated electrically doped tunnel-FET based biosensors. Superlattices Microstruct., 111, 767–775, 2017. 32. Patil, M., Gedam, A., Mishra, G.P., Performance assessment of a cavity on source charge plasma TFET-based biosensor. IEEE Sens. J., 21, 3, 2526–2532, 2021. 33. Rahman, E., Shadman, A., Khosru, Q., Effect of biomolecule position and fill in factor on sensitivity of a dielectric modulated double gate junctionless MOSFET biosensor. Sens. Bio-Sens. Res., 13, 49–54, 2017. 34. Wadhwa, G. and Raj, B., Design, simulation and performance analysis of JLTFET biosensor for high sensitivity. IEEE Trans. Nanotechnol., 18, 567– 574, 2019. 35. Sadighbayan, D., Hasanzadeh, M., Ghafar-Zadeh, E., Biosensing based on field-effect transistors (FET): Recent progress and challenges. TrAC Trends Anal. Chem., 133, 116067, 2020, https://doi.org/10.1016/j.trac.2020.116067. 36. Sung, D. and Koo, J., A review of BioFET’s basic principles and materials for biomedical applications. Biomed. Eng. Lett., 11, 85–96, 2021, https://doi. org/10.1007/s13534-021-00187-8.

9 Biodegradable and Flexible Electronics: Types and Applications Vrinda Gupta1*, Sachin Himalyan2 and Archit Sundriyal2 Dept. of Electronics & Communication Engineering, NIT Kurukshetra, Kurukshetra, India 2 School of VLSI Design and Embedded Systems, NIT Kurukshetra, Kurukshetra, India

1

Abstract

Due to rapid technological advancement in electronics, the constant upgrade of electronic products provides different alternatives each day, which has led to the issue of e-waste. As it harms the environment, it requires periodic monitoring to achieve sustainable development goals. Biodegradable and flexible electronics technology provides new ways of achieving it. Biodegradable electronics have led to the development of transient electronic devices as an alternative to traditional electronics, innovated with soluble, biologically compatible materials like silk protein, nanofibrils cellulose, functional elastomers, gels, and piezoelectric. This technology yields multifaceted applications for medical and diagnostic purposes, such as sensing, monitoring, and assisting the remedial process. On the other hand, flexible electronic technology deals with applications requiring high flexibility and durability. The emphasis on flexible electronic research has increased with the increasing demand for wearable and printable electronic technology. This technology has generated an innovative field of study that poses various applications in biomedical, energy, consumer electronics, IoT, and robotics. Firstly, this chapter introduces and motivates biodegradable and flexible electronics. Then it explains different materials and technologies employed for their production. Finally, the chapter explores applications, recent developments, and obstacles associated with each technology. Keywords:  Biodegradable, flexible, transient, electronics, biomedical, sustainable, wearable *Corresponding author: [email protected] Suman Lata Tripathi, Abhishek Kumar, K. Srinivasa Rao, and Prasantha R. Mudimela (eds.) Nanodevices for Integrated Circuit Design, (157–180) © 2023 Scrivener Publishing LLC

157

158  Nanodevices for Integrated Circuit Design

9.1 Introduction It has been 30 years since the 1992 Rio Earth summit, where 172 nations participated and contemplated diverse issues of concern to humankind and the ecology due to its deeds, which led to significant protocols and agreements like Kyoto and Paris. After that, sustainability became a primary goal to achieve for every nation. In order to understand our responsibility towards the forthcoming generation, sustainable development is the critical factor in achieving the same. However, one primary concern is why we have not been capable of accomplishing these goals for a long time. The human tendency to incorporate novel technology in each field results in the current and previous technology becoming redundant or obsolete, which leads to a significant roadblock in achieving sustainability called solid waste pollution. Different sources of solid waste pollution range from single-use plastic items at the consumer level to industrial wastes generated at the production level. Electronic waste contributes to a sizable portion of solid waste produced daily. Initially, mass-produced electronics were supposed to have a life span of 40 years. However, remarkable technological advances reduced it to an average lifespan of 3-4 years, as depicted in Table 9.1, meaning that consumers replace electronics every four years with appliances having new features. The amount of e-waste generated annually exceeds 50 million metric tons, averaging 7kg of e-waste per capita. Only 17.3% of this waste is collected and recycled, the rest contributing to the numerous hazards of solid waste. The conventional disposal method of e-waste primarily consists of landfilling and ignition methods, which leads to groundwater and atmospheric contamination due to heavy metals like cadmium, mercury, and lead. Figure 9.1 illustrates the effect of exposure to heavy metals in Table 9.1  Average lifespan of electronic devices [1]. Device

Average lifespan (y)

Mobile Phones

3

Desktop

5

Laptops

4

Television

10

Printers

4

Biodegradable and Flexible Electronics  159 Lead

Dioxins Decreases immunity. Affects nervous, and reproductive systems.

Copper

Causes cognitive and verbal defects majorly in children

Arsenic Carcinogenic, causes diabetes and cardiovascular diseases.

Affects respiratory system and kidneys Cadmium Mercury Affects lungs and kidneys

Affects metabolism of calcium and makes the bones weak

Figure 9.1  Health concerns due to e-waste materials.

conventional electronics. Exposure to these injurious substances poses grave health concerns, especially for the vulnerable young generation, which hinders the development and roots for irredeemable damage when exposed to these toxic elements. The severity of these problems leads to the need for research on alternative materials which are both sustainable and non-hazardous. Thorough research on different materials led to the development of transient or biodegradable electronics, resulting in multifaceted applications to tackle the concerns posed by conventional electronic waste. Figure 9.2 shows the bibliometric analysis of biodegradable and flexible electronics on a VOS viewer using Scopus. This analysis shows that significant research areas in this field are biodegradable polymers, implantable devices, nanocomposites, tissue engineering, drug delivery systems, printed electronics, wearable electronic devices, Graphene, and cellulose-­ based materials. The chapter first introduces the concept of biodegradability and its significance in sustainability, and then discusses the effects of conventional electronic material on the human body. Next, it explores the evolution and milestones in the field. A further section of the chapter contains a detailed discussion of different biodegradable and flexible materials and their applications as different components of an electronic system. Later, it presents the applications of biodegradable and flexible materials in multiple fields.

160  Nanodevices for Integrated Circuit Design

plastic products e-waste graphene nanoplatelets plastic chemical structure plastics applications textiles quantum electronics biomass elastomers amines polymer matrix composites electrospinning electronic packaging fibers water treatment polymer composite nanocomposites current

polyesters biochemistry

biodegradable polymers

moisture

high dielectric constants

light emitting diodes

printed electronics

soft electronics

substrates solar cells biocompatibility

humidity sensors humidity sensor inkjet printing

biodegra-dable materials biodegradable electronics

toxic materials transistors

thin film transistors

drug effect

fibroin

electronics

drug carriers

drug release polyester nanoparticle fibroblast article

porosity

medical applications chitosan

graphene chemicals

polymer review

biodegradability dna

cellulose

wastes electronics wastes

polymers

nanocomposite

sustainable development

organic field ef`fect transisto

tissue engineering

adhesion biotechnology

drug delivery system human ph

nanowire

animals

animal biosensing techniques devices

animal model

animal tissue brain rat

wearable electronic devices

bone regeneration physiologic monitoring

electrical equipment implantable devices

transient electronics

silicon

semiconductor biomedical devices bioresorbable materials batteries

prostheses and implants rats, sprague-dawley power supply

implantable medical devices electric double layer nam material science encapsulation layer artificial synapse switching saline water biocompatible polymer

VOSviewer

Figure 9.2  Keyword analysis of “Biodegradable and Flexible Electronics” on VOSviewer.

The last section highlights recent advances in technology. The chapter concludes by giving a chapter summary at the end.

9.2 Biodegradable and Flexible Electronics Biodegradable electronics is an innovative research area delving into neoteric materials, some of which are omnipresent, but their potential is untapped. Biodegradable electronics is a subdomain of green electronics which usually deals with the development of modern electronic devices using new materials which are biodegradable, eco-friendly, bio-compatible, and sustainable. Another term used to describe biodegradable electronics is transient electronics; transient means short-lived or temporary. The pseudonym transient electronics describes the category of electronics that can dissolve, degrade, or disintegrate gradually; this new capability of modern electronics having a controllable lifetime opens an exciting purview of previously inaccessible opportunities. The evolution of biodegradable electronic devices roots back to biodegradable materials, which have diverse applications in fields like medicine, environmental protection, electronics, and energy. Initial research explored biomedical applications only; later, it examined more sophisticated applications like sensors based on biodegradable materials, batteries, and biopolymeric electronics.

Biodegradable and Flexible Electronics  161 Source / Drain (Ag) 

Active Layer (DDFTTF)  Gate Dielectric (PVA) 

Gate (Ag)  Substrate (PLGA) 

Figure 9.3  Selected materials and device configuration for organic TFT [2].

One  of the significant studies entailing the newest dimension of biodegradable materials was the construction of organic TFT using biodegradable semiconductors and dielectrics, as depicted in Figure (9.3). This study highlighted using various biodegradable components to construct an in vivo resorbable transistor. This organic transistor consisted of DDFTTF as a semiconducting active layer material; DDFTT 5,5′-bis-(7-dodecyl-9H-­ fluoren-2-yl)-2,2′-bithiophene is a p-channel semiconductor molecule which has similar biodegradable characteristics as melanin. Silver and gold, possessing inert, biocompatible properties, were chosen as interconnect metals because of their low to minimal biofouling capability when considered for biomedical implantation applications. For the transistor substrate, 99% of the whole device mass PLGA was used; PLGA/ PLGpoly (lactic-co-glycolic acid) is a biodegradable polymer. The paper describes PLGA as having very smooth surfaces for fabrication, making it suitable for a device substrate. PVA, a biodegradable polymer having large dielectric constant and thin film processing capability, served as a dielectric for the transistor. When exposed to water, the organic transistor was water-stable and underwent no loss of electrical properties, as depicted in Table (9.2). The table infers that non-cross-linked PVA (nPVA) used as a dielectric exhibited high electron mobility and smaller threshold voltages compared to photo-cross-linked PVA (xPVA). In vitro degradation of Organic TFT over days showed the intact structural integrity of the device till 40 days; total resorption occurred in 70 days. Also, the device transformed from entirely transparent to opaque on day 10 [2]. Further studies carried out in 2012 showed exceptional outcomes in transient electronics. The fabrication of a single-crystal silicon membrane dissolving at a modest rate in PBS (Phosphate Buffer Solution) resulted in the development of entirely operational active and passive electronic devices [3]. Today the field of biodegradable electronics has emerged due

162  Nanodevices for Integrated Circuit Design Table 9.2  Electrical properties of organic TFT fabricated on PLGA substrate with nPVA and xPVA dielectrics [2]. Dielectric material Electrical property

nPVA

xPVA

Dielectric constant, k

7.6

5.20

Mobility, µ[cm2-sec-1-V-1]

0.207

0.057

Threshold voltage, VT[V]

-15.4

-18.9

to advancements in the field of transient electronics, which is closely related to material sciences. The progress in biodegradable electronics has led to the development of cellulose-based conductive polymers. Nanofiber-based electronic packaging, biodegradable skin for HMI, ink-based printed electronics, biodegradable piezoelectric sensors, silk substrate, and graphenebased electronics show that the field is fast growing and has untapped potential. The advent of modern electronics in the mid-20th century and the transistor’s invention opened doors for many applications that would be portable, smaller in size, and easier to access for future generations. This significant development replaced clumsy vacuum tubes in television and computers, changing the course of history for electronics and computers in the digital age. First designed for small portable radio applications and military equipment, transistors nowadays are indispensable for all modern technology, including telecommunications, weather forecasts, space applications, audio, and fast-generation processors. Its low power and small area requirement have enabled engineers to accommodate billions of transistors in a single chip. Since then, motivation for the nano design of transistors and other devices has been a common goal for researchers and scientists in the present era. The first calculating machines, like Analytical Engine developed by Charles Babbage, acquired considerable space. Today we access an enormous amount of memory in our computers which were considered inconceivable in earlier times. Mobile phones and laptops with much larger computing capabilities accomplish the goal of having portable electronics. With the size of the transistor reducing year by year, a new branch of nano-electronics emerged that focuses on portability, efficiency, and cost all at the same time for more sustainable electronics that can answer future challenges of humans harmoniously.

Biodegradable and Flexible Electronics  163 Flexible electronics are introduced into the scenario, creating a critical link between nature and itself to address all future challenges. Some flexible electronics developed from nature are biodegradable, which after their use can decompose, and some which are implantable can cope with human tissues when planted inside body parts. The availability of flexible electronics provides a constant source of inspiration and additional room for material advancement, which forms the basis for these devices’ architectural and operational layouts. Herein, the selected material with a specific function is nature-inspired with some additional functionality—flexible electronics of tomorrow focus on excellent mechanical properties. Flexible micro-devices are worthy of performing various kinds of humanitarian aid and diversified application markets. Fortunately, various living organisms in nature exhibit many multifunctional features and unique adaptive structures resulting from their evolution and genetic hybridization. They often leave us with precious evidence to analyze the barriers to implementing flexible electronics with incredibly upgraded characteristics. One of the essential features of flexible electronics is excellent mechanical strength to bear large stress-strain applications. It gives them the freedom to undergo a considerable change in dimensions along with their primary functions, such as power generation and environmental stimuli sensing. When combined with innovative structural design, biomaterials open new possibilities for devices with intelligent performance. For example, skin-attached wearable devices desire features like good adhesion and resistance to water. Observing protuberance in Octopus suckers, scientists have developed an artificial octopus-like patch with high water adhesion capability under dry and moist conditions on different surfaces; this is a promising approach for skin-attached wearable sensors for in vitro and in vivo signal monitoring. The environment-sensing ability, the most prominent and widespread feature in many flexible electronic devices to sense and react to atmosphere conditions, is also obtained from physically existing natural phenomena such as sunlight, pressure, lightning, temperature, and humidity. Recently, a textile-based flexible and printable material (TFPM) in printable technology has been an enticing substitute to charge devices used in daily electronics items. Printable materials are incorporated into clothing and can potentially satisfy the energy requirements of mobile electronics. It consists of solar cells of flexible nature accompanied by a light charge controller and a systematic design. Sensors and printed circuit boards with quick response, customization, and flexibility are recent innovations, including the invention of Triboelectric Nanogenerators (TENGs), which allow swift conversion of mechanical energy released into electrical one

164  Nanodevices for Integrated Circuit Design during muscular movement by the human body. In these devices, one or more electrical properties of the device material change; for example, separation is created between the surface charges of the device to develop potential differences. Values of these alternating voltage differences keep changing during body movements which are recorded and stored in a storage unit and later used as a power source for electrical devices.

9.3 Types of Materials Used for Biodegradable and Flexible Electronics A new range of flexible, biodegradable electronics with features nearly identical to traditional electronics has been made possible by intensive research in material sciences. A substrate, a conducting substance, an insulator, a dielectric, and a semiconductor are all essential parts of any electronic device. In contrast, the backplane, front plane, and encapsulating material make up the physical structure of any electronic appliance containing these electronic devices. A device’s capacity to be both flexible and biodegradable depends on the materials employed in its production. This section covers the physical characteristics of flexible and biodegradable materials that make them suitable for the intended applications.

9.3.1 Materials for Biodegradable Electronics Biodegradable electronics require naturally decomposing or dissolvable materials for different parts of the system, which leaves little to no trace after a certain amount of time. Several naturally occurring materials possess properties viable for biodegradable electronic applications. This section further discusses different materials suitable for biodegradable electronics. I. Substrates and Insulator The basis of an electronic device is its substrate. Typically, biodegradable substrates should be inexpensive, have insulating qualities, have excellent mechanical strength, and be biodegradable for medical applications. One of the first and best-known “substrates” made from natural resources is paper, it comes from plant-based cellulose in a wide variety, and the technology of manufacturing paper in large quantities with appropriate mechanical and surface properties is well-developed [4]. Paper-based electronics have revolutionized printable electronics technology and made it possible to develop fully functional electronic circuits. In the 1960s, the concept of

Biodegradable and Flexible Electronics  165 “printing circuits emerged in Westinghouse Labs through the creation of a thin film transistor (TFT) paper strip using a custom-built vacuum deposition for the project [5]. Research on surface-modified paper-based electrodes shows stable and comparatively lower resistance values (up to 80% less). Modifying paper with a polymer coating to deal with its porous nature has led to greater mechanical strength. Lin Lui et al. developed a paper-based solar cell, the first long-term biological solar cell that uses bacteria as a source of self-sustainable energy. The solar cell is fabricated on a stack of papers, providing stability and extended power life [6]. Silk is another naturally occurring fiber polymeric material used in textiles, and it consists of two main components fibroin and sericin. Silk’s biocompatible, structural, and flexible properties make it a popular material for multiple applications like sensors and smart clothing. Silk is an organic material, making it perfect for implantable sensors since it does not trigger any adverse immune response in the human body. Silk layered with a silver nanowire electrode led to the development of an (all-fiber multifunctional sensor) AFMS which provides multi-sensing capabilities like temperature, pressure, and humidity. Inorganic transistors, silk used as an insulating material for gates demonstrated greater mobilities (~ 23 cm2/Vs) in low-voltage applications [7]. Silk is a natural material that has controlled biodegradability, leaving little to no traces after being naturally or chemically decomposed, which makes it viable for biodegradable and flexible electronic devices. Gelatin is a naturally occurring hydrogel obtained from animal body parts with a chemical composition resembling collagen. Gelatin finds applications in capsules because of its suitable properties. Besides this, Gelatin can be used as a substrate alternative for plastic because it is ecofriendly, organic, and flexible, which makes it more advantageous than the latter. Gelatin substrates degrade in almost 18 days which minimizes their environmental impacts. Gelatin with a similar resistive layer has clean interfaces and robust linkage, making it stable [8]. II. Dielectrics Dielectric materials are usually electrical insulators driven by an electric field and the moving charges; these materials are an integral part of electronic devices, especially transistors and capacitors. Dielectric properties can be present in naturally occurring and synthetic materials, mainly polymers. Egg albumin is a natural protein that, when layered with Gelatin, can be used as a dielectric material in OFETs; devices fabricated with the resulting material showed exceptional electric characteristics [9]. Shellac is a resinbased natural polymer secreted from lac bugs explored as a dielectric in

166  Nanodevices for Integrated Circuit Design OFETs the comparison of the performance of shellac with PVP poly(4-vinylphenol) showed better electrical properties up to two magnitudes greater than PVP film [10]. III. Semiconductors Semiconducting materials are the key functional elements of active electronic devices; pi-conjugated molecules are widely available and are promising for semiconductor applications. Moreover, natural dyes, which are safe and eco-friendly, also contain these conjugated molecules. Nevertheless, semiconducting materials are scarce compared to other biodegradable components of electronic devices like substrates, conductors, and dielectrics. π-conjugated linear molecules function as semiconductors; β-carotene is an example of such a molecule. Devices fabricated on biodegradable plastic substrates with β-carotene and glucose as a biodegradable gate-­insulating material make genuinely “natural” OFETs [11]. Indigo, a natural dye from plants and animals, is non-toxic and biodegradable; Figure 9.4 depicts the structure of indigo. The composition of indigo is biologically stable. The solid intermolecular interactions of π-stacking reinforced by hydrogen bonding result in indigoid dyes’ excellent charge transport properties. Transportation of charge is anisotropic due to the directional nature of π-stacking. The device’s optimal performance requires a “standing-­up” conformation of the molecules with π-stacking parallel to the gate dielectric. Aliphatic materials exhibit dielectric properties, and polyethylene or tetra tetracontane are used in biodegradable electronics to achieve this property. Indigo and Tyrian purple exhibit reversible two-electron reduction and oxidation, and small band gaps (1.7 - 1.8 eV), making them applicable for OFETs and voltage inverter circuits [11]. IV. Electrodes Electrodes are responsible for carrier transportation in an electronic device; conventional electronic devices use copper, lead, and aluminum.

O H N

N H O

Figure 9.4  Chemical structure of Indigo [12].

Biodegradable and Flexible Electronics  167 as electrodes to affect the human body, as discussed earlier. For biodegradable electronic applications, noble metals and conducting biopolymers have prominent use because of their inert biological and chemical nature. For biomedical applications, the implanted sensors into the human body should not react with the body and should pass safely. Gold, Silver, Titanium, and their alloys show non-reactance with the human body in medical applications. Since these metals are not cost-effective, the research has also shifted towards metals like Magnesium, Manganese, Tungsten, and Zinc. When subjected to metabolism, these metals show inert characteristics and can also be dissolved via chemical processes, leaving little to no waste. Materials other than metals can also possess the capability to act as possible electrodes; doping certain organic polymeric compounds results in increased conductivity. Polymers, on the other hand, also exhibit exceptional flexibility; therefore, they are more favorable for fabrication. Melanin, a natural pigment polymer, has possible applications in biodegradable electronics due to its increased conductivity during hydration [13]. PEDOT, a polymer of (3,4-ethylene dioxythiophene), and styrene sulfonate are two other polymeric materials. They are versatile, with high electrical conductivity, thermal stability, and processability. It has become a concern material with applications in biomedical sensing [14].

9.3.2 Materials for Flexible Electronics The following sections discuss materials for flexible design materials prominently derived from nature with specific functional features. Progress has been made in the world in recent decades by closely going through the properties of these materials. It has enabled material scientists and engineers to emphasize design structures on these materials as their base or substrate. Some of them briefly are: I. Zinc Oxide (ZnO) Zinc Oxide is the most common inorganic semiconductor in flexible electronics because of its high electrical performance, low processing temperature, and good optical transparency. It also has a wide band gap (3.37eV), and distinct electrical, catalytic, and optical property helps in playing a vital role in sensing, energy storage, dielectric properties, and photo detecting. Accompanied by intelligent design, one can easily harness its properties in developing flexible electronics. One example where zinc oxide material finds its application is the Tree root-inspired interlocking systems [15]. Its zinc oxide implementation on nanowire arrays electrode improves static

168  Nanodevices for Integrated Circuit Design and dynamic sensitivities. Another recent advancement that includes zinc oxide is the Amorphous oxide semiconductor Indium-Gallium Zinc oxide IGZO TFTs. These TFTs exhibit outstanding mobility values, error-free signal communication, resolution, and reduced cost, making them ideal from a market point of view. Physical properties like a photo-sensitive transparent layer and an improved refractive index make it immaculate backplane material for modern-day LCD screens, offering additional portability features and thin layer width [16]. These IGZO TFTs have a slight edge over zinc oxide during layer deposition due to their amorphous phase while maintaining high mobility, low process temperature, and low current values, making them highly desirable for low-power devices. Originally developed and patented by Japanese science and technology (JST), major companies like Samsung and Sharp hold a license for these TFTs and their market applications like OLED TVs, photonic systems, and 3D nano-­ electronics [17]. II. Chitin Nanofibrils Another material suitable these days for flexible electronics is new Chitin Nanofibrils (ChNF) which exhibit desirable features due to prolonged and protracted polymer structure ideal for making solid nanomaterials. It is a naturally occurring straight-chain biomolecule generally found in mushrooms, shells of crustaceans, and arthropods [17]. Other sources such as Crabs, Lobster, Shrimp, and insects have been researched subjects in recent years. Figure 9.5 shows the structure of Chitin and Chitosan. When the R1 chain has a concentration exceeding 50%, the structure is considered chitin, and on the other hand, if the same happens with chain R2, it is considered chitosan. Original chitin consists of anti-parallel chain alignment in the molecule, creating nanofibers connected through inter/intramolecular hydrogen bonds.

4

O

6 3

OH 5

2

HO

R2

HO

O O R1

O

1

O

OH

O R1 = – NH If R1 > 50%

C

CH3

R2 = – NH2

Chitin, and if R2 > 50%

Figure 9.5  Chemical structure of Chitin & Chitosan [18].

Chitosan.

Biodegradable and Flexible Electronics  169 GREATER MOLAR MASS

GOOD ACETYLATION

PROPERTIES OF CHITIN

HIGH CRYSTALLINITY INDEX

SHORT DIAMETER

Figure 9.6  Properties of Chitin [18].

It mainly has a crystalline structure and exists in three classified forms: α-chitin, β-chitin, and γ-chitin. Due to the properties depicted in Figure 9.6, fibers made from chitin and chitosan are less costly, much more friendly, and suitable against other fibrils having synthetic nature. When undergoing acetylation (Chitosan), chitin forms a colloidal suspension that is naturally stable. It has made it possible to create strong films, hydrogels, aerogels, foams, and polymer matrices from their nanocomposites and microfibers. The extraction method of chitin primarily includes acid hydrolysis, mechanical disintegration, oxidation, and electrospinning. One of the main reasons for this material’s mechanical strength and hardness is that the outer layer is coated with protein and is embedded in a protein matrix, thus enhancing flexibility and elasticity. Naturally occurring raw chitin undergoes purification steps like demineralization, deproteinization, and decolorization. The chemical process preparation method is not suitable due to the hydrolytic degradation of the chitin during the process. Other biofriendly characteristics of chitin make it fruitful for humankind and material industry applications [19]. III. Collagen Nanofibers Collagen is a fiber-like structure in bones and cartilage, which exhibits the piezoelectric property and is responsible for generating electrical signals in response to internal forces or stress. Being a biological protein, it is a crucial component of the extracellular matrix like bones, cartilage, teeth, and blood vessel. It is actively present in body parts that provide mechanical strength and support. Collagen has become a critical substrate for flexible electronics that employs electron beam deposition using a shadow mask in their preparation techniques. It is a constituent of the protein family, all of which are found in vertebrates and have amino acids sequence of [Gly-X-Y]n.

170  Nanodevices for Integrated Circuit Design A glycine sequence has different patterns, the main features that decide the collagen type. Its type 1 forms higher-order structures called fibrils. It consists of tropocollagen comprising three peptide chains held together by hydrogen bonds. Connective tissues, the middle layer of skin, sinew, and ligament, contain collagen, a vital extracellular matrix constituent. A fibroblast is a typical cell that produces collagen type I and secretes it as a single triple helix molecule into the extracellular domain. Collagen assembles itself into micro- and macro fibrils, fibers of varying sizes and densities, and eventually into bundles of threads in the current physiological environment. However, collagen dissolves in acidic solutions and is insoluble in water and saline solutions of particular ionic strength. Gelatin is a permanently hydrolyzed kind of collagen. Gelatin differs significantly from collagen because its triple helical peptide structure “unwinds” into single peptide chains and is thus soluble in water. IV. Graphene Nanoplatelets Graphene is a single-layered carbon allotrope whose excellent properties have been a boon for material science. It is the initial two-dimensional material developed from a hexagonal honeycomb chemical structure. It has a thickness of one atom (0.34nm) and possesses unique physical properties, which, as a result, is a fundamental unit for small-sized new devices. For example, graphene ink and coating, due to its excellent thermal and conductive properties and, consequently, products such as printed electronics, RFID tags, heat sinks, intelligent labels, and packaging, all present opportunities in wearable electronics today. On the other hand, Graphene platelets (GNPs) are multigraphene-­ layered, platelet-like graphite nanocrystals that have a blackish-colored appearance and possess attractive characteristics, including high electrical conductivity, modulus, strength, high thermal conductivity, and high specific surface area.(GNPs) usually consists of single or multilayer Graphene mixed primarily with thicker graphite and is structurally midway between Graphene and graphite [21]. Graphene nanoplatelets combine largescale production and low costs with fair enough physical properties. The extraction of nanoflake powder involves the step of liquid phase exfoliation. When graphite has fewer layers (less than 10), it is considered a 2D material. Due to its high flexibility and low sheet resistance, it has gained importance for research in the world of material science [22]. It has been a great alternative to traditional rigid elements that were a challenge a few years ago. Combining with other nanomaterials, Graphene provides wide applications in devices like supercapacitors, batteries, and electrodes. It is

Biodegradable and Flexible Electronics  171 relatively easier and economical to use graphene nanoplatelets in areas of power systems because they improve the durability, capacity, the performance of installed machines.

9.4 Applications of Biodegradable and Flexible Electronic Devices As discussed earlier, various properties of biodegradable and flexible electronic devices enable numerous applications in different fields, as represented in Figure 9.7. These devices’ biological compatibility and durability are vital advantages, opening up new opportunities for biomedical applications like sensing and diagnosis, therapy, and drug delivery, which require a high degree of biocompatibility. External applications like smart textiles, wearable sensor technology, biomimicking robots, and soft actuators must be durable and flexible. Other biodegradable and flexible electronics applications include consumer electronics like curved displays, foldable smartphones, flexible wearables, and flexible organic photovoltaics.

Figure 9.7  Chemical structure of graphene nanoplatelets [20].

172  Nanodevices for Integrated Circuit Design

9.4.1 Sensing and Diagnosis Critical disease profiling requires constant monitoring of patients; invasive testing is not always preferred when frequent testing is involved. Biocompatible materials with electronic properties allow non-invasive testing, which solves the problem discussed earlier. Biodegradable electronic devices have enabled the development of a new series of sensors which does not react with biological processes and are also easy to extract after use. These include resorbable neural and heart sensors that profile neurological diseases like tumors, paralytic attacks, brain injury, and cardiovascular diseases. Kang SK et al. proposed a resorbable silicon device for monitoring and wireless transmitting cranial pressure and brain temperature data to diagnose brain injuries. This sensor does not require patient reoperation for extraction. The resorbable properties of the material used in the sensor enables it to decompose either via the in-vitro method or simply via metabolism [23]. Chunliang Zhang et al. devised a biodegradable photo-sensing device made of flexible organic material with non-toxic properties for economic and environment-friendly sensor applications [24]. Jingquan Han et al. describe a conducting polymer-based material extracted from natural sources; it contains an association of natural rubber for elasticity, nanofibers for enhanced strength, and polyaniline for electrical conductivity. This material’s durability and electrical properties make it viable for motion-sensing applications as shown in Figure 9.8 [25].

Photovoltaics  Energy storage 

Wearables  Biodegradable and flexible electronics  

Drug delivery 

Smart Textiles Sensing and Diagnostics 

Figure 9.8  Applications of biodegradable and flexible electronic devices.

Biodegradable and Flexible Electronics  173

9.4.2 Energy Storage The scarcity of energy storage devices is a big issue when it comes to renewable energy production; the potential of any renewable energy source is difficult to extract unless there is an arrangement to store the generated energy. Currently, the material used in conventional batteries is toxic and generates hazardous waste if disposed of improperly. Conducting properties of biodegradable materials discussed earlier can be used as an eco-friendly alternative to conventional materials used in energy storage. The batteries made from these materials can be safely disposed of as they leave minimal residue upon degradation. LinLiu et al. devised an environment-friendly solar cell that is paper-based; the performance of this biological solar cell is at par with conventional solar cells. They provide a cheap energy source for remote medical diagnosis applications where energy scarcity is present [26]. Tenglongmei et al. proposed a fiber-based biodegradable battery having manganese oxide, chitosan, and PDA as constituent materials. The battery is flexible and rechargeable and can be used in vivo applications to power up the biological sensors discussed in section 12.4.1.A. Poulin et al. demonstrate another innovative application of biodegradable electronics by developing an eco-friendly degradable battery for POC treatment and sensing applications. The proposed battery uses zinc, graphite, and paper substrate, which makes it biodegradable and nontoxic; one of the most significant features of this battery is that it is water activated, and the substrate, via wicking, activates the battery for use [27].

9.4.3 Smart Textiles “Smart textiles” can sense external environmental conditions and respond intelligently. It is a study that explores new possibilities for using standard fabrics in an extended way, which can sense human activities automatically and cope with the changing scenario around them. These advanced fabrics consist of electronic circuits and interconnections fabricated/woven into them, providing flexibility, increased mechanical movement, and an ideal size that is hard to obtain from present fabrication processes. All circuits and connections are drawn interior to layer and hence are less susceptible to becoming entangled or snagged by external objects [28]. The basic building block of these textiles is conductive fabrics produced by weaving the yarns in a textile structure. However, the process is complicated as it requires a periodic check to look after the comfort of a user wearing it.

174  Nanodevices for Integrated Circuit Design These interconnections of yarns allow sensors to accommodate, which plays a crucial role in additional functions over conventional purposes in these textiles. One such example of smart textile that many armies of the world use are the camouflage effect in the uniform which was first introduced to the world by the US army made with the help of their industries to meet their military expectations and needs. Nowadays, sensors employed with optical fiber are integrated into textiles and are operated along a single optical fiber using different multiplexing techniques forming multi-dimensional distributed sensing network systems [29]. They are comparatively easier to embed into textile’s structural composites for monitoring the manufacturing process and internal health conditions. Some of the notable areas of intelligent textiles are as follows:

9.4.3.1 Chameleonic Textiles These are smart textiles that change color with the change in temperature due to the chromic dyes applied on the surface changing color. Such materials that radiate color or change it due to external stimuli causing thermal inductions are called chromic materials.

9.4.3.2 Intelligent Textile Sutures When considered for medical applications, some surgical sutures have the potential to act as intelligent fibers. A suture is a thread that joins tissues or binds blood vessels. Many different kinds of sutures are innovative absorbable materials since they hold the edges of the wound together until it has healed sufficiently. The suture does not dissolve into the body’s system until that point. Over several weeks, the suture’s tensile characteristics gradually lessen as the wound heals. The suture’s bulk, however, remains  constant throughout the healing period.

9.4.3.3 Textile-Based Flexible and Printable Material As mentioned in the previous sections, TFPM finds its role in both smart textiles and, at the same time, wearable electronics. All of these have external stimuli sensing ability, adaptive nature, and capability to change their behavior according to circumstances and are classified into three textiles [29]: 1) Passive smart textiles 2) Active smart textiles 3) Very smart textile.

Biodegradable and Flexible Electronics  175 .

TFPM being an essential part of wearable electronics, the wearable electronics section discusses the application of TFPM in the further section.

9.4.4 Wearable Electronics Wearable electronics are the result of intelligent research done on materials to overcome future challenges in every field, including the medical world, where implantable electronics are essential in complex surgeries within the human body. However, wearable electronics and smart textiles resemble each other because of the common ground of applications of one on the other. This section mainly deals with part of wearable electronics, i.e., implantable electronics overlapped with smart E-skin. The development of E-Skin takes motivation from natural skin and its beautiful properties, especially that of self-healing. Inspired by sensing and reception features of natural skin, scientists have developed a “learning-mimicking-creating” LMC cycle. E-skin supports various applications like robotics, prosthetics, and human health monitoring. In E-skin development, many unique properties of the skin of different organisms are also observed, such as chameleons, mussels, and octopuses. Sensors of new kinds consist of capacitive flexible sensors that serve as a base for E-skin. External stimuli of any kind, like mechanical deformations and stress/strain, are converted into electrical signals that are caused majorly due to variations in the relative permittivity of materials, overlapping area, and separation distance. Such artificial skins detect bioelectric signals to study various cardiovascular and neurological ailments [30, 31]. The self-healing properties of many animals have also pushed researchers to go a step further in developing artificial skin that would automatically heal from any wound. There are two types of healing one is external healing, and another is internal healing. External recovery is where already present reactive reagent gets re-distributed over layers resulting in bond formation, while internal healing depends on the reorganization of material within itself. Micro-nickel microparticles and polymeric material are used in self-healing materials these days. Implantable electronics often consist of elastomers and gels that offer biodegradation due to the chemical composition or nature of the functional group present in them. Elastomers tend to have high flexibility and mechanical elasticity. Biodegradability arises from the fact that bonds present in them undergo different forms of degradation due to hydrolysis and oxidation. One such elastomer is polyester elastomer PGS, which has an ester bond that degrades under hydrolysis or enzyme action. Generally, porous materials or materials with a rough surface have high water affinity,

176  Nanodevices for Integrated Circuit Design low crystallinity, and the desired coupling. They tend to have a significant rate of hydrolysis for creating nanomaterials for use in electronics [32– 34]. Electronic fillers that blend with biodegradable elastic polymers have routinely used several inorganic nanomaterials and conjugated polymers. These fillers offer conductivity and elasticity by forming percolation networks that ensure ongoing carrier movement even when stretched. Elastomers and polymeric network structures of gels may expand in a solvent and retain a significant amount of solvent without dissolving. Different gels include gelatin-based gel and alginate-based gels that interact with soft tissues within the body, offering required ionic conduction and solubility in water simultaneously. They serve an essential role as a substrate in implantable electronics without disrupting the normal functioning of the skin and other internal organs [35].

9.5 Conclusion Flexible and biodegradable electronics offer novel concepts for the next generation of technology. They degrade biologically within the human body after a period of use, and consumer applications with appealing designs, such as foldable phones with rollable displays, to advanced electronics that make detecting disease symptoms more straightforward using artificial intelligence techniques. Trends of new methodologies for fabricating devices every year excite researchers to look for more fascinating designs in an enthralling way. Desirable properties of wearable electronics materials of tomorrow include flexibility, mechanical strength, surface adhesion, and water resistance while maintaining their eco-friendly nature, device performance, and reliability. However, the speed of new materials may not be as fast as desired; flexible electronics evolve every day. The commencement of research toward the sustainable development of biodegradable and flexible electronics can be a high-demand subject in the coming years. With surging demands for electronic devices and faster technology, there are severe limitations when dumping them biologically without harming mother earth. Other factors like limitations in design structures are also a hurdle in implementing flexible electronics, which hampers the flexibility desired in layers. Efforts in the direction of learning from nature have been the focus of researchers. Naturally occurring materials such as cellulose, starch, and silk fibroin are under consideration and thorough examination for new materials for the biodegradable electronics of tomorrow.

Biodegradable and Flexible Electronics  177 Although much has been discovered and developed, much future work is still required for biodegradable and flexible electronics to become a part of our daily life. This field of electronics has a long way to cover before delivering desired results due to certain limitations in materials properties and other device functionalities [32].

References 1. Bisoyi, B. and Das, B., An approach to en route environmentally sustainable future through green computing. Proc. of Intl. Conf. on Smart Computing and Informatics, Visakhapatnam, India, 3-4 March 2017, vol. 1, 2017. 2. Bettinger, C.J. and Bao, Z., Organic thin-film transistors fabricated on resorbable biomaterial substrates. Adv. Mater. (Deerfield Beach, Fla.), 22, 5, 651–655, 2010. 3. Hwang, S.W. et al., A physically transient form of silicon electronics. Sci. (New York, N.Y.), 337, 6102, 1640–1644, 2012. 4. Bollström, R. et al., A multilayer coated fiber-based substrate suitable for printed functionality. Org. Electron., 10, 5, 1020–1023, 2009. 5. Brody, T.P., the thin film transistor – A late flowering bloom. IEEE Trans. Electron Devices, 31, 1614–1628, 1984 6. Liu, L. and Choi, S., A paper-based biological solar cell. SLAS Technol., 25, 1, 75–81, 2020. 7. Wen, D.L., Pang, Y.X., Huang, P. et al., Silk fibroin-based wearable all-fiber multifunctional sensor for smart clothing. Adv. Fiber Mater., 4, 873–884, 2022. 8. Chang, Y.-C. et al., A biodegradable gelatinsubstrate and its application for crack suppression of flexible gelatin resistive memory device. Adv. Electron. Mater., 8, 2101014, 2022. 9. Konwar, G. et al., Solution-processed biopolymer dielectric based organic field-effect transistors for sustainable electronics. 6th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), pp. 107–109, 2022. 10. WoonBaek, S., Ha, J.-W., Yoon, M., Hwang, D.-H., Lee, J., Shellac films as a natural dielectric layer for enhanced electron transport in polymer field-­ effect transistors. ACS Appl. Mater. Interfaces, 10, 22, 18948–18955, 2018. 11. Irimia-Vladu, M. et al., Indigo - a natural pigment for high performance ambipolar organic field effect transistors and circuits. Adv. Mater., 24, 375– 380, 2012. 12. Ullrich, R., Poraj-Kobielska, M., Herold-Majumdar, O.M., Vind, J., Hofrichter, M., Synthesis of Indigo-dyes from Indole derivatives by unspecific peroxygenases and their application for in-situ dyeing. Catalysts, 11, 1–19, 2021. 13. Sharifi, M. et al., Cancer diagnosis using nanomaterials based electrochemical nanobiosensors. Biosens. Bioelectron., 126, 773–784, February 1 2019.

178  Nanodevices for Integrated Circuit Design 14. Yang, Y., Deng, H., Fu, Q., Recent progress on PEDOT: PSS based polymer blends and composites for flexible electronics and thermoelectric devices. Mater. Chem. Front., 4, 11, 3130–3152, 2020. 15. Wang, P. et al., The evolution of flexible electronics: From nature, beyond nature, and to nature. Adv. Sci., 7, 2001116, 2020. 16. Han, K., Samanta, S., Sun, C., Gong, X., Top-gate short channel amorphous indium-gallium-zinc-oxide thin film transistors with sub-1.2 nm equivalent oxide thickness. IEEE J. Electron Devices Soc., 9, 1125–1130, 2021. 17. JST signs a patent license agreement with Samsung for high-performance thin film transistor technology, JST Signs Patent License Agreement with Samsung for High-Performance Thin Film Transistor Technology-Major Entry of Japanese Basic Research Results into Global Display Industry, Retrieved November 28, 2022, from https://www.jst.go.jp/pr/announce/20110720-2/ index_e.html. 18. Yang, X., Liu, J., Pei, Y., Zheng, X., Tang, K., Recent progress in preparation and application of nano-chitin materials. Energy Environ. Mater., 3, 492–515, 2020. 19. Elieh-Ali-Komi, D. and Hamblin, M.R., Chitin and chitosan: Production and application of versatile biomedical nanomaterials. Int. J. Adv. Res. (Indore), 4, 3, 411–427, 2016Mar2016. 20. Parente, J.M., Santos, P., Valvez, S., Silva, M.P., Reis, P.N.B., The fatigue behavior of graphene composites: An overview. Proc. Struct. Integrity, 25, 282–293, 2020, ISSN 2452-3216. 21. Cataldi, P., Athanassiou, A., Bayer, I.S., Graphene nanoplatelets-based advanced materials and recent progress in sustainable applications. Appl. Sci., 8, 1438, 2018. 22. Kuan, C.-F., Chiang, C.-L., Lin, S.-H., Huang, W.-G., Hsieh, W.-Y., Shen, M.-Y., Characterization and properties of graphene nanoplatelets/XNBR nanocomposites. Polym. Polym. Compos., 26, 1, 59–68, 2018. 23. Kang, S.K. et al., Bioresorbable silicon electronic sensors for the brain. Nature, 530, 71–76, 2016. 24. Zhang, C., Cha, R., Zhang, P., Luo, H., Jiang, X., Cellulosic substrate materials with multi-scale building blocks: Fabrications, properties, and applications in bioelectronic devices. Chem. Eng. J., 430, 132562, 2016. 25. Han, J. et al., Nanocellulose-templated assembly of polyaniline in natural rubber-based hybrid elastomers toward flexible electronic conductors. Ind. Crops Prod., 28, 94–107, 2016. 26. Liu, L. and Choi, S., A paper-based biological solar cell. SLAS Technol., 25, 1, 75–81, 2020. 27. Poulin, A., Aeby, X., Nyström, G., A water-activated disposable paper battery. Sci. Rep., 12, 11919, 2022. 28. Miah, M.R. et al., Textile-based flexible and printable sensors for next generation uses and their contemporary challenges: A critical review. Sens. Actuators A: Phys., 344, 113696, 2022.

Biodegradable and Flexible Electronics  179 29. Stoppa, M. and Chiolerio, A., Wearable electronics and smart textiles: A critical review. Sensors (Basel), 14, 7, 11957–92, 2014 Jul 7. 30. Nie, B., Liu, S., Qu, Q., Zhang, Y., Zhao, M., Liu, J., Bio-inspired flexible electronics for smart E-skin. Acta Biomater., 139, 280–295, 2022. 31. Derya, B., Daniel, C., Guillermo, B., Flexible electronics: Status, challenges, and opportunities. Front. Electron., 1, 1–13, 2020. 32. Tripathi, S.L., Alvi, P.A., Subramaniam, U., Electrical and electronic devices, circuits and materials: Technological challenges and solutions, Edited book (In Press) in Scrivener Publishing, Wiley, Boca Raton, 2021, 978119750369, DOI:10.1002/9781119755104. 33. Lata Tripathi, S. and Dwivedi, S. (Eds.), Electronic devices and circuit design: Challenges and applications in the Internet of Things, 1st ed., Apple Academic Press, Boca Raton, New York, 2022, https://doi.org/10.1201/9781003145776. 34. Tripathi, S.L., Alvi, P.A., Subramaniam, U., Electrical and electronic devices, circuits and materials: Design and applications, 1st ed., CRC Press, Boca Raton, 2021, https://doi.org/10.1201/9781003097723. 35. Chen, S., Wu, Z., Chu, C., Ni, Y., Neisiany, R.E., You, Z., Biodegradable elastomers and gels for elastic electronics. Adv. Sci., 9, 2105146, 2022.

10 Novel Parameters Extraction Method of High-Speed PIN Diode for Power Integrated Circuit Sami Ghedira* and Abdelaali Fargi Laboratory of Microelectronics and Instrumentation, Department of Physics, University of Monastir, Monastir, Tunisia

Abstract

The design of a power integrated circuit requires accurate simulations to predict its behavior under different operating conditions. The accuracy of the simulation depends mainly on the types of component models and especially the associated physical parameters. However, for intellectual property reasons, the parameters of the commercialized components are not provided by the manufacturers of semiconductor devices. Moreover, the estimation methods of the majority of the physical parameters of bipolar devices are not as simple as those of unipolar devices. This book chapter aims to present a new approach to estimate the main design parameters of the power PIN diode. In this work, we are interested in the estimation of these parameters with more direct methods. The important gain expected will result from taking into account the physics of the diode in switching. In fact, our idea is to find a decoupling of the estimation of the ambipolar lifetime in forward bias, and the identification of the other parameters in reverse bias. This idea is based on two methods. The first one consists in developing a new circuit allowing the measurement of reverse switching from the diode steady state to estimate its doping profile parameters. The second step consists in estimating the ambipolar lifetime from the analysis of the voltage drop across the terminals of a diode initially polarized forward and whose current will be abruptly removed. Physical models sufficiently accurate under the conditions of the experiments have been developed. Then, the use of optimization methods can identify the technological parameters. The cost function will be based on a comparison between the experiment and the simulation. To validate our estimation method, a more complete *Corresponding author: [email protected] Suman Lata Tripathi, Abhishek Kumar, K. Srinivasa Rao, and Prasantha R. Mudimela (eds.) Nanodevices for Integrated Circuit Design, (181–210) © 2023 Scrivener Publishing LLC

181

182  Nanodevices for Integrated Circuit Design comparison between the TCAD numerical simulation and the experiment- in the case of turn-off of the diode - will be conducted on several devices. The results obtained show that our parameter extraction methodology has a high accuracy with less computation time. Keywords:  PIN diode, parameters extraction, ambipolar lifetime, OCVD, TCAD simulation, modeling

10.1 Introduction The modeling of power PIN diodes has been the focus of many works [1–10]. Several types of such models have been developed from those based on the notion of equivalent electrical circuits, to the most accurate models that use the solution of semiconductor equations (so-called exact or complete models), and through intermediates. While remaining close to the physics, these intermediates use simplifying hypotheses that make them less computationally expensive. These models require precise knowledge of technological or physical PIN diode parameters such as the ambipolar lifetime τ and the parameters of the doping profile: the effective area A of the diode, the doping ND and the width W of the central zone. The accuracy of these parameters will allow, during simulations, to provide a detailed description of the stresses undergone by the device during the switching phases and during the stationary states with a reasonable cost. Several research works have focused on the identification of these parameters. Most of these works use methods based on the analysis of transient reverse recovery measurements of the diode from the ON-state [5, 11–14]. In particular, these methods rely on the knowledge of the effective area value and the breakdown voltage value of the diode to identify the other parameters. Unfortunately, and for intellectual property reasons, the values of these parameters are not provided by the semiconductor device manufacturers. This complicates the accurate estimation of the majority of bipolar device parameters. As a result, researchers are obligated to use destructive techniques and expensive test benches. This also shows the potential interest of non-destructive methods to accurately estimate these technological parameters. Therefore, the aim of our work is to develop a novel non-destructive extraction technique to estimate the technological parameters of the power diode by more direct methods. Inspired by the classical approach, our idea is to decouple the identification of the doping profile parameters in reverse bias and the identification of the ambipolar lifetime in forward bias. In this

High-Speed PIN Diode  183 work we will present our new circuit designed to estimate the doping profile parameters (A, ND and W) from the analysis of the transient waveform in reverse switching from the thermodynamic equilibrium state of the diode. We also propose the development of a new analytical model, with state variables, describing the behavior of the bipolar diode in reverse bias. This model will take into account a more realistic doping profile than the classical abrupt junction model. This will allow us to identify the parameters of the doping profile using an automatic optimization method to minimize the difference between the experiment and the simulation. The second step is to find an accurate method to estimate the ambipolar lifetime of a diode in high injection. Several works have shown that the Open Circuit Voltage Decay (OCVD) technique is a simple method and very sensitive to the ambipolar lifetime [15]. For this purpose, we will use TCAD numerical simulations to analyze this method. This analysis will allow us to consider the non-uniform distribution of carriers in the base region of a diode under high injection to identify the ambipolar lifetime. To do this, we propose to estimate the value of the ambipolar lifetime from a comparison between the measurement and the TCAD numerical simulation of the OCVD circuit. In order to validate our work, we have developed an automatic measurement bench that will allow the transient measurement of the diode current and voltage in reverse switching. This will allow us to validate our study by comparing the experimental results with the TCAD simulation.

10.2 Review of the Technology and Physics of Power PIN Diodes The design of bipolar PIN diodes is the subject of many works. Semiconductor physics imposes important constraints for the realization of fast switching power diodes. It is therefore necessary to correctly evaluate their performance in terms of voltage drop in forward bias, breakdown voltage in reverse bias and switching speed.

10.2.1 Technological Aspect Generally, there are two main types of power diodes, hard-switching diodes (slow diodes) and very fast-switching diodes. Both types of diodes generally have the same doping profile structure, as shown in Figure 10.1.

184  Nanodevices for Integrated Circuit Design 21 20

Nmax

Pmax

19 18

A

log (Concentration (cm -3>)

17 16 15

ND

14 13 12 11

Xjp

10

XjN

W

9 8 7 6 0

20

40

60 Distance (Microns)

80

100

Figure 10.1  Typical doping profile structure of a power PIN diode and its technological parameters.

This typical structure is composed by three regions: anode, intrinsic or base region and cathode. The anode region is a high-doped P-type semiconductor (P+), base region is a low-doped N-type semiconductor (N-) and the cathode region is a high-doped N-type (N+). Fast bipolar diodes are generally designed for power conversion applications to improve the dynamic performance of the reverse recovery state. Technologically, this means reducing the width of the base region and decreasing in the value of the carrier lifetime. On the other hand, hard-switching diodes are very slow and are generally designed for applications where switching losses have a secondary role [16], and where low forward conduction losses are required.

10.2.2 Physical Aspect Due to the rapid technological evolution of semiconductor device manufacturing, industrialists require bipolar diodes with low-voltage drop in forward bias, very fast switching and high breakdown voltage in reverse bias. In this context, several studies on the physical behavior of the bipolar diode have allowed to associate the electrical constraints to the technological parameters of this component. The first constraint results from

High-Speed PIN Diode  185 the desired blocking voltage. The level of the breakdown voltage imposes a choice of the couple (doping, width) of the base region. A compromise is therefore necessary between the ON-state voltage drop and the switching speed of the diode. As a result, manufacturers of bipolar power diodes are working on solutions to satisfy these requirements. The technological dimensions that enable these trade-offs are the values of the physical parameters of the PIN diode structure shown in Figure 10.1. These parameters are the ND doping of the base region, the width(W) of the base region, the effective area (A) of the diode, and the ambipolar lifetime (τ). These same technology parameters are used in most physical models of the power diode that account for the high injection. This shows the very important potential interest in developing methods for estimating these technological parameters. To validate our identification procedure of these parameters, we have chosen Sentaurus as a reference tool. Sentaurus is a simulator marketed by the company Synopsys TCAD (Technology Compute-Aided Design) [17] that uses a numerical resolution of the semiconductor equations. The equations used are composed of the Poisson equation and the transport equations [18]: Poisson equation



q ∂E ( x , t ) = [ Γ( x ) + p( x , t ) − n( x , t )] ∂x εs

(10.1)

Electrical potential (Faraday equation)

∂ψ ( x , t ) = − E( x , t ) ∂x



(10.2)

Continuity equations



∂p 1 ∂ Jp (x ,t ) ( x , t ) = −U ( x , t ) − ∂t q ∂x



∂n 1 ∂ Jn ( x , t ) = −U( x , t ) + ( x ,t ) ∂t q ∂x

(10.3)

(10.4)

186  Nanodevices for Integrated Circuit Design where the generation-recombination rate (Shockley-Read-Hall) is:



pn − ni2 U( x , t ) = τ pn + τ n p + τ 0ni



(10.5)

Transport equations (drift and diffusion)





J p ( x , t ) = qµ p p( x , t )E( x , t ) − qD p

∂p ( x ,t ) ∂x

(10.6)

J n ( x , t ) = qµnn( x , t )E( x , t ) + qDn

∂n ( x ,t ) ∂x

(10.7)

10.3 State of the Art of PIN Diode Parameters Extraction Most of the published work on modeling and parameter extraction of power PIN diodes uses the four technology parameters of the diode doping profile of Figure 10.1: A, ND, W and τ. In [19] A. Strollo et al. propose a technique for extracting the parameters of the charge-localized model. This model consists of several parameters, not all of them have physical significance, and their extraction procedure seems to be very complex, which limits the accuracy of these parameters. In [20] X. Kang et al. detailed their procedure for extracting the physical parameters (ND, W, τ and A) of the bipolar diode. This procedure is mainly based on the electrical datasheet which does not lead to an accurate identification of the parameters. For example, to estimate ND or W, the value of the maximum reverse voltage VRM from the datasheet is used instead of the value of the breakdown voltage, VBR. In [11] an extracting procedure for technological PIN diodes parameters has been proposed. This method is based on the comparison between numerical TCAD simulations and measurements of the current and voltage waveforms during the turn-off of the device under test. This procedure follows the same approach as the one detailed in [20], but it is more complete and accurate. It considers the effects of wiring inductances in the experimental circuit and uses a more efficient method to more accurately

High-Speed PIN Diode  187 estimate the ambipolar lifetime and effective area from the reverse voltage waveform. Although this method is accurate, it uses a multi-step procedure with a very long computation time. This technique will be used for the validation of our identification method. In [21], A. Bryant et al. propose a method based on two steps for parameters extraction of the PIN diode Fourier series model. The first step consists in estimating the parameters based on a single datasheet measurement of the diode in reverse switching. The second step consists in refining these estimated parameters from an automated optimization procedure specific to PSPICE. On the one hand, the manufacturer’s technology data is not always available. On the other hand, this method is not accurate since it is based on a single non-repetitive measurement without taking into account the different experimental conditions. A parameter extraction procedure similar to [21] has been presented in [4]. In [6], A. Shaker et al. proposed a technique for extracting the PIN diode model parameters using MATLAB. The parameter extraction method uses a MATLAB optimization routine. This routine is based on a simple comparison between experimental data and MATLAB simulation of voltage and current transient waveforms, varying the model parameters to obtain a better match. This model was improved in [7] by taking into account thermal effects to obtain a dynamic electrothermal model. In this work the authors did not develop a precise method of parameter extraction, they just used existing methods to validate the diode model. It is in 2021 that Shaker et al. made an investment to present in [14] a procedure to extract the parameters of the model [7]. The method used has been improved with a global inspiration of the approach used in the procedure presented in [11], by using mathematical relations between the switching circuit parameters and the technological parameters of the diode. Indeed, the value of VRM is extracted from the datasheet to estimate W and ND of the base region. The effective area A is estimated from the value of IF current extracted from the datasheet. The carrier lifetime in high injection is also estimated using VF from the datasheet. The values lack precision and the method uses a long procedure that requires significant processing time. In all these works, the methods for extracting technological parameters of bipolar diodes are based on measurements of turn-off switching. Under these conditions, these parameters are strongly coupled to each other since the diode switches from an on-state to the off-state in reverse recovery. However, the blocking state depends on W, A and ND and the on state depends on the ambipolar lifetime. Consequently, this inevitable coupling complicates the task of simultaneous identification of these parameters and decreases their accuracy.

188  Nanodevices for Integrated Circuit Design

10.4 Proposed Method 10.4.1 Principle The objective of this work is to develop a new technique for extracting the technological parameters of the power diode based on the component’s physics. The principle of our methodology is to decouple the identification of the ambipolar lifetime from the identification of the other diode parameters. In our later works [22, 23], we have proved that we can estimate the doping profile parameters (A, ND and W) from the analysis of the transient waveforms in reverse switching from the thermodynamic-­ equilibrium state of the diode. For this purpose, we have developed a new circuit DMTVCA (Depletion Mode Transient Voltage and Current Analysis) to estimate these parameters based on a comparison between the results of measurement and Sentaurus numerical simulation. To improve this identification method, we propose in this chapter the development of a new analytical model of the bipolar diode sufficiently accurate under the conditions of the experiments. This model will take into account a two-­ exponential doping profile, more realistic than the classical abrupt junction model. This will allow us to identify the technological parameters A, ND and W using an automatic optimization method to minimize the discrepancy between experiment and simulation. In a second step, we will use the Sentaurus numerical simulation to analyze the voltage drop across an initially forward-biased diode whose current is abruptly removed (OCVD). This analysis will allow us to take into account the non-uniform distribution of the carriers in the base region of a diode in strong injection to identify the ambipolar lifetime.

10.4.2 Doping Profile Parameters Identification 10.4.2.1 Experimental Method Figure 10.2 shows the typical waveforms that can be obtained from the measurement and simulation of the DMTVCA circuit shown in Figure 10.3 [24]. The originality of this circuit is to obtain transient waveforms of voltage and current during the turn-off of a diode initially at thermodynamic equilibrium. Under these conditions, high injection is avoided and power losses and self-heating of the device during switching are limited. In this DMTVCA circuit, the inductance, LM, is inserted to smooth the current slope during the diode switching. It also reduces the effect of parasitic elements such as parasitic inductance. An RE resistor is connected in

High-Speed PIN Diode  189 0.3

(a)

(b)

0

0.2 -100

trr

0.0

Vdiode (V)

Idiode (A)

0.1

VR

-0.1

-0.2 IRM di/dt

-200

VRM

-300

-0.3 -400

-0.4 0

50

100

150 Time (ns)

200

250

0

50

100

150 Time (ns)

200

250

Figure 10.2  Waveforms of current (a) and voltage (b) of a PIN diode obtained from the DMTVCA circuit for an applied voltage VR = 200V, and these transient parameters VRM, IRM, trr and di/dt.

LM Rg

MOSFET

+

VR

C

Vdiode

– Diode Under Test

RE

Probe Model

Probe Model

Figure 10.3  Mosfet-diode reverse switching cell: DMTVCA circuit.

parallel with the diode to minimize the effect of the MOSFET leakage currents and thus ensure the initial thermodynamic state. In the simulation, the MOSFET (2SK1317) is represented by the SPICE level 3 model.

10.4.2.2 Model Description Since the TCAD numerical simulator is very expensive in terms of computation time, we need to develop a diode state variable model that is compatible with numerical optimization methods. This analytical model will be easy to implement in circuit simulators. Indeed, in reverse bias, the assumption of complete desertion of the space charge region (SCR) is given by:

190  Nanodevices for Integrated Circuit Design

|Γ| >> n, p

(10.8)

where |Γ| is the net doping profile, p is the hole profile and n is the electron profile. Figure 10.4 shows an example of a Sentaurus numerical simulation of the (SCR) in the depletion condition. The desertion assumption allows decoupling the Poisson equation from the transport equations. Therefore, an analytical solution of the Poisson equation is possible for example by using an exponential doping profile. We have therefore chosen to model the SCR extending between xD and xE. The net doping profile that we propose has the advantage of allowing an analytical solution of the Poisson equation:

Γ ( x ) = N max (exp( −



x x −W ) − 1 + exp( )) aD ae

with: aD =

(10.9)

x jp N max ln( ) ND

(10.10)

21 20 19 log (Concentration (cm -3))

18

Net doping

17 16 15 14 13 Hole profile p(x) 12 11

Electron profile e(x)

10 9 8 7 6

SCR XD 0

XE 20

40 60 Distance (Microns)

80

100

Figure 10.4  Example of Sentaurus simulation of SCR in depletion mode in the case of PIN diode for static reverse bias for VR =400V at stationary state.

High-Speed PIN Diode  191

ae =

x jN N ln( max ) ND

(10.11)

where Nmax is the concentration of the epitaxial zone, aD and ae define respectively the slopes on the side of the diffused zone and on the side of the NN+ neutral region, xjp and xjN are the depths of the P+N and NN+ junctions. To avoid excessive truncation errors, we need to normalize the state variables of the model. Also, we choose to normalize the lengths by the length aD, the potential difference in the SCR (ψe − ψD) will be normalized by the thermal potential uT, the electric field by uT/aD, and the dopant concentration by ND. The normalized Poisson equation is then written:



de = rγ ( y ) dy

(10.12)



where y corresponds to the normalized x-axis (y = x/aD), e represents the normalized electric field E (E= e uT/aD),



and γ ( y ) =

Γ( y ) ND

(10.13)

is the normalized doping and is written as follows:



γ ( y ) = exp( − y ) − 1 + exp(

aD y − W ) ae

In this case, the dimesionless number r will be defined by: r = 

(10.14)

qN D aD2 euT (10.15)

192  Nanodevices for Integrated Circuit Design

10.4.2.2.1 Boundary Conditions

The quasi-neutral region P+, on the side of the diffused layer, is non-­ uniform. Under these conditions, the diffusion current density of holes resulting from the doping gradient is far from negligible and therefore the diffusion current is compensated by a drift current resulting from the electric field:



E( x ) = uT

1 ∂ Γ( x ) Γ( x ) ∂ x

(10.16)

therefore, at the left boundary of the diffused layer, the normalized electric field is written:

e( y D ) =

1 ∂γ ( y ) γ ( y D ) ∂ y y = yD



(10.17)

and at the right boundary of the SCR, the electric field is in triangular form, and in this case, we have e(y) = 0, or in trapezoidal form, and in this case, we have the following expression (see Figure 10.5):

e( ye ) =

1 ∂γ ( y) γ ( y e ) ∂ y y = ye

(10.18)



10.4.2.2.2 Analysis of the Voltage Drop Across the Diode from TCAD Simulation

We will use Sentaurus TCAD numerical simulation to determine an analytical expression for the voltage across the diode in reverse bias. As shown in Figure 10.6, the voltage drop VD across the diode is by nature the difference in potential between the anode and the cathode:

vD = ψa – ψc

(10.19)

High-Speed PIN Diode  193 E(KV/cm)

ND cm-3

1.6 1.5

1e19

1.4

1e18

1.3 1.2 1.1

1e16

1.0

1e15

0.9

1e14

0.8 0.7 0.6 0.5 0.4 0.3 0.2

Net doping

1e17

Trapezoidal electric field

1e13

E(XE)

1e12

W

1e11

Triangular electric field

1e10 1e9

0.1

1e8

0.0

1e7

E(XD)

0

E(X)=0 20

40

x (um)

60

80

100

Figure 10.5  Evolution of the electric field for a Gaussian junction in the case of a limitation or not of the SCR. This Figure corresponds to a Sentaurus simulation of the PIN diode.

This potential is obtained from the Sentaurus simulation of the diode, for VR=40V at stationary state. Observing the Figure 10.6, we have used several intermediate potentials. This allows us to identify the different semiconductors regions of the diode. Equation (10.20) presents this decomposition of the potential at the terminals of the diode:

vD = ψa – ψc = (ψa – ψ1) + (ψ1 – ψ2) + (ψ2 – ψ3) + (ψ3 – ψ4) + (ψ4 – ψ5) + (ψ5 – ψc) (10.20) The equation (10.20) can be written as follows:



v D = ζ M1 − uT log

Pmax Nmax − uB + Rdi − uT log + ζ M2 (10.21) pa ND

194  Nanodevices for Integrated Circuit Design 21 20

Nmax

Pmax

log (Concentration (cm –3) )

19 18 17

pa

16

ND

15

na

14 13 12 11 10 9 8 7 6

(V)

XE

XD 0

20

40

60

80

100

5 5

4

3

0

UR = Rd* i

0

−5 Ohmic Contact −10 −15

Electrical Potential

−20

Ub

−25 Ohmic Contact

−30 −35

uj

a

2

1

−45

0

20

40

60 x (um)

80

100

Figure 10.6  Evolution of the power diode electric potential in reverse bias.

where: * ζ M1 = ψ a − ψ 1 et ζ M2 = ψ 5 − ψ c are respectively the voltage drops across the ohmic contacts at the anode and at the cathode. By nature, they are constant. * uB = ψ3 – ψ2 is the voltage across the SCR, * Rd * i = ψ3 – ψ4 is the voltage drop across the ohmic region in the lowdoped layer. The resistance of this region is given by:



Rd =

W − xe qAN D µn



(10.22)

High-Speed PIN Diode  195 The logarithmic terms refer to the voltage drops, related to the doping gradient in the lateral neutral regions of the diode, where pa is the hole concentration at the right boundary of SCR. The constants ζ M1 and ζ M2 depend on the contact metals used. As only their summation ζ M1 + ζ M2 is important, we will arbitrarily choose a value that simplifies the expressions. At thermodynamic equilibrium, the voltage drop across the diode is zero:

VD = 0 and i = 0

(10.23)

Classically the voltage drop across the SCR is given by:

pa0 N D u j = u = uT log 2 ni 0 B



(10.24)

Therefore, we choose:





ζ M1 = uT log

Pmax ni

(10.25)

ζ M2 = uT log

Nmax ni

(10.26)

which respects (10.21) at thermodynamic equilibrium. Taking into account equations (10.25) and (10.26), the voltage drop across the diode out of thermodynamic equilibrium is given from equation (10.21) by:



v D (t ) = uT log

pa (t )N D − uB (t ) + Rd (t )i(t ) ni2

(10.27)

The value of the concentration pa can be determined from equation x (10.14) at the left boundary of the SCR for y = y D = D . The normalized aD concentration pa is therefore given by:



 pa  a y −W   = γ= ( y D )  exp ( − y D ) − 1 + exp  D D   (10.28) ND ae   

196  Nanodevices for Integrated Circuit Design So, considering (10.28), equation (10.27) takes the following form:



= v D 2uT log

ND + uT log γ ( y D ) − uB + Rd i ni

(10.29)

In this case, it remains to determine the expression of the voltage drop uB across the SCR. This is obviously obtained by the integration of the Poisson equation.

10.4.2.2.3 Expression of the Potential in the SCR

We determine the potential Ψ(y) in the SCR from the normalized equation:



e( y) = −

1 dψ ( y) uT dy

(10.30)

The expression of the electric field can be determined from equation (10.12). So, if we designate by H(y) and I(y) the two successive primitives of γ(y): y

∫

H ( y) = γ ( z)dz ,

0

(10.31)



y

∫

I ( y ) = H ( z )dz

0

(10.32)



Then applying Gauss’s theorem to the SCR, we obtain the electric field expressions:

e(y) = r(H(y) – H(yD)) + e(yD)

(10.33)

e(ye) – e(yD) = r(H(ye) – (H(yD)),

(10.34)

where r is the dimensionless number in equation (10.15). From equation (10.30) and (10.33), we deduce the normalized height of the potential barrier uB across the SCR:

High-Speed PIN Diode  197

ψ ( y e ) −ψ ( y D ) = r  I ( ye ) − I ( y D ) − ( ye − y D )H ( y D )  uT (10.35) + ( ye − y D )e( y D )

uB = 

Taking into account the expression for the doping profile given by equation (10.14), the terms e(yD), I(ye), I(yD) and H(yD) are determined from equations (10.17), 10.(31) and (10.32) respectively, The external variable of our model will thus be represented by the voltage drop VD across the diode. It remains now to provide the equation of state for the SCR model.

10.4.2.2.4 State Equation of the SCR Model

The electrostatic charge Qe on the side of the epitaxial layer between the abscissa y = 0 and the normalized abscissa ye (see Figure 10.7) is given by: ye

∫

= Qe Q= Qr H ( ye ) r γ ( y )dy



0

(10.36)

where

Qr = qAaDND



(10.37)

log (Concentration (cm -3))

20 19 18 17

Ω P+

16 15 14 13

ND Qe

+ + + +

12 11 10 9 yD y=0

ye

Abscissa y

Figure 10.7  Schematic representation of the electrostatic charge in the SCR.

198  Nanodevices for Integrated Circuit Design Classically, under these reverse bias conditions, in the SCR, the hole current is negligible. So, the balance of charge on the volume of Figure 10.7, allows to write:



dH ( ye ) dye dQe Q= = −i r dt dye dt

(10.38)

And therefore, the equation of state of the model can be represented by this charge balance, and is then written in the following form:



dye i =− dt γ ( ye )Qr



(10.39)

where ye is the state variable of the model, and



γ ( ye ) = exp ( − ye ) − 1 + exp

aD ye − W ae

(10.40)

This state variable model can be implemented in a PACTE circuit simulator. This software allows the simulation of different components and power circuits [25]. This model will be used to identify the technological parameters W, A and ND. It has the advantage of being much faster than the TCAD numerical simulation.

10.4.2.3 Parameters Extraction Procedure To estimate the technological parameters of a commercial diode, we used an optimization method providing a minimum error between the values of the transient electrical parameters of the experiment and those of the simulation. These transient parameters are presented in Figure 10.2. The search ranges of the different model parameters are estimated versus the current and voltage rating and the diode speed. The circuit used for simulation is identical to the DMTVCA measurement circuit. Among the optimization methods integrated in the PACTE circuit simulator, we have chosen the simulated annealing method. This is a stochastic

High-Speed PIN Diode  199 search method for the absolute minimum of a cost function. It is based on an analogy between the cost function and the energy of a material undergoing cooling. The cost function is defined by



J(x) = Max(M1, M2, M3)

(10.41)

where M1, M2, M3 are the partial costs for each comparison simulation/ experiment. The partial cost M is determined from the relative variation on the transient parameters of the simulated signals and the experimental signals, e.g.



e s e s e s I RM − I RM VRM − VRM t RR (dI R / dt )e − (dI R / dt )s − t RR M= , , , e e e I RM VRM t RR (dI R / dt )e

(10.42) where the exponent e corresponds to the transient parameters of the experiment and the exponent s corresponds to the transient parameters of the simulated signals. In a second optimization phase we used the relaxation method (dichotomous search) which is a descent method and converges faster to the local minimum. The criterion chosen is the transient parameters IRM, VRM, tRR, and dIR/dt for two or three inverse switching signals, of which there must be at least one measurement under triangular field conditions, and there must be at least one measurement under trapezoidal field conditions. Therefore, we have applied this identification method on several measurement cases for each diode at different voltages. Figures 10.8 and 10.9 show the comparison results obtained between the analytical model simulation, the experiment and the Sentaurus numerical simulation for two measurement cases of the STTA1206D diode (12A, 600V) in reverse bias. Table 10.1 shows the results of the relative errors on the transient parameters for three measurement cases of the STTA1206D diode. These good results allowed the identification of the parameters of several commercialized diodes and in particular for the STTA1206D diode, these parameters are given by Table 10.2:

200  Nanodevices for Integrated Circuit Design (V)

v

0

/test/D.u

stadi200.x : voltage

v

−200 −400 −600

0

(A) 0.75 0.50

25 i

/test/D.i

50

75 t (ns)

100

125

150

stadi200.x : current

i

0.25 0.00 −0.25 −0.50 −0.75

0

25

50

75 t (ns)

100

125

150

Figure 10.8  Comparison results between DMTVCA measurement (black), analytical model (red), and numerical simulation (blue) at voltage Vr=200V for STTA1206D diode. (V) 200 0

vd

/test/D.u

v

stadi400.x : voltage

–200 –400 –600 –800 –1000 (A)

0

25 id

1.0 0.5

/test/D.i

50

75 t (ns)

100

i

125

150

stadi400.x : current

0.0 −0.5 −1.0 −1.5

0

25

50

75 t (ns)

100

125

150

Figure 10.9  Comparison results between DMTVCA measurement (red), analytical model (black), and numerical simulation (blue) at an applied voltage Vr=400V for the STTA1206D diode.

High-Speed PIN Diode  201 Table 10.1  Relative variation between simulation (Sentaurus and model) and experiment for the transient parameters in the three cases of measurement of the STTA1206D diode. VR = 50V

VR = 200V

VR = 400V

Measure

TCAD Model TCAD (%) (%) Measure (%)

Model (%)

Measure

TCAD (%)

Model (%)

I (mA) RM

211

0,05

0,9

617

1,4

1,5

1.04

0,19

0,96

V (V) RM

125

0,02

1,1

493

2

1,1

814

0,02

0.3

t (ns) RR

28,6

1,9

1,4

24,36

1,6

1,4

21,68

0,5

0,41

dI /dt(A/ 25,6 R µs)

0,9

1,5

90,4

2.2

2,3

146,56

2,6

0,75

Table 10.2  Values of the parameters A, W and ND obtained with the identification procedure. Parameters

A (mm²)

ND (cm-3)

W (µm)

STTA1206D

4,84

2 1014

35

STTA81200

6

1.2 1014

90

STTB506

3.65

3 1014

50

SiC diode

1.2

7.65 1014

42

10.4.3 Ambipolar Lifetime Estimation 10.4.3.1 Experimental Method The OCVD method is a simple method, widely used to measure the ambipolar lifetime [26–28]. This method consists of annulling the forward current flowing through the diode and observing the rate of variation of the forward voltage drop across the diode. Therefore, the lifetime can be calculated directly from the slope of the voltage drop at the time of the interruption of the direct current in the diode. In this case, the expression of the ambipolar lifetime given by Wilson in [15], is written in the following form:



τ = 2uT

∆t ∆v D

(10.43)

202  Nanodevices for Integrated Circuit Design K D

R +

–

Figure 10.10  Circuit used in the OCVD method.

The circuit we used in this method is shown in Figure 10.10. The switch K is a mechanical mercury relay. The interest of using such a relay is to have a very fast cut-off of the current. The time of its cutoff must be much lower than the value of the ambipolar lifetime. Indeed, the speed of this relay allowed us to have a time of cut of current of the order of 10ns. This allows us to have a good accuracy on the estimation of the ambipolar lifetime for ultra-fast diodes.

10.4.3.2 Numerical Analysis of OCVD Method It is well known that, in forward bias, the base region of a power diode goes into the high injection condition, where the hole concentration is given by the following one-dimensional diffusion equation:



p( x , t ) ∂p ∂2p ( x ,t ) = D 2 ( x ,t ) − ∂t ∂x τ

(10.44)

Under OCVD conditions, the current is cancelled out very quickly, and the assumption to simplify equation (10.44) is based on the negligible variation of the hole concentration in space, to assume that p(x, t) = p(t). In this case the ambipolar diffusion equation is written in the following simplified form:

∂p p =− ∂t τ





i.e.

 d ln p dv D  1 = − * dt  τ  dv D

(10.45)

(10.46)

High-Speed PIN Diode  203 According to the Boltzmann approximation, we have

pn = p 2 = ni2 exp(



vD ) uT

(10.47)

Deriving the expression (10.47) in accordance to vD we obtain:

d ln p 1 = dv D 2uT



(10.48)

3.00

Thus substituting (10.48) into (10.46), we obtain the expression for the ambipolar lifetime given by equation (10.43). Thus, this analytic expression assumes a uniform concentration profile in the high-injection region in the static state. This simplifies the ambipolar diffusion partial differential equation into an ordinary differential equation. To analyze the accuracy of the analytical expression of the ambipolar lifetime, we have plotted the profile of the carrier concentration in the high injection region from Sentaurus numerical simulation (Figure 10.11). This simulation shows that the concentration profile is not uniform in this

Concentration (cmt-3) x1016 1.00 2.00

p(t0, x)

0.00

n(t0, x)

0

20

40 60 Distance (Microns)

80

100

Figure 10.11  Minorities concentration profile in the base of the diode at the stationary state obtained from the TCAD simulation in the case of the OCVD method.

204  Nanodevices for Integrated Circuit Design region. Note that the simulation obtained in Figure 10.11, was performed for the values of technological parameters of the diode in high injection. We chose the OCVD method to estimate the ambipolar lifetime value in high injection, because this method simply provides VD(t) signals that are very sensitive to the ambipolar lifetime. Our proposal is to compare the measured voltage drop transient characteristic with that simulated from the TCAD Sentaurus simulation. This will take into account the non-­ uniformity of the concentration profile in the intrinsic region, when the diode undergoes the current cut-off. Table 10.3 shows the result of ambipolar lifetime identifications obtained for the diodes corresponding to Table 10.2. Table 10.3  Ambipolar lifetime values for different power diodes obtained by OCVD Method. Diodes PIN

STTA1206D

STTA81200

STTB506

SiC diode

τ (ns)

110

200

250

41

(A) 1.2 1.0

i

graph0.x : current

/test/D.u

0.8 0.6 0.4 0.2 0.0 0.45 (V)

1.0

0.55

0.50 /test/D.u

t (us)

0.60

v

0.65

0.70

graph0.x : voltage

0.8 0.6 0.4 0.2 0.45

0.50

0.55

t (us)

0.60

0.65

0.70

Figure 10.12  Comparison between OCVD measures (red) and those obtained with the TCAD numerical simulation (blue), for the case of STTA1206D diode.

High-Speed PIN Diode  205

10.4.3.3 Parameters Extraction Procedure Taking into account the technological parameters identified in Table 10.2, a comparison between the voltage drop simulated with the Sentaurus model and that obtained from the experiment allows us to estimate the value of the lifetime which will be equal to 110ns. For a difference of 30% we obtain the value of the lifetime from the calculation of the slope by the OCVD method, which is equal to 140ns.The criterion for optimizing the ambipolar lifetime is based on the value of the forward current in the diode, the slope of the cutoff of this current and the slope of the voltage drop when the current is equal to zero. Figure 10.12 shows a comparison between the measured forward voltage drop and the one simulated with Sentaurus to determine the ambipolar lifetime of the STTA1206D diode.

10.5 Validation The validation of our technique of identification of the technological parameters of the power diodes is based on a comparative study between the numerical simulation TCAD and the measurements of the transient characteristics of the turn-off of a diode. To characterize the power diode at turn-off, we used a chopper circuit as a measurement circuit and for simulation. This circuit is presented on Figure 10.13:

LD

VR R

C

D IF

M1

IRF740

Figure 10.13  Test circuit of the power PIN diode in turn-off.

M2 IGBT

206  Nanodevices for Integrated Circuit Design This circuit is composed of a current source and a voltage source, a command switch M1 and a spontaneous switch which is the diode D to test. The sources are driven by the GPIB bus. The M1 switch is a fast MOS (IRF740) which is relieved by an M2 IGBT. The IGBT provides most of the power dissipation and conducts most of the time during the 50ms switching period. To avoid heating up the diode, it conducts for a very short time: a few microseconds. During the conduction of the diode, the direct current IF is positive, so the voltage generator must consume energy. This results in charging the capacitor C. This causes problems with the regulation of the voltage source VR which is not reversible in current. To avoid this problem, we have added a resistor R in the test circuit, in parallel with the VR source. The following Figures (Figure 10.14 and Figure 10.15) show a comparison between the numerical simulation TCAD and the experiment for two cases of measurement with the diode STTA1206D. In the numerical simulation we have taken into account the technological parameters obtained with our method for the diode STTA1206D. (A)

i

2

i

m501A.x : current

0

−2

−4

(V)

0

50 v

50

100 t (ns)

150

200

m501A.x : voltage

v

0 –50 –100 –150

0

50

100 t (ns)

150

200

Figure 10.14  Comparison between TCAD simulation (blue) and measurement (red) of switching at opening of the STTA1206D diode for the case (IF = 1A, VR = 50V).

High-Speed PIN Diode  207 (A)

i

4

i

mes1001A.x : voltage

2 0 –2 –4 –6

0

(V)

50 0 –50 –100 –150 –200 –250 –300 –350

50 v

0

v

50

100 t (ns)

150

100 t (ns)

150

200

mes1001A.x : voltage

200

Figure 10.15  Comparison between TCAD simulation (blue) and measurement (red) of switching at opening of the STTA1206D diode for the case (IF = 1A, VR = 100V).

10.6 Conclusion In this chapter we have presented a method for identifying the technological parameters of a power diode in two steps. In the first step, we have shown that the doping parameters ND, W and A can be estimated from the analysis of transient signals related to two or three reverse switches from the off state. For this purpose, we have developed the DMTVCA circuit and the corresponding analytical model. This model showed a very good correspondence with the complete Sentaurus model and with the experimental results. These good results come from the consideration of a more realistic doping profile compared to the abrupt junction model. This allowed us to identify the parameters of the doping profile by using an optimization method to minimize the error between experiment and simulation. Note also that our technique allows for a smooth and low noise measurement. In the second step, we analyze the voltage drop across a diode that is initially polarized forward and whose current is abruptly removed (OCVD). This allowed us to identify the ambipolar lifetime from a comparison between measurement and numerical simulation that showed a very good match.

208  Nanodevices for Integrated Circuit Design Finally, we have developed an automatic measurement bench that allows the measurement of the current and voltage of the diode in transient switching. This allowed us to validate our study by comparing the experimental results with the numerical simulation of the diodes identified from our method. Our work provides a simple method that allows such identification from flexible and non-destructive measurements. Note that this method of estimating technological parameters is used to build a library of components for analytical models of the power diode.

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11 Edge AI – A Promising Technology Remya R.1, Nalesh S.2 and Kala S.1* Department of ECE, Indian Institute of Information Technology Kottayam, Kerala, India 2 Department of Electronics, Cochin University of Science and Technology, Kerala, India

1

Abstract

Edge Artificial Intelligence (Edge AI) has become the buzzword for every industry organization. Edge intelligence utilizes edge computing to access and analyze the data from locally harvested areas and use artificial intelligence (AI) that enables the machine to make accurate decisions and predictions of such data. Two significant reasons for the efficacy of the deployment of AI models at the edge are innovations of sophisticated computing frameworks like Deep Neural Networks (DNNs) and advances in computing infrastructure. The challenges of deploying DNNs on edge are their huge memory requirement and computational complexity. DNN Compression techniques minimize the number of parameters and bits required without much accuracy loss. It reduces the memory and bandwidth requirements of the DNNs to best fit edge devices. In this chapter, we discuss different DNN model compression techniques and devices best suited for acceleration, considering multiple factors like the type of compressions and device characteristics. Keywords:  DNN, CNN, RNN, pruning, knowledge distillation, low-rank factorization, quantization

11.1 Introduction Edge intelligence is the integration of artificial intelligence and edge computing. Edge computing is an advancement of cloud computing that brings the computation, data storage, data transfer, and power, closer to the *Corresponding author: [email protected] Suman Lata Tripathi, Abhishek Kumar, K. Srinivasa Rao, and Prasantha R. Mudimela (eds.) Nanodevices for Integrated Circuit Design, (211–226) © 2023 Scrivener Publishing LLC

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212  Nanodevices for Integrated Circuit Design occurrence of an event rather than from a central data server. The benefits of edge computing are speed, security, scalability, cost-effectiveness and reliability. Two significant reasons for the efficacy of the deployment of AI models at the edge are innovations of sophisticated computing frameworks like Deep Neural Networks and advances in computing infrastructure [1]. DNNs are classified as Convolutional Neural Networks (CNNs) and Recurrent Neural networks (RNNs). CNNs are commonly used in solving problems related to spatial data such as images, whereas RNNs are better suited for analyzing temporal data such as videos. These data-driven models yield good accuracy due to the plethora of data generated in video surveillance, medical imaging, time-stamped data from sensors etc. [2]. The challenges of deploying DNNs on edge are their huge memory requirement and computational complexity. The inference time of DNNs can be reduced by compressing the network to minimize the number of parameters and bits required without much accuracy reduction. It reduces the memory and bandwidth requirements of DNNs to best fit edge devices. Pruning, Low-Rank Factorization, Quantization and Knowledge Distillation are four different basic compression techniques in the domain of DNNs to reduce the number of parameters and bits [3, 31]. Heterogeneous computing is the technique where different types of processors with different data-path architectures are applied to optimize the execution of specific computational workloads. Traditional CPUs are often inefficient for kinds of computational workloads like DNNs. System operation can be optimized by adding additional processing resources like Graphics Processing Units (GPUs) and Field Programmable Gate Arrays (FPGAs). Though DNNs are computationally complex, the parallelism involved in these models is best suited for various accelerators like FPGAs and GPUs [4, 5]. Unlike GPUs or Application Specific Integrated Circuits (ASICs), FPGAs are reconfigurable architectures. This capability makes FPGAs an excellent alternative to ASICs, which require a long development time and a significant investment to design and fabricate. GPUs are specialized processing cores that can be used to speed up computational tasks. It uses a SIMD architecture which makes it well-suited for deep learning computations, which require the same process to be performed for numerous data items. Several deep learning frameworks, such as Pytorch and TensorFlow, abstract the complexities of programming directly with Compute Unified

Edge AI – A Promising Technology  213 Device Architecture (CUDA) and have made GPU processing accessible to modern deep learning implementations [6, 7].

11.2 Deep Neural Networks Deep Learning is a sub-field of machine learning in AI that deals with algorithms inspired by the biological structure and functioning of a brain to build machines with intelligence. A simplified version of a Deep Neural Network is a layered organization of neurons (similar to the neurons in the brain) with connections to other neurons. These neurons pass information to other neurons based on the received input and form a complex network that learns with some feedback mechanism. Figure 11.1 represents an N-layered Deep Neural Network. Typically there are three types of DNNs, as given below. • Multi-Layer Perceptrons (MLP) • Convolutional Neural Networks (CNN) • Recurrent Neural Networks (RNN)

Input Layer

Output Layer

Layer N Hidden Layers Layer 1

Figure 11.1  Deep neural network.

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11.2.1 Multi-Layer Perceptrons (MLP) The simplest kind of feed-forward network is a multilayer perceptron (MLP), and has the architecture as shown in Figure 11.1. Here, the units are arranged into a set of layers, and each layer contains some number of identical units. Every unit in one layer is connected to every unit in the next layer; we say that the network is fully connected. The first layer is the input layer, and its units take the values of the input features. The last layer is the output layer, and it has one unit for each value the network outputs. All the layers in between these are known as hidden layers, because we do not know ahead of time what these units should compute, and this needs to be discovered during learning. The units in these layers are known as input units, output units, and hidden units, respectively. The number of layers is known as the depth, and the number of units in a layer is known as the width. The first layer of perceptrons in the hidden layer will take the input features and build linear models. These linear models are passed as input to perceptrons in the next layer of the hidden layer. These perceptrons sum together the linear input models and give non-linear output models. The more layers in the hidden layer, the more complex non-linear models we can find. These models are combined at the output layer to give a final model capable of classifying input data points. Deep learning refers to training neural nets with many layers. As the number of layers increases, the parameters associated with it also increase, and so is the size of the network.

11.2.2 Convolutional Neural Networks (CNNs) Convolutional neural networks are distinguished from other neural networks by their superior performance with image, speech, or audio signal inputs. They have three main types of layers, as follows: • Convolutional layer • Pooling layer • Fully-connected (FC) layer The convolutional layer is the first layer of a convolutional neural network. Additional convolutional or pooling layers can be the hidden layers and fully-connected layers towards the end of the network. With each increase in layer count, the CNN increases complexity and identifies more significant portions of the image. Initial layers focus on superficial features,

Edge AI – A Promising Technology  215 Table 11.1  Computational complexity of CNNs. Model

Input size

Parameter

FLOPs

Top1/Top2 error

AlexNet

227×227

233 MB

727M

41.80/19.20

Vgg19

224×224

548 MB

20G

28.70/9.90

ResNet152

224×224

230 MB

11G

23/6.70

GoogleNet

224×224

51 MB

2G

34.20/12.90

DenseNet

224×224

77 MB

4G

22.80/6.40

such as colors and edges. As the image data progresses through the layers of the CNN, it starts to recognize more significant elements or shapes of the object until it finally identifies the intended object. ResNet, GoogleNet, DenseNet etc. are a few state-of-the-art CNNs which can yield an acceptable accuracy, but with millions of parameters, a few MBs of trained network size and billions of floating point operations (FLOPs). To increase the accuracy of the networks, different types of interconnections are used in these models, such as skip connections in ResNet and inception modules in GoogleNet etc. Table 11.1 gives the computational complexity of CNNs.

11.2.3 Recurrent Neural Networks (RNNs) RNNs are deep learning models that deal with temporal data, which may contain observations collected for a defined time frame as shown in Figure 11.2. These sequences can pertain to weather reading, customers’ shopping patterns, word sequence, etc. Manual analysis of such sequences can be challenging as an overwhelming amount of data becomes available,

Y

H

Y1

Y2

Y3

Yt

H1

H2

H3

Ht

X1

X2

X3

Xt

Unfold X

Time

Figure 11.2  Unrolled recurrent neural network [10].

216  Nanodevices for Integrated Circuit Design and finding patterns in the data becomes problematic. RNN is a popular deep-learning technique for analyzing and predicting outcomes for time-series data. Multiple variants, such as Long Short-Term Memory (LSTM), Gated Feedback Recurrent Neural Networks (GRU) etc., are available for different applications [8–10]. Figure 11.2 shows the basic architecture of an RNN, which has feedback loops unlike CNN.

11.3 Model Compression Techniques for Deep Learning Model compression aims to achieve a simplified model from the original without significantly diminished accuracy. Size reduction  means that the compressed model has fewer and/or smaller parameters and thus, uses less RAM when run [11, 12]. A  latency reduction  is a decrease in the time it takes for the model to make an inference based on an input to the trained model, typically translating to lower energy consumption at runtime. Model size and latency often go hand-in-hand because larger models require more memory access. Both types of reduction are desirable for deploying models where computing resources face strict size and power constraints [13, 14]. The following are some popular, heavily researched methods for achieving compressed models: • • • •

Pruning Quantization Low-rank approximation and sparsity Knowledge distillation

11.3.1 Pruning Structured and Unstructured Pruning Pruning techniques are used to remove the redundant parameters of a DNN. The motivation behind pruning is that networks tend to be over-­ parameterized, with multiple features encoding nearly the same information. So, cutting off redundant parameters will not reduce the accuracy but the size of the network [15, 16]. Pruning can be divided into two types based on the type of network component removed:  unstructured pruning involves removing individual weights or links as shown in Figure 11.3. In contrast, structured pruning involves removing entire channels or filters [17], as shown in Figure 11.4.

Edge AI – A Promising Technology  217

Input Layer

Output Layer

Layer N Hidden Layers Layer 1

Figure 11.3  Weight pruning.

Input Layer

Output Layer

Layer N Hidden Layers Layer 1

Figure 11.4  Structured pruning.

11.3.2 Quantization The fundamental idea behind quantization is that converting the weights and inputs into integer types consumes less memory, and the calculations are faster on particular hardware. However, we can lose significant accuracy if not chosen appropriately [18]. There are different quantization

0.657

0.637

0.772

0.768

MobileNet V1 0.709

MobileNetV2 0.719

0.78

InceptionV3

ResNetV2_101 0.77

Model

Top1 accuracy Top1 (Post accuracy training (Original) quantized)

N/A

0.775

0.709

0.70

3973

1130

89

124

Top1 accuracy (Quantization Latency aware (Original) training) (ms)

Table 11.2  Effect of quantization on network models.

2868

845

98

112

N/A

543

54

64

178.3

95.7

14

16.9

44.9

23.9

3.6

4.3

Latency Latency (Post (Quantization training aware Size Size quantized) training) (Original) (Optimized) (ms) (ms) (MB) (MB)

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Edge AI – A Promising Technology  219 techniques in the literature to get a small model with acceptable accuracy. Table 11.2 shows the effect of quantization on a few sample models, as given in Tensorflow Lite documentation.

11.3.3 Low Rank Factorization The rank of a matrix is defined as the dimension of the vector space spanned by its columns, which is equal to its number of linearly-independent columns. That is, if an element of a matrix can be computed using others that are present, there is some redundancy of information occurring in the matrix. Since low-rank matrices encode redundant data, we can use them to approximate the redundant layers of a network, which is what low-rank approximation does [19]. The goal is to reduce the computational complexity of computing operations in a DNN by approximating the N full-rank filters with a linear combination of M lower-rank filters where M