JUNE 2012 IEEE MTT-V060-I06 (2012-06B) [60, 6 ed.]

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JUNE 2012

VOLUME 60

NUMBER 6

IETMAB

(ISSN 0018-9480)

PART II OF TWO PARTS

SPECIAL ISSUE ON POWER AMPLIFIERS Guest Editorial .... ......... ........ ......... ......... ......... ......... ......... ........ ......... ......... .. Z. Popovic´ and B. Kim

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PAPERS

Electron Devices and Device Modeling LDMOS Technology for RF Power Amplifiers (Invited Paper) .. ......... ........ . S. J. C. H. Theeuwen and J. H. Qureshi Hybrid and Monolithic RF Integrated Circuits A Review of GaN on SiC High Electron-Mobility Power Transistors and MMICs (Invited Paper) ..... ......... ......... .. .. ........ ......... ......... ........ ......... . R. S. Pengelly, S. M. Wood, J. W. Milligan, S. T. Sheppard, and W. L. Pribble Design of CMOS Power Amplifiers (Invited Paper) ..... ......... ......... ... A. M. Niknejad, D. Chowdhury, and J. Chen Controlling Active Load–Pull in a Dual-Input Inverse Load Modulated Doherty Architecture .. ........ ......... ......... .. .. ........ .. T. M. Hone, S. Bensmida, K. A. Morris, M. A. Beach, J. P. McGeehan, J. Lees, J. Benedikt, and P. J. Tasker 12-W -Band MMIC HPA and Driver Amplifiers in InGaP-GaAs HBT Technology for Space SAR T/R Modules .... .. .. ........ ......... ......... ........ ......... ......... ........ ......... ......... .... C. Florian, R. P. Paganelli, and J. A. Lonac Multiharmonic Volterra Model Dedicated to the Design of Wideband and Highly Efficient GaN Power Amplifiers .... .. .. ........ ......... ......... ........ . W. Demenitroux, C. Mazière, E. Gatard, S. Dellier, M. Campovecchio, and R. Quéré Design of Adaptive Highly Efficient GaN Power Amplifier for Octave-Bandwidth Application and Dynamic Load Modulation ..... ......... ........ ......... ......... ........ ......... ......... ........ ......... ........ K. Chen and D. Peroulis Design of a Concurrent Dual-Band 1.8–2.4-GHz GaN-HEMT Doherty Power Amplifier ....... ........ ......... ......... .. .. ........ ......... ......... ........ ......... .. P. Saad, P. Colantonio, L. Piazzon, F. Giannini, K. Andersson, and C. Fager Design of a Wideband High-Voltage High-Efficiency BiCMOS Envelope Amplifier for Micro-Base-Station RF Power Amplifiers ...... ......... ........ ......... ......... ........ ......... ......... ........ ......... ......... ........ ......... ......... .. .. ........ ..... M. Kwak, D. F. Kimball, C. D. Presti, A. Scuderi, C. Santagati, J. J. Yan, P. M. Asbeck, and L. E. Larson

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(Contents Continued on Back Cover)

(Contents Continued from Front Cover) High-Efficiency Cellular Power Amplifiers Based on a Modified LDMOS Process on Bulk Silicon and Silicon-On-Insulator Substrates With Integrated Power Management Circuitry ....... ......... ........ ......... ......... .. .. ........ ......... ......... ........ ......... ......... ...... A. Tombak, D. C. Dening, M. S. Carroll, J. Costa, and E. Spears -Band and -Band Power Amplifiers in 45-nm CMOS SOI .. ..... J. Kim, H. Dabag, P. Asbeck, and J. F. Buckwalter A Fully Integrated Watt-Level Linear 900-MHz CMOS RF Power Amplifier for LTE-Applications ... ......... ......... .. .. ........ ......... ......... ........ ......... ......... ........ ......... ......... ........ ......... .... B. François and P. Reynaert Analytical Design Methodology of Outphasing Amplification Systems Using a New Simplified Chireix Combiner Model .. ......... ......... . ....... ......... ... M. El-Asmar, A. Birafane, M. Helaoui, A. B. Kouki, and F. M. Ghannouchi A Zero-Voltage-Switching Contour-Based Outphasing Power Amplifier ........ ... N. Singhal, H. Zhang, and S. Pamarti Modeling and Digital Predistortion of Class-D Outphasing RF Power Amplifiers ....... ......... ........ ......... ......... .. .. ........ ......... ......... ........ ......... ........ P. N. Landin, J. Fritzin, W. Van Moer, M. Isaksson, and A. Alvandpour Investigation of Wideband Load Transformation Networks for Class-E Switching-Mode Power Amplifiers .... ......... .. .. ........ ......... ......... ........ ......... ......... ........ .. M.-D. Wei, D. Kalim, D. Erguvan, S.-F. Chang, and R. Negra The Continuous Inverse Class-F Mode With Resistive Second-Harmonic Impedance ... ......... ........ ......... ......... .. .. ........ ......... ......... ........ .. V. Carrubba, M. Akmal, R. Quay, J. Lees, J. Benedikt, S. C. Cripps, and P. J. Tasker Behaviors of Class-F and Class-F Amplifiers .. ........ ......... ......... .... J. Moon, S. Jee, J. Kim, J. Kim, and B. Kim A Simplified Broadband Design Methodology for Linearized High-Efficiency Continuous Class-F Power Amplifiers . .. .. ........ ......... ......... ........ ......... ......... ........ ......... ......... ...... N. Tuffy, L. Guan, A. Zhu, and T. J. Brazil Instrumentation and Measurement Techniques New Trends for the Nonlinear Measurement and Modeling of High-Power RF Transistors and Amplifiers With Memory Effects (Invited Paper) . ........ ......... ... ....... ........ .... P. Roblin, D. E. Root, J. Verspecht, Y. Ko, and J. P. Teyssier

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RF Applications and Systems Complex-Chebyshev Functional Link Neural Network Behavioral Model for Broadband Wireless Power Amplifiers .. .. .. ........ ......... ......... ........ ......... ......... ........ ......... ......... ........ ..... M. Li, J. Liu, Y. Jiang, and W. Feng Subsampling Feedback Loop Applicable to Concurrent Dual-Band Linearization Architecture . ........ ......... ......... .. .. ........ ......... ......... ........ ......... ......... . S. A. Bassam, A. Kwan, W. Chen, M. Helaoui, and F. M. Ghannouchi Design of a Direct Conversion Transmitter to Resist Combined Effects of Power Amplifier Distortion and Local Oscillator Pulling . ......... ......... ........ ...... .... ......... ........ ......... . C.-H. Hsiao, C.-T. Chen, T.-S. Horng, and K.-C. Peng Codesign of PA, Supply, and Signal Processing for Linear Supply-Modulated RF Transmitters ........ ......... ......... .. .. ........ ......... ......... ........ ....... J. Hoversten, S. Schafer, M. Roberg, M. Norris, D. Maksimovic´, and Z. Popovic´

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Special Issue on Biomedical Applications of RF/Microwave Technologies ..... ......... ......... ........ ......... ......... .

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Digital Object Identifier 10.1109/TMTT.2012.2201281

IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 60, NO. 6, JUNE 2012

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Guest Editorial

A

NYONE who has attended the IEEE Microwave Theory and Techniques Society (IEEE MTT-S) International Microwave Symposium (IMS) has probably experienced the standing-room-only attendance in power-amplifier sessions. In the past two years, 45 papers in this TRANSACTIONS has dealt with the topic of power amplifiers, and there were, on average, about ten sessions, and three workshops at the IEEE MTT-S IMS each year devoted to power amplifiers over the past several years. Obviously, this is a topic of interest to the engineering and research microwave communities. Power amplifiers have always been an important front-end building block in both military and commercial wireless communication and radar systems. Transmitted power and how it is generated determines capacity, range, signal-to-noise ratio, and other system parameters such as dissipation and related generator and cooling requirements. The load-modulated Doherty amplifier are prevailing over the inefficient class-A amplifiers for the cellular base-station infrastructure, while still highly nonlinear, but efficient, class-C amplifiers are prevalent in radar front ends. The days of signals with constant envelopes are behind us, and power is becoming an increasingly important resource. In communications, the need for increased capacity implies increasingly spectrally efficient modulation schemes, which, in turn, carry the challenge of efficient and high-fidelity amplification of signals with high peak-to-average ratios (PARs). In radar, spectral confinement is increasingly becoming a problem due to constant-envelope pulse shapes, which result in spectrum spreading. Over the past few decades, the past challenges of developing semiconductors with high carrier mobilities and high breakdown voltages have been overcome. Power-amplifier designers now have at their disposal GaAs, GaN, Si, SiGe, and InP to choose from for their specific applications. With new devices available, many power-amplifier architectures were revisited or developed with a focus on high efficiency and linearity. In the 1990s, it was impossible to conceive of a class-E power amplifier at microwave frequencies or of an Si-based 1-kW power amplifier at low microwave frequencies. Greater than 60% efficient power amplifiers are now almost common place, whereas a decade ago this would have been a star result. While CMOS power amplifiers are being developed for lower power applications, such as handsets, GaN, LDMOS, and high-voltage GaAs devices are evolving for high power transmitter applications. What are the challenges that face the power-amplifier designer today? As signal modulation schemes of the carrier become increasingly spectrally efficient, which implies large envelope variations (PARs) and bandwidths, the requirements on the power amplifier become difficult. To meet these requirements, further improvements in semiconductor devices and their nonlinear modeling, efficient amplifier circuit topologies, linearization methods, and transmitter architectures are needed. High-efficiency amplifier topologies are reaching over 80% power-added efficiency (PAE), but maintaining this high efficiency over varying envelope values requires new architectures. Amplification of the signal with tolerable distortion requires linearization techniques, and a dominant approach has been digital predistortion (DPD). Finally, to design such sophisticated power amplifiers, various modeling and measurement techniques have been introduced. This Special Issue has papers that cover topics that range from detailed nonlinear device modeling to relatively complex transmitter architectures. Excellent overviews of GaN, LDMOS, and CMOS technologies written by some of the world’s industry and academic leaders are likely to become handbook-level material. An in-depth discussion of nonlinear modeling provides a clear picture of how various memory effects are taken into account in nonlinear time and frequency-domain device modeling. Several transmitter-level papers discuss co-design and integration of dynamic power supplies with efficient power amplifiers for applications such as emerging micro-base-stations with high PAR signals. Monolithic microwave integrated circuit (MMIC) power amplifiers for applications such as space-born synthetic aperture radar that use broadband pulsed signals are also discussed. The carrier frequencies range from UHF to -band with various field-effect transistor (FET) and bipolar device technologies, and the papers address high-efficiency amplifier behavior and design, techniques for increasing bandwidth for efficient power amplifiers, various analog and digital linearization methods, and transmitters with high levels of integration. More research-oriented topics in this Special Issue include some new design methodologies for outphasing and other highefficiency topologies, dynamic load modulation for octave bandwidth power amplifiers, and dual-band Doherty power amplifiers. Every special issue has a finite number of pages, and some emerging research topics that would have made this Special Issue more complete are missing. For example, it would be interesting to learn more about design of power amplifiers that have to deal with variable complex loads, or about challenges and limitations of concepts for directly digitally driven power amplifiers. Power amplifiers with harmonic injection at input and/or output, used in the past with tube technology, in theory can provide efficiency with simultaneous linearity, and possibly over a wide bandwidth. Integration of power amplifiers with low-noise amplifiers (LNAs) Digital Object Identifier 10.1109/TMTT.2012.2192666 0018-9480/$31.00 © 2012 IEEE

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is another interesting topic for the front-end system designer. A good overview of emerging higher frequency GaN MMIC design techniques would also be of interest to many readers. Possibly a future special issue on power amplifiers can address these topics. We hope that in this Special Issue you will find plenty of new things to learn and share with your colleagues. Enjoy the read! ZOYA POPOVIĆ, Guest Editor Department of Electrical, Computer, and Energy Engineering University of Colorado Boulder, CO 80309-0425 USA BUMMAN KIM, Guest Editor Department of Electrical Engineering Pohang University of Science and Technology Gyeungbuk, Pohang, 790-784 Korea

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LDMOS Technology for RF Power Amplifiers S. J. C. H. Theeuwen and J. H. Qureshi (Invited Paper)

Abstract—We show the status of laterally diffused metal–oxide–semiconductor (LDMOS) technology, which has been the device of choice for RF power applications for more than one decade. LDMOS fulfills the requirements for a wide range of class AB and pulsed applications, such as base station, broadcast, and microwave. We present state-of-the-art RF performance of the LDMOS transistor measured with a load–pull test setup, achieving class-AB drain efficiencies of 70% at 2 GHz for on-wafer and packaged devices. Furthermore, the results for several class-AB and Doherty amplifier implementations constructed with this technology are shown. As an illustration, a three-way Doherty application is demonstrated, which has a 7.5-dB back-off efficiency of 47% at 1.8 GHz with a peak power of 700 W and linearity numbers better than 65 dBc. Index Terms—Microwave amplifiers, MOSFET power amplifiers (PAs), power amplifiers, semiconductor device fabrication.

I. INTRODUCTION

A

BOUT 20 years ago, laterally diffused metal–oxide–semiconductor (LDMOS) transistors were first introduced into the RF power market as a replacement of bipolar transistors for base-station applications [1], [2]. The RF performance of LDMOS has spectacularly improved over the last decades [3], [4]. Today, LDMOS is the leading technology for a wide variety of RF power applications, to mention a few: base station, broadcast, FM, VHF, UHF, industrial, scientific, medical (ISM), and radar [5], while many new opportunities are being considered, e.g., as RF lighting [6] and microwave cooking. The LDMOS frequency range of operation has expanded in the last decades, now covering a range from 1 MHz up to 4 GHz, including Wimax [7] and -band radar frequencies [8]. The power range of LDMOS spans more than three decades ranging from a few watts for driver devices up to a few thousands of watts for pulsed applications. The main driver for LDMOS has been the high volume base-station application, which requires continuous improvement, especially in efficiency, of the LDMOS technology. In the early days, LDMOS was operated in class AB in feed-forward systems, while today, two- or three-way Doherty amplifiers in Manuscript received October 10, 2011; revised March 22, 2012; accepted March 25, 2012. Date of publication May 08, 2012; date of current version May 25, 2012. The authors are with NXP Semiconductors, 6534AE Nijmegen, The Netherlands (e-mail: [email protected]; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2012.2193141

combination with digital pre-distortion (DPD) systems are the state-of-art for efficient base stations. The DPD enables good pre-distortibility at minimum power back-off (PBO), while the Doherty amplifier concept brings high back-off efficiency at the cost of linearity and gain reduction. LDMOS technology is very suitable for DPD and Doherty amplifiers [9]: due to its high gain ( 20 dB at 2 GHz), good efficiency, pre-distortibility, excellent reliability, and low cost. The supply voltage of the mainstream LDMOS applications, in particular base station, is around 30 V, which gives a good tradeoff between power and efficiency. From low-frequency ( 500 MHz) and digital terrestrial television amplifiers applications, there has been a demand for high power levels. This has fueled the development of a 50-V supply voltage LDMOS [10], [11]. At the moment, the 30- and 50-V LDMOS technologies coexist on the market, each serving their own application segment. In this paper, we show today’s 30- and 50-V LDMOS technology giving device cross sections and showing RF results of on-wafer and packaged devices measured with load–pull setups. The evolution of the performance is discussed, including the key improvement parameters and the reliability [12], [13]. In the second half of this paper, we give an overview of the performance of power LDMOS devices and the performance in several Doherty amplifiers over the various frequency bands. A few of the illustrations are a 700-W 30-V LDMOS Doherty implementation at 1.8 GHz, giving 47% efficiency at 7.5-dB back-off while meeting the tough linearity specs of multicarrier global system for mobile communications (MC-GSM) signals. Moreover, in order to demonstrate the benefits of 50-V LDMOS technology, a 400-W 50-V LDMOS Doherty amplifier is presented that has a bandwidth of 160 MHz around 890-MHz carrier frequency. In addition to that, high-frequency applications of the LDMOS technology are demonstrated by a 40-W -band PA device for weather radar applications for 2.7–3.3 GHz. II. LDMOS DEVICE TECHNOLOGY A schematic cross section of LDMOS is shown in Fig. 1. A difference with standard CMOS is that an LDMOS transistor has a drain extension region to support the breakdown voltage. The 30- [1]–[4] and 50-V [10], [11] technology have a typical breakdown voltage of 70 and 120 V, respectively, which requires a drain extension length of 3 and 6 m. The epi thickness is about equal to the drain extension length. The LDMOS n source region is connected to the backside via a metal bridge, a p sinker, and a highly conducting p substrate. Electrons flow from the source to drain if the gate is positively biased inverting the laterally diffused p-well channel. The drain is shielded from

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Fig. 1. Schematic image of an LDMOS device.

the gate by a field plate realizing an extremely low feedback capacitance and good hot carrier reliability properties. Many fingers are placed in parallel to form a power die, resulting in a total finger length of 10–1000 mm. Modern LDMOS technology is processed in a CMOS-fab, exploiting 8-in wafer manufacturing and lithography tools with capabilities down to 0.14 m. Additions to the CMOS process are a source sinker to the substrate, backside metallization, and tungsten shields between the drain and gate. The back-end metallization consists of multiple metal layers with thick top metals. In Fig. 2, we show a five-metal AlCu LDMOS backend. The top metal layers metal 4 and metal 5 are 2- and 3- m thick, respectively. The drain metallization has a mushroom shape with a wide top for an optimum tradeoff between electromigration reliability and performance parameters, such as (on)-resistance and output capacitance. Two polysilicon gates, partly covered with a tungsten shield, are visible at the bottom part of the photograph. A close-up of the gate area is shown in Fig. 3. The gate is covered with a thick CoSi layer to reduce the gate resistance. The thermal oxide of the gate is thin at the source side and is tapered toward a thicker oxide at the drain side, resulting in a first field plate formed by the gate. This construction gives a high gain and good reliability of the transistor. In the inset, the evolution of the gate length shows a reduction from 800 nm in the beginning of the LDMOS development down to 250 nm in 2012. The gate length reduction has spectacularly increased the LDMOS gain [7], [8]. The tungsten shield plate is in close proximity to the gate and is connected to the source metal with a repetitive metal connection (not shown). This shield not only reduces the feedback capacitance between gate and drain, but also reduces the electric fields at the end of the gate. This improved reliability makes it possible to increase the doping levels of the drain extension leading to an increase in efficiency and power density. Multiple field plates are used in the 50-V technology. The gate area for

Fig. 2. SEM cross-section photograph of LDMOS. (middle) Mushroom-type drain with thick metal 4 and metal 5 is present. (bottom) Two polysilicon gates, which are partly covered by the tungsten shield. The metal 2 lines ground the complete source region.

Fig. 3. SEM cross-section photograph of the gate region. LDMOS has got a polysilicon gate with cobalt silicide on top. The gate oxide becomes thicker toward the drain side of the gate forming a first field plate. The source connected shield is visible at the right-hand side of the gate. The inset shows the evolution of the gate length.

50-V LDMOS with three tungsten shields is depicted in Fig. 4. The shields are laid out in a staircase design above the drain extension region. This staircase shield construction reduces the electric field peaks at the gate side of the drain extension, resulting in an almost ideal constant lateral field distribution [10]. In Section III, we give an overview of the RF performance of the intrinsic LDMOS technology (both 30 and 50 V). The RF measurements are done with load–pull setup for on-wafer and unmatched packaged devices. In the following paragraph,

THEEUWEN AND QURESHI: LDMOS TECHNOLOGY FOR RF PAs

Fig. 4. SEM cross-section photograph of the shield construction of the 50-V LDMOS. This shield consists of three tungsten metal layers forming a staircase construction.

Fig. 5. Maximum efficiency versus output power contour boundaries for 30-V LDMOS technology. Measurements are done for NXP latest 30-V generation with an on-wafer load–pull setup. A pulsed signal with 10% duty cycle and pulsewidth of 1 ms is used.

the evolution of performance is shown for both unmatched low power and matched power devices. Furthermore, the key parameters are given and the ruggedness reliability is discussed. In Section IV, we show the RF performance of power devices, and in Section V, the results of devices in various Doherty implementations are discussed. In Section VI, we show an -band radar device for weather radar applications. III. INTRINSIC LDMOS PERFORMANCE A. 30-V LDMOS RF Performance We show pulsed RF measurements from an on wafer load–pull setup for a state of the art 30-V LDMOS technology in Fig. 5 for a frequency range from 1 to 4 GHz. The device measured has a total gate finger length of 4.2 mm and is biased with a supply voltage of 28 V and a drain current of 5 mA per mm gate periphery to achieve class-AB performance. The efficiency versus power tradeoff can be made visible by plotting the boundary contours of all measurements obtained

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Fig. 6. Frequency roll-off of the drain efficiency for 30-V LDMOS. The dotted line represents a loss model [4], which description and equations are depicted in the bottom part of the figure.

Fig. 7. Frequency roll-off of the transducer gain of 30-V LDMOS [8]. The solid line is the 6-dB/octave behavior.

by load–pulling the device over all possible load impedance states. From Fig. 5, we see that the power density of 30-V LDMOS is 1.4 W/mm for the measured frequency range. We show in the next paragraph that this power density can be increased to 2 W/mm for the 50-V technology. The maximum drain efficiency of the same LDMOS is 72% and shows hardly any roll-off versus frequency up to 3 GHz, where a drain efficiency of 68% is measured. This efficiency is very close to the theoretical class-B maximum efficiency of 78.5%. In the frequency range from 3 to 4 GHz, the efficiency falls off to 62% at 4 GHz. The frequency roll-off is plotted in Fig. 6, where a loss model fit of the indicated model [4] is included. In this model, the efficiency is limited at low frequency by the series resistance of the LDMOS. The resistance of the drain extension is the dominant contribution to this series resistance. The efficiency roll-off at high frequencies is caused by losses due to the output capacitance. The gain versus frequency of LDMOS is plotted in Fig. 7. It follows a 6-dB/octave roll-off as represented by the solid line. The gain at 2 GHz is 21 dB, while the gain at 4 GHz is 15 dB.

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Fig. 8. Efficiency-power contour boundaries for 50-V LDMOS technology [10]. Measurements are done at 1 GHz in a load–pull setup with a pulsed signal with 10% duty cycle and pulsewidth of 1 ms.

B. 50-V LDMOS RF Performance The 50-V LDMOS was developed in 2007, to increase the power density and impedance levels, for broadcast and ISM applications [10], [11]. The efficiency power boundary contours for the 50-V LDMOS are plotted in Fig. 8 as measured by load–pulling at 1 GHz. The maximum power density is more than 2 W/mm for this 50-V LDMOS. This increase in power density from 1.4 W/mm for 30-V LDMOS to 2 W/mm is predominantly caused by the increase of supply voltage from 28 to 50 V, while the current capability of these technologies is similar. The maximum drain efficiency is also very similar, yielding a value of 67% at 1 GHz. However, the drain extension needed to accommodate the 120-V break down is roughly two times longer and introduces a larger voltage dependent part of the output capacitance giving rise to more losses at higher frequencies. Therefore, this 50-V LDMOS technology has thus far found its introduction in applications below 1.5 GHz, although a further evolution of reduction in losses can be expected opening the possibilities for 2-GHz (Doherty) applications. C. Evolution of RF Performance In power applications, LDMOS devices with multiple fingers in parallel are mounted in a ceramic or plastic package. The flange is eutectically soldered to the source backside of the device while the drain and gate are connected via bond wires to the leads. The input and output impedance of a high-power device can be below a few ohm. High- input and output matching inside the package is applied to up-transform this impedance level. In Fig. 9, we show the evolution of the power density at 2.14 GHz for a 150-W packaged LDMOS. Over the last decade, the power density has about doubled, achieving more than 1 W/mm for the latest LDMOS generation. This is mainly achieved by increasing the current capability of the LDMOS. The power density is significantly lower than the on-wafer power density of 1.4 W/mm. The evolution of the maximum drain efficiency over the last decade is plotted in Fig. 10. Both the results for an internally matched 150-W device

Fig. 9. Evolution of power density for 30-V LDMOS. The power at 3-dB are given for gain compression and 1-dB gain compression a 150-W power device at 2.14 GHz. The devices are biased in class AB with 5 mA/mm and a 28-V supply voltage. Lines guide the eye. The data up to 2006 was published in [4], while the other data is taken from [19].

Fig. 10. Evolution of the drain efficiency for 30-V LDMOS. The efficiency has increased to 67% at 2.14 GHz for a 150-W device and to 55% at 3.6 GHz for a 10-W device. Lines guide the eye. Data from [4], [8], and [19].

at 2.14 GHz (corresponding to Fig. 9) and a 10-W unmatched device at 3.6 GHz are shown. The peak efficiency in class AB of the latest generation LDMOS is almost 70% at 2.14 GHz, close to the on-wafer load–pull result shown in the Section III-A. At 3.6 GHz, the drain efficiency is 55%, a lower value than the on-wafer measurement, indicating that extra losses due to the packaged configuration are present. The evolution of peak efficiency has mainly been achieved by a reduction of the output capacitance losses, which is discussed in Section III-D. D. Evolution of Key Parameters Key parameters for LDMOS are not only dc parameters, such as on-resistance and the maximum current capability, but also the output, input, and feedback capacitances. These capacitances are especially important because they lead to a frequency-dependent behavior of the RF parameters; the output capacitance is important for the frequency-dependent losses

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Fig. 11. Output capacitance ( ) evolution for 30- and 50-V LDMOS for V and equal to the supply voltage, measured at 1 MHz. The output capacitance has been normalized by the 3-dB compression power. Lines guide the eye. Data taken from evaluation devices [7], [8], [10], [19].

Fig. 13. (top) Equivalent circuit of the LDMOS with parasitic NPN bipolar transistor. (bottom) TLP curves for the 30- and 50-V LDMOS [12].

Fig. 12. Feedback capacitance ( ) evolution for 30- and 50-V LDMOS at V and equal to the supply voltage, measured at 1 MHz. condition The capacitance has been normalized by the 3-dB compression power. Lines guide the eye. Data taken from internal evaluation devices [7], [8], [10], [19].

(see Fig. 6), but also for the bandwidth of the power amplifier (PA). The reduction of the output capacitance is plotted in Fig. 11 for both 30- and 50-V LDMOS. The output capacitance has been reduced by a factor of 2 in the last decade. This reduction was achieved by scaling down the physical size of the drain contact width and by increasing the power density of the technology. The 50-V LDMOS has a much lower output capacitance for the same power level due to the higher power density of the 50-V device. The input capacitance has been kept constant during the LDMOS evolution by scaling the gate–oxide thickness proportionally to the gate length. The feedback capacitance evolution of 30- and 50-V LDMOS is given in Fig. 12. A similar large reduction trend is found as for the output capacitance evolution. The feedback capacitance in LDMOS is small compared to the output capacitance: the value is typically 7% of the value. Along with the evolution in output and feedback capacitance the on-resistance has also been improved. The on-resistance of the latest 30-V LDMOS and 50-V LDMOS devices is typically 14 and 29 m mm, respectively. E. Ruggedness Reliability Ruggedness is the most important reliability parameter for RF power devices apart from the traditional quiescent current

degradation and electromigration robustness. Ruggedness in LDMOS can be correlated to the inherently present parasitic bipolar NPN transistor [12], [13]. Important transistor paand the rameters for triggering are the base resistance . The corresponding electrical drain-to-base capacitance scheme is given in Fig. 13 (top). The drain–source diode clamps the voltage across the LDMOS and the parasitic bipolar and sinks the excess current to the substrate. For large sink currents, however, the drain–source voltage exceeds the diode breakdown voltage and the parasitic bipolar transistor can be triggered. As a characterization tool for triggering of this bipolar, transmission line pulse (TLP) measurements of the current–voltage characteristics are used [12]. The current and voltage characteristics for the 30- and 50-V LDMOS are given in Fig. 13 (bottom). From this figure, we see that the 30-V LDMOS has a breakdown of 70 V and a snapback voltage of 90 V. The 50-V LDMOS has a breakdown voltage of 120 V and a snapback voltage of 150 V. This snapback behavior has been realized by tailoring the electric fields in the LDMOS. The introduction of the triple stair case shield (see Fig. 4) plays an essential part in improving the snapback behavior of the 50-V technology. The extra voltage margin between the breakdown and snapback voltage allows the device to handle large drain voltage swings, as can occur in mismatch conditions, making the device very rugged. IV. RF PERFORMANCE OF LDMOS POWER DEVICES In this section, we describe the performance of LDMOS power devices, i.e., internally matched devices with peak power levels above 300 W. A photograph of typical internal matching structure of LDMOS is shown in Fig. 14.

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Fig. 14. Photograph of an LDMOS power device with highmatching inside the package.

input and output Fig. 16. Efficiency, power, and gain contours in Smith chart representation along with the load trajectory (indicated by the arrow) of a three-way DPA.

the Smith chart representation. The input of the device is conjugately matched and class-AB conditions are enforced (by shorting the harmonics) while obtaining the data presented in Fig. 16. In an ideal PA device, the points (loads) for maximum power, efficiency, and gain are located along a straight line; however, in real PA devices, these points make a triangle (see Fig. 16). The main reason for the separation of these contours in LDMOS devices (under class-AB bias) is the feedback mechanism, e.g., due to the feedback capacitance and source inductance [14]. Fig. 15. Efficiency versus output power LDMOS device at 960 MHz.

for a 400-W peak power 30-V

V. LDMOS DOHERTY IMPLEMENTATIONS A. DPAs Operation

Based on the efficiency power contours, we will show the key parameters for Doherty power amplifiers (DPAs). The load–pull data of a 400-W LDMOS power device is shown in Fig. 15. The efficiency power data presented in Fig. 15 is obtained by sweeping the output load and input power of the PA device. The higher power levels usually correspond to low output loading conditions, whereas lower power levels are the result of higher output loading conditions [14]. Moreover, the data presented in Fig. 15 indicate that the PA device have maximum efficiency of 70% at an output power of 200 W, which is around 3 dB lower than the maximum power of the device. Moreover, at power levels less than 200 W, the device show continuous decrease in efficiency. The reason for such behavior lies in the loss mechanisms shown in Fig. 6. At higher power levels, the dominant loss mechanism is , whereas at lower power levels, the loss is dominated by mechanism. Apart from the efficiency and power level of the LDMOS power device, the location of the power, efficiency, and gain contour maximum is also very important for high-efficiency concepts like the DPA. In Fig. 16, we show the efficiency, power, and gain contours of the 400-W LDMOS device in

The DPA is a very old concept to increase the average efficiency of the microwave transmitter. It was initially proposed in 1936 [15] to improve the efficiency of AM broadcast transmitters. It works on the principle of active load modulation of a PA device (main device) by injecting current from a second PA device (peaking device) into a common load. In the recent years, there is significant advancement in Doherty design techniques, e.g., multipath DPAs [9], [14], [16], [18], which have led to an increase of average efficiency of WCDMA base stations. The details of the DPA operation are given in [9], [14], and [16]; therefore, in this paper, we focus more on the impact of the device parameters on the performance of the DPA. A DPA is normally used to amplify the modulated signals having high peak-to-average ratios (PARs), which means that most of time the DPA operates at the power levels that correspond to the average power of the output signal. At those power levels, the main PA device in the DPA configuration operates alone at high loading conditions (in order to increase the terminal voltages, and therefore, the efficiency). Hence, the efficiency of the main device at back-off power levels with increased loading conditions (e.g., for a two-way and

THEEUWEN AND QURESHI: LDMOS TECHNOLOGY FOR RF PAs

for a three-way DPA) is very important for the average efficiency of the DPA. From Fig. 15, we see that the LDMOS peak efficiency of close to 70% is situated around a power level of 200 W, which is at 3-dB back-off. This makes this device favorable for being used as the main device in the two-way DPA, as in the two-way DPA, the main device is subjected to 3-dB back-off once the power of the full PA is backed off by 6 dB. Similarly, if the device is used as a main device in three-way DPA configuration, the load–pull data of Fig. 15 shows 65% efficiency at 4.7-dB back-off power levels (134 W), which corresponds to the 9.6-dB back-off of the total PA. In addition to the efficiency, the gain of an RF PA is also very important for DPA. The gain of a DPA is less than the intrinsic gain of the PA transistor and depends on following three parameters: 1) gain of the intrinsic device; 2) configuration of the DPA (e.g., two- or three-way); 3) change of gain along the load trajectory of the DPA. The last parameter depends on the location of the contour maxima of power, gain, and efficiency of the device, which should lie along the load-line trajectory of the main device in the DPA configuration, as shown in Fig. 16. In view of above considerations, efforts have been made to reduce the losses of the LDMOS transistors in order to improve its efficiency, especially in three-way DPA [16], [18] configurations. In addition to that, considerable effort has also been put to reduce the feedback mechanisms in the device, as well as in the package to improve the gain performance of the device in the DPA configuration. The result is an optimized high-efficiency high-power PA device technology suitable for two- and three-way DPAs [9]. B. 30-V LDMOS DPAs Results In Fig. 17, we show a photograph of a three-way DPA board designed at 1.8 GHz. This amplifier is based on the three-way Doherty concept [18] and contains three 250-W LDMOS devices. The top device is biased in class-AB and acts as a main device and the bottom two devices are biased in class-C mode and act as peaking devices. The power at the input is split with a passive power splitter. The gate biasing of the devices ensures that only the main PA device is active at deep PBO levels ( 10 dB), while peaking 1 (middle device) and peaking 2 (bottom device) turn on at medium dB dB and high power levels, respectively. The output power of the devices is combined with a three-way power combiner. The instantaneous efficiency of this three-way LDMOS DPA is shown in Fig. 18. The DPA has a peak power of 700 W and an instantaneous efficiency of 50% at 7.5-dB PBO. This results in an average efficiency of 47% for modulated signals having high PARs, e.g., MC-GSM and third-generation (3G) WCDMA. The spectrum of an MC-GSM signal after DPD is shown in Fig. 19. These are obtained using Opticron DPD setup. The wide RF and video bandwidth of the DPA allows to correct the linearity better than 65 dBc for an average output power of 120 W, with a signal PAR of 6.2 dB and 20-MHz signal bandwidth.

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Fig. 17. Photograph of a 700-W peak power three-way DPA, designed for 1.8 GHz.

Fig. 18. Measured efficiency versus output power of the three-way DPA designed for 1.8 GHz [18].

Fig. 19. Output spectrum of three-way LDMOS DPA with 6C-GSM signal after applying pre-distortion.

An overview of the performance of various three-way DPAs is given in Table I. The efficiency of the DPAs decreases with operating frequency, but it is still possible to achieve average efficiencies close to 50% up to 2 GHz and 40% at 2.7 GHz. A

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TABLE I PERFORMANCE OF SEVERAL THREE-WAY DPAs DESIGNED FOR DIFFERENT FREQUENCIES. SEVEN DPAS ARE BASED ON 30-V LDMOS AND ONE DPA IS BASED ON 50-V LDMOS. PEAK POWER, GAIN, EFFICIENCY AT AVERAGE POWER, AND ACPR VALUES AFTER APPLYING PRE-DISTORTION ARE GIVEN

Fig. 21. The efficiency and gain performance of an -band PA at output power of 40 W made with 30-V LDMOS technology.

applications for these frequencies are -band radar and Wimax and LTE bands for base station. As an example, we show a 40-W -band radar device for weather radar applications for 2.7–3.3 GHz in Fig. 21. The high intrinsic gain and low output capacitance of the current LDMOS technology allows to design with a gain of 13 dB over the full band (2.7–3.3 GHz) with an efficiency more than 50%. VII. CONCLUSION

Fig. 20. Measured efficiency at 8-dB back-off of a broadband 50-V LDMOS two-way DPA.

DPA based on 50-V LDMOS is also given in Table I, showing comparative performance at 1 GHz. C. 50-V LDMOS Doherty Results The 50-V LDMOS technology allows higher RF voltage swings at the drain of the PA devices resulting in increased power density and higher values of required output loads. This high load impedance results in lower quality ( ) factor output matching network, thereby decreasing the losses and increasing the fractional bandwidth of the output match significantly [17]. Furthermore, 50-V LDMOS technology allows a compact output matching network, and therefore a more dense packing of the power, resulting in a smaller packaged device. In Fig. 20, we show the frequency response from a broadband 800–960-MHz 400-W LDMOS DPA. The gain is typically 20 dB and the efficiency at 8-dB back-off, as required for DVB and MC-GSM signals, is 37%–42% over the band, which is a 10% improvement compared to class-AB operation. VI. LDMOS AT S-BAND APPLICATIONS The evolution of LDMOS has not only resulted in the extension of LDMOS to higher power levels, but has also opened the possibilities for LDMOS in 3–4-GHz frequency range. Typical

We have given SEM device cross sections of state-of-the-art 30- and 50-V LDMOS technology showing the special gate construction and the staircase shield construction. The intrinsic device performance has been presented for a frequency range of 1–4 GHz and the key device parameters were discussed. Furthermore, the performance of power devices and of several three-way Doherty amplifiers has been shown. Average efficiencies close to 50% can be achieved with three-way Doherty LDMOS amplifiers at 2 GHz in combination with high gain and low adjacent channel power ratio (ACPR) after pre-distortion. LDMOS is also suitable for broadband high-efficiency Doherty amplifiers, as shown for a 50-V LDMOS DPA. Finally, an -band weather radar LDMOS amplifier was presented having 13 dB of gain and more than 50% efficiency. New ideas related to device technology and electromagnetics are being applied to the LDMOS technology to open up even more advanced concepts, like -way DPAs and switching mode amplifiers. ACKNOWLEDGMENT The authors wish to acknowledge all their colleagues at NXP RF Power-Base Station, especially P. Hammes, J. de Boet, W. Sneijers, J. Zhao, S. van Nederveen, E. Neo, P. van Westen, M. de Vossen, and P. Valk for providing data, and R. Jos, F. van Rijs, H. Peuscher, and J. Gajadharsing for reviewing this paper’s manuscript. REFERENCES [1] A. Wood, C. Dragon, and W. Burger, “High performance silicon LDMOS technology for 2 GHz RF power amplifier applications,” in Int. Electron Device Meeting Tech. Dig., 1996, pp. 87–90. [2] H. F. F. Jos, “Novel LDMOS structure for 2 GHz high power basestation application,” in Eur. Microw. Conf., 1998, pp. 739–744.

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[3] H. Brech, W. Brakensiek, D. Burdeaux, W. Burger, C. Dragon, G. Formicone, B. Pryor, and D. Rice, “Record efficiency and gain at 2.1 GHz of high power RF transistors for cellular and 3G base stations,” in Int. Electron Device Meeting Tech. Dig., 2003, pp. 359–362. [4] F. van Rijs and S. J. C. H. Theeuwen, “Efficiency improvement of LDMOS transistors for base stations: Towards the theoretical limit,” in Int. Electron Device Meeting Tech. Dig., 2006, pp. 205–208. [5] D. Vye, L. Pelletier, S. Theeuwen, D. Aichele, R. Crampton, R. Pengelly, and B. Battaglia, “The new power brokers: High voltage RF devices,” Microw. J., vol. 7, pp. 22–40, Jun. 2009. [6] K. Werner and S. Theeuwen, “RF driven plasma lighting—The next revolution in light sources are powered by solid state RF technology,” Microw. J., vol. 12, pp. 68–74, Dec. 2010. [7] F. van Rijs, “Status and trends of silicon LDMOS base station PA technologies to go beyond 2.5 GHz applications,” in Radio Wireless Symp., 2008, pp. 69–72. [8] S. J. C. H. Theeuwen and H. Mollee, “ -band radar LDMOS transistors,” in Proc. 4th Eur. Microw. Integr. Circuits Conf., 2009, pp. 53–56, EuMIC04-1. [9] J. Gajadharsing, “Recent advances in Doherty amplifiers for wireless infrastructure,” presented at the IEEE MTT-S Int. Microw. Symp. Workshop, 2009. [10] S. J. C. H. Theeuwen, W. J. A. M. Sneijers, J. G. E. Klappe, and J. A. M. de Boet, “High voltage RF LDMOS technology for broadcast applications,” in Proc. 3th Eur. Microw. Integr. Circuits Conf., 2008, pp. 24–27, EuMIC02-2. [11] P. Piel, W. Burger, D. Burdeaux, and W. Brakensiek, “50VRFLDMOS: An ideal RF power technology for ISM, broadcast, and radar applications,” Freescale Seminconduct., Tempe, AZ, 2011, White Paper. [12] S. J. C. H. Theeuwen, J. A. M. de Boet, V. J. Bloem, and W. J. A. M. Sneijers, “LDMOS ruggedness reliability,” Microw. J., vol. 5, pp. 96–104, Apr. 2009. [13] D. C. Burdeaux and W. R. Burger, “Intrinsic reliability of RF power LDMOS FETs,” in IRPS11, 2011, pp. 435–443. [14] S. C. Cripps, A RF Power Amplifier for Wireless Communications, 2nd ed. Boston, MA: Artech House, 2006, ch. 2. [15] W. H. Doherty, “A new high efficiency amplifier for modulated waves,” Proc. IRE, vol. 25, no. 9, pp. 1163–1182, Sep. 1936. [16] W. C. Neo, J. H. Qureshi, M. J. Pelk, J. R. Gajadharsing, and L. C. N. deVreede, “A mixed-signal approach towards linear and efficient -way Doherty,” IEEE Trans. Microw. Theory Tech., vol. 55, no. 5, pp. 866–879, May 2007. [17] D. M. Pozar, Microwave Engineering, 3rd ed. New York: Wiley, 2005. [18] J. Gajadharsing, “Recent advanced in Doherty amplifiers,” presented at the IEEE MTT-S Int. Microw. Symp. Workshop, 2011, WS134.

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[19] “RF Design Manual” NXP, Nijmegen, The Netherlands, May 2011. [Online]. Available: www.nxp.com [20] “FSL Q2 2010 product and technology updates,” Freescale Semiconduct., Austin, TX, 2011. [Online]. Available: www.freescale.com S. J. C. H. Theeuwen was born in Nuth, The Netherlands, in 1970. He received the M.Sc. degree in physics from the Eindhoven University of Technology, Eindhoven, The Netherlands, and the Ph.D. degree in physics from the Delft University of Technology, Delft, The Netherlands. In 2000, he joined the Marketing, Strategy and Innovation Group, Philips Semiconductors Nijmegen, The Netherlands, as a Device Physicist involved with the development of high-frequency transistors in Si and III–V materials. He is currently with NXP Semiconductors (spun-out of Philips in 2006), Nijmegen, The Netherlands, involved with the RF Innovation Group in the development of highly efficient LDMOS devices for base station, broadcast, and microwave applications. Among his device physics research subjects are the hot carrier injection degradation, ruggedness, power density, and loss mechanisms for RF power LDMOS devices. He has authored or coauthored over 30 scientific papers. He has coauthored over a dozen patent applications.

J. H. Qureshi was born in Multan , Pakistan, in 1976. He received the B.S. degree in electrical engineering from the University of Engineering and Technology Taxila, Taxila, Pakistan, in 2000, the Masters degreei n electrical engineering from the Technical University Delft (TuDelft), Delft, The Netherlands, in 2006, and is currently working toward the Ph.D. degree at TuDelft. From 2000 to 2004, he was with Avaz Networks Paksitan, where he was involved in analog and digital circuit design for communication systems. In 2006, he joined Electronic Research Laboratory, TuDelft, where he was involved with the design of high-efficiency power amplifier (e.g., outphasing and Doherty amplifiers) and microwave active and passive circuit design. In 2010, he joined the Innovation Group of RF Power and Base-station, NXP Semiconductors, Nijmegen, The Netherlands. His research interests include high-efficiency wideband RF power amplifier design, RF system design, microwave active and passive circuit design, and advanced transmitter architectures for future base-stations and RF power applications.

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A Review of GaN on SiC High Electron-Mobility Power Transistors and MMICs Raymond S. Pengelly, Fellow, IEEE, Simon M. Wood, Member, IEEE, James W. Milligan, Member, IEEE, Scott T. Sheppard, Member, IEEE, and William L. Pribble, Member, IEEE (Invited Paper)

Abstract—Gallium–nitride power transistor (GaN HEMT) and integrated circuit technologies have matured dramatically over the last few years, and many hundreds of thousands of devices have been manufactured and fielded in applications ranging from pulsed radars and counter-IED jammers to CATV modules and fourth-generation infrastructure base-stations. GaN HEMT devices, exhibiting high power densities coupled with high breakdown voltages, have opened up the possibilities for highly efficient power amplifiers (PAs) exploiting the principles of waveform engineered designs. This paper summarizes the unique advantages of GaN HEMTs compared to other power transistor technologies, with examples of where such features have been exploited. Since RF power densities of GaN HEMTs are many times higher than other technologies, much attention has also been given to thermal management—examples of both commercial “off-the-shelf” packaging as well as custom heat-sinks are described. The very desirable feature of having accurate large-signal models for both discrete transistors and monolithic microwave integrated circuit foundry are emphasized with a number of circuit design examples. GaN HEMT technology has been a major enabler for both very broadband high-PAs and very high-efficiency designs. This paper describes examples of broadband amplifiers, as well as several of the main areas of high-efficiency amplifier design—notably Class-D, Class-E, Class-F, and Class-J approaches, Doherty PAs, envelope-tracking techniques, and Chireix outphasing.

TABLE I MATERIAL PROPERTIES OF MICROWAVE SEMICONDUCTORS [1]

TABLE II IMPACT OF GaN ON PA CONCEPTS

Index Terms—Broadband, gallium nitride (GaN), high efficiency, monolithic microwave integrated circuit (MMIC), power amplifier (PAs), power transistor, silicon carbide.

I. INTRODUCTION

W

IDE-BANDGAP semiconductor technology for high-power microwave devices has matured rapidly over the last several years as evidenced by the fact that AlGaN/GaN HEMTs have been available as commercial-off-the-shelf (COTS) devices since 2005. The material properties of GaN compared to competing materials are presented in Table I. AlGaN/GaN HEMTs possess high breakdown voltage, which allows large drain voltages to be used, leading to high output impedance per watt of RF power, resulting in easier matching and lower loss matching circuits. The high

Manuscript received September 19, 2011; revised January 12, 2012; accepted January 23, 2012. Date of publication February 23, 2012; date of current version May 25, 2012. The authors are with Cree Inc., Durham, NC 27709 USA (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2012.2187535

sheet charge leads to large current densities and transistor area can be reduced resulting in high watts per millimeter of gate periphery. The high saturated drift velocity leads to high saturation current densities and watts per unit gate periphery. In turn, this leads to lower capacitances per watt of output power. Low output capacitance and drain-to-source resistance per watt also make GaN HEMTs suitable for switch-mode amplifiers. Research and development of GaN HEMTs gained considerable momentum in the late 1990s and early 2000s when it became possible to reproducibly grow high-quality 4H-SiC substrates [2], [3]. In particular, GaN HEMT technologies have had a significant impact on various power amplifier (PA) concepts, as outlined in Table II [4] where a comparison is made between silicon LDMOSFETs (the “incumbent” technology for many applications) and GaN on SiC HEMTs. High total RF powers from GaN HEMT transistors over a wide frequency range have been reported for single die up to several hundred watts [5], [6]. However, these high power densities, in terms of watts per millimeter, also present extreme power dissipation demands on both the transistor layouts, as

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well as the semiconductor substrates. Fortunately, the high thermal conductivity of SiC substrates ( 330 W/m K) allows these high power densities to be efficiently dissipated for realistic drain efficiencies, preventing the extreme channel temperatures that would result due to self-heating with other substrate technologies. For example, a commercially available 120-W discrete transistor (Cree CGH40120F) operating at 28 V will generate 120 W of continuous wave (CW) RF power, and at its saturated output power, has a drain efficiency of 65%. With a rated CW thermal resistance of 1.5 C/W, the dissipated power is 64 W with a channel temperature rise of 96 C allowing the device to comfortably operate at baseplate temperatures in excess of 100 C. The effective pulsed thermal resistances of such devices are also lower (dependent on pulsewidth and duty factor)—this aspect will be covered in Section IX. In summary, GaN offers a rugged and reliable technology capable of high-voltage and high-temperature operation. This opens up many industrial, defense, medical, and commercial applications that can be targeted by GaN. II. OVERVIEW OF TECHNOLOGY Early progress on GaN/AlGaN HEMT technology in the 1990s was concentrated on three main areas, including improving epitaxial layer material quality, selecting the best substrate materials, and developing unit processes (e.g., [7]). Many of the advances in hetero-epitaxy of GaN and AlGaN were based on early metal–organic chemical vapor deposition (MOCVD) work in the field of opto-electronics [8]. However, both molecular beam epitaxy (MBE) and MOCVD growth methods were perceived as viable for GaN-based electronics devices [9], [10]. Most of the advancements in epitaxial growth were first achieved on sapphire due to its availability, but commercial ventures for GaN HEMT devices have all adopted either Si as a “low-cost” substrate or semi-insulating 6H- or 4H-SiC for superior high-power performance and thermal management. State-of-the-art power levels have been demonstrated on SiC substrates with total output powers of 800 W at 2.9 GHz [6] and over 500 W at 3.5 GHz [11]. The performance benefits for these devices are remarkable due to their ability to make heterostructures in a material system that also supports high breakdown fields. This has provided the key components necessary for high breakdown voltage and high transconductance device results as the technology advanced in the mid 1990s [10]. Clear understanding of the phenomenon of 2DEG carrier densities greater than 1 10 /cm was achieved after strain- and polarization-induced charges were clearly explained [11]. Subsequent device structure and processing enhancements led to the first results of passivated GaN HEMTs with results showing the clear thermal advantage of using SiC as a substrate instead of sapphire for high total RF power [14] and [15]. The epilayers for Cree commercial HEMTs are grown by MOCVD in a high-volume reactor on 100-mm semi-insulating 4H silicon carbide (SI 4H-SiC) substrates that are cut on-axis. The epitaxial growth process is highly reproducible and in production for several years, in part due to the funding on the Defense Advanced Research Projects Agnecy (DARPA) Wide Bandgap Semiconductor (WBGS) Program that was initiated

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Fig. 1. Schematic cross section of the AlGaN/AlN/GaN HEMT RF structure showing integrated first field plate and source-connected second field plate.

in 2002 [16]. Typical structures comprise an AlN nucleation layer, 1.4 m of Fe-doped insulating GaN, approximately 0.6 nm of an AlN barrier layer, and a 25-nm cap layer of undoped Al Ga N. This nominal layer thickness and mole fraction yield sheet electron concentrations in the range of 8 to 10 10 /cm , but due to the AlN interlayer has the strong advantage of electron mobilities near 2000 cm /V s at room temperature [17]. The channel sheet resistance is about 335 per square. As shown in the schematic cross section of Fig. 1, the device is fabricated with ohmic contacts that are formed directly on the top AlGaN layer. Device isolation is achieved using nitrogen implants to achieve a planar structure [18]. Gate electrodes are formed by recessing through a first SiN dielectric to the AlGaN and then depositing Ni/Pt/Au metallization. Very strong peak electric fields occur at the drain-side edge of the metal semiconductor junction in this lateral device. The optimized device includes a lateral extension of the gate electrode on the drain side to provide an elegant integration of field shaping with the gate metallization. The gate footprint is offset to reduce source resistance and increase gate-to-drain breakdown voltage. The gate length of the device is nominally 0.4 m, and the gate-to-drain spacing is about 3 m. After a second passivation, a source connected second field plate is fabricated to provide further electric field shaping at the highest drain voltages and to reduce gate to drain feedback capacitance of the device [19], [20]. The 1-mA/mm (gate current) breakdown voltage of this structure exceeds 150 V. Unit cell devices exhibit CW on-wafer output power levels of 4–5 W/mm when measured on a load–pull bench at 28 V and 3.5 GHz. The gate connected second field plate together with integrated first field plate has become the most widespread device structure in the industry for RF applications below 20 GHz. Microwave monolithic circuit demonstrations were an early goal of those developing the technology. Besides Cree Inc., a number of other GaN MMIC foundries provide similar technologies such as Triquint, Raytheon, and Hughes Research Laboratories. After the basic transistor device is completed, standard passive components such as metal–insulator–metal (MIM) capacitors, thin-film resistors, and through-wafer slot vias are utilized in the Cree Inc. process to achieve high-performance versatile monolithic microwave integrated circuit (MMIC) products (Fig. 2). The MIM capacitors have been developed to support peak voltages greater than 100 V. SiC substrate vias has allowed the straightforward implementation of the amplifier circuits without the need of cumbersome

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Fig. 2. Schematic cross section of typical GaN HEMT MMIC process.

coplanar waveguide grounding schemes. Specifically, slot vias are implemented in the 100- m-thick SiC substrates to simplify layout and increase gain. Three types of resistors are available: nichrome thin film with 12- /square resistance and two “bulk” GaN resistors with 70- and 400- /square resistance. Bulk GaN resistor layers are covered by thick dielectric insulators, enabling metal crossovers. A 0.4- m gate-length 28-V process provides 4.5 W/mm of gate periphery for circuits between dc to 8 GHz, while a 0.25- m gate-length 40-V process provides 7 W/mm of gate periphery between dc and 18 GHz. III. GaN HEMT LARGE-SIGNAL MODELING Field-effect transistor (FET) models have a long history. In Shockley’s original FET work, a physical representation was derived to predict operation of the junction field-effect transistor (JFET). Models have evolved from this point to describe and design new field-effect devices and to facilitate their various uses. There have been many new device structures and circuits produced over the 60 years that have passed since Shockley’s work, as well as an equally impressive list of modeling approaches. This branching of FET lineage has been driven by both military and civilian radar and communication system needs. In addition, various types of device models have been developed depending on application. An area of intense focus for both device and model development has been that of high-efficiency PAs. System cost is driven by prime power and cooling requirements and improved efficiency is the key to reducing these costs. Improved power devices, along with proper measurements and models, have driven an increase in performance; hence, the focus of the presently described review. Recently, most effort in PA design has been focused on GaAs pseudomorphic HEMTs (pHEMTs), Si LDMOSFETs, and GaN HEMTs. Models have been developed and adapted to these devices and share many common features because they are all field-effect structures. The focus of this study is to provide an example of this adaptation to the development of GaN HEMT models for MMIC and RF integrated circuit (RFIC) design. There have been excellent overviews of the state of modeling over the years. One recent example is by Dunleavy et al. [21]. The intent of this section of this paper is to present one possible solution to the modeling/design problem as applied to the GaN HEMT while acknowledging that there are many other viable solutions. There are two general approaches to HEMT (or other active device) modeling. One is table based, the best known of which has been developed by Root. The table data can either be measured or simulated using 2-D physical simulators. An extension

of this work appears in [22]. A more recent version of this approach is the new -parameter model formulation, which is based on significant small- and large-signal measurements [23]. This approach can be very accurate, but requires intensive measurement resources. To improve accuracy, the entire simulation space must be mapped using both large- and small-signal measurements including load–pull and linearity. It is certainly desirable to have the largest possible measurement database from which to extract and verify any model, but these measurements can be time consuming and expensive. A properly formulated model based on physical equations allows a reduction in required measurements without a significant loss in accuracy. The second approach involves the description of the active device by closed-form physical equations, the parameters of which can be extracted from measured data. This is the approach chosen to support Cree Inc. device models and reported here. There has been much work over the past 60 years on this topic, ramping significantly with the advent of the GaAs MESFET in the late 1970s. The model described here uses various formulations, from published work, combined in such a way as to allow parameter extraction using a minimal set of measurements. An added aspect to the model development is verification using an extensive library of MMIC amplifier designs up to 20 GHz, as well as a large number of hybrid circuits using packaged devices. The model was originally developed specifically for MMIC design, thus allowing continuous improvements as MMICs were developed, measured, and simulations verified. The starting point for the HEMT model is the drain current formulation. The basis for the function is very similar to the formulation given by Statz et al. [24]. A common feature in the drain formulation of this model and other notable versions [25], [26] is the drain voltage saturation parameter

A variant of this function is included in the present model together with a gate voltage parameter similar to that in [25]. Another feature, using work from [26], has proven useful in modeling drain current variations near pinch-off as

A feature common to these drain current formulations, which caused an issue early in the work, was the lack of a gate voltage saturation mechanism. The original intent would be to limit channel current with forward gate conduction. This proved somewhat problematic in practice, particularly when high compression is used in high-efficiency PAs. The hyperbolic tangent function, ubiquitous in modeling, proved helpful in saturating . A well-known application is found in the Angelov (or Chalmers) model [27]. A deficiency in this approach became apparent in fitting GaN HEMT devices for both linearity and efficiency predictions. As shown in [24], the GaAs MESFET (and in the GaN HEMT as well) drain current obeys a square-law dependence on gate voltage near pinch-off. This can be approximated with a high-order polynomial argument within the tanh function, but this is difficult to fit and has shown convergence problems. Furthermore, compression both at pinch-off and open channel necessarily share characteristics

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Fig. 3. HEMT SDD model schematic.

in the Angelov formulation. Experience did not show good fits either in linearity or high levels of compression. A reasonable solution for this problem has been proposed by Fager et al. [28] and the gate voltage compression expression allows the function to be tailored separately from the square-law pinch-off allowing compression in a controlled and continuous manner. The characteristic also involves trapping and dispersive effects. Many device models are formulated to fit both transconductance and output conductance dispersion, as well as knee collapse, which is common in high-breakdown high-voltage devices. The Cree Inc. model uses the dc knee voltage as controlled by the parameter to fit the observed RF knee without explicit fitting of the dc knee. This has not proven to be an issue in drain current prediction, nor has transconductance dispersion been shown to be a particular problem with GaN HEMT devices. Observations have shown output conductance dispersion to be an issue for self-consistent fits from small to large-signal operation. The solution for this problem has been found in the work of Jeon et al. [29]. Adding a small-signal perturbation to the function separates the small-signal output conductance from the drain current slope providing a good fit over the range of input power. The HEMT model schematic is shown in Fig. 3. This shows the drain current implemented in Agilent’s Advanced Design System as a symbolically defined device (SDD). The overall structure is based on the standard 13-element small-signal FET model. Although there have been many corrections and additions to this model since development of the GaAs MESFET, the standard 13-element model is straightforward to fit and

lends itself well to simple voltage-dependent capacitance models. Inspection of the schematic shows that both and are functions of the terminal voltages and implemented as gate charge formulations. There is also a gate forward conduction diode based on the standard exponential characteristic. Proper modeling of forward conduction is essential to the prediction of over-compressed operation, particularly in the case of broadband amplifiers. Improvement of convergence dictates that the exponential function must be limited. In this case, some arbitrarily large hard limit can be chosen with detriment to convergence properties. The and voltage functions use the tanh function similar to Fager et al. [28]. Extensive modeling and load–pull fits show that does not need to dynamically vary with drain voltage, but should scale as drain voltage is changed for the wide-bandgap HEMT device. The model as shown in Fig. 3 also includes noise calculation, is dependent on a dynamic thermal model based on channel dissipated power [30], and can be scaled for various unit cell configurations, as well as for parallel operation. The four noise sources represent the drain current noise and thermal noise from the FET internal resistances. Input and output noise is found to be correlated for the GaN HEMT. The model is partially based on the work of Lazaro et al. [31], as well as an empirical study of noise data [32]. The implementation as correlated noise sources simplifies the transition to a Verilog-A [33] translation used to develop models for both Agilent’s ADS and AWR’s Microwave Office simulators. The thermal model is based on a single-pole configuration, which provides for scaling as a function of dc dissipated power. Additional detailed thermal modeling can be performed using finite-element simulators and an

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TABLE III THEORETICAL MAXIMUM EFFICIENCIES OF VARIOUS CLASS PAs

V. BROADBAND AMPLIFIER EXAMPLES

Fig. 4. Measured versus modeled load–pull contours (output power: left; PAE: right).

equivalent thermal resistance is defined for the electro-thermal model. Thermal resistance calculations can also be calculated analytically as demonstrated by Darwish et al. [34]. Thermal calculations are essential for GaN HEMT amplifier design due to the high dissipated power associated with high drain bias. The model parameters are extracted from measured -parameters over a range of bias values, as well as measured load–pull data. The thermal degradation has been characterized using pulsed on-wafer measurements and equates to 0.01 dBm per C in output power. As previously discussed, the model is self-consistent over power and fits measurements over a large dynamic range. All model development was based on a two-fingered 720- m device and has been scaled successfully to a total gate periphery of 48 mm. The model fits -parameters up to 20 GHz and a typical load–pull fit at 10 GHz is shown in Fig. 4. The power contours are in 0.5-dB steps from 33.5 to 34.5 dBm and power-added efficiency (PAE) contours are in 10% steps from 30% to 50%. Extracting model parameters over the full range of -parameters up to 20 GHz and at least two load–pull frequencies, typically 3.5 and 10 GHz, provide accurate results for both narrowband and broadband designs up to 20 GHz with narrowband power levels in excess of 100 W. Packaged model parameters have also been developed to support discrete transistors using the same intrinsic model used for MMIC PA design. IV. BRIEF DESCRIPTION OF AMPLIFIER CLASSES GaN HEMT technology has not only opened up a resurgence in the investigation of various PA classes such as D, E, and F, but has also led to investigations into new modes of operation such as Class J [35], [36]. In general, there has been a lot of attention given to “waveform engineering” in the last few years [37], [38]—this has undoubtedly been due to the fact that GaN HEMT devices allow voltage and current swings on the drains of the devices that can far exceed other RF power semiconductor technologies. Table III gives a basic summary of the theoretical maximum efficiencies that can be provided by various amplifier classes. In practice, the maximum efficiencies will be lower because of a number of reasons [39]: conductance losses, losses, passive component losses, and discharge losses.

Since GaN HEMTs have high-power densities and low input and output capacitances per watt of RF output power, compared to most other microwave semiconductors, they have become useful devices to achieve high powers over broad bandwidths. A variety of circuit approaches have been demonstrated over a range of power levels, frequencies and terminating impedances—these include distributed (traveling wave), lossy match, and gate-to-drain feedback. Three of the most popular applications have been in software-defined radios, broadband jammers, and instrumentation amplifiers. In the latter case, relatively large power levels are required for such applications as automotive electromagnetic compatibility (EMC) testing—multiple baluns for power combining are often used to achieve wide bandwidths at high power levels. Cree Inc. has been developing GaN products for the past six years. All of these devices are based on a 0.4- m gate-length process and range in complexity from discrete unmatched transistors for wideband applications to multichip hybrid assemblies and packaged MMICs. An example of a discrete GaN HEMT for a very broadband amplifier application is the CGH40006S. This device is an unmatched transistor suitable for use in broadband applications, either as an output stage in military communication handheld radios or as a driver in counter IED jamming amplifiers. The challenge at this power level was to design an amplifier that would cover from 2 through 6 GHz. The transistor is housed in a plastic surface mount quad-flat no-leads (QFN) package. This package approach presents two key challenges: thermal management and electrical design to 6 GHz. The thermal design challenge was solved by placing the QFN packaged part on top of an array of filled vias. The vias were filled with conductive epoxy. The thermal conductivity of such epoxy-filled vias, although not as high as copper-plated vias, is sufficient. Simulations of the thermal stack were made using finite-element analysis (FEA) software (Fig. 5). Initial thermal simulations were performed at 4 W/mm (of gate periphery) of power dissipation to ensure that the channel temperature remained under 225 C when operating at a case temperature of 85 C. Consideration was also given to the surface temperature of the die as the plastic of the QFN package is in direct contact with the transistor. From simulation it was determined that the surface of the die would be 30 C lower than the peak channel temperature. The target power dissipation was then used as a design goal in the electrical simulations. Using the thermal engine of the large-signal model, it was possible to optimize the circuit’s electrical performance for best thermal performance. The electrical design challenge of the amplifier was caused by the source inductance of the via array and its impact on the performance of the final circuit. It was determined, during the design process that the launch of the RF signal from the printed circuit board to the package was critical. The use of a ground–signal–ground

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Fig. 8. Simulated optimum source and load impedances for CGH40006S.

Fig. 5. Use of FEA tools to design a via array for best thermal management (top left: QFN package; top right: half of QFN package on via array; bottom left: temperature profile of QFN packaged transistor). Fig. 9. Measured versus simulated small-signal performance of the CGH40006S in a broadband reference design.

Fig. 6. Layout view of CGH40006S with associated via array and GSG feed structure.

Fig. 10. Large-signal performance of the CGH40006S in a broadband reference design. Fig. 7. Effects of source inductance and GSG feed on

.

(GSG) launch reduced the effect of source inductance on the maximum available gain of the device above 4 GHz. The breakpoint in is extended from 3.5 to 5 GHz, resulting in an increase in gain of 2 dB at 6 GHz (Figs. 6 and 7). The via array was modeled using a layout-driven simulation approach in Microwave Office. The circuit design approach was to synthesize matching circuits to match simulated source and load–pull impedances derived from the large-signal model. Fig. 8 indicates that matching to the input of this device was more complex than matching to the output. This is often the case with broadband circuit designs using GaN HEMTs.

Excellent correlation was shown between measured and simulated circuit performances (Fig. 9) demonstrating the accuracy of the large-signal model. Furthermore, with careful layout driven techniques, a more complex and time-consuming 3-D analysis of the via array was not necessary. Fig. 10 shows the measured large-signal performance of the complete amplifier (Fig. 11) over 2–6 GHz. Power gain is maintained at greater than 11 dB with 7-W minimum output power and drain efficiencies of greater than 50%. Lin et al. [40] have used both the distributed and feedback approaches to design a range of commercial amplifiers covering saturated power levels up to 40 dBm over frequency ranges covering from 30 to 4000 MHz. Fig. 12 shows a comparison be-

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Fig. 11. Photograph of CGH40006S in a 2–6-GHz broadband reference design.

Fig. 13. Continuous Class-F mode PA [41].

Fig. 12. Measured and simulated output power for broadband feedback amplifier [40].

tween measured and large-signal modeled results for one of the feedback amplifiers. Carrubba et al. [41] recently demonstrated a novel, highly efficient, and broadband RF PA operating in “continuous class-F” mode. The introduction and experimental verification of this new PA mode demonstrated that it is possible to maintain expected output performance, both in terms of efficiency and power, over a very wide bandwidth. Using recently established continuous Class-F theory, an output matching network was designed to terminate the first three harmonic impedances. This resulted in a PA delivering an average drain efficiency of 74% and average output power of 10.5 W for an octave bandwidth between 0.55–1.1 GHz. Fig. 13 shows the practical implementation of the PA, while Fig. 14 shows the comparison between measurements and simulations. VI. HIGH EFFICIENCY PA EXAMPLES Much recent work has been achieved in the area of high-efficiency PA design using GaN HEMTs for a variety of classes of operation. This paper provides a number of circuit examples, but is, by no means, an exhaustive source of recent multiple designs. Class D: Lin and Fathy [42] have demonstrated a Class-D amplifier using Cree CGH40010F transistors. A 50–550-MHz wideband GaN HEMT PA with over 20-W output power and

63% drain efficiency was successfully developed. The wideband PA utilized two GaN HEMTs and operated in a push–pull voltage mode—Class D. The design was based on a large-signal simulation to optimize the PA’s output power and efficiency. To assure wideband operation, a coaxial line impedance transformer was used as part of the input matching network; a wideband 1:1 ferrite loaded balun and low-pass filters were utilized on the amplifier’s output instead of the conventional serial harmonic termination. Peak voltage swing on the drains of the transistors is 55 V (well within the breakdown voltage of the process). The practical implementation of the amplifier is shown in Fig. 15 and measured results are shown in Fig. 16. Class E: Shi et al. [43] have developed a very compact highly efficient 65-W wideband GaN Class-E PA. Optimum Class-E loading conditions were achieved over a broad frequency range using a wideband design and implementation approach using bond-wire inductors and MOS/MIM capacitors. The amplifier output network schematic is shown in Fig. 17. A photograph of the implementation is presented in Fig. 18, showing the employment of Cree 14.4-mm GaN die. The PA operates from 1.7 to 2.3 GHz with a power gain of 12.3 0.9 dB, while providing an output power of 42–65 W with a PAE ranging from 63% to 72%. The total area of the amplifier including bias networks is only 20 mm 20 mm. Class-E Doherty: Combining the advantages of Class-E and Doherty PA (DPA) operations has resulted in some of the highest PAEs at backed-off power levels reported to date. For example, Choi et al. [44] have described work on a two-way Doherty amplifier employing Class-E single-ended circuits for both the carrier and peaking amplifiers. The individual amplifiers, utilizing Cree CGH40010F transistors, were optimally matched at fundamental, second, and third harmonics using transmission lines on Taconic substrates (with dielectric constant of 2.6) to provide PAEs from 58% to 76% with output powers from 39.6 to 41.2 dBm and gains from 8.3 to 14.3 dB across 2.7–3.1 GHz. The switching Doherty amplifier consists of a carrier amplifier, peaking amplifier, broadband Wilkinson divider, offset lines, and output combiner. Fig. 19 shows the

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Fig. 14. Measured and simulated performance of continuous Class-F PA [41].

fabricated PA where the input divider uses multiple sections to minimize the effect of Class-E load conditions. Linearity of the amplifier was not a major concern since the application was for multifunction radar. PAE and drain efficiency at 6-dB back-off were 63% and 73%, respectively (Fig. 20). Class-E Chireix Outphasing: A Chireix outphasing PA is a promising candidate to work around classical linearity-efficiency tradeoffs and is based on linear amplification using nonlinear components (LINC). In an out-phasing transmitter, a complex modulated input signal is split into two signals with constant amplitude and a relative phase difference, corresponding to the time-varying envelope of the original input signal. The two branch signals are amplified by switch-mode power amplifiers (SMPAs). After combining both branch signals at the outputs of these SMPAs, an amplified replica of the original input signal results. Unfortunately, due to the nonisolating properties of the combiner, a time-varying reactive load modulation exists at the output of both SMPAs. To mitigate this unwanted load modulation, Chireix compensation elements are placed at the input ports of the power combiner. This creates an efficiency peak at a specified power back-off level, resulting in an improved average PA efficiency. The Chireix outphasing combiner is usually based on quarter-wave transmission lines and can be found in many publications on outphasing PAs. The Chireix compensation elements are either lumped or can be incorporated in the combiner. There are, however, some drawbacks to the classical Chireix combiner. The efficiency not only depends on the outphasing angle, but also on frequency since both the Chireix compensation elements and the quarter-wave lines are frequency dependent. Class-B, Class-D, and Class-F implementations have traditionally been used in the branch PAs, but recently Class-E has been identified as an even better candidate, demonstrating higher efficiency over a wider dynamic range [45]. Transformers can convert a single-ended load into a floating load. However, a lumped-element transformer is difficult to implement for high powers at RF frequencies. Coupled lines can be used to combine the outputs as in a Marchand balun. Van der Heijden et al. [46] have fabricated an outphasing SMPA with a Class-E Chireix coupled-line combiner. Fig. 21 shows the schematic of the amplifier. The Class-E PA switches were realized with commercially available Cree GaN HEMT transistor die. Since the GaN stages need to be driven with pulse-wave

Fig. 15. Practical implementation of Class-D UHF PA [42].

signals (to obtain the highest efficiency), a high-voltage CMOS driver topology was used in a 65-nm process. Fig. 22 shows a close-up of the CMOS-GaN SMPA lineup. Fig. 23 shows drain efficiency, total lineup efficiency, and power gain as a function of output power. At 10-dB back-off, the drain efficiency is 65% and the total lineup efficiency is 44%. At 8-dB back-off, the drain efficiency is 70% and the total lineup efficiency is 53%. The drain efficiency at 10-dB back-off is comparable to what has been published for a three-way GaN DPA, but with wider bandwidth capability. Class-F: A wide range of both Class-F and inverse Class-F PAs have been described in the literature. Typical of these is the PA design produced by Schelmzer and Long [47]. In a Class-F amplifier, the output matching network must absorb the of the HEMT and the interconnect inductance while providing the correct fundamental and harmonic resistances at the intrinsic drain of the transistor. It is beneficial if the matching network can be tuned to different values of so the amplifier can be designed for different supply voltages, especially for GaN transistors, which can be matched to a range of impedances due to their high breakdown voltage. Fig. 24 illustrates a matching network that can accomplish this. Two separate bond-wires are used at the drain pad. This allows the bond-wire inductance to be incorporated into the quarter-wavelength drain bias transmission line giving the lowest even harmonic impedances at the drain. and can be tuned to absorb and and simultaneously present a real impedance at the fundamental, , and a very

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Fig. 18. Practical implementation of compact Class-E PA [43].

Fig. 16. Measured performance of Class-D PA [42].

Fig. 19. Practical implementation of Class-E DPA [44].

Fig. 17. Class-E output matching network for compact PA [43].

high real impedance at the third harmonic. Effectively, both matching networks terminate the second, third, and fourth harmonics and some of the higher order even harmonics as well. The output matching network topology is a particularly good fit for the GaN transistor used (Cree CGH60015D, 3.6-mm gatewidth transistor) having a of about 0.9 pF. The output matching network was capable of tuning from 25 to 120 while maintaining a high third harmonic impedance and realizable transmission-line impedance. The amplifier was constructed on a low-loss printed-circuitboard substrate with gold-plated traces mounted to a copper carrier. The GaN HEMT was directly mounted to the copper carrier and used wire-bond interconnects. Fig. 25 shows a photograph of the amplifier. The amplifier was tested at 2 GHz where only the fundamental frequency component was measured for the results. The amplifier had a peak PAE of 85.5% with an output power of 16.5 W with a drain bias voltage of 42.5 V. The peak

Fig. 20. Gain and efficiency of Class-E DPA [44].

gain was 15.8 dB, and it had a compressed gain at peak PAE of 13.0 dB. The peak drain efficiency was 91%. Class-J: Moon et al. [36] have presented the theory of operation of Class-J PAs with linear and nonlinear output capacitors . The efficiency of a Class-J amplifier is enhanced by the nonlinear capacitance because of harmonic generation from the nonlinear , especially the second-harmonic voltage component. This harmonic voltage allows the reduction of the phase difference between the fundamental voltage and current components from 45° to less than 45° while maintaining a

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Fig. 24. Output matching network for Class-F PA [47].

Fig. 21. Schematic of Class-E Chireix coupled line outphasing PA [46].

Fig. 22. Close-up photograph of CMOS driven Class-E GaN HEMTs [46]. Fig. 25. Practical implementation of bare die GaN HEMT Class-F PA [47].

Fig. 23. Power gain, drain, and total lineup efficiencies of Class-E Chireix outphasing PA [46].

half-sinusoidal shape. Therefore, a Class-J amplifier with the nonlinear can deliver larger output power and higher efficiency compared with a linear . The Class-J amplifier can be further optimized by employing a so-called saturated PA, a recently reported amplifier type presented by the same authors. The phase difference of that proposed PA is zero. Like the Class-J amplifier, the PA uses a nonlinear to shape the voltage waveform with a purely resistive fundamental load impedance at the current source, which enhances the output power and efficiency. A highly efficient amplifier based on

Fig. 26. Practical implementation of Class-J PA [36].

the saturated PA was designed using a Cree CGH40010F GaN HEMT at 2.14 GHz (Fig. 26). It provided a PAE of 77.3% at a saturated power of 40.6 dBm (11.5 W). DPAs: There has been a very large body of work completed on high-efficiency DPAs over the last few years. This paper will only describe a few examples, but there are various approaches

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TABLE IV VARIOUS TYPES OF DPA CONFIGURATIONS

Fig. 27. Two different types of three-stage DPAs [48].

covering “conventional” two-way, -way, and -stage, asymmetrical (both unequal power division and unequal transistor peripheries), as well as different classes of operation for carrier and peaking amplifiers. Kim et al. have provided an extensive overview of DPA design specifically employing GaN HEMTs [48]. Of particular interest is the description of various three-way approaches shown schematically in Fig. 27. There are two kinds of three-stage DPA architectures, as shown in Fig. 27(a) and (b). Fig. 27(a) is a widely known structure. The topology is a parallel combination of one DPA used as a carrier PA with an additional peaking PA. The first peaking PA modulates the load of the carrier PA initially and the second peaking PA modulates the load of the previous Doherty stage at a higher power. The topology in Fig. 27(b) is a parallel combination of one carrier PA and one DPA used as a peaking PA. Both the three-stage and the three-way architectures use three PA units, but the two peaking PAs are turned on sequentially in the three-stage DPA instead of simultaneously like a multistage amplifier. Thus, three peak efficiency points are formed: at the two turn-on points and at the peak power. In the three-way structure, the peaking PAs are turned on simultaneously, similar to -way power combining. To achieve proper load modulation, the three-way DPA requires two quarter-wavelength transmission lines, but the three-stage DPAs require three and four quarter-wavelength transmission lines, respectively. A comparison of the achievable efficiencies of various types of DPAs is shown in Table IV. To implement the three-stage DPA, a Class-AB mode PA was designed at 2.655 GHz using Cree’s CGH40045F GaN HEMT devices. A simple method to overcome the problem of incomplete load modulation due to unequal currents in the carrier and

Fig. 28. Practical implementation of three-stage DPA [48].

peaking amplifiers was to control the gate bias of the peaking PAs. Gate bias control of the DPA is also often employed for accurate intermodulation cancellation. Gate bias control of the peaking PA was also used for performance optimization, that is, to simultaneously achieve high efficiency at the backed-off input power, as well as at high peak powers. In this example, the quiescent bias current of the carrier PA was 55 mA, and the PA delivered 64.6% drain efficiency at an output power of 46.4 dBm. The implemented PA with 1:1:1 ratio is shown in Fig. 28. The measured efficiency is illustrated in Fig. 29(a). This amplifier was employed for amplification of an 802.16e Mobile WiMAX signal with 7.8-dB peak-to-average power ratio (PAPR). Fig. 29(b) shows the measured efficiency of the envelope-tracking three-stage DPA with and without gate bias adaptation. Grebennikov [49] described a novel high-efficiency four-stage DPA architecture convenient for practical implementation in base-station applications for modern communication standards. Each PA was based on a 25-W Cree GaN HEMT device with the transmission-line load network corresponding to an inverse Class-F mode approximation. In a CW operation

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Fig. 29. (a) Gain and efficiency of DPA versus output power. (b) Gain, output power, and efficiencies of DPA with and without gate bias adaptation [48].

mode with the same bias voltage for each transistor, an output power of 50 dBm with a drain efficiency of 77% was achieved at a supply voltage of 34 V. In a single-carrier W-CDMA operation mode with a PAPR of 6.5 dB, a high drain efficiency of 61% was achieved at an average output power of 43 dBm, with ACLR1 measured at a 31-dBc level. The Doherty configuration is shown in Fig. 30 and affords high efficiency to be maintained over a wide region of back-off conditions. In theory, three-way DPA implementations can offer even better efficiencies in power back-off operation, which is highly desirable when dealing with single or multiple (unclipped) W-CDMA channels or modern fourth-generation (4G) signals with high crest factors. Unfortunately, practical three-way DPA implementations rarely meet their expectations due their complicated implementation. To overcome these implementation issues and enable reproducible, as well as very efficient -way Doherty amplifiers, the use of mixed-signal techniques was recently proposed to establish digital input control of the individual amplifier cells [50]. This approach facilitates the independent optimization of the amplifier-cell drive conditions for maximum efficiency. Neo et al. [51] had previously employed Si LDMOS transistors in the PAs, but have extended this concept to demonstrate the capabilities with GaN HEMT transistors. The system setup for the three-way DPA is shown in Fig. 31. The system is calibrated to maximize the backed-off power efficiency by adjusting the relative input phases of the three signals, as well as optimizing performance as a function of the

Fig. 30. Four-way DPA implementation [49].

Fig. 31. Schematic diagram of three-way mixed-signal DPA [50].

relative sizes of the transistors used in the carrier and peaking amplifiers. Fig. 32 also shows the normalized measured PAE of a 45-W Class-B GaN amplifier, which utilized an identical device as applied in the peak 1 amplifier. It is interesting to see that at maximum output powers, both the DPA, as well as the Class-B amplifier using the same device technology reach a maximum PAE of almost 70%, confirming the close to ideal operation of the DPA design at full power. Note that the PAE of the Class-B GaN amplifier decreases proportionally to the square of the back-off power, whereas the GaN three-way DPA demonstrates very high efficiency throughout the entire back-off range of 12 dB. At the 12-dB back-off point, the GaN three-way DPA provides three times higher PAE than the Class-B amplifier

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Fig. 32. Measured PAE of three-way DPA versus output power under two different mixed-signal conditions when compared to a single-ended Class-B amplifier [50].

for CW signals, indicating the very high efficiency potential of the three-way DPA for complex modulated signals with a high PAPR. The CW performance of the three-way GaN DPA was characterized and optimized using software control, yielding a measured performance of: 68% PAE at 50 dBm (full power), 70.4% at 45 dBm (first back-off point), and 64% at 38 dBm (second back-off point), while the measured transducer power gain was greater than 10 dB at all times. To demonstrate that this exceptional high-efficiency performance could be effectively utilized for practical base-station operation, the GaN three-way DPA was driven by a W-CDMA signal with a crest factor of 11.5 dB. Using a dedicated memory-effect compensating predistortion algorithm, the resulting measured PAE for this signal was 53% at an average power of 38.5 dBm, while meeting all linearity specifications. This was the highest PAE performance ever reported for any PA operating with a W-CDMA signal without using crest factor reduction techniques (at the time of the publication in 2008). Envelope Tracking (ET) PAs: The high-voltage operation of GaN HEMTs is particularly attractive for ET techniques that are used to maintain high efficiencies over a wide range of operating drain voltages under saturated power conditions. Over the last few years there have been a variety of reported results on ET-based amplifiers using a variety of RF semiconductor technologies such as Si LDMOSFET, GaAs HVHBT, and GaN HEMT [52], [53], [54]. Yamaki et al. [5] have described an optimized GaN device consisting of a single-die HEMT with 43 mm of gate periphery together with internal matching circuits in a package. The package size is 13.2 mm 21.0 mm. In order to realize high efficiencies, the authors implemented an inverse Class-F PA with harmonic terminations with output-matching networks inside the package. A single GaN HEMT die has advantages in terms of simplicity and cost effectiveness. The authors processed two types of GaN HEMT (A and B). The gate periphery and length were 43 mm and 0.6 m for 200-W output power, respectively. The gate electrode consisted of Ni/Au, and SiN

Fig. 33. Drain efficiency versus output power for GaN HEMTs A and B [5].

passivation was deposited on the GaN cap layer using plasma CVD. The structure of GaN HEMT (A) was “conventional,” which had already been manufactured as the commercially available EGN21C210I2D. The electrode structure and AlGaN electron supply layer of GaN HEMT (B) was changed to improve breakdown voltage to greater than 300 V allowing safe drain voltage operation under ET up to 65 V. Fig. 33 shows the drain efficiency measured at various drain voltages as a function of output power at 2.14 GHz together with a probability density function (PDF) of the W-CDMA signal. The bold line on the efficiency curves represents the operating point of the ET system. As shown in Fig. 33(a), the drain efficiency of the GaN HEMT (A) device was more than 65% over a 30 V ( dBm) to 40 V (52.7 dBm) drain bias range with a maximum drain efficiency of 68%. When a W-CDMA signal with 7-dB PAPR is used in this case, the drain efficiency of the GaN HEMT (A) device decreased significantly below the average power. As shown in Fig. 33(b), the drain efficiency of the GaN HEMT (B) device was more than 65% over a 15-V ( dBm) to 45-V (51.5 dBm) drain bias range with maximum drain efficiency of 72.5%. This result indicated that the GaN HEMT (B) device provided 65% efficiency over a wide range of powers (9 dB) as a result of the high-voltage operation and the improved characteristics.

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TABLE V COMMONLY USED MATERIALS FOR THERMAL MANAGEMENT GaN HEMT TRANSISTORS AND MMICs

Fig. 34. CMPA5585025F shown in custom developed ten-lead 50with dedicated bias leads.

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package

VII. MONOLITHIC PA EXAMPLES SiC is an excellent semi-insulating material, which allows it to be used for low-loss transmission lines and lumped elements (see Table I for properties of SiC) in addition to active devices such as HEMTs. Thus, GaN on SiC monolithic integrated circuits have become a popular platform for a range of circuits including wideband PAs. The first example is of a commercially available GaN HEMT MMIC, the CMPA5585025F, from Cree Inc. This MMIC is a packaged two-stage amplifier for satellite communications applications. The MMIC covers both the commercial, 5.8–7.2 GHz, and military, 7.9–8.4 GHz, frequency allocations. The availability of this packaged GaN HEMT MMIC has increased significantly state-of-the-art performance in terms of efficiency, gain, and power. In comparison, an internally matched GaAs FET only covers one band of interest. Target RF output power at 85 C case temperature, assuming a copper–tungsten composite package flange, was 25 W (CW). The efficiency and power gain targets were 40% PAE and 15–20 dB, respectively, across the frequency bands. A new multilead package was also developed for the MMIC, which can be used for a complete range of MMICs. The availability of commercially available packages for high-power large-area MMICs is somewhat limited. Most high power packages have relatively poor thermal conductivities and only have a single input and output RF lead. To take full advantage of a high-performance MMIC, it is very desirable to have multiple dedicated bias leads on either side of the RF leads to optimally distribute bias voltages to the MMIC (Fig. 34). This is an important design consideration since dc-bias networks often affect the overall stability of the amplifier—especially when working with high-power high-gain MMICs enclosed within small form factors. Each lead is also provides RF impedance of 50 operating to 15 GHz or so. This package also has the advantage of superior thermal conductivity as the flange material is 1:3:1 CPC (see Table V) enabling the packaged MMIC to be used to full case temperature without any de-rating of its linear output power. The MMIC was characterized for its linear performance under offset quadrature phase shift keyed (OQPSK) modulation. The linearity specification requires spectral purity

Fig. 35. CMPA5585025F spectral mask under 1.6-Ms/s OQPSK at 15-W average output power.

measurements at a spectral offset of one symbol from the center frequency, i.e., for a 1.6-Ms/s signal rate, the spectral mask is measured at 1.6-MHz offset from the center of the carrier. At this frequency, the spectral emissions are required to be less than 25 dBc. The multiple bias leads of the package allow for large video bandwidths to be supported. This allows compliance with the inevitable increase in data that satellite communications systems will have to handle in the near future. Fig. 35 shows the spectral mask of the CMPA5585025F at both 7.9 and 8.4 GHz. At these frequencies, the PAE is 25%—over twice that of an internally matched discrete GaAs FET. GaN HEMTs have adequate linearity when biased in Class A/B, whereas GaAs FETs are biased in Class A and are operated typically at 10 dB below their 1-dB compression point. Consequently the PAEs for the latter devices are usually less than 10%. Also, due to their low power densities, GaAs FETs also have large gate peripheries to achieve the required output power, which lead to devices with very high output capacitance with power gains of only 6 dB or so. The GaN MMIC described here typically provides 20-dB gain at its rated linear output power across both - and -bands. A summary of performance is shown in Fig. 36. Distributed MMIC Amplifier Design Example: A dc–6-GHz distributed MMIC amplifier (Cree CMPA0060025F) was designed using the nonlinear model-based design process described earlier [55]. The distributed (traveling wave) amplifier

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Fig. 38. Drain efficiency versus frequency at MMIC.

dBm for NDPA

Fig. 36. CMPA5585025F output power, gain, and PAE at rated linear output power under 1.6-Ms/s OQPSK modulation.

Fig. 39. Output power at

Fig. 37. Cascode NDPA MMIC.

is particularly useful in low-pass multioctave applications. The power and efficiency limitations for a reactively match amplifier are governed by the Bode–Fano power-bandwidth limit and by passive circuit losses. For very high-power levels, these limits dictate a maximum drain voltage based on a load-line match over the required bandwidth. In principle, the reactive elements of the active devices can be absorbed into the gate and drain synthetic transmission lines of a distributed topology with the limitations being gate line cutoff frequency and loss along the drain line [56]. A further complication in the design of power distributed amplifiers is that of device load-line match over the required band. Using standard distributed design techniques, some active devices may actually sink power in parts of the band. To achieve high efficiency from the distributed amplifier, a nonuniform approach is used in the design of the output transmission line where the characteristic impedance changes cell by cell and the output reverse termination is eliminated [57]. Proper design of the gate and drain lines and resizing of the individual cells will establish a reasonable load-line impedance for each cell. Other issues affecting nonuniform distributed power amplifier (NDPA) performance include output line loss, drain–gate feedback, and drain voltage level required to provide power to a 50- load. Each of these design problems can be reduced by using a balanced cascode configuration for individual cells [58]. The cascode configuration exhibits significantly reduced feedback and output conductance compared to a single common-

dBm for NDPA MMIC.

source stage. With the common-source and common-gate stages balanced as shown in [58], the drain voltage can be increased as much as twofold without incurring breakdown issues. Although device breakdown would support operation of the cascode cell up to a drain voltage of 80 V, the design becomes thermally limited. For CW operation, experience shows that 4–5 W/mm is the limit of dissipated power to maintain channel temperatures 200 C. The dynamic self-heating feature of the nonlinear model is crucial for predicting this operation. For the five-stage design example shown in Fig. 37, this limit is a drain voltage of 50 V. This should give an output power into 50 of W The measured performance of this amplifier is shown in Figs. 38 and 39. The amplifier produces 25 W of RF power up to 6 GHz with approximately 30% PAE. This shows that the cascode cell NDPA can be designed with a high-efficiency load line over a decade bandwidth. VIII. VERY HIGH PAs The majority of existing radar systems utilize technologies such as klystrons, magnetrons, or traveling-wave tube amplifiers (TWTAs) for their PAs. As end users demand more capability and operability for radar systems, they have been in search of more reliable cost-effective highly efficient, yet small-sized radar PAs. There have been two major independent approaches to overcome these challenges and to meet the needs—the first approach is to provide a miniaturized traveling-wave tube (TWT) to help make radar system smaller; the other approach is based on solid-state PAs using GaAs MESFETs or Si bipolar transistors. More recently, GaN HEMTs have become a very promising technology for small-size

PENGELLY et al.: REVIEW OF GaN ON SiC HIGH ELECTRON-MOBILITY POWER TRANSISTORS AND MMICs

Fig. 40. Practical implementation of 1-kW -band GaN HEMT PA [59].

Fig. 41. Measured output power and total line-up efficiency of 1-kW PA [59].

-band

high-efficiency PAs in the kilowatt range. Kwack et al. [59], for example, have described the design and manufacture of multistage -band 1-kW pallets consisting of a pre-driver stage, driver stage, and four combined 300-W units. Fig. 40 shows detail of the complete 1-kW pallet. As shown in Fig. 41, the SSPA successfully achieved output powers above 1 kW from 2900 to 3300 MHz. The efficiency of the whole PA, including the bias circuits, was about 34%. The output power was measured at the midpoint of the pulsewidth (100 ms with a 10% duty factor), and the efficiency was calculated using the peak current value during the pulse. During the pulse, the output power overshoots at the beginning of the pulse, and then gradually comes down with time, which is defined as power droop (the main cause of power droop being the thermal degradation of performance in the particular semiconductor technology, which for GaN is considerably better than either GaAs or Si due to the superior thermal conductivity of SiC). IX. THERMAL MANAGEMENT AND PACKAGING A systematic and consistent approach to the thermal modeling and measurement of GaN on SiC HEMT power transistors has been described [60]. Since the power density of such multilayered wide bandgap structures and assemblies can be very

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high compared with other transistor technologies, the application of such an approach to the prediction of operating channel temperatures (and hence, product lifetime) is important. Both CW and transient (i.e., pulsed and digitally modulated) thermal resistances were calculated for a range of transistor structures and sizes as a function of power density, pulse length, and duty factor and compared with measured channel temperatures and RF parameters. The resulting thermal resistance values have then been imported into new “self-heating” large-signal models so that transistor channel temperatures and the resulting effects on RF performance such as gain, output power, and efficiency can be determined during the amplifier design phase. GaN HEMT devices place considerable onus on the type of packaging used to house them because of the relatively high RF power density and resulting dissipated heat density from the die. Table V shows some of the commonly available materials used for commercial transistor packages that are suitable for many GaN HEMT devices. The most popular materials used today are copper–tungsten copper–molybdenum–copper, and copper–copper–molybdenum–copper. These materials not only have good thermal expansion coefficient matches to SiC, but also to the alumina ceramic materials most often employed for lead frames. All flange materials also need to have stable properties with regard to temperature, e.g., bowing and flatness, as well as suitable low surface roughness after plating allowing efficient, and void free die attach usually employing AuSn eutectic solder pre-forms. PAEs for relatively narrowband CW PAs employing GaN can be high (typically greater than 60%), but in certain cases (such as high-frequency ultra-broadband MMICs), efficiencies can be in the low 20% region. In these cases, more exotic materials are required for die mounting such as aluminum diamond or silver diamond composites [61], [62], which have thermal conductivities two to three times that of copper-based materials. Such increases in thermal conductivity have a marked effect on the operating channel temperature of the transistors—typically lowering the temperature by 25% or so (thus, if with Cu–Mo–Cu the was 200 C it will be reduced to 150 C (using silver diamond). For pulsed applications, the situation is quite different. With almost an infinite number of pulsewidth and duty cycle combinations, an effective way of communicating the thermal resistance versus time is essential. The best approach is plotting versus time in a semi-log scale for several duty cycles. In order to perform transient thermal analysis, density and specific heat material properties must be used in addition to thermal conductivity for time constant calculations of each material. The density and specific heat values used are listed in Table VI. Fig. 42 shows the transient thermal response of a 28.8-mm gatewidth GaN HEMT device in a 60-mil-thick CMC package dissipating 8 W/mm of power at 10%, 20%, 50% duty cycles. The transient response shows two distinct slopes of resistance versus time prior to full thermal saturation at approximately 400 ms. These two slopes can be attributed to the different transient thermal properties of the die and package. Fig. 43 shows how performing a transient thermal analysis with the same die, but mounted into a 40-mil-thick CuW package has the same thermal response during the first 100 ms, but is significantly

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TABLE VI MATERIAL PROPERTIES FOR TRANSIENT THERMAL ANALYSIS

Fig. 44. Output power and PAE of nominal 30-W PA versus 10:1 VSWR mismatch [63].

Fig. 42. Thermal resistance versus time for a 28.8-mm gatewidth GaN HEMT.

Fig. 45. Twelve 95-GHz GaN HEMT MMIC modules in a low-loss radial line combiner arrangement.

Fig. 43. Transient response of 28.8-mm gatewidth GaN HEMT in two different packages.

different after this point. The thermal resistance increase of the device with the CuW package can be explained by the slower thermal response of the material. X. ROBUSTNESS GaN HEMTs have been shown to survive output voltage standing-wave ratio (VSWR) mismatches well compared to Si LDMOSFETs and GaAs FETs. This can result in eliminating or simplifying protection circuitry and reducing field failure rates. The robustness is directly linked to the ability of the devices to handle large voltage and current swings for both transmitted and reflected RF power, as well as to deal with increased heat dissipation. Most GaN transistors are specified to withstand a 10:1 output mismatch VSWR at fully rated output power. For example, Quay et al. [63] have described a series of mismatch

stress testing on a nominal 30-W device operating at 50 V under 10:1 VSWR. Fig. 44 shows the resultant degradation in output power and PAE as a function of output tuner position. The PAE, under certain tuner positions, can be as low as 7% with a corresponding drop in RF power to 4 W with a maximum channel temperature of 278 C—even so the device did not fail. XI. OTHER DEVELOPMENTS Although commercially available GaN HEMT transistors and MMICs today are concentrated at frequencies below 18 GHz, a considerable amount of work has been achieved at much higher frequencies, indicating the potential for short gate-length devices. For example, Micovic et al. [64] have reported promising results for MMIC PAs at 88 GHz. The authors used 4 37.5 m wide devices having a gate length of 0.15 m as the basic unit cell building blocks. The devices had extrinsic peak transconductances exceeding 360 mS/mm at V, of 0.8 A/mm, of 1.2 A/mm, exceeding 90 GHz, and exceeding 200 GHz. Three-stage MMIC PAs had small-signal gains of 19.6 dB at 84 GHz. The peak power of a MMIC-based module was 842 mW at a drain bias of 14 V and a frequency of 88 GHz. Associated PAE of the

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module at peak output power was 14.8% with associated gain of 9.3 dB. The output power of the module exceeded 560 mW over 84–95 GHz. Schellenberg et al. [65] have produced a solid-state PA with an output power of 5.2 W at 95 GHz and greater than 3 W over the 94–98.5-GHz band employing such MMICs. The results were achieved by combining 12 of the MMICs in a low-loss radial line combiner network, as shown in Fig. 45. XII. CONCLUSION This paper has attempted to give a broad review of GaN HEMTs in terms of their wide-bandgap advantages over other semiconductor technologies. An overview of a typical AlGaN/GaN on SiC manufacturing technology was followed with a review of small- and large-signal models allowing the accurate design of both hybrid and monolithic circuits. An extensive description of various examples of broadband and high-efficiency PAs was given and followed by comments on thermal management and robustness. GaN HEMT technologies and applications have been and continue to be some of the most challenging and exciting in the RF and microwave industry [66]. ACKNOWLEDGMENT The authors would like to thank numerous colleagues and coworkers for their successful work on wide-bandgap transistors, hybrid, and MMIC PAs. Acknowledgements are made particularly to those referenced authors that have provided examples of PAs covering a wide range of frequencies and power levels. REFERENCES [1] RF and Microwave Semiconductor Handbook, M. Golio, Ed.. Boca Raton, FL: CRC, 2003, ch. 3, p. 3. [2] D. Hobgood, M. Brady, W. Brixius, G. Fechko, R. Glass, D. Henshall, J. Jenny, R. Leonard, D. Malta, S. G. Muller, V. Tsvetkov, and C. Carter, “Status of large diameter SiC crystal growth for electronic and optical applications,” Silicon Carbide Rel. Mater., 1999 (Part 1), Mater. Sci. Forum, vol. 338–342, pp. 3–8, 2000. [3] S. T. Sheppard, W. L. Pribble, D. T. Emerson, Z. Ring, R. P. Smith, S. T. Allen, J. W. Milligan, and J. W. Palmour, “Technology development for Gan/AlGaN HEMT hybrid and MMIC amplifiers on semi-insulating SiC substrates,” in Proc. IEEE/Cornell High Perform. Devices Conf., Ithaca, NY, Aug. 7–9, 2000, pp. 232–236, IEEE Cat. 00CH37122. [4] S. McGrath and T. Rodle, “Moving past the hype: Real opportunities for wide bandgap compound semiconductors in RF power markets,” CSMantech On-Line Dig. 2005. [Online]. Available: http://www.csmantech.org/Digests/2005/index2005.html, Paper 1.4 [5] F. Yamaki, K. Inoue, N. Ui, A. Kawana, and S. Sano, “A 65% drain efficiency GaN HEMT with 200 W peak power for 20 V to 65 V envelope tracking base station amplifier,” in IEEE MTT-S Int. Microw. Symp. Dig., Baltimore, MD, Jun. 2011, Flash Drive. [6] E. Mitani, M. Aojima, A. Maekawa, and S. Sano, “An 800-W AlGaN/GaN HEMT for S-band high-power application,” CSMantech On-Line Dig. 2007. [Online]. Available: http://www.csmantech.org/Digests/2007/2007%20Papers/11b.pdf [7] R. Gaka, J. W. Wang, A. Osinsky, Q. Chen, M. A. Khan, A. O. Orlov, G. L. Snider, and M. S. Shur, “Electron transport in AlGaN–GaN heterostructures grown on 6H-SiC substrates,” Appl. Phys. Lett., vol. 72, no. 6, pp. 707–709, Feb. 1998. [8] B. P. Keller et al., “Metalorganic chemical vapor deposition growth of high optical quality and high mobility GaN,” J. Electron. Mater., vol. 24, pp. 1707–1709, Nov. 1995. [9] S. Keller et al., “Metalorganic chemical vapor deposition of high mobility AlGaN/GaN heterostructures,” J. Appl. Phys., vol. 86, pp. 5850–5857, Nov. 1999.

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[10] I. P. Smorchkova et al., “Polarization-induced charge and electron mobility in AlGaN/GaN heterostructures grown by plasma-assisted molecular-beam epitaxy,” J. Appl. Phys., vol. 86, no. 8, pp. 4520–4526, Oct. 1999. [11] Y. F. Wu, S. M. Wood, R. P. Smith, S. Sheppard, S. T. Allen, P. Parikh, and J. Milligan, “An internally-matched GaN HEMT amplifier with 550-watt peak power at 3.5 GHz,” in Int. Electron Devices Meeting, Dec. 11–13, 2006, pp. 1–3. [12] Y. F. Wu et al., “Very high breakdown voltage and large transconductance realized on GaN heterojunction field-effect transistors,” Appl. Phys. Lett., vol. 69, pp. 1438–1440, Sep. 1996. [13] O. Ambacher, J. Smart, J. R. Shealy, N. G. Weimann, K. Chu, M. Murphy, W. J. Schaff, L. F. Eastman, R. Dimitrov, L. Wittmer, M. Stutzman, W. Rieger, and J. Hilsenbeck, “Two-dimensional electron gases induced by spontaneous and piezoelectric polarization charges in N- and Ga-face AlGaN/GaN heterostructures,” J. Appl. Phys., vol. 85, no. 6, pp. 3222–3333, 1999. [14] Y. F. Wu, D. Kapolnek, J. P. Ibbetson, P. Parikh, B. P. Keller, and U. K. Mishra, “Very-high power density AlGaN/GaN HEMTs,” IEEE Trans. Electron Devices, vol. 48, pp. 586–590, 2001. [15] B. M. Green, K. K. Chu, E. M. Chumbes, J. A. Smart, J. R. Shealy, and L. F. Eastman, “The effect of surface passivation on the microwave characteristics of undoped AlGaN/GaN HEMTs,” IEEE Electron Device Lett., vol. 21, no. 6, pp. 268–270, Jun. 2000. [16] M. Rosker, “Wide bandgap semiconductor devices and MMICs: A DARPA perspective,” in Int. Compound Semiconduct. Manuf. Technol. Conf., New Orleans, LA, Apr. 2005, p. 1.2. [17] L. Shen, S. Heikman, B. Moran, R. Coffie, N. Q. Zhang, D. Buttari, I. P. Smorchkova, S. Keller, S. P. DenBaars, and U. K. Mishra, “AlGaN/ AlN/GaN high-power microwave HEMT,” IEEE Electron Device Lett., vol. 22, no. 10, pp. 457–459, Oct. 2001. [18] S. C. Binari, H. B. Dietrich, G. Kelner, L. B. Rowland, K. Doverspike, and D. K. Wickenden, “H, He, and N implant isolation of n-type GaN,” J. Appl. Phys., vol. 78, no. 5, pp. 3008–3011, 1995. [19] Y. F. Wu, M. Moore, A. Saxler, T. Wisleder, and P. Parikh, “40-W/mm double field-plated GaN HEMTs,” in 64th Device Res. Conf., Jun. 2006, pp. 151–152. [20] Y. Okamoto, Y. Ando, K. Hataya, T. Nakayama, H. Miyamoto, T. Inoue, M. Senda, K. Hirata, M. Kosaki, N. Shibata, and M. Kuzuhara, “Improved power performance for a recessed-gate AlGaN–GaN heterojunction FET with a field-modulating plate,” IEEE Trans. Microw. Theory Tech., vol. 52, no. 11, pp. 2536–2540, Nov. 2004. [21] L. Dunleavy, C. Baylis, W. Curtice, and R. Connick, “Modeling GaN: Powerful but challenging,” IEEE Microw. Mag., pp. 83–96, Oct. 2010. [22] J. Wood and D. Root, “A symmetric and thermally-de-embedded nonlinear FET model for wireless and microwave applications,” in IEEE MTT-S Int. Microw. Symp. Dig., 2004, pp. 35–38. [23] J. Verspecht and D. E. Root, “Polyharmonic distortion modeling,” IEEE Microw. Mag., no. 3, pp. 44–45, Jun. 2006. [24] H. Statz, P. Newman, I. Smith, R. Pucel, and H. Haus, “GaAs FET devcie and circuit simulation in spice,” IEEE Trans. Electron Devices, vol. ED-34, no. 2, pp. 160–169, Feb. 1987. [25] A. Materka and T. Kacprzak, “Computer calculation of large-signal GaAs FET amplifier characteristics,” IEEE Trans. Microw. Theory Tech., vol. MTT-33, no. 2, pp. 129–135, Feb. 1985. [26] W. Curtice and M. Ettenberg, “A nonlinear GaAs FET model for use in the design of output circuits for power amplifiers,” IEEE Trans. Microw. Theory Tech., vol. MTT-33, no. 12, pp. 1383–1393, Dec. 1985. [27] I. Angelov, H. Zirath, and N. Rorsman, “A new empirical nonlinear model for HEMT and MESFET devices,” IEEE Trans. Microw. Theory Tech., vol. 40, no. 12, pp. 2258–2266, Dec. 1992. [28] C. Fager, J. C. Pedro, N. B. de Carvalho, and H. Zirath, “Prediction of IMD in LDMOS transistor amplifiers using a new large-signal model,” IEEE Trans. Microw. Theory Tech., vol. 50, no. 12, pp. 2834–2842, Dec. 2002. [29] K. Jeon, Y. Kwon, and S. Hong, “A frequency dispersion model of GaAs MESFET for large-signal applications,” IEEE Microw. Guided Wave Lett., vol. 7, no. 3, pp. 78–80, Mar. 1997. [30] E. Filseth and M. Jachowski, “SPICE extensions dynamically model thermal properties,” EDN, pp. 169–180, Apr. 1988. [31] A. Lazaro, L. Pradell, and J. O’Callaghan, “FET noise-parameter determination using a novel technique based on 50- noise-figure measurements,” IEEE Trans. Microw. Theory Tech., vol. 47, no. 3, pp. 315–324, Mar. 1999. [32] L. Dunleavy, 2009, Modelithics Inc., private communication.

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[33] D. Fitzpatrick and I. Miller, Analog Behavioral Modeling With the Verilog-A Language. Norwell, MA: Kluwer, 1998. [34] A. M. Darwish, A. Bayba, and H. A. Hung, “Thermal resistance calculation of AlGan/GaN devices,” IEEE Trans. Microw. Theory Tech., vol. 52, no. 11, pp. 2611–2620, Nov. 2004. [35] N. Tuffy, A. Zhu, and T. J. Brazil, “Class-J RF power amplifier with wideband harmonic suppression,” in IEEE MTT-S Int. Microw. Symp. Dig., Baltimore, MD, Jun. 2011, Flash Drive. [36] J. Moon, J. Kim, and B. Kim, “Investigation of a class-J power amplifier with a nonlinear cout for optimized operation,” IEEE Trans. Microw. Theory Tech., vol. 58, no. 11, pp. 2800–2811, Nov. 2010. [37] S. C. Cripps, RF Power Amplifiers for Wireless Communications, 2nd ed. Norwood, MA: Artech House, 2006. [38] P. J. Tasker, “Practical waveform engineering,” IEEE Microw. Mag., pp. 65–76, Dec. 2009. [39] S. El-Hamamsy, “Design of high efficiency RF class-D power amplifier,” IEEE Trans. Power Electron., vol. 9, no. 3, pp. 297–308, May 1994. [40] S. Lin, M. Eron, and S. Turner, “Development of broadband amplifier based on GaN HEMTs,” in IEEE Wamicon Conf. Dig., Clearwater, FL, Apr. 2011, CD. [41] V. Carrubba, J. Lees, J. Benedikt, P. J. Tasker, and S. C. Cripps, “A novel highly efficient broadband continuous class-F RFPA delivering 74% average efficiency for an octave bandwidth,” in IEEE MTT-S Int. Microw. Symp. Dig., Baltimore, MD, Jun. 2011, Flash Drive. [42] S. Lin and A. E. Fathy, “A 20 W GaN HEMT VHF/UHF class-D amplifier,” in IEEE Wamicon Conf. Dig., Clearwater, FL, Apr. 2011, CD. [43] K. Shi, D. A. Calvillo-Cortes, L. C. N. de Vreede, and F. van Rijs, “A compact 65 W 1.7 to 2.3 GHz class-E GaN power amplifier for basestations,” in Eur. Microw. Conf. Dig., Manchester, U.K., Oct. 2011, pp. 542–545. [44] G. W. Choi, H. J. Kim, W. J. Hwang, S. W. Shin, J. J. Choi, and S. J. Ha, “High efficiency class-E tuned Doherty amplifier using GaN HEMT,” in IEEE MTT-S Int. Microw. Symp. Dig., 2009, pp. 925–928. [45] T. K. Mouthaan and K. M. Faulkner, “Load pull analysis of Chireix outphasing class-E power amplifiers,” in Proc. Asia–Pacific Microw. Conf., Dec. 2009, pp. 2180–2183. [46] M. P. van der Heijden, M. Acar, J. S. Vromans, and D. A. CalvilloCortes, “A 19 W high-efficiency wideband CMOS-GaN class-E chireix RF outphasing power amplifier,” in IEEE MTT-S Int. Microw. Symp. Dig., Baltimore, MD, Jun. 2011, Flash Drive. [47] D. Schmelzer and S. I. Long, “A GaN HEMT class F amplifier at 2 GHz with 80% PAE,” in IEEE Compound Semiconduct. IC Symp., 2006, pp. 96–99. [48] B. Kim, I. Kim, and J. Moon, “Advanced Doherty architecture,” IEEE Microw. Mag., vol. 5, pp. 72–86, Aug. 2010. [49] A. Grebennikov, “A high-efficiency 100-W four-stage Doherty GaN HEMT power amplifier module for WCDMA systems,” in ARMMS Conf., Apr. 2011. [Online]. Available: www.armms.org [50] M. J. Pelk, W. C. E. Neo, J. R. Gajadharsing, R. S. Pengelly, and L. C. N. de Vreede, “A high-efficiency 100-W GaN three-way Doherty amplifier for base-station applications,” IEEE Trans. Microw. Theory Tech., vol. 56, no. 7, pp. 1582–1591, Jul. 2008. [51] W. C. E. Neo, J. Qureshi, M. J. Pelk, J. R. Gajadharsing, and L. C. N. de Vreede, “A mixed-signal approach towards linear and efficient -way Doherty amplifiers,” IEEE Trans. Microw. Theory Tech., vol. 55, no. 5, pp. 866–879, May 2007. [52] P. Draxler, S. Lanfranco, D. Kimball, C. Hsia, J. Jeong, J. Van de Sluis, and P. M. Asbeck, “High efficiency envelope tracking LDMOS power amplifier for W-CDMA’,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2006, pp. 1534–1537. [53] C. Steinbeiser, T. Landon, G. Burgin, O. Krutko, J. Haley, P. Page, D. Kimball, and P. M. Asbeck, “HVHBT Doherty and envelope tracking PAs for high efficiency WCDMA and WiMAX basestation applications,” in IEEE Power Amplifier Symp., Jan. 2009, pp. 57–61. [54] A. Cidronali, N. Giovannelli, T. Vlasits, R. Hernaman, and G. Manes, “A 240 W dual-band 870 and 2140 MHz envelope tracking GaN PA designed by a probability distribution conscious approach,” in IEEE MTT-S Int. Microw. Symp. Dig., Baltimore, MD, Jun. 2011, Flash Drive. [55] S. Wood, C. Platis, D. Farrell, B. Millon, B. Pribble, P. Smith, R. Pengelly, and J. Milligan, “Advances in high power GaN HEMT transistors,” Microw. Eng. Europe, pp. 2–7, May 2009.

[56] J. Beyer, S. N. Prasad, R. Becker, J. E. Nordman, and G. K. Hohenwarter, “MESFET distributed amplifier design guidelines,” IEEE Trans. Microw. Theory Tech., vol. MTT-32, no. 3, pp. 268–275, Mar. 1984. [57] G. Vendelin, A. Pavio, and U. Rohde, Microwave Circuit Design Using Linear and Nonlinear Techniques. Hoboken, NJ: Wiley, 2005. [58] A. Inoue, S. Goto, T. Kunii, T. Ishikawa, and Y. Matsuda, “A high efficiency, high voltage, balanced cascode FET,” in IEEE MTT-S Int. Microw. Symp. Dig., 2005, pp. 669–672. [59] J. Kwack, K. Kim, and S. Cho, “1 kW -band solid state radar amplifier,” in IEEE Wamicon Conf. Dig., Clearwater, FL, Apr. 2011, CD. [60] A. Prejs, S. Wood, R. Pengelly, and W. Pribble, “Thermal analysis and its application to high power GaN HEMT amplifiers,” in IEEE MTT-S Int. Microw. Symp. Dig., Boston, MA, Jun. 2009, pp. 917–920. [61] K. Loutfy, “Aluminum diamond meets cost and technical challenges for removing heat from GaN devices,” Microw. Product Dig., pp. 14, 54–60, Jun. 2011. [62] O. Vendier et al., “AGAPAC: Advanced GaN package for space,” Thales Alenia Space, France. [Online]. Available: http://ec.europa.eu/enterprise/newsroom/cf/_getdocument.cfm?doc_id=6484, O. Vendier, Proj. Coordinator [63] R. Quay, M. Musser, F. van Raay, T. Maier, and M. Mikulla, “Managing power density of high-power GaN devices,” in IEEE MTT-S Int. Microw. Symp. Workshop Dig., Boston, MA, 2009, pp. 71–86, Workshop Notes WMF “Is GaN ready for system insertion?”. [64] M. Micovic, A. Kurdoghlian, K. Shinohara, S. Burnham, I. Milosavljevic, M. Hu, A. Corrion, A. Fung, R. Lin, L. Samoska, P. Kangaslahti, B. Lambrigtsen, P. Goldsmith, W. S. Wong, A. Schmitz, P. Hashimoto, P. J. Willadsen, and D. H. Chow, “ -band GaN MMIC with 842 mW output power at 88 GHz,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2010, Flash Drive. [65] J. Schellenberg, E. Watkins, M. Micovic, B. Kim, and K. Han, “ -band, 5 W solid-state power amplifier/combiner,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2010, Flash Drive. [66] R. Quay, Gallium Nitride Electronics, ser. Mater. Sci. Berlin, Germany: Springer, 2008.

Raymond S. Pengelly (M’86–F’11) received the B.Sc. and M.Sc. degrees from Southampton University, Southampton, U.K., in 1969 and 1973, respectively. From 1969 to 1986, he was with the Plessey Company, both Romsey and Towcester, U.K., where he was involved in a variety of engineering roles with increasing seniority. From 1978 to 1986, he managed the world-renowned GaAs MMIC Department, Plessey Research, Caswell, U.K. In 1986, he was with the Tachonics Corporation, Princeton, NJ, where he was Executive Director of Design for analog and microwave GaAs MMICs. In 1989, he joined Compact Software, Paterson, NJ, as Vice President of Marketing and Sales, where he was responsible for the development of state-of-the-art computer-aided design tools to the RF, microwave, and lightwave industries. Beginning in 1993, he was with Raytheon Commercial Electronics, Andover, Massachusetts, in a number of positions including MMIC Design and Product Development Manager and Director of Advanced Products and New Techniques. Under these capacities, he managed a growing team to develop new products for emerging markets including PAs for wireless local loop applications using pHEMT technology, Si-Ge mixed signal products, flip-chip and chip scale packaging, as well as new subsystem techniques such as I/Q pre-distortion. Since August 1999, he has been with Cree Inc., Durham, NC, where he was initially the General Manager for Cree Microwave responsible for bringing Cree Inc.’s wide-bandgap transistor technology to the commercial marketplace. From September 2005 to the present, he has been responsible for strategic business development of wide-bandgap technologies for RF and microwave applications for Cree Inc., and most recently has been involved in the commercial release of GaN HEMT transistors and MMICs for general-purpose and telecommunications applications. He has authored or coauthored over 120 technical papers and four technical books. He holds 14 patents. Mr. Pengelly is a Fellow of the Institution of Engineering Technology (IET).

PENGELLY et al.: REVIEW OF GaN ON SiC HIGH ELECTRON-MOBILITY POWER TRANSISTORS AND MMICs

Simon M. Wood (M’99) received the Bachelor of Engineering degree from the University of Bradford, Bradford, U.K., in 1995. He began his career in electronics with Marconi Instruments Ltd., Stevenage, U.K., where he designed front-end modules for RF test equipment. In 1998, he joined Raytheon Microelectronics, Andover, MA, where he was involved in the design of MMIC PAs for cell-phone applications. In 2000, he joined Cree Inc., Durham, NC, where he has designed amplifiers using SiC MESFET, Si LDMOS, and more recently, GaN HEMT devices. Since November 2005, he has been Manager of Product Development with Cree Inc. In his professional activities, he has authored or coauthored numerous magazine papers and has presented papers and led workshops at international conferences. He holds six U.S. patents in amplifier design. Mr. Wood was the secretary of the Steering Committee for the 2006 IEEE Microwave Theory and Techniques Society (IEEE MTT-S) International Microwave Symposium (IMS), San Francisco, CA.

James W. Milligan (M’84) began his career in 1984 with General Electric, where he was involved with the design of solid-state phased-array antennas, transmit/receive (T/R) modules, and GaAs monolithic microwave integratex circuit (MMIC) PAs. In 1994, he joined Lockheed Martin, Moorestown, NJ, where he was responsible for the design and development of advanced phased-array antenna systems, T/R modules, and MMIC power-amplifier technology. In 1999, he joined Cree Inc., Durham, NC, where he has held positions of increasing responsibility including the management of Cree Inc.’s RF/Microwave Design Group. He is currently the Director of Cree Inc.’s RF and Microwave Business Segment and is responsible for GaN RF transistor products, MMIC Foundry services, and new product development activities for commercial and military applications.

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Scott T. Sheppard (S’85–M’90) received the BSEE degree from the University of Southwestern Louisiana, Lafayette, in 1989, and the Ph.D. degree from Purdue University, West Lafayette, IN, in 1995. He was involved in the development of wide-bandgap semiconductors for 19 years. While with Purdue University, his primary interests were the development of MOS technology for devices and circuits using silicon carbide. From 1995 to 1996, he was with the Daimler Benz Research Institute, Frankfurt, Germany, where he developed basic process technology for high-temperature JFETs in SiC. Over the 15 years with Cree Inc., Durham, NC, he has developed processes and device structures for high-temperature SiC CMOS, III-nitride blue laser diodes and microwave GaN HEMT discretes and MMICs. He has primarily been responsible for process development and process integration of MMIC technology for PAs, low-noise amplifiers, and limiters with the GaN-on-SiC platform and currently manages a Research and Development Group that brings new device concepts to market. Dr. Sheppard was the recipient of the National Science Foundation (NSF) International Postdoctoral Fellowship (1995–1996).

William L. Pribble (S’86–M’90) received the B.S. degree in electrical engineering from the Virginia Polytechnic Institute and State University, Blacksburg, in 1987, and the M.S.E.E. degree from North Carolina State University, Raleigh, in 1990. In 1990, he was with the GaAs Technology Center, ITT, where he was involved with power FET characterization and modeling and designed PAs of varying bandwidths from 1 to 18 GHz. In 1997, he joined Cree Inc., Durham, NC, where he has been involved in all phases of wide-bandgap device characterization, modeling, and amplifier design. He has authored or coauthored several papers. Mr. Pribble has contributed to a number of IEEE Microwave Theory and Techniques Society (IEEE MTT-S) workshops.

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Design of CMOS Power Amplifiers Ali M. Niknejad, Senior Member, IEEE, Debopriyo Chowdhury, Member, IEEE, and Jiashu Chen, Student Member, IEEE (Invited Paper)

Abstract—This paper describes the key technology and circuit design issues facing the design of an efficient linear RF CMOS power amplifier for modern communication standards incorporating high peak-to-average ratio signals. We show that most important limitations arise from the limited breakdown voltage of nanoscale CMOS devices and the large back-off requirements to achieve the required linearity, both of which result in poor average efficiency. Two fundamentally different approaches to tackle these problems are presented along with silicon prototype measurements. In the first approach, transformer power combining and bias-point optimization are used to increase the output power and linearity of the “analog” amplifier. In the second approach, a mixed-signal “digital” polar architecture is employed, wherein the amplitude modulation is formed through an RF DAC structure. Index Terms—CMOS power amplifier (PA), CMOS RF PA, digital PA, digital RF.

I. INTRODUCTION

T

HE past 20 years have witnessed the proliferation of wireless technology, fueled in part by advances in transistor scaling and digital signal processing, and in part by advances in transceiver architectures that are amenable to silicon integration. Today, wireless transceivers are ubiquitous, appearing not only in cellular phones, but in tablets, laptops, gaming consoles, and a plethora of consumer electronics. The growth is likely to continue into new consumer and medical devices, especially as the cost and the footprint continue to reduce. Much of this phenomenal success of the wireless industry can be attributed to the advancement in semiconductor technology, particularly CMOS technology. Hand-in-hand with digital circuits, most of the RF building blocks have now been designed successfully using advanced CMOS technology, enabling true SoCs. However, one hurdle to overcome is the power amplifier (PA), which is commonly implemented in a more mature technology, mostly nonsilicon, and requires a separate package and external front-end components (e.g., inductors, capacitors, and SAW filters). Research on CMOS PAs has been very active among the academic and industrial community, as highlighted in the literature survey shown in Fig. 1. The published results cluster around

Manuscript received October 17, 2011; revised March 19, 2012 and March 19, 2012; accepted March 25, 2012. Date of publication May 09, 2012; date of current version May 25, 2012. This work was supported by the National Science Foundation through NSF Infrastructure Grant 0403427. A. M. Niknejad and J. Chen are with the Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94708 USA (e-mail: [email protected]). D. Chowdhury is with Broadcom Corporation, San Diego, CA 92127 USA. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2012.2193898

Fig. 1. (a) Peak power and (b) peak efficiency versus frequency for published CMOS PAs from 2004 to 2011 covering technology nodes from CMOS 180 to 45 nm.

1–2 GHz, mainly for mobile phone applications, at 2.4 GHz for WLAN and at 60 GHz for short-range high-data-rate links. A clear trend is a drop in power with frequency, with peak powers above 3 W at 1 GHz and dropping significantly below 100 mW at 60 GHz. The range in power reflects different applications and the inherent tradeoff in linearity and efficiency, as reflected in Fig. 1. The spread in efficiency is accounted for by process options (e.g., metal stack-up or supply voltage), fully integrated designs versus designs incorporating external passive elements, and linear versus nonlinear switching PAs. Like the power trend, the efficiency drops with frequency, mainly a result of the limited available gain from the transistors at higher frequencies (operation closer to activity limits) and the need to use smaller device sizes to limit capacitance. One of the first significant contributions was a watt-level Class-E differential PA [1], implemented in 0.35- m CMOS technology. It leveraged high- bond-wires as inductors for the matching network, and a microstrip balun on the board for differential-to-single-ended conversion at the output. The PA could transmit 1-W power at 2 GHz with 41% power-added efficiency (PAE) using a 2-V supply. Since then, there have been quite a few publications on CMOS RF PAs [2]–[6]. They all rely on off-chip components such as bond-wires, off-chip inductors, off-chip capacitors to implement low-loss impedance transformation network, and thick-gate-oxide transistors to

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NIKNEJAD et al.: DESIGN OF CMOS POWER AMPLIFIERS

avoid over stressing devices. Since second-generation systems were the most popular at that time, the majority of published CMOS PAs were nonlinear power amplifiers. With the continued scaling of supply voltage, generating higher output power in CMOS technology became even more challenging. Various techniques were published in the literature, such as stacking transformers and power combiners. Stacked transformers have been a key ingredient in designing high-power PAs in silicon. The first stacked PA was used for a driver of a 3.7-W SiGe PA [7]. In a seminal work, the idea of stacking transformers was morphed into the distributed active transformer (DAT) [8], which was introduced to increase the output voltage of a CMOS PA using an on-chip transformer, also obviating the need for a matching network. High power and high efficiency were realized using an efficient Class-E/F architecture [9]. The increased demand for higher data rates as well as the scarcity of available spectrum soon pushed wireless standards to adopt more spectrally efficient modulation employing both amplitude and phase modulation [like quadrature amplitude modulation (QAM)]. Furthermore, to counteract multipath fading, newer standards such as 802.11a,g,n (WLAN), WiMAX, and LTE are employing an orthogonal frequency-division multiplexing (OFDM) scheme. The use of multiple subcarriers increases the peak-to-avergae ratio (PAR) of the signal, imposing stringent linearity requirements on the PA. Much research has focused on improving the efficiency and output power of linear PAs using transformer combining [11]–[13]. For instance, in collaboration with Intel, our team demonstrated a watt-level PA with 36% peak efficiency supporting an OFDM-modulated WiMAX/WLAN signal [14]. The design of this PA will be highlighted in this paper. Circuit-level techniques to combat nonlinearity of the PA will be discussed in relation to this PA design. Transformer combiners and the DAT structure have also been used up to the microwave and millimeter-wave band (60 and 90 GHz) [15]–[18] and will be briefly highlighted in this paper. The utilization of spectrally efficient complex modulation format necessitates the use of linear power amplifiers. However, it is well known that linearity and efficiency of the PA do not go hand-in-hand. Nonlinear or switching PAs such as Classes D and E are very efficient but cannot transmit amplitude modulation. Hence, most linear PAs use Class-A/AB amplifiers as a compromise between efficiency and linearity. Due to the inherent difficulty in the realization of a linear and efficient PA, much work has gone into transmitter architectures that can incorporate nonlinear PAs yet transmit amplitude information. For instance, a Cartesian feedback loop has been demonstrated to linearize a Class-C PA [19]. The concept of outphasing, or the decomposition of the carrier into two constant envelope signals, which is a classic technique plagued by load-pull modulation effects, has made a comeback in recent years [20]–[22]. The polar transmitter architecture, with origins in the envelope elimination and restoration techniques (EER) [23], has received more attention [24], [25], whereby the amplitude and phase modulations are processed separately and combined at the output of the PA, thus allowing an efficient switching PA to process the phase-modulated signal. In recent years, the speed of CMOS technology has increased manifold times, enabling the concept of an RF digital-to-analog converter (RF DAC).

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A digital polar architecture, first proposed by the author [26], has been demonstrated in low-power [27] and medium power regimes [28]–[30]. This architecture is very promising since it uses transistors as switches in a power DAC and has good efficiency and linearity, but introduces quantization noise and clock spectral lines at the output of the amplifier. This PA architecture will also be highlighted as a design example in this paper. II. CMOS TECHNOLOGY FOR RF PAS Most CMOS PAs incorporate some or all of the passive matching/biasing components by utilizing integrated inductors/transformers and capacitors. Often, the intrinsic metal layers meant for interconnect are used to build spiral inductors, capacitors, and transformers. In almost all modern processes, these metal layers are made with copper rather than aluminum, which is very good due to its lower loss and higher ac current-handling capability. In a relatively mature technology node like 90-nm CMOS, a typical process may have about seven or eight metal layers, and, optionally, two to three layers can be made thick (over 1 m). Silicon dioxide is the dielectric of choice, and polysilicon gate transistors are standard devices. By contrast, a hypothetical 22-nm process node may involve many technology enhancements such as metal gates (to fight gate depletion), SiGe source–drain junctions (to introduce strain to improve the mobility of transistors), and high-K gate dielectrics and low-K intermetal dielectrics to enhance gate control and to minimize the interconnect capacitance. Even though more metal layers may be available (up to ten), all but the last are extremely thin and, as a result, more resistive, and only the top metal layer is sufficiently thick to implement passive structures in a single layer. In fact, we find that scaling to 22 nm may offer faster transistors, but it does not inherently improve the power-handling capability of the process. Also, with scaling, the interlayer dielectrics are thinner, and, as a result, the uppermost layer is either closer to the substrate or, at best, at the same distance, so capacitive parasitics on inductors and transformers remain about the same or increase (worsen) with scaling. While bulk silicon is by far the dominant substrate (and lossy), there are good reasons to believe that an SOI substrate may become more commonplace in a deeply scaled device. However, unfortunately, the thickness of the oxide in an SOI process is often relatively thin, and a bulk CMOS substrate is often used as a carrier. Thus, the SOI option does not materially impact the effective dielectric thickness of the metal layers to the bulk substrate. Many technologies offer an extra metal layer that can be used to “cap” the top metal layer in order to increase its thickness. Unfortunately, this capping layer is often made of aluminum and as a result most of the ac current flows on the bottom layer, reducing the efficacy of the additional layer. Another possibility is the application of “redistribution” layers, often used in a flip-chip process, which are further away from the substrate and offer lower loss. In special circumstances, these options can be used to enhance the performance of passive devices, particularly inductors/transformers. While a given CMOS technology node has many flavors and options, such as thicker metal layers, low threshold transistors, and perhaps even higher breakdown voltage transistors, the

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choice of process is often a holistic decision based on digital, analog, and RF performance requirements, and the PA may play a small role in driving this decision. Therefore, it is not rare to find the worst lineup of process options available to a PA designer.

through the substrate, which can be modeled as a lossy dielec10 S/m, conductive and displacement curtric. For silicon, rent are equal at

A. Voltage Breakdown

which shows that, at most microwave frequencies of interest, both mechanisms play an important role. In addition to displacement current, eddy currents are also induced in the substrate due to the varying magnetic fields impinging on the conductive substrate [34], [35]. This loss mechanism is particularly important when the substrate conductivity is high. For this reason, great care must be exercised to avoid any high doping structures to appear near, especially under, inductors or transformer windings. Many CMOS process technologies automatically create p-wells on the surface to minimize the substrate resistance to prevent latch up. Such wells are created by inverting the n-well mask layer. If a well blocking layer is not employed, this places a thin conductive sheet below the inductor windings and can result in substantial eddy current losses. Substrate contacts on the surface of the silicon substrate provide a return path to ground, and some of the substrate currents flow to ground whereas other parts couple back to the structure. It is important to model the location of the substrate contacts in simulation to account for substrate losses. It is prudent to layout the substrate contacts intentionally rather than relying on the substrate contacts within transistors. This is especially true in transformers, since they are essentially four-port structures that support both even- and odd-mode excitation. The desired mode is the odd mode, in which the signals within the structure are differential in nature. However, due to mismatches and even harmonics, common-mode excitation can excite even modes which couple from winding to winding through capacitive coupling. The return path for these common-mode signals is through the substrate, and it is therefore necessary to create the return path in a well-defined manner to improve the match between simulation and measurements.

Short-channel CMOS devices have several important breakdown mechanisms. Due to the thin gate oxide, one of the most common breakdown mechanisms is through the gate. This is set by the dielectric breakdown in the gate. If the gate oxide is only 1 nm thick, then even 1 V applied to the gate oxide results in a gate/oxide field of 10 MV/cm. Good quality thin ( 10 nm) SiO films usually have breakdown fields of 15 MV/cm [31]. While thick oxides have an abrupt breakdown, thin oxides typically have a “soft” breakdown mechanism, with the current increasing gradually rather than abruptly. Oxide breakdown must be avoided because it results in the creation of electron/hole traps in the oxide and the creation of surface states at the oxidesilicon interface, both of which are detrimental to the operation of the MOSFET device. The second important mechanism is through impact ionization at the drain of the transistor. In the depletion region near the drain, the peak electric fields are sufficiently large to pull electrons from the valence band into the conduction band. These electrons gain energy from the high fields and, through the process of impact ionization, create additional electron/hole pairs. The process can runaway and avalanche, with hole current flowing to the substrate and the “hot” electrons injected into the oxide of the transistor. Unfortunately, the onset of impact ionization is more severe for nMOS devices. It is important to note that both of these breakdown mechanisms can have slow but accumulative effects on the performance of the device. When a device is operated near breakdown, the accumulated traps and charges in the oxide impact the threshold voltage and change the device characteristics over time. By observing the substrate current in the laboratory or through simulation, one can gauge and even calculate the lifetime of a transistor [32]. Some recent studies have focused on the RF breakdown mechanism and shed some light on the topic. For instance, the work in [33] has performed RF measurements and shown that the negative effects of impact ionization on threshold shifts in the transistor is constant with frequency up to the limit of 3 GHz. On the other hand, the gate-oxide stress effects do show a dramatic frequency dependence. Again, the work in [33] has shown an 18-fold increase in the gate-oxide lifetime at high frequency (1.8 GHz) when a unipolar sinusoidal signal is excited from 5.6 MHz to 1.8 GHz. B. Silicon Substrate Losses CMOS devices are by and large fabricated on a bulk silicon substrate, with a doping level corresponding to about a substrate resistance of about 10 -cm. The conductive nature of the substrate is another loss mechanism that puts a limit on the quality factor of passive components, particularly inductors, fabricated on the substrate. Since the distance of metal layers to the substrate is much smaller than the lateral dimensions of passive structures, a substantial amount of capacitive coupling occurs

GHz

(1)

C. Transistor Device Losses and Modeling CMOS power transistors are extremely large (several millimeters) and are typically laid out as a grid of smaller transistors in parallel. The key decision is the width per finger and the number of fingers per unit element. Large finger widths result in high gate resistance, which lowers the power gain of the device, whereas short fingers incur more capacitive parasitics. Designing a unit cell with a smaller count is helpful in reducing the substrate resistance per cell, which minimizes the risk of latch drops in the substrate. up and A significant amount of loss occurs in the metal trace intraconnect, connecting top metal to the source–drain and gate of the transistor. Due to the large current levels—a direct result of operating with a low supply—any series resistance results in losses. Extraction is critical for design of a power transistor, and care should be exercised to section the layout parasitics so that the distributed nature of the currents can be preserved. One of the major issues with PA design is the lack of compact models characterized for high power and high frequency operation. Most transistors are relatively well characterized at dc ( – and – ) and at high frequency using small-signal -parameters. The large-signal performance is therefore only

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extrapolated from dc and small-signal measurements. Fortunately, most nonlinear mechanism in CMOS transistors are only [36]. weakly frequency-dependent even up to the device When differences are found between measurement and simulation, they can often be attributed to measurement or design error. For example, the introduction of even a small amount of trace inductance in the source of the device has a large impact on the large signal performance. Likewise, if memory effects are seen in a CMOS amplifier, it is often the result of bias/RF interactions rather than the core device. D. Impedance Transformation Network Losses To realize high output power requires an impedance transformation network to lower the load from 50 to the required impedance. Assuming for simplicity that the PA can swing over , then the required transformation ratio the full rail voltage is given by to reach a given power

(2) For instance, to reach 1 W of output power with 1 V of supply requires a transformation ratio of 100, whereas using a 3-V supply reduces the ratio to 11. The significance of this cannot be overstated because the loss in the transformation network is directly related to this factor. For a simple matching network, one can show that the loss is approximately given by [37]

(3) is the component and is the network , which where is related to the matching ratio. Due to low quality factor of on-chip components, we can see the benefit of employing the smallest possible transformation ratio. In the limit, the best approach is to perform power combining to bring down the power requirement per transistor to the point where one can simply avoid impedance matching altogether. This will be discussed in detail in Section III. III. CIRCUIT TECHNIQUES FOR CMOS PAs A. Stressing CMOS With High Voltage Operating a CMOS PA with the higher supply voltage is the simplest and most effective way to increase the output power and improve the efficiency of the PA. As discussed above, the efficiency improves since for a given output power, the transformation ratio from the 50- load to the required load for the PA decreases. The voltage limit is given by breakdown and reliability (lifetime) limits, and increasing the voltage therefore requires innovation in the circuit topology and or device level innovations (such as the lightly doped drain). In this paper, we focus on circuit-level techniques. 1) PA Class of Operation: The voltage stress on the transistor is related to the class of operation. In nearly all PAs, an inductor is used to bias the drain voltage of the inductor (either

directly, through a matching network, or through a transformer winding/center tap). Since the inductor voltage must have a zero average across it, it swings both in the positive and negative directions, allowing the drain voltage to go above . Most linear amplifiers (Class A, A/B) only incur a voltage stress of about 2 the supply voltage. In typical switching amplifiers (Class E/F), we find that the voltage stress may be three to four times higher than the supply voltage. One exception is the Class-D amplifier, which uses two switches to limit the voltage excursion to the supply rails. Class-D amplfiers, which are popular at lower frequencies, are not as efficient at higher RF frequencies due to the switching losses due to the device output capacitance, which can at a given frequency. Amplibe estimated by computing fiers that offer zero voltage switching (ZVS), such as Class-E and Class-D , do not incur such a loss at the price of higher voltage stress on the transistor. 2) Cascode Devices: The most straightforward way to protect transistors is to stack them into a cascode configuration. This applies to both linear and switching amplifier classes. In a linear amplifier, the cascode transistor gate is biased to allow the largest possible swing on the negative excursion of the drain . During the voltage, which is limited to approximately highest voltage excursions, if the gate is biased at a constant voltage, the bottom transistor experiences a smaller voltage swing, which is easily designed to be below the breakdown limit. The cascode transistor is stressed on the gate–drain by a . voltage of approximately , then . For instance, if The drain voltage of the cascode device will see the full transistor stress, but the drain depletion electric field is still lower than a single transistor due to the presence of the input device, which lowers hot-electron impact ionization rates. More importantly, the peak field occurs when the transistor current is at a minimum, which also helps to reduce the rate of impact ionization. One can increase the supply voltage beyond the technology node limits by employing a thick oxide transistor in the cascode. The input transistor is still protected by the cascode device, and the gain of the amplifier is still largely a function of the input transistor (the cascode is a current buffer), which means that we get the benefits of both high gain from a thin oxide and the voltage tolerance of a thick oxide device. Note that the swing loss due to a cascode device can be more than compensated if a correspondingly larger supply voltage is used. If the gate is instead self-biased, as proposed by [38], then the stress induced on the cascode device can be reduced and as a result an even higher supply voltage can be used. 3) Differential Stages: Differential amplifiers, or, more commonly, pseudodifferential (balanced) amplifiers, offer many benefits in integrated circuits. In a PA application, they double the voltage swing to a balanced load, which quadruples the output power, without incurring any additional stress. For this reason, most efficient PAs are realized as differential stages. Unless a balanced load is used, a balun is required. Fortunately the balun functionality can often be embedded into the impedance transformer or power combiner, so its loss is already accounted for. Otherwise, an bridge balun can be used to convert the signal into single-ended mode. Differential amplifiers have also been successClass-E and Class-D fully employed. In particular, Class-E/F [9] amplifiers use the

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their secondary windings connected in series. It is important to realize that the secondary winding of each transformer carries . As such, all power amplifiers are the same current coupled to each other. In other words, the impedance seen by each PA is also determined by the output voltage and output impedance of all other amplifiers. It can be shown [39] that the , seen by each PA, is given by impedance (5) (6) Fig. 2. Principle of transformer-based power combining.

un/balanced property at odd/even harmonics to synthesize the desired load impedance. 4) Complementary Amplifiers: RF pMOS devices are not used as often as nMOS amplifiers due to their lower mobility. In general, one can obtain more gain for a given capacitance by doubling the nMOS size. But the pMOS device can also provide voltage protection by dropping the supply voltage over two devices, as in a Class-D amplifier. A variation of this theme utilizes two stacked Class-E amplifiers [10] driven in phase (both nMOS and pMOS on simultaneously). When both transistors are on, the full rail appears across the inductor. However, when the transistors are turned off, the top of the inductor kicks low while the bottom of the inductor kicks high, which doubles the swing on the inductor during the off period and, as a result, halves the stress on the transistors. Note that, while the inputs are driven in phase, the two outputs are output of phase. A transformer or bridge balun can be used to drive a single-ended load. B. Power Combining Generation of high output power in low-voltage CMOS technology is definitely a challenging problem. One of the approaches to increase the output power capability is power combining. While many methods of combining power can be envisioned, one of the most popular techniques that has gained significant momentum in recent years is transformer-based power combining. The principle of transformer-based power combining is shown in Fig. 2 [8], [11]. Here, the primary windings are driven by independent amplifiers (represented in the figure by their Thevenin equivalent), while their secondaries are connected in series. Thus, the individual amplifiers may be driven by a low power supply, but the voltages add up on the secondary side, generating higher output power. In practice, mostly 1:1 transformers are used as unit elements in the power combiner in Fig. 2) to ensure less capacitive coupling design ( and higher quality factor. Under such a condition (4) The power delivered to the load will be the sum of the output power delivered by each amplifier minus the power dissipated in the matching network. It is thus of foremost importance to be able to design an efficient power combining network. The power combiner, in addition to efficiently summing the ac voltages of the individual amplifiers, also performs an transformers with impedance transformation. Fig. 2 shows

, and its primary Here, the turn ratio of transformer is is driven by an amplifier represented by its Thevenin equivaand output impedance . It can lent voltage source clearly be seen that the transformed load impedance depends on both the output impedance and output voltage (both magnitude and phase) of each PA, which can be considered as a form of load-pull. When all power amplifiers have the same output impedance and generate the same output voltage, and all of the transformers use the same winding ratio , (5) simplifies to a resistive value of (7) The impedance seen by each amplifier is now determined by two factors only: the turns ratio of each transformer and the number of parallel stages . Under the same conditions, the total output power delivered to the load equals (8) and the impedance transformation ratio is defined as (9) From (8), it can be seen that the output power can be increased either by increasing or . The idea of a fully integrated transformer based power combining has been demonstrated in [8], with so-called “slab” inductors to realize highly efficient on-chip distributive active transformer (DAT). One of the primary advantages of the DAT is the use of high- 1:1 transformer. By stacking the secondary of the 1:1 transformer in series, it combines the power from several parallel driven small amplifiers with high efficiency. Circular geometry is adopted as a means to create low-loss virtual ac grounds to avoid using long metal leads. The double-differential architecture requires every transistor to be active to create low-loss ac grounds on-chip. Our research has focused on the design of transformer-based power combiners as well. However, the main differentiation from other existing approaches is that the proposed topology provides great flexibility during implementation and enables access and control of each unit. In this approach, all of the unit amplifiers are independent (load-pulling effects need to be taken into account) of each other, and, hence, at lower output power, one or more of them can be turned off to enhance efficiency at backed-off power levels. The ideal efficiency versus output power characteristics as one or more stages are turned off is

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Fig. 5. Dual-loop transformer power combiner.

Fig. 3. Efficiency enhancement due to load modulation at power back-off.

Fig. 4. Transformer-based “figure-eight” power-combining network.

shown in Fig. 3. Further details of the operation principle under power back-off can be found at [11], [39]. The layout of such power combiners is critical to ensure low insertion loss. Two efficient layouts, a “figure-eight” power combiner [12] and a “dual-loop” [40] power combiner will be discussed here. The “figure-eight” structure is shown in Fig. 4. Four independent 1:1 transformers are utilized to design this 4:1 power combiner. This lateral structure places both the primary and secondary windings on the same metal layer. However, an important feature of this layout is the fact that the secondary winding is implemented in alternating orientation, resembling an “8.” This layout forces the current in two adjacent primary windings to flow in the same direction, thereby minimizing the effects of internal flux cancellation. This results in better coupling and significant efficiency improvement. An additional benefit stems from the alternating direction of the secondary windings. The secondary loop is now immune to common-mode coupling from a distant source since the incoming magnetic flux induces voltages of opposite polarity across each section of the “figure-eight.” It is thus advantageous to employ an even number of stages. A third important feature of the proposed structure is the use of two parallel coils for each primary, as is seen in Fig. 4. Because of the presence of primary windings on either side of each secondary winding, the current crowding (proximity) effect is mitigated, similar to the parallel primary 2:1 transformer. Since the current is spread more uniformly in the secondary, the losses are reduced. For example, the insertion loss of the proposed power combiner is 1.35 dB (75% efficient) and varies by only 0.4% over the band of interest.

The “figure-eight” power combiner is attractive since it helps to reduce losses associated with negative mutual coupling between adjacent primary leads, thereby improving transformer efficiency. However, in the “figure-eight” architecture, all of the primary windings are not symmetric with respect to the secondary, thereby introducing some amplitude and phase mismatch. In some applications, this imbalance can cause efficiency loss. In such cases, a dual-loop power combiner can be utilized, as shown in Fig. 5 [40]. Although it is more symmetric, it does not have the benefit of alternating orientation of “figure-eight.” Hence, the two primary coils need to be placed a certain distance apart to prevent internal flux cancellation. The insertion loss can be made comparable to the “figure-eight” structure, at the expense of more area. The power combiners we have discussed so far (DAT, “figureeight” combiner, dual-loop combiner) all belong to a class of transformer-based power combiners that can be called a series power-combining transformer (SCT). The basic idea is that, in such power combiners, the secondaries of the transformers are connected in series, adding up the output voltages and increasing output power across the load. However, another configuration of power combiners using transformers is possible where the currents from individual primaries are reflected to the secondary side and added. Hence, instead of a voltage-summing combiner, such combiners can be termed as current-combiners or parallel power-combining transformers (PCTs) [41]. Fig. 6 show the conceptual diagrams of SCTs and PCTs. The ( is system of transformers can be defined as is the number of primary the number of primary windings, is the number of secondary turns). For the SCT, turns, and the secondary windings of the transformers are connected in series sharing the same current . It has been derived in [41] that the power efficiency of the SCT can be represented as (10)

is the output power and is the power of the unit cell. Here, A similar analysis for the parallel PCT yields (11)

It is seen from the above equations that, in an SCT, the insertion loss increases with increasing the number of stages. However, one of the advantages of the PCT is that the loss can theoretically be minimized by increasing the number of stages [41].

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Fig. 7. Schematic of the two-stage transformer-coupled 2.4-GHz PA.

Fig. 6. SCT versus PCT, from [41].

On the other hand, for the same turns ratio, the input impedance presented by the PCT is higher than the SCT. Since PAs typically require lower impedance to deliver high output power, PCTs need to employ higher turns ratio to get the impedance down. A higher turns ratio usually lowers the quality factor of the windings, leading to increased losses. Thus, the choice between the SCT and the PCT is very application- and technology-dependent, and there is no clear single winner. IV. DESIGN EXAMPLES We have discussed the linearity requirements of PAs used in modern wireless transceivers. At the same time, the challenges involved in generating watt-level output power efficiently in scaled CMOS processes have been enumerated. Power-combining techniques to increase the output power have been discussed as well. Here, we present specific PA design examples incorporating the design ideas presented thus far. The first example is a linear Class-AB PA using transformer-based power combining. A 60-GHz millimeter-wave PA is presented next, and, finally, the third example is a mixed-signal “digital” polar transmitter. A. CMOS WiMax 4G PA Here, we examine the design of a very high-output-power transformer-coupled RF PA with stringent linearity requirements. A power-combiner architecture, similar to the dual-loop power combiner described earlier [11], was utilized. The targeted application for such a PA is for newer standards like WiMAX or LTE. Such a PA requires high output power as well as high linearity, since the modulation format employs both amplitude and phase modulation (16/64 QAM). In addition, the use of OFDM increases the PAR of the signal, putting further burden on the PA. The PA in this work is a two-stage all-transformer-coupled design, as shown in Fig. 7 [14]. An

input transformer converts the single-ended signal into differential form, while performing the input matching as well. The two output stages are combined using a transformer-based power combiner. When delivering saturated output power in excess of (in Fig. 7) can swing 1 W, the drain voltages of very high. Hence, a cascode configuration is adopted, using thin-oxide (90-nm) transistor for the common-source device, and high-voltage thick-oxide transistor (0.35 m) for the common-gate device. In order to ensure reliability (breakdown prevention as well as hot carrier effect mitigation) when delivering saturated output power, a dynamic bias network is employed on the cascode gate [38]. However, compared with a traditional resistive feedback network, a capacitive feedback network is used. This allows the gate of the cascode transistors to be biased independent of the supply voltage. This will is critical, since a high dc voltage at the gates of translate into higher potential at the drain of the thin-oxide , possibly stressing them. In addition, the devices feedback capacitors can be conveniently absorbed into the tuning capacitors needed on the transformer primary. It has been already emphasized that PA linearity is one of the most important requirements for a wireless system that employs complex modulation like WLAN, WiMAX, and LTE. Amplitude and phase nonlinearity are the two most important issues in implementing a PA with stringent EVM and spectral mask requirements. Conventional wisdom in linear PA design is to use a Class-A amplifier in which the transistor is always on. Howin nanoscale CMOS ever, due to low output impedance with increasing output swing, processes and reduction in Class-A PAs have “soft” compressive characteristics. This leads to a large back-off (often exceeding 10 dB) from the maximum output voltage swing in order to meet its linearity requirements. This often yields very poor efficiency—less than 5% in some cases, where modulated signal with high PAR is used. In the presence of a maximum achievable output swing (limited by ), the most optimal AM–AM response for EVM and spectral . A PA with purity is a brick wall in gain versus input power this “hard clipped” behavior requires the minimum back-off from peak power to meet EVM requirements. Of course, such a brick-wall characteristic cannot be produced by a real amplifier. However, if we can keep the ripple on the gain (both droop and

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Fig. 8. Measured AM–AM response for different gate bias voltages at 2.4 GHz.

Fig. 10. Test FR4 board with the packaged chip and die micrograph of the PA.

Fig. 9. Measured variation in phase of of the PA as a function of input power at 2.4 GHz with PMOS-based compensation scheme.

overshoot) to about 0.5 dB up to the required output power, then the EVM requirements can be satisfied with almost the same back-off as an ideal clipper. Thus, if the gate bias voltage is chosen so as to balance the gain compression and expansion, then a nearly flat gain response can be synthesized (as confirmed in Fig. 8). Note that such Class-AB amplifiers are well known in the literature, but are typically thought of as being a compromise between efficiency and linearity. However, by choosing the optimal bias point, an appropriate AM–AM response can be engineered, which will ensure linearity (i.e., required back-off) better than a Class-A amplifier in terms of EVM. In contrast with this fully analog technique of AM–PM compensation, a mixed-signal way of reducing AM-PM distortion has also been proposed in [42]. The technique uses a varactor as part of a tuned circuit to introduce a phase shift that counteracts the AM–PM distortion of the PA. The varactor is controlled by the amplitude of the IQ baseband data in a feedforward fashion. The technique has been demonstrated in a Class-AB CMOS PA designed for WLAN applications and implemented in a 90-nm CMOS process. Although a Class-AB amplifier with an optimal bias voltage can be engineered to have near-optimal AM-AM response, the amplifier has more phase distortion (AM–PM distortion) than a Class A PA. One of the main contributors to AM–PM distortion is the nonlinear gate capacitance of the output transistor. To reduce this AM–PM distortion, a pMOS-based capacitive compensation technique has been proposed in [43] and used in this design. The variation in gate capacitance of a pMOS with increasing input bias is complementary to that of the nMOS device. Therefore, it is possible to compensate or partially cancel

Fig. 11. Measured large-signal performance of the PA.

the nonlinearity of the nMOS with the aid of the pMOS device. In addition to bias point optimization, harmonic termination techniques at the PA output can also be implemented to improve PA linearity, as proposed in [44]. In particular, secondharmonic traps (consisting of resonant and ) circuits have been placed on PA drain nodes as well as on the source node (utilizing bond wire) to improve performance. The PA was fabricated in a 90-nm CMOS technology, packaged using a 32-pin MLF package and mounted on a FR4 board (Fig. 10). Large-signal measurements were performed using a is 30.1 dBm, and CW tone at 2.3 GHz. The measured is 28 dBm. The can be varied from approximately 27 to 28.5 dBm by adjusting the gate bias of the output stage. The peak drain efficiency is 36%, and the peak PAE is 33% (Fig. 11). Finally, the PA was tested with complex modulation. As an example, the 802.16e mobile WiMAX with 1024-carrier OFDM (10-MHz bandwidth) has been chosen. When excited by the WiMAX signal, the PA delivers 22.7 dBm of average output power at 14.2% drain efficiency and 12.4% PAE, while being fully compliant with the spectral mask requirements. The increased flatness in the AM–AM and AM–PM response enables the PA to meet the mask with only 7.4-dB back-off from . The measured EVM for 16/64-QAM OFDM input is better

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Fig. 14. Improvement in EVM by utilizing DPD. Fig. 12. Block diagram of PA using PCT.

Fig. 13.

linearization using main and auxiliary stages.

than 25 dB at the average output power and meets WiMAX requirements. Recently, a power-combined PA has been published [45] that uses similar analog techniques but also utilizes digital predistortion (DPD) to counteract PA nonlinearity and improve efficiency. In fact, with the evolution of fully integrated SoCs, it makes sense to harness the speed and power of DSP to counteract the analog imperfections. The block diagram is shown in Fig. 12. It has three differential stages with the introduced power combiner at the output. It is a current-mode transformer-based combiner (PCT). To improve the linearity of the PA, an auxiliary stage is used. The main and auxiliary devices are biased with an offset level to linearize the effective transconductance over a wide range of input voltages (Fig. 13). By utilizing this point of the transanalog gm-linearization scheme, the . In order to improve the mitter is enhanced to be closer to linearity further, an open-loop digital predistortion technique is used. The improvement in EVM obtained by utilizing DPD is illustrated in Fig. 14. B. 60-GHz CMOS PA Transformer power combining can also be utilized to improve the output power of millimeter-wave PAs. Besides all of the issues discussed in the previous example, designing CMOS PAs operating at 60 GHz or above faces additional challenges due to reduced transistor power gain, increased transistor intraconnect parasitic loss, and inaccuracy in device models. Here, we briefly discuss the design of a medium-power-level-transformer power-combined 60-GHz PA. This PA is intended for

Fig. 15. Dual-differential-input 60-GHz DAT power combiner.

emerging high-data-rate indoor short-range wireless standards such as WirelessHD and WiGig. A simple 1:1 transformer can perform differential-to-singleended conversion, and PAs with such transformers have demonstrated up to 12 dBm of output power with a 1-V supply [16]. Higher output power levels have also been obtained by combining multiple differential pairs through PCT [52] or a combination of SCT and PCT [53]. However, a pure SCT is preferred for higher output power at millimeter-wave frequencies due to the lower input impedance. Fig. 15 shows the proposed dual-differential-input DAT power combiner, which is essentially an SCT. The original DAT structure introduced in [8] has four differential input ports. Due to the physical locations of the input ports, the structure requires a complicated input distribution network and this proves to be very lossy at millimeter-wave frequencies [51]. Given the limited power gain of the output stage, usually below 10 dB at 60 GHz, the driver power consumption is usually a significant portion of the total power. With a complex distribution network, the driver stage is even more burdened to compensate for the loss. In contrast, the proposed dual-differential-input DAT has fewer input ports, and their physical location allows much simpler input distribution, which eventually leads to higher efficiency. As discussed earlier, multiple metal layers can be strapped to improve the -factor of on-chip passives. In this design, the aluminum capping layer is strapped together with the top copper layer to form the primary winding of the transformer. By increasing the thickness more than 130%, the -factor is improved by nearly 50%, reaching 15.5 at 60 GHz. This enables the DAT power combiner to achieve a low insertion loss of 0.65 dB.

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Fig. 16. Schematic of the three-stage 60-GHz CMOS PA.

Fig. 18. Chip micrograph of the 65 nm 60 GHz PA.

C. “Digital” CMOS PA

Fig. 17. Measurement results of the 60-GHz CMOS PA.

Characterization of power transistor behaviors at millimeter-wave frequencies is important to minimize the device model uncertainty. Special attention is paid to the layout style in order to maximize the transistor maximum stable gain. An iterative output stage design procedure results in an optimal transistor size of 140 m with 2- m finger width. A stand-alone 140- m power transistor was fabricated and two-port -parameters of the common-source configuration were measured up to 110 GHz for different bias points. To capture the inductive parasitic effects—not negligible due to the power-transistor dimension—a lumped-element model using inductors and resistors are wrapped around the core BSIM model. This results in better matching between the simulation and measurement at millimeter-wave frequencies. Fig. 16 shows the schematic of the PA. The prototype includes three active gain stages while the same DAT structure is also used as a part of the compact signal distribution network for the output stage. The PA is fabricated in a 65-nm 1P7M CMOS process. The measurement results are shown in Fig. 17. It achieves a power gain of 20.2 dB and a 3-dB bandwidth of 9 GHz. With a 1-V supply voltage, the measured 1-dB gaincompressed output power is 15 dBm, and the saturated output power is 18.6 dBm. The measured peak PAE is 15.1%, and the peak drain efficiency is 16.4%. The power performance is also measured over the IEEE 802.15.3c band from 58 to 64 GHz, , 13.8 dBm , over which the PA maintains 17.8 dBm and 12.6% PAE. Finally, the PA was tested with the 512-subcarrier 16-QAM OFDM signal at a 4-Gb/s data rate. An EVM of 20 dB was achieved with an average output power of 8 dBm. A chip micrograph of the PA is shown in Fig. 18.

In the previous sections, we described a high-power linear CMOS power amplifier, employing a transformer-based on-chip power combiner. Since the input signal to the power amplifier has a varying envelope, a linear PA (Classes A/AB/B), like the one described, needs to be used. As discussed earlier, the polar architecture has emerged as a promising system-level approach for the realization of a flexible, efficient TX architecture which can allow the use of more efficient nonlinear PAs. In a classic implementation, the amplitude modulation is reconstructed by varying the supply voltage of a saturated PA. This is achieved by using dedicated supply modulators, either switch-mode or linear regulators. However, such supply modulators have an efficiency–bandwidth tradeoff. In addition to the efficiency–linearity tradeoff that is inherent in conventional analog transmitters, such analog systems also require a large number of passive matching networks. Analog and RF circuits do not scale well with technology, since the area of the passive components at a given frequency is almost constant over technology nodes. Thus, a solution that employs fewer passives, has a smaller form-factor, and is scalable to newer technology nodes would be very attractive. A digitally modulated polar PA has the potential of allowing such a scalable solution, while simultaneously breaking the efficiency–bandwidth tradeoff found in analog supply modulators. In addition, it can conserve power by merging more functionalities into one block. The principle of such a mixed-signal sosignal lution is shown in Fig. 19 [27], [28]. The amplitude is in the digital domain, while the phase bits are used to gen. In such a system, erate a phase-modulated RF signal the core PA is sliced into several weighted unit cells (like in a DAC), which are turned on or off by the amplitude control word . In this way, the amplitude information is transmitted. By employing such a digital switching technique, the analog circuit complexity is reduced, since wide-bandwidth supply modulators are avoided and the circuit is more directly interfaced

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Fig. 19. Digitally modulated polar PA. Fig. 21. Block diagram of the mixed-signal polar transmitter.

Fig. 20. Inverse Class-D D

power amplifier.

to the digital baseband. In addition, because of the digital na, simple inverters can be used as drivers, elimiture of nating the need for inter-stage matching networks. The output matching network will still be needed for optimizing power and efficiency. Such a mixed-signal transmitter thus has the potential for multimode operation. In this paper, we provide an example design of such a mixedsignal transmitter architecture with major focus on an efficient PA design [46]. We will show how an efficient yet compact switching PA can be designed and how it can be operated as an RF DAC. The work in [46] proposes the use of a current-mode PA. Such an amplifier is illustrated in inverse Class-D D Fig. 20. This amplifier is the dual of a conventional Class-D PA [47] and uses only one parallel LC tank that can be conveniently absorbed into the output transformer network. In a Class-D PA, the current through the transistor is a square wave, whereas the output voltage is sinusoidal (due to the parallel resonant network). Similar to other switching PAs, the overlap between high voltage and high current is avoided, thereby achieving 100% ideal drain efficiency. In addition, when the transistor turns on, the voltage across the transistor is zero. Thus, the output capacitance discharge problem is eliminated, just like in a Class-E amplifier. The design equations and optimization procedure has been outlined in details in [48]. As we clearly see, the passive network complexity is greatly reduced in this topology. The tank required in this design ( and in Fig. 20) parallel is realized using an on-chip transformer, which simultaneously performs impedance transformation and differential-to-single ended conversion. The architecture of transformer-coupled inverse Class-D PA is thus very compact and amenable to integration in nanoscale CMOS processes. The amplitude and phase resolution of the system is determined by two major considerations—signal integrity (i.e., EVM and transmit mask) requirements and out-of-band noise floor.

Fig. 22. Chip micrograph of the 65-nm mixed-signal polar PA.

Out-of-band noise in particular requires increasing attention due to coexistence considerations. In order to have a noise density better than 140 dBc/Hz and an EVM better than 28 dB (for 20-MHz 802.11g standard), 8 b of resolution on amplitude path and 10 b on phase path were needed. Oversampling (1-GHz clock rate) is employed on both amplitude and phase paths to further reduce noise density. However, to further reduce the out-of-band noise as required in stringent coexistence cases, higher resolution on the RF DAC may be needed, as demonstrated in [30], in which a 17-b DAC driver PA achieves better than 158-dBc/Hz noise. A block diagram of the complete system is shown in Fig. 21. In this prototype, the baseband data generator, cordic algorithm, and lookup tables (LUTs) for predistortion are implemented in an FPGA. The eight amplitude bits at 200 MHz are fed directly to the chip, while the phase bits are fed to an external DAC/modulator chip to create a 2.4-GHz phase-modulated signal. On the phase path, all LO distribution and clock trees are integrated on-chip. On the amplitude path, digital filters, binary-to-thermometer decoder, NAND gates, driver inverters, and PA array are all implemented on-chip. The chip has been fabricated in 65-nm digital CMOS process without any RF options (Fig. 22). Operating from a 1-V supply,

NIKNEJAD et al.: DESIGN OF CMOS POWER AMPLIFIERS

the PA achieves a peak output power of 21.8 dBm. The peak efficiency (including matching network loss) is 44%, while the PAE (including power of all drivers, decoders, LO distribution, and clock receivers) is 38%. While similar PA efficiencies were also achieved using linear Class-AB power amplifiers [14], [45], [50], it should be noted that such Class-AB amplifiers employ ultrathick metal (UTM) and operate from a higher supply voltage using thick-oxide devices. The AM–AM and AM–PM errors have been corrected using independent LUTs for a nominal load. Finally, the transmitter was tested with 802.11g 54-Mb/s 64-QAM WLAN OFDM signal. The transmitter output spectrum meets WLAN requirements with high margin. The measured EVM is 28 dB, while transmitting an average power of 14 dBm with 18% average PA efficiency. The average power consumption of the entire transmitter is only 150 mW, which is lower than traditional WLAN transmitter power consumption. The advantage of such a digital PA is that it includes more functionality (like DAC or a mixer) than a stand-alone PA. Hence, from a complete transmitter point of view, the mixed-signal polar transmitter described here is more power-efficient. V. CONCLUSION CMOS PAs are one of the last hurdles in the realization of an ultralow-cost single-chip RF system. As highlighted in this paper, much progress has been made in the past decade towards improving the output power and the efficiency of CMOS-based PAs through circuit and architecture innovation. At the same time, much more progress is still needed, since technology advancements tend to make the design of CMOS PAs even more difficult, and new applications emerge in the millimeter-wave bands. We therefore expect this field of study to have an equally vibrant and rich future. ACKNOWLEDGMENT The authors would like to thank STMicroelectronics for foundry donation. REFERENCES [1] K. C. Tsai and P. R. Gray, “A 1.9-GHz, 1-W CMOS class-E power amplifier for wireless communications,” IEEE J. Solid-State Circuits, vol. 34, no. 7, pp. 962–970, Jul. 1999. [2] C. Yoo and Q. Huang, “A common-gate switched, 0.9 W class-E power amplifier with 41% PAE in 0.25 m CMOS,” in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2000, pp. 56–57. [3] P. Asbeck and C. Fallesen, “A 29 dBm 1.9 GHz class B power amplifier in a digital CMOS process,” in Proc. ICECS, 2000, vol. 1, pp. 17–20. [4] T. C. Kuo and B. Lusignan, “A 1.5 W class-F RF power amplifier in 0.2 m CMOS technology,” in ISSCC Dig. Tech. Papers, 2001, pp. 154–155. [5] A. Shirvani, D. K. Su, and B. Wooley, “A CMOS RF power amplifier with parallel amplification for efficient power control,” in ISSCC Dig. Tech. Papers, 2001, pp. 156–157. [6] C. Fallesen and P. Asbeck, “A 1 W 0.35 m CMOS power amplifier for GSM-1800 with 45% PAE,” in ISSCC Dig. Tech. Papers, 2001, pp. 158–159. [7] W. Simburger, H.-D. Wohlmuth, and P. Weger, “A monolithic 3.7 W silicon power amplifier with 59% PAE at 0.9 GHz,” in ISSCC Dig. Tech. Papers, 1999, pp. 230–231. [8] I. Aoki, S. Kee, D. Rutledge, and A. Hajimiri, “Distributed active transformer—A new power-combining and impedance-transformation technique,” IEEE Trans. Microw. Theory Tech., vol. 50, no. 1, pp. 316–331, Jan. 2002.

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[34] J. Craninckx and M. Steyaert, “A 1.8-GHz low-phase-noise spiral-LC CMOS VCO,” in VLSI Dig. Tech. Papers, Jun. 1996, pp. 30–31. [35] A. M. Niknejad and R. G. Meyer, “Analysis of eddy-current losses over conductive substrates with applications to monolithic inductors and transformers,” IEEE Trans. Microw. Theory Tech., vol. 49, no. 1, pp. 166–176, Jan. 2001. [36] S. Emami, C. H. Doan, A. M. Niknejad, and R. W. Brodersen, “Largesignal millimeter-wave CMOS modeling with BSIM3,” in RFIC Dig. Papers, 2004, pp. 163–166. [37] A. M. Niknejad, Electromagnetics for High-Speed Analog and Digital Communication Circuits. Cambrdige, U.K.: Cambridge Univ., 2007. [38] T. Sowlati and D. Leenaerts, “2.4 GHz 0.18 m CMOS self-biased cascode power amplifier with 23 dBm output power,” in ISSCC Dig. Tech. Papers, Feb. 2002, pp. 294–295. [39] D. Chowdhury, P. Reynaert, and A. M. Niknejad, “Transformer-coupled power amplifier stability power back-off analysis,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 55, no. 6, pp. 507–511, Jun. 2008. [40] G. Liu, P. Haldi, T.-J. King-Liu, and A. M. Niknejad, “Fully integrated CMOS power amplifier with efficiency enhancement at power backoff,” IEEE J. Solid-State Circuits, vol. 43, no. 3, pp. 600–609, Mar. 2008. [41] K. H. An, “Power-combining transformer techniques for fully-integrated CMOS power amplifiers,” IEEE J. Solid-State Circuits, vol. 43, no. 5, pp. 1064–1075, May 2008. [42] Y. Palaskas, S. S. Taylor, A. Pellerano, I. Rippke, R. Bishop, A. Ravi, H. Lakdawala, and K. Soumyanath, “A 5 GHz class-AB power amplifier in 90 nm CMOS with digitally-assisted AM-PM correction,” in Proc. IEEE CICC, Sep. 2005, pp. 813–816. [43] C. Wang, M. Vaidyanathan, and L. E. Larson, “A capacitance-compensation technique for improved linearity in CMOS class-AB power amplifiers,” IEEE J. Solid-State Circuits, vol. 39, no. 11, pp. 1927–1937, Nov. 2004. [44] J. Kang, A. Hajimiri, and B. Kim, “A single-chip linear CMOS power amplifier for 2.4 GHz WLAN,” in Proc. ISSCC, 2006, pp. 761–769. [45] A. Afsahi and L. E. Larson, “An integrated 33.5 dBm linear 2.4 GHz power amplifier in 65 nm CMOS for WLAN applications,” in Proc. CICC, Sep. 2010, pp. 1–4. [46] D. Chowdhury, L. Ye, E. Alon, and A. M. Niknejad, “An efficient mixed-signal 2.4-GHz polar power amplifier in 65-nm CMOS technology,” IEEE J. Solid-State Circuits, vol. 46, no. 8, pp. 1796–1809, Aug. 2011. [47] T. P. Hung, A. G. Metzger, P. J. Zampardi, M. Iwamoto, and P. M. Asbeck, “Design of high-efficiency current-mode class-D amplifiers for wireless handsets,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 1, pp. 144–151, Jan. 2005. [48] D. Chowdhury, S. V. Thyagarajan, L. Ye, E. Alon, and A. M. Niknejad, “A fully-integrated efficient CMOS inverse Class-D power amplifier for digital polar transmitters,” in Proc. RFIC, Jun. 2011, pp. 1–4. [49] P. Reynaert and M. Steyaert, RF Power Amplifiers for Mobile Communications. Dordrecht, The Netherlands: Springer, 2006. [50] O. Degani, F. Cossoy, S. Shahaf, D. Chowdhury, C. D. Hull, C. Emanuel, and R. Shmuel, “A 90 nm CMOS power amplifier for 802.16e (WiMAX) applications,” in Proc. IEEE RFIC, Jun. 2009, pp. 373–376. [51] U. R. Pfeiffer and D. Goren, “A 23-dBm 60-GHz distributed active transformer in a silicon process technology,” IEEE Trans. Microw. Theory Tech., vol. 55, no. 5, pp. 857–865, May 2007. [52] B. Martineau, V. Knopik, A. Siligaris, F. Gianesello, and D. Belot, “A 53-to-68 GHz 18 dBm power amplifier with an 8-way combiner in standard 65 nm CMOS,” in ISSCC Dig. Tech. Papers, Feb. 2010, pp. 428–429. [53] J.-W. Lai and A. Valdes-Garcia, “A 1 V 17.9 dBm 60 GHz power amplifier in standard 65 nm CMOS,” in ISSCC Dig. Tech. Papers, Feb. 2010, pp. 424–425.

Ali M. Niknejad (SM’10) received the B.S.E.E. degree from the University of California, Los Angeles, in 1994, and the M.S. and Ph.D. degrees in electrical engineering from the University of California, Berkeley, in 1997 and 2000, respectively. He is currently an Associate Professor with the Electrical Engineering and Computer Science Department, University of California, Berkeley, and Codirector of the Berkeley Wireless Research Center and the BSIM Research Group. He is a cofounder of HMicro and inventor of the REACH technology, which has the potential to deliver robust wireless solutions to the healthcare industry. His research interests lie within the area of wireless and broadband communications and biomedical imaging (RF, millimeter-wave, and subterahertz), including the implementation of integrated communication systems in silicon using CMOS, SiGe, and BiCMOS processes. The focus areas of his research include analog, RF, mixed-signal, millimeter-wave circuits, device physics and compact modeling, and numerical techniques in electromagnetics.

Debopriyo Chowdhury (M’10) received the B.Tech. degree from the Indian Institute of Technology, Kharagpur, India, in 2005, and the Ph.D. degree from the University of California, Berkeley, in 2010, both in electrical engineering. He is currently a Staff Scientist with Broadcom Corporation, San Diego, CA, working on next-generation mobile wireless solutions. His major research interests are in RF and millimeter-wave circuits, power amplifiers, high-speed circuits, and biomedical devices. He has held internship positions at Qualcomm Inc., Santa Clara, CA, with the Advanced RF Technology Group at Intel Corporation, Hillsboro, OR, and with Texas Instruments India Pvt. Ltd. Dr. Chowdhury was the recipient of the IEEE Microwave Graduate Fellowship in 2008 and the prestigious Intel Fellowship for graduate studies in 08–09. He was also the corecipient of the Best Student Paper Award at IEEE RFIC in 2007 and the Intel-CICC Student Scholarship Award in 2010.

Jiashu Chen (S’11) received the B.E. degree in electronic engineering (with First Class Honours) from City University of Hong Kong, Hong Kong, in 2007. He is currently working toward the Ph.D. degree at the University of California, Berkeley. As an undergraduate student, he also studied at Fudan University in Shanghai and Carnegie Mellon University, Pittsburgh, PA. He is a Member of the Berkeley Wireless Research Center (BWRC). He held an internship position at Maxim Integrated Products, Inc., in 2010. His research focuses on power amplifiers in silicon technologies, millimeter-wave beamforming transceivers, and advanced transmitter architectures. Mr. Chen is a recipient of the prestigious 2007 International Fulbright Science and Technology Fellowship, which is awarded by the U.S. Department of State to 27 international Ph.D. students out of 110 nominations from 70 countries. He is also a recipient of many other awards, including the Best Student Paper Award at the 2010 Radio Frequency Integrated Circuits Symposium, Analog Devices Outstanding Student Designer Award in 2011, the IEEE Microwave Theory and Techniques Society (MTT-S) Undergraduate/Pre-graduate Fellowship in 2007, and the Scholarship for Outstanding Chinese Mainland Students from the Hong Kong University Grants Committee in 2004.

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Controlling Active Load–Pull in a Dual-Input Inverse Load Modulated Doherty Architecture Thomas M. Hone, Souheil Bensmida, Member, IEEE, Kevin A. Morris, Mark A. Beach, Member, IEEE, Joe P. McGeehan, Jonathan Lees, Johannes Benedikt, and Paul J. Tasker, Senior Member, IEEE

Abstract—Mathematical analysis of Doherty amplifiers have assumed many simplifications. Most notably, the peaking amplifier does not contribute power into the load and the peaking stage has an observed impedance of infinity. This paper will show that these simplifications impair the performance of a single-input Doherty amplifier and that phase tuning for compensation is needed to improve the overall system performance. The dual-input Doherty amplifier is capable of overcoming the limitations of power-dependent phase imbalance and phase compensation lines at the input of the peaking stage; however, the characterization of such an architecture is not straightforward. A new measurement technique is proposed to measure dc current, dc voltage, and output power levels to allow unique characterization of a dual-input Doherty amplifier. Phase compensation lines at the input of the peaking amplifier will be shown to be not required, as long as correct offset lines are calculated for both the carrier and peaking stage and that the transmission-line length is not necessarily required for active load–pull. Results of a dual-input inverse load modulated Doherty amplifier are presented where the peaking stage delivers 10 dB less of maximum output power than the carrier, while still maintaining Doherty behavior. The peaking stage can therefore be implemented with a smaller device than the carrier. Index Terms—Active load–pull, dual-input Doherty amplifier, inverse load modulation.

I. INTRODUCTION

T

HE efficiency performance of an amplifier at any output power back-off level is important when amplifying signals with large peak-to-average power ratios (PAPRs), such that a high average efficiency can be achieved [1]. Long-term evolution (LTE) utilizes the orthogonal frequency division multiplexing (OFDM) modulation scheme, where the PAPR of an LTE signal can be more than 10 dB depending on the bandwidth the signal occupies and on the superposition of the sub-carriers [2]. To ensure that such a signal is efficiently amplified, amplifiers are designed and incorporated as part of an efficiency enhancing architecture where the efficiency performance at output Manuscript received September 30, 2011; revised February 14, 2012; accepted February 21, 2012. Date of publication April 12, 2012; date of current version May 25, 2012. This work was supported by the Engineering and Physical Sciences Research Council (EPSRC) under Grant EP/F033370/1 and Grant EP/F033702/1. T. M. Hone, S. Bensmida, K. A. Morris, M. A. Beach, and J. P. McGeehan are with the Centre for Communications Research, University of Bristol, Bristol BS8 1UB, U.K. (e-mail: [email protected]). J. Lees, J. Benedikt, and P. J. Tasker are with the High Frequency Centre, Cardiff School of Engineering, Cardiff CF24 3AA, U.K. (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2012.2190748

power back-off is dramatically improved compared to a singlestage amplifier [3]. Active load modulated architectures are one of three different types of efficiency enhancing schemes. The Doherty amplifier is currently a popular active load modulated architecture and achieves this performance by using a quarter-wavelength transmission-line impedance-transformation network [4]. The Doherty amplifier has been extensively mathematically analyzed for efficiency [5], behavior modeling and generalized equations for Doherty designs [6], [7]. However, these ideal mathematical equations do not include the impact of the knee voltage. They also assume that the peaking stage does not deliver power into the load and that the observed impedance of the peaking amplifier is infinity. When applying these ideal design equations to transistor-based implementations, it becomes apparent that they do not match the physical performance of the Doherty amplifier. It has been shown in [8] that the knee voltage affects the value of the load line required for a specific output power back-off level and they have included their observations into the ideal mathematical Doherty design equations. The findings from [9] confirm that the observed impedance of a transistor is not infinity, causing output power to leak through the peaking stage if it is not taken into consideration. The modern Doherty amplifier has been tuned such that these practical limitations can be overcome. The bias condition for the peaking amplifier can reduce the amount of power that is wasted through leakage [10] and is typically biased in class C. However, a class C bias condition reduces the maximum output power of the peaking stage compared to the carrier stage, which is conventionally biased in class AB/B. This creates an output power ratio misalignment such that under saturated active load–pull occurs. Asymmetrical designs [11], uneven power splitting at the input [12], and uneven power drive with power matching [13] have been proposed to solve this problem. The asymmetrical designs require a larger device for the peaking stage, which is not always viable. The single-input Doherty amplifier using a power divider also suffers from power-dependent phase imbalance between the carrier and peaking stages resulting in suboptimal performance. By varying the gate voltage at both the carrier and peaking amplifier, it is possible to rematch the Doherty configuration as close as possible to the correct load lines [14]. An alternative means of resolving the power-dependent phase imbalance is to split the input of the carrier and peaking stages such that they are independent of each other [15]. By applying phase control to one of the inputs, the power-dependent phase imbalance can be overcome.

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Fig. 1. Simplified model of a classical Doherty amplifier, 50- load transformed into an intermediate 25- load using a 35.4- quarter-wavelength transmission line.

These extensive optimizations have made the Doherty amplifier very unforgiving toward bad design, where the calculation of a bad phase-offset line can impair the efficiency performance of the architecture. This paper will present the impact of the peaking amplifier injecting power into the common load, the importance of the offset lines in active load–pull, and that the transmission line length is not necessarily required for active load–pull. A generic method of extracting the required input waveforms will be shown for a dual-input Doherty architecture with no phase compensation delay lines at the input. Finally, the results of a dual-input inverse load modulated Doherty amplifier using the proposed measurement technique will be shown where the carrier and peaking stage maximum output power is 39.5 and 30 dBm, respectively, a 10-dB difference, allowing for a smaller peaking stage with respect to the carrier. The peaking amplifier therefore does not contribute power into the load at low output power levels. II. ACTIVE LOAD MODULATION Fig. 1 shows a simplified model of a classical Doherty amplifier consisting of two amplifiers, the carrier and peaking amplifiers, with a 50- characteristic impedance transmission line situated between the two stages. A 35.4- characteristic impedance transmission line is used to transform a load, typically 50 , into a 25- load. The carrier and peaking amplifier deliver the currents and , respectively, where the current is the transformed current caused by the transmission line. The impedance is determined by the parallel combination of the transformed load impedance, 25 , and the apparent impedance of the peaking amplifier. For this analysis, it is assumed that the peaking stage has an apparent impedance of , and thus is 25 . This is an assumption and its effect will be explored and explained in greater detail in Section III. The impedance is the transformed impedance of about the origin of the Smith chart determined by (1), where is the characteristic impedance of the line. In a classical Doherty design, as shown in Fig. 1, when the peaking stage is switched off, the impedance presented to the carrier stage is 100 (1) (2)

Fig. 2. Simulated voltages metrical Doherty amplifier.

(circle) and

(square) of a classical unsym-

To achieve active load–pull, the voltage across impedance has to be controlled such that (2) is obeyed. is regarded as constant, voltage is determined by the output of the carrier amplifier and should remain constant if the correct value of is presented. By varying voltage , which is bound between and V, the impedance presented to the carrier amplifier can be controlled from 50 to 100 . Equation (2) assumes that the peaking stage only controls the voltage across . The peaking amplifier achieves this in reality by contributing power into . This means that the voltage , across , is capable of going above the drain supply voltage of the carrier amplifier because two in-phase signals with maximum equal voltage swing can superimpose on each other. This in turn means that the voltage is also capable of exceeding the drain supply voltage of the carrier. A simulation of a classical unsymmetrical Doherty amplifier with 12-dB dynamic output power was designed using a junction field-effect transistor (JFET) model both for the carrier and peaking stages using Agilent’s Advanced Design System (ADS), where a classical unsymmetrical Doherty amplifier is defined by a single common input, which is split equally using a lossless splitter to drive the carrier and peaking amplifier. The carrier and peaking stages are biased in class B and C, respectively, and the peaking stage current density is twice that of the carrier, making it unsymmetrical. Fig. 2 shows the voltages (circle) and (square) of the simulated circuit. From 21 to 32 dBm of output power level, increases approximately linearly with the input drive of the carrier. The peaking stage, which is biased in deep class C, does not conduct within this region of operation. From 32- to 45-dBm output power, active load–pull occurs and as expected, voltage is kept constant. The peaking amplifier conducts in this region and delivers power into the load to enable the active load–pull phenomena. Equation (2) is valid until a maximum output power of 41 dBm. Above this power level, the peaking stage does not only load–pull the load line for the main stage, but also contributes significantly to the overall output power because of the in-phase superposition. This is in accordance with

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Fig. 3. Measurements from 850 to 950 MHz of observed output impedances of two amplifiers biased from deep AB to class C.

what has been reported in [16] and contributes to incorrect active load modulation. The maximum output power of this architecture is the maximum output power of the carrier stage plus 3 dB as classical Doherty theory states that the carrier and peaking amplifier stages must be equal in size. The extra 3 dB is not always obtained due to the power leakage through the peaking stage since its impedance is not necessarily . To minimize the power that is leaked through the peaking amplifier, a quasi-open circuit condition is required. III. QUASI-OPEN CIRCUIT If the peaking amplifier is incorrectly combined together with the carrier amplifier in a Doherty configuration, current may leak through the peaking stage. This results in a reduction of maximum obtainable output power and system efficiency. This is caused because there is no isolation provided by the transmission line situated between the carrier and peaking amplifier stages. From the carrier stage perspective, the impedance presented by the peaking stage is in parallel with a 50- load, as seen in Fig. 1. Simple linear circuit theory states that current from the carrier will split depending on the values of the two parallel loads. To maximize the current into the 50- load, and thus maximize power transfer into the load, the impedance of the peaking stage must be , which cannot be achieved in reality. The observed impedance of a biased amplifier with no RF input is dependent on the bias condition and the output matching network. Fig. 3 shows the measured observed impedances from 850 to 950 MHz of two different fully matched GaN HEMT (CREE CGH40010) amplifiers with varying gate bias levels. The gate voltage of both amplifiers was varied such that the quiescent drain current was varied from deep AB ( mA) to class C with a drain supply voltage of 28 V. The measurements were taken by connecting a vector network analyzer directly to the output terminal of the fully matched amplifiers and measuring the reflection coefficient. Class B and C bias conditions produce impedances near the edge of the Smith chart and are therefore the most suitable classes of operation for the peaking amplifier. By driving into deep class

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Fig. 4. Photograph of the “inverse-load modulated” Doherty amplifier.

C, the impedance cannot be moved closer to the edge of the Smith chart. The design of the output matching network can impact the observed impedance of an amplifier in magnitude and phase. Fig. 3 shows that the second GaN HEMT amplifier is more sensitive towards frequency, but produces a similar magnitude response as the first amplifier. The magnitude response is similar because identical devices are used for both amplifiers. The frequency sensitivity is caused by the design of the output matching network of the two amplifiers. The first amplifier uses a broadband fundamental matching network, which has no stubs, where the design is similar to the amplifier reported in [17]. The second amplifier, presented in [18], uses a complex harmonically designed matching network, which uses stubs. Although this network presents the correct required impedances for its class of operation, it inherently exhibits a large frequency dependence in terms of scattering parameters. Fig. 4 presents a photograph of the two amplifiers combined together in an “inverse-load modulated” architecture. The observed impedance of an amplifier can be transformed toward the real axis by using an offset line [19]. If the transformation is done toward a perfect open, a quasi-open circuit condition can be achieved, as shown in Fig. 5. This is done by using a T-junction made from a transmission line and several SMA adaptors. By experimentally adding or removing SMA adaptors, the offset length can be tuned. The T-junction consists of three different branch lengths such that a greater selection of adaptor and T-junction combinations can be implemented. The maximum impedances that can be obtained are 560 and 670 at 900 MHz for amplifier 1 and 2, respectively, both biased in class C. The second amplifier will be used throughout this paper as the peaking stage, while the first amplifier will be used for the carrier stage. The quasi-open circuit offset line length for the peaking stage is determined when the GaN HEMT is biased with no RF input. When the carrier amplifier is turned on, the observed impedance of the carrier amplifier transforms away from the quasi-open circuit, as shown in Fig. 5 using triangle markers. The channel becomes the equivalent of an open, which is transformed toward a complex value due to the parasitic power dependent elements within the transistor

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Fig. 6. “Inverse-load modulated” combining structure.

Fig. 5. Quasi-open circuit measurements of amplifier 1 (circle) and amplifier 2 (square). Simulated results of how the quasi-open circuit of amplifier 1 (triangle) is affected when driven with an RF signal.

package and die, such as the nonlinear [20]. This explains the power-dependent phase misalignment between the carrier and peaking stage at different output powers. The impedance becomes complex because the complex observed impedance of the peaking stage combines in parallel with a purely real load. The peaking amplifier must inject the appropriate conjugate phase component to ensure that the complex part of is cancelled out such that the transformation of the impedance remains purely real, as dictated by (2). A dual-input Doherty design is capable of achieving this without the need for an uneven input power design and complex phase compensation at the input of the peaking amplifier. A simulation of a fully matched GaN HEMT (CREE CGH40010 model) shows the quasi-open circuit shifting away from the original measured quasi-open circuit point when driving a transistor, as seen in Fig. 5. It has been shown in [21] that a 50- characteristic impedance transmission line and a 50- load, where the static load line is 50 , can produce identical Doherty behavior as a 50- characteristic impedance transmission line with a 25- load, where the static load line is 100 . This “inverse-load modulated” combining structure requires less current and thus less power to achieve optimal active load–pull, allowing for the use of a smaller peaking amplifier compared to the carrier amplifier. This would be beneficial for base stations, where power consumption and availability of a larger peaking amplifier are problematic, and handsets, where power consumption is important. The decrease in the magnitude of the observed impedance when an amplifier begins to conduct can be taken advantage off in an inverse load modulated combining network. The decreasing value of will transform toward an increasing value of , which aids the active load–pull requirements for an “inverse-load modulated” architecture. IV. EXPERIMENTAL SETUP Two harmonically tuned amplifiers biased in class B (1-mA quiescent current ) and C (0-mA quiescent current ) for the carrier and peaking stage, respectively, are combined

Fig. 7. Impedances presented to the carrier amplifier (circle) and peaking amplifier (square) from 850 to 950 MHz. The markers are placed at 900 MHz.

together using two offset lines with a common 50- load, an inverse load modulated combiner, as shown in Fig. 6. The drain voltage terminals of the carrier and peaking stage are biased at 28 V and are connected together such that the system current could be measured for any given carrier input, allowing for the calculation of the system efficiency. The offset lengths and are determined such that both the carrier and peaking amplifiers see as close as possible to 50 when both amplifiers are biased with no RF input, as shown in Fig. 7, where the measurements are taken from 850 to 950 MHz. At 900 MHz, the carrier (circle) and peaking (square) are presented with 49 and 45 , respectively. This prevents any mismatch for the static load line case and ensures maximum power transfer from both the carrier and peaking amplifiers into the load. In this configuration, the transmission line length is not important as long as the starting conditions of the carrier and peaking amplifier are met as stated above. The carrier offset line will both act as a quasi-open circuit enabler and a complex impedance transformation network, where the transformation depends on the length . The complete measurement set up is shown in Fig. 8. The carrier amplifier (PA1) is driven by a repeatable envelope signal scanning its entire input dynamic range. During every envelope period, a driving signal with a specific combination of magnitude and phase is applied to the input of the peaking amplifier (PA2). This presents a set of load lines to both the carrier and peaking amplifier stages. By sweeping the magnitude and phase

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Fig. 8. Measurement setup.

of the peaking amplifier input signal, the entire Smith chart is scanned, presenting all possible impedances on the Smith chart to the carrier amplifier and all corresponding reverse load–pull impedances to the peaking amplifier. To calculate the dc power consumption, and are measured using the high-frequency oscilloscope (LeCroy 6100 A) and the current probe (Tektronix TCP300), respectively. The drain terminals of the carrier and peaking stage are connected together such that the system and are measured. The RF output power is calculated using the vector signal analyzer (VSA Rhode & Schwartz FSQ) to capture the output waveform, which is normalized to its mean value. It is then multiplied by the average output power measured using a power probe at the output of the combiner. A similar procedure is used to calculate the input power level of the carrier stage, where the input waveform is extracted from the arbitrary signal generator (ARB Rhode & Schwartz SMATE 200 A) at baseband. This allows for the calculation of instantaneous drain efficiency for any dual-input Doherty amplifier. The input of the peaking amplifier is also extracted at baseband from the arbitrary signal generator and its magnitude is normalized. This measurement set up allows for faster and realistic environment characterization of any dual-input Doherty amplifier unlike continuous wave (CW) measurements, which are more time consuming and tedious. V. MEASUREMENT RESULTS Fig. 9 shows all instantaneous drain efficiencies for any given output power at 900 MHz. A maximum drain efficiency of 65% is achieved with a drain efficiency of 48% at 6-dB output power back-off. From the complete data set, Fig. 9, where every possible combination of carrier and peaking output power combines together and performs active load–pull, Fig. 10 is produced by extracting the maximum points for any given output power level by using a script for post processing on the complete data set. In order to highlight the usefulness of the proposed characterization procedure, the two dual drive inputs have been driven with the same signal in order to simulate a single input classical architecture, and the resulting efficiency (square markers) is shown in Fig. 10. This implies that optimizing an “inverse-load modulated” Doherty architecture requires independent dual drive inputs. The complex input envelope of the peaking amplifier that corresponds to the efficiency profile shown in Fig. 10 can at this

Fig. 9. Active load–pull measurement results for all possible carrier and peaking amplifiers output power combinations.

Fig. 10. Maximum drain efficiency profile from complete data set (circle). Drain efficiency profile while the structure is in a single input configuration (square).

stage be easily extracted. In other words, the relationship between the carrier amplifier driving signal and the peaking amplifier driving signal that optimizes efficiency is extracted. Fig. 11 shows this complex function in terms of magnitude and phase. It was expected that the peaking stage ought to switch off when reaching the maximum output power of the carrier amplifier because the static load line is close to 50 , as discussed in Section IV. Instead the peaking stage is injecting power into the combining network causing a more optimal load line condition for maximum drain efficiency at saturation. This could have only been obtained by using a dual-input architecture and a generic characterization measurement setup. Although one may argue that the use of two signal generators and two drivers increases the complexity of the Doherty architecture. It provides immunity to imperfect offset line calculations at the input, greater flexibility, and reconfigurability. Fig. 12 represents the corresponding amplitude modulation-to-amplitude modulation (AM–AM) and amplitude modulation-to-phase modulation (AM–PM) response while the structure is driven to exhibit the maximum efficiency depicted in Fig. 10. In order to estimate the linearity performance of the

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Fig. 13. Simulated linearity performance using a 1.4-MHz 3GPP LTE signal. Fig. 11. Magnitude (circle) and phase (star) relationship between the carrier amplifier driving signal and peaking amplifier driving signal for maximum drain efficiency.

in [1]. By rearranging the equation, (3) can be obtained, where and are the transformed carrier current, the peaking current, the load impedance and the parallel impedance of the load and peaking amplifier, respectively, as discussed in Section II, Fig. 1. In classical active load modulation, is 25 , while in inverse active load modulation, is 50 , assuming that the and requirements [6], [7] for inverse and classical load modulation are identical. will be smaller for inverse than classical load modulation (3)

Fig. 12. AM–AM (circle) and AM–PM (star) response while the architecture is driven to exhibit the maximum efficiency.

structure, a memoryless behavioral model is extracted from the AM–AM and AM–PM response. A narrowband modulated signal (1.4-MHz 3GPP LTE signal) is applied to the extracted behavioral model and the spectrum regrowth of its output signal is shown in Fig. 13. This gives an idea on the linearity of the structure while the efficiency is the criteria of optimization. The static load condition of 50 seen by both the carrier and peaking amplifier allow for easy assessment of the maximum power each stage injects into the load. When the peaking amplifier is biased with no RF input signal, the carrier amplifier delivers 39.5 dBm of power into the load when it is driven with 27.6 dBm. When the carrier amplifier is biased with no RF input signal, the peaking amplifier delivers 30 dBm of power into the load when it is driven with 16.4 dBm. The peaking amplifier can therefore be implemented using a smaller device with respect to the carrier. This observation can be explained using the equation that explains active load–pull using a generator model, as presented

Although the efficiency performance of a dual-input drive classical Doherty amplifier reported in [15] is better, one can stress that the results reported in this paper are produced using an unoptimized structure. The losses caused by biasing the amplifiers out of their designed specification and the losses induced by using SMA adaptors and a T-junction impair the overall efficiency performance of the architecture. The back-off performance is further impaired by using a 10-W peaking amplifier, when only 1 W of power is required to be delivered by the peaking stage to actively “inverse-load modulate” a 10-W carrier amplifier. VI. CONCLUSION A generic Doherty characterization measurement system has been presented where any dual-input Doherty amplifier can be characterized without the need of input compensation lines. This simplifies the design procedure of Doherty amplifiers and allows for greater flexibility in design. From the total measurement result set, any value of drain efficiency can be extracted with its corresponding input requirements for both the carrier and peaking amplifier. The maximum drain efficiency results have been shown in this paper with a dual-input inverse load modulated Doherty at 900 MHz. By using an inverse load modulated combining architecture, it has been shown that a smaller peaking stage, 10-dB less maximum output power, is capable of achieving identical Doherty behavior and that the electrical lengths for the initial starting conditions for the carrier and peaking stage are more important

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than incorporating a transmission line. This further simplifies the amplifier design by making the calculation of the characteristic impedance of the transmission line for a specific back-off performance obsolete. ACKNOWLEDGMENT The authors would like to thank the Engineering and Physical Sciences Research Council (EPSRC) for their support by funding this work, which has been carried out as part of the Holistic Design of Power Amplifiers for Future Wireless Systems Project. The authors would also like to thank K. Mimis, University of Bristol, Bristol, U.K., and V. Carrubba, Cardiff University, Cardiff, U.K., for the use of their amplifiers within this work. REFERENCES [1] S. C. Cripps, RF Power Amplifiers for Wireless Communications, 2nd ed. Boston, MA: Artech House, 2006. [2] S. H. Han and J. H. Lee, “An overview of peak-to-average power ratio reduction techniques for multicarrier transmission,” IEEE Wireless Commun., vol. 12, no. 2, pp. 56–65, Apr. 2005. [3] P. B. Kenington, High-Linearity RF Amplifier Design. Boston, MA: Artech House, 2000. [4] W. H. Doherty, “A new high efficiency power amplifier for modulated waves,” Proc. IRE, vol. 24, no. 9, pp. 1163–1182, Sep. 1936. [5] F. H. Raab, “Efficiency of Doherty RF power-amplifier systems,” IEEE Trans. Broadcast., vol. BC-33, no. 3, pp. 77–83, Sep. 1987. [6] N. Srirattana, A. Raghavan, D. Heo, P. E. Allen, and J. Laskar, “Analysis and design of a high-efficiency multistage Doherty power amplifier for wireless communications,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 3, pp. 852–860, Mar. 2005. [7] W. C. E. Neo, J. Qureshi, M. J. Pelk, J. R. Gajadharsing, and L. C. N. de Vreede, “A mixed-signal approach towards linear and efficient -way Doherty amplifiers,” IEEE Trans. Microw. Theory Tech., vol. 55, no. 5, pp. 866–879, May 2007. [8] J. Moon, J. Kim, J. Kim, I. Kim, and B. Kim, “Efficiency enhancement of Doherty amplifier through mitigation of the knee voltage effect,” IEEE Trans. Microw. Theory Tech., vol. 59, no. 1, pp. 143–152, Jan. 2011. [9] Y. Yang, J. Cha, B. Shin, and B. Kim, “A fully matched -way Doherty amplifier with optimized linearity,” IEEE Trans. Microw. Theory Tech., vol. 51, no. 3, pp. 986–993, Mar. 2003. [10] S.-C. Jung, O. Hammi, and F. M. Ghannouchi, “Design optimization and DPD linearization of gan based unsymmetrical Doherty power amplifiers for 3G multicarrier applications,” IEEE Trans. Microw. Theory Tech., vol. 57, no. 9, pp. 2105–2113, Sep. 2009. [11] J. Kim, B. Fehri, S. Boumaiza, and J. Wood, “Power efficiency and linearity enhancement using optimized asymmetrical Doherty power amplifiers,” IEEE Trans. Microw. Theory Tech., vol. 59, no. 2, pp. 425–434, Feb. 2011. [12] M. Nick and A. Mortazawi, “Adaptive input power distribution in Doherty power amplifiers for linearity and efficiency enhancement,” IEEE Trans. Microw. Theory Tech., vol. 58, no. 11, pp. 2764–2771, Nov. 2010. [13] J. Kim, J. Cha, I. Kim, and B. Kim, “Optimum operation of asymmetrical-cells-based linear Doherty power amplifiers—Uneven power drive and power matching,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 5, pp. 1802–1809, May 2005. [14] I. Kim and B. Kim, “A 2.655 GHz 3-stage Doherty power amplifier using envelope tracking technique,” in IEEE MTT-S Int. Microw. Symp. Dig., 2010, pp. 1496–1499. [15] R. Darraji, F. M. Ghannouchi, and O. Hammi, “A dual-input digitally driven Doherty amplifier architecture for performance enhancement of Doherty transmitters,” IEEE Trans. Microw. Theory Tech, vol. 59, no. 5, pp. 1284–1293, May 2011. [16] J. Moon, Y. Y. Woo, and B. Kim, “A highly efficienct Doherty power amplifier employing optimized carrier cell,” in Proc. Eur. Microw. Conf., 2009, pp. 1720–1723. [17] K. Mimis, K. A. Morris, and J. P. McGeehan, “A 2 GHz GaN class-J power amplifier for base station applications,” in IEEE MTT-S Radio Wireless Symp., 2011, pp. 5–8.

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[18] V. Carrubba, J. Lees, J. Benedikt, P. J. Tasker, and S. C. Cripps, “A novel highly efficient broadband continuous class-F RFPA delivering 74% average efficiency for an octave bandwidth,” in IEEE MTT-S Int. Microw. Symp. Dig., 2011, pp. 1–4. [19] Y. Yang, J. Yi, Y. Y. Woo, and B. Kim, “Optimum design for linearity and efficiency of a microwave Doherty amplifier using a new load matching technique,” Microw. J., vol. 44, no. 12, pp. 20–36, Dec. 2001. [20] J. Moon, J. Kim, and B. Kim, “Investigation of a class-J power amplifier with a nonlinear cout for optimized operation,” IEEE Trans. Microw. Theory Tech., vol. 58, no. 11, pp. 2800–2811, Nov. 2010. [21] T. Hone, S. BenSmida, M. Paynter, K. Morris, M. Beach, J. McGeehan, J. Lees, J. Benedikt, and P. Tasker, “Optimized load modulation in a Doherty amplifier using a current injection technique,” in Proc. Eur. Microw. Conf., 2011, pp. 296–299. Thomas M. Hone received the M.Eng. degree in electrical and electronic engineering with management from the University of Bristol, Bristol, U.K., in 2009, and is currently working toward the Ph.D. degree at the University of Bristol. His research interest is in efficiency-enhancing architectures for wideband and high PAPR signals and field-programmable gate array (FPGA) implementations of high throughput signal processing.

Souheil Bensmida (M’07) received the D.E.A. degree in electronics and instrumentation from the University of Pierre and Marie Curie Paris 6, Paris, France, in 2000, and the Ph.D. degree in electronics and communications from the Ecole Nationale Supérieure des Télécommunications (ENST), Paris, France, in 2005. From October 2006 to September 2008, he was a Post Doctoral Fellow with the iRadio Laboratory, University of Calgary, Calgary, AB. Canada. He is currently a Research Associate with the University of Bristol, Bristol, U.K. His research interest is the nonlinear characterization and linearization of power amplifiers for mobile and satellite applications and microwave instrumentation. Kevin A. Morris received the B.Eng. and Ph.D. degrees in electronics and communications engineering from the University of Bristol, Bristol, U.K., in 1995 and 1999, respectively. In 1998, he became a Research Associate with the CCR, University of Bristol, a Lecturer in RF engineering in 2001, and Senior Lecturer in August 2007. He is currently involved with a number of research programes within the U.K. He is the principle investigator on a five-year collaborative Engineering and Physical Sciences Research Council (EPSRC) project between the University of Cardiff and University of Bristol. The aim of this project is the rigorous design of efficient power amplifiers for use in future communications systems. He also leads a three-year industrially funded project in the area of efficient linear amplification design. He has authored or coauthored 37 academic papers. He coholds five patents. His research interests are principally in looking at methods of reducing power consumption in communications systems including the area of RF hardware design with specific interest in the design of efficient linear broadband power amplifiers for use within future communications systems. Mark A. Beach (A’90–M’06) received the Ph.D. degree for research addressing the application of smart antennas to global positioning systems (GPSs) from the University of Bristol, Bristol, U.K., in 1989. He subsequently joined the University of Bristol, as a Member of Academic Staff. He was promoted to Senior Lecturer in 1996, Reader in 1998, and Professor in 2003, and from 2006 to 2010, was the Head of the Department of Electrical and Electronic Engineering. His research interests include the application of multiple antenna technology to enhance the performance of wireless systems, with particular emphasis on spatio-temporal aspects of the channel, as well as enabling RF technologies for “green radio.”

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Joe P. McGeehan received the Ph.D. and D.Eng. degrees in electrical and electronic engineering from the University of Liverpool, Liverpool, U.K., in 1971 and 2003, respectively. He is currently the Director of the Centre for Communications Research, University of Bristol, and Senior General Advisor of the Telecommunications Research Laboratory, Toshiba. Since 1973, he has researched spectrum-efficient mobile-radio communication systems and has pioneered work in many areas including linearized power amplifiers, WCDMA (3G), and smart antennas. Dr. McGeehan is a Fellow of the Royal Academy of Engineering. He has served on numerous international committees and was advisor to the U.K.’s first DTI/MOD “Defense Spectrum Review Committee” in the late 1970s. He was the recipient of a CBE in 2004 for services to the communications industry. In 2004, he was listed as one of the world’s top technology agenda setters by silicon.com (USA). He was corecipient of the IEEE Vehicular Technology Transactions’ Neal Shepherd Memorial Award for his work on SMART antennas and the Proceeding of the IEE Mountbatten Premium for work on satellite-tracking.

Jonathan Lees received the B.Eng. degree in electronic engineering from Swansea University, Swansea, U.K., in 1992, and the M.Sc. and Ph.D. degrees from Cardiff University, Cardiff, U.K., in 2001 and 2006, respectively. From 1992 to 2002, he developed global positioning systems and advanced optical instrumentation tracking systems with QinetiQ. He is currently a Lecturer with the Centre for High Frequency Engineering, Cardiff University. His research concerns PA design, load–pull, and large-signal measurement systems. Dr. Lees is a Charted Engineer in the U.K.

Johannes Benedikt received the Dipl.-Ing. degree from the University of Ulm, Ulm, Germany, in 1997, and the Ph.D. degree from Cardiff University, Cardiff, U.K., in 2002. During this time, he was also a Senior Research Associate with Cardiff University, beginning in October 2000, where he supervised a research program with Nokia on RF power amplifiers (RFPAs). In December 2003, he became a Lecturer with Cardiff University, where he was responsible for furthering research in the high-frequency area. In April 2010, he became a Professor with Cardiff University, and is the Chief Technical Officer (CTO) of the successful University spin-off company Mesuro. His main research focus is on development of systems for the measurement and engineering of RF current and voltage waveforms and their application in complex PA design.

Paul J. Tasker (M’88–SM’07) received the B.Sc. degree in physics and electronics and the Ph.D. degree in electronic engineering from Leeds University, Leeds, U.K., in 1979 and 1983 respectively. From 1984 to 1990, he was a Research Associate with Cornell University, Ithaca, NY, where he was involved in the early development of the heterostructure field-effect transistors (HFETs). From 1990 to 1995, he was a Senior Researcher and Manager with the Fraunhofer Institute for Applied Solid State Physics (IAF), Freiburg, Germany, where he was responsible for the development of millimeter-wave monolithic microwave integrated circuits (MMICs). In the summer of 1995, he joined the School of Engineering, Cardiff University, Cardiff, U.K., as a Professor, where he has established the Cardiff University and Agilent Technology Centre for High Frequency Engineering. The center’s research objective is to pioneer the development and application of RF-IV waveform and engineering systems with a particular focus on addressing the PA design problem. He has authored or coauthored over 200 journal and conference publications. Prof. Tasker was an IEEE Distinguished Microwave Lecturer (2008-2010). He has given a number of invited conference workshop presentations.

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-Band MMIC HPA and Driver Amplifiers in InGaP-GaAs HBT Technology for Space SAR T/R Modules Corrado Florian, Member, IEEE, Rudi Paolo Paganelli, and Julio Andres Lonac

Abstract—The chip-set for the transmitting power lineup of satellite SAR antenna T/R modules has been designed and implemented exploiting a 2- m GaInP-GaAs heterojunction bipolar transistor (HBT) technology suitable for space applications. The HBT technology features an integrated emitter ballast resistor that enables high-power density operation without suffering thermal runaway phenomena. Two monolithic microwave integrated circuit (MMIC) driver amplifiers and a MMIC HPA are described: the drivers exhibit small-signal gains exceeding 21 dB and P1 dB output power of about 28 and 29 dBm, respectively, in a 2-GHz bandwidth and CW condition. The HPA delivers more than 40-dBm power at about 2.5-dB gain compression and power-added efficiency (PAE) exceeding 36% in a 700-MHz bandwidth in pulsed operation. Its peak performance at the center of the band are 40.9-dBm output power and 45% PAE. These performance are obtained within tight de-rating conditions for space applications. Index Terms—InGaP-GaAs heterjunction bipolar transistor (HBT), monolithic microwave integrated circuit (MMIC) HPA, power amplifier (PA), synthetic aperture radar (SAR), transmit–receive (T/R) module, -band.

Italia. The four satellites of first generation of Cosmo SkyMed are currently in orbit sending to ground bases a huge amount of information useful for scientific research, Earth monitoring and security in Europe [3]. Indeed the capability of -band SAR to gather ground images continuously, regardless of lightness and weather conditions, is extremely useful in several fields, such as agriculture, floods and earthquake control, natural hazard and sea-level monitoring, boarder control, and military applications. The next-generation SAR antenna addresses increasing performance in terms of duration, coverage, and resolution of the service. As far as regarding the transmitting chain of the T/R module, the demand for improved system performance implies the optimization of key parameters: bandwidth, gain, power-added efficiency (PAE), and output power. To assess the achievable performances, different technologies already suitable for space application (GaAs pHEMT and InGaP-GaAs HBT) and different European suppliers were explored. In the following, the performance achieved by a space-evaluated HBT technology is reported.

I. INTRODUCTION

II. TECHNOLOGY

HIS paper describes the design and performance of two monolithic driver amplifiers and an HPA, operating at -band to be used in the transmitting power lineup of transmit–receive (T/R) modules, employed in satellite synthetic aperture radar (SAR) antennas for earth observation. This activity was promoted by the Italian Space Agency with the object of assessing the achievable performance of new monolithic microwave integrated circuits (MMIC) and technologies for the second generation of Cosmo SkyMed [1], a European constellation of four satellites equipped with SAR antennas [2], whose T/R modules will be produced by Thales Alenia Space

The technology adopted for the design of the MMICs is a GaInP-GaAs HBT of 2- m emitter length with 100- m-thick substrate from UMS foundry. Minimum collector-emitter breakdown voltage is 18 V. Microstrip lines with thickness up to 6.8 m can be used exploiting three metal layers for the minimization of losses. MIM capacitors with 250-pF mm density, spiral inductors, and both TaN and TiWSi metallic resistors are available for the MMIC design. The process also offers air bridges for metal line crossover and via holes for of the technology is 25 grounding. The cutoff frequency GHz. The associated gain in CW of an 8 40- m device biased 8 V and matched at 33 kA cm current density with for maximum output power at 10 GHz is 10.4 dB at 1-dB gain compression. The technology is an upgrade of a process already evaluated and used for space applications [4], and it was also the one adopted for the HPA of the first generation of Cosmo SkyMed. It is worth noting that GaAs-based HBT technologies are widely used for power amplifiers in mobile phones, operating with low collector bias voltage (under 5 V) at - and -bands [5], [6], but they are usually not adopted with higher collector bias levels and at higher frequency bands. As a matter of fact, the main problem associated with HBT technologies is the thermal management of high-power density devices: indeed, because of the positive temperature feedback of bipolars, HBT devices suffer from current collapse [7] or

T

Manuscript received September 30, 2011; revised February 09, 2012; accepted February 14, 2012. Date of publication April 03, 2012; date of current version May 25, 2012. This work was supported by the Italian Space Agency (ASI) under Project “Promix—Design and implementation of MMIC chip-set for X-band T/R modules for second generation SAR” ASI Contract N. 1/042/08/0. C. Florian is with the Department of Electronics, Computer Sciences and Systems (DEIS), University of Bologna, Bologna 40136, Italy (e-mail: [email protected]). R. P. Paganelli is with the National Research Council, Institute of Electronics, Computer and Telecommunication Engineering (CNR-IEIIT), Bologna 40136, Italy (e-mail: [email protected]). J. A. Lonac was with MEC srl, 40127 Bologna, Italy. He is now with Huawei, 20152 Milan, Italy (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2012.2189234

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second breakdown phenomena [8], due to thermal instabilities in multifinger power transistors. For this reason, high-power density biasing regions associated with high collector bias voltages are particularly critical and usually avoided. Targeting high-power density operation, the selected process is designed to operate at a collector bias voltage up to 9 V, exploiting the negative feedback effect of a ballast resistor integrated in a layer within the device emitter fingers. The combination of ballast resistors and a thick gold structure (called thermal drain), which connects the emitter fingers, homogeneously distributing the heat between them, makes the devices thermally stable and capable of working at high bias voltage 9 V and current density, up to 33 kA cm [9]. It is also very important to remark that this goal is accomplished without sensibly degrading the high-frequency gain performance, thus making the technology suitable for the -band. Moreover, two different types of transistor topologies can be used [9], [10]: in addition to the standard multifinger topology, the bicell structure is also available, which, combining two emitter fingers sharing one central base stripe, has demonstrated improvements both in terms of electrical parasitics and achievable power densities, featuring also improved thermal behavior [11]. The bicell structure was chosen for the design of the final stage of the HPA to maximize output power, while maintaining the device temperature under the limit required by Space applications.

Fig. 1. Load-pull power contours at 9.6 GHz (CW) for a 10 110 mA and 7.2 V. device biased at

50

m HBT

III. MMIC AMPLIFIER DESIGN AND PERFORMANCE The designs of the MMIC amplifiers were carried out exploiting the foundry design kits for both active and passive components. Moreover, electromagnetic simulations of many sections of the matching networks were performed as well. Finally, , -parameter and large-signal load-pull measurements (in CW operation) of some HBT samples were carried out and exploited in the design, in addition to the electrical model of the design kit. Device -parameters were adopted in particular for the smallsignal stability analyses and for the amplifier input-matching design, whereas load-pull data were used for the choice of the device optimum loading condition to reach the best performances in terms of power and efficiency. As an example, in Fig. 1 the load-pull contours for a parallel HBT 10 50 m device at 9.6 GHz are shown. The load-pull system is capable of controlling the impedance at the fundamental frequency, while the secondand third-harmonic impedances are only monitored during the measurement. Hence, the synthesis of the harmonic impedances for the optimization of the HPA performances were essentially based on simulation data. The device is biased in class AB, with 110 mA 11 kA cm and 7.2 V. As can be seen in Fig. 1, the maximum output power for this device at 1-dB compression point is about 29.5 dBm: this value corresponds to 1.8-W/mm power density. Definitely higher power densities (about 3 W/mm) are available from this process, if biased at maximum ratings: nevertheless, the bias points of the HBT devices in the MMICs were chosen at levels of power densities to be compliant with Space de-rating constraints for collector–emitter breakdown voltage, current density, and operative channel temperature.

Fig. 2. Structure of the stabilizing and prematching network and factor and available gain, before and after the stabilization for the 4 30 m HBT cell.

A. Driver Amplifiers Two driver amplifiers have been designed and implemented: both amplifiers feature two gain stages, exploiting a 4 30 m device in the first one. The first amplifier (Driver1) was designed with a single device m output stage, whereas the second one (Driver2) uses two 8 40 m cells for its output section. The second solution was selected to reach slightly higher output power (higher total device periphery) and higher gain (shorter emitter fingers), targeting slightly higher margins with respect to specification goals at the expense of higher supply power. A conservative design choice was assumed to make every HBT device unconditionally stable from 300 MHz upward by using a parallel RC network in series with the base as shown in Fig. 2 (Rs//Cs). Before the stabilization network, a shunt metal–insulator–metal (MIM) capacitor (Cp in Fig. 2) is connected directly at the device base to perform an impedance prematching, leading the device input impedance into lower Q regions of the Smith chart, thus maximizing the network bandwidth. In Fig. 2, the stability factor and maximum available

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Fig. 3. Schematic and picture of the MMIC driver1 amplifier: dimensions are 3.4 1.8 mm.

gain of the 4 30 m HBT before and after the insertion of the stabilizing and prematching network are shown. The device stabilization is obtained by trading off about 2 dB of available gain in the design bandwidth. Matching networks of both MMICs were implemented with a combination of lumped - sections and distributed microstrip structures, which are clearly described in the schematics of Figs. 3 and 4. Those networks are designed to implement impedance transformations with limited Q to achieve the required matching in the largest achievable frequency band. As far as regarding Driver2, the two cells of the final stage are combined both at the base and collector sections by a microstrip T-junction (indicated as “Splitter” and “Combiner,” respectively, in the schematic of Driver2 in Fig. 4): the connection is made at the input after the base stabilization (RS2//CS2) and prematching (CP2) networks and at the output after L2-C5-Line3 matching sections. The integrated bias networks use high value series spiral inductors 4 nH 3.5 nH 3 nH and large shunt MIM capacitors 10 pF 10 pF 12 pF for RF decoupling. The only exception to this topology is the collector bias network of Driver2’s second stage, which exploits a high-impedance microstrip line (followed by a shunt capacitor CBC2), which provides the collector current symmetrically to both the HBTs. In the base bias networks, an integrated series resistor is included (RB1 and RB2), which is also suitably designed to obtain (in cooperation with the integrated emitter ballast resistor) the stabilization of the device bias point in the specified temperature variation range. Moreover, the choice of the base bias resistor is important also for the high-frequency gain compression characteristic of the device, hence its value is optimized even with respect to this parameter.

Fig. 4. Schematic and picture of the MMIC driver2 amplifier: dimensions are 3.4 1.8 mm.

TABLE I DRIVER AMPLIFIER BIAS CONDITIONS

All of the devices are biased in class AB. The bias values for the amplifiers working at small signal are shown in Table I. Since the T/R module application is in pulsed mode, currents and power consumption shown in the table have to be considered as worst case values, referring to 100% duty cycle condition (i.e., CW operation), whereas a typical maximum duty cycle is about 30%. Furthermore, improved gain and power performance are obtained in pulsed operation, as the operating junction temperature is much lower. All of the driver circuits’ -parameter have been measured on wafer (32 chips per circuit) at de-rated bias conditions in order to avoid problems related to power dissipation. The performance dispersion was very low: as an example the S21 parameter variation was within 0.5 dB. This indicated good process quality and low process dispersion. Three MMIC for every circuit were selected from the wafer an were mounted on a test jig for full characterization: their performances were extremely close: hence, for the sake of clarity, in the following figures the measured data for a single amplifier for each type will be shown. Measured CW small-signal data in Fig. 5 indicate very good performance for both transmission and reflection parameters:

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Fig. 5. S parameter of the driver amplifiers in CW. Base plate temperature 40 C. Fig. 7. Measured CW performance and simulations of the drivers at 1-dB compression point.

TABLE II JUNCTION TEMPERATURE AT

Fig. 6. Large-signal performance in CW of the two driver amplifiers at 9.6 GHz 40 C. varying the available input power. Base plate temperature

the design specifications ( 18 dB and 10 dB) were fulfilled in about 2-GHz bandwidth around 9.6 GHz. The results are also in very good agreement with simulations performed exploiting design kit models and EM simulations for

50 C

the passive structures and measured -parameter data for the active devices. The limited discrepancies in the resonance frequencies of reflection parameters are compatible with the uncertainty of the length and shape of the input and output bonding wires, that at this stage were implemented with a manual-controlled bonding machine. Since the radar application does not require amplitude linearity, the performances of the drivers at nonlinear large-signal condition are of interest: working in nonlinear regime the drivers exhibit higher PAE, which enhances the PAE of the entire lineup. In Fig. 6, swept-power CW performance (output power, PAE, and gain) of the two amplifiers are shown at 9.6 GHz: the nonlinear characteristics exhibit the expected behavior for class-AB amplifiers. At 1-dB compression point, both amplifiers have a

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Fig. 8. Schematic of one half of the HPA (the other half is symmetric).

PAE higher than 50%, transducer gain over 20 dB and output power of 28.5 dBm (Driver1) and 29.7 dBm (Driver2), respectively. At higher gain compression Driver2 delivers more than 1-W output power with 57% PAE. Performances at P1 dB along the bandwidth are shown in Fig. 7 along with simulations data: CW output power exceeds 28 dBm and about 29 dBm, respectively, with very good PAE performance. In pulsed-mode operation (drain-pulsed, 100- s pulse length with 35% duty cycle), the measured output power is typically 0.6 dB higher with gain increasing of about 1 dB. In Fig. 7, simulation results are shown as well: the nonlinear HBT models of the foundry design kits were reasonably accurate for the prediction of output power and large-signal gain, while the PAE was clearly underestimated. The higher error in the prediction of PAE is generally expected, as it is an indirect parameter: in this case, it was observed that the simulation error was due to a slight underestimation of output power and gain, but mainly to an overestimation of the collector current. In this regard, it is fair to notice that, in the drivers’ designs, the selected bias points and loading impedances for the HBTs were quite different from the conditions for maximum output power about which the nonlinear HBT models were identified and optimized. In order to be compliant with space qualification rules, besides maximum voltages and current densities in active and passive structures, the device junction temperature was considered during the design. The calculation of the peak junction temperature of HBT devices in operating conditions was carried out exploiting the thermal model embedded in the nonlinear foundry models: this model is described in [12]. Using this model and some additional information provided by the foundry manual, it was also possible to estimate the variation of the peak junction temperature for different pulse length and duty cycles. In Table II, the simulated junction temperatures of the HBT devices are listed at small-signal (SS) and P1 dB (LS) operating regimes, when the base plate temperature is set

Fig. 9. Photograph of the MMIC HPA: 5.5

4.5 mm.

at 50 C, which is the maximum specified operating temperature of the T/R module. B. 12-W MMIC HPA The two-stage HPA was designed exploiting eight 8 2 60 m bi-cell devices in the final stage and four standard 8 40 m devices in the first one. The schematic of the MMIC is shown in Fig. 8: one half of the circuit is described, since the other half is perfectly symmetric. The photograph of the MMIC is displayed in Fig. 9: physical dimensions are 5.5 4.5 mm. The stabilization (Rs1//Cs1 and Rs2//Cs2) and prematching (Cp1 and Cp2) networks of every device were carried out in a similar manner and with the same tradeoffs described for the driver amplifiers. The main difference in this case is due to the limited available gain of the large bi-cell devices of the final stage: since

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at 9.5 GHz their available gain is about 12 dB, to preserve the PAE of the HPA, the base R-C stabilization network (Rs2//Cs2) was designed to minimize its loss at about 0.7 dB, at the expense of a limited stabilization effect, with respect to the networks designed for the smaller devices of the first stage and of the driver amplifiers. For this reason, the final stage devices of the HPA were not unconditionally stable, and more care was adopted in the synthesis of their matching networks to avoid any stability issues. Moreover, the Rs2//Cs2 network was also dimensioned to minimize the device gain at half the operative frequency, in order to avoid the startup of unwanted subharmonic oscillations, when operating at high compression levels [13]–[15]. Integrated base bias networks (LB1-CB and LB2-CB) adopt analog lumped components and topologies implemented in the driver amplifiers. The collector bias networks of the first stage are implemented (starting from the dc pad) with a grounded MIM capacitor CBC, followed by a microstrip line section (line1 in Fig. 8), whose length is designed to synthesize a purely reactive impedance at its insertion point in the inter-stage network (section B): in this way, nearly no active power is fed towards the bias network. The bias line itself is not necessarily a high impedance for the RF signal, and, indeed, it typically has a role in the network impedance transformation. Therefore, great care must be taken to avoid unbalanced operation on the active devices of the same stage. The synthesis of the inter-stage matching network (ISMN) between the first and final stages is the most challenging part of the design: this network operates the transformation from the input impedance of the final stage devices to the optimal load impedance for the first stage ones. In Fig. 10, is shown in the frequency band of interest with 100-MHz steps along with the target zone for . are the impedances of the final stage devices at their large-signal operative point (about 2-dB gain compression), hence, they are calculated by means of a large-signal harmonic balance analysis as the ratio of input voltage and current at the fundamental frequency. As they are large periphery bipolar devices, is very small, with the real part of the order of 0.45 . As an example, at 9.3 GHz, . For this reason, the Smith chart of Fig. 10 is normalized at 5 , otherwise the differences between at different frequencies would not be appreciable. The loading impedance of the first stage devices cannot be chosen only for gain maximization as for typical driver stages, since the maximum power is also delivered to the final stage to properly drive it and the device operating temperature (i.e., efficiency) are design targets which do not come for free. Any impedance within the target zone of Fig. 10 meets the design targets. It is worth noticing that the central point of the target zone corresponds to 10 , meaning that the average impedance transformation ratio of the ISMN is about 20, which is difficult to obtain in a large bandwidth, while maintaining low network losses. Furthermore (see Fig. 10), has a Q between 3–5, which is quite high and makes it difficult to obtain large bandwidth. All of these issues make the synthesis of the ISMN very challenging, so that this part of the circuit is primarily responsible for the bandwidth limitations. As can be seen in Fig. 9, as a consequence to the aforementioned characteristics, the ISMN occupies a large area of the

Fig. 10. Impedance transformation between the final-stage device input and the first-stage device optimum operated by the ISMN, impedance displayed in a 5- normalized Smith chart.

MMIC: to broaden the bandwidth, four matching sections have been designed, each one built with a series microstrip line and a shunt capacitor (from C1 to C4 in Fig. 8). The microstrip line sections have been chosen rather than spiral inductors to minimize the network losses, which are thus limited to about 1.5 dB. As far as regarding the final stage, its eight bi-cell devices have to be physically “packed” as close as possible to minimize the chip vertical dimension: to this aim, adjacent devices share two of their eight via holes (four per side) that connect their emitter to the ground plane under the chip. With this solution, the devices of the output stage are merged in a single power bar. From an electrical point of view, this configuration implies that the emitter series inductance of shared vias is virtually doubled, slightly modifying the device current paths. These vias play also an important role in the heat removal process because they provide the path from the hot top thermal-drain and the cold back-side of the chip [9]; therefore, this “sharing” solution has the unhelpful effect of slightly increasing the overall device thermal resistance, but it also has the beneficial effect of thermally coupling the devices in the power bar, almost uniformly distributing the temperature between them and then decreasing the risk of thermal instabilities. At the power bar output, all the device collectors are connected directly to a microstrip line, following the bus-bar approach [16], [17]: the bus-bar (highlighted in red in the schematic of Fig. 8) is designed to implement at the device insertion points a uniform voltage section for dc and RF, enabling the power combining of all the device output signals simultaneously in phase at the extracting sections (S1 and S2 in Fig. 8), where the power is drawn from the bus bar by a conventional microstrip tree structure. The main design effort is to guarantee in-phase power combining at the bus-bar in the larger possible bandwidth, while loading all of the HBT with the same identical impedance: if these requirements are satisfied, the power coupling achieves the maximum efficiency, limited only by the microstrip lines-series loss. Moreover, also the second and third harmonics of the device loading impedance have been accurately synthesized with the bus-bar in order to evenly shape the HBT dynamic load lines of every cell with the target of enhancing the efficiency without sensibly degrading the maximum output power condition. In Fig. 11, the simulated optimum loading impedances at 9.3 GHz are shown:

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Fig. 11. Simulated typical optimum loading impedances of the HBT 8 2 60 m device of the HPA final stage. Fig. 12. Final-stage HBT devices’ load lines at 2.5-dB gain compression.

at fundamental (which is the same obtained with load-pull measurement), while the second- and third-harmonic impedances can be chosen within the highlighted zones of Fig. 11, possibly purely reactive and mainly very similar (between different devices of the bar). The design parameters of the bus-bar are basically the lengths of the connecting taps along the line (highlighted in green in the schematic of Fig. 8) and the values of the capacitors shunted to ground (CX), which are placed between each pair of device along the bar (see Fig. 8) at symmetrical sections: for a proper low-loss power combining in the bar, it is important that, at these sections, no RF current is fed along the bus-bar between adjacent device pairs [16]. In our design, this condition of symmetry is observed at the upper and lower edges of the bus-bar (section A in Fig. 8): hence, at those points, the bias is inserted without the need for high impedance lines (see Fig. 8), with obvious advantages in terms of space saving and losses minimization. After the bus-bar, the output matching network implements a conventional two-step tree combiner exploiting microstrip lines and lumped MIM capacitors (C5, C6, and C7) for impedance transformations. The simulated load lines of the intrinsic currents obtained for four of the eight final-stage devices with the design are shown in Fig. 12: the load lines are almost identical due to the symmetry of the bus-bar, which is designed to load the devices with almost identical impedances up to the third harmonic (the load lines of the other four devices are not shown, since they are perfectly identical due to the symmetry of the HPA layout). Moreover ,the load lines are shaped to avoid breakdown and second breakdown regions. Table III lists the quiescent bias conditions of the HPA and its operative working point when driven in large-signal operation (about 2.5-dB gain compression) by the input signal. The listed values refer to CW working conditions (100% duty cycle) and must be accordingly scaled when the device is operated in pulsed mode. The auto-polarization of the HPA second stage in operative working conditions ( from 1.91 to 2.94 A, meaning Jc from 12.3 to 18.9 kA cm ) is substantial, due to the choice of the HPA quiescent point in deep class AB to enhance efficiency. Even for the HPA, the peak junction temperature of active devices was evaluated: in Table IV, the junction temperature of both the first- and second-stage devices are listed at various operating conditions, which range from dc to fairly short pulsewidth and duty cycle. In CW, the second-stage junction

TABLE III HPA BIAS CONDTIONS AND OPERATIVE WORKING POINT

TABLE IV JUNCTION TEMPERATURE AT

50 C

temperature would exceed the maximum specified temperature, which was fixed at 120 C for this process operating within Space-qualification constrains, whereas in pulsed operation all of the temperatures are well below the limit. Also, for all of the HPA circuits (30 chips) ,S parameters at a de-rated bias point have been measured on wafer, showing very limited performance variation. This was again an indication of the process quality and of low dispersion. Referring to this data, three HPA samples have been selected from the wafer to be measured in large signal operating conditions. Also, at large signal, the performance variations were negligible, suggesting not only low process dispersion, but also robustness of the design. Since the performance differences between the three samples were negligible, in the following, the measured data for a single HPA will be shown. In order to manage the HPA biasing, RF accesses, and power dissipation, the MMIC was mounted in a suitably designed test jig, as shown in Fig. 13. The jig features low-frequency bias networks implemented with SMD components on FR4 substrate, a metal carrier, 50- microstrip lines on a high-frequency laminate for the MMIC RF accesses, and connectors for the coaxial-to-microstrip transitions. The MMIC is connected to the external structures by means of bonding wires (25- m-diameter gold wire, wedge bonding). As can be seen in Fig. 13, the carrier is screwed to a Peltier cell in order to control the MMIC backside temperature during the characterization.

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Fig. 13. Test jig for the HPA characterization: the jig is bolted to a Peltier cell to control the backside temperature during characterization. Fig. 15. Performance of the HPA in pulsed-mode operation (50- s RF pulse width, 20% duty cycle) at 2.5-dB gain compression and 40 C base plate temperature.

Fig. 14. Measured HPA final-stage current in collector-pulsed condition with and without RF signal applied. Bias pulse length 54 s, RF pulse length 50 s.

Indeed, a thermistor is applied to the metal carrier very near to the MMIC to monitor the temperature. The HPA has been characterized in pulsed-mode operation with various pulse lengths and duty cycles. A large-bandwidth (50 MHz) current probe [18] was used in the setup to measure the amplifier final-stage current in the time domain. Measurement were made with the HPA base bias fixed at the nominal value, while the collector voltage is pulsed between 0 and 7.2 V. Once the bias pulse has been applied to the HPA, after a wait of 2 s for the bias to settle, the RF pulse is applied at the HPA input. By monitoring the collector current in the time domain, it is possible to observe the substantial difference between the bias pulsed working point and the actual large-signal operative working point of the amplifier, when driven by the RF signal at about 2.5-dB gain compression. In Fig. 14, the measured collector current of the HPA final stage is shown with and without the RF signal applied: an increment of about 54% of the dc current with respect to the bias value is observed, due to auto-polarization of the amplifier by the RF signal. Fig. 15 shows the HPA output power and PAE along the bandwidth, while operating at constant gain compression level of about 2.5 dB. The operative associated gain is about 18.5 dB (small-signal gain about 21 dB along the bandwidth). The RF

Fig. 16. Measured performance of the HPA at 9.3 GHz in pulsed-mode operation (50- s RF pulse width, 20% duty cycle) at 40 C base plate temperature.

pulse length is 50 s with 20% duty cycle, which are typical parameters for -band SAR systems. In Fig. 15, the simulated performance are shown with the dashed lines. A frequency shift of about 200 MHz (2% of the central frequency) can be observed. The measured output power is higher than simulated (up to 0.9-dB difference), mainly because the simulation data represent CW operative regime, whereas pulsed mode operation is beneficial for the HPA performance, as will be also discussed in the following. For the same reason, the simulated gain is about 2 dB lower that the measured one. As a consequence, the PAE is typically underestimated as well. Peak performance at the center of the bandwidth are 40.9 dBm (12.3 W) and . This output power corresponds to 1.6 W/mm of device periphery at circuit level. The output power exceeds 40 dBm (1.3 W/mm) along 1-GHz bandwidth. The PAE is over 39% within 500-MHz bandwidth, while it tops 33% for 1-GHz bandwidth. It has been observed that the lower and points between 9.4 and 9.6 GHz are due to the inability of the driver stage to properly drive the final one. If driven with higher input power, the HPA is capable of delivering more than 40.5 dBm at those frequencies, despite further lowering the PAE. Indeed, the device power bar with a bus-bar combining network has proved

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COMPARISON OF THE HBT HPA WITH

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TABLE V -BAND HPA MMIC IN GAAS PHEMT TECHNOLOGY

to be broadband, whereas, as mentioned before, the bandwidth limitation comes from the difficulty to synthesize a broadband inter-stage network. Because of the large impedance transformation required, the high-Q input characteristic of HBT devices and the nonnegligible input impedance variation along 10% bandwidth (see Fig. 10). In Fig. 16, the HPA measured performance at 9.3 GHz are shown as a function of the amplifier input power. Higher power densities (2.85 W/mm) were obtained with a very similar HBT process in [10]: nevertheless, it must be taken into account that in that case the same space application de-rating constraints were not applied, hence the devices are biased at higher voltage ( 10 V instead of 7.2 V) and operate at higher current levels ( 33 kA cm instead of 18.9 kA cm ). Furthermore, in [10], the reported performance are obtained with pulse length of 1.6 s and 10% duty cycle, which are not useful for the SAR application object of our activity. In [19], the same similar process was exploited obtaining comparable output power and PAE performance in a larger bandwidth; nonetheless, even in this case the collector bias is sensibly higher 9 V and the operative current density is bigger 26 kA cm . It must be noted that 9 V is a value relatively unsafe with respect to secondary breakdown failure. Indeed, according to Fig. 12, the second breakdown seems very well fixed at the device level, but, dealing with a power stage made of several devices whose thermal coupling is not that predictable, the risk of odd thermal instabilities is still present and can be effectively avoided only by reducing the collector bias voltage. It is now interesting to compare the HBT HPA performance with GaAs pHEMT technologies that represent the more adopted solution for this kind of application. In Table V, the performance of several state-of-the-art GaAs pHEMT -band HPAs mainly designed for radar applications are listed. It can be observed that the performance of the HPA designed in this work is competitive with the pHEMT HPAs in the literature. The HBT technology has an advantage in terms of power density per mm of active device periphery due to the higher current density, while GaAs pHEMT circuits feature higher bandwidth due to higher cut off frequency. It still should be observed that a detailed and fair comparison between different HPAs in the literature is very difficult, because every design is carried out exploiting the devices with different

Fig. 17. Measured

and PAE at 9.3 GHz with different pulse regimes.

levels of margin with respect to maximum ratings, hence different levels of reliability should be expected from different designs, and this is a crucial issue when dealing with a Space application. Furthermore, the performance should be compared at the same temperature, pulse length, and duty cycle. The HPA behavior at different operating regimes was also characterized. In Fig. 17, the HPA performance at 9.3 GHz are shown at various pulse length and duty cycle conditions with the base plate held constant at 40 C. When going from CW (100% duty cycle) to 50 s (20% duty cycle) a clear advantage for power, gain, and PAE performance can be appreciated; these advantages tend to saturate for lower pulse lengths. This behavior related to the pulse length and duty cycle, which is very important for SAR operation, has been further investigated by analyzing the measurement of the HPA current and bias voltage in the time domain during the pulse. Different phenomena take part in the performance degradation, when increasing pulse length and duty cycle: in Fig. 18, the final stage collector current and voltage are displayed for a 100- s pulse. The graph is a magnification of the upper part of the waveforms in order to appreciate the drop of both current and voltage. The current drop along the pulse is a thermal phenomenon due to the device heating: letting alone the initial ringing of the current, due to external stabilization shunt capacitors in the collector bias line ( in Fig. 19), the current drops from approximately 2.87 to 2.78 A, hence 3%. Regarding the voltage, it drops from 7.2 to 6.97

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Fig. 19. Simplified schematic of the pulsed bias supply setup.

Fig. 18. Measured collector current and voltage drops along a 100- s pulse.

V, which is also 3%. The voltage drop depends on the characteristic of the equivalent capacitor implemented in the pulsed bias circuit (see Fig. 19) to sustain the collector bias voltage during the pulse. In Fig. 19, a simplified schematic of a traditional pulsed bias circuit for the HPA collector pulsing is outlined. This schematic represents both the HPA characterization setup and an actual HPA bias circuit in an SAR antenna. In the T/R module section of a SAR antenna, typically a bank of electrolytic capacitors is placed as close as possible to the HPAs in order to guarantee the lower possible voltage drop at the HPA drain or collector bias pads during the pulse: indeed, during the pulse, the collector current ( in Fig. 19) is drained almost only from the capacitor bank close to the HPA. Therefore, sustains the collector voltage almost alone, since the main bias unit of the satellite cannot supply the impulsive current, because of the nonnegligible parasitic effects ( and ) of the long supply bus lines. The role of the main supply unit is to recharge the capacitors during the off-state time interval. Ideally, the bank of capacitors should be sufficiently large to avoid voltage drop during the pulse, but obvious limitations in terms of capacitor quality factor [equivalent series resistance (ESR)], capacitance value, inductive series parasitics, and a maximum number of capacitors sets unavoidable limitations; hence, a certain degree of voltage drop has to be accepted, and it is one of the major causes of output phase deviation during the transmitted pulse (clearly a problem for SAR application). In the measurement setup adopted for the characterization (Fig. 19), the pulsed bias circuit is very similar to the one implemented in the actual SAR antenna [2]: the selected capacitors feature very low ESR, the total equivalent capacitance for the HPA collector bias is 1200 F, and the parasitic inductance and resistance of the connection between the bank of capacitors and the MMIC are very limited, due to very short cabling (5 cm). It is fair to notice that the very high current density of HBT technology is a drawback with respect to this phenomenon. Regarding this matter, emerging GaN technologies, which offer high-power density by working with very high drain voltages rather than high current densities, have a clear advantage. The current and voltage drop along the pulse are two contributions to the performance degradation as the pulsewidth increases: in addition to them the main degradation mechanism is the reduction of the average HPA current, when the duty cycle increases.

Fig. 20. Final-stage collector currents measured for different pulse lengths.

The instantaneousfinalstagecurrentofthe HPAfordifferentcombination of pulse length and duty cycle are displayed in Fig. 20. All of the bias conditions and the RF input power level are the same for the four different measurements: furthermore also the base plate temperature is kept constant at 40 C. It is very clear that larger duty cycles have less time for the HBT devices to cool down during the “off-state.” Hence, the devices work in a thermal regime characterized by an higher mean junction temperature, which results in a lower current during the pulse. The thermal state at which the devices operate for a particular combination of pulse length and duty cycle depends on the overall thermal impedance of the assembly, and then not only on the thermal impedance of the single HBT device. From Fig. 20, it can be appreciated that the mean collector current of the HPA final stage with a pulse of 200 s at 70% duty cycle (a condition very similar to CW) is 2.49 A, while it increases to 2.96 A for a pulse of 50 s at 20% duty cycle: the increase of collector current is 0.47 A, which is a considerable . Waveforms of Fig. 20 also confirm the tendency of this effect to saturate, as observed from output power measurement of Fig. 17: nonetheless, for this particular case, the extremely limited advantage observed in output power (Fig. 17) when switching from a 50- s–20% pulse to a 25- s–10% one is also due to the fact that, for the shorter pulse, the effect of the initial current ringing becomes important and clearly detrimental in that case. This is also an important indication of the importance of the pulsed bias supply circuit for the T/R modules: indeed

FLORIAN et al.: 12-W

-BAND MMIC HPA AND DRIVER AMPLIFIERS IN INGAP-GAAS HBT TECHNOLOGY FOR SPACE SAR T/R MODULES

the current ringing can be highly limited by exploiting some well-inserted lossy elements, by optimizing the value and characteristic of the stabilization shunt capacitors ( in Fig. 19) in the collector bias line and by shaping the rise of the pulse. IV. CONCLUSION The design and characterization of two MMIC driver amplifiers and an MMIC HPA exploiting an InGaP-GaAs HBT technology at -band for SAR T/R module space application were described. The circuit design was performed within Space de-rating constrains, taking into account electrical and thermal limitation which affect reliability. Following these guidelines, the achieved performances can represent an assessment of this technology regarding its exploitation for space SAR systems. If adopted in a T/R module which combines two HPA to transmit simultaneously in the two polarizations [2], the MMICs can implement a power lineup with about 40-dB gain, more than 10-W output power and PAE exceeding 33% in 1-GHz bandwidth. Waiting for commercially available GaN HEMT processes, with sufficient reliability characteristics and heritage for space programs (in addition to already excellent maximum performance as, for example, in [30] and [31]), this InGaP-GaAs HBT technology can be considered attractive for these applications, having shown better or comparable performance than GaAs pHEMT processes. ACKNOWLEDGMENT The authors would like to thank Prof. V. Monaco, manager of the project “Promix,” and Prof. A. Santarelli, person in charge in this project for the University of Bologna. REFERENCES [1] F. Caltagirone, G. De Luca, F. Covello, G. Marano, G. Angino, and M. Piemontese, “Status, results, potentiality and evolution of COSMOSkyMed, the Italian earth observation constellation for risk management and security,” in Proc. IEEE IGARSS Int. Geosci. Remote Sens. Symp., 2010, pp. 4393–4396. [2] P. Capece, L. Borgarelli, M. Di Lazzaro, U. Di Marcantonio, and A. Torre, “COSMO SkyMed active phased array SAR instrument,” in Proc. IEEE Radar Conf., 2008, pp. 1–4. [3] M. Di Lazzaro et al., “COSMO-SkyMed: The dual-use component of a Geospatial system for environment and security,” in Proc. IEEE Aerospace Conf., 2008, pp. 1–10. [4] P. Auxemery, G. Pataut, H. Blanck, and W. Doser, “Power HBT reliability for space applications,” in Proc. Gallium Arsenide Application Symp., Munich, Germany, 2003, pp. 287–290. [5] Y. Yang et al., “A super ruggedness InGaP/GaAs HBT for GSM power amplifiers,” in Proc. GaAs ManTech Conf., 2005, Paper n.3, Sec. 12. [6] R. Hattori et al., “Manufacturing technology of InGaP HBT power amplifiers for cellular phone applications,” in Proc. GaAs ManTech Conf., 2002, Paper n.1, Sec. 12. [7] W. Liu, S. Nelson, D. G. Hill, and A. Khatibzadeh, “Current gain collapse in microwave multifinger heterojunction bipolar transistors operated at very high power densities,” IEEE Trans. Electron Devices, vol. 40, no. 11, pp. 1917–1927, Nov. 1993. [8] P. P. Wang, “Thermal instability and secondary breakdown in power transistors,” IEEE Trans. Aerosp. Electron. Syst., vol. AES-7, no. 6, pp. 1195–1200, Dec. 1971. [9] “X-band GaInP HBT 10 W high power amplifier including on-chip bias control circuit,” in IEEE MTT-S Int. Microw. Symp. Dig., 2003, vol. 2, pp. 855–858. [10] S. Piotrowicz et al., “Ultra compact X-Band GaInP/GaAs HBT MMIC amplifiers: 11 W, 42% of PAE on 13 mm and 8.7 W, 38% of PAE on 9 mm ,” in IEEE MTT-S Int. Microw. Symp. Dig., 2006, pp. 1867–1870.

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[11] D. Floriot, E. Chartier, N. Caillas, S. Delage, J. C. Jacquet, and S. Piotrowicz, “InGaP power HBTs: Basic power cells for high power transistors,” in Proc. Gallium Arsenide Application Symp., Milan, Italy, 2002, pp. 1–4. [12] T. Peyretaillade, M. Perez, S. Mons, R. Sommet, P. Auxemery, J. C. Lalaurie, and R. Quere, “A pulsed-measurement based electrothermal model of HBT with thermal stability prediction capabilities,” in IEEE MTT-S Int. Microw. Symp. Dig., 1997, vol. 3, pp. 1515–1518. [13] A. Anakabe, J.-M. Collantes, J. Portilla, J. Jugo, A. Mallet, L. Lapierre, and J.-P. Fraysse, “Analysis and elimination of parametric oscillations in monolithic power amplifiers,” in IEEE MTT-S Int. Microw. Symp. Dig., 2002, vol. 3, pp. 2181–2184. [14] D. Teeter, A. Platzker, and R. Bourque, “A compact network for eliminating parametric oscillations in high power MMIC amplifiers,” in IEEE MTT-S Int. Microw. Symp. Dig., 1999, vol. 3, pp. 967–970. [15] A. P. de Hek, A. de Boer, and T. Svensson, “C-band 10-Watt HBT high-power amplifier with 50% PAE,” in Proc. Gallium Arsenide Applications Symp., London, U.K., 2001. [16] S. P. Marsh, D. K. Y. Lau, R. Sloan, and L. E. Davis, “Design and analysis of an X-band MMIC “bus-bar” power combiner,” in Proc. IEEE EDMO Symp., 1999, pp. 164–169. [17] S. P. Marsh, “MMIC power splitting and combining techniques,” in Proc. Inst. Elect. Eng. Tutorial Coll. Design RFIC’s MMIC’s, London, U.K., 1997, pp. 6/1–6/7. [18] “Agilent 1147A 50 MHz/15A AC/DC Current Probe,” Agilent [Online]. Available: http://www.home.agilent.com/ [19] A. M. Couturier, S. Heckmann, V. Serru, T. Huet, P. Chaumas, J. J. Fontecave, M. Camiade, J. P. Viaud, and S. Piotrowicz, “A robust 11 W high efficiency -band GaInP HBT amplifier,” in IEEE MTT-S Int. Microw. Symp. Dig., 2007, pp. 813–816. [20] T. Huet, J. Gruenenpuett, Z. Ouarch, D. Bouw, V. Serru, M. Camiade, C. Chang, and P. Chaumas, “A 8 W high efficiency X-band power pHEMT amplifier,” in Proc. 38th Eur. Microw. Conf., 2008, pp. 289–292. [21] C.-K. Chu, H.-K. Huang, H.-Z. Liu, C.-H. Lin, C.-H. Chang, C.-L. Wu, C.-S. Chang, and Y.-H. Wang, “An X-band high-power and high-PAE PHEMT MMIC power amplifier for pulse and CW operation,” IEEE Microw. Wireless Compon. Lett., vol. 18, no. 10, pp. 707–709, Oct. 2008. [22] C. Costrini, M. Calori, C. Lanzieri, and C. Proietti, “A 25% bandwidth 8 W X-band HPA for radar applications,” in Proc. Eur. Microw. Integr. Circuit Conf., 2007, pp. 151–153. [23] A. P. de Hek, G. van der Bent, M. van Wanum, and F. E. van Vliet, “A cost-effective 10 Watt X-band high power amplifier and 1 Watt driver amplifier chip-set,” in Proc. Eur. Gallium Arsenide and Other Semiconductor Application Symp., 2005, pp. 37–40. [24] R. Wang, M. Cole, L. D. Hou, P. Chu, C. D. Chang, T. A. Midford, and T. Cisco, “A 55% efficiency 5 W PHEMT X-band MMIC high power amplifier,” in IEEE GaAs IC Symp. Dig., 1996, pp. 111–114. [25] A. P. de Hek, P. A. H. Hunneman, M. Demmler, and A. Hülsmann, “A compact broadband high efficient -band 9-watt PHEMT MMIC highpower amplifier for phased array radar applications,” in Proc. Gallium Arsenide Applications Symp., Oct. 1999, pp. 276–280. [26] F. Scappaviva, R. Cignani, C. Florian, G. Vannini, F. Filicori, and M. Feudale, “10 Watt high efficiency GaAs MMIC power amplifier for space applications,” in Proc. 38th Eur. Microw. Conf., 2008, pp. 1429–1432. [27] C. K. Chu, H. K. Huang, H. Z. Liu, C. H. Lin, C. H. Chang, C. L. Wu, C. S. Chang, and Y. H. Wang, “A 9.1–10.7 GHz 10-W, 40-dB gain four-stage PHEMT MMIC power amplifier,” IEEE Microw. Wireless Compon. Lett., vol. 17, no. 2, pp. 151–153, Feb. 2007. [28] W. Bosch, J. G. E. Mayock, M. F. O’Keefe, and J. McMonagle, “Low cost X-band power amplifier MMIC fabricated on a 0.25 m GaAs pHEMT process,” in Proc. IEEE Int. Radar Conf., 2005, pp. 22–26. [29] C. K. Chu, H. K. Huang, H. Z. Liu, R. J. Chiu, C. H. Lin, C. C. Wang, Y. H. Wang, C. C. Hsu, W. Wu, C. L. Wu, and C. S. Chang, “A fully matched 8 W X-band PHEMT MMIC high power amplifier,” in Proc. EEE GaAs IC Symp. Dig., 2004, pp. 137–140. [30] P. Schuh, R. Leberer, H. Sledzik, M. Oppermann, B. Adelseck, H. Brugger, R. Quay, M. Mikulla, and G. Weimann, “Advanced high power amplifier chain for X-band T/R-modules based on GaN MMICs,” in Proc. 1st Eur. Microw. Integr. Circuits Conf., 2006, pp. 241–244. [31] A. Bettidi, A. Cetronio, M. Cicolani, C. Costrini, C. Lanzieri, S. Maccaroni, L. Marescialli, M. Peroni, and P. Romanini, “X-band T/R module in state-of-the-art GaN technology,” in Proc. Eur. Radar Conf., 2009, pp. 258–261.

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Corrado Florian (S’02–M’04) was born in Forlì, Italy, in 1975. He received the M.S. degree in electronic engineering from the University of Ferrara, Ferrara, Italy, in 2000, and the Ph.D. degree in electronic and computer science engineering from the University of Bologna, Bologna, Italy, in 2004. He is currently a Research Associate with the Department of Electronics, Computer Science and Systems, University of Bologna, Bologna, Italy. His main research activity is in the areas of microwave monolithic circuit design, hybrid RF circuit design, nonlinear dynamic system characterization and modeling, and microwave and millimeter-wave device characterization and modeling.

Rudi Paolo Paganelli received the Dr. Eng. degree in electrical engineering and the Ph.D. degree in electrical engineering, computer science and telecommunications from the University of Bologna, Bologna, Italy, in 1998 and 2002, respectively. In 2002, he joined the CNR-IEIIT, Bologna, Italy, as a Research Fellow and, from 2003, he has served as an Assistant Professor of power electronics at the University of Bologna. His research interests include electronic device modeling, microwave circuit design, nonlinear circuits and power electronics.

Julio Andrés Lonac was born in La Plata, Argentina, on July 8, 1976. He received the M.S. degree in electronics from the University of La Plata, Buenos Aires, Argentina, in 2001, and the Ph.D. degree in electronics and computer science from the University of Bologna, Bologna, Italy, in 2005. He was a Research Fellow with the University of Ferrara (2006–2007) and with CoRiTel (a Research Consortium composed of two industrial partners: Ericsson Lab Italy and ITS, and four universities: University of Rome “La Sapienza,” University of Bologna, University of Salerno, and Politecnico di Milano) (2007–2008). He was a MMIC Designer with Microwave Electronics for Communications (MEC) Srl, Bologna, Italy (a spin-off company from the University of Bologna and University of Ferrara) from 2009 to 2010. He is currently a MMIC Designer with Huawei, Milan, Italy. His major field of study concerns the modeling and design of MMICs for civil and military telecommunication and radar applications.

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1

Multiharmonic Volterra Model Dedicated to the Design of Wideband and Highly Efficient GaN Power Amplifiers Wilfried Demenitroux, Christophe Mazière, Emmanuel Gatard, Stéphane Dellier, Michel Campovecchio, and Raymond Quéré, Fellow, IEEE

Abstract—This paper presents a complete validation of the new behavioral model called the multiharmonic Volterra (MHV) model for designing wideband and highly efficient power amplifiers with packaged transistors in computer-aided design (CAD) software. The proposed model topology is based on the principle of the harmonic superposition introduced by the Agilent -parameters, which is combined with the dynamic Volterra theory to give an MHV model that can handle short-term memory effects. The MHV models of 10- and 100-W packaged GaN transistors have been extracted from time-domain load–pull measurements under continuous wave and pulsed modes, respectively. Both MHV models have been implemented into CAD software to design 10and 85-W power amplifiers in - and -bands. Finally, the first power amplifier exhibited mean measured values of 10-W output power and 65% power-added efficiency over 36% bandwidth centered at 2.2 GHz, while the second one exhibited 85-W output power and 65% drain efficiency over 50% bandwidth centered at 1.6 GHz. Index Terms—Behavioral modeling, high efficiency, memory effects, pulsed mode, wideband high power amplifier (HPA).

I. INTRODUCTION

I

MPORTANT characteristics for future RF communication systems are high power-added efficiency, high linearity, and wide bandwidth ( 20%). Today’s base stations consume a lot of power to send complex and wideband modulated signals. Power amplifiers are the main consumers of the base stations’ power because of their low efficiency and the need for cooling. Therefore, developing highly efficient base stations, in order to reduce their overcrowding and their ecologic impact (global warming, earn energy), is necessary. The best known amplifier classes to achieve high efficiency are the class F and class F . The major issue of these oper-

Manuscript received October 01, 2011; revised March 04, 2012; accepted March 07, 2012. This work was supported in part by the Catrene project “PANAMA.” W. Demenitroux is with AMCAD Engineering, 87000 Limoges, France, and also with the XLIM Laboratory, C2S2, 87000 Limoges, France (e-mail: [email protected]). C. Mazière, E. Gatard, and S. Dellier are with AMCAD Engineering, 87000 Limoges, France (e-mail: [email protected]; [email protected]). M. Campovecchio and R. Quéré are with the XLIM Laboratory, C2S2, 87000 Limoges, France (e-mail: [email protected]; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2012.2191305

ating modes is that the control of the impedance by stubs is very narrowband. Thus, a new class, class-J, has been introduced in [1] to reach high-efficiency and wideband performances. One drawback of class-J is that the fundamental and harmonic impedances are indicated in the current source reference plane. In general, computer-aided design (CAD) software is used in the design flow to reduce the cost and optimize the repeatability of manufactured power amplifiers. Nevertheless, extracting a CAD model of a packaged transistor, which is, in general, “phenomenological,” is a very hard task because of the dispersive behavior of the package that hides the other elements of the transistor. In [2], the design of the matching circuit is derived from load–pull data in the packaged plane. It gives good results in drain efficiency and output power, but the design has been developed with a model provided by the device manufacturer. Recently, -parameters have been introduced as the parameters of the poly-harmonic distortion (PHD) nonlinear behavioral model [3], [4]. At first, this approach was applied to 50- devices (amplifier), and then it has been generalized to non-50devices (transistors) in [5]. Finally, an extension of -parameters has been proposed [6], [7] to take into account short-term memory effects for 50- and non-50- devices based on the work initiated in [8]–[11]. The purpose of this paper is to propose a practical and exhaustive validation of the new approach described in [6] and [7] for modeling packaged GaN transistors by designing wideband and highly efficient power amplifiers. II.

VOLTERRA (MHV) MODEL PACKAGED TRANSISTOR

MULTIHARMONIC

FOR

A. Theory of the MHV Model Fig. 1 shows a representation of the MHV model, which considers the nonlinear device (e.g., transistor) where memory effects take place, with the incident and reflected waves and at each port number and their corresponding frequency spectra at fundamental and harmonics. The output wave can be expressed as a sum of the fundamental and harmonic modulated tones described by (1) The general equation of a nonlinear system without memory leads to the mapping of the entire incident waves described in envelope domain, as expressed in (2) as follows:

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Fig. 2. Topology of the MHV model. Fig. 1. Topology of the MHV model.

(2)

Assuming that the main nonlinearity is driven by the incident power wave at the fundamental frequency, the harmonic superposition can be applied to (2) and leads to the following relationship governing the two-port nonlinear system: with (5)

with (3)

In a first assumption, the model is simplified in order to take into account only the memory effects. The kernel is removed from the expression because it describes the lowfrequency memory effects. The expression of the MHV model is then described as

and are described by the However, all the terms level of the incident wave in a static way. By using a discrete description with memory duration ( is the sampling step), (3) becomes

with (4) In order to model (4), the general idea is to apply Volterra series to each terms and of (3)

(6) The topology of the MHV model is described in Fig. 2. This model is only valid for weakly mismatched devices (amplifiers), but the method can be easily generalized to highly mismatched devices (transistors). As this expression is derived from the linearization of (4) around the incident waves , the validity domain of the model is close to used for the model because of the expression of defined as (7) of the simulation is far away It is obvious that if the from , the value of is nonnegligible and the model becomes inaccurate. Therefore, in order to take into account the large mismatch of packaged transistors within 50 , has

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to be swept around the area of interest on the Smith chart. The final expression of the MHV model dedicated to mismatched transistor is described in (8) as follows:

3

described with two separable variables: the residues describe the power dependence, while the poles describe the frequency dependence. The general equation of each and terms is (13) The next step is to make the integration calculus of the timedomain convolution described in (12)

with (8) Finally, it is very important to take into account the dc component that is needed to calculate the power consumption and the efficiency of the device. The currents are described as a function of the incident waves, with a lower bound defined as the dc quiescent bias point

with (14) By applying, respectively, a Fourier transform to (14) and integrating the description function poles and residues, the equation of the model becomes

(9) with

quiescent bias point and

.

B. Numerical Implementation The MHV model has been implemented in commercial software. All the terms and of the model are split into two functions: one describes the dependence on the level, while the other describes the frequency dependence. Gustavsen and Semlyen [12] and Gustavesen [12]–[14] developed an identification of (10) with a very good numeric stability and has implemented this identification in a MATLAB code called “Vector Fitting.” It is a simple description by poles and residues identification

with (15) and

(10) By studying the vector fitting code, possibilities have been found to fix the localization of the stable poles on an entire base of measurements representing a discrete or kernels basis swept in the level and frequency (11) The residues of the vector fitting description have been used to describe the nonlinearity . From (11), a nonlinearity can be expressed as a discrete basis (12)

of

In order to have a continuous function on the variation range , a spline interpolation is used. Thus, the MHV model is

The model is a multiplication of the frequency-domain integral (filtering effect) by the static nonlinearity . This last equation is illustrated in a graphical way in Fig. 3. C. Extraction Methodology To extract the and terms of the MHV model, the approach based on the one developed by Verspecht and Root in [3] is used. In order to illustrate the extraction methodology, the case of a two harmonics ( and ) model is described. The first step is to measure the nonlinear state due to the incident wave at . The corresponding equation to solve for each level of input power is described in (16) as follows: (16)

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Fig. 4. Extraction methodology of the MHV model.

Fig. 3. Numerical implementation of the MHV model.

After that, the influence of each incident wave ( at , and at and ) on each reflected waves ( and at and ) are measured, one by one. Each system is solved by the matrix calculation depicted in (17) as follows: Fig. 5. Experimental setup dedicated to MHV model extraction.

(17) When these steps are finished, one model is extracted. The procedure is applied for each value of chosen in order to cover the area of interest on the Smith chart. Finally, the previous method is applied for several frequencies and enables to capture the high-frequency memory effects. D. Experimental Bench of Extraction There are two ways of extracting the MHV model. The first solution is to use an active method, which adds a tickler tone at the input and the output of the device-under-test (DUT) and sweeps the phase of this tone to extract the influence of each incident wave on the reflected waves, as depicted in Fig. 4. This method is very fast, but it is very difficult to extract the model of very high-power devices as the generation of a tickler tone requires wideband and high power amplifiers (HPAs). To overcome this issue of the active method, a passive approach has been developed. Indeed, as in the case of load–pull, there are two solutions to synthesize load impedances: the active one is based on the reinjection of a signal at the frequency of interest, while the passive one controls the load impedance by mechanical tuners. Therefore, to enable the extraction of MHV model for high-power transistors, the -waves are set to zero each by each using a mechanical tuner.

A dedicated measurement bench has been developed. It is based on a time-domain load–pull setup, as depicted in Fig. 5. The central element of the bench is the nonlinear vector network analyzer (NVNA), which measures the magnitude and relative phase of each incident and scattered wave at each port of the DUT, thanks to the low-loss couplers. The tuner allows to set to zero the scattered waves, and sweep the of the model, as explained earlier. This bench has been automated in order to save time. The bench enables to measure and extract the MHV model with two kinds of excitation: continuous waves (CWs) or pulsed mode. Sometimes, in order to avoid thermal runaway of high-power transistors ( 50 W) and protect the time-domain load–pull environment (bias tee, tuners), the measurements need to be done under short RF pulses. However, the RF pulse has to be long enough to properly capture the short-term memory introduced by the pulse variation and not by the shape of the pulse. This is an alternative method of CW extraction, which seems suitable for automatic extraction. The configuration of the pulse identification is shown in Fig. 6. This is very useful for modeling a high-power device that must be characterized in pulsed mode to prevent destructive thermal state. Nevertheless, when the model is extracted from pulsed signals, it cannot be used for CW excitation. E. Experimental Validation of the MHV Model Applied to a 10-W Packaged GaN Transistor in CW Mode In CW mode, the MHV model of a 10-W packaged GaN transistor has been extracted with time-domain load–pull measurements at the quiescent bias point ( V,

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Fig. 6. Identification time response.

Fig. 9. Comparison between MHV model simulation (color solid line) and CW power measurements (black dots) at the optimum of PAE at 2.65 GHz.

Fig. 7. Comparison between MHV model simulation (color solid line) and CW power measurements (black dots) at the optimum of PAE at 1.85 GHz.

Fig. 10. Measured and simulated time-domain waveform of drain voltage and current at the maximum of PAE for the 10-W packaged transistor @2.25 GHz.

F. Experimental Validation of the MHV Model Applied to a 100-W GaN Packaged Transistor in Pulsed Mode

Fig. 8. Comparison between MHV model simulation (color solid line) and CW power measurements (black dots) at the optimum of PAE at 2.25 GHz.

mA) in the frequency range of extraction [1.85–2.65] GHz. In order to check the model accuracy, simulations of the MHV model are compared with power measurements when the device is matched to its optimum loads at the fundamental and harmonics ( and ) for the maximum of PAE. Figs. 7–9 show the very good agreement obtained between measured and simulated output power, power gain, and PAE at 1.85, 2.25, and 2.65 GHz, respectively. In order to validate the simulation of absolute phase, the measured and simulated time-domain waveforms have been compared. At 2.25 GHz, Fig. 10 illustrates the good agreement obtained between simulated and measured waveforms of drain voltage and current at the maximum of PAE.

In pulsed mode, the MHV model of a 100-W packaged GaN transistor has been extracted with time-domain load–pull measurements at the quiescent bias point ( V, mA) in the frequency range of extraction [1.2–2] GHz. As in the preceding case of the 10-W packaged transistor in CW mode, simulations of the 100-W MHV model are compared with power measurements when the packaged transistor is matched to its optimum loads at the fundamental and harmonics ( and ) for the maximum of PAE. In this case of a high-power transistor, all measurements have been performed in pulsed mode at several frequencies in -band. Figs. 11–13 show the good agreement obtained between measured and simulated output power, power gain, and PAE at 1.3, 1.7, and 2 GHz, respectively. As in the previous case of the 10-W model, the simulation of absolute phase is checked by plotting the measured and simulated time-domain waveforms. In the case of the 100-W MHV model, Fig. 14 shows the good agreement obtained at 1.7 GHz between simulated and measured waveforms of drain voltage and current at the maximum of PAE. Both 10- and 100-W MHV models have demonstrated good agreements between simulations and measurements so that Section III is dedicated to the design of two power amplifiers based on the use of these MHV models.

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Fig. 11. Comparison between MHV model simulation (color solid line) and pulsed power measurements (black dot) at the optimum of PAE @1.3 GHz.

Fig. 13. Comparison between MHV model simulation (color solid line) and pulsed power measurements (black dot) on the PAE optimum @ 2.0 GHz.

Fig. 14. Measured and simulated time-domain waveform of drain voltage and current at the maximum of PAE for the 100-W packaged transistor @1.7 GHz.

Fig. 12. Comparison between MHV model simulation (color solid line) and pulsed power measurements (black dot) on the PAE optimum @1.7 GHz.

III. DESIGN OF POWER AMPLIFIERS In this section, two power amplifiers will be designed using the preceding MHV models. The first one is a 10-W power amplifier in CW mode over 1.85–2.65 GHz, and the second one is a 85-W power amplifier in pulsed mode over 1.2–2 GHz. Our aim is to highlight the accuracy of the MHV model to design wideband and highly efficient power amplifiers in the case of CW or pulsed modes avoiding the complex and time-consuming extraction of classical nonlinear models of packaged power transistors. A. Design of a 10-W GaN Power Amplifier 1) Choice of the Operating Class: Since our goal is to design a wideband and efficient power amplifier, the narrowband class-F and class-F cannot be used. Therefore, the design will be based on a wideband harmonic control that is derived from the class-J concept. The bias point is set to a deep AB class. Indeed, instead of using lumped and elements such as in class-J proposed by Cripps [1], distributed elements are used to independently control the load impedance at and over a wide frequency range. As depicted in Fig. 15, radial stubs are

Fig. 15. Topology of the harmonic output matching network @

.

used and combined with a delay line to offset the value of the radial stub at the device port. The length of the radial stub is set to be invisible to and the angle of the stub is set to control the impedance at over a wide bandwidth ( 30%). To control the impedance at over a wide bandwidth, a matching by a nonuniform tapered line is then used (such as a Klopfenstein taper [15]). 2) Optimal Load and Source Impedance Analysis: To achieve high PAE and output power over a large bandwidth, the load impedances of the transistor at the fundamental and harmonic frequencies have to be controlled into the good area of

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Fig. 16. Optimum fundamental load impedances measured (color dot) and synthesized with the output matching circuit (black line) at the package plane.

the Smith chart over the entire bandwidth. The design challenge is that the phase rotation of these optimum impedances versus increasing frequency is counterclockwise on the Smith chart, while the phase rotation of a physical realizable circuit versus increasing frequency is clockwise on the Smith chart. Therefore, a tradeoff has to be found between wideband operation and high PAE since designing an ideal matching circuit, which presents the exact optimum impedances over all the bandwidth, cannot be achieved because of the counterclockwise phase rotation of the optimum impedances. Therefore, our design tradeoff was based on a precise control of the impedances presented to the fundamental over the bandwidth, while the impedances presented to the second harmonic will be confined into the Smith area, which corresponds to a maximum decrease of five points below the optimum PAE. Due to the frequency cutoff of the package, the influence of the third harmonic is negligible in this bandwidth, and has not been controlled precisely. In the case of the 10-W packaged GaN transistor, the optimum PAE contours has been measured at the minimum, center, and maximum frequencies of the bandwidth. The measured optimum impedance loci and the synthesized impedances at the fundamental frequencies are compared in Fig. 16 over the entire bandwidth. As predicted, the phase rotations are opposite, but the matching circuit keeps the synthesized impedances close to the optimum ones over the bandwidth. The results of the synthesized impedances at the second harmonic frequencies are plotted in Fig. 17 and compared to the contours of PAE decrease at . As observed in Fig. 17, the synthesized impedance at remains in the required Smith area at the center frequency, while at the minimum and maximum frequencies, the synthesized impedances at are moving away from the required Smith area, reaching a ten-point decrease of PAE. To design the input matching circuit, only the source impedances at fundamental frequencies have been controlled over the entire bandwidth. Due to the strong mismatch of the device input, the choice has been made to control the impedance at the center of the entire bandwidth. The measured optimum source impedances and the synthesized impedances at fundamental frequencies are compared in Fig. 18 over the entire bandwidth. 3) Fabricated 10-W Power Amplifier: The schematic principle of a class-J power amplifier is depicted in Fig. 19. In our case, the and components have been replaced with distributed lines and radial stubs, as can be observed in the pho-

Fig. 17. Second harmonic load–pull PAE contours @ GHz (left), GHz (middle), and GHz (right) indicating the drain @ efficiency decrease below the optimum PAE at the package plane.

Fig. 18. Optimal fundamental source impedance measured (color dot) and synthesized with the input matching circuit (black line) at the package plane.

Fig. 19. Schematic principle of a class-J power amplifier.

tograph of the fabricated power amplifier shown in Fig. 20. The optimum load impedance at is controlled by the two radial stubs that are the closest to the transistor, while the optimum load impedance at is controlled by the nonuniform tapered line placed on the output RF path. For the input matching, only the source impedance at is matched for maximum gain by using a nonuniform tapered line placed on the input RF path. Finally, the power amplifier was fabricated on a 20-mil-thick Rogers substrate with a dielectric constant of 3.66 integrating Cree’s CGH40010 packaged GaN HEMT. B. Design of a 85-W GaN Power Amplifier 1) Choice of the Operating Class: The same operating class (class-J) and the same design method of harmonic control than those described for the 10-W power amplifier have been used for

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Fig. 20. Photograph of the 10-W GaN power amplifier.

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Fig. 22. Second harmonic load–pull PAE contours @ GHz (left), GHz (middle), and GHz (right) indicating the drain @ efficiency percentage below maximum on the entire Smith chart at the package plane.

Fig. 23. Optimal fundamental source impedance measured (color dot) and synthesized with the input matching circuit (black line) at the package plane. Fig. 21. Optimal fundamental load measured (color dot) and synthesized with the output matching circuit (black line) at the package plane.

the 85-W power amplifier, except that the frequency bandwidth is 1.2–2 GHz. 2) Optimal Load and Source Impedance Analysis: To achieve high PAE and output power over a large bandwidth, the load impedances of the transistor at the fundamental and harmonic frequencies have to be controlled into the good area of the Smith chart over the entire bandwidth. In the case of the 100-W packaged GaN transistor, the optimum PAE contours has been measured at the minimum, center, and maximum frequencies of the 1.2–2-GHz bandwidth. The measured optimum impedance loci and the synthesized impedances at the fundamental frequencies are compared in Fig. 21 over the entire bandwidth. It can be noted that the phase rotations are opposite, but the matching circuit keeps the synthesized impedances as close as possible to the optimum ones over the bandwidth. The results of the synthesized impedances at the second harmonic frequencies are plotted in Fig. 22 and compared to the contours of PAE decrease at . As observed in Fig. 22, the synthesized impedance at remains in the required Smith area over the entire bandwidth with less than a five-point decrease of PAE. As in the preceding case of the 10-W device, the design of the input matching circuit have been performed to control only the source impedances at the fundamental frequencies over the bandwidth. The measured optimum source impedances and the

synthesized impedances at fundamental frequencies are compared in Fig. 23 over the entire bandwidth. 3) Fabricated 85-W Power Amplifier: Fig. 24 shows a photograph of the fabricated 85-W power amplifier. As in the case of the 10-W amplifier, the optimum load impedance at is controlled by the two radial stubs that are the closest to the transistor, while the optimum load impedance at is controlled by the nonuniform tapered line placed on the output RF path. For the input matching, only the source impedance at is matched for maximum gain by using a nonuniform tapered line placed on the input RF path. The 85-W power amplifier was fabricated on the same 20-mil-thick Rogers substrate with a dielectric constant of 3.66 integrating the Eudyna’s EGN045mk packaged GaN HEMT. IV. MEASUREMENT RESULTS OF THE POWER AMPLIFIERS A. Measurement Results of the 10-W Amplifier in CW Mode 1) -Parameter Measurements: Fig. 25 shows the measured -parameters of the 10-W power amplifier from 1.4 to 3 GHz at a bias point of V and mA. It can be noted that the simulation are restricted to the frequency range of extraction that was used for the MHV model (1.8–2.6 GHz for the 10-W GaN transistor). A good agreement is obtained between -parameter simulations and measurements, except in the case of because of the inaccurate model of the output decoupling capacitor on the RF

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Fig. 27. Comparison between simulated (color solid line) and measured (black dots) output power, gain, and drain efficiency at 2.2 GHz. Fig. 24. Photograph of the 85-W GaN power amplifier.

Fig. 28. Comparison between simulated (color solid line) and measured (black dots) output power, gain, and drain efficiency at 2.6 GHz.

Fig. 25. Comparison between simulated (black) and measured (red in online V and A. version) -parameters at a bias point of

Fig. 29. Measured results of the 10-W power amplifier from 1.7 to 2.7 GHz in CW mode.

Fig. 26. Comparison between simulated (color solid line) and measured (black dots) output power, gain, and drain efficiency at 1.8 GHz.

path. This comparison verifies that the MHV model enables a good modeling of the transistor at low signal levels even if this comparison includes the modeling and measurement of the passive matching circuits.

2) Power Measurements of the 10-W Amplifier: Power measurements of the 10-W power amplifier were performed in the CW mode from 1.7 to 2.7 GHz. Figs. 26–28 compare measured and simulated output power, gain, and drain efficiency at 1.8, 2.2, and 2.6 GHz, respectively. A good agreement is obtained between measurements and simulations at each frequency with an error lower than five points for efficiency and 0.3 dB for output power.

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Fig. 30. Comparison between simulated (black) and measured (red in online V and A. version) pulsed -parameters at a bias point of

Fig. 31. Comparison between simulated (color solid line) and measured (black dots) output power, gain, and drain efficiency at 1.2 GHz.

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Fig. 33. Comparison between simulated (color solid line) and measured (black dots) output power, gain, and drain efficiency at 2 GHz.

Fig. 34. Measured results of the 85-W power amplifier from 1 to 2.2 GHz in pulsed mode.

TABLE I COMPARISON OF WIDEBAND POWER AMPLIFIERS IN

- AND -BANDS

Fig. 32. Comparison between simulated (color solid line) and measured (black dots) output power, gain, and drain efficiency at 1.6 GHz.

Fig. 29 shows the measured output power, gain, drain efficiency, and PAE from 1.7 to 2.7 GHz at 23-dBm input power. In the 1.8–2.6-GHz band, the average values of output power and PAE are 40.7 dBm and 65%, respectively. B. Measurements of the 85-W Amplifier in Pulsed Mode 1) -Parameter Measurements: Fig. 30 shows the measured pulsed -parameters of the 85-W power amplifier from 1 to 3 GHz at a bias point of V and mA.

It can be noted that the simulation are restricted to the extraction band that was used for the MHV model (1.2–2 GHz for the 100-W GaN transistor). As in the case of the 10-W power amplifier, a good agreement is obtained between pulsed -parameter measurements and simulations. 2) Power Measurements of the 85-W Amplifier: Power measurements of the 85-W power amplifier have been performed in pulsed mode from 1 to 2.2 GHz. Figs. 31–33 compare measured and simulated output power, power gain, and drain efficiency at

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1.2, 1.6, and 2 GHz, respectively. A good agreement is obtained between measurements and simulations at each frequency with an error lower than five points for PAE and 0.3 dB for output powers. Fig. 34 shows the measured output power, gain, drain efficiency, and PAE from 1 to 2.2 GHz at 36-dBm input power. In the 1.2–2-GHz band (50% relative bandwidth), the average values of output power and drain efficiency are 85 W and 65%, respectively. V. COMPARISON WITH STATE-OF-THE-ART In order to highlight the good results obtained with the two power amplifiers 10 and 85 W designed with the MHV model, a comparison with other published works in similar frequency bandwidths is given in Table I. VI. CONCLUSION This paper has focused on the mathematical formulation, measurement-based extraction, and validation of an MHV model. This MHV model is illustrated through the examples of 10- and 100-W packaged GaN transistors. In addition, two wideband HPAs are designed in - and -bands using the MHV model. Comparisons between measurements and simulations demonstrate the ability of the MHV model to accurately predict the linear and nonlinear behaviors of mismatched packaged transistors in a design flow dedicated to wideband power amplifiers. The measurement-based extraction of the MHV model is less time consuming (few hours) and less complex than the extraction of a classical nonlinear equivalent-circuit model because it is directly provided by the dedicated measurement setup. This conclusion is even more verified in the case of packaged devices. As a result of its direct extraction from measurements, the MHV model is very accurate inside its extraction boundaries, while the nonlinear equivalent-circuit model has a greater ability to predict the device behavior beyond its extraction limits. REFERENCES [1] S. C. Cripps, RF Power Amplifiers for Wireless Communications, 2nd ed. Norwood, MA: Artech House, 2006. [2] D. Y.-T. Wu, F. Mkadem, and S. Boumaiza, “Design of a broadband and highly efficient 45 W GaN power amplifier via simplified real frequency technique,” in IEEE MTT-S Int. Microw. Symp. Dig., May 23–28, 2010, pp. 1090–1093. [3] J. Verspecht and D. Root, “Polyharmonic distorsion modeling,” IEEE Microw. Mag., vol. 7, no. 3, pp. 44–57, Jun. 2006. [4] J. M. Horn, J. Verspecht, D. Gunyan, L. Betts, D. E. Root, and J. Eriksson, “ -parameter measurement and simulation of a GSM handset amplifier,” in Eur. Microw. Integr. Circuits Conf., Oct. 27–28, 2008, pp. 135–138. [5] D. E. Root, J. Xu, J. Horn, M. Iwamoto, and G. Simpson, “Device modeling with NVNAs and -parameters,” in Integr. Nonlinear Microw. Millimeter-Wave Circuits Workshop, Apr. 26–27, 2010, pp. 12–15. [6] W. Demenitroux, C. Maziere, T. Gasseling, B. Gustavsen, M. Campovecchio, and R. Quere, “A new multi-harmonic and bilateral behavioral model taking into account short term memory effect,” in Eur. Microw. Conf., Paris, France, 2010, pp. 473–476.

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[7] W. D. C. Maziere, E. Gatard, S. Dellier, C. Saboureau, M. Campovecchio, and R. Quere, “A new multi-harmonic Volterra model dedicated to GaN packaged transistor or SSPA for pulse application,” in IEEE MTT-S Int. Microw. Symp. Dig., Boston, MA, Jun. 2009, pp. 1–4. [8] N. Le Gallou, E. Ngoya, H. Buret, D. Barataud, and J. M. Nebus, “An improved behavioral modeling technique for high power amplifiers with memory,” in IEEE MTT-S Int. Microw. Symp. Dig., 2001, vol. 2, pp. 983–986. [9] A. Soury and E. Ngoya, “A two-kernel nonlinear impulse response model for handling long term memory effects in RF and microwave solid state circuits,” in IEEE MTT-S Int. Microw. Symp. Dig., San Francisco, CA, Jun. 2006, pp. 1105–1108. [10] C. Mazière, A. Soury, E. Ngoya, and J. Nébus, “A system level model of solid state amplifiers with memory based on a nonlinear feedback loop principle,” in IEEE Int. Eur. Microw. Conf., Paris, France, Oct. 2005, vol. 1, pp. 853–856. [11] E. Ngoya, C. Quindroit, and J. Nébus, “Improvements on long term memory modeling in power amplifiers,” in IEEE MTT-S Int. Microw. Symp. Dig., Boston, MA, Jun. 2009, vol. 2, pp. 1357–1360. [12] B. Gustavsen and A. Semlyen, “Rational approximation of frequency domain responses by vector fitting,” IEEE Trans. Power Del., vol. 14, no. 3, pp. 1052–1061, Jul. 1999. [13] B. Gustavsen, “Improving the pole relocating properties of vector fitting,” IEEE Trans. Power Del., vol. 21, no. 3, pp. 1587–1592, Jul. 2006. [14] “Vector fitting website,” SINTEF, Oslo, Norway, 2009. [Online]. Available: www.energy.sintef.no/produkt/VECTFIT/index.asp [15] R. W. Klopfenstein, “A transmission line taper of improved design,” Proc. IRE, vol. 44, no. 1, pp. 31–35, Jan. 1956. [16] M. P. Van der Heijden et al., “A compact 12-watt high-efficiency 2.1–2.7 GHz class-E GaN HEMT power amplifier for base stations,” in IEEE MTT-S Int. Microw. Symp. Dig., Boston, MA, Jun. 2009, pp. 657–660. [17] P. Wright, J. Lees, J. Benedikt, P. J. Tasker, and S. C. Cripps, “A methodology for realizing high efficiency Class-J in a linear and broadband PA,” IEEE Trans. Microw. Theory Tech., vol. 57, no. 12, pp. 3196–3204, Dec. 2009. [18] P. Saad, C. Fager, H. Cao, H. Zirath, and K. Andersson, “Design of a highly efficient 2–4-GHz octave bandwidth GaN-HEMT power amplifier,” IEEE Trans. Microw. Theory Tech., vol. 58, no. 7, pp. 1677–1685, Jul. 2010. [19] A. Ramadan, T. Reveyrand, A. Martin, J.-M. Nebus, P. Bouysse, L. Lapierre, J.-F. Villemazet, and S. Forestier, “Two-stage GaN HEMT amplifier with gate–source voltage shaping for efficiency versus bandwidth enhancements,” IEEE Trans. Microw. Theory Tech., vol. 59, no. 3, pp. 699–706, Mar. 2011. [20] V. Carruba, J. Less, and J. Benedikt et al., “A novel highly efficient broadband continous class-F RFPA delivering 74% average efficiency for an octave bandwidth,” in IEEE MTT-S Int. Microw. Symp. Dig., Baltimore, Jun. 2011, pp. 1–4. [21] K. Chen and D. Peroulis, “Design of highly efficient broadband class-E power amplifier using synthesized low-pass matching networks,” in IEEE MTT-S Int. Microw. Symp. Dig., Baltimore, MD, Dec. 2011, vol. 59, no. 12. [22] M. Ozen, R. Jos, C. M. Andersson, M. Acar, and C. Fager, “High-efficiency RF pulsewidth modulation of class-E power amplifiers,” IEEE Trans. Microw. Theory Tech., vol. 59, no. 11, pp. 2931–2942, Nov. 2011.

Wilfried Demenitroux was born in Limoges, France, in 1985. He received the M.S. and Ph.D. degrees in electrical engineering from Limoges University, Limoges, France, in 2008 and 2011, respectively. From 2008 to 2011, he was with AMCAD Engineering, Limoges, France, and the XLIM Laboratory, Limoges, France, where he was involved with behavioral modeling of transistors dedicated to the design of high-power, high-efficiency, and broadband amplifiers. In 2011, he became an RF and Microwave Engineer with AMCAD Engineering. His research interests include behavioral modeling, time-domain load–pull measurements, wideband and high-efficiency power-amplifier design, and envelop tracking.

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Christophe Mazière was born in Limoges, France, in 1977. He received the M.S. and Ph.D. degrees in electrical engineering from the University of Limoges, Limoges, France, in 2001 and 2004, respectively. In 2006, he joined AMCAD Engineering, Limoges, France, where he is involved with the development of advanced test benches for high-power device characterization. Since 2009, he has developed the activity of behavioral modeling with multiharmonics models. His research concerns behavioral modeling of nonlinear devices.

Emmanuel Gatard received the Electronics and Telecommunications Engineering degree from ENSIL, Limoges, France, in 2002, and the Ph.D. degree in electrical engineering from the University of Limoges, Limoges, France, in 2006. Since 2008, he has been with AMCAD Engineering, Limoges, France, where he is in charge of advanced test benches development for high-power device characterization. He is also involved with envelope-tracking amplifiers and microelectromechanical systems (MEMS) switches modeling. His research interests with the XLIM Research Laboratory concern electrothermal modeling of power semiconductor devices dedicated to circuit simulations, physics-based electron device simulations, and nonlinear thermal modeling.

Stéphane Dellier received the M.S. and Ph.D. degrees in electrical engineering from the University of Limoges, Limoges, France, in 2001 and 2005, respectively. His doctoral research concerned microwave circuit design. In 2004, he cofounded AMCAD Engineering, Limoges, France, a company that provides new RF and microwave solutions to semiconductor professionals. He is currently Project Leader with AMCAD Engineering, where he is focused on stability analysis of microwave circuits and CAD design flow.

Michel Campovecchio received the M.S. and Ph.D. degrees in electrical engineering from the Technical University of Limoges, Limoges, France, in 1989 and 1993, respectively. In 1994, he joined the XLIM Institute (formerly IRCOM), Centre National de la Recherche Scientifique (CNRS), Limoges, France, to investigate the nonlinear modeling of high-power microwave transistors and the design of wideband power amplifiers. In 2000, he became a Full Professor of electrical engineering with the University of Limoges, where he is in charge of the Power Amplifier Group, XLIM Institute. His current research interests include wideband high-efficiency and HPAs in III–V and III-N technologies for radar and space applications.

Raymond Quéré (M’88–SM’99) received the Electrical Engineering degree and French Agrégation degree in physics from ENSEEIHT-Toulouse, Toulouse, France, in 1976 and 1978, respectively, and the Ph.D. degree in electrical engineering from the University of Limoges, Limonges, France, in 1989. In 1992, he became a Full Professor with the University of Limoges, where he currently heads the research group on high-frequency nonlinear circuits and systems with the Institut de Recherche en Communications Optiques et Microondes (IRCOM), Centre National de la Recherche Scientifique (CNRS), Toulouse, France. He is mainly involved in nonlinear modeling and design of microwave devices and circuits. He serves as a reviewer for several journals. Dr. Quéré became general chairman of European Microwave Week, Paris, France, in 2005. He is involved in a number of Technical Program Committees.

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Design of Adaptive Highly Efficient GaN Power Amplifier for Octave-Bandwidth Application and Dynamic Load Modulation Kenle Chen, Student Member, IEEE, and Dimitrios Peroulis, Member, IEEE

Abstract—This paper presents a novel adaptive power amplifier (PA) architecture for performing dynamic-load-modulation. For the first time, a dynamically-load-modulated PA design that achieves octave bandwidth, high power and high efficiency simultaneously is experimentally demonstrated. This PA design is based on a commercial GaN HEMT. The output matching scheme incorporates a broadband static matching for high-efficiency at the maximum power level and a wideband dynamic matching for efficiency enhancement at power back-offs. The impedance and frequency tunability is realized using silicon diode varactors with a very high breakdown voltage of 90 V. Experimental results show that a dynamic-load-modulation from maximum power to 10-dB back-off is achieved from 1 to 1.9 GHz, with a measured performance of 10-W peak power, 10-dB gain, 64%–79% peak-power efficiency, and 30%–45% efficiency at 10-dB power back-off throughout this band. Index Terms—Adaptive, broadband matching, diode varactor, dynamic load modulation, GaN, high efficiency, high power, power amplifier (PA), tunable matching network.

I. INTRODUCTION

P

OWER amplifiers (PAs) are the most energy-consuming component in wireless transceivers. Modern wireless communication systems require high PA efficiency to achieve reduced energy consumption and better device reliability. Such PAs are usually designed and implemented based on switch-mode (Classes D and E) and harmonic-tuned topologies (Classes J, F, and F ) [1], [2], which, however, operate efficiently only at high saturation levels. Nevertheless, modern bandwidth-efficient communication signals usually have high peak-to-average ratios (PARs), e.g., around 8-dB PAR for a typical 3GPP long-term-evolution (LTE) signal [3]. Thus, in these systems, PAs tend to work in significant power back-offs, leading to degradations of average efficiencies. Several techniques have been proposed and demonstrated to improve the efficiency at power back-offs, such as dynamic power supply [6], [7], Doherty PAs [4], [5], and outphasing Manuscript received September 29, 2011; revised February 13, 2012; accepted February 16, 2012. Date of publication April 03, 2012; date of current version May 25, 2012. This work was supported by Rockwell Collins Inc., Cedar Rapids, IA. The authors are with the School of Electrical and Computer Engineering and Birck Nano Technology Center, Purdue University, West Lafayette, IN 47906 USA (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2012.2189232

method [5]. However, extra amplifiers are required in those methods, leading to extra loss, size issues and increased circuit complexity. Comparatively, dynamic load modulation (DLM) has been proposed and demonstrated as an effective substitution [9]–[13]. It utilizes tunable output matching networks (OMNs) with passive tuning components that consume negligible dc power and can be designed as a part of the OMN. Moreover, the DLM technique has also been demonstrated at transmitter-level [14], [15], where the varactor-based matching network is controlled by the baseband signal, generated and predistorted by the DSP module. Furthermore, traditional high-efficiency PAs require precise harmonic terminations, resulting in bandwidth restrictions of those PAs. However, in some future wireless systems, more and more frequency bands and spectrum allocations will be involved. Also, the effective bandwidth of the communication signals, such as WCDMA, LTE and WiMax, can be as wide as 20 MHz. Therefore, there is a pressing need to extend the frequency performance of traditional high-efficiency PAs. Recently, several static design methodologies [16]–[19] have been proposed to address this problem, achieving high efficiencies ( 60%) across octave-level bandwidths. Nevertheless, such high efficiencies are only achieved at maximum power levels, which drop significantly at the power back-offs, e.g. around 20% at 10-dB back-off in [18] and [19]. It is also important to note that most of the current DLMPAs/transmitters are designed for single-band operation [11], [12], [15], due to the complication of the varactor-based DLM matching. A multiband design has been demonstrated using the approach [10], but the peak efficiency and power are fairly low (50%, 28 dBm). In this research, we perform DLM over an octave bandwidth while maintaining the same level of peak efficiency and power as those achieved in static designs [16], [18], [19]. This adaptive PA design is based on a commercial GaN HEMT and diode varactors with a high breakdown voltage are used as the tuning element. The tunable output matching netreswork is designed using a combination of a tunable series onator and a fixed multistage low-pass filter-transformer. This tunable matching network provides not only the optimal fundamental impedance according to various power levels and frequencies, but also very favorable harmonic impedances. Moreover, only one tuning element is used in this DLM-PA topology, yielding simpler controlling scheme and lower insertion loss, compared to those which use multiple varactors/switches [10], [11], [13]. Using the proposed topology, the DLM-PA in this paper presents the optimized performance over a bandwidth of

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Fig. 2. DLM-PA schematic for achieving a continous broad bandwidth.

Fig. 1. Schematics of DLM-PA. (a) Separate design [12]. (b) Codesign [10], [15].

1–1.9 GHz (62%) with a peak power of around 10 W, efficiency of 64%–79% at the peak power level, and 30%–45% efficiency at 10-dB power back-off. II. BROADBAND DYNAMICALLY-LOAD-MODULATED PA A. Extending the Bandwidth of DLM-PA Fig. 1(a) schematically illustrates a typical DLM transmitter [12], [14], which consists of a static PA and a tunable matching network (TMN). The PA and TMN are designed and implemented independently. This method enables measurement-based characterizations of the PA and tunable matching network, leading to a better design accuracy. However, this independently designed DLM-PA contains more elements than a stand-alone PA, resulting in additional insertion loss and mismatch, as well as an efficiency-decrease (from 70% in [2] to 57% in [12]). Also, as mentioned in [15] the bandwidth is limited to 5 MHz, due to the interconnecting 50- transmission line between the PA and TMN. Thus, this independent design methodology is not optimal for implementing a broadband DLM-PA. Alternatively, as shown in Fig. 1(b), the design of PA output matching network and TMN is integrated, achieving a reduced circuit complexity and potential for broadband application. A multiband design is presented in [10] using this codesign method, which is based on a classical ladder-based tunable matching network topology. It is noted that this design gives priority to the fundamental-impedance matching rather than the harmonics, leading to a relatively low peak-power efficiency (40%–50%). In [15], another codesign method is proposed, in which harmonic matching is performed in parallel with fundamental matching, leading to a high efficiency at , which is comparable to those of the static PAs. However, this approach dose not address the multiband design. To extend the bandwidth of the DLM-PA to an octave-level, a novel dynamically load modulated PA topology is proposed in

Fig. 3. Efficiency-optimized load impedance at various output power from 10 to 1 W within -band, extracted from the loadpull simulation using ADS.

this investigation as shown in Fig. 2. Two steps are involved in this DLM matching scheme. First, a fixed filter-matching network is designed to transform the 50- load to the optimal impedance at maximum power level within the passband of the filter, while providing a stopband reflection coefficient of , as required for high efficiencies. Second, a varactor-based tunable circuit is connected between the filter and transistor, to provide the optimal fundamental impedance for the transistor with respect to various power levels and frequencies. While the tunable matching circuit also affects the harmonic impedances, it does not change the magnitude of , due to its zero-resistance (ideally). Thus, harmonics are still rejected. In turn, a continuous broad bandwidth can be achieved using this DLM-PA topology, while a high efficiency can be maintained. B. Transistor Characterization for Dynamic-Load-Modulation To demonstrate the proposed design methodology, a Cree GaN HEMT (CGH40025, 25 W, dc-6 GHz) is selected as the RF power device. As mentioned in [10] and [15], the co-design method relies heavily on the accuracy of the transistor model. In [19], the manufacturer’s model is demonstrated to be very trustable for the broadband high-efficiency PA design, and it is thus utilized for this broadband DLM-PA design. The transistor is characterized using load-pull simulation setup in Agilent’s Advanced Design System (ADS) [20]. The initial target bandwidth is the entire -band from 1 to 2 GHz. Fig. 3 shows the simulated dynamic load locus at 1, 1.5, and 2 GHz, respectively. The desired output impedance varies with both power and frequency. When the power level

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Fig. 4. Simulated load-pull contours of the second harmonic impedance. (a) At GHz. (b) At GHz [19].

drops (from 10 to 1 W), the desired impedance becomes more inductive. Specifically, it approximately moves along the 10constant-resistance circle on the Smith chart, as indicated by the arrows in Fig. 3. Having such a trajectory with a nearly constant real part is a key enable for the proposed design. Another GaN transistor used in [15] shows similar DLM impedance trajectory. It is also observed from Fig. 3 that the DLM locus at 2 GHz deviates slightly from the constant-resistance circle, because the parasitic effects of the transistor becomes more significant at higher frequencies. Harmonic-impedance matching is also critical for high-efficiency PAs. Only the second harmonic is considered in this research as it plays the most important role in affecting the PA efficiency. Fig. 4 shows the simulated load-pull contours of the second harmonic at 1 and 2 GHz, indicating the tolerable region of the second harmonic impedance in which the high efficiency can be achieved. On the PA designer’s side, there are three challenging requirements for the tunable output matching network: 1) to over the dynamic load modulation locus within a broad bandwidth; 2) to be capable of handling the PA output power (10 W at maximum); 3) to provide appropriate harmonic impedance avoiding the low-efficiency region. In the following section, the design of the tunable output matching network will be presented in detail, including topology selection, varactor selection, bandwidth–power tradeoff, and characterizations. III. TUNABLE OUTPUT MATCHING NETWORK DESIGN A. Broadband DLM Matching Scheme for the GaN Transistor As shown in Fig. 3, the desired DLM trajectory within 1–2 GHz is nearly located on the 10- constant-resistance circle. To match this particular locus within the target bandwidth, the matching scheme in Fig. 2 is modified slightly. The output matching network is constructed with a tunable series “resonator” and a fixed low-pass matching network, as shown in Fig. 5. Instead of matching 50- load to , the fixed matching network is designed to transform 50 load to 10 within the desired bandwidth. Then, a fixed inductor and a tunable capacitor are connected in series with the fixed

Fig. 5. Output matching network topology for performing broadband DLM on the Cree GaN transistor.

Fig. 6. Fixed output matching network design. (a) Ideal low-pass topology. (b) Implemented circuit using all-distributed elements on Rogers Duroid 5880LZ substrate.

matching network to provide a variable imaginary part. Thus, the input impedance of this entire matching network is given by (1) within the desired bandwidth. By changing the value of , the frequency-induced impedance variation is compensated and can be brought to any point of the blue region in Fig. 5, which covers the desired DLM trajectory. In turn, only one tuning element is required for this topology. This matching network topology is actually equivalent to that shown in Fig. 3, because a part of the fixed inductor can be absorbed in the fixed matching network to provide the inductive . B. Fixed Matching Network The fixed matching network is aimed to transform 50 to 10 within the bandwidth of interest (a 67%-bandwidth 5:1 impedance transformer). Recently, a high-order

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shown in Fig. 6(b). The inductors and capacitors are replaced by high-impedance (high- ) transmission line sections and low-impedance open-circuit stubs, respectively. The parameters of the implemented low-pass matching network are also shown in Fig. 6(b). Fig. 7(a) and (b) plots the simulated fundamental and secondharmonic impedances of the implemented low-pass matching network within the target frequency band. A good agreement between schematic and full-wave simulations is observed. The input impedance enclosed in the black circle (within 1–2 GHz) has a real part of approximately 10 . Fig. 7. Input impedance of the implemented fixed matching network extracted from (a) schematic simulation and (b) full-wave simulation.

C. Tunable Series

Resonator

The tunable capacitor is the most critical component in the output matching network. To date, various varactor techniques have been utilized to implement the tunable PA, such as diodes [10]–[12], MEMS varactors/switches [13], and LDMOS [15]. Considering the tuning range and commercial availability, diode varactors are chosen in this design. For a diode varactor, quality factor, power handling, tuning range, and linearity are the most important parameters taken into account for microwave applications. The GaAs varactor diodes, used in [11], has a high quality factor of up to 3000 at 50 MHz, but its low break down voltage, typically 20 V, hinders its application to high power circuits. The hyperabrupt-doping silicon diodes yield a very high tuning range, but they also lead to a low quality factor [23], [24] and poor linearity [25]. Considering these four parameters, the abrupt-junction silicon diode varactors from Micrometrics (MTV4090 series) are utilized for implementing this tunable PA. They have a high break down voltage of 90 V, high tuning range of , and fairly high quality factors of 750–1000 at 50 MHz [23]. A similar Micrometrics varactor (MTV4060-12-20) has been successfully applied in high power designs [12], [14]. The voltage-dependent junction capacitance of this uniformly doped diode is theoretically expressed as (2) where

denotes the initial capacitance value, . Thus, the imaginary part of (1) becomes

, and (3)

Fig. 8. Broadband DLM matching scheme using diode-varactor-based tunable matching network. (a) At 1 GHz. (b) At 1.5 GHz. (c) At 2 GHz.

low-pass filter has been successfully applied in designing octave-bandwidth high-efficiency PAs [19]. This low-pass-filter matching topology is also utilized in this design. A 3-stage low-pass matching network is designed to achieve the 5:1 impedance transformer across the 1–2 GHz bandwidth, as shown in Fig. 6(a). Using the similar synthesis and implementation method as presented in [19], the fixed low-pass matching network is implemented using transmission lines,

does not have to be in (2) as a combination where of varactors (series or/and parallel) can be used in the actual circuit, which allows a better design flexibility. Fig. 8 depicts how the DLM locus is matched using the tunable OMN within 1–2 GHz, where stands for the optimized input impedance of the tunable OMN for different frequencies and power levels. As the fixed matching network has already transformed the 50- load to the region enclosed in the red circle, the impedance moves clockwise due to the series inductor and is brought back by the varactor. As the frequency increases, the fixed inductor makes the impedance travel farther and a smaller capacitance is needed to compensate it. Therefore, at different frequencies, different fragments of the diode tuning range are used to cover the DLM locus, as shown in Fig. 8(a)–(c). The blue lines represent the covered DLM locus

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Fig. 10. Prediction of the voltage swing on the tuning element.

Fig. 9. Turn-on and breakdown limits of diode varactors in presence of RF swings [12].

corresponding to the capacitance value of the varactor. It is also observed that denotes of 1 W output power at 1 GHz, denotes of 10 W output power at 2 GHz. Therefore, as depicted in Fig. 8(a)–(c), the dynamic load modulation locus can be covered at every frequency point within the 1–2 GHz band, and the nearly entire tuning range of the varactor is applied. To optimize this tunable resonator, firstly, the values of and can be estimated analytically by

Therefore, the RF swing of each varactor diode is divided by a factor of . Practically, this method introduces extra parasitics that should be considered carefully for GHz-level applications. In this design, is considered, serving as the anti-series (or back-to-back) diodes pair [26]. On the other hand, to further reduce the series resistance, five pairs of anti-series diodes are stacked in parallel as a single tuning element. This anti-series topology also enhances the linearity of the varactor, which has been demonstrated in [25] and [26]. The RF voltage swing is also dependent on the matching network topology and the location of the tuning element. In [12], the varactors are connected in parallel with the load, so the voltage swing across the varactor is the same as the load voltage amplitude. In our design, the varactor is connected in series with the transistor drain (Fig. 10). Therefore, the voltage swing across it is dependent on the output RF current of the drain, which can be approximately calculated by (6)

(4) 16 and 6 denote the imaginary parts of at 1 W, 1 GHz [Fig. 8(a)] and at 10 W, 2 GHz [Fig. 8(c)], respectively. According to (4), and need to be determined in order to find the proper values of and . Due to the RF swing across the varactor, which should be carefully considered in the high power design, the entire tuning range is usually not achievable. The final design will be further optimized using ADS simulation together with a compromise between bandwidth and power-handling capability. where

D. Power Handling Issues and Enhancement For the adaptive high power amplifier application, the RF voltage swing on a tuning element is usually very large, e.g., 26.6 V when an output power of 7 W is delivered [12]. To avoid turn-on and breakdown of the diode, as illustrated in Fig. 9, the dc-bias voltage and the RF voltage swing should satisfy the following relation: (5) should be sufficiently far Therefore, as illustrated in Fig. 9, away from the turn-on point (0 V) and the breakdown point (90 V), which actually reduces the tuning range of the varactor . To enhance the power handling of the varactor diodes and to increase the tuning range, a diodes-stack with elements in parallel and series can be utilized [25].

is around 10 and maximum is 10 W. In turn, where the voltage swing across the varactor can be estimated by (7) The above (7) underlines that a larger capacitance value results in a smaller voltage swing. However, (3) also implies that a smaller is needed to achieve a larger impedance tuning range. Therefore, a compromise between the tuning range and the voltage swing is necessarily made here to select the value of . Herein, a simplified ADS model of the output matching network is utilized to investigate the proper value of , which is shown in Fig. 11(a). A 5 2 varactor stack is used here, leading to . In this topology, the voltage swing across each diode is an half of the total voltage swing across the diode-stack. For any given value , a harmonic-balance (HB) ADS simulation provides the expected maximum voltage swing at 1 GHz [red line in online version in Fig. 11(b)]. Based on Fig. 8 under the restriction outlined in (5), the maximum frequency that a perfect match can be achieved will depend on this voltage swing. This maximum frequency can be calculated by HB simulation by varying the bias voltage in Fig. 11(a). The maximum frequency versus is plotted in Fig. 11(b). It can be seen that, as the value of increases, the voltage swing drops significantly from 70 V to around 10 V, while increases sharply and reaches a local maximum when

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Fig. 11. Determining the optimal value of (b) Voltage swing and tuning range versus

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. (a) Simplified ADS model. .

Fig. 12. Circuit topology of the output matching network.

pF. For pF, the tuning range decreases gradually, because a larger initial capacitance value leads to a smaller reactance variation range as indicated in (3). Therefore, the optimal value of is around 40 pF for achieving a maximum frequency tuning range. However, according to [23], a larger capacitance value leads to a lower quality factor. As a result, the Micrometrics diode varactor with pF and at 50 MHz (MTV4090-12-1) is selected, leading to pF for the 5 2 diodes stack. To achieve a wider frequency tuning range, a compromise needs to be made with lower output power and/or smaller dynamic range, e.g., 5–1 W. The output matching network is eventually optimized together with the transistor using ADS, in order to perfect the PA performance in frequency and efficiency. The finalized design is schematically shown in Fig. 12. The diode model used in this design is shown in the dotted rectangle of Fig. 12, same as that presented in [12]. The parasitics involve a series inductance of 1.5 nH, a series resistance of 1.2 , and a parallel capacitance of 0.2 pF. The inductive parasitic (due to both the package and connection) and detuning effect

Fig. 13. Measured and simulated input impedances and simulated second-harmonic impedance of the output matching network. (a) At 1 GHz. (b) At 1.5 GHz. (c) At 1.9 GHz.

of the diode-stack layout can result in a fairly significant mismatch, as mentioned in [12]. It is important to note that these two effects can be compensated by the series inductor in this particular topology, leading to no adverse impact on the matching accuracy. This series inductor is implemented using a 96- transmission line with an electrical length of 5.8 at 1.5 GHz (2.3 mm), which is approximately equivalent to a 2.1-nH inductor. Another 2.1-mm 42- transmission line is placed on the left-hand side of the varactor to fit the leading pad of the packaged GaN transistor. E. Evaluation of the Entire Tunable Output Matching Network The varactor-based tunable OMN is implemented and characterized in advance of the PA. Fig. 13 shows the measured and simulated small-signal DLM impedance locus of the tunable OMN at 1, 1.5, and 1.9 GHz, respectively. The simulation and measurement agree well with each other. They show a good coverage of the optimal DLM locus (Fig. 3). Fig. 13 also plots the simulated second-harmonic impedance corresponding the fundamental one with the same , indicating that of this

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TABLE I SUMMARY OF LARGE-SIGNAL SIMULATION RESULTS

Fig. 17. Fabricated circuit of the adaptive power amplifier.

Fig. 14. Simulated voltage waveforms on the varactors for 1-W output power at 1 GHz.

Fig. 15. Simulated voltage waveforms on the stack of varactors for 10-W output power at 1, 1.5, and 1.9 GHz.

Fig. 16. Schematic of the input matching network [19].

output matching network locates in the high-efficiency region compared to Fig. 4. Furthermore, the large-signal characterization of the tunable OMN is performed using the HB simulator in ADS. Table I lists the simulation results at different power levels and different frequencies, indicating a low insertion loss of 0.4 dB and 10-W power handling capability. Fig. 14 shows the simulated voltage waveforms of the matching network for V and . and are the voltage swings across two varactors in series in Fig. 12. It is observed from Fig. 14 that the

Fig. 18. Measured PA performance at 1.3 GHz versus output power for various varactor bias voltages. (a) PAE. (b) Efficiency. (c) Gain.

varactor voltages do not cross 0 V, thus avoiding the turn-on effect. It is also noted that although the voltage waveforms on each of the varactors are distorted, the total voltage of anti-series varactors is almost a perfect sinusoidal wave. Fig. 15 shows the simulated at 1, 1.5, and 2 GHz when 10-W power is delivered. As the total voltage swing is equally shared by these two series varactors, i.e., , the turn-on or

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Fig. 19. Optimal bias voltage of varactor diode at the maximum power level and 10-dB back-off within 0.9–2 GHz.

Fig. 21. Measured and simulated efficiency at the maximum power level.

Fig. 22. Measured PAE and gain at the maximum power level. Fig. 20. Measured maximum output power and harmonics level.

breakdown limits expressed in (5) are not exceeded, according to the bias voltages listed in Table I. IV. PA DESIGN AND IMPLEMENTATION The broadband input matching network in this design is the same as that in [19], which has been optimized for -band input matching of the CGH40025 transistor. The schematic of the input matching network is shown in Fig. 16. The entire PA circuit is fabricated on a Rogers Duroid 5880LZ substrate with a thickness of 20 mil, as shown in Fig. 17. The circuit board is mounted on an aluminum plate which serves as a heat sink and common ground. The gate bias network is realized using a 27–nH Coilcraft air-coil inductor in series with a 250- resistor. The same inductor is also used for the drain biasing network. A Coilcraft conical inductor of 0.57 H, which is ultra broadband and high- , is utilized to bias the varactors. It is important to note that the actual bias voltage on the varactor is the electrical potential difference between the varactor voltage and the drain voltage, as shown in the insert of Fig. 17, which is given by

Fig. 23. Measured and simulated drain efficiency at 10-dB power back-off.

(8) The dc blocks are not included in this circuit board, and two external dc blocks are connected at the input and output in the PA testing. V. EXPERIMENTAL RESULTS OF THE BROADBAND LOAD-MODULATED PA In previous sections, the optimum bias voltage of the varactor has been found from the independent characterizations of the

Fig. 24. PA gain at 10-dB back-off under static operation and DLM operation.

transistor and the tunable OMN, as shown in Fig. 3 and Fig. 13, respectively. Combining them together as the adaptive PA, the actual optimum-bias-voltage is obtained eventually in the PA testing, by perfecting the PA efficiency with respect to different frequencies and different power levels. Two cases are compared

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Fig. 25. Measured PA gain and efficiency under the DLM operation and static operation. (a) 1 GHz. (b) 1.1 GHz. (c) 1.2 GHz. (d) 1.3 GHz. (e) 1.4 GHz. (f) 1.5 GHz. (g) 1.6 GHz. (h) 1.7 GHz. (i) 1.8 GHz.

here: 1) the classical high-efficiency PA with the TMN statically tuned for only the maximum power level at each frequency point; 2) the dynamic PA with OMN dynamically modulated for different power level. The transistor gate is biased at the pinch-off point of 3.3 V. The DLM-PA is excited with a continuous-wave input signal, which is generated by an Agilent signal generator and boosted by a driver PA. The output power is measured by a spectrum analyzer, and the losses in the connecting cables has been calibrated beforehand. A power-sweep experiment is first performed with the realized PA at 1.3 GHz for various varactor bias voltages to validate its operation. Fig. 18 shows the measured PAE, efficiency and gain versus for five different values, indicating that a significant enhancement at power back-offs can be achieved by decreasing . It is also seen from Fig. 18(c) that a flatter gain versus , compared to the static case, is achieved under the efficiency-optimized controlling scheme, implying a good potential for performing linearization on this PA using digital-predistortion-based techniques, such as [14] and [15]. The same experiment is conducted over the entire band from 0.9 to 2 GHz with steps of 0.1 GHz. Fig. 19 shows the optimized at maximum power level and 10-dB back-off, as well as the drain bias voltage, versus frequency. Fig. 20 plots the measured maximum power and corresponding harmonics level at each frequency point. This is the highest power level demonstrated for the adaptive PA design compared to the state-of-the-art results [10], [12], [15]. It is also seen from Fig. 20 that the second and

third harmonics are very low (less than 30 dBc for most of the frequency points), due to the combined filter behavior of the low-pass matching network and the resonator tank. Moreover, the high-linearity antiseries topology of varactors leads to an insignificant contribution to the harmonic generation [12]. Fig. 21 plots the measured efficiency at the maximum power level within the entire band, which agrees with the predicted efficiency from ADS simulation. The measured efficiency of 64%–79% is achieved from 1 to 1.9 GHz. Fig. 22 shows the measured PAE and gain at the maximum power level, which shows that 55%–72% PAE and 10-dB gain are achieved from 1 to 1.9 GHz. The drop of PA performance above 1.9 GHz is primarily due to the connection parasitics and the dispersive effect of the varactor-stack. The maximum-power performance of this tunable PA compares favorably to the state-ofthe-art static broadband PAs [16]–[18]. Compared to the static low-pass-filter-based PA in [19], the efficiency-degradation of this adaptive PA is mainly owing to the lossy diode varactors. The PA performance can be further improved, if using varactors with higher quality factors, e.g. MEMS, ferroelectric or LDMOS transistor [15]. The measured and simulated PA efficiencies at 10-dB power back-off are shown in Fig. 23, indicating a good agreement between measurement and simulation. The comparison is made between the static operation (fixed for ) and DLM operation (efficiency-optimized ). From 1 to 1.7 GHz, the efficiency improvement at 10-dB back-off is typically greater than 15%, resulting in an effective doubling of the efficiency when

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compared to the PA with a static load. The efficiency improvement degrades when operating above 1.8 GHz, because the optimal DLM locus deviates from the constant-resistance circle [see Fig. 3(c)] due to the transistor’s package parasitics. For higher frequency applications, i.e., 2 GHz, the same design methodology can be conducted on an unpackaged transistor, e.g. the one used in a 2.65 GHz load-modulated PA in [15]. Moreover, the DLM operation results in a minimal effect on the PA gain at the 10-dB back-off, which can be observed from Fig. 24. Fig. 25 plots the measured efficiency and gain of this loadmodulated PA under the efficiency-optimized and static operations from 1 to 1.8 GHz. It is indicated that an optimized DLM operation can be conducted over a broad power range ( 10 dB) within the entire -band. The reduction of dc power consumption using this DLM optimization can be calculated by (9) For example, the increase of efficiency from 25% to 40% at 1-W power level, shown in Fig. 25 (operating at 1.3 GHz), indicates a 1.8-W reduction of the dc power consumption. For amplification of an actual communication signal, is dynamically tuned by the base-band processor according to the instantaneous envelop of the signal. Using the dynamic-controlling and linearization techniques for single-band DLM-PAs [14], [15], which has the same load-adaption range, a multiband DLM transmitter can be created with this PA. VI. CONCLUSION A novel methodology for designing and implementing adaptive power amplifier with continuous tunability for broadband dynamic-load-modulation has been proposed in this paper. The tunable output matching network is composed of a combination of a tunable series resonator in cascade with a sixth-order low-pass filter. Commercial available diode varactors with high breakdown voltage and high tuning range are used to realize the tunability. The implemented PA achieves a substantial operating frequency band from 1–1.9 GHz, in which an optimal dynamic-loadline-modulation is performed. A PA performance of 10-W peak power, 10-dB gain, 64%–79% peak-power efficiency, and 30%–45% 10-dB back-off efficiency has been measured throughout this band. This is the first experimental demonstration of a high-power, high-efficiency, broadband and dynamically-load-modulated PA suitable for next-generation wireless communication systems. ACKNOWLEDGMENT The authors would like to thank Dr. W. Chappell and his research group, Purdue University, West Lafayette, IN, for fabrication assistance, and Cree Inc., Durham, NC, for supplying the transistor model. REFERENCES [1] P. Saad, H. M. Nemati, M. Thorsell, K. Andersson, and C. Fager, “An inverse class-F GaN HEMT power amplifier with 78% PAE at 3.5 GHz,” in 39rd Eur. Microw. Conf., Oct. 2009, vol. 1, pp. 496–499.

[2] A. Adahl and H. Zirath, “A 1 GHz class E LDMOS power amplifier,” in 33rd Eur. Microw. Conf., Oct. 2003, vol. 1, pp. 285–288. [3] D. Kang, D. Kim, J. Choi, J. Kim, Y. Cho, and B. Kim, “A multimode/multiband power amplifier with a boosted suply modulator,” IEEE Trans. Microw. Theory Tech., vol. 58, no. 10, pp. 2598–2608, Oct. 2010. [4] J. Kang, D. Yu, K. Min, and B. Kim, “A ultra-high PAE Doherty amplifier based on 0.13-mm CMOS process,” IEEE Microw. Wireless Compon. Lett., vol. 16, no. 9, pp. 505–507, Sep. 2006. [5] M. Pelk, W. Neo, J. Gajadharsing, R. Pengelly, and L. de Vreede, “A high-efficiency 100-W GaN three-way Doherty amplifier for base-station applications,” IEEE Trans. Microw. Theory Tech., vol. 56, no. 7, pp. 1582–1591, Jul. 2008. [6] G. Hanington, P.-F. Chen, P. M. Asbeck, and L. E. Larson, “Highefficiency power amplifier using dynamic power-supply voltage for CDMA applications,” IEEE Trans. Microw. Theory Tech., vol. 47, no. 8, pp. 1471–1476, Aug. 1999. [7] J. Jeong, D. Kimball, M. Kwak, P. Draxler, C. Hsia, C. Steinbeiser, T. Landon, O. Krutko, L. Larson, and P. Asbeck, “High-efficiency WCDMA envelope tracking base-station amplifier implemented with GaAs HVHBTs,” IEEE J. Solid-State Circuits, vol. 44, no. 10, pp. 2629–2639, Oct. 2009. [8] J. Qureshi, M. Pelk, M. Marchetti, W. Neo, J. Gajadharsing, M. van der Heijden, and L. de Vreede, “90-W peak power GaN outphasing amplifier with optimum input signal conditioning,” IEEE Trans. Microw. Theory Tech., vol. 57, no. 8, pp. 1925–1935, Aug. 2009. [9] F. H. Raab, “High-efficiency linear amplification by dynamic load modulation,” in Proc. IEEE MTTS Int. Microw. Symp., 2003, pp. 1717–1720. [10] W. E. Neo, J. Lin, X. Liu, L. C. N. de Vreede, L. E. Larson, M. Spirito, M. Pelk, K. Buisman, A. Akhnoukh, A. de Graauw, and L. Nanver, “Adaptive multi-band multi-mode power amplifier using integrated varactor-based tunable matching network,” IEEE J. Solid-State Circuits, vol. 41, no. 9, pp. 2166–2177, Sep. 2006. [11] J. Fu and A. Mortazawi, “Improving power amplifier efficiency and linearity using a dynamically controlled tunable matching network,” IEEE Trans. Microw. Theory Tech., vol. 56, no. 12, pp. 3239–3244, Dec. 2008. [12] H. M. Nemati, C. Fager, U. Gustavsson, R. Jos, and H. Zirath, “Design of varactor-based tunable matching networks for dynamic load modulation of high power amplifier,” IEEE Trans. Microw. Theory Tech., vol. 57, no. 5, pp. 1110–1118, May 2009. [13] A. M. M. Mohamed, S. Boumaiza, and R. R. Mansour, “Novel reconfigurable fundamental/harmonic matching network for enhancing the efficiency of power amplifiers,” in Proc. Eur. Microw. Conf. Tech., Sep. 2009, pp. 1122–1125. [14] H. Cao, H. M. Nemati, A. S. Tehrani, T. Eriksson, J. Grahn, and C. Fager, “Linearization of efficiency-optimized dynamic load modulation transmitter architectures,” IEEE Trans. Microw. Theory Tech., vol. 58, no. 4, pp. 873–881, Apr. 2010. [15] H. M. Nemati, H. Cao, B. Almgren, T. Eriksson, and C. Fager, “Design of highly efficient load modulation transmitter for wideband cellular applications,” IEEE Trans. Microw. Theory Tech., vol. 58, no. 11, pp. 2820–2828, Nov. 2010. [16] P. Wright, J. Lees, J. Benedikt, P. J. Tasker, and S. C. Cripps, “A methodology for realizing high efficiency class-J in a linear and broadband PA,” IEEE Trans. Microw. Theory Tech., vol. 57, no. 12, pp. 3196–3204, Dec. 2009. [17] D. Wu, F. Mkadem, and S. Boumaiza, “Design of a broadband and highly efficient 45 W GaN power amplifier via simplified real frequency technique,” in Proc. IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2010, pp. 1090–1093. [18] P. Saad, C. Fager, H. Cao, H. Zirath, and K. Andersson, “Design of a highly efficient 2–4-GHz octave bandwidth GaN-HEMT power amplifier,” IEEE Trans. Microw. Theory Tech., vol. 58, no. 7, pp. 1677–1685, Jul. 2010. [19] K. Chen and D. Peroulis, “Design of highly efficient broadband class-E power amplifier using synthesized low-pass matching networks,” IEEE Trans. Microw. Theory Tech., vol. 59, no. 12, pp. 3162–3173, Dec. 2011. [20] “Agilent Technologies Inc.,” Santa Clara, CA [Online]. Available: http://www.agilent.com [21] F. H. Raab, “Electronically tunable class-E power amplifier,” in Proc. IEEE MTTS Int. Microw. Symp., 2001, pp. 1513–1516. [22] S. C. Cripps, RF Power Amplifier for Wireless Communications, 2nd ed. Boston, MA: Artech, 2006.

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.

[23] “Aeroflex/Metelics,” Londonderry, NH [Online]. Available: http://www.aeroflex.com/ams/metelics [24] “Skyworks Solution Inc.,” Woburn, MA [Online]. Available: http:// www.skyworksinc.com/ [25] R. G. Meyer and M. L. Stephens, “Distortion in variable-capacitance diodes,” IEEE J. Solid-State Circuits, vol. 10, no. SSC-1, pp. 47–54, Feb. 1975. [26] K. Buisman, L. C. N. de Vreede, L. E. Larson, M. Spirito, A. Akhnoukh, T. L. M. Scholtes, and L. Nanver, “Distortion-free varactor diode topologies for RF adaptivity,” in Proc. IEEE MTTS Int. Microw. Symp., 2005, pp. 157–160

Kenle Chen (S’10) received the Bachelor’s degree in communication engineering from Xi’an Jiaotong University, Xi’an, China, in 2005, the Master’s degree in electronics and information engineering from Peking University, Beijing, China, in 2008, and is currently working toward the Ph.D. degree at Purdue University, West Lafayette, IN. From 2007 to 2008, he was with the Institute of Micro Electronics, National Key Laboratory of Micro/Nano Fabrication, Peking University, where his research focused on RF MEMS switches, tunable filters and vacuum packaging. He is with the School of Electrical and Computer Engineering and Birck Nanotechnology Center, Purdue University. His research interests include broadband highly efficient PA design methodologies, adaptive PAs and transmitters, integration of PA and high- filter (codesign technique), and high power failure mechanisms of microwave devices. Mr. Chen was the recipient of the Third-Place Award of the Student High Efficiency Power Amplifier Design Competition in 2011 IEEE MTT-S International Microwave Symposium (IMS).

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Dimitrios Peroulis (S’99–M’04) received the Ph.D. degree in electrical engineering from the University of Michigan at Ann Arbor in 2003. He has been with Purdue University, West Lafayette, IN, since August 2003, where he leads the Adaptive Radio Electronics and Sensors (ARES) Team that focuses on reconfigurable analog/RF electronics for adaptive communications, signal intelligence, and harsh-environment sensors. He has been a PI/co-PI in over 40 projects funded by government agencies and industry in these areas. Since 2007, he has been a key contributor to the DARPA Analog Spectral Processors (ASP, Phases I–III) project resulting in the first widely tunable (tuning range 3:1) preselect radio filters with unprecedented quality factors and power handling ( 10 W) for high frequency applications (1–30 GHz). A wide variety of reconfigurable filters with simultaneously adaptable features including frequency, bandwidth, rejection level, filter order, and group delay have been demonstrated over the past four years. His group recently codeveloped a ground-breaking concept of field programmable filter arrays (FPFAs). Inspired by FPGAs in digital systems, FPFAs are based on a sea of coupled resonators and multiple ports in order to enable reutilization of the same adaptive resonators to support diverse needs for dissimilar systems. Arbitrary operational modes and multiple operational channels may be created and reconfigured at will. He has made significant advances in high-power high-efficient power amplifiers and RF CMOS ICs with high-efficiency antennas. In the areas of sensors, he has also demonstrated the first wireless battery-free high-temperature MEMS sensors for health monitoring of sensitive bearings in aircraft engines. These sensors continuously monitor (RFID-type) the true temperature of the bearing to over 300 C or 550 C (depending on the design) and wirelessly transmit it to a base station. These sensors are based on well-established silicon processing for low-cost high-yield manufacturing. They have demonstrated extremely robust operation for over 1-B cycles and continuous loading for over three months without failure. Prof. Peroulis’ team won third place in the student PA design competition at the 2011 International Microwave Symposium (IMS). He was assistant team leader to a student design team at Purdue University that won the first place awards in Phases I and II of the 2007–2008 SRC/SIA IC Design Challenge by demonstrating high-efficiency chip-to-chip wireless links with U-band transceivers. Further advances led to bondwire Yagi antenna arrays with efficiencies exceeding 80%.

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Design of a Concurrent Dual-Band 1.8–2.4-GHz GaN-HEMT Doherty Power Amplifier Paul Saad, Student Member, IEEE, Paolo Colantonio, Luca Piazzon, Franco Giannini, Kristoffer Andersson, Member, IEEE, and Christian Fager, Member, IEEE

Abstract—In this paper, the design, implementation, and experimental results of a high-efficiency dual-band GaN-HEMT Doherty power amplifier (DPA) are presented. An extensive discussion about the design of the passive structures is presented showing different possible topologies of the dual-band DPA. One of the proposed topologies is used to design a dual-band DPA in hybrid technology for the frequency bands 1.8 and 2.4 GHz with the second efficiency peak at 6-dB output power back-off (OBO). For a continuous-wave output power of 20 W, the measured power-added efficiency (PAE) is 64% and 54% at 1.8 and 2.4 GHz, respectively. At –dB OBO, the resulting measured PAEs were 60% and 44% in the two frequency bands. Linearized concurrent modulated measurement using 10-MHz LTE signal with 7-dB peak-to-average-ratio (PAR) at 1.8 GHz and 10-MHz WiMAX signal with 8.5-dB PAR at 2.4 GHz shows an average PAE of 34%, at an adjacent channel leakage ratio of 48 dBc and 46 dBc at 1.8 and 2.4 GHz, respectively. Index Terms—Doherty power amplifier (DPA), dual-band amplifier, dual-band matching networks, GaN-HEMT, high efficiency, power amplifier (PA).

I. INTRODUCTION

T

HE FAST development of wireless communication systems and the roll-out of new standards, such as Worldwide Interoperability for Microwave Access (WiMAX) and 4G Long Term Evolution (LTE), requires that the mobile radio base stations support multiple bands and process several types of standards [1]. Consequently there is an increasing demand of multiband, multistandard wireless transceivers able to simultaneously manage different types of signals. In this context, software-defined radio (SDR) is a feasible solution for reconfigurable radios, which can perform the same functions at different frequencies/modulations using the same hardware [2]. However, it is at the RF front-end stage that it becomes problematic to

Manuscript received September 30, 2011; revised January 31, 2012; accepted February 02, 2012. Date of publication April 03, 2012; date of current version May 25, 2012. This research has been carried out in the University of Roma Tor Vergata and in the GigaHertz Centre in a joint project financed by the Swedish Governmental Agency for Innovation Systems (VINNOVA), Chalmers University of Technology, ComHeat Microwave AB, Ericsson AB, Infineon Technologies Austria AG, Mitsubishi Electric Corporation, NXP Semiconductors BV, Saab AB, and SP Technical Research Institute of Sweden. P. Saad, K. Andersson, and C. Fager are with the Department of Microtechnology and Nanoscience, Chalmers University of Technology, 41296 Gothenburg, Sweden (e-mail: [email protected]). P. Colantonio, L. Piazzon, and F. Giannini are with the Department of Electronic Engineering, University of Rome Tor Vergata, 00133 Rome, Italy (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2012.2189120

satisfy the multiband/multistandard features. The power amplifier (PA) is a key component in multiband or multistandard solutions, since its performance strongly influence the overall system performance in terms of bandwidth, output power, and efficiency [3], [4]. Modulated signals in modern wireless communication systems have large amplitude variations, which results in high peak-to-average ratios (PARs), sometimes exceeding 10 dB. To prevent clipping of the signal peaks and thereby strong distortion of the transmitted information, the PA has to operate at an average output power far from the saturation region and hence, at low efficiency levels. Different techniques have been proposed to increase the average efficiency of power amplifiers for signals having high PAR. Envelope elimination and restoration (EER) [5], envelope tracking (ET) [6], Doherty amplifiers [7], and varactor-based dynamic load modulation [8] are the most common. The ease of configuration and the circuit simplicity give the Doherty power amplifier (DPA) many advantages over the other techniques. In DPA, high average efficiency is achieved by dynamically adapting the PA load impedance to keep the amplifier in compression during modulation [7], [9]–[11]. So far, a great deal of work has been done on narrowband DPAs, where the efficiency was improved at back-off operation and high-linearity performance was achieved with the help of digital predistortion techniques or by utilizing intermodulation cancellation [4], [11]–[20]. However, most of the published Doherty PAs were designed to work in a single band, and therefore they do not satisfy the multiband, multistandard requirements of the modern radio base stations. To overcome this major limitation, new design techniques have been used to increase the bandwidth of the DPA [21]–[24]. The drawback is that wideband DPAs do not always have ideal operation over the bandwidth of operation. This leads to significant degradation in the DPA performance compared to the case where DPAs are designed and optimized for single-frequency operation. Recently, there have been some efforts to optimize a DPA for dual-band operation. Unfortunately, the first prototype of a dual-band DPA reported in [25] was working in the first band only, due to intrinsic effects of device packaging in the second band. A working dual-band DPA, operating at 880 MHz and 1.96 GHz, was proposed in [26], and recently a linearization solution for such amplifier was proposed in [27]. In this paper, a detailed design methodology for a high-efficiency dual-band DPA is reported and validated successfully by state-of-the-art experimental results. The procedure is based on load-pull/source-pull simulation approach together with a

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TABLE I STATE-OF-THE-ART SINGLE-BAND AND DUAL-BAND DPAS. PRESENTED VALUES ARE FOR “BREAK” AND “SATURATION” CONDITIONS

Fig. 2. Dual-band ITN. The load

Fig. 1. Conventional DPA topology. Main and Auxiliary amplifiers.

and

are the loads seen by the

comprehensive design of the passive structures of the DPA. Comparison between the performance of the presented DPA with recently published single-band and dual-band DPAs are summarized in Table I. The dual-band DPA shows similar or even better performance when compared with single-band DPAs, because the design is optimized for the two frequency bands without any significant tradeoff. The comparison with recently published dual-band DPAs shows the superior performance of the designed DPA and thereby demonstrates the usefulness of the proposed approach for the design of DPAs for future wireless systems. This paper is organized as follows. In Section II, the description of conventional Doherty architecture and the design issues and approaches for a dual band design are extensively discussed. In Section III, the design strategy is presented, while the designed dual-band DPA is discussed in Section IV. The experimental results are presented in Section V, and conclusions are given in Section VI. II. DESIGN ISSUES IN A DUAL-BAND DPA The architecture and operation principle of DPAs have been thoroughly discussed in the literature [7], [13], [15], [30]. Fig. 1 shows a block diagram of a conventional DPA, which is composed of the combination of two PAs (main and auxiliary), an input power splitter (IPS), a phase compensation network (PCN), an impedance inverter network (IIN), and an impedance transformer network (ITN) at the output to match towards 50terminations. The main amplifier is usually biased in Class-AB, while the auxiliary amplifier is biased in Class-C. The main and auxiliary amplifiers are combined through the IIN, usually implemented

is transformed to a resistance

.

using a quarter-wave transmission line, with the aim to modulate the load impedance of the main amplifier through the current supplied by the auxiliary amplifier into the external load [4]. Thus, the DPA operates at a nearly constant efficiency for a targeted output power back-off (OPO) range, typically of 6 dB. In order to obtain a dual-band operation in a DPA, the passive structures, such as main and auxiliary matching networks, IPS, PCN, IIN, and ITN, must be designed to ensure Doherty behavior simultaneously in both frequency bands. The different possible dual-band implementations for each passive structure are presented in this section. As will be pointed out, the dual-band DPA designer has to be careful when combining the different dual-band structures used to realize the DPA since some of these structures are incompatible. A. Impedance Transformer Network The ITN is used to transform the output load (50 ) to the required resistance value at the DPA common node (C.N.) as shown in Fig. 1. In [31], it is shown that a transformer with two sections can achieve ideal impedance matching at two arbitrary frequencies. The transformer scheme, shown in Fig. 2, is represented by two transmission lines with characteristic impedances and electrical lengths , respectively. The design equations to transform a resistive load to a different resistive load , at two simultaneous frequencies and are presented in [31]. B. Impedance Inverter Network The IIN must function as a quarter-wave transmission line, at the two frequency bands, independently of the termination impedance. However, the dual-section transformer discussed above cannot be used because it behaves as a quarter-wave impedance transformer only for fixed value of the load . An example is given to support this statement. Assuming 25 and 100 , and the two operating frequencies 1.8 GHz and GHz, then this results in transmission lines having 69.3 36.1

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Fig. 3. Simulated input impedance former shown in Fig. 2.

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of the dual-band impedance trans-

the branch-line coupler (BLC) [33] are the most used power dividers to equally or unequally divide the input power. The main difference between the two dividers is the phase relationship between the output ports. The Wilkinson divides the output power in phase while the BLC introduces a 90 phase shift. In principle, to create a dual-band divider [35], [32], it is sufficient to replace each quarter-wave transmission line with the equivalent dual-band T- or -network shown in Fig. 4. Usually the dual-band approaches for the IPS design are narrowband solutions, whose matching and coupling factors are strictly frequency-dependent. To reduce the design sensitivity related to practical frequency shifts occurring in the realization of the other passive networks, a wideband topology for the IPS is preferred because it ensures satisfactory matching condition in the vicinity of the selected operating frequencies. However, the separation between the operating bands can create a limitation for using a wideband topology since it is challenging to design such splitter for band separation greater than one octave. In the latter case, a dual-band BLC should be adopted to overcome this limitation. D. Phase Compensation Network

Fig. 4. Dual-band impedance inverter network. (a) T-network. (b)

-network.

and 68.3 . Moreover, assuming that the input impedance is now doubled to 50 (for example, as happens at the common node C.N. in Fig. 1), the load at the other point (e.g., at the main output) becomes complex at the two frequencies, as depicted in Fig. 3. Consequently, the examined structure cannot realize a proper dual-band IIN for the main device output, while its use as dual-band ITN at the DPA output remains valid. To realize a dual-band IIN, for a correct load modulation in the DPA architecture, different structures are required. In [32], it is shown that an equivalent quarter-wavelength transmission line of characteristic impedance , at two incommensurate frequencies and , can be realized by using a T- or a -network, as shown in Fig. 4. The design equations for both the T-network and -network are given in [32] as function of the operating frequencies and and of the equivalent characteristic impedance . Moreover, due to the periodical behavior of these structures, the solution depends also by two integers and [33] that should be selected for physical constraints, i.e., realizability and dimension of the resulting transmission lines. Finally, the phase response of the IIN may be different at the operating frequencies, depending on the selected topology and value of [25], [33]. As a consequence, to ensure proper Doherty operation, the phase shift introduced at the two frequencies by the IIN has to be compensated by a suitable IPS-PCN structure. C. Input Power Splitter To compensate for the different turn-on behaviors of the main and auxiliary amplifiers, the input power should be split unevenly [13], [18]. Consequently, a wideband or dual-band uneven power splitter is required. The Wilkinson divider [34] and

To ensure in-phase addition of the output signals from the main and auxiliary amplifiers at the common node (C.N.), the phase response introduced by the output IIN has to be properly compensated for in the auxiliary branch. Such a compensation must be performed taking into account for the phase response of the input power splitter. In fact, if such an IPS is realized through a BLC, then the phase compensation is directly integrated in this element, providing the correct output port connections. Conversely, if Wilkinson structure is adopted, then a suitable PCN is required at the input of the Auxiliary or Main amplifiers. In these cases, the required PCN network can be realized by using one of the dual-band structures presented in Section II-A. E. Dual-Band DPA Topologies Here, the possible configurations to implement a dual-band DPA will be enumerated. The configuration that most closely resembles the general topology shown in Fig. 1 is certainly the one that requires the presence of a dual-band Wilkinson input divider, two dual-band quarter-wave transmission lines to realize the IIN and the PCN, and a two-section transformer to realize the ITN. However, in this case, the overall structure of the DPA is very cumbersome, due to the simultaneous presence of a dual-band Wilkinson divider and two impedance inverters. A more compact solution can be obtained adopting a branch-line splitter, whose phase relation of the outgoing signals avoids the need of the phase shifter at the input of the auxiliary amplifier. However, the designer must pay attention to the structures adopted for the realization of branch-line and IIN to allow a proper phase relation between main and auxiliary branches. Again, referring to the discussion above, the possible configurations for realizing dual-band DPA are summarized in Table II. III. DUAL-BAND DPA DESIGN The design of a dual-band DPA for 1.8 and 2.4 GHz is presented here. These frequencies are arbitrarily chosen and the

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TABLE II DUAL-BAND DPA CONFIGURATIONS

Fig. 5. Simulated optimum load impedances of the main device at the transistor output reference plane.

TABLE III MAIN, AUXILIARY, AND DOHERTY AMPLIFIER DESIGN PARAMETERS

Fig. 6. Simulated optimum source impedances of the main device at the transistor input reference plane.

TABLE IV ELEMENT VALUES OF THE REALIZED BLC

presented design approach is applicable to any desired combination of two frequency bands. For both main and auxiliary amplifiers, a 3.6-mm GaN bare-die device, Cree CGH60015DE [36], has been used. The device has a breakdown voltage of 100 V, a knee voltage of 5 V, a pinch-off voltage of 3.2 V, and a saturation drain current of 2.3 A, approximately. A nonlinear model of the device, supplied by the manufacturer and optimized for Class-AB biasing condition, has been used for the design. The DPA parameters have been theoretically inferred from the dc– - curves of the device by applying the design approach in [13]. The values of the design parameters and their symbols are listed in Table III, where “Break” refers to the turn-on of the auxiliary device, and “Saturation” refers to the saturation of the DPA. It is important to stress that the parameters reported in Table III are numerically computed by the device data mentioned above and not related to the frequency of operation. Moreover, the parameters , and refer to the intrinsic current source of the active device [13], while refers to the resistance at the output connection node. A. Matching Networks The first step to design the dual-band main PA was to perform load/source-pull simulations to find the optimum load and source impedances fulfilling the intrinsic load conditions (i.e., at the device intrinsic current source), reported in Table III:

and , at 1.8 and 2.4 GHz, respectively. Since the efficiency of the Doherty amplifier at the break condition is equal to that of the Class-AB PA, to further improve the efficiency, harmonic load-pull/source-pull simulations were performed to find the second- and third-harmonic load impedances of 1.8 and 2.4 GHz. The simulations have shown that the effects of the second harmonic at the input and the third harmonic at the output on the efficiency was very small. Therefore, and in order to decrease the complexity of the matching networks, only the fundamental and the second harmonic have been considered in the design of the output matching network, while only the fundamental frequencies have been considered in the design of the input matching network. The resulting optimum load impedances at fundamental and second harmonic frequencies, at break and saturation conditions, are shown in Fig. 5. The stars represent the purely resistive loading values at the device intrinsic reference plane (i.e., across the device output current source). The empty symbols are the loads identified by load/ source-pull simulations, while the filled symbols are the final impedance values synthesized by a distributed approach [37]. Similarly, in Fig. 6 are reported the optimum source impedances at fundamental frequencies at the break and saturation conditions, identified by load/source-pull simulations (stars) and realized by a distributed approach (filled circle), at the two operating frequencies. In the design of the input matching network,

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Fig. 10. Simulated and measured phase difference between two quadrature outputs. Fig. 7. Photograph of the realized wideband Branch Line Coupler.

Fig. 8. Simulated and measured

and

of the BLC.

Fig. 11. Simulated -parameters of: (a) ITN and (b) IIN.

TABLE V ELEMENT VALUES OF THE IIN AND ITN

B. Branch-Line Coupler

Fig. 9. Simulated and measured

and

of the BLC.

a 56- series resistance in parallel with a 2.4 pF capacitance and a 270- shunt resistance are added in order to ensure the small signal stability of the DPA.

In this design, due to the fact that the two operating frequencies are separated by 600 MHz only, a wideband BLC design was adopted instead of a dual-band BLC. The design approach adopted is based on the conventional wideband BLC proposed in [38]. Considering that the proposed BLC in [38] is for equal power division, the characteristic impedances of the transmission lines have been optimized to infer the desired splitting factor given in Table III. For the realization, using the Rogers 5870 substrate with and thickness of 0.8 mm, the resulting element parameters are summarized in Table IV, while the photograph of the realized BLC is shown in Fig. 7. Figs. 8 and 9 show the simulated and measured -parameters of the manufactured BLC. As can be noted, the measured

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Fig. 12. Dual-band DPA circuit diagram.

return loss and isolation are better than 24 and 25 dB at 1.8 and 2.4 GHz, respectively. The magnitude of the measured insertion loss are 3.5 dB and 2.8 dB at 1.8 Hz and 2.4 GHz. These measurements satisfy the required splitting factor, reported in Table III, where 45% ( 3.5 dB) of the input power must go to the main amplifier, while 55% ( 2.8 dB) goes to the auxiliary. Fig. 10 reports measured and simulated phase response of the fabricated coupler. The phase differences between the output ports are 90.1 at 1.8 GHz and 90.2 at 2.4 GHz. C. Impedance Transformation and Inverting Networks As shown in Table III, an ITN that transforms the standard at 1.8 and 2.4 GHz is re50- termination load to quired. Therefore, the two section dual-band impedance transformer discussed in Section II-B is adopted. Conversely, for the IIN, the selected structure should introduce the same phase-shift imposed by the BLC at the two operating frequencies. Moreover, referring to Table III, the IIN must have a characteristic impedance of 26 . The designed BLC has phase-shift at both operating frequencies (Fig. 10). Fig. 11 shows the simulation results of the designed ITN and IIN. As can be noted, the ITN performs the impedance transformation from 50 to a resistive value 13 at 1.8 GHz and 2.4 GHz, while having a negligible imaginary part. Similarly, the IIN realizes the required impedance transformation. In fact, for 13 the transformed impedance is 52 (required 58 ) at both frequencies, with a negligible imaginary part. When 26 , the transformed impedance becomes 26 (as required) with negligible imaginary part, at both frequencies again. The resulting element parameters of the IIN and ITN networks are summarized in Table V. IV. DUAL-BAND DPA IMPLEMENTATION The same structure adopted for the main amplifier was replicated for the auxiliary and connected through the BCL and ITN

Fig. 13. Performance variation during Monte Carlo simulations of the dualband DPA.

at the input and output, respectively. The resulting circuit diagram of the complete designed dual-band DPA is shown in Fig. 12. The space between the transistor and the PCB lines is reduced as much as possible by careful alignment to avoid undesirable parasitics that will reduce the bandwidth. Two inductances and are used to model the input and output bond-wire inductances, respectively, whose values were estimated to be 0.15 nH each. A dual-band design approach has been adopted in the design of the matching networks. The impedance buffer methodology, already proposed in [37], has been used for the matching of harmonics. Such an approach allows arbitrary reactive loads to be synthesized for an unlimited number of arbitrary frequencies. The output matching network consists of two subnetworks, used to control the second-harmonics loading conditions (the distributed network surrounded by the dashed rectangle in Fig. 12) and the two fundamental impedances (solid rectangle). For the harmonics, the parallel short-circuited stub at the output provides a short circuit at at the connecting point A, while the parallel open-circuited stub provides

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Fig. 14. Photograph of the implemented dual-band DPA.

a short circuit at at the connecting point B. This way, the optimization of fundamental and second harmonic impedances can be performed independently. The widths and lengths of and are used for realizing the required second harmonic impedances of and at the output. Taking into account the effect of the network controlling the harmonics, a dual-band ad hoc matching network, (dashed box in Fig. 12), has been designed and optimized to provide the matching at the two fundamental frequencies and . The input matching network consists of the stabilizing network (dashed box) and the distributed network surrounded by the solid rectangle designed to provide the input matching simultaneously at the two fundamental frequencies and . In order to study the impact of components variability and uncertainty on the DPA performance, Monte Carlo simulations have been performed. In these simulations, the uncertainties introduced by the manufacturing process, the lumped components, and 100-mV dc bias points of the main and auxilary devices have been considered. As shown in Fig. 13), the design is robust and not very sensitive to these deviations. The variations of the PAE and gain are less than 5% and 0.5 dB, respectively. The PA was implemented on a Rogers 5870 substrate with and thickness of 0.8 mm. Its size is 30 10 cm . A photograph of the manufactured dual-band DPA, using bare-die GaN-HEMT CGH60015DE devices, is shown in Fig. 14. V. MEASUREMENT RESULTS The DPA has been characterized by small-signal, large-signal, and modulated measurements to evaluate its performance. A. Small-Signal Measurements The realized dual band DPA was characterized in small signal conditions (S-parameters) to check its frequency behavior. A drain bias of 28 V was used for both devices. The main amplifier was biased for a quiescent drain current of 150 mA (gate voltage of 3.0 V) while the auxiliary amplifier was biased below pinch-off (gate voltage of 5.5 V). The measured and simulated -parameters are reported in Fig. 15, showing a very good agreement. The input match is better than 10 dB between 1.8 and 2.4 GHz due to the wideband BLC at the input. Moreover, the measurement shows the correct behavior of the

Fig. 15. Measured and simulated -parameters of the realized dual band DPA.

DPA in the vicinity of 1.8 and 2.4 GHz, with roughly 14 dB of small signal gain . B. Large-Signal Measurements Large-signal continuous wave (CW) measurements have been performed in order to evaluate the dual-band DPA under steady-state conditions. In this measurement, the same biasing, as for the -parameters measurement, is used. Under these conditions, about 27 dBm of input power was required to turn on the auxiliary device. The DPA was first characterized versus frequency between 1.6 and 2.6 GHz to study its frequency response under largesignal conditions. Fig. 16 shows simulated and measured drain efficiency and output power versus frequency of the dual-band DPA under a constant input power of 33 dBm, corresponding to saturated operation. From Fig. 16, it can be noted that the frequency response of the DPA is well predicted by simulations. The measured output power is slightly higher than 43 dBm in the two bands, with a measured drain efficiency of 69% at 1.8 GHz and 61% at 2.4 GHz. The drain efficiency is maintained higher than 55% in 150-MHz bandwidth around the 1.8-GHz band and in 100-MHz bandwidth around the 2.4-GHz band.

SAAD et al.: DESIGN OF CONCURRENT DUAL-BAND 1.8–2.4-GHz GaN-HEMT DPA

Fig. 16. Measured and simulated drain efficiency and gain of the DPA versus frequency at a fixed input power of 33 dBm.

Fig. 17. Measured PAE and gain of the DPA versus output power at the two operating bands.

Fig. 17 shows measured power gain and power-added efficiency (PAE) versus output power at 1.8 and 2.4 GHz, respectively. It can be easily noticed that a Doherty region resulting in high, almost constant, efficiency across the OBO range of 6 dB is observed. For the 1.8-GHz band, the measured PAE is 64% at an output power of 43 dBm and 60% at an output power of 37 dBm (6 dB OBO). Similarly, for the 2.4-GHz band, a 54% of PAE is measured at 43-dBm output power and 44% at 6 dB OBO. The gain compression in the Doherty region is limited to 1 dB for 1.8 GHz and 1.2 dB for 2.4 GHz. C. Modulated Measurements Linearized modulated measurements have been performed to show that the DPA has the capability of being linearized and to evaluate its performance when used with modern wireless communication signals. The linearized modulated measurements were performed using the memory polynomial model with nonlinear order 7 and memory depth 3 [39]. The DPA was tested first in nonconcurrent mode using one modulated signal at

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Fig. 18. PA output signal spectrum of a 10-MHz LTE signal at center frequency of 1.8 GHz before and after digital predistortion.

Fig. 19. PA output signal spectrum of a 10-MHz WiMAX signal at center frequency of 2.4 GHz before and after digital predistortion.

the time. The signals used are 5-MHz WCDMA, 10-MHz LTE signals both with 7-dB PAR, and WiMAX signal with 8.5-dB PAR. Then, the DPA was tested in concurrent mode where two modulated signals are applied at the input of the DPA at the same time. The linearization was performed with the 2-D-DPD technique presented in [27]. In the first experiment, the WCDMA and the LTE signals were applied at 1.8 and 2.4 GHz bands, respectively. In the second experiment, the LTE signal is applied at 1.8-GHz band while the WiMAX signal is applied at the 2.4-GHz band. The measured output spectrum at 1.8 and 2.4 GHz (second experiment), before and after DPD, for an average input power of 22 dBm, are shown in Figs. 18 and 19, respectively. Average output power, PAE, and ACLR, with and without DPD of all experiments, at the two operating bands, are summarized in Table VI. As expected, we notice that in concurrent mode the average PAE is degraded by 10%–20% compared with the case where the PA is driven by one modulated signal at the time. However, these results show that standard DPD methods

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TABLE VI AVERAGE POUT, AVERAGE PAE, AND ACLR

can be used to linearize the DPA in nonconcurrent and concurrent modes to meet modern wireless communication system standards. VI. CONCLUSION In this paper, an extensive design procedure for highly efficient dual-band DPAs has been presented. In particular, the procedure concentrates on the design of the passive structures, presenting several possible topologies for the dual-band DPA. Moreover, the procedure uses a load/source-pull methodology combined with second harmonic tuning to maximize the efficiency performance. The proposed design procedure has been demonstrated by implementing a hybrid GaN-HEMT dual-band DPA. The success of the presented method was verified by experimental results that show, at 1.8 GHz, a PAE between 60% and 64% in a 6-dB OBO for CW measurement. At 2.4 GHz and for the same OBO, a PAE between 44% and 54% was recorded. The measured saturated output power exceeds 43 dBm in both bands. Moreover, linearized concurrent modulated measurements using 5-MHz WCDMA and 10-MHz LTE and WiMAX signals demonstrate that the DPA achieves high average efficiency in both bands and can easily be linearized to meet wireless communication systems standards. The excellent performances obtained demonstrate the advantage and potential of the proposed approach for the design of dual-band DPAs for future wireless systems, combining multiband, high-efficiency, and linearity design techniques. ACKNOWLEDGMENT The authors would like to thank H. Cao, Department of Microtechnology and Nanoscience, Chalmers University of Technology, Gothenburg, Sweden, and J. Moon, Department of Electrical Engineering, Pohang University of Science and Technology (POSTECH), Pohang, Korea, for their technical support during measurements. REFERENCES [1] J.-M. Chung, K. Park, T. Won, W. Oh, and S. Choi, “New protocols for future wireless systems,” in Proc. 53rd IEEE Int. Midwest Symp. Circuits Syst., Aug. 2010, pp. 692–695.

[2] H. Arslan, Cognitive Radio, Software Defined Radio, and Adaptive Wireless Systems. Berlin, Germany: Springer, 2007. [3] S. C. Cripps, RF Power Amplifiers for Wireless Communications. Norwood, MA: Artech House, 2006. [4] P. Colantonio, F. Giannini, and E. Limiti, High Efficiency RF and Microwave Solid State Power Amplifiers. Hoboken, NJ: Wiley, 2009. [5] F. Raab, “Intermodulation distortion in Kahn-technique transmitters,” IEEE Trans. Microw. Theory Tech., vol. 44, no. 12, pp. 2273–2278, Dec. 1996. [6] F. Raab, P. Asbeck, S. Cripps, P. Kenington, Z. Popovic, N. Pothecary, J. Sevic, and N. Sokal, “Power amplifiers and transmitters for RF and microwave,” IEEE Trans. Microw. Theory Tech., vol. 50, no. 3, pp. 814–826, Mar. 2002. [7] W. Doherty, “A new high efficiency power amplifier for modulated waves,” Proc. Inst. Radio Engineers, vol. 24, no. 9, pp. 1163–1182, Sep. 1936. [8] H. Nemati, C. Fager, U. Gustavsson, R. Jos, and H. Zirath, “Design of varactor-based tunable matching networks for dynamic load modulation of high power amplifiers,” IEEE Trans. Microw. Theory Tech., vol. 57, no. 5, pp. 1110–1118, May 2009. [9] S. C. Cripps, Advanced Techniques in RF Power Amplifiers Design. Norwood, MA: Artech House, 2002. [10] P. B. Kenington, High-Linearity RF Amplifier Design. Norwood, MA: Artech House, 2000. [11] M. Iwamoto, A. Williams, P.-F. Chen, A. Metzger, C. Wang, L. Larson, and P. Asbeck, “An extended Doherty amplifier with high efficiency over a wide power range,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2001, vol. 2, pp. 931–934. [12] A. Markos, P. Colantonio, F. Giannini, R. Giofré, M. Imbimbo, and G. Kompa, “A 6 W uneven Doherty power amplifier in GaN technology,” in Proc. 37th Eur. Microw. Conf., Oct. 2007, pp. 1097–1100. [13] P. Colantonio, F. Giannini, R. Giofrè, and L. Piazzon, “The AB-C Doherty power amplifier. Part I: Theory,” Int. J. Microw. Comput.-Aided Eng., vol. 19, no. 3, pp. 293–306, 2009. [14] K. Cho, W. Kim, S. Stapleton, J. Kim, B. Lee, J. Choi, and J. Kim, “Gallium-nitride microwave Doherty power amplifier with 40 W PEP and 68% PAE,” Electron. Lett., vol. 42, no. 12, pp. 704–705, Jun. 2006. [15] P. Colantonio, F. Giannini, R. Giofrè, and L. Piazzon, “The AB-C Doherty power amplifier. Part II: Validation,” Int. J. Microw. Comput.Aided Eng., vol. 19, no. 3, pp. 307–316, 2009. [16] Y.-S. Lee, M.-W. Lee, and Y.-H. Jeong, “Unequal-cells-based GaN HEMT Doherty amplifier with an extended efficiency range,” IEEE Microw. Wireless Compon. Lett., vol. 18, no. 8, pp. 536–538, Aug. 2008. [17] O. Hammi, J. Sirois, S. Boumaiza, and F. Ghannouchi, “Design and performance analysis of mismatched Doherty amplifiers using an accurate load-pull-based model,” IEEE Trans. Microw. Theory Tech., vol. 54, no. 8, pp. 3246–3254, Aug. 2006. [18] B. Kim, J. Kim, I. Kim, J. Cha, and S. Hong, “Microwave doherty power amplifier for high efficiency and linearity,” in Proc. Int. Workshop Integr. Nonlinear Microw. Millimeter-Wave Circuits, Jan. 2006, pp. 22–25. [19] J. Kim, J. Moon, Y. Y. Woo, S. Hong, I. Kim, J. Kim, and B. Kim, “Analysis of a fully matched saturated Doherty amplifier with excellent efficiency,” IEEE Trans. Microw. Theory Tech., vol. 56, no. 2, pp. 328–338, Feb. 2008.

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[20] A. Markos, K. Bathich, F. Golden, and G. Boeck, “A 50 W unsymmetrical GaN Doherty amplifier for LTE applications,” in Proc. 40th Eur. Microw. Conf., Sep. 2010, pp. 994–997. [21] Y.-S. Lee, M.-W. Lee, S.-H. Kam, and Y.-H. Jeong, “A new wideband distributed Doherty amplifier for WCDMA repeater applications,” IEEE Microw. Wireless Compon. Lett., vol. 19, no. 10, pp. 668–670, Oct. 2009. [22] J. Qureshi, L. Nan, E. Neo, F. Rijs, I. Blednov, and L. de Vreede, “A wideband 20 W LDMOS Doherty power amplifier,” in IEEE MTT-S Int. Microw. Symp. Dig., May 2010, pp. 1–4. [23] J. Kim, J. Son, J. Moon, and B. Kim, “A saturated Doherty power amplifier based on saturated amplifier,” IEEE Microw. Wireless Compon. Lett., vol. 20, no. 2, pp. 109–111, Feb. 2010. [24] K. Bathich, A. Markos, and G. Boeck, “Frequency response analysis and bandwidth extension of the Doherty amplifier,” IEEE Trans. Microw. Theory Tech., vol. 59, no. 4, pp. 934–944, Apr. 2011. [25] P. Colantonio, F. Feudo, F. Giannini, R. Giofrè, and L. Piazzon, “Design of a dual-band GaN Doherty amplifier,” in Proc. 18th Int. Conf. Microw. Radar Wireless Commun., Jun. 2010, pp. 1–4. [26] X. Li, W. Chen, Z. Zhang, Z. Feng, X. Tang, and K. Mouthaan, “A concurrent dual-band Doherty power amplifier,” in Proc. Asia–Pacific Microw. Conf. Proc., Dec. 2010, pp. 654–657. [27] W. Chen, S. A. Bassam, X. Li, Y. Liu, K. Rawat, M. Helaoui, F. M. Ghannouchi, and Z. Feng, “Design and linearization of concurrent dual-band Doherty power amplifier with frequency-dependent power ranges,” IEEE Trans. Microw. Theory Tech., vol. 59, no. 10, pp. 2537–2546, Oct. 2011. [28] L. Yong-Sub, L. Mun-Woo, and J. Yoon-Ha, “High-efficiency class-Ecells-based GaN HEMT Doherty amplifier for WCDMA applications,” in Proc. 38th Eur. Microw. Conf., Oct. 2008, pp. 428–431. [29] A. Markos, K. Bathich, F. Golden, and G. Boeck, “A 50 W unsymmetrical GaN Doherty amplifier for LTE applications,” in Proc. 40th Eur. Microw. Conf., Sep. 2010, pp. 994–997. [30] B. Kim, J. Kim, I. Kim, and J. Cha, “The doherty power amplifier,” IEEE Microw. Mag., vol. 7, no. 5, pp. 42–50, Oct. 2006. [31] C. Monzon, “A small dual-frequency transformer in two sections,” IEEE Trans. Microw. Theory Tech., vol. 51, no. 4, pp. 1157–1161, Apr. 2003. [32] H. Zhang and K. J. Chen, “A stub tapped branch-line coupler for dualband operations,” IEEE Microw. Wireless Compon. Lett., vol. 17, no. 2, pp. 106–108, Feb. 2007. [33] D. M. Pozar, Microwave Engineering. New York: Wiley, 2005. [34] E. Wilkinson, “An N-way hybrid power divider,” IRE Trans. Microw. Theory Tech., vol. MTT-8, no. 1, pp. 116–118, Jan. 1960. [35] A. Mohra, “Compact dual band Wilkinson power divider,” in Proc. Nat. Radio Sci. Conf., Mar. 2008, pp. 1–7. [36] “CGH60015D datasheet,” Cree Inc. [Online]. Available: http://www. cree.com/products/pdf/CGH60015D.pdf Durham, USA, [Online]. Available [37] P. Colantonio, F. Giannini, R. Giofrè, and L. Piazzon, “A design technique for concurrent dual band harmonic tuned power amplifier,” IEEE Trans. Microw. Theory Tech., vol. 56, no. 11, pp. 2545–2555, Nov. 2008. [38] M. Muraguchi, T. Yukitake, and Y. Naito, “Optimum design of 3-Db branch-line couplers using microstrip lines,” IEEE Trans. Microw. Theory Tech., vol. MTT-31, no. 8, pp. 674–678, Aug. 1983. [39] J. Kim and K. Konstantinou, “Digital predistortion of wideband signals based on power amplifier model with memory,” Electron. Lett., vol. 37, no. 23, pp. 1417–1418, Nov. 2001.

Paul Saad (S’09) received the B.S. degree in electrical engineering from the Lebanese University, Beirut, Lebanon, in 2005, and the M.S. degree in RF and microwave engineering from the University of Gävle, Gävle, Sweden, in 2007. He is currently working toward the Ph.D. degree at the GigaHertz Centre, Microwave Electronics Laboratory, Chalmers University of Technology, Göteborg, Sweden. His research concerns the design of high-efficiency multiband and wideband power amplifiers. Mr. Saad was the recipient of the 2009 Certificate of High Achievement and the 2010 First Place Award of the Student High Efficiency Power Amplifier

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Design Competition of the IEEE Microwave Theory and Techniques Society (IEEE MTT-S) International Microwave Symposium. Paolo Colantonio was born in Rome, Italy, on March 22, 1969. He received the degree in electronic engineering and Ph.D. degree in microelectronics and telecommunications from the University of Rome “Tor Vergata,” Rome, in 1994 and 2000, respectively. In 1999, he became a Research Assistant with the University of Rome “Tor Vergata,” Rome, Italy, where, since 2002, he has been a Professor of microwave electronics. He authored or coauthored more than 140 scientific papers. His main research activities are in the field of nonlinear microwave circuit design methodologies, nonlinear analysis techniques, and modeling of microwave active devices. Luca Piazzon was born in Frascati, Italy, in 1982. He received the B.S. degree in electronic engineering from the University of Rome “Tor Vergata,” Rome, Italy, in 2007, where he is currently working toward the Ph.D. degree. His current research interests include RF power amplifier theory, design and test, linearization techniques, and efficiency-improving methodologies.

Franco Giannini was born in Galatina, Italy, on November 9, 1944. He received the Electronics Engineering degree (summa cum laude) from the University of Roma “La Sapienza,” Rome, Italy, in 1968. Since 1980, he has been a Full Professor of applied electronics with the University of Rome “Tor Vergata,” Rome, Italy. Since 2001, he has been an Honorary Professor with the Warsaw University of Technology (WUT), Warsaw, Poland. He has been involved with problems concerning modeling, characterization, and design methodologies of linear and nonlinear active microwave components, circuits, and subsystems, including MMICs. He is a consultant for various national and international industrial and governmental organizations, including the International Telecommunication Union and the European Union. He has authored or coauthored over 430 scientific papers. Prof. Giannini is a member of the Board of Directors of the Italian Space Agency (ASI). He is president of the GAAS Association. He has also been a member of numerous committees of international scientific conferences. He was the recipient of the Doctor Honoris Causa degree from the WUT in 2008. Kristoffer Andersson (S’03–M’06) received the M.Sc. and Ph.D. degrees in electrical engineering from Chalmers University of Technology, Göteborg, Sweden, in 2001 and 2006, respectively. His research interests are in the area of characterization and modeling of wide-bandgap transistors.

Christian Fager (M’03) received the M.Sc. and Ph.D. degrees in electrical engineering and microwave electronics, from Chalmers University of Technology, Göteborg, Sweden, in 1998 and 2003, respectively. He is currently an Associate Professor and project leader with the GigaHertz Centre, Microwave Electronics Laboratory, Chalmers University of Technology, Göteborg, Sweden. His research interests are in the areas of large signal transistor modeling and high efficiency power amplifier architectures. Dr. Fager was the recipient of the Best Student Paper Award at the IEEE Microwave Theory and Techniques Society (IEEE MTT-S) International Microwave Symposium in 2002.

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Design of a Wideband High-Voltage High-Efficiency BiCMOS Envelope Amplifier for Micro-Base-Station RF Power Amplifiers Myoungbo Kwak, Student Member, IEEE, Donald F. Kimball, Member, IEEE, Calogero D. Presti, Member, IEEE, Antonino Scuderi, Member, IEEE, Carmelo Santagati, Jonmei J. Yan, Student Member, IEEE, Peter M. Asbeck, Fellow, IEEE, and Lawrence E. Larson, Fellow, IEEE

Abstract—A high-performance bipolar-CMOS-DMOS (BCD) monolithic envelope amplifier for micro-base-station power amplifiers (PAs) is presented. Measurement of the BCD high-voltage V envelope amplifier shows an efficiency of 72% using 7.7-dB peak-to-average ratio WCDMA input signals at an average envelope amplifier output power above 3 W. A WCDMA envelope-tracking RF PA at 2.14 GHz, including a GaN field-effect transistor RF stage, has an overall drain efficiency above 51%, with a normalized power root-mean-square error below 1.2% and an adjacent channel leakage ratio of 49 dBc at 5-MHz offset using memory-effect mitigation digital pre-distortion, at an average output power above 2 W and a gain of 10 dB. Index Terms—Base-station power amplifier (PA), bipolarCMOS-DMOS (BCD), digital pre-distortion (DPD), efficiency, envelope tracking (ET), linearity, memory mitigation, micro-base-station, WCDMA.

I. INTRODUCTION HE RECENT increase of mobile data usage and the emergence of new applications, such as mobile web browsing and video streaming content, have motivated research on the extension of cellular network coverage without increasing the density of traditional macro-base-stations [1]. By installing smaller base-stations, such as micro, pico, and femto cells, to complement the conventional macro-base-stations, coverage can be significantly improved. Table I compares the categories of these new smaller base-stations to the traditional macro-base-station [2]. The micro-base-station concept is ideal for operators needing a cost-effective solution for high data rates to end users, without overbuilding the traditional macro-base-station network.

T

Manuscript received June 22, 2011; revised December 20, 2011; accepted December 22, 2011. Date of publication February 03, 2012; date of current version May 25, 2012. M. Kwak, J. J. Yan, and P. M. Asbeck are with the Department of Electrical and Computer Engineering, University of California at San Diego, La Jolla, CA 92093 USA (e-mail: [email protected]). D. F. Kimball is with the California Institute for Telecommunications and Information Technology, University of California at San Diego, La Jolla, CA 92093 USA. C. D. Presti is with Qualcomm Inc., San Diego, CA 92121 USA. A. Scuderi and C. Santagati are with STMicroelectronics, Catania I-95121, Italy. L. E. Larson is with the School of Engineering, Brown University, Providence, RI 02912 USA. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2012.2184128

In modern wireless communication transmitter systems, high power efficiency is an important objective in addition to high linearity. The envelope-tracking (ET) system shown in Fig. 1 improves the efficiency of a power amplifier (PA) by superimposing the envelope signal at the drain, such that the RF amplifier operates consistently closer to saturation [3]. The RF transistor is biased in the Class-AB region and the envelope signal provides the dynamic supply biasing to the RF PA. In much of the past work, ET techniques for macro-base-stations have demonstrated excellent performance, but the envelope amplifier was implemented using discrete components [4]–[7]. Compared to these discrete solutions, an integrated-circuit (IC) implementation for the envelope amplifier brings many benefits because: 1) it can minimize cost; 2) an integrated signal path provides better signal integrity; and 3) each transistor design parameter can be chosen for optimum size and power level for better performance. In [8]–[12], integrated envelope amplifiers for handset applications have been reported; however, the average output power was less than 1 W and the supply voltage was limited to 5 V due to the breakdown voltage of the CMOS transistors. For micro-base-station applications, a higher supply voltage is required to generate the average output power of 2–4 W. Recently, high-voltage LDMOS devices have been integrated with CMOS devices in a single IC process [13]. In this paper, we implement a high-voltage envelope amplifier in a bipolar-CMOS-DMOS (BCD) process technology for micro-base-station applications. To our knowledge, this is the first high-voltage monolithic envelope amplifier for multiwatt wide bandwidth RF applications. Adding to prior work [14], this paper will describe the detailed design considerations and implementation of a monolithic BCD wideband high-efficiency envelope amplifier, and its application to an ET PA for micro-base-station applications. This paper is organized as follows. Section II presents the ET system design consideration and the comparison with a conventional architecture. Section III describes the detailed design consideration and circuit level implementation of a proposed envelope amplifier. In Section IV, experimental results are shown for WCDMA signals and a conclusion is given in Section V. II. ET AMPLIFIER SYSTEM DESIGN The ET system shown in Fig. 1 improves the efficiency of a PA by modulating the power supply to a nearly saturated RF

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KWAK et al.: DESIGN OF WIDEBAND HIGH-VOLTAGE HIGH-EFFICIENCY BiCMOS ENVELOPE AMPLIFIER

COMPARISON

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TABLE I OF BASE STATIONS [2]

Fig. 1. Block diagram of wireless transmitter with ET system for improved efficiency.

PA stage. As compared with a constant dc supply voltage, the thermal dissipation is dramatically reduced and the transistor temperature is maintained at a low value. Another benefit of the ET technique, compared with other techniques such as the Doherty or LINC, is that the efficiency enhancement mechanism is totally decoupled from the RF matching [15]. The overall efficiency of the ET RF PA is approximately

Fig. 2. BCD6 process cross section through the fourth-layer metal [13].

(1) and are the efficiencies of the RF amplifier and where envelope amplifier, respectively. From (1), it is important to optimize the efficiencies of both the envelope amplifier and RF amplifier to maximize the overall efficiency. A. High-Voltage Envelope Amplifier Design Considerations The envelope amplifier was fabricated in STMicroelectronics’ 0.35- m BCD process, which allows mixing different structures such as CMOS for digital circuits and DMOS structures for power and high-voltage applications [13]. Fig. 2 shows a cross section of the BCD6 process, and the DMOS transistors are fully compatible with the existing 0.35- m CMOS process. The power MOS devices used in the design are 30-V N- and P-channel LDMOS field-effect transistors (FETs) with m mm and m mm , respectively, at V. The conventional envelope amplifier shown in Fig. 3 comprises a linear stage to provide a wideband, but less efficient, voltage source in parallel with a switching stage, which provides a narrowband, but efficient dynamic current source [6]. The current is supplied to the drain of the RF PA from both the linear stage and switching stage through a current feedback network, which senses the current flowing from the linear stage and turns on and off the buck converting switcher. The linear stage

Fig. 3. Conventional linear-assisted hybrid envelope amplifier for ET applications [6].

provides the difference between the desired output current and the current provided by the switching stage such that the overall difference current is minimized [6]. In Fig. 3, the current sensing circuitry needs to accommodate a rail-to-rail input voltage swing. For micro-base-station applications, a high supply voltage, such as 15 V, is required to generate the average RF output power of 2–4 W. To meet this high supply voltage requirement, 0.35- m 30-V N- and P-channel LDMOS FETs were used to implement the linear stage and switching FETs in the switcher stage. In addition, the maximum allowable magnitude of of these LDMOS devices is limited to 3.3 V to protect the gate oxide. Hence, the conventional current sensing circuitry, which is subject to rail-to-rail voltage swings, cannot be used with these LDMOS devices.

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Fig. 4. Proposed monolithic envelope amplifier with improved operation at . high

Fig. 6. CMOS comparator with controllable offset. Devices are 0.35- m CMOS, and the device widths of each transistor m, m, m, m. Minimum length of 0.35 m is used for all the devices.

input signaling (e.g., 10% of 15-V switching noise level can be almost 50% of 3.3 V). Detailed design techniques and circuit implementations for the envelope amplifier will be discussed in Section III. B. RF PA Design Considerations

Fig. 5. Simplified schematic of the linear stage. All the devices are 0.35- m was limited to 3.3 V in all cases. Device width of each DMOS, and the mm, mm, transistor is mm, mm, mm, mm.

The proposed envelope amplifier block diagram, as shown in Fig. 4, employs dual current sensing comparators, which require limited voltage swings. Detailed connections from the amplifier in the linear stage to the lowcomparators in the switcher stage are shown in Fig. 5. Fig. 6 shows the schematic of the comparator with the offset voltage controllable by bias current . This architecture has several advantages. First, the supply voltage and output voltage swing of each comparator is set to 3.3 V to maintain the reliability of the LDMOS devices. Second, dynamic power consumption in the lowcomparator is reduced because the dynamic power loss is proportional to the square of the supply voltage, as shown in (7), and the supply voltage is reduced from 15 to 3.3 V. Third, a current sensing resistor is not needed and the required input dynamic range in the comparator is not rail-to-rail. Finally, common-mode noise is reduced due to the differential input signal. In this design, the supply voltage of the linear stage and the switching stage is 15 V. Thus, there is a switching signal in the switcher-stage output from 0 to 15 V. However, the supply voltage of the lowcomparator is only 3.3 V as compared with this 15-V switching signal. Thus, if we use a single-ended input signal for these lowcomparators, a small amount of noise can have a large impact on the lowcomparator

The RF transistors were fabricated using a separate GaN-on-silicon heterostructure field-effect transistor (HFET) process [16]. GaN HFETs offer efficiency, bandwidth, and power advantages compared to Si LDMOS FETs. The high charge density combined with the ability to operate HFETs at high voltages (e.g., V) results in devices that have approximately ten times the power density of silicon and wider bandwidths due to the resulting higher input and output impedances [16]. However, the price gap between GaN HFETs and Si LDMOS power transistors is still significant because the majority of GaN HFETs are produced on silicon–carbide substrates [16]. GaN HFETs grown on a silicon substrate, which were used in this design, potentially offer substantial cost savings by combining the high-performance attributes of GaN HFETs with the economies of Si wafer substrates. In addition, devices with low values of are preferred in the ET system for optimum efficiency [6]. GaN HFETs have intrinsic benefits of lower output capacitance and on-resistance compared to Si LDMOS FETs. If a constant drain bias is used (e.g., V), the RF power-added efficiency rapidly degrades as the output power is backed-off. The maximum efficiency can be achieved at the peak output power and cannot be maintained over a wide range. In our design, the GaN HEMT, which is manufactured for a 28-V supply voltage, is used with a peak 15-V supply voltage. The limited supply voltage can degrade the performance of the RF PA in terms of efficiency because the efficiency is generally proportional to the output power (i.e., peak output voltage). However, the required average output power is 2–4 W for the micro-base-station application, and the supply voltage of 15 V is selected for this design. With an ET technique, the drain supply

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voltage is dynamically varied from 1 to 14 V with the output power level so as to maintain high efficiency at most times. Since the RF PA is highly saturated and the device acts as a switch when highly saturated (and the voltage and the current waveforms are engineered appropriately), higher efficiency than the class-B (or class-AB)-like RF PA can be achieved [6]. In this approach, the envelope signal does not have to be very accurate and the drain supply voltage could be tracked for the envelope signal with a several-decibel margin [15]. The GaN HFET was biased in class-AB mode. III. ET AMPLIFIER CIRCUIT DESIGN AND IMPLEMENTATION High efficiency is one of the main goals in the envelope amplifier circuit design, while maintaining an acceptable linearity specification. The efficiency of the proposed envelope amplifier can be evaluated by considering the power loss mechanisms associated with each stage. The efficiency of the envelope amplifier is given by (2) where , is the output power of the envelope amplifier, is the dc power dissipated by the envelope amplifier, is the total power loss of the envelope amplifier, is the loss of the linear stage, and is the loss of the switcher stage. In previous work [6], linear-stage efficiency was analyzed in the presence of an ideal switcher stage, and the loss of the linear stage is ideally zero at the average (or dc) level of the input signal since all the average power is supplied by the ideal switcher stage. In a real circuit implementation, the power loss at this operating point is not zero due to fact that the output stage quiescent current is not zero and there are static dc-bias currents. Fig. 5 shows the schematic of the linear stage. The first stage is implemented with a folded-cascode type amplifier to achieve high gain, and the output transistors are connected in a common-source configuration for near rail-to-rail output voltages [17]. Class-B output stages have very low quiescent current, but introduce crossover distortion. To achieve a good compromise between distortion and quiescent dissipation, the output stage is biased in class-AB mode. In this case, the output transistors are biased at a small (3%) quiescent current compared to the maximum output current to prevent a turn-on delay of the nonactive output transistor [17]. The class-AB biasing can be realized by keeping the voltage difference between the gates of the output transistors M1 and M2 at a constant value. In [9], the class-AB biasing circuitry was implemented with a source follower. In this design, the class-AB control is implemented by and , as shown in Fig. 5, to save die area and reduce dc-bias currents [17]. The power loss in the buck switching converter comes from two sources: conduction loss and switching loss , as shown in Fig. 7. These two sources have different design parameters and it is important to minimize these power losses together in the switcher-stage circuit design.

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Fig. 7. Switch voltages and currents in a buck-converting switcher [18].

The power loss of the switching FETs in the switcher stage is simulated as a function of the various device widths and the average switching frequencies, and the results are shown in Fig. 8. As shown in Fig. 7, the conduction loss results from the loss that is generated when the P-channel (or N-channel) LDMOS switching FET is on, and is approximately (3) where is the average duty cycle ratio of the switching pulses, is the drain current while the switching FET is on, is the on resistance of the P-channel LDMOS switching FET, and is the resistance of the N-channel LDMOS switching FET. The conduction loss, as shown in Fig. 8(a), is not dependent on the switching frequency and is inversely proportional to the device width. To minimize the conduction loss, the wider device width is preferred. The switching loss is the sum of the losses caused from simultaneous current and voltage during the turn-on and turn-off time, as well as the loss due to the output drain capacitance and the loss due to the input gate capacitance during switching. Thus, the switching loss can be expressed as the sum of three factors (4) is the crossover loss when both p- and where n-channel devices are on during the turn-on and turn-off periods, is the dynamic dissipation at the switcher output node, and is the input driver power dissipation. In Fig. 7, the switching loss is generated during the switch turn-on and turn-off time period and is dependent on the switching frequency. The crossover loss is given by (5) is the crossover time, which is the sum of the where turn-on and turn-off time period, is the commutation parameter (assuming to a first approximation [18]), and is the average switching frequency, respectively. Note that the crossover loss is not dependent on the device width and is proportional to the switching frequency, as shown in Fig. 8(b).

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Fig. 8. Simulation of the power loss in the switch FETs, as a function of device width and switching frequencies. The width of the P-channel LDMOS switch FET was twice that of the N-channel LDMOS switch FET. (a) Conduction loss. (b) Crossover loss. (c) Dynamic power dissipation at the output node. (d) Total V and . power loss in the switch-FETs.

Fig. 9. Simulation of the total power loss in the switch FETs as a function of the P-channel LDMOS switch FET width. The width of the N-channel LDMOS switch FET was set to 40 mm. An optimum P-channel FET width of 80 mm was V and . used for this design.

The dynamic power dissipation at the switcher output node is given by (6) where is the total drain capacitance at the output node. This loss is dependent on the switching frequency and the device width, as shown in Fig. 8(c). To minimize the switching power loss, the device is required to have a low input and output capacitance (i.e., smaller device width), but this causes a higher conduction loss. For example, the switching power loss in Fig. 8(c) can be reduced with smaller device width, however, the smaller

Fig. 10. Simulation of the power loss in the driver as a function of switch-FET device width and switching frequencies. The width of the P-channel LDMOS V switch FET was twice that of the N-channel LDMOS switch FET. . and

device width will result in the higher conduction loss, as shown in Fig. 8(a). With a low switching frequency, such as 1 MHz, the conduction loss would be dominant because the switching loss is inversely proportional to the switching frequency. In this case, the circuit designer would prefer to increase the device width to reduce the conduction loss, as shown in Fig. 8(d). However, a faster switching frequency is required to support a wideband signal and the optimum device width is found in the balance of the conduction loss and the switching loss to improve the overall efficiency. In this design, the width of the switching FET is set to 40 and 80 mm for the N- and P-channel, respectively,

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Fig. 11. Chip micrograph of the BCD envelope amplifier. The chip occupies 5.85-mm die area including the pads.

Fig. 14. Comparison of measured and simulated envelope amplifier efficiency as function of signal bandwidth and output power. Sine-wave input V and .

Fig. 12. Measured envelope amplifier input, output voltage, and switcher-stage output voltage. The envelope input signal is a 7.7-dB peak-to-average ratio (PAR) 4-MHz WCDMA signal. The closed-loop gain is 20 dB with 15-V supply voltage (200 ns/div). Fig. 15. Comparison of measured and simulated comparator offset voltage versus input bias current.

Fig. 13. Measured baseband envelope amplifier output spectrum for a 4-MHz WCDMA signal. The noise is 132.6 dBc/Hz at a 180-MHz offset. V and .

to minimize a total power loss in the switch FETs, as shown in Fig. 8(d). For a fixed N-channel switching FET width of 40 mm, the P-channel switching FET width is swept to check the power loss in the switch FETs, as shown in Fig. 9. The device width ratio between the N- and P-channel switching FET has an optimum value when the ratio is 1:2 in this simulation. To minimize shoot-through currents in the switcher stage, which affects , an input offset voltage control feature is proposed. Without this feature, the gate control signal for Nand P-channel LDMOS FETs in the switcher stage are synchronized, and for a short time, both transistors are turned on. These

Fig. 16. Measured envelope amplifier efficiency with a 7.7-dB PAR 4-MHz WCDMA signal and a 10- resistive load as a function of the comparator offset voltage.

shoot-through currents cause additional undesirable power loss in the switcher stage. In past work [19], a dead-time control logic was implemented with digital logic gates, and a rail-to-rail voltage swing was required. This kind of circuit cannot be easily used with thin-gate LDMOS FETs for reliability reasons. In the proposed architecture in Fig. 4, the comparator operating at lower voltages (closer to ground) has a positive input offset voltage and the output signal is nonoverlapping with the output signal of the high-side comparator to minimize shoot-

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Fig. 17. Measured results on GaN HFET PA with WCDMA input at 2.14 GHz. (a) Instantaneous drain efficiency versus drain voltage. (b) Instantaneous gain versus drain voltage. (d) Instantaneous output power versus drain voltage. versus drain voltage. (c) Instantaneous envelope load line

through currents. The comparator output voltage swing level is limited to 3.3 V in order to meet the maximum gate-to-source voltage requirements of the switcher stage. This topology also helps to reduce the power loss in the driver stage, given by

(7) where is the total gate capacitance at the input node, and is the gate-to-source turn-on voltage, respectively [19]. With the help of the limited input voltage swing, the power loss in the driver stage is a relatively small portion (10%–20%) compared with other power losses in the switch FETs. Like the dynamic power dissipation in the switch FETs in (6), the device width of the switch FETs and the switching frequency affect the driver power loss, as shown in Fig. 10. Thus, a smaller device width in the switch FETs is also required to minimize the driver loss, but the increase in the conduction loss should be considered at the same time. Fig. 6 shows the schematic of the comparator with the offset voltage controllable by bias current . In addition, this comparator senses the current by monitoring the input voltage of the class-AB biased final stage of the linear stage. The input stage of the comparator has a differential architecture to increase the voltage swing and reduce common-mode noise effects.

IV. MEASURED ET PA RESULTS The proposed envelope amplifier is fabricated using a 0.35- m BCD process with four metal layers [13]. A chip micrograph is shown in Fig. 11, and it measures 3.9 mm 1.5 mm. The performance of the ET PA was measured with a single-carrier WCDMA downlink signal at 2.14 GHz. The peak-to-average power ratio (PAPR) of the signal is 7.7 dB. Input signals such as the envelope and RF signals are generated in the digital domain and transformed to analog signals by the digital-to-analog converters (DACs), as shown in Fig. 1. The envelope signal is detroughed so that the minimum drain voltage is 1.4 V, to avoid gain collapse of the RF amplifier at low drain voltages, and amplified in the envelope amplifier. The time-delay difference between the envelope signal path and the RF signal path is adjusted to minimize the resulting distortion [19]. A GaN HFET-based RF PA was used with the high-voltage envelope amplifier for the complete ET PA. The gate of the GaN HFET was biased at 1.4 V and the drain supply voltage was modulated by the envelope amplifier from 1.4 to 14.0 V. The closed-loop voltage gain of the envelope amplifier was set to 20 dB with a 15-V supply voltage. Fig. 12 shows the measured time-domain input and output of the envelope amplifier in conjunction with the switcher-stage output. The output voltage of the envelope amplifier is ten times the input voltage and the switching voltage is rail-to-rail. The

KWAK et al.: DESIGN OF WIDEBAND HIGH-VOLTAGE HIGH-EFFICIENCY BiCMOS ENVELOPE AMPLIFIER

average switching frequency was 2 MHz for a single-carrier WCDMA signal (4-MHz bandwidth). To check the noise performance of the proposed envelope amplifier, the measured spectrum at the output voltage with a 10- resistive load is shown in Fig. 13. The noise at the WCDMA receive-band 180-MHz offset was measured to check the indirect effects of the receiveband noise in a WCDMA system. With the envelope signal supplied by a 14-bit DAC, the noise floor at the output of the DAC at a 180-MHz offset was measured to be 136 dBc/Hz relative to the dc output. At the output of the envelope amplifier, there is an upward boost in the noise at a 180-MHz offset of 3.4 dB, which is caused by an envelope amplifier, and the measured noise at the 180-MHz offset is 132.6 dBc/Hz. Fig. 14 shows the measured efficiency of the envelope amplifier as a function of the signal bandwidth and output power. As the signal frequency of the input single-tone sine waveform is increased from 1 to 5 MHz, the overall efficiency drops because of the increased switching loss. The switching loss is proportional to the switching frequency, and the simulated total switcher loss in the switch FETs at 5 MHz is 2.5 times higher than that of the 1-MHz case, as shown in Fig. 8(d). If desired, the switcher-stage efficiency can be improved at wider bandwidths by using a multiswitcher architecture [7]. To minimize the shoot-through currents, a controllable offset voltage was applied to the low-side comparator operating at a lower voltage in Fig. 4. This offset voltage is controllable with an input bias current , as shown in Fig. 15, and linearly increased according to this bias current. The value of the offset voltage determines the nonoverlapping time between the output signal of the low-side comparator and that of the high-side comparator. Without this nonoverlapping time, there would be an unwanted power loss due to the shoot-through currents when both switch FETs are turned on for a short time. However, if there is excess nonoverlapping time, both switch FETs are turned off simultaneously and the body diode of the N-channel switch FET will contribute to an additional power loss by turning on and conducting current. The efficiency of the envelope amplifier with a 10- resistive load was measured with a WCDMA signal to find an optimum offset voltage of the comparator, as shown in Fig. 16. The optimum offset voltage was determined to be 120 mV so as to avoid the shoot-through currents in the switcher stage with margin. The instantaneous values of , , , and are measured utilizing a high-speed sampling oscilloscope to analyze the characteristics of the RF stage and the envelope amplifier, respectively. Fig. 17 shows experimental results of the drain efficiency, gain, envelope load line, and output power. The instantaneous RF PA drain efficiency is shown in Fig. 17(a), and it reaches a maximum above 80% at the peak envelope voltage. Around the rms voltage of the envelope signal (5.8 V), the drain efficiency of the RF stage was above 60%, and the average drain efficiency of the RF stage was calculated to be 71%. The measured overall drain efficiency of the ET RF PA is 51% under these signal conditions and the high-voltage envelope amplifier shows an average efficiency of 72% by (1). The measured gain of the RF stage and the envelope load line is approximately 10 dB and 10 , as shown in Fig. 17(b) and (c), respectively. Fig. 18 shows the measured drain efficiency of

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Fig. 18. Measured drain efficiency of the RF stage along with a WCDMA signal probability density function.

TABLE II ENVELOPE AMPLFIER PERFORMANCE SUMMARY IN A WCDMA ET SYSTEM

Fig. 19. Normalized measured output power spectral density of single-carrier WCDMA signal with 7.7-dB PAR before predistortion, after pre-distortion, GHz, and after memory-effect mitigation DPD ( W).

the RF stage with a WCDMA signal probability density function. With a constant supply voltage, the RF PA efficiency will drop dramatically as the output power is backed off. However, in the ET RF PA system, the optimal RF PA efficiency follows the ET trajectory, and high efficiency above 60% can be maintained over a 10-dB range of output power, as shown in Fig. 18. Table II shows the performance summary of this envelope amplifier IC in a WCDMA ET system. Fig. 19 shows a comparison of the normalized output signal spectrum before and after memory-effect mitigation digital pre-distortion (DPD). We applied a memory-effect mitigation algorithm to improve the memory effects associated with this device. The memoryless DPD is a high-order polynomial for the

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Fig. 20. Measured: (a) AM–AM and (c) AM–PM performance before pre-distortion and (b) AM–AM and (d) AM–PM performance after memory-effect mitigation pre-distortion.

TABLE III PERFORMANCE SUMMARY OF ET PA WITH WCDMA SIGNAL

Drain efficiency (DE), memoryless digital pre-distortion (ML DPD), WCDMA specifications: dBc, dBc, ACLR1 at 5-MHz offset, ACLR2 at 10-MHz offset for WCDMA.

magnitude (usually ninth) and a second high-order polynomial for the phase (usually eleventh). Memory-effect mitigation is a technique used to quantify all deterministic memory with no specific target model topology based on nonlinear perturbation theory, as detailed in [21]. The adjacent channel leakage power ratio (ACLR) performance is improved by 20 and 13 dB at the 5- and 10-MHz offset, respectively, and the specifications are met with margin through memory-effect mitigation DPD. The ACLR specifications for WCDMA radio base-station output signals are 45 dBc at the 5-MHz offset and 50 dBc at the 10-MHz offset. Fig. 20 shows the measured AM–AM and AM–PM characteristics before and after memory-effect mitigation DPD. The scatter of the plotted data indicates a perturbation to the instantaneous gain caused by deterministic

memory effects [6] and these memory effects are compensated after memory-effect mitigation DPD. The average measured drain efficiency of the PA, including dissipation of the envelope amplifier, is 51% with an average output power of 2.5 W and a peak output power of 15 W. The gain and normalized power root mean square error (NRMSE) are 10.2 dB and 1.2% after memory-effect mitigation DPD, respectively. At full output power, the peak envelope voltage was 14 V and the rms voltage was 5.8 V. Table III summarizes the measured performance of the ET PA with a single-carrier WCDMA signal, and Table IV summarizes a comparison of this work and the previously published ET PAs with monolithic envelope amplifiers. In previous monolithic ET amplifiers (Table IV), the average output power of the integrated envelope

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TABLE IV COMPARISON TO PREVIOUS MONOLITIC ET WORK AND THE WORK PRESENTED IN THIS PAPER

peak efficiency at the peak output power

amplifiers has been below 1 W and the supply voltage has been limited due to the low breakdown voltage of the CMOS transistors. For micro-base-station applications, a higher supply voltage is required to generate the average output power of 2–4 W, and this high-voltage envelope amplifier shows the average output power more than 2 W and an average efficiency of 72%. To our knowledge, this is the first high-voltage monolithic envelope amplifier for multiwatt wide-bandwidth RF applications, and the overall performance demonstrated in the complete ET system is shown in Table III. V. CONCLUSION A high-performance high-voltage BCD monolithic envelope amplifier was presented to achieve high efficiency and linearity for wide-bandwidth micro-base-station PA applications. The overall drain efficiency of the ET system is 51% at 34-dBm output power with an average high-voltage envelope amplifier efficiency of 72%, and the linearity requirements are met after memory-effect DPD for a WCDMA signal with a PAPR of 7.7 dB. The results make this architecture an attractive candidate for monolithic integration of a high-voltage envelope amplifier for micro-base-station RF PA applications. ACKNOWLEDGMENT The authors would like to thank G. Meola, STMicroelectronics, Catania, Italy, for fabricating the chip, S. Lanfranco, Nokia Siemens Networks, Espoo, Finland, for supporting this study, R. Cochran, Nitronex, Durham, NC, for providing the HFETs, and the assistance of C. Vu, University of California at San Diego (UCSD), La Jolla, on measurements. REFERENCES [1] R. Irmer and F. Diehm, “On coverage and capacity of relaying in LTEadvanced in example deployments,” in Proc. IEEE 19th Int. Pers., Indoor, Mobile Radio Commun, Symp., 2008, pp. 1–5. [2] “Achieving cost-effective broadband coverage with WiMAX micro, pico and femto base-stations,” Fujitsu, Tokyo, Japan, 2011. [Online]. Available: http://www.fujitsu.com/ [3] F. Wang, A. H. Yang, D. F. Kimball, L. E. Larson, and P. M. Asbeck, “Design of wide-bandwidth envelope-tracking power amplifiers for OFDM applications,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 4, pp. 1244–1255, Apr. 2005. [4] P. Draxler, S. Lanfranco, D. Kimball, C. Hsia, J. Jeong, J. van de Sluis, and P. M. Asbeck, “High efficiency envelope tracking LDMOS power amplifier for W-CDMA,” in IEEE MTT-S Int. Microw. Symp. Dig., 2006, pp. 1534–1537.

[5] D. F. Kimball, J. Jeong, C. Hsia, P. Draxler, S. Lanfranco, W. Nagy, K. Linthicum, L. E. Larson, and P. M. Asbeck, “High-efficiency envelopetracking WCDMA base-station amplifier using GaN HFETs,” IEEE Trans. Microw. Theory Tech., vol. 54, no. 11, pp. 3848–3856, Nov. 2006. [6] J. Jeong, D. F. Kimball, M. Kwak, P. Draxler, C. Hsia, C. Steinbeiser, T. Landon, O. Krutko, L. E. Larson, and P. M. Asbeck, “High-efficiency WCDMA envelope tracking base-station amplifier implemented with GaAs HVHBTs,” IEEE J. Solid-State Circuits, vol. 44, no. 10, pp. 2629–2639, Oct. 2009. [7] C. Hsia, D. F. Kimball, S. Lanfranco, and P. M. Asbeck, “Wideband high efficiency digitally-assisted envelope amplifier with dual switching stages for radio base-station envelope tracking power amplifiers,” in IEEE MTT-S Int. Microw. Symp. Dig., 2010, pp. 672–675. [8] T.-W. Kwak, M.-C. Lee, and G.-H. Cho, “A 2 W CMOS hybrid switching amplitude modulator for EDGE polar transmitters,” IEEE J. Solid-State Circuits, vol. 42, no. 12, pp. 2666–2676, Dec. 2007. [9] F. Wang, D. F. Kimball, D. Y. Lie, P. M. Asbeck, and L. E. Larson, “A monolithic high-efficiency 2.4-GHz 20-dBm SiGe BiCMOS envelopetracking OFDM power amplifier,” IEEE J. Solid-State Circuits, vol. 42, no. 6, pp. 1271–1281, Jun. 2007. [10] W.-Y. Chu, B. Bakkaloglu, and S. Kiaei, “A 10 MHz-bandwidth, 2 mV ripple PA regulator for CDMA transmitters,” IEEE J. Solid-State Circuits, vol. 43, no. 12, pp. 2809–2819, Dec. 2008. [11] V. Pinon, F. Hasbani, A. Giry, D. Pache, and C. Gamier, “A singlechip WCDMA envelope reconstruction LDMOS PA with 130 MHz switched-mode power supply,” in Proc. IEEE Int. Solid-State Circuits Conf. Tech. Dig., 2008, pp. 564–636. [12] D. Kim, J. Choi, D. Kang, and B. Kim, “High efficiency and wideband envelope tracking power amplifier with sweet spot tracking,” in Proc. IEEE Radio Freq. Integr. Circuits Symp., 2010, pp. 255–258. [13] C. Contiero, A. Andreini, and P. Galbiati, “Roadmap differentiation and emerging trends in BCD technology,” in Proc. 32nd Eur. SolidState Device Res. Conf., 2002, pp. 275–282. [14] M. Kwak, D. Kimball, C. Presti, A. Scuderi, C. Santagati, J. Yan, P. M. Asbeck, and L. E. Larson, “Wideband high efficiency envelope tracking integrated circuit for micro-base station power amplifiers,” in Proc. IEEE Radio Freq. Integr. Circuits Symp., 2011, pp. 145–148. [15] S. C. Cripps, RF Power Amplifiers for Wireless Communications. Norwood, MA: Artech House, 2006. [16] “Built using the SIGANTIC NRF1 process—A proprietary GaN-onsilicon technology,” Nitronex, Durham, NC, 2011. [Online]. Available: http://www.nitronex.com/ [17] R. Hogervorst, J. P. Tero, R. G. H. Eschauzier, and J. H. Huijsing, “A compact power-efficient 3 V CMOS rail-to-rail input/output operational amplifier for VLSI cell libraries,” IEEE J. Solid-State Circuits, vol. 29, no. 12, pp. 1505–1513, Dec. 1994. [18] P. T. Krein, Elements of Power Electronics. Oxford, U.K.: Oxford Univ. Press, 1998. [19] F. Wang, D. F. Kimball, J. D. Popp, A. H. Yang, D. Y. Lie, P. M. Asbeck, and L. E. Larson, “An improved power-added efficiency 19-dBm hybrid envelope elimination and restoration power amplifier for 802.11 g WLAN applications,” IEEE Trans. Microw. Theory Tech., vol. 54, no. 12, pp. 4086–4099, Dec. 2006. [20] M. Hassan, M. Kwak, V. W. Leung, C. Hsia, J. J. Yan, D. F. Kimball, L. E. Larson, and P. M. Asbeck, “High efficiency envelope tracking power amplifier with very low quiescent power for 20 MHz LTE,” in Proc. IEEE Radio Freq. Integr. Circuits Symp., 2011, pp. 131–134. [21] P. Draxler, J. Deng, D. Kimball, I. Langmore, and P. M. Asbeck, “Memory effect evaluation and predistortion of power amplifiers,” in IEEE MTT-S Int. Microw. Symp. Dig., 2005, pp. 1549–1552.

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Myoungbo Kwak (S’06) received the B.S. and M. Eng. degrees in electronics engineering from Sogang University, Seoul, Korea, in 1995 and 1997, respectively, and is currently working toward the Ph.D. degree at the University of California at San Diego (UCSD), La Jolla. In 1997, he joined Samsung Electronics Ltd., Giheung, Korea, where he was mainly involved with the development of a high-speed interface core for multi-Gb/s serial links and phase-locked loop (PLL) design. Since 2006, he has been with the RF Integrated Circuit (RFIC) Group, UCSD. His current research interests include RF and analog circuit design for wireless communications.

Donald F. Kimball (S’82–M’83) was born in Cleveland, OH, in 1959. He received the B.S.E.E. (suma cum laude with distinction) and M.S.E.E. degree from The Ohio State University, Columbus, in 1982 and 1983 respectively. From 1983 to 1986, he was with the Data General Corporation, as a TEMPEST Engineer. From 1986 to 1994, he as with Data Products New England, as an Electromagnetic Compatibility Engineer/Manager. From 1994 to 1999, he was with Qualcomm Inc., as a Regulatory Product Approval Engineer/Manager. From 1999 to 2002, he was with Ericsson, Inc., as a Research and Technology Engineer/Manager. Since 2003, he has been with Calit2, University of California at San Diego, as a Principal Development Engineer. He has authored or coauthored numerous technical papers concerning high-efficiency high-linearity high-power RF amplifiers (HPAs). His research interests include HPA envelope elimination and restoration techniques, switching HPAs, adaptive DPD, memory effect inversion, mobile and portable wireless device battery management, and small electric powered radio controlled autonomous aircraft. He holds 7 U.S. patents associated with HPAs.

Calogero D. Presti (S’05–M’08) received the Laurea degree in electronics engineering (cum laude) and Ph.D. degree in electronics and automation engineering from the University of Catania, Catania, Italy, in 2005 and 2008, respectively, and the Diploma degree (cum laude) from the Scuola Superiore di Catania, Catania, Italy, in 2005. From 2004 to 2005, he was with the Center for Materials and Technologies for Information and Communication Science (MATIS CNR INFM), Catania, Italy, where he was involved in the modeling of nanostructured materials and the design of 2-D photonic crystals for silicon-based opto-electronics. In 2005, he joined the Radio Frequency Advanced Design Center (RF ADC), Catania, Italy, a joint research group supported by the University of Catania and STMicroelectronics, where his doctoral research was focused on CMOS power amplifiers (PAs), RF switches, device reliability, and digital predistortion. During 2009, he was a Post-Doctoral Researcher with the University of California at San Diego, La Jolla, where he was mainly involved with PA DPD and ET. In 2010, he joined Qualcomm Inc., San Diego, CA, as a member of the RF/Analog Design Team.

Antonino Scuderi (S’04–M’06) was born in Catania, Italy, in 1972. He received the Laurea degree in electronics engineering (cum laude) and Ph.D. degree in electronics and automation engineering from the University of Catania, Catania, Italy, in 1997 and 2006, respectively. From 1999 to 2005, he was with the Radio Frequency Advanced Design Center (RF-ADC), a joint research center supported by the University of Catania and STMicroelectronics, Catania, Italy, where he managed the STMicroelectronics RF PA

advanced design team. Since 2006, he has been with STMicroelectronics, where, until 2009, he was Manager of RF Power Developments. He is currently a Senior Manager of Microsystems Developments involved in the fields of power RF, power compounds, flexible electronics, and healthcare. He has authored or coauthored over 40 scientific papers. He holds ten industrial patents.

Carmelo Santagati received the Laurea degree in electronics engineering from the University of Catania, Catania, Italy, in 2002. From 2003 to 2006, he was with the Radio Frequency Advanced Design Center (RF-ADC), Catania, Italy, a joint research group supported by the University of Catania and STMicroelectronics, Catania, Italy, where he performed research on bipolar and CMOS PAs for wireless handsets. During 2007, he was with the Advanced RF IPs Design Group, STMicroelectronics, where he was involved with the design and development of high-efficiency multimode/multiband PA modules and voltage standing-wave ratio (VSWR) correction techniques. He is currently a Design Engineer with STMicroelectronics, where he is involved with power management integrated circuits for wireless applications and standard linear and interface markets.

Jonmei J. Yan (S’03) received the Bachelor’s and Master’s degrees in electrical engineering from the University of California at San Diego, La Jolla, and is currently working toward the Ph.D. degree at the University of California at San Diego. She was with ARM Inc., as an Analog Designer, where she was involved in the design and layout of the custom high-speed inputs/outputs (I/Os). She also guided the automation of the quality control process. Since 2006, she has been a Design Engineer with MaXentric Technologies, where she leads mul-band as the Principle Investigator. tiple PA projects ranging from UHF to Her research interests include high-efficiency/high-power RF amplifiers for wireless communications and adaptive DPD. She is currently engaged in research on broadband PAs, ET PAs, and advanced DPD techniques.

Peter M. Asbeck (M’75–SM’97–F’00) received the B.S. and Ph.D. degrees from the Massachusetts Institute of Technology (MIT), Cambridge, in 1969 and in 1975, respectively. He was with the Sarnoff Research Center, Princeton, NJ, and Philips Laboratory, Briarcliff Manor, NY, where he was involved in the areas of quantum electronics and GaAlAs/GaAs laser physics. In 1978, he joined the Rockwell International Science Center, where he was involved in the development of high-speed devices and circuits using III–V compounds and heterojunctions. He pioneered efforts to develop heterojunction bipolar transistors based on GaAlAs/GaAs and InAlAs/InGaAs materials. In 1991, he joined the University of California at San Diego, La Jolla, where he is the Skyworks Chair Professor with the Department of Electrical and Computer Engineering. His research has led to over 350 publications. His research interests are in development of high-performance transistor technologies and their circuit applications. Dr. Asbeck is a member of the National Academy of Engineering. He has been a Distinguished Lecturer of the IEEE Electron Device Society and of the IEEE Microwave Theory and Techniques Society (IEEE MTT-S). He was the recipient of the 2003 IEEE David Sarnoff Award for his research on heterojunction bipolar transistors.

KWAK et al.: DESIGN OF WIDEBAND HIGH-VOLTAGE HIGH-EFFICIENCY BiCMOS ENVELOPE AMPLIFIER

Lawrence E. Larson (S’82–M’86–SM’90–F’00) received the B.S. degree in electrical engineering from Cornell University, Ithaca, NY, in 1979, and the Ph.D. degree from the University of California at Los Angeles (UCLA), in 1986. From 1980 to 1996, he was with Hughes Research Laboratories, Malibu, CA, where he directed the development of high-frequency microelectronics in GaAs, InP, Si/SiGe, and microelectromechanical systems (MEMS) technologies. In 1996, he joined the faculty of the University of California at San Diego (UCSD), La Jolla, where he was the inaugural Holder of the Communications Industry Chair. From 2001 to 2006, he was Director of the UCSD Center for Wireless Communications. From 2007 to 2011, he was Chair of

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the Department of Electrical and Computer Engineering, UCSD. In 2011, he joined Brown University, Providence, RI, where he is Founding Dean of the School of Engineering. During the 2000–2001 academic year, he was on leave with IBM Research, San Diego, CA. During the 2004–2005 academic year, he was a Visiting Professor with the Technical University of Delft (TU Delft), Delft, The Netherlands. He has authored or coauthored over 300 papers. He has coauthored three books. He holds 40 U.S. patents. Dr. Larson was the 1994 recipient of the Hughes Sector Patent Award for his research on RF MEMS. He was corecipient of the 1996 Lawrence A. Hyland Patent Award of Hughes Electronics for his research on low-noise millimeterwave HEMTs and the 1999 IBM Microelectronics Excellence Award for his research on Si/SiGe HBT technology.

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High-Efficiency Cellular Power Amplifiers Based on a Modified LDMOS Process on Bulk Silicon and Silicon-On-Insulator Substrates With Integrated Power Management Circuitry Ali Tombak, David C. Dening, Michael S. Carroll, Julio Costa, and Edward Spears

Abstract—An RF high-voltage CMOS technology is presented for cost-effective monolithic integration of cellular RF transmit functions. The technology integrates a modified LDMOS RF power transistor capable of nearly comparable linear and saturated RF power characteristics to GaAs solutions at cellular frequency bands. Measured results for multistage cellular power amplifier (PA) designs processed on bulk-Si and silicon-on-insulator on high-resistivity Si substrates (1 k cm) are presented. The low-band multistage PA achieves greater than 60% power-added efficiency (PAE) with more than 35.5-dBm output power. The high-band PA achieves 45%–53% PAE across the band with greater than 33.4-dBm output power. Measured linearity performance is presented using an EDGE modulation source. A dc/dc buck converter was also integrated in the PA die as the power management circuitry. Measured results for the output power, PAE, and spurious emissions in the receive band while the dc/dc converter is biasing the PA and running at different modes are reported. Index Terms—Copper pillar flip-chip, DC/DC converter, front-end module (FEM), integrated power MOS (IPMOS), LDMOS, receive (RX) band noise, silicon-on-insulator (SOI), silicon power amplifier (PA), spurious, transmit module (TXM).

I. INTRODUCTION

T

HE MARKET for mobile handsets and connected devices is characterized as among the largest global markets for the RF semiconductor industry. It is expected that new device shipments will grow at an average rate of 10% over the next decade. With the smartphone revolution, the handset starts playing an even more important role in our lives. Today’s wireless handset is a highly sophisticated device capable of operating in global frequency bands and standards, offering navigational assistance [global positioning system (GPS)], enabling video telephony, downloading email, exchanging

Manuscript received September 30, 2011; revised March 12, 2012; accepted March 13, 2012. Date of publication April 20, 2012; date of current version May 25, 2012. A. Tombak, M. S. Carroll, J. Costa, and E. Spears are with the Technology Platforms Organization, RFMD Inc., Greensboro, NC 27409 USA (e-mail: [email protected]; [email protected]; [email protected]; [email protected]). D. C. Dening was with the Technology Platforms Organization, RFMD Inc., Greensboro, NC 27409 USA. He is now with Skyworks Solutions Inc., Greensboro, NC 27409 USA (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2012.2191975

Fig. 1. Typical 2.5G RF TX module designed for quad-band GSM/GPRS/ EDGE cellular applications 6 5 mm . In addition to the two power GaAs HBT PAs, pHEMT RF switch, and HVCMOS power management die, the module includes several surface-mounted passive devices on a four-layer laminate.

photo/video, and hosting other numerous applications that require very high data rates and more efficient processing of data. Another trend happening in the wireless handset is the reduction of the real estate available to the radio. While the mode and band coverage are increasing, wireless handsets are being designed that are lighter and smaller than ever before. Hence, the number of discrete RF components in the mobile handset has been continuously decreasing as original equipment manufacturers (OEMs) have been demanding more and more modular solutions. The key solution to this tremendous pressure is the integration of the radio [1]–[7]. RF transmit modules (TXMs) [or front-end modules (FEMs)] have become standard components in modern cellular handset applications. Current cellular TXMs exist in different configurations. They are typically defined as system-in-package (S-i-P) solutions that integrate all of the necessary RF transmission functions, which exist between the antenna and the transceiver block of an RF system. Fig. 1 depicts a typical quad-band global system for mobile communications (GSM)/general packet radio service (GPRS)/EDGE RF TXM, which includes two RF power amplifiers (PAs) (commonly designed using two separate GaAs HBT PA dies), RF antenna transmit (TX)/receive (RX) time-domain multiplexing switch between

0018-9480/$31.00 © 2012 IEEE

TOMBAK et al.: HIGH-EFFICIENCY CELLULAR PAs BASED ON MODIFIED LDMOS PROCESS

the high-power TX and RX blocks (typically implemented using depletion-mode GaAs pseudomorphic HEMT (pHEMT) technology), as well as a silicon power management CMOS chip, which typically provides the necessary bias and control functionality for the PA and the switch dies. The CMOS power management integrated circuit (IC) is typically implemented in a high-voltage CMOS (HVCMOS) technology. It provides amplifier power level and mode control, bias management, dc-to-dc converter, power regulators, electrostatic discharge (ESD) handling, and even more complex RF modulation circuits for some applications. The transceiver, baseband, and power management ICs must strictly be based on CMOS due to the unmatched performance and low cost of this technology. As the integration in the radio occurs, technology will drive the partitioning toward the transceiver/baseband in deep-submicrometer CMOS, and the front-end in a higher voltage less expensive CMOS process. One of the major difficulties facing the suppliers of RF components for the cellular market is the fact that the evolution of RF system standards toward third-generation (3G) and fourth-generation (4G) creates the need for increasingly more complex RF system modules. In the specific case of cellular 3G standard, the RF system suppliers are being asked to provide integrated RF TX modules capable of simultaneously supporting the existing quad-band GSM/EDGE standards and standalone or converged multiband Universal Mobile Telecommunications System (UMTS) WCDMA 3G standards. Future system specifications beyond 3G and 4G will require an even larger number of multistandard TX functions. It is obvious that such complex RF TX systems could greatly benefit from much higher degrees of integration [1]–[7]. In this paper, a 0.5- m RF HVCMOS technology processed on bulk Si and silicon-on-insulator (SOI) on high-resistivity Si substrates is described as a cost-effective solution for monolithic integration of cellular RF TX functions. This technology was engineered to provide a high-yield, highly integrated, and compact RF technology solution to multiple RF FEM requirements. The technology integrates a modified LDMOS transistor capable of nearly comparable linear and saturated RF power characteristics to GaAs solutions at cellular frequency bands [8], [9]. Measured results for multistage PA designs, as well as PAs with an integrated dc/dc converter as part of the power management circuitry, are presented. II. TECHNOLOGY The technology was engineered using, as a foundation, a conventional 0.5- m RF HVCMOS process that is already deployed in large volume for use in PA controller applications. The 5-V nMOS and pMOS devices are built utilizing a single 130-Å gate–oxide, silicided polysilicon gate electrodes with effective gate lengths of 0.5 m. A modified LDMOS-based MOS device, integrated power MOS (IPMOS), was also designed to provide integration of high-performance reliable RF power devices in the technology for cellular applications. The IPMOS device implementation differs from conventional LDMOS approaches such that the handle wafer does not provide an electrical/thermal dissipation path for the power devices. Instead, a copper pillar flip-chip packaging methodology was developed that provides a low thermal resistance

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Fig. 2. Cross section of the IPMOS power device on bulk-Si substrate.

Fig. 3. Cross section of the IPMOS power device on SOI substrate.

path for the power field-effect transistor (FET) cells, while at the same time providing optimal ground inductances for the amplifier [10]. This latter feature is particularly important for RF power applications at cellular HB (1710–1980 MHz), where RF power gain of large silicon power cells is critical. Since the IPMOS device implementation does not rely on the substrate for grounding, the technology can also be processed on SOI substrates as part of a broader effort to integrate the TX/RX switches in the same PA process. Compared to the standard bulk CMOS process, SOI CMOS offers better frequency response, high- passive components, and better isolation. With the capability to isolate device bodies using a trench isolation process, transistors can be stacked to design high-power RF switches that handle high off-state RF voltages. The handle wafer resistivity is 1000 cm for SOI versus 3 cm for bulk Si substrates. The thickness of the SOI epitaxial layer is greater than 1 m. A cross section of the IPMOS power device and the implant schedule employed in the IPMOS device integration on an SOI substrate are shown in Figs. 2 and 3, respectively. Table I shows dc and RF parameters for IPMOS devices implemented in both bulk-Si and SOI substrates, which shows that most parameters are identical for both substrates. Also, a plot of IPMOS and versus at nominal voltage of 3.5 V is shown in Fig. 4 for bulk-Si and SOI substrates. The decrease in and for SOI devices is attributed to self-heating of the device during wafer-level measurements. The actual difference in and for packaged SOI products using a copper pillar flip-chip is expected to be negligible. The small increase in for SOI devices is attributed to reduced parasitic capacitance. A metal–insulator–metal (MIM) capacitor with capacitance density of 2000 pF/mm and breakdown voltages near 20 V is also integrated in the process.

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TABLE I IPMOS DEVICE PARAMETERS AT BULK SILICON AND SOI SUBSTRATES

Fig. 5. Schematic of the three-stage IPMOS PAs and topology of the matching networks.

Fig. 6. Measured 900-MHz band

Fig. 4. strates

and

versus V .

for IPMOS devices at bulk-Si and SOI sub-

The process includes a 3- m-thick aluminum third metal layer, which is usually used in RF design. III. IPMOS PAs Extensive thermal simulations and measurements were performed to generate power cells that provided the best tradeoff in RF and thermal characteristics for a given power dissipation level. RF load–pull and board-level characterization was also performed on these flip-chip IPMOS power cells for operation at multiple modulation and frequency bands. Using these optimized cells, three-stage PAs were designed to operate at GSM850/900 [low band (LB)] and digital communication system (DCS)/personal communication system (PCS) [high band (HB)] frequency bands. The LB PA included a 1-mm-wide first-stage, 8-mm-wide second-stage, and 40-mm-wide final-stage IPMOS transistors, whereas the HB PA had the same size first- and second-stage devices, but a 30-mm-wide final-stage IPMOS device. A four-layer laminate board was used to design necessary impedance matching networks to the individual PA stages using surface mount components. A regular three-section low-pass output matching network and one-section high-pass interstage matching networks were used to design the multistage IPMOS PAs. A general schematic and topology of the matching networks for the designed IPMOS PAs are shown in Fig. 5. The gate biases

and PAE versus frequency for the PA at GSM 850/ dBm .

were applied through an integrated bias circuitry that generated the necessary gate voltages for the PA stages using a bandgap voltage reference with a proportional to absolute temperature current source , and several current mirrors. The PA quiescent bias was 84 mA, and the leakage current was approximately 25 nA when the bias was disabled. The measurements were performed at room temperature with a 10% pulsed system at a battery voltage of 3.5 V. The measured and power-added efficiency (PAE) for the multistage PAs processed on bulk-Si- and SOI-based substrates are shown in Figs. 6 and 7 at cellular LB and HB frequencies, respectively. The input power was 3 dBm. At GSM850/900-MHz band, the SOI PA achieved typical PAEs greater than 60% with ranging from 35.5 to 36.7 dBm. The bulk-Si based multistage PA achieves approximately 0.2 dB less output power and 4-percentage-point average drop in the PAE. At the DCS/PCS band, the SOI PA achieved typical PAEs in the range of 45%–53% with ranging from 33.4 to 34 dBm. The bulk-Si-based PA achieves approximately 0.6-dB less output power on average and 6-percentage-point average drop in the PAE. The PAs fabricated on SOI substrates performs better than the PAs in the bulk-Si substrate for both bands due mostly to the high-resistivity handle wafer offering lower loss interconnects and matching elements, and lower parasitics. Table II presents a comparison of the IPMOS PA performance with other PAs based on Si CMOS-, Si LDMOS-, SiGe HBT-, and GaAs-HBT based technologies, which shows that the IPMOS PAs presented in this paper compare very well with PAs designed using other technologies. The LB PA was also tested using an EDGE modulated signal [eight phase-shift keying (8PSK)] at the input of the PA. The

TOMBAK et al.: HIGH-EFFICIENCY CELLULAR PAs BASED ON MODIFIED LDMOS PROCESS

Fig. 7. Measured dBm .

and PAE versus frequency for the PA at DCS/PCS band

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Fig. 8. Measured EVM versus 849, 870, 880, and 915 MHz.

for an EDGE modulated signal at 824,

TABLE II COMPARISON OF THE IPMOS PA WITH OTHER PA TECHNOLOGIES

Fig. 9. Measured PAE and upper/lower channel ACPR/ALT channel power for an EDGE modulated signal. The carrier frequency was at ratio versus 200-, 400-, and 600-kHz 880 MHz. The ACP/ALT data was collected at offset from the carrier frequency.

gate bias voltages were held the same as in the saturated mode of operation. The measured error vector magnitude (EVM), and measured PAE and adjacent channel power ratio (ACPR)/alternate channel power ratio (ALT1,2R) as a function of the output power are shown in Figs. 8 and 9, respectively. The measured EVM was less than 3.5% up to 29-dBm output power. The measured ACPR and ALT1R/ALT2R were also better than 36 and 56 dBc, respectively. The tuned PAs were also tested at various duty cycles and temperatures. The measured and PAE versus temperature at 12.5% and 50% duty cycles are shown in Table III for LB and HB IPMOS PAs. The input power was 3 dBm. In the worst case, the measured and PAE were degraded by approximately 0.9 dB and 7-percentage-points from low to high temperature for both bands, respectively. The measured results are similar to commercially available GaAs-based PAs for GSM saturated PA applications, which shows that the engineered IPMOS devices can withstand typical operating conditions of saturated PAs. IV. INTEGRATED DC/DC CONVERTER AND IPMOS PA Using dc/dc converters to dynamically adjust the battery voltage has been an increasingly popular efficiency enhancement technique at backed-off output power levels [13]–[17]. A dc/dc buck converter was also integrated with the three-stage PAs as power management circuitry. The dc/dc buck converter

TABLE III IPMOS PA PERFORMANCE VERSUS. DUTY CYCLE AND AMBIENT TEMPERATURE

was a differential switcher [18] with each branch composed of 15-cm-wide and 0.6- m-long positive-channel field-effect transistor (PFET) and 5-cm-wide and 0.6- m-long negative-channel field-effect transistor (NFET) devices at its output. A block diagram of the differential dc/dc converter is shown in Fig. 10. The converter sections are driven in a pulsewidth modulation (PWM) mode 180 apart using dual sawtooth signals generated by the oscillator. Each section employs an average current feedback loop that acts to balance the inductor currents between the halves. The losses in the dc/dc converter were approximated in the standalone mode. Using a 3.5-V supply

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Fig. 11. Analysis of the losses in the differential dc/dc converter shows a good match between the FET and inductor losses. The maximum converter loss is less than 10% of the maximum output power. Fig. 10. Differential dc/dc converter includes two converters running in parallel and driven by two clocking signals that are phased 180 apart.

and a 1.53- resistive load, the control was adjusted to sweep the output throughout its full range while monitoring the currents and voltages from the input supply and the output to the load resistor. A quiescent current of 2 mA flows in the control circuitry when the converter is not switching. The switching losses were estimated from the lowest output voltage and current after removing the almost insignificant 7 mW of power delivered to the load resistor at this data point, which minimized resistive losses within the converter. It was assumed that switching losses remained constant over the range of operation since they stem from the currents used to charge and discharge the internal capacitive nodes within the converter. During each clock cycle the same amount of charge is required independent of the timing determined by the PWM duty cycle. The inductor dc resistance and the output current were used to approximate the inductor losses. The remainder of the loss was then attributed to resistive losses in the FETs. Fig. 11 summarizes the results of the converter loss estimation. The losses in the inductors were close to the losses attributed to the FETs implying that the output devices were about the right size for this application. The shape of the FET and inductor loss components was parabolic with increasing output current and starts at zero power, as would be expected from an trend. The FET loss curve contains all of the errors from the approximations in the other losses and can be seen to deviate slightly from the shape of the inductor losses. Some of this deviation may be attributed to differences in the saturated resistance between the output NFETs and PFETs. As the duty cycle varies over the output range, the loss contributions from the saturated top and bottom devices changes. The maximum switcher loss was 0.6 W while delivering more than 6 W to the resistor used in the evaluation. The maximum converter output power was in line with the power supply requirements for an LB RF PA with an output power of 3 W at 50% efficiency. The converter efficiency was greater than 90% at full output voltage. Fig. 11 belonged to a standalone dc/dc converter die on bulk-Si substrates. However, since the majority of the total loss contribution comes from inductive and FET losses, no

Fig. 12. Layout of the integrated dc/dc converter and PA. The die size is 3.2 1.9 mm .

significant difference in dc/dc converter performance on SOI substrates is expected. A picture of the dc/dc converter die integrated with a threestage PA on the SOI substrate and the associated evaluation board are shown in Figs. 12 and 13, respectively. The total die size was 3.2 1.9 mm , whereas the size for the dc/dc converter portion of the die was 1.15 1.9 mm . The output voltage of the converter was controlled by varying the voltage between 0.25–1.75 V. The low-pass filter at the output of the converter included a 1- H series inductor for each differential branch and a 1- F shunt capacitor on the printed circuit board. In order to test the performance of the dc/dc converter and associated PAE savings, the and PAE of the PA was recorded for three different cases, as shown in Fig. 14; 1) fixed of 3.5 V through the dc source and varying ; 2) fixed and varying through the dc/dc converter; and 3) fixed and varying through a dc source in order to emulate an ideal dc/dc converter for calculating the internal efficiency of the dc/dc converter. The PA gain for case 1 and case 2 were also included in Fig. 14. The test frequency was at 915 MHz. The connection between the dc/dc converter and the PA was achieved using cable assembly. The calculated dc/dc converter efficiency was better than 90% for levels greater than 25 dBm, and decreased gradually for

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Fig. 15. Measured RX band noise at different test configurations when dc/dc converter biases the PA.

Fig. 13. Photograph of the evaluation board to test the PA and the dc/dc converter.

Fig. 14. Measured efficiency and gain versus when the PA is biased through various power control schemes, and the converter output voltage when the PA is biased through the converter. versus

levels lower than 25 dBm, which is a typical behavior for a buck converter. By controlling the through the converter, up to 25-percentage-point improvement in the PAE of the PA was observed compared to the fixed VDD and varying case (Case 1). For example, at dBm, the improvement in PAE was approximately 23-percentage-points. DC/DC converters can generate significant spurious noise in the TX and RX bands due to the switching action. A differential dc/dc converter provides a number of advantages over a comparable single phase converter. Operating two parallel buck converters 180 apart into a common filter capacitor reduces the output voltage ripple by more than three times when compared to an equivalent-sized single-phase converter. In a differential converter, the NFET switching current transients into ground are doubled in frequency and are reduced to half of the amplitude of a comparable single phase converter. For example, the nominal clock frequency was set at 1.6 MHz in this design, but edges in the NFET ground currents will occur at twice that rate. The dc/dc converter was designed with various features such that it can be operated in differential or common modes.

Among various spurious reduction techniques [19], [20], randomly dithering the switching frequency between 1–2 MHz was implemented to reduce spurious emissions in both TX and RX bands. In order to measure the spurious noise generated by the dc/dc converter, the RX band noise was measured for various different test configurations, while the dc/dc converter was providing the dc bias to the PA, as shown in Fig. 15. The tests were performed using a Rohde and Schwarz FSEB spectrum analyzer. Linear averaging factor of 100, root mean square (rms) power detector, and a resolution bandwidth of 100 kHz were used in the spectrum analyzer for the measurements. The TX frequency was 915 MHz. All the parts tested included an integrated bias circuit, rather than an external bias voltage, for dc biasing the gates of the IPMOS devices. Only LB RX band noise was tested due to setup constraints and more stringent specifications at this band. At full power level, the measured RX band noise power was better than 83 dBm between 925–960 MHz, which is below the European Telecommunications Standards Institute (ETSI) specifications. At full output voltage, the dc/dc converter does not switch, but some spurious emissions still existed due to clock noise. On the other hand, when the output voltage of the dc/dc converter is reduced, it starts switching, and the RX band noise floor increases to a range from 78 to 74 dBm (with dithering) and from 925 to 960 MHz. The output voltage of the dc/dc converter was adjusted such that the spurs were maximized for Fig. 15. Significant spurious emission levels were detected for cases when the dithering mode in the converter was turned off. Upon enabling the dithering mode in the converter, the spurious peaks have been substantially reduced since the spurious energy was spread across the band. However, measured RX band noise levels were still not compliant with the ETSI specifications, which requires spur levels lower than 67 dBm between 925–935 MHz, and lower than 79 dBm between 935–960 MHz. In order to understand the noise coupling mechanism better, several other tests were also performed. The IC technology allowed blocking the p-well implant step at selected locations on the design during processing in the foundry so that the epi device layer shown in Fig. 3 does not get p-well implants. Therefore, the device layer resistivity is kept at 10 cm for better isolation.

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At HB, PAE of 45%–53% was achieved across the band with greater than 33.4-dBm output power. The measured EVM using an EDGE modulated input signal was less than 3.5% up to 29-dBm output power with 28% PAE. A dc/dc buck converter was also integrated in the same die as the power management circuitry. Controlling using the dc/dc converter improved the PAE by up to 25-percentage points. Measured RX band noise and spurious emission levels with the dc/dc converter were also reported. REFERENCES

Fig. 16. Measured RX band noise when: (a) the unused silicon space was not blocked during the p-well implant step in the foundry, (b) the p-well implant was blocked, (c) the dc/dc converter and PA are on separate dies but mounted side by side, and (d) the dc/dc converter is biasing only the Q2 and Q3 IPMOS devices in the multistage PA lineup.

We also tested a case where the dc/dc converter and the multistage PA are on separate dies, but were mounted side by side, as well as a case where the dc/dc converter provides the bias to only second- and third-stage IPMOS devices. The measured results are shown in Fig. 16. Blocking the p-well implant in the unutilized space between the dc/dc converter and the PA improved the RX band noise by approximately 2 dB. Having separate dc/dc converter and PA dies side by side improved the RX band noise by an additional 2 dB. This latter result shows that the noise coupling mechanism is not purely within the die, but also related with how the dc/dc converter and PA are tied together. In the carrying laminate and evaluation board, the grounds for the PA and dc/dc converter were all separate and the connection was made using cable assembly externally. Extensive experiments were also performed with the output filter of the dc/dc converter; however, no significant spur improvement was observed. In the last case where the dc/dc converter was biasing the last two stages of the multistage PA, significant reduction in spurious emissions, which was also below the ETSI specifications, was measured as shown in Fig. 16. This result suggests that the first-stage IPMOS device in the multistage PA plays a significant role. Not having the first stage reduced the gain by about 10 dB; hence, the coupled noise was not amplified compared to a three-stage PA. The results also suggest that the first-stage PA and the accompanying matching circuitry must be located as far away as possible from the noise generation circuitry such that minimal noise is coupled. V. CONCLUSION An RF HVCMOS technology was presented for cost-effective monolithic integration of cellular RF TX functions. The technology integrated a modified RF power LDMOS transistor capable of nearly comparable linear and saturated RF power characteristics to GaAs solutions at cellular frequency bands. Measured results for multistage cellular PA designs processed on bulk-Si and SOI on high-resistivity Si substrates (1 k cm) were presented. At cellular LB, measured and PAE were similar to commercially available GaAs HBT-based PAs.

[1] A. Upton and V. Steel, “The current state of technology and future trends in wireless communications and applications,” Microw. J., vol. 49, no. 9, pp. 22–38, Sep. 2006. [2] R. Jos, “Technology developments driving an evolution of cellular power amplifiers to integrated RF front-end modules,” IEEE J. Solid-State Circuits, vol. 36, no. 9, pp. 1382–1389, Sep. 2001. [3] P. V. Wright, “Integrated front-end modules for cell phones,” in IEEE Ultrason. Symp., Sep. 2005, vol. 1, pp. 564–572. [4] J. Costa, M. Carroll, J. Jorgenson, T. McKay, T. Ivanov, T. Dinh, D. Kozuch, G. Remoundos, D. Kerr, A. Tombak, J. McMacken, and M. Zybura, “A silicon RFCMOS SOI technology for integrated cellular/ WLAN RF TX modules,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2007, pp. 445–448. [5] I. Aoki, S. Kee, R. Magoon, R. Aparicio, F. Bohn, J. Zachan, G. Hatcher, D. McClymont, and A. Hajimiri, “A fully-integrated quad-band GSM/GPRS CMOS power amplifier,” IEEE J. Solid-State Circuits, vol. 43, no. 12, pp. 2747–2758, Dec. 2008. [6] B. Jin, K. Han, J. Choi, D. Kang, and B. Kim, “The fully integrated CMOS RF power amplifier using the semi-lumped transformer,” Microw. Opt. Technol. Lett., vol. 50, no. 11, pp. 2857–2860, Nov. 2008. [7] Y. Tan, M. Kumar, C. Jun, and J. K. O. Sin, “A SOI LDMOS technology compatible with CMOS, BJT, and passive components for fully-integrated RF power amplifiers,” IEEE Trans. Electron Devices, vol. 48, no. 10, pp. 2428–2433, Oct. 2001. [8] A. Tombak, R. J. Baeten, J. D. Jorgenson, and D. C. Dening, “A flipchip silicon IPMOS power amplifier and a DC/DC converter for GSM 850/900/1800/1900 MHz systems,” in IEEE RFIC Symp., Jun. 2007, pp. 79–82. [9] A. Tombak, R. J. Baeten, J. D. Jorgenson, and D. C. Dening, “Integration of a cellular handset power amplifier and a DC/DC converter in a silicon-on-insulator (SOI) technology,” in IEEE RFIC Symp., Jun. 2008, pp. 413–416. [10] J. Costa, T. Ivanov, and M. Carroll, “Integrated power devices and signal isolation structure,” U.S. Patent 7 135 766, Nov. 14, 2006. [11] A. Pallotta, F. Pidala, L. Labate, and A. Moscatelli, “Quad-band GSM silicon PA module on LTCC embedding a coupler-based RF power controller,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2007, pp. 163–166. [12] J. Pusl, S. Sridharan, D. Helms, P. Antognetti, and M. Doherty, “A silicon germanium, high efficiency power amplifier chipset for GSM/DCS-PCS/WCDMA handset applications,” in Eur. Microw. Conf., Sep. 24–26, 2001, pp. 1–4. [13] P. M. Asbeck, L. Larson, Z. Popović, and T. Itoh, “Power amplifier approaches for high efficiency and linearity,” in RF Technologies for Low Power Wireless Communications, T. Itoh, G. Haddad, and J. Harvey, Eds. New York: Wiley, 2001, ch. 6. [14] G. Hanington, P. Chen, P. Asbeck, and L. Larson, “High-efficiency power amplifier using dynamic power-supply voltage for CDMA applications,” IEEE Trans. Microw. Theory Tech., vol. 47, no. 8, pp. 1471–1476, Aug. 1999. [15] J. Choi, D. Kim, D. Kang, and B. Kim, “A new power management IC architecture for envelope tracking power amplifier,” IEEE Trans. Microw. Theory Tech., vol. 59, no. 7, pp. 1796–1802, Jul. 2011. [16] N. Wang, V. Yousefzadeh, D. Maksimovic, S. Pajic, and Z. Popović, “60% efficient 10 GHz power amplifier with dynamic drain bias control,” IEEE Trans. Microw. Theory Tech., vol. 52, no. 3, pp. 1077–1081, Mar. 2003. [17] V. Yousefzadeh, N. Wang, Z. Popović, and D. Maksimovic, “A digitally controlled DC/DC converter for an RF power amplifier,” IEEE Trans. Power Electron., vol. 21, no. 1, pp. 164–172, Jan. 2006.

TOMBAK et al.: HIGH-EFFICIENCY CELLULAR PAs BASED ON MODIFIED LDMOS PROCESS

[18] D. Dening, “Multi-phase switching power supply for mobile telephone applications,” U.S. Patent 7 301 400, Nov. 27, 2007. [19] H. Kobayashi and P. M. Asbeck, “Active cancellation of switching noise for DC–DC converter-driven RF power amplifiers,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2002, vol. 3, pp. 1647–1650. [20] E. J. Kim, C.-H. Cho, W. Kim, C.-H. Lee, and J. Laskar, “Spurious noise reduction by modulating switching frequency in DC-to-DC converter for RF power amplifier,” in IEEE Radio Freq. Integr. Circuits Symp., May 23–25, 2010, pp. 43–46. Ali Tombak received the B.S. degree in electrical engineering from the Middle East Technical University, Ankara, Turkey in 1999, the M.S. degree in electrical engineering from North Carolina State University, Raleigh, in 2000, and the Ph.D. degree in electrical engineering from The University of Michigan at Ann Arbor, in 2004. From 1998 to 1999, he was with ASELSAN Military Electronics Inc., Ankara, Turkey. From 1999 to 2004, he was a Graduate Research Assistant with North Carolina State University and The University of Michigan at Ann Arbor. Upon graduation, he joined the Corporate Research and Development Department, RFMD Inc., Greensboro, NC. He is currently a Staff Design Engineer in the Technology Platforms Organization, RFMD Inc. He has authored over 29 journal and conference publications. He holds one U.S. patent. His research interests include high-frequency PAs and switches for cellular and wireless local area network (WLAN) applications based on bulk silicon, SOI, and silicon–germanium (SiGe)-based IC technologies. Dr. Tombak was an elected Board member of Turkish–American Scientists and Scholars Association (2005–2007). He was the recipient of several spotlight awards at RFMD Inc. for his outstanding contributions in securing several strategic design wins to the company. He was also the recipient of a 1999 Turkish Scientific and Technical Research Council (TUBITAK) North American Treaty Organization (NATO) scholarship and the First Degree of the National Science Olympiads on Physics organized by TUBITAK in 1993.

David C. Dening received the B.S. degree from Clarkson College of Technology, Potsdam, NY, in 1967, the M.S. and Ph.D. degrees in physics from Rensselaer Polytechnic Institute, Troy, NY, in 1973, and the M.S.E.E. and Ph.D. degrees in electrical engineering from Virginia Polytechnic Institute and State University, Blacksburg, in 1975 and 1984. In 1978, he joined the Electronics Laboratory (then General Electric), where he was involved with high-temperature ICs, and later designed monolithic microwave integrated circuit (MMIC) amplifiers. In 1996, he joined RF Micro Devices, Greensboro, NC, where he was a Senior Staff Engineer. In 2011, he retired from RFMD Inc., and joined the Skyworks Inc. Design Center, Greensboro, NC. He has been engaged in analog, digital, and RF IC design using CMOS, HBT, and pseudomorphic HEMT (pHEMT) technologies. His designs include switch mode power supplies, 100-V monolithic charge pumps, drivers for microelectromechanical systems (MEMS) switches, and numerous RF amplifiers and products. He holds over 25 U.S patents.

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Michael S. Carroll received the Ph.D. degree in electrical engineering from the University of Florida, Gainesville, FL in 1995. He was a Member of Technical Staff with AT&T Bell Laboratories, Lucent Technologies, and Agere Systems in Orlando, FL, from 1995 through 2003. Since 2003, he has been with RFMD Inc. in Greensboro, NC, where he is currently a Senior Manager of Engineering. His current work includes device engineering and design of cellular radio products, including RF PAs and antenna switches.

Julio Costa was born in São Paulo, Brazil. He received the B.S. degree from the University of Wisconsin–Madison, in 1984, and the M.S. and Ph.D. degrees from the University of Minnesota at Minneapolis–St. Paul, in 1987 and 1991, respectively, all in electrical engineering. From 1991 to 2001, he was with the Motorola Semiconductor Products Sector (now Freescale), where he was a Researcher and Technical Manager involved with silicon and GaAs RF technology development. Until 2002, he was with ON Semiconductor, where he was a Director of research and development and focused on power management technology solutions. He is currently a Director of Technology Development with RFMD Inc., Greensboro, NC, where, since 2002, he has led a group of researchers focusing on SOI and RF MEMS technologies for next-generation wireless systems. He has authored or coauthored over 40 publications and presentations. He holds 19 patents in the area of device and process technologies in RF.

Edward Spears received the B.S. degree in electrical engineering from City College of New York, New York, NY, in 1981. From 1981 to 1999, he was with Motorola Inc. In 1999, he joined RFMD Inc., Greensboro, NC, where he is currently the Director of Advanced Development with the Technology Platforms Organization, and managing a research group of senior researchers in advanced circuit design and technology development. He has authored 13 journal and conference publications. He holds six U.S. patents. His current research interests include high-performance PA design in GaAs and silicon technologies.

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-Band and -Band Power Amplifiers in 45-nm CMOS SOI Joohwa Kim, Member, IEEE, Hayg Dabag, Student Member, IEEE, Peter Asbeck, Fellow, IEEE, and James F. Buckwalter, Member, IEEE

Abstract—The performance of high-efficiency millimeter-wave (mm-wave) power amplifiers (PAs) implemented in a 45-nm silicon-on-insulator (SOI) process is presented. Multistage class-AB designs are investigated for - and -bands and a push–pull amplifier is investigated at -band. The -band, class-AB PA achieves a saturated output power of 15 dBm and power-added efficiency (PAE) of 27% from a 2-V supply. The -band, class-AB PA achieves a saturated output power of 12.4 dBm and PAE of 14.2% from a 2-V supply. The performance demonstrates the high efficiency possible for mm-wave PAs in a SOI process. Index Terms—Millimeter wave (mm wave), mm-wave power amplifier (PA), -band, silicon-on-insulator (SOI), silicon RF integrated circuit (RFIC), -band.

I. INTRODUCTION

M

ILLIMETER-WAVE (mm-wave) bands will support a growing range of terrestrial wireless communication, satellite communication, and automotive radar. In particular, -band is particularly relevant for satellite communication, while -band applications include point-to-point communication as well as imaging [1]. Compound semiconductor monolithic microwave integrated circuits (MMICs) have been a preferred choice for such applications because these processes offer both high output power and high efficiency; recent work in GaN has demonstrated nearly 1 W at 88 GHz [2]. Broader commercialization motivates lower cost technologies. An attractive candidate for replacing the III–V devices in power amplifiers (PAs) are devices native to silicon processes. While highly scaled CMOS processes have high cutoff frequencies, field-effect transistors (FETs) in these processes are susceptible to numerous breakdown issues that limit the drain voltage and traditionally do not favor high-performance PA applications. Breakdown in a 45-nm CMOS FET dictates a nominal supply voltage of around 1 V. Therefore, the high-frequency output power obtained from a single device is limited by the width of Manuscript received October 02, 2011; revised March 15, 2012; accepted March 19, 2012. Date of publication May 08, 2012; date of current version May 25, 2012. This work was supported by the Defense Advanced Research Projects Agency (DARPA) under the ELASTx Program and by DARPA under the LEAP Program. J. Kim was with the Electrical and Computer Engineering Department, University of California at San Diego, La Jolla, CA 92093-0409 USA. He is now with Marvell Semiconductor, Santa Clara, CA 95054 USA (e-mail: joohwa. [email protected]). H. Dabag, P. Asbeck, and J. F. Buckwalter are with the Department of Electrical and Computer Engineering, University of California at San Diego, La Jolla, CA 92093 USA. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2012.2193593

the FET. Wide devices present low-impedance levels at the transistor’s gate and drain, which makes the mm-wave circuit design susceptible to the low quality factor associated with inherent device and interconnect parasitic capacitances. These losses in the device interconnects and matching networks significantly lowers the efficiency of mm-wave PAs. This paper compares the implementation of three mm-wave PAs at - and -bands using a 45-nm CMOS SOI process. In Section II, the small- and large-signal characterization of the devices are discussed. In Section III, two -band PA designs are presented based on a class-AB and push–pull amplifier circuit and discussed. The push–pull amplifier uses both n-FET and p-FET devices to produce gain at 45 GHz and is possible due to the high of both devices in this process. Additionally, a -band PA is presented based on a class-AB amplifier. Circuit measurements are reported in Section IV along with comparisons between the designs and the state-of-the art. The 45-nm CMOS silicon-on-insulator (SOI) process is shown to offer high PAE at mm-wave bands. II. 45-nm SOI CMOS PROCESS The native n-FET in this CMOS SOI process has an effective of 380 GHz. gate length of 40 nm and a cutoff frequency However, device contacts and interconnects significantly reduce the and of the native device. Characterization of in this process is highly dependent on the device layout and the parasitics associated with the interconnect stack. An 11-metal option is available with a top aluminum interconnect layer m . The top m and two thick copper layers aluminum layer is 9 m above the substrate. Capacitance of the floating source and drain nodes are reduced by a 145-nmthick buried-oxide layer (BOX), which reduces the losses in the cm) silicon substrate. relatively low resistivity (13 and is plotted versus the drain current The simulated density based on the layout of a single-contact 160- m n-FET in Fig. 1. The drain, gate, and source connections are simulated with an electromagnetic (EM) field solver (SONNET) from the top metal layer to the second metal layer. For physical connections between the device diffusions and the second metal layer, extraction of the layout of the device is used. The device layout introduces parasitic gate–source and gate–drain capacitance of approximately 0.05 fF per micrometer. For example, the 160- m n-FET broken into 160 1- m fingers has an additional parasitic gate–source and gate–drain capacitance of 8 fF. Additionally, the parasitic capacitances between gate, drain, and source to the substrate is also about 3.5 4 fF. Whereas the native device model, i.e., excluding layout parasitics, is 380 GHz, these layout parasitic capacitances reduce

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Fig. 1. Simulated for a 40-nm n-FET. The inset illustration shows device and SONNET modeling for metal inthe combination of extracted terconnects.

Fig. 2. Simulated (solid) and measured (dotted) I–V characterization of an n-FET. The measured 250- m n-FET is normalized to 1 m. The measurement setup is limited to a current 100 mA.

the native device by around 40% and 50%. Above a current density of 0.27 mA m, both and are greater than 200 GHz for the extracted device. The simulated and measured large-signal drain current behavior of a large (250- m) n-FET is plotted in Fig. 2. A slightly larger width is measured because a 160- m n-FET test structure was not available. The dc current is normalized to 1 m of device width to account for the actual design. The I–V curves are measured for a fixed gate–source voltage . The drain current is measured as the drain voltage is swept from 0 to 2 V. The swept I–V measurement saturates at 100 mA and constrains the peak measured current density for this device to 0.4 mA m. The device undergoes a burn-in process where the gate is exposed to an RF (1 GHz) signal under nominal bias conditions. To best fit the simulated I–V characteristic to the measured behavior, a 2- series source resistance is included in the simulation of the 250- m device. This resistance de-embeds the cable, probe contact, and on-chip interconnect resistance in the test setup.

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Fig. 3. Measured phase and attenuation versus frequency for a 670- m-long s-CPW transmission line.

The measured I–V curves exhibit many of the known limitations of high-scaled FETs. Above V, drain-induced barrier lowering is evident. The high gate bias curve suggests a peak drain current density of around 0.4 mA m at a knee voltage of 0.5 V. The devices were measured to a maximum drain–source voltage of 2.5 V where destructive behavior was observed. This suggested that devices will handle drain voltages of 2 V. A class-A load-line resistance of 3750 k m is characterized from these simulations considering a bias voltage of 1 V. All transmission lines are custom implementations based on a shielded coplanar waveguide (s-CPW) with the signal on the top aluminum metal m and the shield on an intermediate metal layer 6.3- m below the top metal [3]. The shielded microstrip transmission lines prevent currents from being induced in the low-resistivity substrate. The characteristic impedance is chosen with the linewidth and side shielding spacing and a characteristic impedance of 50 is realized for a width and spacing of 8 m. Fig. 3 shows measurements of a 670- m s-CPW transmission line. This line is designed to be close to 90 at 45 GHz and the measurement is de-embedded to the pads of the test structure. The measured phase shift suggests that a transmission line has a length of 780 m. is 0.5 dB. Accordingly, the attenuation of the s-CPW of the Normalizing these constants, the phase constant is 114 mm and attenuation constant is 0.64 dB/mm and suggests a quality factor of 17 at 45 GHz. III. mm-Wave PA DESIGN CONSTRAINTS Power-added efficiency (PAE) in mm-wave amplifiers is predicted from a combination of device and circuit design factors. The PAE is bounded by the product of factors that depend on gain , knee voltage or minimum voltage swing , and supply , waveform shape factor , and the loss factor associated with output matching network (1)

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The first term applies to unilateral amplifiers assuming the drain efficiency is 100%. In this case, the difference between the input power and output power limits the amplifier performance and low gain at mm-wave bands limits that PAE. The second term is a characteristic of only the transistor operation limits. The knee voltage keeps the transistor in saturation where the are highest. It is desirable to provide the largest supply voltage to the device without compromising the transistor reliability. To this end, FET stacking has been proposed at mm-wave bands to allow high supply voltages without exposing individual devices to anything greater than nominal supplies [4], [5]. The third term is determined by the passives available in a monolithic process. Low matching element quality factor limits the effectiveness of using high-impedance transformations to increase the output power of the transistor. For an match, the loss factor is where is the quality factor of the passive elements and is the impedance transformation. The load-line resistance of the transistor determines the required impedance transformation. Wider devices will reduce the load-line resistance and require more impedance transformation into a 50- load. The quality factor of the on-chip s-CPW transmission lines suggests that should be small relative to to avoid significant loss in the output matching network. For of 15, the impedance transformation should be under four to prevent more than a decibel of extra loss. Finally, the shape factor ranges from one-half to one based on the operational class of the amplifier. For class-A operation, the is one-half. Switch-mode amplifiers realize drain efficiencies approaching unity through harmonic tuning of the amplifier. However, tuning the harmonics of a mm-wave signal requires gain at these harmonics. Since the transistor current gain is typically falling off at these harmonics and lower quality factor passives is available at the harmonic frequencies, the harmonic gain is low. For mm-wave PAs, class-A and class-AB amplifiers currently demonstrate the highest PAEs and output power levels. The high of the 45-nm n-FET provides gain at the mm-wave bands. However, thin oxide devices compel a lower supply voltage, which reduces the ratio of shown in the second term. To allow higher , circuits employ cascode or stacked FETs to increase the output power [4]–[6]. From Fig. 2, a 25- load line is realized with a 250- m n-FET and reaches a saturated current of 60 mA. In class-A operation, the single-stage PA is limited to a 1-V supply and saturates at an output power of around 16.5 dBm. Two PA approaches were pursued for -band operation. First, a two-stage class-AB amplifier is presented. Second, a push–pull amplifier is investigated based on the parallel combination of the n-FET and p-FET devices. The p-FET devices in the 45-nm SOI process offer an of 200 GHz and are suitable for mm-wave operation. A -band amplifier is also demonstrated, which uses a similar topology to the -band amplifier to provide comparison of performance results. A.

-Band Class-AB PA

The first approach was to investigate a class-AB mm-wave PA. The schematic of the proposed two stage PA is shown in Fig. 4. To allow the transistor to operate under higher bias

Fig. 4. Schematic of -band PA (biasing not shown). Transmission-line geometry is specified according to width m space m length m .

voltages, a cascode stage is employed in the two stages. Additionally, the cascode improves the stability by isolating the gate–drain capacitance of the common-source FET. The first stage is a class- pre-driver, which provides gain. The second stage is designed for class-AB operation. Input and output matching networks are implemented with s-CPW lines. All capacitors are implemented using metal–oxide–metal (MOM) interdigitated capacitors. The capacitor (387 fF) provides dc blocking, as well as input impedance matching. Transmission line has a length of 160 m pH to provide shunt loading of the first stage. Interstage matching between the first and second stage is realized through capacitor (147 fF). Transmission line is an inductive shunt load pH for the class-AB second stage. The output matching is realized using a single open-stub transmission line . The remaining circuit parameters for the -band class AB are summarized in the table in Fig. 4. Circuit simulations are performed using the extracted device model described in Section II with EM simulations (SONNET) for all transmission-line elements, except for interdigitated capacitors, which rely on design kit modeling. Simulated results for the two-stage amplifier indicate a peak gain at 45 GHz of 28 dB (see Fig. 8). The 3-dB bandwidth is 6.3 GHz from 42.7 to 48.4 GHz. The input matching extends from 41 to 50 GHz or roughly 20% bandwidth. Circuit simulations that incorporate EM modeling of passive structures predict that the PAE of the two-stage design should reach a PAE of 33% at a peak output power of 17 dBm. B.

-band Push–Pull PA

An alternative approach at -band is the push–pull PA illustrated in Fig. 5. This amplifier utilizes a shunt combination of the n-FET and p-FET devices to source and sink current into the load. The push–pull amplifier is novel at mm-wave bands since highly scaled p-FETs only recently have demonstrated sufficiently high . With a gate length of 40 nm, the of 280 GHz based on the native device model and reduces to 200 GHz considering the layout parasitic resistance and capacitance of the interconnect. Notably, the degradation in the of the pMOS

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Fig. 5. Schematic of -band push–pull PA (biasing not shown). Transmissionline geometry is specified according to width m space m length m .

device is not as substantial as is observed from the n-FET. Since this amplifier does not use a tuned load, the frequency response offers more bandwidth than is present for the tuned class AB [5]. The push–pull PA limits the maximum device size at high frequency. The p-FET is limited by the lower hole mobility. Therefore, the same transconductance requires the width of the p-FET to be approximately twice as wide as the n-FET. Therefore, the combination of the n-FET and p-FET gate–source capacitances substantially increases the capacitance seen at the input of the amplifier. As the n-FET and p-FET width increases, both the input and output capacitances are increased and the output impedance is reduced. Consequently, a high-impedance transformation is required to resonate with the output capacitance at the mm-wave frequency. From simulation, a 60- m n-FET (100- m p-FET) achieves the highest PAE. The input matching is realized using a single short-stub transmission line pH . The capacitor (387 fF) is used to provide dc blocking. The capacitors and (118 fF) are used to provide appropriate biasing for class-B operation of both n-FET and p-FET devices. The interstage matching between the first and second stage is realized using the transmission line . The second-stage devices are identical with the first stage and both n-FET and p-FET are biased at class-B operation. The output matching is also realized using a single short-stub transmission line pH . Note that biasing of all the gates is provided through resistors of 1 , which are not shown in the schematic. Simulated results for the two-stage push–pull amplifier based on the extracted model for the active devices and the EM simulation for transmission-line loads predict a gain of 7.3 dB at 48 GHz with a 3-dB bandwidth of 20 GHz (from 37 to 57 GHz) (see Fig. 10). The input impedance is matched to 50 over 44 48 GHz dB . Simulations of the PAE at 45 GHz indicate that the two-stage design reached a PAE of 20% at a peak output power of 10 dBm. C.

-Band Class-AB PA

The -band PA is shown in Fig. 6. The circuit topology is similar to the -band with changes to the matching elements summarized in Fig. 6. Lower quality factor of the matching elements offers a wideband frequency response between 70–100 GHz. A peak gain of 12 dB is simulated at 84 GHz (see Fig. 12). At this higher frequency, the gain of the amplifier is reduced by 10 dB, or roughly 5 dB per stage, relative to the

Fig. 6. Schematic of -band class-AB PA (biasing not shown). Transmissionline geometry is specified according to width m space m length m .

-band simulation. The simulated peak PAE is 19.4% at the peak output power of 14 dBm. Therefore, comparison of the peak output power and PAE at and -band suggests that the power reduces by 3 dB and the PAE drops by 13.6%. IV. MEASUREMENTS All PA circuits are implemented in a 45-nm SOI CMOS technology. The effective gate length of the process is 40 nm. The chip microphotographs are shown in Fig. 7. The -band, class-AB PA measures 460 m by 940 m. The -band, push–pull PA measures 640 m by 770 m, and the -band, class-AB PA measures 440 m by 730 m including pads. A. Measurement Procedure Small-signal -parameters are measured using the Agilent E8361A two-port network analyzer using on-chip probing with Picoprobe coplanar 67A ground–signal–ground (GSG) probes. Careful and repeatable calibration of test setup losses is necessary for accurate power and PAE measurement. The large-signal characterization is made using an Agilent E4400 spectrum analyzer and Agilent E4419B power meter with 8487A 50-GHz power sensor. The spectrum analyzer is used to observe potential oscillations under large-signal conditions. Since the Agilent E8257D power signal generator (PSG) output power is limited to 14 dBm for frequencies above 30 GHz, an external PA (MARKI A2050) is used to compensate for the cable loss. An Agilent 10-dB directional coupler (AG 87301) is used to sense the input and output power an Agilent E4419B power meter. To ensure the PA is not exhibiting any oscillation, another 10-dB directional coupler is used at the output node to feed an Agilent E4448A power spectrum analyzer (PSA). Probe losses are calibrated from a CS-5 calibration substrate at 0.4 dB at 45 GHz. B.

-Band Class-AB PA

The simulated and measured -parameters are shown in Fig. 8 from 40 to 50 GHz. An inset plot shows the -parameters from 0 to 50 GHz. The peak measured gain is 20 dB and is around 6 dB under the simulated peak gain. Sources for this discrepancy stem from overly optimistic quality factor for

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Fig. 8. Simulated (dashed) and measured (solid) class-AB PA.

-parameter of the

Fig. 9. Measured large-signal gain and efficiency of the at 45 GHz.

-band

-band class-AB PA

the lower supply conditions, the PAE increases to 27.5%, while the saturated power is 15 dBm. During several hours of testing, no appreciable degradation in the gain was observed. Longterm reliability of mm-wave amplifiers based on the 45-nm SOI technology remains an important consideration for operating at higher supply voltages. Fig. 7. Microphotograph of a -band class-AB PA (top), PA (center), and -band class-AB PA (bottom).

-band push–pull

interdigitated capacitors forming the dc decoupling network to the gate and higher than expected losses in transmission-line elements. The input matching is satisfied over the 9-GHz bandwidth. The large-signal behavior of the PA at 45 GHz is plotted in Fig. 9 for two supply conditions: 2 and 2.5 V. As has been discussed in the device characterization, the supply for a single device can reach 2 V without evident destructive behavior. In the cascode amplifier, the supply is shared across both transistors, but high RF output power causes a large swing across the gate–drain junction of the cascode device. The input power at the higher supply reaches a PAE of 22.5% at 16.5 dBm. Under

C.

-Band Push–Pull PA

The simulated and measured -parameters of the push–pull PA are shown in Fig. 10 from 40 to 50 GHz. The peak gain is 7 dB for the two-stage amplifier. The input return loss is better than 8 dB and indicates relatively wideband performance. Large-signal characteristics of the push–pull amplifier at 42 GHz are shown in Fig. 11. The peak PAE is 15% at an output power of 9 dBm and the saturated output power is 10.5 dBm. The gain of the amplifier indicates class-B operation at low-power levels. D.

-Band Class-AB PA

The simulated and measured -parameters of the -band PA are shown in Fig. 12 from 70 to 100 GHz. The peak gain is 11 dB from 75 to 90 GHz and the input and output return loss is

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Fig. 10. Simulated (dashed) and measured (simulated) -band push–pull PA.

-parameters of

Fig. 13. Measured gain and PAE of the 80 GHz.

Fig. 14. PAE and Fig. 11. Measured large-signal gain and efficiency of the at 42 GHz.

of the

-band class-AB PA

V at

-band class-AB PA.

-band push–pull PA

The PAE and 1-dB compression point of the -band PA is measured as a function of frequency in Fig. 14. The peak PAE of 14.1% was achieved at 80 GHz. As the PA frequency increases to 90 GHz, the PAE drops to 10% while the power decreases 1.8 dB. E. Comparison to Silicon-Based mm-Wave PAs

Fig. 12. Simulated (dashed) and measured (solid) class-AB PA.

-parameters of

-band

suitable over the same frequency range. The circuit isolation is better than 35 dB over this range. The measured large-signal characteristics at 80 GHz are plotted in Fig. 13. The gain is greater than 11 dB and the saturated output power reaches 12.4 dBm. The peak PAE is 14.1% and is reached for an output power of 12 dBm.

A comparison to work between 40–60 GHz is shown in Table I for silicon and silicon–germanium processes. The measured results are compared at drain supplies of 2 and 2.5 V to demonstrate the peak PAE and performance. While the 45-nm SOI process does not generate power levels comparable to 120-nm SiGe technologies, the peak PAE outperforms other Si/SiGe-based demonstrations. The peak outperforms previous bulk Si and CMOS SOI processes, except recent work using FET stacking in 45-nm CMOS SOI to allow higher supplies (4 V) to achieve greater output power with 20% efficiency [7]. The peak PAE and saturated output power are similar to recently reported records at 60 GHz [8]. A comparison to work at -band (75–110 GHz) is provided in Table II. Again this work demonstrates lower saturated output power compared with recent SiGe PA demonstrations. However, the peak PAE is superior to prior demonstrations. When compared with the 45-GHz class-AB amplifier, the saturated output power has reduced by 2.5 dB and the PAE has dropped

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COMPARISON TO

AND

COMPARISON TO

TABLE I -BAND PAs IN Si/SiGe PROCESSES

TABLE II -BAND PAs in Si/SiGe PROCESSES

by 13% relative for a given two-stage amplifier based on a similar topology. V. CONCLUSIONS This paper has investigated three PA circuits based on class-AB and push–pull circuit topologies implemented in a 45-nm CMOS SOI process. Two-stage amplifiers are determined to offer suitable gain and saturated output power while offering the highest reported PAE compared to other Si and SiGe processes. The -band class-AB PA achieves a saturated output power of 15 dBm and PAE of 27% at a 2-V supply. The -band class-AB PA achieves a saturated output power of 12.4 dBm and PAE of 14.2% at a 2-V supply. ACKNOWLEDGMENT The authors thank Dr. S. Raman, Defense Advanced Research Projects Agency (DARPA) Microsystems Technology Office (MTO), Arlington, VA, and Dr. D. Palmer, Army Research Laboratories, Adelphi, MD. REFERENCES [1] J. May and G. Rebeiz, “High-performance -band SiGe RFICs for passive millimeter-wave imaging,” in Proc. IEEE Radio Freq. Integr. Circuits Symp., Jun. 2009, pp. 437–440. [2] M. Micovic, A. Kurdoghlian, K. Shinohara, S. Burnham, I. Milosavljevic, M. Hu, A. Corrion, A. Fung, R. Lin, L. Samoska, P. Kangaslahti, B. Lambrigtsen, P. Goldsmith, W. S. Wong, A. Schmitz, P. Hashimoto, P. J. Willadsen, and D. H. Chow, “ -band GaN MMIC with 842 mW output power at 88 GHz,” in IEEE MTT-S Int. Microw. Symp. Dig., 2010, pp. 237–239. [3] B. Cetinoneri, Y. A. Atesal, A. Fung, and G. M. Rebeiz, “ -band amplifiers with 6-dB noise figure and milliwatt-level 170–200-GHz doublers in 45-nm CMOS,” IEEE Trans. Microw. Theory Tech., vol. 60, no. 3, pp. 692–701, Mar. 2012. [4] S. Pornpromlikit, J. Jeong, C. D. Presti, A. Scuderi, and P. M. Asbeck, “A watt-level stacked-FET linear power amplifier in silicon-on-insulator CMOS,” IEEE Trans. Microw. Theory Tech., vol. 58, no. 1, pp. 57–64, Jan. 2010.

[5] J. Kim and J. F. Buckwalter, “A 40-Gb/s optical transceiver front-end in 45 nm SOI CMOS technology,” in Proc. IEEE Custom Integr. Circuits Conf. (CICC), 2010, pp. 1–4. [6] S. Leuschner, S. Pinarello, U. Hodel, J.-E. Mueller, and H. Klar, “A 31-dBm, high ruggedness power amplifier in 65-nm standard CMOS with high-efficiency stacked-cascode stages,” in Proc. IEEE Radio Freq. Integr. Circuits Symp., 2010, pp. 395–398. [7] S. Pornpromlikit, H. Dabag, B. Hanafi, J. Kim, L. E. Larson, J. F. Buckwalter, and P. M. Asbeck, “A -band amplifier implemented with stacked 45-nm CMOS FETs,” in Proc. IEEE Compound Semicond. Integr. Circuit Symp., 2011, pp. 1–4. [8] A. Siligaris, Y. Hamada, C. Mounet, C. Raynaud, B. Martineau, N. Deparis, N. Rolland, M. Fukaishi, and P. Vincent, “A 60 GHz power amplifier with 14.5 dBm saturation power and 25% peak PAE in CMOS 65 nm SOI,” IEEE J. Solid-State Circuits, vol. 45, no. 7, pp. 1286–1294, Jul. 2010. [9] U. R. Pfeiffer and D. Goren, “A 23-dBm 60-GHz distributed active transformer in a silicon process technology,” IEEE Trans. Microw. Theory Tech., vol. 55, no. 5, pp. 857–865, May 2007. [10] N. Kalantari and J. F. Buckwalter, “A 19.4 dBm, -band class-E power amplifier in a 0.12 m SiGe BiCMOS process,” IEEE Microw. Wireless Compon. Lett., vol. 20, no. 5, pp. 283–285, May 2010. [11] K. Raczkowski, S. Thijs, W. De Raedt, B. Nauwelaers, and P. Wambacq, “50-to-67 GHz ESD-protected power amplifiers in digital 45 nm LP CMOS,” in Proc. IEEE Int. Solid-State Circuits Conf. Tech. Dig., 2009, pp. 382–383. [12] W. L. Chan and J. R. Long, “A 58–65 GHz neutralized CMOS power amplifier with PAE above 10% at 1-V supply,” IEEE J. Solid-State Circuits, vol. 45, no. 3, pp. 554–564, Mar. 2010. [13] H.-T. Dabag, J. Kim, L. E. Larson, J. F. Buckwalter, and P. M. Asbeck, “A 45-GHz SiGe HBT amplifier at greater than 25% efficiency and 30 mW output power,” in Proc. IEEE Bipolar/BiCMOS Circuits Technol. Meeting, 2011, pp. 25–28. [14] Y.-S. Jiang, J.-H. Tsai, and H. Wang, “A -band medium power amplifier in 90 nm CMOS,” IEEE Microw. Wireless Compon. Lett., vol. 18, no. 12, pp. 818–820, 2008. [15] M. Chang and G. M. Rebeiz, “A wideband high-efficiency 79–97 GHz SiGe linear power amplifier with 90 mW output,” in Proc. IEEE Bipolar/BiCMOS Circuits Technol. Meeting, 2008, pp. 69–72. [16] Z. Xu, Q. J. Gu, and M.-C. F. Chang, “A -band current combined and 9.4% maximum PAE in 65 power amplifier with 14.8-dBm nm CMOS,” in Proc. IEEE Radio Freq. Integr. Circuits Symp., 2011, pp. 1–4. [17] D. A. Chan and M. Feng, “A compact -band CMOS power amplifier with gain boosting and short-circuited stub matching for high power and high efficiency operation,” IEEE Microw. Wireless Compon. Lett., vol. 21, no. 2, pp. 98–100, Feb. 2011.

KIM et al.:

-BAND AND

-BAND PAs IN 45-nm CMOS SOI

Joohwa Kim (S’06–M’11) received the B.S. degree in electrical engineering from the University of Arizona, Tucson, in 2007, and the M.S. and Ph.D. degrees in electrical engineering from the University of California at San Diego, La Jolla, in 2009 and 2011, respectively. His doctoral study included high-speed analog, RF, and mm-wave integrated circuit design for wireless and wired communications. He held an internship with the Sun Microsystems Laboratory, Oracle, San Diego, CA, where he was inolved with high-speed circuits for silicon-based on-chip optical interconnects. In 2011, he joined Marvell Semiconductor, Santa Clara, CA, where he is currently involved wtih high-speed I/O interface circuit design. Dr. Kim was the recipient of the 2011 IEEE Circuit and Systems Society Outstanding Young Author Award.

Hayg Dabag (S’10) received the Dipl.-Ing degree in electrical engineering from Ruhr University Bochum, Bochum, Germany, in 2008, the M.S. degree in electrical engineering from the University of California at San Diego (UCSD), La Jolla, in 2011, and is currently working toward the Ph.D. degree at UCSD. He attended Purdue University, West Lafayette, IN, as an exchange student during his undergraduate studies. He held two internships with Qualcomm Inc., where he was involved with high-voltage tolerant analog circuits, mixed-signal integrated circuit (IC) design, and DAC behavioral modeling. His research interests include mm-wave amplifier design and digital predistortion of PAs.

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Peter Asbeck (M’75–SM’97–F’00) received the B.S. and Ph.D. degrees from the Massachusetts Institute of Technology (MIT), Cambridge, in 1969 and 1975, respectively. He was with the Sarnoff Research Center, Princeton, NJ, and Philips Laboratory, Briarcliff Manor, NY, during which time he was involved in the areas of quantum electronics and GaAlAs/GaAs laser physics. In 1978, he joined the Rockwell International Science Center, where he was involved in the development of high-speed devices and circuits using III–V compounds and heterojunctions. He pioneered efforts to develop heterojunction bipolar transistors based on GaAlAs/GaAs and InAlAs/InGaAs materials. In 1991, he joined the University of California at San Diego, La Jolla, where he is currently the Skyworks Chair Professor with the Department of Electrical and Computer Engineering. He has authored or coauthored over 350 publications. His research interests are in the development of high-performance transistor technologies and their circuit applications. Dr. Asbeck is a member of the National Academy of Engineering. He has been a Distinguished Lecturer of the IEEE Electron Device Society and the IEEE Microwave Theory and Techniques Society (IEEE MTT-S). He as the recipient of the 2003 IEEE David Sarnoff Award for his work on heterojunction bipolar transistors.

James F. Buckwalter (S’01–M’06) received the Ph.D. degree in electrical engineering from the California Institute of Technology, Pasadena, in 2006. He is currently an Assistant Professor of electrical and computer engineering with the University of California at San Diego (UCSD), La Jolla. From 1999 to 2000, he was a Research Scientist with Telcordia Technologies. During Summer 2004, he was with the IBM T. J. Watson Research Center, Yorktown Heights, NY. In 2006, he joined Luxtera, Carlsbad, CA. In July 2006, he joined the faculty of UCSD. Dr. Buckwalter was the recipient of a 2004 IBM Ph.D. Fellowship, the 2007 Defense Advanced Research Projects Agency (DARPA) Young Faculty Award, and the 2011 National Science Foundation (NSF) CAREER Award.

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A Fully Integrated Watt-Level Linear 900-MHz CMOS RF Power Amplifier for LTE-Applications Brecht François, Student Member, IEEE, and Patrick Reynaert, Senior Member, IEEE

Abstract—There is a growing demand for the implementation of the RF power amplifier (PA) in CMOS technologies, due to its cost and integration benefits. Most of the already reported CMOS PAs do not have sufficient output power nor linearity to cope with the long term evolution (LTE) requirements. In this paper, the linearity requirements for power amplifiers targeting LTE-applications are investigated. Based on this system level analysis, a single-chip fully integrated CMOS power amplifier with sufficient power and linearity for emerging E-UTRA/LTE- applications is designed. This 90-nm LTE-band VIII CMOS linear power amplifier uses a distributed active transformer (DAT) as power combiner and delivers an output power up to 29.4 dBm with 25.8% power-added efficiency (PAE) and has 28-dB small-signal gain. The choice of optimal biasing ensures a very flat gain and small AM-PM distortion up to high output power. While applying an uplink LTE signal, the PA produces 25 dBm of average output power with 15% PAE while obeying the stringent EVM-specifications. Index Terms—CMOS RF power amplifier (PA), distributed active transformer (DAT), linearity optimization, long term evolution (LTE) , power combiner.

I. INTRODUCTION

T

HERE is a tremendous interest from industry in completely integrated radio solutions in CMOS technology. CMOS offers a powerful platform for realizing a fully integrated radio system-on-chip (SoC) with its unparalleled integration level and extensive digital processing capability. CMOS PAs have demonstrated their suitability for advanced wireless communication standards, such as LTE/LTE-advanced and WiMAX, with good performance in output power, efficiency, and linearity performances. Long term evolution (LTE) is the next step forward in cellular 3G services towards the 4G cellular services. LTE is a 3GPP standard that provides an uplink speed of up to 50 Megabits per second (MB/s) and a downlink speed of up to 100 Mbps [1]. LTE will bring many technical benefits to cellular networks. The bandwidth needs to be scalable from 1.25 to 20 MHz [1]. This will accommodate the needs of different network operators that have different bandwidth allocations, and also allow operators to provide different services based on the spectrum. LTE

Manuscript received September 30, 2011; revised January 31, 2012; accepted February 23, 2012. Date of publication March 20, 2012; date of current version May 25, 2012. This work was supported by the European Union’s Seventh Framework Programme (FP7/2007-2013) under Grant 248277 (DRAGON). The authors are with the Microelectronics and Sensors Division (MICAS), Department of Electrical Engineering (ESAT), Catholic University of Leuven, 3001 Leuven, Belgium (e-mail: [email protected]; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2012.2189411

is also expected to improve spectral efficiency in 3G networks, allowing carriers to provide more data and voice services over a given bandwidth. Going to larger bandwidths requires high-linearity performance for the complete band, while not sacrificing in efficiency. Many commercially available power amplifiers (PAs) based on a III-V compound semiconductor can produce a saturated output power much over 30 dBm with peak power-added efficiency (PAEs) greater than 45%, but they need 3–4 dB-backoff from the compression point to meet the 3GPP LTE linearity requirements, resulting in lower overall PAE [2], [3]. Recently, a state-of-the-art linear SiGe dual-standard LTE/WiMAX PA has been reported with a saturated power of 30 dBm and a peak PAE of 30%, but its PAE is less than 20% once backed off around 6 dB to satisfy the WiMAX linearity requirements [4]. Newly, CMOS PAs with on-chip transformers have successfully delivered over 30-dBm saturated output power with the best PAE value around 50% [5], [6], but they need a large back-off to meet the linearity specifications of LTE signals. Nevertheless, standard CMOS is rapidly catching up. Standard CMOS is the desired technology for the implementation of low-cost high-volume products. However, the use of a CMOS technology for a PA design introduces some challenges. Nanoscale CMOS technologies offer the advantage of realizing a design at high frequency, but unfortunately this also implies much lower breakdown voltages. This explains why the PA has been the last subblock to be integrated entirely in a standard CMOS technology. Delivering RF power in excess of 1 W to a 50- load at high operation frequencies in CMOS has been the bottleneck for many years, because it requires a peak-to-peak voltage of at least 20 V [7]. To achieve a large output power in a standard CMOS technology despite the low transistor breakdown voltage, an impedance transformation is required to transform the 50- load to a lower impedance [8]. Unfortunately, the low quality passives in CMOS, such as L–C networks or spiral transformers, fundamentally limit the designer to achieve a high output power when a high transformation ratio is necessary [9]. The distributed active transformer (DAT) allows alleviating the effect of the low-Q passive elements integrated in the output matching network of a standard CMOS process [5], [9], [10] and simultaneously makes it viable to realize a fully-integrated watt-level PAs by using low-breakdown voltage transistors. However, most of the already reported Watt-level CMOS PAs, [5], [7]–[9], [11], [12], do not have sufficient linearity to cope with the LTE linearity requirements so far. This paper presents one of the first implementations of a fully integrated CMOS PA that has both high output power and lin-

0018-9480/$31.00 © 2012 IEEE

FRANÇOIS AND REYNAERT: FULLY INTEGRATED WATT-LEVEL LINEAR 900-MHZ CMOS RF PA FOR LTE-APPLICATIONS

TABLE I EVM REQUIREMENTS FOR THE E-UTRA/LTE-UPLINK SIGNALS DIFFERENT CONSTELLATIONS

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FOR

Fig. 2. Simulated output spectrum of an ideal linear amplifier for different clipping levels while applying an LTE-signal (16-QAM) with 10-MHz bandwidth and 6.92-dB PAPR.

Fig. 1. Simulated EVM with respect to clipping level of an ideal linear amplifier while applying an LTE-signal (16-QAM) with 10-MHz bandwidth and 6.92-dB PAPR.

earity required for LTE-applications. The paper is organized as follows: Section II will outline the targeted specifications of the PA based on spectral mask and EVM requirements. Based on these requirements a system analysis is performed. Section III presents a distributed active transformer based RF PA architecture that can allow generation of high output power on-chip while using low-voltage standard CMOS process. Section V explains the details on the PA implementation. The measurement results of the two-stage PA with clover-shaped DAT will be summarized in Section VI with special attention to the linearity requirements. Finally, Section VII concludes this paper. II. LTE SPECIFICATIONS FOR THE RF PA AND SYSTEM LEVEL EVALUATION In this section, the required linear peak output power, , for an LTE PA is investigated. First, the important LTE requirements are discussed. As mentioned in the introduction, the required average output power from the PA for LTE-applications is 23 dBm, while complying with the LTE 3GPP standard Release 8 EVM and Mask requirements [1]. But the total antenna port average output power may never exceed 23 dBm due to SAR regulations, i.e., class 3 power requirements. Taking into account a 2-dB front-end insertion loss (IL) (switches), a 25-dBm average output power must be feasible at the PA output. In LTE, the uplink transmission scheme is based on singlecarrier FDMA, more specifically DFTS-OFDM, and depending on channel quality, the data is mapped onto a QPSK, 16-QAM, or 64-QAM signal constellation. For signals of this kind, the transmitter must provide large reserves for the peak power to prevent signal compression and thus an increase of the bit error rate at the receiver. The peak power or the peak-to-average ratio (PAPR) of a signal is therefore an important transmitter design criterion. While applying a 16-QAM signal with 10-MHz bandwidth, the PAPR is around 7 dB. For this modulated output signal, the PA must be able to amplify linearly up to 32 dBm

Fig. 3. Flowchart of the system evaluation of the PA with varying the clipping level for LTE applications.

output power. However in practice, a certain degradation of the signal is allowed. Therefore PAs having less peak output power can be used to deliver 25-dBm average output power. In this condition, the output of the amplifier is clipped due to saturation. For each constellation, different EVM limits apply, as shown in Table I. Unlike the QPSK and the 16-QAM modulation, it is still premature to specify the 64-QAM EVM-limit for uplink. In the 3GPP standard, the EVM limit for the 16-QAM modulated signal is defined as 12.5%, but the industry tends to target a much more stringent EVM-limit of 5.6% 25 dB , as shown in Fig. 1. The other most important linearity constraint for an LTE PA is the spectrum emission mask, as shown in Fig. 2 for a signal with 10-MHz bandwidth. Notice that the power values for the out-of-band emissions vary, depending on the resolution bandwidth (30 kHz and 1 MHz), as is common also in the spectrum emission mask for WCDMA and HSPA. The first 1-MHz band adjacent to the occupied channel has a limit of 18 dBm with a resolution bandwidth of 30 kHz, but this is transformed in the figure to 2.77 dBm MHz. More details on the spectrum emission mask can be found in [1] (see Table 6.2.4-1). To investigate the effect of clipping at the output due to saturation of the amplifier, a system level simulation is performed. A PA with hard clipping behavior is simulated to verify the effect of clipping on EVM and output spectrum, as shown in Fig. 3. The constellation of the applied modulated signal is 16-QAM with a bandwidth of 10 MHz. Fig. 1 shows the degradation in EVM with respect to the clipping level of the modulated LTE-signal. Clipping level is defined as shown in Fig. 1. The amplifier still meets the 25 dB EVM limit while the output signal is clipped 4.3 dB.

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Fig. 4. Schematic of the designed DAT and the circuit design of the main amplifier.

On the other hand, the effect of clipping is more severe for the spectral mask requirements. As shown in Fig. 2, an ideal amplifier meets the spectral mask easily. While clipping the modulated signal 3 dB, the amplifier barely meets the stringent spectrum emission mask. Finally, to meet the output power requirements while obeying the linearity requirements, the linear peak output power of the amplifier is calculated in (1), where IL represents the front-end insertion loss (switches) and ACL represents the allowable clipping level (1) To achieve the required 23-dBm average output power for LTEapplications, the PA should be able to linearly amplify up to 29 dBm, since the ACL is 3 dB. The efficiency of linear PAs degrades significantly at power back-off. To improve the average efficiency, the PA should satisfy the LTE specifications close to its peak output power level. Thus, in this work, a highly linear PA is designed to obey the LTE-linearity requirements with high average efficiency. III. DAT-BASED PA DESIGN Section III-A describes the implementation of distributed active transformer. Section III-B explains the design details for the main and driving stage. A. Distributed Active Transformer The DAT was first introduced by Aoki in 2002 [9] and the designed clover shaped DAT is shown in Fig. 4. Its primary side consists of four independent unity transformers that are driven by independent differential amplifiers. The RF power is magnetically coupled from the four primary slabs to the secondary winding. At the secondary side of the DAT power combiner, the voltages add up in the voltage domain to achieve the high voltage levels necessary for a watt-level output into the 50- load. The DAT is not only combining the power of the four differential amplifiers, it also transforms the impedance seen by

each amplifier [8], [9] and the large voltage swing on the secondary loop does not pose any reliability issue since no transistor electrically connected to the large output swing. More information on reliability of the design PA is given in Section IV. The distributed active transformer was implemented in the thick top metal (3.2 M) to maximize the quality factor of both primary and secondary windings. Primary and secondary slabs are separated with the minimal spacing to increase the coupling factor. In other words, the effective resistance loss of the DAT is minimized. The DAT was optimized for the optimal load using the passive power transfer efficiency. The passive power transfer efficiency was both calculated and simulated using a 2.5-D electromagnetic simulator. The calculation was based on the analysis given in [9]. This efficiency calculation is only depending on the quality factors of both windings and on the coupling factor. This optimization resulted in an optimal width for the inner slab of 32 and the outer slab of 52 and their quality factors are 21.2 and 14.8, respectively. This resulted in a theoretical maximum efficiency of 77.6%. The passive power transfer efficiency of a matching network, , can be calculated as the ratio of the power delivered to the load to the power delivered into the network [13]. In terms of scattering parameters, the efficiency expression becomes (2) The simulated passive power transfer efficiency of the DAT, is shown in Fig. 5. The peak passive power transfer efficiency is achieved at the desired operation frequency band, which is close to the calculated efficiency. Due to the huge voltage swing in the secondary winding of the power combiner, the unwanted coupling from output-to-input is significant and becomes even more important when the driver and driving splitting network are realized inside the DAT-transformer, as shown in Fig. 4. To reduce this coupling, the DAT is slightly dented in the middle into a clover shape in order to minimize the length of the driver lines. In addition, the driver lines

FRANÇOIS AND REYNAERT: FULLY INTEGRATED WATT-LEVEL LINEAR 900-MHZ CMOS RF PA FOR LTE-APPLICATIONS

Fig. 5. Passive power transfer efficiency of the DAT versus frequency.

Fig. 6. Driver amplifier and power splitting network.

are realized on top of each other with a spacing of only 0.32 , to increase the coupling factor between the driving lines and decrease the coupling from other close by components, as shown in Fig. 6. This resulted in the very high 0.96 driver line coupling factor. Furthermore, considering a cross sectional view of the chip, the driver lines were realized in the middle metals with 2.39 separation from the thick top metal, used for the DAT combiner, to reduce the coupling slightly further. Moreover, the driver lines are exactly passing in the middle of each differential amplifier and taken into account the symmetry of both the power splitting network and the clover shaped DAT, the magnetic coupling is minimized. Finally, this resulted in the clover shaped DAT and since not only the main amplifiers but also the driver amplifier are inside the DAT, this design proves to be very area efficient. B. Main and Driver Amplifier The clover-shaped magnetically coupled power combiner shown in Fig. 4 is used as the output power combiner. Each main amplifier consists of a push–pull amplifier. The power stage was designed as a Class AB for both good efficiency and linearity.

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Fig. 7. PAE- and the -circles of load–pull simulations of the extracted transistors. The “fat” dot represents the transformed impedance seen at the drain of each side of the differential amplifier. The Smith Chart has a normalized -circles are 4% and 0.5 impedance of 5 . The step used for PAE- and the dB, respectively.

Since the drain of a power core transistor can experience a signal swing at its drain larger than two-times the nominal supply voltage, a cascode structure in the power cell is used so the voltage is divided over both the common source and common gate transistor. The common source transistor has a gate length of 90 nm while the common gate transistor is a 250-nm-thick oxide transistor device. To maximize the efficiency of the amplifier, the 50 load should be transformed in the desired impedance for the optimal operation of the active devices. As already explained, the DAT allows impedance transformation and power combining simultaneously. Additional capacitors at the output and at the primary loop and the parasitic capacitors of the transistors itself, fulfill part of the matching network. The gate widths of the transistors are determined by load–pull simulation to achieve the optimum efficiency and output power. This resulted in optimal gate widths of the common source power transistors, MP1, and the common gate transistors, MP2, of 4.6 and 8.6 mm, respectively. Fig. 7 shows the results for both the PAE- and -circles of the load–pull simulations of the extracted transistors on the Smith Chart. The “fat” dot in Fig. 7 represents the simulated transformed impedance, , seen at the drain by the transistors. The main stage achieves a simulated drain efficiency of 54%. The advantage of differential driving each primary inductor of the DAT, as presented in Fig. 4, is a virtual ground created in the middle of each primary inductor [9]. Consequently, the parasitic leakage inductance of the power combiner is used as the dc feed inductor for the main amplifier. Another advantage of this differential push–pull technique is the reduced coupling of the second harmonics. First of all, the differential pair substantially rejects the even harmonics. Second, since the corners of the clover shaped DAT are virtual grounds, bypass capacitors, , are used to short the impedance at the second harmonic to the AC ground at two common source transistors from the differential power cell. Every bypass capacitor has a certain quality factor, which is proportional to the ratio of the capacitance by the resistance of the capacitor. Since this bypass capacitor is part of the common mode impedance, lowering the quality factor of the capacitor will reduce the impedance over a wide frequency range and minimize the coupling to the substrate, which helps to stabilize

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Fig. 10. Measurement results for PAE (%) and DE (%) when the PA reaches , for different operation frequencies. its peak output power,

Fig. 8. Die photograph of the quad-core fully integrated CMOS PA.

oxide transistor handles a peak of 2.8-V . Therefore, the supply voltage is chosen as 2 V to ensure reliability. In addition, the metal widths of both the DAT-combiner (32 and 52 for the inner and outer slab respectively) and the transistors interconnects and routing are selected and verified to satisfy the electromigration rules at the peak output power. Furthermore, to cope with the high current densities inside the transistors, each interconnect of the transistor subblocks of each PA is constructed using multiple metal layers. V. SILICON IMPLEMENTATION Fig. 8 shows a die micrograph of the chip. The fully integrated quad-core CMOS RF PA is implemented in a standard 90-nm CMOS process. The die size is 1.8 mm 1.85 mm. The PA is designed for the extended GSM-band and for band VIII of the LTE standards. VI. MEASUREMENT RESULTS A. Measurement Setup

Fig. 9. Measured drain efficiency (DE) (%), PAE (%), and gain (dB) versus input power (dBm).

the RF PA [14]. In order to reduce the third harmonic distortion, the common source transistors are biased slightly below the threshold voltage [15]. Similar to the main stage, the driver amplifiers are designed as Class AB amplifiers to obtain good linearity and efficiency. Again, load–pull simulations were performed in order to guarantee an optimal efficiency performance. In this Class AB driver, the bondwire serves as the RF choke. The input of the PA is fully differential, and , as shown in Fig. 4. Matching at the input of the driver stage, to 50 is achieved by tuning the parasitic capacitances of the transistors with the bondwire and together with the stabilizing resistor at the gate, the reflection coefficient is minimized. IV. RELIABILITY Reliability is important for the lifetime of the product. The maximum gate-drain voltage stress on the 1.2-V 90-nm common source transistor is 1.45 V while the 2.5-V-thick

During measurements, the chip is glued on an alumina substrate that is connected to a brass heat sink using thermal conductive glue to allow sufficient thermal dissipation during measurements and to minimize the effects of the thermal variations. All the pins, including the input and output, are wire bonded on the alumina substrate. All output powers are measured using a power meter. B. Experimental Results 1) Single-Tone Characterization: To characterize the gain, power and efficiency of the PA, continuous wave signals are applied to the designed PA at 930 MHz. The measurement results, shown in Fig. 9, illustrate that the PA delivers an output power up to 29.4 dBm with a small-signal gain of 28 dB using a 2-V supply voltage. A power added efficiency (PAE) of 25.8% with 28.4% drain efficiency (DE) is achieved. Fig. 10 shows the performance of the PA across the frequency band. By considering the peak output power, , the 3-dB bandwidth is around 450 MHz. The designed PA still operates at a PAE which is above 24% in the frequency band between 880 MHz–1.09 GHz while achieving an output power of more than 29 dBm and only varying 0.4 dB. In this frequency band, the PAE only varies maximally 2%.

FRANÇOIS AND REYNAERT: FULLY INTEGRATED WATT-LEVEL LINEAR 900-MHZ CMOS RF PA FOR LTE-APPLICATIONS

Fig. 11. Measurement results for DE (%), PAE (%) and peak output power , for different supply voltages, Vdd (V), at 930 MHz. (dBm),

Fig. 12. Measured AM-AM response for different gate bias voltages V, V, and V) at 930 MHz. (

In Fig. 11, the PAE, the drain efficiency and the peak output power, , are investigated as a function of the dc supply voltage. The peak PAE is reached at a supply voltage of 2 V, but with a supply voltage of 2.6 V, the PA is able to deliver an output power up to 31 dBm or 1.26 W with a drain efficiency of 25.3% and 23.4%. 2) AM-AM and AM-PM Distortion: Fig. 12 shows the measured AM-AM response for different gate bias voltage at 930 MHz. Class AB amplifiers suffer both from gain expansion and compression. Gain expansion is known as the effect that the gain slightly increases when the input power is increasing. On the contrary, gain compression happens in the transistors because the transistors’ change in gate voltage doesn’t result in a related change in drain-source voltage. As depicted in Fig. 12, increasing the gate bias voltage, , induces some “early” compression, while decreasing the gate bias, causes gain expansion before the gain compression. Both effects should be minimized in order to optimize EVM for both the driver and main amplifier. Hence, the transistors operating in class AB behavior were biased to achieve maximally flat gain and this is illustrated by the mid-curve in Fig. 12. Fig. 12 shows the AM–AM response for different gate bias voltages ( , and ) which results in 30.97-, 36.28-, and 45.2-mA quiescent current for each transistor respectively. Additionally, the gate bias is slightly adjusted to be as close as possible to the point where the small-signal gain is null, , or in other words to minimize the third order intermodulation products [15]. As retrievable

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Fig. 13. Measured AM-AM and AM-PM response for the optimal gate bias.

Fig. 14. Measurement results for the PAE (%) and the EVM (dB) with and without predistortion versus average output power (dBm) for the applied uplink 10 MHz LTE-signal at 930 MHz.

Fig. 15. Measured output spectrum for the applied 10 MHz uplink LTE-signal at 21.6 dBm average output power at 930 MHz.

from Fig. 12, the point is at 27.7 dBm, which is only 1.7 dB less than the peak output power. Simultaneously with the AM–AM distortion, the AM–PM distortion is measured. The effect of the AM-PM distortion is as important as the AM–AM distortion on the EVM. Just as the measurement for the AM-AM distortion, this measurement was realized by applying an unmodulated carrier to the RF PA while increasing the envelope of the applied signal, based on a pulse profile measurement to avoid the impact of the thermal effects on the AM–AM- or AM–PM-curve profile. This measurement was done with the R&S ZVA-40 Network Analyzer. Fig. 13

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TABLE II PERFORMANCE COMPARISON OF WATT-LEVEL LINEAR CMOS RF PAS

shows the AM–AM and the AM–PM distortion of the designed PA with the optimal bias to achieve maximally flat gain. As seen in the graph, when using the bias on the decision criteria explained above, the phase is only distorted by three degrees over the full operation range up to 29.4 dBm. 3) Measurements With Modulated Signals: The EVM and PAE of the PA for LTE-signals as a function of the desired output power are investigated. The EVM was measured to determine the linearity of the designed PA with the 16-QAM modulated E-UTRA/LTE-signal with a PAPR of 6.92 dB. Fig. 14 shows the EVM and the PAE versus the average output power. The PA satisfies the industry based EVM LTE specifications (5.6%) with 16.5% drain efficiency and 15% PAE while delivering 25 dBm average output power. This is the required output power for LTE taking into account the switch losses at the output, referring to the system analysis in Section II. Thus, the measurement result with the optimal biasing to achieve a flat gain curve, shown by the dotted lines in Fig. 14, already demonstrates that with a peak output power of 29.4 dBm an average output power of 25 dBm is delivered to the load while meeting the stringent industry based EVM-specifications. With the use of a simple look-up based digital predistortion algorithm (DPD), based on the AM-AM and AM-PM distortion measurements from Fig. 13, and with 1 dB hard clipping, the average output power can be further increased from 25 to 25.9 dBm, while obeying the EVM-specifications. This also increases the PAE from 15% to 17% with a drain efficiency of 18.6%, as shown in Fig. 14. This is a relative increase of 13% in efficiency and almost 1 dB more output power is pushed by the amplifier. With this simple DPD, the output power only increases 1 dB. This again proves the already high inherent linear behavior of this PA. The PA still satisfies the LTE spectral mask requirements at 21.6-dBm-average output power. The measured spectrum and mask are shown in Fig. 15. The corresponding ACLR1 is 33.4 and 34.2 dB. As proven in the system level LTE analysis in Section II, the spectral mask requirements are more difficult to obey than the EVM requirements and due to noise pickup in the measurement setup at 1–5-MHz-offset from the channel

bandwidth, the RF PA delivers slightly less output power while obeying the spectral mask specifications than while obeying the EVM requirements. To conclude, the performance of designed PA is summarized and compared to state-of-the-art linear CMOS and commercial PAs in Table II. Unlike all PAs mentioned in this table, the commercial PA is designed in GaAs-technology. Unfortunately, this is one of the first measured LTE PAs for the LTE band VIII while most of the PAs are designed for higher operation frequencies and make use of a higher supply voltage to reach the watt-level output power. In this table, the performance of the designed PA is summarized and shows that the PA delivers higher output power and achieves higher efficiency without any predistortion technique while obeying the EVM-linearity requirements (@-25-dB EVM or 5.6% EVM) for the LTE communication standard. And all this in a very limited area. VII. CONCLUSION In this paper, the linearity requirements for PAs targeting the LTE-performance are investigated. A two-stage watt-level fully integrated RF PA in 90-nm CMOS technology competent of achieving the LTE-performance requirements, is demonstrated. To achieve the watt-level output power, a clover shape DAT combiner is presented. And the driver stage and power splitting network are completely constructed inside the DAT. The PA delivers 29.4-dBm saturated output power with 25.8% PAE using 2-V supply. While applying an uplink LTE signal, the PA produces 25 dBm of average output power with 15% PAE while obeying the stringent EVM-specifications. ACKNOWLEDGMENT The authors would like to thank the support from Ericsson on the LTE standard, as well as their colleague, E. Kaymaksüt, for the many fruitful technical discussions. REFERENCES [1] “User equipment (UE) radio transmission and reception (Release 8)” 2010, 3GPP Tech. Spec. 36.101 v8.3.0.

FRANÇOIS AND REYNAERT: FULLY INTEGRATED WATT-LEVEL LINEAR 900-MHZ CMOS RF PA FOR LTE-APPLICATIONS

[2] Y. Li, J. Lopez, P.-H. Wu, W. Hu, R. Wu, and D. Lie, “A SiGe envelope-tracking power amplifier with an integrated CMOS envelope modulator for mobile WiMAX/3GPP LTE transmitters,” IEEE Trans. Microw. Theory Tech., vol. 59, no. 10, pp. 2525–2536, Oct. 2011. [3] “SKY65126-21:800-900 MHz high linearity 2 W power amplifier” Skyworks, 2011. [Online]. Available: http://www.skyworksinc.com/uploads/documents/200954E.pdf [4] V. Krishnamurthy, K. Hershberger, B. Eplett, J. Dekosky, H. Zhao, D. Poulin, R. Rood, and E. Prince, “SiGe power amplifier ICs for 4G (WiMAX and LTE) mobile and nomadic applications,” in Proc. IEEE Radio Frequency Integr. Circuits Symp. (RFIC), May 2010, pp. 569–572. [5] I. Aoki, S. Kee, R. Magoon, R. Aparicio, F. Bohn, J. Zachan, G. Hatcher, D. McClymont, and A. Hajimiri, “A fully-integrated quad-band GSM/GPRS CMOS power amplifier,” IEEE J. Solid-State Circuits, vol. 43, no. 12, pp. 2747–2758, Dec. 2008. [6] O. Degani, F. Cossoy, S. Shahaf, E. Cohen, V. Kravtsov, O. Sendik, D. Chowdhury, C. Hull, and S. Ravid, “A 90-nm CMOS power amplifier for 802.16e (WiMAX) applications,” IEEE Trans. Microw. Theory Tech., vol. 58, no. 5, pp. 1431–1437, May 2010. [7] K.-C. Tsai and P. Gray, “A 1.9-GHz, 1-W CMOS class-E power amplifier for wireless communications,” IEEE J. Solid-State Circuits, vol. 34, no. 7, pp. 962–970, Jul. 1999. [8] I. Aoki, S. Kee, D. Rutledge, and A. Hajimiri, “Fully integrated CMOS power amplifier design using the distributed active-transformer architecture,” IEEE J. Solid-State Circuits, vol. 37, no. 3, pp. 371–383, Mar. 2002. [9] I. Aoki, S. Kee, D. Rutledge, and A. Hajimiri, “Distributed active transformer—A new power-combining and impedance-transformation technique,” IEEE Trans. Microw. Theory Tech., vol. 50, no. 1, pp. 316–331, Jan. 2002. [10] S. Kim, K. Lee, J. Lee, B. Kim, S. Kee, I. Aoki, and D. Rutledge, “An optimized design of distributed active transformer,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 1, pp. 380–388, Jan. 2005. [11] I. Aoki, S. Kee, D. Rutledge, and A. Hajimiri, “A 2.4-GHz, 2.2-W, 2-V fully-integrated CMOS circular-geometry active-transformer power amplifier,” in IEEE Conf. Custom Integr. Circuits , May 2001, pp. 57–60. [12] O. Lee, K. H. An, H. Kim, D. H. Lee, J. Han, K. S. Yang, C.-H. Lee, H. Kim, and J. Laskar, “Analysis and design of fully integrated highpower parallel-circuit class-E CMOS power amplifiers,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 3, pp. 725–734, Mar. 2010. [13] B. François and P. Reynaert, “A fully integrated CMOS power amplifier for LTE-applications using clover shaped DAT,” in Proc. ESSCIRC, Sep. 2011, pp. 303–306. [14] D. Chowdhury, C. Hull, O. Degani, P. Goyal, Y. Wang, and A. Niknejad, “A single-chip highly linear 2.4 GHz 30 dBm power amplifier in 90 nm CMOS,” in Proc. IEEE Int. Solid-State Circuits Conf., Feb. 2009, pp. 378–379. [15] C. Fager, J. Pedro, N. de Carvalho, H. Zirath, F. Fortes, and M. Rosario, “A comprehensive analysis of IMD behavior in RF CMOS power amplifiers,” IEEE J. Solid-State Circuits, , vol. 39, no. 1, pp. 24–34, Jan. 2004. [16] A. Afsahi, A. Behzad, and L. Larson, “A 65 nm CMOS 2.4 GHz 31.5 dBm power amplifier with a distributed LC power-combining network and improved linearization for WLAN applications,” in Proc. IEEE Int. Solid-State Circuits Conf., Feb. 2010, pp. 452–453.

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[17] A. Afsahi and L. Larson, “An integrated 33.5 dBm linear 2.4 GHz power amplifier in 65 nm CMOS for WLAN applications,” in Proc. IEEE Custom Integr. Circuits Conf. (CICC), Sep. 2010, pp. 1–4. [18] J. Fritzin, C. Svensson, and A. Alvandpour, “A 32 dBm 1.85 GHz class-D outphasing RF PA in 130 nm CMOS for WCDMA/LTE,” in Proc. ESSCIRC, Sep. 2011, pp. 127–130. [19] J. Han, Y. Kim, C. Park, D. Lee, and S. Hong, “A fully-integrated 900-MHz CMOS power amplifier for mobile RFID reader applications,” in Proc. IEEE Radio Frequency Integr. Circuits (RFIC) Symp., Jun. 2006, pp. 4–8.

Brecht François (S’08) was born in Kortrijk, Belgium, in 1984. He received the M.Sc. degree in electronics and electrical engineering from the Catholic University of Leuven (KULeuven), Leuven, Belgium, in 2008, and is currently working toward the Ph.D. degree on the design of CMOS RF PAs at KULeuven. Since 2008, he has been a Teaching and Research Assistant at the MICAS Laboratory, Department of Electrical Engineering (ESAT), KULeuven.

Patrick Reynaert (S’01–M’07–SM’12) was born in Wilrijk, Belgium, in 1976. He received the M.Ing. degree in electronics from the Karel de Grote Hogeschool, Antwerpen, Belgium, in 1998, and received the M.Sc. degree in electrical engineering and Ph.D. degree in engineering science from the Catholic University of Leuven (KULeuven), Leuven, Belgium, in 2001 and 2006, respectively. Since October 2007, he has been an Associate Professor with the Department of Electrical Engineering at KULeuven, and a Staff Member of the ESAT-MICAS Research Group. From 2001 to 2006, he was a Teaching and Research Assistant with the MICAS Research Group of the Department of Electrical Engineering (ESAT), KULeuven. While working toward his Ph.D. degree, his main research focus was on CMOS RF PAs and analog circuit design for mobile and wireless communications. From 2001 to 2006, he was also a Lector with the ACE-Group, Leuven, Belgium were he taught several undergraduate courses on electronic circuit design. During 2006–2007, he was a Postdoctoral Researcher with the Department of Electrical Engineering and Computer Sciences, University of California at Berkeley. At the Berkeley Wireless Research Center, he was working on mm-wave CMOS integrated circuits within the group of Prof. Ali Niknejad. During the Summer of 2007, he was a Visiting Researcher with Infineon, Villach, Austria, where he worked on the linearization of basestation PAs. Dr. Reynaert was the recipient of a Francqui Foundation Fellowship from the Belgian American Educational Foundation.

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Analytical Design Methodology of Outphasing Amplification Systems Using a New Simplified Chireix Combiner Model Mohamed El-Asmar, Member, IEEE, Ahmed Birafane, Mohamed Helaoui, Member, IEEE, Ammar B. Kouki, Senior Member, IEEE, and Fadhel M. Ghannouchi, Fellow, IEEE

Abstract—An analytical design methodology of outphasing amplification systems is proposed using new simplified analytical expressions for the instantaneous efficiency and the input/output voltages of Chireix outphasing combiners. These expressions are derived first for ideal voltage sources with nonzero internal impedance and later for ideal Class-B amplifiers where dc current variation is incorporated. They take into account the impedance mismatch between the amplifiers and the lossless combining structure and account explicitly for the all of the combiner’s electrical parameters. We show that the maximum achievable instantaneous combining efficiency can be controlled in position and in value through the judicious choice of the combiner’s stub length and transmission-line characteristic impedance. We further show that, when this choice is combined with the amplified signal’s distribution, the average combining efficiency can be precisely controlled and easily maximized. Various validations of the proposed expressions are performed by comparison with experimental and simulation results for various combiners as well as for a complete linear amplification with nonlinear components amplifier. Excellent agreement between simulations and measurements is obtained in all cases considered. Index Terms—Chireix combiner, linear amplification with nonlinear components (LINC)-outphasing, linearity, power efficiency, simplified model.

I. INTRODUCTION

P

OWER amplifier efficiency and linearity continue to be key factors in modern wireless communication systems. There is a tradeoff between these two properties, and it is quite a challenge to satisfy both of them simultaneously. The linear amplification with nonlinear components (LINC) technique [1]–[3] is a potential solution that may offer high efficiency with good linearity. In this technique, a complex modulated signal is split into two constant envelope, phase-modulated signals that are amplified by high efficiency nonlinear amplifiers and then combined at the output, as shown in Fig. 1. When a combiner

Manuscript received September 30, 2011; revised March 17, 2012; accepted March 23, 2012. Date of publication May 14, 2012; date of current version May 25, 2012. This work was supported in part by Alberta Innovates Technologies Futures (AITF), the Natural Sciences and Engineering Research Council of Canada (NSERC), and the Canada Research Chairs program. M. El-Asmar, A. Birafane, and A. B. Kouki are with the Communications and Microelectronics Laboratory (LACIME), Department of Electrical Engineering, École de Technologie Supérieure, Montréal, QC Canada H3C 1K3. M. Helaoui and F. M. Ghannouchi are with the Intelligent RF Radio Laboratory, Electrical and Computer Engineering Department, University of Calgary, Calgary, AB Canada T2N 1N4 (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2012.2193897

Fig. 1. Chireix-outphasing amplifier topology.

having matched and isolated ports is used, the LINC amplifier presents good linearity but with degraded efficiency [4]. This efficiency reduction is more pronounced for signals with a high peak-to-average power ratio as the out-of-phase components of the signal cancel out in the isolation resistance of the combiner. Any distortion observed at the output signal in such a case is generally caused by the imbalance between the two RF amplifier branches. Recently, a modified implementation of the LINC concept (MILC) was proposed [5], [6] whereby a mix of the LINC and in-phase decompositions is used to improve efficiency. This technique was tested using resistive combiners which still limit the overall efficiency. To overcome the efficiency limitations of resistive combiners, a class of lossless, outphasing combiners (i.e., Chireix combiners) was considered [2], [7], [8]. Up until recently, all studies cited in the literature on the Chireix-outphasing have been based on the model of [9], (e.g., see [10]). However, this model does not predict, nor account for, the level of distortion observed when the Chireix combiner is used. In [11], a new analytical approach was introduced where rigorous analytical expressions for the output signals and the Chireix combiner’s efficiency were presented. This approach takes into account the unmatched and nonisolated nature of the Chireix combiner and the reflection effects associated with it in a given reference impedance system. In the standard LINC signal decomposition, the amplitude is converted into two modulation of the input signal phase-modulated constant envelope signals and . The expressions giving the various voltages are summarized here following the same notation as in [11]:

0018-9480/$31.00 © 2012 IEEE

(1) (2) (3)

EL-ASMAR et al.: ANALYTICAL DESIGN METHODOLOGY OF OUTPHASING AMPLIFICATION SYSTEMS

where the carrier and the original phase modulation angle have been suppressed and is the LINC decomposition angle corresponding to the added phase modulation (Fig. 1). The mismatches between the two amplifiers, which are assumed , and the inputs of the to present an output impedance of Chireix combiner introduce amplitude and phase distortions in the output voltages Vo1 and Vo2 on both branches. In particular, the input phase is changed to an output phase given implicitly by [11]

(4) where is the normalized characteristic admittance of the combiner lines. Consequently, the normalized character; istic impedance of the combiner lines is given as see Fig. 1. The constant in this equation is related to the stub [11]. It should be susceptance (see Fig. 1) by noted that the susceptance B can be obtained by different circuit elements; an inductance and a capacitance, open-circuited stubs or short-circuited stubs. When using stubs, the characteristic impedance of the stub line does not have to be same as , as long as this characteristic impedance and the stubs lengths are properly done to produce jB susceptances. The expression of the instantaneous efficiency is given in terms of by [11]

(5) While (5) has been proven to be accurate (see [11]), it is far from being intuitive and it is not readily usable for overall efficiency estimation or the design of optimal outphasing combiners. Alternatively, finding the explicit expression of the instantaneous efficiency versus the input phase , instead of , though mathematically feasible by combining (4) and (5), is quite tedious and requires complex mathematical manipulations. In addition, in [11] both output voltage and impedance as complex expressions are given versus the output phase expressions making linearity assessment of the combiner quite cumbersome. In light of these considerations, finding simplified expressions for the Chireix combiner’s efficiency and linearity characteristics versus the LINC decomposition angle is highly desirable and remains an open research question. The remainder of this paper is organized as follows. In Section II, the new simplified expressions for the instantaneous output voltages and efficiency of lossless outphasing combiners and the as a function of the LINC decomposition angle combiner’s parameters are presented. Section III presents theoretical and experimental validations of the newly developed outphasing combiner model. In Section IV, the application of the new model to the optimal design of an outphasing combiner for a given modulated signal is demonstrated with a 16 quadrature amplitude modulation (QAM) signal and validated experimentally. In Section V, an implementation of LINC system with Chireix combiners is investigated using Class-B amplifiers. An analytical expression of the total efficiency incorporating the Chireix combiner’s efficiency and the impact of mutual loading of amplifiers on their dc current consumption is

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proposed. The new equations are validated by comparison with simulations and measurements. Finally, an overall conclusion is presented. II. PROPOSED SIMPLIFIED MODEL In this paper, we show that, following [12], it is possible to simplify analytically the Chireix model of [11]. Judiciously combining (4) and (5), a simplified expression of the instantaneous efficiency as a function of the input LINC decomposition angle is proposed. The simplified expressions of both voltages and efficiency equations versus the input phase are also presented. The proposed expressions are considerably simpler and easier to use than those in [11]. Furthermore, the simplified expressions of Chireix system proposed in this work take into account the reflection and nonisolation effects associated with the Chireix combiner. To validate the simplified model over wide range of Chireix combiner parameters, ADS [13] simulations and experimental measurements are carried out. A. Efficiency Based on (4) and (5) and on the observations given in [12], we can demonstrate that the expression of the instantaneous efficiency takes on the following simplified form (see details in Appendix A): (6) . Clearly, this equation is of the form where is independent of and constant for a given combiner. It is given by

where

(7) which can be written in terms of the characteristic impedance , , as (8) This new simplified expression for the instantaneous efficiency replaces the two complex equations (4) and (5). It offers a more intuitive representation and clearly shows the effect of the stubs on the efficiency of the Chireix system. Indeed, knowing that the matched combiner has an instantaneous efficiency curve that follows a distribution, one can easily see that the effect of using a Chireix combiner with stubs amounts to a shift by , the electrical stub length, in the instantaneous efficiency curve. The maximum efficiency value however can be less than 1 if the proper choice of the line impedance is not made. Indeed, a graphical analysis of (8), whereby the factor is plotted versus for various values, as shown in Fig. 2, clearly illustrates that specific combinations of and values lead to a maximum attainable efficiency of 100%. These curves also illustrate that the required normalized characteristic impedance of the combiner transmission lines must be less than or equal to , with the lower impedances shifting the location of the maximum efficiency towards lower power levels, i.e., greater

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these complex expressions to simple formulas expressed explicitly as a function of instead of . First, we show in Appendix A that (4) can be rewritten as (10) Next, combining this equation with the expressions for reflecas presented in tion coefficients and the input impedances and [11]. We obtain the new simplified expressions for given by (see Appendix B for details)

Fig. 2. Variation of factor in function of stub length of combiner line impedance .

for different values

values. In fact, one can easily see this mathematically by search for the maximum of the factor. Setting the derivate of (8) equal to 0 yields (9) where is the optimal characteristic impedance for a given Chireix stub electric length . This impedance insures that the combiner instantaneous efficiency is maximum for all LINC decomposition angles , and that it reaches 100% when . Equations (6), (8), and (9) are the necessary tools to the design of Chireix combiners that will give the maximum attainable average efficiency for a given modulated signal. Indeed, the probability density function of the modulated signal is first used to identify the average signal level, the level which occurs most often, and the corresponding LINC decomposition angle, . Next, from (6), we can determine directly the required stub length , to place the maximum of the instantaneous efficiency curve at the average power level. Finally, using (9), the characteristic impedance of the combiner lines can be determined. Clearly, lower characteristic impedances are needed for higher peak-to-average signals where the average corresponds to increasing values, , always corresponding to the peak signal level. B. Voltage Expressions Having established the new expression for the instantaneous combining efficiency, we next consider those of the output voltages. Taking into account the impedance mismatching that occurs at the inputs of the Chireix combiner, it was shown in [11] that the constant envelope nature of the input signal is lost at and shown in the output. Indeed, the output voltages, Fig. 1, vary in magnitude and phase versus . These voltages are expressed in terms of instead of , and (4) is again needed to obtain the explicit expressions in terms of the original LINC decomposition angle . Again, the presence of and the need for (4) makes it very difficult to gain any insight into the behavior of the Chireix combiner and its impact on the linearity of the LINC amplifier. Here, we show that it is possible to simplify

(11) This new expression is very simple and shows the explicit dependence of the two voltages on the input phase . The origin of the variation of the above voltages versus is attributed to the Chireix combiner structure especially to the stubs value . The stubs effect on these voltages can be shown and explained easily by (11). Next, we consider the output voltage Vo, which is the result of the combined voltages Vo1 and Vo2 through the Chireix combiner. The complex voltage expression Vo given in [11] has the following form: (12) Equation (12) can also be simplified to an explicit form of Vo versus the input phase . Indeed, using (6), (10), and (12) and combining them judiciously we find the following new simplified expression (see details in Appendix C): (13) Equation (13) shows that the output voltage of the Chireix system is proportional to the term instead of term. Clearly, since corresponds to the linear behavior, a phase-only predistortion, whereby one branch is phase-shifted by an angle relative to the other, would linearize the Chireix combiner. This intuitive result would require complex derivations with other models such as [11]. Furthermore, we can see that this predistortion will make the combining efficiency found , which is equivalent to the in (6) follow the form , i.e., by choosing matched combiner efficiency with using (9). With the above simplified voltage expressions, we can analyze quantitatively the effect of the stubs on the linearity of the Chireix system. First, we note that (13) is of the form describing the output voltage. , Knowing that the input voltage Vin is equal to the nonlinearity observed in the Chireix system is thus quantified and is presented by this term. To avoid this nonlinearity the term must be equal to zero. Consequently, the Chireix system becomes linear when the stubs are withdrawn. III. SIMPLIFIED MODEL VALIDATION To validate the accuracy of the proposed model of Chireix systems, we fabricated three different Chireix combiners and performed experimental measurements on all of them. The combiners where fabricated in microstrip technology using a Duroid

EL-ASMAR et al.: ANALYTICAL DESIGN METHODOLOGY OF OUTPHASING AMPLIFICATION SYSTEMS

Fig. 3. Comparison between the measured efficiency (dotted line) and the sim20 , plified analytical model of (6) (solid lines) for variable stubs’ length ( . 45 , and 70 ) and constant characteristic impedance

substrate ( , 31 mils). Each combiner is made of two quarter-wavelength lines and two stubs, one stub having an electric length of and the second having an electric length of . The experimental setup used for all measurements is made of two signal generators coherently locked using external generators, the combiner(s), and a power meter. The details of the measurement procedure are as follows. First, the generators’ output power is calibrated using the setup’s power meter. The instantaneous combiner efficiency is then measured by varying the relative phase between the two generators over a 90 range. The efficiency is obtained by taking the ratio of the power at the output of the combiner, as measured by the power meter, to the sum of the powers injected by the two generators. Two sets of measurements where taken in this manner to validate (6) and (8). The first set corresponds 20 , 45 , and 70 to the three Chireix combiners with when . The second set corresponds to three Chireix combiners with 45 and 0.6, 1.4. The comparison between the measured results and our simplified model of the combiner’s instantaneous efficiency of (6) are shown in Figs. 3 and 4, where the solid lines correspond to (6) while the symbols represent the measurements. In order to compensate for the circuit losses, the measured efficiency was scaled to a maximum of 100%. Excellent agreement between the proposed instantaneous efficiency model and measurements is seen for all combiner cases considered. The efficiency of 100% is obtained for certain values of stubs. This is possible because we use the generators instead of RF amplifers at input of the combiners. This 100% efficiency is not possible to obtain when we consider the RF amplifiers at the input of the combiner because the global efficiency depends on the RF amplifier’s efficiency. IV. APPLICATION TO THE DESIGN OF AN OPTIMAL OUTPHASING COMBINER Having established the validity of the proposed model both theoretically and experimentally, we next focus on using the added physical insight that the new equations bring to the design of an optimal outphasing combiner, one that maximizes the

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Fig. 4. Comparison between the measured efficiency (symbols) and the simplified analytical model of (6) (solid lines) for variable characteristic impedance 0.6, 1, 1.4) and constant stub length . (

Fig. 5. Optimization of the combiner efficiency using the PDF of 16-QAM modulated signal.

average combining efficiency for a given modulated signal. The design parameters are the length of the stubs and the characteristic impedance . Here, we consider a 16-QAM signal and seek the combiner that will maximize the average combining efficiency. The signal has a symbol rate of 1 MS/s and is filtered with a root-raised cosine filter (RRCF) having a roll-off factor of 0.35, thus yielding a 1.35-MHz modulation bandwidth and a peak-to-average ratio of 6.5 dB. We start by examining the PDF of the signal as shown in Fig. 5. Next, we identify from this figure the LINC decomposition angle corresponding to the most frequently occurring signal level, which, in this case, is about 60 . Clearly, a combiner having a maximum combining , as shown in Fig. 5, would maximize efficiency at the average combining efficiency. Designing such a combiner is straightforward using (6) and (9). First, from (6), we determine while from (9) that the stub electric length must be or we find the normalized characteristic impedance, in a 50- system. This design procedure is not only intuitive and direct, but it is also considerably simpler than the alternative of using the original equations and searching for the optimal combiner though multiple simulations [13].

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TABLE I THEORETICAL AND MEASURED AVERAGE EFFICIENCY FOR DIFFERENT TYPES OF COMBINER WITH 16-QAM SIGNAL

Fig. 6. Class-B PA with variable charge

.

To validate our design, we carried out an experimental study consisting of comparing the average combining efficiency of four different Chireix combiners. The first three combiners were chosen somewhat arbitrarily and are characterized by: 1) , , which is a stubless combiner that produces a , , which good match into a 50- load; 2) , gives a somewhat intuitive median solution; and 3) , which has the good stub length but the characteristic impedance suited for stubless quarter-wavelength combiners in 50 . The fourth combiner is based on the above design, i.e., , . It should be noted that combiners 1, 2, and 4 value of unity [see (9)] while have a maximum for combiner 3 as its characteristic impedance is not optimal. All four Chireix combiners were fabricated using the same substrate and 31 mils). ( Using the same measurement setup described in Fig. 6, where careful attention was paid to the phase coherence of the generators (RF and baseband), the 16-QAM signal was decomposed according to the LINC technique using the ADS simulator. The resulting data files for the two signals were loaded into the signal generators and output at 2.14 GHz. The average input and output powers of the combiner were measured using the power meter of the setup and the average efficiency was determined by taking the ratio of the combiner’s output power to the sum of its input powers. These measured results are summarized in Table I. The is commeasured average efficiency for each combiner, , pared with the theoretically calculated average efficiency, for the same combiner. This latter efficiency is computed using the instantaneous combining efficiency of (6) and the PDF of as follows: the 16-QAM signal

(14) Table I shows the measured and simulated average efficiency values for the four combiners. Good agreement, within the precision of the measurement setup, between measured and simulated values is obtained. This table also confirms that the designed combiner does indeed produce the maximum average efficiency for the 16-QAM signal.

In the above analysis, only ideal sources were considered and the efficiency was limited to that of the combiner without including any efficiency variation resulting from the variation of the dc power consumption of the amplifiers. To illustrate how the proposed model can be applied with realistic amplifiers, we consider two Class-B RF amplifiers in a Chireix system. V. IMPLEMENTATION OF A LINC SYSTEM WITH A CHIREIX COMBINER WITHOUT STUB The efficiency defined above in (6) consists of the instantaneous efficiency of the Chireix combiner decoupled from the two RF amplifiers. The coupling of two PAs via reactive combiners is a non linear problem arising from the complex load modulation caused by the reactive Chireix-combiner interacting with the PAs. To introduce the impact of the RF amplifiers on the total Chireix system efficiency, one must have an accurate power amplifier model that predicts well the behavior of both PAs as their loads vary with the outphasing angle. In the case of two Class-B amplifiers, such a model can be relatively well approximated. For this reason, we consider a Class-B based LINC system with a Chireix combiner. A. Class-B Amplifier Model in a LINC System The classical formulas for efficiency of outphased LINC amplifiers were generally based on the model proposed in [9] where both amplifiers are considered to be ideal voltage sources. As noted in [10], this is not a very practical assumption as ideal voltage sources are not realizable at high frequencies. Therefore, we consider an amplifier model that includes a nonzero and we focus on Class-B amplifiers. internal impedance In Fig. 7, we show one branch of the LINC system, which versus consists of a Class-B amplifier with variable load . Indeed, is the dc current, corresponds to the internal represents the load impedance seen impedance of the PA and varies, as by the amplifier. As the outphasing angle varies, to also vary, thereby per the equation given by [11], causing changing the consumed dc power. By analyzing Fig. 7, we can determine the overall outphased LINC amplifier efficiency.

EL-ASMAR et al.: ANALYTICAL DESIGN METHODOLOGY OF OUTPHASING AMPLIFICATION SYSTEMS

Fig. 7. Photograph of the fabricated LINC PA with stubless Chireix combiner

B. Stubless LINC System Efficiency With Class-B Amplifiers

Fig. 8. Comparison between measurement (red line) and (21) ( symbols).

presented by the setup of Fig. 6 that varies linearly instead of . Equation (15) can be changed by versus

In Class-B amplifiers, the current (see Fig. 7) varies lincurrent in each early with the RF output current . Thus, the branch consumed by the Class-B amplifier is given by [14]

(15)

(18) Each RF Class-B amplifier sees the impedance at its output. can be expressed as a function of the This means the current and the impedance , which transfundamental voltage forms (18) as follows:

The load impedance seen by the Class-B amplifier in a LINC can be system without a stub in optimum condition expressed as (16) When

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(19) depends on dc voltage . By following the The voltage parameters, we can obtain analysis done in [15] using the (20)

, (16) becomes

(17) varies versus and presents an infiThe load impedance impedance given by nite reactance when nears 90 . The (17) corresponds to the impedance seen by one of two amplifiers of the Chireix system at the fundamental frequency component. The other harmonics see an impedance variable with and different from since the branch line used in Chireix system corresponds to the fundamental frequency and change the impedance value for other harmonics. In the above condition, the amplifier is not operated at its optimum condition when takes nonzero values. Consequently, when the reactance of presents an infinite value ( near 90 ) at the fundamental, current beyond the amplifier consumes some residual equaling 80 ; see Fig. 8. This residual dc current is equal to zero in ideal case with optimum load impedance. In our case with variable load impedance for each harmonic, the residual current takes nonzero value and corresponds to nonlinearity in Class-B amplifier dc consumption. We assume in this study that the residual dc current is constant in order to give first approach of dc consumption of Class-B amplifier in such conditions. Consequently, we can show using the experimental measurements

corresponds to knee voltage. In this case, using The voltage (17), (19) is changed to (21) with (22) The overall drain efficiency of the Chireix system can then be expressed as (23) where and refer to the output voltage and impedance, , (17), respectively, as shown in Fig. 1. Using (13) with (21), and (23), the overall drain efficiency becomes (24)

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Fig. 9. Experimental test bunch used to validate our efficiency expression (21) by using a Class-B amplifier.

correspond to a maximum of current when [see (21)]. The measurement curve of the current in Fig. 8 cannot give us the accurate value of which is needed to fit accurately the efficiency measured by using (24). current by However, the fit of the measurement curve of the . Equation (24) applies (21) can give an accurate value of correto the general Chireix combiner without stubs where sponds to

Fig. 10. Drain-efficiency variation versus outphasing angle for the design LINC amplification system with a Chireix combiner compared with the drain efficiency of a LINC system with a Wilkinson combiner and to the theoretical efficiency from (23) and (24).

where

(25) However, nonzero stubs lead to nonlinearities, see Fig. 4. Therefore, it is important to consider the case of a Chireix without stubs. C. Experimental Validation Using the 2-W transistor RT233 from RFHIC Inc., two identical Class-B PAs were designed for WCDMA applications around 2.14 GHz. The transistors were biased at a gate voltage 2.5 V while the drain equal to the threshold 22 V. For an input power of 24 dBm, was biased at the designed PAs have a gain of 11 dB and a drain efficiency and power-added efficiency (PAE) equal to 60% and 57%, respectively. Using these two Class-B PAs, a LINC amplification system using a stubless Chireix combiner was designed and implemented as shown in Fig. 9. This circuit will be used to validate the model equations provided in the previous section. In the validation process, the drain–current variation versus outphasing angle will be validated first, and then the measured efficiency of the entire LINC system will be compared with (24). To validate (21) and (22), which provide the drain–current variation versus the outphasing angle, we consider Fig. 8, which shows the dc current consumed by RF Class B amplifier 2W RT233 in LINC setup showing in Fig. 6. The determination of constant needs to know , , and parameters. In the and experimental setup of Fig. 6, we consider 22 V; however, is determined using the – measurements of a 2-W RT233 amplifier, which gives the value of 3 V. By current versus , using (21), fitting the measurement curve of 178 mA, 60 mA and we obtain 235 mA. Finally, by using the above values extracted from the

real measurement of setup of Fig. 6, we validate our model of the current variation versus outphasing angle given by (21). The comparison of this equation with the above parameters to the measured current values versus outphasing angles shows a good fit and therefore a good agreement between measurement and the model current equation. The efficiency of the implemented LINC amplification system with a Chireix combiner was measured and compared with the theoretical efficiency of the LINC system when using an isolated Wilkinson combiner [16] and to the theoretical efficiency obtained from (24) and (25) after normalizing it by the measured peak efficiency of the LINC system. This is done by 60 mA and 235 mA using the parameters of obtained from the – measurement as shown above, and by using (25), the measured calculating the values of 22.8 V, and output voltage at zero outphasing angle 22 V and 3 V. the device parameters Fig. 10 shows the drain efficiency variation of the LINC system as a function of the outphasing angle for the four cases. The measured efficiency of the LINC system with Chireix combiner is closely predicted by the theoretical equation (24). The parameter is replaced efficiency obtained by (23), where the by the data obtained directly from measurement instead to use (21), is considered and shows identical behavior of the efficonsumption ciency measured. Thus, the accurate model of of a Class-B amplifier is important to predict the behavior of current efficiency. Our approach, considering the residual to be constant, gives very good results in Fig. 10, despite some differences observed in Fig. 8 between (21) and measurement takes an when higher than 80 . Indeed, when the term behavior. infinite value with near 90 , (24) presents The above behavior takes small value beyond equaling 80 , as seen in Fig. 10, and then the difference observed in Fig. 8 has a negligible effect in the same zone. These three efficiencies are considerably different from the efficiency of the LINC system when using a Wilkinson combiner. Indeed, for equal to 60 , which corresponds to 6-dB back-off, the measured efficiency improves from 14% to 27% when passing from the isolated combiner to a Chireix combiner. The use of a nonisolated combiner doubled the efficiency of the LINC system in back-off due to the load modulation. Again, this

EL-ASMAR et al.: ANALYTICAL DESIGN METHODOLOGY OF OUTPHASING AMPLIFICATION SYSTEMS

effect is accurately predicted with the developed theoretical efficiency expression.

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which is in the form and the denominator

. We now evaluate the numerator separately as follows:

VI. CONCLUSION An analytical design methodology of outphasing amplification systems was presented. This methodology relies on a simplified analytical model of the Chireix combiner efficiency and voltage expressions, which provide a more intuitive insight into the combiner’s behavior directly as a function of the input signal’s amplitude. This model was first validated by simulation and through measurements using signal generators, thereby avoiding the mutual loading effects that exist with real amplifiers. Later, a Class-B amplifier-based outphasing system was studied theoretically, by simulations and experimentally. It was shown that, when the proposed simplified combiner model is coupled with amplifier models that can accurately capture dc current variation as a function of the change in load impedance resulting from signal outphasing, the overall efficiency of the outphasing amplification system can be predicted accurately. The proposed models can be used to design for specific placement of the maximum in the instantaneous efficiency curve, which can in turn be used with signal statistics to maximize the overall efficiency. However, one must still take into account linearity concerns since, as per the voltage expressions of the proposed model, electrically longer stubs are more nonlinear.

Arranging obtain

in the form

, we

which can be simplified to

Similarly, we have

APPENDIX A SIMPLIFICATION OF THE EFFICIENCY EXPRESSION which yields, after simplification,

Starting with (5), we have

(A1) Letting written as

and simplifying by

which can be put in the form

, (A1) can be We observe that the following form:

Next, we evaluate following expression:

. The last term is

. Hence, the efficiency expression takes

(A2) in terms of . Using (4) and using the which can be simplified as follows: (A4) (A3)

Combining (A2) and (A3), we obtain

AND

APPENDIX B EXPRESSIONS AT THE COMBINER’S INPUTS

Taking into account of the reflection coefficient occurred by the unmatched Chireix combiner, the voltage at the input of the combiner could be expressed as follows [11]: (B1) (B2)

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(C3)

On the other hand, we know that

Combining (A4) and (B4), we find the final simplified expression of the output voltage, namely

(C5)

Then, we can say that

(B3) Evaluating

The authors would like to thank W. Hamdane for his help with the measurement setup and Cree Inc. and RFHIC Inc. for their collaboration with devices and device models.

by (B2), (C3) can be written as follows: (B4)

Using (A3) to replace

, (B4) will be

Finally

(B5) APPENDIX C SIMPLIFICATION OF THE OUTPUT VOLTAGE EXPRESSION The complex expression of

is given as [11] (C1)

where that

ACKNOWLEDGMENT

. Also from [11], we know

(C2) , we have (C3), shown at the top of Then. letting this page. According to (A2), we know that the efficiency can be written of the form

We notice, by examining this expression and the result obtained in (C3), that we can express as a function of as follows: (C4)

REFERENCES [1] D. C. Cox, “Linear amplification with nonlinear components,” IEEE Trans. Commun, vol. COM-22, no. 12, pp. 1942–1945, Dec. 1974. [2] H. Chireix, “High power outphasing modulation,” Pro. IRE, vol. 23, pp. 1370–1392, Nov. 1935. [3] X. Zhang, L. E. Larson, and P. M. Asbeck, Design of Linear RF Outphasing Power Amplifiers. Boston, MA: Artech House, 2003. [4] Y. Yaehyok, Y. Yang, and B. Kim, “Effect of efficiency optimization on linearity of LINC amplifiers with CDMA signal,” in IEEE MTT-S Int. Microw. Symp. Dig., May 2001, vol. 2, pp. 1359–1362. [5] G. Poitau and A. Kouki, “MILC: Modified Implementation of the LINC Concept,” in Proc. IEEE Int. Microw. Symp., Jun. 2006, pp. 1883–1886. [6] M. Helaoui, S. Boumaiza, F. M. Ghannouchi, A. B. Kouki, and A. Ghazel, “A new mode-multiplexing LINC architecture to boost the efficiency of WiMAX up-link transmitters,” IEEE Trans. Microw. Theory Tech., vol. 55, no. 2, pt. 1, pp. 248–253, Feb. 2007. [7] W. Gerhard and R. Knoechel, “Differentially coupled outphasing WCDMA transmitter with inverse class F power amplifiers,” in IEEE MTT-S Microw. Int. Symp. Dig., San Diego, CA, Jan. 2006, pp. 355–358. [8] I. Hakala, L. Gharavi, and R. Kaunisto, “Chireix power combining with saturated class-B power amplifiers,” in Proc. 34th Eur. Microw. Conf., Oct. 11–15, 2004, vol. 1, pp. 1–4. [9] F. H. Raab, “Efficiency of outphasing RF power-amplifier systems,” IEEE Trans. Commum., vol. COM-33, pp. 1094–1099, Oct. 1985. [10] I. Hakala, D. K. Choi, L. Gharavi, N. Kajakine, J. Koskela, and R. Kaunisto, “A 2.14-GHz chireix outphasing transmitter,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 6, pp. 2129–2138, Jun. 2005. [11] A. Birafane and A. Kouki, “On the linearity and efficiency of outphasing microwave amplifier,” IEEE Trans. Microw. Theory Tech., vol. 52, no. 7, pp. 1702–1708, Jul. 2004. [12] M. El-Asmar, A. Birafane, and A. B Kouki, “A simplified model for chireix outphasing combiner efficiency,” in Proc. 36th Eur. Microw. Conf., Manchester, U.K., Sep. 2006, pp. 192–195. [13] Advanced Design System. Agilent Technologies, Palo Alto, CA, 2005. [14] H. L. Krauss, C. W. Bostian, and F. H. Raab, Solid State Radio Engineering. New York: Wiley, 1980. [15] V. Kaper, V. Tilak, B. Green, T. Prunty, J. Smart, L. F. Eastman, and J. R. Shealy, “Dependence of power and efficiency of AlGaN/GaN HEMTs on the load resistance for class B bias,” in Proc. IEEE Lester Eastman Conf. High Performance Devices Conf., 2002, pp. 118–125. [16] A. Birafane, M. El-Asmar, A. B. Kouki, M. Helaoui, and F. M. Ghannouchi, “Analyzing LINC systems,” IEEE Microw. Mag., vol. 11, no. 5, pp. 59–71, Aug. 2010.

Mohamed El-Asmar (M’09), photograph and biography not available at the time of publication.

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Ahmed Birafane received the B.Sc. degree in electronic engineering from ENSIETA, Brest, France, in 1990, the M.Sc. degree in electronic engineering from University of Lille, Lille, France, in 1991, and the Ph.D. degree in microwave and RF domain from University of Paris XI, Paris, France, in 1997. His doctoral work consisted of nonlinear modelling of heterojunction bipolar transistors (HBTs) for a design of microwave circuits with corresponding characteristics procedure. In 1999, he joined the RF team, LACIME Laboratory, Communications and Microelectronics Laboratory (LACIME), Department of Electrical Engineering, École de Technologie Supérieure (ETS), Montréal, QC Canada, as a Post Doctoral Researcher in HBT modeling. In 2000, he was a Consultant for the project of Design and Development of Ku Band Solid State Power Transmitter (SSPB) for VSATs for Satcomm Networking Technology Inc. He was an RF Engineer and Researcher with the R&D team at Wavesat Telecom, Inc., Montreal. In 2001, he was involved with the study of linearity and efficiency of LINC and Chireix-outphasing project in a postdoctoral position with ETS, where, since 2008, he has been with the GaN HEMT modeling project.

Mohamed Helaoui (S’06–M’09) received the M.Sc. degree in communications and information technology from École Supérieure des Communications de Tunis, Tunis, Tunisia, in 2003, and the Ph.D. degree in electrical engineering from the University of Calgary, Calgary, AB, Canada, in 2008. He is currently an Assistant Professor with the Department of Electrical and Computer Engineering, University of Calgary, Calgary, AB, Canada. His current research interests include digital signal processing, power efficiency enhancement for wireless transmitters, switching-mode power amplifiers, and advanced transceiver design for software defined radio and millimeter-wave applications. His research activities have led to over 60 publications and seven pending patents. Dr. Helaoui is a member of the COMMTTAP chapter of the IEEE Southern Alberta section.

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Ammar B. Kouki (S’88–M’92–SM’01) received the B.S. (with honors) and M.S. degrees in engineering science from the Pennsylvania State University, University Park, in 1985 and 1987, respectively, and the Ph.D. degree in electrical engineering from the University of Illinois at Urbana-Champaign, Urbana, in 1991. Between 1988 and 1991, he was a Consultant with the National Center for Supercomputing Applications (NCSA). From 1991 to 1993, he was a Postdoctoral Fellow with the Microwave Research Laboratory, École Polytechnique de Montréal, Montréal, QC, Canada. From 1994 to 1998, he was a Senior Microwave Engineer with the same laboratory, where he was involved with power amplifier linearization techniques. In 1998, he cofounded AmpliX Inc., a company that specialized in RF linearizers for wireless and SatCom applications. In 1998, he joined the faculty of the École de Technologie Supérieure, Montréal, QC, Canada, where he is currently a Full Professor of Electrical Engineering, Director of the LACIME Lab, founding director of the LTCC@ETS laboratory, and one of the cofounders of ISR Technologies, a software-defined radio company. He has authored or coauthored over 190 peer-reviewed publications and holds six patents, with an additional three under review. He has diversified research interests that cover the areas of radio communication and navigation with focus on devices, intelligent, and efficient RF front-ends/transceiver architectures, circuit and package integration in LTCC, and antenna and propagation. He works on active device modeling and characterization, power-amplifier design, linearization, and efficiency enhancement techniques. He is also engaged in research on computational electromagnetic techniques for the modeling and design of passive microwave structures.

Fadhel M. Ghannouchi (S’84–M’88–SM’93–F’07) is currently an iCORE Professor and Senior Canada Research Chair with the Electrical and Computer Engineering Department, The Schulich School of Engineering, University of Calgary, Calgary, AB, Canada, and Director of Intelligent RF Radio Laboratory. He held several invited positions with several academic and research institutions in Europe, North America, and Japan. He has provided consulting services to a number of microwave and wireless communications companies. His research interests are in the areas of microwave instrumentation and measurements, nonlinear modeling of microwave devices and communications systems, design of power and spectrum efficient microwave amplification systems and design of intelligent RF transceivers for wireless and satellite communications. His research activities have led to over 450 publications and 12 patents (five pending). Prof. Ghannouchi is a Fellow of the IET and a Distinguished Microwave Lecturer for the IEEE Microwave Theory and Techniques Society (MTT-S).

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A Zero-Voltage-Switching Contour-Based Outphasing Power Amplifier Nitesh Singhal, Member, IEEE, Haoxing Zhang, Student Member, IEEE, and Sudhakar Pamarti, Member, IEEE

Abstract—A parallel class-E modified Chireix outphasing power amplifier (PA) that can maintain high efficiency across a wide output power range is presented. The architecture presented essentially implements a zero voltage switching (ZVS) contour-based PA using a modified Chireix outphasing structure. It utilizes the inherent load modulation present in the outphasing scheme and combines it with duty cycle modulation to satisfy ZVS conditions over a wide range of output powers. Thus, a ZVS contour-based PA is realized, and the amplifier maintains high efficiency for about 9-dB back-off of output power. Beyond the 9-dB range, simple outphasing is performed to extend the dynamic range up to about 30 dB. The proposed PA, implemented using discrete components on an FR4 printed circuit board, achieves a dynamic range of 30 dB with a peak power of 29 dBm and a peak drain efficiency of 65% at about 6-dB back-off from the peak output power at 100 MHz from a 3-V supply. Index Terms—Peak-to-average power ratio (PAR), power amplifier (PA), zero voltage switching (ZVS).

I. INTRODUCTION

M

ODERN wireless communication systems use complex modulation schemes to accommodate higher data rates. As a result, the RF power amplifier (PA) has to amplify modulated signals with large peak-to-average power ratio (PAR). Linear PAs (classes A, B, AB, C) can amplify signals with large envelope variations, but are inefficient. Switching PAs (classes D, D , E, F, F , etc.) are efficient, but can only amplify constant envelope signals. Various techniques viz., polar [3], [4], polar loop [5], envelope tracking [6], direct digital RF modulation [7], [8], duty cycle modulation [9], dynamic load modulation [10], Doherty [11] and its multistage variants [12], outphasing or linear amplification with nonlinear components (LINC) [13]–[23], LINC with dynamic load modulation [24], and ZVS contour PA [1], [2], [25] have been proposed to simultaneously achieve high efficiency and linearity with varying degrees of success. The LINC architecture and its variants, Chireix [14]–[19] and LINC with dynamic load modulation [24], generically referred to as outphasing PAs, are particularly promising. Manuscript received September 30, 2011; revised February 27, 2012; accepted March 05, 2012. Date of publication April 11, 2012; date of current version May 25, 2012. This work was supported by the National Science Foundation (NSF) under Award ECCS 1102123. N. Singhal and S. Pamarti are with the Department of Electrical Engineering, University of California at Los Angeles (UCLA), Los Angeles, CA 90095-1594 USA (e-mail: [email protected]). H. Zhang is with the Department of Electrical Engineering, Zhejiang University, Hangzhou 310058, China. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2012.2190747

They combine two constant envelop high-power signals with a relative phase offset, called the outphasing angle, that can be dynamically changed to achieve desired envelope variation with good linearity. The anticipation is that high efficiency can be simultaneously achieved if efficient switching PAs are used to amplify the constant envelope signals. Unfortunately, practical low-loss combiners are nonisolating, thereby presenting the PAs with a load mismatch that changes with the outphasing angle and degrades their efficiency, particularly under back-off. For example, if class-E switching PAs were employed, the load mismatch violates zero voltage switching (ZVS) conditions (required for high-efficiency operation) at all but the peak output power, resulting in significant efficiency degradation under back-off. The Chireix [14]–[19] and LINC with dynamic modulation [24] architectures reduce the load mismatch using fixed or dynamically variable reactive terminations. However, most implementations are still forced to use linear class PAs that are less sensitive (compared to switching PAs) to the residual load mismatch. In the ZVS contour PA [1], [2], [25], a combination of duty cycle modulation and dynamic load modulation are employed in concert such that ZVS conditions are satisfied in a class-E PA for, theoretically, all output power levels. However, the dynamically tunable load network used in this technique imposes a tradeoff between achievable efficiency and power back-off range. Measurements (of a discrete 100-MHz 24-dBm series class-E prototype) showed that up to 13-dB envelope back-off could be achieved with no drain efficiency degradation. This paper presents a new technique that realizes a ZVS contour PA by exploiting the inherent load modulation present in a class-E-based outphasing structure. Essentially, for every outphasing angle, it selects appropriate PA driving waveform duty cycle and PA reactive termination values such that ZVS conditions are satisfied, theoretically, for all outphasing angles (i.e., power levels). Measurement results (from a 100-MHz 29-dBm discrete prototype) are described that show that ZVS conditions are satisfied and high efficiency is maintained for a 9-dB back-off; a drain efficiency of 65% is achieved at 6-dB back-off. The back-off range was limited only by the lowest achievable duty cycle on the discrete prototype. Beyond the 9-dB range, further back-off up to 30 dB was demonstrated by performing simple outphasing. The proposed technique improves over both the outphasing and the ZVS contour PAs in multiple ways. Foremost, it reduces efficiency degradation at back-off in outphasing scheme while using class-E PAs. Secondly, as described later in this paper, it avoids the efficiency and dynamic range limitations of the ZVS contour PA by using a much simpler tunable load network.

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Fig. 1. (a) Conventional outphasing. (b) Simulated output power and drain efficiency while using ideal class-E PAs in conventional outphasing. (c) Chireix-based outphasing. (d) Simulated output power and drain efficiency while using ideal class-E PAs in Chireix-based outphasing.

The scheme can also be utilized to generate wide-bandwidth modulated RF signals by dynamically changing the duty cycle of the PA driving waveform and the reactive terminations in the PA to achieve high average efficiency. Transistor level Spectre RF simulations in 130-nm RF CMOS technology with realistic modeling of all passives in ASITIC at 2.4 GHz using a 9-dB PAR 16 quadrature amplitude modulation (QAM) signal were performed. Simulations suggest that an average drain efficiency of 35% and an average power-added efficiency (PAE) of 25% can be achieved for RF bandwidths up to 40 MHz at an average output power of 15 dBm. The simulated adjacent channel power ratio (ACPR) at an offset of 30 MHz from the center frequency was found to be 35 dBc/Hz, while the EVM achieved was less than 4%. This paper is divided into five sections. Section II presents a brief overview of the outphasing and ZVS contour PA techniques. Section III describes the proposed ZVS contour-based outphasing PA. Section IV discusses the various loss mechanisms in the proposed PA. Section V presents detailed measurement results for the aforementioned discrete prototype. Section V also presents results from transistor-level simulations performed to evaluate the linearity and efficiency of the scheme while generating modulated RF signals at 2.4 GHz.

transmission-line-based combiner) to reintroduce the envelope variations in the final output. The instantaneous value of depends upon the instantaneous envelope value. For example, when the instantaneous envelope value is at its maximum, the two PAs operate in push–pull fashion and the phase offset is 180 . As the envelope value decreases, the phase offset is also decreased to reduce the output power. When the phase offset is decreased to 0 , the output voltages of the two PAs are in phase, resulting in, theoretically, zero output power. However, due to the nonisolating properties of the combiner, both PAs see varying reactive, as well as resistive admittances [see Fig. 1(a)]. The admittances seen by the first (leading in voltage) and second PA (lagging in voltage) are given as [14], [15]

II. OVERVIEW OF OUTPHASING AND ZVS CONTOUR PA

If class-E PAs are used in the outphasing scheme, the varying reactive, as well as resistive admittances seen by the two PAs violate ZVS conditions and degrade the efficiency of under backoff. This is shown in Fig. 1(b), which plots the variation of simulated output power and drain efficiency with the phase offset for class-E PAs designed using lossless elements in an outphasing structure. As the phase offset is decreased from 180 , lower output powers are realized, but the drain efficiency degrades due to increased ZVS loss caused by the undesired load modulation present in the scheme.

A. Outphasing PA In an outphasing PA, an amplitude- and phase-modulated signal is split into two constant envelope phase-modulated signals with a phase offset of [see Fig. 1(a)]. For simplicity, the relevant phase modulation has not been shown in Fig. 1(a). The two phase modulated but phase offset signals drive two efficient switching-mode PAs whose outputs are combined using an RF combiner (lumped transformer or

(1) where (2) and (3)

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Fig. 2. (a) Previously proposed ZVS contour-based PA. (b) Variation of with duty cycle .

This can be alleviated to some extent by placing Chireix compensation elements at the inputs of the power combiner [see Fig. 1(c)]. These compensation elements tune out the varying reactive susceptances at a particular phase offset and help achieve a better back-off efficiency curve. Although Chireix combining leads to efficiency peaking at a particular backed-off output power, the PAs continue to see varying reactive and resistive loads at other power back-off values. Chireix-based combining has been used for saturated class-B, class-D, and class-F PAs [14]–[18] whose output voltage characteristics are relatively insensitive to such load variations; however, their efficiency is invariably lower than a class-E PA. However if a class-E PA is used in the Chireix-based outphasing structure, it results in poor dynamic range of output power [23]. This is shown in Fig. 1(d), which plots the variation of simulated output power and drain efficiency with the phase offset for class-E amplifiers designed using lossless elements in a Chireix-based outphasing structure. As can be seen from Fig. 1(d), although good efficiency can be maintained over wide phase offset values, the achievable dynamic range is limited to around 6 dB, which is unsuitable for high PAR envelope signals. Note that even if dynamically varying Chireix susceptances are used at the input of the power combiner to tune out the unwanted susceptances ( ) at each phase offset (as has been done in [24] for saturated class-B PAs), the class-E amplifiers continue to see varying resistive impedances, which results into violation of ZVS conditions and degraded back-off efficiency. Thus, though the outphasing structure offers a simple and elegant way of using high-efficiency switching PAs to generate envelope modulated signals, the varying impedances seen by the PAs leads to poor back-off efficiency and/or limited dynamic range while using class-E amplifiers. However, note that there are other topologies of class-E PAs like the variable slope class-E PA, which lend themselves more readily to an outphasing architecture [19]. The variable slope class-E PA offers high efficiency by changing the slope of the drain voltage at the turn-ON instance while still maintaining ZVS conditions for the varying loads presented to the PAs by the outphasing action. The architecture presented in [19] achieves high efficiency over a wide dynamic range. However, since the variable slope class-E PA does not maintain zero slope condition at the turn-ON instance, they can be sensitive to mismatches in component values due to process, voltage, and temperature (PVT) variations.

with duty cycle

. (c) Variation of

B. ZVS Contour PA Conventionally, a class-E PA is designed to meet ZVS conditions at 50% duty cycle and a particular output power level from a fixed supply voltage [26]. ZVS conditions ensure that just when the transistor turns ON [see Fig. 2(a)] during each carrier period, the drain voltage is at 0, thereby avoiding any wasted power in discharging the drain. The ZVS contour PA is based on the fact that it is possible to meet ZVS conditions and thus ideally 100% efficiency in a parallel class-E PA, not only at a particular power level, but also at backed-off power levels by a simultaneous modulation of the duty cycle , drain capacitance , and the load seen by the PA, [see Fig. 2(a)]. Note that though a ZVS contour PA realized in [25] was based on a series class-E PA, the parallel version of the scheme has been subsequently proposed and realized in [1] and [2]. Specifically ZVS conditions can be satisfied in a parallel class-E PA at all power levels by choosing the load seen by the PA, and the drain capacitance as a function of the duty cycle [see Fig. 2(a)] such that [1], [2] (4) (5) where is the drain inductance, as shown in Fig. 2(a), is the angular switching in radians/second, and and are functions of , plotted in Fig. 2(b) and (c), respectively. The functions and have been derived theoretically using numerical fitting techniques. Note that prior analysis done by Zulinski and Steadman in [27] also conceptually suggest at the existence of such functions for class-E PAs with finite dc inductance. The details of the theoretical derivation of functions and are a subject of another paper and have been omitted here for the sake of brevity. The fitted functions for and are

(6) (7) As can be seen from Fig. 2(b) and (c), as is decreased, decreases, while increases. For a fixed drain inductance , both the drain capacitance and the load seen by the PA, , need to be increased to follow these functions. Theoretically the scheme can provide infinite power back-off, but

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its dynamic range is limited by the lowest duty cycle that can be reliably generated. At RF frequencies, this is close to about 20% even in scaled processes. The achievable dynamic range for a 20%–50% duty cycle modulation while using a parallel class-E PA to realize the ZVS contour PA is about 9–10 dB [1], [2]. It is essential to increase the dynamic range of a ZVS contour PA since most wireless systems require a much wider range of output powernotonlyfor generating high PAR signals,butalso for power control applications. This can be achieved by simple load modulation at the cost of efficiency beyond the 9–10-dB dynamic range achieved by the ZVS contour PA. However, in [1] and [2], the required load modulation in is achieved by using a tunable LC–LC transformation network [see Fig. 2(a)]. This has the following three important limitations. 1) For the LC–LC tunable network used in [1] and [2], the transformed load is always less than . This leaves little room to extend the dynamic range of output power through simple load modulation once the entire ZVS contour range (mostly limited by the lowest duty cycle that can be produced) has been exercised. 2) The peak efficiency of such a tunable network degrades as the dynamic range is increased. This degrades the peak efficiency of the ZVS contour PA as compared to conventional schemes like load or duty cycle modulation. 3) Since the network uses two inductors instead of the one used in a simple low-pass LC transformation network, its integrated circuit (IC) implementation is costly. Thus, in spite of the high back-off efficiency offered by the ZVS contour PA, its limited dynamic range makes it suitable to use only while generating relatively low PAR and finite PMR envelope signals. III. ZVS CONTOUR-BASED OUTPHASING PA

equal and purely resistive loads ( ) as required by the ZVS contour PA. Next, to satisfy ZVS conditions, for each value of the outphasing angle , the duty cycle , as well as the drain capacitor for both the PAs in the outphasing structure can be chosen according to (8) and (9) with being . This is shown in Fig. 3(a) where two parallel class-E PAs with tunable drain capacitances are driven by duty cycle modulated drives offset by a phase of . Note that though the driving waveforms are offset by a phase of , they have the same duty cycle, . The outputs of the two PAs are combined using a lumped transformer-based power combiner. Tunable susceptances are added at the inputs of the power combiner to tune out the varying susceptance produced due to outphasing. The susceptances produced due to outphasing are plotted as a function of the phase offset in Fig. 3(b). As the phase offset, , increases from 0 to 180 , the leading PA sees capacitive susceptance while the lagging PA sees inductive susceptance. Thus, a tunable inductive susceptance, , is added at the leading end, while a tunable capacitive susceptance, , is added at the lagging end. A discussion on the realization and range of the tunable Chireix susceptances is described in Section III-B. Thus, for a given phase offset, , between the drives of the two PAs, the following procedure can be outlined to allow the PAs to satisfy ZVS conditions at all phase offsets. 1) Tune the inductive susceptance at the leading end of the power combiner so as to provide an inductance given as (10) 2) Tune the capacitive susceptance at the lagging end of the power combiner so as to provide a capacitance given as (11)

A. Concept and Architecture Consider the requirements for satisfying ZVS conditions in the ZVS contour PA. Clearly (4) and (5) suggest that for a fixed drain inductor and a varying load resistance seen by the PA, ZVS conditions can be satisfied if we chose the duty cycle and the drain capacitance as (8)

3) Determine the resistance seen by each PA as (12) with the phase offset is plotted in The variation of Fig. 3(b). 4) Drive the two PAs with RF drives offset by a phase of and having the same duty cycle given as (13)

(9) where is the inverse of the function plotted in Fig. 2(b). As mentioned before, the PAs used in the outphasing structure see varying reactive as well as resistive admittances ( ) [given by (2) and (3)], which depend on the phase offset . Thus, if for each value of outphasing angle the varying susceptance seen at the inputs of the combiner are tuned out using tunable susceptances , then the two PAs can see

is the inverse of the function plotted in where Fig. 2(b). The variation of duty cycle with the phase offset is plotted in Fig. 3(c). 5) Tune the drain capacitance so as to provide a capacitance given as

(14)

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As a result of this simultaneous modulation of the duty cycle, drain capacitance, and tunable Chireix susceptances with the phase offset , ZVS conditions are satisfied while the output power varies as [1], [2]

(15) is a numerically derived function obtained through where curve fitting, the details of which are omitted here for the sake of brevity. The function found through curve fitting is (16) The function is plotted versus the duty cycle in Fig. 3(d). Note that the expression for the output power differs from the conventional outphasing schemes in the sense that it contains a term. The function signifies the extra back-off achieved due to the simultaneous duty cycle modulation performed in the ZVS contour PA. This is around 3 dB for a duty cycle variation of 20%–50%. The variation of output power, with the phase offset , is plotted in Fig. 3(e) for a V and a . Note from Fig. 3(e) that for a variation of around 9 dB in the output power, the phase offset needs to be decreased from 180 to 60 . As can be seen from Fig. 3(c), for the same change in the phase offset, the duty cycle needs to be decreased from 50% to 20%. As mentioned before, it is practically very difficult to generate RF drives with less than 20% duty cycle, even in scaled processes. This limits the total available range of output powers that can be generated using a ZVS contour-based outphasing PA to about 9 dB. However, beyond the 9-dB dynamic range, simple outphasing can be performed, i.e., the phase offset can be further decreased (thus increasing the load seen by the PAs even further) without changing the duty cycle or the drain capacitance so as to realize lower output powers. Of course, the extension of dynamic range through simple outphasing is inefficient as ZVS conditions are no longer satisfied. However, this has little effect on the overall average efficiency while generating signals having 6–9-dB PAR. This is because these signals on an average tend to be around 6–9-dB back-off from peak output power. The dc power consumed in generating powers lower than 9-dB back-off is also minimal and does not affect the overall efficiency significantly. As mentioned before, here a parallel class-E-based ZVS contour PA has been realized by utilizing the inherent load modulation in the outphasing scheme. Similarly it is also possible to realize a series class-E-based ZVS contour PA [25] by utilizing the intrinsic load modulation present in the outphasing action. The advantages of using a parallel class-E PA to realize a ZVS contour PA over the series class-E version are manifold. The parallel class-E version employs a finite drain inductance as opposed to an RF choke used in the series class-E version. Thus, a ZVS contour PA based on a parallel class-E PA is easier to implement in an IC-like environment.

Similarly, since for a given output power and 50% duty cycle the resistive load seen by the parallel class-E PA is almost twice that required by the series class-E PA [29], [30], the associated losses in the impedance transformation network, switching transistor, and the drain inductors are also lower [29], [30]. These lower loss characteristics of the parallel class-E PA remain true at lower duty cycles also, and hence, a parallel class-E-based ZVS contour PA is seen to be about 10%–20% more efficient than its series version at all output power levels. B. Range of Tunable Chireix Susceptances The susceptances [where is given by (3)] produced due to outphasing are plotted as a function of the phase offset in Fig. 3(b). Since the leading PA sees capacitive susceptances, a tunable inductive susceptance needs to be added at the leading end of the power combiner. is implemented by using a parallel combination of a fixed inductor and a tunable capacitor. Since the largest capacitive susceptance seen by the leading PA is (at ), a fixed inductor of value needs to be added at the leading end. For any other phase offset, the tunable capacitor that provides a minimum capacitance of 0 at and a maximum capacitance of at and 180 can be used to provide a lower inductive susceptance. However, almost all tunable capacitances, such as varactor diodes and capacitor banks, have a certain minimum capacitance . This implies that the tunable capacitor at the leading end should provide a capacitance ranging from (at ) to (at and ). Furthermore, an inductor of value needs to be added in parallel to , thus decreasing the total fixed inductance at the leading end to (17) On the other hand, the lagging PA sees inductive susceptances, which needs to be tuned out using a tunable capacitor . The maximum capacitive susceptance needed at the lagging end is at the phase offset of . Thus, a tunable capacitor offering a maximum capacitance of at the phase offset of and a minimum capacitance of 0 at and 180 should be used at the lagging end. However, due to symmetry purposes, the fixed inductor used at the leading end should also be placed at the lagging end. Thus, the tunable capacitance at the lagging end should provide a capacitance ranging from (at and 180 ) to (at ). This variation of the two tunable capacitances is also summarized in Table I. IV. LOSSES IN THE ZVS CONTOUR-BASED OUTPHASING PA and the The finite quality factor of the drain inductor inductor used in the tunable Chireix susceptances, as well as the finite nonzero switch resistance [see Fig. 4(a)] degrade the efficiency of the proposed PA in spite of the ZVS conditions being satisfied. However, the loss characteristic is such that the percentage loss at backed-off output powers is always less than the loss at the peak output power. Thus, the efficiency at backed-off power levels in the dynamic range in which ZVS

SINGHAL et al.: ZVS CONTOUR-BASED OUTPHASING PA

Fig. 3. (a) Proposed ZVS contour-based outphasing PA. (b) Variation of and with duty cycle . (e) Variation of output power (d) Variation of function

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with phase offset with phase offset

. (c) Variation of duty cycle ( ) with phase offset with V and .

.

TABLE I RANGE OF TUNABLE CAPACITANCES

contour-based outphasing is performed is actually greater than the efficiency achieved at peak power. A. Losses in the Switch and Drain Inductor As mentioned earlier, as the phase offset is decreased, the load seen by the two PAs, , increases [see (12)] while the duty cycle, is simultaneously reduced [see Fig. 3(c)]. The increase in the load, , accompanied by a simultaneous decrease in the duty cycle, , in the ZVS contour-based outphasing PA, has the following two important consequences. • As increases, the effective resistance seen by the PA supply also increases. However, the finite on-resistance of the switch, , remains the same. Also, as the duty cycle is simultaneously reduced, the switch is turned ON for a proportionately lesser amount of time. Thus, the percentage loss in the switch decreases significantly. This is verified by simulations and the simulated switch loss normalized to the output power (for and ), plotted in Fig. 5, is seen to decrease as is reduced.

Fig. 4. (a) Proposed ZVS contour-based outphasing PA with various loss elements. (b) Example implementation of the tunable capacitances in the proposed PA.

• As is reduced, the amount of harmonic currents from the supply also increase, increasing the harmonic loss in the parasitic resistance associated with the drain inductor . The simulated drain inductor loss is also plotted in Fig. 5,

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bank situated at the leading end of the power combiner, (at and ), and (at ), thus for this bank is given as (20) Similarly for the capacitor bank situated at the lagging end of the power combiner, (at ) and (at and ) . Substituting the values of and in (19), for this bank is given as Fig. 5. Variation of losses in the switch and the drain inductor normalized to the , , and . output power with the duty cycle ( ) for

where a quality factor of 25 is assumed in the drain inductor. As can be seen from this figure, the percentage loss in the drain inductor increases as is reduced. Fig. 5 also plots the total loss as is decreased from 50% to 20%. As is decreased, the percentage loss in the switch decreases, while that in the drain inductor increases. Initially the decrease in the switch loss outweighs the increase in the inductor loss, thus the total loss decreases until about where the total loss is at its minimum. Beyond , the increase in the inductor loss begins to dominate any gains from the reducing switch loss, and thus the total loss starts to increase again as is further reduced to . Thus, the drain efficiency peaks up until about 6 dB of back-off ( ) and starts degrading again. This is also verified in the measurement results described in Section V. The overall drain efficiency of the proposed PA though also depends upon the losses in the implementation of the proposed tunable Chireix susceptances, analyzed in detail in Section IV-B. B. Losses in the Tunable Chireix Susceptances The finite quality factor of the fixed inductor , as well as that of the tunable capacitances used in implementing the tunable susceptances, degrades the efficiency of the proposed PA. The exact losses in the tunable capacitances depend on the choice of the implementation. Here, we discuss the losses while using a bank of unit capacitance, in series with a switch [see Fig. 4(b)]. The capacitance in the bank can be decreased or increased by turning ON or OFF one or more branches [see Fig. 4(b)]. The minimum capacitance, , provided by such a bank is limited by the parasitic capacitance of the switch . Note that when a particular branch is OFF, it still contributes a capacitance . . Thus, the minimum capacitance offered by such a capacitance bank is (all branches turned OFF). Similarly, the maximum capacitance provided by the bank when all branches are turned ON is . Thus, to exercise a range of capacitances , and should be chosen as (18) (19) As mentioned in Section III, for both the capacitor . For the capacitor banks,

(21) Thus, , and in turn, the size of the switches in both the banks, depends upon the value chosen for . A larger implies that a wider switch can be used, which, in turn, reduces the loss in the switch when a particular branch is turned ON. However, the loss in the inductor limits the value of , which can be used. This is because a larger requires a smaller [see (17)], which decreases the parasitic resistance associated with , where is the quality factor of the inductor . Since is in parallel to the resistance , seen by the PA, a smaller implies a larger loss. In fact, the loss in the inductor normalized to the output power is given as (22) (23) increases as Thus, the percentage loss in the inductor is increased. Note that as the phase offset is decreased, the loss in the inductor also increases. This is because at smaller phase offsets the resistance seen by the PA, , also increases and becomes comparable to , and thus the loss in increases. The capacitance banks shown in Fig. 4(b) were simulated by implementing each capacitance as an array of 64-unitsized elements using switches from 0.13- m CMOS technology for and Mrad/s and . The value of chosen was 24 pF. For this value of , the values of , , and were found to be approximately 30 nH, 0.5 pF, and 3.2 pF respectively. For this inductor value and quality factor, the normalized loss increased from 1% to 4% as the phase offset was decreased from 180 to 60 (ZVS contour-based outphasing range). However, beyond the ZVS contour range when simple outphasing is performed, becomes comparable to and the efficiency degrades rapidly. Note that is invariably inversely proportional to , thus for the same , is independent of the frequency of operation. The loss in the switches in the capacitance banks was found to be less than 0.4% for lying between 180 –60 . However, note that the switch sizes and [see (20) and (21)] are inversely proportional to the frequency of operation (since is inversely proportional to ); hence, the loss in the switches increases as the frequency of operation increases. Thus, the loss at a higher frequency, say,

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2.4 GHz, would be around 10% for the same technology used to implement the switches. V. EXPERIMENTAL RESULTS A. Static Measurement Results A 100-MHz 29-dBm peak-power ZVS contour-based outphasing PA was built using discrete components on an FR4 printed circuit board (PCB) to demonstrate the technique [see Fig. 6(a)]. The PA operates from a 3-V supply. It consists of two common-source -channel enhancement-mode lateral field-effect RF power transistors (PD84001, manufactured by ST Microelectronics), which were used as switches for the two PAs. The two PAs were connected in an outphasing structure through the primary winding of a lumped surface mount 1:1 transformer (ADT1-1WT-1, manufactured by Mini Circuits). The transistor has an ON resistance of 1.5–2 when driven with a 6–7-V input. A 10-nH planar inductor was used as the drain inductor while two 30-nH fixed planar inductors were soldered on the two inputs of the primary winding of the transformer. A low-pass LC transformation network was used to transform 50 to on the secondary side of the transformer. To exercise the ZVS contour range: 1) the phase offset between the two PAs was changed from 180 to 60 ; 2) the duty cycle of the 100-MHz driving waveforms for both the PA was simultaneously changed from 50% to 20% using an HP8122A pulse generator; 3) the drain capacitance was varied from 100 to 200 pF; 4) the capacitor on the leading end was decreased from 85 to 24 pF; and 5) the capacitor on the lagging end was simultaneously increased from 85 to 146 pF. As a result of this simultaneous variation of phase offset, duty cycle, and tunable capacitances, the output power varied from 29 to 20 dBm. The drain efficiency increased from 50% to 65% at about 6-dB back-off from the peak power of 29 dBm and then decreased back to 50% at the output power of 20 dBm. The variation of drain efficiency versus the output power is plotted in Fig. 6(b). The measured drain efficiency curve confirms the fact that the total loss in the switching transistor and the drain inductor decreases as output power is backed-off by 6 dB and then increases again. A single-stage inverter-based driver operating from a 6-V supply was used to drive the PA. The dc power consumed by the driver stage was around 100 mW. Thus, the overall efficiency of the PA increased from 47% to 49% at about 6-dB back-off from peak power and decreased to 33% at about 9-dB back-off from peak output power. This is plotted in Fig. 6(c). Note that an even better overall efficiency can be achieved if we reduce the driving voltage of the PAs at lower output powers. This is because as mentioned before, the switch loss decreases significantly at lower output powers; hence, it is possible to decrease the switch size or decrease the drive voltage and save on the driving power, at the cost of minimal increase in the switch loss. However, this has not been performed here. Fig. 7 plots the measured drain waveforms for the two PAs at different duty cycles and phase offsets, clearly showing that both PAs achieve ZVS conditions at all settings. Beyond the ZVS contour range, simple outphasing was performed to extend the dynamic range to 30 dB. Thus, the phase offset was further decreased from 60 to 0 , while the duty cycle

Fig. 6. (a) Photograph of the 100-MHz discrete PA operating from a 3-V supply built on an FR4 PCB. (b) Comparison of measured drain efficiency of the proposed scheme and conventional outphasing. (c) Comparison of measured overall efficiency.

was kept fixed at 20%. The efficiency in this regime degraded rapidly due to increased losses in the inductors and and due to the ZVS conditions not being satisfied anymore. To compare the proposed technique with conventional outphasing, the fixed inductance and tunable capacitances at the leading and lagging end were removed; the drain capacitance was kept at the maximum power setting while the duty cycle was kept fixed at 50%. The phase offset between the drives was then decreased and power back-off was realized. However,

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than conventional outphasing in the 9-dB dynamic range, but also offers a 3-dB wider dynamic range due to the simultaneous duty cycle modulation performed in this range. The overall efficiency of the conventional outphasing structure is also plotted in Fig. 6(c). B. Dynamic Simulation Results

Fig. 7. Measured drain voltages of the two PAs at: (a) phase offset , (b) , , and (c) , duty cycle

, .

the drain efficiency degraded rapidly and is plotted in Fig. 6(b). Note that the proposed scheme not only offers better efficiency

As mentioned before, the scheme can be used to generate wide-bandwidth RF modulated signals at gigahertz frequencies. Note that measurement-based verification of a prototype IC (fabricated in 130-nm CMOS technology) has already demonstrated that the ZVS contour PA can be used to generate wide-bandwidth modulated RF signals with good linearity and efficiency [1]. Here we provide simulation-based verification of the performance of the proposed scheme while generating modulated RF signals at gigahertz frequencies. To generate the modulated signals, first a ZVS contour-based outphasing PA was designed to operate at 2.4 GHz and provide a peak power of 25 dBm from a 0.8-V supply. The PA was designed using transistors from 130-nm RF CMOS technology. Realistic models of all passives were used by designing them in ASITIC using the ultra thick metals (UTMs) available in the eight-metal 130-nm RF CMOS process. The simulated drain and PAE at the peak output power was found to be 60% and 50%, respectively. Next, transient simulations in Spectre RF were performed to obtain a relationship between the phase offset and the output voltage [see Fig. 8(a)]. Similarly a relationship between the phase offset [see Fig. 8(b)] and the output phase was obtained. Next envelope and phase signals were generated by using a 20-MHz (RF bandwidth) 9-dB PAR 16-QAM signal. The envelope and phase signals were oversampled at 100 MHz and quantized to 64 distinct levels. The inverse relationship between the output voltage and the phase offset developed before was then utilized to predistort the oversampled and quantized envelope signal and obtain the instantaneous phase offset values. Similarly the phase signal was predistorted using the inverse relationship between the output phase and the phase offset to correct for any systematic AM–PM nonlinearity. This predistorted phase signal is then used by a synthesizer to generate a phase modulated signal. The instantaneous value of phase offset was then used to generate the instantaneous values of signals needed to turn ON/OFF elements in the capacitor banks and the instantaneous duty cycle of the driving waveform using the relationships developed in (10)–(14). Thus, the duty cycle of the phase-modulated driving signal and the number of elements turned ON in the capacitor banks were dynamically changed at 100 MHz to reintroduce the envelope and phase variations in the output signal while forcing the PA to move along a ZVS contour and maintain high efficiency. Simulations suggest that an average drain efficiency of 35% and an average PAE of 25% can be achieved for RF bandwidths up to 40 MHz at an average output power of 15 dBm for a 9-dB PAR 16-QAM signal. The simulated ACPR at an offset of 30 MHz from the center frequency was found to be 35 dBc/Hz, while the error vector magnitude (EVM) achieved was less than 4%. Fig. 8(c) and (d) plots the simulated output spectrum of the scheme for RF bandwidths of 20 and 40 MHz,

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Fig. 8. (a) Relationship between simulated output voltage and phase offset . (b) Plot of simulated output phase with phase offset . (c) Simulated output spectrum for an RF bandwidth of 20 MHz. (d) Simulated output spectrum of for an RF bandwidth of 40 MHz. (e) Plot of simulated average drain efficiency and average PAE versus RF bandwidth.

respectively. Note that since the PA has about 30 dB of dynamic range, it translates to a noise performance of about 5 bits and the ACPR and EVM performance is dominated by this noise floor. Fig. 8(e) plots the simulated average drain efficiency and average PAE of the scheme for RF bandwidths up to 40 MHz. Note that the average drain and PAE do not show appreciable degradation with increasing RF bandwidth, suggesting that the losses in the PA due to the dynamic switching of various capacitor banks are also minimal. An exact analysis of these dynamic losses is the subject of another paper and has been omitted here for the sake of brevity. The performance of the PA in the presence of timing mismatches between the signals changing the capacitor bank settings, as well as the duty cycle, was also studied. For the 20-MHz RF bandwidth 9-dB PAR 16-QAM signal, a misalignment of up to 2 ns between the duty cycle signals and the various capacitor bank signals was randomly introduced. This deteriorated the EVM by 1.5% and had a negligible effect on the ACPR and average efficiency performance of the PA. VI. CONCLUSION In conclusion a novel ZVS contour-based outphasing PA has been presented. The proposed scheme offers a marked improvement in the drain efficiency for 9-dB power back-off over conventional outphasing. The scheme also offers a 3-dB wider dynamic range than conventional outphasing of class-E PAs. The scheme also improves on the dynamic range offered by the previously proposed ZVS contour PA. It extends the dynamic range of the ZVS contour PA from 10 to 30 dB, thus making it suitable to generate high PAR signals with good efficiency.

REFERENCES [1] N. Singhal, N. Nidhi, A. Ghosh, and S. Pamarti, “A 19 dBm 0.13 m CMOS parallel class-E switching PA with minimal efficiency degradation under 6 dB back-off,” in IEEE Radio Freq. Integr. Circuits Symp., Jun. 5–7, 2011, pp. 1–4. [2] N. Singhal, N. Nidhi, and S. Pamarti, “A power amplifier with minimal efficiency degradation under back-off,” in Proc. IEEE Int. Circuits Syst. Symp., May–Jun. 30–2, 2010, pp. 1851–1854. [3] P. Reynaert and M. S. J. Steyaert, “A 1.75-GHz polar modulated CMOS RF power amplifier for GSM-EDGE,” IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2598–2608, Dec. 2005. [4] J. Kitchen, C. Chu, S. Kiaei, and B. Bakkaloglu, “Supply modulators for RF polar transmitters,” in IEEE Radio Freq. Integr. Circuits Symp., Jun.–Apr. 17–17, 2008, pp. 417–420. [5] T. Sowlati, D. Rozenblit, R. Pullela, M. Damgaard, E. McCarthy, D. Koh, D. Ripley, F. Balteanu, and I. Gheorghe, “Quad-band GSM/GPRS/EDGE polar loop transmitter,” IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2179–2189, Dec. 2004. [6] F. Wang, D. F. Kimball, D. Y. Lie, P. M. Asbeck, and L. E. Larson, “A monolithic high-efficiency 2.4-GHz 20-dBm SiGe BiCMOS envelopetracking OFDM power amplifier,” IEEE J. Solid-State Circuits, vol. 42, no. 6, pp. 1271–1281, Jun. 2007. [7] A. Jayaraman, P. F. Chen, G. Hanington, L. Larson, and P. Asbeck, “Linear high-efficiency microwave power amplifiers using bandpass delta–sigma modulators,” IEEE Microw. Guided Wave Lett., vol. 8, no. 3, pp. 121–123, Mar. 1998. [8] J. Keyzer, J. Hinrichs, A. Metzger, M. Iwamoto, I. Galton, and P. Asbeck, “Digital generation of RF signals for wireless communications with bandpass delta-sigma modulation,” in IEEE MTT-S Int. Microw. Symp. Dig., 2001, vol. 3, pp. 2127–2130. [9] F. H. Raab, “High-efficiency linear amplification by dynamic load modulation,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 8–13, 2003, vol. 3, pp. 1717–1720. [10] J. S. Walling, H. Lakdawala, Y. Palaskas, A. Ravi, O. Degani, K. Soumyanath, and D. J. Allstot, “A class-E PA with pulse-width and pulse-position modulation in 65 nm CMOS,” IEEE J. Solid-State Circuits, vol. 44, no. 6, pp. 1668–1678, Jun. 2009. [11] N. Wongkomet, L. Tee, and P. R. Gray, “A 31.5 dBm CMOS RF Doherty power amplifier for wireless communications,” IEEE J. SolidState Circuits, vol. 41, no. 12, pp. 2852–2859, Dec. 2006.

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[12] N. Srirattana, A. Raghavan, D. Heo, P. E. Allen, and J. Laskar, “Analysis and design of a high-efficiency multistage Doherty power amplifier for wireless communications,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 3, pp. 852–860, Mar. 2005. [13] D. Cox, “Linear amplification with nonlinear components,” IEEE Trans. Commun., vol. COM-22, no. 12, pp. 1942–1945, Dec. 1974. [14] H. Chireix, “High power outphasing modulation,” Proc. IRE, vol. 23, no. 11, pp. 1370–1392, Nov. 1935. [15] F. Raab, “Efficiency of outphasing RF power-amplifier systems,” IEEE Trans. Commun., vol. COM-33, no. 10, pp. 1094–1099, Oct. 1985. [16] T.-P. Hung, D. K. Choi, L. E. Larson, and P. M. Asbeck, “CMOS outphasing class-D amplifier with Chireix combiner,” IEEE Microw. Wireless Compon. Lett., vol. 17, no. 8, pp. 619–621, Aug. 2007. [17] J. Grundlingh, K. Parker, and G. Rabjohn, “A high efficiency Chireix out-phasing power amplifier for 5 GHz WLAN applications,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 6–11, 2004, vol. 3, pp. 1535–1538. [18] I. Hakala, D. K. Choi, L. Gharavi, N. Kajakine, J. Koskela, and R. Kaunisto, “A 2.14-GHz Chireix outphasing transmitter,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 6, pp. 2129–2138, Jun. 2005. [19] M. P. Van Der Heijden, M. Acar, J. S. Vromans, and D. A. Calvillo-Cortes, “A 19 W high-efficiency wideband CMOS-GaN class-E Chireix RF outphasing power amplifier,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 5–10, 2011, pp. 1–4. [20] W. Gerhard and R. Knoechel, “Novel transmission line combiner for highly efficient outphasing RF power amplifiers,” in Eur. Microw. Conf., Oct. 9–12, 2007, pp. 1433–1436. [21] M. C. A. Van Schie, M. P. Van Der Heijden, M. Acar, A. J. M. De Graauw, and L. C. N. De Vreede, “Analysis and design of a wideband high efficiency CMOS outphasing amplifier,” in IEEE Radio Freq. Integr. Circuits Symp., May 23–25, 2010, pp. 399–402. [22] J. H. Qureshi, M. J. Pelk, M. Marchetti, W. C. E. Neo, J. R. Gajadharsing, M. P. van der Heijden, and L. C. N. de Vreede, “A 90-W peak power GaN outphasing amplifier with optimum input signal conditioning,” IEEE Trans. Microw. Theory Tech., vol. 57, no. 8, pp. 1925–1935, Aug. 2009. [23] R. Beltran, F. H. Raab, and A. Velazquez, “HF outphasing transmitter using class-E power amplifiers,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 7–12, 2009, pp. 757–760. [24] S. Moloudi, K. Takinami, M. Youssef, M. Mikhemar, and A. Abidi, “An outphasing power amplifier for a software-defined radio transmitter,” in IEEE Int. Solid-State Circuits Conf. Tech. Dig., Feb. 3–7, 2008, pp. 568–636. [25] N. Singhal, N. Nidhi, R. Patel, and S. Pamarti, “A zero-voltageswitching contour-based power amplifier with minimal efficiency degradation under back-off,” IEEE Trans. Microw. Theory Tech., vol. 59, no. 6, pp. 1589–1598, Jun. 2011. [26] A. Grebennikov and N. O. Sokal, “Switch mode RF power amplifiers,” Newness, pp. 254–255, 2007, 1st ed. [27] R. Zulinski and J. Steadman, “Class E power amplifiers and frequency multipliers with finite DC-feed inductance,” IEEE Trans. Circuits Syst., vol. CAS-34, no. 9, pp. 1074–1087, Sep. 1987. [28] M. Ozen, C. M. Andersson, M. Thorsell, K. Andersson, N. Rorsman, C. Fager, M. Acar, M. P. van der Heijden, and R. Jos, “High efficiency RF pulsewidth modulation with tunable load network class-E PA,” in IEEE 12th Annu. Wireless Microw. Technol. Conf., Apr. 18–19, 2011, pp. 1–6. [29] O. Lee, K. H. An, H. Kim, D. H. Lee, J. Han, K. S. Yang, C.-H. Lee, H. Kim, and J. Laskar, “Analysis and design of fully integrated highpower parallel-circuit class-E CMOS power amplifiers,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 3, pp. 725–734, Mar. 2010. [30] C. Yoo and Q. Huang, “A common-gate switched 0.9-W class-E power amplifier with 41% PAE in 0.25- m CMOS,” IEEE J. Solid-State Circuits, vol. 36, no. 5, pp. 823–830, May 2001. [31] F. H. Raab, “Electronically tuned power amplifier,” U.S. Patent 7 202 734, Apr. 10, 2007. [32] F. H. Raab, “Idealized operation of the class E tuned power amplifier,” IEEE Trans. Circuits Syst., vol. CAS-24, no. 12, pp. 725–735, Dec. 1977.

[33] M. Acar, A. J. Annema, and B. Nauta, “Analytical design equations for class E power amplifiers,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, no. 12, pp. 2706–2717, Dec. 2007. [34] F. Wang, D. F. Kimball, D. Y. Lie, P. M. Asbeck, and L. E. Larson, “A monolithic high-efficiency 2.4-GHz 20-dBm SiGe BiCMOS envelopetracking OFDM power amplifier,” IEEE J. Solid-State Circuits, vol. 42, no. 6, pp. 1271–1281, Jun. 2007. [35] N. Wongkomet, L. Tee, and P. R. Gray, “A 31.5 dBm CMOS RF Doherty power amplifier for wireless communications,” IEEE J. SolidState Circuits, vol. 41, no. 12, pp. 2852–2859, Dec. 2006. [36] A. Kavousian, D. K. Su, M. Hekmat, A. Shirvani, and B. A. Wooley, “A digitally modulated polar CMOS power amplifier with a 20-MHz channel bandwidth,” IEEE J. Solid-State Circuits, vol. 43, no. 10, pp. 2251–2258, Oct. 2008. [37] S. Kousai and A. Hajimiri, “An octave-range watt-level fully integrated CMOS switching power mixer array for linearization and back-off efficiency improvement,” in IEEE Int. Solid-State Circuits Conf. Tech. Dig., Feb. 8–12, 2009, pp. 376–377. [38] D. Chowdhury, L. Ye, E. Alon, and A. M. Niknejad, “A 2.4 GHz CMOS mixed-signal polar power amplifier with low-power integrated filtering in 65 nm CMOS,” in IEEE Custom Integr. Circuits Conf., Sep. 19–22, 2010, pp. 1–4. [39] C. D. Presti, F. Carrara, G. Palmisano, and A. Scuderi, “A high-resolution 24-dBm digitally-controlled CMOS PA for multi-standard RF polar transmitters,” in 34th Eur. Solid-State Circuits Conf., Sep. 15–19, 2008, pp. 482–485.

Nitesh Singhal (S’06–M’10) received the Bachelors and Masters degrees in technology from the Indian Institute of Technology, Kharagpur, India, in 2005. In 2005, he joined the University of California at Los Angeles (UCLA), as a doctoral student. He is mostly interested in wireless communication system hardware, especially RF and mixed-signal circuit blocks such as RF transmitters. His area of research is primarily applying digital techniques in mixed signal and RF circuits.

Haoxing Zhang (S’11) is currently working toward the B.Tech degree in electrical engineering from Zhejiang University, Hangzhou, China. His research interest is mainly concerned with wireless communication system design, both on a circuit and system level. As an undergraduate student, he has led a research project on wireless sensor networks. He has also been involved with the modeling of some digital RF circuits.

Sudhakar Pamarti (S’98–M’03) received the B.Tech. degree in electronics and electrical communication engineering from the Indian Institute of Technology, Kharagpur, India, in 1995, and the M.S. and Ph.D. degrees in electrical engineering from the University of California at San Diego, La Jolla, in 1999 and 2003, respectively. He is currently with the University of California at Los Angeles (UCLA). His research concerns the development of mixed-signal circuit-based solutions to problems that are traditionally solved using analog circuitry.

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Modeling and Digital Predistortion of Class-D Outphasing RF Power Amplifiers Per N. Landin, Student Member, IEEE, Jonas Fritzin, Student Member, IEEE, Wendy Van Moer, Senior Member, IEEE, Magnus Isaksson, Member, IEEE, and Atila Alvandpour, Senior Member, IEEE

Abstract—This paper presents a direct model structure for describing class-D outphasing power amplifiers (PAs) and a method for digitally predistorting these amplifiers. The direct model structure is based on modeling differences in gain and delay, nonlinear interactions between the two paths, and differences in the amplifier behavior. The digital predistortion method is designed to operate only on the input signals’ phases, to correct for both amplitude and phase mismatches. This eliminates the need for additional voltage supplies to compensate for gain mismatch. Model and predistortion performance are evaluated on a 32-dBm peak-output-power class-D outphasing PA in CMOS with on-chip transformers. The excitation signal is a 5-MHz downlink WCDMA signal with peak-to-average power ratio of 9.5 dB. Using the proposed digital predistorter, the 5-MHz adjacent channel leakage power ratio (ACLR) was improved by 13.5 dB, from 32.1 to 45.6 dBc. The 10-MHz ACLR was improved by 6.4 dB, from 44.3 to 50.7 dBc, making the amplifier pass the 3GPP ACLR requirements. Index Terms—Behavioral modeling, digital predistortion, LINC, outphasing amplifier, power amplifiers (PAs).

I. INTRODUCTION

E

FFICIENT AND linear amplification of amplitude-modulated high-frequency signals still poses a major problem in modern wireless transmitters. An amplifier structure that aims at increasing efficiency while maintaining linearity is the outphasing amplifier [1], [2].

Manuscript received July 13, 2011; revised January 27, 2012; accepted January 30, 2012. Date of publication February 27, 2012; date of current version May 25, 2012. This work was supported by the Swedish Research Council (VR), the Excellence Center, Linköping-Lund in Information Technology (ELLIIT), Ericsson Research, the Research Foundation Flanders (FWO) under a postdoctoral fellowship, the Flemish Government (METH1), and the LM Ericsson Research Foundation under a grant. P. N. Landin is with the Department of Electronics, Mathematics and Natural Sciences, University of Gävle, 80176 Gävle, Sweden, and also with the Statistical Signal Processing Laboratory, ACCESS Linneaus Center, KTH Royal Institute of Technology and Department ELEC, Vrije Universiteit Brussel, 1050 Ixelles, Belgium (e-mail: [email protected]). J. Fritzin was with the Department of Electrical Engineering, Linköping University, 581 83 Linköping, Sweden. He is now with Ericsson AB, 115 41 Stockholm, Sweden (e-mail: [email protected]). W. Van Moer is with the Department of Electronics, Mathematics and Natural Sciences, University of Gävle, 80176 Gävle, Sweden, and also with the Department ELEC, Vrije Universiteit Brussel, 1050 Ixelles, Belgium. M. Isaksson is with the Department of Electronics, Mathematics and Natural Sciences, University of Gävle, 80176 Gävle, Sweden. A. Alvandpour is with the Department of Electrical Engineering, Linköping University, 581 83 Linköping, Sweden (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2012.2187532

The outphasing amplifier is based on separately amplifying two purely phase-modulated signals using efficient amplifiers, such as switching amplifiers, and then combining these two signals to restore the original amplitude- and phase-modulated signal. In recent years, the interest in the outphasing amplifier architecture and its’ potential for high-efficiency operation has resulted in many new techniques to further improve the power efficiency. Outphasing power amplifiers (PAs) using class-D amplifiers have been implemented and tested in [3]–[7]. These have all evaluated the performance on uplink-like signals when considering telecommunication standards or wireless local area network (WLAN). Methods to improve the efficiency in back-off have been proposed by dynamic power control implemented by turning off amplifier stages [5], more efficient-combining network topologies [8], [9], multilevel and multimode techniques [10], [11] and power-recycling techniques [12], [13]. Ideally, the outphasing amplifier should provide linear amplification. However, in practice, outphasing amplifiers experience mismatch in gain and phase [14], different behavior in the two amplifiers [14], finite bandwidth [15] and interactions between the branches [16]. Analysis of these sources generating nonlinear distortions was done in [14]–[20]. Nonlinear distortion in outphasing amplifiers arising from nonideal switching in class-D amplifiers was analyzed in [6]. Corrections for these sources of nonlinear distortions have been proposed earlier by adjusting the amplitudes and/or phases of the input signals [17]–[24]. In the case of phase-only predistortion, the predistorters did consider Chireix combiners [17], but without amplitude mismatch. In this paper, the focus is on analyzing and correcting the undesired behavior of outphasing amplifiers using baseband processing techniques. This is done to make the outphasing amplifier pass regulatory requirements on linearity measures, such as adjacent channel leakage power ratio (ACLR). In a first step, a new black-box behavioral model describing the relationship between the input and output signals is derived. The proposed model includes all the previously mentioned sources of nonlinear behavior, except for the bandwidth limitation in [15]. However, the model can be extended to include this behavior as well. A black-box model using a similar basic idea was proposed in [3], but it operated on the phase of the outphasing signals, and was evaluated on a low-power PA for user equipment signals with lower peak-to-average-power ratio (PAPR) 3 dB. In this paper, the model is based on the amplitude, and it also takes timing distortions into account. The

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results are evaluated for more demanding base-station signals with PAPR 10 dB and more stringent ACLR requirements. Once the direct model is identified, the predistorter parameters are searched for by putting the predistorter in front of the model and performing a search for the predistorter parameters. Using a direct model to numerically identify the predistorter is not a novel idea, but to the authors’ best knowledge, it has not been used for the direct model or the predistorter model, as proposed in this paper. The predistortion method has not been implemented in hardware, but is applicable at the baseband level. The goal is to find suitable models to describe the amplifier and predistorters for class-D outphasing PAs, compensating amplitude and gain mismatches without requiring a second voltage supply to compensate the amplitude mismatch. The performance of the proposed predistorter is experimentally evaluated on a 32-dBm peak output power CMOS class-D outphasing PA [4]. This peak power is the highest reported for all class-D RF PAs [4]. Class-D amplifiers necessitates the use of phase-only predistortion to compensate both amplitude and phase mismatches, due to the constant envelope output of the class-D stages, unlike previously proposed predistorters. The earlier proposed predistorters change the input signal amplitude when linear amplifiers are used [18], [21], [22], or include adjustments of the voltage through the use of multiple voltage supplies in the output stage [23], [24] to compensate for the gain mismatch. Using the method proposed in this paper, only a single voltage supply is necessary. Due to the nonlinear nature of the models, the extraction of the model and the predistortion parameters becomes a nonlinear problem. Methods for deriving parameter values used to initiate the search for both direct model and predistorter parameters are proposed. In short, the contributions of the paper are: 1) the derivation of a black-box model for outphasing amplifier behavior; 2) a phase-only predistortion method that compensates both amplitude and phase mismatches; and 3) proposing initial values for starting the parameter search. This paper starts by introducing the concept of the outphasing amplifier in Section II in order to motivate the choices of direct model and predistorter structures. A behavioral model for outphasing amplifier structures is given in Section III. A digital predistortion model is proposed in Section IV. Methods for estimating the initial parameters of both behavioral model and digital predistorter are given in Section V. The measurement setup and outphasing amplifier used to obtain data for modeling and predistortion are described in Section VI. Results from the modeling and predistortion are presented in Section VII. II. OUTPHASING AMPLIFIER The signals considered here are sampled complex valued baseband signals (1) being the amplitude modulation and being the with phase modulation. is the sampling instant for sample using a sampling rate of .

Fig. 1. Geometric explanation behind the construction of the outphasing sigis the outphasing angle, is the angle of the original signal . nals. is the component from (2) and (3) used to create the constant envelope amand . plitude signals

Fig. 2. Illustration of the outphasing amplification concept. The dotted box represents parts that are considered to belong to the outphasing amplifier: the two amplifiers A1 and A2 and the combiner. The SCS applies the transformation of , creating the envelope amplitude constant the expressions in (2) and (3) to and . These signals are amplified by the (non)linear amplisignals . fiers A1 and A2, and finally combined into the output signal

The baseband signal can be decomposed as the sum of two amplitude envelope constant signals by writing [25] (2) and (3) is the maximum value of the amplitude , where is the outphasing angle, is the phase modulation from (1), and . The signal is constructed as (4) This is illustrated in Fig. 1. It should be noted that the signal has wider bandwidth than the original signal and extends into the adjacent channels. Any imbalance between branches will make the distort the output spectrum and degrade ACLR. The transformation from to and is the function of the signal component separator (SCS) in Fig. 2. The operation of the outphasing amplifier is illustrated in Fig. 2. The outphasing amplifier is considered to consist of the two amplifiers A1 and A2 and the combiner. In Fig. 2, the outphasing amplifier and SCS are illustrated in baseband form. The baseband signals and are modulated onto a carrier and

LANDIN et al.: MODELING AND DIGITAL PREDISTORTION OF CLASS-D OUTPHASING RF PAs

input to the outphasing amplifier. The output signal is then measured and transformed back to low-pass equivalent form. However, as the direct model and predistorter operate on baseband signals, that perspective is kept throughout this paper. The lowest amplitude the output signal can reach is limited by the difference between the two output power levels in the two amplifiers [3]. A measure of the maximum-to-minimum ratio of an output signal is given by the dynamic range (5) and are the static gains of paths 1 and 2, respecwhere tively. The static gain in relation to the models is further discussed in Section III. The influence of limited dynamic range was analyzed in [14]. III. BEHAVIORAL MODEL In outphasing amplifiers, nonlinear distortions are caused by different delays, gains, nonlinear behavior of the two amplifiers, A1 and A2 [14], nonlinear interactions between the two paths [16], memory effects due to heating [21], and bandwidth limitations in the signal generation and/or amplifier matching networks [15]. No low-frequency memory effects from heating, or high-frequency memory effects due to frequency dependence of the amplifier, in the form of dependency on previous input (or output) samples, are used in this study. The structure of the amplifier should be reflected in the model. Thus, the output is modeled as a sum of two different functions and

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process using four on-chip transformers is not ideal, there will be gain mismatches between the amplifier stages. There, the gain mismatches creates both amplitude and phase distortion. Additionally, the class-D stages can contribute with nonlinear behavior due to nonideal operation [6]. Since no sufficiently accurate trigger is available, the sampled output signal cannot be used directly for modeling purposes. Initial estimates are provided using a cross-correlation method followed by a phase interpolation (see Section VI for details). This corresponds to having one time offset between the two input signals and the output signal. However, there is also the possibility of having different delays in the two amplifier paths [14], meaning that an additional relative delay between the paths should be included. Together this makes the use of two separate delay terms necessary: one to describe the difference in runtime between the paths and one to describe the total offset between the input signals and the output signal. This can be written as (8) being the time offsets. and are with the low-pass equivalent output signals of the amplifiers A1 and A2, respectively. For theoretical applications, one offset can be removed because the input–output synchronization is a measurement related problem. Nevertheless, both terms should be considered in a practical implementation, unless there is a guarantee that no mismatch in delay exists. Putting all of the above together gives the modeled output signal

(6) being the model parameters. with The functions and are chosen as complex exponential functions with separate gain functions and . These gain functions are introduced with reference to the nonlinear interactions between the amplifiers [16]. Hence, the model is formulated as

(7) where and are the parameters of the gain functions and , respectively, while and are the parameters for the phase distortion functions of paths 1 and 2, respectively. The functions and should each be chosen such that they have one component that is independent of the signal. This is the static gain termed and , respectively, in (5). In this study, amplifiers A1 and A2 are class-D amplifiers, which means that they operate as switches, i.e., the output is tied to either or ground. Ideally, such stages can be considered ideal voltage sources whose output voltages are independent of the load [26]. The amplifier used for experimental verifications uses four transformers as combiners [4], i.e., there is no isolation between the paths. The envelope of class-D stages is constant, which means that the input amplitude cannot be changed in order to change the envelope amplitude. As the signal-combining

(9) with as the model parameter vector. are the parameters of the gain functions , , the parameters of the phase distortion functions , and is the timing mismatch for path , where . A normalization of the measured output signal is used by setting the maximum amplitude of to have the same maximum amplitude as that of . This choice is made because there is no combination of and that can give a larger amplitude than this. The exact forms of the functions and have thus far not been specified. These can be chosen as arbitrary functions of the input signal . Here, they are chosen as polynomials in the input amplitude, i.e., (10) for the phase distortion of path , and similar for the gain function . With this choice, the static gains and are given by and , respectively. With the used expressions, memory can be included by introducing a dependency on previous input samples, similar to a memory polynomial structure.

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Behavioral models of RF PAs normally consider single-RFinput systems, such as traditional class-AB, class-B, and singleinput Doherty PAs (see [27]–[29] and the references therein). Models for multi-input RF PAs have considered envelope-elimination and restoration (EER), envelope tracking (ET), and dynamic load modulation transmitters [30], [31], although in principle similar methods could be used for outphasing amplifiers. In [3], a model similar to the one proposed in this paper was used. That model used the outphasing phase as input signal and could not model any gain variation. IV. DIGITAL PREDISTORTION Ideally, the outphasing amplifier is perfectly linear, i.e., the outphasing amplifier should take an input signal and deliver a linearly amplified version at the output of the PA. Considering published outphasing PAs, they typically do not need digital predistortion for uplink/terminal applications [4]–[7], [32]. However, basestation signals with larger peak-to-average power ratio, i.e., larger phase variations, and more strict linearity requirements are used in the measurements, therefore digital predistortion is needed to make the output signal from the outphasing amplifier pass regulatory requirements such as spectral mask and ACLR limits [33]. To the authors’ best knowledge, this is the first class-D outphasing PA demonstrating sufficient linearity for base-station signals. Due to the use of class-D amplifiers, the input amplitudes must be kept constant, i.e., no predistorter functions changing the amplitudes of the input signals are allowed. The different gain factors limit the achievable dynamic range [19]. However, within this dynamic range, the outphasing amplifier can reach all amplitudes by changing the phases of the two input outphasing signals. By changing only the phases, the need for additional voltage supplies, when eliminating the gain mismatch via the supplies, is avoided [23], [24]. Using phase-only predistortion functions leaves one natural choice for the predistorted signals: complex exponential functions as

By using the predistorted signals and as input signals instead of and , the idea is to make the predistorted outphasing amplifier behave as a linear amplifier. Finding the parameters and of the predistorter is done by using the direct model to model the predistorted output signal. An error criterion based on the difference between the input signal and a scaled version of the output signal is used to reach the goal of a linearly behaving outphasing amplifier. The search for the predistorter parameters is explained in detail in Section V. A phase-only predistortion model for Chireix combiners was proposed in [17], but did not consider amplitude mismatch or other combiner architectures. The predistorter proposed in this paper is applicable to all combiner architectures, and additionally handles differences in gain, path delay, and nonlinear characteristics. However, this flexibility comes at the cost of a computationally more expensive parameter identification method. In [34], a predistortion was implemented by comparing the input and output samples to create a memoryless predistorter for a high-power GaN mixed-mode outphasing PA. Other implementations of predistorters have used the physical approach of considering gain and phase imbalance [21]–[23], [35]. The predistorter that was proposed in [3] shares the general structure with the predistorter proposed here, although it operates on the outphasing angle and it lacks initial value estimates. If both output signals and were available, one could view the system as a two-input two-output system with cross-terms describing the influence of one amplifier on the other. However, that is not the case as we only have access to the sum of these signals in the form of . Thus, the predistorter must be found using only the measured output signal . V. PARAMETER ESTIMATION This section introduces the numerical goals of the direct model and the predistorter in terms of error criteria that are to be minimized. The search for the parameters starts with the parameters of the direct model, as these are needed to find the parameters of the predistorter.

(11) A. Direct Model

for path 1 and (12) for path 2. and are the predistorter parameters for paths 1 and 2, respectively, and and are the phasepredistortion functions. signifies the direct model parameters, as in (9). The adopted form for the phase distortion functions are also polynomials in the input envelope amplitude , i.e., (13) with being the order. Also, it is possible to include dependency on previous input samples in the form of a memory polynomial if desired.

The direct model should describe the relationship between the input and output signals with as low model error as possible. This requirement is translated as an error measure that is to be minimized. The sum-square error given by (14) is the difference between the modeled output is used. Here, and the measured output . The task is now to find the parameters that minimizes (14). This is a nontrivial task as the model is nonlinear in at least some of the parameters: the delays and and the parameters and of the phase polynomials. Depending on which functions are used for and , the problem can be linear or nonlinear in these parameters.

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Initial estimates for the parameters and in the gain functions and are obtained by assuming that the phase distortion is 0 in a first step. That is, find such that

(15) is minimized. If and are linear in the parameters, this problem is a linear least squares problem. As an example, consider the case when and are constants, then the minimization of (15) is equivalent to solving the system of linear equations given by (16) , , and where , , and are the samples of stacked into column vectors. Given the estimates and above, one can form estimates of the output signals from amplifier A1 and from amplifier A2. Recall that the output signal is the sum of and as

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If the function is linear in the parameters, minimizing (22) is a linear least squares problem. The initial parameter estimates for can be obtained in a similar way as for . Initial estimates for the time offsets and can, in this case, be set to 0 because the output signal is synchronized to the input signal using a phase interpolation synchronization method. It is assumed that the amplifier and measurement setup are sufficiently well designed to have negligible difference in delay between the paths as a first estimate. Initial estimates for all parameters have now been found. The model parameters can now be searched for using a nonlinear optimization method [36] that minimizes the model error in (14) as function of the parameters . B. Digital Predistortion For the predistortion, the problem is similar to the problem of estimating the parameters in the direct model. However, a major difference is that the predistorted signal is passed through the direct model. This makes the parameter estimation a nonlinear problem. The reason this is done is because one no longer wants to have an output signal from the model that is similar to the measured output signal, but rather to make it similar to a linearly amplified version of the original input signal. As a cost function, the sum-square error

(23) (17) with

being the model error. Approximate the signals and with (18)

respectively, (19) By rearranging (17), an estimate of

is obtained as (20)

and of

as (21)

The amplitude difference is now estimated and parameterized. The remaining error that should be estimated is the phase difference between and . This difference is approximated by the function by minimizing (22) with respect to

.

is used. is the predistorted error signal, i.e., the difference between the original input signal and a linearly scaled version of the measured output signal. is the modeled output signal from the amplifier when the predistorted input signal is used. are the parameters in the digital predistortion algorithm. We now know, based upon earlier discussion, that no adjustments to the amplitude of the input signals are allowed due to the class-D operation of the amplifiers. Thus, parameters requiring an initial estimate are the parameters in the phase polynomials (11) and (12). The idea is now to establish approximate inverses of the phase distortion in A1 and A2. For this purpose it is assumed that the inverse phase distortion in each amplifier (A1 and A2) can be approximated by a polynomial in . In line with the th-order inverse of Volterra theory [37], a polynomial is a possible choice for inverting function of another polynomial. Now we have transformed the problem into one that consists of finding the approximate inverse of a polynomial using another polynomial. We want to use the derived model as a predistorter, i.e., operating on the input signal to the outphasing amplifier, the inverse we are seeking is a pre-inverse. Due to a theorem by Schetzen [37], we know that the pre-inverse of a Volterra system is equal to the post-inverse, up to a given order . Using the above similarity of post- and pre-inverses, we say that a first estimate of the pre-inverse of the phase

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distortion is given by the post-inverse of the phase distortion in each branch. This is a problem that is linear in the parameters, if the functions and are linear in the parameters. Hence, for path 1, the initial parameters of the phase predistortion are found by solving (24) where denotes the angle of . This is a parameterlinear problem if is parameter linear in . As an example, consider the case where is linear in the parameters . Equation (24) can then be solved using a linear least squares method. To illustrate this, let with being a column vector formed from the values of , and being the regression matrix. Using the similarities between the post- and pre-inverse discussed earlier, (24) can be rewritten as

Fig. 3. Principle of the measurement setup containing a signal generator with phase coherent outputs and a vector signal analyzer. All instruments are connected to a PC running MATLAB for instrument control, modeling, digital preand distortion, and signal component separation. The baseband signals are transferred to the vector signal generators, modulated onto a carrier and input to amplifiers A1 and A2, respectively. The amplified signals are output , which is sampled and from the amplifiers and added to create the signal processed by the vector signal analyzer.

(25) . where is a column vector formed from the angles of Equation (25) is linear in the parameters . denotes the standard Euclidean norm. The same approach is used for estimating initial values for the predistortion parameters for path 2. All parameters now have initial estimates meaning that (23) can be minimized using an optimization method, as for the minimization of the direct model error in (14). However, the lowest amplitudes cannot be fully corrected due to the gain imbalance. An initial estimate used to start the parameter search ignores the samples of lowest amplitude in (24). However, the final results take this amplitude range into account by the use of the search method.

Fig. 4. Principle of the used class-D outphasing amplifier (from [4]).

VI. MEASUREMENT SETUP The measurement equipment for testing outphasing amplifiers is similar to that used for behavioral modeling and digital predistortion of other amplifier types. This means a vector signal analyzer is required for the measurements and a vector signal generator is needed for the signal generation. The measurement equipment used is an R&S FSQ26 vector signal analyzer and two R&S SMBV100A vector signal generators with the phase-coherent RF output option. This equipment is controlled by a PC running MATLAB. Signal component separation, i.e., the operation of the SCS in Fig. 2, is done in MATLAB. The baseband outphasing signals and , with sampling rates of 92 MHz, are uploaded to the signal generators and modulated onto a carrier. The setup is shown in Fig. 3. Synchronization of the input signal and the measured output signal must be done prior to any modeling as the measurement system is asynchronous. A coarse synchronization is given by a cross-correlation between the input and output signals. A phase interpolation [29] is then applied to achieve sub-sample synchronization. However, there is no guarantee that this gives a sufficiently good synchronization between the

Fig. 5. Chip photograph of the outphasing amplifier (from [4]).

three terms , , and , but it is a first estimate used in the modeling process. The noise in the measured output signal is reduced using coherent averaging [29]. The output signal is averaged five times. The outphasing PA is based on eight class-D amplifier stages, whose outputs are combined by utilizing four on-chip transformers (see Fig. 4 for the amplifier principle and Fig. 5 for the chip photograph). The signals and are connected as described in [6]. The peak output power is 32 dBm, demonstrating state-ofthe-art output power of class-D RF PAs and is one of the first fully integrated watt-level outphasing PAs [4], [5], [7]. The outputs of the class-D stages connected to the transformers are driven by a tapered buffer. The gain is 22 dB from the input

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Fig. 7. Model performance as NMSE and ACEPR are shown as functions of the order of the phase polynomial when the gain functions are kept constant.

Fig. 6. Measured output power ( ), drain efficiency (DE) and power-added efficiency (PAE) are shown as functions of the outphasing angle (from [4]). Note that the outphasing angle is defined over 90 90 due to the way it is introduced in Fig. 1.

of the buffer to the output. The dc power consumption of the smallest buffer stage (inverter) was considered as input power. The measured output power over outphasing angle at 1.85 GHz is shown in Fig. 6. The dynamic range of the amplifier is 40 dB at 1.85 GHz [4]. The output stage of the PA was designed for a 5.5-V supply and was driven by a 1.3-V driver. In order to avoid excessive heating of the device, the supply voltage in the output stage was lowered to approximately 4.1 V, resulting in an average output power of 20 dBm and peaks around 29.5 dBm. Thus, the 32- and 29.5-dBm output power levels are achieved at the same outphasing angle, but with different supply voltages in the output stage. The excitation signals that were used are two downlink 5-MHz 16-QAM WCDMA signals with PAPR of 9.5 dB. One signal is used to identify the model and predistorter parameters, while the other is used to validate model and predistorter performance. VII. RESULTS All results presented here are for the validation data set, i.e., the data set that was not used to extract the model parameters. The direct model performance is measured using the normalized mean square error (NMSE) and the adjacent channel error power ratio (ACEPR). The NMSE is given by (26) with

being the estimated power spectrum of the signal , and being the estimated power spectrum of the model error . The integrations are made over the available bandwidth BW. The ACEPR is given by [29] (27) with and as for the NMSE. The integration in the numerator is done over the channel containing the input signal. For the denominator, the integration is done over the adjacent channel (upper or lower) containing the largest model error

Fig. 8. 5- and 10-MHz ACLR for the used WCDMA signal are shown as functions of the dynamic range, defined in (5), i.e., when there is amplitude mismatch between the two class-D stages. The first case (marked “no DPD”) shows the ACLR when the WCDMA signal is transmitted through an outphasing amplifier with limited dynamic range. The second case (marked “DPD”) shows the achievable performance when the amplitude mismatch is compensated as far as possible, i.e., there is distortion only in the samples with amplitudes below the dynamic range defined in (5). This indicates the lowest achievable ACLR for an outphasing amplifier, assuming that a predistorter can correct all distortion, except the gain mismatch below the dynamic range. The limitations of 48and 55-dBc ACLR at 5- and 10-MHz offset, respectively, are due to the used WCDMA signal.

power [29]. For the predistortion, ACLR is used as a measure of predistortion performance. The model performance as NMSE and ACEPR are computed for orders of the phase polynomial going from 1 to 10. The gain functions and are kept constant, thus considering the class-D amplifiers to operate at constant amplitude. The obtained model performance is shown in Fig. 7 as functions of the phase polynomial order. At a model order of 5, no gains in model performance is achieved by further increasing the polynomial order. A model with this performance should have sufficient performance to be used for extracting the predistorter. Note that, for simplicity, we have restricted the modeling to only consider the same polynomial order for both paths 1 and 2. Using the model proposed in [3], the lowest NMSE was 32.3 dB and the lowest ACEPR was 44.3 dB. Since the model proposed in this paper has lower model errors, the predistorter is extracted on the models in (9) proposed in this paper. According to the static gains in and , the amplifier dynamic range, defined in (5), is approximately 40 dB, in agreement with the measurements in [4]. Limited dynamic range puts limits on the achievable ACLR due to the amplitude mismatch. Assuming a correction method that can correct all errors, except

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REFERENCES

Fig. 9. Power spectra of the original output signal and the predistorted WCDMA signal.

TABLE I MEASURED ACLR FOR WCDMA WITH RESPECT TO 3GPP REQUIREMENTS

the gain mismatch below the dynamic range, what ACLR can be achieved? Fig. 8 shows the ACLR without and with correction for the case of pure amplitude mismatch, as it is assumed that all other errors can be perfectly corrected. With 40-dB dynamic range, the lowest 5- and 10-MHz ACLR are 48 and 55dBc, respectively. The performance of the predistorter using a direct model of order 1 for and , and order 5 for , and a predistorter of order 5 for and is shown in Fig. 9. Measured ACLR values are given in Table I. The predistortion improves the 5-MHz ACLR by approximately 13.5 dB, from 32.1 to 45.6 dBc, and the 10-MHz ACLR by 6.4 dB, from 44.3 to 50.7 dBc. Thus, the predistorter makes the PA fulfill the ACLR requirements according to 3GPP [33]. The error vector magnitude (EVM) is also improved from approximately 5% to approximately 1.5%. VIII. CONCLUSIONS A novel nonlinear black-box model structure for modeling outphasing amplifiers has been introduced. It allows for flexible modeling of outphasing amplifiers by considering time and gain mismatches, different nonlinear behavior in the amplifiers, and nonlinear interaction between the amplifiers through the use of arbitrary amplitude and phase distortion functions. A phase-only predistortion algorithm based on the direct model was also proposed. This predistorter successfully linearized a 32-dBm peak power CMOS class-D outphasing PA to fulfill the linearity requirements according to the 3GPP standards when using a 5-MHz WCDMA signal with 9.5-dB PAPR. The performance improvements were as follows: the 5-MHz ACLR decreased by 13.5 dB, from 32.1 to 45.6 and the 10-MHz ACLR decreased by 6.4 dB, from 44.3 to 50.7 dBc. Theoretical limits on achievable ACLR due to limited dynamic range, i.e., gain mismatch, were also presented.

[1] D. Cox, “Linear amplification with nonlinear components,” IEEE Trans. Commun., vol. COM-22, no. 12, pp. 1942–1945, Dec. 1974. [2] H. Chireix, “High power outphasing modulation,” Proc. IRE, vol. 23, no. 11, pp. 1370–1392, Nov. 1935. [3] J. Fritzin, Y. Jung, P. N. Landin, P. Händel, M. Enqvist, and A. Alvandpour, “Phase predistortion of a class-D outphasing RF amplifier in 90 nm CMOS,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 58, no. 10, pp. 642–646, Oct. 2011. [4] J. Fritzin, C. Svensson, and A. Alvandpour, “A 32 dBm 1.85 GHz class-D outphasing RF PA in 130 nm CMOS for WCDMA/LTE,” in IEEE Eur. Solid-State Circuits Conf., Sep. 2011, pp. 127–130. [5] W. Tai, H. Xu, A. Ravi, H. Lakdawala, O. Degani, L. Carley, and Y. Palaskas, “A 31.5 dBm outphasing class-D power amplifier in 45 nm CMOS with back-off efficiency enhancement by dynamic power control,” in Proc. Eur. Solid-State Circuits Conf., Sep. 2011, pp. 131–134. [6] H. Xu, Y. Palaskas, A. Ravi, M. Sajadieh, M. El-Tanani, and K. Soumyanath, “A flip-chip-packaged 25.3 dBm class-D outphasing power amplifier in 32 nm CMOS for WLAN application,” IEEE J. Solid-State Circuits, vol. 46, no. 7, pp. 1596–1605, Jul. 2011. [7] J. Fritzin, C. Svensson, and A. Alvandpour, “A wideband fully integrated 30 dBm class-D outphasing RF PA in 65 nm CMOS,” in Proc. IEEE Int. Integr. Circuits Symp. , Dec. 2011, pp. 25–28. [8] D. Perreault, “A new power combining and outphasing modulation system for high-efficiency power amplification,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 58, no. 8, pp. 1713–1726, Aug. 2011. [9] W. Gerhard and R. Knoechel, “Improved design of outphasing power amplifier combiners,” in Proc. German Microw. Conf., Mar. 2009, pp. 1–4. [10] M. Helaoui, S. Boumaiza, F. M. Ghannouchi, A. B. Kouki, and A. Ghazel, “A new mode-multiplexing LINC architecture to boost the efficiency of WiMAX up-link transmitters,” IEEE Trans. Microw. Theory Tech., vol. 55, no. 2, pp. 248–253, Feb. 2007. [11] P. Godoy, S. Chung, T. Barton, D. Perreault, and J. Dawson, “A 2.5-GHz asymmetric multilevel outphasing power amplifier in 65-nm CMOS,” in Proc. IEEE Power Amplifiers for Wireless Radio Appl. Top. Conf., Jan. 2011, pp. 57–60. [12] R. Langridge, T. Thornton, P. Asbeck, and L. Larson, “A power re-use technique for improved efficiency of outphasing microwave power amplifiers,” IEEE Trans. Microw. Theory Tech., vol. 47, no. 8, pp. 1467–1470, Aug. 1999. [13] P. Godoy, D. Perreault, and J. Dawson, “Outphasing energy recovery amplifier with resistance compression for improved efficiency,” IEEE Trans. Microw. Theory Tech., vol. 57, no. 12, pp. 2895–2906, Dec. 2009. [14] F. Casadevall and J. Olmos, “On the behavior of the LINC transmitter,” in Proc. IEEE Veh. Technol. Conf., May 1990, pp. 29–34. [15] W. Gerhard and R. Knöchel, “Prediction of bandwidth requirements for a digitally based WCDMA phase modulated outphasing transmitter,” in Proc. Eur. Wireless Technol. Conf., Oct. 2005, pp. 97–100. [16] F. Raab, “Efficiency of outphasing RF power-amplifier systems,” IEEE Trans. Commun., vol. COM-33, no. 10, pp. 1094–1099, Oct. 1985. [17] A. Birafane and A. Kouki, “Phase-only predistortion for LINC amplifiers with Chireix-outphasing combiners,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 6, pp. 2240–2250, Jun. 2005. [18] S.-S. Myoung, I.-K. Lee, J.-G. Yook, K. Lim, and J. Laskar, “Mismatch detection and compensation method for the LINC system using a closed-form expression,” IEEE Trans. Microw. Theory Tech., vol. 56, no. 12, pp. 3050–3057, Dec. 2008. [19] A. Birafane, M. El-Asmar, A. B. Kouki, M. Helaoui, and F. M. Ghannouchi, “Analyzing LINC systems,” IEEE Microw. Mag., vol. 11, no. 5, pp. 59–71, Aug. 2010. [20] M. Helaoui, S. Boumaiza, and F. Ghannouchi, “On the outphasing power amplifier nonlinearity analysis and correction using digital predistortion technique,” in IEEE Radio Wireless Symp. Dig., Jan. 2008, pp. 751–754. [21] A. Huttunen and R. Kaunisto, “A 20-W Chireix outphasing transmitter for WCDMA base stations,” IEEE Trans. Microw. Theory Tech., vol. 55, no. 12, pp. 2709–2718, Dec. 2007. [22] X. Zhang, L. Larson, P. Asbeck, and P. Nanawa, “Gain/phase imbalance-minimization techniques for LINC transmitters,” IEEE Trans. Microw. Theory Tech., vol. 49, no. 12, pp. 2507–2516, Dec. 2001. [23] I. Hakala, D. Choi, L. Gharavi, N. Kajakine, J. Koskela, and R. Kaunisto, “A 2.14-GHz Chireix outphasing transmitter,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 6, pp. 2129–2138, Jun. 2005.

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[24] S. Moloudi, K. Takinami, M. Youssef, M. Mikhemar, and A. Abidi, “An outphasing power amplifier for a software-defined radio transmitter,” in IEEE Int. Solid-State Circuits Conf. Dig., Feb. 2008, pp. 568–636. [25] X. Zhang, L. Larson, and A. M. Asbeck, Design of Linear RF Outphasing Power Amplifiers. Norwood, MA: Artech House, 2003. [26] J. Yao and S. Long, “Power amplifier selection for LINC applications,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 8, pp. 763–767, Aug. 2006. [27] J. Pedro and S. Maas, “A comparative overview of microwave and wireless power-amplifier behavioral modeling approaches,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 4, pp. 1150–1163, Apr. 2005. [28] D. Schreurs, M. O’Droma, A. Goacher, and M. Gadringer, RF Power Amplifier Behavioral Modeling. Norwood, MA: Artech House, 2009. [29] M. Isaksson, D. Wisell, and D. Rönnow, “A comparative analysis of behavioral models for RF power amplifiers,” IEEE Trans. Microw. Theory Tech., vol. 54, no. 1, pp. 348–359, Jan. 2006. [30] H. Cao, H. Nemati, A. S. Tehrani, T. Eriksson, and C. Fager, “Digital predistortion for high efficiency power amplifier architectures using a dual-input modeling approach,” IEEE Trans. Microw. Theory Tech., to be published. [31] H. Nemati, H. Cao, B. Almgren, T. Eriksson, and C. Fager, “Design of highly efficient load modulation transmitter for wideband cellular applications,” IEEE Trans. Microw. Theory Tech., vol. 58, no. 11, pp. 2820–2828, Nov. 2010. [32] H. Xu, Y. Palaskas, A. Ravi, and K. Soumyanath, “A highly linear 25 dBm outphasing power amplifier in 32 nm CMOS for WLAN application,” in Proc. Eur. Solid-State Circuits Conf., Sep. 2010, pp. 306–309. [33] 3GPP TS 25.104; 3rd Generation Partnership Project; Technical Specification Group Radio Access Network; Base Station (BS) Radio Transmission and Reception (FDD) (Release 11), 3GPP Standard, Rev. V11.0.0, 2011. [34] J. Qureshi, M. Pelk, M. Marchetti, W. Neo, J. Gajadharsing, M. van der Heijden, and L. de Vreede, “A 90-W peak power GaN outphasing amplifier with optimum input signal conditioning,” IEEE Trans. Microw. Theory Tech., vol. 57, no. 8, pp. 1925–1935, Aug. 2009. [35] J. Hur, H. Kim, O. Lee, K.-W. Kim, K. Lim, and F. Bien, “An amplitude and phase mismatches calibration technique for the LINC transmitter with unbalanced phase control,” IEEE Trans. Veh. Technol., vol. 60, no. 9, pp. 4184–4193, Nov. 2011. [36] M. Heath, Scientific Computing: An Introductory Survey. New York: McGraw-Hill, 2002. [37] M. Schetzen, The Volterra and Wiener Theories of Nonlinear Systems. Melbourne, FL: Krieger, 2006. Per N. Landin (S’07) received the M.Sc. degree from the Uppsala University, Uppsala, Sweden, in 2007, the Licentiate in Technology degree from the KTH Royal Institute of Technology, Stockholm, Sweden, in 2009, and is currently working toward the Ph.D. degree at the University of Gävle, Gävle, Sweden, and the KTH Royal Institute of Technology. His main interest is signal-processing techniques for modeling and linearization of nonlinear RF devices. Jonas Fritzin (S’07) received the M.S. degree in electrical engineering from the Chalmers University of Technology, Göteborg, Sweden, in 2004 and the Ph.D. degree from Linköping University, Linköping, Sweden, in 2011. Since January 2012, he has been an RF Application-Specific Integrated Circuit (RF-ASIC) Designer with Ericsson AB, Stockholm, Sweden. His research interests includes CMOS RF PAs and transmitters and predistortion.

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Wendy Van Moer (M’97–SM’07) received the Engineer and Ph.D. degrees in applied sciences from Vrije Universiteit Brussel (VUB), Brussels, Belgium, in 1997 and 2001, respectively. She is currently an Associate professor with the Electrical Measurement Department (ELEC), VUB. Her main research interests are nonlinear measurement and modeling techniques for medical and highfrequency applications. Dr. Van Moer has been an associate editor for the IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT since 2007, and in 2010, she became an associate editor for the IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES. She is a member of the Administrative Committee (AdCom) of the IEEE Instrumentation and Measurement Society. She was the recipient of the 2006 Outstanding Young Engineer Award of the IEEE Instrumentation and Measurement Society. Magnus Isaksson (S’98–M’07) received the M.Sc. degree in microwave engineering from the University of Gävle, Gävle, Sweden, in 2000, the Licentiate degree from Uppsala University, Uppsala, Sweden, in 2006, and the Ph.D. degree from the Royal Institute of Technology, Stockholm, Sweden, in 2007. From 1989 to 1999, he was with Televerket, Gävle, Sweden, where he was involved with communication products. He is a Teacher of signal processing for telecommunications and is currently the Head of the Department of Electronics, Mathematics, and Natural Sciences, University of Gävle, Gävle, Sweden. He is also currently Head of research within the fields of electronics, mathematics, and natural sciences with the University of Gävle. He has authored or coauthored many published peer-review journal papers, books, and conference proceedings. His main interests are signal-processing algorithms for RF measurements and modeling of nonlinear microwave systems. Atila Alvandpour (M’99–SM’04) received the M.S. and Ph.D. degrees from Linköping University, Linköping, Sweden, in 1995 and 1999, respectively. From 1999 to 2003, he was a Senior Research Scientist with the Circuit Research Laboratory, Intel Corporation. In 2003, he joined the Department of Electrical Engineering, Linköping University, as a Professor of very large scale integration (VLSI) design. Since 2004, he has been the Head of the Electronic Devices Division. He is also the Coordinator of the Linköping Center for Electronics and Embedded Systems (LINCE). He has authored or coauthored approximately 100 papers in international journals and conferences. He holds 24 U.S. patents. His research interests include various issues in design of integrated circuits and systems in advanced nanoscale technologies with a special focus on efficient analog-to-digital data converters, wireless transceiver front-ends, sensor interface electronics, high-speed signaling, on-chip clock generators and synthesizers, low-power/high-performance digital circuits and memories, and chip design techniques. Prof. Alvandpour has served on many Technical Program Committees of IEEE and other international conferences, including the IEEE International Solid-State Circuits Conference (ISSCC) and the European Solid-State Circuits Conference (ESSCIRC). He has also been a guest editor for the IEEE JOURNAL OF SOLID-STATE CIRCUITS.

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Investigation of Wideband Load Transformation Networks for Class-E Switching-Mode Power Amplifiers Muh-Dey Wei, Student Member, IEEE, Danish Kalim, Student Member, IEEE, Denis Erguvan, Sheng-Fuh Chang, Senior Member, IEEE, and Renato Negra, Member, IEEE

Abstract—In this paper, single-ended and differential class-E load transformation networks (LTNs) for wideband operation are investigated. For this purpose, a differential third parallel-tuned tank LTN and a parallel-circuit load LTN without suppressing tanks are proposed to fulfill the class-E wideband condition. The differential parallel-circuit load (DPCL), which considers the finite RF chokes, has higher output resistance, and because of the differential structure, which ensures an open circuit at even harmonic frequencies, it is able to cover a wide frequency range. Consequently, the DPCL is well suited for highly integrated monolithic designs, as well as wideband application. Based on this analysis, a wideband class-E switching-mode power amplifier in CMOS 90 nm using the DPCL is designed. By deliberately combining the LTN with an on-chip balun, a compact size of 1.2 mm is achieved. The circuit performance dependency on bond-wire length variation is analyzed and discussed. Measured results show a peak output power of 28.7 dBm, power-added efficiency (PAE) of 48.0%, and drain efficiency of 55.0% at 2.3 GHz. From 1.7 to 2.7 GHz, PAE is higher than 42% and output power is above 25 dBm. Index Terms—Class E, load transmission network (LTN), power amplifier (PA), switching mode, wideband.

I. INTRODUCTION

F

OR next-generation wireless mobile device characteristics, multistandard capability for high data-rate applications is demanded. These requirements are typically associated with high power consumption and high costs of such mobile terminals. Therefore, designing power-efficient circuits to enhance Manuscript received October 01, 2011; revised February 24, 2012; accepted March 05, 2012. Date of publication April 26, 2012; date of current version May 25, 2012. This work was supported by the Ultra Highspeed Mobile Information and Communication (UMIC) Research Centre, RWTH Aachen University, and the National Science Council of Taiwan. M.-D. Wei is with Mixed-Signal CMOS Circuits, Ultra Highspeed Mobile Information and Communication (UMIC) Research Centre, RWTH Aachen University, Aachen 52056, Germany, and also with the Department of Electrical Engineering, National Chung Cheng University, Chiayiv 62102, Taiwan (e-mail: [email protected]). D. Kalim, and R. Negra are with the Mixed-Signal CMOS Circuits, Ultra Highspeed Mobile Information and Communication (UMIC) Research Centre, RWTH Aachen University, Aachen 52056, Germany (e-mail: [email protected]). D. Erguvan is with Deutsche Bahn AG, 10785 Berlin, Germany. S.-F. Chang is with the Department of Electrical Engineering, the Department of Communications Engineering, and the Center for Telecommunication Research, National Chung Cheng University, Chiayi 62102, Taiwan (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2012.2191304

Fig. 1. General block diagram of an SMPA.

battery lifetime at an affordable price has become an important research topic over the last decade. The most power-hungry building block in a wireless device RF front-end is typically the power amplifier (PA). Hence, improving dc-to-RF efficiency of a PA has a significant impact on battery lifetime. PAs can be broadly categorized as linear and switching-mode power amplifiers (SMPAs). The later ones have already been widely used in audio applications over decades. Today, SMPAs for microwave/RF are getting more and more attention due to the fact that they provide high energy efficiency. Theoretically, an SMPA is able to reach 100% efficiency because the transistor operates as an on/off switch (SW), as depicted in Fig. 1. This implies that high output voltage across and output current through the device do not exist simultaneously, which results in little dissipated power in the active device, and hence, in high dc-to-RF efficiency. However, in practical implementations, the achievable efficiency depends mainly on the losses of the active and passive devices and on how many higher harmonic frequency components can be properly terminated [1] maintaining a reasonable circuit complexity. The feasibility of different operation modes of SMPAs, such as current-mode class-D [2], class-E [3], class-F [4], [5], and class-F [6], have already been successfully demonstrated at microwave frequencies. Each of these type has different output waveforms, and hence, particular requirements on the load transformation network (LTN), especially in regard to harmonic frequency termination. In order to prevent power dissipation at higher harmonic frequencies, which originate from the nonlinear operation of the active device, these signal components have to be terminated either in a low or a very high impedance. This fact restricts the operational bandwidth of SMPAs to less than one octave. Several approaches have been proposed to overcome this limitation. Multiband multiharmonic load networks [7]–[9], and particularly those based on transmission lines and multiple

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Fig. 2. Schematic of a class-E SMPA using a series-tuned tank LTN.

Fig. 3. Single-ended test bench used to compare the performances of different LTNs.

tuned tanks, are not well suited for application in wireless user terminals. The huge die area requirement of these devices at wireless communication frequencies would make a PA based on these approaches extremely expensive. Moreover, the substrate loss and costs of digital centric CMOS nodes require the LTN to be either off-chip for best performance, or in the case of high integration, to be very area efficient and with low excessive loss. A tunable/reconfigurable approach, such as in [10], is challenging to realize in standard CMOS due to the high-voltage stress on the SWs arising at high output power levels. Special design techniques or even process steps are needed to circumvent these challenges. The most suitable topology for covering multiple wireless communication bands with one SMPA appears to be a wideband LTN. Such circuits are of low-to-moderate complexity and can be fully integrated on-chip within a reasonable amount of die area. Consequently, this paper studies wideband class-E LTN, with special emphasis on differential topologies due to their benefits in RF integrated circuit (RFIC) technology with the aim to design a highly efficient amplifier, which can cover as many wireless communication bands as possible without necessitating any switching or tunable components. Based on simulation results using various LTN, a wideband class-E SMPA in CMOS 90-nm technology was designed and implemented. By merging the on-chip balun with the differential parallel coupled load LTN allowed the full integration of an amplifier, which is able to cover the 2.5-GHz long-term evolution (LTE) band-7, the 2.4-GHz industrial–scientific–medical (ISM), and the 1.8-GHz wireless application bands. The circuit provides more than 25 dBm of output power with efficiency greater than 42% over the entire frequency range from 1.7 to 2.7 GHz. II. INVESTIGATION OF SINGLE-ENDED WIDEBAND OPERATION The class-E impedance conditions for zero-voltage switching (ZVS) and zero-derivative switching (ZDS) have to be provided by the LTN. A series-tuned tank, shown in Fig. 2, has been proposed in [3] where an ideal RF choke (RFC), which presents an infinite impedance at all frequency but dc, is assumed. From the derivation of the differential equations, the required impedance is obtained as [11] at at

(1)

where is the optimum load resistance. For a desired output power, , , and , the required total switching capacitance can be calculated by [3] (2) (3) is the supply voltage, is the knee voltage of where the active device operated as the SW, and is the fundamental frequency of operation. The parasitic capacitance of the SW [e.g., of a field-effect transistor (FET)] is included in . Three different load coupling networks, the series-tuned tank load, parallel-tuned tank load, and parallel-circuit load (PCL), all suitable for providing the ZVS and the ZDS conditions for nominal class-E operation, are analyzed in simulations with regard to their broadband performance. Fig. 3 shows the test bench for all following single-ended simulations. An SW, with the ON resistance, , of 0.01 , the OFF resistance, , of 1 M and V, is used. The input switching signal is a square waveform with a duty cycle of 50%. The inductance of the RFC is chosen to be 1 mH. No separate dc block is necessary in the series-tuned tank LTNs, as the series-tuned tank already provides inherently this function. A. Series-Tuned Tank The classical network employing a series-tuned tank is shown in Fig. 2. The series tank, consisting of and , is inserted between the SW and the load to suppress higher harmonic content in the load. Besides that, the tank is tuned slightly below in order to provide the correct inductive load angle at for high efficient class-E operation. The loaded quality factor, , of the output network is defined as (4) The theoretical values of a series-tuned tank LTN can be calculated from [3] (5) (6)

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TABLE I VALUES OF THE SINGLE-ENDED LTNs FOR OUTPUT POWER OF 1 W AT 2.3 GHz

AN

Fig. 5. Class-E SMPA using parallel-tuned tank LTN.

be sized to provide the correct class-E conditions at the fundamental frequency, . is employed to transform the actual output resistance, , which typically is 50 , to the optimum load resistance, , required for the targeted output power. This parallel-tuned tank LTN suppresses the second harmonic over a wide frequency range. Therefore, a circuit based on this LTN will provide a wider bandwidth with less inductance than the classical approach. The value for the circuit element in Fig. 5 can be calculated with the expressions derived in [13] (7) (8) (9)

Fig. 4. Broadband performance of the series-tuned tank LTN as function of the . (a) Output power. (b) DE. design parameter

The operational bandwidth of the amplifier depends on the value of , which is a design parameter and can be selected according to the desired circuit performance. A lower value leads to a wider bandwidth design, both in terms of and efficiency, . Once is selected, and can be calculated using (5) and (6). The components values for the series-tuned tank as a function of different values for 1 W of output power and a supply voltage of 2.5 V are tabulated in Table I. The simulation results of analyzing the operational bandwidth of these circuits plotted in Fig. 4 confirm the data given in [12]. B. Parallel-Tuned Tank An alternative LTN using a parallel tank tuned to the second harmonic and connected in series to the load has been proposed in [13] to obtain wider bandwidths than with the series-tuned tank. The parallel-tuned tank LTN is illustrated in Fig. 5. The parallel tank, composed of and , is designed to provide a high impedance at the second harmonic, , since it affects efficiency more than the higher harmonics [1]. The parallel tank becomes inductive below the resonance frequency and can, hence,

The component values for 1 W of output power at 2.3 GHz are compared in Table I with the ones of the conventional approach. Since resonates at the second harmonic, the size of is smaller than in the series-tuned tank LTN. A reduced inductance value is definitely an important advantage in monolithic integrated designs as it leads to more compact designs, and extends the applicable frequency range of this LTN because of the higher self-resonance frequency of a smaller inductor. The simulated results are compared with different LTNs in Section II-C. C. PCL In some circumstances, such as in monolithic integrated circuits, it is difficult to practically approximate an ideal RFC, i.e., to provide a suitably high RF impedance. The RFC in monolithic chips can be realized with either on-chip spiral inductors or bond wires. Either one is not convenient as an ideal current source [14], [15]. This implies that the effects of an unideal RFC on the circuit behavior have to be considered. In addition, if the output capacitance, , of the available device is too large to obtain nominal class-E operation at a given frequency, using a finite dc feed inductance is able to resonate out part of this capacitance, so that the device can be operated in nominal class-E mode at higher frequencies. The LTN with finite dc feed inductance, , instead of an ideal RFC is illustrated in Fig. 6. Under the constraint of a finite dc feed inductance, the resonant frequency , of , and

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Fig. 6. Class-E SMPA using PCL LTN.

determines the mode of operation, and hence, the performances of the circuit. Three specific modes are defined in the literature [16]: subharmonic , even-harmonic , and PCL mode . In the PCL mode, the class-E conditions (i.e., ZVS and ZDS) can be fulfilled by using only the resonator. The tank provides the correct load angle at the fundamental frequency, and thus, nominal class-E output waveforms can be obtained. In order to filter out higher harmonics, a series resonator tuned to is added. In the PCL operation mode, the output load appears in parallel with the SW. From in (1), only the real part remains at . The optimum impedance can now be written as at at

Fig. 7. Comparisons with class-E SMPAs using the LTN of classical seriestuned tank, STT (line), parallel-tuned tank, PTT (dot), and parallel-circuit load, PCL (dash). (a) Output power. (b) DE.

TABLE II BANDWIDTH OF OUTPUT POWER AND DE

(10)

Compared with the typical class-E condition in (1), there is no imaginary part because of the absence of the imaginary impedance in this mode. For a given output power, the resulting of this PCL mode is significantly larger than in the conventional LTNs, which allows attaining wide bandwidths. The values for , , and for the PCL LTN can be calculated from the expressions given in [17]

bandwidth performance is given in Table II. According to this data, the PCL offers the largest bandwidth, which makes it the topology of choice for flexible multiband applications.

(11) (12) (13) This is 2.42 times larger than the one in (2). The component values for the analyzed single-ended LTNs are summarized in Table I. Three class-E SMPAs with different LTNs, series-tuned tank, parallel-tuned tank, and PCL, under the same output power of 1 W at GHz, have been simulated and their performance compared. Fig. 7 shows simulated output power and drain efficiency (DE). The 1-dB-output power bandwidth is 33.2%, 26.1%, and 50.2% for the series-tuned tank, paralleltuned tank, and PCL, respectively, as shown in Fig. 7(a). Considering DE plotted in Fig. 7(b), the 80% DE bandwidths are 29.2%, 25.2%, and 58.6% for the series-tuned tank, parallel-tuned tank, and PCL, respectively. The comparison of the

III. INVESTIGATION OF DIFFERENTIAL WIDEBAND OPERATION Differential circuit topologies are often preferred over single-ended ones due to their benefits in regard to noise and coupling robustness. Moreover, the availability of complementary devices in silicon technologies favors differential topology for system-on-chip (SoC) solutions. Three differential class-E LTNs, differential series-tuned tank, differential parallel-tuned tank, and differential parallel-circuit load (DPCL) are therefore addressed in the following. The differential test bench illustrated in Fig. 8 differs only slightly from the single-ended one in Fig. 3. Here, differential input signals drive the SWs and the output signals are combined through an ideal balun. A. Differential Series-Tuned Tank The differential LTN with series-tuned tank is shown in Fig. 9. Each of the series tanks, and , provides the correct impedance for each path. The design concepts

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Fig. 10. Differential LTN with parallel-tuned tank.

Fig. 8. Differential test bench used to compare the performances of different LTNs.

TABLE III VALUES OF THE DIFFERENTIAL PARALLEL-TUNED TANK LTN

Fig. 9. Differential LTN with series-tuned tank.

and values of the LTN are the same as for the single-ended series-tuned tank. B. Differential Parallel-Tuned Tank The differential LTN with a parallel-tuned tank is shown in Fig. 10. Due to the differential topology, ideally all even harmonics are inherently terminated with an open circuit. As a consequence, the parallel-tuned tank is tuned to instead of , as in the single-ended case. The component values for , , and can be calculated as follows: (14) (15) (16) and are the optimum and actual output resistance, where respectively. Table III summarizes the design parameters for a 1-W 2.3-GHz class-E SMPA using the differential parallel-tuned tank LTN. Since resonates at , either inductance

Fig. 11. DPCL with series-tuned tanks.

or capacitance becomes small. As can be seen in Table III, for the given example is only 0.432 nH. This requires a careful consideration of process tolerances in a practical circuit implementation. C. DPCL The differential LTN with PCL is shown in Fig. 11. The finite , is considered in the LTN. and RFC, provide the class-E switching conditions. The tanks, and , are tune to to provide minimum attenuation of the wanted signal at this frequency, while suppressing higher harmonic content in the load. The value of each element of the LTN is the same as for the single-ended PCL LTN. Three class-E SMPAs with differential series-tuned tank-, parallel-tuned tank-, and PCL-LTN have been designed and simulated to provide an output power of 1 W at 2.3 GHz. In simulations, the values of the differential series-tuned tank LTN and the PCL LTN are the same as the single-ended series-tuned tank and PCL LTN listed in Table I. However, the values for the differential parallel-tuned tank LTN are different in the differential case and are therefore summarized in Table III.

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Fig. 12. Comparisons with differential class-E SMPAs using the LTN of seriestuned tank, DSTT (line), parallel-tuned tank, DPTT (dot), and parallel-circuit load, DPCL (dash). (a) Output power. (b) DE.

Fig. 13. DPCL without series-tuned tanks.

Simulated output power and DE of the three amplifiers are plotted in Fig. 12. The bandwidth performances of the differential LTNs are comparable to the single-ended versions. Also in the differential design, the DPCL provides the largest bandwidth. From Fig. 12(b), it can be seen that from 1.75 to 3.24 GHz, i.e., over a relative bandwidth of 60%, DE remains above 80% when employing the DPCL LTN. Due to the differential topology, all even harmonics are open-circuited intrinsically, whereas the odd harmonic frequency components still remain in the output load. If sufficient third harmonic suppression is provided by the remaining system components, the tanks and in Fig. 11 can be eliminated as shown in Fig. 13. The simulated results of the DPCL with and without tanks are compared in Fig. 14. First we take a look at the output power shown in Fig. 14(a). The DPCL without tanks provides output power greater than 30 dBm from 1.8 to 3.4 GHz. This is because bandwidth limitations caused by tanks do not prevail in this LTN.

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Fig. 14. Comparisons with the DPCL and LTN with (line) and without (dot) series-tuned tanks. (a) Output power. (b) DE.

Fig. 15. Output spectrum of DPCL with (circle) tanks and without (triangle) tanks at the frequency of 3.0 GHz.

On the other hand, from 2.0 to 3.8 GHz, DE shown in Fig. 14(b) is slightly decreased because all odd harmonics, e.g., , still exist in the load due to the absence of tanks. Fig. 15 shows the output spectra of both DPCL LTNs at 3.0 GHz. In this simulation, the power difference between and is 42.3 dBc in the DPCL with tanks and 19.2 dBc in the DPCL without tanks. As expected, the power of odd harmonics in the DPCL without tanks is higher than in the one with tanks. Moreover, the DPCL without tanks provides high efficiency over a wide frequency range because output power is high over a wide band. IV. CIRCUIT DESIGN The DPCL without tanks is chosen because it has several advantages for monolithic designs such as easy implementation, compact size, as well as the wideband performance. The schematic of the wideband CMOS class-E SMPA is shown in Fig. 16. The SMPA consists of three parts: an input matching network (IMN), transistors operated as SWs, and a DPCL LTN

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TABLE IV DIMENSION OF THE CMOS SMPA

inductance and capacitance of the on-chip balun illustrated in Fig. 17(b) can be calculated by (17) (18) Fig. 16. Schematic of the proposed wideband class-E SMPA.

(19) Capacitance and inductance can be absorbed into the DPCL LTN since and , as well as and , are connected in parallel. Hence, , , , and in Fig. 16 are given by (20) (21) (22)

Fig. 17. Schematics of a lattice-type balun.

combined with an on-chip differential-to-single-ended (D-to-S) balun. The IMN, composed of , , , and , is centered at 2.3 GHz. The DPCL LTN consists of , , , and comprise both drain-to-source capacitances, and , the value of which depend on the dimensions of the transistors. As mentioned earlier, the RFCs, and , can be realized with either spiral inductors or bond wires. In the presented design, the output balun is realized on-chip in order to increase the degree of integration, and thus, reducing the final assembly costs. A. Merging of On-Chip Balun and LTN Two representations of a single-order lattice-type balun [18] are drawn in Fig. 17(a) and (b), where (a) and (b) are electrically identical. In the following, we refer to the representation of the lattice balun in Fig. 17(b), as it is easier to explain the design of the output network than with the schematic in Fig. 17(a). The single-ended output impedance, , is generally 50 in wireless communication systems. Once and —e.g., the system reference impedance—are determined, , together with and can be calculated to provide a 90 phase shift at the input terminals. The

(23) and are optimized using (12) and (13), respecwhere tively. The LTN is not only able to provide the required class-E switching conditions, but also to perform the D-to-S on-chip balun. In this way, valuable chip area can be saved. can be chosen to be 50 to obtain wide bandwidth. Due to the DPCL LTN, the calculated differential output power is 28.3 dBm with an . By reducing , one can increase output power. V. IMPLEMENTATION The starting values for and are calculated to be 1.01 nH and 2.37 pF, respectively, for an output power of 29.3 dBm with chosen to obtain higher output power. The output power calculated by (11) has to be increased by 3 dB because of the differential topology. The initial values were fine tuned in simulation using the commercial computer-aided-design tool, Cadence Spectre, and BSIM transistor models provided by the foundry. A. Implementation in CMOS Process The proposed SMPA was implemented in a CMOS 90-nm process with a low-power (LP) option. This enables the integration of other transceiver building blocks onto a single chip. The

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Fig. 19. Measurement setup.

Fig. 20. Microphotograph of the realized SMPA in a 90-nm CMOS technology.

Fig. 18. Simulated PAE (circle) and output power (triangle). (a) Sweeping . (b) Difference between and (fixed bond-wire inductance and changed ). (c) Difference (fixed and changed ).

LP option provides transistors with either 1.2 or 2.5 V of nominal supply voltage. In order to obtain the highest possible for best wideband performance, the 2.5-V device was chosen for this design. The transistors, and in Fig. 16, have identical dimensions of m m and are biased at mV, i.e., below threshold. Both theoretical and actual implemented values of the circuit components are summarized in Table IV. It is necessary to ensure that the peak output voltage and current do not exceed the breakdown voltage of this LP process devices and current handling capabilities of the interconnects under any circumstances.

Fig. 21. Output power (circle) and dc power consumption (triangle) versus input power at the center frequency of 2.3 GHz. (measurement: solid black; simulation: dashed white).

The peak voltage and current with the finite dc feed inductance are derived in [17] and are written as (24) (25)

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Fig. 22. PAE (circle) and DE (triangle) versus input power at the center frequency of 2.3 GHz (measurement: solid black; simulation: dashed white).

Fig. 24. Measured output voltage (circle) and PAE (triangle) versus supply for an input drive signal of 17 dBm. voltage

Fig. 25. Reliability testing for 12 h at an input power of 17 dBm. Fig. 23. Measured output power (circle) and PAE (triangle) versus operation frequency at an input power of 17 dBm (measurement: solid black; simulation: dashed white).

Maximum current handling capabilities of the interconnects have to be carefully considered during layout to avoid reliability issues. The dc current density of the available ultra-thick metal (UTM), consisting of 33-kÅ-thick Cu, is approximately 25 mA for a linewidth of 1 m. Although a wider track would be able to handle more current, it not only increases parasitic capacitance to ground of the interconnect, but also affects chip area consumption to some extend. Moreover, in advanced CMOS processes, it is mandatory to strictly follow the design and antenna rules check (ARC), to avoid gate–oxide damage during fabricating. This results in limitations regarding the maximum usable track width, as well as maximum metal density. The capacitors and were realized by metal–insulator–metal (MIM) capacitors, whereas the inductances , , and were implemented as on-chip spiral inductors using the thick UTM. The SMPA was implemented in a multiproject chip. Consequently, a favorable placement of the SMPA in regard to bond-wire length and symmetry was not possible. The minimum length of the bond wire due to the chip layout and package is estimated to be roughly 4 mm. Both inductances and were realized by using two 25- m-thick gold bond

wires in parallel to enhance power handling. The resulting effective inductance is therefore estimated to about 2 nH for each inductor. B. Variation of Bond Wires In Fig. 16, the inductors, and , perform parts of the LTN and the on-chip balun. Each of and is realized by a bond wire, which can be modeled by an inductor in series with an internal resistor, where a single bond wire of 1-mm length is assumed to provide approximately 1 nH of inductance. Since it is difficult to precisely control the lengths of bond wires produced by a manual bonder, it is important to analyze the effects of bond-wire-length variations on circuit performance. Only some variations are considered here. The first case is that both bond wires, and , change equally in physical length. Fig. 18(a) shows the simulated power-added efficiency (PAE) and output power when the inductance of the corresponding bond wire is tuned from 0.01 to 4 nH. However, because and are located at opposite sides of the chip, under real circumstances their inductances will always differ from each other. Therefore, it is also necessary to consider nonidentical inductances in the analysis: 20% difference between and is simulated and plotted in Fig. 18(b) and (c) while keeping either or constant.

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TABLE V PERFORMANCE COMPARISON OF THE PRESENTED DESIGN WITH OTHER CMOS SMPAs

is In Fig. 18(b), maximum PAE is as high as 63.2% when greater by 6% than , which is expected. In fact, the optimum values for and calculated by (22) and (23) are different because the balun is merged together with the LTN. Maximum PAE occurs if, and only if, the LTN provides nominal class-E condition to both transistors simultaneously. However, the analysis shows that the chip is able to maintain suitable performance in spite of unavoidable bond-wire tolerances. PAE is better than 54% even for a difference as large as 20%, which confirms the insensitivity of the selected approach. VI. SIMULATION AND MEASUREMENT A. Measurement Setup The chip was measured by a partial on-wafer manner where SÜSS differential ground–signal–signal–ground (GSSG) and single-ended ground–signal–ground (GSG) probes were used for RF input and output ports, respectively. The specified loss of these probe tips of around 0.3 dB in the frequency range of interest was de-embedded from the data measured with a spectrum analyzer. The chip was glued on a printed circuit board (PCB) using a silver conductive adhesive. The PCB is a Rogers RO4003 board with a substrate and copper thickness of 0.81 mm and 35 m, respectively. Fig. 19 briefly illustrates the measurement setup. To generate a differential input signals with suitable input power, a Mini-Circuits preamplifier and a 180 hybrid balun were added. DC biasing was done through the bond wires connected to a dedicated microstrip structure. A good performance of the circuit requires a low-impedance RF ground at the injection point on the measurement board. This was achieved by means of a quarter-wavelength open-circuited stub. In order to cover a larger bandwidth, decoupling capacitors were added in parallel to the open stubs at the node on the PCB. Except these decoupling components, the circuit does not require additional external components to operate. The chip was placed on a grounded metal-patch for heat-sinking purpose. The microphotograph of the CMOS SMPA is shown in Fig. 20. The entire chip, including an on-chip balun and all I/O pads, occupies an area of 1.2 mm 1.0 mm.

B. Simulation and Measurement Results As mentioned earlier, a Cadence Spectre simulator was used in the design and the device models were provided by the foundry Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu, Taiwan. The following data was produced by using the typical parameter set for the models. Note that a and bond wires in the length of 4 mm is assumed for following simulations. Output power and dc power consumption versus input power at the center frequency of 2.3 GHz are shown in Fig. 21. The saturated output power delivered into a 50- load is 28.7 dBm. PAE and DE, , are illustrated in Fig. 22. Measured peak % and % are achieved at a drive level of 17 dBm. Fig. 23 shows the wideband performance of the SMPA. From 1.7 to 2.7 GHz, measured peak PAE is greater than 42% and output power is greater than 25 dBm up to 2.8 GHz. The chip has a bandwidth, defined as output power greater than 25 dBm, of 48.9%. C. Linearity Fig. 24 shows the measured relationship between applied supply voltage and output voltage on a 50- load and PAE of the fabricated wideband CMOS SMPA. As can be seen, the PA shows a quasilinear behavior between and output voltage, which makes the SMPA suitable for the use in polar transmitters [27], [28]. Over an output power dynamic range of almost 8.6 dBm, i.e., for supply voltages greater than 0.7 V, measured PAE is larger than 20%. D. Reliability The SMPA was operated under optimum PAE conditions over an extended period to test the reliability of the chip and the design. For this purpose, output power and PAE were observed in regular intervals, with an a 17-dBm strong 2.3-GHz continuous wave (CW) signal fed to the input of the circuit. These parameter correspond to the condition under which the SMPA provides peak PAE. The data is plotted in Fig. 25. During a measurement period of 12 h, the variations of peak output power and peak PAE were less than 0.2 dBm and 1.6% points, respectively. One reason for these variations is that the environmental temperature could not be kept constant during this period of time. Nevertheless, the small observed deviations confirm that

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the bond wires. This was not possible with the current version due to the placement of the circuit on the chip.

TABLE VI BANDWIDTH COMPARISON OF THE DESIGNED WIDEBAND AMPLIFIER WITH OTHER CMOS SMPAs

ACKNOWLEDGMENT The authors acknowledge and thank the research cluster “Ultra High Speed Information and Communication” (UMIC), RWTH Aachen University, Aachen, Germany and the National Science Council (NSC), Taiwan for their support of this work. REFERENCES

the design of the PA is reliable: the layout is well considered and every metal interconnection is appropriate to continuously handle high power. The measured performance of the SMPA is summarized in Tables V and VI, and compared with other published CMOS SMPA designs. The following figure-of-merits (FOMs) are used to compare the performance of the designed chip with state-ofthe-art CMOS SMPAs: Freq Freq chip size Freq chip size

Hz Hz mm Hz mm

(26) (27) (28)

where BW is the PAE bandwidth. Due to its high efficiency, compact size, and wide bandwidth, the presented circuit has an outstanding of 105.1, of 87.6, and of 22.25. In addition, the chip provides a wide available operational bandwidth and can therefore cover several wireless communication bands. VII. CONCLUSION The wideband performances of single-ended and differential class-E LTNs have been investigated and two differential LTNs, i.e., differential parallel-tuned tank and DPCL, have been proposed in the paper. The DPCL LTN without tanks is able to cover a wide frequency range with good performance. Therefore, a wide bandwidth SMPA in 90-nm LP CMOS technology is implemented and measured. This enables technically the integration of the PA together with the rest of the transceiver on the same chip. By combining the LTN with an on-chip balun, the complete design of the implemented class-E SMPA is layed out in an area of 1.2 mm . The RFCs were realized by exploiting the inductance of bond wires. Measured peak PAE and DE are 48.0% and 55.0%, respectively, while the obtained peak output power of 28.7 dBm is appropriate for many wireless standards. Measurements also demonstrate the wideband performances of this CMOS SMPA. From 1.7 to 2.7 GHz, peak PAE and output power are greater than 42% and 25 dBm, respectively. Since simulations and measurements agree well, the performance of the wideband CMOS SMPA could be improved further by optimizing the lengths of

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[22] H.-Y. Liao, M.-W. Pan, and H.-K. Chiou, “Fully-integrated CMOS class-E power amplifier using broadband and low-loss 1:4 transmission-line transformer,” Electron. Lett., vol. 46, no. 22, pp. 1490–1491, Oct. 2010. [23] A. Mazzanti, L. Larcher, R. Brama, and F. Svelto, “Analysis of reliability and power efficiency in cascode class-E PAs,” IEEE J. Solid-State Circuits, vol. 41, no. 5, pp. 1222–1229, May 2006. [24] O. Lee, K. S. Yang, K. H. An, Y. Kim, H. Kim, J. J. Chang, W. Woo, C.-H. Lee, and J. Laskar, “A 1.8-GHz 2-watt fully integrated CMOS push-pull parallel-combined power amplifier design,” in Proc. IEEE Radio Freq. Integr. Circuits Symp., Jun. 2007, pp. 435–438. [25] R. Brama, L. Larcher, A. Mazzanti, and F. Svelto, “A 30.5 dBm 48% PAE CMOS class-E PA with integrated balun for RF applications,” IEEE J. Solid-State Circuits, vol. 43, no. 8, pp. 1755–1762, Aug. 2008. [26] P. Reynaert and M. S. J. Steyaert, “A 2.45-GHz 0.13- m CMOS PA with parallel amplification,” IEEE J. Solid-State Circuits, vol. 42, no. 3, pp. 551–562, Mar. 2007. [27] E. McCune, “Multi-mode and multi-band polar transmitter for GSM, NADC, and EDGE,” in IEEE Wireless Commun. Network., Mar. 2003, vol. 2, pp. 812–815. [28] D. Chowdhury, L. Ye, E. Alon, and A. Niknejad, “An efficient mixedsignal 2.4-GHz polar power amplifier in 65-nm CMOS technology,” IEEE J. Solid-State Circuits, vol. 46, no. 8, pp. 1796–1809, Aug. 2011.

Muh-Dey Wei (S’06) was born in Kaohsiung, Taiwan. He received the M.Sc. degree in electrical engineering from National Chung Cheng University, Chiayi, Taiwan, in 2006, and is currently working toward the Ph.D. degree at National Chung Cheng University and at RWTH Aachen University, Aachen, Germany. He is currently with the Mixed Signal CMOS Circuits Group, RWTH Aachen University. His current research interests are multiband high-efficiency transmitters, CMOS LP low-phase-noise voltage-controlled oscillators (VCOs) and high-efficient SMPAs. Mr. Wei is the recipient of a Deutscher Akademischer Austauschdienst/National Science Council (DAAD/NSC) Scholarship.

Danish Kalim (S’09) received the B.E. degree in electronics engineering from the NED University of Engineering and Technology, Karachi, Pakistan, in 2002, the M.Sc. degree in communications engineering from RWTH Aachen University, Aachen, Germany, in 2008, and is currently working toward the Ph.D. degree at RWTH Aachen University. From 2003 to 2005 he was a Design Engineer with Power Research, Karachi, Pakistan, where he was involved with global positioning system (GPS)-based navigation systems. His research interests are multiband and broadband SMPAs, asymmetric Doherty PAs, and advanced RF transmitter architectures.

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Denis Erguvan was born in Köln, Germany, in 1977. He received the Dipl.-Ing. degree in electrical engineering from RWTH Aachen University, Aachen, Germany. He then joined the Mixed-Signal CMOS Circuits Research Group, RWTH-Aachen University, where he was involved with the design of broadband PAs. He is currently a District Manager with Deutsche Bahn AG, Berlin, Germany.

Sheng-Fuh Chang (S’83–M’92–SM’07) received the B.S. and M.S. degrees in communications engineering from National Chiao-Tung University, Hsinchu, Taiwan, in 1982 and 1984, respectively, and the Ph.D. degree in electrical engineering from the University of Wisconsin–Madison, in 1991. He has been involved with high-power microwave and millimeter-wave sources, such as free-electron lasers and Cerenkov masers, with the Center for Plasma Theory and Computation, University of Wisconsin–Madison. In 1992, he joined the Hyton -band satellite Technology Corporation, with responsibility for - and low-noise down-converters and MMDS transceivers. In 1994, he joined the Department of Electrical Engineering, National Chung Cheng University, Taiwan. Currently, he is a full professor with the Department of Electrical Engineering, Department of Communications Engineering. He is also the director of the Center for Telecommunication Research, National Chung Cheng University, Chiayi, Taiwan. His research interests include microwave and millimeter-wave integrated circuits (ICs), multifunctional RF transceivers, microwave vital signal measurement, and wireless indoor positioning. Prof. Chang is a member of Phi Tau Phi and Sigma Xi.

Renato Negra (S’06–M’06) received the M.Sc. degree in telematics from the Graz University of Technology, Graz, Austria, in 1999, and the Ph.D. degree in electrical engineering from ETH Zurich, Zurich, Switzerland, in 2006. His doctoral research was focused on power-efficient linear amplification of wireless communication signals. From 1998 to 2000, he was with Alcatel Space Norway AS (now NorSpace AS), Horten, Norway, where he was involved in the design and characterization of space-qualified RF equipment. In April 2000, he joined the Laboratory for Electromagnetic Fields and Microwave Electronics, ETH Zurich. From 2006 to May 2008, he was a Post-Doctoral Fellow with the iRadio Lab, University of Calgary, Calgary, AB, Canada, where he was involved with SMPAs and advanced wireless transmitter architectures. Since June 2008, he has been an Assistant Professor with RWTH Aachen University, Aachen, Germany, where he heads the Mixed-Signal CMOS Circuits Group, Ultra high-speed Mobile Information and Communication (UMIC) Research Centre. His research interests are highly efficient PAs, advance transmitter architectures, software-defined and reconfigurable radios, and mixed-signal as well as millimeter-wave circuits.

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IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 60, NO. 6, JUNE 2012

The Continuous Inverse Class-F Mode With Resistive Second-Harmonic Impedance Vincenzo Carrubba, Member, IEEE, Muhammad Akmal, Rüdiger Quay, Senior Member, IEEE, Jonathan Lees, Johannes Benedikt, Steve C. Cripps, Fellow, IEEE, and Paul J. Tasker, Senior Member, IEEE

Abstract—In this paper, an extended version of the continmode power amplifier (PA) design approach is uous classpresented. A new formulation describing the current waveform in terms of just two additional parameters, while maintaining a constant half-wave rectified sinusoidal voltage waveform, allows multiple solutions of fundamental and second-harmonic impedances that provide optimum performance to be computed. By varying only the imaginary parts of fundamental and second-harmonic impedances, it is shown that output performance in terms of power and efficiency is maintained constant and equal to that achievable from the standard class. Indeed, when presenting resistive second-harmonic impedances, it will be demonstrated that the fundamental load can be adjusted to maintain satisfactory output performances greater than a certain predetermined target value. The measurements, conducted on a GaAs pHEMT device at 1 GHz, show a good agreement with the theoretical analysis, revealing drain efficiencies greater than 70% for a very large range of load solutions, which can translate to an ability to accommodate reactive impedance variations with frequency when designing broadband PAs. Index Terms—Broadband amplifiers, microwave devices, microwave measurements, power amplifiers (PAs), radio frequency (RF).

I. INTRODUCTION

C

ELLULAR phone technology has improved considerably over time. During the last decades, different narrowband power amplifier (PA) modes have been theoretically and experimentally explored [1], [2] and further developed [3]. Through the use of waveform engineering and by knowing the different drain voltage and current waveforms, it is possible to define the transistor operation modes. Therefore, by shaping those waveforms, output power, gain and efficiency can be optimized. However, the standard modes starting from the linear class-A to Manuscript received August 17, 2011 revised February 13, 2012; accepted February 16, 2012. Date of publication April 03, 2012; date of current version May 25, 2012. This work was supported in part by the Engineering and Physical Sciences Research Council (EPSRC) under Grant EP/F033702/1 and by Freescale Semiconductor as part of OPERA-NET—a Celtic Eureka funded R&D European Project. V. Carrubba and R. Quay are with the Fraunhofer Institute for Applied Solid State Physics (IAF), 79108, Freiburg, Germany (e-mail: [email protected]; [email protected]). M. Akmal, J. Lees, J. Benedikt, S. C. Cripps, and P. J. Tasker are with the Centre for High Frequency Engineering, Cardiff School of Engineering, Cardiff University, CF 24 3AA, Cardiff, U.K. (e-mail: [email protected]; [email protected]; [email protected]; [email protected]; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2012.2189228

the high-efficiency class-F or inverse class-F (class-F ) perform for the singular frequency solution [1]–[6]. The world’s ongoing standards third-generation (3G) have driven the research on what will be the new emerging fourth generation (4G) such as Long Term Evolution Advanced (LTE-Advanced) [7]. In these new emerging high-quality wireless communication standards, one of the main aimd is to provide higher data rates of around 100 Mb/s for high-mobility communication such as from cars and trains and 1 Gb/s for low-mobility communication such as pedestrians or when stationary [8]. Such standards are not only characterized by higher data rates, but they are also characterized in terms of user capacity and advanced services. This means that the optimum output performance required from the PA for the singular frequency must now be obtained for a wide band of the spectrum frequency. Therefore, broadband and/or multiband PAs for which the overall output performance is optimized are nowadays required and under continuous development. Different techniques have been so far adopted for the realization of both multiband [9], [10] and broadband PAs [11]–[15]. Furthermore, recent investigations have shown theoretical analysis supported by experimental results [16]–[20] as well as actual PA realizations [21]–[26] where the fundamental and harmonic loads can be varied properly from the optimum condition while still maintaining the requested output performance. This paper presents, for the first time, an extended mathematical formulation applied to the inverse class-F mode allowing the proper match of fundamental and harmonic impedances. Starting from the standard inverse class-F state for which optimum fundamental impedance, open-circuit second-harmonic load and short-circuit third-harmonic termination are required, by varying properly such impedances, it will be demonstrated that the output performance does not change significantly. More specifically, by moving the second-harmonic termination inside the Smith chart (resistive second-harmonic load from the opencircuit condition), thus varying the magnitude and phase of such harmonic and adjusting properly the magnitude and phase of the fundamental load in accordance with this new theory, satisfactory output power and drain efficiency are achieved. The third-harmonic termination is maintained fixed at short circuit. The possibility of applying the different theories termed “continuous modes” [16]–[20] on both the inverted and noninverted classes of operation have different advantages, which can be exploited with different technology, device size, and different operating frequencies. For the device size, the choice of using the inverted or noninverted mode depends of the ratio between the harmonics and fundamental impedances, as

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CARRUBBA et al.: CONTINUOUS INVERSE CLASS-F MODE WITH RESISTIVE SECOND-HARMONIC IMPEDANCE

demonstrated here [27]. In terms of frequency, if the device presents low but high operating frequency is required, the noninverted mode would be a preferable choice. This is due to the fact that only first two impedances need to be optimized while the third-harmonic termination would probably be short-circuited due to the drain–source capacitor . This paper is organized as follows. Section II presents briefly the theoretical analysis of the: 1) standard inverse class-F and 2) continuous inverse class-F mode where varying the second-harmonic impedance only on the edge of the Smith chart. Furthermore, a detailed new extended theoretical analysis based on the continuous inverse class-F mode with varying both the reactive and resistive parts of fundamental and second-harmonic impedances are presented in Section II-C. The measurement system is described in Section III-A, and practical measurements on a power transistor are presented in Section III-B. Finally, the conclusion is given in Section IV. II. STANDARD, REACTIVE CONTINUOUS, AND RESISTIVE-REACTIVE CONTINUOUS INVERSE CLASS-F MODES

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(3) where (4) (5) (6) (7) (8) (9) (10) (11) (12)

The inverse class-F PA requires a square current waveform and a half-wave rectified sinusoidal voltage waveform at its intrinsic current-generator plane. These waveforms are achieved by presenting the optimum fundamental impedance [function of the device-under-test (DUT)], open-circuit second-harmonic load and short-circuit third-harmonic termination . The constant values of the fundamental and harmonic impedances lead to an optimized inverse class-F PA for the given fixed frequency. Recent investigations [16]–[20] have shown that it is actually possible to move the second- and/or third-harmonic impedance from the short-circuit and/or open-circuit condition by proper variation of the fundamental load, exploiting a new design space. The following equation shows the standard half-wave rectified sinusoidal voltage waveform (second-harmonic peaking): (1) while (2) shows the new formulation for the current waveform where , and represent the dc, fundamental, and third-harmonic current components, respectively, when . The parameters and are empiric parameters that will describe the new design space. The voltage waveform is normalized to unity. As it can be noted, the voltage waveform is not a function of either and while the current waveform will vary with such parameters. Expanding (2) gives

where represents the quiescent current. [equations from (5)–(7)] represent the real part of the current components of the fundamental, second and third-harmonic impedances, and [equations from (8)–(12)] represent the imaginary part of the current components of the fundamental, second-, third-, fourth-, and fifth-harmonic impedances. The real parts greater than three and the imaginary parts greater than five are equal to zero. 1) Standard Inverse Class-F : When the parameters , as it can be noted from (3) and from equations from (4)–(12), all of the imaginary parts are equal to zero as well as the real part of the second-harmonic current termination , thus (3) leads to the first bracket of (2). Here, the optimum fundamental load, open-circuit second-harmonic load, and short-circuit third-harmonic termination are presented in Fig. 1 (admittance points for ). These impedances reveal the standard inverse class-F square current waveform and the second-harmonic peaking half-wave rectified sinusoidal voltage waveform as shown in black and red, respectively, in Fig. 2. 2) Reactive Continuous Inverse Class-F : Keeping and varying the parameter the second-harmonic termination varies reactively on the edge of the Smith chart from its open-circuit condition while the fundamental impedance varies on its circle of constant susceptance with an inverse relationship as shown in Fig. 1 (as well as in Fig. 3). It is important to highlight that for this mode to work successfully, non-zero crossing current waveforms are essential, which means that the parameter has to vary between and 1. The proper variation of fundamental and second-harmonic load (with keeping a constant short-circuit third-harmonic termination) leads to the waveforms shown in Fig. 2. Here, for and the family of continuous current waveform is shown (blue and green respectively) defining the new design space. Although varying the parameter causes the required fundamental and second-harmonic susceptances to vary, both

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Fig. 3. Theoretical fundamental and second-harmonic susceptances (B1 and B2) both normalized to the fundamental conductance (G1) and efficiency and in steps of 0.25. output power (normalized to unity) for Fig. 1. Admittance chart for the theoretical continuous inverse class-F admitin tances range for the first three harmonic loads, when varying steps of 0.25.

Fig. 2. Theoretical continuous inverse class-F current and voltage waveforms in steps of 0.25. for

fundamental and second-harmonic conductances remain constant. Therefore, assuming a constant voltage waveform, a constant optimum output power (in Fig. 3 normalized to unity) over a wide range of can be maintained. As dc current and voltage components will also be maintained as constant, this leads to constant drain efficiency as well, which in this case is 81.85% as three harmonic contents are considered in both voltage and current waveforms, as shown in Fig. 3. Note that B1 and B2 are inversely proportional in order to maintain a constant output power and efficiency. 3) Reactive-Resistive Continuous Inverse Class-F : As shown so far, despite the reactive variation of the fundamental impedance, if adjusting properly the second-harmonic impedance on the perimeter of the Smith chart , the optimum inverse class-F output power and efficiency can still be maintained as constant. However, when dealing with real PAs, it is not possible to realize ideal matching networks with reflection coefficient equal to unity. This means for instance that the harmonic impedances (in this case the second-harmonic load) cannot be maintained as a perfect open-circuit. For this reason, the new mathematical formulation taking into account and varying both parameters and is presented. When varying and including the parameter , a new enlarged design space that the authors have termed

reactive-resistive continuous inverse class-F mode (or extended continuous inverse class-F mode), where fundamental and second-harmonic loads can now both be located inside the Smith Chart is presented, as shown in Fig. 4. When varying the second-harmonic load inside the Smith chart , the output performance start to slowly degrade, but, by properly adjusting the fundamental load in accordance with (2), useful performance in terms of power and efficiency can still be achieved. Fig. 5 shows the theoretical computed new family of current waveforms as a function of both parameters and . The current waveform amplitudes decrease with increasing . This is due to the fact that by increasing , the fundamental impedance also increases in accordance with (2), therefore maintaining a constant half-wave rectified sinusoidal voltage waveform, the current waveforms then must decrease in magnitude. Besides, it can be noted that, if considering the standard class( , red waveforms), when increasing , bigger troughs in the waveforms are developed. As already mentioned earlier, the parameter and now also must be varied between 1 and 1 to maintain a nonzero crossing current waveforms. It can be seen from Fig. 6 that drain efficiency varies with , but it would be maintained constant with varying . However, it is important to highlight that, in order to present a positive second-harmonic impedance (inside the Smith chart), the parameter should be constrained between 0 and 1. This is because for negative values of , , the current waveform will still be positive, but negative secondharmonic impedances need to be presented in order to allow the continuous mode to exist. Fig. 7 shows the variation of efficiency as a function of with a constant value of . It can be seen that, for , the standard classwith drain efficiency of 81.85% is obtained. When increasing , the value of efficiency starts to decrease, but considering a certain predetermined target minimum value of efficiency, in this case has been chosen thus given a maximum value for , a very large range of impedances can be obtained maintaining efficiencies greater than 70%. The small degradation in efficiency is traded off against the advantage of having multiple solutions in order to facilitate the design of broadband PAs. It should be noted that for the efficiency increase from its optimum of 81.85% up to almost 100%. This is due to the fact that for in accordance with

CARRUBBA et al.: CONTINUOUS INVERSE CLASS-F MODE WITH RESISTIVE SECOND-HARMONIC IMPEDANCE

Fig. 4. Extended continuous classboth in steps of 0.2.

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for the first two harmonic impedances (third-harmonic load is kept short-circuited) when varying

Fig. 5. Theoretical extended continuous class-

current waveforms when varying

in steps of 0.25 and

and

in steps of 0.2.

Fig. 7. Theoretical efficiency and second-harmonic resistance function of with in steps of 0.2, for constant . Fig. 6. Theoretical efficiency and 1. been varied between

contour plot function of

and

with both

(2) negative second-harmonic impedances are presented [28]. For the analysis and measurements presented in this paper, only positive values of have been considered. Table I shows the reflection coefficient of both fundamental and second-harmonic impedances as a function of , for with step 0.1, for a constant value and considering a 50 optimum fundamental load for the standard class. The phases of both and are all equal to zero for the different values of as, in this case, a constant value has been considered (impedances on the real axes of the

TABLE I REFLECTION COEFFICIENTS OF FUNDAMENTAL AND SECOND-HARMONIC IMPEDANCES AS A FUNCTION OF ALPHA

Smith chart). Besides, as it can be seen from both Table I and Fig. 4, starting from the standard classcondition , where and , increasing the value of , the fundamental load goes toward higher impedances whilst the second-harmonic load goes inside the Smith chart. The third-harmonic impedance is kept constant at a short-circuit.

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Fig. 8. Measurement system architecture in the active ELP configuration.

Fig. 9. Measured inverse class-F voltage and current waveforms function of input power.

III. EXPERIMENTAL MEASUREMENTS A. Measurement System Description The design space defined theoretically in the previous sections has been explored experimentally using the active envelope load-pull (ELP) measurement system developed at Cardiff University [29]. The measurement system configuration using the ELP architecture is shown in Fig. 8. This system is based on the Microwave Transition Analyzer (MTA) sampling scope demonstrated by Demmler et al. [30]. The input signal is provided by a Synthesised Sweeper Source (83640A), delivering power up to 25 dBm. Here, a linear broadband drive power amplifier (PA) is necessary for delivering the required power to the input of the DUT. As it can be seen, the input signal is coupled using a broadband directional coupler where additional attenuators could be used in order to reduce the overall power sent to the MTA ports to less than the maximum safe power allowed (in the order of 0 dBm). A test set of switches is used allowing the two-channel MTA to operate as a four-channel receiver measuring the overall incident and reflected traveling waveforms. Channel 1 is used to measure both the incident waves at the input and output of the DUT while channel 2 is used to measure the reflective waves and determined by the direction of the switches. The dc biasing of the device is achieved by using two bias tees, one at the input and one at the output of the DUT, with a current capability of 0.5 A at the RF bandwidth from 45 MHz to 40 GHz. For higher power (current) capability hybrid couplers can be used. In this case, the dc signal can still go through the bias tee, then joining the RF signal which can go through the hybrid coupler. The fundamental and harmonic impedances are presented by using the ELP technique [29]. In this technique, the device transmitted signal flows through the directional coupler with the aim of isolating the transmitted wave with the injected signal . The transmitted signal , which is rich in harmonic content, is then divided into the three harmonics , , and through an appropriate triplexer, and the three signals can therefore flow into the ELP modules. A detailed analysis and explanation of the ELP configuration can be found in [29]. It is important to highlight that the continuous theory presented in this paper can be experimentally explored by using different harmonic load-pull systems [31]–[33], being the main

Fig. 10. Measured inverse class-F efficiency and available gain function of output power sweep.

Fig. 11. Measured extended continuous inverse class-F range of fundamental (circles), (red) second (blue) and third (green) harmonic loads for (crosses) and (triangles).

target of this work to present the appropriate terminations. Active harmonic load-pull systems would give better performance if compared with the passive load-pull systems as the high harmonic terminations can be easily presented with reflection coefficient (on the edge of the Smith chart) necessary for the high efficiency states. For the passive load-pull systems, reflection coefficient equal to unity cannot be achieved, leading to degradation to the overall performance. This is primarily due to the fact that any losses introduced between the device itself and the load-pull system will reduce the maximum magnitude of the

CARRUBBA et al.: CONTINUOUS INVERSE CLASS-F MODE WITH RESISTIVE SECOND-HARMONIC IMPEDANCE

Fig. 12. Measured extended continuous classin steps of 1 and for

current waveforms when varying in steps of 0.2.

modified signal , limiting the range of load impedances that can be presented. However, recent works have demonstrated passive load-pull systems with near to unity [34], [35]. B. Measurement Results The measurements have been carried out on a 20-dBm GaAs transistor from TriQuint at 4 V of drain voltage and 1 GHz of fundamental frequency. The standard narrowband classmode produces a peak output voltage of and, with the breakdown voltage of this device known to be in the region of 12 V, a drain dc voltage of 4 V has been used. In the standard case (where ), and for the device used in this experiment, the optimum tradeoff between power and efficiency was found for a drain dc quiescent current around 35 mA. As can also be noted from Fig. 9, this corresponds to an RF current swing up to around 65 mA which is not the maximum achievable because of the increasing in the knee region. Now, for this device, when dealing with the new continuous inverse class-F mode, it is possible to utilize the full current drive capability without compromising efficiency. The process implemented in [36] has been used to obtain an optimized standard classdesign. An initial gate bias and input power sweep has been conducted in order to achieve the right bias voltage. For the standard classmode, the optimum bias voltage has been chosen in order to minimize the second-harmonic current component, which is typically around the class-A bias point. For the device used, 0.45 V has been chosen. As measurements have been conducted at the device’s current generator plane, a short-circuit third-harmonic impedance and an open-circuit second-harmonic impedance has been provided, whilst the fundamental impedance has been swept. To achieve the best tradeoff between output power and drain efficiency, a fundamental load impedance of has been chosen at the device current-generator plane, after de-embedding a drain source capacitor 0.23 pF [37]. Fig. 9 shows the measured standard inverse class-F voltage and current waveforms for different input power (at the device intrinsic plane) while

in steps of 0.2 and

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in steps of 0.2 and load-lines

Fig. 10 shows the measured drain efficiency and available gain function of the output power sweep. Drain efficiency of , gain of 17.9 dB and output power of 19.2 dBm have been obtained at approximately 3 dB of gain compression. Once the conventional classmode was established, at around 2–3 dB of compression, the parameters and have been varied and the new solutions of fundamental and secondharmonic loads have been identified as shown in Fig. 11. The third-harmonic load is kept around the short-circuit point. Fig. 12 shows the measured current and voltage waveforms for the impedance points presented in Fig. 11, which means for and for with both steps of 0.2. In addition, the load-lines for with step of 0.2 and for with steps of 1 are also presented. As predicted in the theoretical waveforms (Fig. 5), when increasing the parameter , the achievable maximum peak current waveform decreases. Again, the waveforms for (red) show bigger troughs with increasing , consistent with theoretical predictions. All of these new current waveforms are achieved for fundamental and second-harmonic impedances varied in accordance with (5), (6), (8), and (9) and shown in Fig. 11; therefore, in this case, such equations have been normalized to the optimum initial fundamental impedance of . For all of the measurements, the third-harmonic impedance was set to around the short-circuit whilst the higher impedances greater than three have been considered to be equal to the measurement system characteristic impedance, i.e., 50 . Figs. 13 and 14 show the measured drain efficiency, output power, available gain, and source available power as a function of both and . It can be seen that, with varying the parameter , the device output performance can be maintained almost invariant. The power is approximately constant for all the range of whilst the efficiency is maintained greater than 70% with maximum peak up to 80.9%; dropping just on the edges of the range for the last points of . The available gain decreases with decreasing , this is due to the fact that for the device

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Fig. 13. Measured drain efficiency and varying

and output power with both in steps of 0.2.

when

standard narrow band classcondition, it has been demonstrated that varying the second-harmonic load around the edge of the Smith chart from the open-circuit condition and adjusting the phase of the fundamental impedance, constant output performances can be maintained. Additionally, it has been demonstrated that when presenting a resistive second-harmonic load, the new current formulation will change both magnitude and phase of the required fundamental load, providing the right condition in order to maintain the desired drain efficiency greater than a certain predetermined value, which here the authors have chosen at 70%. The main aim of this work is to provide to the PA designer different useful waveform solutions providing high power and efficiency. Thus, introducing higher flexibility in the PA design process, thanks to providing the opportunity to accommodate reactive impedance variations with frequency when designing broadband PAs. ACKNOWLEDGMENT The authors would like to thank TriQuint Semiconductor for supplying the devices. REFERENCES

Fig. 14. Measured available gain when varying and

and source available power with both in steps of 0.2.

need to be driven harder in order to maintain a constant voltage waveform, this requirement is also identified in the trace. When varying the parameter , the output performance is obviously degraded as the second-harmonic impedance goes inside the Smith chart. However, adjusting the fundamental impedance in accordance with this new theory, efficiencies greater than 70% can still be achieved, thus allowing the realization of high efficiency classPAs, but now for a significantly expanded design space. This will then translate into the ability to design circuits with variable reactive impedances, tracking this “design space” over a wider band of frequencies. The possibility of having different solutions with different current waveforms with varying the output impedances is counter intuitive. In ideal devices, the drain current is obtained through the input voltage, as the transistor is an input voltage-controlled current source. Therefore, once the current waveform is achieved by proper input drive, the voltage waveform would be function of the output impedances. However, in real devices, the actual drain current varies with varying the impedances being the output related to the input through the feedback capacitor as well as being the drain voltage and current waveforms related to each other through the knee region [1]. In this case, by varying properly the impedances and by adjusting slightly the input power (as shown in Fig. 14), it is possible to maintain an almost fixed voltage waveform as reported in Fig. 12. IV. CONCLUSION This paper has presented an extended formulation on the current waveform for the continuous class. Starting from the

[1] S. C. Cripps, RF Power Amplifier for Wireless Communication, 2nd ed. Norwood, MA: Artech House, 2006. [2] F. Colantonio, F. Giannini, and E. Limiti, High Efficiency RF and Microwave Solid State Power Amplifiers. Hoboken, NJ: Wiley, 2009. [3] F. Raab, “Class-F power amplifier with maximally flat waveforms,” IEEE Trans. Microw. Theory Tech., vol. 31, no. 11, pp. 2007–2012, Nov. 1997. [4] E. Cipriani, P. Colantonio, F. Giannini, and R. Giofré, “Theoretical and PAs,” in Proc. experimental comparison of class F versus Class Eur. Micro. Integr. Circuits Conf., Sep. 2010, pp. 428–431. [5] S. Gao, P. Butterworth, A. Sambell, C. Sanabria, H. Xu, S. Heikman, U. Mishra, and R. A. York, “Microwave class-F and inverse class-F power amplifiers designs using GaN technology and GaAs pHEMT,” in Proc. Eur. Micro. Integr. Circuits Conf., Sep. 2006, pp. 493–496. [6] P. Wright, A. Sheikh, C. Roff, P. J. Tasker, and J. Benedikt, “Highly efficient operation modes in GaN power transistors delivering upwards of 81% efficiency and 12 W output power,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2008, pp. 1147–1150. [7] S. Abeta, “Toward LTE commercial launch and future plan for LTE enhancements (LTE-Advanced),” in Proc. Int. Conf. Commun. Syst., 2010, pp. 146–150. [8] Y. K. Kim and R. Prasad, 4G Roadmap and Emerging Communication Technologies. Boston, MA: Artech House, 2006. [9] D. Kalim and R. Negra, “Concurrent planar multiharmonic dual-band load coupling network for switching-mode power amplifiers,” in IEEE MTT-S Int. Microwa. Symp. Dig., Jun. 2010, pp. 1–4. [10] P. Colantonio, F. Giannini, R. Giofre, and L. Piazzon, “A design technique for concurrent dual-band harmonic tuned power amplifier,” IEEE Trans. Microw. Theory Tech., vol. 56, no. 11, pp. 2545–2555, Nov. 2008. [11] J. J. Komiak, C. Kanin, and P. C. Chao, “Decade bandwidth 2 to 20 GHz GaN HEMT power amplifier MMICs in DFP and no FP technology,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2011, pp. 1–4. [12] A. A. Tanany, D. Gruner, A. Sayed, and G. Boeck, “Highly efficient harmonically tuned broadband GaN power amplifier,” in Proc. Eur. Microw. Integ. Circuits Conf., Oct. 2010, pp. 5–8. [13] S. Di Falco, A. Raffo, F. Scappaviva, D. Resca, M. Pagani, and G. Vannini, “High-efficiency broadband power amplifier design technique based on a measured-load-line approach,” in IEEE MTT-S Int. Microw. Symp. Dig., Jul. 2010, pp. 1–1. [14] P. Colantonio, F. Giannini, R. Giofre, E. Limiti, A. Serino, M. Peroni, P. Romanini, and C. Proietti, “A -band high-efficiency second harmonic tuned power amplifier in GaN technology,” IEEE Trans. Microw. Theory Tech., vol. 54, no. 6, pp. 2713–2722, Jun. 2006. [15] H. Sledzik, R. Reber, B. Bunz, P. Schuh, M. Oppermann, M. Mußer, M. Seelmann-Eggebert, and R. Quay, “GaN based power amplifiers for broadband applications from 2 GHz to 6 GHz,” in Proc. Eur. Microw. Conf., Sep. 2010, pp. 1658–1661.

CARRUBBA et al.: CONTINUOUS INVERSE CLASS-F MODE WITH RESISTIVE SECOND-HARMONIC IMPEDANCE

[16] C. Cripps, P. J. Tasker, A. L. Clarke, J. Lees, and J. Benedikt, “On the continuity of high efficiency modes in linear RF power amplifiers,” IEEE Microw. Wireless Compon. Lett., vol. 19, no. 10, pp. 665–667, Oct. 2009. [17] V. Carrubba, A. L. Clarke, M. Akmal, J. Lees, J. Benedikt, P. J. Tasker, and S. C. Cripps, “The continuous class-F mode power amplifier,” in Proc. Eur. Microw. Conf., Sep. 2010, pp. 432–435. [18] C. Friesicke and A. F. Jacob, “Mode continua for inverse class-F RF power amplifier,” in Proc. IEEE German Microw. Conf., Mar. 2011, pp. 1–4. [19] V. Carrubba, A. L. Clarke, M. Akmal, Z. Yusoff, J. Lees, J. Benedikt, S. C. Cripps, and P. J. Tasker, “Exploring the design space for broadband PAs using the novel continuous inverse class-F mode,” in Proc. Eur. Microw. Conf., Oct. 2011, pp. 10–13. [20] V. Carrubba, A. L. Clarke, M. Akmal, J. Lees, J. Benedikt, P. J. Tasker, and S. C. Cripps, “On the extension of the continuous class-F mode power amplifier,” IEEE Trans. Microw. Theory Tech., vol. 59, no. 5, pp. 1294–1303, May 2011. [21] P. Wright, J. Lees, J. Benedikt, P. J. Tasker, and S. Cripps, “A methodology for realizing high efficiency class-J in a linear and broadband PA,” IEEE Trans. Microw. Theory Tech., vol. 57, no. 12, pp. 3196–3204, Dec. 2009. [22] K. Mimis, K. A. Morris, and J. P. McGeehan, “A 2 GHz GaN class-J power amplifier for base station applications,” in Proc. Power Amplifier Wireless Radio Applic., Jan. 2011, pp. 5–8. [23] N. Tuffy, A. Zhu, and T. J. Brazil, “Class-J RF power amplifier with wideband harmonic suppression,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2011, pp. 1–1. [24] J. R. Powell, M. J. Uren, T. Martin, A. McLachlan, P. Tasker, S. Woodington, J. Bell, R. Saini, J. Benedikt, and S. C. Cripps, “GaAs X-band broadband amplifier MMIC based high efficiency on the class B to class J continuum,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2011, pp. 1–4. [25] V. Carrubba, J. Lees, J. Benedikt, P. J. Tasker, and S. C. Cripps, “A novel highly efficient broadband continuous class-F RFPA delivering 74% average efficiency for an octave bandwidth,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2011, pp. 1–4. [26] N. Tuffy, A. Zhu, and T. J. Brazil, “Novel realization of a broadband high-efficiency continuous class-F power amplifier,” in Proc. Eur. Microw. Integr. Circuits Conf., Oct. 2011, pp. 120–123. [27] C. Roff, J. Benedikt, and P. J. Tasker, “Design approach for realization of very high efficiency power amplifiers,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2007, pp. 143–146. [28] A. AlMuhaisen, P. Wright, J. Lees, P. J. Tasker, S. C. Cripps, and J. Benedikt, “Novel wide band high-efficiency active harmonic injection power amplifier concept,” in IEEE MTT-S Int. Microw. Symp. Dig., May 2010, pp. 664–667. [29] M. S. Hashmi, A. L. Clarke, S. P. Woodington, J. Lees, J. Benedikt, and P. J. Tasker, “An accurate calibrated-able multiharmonic active loadpull system based on the envelope load-pull concept,” IEEE Trans. Microw. Theory Tech., vol. 58, no. 3, pp. 656–664, Mar. 2010. [30] M. Demmler, P. J. Tasker, and M. Schlechtweg, “A vector corrected high power on-wafer measurement system with a frequency range for the higher harmonics up to 40 GHz,” in Proc. 24th Eur. Microw. Conf., Sep. 1994, pp. 1367–1372. [31] Z. Aboush, C. Jones, G. Knight, A. Sheikh, H. Lee, J. Benedikt, and P. J. Tasker, “High power active harmonic load-pull system for characterization of high power 100-watt transistors,” in Proc. Eur. Microw. Conf., Oct. 2005, pp. 4–4. [32] D. Barataud, F. Blache, A. Mallet, P. P. Bouysse, J. M. Nebus, J. P. Villotte, J. Obregon, J. Verspecht, and P. Auxemery, “Measurement and control of current/voltage waveforms of microwave transistors using a harmonic load-pull system for the optimum design of high efficiency power amplifiers,” IEEE Trans. Instrum. Meas., vol. 48, no. 4, pp. 835–842, Aug. 1999. [33] A. Ferrero and V. Teppati, “A complete measurement system test-set for non-linear device characterization,” in ARFTG Conf. Dig., Nov. 2001, pp. 1–3. [34] F. M. Ghannouchi, M. S. Hashmi, S. Bensmida, and M. Helaoui, “Loop enhanced passive source-and-Load-Pull technique for high reflection factor synthesis,” IEEE Trans. Microw. Theory Tech., vol. 58, no. 11, pp. 2952–2959, Nov. 2010. [35] V. Teppati, A. Ferrero, and U. Pisani, “Recent advances in real-time load-pull systems,” IEEE Trans. Instrum. Meas., vol. 57, no. 11, pp. 2640–2646, Nov. 2008. [36] A. L. Clarke, M. Akmal, J. Lees, P. J. Tasker, and J. Benedikt, “Investigation and analysis into device optimization for attaining efficiencies in-excess of 90% when accounting for higher harmonics,” in IEEE MTT-S Int. Microw. Symp. Dig., May 2010, pp. 1114–1117.

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[37] R. Gaddi, P. J. Tasker, and J. A. Pla, “Direct extraction of LDMOS small signal parameters from off-state measurements,” Electron. Lett., vol. 36, no. 23, pp. 1964–1966, Nov. 2000.

Vincenzo Carrubba (M’11) received the B.Sc. degree in electronic engineering and M.Sc. degree in microelectronic engineering from the University of Catania, Catania, Italy, in 2005 and 2008, respectively. He is currently working toward the Ph.D. degree in electronic engineering at the Centre for High Frequency Engineering, Cardiff University, Cardiff, Wales, U.K. While with the University of Cardiff, his research interests were the development of active load-pull techniques, the characterization of RF/microwave devices and the design of narrow band and broadband power amplifiers used in wireless communications. He is currently with the Fraunhofer Institute for Applied Solid-State Physics (IAF), Freiburg, Germany. Here his main interests include the design of hybrid and monolithic microwave integrated circuit broadband power amplifiers.

Muhammad Akmal was born in Gujranwala, Pakistan. He received the B.Sc. degree in electrical engineering (with distinction) from Bahauddin, Zakariya University, Multan, Pakistan, in 2005, and the M.Sc. degree in electronic engineering (with distinction) from Cardiff University, Cardiff, Wales, U.K., in 2008, where he is currently working toward the Ph.D. degree. From 2005 to 2006, he was with Alcatel Telecom Pakistan, Lahore, Pakistan, as a Technical Support Engineer, where he was involved in the maintenance, troubleshooting, and all of the major operational applications of Alcatel 1000 E 10 MM, a high-capacity network switching subsystem. He joined the Cardiff School of Engineering in September 2006. His current research interests are developing the modulated waveform measurement system, characterization of nonlinear distotsion in microwave power transistors, linearization, and design and measurements of high-power and spectrum-efficient power amplifiers.

Rüdiger Quay (SM’10) received the Diploma degree in physics and the Diploma in economics from Rheinisch-Westfälische Technische Hochschule (RWTH), Aachen, Germany, in 1997 and 2003, respectively, and the Ph.D. degree in technical sciences (with honors) and the venia legendi in microelectronics from the Technische Universität Wien, Vienna, Austria He is currently a Research Engineer with the Fraunhofer Institute of Applied Solid-State Physics, Freiburg, Germany, heading the RF-devices and characterization group. He has authored and coauthored over 100 refereed publications and three monographs. Dr. Quay is a member of the IEEE Microwave Theory and Techniques Society (IEEE MTT-S) and chairman of MTT-6.

Jonathan Lees received the B.Eng. degree in electronic engineering from Swansea University, Wales, U.K., in 1992, and the M.Sc. and Ph.D. degrees from Cardiff University, Cardiff, U.K., in 2001 and 2006, respectively. From 1992 to 2002, he was with QinetiQ, where he developed global positioning and advanced optical instrumentation tracking systems. He is a Chartered Engineer and he is now a Lecturer with the Centre for High Frequency Engineering, Cardiff University, Cardiff, U.K., where his research continues into power amplifiers design, load-pull, and large-signal measurement systems.

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Johannes Benedikt received the Dipl.-Ing degree from the University of Ulm, Ulm, Germany, in 1997, and the Ph.D. degree from Cardiff University, Cardiff, U.K., in 2002. During this time, he took on an additional position as a Senior Research Associate with Cardiff University, Cardiff, U.K., starting in October 2000, where he supervised a research program with Nokia on RFPAs. In December 2003, he was appointed a Lecturer with Cardiff University, where he was responsible for furthering research in the high-frequency area. In April 2010, he was awarded a Professorship at Cardiff University. His main research focus is on development of systems for the measurement and engineering of RF current and voltage waveforms and their application in complex PA design.

Steve C. Cripps (M’81–SM’92–F’11) received the Ph.D. degree from Cambridge University, Cambridge, U.K. He was with Plessey Research, where he was involved with GaAsFET hybrid circuit development. Later, he joined Waitkins-Johnson’s Solid State Division, Palo Alto, CA, and he has held Engineering and Management positions at WJ, Loral, and Celeritek. During this period, he designed the industry’s first 2–8 and 6–19 GHz 1 watt solid-state amplifiers. In 1983, he published a technique for microwave power amplifier design, which has become widely adopted in the industry. In 1990, he became an independent consultant and was active in a variety of commercial RF product developments, including the design of several cellular telephone PA MMIC products. In 1996, he returned to the U.K., where he is consulting activities continue to be focused in the RFPA area. He has recently been appointed

a Professional Research Fellow at Cardiff University, U.K. He has recently authored a second edition of his best selling book, RF Power Amplifiers Design for Wireless Communication (Artech House, 2006). Dr. Cripps was a recipient of the 2008 IEEE Microwave Applications Award. He is currently vice-chair of the High Power Amplifier Subcommittee of the Technical Coordination and Technical Program Committees of the IEEE Microwave Theory and Techniques Society (IEEE MTT-S) and writes the regular “Microwave Bytes” column in the IEEE Microwave Magazine.

Paul J. Tasker (M’88–SM’07) received the B.Sc. degree in physics and electronics and Ph.D. degree in electronic engineering from Leeds University, Leeds, U.K., in 1979 and 1983, respectively. From 1984 to 1990, he was a Research Associate with Cornell University, Ithaca, NY, with Prof. L. Eastman, where he was involved in the early development of HFET transistors. From 1990 to 1995, he was a Senior Researcher and Manager with the Fraunhofer Institute for Applied Solid State Physics (IAF), Freiburg, Germany, where he was responsible for the development of millimeter wave MMICs. He joined the School of Engineering, Cardiff University, Cardiff, U.K., as a Professor in the summer of 1995, where he has been establishing the Cardiff University and Agilent Technology Centre for High Frequency Engineering. The center’s research objective is to pioneer the development and application of RF-IV waveform and engineering systems, with a particular focus to addressing the PA design problem. He has contributed to over 200 journal and conference publications and given a number of invited conference workshop presentations. Dr. Tasker was appointed an IEEE Distinguished Microwave Lecturer for the term of 2008–2010.

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Behaviors of Class-F and Class-F

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Amplifiers

Junghwan Moon, Student Member, IEEE, Seunghoon Jee, Student Member, IEEE, Jungjoon Kim, Student Member, IEEE, Jangheon Kim, Member, IEEE, and Bumman Kim, Fellow, IEEE Abstract—Operational behaviors of the class-F and class-F amplifiers are investigated. For the half-sinusoidal voltage waveamplifier, the amplifier should be operated form of the class-F in the highly saturated region, in which the phase relation between the fundamental and second harmonic currents are out-of-phase. The class-F amplifier can operate at the less saturated region to form a half sinewave current waveform. Therefore, the class-F amplifier has a bifurcated current waveform from the hard saturated operation, but the class-F amplifier operates as a switch at the saturated region for a second harmonic tuned half-sine waveform. To get the hard saturated operation, the fundamental load is very times larger than that of the tuned load large, more than amplifier. The operational behaviors of the amplifiers are explored with the nonlinear output capacitor. Since the capacitor generates a large second harmonic voltage with smaller higher order terms, the class-F amplifier with the nonlinear capacitor can deliver the proper half-sinusoidal voltage waveforms at a lower power, but the effect of the nonlinear capacitor is small for the class-F amplifier. The class-F amplifier delivers the superior performance at the highly saturated operation due to its larger fundamental current and voltage generation at the expense of the larger voltage swing. The simulation results lead to the conclusion that the class-F amplifier with the nonlinear capacitor is suitable topology for high amplifier efficiency. However, in the strict sense, the class-F with the nonlinear capacitor is not the classical class-F amplifier because the voltage-shaping mechanisms and the fundamental load are quite different. We call it the saturated amplifier since the amplifier is the optimized structure of the power amplifier operation at the saturated mode. Index Terms—Class-F , class-F, efficiency, nonlinear capacitor, power amplifier (PA), saturated PA.

I. INTRODUCTION

H

IGH efficiency is a crucial design consideration not only for the power amplifier (PA) itself, but also for the transmitters, such as Doherty and supply modulated PAs, for thermal

Manuscript received October 01, 2011; revised February 07, 2012; accepted February 21, 2012. Date of publication April 06, 2012; date of current version May 25, 2012. This work was supported by The Ministry of Knowledge Economy (MKE), Korea, under the Information Technology Research Center (ITRC) support program supervised by the National IT Industry Promotion Agency (NIPA) [NIPA-2012-(C1090-1211-0011)], the World Class University program funded by the Ministry of Education, Science and Technology through the National Research Foundation of Korea (R31-10100), and the Brain Korea 21 Project in 2012. J. Moon is with the Department of Electrical Engineering and the Division of Information Technology Convergence Engineering, Pohang University of Science and Technology, Pohang, Gyeongbuk, 790-784, Korea, and also with the Telecommunication Systems Division, Samsung Electronics Company Ltd., Suwon, Gyeunggi 443-742, Korea (e-mail: [email protected]). S. Jee, J. Kim, and B. Kim are with the Department of Electrical Engineering and Division of Information Technology Convergence Engineering, Pohang University of Science and Technology, Pohang, Gyeongbuk, 790-784, Korea (e-mail: [email protected]; [email protected]; [email protected]). J. Kim is with the Telecommunication Systems Division, Samsung Electronics Company Ltd., Suwon, Gyeunggi 443-742, Korea (e-mail: [email protected]). Digital Object Identifier 10.1109/TMTT.2012.2190749

management, reliability, and size [1]–[23]. Several PA topologies, such as class-E, class-F, and class-F , have been proposed to achieve high efficiency [3]–[17]. In the class-E PA, a transistor acts as a switch. The voltage of the class-E amplifier is generated by charging and discharging of output capacitor in parallel with the switch. Since this amplifier tunes all harmonic components using the LC resonator, it delivers the highest efficiency among the proposed amplifiers. However, the charging step of the capacitor cannot be abrupt. Above the theoretical maximum frequency , the capacitor cannot discharge fast enough to support the ideal waveform [3], [4]. As a result, efficiency of the class-E PA is degraded significantly at the high frequency above [3]–[6]. To deliver high efficiency at the high frequency, the harmonically tuned PAs, such as class-F and class-F amplifiers, have been extensively studied [7]–[23]. The ideal class-F amplifier has half-sinusoidal current and rectangular voltage waveforms in conjunction with the short circuit for even harmonic and open circuit for odd harmonic. Thus, there is no overlapping between the current and voltage, resulting in zero internal dissipation power. In addition, since there is no harmonic power, the class-F amplifier delivers the theoretical efficiency of 100%. The class-F is a dual of the class-F PA where the current and voltage waveforms are interchanged. With the same drain supply voltage, the class-F amplifier has larger peak voltage value than that of class-F, incurring the reliability problem due to breakdown of the device. Thus, some research has compared and analyzed the class-F and class-F PAs under the condition of the same voltage swing [7], [8]. Recently, due to advances in wide bandgap semiconductor technology such as gallium–nitride (GaN) high electron-mobility transistor (HEMT) technology, a large voltage swing becomes feasible. This resolves the maximum voltage limitation of the class-F amplifier, allowing the amplifier to operate with the same supply voltage of the class-F PA. As the breakdown issue of the class-F amplifier is moderated, a lot of research has investigated the PAs under the condition of the same supply voltage [9]–[16]. Although the previous research clearly show that the class-F amplifier outperforms the class-F PA, there is no in-depth explanation for the performance of the class-F amplifier. Moreover, most of these analyses have been carried out under the assumption of the linear input and output device capacitances. In this paper, the class-F and class-F amplifiers are numerically compared in terms of the optimum load impedance, output power, and efficiency according to the conduction angle. The numerical analysis is validated using a simplified model with linear and nonlinear capacitors. Unlike the class-F amplifier, the operation of the class-F PA is strongly affected by the nonlinear output capacitor because the capacitor generates a

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A. Numerical Comparison 1) Basic Formulations: For the numerical analysis of the class-F and class-F amplifiers, most of assumptions, related to the active device, the number of harmonics to be controlled, and the load conditions, are made based on [15], [17], and [18]. The additional assumptions used in this study are as follows. • Input harmonic is not considered, and the current waveform is assumed to be bifurcated when the amplifier is overdriven beyond the maximum linear input power level, as shown in Fig. 1, where is the overdriving ratio. • The same supply voltages are assumed for both amplifiers. Based on the assumptions, the voltage waveforms of the class-F and class-F PAs [17], [18] are expressed by

Fig. 1. Modeled current waveform when the PA is overdriven.

large second harmonic voltage component, shaping the voltage waveform. The current waveform is bifurcated due to the saturated operation, resulting in a quasi-rectangular waveform [15], [21]. The operation of class-F amplifier is different and the bifurcation does not occur. Thus, the fundamental current of the class-F PA is reduced and voltage is enlarged, requiring a large fundamental load. The fundamental load should be times larger than that of the tuned amplifier. Thus, the class-F PA with the nonlinear capacitor can be considered a new kind of amplifier, which is called as a saturated amplifier [3], [19]–[21]. This amplifier is the optimized structure of PA operation at the saturated mode. Although the current and voltage waveforms of the saturated amplifier are the same as those of the class-F amplifier, the waveform-shaping mechanisms of both amplifiers are different. This paper is organized as follows. In Section II, the class-F and class-F amplifiers are numerically analyzed according to the conduction angle. In addition, the numerical analysis is verified by the simplified device model with the linear capacitor. With the device model with the nonlinear capacitor, the operational behaviors of the both amplifiers are further explored in Section III. In Section IV, the commercial device model is used for comparing the class-F and saturated amplifiers. In addition, the operation of the saturated amplifier using the model is verified. Finally, the conclusions are presented in Section V. II. ANALYSIS FOR BASIC OPERATION OF CLASS-F CLASS-F AMPLIFIERS USING IDEALIZED CURRENT WAVEFORM

AND

In this section, the class-F and class-F amplifiers are analyzed for output power, efficiency, and gain performances in terms of input overdriving power, load impedance, and conduction angle. Numerical analysis is carried out using an idealized current waveform, shown in Fig. 1, then a simplified device model is employed to validate the analysis. The following analysis and results are dependent on harmonic load such as operation at the saturation region. The process is accurate for the class-F amplifier, but has a limitation for the class-F amplifier. However, the class-F amplifier does not drive into the saturated mode. Thus, the followings provide the operation behaviors and good guidelines for the class-F and class-F amplifiers.

(1) (2) ,

,

, and

are defined by

(3) For the class-F amplifier, the maximum fundamental voltage, which is times larger than that of the tuned load amplifier , can be achieved with of 1/6 [17]. The tuned load amplifier represents the amplifier with short-circuit termination for all harmonics. Similarly, for the class-F amplifier, the maximum fundamental voltage, times larger than that of the tuned load PA, can be obtained with of [18]. For the resistive loads, the amplifiers can have the maximum fundamental voltages when the phase relation between the fundamental and each harmonic component are out-of-phase. However, as shown in Fig. 2, the phase relation between the fundamental and second or third harmonic is not always satisfied, and can be achieved only at the overdriven operation. Since the active device acts as an ideal voltage controlled current source, the proper voltage waveforms for the class-F and class-F amplifiers can be obtained using the suitable load impedances. The required third harmonic load impedance for the class-F amplifier and second harmonic load impedance for the class-F amplifier are derived from and , respectively [17], [18]. The harmonic load impedances are proportional to the current ratios. However, the harmonic current components are quite small compared to the fundamental current when the phases of the harmonic components begin to reverse from in-phase to out-of-phase, as shown in Fig. 2. As a result, the required harmonic load impedances are very large and unfeasible. For practical comparison, the performances of the

MOON et al.: BEHAVIORS OF CLASS-F AND CLASS-F

AMPLIFIERS

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Fig. 3. Calculated input overdrive ratios to achieve the proper operations of class-F and class-F amplifiers.

Fig. 4. Calculated fundamental load impedance ratios for class-F and class-F amplifiers with respect to the tuned load PA.

Fig. 2. Fourier components of the overdriven current waveform shown in Fig. 1. (a) Fundamental, (b) second harmonic, and (c) third harmonic components.

class-F and class-F amplifiers are compared under the condition that the required third or second harmonic load impedance is less than five times the fundamental load impedance. The required input overdrive ratios, according to the conduction angle, for the class-F and class-F amplifiers are depicted in Fig. 3. Compared to the class-F, the class-F amplifier requires larger overdrive ratio, reducing the fundamental current as shown in Fig. 2(a). In this figure, the practical case represents when the required harmonic load impedances are limited to the five times of the fundamental load impedances and ideal case represents when the harmonic load impedances are not limited. 2) Comparison: Fig. 4 shows the calculated fundamental load impedance ratios for the class-F and class-F PAs over the tuned load amplifier. For conduction angle above 120 , the

class-F PA has the fundamental voltage 1.15 times larger than that of the tuned load PA, while the fundamental current is similar to that of the tuned load PA because the required phase relation can be satisfied with low input overdrive level less than 2 dB. For this level, the fundamental current is nearly maintained for the maximum value, as shown in Fig. 2(a), for the conduction angle above 120 . However, for the conduction angle below 120 , the fundamental load impedance starts to increase, but the conduction angle below 120 is not usually employed because of the low output power. Thus, the fundamental load impedance of the class-F amplifier can be regarded as . The class-F amplifier delivers the fundamental voltage times larger than that of the tuned load amplifier. However, it requires the highly overdriven operation to obtain the proper phase relation, as shown in Fig. 3. As a result, the fundamental current of the class-F amplifier is lower than that of the class-F or tuned load amplifiers for most of the conduction angles. Although the ideal fundamental load impedance ratio of the class-F PA is about , the impedance increases significantly as the conduction angle decreases. It is worthwhile to notice that the bifurcated current waveform is suitable to the

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conduction angle increases, the class-F amplifier is still in the heavily saturated region, but the fundamental current increases, and the ratio of fundamental to dc currents increases, enhancing the efficiency, as shown in Fig. 5(b). B. Analysis Using Simplified Device Model

Fig. 5. Calculated output performances of class-F, class-F PAs. (a) Output power. (b) Efficiency.

, and tuned load

class-F amplifier, but not to the class-F amplifier. However, the class-F amplifier operates near the saturation region and the error can be small. Also, this model does not accurately describe the saturated characteristic of the current, and we will revisit this behavior in Section II-B.2. Fig. 5 shows the calculated output power and efficiency characteristics of the class-F, class-F , and tuned load amplifiers. Due to the reduced fundamental current of the class-F amplifier, this amplifier delivers the output power less than that of the class-F or tuned load PA below the conduction angle of 220 even though the class-F amplifier has the largest fundamental voltage component. As the conduction angle increases, the required input overdrive ratio decreases and the fundamental current of the class-F amplifier increases rapidly, resulting in the larger output power, as shown in Fig. 5(a). Fig. 5(b) illustrates the efficiencies of the amplifiers. Since the class-F amplifier operates at a highly saturated mode for all conduction angles, the ratio of fundamental to dc currents of the amplifier is lower than that of the class-F or tuned load PA. However, among the three PAs, the class-F PA has the largest fundamental voltage component for the same dc bias. Thus, at the low conduction angle below 180 , the current is low and the efficiency is similar to that of the class-F amplifier. As the

In this section, the numerical analysis carried out in Section II-A is verified using the simplified device model with a linear capacitor. The comparison is made for the conduction angle between 180 and 250 , which is the practical operation region. 1) Device Model: Fig. 6(a) shows the simplified transistor model employed in this study. It consists of the input capacitor , input resistance , nonlinear voltage-controlled current source, nonlinear output conductance , and output capacitor . The feedback capacitor is absorbed into and by the Miller theorem. Fig. 6(b) depicts the dc–IV characteristic, extracted from Cree GaN HEMT CGH60015 large-signal model by applying the pulsed signal. The extracted input and output capacitors are illustrated in Fig. 6(c) and (d), respectively. Although the capacitors are nonlinear, they are regarded as the linear components to simply explore the operation of the class-F and class-F amplifiers. However, in Section III, the transistor model including the nonlinear capacitors is employed to accurately investigate the operational behaviors of the amplifiers. 2) Results: For reference, a tuned load PA is also designed during the analysis of class-F and class-F amplifiers. In order to maximize the gain, the fundamental source impedances for all PAs are conjugately matched to , while the harmonics at the input are shorted. The fundamental load impedance of the tuned load PA is determined by (4) corresponds to the conduction angle. During the simulation, all amplifiers have the drain supply voltage of 30 V. Since the class-F amplifier has 1.15 times larger fundamental voltage and the comparable fundamental current compared to the tuned load PA, is , as mentioned in Section II-A.2. Although the class-F amplifier delivers times larger fundamental voltage than the tuned load PA, the amplifier operates in deeply saturated region, in which the fundamental current cannot be exactly estimated. Thus, the fundamental load impedance of the class-F amplifier is optimized for the maximum output power. The harmonic manipulation at the load is carried out up to third harmonic for simplicity. For the tuned load PA, the harmonics at the load are shorted. For the class-F amplifier, the second harmonic is shorted, but the third harmonic is selected to maximize output power and efficiency, but is limited to five times . Similarly, the third harmonic of the class-F amplifier is shorted, but the second harmonic of the amplifier is optimized for the output power and efficiency within five times . Since the current model used in Section II-A is an idealized one, the fundamental current at the deeply saturated region is much lower than that of the real device model. Thus, the impedance ratio of the class-F amplifier is similar to the real

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Fig. 7. Simulated load impedance ratios.

larger voltage of the class-F amplifier increases the output power of the amplifier, and even at a low conduction angle, the output powers of the class-F and class-F PAs are similar, as shown in Fig. 8(a). Due to the heavily saturated operation of the class-F amplifier, the gain is lower than that of the class-F or tuned load PA, as shown in Fig. 8(b). As mentioned in Section II-A.2, the fundamental voltages of the amplifiers are nearly the same for the different conduction angle. The maximum voltages of the amplifiers are nearly maintained, 76.5 V for the class-F amplifier and 57.2 V for the class-F and tuned load PAs. The ratio of the fundamental current to dc current of the class-F amplifier is nearly constant for the larger conduction angle, as shown in Fig. 9, and the efficiency of the class-F amplifier is maintained at the larger conduction angle, while those of the other PAs are reduced, as shown in Fig. 8(b). In addition, the fundamental load impedance of the class-F amplifier is larger than that of the class-F amplifier, and the class-F amplifier has a reduced knee voltage effect, increasing the efficiency. Thus, the efficiency difference between the two amplifiers is slightly increased compared to the difference in Fig. 5(b). In short, the simulation based on the idealized current waveform is accurate, except for the class-F amplifier with a small conduction angle. The model predicts that as the conduction angle increases, the class-F amplifier is superior to the class-F PA for the output power and efficiency. However, for the proper voltage shaping of the class-F amplifier, it should be driven into the deeply saturated state, degrading the power gain and requiring a large voltage swing. III. POWER-LEVEL-DEPENDENT CHARACTERISTICS CLASS-F AND CLASS-F AMPLIFIERS USING THE SIMPLIFIED MODEL Fig. 6. Simplified transistor model used in this study. (a) Equivalent transistor model. (b) DC–IV characteristic. Capacitances for the linear and nonlinear: (c) input capacitors and (d) output capacitors. All parameters in (a) are extracted from the Cree GaN HEMT CGH60015 large-signal model using Agilent ADS.

case, but that of the class-F amplifier is somewhat exaggerated. The impedance of the class-F amplifier is almost constant for the conduction angle. Fig. 7 shows the simulated load impedance ratios of the class-F and class-F amplifiers. This

OF

In this section, the operational behaviors of the class-F and class-F amplifiers are further investigated with the device model, including the input and output nonlinear capacitors, as shown in Fig. 6. These capacitors vary according to the power level. Thus, the comparison of the class-F and class-F amplifiers are accomplished according to the power level. Although the class-B or class-C biased PA delivers better efficiency, it has poor linearity with lower output power compared to the class-AB amplifier. Thus, hereafter, all PAs are biased at the

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Fig. 8. Simulated performances of class-F, class-F , and tuned load PAs versus conduction angle. (a) Output power. (b) Power gain and efficiency.

Fig. 10. Simulated fundamental: (a) output currents and (b) voltages of class-F, , class-F , and tuned load PAs according to the input class-F with the power level. During the simulation, all PAs are biased at a conduction angle of 190 .

A. Class-F and Class-F

Fig. 9. Simulated output currents and voltages of class-F, class-F load PAs.

, and tuned

class-AB PA with a conduction angle of 190 . The optimum load impedances for the amplifiers are initially selected based on the analysis in Section II, then slightly tuned to maximize the output power and efficiency.

Amplifiers with Linear Capacitor

Before considering the effects caused by the nonlinear capacitor, for a reference, the power-level dependent behaviors of the class-F and class-F amplifiers with the linear capacitor are analyzed. To compare the amplifiers under the same knee voltage effect, the class-F amplifier with is also designed. Fig. 10 shows the simulated fundamental currents and voltages of the class-F, class-F with the , class-F , and tuned load amplifiers, and Fig. 11 depicts the simulated voltage and current waveforms and load-lines of the amplifiers. For the input power of below 10 dBm, all PAs are in the linear region, in which the current is mainly determined by the input power. Thus, the fundamental currents of the PAs are nearly the same at the region. However, since the class-F and class-F amplifiers with the amplifiers have a fundamental load impedance larger than the other PAs, their maximum currents are limited. Compared to the class-F amplifier, the fundamental voltages of the other two amplifiers are larger due to the larger fundamental load. As the input power increases, the amplifiers generate harmonic currents, shaping the voltage waveforms. Since the phase relation of the fundamental to third harmonic currents

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Fig. 11. Simulated voltage and current waveforms and load-lines of: (a) class-F, (b) class-F with the

are out-of-phase even at a low input power level, the proper voltage shape is carried out earlier for the class-F amplifier, and at the input power of 10 dBm, the two class-F amplifiers have the proper voltage waveforms. However, the second harmonic current is in-phase at the low input power and the voltage waveform for the class-F amplifier is in the reversed half-sinusoidal waveform. Even though the fundamental load impedance of the class-F amplifier is the same as the class-F amplifier with , the fundamental voltage component at this power level is smaller. This improper operation also deteriorates the current waveform, as shown in Fig. 11(c), reducing the fundamental current. The proper phase relationship of the currents is obtained above 20 dBm, and the half-sinusoidal voltage waveform is achieved, increasing the fundamental voltage. In addition, the properly shaped voltage waveform also generates the properly shaped current waveform, as shown in Fig. 11(c), thereby continuously enhancing the fundamental current and voltage as the power level increases. Due to the harmonic load, the class-F amplifier operates as a saturated amplifier at the high power region, following the bifurcated current waveform, but the bifurcation is limited due to the second harmonic voltage. However, the current waveform of the class-F amplifier should be different from the bifurcated waveform. Due to the shorted second harmonic load, the second harmonic voltage cannot be supported, but only the third harmonic voltage can. Therefore, the device operates as a switch in the saturated region, as shown in Fig. 11(a) and (b). The fundamental load impedance of the class-F amplifier with the is larger than that of the class-F amplifier and its maximum fundamental current is lower, but the fundamental voltage is slightly increased due to the low knee voltage. Fig. 12 shows the simulated performances of the amplifiers. At a high power, the fundamental currents of the class-F amplifiers are maintained, but the dc currents are increased as the input power enlarges, degrading the efficiency with constant output powers [see Fig. 12(a) and (b)]. Due to the larger fundamental load impedance of the class-F amplifier with , the output power is lower than that of the class-F amplifier. For

, and (c) class-F

amplifiers.

the class-F amplifier, even though the fundamental current is a little low, the fundamental voltage is increased up to times the fundamental voltage of the tuned load PA. Thus, the output power of the class-F amplifier at the high power region is larger than the others. However, the improper phase relation of the currents at the low power region reduces the output power, degrading the gain and efficiency. The class-F amplifier with the and class-F amplifiers have the same knee voltage effect. Thus, the maximum efficiencies of the amplifiers is nearly the same. At a high drive level, the fundamental current of the class-F amplifier increases together with the dc current. Therefore, the output power increases with near constant efficiency. Overall, the class-F PA can deliver the best output power and efficiency performances at the cost of the larger voltage swing. B. Class-F Amplifier With Nonlinear Capacitor The input and output nonlinear capacitors, shown in Fig. 6(c) and (d), change according to the input power level. , including the nonlinear gate–source capacitor and gate–drain capacitor transferred by the Miller effect, increases as the gate–source voltage increases. Although this capacitor changes also with the drain–source voltage, we assume the gate–source voltage dependent change only for simplicity. , consisted of the nonlinear drain–source capacitor and Miller transferred gate–drain capacitor, decreases as the drain–source voltage increases. These nonlinear capacitors generate the harmonic voltage components at the input and output of the transistor. Those harmonic components are pretty large and change the operational behaviors of the amplifiers. Nonlinear generates the harmonics with some phase. Thus, the harmonic load should be adjusted for the phase and is no longer resistive. Nonlinear also generates a large second harmonic with smaller high-order harmonics. The capacitor also contributes to the current shaping because the nonlinear capacitance is the voltage-dependent output load. 1) Effects of the Nonlinear Input Capacitor: To explore the influence of the nonlinear input capacitor on the Class-F amplifier, the third harmonic load–pull simulation is carried

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Fig. 12. Simulated: (a) output power, (b) efficiency, and (c) power gain performances of class-F, class-F with to the input power level.

, class-F

, and tuned load PA according

Fig. 13. Third harmonic load–pull simulation results: efficiency and output power contours of class-F PA with the linear and nonlinear input capacitors.

out, for simplicity, without the linear output capacitor. As the input power increases, the capacitance of the nonlinear capacitor also enlarges, degrading the gain performance. Thus, for the load–pull simulation, the input powers of the PAs with the linear and nonlinear capacitors are set to 20 and 24 dBm, respectively. The fundamental load impedances for both PAs are adjusted to provide the maximum efficiency. All harmonic impedances at the source are shorted, which is nearly the optimum condition. Fig. 13 shows the efficiency and output power contours and Fig. 14 depicts , , and contours of the class-F amplifier with the linear and nonlinear input capacitors, respectively. , , and represent the magnitudes of the fundamental voltage, fundamental current, and dc current, respectively. The nonlinear input capacitor changes the phase relation between the fundamental and third harmonic currents, and the optimum third harmonic impedance for the high efficiency and output power is not purely resistive. Since the nonlinear input capacitor generates the in-phased second harmonic, the voltage across the capacitor becomes the reversed half-sinusoidal shape. Thus, the effective conduction angle is increased, decreasing the efficiency. As the input power increases, the input capacitance also increases, reducing the gain. In addition, due to the enlarged effective conduction angle caused by the nonlinear capacitor, the maximum and of the amplifier with the nonlinear capacitor are increased. Therefore, the maximum output power is slightly increased by 0.06 dBm, to 42.942 dBm. However, the maximum is quite larger and the maximum efficiency is somewhat lowered.

Fig. 14. Third harmonic load–pull simulation results: , , and tours of class-F PA with the linear and nonlinear input capacitors.

con-

2) Effects of the Nonlinear Output Capacitor: To explore the influence of the nonlinear on the class-F amplifier, the third harmonic load–pull simulation is carried out when is nonlinear. The fundamental load impedances for the amplifiers with the linear and nonlinear output capacitors are adjusted to maximize the output power at the input power of 24 dBm. The fundamental source impedances of the amplifiers are conjugately matched to deliver the maximum power to the input of the transistor. Fig. 15 shows the efficiency and output power contours of the class-F amplifier with linear and nonlinear output capacitors and Fig. 16 illustrates , , and contours of the amplifier. Even though the maximum and of the PA with the nonlinear are similar to the PA with the linear capacitor, the PA with the nonlinear capacitor has larger and over a wider impedance level. Apparently, such characteristics are caused by the harmonic generation of the nonlinear capacitor. In this region, the ratio of and of the PA with the nonlinear output capacitor is slightly larger than the PA with linear output capacitor, resulting in higher efficiency over a wider impedance level. Fig. 17 shows the simu-

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Fig. 15. Third harmonic load–pull simulation results: efficiency and output power contours of class-F PA with the linear and nonlinear output capacitors.

Fig. 17. Simulated: (a) fundamental voltage and current and (b) output power and efficiency characteristics of class-F PAs with the linear and nonlinear output capacitor according to the input power. Fig. 16. Third harmonic load–pull simulation results: , , and contours of class-F PA with the linear and nonlinear output capacitors.

lated fundamental voltage, fundamental current, output power, and efficiency characteristics of the class-F amplifier with the linear and nonlinear . Since the nonlinear output capacitor generates a large second harmonic with a small third harmonic, both PAs provide nearly the same performance. Fig. 18 represents the voltage and current waveforms when the amplifiers deliver the maximum efficiency. C. Class-F

Amplifier with Nonlinear Capacitor

1) Effects of the Nonlinear Input Capacitor: Similarly to the Class-F amplifier, the nonlinear input capacitor increases the effective conduction angle. Therefore, the dc and fundamental currents and fundamental voltage are enlarged. Since the efficiency is maintained for the conduction angle, as shown in numerical analysis results for the Class-F PA in Section II-A, the efficiencies of the two PAs are nearly the same. The results are summarized in Table I. 2) Effects of the Nonlinear Output Capacitor: To explore the influence of the nonlinear output capacitor on the class-F amplifier, the second harmonic load–pull simulation is carried out for the model with the nonlinear input capacitor. Fundamental load impedances for the PAs with the linear and nonlinear output

Fig. 18. Simulated voltage and current waveforms of class-F PA with the linear and nonlinear output capacitors at the input power of 25 dBm.

capacitors are adjusted to maximize the output power. In order to deliver the maximum input power to the transistor at the maximum power level, the fundamental source impedances of the both PAs are conjugately matched. The simulations are conducted at the input power of 27.7 dBm. Fig. 19 shows , , and contours of the class-F amplifier with the linear and nonlinear output capacitors. Similarly to the class-F amplifier, the class-F amplifier with the nonlinear capacitor has

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TABLE I FUNDAMENTAL

AND

DC COMPONENTS

OF THE CURRENT AND VOLTAGE OF THE CLASS-F AND WITH LINEAR AND NONLINEAR INPUT CAPACITORS

CLASS-F

AMPLIFIERS

Fig. 19. Second harmonic load–pull simulation results: , , and contours of class-F PA with linear and nonlinear output capacitors.

Fig. 21. Simulated: (a) fundamental voltage and current and (b) output power and efficiency characteristics of class-F PA with linear and nonlinear output capacitors according to the input power. Fig. 20. Second harmonic load–pull simulation results: efficiency and output power contours of class-F PA with linear and nonlinear output capacitors (the second harmonic load–pull).

larger and over a wider region on the Smith chart. In addition, the ratio of to of the amplifier is larger than that of the class-F amplifier with the linear capacitor, resulting in larger efficiency and output power across the wider impedance level, as shown in Fig. 20. Fig. 21(a) shows the simulated fundamental voltage and current characteristics of the class-F amplifier with the linear and nonlinear . It shows an interesting result; the amplifier with the nonlinear output capacitor generates higher

fundamental voltage even though the PA is not driven into the highly saturated region. In this low power region, the phase relation between the fundamental and second harmonic currents are in phase. Thus, if we assume that the voltage is generated by the current and load impedance, the proper half-sinusoidal voltage waveform can not be achieved. However, due to the harmonic generation of the nonlinear output capacitor, the PA with the nonlinear capacitor can provide the proper half-sinusoidal voltage shape, increasing the output power and efficiency. The current shaping is achieved through the saturated operation, as shown in Fig. 11(c), with a large load impedance, larger than contrary to the lower load of

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the conventional class-F amplifier. The voltage shaping is mainly accomplished by the nonlinear output capacitor and the harmonic load assists to obtain the optimum efficiency. These behaviors are quite different from the conventional class-F PA. This amplifier is the optimized version at the saturated operation, and we have already introduced these kinds of PAd as a saturated amplifier [3], [19]–[21]. The proper voltage waveform shaping assisted by the output capacitor generates the proper current waveform also, increasing the fundamental current. Thus, the amplifier delivers higher efficiency and output power than the PA with the linear capacitor from the medium to high power levels, as shown in Fig. 21(b). At the maximum power region, the saturated operation itself can generate enough second harmonic current and the two PAs deliver the same performance. Fig. 22 shows the simulated voltage and current waveforms of the class-F amplifier with the linear and nonlinear output capacitors at the input power of 10, 20, and 28 dBm. For the PA with the linear capacitor, due to the improper phase relationship of the currents, the proper voltage waveform is not generated at the low power, leading to the deeply saturated current waveform. However, with the nonlinear output capacitor, the half-sinusoidal voltage waveform is maintained even at the low power. As shown in Fig. 23, the fundamental voltage component of the saturated amplifier is larger than that of the class-F amplifier over the power levels, although the current is somewhat limited. Therefore, the saturated PA outperforms the class-F PA. The gain is higher at a lower power, but is compressed faster. D. Summary In this section, the characteristics of the class-F and class-F amplifiers with the linear and nonlinear capacitors are summarized. The harmonics generated by the nonlinear capacitor significantly change the operational behaviors of the amplifiers. The nonlinear input capacitor enlarges the effective conduction angle, increasing the output power. The efficiency is maintained for the class-F amplifiers, but is decreased for the class-F amplifier, as summarized in Table I. The nonlinear output capacitor generates a large second harmonic voltage with smaller highorder terms. Thus, the class-F amplifiers with the linear and nonlinear output capacitors provide the similar performance, as shown in Fig. 17. However, the tolerance for the harmonic load is increased due to the third harmonic voltage generated by the nonlinear capacitor, and the amplifier with the nonlinear capacitor has a little higher output power and efficiency across the broad third harmonic load impedance, as shown in Fig. 15. Similar to the class-F amplifier, the class-F amplifier with the nonlinear capacitor also has a large tolerance for the second harmonic load, as shown in Fig. 20. Although the class-F amplifier with the linear output capacitor cannot generate the proper half-sinusoidal voltage waveform below the deeply saturated input power level, as shown in Fig. 22, the amplifier with the nonlinear output capacitor can because the capacitor generates the proper second harmonic voltage, forming the half-sinusoidal voltage waveform even at the low input power level. Thus, the amplifier has larger fundamental voltage and current at the low power level, increasing the output power and efficiency, as shown in Fig. 21. Moreover, the fundamental load

Fig. 22. Simulated voltage and current waveforms of class-F PA with linear and nonlinear output capacitors at the input power of: (a) 10 dBm, (b) 20 dBm, and (c) 28 dBm.

should be a lot larger than the tuned load amplifier contrary to the lower load in the conventional wisdom. The deeply saturated operation provides the quasi-rectangle current with a reduced bifurcated current. Since the amplifier takes advantage of the nonlinear output capacitor to shape the voltage waveform, it has large tolerance for the harmonic load. As we described in [3], the second harmonic load at the current source is opened and the third harmonic is shorted by the large output capacitance. The higher order terms have a minor effect on the performance. The operation mechanism of the class-F amplifier, we have discovered thus far, is quite different from the conventional class-F amplifier. This mode of operation is the optimized power operation in the saturated mode, and we call it the saturated amplifier. There are several PAs optimized using the load–pull data in [22] and [23], and those amplifier are the saturated amplifiers, supporting our claim.

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Fig. 24. Simulated efficiencies and power gains of the class-F and saturated amplifiers using a real device.

urated. Due to the larger fundamental load impedance of the saturated amplifier, it has lower maximum current. Thus, compared with the other amplifiers, the saturated amplifier has the heavily compressed gain characteristic, but delivers the higher output power and efficiency, as shown in Fig. 23. These simulation results show that the saturated amplifier is the better suited architecture for the high-efficiency PA at a high frequency. IV. IMPLEMENTATION AND EXPERIMENTAL RESULTS

Fig. 23. Simulated performance comparisons of tuned load PA, class-F PA, and saturated PAs with the input and output nonlinear capacitors. (a) Fundamental voltage and current. (b) Output power. (c) Power gain and efficiency.

Figs. 12 and 21 show the simulated continuous wave (CW) performance of the amplifiers with the linear and nonlinear capacitors, respectively. Since the nonlinear output capacitor generates the proper second harmonic voltage component, the saturated amplifier can have the half-sinusoidal voltage waveform for all input power levels, and the fundamental voltage is larger than those of others. Moreover, the fundamental voltage increases with input power drive although the current level is sat-

In Section III, the class-F and class-F amplifiers with the nonlinear capacitor are investigated. To validate the voltage waveform shaping by the nonlinear output capacitor and the highly efficient operation of the saturated amplifier, we designed and implemented the amplifier at 2.655 GHz using the Cree GaN HEMT CGH40010 packaged device containing a CGH60015 bare die. Since the commercial device model includes the package effects such as the bonding wires, package leads, and parasitics, the simulation is carried out using the bare-chip model to explore the inherent operation of the saturated amplifier. In addition, the saturated amplifier is compared with the class-F amplifier using the bare-chip model. For the implementation, the packaged device containing the bare chip is employed for simulation and to build the amplifier. Fig. 24 shows the simulated efficiencies and power gains of the class-F and saturated amplifiers using the bare-chip model. As expected, the saturated amplifier delivers the improved gain and efficiency characteristic compared to the class-F amplifier. However, the gain compression is not that fast. The efficiency curves for the two PAs are also similar to the previous simulation result in Section III. Fig. 25 shows the second harmonic load–pull contours and time-domain voltage and current waveforms of the saturated amplifier using the bare-chip model. During the simulation, the fundamental and third harmonic loads are set to and , respectively. Due to the harmonic generation of the nonlinear output capacitor, the high efficiency is maintained across the wide second harmonic impedance region. Moreover, even if the input power is low, the half sinusoidal voltage waveform is generated, proving the harmonic generation by the nonlinear output capacitor.

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Fig. 27. Simulated and measured -paramenters.

Fig. 28. Simulated and measured output power, drain efficiency, PAE, and power gain. Fig. 25. Real device simulation results. (a) Second harmonic load–pull contours. (b) Time-domain voltage and current waveforms of the saturated PA.

Fig. 29. Measured ACLR, drain efficiency, and PAE when the implemented PA is excited by m-WiMAX signal.

Fig. 26. Photograph of implemented saturated amplifier.

Fig. 26 shows a photograph of the implemented saturated amplifier. The amplifier is built on an RF-35 substrate with

and thickness of 30 mil. In the experiment, the amplifier is biased at 2.1 V ( mA, conduction angle of about 190 ) at a supplied drain voltage of 28 V. The amplifier provides a maximum power-added efficiency (PAE) of 73.5% at a saturated output power of 41 dBm. Moreover, the well-matched small-signal characteristics between the measurement and simulation are shown in Fig. 27. The simulated and measured output power, efficiency, and gain characteristics for

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Fig. 30. Measured spectras at an average output power of 33.5 dBm before and after linearization. TABLE II LINEARIZATION PERFORMANCE AT AN AVERAGE OUTPUT POWER OF 33.5 dBm FOR m-WIMAX SIGNAL

with smaller high-order terms, the operational behaviors are changed in comparison with the amplifiers with the linear capacitor. The operation of the class-F amplifier with the nonlinear output capacitor is especially quite different from that of the classical class-F PA, in which the voltage shaping is carried out by the large second harmonic voltage. Thus, the class-F amplifier with the nonlinear capacitor has the half-sinusoidal voltage waveform even at the low power level. Compared to the class-F amplifier, the class-F amplifier delivers superior performance due to its larger fundamental voltage. The simulation results lead to the conclusion that the nonlinear output capacitor is important element for the class-F amplifier for the voltage shaping. The class-F amplifier we have defined is quite different from the classical class-F amplifier, which is not clearly defined for practical design, because the voltageshaping mechanisms and the fundamental load are not the same. We have called it the saturated amplifier since this amplifier is the optimized structure for high efficiency. To validate the voltage waveform shaping by the nonlinear output capacitor and the highly efficient operation of the saturated amplifier, we designed and implemented the amplifier at 2.655 GHz. It provides a maximum PAE of 73.5% at a saturated output power of 41 dBm. ACKNOWLEDGMENT

a CW signal are also well matched, as shown in Fig. 28. Fig. 29 depicts the measured adjacent channel leakage ratio (ACLR) and efficiencies for mobile world wide interoperability for microwave access signal with 7.7-dB peak-to-average power ratio and 10-MHz signal bandwidth. The amplifier delivers a PAE of 33.6% at an average output power of 33.5 dBm. To validate potential of the implemented amplifier as a main block of a linear femto-cell application, the linearization of the amplifier is conducted using a digital feedback predistortion technique [24]. Fig. 30 illustrates the measured output spectra before and after the linearization. The ACLRs at the offset frequencies of 5.32 and 6.05 MHz are 49.3 and 50.1 dBc, respectively, which are improvements of 21.6 and 20.9 dB, respectively, at an average output power of 33.5 dBm. The linearization results are summarized in Table II. V. CONCLUSIONS The operational behaviors of the class-F and class-F amplifiers have been analyzed. The analysis are conducted through the numerical description for the current sources and simulations using the simplified transistor models with the linear and nonlinear capacitors. In the numerical description, the output power, efficiency, and gain characteristics of the amplifiers are compared according to the conduction angle. In addition, the optimum load impedances and input overdrive ratios are derived. The numerical analysis is then validated using the simplified real device model. With the nonlinear capacitor, the amplifiers are investigated according to the power level. Since the capacitor generates harmonics, a large second harmonic voltage

The authors would like to thank Cree Inc., Durham, NC, for providing the GaN HEMT transistors and models used in this study. REFERENCES [1] S. C. Cripps, RF Power Amplifiers for Wireless Communications, 2nd ed. Norwood, MA: Artech House, 2006. [2] J. Choi, D. Kang, D. Kim, J. Park, B. Jin, and B. Kim, “Power amplifiers and transimitters for next generation mobile handset,” J. Semicond. Technol. Sci., vol. 9, no. 4, pp. 249–256, Dec. 2009. [3] S. Jee, J. Moon, J. Kim, J. Son, and B. Kim, “Switching behavior of class-E power amplifier and its operation above maximum frequency,” IEEE Trans. Microw. Theory Tech., vol. 60, no. 1, pp. 89–98, Jan. 2012. [4] T. B. Mader and Z. B. Popović, “The transmission-line high-efficiency class-E amplifier,” IEEE Microw. Guided Wave Lett., vol. 5, no. 9, pp. 290–292, Sep. 1995. [5] E. Cipriani, P. Colantonio, F. Giannini, and R. Giofrè, “Optimization of class E power amplifier design above theoretical maximum frequency,” in Proc. 38th Eur. Microw. Conf., Oct. 2008, pp. 1541–1544. [6] E. Cipriani, P. Colantonio, F. Giannini, and R. Giofrè, “Theory and experimental validation of a class E PA above theoretical maximum frequency,” Int. J. Microw. Wireless Technol., vol. 1, no. 4, pp. 293–299, Jun. 2009. [7] A. L. Clarke, M. Akmal, J. Lees, P. J. Tasker, and J. Benedikt, “Investigation and analysis into device optimization for attaining efficiencies in-excess of 90% when accounting for higher harmonics,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2010, pp. 1114–1117. [8] A. Sheikh, C. Roff, J. Benedikt, P. J. Tasker, B. Noori, J. Wood, and P. H. Aaen, “Peak class F and inverse class F drain efficiencies using Si LDMOS in a limited bandwidth design,” IEEE Microw. Wireless Compon. Lett., vol. 19, no. 7, pp. 473–475, Jul. 2009. [9] C. J. Wei, P. DiCarlo, Y. A. Tkachenko, R. McMorrow, and D. Bartle, “Analysis and experimental waveform study on inverse class class-F mode of microwave power FETs,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2000, pp. 525–528. [10] A. Inoue, T. Heima, A. Ohta, R. Hattoru, and Y. Mitsui, “Analysis of class-F and inverse class-F amplifiers,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2000, pp. 775–778. [11] A. Inoue, A. Ohta, S. Goto, T. Ishikawa, and Y. Matsuda, “The efficiency of class-F and inverse class-F amplifiers,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2004, pp. 1947–1950.

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[12] S. Goto, T. Kunii, A. Ohta, A. Inoue, Y. Hosokawa, R. Hattori, and Y. Mitsui, “Effect of bias condition and input harmonic termination on high efficiency inverse class-F amplifiers,” in Proc. 31th Eur. Microw. Conf., Sep. 2010, pp. 1–4. [13] Y. Y. Woo, Y. Yang, and B. Kim, “Analysis and experiments for highefficiency class-F and inverse class-F power amplifiers,” IEEE Trans. Microw. Theory Tech., vol. 54, no. 5, pp. 1969–1974, May 2006. [14] E. Cipriani, P. Colantonio, F. Giannini, and R. Giofrè, “Class F PA: Theoretical aspects,” in Integr. Nonlinear Microw. Millimeter-Wave Circuits Workshop, Apr. 2010, pp. 29–32. [15] E. Cipriani, P. Colantonio, F. Giannini, and R. Giofrè, “Theoretical and PAs,” in Proc. experimental comparison of class F versus class F 40th Eur. Microw. Conf., Sep. 2010, pp. 428–431. [16] J. H. Kim, G. D. Jo, J. H. Oh, Y. H. Kim, K. C. Lee, and J. H. Jung, “Modeling and design methodology of high-efficiency class-F and class-F power amplifiers,” IEEE Trans. Microw. Theory Tech., vol. 59, no. 1, pp. 153–165, Jan. 2011. [17] P. Colantonio, F. Giannini, G. Leuzzi, and E. Limiti, “On the class-F power amplifier design,” Int. J. RF Microw. Comput.-Aided Eng., vol. 9, no. 2, pp. 129–149, Feb. 1999. [18] P. Colantonio, F. Giannini, G. Leuzzi, and E. Limiti, “High efficiency low-voltage power amplifier design by second-harmonic manipulation,” Int. J. RF Microw. Comput.-Aided Eng., vol. 10, no. 1, pp. 19–32, Jan. 2000. [19] J. Moon, J. Kim, and B. Kim, “Investigation of a class-J power amfor optimized operation,” IEEE Trans. plifier with a nonlinear Microw. Theory Tech., vol. 58, no. 11, pp. 2800–2811, Nov. 2010. [20] J. Kim, J. Kim, J. Moon, J. Son, I. Kim, S. Jee, and B. Kim, “Saturated power amplifier optimized for efficiency using self-generated harmonic current and voltage,” IEEE Trans. Microw. Theory Tech., vol. 59, no. 8, pp. 2049–2058, Aug. 2011. [21] J. Moon, S. Jee, J. Kim, and B. Kim, “Investigation of a class F power amplifier with a nonlinear ,” in Proc. 41th Eur. Microw. Conf., Sep. 2011, pp. 124–127. [22] P. Saad, H. M. Nemati, K. Andersoon, and C. Fager, “Highly efficient GaN-HEMT power amplifiers at 3.5 GHz and 5.5 GHz,” in IEEE 12th Annu. Wireless Microw. Technol. Conf., Apr. 2011, pp. 1–4. [23] H. M. Nemati, C. Fager, M. Thorsell, and H. Zirath, “High-efficiency LDMOS power-amplifier design at 1 GHz using an optimized transistor model,” IEEE Trans. Microw. Theory Tech., vol. 57, no. 7, pp. 1647–1654, Jul. 2009. [24] Y. Y. Woo, J. Kim, J. Yi, S. Hong, I. Kim, J. Moon, and B. Kim, “Adaptive digital feedback predistortion technique for linearizing power amplifier,” IEEE Trans. Microw. Theory Tech., vol. 55, no. 5, pp. 932–940, May 2007.

Junghwan Moon (S’07) received the B.S. degree in electrical and computer engineering from the University of Seoul, Seoul, Korea, in 2006, and the Ph.D. degree in electrical engineering from the Pohang University of Science and Technology (POSTECH), Pohang, Gyeongbuk, Korea, in 2012. He is currently a Senior Engineer with the Telecommunication Systems Division, Samsung Electronics Company Ltd., Suwon, Korea. In 2011, he was a Visiting Researcher with the GigaHertz Centre, Microwave Electronics Laboratory, Chalmers University of Technology, Göteborg, Sweden. He has authored or coauthored over 50 papers in international journals and conference proceedings. His current research interests include linear, efficient, and wideband RF PA/transmitter design and digital predistortion (DPD) techniques. Dr. Moon was the recipient of the Highest Efficiency Award of the 2008 Student High-Efficiency Power Amplifier Design Competition, IEEE MTT-S International Microwave Symposium (IMS), the 2011 First Place Award of the Student High-Efficiency Power Amplifier Design Competition, IEEE MTT-S IMS, and the 2012 Best Thesis Award in electrical engineering of POSTECH.

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Seunghoon Jee (S’11) received the B.S. degree in electronic and electrical engineering from Kyungpook National University, Daegu, Korea, in 2009, and is currently working toward the Ph.D. degree at the Pohang University of Science and Technology (POSTECH), Pohang, Gyeongbuk, Korea. His current research interests include highly linear and efficient RF PA design.

Jungjoon Kim (S’10) received the B.S. degree in electrical engineering from Han-Yang University, Ansan, Korea, in 2007, the Master degree in electrical engineering from the Pohang University of Science and Technology (POSTECH), Pohang, Gyeongbuk, Korea, in 2009, and is currently working toward the Ph.D. degree at POSTECH. His current research interests include RF PA design and supply modulator design for highly efficient transmitter systems. Jangheon Kim (S’07–M’09) received the B.S. degree in electronics and information engineering from Chonbuk National University, Chonju, Korea, in 2003, and the Ph.D. degree in electrical engineering from the Pohang University of Science and Technology (POSTECH), Pohang, Gyeongbuk, Korea, in 2009. He is currently a Senior Engineer with the Systems Research and Development Team, Telecommunication Systems Division, Samsung Electronics Company Ltd., Suwon, Korea. From 2009 to 2010, he was a Post-Doctoral Fellow with the University of Waterloo, Waterloo, ON, Canada. He has authored or coauthored over 40 papers in international journals and conference proceedings. His current research interests include highly linear and efficient RF PA design, digital predistortion (DPD) techniques, and highly efficient transmitters for wireless communication systems. Dr. Kim was the recipient of the Highest Efficiency Award of the 2008 Student High-Efficiency Power Amplifier Design Competition of IEEE MTT-S International Microwave Symposium (IMS) and the 2010 MICROWAVE AND WIRELESS COMPONENTS LETTERS Outstanding Reviewer Award. Bumman Kim (M’78–SM’97–F’07) received the Ph.D. degree in electrical engineering from Carnegie Mellon University, Pittsburgh, PA, in 1979. From 1978 to 1981, he was engaged in fiber-optic network component research with GTE Laboratories Inc. In 1981, he joined the Central Research Laboratories, Texas Instruments Incorporated, where he was involved in development of GaAs power field-effect transistors (FETs) and monolithic microwave integrated circuits (MMICs). He has developed a large-signal model of a power FET, dual-gate FETs for gain control, high-power distributed amplifiers, and various millimeter-wave MMICs. In 1989, he joined the Pohang University of Science and Technology (POSTECH), Pohang, Gyeongbuk, Korea, where he is a POSTECH Fellow and a Namko Professor with the Department of Electrical Engineering, and Director of the Microwave Application Research Center, where he is involved in device and circuit technology for RF integrated circuits (RFICs). He has authored over 300 technical papers. Prof. Kim is a member of the Korean Academy of Science and Technology and the National Academy of Engineering of Korea. He was an associate editor for the IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, a Distinguished Lecturer of the IEEE Microwave Theory and Techniques Society (IEEE MTT-S), and an Administrative Committee (AdCom) member.

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A Simplified Broadband Design Methodology for Linearized High-Efficiency Continuous Class-F Power Amplifiers Neal Tuffy, Student Member, IEEE, Lei Guan, Student Member, IEEE, Anding Zhu, Member, IEEE, and Thomas J Brazil, Fellow, IEEE

Abstract—This paper describes the design approach employed for achieving approximated continuous Class-F power amplifier (PA) modes over wide bandwidths. The importance of the nonlinear device capacitance for wave-shaping the continuous Class-F voltage and current waveforms is highlighted, thus reducing the device sensitivity to second and third harmonic impedance terminations. By identifying the high-efficiency regions on the reactance plane for harmonic band placement, the design can be reduced to a fundamental matching problem. The distributed simplified real frequency technique synthesis algorithm can then be utilized to achieve wideband operation. Using a 10-W Cree GaN HEMT device, greater than 70% efficiency has been measured over a 51% bandwidth from 1.45 to 2.45 GHz, with output powers of 11–16.8 W. The nonlinear PA was then linearized using digital predistortion with 20-MHz long-term evolution and 40-MHz eight-carrier W-CDMA excitation signals, to attain adjacent channel power ratios below 53 and 49 dBc, respectively. To the best of the authors’ knowledge, the measured results represent the best performance obtained from a broadband switch-mode PA, and the best linearized switch-mode performance using 20and 40-MHz modulated signals. Index Terms—Broadband, Class-F, digital predistortion (DPD), high efficiency, power amplifier (PA).

I. INTRODUCTION

H

IGH-EFFICIENCY power amplifiers (PAs) have received widespread interest recently due to the drive towards lower operational costs in basestation transceivers. Fourth-generation (4G) wireless systems, such as long-term evolution (LTE)-advanced, require high data rates, which utilize large bandwidths of up to 100 MHz. These demands impose great difficulty on designing PAs to meet stringent bandwidth and efficiency specifications, while simultaneously conforming to spectral mask and in-band distortion requirements. Recently, elaborate solutions using envelope tracking and Doherty PAs have been explored [1]–[3], while incorporating digital predistortion (DPD) for highly linear efficient operation [4]–[6]. Manuscript received September 09, 2011; revised December 02, 2011; accepted December 14, 2011. Date of publication March 07, 2012; date of current version May 25, 2012. This work was supported by the Science Foundation Ireland under the Principal Investigator Award scheme. The authors are with the School of Electrical, Electronic and Communications Engineering, University College Dublin, Dublin 4, Ireland (e-mail: neal. [email protected]; [email protected]; [email protected]; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2012.2187534

However, both architectures possess intrinsic bandwidth limitations that have been only moderately overcome [7], [8]. PAs operating in the switch-mode domain exploit the nonlinear region of the device to impose a highly efficient set of nonoverlapping current and voltage drain waveforms. For example, Class-F operation [9] describes an infinite set of fundamental and harmonic impedances to present to the device, which produce nonoverlapping square-wave voltage and halfsinusoidal current drain waveforms. From practical considerations, only a small number of harmonics can be controlled, resulting in a reduction of the maximum obtainable efficiency from 100%. At RF, the parasitics of the device become significant and they must therefore be resonated out to present the required impedances at the internal current generator plane. Retransmission lines alization typically involves the use of for presenting the precise harmonic impedances. The inclusion of sensitive harmonic resonators then results in an increase of the network factor, corresponding to narrowband operation. The inherent narrowband performance of the Class-F amplifier restricts its potential for integration within wideband or multiband transceivers. The Class-J amplifier has recently been proposed [10] to alleviate the precise harmonic shorting requirements of the Class-B (or Class-AB) amplifier. The Class-J principle was then extended to the Class-F amplifier for circumventing its innate narrowband behavior, and termed the continuous Class-F [11] amplifier. The continuous Class-F amplifier offers a wide range of voltage waveforms (which all deliver Class-F performance) that can be dynamically exploited across a desired bandwidth. The need for harmonic shorting is then eliminated, thus obviating the necessity for narrowband harmonic resonators. The device parasitics then become an integral part of the matching network and collaborate with the external matching network to manipulate the waveforms over the band of interest, to deliver broadband and highly efficient PA performance. The main purpose of this paper is to present a design approach for simplifying the matching procedure in broadband continuous Class-F amplifier design. Continuous Class-F studies to date have focused on lower frequencies [11]–[13], whereas this design extends the operation to incorporate commercial third-generation (3G) and 4G bands. By employing suitable output power back off (OPBO), aided with a robust linearization methodology such as DPD, the designed PA delivers high linearity with modulated signals. Furthermore, it will be shown for the first time that linearized switch-mode

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PA performance can exceed modern Doherty PA results with wideband excitation signals at 2.14 GHz. In this paper, Section II derives the ideal continuous Class-F amplifier waveforms and impedance conditions. Section III elaborates on previous work [14] to establish the criteria for approximated continuous Class-F operation, and the importance of the nonlinear drain–source device capacitance in waveform shaping. The high-efficiency regions on the harmonic reactance plane are identified and the simplified real frequency technique (SRFT) [15] synthesis algorithm is employed to design over a wide bandwidth in Section IV. In Section V, measurements on the fabricated PA reveal greater than 70% efficiency with at least 11 W of output power over the 1.45–2.45-GHz bandwidth. When the obtained peak efficiency is appropriately high, Section VI demonstrates the efficient operation of the switch-mode PA with modulated excitations. Conclusions are presented in Section VII.

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generalized voltage drain waveform composed of all frequencies up to the fourth harmonic, while ensuring no power is dissipated at the harmonics

(3) Noting that the even function given by (2) has two zeros at in the range , the Rhodes singularity condition [16] can be exploited to determine the optimum coefficients that satisfy (3). This gives rise to a system of linear-dependent equations, which can be expressed as follows:

II. CONTINUOUS CLASS-F THEORY A. Class-F Amplifier

(4)

The Class-F amplifier achieves highly efficient power amplification by saturating the device and manipulating the generated harmonics in such a manner as to produce nonoverlapping drain waveforms. Class-F operation requires open-circuit terminations at odd harmonics, with short-circuit terminations at the even harmonics. By choosing a Class-B bias point, a half-sinusoidal drain current waveform is formed, given by (1) as follows with a resulting square-wave drain voltage waveform:

By computing the row reduced echelon form of (4), system (5) is found as follows:

(1) The ideal Class-F waveforms give 100% efficiency in conversion of dc to fundamental frequency power, as no harmonic power can be generated. In practice, control of up to the third harmonic is customary, as the benefit of further harmonic control typically produces negligible efficiency improvements. To analyze the Class-F performance, the normalized drain voltage waveform can be expressed as follows [10]:

The above under-determined system can then be used to extract the coefficient values by employing the parameterization . This results in and . The drain voltage waveform can then be expressed as a function of the parameter

(2)

(6)

The above equation represents a voltage waveform that uniquely delivers maximum power with 90.7% efficiency. Imposing this exact waveform at the current generator plane of the device requires precise tuning to compensate for the device parasitics at RF. This sole set of current and voltage waveforms for maximum power and efficiency can usually only be realized at a single frequency, resulting in performance degradation over a broad bandwidth.

, at which point Class-F performance is maintained up to the voltage waveform drops below zero, which requires the dc component to be increased, therefore compromising efficiency. This waveform provides a degree of freedom , which can be used over a bandwidth to maintain maximum power and efficiency. A factorization can be performed to arrive at the form presented in [11]

B. Continuous Class-F Amplifier Continuous Class-F operation describes a range of solutions that all deliver the same power and efficiency as in the Class-F case. This family of solutions can be found by starting with a

(5)

(7) The tradeoff, in comparison to Class-F, is seen as an increase in the magnitude of the drain voltage waveform (from normalized amplitude of 2 to a maximum of 3.37), which is shown in Fig. 1.

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Fig. 1. Continuous Class-F waveforms for

.

Fig. 2. Efficiency as a function of nent.

Although, by utilizing high breakdown voltage device technologies such as GaN, such large voltage waveform excursions can be sustained. To exploit these modes over a desired bandwidth, it then becomes necessary to determine the required frequency-domain impedances as varies. The load impedance to be presented at each harmonic can be expressed as (8) where denotes the th frequency component. Defining as the Class-B optimum fundamental load impedance, it is given by (9) as follows: (9)

The harmonic impedances are then found by substituting (1) and (6) into (8) as follows:

(10) It is seen from (10) that the fundamental, second, and fourth harmonic impedances are dependent on the parameter , whereas the third harmonic remains at a constant open circuit. These demanding impedance conditions for continuous Class-F operation requires further investigation to understand how performance degradation can be minimized with imprecise harmonic terminations. III. APPROXIMATED CONTINUOUS CLASS-F MODES The requirement, given by (10), to present the exact impedance terminations over four frequency bands becomes unfeasible in practice. It is therefore necessary to devise a strategy to approximate the continuous Class-F modes over the band of interest.

without fourth harmonic voltage compo-

A. Neglecting the Fourth Harmonic Impedance Requirement The first approach is to analyze the consequence of neglecting the fourth harmonic band impedances. By disregarding the fourth harmonic component in the continuous Class-F drain voltage waveform, the efficiency can be calculated as the parameter varies. The result is shown in Fig. 2 where the efficiency is seen to be maximum for Class-F and reduces with increasing , as expected from (10). The loss in efficiency is 4.5% in the worst case, which justifies omitting the fourth harmonic band impedance condition. When exploiting the nonlinear , it will be shown that it can dominate the harmonic band response, thus the need for precise fourth harmonic terminations becomes redundant. B. Analysis of Nonlinear Device Output Capacitance It was shown in [17] that for obtaining high efficiency in the Class-J case, the nonlinear device output capacitance can circumvent the need for a highly precise second harmonic termination. It was therefore necessary to test the continuous Class-F case with nonlinear device output capacitance to predict if the demanding third harmonic band open-circuit requirement could be relaxed, and if the overall high sensitivity to harmonic terminations could be alleviated. The nonlinear capacitance profile given in [17] was used in accordance with the parasitic model extracted in [18] and is shown in Fig. 3. is then given by

[pF] (11) This model offers an approximated large-signal model for the 10-W Cree CGH40010FE GaN HEMT device, and assists in understanding the design tradeoffs for continuous Class-F broadband operation. The model also permits convenient access to the internal drain terminal, which provides the time-domain voltage and current waveforms. By comparing the nonlinear with its linear small-signal counterpart, an insight can be obtained into its importance in shaping the drain waveforms, thus reducing the dependency on

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Fig. 3. Approximated large-signal device model [17], [18].

precise package plane terminations. Using Agilent’s ADS 2009, harmonic load–pull was performed on the device to determine continuous Class-F operation with nonlinear and linear . The 3-D reactance plane plots shown in Figs. 4 and 5 were generated by sweeping the harmonic reactances while maintaining the optimum fundamental impedance of at 2.45 GHz. It is evident that when considering both power and efficiency, the linear exhibits far greater sensitivity to inaccuracies in harmonic terminations. By imposing the information from both sets of 3-D plots, a contour plot was created, which illustrates the contours for 80% efficiency and 10-W power. The choice of 10 W as the minimum output power ensures a high power utilization factor (PUF) [10] from the 10-W device. The shaded region represents the areas on the reactance plane where the desired design criteria of greater than 10 W of output power and 80% drain efficiency (DE) are satisfied. For the nonlinear , about 65% of the shown reactance plane delivers the required performance, whereas only about 20% of the linear reactance plane meets the desired specifications. To understand how the nonlinear provides superior results with harmonic reactance variation, it is necessary to look at the voltage and current drain waveforms and their corresponding frequency components. Referring to Fig. 6(a), the current generator plane waveforms are seen in continuous Class-F operation for both linear and nonlinear . Firstly, it is observed that the magnitude of the drain voltage waveform with nonlinear exceeds the linear case by about 15 V. The current waveform with nonlinear also appears to exhibit a “squared” type appearance in comparison to the linear current waveform. Fig. 6(b) presents the frequency-domain impedances up to the third harmonics of the waveforms. With a linear , an open circuit is presented at the third harmonic, which generates minimal third harmonic component in the current waveform. As the appropriate reactive termination is presented at the second harmonic, the resulting waveforms appear strongly correlated with the ideal waveforms of Fig. 1. Considering the waveforms with nonlinear , it is seen that the open-circuited third harmonic requirement is not met. Also, it is observed that the nonlinear gives a negative resistance at the harmonics, which arises due to the frequency generating property of the nonlinear capacitance. This ensures a prominent third harmonic component of current that shapes the current toward a square wave, thus reducing waveform overlap and improving efficiency. The second harmonic impedance also has a large magnitude in comparison to the linear waveform due to a significant reduction in the second harmonic current component and an increase in second harmonic voltage component. This increase in second harmonic

Fig. 4. Variation of DE and output power over the second and third harmonic . reactance plane with linear

voltage causes an enlargement in the overall magnitude of the drain voltage waveform. Fig. 6(b) also demonstrates that the nonlinear acts to reduce the phase difference between the fundamental current and voltage. This implies a decrease in reactive power and an increase in the output power extracted from the device. By exploiting the innate nonlinear of the device, approximated continuous Class-F modes can be utilized that are far less sensitive to harmonic terminations, as the nonlinear supplies a high degree of favorable waveform shaping. This principle has important implications for the design of high-efficiency broadband amplifiers. By restricting the harmonic band

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Fig. 6. (a) Simulated time-domain waveforms and (b) harmonic impedances . for continuous Class-F operation with linear and nonlinear

Fig. 5. Variation of DE and output power over the second and third harmonic . reactance plane with nonlinear

reactance roll-off to the high-efficiency regions of the reactance plane, the design complexity is reduced to that of a fundamental band matching problem. IV. BROADBAND CONTINUOUS CLASS-F SYNTHESIS AND DESIGN To realize the approximated continuous Class-F modes, the performance degradation with varying fundamental impedance terminations must be analyzed across the band. The sensitivity of the fundamental impedance terminations with predefined harmonic band reactance roll-offs were initially investigated by producing the load–pull, power, and efficiency contours from

1.45 to 2.45 GHz. Fig. 7 shows a set of contours, which result from merging the power and efficiency contours, and give the optimum fundamental impedances to present to the device package plane across the bandwidth. The contours were produced by adhering to the design criteria of 41 dBm of output power and 80% DE. This offers a design margin of 10% efficiency and 1 dB of output power. The contours are seen to diminish in area as frequency increases, indicating the need for greater precision at the higher end of the band. To supply the required precise fundamental impedances and controlled harmonic band reactance roll-off, the distributed SRFT algorithm can then be employed for the design of the matching networks. A. Distributed Network Synthesis via SRFT The SRFT synthesis algorithm was first proposed by Yarman and Carlin [15], which established a computationally efficient solution to the earlier work by Carlin and Komiak [19]. Initial forms of the SRFT focused on lumped LC network synthesis that were then subsequently modified for distributed synthesis involving commensurate transmission lines [20]. The core principle of the SRFT involves formulating the synthesis problem in such a manner as to produce an objective function that is quadratic in its unknowns, and is therefore convergent under

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harmonic band reactances to lie within the designated high-efficiency regions of the reactance plane. The -parameters for a lossless two-port matching network constructed with commensurate transmission lines can then be established as a function of . Ensuring the network is free from finite transmission zeros, the -parameters are given by

(15)

where is the total number of zeros at dc and is the total number of cascaded sections. The TPG can then be reformulated in terms of by using (12) and (15), with the substitution

Fig. 7. Merged output power and efficiency contours representing 80% efficiency and 41dBm of output power over the 1.45–2.45-GHz bandwidth.

(16) The coefficients of the polynomial are initialized and is chosen. The polynomial is then found using (17), which was determined via the lossless condition [21] (17)

Fig. 8. Matching network to maximize TPG from device to a 50-

load.

nonlinear optimization. The distributed form of the SRFT offers accurate fundamental band impedance realization and direct control of harmonic band reactance roll-off. In comparison, lumped synthesis usually requires conversion to a distributed network for fabrication at RF, which presents great difficulty in simultaneously obtaining the desired harmonic band responses. To quantify the quality of the match between the deviceunder-test (DUT) and the 50- load over the band, we can introduce the transducer power gain (TPG). Referring to Fig. 8, the TPG can be expressed as follows: (12) The complex Richard variable

can be defined as follows: (13)

where the constant delay

is set as (14)

represents the highest frequency In the above equation, for optimization and the variable can be set by the designer for controlling the electrical length of the commensurate transmission lines. This parameter can then be chosen to restrict the

Careful numerical construction of the strictly Hurwitz polynomial is required, which is formed by the left-half plane (LHP) roots of . The TPG is then uniquely defined and can then be maximized across the band by nonlinear optimization of the coefficients of , which are quadratic in its unknowns. When the optimum coefficients are identified, the relationship can be used to determine of the optimum matching network. Synthesis of the network can then be performed using normalization change and Richard extractions [21]. This determines the characteristic impedances of the commensurate lines in a sequential manner for the optimum output match. A similar procedure can also be followed to provide the optimum input match for maximizing the performance across the band of interest. By identifying the power and efficiency contours that adhere to the design goals, the SRFT algorithm can then be used to provide the optimum matching networks. B. Transmission Line Continuous Class-F PA Realization To obtain maximum benefits from using the SRFT algorithm, the optimum impedances must be carefully selected. Choosing the desired impedances close to the center of the contours in Fig. 7 permits maximum variation in impedance terminations. Although care must be taken to chose the Smith Chart impedance trajectory such that clockwise phase rotation occurs with increasing frequency. This condition arises due to passive distributed networks always producing clockwise phase rotation on the Smith chart [22]. By selecting the desired impedances comfortably inside the contours while simultaneously presenting a smooth clockwise impedance trajectory, the SRFT algorithm can produce optimum results. Fig. 9 shows the resulting circuit from utilizing the SRFT algorithm. A frequency of 2 GHz was used to specify the shown characteristic

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Fig. 9. Distributed amplifier designed via distributed SRFT synthesis algorithm.

Fig. 10. Input and output matching network impedances at the package plane.

impedances and electrical lengths. It is seen that the first line on the input match is not commensurate, and was incorporated to minimize the discontinuity between the device tab and the circuit. This allows for greater precision in predicting the impedance presented to the device when converted to microstrip. The parameter was chosen at 0.38 to produce an output harmonic band reactance roll-off, which remains within the high-efficiency regions. The input harmonic band terminations were found to have minimal effect on the efficiency so the primary concern was given to accuracy in fundamental input matching. It was also necessary to ensure the characteristic impedance of the lines do not exceed the chosen bounds of . This gave practical dimensions for microstrip fabrication, based on the RF35 board parameters and frequency of operation. Fig. 10 shows the matching network impedance trajectories on the Smith chart, where the output match lies inside the contours across the fundamental band with the harmonic band trajectory remaining in the high-efficiency region. Thus, the design goals are obtained across the 50% bandwidth, as shown in Fig. 11. V. FABRICATION AND EXPERIMENTAL TESTS Firstly, the distributed circuit shown in Fig. 9 was converted to microstrip for fabrication and testing. Upon transformation to microstrip, it was necessary to tune the length of the lines to compensate for large discontinuities between high and low characteristic impedances. Careful monitoring of the second and third harmonic band reactance roll-off when tuning ensured they did not enter the low-efficiency regions. Bias networks were incorporated into the circuit at points where minimal impact on

Fig. 11. Simulated results obtained from the designed distributed amplifier.

the fundamental band impedance and harmonic band reactance roll-off occurred. Stability networks were also integrated into the layout to prevent low-frequency oscillations. The layout of the final amplifier is shown in Fig. 12. Figs. 13 and 14 display the measured impedances presented by the input and output microstrip matching networks. The losses over the higher third harmonic band frequencies in the output match are greater than expected, due to large resonances occurring from the wide lines. However, the presented third harmonic terminations lie in the high-efficiency region of the reactance plane while providing sufficiently high impedance to allow the nonlinearity to shape the waveforms advantageously and maintain high performance. The commercially available 10-W Cree CGH40010FE GaN HEMT packaged device was used for implementation. A gate bias of 3.2 V was chosen, giving a quiescent current of 10 mA with the drain bias set at 28 V. A Taconic RF35 board was selected with a board thickness of 1.52 mm, a copper thickness of 35 m, and an . The PA was tested with continuous wave (CW) excitation from 1.45–2.45 GHz and the results are illustrated in Fig. 15. It can be seen that greater than 70% efficiency is obtained from 1.45–2.45 GHz giving a bandwidth of 51%. The maximum efficiency measured across the band is 81% at 1.7 GHz with a maximum power-added efficiency (PAE) of 74.6% at 1.6 GHz. Across the band at least 11 W of power is delivered with a maximum power of 16.8 W, corresponding to 40.4–42.2 dBm. Gain between 10–12.6 dB was also measured. Fig. 16 shows a picture of the final PA. A comparison with similar contemporary state-of-the-art broadband PA results is outlined in Table I, and it is evident this work surpasses the others

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Fig. 12. Final amplifier layout.

VI. LINEARITY IMPROVEMENT WITH WIDEBAND MODULATED EXCITATION SIGNALS

Fig. 13. Measured input matching network impedances of the final amplifier.

To validate the potential of the switch-mode PA for use with modulated excitations, it was then necessary to explore its capability for linearization by applying DPD. Fig. 17(a) shows the load lines of the amplifier at 2.14 GHz under different levels of output power back-off (OPBO). It is seen that the PA exits the nonlinear switching region after approximately 3 dB of OPBO, corresponding to a linearity improvement while maintaining high efficiency at 66%, as shown in Fig. 17(b). This demonstrates the potential for switch-mode PAs to deliver excellent performance with amplitude modulated signals due to the high peak efficiency. For accommodating the 6.5-dB peak-to-average power ratio (PAPR) of the proposed excitation signals, approximately 6.5 dB of OPBO is required, which corresponds to a DE of 42% with a CW drive signal, as shown in Fig. 17(b). Due to its moderate implementation complexity and excellent linearization performance, DPD has been largely used for improving the linearity of PAs. In order to linearize the designed continuous Class-F PA, in this paper, we use the simplified second-order dynamic deviation reduction-based Volterra series model proposed in [23]. The predistortion testbench was set up as shown in Fig. 18. Initially, a baseband in-phase/quadrature (I/Q) complex signal was created in MATLAB, and fed to the baseband and RF boards to modulate and up-convert to the RF frequency. The modulated RF signal was finally then sent to the PA. At the output, the RF signal was down-converted and demodulated to baseband for DPD coefficient extraction [24]. The baseband I/Q data sampling rate was set at 368.64 Msamples/s. A. DPD With 20-MHz Single-Carrier LTE Signal

Fig. 14. Measured output matching network impedances of the final amplifier.

in terms of frequency of operation, output power, and DE across the band.

In the first test, a 20-MHz single-carrier LTE signal was used to excite the designed continuous Class-F PA. The memory length parameter and the order of the nonlinearity for DPD were set as and (48 coefficients in total). The linearization performance can be evaluated in both the time and frequency domains. The time-domain AM/AM and AM/PM characterization plots are shown in Fig. 19, where it can be seen that both the static nonlinearities and memory effects are almost completely removed after linearization. In the frequency domain, the continuous Class-F PA output spectra

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Fig. 15. Measured results of the final amplifier from 1.45 to 2.45 GHz.

Fig. 16. Photograph of final continuous Class-F PA.

TABLE I COMPARISON WITH STATE-OF-THE-ART BROADBAND PAs

with and without predistortion are shown in Fig. 20, where we can see the spectral regrowth has been significantly reduced. Furthermore, the adjacent channel power ratio (ACPR), normalized root mean square error (NRMSE) [25], output power, and DE before and after DPD are listed in Table II. From Table II, we can see that after application of the DPD, the ACPR at 20-MHz offset is reduced from 30.1 and 29.1 dBc to 53.7 and 53.1 dBc, whereas at 40-MHz offset the reduction in ACPR is from 53.4 and 53.8 dBc to 55.7 and 55.5 dBc. The NRMSE is substantially improved from 8.44% to 1.05%. Though the output power and DE suffer minor loss (around 0.3% loss), the linearity has been significantly improved (around 25-dB improvement at first adjacent ACPR) by the DPD. As a result, the designed PA can supply 35.77 dBm of output power with 46.2% DE, resulting in

Fig. 17. (a) Continuous Class-F loadlines at 2.14 GHz with OPBO. (b) PA efficiency variation with OPBO at 2.14 GHz.

ACPR below respectively.

53 and

55 dBc at

20 and

40-MHz offset,

B. DPD With 40-MHz Multicarrier W-CDMA Signal Utilizing excitation signals with wider bandwidths implies a further degradation in ACPR, which significantly increases the difficulty in meeting the demanding linearity requirements. To further evaluate the performance of the designed continuous Class-F PA with linearization, a 40-MHz eight-carrier

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TABLE II LINEARIZATION PERFORMANCE FOR 1C-LTE SIGNAL

Fig. 18. Predistortion testbench setup.

Fig. 19. AM/AM and AM/PM plots for 20-MHz signal carrier LTE signal with and without DPD.

Fig. 21. AM/AM and AM/PM plots for 40-MHz eight-carrier WCDMA signal with and without DPD.

can be achieved with ACPR down to 49.7 and 49.4 dBc at 5-MHz offset, with 52.1 and 52.3 dBc at 10-MHz offset. The NRMSE is reduced from 10.77% to 1.44%. Though the bandwidth of eight-carrier W-CDMA is double that of LTE signal used in the first test, the designed PA can supply 35.41 dBm of output power and 46% DE with ACPR below 49 and 52 dBc at 5- and 10-MHz offset, respectively. Fig. 20. PA output spectra for 20-MHz LTE signal with and without DPD.

W-CDMA signal was used as excitation to the PA. The nonlinear order and memory length was set as and (73 coefficients in total). By similarly illustrating the linearization performance in the time domain, the AM/AM and AM/PM plots are shown in Fig. 21, where we can see that the PA suffers from stronger nonlinearities and longer memory effects as expected. After employing the DPD, the nonlinearity has been largely alleviated. In the frequency domain, the spectra of the PA output are shown in Fig. 22 with ACPR, NRMSE, output power, and DE listed in Table III. As expected, the ACPR performance without linearization is considerably worse with the 40-MHz drive signal, only 25.6 and 24.9 dBc at 5-MHz offset, whereas 26.1 and 26.7 dBc at 10-MHz offset were obtained. After employing DPD, an improvement of 25 dB

C. Continuous Class-F and Doherty PA Comparison Although the continuous Class-F PA operates in the highly nonlinear switch-mode region with peak drive, it has been shown to be linearizable and surpass the spectral mask requirements under modulated excitation. The linearized results with 20-MHz LTE and 40-MHz eight-carrier W-CDMA signals merits a comparison with a selection of comparable state-of-the-art linearized PAs, as shown in Table IV. This indicates similar results in terms of linearity and efficiency between the Doherty and continuous Class-F PAs under modulated signal drive. The designed PA was also the only amplifier reported in Table IV that was completely linearized over a 40-MHz bandwidth, while still delivering excellent efficiency performance. The superior bandwidth performance of the continuous Class-F provides a major advantage over the Doherty architecture as it is not limited by narrowband quarter-wave transformers. Also, the reduction in circuit complexity and ease

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Fig. 22. PA output spectra for 40-MHz eight-carrier WCDMA signal with and without DPD.

TABLE III LINEARIZATION PERFORMANCE FOR EIGHT-CARRIER WCDMA SIGNAL

TABLE IV HIGH EFFICIENCY LINEAR MODULATED PA COMPARISON

of design makes the continuous Class-F PA more attractive than its Doherty counterpart. VII. CONCLUSION The continuous Class-F amplifier has been analyzed to develop a strategy for alleviating the demanding impedance requirements, and to provide approximated continuous Class-F operation over wide bandwidths. The nonlinear was seen to be critical in shaping the waveforms and reducing the sensitivity of the amplifier performance to variations in second and third

harmonic band reactances. This reduced the complexity of the design to that of a fundamental matching problem. The SRFT distributed synthesis algorithm provides a powerful tool for then accurately realizing desired fundamental impedances across a band while simultaneously providing optimum harmonic band reactance roll-off. Measurements of the fabricated amplifier reveal greater than 70% DE with at least 11 W of output power from 1.45 to 2.45 GHz, representing a 51% bandwidth. Linearization was accomplished with a 20-MHz LTE signal and a 40-MHz eight-carrier W-CDMA signal at 2.14 GHz, which both exceeded the spectral emissions mask and in-band distortion requirements. Drain efficiencies of 46%, with greater than 35 dBm of output power were obtained in both cases, which were shown to outperform similar contemporary Doherty PA results. The vastly superior bandwidth performance of this amplifier and its relatively simple circuit design demonstrates a robust PA for modern high-efficiency linear transceiver architectures in wideband or multiband operation. REFERENCES [1] D. F. Kimball et al., “High-efficiency envelope tracking W-CDMA base-station amplifier using GaN HFETs,” IEEE Trans. Microw. Theory Tech., vol. 54, no. 11, pp. 3848–3856, Nov. 2006. [2] J. Moon, J. Kim, J. Kim, I. Kim, and B. Kim, “Efficiency enhancement of Doherty amplifier through mitigation of the knee voltage effect,” IEEE Trans. Microw. Theory Tech., vol. 59, no. 1, pp. 143–152, Jan. 2011. [3] A. Z. Markos, K. Bathich, F. Golden, and G. Boeck, “A 50 W unsymmetrical GaN Doherty amplifier for LTE applications,” in Proc. 40th Eur. Microw. Conf., Sep. 28–30, 2010, pp. 994–997. [4] J. Kim et al., “Analysis of a fully matched saturated Doherty amplifier with excellent efficiency,” IEEE Trans. Microw. Theory Tech., vol. 56, no. 2, pp. 328–338, Feb. 2008. [5] M. Lee, Y. Lee, S. Kam, and Y. Jeong, “Optimum bias for highly linear and efficient Doherty power amplifier with memoryless digital predistortion,” in Proc. 39th EuMC 2009, Sep. 2009, pp. 1441–1444. [6] S. Jung, O. Hammi, and F. M. Ghannouchi, “Design optimization and DPD linearization of GaN-based unsymmetrical Doherty power amplifiers for 3G multicarrier applications,” IEEE Trans. Microw. Theory Tech, vol. 57, no. 9, pp. 2105–2113, Sep. 2009. [7] M. Sarkeshi, O. Leong, and A. van Roermund, “A novel Doherty amplifier for enhanced load modulation and higher bandwidth,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2008, pp. 763–766. [8] D. Kang et al., “A multimode/multiband power amplifier with a boosted supply modulator,” IEEE Trans. Microw. Theory Tech., vol. 58, no. 10, pp. 2598–2608, Oct. 2010. [9] H. L. Krauss, C. W. Bostain, and F. H. Raab, Solid State Radio Engineering. New York: Wiley, 1980. [10] S. C. Cripps, RF Power Amplifier for Wireless Communication, 2nd ed. Norwood, MA: Artech House, 2006. [11] V. Carrubba et al., “The continuous class-F mode power amplifier,” in Proc. 40th Eur. Microw. Conf., Sep. 2010, pp. 432–435. [12] V. Carrubba, J. Lees, J. Benedikt, P. J. Tasker, and S. C. Cripps, “A novel highly efficient broadband continuous class-F RFPA delivering 74% average efficiency for an octave bandwidth,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 5–10, 2011, pp. 1–4. [13] V. Carrubba et al., “On the extension of the continuous class-F mode power amplifier,” IEEE Trans. Microw. Theory Tech., vol. 59, no. 5, pp. 1294–1303, May 2011. [14] N. Tuffy, A. Zhu, and T. J Brazil, “Novel realisation of a broadband high-efficiency continuous class-F power amplifier,” in IEEE Eur. Microw. Conf., Oct. 2011, pp. 120–123. [15] B. S. Yarman and H. J. Carlin, “A simplified “real frequency” technique applied to broadband multistage microwave amplifiers,” IEEE Trans. Microw. Theory Tech, vol. MTT-30, no. 12, pp. 2216–2222, Dec. 1982. [16] J. D. Rhodes, “Output universality in maximum efficiency power amplifiers,” Int. J. Theoretical Appl., vol. 31, pp. 385–405, 2003. [17] J. Moon, J. Kim, and B. Kim, “Investigation of a class-J power amplifor optimized operation,” IEEE Trans. Mifier with a nonlinear crow. Theory Tech., vol. 58, no. 11, pp. 2800–2811, Nov. 2010.

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[18] P. J. Tasker and J. Benedikt, “Waveform inspired models and the harmonic balance emulator,” IEEE Microw. Mag., vol. 12, no. 2, pp. 38–54, Apr. 2011. [19] H. J. Carlin and J. J. Komiak, “A new method of broadband equalization applied to microwave amplifiers,” IEEE Trans. Microw. Theory Tech., vol. MTT-27, no. 2, pp. 93–99, Feb. 1979. [20] B. S. Yarman and A. Aksen, “An integrated design tool to construct lossless matching networks with mixed lumped and distributed elements,” IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 39, no. 9, pp. 713–723, Sep. 1992. [21] B. S. Yarman, Design of Ultra Wideband Power Transfer Networks. New York: Wiley, 2010. [22] D. Y.-T. Wu et al., “Design of a broadband and highly efficient 45 W GaN power amplifier via simplified real frequency technique,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2010, pp. 1090–1093. [23] L. Guan and A. Zhu, “Simplified dynamic deviation reduction-based Volterra model for Doherty power amplifiers,” in IEEE Int. Integr. Nonlinear Microw. Millimeter-Wave Circuits Workshop, Vienna, Austria, Apr. 2011, pp. 1–4. [24] L. Guan and A. Zhu, “Dual-loop model extraction for digital predistortion of wideband RF power amplifiers,” IEEE Microw. Wireless Compon. Lett., vol. 21, no. 9, pp. 501–503, Sep. 2011. [25] A. Zhu, P. J. Draxler, J. J. Yan, T. J. Brazil, D. F. Kimball, and P. M. Asbeck, “Open-loop digital predistorter for RF power amplifiers using dynamic deviation reduction-based Volterra series,” IEEE Trans. Microw. Theory Tech., vol. 56, no. 7, pp. 1524–1534, Jul. 2008. [26] H. Xu et al., “A high-efficiency class-E GaN HEMT power amplifier at 1.9 GHz,” in IEEE Microw. Wireless Compon. Lett., Jan. 2006, vol. 16, no. 1, pp. 22–24. [27] P. Wright, J. Lees, J. Benedikt, P. J. Tasker, and S. C. Cripps, “A methodology for realizing high efficiency class-J in a linear broadband PA,” IEEE Trans. Microw. Theory Tech., vol. 57, no. 12, pp. 3196–3204, Dec. 2009. [28] M. P. van der Heijden, M. Acar, and J. S. Vromans, “A compact 12-watt high-efficiency 2.1–2.7 GHz class-E GaN HEMT power amplifier for base stations,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2009, pp. 657–660. [29] J. Wang, Y. Xu, and X. Zhu, “Digital predistorted inverse class-F GaN PA with novel PAPR reduction technique,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 5–10, 2011, pp. 1–1.

Neal Tuffy (S’12) received the B.E. degree in electronic engineering from University College Dublin, Dublin, Ireland, in 2006, and is currently working toward the Ph.D. degree at University College Dublin. He is currently with the RF and Microwave Research Group, University College Dublin. His research interests include waveform engineering techniques, particularly for the design and fabrication of high-efficiency broadband PAs.

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Lei Guan (S’09) received the B.E. and M.E. degrees in electronic engineering from the Harbin Institute of Technology, Harbin, China, in 2006 and 2008, respectively, and is currently working toward the Ph.D. degree at University College Dublin. He is currently with the RF and Microwave Research Group, University College Dublin. His research interests include linearization and system-level modeling of RF/microwave PAs with an emphasis on DPD based on Volterra series and its field-programmable gate-array (FPGA) hardware implementation. He also has interests in nonlinear system identification algorithms, digital signal processing (DSP), and wireless communication system design.

Anding Zhu (S’00–M’04) received the B.E. degree in telecommunication engineering from North China Electric Power University, Baoding, China, in 1997, the M.E. degree in computer applications from the Beijing University of Posts and Telecommunications, Beijing, China, in 2000, and the Ph.D. degree in electronic engineering from University College Dublin (UCD), Dublin, Ireland, in 2004. He is currently a Lecturer with the School of Electrical, Electronic and Communications Engineering, UCD. His research interests include high-frequency nonlinear system modeling and device characterization techniques with a particular emphasis on Volterra-series-based behavioral modeling and linearization for RF PAs. He is also interested in wireless and RF system design, digital signal processing, and nonlinear system identification algorithms.

Thomas J. Brazil (M’86–SM’02–F’04) received the B.E. degree in electrical engineering from University College Dublin (UCD), Dublin, Ireland, in 1973, and the Ph.D. degree in electronic engineering from the National University of Ireland, Dublin, Ireland, in 1977. He was subsequently involved with microwave subsystem development with Plessey Research, Caswell, U.K., prior to rejoining UCD in 1980. He is currently a Professor of electronic engineering and Head of the School of Electrical, Electronic and Communications Engineering, UCD. His research interests are in the fields of nonlinear modeling and characterization techniques at the device, circuit, and system levels. He also has interests in nonlinear simulation algorithms and several areas of microwave subsystem design and applications. He has authored or coauthored numerous publications appearing in international scientific literature. Prof. Brazil is a Fellow of Engineer Ireland. He is a member of the Royal Irish Academy. From 1998 to 2001, he was an IEEE Microwave Theory and Techniques Society (MTT-S) Worldwide Distinguished Lecturer in high-frequency computer-aided design (CAD) applied to wireless systems. He is currently a member of the IEEE MTT-1 Technical Committee on CAD.

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New Trends for the Nonlinear Measurement and Modeling of High-Power RF Transistors and Amplifiers With Memory Effects Patrick Roblin, Member, IEEE, David E. Root, Fellow, IEEE, Jan Verspecht, Fellow, IEEE, Youngseo Ko, Member, IEEE, and Jean Pierre Teyssier, Member, IEEE (Invited Paper)

Abstract—Power amplifier (PA) behavior is inextricably linked to the characteristics of the transistors underlying the PA design. All transistors exhibit some degree of memory effects, which must therefore be taken into account in the modeling and design of these PAs. In this paper, we will present new trends for the characterization, device modeling, and behavioral modeling of power transistors and amplifiers with strong memory effects. First the impact of thermal and electrical memory effects upon the performance of a transistor will be revealed by comparing continuous wave and pulsed RF large-signal measurements. Pulsed-RF load–pull from the proper hot bias condition yields a more realistic representation of the peak power response of transistors excited with modulated signals with high peak-to-average power ratio. Next, an advanced device modeling method based on large-signal data from a modern nonlinear vector network analyzer instrument, coupled with modeling approaches based on advanced artificial neural network technology, will be presented. This approach enables the generation of accurate and robust time-domain nonlinear simulation models of modern transistors that exhibit significant memory effects. Finally an extension of the X-parameter (X-parameter is a trademark of Agilent Technologies Inc.) behavioral model to account for model memory effects of RF and microwave components will be presented. The approach can be used to model hard nonlinear behavior and long-term memory effects and is valid for all possible modulation formats for all possible peak-to-average ratios and for a wide range of modulation bandwidths. Both the device and behavioral models have been validated by measurements and are implemented in a commercial nonlinear circuit simulator. Index Terms—Behavioral model, device modeling, large-signal RF measurements, memory effects.

I. INTRODUCTION

P

OWER transistor amplifiers express behavior that has as its origin the memory effects of the transistor technology on which they are built. The term memory is used here to de-

Manuscript received October 02, 2011; revised February 29, 2012; accepted March 05, 2012. Date of publication May 01, 2012; date of current version May 25, 2012. This work was supported in part by the National Science Foundation (NSF) under Grant ECS 1129013. P. Roblin and Y. Ko are with the Department of Electrical and Computer Engieering, The Ohio State University, Columbus, OH 43210 USA (e-mail: [email protected]; [email protected]). D. E. Root is with the Electronic Measurement Group, Agilent Technologies Inc., Santa Rosa, CA 95403 USA (e-mail: [email protected]). J. Verspecht is with Agilent Technologies Belgium SA/NV, Opwijk B-1745, Belgium (e-mail: [email protected]). J. P. Teyssier is with XLIM, University of Limoges, Limoges 87032, France (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2012.2193140

scribe effects that vary on timescales much longer than those associated with the RF period. Some causes of memory effects in transistors are dynamic self-heating (always present due to thermodynamic considerations), dynamic trapping (capture and emission) effects, prevalent especially in some compound semiconductor material systems (e.g., GaN and GaAs), and parasitic bipolar transistor effects in semiconductor-on-insulator (SOI) MOSFETs. In microwave components, the biasing circuit is also known to introduce memory effects that must be considered in behavioral modeling. Self-heating plays a major role in power transistor operation. Conversion of electrical energy to heat creates a change in device temperature that, in turn, affects key electrical device characteristics, such as power gain. The device temperature distribution depends significantly on the class of operation, itself determined by dc-bias conditions, load conditions, and power levels associated with the RF signals. Thermal boundary conditions are also very important. Trapping phenomena, in the bulk or at the surface of semiconductor material, are prevalent in III–V field-effect transistor (FET) technologies, such as GaAs-based MESFETs and pseudomorphic HEMTs (pHEMTs), and recently introduced high-speed and power technologies based on GaN. Trapping effects of different types are claimed to be responsible for “power slump,” “knee collapse,” and the phenomena of drain-lag and gate-lag [1], [2]. Memory effects make it much more difficult to estimate, from conventional transistor characterization data, the actual largesignal transistor performance at RF frequencies and large-amplitude stimuli. It is generally impossible to infer, accurately, the power or efficiency of a GaN transistor at large input power from dc and linear -parameter measurements alone. Multiple mechanisms producing long-term memory are often present simultaneously in transistors, making it difficult to separately identify and model the independent contributions for a particular device, Over the past 20 years, pulsed bias and pulsed -parameter measurement techniques have been deployed to provide information that device modelers could use to separate distinct memory mechanisms for more comprehensive models. The timescales (e.g., 100 ns) for such measurements are shorter than the timescales for variation of a “slow” variable like temperature or states related to trapping. Such “iso-thermal” or “iso-dynamic” data gives a snapshot of the device currents

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ROBLIN et al.: NEW TRENDS FOR NONLINEAR MEASUREMENT AND MODELING OF HIGH-POWER RF TRANSISTORS AND AMPLIFIERS

and linear behavior at conditions set by the quiescent operating point from which the pulses originate. However, all this information is parameterized by the quiescent point. Converting this into a comprehensive dynamic model is a very difficult task, taking many additional steps, and many additional approximations. This is especially true for the details of how the trap states affect both the current, and the output charge storage of the device. Examples of such approaches, based on different assumptions about how the traps modify the drain current, are given in [1] and [7]. Much less work has concerned how the trapping effects modify the model terminal charges, and therefore the “high-frequency” memory of the intrinsic device. Even though traps will not normally respond instantaneously to an RF signal, the average trap occupation will still depend on the dynamic load-line trajectory for large-signal excitations [8], [9] due to cyclostationary effects. Indeed, as was demonstrated in [10], the trap occupation is dependent on the time average of the bias-dependent emission and capture rates along the dynamic load-line trajectory. Measurements revealing the impact of thermal and electrical memory effects upon the large-signal RF response of a transistor will be presented in Section II. This will be achieved by comparing continuous wave (CW) and pulsed RF large-signal measurements for various hot-bias conditions and duty rates. Pulsed-RF measurements are useful to obtain a more realistic characterization of the RF response of a transistor at peak power when excited with modulated signals with high peak-to-average power ratio (PAPR) excitations. Section III will present a systematic and accurate approach to generating a detailed time-domain large-signal simulation model directly from large-signal data from a modern nonlinear vector network analyzer (NVNA) instrument. A complete methodology will be used to convert the data directly into nonlinear constitutive relations of current and charge that include detailed dependence on the temperature and the two trap states considered. Behavioral modeling of microwave components is an alternate approach to device modeling, which is of great interest to the designers of amplifiers that are used in today’s wireless communication infrastructure. An important problem faced by these engineers is the difficulty to characterize, describe, and simulate the nonlinear behavior of amplifiers that are stimulated by signals that have a high peak-to-average ratio and that stimulate the amplifier at a power range covering the full operating range. This is problematic for at least two reasons. Firstly, the amplifier behavior may be driven into full saturation and is as such strongly nonlinear. A good overview of existing techniques for the behavioral modeling of microwave amplifiers can be found in [11]. Most of the existing approaches are based on Volterra theory and as such rely on polynomial approximations. Polynomial approximations cannot easily handle hard nonlinear behavior such as saturation. Secondly, the amplifier behavior shows memory effects as previously discussed. Unfortunately approaches that can handle hard nonlinear behavior, such as a simple compression and AM-to-PM characteristic or a more advanced poly-harmonic distortion (PHD) model [12], [13], have no straightforward way of dealing with memory effects.

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Section IV of this paper will present an original behavioral model that is not based on polynomials and that can easily handle memory effects. One of the advantages of the new approach, called dynamic X-parameters, is that the model can be extracted by performing a simple set of measurements. Another advantage is that the model remains valid for a wide range of modulation bandwidths, which is typically not the case for classic approaches. II. PULSED AND CW LARGE-SIGNAL MEASUREMENTS As was discussed in Section I, various types of low-frequency memory effects arise in transistors due to different physical processes. Self-heating, trapping, and bipolar parasitic transistor effects in MOSFETs are typically the main sources of low-frequency memory effects with electrical time constants running from 100 s to 100 ns. It is of interest to investigate the impact of these memory effects on the performance of power amplifiers (PAs) excited by signals with high PAPR. Complex modulated signals such as WiMAX and long-term evolution (LTE) exhibit large PAPR reaching 10 dB. However PAPRs larger or equal to 10 dB arise with a very small probability (typically 10 ) and take place for short duration on the order of 100 ns. Thus, most of the time the amplifier is amplifying the modulated signals at the average power. This raises questions about which characterization and modeling techniques enable a realistic simulation of the device performance for excitations with large PAPR. Load–pull is a phenomenological technique that is often used either in simulation or experimentally to design PAs. In load–pull measurements, the multiharmonic terminations presented by the load and source networks are tuned to optimize the power-added efficiency (PAE) of the PA while maintaining its gain over the dynamic range of the output power. Conventionally, load–pull relies on CW RF signals. However, CW load–pull may not provide a reliable evaluation of the transistor performance if the device exhibits strong memory effects. To demonstrate this, let us first consider self-heating. For amplifiers operating in class B, AB, or class F, the power dissipated by the transistor increases with increasing input power. However, considering that peak power is typically achieved for a very short duration (100 ns), has a low probability of occurrence, and thermal effects are usually relatively slow s , the device will remain operating at the temperature established by the average dissipated power. Therefore, CW load–pull at the peak power may not yield realistic results due to the comparatively much larger self-heating it will induce. Next consider the impact of traps in devices such as GaN HEMTs. Under low-power CW operation, the drain voltage peak remains typically small and the traps are not activated. However, for modulated RF signals, the instantaneous drain voltage reaches intermittently large values (50–60 V). Traps in GaN typically have very short capture time (ns) at high drain voltages (50 V) and very long emission time (s) at lower drain voltages 40 V . Therefore, traps charge during the brief periods of peak power and do not have time to discharge during the intervening time. The dominant response of the transistor for the average input power is then directly affected by the

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Fig. 1. Pulsed I–V pulsed RF test bed used to perform both pulsed-RF RTALP and pulsed active load–pull.

charged traps and associated “knee walkout” effect resulting from these intermittent high power peaks of the modulated RF signal. Thus, the dynamics of charge trapping for modulated RF excitations cannot be captured by CW load–pull simulations and measurements. An increase of output noise can also be detected due to the activated traps. Note that the state of the traps is not determined by the dc-bias condition, but by the RF load line (cyclostationary effect) [8]–[10]. Other memory effects such as the slow parasitic bipolar in SOI-MOSFET may also be expected to be affected by the dynamic RF load lines. The impact of memory effects on the transistor performance excited by signals with high PAPR can be detrimental (trap case) or beneficial [lower temperature of operation or reduced parasitic bipolar junction transistor (BJT)] depending on the particular dominant memory process. Since CW load–pull measurements may not provide a realistic characterization approach, other alternatives must be pursued. To more realistically characterize the performance of a transistor for RF signals with high PAPR modulation, pulsed RF large-signal measurements from a well-defined hot-bias operating condition offers such an alternative. The pulsed I–V/RF testbed used in this section is shown in Fig. 1. The pulsed measurements with the large-signal network analyzer (LSNA) rely on the method of multiple recording data acquisition [14], [9] to achieve 0% desensitization independently of the duty rate. The new technique of pulsed-RF real-time active load–pull (RTALP) [15], [16] measurements was used to optimize the output load. To investigate the use of pulsed-RF large-signal measurements to characterize memory effects, we shall now consider a sub-cell of a power SOI-MOSFET transistor. This device will be initially tested for three different incident power levels of 1, 4, and 11 dBm at 1.9 GHz, for CW and pulsed RF signals of 1% duty rate. The PAE contour plot obtained from pulsed-RTALP is shown in Fig. 2 for an input power level of 0.4 dBm. The optimal load selected for low-power operation

Fig. 2. Constant PAE contour obtained from pulsed-RTALP shown here for 0.4-dBm incident power at 1.9 GHz for class-AB operation.

Fig. 3. RF transfer obtained for CW (dashed lines) and pulsed (plain lines) RF excitations with incident power of 1, 4, and 11 dBm and 1% duty rate at 1.9 GHz.

yields a maximum PAE of 66%. Note that a different drain load of is used at 11-dBm incident power. The transistor is found to operate in quasi-class AB. Load–pull at the second and third harmonic were verified to yield negligible PAE improvements. The RF transfer characteristic versus and dynamic load lines versus obtained are shown in Figs. 3 and 4 and the performance of the device is summarized in Table I. The gate voltage swing shown in Fig. 3 is seen to be about the same for the various incident signals. The output drain current is also similar for the 1- and 4-dBm incident power levels. However, for 11-dBm incident power, the drain current swing is much larger. The drain current under pulsed RF reaches a more negative value indicating an increased power generation during the RF cycle associated with the drain charge storage. Fig. 4 also shows a corresponding increased drain voltage swing. It is

ROBLIN et al.: NEW TRENDS FOR NONLINEAR MEASUREMENT AND MODELING OF HIGH-POWER RF TRANSISTORS AND AMPLIFIERS

Fig. 4. Drain load lines obtained for CW (dashed lines) and pulsed (plain lines) RF excitations at 1.9 GHz with incident power of 1, 4, and 11 dBm and 1% duty rate.

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Fig. 5. RF transfer at 1.9 GHz obtained for 11-dBm CW (black line with circles) and pulsed RF excitations for 1% (blue and red lines (in online version) with up and down triangles) and 4% (magenta line (in online version) with square) duty rate and different hot biases.

TABLE I CW AND PULSED RF TRANSISTOR PERFORMANCE AT 1.9 GHz

to be noted that the pulsed-RF load line reaches a lower knee voltage than expected from the dc and pulsed I–V at V (gray dashed and plain lines in Fig. 4). As indicated in Table I, the pulsed RF measurements exhibit an improved PAE of 14% compared to the CW measurement while maintaining the same power gain. To investigate the physical origin of this memory effect, we shall now: 1) vary the dc-bias points of the pulsed-RF measurements or 2) change the duty rate. The results are shown in Figs. 5 and 6 and the transistor performance summarized in Table II. The previous pulsed RF load line (red line (in online version) with top triangles) that was measured with the device at the dc-bias temperature (no RF applied) and the CW load line (black line with diamonds) are included for references. The pulsed RF load lines with a higher hot-biasing current of 11.8 mA (blue line (in online version) with down triangles) that largely overestimates the self-heating in CW operation is seen to remain similar to the pulsed RF load line with the bias-point temperature (red line (in online version) with up triangles). A resulting decrease in PAE of only 2% with this overestimated operating temperature is obtained as shown in Table II. Clearly, self-heating is not the dominant memory effect in this device.

Fig. 6. RF dynamic load line at 1.9 GHz obtained for 11-dBm CW (black line with circles) and pulsed RF excitations for 1% (blue and red lines (in online version) with low and upper triangles) and 4% (magenta line (in online version) with square) duty rate and different hot biases.

TABLE II CW AND PULSED RF TRANSISTOR PERFORMANCE @ 11 dBm

Now increasing the duty rate from 1% to 4% (magenta line (in online version) with squares) is seen to produce a dynamic transfer characteristic and a dynamic load line that is bridging the gap between the ones obtained from CW and pulsed RF in

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Figs. 3 and 4. The increased duty rate also yields a reduced PAE increase of 8% instead of 14% in Table II. In the particular case of the SOI technology considered, the memory effects have a beneficial impact on the device performance. Namely, under the transient peaks of the modulated RF excitations, the transistor performed better than expected from operation at CW peak power while maintaining the same operating temperature. A similar trend was observed on different devices and on different wafers. The precise origin of this memory effect is not known, but several assertions can be made. Self-heating associated with the power dissipation in the device was verified not to be the controlling factor. This is explained by the relatively low thermal resistance of the substrate used. The different gate voltage swing, drain voltage swing, and drain current swing observed in Figs. 3 and 4 indicate that the gate and drain charges under the channel are different under pulsed and CW operations. The lower effective knee voltage observed in pulsed operation compared to CW operation could arise from a reduced effective channel resistance. The more negative drain current observed in Figs. 3 and 4 under pulsed operation that is associated with the improved PAE (negative power dissipation) is also indicative of a more efficient recovery of the charge stored in the channel. Presumably under unrealistic CW operation at peak power, the steady-state impact ionization may lead to charge accumulation adversely modifying the channel characteristics of the transistors. Note that memory effects do not always have a beneficial impact like in the SOI MOSFET considered here. For example, trapping in GaN HEMTs induced by the transient peaks of the envelope of complex modulated RF excitations usually degrades the device performance, as was discussed. In all the cases, the impact of memory effects on the transistor performance for RF signals with high PAPR needs to be carefully assessed. This is particularly needed for a more realistic design of PAs relying on some type of load modulation for improved power efficiency. In such a case, pulsed-RF load–pull from the proper hot bias condition will yield a more realistic representation of the peak power response of transistors excited with modulated signals with high PAPR. The modeling of memory effects will now be investigated in Sections III and IV. III. TIME-DOMAIN DEVICE MODELING A. State Equations for Dynamical Variables In this section, we are concerned with the development of a detailed time-domain large-signal simulation model directly from large-signal data from a modern NVNA instrument. We assume we can model the transistor by a set of coupled nonlinear ordinary differential equations of circuit theory. This means there is postulated a set of coupled nonlinear equivalent circuits for the electrical, thermal, and other dynamical variables (e.g., trap states) that determine the behavior of the device model. An intrinsic model of a III–V FET with thermal and trapping dependent memory is presented in Fig. 7. A simple onepole thermal equivalent circuit is used to compute the junction

Fig. 7. Nonlinear equivalent circuit of III-V FET model with dynamic selfheating and trapping.

temperature from knowledge of the dissipated electrical power. More poles can be added if necessary to better model the distributed nature of heat propagation. Two species of trapping and emission phenomena are described by the remaining equivalent circuits in Fig. 7. These are of the form proposed in [1] to describe gate-lag and drain-lag phenomena, respectively, common in III–V GaAs and GaN FETs. The key dynamical principle here is that there are asymmetric fast capture processes (in the directions of the diode) and slow emission processes that depend on both the direction and the rate of the applied fields (voltages). The intrinsic electrical model for currents and charges depends nonlinearly on five variables—the two instantaneous intrinsic terminal voltages, the junction temperature, and the two trap state voltages across the respective gate-lag and drain-lag capacitors, respectively. The equations for the instantaneous drain current and the other time-dependent dynamical variables associated with junction temperature, , and traps states for gate-lag and drainlag, respectively, and , are given in (1)– (4). Gate current equations can be found in [3]

(1) (2) (3) (4) Equations (2)–(4) are state equations—first-order differential equations for the evolution of the key dynamical (state) variables that are arguments of the electrical constitutive relations appearing in (1). The functions and appearing in (3) and (4), respectively, are diode-like nonlinearities that account for preferential trapping rates when the instantaneous gate (drain) voltage becomes more negative (positive) than the values of and . The parameters and are characteristic emission times, typically assumed to be very long compared to the RF time scales.

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Fig. 8. Model identification process with explicit functional formulas for state variable values.

B. State Variable Identification From Large-Signal Waveforms The model identification process is then to define the detailed nonlinear constitutive relations defining the current and charge function, , and , respectively, in (1), as nonlinear functions of all five independent variables. Remarkably, it is possible to identify these complicated multivariate dependencies directly from measured device large-signal waveform data under purely steady-state conditions. That is, by exciting the device with CW large-signal sinusoidal inputs at each port, varying the input and output port power, the relative phase between input and output port excitations, dc-bias conditions, and backside (or case) temperatures, it is possible to sample the detailed dependence of the current and charge functions everywhere in the operating space of the five independent variables [3]. To understand why this is true, we note that at typical RF frequencies, the temperature cannot follow the RF signal. At steady state, therefore, the junction temperature assumes a fixed value equal to the increase over ambient temperature given by the average dissipated power over an RF cycle, multiplied by the thermal resistance (a parameter that can be extracted by other techniques [5]). For each steady-state periodic large-signal RF load line, the junction temperature can be calculated by the simple formula in Fig. 8. For trap capture rates much faster than the RF signal, and for emission rates much slower than the RF signal, the trap circuits operate as peak detectors. The value, under steady-state largesignal conditions for these trap states, therefore, becomes the minimum (maximum) of the excursion of the waveforms over a given period. Thus, the large-signal RF CW excitation sets the values of the slow dynamical variables, but the measurement allows for their computation using simple formulas. The present methodology associates a set of three auxiliary values for , , and with each waveform measurement, one waveform per power, dc bias, backside temperature, and complex load. That is, the junction temperature value and values for the trap states are functionals of the particular waveform. The model identification flow is given by Fig. 8.

Fig. 9. Parametric plot of measured dynamic load lines used for large-signal versus and (bottom) versus model generation: (top) .

It is possible to engineer a complete set of dynamic load lines by properly varying the load (through passive tuning or active injection at port 2), RF power, dc-bias conditions, and backside temperatures to cover the entire large-signal operating range of the device. An example of measured waveforms, in space and space is given in Fig. 9. It is important to note that this region extends far beyond the conventional region of dc operation of a device. A great advantage of NVNA data is that the extreme regions of the device operation can be characterized with much less degradation of the transistor. This is because the instantaneous voltages only enter the high-stress regions for sub-nanosecond periods as the device is stimulated with signals at 1 GHz or higher frequency. For the same reason, less energy is dissipated in the device at high instantaneous power regions than under dc conditions. The larger domain of device operation means the need for the final model to extrapolate during large-signal simulation is dramatically reduced or even eliminated completely. Actual nonlinear data obtained under realistic operating conditions means the modeling process does not have to “extrapolate” from linear and dc data to predict nonlinear RF behavior, as do the approaches based on small-signal data parameterized by dc-bias conditions. Moreover, the NVNA data provides detailed waveforms for comprehensive nonlinear model validation without the need for additional instruments, such as spectrum analyzers, that only give the magnitude of the generated spectrum—the NVNA measures the magnitudes and the phases of the distortion products.

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C. Constitutive Relation Approximation The remaining task is to smoothly approximate the device-specific nonlinear constitutive relations from the sampled values of the waveforms and dynamical variables obtained by the procedure outlined in Section III-B. In principle, any of a wide variety of fitting techniques can be used to fit the currents and charges as nonlinear functions of each of the five independent variables. In the work reported here, advanced artificial neural network (ANN) training techniques were implemented [3]. ANNs have a great many advantages over other methods [6]. Unlike polynomials, ANNs have infinitely many nonzero partial derivatives, useful for high-order distortion simulation at relatively small amplitudes, and ANNs do not diverge beyond the training region, a property useful for robust convergence in nonlinear simulators. ANNs can be trained easily on the scattered data in the multivariate space of independent variables. ANN-based nonlinear constitutive relations can be easily compiled into standard nonlinear circuit simulators. Previously, specific and simplified assumptions about how the trap state values affect the shape of the current and chargestorage characteristics had to be assumed, typically by modifying the intrinsic terminal voltages or parameters in the constitutive relations such as threshold voltage [1], drain resistance [2], or adding simple self back-gating equivalent circuits [17]. There is great insight that can be obtained by looking at the constructed constitutive relations based on large-signal steadystate waveforms. Two examples of generated intrinsic constitutive relations for different sets of trap states are shown in Fig. 10. The model current constitutive relations corresponding to extreme trap states [see Fig. 10 (top)] bears a striking resemblance to pulsed bias characterization from quiescent bias points associated with the trap state biases [4]. The advantage of the NVNA approach is that the model characteristics are inferred from DUT responses to signals typically three or more orders of magnitude faster than what can be measured with most pulsed systems that are typically limited from 0.1 to 1 m. The complete model solves for the trap states, junction temperature, and currents self-consistently during simulation. When embedded back into the parasitic model, final comparison can be made to measured data. Fig. 11 shows the validation with measured dc I–V curves. Note how different the static nonisothermal I–V curves in Fig. 11 are from the intrinsic model constitutive relations under the conditions of Fig. 10 (top) and (bottom). Although not shown here, the dependence of the key constitutive relations on five state variables provides sufficient degrees of freedom to fit the bias dependence of the small-signal model over the entire bias space at both dc and high frequencies [3]. That is, frequency dispersion phenomena are predicted accurately under small- and large-signal conditions as a consequence of incorporating properly both dynamic trapping and electrothermal effects. Models with just electrothermal effects are not capable of such good fits to both dc and high-frequency behavior at all biases. Fig. 12 shows the nonlinear validation results for the advanced FET model for power-dependent gain and bias current versus power. The distinctive car-shaped gain compression

Fig. 10. intrinsic model constitutive relation. (top) For large fixed trap state values indicating knee collapse. (bottom) When trap states move with dc bias.

Fig. 11. Simulation of full model (solid line) and measured (symbols) comparison of extrinsic dc I–V curves.

characteristic and significant nonmonotonic dependence of the bias current with power is a result of the dynamics of drain-lag and the detailed constitutive relation obtained with the ANN training. Fig. 13 shows the model validation of distortion versus power for this device, validating both the dynamical description and accuracy and robustness of the ANN approach to modeling the complicated constitutive relations. Fig. 14 shows the model simulation and NVNA waveform validation measurement of a steady-state dynamic load line at a complex output impedance not used in the ANN training. Also shown is the set of dc-bias conditions demonstrating how much

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of dealing with memory effects. As explained in [20], memory effects can be classified as either short term or long term. Short-term memory effects are caused by physical dynamics that occur at the timescale of the carrier. This is, for example, the case with frequency dispersion in filters. Long-term memory effects are caused by physical dynamics happening at a much longer timescale. This is, for example, the case for dynamic self-heating or self-biasing effects. In this section, a new behavioral model that can easily handle long-term memory effects for a wide range of modulation bandwidths is presented. A. Introduction of the Model Equations Fig. 12. Modeled and measured gain versus .

, and dc-bias current versus

Fig. 13. Measured and modeled fundamental and harmonic output power versus input power.

Unlike existing approaches that deal with long-term memory, the approach we present is not derived from Volterra theory, but is derived from simple first principles. The result is a model that describes hard nonlinear behavior, as well as long-term memory effects. In all of the following, a simple matched system will be considered, having only one input signal , the incident fundamental, and one output signal, , typically the amplified signal. Note that all signals are considered to be complex envelope representations of a modulated carrier. All of the concepts can be extended toward mismatched conditions by including the incident and scattered wave signals, and , at both signal ports, and can be extended towards harmonic effects like the models described in [12] by including the harmonics of the carrier signal. The above extensions are outside the scope of this paper. It will be assumed that the input signal can be represented as a modulated carrier with a fixed frequency. Our model is a so-called low-pass equivalent model that only processes the envelope information signal [11]. The new model equation, which will be derived later, is

(5)

Fig. 14. Simulated (dashed line) and independently measured large-signal dynamic load line (circles) extending beyond dc I–V data (plain line).

more of the device operating range is accessible by NVNA characterization methods. IV. DYNAMIC BEHAVIORAL MODELING Behavioral modeling of microwave components provides an alternate modeling approach that bypasses the need for detailed device and circuit modeling of the circuits involved. Unfortunately as was discussed in Section I, behavioral models that can handle hard nonlinear behavior, like AM-to-PM characteristic or the PHD model, have no straightforward way

The basic idea of the new approach is that can be written as the superposition of a static part, represented by the nonlinear function , and a dynamic part, represented by a simple integral over time of a nonlinear function . Note that , as well as the integrated function , are a function of the instantaneous amplitude of the input signal . The dependency on the phase of the input signal is represented as a separate multiplicative vector . To simplify the mathematical notation, introduce . As shown in [12], this phase dependency can be explained by the principle of time-delay invariance. The static part behaves like a classic PHD model. The dynamic part is original as it represents the long-term memory effects. These are described as the integral effect of a general nonlinear function of the instantaneous amplitude of the input signal , the past values of the input signal , and how long ago that past value occurred (variable ). The model (5) can be derived by using the notion of hidden variables [18]. B. Derivation of the Model Equation To derive (5), one starts with writing the simple static PHDmodel equation, as described in [12], which is equivalent to a

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simple compression and AM-to-PM characteristic. This results in (6) In (6), the function represents the mapping from the amplitude of the input signal to the corresponding output signal amplitude and phase, whereby the dependency on the phase of the input signal is represented as a separate multiplicative vector. As described in [18], memory effects can be introduced by making use of one or more hidden variables. The idea is that, in a system with memory, the mapping from the input signal to the output signal is no longer a function of the input signal amplitude only, but is also a function of an arbitrary number of a priori unknown hidden variables, denoted . These variables represent time varying physical quantities inside the component, such as temperatures, bias voltages or currents, trapping states, that influence the mapping from the input signal to the output signal. With the introduction of the hidden variables, (6) becomes (7) To make (7) useful in the context of a black-box modeling approach, one further needs to make an assumption regarding the relationship between the hidden variables and the input signal. Note that one could use a priori information on the physics of the device-under-test (DUT) to find this relationship. The black-box assumption on the relationship between the input signal and the hidden variables is mathematically expressed as

of the bias voltage, which modulates the PHD model. One can easily imagine many other physical effects that are described by (8), such as trapping effects and self-heating, whereby the dissipated power is a nonlinear function of and causes temperature changes, which are linearly related to the dissipated power, and which modulate the PHD model. The link with (5) is then made by assuming that one can linearize (7) in the hidden variables . In order to linearize, we need to choose an operating point. In the following, we choose to linearize around the steady-state solution for the hidden variables that corresponds to the instantaneous amplitude . In other words, we linearize around the steady-state solution that the system would reach assuming that we keep the input amplitude constant for all future time instants, the amplitude being equal to the instantaneous input amplitude. This linearization implicitly assumes that the deviations of the hidden variables from their steady-state solution are always small enough not to violate the superposition principle. These steady-state solutions are a function of the input signal amplitude and are noted in the following by . For example, the value of is equal to the asymptotic value of the hidden variable when one applies a constant input signal amplitude equal to . Note that the argument of is a signal amplitude, whereas the argument of the hidden variable is time. The functions are easily calculated by simply substituting by a constant in (7) (9) with

(8) Equation (8) expresses that the th hidden variable is generated by a linear filter operation, characterized by its impulse response , which operates on a nonlinear function of the input signal amplitude , can be interpreted as a source term that describes how the input signal is related to the excitation of a particular hidden variable; in general, this is a nonlinear relationship. A good example could be, e.g., that describes the power dissipation as a function of the input signal, whereby is the temperature. The impulse response describes the actual dynamics of a hidden variable, e.g., could describe a thermal relaxation. Note that the model as described in [13] is actually a special case of the above equations whereby there is only one hidden variable with

(10) Equation (7) can then be rewritten as

(11) with (12) represents the deviation of In (12), the new variable the hidden variable from its steady-state solution corresponding to the instantaneous input signal amplitude. It is now further assumed that (7) can be linearized in these deviations from steady-state . This results in

or and

(13) with

(14) In [13], the equations are physically related to the assumption that the amplitude squared relates to the bias current flowing through a first-order linear bias circuit, which causes a variation

and (15)

ROBLIN et al.: NEW TRENDS FOR NONLINEAR MEASUREMENT AND MODELING OF HIGH-POWER RF TRANSISTORS AND AMPLIFIERS

The functions represent the sensitivity of the output signal to variations of the th hidden variable. For example, if represents the temperature, represents how sensitive the output signal is to temperature changes. Note that is a general nonlinear function of the instantaneous input signal amplitude. It is perfectly possible for example that the output signal is highly sensitive to temperature changes for small input signals (corresponding to a temperature-dependent small-signal gain), but not at all for high input signals whereby the output is fully saturated. In the structure of (13), one can distinguish a static part, represented by and a dynamic part, represented by the summation over the hidden variables index “ .” The static part, which can be derived from by using (14), corresponds to a classic static PHD model. Note that the subscript “ ” is used in since this function corresponds to the response of the DUT to a single-tone CW excitation. Substitution of in (12) using (8) and subsequently substitution of in (13) using (12) results in

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Equation (18) reveals that the multivariate function is not arbitrary since the following relationship will always be valid: (20) As will be shown next, this property is key in the experimental . determination of the function C. Model Identification An important question is how one can determine the model functions and from experiments. As will be shown in the following, the model can completely be identified from measuring a simple set of large-signal step responses. The set of input step signals should be such that one switches, at time zero, from one value to another value, covering the whole range of possible input signal values. Consider the application of a step input signal, whereby for and for . The solution for such a large-signal step response will be noted as and is then given by

(21) (16) Using (10) and changing the order of summation and integration, one can write (22) Equations (20) and (22) can be rewritten as

(17) In general, one may neither know what the hidden variables are, nor how many there are or how they interact with the system. Nevertheless, one can always define the multivariate function by

(23) Taking the derivative versus “ ” at both sides of the above equation results in

(18) (24)

such that

(25)

(19) which is identical to (5). As such, we have been able to derive (5) from a hidden variables approach, which was the goal of this paragraph.

Note that, as a consequence of the inherent causality of (5), only needs to be defined for positive values of “ .” Equation (25) has important consequences. First of all, it allows for a straightforward measurement of the function by taking the inverse of the derivative of the step response when starting with input amplitude “ ” and switching to input amplitude “ ” at time 0.

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A second important consequence is that there is a one-to-one mapping between the model and the step responses. Given that one can measure all possible large-signal step responses, one could apply the principle of Ockham’s razor and raise the question “what is the simplest nonlinear dynamic model that is able to generate the measured large signal step responses?” The answer is the model as described by (5). This is definitely a significant advantage of the new modeling approach when compared to existing black-box memory modeling methods. D. Simplification in Case of Fast Varying Input Envelopes As explained in [19], an interesting case occurs when the input envelope varies fast relative to the timescale of the kernel and whereby the input envelope has ergodic properties (this means that the statistical characteristics are constant over time). The model will then be seemingly static, but with a static characteristic that is determined by the probability density function of the input envelope. Consider (5),

(26) For a fast variation of , one can write the dynamic memory term on the right-hand side of (26) as follows [19]:

(27) with equal to the probability density function of the input envelope amplitude, which is now considered to be a stochastic variable denoted by “ .” Changing the order of integration on the right-hand side of (27) leads to

(28) Next we will calculate the inner integral of the right-hand side of (28) by using identity (25) (29) whereby one notes that the integral operator at the right-hand side annihilates the derivative operator. The result is

(30)

As , subsequent substitution of (30) in (28) and in (26) results in

(31) From (31), one can conclude that the relationship between the input envelope and the output envelope will be given by a seemingly static characteristic. This static characteristic is equal to a weighted average of the large-signal step responses evaluated at time zero, using as a weight function the probability density function of the envelope input values. Since this simplified dynamic X-parameter model is typically valid for a wideband modulation, which is equivalent to a fast varying envelope, it is called a wideband X-parameter model. E. Experimental Model Identification and Validation The dynamic X-parameter model and the wideband X-parameter model were first experimentally validated using a Mini-Circuits ZFL AD packaged microwave amplifier. Two measurement platforms were used for the extraction of the model, as well as for the validation of the model. A first measurement platform was based on a customized PNA-X, a second measurement platform was based on a PXA digital spectrum analyzer in combination with an ESG or MXG digital synthesizer, all from Agilent Technologies Inc., Santa Rosa, CA. Note that the model extraction is based on using large-signal steps as excitation signals, whereas the model validation is based on using two-tone signals, as well as a periodically modulated signals with WCDMA characteristics. The model extraction, as well as the model validation was also performed using a carrier frequency equal to 1.75 GHz. Measured results of the model extraction are represented in Figs. 15–17. For the large-signal step experiments, the values of and are both swept from close to zero to . Note that the maximum input value of corresponds to about 5 dB of compression. Fig. 15 shows the large signal output steps for a fixed value of for and for sweeping . Note the rather slow frequency ringing in the step response. Both the static X-parameter kernel and the memory kernel are extracted from the above-mentioned set of largesignal step measurements. The corresponds to a classic AM–AM AM–PM characteristic. The new memory kernel is hard to visualize, as it is defined as a complex number defined on a square prism (two sides correspond to the amplitude ranges of and , the third side corresponds to the time duration of the memory). Fig. 16 shows the amplitude of the memory kernel at a fixed time instant (equal to 50 ns) as a function of and . Fig. 17 shows the time evolution of the kernel for a small and a large . The upper graphic has a time range of 60 s, where as the bottom graphic zooms in on the first 5 s only. Validation results are shown in Figs. 18 and 19. The first experiment is based on two-tone signals with a tone separation of 19.2 kHz, repeated for four different power levels. The measured input signals are also used to stimulate the extracted dy-

ROBLIN et al.: NEW TRENDS FOR NONLINEAR MEASUREMENT AND MODELING OF HIGH-POWER RF TRANSISTORS AND AMPLIFIERS

Fig. 15. Measured large-signal output steps for a fixed large value of swept).

(

Fig. 16. Memory kernel at fixed plifier.

am-

ns for Mini-Circuit ZFL

AD

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Fig. 18. Measured and modeled amplitude of the output envelope (19.2-kHz tone spacing) (solid measured, dots modeled).

Fig. 19. Measured and modeled dynamic compression characteristic (measured: solid, modeled: dashed).

Fig. 20. Measured and modeled IM3 amplitude for two-tone experiment (solid modeled, dots measured).

Fig. 17. Memory kernel (V s) versus time ( s) for a step transition from low (0.01 ) to high (0.2 ) input amplitude. (solid real part; dashed imaginary part).

namic X-parameter model inside the ADS2009 envelope simulator. The simulated output signals, as well as the measured output signals, are represented in Fig. 18. One notes the skewing of the output waveform, due to long-term memory effects, and the accuracy of the model to predict this behavior. An interesting way to look at this data is the dynamic compression characteristic shown in Fig. 19. It is a plot of the instantaneous output amplitude versus the instantaneous input amplitude for the four two-tone experiments. The modeled and the measured results are shown. As one notes, there is a significant looping effect for the higher power level, a clear manifestation of long-term memory effects, which is accurately modeled by

the dynamic X-parameter model. Whereas the tone spacing in Fig. 18 was fixed at 19.2 kHz, it is interesting to check what happens if one sweeps the tone spacing across a wide range, in our case, almost four decades from 1.2 kHz to 10 MHz. Fig. 20 shows the measured and modeled third-order-intermodulation (IM3) product amplitudes (both upper and lower) as a function of the frequency spacing, at a 10-dBm fixed input amplitude level per tone. Note that the model predicts the resonance around 60-kHz tone spacing very well. The model also predicts the asymmetry in the lower and upper IM3 characteristics. More advanced modulated signals were also applied, as shown in Fig. 21. In this figure, we plot the modeled and measured spectral regrowth when stimulating the amplifier with a signal with WCDMA characteristics (matching modulation bandwidth and statistics). To show the improvement of the dynamic X-parameter model over a static X-parameter approach, the prediction based on a static (or CW) X-parameter

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Fig. 21. Spectral regrowth using a signal with WCDMA characteristics.

Fig. 22. Spectral regrowth prediction using wideband X-parameters (25-W GaN amplifier of CREE @ 2-GHz carrier, LTE signal is used).

approach is included. One notes that the dynamic X-parameter predicts the spectral regrowth with great accuracy with an error less than 1 dB, whereas the CW X-parameter systematically overestimates the spectral regrowth by about 5 dB. Results on the validation of the wideband X-parameter modeling approach, applied to the ZFL AD , can be found in [19]. The wideband X-parameter model was also validated using a CREE CMP2560025 F amplifier. This is a 25-W 2500–6000-MHz GaN monolithic microwave integrated circuit (MMIC) PA. A setup using an MXG digital synthesizer and an PXA digital spectrum analyzer were used for extracting the wideband X-parameter kernel and for performing the validation measurements using an LTE signal at a 2-GHz carrier. The result is shown in Fig. 22. One notes that the spectral regrowth is accurately predicted, with an error less than 0.3 dB across a modulation bandwidth of about 40 MHz. V. CONCLUSIONS Low-frequency memory effects associated with self-heating, traps, parasitic BJT, and biasing circuits can greatly impact the large-signal RF performance of transistors and amplifiers excited by modulated RF signals. In this paper, the authors have presented new synergetic approaches for the: 1) characterization; 2) device modeling; and 3) behavioral modeling of power transistors and amplifiers with strong memory effects. In the first part of this paper (Section II), the use of CW and pulsed RF large-signal measurements was investigated to

quantify the impact of thermal and electrical memory effects upon the large-signal RF performance of transistors. Pulsed-RF load–pull measurements from realistic average hot bias condition yield a more realistic representation of the peak power response of transistors excited with modulated signals with high PAPR than can be obtained by CW load–pull measurements. For the SOI-MOSFET transistor considered, an improved efficiency of 14% was observed under pulsed operation compared to CW operation yielding a peak PAE of 73.7%. The results obtained further demonstrated that slow memory effects do not respond solely to the average bias or temperature, but can also depend on the RF load lines. Similar effects have been observed in GaN were intermittent high drain voltages can charges traps and induce knee voltage walkout degrading in that case the average performance of the transistor. The understanding of these processes is critical for both the design and simulation of amplifiers involving transistors exhibiting memory effects. In the second part of the paper (Section III), an RF device model capable of accounting for memory effects under largesignal operation was presented. The methodology used is a systematic, general, and powerful approach for characterizing and identifying an advanced self-heating and trap-dependent nonlinear simulation model directly from large-signal waveform data from an NVNA. The detailed nonlinear model constitutive relations for drain current and charge as functions of instantaneous terminal voltages, dynamic junction temperature, and two species of trap states, are identified and constructed using ANN modeling technology. The process is more procedural, more general, and more accurate than previous methods based on pulsed I–V/ -parameter data and simplified constitutive relations based on particular assumed trapping mechanisms. The model is implemented in a commercial nonlinear circuit simulator and is usable in all analysis modes (e.g., transient, harmonic balance, circuit envelope, small-signal, etc.). The model has been validated extensively for dc, linear, and large-signal conditions. In the third part of this paper (Section IV), dynamic X-parameters and a simplified version called wideband X-parameters were introduced as novel ways to build behavioral models for RF PAs that include long-term memory effects. The kernels of these models can be extracted by using a set of large-signal step response measurements, which are readily straightforward to perform. The resulting measurement-based models can be implemented in a commercial complex envelope simulator and accurately predict the behavior of the amplifier, including long-term memory effects. Unlike any existing black-box modeling approach, the dynamic X-parameter model is valid for a wide range of signals: for high power and low power, for slow as well as fast modulation, for pulsed signals, for two-tone signals, and for wideband modulated signals like, e.g., WCDMA and LTE. The model remains accurate for all possible modulation formats, independent of the probability density function or derived figures-of-merit (like, e.g., PAPR) of the input signal. The various measurement and modeling techniques presented in this paper for transistors and amplifiers with strong memory effects should benefit the PA community in multiple ways. The

ROBLIN et al.: NEW TRENDS FOR NONLINEAR MEASUREMENT AND MODELING OF HIGH-POWER RF TRANSISTORS AND AMPLIFIERS

pulsed-RF load–pull characterization can be directly used for amplifier design as in the case of load modulation [21] besides being used for device model extraction or verification. The enhanced transistor model that accounts for memory effects provides more realistic simulations for PA design. Finally, the novel PA behavioral model can greatly benefit the linearization of PAs exhibiting memory effects. ACKNOWLEDGMENT The device modeling work was performed in collaboration with J. Xu, J. Horn, and M. Iwamoto, all with Agilent Technologies Inc., Santa Rosa, CA, and was first reported in [3]. The measurements used for validating the behavioral model were performed in collaboration with J. Horn and T. Nielsen, Agilent Technologies, Denmark A/S, and was first reported in [18] and [19]. The authors gratefully acknowledge their contributions.

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[16] P. Roblin, P. Y. S. Ko, C. K. Yang, I. Suh, and S. J. Doo, “NVNA techniques for pulsed RF measurements,” IEEE Microw. Mag., vol. 13, no. 2, pp. 65–76, Apr. 2011. [17] Z. Ouarch, J. M. Collantes, J. P. Teyssier, and R. Quere, “Measurement based nonlinear electrothermal modeling of GaAs FET with dynamical trapping effects,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 1998, pp. 599–602. [18] J. Verspecht, J. Horn, L. Betts, C. Gillease, D. E. Root, R. Pollard, and D. Gunyan, “Extension of -parameters to include long-term dynamic memory effects,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2009, pp. 741–744. [19] J. Verspecht, J. Horn, and D. E. Root, “A simplified extension of -parameters to describe memory effects for wideband modulated signals,” in 75th ARFTG Conf. Rec., Jun. 2010, pp. 1–6. [20] A. Soury and E. Ngoya, “Using sub-systems behavioral modeling to speed-up RFIC design optimizations and verifications,” in INMMIC Conf. Rec., CITY, Spain, 2008, pp. 165–168. [21] H. Jang, Y. Ko, P. Roblin, C. Yang, and H. Park, “Pulsed load–pull based optimal load-modulation PA design methodology for average efficiency enhancement,” in 78th ARFTG Conf. Dig., Phoenix, AZ, Dec. 2011, pp. 1–6.

REFERENCES [1] O. Jardel, F. DeGroote, T. Reveyrand, J. C. Jacquet, C. Charbonniaud, J. P. Teyssier, D. Floriot, and R. Quere, “An electrothermal model for AlGaN/GaN power HEMTs including trapping effects to improve large-signal simulation results on high VSWR,” IEEE Trans. Microw. Theory Tech., vol. 55, no. 12, pp. 2660–2669, Dec. 2007. [2] A. M. Conway and P. M. Asbeck, “Virtual gate large-signal model of GaN HFETs,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2007, pp. 605–608. [3] J. Xu, J. Horn, M. Iwamoto, and D. E. Root, “Large-signal FET model with multiple time scale dynamics from nonlinear vector network analyzer data,” in IEEE MTT-S Int. Microw. Symp. Dig., May 2010, pp. 417–420. [4] A. E. Parker and D. E. Root, “Pulse measurements quantify dispersion in pHEMTs,” in URSI Int. Signals, Syst., Electron. Symp., Pisa, Italy, Sep. 1998, pp. 444–449. [5] M. Iwamoto, J. Xu, and D. E. Root, “DC and thermal modeling: III-V FETs and HBTs,” in Nonlinear Transistor Model Parameter Extraction Techniques. Cambridge, U.K.: Cambridge Univ. Press, 2011. [6] S. Haykin, Neural Networks: A Comprehensive Foundation, 2nd ed. New York: Prentice-Hall, 1999. [7] S. A. Albahrani, J. G. Rathmell, and A. E. Parker, “Characterizing drain current dispersion in GaN HEMTs with a new trap model,” in Proc. 39th Eur. Microw. Conf., Rome, Italy, Oct. 2009, pp. 1692–1695. [8] I. Suh, P. Roblin, Y. Ko, C.-K. Yang, A. Malonis, A. Arehart, S. Ringel, C. Poblenz, Y. P. Speck, and U. Mishra, “Additive phase noise measurements of AlGaN/GaN HEMTs using a large signal network analyzer and tunable monochromatic light source,” in 74th ARFTG Conf. Dig., Boulder, CO, Dec. 2009, pp. 1–5. [9] P. Roblin, Nonlinear RF Circuits and Nonlinear Vector Analyzer. Cambridge, U.K.: Cambridge Univ. Press, 2011. [10] A. S. Roy and C. C. Enz, “Analytical modeling of large-signal cyclostationary low-frequency noise with arbitrary periodic input,” IEEE Trans. Electron Devices, vol. 54, no. 9, pp. 2537–2545, Sep. 2007. [11] J. C. Pedro and S. A. Maas, “A comparative overview of microwave and wireless power-amplifier behavioral modeling approaches,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 4, pp. 1150–1163, Apr. 2005. [12] J. Verspecht and D. Root, “Polyharmonic distortion modeling,” IEEE Microw. Mag., vol. 7, no. 3, pp. 44–57, Jun. 2006. [13] J. Verspecht, D. Gunyan, J. Horn, J. Xu, A. Cognata, and D. Root, “Multi-port, and dynamic memory enhancements to PHD nonlinear behavioral models from large-signal measurements and simulations,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2007, pp. 969–972. [14] F. De Groote, O. Jardel, T. Reveyrand, J. -P. Teyssier, and R. Quéré, “Very small duty cycles for pulsed time domain transistor characterization,” 37th Eur. Microw. Conf., vol. 4, pp. 112–117, Jun. 2008. [15] F. De Groote, P. Roblin, J. P. Teyssier, C. Yang, S. Doo, and M. V. Bossche, “Pulsed multi-tone measurements for time domain load pull characterizations of power transistors,” in 73th ARFTG Conf. Dig., Boston, MA, May 2009, pp. 1–4.

Patrick Roblin (M’85) was born in Paris, France, in September 1958. He received the Maitrise de Physics degree from the Louis Pasteur University, Strasbourg, France, in 1980, and the D.Sc. degrees in electrical engineering from Washington University, St. Louis, MO, in 1984. In 1984, he joined the Department of Electrical Engineering, The Ohio State University (OSU), Columbus, where he is currently a Professor. He is the founder of the Non-Linear RF Research Laboratory, OSU. At OSU, he has developed two educational RF/microwave laboratories and associated curriculum for training both undergraduate and graduate students. He authored Nonlinear RF Circuits and Nonlinear Vector Network Analyzers (Cambridge Univ. Press, 2011). He coauthored the textbook High-Speed Heterostructure Devices (Cambridge Univ. Press, 2002). His current research interests include the measurement, modeling, design, and linearization of nonlinear RF devices and circuits such as oscillators, mixers, and PAs.

David E. Root (M’89–SM’01–F’02) received the B.S. degrees in physics and mathematics in 1978, and the Ph.D. degree in physics in 1986, from the Massachusetts Institute of Technology (MIT), Cambridge. In 1985, he joined the Hewlett-Packard Company (now Agilent Technologies), where he has held technical, management, and strategic positions. He is currently an Agilent Research Fellow with the Measurement Research Laboratories, Agilent Technologies, Santa Rosa, CA. His current responsibilities include nonlinear behavioral and device modeling, large-signal simulation, and nonlinear measurements for new technical capabilities and business opportunities for Agilent Technologies. In Fall 2005, he was a Visiting Scholar and Lecturer with the University of California at San Diego, La Jolla. He has authored or coauthored over 100 peer-reviewed technical journal papers, international conference and workshop papers, short courses, books, and book chapters. He coauthored and coedited Nonlinear Transistor Model Parameter Extraction Techniques (Cambridge Univ. Press, 2011) and Fundamentals of Nonlinear Behavioral Modeling for RF and Microwave Design (Artech House, 2005). He serves as reviewer for several technical journals and international conferences. Dr. Root was an IEEE Microwave Theory and Techniques Society (IEEE MTT-S) Distinguished Microwave Lecturer (2006–2008). He is past chair of the IEEE Working Committee on Computer-Aided Design (CAD) (MTT-1). Since 1995, he has been a member of the Technical Program Committee of the IEEE MTT-S International Microwave Symposium (IMS). He was a corecipient of the 2007 IEEE ARFTG Technology Award.

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Jan Verspecht (M’94–SM’05–F’07) was born in Merchtem, Belgium, on December 12, 1967. He received the Electrical Engineering and Ph.D. degrees from Vrije Universiteit Brussel (VUB), Brussels, Belgium, in 1990 and 1995, respectively. From 1990 to 1999, he was a Research Engineer with the Hewlett-Packard Company. From 1999 to 2002, he became a Technical Leader with Agilent Technologies Inc., Santa Rosa, CA. In 2003, he founded the company Jan Verspecht b.v.b.a., where he held the position of Chief Consultant until 2011. In 2008, he cofounded the company Verspecht-Teyssier-DeGroote s.a.s., where he was responsible for business development until 2011. In 2012, he rejoined Agilent Technologies Inc., as a Master Research Engineer. He is a pioneer of and key contributor to the development of NVNA technology. He has authored over 30 conference papers, 14 refereed journal papers, one book chapter, and the ARFTG short course on “Large-Signal Network Analysis.” He holds nine

patents. He is an inventor of -parameters. His research interests include the large-signal characterization and behavioral modeling of RF, microwave, and digital components. Dr. Verspecht was the recipient of the 2002 ARFTG Technology Award and the 2009 Best IEEE Microwave Theory and Techniques Society (IEEE MTT-S) International Microwave Symposium (IMS) Oral Presentation Award.

Youngseo Ko, photograph and biography not available at time of publication.

Jean Pierre Teyssier, photograph and biography not available at time of publication.

IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 60, NO. 6, JUNE 2012

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Complex-Chebyshev Functional Link Neural Network Behavioral Model for Broadband Wireless Power Amplifiers Mingyu Li, Jinting Liu, Yang Jiang, and Wenjiang Feng

Abstract—The Neural Network (NN) based models are commonly used in power amplifier modeling and predistorter design, and seen as a potential alternative to model and compensate broadband power amplifiers (PAs) having medium- to-strong memory effects along with high-order nonlinearity. In this paper, we propose a novel computationally efficient behavior model based on complex-Chebyshev functional link neural network (CCFLNN) suitable for dynamic modeling of wireless PAs. The CCFLNN exhibits a simpler compact structure than the previously reported NNs and can require less computational burden during the learning process since it uses the complex-valued topology and does not need the hidden layers, which exist in most of the conventional neural-network-based models. The proposed approach utilizes the complex-valued inverse QR-decomposition-based recursive least square algorithm to update the weighting coefficients of the CCFLNN model. The proposed model is comparatively compared with a real-valued focused time-delay NN model and a conventional memory polynomial model with respect to computation complexities and modeling performance. The accurate modeling capacity of the CCFLNN model is demonstrated through a full characteristic (working in the strongly nonlinear region) 170-W class AB amplifier driven by a multicarrier WCDMA signal. Furthermore, the proposed model has been applied for linearizing a real PA in multicarrier application. Results obtained from the measurement clearly show that the proposed digital predistorter can eliminate various intensity in-band and out-of band distortions. Index Terms—Behavioral modeling, complex-Chebyshev functional link neural network (CCFLNN), digital predistortion, inverse QR-decomposition-based recursive least square, memory effect, power amplifier (PA).

I. INTRODUCTION

T

HE radio frequency (RF) PAs, which are inherently nonlinear, are indispensable components in a wireless communication system. The nonlinearity of the PA is usually represented by both the magnitude compression and the phase distortion. The result is the bit error rate (BER) degradation within the channel and spectrum regrowth in adjacent channels. Manuscript received October 05, 2011; revised February 20, 2012; accepted February 22, 2012. Date of publication March 14, 2012; date of current version May 25, 2012. This work was supported in part by the Fundamental Research Funds for the Central Universities of China under Grant CDJRC10160012. The authors are with the College of Communication Engineering, Chongqing University, Chongqing Shapingba 400044, China (e-mail: myli2004@yahoo. com.cn; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2012.2189239

Co-channel interference inside the signal bandwidth causes deviations of the received signal constellation from the ideal reference signal constellation and degrades the BER at the receiver. Adjacent channel interference produces out-of-band signals and raises the noise floor in adjacent channels. Moreover, power efficiency is of major concern when designing wireless PAs. In the particular case of the amplification stage, any improvement in the power efficiency contributes significantly to power consumption reduction, considerably reduces the energy bill, which means the PA should be operated at a power level near its strongly nonlinear region, implying significant nonlinear distortion and spectral regrowth. To reduce the nonlinearity and improve the power consumption, a number of linearization techniques, such as feedforward [1], [2], feedback [3] and predistortion methods, [4], [5] were suggested in the literature to deal with these undesirable distortions. Among these linearization techniques, digital predistortion (DPD) is undeniably the most cost effective technique [5]. By taking advantage of the accuracy of digital signal processing, DPD offers reconfiguration capacity in synthesizing the predistortion function, which makes it suitable for multi-mode and multi-band applications. Although there are many techniques to perform DPD, the fundamental idea is that a predistorter is constructed to compensate the nonlinear compression characteristics representing the PAs. Then, the overall cascaded system (DPD+PA) approximates the linear and identity operator, and hence the nonlinearity of the amplifier is removed or reduced. In such a context, an essential first step in analyzing the PA system and designing a linearizer is to model the PA nonlinearity accurately. Behavioral modeling of RF PAs, in the context of advanced modulation and access techniques with high peak to average power ratios (PAPR) such as OFDM, WCDMA and LTE-advanced system etc., has become increasingly important and, to some extent, unavoidable in RF/DSP co-simulation and DPD linearization. The main focus of the behavioral modeling activity has thus far been on the development of models that can faithfully represent the nonlinear behavior of the amplifier. Their accuracy is highly sensitive to the adopted model structure and the parameter extraction procedure. However, as signal bandwidth increases particularly in multi-carrier spread spectrum communication systems, memory effects become obvious. To accurately model a PA, we have to take into account both nonlinearities and memory effects. Many behavioral models for RF PAs have been developed and evaluated in recent years. According to the several classified criteria, such as the inclusion or exclusion of memory effects, the number of

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boxes in the model and the different model structure, these reported models can be categorized as memoryless look-up table model [6], [7], Volterra model [8]–[11], Wiener and augmented Wiener model [12], [13], Hammerstein and Enhanced Hammerstein model [14], generalized memory polynomial model [15]–[17], neural network model [18]–[21], etc. In addition, an overview and comparative analysis of the complexity/accuracy tradeoff together with approximation capability of the various models according to the different signal bandwidth have been presented in [22]–[24]. However, as radio systems evolve to use much more complicated modulation schemes and wider signal bandwidth, these kinds of modeling techniques are still far from being mature since the behavioral models accuracy is highly sensitive to the adopted model structure and the parameter extraction procedure [24]–[26]. Meanwhile, the evaluation of the accuracy of behavioral models is essential in the selection of an appropriate model. For example, one important conclusion of the study given in [24] from theoretical framework was that, as some of the models are already universal approximants, it seems that behavioral model quality is nowadays more conditioned by the adopted parameter extraction process than by the model topology itself. That is, for much more complicated models, whose generality is excellent, must adopt complicated parameter estimation algorithms. A study of performance evaluation metrics for behavioral models of PAs is presented in [27]. The normalized absolute mean spectrum error (NAMSE), which provides a microscopic evaluation of the model performance in the spectral domain, is provided along with other evaluation criteria for accurate benchmarking of behavioral models. Moreover, to fairly compare the different models, the number of floating point operations (FLOPs) is employed in [28] for measuring the complexity. Recently, neural networks have emerged as a powerful learning technique to perform PA modeling and predistorter design due to their ability to learn based on optimization of an appropriate error function and their excellent performance for approximation of nonlinear function. Presently, most of the NN-based PA behavioral modeling and predistorter design techniques are based on multilayer feedforward networks, such as multilayer perceptron (MLP) trained with backpropagation (BP) or more efficient variation of this algorithm. For example, an adaptive predistortion technique based on a real-valued focused time-delay NN was presented in [29] for the linearization of 3G base-band PA. As an alternative to the MLP, there are has been considerable interest in radial basis function (RBF) network behavioral models [30], primarily because of its simpler structure. These established NN behavioral models can provide better performance for PAs with nonlinear memory effects, but most of these have complicated neural topologies and training algorithms, which increase the computation complexities, and it is difficult to implement these neural network models in digital signal processors (DSP). The functional link NN (FLNN) can be used for function approximation and pattern classification with faster convergence and lesser computational complexity than a MLP network. A lot of FLNN models using orthonormal functions for functional expansion for the problem of nonlinear dynamic system identifica-

tion have been reported [31]–[34]. It is shown that with proper choice of functional expansions, the FLNN is capable of performing better than MLP in the system identification problem. The Chebyshev FLNN is one class of the FLNN in which function expansion is carried out using orthogonal Chebyshev polynomials. A Chebyshev polynomial- based unified model NN for dynamic function approximation was reported in [32], which RLS learning algorithm is used for parameter estimation. It is pointed out that this network has universal approximation capability and has considerable faster convergence than a MLP network. In this paper, we propose a complex-Chebyshev FLNN structure for modeling the RF PAs with memory effects. To our knowledge, this is the first time that the CCFLNN is used for nonlinear dynamic system identification problem. Furthermore, the robust inverse QR-decomposition-based recursive least square (RLS) learning algorithm can significantly improve the model accuracy and well suite for DSP implementation. The proposed model is comparatively compared with real-valued focused time-delay NN model trained with different algorithm and conventional memory polynomial model in terms of normalized mean square error (NMSE) and adjacent channel error power radio (ACEPR). Additionally, The DPD model based on the proposed CCFLNN is validated for linearizing a class AB amplifier. The linearization performance of this predistorter is compared with the real-valued focused time-delay NN structure. The modeling and linearization performance clearly show that the CCFLNN model provides excellent results. This paper is organized as follows. Section II describes the proposed model. A robust inverse QR-decomposition-based RLS learning algorithm for CCFLNN model and the associated analysis of computational complexity are given in Section III. In Section IV, modeling results and performance are presented and discussed in detail by comparison with real-valued focused time-delay NN and conventional memory polynomial. The CCFLNN model is successfully applied in DPD system and the experimental results are presented in Section V. Finally, Section VI gives brief conclusion and discussion. II. CCFLNN BEHAVIORAL MODEL OF PAs The FLNN, initially proposed by Pao [35], is a single-layer NN structure capable of performing function approximation and pattern classification. Fig. 1 depicts the block diagram of an -dimensional input of FLNN model without any hidden layer, in which a functional expansion block is used to expand the dimension of the input pattern. The functional expansion effectively increases the dimensionality of the input vector and hence the hyperplanes generated by the FLANN provides greater discrimination capability in the input signal space. Thus, the FLNN is basically a flat net and the need of the hidden layer is removed and hence, the learning algorithm used in this network offers less computational complexity and higher convergence speed than those of other traditional NN. Fig. 1 shows how each input data and its delay is delivered to the function expansion module. Every output of the function expansion module is multiplied by the corresponding linear weight and all are summed up to carry out the FLNN output. Generally, a linear node in its output layer is used in the FLNN structure.

LI et al.: COMPLEX-CHEBYSHEV FUNCTIONAL LINK NEURAL NETWORK BEHAVIORAL MODEL

The dimension of the input pattern increase from 1 to basis function given by

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by a

(5) In this study, the functional expansion block comprises of a subset of orthogonal Chebyshev polynomials as shown in Fig. 1. The close-form expression for Chebyshev polynomials of any order [32] is written as (6) Fig. 1. FLNN model structure with an m-dimensional input.

However, we must do some modification for the FLNN model when the output layer has nonlinear activation functions in order to employ the linear least square learning algorithm. This modification is easy. In fact, we can use the inverse function theorem and choose a suitable activation function. Consequently, there exist a as new target data. The sigmoid function and hyperbolic sigmoid function often used in the neural networks will satisfy the inverse function theorem. Different from the already reported CFLNN model, every data transfer point and every processing unit in our FLNN model are all based on the complex-valued process. Considering the memory effects of the PA, the output of the model at instant k is a function of real values of present and past inputs, which can be represented by the following equation:

where is the integer part of , and is the order of Chebyshev polynomial expansion. The first few Chebyshev polynomials are given by

(7)

When there are multi-input signals, the entire Chebyshev functional expansion expression using the Chebyshev polynomials is given as follows [32]:

(1) where is the number of previous samples included in the model means that memory depth is introduced into this model. The structure of the FLNN model has input nodes corresponding to the complex baseband of the PA input and one output node corresponding to the complex baseband of the PA output . Based on the CCFLNN model shown in Fig. 1, (1) can be rewritten as follows:

(8) For example, if the order n of the Chebyshev functional expansion is set to 3, then (5) can be expanded as the following:

(2) where denotes the conjugate transpose, and the weight vector at instant is defined as (3) If a linear node in the FLNN model output is used, then (2) can be modified as follows:

(4)

(9) In this situation, the length of Chebyshev functional expansion is . Considering the baseband representation of passband nonlinearities, proper conjugation must be applied in (9). Such conjugation designation ensures that in the nonlinear case, PA AM/AM and AM/PM conversions are sufficient to characterize the device [36]. According to the baseband representation, (9)

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the

can be rewritten as follows:

desired response vector (14) posteriori error vector

and the

(15) (10) There exists an equivalent representation between the singlehidden MLP NN and the FLNN, which have been given in [32]. That is, assume the feedforward MLP NNs, which has only one hidden layer, and the activation functions of the output layer are all linear. If every activation function in hidden layer satisfies the Riemann integrable condition, then the feedforward NNs can always be represented as a unified model based on Chebyshev polynomials as follows: (11) where is the activation function input. We can conclude that the FLNN model provides the similar modeling capability compared with the MLP NN in the nonlinear system identification from this sense. III. PARAMETERS EXTRACTION OF CCFLNN BEHAVIORAL MODEL The design of a CCFLNN behavioral model is composed of two phases: the learning procedure and the testing phase. Learning procedure of the CCFLNN model commonly is performed with fitting the measured input and output complex equivalent baseband data using some learning algorithm. After training process is completed, the generalization capability of the trained network is checked in the testing phase. To do this, a set of input-output data pairs different from these used in the training phase is delivered to the CCFLNN to measure the performance of the model. Here, a complex-valued inverse QR-decomposition-based RLS algorithm is given in this section for the parameter estimation of the proposed CCFLNN model. A. Learning Algorithm for CCFLNN To obtain a recursive inverse QR-decomposition-based RLS algorithm, we first define the error signal at time instant as follows: (12)

We can combine the

(11) in a single equation as (16)

If we define the

exponential weighting matrix (17)

We can express the total squared error as follows: (18) Minimizing the objective function in (16) with respect to the weight vector results in (19) where the sample input-signal autocorrelation matrix is given by (20) and the sample cross-correlation vector by

is given (21)

The Cholesky decomposition of

is given by (22)

is a lower triangular Cholsesky decomwhere position matrix. The matrix is related to through an orthogonal rotation matrix as (23) In the inverse QR-decomposition-based RLS algorithm, matrix is updated instead of , and the CCFLNN weight vector is explicitly computed as a part of the algorithm. The motivation for computing matrix becomes clear if we combine the definition of the autocorrelation matrix in (22) with the weight update in the RLS algorithm

where

are the desired outputs at time instant and represent the outputs of CCFLNN model at time instant . Using the data matrix

(24) Then vector

.. .

.. .

..

.

.. .

is responsible for zeroing the new coming data as follows:

(13) (25)

LI et al.: COMPLEX-CHEBYSHEV FUNCTIONAL LINK NEURAL NETWORK BEHAVIORAL MODEL

Regardless of the type of triangularization to generate orthogonal matrix can be partitioned as

,

At this point, it is important to emphasize the structure as a product of Givens rotation matrices given by . Here, the complex Givens rotation is used for the implementation of inverse QRD-RLS algorithm to updating the CCFLNN model complex weighting matrix.

of (26)

where and the elements of , and depend on the type of triangularization (in our case, lower triangularization). These variables can be identified by manipulating (25), and (19) defines the variables involved in the structure of the rotation matrix

(27)

Now, consider the inverse of both sides of the update equation in (25). The inversion is possible if we first for matrix augment the matrix on the left side of (25) with the unit vector to make the matrix a square matrix. As a result, we get (28) By inverting and transposing both sides of (28), assuming that the inverse exits, we get

(29) Defining vector

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as (30)

Equation (29) can be written in the following compact form:

(31) Then (31) can be expressed as two equations: (32) and (33) in (33), we can compute If we know the value of vector the rotation matrix , which can then be used in (32) to compute . By comparing (27) and (32), we can rewrite (24) as (34)

B. Analysis of Computational Complexity It is well known that computational complexity is one of the important issues in implementing the behavioral model and DPD. In this section, we can present a comparison of computational complexity between the proposed CCFLNN model and the complex multi-layer MLP TDNN. Commonly, the computational complexity can be classified into identification complexity, running complexity and adaptation complexity [22]. Among the three complexities, adaptation complexity may be of less importance, and for the identification complexity comparison, a simple approach is to record the running time of the parameter learning algorithm. Moreover, the robustness, convergence speed and accuracy of the learning algorithm must also be compared to establish an optimal model. It is well known that the inverse QR-decomposition-based RLS algorithm employs orthogonal rotation operations to recursively update the weight, thus preserving the inherent stability properties and fast convergence properties of QR approaches and be fit for hardware implementation of digital circuit [37]–[39]. The gradient-based learning algorithm, generally adapted by the multi-layer MLP NN, has disadvantages, such as slow convergence, numerical instability and easily falls into a local minimum. Therefore, the learning algorithm of the CCFLNN model distinctly exceeds the learning algorithm of the MLP NN in the identification complexity. The error convergence curves of the inverse QR-decomposition-based RLS algorithm will be given in the following section. In this comparison, the focus is on running complexity due to its computational costs on the model implementation. The number of parameters and floating point operations (FLOPs) is widely used measure for running complexity [22]. Currently, there are three basic computations, i.e., multiplication, addition and computation of activation function involved for updating weights of the MLP and FLNN. The three computations in the network are due to the following steps: 1) forward calculations to get the activation value of all the nodes and the output value of the networks; 2) calculating the square error of the output layer; 3) updating weights of the entire network. Since FLOPs is actually a measure for the number of additions, subtractions and multiplications, then the three basic computations are used here for the comparison of running complexity. Let us consider an L-layer MLP with nodes in layer , , where and represent the number of nodes in the input and output layers, respectively. Considering the mostly application situation, we set the L to 2 or 3. That is, the one-hidden-layer and two-hidden-layer MLP are used for the comparison. The comparison of running complexity of

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TABLE I COMPARISON OF RUNNING COMPLEXITY BETWEEN AN 2-LAYER MLP, AN 3-LAYER MLP AND A CCFLNN

CCFLNN, one-hidden-layer and two-hidden-layer MLP using different learning algorithms during one iteration are summarized in Table I. It is obvious from Table I that the number of parameters and the three basic computations are much less in the case of CCFLNN than that of the two MLP network. IV. CCFLNN BEHAVIORAL MODEL VALIDATION In order to characterize the PA, the model validation tests are presented in this paper. By using the Agilent connected solution test bench [40], we captured the complex envelope data from the measured input and output of the PA, and then used them to extract and validate the behavioral model proposed. For a thorough comparison of the behavioral model performance, the real-valued focused time-delay NN model with different training algorithm, which has been proposed in [29] for DPD, and the conventional memory polynomial model [15] are given here once again. The real-valued focused time-delay NN model used for the comparison uses the real-valued form. A. Measurement Setup The test bench setup used the ADS-ESG-VSA89600 connected solution shown in Fig. 2 [40]. The IQ data files are constructed in ADS and sent to the Agilent Technologies E4438C ESG Vector Signal Generator using the Agilent connected solution. The ESG is used to modulate the data and up convert it to the RF frequency. The received data is acquired using the PSA (E4440A) and VSA89600 software in the IQ mode. The complex envelope data from the measured output of the device under test (DUT) is captured, and it would be used to extract and validate the behavioral modeling proposed. The captured IQ baseband signal of the PA is read back into MATLAB to be time aligned and further processed as necessary for model generation and model validation. Since the behavioral model performance is dependent on the input signal, two WCDMA signals, which were designed in ADS using the Test Model 1 3GPP complex modulation [41], have been used as the excitation for the model identification and validation in this study, a two-carrier WCDMA signal and a three-carrier WCDMA signal. The two-carrier WCDMA signal has a channel bandwidth of 10 MHz, and the composite input peak-to-average power radio equal to 9.87 [email protected]% probability on complementary cumulative distribution function

Fig. 2. Block diagram of the measurement setup used for evaluation of the behavioral models and DPD.

(CCDF). The three-carrier WCDMA signal has a channel bandwidth of 15 MHz, and the composite input peak-to- average radio (PAR) is 10.77 dB. The RF power amplifier under test is a class-AB PA using a Freescale MRF21170H MOSFET transistor designed for WCDMA base station applications with frequencies from 2110 to 2170 MHz. The class-AB amplifier is capable of producing approximately 52.75 dBm of output power at 1-dB compression point in the 2.14-GHz wireless band. A medium power PA (10 W peak power output) and a highly linear amplifier from Mini-Circuits precede the main output amplifier acting as driver amplifiers. Before the insertion of the PAs in the transmitter chain, a set of measurements and a calibration procedure to eliminate DC offsets was performed to ensure that no significant degradation was added by components in the closed-loop configuration. The output equivalent complex bansband data of the amplifier is collected at the 1-dB compression point output power levels. B. Model Evaluation Criterion Evaluation of the behavioral model performance of PAs exhibiting nonlinear memory effects is a very critical task. Accordingly, different metrics need be considered to evaluate the accuracy of a behavioral model in the predicting the in-band and out-band distortion of DUT behavior. In order to evaluate the in-band performance of PA behavioral models, the normalized square error (NMSE) is commonly used and is defined as [27]

dB

(35)

and are the measured and modeled where output waveforms, respectively, and is the number of sample points of the output waveform. In instances where the out-of-band performance of the PA is of more importance, the adjacent channel error power radio

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(ACEPR) can be used, which is defined as the radio between the power of the error signal and the power of the measured output signal within the channel. The ACEPR can be calculated for both the lower and upper adjacent channels. However, in this work, the average ACEPR is defined [28]. The average ACEPR is given by

(36) and are the discrete Fourier transforms where of and the error signal , respectively, and the error signal is defined as

Fig. 3. Real part comparison of the complex baseband data of the CCFLNN behavioral model and measured two-carrier WCDMA signals.

(37) C. Model Results A single-layer CCFLNN with the linear output node, as shown in Fig. 1, was used to illustrate the performance of this behavioral model. It contains one neuron in the output layer and the order of the Chebyshev functional expansion is set to 5. The number of taps in the input signal was set to 3 through an optimization procedure. For the CCFLNN, the input layer was expanded to 24 terms using functional expansion expression (8). We compared performance of the proposed CCFLNN with a three-layer real-valued focused time-delay NN [29] and a conventional memory polynomial [15]. For this purpose, we used the same architecture (7-15-2) of real-valued focused time-delay NN as used in [29]. The conventional memory polynomial used for the comparison has three delay taps and 9th odd-order nonlinearity. Ten-thousand (10 K) sample data for both the two WCDMA signals are used to train the CCFLNN and real-valued focused time-delay NN model respectively. Another ten-thousand (10 K) sample data from measurement at another period of time are used to test the behavioral model trained. For comparison between the performances of the three behavioral models, the two test signals previously presently (two-carrier and three-carrier WCDMA) were used. The model accuracy was evaluated using two criteria (NMSE and ACEPR). For each signal, the three models were identified. Through a comparative study of various training algorithms, the Levenberg-Marquardt (LM) BP algorithm was chosen as the most suitable algorithm for the real-valued focused time-delay NN topology since it achieved the lowest MSE performance. The conjugate gradients and the quasi-Newton (BFG) algorithms are narrowed down to much smaller values than the conventional gradient descent methods for the real-valued focused time-delay NN training. Here, the real-valued focused time-delay NN trained with the BFG algorithm is also used for the behavioral model comparison. The parameters of the memory polynomial are estimated using the same inverse QR-decomposition-based RLS algorithm employed in the CCFLNN model. The first verification of the CCFLNN model is to see how well it predicts the test data set, which has not been used in

the training. Fig. 3 presents a small sample of real part of the time-domain complex baseband data obtained with the proposed models when the two-carrier input signal is applied to the PA. It can be seen that the model predicts the measured data extremely well. The imaginary part of the complex baseband data exhibits the same excellent agreement between the model and the measured data. Fig. 4 depicts the comparison between the spectrum measured and that obtained using the CCFLNN model in response to the two-carrier WCDMA signal. A good matching is obtained even in the alternate channel. Similar behavior of the CCFLNN models was observed for the three-carrier WCDMA signal in Fig. 6. It demonstrates that the CCFLNN behavioral model also has good performance in the frequency domain. As the comparison, it can again be seen that the real-valued focused time-delay NN has good modeling capability only for in-band data form Fig. 5. The real-valued focused time-delay NN may eventually be able to give a better performance as the CCFLNN model through a sufficient training process. Whereas, the more time and computational resource will be spend in the process. As a comparison, a typical convergence curve of the CCFLNN learning process using the two-carrier WCDMA signals is shown in Fig. 7. It is obvious that the complex inverse QR-decomposition-based RLS algorithm has a very fast convergence speed and simultaneously preserves the inherent numerical stability properties, which make it extraordinarily suite for on-line behavioral modeling and DPD applications. To quantitatively compare the performances of the different models, two performance evaluation criterion (NMSE and ACEPR) were calculated for each signal. In Table II, the modeling performances of the proposed model are compared with the real-valued focused time-delay NN model trained with different algorithm. According to the results calculated in Table II, CCFLNN behavioral model led to the best NMSE and ACEPR performance, in comparison with the two other models. In addition, the real-valued focused time-delay NN model trained with Levenberg-Marquardt Algorithm (LMA) resulted in comparable performance with memory polynomial model for the two-carrier WCDMA signals. For the three-carrier WCDMA signals The NMSE and ACEPR of the memory polynomial model are limited to 39.54

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Fig. 4. PSD comparison between the CCFLNN behavioral model and the measurement data for the two-carrier WCDMA signal.

Fig. 7. Convergence curve of the learning process of the inverse QR- decomposition-based RLS algorithm.

TABLE II COMPARISON OF CALCULATED PERFORMANCE EVALUATION CRITERIONS FOR CCFLNN, REAL-VALUED FOCUSED TIME-DELAY NN TRAINED WITH DIFFERENT ALGORITHM AND MEMORY POLYNOMIAL

Fig. 5. PSD comparison between the real-valued focused time-delay NN behavioral model trained with LM algorithm and the measurement data for the two-carrier WCDMA signal.

Fig. 6. PSD comparison between the CCFLNN behavioral model and the measurement data for the three-carrier WCDMA signal.

and 43.30 dB respectively. And the real-valued focused time-delay NN model trained with BFG algorithm appeared to be the least accurate model among those considered. The above results indicate that the CCFLNN behavioral model describes the dynamical behavior of the amplifier accurately. Given the statistical nature of the drive signal, it is important that the signal statistics are also compensated by the model. This can be verified by observing the complementary

cumulative distribution function (CCDF) for the measured data and the modeled signal [20]. The CCDF is a statistical method that shows the amount of time the signal spends above any given power level. The need for CCDF arises primarily when dealing with digitally modulated signals in spread spectrum systems such as cdma2000 and WCDMA. Because these types of signals are noise-like, CCDF curves provide a useful characterization of the signal power peaks. Using CCDF curves, power amplifier designers know exactly how stressful a signal the amplifier will need to handle. The CCDF curve can also be used to determine the impact of filtering on a signal. As can be seen in Fig. 8, the measured and modeled output signals have very similar compression curves compared with the input signal, indicating that the model has not only preserved the amplifier dynamics and memory behavior, but also reproduced the signal statistics. V. DPD LINEARIZATION The proposed CCFLNN model, as well as the considered real-valued focused time-delay NN-LMA models, can also be applied to DPD. In a predistortion algorithm, the choice of predistorter structure and its computation algorithm have the same critical importance. To validate effectiveness of these predistorters, a Matlab/ADS platform is used to linearize the

LI et al.: COMPLEX-CHEBYSHEV FUNCTIONAL LINK NEURAL NETWORK BEHAVIORAL MODEL

Fig. 8. CCDF curves for input signals, measured and modeled output complex baseband signals.

class-AB amplifier presented in the above section. This platform has been given in Fig. 2 which representing a transmitter for 3G WCDMA signals. It can be shown that the platform is composed of a forward path and a feedback loop. A sample from the signal at the output of the power amplifier is attenuated in the feedback path. This signal is down-converted to IF and sampled to obtain the IQ components of the complex modulated signal within the PSAE4443A. These signals are collected via the VSA89600 and put into the Matlab, and further compared to the real IQ components of the signal sent to the power amplifier. A DPD model is extracted and validated using the proposed method in above section. Then the model coefficients are applied to the DPD block [42]. In the forward path, the generated predistorted signals were downloaded into the ESG4438C and then modulated and up-converted to RF and fed to the PA. The proposed predistortion scheme was validated with a 2.14-GHz class AB amplifier, which was excited with threecarrier WCDMA signal. This signal has a PAPR of 9.8 dB and a total bandwidth of 10 MHz, and the sampling rate is 92.16 million samples per second. An indirect learning architecture is employed to update the parameters of the CCFLNN model. The advantage of this approach is that it eliminates the need for PA model assumptions and parameter estimation. To illustrate the superior compensation capability, Fig. 9 shows the measured spectra at the output of the linearized PA obtained using two different DPD scheme (CCFLNN, real-valued focused time-delay NN-LMA), with the dimensions previously used for behavioral modeling. Fig. 9 also presents the measured output spectra when no DPD was applied. For each predistorter, the ACPR (adjacent channel power radio) at the output of the linearized PA was obtained at two frequency offsets around the carrier frequency ( 5 MHz, 10 MHz). The achieved results are summarized in Table III. The predistortion performance achieved in this study is comparable with that proposed in [28], [29] under the condition of higher PAPR. If the decresting algorithm with soft clipping and filtering is used, then the predistortion performance will be further improved. At this point, it is important to emphasize that the behavioral model and DPD parameter extraction procedure is different from previous work. An important benefit of this com-

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Fig. 9. PSD comparison of different scenarios for two-carrier WCDMA signal.

TABLE III SUMMARY OF THE ACPR WITH THE DPD LINEARIZATION RESULTS

plex inverse QR-decomposition-based RLS algorithm is that the Givens rotation computations are easily mapped onto systolic array structure for a parallel implementation [37]. This is a very important aspect of the presented PA behavioral model and DPD. This means that such a parallel implementation can make model-based design of predistorter systems or systemlevel RF/DSP Co-simulation a reality. VI. CONCLUSION In this paper, a novel computationally efficient behavioral model based on complex-Chebyshev functional link neural network (CCFLNN) was proposed to model and compensate for the distortion of PAs exhibiting the memory effect. Using the complex inverse QR-decomposition-based RLS learning algorithm, the proposed model joins good prediction ability with practical implementation characteristics. Furthermore, the inverse QR-decomposition-based RLS method employs orthogonal rotation operations to recursively update the weights, thus preserves the inherent numerical stability properties of QR approaches. The proposed model is comparatively compared with the real-valued focused time-delay NN behavioral model and the memory polynomial model with respect to computation complexities and modeling performance. The results of the modeling assessment clearly show that the CCFLNN behavioral model outperforms the real-valued focused time-delay NN model trained with different algorithms and memory polynomial model. Furthermore, the proposed model has been applied for linearizing the real PA in multi-carrier application.

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Experimental results have shown that by employing the proposed structure, both nonlinear distortion and memory effects of the PA driven with three-carrier WCDMA signal can be significantly reduced. REFERENCES [1] P. B. Kenington, High-Linearity RF Amplifier Design. Norwood, MA: Artech House, 2000. [2] Y. Yang, Y. Y. Woo, and B. Kim, “Optimization for error-canceling loop of the feedforward amplifier using a new system-level mathematical model,” IEEE Trans. Microw. Theory Tech., vol. 51, no. 2, pp. 475–482, Feb. 2003. [3] Y. Kim, Y. Yang, S. Kang, and B. Kim, “Linearization of 1.85 GHz amplifier using feedback predistortion loop,” in Proc. IEEE MTT-S Int. Microw. Symp. Dig., Jun. 1998, pp. 1678–1678. [4] J. Yi, Y. Yang, M. Park, W. Kang, and B. Kim, “Analog predistortion linearizer for high power RF amplifier,” IEEE Trans. Microw. Theory Tech., vol. 48, no. 12, pp. 2709–2713, Dec. 2000. [5] S. C. Cripps, RF Power Amplifiers for Wireless Communications, 2nd ed. Norwood, MA: Artech House, 2006. [6] K. J. Muhonen, M. Kavehrad, and R. Krishnamurthy, “Look-up table techniques for adaptive digital predistortion: A development and comparison.,” IEEE Trans. Veh. Technol., vol. 49, no. 9, pp. 1995–2002, Sep. 2000. [7] J. K. Cavers, “Amplifier linearization using a digital predistorter with fast adaptation and low memory requirements,” IEEE Trans. Veh. Technol., vol. 39, no. 4, pp. 374–382, Nov. 1990. [8] D. Mirri, G. Iuculano, F. Filicori, G. Pasini, G. Vannini, and G. P. Gualtieri, “A modified Volterra series approach for nonlinear dynamic systems modeling,” IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 49, no. 8, pp. 1118–1128, Aug. 2002. [9] A. Zhu and T. J. Brazil, “Behavioral modeling of RF power amplifiers based on pruned Volterra series,” IEEE Microw. Wireless Compon. Lett., vol. 14, no. 12, pp. 563–565, Dec. 2004. [10] N. Safari, T. Røste, P. Fedorenko, and J. S. Kenny, “An approximation of Volterra series using delay envelopes, applied to digital predistortion of RF power amplifiers with memory effects,” IEEE Microw. Wireless Compon. Lett., vol. 18, no. 2, pp. 115–117, Feb. 2008. [11] A. Zhu, P. J. Draxler, J. J. Yan, T. J. Brazil, D. F. Kimball, and P. M. Asbeck, “Open-loop digital predistorter for RF power amplifiers using dynamic deviation reduction-based volterra series,” IEEE Trans. Microw. Theory Tech., vol. 56, pp. 1524–1534, Jul. 2008. [12] C. J. Clark, G. Chrisikos, M. S. Muha, A. A. Moulthrop, and C. P. Silva, “Time-domain envelope measurement technique with application to wideband power amplifier modeling,” IEEE Trans. Microw. Theory Tech., vol. 46, pp. 2531–2540, Dec. 1998. [13] T. Liu, S. Boumaiza, and F. M. Ghannouchi, “Deembedding static nonlinearities and accurately identifying and modeling memory effects in wideband RF transmitters,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 11, pp. 3578–3587, Nov. 2005. [14] T. Liu, S. Boumaiza, and F. M. Ghannouchi, “Augmented Hammerstein predistorter for linearization of broadband wireless transmitters,” IEEE Trans. Microw. Theory Tech., vol. 54, no. 4, pp. 1340–1349, Apr. 2006. [15] L. Ding, G. T. Shou, D. R. Morgan, Z. Ma, J. S. Kenney, J. Kim, and C. R. Giardina, “A robust digital baseband predistorter constructed using memory polynomial,” IEEE Trans. Commun., vol. 52, no. 1, pp. 159–165, Jan. 2004. [16] J. Kim and K. Konstantinou, “Digital predistortion of wideband signals based on power amplifier model with memory,” Electron. Lett., vol. 37, no. 23, pp. 1417–1418, Nov. 2001. [17] D. R. Morgan, Z. Ma, J. Kim, M. G. Zierdt, and J. Pastalan, “A generalized memory polynomial model for digital predistortion of RF power amplifiers,” IEEE Trans. Signal Process., vol. 54, no. 10, pp. 3852–3860, Oct. 2006. [18] T. Liu, S. Boumaiza, and F. M. Ghannouchi, “Dynamic behavioral modeling of 3G power amplifiers using real-valued time delay neural networks,” IEEE Trans. Microw. Theory Tech., vol. 52, no. 3, pp. 1025–1033, Mar. 2004. [19] M. Isaksson, D. Wisell, and D. Rönnow, “Wide-band dynamic modeling of power amplifiers using radial-basis function neural networks,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 11, pp. 3422–3428, Nov. 2005.

[20] J. Wood, M. LeFevre, D. Runton, J. C. Nanan, B. H. Noori, and P. H. Aaen, “Envelope-domain time series (ET) behavioral model of a doherty RF power amplifier for system design,” IEEE Trans. Microw. Theory Tech., vol. 54, no. 8, pp. 3163–3172, Aug. 2006. [21] J. F. Zhai, J. Y. Zhou, and L. Zhang et al., “The dynamic behavioral model of RF power amplifiers with the modified ANFIS,” IEEE Trans. Microw. Theory Tech., vol. 57, no. 1, pp. 27–35, Jan. 2009. [22] A. S. Tehrani, H. Cao, S. Afsardoost, T. Eriksson, M. Isaksson, and C. Fager, “A comparative analysis of the complexity/accuracy tradeoff in power amplifier behavioral models,” IEEE Trans. Microw. Theory Tech., vol. 58, no. 7, pp. 1510–1520, Jun. 2010. [23] M. Isaksson, D. Wisell, and D. Rönnow, “A comparative analysis of behavioral models for RF power amplifiers,” IEEE Trans. Microw. Theory Tech., vol. 54, no. 1, pp. 348–359, Jan. 2006. [24] J. C. Pedro and S. A. Maas, “A comparative overview of microwave and wireless power-amplifier behavioral modeling approaches,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 4, pp. 1150–1163, Apr. 2005. [25] A. Zhu, J. C. Pedro, and T. J. Brazil, “Dynamic deviation reduction based Volterra behavioral modeling of RF power amplifiers,” IEEE Trans. Microw. Theory Tech., vol. 54, no. 12, pp. 4323–4332, Dec. 2006. [26] T. R. Cunha, J. C. Pedro, and P. M. Cabral, “Design of a power-amplifier feed-forward RF Model with physical knowledge considerations,” IEEE Trans. Microw. Theory Tech., vol. 55, no. 12, pp. 2747–2756, Dec. 2007. [27] O. Hammi, M. Younes, and F. M. Ghannouchi, “Metrics and methods for benchmarking of RF transmitter behavioral models with application to the development of a novel hybrid memory polynomial model,” IEEE Trans. Broadcast., vol. 56, no. 3, pp. 350–357, Sep. 2010. [28] J. Moon and B. Kim, “Enhanced Hammerstein behavioral model for broadband wireless transmitters,” IEEE Trans. Microw. Theory Tech., vol. 59, no. 4, pp. 924–933, Apr. 2011. [29] M. Rawat, K. Rawat, and F. M. Ghannouchi, “Adaptive digital predistortion of wireless power amplifiers/transmitters using dynamic realvalued focused time delay line neural networks,” IEEE Trans. Microw. Theory Tech., vol. 58, no. 1, pp. 95–104, Jan. 2010. [30] M. Li, S. He, and X. Li, “Complex radial basis function networks trained by QR-decomposition recursive least square algorithms applied in behavioral modeling of nonlinear power amplifiers,” in Int. J. RF Microw. Comput.-Aided Eng., 2009, vol. 19, no. 6, pp. 634–646. [31] J. C. Patra and A. C. Kot, “Nonlinear dynamic system identification using Chebyshev functional link artificial neural network,” IEEE Trans. Syst., Man, Cybern. B, Cybern., vol. 32, no. 4, pp. 505–511, Aug. 2002. [32] T. T. Lee and J. T. Jeng, “The chebyshev polynomial based unified mode! neural networks for function approximations,” IEEE Trans. Syst., Man Cybern., vol. 28, no. 6, pt. B, pp. 925–935, Jun. 1998. [33] W. D. Weng, C. S. Yang, and R. C. Lin, “A channel equalizer using reduced decision feedback Chebyshev functional link artificial neural networks,” Inf. Sci., vol. 177, no. 13, pp. 2642–2654, 2007. [34] H. Zhao and J. Zhang, “Pipelined Chebyshev functional link artificial recurrent neural network for nonlinear adaptive filter,” IEEE Trans. Syst., Man, Cybern., vol. 40, no. 1, pt. B, pp. 162–172, Feb. 2010. [35] Y. H. Pao, Adaptive Pattern Recognition and Neural Networks. Reading, MA: Addison Wesley, 1989. [36] G. T. Zhou, H. Qian, L. Ding, and R. Raich, “On the baseband representation of a bandpass nonlinearity,” IEEE Trans. Signal Process., vol. 53, no. 8, pp. 2953–2957, Aug. 2005. [37] S. T. Alexander and A. L. Ghirnikar, “A method for recursive least squares adaptive filtering based upon an inverse QR decomposition,” IEEE Trans. Signal Process., vol. 41, no. 1, pp. 20–30, Jan. 1993. [38] P. S. R. Diniz, Adaptive Filtering: Algorithms and Practical Implementation, 2nd ed. Norwell, MA: Kluwer, 2002. [39] S. D. Muruganathan and A. B. Sesay, “A QRD-RLS-based predistortion scheme for high-power amplifier linearization,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 10, pp. 1108–1112, Oct. 2006. [40] “Connected simulation and test solutions using the advanced design system,” Agilent Technol.. Palo Alto, CA, Applicat. Notes 1394, 2000. [41] F. Fernet, “An ADS bench for generating multi-carrier 3GPP WCDMA ACLR test signals,” High Freq. Electron., pp. 34–42, Nov. 2002. [42] L. Ding, Z. Ma, D. R. Morgan, M. Zierdt, and G. T. Zhou, “Compensation of frequency-dependent gain/phase imbalance in predistortion linearization systems,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 1, pp. 390–397, Jan. 2008.

LI et al.: COMPLEX-CHEBYSHEV FUNCTIONAL LINK NEURAL NETWORK BEHAVIORAL MODEL

Mingyu Li received the Ph.D. degree in electronic engineering from the University of Electronic Science and Technology of China (UESTC), Chengdu, China, in 2009. He is currently a lecturer with the College of Communication Engineering, Chongqing University, Chongqing, China. His main research interests include nonlinear modeling and linearization of wideband power amplifiers for wireless applications, statistical and adaptive signal processing for wireless communications and nonlinear system identification

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Yang Jiang is an Associate Professor with the College of Communication Engineering, Chongqing University, Chongqing, China. His research interests are in the area of wireless communication and nonlinear signal processing.

techniques.

Jinting Liu received the B.Sc. degree in electronic engineering from Binzhou Institute, China, in 2011. He is currently working towards the M.Sc. degree in communication engineering at the Chongqing University, Chongqing, China. His research interests include digital predistortion and software defined radio.

Wenjiang Feng is a Professor with the College of Communication Engineering, Chongqing University, Chongqing, China. His research interests focused on digital signal processing and Cognitive Radio.

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Subsampling Feedback Loop Applicable to Concurrent Dual-Band Linearization Architecture Seyed Aidin Bassam, Member, IEEE, Andrew Kwan, Member, IEEE, Wenhua Chen, Senior Member, IEEE, Mohamed Helaoui, Member, IEEE, and Fadhel M. Ghannouchi, Fellow, IEEE

Abstract—This paper demonstrates an energy-efficient and low-complexity subsampling receiver adopted in the feedback loop of the dual-band power amplifier (PA) linearization architecture. The challenges and issues on finding the valid subsampling frequencies in nonlinear system are discussed, and a systematic approach for finding valid subsampling frequencies is presented. The subsampling-based receiver is applied as a proper solution for the feedback loop of the dual-band linearization architecture. It is shown that the subsampling feedback loop reduces the complexity and the cost of the dual-band linearization architecture. The simulation and measurement results show the proper functionality of the presented technique and demonstrate a good linearization performance. The measurement results show that when using this method, more than 15-dB improvement in normalized mean squared error and more than 17-dB improvement in adjacent channel power ratio are achieved for a wideband class-AB PA, compared with the unlinearized method. Index Terms—Dual-band transmitter, linearization technique, nonlinear system, subsampling technique.

I. INTRODUCTION

S

UBSAMPLING, or bandpass sampling, is a technique for sampling the band-limited RF signal at a rate much lower than Nyquist rate [1], [2]. The subsampling technique has been considered as a flexible solution for reconfigurable radio receivers, particularly in multistandard applications [3]–[5]. As multistandard transceivers are more and more ubiquitous in the cellular industry, the needs for more flexible topologies with fewer RF components and lower power consumption become critical. Manuscript received September 30, 2011; revised February 29, 2012; accepted March 05, 2012. Date of publication April 24, 2012; date of current version May 25, 2012. This work was supported by the Alberta Innovate Technology Futures (AITF), the Natural Sciences and Engineering Research Council of Canada (NSERC), and the Canada Research Chairs (CRC) Program. S. A. Bassam was with the Intelligent RF Radio Laboratory (iRadio Lab), Department of Electrical and Computer Engineering, University of Calgary, Calgary, AB, Canada T2N 1N4. He is now with the Hardware Engineering Team, Powerwave Technologies, Santa Ana, CA 92705 USA (e-mail: sabassam@ieee. org). A. Kwan, M. Helaoui, and F. M. Ghannouchi are with the Intelligent RF Radio Laboratory (iRadio Lab), Department of Electrical and Computer Engineering, University of Calgary, Calgary, AB, Canada T2N 1N4 (e-mail: [email protected]; [email protected]; [email protected]). W. Chen was with the Intelligent RF Radio Laboratory (iRadio Lab), Department of Electrical and Computer Engineering, University of Calgary, Calgary, AB, Canada T2N 1N4. He is now with the Department of Electronic Engineering, Tsinghua University, Beiing 100084, China (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2012.2192745

A power-efficient, low-complex, and reconfigurable radio system requires the design of energy-efficient transmitter and receiver architectures. At the transmitter side, the power consumption is mainly dominated by the RF power amplifier (PA) unit. Generally, PAs are the most power consuming and the least power efficient active devices in the RF chain. Moreover, their nonlinear behavior and nonflat frequency response introduce unwanted intermodulation distortions into the system, which could significantly degrade the output signal quality. At the receiver side, the low-complexity, reduced number of RF components, and reconfigurability features of the subsampling architecture make it suitable for energy-efficient transceivers. This paper demonstrates an energy-efficient and low-complexity dual-band PA linearization architecture based on a subsampling receiver in the feedback loop. The subsampling receiver architecture is designed to concurrently down-convert the dual-band RF signals through a single receiver chain. As explained later in this paper, using a subsampling technique simplifies the feedback loop topology, requires fewer number of RF components, and reduces the power consumption. The linearization technique is based on the well-known digital predistortion (DPD) linearization [6]. The DPD technique [6] compensates for the transmitter nonlinearity while operating in the high-efficiency and nonlinear region. This is achieved by passing the input signal to a normalized inverse function of the PA, where the cascade of the inverse function and the nonlinear PA results in a system with linear gain. Fig. 1 is a block diagram of a predistortion system, where is the baseband input signal to the PA. The baseband to RF conversion consists of a digital-to-analog converter (DAC) to convert the signal into the analog domain, and an up-conversion unit to translate into RF domain. Conversely, the feedback loop includes a RF down-conversion unit and an analog-to-digital converter (ADC), where the output is fed into a digital signal-processing unit. The input signal ( ) and attenuated output of the PA ( ) are used to generate the inverse behavioral model of the PA, where the predistorter is set to unity gain for initial characterization. The predistorter is adaptively updated to compensate for dynamic effects that are exhibited by the PA. Reference [7] presented a concurrent dual-band IF DPD linearization architecture using a subsampling receiver. The two RF signals are concurrently down-converted to two known IF signals, and a single processing block had been used to compensate for the distortions. The proposed architecture has been simulated where the results show signal quality improvements after linearization. As shown in [8]–[10], dual-band nonlinear devices will produce intermodulation, cross modulation, and harmonic products

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BASSAM et al.: SUBSAMPLING FEEDBACK LOOP

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Fig. 1. Block diagram of a general DPD linearization block.

caused by the two fundamental signals. In order to obtain samples from the output of the dual-band system, a dual-branch or dual-band down converter is conventionally needed in the feedback loop, which increases the complexity and power consumption of the DPD linearization block. Substituting the dualband or dual-branch receiver feedback loop of the linearization topology with subsampling receiver architecture reduces the complexity of the system. The subsampling down conversion is not very common as receivers because of its poor performance in the presence of uncontrolled interfering signals. However, in the case of a DPD feedback loop, the problem is different and the interfering signals can be controlled to not affect the signal quality. The different intermodulation, cross modulation, and harmonic products make choosing the sampling frequency a complex task in order to avoid any overlap between the down-converted desired signals and their intermodulation and cross-modulation products. Therefore, it is imperative to develop an algorithm to select the sampling frequency so that it takes into account all the possible frequencies such that the target signals will not be interfered with. The methodology of using 2-D DPD for a concurrent dualband PA is presented and demonstrated in [9]. Here, in this paper, the same technique is considered and simplified further and the subsampling theory has been adopted to develop a new feedback loop architecture. Comparing to [9], a more efficient configuration has been developed and implemented using commercially available components. This paper is organized as follows. Section II briefly overviews the subsampling technique and demonstrates the concept of its operation. Section III demonstrates the adoption of the subsampling technique into the feedback loop of the digital linearizer block and introduces the principle of the concurrent dual-band linearization algorithm. Section IV first covers the difficulties and challenges in using the subsampling technique in dual-band nonlinear systems and then describes the algorithm used to generate valid subsampling frequencies where signals do not overlap with the fundamental signals. Section V shows the computer simulated results. Finally, Section VI presents subsampling measurement results for the ADC used, and predistortion performance using a subsampling receiver architecture for the feedback loop. II. SUBSAMPLING TECHNIQUE AND ITS OPERATION Sampling the band-limited RF signal at frequency rates much lower than the carrier frequency, but higher than signal band-

Fig. 2. Block diagram of a general subsampling receiver.

Fig. 3. Power spectrum of the signal at the input (top) and output (bottom) of a nonlinear dual-band transmitter.

width, folds the RF signal to the lower frequencies, where these replicates of the RF signal at baseband or IFs can be used to reconstruct the baseband signal. To make sure that there is no aliasing between the replicas, the subsampling rate, , should be chosen in the following range (1):

where Nyquist Rate

(1)

where and are the lower and upper frequencies of the band-limited RF signal, is the signal bandwidth, and is an integer value. Fig. 2 shows a general block diagram of subsampling-based receiver. It consists of an RF bandpass filter, a low-noise amplifier (LNA), a track and hold (T&H), and an ADC followed by a baseband digital signal processing (DSP) unit. The T&H is required to expand the analog bandwidth of the receiver and defines the RF range of receiver operation. The sampling clock of the T&H and ADC are chosen from (1) to avoid any aliasing.

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Fig. 4. Block diagram of a dual-band adaptive linearization system.

III. SUBSAMPLING TECHNIQUE IN DUAL-BAND DPD LINEARIZATION ARCHITECTURE A. Dual-Band DPD Linearization Architecture The single-band adaptive predistortion system shown in Fig. 1 can be extended to accommodate a dual-band predistortion application. For a dual-band operation transmitter with nonlinearity, the first and second bands will produce intermodulation (nonlinearity components within the band), cross-modulation (mixing within the two bands), and harmonics (integer multiple of the band) products. Typically, these unwanted components should be attenuated by the PA circuit and/or bandpass filters. Fig. 3 shows the power spectrum of the input signal, and the output signal when passed through a third-order nonlinear system. The system block diagram of the dual-band linearization architecture is displayed in Fig. 4 [9], [10]. The input signals, and , are fed into two distinct predistorters. This design allows for the compensation of cross-modulation and intermodulation products caused by the fundamental signals. The predistorter outputs are up-converted and added in the RF domain through the use of a power combiner. The feedback path of the dual-band linearizer requires the use of two down-conversion stages, as well as bandpass filters to remove most of the imperfections caused by the PA. The inputs to the PA, and , as well as the time-aligned output of each band of the PA, and , are used to generate the predistorter. The kernel of the linearization processing algorithm for prediction and compensation of the distortions and intermodulations is as follows [9]:

(2)

The kernels of (2) can be found through a least squares approach. The DPD equations can be derived by exchanging the variables and . After the coefficients have been found, applying both input signals to each predistorter will generate the predistorted signals for a linearized system [9]. This feedback architecture as presented in [9] and [10] is based on two separate feedback loops for each of the active RF bands. This requires additional signal-processing resources for the signal’s time alignment and also needs extra RF components. As explained in the following sections, two feedback loops are simplified into a single feedback loop by using the modified subsampling receiver architecture. B. Dual-Band DPD Linearization Architecture With Subsampling-Based Feedback Loop Concurrent multiband receiver architectures traditionally require a bandpass filter, down-conversion stage, and ADC for the translation of each RF frequency to baseband. Using subsampling with a high-speed ADC allows the elimination of all these components; however, the user needs to make sure the signals do not overlap in the subsampled spectral domain. Sampling multiple bands at the same time also eliminates the time delay taken between different band paths caused by the filters. Fig. 5 displays the dual-band predistortion architecture with a subsampling feedback loop. After subsampling of the PA output, the desired frequency bands are digitally filtered and down-sampled to acquire their respective baseband waveforms. Compared with a traditional subsampling receiver, the subsampling feedback loop does not have to handle issues such as unwanted signal interference that may exist in a wireless channel. Requirements such as high dynamic range, linearity, and sampling frequency are critical for selecting an ADC for this architecture. In addition, [11] discusses the effect of clock jitter on the ADC sampling accuracy. Oversampling the signal helps reduce the effects of jitter on the system; therefore, the subsampling frequency chosen should be relatively close to the maximum operating frequency of the ADC.

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1993

Fig. 5. Dual-band DPD with subsampled feedback loop.

TABLE I RANGES OF VALID SAMPLING FREQUENCIES FOR A DUAL-BAND SIGNAL

Fig. 6. Truncated frequency axis of two signal bands at their RF frequencies.

IV. VALID SUBSAMPLING FREQUENCIES NONLINEAR DUAL-BAND SIGNALS

FOR

A. Subsampling Frequencies for the Fundamental Dual-Band Signals The subsampling frequency range in (1) is valid for singleband RF signal. In [8], the subsampling approach was extended for the scenario where the signal-band RF signal and its harmonics are available. The universal formula to find all the valid subsampling frequencies in the presence of the signal harmonics is based on the following criterion [8]: (3) where and are any two of the harmonics of the and is an integer value as follows:

to ensure that the two signals do not overlap in the subsampled domain. An algorithm is described in [4] that can generate a list of valid subsampling frequencies for a dual-band system. Denoting the bands for the lower band, and for the upper band, the lower and upper signal boundaries can be defined as (5)

The maximum replica order of the lower band ( strained by the following:

) is con-

signal (6) (4)

is the largest integer smaller or equal to . Extending where it for the dual-band signals requires major modification and further analysis. Considering two RF signals at carrier frequencies of and , with their respective bandwidths and , as shown in Fig. 6, the subsampling frequency, , must be chosen

Using the relation orders of the upper band

, the constraint for valid replica is (7)

Table I lists all the possible subsampling frequencies for a dual-band RF signal, defined in [4].

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B. Subsampling Frequencies for Nonoverlapping Intermodulation, Cross Modulation, and Harmonic Frequencies The intermodulation, cross-modulation, and harmonics generated by the fundamental signals are not required for the predistortion application. A relaxed version of the algorithm in Section IV-A can be used, where the unwanted signals’ only restriction is not to overlap with the fundamental tones, and may be aliased over another unwanted signal. For Fig. 6 and setting , the modified formula from (3) is as follows: (8) where , is the restricted fundamental signal (either or ), and is the interfering signal (a intermodulation, cross-modulation, or harmonic). The maximum value of can be constrained by the following formula: (9) To find the sampling frequency upper bound, the bandwidths of the two frequencies must not overlap with each other. Thus, the following upper bound constraint must hold: (10) Rearranging (10), the upper sampling frequency bound can be found as (11) Similarly, the sampling frequency lower bound can be computed from the following:

Fig. 7. Flowchart demonstrating the steps involved in finding the valid frequencies .

(12)

adopted for this study since the main objective is to have all the possible solutions and to select the proper subsampling frequency.

(13)

V. COMPUTER SIMULATION—VALID SUBSAMPLING FREQUENCIES

resulting in

must be considTo account for the image frequency, ered, and (8)–(13) can be repeated with . The valid subsampling frequencies are the ones that can be found in both and . Cycling through all the possible (intermodulation, cross-modulation, and harmonic signals) with the possible fundamental signals ( , ) will give all the possible subsampling frequencies. A flowchart of finding valid subsampling frequencies is shown in Fig. 7, where using the method described in Sections IV-A and IV-B are used. A MATLAB script is written based on this to find the valid frequency and is used in the following sections for both simulation and measurement validations. Reference [12] demonstrated an integrative algorithm to find the minimum valid subsampling frequency with lower computational complexity. However, this approach is not

Computer simulation using MATLAB is performed to find the valid subsampling frequency for concurrent 5-MHz signals at the carrier frequencies of 880 and 1978 MHz. The PA is modeled as fifth-order nonlinear system where intermodulation, cross-modulation, and harmonic up to fifth order have been considered. Since it is assumed that PA nonlinearity is of fifth order, the intermodulation products around each fundamental frequency introduce distortions and out-of-band regrowth at about five times the bandwidth. Therefore, a guard interval of five times the signal bandwidth is considered around each fundamental frequency to make sure that there is no overlap with any interfering signals. Table II shows the valid subsampling frequency ranges up to 1 GHz.

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TABLE II VALID SUBSAMPLING FREQUENCIES UP TO 1 GHz

TABLE III PREDICTED RF AND BASEBAND FREQUENCIES USING SUBSAMPLED FREQUENCY OF 619.8 MHz

A

From Table II, a subsampling frequency of 619.8 MHz from the first valid frequency zone is chosen for further simulation and measurement validations. After subsampling, the resulting IF from its RF center frequency counterpart is determined as follows: if

is even (14) if

is odd

is the center frequency at RF, is the IF, is the where sampling frequency, and is the remainder of the division operation. Table III shows a list of the RF and subsampled baseband frequencies, while Fig. 8(a) shows the spectrum of signal at the output of the nonlinear PA with up to the fifth-order intermodulation, cross modulation, and harmonic products from 0 to 4000 MHz. By subsampling the signals at Fig. 8(a) with sampling frequency of 619.8 MHz, the replicas of the signals are located at frequencies as shown in Fig. 8(b). The values of fundamental and harmonic frequency terms are presented in Table III. Fig. 8(b) shows that the signals of interest [880 MHz (blue in on-

Fig. 8. (a) Predicted RF fundamental and harmonics up to 4 GHz. (b) Subsampled result using a sampling frequency of 619.8 MHz.

line version), 1978 MHz (red in online version)] do not overlap with any of the harmonics and intermodulation signals and have sufficient guard band such that the spectral regrowth caused by the nonlinearity of the fundamental signals will not overlap with any interfering signals. VI. EXPERIMENTAL RESULTS The experimental setup of the dual-band linearization architecture in Fig. 5 is developed as presented in Fig. 9. The

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Fig. 9. Experimental setup for dual-band linearization architecture.

nonlinear device-under-test is a Doherty-based concurrent dual-band PA using Cree CRF24010 transistors operating at 880- and 1978-MHz frequency bands [13]. Two independent WCDMA signals are downloaded into the two baseband time-aligned Agilent E4438C vector signal generators, and up-converted to the desired lower and upper RF frequencies. The lower band’s WCDMA signal has a sampling frequency of 42.24 MHz with peak-to-average power ratio (PAPR) of 8.6 dB @ 99.9% probability, while the upper band’s WCDMA signal sampling frequency is 42.24 MHz with PAPR of 8.7 dB @ 99.9% probability. These two signals are combined using a broadband Wilkinson power combiner, and preamplified using a commercial driver amplifier before being fed the Doherty-based concurrent dual-band PA. The lower band’s average input power into the PA was 22 dBm, while the upper band’s average input power into the PA was 24 dBm. The 2-dB offset in the upper band is for targeting equal power in both bands at the output of the PA. A coupler is used at the output of the PA to capture the signal for the feedback loop of the system in Fig. 5. The feedback loop is based on subsampling technique using the ADC development kit and logic signal analyzer. It consists of the time interleaved 800 MSPS ADC development board from SP Devices, Linköping, Sweden, [14]. The ADC was connected to an Agilent 16901A logic analyzer mainframe to allow triggering and deep memory depth capture. After capture of the signal, the data is filtered around the signal bands of interest, then digitally down-converted to baseband signals for linearization processing. A separate signal generator was also required to supply the ADC development board with the necessary sampling frequency clock, and all signal generators were phase locked with a reference clock. Fig. 10(a) shows the output spectrum of the PA under test, captured using a spectrum analyzer. Compared to Fig. 8(a) and Table III, there is an extra term (p) which is a seventh-order intermodulation product at 436 MHz. The power differences and the fact that terms (i) and (j) are not visible is due to the design of the PA output matching network. Fig. 10(b) shows the digitized signal captured from the PA under test by the ADC and logic analyzer using a sampling frequency of 619.8 MHz. In the ADC development board, there are two ADCs operating in a time interleaved manner to increase

Fig. 10. (a) RF spectra at the output of the PA. (b) Normalized spectra of the captured subsampled signal using an ADC operating at 619.8 MHz.

the overall sampling rate of the system, where one ADC is sampled on the rising edge of the clock, and the other is sampled on the falling edge. Ideally, both ADCs should be identical; however, gain mismatches and timing skew will cause the reconstructed signal to have attenuated replicas at specific frequencies [15]. For example, if is the input signal frequency, then mismatches can cause a replica to appear at . Compared to simulation results in Fig. 8(b), the distinct 5-MHz attenuated fundamental signals that exist at 49.7 MHz ( ) and 191.3 MHz ( ) are caused by these mismatch effects in the ADC time-interleaved architecture. Signals higher than 1.4 GHz (the rated analog bandwidth of the ADC system) are attenuated due to the loss in the ADC versus frequency in RF, and can be seen by the significant power difference of the upper band signal (b) compared with the lower band signal (a). This can be compensated by including an extra wideband T&H unit before the ADC into the final solution. The seventh-order intermodulation produce (p) is captured by the ADC, and resides at 183.8 MHz [as shown in Fig. 10(b)].

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Fig. 12. (a) AM–AM and (b) AM–PM for the 880-MHz band and the (c) AM–AM and (d) AM–PM for the 1978-MHz band of the Doherty PA; with and without linearization.

Fig. 11. Linearization results for: (a) 880 MHz and (b) 1978 MHz using concurrent dual-band predistortion on a Doherty PA with subsampling and conventional dual-branch feedback loops.

The fundamental signals are bandpass filtered in MATLAB, and digitally down-converted to baseband for dual-band predistortion processing. Processing the signals captured by the subsampling-based feedback loop and predistorting the input signals based on linearization block and (2), the spectrum of the output signals with and without linearization are shown in Fig. 11(a) and (b). Using the dual-band linearization architecture, one can significantly compensate for the in-band and out-of-band distortions and bandwidth regrowth to reduce the interference within the adjacent channels. The only drawback of the subsampling based system is the higher noise level due to the noise folding caused by the subsampling process, which is shown by the raised noise floor at the PA output. However, this is negligible compare to the improvement

achieved in distortion compensations. The linearization capability of the subsampling based feedback loop is also compared with the conventional dual-branch feedback system where the output signal of the dual-branch linearizer is also included in Fig. 11. It is clear from Fig. 11(a) that the subsampling-based architecture and conventional dual-branch architecture have the same out-of-band compensation performance. In the upper frequency band, as shown in Fig. 11(b), the dual-branch architecture has a little bit better out of band reduction, which is mainly due to the analog bandwidth limitation of the ADC of the subsampling architecture. Upon usage of proper T&H with appropriate analog bandwidth, the same performance should be expected for the upper frequency band. Fig. 12 shows the PA characteristics without linearization, and the cascade of the linearizer and PA. The results of linearization are shown with conventional dual-branch feedback loops; the AM–AM and AM–PM with subsampling linearization are omitted for clarity since the results are similar to the conventional dual-branch method. The better evaluation of in-band and out-band signal quality with and without linearization are by measuring the normalized mean squared error (NMSE) and adjacent channel power ratio (ACPR). The measurement results in Table IV show that having performed linearization, the in-band signal quality (NMSE) is improved by more than 10 dB and the out-of-band distortion compensation (ACPR) is around 10 dB for lower band and for upper band. Moreover, for both frequency bands, the subsampling based receiver has the same level of performance as the conventional dual-branch architecture.

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RESULTS

TABLE IV PREDISTORTION WITH SUBSAMPLING FEEDBACK LOOP FOR A DUAL-BAND DOHERTY PA

OF

RESULTS

TABLE V PREDISTORTION WITH SUBSAMPLING FEEDBACK LOOP FOR A WIDEBAND CLASS-AB PA

OF

(with 10-MHz total bandwidth) is transmitted at 942.5 MHz with a PAPR of 9.42 @ 99.9% probability, while a long-term evolution (LTE) signal (with 5-MHz bandwidth) is transmitted at 1492.9 MHz with a PAPR of 8.5 @ 99.9% probability. Both signals had a sampling frequency of 61.44 MHz and were transmitted with an average input power of 9 dBm. Using the algorithm outlined in Section IV, the selected subsampling frequency to avoid aliasing was chosen to be 726 MHz. Fig. 13 shows the output spectra of the PA at the two bands, with and without linearization, while Table V presents the measured NMSE and ACPR. Compared with the results from the dual-band Doherty PA (Fig. 11 and Table IV), the spectral regrowth at the adjacent bands are compensated more in the wideband class-AB PA. Due to the highly nonlinear nature of the Doherty PA, the linearization performance obtained does not quite reach the linearization performance of the wideband class-AB PA. This can be resolved by changing the predistortion algorithm to use a higher nonlinearity order. VII. CONCLUSION This paper has demonstrated the realization and simplification of the feedback loop of the dual-band linearization architecture by using the subsampling receiver. The subsampling technique and its implementation challenges and issues were discussed. A suitable subsampling frequency was determined in simulation using algorithms described in Section IV. The experimental setup was developed to prove the concept of the linearization architecture based on subsampling feedback loop. The measurement results showed that by using this method, more than 15-dB improvement in NMSE and more than 17-dB improvement in ACPR are achieved for a wideband class-AB PA, compared with the unlinearized method. ACKNOWLEDGMENT The authors would like to thank C. Simon and M. Younes, both with the University of Calgary, Calgary, AB, Canada, for their technical assistance and support. Fig. 13. Linearization results for: (a) 942.5 MHz and (b) 1485.9 MHz using concurrent dual-band predistortion on a wideband PA with subsampling and conventional dual-branch feedback loops.

As a supplement measurement, a Mini-Circuits ZHL-42W wideband class-AB PA was used to validate the dual-band DPD with a subsampling receiver. A two-carrier WCDMA signal

REFERENCES [1] R. Vaughan, N. Scott, and D. White, “The theory of bandpass sampling,” IEEE Trans. Signal Process., vol. 39, no. 9, pp. 1973–1984, Sep. 1991. [2] O. D. Grace and S. P. Piti, “Quadrature sampling of high-frequency waveforms,” J. Acoust. Soc. Amer., vol. 44, no. 5, pp. 1453–1454, 1968.

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[3] C. DeVries and R. Mason, “Subsampling architecture for low power receivers,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 55, no. 4, pp. 304–308, Apr. 2008. [4] C.-H. Tseng and S.-C. Chou, “Direct downconversion of multiband RF signals using bandpass sampling,” IEEE Trans. Wireless Commun., vol. 5, no. 1, pp. 72–76, Jan. 2006. [5] S. Bassam, M. Helaoui, and F. Ghannouchi, “De-interleaved direct down-conversion receiver for SDR applications,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2009, pp. 1661–1664. [6] M. Helaoui, S. Boumaiza, A. Ghazel, and F. Ghannouchi, “On the RF/DSP design for efficiency of OFDM transmitters,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 7, pp. 2355–2361, Jul. 2005. [7] A. Cidronali, I. Magrini, R. Fagotti, and G. Manes, “A new approach for concurrent dual-band IF digital predistortion: System design and analysis,” in Integr. Nonlinear Microw. Millimetre-Wave Circuits Workshop, Nov. 2008, pp. 127–130. [8] C.-H. Tseng, “A universal formula for the complete bandpass sampling requirements of nonlinear systems,” IEEE Trans. Signal Process., vol. 57, no. 10, pp. 3869–3878, Oct. 2009. [9] S. A. Bassam, M. Helaoui, and F. M. Ghannouchi, “2-D digital predistortion (2-D-DPD) architecture for concurrent dual-band transmitters,” IEEE Trans. Microw. Theory Tech., vol. 59, no. 10, pp. 2547–2553, Oct. 2011. [10] S. Bassam, W. Chen, M. Helaoui, F. Ghannouchi, and Z. Feng, “Linearization of concurrent dual-band power amplifier based on 2D-DPD technique,” IEEE Microw. Wireless Compon. Lett., vol. 21, no. 12, pp. 685–687, Dec. 2011. [11] M. Patel, I. Darwazeh, and J. O’Reilly, “Bandpass sampling for software radio receivers, and the effect of oversampling on aperture jitter,” in IEEE 55th Veh. Technol. Conf., Spring, 2002, vol. 4, pp. 1901–1905. [12] Y.-P. Lin, Y.-D. Liu, and S.-M. Phoong, “A new iterative algorithm for finding the minimum sampling frequency of multiband signals,” IEEE Trans. Signal Process., vol. 58, no. 10, pp. 5446–5450, Oct. 2010. [13] W. Chen, S. A. Bassam, X. Li, Y. Liu, K. Rawat, M. Helaoui, F. M. Ghannouchi, and Z. Feng, “Design and linearization of concurrent dual-band Doherty power amplifier with frequency-dependent power ranges,” IEEE Trans. Microw. Theory Tech., vol. 59, no. 10, pp. 2537–2546, Oct. 2011. [14] “ADS5474 ADX evaluation board for interleaving,” Texas Instrum. Inc., Dallas, TX, 2008. [15] N. Kurosawa, H. Kobayashi, K. Maruyama, H. Sugawara, and K. Kobayashi, “Explicit analysis of channel mismatch effects in time-interleaved ADC systems,” IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 48, no. 3, pp. 261–271, Mar. 2001.

Seyed Aidin Bassam (S’06–M’11) received the PhD degree in electrical engineering from the University of Calgary, Calgary, AB, Canada, in 2010. From 2010 to 2011, he was a Postdoctoral Researcher with the Intelligent RF Radio Laboratory (iRadio Lab), University of Calgary. He is currently a member of the Hardware Engineering Team, Powerwave Technologies, Santa Ana, CA. His research interests are high-power RF amplifier design, DPD and linearization techniques, and advanced digital signal-processing techniques applicable to software-defined radio, and multistandard and multiband wireless communication systems.

1999

Andrew Kwan (S’07–M’10) received the B.Sc. degree in computer engineering and M.Sc. degree in electrical engineering from the University of Calgary, Calgary, AB, Canada, in 2006 and 2009, respectively. He is currently a Research Associate with the Intelligent RF Radio Laboratory (iRadio Lab), University of Calgary. His research interests include signal processing for wireless communications systems, power-efficiency enhancement for RF transceivers, embedded systems, and software-defined radios.

Wenhua Chen (S’03–M’07–SM’11) received the B.S. degree in microwave engineering from the University of Electronic Science and Technology of China (UESTC), Chengdu, China, in 2001, and the Ph.D. degree in electronic engineering from Tsinghua University, Beijing, China, in 2006. From 2010 to 2011, he was a Postdoctoral Fellow with the Intelligent RF Radio Laboratory (iRadio Lab), University of Calgary. He is currently an Associate Professor with the Department of Electronic Engineering, Tsinghua University, Beijing, China. He has authored or coauthored over 70 journal and conference papers. He holds two U.S. patents. He has several Chinese patents pending. His main research interests include power-efficiency enhancement for wireless transmitters, PA predistortion, and reconfigurable and smart antennas.

Mohamed Helaoui (S’06–M’09) received the M.Sc. degree in communications and information technology from the École Supérieure des Communications de Tunis, Ariana, Tunisia, in 2003, and the Ph.D. degree in electrical engineering from the University of Calgary, Calgary, AB, Canada, in 2008. His current research interests include DSP, power-efficiency enhancement for wireless transmitters, switching-mode PAs, and advanced transmitter design for software-defined radio and millimeter-wave applications. His research activities have led to over 50 publications and six patents (pending). Dr. Helaoui is a member of the COMMTTAP Chapter, IEEE Southern Alberta Section.

Fadhel M. Ghannouchi (S’84–M’88–SM’93–F’07) is currently a Professor, AITF/Canada Research Chair, and Director of the Intelligent RF Radio Laboratory (i Radio Lab), Electrical and Computer Engineering Department, Schulich School of Engineering, University of Calgary, Calgary, AB, Alberta. He has held several invited positions at several academic and research institutions in Europe, North America, and Japan. He has provided consulting services to a number of microwave and wireless communications companies. He has authored or coauthored over 500 publications. He holds 12 U.S. patents with five pending. His research interests are in the areas of microwave instrumentation and measurements, nonlinear modeling of microwave devices and communications systems, design of power- and spectrum-efficient microwave amplification systems, and design of intelligent RF transceivers for wireless and satellite communications. Prof. Ghannouchi is a Fellow of the Institution of Engineering and Technology (IET). He is a Distinguish Microwave Lecturer of the IEEE Microwave Theory and Techniques Society (IEEE MTT-S).

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Design of a Direct Conversion Transmitter to Resist Combined Effects of Power Amplifier Distortion and Local Oscillator Pulling Chieh-Hsun Hsiao, Student Member, IEEE, Chi-Tsan Chen, Student Member, IEEE, Tzyy-Sheng Horng, Senior Member, IEEE, and Kang-Chun Peng, Member, IEEE

Abstract—This work elucidates how the combined effects of power-amplifier distortion and local-oscillator (LO) pulling adversely impact a wireless direct-conversion transmitter (DCT) that adopts a time-varying envelope modulation. An analytical model is developed to evaluate the deterioration of DCT output signal quality, including error vector magnitude, adjacent channel power ratio, and spectral regrowth. Additionally, an integrated approach for PA linearization and anti-LO pulling is designed based on an open-loop digital-predistortion method and the proposed analog feedback compensation mechanism. Experimental results demonstrate that a quadrature-modulation-based DCT that incorporates the proposed approaches can significantly improve the LO spectral purity, while achieving a high linearity and efficiency performance simultaneously. These attributes are highly desired for third-generation systems such as cdma2000 1x and W-CDMA. Index Terms—Digital predistortion (DPD), direct conversion transmitter (DCT), local-oscillator (LO) pulling, power amplifier (PA), PA linearization, transmitted signal quality.

I. INTRODUCTION

W

IRELESS communications have driven the demand for increased capacity and flexibility of RF transceiver design in recent decades [1], [2]. Achieving high-data-rate signal transmission for multimedia communications, especially in wide modulation bandwidth and high peak-to-average power ratio (PAPR), has led to stringent linearity constraints on signal conversion and amplification [3], [4]. Fig. 1 illustrates a widely adopted quadrature-modulation-based direct-conversion transmitter (DCT) [2], which is characterized by its low modulation distortion, regardless of the data rate. The DCT consists mainly of a local oscillator (LO) to provide a pure sinusoidal signal and a quadrature modulator to perform the baseband IQ modulation, as well as a power amplifier (PA) to boost the transmitted Manuscript received October 01, 2011; revised March 09, 2012; accepted March 13, 2012. Date of publication April 30, 2012; date of current version May 25, 2012. This work was supported in part by the National Science Council, Taiwan, under Grant 100-2221-E-110-081-MY3, Grant 100-2221-E-110-082MY3, and Grant 100-2622-E-110-001-CC1. C.-H. Hsiao, C.-T. Chen, and T.-S. Horng are with the Department of Electrical Engineering, National Sun Yat-Sen University, Kaohsiung 804, Taiwan (e-mail: [email protected]; [email protected]; [email protected]). K.-C. Peng is with the Department of Computer and Communication Engineering, National Kaohsiung First University of Science and Technology, Kaohsiung 811, Taiwan (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2012.2193139

Fig. 1. Illustration of transmitted signal quality degradation owing to combined effects of PA distortion and LO pulling in a DCT.

signal power level. However, when the DCT is operated in a time-varying envelope modulation system, the combined effects of PA distortion and LO pulling significantly deteriorate the system’s signal quality, including the LO spectral impurity and DCT output spectral regrowth. The above problems thus pose major bottlenecks in implementing RF transceiver system-on-chip (SoC). According to a survey of PA linearization strategies [3]–[7], the digital predistortion (DPD) method is a highly promising solution to improve the PA performance because of its relatively easy programming, low power consumption, and superior linearization. Based on the characteristics of the PA’s amplitude-to-amplitude modulation (AM–AM) and amplitude-tophase modulation (AM–PM) distortions, the predistorter implemented in baseband can synthesize the predistorted baseband in-phase/quadrature (IQ) modulation signals to compensate for PA’s amplitude compression and phase error. However, as the system modulation bandwidth increases, the DPD methods are generally difficult to improve the transmitted signal quality effectively, due to the limited sampling rate and the excessive quantization noise [5], [7]. The other critical distortion issue, the LO pulling effect, has received considerable attention under various injection conditions. In 2004, Razavi [8] considered a phase-locked oscillator (PLO) under an independent sinusoidal injection. In 2008, Li et al. [9] devised a numerical approach for accurately predicting the LO output spectra and phase noise under an independent modulation injection. While imitating a realistic phenomenon in which an injection signal into the LO correlates with the LO output signal, our previous works [10], [11] introduced a rigorous phase dynamic model for a PLO under directly modulated self-injection to evaluate the degradation of LO phase noise and transmitted signal quality. Moreover, closed-loop analytical models in both frequency domain [12] and time domain

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HSIAO et al.: DESIGN OF DCT TO RESIST COMBINED EFFECTS OF PA DISTORTION AND LO PULLING

[13] were developed to analyze the frequency modulation (FM) distortions caused by the LO pulling effect in a time-varying envelope modulation system. In addition to the above efforts, several works have attempted to mitigate the LO pulling effect. The most common means is to isolate the LO far away from the noisy source with the assistance of the clock retiming approach [14] and bulky off-chip elements [15], which significantly increases hardware complexity and degrades the system integration. A preliminary publication of this work [13] proposed a solution approach by combining a second-point VCO modulation loop and an inner self-injection loop, capable of reducing the LO pulling effect on the transmitted signal distortions. However, if the serious AM–AM and AM–PM distortions of a PA dominate the deterioration of the transmitted signal quality at a high DCT output power, the improved approach in [13] is no longer applicable. While elucidating the combined effects of PA distortion and LO pulling, this work significantly expands upon the results of [13] by including a detailed analysis of the PA’s AM–AM and AM–PM distortions. The rigorous analytical model adopted here can characterize the DCT signal quality deterioration when an LO is pulled by a self-dependent time-varying envelope modulation signal. This work also develops an improved approach, in which an open-loop DPD, a second-point VCO modulation loop, and an inner self-injection loop are incorporated to enhance the DCT’s LO spectral purity, PA linearity, and average efficiency simultaneously. II. ANALYSIS APPROACHES This section introduces the analytical model for a DCT with combined effects of PA distortion and LO pulling. A time-varying envelope modulation system is also considered when the deterioration of transmitted signal quality is characterized using the proposed model.

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Fig. 2. System model of a DCT with combined effects of LO pulling and PA distortion.

are the envelope and phase modulation (PM) component of the PA’s input signal, respectively, based on quadrature modulation of the baseband in-phase and quadrature signals. Moreover, and express the PA’s AM–AM distortion function and AM–PM distortion function, respectively. Notably, is the RF carrier frequency. Fig. 2 illustrates the proposed system model of a DCT with combined effects of PA distortion and LO pulling. The baseband IQ modulation signals are synthesized by a vector signal generator (VSG), and modulated on the RF carrier by a quadrature modulator. A PA is then used to boost the modulated signal power. To accommodate high-data-rate signal transmission, the power back-off is needed to ensure linear operation of the PA [3]. However, for a high PAPR modulation system, a high output back-off (OBO) value must be used accordingly to prevent signal distortion. Unfortunately, the PA’s efficiency peaks only when the PA operates near saturation and declines rapidly with a decreasing output power. Under the consideration of excellent linearization and low digital processing complexity, this work implements an open-loop DPD approach in baseband to reduce the PA nonlinear distortions and increase the DCT efficiency [5]–[7], [16].

A. PA Distortion

B. LO Pulling Effect

PA distortion originates mainly from two categories of nonlinearities, which are associated with the input signal amplitude [3]. Defined as the nonlinear relation between the amplitudes of the input and output signal, AM–AM distortion often compresses the gain and saturates the output signal amplitude. Conversely, AM–PM distortion describes the output phenomenon in which the PA output phase varies with the input signal amplitude. The above two distortions both induce intermodulation to degrade PA linearity and transmitted signal quality. Consider the time-domain waveforms of the PA’s input signal and output signal in a complex form, as expressed in the following equations:

As mentioned in Section I, the LO pulling effect has become a major distortion issue with the advances in integrated circuit (IC) process technologies. In the DCT architecture (Fig. 2), the LO is normally implemented by a phase-locked loop (PLL) to control the synthesized signal’s frequency and phase precisely, which is achieved by adjusting the voltage-controlled oscillator (VCO) output phase to align with the phase of reference signal through tuning voltage and frequency sensitivity . Based on Adler’s analysis [17] and our previous work [13], the instantaneous output frequency of an LO pulled by a timevarying envelope modulation signal can be expressed as

(1) (2) where

(3)

(4) where (5) refers to the inherent oscillation frequency of the VCO and is assumed here to be a summation of synthesized frequency and the instantaneous frequency variation caused by the PLL. and also represent the time-varying and constant

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amplitudes of the injection and oscillation signals, respectively. Meanwhile, is the quality factor of the oscillator’s tank circuit. Moreover, is regarded as the instantaneous phase difference between the injection signal and oscillation signal. By assuming that VCO is finally phase locked under a weak narrowband modulation injection, we can infer that and . Therefore, the resulting LO output frequency can be approximated as

phase formulation for the coexistence of phase locking and injection locking can also be found in [14] and [15]. However, this work differs from those works by considering the PA’s AM–PM distortion additionally. Based on the above derivations, Fig. 2 illustrates the system model in a complex expression of all signals of interest in the DCT with the combined effects of PA distortion and LO pulling. Consider the LO output signal in the following form:

(6)

(10)

where (7) is the time-varying locking range of a free-running oscillator injected by a time-varying envelope modulation signal. In (6), the frequency terms, and , express the frequency fluctuation caused by the phase- and injection-locking process, respectively. Furthermore, and represent the amplitude-to-frequency modulation (AM–FM) and phase-to-frequency modulation (PM–FM) distortions that result from the envelope and phase variations, respectively, of an IQ-modulated signal that pulls the LO. Both distortions degrade the quality of IQ modulation in terms of the FM component. Consider a situation in which the injection signal originates from the DCT output modulated signal via the pulling signal injection path with time delay . Based on assumptions of low LO phase noise and narrow modulation bandwidth, the injection-induced PM–FM distortion can be approximated as

(8) where , , and denote the instantaneous phase response of the LO output, IQ modulation, and PA’s AM–PM distortion, respectively. Incorporating (8) into (6) and integrating (6) yields the resulting LO output phase

(9) and refer to the initial oscillation phase and where the synthesized carrier phase, respectively. The phase fluctuation terms, and , in (9) are induced by the phase- and injection-locking process, respectively. A similar

where is assumed to be the comprehensive phase fluctuation, which originates from the frequency variations of phase- and injection-locking processes. With the discrete-time calculation approach in [9], can be calculated recursively and formulated as a pulse train weighted by . Therefore, the time-domain waveform of DCT output signal can be expressed as (11), shown at the bottom of this page, where denotes the impulse response of a reconstruction filter. This work also characterizes the transmitted signal quality degradation owing to the combined PA distortion and LO pulling effects by assuming that the baseband IQ signal is independent of the LO signal, i.e., and are modulated with an uncorrelated LO signal in quadrature modulation. Finally, incorporating the above equations into Agilent EEsof ADS Ptolemy software to perform system co-simulation allows us to evaluate the degraded transmitted signal quality by some major indices, such as error vector magnitude (EVM), adjacent channel power ratio (ACPR), and spectral regrowth. Fig. 3(a) compares different distortion mechanisms in term of transmitted signal quality degradation, while DCT delivers a 1.98-GHz cdma2000 1x quadrature phase-shift keying (QPSK) modulated signal with a channel bandwidth of 1.25 MHz. In this figure, the solid line in blue (in online version), dotted line in red (in online version), and broken line in gray represent the DCT output spectra with no distortion, only PA distortion, and the effects of PA distortion and LO pulling in combination, respectively. The corresponding ACPRs in the same order as above are 47.2, 37.4, and 32.5 dB. Fig. 3(b) shows the demodulated constellation with respect to Fig. 3(a). The corresponding EVMs in the same order as above are 1.3%, 9.4%, and 31.9%. Above results are simulated when the DCT is operated at an OBO of 6 dB and a pulling signal power ratio of 65 dB. The setting of the OBO is referred to as the PAPR of the synthesized QPSK-modulated signal, while the pulling signal power ratio is defined as the power ratio between the injection signal and the LO output signal (i.e., ). Above comparisons

(11)

HSIAO et al.: DESIGN OF DCT TO RESIST COMBINED EFFECTS OF PA DISTORTION AND LO PULLING

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Fig. 4. Block diagram of the proposed transmitter experimental setup for improving the combined effects of LO pulling and PA distortion.

Fig. 5. System model of the experimental DCT shown in Fig. 4.

Fig. 3. Comparison of output signal quality under different distortion mechanisms when DCT delivers a 1.98-GHz QPSK-modulated signal with a 1.25-MHz channel bandwidth. (a) Transmit spectrum. (b) Constellation.

demonstrate that more serious transmitted signal quality degradation originates from the combined effects of PA distortion and LO pulling. III. IMPROVEMENT APPROACHES Various PA linearization and anti-LO pulling approaches have been developed to alleviate the transmitted signal distortions. Some works [12], [18]–[21] have asserted that the adaptive DPD method may be an effective means of resolving these two major DCT design bottlenecks. With the powerful computation ability of digital circuitry in baseband, a predistorter can provide accurate predistorted values to compensate for the PA’s AM–AM and AM–PM distortions through an adaptive calculation algorithm. By exploiting this characteristic, Bashir et al. [12] developed a novel approach for mitigating the LO pulling effect. Therefore, that work introduced an adaptive digital-controlled-delay circuit to break the synchronization between the aggressors and the victims, capable of mitigating the LO pulling effect in the digital polar transmitter architecture. However, if the PA’s nonlinear distortion is considered with the LO pulling effect simultaneously, the serious AM–AM and AM–PM distortions substantially induce a heavy memory load and long convergence time in the adaptive predistortion algorithm. In other words, either the system modulation bandwidth must be reduced or the transmitter OBO value increased to ensure sufficient improvement on the transmitted signal quality

[21]. However, the transmitter efficiency declines rapidly as the output power decreases. To overcome the above limitations, this work adopts the open-loop DPD method to reduce the PA’s AM–AM and AM–PM distortions. Meanwhile, the proposed second-point VCO modulation and inner self-injection approaches mitigate the LO pulling effect with dependence on the PA’s AM–PM distortion. Fig. 4 schematically depicts the proposed DCT experimental setup, while Fig. 5 illustrates the proposed system model with respect to Fig. 4. The proposed DCT consists mainly of a PLLbased LO, an IQ modulator, a PA, and a baseband digital predistorter (BDP). Baseband I and Q component signals are provided by an Agilent E4438C vector signal generator (VSG) and then predistorted by the BDP. To imitate the real LO pulling phenomenon, a portion of DCT output is fed back to interfere with LO through a delay line with time delay , an attenuator, and a power combiner, serving as a pulling injection signal. Moreover, with the help of a circulator, the pulling injection signals and the LO output signals can be separated for individual measurement during the experiment, as done in our previous work [11]. In addition to the baseband IQ predistortion process for PA linearization, this work combines the proposed second-point VCO modulation and inner self-injection approaches to reduce the LO spectral impurity incurred by the LO pulling effect. A. Baseband DPD This work attempts to enhance the PA linearity by implementing an open-loop DPD method in baseband [16], [22], [23]. The predistortion concept is described in the following explanation. By continuing with the derivation in Section II-A,

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according to the continuous-wave (CW) measurements of the PA in the absence of DPD, one can characterize the PA’s nonlinear functions of gain compression and phase distortion with respect to the input sinusoidal phasor as follows:

(12) Assume that the linearization specifications for the PA’s AM–AM and AM–PM distortion are a constant voltage gain of and phase difference of zero degree. Therefore, the relative inverse functions, and , can be mathematically expressed as (13) Fig. 4 illustrates the approximate implementation of a DPD approach. The baseband in-phase and quadrature component waveforms and are synthesized by the VSG and fed to the BDP unit for predistortion based on the customized AM–AM and AM–PM lookup tables (LUTs), and subsequently converted into analog waveforms and through the digital-to-analog converters (DACs). The predistorted baseband signals are quadrature modulated onto the RF carrier, which forms the input RF signal of the PA. Theoretically, the PA’s nonlinear distortions can be effectively reduced with the above predistortion process. However, if the phase shift incurred by the injection-locking effect is considered, the phase error term in (12) should be rewritten as (14) where is an injection-locking phase shift that is dependent on the injection signal amplitude. Obviously, (14) reveals that the transmitted-signal PM distortion originates from the PA’s inherent AM–PM distortion and the LO pulling induced FM distortion. Above results also validate our postulation that the open-loop DPD method fails to alleviate the PM distortion of a transmitted signal, owing to the lack of an improvement mechanism for the LO pulling effect. B. Second-Point VCO Modulation An adaptive DPD technique based on feedback concepts has been developed recently to compensate for the inadequate PA linearization of the conventional predistortion approaches. Chung et al. [21] devised an open-loop DPD method embedded with an analog feedback estimation mechanism to expand the system modulation bandwidth and increase the convergence of the predistortion algorithm. The proposed approaches of this work also exploit this characteristic to reduce the PA nonlinear distortion and LO pulling effect simultaneously. Two equivalent analog feedback mechanisms are proposed in this work, while the distorted envelope and phase signals in the analog form are extracted and fed back to serve as self-adjusting signals to correct the phase error given in (14). Based

on the improved results, the proposed approaches significantly contribute efforts to enhance the DCT’s LO spectral purity, PA linearity, and average efficiency simultaneously. As discussed in Section II-B, the serious AM–FM and PM–FM distortions caused by the LO pulling effect significantly degrade the transmitted signal quality in a time-varying envelope modulation system. Moreover, implementing the DPD method should, theoretically, mitigate the PA’s AM–AM and AM–PM distortions. However, owing to the limitation of LUT’s resolution and PA’s physical defects (e.g., thermal noise or memory effect [24]), the transmitted-signal PM distortion is difficult to be cancelled out entirely by using the open-loop DPD method. To eliminate the transmitted signal distortions caused by the PA nonlinear effect in combination with the LO pulling effect, in contrast to the approach of [13], this work offers designing flexibility by introducing a multiplexer in the second-point VCO modulation loop, as shown in Fig. 4. The mixing objects of the RF mixer can be dynamically switched depending on which of the above two effects will dominate. Firstly, by assuming that the DPD method substantially mitigates the PA’s AM–AM distortion, the transmitted-signal PM distortion, caused by the LO pulling induced FM distortion and PA’s AM–PM distortion, dominates the transmitted signal quality degradation. Thus, according to Fig. 4, the feedback baseband envelope signal is extracted from the low-frequency mixing product of the DCT output signal and a calibrated LO signal with the assistance of an RF mixer and a low-pass filter. Mathematically, the extracted baseband envelope signal, , can be expressed as the following equation: (15) where (16) and (17) denote phase shift and In the above equations, and voltage gain of the phase shifter and the variable-gain amplifier (VGA), respectively, which are used in the second-point VCO modulation loop to maximize the conversion gain of the RF mixer. After low-pass filtering out the unwanted frequency items, can be approximated as (18) under small-angle approximation by incorporating (16) and (17) into (15) when , i.e., (18) denotes an equivalent voltage gain associated where with the injection signal amplitude . To remove the LO spectral impurity, the extracted baseband envelope is fed back to the VCO’s second modulation point with tuning sensitivity in order to correct the LO output frequency or phase. Consequently, by incorporating (8) into (6) with consid-

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2005

Fig. 6. Experimental results for the experimental DCT when delivering a 1.98-GHz cdma2000 1x QPSK-modulated signal with a channel bandwidth of 1.25 MHz and an OBO of 6 dB. (a) EVM. (b) ACPR.

Fig. 7. Experimental results for the proposed DCT when delivering a 1.98-GHz W-CDMA QPSK-modulated signal with a channel bandwidth of 3.84 MHz and an OBO of 8 dB. (a) EVM. (b) ACLR.

eration of adding the second-point VCO modulation frequency, the LO output frequency can be expressed as

that designers should only preserve the BDP’s AM–AM predistortion function, while replacing the original AM–PM compensation mechanism with the proposed second-point VCO modulation approach. Notably, in this suggested approach, the PA’s AM–PM distortion function is extracted first from the low-frequency mixing product of the PA’s input signal and output signal , as noted in Fig. 4, then a closed feedback loop is established to mainly compensate for the PA’s AM–PM distortion.

(19) where . Assume that the pulling signal injection path delay is sufficiently small when compared to the system modulation symbol time . This can be regarded as true because is about 20 ns for our experimental case, while is around 800 and 260 ns for the cdma2000 1x and W-CDMA systems, respectively. Therefore, the last term in (19) can be disregarded. Finally, the concerned LO spectral impurity caused by the LO pulling effect can be eliminated while satisfying the following cancellation condition: (20) Secondly, if the open-loop DPD method fails to reduce the PA nonlinear distortion, especially the serious PA’s AM–PM distortion due to the thermal noise or memory effect, we recommend

C. Inner Self-Injection Above analyses also reveal that, if the pulling signal injection path delay cannot be ignored, the residual spectral impurity term in (19) may significantly degrade the improvement on the transmitted signal quality ultimately. Additionally, some critical PA physical defect issues are too complex to be discussed with the LO pulling effect, which may decrease the improvement of the above cancellation approach. Therefore, an inner self-injection loop is additionally introduced in the proposed DCT to further improve the transmitted signal quality. Based on the oscillator self-injection-locking concept in [25] and [26], our previous work [11] developed an inner self-injection approach to mitigate the LO pulling effect in a constant envelope modulation system. Figs. 4 and 5 indicate that, in the inner self-injection loop, a part of the pulled LO output signal

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Fig. 8. Experimental results for the proposed DCT when delivering a 1.98-GHz cdma2000 1x QPSK-modulated signal with a channel bandwidth of 1.25 MHz and a pulling signal power ratio of 65 dB. (a) EVM. (b) ACPR.

Fig. 9. Experimental results for the proposed DCT when delivering a 1.98-GHz W-CDMA QPSK-modulated signal with a channel bandwidth of 3.84 MHz and a pulling signal power ratio of 65 dB. (a) EVM. (b) ACLR.

is fed back and injected into the VCO via a delay line with time delay , a phase shifter with phase shift , and a VGA for voltage amplification. When the inner self-injection approach is applied, the concerned LO spectral impurity can be formulated as

a system block diagram, as shown in Fig. 4. In the experiments, the LO is locked at 1.98 GHz, delivering an oscillation power of 0 dBm. The PA achieves a maximum CW output power of 29.3 dBm. Based on use of the Agilent E4438C VSG applied with Agilent EEsof ADS Ptolemy software, the third-generation (3G) system modulation signal is generated, including cdma2000 1x QPSK-modulated signals with a PAPR of about 6 dB [27] and one-frequency-aggregation (1-FA) W-CDMA QPSK-modulated signals with a PAPR of about 8 dB [28]. Sections IV-A and IV-B validate the improved effectiveness of the transmitted signal quality in terms of EVMs, ACPRs, or adjacent channel leakage ratios (ACLRs), spectral regrowth, and average efficiencies under various injection conditions and modulation systems

(21) where

denotes the inner self-injection locking range. also represents the relation between the instantaneous inner self-injection phase and the LO output phase. By assuming that is sufficiently small to make the approximation and is equal to 180 , (21) can be re-approximated as (22) Equation (22) clearly reveals that the LO spectral impurity can be effectively suppressed by increasing the product of the inner self-injection locking range and path delay . IV. RESULTS AND DISCUSSION This work demonstrates the effectiveness of the proposed improvement approaches by implementing a prototype DCT with

A. Ability to Resist PA Distortion and LO Pulling Fig. 6(a) and (b) summarizes the experimental results of EVMs and ACPRs, respectively, under various pulling signal power ratios when the DCT delivers a 1.98 GHz cdma2000 1x QPSK-modulated signal with a channel bandwidth of 1.25 MHz and an OBO of 6 dB. These figures include results achieved by using various improvement approaches, where the dotted lines in red (in online version), broken lines in blue (in online version), and solid lines in black denote the measurement results of without improvements, only the DPD method, and with the proposed approaches, respectively. Additionally,

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Fig. 10. Comparison of measured average efficiencies with respect to OBO for the proposed DCTs operating with a pulling signal power ratio of 65 dB. (a) Delivering a 1.98-GHz cdma2000 1x QPSK-modulated signal with a channel bandwidth of 1.25 MHz. (b) Delivering a 1.98-GHz W-CDMA QPSK-modulated signal with a channel bandwidth of 3.84 MHz.

Fig. 11. Experimental results of transmit spectra for the proposed DCTs operating with an OBO of 2.5 dB and a pulling signal power ratio of 65 dB. (a) 1.98-GHz cdma2000 1x QPSK-modulated signal with a channel bandwidth of 1.25 MHz. (b) 1.98-GHz W-CDMA QPSK-modulated signal with a channel bandwidth of 3.84 MHz.

the solid lines in gray depict the EVM and ACPR minimum specifications for the applied system. Both EVM and ACPR significantly decrease with an increasing pulling signal power ratio value. Measurement results indicate that the proposed approach improves the EVM by 15.6% and ACPR by 7.7 dB when the pulling signal power ratio equals 55 dB. Moreover, to emphasize the advantages of wideband and adaptability, Fig. 7(a) and (b) compares the EVMs and ACLRs, respectively, under various pulling signal power ratios when the DCT delivers a 1.98-GHz W-CDMA QPSK-modulated signal with a channel bandwidth of 3.84 MHz and an OBO of 8 dB. According to this figure, a significant improvement on transmitted signal quality is achieved on EVM and ACPR of 85% and 14.65 dB, respectively, when the pulling signal power ratio equals 55 dB. According to Figs. 6 and 7, the experimental results verify that the proposed approaches can effectively diminish the combined effects of PA distortion and LO pulling in a time-varying envelope modulation system.

ACLRs [see Figs. 8(b) and 9(b)] under a constant pulling signal power ratio of 65 dB, but with different OBOs for a DCT that delivers a 1.98-GHz cdma2000 1x QPSK-modulated signal and a W-CDMA QPSK-modulation signal, respectively. In comparison with the conventional DPD methods, the proposed approaches markedly improve in modulation quality. Under the constraint that satisfies the ACPR/ACLR specifications, the proposed approaches can increase the OBO by about 4 and 6.5 dB for cdma2000 1x system and W-CDMA system, respectively. Fig. 10 shows the measured average efficiencies with respect to OBO under a constraint that ACPRs/ACLRs must meet the system specifications. In Fig. 10(a), the black lines and gray lines denote the average efficiencies of with and without improvement, respectively, in the cdma2000 1x system. These results indicate that the average DC-to-RF efficiency and average power-added efficiency (PAE) improve significantly, ranging from 25.9% to 39.5% and 20.9% to 30.8%, respectively. Moreover, in Fig. 10(b), a similar improvement on average efficiencies can also be found when the DCT delivers a W-CDMA modulation signal, which ranges from 21.6% to 47.1% at average DC-to-RF efficiency and ranges from 17.9% to 38.2% at average PAE. Experimental results show that the proposed approaches have more obvious improvements on the W-CDMA system than on

B. Ability to Enhance DCT Linearity and Average Efficiency This work also demonstrates the effectiveness of the proposed approaches in enhancing the DCT performance. Figs. 8 and 9 compare the EVMs [see Figs. 8(a) and 9(a)] and ACPRs/

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the cdma2000 1x system. Above comparisons verify the inference in Section III that the open-loop DPD method fails to accurately compensate for the PA nonlinear distortion due to the lack of adaptive self-correcting mechanism. This failure explains the degraded improvement with an increasing system modulation bandwidth. However, the proposed combined approaches can overcome this limitation. Finally, Fig. 11(a) and (b), respectively, compares the transmit spectra measurement results for the cdma2000 1x and W-CDMA DCTs when operating at an OBO of 2.5 dB and a pulling signal power ratio of 65 dB. In these figures, the solid lines in black and dotted lines in gray denote the DCT output spectrum of without and with improvement, respectively. Above results reveal that the proposed DCT possesses a significant improvement in spectral regrowth, while achieving a high efficiency simultaneously. In contrast to existing adaptive DPD methods, the combined approach of the open-loop DPD and analog RF feedback technique in this study can reduce DSP computation time and requirements, thus benefiting higher data-rate modulation schemes. However, the RF complexity is undoubtedly increased. Therefore, we recommend that designers use our proposed approach for high data-rate wireless communication systems that suffer from the combined effects of PA distortion and LO pulling. V. CONCLUSION This paper has presented the combined effects of PA distortion and LO pulling on a DCT in a time-varying envelope modulation system. The proposed theoretical model and analysis approaches can account for and forecast the degraded transmitted signal quality, including the factors such as EVMs, ACPRs, and spectral regrowth. To mitigate the adverse effects on the above factors, an innovative approach, capable of incorporating a baseband DPD method, a second-point VCO modulation approach, and an inner self-injection technique, is developed to improve the deteriorated transmit signal quality. Additionally, the proposed approaches also provide an excellent PA linearization capability and are successfully identified in a case-study application to the cdma2000 1x and W-CDMA systems. Consequently, the proposed DCT is characterized by its superior linearity, high average efficiency, and effective anti-LO pulling properties for application to a high PAPR wireless system. Efforts are underway to extend the proposed approach and related results to more complex modulation systems, such as worldwide interoperability for microwave access (WiMAX) and long term evolution (LTE). REFERENCES [1] B. Razavi, “Challenges in portable RF transceiver design,” IEEE Circuits Device Mag., vol. 12, no. 5, pp. 12–25, Sep. 1996. [2] B. Razavi, “RF transmitter architectures and circuits,” in Proc. IEEE Custon Integr. Circuits Conf., Aug. 1999, pp. 197–204. [3] S. C. Cripps, Advanced Techniques in RF Power Amplifier Design. Norwood, MA: Artech House, 2002. [4] P. B. Kenington, High-Linearity RF Amplifier Design. Norwood, MA: Artech House, 2000. [5] S. P. Stapleton, “Digital predistortion of power amplifiers,” Agilent Technol. Inc., Santa Clara, CA, Sep. 1, 2005. [Online]. Available: http://www.agilent.com

[6] J. K. Cavers, “Amplifier linearization using a digital predistorter with fast adaptation and low memory requirements,” IEEE Trans. Veh. Technol., vol. 39, no. 4, pp. 374–382, Nov. 1990. [7] L. Sundstrom, M. Haulkner, and M. Johanson, “Quantization analysis and design of a digital predistortion linearizer for RF power amplifier,” IEEE Trans. Veh. Technol., vol. 45, no. 4, pp. 707–719, Nov. 1996. [8] B. Razavi, “A study of injection locking and pulling in oscillators,” IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1415–1424, Sep. 2004. [9] C.-J. Li, C.-H. Hsiao, F.-K. Wang, T.-S. Horng, and K.-C. Peng, “A rigorous analysis of a phased-locked oscillator under injection,” IEEE Trans. Microw. Theory Tech., vol. 58, no. 5, pp. 1391–1400, May 2010. [10] C.-H. Hsiao, C.-J. Li, F.-K. Wang, T.-S. Horng, and K.-C. Peng, “Study of direct-conversion transmitter pulling effects in constant envelope modulation systems,” in IEEE MTT-S Int. Microw. Symp. Dig., May 2010, pp. 1174–1177. [11] C.-H. Hsiao, C.-J. Li, F.-K. Wang, T.-S. Horng, and K.-C. Peng, “Analysis and improvement of direct-conversion transmitter pulling effects in constant envelope modulation systems,” IEEE Trans. Microw. Theory Tech., vol. 58, no. 12, pp. 4137–4146, Dec. 2010. [12] I. Bashir, R.-B. Staszewski, O. Eliezer, B. Banerjee, and P.-T. Balsara, “A novel approach for mitigation of RF oscillator pulling in a polar transmitter,” IEEE J. Solid-State Circuits, vol. 46, no. 2, pp. 403–415, Feb. 2011. [13] C.-H. Hsiao, C.-T. Chen, T.-S. Horng, and K.-C. Peng, “Direct-conversion transmitter with resistance to local oscillator pulling in nonconstant envelope modulation systems,” in IEEE MTT-S Int. Microw. Symp. Dig., May 2011, pp. 1174–1177. [14] S. Mendel, C. Vogel, and N. Da Dalt, “A phase-domain all-digital phaselocked loop architecture without reference clock retiming,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 56, no. 11, pp. 860–864, Nov. 2009. [15] J. Dominguez, A. Suarez, and S. Sancho, “Semi-analytical formulation for the analysis and reduction of injection-pulling in front-end oscillators,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2009, pp. 1589–1592. [16] C.-T. Chen, C.-J. Li, T.-S. Horng, J.-K. Jau, and J.-Y. Li, “Design and linearization of class-E power amplifier for non-constant envelope modulation,” IEEE Trans. Microw. Theory Tech., vol. 57, no. 4, pp. 957–964, Apr. 2009. [17] R. Adler, “A study of locking phenomena in oscillators,” Proc. IRE, vol. 34, no. 6, pp. 351–357, Jun. 1946. [18] S. P. Stapleton, G. S. Kandola, and J. K. Cavers, “Simulation and analysis of an adaptive predistorter utilizing a complex spectral convolution,” IEEE Trans. Veh. Technol., vol. 41, no. 4, pp. 387–394, Nov. 1992. [19] M. Faulkner and M. Johansson, “Adaptive linearization using predistortion—Experimental results,” IEEE Trans. Veh. Technol., vol. 43, no. 2, pp. 323–332, May 1994. [20] J. Kim, C. Park, J. Moon, and B. Kim, “Analysis of adaptive digital feedback linearization techniques,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 2, pp. 345–354, Feb. 2010. [21] S. Chung, J.-W. Holloway, and J.-L. Dawson, “Open-loop digital predistortion using Cartesian feedback for adaptive RF power amplifier linearization,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2007, pp. 1449–1452. [22] K. J. Muhonen, M. Kavehrad, and R. Krishnamoorthy, “Look-up table techniques for adaptive digital predistortion: a development and comparison,” IEEE Trans. Veh. Technol., vol. 49, no. 5, pp. 1995–2002, Sep. 2000. [23] C. H. Lin et al., “Dynamically optimum lookup-table spacing for power amplifier predistortion linearization,” IEEE Trans. Microw. Theory Tech., vol. 54, no. 5, pp. 2118–2127, May 2006. [24] H. Ku and J.-S. Kenney, “Behavioral modeling of nonlinear RF power amplifiers considering memory effects,” IEEE Trans. Microw. Theory Tech., vol. 51, no. 12, pp. 2495–2504, Dec. 2003. [25] H.-C. Chang, “Stability analysis of self-injection-locked oscillators,” IEEE Trans. Microw. Theory Tech., vol. 51, no. 9, pp. 1989–1993, Sep. 2003. [26] A. Suarez and F. Ramirez, “Analysis of stabilization circuits for phase-noise reduction in microwave oscillators,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 9, pp. 2743–2751, Sep. 2005. [27] B. Yuen, “Crest factor invariant RF power detector,” Texas Instrum. Incorporated, Dallas, TX, Appl. Note 1434, 2006. [28] J. Moon, J. Son, J. Kim, I. Kim, S. Jee, Y. Y. Woo, and B. Kim, “Doherty amplifier with envelope tracking for high efficiency,” in IEEE MTT-S Int. Microw. Symp. Dig., May 2010, pp. 1086–1089.

HSIAO et al.: DESIGN OF DCT TO RESIST COMBINED EFFECTS OF PA DISTORTION AND LO PULLING

Chieh-Hsun Hsiao (S’10) was born June 5, 1984, in Kaohsiung, Taiwan. He received the B.S.E.E. and M.S.E.E. degrees from the National Sun Yat-Sen University, Kaohsiung, Taiwan, in 2006 and 2008, respectively, and is currently working toward the Ph.D. degree in electrical engineering at National Sun Yat-Sen University. His doctoral research concerns phase- and injection-locked oscillators.

Chi-Tsan Chen (S’07) was born in Taichung, Taiwan, in 1982. He received the B.S.E.E. and M.S.E.E degrees from National Sun Yat-Sen University, Kaohsiung, Taiwan, in 2005 and 2007, respectively, and is currently working toward the Ph.D. degree in electrical engineering at National Sun Yat-Sen University. His current research interests include RF PAs, highly efficient and linear transmitter design, and low-power transceivers.

Tzyy-Sheng Horng (S’88–M’92–SM’05) was born in Taichung, Taiwan, on December 7, 1963. He received the B.S.E.E. degree from National Taiwan University, Taipei, Taiwan, in 1985, and the M.S.E.E. and Ph.D. degrees from the University of California at Los Angeles (UCLA), in 1990 and 1992, respectively. Since August 1992, he has been with the Department of Electrical Engineering, National Sun Yat-Sen University, Kaohsiung, Taiwan, where he was the Director of the Telecommunication Research and De-

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velopment Center (2003–2008) and Director of the Institute of Communications Engineering (2004–2007), and where he is currently a Professor and the Advanced Semiconductor Engineering Inc. (ASE Inc.) Chair Professor. He has authored or coauthored over 100 technical publications published in IEEE journals and conferences proceedings. He holds over ten patents. His research interests include RF and microwave ICs and components, RF signal integrity for wireless system-in-package, digitally assisted RF technologies, and green radios for cognitive sensors and Doppler radars. Dr. Horng has served on several Technical Program Committees of international conferences including the International Association of Science and Technology for Development (IASTED) International Conference on Wireless and Optical Communications, the IEEE Region 10 International Technical Conference, the IEEE International Workshop on Electrical Design of Advanced Packaging and Systems, the Asia–Pacific Microwave Conference, the IEEE Radio and Wireless Symposium, and the Electronic Components and Technology Conference. He was the recipient of the 1996 Young Scientist Award presented by the International Union of Radio Science, the 1998 Industry–Education Cooperation Award presented by the Ministry of Education, Taiwan, and the 2010 Distinguished Electrical Engineer Award presented by the Chinese Institute of Electrical Engineering, Taiwan.

Kang-Chun Peng (S’00–M’05) was born February 18, 1976, in Taipei, Taiwan. He received the B.S.E.E., M.S.E.E., and Ph.D. degrees from National Sun Yat-Sen University, Kaohsiung, Taiwan, in 1998, 2000, and 2005, respectively. He is currently an Assistant Professor with the Department of Computer and Communication Engineering, National Kaohsiung First University of Science and Technology, Kaohsiung, Taiwan. His current research interests are in the area of delta–sigma modulation techniques, low-noise PLLs, low-power VCOs, and modulated frequency synthesizers.

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IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 60, NO. 6, JUNE 2012

Codesign of PA, Supply, and Signal Processing for Linear Supply-Modulated RF Transmitters John Hoversten, Member, IEEE, Scott Schafer, Student Member, IEEE, Michael Roberg, Student Member, IEEE, Mark Norris, Student Member, IEEE, Dragan Maksimović, Member, IEEE, and Zoya Popović, Fellow, IEEE

Abstract—This paper presents a method for achieving high-efficiency linear transmitters by codesign of the RF power amplifier (PA), dynamic supply, and signal processing. For varying amplitude signals, the average efficiency of the PA is improved by adding a supply modulator with requirements derived from nonstandard PA modeling. The efficient PA and supply modulator both introduce signal distortion. A targeted linearization procedure is demonstrated with reduced complexity compared to standard digital predistortion. Experimental results on a 2.14-GHz 81% efficient 40-W peak power GaN PA illustrate the codesign method by achieving 52.5% composite power-added efficiency with high linearity for a W-CDMA signal with a 23-MHz supply modulator bandwidth. Index Terms—Envelope elimination and restoration (EER), envelope tracking (ET), microwave power amplifiers (PAs), polar transmitter.

I. INTRODUCTION

M

ODERN modulation schemes include amplitude- and phase-modulated signals with high peak-to-average ratios (PARs) and bandwidths. In addition, in two-way communications, the up- and down-link signals have different power levels and PARs. The main challenge in transmitter design is achieving simultaneous linearity and efficiency [1], and existing solutions include outphasing [2], [3], different Doherty PA architectures (e.g., [4]–[6]) and various types of envelope tracking (ET) [7]–[9]. ET and polar split transmitters originate from envelope elimination and restoration (EER) pioneered in the 1950s [10]. In this approach, signal amplification is done by modulating both the RF power amplifier (RFPA) and its dc supply with some prescribed dependence, which we refer

Manuscript received October 01, 2011; revised January 11, 2012; accepted January 12, 2012. Date of publication March 15, 2012; date of current version May 25, 2012. This work was supported by the National Semiconductor Corporation (now Texas Instruments Incorporated) through the Colorado Power Electronics Center (CoPEC), Berrie Hill Research Corporation, by the U.S. Air Force under Contract FA8650-10-D-1746-0006, and by the Office of Naval Research under the Defense Advanced Research Projects Agency (DARPA) Microscale Power Conversion (MPC) Program under Grant N00014-11-1-0931. J. Hoversten is with Texas Instruments Incorporated, Longmont, CO 805037752 USA. S. Schafer, M. Roberg, D. Maksimović, and Z. Popović are with the Department of Electrical, Computer and Energy Engineering, University of Colorado at Boulder, Boulder, CO 80309-0425 USA (e-mail: [email protected]). M. Norris was with the Department of Electrical, Computer and Energy Engineering, University of Colorado at Boulder, Boulder, CO 80309-0425 USA. He is now with Texas Instruments Incorporated, Longmont, CO 80503-7752 USA. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2012.2187920

Fig. 1. Various input trajectories shown in the literature, defined as the gener. A: Traditional linear PA with constant ally nonlinear dependence . B: EER with constant and full supply modulation. C: ET. D: PDM. E: Partial supply modulation. F: Offset supply for minimum drive amplitude. G: Following best path for parameter (i.e., PAE, gain, linearity). The envelope voltage PDF of a WCDMA signal preprocessed for a 7-dB PAR is also shown.

to as the “input trajectory.” Fig. 1 shows an illustrative plot of the supply voltage variation with input signal amplitude, , where the analog input signal to be amplified is given by . In a standard linear amplifier, the supply is constant, as represented by line A in Fig. 1. EER, or full supply modulation shown with line B and first proposed by Kahn, implies a constant input envelope with the entire signal amplitude being modulated by the supply. Other curves (C–F) show examples reported in the literature, corresponding to transmitters that have been termed various names, such as ET, wideband ET (WBET), polar modulation, hybrid quadrature polar modulation (HQPM), EER, hybrid EER (HEER), partial drive modulation (PDM), and discrete dynamic voltage biasing (DDVB). Table I gives examples of various experimental input trajectories reported in the literature along with the stated PA classes of operation. Other trajectory examples obtained illustrated by simulation are given in [11]. If the probability density function of the envelope voltage is superimposed in Fig. 1 for a given signal, a designer has a starting point for the range of supply voltages that the supply modulator needs to provide. This, however, does not give any information about the signal bandwidth, which will determine how fast the supply needs to be. The average transmitter efficiency for a signal with a known probability density function can be calculated from [24]

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HOVERSTEN et al.: CODESIGN OF PA, SUPPLY, AND SIGNAL PROCESSING FOR LINEAR SUPPLY-MODULATED RF TRANSMITTERS

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TABLE I EXAMPLES OF TRANSMITTERS WITH SUPPLY MODULATION

Fig. 2. Block diagram of a general supply-modulated transmitter contains components at several frequency ranges: the RF portion with an upconverter, driver PA and high-efficiency PA optimized for efficiency over a range of envelopes; the signal envelope bandwidth supply modulator circuit, which provides the bias to the RFPA in some relationship to the envelope of the signal; and the digital portion, which performs the signal split and other processing necessary for linas the “signal earization and control. We refer to the ratio of signals and split,” and this parameter can be optimized for efficiency, linearity, etc. of the entire transmitter.

and is obviously maximized when both the RFPA efficiency and the supply modulator efficiency are maximized over all input amplitudes. Referring to Fig. 1, for the linear amplifier case (A), the average efficiency is low, but the amplifier can be kept fairly linear and this has been standard practice. An EER transmitter, (B), can be very efficient provided the supply modulator is efficient, but the linearity will be poor. Full ET, (C), has a dynamic RF input amplitude proportional to the signal envelope, giving the highest PA efficiency, but making efficient supply modulator design difficult. Partial supply or PDM can be achieved along different nonlinear and possibly nonsmooth trajectories. One example of PDM, (D), has been reported in [24] where a minimal value is specified for the drive voltage, resulting in efficiency improvements for low signal amplitudes at the expense of linearity. Examples of partial supply modulation that have been reported in the literature are given by E, F, and G. The curve for E* in the table is similar in shape to E, but shifted near zero supply voltage for low . The curved trajectory G trades PA efficiency, linearity, and supply modulator efficiency: at low envelopes, the supply is held constant, and the curve exhibits a second deflection point for higher input signal values. This paper develops a codesign method for determining RFPA, supply-modulator and signal-processing requirements under given efficiency and linearity constraints, building on initial simulation results first presented in [11]. The generalized transmitter block diagram is shown in Fig. 2, with the following main components: 1) high-efficiency RFPA designed optimized for efficiency over a range of envelopes; 2) efficient supply modulator; 3) feedback circuit for calibration and linearization; 4) digital control circuit, which includes the signal split and predistortion. The signals and are baseband (digital) signals. The ratio of signals and is referred to as the “signal split,” and this ratio is critical to achieving high overall average power-added efficiency (PAE) of the system. The signal split applies a transformation to the desired signal envelope to produce the supply

modulator digital input, and determines the weighting of the complex signal paths. A properly chosen vector of input baseband signals enables optimal efficiency and linearity for a specific type of signal (PAR, PDF, bandwidth). This general supply modulated PA can be configured to be an ET, EER, polar, partial drive, or partial supply transmitter. The contributions of this paper are as follows. • Section II describes the modeling approach and presents a characterization method for a high-efficiency PA designed for the architecture in Fig. 2; • Section III presents the method used to determine supply modulator characteristics and the signal split ( ); • Section IV presents experimental results that demonstrate the approach, and describes sources of signal distortion. The final linearization approach is demonstrated on a measured spectrum with reduced regrowth after each step of the targeted linearization method. The heat dissipation is dramatically reduced and distributed more uniformly between system components. II. PA MODELING AND CHARACTERIZATION In this section, we present the basic measurement and simulation method required to characterize a PA for the architecture in Fig. 2. The method is first illustrated using simulated data for a typical PA that would be suitable for such a transmitter, which needs to be designed to have high efficiency over a range of supply voltages. This means that no specific class of operation will be appropriate, although a class is usually specified when discussing ET transmitters in [10]–[19]. For example, in a class-F PA, the harmonic terminations in the output network take into account the output capacitance of the device. However, changes with operating supply voltage so the terminations will not satisfy class-F conditions for all envelope values. Another example is a class-E power amplifier (PA) in which the output device capacitance is a part of a specific output complex impedance that enables soft switching [1]; changing the supply voltage will change and modify the class-E impedance at the fundamental.

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Fig. 3. Static model of PA characterized for multiple supply voltages. This can be used as a static LUT for supply-modulated system simulation. From: (a) constant output RF voltage and (b) constant current contours, as the RF input voltage and supply voltage are varied, other parameters such as (c) gain and (d) PAE can be calculated. For these simulations, the RF load is kept fixed at 50 .

The simulations in this section are performed with a nonlinear model for a Eudyna high-power GaN HEMT (EGN030MK) for a gate bias of 1 V and a drain bias from 0 to 35 V. The PA design takes into account small-signal gain, efficiency, and output power over a range of supply voltages corresponding to an input envelope range of 15 V for a WCDMA downlink signal, resulting in class-AB operation. Once the PA is designed with supply modulation in mind, in addition to standard characterization ( , PAE versus ), the PA also needs to be characterized as the bias is varied. First both and are varied and output voltage and drain current are measured as shown in Fig. 3(a) and (b). From this data, relevant static parameterized plots can be derived. The gain and PAE are plotted in Fig. 3(c) and (d), and other parameters such as insertion phase can be obtained. This data serves as a static 2-D lookup table (LUT) PA model for subsequent system simulations. From these figures, the following observations can be made. Under pure drive modulation (horizontal blue line A in online version), gain decreases as the PA enters high-power high-efficiency compressed operation, causing distortion of the output signal. This is the traditional PA driving method with no supply modulation. Under pure drain modulation (vertical

red line B in online version), efficiency remains high over a larger output power range. PA gain variation is much more significant in this case than under traditional drive modulation, requiring significant pre-correction of . Both A and B input trajectories intersect a wide range of drain currents and output powers. Other input trajectories from Fig. 1 trade efficiency and linearity. An input trajectory that focuses on high efficiency is shown in Fig. 3(d), which would require some type of linearization. One can also choose the trajectory to increase PA linearity and reduce the amount of pre-distortion required, as shown by the trajectory in Fig. 3(c), which follows a constant 12-dB gain curve. It is difficult to determine what the “best” trajectory is for the transmitter as a whole without additional system specifications, such as supply modulator efficiency, overall size, or complexity of the digital processing. It is important to note that the data is static and should not include dynamic effects. For example, it would be appropriate to measure the data under pulsed RF conditions where the pulse is shorter than the thermal time constant of the device. Unfortunately, PAs have dynamic effects at time constants around the signal bandwidth due to, e.g., matching and bias lines, which can be accounted for by modeling the network as frequency dependent.

HOVERSTEN et al.: CODESIGN OF PA, SUPPLY, AND SIGNAL PROCESSING FOR LINEAR SUPPLY-MODULATED RF TRANSMITTERS

Fig. 4. Simulated data from Fig. 3(d), replotted in terms of output envelope , which takes the PA gain into account. This plot is used to define voltage three output trajectories discussed in the text.

III. SIGNAL SPLIT DESIGN Although the input trajectory is a relevant starting point for supply-modulated PA design, an “output trajectory” is a more practical representation since it includes the PA gain and is the quantity of interest. Choosing a trajectory determines not only the gain and efficiency for a varying signal, but also requirements for the supply modulator: total voltage range, voltage slew rate, variation, and bandwidth of the PA acting as a load to the supply. A. PA-Optimized Trajectory Fig. 4 shows PAE contours derived from Fig. 3(c) and (d). Thus, if the goal of the transmitter design is to maximize efficiency, the supply should follow the output envelope, as shown with curve T3, since it intersects the lower efficiency contours over the smallest range of values. However, the knee voltage of the device limits PA performance at low supply voltages. As decreases, there is little room for the input signal before entering the knee voltage region, which leads to reduced gain and/or linearity. B. Trajectory Implications on Supply Requirements Caution should be used when choosing what appears to be the “best” trajectory for efficiency. Curve T3 optimizes RFPA efficiency, but clearly requires increased supply dynamic capabilities, which usually results in lower supply modulator efficiency, discussed for example, in [25]. An important parameter to consider for supply modulator design is the percentage change in output voltage that results from a 1% error in the supply voltage, which we define as “PA supply sensitivity” given by

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This parameter, defined first in [11], is similar to the power supply rejection ratio (PSRR) often considered in analog electronics [26]. Contours of constant are shown in Fig. 5, and it is

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Fig. 5. Simulated contours of constant supply sensitivity parameter with the three trajectories from Fig. 4 provide information on the requirements for supply modulator design.

clear that choosing the highest efficiency output trajectory (T3) implies the most challenging supply modulator requirements. In this case, the supply modulator needs to maintain the predetermined supply voltage within 1% to prevent a 90% error in output envelope for V, which is a very difficult specification for a practical supply. Trajectory T2 trades supply modulator requirements for some PA efficiency resulting in an easier system design. The supply modulator is responsible for amplifying the envelope voltage waveform with the following requirements: 1) certain minimum and maximum output voltage level; 2) flat gain over a specified bandwidth; 3) maximum slew rate for acceptable distortion; 4) drive a time-varying load (the RFPA). The first two requirements are contradictory because high-power devices that enable large voltage swings have large capacitance, limiting maximum speed. For a given dynamic range, architecture may allow a dc offset to be applied to the output voltage range to allow higher peak voltages at the expense of higher minimum voltage. The maximum and minimum drain voltages impact RFPA efficiency. Bandwidth and frequency response are small-signal parameters, while slew rate describes large-signal performance and is the limiting factor for the supply modulator. For example, a fast voltage ramp across a low-impedance load may deplete the charge stored in supply modulator decoupling capacitors, causing the supply voltage rail to dip, with resulting output signal distortion due to inadequate slew-rate capability. Table II shows simulated required bandwidths and slew rates, which would results in acceptable adjacent channel power ratio (ACPR) for a WCDMA down-link signal with 7-dB PAR, for the three trajectories discussed throughout this section. The analysis used to produce these results involves simulation of an idealized supply-modulated transmitter imposing bandwidth and slew rate limitations on the supply modulator, as discussed in [22]. T3 optimizes PA efficiency, but imposes yet another difficult requirement on the supply modulator: a bandwidth of 23 MHz with a slew rate of 230 V s and a voltage swing of 27 V.

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TABLE II SUPPLY MODULATOR REQUIREMENTS TO ACHIEVE NEGLIGIBLE SYSTEM DISTORTION

Fig. 7. Measured load–pull data for a TriQuint Semiconductor TGF-2003–10 GaN HEMT. The “class” of the amplifier is ambiguous because the operating point will move with the supply bias. The goal is to optimize the operating point over the supply modulator range of voltages for gain, power, and/or efficiency. V), constant drain effiContours of constant measured power (at ciency at 20, 28, and 36 V, and constant small-signal gain contour for a 12-V supply shown on a 10- Smith chart.

TABLE III PA HARMONIC TERMINATIONS AT THE VIRTUAL DRAIN OF THE TRANSISTOR Fig. 6. Simulated resistance seen by the supply modulator and drain current to meet the three trathat supply modulator must supply as a function of jectories shown in Figs. 4 and 5. For signals with low envelope voltages, the resistance changes very rapidly, increasing the dynamic capability requirement of the supply modulator.

The load driven by the supply modulator ( ) at the PA drain supply terminals is referred to as the drain resistance. Note that this is not directly related to the PA load line and is made constant over the RF cycle by the RF choke. varies with PA output power and efficiency as

and this variation is dependent upon design of the signal split, as shown in Fig. 6 for the three simulated trajectories. Therefore, the output impedance of the supply modulator should be kept low over a wide frequency range to limit error due to voltage division between the supply modulator output impedance and load PA impedance. Fig. 6 also shows the simulated drain–current variation with output envelope for the three trajectories, where T3 requires a maximum-to-minimum current ratio of 16, while the T1 ratio is only 4, significantly lowering the burden on the supply modulator. IV. EXPERIMENTAL RESULTS AND TARGETED LINEARIZATION In this section, we present measured results produced using the method illustrated by simulations of Sections II and III. Note that the PA is designed for supply modulation and based on a TriQuint Semiconductor GaN transistor with no available nonlinear model. While the simulations in Section II are performed with an existing nonlinear model for a Class AB PA, even this available model would not be valid for an extremely saturated class-F experimental PA. The PA in the general supply-modulated transmitter needs to be designed to have high efficiency over a range of supply voltages. This means that no specific class of operation will be ap-

propriate, and the output impedance at the fundamental needs to be a tradeoff that optimizes power, low-voltage small-signal gain, midvoltage efficiency, and high peak power. As an illustration of the type of impedance tradeoff at the PA output, Fig. 7 shows load–pull contours at the bond-wire plane of a TriQuint Semiconductor TGF-2003-10 discrete device for an example high-efficiency PA design used in this work. In the final PA, the chip device is mounted on a 15-mil-thick gold-plated CuMo pedestal using an eutectic die attach with AuSn performs, and wire bonded to the microstrip circuit (30-mil RO4350B substrate) with eight 1.25-mil-diameter wire bonds. The matching circuits present fundamental impedances of at the bond-wire plane and extracted at the virtual drain of the device. The harmonic terminations at the virtual drain were designed for a class-F PA [27] at a midrange supply voltage of 28 V and given in Table III. The PA input matching is accomplished with ATC600F capacitors, while the output microstrip matching circuit has 0.27-dB insertion loss. The output supply circuit is designed for pulsed RF measurements to obtain the static nonlinear characteristics, as described in Fig. 3. A photograph of the PA is shown in Fig. 8, along with measured and simulated fundamental, second, and third harmonic impedances listed in Table III. The PA gives 36-W pulsed power with 81% drain efficiency and 14.5-dB gain (78% PAE) for a 28-V drain bias at 2.14 GHz. The PA is characterized following the method described in Section II and the output results are shown in Fig. 9. The trajectory is chosen to trade off PA efficiency and linearity, taking into account supply modulator voltage range. The corresponding drive variation is plotted for completeness.

HOVERSTEN et al.: CODESIGN OF PA, SUPPLY, AND SIGNAL PROCESSING FOR LINEAR SUPPLY-MODULATED RF TRANSMITTERS

Fig. 8. Photograph of a high-efficiency PA implemented using the TGF-2003-10 discrete device and the load–pull data from Fig. 7 with second and third harmonic terminations [27].

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Fig. 10. Block diagram (left) of the supply modulator used for characterization, and photograph (right) of the linear amplifier. Gain peaking is applied to extend V for both the linear amplifier and the bandwidth beyond 70 MHz. varying from 3 to 32 V. switcher stage with the

dual-row 2.54-mm header connector was used with the top row connected to the modulator output and the bottom row to the ground plane, as shown in Fig. 10. A. Sources of Distortion

Fig. 9. Measured and versus with contours of measured PAE shown in color (in online version). The trajectory chosen for further demonstration is shown via the black solid line.

With the trajectory chosen and expected static performance known, dynamic effects can now be addressed. A linear supply modulator is next implemented as shown in Fig. 10 to finalize obtaining specification parameters for the final supply modulator. Similar to the configuration described in [28], the supply modulator is a parallel combination of a wide-bandwidth high slew-rate linear amplifier and a standard synchronous buck switcher that supplies a dc output current that results in the maximum efficiency for a given envelope signal [29]. Designed for laboratory testing purposes, this supply modulator does not have final-solution efficiency or form factor, but it does enable system characterization experiments. The linear amplifier stage consists of three voltage-gain stages followed by a buffer consisting of 48 LM7372 op-amps in parallel, to obtain up to 7-A 30-V output capabilities with over 100-MHz bandwidth and 3000-V s slew rate. The range is 3–32 V with a supply rail ( ) of 36 V for the linear amplifier and switcher stage. Particular attention was given to op-amp frequency compensation, printed circuit board (PCB) layout, and dc supply decoupling to achieve stable wide-bandwidth operation and current sharing among buffer op-amps. To minimize the inductance and retain high signal bandwidth between the supply modulator and the PA, a 76.2-mm-wide

In the block diagram of Fig. 2, there are a number of distortion mechanisms, which can, in principle, be corrected by complex digital predistortion (DPD). However, if the sources of distortion are identified and addressed one at a time using the simplest solution, the complexity of the final DPD can be dramatically reduced. We consider four distinct mechanisms of distortion. • Supply modulator gain and phase distortion, due to the frequency response of the supply modulator path. This linear time-varying mechanism can be corrected with a linear equalizer (digital filter). • RFPA gain variation with . This nonlinear time-invariant distortion can be corrected with standard AM–AM and AM–PM methods using LUT data. • Path delay difference between the and paths in Fig. 2 occurs when both and are changing over time, which can be corrected by adding delay in the path. • Remaining nonlinear time-varying distortion, such as dynamic memory effects in the PA, are corrected with polynomial-based DPD after all other simpler corrections have been made. In this approach, the order of operations is important: if the path is not equalized first, the linear time-varying distortion of the supply modulator will become nonlinear timevarying distortion at the RFPA output, resulting in much more difficult required linearization. Section IV-B provides experimental results of this targeted linearization method. B. Gain of Supply Modulator The signal path may have several analog components that have amplitude and phase response with frequency. The measured response for the supply modulator shown in Fig. 10 is shown via the red line (in online version) in Fig. 11(b). After applying digital filtering, the corrected gain and delay frequency

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Fig. 12. Measured PA AM–AM and AM–PM correction through static adaptation. The red line (in online version) is the extracted trend of the measured data points.

Fig. 11. (a) Block diagram showing method to measure the broadband gain and delay characteristics of the supply modulator path using a repeated chirp (frequency-modulated) excitation and “demodulating” to obtain I and Q components. There is a tradeoff between the resolvable supply modulator frequency response, length of the chirp, lower and upper chirp frequency, and the resolution of the capture instrument (oscilloscope). (b) Measured gain and delay response of the linear supply modulator from Fig. 10 before and after the correction.

dependence are flat to 70 MHz. Since without knowing the properties of the particular signal that is amplified, there is no benchmark for how much bandwidth the modulator needs to have, the measurements are in far excess of the supply modulator bandwidth and RF bandwidth. The correction is not expected to change over operating conditions. The frequency response is measured by driving the path with a logarithmic chirp from 1 to 110 MHz every 4 ms. The resulting signal is multiplied by the original signal shifted by 90° and low-pass filtered. Equivalently, the process could be thought of “modulating” the signal (chirp) and “mixing” the resulting signal with the original chirp [see Fig. 11(a)]. This results in an in-phase (I) and quadrature (Q) component of gain over frequency. The adjusted gain and delay correct the time-varying linear response so that the distortion introduced by the supply modulator does not go through the nonlinear distortion of the RFPA. This simple equalization is the initial step taken to reduce spectrum regrowth. C. PA Gain Linearization Measured PA gain and insertion phase vary with through the path. For example, for low expected output power, an increase of input power will be needed because of lower gain with smaller . The PA has a complex expected gain . The signal split ( ) adjusts for the expected gain to make the system linear. This procedure cannot be done using the same method as in Section IV-B because the PA has a nonlinear response and depends on the operating

conditions. Instead, the PA is “corrected” by implementing a closed-loop adaptation ( in Fig. 2). The initial starting point for the coefficient is for all (linear transmitter) and has “converged” when the difference between two consecutive iterations is negligible. Fig. 12 shows the extracted trend from the variation in the magnitude and phase of the RFPA gain parameter. This type of PA data is presented in many of the publications on this topic, e.g., [21] and [30]. This step of the targeted linearization iteratively corrects for AM–AM and AM–PM static PA nonlinearities. D. Path Delay Correction The relative delay between the supply modulator and PA paths is due to the fact that both the supply voltage and input RF voltage are changing. The and signal paths must be aligned in time at the PA, otherwise some distortion will be incurred at the output. There is no distortion when is low because then (see Table II for values of corresponding to different trajectories). Delay distortion is much more apparent when there are large changes in amplitude, as this causes the greatest amount of amplitude error for small differences in time (Fig. 13). This behavior causes amplitude/phase correlation methods to fail. Though there are several options to correct for path delay, Fig. 14 shows the results of a simple brute-force approach of measuring the adjacent channel power (ACP) at a certain frequency offset, and setting the additional delay at a value that produces the minimum ACP. E. DPD for Final Correction Digital pre-distortion is the last implemented targeted linearization step. It aims to create a digital “inverse” of the PA distortion [31]. In contrast to the previous sections, which implemented adaptive static or linear time-invariant pre-distortion, digital pre-distortion here refers to polynomial-based techniques, which aim to correct dynamic linear and nonlinear distortion of the transmitter system. Polynomial-based

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Fig. 13. Illustration of signal path delay causing gain error. Steeper slopes correspond to a greater gain error because of the larger difference (at that instant of time) between the expected signal and actual signal.

Fig. 15. Normalized measured spectrum of the supply-modulated transmitter amplifying a W-CDMA signal at 2.14 GHz at various stages of the targeted linearization process.

TABLE IV MEASURED TX PERFORMANCE FOR TWO TRAJECTORIES

Fig. 14. Measured ACP at two offsets (5 and 10 MHz) as a function of signal and paths gives the delay needed path delay difference between the to minimize distortion due to time misalignment.

techniques use weighted basis functions to account for static nonlinearity ( ), linear frequency response ( ), and dynamic nonlinearity ( ). The series terms should be chosen carefully to avoid creating unnecessary computational complexity or over-fitting the system. Two examples of expansion sets are memory polynomial [32] and dynamic deviation reduction (DDR) [33]. The DDR DPD routine has three complexity control parameters. is the order of nonlinearity, and only odd orders are used here. is the maximum memory depth in number of samples, implying that the sample rate is relevant. For our case, the sample rate was 1/2 of the signal sample rate, around 100 MHz. The final control parameter is order of the dynamics, where is completely static, and as increases, the DPD approaches the full Volterra model. For PAs that have a minimum , the designer can make use of piecewise Volterra series, as in [34]. The different modes of operation of the PA can be modeled separately and have different expansion functions to account for different types of dynamic distortion. The first mode is the linear region ( ) and the second is saturation ( ). For the measured spectrum shown in Fig. 15, the “two-level” DPD refers to two predistorters. One operates at low amplitude regions ( 14 V drain voltage) and the other at high amplitude

regions ( 14 V) with and , respectively. The DPD is implemented only after the other targeted linearizations have been applied and the complexity is minimized. If DPD were to be performed first, a significant number of additional terms would be needed to achieve the same linearity. F. Measured Transmitter Results The final measured results are summarized in Fig. 15 and Table IV. In the measured spectrum, several stages of targeted linearization are shown. The “initial” spectrum includes only supply modulator frequency response equalization, and includes an a priori estimated delay mismatch likely less than 1 ns from optimal. The spectrum labeled “initial signal split and time alignment” shows the result after the first iteration to correct the static AM/AM and AM/PM of the PA through a LUT, as well as the delay correction for minimal ACP. The final signal split result is shown after the sixth iteration. The “two-level DDR DPD” is the resulting spectrum after four iterations on the DPD coefficients. Note that iterations are not unusual in commercial DPD implementations, and some of the iterating and fine tuning can be done while the transmitter is active. Table IV compares two trajectories on the same PA from Fig. 8 and a custom-designed supply modulator [11]: drive modulation (A in Fig. 1) with set to 32 V and the trajectory in

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Fig. 9 with peak reaching 32 V. Note that the supply-modulated trajectory results in a measured composite average transmitter PAE of 52.5% with 8-W average output power for a 7-dB PAR signal with 23-MHz supply modulator bandwidth. The linearity is met for W-CDMA downlink signals, with an error vector magnitude (EVM) below 1%. To meet linearity, in this case, the PA average drain efficiency was 75.9% compared to 30% for the drive modulated case. The efficiency measurements for the supply-modulated transmitter are not straightforward since they include measurements of both supply modulator and PA efficiencies. Briefly, first the system efficiency is calculated as the PA output power, , divided by the supply modulator input power. is measured by an average power meter with a low-impedance supply modulator-PA interconnect (Section IV). The second step is to replace the low-impedance interconnect by a current probe, which degrades linearity, but the system efficiency remains nearly unchanged. The final step is to find the component efficiencies using the instantaneous voltage and current output of the supply modulator captured by an oscilloscope. We believe these reflect the actual component efficiencies, provided that their product is very nearly equal to the system efficiency. An interesting conclusion from the results in Table IV can be drawn by observing the dissipated heat for the two trajectories. When the optimized trajectory is compared to the flat trajectory (A), which corresponds to drive modulation, operating from a battery the supply-modulated transmitter would last 75% longer, and in a fixed installation consume 43% less power. PA dissipation is reduced from 19.8 W to only 2.7 W, reducing the cooling requirements. In the supply-modulated transmitter, 61% less heat is produced, and more importantly, the transistor in the PA operates with 86% less heat. The power dissipation is reduced, but also spread between the PA and supply modulator, reducing further heat sinking requirements and thermal device stress. V. DISCUSSION The general supply-modulated transmitter architecture from Fig. 2 introduces considerable complexity in order to improve overall efficiency. An efficient dynamic supply is added to an efficient RFPA, and the supply introduces additional distortion. This paper shows how to characterize the PA in order to determine supply requirements, and then how to correct distortion using a simple targeted linearization process. The implementation details of all the steps described here depend on the signal characteristics, in particular on the signal envelope bandwidth, rather than the signal I and Q component bandwidth. For example, a Gaussian multiple shift keyed (GMSK) signal with 4-MHz double-sided complex modulation bandwidth has a constant amplitude, with 0-Hz envelope bandwidth. In this case, no supply modulator would be required ( ). Consider next the spectrum of a four-tone 4-MHz bandwidth [orthogonal frequency division multiplexing (OFDM)] signal shown in Fig. 16. Though the I and Q components are band-limited to 4 MHz, the amplitude of the signal has frequency components extending far beyond 20 MHz. In this case, the supply modulator bandwidth choice will determine the amount of distortion that has to be dealt with [22]. The signal split needs to be chosen to minimize distortion while maintaining high efficiency.

Fig. 16. Simulated four-tone spectrum showing the I, Q, and amplitude components of a signal. While the I and Q are well within a 5-MHz bandwidth, the amplitude (and therefore, the supply modulator) bandwidth has frequency components well beyond 20 MHz of the signal.

Increased instantaneous transmission bandwidth presents a challenge to the supply-modulated transmitter technique, placing more demands on supply modulator bandwidth, PA-supply modulator interconnect, and signal timing accuracy. As discussed previously, the linearity degradation can be reduced by selecting a less aggressive signal split in exchange for PA efficiency. A second option is to design the supply modulator, interconnect, and timing alignment mechanisms to meet the more stringent linearity requirements, thus degrading system efficiency via supply modulator or digital power dissipation. codesign of the transmitter system allows for the best tradeoff of PA, supply modulator, and digital power consumption for highest overall system efficiency. In the general supply-modulated system from Fig. 2, the average transmitter efficiency (1) strongly depends on the efficiency of the supply modulator, which, in turn, depends on the required supply modulator bandwidth and slew-rate requirements. A combination of a high-performance linear amplifier and a standard switched-mode power converter, as shown in Fig. 10, can serve laboratory testing and characterization purposes for a range of signals, and for various polar split designs, but at the expense of reduced efficiency. To reach high-efficiency targets for the transmitter system, it is essential to consider techniques to improve dynamic response capabilities of a high-efficiency switcher in the supply modulator. For example, an optimum signal split between the linear amplifier and the switcher has been considered in [35]. Multilevel switcher configurations have been investigated in [36] and [37]. An approach based on high-bandwidth multiphase concept [38] and soft-switching techniques [39] has recently demonstrated a switched-mode supply with 10-MHz large-signal tracking bandwidth, more than 200-V s slew-rate capability, together with efficiency exceeding 90% [40]. Design, implementation, and integration of such more advanced supply modulators in vector-split polar transmitters remains an area of active research. In summary, the general supply-modulated transmitter from Fig. 2 has a digitally reconfigured signal split, which enables any trajectory from Fig. 1, or even a combination of trajectories that varies in time. Although specific versions of this approach

HOVERSTEN et al.: CODESIGN OF PA, SUPPLY, AND SIGNAL PROCESSING FOR LINEAR SUPPLY-MODULATED RF TRANSMITTERS

have been demonstrated in the literature with excellent results, to the best of our knowledge, a general approach to PA characterization, supply modulator requirement determination, and targeted distortion correction is for the first time presented. The spectrum in Fig. 15 and the experimental results in Table IV validate the approach on an example W-CDMA 40-W peak-power 2.14-GHz GaN PA with a 69.1% efficient supply modulator. The supply modulated transmitter composite PAE is measured to be 52.5% with 61.0% less heat produced than in the drive modulated linear amplifier. It is further shown that the heat dissipation is distributed between the system components reducing thermal stress on the RF transistor. ACKNOWLEDGMENT The authors are grateful to TriQuint Semiconductor, Richardson, TX, for generous device donations and help with packaging, and to R. Woolf , Texas Instruments Incorporated, Longmont, CO, for many useful discussions. REFERENCES [1] F. Raab, P. Asbeck, S. Cripps, P. Kenington, Z. Popović, N. Pothecary, J. Sevic, and N. Sokal, “Power amplifiers and transmitters for RF and microwave,” IEEE Trans. Microw. Theory Tech., vol. 50, no. 3, pp. 814–826, Mar. 2002. [2] P. A. X. Zhang and L. E. Larson, Design of Linear RF Outphasing Power Amplifiers. Norwood, MA: Artech House, 2003. [3] M. P. van der Heijden, M. Acar, J. S. Vromans, and D. A. Calvillo-Cortes, “A 19 W high-efficiency wideband CMOS-GaN class-E Chireix RF outphasing power amplifier,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2011, pp. 1–4. [4] B. Kim, J. Kim, I. Kim, and J. Cha, “The Doherty power amplifier,” IEEE Microw. Mag., vol. 7, no. 5, pp. 42–50, Oct. 2006. [5] M. Pelk, W. Neo, J. Gajadharsing, R. Pengelly, and L. de Vreede, “A high-efficiency 100-W GaN three-way Doherty amplifier for base-station applications,” IEEE Trans. Microw. Theory Tech., vol. 56, no. 7, pp. 1582–1591, Jul. 2008. [6] C. Burns, A. Chang, and D. Runton, “A 900 MHz, 500 W Doherty power amplifier using optimized output matched Si LDMOS power transistors,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2007, pp. 1577–1580. [7] D. Kimball, J. Jeong, C. Hsia, P. Draxler, S. Lanfranco, W. Nagy, K. Linthicum, L. Larson, and P. Asbeck, “High-efficiency envelopetracking W-CDMA base-station amplifier using GaN HFETs,” IEEE Trans. Microw. Theory Tech., vol. 54, no. 11, pp. 3848–3856, Nov. 2006. [8] F. Raab, “High-efficiency linear amplification by dynamic load modulation,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2003, vol. 3, pp. 1717–1720. [9] F. Lepine, R. Jos, and H. Zirath, “A load modulated high efficiency power amplifier,” in 36th Eur. Microw. Conf., Sep. 2006, pp. 411–414. [10] L. Kahn, “Single-sideband transmission by envelope elimination and restoration,” Proc. IRE, vol. 40, no. 7, pp. 803–806, Jul. 1952. [11] J. Hoversten and Z. Popović, “System considerations for efficient and linear supply modulated RF transmitters,” in IEEE 12th Contr. and Modeling for Power Electron. Workshop, Jun. 2010, pp. 1–8. [12] F. Raab, B. Sigmon, R. Myers, and R. Jackson, “ -band transmitter using Kahn EER technique,” IEEE Trans. Microw. Theory Tech., vol. 46, no. 12, pp. 2220–2225, Dec. 1998. [13] F. Raab, “Drive modulation in Kahn-technique transmitters,” in IEEE MTT-S Int. Microw. Symp. Dig., 1999, vol. 2, pp. 811–814. [14] M. Weiss, F. Raab, and Z. Popović, “Linearity of -band class-F power amplifiers in high-efficiency transmitters,” IEEE Trans. Microw. Theory Tech., vol. 49, no. 6, pp. 1174–1179, Jun. 2001. [15] N. Wang, V. Yousefzadeh, D. Maksimović, S. Pajic, and Z. Popović, “60% efficient 10-GHz power amplifier with dynamic drain bias control,” IEEE Trans. Microw. Theory Tech., vol. 52, no. 3, pp. 1077–1081, Mar. 2004.

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[16] F. Wang, A. Yang, D. Kimball, L. Larson, and P. Asbeck, “Design of wide-bandwidth envelope-tracking power amplifiers for OFDM applications,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 4, pp. 1244–1255, Apr. 2005. [17] H. Nemati, C. Fager, U. Gustavsson, R. Jos, and H. Zirath, “Characterization of switched mode LDMOS and GaN power amplifiers for optimal use in polar transmitter architectures,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2008, pp. 1505–1508. [18] N. Lopez, X. Jiang, D. Maksimović, and Z. Popović, “A high-efficiency linear polar transmitter for EDGE,” in IEEE Radio Wireless Symp., Jan. 2008, pp. 199–202. [19] C.-J. Li, C.-T. Chen, T.-S. Horng, J.-K. Jau, and J.-Y Li, “High averageefficiency multimode RF transmitter using a hybrid quadrature polar modulator,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 55, no. 3, pp. 249–253, Mar. 2008. [20] I. Kim, J. Kim, J. Moon, and B. Kim, “Optimized envelope shaping for hybrid EER transmitter of mobile WiMAX—Optimized ET operation,” IEEE Microw. Wireless Compon. Lett., vol. 19, no. 5, pp. 335–337, May 2009. [21] J. Jeong, D. Kimball, M. Kwak, P. Draxler, C. Hsia, C. Steinbeiser, T. Landon, O. Krutko, L. Larson, and P. Asbeck, “High-efficiency WCDMA envelope tracking base-station amplifier implemented with GaAs HVHBTs,” IEEE J. Solid-State Circuits, vol. 44, no. 10, pp. 2629–2639, Oct. 2009. [22] J. Hoversten and Z. Popović, “Envelope tracking transmitter system analysis method,” in IEEE Radio Wireless Symp., Jan. 2010, pp. 180–183. [23] M. Mercanti, A. Cidronali, S. Maurri, and G. Manes, “HEMT GaAs/GaN power amplifiers architecture with discrete dynamic voltage bias control in envelope tracking RF transmitter for W-CDMA signals,” in IEEE Power Amp. Wireless Radio Appl. Top. Conf., Jan. 2011, pp. 9–12. [24] M. Weiss, F. Raab, and Z. Popović, “Linearity of -band class-F power amplifiers in high-efficiency transmitters,” IEEE Trans. Microw. Theory Tech., vol. 49, no. 6, pp. 1174–1179, Jun. 2001. [25] J. H. Kim, G. D. Jo, J. H. Oh, Y. H. Kim, K. C. Lee, J. H. Jung, and C. S. Park, “High-efficiency envelope-tracking transmitter with optimized class-F amplifier and 2-bit envelope amplifier for 3G LTE base station,” IEEE Trans. Microw. Theory Tech., vol. 59, no. 6, pp. 1610–1621, Jun. 2011. [26] P. Gray, P. Hurst, S. Lewis, and R. Meyer, Analysis and Design of Analog Integrated Circuits. New York: Wiley, 2009. [Online]. Available: http://books.google.com/books?id=VBB4QAAACAAJ [27] J. Hoversten, M. Roberg, and Z. Popović, “Harmonic load pull of highpower microwave devices using fundamental-only load pull tuners,” in 75th ARFTG Microw. Meas. Conf., May 2010, pp. 1–4. [28] N. Wang, X. Peng, V. Yousefzadeh, D. Maksimović, S. Pajic, and Z. Popović, “Linearity of -band class-E power amplifiers in EER operation,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 3, pp. 1096–1102, Mar. 2005. [29] J. Stauth and S. Sanders, “Optimum biasing for parallel hybrid switching-linear regulators,” IEEE Trans. Power Electron., vol. 22, no. 5, pp. 1978–1985, Sep. 2007. [30] P. Draxler, S. Lanfranco, D. Kimball, C. Hsia, J. Jeong, J. van de Sluis, and P. Asbeck, “High efficiency envelope tracking LDMOS power amplifier for W-CDMA,” in IEEE MTT-S Int. Microw. Symp. Dig. , Jun. 2006, pp. 1534–1537. [31] F. Ghannouchi and O. Hammi, “Behavioral modeling and predistortion,” IEEE Microw. Mag., vol. 10, no. 7, pp. 52–64, Dec. 2009. [32] D. Morgan, Z. Ma, J. Kim, M. Zierdt, and J. Pastalan, “A generalized memory polynomial model for digital predistortion of RF power amplifiers,” IEEE Trans. Signal Process., vol. 54, no. 10, pp. 3852–3860, Oct. 2006. [33] A. Zhu, P. Draxler, J. Yan, T. Brazil, D. Kimball, and P. Asbeck, “Open-loop digital predistorter for RF power amplifiers using dynamic deviation reduction-based Volterra series,” IEEE Trans. Microw. Theory Tech., vol. 56, no. 7, pp. 1524–1534, Jul. 2008. [34] A. Zhu, P. Draxler, C. Hsia, T. Brazil, D. Kimball, and P. Asbeck, “Digital predistortion for envelope-tracking power amplifiers using decomposed piecewise Volterra series,” IEEE Trans. Microw. Theory Tech., vol. 56, no. 10, pp. 2237–2247, Oct. 2008. [35] V. Yousefzadeh, E. Alarcon, and D. Maksimović, “Band separation and efficiency optimization in linear-assisted switching power amplifiers,” in 37th IEEE Power Electron. Specialists Conf., Jun. 2006, pp. 1–7. [36] M. Rodriguez, P. Miaja, A. Rodriguez, and J. Sebastian, “Multilevel converter for envelope tracking in RF power amplifiers,” in IEEE Energy Conversion Congr. and Expo., Sep. 2009, pp. 503–510.

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[37] M. Vasic, O. Garcia, J. Oliver, P. Alou, D. Diaz, and J. Cobos, “Multilevel power supply for high-efficiency RF amplifiers,” IEEE Trans. Power Electron., vol. 25, no. 4, pp. 1078–1089, Apr. 2010. [38] Y. Zhang, X. Zhang, R. Zane, and D. Maksimović, “Wide-bandwidth digital multi-phase controller,” in 37th IEEE Power Electron. Specialists Conf., Jun. 2006, pp. 1–7. [39] D. Maksimović, “Design of the zero-voltage-switching quasi-squarewave resonant switch,” in 24th Annu. IEEE Power Electron. Specialists Conf. Rec., Jun. 1993, pp. 323–329. [40] M. Norris and D. Maksimović, “10 MHz large signal bandwidth, 95% efficient power supply for 3G–4G cell phone base stations,” in Proc. IEEE Appl. Power Electron. Conf. Expo., Feb. 5–9, 2012, pp. 7–13.

John Hoversten (S’03–M’11) received the B.S. degree from Embry-Riddle Aeronautical University, Prescott, AZ, in 2005, and the M.S. and Ph.D. degrees from the University of Colorado at Boulder, in 2008 and 2010, all in electrical engineering. His graduate research concerned the area of high-efficiency RF power amplification with a focus on harmonic-tuned PA design and ET techniques. Since 2008, he has been involved in research efforts centered around RF front end efficiency enhancement with Texas Instruments Incorporated (formerly National Semiconductor). He is currently an RF/system Design Engineer with Silicon Valley Laboratories, Texas Instruments Incorporated, Longmont, CO.

Scott Schafer (S’10) received the B.S. degree in engineering physics from the Colorado School of Mines, Golden, in 2010, and is currently working toward the Ph.D. degree at the University of Colorado at Boulder. His research has included millimeter-wave near-field probing. His current research interests include GaN monolithic microwave integrated circuit (MMIC) microwave PA design and high-efficiency linear transmitters.

Michael Roberg (S’09) received the B.S. degree in electrical engineering from Bucknell University, Lewisburg, PA, in 2003, the M.S.E.E. degree from the University of Pennsylvania, Philadelphia, in 2006, and is currently working toward the Ph.D. degree at the University of Colorado at Boulder. From 2003 to 2009, he was an Engineer with Lockheed Martin–MS2, Moorestown, NJ, where he was involved with advanced phased-array radar systems. His current research interests include microwave PA theory and design and high-efficiency radar and communication system transmitters.

Mark Norris (S’08) received the B.S. degree in electrical and computer engineering and Ph.D. degree in multiphases tracking power supplies from the University of Colorado at Boulder, in 1989 and 2012, respectively. For four years, he designed gas chromatography equipment for Base Line Industries. He spent the next two years implanting power supplies for sputtering equipment up to 30 kW. From 1995 to 2005, he was Lead Electrical Engineer for pulse oximetry with Ohmeda–Datex Ohmeda–GE, where he successfully applied multiplexing techniques from communications to enhance the cost and performance of pulse oximeters. He is currently with Texas Instruments Incorporated, Longmont, CO, where he designs integrated circuits (ICs) for mobile power applications. He holds 19 patents. His research has focused on efficiently extending the large-signal bandwidth of multiphase switch-mode power supplies beyond 20 MHz for use in EER of RF transmitters in LTE cell-phone base stations.

Dragan Maksimović received the B.S. and M.S. degrees in electrical engineering from the University of Belgrade, Belgrade, Yugoslavia, in 1984 and 1986, respectively, and the Ph.D. degree from the California Institute of Technology, Pasadena, in 1989. From 1989 to 1992, he was with the University of Belgrade. Since 1992, he has been with the Department of Electrical, Computer and Energy Engineering, University of Colorado at Boulder, where he is currently a Professor and Director of the Colorado Power Electronics Center (CoPEC). His current research interests include mixed-signal integrated-circuit design for control of power electronics and digital control techniques, as well as energy efficiency and renewable energy applications of power electronics. Prof. Maksimovic was the recipient of the 1997 National Science Foundation (NSF) CAREER Award, the 1997 IEEE Power Electronics Society Transactions Prize Paper Award, the 2009 and 2010 IEEE Power Electronics Society Prize Letter Awards, the 2004 and 2011 Holland Excellence in Teaching Awards, and the 2006 University of Colorado Inventor of the Year Award.

Zoya Popović (S’86–M’90–M’99–F’02) received the Dipl.Ing. degree from the University of Belgrade, Belgrade, Serbia, Yugoslavia, in 1985, and the Ph.D. degree from the California Institute of Technology, Pasadena, in 1990. Since 1990, she has been with the University of Colorado at Boulder, where she is currently a Distinguished Professor and holds the Hudson Moore Jr. Chair with the Department of Electrical, Computer and Energy Engineering. In 2001, she was a Visiting Professor with the Technical University of Munich, Munich, Germany. Since 1991, she has graduated 44 Ph.D. students. Her research interests include high-efficiency, low-noise, and broadband microwave and millimeter-wave circuits, quasi-optical millimeter-wave techniques, active antenna arrays, and wireless powering for batteryless sensors. Prof. Popović was the recipient of the 1993 and 2006 Microwave Prizes presented by the IEEE Microwave Theory and Techniques Society (IEEE MTT-S) for the best journal papers and the 1996 URSI Issac Koga Gold Medal. In 1997, Eta Kappa Nu students chose her as a Professor of the Year. She was the recipient of a 2000 Humboldt Research Award for Senior U.S. Scientists of the German Alexander von Humboldt Stiftung. She was elected a Foreign Member of the Serbian Academy of Sciences and Arts in 2006. She was also the recipient of the 2001 Hewlett-Packard (HP)/American Society for Engineering Education (ASEE) Terman Medal for combined teaching and research excellence.

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EDITORIAL BOARD Editor-in-Chief: GEORGE E. PONCHAK Associate Editors: H. ZIRATH, W. VAN MOER, J.-S. RIEH, Q. XUE, L. ZHU, K. J. CHEN, M. YU, C.-W. TANG, J. PAPAPOLYMEROU, N. S. BARKER, C. D. SARRIS, C. FUMEAUX, D. HEO, B. BAKKALOGLU The following members reviewed papers during 2011

P. Aaen A. Abbaspour-Tamijani A. Abbosh D. Abbott A. Abdipour M. Abe M. Abegaonkar R. Abhari A. Abramowicz M. Acar L. Accatino R. Achar E. Ackerman J. Adam K. Agawa M. Ahmad H.-R. Ahn B. Ai M. Aikawa J. Aikio C. Aitchison M. Akaike T. Akin S. Aksoy I. Aksun A. Akyurtlu G. Ala L. Albasha A. Alexanian W. Ali-Ahmad F. Alimenti R. Allam K. Allen A. Alphones A. Alu A. Álvarez-Melcon A. Al-Zayed S. Amari H. Amasuga R. Amaya H. An D. Anagnostou M. Andersen K. Andersson M. Ando Y. Ando P. Andreani M. Andrés W. Andress K. Ang C. Angell I. Angelov Y. Antar G. Antonini H. Aoki V. Aparin F. Apollonio R. Araneo J. Archer F. Ares F. Ariaei T. Arima M. Armendariz L. Arnaut F. Arndt E. Artal H. Arthaber F. Aryanfar U. Arz M. Asai Y. Asano A. Asensio-Lopez K. Ashby H. Ashoka A. Atalar A. Atia S. Auster I. Awai A. Aydiner M. Ayza K. Azadet R. Azaro A. Babakhani P. Baccarelli M. Baginski I. Bahl S. Bajpai J. Baker-Jarvis B. Bakkaloglu M. Bakr A. Baladin C. Balanis S. Balasubramaniam J. Balbastre J. Ball P. Balsara Q. Balzano A. Banai S. Banba R. Bansal D. Barataud A. Barbosa F. Bardati I. Bardi J. Bardin A. Barel S. Barker F. Barnes J. Barr G. Bartolucci R. Bashirullan S. Bastioli A. Basu B. Bates R. Baxley Y. Bayram J.-B. Bégueret N. Behdad F. Belgacem H. Bell D. Belot J. Benedikt T. Berceli C. Berland M. Berroth G. Bertin E. Bertran A. Bessemoulin M. Beurden A. Bevilacqua A. Beyer M. Bialkowski

E. Biebl P. Bienstman S. Bila D. Blackham R. Blaikie M. Blank P. Blockley P. Blondy P. Blount D. Boccoli G. Boeck L. Boglione R. Boix G. Bonaguide F. Bonani G. Bonmassar O. Boos B. Borges V. Boria-Esbert O. Boric-Lubecke A. Borji S. Borm J. Bornemann W. Bosch R. Bosisio H. Boss G. Botta N. Boulejfen S. Boumaiza J. Bouny C. Boyd C. Bozler M. Bozzi R. Bradley D. Braess N. Braithwaite M. Brandolini G. Branner T. Brazil J. Breitbarth M. Bressan K. Breuer B. Bridges D. Bridges J. Brinkhoff E. Brown S. Brozovich E. Bryerton D. Budimir G. Burdge P. Burghignoli N. Buris C. C. Galup-Montoro B. Cabon P. Cabral L. Cabria C. Caloz C. Camacho-Peñalosa V. Camarchia E. Camargo R. Cameron M. Camiade C. Campbell M. Campovecchio F. Canavero A. Cangellaris A. Cantoni C. Cao F. Capolino F. Cappelluti G. Carchon J. Carmo K. Carr F. Carrez R. Carrillo-Ramirez P. Carro R. Carter N. Carvalho P. Casas R. Castello J. Catala M. Cavagnaro R. Caverly D. Cavigia J. Cazaux M. Celuch Z. Cendes D. Chadha M. Chae S. Chakraborty C. Chan C. Chang H. Chang K. Chang S. Chang T. Chang W. Chang E. Channabasappa H. Chapell W. Chappell C. Charles M. Chatras I. Chatterjee G. Chattopadhyay S. Chaudhuri S. Chebolu A. Cheldavi A. Chen C. Chen H. Chen J. Chen K. Chen M. Chen N. Chen S. Chen Y. Chen Z. Chen Z.-N. Chen H. Cheng K. Cheng M. Cheng Y. Cheng C. Cheon C. Chi M. Chia Y. Chiang J. Chiao A. Chin K. Chin H. Chiou Y. Chiou C. Chiu

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Digital Object Identifier 10.1109/TMTT.2012.2201280

S. Islam M. Ito K. Itoh T. Itoh Y. Itoh A. Ittipiboon F. Ivanek D. Iverson M. Iwamoto D. Jablonski D. Jachowski C. Jackson D. Jackson R. Jackson A. Jacob K. Jacobs S. Jacobsen D. Jaeger J. Jaeger S. Jagannathan N. Jain G. James M. Janezic S. Jang M. Jankovic D. Jansen L. Jansson H. Jantunen H. Jardon-Aguilar J. Jargon N. Jarosik B. Jarry P. Jarry A. Jastrzebski B. Jemison W. Jemison S. Jeng A. Jenkins S. Jeon D. Jeong J. Jeong Y. Jeong A. Jerng T. Jerse T. Jiang X. Jiang G. Jianjun D. Jiao J. Jin J. M. Jin J. Joe T. Johnson B. Jokanovic U. Jordan K. Joshin J. Joubert S. Jung T. Kaho S. Kanamaluru K. Kanaya S. Kang P. Kangaslahti B. Kapilevich I. Karanasiou M. Karim T. Kataoka A. Katz R. Kaul R. Kaunisto T. Kawai S. Kawasaki M. Kazimierczuk L. Kempel P. Kenington P. Kennedy A. Kerr D. Kettle A. Khalil W. Khalil S. Khang A. Khanifar A. Khanna R. Khazaka J. Khoja S. Kiaei J. Kiang B. Kim C. Kim D. Kim H. Kim I. Kim J. Kim S. Kim T. Kim W. Kim N. Kinayman R. King N. Kinzie S. Kirchoefer A. Kirilenko M. Kishihara T. Kitazawa J. Kitchen T. Klapwijk E. Klumperink D. Klymyshyn L. Knockaert R. Knoechel M. Koch K. Koh N. Kolias J. Komiak A. Komijani G. Kompa A. Konanur A. Konczykowska H. Kondoh B. Kopp B. Kormanyos J. Korvink P. Kosmas Y. Kotsuka S. Koziel A. Kozyrev V. Krishnamurthy H. Krishnaswamy C. Krowne J. Krupka D. Kryger H. Ku H. Kubo A. Kucar

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